/* ** ################################################################### ** Processors: MIMX9596AVTXN_ca55 ** MIMX9596AVZXN_ca55 ** MIMX9596DVTXQ_ca55 ** MIMX9596DVYXQ_ca55 ** MIMX9596DVZXQ_ca55 ** MIMX9596XVTXL_ca55 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** ** Reference manual: iMX95RM rev1 draftM ** Version: rev. 1.0, 2023-01-10 ** Build: b240402 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMX9596_ca55 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2024 NXP ** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2023-01-10) ** Initial version. ** ** ################################################################### */ /*! * @file MIMX9596_ca55.h * @version 1.0 * @date 2023-01-10 * @brief CMSIS Peripheral Access Layer for MIMX9596_ca55 * * CMSIS Peripheral Access Layer for MIMX9596_ca55 */ #if !defined(MIMX9596_CA55_H_) #define MIMX9596_CA55_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0000U /** Peripheral GIC Distributor base address */ #define GIC_DISTRIBUTOR_BASE (0x48000000u) /** Peripheral GIC Redistributor base address */ #define GIC_REDISTRIBUTOR_BASE (0x48060000u) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 408 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ Software0_IRQn = 0, /**< Cortex-A55 Software Generated Interrupt 0 */ Software1_IRQn = 1, /**< Cortex-A55 Software Generated Interrupt 1 */ Software2_IRQn = 2, /**< Cortex-A55 Software Generated Interrupt 2 */ Software3_IRQn = 3, /**< Cortex-A55 Software Generated Interrupt 3 */ Software4_IRQn = 4, /**< Cortex-A55 Software Generated Interrupt 4 */ Software5_IRQn = 5, /**< Cortex-A55 Software Generated Interrupt 5 */ Software6_IRQn = 6, /**< Cortex-A55 Software Generated Interrupt 6 */ Software7_IRQn = 7, /**< Cortex-A55 Software Generated Interrupt 7 */ Software8_IRQn = 8, /**< Cortex-A55 Software Generated Interrupt 8 */ Software9_IRQn = 9, /**< Cortex-A55 Software Generated Interrupt 9 */ Software10_IRQn = 10, /**< Cortex-A55 Software Generated Interrupt 10 */ Software11_IRQn = 11, /**< Cortex-A55 Software Generated Interrupt 11 */ Software12_IRQn = 12, /**< Cortex-A55 Software Generated Interrupt 12 */ Software13_IRQn = 13, /**< Cortex-A55 Software Generated Interrupt 13 */ Software14_IRQn = 14, /**< Cortex-A55 Software Generated Interrupt 14 */ Software15_IRQn = 15, /**< Cortex-A55 Software Generated Interrupt 15 */ VirtualMaintenance_IRQn = 25, /**< Cortex-A55 Virtual Maintenance Interrupt */ HypervisorTimer_IRQn = 26, /**< Cortex-A55 Hypervisor Timer Interrupt */ VirtualTimer_IRQn = 27, /**< Cortex-A55 Virtual Timer Interrupt */ LegacyFastInt_IRQn = 28, /**< Cortex-A55 Legacy nFIQ signal Interrupt */ SecurePhyTimer_IRQn = 29, /**< Cortex-A55 Secure Physical Timer Interrupt */ NonSecurePhyTimer_IRQn = 30, /**< Cortex-A55 Non-secure Physical Timer Interrupt */ LegacyIRQ_IRQn = 31, /**< Cortex-A55 Legacy nIRQ Interrupt */ /* Device specific interrupts */ Reserved32_IRQn = 32, /**< Reserved interrupt */ Reserved33_IRQn = 33, /**< DAP interrupt */ Reserved34_IRQn = 34, /**< CTI trigger outputs from CM7 platform */ Reserved35_IRQn = 35, /**< CTI trigger outputs from CM33 platform */ Reserved36_IRQn = 36, /**< CTI trigger outputs from CA55 platform */ Reserved37_IRQn = 37, /**< Performance Unit Interrupts from CA55 platform */ Reserved38_IRQn = 38, /**< ECC error from CA55 platform cache */ Reserved39_IRQn = 39, /**< 1-bit or 2-bit ECC or Parity error from CA55 platform cache */ CAN1_IRQn = 40, /**< CAN1 interrupt */ CAN1_ERROR_IRQn = 41, /**< CAN1 error interrupt */ Reserved42_IRQn = 42, /**< General Purpose Input/Output 1 interrupt 0 */ Reserved43_IRQn = 43, /**< General Purpose Input/Output 1 interrupt 1 */ I3C1_IRQn = 44, /**< Improved Inter-Integrated Circuit 1 interrupt */ LPI2C1_IRQn = 45, /**< Low Power Inter-Integrated Circuit module 1 */ LPI2C2_IRQn = 46, /**< Low Power Inter-Integrated Circuit module 2 */ LPIT1_IRQn = 47, /**< Low Power Periodic Interrupt Timer 1 */ LPSPI1_IRQn = 48, /**< Low Power Serial Peripheral Interface 1 */ LPSPI2_IRQn = 49, /**< Low Power Serial Peripheral Interface 2 */ LPTMR1_IRQn = 50, /**< Low Power Timer 1 */ LPUART1_IRQn = 51, /**< Low Power UART 1 */ LPUART2_IRQn = 52, /**< Low Power UART 2 */ Reserved53_IRQn = 53, /**< AONMIX Sentinel MU0 SideA interrupt */ Reserved54_IRQn = 54, /**< AONMIX Sentinel MU1 SideA interrupt */ Reserved55_IRQn = 55, /**< AONMIX Sentinel MU2 SideA interrupt */ Reserved56_IRQn = 56, /**< AONMIX Sentinel MU3 SideA interrupt */ Reserved57_IRQn = 57, /**< AONMIX Sentinel MU4 SideA interrupt */ Reserved58_IRQn = 58, /**< AONMIX Sentinel MU5 SideA interrupt */ V2X_FH_APCH0_IRQn = 59, /**< V2X-FH MU APCH0 (APP0) interrupt */ V2X_FH_APHSM1_IRQn = 60, /**< V2X-FH MU APHSM1 (HSM1) interrupt */ TPM1_IRQn = 61, /**< Timer PWM module 1 */ TPM2_IRQn = 62, /**< Timer PWM module 2 */ WDOG1_IRQn = 63, /**< Watchdog 1 Interrupt */ WDOG2_IRQn = 64, /**< Watchdog 2 Interrupt */ TRDC_MGR_A_IRQn = 65, /**< AONMIX TRDC transfer error interrupt */ SAI1_IRQn = 66, /**< Serial Audio Interface 1 */ Reserved67_IRQn = 67, /**< AONMIX M33 PS Error */ Reserved68_IRQn = 68, /**< AONMIX M33 TCM Error interrupt */ Reserved69_IRQn = 69, /**< M7MIX ECC Multi-bit error */ CAN2_IRQn = 70, /**< CAN2 interrupt */ CAN2_ERROR_IRQn = 71, /**< CAN2 error interrupt */ CAN3_IRQn = 72, /**< CAN3 interrupt */ CAN3_ERROR_IRQn = 73, /**< CAN3 error interrupt */ CAN4_IRQn = 74, /**< CAN4 interrupt */ CAN4_ERROR_IRQn = 75, /**< CAN4 error interrupt */ CAN5_IRQn = 76, /**< CAN5 interrupt */ CAN5_ERROR_IRQn = 77, /**< CAN5 error interrupt */ FLEXIO1_IRQn = 78, /**< Flexible IO 1 interrupt */ FLEXIO2_IRQn = 79, /**< Flexible IO 2 interrupt */ FlexSPI1_IRQn = 80, /**< FlexSPI controller interface interrupt 1 */ Reserved81_IRQn = 81, /**< General Purpose Input/Output 2 interrupt 0 */ Reserved82_IRQn = 82, /**< General Purpose Input/Output 2 interrupt 1 */ Reserved83_IRQn = 83, /**< General Purpose Input/Output 3 interrupt 0 */ Reserved84_IRQn = 84, /**< General Purpose Input/Output 3 interrupt 1 */ Reserved85_IRQn = 85, /**< General Purpose Input/Output 4 interrupt 0 */ Reserved86_IRQn = 86, /**< General Purpose Input/Output 4 interrupt 1 */ Reserved87_IRQn = 87, /**< General Purpose Input/Output 5 interrupt 0 */ Reserved88_IRQn = 88, /**< General Purpose Input/Output 5 interrupt 1 */ I3C2_IRQn = 89, /**< Improved Inter-Integrated Circuit 2 interrupt */ LPI2C3_IRQn = 90, /**< Low Power Inter-Integrated Circuit module 3 */ LPI2C4_IRQn = 91, /**< Low Power Inter-Integrated Circuit module 4 */ LPIT2_IRQn = 92, /**< Low Power Periodic Interrupt Timer 2 */ LPSPI3_IRQn = 93, /**< Low Power Serial Peripheral Interface 3 */ LPSPI4_IRQn = 94, /**< Low Power Serial Peripheral Interface 4 */ LPTMR2_IRQn = 95, /**< Low Power Timer 2 */ LPUART3_IRQn = 96, /**< Low Power UART 3 */ LPUART4_IRQn = 97, /**< Low Power UART 4 */ LPUART5_IRQn = 98, /**< Low Power UART 5 */ LPUART6_IRQn = 99, /**< Low Power UART 6 */ LPUART7_IRQn = 100, /**< Low Power UART 7 */ LPUART8_IRQn = 101, /**< Low Power UART 8 */ Reserved102_IRQn = 102, /**< MTR Master error interrupt */ Reserved103_IRQn = 103, /**< BBNSM Non-Secure interrupt */ Reserved104_IRQn = 104, /**< System Counter compare interrupt */ TPM3_IRQn = 105, /**< Timer PWM module 3 */ TPM4_IRQn = 106, /**< Timer PWM module 4 */ TPM5_IRQn = 107, /**< Timer PWM module 5 */ TPM6_IRQn = 108, /**< Timer PWM module 6 */ WDOG3_IRQn = 109, /**< Watchdog 3 Interrupt */ WDOG4_IRQn = 110, /**< Watchdog 4 Interrupt */ WDOG5_IRQn = 111, /**< Watchdog 5 Interrupt */ TMPSNS1_THR1_IRQn = 112, /**< ANAMIX TempSensor non-secure interrupt from Threshold 1 */ TMPSNS1_THR2_IRQn = 113, /**< ANAMIX TempSensor non-secure interrupt from Threshold 2 */ TMPSNS1_DRDY_IRQn = 114, /**< ANAMIX TempSensor non-secure data ready interrupt */ TMPSNS2_THR1_IRQn = 115, /**< CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */ TMPSNS2_THR2_IRQn = 116, /**< CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */ TMPSNS2_DRDY_IRQn = 117, /**< CORTEXAMIX TempSensor non-secure data ready interrupt */ uSDHC1_IRQn = 118, /**< ultra Secure Digital Host Controller interrupt 1 */ uSDHC2_IRQn = 119, /**< ultra Secure Digital Host Controller interrupt 2 */ Reserved120_IRQn = 120, /**< MEGAMIX TRDC transfer error interrupt */ Reserved121_IRQn = 121, /**< NIC_WRAPPER TRDC transfer error interrupt */ Reserved122_IRQn = 122, /**< NOCMIX TRDC transfer error interrupt */ Reserved123_IRQn = 123, /**< DRAM controller Performance Monitor Interrupt */ Reserved124_IRQn = 124, /**< DRAM controller Critical Interrupt */ Reserved125_IRQn = 125, /**< DRAM Phy Critical Interrupt */ Reserved126_IRQn = 126, /**< Reserved */ DMA3_ERROR_IRQn = 127, /**< eDMA1 error interrupt */ DMA3_0_IRQn = 128, /**< eDMA1 channel 0 interrupt */ DMA3_1_IRQn = 129, /**< eDMA1 channel 1 interrupt */ DMA3_2_IRQn = 130, /**< eDMA1 channel 2 interrupt */ DMA3_3_IRQn = 131, /**< eDMA1 channel 3 interrupt */ DMA3_4_IRQn = 132, /**< eDMA1 channel 4 interrupt */ DMA3_5_IRQn = 133, /**< eDMA1 channel 5 interrupt */ DMA3_6_IRQn = 134, /**< eDMA1 channel 6 interrupt */ DMA3_7_IRQn = 135, /**< eDMA1 channel 7 interrupt */ DMA3_8_IRQn = 136, /**< eDMA1 channel 8 interrupt */ DMA3_9_IRQn = 137, /**< eDMA1 channel 9 interrupt */ DMA3_10_IRQn = 138, /**< eDMA1 channel 10 interrupt */ DMA3_11_IRQn = 139, /**< eDMA1 channel 11 interrupt */ DMA3_12_IRQn = 140, /**< eDMA1 channel 12 interrupt */ DMA3_13_IRQn = 141, /**< eDMA1 channel 13 interrupt */ DMA3_14_IRQn = 142, /**< eDMA1 channel 14 interrupt */ DMA3_15_IRQn = 143, /**< eDMA1 channel 15 interrupt */ DMA3_16_IRQn = 144, /**< eDMA1 channel 16 interrupt */ DMA3_17_IRQn = 145, /**< eDMA1 channel 17 interrupt */ DMA3_18_IRQn = 146, /**< eDMA1 channel 18 interrupt */ DMA3_19_IRQn = 147, /**< eDMA1 channel 19 interrupt */ DMA3_20_IRQn = 148, /**< eDMA1 channel 20 interrupt */ DMA3_21_IRQn = 149, /**< eDMA1 channel 21 interrupt */ DMA3_22_IRQn = 150, /**< eDMA1 channel 22 interrupt */ DMA3_23_IRQn = 151, /**< eDMA1 channel 23 interrupt */ DMA3_24_IRQn = 152, /**< eDMA1 channel 24 interrupt */ DMA3_25_IRQn = 153, /**< eDMA1 channel 25 interrupt */ DMA3_26_IRQn = 154, /**< eDMA1 channel 26 interrupt */ DMA3_27_IRQn = 155, /**< eDMA1 channel 27 interrupt */ DMA3_28_IRQn = 156, /**< eDMA1 channel 28 interrupt */ DMA3_29_IRQn = 157, /**< eDMA1 channel 29 interrupt */ DMA3_30_IRQn = 158, /**< eDMA1 channel 30 interrupt */ DMA5_2_ERROR_IRQn = 159, /**< eDMA2 error interrupt */ DMA5_2_0_1_IRQn = 160, /**< eDMA2 channel 0/1 interrupt */ DMA5_2_2_3_IRQn = 161, /**< eDMA2 channel 2/3 interrupt */ DMA5_2_4_5_IRQn = 162, /**< eDMA2 channel 4/5 interrupt */ DMA5_2_6_7_IRQn = 163, /**< eDMA2 channel 6/7 interrupt */ DMA5_2_8_9_IRQn = 164, /**< eDMA2 channel 8/9 interrupt */ DMA5_2_10_11_IRQn = 165, /**< eDMA2 channel 10/11 interrupt */ DMA5_2_12_13_IRQn = 166, /**< eDMA2 channel 12/13 interrupt */ DMA5_2_14_15_IRQn = 167, /**< eDMA2 channel 14/15 interrupt */ DMA5_2_16_17_IRQn = 168, /**< eDMA2 channel 16/17 interrupt */ DMA5_2_18_19_IRQn = 169, /**< eDMA2 channel 18/19 interrupt */ DMA5_2_20_21_IRQn = 170, /**< eDMA2 channel 20/21 interrupt */ DMA5_2_22_23_IRQn = 171, /**< eDMA2 channel 22/23 interrupt */ DMA5_2_24_25_IRQn = 172, /**< eDMA2 channel 24/25 interrupt */ DMA5_2_26_27_IRQn = 173, /**< eDMA2 channel 26/27 interrupt */ DMA5_2_28_29_IRQn = 174, /**< eDMA2 channel 28/29 interrupt */ DMA5_2_30_31_IRQn = 175, /**< eDMA2 channel 30/31 interrupt */ DMA5_2_32_33_IRQn = 176, /**< eDMA2 channel 32/33 interrupt */ DMA5_2_34_35_IRQn = 177, /**< eDMA2 channel 34/35 interrupt */ DMA5_2_36_37_IRQn = 178, /**< eDMA2 channel 36/37 interrupt */ DMA5_2_38_39_IRQn = 179, /**< eDMA2 channel 38/39 interrupt */ DMA5_2_40_41_IRQn = 180, /**< eDMA2 channel 40/41 interrupt */ DMA5_2_42_43_IRQn = 181, /**< eDMA2 channel 42/43 interrupt */ DMA5_2_44_45_IRQn = 182, /**< eDMA2 channel 44/45 interrupt */ DMA5_2_46_47_IRQn = 183, /**< eDMA2 channel 46/47 interrupt */ DMA5_2_48_49_IRQn = 184, /**< eDMA2 channel 48/49 interrupt */ DMA5_2_50_51_IRQn = 185, /**< eDMA2 channel 50/51 interrupt */ DMA5_2_52_53_IRQn = 186, /**< eDMA2 channel 52/53 interrupt */ DMA5_2_54_55_IRQn = 187, /**< eDMA2 channel 54/55 interrupt */ DMA5_2_56_57_IRQn = 188, /**< eDMA2 channel 56/57 interrupt */ DMA5_2_58_59_IRQn = 189, /**< eDMA2 channel 58/59 interrupt */ DMA5_2_60_61_IRQn = 190, /**< eDMA2 channel 60/61 interrupt */ DMA5_2_62_63_IRQn = 191, /**< eDMA2 channel 62/63 interrupt */ Reserved192_IRQn = 192, /**< Sentinel Group 1 reset source if no s500 reference clock is detected. Output synchronized to 32khz clk. */ Reserved193_IRQn = 193, /**< Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */ Reserved194_IRQn = 194, /**< Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */ Reserved195_IRQn = 195, /**< JTAGSW DAP MDM-AP SRC reset source */ Reserved196_IRQn = 196, /**< JTAGC SRC reset source */ Reserved197_IRQn = 197, /**< CM33 SYSREQRST SRC reset source */ Reserved198_IRQn = 198, /**< CM33 LOCKUP SRC reset source */ Reserved199_IRQn = 199, /**< CM7 SYSREQRST SRC reset source */ Reserved200_IRQn = 200, /**< CM7 LOCKUP SRC reset source */ SAI2_IRQn = 201, /**< Serial Audio Interface 2 */ SAI3_IRQn = 202, /**< Serial Audio Interface 3 */ SAI4_IRQn = 203, /**< Serial Audio Interface 4 */ SAI5_IRQn = 204, /**< Serial Audio Interface 5 */ Reserved205_IRQn = 205, /**< USB-1 Wake-up Interrupt */ Reserved206_IRQn = 206, /**< USB-2 Wake-up Interrupt */ USB1_IRQn = 207, /**< USB-1 Interrupt */ USB2_IRQn = 208, /**< USB-2 Interrupt */ LPSPI5_IRQn = 209, /**< Low Power Serial Peripheral Interface 5 */ LPSPI6_IRQn = 210, /**< Low Power Serial Peripheral Interface 6 */ LPSPI7_IRQn = 211, /**< Low Power Serial Peripheral Interface 7 */ LPSPI8_IRQn = 212, /**< Low Power Serial Peripheral Interface 8 */ LPI2C5_IRQn = 213, /**< Low Power Inter-Integrated Circuit module 5 */ LPI2C6_IRQn = 214, /**< Low Power Inter-Integrated Circuit module 6 */ LPI2C7_IRQn = 215, /**< Low Power Inter-Integrated Circuit module 7 */ LPI2C8_IRQn = 216, /**< Low Power Inter-Integrated Circuit module 8 */ PDM_HWVAD_ERROR_IRQn = 217, /**< PDM interrupt */ PDM_HWVAD_EVENT_IRQn = 218, /**< PDM interrupt */ PDM_ERROR_IRQn = 219, /**< PDM interrupt */ PDM_EVENT_IRQn = 220, /**< PDM interrupt */ Reserved221_IRQn = 221, /**< AUDIO XCVR interrupt */ Reserved222_IRQn = 222, /**< AUDIO XCVR interrupt */ uSDHC3_IRQn = 223, /**< ultra Secure Digital Host Controller interrupt 3 */ Reserved224_IRQn = 224, /**< OCRAM MECC interrupt */ Reserved225_IRQn = 225, /**< OCRAM MECC interrupt */ Reserved226_IRQn = 226, /**< CM33 MCM interrupt */ Reserved227_IRQn = 227, /**< ANAMIX SFA interrupt */ Reserved228_IRQn = 228, /**< GIC700 Fault */ Reserved229_IRQn = 229, /**< GIC700 Error */ Reserved230_IRQn = 230, /**< GIC700 PMU Counter Overflow */ ADC_ER_IRQn = 231, /**< ADC interrupt */ ADC_WD_IRQn = 232, /**< ADC interrupt */ ADC_EOC_IRQn = 233, /**< ADC interrupt */ Reserved234_IRQn = 234, /**< s500 glue logic IRQ */ Reserved235_IRQn = 235, /**< I3C1 wakeup irq after double sync */ Reserved236_IRQn = 236, /**< I3C2 wakeup irq after double sync */ MU5_A_IRQn = 237, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MU6_A_IRQn = 238, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MU7_B_IRQn = 239, /**< WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ MU8_B_IRQn = 240, /**< WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ Reserved241_IRQn = 241, /**< WAKEUPMIX XSPI Responder */ Reserved242_IRQn = 242, /**< AONMIX FCCU Interrupt Reaction 0 */ Reserved243_IRQn = 243, /**< AONMIX FCCU Interrupt Reaction 1 */ Reserved244_IRQn = 244, /**< AONMIX FCCU Interrupt Reaction 2 */ Reserved245_IRQn = 245, /**< AONMIX STCU Selftest end Interrupt */ DISP_IRQSTEER0_IRQn = 246, /**< DISPLAYMIX IRQSTEER 0 */ DISP_IRQSTEER1_IRQn = 247, /**< DISPLAYMIX IRQSTEER 1 */ DISP_IRQSTEER2_IRQn = 248, /**< DISPLAYMIX IRQSTEER 2 */ DISP_IRQSTEER3_IRQn = 249, /**< DISPLAYMIX IRQSTEER 3 */ DISP_IRQSTEER4_IRQn = 250, /**< DISPLAYMIX IRQSTEER 4 */ DISP_IRQSTEER7_IRQn = 251, /**< DISPLAYMIX IRQSTEER 7 */ Reserved252_IRQn = 252, /**< CAMERAMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ ISI_IRQn = 253, /**< CAMERAMIX ISI interrupt Channel 0 */ Reserved254_IRQn = 254, /**< ISP Processing Interrupt - Context 0 */ Reserved255_IRQn = 255, /**< M7MIX MCM interrupt */ MU1_A_IRQn = 256, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MU1_B_IRQn = 257, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ MU2_A_IRQn = 258, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MU2_B_IRQn = 259, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ MU3_A_IRQn = 260, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MU3_B_IRQn = 261, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ MU4_A_IRQn = 262, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MU4_B_IRQn = 263, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ MU5_B_IRQn = 264, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ MU6_B_IRQn = 265, /**< AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ MU7_A_IRQn = 266, /**< WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MU8_A_IRQn = 267, /**< WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ MSGINTR1_IRQn = 268, /**< MSGINTR Instance 1, Interrupt */ MSGINTR2_IRQn = 269, /**< MSGINTR Instance 2, Interrupts */ Reserved270_IRQn = 270, /**< V2X-FH MU APCH1 (APP1) interrupt */ Reserved271_IRQn = 271, /**< V2X-FH MU APHSM2 (HSM2) interrupt */ Reserved272_IRQn = 272, /**< CAMERAMIX TRDC transfer error interrupt */ Reserved273_IRQn = 273, /**< DISPLAYMIX TRDC transfer error interrupt */ Reserved274_IRQn = 274, /**< NETCMIX TRDC transfer error interrupt */ Reserved275_IRQn = 275, /**< GPUMIX TRDC transfer error interrupt */ Reserved276_IRQn = 276, /**< HSIOMIX TRDC transfer error interrupt */ Reserved277_IRQn = 277, /**< VPUMIX TRDC transfer error interrupt */ Reserved278_IRQn = 278, /**< AONMIX ERM Single bit corrected ECC Error */ Reserved279_IRQn = 279, /**< M7MIX ERM Single bit corrected ECC Error */ Reserved280_IRQn = 280, /**< WAKEUPMIX ERM Single bit corrected ECC Error */ Reserved281_IRQn = 281, /**< NPUMIX ERM Single bit corrected ECC Error */ Reserved282_IRQn = 282, /**< WAKEUPMIX ACP EDMA error interrupt */ Reserved283_IRQn = 283, /**< OCRAM_C ECC multiple bit or address error */ Reserved284_IRQn = 284, /**< CAMERAMIX Cortex-M0+ Cache write-buffer error */ Reserved285_IRQn = 285, /**< CAMERAMIX Cortex-M0+ Cache data parity error */ Reserved286_IRQn = 286, /**< V2X-FH MU APSHE (SHE) interrupt */ Reserved287_IRQn = 287, /**< V2X-FH MU SCU/APDEBUG (DEBUG) interrupt */ DMA5_3_0_1_IRQn = 288, /**< eDMA3 channel 0/1 interrupt */ DMA5_3_2_3_IRQn = 289, /**< eDMA3 channel 2/3 interrupt */ DMA5_3_4_5_IRQn = 290, /**< eDMA3 channel 4/5 interrupt */ DMA5_3_6_7_IRQn = 291, /**< eDMA3 channel 6/7 interrupt */ DMA5_3_8_9_IRQn = 292, /**< eDMA3 channel 8/9 interrupt */ DMA5_3_10_11_IRQn = 293, /**< eDMA3 channel 10/11 interrupt */ DMA5_3_12_13_IRQn = 294, /**< eDMA3 channel 12/13 interrupt */ DMA5_3_14_15_IRQn = 295, /**< eDMA3 channel 14/15 interrupt */ DMA5_3_16_17_IRQn = 296, /**< eDMA3 channel 16/17 interrupt */ DMA5_3_18_19_IRQn = 297, /**< eDMA3 channel 18/19 interrupt */ DMA5_3_20_21_IRQn = 298, /**< eDMA3 channel 20/21 interrupt */ DMA5_3_22_23_IRQn = 299, /**< eDMA3 channel 22/23 interrupt */ DMA5_3_24_25_IRQn = 300, /**< eDMA3 channel 24/25 interrupt */ DMA5_3_26_27_IRQn = 301, /**< eDMA3 channel 26/27 interrupt */ DMA5_3_28_29_IRQn = 302, /**< eDMA3 channel 28/29 interrupt */ DMA5_3_30_31_IRQn = 303, /**< eDMA3 channel 30/31 interrupt */ DMA5_3_32_33_IRQn = 304, /**< eDMA3 channel 32/33 interrupt */ DMA5_3_34_35_IRQn = 305, /**< eDMA3 channel 34/35 interrupt */ DMA5_3_36_37_IRQn = 306, /**< eDMA3 channel 36/37 interrupt */ DMA5_3_38_39_IRQn = 307, /**< eDMA3 channel 38/39 interrupt */ DMA5_3_40_41_IRQn = 308, /**< eDMA3 channel 40/41 interrupt */ DMA5_3_42_43_IRQn = 309, /**< eDMA3 channel 42/43 interrupt */ DMA5_3_44_45_IRQn = 310, /**< eDMA3 channel 44/45 interrupt */ DMA5_3_46_47_IRQn = 311, /**< eDMA3 channel 46/47 interrupt */ DMA5_3_48_49_IRQn = 312, /**< eDMA3 channel 48/49 interrupt */ DMA5_3_50_51_IRQn = 313, /**< eDMA3 channel 50/51 interrupt */ DMA5_3_52_53_IRQn = 314, /**< eDMA3 channel 52/53 interrupt */ DMA5_3_54_55_IRQn = 315, /**< eDMA3 channel 54/55 interrupt */ DMA5_3_56_57_IRQn = 316, /**< eDMA3 channel 56/57 interrupt */ DMA5_3_58_59_IRQn = 317, /**< eDMA3 channel 58/59 interrupt */ DMA5_3_60_61_IRQn = 318, /**< eDMA3 channel 60/61 interrupt */ DMA5_3_62_63_IRQn = 319, /**< eDMA3 channel 62/63 interrupt */ Reserved320_IRQn = 320, /**< GPUMIX GPU Interrupt */ Reserved321_IRQn = 321, /**< GPUMIX Job Interrupt */ Reserved322_IRQn = 322, /**< GPUMIX MMU Interrupt */ Reserved323_IRQn = 323, /**< Reserved INTERRUPT */ Reserved324_IRQn = 324, /**< Reserved interrupt */ Reserved325_IRQn = 325, /**< Reserved interrupt */ Reserved326_IRQn = 326, /**< Reserved interrupt */ Reserved327_IRQn = 327, /**< Reserved interrupt */ Reserved328_IRQn = 328, /**< Reserved interrupt */ Reserved329_IRQn = 329, /**< Reserved interrupt */ Reserved330_IRQn = 330, /**< Reserved interrupt */ Reserved331_IRQn = 331, /**< Reserved interrupt */ Reserved332_IRQn = 332, /**< Reserved interrupt */ Reserved333_IRQn = 333, /**< Reserved interrupt */ Reserved334_IRQn = 334, /**< Reserved interrupt */ Reserved335_IRQn = 335, /**< Reserved interrupt */ Reserved336_IRQn = 336, /**< NETC iEPRC PCI INT */ Reserved337_IRQn = 337, /**< NETC iEPRC PCI INT */ Reserved338_IRQn = 338, /**< PCIe Controller 1 INTA */ Reserved339_IRQn = 339, /**< PCIe Controller 1 INTB */ Reserved340_IRQn = 340, /**< PCIe Controller 1 INTC */ Reserved341_IRQn = 341, /**< PCIe Controller 1 INTD */ Reserved342_IRQn = 342, /**< PCIe interrupts */ Reserved343_IRQn = 343, /**< PCIe Controller EDMA channel interrupt */ Reserved344_IRQn = 344, /**< PCIe Controller 1 INTA */ Reserved345_IRQn = 345, /**< PCIe Controller 1 INTB */ Reserved346_IRQn = 346, /**< PCIe Controller 1 INTC */ Reserved347_IRQn = 347, /**< PCIe Controller 1 INTD */ Reserved348_IRQn = 348, /**< PCIe miscellaneous interrupts */ Reserved349_IRQn = 349, /**< PCIe Controller EDMA channel interrupt */ Reserved350_IRQn = 350, /**< Wakeup interrupt from CLKREQ#, WAKEUP#, BEACON_DET */ Reserved351_IRQn = 351, /**< NPUMIX Functional interrupt */ Reserved352_IRQn = 352, /**< DISPLAYMIX Real-time traffic TBU: Fault Handling RAS Interrupt for a contained error */ Reserved353_IRQn = 353, /**< DISPLAYMIX Real-time traffic TBU: Error Handling RAS Interrupt for an uncontained error */ Reserved354_IRQn = 354, /**< DISPLAYMIX Real-time traffic TBU: Critical Error Interrupt for an uncontainable error */ Reserved355_IRQn = 355, /**< DISPLAYMIX Real-time traffic TBU: PMU Interrupt */ Reserved356_IRQn = 356, /**< TCU Event queue, secure interrupt */ Reserved357_IRQn = 357, /**< TCU Event queue, non-secure interrupt */ Reserved358_IRQn = 358, /**< TCU SYNC complete, non-secure interrupt */ Reserved359_IRQn = 359, /**< TCU SYNC complete, secure interrupt */ Reserved360_IRQn = 360, /**< TCU global non-secure interrupt */ Reserved361_IRQn = 361, /**< TCU global secure interrupt */ Reserved362_IRQn = 362, /**< TCU fault handling RAS interrupt for a contained error */ Reserved363_IRQn = 363, /**< TCU error recovery RAS interrupt for an uncontained error */ Reserved364_IRQn = 364, /**< TCU critical error interrupt, for an uncontainable uncorrected error */ Reserved365_IRQn = 365, /**< TCU PMU interrupt */ Reserved366_IRQn = 366, /**< TCU Page Request Interface */ Reserved367_IRQn = 367, /**< SRC/GPC Low Power Handshake Gasket interrupt request for system management */ Reserved368_IRQn = 368, /**< CAMERAMIX MU Ored of all */ Reserved369_IRQn = 369, /**< CAMERAMIX MU Ored of all */ Reserved370_IRQn = 370, /**< CAMERAMIX MU Ored of all */ Reserved371_IRQn = 371, /**< CAMERAMIX MU Ored of all */ Reserved372_IRQn = 372, /**< CAMERAMIX MU Ored of all */ Reserved373_IRQn = 373, /**< CAMERAMIX MU Ored of all */ Reserved374_IRQn = 374, /**< CAMERAMIX MU Ored of all */ Reserved375_IRQn = 375, /**< CAMERAMIX MU Ored of all */ Reserved376_IRQn = 376, /**< CAMERAMIX ISI interrupt Channel 1 */ Reserved377_IRQn = 377, /**< CAMERAMIX ISI interrupt Channel 2 */ Reserved378_IRQn = 378, /**< CAMERAMIX ISI interrupt Channel 3 */ Reserved379_IRQn = 379, /**< CAMERAMIX ISI interrupt Channel 4 */ Reserved380_IRQn = 380, /**< CAMERAMIX ISI interrupt Channel 5 */ Reserved381_IRQn = 381, /**< CAMERAMIX ISI interrupt Channel 6 */ Reserved382_IRQn = 382, /**< CAMERAMIX ISI interrupt Channel 7 */ Reserved383_IRQn = 383, /**< CAMERAMIX EDMA error interrupt */ Reserved384_IRQn = 384, /**< CAMERAMIX EDMA channel 0 interrupt */ Reserved385_IRQn = 385, /**< CAMERAMIX EDMA channel 2 interrupt */ Reserved386_IRQn = 386, /**< CAMERAMIX EDMA channel 4 interrupt */ Reserved387_IRQn = 387, /**< CAMERAMIX EDMA channel 6 interrupt */ Reserved388_IRQn = 388, /**< CAMERAMIX EDMA channel 8 interrupt */ Reserved389_IRQn = 389, /**< CAMERAMIX EDMA channel 10 interrupt */ Reserved390_IRQn = 390, /**< CAMERAMIX EDMA channel 12 interrupt */ Reserved391_IRQn = 391, /**< CAMERAMIX EDMA channel 14 interrupt */ Reserved392_IRQn = 392, /**< CAMERAMIX EDMA channel 16 interrupt */ Reserved393_IRQn = 393, /**< CAMERAMIX EDMA channel 18 interrupt */ Reserved394_IRQn = 394, /**< CAMERAMIX EDMA channel 20 interrupt */ Reserved395_IRQn = 395, /**< CAMERAMIX EDMA channel 22 interrupt */ Reserved396_IRQn = 396, /**< CAMERAMIX EDMA channel 24 interrupt */ Reserved397_IRQn = 397, /**< CAMERAMIX EDMA channel 26 interrupt */ Reserved398_IRQn = 398, /**< CAMERAMIX EDMA channel 28 interrupt */ Reserved399_IRQn = 399, /**< CAMERAMIX EDMA channel 30 interrupt */ Reserved400_IRQn = 400, /**< CAMERAMIX CSI Formatting Unit 1: Buffer overflow */ Reserved401_IRQn = 401, /**< CAMERAMIX CSI Formatting Unit 1: Interlaced Error */ Reserved402_IRQn = 402, /**< CAMERAMIX CSI Formatting Unit 1: Pixel Data Type Error */ Reserved403_IRQn = 403, /**< CAMERAMIX CSI Formatting Unit 2: Buffer overflow */ Reserved404_IRQn = 404, /**< CAMERAMIX CSI Formatting Unit 2: Interlaced Error */ Reserved405_IRQn = 405, /**< CAMERAMIX CSI Formatting Unit 2: Pixel Data Type Error */ Reserved406_IRQn = 406, /**< CAMERAMIX CSI1 */ Reserved407_IRQn = 407 /**< CAMERAMIX CSI2 */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex A55 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex A55 Core Configuration * @{ */ #define __CA55_REV 0x0004 /**< Core revision r0p4 */ #define __GIC_PRIO_BITS 4 /**< Number of priority bits implemented in the GIC */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #define __FPU_USED 1 /**< Indicates whether an FPU is used or not */ #define __GIC_PRESENT 1 /**< Defines if a GIC is present or not */ #define __MMU_PRESENT 1 /**< MMU present or not */ #define __TIM_PRESENT 1 /**< Defines if a Timer is present or not */ #define __CACHE_PRESENT 1 /**< CACHE present or not */ #include "core_ca55.h" /* Core Peripheral Access Layer */ #include "system_MIMX9596_ca55.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #else #pragma push #pragma anon_unions #endif #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Main Configuration, offset: 0x0 */ __IO uint32_t MSR; /**< Main Status, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t ISR; /**< Interrupt Status, offset: 0x10 */ __IO uint32_t CEOCFR0; /**< Channel Pending 0, offset: 0x14 */ __IO uint32_t CEOCFR1; /**< Channel Pending 1, offset: 0x18 */ uint8_t RESERVED_1[4]; __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x20 */ __IO uint32_t CIMR0; /**< Channel Interrupt Mask 0, offset: 0x24 */ __IO uint32_t CIMR1; /**< Channel Interrupt Mask 1, offset: 0x28 */ uint8_t RESERVED_2[4]; __IO uint32_t WTISR; /**< Watchdog Threshold Interrupt Status, offset: 0x30 */ __IO uint32_t WTIMR; /**< Watchdog Threshold Interrupt Mask, offset: 0x34 */ uint8_t RESERVED_3[8]; __IO uint32_t DMAE; /**< DMAE, offset: 0x40 */ __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ __IO uint32_t DMAR1; /**< DMA 1, offset: 0x48 */ uint8_t RESERVED_4[20]; __IO uint32_t THRHLR0; /**< Analog Watchdog Threshold 0, offset: 0x60 */ __IO uint32_t THRHLR1; /**< Analog Watchdog Threshold 1, offset: 0x64 */ __IO uint32_t THRHLR2; /**< Analog Watchdog Threshold 2, offset: 0x68 */ __IO uint32_t THRHLR3; /**< Analog Watchdog Threshold 3, offset: 0x6C */ uint8_t RESERVED_5[16]; __IO uint32_t PSCR; /**< Presampling Control, offset: 0x80 */ __IO uint32_t PSR0; /**< Presampling 0, offset: 0x84 */ __IO uint32_t PSR1; /**< Presampling 1, offset: 0x88 */ uint8_t RESERVED_6[8]; __IO uint32_t CTR0; /**< Conversion Timing 0, offset: 0x94 */ __IO uint32_t CTR1; /**< Conversion Timing 1, offset: 0x98 */ uint8_t RESERVED_7[8]; __IO uint32_t NCMR0; /**< Normal Conversion Mask 0, offset: 0xA4 */ __IO uint32_t NCMR1; /**< Normal Conversion Mask 1, offset: 0xA8 */ uint8_t RESERVED_8[8]; __IO uint32_t JCMR0; /**< Injected Conversion Mask 0, offset: 0xB4 */ __IO uint32_t JCMR1; /**< Injected Conversion Mask 1, offset: 0xB8 */ uint8_t RESERVED_9[4]; __IO uint32_t USROFSGN; /**< User OFFSET and Gain, offset: 0xC0 */ uint8_t RESERVED_10[4]; __IO uint32_t PDEDR; /**< Power Down Exit Delay, offset: 0xC8 */ uint8_t RESERVED_11[52]; __I uint32_t PCDR[8]; /**< Precision Channel n Data, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_12[96]; __I uint32_t ICDR[8]; /**< Internal Channel n Data, array offset: 0x180, array step: 0x4 */ uint8_t RESERVED_13[224]; __IO uint32_t THRHLR4; /**< Analog Watchdog Threshold 4, offset: 0x280 */ __IO uint32_t THRHLR5; /**< Analog Watchdog Threshold 5, offset: 0x284 */ __IO uint32_t THRHLR6; /**< Analog Watchdog Threshold 6, offset: 0x288 */ __IO uint32_t THRHLR7; /**< Analog Watchdog Threshold 7, offset: 0x28C */ uint8_t RESERVED_14[32]; __IO uint32_t CWSELR0; /**< Channel Watchdog Select 0, offset: 0x2B0 */ uint8_t RESERVED_15[12]; __IO uint32_t CWSELR4; /**< Channel Watchdog Select 4, offset: 0x2C0 */ uint8_t RESERVED_16[28]; __IO uint32_t CWENR0; /**< Channel Watchdog Enable 0, offset: 0x2E0 */ __IO uint32_t CWENR1; /**< Channel Watchdog Enable 1, offset: 0x2E4 */ uint8_t RESERVED_17[8]; __IO uint32_t AWORR0; /**< Analog Watchdog Out of Range 0, offset: 0x2F0 */ __IO uint32_t AWORR1; /**< Analog Watchdog Out of Range 1, offset: 0x2F4 */ uint8_t RESERVED_18[72]; __IO uint32_t STCR1; /**< Self-Test Configuration 1, offset: 0x340 */ __IO uint32_t STCR2; /**< Self-Test Configuration 2, offset: 0x344 */ __IO uint32_t STCR3; /**< Self-Test Configuration 3, offset: 0x348 */ __IO uint32_t STBRR; /**< Self-Test Baud Rate, offset: 0x34C */ __IO uint32_t STSR1; /**< Self-Test Status 1, offset: 0x350 */ __I uint32_t STSR2; /**< Self-Test Status 2, offset: 0x354 */ __I uint32_t STSR3; /**< Self-Test Status 3, offset: 0x358 */ __I uint32_t STSR4; /**< Self-Test Status 4, offset: 0x35C */ uint8_t RESERVED_19[16]; __I uint32_t STDR1; /**< Self-Test Data 1, offset: 0x370 */ __I uint32_t STDR2; /**< Self-Test Data 2, offset: 0x374 */ uint8_t RESERVED_20[8]; __IO uint32_t STAW0R; /**< Self-Test Analog Watchdog 0, offset: 0x380 */ __IO uint32_t STAW1AR; /**< Self-Test Analog Watchdog 1A, offset: 0x384 */ __IO uint32_t STAW1BR; /**< Self-Test Analog Watchdog 1B, offset: 0x388 */ __IO uint32_t STAW2R; /**< Self-Test Analog Watchdog 2, offset: 0x38C */ uint32_t STAW3R; /**< Self-Test Analog Watchdog 3, offset: 0x390 */ __IO uint32_t STAW4R; /**< Self-Test Analog Watchdog 4, offset: 0x394 */ __IO uint32_t STAW5R; /**< Self-Test Analog Watchdog 5, offset: 0x398 */ __I uint32_t CALSTAT; /**< Calibration Status, offset: 0x39C */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /*! @name MCR - Main Configuration */ /*! @{ */ #define ADC_MCR_PWDN_MASK (0x1U) #define ADC_MCR_PWDN_SHIFT (0U) /*! PWDN - Power-Down Enable * 0b0..When ADC status is in Power-down mode (MSR[ADCSTATUS] = 001b), start ADC transition to IDLE mode * 0b1..Request to enter Power-down mode */ #define ADC_MCR_PWDN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_PWDN_SHIFT)) & ADC_MCR_PWDN_MASK) #define ADC_MCR_ACKO_MASK (0x20U) #define ADC_MCR_ACKO_SHIFT (5U) /*! ACKO - Auto-Clock-Off Mode Enable * 0b0..Auto-Clock-Off feature is disabled * 0b1..Auto-Clock-Off feature is enabled */ #define ADC_MCR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ACKO_SHIFT)) & ADC_MCR_ACKO_MASK) #define ADC_MCR_ABORT_MASK (0x40U) #define ADC_MCR_ABORT_SHIFT (6U) /*! ABORT - Abort Conversion * 0b0..Channel conversion has been aborted, or channel conversion is not currently running * 0b1..Abort current channel conversion */ #define ADC_MCR_ABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORT_SHIFT)) & ADC_MCR_ABORT_MASK) #define ADC_MCR_ABORTCHAIN_MASK (0x80U) #define ADC_MCR_ABORTCHAIN_SHIFT (7U) /*! ABORTCHAIN - Abort Conversion Chain * 0b0..Chain conversion aborted or is currently not running * 0b1..Abort current chain conversion */ #define ADC_MCR_ABORTCHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ABORTCHAIN_SHIFT)) & ADC_MCR_ABORTCHAIN_MASK) #define ADC_MCR_ADCLKSE_MASK (0x100U) #define ADC_MCR_ADCLKSE_SHIFT (8U) /*! ADCLKSE - Analog Clock Frequency Select * 0b0..AD_CLK frequency is half * 0b1..AD_CLK frequency is equal to bus clock frequency */ #define ADC_MCR_ADCLKSE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ADCLKSE_SHIFT)) & ADC_MCR_ADCLKSE_MASK) #define ADC_MCR_TSAMP_MASK (0x600U) #define ADC_MCR_TSAMP_SHIFT (9U) /*! TSAMP - Sample Time for Calibration * 0b00..22 cycles of AD_CLK (default) * 0b01..8 cycles of AD_CLK * 0b10..16 cycle of AD_CLK * 0b11..32 cycle of AD_CLK */ #define ADC_MCR_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_TSAMP_SHIFT)) & ADC_MCR_TSAMP_MASK) #define ADC_MCR_NRSMPL_MASK (0x1800U) #define ADC_MCR_NRSMPL_SHIFT (11U) /*! NRSMPL - Number of Averaging Samples * 0b00..16 * 0b01..32 * 0b10..128 * 0b11..512 */ #define ADC_MCR_NRSMPL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NRSMPL_SHIFT)) & ADC_MCR_NRSMPL_MASK) #define ADC_MCR_AVGEN_MASK (0x2000U) #define ADC_MCR_AVGEN_SHIFT (13U) /*! AVGEN - Average Enable * 0b0..Disable * 0b1..Enable (default) */ #define ADC_MCR_AVGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_AVGEN_SHIFT)) & ADC_MCR_AVGEN_MASK) #define ADC_MCR_CALSTART_MASK (0x4000U) #define ADC_MCR_CALSTART_SHIFT (14U) /*! CALSTART - Calibration Start * 0b0..No effect * 0b1..Start calibration */ #define ADC_MCR_CALSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_CALSTART_SHIFT)) & ADC_MCR_CALSTART_MASK) #define ADC_MCR_STCL_MASK (0x8000U) #define ADC_MCR_STCL_SHIFT (15U) /*! STCL - Self-Testing Configuration Lock * 0b0..Not locked * 0b1..Locked */ #define ADC_MCR_STCL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_STCL_SHIFT)) & ADC_MCR_STCL_MASK) #define ADC_MCR_JSTART_MASK (0x100000U) #define ADC_MCR_JSTART_SHIFT (20U) /*! JSTART - Start Injection Conversion */ #define ADC_MCR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_JSTART_SHIFT)) & ADC_MCR_JSTART_MASK) #define ADC_MCR_NSTART_MASK (0x1000000U) #define ADC_MCR_NSTART_SHIFT (24U) /*! NSTART - Normal Conversion Start */ #define ADC_MCR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_NSTART_SHIFT)) & ADC_MCR_NSTART_MASK) #define ADC_MCR_MODE_MASK (0x20000000U) #define ADC_MCR_MODE_SHIFT (29U) /*! MODE - Normal Scan Mode Select * 0b0..One-Shot Operation mode * 0b1..Scan Operation mode */ #define ADC_MCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_MODE_SHIFT)) & ADC_MCR_MODE_MASK) #define ADC_MCR_WLSIDE_MASK (0x40000000U) #define ADC_MCR_WLSIDE_SHIFT (30U) /*! WLSIDE - Write Left Side * 0b0..Write right-aligned conversion data (from 11 to 0) * 0b1..Write left-aligned conversion data (from 15 to 4) */ #define ADC_MCR_WLSIDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_WLSIDE_SHIFT)) & ADC_MCR_WLSIDE_MASK) #define ADC_MCR_OWREN_MASK (0x80000000U) #define ADC_MCR_OWREN_SHIFT (31U) /*! OWREN - Overwrite Enable * 0b0..Older valid conversion data is not overwritten by newer conversion data * 0b1..Newer conversion result is always overwritten, irrespective of the validity of older conversion data */ #define ADC_MCR_OWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_MCR_OWREN_SHIFT)) & ADC_MCR_OWREN_MASK) /*! @} */ /*! @name MSR - Main Status */ /*! @{ */ #define ADC_MSR_ADCSTATUS_MASK (0x7U) #define ADC_MSR_ADCSTATUS_SHIFT (0U) /*! ADCSTATUS - ADC Status * 0b000..Idle * 0b001..Power-down * 0b100..Sample * 0b110..Conversion * 0b010..Wait state * 0b011..Busy in calibration */ #define ADC_MSR_ADCSTATUS(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ADCSTATUS_SHIFT)) & ADC_MSR_ADCSTATUS_MASK) #define ADC_MSR_ACKO_MASK (0x20U) #define ADC_MSR_ACKO_SHIFT (5U) /*! ACKO - Auto-Clock-Off Enable * 0b0..Auto-Clock-Off feature is not enabled * 0b1..Auto-Clock-Off feature is enabled */ #define ADC_MSR_ACKO(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_ACKO_SHIFT)) & ADC_MSR_ACKO_MASK) #define ADC_MSR_CHADDR_MASK (0xFE00U) #define ADC_MSR_CHADDR_SHIFT (9U) /*! CHADDR - Channel Address * 0b0000000..Channel 0 selected * 0b0000001..Channel 1 selected * 0b0000010..Channel 2 selected * 0b0000011..Channel 3 selected * 0b0000100..Channel 4 selected * 0b0000101..Channel 5 selected * 0b0000110..Channel 6 selected * 0b0000111..Channel 7 selected * 0b0001000..Reserved * 0b0001001..Reserved * 0b0001010..Reserved * 0b0001011..Bandgap input selected * 0b0001100..Pre-sample voltage - 1 : DVDD1P0/2 * 0b0001101..Pre-sample voltage - 2 : AVDD1p8/4 * 0b0001110..Pre-sample voltage - 3 : VREFL_1p8 * 0b0001111..Pre-sample voltage - 4 : VREFH_1p8 */ #define ADC_MSR_CHADDR(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CHADDR_SHIFT)) & ADC_MSR_CHADDR_MASK) #define ADC_MSR_SELF_TEST_S_MASK (0x40000U) #define ADC_MSR_SELF_TEST_S_SHIFT (18U) /*! SELF_TEST_S - Self-Test Status * 0b0..Self-test conversion is not in process * 0b1..Self-test conversion is in process */ #define ADC_MSR_SELF_TEST_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_SELF_TEST_S_SHIFT)) & ADC_MSR_SELF_TEST_S_MASK) #define ADC_MSR_JSTART_MASK (0x100000U) #define ADC_MSR_JSTART_SHIFT (20U) /*! JSTART - Injected Conversion Status * 0b0..Injected conversion is not in process * 0b1..Injected conversion is in process */ #define ADC_MSR_JSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JSTART_SHIFT)) & ADC_MSR_JSTART_MASK) #define ADC_MSR_JABORT_MASK (0x800000U) #define ADC_MSR_JABORT_SHIFT (23U) /*! JABORT - Injected Conversion Abort Status * 0b0..Injected conversion has not been aborted * 0b1..Injected conversion has been aborted */ #define ADC_MSR_JABORT(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_JABORT_SHIFT)) & ADC_MSR_JABORT_MASK) #define ADC_MSR_NSTART_MASK (0x1000000U) #define ADC_MSR_NSTART_SHIFT (24U) /*! NSTART - Normal Conversion Status * 0b0..Normal conversion is not in process * 0b1..Normal conversion is in process */ #define ADC_MSR_NSTART(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_NSTART_SHIFT)) & ADC_MSR_NSTART_MASK) #define ADC_MSR_CALBUSY_MASK (0x20000000U) #define ADC_MSR_CALBUSY_SHIFT (29U) /*! CALBUSY - Calibration Busy * 0b0..ADC is ready for use * 0b1..ADC is busy in a calibration process */ #define ADC_MSR_CALBUSY(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALBUSY_SHIFT)) & ADC_MSR_CALBUSY_MASK) #define ADC_MSR_CALFAIL_MASK (0x40000000U) #define ADC_MSR_CALFAIL_SHIFT (30U) /*! CALFAIL - Calibration Failed * 0b0..Calibration passed (must be checked with CALBUSY = 0b) * 0b1..Calibration failed * 0b0..No effect * 0b1..Clear the flag */ #define ADC_MSR_CALFAIL(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALFAIL_SHIFT)) & ADC_MSR_CALFAIL_MASK) #define ADC_MSR_CALIBRTD_MASK (0x80000000U) #define ADC_MSR_CALIBRTD_SHIFT (31U) /*! CALIBRTD - Calibration Status * 0b0..Uncalibrated or calibration unsuccessful * 0b1..Calibrated or calibration successful */ #define ADC_MSR_CALIBRTD(x) (((uint32_t)(((uint32_t)(x)) << ADC_MSR_CALIBRTD_SHIFT)) & ADC_MSR_CALIBRTD_MASK) /*! @} */ /*! @name ISR - Interrupt Status */ /*! @{ */ #define ADC_ISR_ECH_MASK (0x1U) #define ADC_ISR_ECH_SHIFT (0U) /*! ECH - End of Conversion Chain * 0b0..End of conversion chain has not occurred * 0b1..End of conversion chain has occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_ISR_ECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_ECH_SHIFT)) & ADC_ISR_ECH_MASK) #define ADC_ISR_EOC_MASK (0x2U) #define ADC_ISR_EOC_SHIFT (1U) /*! EOC - End of Channel Conversion * 0b0..Channel end of conversion has not occurred * 0b1..Channel end of conversion has occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_ISR_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_EOC_SHIFT)) & ADC_ISR_EOC_MASK) #define ADC_ISR_JECH_MASK (0x4U) #define ADC_ISR_JECH_SHIFT (2U) /*! JECH - Injected End of Conversion Chain * 0b0..Injected channel end of conversion chain has not occurred * 0b1..Injected channel end of conversion chain has occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_ISR_JECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JECH_SHIFT)) & ADC_ISR_JECH_MASK) #define ADC_ISR_JEOC_MASK (0x8U) #define ADC_ISR_JEOC_SHIFT (3U) /*! JEOC - Injected Channel End of Conversion * 0b0..Injected channel end of conversion has not occurred * 0b1..Injected channel end of conversion has occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_ISR_JEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ISR_JEOC_SHIFT)) & ADC_ISR_JEOC_MASK) /*! @} */ /*! @name CEOCFR0 - Channel Pending 0 */ /*! @{ */ #define ADC_CEOCFR0_EOC_CH0_MASK (0x1U) #define ADC_CEOCFR0_EOC_CH0_SHIFT (0U) /*! EOC_CH0 - Channel 0 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH0_SHIFT)) & ADC_CEOCFR0_EOC_CH0_MASK) #define ADC_CEOCFR0_EOC_CH1_MASK (0x2U) #define ADC_CEOCFR0_EOC_CH1_SHIFT (1U) /*! EOC_CH1 - Channel 1 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH1_SHIFT)) & ADC_CEOCFR0_EOC_CH1_MASK) #define ADC_CEOCFR0_EOC_CH2_MASK (0x4U) #define ADC_CEOCFR0_EOC_CH2_SHIFT (2U) /*! EOC_CH2 - Channel 2 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH2_SHIFT)) & ADC_CEOCFR0_EOC_CH2_MASK) #define ADC_CEOCFR0_EOC_CH3_MASK (0x8U) #define ADC_CEOCFR0_EOC_CH3_SHIFT (3U) /*! EOC_CH3 - Channel 3 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH3_SHIFT)) & ADC_CEOCFR0_EOC_CH3_MASK) #define ADC_CEOCFR0_EOC_CH4_MASK (0x10U) #define ADC_CEOCFR0_EOC_CH4_SHIFT (4U) /*! EOC_CH4 - Channel 4 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH4_SHIFT)) & ADC_CEOCFR0_EOC_CH4_MASK) #define ADC_CEOCFR0_EOC_CH5_MASK (0x20U) #define ADC_CEOCFR0_EOC_CH5_SHIFT (5U) /*! EOC_CH5 - Channel 5 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH5_SHIFT)) & ADC_CEOCFR0_EOC_CH5_MASK) #define ADC_CEOCFR0_EOC_CH6_MASK (0x40U) #define ADC_CEOCFR0_EOC_CH6_SHIFT (6U) /*! EOC_CH6 - Channel 6 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH6_SHIFT)) & ADC_CEOCFR0_EOC_CH6_MASK) #define ADC_CEOCFR0_EOC_CH7_MASK (0x80U) #define ADC_CEOCFR0_EOC_CH7_SHIFT (7U) /*! EOC_CH7 - Channel 7 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR0_EOC_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR0_EOC_CH7_SHIFT)) & ADC_CEOCFR0_EOC_CH7_MASK) /*! @} */ /*! @name CEOCFR1 - Channel Pending 1 */ /*! @{ */ #define ADC_CEOCFR1_EOC_CH32_MASK (0x1U) #define ADC_CEOCFR1_EOC_CH32_SHIFT (0U) /*! EOC_CH32 - Channel 32 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH32_SHIFT)) & ADC_CEOCFR1_EOC_CH32_MASK) #define ADC_CEOCFR1_EOC_CH33_MASK (0x2U) #define ADC_CEOCFR1_EOC_CH33_SHIFT (1U) /*! EOC_CH33 - Channel 33 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH33_SHIFT)) & ADC_CEOCFR1_EOC_CH33_MASK) #define ADC_CEOCFR1_EOC_CH34_MASK (0x4U) #define ADC_CEOCFR1_EOC_CH34_SHIFT (2U) /*! EOC_CH34 - Channel 34 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH34_SHIFT)) & ADC_CEOCFR1_EOC_CH34_MASK) #define ADC_CEOCFR1_EOC_CH35_MASK (0x8U) #define ADC_CEOCFR1_EOC_CH35_SHIFT (3U) /*! EOC_CH35 - Channel 35 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH35_SHIFT)) & ADC_CEOCFR1_EOC_CH35_MASK) #define ADC_CEOCFR1_EOC_CH36_MASK (0x10U) #define ADC_CEOCFR1_EOC_CH36_SHIFT (4U) /*! EOC_CH36 - Channel 36 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH36_SHIFT)) & ADC_CEOCFR1_EOC_CH36_MASK) #define ADC_CEOCFR1_EOC_CH37_MASK (0x20U) #define ADC_CEOCFR1_EOC_CH37_SHIFT (5U) /*! EOC_CH37 - Channel 37 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH37_SHIFT)) & ADC_CEOCFR1_EOC_CH37_MASK) #define ADC_CEOCFR1_EOC_CH38_MASK (0x40U) #define ADC_CEOCFR1_EOC_CH38_SHIFT (6U) /*! EOC_CH38 - Channel 38 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH38_SHIFT)) & ADC_CEOCFR1_EOC_CH38_MASK) #define ADC_CEOCFR1_EOC_CH39_MASK (0x80U) #define ADC_CEOCFR1_EOC_CH39_SHIFT (7U) /*! EOC_CH39 - Channel 39 EOC Status * 0b0..Conversion not complete * 0b1..Conversion complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_CEOCFR1_EOC_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CEOCFR1_EOC_CH39_SHIFT)) & ADC_CEOCFR1_EOC_CH39_MASK) /*! @} */ /*! @name IMR - Interrupt Mask */ /*! @{ */ #define ADC_IMR_MSKECH_MASK (0x1U) #define ADC_IMR_MSKECH_SHIFT (0U) /*! MSKECH - End of Chain Conversion Interrupt Mask * 0b0..End of chain conversion interrupt disabled * 0b1..End of chain conversion interrupt enabled */ #define ADC_IMR_MSKECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKECH_SHIFT)) & ADC_IMR_MSKECH_MASK) #define ADC_IMR_MSKEOC_MASK (0x2U) #define ADC_IMR_MSKEOC_SHIFT (1U) /*! MSKEOC - End of Conversion Interrupt Mask * 0b0..End of conversion interrupt disabled * 0b1..End of conversion interrupt enabled */ #define ADC_IMR_MSKEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKEOC_SHIFT)) & ADC_IMR_MSKEOC_MASK) #define ADC_IMR_MSKJECH_MASK (0x4U) #define ADC_IMR_MSKJECH_SHIFT (2U) /*! MSKJECH - End of Injected Chain Conversion Interrupt Mask * 0b0..End of injected chain conversion interrupt disabled * 0b1..End of injected chain conversion interrupt enabled */ #define ADC_IMR_MSKJECH(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJECH_SHIFT)) & ADC_IMR_MSKJECH_MASK) #define ADC_IMR_MSKJEOC_MASK (0x8U) #define ADC_IMR_MSKJEOC_SHIFT (3U) /*! MSKJEOC - End of Injected Conversion Interrupt Mask * 0b0..End of injected conversion interrupt disabled * 0b1..End of injected conversion interrupt enabled */ #define ADC_IMR_MSKJEOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_IMR_MSKJEOC_SHIFT)) & ADC_IMR_MSKJEOC_MASK) /*! @} */ /*! @name CIMR0 - Channel Interrupt Mask 0 */ /*! @{ */ #define ADC_CIMR0_CIM0_MASK (0x1U) #define ADC_CIMR0_CIM0_SHIFT (0U) /*! CIM0 - Channel 0 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM0_SHIFT)) & ADC_CIMR0_CIM0_MASK) #define ADC_CIMR0_CIM1_MASK (0x2U) #define ADC_CIMR0_CIM1_SHIFT (1U) /*! CIM1 - Channel 1 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM1_SHIFT)) & ADC_CIMR0_CIM1_MASK) #define ADC_CIMR0_CIM2_MASK (0x4U) #define ADC_CIMR0_CIM2_SHIFT (2U) /*! CIM2 - Channel 2 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM2_SHIFT)) & ADC_CIMR0_CIM2_MASK) #define ADC_CIMR0_CIM3_MASK (0x8U) #define ADC_CIMR0_CIM3_SHIFT (3U) /*! CIM3 - Channel 3 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM3_SHIFT)) & ADC_CIMR0_CIM3_MASK) #define ADC_CIMR0_CIM4_MASK (0x10U) #define ADC_CIMR0_CIM4_SHIFT (4U) /*! CIM4 - Channel 4 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM4_SHIFT)) & ADC_CIMR0_CIM4_MASK) #define ADC_CIMR0_CIM5_MASK (0x20U) #define ADC_CIMR0_CIM5_SHIFT (5U) /*! CIM5 - Channel 5 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM5_SHIFT)) & ADC_CIMR0_CIM5_MASK) #define ADC_CIMR0_CIM6_MASK (0x40U) #define ADC_CIMR0_CIM6_SHIFT (6U) /*! CIM6 - Channel 6 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM6_SHIFT)) & ADC_CIMR0_CIM6_MASK) #define ADC_CIMR0_CIM7_MASK (0x80U) #define ADC_CIMR0_CIM7_SHIFT (7U) /*! CIM7 - Channel 7 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR0_CIM7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR0_CIM7_SHIFT)) & ADC_CIMR0_CIM7_MASK) /*! @} */ /*! @name CIMR1 - Channel Interrupt Mask 1 */ /*! @{ */ #define ADC_CIMR1_CIM32_MASK (0x1U) #define ADC_CIMR1_CIM32_SHIFT (0U) /*! CIM32 - Channel 32 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM32_SHIFT)) & ADC_CIMR1_CIM32_MASK) #define ADC_CIMR1_CIM33_MASK (0x2U) #define ADC_CIMR1_CIM33_SHIFT (1U) /*! CIM33 - Channel 33 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM33_SHIFT)) & ADC_CIMR1_CIM33_MASK) #define ADC_CIMR1_CIM34_MASK (0x4U) #define ADC_CIMR1_CIM34_SHIFT (2U) /*! CIM34 - Channel 34 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM34_SHIFT)) & ADC_CIMR1_CIM34_MASK) #define ADC_CIMR1_CIM35_MASK (0x8U) #define ADC_CIMR1_CIM35_SHIFT (3U) /*! CIM35 - Channel 35 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM35_SHIFT)) & ADC_CIMR1_CIM35_MASK) #define ADC_CIMR1_CIM36_MASK (0x10U) #define ADC_CIMR1_CIM36_SHIFT (4U) /*! CIM36 - Channel 36 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM36_SHIFT)) & ADC_CIMR1_CIM36_MASK) #define ADC_CIMR1_CIM37_MASK (0x20U) #define ADC_CIMR1_CIM37_SHIFT (5U) /*! CIM37 - Channel 37 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM37_SHIFT)) & ADC_CIMR1_CIM37_MASK) #define ADC_CIMR1_CIM38_MASK (0x40U) #define ADC_CIMR1_CIM38_SHIFT (6U) /*! CIM38 - Channel 38 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM38_SHIFT)) & ADC_CIMR1_CIM38_MASK) #define ADC_CIMR1_CIM39_MASK (0x80U) #define ADC_CIMR1_CIM39_SHIFT (7U) /*! CIM39 - Channel 39 Interrupt Enable * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_CIMR1_CIM39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CIMR1_CIM39_SHIFT)) & ADC_CIMR1_CIM39_MASK) /*! @} */ /*! @name WTISR - Watchdog Threshold Interrupt Status */ /*! @{ */ #define ADC_WTISR_WDG0L_MASK (0x1U) #define ADC_WTISR_WDG0L_SHIFT (0U) /*! WDG0L - Channel 0 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG0L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0L_SHIFT)) & ADC_WTISR_WDG0L_MASK) #define ADC_WTISR_WDG0H_MASK (0x2U) #define ADC_WTISR_WDG0H_SHIFT (1U) /*! WDG0H - Channel 0 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG0H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG0H_SHIFT)) & ADC_WTISR_WDG0H_MASK) #define ADC_WTISR_WDG1L_MASK (0x4U) #define ADC_WTISR_WDG1L_SHIFT (2U) /*! WDG1L - Channel 1 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG1L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1L_SHIFT)) & ADC_WTISR_WDG1L_MASK) #define ADC_WTISR_WDG1H_MASK (0x8U) #define ADC_WTISR_WDG1H_SHIFT (3U) /*! WDG1H - Channel 1 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG1H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG1H_SHIFT)) & ADC_WTISR_WDG1H_MASK) #define ADC_WTISR_WDG2L_MASK (0x10U) #define ADC_WTISR_WDG2L_SHIFT (4U) /*! WDG2L - Channel 2 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG2L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2L_SHIFT)) & ADC_WTISR_WDG2L_MASK) #define ADC_WTISR_WDG2H_MASK (0x20U) #define ADC_WTISR_WDG2H_SHIFT (5U) /*! WDG2H - Channel 2 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG2H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG2H_SHIFT)) & ADC_WTISR_WDG2H_MASK) #define ADC_WTISR_WDG3L_MASK (0x40U) #define ADC_WTISR_WDG3L_SHIFT (6U) /*! WDG3L - Channel 3 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG3L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3L_SHIFT)) & ADC_WTISR_WDG3L_MASK) #define ADC_WTISR_WDG3H_MASK (0x80U) #define ADC_WTISR_WDG3H_SHIFT (7U) /*! WDG3H - Channel 3 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG3H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG3H_SHIFT)) & ADC_WTISR_WDG3H_MASK) #define ADC_WTISR_WDG4L_MASK (0x100U) #define ADC_WTISR_WDG4L_SHIFT (8U) /*! WDG4L - Channel 4 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG4L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4L_SHIFT)) & ADC_WTISR_WDG4L_MASK) #define ADC_WTISR_WDG4H_MASK (0x200U) #define ADC_WTISR_WDG4H_SHIFT (9U) /*! WDG4H - Channel 4 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG4H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG4H_SHIFT)) & ADC_WTISR_WDG4H_MASK) #define ADC_WTISR_WDG5L_MASK (0x400U) #define ADC_WTISR_WDG5L_SHIFT (10U) /*! WDG5L - Channel 5 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG5L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5L_SHIFT)) & ADC_WTISR_WDG5L_MASK) #define ADC_WTISR_WDG5H_MASK (0x800U) #define ADC_WTISR_WDG5H_SHIFT (11U) /*! WDG5H - Channel 5 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG5H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG5H_SHIFT)) & ADC_WTISR_WDG5H_MASK) #define ADC_WTISR_WDG6L_MASK (0x1000U) #define ADC_WTISR_WDG6L_SHIFT (12U) /*! WDG6L - Channel 6 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG6L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6L_SHIFT)) & ADC_WTISR_WDG6L_MASK) #define ADC_WTISR_WDG6H_MASK (0x2000U) #define ADC_WTISR_WDG6H_SHIFT (13U) /*! WDG6H - Channel 6 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG6H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG6H_SHIFT)) & ADC_WTISR_WDG6H_MASK) #define ADC_WTISR_WDG7L_MASK (0x4000U) #define ADC_WTISR_WDG7L_SHIFT (14U) /*! WDG7L - Channel 7 Watchdog Low Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG7L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7L_SHIFT)) & ADC_WTISR_WDG7L_MASK) #define ADC_WTISR_WDG7H_MASK (0x8000U) #define ADC_WTISR_WDG7H_SHIFT (15U) /*! WDG7H - Channel 7 Watchdog High Threshold Interrupt * 0b0..Interrupt not asserted * 0b1..Interrupt asserted * 0b0..No effect * 0b1..Clear the flag */ #define ADC_WTISR_WDG7H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTISR_WDG7H_SHIFT)) & ADC_WTISR_WDG7H_MASK) /*! @} */ /*! @name WTIMR - Watchdog Threshold Interrupt Mask */ /*! @{ */ #define ADC_WTIMR_MSKWDG0L_MASK (0x1U) #define ADC_WTIMR_MSKWDG0L_SHIFT (0U) /*! MSKWDG0L - Channel 0 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG0L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0L_SHIFT)) & ADC_WTIMR_MSKWDG0L_MASK) #define ADC_WTIMR_MSKWDG0H_MASK (0x2U) #define ADC_WTIMR_MSKWDG0H_SHIFT (1U) /*! MSKWDG0H - Channel 0 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG0H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG0H_SHIFT)) & ADC_WTIMR_MSKWDG0H_MASK) #define ADC_WTIMR_MSKWDG1L_MASK (0x4U) #define ADC_WTIMR_MSKWDG1L_SHIFT (2U) /*! MSKWDG1L - Channel 1 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG1L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1L_SHIFT)) & ADC_WTIMR_MSKWDG1L_MASK) #define ADC_WTIMR_MSKWDG1H_MASK (0x8U) #define ADC_WTIMR_MSKWDG1H_SHIFT (3U) /*! MSKWDG1H - Channel 1 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG1H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG1H_SHIFT)) & ADC_WTIMR_MSKWDG1H_MASK) #define ADC_WTIMR_MSKWDG2L_MASK (0x10U) #define ADC_WTIMR_MSKWDG2L_SHIFT (4U) /*! MSKWDG2L - Channel 2 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG2L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2L_SHIFT)) & ADC_WTIMR_MSKWDG2L_MASK) #define ADC_WTIMR_MSKWDG2H_MASK (0x20U) #define ADC_WTIMR_MSKWDG2H_SHIFT (5U) /*! MSKWDG2H - Channel 2 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG2H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG2H_SHIFT)) & ADC_WTIMR_MSKWDG2H_MASK) #define ADC_WTIMR_MSKWDG3L_MASK (0x40U) #define ADC_WTIMR_MSKWDG3L_SHIFT (6U) /*! MSKWDG3L - Channel 3 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG3L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3L_SHIFT)) & ADC_WTIMR_MSKWDG3L_MASK) #define ADC_WTIMR_MSKWDG3H_MASK (0x80U) #define ADC_WTIMR_MSKWDG3H_SHIFT (7U) /*! MSKWDG3H - Channel 3 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG3H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG3H_SHIFT)) & ADC_WTIMR_MSKWDG3H_MASK) #define ADC_WTIMR_MSKWDG4L_MASK (0x100U) #define ADC_WTIMR_MSKWDG4L_SHIFT (8U) /*! MSKWDG4L - Channel 4 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG4L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4L_SHIFT)) & ADC_WTIMR_MSKWDG4L_MASK) #define ADC_WTIMR_MSKWDG4H_MASK (0x200U) #define ADC_WTIMR_MSKWDG4H_SHIFT (9U) /*! MSKWDG4H - Channel 4 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG4H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG4H_SHIFT)) & ADC_WTIMR_MSKWDG4H_MASK) #define ADC_WTIMR_MSKWDG5L_MASK (0x400U) #define ADC_WTIMR_MSKWDG5L_SHIFT (10U) /*! MSKWDG5L - Channel 5 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG5L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5L_SHIFT)) & ADC_WTIMR_MSKWDG5L_MASK) #define ADC_WTIMR_MSKWDG5H_MASK (0x800U) #define ADC_WTIMR_MSKWDG5H_SHIFT (11U) /*! MSKWDG5H - Channel 5 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG5H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG5H_SHIFT)) & ADC_WTIMR_MSKWDG5H_MASK) #define ADC_WTIMR_MSKWDG6L_MASK (0x1000U) #define ADC_WTIMR_MSKWDG6L_SHIFT (12U) /*! MSKWDG6L - Channel 6 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG6L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6L_SHIFT)) & ADC_WTIMR_MSKWDG6L_MASK) #define ADC_WTIMR_MSKWDG6H_MASK (0x2000U) #define ADC_WTIMR_MSKWDG6H_SHIFT (13U) /*! MSKWDG6H - Channel 6 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG6H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG6H_SHIFT)) & ADC_WTIMR_MSKWDG6H_MASK) #define ADC_WTIMR_MSKWDG7L_MASK (0x4000U) #define ADC_WTIMR_MSKWDG7L_SHIFT (14U) /*! MSKWDG7L - Channel 7 Watchdog Low Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG7L(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7L_SHIFT)) & ADC_WTIMR_MSKWDG7L_MASK) #define ADC_WTIMR_MSKWDG7H_MASK (0x8000U) #define ADC_WTIMR_MSKWDG7H_SHIFT (15U) /*! MSKWDG7H - Channel 7 Watchdog High Threshold Interrupt Mask * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define ADC_WTIMR_MSKWDG7H(x) (((uint32_t)(((uint32_t)(x)) << ADC_WTIMR_MSKWDG7H_SHIFT)) & ADC_WTIMR_MSKWDG7H_MASK) /*! @} */ /*! @name DMAE - DMAE */ /*! @{ */ #define ADC_DMAE_DMAEN_MASK (0x1U) #define ADC_DMAE_DMAEN_SHIFT (0U) /*! DMAEN - DMA Global Enable * 0b0..DMA feature is disabled * 0b1..DMA feature is enabled */ #define ADC_DMAE_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DMAEN_SHIFT)) & ADC_DMAE_DMAEN_MASK) #define ADC_DMAE_DCLR_MASK (0x2U) #define ADC_DMAE_DCLR_SHIFT (1U) /*! DCLR - DMA Clear Sequence Enable * 0b0..DMA request cleared by acknowledge from DMA controller * 0b1..DMA request cleared on read of data registers */ #define ADC_DMAE_DCLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAE_DCLR_SHIFT)) & ADC_DMAE_DCLR_MASK) /*! @} */ /*! @name DMAR0 - DMA 0 */ /*! @{ */ #define ADC_DMAR0_DMA0_MASK (0x1U) #define ADC_DMAR0_DMA0_SHIFT (0U) /*! DMA0 - Channel 0 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA0_SHIFT)) & ADC_DMAR0_DMA0_MASK) #define ADC_DMAR0_DMA1_MASK (0x2U) #define ADC_DMAR0_DMA1_SHIFT (1U) /*! DMA1 - Channel 1 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA1_SHIFT)) & ADC_DMAR0_DMA1_MASK) #define ADC_DMAR0_DMA2_MASK (0x4U) #define ADC_DMAR0_DMA2_SHIFT (2U) /*! DMA2 - Channel 2 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA2_SHIFT)) & ADC_DMAR0_DMA2_MASK) #define ADC_DMAR0_DMA3_MASK (0x8U) #define ADC_DMAR0_DMA3_SHIFT (3U) /*! DMA3 - Channel 3 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA3_SHIFT)) & ADC_DMAR0_DMA3_MASK) #define ADC_DMAR0_DMA4_MASK (0x10U) #define ADC_DMAR0_DMA4_SHIFT (4U) /*! DMA4 - Channel 4 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA4_SHIFT)) & ADC_DMAR0_DMA4_MASK) #define ADC_DMAR0_DMA5_MASK (0x20U) #define ADC_DMAR0_DMA5_SHIFT (5U) /*! DMA5 - Channel 5 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA5_SHIFT)) & ADC_DMAR0_DMA5_MASK) #define ADC_DMAR0_DMA6_MASK (0x40U) #define ADC_DMAR0_DMA6_SHIFT (6U) /*! DMA6 - Channel 6 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA6_SHIFT)) & ADC_DMAR0_DMA6_MASK) #define ADC_DMAR0_DMA7_MASK (0x80U) #define ADC_DMAR0_DMA7_SHIFT (7U) /*! DMA7 - Channel 7 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR0_DMA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR0_DMA7_SHIFT)) & ADC_DMAR0_DMA7_MASK) /*! @} */ /*! @name DMAR1 - DMA 1 */ /*! @{ */ #define ADC_DMAR1_DMA32_MASK (0x1U) #define ADC_DMAR1_DMA32_SHIFT (0U) /*! DMA32 - Channel 32 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA32(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA32_SHIFT)) & ADC_DMAR1_DMA32_MASK) #define ADC_DMAR1_DMA33_MASK (0x2U) #define ADC_DMAR1_DMA33_SHIFT (1U) /*! DMA33 - Channel 33 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA33(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA33_SHIFT)) & ADC_DMAR1_DMA33_MASK) #define ADC_DMAR1_DMA34_MASK (0x4U) #define ADC_DMAR1_DMA34_SHIFT (2U) /*! DMA34 - Channel 34 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA34(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA34_SHIFT)) & ADC_DMAR1_DMA34_MASK) #define ADC_DMAR1_DMA35_MASK (0x8U) #define ADC_DMAR1_DMA35_SHIFT (3U) /*! DMA35 - Channel 35 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA35(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA35_SHIFT)) & ADC_DMAR1_DMA35_MASK) #define ADC_DMAR1_DMA36_MASK (0x10U) #define ADC_DMAR1_DMA36_SHIFT (4U) /*! DMA36 - Channel 36 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA36(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA36_SHIFT)) & ADC_DMAR1_DMA36_MASK) #define ADC_DMAR1_DMA37_MASK (0x20U) #define ADC_DMAR1_DMA37_SHIFT (5U) /*! DMA37 - Channel 37 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA37(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA37_SHIFT)) & ADC_DMAR1_DMA37_MASK) #define ADC_DMAR1_DMA38_MASK (0x40U) #define ADC_DMAR1_DMA38_SHIFT (6U) /*! DMA38 - Channel 38 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA38(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA38_SHIFT)) & ADC_DMAR1_DMA38_MASK) #define ADC_DMAR1_DMA39_MASK (0x80U) #define ADC_DMAR1_DMA39_SHIFT (7U) /*! DMA39 - Channel 39 DMA Enable * 0b0..Transfer of data in DMA mode is disabled * 0b1..Transfer of data in DMA mode is enabled */ #define ADC_DMAR1_DMA39(x) (((uint32_t)(((uint32_t)(x)) << ADC_DMAR1_DMA39_SHIFT)) & ADC_DMAR1_DMA39_MASK) /*! @} */ /*! @name THRHLR0 - Analog Watchdog Threshold 0 */ /*! @{ */ #define ADC_THRHLR0_THRL_MASK (0xFFFU) #define ADC_THRHLR0_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR0_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRL_SHIFT)) & ADC_THRHLR0_THRL_MASK) #define ADC_THRHLR0_THRH_MASK (0xFFF0000U) #define ADC_THRHLR0_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR0_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR0_THRH_SHIFT)) & ADC_THRHLR0_THRH_MASK) /*! @} */ /*! @name THRHLR1 - Analog Watchdog Threshold 1 */ /*! @{ */ #define ADC_THRHLR1_THRL_MASK (0xFFFU) #define ADC_THRHLR1_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR1_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRL_SHIFT)) & ADC_THRHLR1_THRL_MASK) #define ADC_THRHLR1_THRH_MASK (0xFFF0000U) #define ADC_THRHLR1_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR1_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR1_THRH_SHIFT)) & ADC_THRHLR1_THRH_MASK) /*! @} */ /*! @name THRHLR2 - Analog Watchdog Threshold 2 */ /*! @{ */ #define ADC_THRHLR2_THRL_MASK (0xFFFU) #define ADC_THRHLR2_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR2_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRL_SHIFT)) & ADC_THRHLR2_THRL_MASK) #define ADC_THRHLR2_THRH_MASK (0xFFF0000U) #define ADC_THRHLR2_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR2_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR2_THRH_SHIFT)) & ADC_THRHLR2_THRH_MASK) /*! @} */ /*! @name THRHLR3 - Analog Watchdog Threshold 3 */ /*! @{ */ #define ADC_THRHLR3_THRL_MASK (0xFFFU) #define ADC_THRHLR3_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR3_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRL_SHIFT)) & ADC_THRHLR3_THRL_MASK) #define ADC_THRHLR3_THRH_MASK (0xFFF0000U) #define ADC_THRHLR3_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR3_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR3_THRH_SHIFT)) & ADC_THRHLR3_THRH_MASK) /*! @} */ /*! @name PSCR - Presampling Control */ /*! @{ */ #define ADC_PSCR_PRECONV_MASK (0x1U) #define ADC_PSCR_PRECONV_SHIFT (0U) /*! PRECONV - Convert Presampled Value * 0b0..Presampling is followed by sampling then conversion. * 0b1..Presampling is followed by the conversion. */ #define ADC_PSCR_PRECONV(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PRECONV_SHIFT)) & ADC_PSCR_PRECONV_MASK) #define ADC_PSCR_PREVAL0_MASK (0x6U) #define ADC_PSCR_PREVAL0_SHIFT (1U) /*! PREVAL0 - Internal Presampling Voltage Selection */ #define ADC_PSCR_PREVAL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL0_SHIFT)) & ADC_PSCR_PREVAL0_MASK) #define ADC_PSCR_PREVAL1_MASK (0x18U) #define ADC_PSCR_PREVAL1_SHIFT (3U) /*! PREVAL1 - Internal Presampling Voltage Selection. */ #define ADC_PSCR_PREVAL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSCR_PREVAL1_SHIFT)) & ADC_PSCR_PREVAL1_MASK) /*! @} */ /*! @name PSR0 - Presampling 0 */ /*! @{ */ #define ADC_PSR0_PRES0_MASK (0x1U) #define ADC_PSR0_PRES0_SHIFT (0U) /*! PRES0 - Presampling Enable for Channel 0 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES0(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES0_SHIFT)) & ADC_PSR0_PRES0_MASK) #define ADC_PSR0_PRES1_MASK (0x2U) #define ADC_PSR0_PRES1_SHIFT (1U) /*! PRES1 - Presampling Enable for Channel 1 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES1(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES1_SHIFT)) & ADC_PSR0_PRES1_MASK) #define ADC_PSR0_PRES2_MASK (0x4U) #define ADC_PSR0_PRES2_SHIFT (2U) /*! PRES2 - Presampling Enable for Channel 2 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES2(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES2_SHIFT)) & ADC_PSR0_PRES2_MASK) #define ADC_PSR0_PRES3_MASK (0x8U) #define ADC_PSR0_PRES3_SHIFT (3U) /*! PRES3 - Presampling Enable for Channel 3 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES3(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES3_SHIFT)) & ADC_PSR0_PRES3_MASK) #define ADC_PSR0_PRES4_MASK (0x10U) #define ADC_PSR0_PRES4_SHIFT (4U) /*! PRES4 - Presampling Enable for Channel 4 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES4(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES4_SHIFT)) & ADC_PSR0_PRES4_MASK) #define ADC_PSR0_PRES5_MASK (0x20U) #define ADC_PSR0_PRES5_SHIFT (5U) /*! PRES5 - Presampling Enable for Channel 5 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES5(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES5_SHIFT)) & ADC_PSR0_PRES5_MASK) #define ADC_PSR0_PRES6_MASK (0x40U) #define ADC_PSR0_PRES6_SHIFT (6U) /*! PRES6 - Presampling Enable for Channel 6 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES6(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES6_SHIFT)) & ADC_PSR0_PRES6_MASK) #define ADC_PSR0_PRES7_MASK (0x80U) #define ADC_PSR0_PRES7_SHIFT (7U) /*! PRES7 - Presampling Enable for Channel 7 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR0_PRES7(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR0_PRES7_SHIFT)) & ADC_PSR0_PRES7_MASK) /*! @} */ /*! @name PSR1 - Presampling 1 */ /*! @{ */ #define ADC_PSR1_PRES32_MASK (0x1U) #define ADC_PSR1_PRES32_SHIFT (0U) /*! PRES32 - Presampling Enable for Channel 32 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES32(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES32_SHIFT)) & ADC_PSR1_PRES32_MASK) #define ADC_PSR1_PRES33_MASK (0x2U) #define ADC_PSR1_PRES33_SHIFT (1U) /*! PRES33 - Presampling Enable for Channel 33 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES33(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES33_SHIFT)) & ADC_PSR1_PRES33_MASK) #define ADC_PSR1_PRES34_MASK (0x4U) #define ADC_PSR1_PRES34_SHIFT (2U) /*! PRES34 - Presampling Enable for Channel 34 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES34(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES34_SHIFT)) & ADC_PSR1_PRES34_MASK) #define ADC_PSR1_PRES35_MASK (0x8U) #define ADC_PSR1_PRES35_SHIFT (3U) /*! PRES35 - Presampling Enable for Channel 35 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES35(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES35_SHIFT)) & ADC_PSR1_PRES35_MASK) #define ADC_PSR1_PRES36_MASK (0x10U) #define ADC_PSR1_PRES36_SHIFT (4U) /*! PRES36 - Presampling Enable for Channel 36 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES36(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES36_SHIFT)) & ADC_PSR1_PRES36_MASK) #define ADC_PSR1_PRES37_MASK (0x20U) #define ADC_PSR1_PRES37_SHIFT (5U) /*! PRES37 - Presampling Enable for Channel 37 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES37(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES37_SHIFT)) & ADC_PSR1_PRES37_MASK) #define ADC_PSR1_PRES38_MASK (0x40U) #define ADC_PSR1_PRES38_SHIFT (6U) /*! PRES38 - Presampling Enable for Channel 38 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES38(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES38_SHIFT)) & ADC_PSR1_PRES38_MASK) #define ADC_PSR1_PRES39_MASK (0x80U) #define ADC_PSR1_PRES39_SHIFT (7U) /*! PRES39 - Presampling Enable for Channel 39 * 0b0..Presampling is disabled * 0b1..Presampling is enabled */ #define ADC_PSR1_PRES39(x) (((uint32_t)(((uint32_t)(x)) << ADC_PSR1_PRES39_SHIFT)) & ADC_PSR1_PRES39_MASK) /*! @} */ /*! @name CTR0 - Conversion Timing 0 */ /*! @{ */ #define ADC_CTR0_INPSAMP_MASK (0xFFU) #define ADC_CTR0_INPSAMP_SHIFT (0U) /*! INPSAMP - Sampling Phase Duration */ #define ADC_CTR0_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR0_INPSAMP_SHIFT)) & ADC_CTR0_INPSAMP_MASK) /*! @} */ /*! @name CTR1 - Conversion Timing 1 */ /*! @{ */ #define ADC_CTR1_INPSAMP_MASK (0xFFU) #define ADC_CTR1_INPSAMP_SHIFT (0U) /*! INPSAMP - Sampling Phase Duration */ #define ADC_CTR1_INPSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTR1_INPSAMP_SHIFT)) & ADC_CTR1_INPSAMP_MASK) /*! @} */ /*! @name NCMR0 - Normal Conversion Mask 0 */ /*! @{ */ #define ADC_NCMR0_CH0_MASK (0x1U) #define ADC_NCMR0_CH0_SHIFT (0U) /*! CH0 - Normal Conversion Mask for Channel 0 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH0_SHIFT)) & ADC_NCMR0_CH0_MASK) #define ADC_NCMR0_CH1_MASK (0x2U) #define ADC_NCMR0_CH1_SHIFT (1U) /*! CH1 - Normal Conversion Mask for Channel 1 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH1_SHIFT)) & ADC_NCMR0_CH1_MASK) #define ADC_NCMR0_CH2_MASK (0x4U) #define ADC_NCMR0_CH2_SHIFT (2U) /*! CH2 - Normal Conversion Mask for Channel 2 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH2_SHIFT)) & ADC_NCMR0_CH2_MASK) #define ADC_NCMR0_CH3_MASK (0x8U) #define ADC_NCMR0_CH3_SHIFT (3U) /*! CH3 - Normal Conversion Mask for Channel 3 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH3_SHIFT)) & ADC_NCMR0_CH3_MASK) #define ADC_NCMR0_CH4_MASK (0x10U) #define ADC_NCMR0_CH4_SHIFT (4U) /*! CH4 - Normal Conversion Mask for Channel 4 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH4_SHIFT)) & ADC_NCMR0_CH4_MASK) #define ADC_NCMR0_CH5_MASK (0x20U) #define ADC_NCMR0_CH5_SHIFT (5U) /*! CH5 - Normal Conversion Mask for Channel 5 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH5_SHIFT)) & ADC_NCMR0_CH5_MASK) #define ADC_NCMR0_CH6_MASK (0x40U) #define ADC_NCMR0_CH6_SHIFT (6U) /*! CH6 - Normal Conversion Mask for Channel 6 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH6_SHIFT)) & ADC_NCMR0_CH6_MASK) #define ADC_NCMR0_CH7_MASK (0x80U) #define ADC_NCMR0_CH7_SHIFT (7U) /*! CH7 - Normal Conversion Mask for Channel 7 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR0_CH7_SHIFT)) & ADC_NCMR0_CH7_MASK) /*! @} */ /*! @name NCMR1 - Normal Conversion Mask 1 */ /*! @{ */ #define ADC_NCMR1_CH32_MASK (0x1U) #define ADC_NCMR1_CH32_SHIFT (0U) /*! CH32 - Normal Conversion Mask for Channel 32 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH32_SHIFT)) & ADC_NCMR1_CH32_MASK) #define ADC_NCMR1_CH33_MASK (0x2U) #define ADC_NCMR1_CH33_SHIFT (1U) /*! CH33 - Normal Conversion Mask for Channel 33 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH33_SHIFT)) & ADC_NCMR1_CH33_MASK) #define ADC_NCMR1_CH34_MASK (0x4U) #define ADC_NCMR1_CH34_SHIFT (2U) /*! CH34 - Normal Conversion Mask for Channel 34 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH34_SHIFT)) & ADC_NCMR1_CH34_MASK) #define ADC_NCMR1_CH35_MASK (0x8U) #define ADC_NCMR1_CH35_SHIFT (3U) /*! CH35 - Normal Conversion Mask for Channel 35 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH35_SHIFT)) & ADC_NCMR1_CH35_MASK) #define ADC_NCMR1_CH36_MASK (0x10U) #define ADC_NCMR1_CH36_SHIFT (4U) /*! CH36 - Normal Conversion Mask for Channel 36 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH36_SHIFT)) & ADC_NCMR1_CH36_MASK) #define ADC_NCMR1_CH37_MASK (0x20U) #define ADC_NCMR1_CH37_SHIFT (5U) /*! CH37 - Normal Conversion Mask for Channel 37 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH37_SHIFT)) & ADC_NCMR1_CH37_MASK) #define ADC_NCMR1_CH38_MASK (0x40U) #define ADC_NCMR1_CH38_SHIFT (6U) /*! CH38 - Normal Conversion Mask for Channel 38 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH38_SHIFT)) & ADC_NCMR1_CH38_MASK) #define ADC_NCMR1_CH39_MASK (0x80U) #define ADC_NCMR1_CH39_SHIFT (7U) /*! CH39 - Normal Conversion Mask for Channel 39 * 0b0..Normal Conversion is disabled * 0b1..Normal Conversion is enabled */ #define ADC_NCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_NCMR1_CH39_SHIFT)) & ADC_NCMR1_CH39_MASK) /*! @} */ /*! @name JCMR0 - Injected Conversion Mask 0 */ /*! @{ */ #define ADC_JCMR0_CH0_MASK (0x1U) #define ADC_JCMR0_CH0_SHIFT (0U) /*! CH0 - Injected Conversion Mask for Channel 0 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH0_SHIFT)) & ADC_JCMR0_CH0_MASK) #define ADC_JCMR0_CH1_MASK (0x2U) #define ADC_JCMR0_CH1_SHIFT (1U) /*! CH1 - Injected Conversion Mask for Channel 1 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH1_SHIFT)) & ADC_JCMR0_CH1_MASK) #define ADC_JCMR0_CH2_MASK (0x4U) #define ADC_JCMR0_CH2_SHIFT (2U) /*! CH2 - Injected Conversion Mask for Channel 2 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH2_SHIFT)) & ADC_JCMR0_CH2_MASK) #define ADC_JCMR0_CH3_MASK (0x8U) #define ADC_JCMR0_CH3_SHIFT (3U) /*! CH3 - Injected Conversion Mask for Channel 3 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH3_SHIFT)) & ADC_JCMR0_CH3_MASK) #define ADC_JCMR0_CH4_MASK (0x10U) #define ADC_JCMR0_CH4_SHIFT (4U) /*! CH4 - Injected Conversion Mask for Channel 4 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH4_SHIFT)) & ADC_JCMR0_CH4_MASK) #define ADC_JCMR0_CH5_MASK (0x20U) #define ADC_JCMR0_CH5_SHIFT (5U) /*! CH5 - Injected Conversion Mask for Channel 5 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH5_SHIFT)) & ADC_JCMR0_CH5_MASK) #define ADC_JCMR0_CH6_MASK (0x40U) #define ADC_JCMR0_CH6_SHIFT (6U) /*! CH6 - Injected Conversion Mask for Channel 6 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH6_SHIFT)) & ADC_JCMR0_CH6_MASK) #define ADC_JCMR0_CH7_MASK (0x80U) #define ADC_JCMR0_CH7_SHIFT (7U) /*! CH7 - Injected Conversion Mask for Channel 7 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR0_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR0_CH7_SHIFT)) & ADC_JCMR0_CH7_MASK) /*! @} */ /*! @name JCMR1 - Injected Conversion Mask 1 */ /*! @{ */ #define ADC_JCMR1_CH32_MASK (0x1U) #define ADC_JCMR1_CH32_SHIFT (0U) /*! CH32 - Injected Conversion Mask for Channel 32 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH32_SHIFT)) & ADC_JCMR1_CH32_MASK) #define ADC_JCMR1_CH33_MASK (0x2U) #define ADC_JCMR1_CH33_SHIFT (1U) /*! CH33 - Injected Conversion Mask for Channel 33 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH33_SHIFT)) & ADC_JCMR1_CH33_MASK) #define ADC_JCMR1_CH34_MASK (0x4U) #define ADC_JCMR1_CH34_SHIFT (2U) /*! CH34 - Injected Conversion Mask for Channel 34 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH34_SHIFT)) & ADC_JCMR1_CH34_MASK) #define ADC_JCMR1_CH35_MASK (0x8U) #define ADC_JCMR1_CH35_SHIFT (3U) /*! CH35 - Injected Conversion Mask for Channel 35 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH35_SHIFT)) & ADC_JCMR1_CH35_MASK) #define ADC_JCMR1_CH36_MASK (0x10U) #define ADC_JCMR1_CH36_SHIFT (4U) /*! CH36 - Injected Conversion Mask for Channel 36 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH36_SHIFT)) & ADC_JCMR1_CH36_MASK) #define ADC_JCMR1_CH37_MASK (0x20U) #define ADC_JCMR1_CH37_SHIFT (5U) /*! CH37 - Injected Conversion Mask for Channel 37 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH37_SHIFT)) & ADC_JCMR1_CH37_MASK) #define ADC_JCMR1_CH38_MASK (0x40U) #define ADC_JCMR1_CH38_SHIFT (6U) /*! CH38 - Injected Conversion Mask for Channel 38 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH38_SHIFT)) & ADC_JCMR1_CH38_MASK) #define ADC_JCMR1_CH39_MASK (0x80U) #define ADC_JCMR1_CH39_SHIFT (7U) /*! CH39 - Injected Conversion Mask for Channel 39 * 0b0..Injected conversion is disabled * 0b1..Injected conversion is enabled */ #define ADC_JCMR1_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_JCMR1_CH39_SHIFT)) & ADC_JCMR1_CH39_MASK) /*! @} */ /*! @name USROFSGN - User OFFSET and Gain */ /*! @{ */ #define ADC_USROFSGN_OFFSUSER_MASK (0xFFU) #define ADC_USROFSGN_OFFSUSER_SHIFT (0U) /*! OFFSUSER - User Defined Offset */ #define ADC_USROFSGN_OFFSUSER(x) (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_OFFSUSER_SHIFT)) & ADC_USROFSGN_OFFSUSER_MASK) #define ADC_USROFSGN_GAINUSER_MASK (0x3FF0000U) #define ADC_USROFSGN_GAINUSER_SHIFT (16U) /*! GAINUSER - User-Defined Gain Value */ #define ADC_USROFSGN_GAINUSER(x) (((uint32_t)(((uint32_t)(x)) << ADC_USROFSGN_GAINUSER_SHIFT)) & ADC_USROFSGN_GAINUSER_MASK) /*! @} */ /*! @name PDEDR - Power Down Exit Delay */ /*! @{ */ #define ADC_PDEDR_PDED_MASK (0xFFU) #define ADC_PDEDR_PDED_SHIFT (0U) /*! PDED - Power Down Exist Delay */ #define ADC_PDEDR_PDED(x) (((uint32_t)(((uint32_t)(x)) << ADC_PDEDR_PDED_SHIFT)) & ADC_PDEDR_PDED_MASK) /*! @} */ /*! @name PCDR - Precision Channel n Data */ /*! @{ */ #define ADC_PCDR_CDATA_MASK (0xFFFU) #define ADC_PCDR_CDATA_SHIFT (0U) /*! CDATA - Channel Converted Data */ #define ADC_PCDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_CDATA_SHIFT)) & ADC_PCDR_CDATA_MASK) #define ADC_PCDR_RESULT_MASK (0x30000U) #define ADC_PCDR_RESULT_SHIFT (16U) /*! RESULT - Mode of Conversion Status * 0b00..Data is a result of Normal conversion mode * 0b01..Data is a result of Injected conversion mode * 0b10..Data is a result of CTU conversion mode * 0b11..Reserved */ #define ADC_PCDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_RESULT_SHIFT)) & ADC_PCDR_RESULT_MASK) #define ADC_PCDR_OVERW_MASK (0x40000U) #define ADC_PCDR_OVERW_SHIFT (18U) /*! OVERW - Data Overwrite * 0b0..Data not overwritten * 0b1..Data overwritten */ #define ADC_PCDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_OVERW_SHIFT)) & ADC_PCDR_OVERW_MASK) #define ADC_PCDR_VALID_MASK (0x80000U) #define ADC_PCDR_VALID_SHIFT (19U) /*! VALID - Conversion Data Valid * 0b0..Not valid data * 0b1..Valid data */ #define ADC_PCDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_PCDR_VALID_SHIFT)) & ADC_PCDR_VALID_MASK) /*! @} */ /* The count of ADC_PCDR */ #define ADC_PCDR_COUNT (8U) /*! @name ICDR - Internal Channel n Data */ /*! @{ */ #define ADC_ICDR_CDATA_MASK (0xFFFU) #define ADC_ICDR_CDATA_SHIFT (0U) /*! CDATA - Channel Converted Data */ #define ADC_ICDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_CDATA_SHIFT)) & ADC_ICDR_CDATA_MASK) #define ADC_ICDR_RESULT_MASK (0x30000U) #define ADC_ICDR_RESULT_SHIFT (16U) /*! RESULT - Mode of Conversion Status * 0b00..Data is a result of Normal conversion mode * 0b01..Data is a result of Injected conversion mode * 0b10..Data is a result of CTU conversion mode * 0b11..Reserved */ #define ADC_ICDR_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_RESULT_SHIFT)) & ADC_ICDR_RESULT_MASK) #define ADC_ICDR_OVERW_MASK (0x40000U) #define ADC_ICDR_OVERW_SHIFT (18U) /*! OVERW - Data Overwrite * 0b0..Data not overwritten * 0b1..Data overwritten */ #define ADC_ICDR_OVERW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_OVERW_SHIFT)) & ADC_ICDR_OVERW_MASK) #define ADC_ICDR_VALID_MASK (0x80000U) #define ADC_ICDR_VALID_SHIFT (19U) /*! VALID - Conversion Data Valid * 0b0..Not valid data * 0b1..Valid data */ #define ADC_ICDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ICDR_VALID_SHIFT)) & ADC_ICDR_VALID_MASK) /*! @} */ /* The count of ADC_ICDR */ #define ADC_ICDR_COUNT (8U) /*! @name THRHLR4 - Analog Watchdog Threshold 4 */ /*! @{ */ #define ADC_THRHLR4_THRL_MASK (0xFFFU) #define ADC_THRHLR4_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR4_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRL_SHIFT)) & ADC_THRHLR4_THRL_MASK) #define ADC_THRHLR4_THRH_MASK (0xFFF0000U) #define ADC_THRHLR4_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR4_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR4_THRH_SHIFT)) & ADC_THRHLR4_THRH_MASK) /*! @} */ /*! @name THRHLR5 - Analog Watchdog Threshold 5 */ /*! @{ */ #define ADC_THRHLR5_THRL_MASK (0xFFFU) #define ADC_THRHLR5_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR5_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRL_SHIFT)) & ADC_THRHLR5_THRL_MASK) #define ADC_THRHLR5_THRH_MASK (0xFFF0000U) #define ADC_THRHLR5_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR5_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR5_THRH_SHIFT)) & ADC_THRHLR5_THRH_MASK) /*! @} */ /*! @name THRHLR6 - Analog Watchdog Threshold 6 */ /*! @{ */ #define ADC_THRHLR6_THRL_MASK (0xFFFU) #define ADC_THRHLR6_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR6_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRL_SHIFT)) & ADC_THRHLR6_THRL_MASK) #define ADC_THRHLR6_THRH_MASK (0xFFF0000U) #define ADC_THRHLR6_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR6_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR6_THRH_SHIFT)) & ADC_THRHLR6_THRH_MASK) /*! @} */ /*! @name THRHLR7 - Analog Watchdog Threshold 7 */ /*! @{ */ #define ADC_THRHLR7_THRL_MASK (0xFFFU) #define ADC_THRHLR7_THRL_SHIFT (0U) /*! THRL - Low Threshold */ #define ADC_THRHLR7_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRL_SHIFT)) & ADC_THRHLR7_THRL_MASK) #define ADC_THRHLR7_THRH_MASK (0xFFF0000U) #define ADC_THRHLR7_THRH_SHIFT (16U) /*! THRH - High Threshold */ #define ADC_THRHLR7_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THRHLR7_THRH_SHIFT)) & ADC_THRHLR7_THRH_MASK) /*! @} */ /*! @name CWSELR0 - Channel Watchdog Select 0 */ /*! @{ */ #define ADC_CWSELR0_WSEL_CH0_MASK (0x7U) #define ADC_CWSELR0_WSEL_CH0_SHIFT (0U) /*! WSEL_CH0 - Channel Watchdog Select for Channel 0 */ #define ADC_CWSELR0_WSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH0_SHIFT)) & ADC_CWSELR0_WSEL_CH0_MASK) #define ADC_CWSELR0_WSEL_CH1_MASK (0x70U) #define ADC_CWSELR0_WSEL_CH1_SHIFT (4U) /*! WSEL_CH1 - Channel Watchdog Select for Channel 1 */ #define ADC_CWSELR0_WSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH1_SHIFT)) & ADC_CWSELR0_WSEL_CH1_MASK) #define ADC_CWSELR0_WSEL_CH2_MASK (0x700U) #define ADC_CWSELR0_WSEL_CH2_SHIFT (8U) /*! WSEL_CH2 - Channel Watchdog Select for Channel 2 */ #define ADC_CWSELR0_WSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH2_SHIFT)) & ADC_CWSELR0_WSEL_CH2_MASK) #define ADC_CWSELR0_WSEL_CH3_MASK (0x7000U) #define ADC_CWSELR0_WSEL_CH3_SHIFT (12U) /*! WSEL_CH3 - Channel Watchdog Select for Channel 3 */ #define ADC_CWSELR0_WSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH3_SHIFT)) & ADC_CWSELR0_WSEL_CH3_MASK) #define ADC_CWSELR0_WSEL_CH4_MASK (0x70000U) #define ADC_CWSELR0_WSEL_CH4_SHIFT (16U) /*! WSEL_CH4 - Channel Watchdog Select for Channel 4 */ #define ADC_CWSELR0_WSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH4_SHIFT)) & ADC_CWSELR0_WSEL_CH4_MASK) #define ADC_CWSELR0_WSEL_CH5_MASK (0x700000U) #define ADC_CWSELR0_WSEL_CH5_SHIFT (20U) /*! WSEL_CH5 - Channel Watchdog Select for Channel 5 */ #define ADC_CWSELR0_WSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH5_SHIFT)) & ADC_CWSELR0_WSEL_CH5_MASK) #define ADC_CWSELR0_WSEL_CH6_MASK (0x7000000U) #define ADC_CWSELR0_WSEL_CH6_SHIFT (24U) /*! WSEL_CH6 - Channel Watchdog Select for Channel 6 */ #define ADC_CWSELR0_WSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH6_SHIFT)) & ADC_CWSELR0_WSEL_CH6_MASK) #define ADC_CWSELR0_WSEL_CH7_MASK (0x70000000U) #define ADC_CWSELR0_WSEL_CH7_SHIFT (28U) /*! WSEL_CH7 - Channel Watchdog Select for Channel 7 */ #define ADC_CWSELR0_WSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR0_WSEL_CH7_SHIFT)) & ADC_CWSELR0_WSEL_CH7_MASK) /*! @} */ /*! @name CWSELR4 - Channel Watchdog Select 4 */ /*! @{ */ #define ADC_CWSELR4_WSEL_CH32_MASK (0x7U) #define ADC_CWSELR4_WSEL_CH32_SHIFT (0U) /*! WSEL_CH32 - Channel Watchdog Select for Channel 32 */ #define ADC_CWSELR4_WSEL_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH32_SHIFT)) & ADC_CWSELR4_WSEL_CH32_MASK) #define ADC_CWSELR4_WSEL_CH33_MASK (0x70U) #define ADC_CWSELR4_WSEL_CH33_SHIFT (4U) /*! WSEL_CH33 - Channel Watchdog Select for Channel 33 */ #define ADC_CWSELR4_WSEL_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH33_SHIFT)) & ADC_CWSELR4_WSEL_CH33_MASK) #define ADC_CWSELR4_WSEL_CH34_MASK (0x700U) #define ADC_CWSELR4_WSEL_CH34_SHIFT (8U) /*! WSEL_CH34 - Channel Watchdog Select for Channel 34 */ #define ADC_CWSELR4_WSEL_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH34_SHIFT)) & ADC_CWSELR4_WSEL_CH34_MASK) #define ADC_CWSELR4_WSEL_CH35_MASK (0x7000U) #define ADC_CWSELR4_WSEL_CH35_SHIFT (12U) /*! WSEL_CH35 - Channel Watchdog Select for Channel 35 */ #define ADC_CWSELR4_WSEL_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH35_SHIFT)) & ADC_CWSELR4_WSEL_CH35_MASK) #define ADC_CWSELR4_WSEL_CH36_MASK (0x70000U) #define ADC_CWSELR4_WSEL_CH36_SHIFT (16U) /*! WSEL_CH36 - Channel Watchdog Select for Channel 36 */ #define ADC_CWSELR4_WSEL_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH36_SHIFT)) & ADC_CWSELR4_WSEL_CH36_MASK) #define ADC_CWSELR4_WSEL_CH37_MASK (0x700000U) #define ADC_CWSELR4_WSEL_CH37_SHIFT (20U) /*! WSEL_CH37 - Channel Watchdog Select for Channel 37 */ #define ADC_CWSELR4_WSEL_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH37_SHIFT)) & ADC_CWSELR4_WSEL_CH37_MASK) #define ADC_CWSELR4_WSEL_CH38_MASK (0x7000000U) #define ADC_CWSELR4_WSEL_CH38_SHIFT (24U) /*! WSEL_CH38 - Channel Watchdog Select for Channel 38 */ #define ADC_CWSELR4_WSEL_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH38_SHIFT)) & ADC_CWSELR4_WSEL_CH38_MASK) #define ADC_CWSELR4_WSEL_CH39_MASK (0x70000000U) #define ADC_CWSELR4_WSEL_CH39_SHIFT (28U) /*! WSEL_CH39 - Channel Watchdog Select for Channel 39 */ #define ADC_CWSELR4_WSEL_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWSELR4_WSEL_CH39_SHIFT)) & ADC_CWSELR4_WSEL_CH39_MASK) /*! @} */ /*! @name CWENR0 - Channel Watchdog Enable 0 */ /*! @{ */ #define ADC_CWENR0_CWEN0_MASK (0x1U) #define ADC_CWENR0_CWEN0_SHIFT (0U) /*! CWEN0 - Watchdog Enable for Channel 0 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN0_SHIFT)) & ADC_CWENR0_CWEN0_MASK) #define ADC_CWENR0_CWEN1_MASK (0x2U) #define ADC_CWENR0_CWEN1_SHIFT (1U) /*! CWEN1 - Watchdog Enable for Channel 1 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN1_SHIFT)) & ADC_CWENR0_CWEN1_MASK) #define ADC_CWENR0_CWEN2_MASK (0x4U) #define ADC_CWENR0_CWEN2_SHIFT (2U) /*! CWEN2 - Watchdog Enable for Channel 2 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN2_SHIFT)) & ADC_CWENR0_CWEN2_MASK) #define ADC_CWENR0_CWEN3_MASK (0x8U) #define ADC_CWENR0_CWEN3_SHIFT (3U) /*! CWEN3 - Watchdog Enable for Channel 3 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN3_SHIFT)) & ADC_CWENR0_CWEN3_MASK) #define ADC_CWENR0_CWEN4_MASK (0x10U) #define ADC_CWENR0_CWEN4_SHIFT (4U) /*! CWEN4 - Watchdog Enable for Channel 4 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN4_SHIFT)) & ADC_CWENR0_CWEN4_MASK) #define ADC_CWENR0_CWEN5_MASK (0x20U) #define ADC_CWENR0_CWEN5_SHIFT (5U) /*! CWEN5 - Watchdog Enable for Channel 5 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN5_SHIFT)) & ADC_CWENR0_CWEN5_MASK) #define ADC_CWENR0_CWEN6_MASK (0x40U) #define ADC_CWENR0_CWEN6_SHIFT (6U) /*! CWEN6 - Watchdog Enable for Channel 6 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN6_SHIFT)) & ADC_CWENR0_CWEN6_MASK) #define ADC_CWENR0_CWEN7_MASK (0x80U) #define ADC_CWENR0_CWEN7_SHIFT (7U) /*! CWEN7 - Watchdog Enable for Channel 7 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR0_CWEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR0_CWEN7_SHIFT)) & ADC_CWENR0_CWEN7_MASK) /*! @} */ /*! @name CWENR1 - Channel Watchdog Enable 1 */ /*! @{ */ #define ADC_CWENR1_CWEN32_MASK (0x1U) #define ADC_CWENR1_CWEN32_SHIFT (0U) /*! CWEN32 - Watchdog Enable for Channel 32 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN32(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN32_SHIFT)) & ADC_CWENR1_CWEN32_MASK) #define ADC_CWENR1_CWEN33_MASK (0x2U) #define ADC_CWENR1_CWEN33_SHIFT (1U) /*! CWEN33 - Watchdog Enable for Channel 33 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN33(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN33_SHIFT)) & ADC_CWENR1_CWEN33_MASK) #define ADC_CWENR1_CWEN34_MASK (0x4U) #define ADC_CWENR1_CWEN34_SHIFT (2U) /*! CWEN34 - Watchdog Enable for Channel 34 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN34(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN34_SHIFT)) & ADC_CWENR1_CWEN34_MASK) #define ADC_CWENR1_CWEN35_MASK (0x8U) #define ADC_CWENR1_CWEN35_SHIFT (3U) /*! CWEN35 - Watchdog Enable for Channel 35 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN35(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN35_SHIFT)) & ADC_CWENR1_CWEN35_MASK) #define ADC_CWENR1_CWEN36_MASK (0x10U) #define ADC_CWENR1_CWEN36_SHIFT (4U) /*! CWEN36 - Watchdog Enable for Channel 36 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN36(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN36_SHIFT)) & ADC_CWENR1_CWEN36_MASK) #define ADC_CWENR1_CWEN37_MASK (0x20U) #define ADC_CWENR1_CWEN37_SHIFT (5U) /*! CWEN37 - Watchdog Enable for Channel 37 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN37(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN37_SHIFT)) & ADC_CWENR1_CWEN37_MASK) #define ADC_CWENR1_CWEN38_MASK (0x40U) #define ADC_CWENR1_CWEN38_SHIFT (6U) /*! CWEN38 - Watchdog Enable for Channel 38 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN38(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN38_SHIFT)) & ADC_CWENR1_CWEN38_MASK) #define ADC_CWENR1_CWEN39_MASK (0x80U) #define ADC_CWENR1_CWEN39_SHIFT (7U) /*! CWEN39 - Watchdog Enable for Channel 39 * 0b0..Watchdog is disabled * 0b1..Watchdog is enabled */ #define ADC_CWENR1_CWEN39(x) (((uint32_t)(((uint32_t)(x)) << ADC_CWENR1_CWEN39_SHIFT)) & ADC_CWENR1_CWEN39_MASK) /*! @} */ /*! @name AWORR0 - Analog Watchdog Out of Range 0 */ /*! @{ */ #define ADC_AWORR0_AWOR_CH0_MASK (0x1U) #define ADC_AWORR0_AWOR_CH0_SHIFT (0U) /*! AWOR_CH0 - Analog Watchdog Out of Range for Channel 0 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH0_SHIFT)) & ADC_AWORR0_AWOR_CH0_MASK) #define ADC_AWORR0_AWOR_CH1_MASK (0x2U) #define ADC_AWORR0_AWOR_CH1_SHIFT (1U) /*! AWOR_CH1 - Analog Watchdog Out of Range for Channel 1 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH1_SHIFT)) & ADC_AWORR0_AWOR_CH1_MASK) #define ADC_AWORR0_AWOR_CH2_MASK (0x4U) #define ADC_AWORR0_AWOR_CH2_SHIFT (2U) /*! AWOR_CH2 - Analog Watchdog Out of Range for Channel 2 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH2_SHIFT)) & ADC_AWORR0_AWOR_CH2_MASK) #define ADC_AWORR0_AWOR_CH3_MASK (0x8U) #define ADC_AWORR0_AWOR_CH3_SHIFT (3U) /*! AWOR_CH3 - Analog Watchdog Out of Range for Channel 3 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH3_SHIFT)) & ADC_AWORR0_AWOR_CH3_MASK) #define ADC_AWORR0_AWOR_CH4_MASK (0x10U) #define ADC_AWORR0_AWOR_CH4_SHIFT (4U) /*! AWOR_CH4 - Analog Watchdog Out of Range for Channel 4 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH4_SHIFT)) & ADC_AWORR0_AWOR_CH4_MASK) #define ADC_AWORR0_AWOR_CH5_MASK (0x20U) #define ADC_AWORR0_AWOR_CH5_SHIFT (5U) /*! AWOR_CH5 - Analog Watchdog Out of Range for Channel 5 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH5_SHIFT)) & ADC_AWORR0_AWOR_CH5_MASK) #define ADC_AWORR0_AWOR_CH6_MASK (0x40U) #define ADC_AWORR0_AWOR_CH6_SHIFT (6U) /*! AWOR_CH6 - Analog Watchdog Out of Range for Channel 6 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH6_SHIFT)) & ADC_AWORR0_AWOR_CH6_MASK) #define ADC_AWORR0_AWOR_CH7_MASK (0x80U) #define ADC_AWORR0_AWOR_CH7_SHIFT (7U) /*! AWOR_CH7 - Analog Watchdog Out of Range for Channel 7 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR0_AWOR_CH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR0_AWOR_CH7_SHIFT)) & ADC_AWORR0_AWOR_CH7_MASK) /*! @} */ /*! @name AWORR1 - Analog Watchdog Out of Range 1 */ /*! @{ */ #define ADC_AWORR1_AWOR_CH32_MASK (0x1U) #define ADC_AWORR1_AWOR_CH32_SHIFT (0U) /*! AWOR_CH32 - Analog Watchdog Out of Range for Channel 32 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH32(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH32_SHIFT)) & ADC_AWORR1_AWOR_CH32_MASK) #define ADC_AWORR1_AWOR_CH33_MASK (0x2U) #define ADC_AWORR1_AWOR_CH33_SHIFT (1U) /*! AWOR_CH33 - Analog Watchdog Out of Range for Channel 33 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH33(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH33_SHIFT)) & ADC_AWORR1_AWOR_CH33_MASK) #define ADC_AWORR1_AWOR_CH34_MASK (0x4U) #define ADC_AWORR1_AWOR_CH34_SHIFT (2U) /*! AWOR_CH34 - Analog Watchdog Out of Range for Channel 34 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH34(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH34_SHIFT)) & ADC_AWORR1_AWOR_CH34_MASK) #define ADC_AWORR1_AWOR_CH35_MASK (0x8U) #define ADC_AWORR1_AWOR_CH35_SHIFT (3U) /*! AWOR_CH35 - Analog Watchdog Out of Range for Channel 35 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH35(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH35_SHIFT)) & ADC_AWORR1_AWOR_CH35_MASK) #define ADC_AWORR1_AWOR_CH36_MASK (0x10U) #define ADC_AWORR1_AWOR_CH36_SHIFT (4U) /*! AWOR_CH36 - Analog Watchdog Out of Range for Channel 36 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH36(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH36_SHIFT)) & ADC_AWORR1_AWOR_CH36_MASK) #define ADC_AWORR1_AWOR_CH37_MASK (0x20U) #define ADC_AWORR1_AWOR_CH37_SHIFT (5U) /*! AWOR_CH37 - Analog Watchdog Out of Range for Channel 37 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH37(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH37_SHIFT)) & ADC_AWORR1_AWOR_CH37_MASK) #define ADC_AWORR1_AWOR_CH38_MASK (0x40U) #define ADC_AWORR1_AWOR_CH38_SHIFT (6U) /*! AWOR_CH38 - Analog Watchdog Out of Range for Channel 38 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH38(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH38_SHIFT)) & ADC_AWORR1_AWOR_CH38_MASK) #define ADC_AWORR1_AWOR_CH39_MASK (0x80U) #define ADC_AWORR1_AWOR_CH39_SHIFT (7U) /*! AWOR_CH39 - Analog Watchdog Out of Range for Channel 39 * 0b0..Converted data is in range * 0b1..Converted data is out of range * 0b0..No effect * 0b1..Clear the flag */ #define ADC_AWORR1_AWOR_CH39(x) (((uint32_t)(((uint32_t)(x)) << ADC_AWORR1_AWOR_CH39_SHIFT)) & ADC_AWORR1_AWOR_CH39_MASK) /*! @} */ /*! @name STCR1 - Self-Test Configuration 1 */ /*! @{ */ #define ADC_STCR1_INPSAMP_S_MASK (0xFF00U) #define ADC_STCR1_INPSAMP_S_SHIFT (8U) /*! INPSAMP_S - Sampling Configuration for Algorithm S */ #define ADC_STCR1_INPSAMP_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_S_SHIFT)) & ADC_STCR1_INPSAMP_S_MASK) #define ADC_STCR1_INPSAMP_C_MASK (0xFF000000U) #define ADC_STCR1_INPSAMP_C_SHIFT (24U) /*! INPSAMP_C - Sampling Configuration for Algorithm C */ #define ADC_STCR1_INPSAMP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR1_INPSAMP_C_SHIFT)) & ADC_STCR1_INPSAMP_C_MASK) /*! @} */ /*! @name STCR2 - Self-Test Configuration 2 */ /*! @{ */ #define ADC_STCR2_FMA_S_MASK (0x1U) #define ADC_STCR2_FMA_S_SHIFT (0U) /*! FMA_S - Fault Mapping for BGAP Algorithm * 0b0..NCF * 0b1..CF */ #define ADC_STCR2_FMA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_S_SHIFT)) & ADC_STCR2_FMA_S_MASK) #define ADC_STCR2_FMA_C_MASK (0x4U) #define ADC_STCR2_FMA_C_SHIFT (2U) /*! FMA_C - Fault Mapping for Algorithm C * 0b0..NCF * 0b1..CF */ #define ADC_STCR2_FMA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_C_SHIFT)) & ADC_STCR2_FMA_C_MASK) #define ADC_STCR2_FMA_WDTERR_MASK (0x8U) #define ADC_STCR2_FMA_WDTERR_SHIFT (3U) /*! FMA_WDTERR - Fault Mapping for Watchdog Timer Error * 0b0..NCF * 0b1..CF */ #define ADC_STCR2_FMA_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDTERR_SHIFT)) & ADC_STCR2_FMA_WDTERR_MASK) #define ADC_STCR2_FMA_WDSERR_MASK (0x10U) #define ADC_STCR2_FMA_WDSERR_SHIFT (4U) /*! FMA_WDSERR - Fault Mapping for Watchdog Sequence Error * 0b0..NCF mapping * 0b1..CF mapping */ #define ADC_STCR2_FMA_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_FMA_WDSERR_SHIFT)) & ADC_STCR2_FMA_WDSERR_MASK) #define ADC_STCR2_EN_MASK (0x80U) #define ADC_STCR2_EN_SHIFT (7U) /*! EN - Self-Testing Channel Enable * 0b0..Disable * 0b1..Enable */ #define ADC_STCR2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_EN_SHIFT)) & ADC_STCR2_EN_MASK) #define ADC_STCR2_MSKERR_S0_MASK (0x800U) #define ADC_STCR2_MSKERR_S0_SHIFT (11U) /*! MSKERR_S0 - Error on Algorithm S0 Channel Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S0_SHIFT)) & ADC_STCR2_MSKERR_S0_MASK) #define ADC_STCR2_MSKERR_S1_MASK (0x1000U) #define ADC_STCR2_MSKERR_S1_SHIFT (12U) /*! MSKERR_S1 - Error on Algorithm S1 Channel Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S1_SHIFT)) & ADC_STCR2_MSKERR_S1_MASK) #define ADC_STCR2_MSKERR_S2_MASK (0x2000U) #define ADC_STCR2_MSKERR_S2_SHIFT (13U) /*! MSKERR_S2 - Error on Algorithm S2 Channel Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_S2_SHIFT)) & ADC_STCR2_MSKERR_S2_MASK) #define ADC_STCR2_MSKERR_C_MASK (0x8000U) #define ADC_STCR2_MSKERR_C_SHIFT (15U) /*! MSKERR_C - Error on Algorithm C Channel Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKERR_C_SHIFT)) & ADC_STCR2_MSKERR_C_MASK) #define ADC_STCR2_MSKWDG_EOA_S_MASK (0x10000U) #define ADC_STCR2_MSKWDG_EOA_S_SHIFT (16U) /*! MSKWDG_EOA_S - End of Algorithm S Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKWDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_S_SHIFT)) & ADC_STCR2_MSKWDG_EOA_S_MASK) #define ADC_STCR2_MSKWDG_EOA_C_MASK (0x40000U) #define ADC_STCR2_MSKWDG_EOA_C_SHIFT (18U) /*! MSKWDG_EOA_C - End of Algorithm C Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKWDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDG_EOA_C_SHIFT)) & ADC_STCR2_MSKWDG_EOA_C_MASK) #define ADC_STCR2_MSKST_EOC_MASK (0x800000U) #define ADC_STCR2_MSKST_EOC_SHIFT (23U) /*! MSKST_EOC - Self-Test EOC Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKST_EOC_SHIFT)) & ADC_STCR2_MSKST_EOC_MASK) #define ADC_STCR2_MSKWDTERR_MASK (0x2000000U) #define ADC_STCR2_MSKWDTERR_SHIFT (25U) /*! MSKWDTERR - Watchdog Timer Error Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKWDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDTERR_SHIFT)) & ADC_STCR2_MSKWDTERR_MASK) #define ADC_STCR2_SERR_MASK (0x4000000U) #define ADC_STCR2_SERR_SHIFT (26U) /*! SERR - Error Fault Injection Field (write-only) */ #define ADC_STCR2_SERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_SERR_SHIFT)) & ADC_STCR2_SERR_MASK) #define ADC_STCR2_MSKWDSERR_MASK (0x8000000U) #define ADC_STCR2_MSKWDSERR_SHIFT (27U) /*! MSKWDSERR - Watchdog Sequence Error Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define ADC_STCR2_MSKWDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR2_MSKWDSERR_SHIFT)) & ADC_STCR2_MSKWDSERR_MASK) /*! @} */ /*! @name STCR3 - Self-Test Configuration 3 */ /*! @{ */ #define ADC_STCR3_MSTEP_MASK (0x1FU) #define ADC_STCR3_MSTEP_SHIFT (0U) /*! MSTEP - Self-Test Step Select */ #define ADC_STCR3_MSTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_MSTEP_SHIFT)) & ADC_STCR3_MSTEP_MASK) #define ADC_STCR3_ALG_MASK (0x300U) #define ADC_STCR3_ALG_SHIFT (8U) /*! ALG - Self-Test Algorithm Select * 0b00..Algorithm S * 0b01..Reserved * 0b10..Algorithm C * 0b11..Algorithm S (for One-Shot Operation mode); Algorithm S + C (for Scan Operation mode) */ #define ADC_STCR3_ALG(x) (((uint32_t)(((uint32_t)(x)) << ADC_STCR3_ALG_SHIFT)) & ADC_STCR3_ALG_MASK) /*! @} */ /*! @name STBRR - Self-Test Baud Rate */ /*! @{ */ #define ADC_STBRR_BR_MASK (0xFFU) #define ADC_STBRR_BR_SHIFT (0U) /*! BR - Algorithm Baud Rate */ #define ADC_STBRR_BR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_BR_SHIFT)) & ADC_STBRR_BR_MASK) #define ADC_STBRR_WDT_MASK (0x70000U) #define ADC_STBRR_WDT_SHIFT (16U) /*! WDT - Watchdog Timer Value * 0b000..0.1 ms ((0008h * Prescaler) cycles at 80 MHz) * 0b001..0.5 ms ((0027h * Prescaler) cycles at 80 MHz) * 0b010..1 ms ((004Eh * Prescaler) cycles at 80 MHz) * 0b011..2 ms ((009Ch * Prescaler) cycles at 80 MHz) * 0b100..5 ms ((0187h * Prescaler) cycles at 80 MHz) * 0b101..10 ms ((030Dh * Prescaler) cycles at 80 MHz) * 0b110..20 ms (061Ah * Prescaler) cycles at 80 MHz) * 0b111..50 ms (0F42h *Prescaler) cycles at 80 MHz) */ #define ADC_STBRR_WDT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STBRR_WDT_SHIFT)) & ADC_STBRR_WDT_MASK) /*! @} */ /*! @name STSR1 - Self-Test Status 1 */ /*! @{ */ #define ADC_STSR1_STEP_C_MASK (0x3E0U) #define ADC_STSR1_STEP_C_SHIFT (5U) /*! STEP_C - Algorithm C Step Number Error */ #define ADC_STSR1_STEP_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_STEP_C_SHIFT)) & ADC_STSR1_STEP_C_MASK) #define ADC_STSR1_ERR_S0_MASK (0x800U) #define ADC_STSR1_ERR_S0_SHIFT (11U) /*! ERR_S0 - Algorithm S0 Error * 0b0..No VREF error * 0b1..VREF error occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_ERR_S0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S0_SHIFT)) & ADC_STSR1_ERR_S0_MASK) #define ADC_STSR1_ERR_S1_MASK (0x1000U) #define ADC_STSR1_ERR_S1_SHIFT (12U) /*! ERR_S1 - Algorithm S1 Error * 0b0..No VDD ERROR * 0b1..VDD ERROR occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_ERR_S1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S1_SHIFT)) & ADC_STSR1_ERR_S1_MASK) #define ADC_STSR1_ERR_S2_MASK (0x2000U) #define ADC_STSR1_ERR_S2_SHIFT (13U) /*! ERR_S2 - Algorithm S2 Error * 0b0..No error occurred on the sampled signal * 0b1..Error occurred on the sampled signal * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_ERR_S2(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_S2_SHIFT)) & ADC_STSR1_ERR_S2_MASK) #define ADC_STSR1_ERR_C_MASK (0x8000U) #define ADC_STSR1_ERR_C_SHIFT (15U) /*! ERR_C - Algorithm C Error * 0b0..No Algorithm C error * 0b1..Algorithm C error occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_ERR_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ERR_C_SHIFT)) & ADC_STSR1_ERR_C_MASK) #define ADC_STSR1_WDG_EOA_S_MASK (0x10000U) #define ADC_STSR1_WDG_EOA_S_SHIFT (16U) /*! WDG_EOA_S - Watchdog End of Algorithm S * 0b0..Self-test end of Algorithm S conversion is not complete. * 0b1..Self-test end of Algorithm S conversion is complete. * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_WDG_EOA_S(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_S_SHIFT)) & ADC_STSR1_WDG_EOA_S_MASK) #define ADC_STSR1_WDG_EOA_C_MASK (0x40000U) #define ADC_STSR1_WDG_EOA_C_SHIFT (18U) /*! WDG_EOA_C - Watchdog End of Algorithm C * 0b0..Self-test end of Algorithm C conversion is not complete * 0b1..Self-test end of Algorithm C conversion is complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_WDG_EOA_C(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDG_EOA_C_SHIFT)) & ADC_STSR1_WDG_EOA_C_MASK) #define ADC_STSR1_ST_EOC_MASK (0x800000U) #define ADC_STSR1_ST_EOC_SHIFT (23U) /*! ST_EOC - Self-Test EOC * 0b0..Self-test end of conversion is not complete * 0b1..Self-test end of conversion is complete * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_ST_EOC(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_ST_EOC_SHIFT)) & ADC_STSR1_ST_EOC_MASK) #define ADC_STSR1_OVERWR_MASK (0x1000000U) #define ADC_STSR1_OVERWR_SHIFT (24U) /*! OVERWR - Overwrite Error * 0b0..No overwrite error * 0b1..Overwrite error occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_OVERWR_SHIFT)) & ADC_STSR1_OVERWR_MASK) #define ADC_STSR1_WDTERR_MASK (0x2000000U) #define ADC_STSR1_WDTERR_SHIFT (25U) /*! WDTERR - Watchdog Timer Error * 0b0..No failure * 0b1..Failure occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_WDTERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDTERR_SHIFT)) & ADC_STSR1_WDTERR_MASK) #define ADC_STSR1_WDSERR_MASK (0x8000000U) #define ADC_STSR1_WDSERR_SHIFT (27U) /*! WDSERR - Watchdog Sequence Errors * 0b0..No failure * 0b1..Failure occurred * 0b0..No effect * 0b1..Clear the flag */ #define ADC_STSR1_WDSERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR1_WDSERR_SHIFT)) & ADC_STSR1_WDSERR_MASK) /*! @} */ /*! @name STSR2 - Self-Test Status 2 */ /*! @{ */ #define ADC_STSR2_DATA0_MASK (0xFFFU) #define ADC_STSR2_DATA0_SHIFT (0U) /*! DATA0 - Test Channel Converted Data when ERR_S1 Occurred */ #define ADC_STSR2_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA0_SHIFT)) & ADC_STSR2_DATA0_MASK) #define ADC_STSR2_DATA1_MASK (0xFFF0000U) #define ADC_STSR2_DATA1_SHIFT (16U) /*! DATA1 - Test Channel Converted Data when ERR_S1 Occurred */ #define ADC_STSR2_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_DATA1_SHIFT)) & ADC_STSR2_DATA1_MASK) #define ADC_STSR2_OVFL_MASK (0x80000000U) #define ADC_STSR2_OVFL_SHIFT (31U) /*! OVFL - Overflow Bit * 0b0..Not overflow * 0b1..Overflow */ #define ADC_STSR2_OVFL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR2_OVFL_SHIFT)) & ADC_STSR2_OVFL_MASK) /*! @} */ /*! @name STSR3 - Self-Test Status 3 */ /*! @{ */ #define ADC_STSR3_DATA0_MASK (0xFFFU) #define ADC_STSR3_DATA0_SHIFT (0U) /*! DATA0 - Test Channel Converted Data when ERR_S0 Occurred */ #define ADC_STSR3_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA0_SHIFT)) & ADC_STSR3_DATA0_MASK) #define ADC_STSR3_DATA1_MASK (0xFFF0000U) #define ADC_STSR3_DATA1_SHIFT (16U) /*! DATA1 - Test Channel Converted Data when ERR_C Occurred */ #define ADC_STSR3_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR3_DATA1_SHIFT)) & ADC_STSR3_DATA1_MASK) /*! @} */ /*! @name STSR4 - Self-Test Status 4 */ /*! @{ */ #define ADC_STSR4_DATA1_MASK (0xFFF0000U) #define ADC_STSR4_DATA1_SHIFT (16U) /*! DATA1 - Test Channel Converted Data When ERR_C Occurred */ #define ADC_STSR4_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STSR4_DATA1_SHIFT)) & ADC_STSR4_DATA1_MASK) /*! @} */ /*! @name STDR1 - Self-Test Data 1 */ /*! @{ */ #define ADC_STDR1_TCDATA_MASK (0xFFFU) #define ADC_STDR1_TCDATA_SHIFT (0U) /*! TCDATA - Test Channel Converted Data */ #define ADC_STDR1_TCDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_TCDATA_SHIFT)) & ADC_STDR1_TCDATA_MASK) #define ADC_STDR1_OWERWR_MASK (0x40000U) #define ADC_STDR1_OWERWR_SHIFT (18U) /*! OWERWR - Overwrite Data * 0b0..Data not overwritten * 0b1..Data overwritten */ #define ADC_STDR1_OWERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_OWERWR_SHIFT)) & ADC_STDR1_OWERWR_MASK) #define ADC_STDR1_VALID_MASK (0x80000U) #define ADC_STDR1_VALID_SHIFT (19U) /*! VALID - Valid Data * 0b0..Data not valid * 0b1..Data valid */ #define ADC_STDR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR1_VALID_SHIFT)) & ADC_STDR1_VALID_MASK) /*! @} */ /*! @name STDR2 - Self-Test Data 2 */ /*! @{ */ #define ADC_STDR2_IDATA_MASK (0xFFFU) #define ADC_STDR2_IDATA_SHIFT (0U) /*! IDATA - Integer Data */ #define ADC_STDR2_IDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_IDATA_SHIFT)) & ADC_STDR2_IDATA_MASK) #define ADC_STDR2_OVERWR_MASK (0x40000U) #define ADC_STDR2_OVERWR_SHIFT (18U) /*! OVERWR - Overwrite Data * 0b0..Data not overwritten * 0b1..Data overwritten */ #define ADC_STDR2_OVERWR(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_OVERWR_SHIFT)) & ADC_STDR2_OVERWR_MASK) #define ADC_STDR2_VALID_MASK (0x80000U) #define ADC_STDR2_VALID_SHIFT (19U) /*! VALID - Valid Data * 0b0..Data not valid * 0b1..Data valid */ #define ADC_STDR2_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_VALID_SHIFT)) & ADC_STDR2_VALID_MASK) #define ADC_STDR2_FDATA_MASK (0xFFF00000U) #define ADC_STDR2_FDATA_SHIFT (20U) /*! FDATA - Fractional Data */ #define ADC_STDR2_FDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STDR2_FDATA_SHIFT)) & ADC_STDR2_FDATA_MASK) /*! @} */ /*! @name STAW0R - Self-Test Analog Watchdog 0 */ /*! @{ */ #define ADC_STAW0R_THRL_MASK (0xFFFU) #define ADC_STAW0R_THRL_SHIFT (0U) /*! THRL - Low Threshold Value for Algorithm S Step0 */ #define ADC_STAW0R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRL_SHIFT)) & ADC_STAW0R_THRL_MASK) #define ADC_STAW0R_THRH_MASK (0xFFF0000U) #define ADC_STAW0R_THRH_SHIFT (16U) /*! THRH - High Threshold Value for Algorithm S Step0 */ #define ADC_STAW0R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_THRH_SHIFT)) & ADC_STAW0R_THRH_MASK) #define ADC_STAW0R_WDTE_MASK (0x40000000U) #define ADC_STAW0R_WDTE_SHIFT (30U) /*! WDTE - Watchdog Timer Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_STAW0R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_WDTE_SHIFT)) & ADC_STAW0R_WDTE_MASK) #define ADC_STAW0R_AWDE_MASK (0x80000000U) #define ADC_STAW0R_AWDE_SHIFT (31U) /*! AWDE - Analog Watchdog Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_STAW0R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW0R_AWDE_SHIFT)) & ADC_STAW0R_AWDE_MASK) /*! @} */ /*! @name STAW1AR - Self-Test Analog Watchdog 1A */ /*! @{ */ #define ADC_STAW1AR_THRL_MASK (0xFFFU) #define ADC_STAW1AR_THRL_SHIFT (0U) /*! THRL - Low Threshold Value for Algorithm S Step1 */ #define ADC_STAW1AR_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRL_SHIFT)) & ADC_STAW1AR_THRL_MASK) #define ADC_STAW1AR_THRH_MASK (0xFFF0000U) #define ADC_STAW1AR_THRH_SHIFT (16U) /*! THRH - High Threshold Value for Algorithm S Step1 */ #define ADC_STAW1AR_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_THRH_SHIFT)) & ADC_STAW1AR_THRH_MASK) #define ADC_STAW1AR_AWDE_MASK (0x80000000U) #define ADC_STAW1AR_AWDE_SHIFT (31U) /*! AWDE - Analog Watchdog Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_STAW1AR_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1AR_AWDE_SHIFT)) & ADC_STAW1AR_AWDE_MASK) /*! @} */ /*! @name STAW1BR - Self-Test Analog Watchdog 1B */ /*! @{ */ #define ADC_STAW1BR_THRL_MASK (0xFFFU) #define ADC_STAW1BR_THRL_SHIFT (0U) /*! THRL - Low Threshold Value for Algorithm S Step1 */ #define ADC_STAW1BR_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRL_SHIFT)) & ADC_STAW1BR_THRL_MASK) #define ADC_STAW1BR_THRH_MASK (0xFFF0000U) #define ADC_STAW1BR_THRH_SHIFT (16U) /*! THRH - High Threshold Value for Algorithm S Step1 */ #define ADC_STAW1BR_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW1BR_THRH_SHIFT)) & ADC_STAW1BR_THRH_MASK) /*! @} */ /*! @name STAW2R - Self-Test Analog Watchdog 2 */ /*! @{ */ #define ADC_STAW2R_THRL_MASK (0xFFFU) #define ADC_STAW2R_THRL_SHIFT (0U) /*! THRL - Threshold level low */ #define ADC_STAW2R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_THRL_SHIFT)) & ADC_STAW2R_THRL_MASK) #define ADC_STAW2R_AWDE_MASK (0x80000000U) #define ADC_STAW2R_AWDE_SHIFT (31U) /*! AWDE - Analog Watchdog Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_STAW2R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW2R_AWDE_SHIFT)) & ADC_STAW2R_AWDE_MASK) /*! @} */ /*! @name STAW4R - Self-Test Analog Watchdog 4 */ /*! @{ */ #define ADC_STAW4R_THRL_MASK (0xFFFU) #define ADC_STAW4R_THRL_SHIFT (0U) /*! THRL - Low Threshold Value for Step0 of Algorithm C */ #define ADC_STAW4R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRL_SHIFT)) & ADC_STAW4R_THRL_MASK) #define ADC_STAW4R_THRH_MASK (0xFFF0000U) #define ADC_STAW4R_THRH_SHIFT (16U) /*! THRH - High Threshold Value for Step0 of Algorithm C */ #define ADC_STAW4R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_THRH_SHIFT)) & ADC_STAW4R_THRH_MASK) #define ADC_STAW4R_WDTE_MASK (0x40000000U) #define ADC_STAW4R_WDTE_SHIFT (30U) /*! WDTE - Watchdog Timer Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_STAW4R_WDTE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_WDTE_SHIFT)) & ADC_STAW4R_WDTE_MASK) #define ADC_STAW4R_AWDE_MASK (0x80000000U) #define ADC_STAW4R_AWDE_SHIFT (31U) /*! AWDE - Analog Watchdog Enable * 0b0..Disabled * 0b1..Enabled */ #define ADC_STAW4R_AWDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW4R_AWDE_SHIFT)) & ADC_STAW4R_AWDE_MASK) /*! @} */ /*! @name STAW5R - Self-Test Analog Watchdog 5 */ /*! @{ */ #define ADC_STAW5R_THRL_MASK (0xFFFU) #define ADC_STAW5R_THRL_SHIFT (0U) /*! THRL - Low Threshold Value for Step0 of Algorithm C */ #define ADC_STAW5R_THRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRL_SHIFT)) & ADC_STAW5R_THRL_MASK) #define ADC_STAW5R_THRH_MASK (0xFFF0000U) #define ADC_STAW5R_THRH_SHIFT (16U) /*! THRH - High Threshold Value for Step N of Algorithm C */ #define ADC_STAW5R_THRH(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAW5R_THRH_SHIFT)) & ADC_STAW5R_THRH_MASK) /*! @} */ /*! @name CALSTAT - Calibration Status */ /*! @{ */ #define ADC_CALSTAT_STAT_1_MASK (0x1U) #define ADC_CALSTAT_STAT_1_SHIFT (0U) /*! STAT_1 - Status of Calibration Step 1 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_1_SHIFT)) & ADC_CALSTAT_STAT_1_MASK) #define ADC_CALSTAT_STAT_2_MASK (0x2U) #define ADC_CALSTAT_STAT_2_SHIFT (1U) /*! STAT_2 - Status of Calibration Step 2 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_2_SHIFT)) & ADC_CALSTAT_STAT_2_MASK) #define ADC_CALSTAT_STAT_3_MASK (0x4U) #define ADC_CALSTAT_STAT_3_SHIFT (2U) /*! STAT_3 - Status of Calibration Step 3 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_3_SHIFT)) & ADC_CALSTAT_STAT_3_MASK) #define ADC_CALSTAT_STAT_4_MASK (0x8U) #define ADC_CALSTAT_STAT_4_SHIFT (3U) /*! STAT_4 - Status of calibration step 4 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_4_SHIFT)) & ADC_CALSTAT_STAT_4_MASK) #define ADC_CALSTAT_STAT_5_MASK (0x10U) #define ADC_CALSTAT_STAT_5_SHIFT (4U) /*! STAT_5 - Status of Calibration Step 5 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_5_SHIFT)) & ADC_CALSTAT_STAT_5_MASK) #define ADC_CALSTAT_STAT_6_MASK (0x20U) #define ADC_CALSTAT_STAT_6_SHIFT (5U) /*! STAT_6 - Status of Calibration Step 6 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_6_SHIFT)) & ADC_CALSTAT_STAT_6_MASK) #define ADC_CALSTAT_STAT_7_MASK (0x40U) #define ADC_CALSTAT_STAT_7_SHIFT (6U) /*! STAT_7 - Status of Calibration Step 7 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_7_SHIFT)) & ADC_CALSTAT_STAT_7_MASK) #define ADC_CALSTAT_STAT_8_MASK (0x80U) #define ADC_CALSTAT_STAT_8_SHIFT (7U) /*! STAT_8 - Status of Calibration Step 8 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_8_SHIFT)) & ADC_CALSTAT_STAT_8_MASK) #define ADC_CALSTAT_STAT_9_MASK (0x100U) #define ADC_CALSTAT_STAT_9_SHIFT (8U) /*! STAT_9 - Status of Calibration Step 9 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_9_SHIFT)) & ADC_CALSTAT_STAT_9_MASK) #define ADC_CALSTAT_STAT_10_MASK (0x200U) #define ADC_CALSTAT_STAT_10_SHIFT (9U) /*! STAT_10 - Status of Calibration Step 10 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_10_SHIFT)) & ADC_CALSTAT_STAT_10_MASK) #define ADC_CALSTAT_STAT_11_MASK (0x400U) #define ADC_CALSTAT_STAT_11_SHIFT (10U) /*! STAT_11 - Status of Calibration Step 11 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_11_SHIFT)) & ADC_CALSTAT_STAT_11_MASK) #define ADC_CALSTAT_STAT_12_MASK (0x800U) #define ADC_CALSTAT_STAT_12_SHIFT (11U) /*! STAT_12 - Status of Calibration Step 12 * 0b0..Test passed * 0b1..Test failed */ #define ADC_CALSTAT_STAT_12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_STAT_12_SHIFT)) & ADC_CALSTAT_STAT_12_MASK) #define ADC_CALSTAT_TEST_RESULT_MASK (0xFFFF0000U) #define ADC_CALSTAT_TEST_RESULT_SHIFT (16U) /*! TEST_RESULT - TEST_RESULT */ #define ADC_CALSTAT_TEST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALSTAT_TEST_RESULT_SHIFT)) & ADC_CALSTAT_TEST_RESULT_MASK) /*! @} */ /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ /** Peripheral ADC base address */ #define ADC_BASE (0x44530000u) /** Peripheral ADC base pointer */ #define ADC ((ADC_Type *)ADC_BASE) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC } /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ALIAS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ALIAS_Peripheral_Access_Layer ALIAS Peripheral Access Layer * @{ */ /** ALIAS - Register Layout Typedef */ typedef struct { __IO uint32_t ALIAS_REG[84]; /**< Alias Read Register, array offset: 0x0, array step: 0x4 */ } ALIAS_Type; /* ---------------------------------------------------------------------------- -- ALIAS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ALIAS_Register_Masks ALIAS Register Masks * @{ */ /*! @name ALIAS_REG - Alias Read Register */ /*! @{ */ #define ALIAS_ALIAS_REG_VAL_MASK (0xFFFFFFFFU) #define ALIAS_ALIAS_REG_VAL_SHIFT (0U) #define ALIAS_ALIAS_REG_VAL(x) (((uint32_t)(((uint32_t)(x)) << ALIAS_ALIAS_REG_VAL_SHIFT)) & ALIAS_ALIAS_REG_VAL_MASK) /*! @} */ /* The count of ALIAS_ALIAS_REG */ #define ALIAS_ALIAS_REG_COUNT (84U) /*! * @} */ /* end of group ALIAS_Register_Masks */ /* ALIAS - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__ALIAS base address */ #define CAMERA__ISP__ALIAS_BASE (0x4AE02000u) /** Peripheral CAMERA__ISP__ALIAS base pointer */ #define CAMERA__ISP__ALIAS ((ALIAS_Type *)CAMERA__ISP__ALIAS_BASE) /** Array initializer of ALIAS peripheral base addresses */ #define ALIAS_BASE_ADDRS { CAMERA__ISP__ALIAS_BASE } /** Array initializer of ALIAS peripheral base pointers */ #define ALIAS_BASE_PTRS { CAMERA__ISP__ALIAS } /*! * @} */ /* end of group ALIAS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_AGDET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_AGDET_Peripheral_Access_Layer ANALOG_AGDET Peripheral Access Layer * @{ */ /** ANALOG_AGDET - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t GD_TEST; /**< Glitch Detector Test Register, offset: 0x4 */ __IO uint32_t GD_MISC; /**< Glitch Detector MISC Register, offset: 0x8 */ uint8_t RESERVED_1[500]; __IO uint32_t GD_CTRL; /**< Glitch Detector Control Register, offset: 0x200 */ } ANALOG_AGDET_Type; /* ---------------------------------------------------------------------------- -- ANALOG_AGDET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_AGDET_Register_Masks ANALOG_AGDET Register Masks * @{ */ /*! @name GD_TEST - Glitch Detector Test Register */ /*! @{ */ #define ANALOG_AGDET_GD_TEST_TEST_EN_MASK (0x1U) #define ANALOG_AGDET_GD_TEST_TEST_EN_SHIFT (0U) /*! TEST_EN - Enable Signal Of Self-Test * 0b0..Disable glitch detector self-test * 0b1..Enable glitch detector self-test */ #define ANALOG_AGDET_GD_TEST_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_TEST_TEST_EN_SHIFT)) & ANALOG_AGDET_GD_TEST_TEST_EN_MASK) #define ANALOG_AGDET_GD_TEST_TEST_VOLTAGE_SEL_MASK (0xF0U) #define ANALOG_AGDET_GD_TEST_TEST_VOLTAGE_SEL_SHIFT (4U) /*! TEST_VOLTAGE_SEL - Test Glitch Voltage Selection * 0b0000..select the test glitch voltage 0 * 0b0001..select the test glitch voltage 1 * 0b0010..select the test glitch voltage 2 * 0b0011..select the test glitch voltage 3 * 0b0100..select the test glitch voltage 4 * 0b0101..select the test glitch voltage 5 * 0b0110..select the test glitch voltage 6 * 0b0111..select the test glitch voltage 7 * 0b1000..select the test glitch voltage 8 * 0b1001..select the test glitch voltage 9 * 0b1010..select the test glitch voltage 10 * 0b1011..select the test glitch voltage 11 * 0b1100..select the test glitch voltage 12 * 0b1101..select the test glitch voltage 13 * 0b1110..select the test glitch voltage 14 * 0b1111..select the test glitch voltage 15 */ #define ANALOG_AGDET_GD_TEST_TEST_VOLTAGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_TEST_TEST_VOLTAGE_SEL_SHIFT)) & ANALOG_AGDET_GD_TEST_TEST_VOLTAGE_SEL_MASK) #define ANALOG_AGDET_GD_TEST_TEST_DONE_MASK (0x100U) #define ANALOG_AGDET_GD_TEST_TEST_DONE_SHIFT (8U) /*! TEST_DONE - Self-Test Done * 0b0..Self-test is not done * 0b1..Self-test is done */ #define ANALOG_AGDET_GD_TEST_TEST_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_TEST_TEST_DONE_SHIFT)) & ANALOG_AGDET_GD_TEST_TEST_DONE_MASK) #define ANALOG_AGDET_GD_TEST_TEST_NEG_DETECTED_MASK (0x400U) #define ANALOG_AGDET_GD_TEST_TEST_NEG_DETECTED_SHIFT (10U) /*! TEST_NEG_DETECTED - Test Negative Glitch Detect Flag * 0b0..Neg edge is not detected during test * 0b1..Neg edge is detected during test */ #define ANALOG_AGDET_GD_TEST_TEST_NEG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_TEST_TEST_NEG_DETECTED_SHIFT)) & ANALOG_AGDET_GD_TEST_TEST_NEG_DETECTED_MASK) #define ANALOG_AGDET_GD_TEST_TEST_POS_DETECTED_MASK (0x800U) #define ANALOG_AGDET_GD_TEST_TEST_POS_DETECTED_SHIFT (11U) /*! TEST_POS_DETECTED - Test Positive Glitch Detect Flag * 0b0..Pos edge is not detected in during self-test * 0b1..Pos edge is detected in during self-test */ #define ANALOG_AGDET_GD_TEST_TEST_POS_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_TEST_TEST_POS_DETECTED_SHIFT)) & ANALOG_AGDET_GD_TEST_TEST_POS_DETECTED_MASK) #define ANALOG_AGDET_GD_TEST_TEST_SEL_MASK (0xF00000U) #define ANALOG_AGDET_GD_TEST_TEST_SEL_SHIFT (20U) /*! TEST_SEL - Test Mode Item Selection * 0b0000..Enter positive glitch self-test mode when GD_TEST[TEST_EN]=1 * 0b0001..Enter negative glitch self-test mode when GD_TEST[TEST_EN]=1 * 0b0010..BG bias current is conducted to ATX when GD_TEST[TEST_EN]=1 * 0b0011..Reserved * 0b0100..Negedge threshold is conducted to ATX when GD_TEST[TEST_EN]=1 * 0b0101..Posedge threshold is conducted to ATX when GD_TEST[TEST_EN]=1 * 0b0110..No function, for further extension * 0b0111..No function, for further extension * 0b1000..vddsoc is conducted to ATX when GD_TEST[TEST_EN]=1 */ #define ANALOG_AGDET_GD_TEST_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_TEST_TEST_SEL_SHIFT)) & ANALOG_AGDET_GD_TEST_TEST_SEL_MASK) #define ANALOG_AGDET_GD_TEST_TEST_DURATION_SEL_MASK (0xFF000000U) #define ANALOG_AGDET_GD_TEST_TEST_DURATION_SEL_SHIFT (24U) /*! TEST_DURATION_SEL - Test Duration Selection * 0b00000000..The duration of test glitch is configured to (3.3 x 1)ns * 0b00000001..The duration of test glitch is configured to (3.3 x 2)ns * 0b00000010..The duration of test glitch is configured to (3.3 x 3)ns * 0b00000011..The duration of test glitch is configured to (3.3 x 4)ns * 0b00000100..The duration of test glitch is configured to (3.3 x 5)ns * 0b00000101..The duration of test glitch is configured to (3.3 x 6)ns * 0b00000110..The duration of test glitch is configured to (3.3 x 7)ns * 0b00000111..The duration of test glitch is configured to (3.3 x 8)ns * 0b00001000..The duration of test glitch is configured to (3.3 x 9)ns * 0b00001001..The duration of test glitch is configured to (3.3 x 10)ns */ #define ANALOG_AGDET_GD_TEST_TEST_DURATION_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_TEST_TEST_DURATION_SEL_SHIFT)) & ANALOG_AGDET_GD_TEST_TEST_DURATION_SEL_MASK) /*! @} */ /*! @name GD_MISC - Glitch Detector MISC Register */ /*! @{ */ #define ANALOG_AGDET_GD_MISC_glitch_det_trim_MASK (0xFF000000U) #define ANALOG_AGDET_GD_MISC_glitch_det_trim_SHIFT (24U) /*! glitch_det_trim - Glitch Detector Trim * 0b00000000..Glitch_det_trim */ #define ANALOG_AGDET_GD_MISC_glitch_det_trim(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_MISC_glitch_det_trim_SHIFT)) & ANALOG_AGDET_GD_MISC_glitch_det_trim_MASK) /*! @} */ /*! @name GD_CTRL - Glitch Detector Control Register */ /*! @{ */ #define ANALOG_AGDET_GD_CTRL_ENABLE_MASK (0x1U) #define ANALOG_AGDET_GD_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - Enable Signal For Glitch Detector * 0b0..Glitch detector is disabled * 0b1..Glitch detector is enabled */ #define ANALOG_AGDET_GD_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_ENABLE_SHIFT)) & ANALOG_AGDET_GD_CTRL_ENABLE_MASK) #define ANALOG_AGDET_GD_CTRL_RST_LATCH_MASK (0x2U) #define ANALOG_AGDET_GD_CTRL_RST_LATCH_SHIFT (1U) /*! RST_LATCH - Reset Glitch Detector Output * 0b1..Write logic 1 to this bit resets the glitch detector output */ #define ANALOG_AGDET_GD_CTRL_RST_LATCH(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_RST_LATCH_SHIFT)) & ANALOG_AGDET_GD_CTRL_RST_LATCH_MASK) #define ANALOG_AGDET_GD_CTRL_TH_LO_TRIM_MASK (0xF00U) #define ANALOG_AGDET_GD_CTRL_TH_LO_TRIM_SHIFT (8U) /*! TH_LO_TRIM - Trim Code For Negative Edge Threshold * 0b0000..Sel trim code 0 for negative glitch threshold * 0b0001..Sel trim code 1 for negative glitch threshold * 0b0010..Sel trim code 2 for negative glitch threshold * 0b0011..Sel trim code 3 for negative glitch threshold * 0b0100..Sel trim code 4 for negative glitch threshold * 0b0101..Sel trim code 5 for negative glitch threshold * 0b0110..Sel trim code 6 for negative glitch threshold * 0b0111..Sel trim code 7 for negative glitch threshold * 0b1000..Sel trim code 8 for negative glitch threshold * 0b1001..Sel trim code 9 for negative glitch threshold * 0b1010..Sel trim code 10 for negative glitch threshold * 0b1011..Sel trim code 11 for negative glitch threshold * 0b1100..Sel trim code 12 for negative glitch threshold * 0b1101..Sel trim code 13 for negative glitch threshold * 0b1110..Sel trim code 14 for negative glitch threshold * 0b1111..Sel trim code 15 for negative glitch threshold */ #define ANALOG_AGDET_GD_CTRL_TH_LO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_TH_LO_TRIM_SHIFT)) & ANALOG_AGDET_GD_CTRL_TH_LO_TRIM_MASK) #define ANALOG_AGDET_GD_CTRL_TH_HI_TRIM_MASK (0xF000U) #define ANALOG_AGDET_GD_CTRL_TH_HI_TRIM_SHIFT (12U) /*! TH_HI_TRIM - Trim Code for Positive Edge Threshold * 0b0000..Sel trim code 0 for positive glitch threshold * 0b0001..Sel trim code 1 for positive glitch threshold * 0b0010..Sel trim code 2 for positive glitch threshold * 0b0011..Sel trim code 3 for positive glitch threshold * 0b0100..Sel trim code 4 for positive glitch threshold * 0b0101..Sel trim code 5 for positive glitch threshold * 0b0110..Sel trim code 6 for positive glitch threshold * 0b0111..Sel trim code 7 for positive glitch threshold * 0b1000..Sel trim code 8 for positive glitch threshold * 0b1001..Sel trim code 9 for positive glitch threshold * 0b1010..Sel trim code 10 for positive glitch threshold * 0b1011..Sel trim code 11 for positive glitch threshold * 0b1100..Sel trim code 12 for positive glitch threshold * 0b1101..Sel trim code 13 for positive glitch threshold * 0b1110..Sel trim code 14 for positive glitch threshold * 0b1111..Sel trim code 15 for positive glitch threshold */ #define ANALOG_AGDET_GD_CTRL_TH_HI_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_TH_HI_TRIM_SHIFT)) & ANALOG_AGDET_GD_CTRL_TH_HI_TRIM_MASK) #define ANALOG_AGDET_GD_CTRL_NEG_DETECTED_MASK (0x10000U) #define ANALOG_AGDET_GD_CTRL_NEG_DETECTED_SHIFT (16U) /*! NEG_DETECTED - Negedge Detected Flag * 0b0..Negedge is not detected on vdd_soc * 0b1..Negedge is detected on vdd_soc */ #define ANALOG_AGDET_GD_CTRL_NEG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_NEG_DETECTED_SHIFT)) & ANALOG_AGDET_GD_CTRL_NEG_DETECTED_MASK) #define ANALOG_AGDET_GD_CTRL_POS_DETECTED_MASK (0x20000U) #define ANALOG_AGDET_GD_CTRL_POS_DETECTED_SHIFT (17U) /*! POS_DETECTED - Posedge Detected Flag * 0b0..Posedge is not detected on vdd_soc * 0b1..Posedge is detected on vdd_soc */ #define ANALOG_AGDET_GD_CTRL_POS_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_POS_DETECTED_SHIFT)) & ANALOG_AGDET_GD_CTRL_POS_DETECTED_MASK) #define ANALOG_AGDET_GD_CTRL_NEG_DET_MASK_MASK (0x1000000U) #define ANALOG_AGDET_GD_CTRL_NEG_DET_MASK_SHIFT (24U) /*! NEG_DET_MASK - Mask the Negative Glitch Detection * 0b0..Detection is enabled * 0b1..Detection is disabled */ #define ANALOG_AGDET_GD_CTRL_NEG_DET_MASK(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_NEG_DET_MASK_SHIFT)) & ANALOG_AGDET_GD_CTRL_NEG_DET_MASK_MASK) #define ANALOG_AGDET_GD_CTRL_POS_DET_MASK_MASK (0x2000000U) #define ANALOG_AGDET_GD_CTRL_POS_DET_MASK_SHIFT (25U) /*! POS_DET_MASK - Mask the Positive Glitch Detection * 0b0..Detection is enabled * 0b1..Detection is disabled */ #define ANALOG_AGDET_GD_CTRL_POS_DET_MASK(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_POS_DET_MASK_SHIFT)) & ANALOG_AGDET_GD_CTRL_POS_DET_MASK_MASK) #define ANALOG_AGDET_GD_CTRL_AUTO_RST_MASK (0x10000000U) #define ANALOG_AGDET_GD_CTRL_AUTO_RST_SHIFT (28U) /*! AUTO_RST - Auto Reset Analog Latches After Enablement * 0b0..There is an auto reset on analog latches, before glitch detector is ready * 0b1..No internal analog latches reset */ #define ANALOG_AGDET_GD_CTRL_AUTO_RST(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_AGDET_GD_CTRL_AUTO_RST_SHIFT)) & ANALOG_AGDET_GD_CTRL_AUTO_RST_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_AGDET_Register_Masks */ /* ANALOG_AGDET - Peripheral instance base addresses */ /** Peripheral ANALOG__AGDET base address */ #define ANALOG__AGDET_BASE (0x44487000u) /** Peripheral ANALOG__AGDET base pointer */ #define ANALOG__AGDET ((ANALOG_AGDET_Type *)ANALOG__AGDET_BASE) /** Array initializer of ANALOG_AGDET peripheral base addresses */ #define ANALOG_AGDET_BASE_ADDRS { ANALOG__AGDET_BASE } /** Array initializer of ANALOG_AGDET peripheral base pointers */ #define ANALOG_AGDET_BASE_PTRS { ANALOG__AGDET } /*! * @} */ /* end of group ANALOG_AGDET_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_CMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_CMU_Peripheral_Access_Layer ANALOG_CMU Peripheral Access Layer * @{ */ /** ANALOG_CMU - Register Layout Typedef */ typedef struct { __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ __IO uint32_t SR; /**< Status Register, offset: 0x10 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ } ANALOG_CMU_Type; /* ---------------------------------------------------------------------------- -- ANALOG_CMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_CMU_Register_Masks ANALOG_CMU Register Masks * @{ */ /*! @name GCR - Global Configuration Register */ /*! @{ */ #define ANALOG_CMU_GCR_FCE_MASK (0x1U) #define ANALOG_CMU_GCR_FCE_SHIFT (0U) /*! FCE - Frequency Check Enable * 0b0..Stops frequency checking * 0b1..Starts frequency checking */ #define ANALOG_CMU_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_GCR_FCE_SHIFT)) & ANALOG_CMU_GCR_FCE_MASK) /*! @} */ /*! @name RCCR - Reference Count Configuration Register */ /*! @{ */ #define ANALOG_CMU_RCCR_REF_CNT_MASK (0xFFFFU) #define ANALOG_CMU_RCCR_REF_CNT_SHIFT (0U) /*! REF_CNT - Reference clock count */ #define ANALOG_CMU_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_RCCR_REF_CNT_SHIFT)) & ANALOG_CMU_RCCR_REF_CNT_MASK) /*! @} */ /*! @name HTCR - High Threshold Configuration Register */ /*! @{ */ #define ANALOG_CMU_HTCR_HFREF_MASK (0xFFFFFFU) #define ANALOG_CMU_HTCR_HFREF_SHIFT (0U) /*! HFREF - High frequency reference threshold */ #define ANALOG_CMU_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_HTCR_HFREF_SHIFT)) & ANALOG_CMU_HTCR_HFREF_MASK) /*! @} */ /*! @name LTCR - Low Threshold Configuration Register */ /*! @{ */ #define ANALOG_CMU_LTCR_LFREF_MASK (0xFFFFFFU) #define ANALOG_CMU_LTCR_LFREF_SHIFT (0U) /*! LFREF - Low Frequency Reference Threshold */ #define ANALOG_CMU_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_LTCR_LFREF_SHIFT)) & ANALOG_CMU_LTCR_LFREF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define ANALOG_CMU_SR_FLL_MASK (0x1U) #define ANALOG_CMU_SR_FLL_SHIFT (0U) /*! FLL - Frequency lower than low frequency reference threshold event status * 0b0..No FLL event * 0b1..FLL event occurred */ #define ANALOG_CMU_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_SR_FLL_SHIFT)) & ANALOG_CMU_SR_FLL_MASK) #define ANALOG_CMU_SR_FHH_MASK (0x2U) #define ANALOG_CMU_SR_FHH_SHIFT (1U) /*! FHH - Frequency higher than high frequency reference threshold event status * 0b0..No FHH event * 0b1..FHH event occurred */ #define ANALOG_CMU_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_SR_FHH_SHIFT)) & ANALOG_CMU_SR_FHH_MASK) #define ANALOG_CMU_SR_RS_MASK (0x10U) #define ANALOG_CMU_SR_RS_SHIFT (4U) /*! RS - Run Status * 0b0..Frequency check stopped * 0b1..Frequency check running */ #define ANALOG_CMU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_SR_RS_SHIFT)) & ANALOG_CMU_SR_RS_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define ANALOG_CMU_IER_FLLAIE_MASK (0x4U) #define ANALOG_CMU_IER_FLLAIE_SHIFT (2U) /*! FLLAIE - Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FLL event interrupt disabled * 0b1..Asynchronous FLL event interrupt enabled */ #define ANALOG_CMU_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_IER_FLLAIE_SHIFT)) & ANALOG_CMU_IER_FLLAIE_MASK) #define ANALOG_CMU_IER_FHHAIE_MASK (0x8U) #define ANALOG_CMU_IER_FHHAIE_SHIFT (3U) /*! FHHAIE - Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FHH event interrupt disabled * 0b1..Asynchronous FHH event interrupt enabled */ #define ANALOG_CMU_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_CMU_IER_FHHAIE_SHIFT)) & ANALOG_CMU_IER_FHHAIE_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_CMU_Register_Masks */ /* ANALOG_CMU - Peripheral instance base addresses */ /** Peripheral ANALOG__CMU0 base address */ #define ANALOG__CMU0_BASE (0x44670000u) /** Peripheral ANALOG__CMU0 base pointer */ #define ANALOG__CMU0 ((ANALOG_CMU_Type *)ANALOG__CMU0_BASE) /** Array initializer of ANALOG_CMU peripheral base addresses */ #define ANALOG_CMU_BASE_ADDRS { ANALOG__CMU0_BASE } /** Array initializer of ANALOG_CMU peripheral base pointers */ #define ANALOG_CMU_BASE_PTRS { ANALOG__CMU0 } /*! * @} */ /* end of group ANALOG_CMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_FRO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_FRO_Peripheral_Access_Layer ANALOG_FRO Peripheral Access Layer * @{ */ /** ANALOG_FRO - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[512]; struct { /* offset: 0x200 */ __IO uint32_t RW; /**< Control Status, offset: 0x200 */ __IO uint32_t SET; /**< Control Status, offset: 0x204 */ __IO uint32_t CLR; /**< Control Status, offset: 0x208 */ __IO uint32_t TOG; /**< Control Status, offset: 0x20C */ } CSR; struct { /* offset: 0x210 */ __IO uint32_t RW; /**< Trim Configuration 1, offset: 0x210 */ __IO uint32_t SET; /**< Trim Configuration 1, offset: 0x214 */ __IO uint32_t CLR; /**< Trim Configuration 1, offset: 0x218 */ __IO uint32_t TOG; /**< Trim Configuration 1, offset: 0x21C */ } CNFG1; struct { /* offset: 0x220 */ __IO uint32_t RW; /**< Trim Configuration 2, offset: 0x220 */ __IO uint32_t SET; /**< Trim Configuration 2, offset: 0x224 */ __IO uint32_t CLR; /**< Trim Configuration 2, offset: 0x228 */ __IO uint32_t TOG; /**< Trim Configuration 2, offset: 0x22C */ } CNFG2; struct { /* offset: 0x230 */ __IO uint32_t RW; /**< FRO Trim, offset: 0x230 */ __IO uint32_t SET; /**< FRO Trim, offset: 0x234 */ __IO uint32_t CLR; /**< FRO Trim, offset: 0x238 */ __IO uint32_t TOG; /**< FRO Trim, offset: 0x23C */ } FROTRIM; struct { /* offset: 0x240 */ __IO uint32_t RW; /**< FRO Expected Trim Count, offset: 0x240 */ __IO uint32_t SET; /**< FRO Expected Trim Count, offset: 0x244 */ __IO uint32_t CLR; /**< FRO Expected Trim Count, offset: 0x248 */ __IO uint32_t TOG; /**< FRO Expected Trim Count, offset: 0x24C */ } TEXPCNT; struct { /* offset: 0x250 */ __I uint32_t RW; /**< FRO Auto Tune Trim, offset: 0x250 */ __I uint32_t SET; /**< FRO Auto Tune Trim, offset: 0x254 */ __I uint32_t CLR; /**< FRO Auto Tune Trim, offset: 0x258 */ __I uint32_t TOG; /**< FRO Auto Tune Trim, offset: 0x25C */ } AUTOTRIM; struct { /* offset: 0x260 */ __I uint32_t RW; /**< FRO Trim Count, offset: 0x260 */ __I uint32_t SET; /**< FRO Trim Count, offset: 0x264 */ __I uint32_t CLR; /**< FRO Trim Count, offset: 0x268 */ __I uint32_t TOG; /**< FRO Trim Count, offset: 0x26C */ } TRIMCNT; } ANALOG_FRO_Type; /* ---------------------------------------------------------------------------- -- ANALOG_FRO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_FRO_Register_Masks ANALOG_FRO Register Masks * @{ */ /*! @name CSR - Control Status */ /*! @{ */ #define ANALOG_FRO_CSR_FROEN_MASK (0x1U) #define ANALOG_FRO_CSR_FROEN_SHIFT (0U) /*! FROEN - FRO Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CSR_FROEN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_FROEN_SHIFT)) & ANALOG_FRO_CSR_FROEN_MASK) #define ANALOG_FRO_CSR_SMODE_MASK (0x2U) #define ANALOG_FRO_CSR_SMODE_SHIFT (1U) /*! SMODE - Suspend Mode * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CSR_SMODE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_SMODE_SHIFT)) & ANALOG_FRO_CSR_SMODE_MASK) #define ANALOG_FRO_CSR_TREN_MASK (0x10U) #define ANALOG_FRO_CSR_TREN_SHIFT (4U) /*! TREN - FRO Trim Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CSR_TREN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_TREN_SHIFT)) & ANALOG_FRO_CSR_TREN_MASK) #define ANALOG_FRO_CSR_TRUPEN_MASK (0x20U) #define ANALOG_FRO_CSR_TRUPEN_SHIFT (5U) /*! TRUPEN - FRO Autotrim Update Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CSR_TRUPEN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_TRUPEN_SHIFT)) & ANALOG_FRO_CSR_TRUPEN_MASK) #define ANALOG_FRO_CSR_COARSEN_MASK (0x40U) #define ANALOG_FRO_CSR_COARSEN_SHIFT (6U) /*! COARSEN - Coarse Trim Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CSR_COARSEN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_COARSEN_SHIFT)) & ANALOG_FRO_CSR_COARSEN_MASK) #define ANALOG_FRO_CSR_TUNEONCE_MASK (0x80U) #define ANALOG_FRO_CSR_TUNEONCE_SHIFT (7U) /*! TUNEONCE - Tune Once Control */ #define ANALOG_FRO_CSR_TUNEONCE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_TUNEONCE_SHIFT)) & ANALOG_FRO_CSR_TUNEONCE_MASK) #define ANALOG_FRO_CSR_CLKGATE_MASK (0x1F00U) #define ANALOG_FRO_CSR_CLKGATE_SHIFT (8U) /*! CLKGATE - FRO Clock Enable * 0bxxxx0..Disables FRO divider 1 clock * 0bxxxx1..Enables FRO divider 1 clock * 0bxxx0x..Disables FRO divider 2 clock * 0bxxx1x..Enables FRO divider 2 clock * 0bxx0xx..Disables FRO divider 3 clock * 0bxx1xx..Enables FRO divider 3 clock * 0bx0xxx..Disables FRO divider 6 clock * 0bx1xxx..Enables FRO divider 6 clock * 0b0xxxx..Disables FRO divider 10 clock * 0b1xxxx..Enables FRO divider 10 clock */ #define ANALOG_FRO_CSR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_CLKGATE_SHIFT)) & ANALOG_FRO_CSR_CLKGATE_MASK) #define ANALOG_FRO_CSR_LOL_ERR_MASK (0x10000U) #define ANALOG_FRO_CSR_LOL_ERR_SHIFT (16U) /*! LOL_ERR - Loss-of-Lock Error Flag * 0b0..Not detected * 0b1..Detected */ #define ANALOG_FRO_CSR_LOL_ERR(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_LOL_ERR_SHIFT)) & ANALOG_FRO_CSR_LOL_ERR_MASK) #define ANALOG_FRO_CSR_TUNE_ERR_MASK (0x20000U) #define ANALOG_FRO_CSR_TUNE_ERR_SHIFT (17U) /*! TUNE_ERR - Tune Error Flag * 0b0..Not detected * 0b1..Detected */ #define ANALOG_FRO_CSR_TUNE_ERR(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_TUNE_ERR_SHIFT)) & ANALOG_FRO_CSR_TUNE_ERR_MASK) #define ANALOG_FRO_CSR_TRUPREQ_MASK (0x40000U) #define ANALOG_FRO_CSR_TRUPREQ_SHIFT (18U) /*! TRUPREQ - Trim Update Request Flag * 0b0..Not detected * 0b1..Detected */ #define ANALOG_FRO_CSR_TRUPREQ(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_TRUPREQ_SHIFT)) & ANALOG_FRO_CSR_TRUPREQ_MASK) #define ANALOG_FRO_CSR_TRIM_LOCK_MASK (0x1000000U) #define ANALOG_FRO_CSR_TRIM_LOCK_SHIFT (24U) /*! TRIM_LOCK - FRO Trim Lock Flag * 0b0..Not locked * 0b1..Locked */ #define ANALOG_FRO_CSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_TRIM_LOCK_SHIFT)) & ANALOG_FRO_CSR_TRIM_LOCK_MASK) #define ANALOG_FRO_CSR_TUNEONCE_DONE_MASK (0x2000000U) #define ANALOG_FRO_CSR_TUNEONCE_DONE_SHIFT (25U) /*! TUNEONCE_DONE - FRO Tune Once Done Flag * 0b0..Not complete * 0b1..Complete */ #define ANALOG_FRO_CSR_TUNEONCE_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CSR_TUNEONCE_DONE_SHIFT)) & ANALOG_FRO_CSR_TUNEONCE_DONE_MASK) /*! @} */ /*! @name CNFG1 - Trim Configuration 1 */ /*! @{ */ #define ANALOG_FRO_CNFG1_REFDIV_MASK (0x7FFU) #define ANALOG_FRO_CNFG1_REFDIV_SHIFT (0U) /*! REFDIV - OSC Reference Clock Divider */ #define ANALOG_FRO_CNFG1_REFDIV(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG1_REFDIV_SHIFT)) & ANALOG_FRO_CNFG1_REFDIV_MASK) #define ANALOG_FRO_CNFG1_FSTUPEN_MASK (0x800U) #define ANALOG_FRO_CNFG1_FSTUPEN_SHIFT (11U) /*! FSTUPEN - FRO Fast Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CNFG1_FSTUPEN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG1_FSTUPEN_SHIFT)) & ANALOG_FRO_CNFG1_FSTUPEN_MASK) #define ANALOG_FRO_CNFG1_LOL_ERR_IE_MASK (0x1000U) #define ANALOG_FRO_CNFG1_LOL_ERR_IE_SHIFT (12U) /*! LOL_ERR_IE - Loss-of-Lock Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CNFG1_LOL_ERR_IE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG1_LOL_ERR_IE_SHIFT)) & ANALOG_FRO_CNFG1_LOL_ERR_IE_MASK) #define ANALOG_FRO_CNFG1_TUNE_ERR_IE_MASK (0x2000U) #define ANALOG_FRO_CNFG1_TUNE_ERR_IE_SHIFT (13U) /*! TUNE_ERR_IE - Tune Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CNFG1_TUNE_ERR_IE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG1_TUNE_ERR_IE_SHIFT)) & ANALOG_FRO_CNFG1_TUNE_ERR_IE_MASK) #define ANALOG_FRO_CNFG1_TRUPREQ_IE_MASK (0x4000U) #define ANALOG_FRO_CNFG1_TRUPREQ_IE_SHIFT (14U) /*! TRUPREQ_IE - Trim Update Request Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ANALOG_FRO_CNFG1_TRUPREQ_IE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG1_TRUPREQ_IE_SHIFT)) & ANALOG_FRO_CNFG1_TRUPREQ_IE_MASK) #define ANALOG_FRO_CNFG1_RFCLKCNT_MASK (0xFFFF0000U) #define ANALOG_FRO_CNFG1_RFCLKCNT_SHIFT (16U) /*! RFCLKCNT - Reference Clock Counter */ #define ANALOG_FRO_CNFG1_RFCLKCNT(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG1_RFCLKCNT_SHIFT)) & ANALOG_FRO_CNFG1_RFCLKCNT_MASK) /*! @} */ /*! @name CNFG2 - Trim Configuration 2 */ /*! @{ */ #define ANALOG_FRO_CNFG2_FRODIV_MASK (0x7U) #define ANALOG_FRO_CNFG2_FRODIV_SHIFT (0U) /*! FRODIV - FRO Clock Divider */ #define ANALOG_FRO_CNFG2_FRODIV(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG2_FRODIV_SHIFT)) & ANALOG_FRO_CNFG2_FRODIV_MASK) #define ANALOG_FRO_CNFG2_CLKGATE_MASK (0x10U) #define ANALOG_FRO_CNFG2_CLKGATE_SHIFT (4U) /*! CLKGATE - FRO 8M Clock Gate Enable */ #define ANALOG_FRO_CNFG2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG2_CLKGATE_SHIFT)) & ANALOG_FRO_CNFG2_CLKGATE_MASK) #define ANALOG_FRO_CNFG2_TRIM1_DELAY_MASK (0xFFF0000U) #define ANALOG_FRO_CNFG2_TRIM1_DELAY_SHIFT (16U) /*! TRIM1_DELAY - Trim 1 Delay Register */ #define ANALOG_FRO_CNFG2_TRIM1_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_CNFG2_TRIM1_DELAY_SHIFT)) & ANALOG_FRO_CNFG2_TRIM1_DELAY_MASK) /*! @} */ /*! @name FROTRIM - FRO Trim */ /*! @{ */ #define ANALOG_FRO_FROTRIM_FINE_TRIM_MASK (0x7FU) #define ANALOG_FRO_FROTRIM_FINE_TRIM_SHIFT (0U) /*! FINE_TRIM - Fine Trim */ #define ANALOG_FRO_FROTRIM_FINE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_FROTRIM_FINE_TRIM_SHIFT)) & ANALOG_FRO_FROTRIM_FINE_TRIM_MASK) #define ANALOG_FRO_FROTRIM_COARSE_TRIM_MASK (0xF80U) #define ANALOG_FRO_FROTRIM_COARSE_TRIM_SHIFT (7U) /*! COARSE_TRIM - Coarse Trim */ #define ANALOG_FRO_FROTRIM_COARSE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_FROTRIM_COARSE_TRIM_SHIFT)) & ANALOG_FRO_FROTRIM_COARSE_TRIM_MASK) #define ANALOG_FRO_FROTRIM_TRIMTEMP_MASK (0x3F0000U) #define ANALOG_FRO_FROTRIM_TRIMTEMP_SHIFT (16U) /*! TRIMTEMP - Trim Temperature */ #define ANALOG_FRO_FROTRIM_TRIMTEMP(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_FROTRIM_TRIMTEMP_SHIFT)) & ANALOG_FRO_FROTRIM_TRIMTEMP_MASK) /*! @} */ /*! @name TEXPCNT - FRO Expected Trim Count */ /*! @{ */ #define ANALOG_FRO_TEXPCNT_TEXPCNT_MASK (0xFFFFU) #define ANALOG_FRO_TEXPCNT_TEXPCNT_SHIFT (0U) /*! TEXPCNT - Trim Expected Count */ #define ANALOG_FRO_TEXPCNT_TEXPCNT(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_TEXPCNT_TEXPCNT_SHIFT)) & ANALOG_FRO_TEXPCNT_TEXPCNT_MASK) #define ANALOG_FRO_TEXPCNT_TEXPCNT_RANGE_MASK (0xFF0000U) #define ANALOG_FRO_TEXPCNT_TEXPCNT_RANGE_SHIFT (16U) /*! TEXPCNT_RANGE - Trim Expected Count Range */ #define ANALOG_FRO_TEXPCNT_TEXPCNT_RANGE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_TEXPCNT_TEXPCNT_RANGE_SHIFT)) & ANALOG_FRO_TEXPCNT_TEXPCNT_RANGE_MASK) /*! @} */ /*! @name AUTOTRIM - FRO Auto Tune Trim */ /*! @{ */ #define ANALOG_FRO_AUTOTRIM_AUTOTRIM_MASK (0xFFFU) #define ANALOG_FRO_AUTOTRIM_AUTOTRIM_SHIFT (0U) /*! AUTOTRIM - Auto Tune Trim Value */ #define ANALOG_FRO_AUTOTRIM_AUTOTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_AUTOTRIM_AUTOTRIM_SHIFT)) & ANALOG_FRO_AUTOTRIM_AUTOTRIM_MASK) /*! @} */ /*! @name TRIMCNT - FRO Trim Count */ /*! @{ */ #define ANALOG_FRO_TRIMCNT_TRIMCNT_MASK (0xFFFFFFFFU) #define ANALOG_FRO_TRIMCNT_TRIMCNT_SHIFT (0U) /*! TRIMCNT - Trim Expected Count */ #define ANALOG_FRO_TRIMCNT_TRIMCNT(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_FRO_TRIMCNT_TRIMCNT_SHIFT)) & ANALOG_FRO_TRIMCNT_TRIMCNT_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_FRO_Register_Masks */ /* ANALOG_FRO - Peripheral instance base addresses */ /** Peripheral ANALOG__FRO base address */ #define ANALOG__FRO_BASE (0x44485000u) /** Peripheral ANALOG__FRO base pointer */ #define ANALOG__FRO ((ANALOG_FRO_Type *)ANALOG__FRO_BASE) /** Array initializer of ANALOG_FRO peripheral base addresses */ #define ANALOG_FRO_BASE_ADDRS { ANALOG__FRO_BASE } /** Array initializer of ANALOG_FRO peripheral base pointers */ #define ANALOG_FRO_BASE_PTRS { ANALOG__FRO } /*! * @} */ /* end of group ANALOG_FRO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_OSC24M Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_OSC24M_Peripheral_Access_Layer ANALOG_OSC24M Peripheral Access Layer * @{ */ /** ANALOG_OSC24M - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[2048]; __I uint32_t DIGPROG_DEVICE_ID; /**< Device ID, offset: 0x800 */ } ANALOG_OSC24M_Type; /* ---------------------------------------------------------------------------- -- ANALOG_OSC24M Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_OSC24M_Register_Masks ANALOG_OSC24M Register Masks * @{ */ /*! @name DIGPROG_DEVICE_ID - Device ID */ /*! @{ */ #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MINOR_MASK (0xFFU) #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MINOR_SHIFT (0U) /*! DIGPROG_MINOR - Bit[3:0] is the metal layer revision. Bit[7:4] is the base layer revision. */ #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MINOR_SHIFT)) & ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MINOR_MASK) #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_SHIFT (8U) /*! DIGPROG_MAJOR_LOWER - DIGPROG_MAJOR_LOWER */ #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_SHIFT)) & ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_LOWER_MASK) #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_SHIFT (16U) /*! DIGPROG_MAJOR_UPPER - DIGPROG_MAJOR_UPPER */ #define ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_SHIFT)) & ANALOG_OSC24M_DIGPROG_DEVICE_ID_DIGPROG_MAJOR_UPPER_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_OSC24M_Register_Masks */ /* ANALOG_OSC24M - Peripheral instance base addresses */ /** Peripheral ANALOG__OSC24M base address */ #define ANALOG__OSC24M_BASE (0x44480000u) /** Peripheral ANALOG__OSC24M base pointer */ #define ANALOG__OSC24M ((ANALOG_OSC24M_Type *)ANALOG__OSC24M_BASE) /** Array initializer of ANALOG_OSC24M peripheral base addresses */ #define ANALOG_OSC24M_BASE_ADDRS { ANALOG__OSC24M_BASE } /** Array initializer of ANALOG_OSC24M peripheral base pointers */ #define ANALOG_OSC24M_BASE_PTRS { ANALOG__OSC24M } /*! * @} */ /* end of group ANALOG_OSC24M_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_PMRO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_PMRO_Peripheral_Access_Layer ANALOG_PMRO Peripheral Access Layer * @{ */ /** ANALOG_PMRO - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL1; /**< Control Register CTRL, offset: 0x0 */ __IO uint32_t CTRL2; /**< Control Register CTRL2, offset: 0x4 */ } ANALOG_PMRO_Type; /* ---------------------------------------------------------------------------- -- ANALOG_PMRO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_PMRO_Register_Masks ANALOG_PMRO Register Masks * @{ */ /*! @name CTRL1 - Control Register CTRL */ /*! @{ */ #define ANALOG_PMRO_CTRL1_EN_MASK (0x3FFFFU) #define ANALOG_PMRO_CTRL1_EN_SHIFT (0U) /*! EN - 18 Dut Ring Oscillator enable */ #define ANALOG_PMRO_CTRL1_EN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_PMRO_CTRL1_EN_SHIFT)) & ANALOG_PMRO_CTRL1_EN_MASK) #define ANALOG_PMRO_CTRL1_DIV_MASK (0x7000000U) #define ANALOG_PMRO_CTRL1_DIV_SHIFT (24U) /*! DIV - Programmable Divider bits * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define ANALOG_PMRO_CTRL1_DIV(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_PMRO_CTRL1_DIV_SHIFT)) & ANALOG_PMRO_CTRL1_DIV_MASK) /*! @} */ /*! @name CTRL2 - Control Register CTRL2 */ /*! @{ */ #define ANALOG_PMRO_CTRL2_CLKGEN_MASK (0x3FFFFU) #define ANALOG_PMRO_CTRL2_CLKGEN_SHIFT (0U) /*! CLKGEN - 18 Dut Ring Oscillator (RO) Clock Gate enable */ #define ANALOG_PMRO_CTRL2_CLKGEN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_PMRO_CTRL2_CLKGEN_SHIFT)) & ANALOG_PMRO_CTRL2_CLKGEN_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_PMRO_Register_Masks */ /* ANALOG_PMRO - Peripheral instance base addresses */ /** Peripheral ANALOG__PMRO base address */ #define ANALOG__PMRO_BASE (0x44484000u) /** Peripheral ANALOG__PMRO base pointer */ #define ANALOG__PMRO ((ANALOG_PMRO_Type *)ANALOG__PMRO_BASE) /** Array initializer of ANALOG_PMRO peripheral base addresses */ #define ANALOG_PMRO_BASE_ADDRS { ANALOG__PMRO_BASE } /** Array initializer of ANALOG_PMRO peripheral base pointers */ #define ANALOG_PMRO_BASE_PTRS { ANALOG__PMRO } /*! * @} */ /* end of group ANALOG_PMRO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_SFA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_SFA_Peripheral_Access_Layer ANALOG_SFA Peripheral Access Layer * @{ */ /** ANALOG_SFA - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL; /**< Signal Frequency Analyser (SFA) Control, offset: 0x0 */ __IO uint32_t CTRL_EXT; /**< Signal Frequency Analyser (SFA) Control Extended, offset: 0x4 */ __IO uint32_t CNT_STAT; /**< Signal Frequency Analyser Count Status Register, offset: 0x8 */ __I uint32_t CUT_CNT; /**< Signal Frequency Analyser Clock Under Test Counter, offset: 0xC */ __I uint32_t REF_CNT; /**< Signal Frequency Analyser Reference Clock Counter, offset: 0x10 */ __IO uint32_t CUT_TARGET; /**< Signal Frequency Analyser Clock Under Test Target Count, offset: 0x14 */ __IO uint32_t REF_TARGET; /**< Signal Frequency Analyser Reference Clock Target Count, offset: 0x18 */ __I uint32_t REF_CNT_ST_SAVED; /**< Signal Frequency Analyser Reference Clock Count Start Saved Register, offset: 0x1C */ __I uint32_t REF_CNT_END_SAVED; /**< Signal Frequency Analyser Reference Clock Count End Saved Register, offset: 0x20 */ } ANALOG_SFA_Type; /* ---------------------------------------------------------------------------- -- ANALOG_SFA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_SFA_Register_Masks ANALOG_SFA Register Masks * @{ */ /*! @name CTRL - Signal Frequency Analyser (SFA) Control */ /*! @{ */ #define ANALOG_SFA_CTRL_MODE_MASK (0x3U) #define ANALOG_SFA_CTRL_MODE_SHIFT (0U) /*! MODE - MEASUREMENT MODE * 0b00..Frequency measurement performed with REF frequency > CUT Frequency. * 0b01..Frequency measurement performed with REF frequency < CUT Frequency. * 0b10..CUT period measurement performed. * 0b11..Trigger based measurement performed. Note, each trigger pulse must be held for at least 2 ref_clk cycles. */ #define ANALOG_SFA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_MODE_SHIFT)) & ANALOG_SFA_CTRL_MODE_MASK) #define ANALOG_SFA_CTRL_TRIG_START_POL_MASK (0x4U) #define ANALOG_SFA_CTRL_TRIG_START_POL_SHIFT (2U) /*! TRIG_START_POL - Trigger Start Polarity * 0b0..Rising edge of TRIGGER[TRIG_START_SEL] will begin the measurement sequence. * 0b1..Falling edge of TRIGGER[TRIG_START_SEL] will begin the measurement sequence. */ #define ANALOG_SFA_CTRL_TRIG_START_POL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_TRIG_START_POL_SHIFT)) & ANALOG_SFA_CTRL_TRIG_START_POL_MASK) #define ANALOG_SFA_CTRL_TRIG_END_POL_MASK (0x8U) #define ANALOG_SFA_CTRL_TRIG_END_POL_SHIFT (3U) /*! TRIG_END_POL - Trigger End Polarity * 0b0..Rising edge of TRIGER[TRIG_END_SEL] will end the measurement sequence. * 0b1..Falling edge of TRIGGER[TRIG_END_SEL] will end the measurement sequence. */ #define ANALOG_SFA_CTRL_TRIG_END_POL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_TRIG_END_POL_SHIFT)) & ANALOG_SFA_CTRL_TRIG_END_POL_MASK) #define ANALOG_SFA_CTRL_SFA_TRIG_MEAS_EN_MASK (0x10U) #define ANALOG_SFA_CTRL_SFA_TRIG_MEAS_EN_SHIFT (4U) /*! SFA_TRIG_MEAS_EN - SFA Triggered Measurement Enable * 0b0..The measurement will start by default with a dummy write to the REF and CUT counters. * 0b1..The measurement will start after receiging a dummy write to the REF_CNT followed by receiving the trigger * edge selected by TRIG_START_SEL and TRIG_START_POL. */ #define ANALOG_SFA_CTRL_SFA_TRIG_MEAS_EN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_SFA_TRIG_MEAS_EN_SHIFT)) & ANALOG_SFA_CTRL_SFA_TRIG_MEAS_EN_MASK) #define ANALOG_SFA_CTRL_SFA_IRQ_EN_MASK (0x20U) #define ANALOG_SFA_CTRL_SFA_IRQ_EN_SHIFT (5U) /*! SFA_IRQ_EN - SFA Interrupt Enable * 0b0..Interrupts are disabled. * 0b1..Interrupts are enabled. */ #define ANALOG_SFA_CTRL_SFA_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_SFA_IRQ_EN_SHIFT)) & ANALOG_SFA_CTRL_SFA_IRQ_EN_MASK) #define ANALOG_SFA_CTRL_SFA_EN_MASK (0x40U) #define ANALOG_SFA_CTRL_SFA_EN_SHIFT (6U) /*! SFA_EN - SFA Enable * 0b0..The SFA is disabled. * 0b1..The SFA is enabled. */ #define ANALOG_SFA_CTRL_SFA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_SFA_EN_SHIFT)) & ANALOG_SFA_CTRL_SFA_EN_MASK) #define ANALOG_SFA_CTRL_TRIG_START_SEL_MASK (0x100U) #define ANALOG_SFA_CTRL_TRIG_START_SEL_SHIFT (8U) /*! TRIG_START_SEL - Signal MUX For Trigger Based Measurement Start */ #define ANALOG_SFA_CTRL_TRIG_START_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_TRIG_START_SEL_SHIFT)) & ANALOG_SFA_CTRL_TRIG_START_SEL_MASK) #define ANALOG_SFA_CTRL_TRIG_END_SEL_MASK (0x1000U) #define ANALOG_SFA_CTRL_TRIG_END_SEL_SHIFT (12U) /*! TRIG_END_SEL - Signal MUX For Trigger Based Measurement End */ #define ANALOG_SFA_CTRL_TRIG_END_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_TRIG_END_SEL_SHIFT)) & ANALOG_SFA_CTRL_TRIG_END_SEL_MASK) #define ANALOG_SFA_CTRL_CUT_PREDIV_MASK (0xFF0000U) #define ANALOG_SFA_CTRL_CUT_PREDIV_SHIFT (16U) /*! CUT_PREDIV - CUT_PREDIV * 0b00000000..No Divide * 0b00000001..No Divide * 0b00000010..Divide by 2 * 0b00000011..Divide by 2 * 0b00000100..Divide by 4 * 0b00000101..Divide by 4 * 0b00000110..Divide by 6 * 0b00000111..Divide by 6 * 0b00001000..Divide by 8 * 0b00001001..Divide by 8 * 0b00001010-0b11111101..Divide by CUT_PREDIV - CUT_PREDIV%2 * 0b11111110..Divide by 254 * 0b11111111..Divide by 254 */ #define ANALOG_SFA_CTRL_CUT_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_CUT_PREDIV_SHIFT)) & ANALOG_SFA_CTRL_CUT_PREDIV_MASK) #define ANALOG_SFA_CTRL_CUT_SEL_MASK (0x1000000U) #define ANALOG_SFA_CTRL_CUT_SEL_SHIFT (24U) /*! CUT_SEL - CUT_SEL */ #define ANALOG_SFA_CTRL_CUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_CUT_SEL_SHIFT)) & ANALOG_SFA_CTRL_CUT_SEL_MASK) /*! @} */ /*! @name CTRL_EXT - Signal Frequency Analyser (SFA) Control Extended */ /*! @{ */ #define ANALOG_SFA_CTRL_EXT_CUT_CLK_EN_MASK (0x1U) #define ANALOG_SFA_CTRL_EXT_CUT_CLK_EN_SHIFT (0U) /*! CUT_CLK_EN - CUT_CLK_EN */ #define ANALOG_SFA_CTRL_EXT_CUT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_EXT_CUT_CLK_EN_SHIFT)) & ANALOG_SFA_CTRL_EXT_CUT_CLK_EN_MASK) #define ANALOG_SFA_CTRL_EXT_CUT_PIN_EN_MASK (0x10000U) #define ANALOG_SFA_CTRL_EXT_CUT_PIN_EN_SHIFT (16U) /*! CUT_PIN_EN - CUT_PIN_EN */ #define ANALOG_SFA_CTRL_EXT_CUT_PIN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CTRL_EXT_CUT_PIN_EN_SHIFT)) & ANALOG_SFA_CTRL_EXT_CUT_PIN_EN_MASK) /*! @} */ /*! @name CNT_STAT - Signal Frequency Analyser Count Status Register */ /*! @{ */ #define ANALOG_SFA_CNT_STAT_REF_STOPPED_MASK (0x1U) #define ANALOG_SFA_CNT_STAT_REF_STOPPED_SHIFT (0U) /*! REF_STOPPED - REF_STOPPED */ #define ANALOG_SFA_CNT_STAT_REF_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CNT_STAT_REF_STOPPED_SHIFT)) & ANALOG_SFA_CNT_STAT_REF_STOPPED_MASK) #define ANALOG_SFA_CNT_STAT_CUT_STOPPED_MASK (0x2U) #define ANALOG_SFA_CNT_STAT_CUT_STOPPED_SHIFT (1U) /*! CUT_STOPPED - CUT_STOPPED */ #define ANALOG_SFA_CNT_STAT_CUT_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CNT_STAT_CUT_STOPPED_SHIFT)) & ANALOG_SFA_CNT_STAT_CUT_STOPPED_MASK) #define ANALOG_SFA_CNT_STAT_MEAS_STARTED_MASK (0x4U) #define ANALOG_SFA_CNT_STAT_MEAS_STARTED_SHIFT (2U) /*! MEAS_STARTED - Measurement Started Flag */ #define ANALOG_SFA_CNT_STAT_MEAS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CNT_STAT_MEAS_STARTED_SHIFT)) & ANALOG_SFA_CNT_STAT_MEAS_STARTED_MASK) #define ANALOG_SFA_CNT_STAT_REF_CNT_TIMEOUT_MASK (0x8U) #define ANALOG_SFA_CNT_STAT_REF_CNT_TIMEOUT_SHIFT (3U) /*! REF_CNT_TIMEOUT - Reference Counter Time Out */ #define ANALOG_SFA_CNT_STAT_REF_CNT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CNT_STAT_REF_CNT_TIMEOUT_SHIFT)) & ANALOG_SFA_CNT_STAT_REF_CNT_TIMEOUT_MASK) #define ANALOG_SFA_CNT_STAT_SFA_IRQ_MASK (0x10U) #define ANALOG_SFA_CNT_STAT_SFA_IRQ_SHIFT (4U) /*! SFA_IRQ - SFA Interrupt Request */ #define ANALOG_SFA_CNT_STAT_SFA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CNT_STAT_SFA_IRQ_SHIFT)) & ANALOG_SFA_CNT_STAT_SFA_IRQ_MASK) /*! @} */ /*! @name CUT_CNT - Signal Frequency Analyser Clock Under Test Counter */ /*! @{ */ #define ANALOG_SFA_CUT_CNT_CUT_CNT_MASK (0xFFFFFFFFU) #define ANALOG_SFA_CUT_CNT_CUT_CNT_SHIFT (0U) /*! CUT_CNT - CUT_CNT */ #define ANALOG_SFA_CUT_CNT_CUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CUT_CNT_CUT_CNT_SHIFT)) & ANALOG_SFA_CUT_CNT_CUT_CNT_MASK) /*! @} */ /*! @name REF_CNT - Signal Frequency Analyser Reference Clock Counter */ /*! @{ */ #define ANALOG_SFA_REF_CNT_REF_CNT_MASK (0xFFFFFFFFU) #define ANALOG_SFA_REF_CNT_REF_CNT_SHIFT (0U) /*! REF_CNT - REF_CNT */ #define ANALOG_SFA_REF_CNT_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_REF_CNT_REF_CNT_SHIFT)) & ANALOG_SFA_REF_CNT_REF_CNT_MASK) /*! @} */ /*! @name CUT_TARGET - Signal Frequency Analyser Clock Under Test Target Count */ /*! @{ */ #define ANALOG_SFA_CUT_TARGET_CUT_TARGET_MASK (0xFFFFFFFFU) #define ANALOG_SFA_CUT_TARGET_CUT_TARGET_SHIFT (0U) /*! CUT_TARGET - CUT_TARGET */ #define ANALOG_SFA_CUT_TARGET_CUT_TARGET(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_CUT_TARGET_CUT_TARGET_SHIFT)) & ANALOG_SFA_CUT_TARGET_CUT_TARGET_MASK) /*! @} */ /*! @name REF_TARGET - Signal Frequency Analyser Reference Clock Target Count */ /*! @{ */ #define ANALOG_SFA_REF_TARGET_REF_TARGET_MASK (0xFFFFFFFFU) #define ANALOG_SFA_REF_TARGET_REF_TARGET_SHIFT (0U) /*! REF_TARGET - REF_TARGET */ #define ANALOG_SFA_REF_TARGET_REF_TARGET(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_REF_TARGET_REF_TARGET_SHIFT)) & ANALOG_SFA_REF_TARGET_REF_TARGET_MASK) /*! @} */ /*! @name REF_CNT_ST_SAVED - Signal Frequency Analyser Reference Clock Count Start Saved Register */ /*! @{ */ #define ANALOG_SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_MASK (0xFFFFFFFFU) #define ANALOG_SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_SHIFT (0U) /*! REF_CNT_ST_SAVED - REF_CNT_ST_SAVED */ #define ANALOG_SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_SHIFT)) & ANALOG_SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_MASK) /*! @} */ /*! @name REF_CNT_END_SAVED - Signal Frequency Analyser Reference Clock Count End Saved Register */ /*! @{ */ #define ANALOG_SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_MASK (0xFFFFFFFFU) #define ANALOG_SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_SHIFT (0U) /*! REF_CNT_END_SAVED - REF_CNT_END_SAVED */ #define ANALOG_SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_SHIFT)) & ANALOG_SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_SFA_Register_Masks */ /* ANALOG_SFA - Peripheral instance base addresses */ /** Peripheral ANALOG__SFA base address */ #define ANALOG__SFA_BASE (0x44483000u) /** Peripheral ANALOG__SFA base pointer */ #define ANALOG__SFA ((ANALOG_SFA_Type *)ANALOG__SFA_BASE) /** Array initializer of ANALOG_SFA peripheral base addresses */ #define ANALOG_SFA_BASE_ADDRS { ANALOG__SFA_BASE } /** Array initializer of ANALOG_SFA peripheral base pointers */ #define ANALOG_SFA_BASE_PTRS { ANALOG__SFA } /*! * @} */ /* end of group ANALOG_SFA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_TCU_Peripheral_Access_Layer ANALOG_TCU Peripheral Access Layer * @{ */ /** ANALOG_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[236]; __I uint32_t TCU_TEMPSENSER_MODE; /**< tempsenser expose test mode, offset: 0x500 */ uint8_t RESERVED_3[60]; __IO uint32_t TCU_CLK_MUXSEL; /**< clock sel, offset: 0x540 */ uint8_t RESERVED_4[12]; __IO uint32_t TCU_EXPOSE; /**< expose mode enable, offset: 0x550 */ uint8_t RESERVED_5[60]; __IO uint32_t TCU_ATX_SENSE_BUS_EN; /**< ATX sense bus enable, offset: 0x590 */ uint8_t RESERVED_6[1212]; struct { /* offset: 0xA50 */ __IO uint32_t RW; /**< ADC control register, offset: 0xA50 */ __IO uint32_t SET; /**< ADC control register, offset: 0xA54 */ __IO uint32_t CLR; /**< ADC control register, offset: 0xA58 */ __IO uint32_t TOG; /**< ADC control register, offset: 0xA5C */ } TCU_ADC_CONTROL_; uint8_t RESERVED_7[416]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_8[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } ANALOG_TCU_Type; /* ---------------------------------------------------------------------------- -- ANALOG_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_TCU_Register_Masks ANALOG_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & ANALOG_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_TEMPSENSER_MODE - tempsenser expose test mode */ /*! @{ */ #define ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_data_MASK (0xFFFFU) #define ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_data_SHIFT (0U) /*! ipt_temp_data - temperature data observation */ #define ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_data(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_data_SHIFT)) & ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_data_MASK) #define ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_valid_MASK (0x10000U) #define ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_valid_SHIFT (16U) /*! ipt_temp_valid - temperature data valid observation */ #define ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_valid(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_valid_SHIFT)) & ANALOG_TCU_TCU_TEMPSENSER_MODE_ipt_temp_valid_MASK) /*! @} */ /*! @name TCU_CLK_MUXSEL - clock sel */ /*! @{ */ #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_clk_src_mux_sel_MASK (0xFU) #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_clk_src_mux_sel_SHIFT (0U) /*! ipt_clk_src_mux_sel - clock source sel */ #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_clk_src_mux_sel(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_CLK_MUXSEL_ipt_clk_src_mux_sel_SHIFT)) & ANALOG_TCU_TCU_CLK_MUXSEL_ipt_clk_src_mux_sel_MASK) #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel1_MASK (0x30U) #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel1_SHIFT (4U) /*! ipt_osc_clkin_mux_sel1 - osc clkin1 sel */ #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel1(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel1_SHIFT)) & ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel1_MASK) #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel0_MASK (0xC0U) #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel0_SHIFT (6U) /*! ipt_osc_clkin_mux_sel0 - osc clkin0 sel */ #define ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel0(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel0_SHIFT)) & ANALOG_TCU_TCU_CLK_MUXSEL_ipt_osc_clkin_mux_sel0_MASK) /*! @} */ /*! @name TCU_EXPOSE - expose mode enable */ /*! @{ */ #define ANALOG_TCU_TCU_EXPOSE_tcu_expose_mode_MASK (0x1U) #define ANALOG_TCU_TCU_EXPOSE_tcu_expose_mode_SHIFT (0U) /*! tcu_expose_mode - dft fuse disable */ #define ANALOG_TCU_TCU_EXPOSE_tcu_expose_mode(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_EXPOSE_tcu_expose_mode_SHIFT)) & ANALOG_TCU_TCU_EXPOSE_tcu_expose_mode_MASK) /*! @} */ /*! @name TCU_ATX_SENSE_BUS_EN - ATX sense bus enable */ /*! @{ */ #define ANALOG_TCU_TCU_ATX_SENSE_BUS_EN_tcu_dft_atx_sense_bus_en_MASK (0x1U) #define ANALOG_TCU_TCU_ATX_SENSE_BUS_EN_tcu_dft_atx_sense_bus_en_SHIFT (0U) /*! tcu_dft_atx_sense_bus_en - ATX sense bus enable vdd_lv domain */ #define ANALOG_TCU_TCU_ATX_SENSE_BUS_EN_tcu_dft_atx_sense_bus_en(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_ATX_SENSE_BUS_EN_tcu_dft_atx_sense_bus_en_SHIFT)) & ANALOG_TCU_TCU_ATX_SENSE_BUS_EN_tcu_dft_atx_sense_bus_en_MASK) /*! @} */ /*! @name TCU_ADC_CONTROL_ - ADC control register */ /*! @{ */ #define ANALOG_TCU_TCU_ADC_CONTROL__adc_muxing_en_MASK (0x1U) #define ANALOG_TCU_TCU_ADC_CONTROL__adc_muxing_en_SHIFT (0U) /*! adc_muxing_en - ADC exposed mode iomux enable */ #define ANALOG_TCU_TCU_ADC_CONTROL__adc_muxing_en(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_ADC_CONTROL__adc_muxing_en_SHIFT)) & ANALOG_TCU_TCU_ADC_CONTROL__adc_muxing_en_MASK) #define ANALOG_TCU_TCU_ADC_CONTROL__adc_tst_wren_MASK (0x2U) #define ANALOG_TCU_TCU_ADC_CONTROL__adc_tst_wren_SHIFT (1U) /*! adc_tst_wren - test mode register write enable */ #define ANALOG_TCU_TCU_ADC_CONTROL__adc_tst_wren(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_ADC_CONTROL__adc_tst_wren_SHIFT)) & ANALOG_TCU_TCU_ADC_CONTROL__adc_tst_wren_MASK) #define ANALOG_TCU_TCU_ADC_CONTROL__adc_all_analog_pd_MASK (0x4U) #define ANALOG_TCU_TCU_ADC_CONTROL__adc_all_analog_pd_SHIFT (2U) /*! adc_all_analog_pd - Enables Powerdown cntrl by adc_adc_pd */ #define ANALOG_TCU_TCU_ADC_CONTROL__adc_all_analog_pd(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_ADC_CONTROL__adc_all_analog_pd_SHIFT)) & ANALOG_TCU_TCU_ADC_CONTROL__adc_all_analog_pd_MASK) #define ANALOG_TCU_TCU_ADC_CONTROL__adc_adc_pd_MASK (0x8U) #define ANALOG_TCU_TCU_ADC_CONTROL__adc_adc_pd_SHIFT (3U) /*! adc_adc_pd - Used to drive powerdown signal when adc_all_analog_pd is set */ #define ANALOG_TCU_TCU_ADC_CONTROL__adc_adc_pd(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_ADC_CONTROL__adc_adc_pd_SHIFT)) & ANALOG_TCU_TCU_ADC_CONTROL__adc_adc_pd_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & ANALOG_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & ANALOG_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & ANALOG_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & ANALOG_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & ANALOG_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define ANALOG_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & ANALOG_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define ANALOG_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define ANALOG_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define ANALOG_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & ANALOG_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define ANALOG_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0xEU) #define ANALOG_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define ANALOG_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & ANALOG_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_TCU_Register_Masks */ /* ANALOG_TCU - Peripheral instance base addresses */ /** Peripheral ANALOG__TCU base address */ #define ANALOG__TCU_BASE (0x444C0000u) /** Peripheral ANALOG__TCU base pointer */ #define ANALOG__TCU ((ANALOG_TCU_Type *)ANALOG__TCU_BASE) /** Array initializer of ANALOG_TCU peripheral base addresses */ #define ANALOG_TCU_BASE_ADDRS { ANALOG__TCU_BASE } /** Array initializer of ANALOG_TCU peripheral base pointers */ #define ANALOG_TCU_BASE_PTRS { ANALOG__TCU } /*! * @} */ /* end of group ANALOG_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_TRGMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_TRGMUX_Peripheral_Access_Layer ANALOG_TRGMUX Peripheral Access Layer * @{ */ /** ANALOG_TRGMUX - Register Layout Typedef */ typedef struct { __IO uint32_t REG0; /**< TRGMUX REG0, offset: 0x0 */ } ANALOG_TRGMUX_Type; /* ---------------------------------------------------------------------------- -- ANALOG_TRGMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_TRGMUX_Register_Masks ANALOG_TRGMUX Register Masks * @{ */ /*! @name REG0 - TRGMUX REG0 */ /*! @{ */ #define ANALOG_TRGMUX_REG0_SEL0_MASK (0xFU) #define ANALOG_TRGMUX_REG0_SEL0_SHIFT (0U) /*! SEL0 - TRGMUX Source Select 0 */ #define ANALOG_TRGMUX_REG0_SEL0(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TRGMUX_REG0_SEL0_SHIFT)) & ANALOG_TRGMUX_REG0_SEL0_MASK) #define ANALOG_TRGMUX_REG0_SEL1_MASK (0xF00U) #define ANALOG_TRGMUX_REG0_SEL1_SHIFT (8U) /*! SEL1 - TRGMUX Source Select 1 */ #define ANALOG_TRGMUX_REG0_SEL1(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TRGMUX_REG0_SEL1_SHIFT)) & ANALOG_TRGMUX_REG0_SEL1_MASK) #define ANALOG_TRGMUX_REG0_LK_MASK (0x80000000U) #define ANALOG_TRGMUX_REG0_LK_SHIFT (31U) /*! LK - TRGMUX Register Lock * 0b0..Register is writable * 0b1..Register is not writable until the next system reset */ #define ANALOG_TRGMUX_REG0_LK(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_TRGMUX_REG0_LK_SHIFT)) & ANALOG_TRGMUX_REG0_LK_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_TRGMUX_Register_Masks */ /* ANALOG_TRGMUX - Peripheral instance base addresses */ /** Peripheral ANALOG__TRGMUX base address */ #define ANALOG__TRGMUX_BASE (0x44531000u) /** Peripheral ANALOG__TRGMUX base pointer */ #define ANALOG__TRGMUX ((ANALOG_TRGMUX_Type *)ANALOG__TRGMUX_BASE) /** Array initializer of ANALOG_TRGMUX peripheral base addresses */ #define ANALOG_TRGMUX_BASE_ADDRS { ANALOG__TRGMUX_BASE } /** Array initializer of ANALOG_TRGMUX peripheral base pointers */ #define ANALOG_TRGMUX_BASE_PTRS { ANALOG__TRGMUX } /*! * @} */ /* end of group ANALOG_TRGMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ANALOG_VDET Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_VDET_Peripheral_Access_Layer ANALOG_VDET Peripheral Access Layer * @{ */ /** ANALOG_VDET - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[528]; __I uint32_t TRIM; /**< Trim Control, offset: 0x210 */ } ANALOG_VDET_Type; /* ---------------------------------------------------------------------------- -- ANALOG_VDET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ANALOG_VDET_Register_Masks ANALOG_VDET Register Masks * @{ */ /*! @name TRIM - Trim Control */ /*! @{ */ #define ANALOG_VDET_TRIM_CORE_HVD_TRIM_CTRL_LV_MASK (0x1FU) #define ANALOG_VDET_TRIM_CORE_HVD_TRIM_CTRL_LV_SHIFT (0U) /*! CORE_HVD_TRIM_CTRL_LV - Core HVD Threshold Value */ #define ANALOG_VDET_TRIM_CORE_HVD_TRIM_CTRL_LV(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_VDET_TRIM_CORE_HVD_TRIM_CTRL_LV_SHIFT)) & ANALOG_VDET_TRIM_CORE_HVD_TRIM_CTRL_LV_MASK) #define ANALOG_VDET_TRIM_CORE_LVD_TRIM_CTRL_LV_MASK (0x1F00U) #define ANALOG_VDET_TRIM_CORE_LVD_TRIM_CTRL_LV_SHIFT (8U) /*! CORE_LVD_TRIM_CTRL_LV - Core LVD Threshold Value */ #define ANALOG_VDET_TRIM_CORE_LVD_TRIM_CTRL_LV(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_VDET_TRIM_CORE_LVD_TRIM_CTRL_LV_SHIFT)) & ANALOG_VDET_TRIM_CORE_LVD_TRIM_CTRL_LV_MASK) #define ANALOG_VDET_TRIM_HV_LVD_TRIM_CTRL_LV_MASK (0x1F0000U) #define ANALOG_VDET_TRIM_HV_LVD_TRIM_CTRL_LV_SHIFT (16U) /*! HV_LVD_TRIM_CTRL_LV - Core HV LVD Threshold Value */ #define ANALOG_VDET_TRIM_HV_LVD_TRIM_CTRL_LV(x) (((uint32_t)(((uint32_t)(x)) << ANALOG_VDET_TRIM_HV_LVD_TRIM_CTRL_LV_SHIFT)) & ANALOG_VDET_TRIM_HV_LVD_TRIM_CTRL_LV_MASK) /*! @} */ /*! * @} */ /* end of group ANALOG_VDET_Register_Masks */ /* ANALOG_VDET - Peripheral instance base addresses */ /** Peripheral ANALOG__VDET base address */ #define ANALOG__VDET_BASE (0x44486000u) /** Peripheral ANALOG__VDET base pointer */ #define ANALOG__VDET ((ANALOG_VDET_Type *)ANALOG__VDET_BASE) /** Array initializer of ANALOG_VDET peripheral base addresses */ #define ANALOG_VDET_BASE_ADDRS { ANALOG__VDET_BASE } /** Array initializer of ANALOG_VDET peripheral base pointers */ #define ANALOG_VDET_BASE_PTRS { ANALOG__VDET } /*! * @} */ /* end of group ANALOG_VDET_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_AXBS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_AXBS_Peripheral_Access_Layer AON_AXBS Peripheral Access Layer * @{ */ /** AON_AXBS - Register Layout Typedef */ typedef struct { __IO uint32_t PRS0; /**< Priority Slave Registers, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t CRS0; /**< Control Register, offset: 0x10 */ uint8_t RESERVED_1[236]; __IO uint32_t PRS1; /**< Priority Slave Registers, offset: 0x100 */ uint8_t RESERVED_2[12]; __IO uint32_t CRS1; /**< Control Register, offset: 0x110 */ uint8_t RESERVED_3[236]; __IO uint32_t PRS2; /**< Priority Slave Registers, offset: 0x200 */ uint8_t RESERVED_4[12]; __IO uint32_t CRS2; /**< Control Register, offset: 0x210 */ uint8_t RESERVED_5[236]; __IO uint32_t PRS3; /**< Priority Slave Registers, offset: 0x300 */ uint8_t RESERVED_6[12]; __IO uint32_t CRS3; /**< Control Register, offset: 0x310 */ uint8_t RESERVED_7[236]; __IO uint32_t PRS4; /**< Priority Slave Registers, offset: 0x400 */ uint8_t RESERVED_8[12]; __IO uint32_t CRS4; /**< Control Register, offset: 0x410 */ uint8_t RESERVED_9[236]; __IO uint32_t PRS5; /**< Priority Slave Registers, offset: 0x500 */ uint8_t RESERVED_10[12]; __IO uint32_t CRS5; /**< Control Register, offset: 0x510 */ uint8_t RESERVED_11[236]; __IO uint32_t PRS6; /**< Priority Slave Registers, offset: 0x600 */ uint8_t RESERVED_12[12]; __IO uint32_t CRS6; /**< Control Register, offset: 0x610 */ uint8_t RESERVED_13[236]; __IO uint32_t PRS7; /**< Priority Slave Registers, offset: 0x700 */ uint8_t RESERVED_14[12]; __IO uint32_t CRS7; /**< Control Register, offset: 0x710 */ uint8_t RESERVED_15[236]; __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ uint8_t RESERVED_16[252]; __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ uint8_t RESERVED_17[252]; __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ uint8_t RESERVED_18[252]; __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ uint8_t RESERVED_19[252]; __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ uint8_t RESERVED_20[252]; __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ uint8_t RESERVED_21[252]; __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */ uint8_t RESERVED_22[252]; __IO uint32_t MGPCR7; /**< Master General Purpose Control Register, offset: 0xF00 */ } AON_AXBS_Type; /* ---------------------------------------------------------------------------- -- AON_AXBS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_AXBS_Register_Masks AON_AXBS Register Masks * @{ */ /*! @name PRS0 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS0_M0_MASK (0x7U) #define AON_AXBS_PRS0_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M0_SHIFT)) & AON_AXBS_PRS0_M0_MASK) #define AON_AXBS_PRS0_M1_MASK (0x70U) #define AON_AXBS_PRS0_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M1_SHIFT)) & AON_AXBS_PRS0_M1_MASK) #define AON_AXBS_PRS0_M2_MASK (0x700U) #define AON_AXBS_PRS0_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M2_SHIFT)) & AON_AXBS_PRS0_M2_MASK) #define AON_AXBS_PRS0_M3_MASK (0x7000U) #define AON_AXBS_PRS0_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M3_SHIFT)) & AON_AXBS_PRS0_M3_MASK) #define AON_AXBS_PRS0_M4_MASK (0x70000U) #define AON_AXBS_PRS0_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M4_SHIFT)) & AON_AXBS_PRS0_M4_MASK) #define AON_AXBS_PRS0_M5_MASK (0x700000U) #define AON_AXBS_PRS0_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M5_SHIFT)) & AON_AXBS_PRS0_M5_MASK) #define AON_AXBS_PRS0_M6_MASK (0x7000000U) #define AON_AXBS_PRS0_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M6_SHIFT)) & AON_AXBS_PRS0_M6_MASK) #define AON_AXBS_PRS0_M7_MASK (0x70000000U) #define AON_AXBS_PRS0_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS0_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS0_M7_SHIFT)) & AON_AXBS_PRS0_M7_MASK) /*! @} */ /*! @name CRS0 - Control Register */ /*! @{ */ #define AON_AXBS_CRS0_PARK_MASK (0x7U) #define AON_AXBS_CRS0_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS0_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_PARK_SHIFT)) & AON_AXBS_CRS0_PARK_MASK) #define AON_AXBS_CRS0_PCTL_MASK (0x30U) #define AON_AXBS_CRS0_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS0_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_PCTL_SHIFT)) & AON_AXBS_CRS0_PCTL_MASK) #define AON_AXBS_CRS0_ARB_MASK (0x300U) #define AON_AXBS_CRS0_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS0_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_ARB_SHIFT)) & AON_AXBS_CRS0_ARB_MASK) #define AON_AXBS_CRS0_HPE0_MASK (0x10000U) #define AON_AXBS_CRS0_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE0_SHIFT)) & AON_AXBS_CRS0_HPE0_MASK) #define AON_AXBS_CRS0_HPE1_MASK (0x20000U) #define AON_AXBS_CRS0_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE1_SHIFT)) & AON_AXBS_CRS0_HPE1_MASK) #define AON_AXBS_CRS0_HPE2_MASK (0x40000U) #define AON_AXBS_CRS0_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE2_SHIFT)) & AON_AXBS_CRS0_HPE2_MASK) #define AON_AXBS_CRS0_HPE3_MASK (0x80000U) #define AON_AXBS_CRS0_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE3_SHIFT)) & AON_AXBS_CRS0_HPE3_MASK) #define AON_AXBS_CRS0_HPE4_MASK (0x100000U) #define AON_AXBS_CRS0_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE4_SHIFT)) & AON_AXBS_CRS0_HPE4_MASK) #define AON_AXBS_CRS0_HPE5_MASK (0x200000U) #define AON_AXBS_CRS0_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE5_SHIFT)) & AON_AXBS_CRS0_HPE5_MASK) #define AON_AXBS_CRS0_HPE6_MASK (0x400000U) #define AON_AXBS_CRS0_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE6_SHIFT)) & AON_AXBS_CRS0_HPE6_MASK) #define AON_AXBS_CRS0_HPE7_MASK (0x800000U) #define AON_AXBS_CRS0_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS0_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HPE7_SHIFT)) & AON_AXBS_CRS0_HPE7_MASK) #define AON_AXBS_CRS0_HLP_MASK (0x40000000U) #define AON_AXBS_CRS0_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS0_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_HLP_SHIFT)) & AON_AXBS_CRS0_HLP_MASK) #define AON_AXBS_CRS0_RO_MASK (0x80000000U) #define AON_AXBS_CRS0_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS0_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS0_RO_SHIFT)) & AON_AXBS_CRS0_RO_MASK) /*! @} */ /*! @name PRS1 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS1_M0_MASK (0x7U) #define AON_AXBS_PRS1_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M0_SHIFT)) & AON_AXBS_PRS1_M0_MASK) #define AON_AXBS_PRS1_M1_MASK (0x70U) #define AON_AXBS_PRS1_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M1_SHIFT)) & AON_AXBS_PRS1_M1_MASK) #define AON_AXBS_PRS1_M2_MASK (0x700U) #define AON_AXBS_PRS1_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M2_SHIFT)) & AON_AXBS_PRS1_M2_MASK) #define AON_AXBS_PRS1_M3_MASK (0x7000U) #define AON_AXBS_PRS1_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M3_SHIFT)) & AON_AXBS_PRS1_M3_MASK) #define AON_AXBS_PRS1_M4_MASK (0x70000U) #define AON_AXBS_PRS1_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M4_SHIFT)) & AON_AXBS_PRS1_M4_MASK) #define AON_AXBS_PRS1_M5_MASK (0x700000U) #define AON_AXBS_PRS1_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M5_SHIFT)) & AON_AXBS_PRS1_M5_MASK) #define AON_AXBS_PRS1_M6_MASK (0x7000000U) #define AON_AXBS_PRS1_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M6_SHIFT)) & AON_AXBS_PRS1_M6_MASK) #define AON_AXBS_PRS1_M7_MASK (0x70000000U) #define AON_AXBS_PRS1_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS1_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS1_M7_SHIFT)) & AON_AXBS_PRS1_M7_MASK) /*! @} */ /*! @name CRS1 - Control Register */ /*! @{ */ #define AON_AXBS_CRS1_PARK_MASK (0x7U) #define AON_AXBS_CRS1_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS1_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_PARK_SHIFT)) & AON_AXBS_CRS1_PARK_MASK) #define AON_AXBS_CRS1_PCTL_MASK (0x30U) #define AON_AXBS_CRS1_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS1_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_PCTL_SHIFT)) & AON_AXBS_CRS1_PCTL_MASK) #define AON_AXBS_CRS1_ARB_MASK (0x300U) #define AON_AXBS_CRS1_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS1_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_ARB_SHIFT)) & AON_AXBS_CRS1_ARB_MASK) #define AON_AXBS_CRS1_HPE0_MASK (0x10000U) #define AON_AXBS_CRS1_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE0_SHIFT)) & AON_AXBS_CRS1_HPE0_MASK) #define AON_AXBS_CRS1_HPE1_MASK (0x20000U) #define AON_AXBS_CRS1_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE1_SHIFT)) & AON_AXBS_CRS1_HPE1_MASK) #define AON_AXBS_CRS1_HPE2_MASK (0x40000U) #define AON_AXBS_CRS1_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE2_SHIFT)) & AON_AXBS_CRS1_HPE2_MASK) #define AON_AXBS_CRS1_HPE3_MASK (0x80000U) #define AON_AXBS_CRS1_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE3_SHIFT)) & AON_AXBS_CRS1_HPE3_MASK) #define AON_AXBS_CRS1_HPE4_MASK (0x100000U) #define AON_AXBS_CRS1_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE4_SHIFT)) & AON_AXBS_CRS1_HPE4_MASK) #define AON_AXBS_CRS1_HPE5_MASK (0x200000U) #define AON_AXBS_CRS1_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE5_SHIFT)) & AON_AXBS_CRS1_HPE5_MASK) #define AON_AXBS_CRS1_HPE6_MASK (0x400000U) #define AON_AXBS_CRS1_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE6_SHIFT)) & AON_AXBS_CRS1_HPE6_MASK) #define AON_AXBS_CRS1_HPE7_MASK (0x800000U) #define AON_AXBS_CRS1_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS1_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HPE7_SHIFT)) & AON_AXBS_CRS1_HPE7_MASK) #define AON_AXBS_CRS1_HLP_MASK (0x40000000U) #define AON_AXBS_CRS1_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS1_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_HLP_SHIFT)) & AON_AXBS_CRS1_HLP_MASK) #define AON_AXBS_CRS1_RO_MASK (0x80000000U) #define AON_AXBS_CRS1_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS1_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS1_RO_SHIFT)) & AON_AXBS_CRS1_RO_MASK) /*! @} */ /*! @name PRS2 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS2_M0_MASK (0x7U) #define AON_AXBS_PRS2_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M0_SHIFT)) & AON_AXBS_PRS2_M0_MASK) #define AON_AXBS_PRS2_M1_MASK (0x70U) #define AON_AXBS_PRS2_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M1_SHIFT)) & AON_AXBS_PRS2_M1_MASK) #define AON_AXBS_PRS2_M2_MASK (0x700U) #define AON_AXBS_PRS2_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M2_SHIFT)) & AON_AXBS_PRS2_M2_MASK) #define AON_AXBS_PRS2_M3_MASK (0x7000U) #define AON_AXBS_PRS2_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M3_SHIFT)) & AON_AXBS_PRS2_M3_MASK) #define AON_AXBS_PRS2_M4_MASK (0x70000U) #define AON_AXBS_PRS2_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M4_SHIFT)) & AON_AXBS_PRS2_M4_MASK) #define AON_AXBS_PRS2_M5_MASK (0x700000U) #define AON_AXBS_PRS2_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M5_SHIFT)) & AON_AXBS_PRS2_M5_MASK) #define AON_AXBS_PRS2_M6_MASK (0x7000000U) #define AON_AXBS_PRS2_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M6_SHIFT)) & AON_AXBS_PRS2_M6_MASK) #define AON_AXBS_PRS2_M7_MASK (0x70000000U) #define AON_AXBS_PRS2_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS2_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS2_M7_SHIFT)) & AON_AXBS_PRS2_M7_MASK) /*! @} */ /*! @name CRS2 - Control Register */ /*! @{ */ #define AON_AXBS_CRS2_PARK_MASK (0x7U) #define AON_AXBS_CRS2_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS2_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_PARK_SHIFT)) & AON_AXBS_CRS2_PARK_MASK) #define AON_AXBS_CRS2_PCTL_MASK (0x30U) #define AON_AXBS_CRS2_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS2_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_PCTL_SHIFT)) & AON_AXBS_CRS2_PCTL_MASK) #define AON_AXBS_CRS2_ARB_MASK (0x300U) #define AON_AXBS_CRS2_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS2_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_ARB_SHIFT)) & AON_AXBS_CRS2_ARB_MASK) #define AON_AXBS_CRS2_HPE0_MASK (0x10000U) #define AON_AXBS_CRS2_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE0_SHIFT)) & AON_AXBS_CRS2_HPE0_MASK) #define AON_AXBS_CRS2_HPE1_MASK (0x20000U) #define AON_AXBS_CRS2_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE1_SHIFT)) & AON_AXBS_CRS2_HPE1_MASK) #define AON_AXBS_CRS2_HPE2_MASK (0x40000U) #define AON_AXBS_CRS2_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE2_SHIFT)) & AON_AXBS_CRS2_HPE2_MASK) #define AON_AXBS_CRS2_HPE3_MASK (0x80000U) #define AON_AXBS_CRS2_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE3_SHIFT)) & AON_AXBS_CRS2_HPE3_MASK) #define AON_AXBS_CRS2_HPE4_MASK (0x100000U) #define AON_AXBS_CRS2_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE4_SHIFT)) & AON_AXBS_CRS2_HPE4_MASK) #define AON_AXBS_CRS2_HPE5_MASK (0x200000U) #define AON_AXBS_CRS2_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE5_SHIFT)) & AON_AXBS_CRS2_HPE5_MASK) #define AON_AXBS_CRS2_HPE6_MASK (0x400000U) #define AON_AXBS_CRS2_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE6_SHIFT)) & AON_AXBS_CRS2_HPE6_MASK) #define AON_AXBS_CRS2_HPE7_MASK (0x800000U) #define AON_AXBS_CRS2_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS2_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HPE7_SHIFT)) & AON_AXBS_CRS2_HPE7_MASK) #define AON_AXBS_CRS2_HLP_MASK (0x40000000U) #define AON_AXBS_CRS2_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS2_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_HLP_SHIFT)) & AON_AXBS_CRS2_HLP_MASK) #define AON_AXBS_CRS2_RO_MASK (0x80000000U) #define AON_AXBS_CRS2_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS2_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS2_RO_SHIFT)) & AON_AXBS_CRS2_RO_MASK) /*! @} */ /*! @name PRS3 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS3_M0_MASK (0x7U) #define AON_AXBS_PRS3_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M0_SHIFT)) & AON_AXBS_PRS3_M0_MASK) #define AON_AXBS_PRS3_M1_MASK (0x70U) #define AON_AXBS_PRS3_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M1_SHIFT)) & AON_AXBS_PRS3_M1_MASK) #define AON_AXBS_PRS3_M2_MASK (0x700U) #define AON_AXBS_PRS3_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M2_SHIFT)) & AON_AXBS_PRS3_M2_MASK) #define AON_AXBS_PRS3_M3_MASK (0x7000U) #define AON_AXBS_PRS3_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M3_SHIFT)) & AON_AXBS_PRS3_M3_MASK) #define AON_AXBS_PRS3_M4_MASK (0x70000U) #define AON_AXBS_PRS3_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M4_SHIFT)) & AON_AXBS_PRS3_M4_MASK) #define AON_AXBS_PRS3_M5_MASK (0x700000U) #define AON_AXBS_PRS3_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M5_SHIFT)) & AON_AXBS_PRS3_M5_MASK) #define AON_AXBS_PRS3_M6_MASK (0x7000000U) #define AON_AXBS_PRS3_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M6_SHIFT)) & AON_AXBS_PRS3_M6_MASK) #define AON_AXBS_PRS3_M7_MASK (0x70000000U) #define AON_AXBS_PRS3_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS3_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS3_M7_SHIFT)) & AON_AXBS_PRS3_M7_MASK) /*! @} */ /*! @name CRS3 - Control Register */ /*! @{ */ #define AON_AXBS_CRS3_PARK_MASK (0x7U) #define AON_AXBS_CRS3_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS3_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_PARK_SHIFT)) & AON_AXBS_CRS3_PARK_MASK) #define AON_AXBS_CRS3_PCTL_MASK (0x30U) #define AON_AXBS_CRS3_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS3_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_PCTL_SHIFT)) & AON_AXBS_CRS3_PCTL_MASK) #define AON_AXBS_CRS3_ARB_MASK (0x300U) #define AON_AXBS_CRS3_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS3_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_ARB_SHIFT)) & AON_AXBS_CRS3_ARB_MASK) #define AON_AXBS_CRS3_HPE0_MASK (0x10000U) #define AON_AXBS_CRS3_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE0_SHIFT)) & AON_AXBS_CRS3_HPE0_MASK) #define AON_AXBS_CRS3_HPE1_MASK (0x20000U) #define AON_AXBS_CRS3_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE1_SHIFT)) & AON_AXBS_CRS3_HPE1_MASK) #define AON_AXBS_CRS3_HPE2_MASK (0x40000U) #define AON_AXBS_CRS3_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE2_SHIFT)) & AON_AXBS_CRS3_HPE2_MASK) #define AON_AXBS_CRS3_HPE3_MASK (0x80000U) #define AON_AXBS_CRS3_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE3_SHIFT)) & AON_AXBS_CRS3_HPE3_MASK) #define AON_AXBS_CRS3_HPE4_MASK (0x100000U) #define AON_AXBS_CRS3_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE4_SHIFT)) & AON_AXBS_CRS3_HPE4_MASK) #define AON_AXBS_CRS3_HPE5_MASK (0x200000U) #define AON_AXBS_CRS3_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE5_SHIFT)) & AON_AXBS_CRS3_HPE5_MASK) #define AON_AXBS_CRS3_HPE6_MASK (0x400000U) #define AON_AXBS_CRS3_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE6_SHIFT)) & AON_AXBS_CRS3_HPE6_MASK) #define AON_AXBS_CRS3_HPE7_MASK (0x800000U) #define AON_AXBS_CRS3_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS3_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HPE7_SHIFT)) & AON_AXBS_CRS3_HPE7_MASK) #define AON_AXBS_CRS3_HLP_MASK (0x40000000U) #define AON_AXBS_CRS3_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS3_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_HLP_SHIFT)) & AON_AXBS_CRS3_HLP_MASK) #define AON_AXBS_CRS3_RO_MASK (0x80000000U) #define AON_AXBS_CRS3_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS3_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS3_RO_SHIFT)) & AON_AXBS_CRS3_RO_MASK) /*! @} */ /*! @name PRS4 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS4_M0_MASK (0x7U) #define AON_AXBS_PRS4_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M0_SHIFT)) & AON_AXBS_PRS4_M0_MASK) #define AON_AXBS_PRS4_M1_MASK (0x70U) #define AON_AXBS_PRS4_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M1_SHIFT)) & AON_AXBS_PRS4_M1_MASK) #define AON_AXBS_PRS4_M2_MASK (0x700U) #define AON_AXBS_PRS4_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M2_SHIFT)) & AON_AXBS_PRS4_M2_MASK) #define AON_AXBS_PRS4_M3_MASK (0x7000U) #define AON_AXBS_PRS4_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M3_SHIFT)) & AON_AXBS_PRS4_M3_MASK) #define AON_AXBS_PRS4_M4_MASK (0x70000U) #define AON_AXBS_PRS4_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M4_SHIFT)) & AON_AXBS_PRS4_M4_MASK) #define AON_AXBS_PRS4_M5_MASK (0x700000U) #define AON_AXBS_PRS4_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M5_SHIFT)) & AON_AXBS_PRS4_M5_MASK) #define AON_AXBS_PRS4_M6_MASK (0x7000000U) #define AON_AXBS_PRS4_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M6_SHIFT)) & AON_AXBS_PRS4_M6_MASK) #define AON_AXBS_PRS4_M7_MASK (0x70000000U) #define AON_AXBS_PRS4_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS4_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS4_M7_SHIFT)) & AON_AXBS_PRS4_M7_MASK) /*! @} */ /*! @name CRS4 - Control Register */ /*! @{ */ #define AON_AXBS_CRS4_PARK_MASK (0x7U) #define AON_AXBS_CRS4_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS4_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_PARK_SHIFT)) & AON_AXBS_CRS4_PARK_MASK) #define AON_AXBS_CRS4_PCTL_MASK (0x30U) #define AON_AXBS_CRS4_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS4_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_PCTL_SHIFT)) & AON_AXBS_CRS4_PCTL_MASK) #define AON_AXBS_CRS4_ARB_MASK (0x300U) #define AON_AXBS_CRS4_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS4_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_ARB_SHIFT)) & AON_AXBS_CRS4_ARB_MASK) #define AON_AXBS_CRS4_HPE0_MASK (0x10000U) #define AON_AXBS_CRS4_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE0_SHIFT)) & AON_AXBS_CRS4_HPE0_MASK) #define AON_AXBS_CRS4_HPE1_MASK (0x20000U) #define AON_AXBS_CRS4_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE1_SHIFT)) & AON_AXBS_CRS4_HPE1_MASK) #define AON_AXBS_CRS4_HPE2_MASK (0x40000U) #define AON_AXBS_CRS4_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE2_SHIFT)) & AON_AXBS_CRS4_HPE2_MASK) #define AON_AXBS_CRS4_HPE3_MASK (0x80000U) #define AON_AXBS_CRS4_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE3_SHIFT)) & AON_AXBS_CRS4_HPE3_MASK) #define AON_AXBS_CRS4_HPE4_MASK (0x100000U) #define AON_AXBS_CRS4_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE4_SHIFT)) & AON_AXBS_CRS4_HPE4_MASK) #define AON_AXBS_CRS4_HPE5_MASK (0x200000U) #define AON_AXBS_CRS4_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE5_SHIFT)) & AON_AXBS_CRS4_HPE5_MASK) #define AON_AXBS_CRS4_HPE6_MASK (0x400000U) #define AON_AXBS_CRS4_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE6_SHIFT)) & AON_AXBS_CRS4_HPE6_MASK) #define AON_AXBS_CRS4_HPE7_MASK (0x800000U) #define AON_AXBS_CRS4_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS4_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HPE7_SHIFT)) & AON_AXBS_CRS4_HPE7_MASK) #define AON_AXBS_CRS4_HLP_MASK (0x40000000U) #define AON_AXBS_CRS4_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS4_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_HLP_SHIFT)) & AON_AXBS_CRS4_HLP_MASK) #define AON_AXBS_CRS4_RO_MASK (0x80000000U) #define AON_AXBS_CRS4_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS4_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS4_RO_SHIFT)) & AON_AXBS_CRS4_RO_MASK) /*! @} */ /*! @name PRS5 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS5_M0_MASK (0x7U) #define AON_AXBS_PRS5_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M0_SHIFT)) & AON_AXBS_PRS5_M0_MASK) #define AON_AXBS_PRS5_M1_MASK (0x70U) #define AON_AXBS_PRS5_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M1_SHIFT)) & AON_AXBS_PRS5_M1_MASK) #define AON_AXBS_PRS5_M2_MASK (0x700U) #define AON_AXBS_PRS5_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M2_SHIFT)) & AON_AXBS_PRS5_M2_MASK) #define AON_AXBS_PRS5_M3_MASK (0x7000U) #define AON_AXBS_PRS5_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M3_SHIFT)) & AON_AXBS_PRS5_M3_MASK) #define AON_AXBS_PRS5_M4_MASK (0x70000U) #define AON_AXBS_PRS5_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M4_SHIFT)) & AON_AXBS_PRS5_M4_MASK) #define AON_AXBS_PRS5_M5_MASK (0x700000U) #define AON_AXBS_PRS5_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M5_SHIFT)) & AON_AXBS_PRS5_M5_MASK) #define AON_AXBS_PRS5_M6_MASK (0x7000000U) #define AON_AXBS_PRS5_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M6_SHIFT)) & AON_AXBS_PRS5_M6_MASK) #define AON_AXBS_PRS5_M7_MASK (0x70000000U) #define AON_AXBS_PRS5_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS5_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS5_M7_SHIFT)) & AON_AXBS_PRS5_M7_MASK) /*! @} */ /*! @name CRS5 - Control Register */ /*! @{ */ #define AON_AXBS_CRS5_PARK_MASK (0x7U) #define AON_AXBS_CRS5_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS5_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_PARK_SHIFT)) & AON_AXBS_CRS5_PARK_MASK) #define AON_AXBS_CRS5_PCTL_MASK (0x30U) #define AON_AXBS_CRS5_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS5_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_PCTL_SHIFT)) & AON_AXBS_CRS5_PCTL_MASK) #define AON_AXBS_CRS5_ARB_MASK (0x300U) #define AON_AXBS_CRS5_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS5_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_ARB_SHIFT)) & AON_AXBS_CRS5_ARB_MASK) #define AON_AXBS_CRS5_HPE0_MASK (0x10000U) #define AON_AXBS_CRS5_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE0_SHIFT)) & AON_AXBS_CRS5_HPE0_MASK) #define AON_AXBS_CRS5_HPE1_MASK (0x20000U) #define AON_AXBS_CRS5_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE1_SHIFT)) & AON_AXBS_CRS5_HPE1_MASK) #define AON_AXBS_CRS5_HPE2_MASK (0x40000U) #define AON_AXBS_CRS5_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE2_SHIFT)) & AON_AXBS_CRS5_HPE2_MASK) #define AON_AXBS_CRS5_HPE3_MASK (0x80000U) #define AON_AXBS_CRS5_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE3_SHIFT)) & AON_AXBS_CRS5_HPE3_MASK) #define AON_AXBS_CRS5_HPE4_MASK (0x100000U) #define AON_AXBS_CRS5_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE4_SHIFT)) & AON_AXBS_CRS5_HPE4_MASK) #define AON_AXBS_CRS5_HPE5_MASK (0x200000U) #define AON_AXBS_CRS5_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE5_SHIFT)) & AON_AXBS_CRS5_HPE5_MASK) #define AON_AXBS_CRS5_HPE6_MASK (0x400000U) #define AON_AXBS_CRS5_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE6_SHIFT)) & AON_AXBS_CRS5_HPE6_MASK) #define AON_AXBS_CRS5_HPE7_MASK (0x800000U) #define AON_AXBS_CRS5_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS5_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HPE7_SHIFT)) & AON_AXBS_CRS5_HPE7_MASK) #define AON_AXBS_CRS5_HLP_MASK (0x40000000U) #define AON_AXBS_CRS5_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS5_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_HLP_SHIFT)) & AON_AXBS_CRS5_HLP_MASK) #define AON_AXBS_CRS5_RO_MASK (0x80000000U) #define AON_AXBS_CRS5_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS5_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS5_RO_SHIFT)) & AON_AXBS_CRS5_RO_MASK) /*! @} */ /*! @name PRS6 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS6_M0_MASK (0x7U) #define AON_AXBS_PRS6_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M0_SHIFT)) & AON_AXBS_PRS6_M0_MASK) #define AON_AXBS_PRS6_M1_MASK (0x70U) #define AON_AXBS_PRS6_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M1_SHIFT)) & AON_AXBS_PRS6_M1_MASK) #define AON_AXBS_PRS6_M2_MASK (0x700U) #define AON_AXBS_PRS6_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M2_SHIFT)) & AON_AXBS_PRS6_M2_MASK) #define AON_AXBS_PRS6_M3_MASK (0x7000U) #define AON_AXBS_PRS6_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M3_SHIFT)) & AON_AXBS_PRS6_M3_MASK) #define AON_AXBS_PRS6_M4_MASK (0x70000U) #define AON_AXBS_PRS6_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M4_SHIFT)) & AON_AXBS_PRS6_M4_MASK) #define AON_AXBS_PRS6_M5_MASK (0x700000U) #define AON_AXBS_PRS6_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M5_SHIFT)) & AON_AXBS_PRS6_M5_MASK) #define AON_AXBS_PRS6_M6_MASK (0x7000000U) #define AON_AXBS_PRS6_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M6_SHIFT)) & AON_AXBS_PRS6_M6_MASK) #define AON_AXBS_PRS6_M7_MASK (0x70000000U) #define AON_AXBS_PRS6_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS6_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS6_M7_SHIFT)) & AON_AXBS_PRS6_M7_MASK) /*! @} */ /*! @name CRS6 - Control Register */ /*! @{ */ #define AON_AXBS_CRS6_PARK_MASK (0x7U) #define AON_AXBS_CRS6_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS6_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_PARK_SHIFT)) & AON_AXBS_CRS6_PARK_MASK) #define AON_AXBS_CRS6_PCTL_MASK (0x30U) #define AON_AXBS_CRS6_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS6_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_PCTL_SHIFT)) & AON_AXBS_CRS6_PCTL_MASK) #define AON_AXBS_CRS6_ARB_MASK (0x300U) #define AON_AXBS_CRS6_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS6_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_ARB_SHIFT)) & AON_AXBS_CRS6_ARB_MASK) #define AON_AXBS_CRS6_HPE0_MASK (0x10000U) #define AON_AXBS_CRS6_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE0_SHIFT)) & AON_AXBS_CRS6_HPE0_MASK) #define AON_AXBS_CRS6_HPE1_MASK (0x20000U) #define AON_AXBS_CRS6_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE1_SHIFT)) & AON_AXBS_CRS6_HPE1_MASK) #define AON_AXBS_CRS6_HPE2_MASK (0x40000U) #define AON_AXBS_CRS6_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE2_SHIFT)) & AON_AXBS_CRS6_HPE2_MASK) #define AON_AXBS_CRS6_HPE3_MASK (0x80000U) #define AON_AXBS_CRS6_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE3_SHIFT)) & AON_AXBS_CRS6_HPE3_MASK) #define AON_AXBS_CRS6_HPE4_MASK (0x100000U) #define AON_AXBS_CRS6_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE4_SHIFT)) & AON_AXBS_CRS6_HPE4_MASK) #define AON_AXBS_CRS6_HPE5_MASK (0x200000U) #define AON_AXBS_CRS6_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE5_SHIFT)) & AON_AXBS_CRS6_HPE5_MASK) #define AON_AXBS_CRS6_HPE6_MASK (0x400000U) #define AON_AXBS_CRS6_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE6_SHIFT)) & AON_AXBS_CRS6_HPE6_MASK) #define AON_AXBS_CRS6_HPE7_MASK (0x800000U) #define AON_AXBS_CRS6_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS6_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HPE7_SHIFT)) & AON_AXBS_CRS6_HPE7_MASK) #define AON_AXBS_CRS6_HLP_MASK (0x40000000U) #define AON_AXBS_CRS6_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS6_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_HLP_SHIFT)) & AON_AXBS_CRS6_HLP_MASK) #define AON_AXBS_CRS6_RO_MASK (0x80000000U) #define AON_AXBS_CRS6_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS6_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS6_RO_SHIFT)) & AON_AXBS_CRS6_RO_MASK) /*! @} */ /*! @name PRS7 - Priority Slave Registers */ /*! @{ */ #define AON_AXBS_PRS7_M0_MASK (0x7U) #define AON_AXBS_PRS7_M0_SHIFT (0U) /*! M0 - Master 0 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or the lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M0_SHIFT)) & AON_AXBS_PRS7_M0_MASK) #define AON_AXBS_PRS7_M1_MASK (0x70U) #define AON_AXBS_PRS7_M1_SHIFT (4U) /*! M1 - Master 1 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M1_SHIFT)) & AON_AXBS_PRS7_M1_MASK) #define AON_AXBS_PRS7_M2_MASK (0x700U) #define AON_AXBS_PRS7_M2_SHIFT (8U) /*! M2 - Master 2 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M2_SHIFT)) & AON_AXBS_PRS7_M2_MASK) #define AON_AXBS_PRS7_M3_MASK (0x7000U) #define AON_AXBS_PRS7_M3_SHIFT (12U) /*! M3 - Master 3 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M3_SHIFT)) & AON_AXBS_PRS7_M3_MASK) #define AON_AXBS_PRS7_M4_MASK (0x70000U) #define AON_AXBS_PRS7_M4_SHIFT (16U) /*! M4 - Master 4 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M4_SHIFT)) & AON_AXBS_PRS7_M4_MASK) #define AON_AXBS_PRS7_M5_MASK (0x700000U) #define AON_AXBS_PRS7_M5_SHIFT (20U) /*! M5 - Master 5 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M5_SHIFT)) & AON_AXBS_PRS7_M5_MASK) #define AON_AXBS_PRS7_M6_MASK (0x7000000U) #define AON_AXBS_PRS7_M6_SHIFT (24U) /*! M6 - Master 6 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8the or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M6_SHIFT)) & AON_AXBS_PRS7_M6_MASK) #define AON_AXBS_PRS7_M7_MASK (0x70000000U) #define AON_AXBS_PRS7_M7_SHIFT (28U) /*! M7 - Master 7 Priority * 0b000..This master has level 1 or highest priority when accessing the slave port. * 0b001..This master has level 2 priority when accessing the slave port. * 0b010..This master has level 3 priority when accessing the slave port. * 0b011..This master has level 4 priority when accessing the slave port. * 0b100..This master has level 5 priority when accessing the slave port. * 0b101..This master has level 6 priority when accessing the slave port. * 0b110..This master has level 7 priority when accessing the slave port. * 0b111..This master has level 8 or lowest priority when accessing the slave port. */ #define AON_AXBS_PRS7_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_PRS7_M7_SHIFT)) & AON_AXBS_PRS7_M7_MASK) /*! @} */ /*! @name CRS7 - Control Register */ /*! @{ */ #define AON_AXBS_CRS7_PARK_MASK (0x7U) #define AON_AXBS_CRS7_PARK_SHIFT (0U) /*! PARK - Park * 0b000..Park on master port M0 * 0b001..Park on master port M1 * 0b010..Park on master port M2 * 0b011..Park on master port M3 * 0b100..Park on master port M4 * 0b101..Park on master port M5 * 0b110..Park on master port M6 * 0b111..Park on master port M7 */ #define AON_AXBS_CRS7_PARK(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_PARK_SHIFT)) & AON_AXBS_CRS7_PARK_MASK) #define AON_AXBS_CRS7_PCTL_MASK (0x30U) #define AON_AXBS_CRS7_PCTL_SHIFT (4U) /*! PCTL - Parking Control * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field. * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port. * 0b10..Low-power park. When no master makes a request, the slave port is not parked on a master and the arbiter * drives all outputs to a constant safe state. * 0b11..Reserved */ #define AON_AXBS_CRS7_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_PCTL_SHIFT)) & AON_AXBS_CRS7_PCTL_MASK) #define AON_AXBS_CRS7_ARB_MASK (0x300U) #define AON_AXBS_CRS7_ARB_SHIFT (8U) /*! ARB - Arbitration Mode * 0b00..Fixed priority * 0b01..Round-robin (rotating) priority * 0b10..Reserved * 0b11..Reserved */ #define AON_AXBS_CRS7_ARB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_ARB_SHIFT)) & AON_AXBS_CRS7_ARB_MASK) #define AON_AXBS_CRS7_HPE0_MASK (0x10000U) #define AON_AXBS_CRS7_HPE0_SHIFT (16U) /*! HPE0 - High Priority Elevation 0 * 0b0..Master high-priority elevation for master 0. is disabled on this slave port. * 0b1..Master high-priority elevation for master 0. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE0_SHIFT)) & AON_AXBS_CRS7_HPE0_MASK) #define AON_AXBS_CRS7_HPE1_MASK (0x20000U) #define AON_AXBS_CRS7_HPE1_SHIFT (17U) /*! HPE1 - High Priority Elevation 1 * 0b0..Master high-priority elevation for master 1. is disabled on this slave port. * 0b1..Master high-priority elevation for master 1. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE1_SHIFT)) & AON_AXBS_CRS7_HPE1_MASK) #define AON_AXBS_CRS7_HPE2_MASK (0x40000U) #define AON_AXBS_CRS7_HPE2_SHIFT (18U) /*! HPE2 - High Priority Elevation 2 * 0b0..Master high-priority elevation for master 2. is disabled on this slave port. * 0b1..Master high-priority elevation for master 2. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE2_SHIFT)) & AON_AXBS_CRS7_HPE2_MASK) #define AON_AXBS_CRS7_HPE3_MASK (0x80000U) #define AON_AXBS_CRS7_HPE3_SHIFT (19U) /*! HPE3 - High Priority Elevation 3 * 0b0..Master high-priority elevation for master 3. is disabled on this slave port. * 0b1..Master high-priority elevation for master 3. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE3_SHIFT)) & AON_AXBS_CRS7_HPE3_MASK) #define AON_AXBS_CRS7_HPE4_MASK (0x100000U) #define AON_AXBS_CRS7_HPE4_SHIFT (20U) /*! HPE4 - High Priority Elevation 4 * 0b0..Master high-priority elevation for master 4. is disabled on this slave port. * 0b1..Master high-priority elevation for master 4. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE4_SHIFT)) & AON_AXBS_CRS7_HPE4_MASK) #define AON_AXBS_CRS7_HPE5_MASK (0x200000U) #define AON_AXBS_CRS7_HPE5_SHIFT (21U) /*! HPE5 - High Priority Elevation 5 * 0b0..Master high-priority elevation for master 5. is disabled on this slave port. * 0b1..Master high-priority elevation for master 5. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE5_SHIFT)) & AON_AXBS_CRS7_HPE5_MASK) #define AON_AXBS_CRS7_HPE6_MASK (0x400000U) #define AON_AXBS_CRS7_HPE6_SHIFT (22U) /*! HPE6 - High Priority Elevation 6 * 0b0..Master high-priority elevation for master 6. is disabled on this slave port. * 0b1..Master high-priority elevation for master 6. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE6_SHIFT)) & AON_AXBS_CRS7_HPE6_MASK) #define AON_AXBS_CRS7_HPE7_MASK (0x800000U) #define AON_AXBS_CRS7_HPE7_SHIFT (23U) /*! HPE7 - High Priority Elevation 7 * 0b0..Master high-priority elevation for master 7. is disabled on this slave port. * 0b1..Master high-priority elevation for master 7. is enabled on this slave port. */ #define AON_AXBS_CRS7_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HPE7_SHIFT)) & AON_AXBS_CRS7_HPE7_MASK) #define AON_AXBS_CRS7_HLP_MASK (0x40000000U) #define AON_AXBS_CRS7_HLP_SHIFT (30U) /*! HLP - Halt Low Priority * 0b0..The low-power mode request has the highest priority for arbitration on this slave port. * 0b1..The low-power mode request has the lowest initial priority for arbitration on this slave port. */ #define AON_AXBS_CRS7_HLP(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_HLP_SHIFT)) & AON_AXBS_CRS7_HLP_MASK) #define AON_AXBS_CRS7_RO_MASK (0x80000000U) #define AON_AXBS_CRS7_RO_SHIFT (31U) /*! RO - Read Only * 0b0..The CRSn and PRSn registers are writeable * 0b1..The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect on the * registers and result in a bus error response). */ #define AON_AXBS_CRS7_RO(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_CRS7_RO_SHIFT)) & AON_AXBS_CRS7_RO_MASK) /*! @} */ /*! @name MGPCR0 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR0_AULB_MASK (0x7U) #define AON_AXBS_MGPCR0_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR0_AULB_SHIFT)) & AON_AXBS_MGPCR0_AULB_MASK) /*! @} */ /*! @name MGPCR1 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR1_AULB_MASK (0x7U) #define AON_AXBS_MGPCR1_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR1_AULB_SHIFT)) & AON_AXBS_MGPCR1_AULB_MASK) /*! @} */ /*! @name MGPCR2 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR2_AULB_MASK (0x7U) #define AON_AXBS_MGPCR2_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR2_AULB_SHIFT)) & AON_AXBS_MGPCR2_AULB_MASK) /*! @} */ /*! @name MGPCR3 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR3_AULB_MASK (0x7U) #define AON_AXBS_MGPCR3_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR3_AULB_SHIFT)) & AON_AXBS_MGPCR3_AULB_MASK) /*! @} */ /*! @name MGPCR4 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR4_AULB_MASK (0x7U) #define AON_AXBS_MGPCR4_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR4_AULB_SHIFT)) & AON_AXBS_MGPCR4_AULB_MASK) /*! @} */ /*! @name MGPCR5 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR5_AULB_MASK (0x7U) #define AON_AXBS_MGPCR5_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR5_AULB_SHIFT)) & AON_AXBS_MGPCR5_AULB_MASK) /*! @} */ /*! @name MGPCR6 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR6_AULB_MASK (0x7U) #define AON_AXBS_MGPCR6_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR6_AULB_SHIFT)) & AON_AXBS_MGPCR6_AULB_MASK) /*! @} */ /*! @name MGPCR7 - Master General Purpose Control Register */ /*! @{ */ #define AON_AXBS_MGPCR7_AULB_MASK (0x7U) #define AON_AXBS_MGPCR7_AULB_SHIFT (0U) /*! AULB - Arbitrates On Undefined Length Bursts * 0b000..No arbitration is allowed during an undefined length burst. * 0b001..Arbitration is allowed at any time during an undefined length burst. * 0b010..Arbitration is allowed after four beats of an undefined length burst. * 0b011..Arbitration is allowed after eight beats of an undefined length burst. * 0b100..Arbitration is allowed after 16 beats of an undefined length burst. * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define AON_AXBS_MGPCR7_AULB(x) (((uint32_t)(((uint32_t)(x)) << AON_AXBS_MGPCR7_AULB_SHIFT)) & AON_AXBS_MGPCR7_AULB_MASK) /*! @} */ /*! * @} */ /* end of group AON_AXBS_Register_Masks */ /* AON_AXBS - Peripheral instance base addresses */ /** Peripheral AON__AXBS base address */ #define AON__AXBS_BASE (0x44510000u) /** Peripheral AON__AXBS base pointer */ #define AON__AXBS ((AON_AXBS_Type *)AON__AXBS_BASE) /** Array initializer of AON_AXBS peripheral base addresses */ #define AON_AXBS_BASE_ADDRS { AON__AXBS_BASE } /** Array initializer of AON_AXBS peripheral base pointers */ #define AON_AXBS_BASE_PTRS { AON__AXBS } /*! * @} */ /* end of group AON_AXBS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_BLK_CTRL_NS_AONMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer AON_BLK_CTRL_NS_AONMIX Peripheral Access Layer * @{ */ /** AON_BLK_CTRL_NS_AONMIX - Register Layout Typedef */ typedef struct { __IO uint32_t GPC_CFG; /**< GPC CORE SLEEP Request Select, offset: 0x0 */ __IO uint32_t UPPER_ADDR; /**< UPPER ADDR BITS[35:32], offset: 0x4 */ __IO uint32_t IPG_DEBUG_CM33; /**< IPG DEBUG MASK BIT for cm33, offset: 0x8 */ __IO uint32_t IPG_DEBUG_CA55C0; /**< IPG DEBUG MASK BIT CA55 CORE0, offset: 0xC */ __IO uint32_t IPG_DEBUG_CA55C1; /**< IPG DEBUG MASK BIT CA55 CORE1, offset: 0x10 */ __IO uint32_t IPG_DEBUG_CA55C2; /**< IPG DEBUG MASK BIT CA55 CORE2, offset: 0x14 */ __IO uint32_t IPG_DEBUG_CA55C3; /**< IPG DEBUG MASK BIT CA55 CORE3, offset: 0x18 */ __IO uint32_t IPG_DEBUG_CA55C4; /**< IPG DEBUG MASK BIT CA55 CORE4, offset: 0x1C */ __IO uint32_t IPG_DEBUG_CA55C5; /**< IPG DEBUG MASK BIT CA55 CORE5, offset: 0x20 */ __IO uint32_t IPG_DEBUG_CM7; /**< IPG DEBUG MASK BIT for cm7, offset: 0x24 */ __I uint32_t FUSE_ACC_DIS; /**< Read-only version of the OCOTP fuse-access-disable bit, offset: 0x28 */ uint8_t RESERVED_0[4]; __I uint32_t OCOTP_FUSE_DATA0; /**< Read-only version of OCOTP fusedata_mtr_cfg_0, offset: 0x30 */ __I uint32_t OCOTP_FUSE_DATA1; /**< Read-only version of OCOTP fusedata_mtr_cfg_1, offset: 0x34 */ __I uint32_t OCOTP_FUSE_DATA2; /**< Read-only version of OCOTP fusedata_mtr_cfg_2, offset: 0x38 */ __I uint32_t OCOTP_FUSE_DATA3; /**< Read-only version of OCOTP fusedata_mtr_cfg_3, offset: 0x3C */ __I uint32_t OCOTP_FUSE_DATA4; /**< Read-only version of OCOTP fusedata_mtr_cfg_4, offset: 0x40 */ __I uint32_t OCOTP_FUSE_DATA5; /**< Read-only version of OCOTP fusedata_mtr_cfg_5, offset: 0x44 */ __I uint32_t OCOTP_FUSE_DATA6; /**< Read-only version of OCOTP fusedata_mtr_cfg_6, offset: 0x48 */ __I uint32_t OCOTP_FUSE_DATA7; /**< Read-only version of OCOTP fusedata_mtr_cfg_7, offset: 0x4C */ __I uint32_t OCOTP_FUSE_DATA8; /**< Read-only version of OCOTP fusedata_mem_trim_cfg0, offset: 0x50 */ __I uint32_t OCOTP_FUSE_DATA9; /**< Read-only version of OCOTP fusedata_mem_trim_cfg1, offset: 0x54 */ __I uint32_t OCOTP_FUSE_DATA10; /**< Read-only version of OCOTP fusedata_mem_trim_cfg2, offset: 0x58 */ __I uint32_t OCOTP_FUSE_DATA11; /**< Read-only version of OCOTP fusedata_mem_trim_cfg3, offset: 0x5C */ __I uint32_t OCOTP_FUSE_DATA12; /**< Read-only version of OCOTP fusedata_mem_trim_cfg4, offset: 0x60 */ __I uint32_t OCOTP_FUSE_DATA13; /**< Read-only version of OCOTP fusedata_mem_trim_cfg5, offset: 0x64 */ __I uint32_t OCOTP_FUSE_DATA14; /**< Read-only version of OCOTP fusedata_mem_trim_cfg6, offset: 0x68 */ __I uint32_t OCOTP_FUSE_DATA15; /**< Read-only version of OCOTP fusedata_mem_trim_cfg7, offset: 0x6C */ __IO uint32_t I3C1_WAKEUP; /**< I3C1 WAKEUPX CLR, offset: 0x70 */ __I uint32_t OCOTP_STATUS; /**< OCOTP status register, offset: 0x74 */ __IO uint32_t PDM_CLK_SEL; /**< PDM clock selection register, offset: 0x78 */ __IO uint32_t I3C1_SDA_IRQ; /**< I3C1 SDA IRQ, offset: 0x7C */ __IO uint32_t SSI; /**< SSI master low power mode control, offset: 0x80 */ __I uint32_t FASTBOOT_ENABLE; /**< fastboot enable, offset: 0x84 */ __IO uint32_t MQS_SETTINGS; /**< MQS settings, offset: 0x88 */ __I uint32_t ELE_FW_PRESENT; /**< Read only bit for fuse ELE_FW_PRESENT, offset: 0x8C */ __I uint32_t AOMIX_SPARE_FUSE; /**< Spare fuse register, offset: 0x90 */ __IO uint32_t IPG_STOP_CTL; /**< IPG_STOP Control Register, offset: 0x94 */ __I uint32_t IPG_STOP_ACK_STATUS; /**< IPG_STOP_ACK Status Register, offset: 0x98 */ __IO uint32_t IPG_DOZE_CTL; /**< IPG_DOZE_CTL Control Register, offset: 0x9C */ __IO uint32_t QREQ_N; /**< QREQ_N Control Register, offset: 0xA0 */ __IO uint32_t SAI_MCLK; /**< SAI1 MCLK Control Register, offset: 0xA4 */ __I uint32_t QACTIVE; /**< QACTIVE Status Register, offset: 0xA8 */ __I uint32_t QDENY; /**< QDENY Status Register, offset: 0xAC */ __I uint32_t QACCEPT_N; /**< QACCEPT_N Status Register, offset: 0xB0 */ } AON_BLK_CTRL_NS_AONMIX_Type; /* ---------------------------------------------------------------------------- -- AON_BLK_CTRL_NS_AONMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_BLK_CTRL_NS_AONMIX_Register_Masks AON_BLK_CTRL_NS_AONMIX Register Masks * @{ */ /*! @name GPC_CFG - GPC CORE SLEEP Request Select */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_SHIFT (0U) /*! M33_SLEEP_SEL - M33 SLEEP Request Select * 0b0..Select SLEEPING as request source * 0b1..Select SLEEPDEEP as request source */ #define AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M33_SLEEP_SEL_MASK) #define AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_SHIFT (1U) /*! M7_SLEEP_SEL - M7 SLEEP Request Select * 0b1..Select SLEEPDEEP as request source * 0b0..Select SLEEPING as request source */ #define AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_GPC_CFG_M7_SLEEP_SEL_MASK) /*! @} */ /*! @name UPPER_ADDR - UPPER ADDR BITS[35:32] */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_ELE_MASK (0xFU) #define AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_ELE_SHIFT (0U) /*! ELE - address bit [35:32] for ELE */ #define AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_ELE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_ELE_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_ELE_MASK) #define AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_edma1_MASK (0xF0U) #define AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_edma1_SHIFT (4U) /*! edma1 - address bit [35:32] for edma1 */ #define AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_UPPER_ADDR_edma1_MASK) /*! @} */ /*! @name IPG_DEBUG_CM33 - IPG DEBUG MASK BIT for cm33 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM33_sys_ctr1_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C0 - IPG DEBUG MASK BIT CA55 CORE0 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C0_sys_ctr1_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C1 - IPG DEBUG MASK BIT CA55 CORE1 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C1_sys_ctr1_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C2 - IPG DEBUG MASK BIT CA55 CORE2 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C2_sys_ctr1_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C3 - IPG DEBUG MASK BIT CA55 CORE3 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C3_sys_ctr1_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C4 - IPG DEBUG MASK BIT CA55 CORE4 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C4_sys_ctr1_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C5 - IPG DEBUG MASK BIT CA55 CORE5 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CA55C5_sys_ctr1_MASK) /*! @} */ /*! @name IPG_DEBUG_CM7 - IPG DEBUG MASK BIT for cm7 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_can1_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_can1_SHIFT (0U) /*! can1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_can1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_can1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_can1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_edma1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_edma1_SHIFT (1U) /*! edma1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_edma1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_edma1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_edma1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c1_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c1_SHIFT (2U) /*! lpi2c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c2_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c2_SHIFT (3U) /*! lpi2c2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpit1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpit1_SHIFT (4U) /*! lpit1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpit1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpit1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpit1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi1_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi1_SHIFT (5U) /*! lpspi1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi2_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi2_SHIFT (6U) /*! lpspi2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lptmr1_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lptmr1_SHIFT (7U) /*! lptmr1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lptmr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lptmr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_lptmr1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sai1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sai1_SHIFT (8U) /*! sai1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sai1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sai1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sai1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm1_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm1_SHIFT (9U) /*! tpm1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm2_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm2_SHIFT (10U) /*! tpm2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_tpm2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog1_SHIFT (11U) /*! wdog1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog2_SHIFT (12U) /*! wdog2 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_wdog2_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_i3c1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_i3c1_SHIFT (13U) /*! i3c1 - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_i3c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_i3c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_i3c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_pdm_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_pdm_SHIFT (14U) /*! pdm - Mask bit for debug halted mode * 0b0..Block does not enter debug halted mode with CA55 * 0b1..Block enters debug halted mode when CA55 is debug halted */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_pdm(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_pdm_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_pdm_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sys_ctr1_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sys_ctr1_SHIFT (15U) /*! sys_ctr1 - Mask bit for debug halted mode * 0b1..Block enters debug halted mode when CA55 is debug halted * 0b0..Block does not enter debug halted mode with CA55 */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sys_ctr1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sys_ctr1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DEBUG_CM7_sys_ctr1_MASK) /*! @} */ /*! @name FUSE_ACC_DIS - Read-only version of the OCOTP fuse-access-disable bit */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT (0U) /*! OSCCA_FUSE_READ_DIS - Fuse read disable bit * 0b1..SoC is not allowed to access the OCOTP * 0b0..SoC is allowed to access the OCOTP registers */ #define AON_BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_FUSE_ACC_DIS_OSCCA_FUSE_READ_DIS_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA0 - Read-only version of OCOTP fusedata_mtr_cfg_0 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_SHIFT (0U) /*! OCOTP_FUSE_DATA0 - OCOTP_FUSE_DATA0 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA0_OCOTP_FUSE_DATA0_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA1 - Read-only version of OCOTP fusedata_mtr_cfg_1 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_SHIFT (0U) /*! OCOTP_FUSE_DATA1 - OCOTP_FUSE_DATA1 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA1_OCOTP_FUSE_DATA1_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA2 - Read-only version of OCOTP fusedata_mtr_cfg_2 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_SHIFT (0U) /*! OCOTP_FUSE_DATA2 - OCOTP_FUSE_DATA2 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA2_OCOTP_FUSE_DATA2_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA3 - Read-only version of OCOTP fusedata_mtr_cfg_3 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_SHIFT (0U) /*! OCOTP_FUSE_DATA3 - OCOTP_FUSE_DATA3 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA3_OCOTP_FUSE_DATA3_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA4 - Read-only version of OCOTP fusedata_mtr_cfg_4 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_SHIFT (0U) /*! OCOTP_FUSE_DATA4 - OCOTP_FUSE_DATA4 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA4_OCOTP_FUSE_DATA4_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA5 - Read-only version of OCOTP fusedata_mtr_cfg_5 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_SHIFT (0U) /*! OCOTP_FUSE_DATA5 - OCOTP_FUSE_DATA5 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA5_OCOTP_FUSE_DATA5_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA6 - Read-only version of OCOTP fusedata_mtr_cfg_6 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_SHIFT (0U) /*! OCOTP_FUSE_DATA6 - OCOTP_FUSE_DATA6 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA6_OCOTP_FUSE_DATA6_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA7 - Read-only version of OCOTP fusedata_mtr_cfg_7 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_SHIFT (0U) /*! OCOTP_FUSE_DATA7 - OCOTP_FUSE_DATA7 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA7_OCOTP_FUSE_DATA7_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA8 - Read-only version of OCOTP fusedata_mem_trim_cfg0 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_SHIFT (0U) /*! OCOTP_FUSE_DATA8 - OCOTP_FUSE_DATA8 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA8_OCOTP_FUSE_DATA8_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA9 - Read-only version of OCOTP fusedata_mem_trim_cfg1 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_SHIFT (0U) /*! OCOTP_FUSE_DATA9 - OCOTP_FUSE_DATA9 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA9_OCOTP_FUSE_DATA9_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA10 - Read-only version of OCOTP fusedata_mem_trim_cfg2 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_SHIFT (0U) /*! OCOTP_FUSE_DATA10 - OCOTP_FUSE_DATA10 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA10_OCOTP_FUSE_DATA10_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA11 - Read-only version of OCOTP fusedata_mem_trim_cfg3 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_SHIFT (0U) /*! OCOTP_FUSE_DATA11 - OCOTP_FUSE_DATA12 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA11_OCOTP_FUSE_DATA11_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA12 - Read-only version of OCOTP fusedata_mem_trim_cfg4 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_SHIFT (0U) /*! OCOTP_FUSE_DATA12 - OCOTP_FUSE_DATA13 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA12_OCOTP_FUSE_DATA12_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA13 - Read-only version of OCOTP fusedata_mem_trim_cfg5 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_SHIFT (0U) /*! OCOTP_FUSE_DATA13 - OCOTP_FUSE_DATA13 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA13_OCOTP_FUSE_DATA13_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA14 - Read-only version of OCOTP fusedata_mem_trim_cfg6 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_SHIFT (0U) /*! OCOTP_FUSE_DATA14 - OCOTP_FUSE_DATA14 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA14_OCOTP_FUSE_DATA14_MASK) /*! @} */ /*! @name OCOTP_FUSE_DATA15 - Read-only version of OCOTP fusedata_mem_trim_cfg7 */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_SHIFT (0U) /*! OCOTP_FUSE_DATA15 - OCOTP_FUSE_DATA15 */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_FUSE_DATA15_OCOTP_FUSE_DATA15_MASK) /*! @} */ /*! @name I3C1_WAKEUP - I3C1 WAKEUPX CLR */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_irq_clr_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_irq_clr_SHIFT (0U) /*! irq_clr - I3C1 interrupt request clear */ #define AON_BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_irq_clr(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_irq_clr_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_I3C1_WAKEUP_irq_clr_MASK) /*! @} */ /*! @name OCOTP_STATUS - OCOTP status register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_STATUS_busy_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_OCOTP_STATUS_busy_SHIFT (0U) /*! busy - OCOTP controller busy bit * 0b1..Busy * 0b0..Idle */ #define AON_BLK_CTRL_NS_AONMIX_OCOTP_STATUS_busy(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_OCOTP_STATUS_busy_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_OCOTP_STATUS_busy_MASK) /*! @} */ /*! @name PDM_CLK_SEL - PDM clock selection register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_sel_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_sel_SHIFT (0U) /*! sel - select source for pdm clock * 0b1..SAI1_MCLK * 0b0..PDM root clock */ #define AON_BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_sel(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_sel_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_PDM_CLK_SEL_sel_MASK) /*! @} */ /*! @name I3C1_SDA_IRQ - I3C1 SDA IRQ */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_enable_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_enable_SHIFT (0U) /*! enable - IRQ enable bit * 0b0..I3C1 SDA IRQ disable * 0b1..I3C1 SDA IRQ enable */ #define AON_BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_enable(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_enable_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_I3C1_SDA_IRQ_enable_MASK) /*! @} */ /*! @name SSI - SSI master low power mode control */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_SHIFT (0U) /*! PAUSE_MODE - AONMIX SSI master pause mode * 0b0..AONMIX SSI master is not in pause mode * 0b1..AONMIX SSI master is not in pause mode */ #define AON_BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_SSI_PAUSE_MODE_MASK) #define AON_BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_SHIFT (1U) /*! BLKHOLE_MODE_B - AONMIX SSI master blackhole mode * 0b1..AONMIX SSI master will exit from blackhole mode * 0b0..AONMIX SSI master will enter into blackhole mode */ #define AON_BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_SSI_BLKHOLE_MODE_B_MASK) /*! @} */ /*! @name FASTBOOT_ENABLE - fastboot enable */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_MASK (0x3U) #define AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_SHIFT (0U) /*! FASTBOOT_ENABLE - FASTBOOT_ENABLE bits */ #define AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_FASTBOOT_ENABLE_MASK) #define AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_MASK (0xCU) #define AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_SHIFT (2U) /*! BP_FASTBOOT_ENABLE - BP_FASTBOOT_ENABLE bits */ #define AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_FASTBOOT_ENABLE_BP_FASTBOOT_ENABLE_MASK) /*! @} */ /*! @name MQS_SETTINGS - MQS settings */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_SHIFT (1U) /*! MQS_EN - MQS Enable * 0b1..Enable MQS * 0b0..Disable MQS */ #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_MQS_EN_MASK) #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_SHIFT (2U) /*! SOFT_RESET - Software Reset * 0b0..Exit software reset for MQS * 0b1..Enable software reset for MQS */ #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_SOFT_RESET_MASK) #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_SHIFT (3U) /*! OVERSAMPLE - Oversample rate * 0b0..64 * 0b1..32 */ #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_OVERSAMPLE_MASK) #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_MASK (0xFF00U) #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_SHIFT (8U) /*! CLK_DIVIDE - Clock divide factor configuration */ #define AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_MQS_SETTINGS_CLK_DIVIDE_MASK) /*! @} */ /*! @name ELE_FW_PRESENT - Read only bit for fuse ELE_FW_PRESENT */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_ELE_FW_PRESENT_ELE_fw_present_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_ELE_FW_PRESENT_ELE_fw_present_SHIFT (0U) /*! ELE_fw_present - Read-only bit for ELE FW present */ #define AON_BLK_CTRL_NS_AONMIX_ELE_FW_PRESENT_ELE_fw_present(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_ELE_FW_PRESENT_ELE_fw_present_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_ELE_FW_PRESENT_ELE_fw_present_MASK) /*! @} */ /*! @name AOMIX_SPARE_FUSE - Spare fuse register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_AOMIX_SPARE_FUSE_Spare_fuse_MASK (0x3U) #define AON_BLK_CTRL_NS_AONMIX_AOMIX_SPARE_FUSE_Spare_fuse_SHIFT (0U) /*! Spare_fuse - Read-only bit for Spare fuse */ #define AON_BLK_CTRL_NS_AONMIX_AOMIX_SPARE_FUSE_Spare_fuse(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_AOMIX_SPARE_FUSE_Spare_fuse_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_AOMIX_SPARE_FUSE_Spare_fuse_MASK) /*! @} */ /*! @name IPG_STOP_CTL - IPG_STOP Control Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_can1_stop_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_can1_stop_SHIFT (0U) /*! can1_stop - CAN1 ipg_stop control * 0b1..Enable stop * 0b0..Disable stop */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_can1_stop(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_can1_stop_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_can1_stop_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_edma1_stop_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_edma1_stop_SHIFT (1U) /*! edma1_stop - EDMA1 ipg_stop control * 0b1..Enable stop * 0b0..Disable stop */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_edma1_stop(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_edma1_stop_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_edma1_stop_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_pdm_stop_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_pdm_stop_SHIFT (9U) /*! pdm_stop - PDM ipg_stop control * 0b0..Disable stop * 0b1..Enable stop */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_pdm_stop(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_pdm_stop_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_pdm_stop_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm1_stop_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm1_stop_SHIFT (11U) /*! tpm1_stop - TPM1 ipg_stop control * 0b0..Disable stop * 0b1..Enable stop */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm1_stop(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm1_stop_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm1_stop_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm2_stop_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm2_stop_SHIFT (12U) /*! tpm2_stop - TPM2 ipg_stop control * 0b0..Disable stop * 0b1..Enable stop */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm2_stop(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm2_stop_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_STOP_CTL_tpm2_stop_MASK) /*! @} */ /*! @name IPG_STOP_ACK_STATUS - IPG_STOP_ACK Status Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_can1_stop_ack_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_can1_stop_ack_SHIFT (0U) /*! can1_stop_ack - CAN1 ipg_stop_ack status * 0b0..No stop acknowledge * 0b1..Stop acknowledge */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_can1_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_can1_stop_ack_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_can1_stop_ack_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_pdm_stop_ack_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_pdm_stop_ack_SHIFT (9U) /*! pdm_stop_ack - PDM ipg_stop_ack status * 0b1..Stop acknowledge * 0b0..No stop acknowledge */ #define AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_pdm_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_pdm_stop_ack_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_STOP_ACK_STATUS_pdm_stop_ack_MASK) /*! @} */ /*! @name IPG_DOZE_CTL - IPG_DOZE_CTL Control Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_can1_doze_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_can1_doze_SHIFT (0U) /*! can1_doze - CAN1 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_can1_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_can1_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_can1_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c1_doze_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c1_doze_SHIFT (2U) /*! lpi2c1_doze - LPI2C1 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c1_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c1_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c1_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c2_doze_MASK (0x8U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c2_doze_SHIFT (3U) /*! lpi2c2_doze - LPI2C2 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c2_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c2_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpi2c2_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpit1_doze_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpit1_doze_SHIFT (4U) /*! lpit1_doze - LPIT1 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpit1_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpit1_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpit1_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi1_doze_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi1_doze_SHIFT (5U) /*! lpspi1_doze - LPSPI1 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi1_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi1_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi1_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi2_doze_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi2_doze_SHIFT (6U) /*! lpspi2_doze - LPSPI2 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi2_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi2_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpspi2_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart1_doze_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart1_doze_SHIFT (7U) /*! lpuart1_doze - LPUART1 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart1_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart1_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart1_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart2_doze_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart2_doze_SHIFT (8U) /*! lpuart2_doze - LPUART2 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart2_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart2_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_lpuart2_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_pdm_doze_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_pdm_doze_SHIFT (9U) /*! pdm_doze - PDM doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_pdm_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_pdm_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_pdm_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm1_doze_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm1_doze_SHIFT (11U) /*! tpm1_doze - TPM1 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm1_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm1_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm1_doze_MASK) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm2_doze_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm2_doze_SHIFT (12U) /*! tpm2_doze - TPM2 doze control * 0b1..Enable doze * 0b0..Disable doze */ #define AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm2_doze(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm2_doze_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_IPG_DOZE_CTL_tpm2_doze_MASK) /*! @} */ /*! @name QREQ_N - QREQ_N Control Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c1_SHIFT (1U) /*! lpi2c1 - lpi2c1 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c2_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c2_SHIFT (2U) /*! lpi2c2 - lpi2c2 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi1_SHIFT (4U) /*! lpspi1 - lpspi1 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi2_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi2_SHIFT (5U) /*! lpspi2 - lpspi2 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart1_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart1_SHIFT (6U) /*! lpuart1 - lpuart1 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart2_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart2_SHIFT (7U) /*! lpuart2 - lpuart2 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_lpuart2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c1_SHIFT (8U) /*! ips_lpi2c1 - ips_lpi2c1 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c2_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c2_SHIFT (9U) /*! ips_lpi2c2 - ips_lpi2c2 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ahb_gpio_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ahb_gpio_SHIFT (10U) /*! ahb_gpio - ahb_gpio */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ahb_gpio(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_ahb_gpio_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_ahb_gpio_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi1_SHIFT (11U) /*! ips_lpspi1 - ips_lpspi1 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi2_SHIFT (12U) /*! ips_lpspi2 - ips_lpspi2 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart1_SHIFT (13U) /*! apb_lpuart1 - apb_lpuart1 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart2_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart2_SHIFT (14U) /*! apb_lpuart2 - apb_lpuart2 */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_apb_lpuart2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_sai_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_sai_SHIFT (15U) /*! ips_sai - ips_sai */ #define AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_sai(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_sai_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QREQ_N_ips_sai_MASK) /*! @} */ /*! @name SAI_MCLK - SAI1 MCLK Control Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_req_MASK (0x1U) #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_req_SHIFT (0U) /*! sai_mclk_req - SAI MCLK request */ #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_req(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_req_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_req_MASK) #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_ack_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_ack_SHIFT (1U) /*! sai_mclk_ack - SAI MCLK ack */ #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_ack(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_ack_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_mclk_ack_MASK) #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_qactive_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_qactive_SHIFT (2U) /*! sai_qactive - SAI qactive */ #define AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_qactive(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_qactive_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_SAI_MCLK_sai_qactive_MASK) /*! @} */ /*! @name QACTIVE - QACTIVE Status Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c1_SHIFT (1U) /*! lpi2c1 - lpi2c1 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c2_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c2_SHIFT (2U) /*! lpi2c2 - lpi2c2 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi1_SHIFT (4U) /*! lpspi1 - lpspi1 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi2_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi2_SHIFT (5U) /*! lpspi2 - lpspi2 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart1_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart1_SHIFT (6U) /*! lpuart1 - lpuart1 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart2_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart2_SHIFT (7U) /*! lpuart2 - lpuart2 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_lpuart2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c1_SHIFT (8U) /*! ips_lpi2c1 - ips_lpi2c1 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c2_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c2_SHIFT (9U) /*! ips_lpi2c2 - ips_lpi2c2 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ahb_gpio_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ahb_gpio_SHIFT (10U) /*! ahb_gpio - ahb_gpio */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ahb_gpio(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_ahb_gpio_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_ahb_gpio_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi1_SHIFT (11U) /*! ips_lpspi1 - ips_lpspi1 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi2_SHIFT (12U) /*! ips_lpspi2 - ips_lpspi2 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart1_SHIFT (13U) /*! apb_lpuart1 - apb_lpuart1 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart2_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart2_SHIFT (14U) /*! apb_lpuart2 - apb_lpuart2 */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_apb_lpuart2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_sai_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_sai_SHIFT (15U) /*! ips_sai - ips_sai */ #define AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_sai(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_sai_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACTIVE_ips_sai_MASK) /*! @} */ /*! @name QDENY - QDENY Status Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c1_SHIFT (1U) /*! lpi2c1 - lpi2c1 */ #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c2_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c2_SHIFT (2U) /*! lpi2c2 - lpi2c2 */ #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QDENY_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi1_SHIFT (4U) /*! lpspi1 - lpspi1 */ #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi2_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi2_SHIFT (5U) /*! lpspi2 - lpspi2 */ #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QDENY_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart1_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart1_SHIFT (6U) /*! lpuart1 - lpuart1 */ #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart2_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart2_SHIFT (7U) /*! lpuart2 - lpuart2 */ #define AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QDENY_lpuart2_MASK) /*! @} */ /*! @name QACCEPT_N - QACCEPT_N Status Register */ /*! @{ */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c1_MASK (0x2U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c1_SHIFT (1U) /*! lpi2c1 - lpi2c1 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c2_MASK (0x4U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c2_SHIFT (2U) /*! lpi2c2 - lpi2c2 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi1_MASK (0x10U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi1_SHIFT (4U) /*! lpspi1 - lpspi1 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi2_MASK (0x20U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi2_SHIFT (5U) /*! lpspi2 - lpspi2 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart1_MASK (0x40U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart1_SHIFT (6U) /*! lpuart1 - lpuart1 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart2_MASK (0x80U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart2_SHIFT (7U) /*! lpuart2 - lpuart2 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_lpuart2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c1_MASK (0x100U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c1_SHIFT (8U) /*! ips_lpi2c1 - ips_lpi2c1 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c2_MASK (0x200U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c2_SHIFT (9U) /*! ips_lpi2c2 - ips_lpi2c2 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpi2c2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ahb_gpio_MASK (0x400U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ahb_gpio_SHIFT (10U) /*! ahb_gpio - ahb_gpio */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ahb_gpio(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ahb_gpio_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ahb_gpio_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi1_MASK (0x800U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi1_SHIFT (11U) /*! ips_lpspi1 - ips_lpspi1 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi2_MASK (0x1000U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi2_SHIFT (12U) /*! ips_lpspi2 - ips_lpspi2 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_lpspi2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart1_MASK (0x2000U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart1_SHIFT (13U) /*! apb_lpuart1 - apb_lpuart1 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart1_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart1_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart2_MASK (0x4000U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart2_SHIFT (14U) /*! apb_lpuart2 - apb_lpuart2 */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart2_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_apb_lpuart2_MASK) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_sai_MASK (0x8000U) #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_sai_SHIFT (15U) /*! ips_sai - ips_sai */ #define AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_sai(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_sai_SHIFT)) & AON_BLK_CTRL_NS_AONMIX_QACCEPT_N_ips_sai_MASK) /*! @} */ /*! * @} */ /* end of group AON_BLK_CTRL_NS_AONMIX_Register_Masks */ /* AON_BLK_CTRL_NS_AONMIX - Peripheral instance base addresses */ /** Peripheral AON__BLK_CTRL_NS_AONMIX1 base address */ #define AON__BLK_CTRL_NS_AONMIX1_BASE (0x44210000u) /** Peripheral AON__BLK_CTRL_NS_AONMIX1 base pointer */ #define AON__BLK_CTRL_NS_AONMIX1 ((AON_BLK_CTRL_NS_AONMIX_Type *)AON__BLK_CTRL_NS_AONMIX1_BASE) /** Array initializer of AON_BLK_CTRL_NS_AONMIX peripheral base addresses */ #define AON_BLK_CTRL_NS_AONMIX_BASE_ADDRS { AON__BLK_CTRL_NS_AONMIX1_BASE } /** Array initializer of AON_BLK_CTRL_NS_AONMIX peripheral base pointers */ #define AON_BLK_CTRL_NS_AONMIX_BASE_PTRS { AON__BLK_CTRL_NS_AONMIX1 } /*! * @} */ /* end of group AON_BLK_CTRL_NS_AONMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_BLK_CTRL_S_AONMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_BLK_CTRL_S_AONMIX_Peripheral_Access_Layer AON_BLK_CTRL_S_AONMIX Peripheral Access Layer * @{ */ /** AON_BLK_CTRL_S_AONMIX - Register Layout Typedef */ typedef struct { __IO uint32_t CM33_IRQ_MASK0; /**< CM33_IRQ_MASK0, offset: 0x0 */ __IO uint32_t CM33_IRQ_MASK1; /**< CM33_IRQ_MASK1, offset: 0x4 */ __IO uint32_t CM33_IRQ_MASK2; /**< CM33_IRQ_MASK2, offset: 0x8 */ __IO uint32_t CM33_IRQ_MASK3; /**< CM33_IRQ_MASK3, offset: 0xC */ __IO uint32_t CM33_IRQ_MASK4; /**< CM33_IRQ_MASK4, offset: 0x10 */ __IO uint32_t CM33_IRQ_MASK5; /**< CM33_IRQ_MASK5, offset: 0x14 */ __IO uint32_t CM33_IRQ_MASK6; /**< CM33_IRQ_MASK6, offset: 0x18 */ __IO uint32_t CM33_IRQ_MASK7; /**< CM33_IRQ_MASK7, offset: 0x1C */ __IO uint32_t CM33_IRQ_MASK8; /**< CM33_IRQ_MASK8, offset: 0x20 */ __IO uint32_t CM33_IRQ_MASK9; /**< CM33_IRQ_MASK9, offset: 0x24 */ __IO uint32_t CM33_IRQ_MASK10; /**< CM33_IRQ_MASK10, offset: 0x28 */ __IO uint32_t CM33_IRQ_MASK11; /**< CM33_IRQ_MASK11, offset: 0x2C */ uint8_t RESERVED_0[16]; __IO uint32_t CA55_IRQ_MASK0; /**< CA55_IRQ_MASK0, offset: 0x40 */ __IO uint32_t CA55_IRQ_MASK1; /**< CA55_IRQ_MASK1, offset: 0x44 */ __IO uint32_t CA55_IRQ_MASK2; /**< CA55_IRQ_MASK2, offset: 0x48 */ __IO uint32_t CA55_IRQ_MASK3; /**< CA55_IRQ_MASK3, offset: 0x4C */ __IO uint32_t CA55_IRQ_MASK4; /**< CA55_IRQ_MASK4, offset: 0x50 */ __IO uint32_t CA55_IRQ_MASK5; /**< CA55_IRQ_MASK5, offset: 0x54 */ __IO uint32_t CA55_IRQ_MASK6; /**< CA55_IRQ_MASK6, offset: 0x58 */ __IO uint32_t CA55_IRQ_MASK7; /**< CA55_IRQ_MASK7, offset: 0x5C */ __IO uint32_t CA55_IRQ_MASK8; /**< CA55_IRQ_MASK8, offset: 0x60 */ __IO uint32_t CA55_IRQ_MASK9; /**< CA55_IRQ_MASK9, offset: 0x64 */ __IO uint32_t CA55_IRQ_MASK10; /**< CA55_IRQ_MASK10, offset: 0x68 */ __IO uint32_t CA55_IRQ_MASK11; /**< CA55_IRQ_MASK11, offset: 0x6C */ uint8_t RESERVED_1[16]; __IO uint32_t CM7_IRQ_MASK0; /**< CM7_IRQ_MASK0, offset: 0x80 */ __IO uint32_t CM7_IRQ_MASK1; /**< CM7_IRQ_MASK1, offset: 0x84 */ __IO uint32_t CM7_IRQ_MASK2; /**< CM7_IRQ_MASK2, offset: 0x88 */ __IO uint32_t CM7_IRQ_MASK3; /**< CM7_IRQ_MASK3, offset: 0x8C */ __IO uint32_t CM7_IRQ_MASK4; /**< CM7_IRQ_MASK4, offset: 0x90 */ __IO uint32_t CM7_IRQ_MASK5; /**< CM7_IRQ_MASK5, offset: 0x94 */ __IO uint32_t CM7_IRQ_MASK6; /**< CM7_IRQ_MASK6, offset: 0x98 */ __IO uint32_t CM7_IRQ_MASK7; /**< CM7_IRQ_MASK7, offset: 0x9C */ __IO uint32_t CM7_IRQ_MASK8; /**< CM7_IRQ_MASK8, offset: 0xA0 */ __IO uint32_t CM7_IRQ_MASK9; /**< CM7_IRQ_MASK9, offset: 0xA4 */ __IO uint32_t CM7_IRQ_MASK10; /**< CM7_IRQ_MASK10, offset: 0xA8 */ __IO uint32_t CM7_IRQ_MASK11; /**< CM7_IRQ_MASK11, offset: 0xAC */ uint8_t RESERVED_2[80]; __IO uint32_t INITSVTOR; /**< M33 restart secure address, offset: 0x100 */ __IO uint32_t INITNSVTOR; /**< M33 restart non-secure address, offset: 0x104 */ __IO uint32_t INITVTOR; /**< M7 restart address, offset: 0x108 */ uint8_t RESERVED_3[20]; __IO uint32_t M33_CFG; /**< M33 Configure Register, offset: 0x120 */ __IO uint32_t M7_CFG; /**< M7 Configure Register, offset: 0x124 */ uint8_t RESERVED_4[8]; __IO uint32_t AXBS_AON_CTRL; /**< AXBS_AON_CTRL, offset: 0x130 */ __IO uint32_t DAP_ACCESS_STKYBIT; /**< Dap Access Sticky Bit, offset: 0x134 */ __IO uint32_t LP_HANDSHAKE_ELE; /**< Low Power Handshake for ELE Register, offset: 0x138 */ __IO uint32_t LP_HANDSHAKE2_ELE; /**< Low Power Handshake 2 for ELE Register, offset: 0x13C */ uint32_t LP_HANDSHAKE3_ELE; /**< Low Power Handshake 3 for ELE Register, offset: 0x140 */ __IO uint32_t LP_HANDSHAKE_SM; /**< Low Power Handshake for System Manager, offset: 0x144 */ __IO uint32_t LP_HANDSHAKE2_SM; /**< Low Power Handshake 2 for System Manager, offset: 0x148 */ uint32_t LP_HANDSHAKE3_SM; /**< Low Power Handshake 3 for System Manager, offset: 0x14C */ __IO uint32_t SM_LP_HANDSHAKE_STATUS; /**< Register interface for system manager to react for the lp_handshake, offset: 0x150 */ uint8_t RESERVED_5[12]; __IO uint32_t CA55_CPUWAIT; /**< CPUWAIT settings for CA55 CPU, offset: 0x160 */ __IO uint32_t CA55_RVBARADDR0_L; /**< CA55_RVBARADDR0_L, offset: 0x164 */ __IO uint32_t CA55_RVBARADDR0_H; /**< CA55_RVBARADDR0_H, offset: 0x168 */ __IO uint32_t CA55_RVBARADDR1_L; /**< CA55_RVBARADDR1_L, offset: 0x16C */ __IO uint32_t CA55_RVBARADDR1_H; /**< CA55_RVBARADDR1_H, offset: 0x170 */ __IO uint32_t CA55_RVBARADDR2_L; /**< CA55_RVBARADDR2_L, offset: 0x174 */ __IO uint32_t CA55_RVBARADDR2_H; /**< CA55_RVBARADDR2_H, offset: 0x178 */ __IO uint32_t CA55_RVBARADDR3_L; /**< CA55_RVBARADDR3_L, offset: 0x17C */ __IO uint32_t CA55_RVBARADDR3_H; /**< CA55_RVBARADDR3_H, offset: 0x180 */ __IO uint32_t CA55_RVBARADDR4_L; /**< CA55_RVBARADDR4_L, offset: 0x184 */ __IO uint32_t CA55_RVBARADDR4_H; /**< CA55_RVBARADDR4_H, offset: 0x188 */ __IO uint32_t CA55_RVBARADDR5_L; /**< CA55_RVBARADDR5_L, offset: 0x18C */ __IO uint32_t CA55_RVBARADDR5_H; /**< CA55_RVBARADDR5_H, offset: 0x190 */ uint8_t RESERVED_6[12]; __IO uint32_t ELE_IRQ_MASK; /**< Mask bits of ELE interrupt, offset: 0x1A0 */ __IO uint32_t ELE_RESET_REQ_MASK; /**< Mask bits of ELE reset, offset: 0x1A4 */ __IO uint32_t ELE_HALT_STATUS; /**< ELE Halt Status Register, offset: 0x1A8 */ __IO uint32_t CA55_MODE; /**< Control the boot mode of two ca55 cores, offset: 0x1AC */ __IO uint32_t NMI_MASK; /**< NMI MASK bits, offset: 0x1B0 */ __IO uint32_t NMI_CLR; /**< NMI clear bit, offset: 0x1B4 */ __IO uint32_t WDOG_ANY_MASK; /**< Wdog any mask, offset: 0x1B8 */ uint8_t RESERVED_7[4]; __IO uint32_t MISC_CFG; /**< Miscellaneous Configure Register, offset: 0x1C0 */ uint8_t RESERVED_8[4]; __I uint32_t ELE_GPO_STATUS; /**< ELE gpo status register, offset: 0x1C8 */ __I uint32_t ELE_RST_REQ_STAT; /**< ELE Reset Request Status Register, offset: 0x1CC */ __I uint32_t ELE_IRQ_REQ_STAT; /**< ELE IRQ Request Status Register, offset: 0x1D0 */ } AON_BLK_CTRL_S_AONMIX_Type; /* ---------------------------------------------------------------------------- -- AON_BLK_CTRL_S_AONMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_BLK_CTRL_S_AONMIX_Register_Masks AON_BLK_CTRL_S_AONMIX Register Masks * @{ */ /*! @name CM33_IRQ_MASK0 - CM33_IRQ_MASK0 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK0_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK0_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK0_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK0_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK0_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK1 - CM33_IRQ_MASK1 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK1_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK1_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK1_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK1_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK1_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK2 - CM33_IRQ_MASK2 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK2_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK2_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK2_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK2_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK2_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK3 - CM33_IRQ_MASK3 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK3_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK3_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK3_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK3_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK3_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK4 - CM33_IRQ_MASK4 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK4_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK4_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK4_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK4_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK4_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK5 - CM33_IRQ_MASK5 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK5_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK5_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK5_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK5_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK5_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK6 - CM33_IRQ_MASK6 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK6_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK6_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK6_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK6_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK6_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK7 - CM33_IRQ_MASK7 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK7_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK7_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK7_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK7_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK7_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK8 - CM33_IRQ_MASK8 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK8_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK8_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK8_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK8_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK8_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK9 - CM33_IRQ_MASK9 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK9_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK9_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK9_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK9_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK9_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK10 - CM33_IRQ_MASK10 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK10_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK10_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK10_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK10_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK10_m_MASK) /*! @} */ /*! @name CM33_IRQ_MASK11 - CM33_IRQ_MASK11 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK11_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK11_m_SHIFT (0U) /*! m - CM33 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK11_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK11_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM33_IRQ_MASK11_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK0 - CA55_IRQ_MASK0 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK0_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK1 - CA55_IRQ_MASK1 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK1_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK2 - CA55_IRQ_MASK2 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK2_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK3 - CA55_IRQ_MASK3 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK3_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK4 - CA55_IRQ_MASK4 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK4_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK5 - CA55_IRQ_MASK5 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK5_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK6 - CA55_IRQ_MASK6 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK6_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK7 - CA55_IRQ_MASK7 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK7_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK7_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK7_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK7_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK7_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK8 - CA55_IRQ_MASK8 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK8_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK8_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK8_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK8_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK8_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK9 - CA55_IRQ_MASK9 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK9_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK9_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK9_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK9_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK9_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK10 - CA55_IRQ_MASK10 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK10_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK10_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK10_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK10_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK10_m_MASK) /*! @} */ /*! @name CA55_IRQ_MASK11 - CA55_IRQ_MASK11 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK11_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK11_m_SHIFT (0U) /*! m - CA55 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK11_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK11_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_IRQ_MASK11_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK0 - CM7_IRQ_MASK0 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK0_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK0_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK0_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK0_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK0_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK1 - CM7_IRQ_MASK1 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK1_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK1_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK1_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK1_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK1_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK2 - CM7_IRQ_MASK2 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK2_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK2_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK2_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK2_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK2_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK3 - CM7_IRQ_MASK3 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK3_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK3_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK3_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK3_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK3_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK4 - CM7_IRQ_MASK4 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK4_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK4_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK4_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK4_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK4_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK5 - CM7_IRQ_MASK5 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK5_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK5_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK5_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK5_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK5_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK6 - CM7_IRQ_MASK6 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK6_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK6_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK6_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK6_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK6_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK7 - CM7_IRQ_MASK7 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK7_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK7_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK7_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK7_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK7_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK8 - CM7_IRQ_MASK8 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK8_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK8_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK8_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK8_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK8_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK9 - CM7_IRQ_MASK9 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK9_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK9_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK9_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK9_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK9_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK10 - CM7_IRQ_MASK10 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK10_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK10_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK10_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK10_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK10_m_MASK) /*! @} */ /*! @name CM7_IRQ_MASK11 - CM7_IRQ_MASK11 */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK11_m_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK11_m_SHIFT (0U) /*! m - CM7 IRQ MASK */ #define AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK11_m(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK11_m_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CM7_IRQ_MASK11_m_MASK) /*! @} */ /*! @name INITSVTOR - M33 restart secure address */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_INITSVTOR_m33_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_INITSVTOR_m33_SHIFT (0U) /*! m33 - INITSVTOR */ #define AON_BLK_CTRL_S_AONMIX_INITSVTOR_m33(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_INITSVTOR_m33_SHIFT)) & AON_BLK_CTRL_S_AONMIX_INITSVTOR_m33_MASK) /*! @} */ /*! @name INITNSVTOR - M33 restart non-secure address */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_INITNSVTOR_m33_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_INITNSVTOR_m33_SHIFT (0U) /*! m33 - INITSVTOR */ #define AON_BLK_CTRL_S_AONMIX_INITNSVTOR_m33(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_INITNSVTOR_m33_SHIFT)) & AON_BLK_CTRL_S_AONMIX_INITNSVTOR_m33_MASK) /*! @} */ /*! @name INITVTOR - M7 restart address */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_INITVTOR_M7_MASK (0xFFFFFF80U) #define AON_BLK_CTRL_S_AONMIX_INITVTOR_M7_SHIFT (7U) /*! M7 - INITVTOR */ #define AON_BLK_CTRL_S_AONMIX_INITVTOR_M7(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_INITVTOR_M7_SHIFT)) & AON_BLK_CTRL_S_AONMIX_INITVTOR_M7_MASK) /*! @} */ /*! @name M33_CFG - M33 Configure Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_M33_CFG_WAIT_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_M33_CFG_WAIT_SHIFT (2U) /*! WAIT - M33 CPU WAIT */ #define AON_BLK_CTRL_S_AONMIX_M33_CFG_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_M33_CFG_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_M33_CFG_WAIT_MASK) #define AON_BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_MASK (0x18U) #define AON_BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_SHIFT (3U) /*! TCM_SIZE - M33 TCM SIZE * 0b11..Reserved * 0b10..Double Sys TCM, 512KB Sys TCM * 0b01..Double Code TCM, 512KB Code TCM * 0b00..Regular TCM, 256KB Code TCM and 256KB Sys TCM */ #define AON_BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_SHIFT)) & AON_BLK_CTRL_S_AONMIX_M33_CFG_TCM_SIZE_MASK) /*! @} */ /*! @name M7_CFG - M7 Configure Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK (0x7U) #define AON_BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_SHIFT (0U) /*! TCM_SIZE - M7 TCM SIZE * 0b000..Regular TCM, 256KB ITCM, and 256KB DTCM * 0b001..Double ITCM, 512KB ITCM * 0b010..Double DTCM, 512KB DTCM * 0b011..Reserved * 0b100..HALF ITCM, 128KB ITCM, and 384KB DTCM * 0b101..HALF DTCM, 384KB ITCM, and 128KB DTCM * 0b110..Reserved * 0b111..Reserved */ #define AON_BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_SHIFT)) & AON_BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK) #define AON_BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_M7_CFG_WAIT_SHIFT (4U) /*! WAIT - M7 CPUWAIT */ #define AON_BLK_CTRL_S_AONMIX_M7_CFG_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_M7_CFG_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK) #define AON_BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_SHIFT (5U) /*! CORECLK_FORCE_ON - Force CM7 core clock on * 0b0..CM7 core clock is off when CM7 is sleeping * 0b1..CM7 core clock is on when CM7 is sleeping */ #define AON_BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_SHIFT)) & AON_BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_MASK) #define AON_BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_MASK (0x40U) #define AON_BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_SHIFT (6U) /*! HCLK_FORCE_ON - CM7 platform AHB clock enable * 0b0..AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible. * 0b1..AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible. */ #define AON_BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_SHIFT)) & AON_BLK_CTRL_S_AONMIX_M7_CFG_HCLK_FORCE_ON_MASK) /*! @} */ /*! @name AXBS_AON_CTRL - AXBS_AON_CTRL */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_SHIFT (0U) /*! FORCE_ROUND_ROBIN - AXBS_AON FORCE_ROUND_ROBIN * 0b0..Enable force round robin (default) * 0b1..Disable force round robin */ #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_SHIFT)) & AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_FORCE_ROUND_ROBIN_MASK) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_SHIFT (1U) /*! M0_HIGH_PRIORITY - M0 High Priority Control Bit * 0b1..High priority * 0b0..Default priority */ #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_SHIFT)) & AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M0_HIGH_PRIORITY_MASK) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_SHIFT (2U) /*! M1_HIGH_PRIORITY - M1 High Priority Control Bit * 0b0..Default priority * 0b1..High priority */ #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_SHIFT)) & AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M1_HIGH_PRIORITY_MASK) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_SHIFT (3U) /*! M2_HIGH_PRIORITY - M2 High Priority Control Bit * 0b0..Default priority * 0b1..High priority */ #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_SHIFT)) & AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M2_HIGH_PRIORITY_MASK) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_SHIFT (4U) /*! M3_HIGH_PRIORITY - M3 High Priority Control Bit * 0b0..Default priority * 0b1..High priority */ #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_SHIFT)) & AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M3_HIGH_PRIORITY_MASK) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_SHIFT (5U) /*! M4_HIGH_PRIORITY - M4 High Priority Control Bit * 0b0..Default priority * 0b1..High priority */ #define AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_SHIFT)) & AON_BLK_CTRL_S_AONMIX_AXBS_AON_CTRL_M4_HIGH_PRIORITY_MASK) /*! @} */ /*! @name DAP_ACCESS_STKYBIT - Dap Access Sticky Bit */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_SHIFT (0U) /*! M33 - M33 DAP_ACCESS_STKYBIT * 0b0..M33 core cannot be accessed by DAP * 0b1..M33 core can be accessed by DAP */ #define AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_SHIFT)) & AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_M33_MASK) #define AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT (1U) /*! A55 - A55 DAP_ACCESS_STKYBIT * 0b1..A55 core can be accessed by DAP * 0b0..A55 core cannot be accessed by DAP */ #define AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_SHIFT)) & AON_BLK_CTRL_S_AONMIX_DAP_ACCESS_STKYBIT_A55_MASK) /*! @} */ /*! @name LP_HANDSHAKE_ELE - Low Power Handshake for ELE Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_SHIFT (1U) /*! aonmix - AON domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_M33_platform_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_M33_platform_SHIFT (2U) /*! M33_platform - CM33 platform cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_M33_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_M33_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_M33_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ELE_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ELE_SHIFT (3U) /*! ELE - ELE cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ELE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ELE_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ELE_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_Cameramix_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_Cameramix_SHIFT (5U) /*! Cameramix - Camera domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_Cameramix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_Cameramix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_Cameramix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu0_MASK (0x80U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu0_SHIFT (7U) /*! A55_cpu0 - CA55_CPU0 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu0(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu0_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu0_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu1_MASK (0x100U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu1_SHIFT (8U) /*! A55_cpu1 - CA55_CPU1 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu1_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu1_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu2_MASK (0x200U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu2_SHIFT (9U) /*! A55_cpu2 - CA55_CPU2 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu2_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu2_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu3_MASK (0x400U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu3_SHIFT (10U) /*! A55_cpu3 - CA55_CPU3 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu3_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu3_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu4_MASK (0x800U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu4_SHIFT (11U) /*! A55_cpu4 - CA55_CPU4 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu4_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu4_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu5_MASK (0x1000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu5_SHIFT (12U) /*! A55_cpu5 - CA55_CPU5 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu5_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_cpu5_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_platform_MASK (0x2000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_platform_SHIFT (13U) /*! A55_platform - CA55_Platform cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_A55_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddrmix_top_MASK (0x4000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddrmix_top_SHIFT (14U) /*! ddrmix_top - DDR domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddrmix_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddrmix_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddrmix_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddr_phy_MASK (0x8000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddr_phy_SHIFT (15U) /*! ddr_phy - DDR PHY cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddr_phy(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddr_phy_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_ddr_phy_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_display_MASK (0x10000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_display_SHIFT (16U) /*! display - Display domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_display(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_display_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_display_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_gpu_MASK (0x20000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_gpu_SHIFT (17U) /*! gpu - GPU domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_gpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_gpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_gpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_top_MASK (0x40000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_top_SHIFT (18U) /*! hsio_top - HSIO domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_aon_MASK (0x80000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_aon_SHIFT (19U) /*! hsio_aon - HSIO_AON cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_aon(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_aon_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_hsio_aon_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_m7mix_MASK (0x100000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_m7mix_SHIFT (20U) /*! m7mix - M7 domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_m7mix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_m7mix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_m7mix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_netc_MASK (0x200000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_netc_SHIFT (21U) /*! netc - NETC domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_netc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_netc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_netc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_noc_MASK (0x400000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_noc_SHIFT (22U) /*! noc - NOC cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_noc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_noc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_noc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_npu_MASK (0x800000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_npu_SHIFT (23U) /*! npu - NPU cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_npu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_npu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_npu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_vpu_MASK (0x1000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_vpu_SHIFT (24U) /*! vpu - VPU cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_vpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_vpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_vpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_top_MASK (0x2000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_top_SHIFT (25U) /*! wakeupmix_top - wakeupmix_top cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_jtag_MASK (0x4000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_jtag_SHIFT (26U) /*! wakeupmix_jtag - wakeupmix_jtag cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_jtag(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_jtag_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_jtag_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog_3_4_MASK (0x8000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog_3_4_SHIFT (27U) /*! wakeupmix_wdog_3_4 - wakeupmix_wdog_3_4 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog_3_4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog_3_4_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog_3_4_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog5_MASK (0x10000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog5_SHIFT (28U) /*! wakeupmix_wdog5 - wakeupmix_wdog5 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog5_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_wakeupmix_wdog5_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_power_MASK (0x40000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_power_SHIFT (30U) /*! aonmix_power - AON domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_power(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_power_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_ELE_aonmix_power_MASK) /*! @} */ /*! @name LP_HANDSHAKE2_ELE - Low Power Handshake 2 for ELE Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_cameramix_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_cameramix_SHIFT (0U) /*! cameramix - Camera domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_cameramix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_cameramix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_cameramix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu0_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu0_SHIFT (2U) /*! A55_cpu0 - CA55_CPU0 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu0(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu0_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu0_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu1_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu1_SHIFT (3U) /*! A55_cpu1 - CA55_CPU1 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu1_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu1_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu2_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu2_SHIFT (4U) /*! A55_cpu2 - CA55_CPU2 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu2_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu2_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu3_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu3_SHIFT (5U) /*! A55_cpu3 - CA55_CPU3 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu3_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu3_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu4_MASK (0x40U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu4_SHIFT (6U) /*! A55_cpu4 - CA55_CPU4 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu4_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu4_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu5_MASK (0x80U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu5_SHIFT (7U) /*! A55_cpu5 - CA55_CPU5 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu5_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_cpu5_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_platform_MASK (0x100U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_platform_SHIFT (8U) /*! A55_platform - CA55_Platform low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_A55_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_ddr_MASK (0x200U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_ddr_SHIFT (9U) /*! ddr - DDR domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_ddr(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_ddr_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_ddr_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_display_MASK (0x400U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_display_SHIFT (10U) /*! display - Display domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_display(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_display_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_display_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_gpu_MASK (0x800U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_gpu_SHIFT (11U) /*! gpu - GPU domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_gpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_gpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_gpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_top_MASK (0x1000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_top_SHIFT (12U) /*! hsio_top - HSIO domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_aon_MASK (0x2000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_aon_SHIFT (13U) /*! hsio_aon - HSIO_AON low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_aon(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_aon_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_hsio_aon_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_m7_platform_MASK (0x4000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_m7_platform_SHIFT (14U) /*! m7_platform - M7 Platform low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_m7_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_m7_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_m7_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_netc_MASK (0x8000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_netc_SHIFT (15U) /*! netc - NETC domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_netc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_netc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_netc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_noc_MASK (0x10000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_noc_SHIFT (16U) /*! noc - NOC low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_noc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_noc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_noc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_npu_MASK (0x20000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_npu_SHIFT (17U) /*! npu - NPU low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_npu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_npu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_npu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_vpu_MASK (0x40000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_vpu_SHIFT (18U) /*! vpu - VPU low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_vpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_vpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_vpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_wakeup_MASK (0x80000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_wakeup_SHIFT (19U) /*! wakeup - WAKEUP low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_wakeup(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_wakeup_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_wakeup_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_osc24mhz_MASK (0x100000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_osc24mhz_SHIFT (20U) /*! osc24mhz - OSC 24MHz low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_osc24mhz(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_osc24mhz_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_ELE_osc24mhz_MASK) /*! @} */ /*! @name LP_HANDSHAKE_SM - Low Power Handshake for System Manager */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_SHIFT (1U) /*! aonmix - AON domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_M33_platform_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_M33_platform_SHIFT (2U) /*! M33_platform - CM33 platform cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_M33_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_M33_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_M33_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ELE_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ELE_SHIFT (3U) /*! ELE - ELE cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ELE(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ELE_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ELE_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_Cameramix_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_Cameramix_SHIFT (5U) /*! Cameramix - Camera domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_Cameramix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_Cameramix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_Cameramix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu0_MASK (0x80U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu0_SHIFT (7U) /*! A55_cpu0 - CA55_CPU0 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu0(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu0_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu0_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu1_MASK (0x100U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu1_SHIFT (8U) /*! A55_cpu1 - CA55_CPU1 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu1_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu1_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu2_MASK (0x200U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu2_SHIFT (9U) /*! A55_cpu2 - CA55_CPU2 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu2_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu2_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu3_MASK (0x400U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu3_SHIFT (10U) /*! A55_cpu3 - CA55_CPU3 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu3_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu3_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu4_MASK (0x800U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu4_SHIFT (11U) /*! A55_cpu4 - CA55_CPU4 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu4_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu4_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu5_MASK (0x1000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu5_SHIFT (12U) /*! A55_cpu5 - CA55_CPU5 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu5_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_cpu5_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_platform_MASK (0x2000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_platform_SHIFT (13U) /*! A55_platform - CA55_Platform cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_A55_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddrmix_top_MASK (0x4000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddrmix_top_SHIFT (14U) /*! ddrmix_top - DDR domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddrmix_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddrmix_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddrmix_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddr_phy_MASK (0x8000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddr_phy_SHIFT (15U) /*! ddr_phy - DDR PHY cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddr_phy(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddr_phy_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_ddr_phy_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_display_MASK (0x10000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_display_SHIFT (16U) /*! display - Display domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_display(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_display_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_display_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_gpu_MASK (0x20000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_gpu_SHIFT (17U) /*! gpu - GPU domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_gpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_gpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_gpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_top_MASK (0x40000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_top_SHIFT (18U) /*! hsio_top - HSIO domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_aon_MASK (0x80000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_aon_SHIFT (19U) /*! hsio_aon - HSIO_AON cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_aon(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_aon_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_hsio_aon_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_m7mix_MASK (0x100000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_m7mix_SHIFT (20U) /*! m7mix - M7 domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_m7mix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_m7mix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_m7mix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_netc_MASK (0x200000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_netc_SHIFT (21U) /*! netc - NETC domain cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_netc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_netc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_netc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_noc_MASK (0x400000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_noc_SHIFT (22U) /*! noc - NOC cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_noc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_noc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_noc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_npu_MASK (0x800000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_npu_SHIFT (23U) /*! npu - NPU cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_npu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_npu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_npu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_vpu_MASK (0x1000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_vpu_SHIFT (24U) /*! vpu - VPU cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_vpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_vpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_vpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_top_MASK (0x2000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_top_SHIFT (25U) /*! wakeupmix_top - wakeupmix_top cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_jtag_MASK (0x4000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_jtag_SHIFT (26U) /*! wakeupmix_jtag - wakeupmix_jtag cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_jtag(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_jtag_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_jtag_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog_3_4_MASK (0x8000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog_3_4_SHIFT (27U) /*! wakeupmix_wdog_3_4 - wakeupmix_wdog_3_4 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog_3_4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog_3_4_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog_3_4_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog5_MASK (0x10000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog5_SHIFT (28U) /*! wakeupmix_wdog5 - wakeupmix_wdog5 cold reset handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog5_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_wakeupmix_wdog5_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_power_MASK (0x40000000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_power_SHIFT (30U) /*! aonmix_power - AON domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_power(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_power_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE_SM_aonmix_power_MASK) /*! @} */ /*! @name LP_HANDSHAKE2_SM - Low Power Handshake 2 for System Manager */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_cameramix_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_cameramix_SHIFT (0U) /*! cameramix - Camera domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_cameramix(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_cameramix_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_cameramix_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu0_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu0_SHIFT (2U) /*! A55_cpu0 - CA55_CPU0 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu0(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu0_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu0_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu1_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu1_SHIFT (3U) /*! A55_cpu1 - CA55_CPU1 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu1_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu1_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu2_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu2_SHIFT (4U) /*! A55_cpu2 - CA55_CPU2 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu2_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu2_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu3_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu3_SHIFT (5U) /*! A55_cpu3 - CA55_CPU3 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu3_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu3_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu4_MASK (0x40U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu4_SHIFT (6U) /*! A55_cpu4 - CA55_CPU4 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu4_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu4_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu5_MASK (0x80U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu5_SHIFT (7U) /*! A55_cpu5 - CA55_CPU5 low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu5_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_cpu5_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_platform_MASK (0x100U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_platform_SHIFT (8U) /*! A55_platform - CA55_Platform low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_A55_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_ddr_MASK (0x200U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_ddr_SHIFT (9U) /*! ddr - DDR domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_ddr(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_ddr_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_ddr_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_display_MASK (0x400U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_display_SHIFT (10U) /*! display - Display domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_display(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_display_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_display_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_gpu_MASK (0x800U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_gpu_SHIFT (11U) /*! gpu - GPU domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_gpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_gpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_gpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_top_MASK (0x1000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_top_SHIFT (12U) /*! hsio_top - HSIO domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_top(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_top_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_top_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_aon_MASK (0x2000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_aon_SHIFT (13U) /*! hsio_aon - HSIO_AON low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_aon(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_aon_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_hsio_aon_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_m7_platform_MASK (0x4000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_m7_platform_SHIFT (14U) /*! m7_platform - M7 Platform low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_m7_platform(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_m7_platform_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_m7_platform_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_netc_MASK (0x8000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_netc_SHIFT (15U) /*! netc - NETC domain low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_netc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_netc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_netc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_noc_MASK (0x10000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_noc_SHIFT (16U) /*! noc - NOC low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_noc(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_noc_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_noc_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_npu_MASK (0x20000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_npu_SHIFT (17U) /*! npu - NPU low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_npu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_npu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_npu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_vpu_MASK (0x40000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_vpu_SHIFT (18U) /*! vpu - VPU low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_vpu(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_vpu_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_vpu_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_wakeup_MASK (0x80000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_wakeup_SHIFT (19U) /*! wakeup - WAKEUP low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_wakeup(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_wakeup_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_wakeup_MASK) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_osc24mhz_MASK (0x100000U) #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_osc24mhz_SHIFT (20U) /*! osc24mhz - OSC 24MHz low power handshake enable * 0b1..Enable * 0b0..Disable */ #define AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_osc24mhz(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_osc24mhz_SHIFT)) & AON_BLK_CTRL_S_AONMIX_LP_HANDSHAKE2_SM_osc24mhz_MASK) /*! @} */ /*! @name SM_LP_HANDSHAKE_STATUS - Register interface for system manager to react for the lp_handshake */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_ack_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_ack_SHIFT (0U) /*! ack - Acknowledge for the lp request * 0b0..No acknowledge * 0b1..Acknowledge */ #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_ack(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_ack_SHIFT)) & AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_ack_MASK) #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_stat_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_stat_SHIFT (1U) /*! stat - Status for clock/reset/power * 0b1..On * 0b0..Off */ #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_stat(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_stat_SHIFT)) & AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_stat_MASK) #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_idx_MASK (0x1FCU) #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_idx_SHIFT (2U) /*! idx - ID of the active lp request */ #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_idx(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_idx_SHIFT)) & AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_idx_MASK) #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_autoack_MASK (0x200U) #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_autoack_SHIFT (9U) /*! autoack - Auto acknowledge enable bit * 0b1..Auto acknowledge enabled * 0b0..Auto acknowledge disabled */ #define AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_autoack(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_autoack_SHIFT)) & AON_BLK_CTRL_S_AONMIX_SM_LP_HANDSHAKE_STATUS_autoack_MASK) /*! @} */ /*! @name CA55_CPUWAIT - CPUWAIT settings for CA55 CPU */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_SHIFT (0U) /*! CPU0_WAIT - Configure CPU0 in CPU WAIT mode * 0b1..Core stops working * 0b0..Core works normally */ #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU0_WAIT_MASK) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_SHIFT (1U) /*! CPU1_WAIT - Configure CPU1 in CPU WAIT mode * 0b1..Core stops working * 0b0..Core works normally */ #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU1_WAIT_MASK) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU2_WAIT_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU2_WAIT_SHIFT (2U) /*! CPU2_WAIT - Configure CPU2 in CPU WAIT mode * 0b1..Core stops working * 0b0..Core works normally */ #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU2_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU2_WAIT_MASK) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU3_WAIT_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU3_WAIT_SHIFT (3U) /*! CPU3_WAIT - Configure CPU3 in CPU WAIT mode * 0b1..Core stops working * 0b0..Core works normally */ #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU3_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU3_WAIT_MASK) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU4_WAIT_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU4_WAIT_SHIFT (4U) /*! CPU4_WAIT - Configure CPU4 in CPU WAIT mode * 0b1..Core stops working * 0b0..Core works normally */ #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU4_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU4_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU4_WAIT_MASK) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU5_WAIT_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU5_WAIT_SHIFT (5U) /*! CPU5_WAIT - Configure CPU5 in CPU WAIT mode * 0b0..Core works normally * 0b1..Core stops working */ #define AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU5_WAIT(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU5_WAIT_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_CPUWAIT_CPU5_WAIT_MASK) /*! @} */ /*! @name CA55_RVBARADDR0_L - CA55_RVBARADDR0_L */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_SHIFT (0U) /*! ADDR0_L - CA55_RVBARADDR0_L */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_L_ADDR0_L_MASK) /*! @} */ /*! @name CA55_RVBARADDR0_H - CA55_RVBARADDR0_H */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_MASK (0x3FU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_SHIFT (0U) /*! ADDR0_H - Higher 6 bits of the boot address of CA55 core0 in 64-bit mode */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR0_H_ADDR0_H_MASK) /*! @} */ /*! @name CA55_RVBARADDR1_L - CA55_RVBARADDR1_L */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_L_ADDR1_L_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_L_ADDR1_L_SHIFT (0U) /*! ADDR1_L - CA55_RVBARADDR1_L */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_L_ADDR1_L(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_L_ADDR1_L_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_L_ADDR1_L_MASK) /*! @} */ /*! @name CA55_RVBARADDR1_H - CA55_RVBARADDR1_H */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_H_ADDR1_H_MASK (0x3FU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_H_ADDR1_H_SHIFT (0U) /*! ADDR1_H - CA55_RVBARADDR1_H */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_H_ADDR1_H(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_H_ADDR1_H_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR1_H_ADDR1_H_MASK) /*! @} */ /*! @name CA55_RVBARADDR2_L - CA55_RVBARADDR2_L */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_L_ADDR2_L_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_L_ADDR2_L_SHIFT (0U) /*! ADDR2_L - CA55_RVBARADDR2_L */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_L_ADDR2_L(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_L_ADDR2_L_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_L_ADDR2_L_MASK) /*! @} */ /*! @name CA55_RVBARADDR2_H - CA55_RVBARADDR2_H */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_H_ADDR2_H_MASK (0x3FU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_H_ADDR2_H_SHIFT (0U) /*! ADDR2_H - CA55_RVBARADDR2_H */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_H_ADDR2_H(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_H_ADDR2_H_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR2_H_ADDR2_H_MASK) /*! @} */ /*! @name CA55_RVBARADDR3_L - CA55_RVBARADDR3_L */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_L_ADDR3_L_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_L_ADDR3_L_SHIFT (0U) /*! ADDR3_L - CA55_RVBARADDR3_L */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_L_ADDR3_L(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_L_ADDR3_L_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_L_ADDR3_L_MASK) /*! @} */ /*! @name CA55_RVBARADDR3_H - CA55_RVBARADDR3_H */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_H_ADDR3_H_MASK (0x3FU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_H_ADDR3_H_SHIFT (0U) /*! ADDR3_H - CA55_RVBARADDR3_H */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_H_ADDR3_H(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_H_ADDR3_H_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR3_H_ADDR3_H_MASK) /*! @} */ /*! @name CA55_RVBARADDR4_L - CA55_RVBARADDR4_L */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_L_ADDR4_L_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_L_ADDR4_L_SHIFT (0U) /*! ADDR4_L - CA55_RVBARADDR4_L */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_L_ADDR4_L(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_L_ADDR4_L_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_L_ADDR4_L_MASK) /*! @} */ /*! @name CA55_RVBARADDR4_H - CA55_RVBARADDR4_H */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_H_ADDR4_H_MASK (0x3FU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_H_ADDR4_H_SHIFT (0U) /*! ADDR4_H - CA55_RVBARADDR4_H */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_H_ADDR4_H(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_H_ADDR4_H_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR4_H_ADDR4_H_MASK) /*! @} */ /*! @name CA55_RVBARADDR5_L - CA55_RVBARADDR5_L */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_L_ADDR5_L_MASK (0xFFFFFFFFU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_L_ADDR5_L_SHIFT (0U) /*! ADDR5_L - CA55_RVBARADDR5_L */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_L_ADDR5_L(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_L_ADDR5_L_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_L_ADDR5_L_MASK) /*! @} */ /*! @name CA55_RVBARADDR5_H - CA55_RVBARADDR5_H */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_H_ADDR5_H_MASK (0x3FU) #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_H_ADDR5_H_SHIFT (0U) /*! ADDR5_H - CA55_RVBARADDR5_H */ #define AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_H_ADDR5_H(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_H_ADDR5_H_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_RVBARADDR5_H_ADDR5_H_MASK) /*! @} */ /*! @name ELE_IRQ_MASK - Mask bits of ELE interrupt */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet0_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet0_SHIFT (0U) /*! noclk_fdet0 - Missing ELE clock reset request. * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet0(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet0_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet0_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet1_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet1_SHIFT (1U) /*! noclk_fdet1 - Missing reference clock reset request. * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet1_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet1_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet2_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet2_SHIFT (2U) /*! noclk_fdet2 - Missing ELE clock reset request. * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet2_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet2_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet3_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet3_SHIFT (3U) /*! noclk_fdet3 - Missing reference clock reset request. * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet3_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_noclk_fdet3_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_32k_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_32k_SHIFT (4U) /*! reset_req_32k - Reset request for missing reference clock. * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_32k(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_32k_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_32k_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_SHIFT (5U) /*! reset_req - Edgelock enclave reset request, active low * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_reset_req_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_sys_fail_MASK (0x40U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_sys_fail_SHIFT (6U) /*! sys_fail - System failure, reset chip * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_sys_fail(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_sys_fail_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_sys_fail_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_lc_bricked_MASK (0x80U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_lc_bricked_SHIFT (7U) /*! lc_bricked - Lifecycle is in bricked state * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_lc_bricked(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_lc_bricked_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_lc_bricked_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_wdg_reset_MASK (0x200U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_wdg_reset_SHIFT (9U) /*! wdg_reset - WDOG reset * 0b1..Mask interrupt * 0b0..Unmask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_wdg_reset(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_wdg_reset_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_wdg_reset_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_rx_full_mask_MASK (0x10000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_rx_full_mask_SHIFT (16U) /*! mu0a_int_rx_full_mask - MU0A interrupt Rx full * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_rx_full_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_rx_full_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_rx_full_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_tx_empty_mask_MASK (0x20000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_tx_empty_mask_SHIFT (17U) /*! mu0a_int_tx_empty_mask - MU0A interrupt Tx empty * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_tx_empty_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_tx_empty_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu0a_int_tx_empty_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_rx_full_mask_MASK (0x40000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_rx_full_mask_SHIFT (18U) /*! mu1a_int_rx_full_mask - MU1A interrupt Rx full * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_rx_full_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_rx_full_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_rx_full_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_tx_empty_mask_MASK (0x80000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_tx_empty_mask_SHIFT (19U) /*! mu1a_int_tx_empty_mask - MU1A interrupt Tx empty * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_tx_empty_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_tx_empty_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu1a_int_tx_empty_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_rx_full_mask_MASK (0x100000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_rx_full_mask_SHIFT (20U) /*! mu2a_int_rx_full_mask - MU2A interrupt Rx full * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_rx_full_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_rx_full_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_rx_full_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_tx_empty_mask_MASK (0x200000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_tx_empty_mask_SHIFT (21U) /*! mu2a_int_tx_empty_mask - MU2A interrupt Tx empty * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_tx_empty_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_tx_empty_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu2a_int_tx_empty_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_rx_full_mask_MASK (0x400000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_rx_full_mask_SHIFT (22U) /*! mu3a_int_rx_full_mask - MU3A interrupt Rx full * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_rx_full_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_rx_full_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_rx_full_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_tx_empty_mask_MASK (0x800000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_tx_empty_mask_SHIFT (23U) /*! mu3a_int_tx_empty_mask - MU3A interrupt Tx empty * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_tx_empty_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_tx_empty_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu3a_int_tx_empty_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_rx_full_mask_MASK (0x1000000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_rx_full_mask_SHIFT (24U) /*! mu4a_int_rx_full_mask - MU4A interrupt Rx full * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_rx_full_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_rx_full_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_rx_full_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_tx_empty_mask_MASK (0x2000000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_tx_empty_mask_SHIFT (25U) /*! mu4a_int_tx_empty_mask - MU4A interrupt Tx empty * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_tx_empty_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_tx_empty_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu4a_int_tx_empty_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_rx_full_mask_MASK (0x4000000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_rx_full_mask_SHIFT (26U) /*! mu5a_int_rx_full_mask - MU5A interrupt Rx full * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_rx_full_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_rx_full_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_rx_full_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_tx_empty_mask_MASK (0x8000000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_tx_empty_mask_SHIFT (27U) /*! mu5a_int_tx_empty_mask - MU5A interrupt Tx empty * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_tx_empty_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_tx_empty_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_mu5a_int_tx_empty_mask_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_event_sys_mask_MASK (0x10000000U) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_event_sys_mask_SHIFT (28U) /*! event_sys_mask - EVENT_SYS reset * 0b0..Unmask interrupt * 0b1..Mask interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_event_sys_mask(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_event_sys_mask_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_MASK_event_sys_mask_MASK) /*! @} */ /*! @name ELE_RESET_REQ_MASK - Mask bits of ELE reset */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet0_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet0_SHIFT (0U) /*! noclk_fdet0 - Missing ELE clock reset request. * 0b0..Unmask reset request * 0b1..Mask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet0(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet0_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet0_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet1_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet1_SHIFT (1U) /*! noclk_fdet1 - Missing reference clock reset request. * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet1_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet1_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet2_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet2_SHIFT (2U) /*! noclk_fdet2 - Missing ELE clock reset request. * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet2_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet2_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet3_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet3_SHIFT (3U) /*! noclk_fdet3 - Missing reference clock reset request. * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet3_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_noclk_fdet3_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_reset_req_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_reset_req_SHIFT (4U) /*! sys_reset_req - System reset request * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_reset_req(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_reset_req_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_reset_req_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_32k_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_32k_SHIFT (5U) /*! reset_req_32k - Reset request for missing reference clock. * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_32k(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_32k_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_32k_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_MASK (0x40U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_SHIFT (6U) /*! reset_req - Edgelock enclave reset request * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_reset_req_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_fail_MASK (0x80U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_fail_SHIFT (7U) /*! sys_fail - System failure, reset chip * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_fail(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_fail_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_sys_fail_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_lc_bricked_MASK (0x100U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_lc_bricked_SHIFT (8U) /*! lc_bricked - Lifecycle is bricked state * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_lc_bricked(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_lc_bricked_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_lc_bricked_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_wdg_reset_MASK (0x400U) #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_wdg_reset_SHIFT (10U) /*! wdg_reset - Watchdog reset request * 0b1..Mask reset request * 0b0..Unmask reset request */ #define AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_wdg_reset(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_wdg_reset_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RESET_REQ_MASK_wdg_reset_MASK) /*! @} */ /*! @name ELE_HALT_STATUS - ELE Halt Status Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_ACK_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_ACK_SHIFT (0U) /*! ELE_HALT_ACK - EdgeLock halt and clock status * 0b1..Remove the clear signal. This bit is not self-clearing and need SW to clear. * 0b0..Clear EdgeLock halt exit interrupt */ #define AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_ACK(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_ACK_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_ACK_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_EXIT_IRQ_CLR_MASK (0x100U) #define AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_EXIT_IRQ_CLR_SHIFT (8U) /*! ELE_HALT_EXIT_IRQ_CLR - EdgeLock halt exit interrupt clear * 0b0..EdgeLock is not fully halted and its clocks must be enabled * 0b1..EdgeLock is fully halted indicating clocks may be removed */ #define AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_EXIT_IRQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_EXIT_IRQ_CLR_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_HALT_STATUS_ELE_HALT_EXIT_IRQ_CLR_MASK) /*! @} */ /*! @name CA55_MODE - Control the boot mode of two ca55 cores */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_CA55_MODE_AA64nAA32_MASK (0x3FU) #define AON_BLK_CTRL_S_AONMIX_CA55_MODE_AA64nAA32_SHIFT (0U) /*! AA64nAA32 - core0 initial mode control bit * 0b000000..State after reset is AARCH32 * 0b000001..State after reset is AARCH64 */ #define AON_BLK_CTRL_S_AONMIX_CA55_MODE_AA64nAA32(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_CA55_MODE_AA64nAA32_SHIFT)) & AON_BLK_CTRL_S_AONMIX_CA55_MODE_AA64nAA32_MASK) /*! @} */ /*! @name NMI_MASK - NMI MASK bits */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM33_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM33_SHIFT (0U) /*! CM33 - CM33 NMI mask bit * 0b0..NMI is usable * 0b1..NMI is masked */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM33(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM33_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM33_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM7_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM7_SHIFT (1U) /*! CM7 - CM7 NMI mask * 0b1..NMI is masked * 0b0..NMI is usable */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM7(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM7_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_CM7_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_NMI_PIN_MASK_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_NMI_PIN_MASK_SHIFT (2U) /*! NMI_PIN_MASK - NMI PIN mask bit * 0b1..NMI is masked * 0b0..NMI is usable */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_NMI_PIN_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_NMI_PIN_MASK_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_NMI_PIN_MASK_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG1_NMI_MASK_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG1_NMI_MASK_SHIFT (3U) /*! WDG1_NMI_MASK - WDG1 NMI mask bit * 0b1..NMI is masked * 0b0..NMI is usable */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG1_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG1_NMI_MASK_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG1_NMI_MASK_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG2_NMI_MASK_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG2_NMI_MASK_SHIFT (4U) /*! WDG2_NMI_MASK - WDG2 NMI mask bit * 0b1..NMI is masked * 0b0..NMI is usable */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG2_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG2_NMI_MASK_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG2_NMI_MASK_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG3_NMI_MASK_MASK (0x20U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG3_NMI_MASK_SHIFT (5U) /*! WDG3_NMI_MASK - WDG3 NMI mask bit * 0b1..NMI is masked * 0b0..NMI is usable */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG3_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG3_NMI_MASK_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG3_NMI_MASK_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG4_NMI_MASK_MASK (0x40U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG4_NMI_MASK_SHIFT (6U) /*! WDG4_NMI_MASK - WDG4 NMI mask bit * 0b1..NMI is masked * 0b0..NMI is usable */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG4_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG4_NMI_MASK_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG4_NMI_MASK_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG5_NMI_MASK_MASK (0x80U) #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG5_NMI_MASK_SHIFT (7U) /*! WDG5_NMI_MASK - WDG5 NMI mask bit * 0b1..NMI is masked * 0b0..NMI is usable */ #define AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG5_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG5_NMI_MASK_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_MASK_WDG5_NMI_MASK_MASK) /*! @} */ /*! @name NMI_CLR - NMI clear bit */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM33_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM33_SHIFT (0U) /*! CM33 - CM33 NMI clear */ #define AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM33(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM33_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM33_MASK) #define AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM7_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM7_SHIFT (1U) /*! CM7 - CM7 NMI clear */ #define AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM7(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM7_SHIFT)) & AON_BLK_CTRL_S_AONMIX_NMI_CLR_CM7_MASK) /*! @} */ /*! @name WDOG_ANY_MASK - Wdog any mask */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog1_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog1_SHIFT (0U) /*! wdog1 - wdog1 to wdog_any mask bit * 0b1..Mask * 0b0..Unmask */ #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog1(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog1_SHIFT)) & AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog1_MASK) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog2_MASK (0x2U) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog2_SHIFT (1U) /*! wdog2 - wdog2 to wdog_any mask bit * 0b1..Mask * 0b0..Unmask */ #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog2(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog2_SHIFT)) & AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog2_MASK) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog3_MASK (0x4U) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog3_SHIFT (2U) /*! wdog3 - wdog3 to wdog_any mask bit * 0b1..Mask * 0b0..Unmask */ #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog3(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog3_SHIFT)) & AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog3_MASK) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog4_MASK (0x8U) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog4_SHIFT (3U) /*! wdog4 - wdog4 to wdog_any mask bit * 0b0..Unmask * 0b1..Mask */ #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog4(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog4_SHIFT)) & AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog4_MASK) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog5_MASK (0x10U) #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog5_SHIFT (4U) /*! wdog5 - wdog5 to wdog_any mask bit * 0b1..Mask * 0b0..Unmask */ #define AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog5(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog5_SHIFT)) & AON_BLK_CTRL_S_AONMIX_WDOG_ANY_MASK_wdog5_MASK) /*! @} */ /*! @name MISC_CFG - Miscellaneous Configure Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_MISC_CFG_netc_cfg_ierb_lock_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_MISC_CFG_netc_cfg_ierb_lock_SHIFT (0U) /*! netc_cfg_ierb_lock - netc.cfg_ierb_lock bit */ #define AON_BLK_CTRL_S_AONMIX_MISC_CFG_netc_cfg_ierb_lock(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_MISC_CFG_netc_cfg_ierb_lock_SHIFT)) & AON_BLK_CTRL_S_AONMIX_MISC_CFG_netc_cfg_ierb_lock_MASK) /*! @} */ /*! @name ELE_GPO_STATUS - ELE gpo status register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_ELE_GPO_STATUS_ELE_GPO_8_MASK (0x1U) #define AON_BLK_CTRL_S_AONMIX_ELE_GPO_STATUS_ELE_GPO_8_SHIFT (0U) /*! ELE_GPO_8 - ELE GPO status */ #define AON_BLK_CTRL_S_AONMIX_ELE_GPO_STATUS_ELE_GPO_8(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_GPO_STATUS_ELE_GPO_8_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_GPO_STATUS_ELE_GPO_8_MASK) /*! @} */ /*! @name ELE_RST_REQ_STAT - ELE Reset Request Status Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_A_MASK (0xFFFFU) #define AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_A_SHIFT (0U) /*! GROUP_A - Group A CSSI events */ #define AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_A(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_A_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_A_MASK) #define AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_B_MASK (0xFFFF0000U) #define AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_B_SHIFT (16U) /*! GROUP_B - Group B RST events */ #define AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_B(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_B_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_RST_REQ_STAT_GROUP_B_MASK) /*! @} */ /*! @name ELE_IRQ_REQ_STAT - ELE IRQ Request Status Register */ /*! @{ */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_REQ_STAT_GROUP_C_MASK (0xFFFFU) #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_REQ_STAT_GROUP_C_SHIFT (0U) /*! GROUP_C - Group C IRQ events */ #define AON_BLK_CTRL_S_AONMIX_ELE_IRQ_REQ_STAT_GROUP_C(x) (((uint32_t)(((uint32_t)(x)) << AON_BLK_CTRL_S_AONMIX_ELE_IRQ_REQ_STAT_GROUP_C_SHIFT)) & AON_BLK_CTRL_S_AONMIX_ELE_IRQ_REQ_STAT_GROUP_C_MASK) /*! @} */ /*! * @} */ /* end of group AON_BLK_CTRL_S_AONMIX_Register_Masks */ /* AON_BLK_CTRL_S_AONMIX - Peripheral instance base addresses */ /** Peripheral AON__BLK_CTRL_S_AONMIX2 base address */ #define AON__BLK_CTRL_S_AONMIX2_BASE (0x444F0000u) /** Peripheral AON__BLK_CTRL_S_AONMIX2 base pointer */ #define AON__BLK_CTRL_S_AONMIX2 ((AON_BLK_CTRL_S_AONMIX_Type *)AON__BLK_CTRL_S_AONMIX2_BASE) /** Array initializer of AON_BLK_CTRL_S_AONMIX peripheral base addresses */ #define AON_BLK_CTRL_S_AONMIX_BASE_ADDRS { AON__BLK_CTRL_S_AONMIX2_BASE } /** Array initializer of AON_BLK_CTRL_S_AONMIX peripheral base pointers */ #define AON_BLK_CTRL_S_AONMIX_BASE_PTRS { AON__BLK_CTRL_S_AONMIX2 } /*! * @} */ /* end of group AON_BLK_CTRL_S_AONMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_CMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_CMU_Peripheral_Access_Layer AON_CMU Peripheral Access Layer * @{ */ /** AON_CMU - Register Layout Typedef */ typedef struct { __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ __IO uint32_t SR; /**< Status Register, offset: 0x10 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ } AON_CMU_Type; /* ---------------------------------------------------------------------------- -- AON_CMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_CMU_Register_Masks AON_CMU Register Masks * @{ */ /*! @name GCR - Global Configuration Register */ /*! @{ */ #define AON_CMU_GCR_FCE_MASK (0x1U) #define AON_CMU_GCR_FCE_SHIFT (0U) /*! FCE - Frequency Check Enable * 0b0..Stops frequency checking * 0b1..Starts frequency checking */ #define AON_CMU_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_GCR_FCE_SHIFT)) & AON_CMU_GCR_FCE_MASK) /*! @} */ /*! @name RCCR - Reference Count Configuration Register */ /*! @{ */ #define AON_CMU_RCCR_REF_CNT_MASK (0xFFFFU) #define AON_CMU_RCCR_REF_CNT_SHIFT (0U) /*! REF_CNT - Reference clock count */ #define AON_CMU_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_RCCR_REF_CNT_SHIFT)) & AON_CMU_RCCR_REF_CNT_MASK) /*! @} */ /*! @name HTCR - High Threshold Configuration Register */ /*! @{ */ #define AON_CMU_HTCR_HFREF_MASK (0xFFFFFFU) #define AON_CMU_HTCR_HFREF_SHIFT (0U) /*! HFREF - High frequency reference threshold */ #define AON_CMU_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_HTCR_HFREF_SHIFT)) & AON_CMU_HTCR_HFREF_MASK) /*! @} */ /*! @name LTCR - Low Threshold Configuration Register */ /*! @{ */ #define AON_CMU_LTCR_LFREF_MASK (0xFFFFFFU) #define AON_CMU_LTCR_LFREF_SHIFT (0U) /*! LFREF - Low Frequency Reference Threshold */ #define AON_CMU_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_LTCR_LFREF_SHIFT)) & AON_CMU_LTCR_LFREF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define AON_CMU_SR_FLL_MASK (0x1U) #define AON_CMU_SR_FLL_SHIFT (0U) /*! FLL - Frequency lower than low frequency reference threshold event status * 0b0..No FLL event * 0b1..FLL event occurred */ #define AON_CMU_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_SR_FLL_SHIFT)) & AON_CMU_SR_FLL_MASK) #define AON_CMU_SR_FHH_MASK (0x2U) #define AON_CMU_SR_FHH_SHIFT (1U) /*! FHH - Frequency higher than high frequency reference threshold event status * 0b0..No FHH event * 0b1..FHH event occurred */ #define AON_CMU_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_SR_FHH_SHIFT)) & AON_CMU_SR_FHH_MASK) #define AON_CMU_SR_RS_MASK (0x10U) #define AON_CMU_SR_RS_SHIFT (4U) /*! RS - Run Status * 0b0..Frequency check stopped * 0b1..Frequency check running */ #define AON_CMU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_SR_RS_SHIFT)) & AON_CMU_SR_RS_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define AON_CMU_IER_FLLAIE_MASK (0x4U) #define AON_CMU_IER_FLLAIE_SHIFT (2U) /*! FLLAIE - Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FLL event interrupt disabled * 0b1..Asynchronous FLL event interrupt enabled */ #define AON_CMU_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_IER_FLLAIE_SHIFT)) & AON_CMU_IER_FLLAIE_MASK) #define AON_CMU_IER_FHHAIE_MASK (0x8U) #define AON_CMU_IER_FHHAIE_SHIFT (3U) /*! FHHAIE - Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FHH event interrupt disabled * 0b1..Asynchronous FHH event interrupt enabled */ #define AON_CMU_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << AON_CMU_IER_FHHAIE_SHIFT)) & AON_CMU_IER_FHHAIE_MASK) /*! @} */ /*! * @} */ /* end of group AON_CMU_Register_Masks */ /* AON_CMU - Peripheral instance base addresses */ /** Peripheral AON__CMUA1 base address */ #define AON__CMUA1_BASE (0x44540000u) /** Peripheral AON__CMUA1 base pointer */ #define AON__CMUA1 ((AON_CMU_Type *)AON__CMUA1_BASE) /** Peripheral AON__CMUA2 base address */ #define AON__CMUA2_BASE (0x44650000u) /** Peripheral AON__CMUA2 base pointer */ #define AON__CMUA2 ((AON_CMU_Type *)AON__CMUA2_BASE) /** Array initializer of AON_CMU peripheral base addresses */ #define AON_CMU_BASE_ADDRS { AON__CMUA1_BASE, AON__CMUA2_BASE } /** Array initializer of AON_CMU peripheral base pointers */ #define AON_CMU_BASE_PTRS { AON__CMUA1, AON__CMUA2 } /*! * @} */ /* end of group AON_CMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_CRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_CRC_Peripheral_Access_Layer AON_CRC Peripheral Access Layer * @{ */ /** AON_CRC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ __IO uint32_t CFG; /**< Configuration Register, array offset: 0x0, array step: 0x10 */ __IO uint32_t INP; /**< Input Register, array offset: 0x4, array step: 0x10 */ __IO uint32_t CSTAT; /**< Current Status Register, array offset: 0x8, array step: 0x10 */ __I uint32_t OUTP; /**< Output Register, array offset: 0xC, array step: 0x10 */ } CHANNEL[3]; } AON_CRC_Type; /* ---------------------------------------------------------------------------- -- AON_CRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_CRC_Register_Masks AON_CRC Register Masks * @{ */ /*! @name CFG - Configuration Register */ /*! @{ */ #define AON_CRC_CFG_INV_MASK (0x1U) #define AON_CRC_CFG_INV_SHIFT (0U) /*! INV - Inversion selection * 0b0..No inversion selection applied on the CRC_OUTP content * 0b1..Inversion selection (bit x bit) applied on the CRC_OUTP content */ #define AON_CRC_CFG_INV(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_CFG_INV_SHIFT)) & AON_CRC_CFG_INV_MASK) #define AON_CRC_CFG_SWAP_MASK (0x2U) #define AON_CRC_CFG_SWAP_SHIFT (1U) /*! SWAP - Swap selection * 0b0..No swap selection applied on the CRC_OUTP content * 0b1..Swap selection (MSB to LSB, LSB to MSB) applied to the CRC_OUTP content */ #define AON_CRC_CFG_SWAP(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_CFG_SWAP_SHIFT)) & AON_CRC_CFG_SWAP_MASK) #define AON_CRC_CFG_POLYG_MASK (0xCU) #define AON_CRC_CFG_POLYG_SHIFT (2U) /*! POLYG - Polynomial selection * 0b00..CRC-CCITT polynomial * 0b01..CRC-32 polynomial * 0b10..CRC-8 polynomial * 0b11..CRC-8-H2F AUTOSAR polynomial */ #define AON_CRC_CFG_POLYG(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_CFG_POLYG_SHIFT)) & AON_CRC_CFG_POLYG_MASK) #define AON_CRC_CFG_SWAP_BITWISE_MASK (0x10U) #define AON_CRC_CFG_SWAP_BITWISE_SHIFT (4U) /*! SWAP_BITWISE - Swap CRC_INP bit-wise * 0b0..Do not swap * 0b1..Perform bit-wise swap on CRC_INP input data internally for CRC-8 and CRC-16 and CRC-32 polynomial calculations */ #define AON_CRC_CFG_SWAP_BITWISE(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_CFG_SWAP_BITWISE_SHIFT)) & AON_CRC_CFG_SWAP_BITWISE_MASK) #define AON_CRC_CFG_SWAP_BYTEWISE_MASK (0x20U) #define AON_CRC_CFG_SWAP_BYTEWISE_SHIFT (5U) /*! SWAP_BYTEWISE - Swap CRC_INP byte-wise * 0b0..Do not swap * 0b1..Perform byte-wise swap on CRC_INP input data internally for CRC-16 and CRC-32 polynomial calculations */ #define AON_CRC_CFG_SWAP_BYTEWISE(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_CFG_SWAP_BYTEWISE_SHIFT)) & AON_CRC_CFG_SWAP_BYTEWISE_MASK) /*! @} */ /* The count of AON_CRC_CFG */ #define AON_CRC_CFG_COUNT (3U) /*! @name INP - Input Register */ /*! @{ */ #define AON_CRC_INP_INP_MASK (0xFFFFFFFFU) #define AON_CRC_INP_INP_SHIFT (0U) /*! INP - Input data for the CRC computation */ #define AON_CRC_INP_INP(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_INP_INP_SHIFT)) & AON_CRC_INP_INP_MASK) /*! @} */ /* The count of AON_CRC_INP */ #define AON_CRC_INP_COUNT (3U) /*! @name CSTAT - Current Status Register */ /*! @{ */ #define AON_CRC_CSTAT_CSTAT_MASK (0xFFFFFFFFU) #define AON_CRC_CSTAT_CSTAT_SHIFT (0U) /*! CSTAT - CRC signature status */ #define AON_CRC_CSTAT_CSTAT(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_CSTAT_CSTAT_SHIFT)) & AON_CRC_CSTAT_CSTAT_MASK) /*! @} */ /* The count of AON_CRC_CSTAT */ #define AON_CRC_CSTAT_COUNT (3U) /*! @name OUTP - Output Register */ /*! @{ */ #define AON_CRC_OUTP_OUTP_MASK (0xFFFFFFFFU) #define AON_CRC_OUTP_OUTP_SHIFT (0U) /*! OUTP - Final CRC signature */ #define AON_CRC_OUTP_OUTP(x) (((uint32_t)(((uint32_t)(x)) << AON_CRC_OUTP_OUTP_SHIFT)) & AON_CRC_OUTP_OUTP_MASK) /*! @} */ /* The count of AON_CRC_OUTP */ #define AON_CRC_OUTP_COUNT (3U) /*! * @} */ /* end of group AON_CRC_Register_Masks */ /* AON_CRC - Peripheral instance base addresses */ /** Peripheral AON__CRCA base address */ #define AON__CRCA_BASE (0x44660000u) /** Peripheral AON__CRCA base pointer */ #define AON__CRCA ((AON_CRC_Type *)AON__CRCA_BASE) /** Array initializer of AON_CRC peripheral base addresses */ #define AON_CRC_BASE_ADDRS { AON__CRCA_BASE } /** Array initializer of AON_CRC peripheral base pointers */ #define AON_CRC_BASE_PTRS { AON__CRCA } /*! * @} */ /* end of group AON_CRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_CSTCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_CSTCU_Peripheral_Access_Layer AON_CSTCU Peripheral Access Layer * @{ */ /** AON_CSTCU - Register Layout Typedef */ typedef struct { __IO uint32_t RUNSWREG; /**< Run Software, offset: 0x0 */ __IO uint32_t LSCHLVLD; /**< LSTCU Scheduler List Valid, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t WDG; /**< Watchdog Timer, offset: 0xC */ __IO uint32_t IE; /**< Interrupt Enable, offset: 0x10 */ __IO uint32_t IF; /**< Interrupt Flag, offset: 0x14 */ uint8_t RESERVED_1[8]; __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x20 */ uint8_t RESERVED_2[4]; __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x28 */ uint8_t RESERVED_3[4]; __I uint32_t LRFSTAT[1]; /**< LSTCU Recoverable Fault Status, array offset: 0x30, array step: 0x4 */ uint8_t RESERVED_4[12]; __I uint32_t LUFSTAT[1]; /**< LSTCU Unrecoverable Fault Status, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_5[12]; __IO uint32_t RDEN; /**< Reset Domain Self-Test Enable, offset: 0x50 */ __I uint32_t RDENSTAT; /**< Reset Domain Enable Status, offset: 0x54 */ __I uint32_t LASTRDEN; /**< Last Run Reset Domain Enable, offset: 0x58 */ uint8_t RESERVED_6[4]; __IO uint32_t BYPLSTCU[1]; /**< Bypass LSTCU, array offset: 0x60, array step: 0x4 */ uint8_t RESERVED_7[12]; __IO uint32_t STAG; /**< Stagger, offset: 0x70 */ uint8_t RESERVED_8[396]; __IO uint32_t LMBPTR[5]; /**< LSTCU MBIST Run Phase Scheduler Pointer, array offset: 0x200, array step: 0x4 */ } AON_CSTCU_Type; /* ---------------------------------------------------------------------------- -- AON_CSTCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_CSTCU_Register_Masks AON_CSTCU Register Masks * @{ */ /*! @name RUNSWREG - Run Software */ /*! @{ */ #define AON_CSTCU_RUNSWREG_RUNSW_MASK (0x1U) #define AON_CSTCU_RUNSWREG_RUNSW_SHIFT (0U) /*! RUNSW - Run Software * 0b0..No self-test run in progress * 0b0..No effect * 0b1..Self-test in progress * 0b1..Starts self-test */ #define AON_CSTCU_RUNSWREG_RUNSW(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RUNSWREG_RUNSW_SHIFT)) & AON_CSTCU_RUNSWREG_RUNSW_MASK) #define AON_CSTCU_RUNSWREG_SW_ABORT_MASK (0x10U) #define AON_CSTCU_RUNSWREG_SW_ABORT_SHIFT (4U) /*! SW_ABORT - Software Abort * 0b0..No self-test abort request * 0b0..No effect * 0b1..Aborts self-test */ #define AON_CSTCU_RUNSWREG_SW_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RUNSWREG_SW_ABORT_SHIFT)) & AON_CSTCU_RUNSWREG_SW_ABORT_MASK) /*! @} */ /*! @name LSCHLVLD - LSTCU Scheduler List Valid */ /*! @{ */ #define AON_CSTCU_LSCHLVLD_MBPLVLD_MASK (0x100U) #define AON_CSTCU_LSCHLVLD_MBPLVLD_SHIFT (8U) /*! MBPLVLD - LSTCU MBIST Pointer List Valid * 0b0..Invalid * 0b1..Valid */ #define AON_CSTCU_LSCHLVLD_MBPLVLD(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LSCHLVLD_MBPLVLD_SHIFT)) & AON_CSTCU_LSCHLVLD_MBPLVLD_MASK) /*! @} */ /*! @name WDG - Watchdog Timer */ /*! @{ */ #define AON_CSTCU_WDG_WDGEOC_MASK (0xFFFFFFFFU) #define AON_CSTCU_WDG_WDGEOC_SHIFT (0U) /*! WDGEOC - Watchdog End of Counter */ #define AON_CSTCU_WDG_WDGEOC(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_WDG_WDGEOC_SHIFT)) & AON_CSTCU_WDG_WDGEOC_MASK) /*! @} */ /*! @name IE - Interrupt Enable */ /*! @{ */ #define AON_CSTCU_IE_STEND_IE_MASK (0x1U) #define AON_CSTCU_IE_STEND_IE_SHIFT (0U) /*! STEND_IE - Self-Test End Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define AON_CSTCU_IE_STEND_IE(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_IE_STEND_IE_SHIFT)) & AON_CSTCU_IE_STEND_IE_MASK) /*! @} */ /*! @name IF - Interrupt Flag */ /*! @{ */ #define AON_CSTCU_IF_STEND_IF_MASK (0x1U) #define AON_CSTCU_IF_STEND_IF_SHIFT (0U) /*! STEND_IF - Self-Test End Interrupt Flag * 0b0..No pending interrupt * 0b1..Pending interrupt * 0b0..No effect * 0b1..Clear the flag */ #define AON_CSTCU_IF_STEND_IF(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_IF_STEND_IF_SHIFT)) & AON_CSTCU_IF_STEND_IF_MASK) /*! @} */ /*! @name ERR_STAT - Error Status */ /*! @{ */ #define AON_CSTCU_ERR_STAT_INVP_MB_MASK (0x2U) #define AON_CSTCU_ERR_STAT_INVP_MB_SHIFT (1U) /*! INVP_MB - Invalid LSTCU Pointer During MBIST Scheduling * 0b0..No invalid LSTCU pointer * 0b1..Invalid LSTCU pointer */ #define AON_CSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_ERR_STAT_INVP_MB_SHIFT)) & AON_CSTCU_ERR_STAT_INVP_MB_MASK) #define AON_CSTCU_ERR_STAT_ABORTHW_MASK (0x100U) #define AON_CSTCU_ERR_STAT_ABORTHW_SHIFT (8U) /*! ABORTHW - Hardware Abort Flag * 0b0..No abort detected * 0b1..Abort detected */ #define AON_CSTCU_ERR_STAT_ABORTHW(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_ERR_STAT_ABORTHW_SHIFT)) & AON_CSTCU_ERR_STAT_ABORTHW_MASK) #define AON_CSTCU_ERR_STAT_ABORTSW_MASK (0x200U) #define AON_CSTCU_ERR_STAT_ABORTSW_SHIFT (9U) /*! ABORTSW - Software Abort Flag * 0b0..No abort detected * 0b1..Abort detected */ #define AON_CSTCU_ERR_STAT_ABORTSW(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_ERR_STAT_ABORTSW_SHIFT)) & AON_CSTCU_ERR_STAT_ABORTSW_MASK) #define AON_CSTCU_ERR_STAT_UFSF_MASK (0x10000U) #define AON_CSTCU_ERR_STAT_UFSF_SHIFT (16U) /*! UFSF - Unrecoverable Fault Status Flag * 0b0..No unrecoverable fault occurred * 0b1..Unrecoverable fault occurred */ #define AON_CSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_ERR_STAT_UFSF_SHIFT)) & AON_CSTCU_ERR_STAT_UFSF_MASK) #define AON_CSTCU_ERR_STAT_RFSF_MASK (0x20000U) #define AON_CSTCU_ERR_STAT_RFSF_SHIFT (17U) /*! RFSF - Recoverable Fault Status Flag * 0b0..No recoverable fault occurred * 0b1..Recoverable fault occurred */ #define AON_CSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_ERR_STAT_RFSF_SHIFT)) & AON_CSTCU_ERR_STAT_RFSF_MASK) /*! @} */ /*! @name ERR_FM - Error Fault Mapping */ /*! @{ */ #define AON_CSTCU_ERR_FM_INVPFMMB_MASK (0x2U) #define AON_CSTCU_ERR_FM_INVPFMMB_SHIFT (1U) /*! INVPFMMB - MBIST Fault Mapping * 0b0..Recoverable fault * 0b1..Unrecoverable fault */ #define AON_CSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_ERR_FM_INVPFMMB_SHIFT)) & AON_CSTCU_ERR_FM_INVPFMMB_MASK) /*! @} */ /*! @name LRFSTAT - LSTCU Recoverable Fault Status */ /*! @{ */ #define AON_CSTCU_LRFSTAT_RFSLSTCU0_MASK (0x1U) #define AON_CSTCU_LRFSTAT_RFSLSTCU0_SHIFT (0U) /*! RFSLSTCU0 - Recoverable Fault Occurrence Status from LSTCU0 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LRFSTAT_RFSLSTCU0(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LRFSTAT_RFSLSTCU0_SHIFT)) & AON_CSTCU_LRFSTAT_RFSLSTCU0_MASK) #define AON_CSTCU_LRFSTAT_RFSLSTCU1_MASK (0x2U) #define AON_CSTCU_LRFSTAT_RFSLSTCU1_SHIFT (1U) /*! RFSLSTCU1 - Recoverable Fault Occurrence Status from LSTCU1 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LRFSTAT_RFSLSTCU1(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LRFSTAT_RFSLSTCU1_SHIFT)) & AON_CSTCU_LRFSTAT_RFSLSTCU1_MASK) #define AON_CSTCU_LRFSTAT_RFSLSTCU2_MASK (0x4U) #define AON_CSTCU_LRFSTAT_RFSLSTCU2_SHIFT (2U) /*! RFSLSTCU2 - Recoverable Fault Occurrence Status from LSTCU2 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LRFSTAT_RFSLSTCU2(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LRFSTAT_RFSLSTCU2_SHIFT)) & AON_CSTCU_LRFSTAT_RFSLSTCU2_MASK) #define AON_CSTCU_LRFSTAT_RFSLSTCU3_MASK (0x8U) #define AON_CSTCU_LRFSTAT_RFSLSTCU3_SHIFT (3U) /*! RFSLSTCU3 - Recoverable Fault Occurrence Status from LSTCU3 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LRFSTAT_RFSLSTCU3(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LRFSTAT_RFSLSTCU3_SHIFT)) & AON_CSTCU_LRFSTAT_RFSLSTCU3_MASK) #define AON_CSTCU_LRFSTAT_RFSLSTCU4_MASK (0x10U) #define AON_CSTCU_LRFSTAT_RFSLSTCU4_SHIFT (4U) /*! RFSLSTCU4 - Recoverable Fault Occurrence Status from LSTCU4 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LRFSTAT_RFSLSTCU4(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LRFSTAT_RFSLSTCU4_SHIFT)) & AON_CSTCU_LRFSTAT_RFSLSTCU4_MASK) /*! @} */ /* The count of AON_CSTCU_LRFSTAT */ #define AON_CSTCU_LRFSTAT_COUNT (1U) /*! @name LUFSTAT - LSTCU Unrecoverable Fault Status */ /*! @{ */ #define AON_CSTCU_LUFSTAT_UFSLSTCU0_MASK (0x1U) #define AON_CSTCU_LUFSTAT_UFSLSTCU0_SHIFT (0U) /*! UFSLSTCU0 - Unrecoverable Fault Occurrence Status from LSTCU0 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LUFSTAT_UFSLSTCU0(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LUFSTAT_UFSLSTCU0_SHIFT)) & AON_CSTCU_LUFSTAT_UFSLSTCU0_MASK) #define AON_CSTCU_LUFSTAT_UFSLSTCU1_MASK (0x2U) #define AON_CSTCU_LUFSTAT_UFSLSTCU1_SHIFT (1U) /*! UFSLSTCU1 - Unrecoverable Fault Occurrence Status from LSTCU1 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LUFSTAT_UFSLSTCU1(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LUFSTAT_UFSLSTCU1_SHIFT)) & AON_CSTCU_LUFSTAT_UFSLSTCU1_MASK) #define AON_CSTCU_LUFSTAT_UFSLSTCU2_MASK (0x4U) #define AON_CSTCU_LUFSTAT_UFSLSTCU2_SHIFT (2U) /*! UFSLSTCU2 - Unrecoverable Fault Occurrence Status from LSTCU2 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LUFSTAT_UFSLSTCU2(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LUFSTAT_UFSLSTCU2_SHIFT)) & AON_CSTCU_LUFSTAT_UFSLSTCU2_MASK) #define AON_CSTCU_LUFSTAT_UFSLSTCU3_MASK (0x8U) #define AON_CSTCU_LUFSTAT_UFSLSTCU3_SHIFT (3U) /*! UFSLSTCU3 - Unrecoverable Fault Occurrence Status from LSTCU3 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LUFSTAT_UFSLSTCU3(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LUFSTAT_UFSLSTCU3_SHIFT)) & AON_CSTCU_LUFSTAT_UFSLSTCU3_MASK) #define AON_CSTCU_LUFSTAT_UFSLSTCU4_MASK (0x10U) #define AON_CSTCU_LUFSTAT_UFSLSTCU4_SHIFT (4U) /*! UFSLSTCU4 - Unrecoverable Fault Occurrence Status from LSTCU4 * 0b0..Not occurred * 0b1..Occurred */ #define AON_CSTCU_LUFSTAT_UFSLSTCU4(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LUFSTAT_UFSLSTCU4_SHIFT)) & AON_CSTCU_LUFSTAT_UFSLSTCU4_MASK) /*! @} */ /* The count of AON_CSTCU_LUFSTAT */ #define AON_CSTCU_LUFSTAT_COUNT (1U) /*! @name RDEN - Reset Domain Self-Test Enable */ /*! @{ */ #define AON_CSTCU_RDEN_SERD0_MASK (0x1U) #define AON_CSTCU_RDEN_SERD0_SHIFT (0U) /*! SERD0 - Enable Self-Test in Reset Domain 0 * 0b0..Disable * 0b1..Enable */ #define AON_CSTCU_RDEN_SERD0(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RDEN_SERD0_SHIFT)) & AON_CSTCU_RDEN_SERD0_MASK) #define AON_CSTCU_RDEN_SERD1_MASK (0x2U) #define AON_CSTCU_RDEN_SERD1_SHIFT (1U) /*! SERD1 - Enable Self-Test in Reset Domain 1 * 0b0..Disable * 0b1..Enable */ #define AON_CSTCU_RDEN_SERD1(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RDEN_SERD1_SHIFT)) & AON_CSTCU_RDEN_SERD1_MASK) #define AON_CSTCU_RDEN_SERD2_MASK (0x4U) #define AON_CSTCU_RDEN_SERD2_SHIFT (2U) /*! SERD2 - Enable Self-Test in Reset Domain 2 * 0b0..Disable * 0b1..Enable */ #define AON_CSTCU_RDEN_SERD2(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RDEN_SERD2_SHIFT)) & AON_CSTCU_RDEN_SERD2_MASK) /*! @} */ /*! @name RDENSTAT - Reset Domain Enable Status */ /*! @{ */ #define AON_CSTCU_RDENSTAT_SESRD0_MASK (0x1U) #define AON_CSTCU_RDENSTAT_SESRD0_SHIFT (0U) /*! SESRD0 - Self-Test Enable Status in Reset Domain 0 * 0b0..Disabled * 0b1..Enabled */ #define AON_CSTCU_RDENSTAT_SESRD0(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RDENSTAT_SESRD0_SHIFT)) & AON_CSTCU_RDENSTAT_SESRD0_MASK) #define AON_CSTCU_RDENSTAT_SESRD1_MASK (0x2U) #define AON_CSTCU_RDENSTAT_SESRD1_SHIFT (1U) /*! SESRD1 - Self-Test Enable Status in Reset Domain 1 * 0b0..Disabled * 0b1..Enabled */ #define AON_CSTCU_RDENSTAT_SESRD1(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RDENSTAT_SESRD1_SHIFT)) & AON_CSTCU_RDENSTAT_SESRD1_MASK) #define AON_CSTCU_RDENSTAT_SESRD2_MASK (0x4U) #define AON_CSTCU_RDENSTAT_SESRD2_SHIFT (2U) /*! SESRD2 - Self-Test Enable Status in Reset Domain 2 * 0b0..Disabled * 0b1..Enabled */ #define AON_CSTCU_RDENSTAT_SESRD2(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_RDENSTAT_SESRD2_SHIFT)) & AON_CSTCU_RDENSTAT_SESRD2_MASK) /*! @} */ /*! @name LASTRDEN - Last Run Reset Domain Enable */ /*! @{ */ #define AON_CSTCU_LASTRDEN_LRSERD0_MASK (0x1U) #define AON_CSTCU_LASTRDEN_LRSERD0_SHIFT (0U) /*! LRSERD0 - Last Run Self-Test Enable Status in Reset Domain 0 * 0b0..Disabled * 0b1..Enabled */ #define AON_CSTCU_LASTRDEN_LRSERD0(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LASTRDEN_LRSERD0_SHIFT)) & AON_CSTCU_LASTRDEN_LRSERD0_MASK) #define AON_CSTCU_LASTRDEN_LRSERD1_MASK (0x2U) #define AON_CSTCU_LASTRDEN_LRSERD1_SHIFT (1U) /*! LRSERD1 - Last Run Self-Test Enable Status in Reset Domain 1 * 0b0..Disabled * 0b1..Enabled */ #define AON_CSTCU_LASTRDEN_LRSERD1(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LASTRDEN_LRSERD1_SHIFT)) & AON_CSTCU_LASTRDEN_LRSERD1_MASK) #define AON_CSTCU_LASTRDEN_LRSERD2_MASK (0x4U) #define AON_CSTCU_LASTRDEN_LRSERD2_SHIFT (2U) /*! LRSERD2 - Last Run Self-Test Enable Status in Reset Domain 2 * 0b0..Disabled * 0b1..Enabled */ #define AON_CSTCU_LASTRDEN_LRSERD2(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LASTRDEN_LRSERD2_SHIFT)) & AON_CSTCU_LASTRDEN_LRSERD2_MASK) /*! @} */ /*! @name BYPLSTCU - Bypass LSTCU */ /*! @{ */ #define AON_CSTCU_BYPLSTCU_BYP_L0_MASK (0x1U) #define AON_CSTCU_BYPLSTCU_BYP_L0_SHIFT (0U) /*! BYP_L0 - Bypass LSTCU 0 * 0b0..No bypass * 0b1..Bypass */ #define AON_CSTCU_BYPLSTCU_BYP_L0(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_BYPLSTCU_BYP_L0_SHIFT)) & AON_CSTCU_BYPLSTCU_BYP_L0_MASK) #define AON_CSTCU_BYPLSTCU_BYP_L1_MASK (0x2U) #define AON_CSTCU_BYPLSTCU_BYP_L1_SHIFT (1U) /*! BYP_L1 - Bypass LSTCU 1 * 0b0..No bypass * 0b1..Bypass */ #define AON_CSTCU_BYPLSTCU_BYP_L1(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_BYPLSTCU_BYP_L1_SHIFT)) & AON_CSTCU_BYPLSTCU_BYP_L1_MASK) #define AON_CSTCU_BYPLSTCU_BYP_L2_MASK (0x4U) #define AON_CSTCU_BYPLSTCU_BYP_L2_SHIFT (2U) /*! BYP_L2 - Bypass LSTCU 2 * 0b0..No bypass * 0b1..Bypass */ #define AON_CSTCU_BYPLSTCU_BYP_L2(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_BYPLSTCU_BYP_L2_SHIFT)) & AON_CSTCU_BYPLSTCU_BYP_L2_MASK) #define AON_CSTCU_BYPLSTCU_BYP_L3_MASK (0x8U) #define AON_CSTCU_BYPLSTCU_BYP_L3_SHIFT (3U) /*! BYP_L3 - Bypass LSTCU 3 * 0b0..No bypass * 0b1..Bypass */ #define AON_CSTCU_BYPLSTCU_BYP_L3(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_BYPLSTCU_BYP_L3_SHIFT)) & AON_CSTCU_BYPLSTCU_BYP_L3_MASK) #define AON_CSTCU_BYPLSTCU_BYP_L4_MASK (0x10U) #define AON_CSTCU_BYPLSTCU_BYP_L4_SHIFT (4U) /*! BYP_L4 - Bypass LSTCU 4 * 0b0..No bypass * 0b1..Bypass */ #define AON_CSTCU_BYPLSTCU_BYP_L4(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_BYPLSTCU_BYP_L4_SHIFT)) & AON_CSTCU_BYPLSTCU_BYP_L4_MASK) /*! @} */ /* The count of AON_CSTCU_BYPLSTCU */ #define AON_CSTCU_BYPLSTCU_COUNT (1U) /*! @name STAG - Stagger */ /*! @{ */ #define AON_CSTCU_STAG_MB_DELAY_MASK (0xFF00U) #define AON_CSTCU_STAG_MB_DELAY_SHIFT (8U) /*! MB_DELAY - MBIST Delay */ #define AON_CSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_STAG_MB_DELAY_SHIFT)) & AON_CSTCU_STAG_MB_DELAY_MASK) /*! @} */ /*! @name LMBPTR - LSTCU MBIST Run Phase Scheduler Pointer */ /*! @{ */ #define AON_CSTCU_LMBPTR_MBPTR_MASK (0xFFU) #define AON_CSTCU_LMBPTR_MBPTR_SHIFT (0U) /*! MBPTR - LSTCU Pointer Scheduled During MBIST Run Phase */ #define AON_CSTCU_LMBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LMBPTR_MBPTR_SHIFT)) & AON_CSTCU_LMBPTR_MBPTR_MASK) #define AON_CSTCU_LMBPTR_MBCSM_MASK (0x100U) #define AON_CSTCU_LMBPTR_MBCSM_SHIFT (8U) /*! MBCSM - MBIST Concurrent or Sequential Mode * 0b0..Sequential mode * 0b1..Concurrent mode */ #define AON_CSTCU_LMBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LMBPTR_MBCSM_SHIFT)) & AON_CSTCU_LMBPTR_MBCSM_MASK) #define AON_CSTCU_LMBPTR_MBEOL_MASK (0x80000000U) #define AON_CSTCU_LMBPTR_MBEOL_SHIFT (31U) /*! MBEOL - MBIST End of List * 0b0..Not end of list * 0b1..End of list */ #define AON_CSTCU_LMBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << AON_CSTCU_LMBPTR_MBEOL_SHIFT)) & AON_CSTCU_LMBPTR_MBEOL_MASK) /*! @} */ /* The count of AON_CSTCU_LMBPTR */ #define AON_CSTCU_LMBPTR_COUNT (5U) /*! * @} */ /* end of group AON_CSTCU_Register_Masks */ /* AON_CSTCU - Peripheral instance base addresses */ /** Peripheral AON__CSTCU base address */ #define AON__CSTCU_BASE (0x44590000u) /** Peripheral AON__CSTCU base pointer */ #define AON__CSTCU ((AON_CSTCU_Type *)AON__CSTCU_BASE) /** Array initializer of AON_CSTCU peripheral base addresses */ #define AON_CSTCU_BASE_ADDRS { AON__CSTCU_BASE } /** Array initializer of AON_CSTCU peripheral base pointers */ #define AON_CSTCU_BASE_PTRS { AON__CSTCU } /*! * @} */ /* end of group AON_CSTCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_EIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_EIM_Peripheral_Access_Layer AON_EIM Peripheral Access Layer * @{ */ /** AON_EIM - Register Layout Typedef */ typedef struct { __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ uint8_t RESERVED_0[248]; __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ __IO uint32_t EICHD0_WORD2; /**< Error Injection Channel Descriptor 0, Word2, offset: 0x108 */ uint8_t RESERVED_1[52]; __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ __IO uint32_t EICHD1_WORD2; /**< Error Injection Channel Descriptor 1, Word2, offset: 0x148 */ uint8_t RESERVED_2[52]; __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ __IO uint32_t EICHD2_WORD2; /**< Error Injection Channel Descriptor 2, Word2, offset: 0x188 */ uint8_t RESERVED_3[52]; __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ __IO uint32_t EICHD3_WORD2; /**< Error Injection Channel Descriptor 3, Word2, offset: 0x1C8 */ uint8_t RESERVED_4[52]; __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ uint8_t RESERVED_5[56]; __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ uint8_t RESERVED_6[56]; __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ uint8_t RESERVED_7[56]; __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ uint8_t RESERVED_8[56]; __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ uint8_t RESERVED_9[56]; __IO uint32_t EICHD9_WORD0; /**< Error Injection Channel Descriptor 9, Word0, offset: 0x340 */ __IO uint32_t EICHD9_WORD1; /**< Error Injection Channel Descriptor 9, Word1, offset: 0x344 */ uint8_t RESERVED_10[56]; __IO uint32_t EICHD10_WORD0; /**< Error Injection Channel Descriptor 10, Word0, offset: 0x380 */ __IO uint32_t EICHD10_WORD1; /**< Error Injection Channel Descriptor 10, Word1, offset: 0x384 */ uint8_t RESERVED_11[56]; __IO uint32_t EICHD11_WORD0; /**< Error Injection Channel Descriptor 11, Word0, offset: 0x3C0 */ __IO uint32_t EICHD11_WORD1; /**< Error Injection Channel Descriptor 11, Word1, offset: 0x3C4 */ uint8_t RESERVED_12[56]; __IO uint32_t EICHD12_WORD0; /**< Error Injection Channel Descriptor 12, Word0, offset: 0x400 */ __IO uint32_t EICHD12_WORD1; /**< Error Injection Channel Descriptor 12, Word1, offset: 0x404 */ } AON_EIM_Type; /* ---------------------------------------------------------------------------- -- AON_EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_EIM_Register_Masks AON_EIM Register Masks * @{ */ /*! @name EIMCR - Error Injection Module Configuration Register */ /*! @{ */ #define AON_EIM_EIMCR_GEIEN_MASK (0x1U) #define AON_EIM_EIMCR_GEIEN_SHIFT (0U) /*! GEIEN - Global Error Injection Enable * 0b0..Disabled * 0b1..Enabled */ #define AON_EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EIMCR_GEIEN_SHIFT)) & AON_EIM_EIMCR_GEIEN_MASK) /*! @} */ /*! @name EICHEN - Error Injection Channel Enable register */ /*! @{ */ #define AON_EIM_EICHEN_EICH12EN_MASK (0x80000U) #define AON_EIM_EICHEN_EICH12EN_SHIFT (19U) /*! EICH12EN - Error Injection Channel 12 Enable * 0b0..Error injection is disabled on Error Injection Channel 12 * 0b1..Error injection is enabled on Error Injection Channel 12 */ #define AON_EIM_EICHEN_EICH12EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH12EN_SHIFT)) & AON_EIM_EICHEN_EICH12EN_MASK) #define AON_EIM_EICHEN_EICH11EN_MASK (0x100000U) #define AON_EIM_EICHEN_EICH11EN_SHIFT (20U) /*! EICH11EN - Error Injection Channel 11 Enable * 0b0..Error injection is disabled on Error Injection Channel 11 * 0b1..Error injection is enabled on Error Injection Channel 11 */ #define AON_EIM_EICHEN_EICH11EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH11EN_SHIFT)) & AON_EIM_EICHEN_EICH11EN_MASK) #define AON_EIM_EICHEN_EICH10EN_MASK (0x200000U) #define AON_EIM_EICHEN_EICH10EN_SHIFT (21U) /*! EICH10EN - Error Injection Channel 10 Enable * 0b0..Error injection is disabled on Error Injection Channel 10 * 0b1..Error injection is enabled on Error Injection Channel 10 */ #define AON_EIM_EICHEN_EICH10EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH10EN_SHIFT)) & AON_EIM_EICHEN_EICH10EN_MASK) #define AON_EIM_EICHEN_EICH9EN_MASK (0x400000U) #define AON_EIM_EICHEN_EICH9EN_SHIFT (22U) /*! EICH9EN - Error Injection Channel 9 Enable * 0b0..Error injection is disabled on Error Injection Channel 9 * 0b1..Error injection is enabled on Error Injection Channel 9 */ #define AON_EIM_EICHEN_EICH9EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH9EN_SHIFT)) & AON_EIM_EICHEN_EICH9EN_MASK) #define AON_EIM_EICHEN_EICH8EN_MASK (0x800000U) #define AON_EIM_EICHEN_EICH8EN_SHIFT (23U) /*! EICH8EN - Error Injection Channel 8 Enable * 0b0..Error injection is disabled on Error Injection Channel 8 * 0b1..Error injection is enabled on Error Injection Channel 8 */ #define AON_EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH8EN_SHIFT)) & AON_EIM_EICHEN_EICH8EN_MASK) #define AON_EIM_EICHEN_EICH7EN_MASK (0x1000000U) #define AON_EIM_EICHEN_EICH7EN_SHIFT (24U) /*! EICH7EN - Error Injection Channel 7 Enable * 0b0..Error injection is disabled on Error Injection Channel 7 * 0b1..Error injection is enabled on Error Injection Channel 7 */ #define AON_EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH7EN_SHIFT)) & AON_EIM_EICHEN_EICH7EN_MASK) #define AON_EIM_EICHEN_EICH6EN_MASK (0x2000000U) #define AON_EIM_EICHEN_EICH6EN_SHIFT (25U) /*! EICH6EN - Error Injection Channel 6 Enable * 0b0..Error injection is disabled on Error Injection Channel 6 * 0b1..Error injection is enabled on Error Injection Channel 6 */ #define AON_EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH6EN_SHIFT)) & AON_EIM_EICHEN_EICH6EN_MASK) #define AON_EIM_EICHEN_EICH5EN_MASK (0x4000000U) #define AON_EIM_EICHEN_EICH5EN_SHIFT (26U) /*! EICH5EN - Error Injection Channel 5 Enable * 0b0..Error injection is disabled on Error Injection Channel 5 * 0b1..Error injection is enabled on Error Injection Channel 5 */ #define AON_EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH5EN_SHIFT)) & AON_EIM_EICHEN_EICH5EN_MASK) #define AON_EIM_EICHEN_EICH4EN_MASK (0x8000000U) #define AON_EIM_EICHEN_EICH4EN_SHIFT (27U) /*! EICH4EN - Error Injection Channel 4 Enable * 0b0..Error injection is disabled on Error Injection Channel 4 * 0b1..Error injection is enabled on Error Injection Channel 4 */ #define AON_EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH4EN_SHIFT)) & AON_EIM_EICHEN_EICH4EN_MASK) #define AON_EIM_EICHEN_EICH3EN_MASK (0x10000000U) #define AON_EIM_EICHEN_EICH3EN_SHIFT (28U) /*! EICH3EN - Error Injection Channel 3 Enable * 0b0..Error injection is disabled on Error Injection Channel 3 * 0b1..Error injection is enabled on Error Injection Channel 3 */ #define AON_EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH3EN_SHIFT)) & AON_EIM_EICHEN_EICH3EN_MASK) #define AON_EIM_EICHEN_EICH2EN_MASK (0x20000000U) #define AON_EIM_EICHEN_EICH2EN_SHIFT (29U) /*! EICH2EN - Error Injection Channel 2 Enable * 0b0..Error injection is disabled on Error Injection Channel 2 * 0b1..Error injection is enabled on Error Injection Channel 2 */ #define AON_EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH2EN_SHIFT)) & AON_EIM_EICHEN_EICH2EN_MASK) #define AON_EIM_EICHEN_EICH1EN_MASK (0x40000000U) #define AON_EIM_EICHEN_EICH1EN_SHIFT (30U) /*! EICH1EN - Error Injection Channel 1 Enable * 0b0..Error injection is disabled on Error Injection Channel 1 * 0b1..Error injection is enabled on Error Injection Channel 1 */ #define AON_EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH1EN_SHIFT)) & AON_EIM_EICHEN_EICH1EN_MASK) #define AON_EIM_EICHEN_EICH0EN_MASK (0x80000000U) #define AON_EIM_EICHEN_EICH0EN_SHIFT (31U) /*! EICH0EN - Error Injection Channel 0 Enable * 0b0..Error injection is disabled on Error Injection Channel 0 * 0b1..Error injection is enabled on Error Injection Channel 0 */ #define AON_EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHEN_EICH0EN_SHIFT)) & AON_EIM_EICHEN_EICH0EN_MASK) /*! @} */ /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ /*! @{ */ #define AON_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define AON_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ /*! @{ */ #define AON_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFU) #define AON_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD2 - Error Injection Channel Descriptor 0, Word2 */ /*! @{ */ #define AON_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define AON_EIM_EICHD0_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT)) & AON_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ /*! @{ */ #define AON_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define AON_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ /*! @{ */ #define AON_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFU) #define AON_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD2 - Error Injection Channel Descriptor 1, Word2 */ /*! @{ */ #define AON_EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define AON_EIM_EICHD1_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT)) & AON_EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ /*! @{ */ #define AON_EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define AON_EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ /*! @{ */ #define AON_EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFU) #define AON_EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD2 - Error Injection Channel Descriptor 2, Word2 */ /*! @{ */ #define AON_EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define AON_EIM_EICHD2_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT)) & AON_EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ /*! @{ */ #define AON_EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define AON_EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ /*! @{ */ #define AON_EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFU) #define AON_EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD2 - Error Injection Channel Descriptor 3, Word2 */ /*! @{ */ #define AON_EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define AON_EIM_EICHD3_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT)) & AON_EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ /*! @{ */ #define AON_EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define AON_EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ /*! @{ */ #define AON_EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ /*! @{ */ #define AON_EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define AON_EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ /*! @{ */ #define AON_EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ /*! @{ */ #define AON_EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define AON_EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ /*! @{ */ #define AON_EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ /*! @{ */ #define AON_EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define AON_EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ /*! @{ */ #define AON_EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ /*! @{ */ #define AON_EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define AON_EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ /*! @{ */ #define AON_EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD9_WORD0 - Error Injection Channel Descriptor 9, Word0 */ /*! @{ */ #define AON_EIM_EICHD9_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define AON_EIM_EICHD9_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD9_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD9_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD9_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD9_WORD1 - Error Injection Channel Descriptor 9, Word1 */ /*! @{ */ #define AON_EIM_EICHD9_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define AON_EIM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD9_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD9_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD10_WORD0 - Error Injection Channel Descriptor 10, Word0 */ /*! @{ */ #define AON_EIM_EICHD10_WORD0_CHKBIT_MASK_MASK (0xC0000000U) #define AON_EIM_EICHD10_WORD0_CHKBIT_MASK_SHIFT (30U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD10_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD10_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD10_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD10_WORD1 - Error Injection Channel Descriptor 10, Word1 */ /*! @{ */ #define AON_EIM_EICHD10_WORD1_B0_3DATA_MASK_MASK (0x1U) #define AON_EIM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD10_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD10_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD11_WORD0 - Error Injection Channel Descriptor 11, Word0 */ /*! @{ */ #define AON_EIM_EICHD11_WORD0_CHKBIT_MASK_MASK (0xF8000000U) #define AON_EIM_EICHD11_WORD0_CHKBIT_MASK_SHIFT (27U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD11_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD11_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD11_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD11_WORD1 - Error Injection Channel Descriptor 11, Word1 */ /*! @{ */ #define AON_EIM_EICHD11_WORD1_B0_3DATA_MASK_MASK (0x1U) #define AON_EIM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD11_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD11_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD12_WORD0 - Error Injection Channel Descriptor 12, Word0 */ /*! @{ */ #define AON_EIM_EICHD12_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define AON_EIM_EICHD12_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define AON_EIM_EICHD12_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD12_WORD0_CHKBIT_MASK_SHIFT)) & AON_EIM_EICHD12_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD12_WORD1 - Error Injection Channel Descriptor 12, Word1 */ /*! @{ */ #define AON_EIM_EICHD12_WORD1_B0_3DATA_MASK_MASK (0x1U) #define AON_EIM_EICHD12_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define AON_EIM_EICHD12_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << AON_EIM_EICHD12_WORD1_B0_3DATA_MASK_SHIFT)) & AON_EIM_EICHD12_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! * @} */ /* end of group AON_EIM_Register_Masks */ /* AON_EIM - Peripheral instance base addresses */ /** Peripheral AON__EIMA base address */ #define AON__EIMA_BASE (0x44550000u) /** Peripheral AON__EIMA base pointer */ #define AON__EIMA ((AON_EIM_Type *)AON__EIMA_BASE) /** Array initializer of AON_EIM peripheral base addresses */ #define AON_EIM_BASE_ADDRS { AON__EIMA_BASE } /** Array initializer of AON_EIM peripheral base pointers */ #define AON_EIM_BASE_PTRS { AON__EIMA } /*! * @} */ /* end of group AON_EIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_FCCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_FCCU_Peripheral_Access_Layer AON_FCCU Peripheral Access Layer * @{ */ /** AON_FCCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[768]; __IO uint32_t GRKNTIMC[1]; /**< Global Reaction Timer Period, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_1[316]; __IO uint32_t GFLTRC_C0; /**< Global Fault Recovery, offset: 0x440 */ __IO uint32_t GFLTRC_C1; /**< Global Fault Recovery, offset: 0x444 */ __IO uint32_t GFLTRC_C2; /**< Global Fault Recovery, offset: 0x448 */ uint8_t RESERVED_2[2100]; __IO uint32_t GFLTOVDC0; /**< Global Fault Overflow Detection, offset: 0xC80 */ __IO uint32_t GFLTOVDC1; /**< Global Fault Overflow Detection, offset: 0xC84 */ __IO uint32_t GFLTOVDC2; /**< Global Fault Overflow Detection, offset: 0xC88 */ uint8_t RESERVED_3[116]; __I uint32_t GRKNTIMS; /**< Global Reaction Timer Status, offset: 0xD00 */ __IO uint32_t GCTRL; /**< Global Space Control, offset: 0xD04 */ __IO uint32_t GINTOVFS; /**< Global DID FSM Status, offset: 0xD08 */ uint8_t RESERVED_4[4]; __IO uint32_t GOVFRKC[1]; /**< Global Overflow Reaction, array offset: 0xD10, array step: 0x4 */ uint8_t RESERVED_5[12]; __IO uint32_t GMEOUTDC; /**< Global Minimum EOUT Duration, offset: 0xD20 */ __IO uint32_t GEOUTTCT; /**< Global EOUT Timer Disable, offset: 0xD24 */ uint8_t RESERVED_6[8]; struct { /* offset: 0xD30, array step: 0x14 */ __IO uint32_t GEOUTPNC; /**< Global EOUT Pin, array offset: 0xD30, array step: 0x14 */ __IO uint32_t GEOUTPMC; /**< Global EOUT Pin Map, array offset: 0xD34, array step: 0x14 */ __IO uint32_t GEOUTMC; /**< Global EOUT Mode, array offset: 0xD38, array step: 0x14 */ __I uint32_t GEOUTTMS; /**< Global EOUT Timer Status, array offset: 0xD3C, array step: 0x14 */ __IO uint32_t GEOUTDIC; /**< Global EOUT DID, array offset: 0xD40, array step: 0x14 */ } GLB_EOUT[2]; uint8_t RESERVED_7[600]; __IO uint32_t GDBGCFG; /**< Global Debug, offset: 0xFB0 */ __I uint32_t GDBGSTAT; /**< Global Debug Status, offset: 0xFB4 */ __I uint32_t GDPFSTAT; /**< Global Debug Pending Fault Status, offset: 0xFB8 */ __I uint32_t GDALTRLD; /**< Global Debug Alternate Reload Status, offset: 0xFBC */ uint8_t RESERVED_8[1306688]; __IO uint32_t FHCFG0; /**< Fault Handler, offset: 0x140000 */ __I uint32_t FHSRVDS0; /**< Fault Handler Status, offset: 0x140004 */ uint8_t RESERVED_9[8]; __IO uint32_t FHFLTENC0_0; /**< Fault Enable, offset: 0x140010 */ __IO uint32_t FHFLTENC0_1; /**< Fault Enable, offset: 0x140014 */ __IO uint32_t FHFLTENC0_2; /**< Fault Enable, offset: 0x140018 */ uint8_t RESERVED_10[52]; __IO uint32_t FHFLTS0_0; /**< Fault Status, offset: 0x140050 */ __IO uint32_t FHFLTS0_1; /**< Fault Status, offset: 0x140054 */ __IO uint32_t FHFLTS0_2; /**< Fault Status, offset: 0x140058 */ uint8_t RESERVED_11[52]; __IO uint32_t FHFLTRKC0_0; /**< Fault Reaction Set Configuration, offset: 0x140090 */ __IO uint32_t FHFLTRKC0_1; /**< Fault Reaction Set Configuration, offset: 0x140094 */ __IO uint32_t FHFLTRKC0_2; /**< Fault Reaction Set Configuration, offset: 0x140098 */ __IO uint32_t FHFLTRKC0_3; /**< Fault Reaction Set Configuration, offset: 0x14009C */ __IO uint32_t FHFLTRKC0_4; /**< Fault Reaction Set Configuration, offset: 0x1400A0 */ __IO uint32_t FHFLTRKC0_5; /**< Fault Reaction Set Configuration, offset: 0x1400A4 */ __IO uint32_t FHFLTRKC0_6; /**< Fault Reaction Set Configuration, offset: 0x1400A8 */ __IO uint32_t FHFLTRKC0_7; /**< Fault Reaction Set Configuration, offset: 0x1400AC */ __IO uint32_t FHFLTRKC0_8; /**< Fault Reaction Set Configuration, offset: 0x1400B0 */ __IO uint32_t FHFLTRKC0_9; /**< Fault Reaction Set Configuration, offset: 0x1400B4 */ __IO uint32_t FHFLTRKC0_10; /**< Fault Reaction Set Configuration, offset: 0x1400B8 */ __IO uint32_t FHFLTRKC0_11; /**< Fault Reaction Set Configuration, offset: 0x1400BC */ __IO uint32_t FHFLTRKC0_12; /**< Fault Reaction Set Configuration, offset: 0x1400C0 */ __IO uint32_t FHFLTRKC0_13; /**< Fault Reaction Set Configuration, offset: 0x1400C4 */ __IO uint32_t FHFLTRKC0_14; /**< Fault Reaction Set Configuration, offset: 0x1400C8 */ __IO uint32_t FHFLTRKC0_15; /**< Fault Reaction Set Configuration, offset: 0x1400CC */ __IO uint32_t FHFLTRKC0_16; /**< Fault Reaction Set Configuration, offset: 0x1400D0 */ __IO uint32_t FHFLTRKC0_17; /**< Fault Reaction Set Configuration, offset: 0x1400D4 */ __IO uint32_t FHFLTRKC0_18; /**< Fault Reaction Set Configuration, offset: 0x1400D8 */ __IO uint32_t FHFLTRKC0_19; /**< Fault Reaction Set Configuration, offset: 0x1400DC */ uint8_t RESERVED_12[432]; __IO uint32_t FHIMRKC0_00; /**< Immediate Reaction Configuration, offset: 0x140290 */ uint8_t RESERVED_13[12]; __IO uint32_t FHDLRKC0_00; /**< Delayed Reaction Configuration, offset: 0x1402A0 */ uint8_t RESERVED_14[12]; __IO uint32_t FHIMRKC0_10; /**< Immediate Reaction Configuration, offset: 0x1402B0 */ uint8_t RESERVED_15[12]; __IO uint32_t FHDLRKC0_10; /**< Delayed Reaction Configuration, offset: 0x1402C0 */ uint8_t RESERVED_16[12]; __IO uint32_t FHIMRKC0_20; /**< Immediate Reaction Configuration, offset: 0x1402D0 */ uint8_t RESERVED_17[12]; __IO uint32_t FHDLRKC0_20; /**< Delayed Reaction Configuration, offset: 0x1402E0 */ uint8_t RESERVED_18[12]; __IO uint32_t FHIMRKC0_30; /**< Immediate Reaction Configuration, offset: 0x1402F0 */ uint8_t RESERVED_19[12]; __IO uint32_t FHDLRKC0_30; /**< Delayed Reaction Configuration, offset: 0x140300 */ uint8_t RESERVED_20[12]; __IO uint32_t FHIMRKC0_40; /**< Immediate Reaction Configuration, offset: 0x140310 */ uint8_t RESERVED_21[12]; __IO uint32_t FHDLRKC0_40; /**< Delayed Reaction Configuration, offset: 0x140320 */ uint8_t RESERVED_22[12]; __IO uint32_t FHIMRKC0_50; /**< Immediate Reaction Configuration, offset: 0x140330 */ uint8_t RESERVED_23[12]; __IO uint32_t FHDLRKC0_50; /**< Delayed Reaction Configuration, offset: 0x140340 */ uint8_t RESERVED_24[12]; __IO uint32_t FHIMRKC0_60; /**< Immediate Reaction Configuration, offset: 0x140350 */ uint8_t RESERVED_25[12]; __IO uint32_t FHDLRKC0_60; /**< Delayed Reaction Configuration, offset: 0x140360 */ uint8_t RESERVED_26[12]; __IO uint32_t FHIMRKC0_70; /**< Immediate Reaction Configuration, offset: 0x140370 */ uint8_t RESERVED_27[12]; __IO uint32_t FHDLRKC0_70; /**< Delayed Reaction Configuration, offset: 0x140380 */ } AON_FCCU_Type; /* ---------------------------------------------------------------------------- -- AON_FCCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_FCCU_Register_Masks AON_FCCU Register Masks * @{ */ /*! @name GRKNTIMC - Global Reaction Timer Period */ /*! @{ */ #define AON_FCCU_GRKNTIMC_RKTIMCFG_MASK (0xFFFFFFFFU) #define AON_FCCU_GRKNTIMC_RKTIMCFG_SHIFT (0U) /*! RKTIMCFG - Reaction Timer Period */ #define AON_FCCU_GRKNTIMC_RKTIMCFG(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GRKNTIMC_RKTIMCFG_SHIFT)) & AON_FCCU_GRKNTIMC_RKTIMCFG_MASK) /*! @} */ /* The count of AON_FCCU_GRKNTIMC */ #define AON_FCCU_GRKNTIMC_COUNT (1U) /*! @name GFLTRC_C0 - Global Fault Recovery */ /*! @{ */ #define AON_FCCU_GFLTRC_C0_RHWSW0_MASK (0x1U) #define AON_FCCU_GFLTRC_C0_RHWSW0_SHIFT (0U) /*! RHWSW0 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW0_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW0_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW1_MASK (0x2U) #define AON_FCCU_GFLTRC_C0_RHWSW1_SHIFT (1U) /*! RHWSW1 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW1_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW1_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW2_MASK (0x4U) #define AON_FCCU_GFLTRC_C0_RHWSW2_SHIFT (2U) /*! RHWSW2 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW2_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW2_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW3_MASK (0x8U) #define AON_FCCU_GFLTRC_C0_RHWSW3_SHIFT (3U) /*! RHWSW3 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW3_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW3_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW4_MASK (0x10U) #define AON_FCCU_GFLTRC_C0_RHWSW4_SHIFT (4U) /*! RHWSW4 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW4_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW4_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW5_MASK (0x20U) #define AON_FCCU_GFLTRC_C0_RHWSW5_SHIFT (5U) /*! RHWSW5 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW5_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW5_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW6_MASK (0x40U) #define AON_FCCU_GFLTRC_C0_RHWSW6_SHIFT (6U) /*! RHWSW6 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW6_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW6_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW7_MASK (0x80U) #define AON_FCCU_GFLTRC_C0_RHWSW7_SHIFT (7U) /*! RHWSW7 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW7(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW7_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW7_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW8_MASK (0x100U) #define AON_FCCU_GFLTRC_C0_RHWSW8_SHIFT (8U) /*! RHWSW8 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW8(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW8_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW8_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW9_MASK (0x200U) #define AON_FCCU_GFLTRC_C0_RHWSW9_SHIFT (9U) /*! RHWSW9 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW9(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW9_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW9_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW10_MASK (0x400U) #define AON_FCCU_GFLTRC_C0_RHWSW10_SHIFT (10U) /*! RHWSW10 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW10(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW10_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW10_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW11_MASK (0x800U) #define AON_FCCU_GFLTRC_C0_RHWSW11_SHIFT (11U) /*! RHWSW11 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW11(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW11_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW11_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW12_MASK (0x1000U) #define AON_FCCU_GFLTRC_C0_RHWSW12_SHIFT (12U) /*! RHWSW12 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW12(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW12_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW12_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW13_MASK (0x2000U) #define AON_FCCU_GFLTRC_C0_RHWSW13_SHIFT (13U) /*! RHWSW13 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW13(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW13_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW13_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW14_MASK (0x4000U) #define AON_FCCU_GFLTRC_C0_RHWSW14_SHIFT (14U) /*! RHWSW14 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW14(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW14_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW14_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW15_MASK (0x8000U) #define AON_FCCU_GFLTRC_C0_RHWSW15_SHIFT (15U) /*! RHWSW15 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW15(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW15_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW15_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW16_MASK (0x10000U) #define AON_FCCU_GFLTRC_C0_RHWSW16_SHIFT (16U) /*! RHWSW16 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW16(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW16_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW16_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW17_MASK (0x20000U) #define AON_FCCU_GFLTRC_C0_RHWSW17_SHIFT (17U) /*! RHWSW17 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW17(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW17_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW17_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW18_MASK (0x40000U) #define AON_FCCU_GFLTRC_C0_RHWSW18_SHIFT (18U) /*! RHWSW18 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW18(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW18_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW18_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW19_MASK (0x80000U) #define AON_FCCU_GFLTRC_C0_RHWSW19_SHIFT (19U) /*! RHWSW19 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW19(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW19_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW19_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW20_MASK (0x100000U) #define AON_FCCU_GFLTRC_C0_RHWSW20_SHIFT (20U) /*! RHWSW20 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW20(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW20_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW20_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW21_MASK (0x200000U) #define AON_FCCU_GFLTRC_C0_RHWSW21_SHIFT (21U) /*! RHWSW21 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW21(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW21_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW21_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW22_MASK (0x400000U) #define AON_FCCU_GFLTRC_C0_RHWSW22_SHIFT (22U) /*! RHWSW22 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW22(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW22_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW22_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW23_MASK (0x800000U) #define AON_FCCU_GFLTRC_C0_RHWSW23_SHIFT (23U) /*! RHWSW23 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW23(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW23_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW23_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW24_MASK (0x1000000U) #define AON_FCCU_GFLTRC_C0_RHWSW24_SHIFT (24U) /*! RHWSW24 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW24(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW24_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW24_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW25_MASK (0x2000000U) #define AON_FCCU_GFLTRC_C0_RHWSW25_SHIFT (25U) /*! RHWSW25 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW25(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW25_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW25_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW26_MASK (0x4000000U) #define AON_FCCU_GFLTRC_C0_RHWSW26_SHIFT (26U) /*! RHWSW26 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW26(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW26_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW26_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW27_MASK (0x8000000U) #define AON_FCCU_GFLTRC_C0_RHWSW27_SHIFT (27U) /*! RHWSW27 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW27(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW27_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW27_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW28_MASK (0x10000000U) #define AON_FCCU_GFLTRC_C0_RHWSW28_SHIFT (28U) /*! RHWSW28 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW28(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW28_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW28_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW29_MASK (0x20000000U) #define AON_FCCU_GFLTRC_C0_RHWSW29_SHIFT (29U) /*! RHWSW29 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW29(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW29_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW29_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW30_MASK (0x40000000U) #define AON_FCCU_GFLTRC_C0_RHWSW30_SHIFT (30U) /*! RHWSW30 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW30(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW30_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW30_MASK) #define AON_FCCU_GFLTRC_C0_RHWSW31_MASK (0x80000000U) #define AON_FCCU_GFLTRC_C0_RHWSW31_SHIFT (31U) /*! RHWSW31 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C0_RHWSW31(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C0_RHWSW31_SHIFT)) & AON_FCCU_GFLTRC_C0_RHWSW31_MASK) /*! @} */ /*! @name GFLTRC_C1 - Global Fault Recovery */ /*! @{ */ #define AON_FCCU_GFLTRC_C1_RHWSW32_MASK (0x1U) #define AON_FCCU_GFLTRC_C1_RHWSW32_SHIFT (0U) /*! RHWSW32 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW32(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW32_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW32_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW33_MASK (0x2U) #define AON_FCCU_GFLTRC_C1_RHWSW33_SHIFT (1U) /*! RHWSW33 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW33(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW33_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW33_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW34_MASK (0x4U) #define AON_FCCU_GFLTRC_C1_RHWSW34_SHIFT (2U) /*! RHWSW34 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW34(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW34_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW34_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW35_MASK (0x8U) #define AON_FCCU_GFLTRC_C1_RHWSW35_SHIFT (3U) /*! RHWSW35 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW35(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW35_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW35_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW36_MASK (0x10U) #define AON_FCCU_GFLTRC_C1_RHWSW36_SHIFT (4U) /*! RHWSW36 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW36(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW36_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW36_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW37_MASK (0x20U) #define AON_FCCU_GFLTRC_C1_RHWSW37_SHIFT (5U) /*! RHWSW37 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW37(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW37_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW37_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW38_MASK (0x40U) #define AON_FCCU_GFLTRC_C1_RHWSW38_SHIFT (6U) /*! RHWSW38 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW38(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW38_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW38_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW39_MASK (0x80U) #define AON_FCCU_GFLTRC_C1_RHWSW39_SHIFT (7U) /*! RHWSW39 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW39(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW39_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW39_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW40_MASK (0x100U) #define AON_FCCU_GFLTRC_C1_RHWSW40_SHIFT (8U) /*! RHWSW40 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW40(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW40_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW40_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW41_MASK (0x200U) #define AON_FCCU_GFLTRC_C1_RHWSW41_SHIFT (9U) /*! RHWSW41 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW41(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW41_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW41_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW42_MASK (0x400U) #define AON_FCCU_GFLTRC_C1_RHWSW42_SHIFT (10U) /*! RHWSW42 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW42(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW42_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW42_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW43_MASK (0x800U) #define AON_FCCU_GFLTRC_C1_RHWSW43_SHIFT (11U) /*! RHWSW43 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW43(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW43_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW43_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW44_MASK (0x1000U) #define AON_FCCU_GFLTRC_C1_RHWSW44_SHIFT (12U) /*! RHWSW44 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW44(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW44_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW44_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW45_MASK (0x2000U) #define AON_FCCU_GFLTRC_C1_RHWSW45_SHIFT (13U) /*! RHWSW45 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW45(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW45_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW45_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW46_MASK (0x4000U) #define AON_FCCU_GFLTRC_C1_RHWSW46_SHIFT (14U) /*! RHWSW46 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW46(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW46_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW46_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW47_MASK (0x8000U) #define AON_FCCU_GFLTRC_C1_RHWSW47_SHIFT (15U) /*! RHWSW47 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW47(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW47_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW47_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW48_MASK (0x10000U) #define AON_FCCU_GFLTRC_C1_RHWSW48_SHIFT (16U) /*! RHWSW48 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW48(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW48_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW48_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW49_MASK (0x20000U) #define AON_FCCU_GFLTRC_C1_RHWSW49_SHIFT (17U) /*! RHWSW49 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW49(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW49_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW49_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW50_MASK (0x40000U) #define AON_FCCU_GFLTRC_C1_RHWSW50_SHIFT (18U) /*! RHWSW50 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW50(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW50_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW50_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW51_MASK (0x80000U) #define AON_FCCU_GFLTRC_C1_RHWSW51_SHIFT (19U) /*! RHWSW51 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW51(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW51_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW51_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW52_MASK (0x100000U) #define AON_FCCU_GFLTRC_C1_RHWSW52_SHIFT (20U) /*! RHWSW52 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW52(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW52_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW52_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW53_MASK (0x200000U) #define AON_FCCU_GFLTRC_C1_RHWSW53_SHIFT (21U) /*! RHWSW53 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW53(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW53_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW53_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW54_MASK (0x400000U) #define AON_FCCU_GFLTRC_C1_RHWSW54_SHIFT (22U) /*! RHWSW54 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW54(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW54_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW54_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW55_MASK (0x800000U) #define AON_FCCU_GFLTRC_C1_RHWSW55_SHIFT (23U) /*! RHWSW55 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW55(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW55_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW55_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW56_MASK (0x1000000U) #define AON_FCCU_GFLTRC_C1_RHWSW56_SHIFT (24U) /*! RHWSW56 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW56(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW56_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW56_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW57_MASK (0x2000000U) #define AON_FCCU_GFLTRC_C1_RHWSW57_SHIFT (25U) /*! RHWSW57 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW57(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW57_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW57_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW58_MASK (0x4000000U) #define AON_FCCU_GFLTRC_C1_RHWSW58_SHIFT (26U) /*! RHWSW58 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW58(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW58_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW58_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW59_MASK (0x8000000U) #define AON_FCCU_GFLTRC_C1_RHWSW59_SHIFT (27U) /*! RHWSW59 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW59(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW59_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW59_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW60_MASK (0x10000000U) #define AON_FCCU_GFLTRC_C1_RHWSW60_SHIFT (28U) /*! RHWSW60 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW60(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW60_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW60_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW61_MASK (0x20000000U) #define AON_FCCU_GFLTRC_C1_RHWSW61_SHIFT (29U) /*! RHWSW61 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW61(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW61_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW61_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW62_MASK (0x40000000U) #define AON_FCCU_GFLTRC_C1_RHWSW62_SHIFT (30U) /*! RHWSW62 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW62(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW62_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW62_MASK) #define AON_FCCU_GFLTRC_C1_RHWSW63_MASK (0x80000000U) #define AON_FCCU_GFLTRC_C1_RHWSW63_SHIFT (31U) /*! RHWSW63 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C1_RHWSW63(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C1_RHWSW63_SHIFT)) & AON_FCCU_GFLTRC_C1_RHWSW63_MASK) /*! @} */ /*! @name GFLTRC_C2 - Global Fault Recovery */ /*! @{ */ #define AON_FCCU_GFLTRC_C2_RHWSW64_MASK (0x1U) #define AON_FCCU_GFLTRC_C2_RHWSW64_SHIFT (0U) /*! RHWSW64 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW64(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW64_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW64_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW65_MASK (0x2U) #define AON_FCCU_GFLTRC_C2_RHWSW65_SHIFT (1U) /*! RHWSW65 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW65(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW65_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW65_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW66_MASK (0x4U) #define AON_FCCU_GFLTRC_C2_RHWSW66_SHIFT (2U) /*! RHWSW66 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW66(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW66_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW66_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW67_MASK (0x8U) #define AON_FCCU_GFLTRC_C2_RHWSW67_SHIFT (3U) /*! RHWSW67 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW67(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW67_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW67_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW68_MASK (0x10U) #define AON_FCCU_GFLTRC_C2_RHWSW68_SHIFT (4U) /*! RHWSW68 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW68(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW68_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW68_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW69_MASK (0x20U) #define AON_FCCU_GFLTRC_C2_RHWSW69_SHIFT (5U) /*! RHWSW69 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW69(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW69_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW69_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW70_MASK (0x40U) #define AON_FCCU_GFLTRC_C2_RHWSW70_SHIFT (6U) /*! RHWSW70 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW70(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW70_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW70_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW71_MASK (0x80U) #define AON_FCCU_GFLTRC_C2_RHWSW71_SHIFT (7U) /*! RHWSW71 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW71(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW71_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW71_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW72_MASK (0x100U) #define AON_FCCU_GFLTRC_C2_RHWSW72_SHIFT (8U) /*! RHWSW72 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW72(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW72_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW72_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW73_MASK (0x200U) #define AON_FCCU_GFLTRC_C2_RHWSW73_SHIFT (9U) /*! RHWSW73 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW73(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW73_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW73_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW74_MASK (0x400U) #define AON_FCCU_GFLTRC_C2_RHWSW74_SHIFT (10U) /*! RHWSW74 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW74(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW74_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW74_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW75_MASK (0x800U) #define AON_FCCU_GFLTRC_C2_RHWSW75_SHIFT (11U) /*! RHWSW75 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW75(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW75_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW75_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW76_MASK (0x1000U) #define AON_FCCU_GFLTRC_C2_RHWSW76_SHIFT (12U) /*! RHWSW76 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW76(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW76_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW76_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW77_MASK (0x2000U) #define AON_FCCU_GFLTRC_C2_RHWSW77_SHIFT (13U) /*! RHWSW77 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW77(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW77_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW77_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW78_MASK (0x4000U) #define AON_FCCU_GFLTRC_C2_RHWSW78_SHIFT (14U) /*! RHWSW78 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW78(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW78_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW78_MASK) #define AON_FCCU_GFLTRC_C2_RHWSW79_MASK (0x8000U) #define AON_FCCU_GFLTRC_C2_RHWSW79_SHIFT (15U) /*! RHWSW79 - Recovery/Clearing Mechanism Hardware Or Software * 0b0..Hardware clearable * 0b1..Software clearable */ #define AON_FCCU_GFLTRC_C2_RHWSW79(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTRC_C2_RHWSW79_SHIFT)) & AON_FCCU_GFLTRC_C2_RHWSW79_MASK) /*! @} */ /*! @name GFLTOVDC0 - Global Fault Overflow Detection */ /*! @{ */ #define AON_FCCU_GFLTOVDC0_OVF_DIS0_MASK (0x1U) #define AON_FCCU_GFLTOVDC0_OVF_DIS0_SHIFT (0U) /*! OVF_DIS0 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS0_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS0_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS1_MASK (0x2U) #define AON_FCCU_GFLTOVDC0_OVF_DIS1_SHIFT (1U) /*! OVF_DIS1 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS1_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS1_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS2_MASK (0x4U) #define AON_FCCU_GFLTOVDC0_OVF_DIS2_SHIFT (2U) /*! OVF_DIS2 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS2_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS2_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS3_MASK (0x8U) #define AON_FCCU_GFLTOVDC0_OVF_DIS3_SHIFT (3U) /*! OVF_DIS3 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS3_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS3_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS4_MASK (0x10U) #define AON_FCCU_GFLTOVDC0_OVF_DIS4_SHIFT (4U) /*! OVF_DIS4 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS4_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS4_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS5_MASK (0x20U) #define AON_FCCU_GFLTOVDC0_OVF_DIS5_SHIFT (5U) /*! OVF_DIS5 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS5_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS5_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS6_MASK (0x40U) #define AON_FCCU_GFLTOVDC0_OVF_DIS6_SHIFT (6U) /*! OVF_DIS6 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS6_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS6_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS7_MASK (0x80U) #define AON_FCCU_GFLTOVDC0_OVF_DIS7_SHIFT (7U) /*! OVF_DIS7 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS7(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS7_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS7_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS8_MASK (0x100U) #define AON_FCCU_GFLTOVDC0_OVF_DIS8_SHIFT (8U) /*! OVF_DIS8 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS8(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS8_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS8_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS9_MASK (0x200U) #define AON_FCCU_GFLTOVDC0_OVF_DIS9_SHIFT (9U) /*! OVF_DIS9 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS9(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS9_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS9_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS10_MASK (0x400U) #define AON_FCCU_GFLTOVDC0_OVF_DIS10_SHIFT (10U) /*! OVF_DIS10 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS10(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS10_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS10_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS11_MASK (0x800U) #define AON_FCCU_GFLTOVDC0_OVF_DIS11_SHIFT (11U) /*! OVF_DIS11 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS11(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS11_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS11_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS12_MASK (0x1000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS12_SHIFT (12U) /*! OVF_DIS12 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS12(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS12_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS12_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS13_MASK (0x2000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS13_SHIFT (13U) /*! OVF_DIS13 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS13(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS13_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS13_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS14_MASK (0x4000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS14_SHIFT (14U) /*! OVF_DIS14 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS14(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS14_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS14_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS15_MASK (0x8000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS15_SHIFT (15U) /*! OVF_DIS15 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS15(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS15_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS15_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS16_MASK (0x10000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS16_SHIFT (16U) /*! OVF_DIS16 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS16(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS16_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS16_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS17_MASK (0x20000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS17_SHIFT (17U) /*! OVF_DIS17 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS17(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS17_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS17_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS18_MASK (0x40000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS18_SHIFT (18U) /*! OVF_DIS18 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS18(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS18_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS18_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS19_MASK (0x80000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS19_SHIFT (19U) /*! OVF_DIS19 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS19(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS19_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS19_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS20_MASK (0x100000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS20_SHIFT (20U) /*! OVF_DIS20 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS20(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS20_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS20_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS21_MASK (0x200000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS21_SHIFT (21U) /*! OVF_DIS21 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS21(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS21_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS21_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS22_MASK (0x400000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS22_SHIFT (22U) /*! OVF_DIS22 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS22(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS22_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS22_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS23_MASK (0x800000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS23_SHIFT (23U) /*! OVF_DIS23 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS23(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS23_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS23_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS24_MASK (0x1000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS24_SHIFT (24U) /*! OVF_DIS24 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS24(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS24_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS24_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS25_MASK (0x2000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS25_SHIFT (25U) /*! OVF_DIS25 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS25(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS25_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS25_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS26_MASK (0x4000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS26_SHIFT (26U) /*! OVF_DIS26 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS26(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS26_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS26_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS27_MASK (0x8000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS27_SHIFT (27U) /*! OVF_DIS27 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS27(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS27_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS27_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS28_MASK (0x10000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS28_SHIFT (28U) /*! OVF_DIS28 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS28(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS28_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS28_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS29_MASK (0x20000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS29_SHIFT (29U) /*! OVF_DIS29 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS29(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS29_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS29_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS30_MASK (0x40000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS30_SHIFT (30U) /*! OVF_DIS30 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS30(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS30_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS30_MASK) #define AON_FCCU_GFLTOVDC0_OVF_DIS31_MASK (0x80000000U) #define AON_FCCU_GFLTOVDC0_OVF_DIS31_SHIFT (31U) /*! OVF_DIS31 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC0_OVF_DIS31(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC0_OVF_DIS31_SHIFT)) & AON_FCCU_GFLTOVDC0_OVF_DIS31_MASK) /*! @} */ /*! @name GFLTOVDC1 - Global Fault Overflow Detection */ /*! @{ */ #define AON_FCCU_GFLTOVDC1_OVF_DIS32_MASK (0x1U) #define AON_FCCU_GFLTOVDC1_OVF_DIS32_SHIFT (0U) /*! OVF_DIS32 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS32(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS32_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS32_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS33_MASK (0x2U) #define AON_FCCU_GFLTOVDC1_OVF_DIS33_SHIFT (1U) /*! OVF_DIS33 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS33(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS33_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS33_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS34_MASK (0x4U) #define AON_FCCU_GFLTOVDC1_OVF_DIS34_SHIFT (2U) /*! OVF_DIS34 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS34(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS34_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS34_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS35_MASK (0x8U) #define AON_FCCU_GFLTOVDC1_OVF_DIS35_SHIFT (3U) /*! OVF_DIS35 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS35(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS35_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS35_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS36_MASK (0x10U) #define AON_FCCU_GFLTOVDC1_OVF_DIS36_SHIFT (4U) /*! OVF_DIS36 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS36(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS36_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS36_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS37_MASK (0x20U) #define AON_FCCU_GFLTOVDC1_OVF_DIS37_SHIFT (5U) /*! OVF_DIS37 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS37(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS37_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS37_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS38_MASK (0x40U) #define AON_FCCU_GFLTOVDC1_OVF_DIS38_SHIFT (6U) /*! OVF_DIS38 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS38(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS38_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS38_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS39_MASK (0x80U) #define AON_FCCU_GFLTOVDC1_OVF_DIS39_SHIFT (7U) /*! OVF_DIS39 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS39(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS39_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS39_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS40_MASK (0x100U) #define AON_FCCU_GFLTOVDC1_OVF_DIS40_SHIFT (8U) /*! OVF_DIS40 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS40(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS40_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS40_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS41_MASK (0x200U) #define AON_FCCU_GFLTOVDC1_OVF_DIS41_SHIFT (9U) /*! OVF_DIS41 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS41(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS41_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS41_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS42_MASK (0x400U) #define AON_FCCU_GFLTOVDC1_OVF_DIS42_SHIFT (10U) /*! OVF_DIS42 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS42(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS42_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS42_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS43_MASK (0x800U) #define AON_FCCU_GFLTOVDC1_OVF_DIS43_SHIFT (11U) /*! OVF_DIS43 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS43(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS43_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS43_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS44_MASK (0x1000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS44_SHIFT (12U) /*! OVF_DIS44 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS44(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS44_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS44_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS45_MASK (0x2000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS45_SHIFT (13U) /*! OVF_DIS45 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS45(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS45_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS45_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS46_MASK (0x4000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS46_SHIFT (14U) /*! OVF_DIS46 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS46(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS46_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS46_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS47_MASK (0x8000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS47_SHIFT (15U) /*! OVF_DIS47 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS47(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS47_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS47_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS48_MASK (0x10000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS48_SHIFT (16U) /*! OVF_DIS48 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS48(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS48_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS48_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS49_MASK (0x20000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS49_SHIFT (17U) /*! OVF_DIS49 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS49(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS49_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS49_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS50_MASK (0x40000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS50_SHIFT (18U) /*! OVF_DIS50 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS50(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS50_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS50_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS51_MASK (0x80000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS51_SHIFT (19U) /*! OVF_DIS51 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS51(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS51_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS51_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS52_MASK (0x100000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS52_SHIFT (20U) /*! OVF_DIS52 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS52(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS52_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS52_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS53_MASK (0x200000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS53_SHIFT (21U) /*! OVF_DIS53 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS53(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS53_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS53_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS54_MASK (0x400000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS54_SHIFT (22U) /*! OVF_DIS54 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS54(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS54_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS54_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS55_MASK (0x800000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS55_SHIFT (23U) /*! OVF_DIS55 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS55(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS55_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS55_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS56_MASK (0x1000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS56_SHIFT (24U) /*! OVF_DIS56 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS56(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS56_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS56_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS57_MASK (0x2000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS57_SHIFT (25U) /*! OVF_DIS57 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS57(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS57_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS57_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS58_MASK (0x4000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS58_SHIFT (26U) /*! OVF_DIS58 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS58(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS58_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS58_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS59_MASK (0x8000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS59_SHIFT (27U) /*! OVF_DIS59 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS59(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS59_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS59_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS60_MASK (0x10000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS60_SHIFT (28U) /*! OVF_DIS60 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS60(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS60_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS60_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS61_MASK (0x20000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS61_SHIFT (29U) /*! OVF_DIS61 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS61(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS61_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS61_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS62_MASK (0x40000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS62_SHIFT (30U) /*! OVF_DIS62 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS62(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS62_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS62_MASK) #define AON_FCCU_GFLTOVDC1_OVF_DIS63_MASK (0x80000000U) #define AON_FCCU_GFLTOVDC1_OVF_DIS63_SHIFT (31U) /*! OVF_DIS63 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC1_OVF_DIS63(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC1_OVF_DIS63_SHIFT)) & AON_FCCU_GFLTOVDC1_OVF_DIS63_MASK) /*! @} */ /*! @name GFLTOVDC2 - Global Fault Overflow Detection */ /*! @{ */ #define AON_FCCU_GFLTOVDC2_OVF_DIS64_MASK (0x1U) #define AON_FCCU_GFLTOVDC2_OVF_DIS64_SHIFT (0U) /*! OVF_DIS64 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS64(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS64_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS64_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS65_MASK (0x2U) #define AON_FCCU_GFLTOVDC2_OVF_DIS65_SHIFT (1U) /*! OVF_DIS65 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS65(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS65_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS65_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS66_MASK (0x4U) #define AON_FCCU_GFLTOVDC2_OVF_DIS66_SHIFT (2U) /*! OVF_DIS66 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS66(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS66_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS66_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS67_MASK (0x8U) #define AON_FCCU_GFLTOVDC2_OVF_DIS67_SHIFT (3U) /*! OVF_DIS67 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS67(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS67_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS67_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS68_MASK (0x10U) #define AON_FCCU_GFLTOVDC2_OVF_DIS68_SHIFT (4U) /*! OVF_DIS68 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS68(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS68_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS68_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS69_MASK (0x20U) #define AON_FCCU_GFLTOVDC2_OVF_DIS69_SHIFT (5U) /*! OVF_DIS69 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS69(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS69_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS69_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS70_MASK (0x40U) #define AON_FCCU_GFLTOVDC2_OVF_DIS70_SHIFT (6U) /*! OVF_DIS70 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS70(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS70_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS70_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS71_MASK (0x80U) #define AON_FCCU_GFLTOVDC2_OVF_DIS71_SHIFT (7U) /*! OVF_DIS71 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS71(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS71_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS71_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS72_MASK (0x100U) #define AON_FCCU_GFLTOVDC2_OVF_DIS72_SHIFT (8U) /*! OVF_DIS72 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS72(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS72_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS72_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS73_MASK (0x200U) #define AON_FCCU_GFLTOVDC2_OVF_DIS73_SHIFT (9U) /*! OVF_DIS73 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS73(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS73_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS73_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS74_MASK (0x400U) #define AON_FCCU_GFLTOVDC2_OVF_DIS74_SHIFT (10U) /*! OVF_DIS74 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS74(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS74_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS74_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS75_MASK (0x800U) #define AON_FCCU_GFLTOVDC2_OVF_DIS75_SHIFT (11U) /*! OVF_DIS75 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS75(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS75_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS75_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS76_MASK (0x1000U) #define AON_FCCU_GFLTOVDC2_OVF_DIS76_SHIFT (12U) /*! OVF_DIS76 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS76(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS76_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS76_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS77_MASK (0x2000U) #define AON_FCCU_GFLTOVDC2_OVF_DIS77_SHIFT (13U) /*! OVF_DIS77 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS77(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS77_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS77_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS78_MASK (0x4000U) #define AON_FCCU_GFLTOVDC2_OVF_DIS78_SHIFT (14U) /*! OVF_DIS78 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS78(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS78_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS78_MASK) #define AON_FCCU_GFLTOVDC2_OVF_DIS79_MASK (0x8000U) #define AON_FCCU_GFLTOVDC2_OVF_DIS79_SHIFT (15U) /*! OVF_DIS79 - Fault Overflow Detection Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GFLTOVDC2_OVF_DIS79(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GFLTOVDC2_OVF_DIS79_SHIFT)) & AON_FCCU_GFLTOVDC2_OVF_DIS79_MASK) /*! @} */ /*! @name GRKNTIMS - Global Reaction Timer Status */ /*! @{ */ #define AON_FCCU_GRKNTIMS_RKTIMVAL_MASK (0xFFFFFFFFU) #define AON_FCCU_GRKNTIMS_RKTIMVAL_SHIFT (0U) /*! RKTIMVAL - Current Reaction Timer */ #define AON_FCCU_GRKNTIMS_RKTIMVAL(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GRKNTIMS_RKTIMVAL_SHIFT)) & AON_FCCU_GRKNTIMS_RKTIMVAL_MASK) /*! @} */ /*! @name GCTRL - Global Space Control */ /*! @{ */ #define AON_FCCU_GCTRL_OVF_EN_MASK (0x1U) #define AON_FCCU_GCTRL_OVF_EN_SHIFT (0U) /*! OVF_EN - Overflow Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GCTRL_OVF_EN(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GCTRL_OVF_EN_SHIFT)) & AON_FCCU_GCTRL_OVF_EN_MASK) /*! @} */ /*! @name GINTOVFS - Global DID FSM Status */ /*! @{ */ #define AON_FCCU_GINTOVFS_FSMSTATE_MASK (0x3U) #define AON_FCCU_GINTOVFS_FSMSTATE_SHIFT (0U) /*! FSMSTATE - FSM State * 0b00..Idle * 0b01..Immediate reaction * 0b10..Delayed reaction * 0b11..Global reaction */ #define AON_FCCU_GINTOVFS_FSMSTATE(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GINTOVFS_FSMSTATE_SHIFT)) & AON_FCCU_GINTOVFS_FSMSTATE_MASK) #define AON_FCCU_GINTOVFS_FLTSERV_MASK (0x80U) #define AON_FCCU_GINTOVFS_FLTSERV_SHIFT (7U) /*! FLTSERV - Fault Serve * 0b0..No fault asserted * 0b1..At least one fault asserted */ #define AON_FCCU_GINTOVFS_FLTSERV(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GINTOVFS_FLTSERV_SHIFT)) & AON_FCCU_GINTOVFS_FLTSERV_MASK) #define AON_FCCU_GINTOVFS_OVF_DET_MASK (0x100U) #define AON_FCCU_GINTOVFS_OVF_DET_SHIFT (8U) /*! OVF_DET - Overflow Detect * 0b0..Not detected * 0b1..Detected */ #define AON_FCCU_GINTOVFS_OVF_DET(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GINTOVFS_OVF_DET_SHIFT)) & AON_FCCU_GINTOVFS_OVF_DET_MASK) #define AON_FCCU_GINTOVFS_SERV_DID_MASK (0xF0000U) #define AON_FCCU_GINTOVFS_SERV_DID_SHIFT (16U) /*! SERV_DID - Domain Being Serviced */ #define AON_FCCU_GINTOVFS_SERV_DID(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GINTOVFS_SERV_DID_SHIFT)) & AON_FCCU_GINTOVFS_SERV_DID_MASK) #define AON_FCCU_GINTOVFS_OVF_DID_MASK (0xF000000U) #define AON_FCCU_GINTOVFS_OVF_DID_SHIFT (24U) /*! OVF_DID - Overflow DID */ #define AON_FCCU_GINTOVFS_OVF_DID(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GINTOVFS_OVF_DID_SHIFT)) & AON_FCCU_GINTOVFS_OVF_DID_MASK) /*! @} */ /*! @name GOVFRKC - Global Overflow Reaction */ /*! @{ */ #define AON_FCCU_GOVFRKC_EOUTEN0_MASK (0x1U) #define AON_FCCU_GOVFRKC_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_EOUTEN0_SHIFT)) & AON_FCCU_GOVFRKC_EOUTEN0_MASK) #define AON_FCCU_GOVFRKC_EOUTEN1_MASK (0x2U) #define AON_FCCU_GOVFRKC_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_EOUTEN1_SHIFT)) & AON_FCCU_GOVFRKC_EOUTEN1_MASK) #define AON_FCCU_GOVFRKC_RKNEN0_MASK (0x4U) #define AON_FCCU_GOVFRKC_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_RKNEN0_SHIFT)) & AON_FCCU_GOVFRKC_RKNEN0_MASK) #define AON_FCCU_GOVFRKC_RKNEN1_MASK (0x8U) #define AON_FCCU_GOVFRKC_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_RKNEN1_SHIFT)) & AON_FCCU_GOVFRKC_RKNEN1_MASK) #define AON_FCCU_GOVFRKC_RKNEN2_MASK (0x10U) #define AON_FCCU_GOVFRKC_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_RKNEN2_SHIFT)) & AON_FCCU_GOVFRKC_RKNEN2_MASK) #define AON_FCCU_GOVFRKC_RKNEN3_MASK (0x20U) #define AON_FCCU_GOVFRKC_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_RKNEN3_SHIFT)) & AON_FCCU_GOVFRKC_RKNEN3_MASK) #define AON_FCCU_GOVFRKC_RKNEN4_MASK (0x40U) #define AON_FCCU_GOVFRKC_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_RKNEN4_SHIFT)) & AON_FCCU_GOVFRKC_RKNEN4_MASK) #define AON_FCCU_GOVFRKC_RKNEN5_MASK (0x80U) #define AON_FCCU_GOVFRKC_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_RKNEN5_SHIFT)) & AON_FCCU_GOVFRKC_RKNEN5_MASK) #define AON_FCCU_GOVFRKC_RKNEN6_MASK (0x100U) #define AON_FCCU_GOVFRKC_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GOVFRKC_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GOVFRKC_RKNEN6_SHIFT)) & AON_FCCU_GOVFRKC_RKNEN6_MASK) /*! @} */ /* The count of AON_FCCU_GOVFRKC */ #define AON_FCCU_GOVFRKC_COUNT (1U) /*! @name GMEOUTDC - Global Minimum EOUT Duration */ /*! @{ */ #define AON_FCCU_GMEOUTDC_EOUTMIND_MASK (0xFFFFFFFFU) #define AON_FCCU_GMEOUTDC_EOUTMIND_SHIFT (0U) /*! EOUTMIND - EOUT Minimum Duration */ #define AON_FCCU_GMEOUTDC_EOUTMIND(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GMEOUTDC_EOUTMIND_SHIFT)) & AON_FCCU_GMEOUTDC_EOUTMIND_MASK) /*! @} */ /*! @name GEOUTTCT - Global EOUT Timer Disable */ /*! @{ */ #define AON_FCCU_GEOUTTCT_TMRDIS0_MASK (0x1U) #define AON_FCCU_GEOUTTCT_TMRDIS0_SHIFT (0U) /*! TMRDIS0 - Timer Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GEOUTTCT_TMRDIS0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTTCT_TMRDIS0_SHIFT)) & AON_FCCU_GEOUTTCT_TMRDIS0_MASK) #define AON_FCCU_GEOUTTCT_TMRDIS1_MASK (0x2U) #define AON_FCCU_GEOUTTCT_TMRDIS1_SHIFT (1U) /*! TMRDIS1 - Timer Disable * 0b0..Enables * 0b1..Disables */ #define AON_FCCU_GEOUTTCT_TMRDIS1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTTCT_TMRDIS1_SHIFT)) & AON_FCCU_GEOUTTCT_TMRDIS1_MASK) /*! @} */ /*! @name GEOUTPNC - Global EOUT Pin */ /*! @{ */ #define AON_FCCU_GEOUTPNC_OBE_VALID_MASK (0x1U) #define AON_FCCU_GEOUTPNC_OBE_VALID_SHIFT (0U) /*! OBE_VALID - Output Buffer Enable Valid * 0b0..Invalid (can be overridden) * 0b1..Valid (cannot be overridden) */ #define AON_FCCU_GEOUTPNC_OBE_VALID(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_OBE_VALID_SHIFT)) & AON_FCCU_GEOUTPNC_OBE_VALID_MASK) #define AON_FCCU_GEOUTPNC_OBE_STAT_MASK (0x2U) #define AON_FCCU_GEOUTPNC_OBE_STAT_SHIFT (1U) /*! OBE_STAT - Output Buffer Enable Status * 0b0..Disabled * 0b1..Enabled */ #define AON_FCCU_GEOUTPNC_OBE_STAT(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_OBE_STAT_SHIFT)) & AON_FCCU_GEOUTPNC_OBE_STAT_MASK) #define AON_FCCU_GEOUTPNC_DO_STAT_MASK (0x8U) #define AON_FCCU_GEOUTPNC_DO_STAT_SHIFT (3U) /*! DO_STAT - Data Output Status * 0b0..Low * 0b1..High */ #define AON_FCCU_GEOUTPNC_DO_STAT(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_DO_STAT_SHIFT)) & AON_FCCU_GEOUTPNC_DO_STAT_MASK) #define AON_FCCU_GEOUTPNC_VAL_CTRL_MASK (0x30U) #define AON_FCCU_GEOUTPNC_VAL_CTRL_SHIFT (4U) /*! VAL_CTRL - Invert Output * 0b00..FSM State, fault status for faults with EOUT enable and EOUT mode-dependent * 0b01..Always low * 0b10..FSM State, fault status for faults with EOUT enable and EOUT mode-dependent * 0b11..Always high */ #define AON_FCCU_GEOUTPNC_VAL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_VAL_CTRL_SHIFT)) & AON_FCCU_GEOUTPNC_VAL_CTRL_MASK) #define AON_FCCU_GEOUTPNC_IBE_MASK (0x100U) #define AON_FCCU_GEOUTPNC_IBE_SHIFT (8U) /*! IBE - Input Buffer Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GEOUTPNC_IBE(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_IBE_SHIFT)) & AON_FCCU_GEOUTPNC_IBE_MASK) #define AON_FCCU_GEOUTPNC_IND_STAT_MASK (0x200U) #define AON_FCCU_GEOUTPNC_IND_STAT_SHIFT (9U) /*! IND_STAT - Input Data From Pad * 0b0..0 * 0b1..1 */ #define AON_FCCU_GEOUTPNC_IND_STAT(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_IND_STAT_SHIFT)) & AON_FCCU_GEOUTPNC_IND_STAT_MASK) #define AON_FCCU_GEOUTPNC_INV_IP_MASK (0x400U) #define AON_FCCU_GEOUTPNC_INV_IP_SHIFT (10U) /*! INV_IP - Invert Input * 0b0..No inversion * 0b1..Inverted */ #define AON_FCCU_GEOUTPNC_INV_IP(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_INV_IP_SHIFT)) & AON_FCCU_GEOUTPNC_INV_IP_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL1_MASK (0x10000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL1_SHIFT (16U) /*! SOC_PAD_CTRL1 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL1_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL1_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL2_MASK (0x20000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL2_SHIFT (17U) /*! SOC_PAD_CTRL2 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL2_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL2_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL3_MASK (0x40000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL3_SHIFT (18U) /*! SOC_PAD_CTRL3 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL3_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL3_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL4_MASK (0x80000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL4_SHIFT (19U) /*! SOC_PAD_CTRL4 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL4_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL4_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL5_MASK (0x100000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL5_SHIFT (20U) /*! SOC_PAD_CTRL5 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL5_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL5_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL6_MASK (0x200000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL6_SHIFT (21U) /*! SOC_PAD_CTRL6 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL6_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL6_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL7_MASK (0x400000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL7_SHIFT (22U) /*! SOC_PAD_CTRL7 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL7_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL7_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL8_MASK (0x800000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL8_SHIFT (23U) /*! SOC_PAD_CTRL8 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL8(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL8_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL8_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL9_MASK (0x1000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL9_SHIFT (24U) /*! SOC_PAD_CTRL9 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL9(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL9_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL9_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL10_MASK (0x2000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL10_SHIFT (25U) /*! SOC_PAD_CTRL10 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL10(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL10_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL10_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL11_MASK (0x4000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL11_SHIFT (26U) /*! SOC_PAD_CTRL11 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL11(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL11_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL11_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL12_MASK (0x8000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL12_SHIFT (27U) /*! SOC_PAD_CTRL12 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL12(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL12_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL12_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL13_MASK (0x10000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL13_SHIFT (28U) /*! SOC_PAD_CTRL13 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL13(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL13_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL13_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL14_MASK (0x20000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL14_SHIFT (29U) /*! SOC_PAD_CTRL14 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL14(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL14_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL14_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL15_MASK (0x40000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL15_SHIFT (30U) /*! SOC_PAD_CTRL15 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL15(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL15_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL15_MASK) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL16_MASK (0x80000000U) #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL16_SHIFT (31U) /*! SOC_PAD_CTRL16 - SoC Pad Control */ #define AON_FCCU_GEOUTPNC_SOC_PAD_CTRL16(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPNC_SOC_PAD_CTRL16_SHIFT)) & AON_FCCU_GEOUTPNC_SOC_PAD_CTRL16_MASK) /*! @} */ /* The count of AON_FCCU_GEOUTPNC */ #define AON_FCCU_GEOUTPNC_COUNT (2U) /*! @name GEOUTPMC - Global EOUT Pin Map */ /*! @{ */ #define AON_FCCU_GEOUTPMC_SPLENB0_MASK (0x1U) #define AON_FCCU_GEOUTPMC_SPLENB0_SHIFT (0U) /*! SPLENB0 - Special Enable Pins */ #define AON_FCCU_GEOUTPMC_SPLENB0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPMC_SPLENB0_SHIFT)) & AON_FCCU_GEOUTPMC_SPLENB0_MASK) #define AON_FCCU_GEOUTPMC_SPLENB1_MASK (0x2U) #define AON_FCCU_GEOUTPMC_SPLENB1_SHIFT (1U) /*! SPLENB1 - Special Enable Pins */ #define AON_FCCU_GEOUTPMC_SPLENB1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPMC_SPLENB1_SHIFT)) & AON_FCCU_GEOUTPMC_SPLENB1_MASK) #define AON_FCCU_GEOUTPMC_SPLENB2_MASK (0x4U) #define AON_FCCU_GEOUTPMC_SPLENB2_SHIFT (2U) /*! SPLENB2 - Special Enable Pins */ #define AON_FCCU_GEOUTPMC_SPLENB2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPMC_SPLENB2_SHIFT)) & AON_FCCU_GEOUTPMC_SPLENB2_MASK) #define AON_FCCU_GEOUTPMC_SPLENB3_MASK (0x8U) #define AON_FCCU_GEOUTPMC_SPLENB3_SHIFT (3U) /*! SPLENB3 - Special Enable Pins */ #define AON_FCCU_GEOUTPMC_SPLENB3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTPMC_SPLENB3_SHIFT)) & AON_FCCU_GEOUTPMC_SPLENB3_MASK) /*! @} */ /* The count of AON_FCCU_GEOUTPMC */ #define AON_FCCU_GEOUTPMC_COUNT (2U) /*! @name GEOUTMC - Global EOUT Mode */ /*! @{ */ #define AON_FCCU_GEOUTMC_EOUTM_MASK (0x7U) #define AON_FCCU_GEOUTMC_EOUTM_SHIFT (0U) /*! EOUTM - EOUT Pin Mode * 0b000..Input only (high-Z, default and safe-state) * 0b001..Push-pull (drive 1 for fault, 0 for normal) * 0b010..Open-drain (drive 0 for fault, high-Z for normal) * 0b011..Open-collector (drive 1 for fault, high-Z for normal) * 0b100..Bi-stable * 0b101..Fault-toggle * *.. */ #define AON_FCCU_GEOUTMC_EOUTM(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTMC_EOUTM_SHIFT)) & AON_FCCU_GEOUTMC_EOUTM_MASK) #define AON_FCCU_GEOUTMC_INV_MASK (0x8U) #define AON_FCCU_GEOUTMC_INV_SHIFT (3U) /*! INV - Invert EOUT * 0b0..Not inverted * 0b1..Inverted */ #define AON_FCCU_GEOUTMC_INV(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTMC_INV_SHIFT)) & AON_FCCU_GEOUTMC_INV_MASK) /*! @} */ /* The count of AON_FCCU_GEOUTMC */ #define AON_FCCU_GEOUTMC_COUNT (2U) /*! @name GEOUTTMS - Global EOUT Timer Status */ /*! @{ */ #define AON_FCCU_GEOUTTMS_EOUTDVAL_MASK (0xFFFFFFFFU) #define AON_FCCU_GEOUTTMS_EOUTDVAL_SHIFT (0U) /*! EOUTDVAL - EOUT (minimum duration timer) Timer Current Value */ #define AON_FCCU_GEOUTTMS_EOUTDVAL(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTTMS_EOUTDVAL_SHIFT)) & AON_FCCU_GEOUTTMS_EOUTDVAL_MASK) /*! @} */ /* The count of AON_FCCU_GEOUTTMS */ #define AON_FCCU_GEOUTTMS_COUNT (2U) /*! @name GEOUTDIC - Global EOUT DID */ /*! @{ */ #define AON_FCCU_GEOUTDIC_DID_EOUT_MASK (0xFU) #define AON_FCCU_GEOUTDIC_DID_EOUT_SHIFT (0U) /*! DID_EOUT - DID for Fault on EOUT */ #define AON_FCCU_GEOUTDIC_DID_EOUT(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GEOUTDIC_DID_EOUT_SHIFT)) & AON_FCCU_GEOUTDIC_DID_EOUT_MASK) /*! @} */ /* The count of AON_FCCU_GEOUTDIC */ #define AON_FCCU_GEOUTDIC_COUNT (2U) /*! @name GDBGCFG - Global Debug */ /*! @{ */ #define AON_FCCU_GDBGCFG_FRZ_MASK (0x10000U) #define AON_FCCU_GDBGCFG_FRZ_SHIFT (16U) /*! FRZ - Freeze On First Fault * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_GDBGCFG_FRZ(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GDBGCFG_FRZ_SHIFT)) & AON_FCCU_GDBGCFG_FRZ_MASK) /*! @} */ /*! @name GDBGSTAT - Global Debug Status */ /*! @{ */ #define AON_FCCU_GDBGSTAT_FLTIND_MASK (0xFFU) #define AON_FCCU_GDBGSTAT_FLTIND_SHIFT (0U) /*! FLTIND - Fault Index */ #define AON_FCCU_GDBGSTAT_FLTIND(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GDBGSTAT_FLTIND_SHIFT)) & AON_FCCU_GDBGSTAT_FLTIND_MASK) /*! @} */ /*! @name GDPFSTAT - Global Debug Pending Fault Status */ /*! @{ */ #define AON_FCCU_GDPFSTAT_PENDFLT0_MASK (0x1U) #define AON_FCCU_GDPFSTAT_PENDFLT0_SHIFT (0U) /*! PENDFLT0 - Pending Fault Status for corresponding EOUT pin */ #define AON_FCCU_GDPFSTAT_PENDFLT0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GDPFSTAT_PENDFLT0_SHIFT)) & AON_FCCU_GDPFSTAT_PENDFLT0_MASK) #define AON_FCCU_GDPFSTAT_PENDFLT1_MASK (0x2U) #define AON_FCCU_GDPFSTAT_PENDFLT1_SHIFT (1U) /*! PENDFLT1 - Pending Fault Status for corresponding EOUT pin */ #define AON_FCCU_GDPFSTAT_PENDFLT1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GDPFSTAT_PENDFLT1_SHIFT)) & AON_FCCU_GDPFSTAT_PENDFLT1_MASK) /*! @} */ /*! @name GDALTRLD - Global Debug Alternate Reload Status */ /*! @{ */ #define AON_FCCU_GDALTRLD_ALTRLD0_MASK (0x1U) #define AON_FCCU_GDALTRLD_ALTRLD0_SHIFT (0U) /*! ALTRLD0 - Alternate timer reload status for corresponding EOUT pin */ #define AON_FCCU_GDALTRLD_ALTRLD0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GDALTRLD_ALTRLD0_SHIFT)) & AON_FCCU_GDALTRLD_ALTRLD0_MASK) #define AON_FCCU_GDALTRLD_ALTRLD1_MASK (0x2U) #define AON_FCCU_GDALTRLD_ALTRLD1_SHIFT (1U) /*! ALTRLD1 - Alternate timer reload status for corresponding EOUT pin */ #define AON_FCCU_GDALTRLD_ALTRLD1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_GDALTRLD_ALTRLD1_SHIFT)) & AON_FCCU_GDALTRLD_ALTRLD1_MASK) /*! @} */ /*! @name FHCFG0 - Fault Handler */ /*! @{ */ #define AON_FCCU_FHCFG0_FHIDEN_MASK (0x1U) #define AON_FCCU_FHCFG0_FHIDEN_SHIFT (0U) /*! FHIDEN - Fault Handler Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHCFG0_FHIDEN(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHCFG0_FHIDEN_SHIFT)) & AON_FCCU_FHCFG0_FHIDEN_MASK) /*! @} */ /*! @name FHSRVDS0 - Fault Handler Status */ /*! @{ */ #define AON_FCCU_FHSRVDS0_SERV_DID_MASK (0xFU) #define AON_FCCU_FHSRVDS0_SERV_DID_SHIFT (0U) /*! SERV_DID - DID Being Serviced */ #define AON_FCCU_FHSRVDS0_SERV_DID(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHSRVDS0_SERV_DID_SHIFT)) & AON_FCCU_FHSRVDS0_SERV_DID_MASK) #define AON_FCCU_FHSRVDS0_AGGFLTS_MASK (0x100U) #define AON_FCCU_FHSRVDS0_AGGFLTS_SHIFT (8U) /*! AGGFLTS - Aggregated Fault Status * 0b0..No faults * 0b1..At least one fault */ #define AON_FCCU_FHSRVDS0_AGGFLTS(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHSRVDS0_AGGFLTS_SHIFT)) & AON_FCCU_FHSRVDS0_AGGFLTS_MASK) /*! @} */ /*! @name FHFLTENC0_0 - Fault Enable */ /*! @{ */ #define AON_FCCU_FHFLTENC0_0_EN0_MASK (0x1U) #define AON_FCCU_FHFLTENC0_0_EN0_SHIFT (0U) /*! EN0 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN0_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN0_MASK) #define AON_FCCU_FHFLTENC0_0_EN1_MASK (0x2U) #define AON_FCCU_FHFLTENC0_0_EN1_SHIFT (1U) /*! EN1 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN1_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN1_MASK) #define AON_FCCU_FHFLTENC0_0_EN2_MASK (0x4U) #define AON_FCCU_FHFLTENC0_0_EN2_SHIFT (2U) /*! EN2 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN2_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN2_MASK) #define AON_FCCU_FHFLTENC0_0_EN3_MASK (0x8U) #define AON_FCCU_FHFLTENC0_0_EN3_SHIFT (3U) /*! EN3 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN3_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN3_MASK) #define AON_FCCU_FHFLTENC0_0_EN4_MASK (0x10U) #define AON_FCCU_FHFLTENC0_0_EN4_SHIFT (4U) /*! EN4 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN4_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN4_MASK) #define AON_FCCU_FHFLTENC0_0_EN5_MASK (0x20U) #define AON_FCCU_FHFLTENC0_0_EN5_SHIFT (5U) /*! EN5 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN5_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN5_MASK) #define AON_FCCU_FHFLTENC0_0_EN6_MASK (0x40U) #define AON_FCCU_FHFLTENC0_0_EN6_SHIFT (6U) /*! EN6 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN6_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN6_MASK) #define AON_FCCU_FHFLTENC0_0_EN7_MASK (0x80U) #define AON_FCCU_FHFLTENC0_0_EN7_SHIFT (7U) /*! EN7 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN7(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN7_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN7_MASK) #define AON_FCCU_FHFLTENC0_0_EN8_MASK (0x100U) #define AON_FCCU_FHFLTENC0_0_EN8_SHIFT (8U) /*! EN8 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN8(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN8_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN8_MASK) #define AON_FCCU_FHFLTENC0_0_EN9_MASK (0x200U) #define AON_FCCU_FHFLTENC0_0_EN9_SHIFT (9U) /*! EN9 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN9(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN9_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN9_MASK) #define AON_FCCU_FHFLTENC0_0_EN10_MASK (0x400U) #define AON_FCCU_FHFLTENC0_0_EN10_SHIFT (10U) /*! EN10 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN10(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN10_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN10_MASK) #define AON_FCCU_FHFLTENC0_0_EN11_MASK (0x800U) #define AON_FCCU_FHFLTENC0_0_EN11_SHIFT (11U) /*! EN11 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN11(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN11_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN11_MASK) #define AON_FCCU_FHFLTENC0_0_EN12_MASK (0x1000U) #define AON_FCCU_FHFLTENC0_0_EN12_SHIFT (12U) /*! EN12 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN12(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN12_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN12_MASK) #define AON_FCCU_FHFLTENC0_0_EN13_MASK (0x2000U) #define AON_FCCU_FHFLTENC0_0_EN13_SHIFT (13U) /*! EN13 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN13(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN13_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN13_MASK) #define AON_FCCU_FHFLTENC0_0_EN14_MASK (0x4000U) #define AON_FCCU_FHFLTENC0_0_EN14_SHIFT (14U) /*! EN14 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN14(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN14_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN14_MASK) #define AON_FCCU_FHFLTENC0_0_EN15_MASK (0x8000U) #define AON_FCCU_FHFLTENC0_0_EN15_SHIFT (15U) /*! EN15 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN15(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN15_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN15_MASK) #define AON_FCCU_FHFLTENC0_0_EN16_MASK (0x10000U) #define AON_FCCU_FHFLTENC0_0_EN16_SHIFT (16U) /*! EN16 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN16(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN16_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN16_MASK) #define AON_FCCU_FHFLTENC0_0_EN17_MASK (0x20000U) #define AON_FCCU_FHFLTENC0_0_EN17_SHIFT (17U) /*! EN17 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN17(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN17_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN17_MASK) #define AON_FCCU_FHFLTENC0_0_EN18_MASK (0x40000U) #define AON_FCCU_FHFLTENC0_0_EN18_SHIFT (18U) /*! EN18 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN18(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN18_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN18_MASK) #define AON_FCCU_FHFLTENC0_0_EN19_MASK (0x80000U) #define AON_FCCU_FHFLTENC0_0_EN19_SHIFT (19U) /*! EN19 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN19(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN19_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN19_MASK) #define AON_FCCU_FHFLTENC0_0_EN20_MASK (0x100000U) #define AON_FCCU_FHFLTENC0_0_EN20_SHIFT (20U) /*! EN20 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN20(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN20_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN20_MASK) #define AON_FCCU_FHFLTENC0_0_EN21_MASK (0x200000U) #define AON_FCCU_FHFLTENC0_0_EN21_SHIFT (21U) /*! EN21 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN21(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN21_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN21_MASK) #define AON_FCCU_FHFLTENC0_0_EN22_MASK (0x400000U) #define AON_FCCU_FHFLTENC0_0_EN22_SHIFT (22U) /*! EN22 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN22(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN22_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN22_MASK) #define AON_FCCU_FHFLTENC0_0_EN23_MASK (0x800000U) #define AON_FCCU_FHFLTENC0_0_EN23_SHIFT (23U) /*! EN23 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN23(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN23_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN23_MASK) #define AON_FCCU_FHFLTENC0_0_EN24_MASK (0x1000000U) #define AON_FCCU_FHFLTENC0_0_EN24_SHIFT (24U) /*! EN24 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN24(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN24_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN24_MASK) #define AON_FCCU_FHFLTENC0_0_EN25_MASK (0x2000000U) #define AON_FCCU_FHFLTENC0_0_EN25_SHIFT (25U) /*! EN25 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN25(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN25_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN25_MASK) #define AON_FCCU_FHFLTENC0_0_EN26_MASK (0x4000000U) #define AON_FCCU_FHFLTENC0_0_EN26_SHIFT (26U) /*! EN26 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN26(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN26_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN26_MASK) #define AON_FCCU_FHFLTENC0_0_EN27_MASK (0x8000000U) #define AON_FCCU_FHFLTENC0_0_EN27_SHIFT (27U) /*! EN27 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN27(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN27_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN27_MASK) #define AON_FCCU_FHFLTENC0_0_EN28_MASK (0x10000000U) #define AON_FCCU_FHFLTENC0_0_EN28_SHIFT (28U) /*! EN28 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN28(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN28_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN28_MASK) #define AON_FCCU_FHFLTENC0_0_EN29_MASK (0x20000000U) #define AON_FCCU_FHFLTENC0_0_EN29_SHIFT (29U) /*! EN29 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN29(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN29_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN29_MASK) #define AON_FCCU_FHFLTENC0_0_EN30_MASK (0x40000000U) #define AON_FCCU_FHFLTENC0_0_EN30_SHIFT (30U) /*! EN30 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN30(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN30_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN30_MASK) #define AON_FCCU_FHFLTENC0_0_EN31_MASK (0x80000000U) #define AON_FCCU_FHFLTENC0_0_EN31_SHIFT (31U) /*! EN31 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_0_EN31(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_0_EN31_SHIFT)) & AON_FCCU_FHFLTENC0_0_EN31_MASK) /*! @} */ /*! @name FHFLTENC0_1 - Fault Enable */ /*! @{ */ #define AON_FCCU_FHFLTENC0_1_EN32_MASK (0x1U) #define AON_FCCU_FHFLTENC0_1_EN32_SHIFT (0U) /*! EN32 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN32(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN32_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN32_MASK) #define AON_FCCU_FHFLTENC0_1_EN33_MASK (0x2U) #define AON_FCCU_FHFLTENC0_1_EN33_SHIFT (1U) /*! EN33 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN33(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN33_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN33_MASK) #define AON_FCCU_FHFLTENC0_1_EN34_MASK (0x4U) #define AON_FCCU_FHFLTENC0_1_EN34_SHIFT (2U) /*! EN34 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN34(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN34_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN34_MASK) #define AON_FCCU_FHFLTENC0_1_EN35_MASK (0x8U) #define AON_FCCU_FHFLTENC0_1_EN35_SHIFT (3U) /*! EN35 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN35(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN35_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN35_MASK) #define AON_FCCU_FHFLTENC0_1_EN36_MASK (0x10U) #define AON_FCCU_FHFLTENC0_1_EN36_SHIFT (4U) /*! EN36 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN36(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN36_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN36_MASK) #define AON_FCCU_FHFLTENC0_1_EN37_MASK (0x20U) #define AON_FCCU_FHFLTENC0_1_EN37_SHIFT (5U) /*! EN37 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN37(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN37_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN37_MASK) #define AON_FCCU_FHFLTENC0_1_EN38_MASK (0x40U) #define AON_FCCU_FHFLTENC0_1_EN38_SHIFT (6U) /*! EN38 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN38(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN38_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN38_MASK) #define AON_FCCU_FHFLTENC0_1_EN39_MASK (0x80U) #define AON_FCCU_FHFLTENC0_1_EN39_SHIFT (7U) /*! EN39 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN39(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN39_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN39_MASK) #define AON_FCCU_FHFLTENC0_1_EN40_MASK (0x100U) #define AON_FCCU_FHFLTENC0_1_EN40_SHIFT (8U) /*! EN40 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN40(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN40_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN40_MASK) #define AON_FCCU_FHFLTENC0_1_EN41_MASK (0x200U) #define AON_FCCU_FHFLTENC0_1_EN41_SHIFT (9U) /*! EN41 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN41(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN41_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN41_MASK) #define AON_FCCU_FHFLTENC0_1_EN42_MASK (0x400U) #define AON_FCCU_FHFLTENC0_1_EN42_SHIFT (10U) /*! EN42 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN42(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN42_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN42_MASK) #define AON_FCCU_FHFLTENC0_1_EN43_MASK (0x800U) #define AON_FCCU_FHFLTENC0_1_EN43_SHIFT (11U) /*! EN43 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN43(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN43_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN43_MASK) #define AON_FCCU_FHFLTENC0_1_EN44_MASK (0x1000U) #define AON_FCCU_FHFLTENC0_1_EN44_SHIFT (12U) /*! EN44 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN44(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN44_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN44_MASK) #define AON_FCCU_FHFLTENC0_1_EN45_MASK (0x2000U) #define AON_FCCU_FHFLTENC0_1_EN45_SHIFT (13U) /*! EN45 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN45(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN45_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN45_MASK) #define AON_FCCU_FHFLTENC0_1_EN46_MASK (0x4000U) #define AON_FCCU_FHFLTENC0_1_EN46_SHIFT (14U) /*! EN46 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN46(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN46_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN46_MASK) #define AON_FCCU_FHFLTENC0_1_EN47_MASK (0x8000U) #define AON_FCCU_FHFLTENC0_1_EN47_SHIFT (15U) /*! EN47 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN47(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN47_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN47_MASK) #define AON_FCCU_FHFLTENC0_1_EN48_MASK (0x10000U) #define AON_FCCU_FHFLTENC0_1_EN48_SHIFT (16U) /*! EN48 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN48(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN48_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN48_MASK) #define AON_FCCU_FHFLTENC0_1_EN49_MASK (0x20000U) #define AON_FCCU_FHFLTENC0_1_EN49_SHIFT (17U) /*! EN49 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN49(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN49_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN49_MASK) #define AON_FCCU_FHFLTENC0_1_EN50_MASK (0x40000U) #define AON_FCCU_FHFLTENC0_1_EN50_SHIFT (18U) /*! EN50 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN50(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN50_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN50_MASK) #define AON_FCCU_FHFLTENC0_1_EN51_MASK (0x80000U) #define AON_FCCU_FHFLTENC0_1_EN51_SHIFT (19U) /*! EN51 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN51(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN51_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN51_MASK) #define AON_FCCU_FHFLTENC0_1_EN52_MASK (0x100000U) #define AON_FCCU_FHFLTENC0_1_EN52_SHIFT (20U) /*! EN52 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN52(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN52_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN52_MASK) #define AON_FCCU_FHFLTENC0_1_EN53_MASK (0x200000U) #define AON_FCCU_FHFLTENC0_1_EN53_SHIFT (21U) /*! EN53 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN53(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN53_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN53_MASK) #define AON_FCCU_FHFLTENC0_1_EN54_MASK (0x400000U) #define AON_FCCU_FHFLTENC0_1_EN54_SHIFT (22U) /*! EN54 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN54(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN54_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN54_MASK) #define AON_FCCU_FHFLTENC0_1_EN55_MASK (0x800000U) #define AON_FCCU_FHFLTENC0_1_EN55_SHIFT (23U) /*! EN55 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN55(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN55_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN55_MASK) #define AON_FCCU_FHFLTENC0_1_EN56_MASK (0x1000000U) #define AON_FCCU_FHFLTENC0_1_EN56_SHIFT (24U) /*! EN56 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN56(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN56_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN56_MASK) #define AON_FCCU_FHFLTENC0_1_EN57_MASK (0x2000000U) #define AON_FCCU_FHFLTENC0_1_EN57_SHIFT (25U) /*! EN57 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN57(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN57_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN57_MASK) #define AON_FCCU_FHFLTENC0_1_EN58_MASK (0x4000000U) #define AON_FCCU_FHFLTENC0_1_EN58_SHIFT (26U) /*! EN58 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN58(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN58_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN58_MASK) #define AON_FCCU_FHFLTENC0_1_EN59_MASK (0x8000000U) #define AON_FCCU_FHFLTENC0_1_EN59_SHIFT (27U) /*! EN59 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN59(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN59_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN59_MASK) #define AON_FCCU_FHFLTENC0_1_EN60_MASK (0x10000000U) #define AON_FCCU_FHFLTENC0_1_EN60_SHIFT (28U) /*! EN60 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN60(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN60_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN60_MASK) #define AON_FCCU_FHFLTENC0_1_EN61_MASK (0x20000000U) #define AON_FCCU_FHFLTENC0_1_EN61_SHIFT (29U) /*! EN61 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN61(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN61_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN61_MASK) #define AON_FCCU_FHFLTENC0_1_EN62_MASK (0x40000000U) #define AON_FCCU_FHFLTENC0_1_EN62_SHIFT (30U) /*! EN62 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN62(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN62_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN62_MASK) #define AON_FCCU_FHFLTENC0_1_EN63_MASK (0x80000000U) #define AON_FCCU_FHFLTENC0_1_EN63_SHIFT (31U) /*! EN63 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_1_EN63(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_1_EN63_SHIFT)) & AON_FCCU_FHFLTENC0_1_EN63_MASK) /*! @} */ /*! @name FHFLTENC0_2 - Fault Enable */ /*! @{ */ #define AON_FCCU_FHFLTENC0_2_EN64_MASK (0x1U) #define AON_FCCU_FHFLTENC0_2_EN64_SHIFT (0U) /*! EN64 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN64(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN64_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN64_MASK) #define AON_FCCU_FHFLTENC0_2_EN65_MASK (0x2U) #define AON_FCCU_FHFLTENC0_2_EN65_SHIFT (1U) /*! EN65 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN65(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN65_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN65_MASK) #define AON_FCCU_FHFLTENC0_2_EN66_MASK (0x4U) #define AON_FCCU_FHFLTENC0_2_EN66_SHIFT (2U) /*! EN66 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN66(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN66_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN66_MASK) #define AON_FCCU_FHFLTENC0_2_EN67_MASK (0x8U) #define AON_FCCU_FHFLTENC0_2_EN67_SHIFT (3U) /*! EN67 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN67(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN67_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN67_MASK) #define AON_FCCU_FHFLTENC0_2_EN68_MASK (0x10U) #define AON_FCCU_FHFLTENC0_2_EN68_SHIFT (4U) /*! EN68 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN68(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN68_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN68_MASK) #define AON_FCCU_FHFLTENC0_2_EN69_MASK (0x20U) #define AON_FCCU_FHFLTENC0_2_EN69_SHIFT (5U) /*! EN69 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN69(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN69_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN69_MASK) #define AON_FCCU_FHFLTENC0_2_EN70_MASK (0x40U) #define AON_FCCU_FHFLTENC0_2_EN70_SHIFT (6U) /*! EN70 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN70(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN70_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN70_MASK) #define AON_FCCU_FHFLTENC0_2_EN71_MASK (0x80U) #define AON_FCCU_FHFLTENC0_2_EN71_SHIFT (7U) /*! EN71 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN71(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN71_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN71_MASK) #define AON_FCCU_FHFLTENC0_2_EN72_MASK (0x100U) #define AON_FCCU_FHFLTENC0_2_EN72_SHIFT (8U) /*! EN72 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN72(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN72_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN72_MASK) #define AON_FCCU_FHFLTENC0_2_EN73_MASK (0x200U) #define AON_FCCU_FHFLTENC0_2_EN73_SHIFT (9U) /*! EN73 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN73(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN73_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN73_MASK) #define AON_FCCU_FHFLTENC0_2_EN74_MASK (0x400U) #define AON_FCCU_FHFLTENC0_2_EN74_SHIFT (10U) /*! EN74 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN74(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN74_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN74_MASK) #define AON_FCCU_FHFLTENC0_2_EN75_MASK (0x800U) #define AON_FCCU_FHFLTENC0_2_EN75_SHIFT (11U) /*! EN75 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN75(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN75_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN75_MASK) #define AON_FCCU_FHFLTENC0_2_EN76_MASK (0x1000U) #define AON_FCCU_FHFLTENC0_2_EN76_SHIFT (12U) /*! EN76 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN76(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN76_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN76_MASK) #define AON_FCCU_FHFLTENC0_2_EN77_MASK (0x2000U) #define AON_FCCU_FHFLTENC0_2_EN77_SHIFT (13U) /*! EN77 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN77(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN77_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN77_MASK) #define AON_FCCU_FHFLTENC0_2_EN78_MASK (0x4000U) #define AON_FCCU_FHFLTENC0_2_EN78_SHIFT (14U) /*! EN78 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN78(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN78_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN78_MASK) #define AON_FCCU_FHFLTENC0_2_EN79_MASK (0x8000U) #define AON_FCCU_FHFLTENC0_2_EN79_SHIFT (15U) /*! EN79 - Fault Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHFLTENC0_2_EN79(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTENC0_2_EN79_SHIFT)) & AON_FCCU_FHFLTENC0_2_EN79_MASK) /*! @} */ /*! @name FHFLTS0_0 - Fault Status */ /*! @{ */ #define AON_FCCU_FHFLTS0_0_STAT0_MASK (0x1U) #define AON_FCCU_FHFLTS0_0_STAT0_SHIFT (0U) /*! STAT0 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT0_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT0_MASK) #define AON_FCCU_FHFLTS0_0_STAT1_MASK (0x2U) #define AON_FCCU_FHFLTS0_0_STAT1_SHIFT (1U) /*! STAT1 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT1_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT1_MASK) #define AON_FCCU_FHFLTS0_0_STAT2_MASK (0x4U) #define AON_FCCU_FHFLTS0_0_STAT2_SHIFT (2U) /*! STAT2 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT2_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT2_MASK) #define AON_FCCU_FHFLTS0_0_STAT3_MASK (0x8U) #define AON_FCCU_FHFLTS0_0_STAT3_SHIFT (3U) /*! STAT3 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT3_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT3_MASK) #define AON_FCCU_FHFLTS0_0_STAT4_MASK (0x10U) #define AON_FCCU_FHFLTS0_0_STAT4_SHIFT (4U) /*! STAT4 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT4_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT4_MASK) #define AON_FCCU_FHFLTS0_0_STAT5_MASK (0x20U) #define AON_FCCU_FHFLTS0_0_STAT5_SHIFT (5U) /*! STAT5 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT5_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT5_MASK) #define AON_FCCU_FHFLTS0_0_STAT6_MASK (0x40U) #define AON_FCCU_FHFLTS0_0_STAT6_SHIFT (6U) /*! STAT6 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT6_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT6_MASK) #define AON_FCCU_FHFLTS0_0_STAT7_MASK (0x80U) #define AON_FCCU_FHFLTS0_0_STAT7_SHIFT (7U) /*! STAT7 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT7(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT7_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT7_MASK) #define AON_FCCU_FHFLTS0_0_STAT8_MASK (0x100U) #define AON_FCCU_FHFLTS0_0_STAT8_SHIFT (8U) /*! STAT8 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT8(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT8_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT8_MASK) #define AON_FCCU_FHFLTS0_0_STAT9_MASK (0x200U) #define AON_FCCU_FHFLTS0_0_STAT9_SHIFT (9U) /*! STAT9 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT9(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT9_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT9_MASK) #define AON_FCCU_FHFLTS0_0_STAT10_MASK (0x400U) #define AON_FCCU_FHFLTS0_0_STAT10_SHIFT (10U) /*! STAT10 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT10(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT10_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT10_MASK) #define AON_FCCU_FHFLTS0_0_STAT11_MASK (0x800U) #define AON_FCCU_FHFLTS0_0_STAT11_SHIFT (11U) /*! STAT11 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT11(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT11_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT11_MASK) #define AON_FCCU_FHFLTS0_0_STAT12_MASK (0x1000U) #define AON_FCCU_FHFLTS0_0_STAT12_SHIFT (12U) /*! STAT12 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT12(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT12_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT12_MASK) #define AON_FCCU_FHFLTS0_0_STAT13_MASK (0x2000U) #define AON_FCCU_FHFLTS0_0_STAT13_SHIFT (13U) /*! STAT13 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT13(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT13_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT13_MASK) #define AON_FCCU_FHFLTS0_0_STAT14_MASK (0x4000U) #define AON_FCCU_FHFLTS0_0_STAT14_SHIFT (14U) /*! STAT14 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT14(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT14_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT14_MASK) #define AON_FCCU_FHFLTS0_0_STAT15_MASK (0x8000U) #define AON_FCCU_FHFLTS0_0_STAT15_SHIFT (15U) /*! STAT15 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT15(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT15_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT15_MASK) #define AON_FCCU_FHFLTS0_0_STAT16_MASK (0x10000U) #define AON_FCCU_FHFLTS0_0_STAT16_SHIFT (16U) /*! STAT16 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT16(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT16_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT16_MASK) #define AON_FCCU_FHFLTS0_0_STAT17_MASK (0x20000U) #define AON_FCCU_FHFLTS0_0_STAT17_SHIFT (17U) /*! STAT17 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT17(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT17_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT17_MASK) #define AON_FCCU_FHFLTS0_0_STAT18_MASK (0x40000U) #define AON_FCCU_FHFLTS0_0_STAT18_SHIFT (18U) /*! STAT18 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT18(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT18_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT18_MASK) #define AON_FCCU_FHFLTS0_0_STAT19_MASK (0x80000U) #define AON_FCCU_FHFLTS0_0_STAT19_SHIFT (19U) /*! STAT19 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT19(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT19_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT19_MASK) #define AON_FCCU_FHFLTS0_0_STAT20_MASK (0x100000U) #define AON_FCCU_FHFLTS0_0_STAT20_SHIFT (20U) /*! STAT20 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT20(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT20_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT20_MASK) #define AON_FCCU_FHFLTS0_0_STAT21_MASK (0x200000U) #define AON_FCCU_FHFLTS0_0_STAT21_SHIFT (21U) /*! STAT21 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT21(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT21_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT21_MASK) #define AON_FCCU_FHFLTS0_0_STAT22_MASK (0x400000U) #define AON_FCCU_FHFLTS0_0_STAT22_SHIFT (22U) /*! STAT22 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT22(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT22_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT22_MASK) #define AON_FCCU_FHFLTS0_0_STAT23_MASK (0x800000U) #define AON_FCCU_FHFLTS0_0_STAT23_SHIFT (23U) /*! STAT23 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT23(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT23_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT23_MASK) #define AON_FCCU_FHFLTS0_0_STAT24_MASK (0x1000000U) #define AON_FCCU_FHFLTS0_0_STAT24_SHIFT (24U) /*! STAT24 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT24(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT24_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT24_MASK) #define AON_FCCU_FHFLTS0_0_STAT25_MASK (0x2000000U) #define AON_FCCU_FHFLTS0_0_STAT25_SHIFT (25U) /*! STAT25 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT25(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT25_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT25_MASK) #define AON_FCCU_FHFLTS0_0_STAT26_MASK (0x4000000U) #define AON_FCCU_FHFLTS0_0_STAT26_SHIFT (26U) /*! STAT26 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT26(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT26_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT26_MASK) #define AON_FCCU_FHFLTS0_0_STAT27_MASK (0x8000000U) #define AON_FCCU_FHFLTS0_0_STAT27_SHIFT (27U) /*! STAT27 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT27(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT27_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT27_MASK) #define AON_FCCU_FHFLTS0_0_STAT28_MASK (0x10000000U) #define AON_FCCU_FHFLTS0_0_STAT28_SHIFT (28U) /*! STAT28 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT28(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT28_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT28_MASK) #define AON_FCCU_FHFLTS0_0_STAT29_MASK (0x20000000U) #define AON_FCCU_FHFLTS0_0_STAT29_SHIFT (29U) /*! STAT29 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT29(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT29_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT29_MASK) #define AON_FCCU_FHFLTS0_0_STAT30_MASK (0x40000000U) #define AON_FCCU_FHFLTS0_0_STAT30_SHIFT (30U) /*! STAT30 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT30(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT30_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT30_MASK) #define AON_FCCU_FHFLTS0_0_STAT31_MASK (0x80000000U) #define AON_FCCU_FHFLTS0_0_STAT31_SHIFT (31U) /*! STAT31 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_0_STAT31(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_0_STAT31_SHIFT)) & AON_FCCU_FHFLTS0_0_STAT31_MASK) /*! @} */ /*! @name FHFLTS0_1 - Fault Status */ /*! @{ */ #define AON_FCCU_FHFLTS0_1_STAT32_MASK (0x1U) #define AON_FCCU_FHFLTS0_1_STAT32_SHIFT (0U) /*! STAT32 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT32(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT32_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT32_MASK) #define AON_FCCU_FHFLTS0_1_STAT33_MASK (0x2U) #define AON_FCCU_FHFLTS0_1_STAT33_SHIFT (1U) /*! STAT33 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT33(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT33_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT33_MASK) #define AON_FCCU_FHFLTS0_1_STAT34_MASK (0x4U) #define AON_FCCU_FHFLTS0_1_STAT34_SHIFT (2U) /*! STAT34 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT34(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT34_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT34_MASK) #define AON_FCCU_FHFLTS0_1_STAT35_MASK (0x8U) #define AON_FCCU_FHFLTS0_1_STAT35_SHIFT (3U) /*! STAT35 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT35(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT35_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT35_MASK) #define AON_FCCU_FHFLTS0_1_STAT36_MASK (0x10U) #define AON_FCCU_FHFLTS0_1_STAT36_SHIFT (4U) /*! STAT36 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT36(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT36_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT36_MASK) #define AON_FCCU_FHFLTS0_1_STAT37_MASK (0x20U) #define AON_FCCU_FHFLTS0_1_STAT37_SHIFT (5U) /*! STAT37 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT37(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT37_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT37_MASK) #define AON_FCCU_FHFLTS0_1_STAT38_MASK (0x40U) #define AON_FCCU_FHFLTS0_1_STAT38_SHIFT (6U) /*! STAT38 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT38(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT38_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT38_MASK) #define AON_FCCU_FHFLTS0_1_STAT39_MASK (0x80U) #define AON_FCCU_FHFLTS0_1_STAT39_SHIFT (7U) /*! STAT39 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT39(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT39_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT39_MASK) #define AON_FCCU_FHFLTS0_1_STAT40_MASK (0x100U) #define AON_FCCU_FHFLTS0_1_STAT40_SHIFT (8U) /*! STAT40 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT40(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT40_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT40_MASK) #define AON_FCCU_FHFLTS0_1_STAT41_MASK (0x200U) #define AON_FCCU_FHFLTS0_1_STAT41_SHIFT (9U) /*! STAT41 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT41(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT41_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT41_MASK) #define AON_FCCU_FHFLTS0_1_STAT42_MASK (0x400U) #define AON_FCCU_FHFLTS0_1_STAT42_SHIFT (10U) /*! STAT42 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT42(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT42_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT42_MASK) #define AON_FCCU_FHFLTS0_1_STAT43_MASK (0x800U) #define AON_FCCU_FHFLTS0_1_STAT43_SHIFT (11U) /*! STAT43 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT43(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT43_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT43_MASK) #define AON_FCCU_FHFLTS0_1_STAT44_MASK (0x1000U) #define AON_FCCU_FHFLTS0_1_STAT44_SHIFT (12U) /*! STAT44 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT44(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT44_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT44_MASK) #define AON_FCCU_FHFLTS0_1_STAT45_MASK (0x2000U) #define AON_FCCU_FHFLTS0_1_STAT45_SHIFT (13U) /*! STAT45 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT45(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT45_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT45_MASK) #define AON_FCCU_FHFLTS0_1_STAT46_MASK (0x4000U) #define AON_FCCU_FHFLTS0_1_STAT46_SHIFT (14U) /*! STAT46 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT46(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT46_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT46_MASK) #define AON_FCCU_FHFLTS0_1_STAT47_MASK (0x8000U) #define AON_FCCU_FHFLTS0_1_STAT47_SHIFT (15U) /*! STAT47 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT47(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT47_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT47_MASK) #define AON_FCCU_FHFLTS0_1_STAT48_MASK (0x10000U) #define AON_FCCU_FHFLTS0_1_STAT48_SHIFT (16U) /*! STAT48 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT48(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT48_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT48_MASK) #define AON_FCCU_FHFLTS0_1_STAT49_MASK (0x20000U) #define AON_FCCU_FHFLTS0_1_STAT49_SHIFT (17U) /*! STAT49 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT49(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT49_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT49_MASK) #define AON_FCCU_FHFLTS0_1_STAT50_MASK (0x40000U) #define AON_FCCU_FHFLTS0_1_STAT50_SHIFT (18U) /*! STAT50 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT50(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT50_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT50_MASK) #define AON_FCCU_FHFLTS0_1_STAT51_MASK (0x80000U) #define AON_FCCU_FHFLTS0_1_STAT51_SHIFT (19U) /*! STAT51 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT51(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT51_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT51_MASK) #define AON_FCCU_FHFLTS0_1_STAT52_MASK (0x100000U) #define AON_FCCU_FHFLTS0_1_STAT52_SHIFT (20U) /*! STAT52 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT52(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT52_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT52_MASK) #define AON_FCCU_FHFLTS0_1_STAT53_MASK (0x200000U) #define AON_FCCU_FHFLTS0_1_STAT53_SHIFT (21U) /*! STAT53 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT53(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT53_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT53_MASK) #define AON_FCCU_FHFLTS0_1_STAT54_MASK (0x400000U) #define AON_FCCU_FHFLTS0_1_STAT54_SHIFT (22U) /*! STAT54 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT54(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT54_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT54_MASK) #define AON_FCCU_FHFLTS0_1_STAT55_MASK (0x800000U) #define AON_FCCU_FHFLTS0_1_STAT55_SHIFT (23U) /*! STAT55 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT55(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT55_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT55_MASK) #define AON_FCCU_FHFLTS0_1_STAT56_MASK (0x1000000U) #define AON_FCCU_FHFLTS0_1_STAT56_SHIFT (24U) /*! STAT56 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT56(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT56_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT56_MASK) #define AON_FCCU_FHFLTS0_1_STAT57_MASK (0x2000000U) #define AON_FCCU_FHFLTS0_1_STAT57_SHIFT (25U) /*! STAT57 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT57(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT57_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT57_MASK) #define AON_FCCU_FHFLTS0_1_STAT58_MASK (0x4000000U) #define AON_FCCU_FHFLTS0_1_STAT58_SHIFT (26U) /*! STAT58 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT58(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT58_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT58_MASK) #define AON_FCCU_FHFLTS0_1_STAT59_MASK (0x8000000U) #define AON_FCCU_FHFLTS0_1_STAT59_SHIFT (27U) /*! STAT59 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT59(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT59_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT59_MASK) #define AON_FCCU_FHFLTS0_1_STAT60_MASK (0x10000000U) #define AON_FCCU_FHFLTS0_1_STAT60_SHIFT (28U) /*! STAT60 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT60(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT60_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT60_MASK) #define AON_FCCU_FHFLTS0_1_STAT61_MASK (0x20000000U) #define AON_FCCU_FHFLTS0_1_STAT61_SHIFT (29U) /*! STAT61 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT61(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT61_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT61_MASK) #define AON_FCCU_FHFLTS0_1_STAT62_MASK (0x40000000U) #define AON_FCCU_FHFLTS0_1_STAT62_SHIFT (30U) /*! STAT62 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT62(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT62_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT62_MASK) #define AON_FCCU_FHFLTS0_1_STAT63_MASK (0x80000000U) #define AON_FCCU_FHFLTS0_1_STAT63_SHIFT (31U) /*! STAT63 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_1_STAT63(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_1_STAT63_SHIFT)) & AON_FCCU_FHFLTS0_1_STAT63_MASK) /*! @} */ /*! @name FHFLTS0_2 - Fault Status */ /*! @{ */ #define AON_FCCU_FHFLTS0_2_STAT64_MASK (0x1U) #define AON_FCCU_FHFLTS0_2_STAT64_SHIFT (0U) /*! STAT64 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT64(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT64_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT64_MASK) #define AON_FCCU_FHFLTS0_2_STAT65_MASK (0x2U) #define AON_FCCU_FHFLTS0_2_STAT65_SHIFT (1U) /*! STAT65 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT65(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT65_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT65_MASK) #define AON_FCCU_FHFLTS0_2_STAT66_MASK (0x4U) #define AON_FCCU_FHFLTS0_2_STAT66_SHIFT (2U) /*! STAT66 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT66(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT66_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT66_MASK) #define AON_FCCU_FHFLTS0_2_STAT67_MASK (0x8U) #define AON_FCCU_FHFLTS0_2_STAT67_SHIFT (3U) /*! STAT67 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT67(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT67_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT67_MASK) #define AON_FCCU_FHFLTS0_2_STAT68_MASK (0x10U) #define AON_FCCU_FHFLTS0_2_STAT68_SHIFT (4U) /*! STAT68 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT68(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT68_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT68_MASK) #define AON_FCCU_FHFLTS0_2_STAT69_MASK (0x20U) #define AON_FCCU_FHFLTS0_2_STAT69_SHIFT (5U) /*! STAT69 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT69(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT69_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT69_MASK) #define AON_FCCU_FHFLTS0_2_STAT70_MASK (0x40U) #define AON_FCCU_FHFLTS0_2_STAT70_SHIFT (6U) /*! STAT70 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT70(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT70_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT70_MASK) #define AON_FCCU_FHFLTS0_2_STAT71_MASK (0x80U) #define AON_FCCU_FHFLTS0_2_STAT71_SHIFT (7U) /*! STAT71 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT71(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT71_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT71_MASK) #define AON_FCCU_FHFLTS0_2_STAT72_MASK (0x100U) #define AON_FCCU_FHFLTS0_2_STAT72_SHIFT (8U) /*! STAT72 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT72(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT72_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT72_MASK) #define AON_FCCU_FHFLTS0_2_STAT73_MASK (0x200U) #define AON_FCCU_FHFLTS0_2_STAT73_SHIFT (9U) /*! STAT73 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT73(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT73_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT73_MASK) #define AON_FCCU_FHFLTS0_2_STAT74_MASK (0x400U) #define AON_FCCU_FHFLTS0_2_STAT74_SHIFT (10U) /*! STAT74 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT74(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT74_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT74_MASK) #define AON_FCCU_FHFLTS0_2_STAT75_MASK (0x800U) #define AON_FCCU_FHFLTS0_2_STAT75_SHIFT (11U) /*! STAT75 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT75(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT75_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT75_MASK) #define AON_FCCU_FHFLTS0_2_STAT76_MASK (0x1000U) #define AON_FCCU_FHFLTS0_2_STAT76_SHIFT (12U) /*! STAT76 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT76(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT76_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT76_MASK) #define AON_FCCU_FHFLTS0_2_STAT77_MASK (0x2000U) #define AON_FCCU_FHFLTS0_2_STAT77_SHIFT (13U) /*! STAT77 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT77(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT77_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT77_MASK) #define AON_FCCU_FHFLTS0_2_STAT78_MASK (0x4000U) #define AON_FCCU_FHFLTS0_2_STAT78_SHIFT (14U) /*! STAT78 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT78(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT78_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT78_MASK) #define AON_FCCU_FHFLTS0_2_STAT79_MASK (0x8000U) #define AON_FCCU_FHFLTS0_2_STAT79_SHIFT (15U) /*! STAT79 - Fault Status * 0b0..Not latched * 0b0..No effect * 0b1..Latched * 0b1..Deasserts (clear) */ #define AON_FCCU_FHFLTS0_2_STAT79(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTS0_2_STAT79_SHIFT)) & AON_FCCU_FHFLTS0_2_STAT79_MASK) /*! @} */ /*! @name FHFLTRKC0_0 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_0_RKNSEL0_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_0_RKNSEL0_SHIFT (0U) /*! RKNSEL0 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_0_RKNSEL0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_0_RKNSEL0_SHIFT)) & AON_FCCU_FHFLTRKC0_0_RKNSEL0_MASK) #define AON_FCCU_FHFLTRKC0_0_RKNSEL1_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_0_RKNSEL1_SHIFT (8U) /*! RKNSEL1 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_0_RKNSEL1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_0_RKNSEL1_SHIFT)) & AON_FCCU_FHFLTRKC0_0_RKNSEL1_MASK) #define AON_FCCU_FHFLTRKC0_0_RKNSEL2_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_0_RKNSEL2_SHIFT (16U) /*! RKNSEL2 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_0_RKNSEL2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_0_RKNSEL2_SHIFT)) & AON_FCCU_FHFLTRKC0_0_RKNSEL2_MASK) #define AON_FCCU_FHFLTRKC0_0_RKNSEL3_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_0_RKNSEL3_SHIFT (24U) /*! RKNSEL3 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_0_RKNSEL3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_0_RKNSEL3_SHIFT)) & AON_FCCU_FHFLTRKC0_0_RKNSEL3_MASK) /*! @} */ /*! @name FHFLTRKC0_1 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_1_RKNSEL4_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_1_RKNSEL4_SHIFT (0U) /*! RKNSEL4 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_1_RKNSEL4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_1_RKNSEL4_SHIFT)) & AON_FCCU_FHFLTRKC0_1_RKNSEL4_MASK) #define AON_FCCU_FHFLTRKC0_1_RKNSEL5_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_1_RKNSEL5_SHIFT (8U) /*! RKNSEL5 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_1_RKNSEL5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_1_RKNSEL5_SHIFT)) & AON_FCCU_FHFLTRKC0_1_RKNSEL5_MASK) #define AON_FCCU_FHFLTRKC0_1_RKNSEL6_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_1_RKNSEL6_SHIFT (16U) /*! RKNSEL6 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_1_RKNSEL6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_1_RKNSEL6_SHIFT)) & AON_FCCU_FHFLTRKC0_1_RKNSEL6_MASK) #define AON_FCCU_FHFLTRKC0_1_RKNSEL7_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_1_RKNSEL7_SHIFT (24U) /*! RKNSEL7 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_1_RKNSEL7(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_1_RKNSEL7_SHIFT)) & AON_FCCU_FHFLTRKC0_1_RKNSEL7_MASK) /*! @} */ /*! @name FHFLTRKC0_2 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_2_RKNSEL8_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_2_RKNSEL8_SHIFT (0U) /*! RKNSEL8 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_2_RKNSEL8(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_2_RKNSEL8_SHIFT)) & AON_FCCU_FHFLTRKC0_2_RKNSEL8_MASK) #define AON_FCCU_FHFLTRKC0_2_RKNSEL9_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_2_RKNSEL9_SHIFT (8U) /*! RKNSEL9 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_2_RKNSEL9(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_2_RKNSEL9_SHIFT)) & AON_FCCU_FHFLTRKC0_2_RKNSEL9_MASK) #define AON_FCCU_FHFLTRKC0_2_RKNSEL10_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_2_RKNSEL10_SHIFT (16U) /*! RKNSEL10 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_2_RKNSEL10(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_2_RKNSEL10_SHIFT)) & AON_FCCU_FHFLTRKC0_2_RKNSEL10_MASK) #define AON_FCCU_FHFLTRKC0_2_RKNSEL11_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_2_RKNSEL11_SHIFT (24U) /*! RKNSEL11 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_2_RKNSEL11(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_2_RKNSEL11_SHIFT)) & AON_FCCU_FHFLTRKC0_2_RKNSEL11_MASK) /*! @} */ /*! @name FHFLTRKC0_3 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_3_RKNSEL12_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_3_RKNSEL12_SHIFT (0U) /*! RKNSEL12 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_3_RKNSEL12(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_3_RKNSEL12_SHIFT)) & AON_FCCU_FHFLTRKC0_3_RKNSEL12_MASK) #define AON_FCCU_FHFLTRKC0_3_RKNSEL13_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_3_RKNSEL13_SHIFT (8U) /*! RKNSEL13 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_3_RKNSEL13(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_3_RKNSEL13_SHIFT)) & AON_FCCU_FHFLTRKC0_3_RKNSEL13_MASK) #define AON_FCCU_FHFLTRKC0_3_RKNSEL14_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_3_RKNSEL14_SHIFT (16U) /*! RKNSEL14 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_3_RKNSEL14(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_3_RKNSEL14_SHIFT)) & AON_FCCU_FHFLTRKC0_3_RKNSEL14_MASK) #define AON_FCCU_FHFLTRKC0_3_RKNSEL15_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_3_RKNSEL15_SHIFT (24U) /*! RKNSEL15 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_3_RKNSEL15(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_3_RKNSEL15_SHIFT)) & AON_FCCU_FHFLTRKC0_3_RKNSEL15_MASK) /*! @} */ /*! @name FHFLTRKC0_4 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_4_RKNSEL16_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_4_RKNSEL16_SHIFT (0U) /*! RKNSEL16 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_4_RKNSEL16(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_4_RKNSEL16_SHIFT)) & AON_FCCU_FHFLTRKC0_4_RKNSEL16_MASK) #define AON_FCCU_FHFLTRKC0_4_RKNSEL17_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_4_RKNSEL17_SHIFT (8U) /*! RKNSEL17 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_4_RKNSEL17(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_4_RKNSEL17_SHIFT)) & AON_FCCU_FHFLTRKC0_4_RKNSEL17_MASK) #define AON_FCCU_FHFLTRKC0_4_RKNSEL18_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_4_RKNSEL18_SHIFT (16U) /*! RKNSEL18 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_4_RKNSEL18(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_4_RKNSEL18_SHIFT)) & AON_FCCU_FHFLTRKC0_4_RKNSEL18_MASK) #define AON_FCCU_FHFLTRKC0_4_RKNSEL19_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_4_RKNSEL19_SHIFT (24U) /*! RKNSEL19 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_4_RKNSEL19(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_4_RKNSEL19_SHIFT)) & AON_FCCU_FHFLTRKC0_4_RKNSEL19_MASK) /*! @} */ /*! @name FHFLTRKC0_5 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_5_RKNSEL20_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_5_RKNSEL20_SHIFT (0U) /*! RKNSEL20 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_5_RKNSEL20(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_5_RKNSEL20_SHIFT)) & AON_FCCU_FHFLTRKC0_5_RKNSEL20_MASK) #define AON_FCCU_FHFLTRKC0_5_RKNSEL21_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_5_RKNSEL21_SHIFT (8U) /*! RKNSEL21 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_5_RKNSEL21(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_5_RKNSEL21_SHIFT)) & AON_FCCU_FHFLTRKC0_5_RKNSEL21_MASK) #define AON_FCCU_FHFLTRKC0_5_RKNSEL22_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_5_RKNSEL22_SHIFT (16U) /*! RKNSEL22 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_5_RKNSEL22(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_5_RKNSEL22_SHIFT)) & AON_FCCU_FHFLTRKC0_5_RKNSEL22_MASK) #define AON_FCCU_FHFLTRKC0_5_RKNSEL23_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_5_RKNSEL23_SHIFT (24U) /*! RKNSEL23 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_5_RKNSEL23(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_5_RKNSEL23_SHIFT)) & AON_FCCU_FHFLTRKC0_5_RKNSEL23_MASK) /*! @} */ /*! @name FHFLTRKC0_6 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_6_RKNSEL24_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_6_RKNSEL24_SHIFT (0U) /*! RKNSEL24 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_6_RKNSEL24(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_6_RKNSEL24_SHIFT)) & AON_FCCU_FHFLTRKC0_6_RKNSEL24_MASK) #define AON_FCCU_FHFLTRKC0_6_RKNSEL25_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_6_RKNSEL25_SHIFT (8U) /*! RKNSEL25 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_6_RKNSEL25(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_6_RKNSEL25_SHIFT)) & AON_FCCU_FHFLTRKC0_6_RKNSEL25_MASK) #define AON_FCCU_FHFLTRKC0_6_RKNSEL26_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_6_RKNSEL26_SHIFT (16U) /*! RKNSEL26 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_6_RKNSEL26(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_6_RKNSEL26_SHIFT)) & AON_FCCU_FHFLTRKC0_6_RKNSEL26_MASK) #define AON_FCCU_FHFLTRKC0_6_RKNSEL27_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_6_RKNSEL27_SHIFT (24U) /*! RKNSEL27 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_6_RKNSEL27(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_6_RKNSEL27_SHIFT)) & AON_FCCU_FHFLTRKC0_6_RKNSEL27_MASK) /*! @} */ /*! @name FHFLTRKC0_7 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_7_RKNSEL28_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_7_RKNSEL28_SHIFT (0U) /*! RKNSEL28 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_7_RKNSEL28(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_7_RKNSEL28_SHIFT)) & AON_FCCU_FHFLTRKC0_7_RKNSEL28_MASK) #define AON_FCCU_FHFLTRKC0_7_RKNSEL29_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_7_RKNSEL29_SHIFT (8U) /*! RKNSEL29 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_7_RKNSEL29(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_7_RKNSEL29_SHIFT)) & AON_FCCU_FHFLTRKC0_7_RKNSEL29_MASK) #define AON_FCCU_FHFLTRKC0_7_RKNSEL30_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_7_RKNSEL30_SHIFT (16U) /*! RKNSEL30 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_7_RKNSEL30(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_7_RKNSEL30_SHIFT)) & AON_FCCU_FHFLTRKC0_7_RKNSEL30_MASK) #define AON_FCCU_FHFLTRKC0_7_RKNSEL31_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_7_RKNSEL31_SHIFT (24U) /*! RKNSEL31 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_7_RKNSEL31(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_7_RKNSEL31_SHIFT)) & AON_FCCU_FHFLTRKC0_7_RKNSEL31_MASK) /*! @} */ /*! @name FHFLTRKC0_8 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_8_RKNSEL32_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_8_RKNSEL32_SHIFT (0U) /*! RKNSEL32 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_8_RKNSEL32(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_8_RKNSEL32_SHIFT)) & AON_FCCU_FHFLTRKC0_8_RKNSEL32_MASK) #define AON_FCCU_FHFLTRKC0_8_RKNSEL33_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_8_RKNSEL33_SHIFT (8U) /*! RKNSEL33 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_8_RKNSEL33(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_8_RKNSEL33_SHIFT)) & AON_FCCU_FHFLTRKC0_8_RKNSEL33_MASK) #define AON_FCCU_FHFLTRKC0_8_RKNSEL34_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_8_RKNSEL34_SHIFT (16U) /*! RKNSEL34 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_8_RKNSEL34(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_8_RKNSEL34_SHIFT)) & AON_FCCU_FHFLTRKC0_8_RKNSEL34_MASK) #define AON_FCCU_FHFLTRKC0_8_RKNSEL35_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_8_RKNSEL35_SHIFT (24U) /*! RKNSEL35 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_8_RKNSEL35(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_8_RKNSEL35_SHIFT)) & AON_FCCU_FHFLTRKC0_8_RKNSEL35_MASK) /*! @} */ /*! @name FHFLTRKC0_9 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_9_RKNSEL36_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_9_RKNSEL36_SHIFT (0U) /*! RKNSEL36 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_9_RKNSEL36(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_9_RKNSEL36_SHIFT)) & AON_FCCU_FHFLTRKC0_9_RKNSEL36_MASK) #define AON_FCCU_FHFLTRKC0_9_RKNSEL37_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_9_RKNSEL37_SHIFT (8U) /*! RKNSEL37 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_9_RKNSEL37(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_9_RKNSEL37_SHIFT)) & AON_FCCU_FHFLTRKC0_9_RKNSEL37_MASK) #define AON_FCCU_FHFLTRKC0_9_RKNSEL38_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_9_RKNSEL38_SHIFT (16U) /*! RKNSEL38 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_9_RKNSEL38(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_9_RKNSEL38_SHIFT)) & AON_FCCU_FHFLTRKC0_9_RKNSEL38_MASK) #define AON_FCCU_FHFLTRKC0_9_RKNSEL39_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_9_RKNSEL39_SHIFT (24U) /*! RKNSEL39 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_9_RKNSEL39(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_9_RKNSEL39_SHIFT)) & AON_FCCU_FHFLTRKC0_9_RKNSEL39_MASK) /*! @} */ /*! @name FHFLTRKC0_10 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_10_RKNSEL40_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_10_RKNSEL40_SHIFT (0U) /*! RKNSEL40 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_10_RKNSEL40(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_10_RKNSEL40_SHIFT)) & AON_FCCU_FHFLTRKC0_10_RKNSEL40_MASK) #define AON_FCCU_FHFLTRKC0_10_RKNSEL41_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_10_RKNSEL41_SHIFT (8U) /*! RKNSEL41 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_10_RKNSEL41(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_10_RKNSEL41_SHIFT)) & AON_FCCU_FHFLTRKC0_10_RKNSEL41_MASK) #define AON_FCCU_FHFLTRKC0_10_RKNSEL42_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_10_RKNSEL42_SHIFT (16U) /*! RKNSEL42 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_10_RKNSEL42(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_10_RKNSEL42_SHIFT)) & AON_FCCU_FHFLTRKC0_10_RKNSEL42_MASK) #define AON_FCCU_FHFLTRKC0_10_RKNSEL43_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_10_RKNSEL43_SHIFT (24U) /*! RKNSEL43 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_10_RKNSEL43(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_10_RKNSEL43_SHIFT)) & AON_FCCU_FHFLTRKC0_10_RKNSEL43_MASK) /*! @} */ /*! @name FHFLTRKC0_11 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_11_RKNSEL44_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_11_RKNSEL44_SHIFT (0U) /*! RKNSEL44 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_11_RKNSEL44(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_11_RKNSEL44_SHIFT)) & AON_FCCU_FHFLTRKC0_11_RKNSEL44_MASK) #define AON_FCCU_FHFLTRKC0_11_RKNSEL45_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_11_RKNSEL45_SHIFT (8U) /*! RKNSEL45 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_11_RKNSEL45(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_11_RKNSEL45_SHIFT)) & AON_FCCU_FHFLTRKC0_11_RKNSEL45_MASK) #define AON_FCCU_FHFLTRKC0_11_RKNSEL46_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_11_RKNSEL46_SHIFT (16U) /*! RKNSEL46 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_11_RKNSEL46(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_11_RKNSEL46_SHIFT)) & AON_FCCU_FHFLTRKC0_11_RKNSEL46_MASK) #define AON_FCCU_FHFLTRKC0_11_RKNSEL47_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_11_RKNSEL47_SHIFT (24U) /*! RKNSEL47 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_11_RKNSEL47(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_11_RKNSEL47_SHIFT)) & AON_FCCU_FHFLTRKC0_11_RKNSEL47_MASK) /*! @} */ /*! @name FHFLTRKC0_12 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_12_RKNSEL48_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_12_RKNSEL48_SHIFT (0U) /*! RKNSEL48 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_12_RKNSEL48(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_12_RKNSEL48_SHIFT)) & AON_FCCU_FHFLTRKC0_12_RKNSEL48_MASK) #define AON_FCCU_FHFLTRKC0_12_RKNSEL49_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_12_RKNSEL49_SHIFT (8U) /*! RKNSEL49 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_12_RKNSEL49(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_12_RKNSEL49_SHIFT)) & AON_FCCU_FHFLTRKC0_12_RKNSEL49_MASK) #define AON_FCCU_FHFLTRKC0_12_RKNSEL50_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_12_RKNSEL50_SHIFT (16U) /*! RKNSEL50 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_12_RKNSEL50(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_12_RKNSEL50_SHIFT)) & AON_FCCU_FHFLTRKC0_12_RKNSEL50_MASK) #define AON_FCCU_FHFLTRKC0_12_RKNSEL51_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_12_RKNSEL51_SHIFT (24U) /*! RKNSEL51 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_12_RKNSEL51(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_12_RKNSEL51_SHIFT)) & AON_FCCU_FHFLTRKC0_12_RKNSEL51_MASK) /*! @} */ /*! @name FHFLTRKC0_13 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_13_RKNSEL52_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_13_RKNSEL52_SHIFT (0U) /*! RKNSEL52 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_13_RKNSEL52(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_13_RKNSEL52_SHIFT)) & AON_FCCU_FHFLTRKC0_13_RKNSEL52_MASK) #define AON_FCCU_FHFLTRKC0_13_RKNSEL53_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_13_RKNSEL53_SHIFT (8U) /*! RKNSEL53 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_13_RKNSEL53(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_13_RKNSEL53_SHIFT)) & AON_FCCU_FHFLTRKC0_13_RKNSEL53_MASK) #define AON_FCCU_FHFLTRKC0_13_RKNSEL54_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_13_RKNSEL54_SHIFT (16U) /*! RKNSEL54 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_13_RKNSEL54(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_13_RKNSEL54_SHIFT)) & AON_FCCU_FHFLTRKC0_13_RKNSEL54_MASK) #define AON_FCCU_FHFLTRKC0_13_RKNSEL55_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_13_RKNSEL55_SHIFT (24U) /*! RKNSEL55 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_13_RKNSEL55(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_13_RKNSEL55_SHIFT)) & AON_FCCU_FHFLTRKC0_13_RKNSEL55_MASK) /*! @} */ /*! @name FHFLTRKC0_14 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_14_RKNSEL56_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_14_RKNSEL56_SHIFT (0U) /*! RKNSEL56 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_14_RKNSEL56(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_14_RKNSEL56_SHIFT)) & AON_FCCU_FHFLTRKC0_14_RKNSEL56_MASK) #define AON_FCCU_FHFLTRKC0_14_RKNSEL57_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_14_RKNSEL57_SHIFT (8U) /*! RKNSEL57 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_14_RKNSEL57(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_14_RKNSEL57_SHIFT)) & AON_FCCU_FHFLTRKC0_14_RKNSEL57_MASK) #define AON_FCCU_FHFLTRKC0_14_RKNSEL58_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_14_RKNSEL58_SHIFT (16U) /*! RKNSEL58 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_14_RKNSEL58(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_14_RKNSEL58_SHIFT)) & AON_FCCU_FHFLTRKC0_14_RKNSEL58_MASK) #define AON_FCCU_FHFLTRKC0_14_RKNSEL59_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_14_RKNSEL59_SHIFT (24U) /*! RKNSEL59 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_14_RKNSEL59(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_14_RKNSEL59_SHIFT)) & AON_FCCU_FHFLTRKC0_14_RKNSEL59_MASK) /*! @} */ /*! @name FHFLTRKC0_15 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_15_RKNSEL60_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_15_RKNSEL60_SHIFT (0U) /*! RKNSEL60 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_15_RKNSEL60(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_15_RKNSEL60_SHIFT)) & AON_FCCU_FHFLTRKC0_15_RKNSEL60_MASK) #define AON_FCCU_FHFLTRKC0_15_RKNSEL61_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_15_RKNSEL61_SHIFT (8U) /*! RKNSEL61 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_15_RKNSEL61(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_15_RKNSEL61_SHIFT)) & AON_FCCU_FHFLTRKC0_15_RKNSEL61_MASK) #define AON_FCCU_FHFLTRKC0_15_RKNSEL62_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_15_RKNSEL62_SHIFT (16U) /*! RKNSEL62 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_15_RKNSEL62(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_15_RKNSEL62_SHIFT)) & AON_FCCU_FHFLTRKC0_15_RKNSEL62_MASK) #define AON_FCCU_FHFLTRKC0_15_RKNSEL63_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_15_RKNSEL63_SHIFT (24U) /*! RKNSEL63 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_15_RKNSEL63(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_15_RKNSEL63_SHIFT)) & AON_FCCU_FHFLTRKC0_15_RKNSEL63_MASK) /*! @} */ /*! @name FHFLTRKC0_16 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_16_RKNSEL64_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_16_RKNSEL64_SHIFT (0U) /*! RKNSEL64 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_16_RKNSEL64(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_16_RKNSEL64_SHIFT)) & AON_FCCU_FHFLTRKC0_16_RKNSEL64_MASK) #define AON_FCCU_FHFLTRKC0_16_RKNSEL65_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_16_RKNSEL65_SHIFT (8U) /*! RKNSEL65 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_16_RKNSEL65(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_16_RKNSEL65_SHIFT)) & AON_FCCU_FHFLTRKC0_16_RKNSEL65_MASK) #define AON_FCCU_FHFLTRKC0_16_RKNSEL66_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_16_RKNSEL66_SHIFT (16U) /*! RKNSEL66 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_16_RKNSEL66(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_16_RKNSEL66_SHIFT)) & AON_FCCU_FHFLTRKC0_16_RKNSEL66_MASK) #define AON_FCCU_FHFLTRKC0_16_RKNSEL67_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_16_RKNSEL67_SHIFT (24U) /*! RKNSEL67 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_16_RKNSEL67(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_16_RKNSEL67_SHIFT)) & AON_FCCU_FHFLTRKC0_16_RKNSEL67_MASK) /*! @} */ /*! @name FHFLTRKC0_17 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_17_RKNSEL68_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_17_RKNSEL68_SHIFT (0U) /*! RKNSEL68 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_17_RKNSEL68(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_17_RKNSEL68_SHIFT)) & AON_FCCU_FHFLTRKC0_17_RKNSEL68_MASK) #define AON_FCCU_FHFLTRKC0_17_RKNSEL69_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_17_RKNSEL69_SHIFT (8U) /*! RKNSEL69 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_17_RKNSEL69(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_17_RKNSEL69_SHIFT)) & AON_FCCU_FHFLTRKC0_17_RKNSEL69_MASK) #define AON_FCCU_FHFLTRKC0_17_RKNSEL70_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_17_RKNSEL70_SHIFT (16U) /*! RKNSEL70 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_17_RKNSEL70(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_17_RKNSEL70_SHIFT)) & AON_FCCU_FHFLTRKC0_17_RKNSEL70_MASK) #define AON_FCCU_FHFLTRKC0_17_RKNSEL71_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_17_RKNSEL71_SHIFT (24U) /*! RKNSEL71 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_17_RKNSEL71(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_17_RKNSEL71_SHIFT)) & AON_FCCU_FHFLTRKC0_17_RKNSEL71_MASK) /*! @} */ /*! @name FHFLTRKC0_18 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_18_RKNSEL72_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_18_RKNSEL72_SHIFT (0U) /*! RKNSEL72 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_18_RKNSEL72(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_18_RKNSEL72_SHIFT)) & AON_FCCU_FHFLTRKC0_18_RKNSEL72_MASK) #define AON_FCCU_FHFLTRKC0_18_RKNSEL73_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_18_RKNSEL73_SHIFT (8U) /*! RKNSEL73 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_18_RKNSEL73(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_18_RKNSEL73_SHIFT)) & AON_FCCU_FHFLTRKC0_18_RKNSEL73_MASK) #define AON_FCCU_FHFLTRKC0_18_RKNSEL74_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_18_RKNSEL74_SHIFT (16U) /*! RKNSEL74 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_18_RKNSEL74(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_18_RKNSEL74_SHIFT)) & AON_FCCU_FHFLTRKC0_18_RKNSEL74_MASK) #define AON_FCCU_FHFLTRKC0_18_RKNSEL75_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_18_RKNSEL75_SHIFT (24U) /*! RKNSEL75 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_18_RKNSEL75(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_18_RKNSEL75_SHIFT)) & AON_FCCU_FHFLTRKC0_18_RKNSEL75_MASK) /*! @} */ /*! @name FHFLTRKC0_19 - Fault Reaction Set Configuration */ /*! @{ */ #define AON_FCCU_FHFLTRKC0_19_RKNSEL76_MASK (0x7U) #define AON_FCCU_FHFLTRKC0_19_RKNSEL76_SHIFT (0U) /*! RKNSEL76 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_19_RKNSEL76(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_19_RKNSEL76_SHIFT)) & AON_FCCU_FHFLTRKC0_19_RKNSEL76_MASK) #define AON_FCCU_FHFLTRKC0_19_RKNSEL77_MASK (0x700U) #define AON_FCCU_FHFLTRKC0_19_RKNSEL77_SHIFT (8U) /*! RKNSEL77 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_19_RKNSEL77(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_19_RKNSEL77_SHIFT)) & AON_FCCU_FHFLTRKC0_19_RKNSEL77_MASK) #define AON_FCCU_FHFLTRKC0_19_RKNSEL78_MASK (0x70000U) #define AON_FCCU_FHFLTRKC0_19_RKNSEL78_SHIFT (16U) /*! RKNSEL78 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_19_RKNSEL78(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_19_RKNSEL78_SHIFT)) & AON_FCCU_FHFLTRKC0_19_RKNSEL78_MASK) #define AON_FCCU_FHFLTRKC0_19_RKNSEL79_MASK (0x7000000U) #define AON_FCCU_FHFLTRKC0_19_RKNSEL79_SHIFT (24U) /*! RKNSEL79 - Reaction Selection */ #define AON_FCCU_FHFLTRKC0_19_RKNSEL79(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHFLTRKC0_19_RKNSEL79_SHIFT)) & AON_FCCU_FHFLTRKC0_19_RKNSEL79_MASK) /*! @} */ /*! @name FHIMRKC0_00 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_00_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_00_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_00_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_00_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_00_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_00_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_00_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_00_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_00_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_00_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_00_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_00_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_00_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_00_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_00_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_00_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_00_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_00_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_00_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_00_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_00_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_00_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_00_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_00_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_00_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_00_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_00_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_00_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_00_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_00 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_00_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_00_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_00_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_00_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_00_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_00_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_00_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_00_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_00_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_00_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_00_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_00_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_00_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_00_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_00_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_00_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_00_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_00_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_00_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_00_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_00_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_00_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_00_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_00_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_00_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_00_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_00_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_00_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_00_RKNEN6_MASK) /*! @} */ /*! @name FHIMRKC0_10 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_10_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_10_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_10_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_10_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_10_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_10_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_10_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_10_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_10_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_10_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_10_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_10_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_10_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_10_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_10_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_10_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_10_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_10_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_10_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_10_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_10_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_10_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_10_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_10_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_10_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_10_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_10_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_10_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_10_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_10 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_10_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_10_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_10_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_10_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_10_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_10_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_10_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_10_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_10_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_10_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_10_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_10_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_10_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_10_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_10_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_10_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_10_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_10_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_10_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_10_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_10_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_10_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_10_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_10_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_10_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_10_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_10_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_10_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_10_RKNEN6_MASK) /*! @} */ /*! @name FHIMRKC0_20 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_20_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_20_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_20_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_20_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_20_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_20_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_20_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_20_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_20_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_20_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_20_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_20_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_20_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_20_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_20_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_20_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_20_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_20_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_20_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_20_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_20_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_20_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_20_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_20_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_20_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_20_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_20_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_20_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_20_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_20 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_20_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_20_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_20_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_20_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_20_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_20_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_20_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_20_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_20_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_20_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_20_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_20_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_20_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_20_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_20_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_20_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_20_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_20_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_20_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_20_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_20_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_20_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_20_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_20_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_20_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_20_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_20_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_20_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_20_RKNEN6_MASK) /*! @} */ /*! @name FHIMRKC0_30 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_30_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_30_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_30_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_30_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_30_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_30_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_30_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_30_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_30_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_30_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_30_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_30_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_30_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_30_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_30_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_30_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_30_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_30_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_30_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_30_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_30_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_30_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_30_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_30_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_30_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_30_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_30_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_30_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_30_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_30 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_30_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_30_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_30_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_30_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_30_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_30_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_30_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_30_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_30_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_30_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_30_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_30_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_30_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_30_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_30_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_30_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_30_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_30_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_30_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_30_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_30_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_30_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_30_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_30_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_30_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_30_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_30_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_30_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_30_RKNEN6_MASK) /*! @} */ /*! @name FHIMRKC0_40 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_40_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_40_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_40_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_40_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_40_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_40_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_40_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_40_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_40_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_40_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_40_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_40_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_40_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_40_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_40_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_40_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_40_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_40_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_40_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_40_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_40_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_40_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_40_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_40_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_40_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_40_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_40_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_40_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_40_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_40 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_40_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_40_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_40_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_40_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_40_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_40_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_40_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_40_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_40_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_40_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_40_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_40_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_40_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_40_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_40_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_40_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_40_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_40_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_40_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_40_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_40_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_40_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_40_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_40_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_40_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_40_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_40_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_40_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_40_RKNEN6_MASK) /*! @} */ /*! @name FHIMRKC0_50 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_50_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_50_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_50_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_50_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_50_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_50_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_50_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_50_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_50_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_50_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_50_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_50_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_50_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_50_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_50_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_50_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_50_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_50_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_50_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_50_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_50_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_50_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_50_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_50_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_50_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_50_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_50_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_50_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_50_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_50 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_50_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_50_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_50_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_50_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_50_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_50_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_50_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_50_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_50_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_50_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_50_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_50_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_50_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_50_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_50_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_50_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_50_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_50_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_50_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_50_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_50_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_50_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_50_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_50_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_50_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_50_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_50_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_50_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_50_RKNEN6_MASK) /*! @} */ /*! @name FHIMRKC0_60 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_60_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_60_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_60_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_60_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_60_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_60_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_60_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_60_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_60_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_60_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_60_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_60_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_60_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_60_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_60_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_60_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_60_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_60_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_60_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_60_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_60_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_60_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_60_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_60_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_60_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_60_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_60_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_60_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_60_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_60 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_60_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_60_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_60_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_60_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_60_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_60_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_60_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_60_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_60_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_60_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_60_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_60_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_60_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_60_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_60_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_60_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_60_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_60_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_60_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_60_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_60_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_60_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_60_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_60_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_60_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_60_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_60_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_60_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_60_RKNEN6_MASK) /*! @} */ /*! @name FHIMRKC0_70 - Immediate Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHIMRKC0_70_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHIMRKC0_70_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_EOUTEN0_SHIFT)) & AON_FCCU_FHIMRKC0_70_EOUTEN0_MASK) #define AON_FCCU_FHIMRKC0_70_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHIMRKC0_70_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_EOUTEN1_SHIFT)) & AON_FCCU_FHIMRKC0_70_EOUTEN1_MASK) #define AON_FCCU_FHIMRKC0_70_RKNEN0_MASK (0x4U) #define AON_FCCU_FHIMRKC0_70_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_RKNEN0_SHIFT)) & AON_FCCU_FHIMRKC0_70_RKNEN0_MASK) #define AON_FCCU_FHIMRKC0_70_RKNEN1_MASK (0x8U) #define AON_FCCU_FHIMRKC0_70_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_RKNEN1_SHIFT)) & AON_FCCU_FHIMRKC0_70_RKNEN1_MASK) #define AON_FCCU_FHIMRKC0_70_RKNEN2_MASK (0x10U) #define AON_FCCU_FHIMRKC0_70_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_RKNEN2_SHIFT)) & AON_FCCU_FHIMRKC0_70_RKNEN2_MASK) #define AON_FCCU_FHIMRKC0_70_RKNEN3_MASK (0x20U) #define AON_FCCU_FHIMRKC0_70_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_RKNEN3_SHIFT)) & AON_FCCU_FHIMRKC0_70_RKNEN3_MASK) #define AON_FCCU_FHIMRKC0_70_RKNEN4_MASK (0x40U) #define AON_FCCU_FHIMRKC0_70_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_RKNEN4_SHIFT)) & AON_FCCU_FHIMRKC0_70_RKNEN4_MASK) #define AON_FCCU_FHIMRKC0_70_RKNEN5_MASK (0x80U) #define AON_FCCU_FHIMRKC0_70_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_RKNEN5_SHIFT)) & AON_FCCU_FHIMRKC0_70_RKNEN5_MASK) #define AON_FCCU_FHIMRKC0_70_RKNEN6_MASK (0x100U) #define AON_FCCU_FHIMRKC0_70_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHIMRKC0_70_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHIMRKC0_70_RKNEN6_SHIFT)) & AON_FCCU_FHIMRKC0_70_RKNEN6_MASK) /*! @} */ /*! @name FHDLRKC0_70 - Delayed Reaction Configuration */ /*! @{ */ #define AON_FCCU_FHDLRKC0_70_EOUTEN0_MASK (0x1U) #define AON_FCCU_FHDLRKC0_70_EOUTEN0_SHIFT (0U) /*! EOUTEN0 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_EOUTEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_EOUTEN0_SHIFT)) & AON_FCCU_FHDLRKC0_70_EOUTEN0_MASK) #define AON_FCCU_FHDLRKC0_70_EOUTEN1_MASK (0x2U) #define AON_FCCU_FHDLRKC0_70_EOUTEN1_SHIFT (1U) /*! EOUTEN1 - EOUT Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_EOUTEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_EOUTEN1_SHIFT)) & AON_FCCU_FHDLRKC0_70_EOUTEN1_MASK) #define AON_FCCU_FHDLRKC0_70_RKNEN0_MASK (0x4U) #define AON_FCCU_FHDLRKC0_70_RKNEN0_SHIFT (2U) /*! RKNEN0 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_RKNEN0_SHIFT)) & AON_FCCU_FHDLRKC0_70_RKNEN0_MASK) #define AON_FCCU_FHDLRKC0_70_RKNEN1_MASK (0x8U) #define AON_FCCU_FHDLRKC0_70_RKNEN1_SHIFT (3U) /*! RKNEN1 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_RKNEN1_SHIFT)) & AON_FCCU_FHDLRKC0_70_RKNEN1_MASK) #define AON_FCCU_FHDLRKC0_70_RKNEN2_MASK (0x10U) #define AON_FCCU_FHDLRKC0_70_RKNEN2_SHIFT (4U) /*! RKNEN2 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_RKNEN2_SHIFT)) & AON_FCCU_FHDLRKC0_70_RKNEN2_MASK) #define AON_FCCU_FHDLRKC0_70_RKNEN3_MASK (0x20U) #define AON_FCCU_FHDLRKC0_70_RKNEN3_SHIFT (5U) /*! RKNEN3 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_RKNEN3_SHIFT)) & AON_FCCU_FHDLRKC0_70_RKNEN3_MASK) #define AON_FCCU_FHDLRKC0_70_RKNEN4_MASK (0x40U) #define AON_FCCU_FHDLRKC0_70_RKNEN4_SHIFT (6U) /*! RKNEN4 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_RKNEN4_SHIFT)) & AON_FCCU_FHDLRKC0_70_RKNEN4_MASK) #define AON_FCCU_FHDLRKC0_70_RKNEN5_MASK (0x80U) #define AON_FCCU_FHDLRKC0_70_RKNEN5_SHIFT (7U) /*! RKNEN5 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_RKNEN5_SHIFT)) & AON_FCCU_FHDLRKC0_70_RKNEN5_MASK) #define AON_FCCU_FHDLRKC0_70_RKNEN6_MASK (0x100U) #define AON_FCCU_FHDLRKC0_70_RKNEN6_SHIFT (8U) /*! RKNEN6 - Reaction Line Enable * 0b0..Disables * 0b1..Enables */ #define AON_FCCU_FHDLRKC0_70_RKNEN6(x) (((uint32_t)(((uint32_t)(x)) << AON_FCCU_FHDLRKC0_70_RKNEN6_SHIFT)) & AON_FCCU_FHDLRKC0_70_RKNEN6_MASK) /*! @} */ /*! * @} */ /* end of group AON_FCCU_Register_Masks */ /* AON_FCCU - Peripheral instance base addresses */ /** Peripheral AON__FCCU base address */ #define AON__FCCU_BASE (0x44570000u) /** Peripheral AON__FCCU base pointer */ #define AON__FCCU ((AON_FCCU_Type *)AON__FCCU_BASE) /** Array initializer of AON_FCCU peripheral base addresses */ #define AON_FCCU_BASE_ADDRS { AON__FCCU_BASE } /** Array initializer of AON_FCCU peripheral base pointers */ #define AON_FCCU_BASE_PTRS { AON__FCCU } /*! * @} */ /* end of group AON_FCCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_INTM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_INTM_Peripheral_Access_Layer AON_INTM Peripheral Access Layer * @{ */ /** AON_INTM - Register Layout Typedef */ typedef struct { __IO uint32_t INTM_MM; /**< Monitor Mode, offset: 0x0 */ __O uint32_t INTM_IACK; /**< Interrupt Acknowledge, offset: 0x4 */ struct { /* offset: 0x8, array step: 0x10 */ __IO uint32_t INTM_IRQSEL; /**< Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3, array offset: 0x8, array step: 0x10 */ __IO uint32_t INTM_LATENCY; /**< Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3, array offset: 0xC, array step: 0x10 */ __I uint32_t INTM_TIMER; /**< Timer for Monitor 0..Timer for Monitor 3, array offset: 0x10, array step: 0x10 */ __I uint32_t INTM_STATUS; /**< Status for Monitor 0..Status for Monitor 3, array offset: 0x14, array step: 0x10 */ } MON[4]; } AON_INTM_Type; /* ---------------------------------------------------------------------------- -- AON_INTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_INTM_Register_Masks AON_INTM Register Masks * @{ */ /*! @name INTM_MM - Monitor Mode */ /*! @{ */ #define AON_INTM_INTM_MM_MM_MASK (0x1U) #define AON_INTM_INTM_MM_MM_SHIFT (0U) /*! MM - Monitor Mode * 0b1..Enable * 0b0..Disable */ #define AON_INTM_INTM_MM_MM(x) (((uint32_t)(((uint32_t)(x)) << AON_INTM_INTM_MM_MM_SHIFT)) & AON_INTM_INTM_MM_MM_MASK) /*! @} */ /*! @name INTM_IACK - Interrupt Acknowledge */ /*! @{ */ #define AON_INTM_INTM_IACK_IRQ_MASK (0x3FFU) #define AON_INTM_INTM_IACK_IRQ_SHIFT (0U) /*! IRQ - Interrupt Request */ #define AON_INTM_INTM_IACK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AON_INTM_INTM_IACK_IRQ_SHIFT)) & AON_INTM_INTM_IACK_IRQ_MASK) /*! @} */ /*! @name INTM_IRQSEL - Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3 */ /*! @{ */ #define AON_INTM_INTM_IRQSEL_IRQ_MASK (0x3FFU) #define AON_INTM_INTM_IRQSEL_IRQ_SHIFT (0U) /*! IRQ - Interrupt Request */ #define AON_INTM_INTM_IRQSEL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AON_INTM_INTM_IRQSEL_IRQ_SHIFT)) & AON_INTM_INTM_IRQSEL_IRQ_MASK) /*! @} */ /* The count of AON_INTM_INTM_IRQSEL */ #define AON_INTM_INTM_IRQSEL_COUNT (4U) /*! @name INTM_LATENCY - Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3 */ /*! @{ */ #define AON_INTM_INTM_LATENCY_LAT_MASK (0xFFFFFFU) #define AON_INTM_INTM_LATENCY_LAT_SHIFT (0U) /*! LAT - Latency */ #define AON_INTM_INTM_LATENCY_LAT(x) (((uint32_t)(((uint32_t)(x)) << AON_INTM_INTM_LATENCY_LAT_SHIFT)) & AON_INTM_INTM_LATENCY_LAT_MASK) /*! @} */ /* The count of AON_INTM_INTM_LATENCY */ #define AON_INTM_INTM_LATENCY_COUNT (4U) /*! @name INTM_TIMER - Timer for Monitor 0..Timer for Monitor 3 */ /*! @{ */ #define AON_INTM_INTM_TIMER_TIMER_MASK (0xFFFFFFU) #define AON_INTM_INTM_TIMER_TIMER_SHIFT (0U) /*! TIMER - Timer */ #define AON_INTM_INTM_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << AON_INTM_INTM_TIMER_TIMER_SHIFT)) & AON_INTM_INTM_TIMER_TIMER_MASK) /*! @} */ /* The count of AON_INTM_INTM_TIMER */ #define AON_INTM_INTM_TIMER_COUNT (4U) /*! @name INTM_STATUS - Status for Monitor 0..Status for Monitor 3 */ /*! @{ */ #define AON_INTM_INTM_STATUS_STATUS_MASK (0x1U) #define AON_INTM_INTM_STATUS_STATUS_SHIFT (0U) /*! STATUS - Monitor status * 0b1..Exceeded * 0b0..Did not exceed */ #define AON_INTM_INTM_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << AON_INTM_INTM_STATUS_STATUS_SHIFT)) & AON_INTM_INTM_STATUS_STATUS_MASK) /*! @} */ /* The count of AON_INTM_INTM_STATUS */ #define AON_INTM_INTM_STATUS_COUNT (4U) /*! * @} */ /* end of group AON_INTM_Register_Masks */ /* AON_INTM - Peripheral instance base addresses */ /** Peripheral AON__INTM base address */ #define AON__INTM_BASE (0x44580000u) /** Peripheral AON__INTM base pointer */ #define AON__INTM ((AON_INTM_Type *)AON__INTM_BASE) /** Array initializer of AON_INTM peripheral base addresses */ #define AON_INTM_BASE_ADDRS { AON__INTM_BASE } /** Array initializer of AON_INTM peripheral base pointers */ #define AON_INTM_BASE_PTRS { AON__INTM } /*! * @} */ /* end of group AON_INTM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_LSTCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_LSTCU_Peripheral_Access_Layer AON_LSTCU Peripheral Access Layer * @{ */ /** AON_LSTCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x10 */ uint8_t RESERVED_2[76]; __I uint32_t MB_RSTAT0; /**< MBIST Run Status 0, offset: 0x60 */ uint8_t RESERVED_3[284]; __IO uint32_t MBFM0; /**< MBIST Fault Mapping 0, offset: 0x180 */ uint8_t RESERVED_4[220]; __IO uint32_t STAG; /**< Stagger, offset: 0x260 */ uint8_t RESERVED_5[12]; __IO uint32_t PH1_DUR; /**< Phase 1 Duration, offset: 0x270 */ uint8_t RESERVED_6[140]; __IO uint32_t MBPTR[1]; /**< MBIST Scheduler Pointer, array offset: 0x300, array step: 0x4 */ } AON_LSTCU_Type; /* ---------------------------------------------------------------------------- -- AON_LSTCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_LSTCU_Register_Masks AON_LSTCU Register Masks * @{ */ /*! @name ERR_STAT - Error Status */ /*! @{ */ #define AON_LSTCU_ERR_STAT_INVP_MB_MASK (0x2U) #define AON_LSTCU_ERR_STAT_INVP_MB_SHIFT (1U) /*! INVP_MB - Invalid Pointer MBIST * 0b0..No invalid pointer * 0b1..Invalid BIST pointer specified */ #define AON_LSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_ERR_STAT_INVP_MB_SHIFT)) & AON_LSTCU_ERR_STAT_INVP_MB_MASK) #define AON_LSTCU_ERR_STAT_UFSF_MASK (0x10000U) #define AON_LSTCU_ERR_STAT_UFSF_SHIFT (16U) /*! UFSF - Unrecoverable Fault Status * 0b0..No unrecoverable fault * 0b1..Unrecoverable fault */ #define AON_LSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_ERR_STAT_UFSF_SHIFT)) & AON_LSTCU_ERR_STAT_UFSF_MASK) #define AON_LSTCU_ERR_STAT_RFSF_MASK (0x20000U) #define AON_LSTCU_ERR_STAT_RFSF_SHIFT (17U) /*! RFSF - Recoverable Fault Status * 0b0..No recoverable fault * 0b1..Recoverable fault */ #define AON_LSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_ERR_STAT_RFSF_SHIFT)) & AON_LSTCU_ERR_STAT_RFSF_MASK) /*! @} */ /*! @name ERR_FM - Error Fault Mapping */ /*! @{ */ #define AON_LSTCU_ERR_FM_INVPFMMB_MASK (0x2U) #define AON_LSTCU_ERR_FM_INVPFMMB_SHIFT (1U) /*! INVPFMMB - Invalid BIST Pointer Fault Mapping During MBIST Scheduling * 0b0..Recoverable * 0b1..Unrecoverable */ #define AON_LSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_ERR_FM_INVPFMMB_SHIFT)) & AON_LSTCU_ERR_FM_INVPFMMB_MASK) /*! @} */ /*! @name MB_RSTAT0 - MBIST Run Status 0 */ /*! @{ */ #define AON_LSTCU_MB_RSTAT0_MBSTAT0_MASK (0x1U) #define AON_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT (0U) /*! MBSTAT0 - MBIST Run Result Status 0 * 0b0..Pass * 0b1..Fail */ #define AON_LSTCU_MB_RSTAT0_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT)) & AON_LSTCU_MB_RSTAT0_MBSTAT0_MASK) /*! @} */ /*! @name MBFM0 - MBIST Fault Mapping 0 */ /*! @{ */ #define AON_LSTCU_MBFM0_MBSTATFM0_MASK (0x1U) #define AON_LSTCU_MBFM0_MBSTATFM0_SHIFT (0U) /*! MBSTATFM0 - MBIST Fault Mapping n * 0b0..Recoverable * 0b1..Unrecoverable */ #define AON_LSTCU_MBFM0_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_MBFM0_MBSTATFM0_SHIFT)) & AON_LSTCU_MBFM0_MBSTATFM0_MASK) /*! @} */ /*! @name STAG - Stagger */ /*! @{ */ #define AON_LSTCU_STAG_MB_DELAY_MASK (0xFF00U) #define AON_LSTCU_STAG_MB_DELAY_SHIFT (8U) /*! MB_DELAY - MBIST Delay */ #define AON_LSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_STAG_MB_DELAY_SHIFT)) & AON_LSTCU_STAG_MB_DELAY_MASK) /*! @} */ /*! @name PH1_DUR - Phase 1 Duration */ /*! @{ */ #define AON_LSTCU_PH1_DUR_PH1DUR_MASK (0x3FFU) #define AON_LSTCU_PH1_DUR_PH1DUR_SHIFT (0U) /*! PH1DUR - Phase 1 Duration */ #define AON_LSTCU_PH1_DUR_PH1DUR(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_PH1_DUR_PH1DUR_SHIFT)) & AON_LSTCU_PH1_DUR_PH1DUR_MASK) /*! @} */ /*! @name MBPTR - MBIST Scheduler Pointer */ /*! @{ */ #define AON_LSTCU_MBPTR_MBPTR_MASK (0xFFU) #define AON_LSTCU_MBPTR_MBPTR_SHIFT (0U) /*! MBPTR - MBIST Pointer */ #define AON_LSTCU_MBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_MBPTR_MBPTR_SHIFT)) & AON_LSTCU_MBPTR_MBPTR_MASK) #define AON_LSTCU_MBPTR_MBCSM_MASK (0x100U) #define AON_LSTCU_MBPTR_MBCSM_SHIFT (8U) /*! MBCSM - MBIST Mode * 0b0..Sequential * 0b1..Concurrent */ #define AON_LSTCU_MBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_MBPTR_MBCSM_SHIFT)) & AON_LSTCU_MBPTR_MBCSM_MASK) #define AON_LSTCU_MBPTR_MBEOL_MASK (0x80000000U) #define AON_LSTCU_MBPTR_MBEOL_SHIFT (31U) /*! MBEOL - MBIST End of List * 0b0..Not end of list * 0b1..End of list */ #define AON_LSTCU_MBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << AON_LSTCU_MBPTR_MBEOL_SHIFT)) & AON_LSTCU_MBPTR_MBEOL_MASK) /*! @} */ /* The count of AON_LSTCU_MBPTR */ #define AON_LSTCU_MBPTR_COUNT (1U) /*! * @} */ /* end of group AON_LSTCU_Register_Masks */ /* AON_LSTCU - Peripheral instance base addresses */ /** Peripheral AON__LSTCUA base address */ #define AON__LSTCUA_BASE (0x445A0000u) /** Peripheral AON__LSTCUA base pointer */ #define AON__LSTCUA ((AON_LSTCU_Type *)AON__LSTCUA_BASE) /** Array initializer of AON_LSTCU peripheral base addresses */ #define AON_LSTCU_BASE_ADDRS { AON__LSTCUA_BASE } /** Array initializer of AON_LSTCU peripheral base pointers */ #define AON_LSTCU_BASE_PTRS { AON__LSTCUA } /*! * @} */ /* end of group AON_LSTCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_MCM_Peripheral_Access_Layer AON_MCM Peripheral Access Layer * @{ */ /** AON_MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[16]; __IO uint32_t ISCR; /**< Interrupt Status and Control, offset: 0x10 */ __IO uint32_t ETBCC; /**< ETB Counter Control, offset: 0x14 */ __IO uint32_t ETBRR; /**< ETB Reload, offset: 0x18 */ __I uint32_t ETBCV; /**< ETB Counter Value, offset: 0x1C */ __I uint32_t FADR; /**< Write Buffer Fault Address, offset: 0x20 */ __I uint32_t FATR; /**< Store Buffer Fault Attributes, offset: 0x24 */ __I uint32_t FDR; /**< Store Buffer Fault Data, offset: 0x28 */ } AON_MCM_Type; /* ---------------------------------------------------------------------------- -- AON_MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_MCM_Register_Masks AON_MCM Register Masks * @{ */ /*! @name ISCR - Interrupt Status and Control */ /*! @{ */ #define AON_MCM_ISCR_IRQ_MASK (0x2U) #define AON_MCM_ISCR_IRQ_SHIFT (1U) /*! IRQ - ETB-Related Interrupt Pending * 0b0..No pending IRQ * 0b1..Pending IRQ */ #define AON_MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_IRQ_SHIFT)) & AON_MCM_ISCR_IRQ_MASK) #define AON_MCM_ISCR_NMI_MASK (0x4U) #define AON_MCM_ISCR_NMI_SHIFT (2U) /*! NMI - Nonmaskable Interrupt Pending * 0b0..No pending NMI * 0b1..Pending NMI */ #define AON_MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_NMI_SHIFT)) & AON_MCM_ISCR_NMI_MASK) #define AON_MCM_ISCR_DHREQ_MASK (0x8U) #define AON_MCM_ISCR_DHREQ_SHIFT (3U) /*! DHREQ - Debug Halt Request Indicator * 0b0..Not initiated * 0b1..Initiated */ #define AON_MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_DHREQ_SHIFT)) & AON_MCM_ISCR_DHREQ_MASK) #define AON_MCM_ISCR_CWBER_MASK (0x10U) #define AON_MCM_ISCR_CWBER_SHIFT (4U) /*! CWBER - Cache Write Buffer Error Status * 0b0..No error * 0b1..Error occurred */ #define AON_MCM_ISCR_CWBER(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_CWBER_SHIFT)) & AON_MCM_ISCR_CWBER_MASK) #define AON_MCM_ISCR_FIOC_MASK (0x100U) #define AON_MCM_ISCR_FIOC_SHIFT (8U) /*! FIOC - FPU Invalid Operation Interrupt Status * 0b0..No interrupt * 0b1..Interrupt occurred */ #define AON_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FIOC_SHIFT)) & AON_MCM_ISCR_FIOC_MASK) #define AON_MCM_ISCR_FDZC_MASK (0x200U) #define AON_MCM_ISCR_FDZC_SHIFT (9U) /*! FDZC - FPU Divide-by-Zero Interrupt Status * 0b0..No interrupt * 0b1..Interrupt occurred */ #define AON_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FDZC_SHIFT)) & AON_MCM_ISCR_FDZC_MASK) #define AON_MCM_ISCR_FOFC_MASK (0x400U) #define AON_MCM_ISCR_FOFC_SHIFT (10U) /*! FOFC - FPU Overflow Interrupt Status * 0b0..No interrupt * 0b1..Interrupt occurred */ #define AON_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FOFC_SHIFT)) & AON_MCM_ISCR_FOFC_MASK) #define AON_MCM_ISCR_FUFC_MASK (0x800U) #define AON_MCM_ISCR_FUFC_SHIFT (11U) /*! FUFC - FPU Underflow Interrupt status * 0b0..No interrupt * 0b1..Interrupt occurred */ #define AON_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FUFC_SHIFT)) & AON_MCM_ISCR_FUFC_MASK) #define AON_MCM_ISCR_FIXC_MASK (0x1000U) #define AON_MCM_ISCR_FIXC_SHIFT (12U) /*! FIXC - FPU Inexact Interrupt Status * 0b0..No interrupt * 0b1..Interrupt occurred */ #define AON_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FIXC_SHIFT)) & AON_MCM_ISCR_FIXC_MASK) #define AON_MCM_ISCR_FIDC_MASK (0x8000U) #define AON_MCM_ISCR_FIDC_SHIFT (15U) /*! FIDC - FPU Input Denormal Interrupt Status * 0b0..No interrupt * 0b1..Interrupt occurred */ #define AON_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FIDC_SHIFT)) & AON_MCM_ISCR_FIDC_MASK) #define AON_MCM_ISCR_CWBEE_MASK (0x100000U) #define AON_MCM_ISCR_CWBEE_SHIFT (20U) /*! CWBEE - Cache Write Buffer Error Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ISCR_CWBEE(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_CWBEE_SHIFT)) & AON_MCM_ISCR_CWBEE_MASK) #define AON_MCM_ISCR_FIOCE_MASK (0x1000000U) #define AON_MCM_ISCR_FIOCE_SHIFT (24U) /*! FIOCE - FPU Invalid Operation Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FIOCE_SHIFT)) & AON_MCM_ISCR_FIOCE_MASK) #define AON_MCM_ISCR_FDZCE_MASK (0x2000000U) #define AON_MCM_ISCR_FDZCE_SHIFT (25U) /*! FDZCE - FPU Divide-by-Zero Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FDZCE_SHIFT)) & AON_MCM_ISCR_FDZCE_MASK) #define AON_MCM_ISCR_FOFCE_MASK (0x4000000U) #define AON_MCM_ISCR_FOFCE_SHIFT (26U) /*! FOFCE - FPU Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FOFCE_SHIFT)) & AON_MCM_ISCR_FOFCE_MASK) #define AON_MCM_ISCR_FUFCE_MASK (0x8000000U) #define AON_MCM_ISCR_FUFCE_SHIFT (27U) /*! FUFCE - FPU Underflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FUFCE_SHIFT)) & AON_MCM_ISCR_FUFCE_MASK) #define AON_MCM_ISCR_FIXCE_MASK (0x10000000U) #define AON_MCM_ISCR_FIXCE_SHIFT (28U) /*! FIXCE - FPU Inexact Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FIXCE_SHIFT)) & AON_MCM_ISCR_FIXCE_MASK) #define AON_MCM_ISCR_FIDCE_MASK (0x80000000U) #define AON_MCM_ISCR_FIDCE_SHIFT (31U) /*! FIDCE - FPU Input Denormal Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ISCR_FIDCE_SHIFT)) & AON_MCM_ISCR_FIDCE_MASK) /*! @} */ /*! @name ETBCC - ETB Counter Control */ /*! @{ */ #define AON_MCM_ETBCC_CNTEN_MASK (0x1U) #define AON_MCM_ETBCC_CNTEN_SHIFT (0U) /*! CNTEN - Counter Enable * 0b0..Disable * 0b1..Enable */ #define AON_MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ETBCC_CNTEN_SHIFT)) & AON_MCM_ETBCC_CNTEN_MASK) #define AON_MCM_ETBCC_RSPT_MASK (0x6U) #define AON_MCM_ETBCC_RSPT_SHIFT (1U) /*! RSPT - Response Type * 0b00..No response * 0b01..Generate a normal interrupt * 0b10..Generate an NMI * 0b11..Generate a debug halt */ #define AON_MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ETBCC_RSPT_SHIFT)) & AON_MCM_ETBCC_RSPT_MASK) #define AON_MCM_ETBCC_RLRQ_MASK (0x8U) #define AON_MCM_ETBCC_RLRQ_SHIFT (3U) /*! RLRQ - Reload Request * 0b0..No effect * 0b1..Reload the counter (clear pending interrupt requests) */ #define AON_MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ETBCC_RLRQ_SHIFT)) & AON_MCM_ETBCC_RLRQ_MASK) /*! @} */ /*! @name ETBRR - ETB Reload */ /*! @{ */ #define AON_MCM_ETBRR_RELOAD_MASK (0x7FFU) #define AON_MCM_ETBRR_RELOAD_SHIFT (0U) /*! RELOAD - Byte Count Reload Value */ #define AON_MCM_ETBRR_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ETBRR_RELOAD_SHIFT)) & AON_MCM_ETBRR_RELOAD_MASK) /*! @} */ /*! @name ETBCV - ETB Counter Value */ /*! @{ */ #define AON_MCM_ETBCV_COUNTER_MASK (0x7FFU) #define AON_MCM_ETBCV_COUNTER_SHIFT (0U) /*! COUNTER - Byte Count Counter Value */ #define AON_MCM_ETBCV_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_ETBCV_COUNTER_SHIFT)) & AON_MCM_ETBCV_COUNTER_MASK) /*! @} */ /*! @name FADR - Write Buffer Fault Address */ /*! @{ */ #define AON_MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) #define AON_MCM_FADR_ADDRESS_SHIFT (0U) /*! ADDRESS - Fault Address */ #define AON_MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FADR_ADDRESS_SHIFT)) & AON_MCM_FADR_ADDRESS_MASK) /*! @} */ /*! @name FATR - Store Buffer Fault Attributes */ /*! @{ */ #define AON_MCM_FATR_BEDA_MASK (0x1U) #define AON_MCM_FATR_BEDA_SHIFT (0U) /*! BEDA - Bus Error Data Access Type * 0b0..Instruction * 0b1..Data */ #define AON_MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FATR_BEDA_SHIFT)) & AON_MCM_FATR_BEDA_MASK) #define AON_MCM_FATR_BEMD_MASK (0x2U) #define AON_MCM_FATR_BEMD_SHIFT (1U) /*! BEMD - Bus Error Privilege Level * 0b0..User mode * 0b1..Supervisor or privileged mode */ #define AON_MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FATR_BEMD_SHIFT)) & AON_MCM_FATR_BEMD_MASK) #define AON_MCM_FATR_BESZ_MASK (0x30U) #define AON_MCM_FATR_BESZ_SHIFT (4U) /*! BESZ - Bus Error Size * 0b00..8-bit * 0b01..16-bit * 0b10..32-bit * 0b11.. */ #define AON_MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FATR_BESZ_SHIFT)) & AON_MCM_FATR_BESZ_MASK) #define AON_MCM_FATR_BEWT_MASK (0x80U) #define AON_MCM_FATR_BEWT_SHIFT (7U) /*! BEWT - Bus Error Write * 0b0..Read * 0b1..Write */ #define AON_MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FATR_BEWT_SHIFT)) & AON_MCM_FATR_BEWT_MASK) #define AON_MCM_FATR_BEMN_MASK (0xF00U) #define AON_MCM_FATR_BEMN_SHIFT (8U) /*! BEMN - Bus Error Master Number */ #define AON_MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FATR_BEMN_SHIFT)) & AON_MCM_FATR_BEMN_MASK) #define AON_MCM_FATR_BEOVR_MASK (0x80000000U) #define AON_MCM_FATR_BEOVR_SHIFT (31U) /*! BEOVR - Bus Error Overrun * 0b0..No overrun * 0b1..Overrun */ #define AON_MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FATR_BEOVR_SHIFT)) & AON_MCM_FATR_BEOVR_MASK) /*! @} */ /*! @name FDR - Store Buffer Fault Data */ /*! @{ */ #define AON_MCM_FDR_DATA_MASK (0xFFFFFFFFU) #define AON_MCM_FDR_DATA_SHIFT (0U) /*! DATA - Fault Data */ #define AON_MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << AON_MCM_FDR_DATA_SHIFT)) & AON_MCM_FDR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group AON_MCM_Register_Masks */ /* AON_MCM - Peripheral instance base addresses */ /** Peripheral AON__MCM base address */ #define AON__MCM_BASE (0xE0080000u) /** Peripheral AON__MCM base pointer */ #define AON__MCM ((AON_MCM_Type *)AON__MCM_BASE) /** Array initializer of AON_MCM peripheral base addresses */ #define AON_MCM_BASE_ADDRS { AON__MCM_BASE } /** Array initializer of AON_MCM peripheral base pointers */ #define AON_MCM_BASE_PTRS { AON__MCM } /*! * @} */ /* end of group AON_MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_ROMCP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_ROMCP_Peripheral_Access_Layer AON_ROMCP Peripheral Access Layer * @{ */ /** AON_ROMCP - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[180]; __IO uint32_t ROMPATCHD[16]; /**< Data Registers, array offset: 0xB4, array step: 0x4 */ __IO uint32_t ROMPATCHCNTL; /**< Control Register, offset: 0xF4 */ uint32_t ROMPATCHENH; /**< Enable Register High, offset: 0xF8 */ __IO uint32_t ROMPATCHENL; /**< Enable Register Low, offset: 0xFC */ __IO uint32_t ROMPATCHA[32]; /**< Address Registers, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_1[136]; __IO uint32_t ROMPATCHSR; /**< Status Register, offset: 0x208 */ } AON_ROMCP_Type; /* ---------------------------------------------------------------------------- -- AON_ROMCP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_ROMCP_Register_Masks AON_ROMCP Register Masks * @{ */ /*! @name ROMPATCHD - Data Registers */ /*! @{ */ #define AON_ROMCP_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) #define AON_ROMCP_ROMPATCHD_DATAX_SHIFT (0U) /*! DATAX - Data Fix Registers */ #define AON_ROMCP_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHD_DATAX_SHIFT)) & AON_ROMCP_ROMPATCHD_DATAX_MASK) /*! @} */ /* The count of AON_ROMCP_ROMPATCHD */ #define AON_ROMCP_ROMPATCHD_COUNT (16U) /*! @name ROMPATCHCNTL - Control Register */ /*! @{ */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX0_MASK (0x1U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT (0U) /*! DATAFIX0 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX0(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX0_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX1_MASK (0x2U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT (1U) /*! DATAFIX1 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX1(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX1_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX2_MASK (0x4U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT (2U) /*! DATAFIX2 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX2(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX2_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX3_MASK (0x8U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT (3U) /*! DATAFIX3 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX3(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX3_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX4_MASK (0x10U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT (4U) /*! DATAFIX4 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX4(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX4_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX5_MASK (0x20U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT (5U) /*! DATAFIX5 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX5(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX5_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX6_MASK (0x40U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT (6U) /*! DATAFIX6 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX6(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX6_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX7_MASK (0x80U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT (7U) /*! DATAFIX7 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX7(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX7_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX8_MASK (0x100U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX8_SHIFT (8U) /*! DATAFIX8 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX8(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX8_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX8_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX9_MASK (0x200U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX9_SHIFT (9U) /*! DATAFIX9 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX9(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX9_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX9_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX10_MASK (0x400U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX10_SHIFT (10U) /*! DATAFIX10 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX10(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX10_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX10_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX11_MASK (0x800U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX11_SHIFT (11U) /*! DATAFIX11 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX11(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX11_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX11_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX12_MASK (0x1000U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX12_SHIFT (12U) /*! DATAFIX12 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX12(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX12_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX12_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX13_MASK (0x2000U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX13_SHIFT (13U) /*! DATAFIX13 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX13(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX13_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX13_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX14_MASK (0x4000U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX14_SHIFT (14U) /*! DATAFIX14 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX14(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX14_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX14_MASK) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX15_MASK (0x8000U) #define AON_ROMCP_ROMPATCHCNTL_DATAFIX15_SHIFT (15U) /*! DATAFIX15 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define AON_ROMCP_ROMPATCHCNTL_DATAFIX15(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DATAFIX15_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DATAFIX15_MASK) #define AON_ROMCP_ROMPATCHCNTL_DIS_MASK (0x20000000U) #define AON_ROMCP_ROMPATCHCNTL_DIS_SHIFT (29U) /*! DIS - Patch Disable * 0b0..Does not affect any Patch operations (default) * 0b1..Disables all Patch operations: data fixing and opcode patching */ #define AON_ROMCP_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & AON_ROMCP_ROMPATCHCNTL_DIS_MASK) /*! @} */ /*! @name ROMPATCHENL - Enable Register Low */ /*! @{ */ #define AON_ROMCP_ROMPATCHENL_ENABLE_MASK (0xFFFFFFFFU) #define AON_ROMCP_ROMPATCHENL_ENABLE_SHIFT (0U) /*! ENABLE - Enable Address Comparator * 0b00000000000000000000000000000000..Address comparator is disabled * 0b00000000000000000000000000000001..Address comparator is enabled; after the associated address is matched, the ROMC will trigger a opcode patch or data fix event. */ #define AON_ROMCP_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHENL_ENABLE_SHIFT)) & AON_ROMCP_ROMPATCHENL_ENABLE_MASK) /*! @} */ /*! @name ROMPATCHA - Address Registers */ /*! @{ */ #define AON_ROMCP_ROMPATCHA_THUMBX_MASK (0x1U) #define AON_ROMCP_ROMPATCHA_THUMBX_SHIFT (0U) /*! THUMBX - THUMB Comparator Select * 0b0..ARM patch * 0b1..THUMB patch (ignore if a data fix) */ #define AON_ROMCP_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHA_THUMBX_SHIFT)) & AON_ROMCP_ROMPATCHA_THUMBX_MASK) #define AON_ROMCP_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) #define AON_ROMCP_ROMPATCHA_ADDRX_SHIFT (1U) /*! ADDRX - Address Comparator Registers */ #define AON_ROMCP_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHA_ADDRX_SHIFT)) & AON_ROMCP_ROMPATCHA_ADDRX_MASK) /*! @} */ /* The count of AON_ROMCP_ROMPATCHA */ #define AON_ROMCP_ROMPATCHA_COUNT (32U) /*! @name ROMPATCHSR - Status Register */ /*! @{ */ #define AON_ROMCP_ROMPATCHSR_SOURCE_MASK (0x3FU) #define AON_ROMCP_ROMPATCHSR_SOURCE_SHIFT (0U) /*! SOURCE - ROMCP Source Number * 0b000000..Address Comparator 0 matched * 0b000001..Address Comparator 1 matched * 0b001111..Address Comparator 15 matched */ #define AON_ROMCP_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & AON_ROMCP_ROMPATCHSR_SOURCE_MASK) #define AON_ROMCP_ROMPATCHSR_SW_MASK (0x20000U) #define AON_ROMCP_ROMPATCHSR_SW_SHIFT (17U) /*! SW - ROMCP AHB Multiple Address Comparator Match Indicator * 0b0..No event or comparator collisions have occurred * 0b1..A collision has occurred */ #define AON_ROMCP_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << AON_ROMCP_ROMPATCHSR_SW_SHIFT)) & AON_ROMCP_ROMPATCHSR_SW_MASK) /*! @} */ /*! * @} */ /* end of group AON_ROMCP_Register_Masks */ /* AON_ROMCP - Peripheral instance base addresses */ /** Peripheral AON__ROMCP1 base address */ #define AON__ROMCP1_BASE (0x44430000u) /** Peripheral AON__ROMCP1 base pointer */ #define AON__ROMCP1 ((AON_ROMCP_Type *)AON__ROMCP1_BASE) /** Array initializer of AON_ROMCP peripheral base addresses */ #define AON_ROMCP_BASE_ADDRS { AON__ROMCP1_BASE } /** Array initializer of AON_ROMCP peripheral base pointers */ #define AON_ROMCP_BASE_PTRS { AON__ROMCP1 } /*! * @} */ /* end of group AON_ROMCP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_SYSPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_SYSPM_Peripheral_Access_Layer AON_SYSPM Peripheral Access Layer * @{ */ /** AON_SYSPM - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x30 */ __IO uint32_t PMCR; /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */ uint8_t RESERVED_0[12]; __I uint8_t PMICTR_HI; /**< Performance Monitor Instruction Counter, array offset: 0x10, array step: 0x30 */ uint8_t RESERVED_1[3]; __I uint32_t PMICTR_LO; /**< Performance Monitor Instruction Counter, array offset: 0x14, array step: 0x30 */ struct { /* offset: 0x18, array step: index*0x30, index2*0x8 */ __I uint8_t HI; /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */ uint8_t RESERVED_0[3]; __I uint32_t LO; /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */ } PMECTR[3]; } PMCR[1]; } AON_SYSPM_Type; /* ---------------------------------------------------------------------------- -- AON_SYSPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_SYSPM_Register_Masks AON_SYSPM Register Masks * @{ */ /*! @name PMCR - Performance Monitor Control */ /*! @{ */ #define AON_SYSPM_PMCR_MENB_MASK (0x1U) #define AON_SYSPM_PMCR_MENB_SHIFT (0U) /*! MENB - Module Is Enabled * 0b0..Disabled * 0b1..Enabled */ #define AON_SYSPM_PMCR_MENB(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_MENB_SHIFT)) & AON_SYSPM_PMCR_MENB_MASK) #define AON_SYSPM_PMCR_SSC_MASK (0xEU) #define AON_SYSPM_PMCR_SSC_SHIFT (1U) /*! SSC - Start and Stop Control * 0b000..Idle or no-op * 0b001..Local stop * 0b010, 0b011..Local start * 0b100.. * 0b101.. * 0b110, 0b111.. */ #define AON_SYSPM_PMCR_SSC(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_SSC_SHIFT)) & AON_SYSPM_PMCR_SSC_MASK) #define AON_SYSPM_PMCR_CMODE_MASK (0x30U) #define AON_SYSPM_PMCR_CMODE_SHIFT (4U) /*! CMODE - Count Mode * 0b00..Counted in both User and Privileged modes * 0b01.. * 0b10..Counted only in User mode * 0b11..Counted only in Privileged mode */ #define AON_SYSPM_PMCR_CMODE(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_CMODE_SHIFT)) & AON_SYSPM_PMCR_CMODE_MASK) #define AON_SYSPM_PMCR_DCIFSH_MASK (0x40U) #define AON_SYSPM_PMCR_DCIFSH_SHIFT (6U) /*! DCIFSH - Disable Counters if Stopped or Halted * 0b0..Continue * 0b1..Stop */ #define AON_SYSPM_PMCR_DCIFSH(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_DCIFSH_SHIFT)) & AON_SYSPM_PMCR_DCIFSH_MASK) #define AON_SYSPM_PMCR_RICTR_MASK (0x80U) #define AON_SYSPM_PMCR_RICTR_SHIFT (7U) /*! RICTR - Reset Instruction Counter * 0b0..Do not reset * 0b1..Clear */ #define AON_SYSPM_PMCR_RICTR(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_RICTR_SHIFT)) & AON_SYSPM_PMCR_RICTR_MASK) #define AON_SYSPM_PMCR_RECTR1_MASK (0x100U) #define AON_SYSPM_PMCR_RECTR1_SHIFT (8U) /*! RECTR1 - Reset Event Counter 1 * 0b0..Run normally * 0b1..Reset */ #define AON_SYSPM_PMCR_RECTR1(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_RECTR1_SHIFT)) & AON_SYSPM_PMCR_RECTR1_MASK) #define AON_SYSPM_PMCR_RECTR2_MASK (0x200U) #define AON_SYSPM_PMCR_RECTR2_SHIFT (9U) /*! RECTR2 - Reset Event Counter 2 * 0b0..Run normally * 0b1..Reset */ #define AON_SYSPM_PMCR_RECTR2(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_RECTR2_SHIFT)) & AON_SYSPM_PMCR_RECTR2_MASK) #define AON_SYSPM_PMCR_RECTR3_MASK (0x400U) #define AON_SYSPM_PMCR_RECTR3_SHIFT (10U) /*! RECTR3 - Reset Event Counter 3 * 0b0..Run normally * 0b1..Reset */ #define AON_SYSPM_PMCR_RECTR3(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_RECTR3_SHIFT)) & AON_SYSPM_PMCR_RECTR3_MASK) #define AON_SYSPM_PMCR_SELEVT1_MASK (0x3F800U) #define AON_SYSPM_PMCR_SELEVT1_SHIFT (11U) /*! SELEVT1 - Select Event 1 */ #define AON_SYSPM_PMCR_SELEVT1(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_SELEVT1_SHIFT)) & AON_SYSPM_PMCR_SELEVT1_MASK) #define AON_SYSPM_PMCR_SELEVT2_MASK (0x1FC0000U) #define AON_SYSPM_PMCR_SELEVT2_SHIFT (18U) /*! SELEVT2 - Select Event 2 */ #define AON_SYSPM_PMCR_SELEVT2(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_SELEVT2_SHIFT)) & AON_SYSPM_PMCR_SELEVT2_MASK) #define AON_SYSPM_PMCR_SELEVT3_MASK (0xFE000000U) #define AON_SYSPM_PMCR_SELEVT3_SHIFT (25U) /*! SELEVT3 - Select Event 3 */ #define AON_SYSPM_PMCR_SELEVT3(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMCR_SELEVT3_SHIFT)) & AON_SYSPM_PMCR_SELEVT3_MASK) /*! @} */ /* The count of AON_SYSPM_PMCR */ #define AON_SYSPM_PMCR_COUNT (1U) /*! @name PMICTR_HI - Performance Monitor Instruction Counter */ /*! @{ */ #define AON_SYSPM_PMICTR_HI_ICTR_MASK (0xFFU) #define AON_SYSPM_PMICTR_HI_ICTR_SHIFT (0U) /*! ICTR - Instruction Counter */ #define AON_SYSPM_PMICTR_HI_ICTR(x) (((uint8_t)(((uint8_t)(x)) << AON_SYSPM_PMICTR_HI_ICTR_SHIFT)) & AON_SYSPM_PMICTR_HI_ICTR_MASK) /*! @} */ /* The count of AON_SYSPM_PMICTR_HI */ #define AON_SYSPM_PMICTR_HI_COUNT (1U) /*! @name PMICTR_LO - Performance Monitor Instruction Counter */ /*! @{ */ #define AON_SYSPM_PMICTR_LO_ICTR_MASK (0xFFFFFFFFU) #define AON_SYSPM_PMICTR_LO_ICTR_SHIFT (0U) /*! ICTR - Instruction Counter */ #define AON_SYSPM_PMICTR_LO_ICTR(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_PMICTR_LO_ICTR_SHIFT)) & AON_SYSPM_PMICTR_LO_ICTR_MASK) /*! @} */ /* The count of AON_SYSPM_PMICTR_LO */ #define AON_SYSPM_PMICTR_LO_COUNT (1U) /*! @name HI - Performance Monitor Event Counter */ /*! @{ */ #define AON_SYSPM_HI_ECTR_MASK (0xFFU) #define AON_SYSPM_HI_ECTR_SHIFT (0U) /*! ECTR - Event Counter */ #define AON_SYSPM_HI_ECTR(x) (((uint8_t)(((uint8_t)(x)) << AON_SYSPM_HI_ECTR_SHIFT)) & AON_SYSPM_HI_ECTR_MASK) /*! @} */ /* The count of AON_SYSPM_HI */ #define AON_SYSPM_HI_COUNT (1U) /* The count of AON_SYSPM_HI */ #define AON_SYSPM_HI_COUNT2 (3U) /*! @name LO - Performance Monitor Event Counter */ /*! @{ */ #define AON_SYSPM_LO_ECTR_MASK (0xFFFFFFFFU) #define AON_SYSPM_LO_ECTR_SHIFT (0U) /*! ECTR - Event Counter */ #define AON_SYSPM_LO_ECTR(x) (((uint32_t)(((uint32_t)(x)) << AON_SYSPM_LO_ECTR_SHIFT)) & AON_SYSPM_LO_ECTR_MASK) /*! @} */ /* The count of AON_SYSPM_LO */ #define AON_SYSPM_LO_COUNT (1U) /* The count of AON_SYSPM_LO */ #define AON_SYSPM_LO_COUNT2 (3U) /*! * @} */ /* end of group AON_SYSPM_Register_Masks */ /* AON_SYSPM - Peripheral instance base addresses */ /** Peripheral AON__M33_PCF1 base address */ #define AON__M33_PCF1_BASE (0x443E0000u) /** Peripheral AON__M33_PCF1 base pointer */ #define AON__M33_PCF1 ((AON_SYSPM_Type *)AON__M33_PCF1_BASE) /** Peripheral AON__M33_PSF1 base address */ #define AON__M33_PSF1_BASE (0x443F0000u) /** Peripheral AON__M33_PSF1 base pointer */ #define AON__M33_PSF1 ((AON_SYSPM_Type *)AON__M33_PSF1_BASE) /** Array initializer of AON_SYSPM peripheral base addresses */ #define AON_SYSPM_BASE_ADDRS { AON__M33_PCF1_BASE, AON__M33_PSF1_BASE } /** Array initializer of AON_SYSPM peripheral base pointers */ #define AON_SYSPM_BASE_PTRS { AON__M33_PCF1, AON__M33_PSF1 } /*! * @} */ /* end of group AON_SYSPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AON_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_TCU_Peripheral_Access_Layer AON_TCU Peripheral Access Layer * @{ */ /** AON_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[348]; __IO uint32_t TCU_CRR_IPT_CORE_HOLD; /**< ipc_core_hold, offset: 0x570 */ uint8_t RESERVED_3[140]; __IO uint32_t TCU_MTR_MCT_ACCESS_; /**< MCT Test Mode CTRL Reg, offset: 0x600 */ uint8_t RESERVED_4[12]; __IO uint32_t TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL0; /**< MCT Launch ALGOSEL0 Reg, offset: 0x610 */ __IO uint32_t TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL1; /**< MCT Launch ALGOSEL1 Reg, offset: 0x614 */ uint8_t RESERVED_5[8]; __IO uint32_t TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL0; /**< MCT Launch BISTSEL0 Reg, offset: 0x620 */ __IO uint32_t TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL1; /**< MCT Launch BISTSEL1 Reg, offset: 0x624 */ __IO uint32_t TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL2; /**< MCT Launch BISTSEL2 Reg, offset: 0x628 */ __IO uint32_t TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL3; /**< MCT Launch BISTSEL2 Reg, offset: 0x62C */ uint8_t RESERVED_6[32]; __IO uint32_t TCU_MTR_DIRECT_BIST_ACCESS_; /**< Direct BIST Access CTRL Reg, offset: 0x650 */ uint8_t RESERVED_7[1452]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_8[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } AON_TCU_Type; /* ---------------------------------------------------------------------------- -- AON_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AON_TCU_Register_Masks AON_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define AON_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define AON_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & AON_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define AON_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define AON_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & AON_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_CRR_IPT_CORE_HOLD - ipc_core_hold */ /*! @{ */ #define AON_TCU_TCU_CRR_IPT_CORE_HOLD_ipt_core_hold_MASK (0x1U) #define AON_TCU_TCU_CRR_IPT_CORE_HOLD_ipt_core_hold_SHIFT (0U) /*! ipt_core_hold - ipt_core_hold */ #define AON_TCU_TCU_CRR_IPT_CORE_HOLD_ipt_core_hold(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_CRR_IPT_CORE_HOLD_ipt_core_hold_SHIFT)) & AON_TCU_TCU_CRR_IPT_CORE_HOLD_ipt_core_hold_MASK) /*! @} */ /*! @name TCU_MTR_MCT_ACCESS_ - MCT Test Mode CTRL Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_test_mode_MASK (0x1U) #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_test_mode_SHIFT (0U) /*! mct_test_mode - For using MCT test mode through the TCU, this bit has to be set first which * enables all the muxes related to this test mode */ #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_test_mode(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__mct_test_mode_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__mct_test_mode_MASK) #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_bist_start_MASK (0x2U) #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_bist_start_SHIFT (1U) /*! mct_launch_bist_start - Signal in the MCT that is basically used to start all the BIST's selected through mct_launch_bistsel registers */ #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_bist_start(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_bist_start_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_bist_start_MASK) #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_crep_MASK (0x4U) #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_crep_SHIFT (2U) /*! mct_launch_crep - Signal in the MCT used to calculate repair while running the BIST incase of any failure */ #define AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_crep(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_crep_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__mct_launch_crep_MASK) /*! @} */ /*! @name TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL0 - MCT Launch ALGOSEL0 Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL0_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL0_out_SHIFT (0U) /*! out - Select the required algorithm */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL0_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL0_out_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL0_out_MASK) /*! @} */ /*! @name TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL1 - MCT Launch ALGOSEL1 Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL1_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL1_out_SHIFT (0U) /*! out - Select the required algorithm */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL1_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL1_out_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_ALGOSEL1_out_MASK) /*! @} */ /*! @name TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL0 - MCT Launch BISTSEL0 Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL0_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL0_out_SHIFT (0U) /*! out - Selects BIST's [31:0] that will be run */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL0_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL0_out_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL0_out_MASK) /*! @} */ /*! @name TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL1 - MCT Launch BISTSEL1 Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL1_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL1_out_SHIFT (0U) /*! out - Selects BIST's [63:32] that will be run */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL1_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL1_out_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL1_out_MASK) /*! @} */ /*! @name TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL2 - MCT Launch BISTSEL2 Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL2_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL2_out_SHIFT (0U) /*! out - Selects BIST's [95:64] that will be run */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL2_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL2_out_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL2_out_MASK) /*! @} */ /*! @name TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL3 - MCT Launch BISTSEL2 Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL3_out_MASK (0xFFFFFFFFU) #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL3_out_SHIFT (0U) /*! out - Selects BIST's [127:96] that will be run */ #define AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL3_out(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL3_out_SHIFT)) & AON_TCU_TCU_MTR_MCT_ACCESS__MCT_LAUNCH_BISTSEL3_out_MASK) /*! @} */ /*! @name TCU_MTR_DIRECT_BIST_ACCESS_ - Direct BIST Access CTRL Reg */ /*! @{ */ #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_mode_MASK (0x1U) #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_mode_SHIFT (0U) /*! bist_mode - bist mode indication */ #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_mode(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_mode_SHIFT)) & AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_mode_MASK) #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_mode_MASK (0x2U) #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_mode_SHIFT (1U) /*! bist_burnin_loop_mode - Test mode bit to qualify the BIST start in Burn-in mode */ #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_mode(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_mode_SHIFT)) & AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_mode_MASK) #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_start_MASK (0x4U) #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_start_SHIFT (2U) /*! bist_burnin_loop_start - start burnin BIST signal */ #define AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_start(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_start_SHIFT)) & AON_TCU_TCU_MTR_DIRECT_BIST_ACCESS__bist_burnin_loop_start_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define AON_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define AON_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define AON_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & AON_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define AON_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define AON_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define AON_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & AON_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define AON_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define AON_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define AON_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & AON_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define AON_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define AON_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define AON_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & AON_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define AON_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define AON_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define AON_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & AON_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define AON_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define AON_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define AON_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & AON_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define AON_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define AON_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define AON_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & AON_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define AON_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x3EU) #define AON_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define AON_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << AON_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & AON_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group AON_TCU_Register_Masks */ /* AON_TCU - Peripheral instance base addresses */ /** Peripheral AON__TCU base address */ #define AON__TCU_BASE (0x444B0000u) /** Peripheral AON__TCU base pointer */ #define AON__TCU ((AON_TCU_Type *)AON__TCU_BASE) /** Array initializer of AON_TCU peripheral base addresses */ #define AON_TCU_BASE_ADDRS { AON__TCU_BASE } /** Array initializer of AON_TCU peripheral base pointers */ #define AON_TCU_BASE_PTRS { AON__TCU } /*! * @} */ /* end of group AON_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AUTOFOCUS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AUTOFOCUS_Peripheral_Access_Layer AUTOFOCUS Peripheral Access Layer * @{ */ /** AUTOFOCUS - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0xB8 */ struct { /* offset: 0x0, array step: index*0xB8, index2*0x8 */ __IO uint32_t POS_CAM; /**< Camera 0 Autofocus ROI 0 Position Register..Camera 0 Autofocus ROI 8 Position Register, array offset: 0x0, array step: index*0xB8, index2*0x8 */ __IO uint32_t SIZE_CAM; /**< Camera 0 Autofocus ROI 0 Size Register..Camera 0 Autofocus ROI 8 Size Register, array offset: 0x4, array step: index*0xB8, index2*0x8 */ } ROI[9]; uint8_t RESERVED_0[8]; struct { /* offset: 0x50, array step: index*0xB8, index2*0x10 */ __IO uint32_t FIL_COEFFS0_CAM; /**< Camera 0 Autofocus Filter 0 Coefficient Set 0 Register..Camera 0 Autofocus Filter 1 Coefficient Set 0 Register, array offset: 0x50, array step: index*0xB8, index2*0x10 */ __IO uint32_t FIL_COEFFS1_CAM; /**< Camera 0 Autofocus Filter 0 Coefficient Set 1 Register..Camera 0 Autofocus Filter 1 Coefficient Set 1 Register, array offset: 0x54, array step: index*0xB8, index2*0x10 */ __IO uint32_t FIL_COEFFS2_CAM; /**< Camera 0 Autofocus Filter 0 Coefficient Set 2 Register..Camera 0 Autofocus Filter 1 Coefficient Set 2 Register, array offset: 0x58, array step: index*0xB8, index2*0x10 */ __IO uint32_t FIL_SHIFT_CAM; /**< Camera 0 Autofocus Filter 0 Shift Register..Camera 0 Autofocus Filter 1 Shift Register, array offset: 0x5C, array step: index*0xB8, index2*0x10 */ } FILTER[2]; struct { /* offset: 0x70, array step: index*0xB8, index2*0x8 */ __I uint32_t ROI_SUM0_CAM; /**< Camera 0 Autofocus ROI 0 SUM Filter 0 Register..Camera 0 Autofocus ROI 8 SUM Filter 0 Register, array offset: 0x70, array step: index*0xB8, index2*0x8 */ __I uint32_t ROI_SUM1_CAM; /**< Camera 0 Autofocus ROI 0 SUM Filter 1 Register..Camera 0 Autofocus ROI 8 SUM Filter 1 Register, array offset: 0x74, array step: index*0xB8, index2*0x8 */ } SUM[9]; } NEO_PIPE2_AF_CONF[1]; } AUTOFOCUS_Type; /* ---------------------------------------------------------------------------- -- AUTOFOCUS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AUTOFOCUS_Register_Masks AUTOFOCUS Register Masks * @{ */ /*! @name POS_CAM - Camera 0 Autofocus ROI 0 Position Register..Camera 0 Autofocus ROI 8 Position Register */ /*! @{ */ #define AUTOFOCUS_POS_CAM_XPOS_MASK (0xFFFFU) #define AUTOFOCUS_POS_CAM_XPOS_SHIFT (0U) #define AUTOFOCUS_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_POS_CAM_XPOS_SHIFT)) & AUTOFOCUS_POS_CAM_XPOS_MASK) #define AUTOFOCUS_POS_CAM_YPOS_MASK (0xFFFF0000U) #define AUTOFOCUS_POS_CAM_YPOS_SHIFT (16U) #define AUTOFOCUS_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_POS_CAM_YPOS_SHIFT)) & AUTOFOCUS_POS_CAM_YPOS_MASK) /*! @} */ /* The count of AUTOFOCUS_POS_CAM */ #define AUTOFOCUS_POS_CAM_COUNT (1U) /* The count of AUTOFOCUS_POS_CAM */ #define AUTOFOCUS_POS_CAM_COUNT2 (9U) /*! @name SIZE_CAM - Camera 0 Autofocus ROI 0 Size Register..Camera 0 Autofocus ROI 8 Size Register */ /*! @{ */ #define AUTOFOCUS_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define AUTOFOCUS_SIZE_CAM_WIDTH_SHIFT (0U) #define AUTOFOCUS_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_SIZE_CAM_WIDTH_SHIFT)) & AUTOFOCUS_SIZE_CAM_WIDTH_MASK) #define AUTOFOCUS_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define AUTOFOCUS_SIZE_CAM_HEIGHT_SHIFT (16U) #define AUTOFOCUS_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_SIZE_CAM_HEIGHT_SHIFT)) & AUTOFOCUS_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of AUTOFOCUS_SIZE_CAM */ #define AUTOFOCUS_SIZE_CAM_COUNT (1U) /* The count of AUTOFOCUS_SIZE_CAM */ #define AUTOFOCUS_SIZE_CAM_COUNT2 (9U) /*! @name FIL_COEFFS0_CAM - Camera 0 Autofocus Filter 0 Coefficient Set 0 Register..Camera 0 Autofocus Filter 1 Coefficient Set 0 Register */ /*! @{ */ #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF0_MASK (0xFFU) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF0_SHIFT (0U) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF0(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS0_CAM_COEFF0_SHIFT)) & AUTOFOCUS_FIL_COEFFS0_CAM_COEFF0_MASK) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF1_MASK (0xFF00U) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF1_SHIFT (8U) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF1(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS0_CAM_COEFF1_SHIFT)) & AUTOFOCUS_FIL_COEFFS0_CAM_COEFF1_MASK) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF2_MASK (0xFF0000U) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF2_SHIFT (16U) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF2(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS0_CAM_COEFF2_SHIFT)) & AUTOFOCUS_FIL_COEFFS0_CAM_COEFF2_MASK) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF3_MASK (0xFF000000U) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF3_SHIFT (24U) #define AUTOFOCUS_FIL_COEFFS0_CAM_COEFF3(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS0_CAM_COEFF3_SHIFT)) & AUTOFOCUS_FIL_COEFFS0_CAM_COEFF3_MASK) /*! @} */ /* The count of AUTOFOCUS_FIL_COEFFS0_CAM */ #define AUTOFOCUS_FIL_COEFFS0_CAM_COUNT (1U) /* The count of AUTOFOCUS_FIL_COEFFS0_CAM */ #define AUTOFOCUS_FIL_COEFFS0_CAM_COUNT2 (2U) /*! @name FIL_COEFFS1_CAM - Camera 0 Autofocus Filter 0 Coefficient Set 1 Register..Camera 0 Autofocus Filter 1 Coefficient Set 1 Register */ /*! @{ */ #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF4_MASK (0xFFU) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF4_SHIFT (0U) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF4(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS1_CAM_COEFF4_SHIFT)) & AUTOFOCUS_FIL_COEFFS1_CAM_COEFF4_MASK) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF5_MASK (0xFF00U) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF5_SHIFT (8U) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF5(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS1_CAM_COEFF5_SHIFT)) & AUTOFOCUS_FIL_COEFFS1_CAM_COEFF5_MASK) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF6_MASK (0xFF0000U) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF6_SHIFT (16U) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF6(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS1_CAM_COEFF6_SHIFT)) & AUTOFOCUS_FIL_COEFFS1_CAM_COEFF6_MASK) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF7_MASK (0xFF000000U) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF7_SHIFT (24U) #define AUTOFOCUS_FIL_COEFFS1_CAM_COEFF7(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS1_CAM_COEFF7_SHIFT)) & AUTOFOCUS_FIL_COEFFS1_CAM_COEFF7_MASK) /*! @} */ /* The count of AUTOFOCUS_FIL_COEFFS1_CAM */ #define AUTOFOCUS_FIL_COEFFS1_CAM_COUNT (1U) /* The count of AUTOFOCUS_FIL_COEFFS1_CAM */ #define AUTOFOCUS_FIL_COEFFS1_CAM_COUNT2 (2U) /*! @name FIL_COEFFS2_CAM - Camera 0 Autofocus Filter 0 Coefficient Set 2 Register..Camera 0 Autofocus Filter 1 Coefficient Set 2 Register */ /*! @{ */ #define AUTOFOCUS_FIL_COEFFS2_CAM_COEFF8_MASK (0xFFU) #define AUTOFOCUS_FIL_COEFFS2_CAM_COEFF8_SHIFT (0U) #define AUTOFOCUS_FIL_COEFFS2_CAM_COEFF8(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_COEFFS2_CAM_COEFF8_SHIFT)) & AUTOFOCUS_FIL_COEFFS2_CAM_COEFF8_MASK) /*! @} */ /* The count of AUTOFOCUS_FIL_COEFFS2_CAM */ #define AUTOFOCUS_FIL_COEFFS2_CAM_COUNT (1U) /* The count of AUTOFOCUS_FIL_COEFFS2_CAM */ #define AUTOFOCUS_FIL_COEFFS2_CAM_COUNT2 (2U) /*! @name FIL_SHIFT_CAM - Camera 0 Autofocus Filter 0 Shift Register..Camera 0 Autofocus Filter 1 Shift Register */ /*! @{ */ #define AUTOFOCUS_FIL_SHIFT_CAM_SHIFT_MASK (0x1FU) #define AUTOFOCUS_FIL_SHIFT_CAM_SHIFT_SHIFT (0U) #define AUTOFOCUS_FIL_SHIFT_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_FIL_SHIFT_CAM_SHIFT_SHIFT)) & AUTOFOCUS_FIL_SHIFT_CAM_SHIFT_MASK) /*! @} */ /* The count of AUTOFOCUS_FIL_SHIFT_CAM */ #define AUTOFOCUS_FIL_SHIFT_CAM_COUNT (1U) /* The count of AUTOFOCUS_FIL_SHIFT_CAM */ #define AUTOFOCUS_FIL_SHIFT_CAM_COUNT2 (2U) /*! @name ROI_SUM0_CAM - Camera 0 Autofocus ROI 0 SUM Filter 0 Register..Camera 0 Autofocus ROI 8 SUM Filter 0 Register */ /*! @{ */ #define AUTOFOCUS_ROI_SUM0_CAM_SUM_MASK (0xFFFFFFFFU) #define AUTOFOCUS_ROI_SUM0_CAM_SUM_SHIFT (0U) #define AUTOFOCUS_ROI_SUM0_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_ROI_SUM0_CAM_SUM_SHIFT)) & AUTOFOCUS_ROI_SUM0_CAM_SUM_MASK) /*! @} */ /* The count of AUTOFOCUS_ROI_SUM0_CAM */ #define AUTOFOCUS_ROI_SUM0_CAM_COUNT (1U) /* The count of AUTOFOCUS_ROI_SUM0_CAM */ #define AUTOFOCUS_ROI_SUM0_CAM_COUNT2 (9U) /*! @name ROI_SUM1_CAM - Camera 0 Autofocus ROI 0 SUM Filter 1 Register..Camera 0 Autofocus ROI 8 SUM Filter 1 Register */ /*! @{ */ #define AUTOFOCUS_ROI_SUM1_CAM_SUM_MASK (0xFFFFFFFFU) #define AUTOFOCUS_ROI_SUM1_CAM_SUM_SHIFT (0U) #define AUTOFOCUS_ROI_SUM1_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << AUTOFOCUS_ROI_SUM1_CAM_SUM_SHIFT)) & AUTOFOCUS_ROI_SUM1_CAM_SUM_MASK) /*! @} */ /* The count of AUTOFOCUS_ROI_SUM1_CAM */ #define AUTOFOCUS_ROI_SUM1_CAM_COUNT (1U) /* The count of AUTOFOCUS_ROI_SUM1_CAM */ #define AUTOFOCUS_ROI_SUM1_CAM_COUNT2 (9U) /*! * @} */ /* end of group AUTOFOCUS_Register_Masks */ /* AUTOFOCUS - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__AUTOFOCUS base address */ #define CAMERA__ISP__AUTOFOCUS_BASE (0x4AE01700u) /** Peripheral CAMERA__ISP__AUTOFOCUS base pointer */ #define CAMERA__ISP__AUTOFOCUS ((AUTOFOCUS_Type *)CAMERA__ISP__AUTOFOCUS_BASE) /** Array initializer of AUTOFOCUS peripheral base addresses */ #define AUTOFOCUS_BASE_ADDRS { CAMERA__ISP__AUTOFOCUS_BASE } /** Array initializer of AUTOFOCUS peripheral base pointers */ #define AUTOFOCUS_BASE_PTRS { CAMERA__ISP__AUTOFOCUS } /*! * @} */ /* end of group AUTOFOCUS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BBSM_BBNSM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BBSM_BBNSM_Peripheral_Access_Layer BBSM_BBNSM Peripheral Access Layer * @{ */ /** BBSM_BBNSM - Register Layout Typedef */ typedef struct { __I uint32_t BBNSM_VID; /**< BBNSM Version ID Register, offset: 0x0 */ __I uint32_t BBNSM_FEATURES; /**< BBNSM Features Register, offset: 0x4 */ __IO uint32_t BBNSM_CTRL; /**< BBNSM Control Register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t BBNSM_INT_EN; /**< BBNSM Interrupt Enable Register, offset: 0x10 */ __IO uint32_t BBNSM_EVENTS; /**< BBNSM Events Register, offset: 0x14 */ uint8_t RESERVED_1[12]; __IO uint32_t BBNSM_PAD_CTRL; /**< BBNSM External Pad Control Register, offset: 0x24 */ uint8_t RESERVED_2[24]; __IO uint32_t BBNSM_RTC_LS; /**< BBNSM Real-Time Counter LS Register, offset: 0x40 */ __IO uint32_t BBNSM_RTC_MS; /**< BBNSM Real-Time Counter MS Register, offset: 0x44 */ uint8_t RESERVED_3[8]; __IO uint32_t BBNSM_TA; /**< BBNSM Time Alarm Register, offset: 0x50 */ uint8_t RESERVED_4[684]; __IO uint32_t GPR[8]; /**< General Purpose Register Word 0..General Purpose Register Word 7, array offset: 0x300, array step: 0x4 */ } BBSM_BBNSM_Type; /* ---------------------------------------------------------------------------- -- BBSM_BBNSM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BBSM_BBNSM_Register_Masks BBSM_BBNSM Register Masks * @{ */ /*! @name BBNSM_VID - BBNSM Version ID Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_VID_BBNSM_IPID_MASK (0xFFU) #define BBSM_BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT (0U) /*! BBNSM_IPID - BBNSM IP ID */ #define BBSM_BBNSM_BBNSM_VID_BBNSM_IPID(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_VID_BBNSM_IPID_SHIFT)) & BBSM_BBNSM_BBNSM_VID_BBNSM_IPID_MASK) #define BBSM_BBNSM_BBNSM_VID_BBNSM_REV_MASK (0xFF00U) #define BBSM_BBNSM_BBNSM_VID_BBNSM_REV_SHIFT (8U) /*! BBNSM_REV - BBNSM Revision */ #define BBSM_BBNSM_BBNSM_VID_BBNSM_REV(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_VID_BBNSM_REV_SHIFT)) & BBSM_BBNSM_BBNSM_VID_BBNSM_REV_MASK) #define BBSM_BBNSM_BBNSM_VID_BBNSM_VID_MASK (0xFF0000U) #define BBSM_BBNSM_BBNSM_VID_BBNSM_VID_SHIFT (16U) /*! BBNSM_VID - BBNSM Version ID */ #define BBSM_BBNSM_BBNSM_VID_BBNSM_VID(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_VID_BBNSM_VID_SHIFT)) & BBSM_BBNSM_BBNSM_VID_BBNSM_VID_MASK) /*! @} */ /*! @name BBNSM_FEATURES - BBNSM Features Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_FEATURES_GPR_SZ_MASK (0xFCU) #define BBSM_BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT (2U) /*! GPR_SZ - GPR Register Array Size * 0b000000..This version of BBNSM does not implement a general-purpose register array. * *..The number of 32-bit words implemented in the general-purpose register array. */ #define BBSM_BBNSM_BBNSM_FEATURES_GPR_SZ(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_FEATURES_GPR_SZ_SHIFT)) & BBSM_BBNSM_BBNSM_FEATURES_GPR_SZ_MASK) /*! @} */ /*! @name BBNSM_CTRL - BBNSM Control Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_CTRL_RTC_EN_MASK (0x3U) #define BBSM_BBNSM_BBNSM_CTRL_RTC_EN_SHIFT (0U) /*! RTC_EN - Real-Time Counter Enable * 0b01..Disable the real-time counter. * 0b10..Enable the real-time counter. */ #define BBSM_BBNSM_BBNSM_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_RTC_EN_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_RTC_EN_MASK) #define BBSM_BBNSM_BBNSM_CTRL_TA_EN_MASK (0xCU) #define BBSM_BBNSM_BBNSM_CTRL_TA_EN_SHIFT (2U) /*! TA_EN - Time Alarm Enable * 0b01..Disable the time alarm. * 0b10..Enable the time alarm. A time alarm event occurs if the value in the real-time counter register is equal * to the value in the time alarm register. */ #define BBSM_BBNSM_BBNSM_CTRL_TA_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_TA_EN_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_TA_EN_MASK) #define BBSM_BBNSM_BBNSM_CTRL_CAL_EN_MASK (0x10U) #define BBSM_BBNSM_BBNSM_CTRL_CAL_EN_SHIFT (4U) /*! CAL_EN - Calibration Enable * 0b0..RTC Time calibration is disabled. * 0b1..RTC Time calibration is enabled. */ #define BBSM_BBNSM_BBNSM_CTRL_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_CAL_EN_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_CAL_EN_MASK) #define BBSM_BBNSM_BBNSM_CTRL_CAL_VAL_MASK (0x1F00U) #define BBSM_BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT (8U) /*! CAL_VAL - Calibration Value * 0b01111..+15 counts per each 32768 ticks of the counter clock. * 0b00010..+2 counts per each 32768 ticks of the counter clock. * 0b00001..+1 counts per each 32768 ticks of the counter clock. * 0b00000..+0 counts per each 32768 ticks of the counter clock. * 0b11111..-1 counts per each 32768 ticks of the counter clock. * 0b11110..-2 counts per each 32768 ticks of the counter clock. * 0b10001..-15 counts per each 32768 ticks of the counter clock. * 0b10000..-16 counts per each 32768 ticks of the counter clock. */ #define BBSM_BBNSM_BBNSM_CTRL_CAL_VAL(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_CAL_VAL_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_CAL_VAL_MASK) #define BBSM_BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK (0x30000U) #define BBSM_BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT (16U) /*! BTN_TIMEOUT - Button Press Timeout * 0b00..5 seconds. * 0b01..10 seconds. * 0b10..15 seconds. * 0b11..Timeout disabled. Long button presses will not request a power down. */ #define BBSM_BBNSM_BBNSM_CTRL_BTN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_BTN_TIMEOUT_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_BTN_TIMEOUT_MASK) #define BBSM_BBNSM_BBNSM_CTRL_DEBOUNCE_MASK (0xC0000U) #define BBSM_BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT (18U) /*! DEBOUNCE - Debounce Time * 0b00..50 milliseconds. * 0b01..100 milliseconds. * 0b10..500 milliseconds. * 0b11..0 milliseconds. */ #define BBSM_BBNSM_BBNSM_CTRL_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_DEBOUNCE_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_DEBOUNCE_MASK) #define BBSM_BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK (0x300000U) #define BBSM_BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT (20U) /*! TURN_ON_TIME - Turn-On Time * 0b00..500 milliseconds. * 0b01..50 milliseconds. * 0b10..100 milliseconds. * 0b11..0 milliseconds. */ #define BBSM_BBNSM_BBNSM_CTRL_TURN_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_TURN_ON_TIME_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_TURN_ON_TIME_MASK) #define BBSM_BBNSM_BBNSM_CTRL_PK_EN_MASK (0x400000U) #define BBSM_BBNSM_BBNSM_CTRL_PK_EN_SHIFT (22U) /*! PK_EN - PMIC On Request Enable * 0b0..PMIC On Request is disabled. * 0b1..PMIC On Request is enabled. */ #define BBSM_BBNSM_BBNSM_CTRL_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_PK_EN_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_PK_EN_MASK) #define BBSM_BBNSM_BBNSM_CTRL_PK_OVR_MASK (0x800000U) #define BBSM_BBNSM_BBNSM_CTRL_PK_OVR_SHIFT (23U) /*! PK_OVR - PMIC On Request Override * 0b0..PMIC On Request Override is disabled. * 0b1..PMIC On Request Override is enabled. */ #define BBSM_BBNSM_BBNSM_CTRL_PK_OVR(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_PK_OVR_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_PK_OVR_MASK) #define BBSM_BBNSM_BBNSM_CTRL_DP_EN_MASK (0x1000000U) #define BBSM_BBNSM_BBNSM_CTRL_DP_EN_SHIFT (24U) /*! DP_EN - Dumb PMIC Enable * 0b0..Smart PMIC is enabled. * 0b1..Dumb PMIC is enabled. */ #define BBSM_BBNSM_BBNSM_CTRL_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_DP_EN_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_DP_EN_MASK) #define BBSM_BBNSM_BBNSM_CTRL_TOSP_MASK (0x2000000U) #define BBSM_BBNSM_BBNSM_CTRL_TOSP_SHIFT (25U) /*! TOSP - Turn Off System Power * 0b0..Leave system power on. * 0b1..Turn off system power when Dumb PMIC is enabled. */ #define BBSM_BBNSM_BBNSM_CTRL_TOSP(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_TOSP_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_TOSP_MASK) #define BBSM_BBNSM_BBNSM_CTRL_BTN_CONFIG_MASK (0x1C000000U) #define BBSM_BBNSM_BBNSM_CTRL_BTN_CONFIG_SHIFT (26U) /*! BTN_CONFIG - Button Configuration. * 0b000..Button signal is active high * 0b001..Button signal is active low * 0b010..Button signal is active on the falling edge * 0b011..Button signal is active on the rising edge * 0b100..Button signal is active on any edge */ #define BBSM_BBNSM_BBNSM_CTRL_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_CTRL_BTN_CONFIG_SHIFT)) & BBSM_BBNSM_BBNSM_CTRL_BTN_CONFIG_MASK) /*! @} */ /*! @name BBNSM_INT_EN - BBNSM Interrupt Enable Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK (0x3U) #define BBSM_BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT (0U) /*! RTC_INT_EN - Real-Time Counter Rollover Interrupt Enable * 0b01..Do not issue an interrupt when RTC has rolled over. The interrupt is cleared when this value is written. * 0b10..Issue an interrupt when RTC has rolled over. */ #define BBSM_BBNSM_BBNSM_INT_EN_RTC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_INT_EN_RTC_INT_EN_SHIFT)) & BBSM_BBNSM_BBNSM_INT_EN_RTC_INT_EN_MASK) #define BBSM_BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK (0xCU) #define BBSM_BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT (2U) /*! TA_INT_EN - Time Alarm Interrupt Enable * 0b01..Do not issue an interrupt when RTC has reached alarm time. The interrupt is cleared when this value is written. * 0b10..Issue an interrupt when RTC has reached alarm time. */ #define BBSM_BBNSM_BBNSM_INT_EN_TA_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_INT_EN_TA_INT_EN_SHIFT)) & BBSM_BBNSM_BBNSM_INT_EN_TA_INT_EN_MASK) #define BBSM_BBNSM_BBNSM_INT_EN_BTN_INT_EN_MASK (0x10U) #define BBSM_BBNSM_BBNSM_INT_EN_BTN_INT_EN_SHIFT (4U) /*! BTN_INT_EN - Button Interrupt Enable * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define BBSM_BBNSM_BBNSM_INT_EN_BTN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_INT_EN_BTN_INT_EN_SHIFT)) & BBSM_BBNSM_BBNSM_INT_EN_BTN_INT_EN_MASK) /*! @} */ /*! @name BBNSM_EVENTS - BBNSM Events Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK (0x3U) #define BBSM_BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT (0U) /*! RTC_ROLL - Real-Time Counter Rollover Event * 0b01..The real-time counter has not rolled over. * 0b10..The real-time counter has rolled over. */ #define BBSM_BBNSM_BBNSM_EVENTS_RTC_ROLL(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_EVENTS_RTC_ROLL_SHIFT)) & BBSM_BBNSM_BBNSM_EVENTS_RTC_ROLL_MASK) #define BBSM_BBNSM_BBNSM_EVENTS_TA_MASK (0xCU) #define BBSM_BBNSM_BBNSM_EVENTS_TA_SHIFT (2U) /*! TA - Time Alarm Event * 0b01..The real-time counter has not reached the alarm time. * 0b10..The real-time counter has reached the alarm time. */ #define BBSM_BBNSM_BBNSM_EVENTS_TA(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_EVENTS_TA_SHIFT)) & BBSM_BBNSM_BBNSM_EVENTS_TA_MASK) #define BBSM_BBNSM_BBNSM_EVENTS_EMG_OFF_MASK (0x10U) #define BBSM_BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT (4U) /*! EMG_OFF - Emergency Off Event * 0b0..An emergency power off has not been requested. * 0b1..An emergency power off has been requested. */ #define BBSM_BBNSM_BBNSM_EVENTS_EMG_OFF(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_EVENTS_EMG_OFF_SHIFT)) & BBSM_BBNSM_BBNSM_EVENTS_EMG_OFF_MASK) #define BBSM_BBNSM_BBNSM_EVENTS_PWR_OFF_MASK (0x20U) #define BBSM_BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT (5U) /*! PWR_OFF - Set Power Off Event * 0b0..The power off interrupt has not been requested. * 0b1..The power off interrupt has been requested. */ #define BBSM_BBNSM_BBNSM_EVENTS_PWR_OFF(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_EVENTS_PWR_OFF_SHIFT)) & BBSM_BBNSM_BBNSM_EVENTS_PWR_OFF_MASK) #define BBSM_BBNSM_BBNSM_EVENTS_PWR_ON_MASK (0x40U) #define BBSM_BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT (6U) /*! PWR_ON - Set Power On Event * 0b0..The power on interrupt has not been requested. * 0b1..The power on interrupt has been requested. */ #define BBSM_BBNSM_BBNSM_EVENTS_PWR_ON(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_EVENTS_PWR_ON_SHIFT)) & BBSM_BBNSM_BBNSM_EVENTS_PWR_ON_MASK) #define BBSM_BBNSM_BBNSM_EVENTS_BTN_MASK (0x80U) #define BBSM_BBNSM_BBNSM_EVENTS_BTN_SHIFT (7U) /*! BTN - Button * 0b0..BTN not pressed * 0b1..BTN pressed */ #define BBSM_BBNSM_BBNSM_EVENTS_BTN(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_EVENTS_BTN_SHIFT)) & BBSM_BBNSM_BBNSM_EVENTS_BTN_MASK) #define BBSM_BBNSM_BBNSM_EVENTS_BI_MASK (0x100U) #define BBSM_BBNSM_BBNSM_EVENTS_BI_SHIFT (8U) /*! BI - Button Interrupt */ #define BBSM_BBNSM_BBNSM_EVENTS_BI(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_EVENTS_BI_SHIFT)) & BBSM_BBNSM_BBNSM_EVENTS_BI_MASK) /*! @} */ /*! @name BBNSM_PAD_CTRL - BBNSM External Pad Control Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK (0x1U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT (0U) /*! PAD_CTRL0 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL0_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK (0x2U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT (1U) /*! PAD_CTRL1 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL1_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK (0x4U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT (2U) /*! PAD_CTRL2 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL2_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK (0x8U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT (3U) /*! PAD_CTRL3 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL3_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK (0x10U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT (4U) /*! PAD_CTRL4 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL4_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK (0x20U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT (5U) /*! PAD_CTRL5 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL5_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK (0x40U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT (6U) /*! PAD_CTRL6 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL6_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK (0x80U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT (7U) /*! PAD_CTRL7 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL7_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK (0x100U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT (8U) /*! PAD_CTRL8 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL8_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK (0x200U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT (9U) /*! PAD_CTRL9 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL9_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK (0x400U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT (10U) /*! PAD_CTRL10 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL10_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK (0x800U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT (11U) /*! PAD_CTRL11 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL11_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK (0x1000U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT (12U) /*! PAD_CTRL12 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL12_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK (0x2000U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT (13U) /*! PAD_CTRL13 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL13_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK (0x4000U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT (14U) /*! PAD_CTRL14 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL14_MASK) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK (0x8000U) #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT (15U) /*! PAD_CTRL15 - Control I/O Pads * 0b0..Deasserts bit n in bbnsm_pad_ctrl[n] * 0b1..Assert bit n in bbnsm_pad_ctrl[n] */ #define BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_SHIFT)) & BBSM_BBNSM_BBNSM_PAD_CTRL_PAD_CTRL15_MASK) /*! @} */ /*! @name BBNSM_RTC_LS - BBNSM Real-Time Counter LS Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_RTC_LS_RTC_MASK (0xFFFFFFFFU) #define BBSM_BBNSM_BBNSM_RTC_LS_RTC_SHIFT (0U) /*! RTC - Real-time Counter */ #define BBSM_BBNSM_BBNSM_RTC_LS_RTC(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_RTC_LS_RTC_SHIFT)) & BBSM_BBNSM_BBNSM_RTC_LS_RTC_MASK) /*! @} */ /*! @name BBNSM_RTC_MS - BBNSM Real-Time Counter MS Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_RTC_MS_RTC_MASK (0x7FFFU) #define BBSM_BBNSM_BBNSM_RTC_MS_RTC_SHIFT (0U) /*! RTC - Real-Time Counter */ #define BBSM_BBNSM_BBNSM_RTC_MS_RTC(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_RTC_MS_RTC_SHIFT)) & BBSM_BBNSM_BBNSM_RTC_MS_RTC_MASK) /*! @} */ /*! @name BBNSM_TA - BBNSM Time Alarm Register */ /*! @{ */ #define BBSM_BBNSM_BBNSM_TA_TA_MASK (0xFFFFFFFFU) #define BBSM_BBNSM_BBNSM_TA_TA_SHIFT (0U) /*! TA - Time Alarm Value */ #define BBSM_BBNSM_BBNSM_TA_TA(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_BBNSM_TA_TA_SHIFT)) & BBSM_BBNSM_BBNSM_TA_TA_MASK) /*! @} */ /*! @name GPR - General Purpose Register Word 0..General Purpose Register Word 7 */ /*! @{ */ #define BBSM_BBNSM_GPR_GPR_MASK (0xFFFFFFFFU) #define BBSM_BBNSM_GPR_GPR_SHIFT (0U) /*! GPR - 32 bits of the GPR. */ #define BBSM_BBNSM_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BBNSM_GPR_GPR_SHIFT)) & BBSM_BBNSM_GPR_GPR_MASK) /*! @} */ /* The count of BBSM_BBNSM_GPR */ #define BBSM_BBNSM_GPR_COUNT (8U) /*! * @} */ /* end of group BBSM_BBNSM_Register_Masks */ /* BBSM_BBNSM - Peripheral instance base addresses */ /** Peripheral BBSM__BBNSM base address */ #define BBSM__BBNSM_BASE (0x44440000u) /** Peripheral BBSM__BBNSM base pointer */ #define BBSM__BBNSM ((BBSM_BBNSM_Type *)BBSM__BBNSM_BASE) /** Array initializer of BBSM_BBNSM peripheral base addresses */ #define BBSM_BBNSM_BASE_ADDRS { BBSM__BBNSM_BASE } /** Array initializer of BBSM_BBNSM peripheral base pointers */ #define BBSM_BBNSM_BASE_PTRS { BBSM__BBNSM } /*! * @} */ /* end of group BBSM_BBNSM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BBSM_BLK_CTRL_BBSMMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BBSM_BLK_CTRL_BBSMMIX_Peripheral_Access_Layer BBSM_BLK_CTRL_BBSMMIX Peripheral Access Layer * @{ */ /** BBSM_BLK_CTRL_BBSMMIX - Register Layout Typedef */ typedef struct { __IO uint32_t SXOSC_CTRL; /**< SXOSC Control Register, offset: 0x0 */ __IO uint32_t SNVS_CLKRST_CTRL; /**< snvs_clkrst Control Register, offset: 0x4 */ } BBSM_BLK_CTRL_BBSMMIX_Type; /* ---------------------------------------------------------------------------- -- BBSM_BLK_CTRL_BBSMMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BBSM_BLK_CTRL_BBSMMIX_Register_Masks BBSM_BLK_CTRL_BBSMMIX Register Masks * @{ */ /*! @name SXOSC_CTRL - SXOSC Control Register */ /*! @{ */ #define BBSM_BLK_CTRL_BBSMMIX_SXOSC_CTRL_pwd_lv_MASK (0x10000U) #define BBSM_BLK_CTRL_BBSMMIX_SXOSC_CTRL_pwd_lv_SHIFT (16U) /*! pwd_lv - Power down/enable signal * 0b0..Power up * 0b1..Power down */ #define BBSM_BLK_CTRL_BBSMMIX_SXOSC_CTRL_pwd_lv(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BLK_CTRL_BBSMMIX_SXOSC_CTRL_pwd_lv_SHIFT)) & BBSM_BLK_CTRL_BBSMMIX_SXOSC_CTRL_pwd_lv_MASK) /*! @} */ /*! @name SNVS_CLKRST_CTRL - snvs_clkrst Control Register */ /*! @{ */ #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_test_sel_MASK (0xF0U) #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_test_sel_SHIFT (4U) /*! test_sel - Test select inputs * 0b0000..Normal functional mode * 0b1000..Bandgap buffer to ADC enabled for ADC test */ #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_test_sel(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_test_sel_SHIFT)) & BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_test_sel_MASK) #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_fast_MASK (0x2000U) #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_fast_SHIFT (13U) /*! tst_xtal_fast - Indicates fast external XTAL crystal * 0b0..Fast external XTAL crystal is disabled * 0b1..Fast external XTAL crystal is enabled */ #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_fast(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_fast_SHIFT)) & BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_fast_MASK) #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_slow_MASK (0x4000U) #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_slow_SHIFT (14U) /*! tst_xtal_slow - Indicates slow external XTAL crystal * 0b1..Slow external XTAL crystal is enabled * 0b0..Slow external XTAL crystal is disabled */ #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_slow(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_slow_SHIFT)) & BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_tst_xtal_slow_MASK) #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_xtal_ok_MASK (0x8000U) #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_xtal_ok_SHIFT (15U) /*! xtal_ok - Indicates XTAL clock is in frequency range and source of 32 kHz clock * 0b0..XTAL clock is not in frequency range and source of 32 KHz clock * 0b1..XTAL clock is in frequency range and source of 32 KHz clock */ #define BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_xtal_ok(x) (((uint32_t)(((uint32_t)(x)) << BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_xtal_ok_SHIFT)) & BBSM_BLK_CTRL_BBSMMIX_SNVS_CLKRST_CTRL_xtal_ok_MASK) /*! @} */ /*! * @} */ /* end of group BBSM_BLK_CTRL_BBSMMIX_Register_Masks */ /* BBSM_BLK_CTRL_BBSMMIX - Peripheral instance base addresses */ /** Peripheral BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1 base address */ #define BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1_BASE (0x44410000u) /** Peripheral BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1 base pointer */ #define BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1 ((BBSM_BLK_CTRL_BBSMMIX_Type *)BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1_BASE) /** Array initializer of BBSM_BLK_CTRL_BBSMMIX peripheral base addresses */ #define BBSM_BLK_CTRL_BBSMMIX_BASE_ADDRS { BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1_BASE } /** Array initializer of BBSM_BLK_CTRL_BBSMMIX peripheral base pointers */ #define BBSM_BLK_CTRL_BBSMMIX_BASE_PTRS { BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1 } /*! * @} */ /* end of group BBSM_BLK_CTRL_BBSMMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BBSM_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BBSM_TCU_Peripheral_Access_Layer BBSM_TCU Peripheral Access Layer * @{ */ /** BBSM_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ } BBSM_TCU_Type; /* ---------------------------------------------------------------------------- -- BBSM_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BBSM_TCU_Register_Masks BBSM_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & BBSM_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & BBSM_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & BBSM_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & BBSM_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & BBSM_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & BBSM_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define BBSM_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << BBSM_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & BBSM_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! * @} */ /* end of group BBSM_TCU_Register_Masks */ /* BBSM_TCU - Peripheral instance base addresses */ /** Peripheral BBSM__TCU_BBSMMIX base address */ #define BBSM__TCU_BBSMMIX_BASE (0x444E0000u) /** Peripheral BBSM__TCU_BBSMMIX base pointer */ #define BBSM__TCU_BBSMMIX ((BBSM_TCU_Type *)BBSM__TCU_BBSMMIX_BASE) /** Array initializer of BBSM_TCU peripheral base addresses */ #define BBSM_TCU_BASE_ADDRS { BBSM__TCU_BBSMMIX_BASE } /** Array initializer of BBSM_TCU peripheral base pointers */ #define BBSM_TCU_BASE_PTRS { BBSM__TCU_BBSMMIX } /*! * @} */ /* end of group BBSM_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BLK_CTRL_CAMERAMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BLK_CTRL_CAMERAMIX_Peripheral_Access_Layer BLK_CTRL_CAMERAMIX Peripheral Access Layer * @{ */ /** BLK_CTRL_CAMERAMIX - Register Layout Typedef */ typedef struct { __IO uint32_t ISP_CLOCK_GATING_CONTROL; /**< ISP Clock gating control, offset: 0x0 */ __IO uint32_t ISP_AXCACHE_CONTROL; /**< ISP AxCache control, offset: 0x4 */ __IO uint32_t ISP_QOS_SETTING; /**< ISP QoS setting, offset: 0x8 */ __IO uint32_t ISI_AXCACHE_CONTROL; /**< ISI AxCache control, offset: 0xC */ __IO uint32_t ISI_QOS_SETTING; /**< ISI QoS setting, offset: 0x10 */ __IO uint32_t PANIC_QOS; /**< ISI Panic QoS setting, offset: 0x14 */ __I uint32_t INIT_PENDING_TX; /**< Init_pending_Tx, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t CSI0_VC_INTERLACED_LINE_COUNT_SET[8]; /**< Virtual Channel interlaced Line count, array offset: 0x20, array step: 0x4 */ __IO uint32_t CSI0_VC_INTERLACED_CTRL; /**< CSI0 VC Interlaced Control, offset: 0x40 */ __IO uint32_t CSI0_VC_INTERLACED_ERROR; /**< CSI0 VC Interlaced Error, offset: 0x44 */ __IO uint32_t CSI0_YUV420_FIRST_LINE_EVEN; /**< CSI0 YUV420 First Line Even, offset: 0x48 */ uint8_t RESERVED_1[4]; __IO uint32_t CSI0_RAW32_CTR; /**< CSI0 RAW32 Control, offset: 0x50 */ __IO uint32_t CSI0_STREAM_FENCING_CTRL; /**< Stream fencing control., offset: 0x54 */ __I uint32_t CSI0_STREAM_FENCING_STATUS; /**< Stream fencing status., offset: 0x58 */ uint8_t RESERVED_2[4]; __IO uint32_t CSI0_NP_data_type_VC[8]; /**< CSI0 VC0 non-pixel data type..CSI0 VC7 non-pixel data type, array offset: 0x60, array step: 0x4 */ __IO uint32_t CSI0_Pixel_data_ctrl_VC[8]; /**< CSI0 Pixel Data Control VC0..CSI0 Pixel Data Control VC7, array offset: 0x80, array step: 0x4 */ __IO uint32_t CSI0_Route_Pixel_data_type_VC[8]; /**< CSI0 Route Pixel Data Type VC0..CSI0 Route Pixel Data Type VC7, array offset: 0xA0, array step: 0x4 */ __IO uint32_t CSI0_Non_Pixel_data_ctrl_VC[8]; /**< CSI0 Non-Pixel Data Control VC0..CSI0 Non-Pixel Data Control VC7, array offset: 0xC0, array step: 0x4 */ __IO uint32_t CSI0_Pixel_data_type_VC[8]; /**< CSI0 Pixel Data Type VC0..CSI0 Pixel Data Type VC7, array offset: 0xE0, array step: 0x4 */ __IO uint32_t CSI0_Pixel_data_type_err_VC[8]; /**< CSI0 Pixel Data Type Error VC0..CSI0 Pixel Data Type Error VC7, array offset: 0x100, array step: 0x4 */ __IO uint32_t CSI1_VC_INTERLACED_LINE_COUNT_SET[8]; /**< Virtual Channel interlaced Line count, array offset: 0x120, array step: 0x4 */ __IO uint32_t CSI1_VC_INTERLACED_CTRL; /**< CSI1 VC Interlaced Control, offset: 0x140 */ __IO uint32_t CSI1_VC_INTERLACED_ERROR; /**< CSI1 VC Interlaced Error, offset: 0x144 */ __IO uint32_t CSI1_YUV420_FIRST_LINE_EVEN; /**< CSI1 YUV420 First Line Even, offset: 0x148 */ uint8_t RESERVED_3[4]; __IO uint32_t CSI1_RAW32_CTR; /**< CSI1 RAW32 Control, offset: 0x150 */ __IO uint32_t CSI1_STREAM_FENCING_CTRL; /**< Stream fencing control., offset: 0x154 */ __I uint32_t CSI1_STREAM_FENCING_STATUS; /**< Stream fencing status., offset: 0x158 */ uint8_t RESERVED_4[4]; __IO uint32_t CSI1_NP_data_type_VC[8]; /**< CSI1 VC0 non-pixel data type..CSI1 VC7 non-pixel data type, array offset: 0x160, array step: 0x4 */ __IO uint32_t CSI1_Pixel_data_ctrl_VC[8]; /**< Control of the routing of the pixel data on Pixel link virtual channel., array offset: 0x180, array step: 0x4 */ __IO uint32_t CSI1_Route_Pixel_data_type_VC[8]; /**< CSI1 Route Pixel Data Type VC0..CSI1 Route Pixel Data Type VC7, array offset: 0x1A0, array step: 0x4 */ __IO uint32_t CSI1_Non_Pixel_data_ctrl_VC[8]; /**< CSI1 Non-Pixel Data Control VC0..CSI1 Non-Pixel Data Control VC7, array offset: 0x1C0, array step: 0x4 */ __IO uint32_t CSI1_Pixel_data_type_VC[8]; /**< CSI1 Pixel Data Type VC0..CSI1 Pixel Data Type VC7, array offset: 0x1E0, array step: 0x4 */ __IO uint32_t CSI1_Pixel_data_type_err_VC[8]; /**< CSI1 Pixel Data Type Error VC0..CSI1 Pixel Data Type Error VC7, array offset: 0x200, array step: 0x4 */ __IO uint32_t CSI0_PIXEL_LINK_RAW10_FORMAT; /**< Pixel link RAW10 format, offset: 0x220 */ __IO uint32_t CSI1_PIXEL_LINK_RAW10_FORMAT; /**< Pixel link RAW10 format, offset: 0x224 */ __IO uint32_t CSI0_BUFFER_OVERFLOW; /**< Buffer Overflow, offset: 0x228 */ __IO uint32_t CSI1_BUFFER_OVERFLOW; /**< Buffer Overflow, offset: 0x22C */ uint8_t RESERVED_5[208]; __IO uint32_t CM0P_ADDR_OFFSET1; /**< Cortex-M0+ Address Offset 1, offset: 0x300 */ __IO uint32_t CM0P_ADDR_OFFSET2; /**< Cortex-M0+ Address Offset 2, offset: 0x304 */ __IO uint32_t CM0P_CPUWAIT; /**< Cortex-M0+ CPUWAIT, offset: 0x308 */ __IO uint32_t CM0P_CTL; /**< Cortex-M0+ Control, offset: 0x30C */ __I uint32_t CM0P_STAT; /**< Cortex-M0+ Status, offset: 0x310 */ __IO uint32_t LPCAC_ERROR; /**< LPCAC Error, offset: 0x314 */ __IO uint32_t LPCAC_ERROR_ADDR; /**< LPCAC Error Address, offset: 0x318 */ __IO uint32_t LPCAC_ERROR_DATA; /**< LPCAC Error Data, offset: 0x31C */ __IO uint32_t ISP_CONFIG; /**< ISP Configuration, offset: 0x320 */ } BLK_CTRL_CAMERAMIX_Type; /* ---------------------------------------------------------------------------- -- BLK_CTRL_CAMERAMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BLK_CTRL_CAMERAMIX_Register_Masks BLK_CTRL_CAMERAMIX Register Masks * @{ */ /*! @name ISP_CLOCK_GATING_CONTROL - ISP Clock gating control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_0_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_0_SHIFT (0U) /*! CSI2_pixel_formatting_0 - Pixel link clock gate control of the CSI2 pixel formatting 0 (Standalone) * 0b0..Do not gate the Pixel link clock of the CSI2 pixel formatting 0 * 0b1..Gate the Pixel link clock of the CSI2 pixel formatting 0 */ #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_0_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_0_MASK) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_1_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_1_SHIFT (1U) /*! CSI2_pixel_formatting_1 - Pixel link clock gate control of the CSI2 pixel formatting 1 (Combo) * 0b1..Gate the Pixel link clock of the CSI2 pixel formatting 1 * 0b0..Do not gate the Pixel link clock of the CSI2 pixel formatting 1 */ #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_1_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_CSI2_pixel_formatting_1_MASK) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_AXI_clock_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_AXI_clock_SHIFT (4U) /*! ISP_AXI_clock - AXI clock gate control of the ISP * 0b1..Gate the AXI clock of the ISP * 0b0..Do not gate the AXI clock of the ISP */ #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_AXI_clock(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_AXI_clock_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_AXI_clock_MASK) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_Pixel_clock_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_Pixel_clock_SHIFT (5U) /*! ISP_Pixel_clock - Pixel clock gate control of the ISP * 0b1..Gate the Pixel clock of the ISP * 0b0..Do not gate the Pixel clock of the ISP */ #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_Pixel_clock(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_Pixel_clock_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_Pixel_clock_MASK) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_ISP_clock_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_ISP_clock_SHIFT (6U) /*! ISP_ISP_clock - ISP clock gate control of the ISP * 0b0..Do not gate the ISP clock of the ISP * 0b1..Gate the ISP clock of the ISP */ #define BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_ISP_clock(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_ISP_clock_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_CLOCK_GATING_CONTROL_ISP_ISP_clock_MASK) /*! @} */ /*! @name ISP_AXCACHE_CONTROL - ISP AxCache control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_ArCache_MASK (0xFU) #define BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_ArCache_SHIFT (0U) /*! ArCache - Set the AXI ArCache signal for the AXI read master ports */ #define BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_ArCache(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_ArCache_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_ArCache_MASK) #define BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_AwCache_MASK (0xF00U) #define BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_AwCache_SHIFT (8U) /*! AwCache - Set the AXI AwCache signal for the AXI write master ports */ #define BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_AwCache(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_AwCache_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_AXCACHE_CONTROL_AwCache_MASK) /*! @} */ /*! @name ISP_QOS_SETTING - ISP QoS setting */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_AwQoS_MASK (0x7U) #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_AwQoS_SHIFT (0U) /*! AwQoS - Set the AXI AwQoS signal for all ISP AXI write ports. */ #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_AwQoS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_AwQoS_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_AwQoS_MASK) #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_ArQoS_MASK (0x700U) #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_ArQoS_SHIFT (8U) /*! ArQoS - Set the AXI ArQoS signal for all ISP AXI write ports. */ #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_ArQoS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_ArQoS_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_ArQoS_MASK) #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_Ar_local_panic_QoS_MASK (0x7000U) #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_Ar_local_panic_QoS_SHIFT (12U) /*! Ar_local_panic_QoS - Set the AXI Hurry/Pressure QoS signal when the o_arpostqos of the AXI read port are set to '1'. */ #define BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_Ar_local_panic_QoS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_Ar_local_panic_QoS_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_QOS_SETTING_Ar_local_panic_QoS_MASK) /*! @} */ /*! @name ISI_AXCACHE_CONTROL - ISI AxCache control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_ArCache_MASK (0xFU) #define BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_ArCache_SHIFT (0U) /*! ArCache - Set the AXI ArCache signal for the AXI read master ports */ #define BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_ArCache(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_ArCache_SHIFT)) & BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_ArCache_MASK) #define BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_AwCache_MASK (0xF00U) #define BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_AwCache_SHIFT (8U) /*! AwCache - Set the AXI AwCache signal for the AXI write master ports */ #define BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_AwCache(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_AwCache_SHIFT)) & BLK_CTRL_CAMERAMIX_ISI_AXCACHE_CONTROL_AwCache_MASK) /*! @} */ /*! @name ISI_QOS_SETTING - ISI QoS setting */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_ISI_QOS_SETTING_AwQoS_MASK (0x7U) #define BLK_CTRL_CAMERAMIX_ISI_QOS_SETTING_AwQoS_SHIFT (0U) /*! AwQoS - Set the AXI AwQoS signal for all ISI AXI read and write ports. */ #define BLK_CTRL_CAMERAMIX_ISI_QOS_SETTING_AwQoS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISI_QOS_SETTING_AwQoS_SHIFT)) & BLK_CTRL_CAMERAMIX_ISI_QOS_SETTING_AwQoS_MASK) /*! @} */ /*! @name PANIC_QOS - ISI Panic QoS setting */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_PANIC_QOS_Panic_QoS_MASK (0x7U) #define BLK_CTRL_CAMERAMIX_PANIC_QOS_Panic_QoS_SHIFT (0U) /*! Panic_QoS - Set the AXI Hurry AwQoS signal for all ISI and ISP AXI write ports, when corresponding panic signals are active. */ #define BLK_CTRL_CAMERAMIX_PANIC_QOS_Panic_QoS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_PANIC_QOS_Panic_QoS_SHIFT)) & BLK_CTRL_CAMERAMIX_PANIC_QOS_Panic_QoS_MASK) /*! @} */ /*! @name INIT_PENDING_TX - Init_pending_Tx */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_0_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_0_SHIFT (0U) /*! Read_AXI_ISP_0 - Read_AXI_ISP_0 pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_0_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_0_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_1_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_1_SHIFT (1U) /*! Read_AXI_ISP_1 - Read_AXI_ISP_1 pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_1_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_AXI_ISP_1_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_0_MASK (0x4U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_0_SHIFT (2U) /*! Write_AXI_ISP_0 - Write_AXI_ISP_0 pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_0_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_0_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_1_MASK (0x8U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_1_SHIFT (3U) /*! Write_AXI_ISP_1 - Write_AXI_ISP_1 pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_1_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_AXI_ISP_1_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_ISI_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_ISI_SHIFT (4U) /*! Read_ISI - Read_ISI pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_ISI(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_ISI_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Read_ISI_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_Y_ISI_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_Y_ISI_SHIFT (5U) /*! Write_Y_ISI - Write_Y_ISI pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_Y_ISI(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_Y_ISI_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_Y_ISI_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_U_ISI_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_U_ISI_SHIFT (6U) /*! Write_U_ISI - Write_U_ISI pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_U_ISI(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_U_ISI_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_U_ISI_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_V_ISI_MASK (0x80U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_V_ISI_SHIFT (7U) /*! Write_V_ISI - Write_V_ISI pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_V_ISI(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_V_ISI_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_Write_V_ISI_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_CM0P_MASK (0x100U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_CM0P_SHIFT (8U) /*! CM0P - CM0P pending transaction * 0b0..No pending transaction * 0b1..Pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_CM0P(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_CM0P_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_CM0P_MASK) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_eDMA_MASK (0x200U) #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_eDMA_SHIFT (9U) /*! eDMA - eDMA pending transaction * 0b1..Pending transaction * 0b0..No pending transaction */ #define BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_eDMA(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_eDMA_SHIFT)) & BLK_CTRL_CAMERAMIX_INIT_PENDING_TX_eDMA_MASK) /*! @} */ /*! @name CSI0_VC_INTERLACED_LINE_COUNT_SET - Virtual Channel interlaced Line count */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_MASK (0x3FFFU) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_SHIFT (0U) /*! Odd_line_count - Odd line count */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_MASK (0x3FFF0000U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_SHIFT (16U) /*! Even_line_count - Even line count */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Even_line_count(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_LINE_COUNT_SET_COUNT (8U) /*! @name CSI0_VC_INTERLACED_CTRL - CSI0 VC Interlaced Control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC0_interlace_mode_MASK (0x3U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC0_interlace_mode_SHIFT (0U) /*! CSI0_VC0_interlace_mode - CSI0 VC0 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC0_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC0_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC0_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC1_interlace_mode_MASK (0xCU) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC1_interlace_mode_SHIFT (2U) /*! CSI0_VC1_interlace_mode - CSI0 VC1 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC1_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC1_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC1_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC2_interlace_mode_MASK (0x30U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC2_interlace_mode_SHIFT (4U) /*! CSI0_VC2_interlace_mode - CSI0 VC2 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC2_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC2_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC2_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC3_interlace_mode_MASK (0xC0U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC3_interlace_mode_SHIFT (6U) /*! CSI0_VC3_interlace_mode - CSI0 VC3 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC3_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC3_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC3_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC4_interlace_mode_MASK (0x300U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC4_interlace_mode_SHIFT (8U) /*! CSI0_VC4_interlace_mode - CSI0 VC4 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC4_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC4_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC4_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC5_interlace_mode_MASK (0xC00U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC5_interlace_mode_SHIFT (10U) /*! CSI0_VC5_interlace_mode - CSI0 VC5 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC5_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC5_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC5_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC6_interlace_mode_MASK (0x3000U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC6_interlace_mode_SHIFT (12U) /*! CSI0_VC6_interlace_mode - CSI0 VC6 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC6_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC6_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC6_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC7_interlace_mode_MASK (0xC000U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC7_interlace_mode_SHIFT (14U) /*! CSI0_VC7_interlace_mode - CSI0 VC7 interlace mode * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC7_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC7_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_CTRL_CSI0_VC7_interlace_mode_MASK) /*! @} */ /*! @name CSI0_VC_INTERLACED_ERROR - CSI0 VC Interlaced Error */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC0_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC0_SHIFT (0U) /*! CSI0_VC0 - CSI0 VC1 line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC0_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC0_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC1_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC1_SHIFT (1U) /*! CSI0_VC1 - CSI0 VC1 line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC1_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC1_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC2_MASK (0x4U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC2_SHIFT (2U) /*! CSI0_VC2 - CSI0 VC2 line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC2_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC2_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC3_MASK (0x8U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC3_SHIFT (3U) /*! CSI0_VC3 - CSI0 VC3 line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC3_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC3_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC4_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC4_SHIFT (4U) /*! CSI0_VC4 - CSI0 VC4 line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC4_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC4_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC5_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC5_SHIFT (5U) /*! CSI0_VC5 - CSI0 VC5 line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC5_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC5_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC6_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC6_SHIFT (6U) /*! CSI0_VC6 - CSI0 VC6 line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC6_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC6_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC7_MASK (0x80U) #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC7_SHIFT (7U) /*! CSI0_VC7 - CSI0 VC7 line count mismatch * 0b1..Line count mismatch error * 0b0..No line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC7_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_VC_INTERLACED_ERROR_CSI0_VC7_MASK) /*! @} */ /*! @name CSI0_YUV420_FIRST_LINE_EVEN - CSI0 YUV420 First Line Even */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC0_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC0_SHIFT (0U) /*! VC0 - CSI0 VC0 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC0_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC0_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC1_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC1_SHIFT (1U) /*! VC1 - CSI0 VC1 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC1_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC1_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC2_MASK (0x4U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC2_SHIFT (2U) /*! VC2 - CSI0 VC2 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC2_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC2_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC3_MASK (0x8U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC3_SHIFT (3U) /*! VC3 - CSI0 VC3 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC3_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC3_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC4_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC4_SHIFT (4U) /*! VC4 - CSI0 VC4 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC4_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC4_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC5_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC5_SHIFT (5U) /*! VC5 - CSI0 VC5 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC5_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC5_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC6_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC6_SHIFT (6U) /*! VC6 - CSI0 VC6 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC6_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC6_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC7_MASK (0x80U) #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC7_SHIFT (7U) /*! VC7 - CSI0 VC7 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC7_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_YUV420_FIRST_LINE_EVEN_VC7_MASK) /*! @} */ /*! @name CSI0_RAW32_CTR - CSI0 RAW32 Control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC0_RAW32_MODE_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC0_RAW32_MODE_SHIFT (0U) /*! CSI0_VC0_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b1..VC is set in RAW32 mode * 0b0..VC is not set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC0_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC0_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC0_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC1_RAW32_MODE_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC1_RAW32_MODE_SHIFT (1U) /*! CSI0_VC1_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC1_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC1_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC1_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC2_RAW32_MODE_MASK (0x4U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC2_RAW32_MODE_SHIFT (2U) /*! CSI0_VC2_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC2_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC2_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC2_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC3_RAW32_MODE_MASK (0x8U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC3_RAW32_MODE_SHIFT (3U) /*! CSI0_VC3_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC3_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC3_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC3_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC4_RAW32_MODE_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC4_RAW32_MODE_SHIFT (4U) /*! CSI0_VC4_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC4_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC4_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC4_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC5_RAW32_MODE_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC5_RAW32_MODE_SHIFT (5U) /*! CSI0_VC5_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC5_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC5_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC5_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC6_RAW32_MODE_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC6_RAW32_MODE_SHIFT (6U) /*! CSI0_VC6_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC6_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC6_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC6_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC7_RAW32_MODE_MASK (0x80U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC7_RAW32_MODE_SHIFT (7U) /*! CSI0_VC7_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b1..VC is set in RAW32 mode * 0b0..VC is not set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC7_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC7_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_VC7_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_RAW_SWAP_MODE_MASK (0xFF00U) #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_RAW_SWAP_MODE_SHIFT (8U) /*! CSI0_RAW_SWAP_MODE - Defines if a virtual channel is set in RAW SWAP mode when index corresponding to the virtual channel is set to '1'. */ #define BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_RAW_SWAP_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_RAW_SWAP_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_RAW32_CTR_CSI0_RAW_SWAP_MODE_MASK) /*! @} */ /*! @name CSI0_STREAM_FENCING_CTRL - Stream fencing control. */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Fencing_Control_MASK (0xFFU) #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Fencing_Control_SHIFT (0U) /*! CSI0_Fencing_Control - [0] Fence VC0...[7] Fence VC7 */ #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Fencing_Control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Fencing_Control_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Fencing_Control_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Reset_Fencing_SM_MASK (0xFF00U) #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Reset_Fencing_SM_SHIFT (8U) /*! CSI0_Reset_Fencing_SM - SW reset of Fencing state machine. One per Virtual channel.[8] : Virtual channel 0...[15]: Virtual channel 7 */ #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Reset_Fencing_SM(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Reset_Fencing_SM_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_CTRL_CSI0_Reset_Fencing_SM_MASK) /*! @} */ /*! @name CSI0_STREAM_FENCING_STATUS - Stream fencing status. */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_STATUS_CSI0_Fencing_Status_MASK (0xFFU) #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_STATUS_CSI0_Fencing_Status_SHIFT (0U) /*! CSI0_Fencing_Status - Indicates when a virtual channel is fenced when set to '1'. [0] VC0 is fenced...[7] VC7 is fenced */ #define BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_STATUS_CSI0_Fencing_Status(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_STATUS_CSI0_Fencing_Status_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_STREAM_FENCING_STATUS_CSI0_Fencing_Status_MASK) /*! @} */ /*! @name CSI0_NP_data_type_VC - CSI0 VC0 non-pixel data type..CSI0 VC7 non-pixel data type */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC0_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC0_NP_data_type_en_SHIFT (0U) /*! CSI0_VC0_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC0_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC0_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC0_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC1_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC1_NP_data_type_en_SHIFT (0U) /*! CSI0_VC1_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC1_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC1_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC1_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC2_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC2_NP_data_type_en_SHIFT (0U) /*! CSI0_VC2_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC2_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC2_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC2_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC3_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC3_NP_data_type_en_SHIFT (0U) /*! CSI0_VC3_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC3_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC3_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC3_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC4_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC4_NP_data_type_en_SHIFT (0U) /*! CSI0_VC4_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC4_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC4_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC4_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC5_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC5_NP_data_type_en_SHIFT (0U) /*! CSI0_VC5_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC5_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC5_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC5_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC6_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC6_NP_data_type_en_SHIFT (0U) /*! CSI0_VC6_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC6_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC6_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC6_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC7_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC7_NP_data_type_en_SHIFT (0U) /*! CSI0_VC7_NP_data_type_en - Enables transport of non-pixel data on pixel link. */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC7_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC7_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_CSI0_VC7_NP_data_type_en_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC */ #define BLK_CTRL_CAMERAMIX_CSI0_NP_data_type_VC_COUNT (8U) /*! @name CSI0_Pixel_data_ctrl_VC - CSI0 Pixel Data Control VC0..CSI0 Pixel Data Control VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_Reroute_VC_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_Reroute_VC_SHIFT (0U) /*! Reroute_VC - Defines if the pixel data are routed to another VC or not * 0b0..Pixel data are not re-routed. * 0b1..Pixel are routed to VC defined by New_VC. */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_Reroute_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_Reroute_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_Reroute_VC_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_New_VC_MASK (0xEU) #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_New_VC_SHIFT (1U) /*! New_VC - Defines the virtual channel on which the pixel data are transported */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_New_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_New_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_New_VC_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_ctrl_VC_COUNT (8U) /*! @name CSI0_Route_Pixel_data_type_VC - CSI0 Route Pixel Data Type VC0..CSI0 Route Pixel Data Type VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_Others_MASK (0x1FFFU) #define BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_Others_SHIFT (0U) /*! Others - Route other pixel data type enable */ #define BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_Others(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_Others_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_Others_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_RAW_MASK (0xFF8000U) #define BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_RAW_SHIFT (15U) /*! RAW - Route RAW pixel data type enable */ #define BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_RAW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_RAW_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_RAW_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC */ #define BLK_CTRL_CAMERAMIX_CSI0_Route_Pixel_data_type_VC_COUNT (8U) /*! @name CSI0_Non_Pixel_data_ctrl_VC - CSI0 Non-Pixel Data Control VC0..CSI0 Non-Pixel Data Control VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_Reroute_VC_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_Reroute_VC_SHIFT (0U) /*! Reroute_VC - Defines if the non-pixel data are routed to another VC or not * 0b1..Non-pixel data are routed to VC defined by New_VC. * 0b0..Non-pixel data are not re-routed. */ #define BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_Reroute_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_Reroute_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_Reroute_VC_MASK) #define BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_New_VC_MASK (0xEU) #define BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_New_VC_SHIFT (1U) /*! New_VC - Defines the virtual channel on which the non-pixel data are transported */ #define BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_New_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_New_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_New_VC_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC */ #define BLK_CTRL_CAMERAMIX_CSI0_Non_Pixel_data_ctrl_VC_COUNT (8U) /*! @name CSI0_Pixel_data_type_VC - CSI0 Pixel Data Type VC0..CSI0 Pixel Data Type VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_VC_type_enable_MASK (0xFFFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_VC_type_enable_SHIFT (0U) /*! type_enable - Pixel data type enable */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_VC_type_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_VC_type_enable_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_VC_type_enable_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_VC */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_VC_COUNT (8U) /*! @name CSI0_Pixel_data_type_err_VC - CSI0 Pixel Data Type Error VC0..CSI0 Pixel Data Type Error VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_err_VC_type_error_MASK (0xFFFFFFU) #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_err_VC_type_error_SHIFT (0U) /*! type_error - Pixel data type error */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_err_VC_type_error(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_err_VC_type_error_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_err_VC_type_error_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_err_VC */ #define BLK_CTRL_CAMERAMIX_CSI0_Pixel_data_type_err_VC_COUNT (8U) /*! @name CSI1_VC_INTERLACED_LINE_COUNT_SET - Virtual Channel interlaced Line count */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_MASK (0x3FFFU) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_SHIFT (0U) /*! Odd_line_count - Odd line count */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Odd_line_count_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_MASK (0x3FFF0000U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_SHIFT (16U) /*! Even_line_count - Even line count */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Even_line_count(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_Even_line_count_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_LINE_COUNT_SET_COUNT (8U) /*! @name CSI1_VC_INTERLACED_CTRL - CSI1 VC Interlaced Control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC0_interlace_mode_MASK (0x3U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC0_interlace_mode_SHIFT (0U) /*! CSI1_VC0_interlace_mode - CSI1 VC0 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC0_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC0_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC0_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC1_interlace_mode_MASK (0xCU) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC1_interlace_mode_SHIFT (2U) /*! CSI1_VC1_interlace_mode - CSI1 VC1 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC1_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC1_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC1_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC2_interlace_mode_MASK (0x30U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC2_interlace_mode_SHIFT (4U) /*! CSI1_VC2_interlace_mode - CSI1 VC2 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC2_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC2_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC2_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC3_interlace_mode_MASK (0xC0U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC3_interlace_mode_SHIFT (6U) /*! CSI1_VC3_interlace_mode - CSI1 VC3 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC3_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC3_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC3_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC4_interlace_mode_MASK (0x300U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC4_interlace_mode_SHIFT (8U) /*! CSI1_VC4_interlace_mode - CSI1 VC4 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC4_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC4_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC4_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC5_interlace_mode_MASK (0xC00U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC5_interlace_mode_SHIFT (10U) /*! CSI1_VC5_interlace_mode - CSI1 VC5 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC5_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC5_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC5_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC6_interlace_mode_MASK (0x3000U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC6_interlace_mode_SHIFT (12U) /*! CSI1_VC6_interlace_mode - CSI1 VC6 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC6_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC6_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC6_interlace_mode_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC7_interlace_mode_MASK (0xC000U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC7_interlace_mode_SHIFT (14U) /*! CSI1_VC7_interlace_mode - CSI1 VC7 interlace mode * 0b00..Virtual Channel is not interlaced : pixel link interlaced/not control field is set 2b00 * 0b01..Virtual Channel is interlaced and generation done according to the CSI2 frame number * 0b10..Virtual Channel is interlaced and generation done according to the number of lines received during one frame * 0b11..Virtual Channel is interlaced. First received frame is considered as ODD. */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC7_interlace_mode(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC7_interlace_mode_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_CTRL_CSI1_VC7_interlace_mode_MASK) /*! @} */ /*! @name CSI1_VC_INTERLACED_ERROR - CSI1 VC Interlaced Error */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC0_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC0_SHIFT (0U) /*! CSI1_VC0 - CSI1 VC0 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC0_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC0_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC1_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC1_SHIFT (1U) /*! CSI1_VC1 - CSI1 VC1 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC1_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC1_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC2_MASK (0x4U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC2_SHIFT (2U) /*! CSI1_VC2 - CSI1 VC2 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC2_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC2_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC3_MASK (0x8U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC3_SHIFT (3U) /*! CSI1_VC3 - CSI1 VC3 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC3_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC3_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC4_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC4_SHIFT (4U) /*! CSI1_VC4 - CSI1 VC4 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC4_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC4_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC5_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC5_SHIFT (5U) /*! CSI1_VC5 - CSI1 VC5 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC5_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC5_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC6_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC6_SHIFT (6U) /*! CSI1_VC6 - CSI1 VC6 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC6_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC6_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC7_MASK (0x80U) #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC7_SHIFT (7U) /*! CSI1_VC7 - CSI1 VC7 Line count mismatch * 0b0..No line count mismatch error * 0b1..Line count mismatch error */ #define BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC7_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_VC_INTERLACED_ERROR_CSI1_VC7_MASK) /*! @} */ /*! @name CSI1_YUV420_FIRST_LINE_EVEN - CSI1 YUV420 First Line Even */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC0_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC0_SHIFT (0U) /*! VC0 - CSI1 VC0 first line even * 0b1..First line is EVEN * 0b0..First line is ODD */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC0_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC0_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC1_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC1_SHIFT (1U) /*! VC1 - CSI1 VC1 first line even */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC1_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC1_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC2_MASK (0x4U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC2_SHIFT (2U) /*! VC2 - CSI1 VC2 first line even * 0b1..First line is EVEN * 0b0..First line is ODD */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC2_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC2_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC3_MASK (0x8U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC3_SHIFT (3U) /*! VC3 - CSI1 VC3 first line even * 0b1..First line is EVEN * 0b0..First line is ODD */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC3_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC3_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC4_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC4_SHIFT (4U) /*! VC4 - CSI1 VC4 first line even * 0b1..First line is EVEN * 0b0..First line is ODD */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC4_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC4_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC5_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC5_SHIFT (5U) /*! VC5 - CSI1 VC5 first line even * 0b1..First line is EVEN * 0b0..First line is ODD */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC5_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC5_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC6_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC6_SHIFT (6U) /*! VC6 - CSI1 VC6 first line even * 0b1..First line is EVEN * 0b0..First line is ODD */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC6_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC6_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC7_MASK (0x80U) #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC7_SHIFT (7U) /*! VC7 - CSI1 VC7 first line even * 0b0..First line is ODD * 0b1..First line is EVEN */ #define BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC7_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_YUV420_FIRST_LINE_EVEN_VC7_MASK) /*! @} */ /*! @name CSI1_RAW32_CTR - CSI1 RAW32 Control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC0_RAW32_MODE_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC0_RAW32_MODE_SHIFT (0U) /*! CSI1_VC0_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC0_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC0_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC0_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC1_RAW32_MODE_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC1_RAW32_MODE_SHIFT (1U) /*! CSI1_VC1_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC1_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC1_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC1_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC2_RAW32_MODE_MASK (0x4U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC2_RAW32_MODE_SHIFT (2U) /*! CSI1_VC2_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC2_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC2_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC2_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC3_RAW32_MODE_MASK (0x8U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC3_RAW32_MODE_SHIFT (3U) /*! CSI1_VC3_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC3_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC3_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC3_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC4_RAW32_MODE_MASK (0x10U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC4_RAW32_MODE_SHIFT (4U) /*! CSI1_VC4_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC4_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC4_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC4_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC5_RAW32_MODE_MASK (0x20U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC5_RAW32_MODE_SHIFT (5U) /*! CSI1_VC5_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC5_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC5_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC5_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC6_RAW32_MODE_MASK (0x40U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC6_RAW32_MODE_SHIFT (6U) /*! CSI1_VC6_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC6_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC6_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC6_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC7_RAW32_MODE_MASK (0x80U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC7_RAW32_MODE_SHIFT (7U) /*! CSI1_VC7_RAW32_MODE - Defines if a virtual channel is set in RAW32 mode * 0b0..VC is not set in RAW32 mode * 0b1..VC is set in RAW32 mode */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC7_RAW32_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC7_RAW32_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_VC7_RAW32_MODE_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_RAW_SWAP_MODE_MASK (0xFF00U) #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_RAW_SWAP_MODE_SHIFT (8U) /*! CSI1_RAW_SWAP_MODE - Defines if a virtual channel is set in RAW SWAP mode when index corresponding to the virtual channel is set to '1'. */ #define BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_RAW_SWAP_MODE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_RAW_SWAP_MODE_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_RAW32_CTR_CSI1_RAW_SWAP_MODE_MASK) /*! @} */ /*! @name CSI1_STREAM_FENCING_CTRL - Stream fencing control. */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Fencing_Control_MASK (0xFFU) #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Fencing_Control_SHIFT (0U) /*! CSI1_Fencing_Control - [0] Fence VC0...[7] Fence VC7 */ #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Fencing_Control(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Fencing_Control_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Fencing_Control_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Reset_Fencing_SM_MASK (0xFF00U) #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Reset_Fencing_SM_SHIFT (8U) /*! CSI1_Reset_Fencing_SM - SW reset of Fencing state machine. One per Virtual channel.[8] : Virtual channel 0...[15]: Virtual channel 7 */ #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Reset_Fencing_SM(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Reset_Fencing_SM_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_CTRL_CSI1_Reset_Fencing_SM_MASK) /*! @} */ /*! @name CSI1_STREAM_FENCING_STATUS - Stream fencing status. */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_STATUS_CSI1_Fencing_Status_MASK (0xFFU) #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_STATUS_CSI1_Fencing_Status_SHIFT (0U) /*! CSI1_Fencing_Status - Indicates when a virtual channel is fenced when set to '1'. [0] VC0 is fenced...[7] VC7 is fenced */ #define BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_STATUS_CSI1_Fencing_Status(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_STATUS_CSI1_Fencing_Status_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_STREAM_FENCING_STATUS_CSI1_Fencing_Status_MASK) /*! @} */ /*! @name CSI1_NP_data_type_VC - CSI1 VC0 non-pixel data type..CSI1 VC7 non-pixel data type */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC0_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC0_NP_data_type_en_SHIFT (0U) /*! CSI1_VC0_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC0_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC0_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC0_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC1_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC1_NP_data_type_en_SHIFT (0U) /*! CSI1_VC1_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC1_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC1_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC1_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC2_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC2_NP_data_type_en_SHIFT (0U) /*! CSI1_VC2_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC2_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC2_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC2_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC3_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC3_NP_data_type_en_SHIFT (0U) /*! CSI1_VC3_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC3_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC3_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC3_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC4_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC4_NP_data_type_en_SHIFT (0U) /*! CSI1_VC4_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC4_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC4_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC4_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC5_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC5_NP_data_type_en_SHIFT (0U) /*! CSI1_VC5_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC5_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC5_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC5_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC6_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC6_NP_data_type_en_SHIFT (0U) /*! CSI1_VC6_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC6_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC6_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC6_NP_data_type_en_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC7_NP_data_type_en_MASK (0x3FFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC7_NP_data_type_en_SHIFT (0U) /*! CSI1_VC7_NP_data_type_en - Enables transport of non-pixel data on pixel link */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC7_NP_data_type_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC7_NP_data_type_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_CSI1_VC7_NP_data_type_en_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC */ #define BLK_CTRL_CAMERAMIX_CSI1_NP_data_type_VC_COUNT (8U) /*! @name CSI1_Pixel_data_ctrl_VC - Control of the routing of the pixel data on Pixel link virtual channel. */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_Reroute_VC_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_Reroute_VC_SHIFT (0U) #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_Reroute_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_Reroute_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_Reroute_VC_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_New_VC_MASK (0xEU) #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_New_VC_SHIFT (1U) /*! New_VC - Defines the virtual channel on which the pixel data are transported */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_New_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_New_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_New_VC_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_ctrl_VC_COUNT (8U) /*! @name CSI1_Route_Pixel_data_type_VC - CSI1 Route Pixel Data Type VC0..CSI1 Route Pixel Data Type VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_Others_MASK (0x1FFFU) #define BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_Others_SHIFT (0U) /*! Others - Route other pixel data type enable */ #define BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_Others(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_Others_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_Others_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_RAW_MASK (0xFF8000U) #define BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_RAW_SHIFT (15U) /*! RAW - Route RAW pixel data type enable */ #define BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_RAW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_RAW_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_RAW_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC */ #define BLK_CTRL_CAMERAMIX_CSI1_Route_Pixel_data_type_VC_COUNT (8U) /*! @name CSI1_Non_Pixel_data_ctrl_VC - CSI1 Non-Pixel Data Control VC0..CSI1 Non-Pixel Data Control VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_Reroute_VC_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_Reroute_VC_SHIFT (0U) /*! Reroute_VC - Defines if the non-pixel data are routed to another VC or not * 0b1..Non-pixel data are routed to VC defined by New_VC. * 0b0..Non-pixel data are not re-routed. */ #define BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_Reroute_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_Reroute_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_Reroute_VC_MASK) #define BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_New_VC_MASK (0xEU) #define BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_New_VC_SHIFT (1U) /*! New_VC - Defines the virtual channel on which the non-pixel data are transported */ #define BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_New_VC(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_New_VC_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_New_VC_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC */ #define BLK_CTRL_CAMERAMIX_CSI1_Non_Pixel_data_ctrl_VC_COUNT (8U) /*! @name CSI1_Pixel_data_type_VC - CSI1 Pixel Data Type VC0..CSI1 Pixel Data Type VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_VC_type_enable_MASK (0xFFFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_VC_type_enable_SHIFT (0U) /*! type_enable - Pixel data type enable */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_VC_type_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_VC_type_enable_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_VC_type_enable_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_VC */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_VC_COUNT (8U) /*! @name CSI1_Pixel_data_type_err_VC - CSI1 Pixel Data Type Error VC0..CSI1 Pixel Data Type Error VC7 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_err_VC_type_error_MASK (0xFFFFFFU) #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_err_VC_type_error_SHIFT (0U) /*! type_error - Pixel data type error */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_err_VC_type_error(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_err_VC_type_error_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_err_VC_type_error_MASK) /*! @} */ /* The count of BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_err_VC */ #define BLK_CTRL_CAMERAMIX_CSI1_Pixel_data_type_err_VC_COUNT (8U) /*! @name CSI0_PIXEL_LINK_RAW10_FORMAT - Pixel link RAW10 format */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_PIXEL_LINK_RAW10_FORMAT_RAW10P_MASK (0xFFU) #define BLK_CTRL_CAMERAMIX_CSI0_PIXEL_LINK_RAW10_FORMAT_RAW10P_SHIFT (0U) /*! RAW10P - RAW10P */ #define BLK_CTRL_CAMERAMIX_CSI0_PIXEL_LINK_RAW10_FORMAT_RAW10P(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_PIXEL_LINK_RAW10_FORMAT_RAW10P_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_PIXEL_LINK_RAW10_FORMAT_RAW10P_MASK) /*! @} */ /*! @name CSI1_PIXEL_LINK_RAW10_FORMAT - Pixel link RAW10 format */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_PIXEL_LINK_RAW10_FORMAT_RAW10P_MASK (0xFFU) #define BLK_CTRL_CAMERAMIX_CSI1_PIXEL_LINK_RAW10_FORMAT_RAW10P_SHIFT (0U) /*! RAW10P - RAW10P */ #define BLK_CTRL_CAMERAMIX_CSI1_PIXEL_LINK_RAW10_FORMAT_RAW10P(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_PIXEL_LINK_RAW10_FORMAT_RAW10P_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_PIXEL_LINK_RAW10_FORMAT_RAW10P_MASK) /*! @} */ /*! @name CSI0_BUFFER_OVERFLOW - Buffer Overflow */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI0_BUFFER_OVERFLOW_Buffer_Overflow_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI0_BUFFER_OVERFLOW_Buffer_Overflow_SHIFT (0U) /*! Buffer_Overflow - Set when the rate adaptation buffer overflows */ #define BLK_CTRL_CAMERAMIX_CSI0_BUFFER_OVERFLOW_Buffer_Overflow(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI0_BUFFER_OVERFLOW_Buffer_Overflow_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI0_BUFFER_OVERFLOW_Buffer_Overflow_MASK) /*! @} */ /*! @name CSI1_BUFFER_OVERFLOW - Buffer Overflow */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CSI1_BUFFER_OVERFLOW_Buffer_Overflow_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CSI1_BUFFER_OVERFLOW_Buffer_Overflow_SHIFT (0U) /*! Buffer_Overflow - Set when the rate adaptation buffer overflows */ #define BLK_CTRL_CAMERAMIX_CSI1_BUFFER_OVERFLOW_Buffer_Overflow(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CSI1_BUFFER_OVERFLOW_Buffer_Overflow_SHIFT)) & BLK_CTRL_CAMERAMIX_CSI1_BUFFER_OVERFLOW_Buffer_Overflow_MASK) /*! @} */ /*! @name CM0P_ADDR_OFFSET1 - Cortex-M0+ Address Offset 1 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET1_OFFSET_MASK (0xFFFFFF00U) #define BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET1_OFFSET_SHIFT (8U) /*! OFFSET - CM0P_ADDR_OFFSET1 */ #define BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET1_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET1_OFFSET_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET1_OFFSET_MASK) /*! @} */ /*! @name CM0P_ADDR_OFFSET2 - Cortex-M0+ Address Offset 2 */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET2_OFFSET_MASK (0xFFFFFF00U) #define BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET2_OFFSET_SHIFT (8U) /*! OFFSET - CM0P_ADDR_OFFSET2 */ #define BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET2_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET2_OFFSET_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_ADDR_OFFSET2_OFFSET_MASK) /*! @} */ /*! @name CM0P_CPUWAIT - Cortex-M0+ CPUWAIT */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_CPW_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_CPW_SHIFT (0U) /*! CPW - Controls CM0P CPUWAIT input signal * 0b0..Processor is running * 0b1..Processor is waiting */ #define BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_CPW(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_CPW_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_CPW_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_RST_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_RST_SHIFT (1U) /*! RST - Software reset of CM0P core and LPCAC * 0b0..CM0P logic is held in reset * 0b1..CM0P logic is not in reset */ #define BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_RST(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_RST_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CPUWAIT_RST_MASK) /*! @} */ /*! @name CM0P_CTL - Cortex-M0+ Control */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_ILT_MASK (0x3FCU) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_ILT_SHIFT (2U) /*! ILT - Controls the CM0Px IRQLATENCY[7:0] input */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_ILT(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_ILT_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_ILT_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_CLR_MASK (0x400U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_CLR_SHIFT (10U) /*! CLR - Clear LPCAC data cache (clr_lpcac) * 0b0..Disable clear of LPCAC data cache * 0b1..Enable clear LPCAC data cache */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_CLR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_CLR_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_CLR_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_NAL_MASK (0x800U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_NAL_SHIFT (11U) /*! NAL - Disable LPCAC data cache allocation (frc_no_alloc) * 0b0..Enable LPCAC data cache allocation * 0b1..Disable LPCAC data cache allocation (Bit DWB also needs to be set to '1') */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_NAL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_NAL_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_NAL_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_DWB_MASK (0x1000U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_DWB_SHIFT (12U) /*! DWB - Disable LPCAC write buffer (dis_lpcac_wtbf) * 0b0..Enable write buffer * 0b1..Disable write buffer */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_DWB(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_DWB_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_DWB_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_DIS_MASK (0x2000U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_DIS_SHIFT (13U) /*! DIS - Disable LPCAC (dis_lpcac) * 0b0..Enable LPCAC * 0b1..Disable LPCAC */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_DIS_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_DIS_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_Boot_MASK (0x8000U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_Boot_SHIFT (15U) /*! Boot - Boot source * 0b0..Boot from OCRAM_L * 0b1..Boot from DDR */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_Boot(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_Boot_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_Boot_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_lim_lpcac_wtbf_MASK (0x10000U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_lim_lpcac_wtbf_SHIFT (16U) /*! lim_lpcac_wtbf - Limit write buffer (lim_lpcac_wtbf) * 0b0..If write buffer is enabled, buffer all writes to spaces that are bufferable. * 0b1..If write buffer is enabled, buffer all writes to spaces that are both bufferable and cacheable. */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_lim_lpcac_wtbf(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_lim_lpcac_wtbf_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_lim_lpcac_wtbf_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_miss_en_MASK (0x20000U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_miss_en_SHIFT (17U) /*! parity_miss_en - Miss on error (parity_miss_en) * 0b0..Disable parity generation, parity checking, and recovery from parity faults * 0b1..Enable parity generation, parity checking, and recovery from parity faults */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_miss_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_miss_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_miss_en_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_fault_en_MASK (0x40000U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_fault_en_SHIFT (18U) /*! parity_fault_en - Enable parity error reporting * 0b0..Disable parity errors and parity error related information reporting * 0b1..Enable parity errors and parity error related information reporting */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_fault_en(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_fault_en_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_parity_fault_en_MASK) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_OCRAM__in_init_req_MASK (0x80000U) #define BLK_CTRL_CAMERAMIX_CM0P_CTL_OCRAM__in_init_req_SHIFT (19U) /*! OCRAM__in_init_req - OCRAM Initialization request */ #define BLK_CTRL_CAMERAMIX_CM0P_CTL_OCRAM__in_init_req(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_CTL_OCRAM__in_init_req_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_CTL_OCRAM__in_init_req_MASK) /*! @} */ /*! @name CM0P_STAT - Cortex-M0+ Status */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_CM0P_STAT_LKP_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_CM0P_STAT_LKP_SHIFT (0U) /*! LKP - CM0P LOCKUP output signal value * 0b0..Processor is not in lockup state * 0b1..Processor is in lockup state, as a result of an unrecoverable exception */ #define BLK_CTRL_CAMERAMIX_CM0P_STAT_LKP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_CM0P_STAT_LKP_SHIFT)) & BLK_CTRL_CAMERAMIX_CM0P_STAT_LKP_MASK) /*! @} */ /*! @name LPCAC_ERROR - LPCAC Error */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_PE_MASK (0x1U) #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_PE_SHIFT (0U) /*! CACHE_PE - Cache data parity error (cache_data_pe). Output of that register is connected to mix output signal 'lpcac_cache_data_pe' */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_PE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_PE_SHIFT)) & BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_PE_MASK) #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_WE_MASK (0x2U) #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_WE_SHIFT (1U) /*! CACHE_WE - Cache write-buffer error (cache_wb_error). Output of that register is connected to * mix output signal 'lpcac_cache_wb_error' */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_WE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_WE_SHIFT)) & BLK_CTRL_CAMERAMIX_LPCAC_ERROR_CACHE_WE_MASK) #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_BUSERR_MASK (0xCU) #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_BUSERR_SHIFT (2U) /*! BUSERR - Bus Error size. In case of Cache write-buffer error or Cache data parity error the * LPCAC. Be_size is latched in that register. */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_BUSERR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_LPCAC_ERROR_BUSERR_SHIFT)) & BLK_CTRL_CAMERAMIX_LPCAC_ERROR_BUSERR_MASK) /*! @} */ /*! @name LPCAC_ERROR_ADDR - LPCAC Error Address */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_ADDR_BUSERR_ADDR_MASK (0xFFFFFFFFU) #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_ADDR_BUSERR_ADDR_SHIFT (0U) /*! BUSERR_ADDR - In case of Cache write-buffer error or Cache data parity error the bus error address is latched in this register */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_ADDR_BUSERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_LPCAC_ERROR_ADDR_BUSERR_ADDR_SHIFT)) & BLK_CTRL_CAMERAMIX_LPCAC_ERROR_ADDR_BUSERR_ADDR_MASK) /*! @} */ /*! @name LPCAC_ERROR_DATA - LPCAC Error Data */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_DATA_BUSERR_DATA_MASK (0xFFFFFFFFU) #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_DATA_BUSERR_DATA_SHIFT (0U) /*! BUSERR_DATA - In case of Cache write-buffer error or Cache data parity error the bus error data is latched in this register */ #define BLK_CTRL_CAMERAMIX_LPCAC_ERROR_DATA_BUSERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_LPCAC_ERROR_DATA_BUSERR_DATA_SHIFT)) & BLK_CTRL_CAMERAMIX_LPCAC_ERROR_DATA_BUSERR_DATA_MASK) /*! @} */ /*! @name ISP_CONFIG - ISP Configuration */ /*! @{ */ #define BLK_CTRL_CAMERAMIX_ISP_CONFIG_Pixel_link_sel_MASK (0x3U) #define BLK_CTRL_CAMERAMIX_ISP_CONFIG_Pixel_link_sel_SHIFT (0U) /*! Pixel_link_sel - Select the pixel link connected to the ISP * 0b00..CSI Pixel Link 0 is connected to the ISP * 0b01..CSI Pixel Link 1 is connected to the ISP */ #define BLK_CTRL_CAMERAMIX_ISP_CONFIG_Pixel_link_sel(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_CAMERAMIX_ISP_CONFIG_Pixel_link_sel_SHIFT)) & BLK_CTRL_CAMERAMIX_ISP_CONFIG_Pixel_link_sel_MASK) /*! @} */ /*! * @} */ /* end of group BLK_CTRL_CAMERAMIX_Register_Masks */ /* BLK_CTRL_CAMERAMIX - Peripheral instance base addresses */ /** Peripheral BLK_CTRL_CAMERAMIX base address */ #define BLK_CTRL_CAMERAMIX_BASE (0x4AC10000u) /** Peripheral BLK_CTRL_CAMERAMIX base pointer */ #define BLK_CTRL_CAMERAMIX ((BLK_CTRL_CAMERAMIX_Type *)BLK_CTRL_CAMERAMIX_BASE) /** Array initializer of BLK_CTRL_CAMERAMIX peripheral base addresses */ #define BLK_CTRL_CAMERAMIX_BASE_ADDRS { BLK_CTRL_CAMERAMIX_BASE } /** Array initializer of BLK_CTRL_CAMERAMIX peripheral base pointers */ #define BLK_CTRL_CAMERAMIX_BASE_PTRS { BLK_CTRL_CAMERAMIX } /*! * @} */ /* end of group BLK_CTRL_CAMERAMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BLK_CTRL_NETCMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BLK_CTRL_NETCMIX_Peripheral_Access_Layer BLK_CTRL_NETCMIX Peripheral Access Layer * @{ */ /** BLK_CTRL_NETCMIX - Register Layout Typedef */ typedef struct { __IO uint32_t MQS_SETTING; /**< MQS Settings, offset: 0x0 */ __IO uint32_t NETCMIX_CLK_SEL; /**< NETC clock select, offset: 0x4 */ __IO uint32_t IPG_DEBUG_SAI2; /**< Each core's debug mode, offset: 0x8 */ __IO uint32_t CFG_LINK_IO_VAR; /**< NETC cfg_link_io_var, offset: 0xC */ __IO uint32_t CFG_LINK_MII_PROT; /**< NETC cfg_link_mii_prot, offset: 0x10 */ __IO uint32_t CFG_LINK_PCS_PROT_0; /**< NETC PCS protocol on link0, offset: 0x14 */ __IO uint32_t CFG_LINK_PCS_PROT_1; /**< NETC PCS protocol on link1, offset: 0x18 */ __IO uint32_t CFG_LINK_PCS_PROT_2; /**< NETC PCS protocol on link2, offset: 0x1C */ __IO uint32_t CFG_SRC_ID; /**< NETC cfg_src_id, offset: 0x20 */ } BLK_CTRL_NETCMIX_Type; /* ---------------------------------------------------------------------------- -- BLK_CTRL_NETCMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BLK_CTRL_NETCMIX_Register_Masks BLK_CTRL_NETCMIX Register Masks * @{ */ /*! @name MQS_SETTING - MQS Settings */ /*! @{ */ #define BLK_CTRL_NETCMIX_MQS_SETTING_SAI_SEL_MASK (0x3U) #define BLK_CTRL_NETCMIX_MQS_SETTING_SAI_SEL_SHIFT (0U) /*! SAI_SEL - SAI2 clock source selection * 0b01..Reserved * 0b00..Select clock source from SAI2 * 0b10..Reserved * 0b11..Reserved */ #define BLK_CTRL_NETCMIX_MQS_SETTING_SAI_SEL(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_MQS_SETTING_SAI_SEL_SHIFT)) & BLK_CTRL_NETCMIX_MQS_SETTING_SAI_SEL_MASK) #define BLK_CTRL_NETCMIX_MQS_SETTING_MQS_EN_MASK (0x4U) #define BLK_CTRL_NETCMIX_MQS_SETTING_MQS_EN_SHIFT (2U) /*! MQS_EN - MQS enable * 0b1..Enable MQS * 0b0..Disable MQS */ #define BLK_CTRL_NETCMIX_MQS_SETTING_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_MQS_SETTING_MQS_EN_SHIFT)) & BLK_CTRL_NETCMIX_MQS_SETTING_MQS_EN_MASK) #define BLK_CTRL_NETCMIX_MQS_SETTING_SOFT_RESET_MASK (0x8U) #define BLK_CTRL_NETCMIX_MQS_SETTING_SOFT_RESET_SHIFT (3U) /*! SOFT_RESET - MQS software reset * 0b0..Exit software reset for MQS * 0b1..Enable software reset for MQS */ #define BLK_CTRL_NETCMIX_MQS_SETTING_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_MQS_SETTING_SOFT_RESET_SHIFT)) & BLK_CTRL_NETCMIX_MQS_SETTING_SOFT_RESET_MASK) #define BLK_CTRL_NETCMIX_MQS_SETTING_OVERSAMPLE_MASK (0x10U) #define BLK_CTRL_NETCMIX_MQS_SETTING_OVERSAMPLE_SHIFT (4U) /*! OVERSAMPLE - Controls the PWM oversampling rate compared with MCLK. * 0b0..32 * 0b1..64 */ #define BLK_CTRL_NETCMIX_MQS_SETTING_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_MQS_SETTING_OVERSAMPLE_SHIFT)) & BLK_CTRL_NETCMIX_MQS_SETTING_OVERSAMPLE_MASK) #define BLK_CTRL_NETCMIX_MQS_SETTING_CLK_DIVIDE_MASK (0x1FE00U) #define BLK_CTRL_NETCMIX_MQS_SETTING_CLK_DIVIDE_SHIFT (9U) /*! CLK_DIVIDE - Clock divide factor configuration */ #define BLK_CTRL_NETCMIX_MQS_SETTING_CLK_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_MQS_SETTING_CLK_DIVIDE_SHIFT)) & BLK_CTRL_NETCMIX_MQS_SETTING_CLK_DIVIDE_MASK) /*! @} */ /*! @name NETCMIX_CLK_SEL - NETC clock select */ /*! @{ */ #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK1_MASK (0x1U) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK1_SHIFT (0U) /*! SAI2_MCLK1 - SAI2 MCLK1 clock root select * 0b0..SAI2_CLK_ROOT * 0b1..SAI2_IPP_IND_SAI_MCLK */ #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK1_SHIFT)) & BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK1_MASK) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK2_MASK (0x1EU) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK2_SHIFT (1U) /*! SAI2_MCLK2 - SAI2 MCLK2 clock root select * 0b1100..Reserved * 0b0001..SAI2_CLK_ROOT * 0b0010..SAI3_CLK_ROOT * 0b0000..SAI1_CLK_ROOT * 0b0011..SAI4_CLK_ROOT * 0b0100..SAI5_CLK_ROOT * 0b0110..Reserved * 0b0101..Reserved * 0b1101..Reserved * 0b1111..SPDIF_RX_ROOT * 0b0111..SAI1_IPP_IND_SAI_MCLK * 0b1000..SAI2_IPP_IND_SAI_MCLK * 0b1001..SAI3_IPP_IND_SAI_MCLK * 0b1010..Reserved * 0b1110..SPDIF_CLK_ROOT * 0b1011..Reserved */ #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK2_SHIFT)) & BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK2_MASK) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET1_TD2_DIR_MASK (0x20U) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET1_TD2_DIR_SHIFT (5U) /*! ENET1_TD2_DIR - ENET1_TD2 direction * 0b0..ENET1_TD2 set as ETH0_RMII_REF50_CLK input (RMII clock from PHY) * 0b1..ENET1_TD2 set as ENET_REF_CLK_ROOT output (RMII clock to PHY) */ #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET1_TD2_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET1_TD2_DIR_SHIFT)) & BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET1_TD2_DIR_MASK) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK3_MASK (0x3C0U) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK3_SHIFT (6U) /*! SAI2_MCLK3 - SAI2 MCLK3 clock root select * 0b1111..SPDIF_RX_ROOT * 0b1110..SPDIF_CLK_ROOT * 0b1101..Reserved * 0b1100..Reserved * 0b1011..Reserved * 0b1010..Reserved * 0b1001..SAI3_IPP_IND_SAI_MCLK * 0b1000..SAI2_IPP_IND_SAI_MCLK * 0b0111..SAI1_IPP_IND_SAI_MCLK * 0b0110..Reserved * 0b0101..Reserved * 0b0100..SAI5_CLK_ROOT * 0b0011..SAI4_CLK_ROOT * 0b0010..SAI3_CLK_ROOT * 0b0001..SAI2_CLK_ROOT * 0b0000..SAI1_CLK_ROOT */ #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK3_SHIFT)) & BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_SAI2_MCLK3_MASK) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET2_TD2_DIR_MASK (0x400U) #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET2_TD2_DIR_SHIFT (10U) /*! ENET2_TD2_DIR - ENET2_TD2 direction * 0b0..ENET2_TD2 set as ETH1_RMII_REF50_CLK input (RMII clock from PHY) * 0b1..ENET2_TD2 set as ENET_REF_CLK_ROOT output (RMII clock to PHY) */ #define BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET2_TD2_DIR(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET2_TD2_DIR_SHIFT)) & BLK_CTRL_NETCMIX_NETCMIX_CLK_SEL_ENET2_TD2_DIR_MASK) /*! @} */ /*! @name IPG_DEBUG_SAI2 - Each core's debug mode */ /*! @{ */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE0_MASK (0x1U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE0_SHIFT (0U) /*! IPG_DEBUG_CA55_CORE0 - CA55 core0 in debug mode * 0b0..Core does not enter debug mode * 0b1..Core enters debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE0_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE0_MASK) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE1_MASK (0x2U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE1_SHIFT (1U) /*! IPG_DEBUG_CA55_CORE1 - CA55 core1 in debug mode * 0b1..Core enters debug mode * 0b0..Core does not enter debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE1_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE1_MASK) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE2_MASK (0x4U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE2_SHIFT (2U) /*! IPG_DEBUG_CA55_CORE2 - CA55 core2 in debug mode * 0b1..Core enters debug mode * 0b0..Core does not enter debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE2_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE2_MASK) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE3_MASK (0x8U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE3_SHIFT (3U) /*! IPG_DEBUG_CA55_CORE3 - CA55 core3 in debug mode * 0b1..Core enters debug mode * 0b0..Core does not enter debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE3_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE3_MASK) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE4_MASK (0x10U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE4_SHIFT (4U) /*! IPG_DEBUG_CA55_CORE4 - CA55 core4 in debug mode * 0b1..Core enters debug mode * 0b0..Core does not enter debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE4_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE4_MASK) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE5_MASK (0x20U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE5_SHIFT (5U) /*! IPG_DEBUG_CA55_CORE5 - CA55 core5 in debug mode * 0b1..Core enters debug mode * 0b0..Core does not enter debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE5_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CA55_CORE5_MASK) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CM33_MASK (0x40U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CM33_SHIFT (6U) /*! IPG_DEBUG_CM33 - CM33 in debug mode * 0b1..Core enters debug mode * 0b0..Core does not enter debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CM33(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CM33_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_CM33_MASK) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_M7_MASK (0x80U) #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_M7_SHIFT (7U) /*! IPG_DEBUG_M7 - M7 in debug mode * 0b1..Core enters debug mode * 0b0..Core does not enter debug mode */ #define BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_M7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_M7_SHIFT)) & BLK_CTRL_NETCMIX_IPG_DEBUG_SAI2_IPG_DEBUG_M7_MASK) /*! @} */ /*! @name CFG_LINK_IO_VAR - NETC cfg_link_io_var */ /*! @{ */ #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_0_MASK (0xFU) #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_0_SHIFT (0U) /*! CFG_LINK_IO_VAR_0 - I/O variant supported by SoC on link 0 * 0b0000..None * 0b0001..16FF 16G SerDes */ #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_0_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_0_MASK) #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_1_MASK (0xF0U) #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_1_SHIFT (4U) /*! CFG_LINK_IO_VAR_1 - I/O variant supported by SoC on link 1 * 0b0001..16FF 16G SerDes * 0b0000..None */ #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_1_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_1_MASK) #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_2_MASK (0xF00U) #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_2_SHIFT (8U) /*! CFG_LINK_IO_VAR_2 - I/O variant supported by SoC on link 2 * 0b0001..16FF 16G SerDes * 0b0000..None */ #define BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_2_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_IO_VAR_CFG_LINK_IO_VAR_2_MASK) /*! @} */ /*! @name CFG_LINK_MII_PROT - NETC cfg_link_mii_prot */ /*! @{ */ #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_0_MASK (0xFU) #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_0_SHIFT (0U) /*! CFG_LINK_MII_PROT_0 - NETC MII protocol on link0 * 0b0000..MII * 0b0001..RMII * 0b0010..RGMII * 0b0100..SGMII * 0b0101..XGMII * 0b0110..Reserved * 0b0111..Reserved * 0b0011..Reserved * 0b1000..Reserved * 0b1001..Reserved * 0b1010..Reserved * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_0_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_0_MASK) #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_1_MASK (0xF0U) #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_1_SHIFT (4U) /*! CFG_LINK_MII_PROT_1 - NETC MII protocol on link1 * 0b1111..Reserved * 0b1110..Reserved * 0b1101..Reserved * 0b1100..Reserved * 0b1011..Reserved * 0b1010..Reserved * 0b1001..Reserved * 0b1000..Reserved * 0b0111..Reserved * 0b0110..Reserved * 0b0101..XGMII * 0b0100..SGMII * 0b0011..Reserved * 0b0010..RGMII * 0b0001..RMII * 0b0000..MII */ #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_1_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_1_MASK) #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_2_MASK (0xF00U) #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_2_SHIFT (8U) /*! CFG_LINK_MII_PROT_2 - NETC MII protocol on link2 * 0b1111..Reserved * 0b1110..Reserved * 0b1101..Reserved * 0b1100..Reserved * 0b1011..Reserved * 0b1010..Reserved * 0b1001..Reserved * 0b1000..Reserved * 0b0111..Reserved * 0b0110..Reserved * 0b0101..XGMII * 0b0100..SGMII * 0b0011..Reserved * 0b0010..RGMII * 0b0001..RMII * 0b0000..MII */ #define BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_2_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_MII_PROT_CFG_LINK_MII_PROT_2_MASK) /*! @} */ /*! @name CFG_LINK_PCS_PROT_0 - NETC PCS protocol on link0 */ /*! @{ */ #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_0_CFG_LINK_PCS_PROT_0_MASK (0xFFFFU) #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_0_CFG_LINK_PCS_PROT_0_SHIFT (0U) /*! CFG_LINK_PCS_PROT_0 - PCS protocol on link0 */ #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_0_CFG_LINK_PCS_PROT_0(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_0_CFG_LINK_PCS_PROT_0_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_0_CFG_LINK_PCS_PROT_0_MASK) /*! @} */ /*! @name CFG_LINK_PCS_PROT_1 - NETC PCS protocol on link1 */ /*! @{ */ #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_1_CFG_LINK_PCS_PROT_1_MASK (0xFFFFU) #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_1_CFG_LINK_PCS_PROT_1_SHIFT (0U) /*! CFG_LINK_PCS_PROT_1 - PCS protocol on link1 */ #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_1_CFG_LINK_PCS_PROT_1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_1_CFG_LINK_PCS_PROT_1_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_1_CFG_LINK_PCS_PROT_1_MASK) /*! @} */ /*! @name CFG_LINK_PCS_PROT_2 - NETC PCS protocol on link2 */ /*! @{ */ #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_2_CFG_LINK_PCS_PROT_2_MASK (0xFFFFU) #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_2_CFG_LINK_PCS_PROT_2_SHIFT (0U) /*! CFG_LINK_PCS_PROT_2 - PCS protocol on link2 */ #define BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_2_CFG_LINK_PCS_PROT_2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_2_CFG_LINK_PCS_PROT_2_SHIFT)) & BLK_CTRL_NETCMIX_CFG_LINK_PCS_PROT_2_CFG_LINK_PCS_PROT_2_MASK) /*! @} */ /*! @name CFG_SRC_ID - NETC cfg_src_id */ /*! @{ */ #define BLK_CTRL_NETCMIX_CFG_SRC_ID_CFG_SRC_ID_MASK (0xFFU) #define BLK_CTRL_NETCMIX_CFG_SRC_ID_CFG_SRC_ID_SHIFT (0U) /*! CFG_SRC_ID - NETC cfgsrc_id */ #define BLK_CTRL_NETCMIX_CFG_SRC_ID_CFG_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_NETCMIX_CFG_SRC_ID_CFG_SRC_ID_SHIFT)) & BLK_CTRL_NETCMIX_CFG_SRC_ID_CFG_SRC_ID_MASK) /*! @} */ /*! * @} */ /* end of group BLK_CTRL_NETCMIX_Register_Masks */ /* BLK_CTRL_NETCMIX - Peripheral instance base addresses */ /** Peripheral BLK_CTRL_NETCMIX base address */ #define BLK_CTRL_NETCMIX_BASE (0x4C810000u) /** Peripheral BLK_CTRL_NETCMIX base pointer */ #define BLK_CTRL_NETCMIX ((BLK_CTRL_NETCMIX_Type *)BLK_CTRL_NETCMIX_BASE) /** Array initializer of BLK_CTRL_NETCMIX peripheral base addresses */ #define BLK_CTRL_NETCMIX_BASE_ADDRS { BLK_CTRL_NETCMIX_BASE } /** Array initializer of BLK_CTRL_NETCMIX peripheral base pointers */ #define BLK_CTRL_NETCMIX_BASE_PTRS { BLK_CTRL_NETCMIX } /*! * @} */ /* end of group BLK_CTRL_NETCMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BLK_CTRL_WAKEUPMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer BLK_CTRL_WAKEUPMIX Peripheral Access Layer * @{ */ /** BLK_CTRL_WAKEUPMIX - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[24]; __I uint32_t EARC_PLL_STATUS; /**< EARC Audio PLL status bits, offset: 0x18 */ __IO uint32_t SAI_CLK_SEL; /**< sai3~5 mclk1~3 clk root mux settings, offset: 0x1C */ __I uint32_t VOLT_DETECT; /**< Voltage detectors output, offset: 0x20 */ uint8_t RESERVED_1[4]; __IO uint32_t AXI_ATTR_CFG; /**< AXI CACHE CONTROL BIT, offset: 0x28 */ __IO uint32_t IPG_DEBUG_CM33; /**< IPG DEBUG mask bit, offset: 0x2C */ __IO uint32_t IPG_DEBUG_CA55C0; /**< IPG DEBUG mask bit for CA55 core0, offset: 0x30 */ __IO uint32_t IPG_DEBUG_CA55C1; /**< IPG DEBUG mask bit for CA55 core1, offset: 0x34 */ __IO uint32_t IPG_DEBUG_CA55C2; /**< IPG DEBUG mask bit for CA55 core2, offset: 0x38 */ __IO uint32_t IPG_DEBUG_CA55C3; /**< IPG DEBUG mask bit for CA55 core3, offset: 0x3C */ __IO uint32_t IPG_DEBUG_CA55C4; /**< IPG DEBUG mask bit for CA55 core4, offset: 0x40 */ __IO uint32_t IPG_DEBUG_CA55C5; /**< IPG DEBUG mask bit for CA55 core5, offset: 0x44 */ __IO uint32_t IPG_DEBUG_CM7; /**< IPG DEBUG mask bit, offset: 0x48 */ __IO uint32_t IPG_DEBUG_2_CM33; /**< IPG DEBUG mask bit, offset: 0x4C */ __IO uint32_t IPG_DEBUG_2_CA55C0; /**< IPG DEBUG mask bit for CA55 core0, offset: 0x50 */ __IO uint32_t IPG_DEBUG_2_CA55C1; /**< IPG DEBUG mask bit for CA55 core1, offset: 0x54 */ __IO uint32_t IPG_DEBUG_2_CA55C2; /**< IPG DEBUG mask bit for CA55 core2, offset: 0x58 */ __IO uint32_t IPG_DEBUG_2_CA55C3; /**< IPG DEBUG mask bit for CA55 core3, offset: 0x5C */ __IO uint32_t IPG_DEBUG_2_CA55C4; /**< IPG DEBUG mask bit for CA55 core4, offset: 0x60 */ __IO uint32_t IPG_DEBUG_2_CA55C5; /**< IPG DEBUG mask bit for CA55 core5, offset: 0x64 */ __IO uint32_t IPG_DEBUG_2_CM7; /**< IPG DEBUG mask bit, offset: 0x68 */ uint8_t RESERVED_2[4]; __IO uint32_t DBG_TRACE_CTL; /**< DEBUG TRACE control, offset: 0x70 */ uint8_t RESERVED_3[16]; __IO uint32_t SMMU_TBU_IRQ_SETUP; /**< SMMU TBU IRQ resynchronization setup, offset: 0x84 */ uint8_t RESERVED_4[4]; __IO uint32_t INITIATOR_TIMEOUT; /**< NOC initiator timeout status, offset: 0x8C */ __IO uint32_t NIU_TO_MA0; /**< Timeout Control for NOC main NIU master m_a_0, offset: 0x90 */ __IO uint32_t NIU_TO_MA1; /**< Timeout Control for NOC main NIU master m_a_1x, offset: 0x94 */ __IO uint32_t NIU_TO_MA2; /**< Timeout Control for NOC main NIU master m_a_2, offset: 0x98 */ __IO uint32_t NIU_TO_MD0; /**< Timeout Control for NOC mega NIU master m_d_0, offset: 0x9C */ __IO uint32_t NIU_TO_MD1; /**< Timeout Control for NOC mega NIU master m_d_1, offset: 0xA0 */ __IO uint32_t NIU_TO_MD2; /**< Timeout Control for NOC mega NIU master m_d_2, offset: 0xA4 */ __IO uint32_t NIU_TO_MD3; /**< Timeout Control for NOC mega NIU master m_d_3, offset: 0xA8 */ __IO uint32_t NIU_TO_MD4; /**< Timeout Control for NOC mega NIU master m_d_4, offset: 0xAC */ __IO uint32_t NIU_TO_MD5; /**< Timeout Control for NOC mega NIU master m_d_5, offset: 0xB0 */ __IO uint32_t NIU_TO_MD6; /**< Timeout Control for NOC mega NIU master m_d_6, offset: 0xB4 */ __IO uint32_t NIU_TO_MD7; /**< Timeout Control for NOC mega NIU master m_d_7, offset: 0xB8 */ __IO uint32_t NIU_TO_MD8; /**< Timeout Control for NOC mega NIU master m_d_8, offset: 0xBC */ __IO uint32_t NIU_TO_MD9; /**< Timeout Control for NOC mega NIU master m_d_9, offset: 0xC0 */ uint8_t RESERVED_5[12]; __IO uint32_t IPG_STOP_CTL_0; /**< IPG_STOP control register 0, offset: 0xD0 */ __I uint32_t IPG_STOP_ACK_STATUS_0; /**< IPG_STOP_ACK status 0, offset: 0xD4 */ __IO uint32_t IPG_DOZE_CTL_0; /**< IPG_DOZE control 0, offset: 0xD8 */ uint32_t IPG_WAIT_CTL_0; /**< IPG_WAIT control 0, offset: 0xDC */ __IO uint32_t IPG_STOP_CTL_1; /**< IPG_STOP control register 1, offset: 0xE0 */ uint32_t IPG_STOP_ACK_STATUS_1; /**< IPG_STOP_ACK status 1, offset: 0xE4 */ __IO uint32_t IPG_DOZE_CTL_1; /**< IPG_DOZE control 1, offset: 0xE8 */ __IO uint32_t IPG_WAIT_CTL_1; /**< IPG_WAIT control 1, offset: 0xEC */ uint8_t RESERVED_6[16]; __IO uint32_t QREQ_CTL_0; /**< QREQ control register 0, offset: 0x100 */ __I uint32_t QACCEPT_STATUS_0; /**< QACCEPT status register 0, offset: 0x104 */ __I uint32_t QDENY_STATUS_0; /**< QDENY status register 0, offset: 0x108 */ __I uint32_t QACTIVE_STATUS_0; /**< QACTIVE status register 0, offset: 0x10C */ __IO uint32_t QREQ_CTL_1; /**< QREQ control register 1, offset: 0x110 */ __I uint32_t QACCEPT_STATUS_1; /**< QACCEPT status register 1, offset: 0x114 */ __I uint32_t QDENY_STATUS_1; /**< QDENY status register 1, offset: 0x118 */ __I uint32_t QACTIVE_STATUS_1; /**< QACTIVE status register 1, offset: 0x11C */ __IO uint32_t QREQ_CTL_2; /**< QREQ control register 2, offset: 0x120 */ __I uint32_t QACCEPT_STATUS_2; /**< QACCEPT status register 2, offset: 0x124 */ __I uint32_t QDENY_STATUS_2; /**< QDENY status register 2, offset: 0x128 */ __I uint32_t QACTIVE_STATUS_2; /**< QACTIVE status register 2, offset: 0x12C */ __IO uint32_t QREQ_CTL_3; /**< QREQ control register 3, offset: 0x130 */ __I uint32_t QACCEPT_STATUS_3; /**< QACCEPT status register 1, offset: 0x134 */ __I uint32_t QDENY_STATUS_3; /**< QDENY status register 3, offset: 0x138 */ __I uint32_t QACTIVE_STATUS_3; /**< QACTIVE status register 3, offset: 0x13C */ } BLK_CTRL_WAKEUPMIX_Type; /* ---------------------------------------------------------------------------- -- BLK_CTRL_WAKEUPMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BLK_CTRL_WAKEUPMIX_Register_Masks BLK_CTRL_WAKEUPMIX Register Masks * @{ */ /*! @name EARC_PLL_STATUS - EARC Audio PLL status bits */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lock_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lock_SHIFT (0U) /*! earc_pll_lock - EARC AUDIO PLL lock status */ #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lock(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lock_SHIFT)) & BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lock_MASK) #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lol_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lol_SHIFT (1U) /*! earc_pll_lol - EARC AUDIO PLL loss of lock status */ #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lol(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lol_SHIFT)) & BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_lol_MASK) #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_powerup_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_powerup_SHIFT (2U) /*! earc_pll_powerup - EARC AUDIO PLL powerup status */ #define BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_powerup(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_powerup_SHIFT)) & BLK_CTRL_WAKEUPMIX_EARC_PLL_STATUS_earc_pll_powerup_MASK) /*! @} */ /*! @name SAI_CLK_SEL - sai3~5 mclk1~3 clk root mux settings */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_SHIFT (0U) /*! SAI3_MCLK1 - SAI3 master clock 1 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK1_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_MASK (0x1EU) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_SHIFT (1U) /*! SAI3_MCLK2 - SAI3 master clock 2 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK2_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_MASK (0x1E0U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_SHIFT (5U) /*! SAI3_MCLK3 - SAI3 master clock 3 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI3_MCLK3_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK1_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK1_SHIFT (9U) /*! SAI4_MCLK1 - SAI4 master clock 1 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK1_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK1_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK2_MASK (0x3C00U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK2_SHIFT (10U) /*! SAI4_MCLK2 - SAI4 master clock 2 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK2_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK2_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK3_MASK (0x3C000U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK3_SHIFT (14U) /*! SAI4_MCLK3 - SAI4 master clock 3 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK3_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI4_MCLK3_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK1_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK1_SHIFT (18U) /*! SAI5_MCLK1 - SAI5 master clock 1 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK1_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK1_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK2_MASK (0x780000U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK2_SHIFT (19U) /*! SAI5_MCLK2 - SAI5 master clock 2 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK2_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK2_MASK) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK3_MASK (0x7800000U) #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK3_SHIFT (23U) /*! SAI5_MCLK3 - SAI5 master clock 3 source selection */ #define BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK3_SHIFT)) & BLK_CTRL_WAKEUPMIX_SAI_CLK_SEL_SAI5_MCLK3_MASK) /*! @} */ /*! @name VOLT_DETECT - Voltage detectors output */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_AON_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_AON_SHIFT (0U) /*! supply_detector_AON - Voltage detectors output of AON */ #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_AON(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_AON_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_AON_MASK) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_GPIO_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_GPIO_SHIFT (1U) /*! supply_detector_GPIO - Voltage detectors output of GPIO */ #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_GPIO(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_GPIO_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_GPIO_MASK) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_SD2_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_SD2_SHIFT (2U) /*! supply_detector_SD2 - Voltage detectors output of SD2 */ #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_SD2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_SD2_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_SD2_MASK) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_WAKEUP_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_WAKEUP_SHIFT (3U) /*! supply_detector_WAKEUP - Voltage detectors output of WAKEUP */ #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_WAKEUP_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_WAKEUP_MASK) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_CCM_DAP_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_CCM_DAP_SHIFT (4U) /*! supply_detector_CCM_DAP - Voltage detectors output of CCM DAP */ #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_CCM_DAP(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_CCM_DAP_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_CCM_DAP_MASK) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_ENET_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_ENET_SHIFT (5U) /*! supply_detector_ENET - Voltage detectors output of ENET */ #define BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_ENET(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_ENET_SHIFT)) & BLK_CTRL_WAKEUPMIX_VOLT_DETECT_supply_detector_ENET_MASK) /*! @} */ /*! @name AXI_ATTR_CFG - AXI CACHE CONTROL BIT */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc1_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc1_SHIFT (0U) /*! arcache_usdhc1 - Static value of arcache[1] = CACHEABLE (C) for AXI initiator usdhc1 * 0b1..Cacheable reads * 0b0..Non-cacheable reads */ #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc1_MASK) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc1_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc1_SHIFT (1U) /*! awcache_usdhc1 - Static value of awcache[1] = CACHEABLE (C) for AXI initiator usdhc1 * 0b1..Cacheable writes * 0b0..Non-cacheable writes */ #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc1_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc1_MASK) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc2_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc2_SHIFT (2U) /*! arcache_usdhc2 - Static value of arcache[1] = CACHEABLE (C) for AXI initiator usdhc2 * 0b1..Cacheable reads * 0b0..Non-cacheable reads */ #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc2_MASK) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc2_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc2_SHIFT (3U) /*! awcache_usdhc2 - Static value of awcache[1] = CACHEABLE (C) for AXI initiator usdhc2 * 0b1..Cacheable writes * 0b0..Non-cacheable writes */ #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc2_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc2_MASK) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc3_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc3_SHIFT (4U) /*! arcache_usdhc3 - Static value of arcache[1] = CACHEABLE (C) for AXI initiator usdhc3 * 0b1..Cacheable reads * 0b0..Non-cacheable reads */ #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc3_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_arcache_usdhc3_MASK) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc3_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc3_SHIFT (5U) /*! awcache_usdhc3 - Static value of awcache[1] = CACHEABLE (C) for AXI initiator usdhc3 * 0b1..Cacheable writes * 0b0..Non-cacheable writes */ #define BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc3_SHIFT)) & BLK_CTRL_WAKEUPMIX_AXI_ATTR_CFG_awcache_usdhc3_MASK) /*! @} */ /*! @name IPG_DEBUG_CM33 - IPG DEBUG mask bit */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM33_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C0 - IPG DEBUG mask bit for CA55 core0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C0_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C1 - IPG DEBUG mask bit for CA55 core1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C1_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C2 - IPG DEBUG mask bit for CA55 core2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C2_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C3 - IPG DEBUG mask bit for CA55 core3 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C3_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C4 - IPG DEBUG mask bit for CA55 core4 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C4_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_CA55C5 - IPG DEBUG mask bit for CA55 core5 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CA55C5_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_CM7 - IPG DEBUG mask bit */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can2_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can2_SHIFT (0U) /*! can2 - CAN2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can3_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can3_SHIFT (1U) /*! can3 - CAN3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can4_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can4_SHIFT (2U) /*! can4 - CAN4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can5_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can5_SHIFT (3U) /*! can5 - CAN5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_can5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio1_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio1_SHIFT (4U) /*! flexio1 - FlexIO1 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio1(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio1_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio1_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio2_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio2_SHIFT (5U) /*! flexio2 - FlexIO2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_flexio2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c3_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c3_SHIFT (6U) /*! lpi2c3 - I2C3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c4_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c4_SHIFT (7U) /*! lpi2c4 - I2C4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c5_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c5_SHIFT (8U) /*! lpi2c5 - I2C5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c6_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c6_SHIFT (9U) /*! lpi2c6 - I2C6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c7_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c7_SHIFT (10U) /*! lpi2c7 - I2C7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c8_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c8_SHIFT (11U) /*! lpi2c8 - I2C8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpi2c8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpit2_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpit2_SHIFT (12U) /*! lpit2 - IT2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpit2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpit2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpit2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi3_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi3_SHIFT (13U) /*! lpspi3 - SPI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi4_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi4_SHIFT (14U) /*! lpspi4 - SPI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi5_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi5_SHIFT (15U) /*! lpspi5 - SPI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi6_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi6_SHIFT (16U) /*! lpspi6 - SPI6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi7_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi7_SHIFT (17U) /*! lpspi7 - SPI7 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi7(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi7_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi7_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi8_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi8_SHIFT (18U) /*! lpspi8 - SPI8 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi8(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi8_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lpspi8_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lptmr2_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lptmr2_SHIFT (19U) /*! lptmr2 - TMR2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lptmr2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lptmr2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_lptmr2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm3_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm3_SHIFT (20U) /*! tpm3 - TPM3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm4_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm4_SHIFT (21U) /*! tpm4 - TPM4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm5_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm5_SHIFT (22U) /*! tpm5 - TPM5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm6_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm6_SHIFT (23U) /*! tpm6 - TPM6 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm6(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm6_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_tpm6_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog3_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog3_SHIFT (24U) /*! wdog3 - WDOG3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog4_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog4_SHIFT (25U) /*! wdog4 - WDOG4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog5_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog5_SHIFT (26U) /*! wdog5 - WDOG5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_wdog5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_i3c2_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_i3c2_SHIFT (27U) /*! i3c2 - I3C2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_i3c2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_i3c2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_i3c2_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai3_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai3_SHIFT (28U) /*! sai3 - SAI3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai3_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai4_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai4_SHIFT (29U) /*! sai4 - SAI4 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai4(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai4_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai4_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai5_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai5_SHIFT (30U) /*! sai5 - SAI5 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai5(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai5_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_sai5_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_edma2_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_edma2_SHIFT (31U) /*! edma2 - EDMA2 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_edma2(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_edma2_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_CM7_edma2_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CM33 - IPG DEBUG mask bit */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM33_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM33_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM33_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM33_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM33_edma3_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CA55C0 - IPG DEBUG mask bit for CA55 core0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C0_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C0_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C0_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C0_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C0_edma3_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CA55C1 - IPG DEBUG mask bit for CA55 core1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C1_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C1_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C1_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C1_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C1_edma3_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CA55C2 - IPG DEBUG mask bit for CA55 core2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C2_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C2_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C2_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C2_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C2_edma3_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CA55C3 - IPG DEBUG mask bit for CA55 core3 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C3_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C3_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C3_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C3_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C3_edma3_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CA55C4 - IPG DEBUG mask bit for CA55 core4 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C4_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C4_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C4_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C4_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C4_edma3_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CA55C5 - IPG DEBUG mask bit for CA55 core5 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C5_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C5_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C5_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C5_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CA55C5_edma3_MASK) /*! @} */ /*! @name IPG_DEBUG_2_CM7 - IPG DEBUG mask bit */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM7_edma3_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM7_edma3_SHIFT (0U) /*! edma3 - EDMA3 debug */ #define BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM7_edma3(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM7_edma3_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DEBUG_2_CM7_edma3_MASK) /*! @} */ /*! @name DBG_TRACE_CTL - DEBUG TRACE control */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_DBG_TRACE_CTL_clken_csswo_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_DBG_TRACE_CTL_clken_csswo_SHIFT (0U) /*! clken_csswo - Enable control of the debug/trace CSSWO clock. 0: trace_en_swo disabled, trace * port clock OFF 1: trace_en_swo enabled, trace port clock ON */ #define BLK_CTRL_WAKEUPMIX_DBG_TRACE_CTL_clken_csswo(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_DBG_TRACE_CTL_clken_csswo_SHIFT)) & BLK_CTRL_WAKEUPMIX_DBG_TRACE_CTL_clken_csswo_MASK) /*! @} */ /*! @name SMMU_TBU_IRQ_SETUP - SMMU TBU IRQ resynchronization setup */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_SMMU_TBU_IRQ_SETUP_stretch_ratio_MASK (0x3U) #define BLK_CTRL_WAKEUPMIX_SMMU_TBU_IRQ_SETUP_stretch_ratio_SHIFT (0U) /*! stretch_ratio - SMMU TBU IRQ stretch ratio for resynchronization * 0b00..Stretch IRQ pulse by 2 * 0b01..Stretch IRQ pulse by 4 * 0b10..Stretch IRQ pulse by 8 * 0b11..Stretch IRQ pulse by 16 */ #define BLK_CTRL_WAKEUPMIX_SMMU_TBU_IRQ_SETUP_stretch_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_SMMU_TBU_IRQ_SETUP_stretch_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_SMMU_TBU_IRQ_SETUP_stretch_ratio_MASK) /*! @} */ /*! @name INITIATOR_TIMEOUT - NOC initiator timeout status */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma0_timeout_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma0_timeout_SHIFT (0U) /*! ma0_timeout - Initiator timeout for ma0_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma0_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma0_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma0_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1a_timeout_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1a_timeout_SHIFT (1U) /*! ma1a_timeout - Initiator timeout for ma1a_timeout (TBU path) */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1a_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1a_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1a_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1b_timeout_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1b_timeout_SHIFT (2U) /*! ma1b_timeout - Initiator timeout for ma1b_timeout (ATU path) */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1b_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1b_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma1b_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2a_timeout_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2a_timeout_SHIFT (3U) /*! ma2a_timeout - Initiator timeout for ma2a_timeout (TBU path) */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2a_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2a_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2a_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2b_timeout_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2b_timeout_SHIFT (4U) /*! ma2b_timeout - Initiator timeout for ma2b_timeout (ATU path) */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2b_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2b_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_ma2b_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md0_timeout_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md0_timeout_SHIFT (16U) /*! md0_timeout - Initiator timeout for md0_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md0_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md0_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md0_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md1_timeout_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md1_timeout_SHIFT (17U) /*! md1_timeout - Initiator timeout for md1_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md1_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md1_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md1_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md2_timeout_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md2_timeout_SHIFT (18U) /*! md2_timeout - Initiator timeout for md2_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md2_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md2_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md2_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md3_timeout_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md3_timeout_SHIFT (19U) /*! md3_timeout - Initiator timeout for md3_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md3_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md3_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md3_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md4_timeout_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md4_timeout_SHIFT (20U) /*! md4_timeout - Initiator timeout for md4_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md4_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md4_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md4_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md5_timeout_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md5_timeout_SHIFT (21U) /*! md5_timeout - Initiator timeout for md5_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md5_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md5_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md5_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md6_timeout_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md6_timeout_SHIFT (22U) /*! md6_timeout - Initiator timeout for md6_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md6_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md6_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md6_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md7_timeout_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md7_timeout_SHIFT (23U) /*! md7_timeout - Initiator timeout for md7_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md7_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md7_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md7_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md8_timeout_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md8_timeout_SHIFT (24U) /*! md8_timeout - Initiator timeout for md8_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md8_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md8_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md8_timeout_MASK) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md9_timeout_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md9_timeout_SHIFT (25U) /*! md9_timeout - Initiator timeout for md9_timeout */ #define BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md9_timeout(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md9_timeout_SHIFT)) & BLK_CTRL_WAKEUPMIX_INITIATOR_TIMEOUT_md9_timeout_MASK) /*! @} */ /*! @name NIU_TO_MA0 - Timeout Control for NOC main NIU master m_a_0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA0_dis_MASK) /*! @} */ /*! @name NIU_TO_MA1 - Timeout Control for NOC main NIU master m_a_1x */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA1_dis_MASK) /*! @} */ /*! @name NIU_TO_MA2 - Timeout Control for NOC main NIU master m_a_2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MA2_dis_MASK) /*! @} */ /*! @name NIU_TO_MD0 - Timeout Control for NOC mega NIU master m_d_0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD0_dis_MASK) /*! @} */ /*! @name NIU_TO_MD1 - Timeout Control for NOC mega NIU master m_d_1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD1_dis_MASK) /*! @} */ /*! @name NIU_TO_MD2 - Timeout Control for NOC mega NIU master m_d_2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD2_dis_MASK) /*! @} */ /*! @name NIU_TO_MD3 - Timeout Control for NOC mega NIU master m_d_3 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD3_dis_MASK) /*! @} */ /*! @name NIU_TO_MD4 - Timeout Control for NOC mega NIU master m_d_4 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD4_dis_MASK) /*! @} */ /*! @name NIU_TO_MD5 - Timeout Control for NOC mega NIU master m_d_5 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD5_dis_MASK) /*! @} */ /*! @name NIU_TO_MD6 - Timeout Control for NOC mega NIU master m_d_6 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD6_dis_MASK) /*! @} */ /*! @name NIU_TO_MD7 - Timeout Control for NOC mega NIU master m_d_7 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD7_dis_MASK) /*! @} */ /*! @name NIU_TO_MD8 - Timeout Control for NOC mega NIU master m_d_8 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD8_dis_MASK) /*! @} */ /*! @name NIU_TO_MD9 - Timeout Control for NOC mega NIU master m_d_9 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_clk_div_ratio_MASK (0x7U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_clk_div_ratio_SHIFT (0U) /*! clk_div_ratio - Timeout clock divider ratio selection * 0b000..Div by 4 * 0b001..Div by 8 * 0b010..Div by 16 (default) * 0b011..Div by 32 * 0b100..Div by 64 * 0b101..Div by 128 * 0b110..Div by 256 * 0b111..Div by 512 */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_clk_div_ratio(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_clk_div_ratio_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_clk_div_ratio_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_upd_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_upd_SHIFT (15U) /*! upd - Timeout divider selection update control */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_upd(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_upd_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_upd_MASK) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_dis_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_dis_SHIFT (31U) /*! dis - Timeout disable * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_dis(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_dis_SHIFT)) & BLK_CTRL_WAKEUPMIX_NIU_TO_MD9_dis_MASK) /*! @} */ /*! @name IPG_STOP_CTL_0 - IPG_STOP control register 0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can2_stop_enable_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can2_stop_enable_SHIFT (0U) /*! can2_stop_enable - CAN2 ipg_stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can2_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can2_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can2_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can3_stop_enable_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can3_stop_enable_SHIFT (1U) /*! can3_stop_enable - CAN3 ipg_stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can3_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can3_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can3_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can4_stop_enable_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can4_stop_enable_SHIFT (2U) /*! can4_stop_enable - CAN4 ipg_stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can4_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can4_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can4_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can5_stop_enable_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can5_stop_enable_SHIFT (3U) /*! can5_stop_enable - CAN5 ipg_stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can5_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can5_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_can5_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma2_stop_enable_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma2_stop_enable_SHIFT (4U) /*! edma2_stop_enable - EDMA2 ipg_stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma2_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma2_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma2_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma3_stop_enable_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma3_stop_enable_SHIFT (5U) /*! edma3_stop_enable - EDMA3 ipg_stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma3_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma3_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_edma3_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_flexspi1_stop_enable_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_flexspi1_stop_enable_SHIFT (8U) /*! flexspi1_stop_enable - FlexSPI1 ipg_stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_flexspi1_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_flexspi1_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_0_flexspi1_stop_enable_MASK) /*! @} */ /*! @name IPG_STOP_ACK_STATUS_0 - IPG_STOP_ACK status 0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can2_stop_ack_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can2_stop_ack_SHIFT (0U) /*! can2_stop_ack - CAN2 ipg_stop_ack status */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can2_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can2_stop_ack_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can2_stop_ack_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can3_stop_ack_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can3_stop_ack_SHIFT (1U) /*! can3_stop_ack - CAN3 ipg_stop_ack status */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can3_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can3_stop_ack_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can3_stop_ack_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can4_stop_ack_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can4_stop_ack_SHIFT (2U) /*! can4_stop_ack - CAN4 ipg_stop_ack status */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can4_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can4_stop_ack_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can4_stop_ack_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can5_stop_ack_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can5_stop_ack_SHIFT (3U) /*! can5_stop_ack - CAN5 ipg_stop_ack status */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can5_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can5_stop_ack_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_can5_stop_ack_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma2_stop_ack_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma2_stop_ack_SHIFT (4U) /*! edma2_stop_ack - EDMA2 ipg_stop_ack status */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma2_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma2_stop_ack_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma2_stop_ack_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma3_stop_ack_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma3_stop_ack_SHIFT (5U) /*! edma3_stop_ack - EDMA3 ipg_stop_ack status */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma3_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma3_stop_ack_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_edma3_stop_ack_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_flexspi1_stop_ack_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_flexspi1_stop_ack_SHIFT (8U) /*! flexspi1_stop_ack - FlexSPI1 ipg_stop_ack status */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_flexspi1_stop_ack(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_flexspi1_stop_ack_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_ACK_STATUS_0_flexspi1_stop_ack_MASK) /*! @} */ /*! @name IPG_DOZE_CTL_0 - IPG_DOZE control 0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can2_doze_enable_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can2_doze_enable_SHIFT (0U) /*! can2_doze_enable - CAN2 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can2_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can2_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can2_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can3_doze_enable_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can3_doze_enable_SHIFT (1U) /*! can3_doze_enable - CAN3 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can3_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can3_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can3_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can4_doze_enable_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can4_doze_enable_SHIFT (2U) /*! can4_doze_enable - CAN4 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can4_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can4_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can4_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can5_doze_enable_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can5_doze_enable_SHIFT (3U) /*! can5_doze_enable - CAN5 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can5_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can5_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_can5_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio1_doze_enable_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio1_doze_enable_SHIFT (6U) /*! flexio1_doze_enable - FlexIO1 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio1_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio1_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio1_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio2_doze_enable_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio2_doze_enable_SHIFT (7U) /*! flexio2_doze_enable - FlexIO2 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio2_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio2_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexio2_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexspi1_doze_enable_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexspi1_doze_enable_SHIFT (8U) /*! flexspi1_doze_enable - FlexSPI1 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexspi1_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexspi1_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_flexspi1_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c3_doze_enable_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c3_doze_enable_SHIFT (9U) /*! lpi2c3_doze_enable - LPI2C3 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c3_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c3_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c3_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c4_doze_enable_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c4_doze_enable_SHIFT (10U) /*! lpi2c4_doze_enable - LPI2C4 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c4_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c4_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c4_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c5_doze_enable_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c5_doze_enable_SHIFT (11U) /*! lpi2c5_doze_enable - LPI2C5 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c5_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c5_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c5_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c6_doze_enable_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c6_doze_enable_SHIFT (12U) /*! lpi2c6_doze_enable - LPI2C6 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c6_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c6_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c6_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c7_doze_enable_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c7_doze_enable_SHIFT (13U) /*! lpi2c7_doze_enable - LPI2C7 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c7_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c7_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c7_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c8_doze_enable_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c8_doze_enable_SHIFT (14U) /*! lpi2c8_doze_enable - LPI2C8 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c8_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c8_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpi2c8_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpit2_doze_enable_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpit2_doze_enable_SHIFT (15U) /*! lpit2_doze_enable - LPIT2 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpit2_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpit2_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpit2_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi3_doze_enable_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi3_doze_enable_SHIFT (16U) /*! lpspi3_doze_enable - LPSPI3 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi3_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi3_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi3_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi4_doze_enable_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi4_doze_enable_SHIFT (17U) /*! lpspi4_doze_enable - LPSPI4 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi4_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi4_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi4_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi5_doze_enable_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi5_doze_enable_SHIFT (18U) /*! lpspi5_doze_enable - LPSPI5 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi5_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi5_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi5_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi6_doze_enable_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi6_doze_enable_SHIFT (19U) /*! lpspi6_doze_enable - LPSPI6 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi6_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi6_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi6_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi7_doze_enable_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi7_doze_enable_SHIFT (20U) /*! lpspi7_doze_enable - LPSPI7 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi7_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi7_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi7_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi8_doze_enable_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi8_doze_enable_SHIFT (21U) /*! lpspi8_doze_enable - LPSPI8 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi8_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi8_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpspi8_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart3_doze_enable_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart3_doze_enable_SHIFT (22U) /*! lpuart3_doze_enable - LPUART3 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart3_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart3_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart3_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart4_doze_enable_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart4_doze_enable_SHIFT (23U) /*! lpuart4_doze_enable - LPUART4 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart4_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart4_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart4_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart5_doze_enable_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart5_doze_enable_SHIFT (24U) /*! lpuart5_doze_enable - LPUART5 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart5_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart5_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart5_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart6_doze_enable_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart6_doze_enable_SHIFT (25U) /*! lpuart6_doze_enable - LPUART6 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart6_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart6_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart6_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart7_doze_enable_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart7_doze_enable_SHIFT (26U) /*! lpuart7_doze_enable - LPUART7 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart7_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart7_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart7_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart8_doze_enable_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart8_doze_enable_SHIFT (27U) /*! lpuart8_doze_enable - LPUART8 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart8_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart8_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_0_lpuart8_doze_enable_MASK) /*! @} */ /*! @name IPG_STOP_CTL_1 - IPG_STOP control register 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm3_stop_enable_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm3_stop_enable_SHIFT (3U) /*! tpm3_stop_enable - TPM3 stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm3_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm3_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm3_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm4_stop_enable_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm4_stop_enable_SHIFT (4U) /*! tpm4_stop_enable - TPM4 stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm4_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm4_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm4_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm5_stop_enable_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm5_stop_enable_SHIFT (5U) /*! tpm5_stop_enable - TPM5 stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm5_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm5_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm5_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm6_stop_enable_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm6_stop_enable_SHIFT (6U) /*! tpm6_stop_enable - TPM6 stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm6_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm6_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_tpm6_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog3_stop_enable_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog3_stop_enable_SHIFT (7U) /*! wdog3_stop_enable - WDOG3 stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog3_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog3_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog3_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog4_stop_enable_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog4_stop_enable_SHIFT (8U) /*! wdog4_stop_enable - WDOG4 stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog4_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog4_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog4_stop_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog5_stop_enable_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog5_stop_enable_SHIFT (9U) /*! wdog5_stop_enable - WDOG5 stop control */ #define BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog5_stop_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog5_stop_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_STOP_CTL_1_wdog5_stop_enable_MASK) /*! @} */ /*! @name IPG_DOZE_CTL_1 - IPG_DOZE control 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm3_doze_enable_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm3_doze_enable_SHIFT (3U) /*! tpm3_doze_enable - TPM3 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm3_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm3_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm3_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm4_doze_enable_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm4_doze_enable_SHIFT (4U) /*! tpm4_doze_enable - TPM4 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm4_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm4_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm4_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm5_doze_enable_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm5_doze_enable_SHIFT (5U) /*! tpm5_doze_enable - TPM5 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm5_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm5_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm5_doze_enable_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm6_doze_enable_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm6_doze_enable_SHIFT (6U) /*! tpm6_doze_enable - TPM6 ipg_doze control */ #define BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm6_doze_enable(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm6_doze_enable_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_DOZE_CTL_1_tpm6_doze_enable_MASK) /*! @} */ /*! @name IPG_WAIT_CTL_1 - IPG_WAIT control 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog3_wait_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog3_wait_SHIFT (7U) /*! wdog3_wait - WDOG3 ipg_wait control */ #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog3_wait(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog3_wait_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog3_wait_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog4_wait_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog4_wait_SHIFT (8U) /*! wdog4_wait - WDOG4 ipg_wait control */ #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog4_wait(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog4_wait_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog4_wait_MASK) #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog5_wait_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog5_wait_SHIFT (9U) /*! wdog5_wait - WDOG5 ipg_wait control */ #define BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog5_wait(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog5_wait_SHIFT)) & BLK_CTRL_WAKEUPMIX_IPG_WAIT_CTL_1_wdog5_wait_MASK) /*! @} */ /*! @name QREQ_CTL_0 - QREQ control register 0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can2_qreq_n_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can2_qreq_n_SHIFT (0U) /*! can2_qreq_n - CAN2 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can2_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can2_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can2_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can3_qreq_n_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can3_qreq_n_SHIFT (1U) /*! can3_qreq_n - CAN3 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can4_qreq_n_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can4_qreq_n_SHIFT (2U) /*! can4_qreq_n - CAN4 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can5_qreq_n_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can5_qreq_n_SHIFT (3U) /*! can5_qreq_n - CAN5 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_can5_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma2_qreq_n_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma2_qreq_n_SHIFT (4U) /*! edma2_qreq_n - EDMA2 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma2_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma2_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma2_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma3_qreq_n_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma3_qreq_n_SHIFT (5U) /*! edma3_qreq_n - EDMA3 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_edma3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio1_qreq_n_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio1_qreq_n_SHIFT (6U) /*! flexio1_qreq_n - FlexIO1 flexio qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio1_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio1_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio1_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio2_qreq_n_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio2_qreq_n_SHIFT (7U) /*! flexio2_qreq_n - FlexIO2 flexio qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio2_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio2_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexio2_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexspi1_qreq_n_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexspi1_qreq_n_SHIFT (8U) /*! flexspi1_qreq_n - FlexSPI1 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexspi1_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexspi1_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_flexspi1_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c3_qreq_n_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c3_qreq_n_SHIFT (9U) /*! lpi2c3_qreq_n - LPI2C3 lpi2c qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c4_qreq_n_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c4_qreq_n_SHIFT (10U) /*! lpi2c4_qreq_n - LPI2C4 lpi2c qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c5_qreq_n_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c5_qreq_n_SHIFT (11U) /*! lpi2c5_qreq_n - LPI2C5 lpi2c qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c5_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c6_qreq_n_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c6_qreq_n_SHIFT (12U) /*! lpi2c6_qreq_n - LPI2C6 lpi2c qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c6_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c6_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c6_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c7_qreq_n_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c7_qreq_n_SHIFT (13U) /*! lpi2c7_qreq_n - LPI2C7 lpi2c qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c7_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c7_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c7_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c8_qreq_n_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c8_qreq_n_SHIFT (14U) /*! lpi2c8_qreq_n - LPI2C8 lpi2c qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c8_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c8_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpi2c8_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpit2_qreq_n_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpit2_qreq_n_SHIFT (15U) /*! lpit2_qreq_n - LPIT2 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpit2_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpit2_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpit2_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi3_qreq_n_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi3_qreq_n_SHIFT (16U) /*! lpspi3_qreq_n - LPSPI3 lpspi qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi4_qreq_n_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi4_qreq_n_SHIFT (17U) /*! lpspi4_qreq_n - LPSPI4 lpspi qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi5_qreq_n_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi5_qreq_n_SHIFT (18U) /*! lpspi5_qreq_n - LPSPI5 lpspi qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi5_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi6_qreq_n_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi6_qreq_n_SHIFT (19U) /*! lpspi6_qreq_n - LPSPI6 lpspi qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi6_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi6_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi6_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi7_qreq_n_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi7_qreq_n_SHIFT (20U) /*! lpspi7_qreq_n - LPSPI7 lpspi qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi7_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi7_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi7_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi8_qreq_n_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi8_qreq_n_SHIFT (21U) /*! lpspi8_qreq_n - LPSPI8 lpspi qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi8_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi8_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpspi8_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart3_qreq_n_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart3_qreq_n_SHIFT (22U) /*! lpuart3_qreq_n - LPUART3 lpuart qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart4_qreq_n_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart4_qreq_n_SHIFT (23U) /*! lpuart4_qreq_n - LPUART4 lpuart qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart5_qreq_n_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart5_qreq_n_SHIFT (24U) /*! lpuart5_qreq_n - LPUART5 lpuart qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart5_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart6_qreq_n_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart6_qreq_n_SHIFT (25U) /*! lpuart6_qreq_n - LPUART6 lpuart qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart6_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart6_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart6_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart7_qreq_n_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart7_qreq_n_SHIFT (26U) /*! lpuart7_qreq_n - LPUART7 lpuart qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart7_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart7_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart7_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart8_qreq_n_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart8_qreq_n_SHIFT (27U) /*! lpuart8_qreq_n - LPUART8 lpuart qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart8_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart8_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_lpuart8_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio2_qreq_n_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio2_qreq_n_SHIFT (28U) /*! gpio2_qreq_n - GPIO2 AHB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio2_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio2_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio2_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio3_qreq_n_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio3_qreq_n_SHIFT (29U) /*! gpio3_qreq_n - GPIO3 AHB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio4_qreq_n_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio4_qreq_n_SHIFT (30U) /*! gpio4_qreq_n - GPIO4 AHB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio5_qreq_n_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio5_qreq_n_SHIFT (31U) /*! gpio5_qreq_n - GPIO5 AHB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_0_gpio5_qreq_n_MASK) /*! @} */ /*! @name QACCEPT_STATUS_0 - QACCEPT status register 0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can2_qaccept_n_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can2_qaccept_n_SHIFT (0U) /*! can2_qaccept_n - CAN2 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can2_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can2_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can2_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can3_qaccept_n_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can3_qaccept_n_SHIFT (1U) /*! can3_qaccept_n - CAN3 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can4_qaccept_n_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can4_qaccept_n_SHIFT (2U) /*! can4_qaccept_n - CAN4 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can5_qaccept_n_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can5_qaccept_n_SHIFT (3U) /*! can5_qaccept_n - CAN5 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_can5_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma2_qaccept_n_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma2_qaccept_n_SHIFT (4U) /*! edma2_qaccept_n - EDMA2 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma2_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma2_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma2_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma3_qaccept_n_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma3_qaccept_n_SHIFT (5U) /*! edma3_qaccept_n - EDMA3 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_edma3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio1_qaccept_n_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio1_qaccept_n_SHIFT (6U) /*! flexio1_qaccept_n - FlexIO1 flexio qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio1_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio1_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio1_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio2_qaccept_n_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio2_qaccept_n_SHIFT (7U) /*! flexio2_qaccept_n - FlexIO2 flexio qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio2_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio2_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexio2_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexspi1_qaccept_n_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexspi1_qaccept_n_SHIFT (8U) /*! flexspi1_qaccept_n - FlexSPI1 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexspi1_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexspi1_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_flexspi1_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c3_qaccept_n_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c3_qaccept_n_SHIFT (9U) /*! lpi2c3_qaccept_n - LPI2C3 lpi2c qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c4_qaccept_n_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c4_qaccept_n_SHIFT (10U) /*! lpi2c4_qaccept_n - LPI2C4 lpi2c qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c5_qaccept_n_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c5_qaccept_n_SHIFT (11U) /*! lpi2c5_qaccept_n - LPI2C5 lpi2c qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c5_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c6_qaccept_n_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c6_qaccept_n_SHIFT (12U) /*! lpi2c6_qaccept_n - LPI2C6 lpi2c qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c6_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c6_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c6_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c7_qaccept_n_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c7_qaccept_n_SHIFT (13U) /*! lpi2c7_qaccept_n - LPI2C7 lpi2c qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c7_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c7_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c7_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c8_qaccept_n_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c8_qaccept_n_SHIFT (14U) /*! lpi2c8_qaccept_n - LPI2C8 lpi2c qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c8_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c8_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpi2c8_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpit2_qaccept_n_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpit2_qaccept_n_SHIFT (15U) /*! lpit2_qaccept_n - LPIT2 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpit2_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpit2_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpit2_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi3_qaccept_n_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi3_qaccept_n_SHIFT (16U) /*! lpspi3_qaccept_n - LPSPI3 lpspi qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi4_qaccept_n_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi4_qaccept_n_SHIFT (17U) /*! lpspi4_qaccept_n - LPSPI4 lpspi qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi5_qaccept_n_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi5_qaccept_n_SHIFT (18U) /*! lpspi5_qaccept_n - LPSPI5 lpspi qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi5_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi6_qaccept_n_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi6_qaccept_n_SHIFT (19U) /*! lpspi6_qaccept_n - LPSPI6 lpspi qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi6_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi6_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi6_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi7_qaccept_n_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi7_qaccept_n_SHIFT (20U) /*! lpspi7_qaccept_n - LPSPI7 lpspi qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi7_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi7_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi7_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi8_qaccept_n_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi8_qaccept_n_SHIFT (21U) /*! lpspi8_qaccept_n - LPSPI8 lpspi qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi8_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi8_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpspi8_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart3_qaccept_n_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart3_qaccept_n_SHIFT (22U) /*! lpuart3_qaccept_n - LPUART3 lpuart qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart4_qaccept_n_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart4_qaccept_n_SHIFT (23U) /*! lpuart4_qaccept_n - LPUART4 lpuart qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart5_qaccept_n_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart5_qaccept_n_SHIFT (24U) /*! lpuart5_qaccept_n - LPUART5 lpuart qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart5_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart6_qaccept_n_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart6_qaccept_n_SHIFT (25U) /*! lpuart6_qaccept_n - LPUART6 lpuart qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart6_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart6_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart6_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart7_qaccept_n_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart7_qaccept_n_SHIFT (26U) /*! lpuart7_qaccept_n - LPUART7 lpuart qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart7_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart7_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart7_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart8_qaccept_n_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart8_qaccept_n_SHIFT (27U) /*! lpuart8_qaccept_n - LPUART8 lpuart qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart8_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart8_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_lpuart8_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio2_qaccept_n_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio2_qaccept_n_SHIFT (28U) /*! gpio2_qaccept_n - GPIO2 AHB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio2_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio2_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio2_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio3_qaccept_n_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio3_qaccept_n_SHIFT (29U) /*! gpio3_qaccept_n - GPIO3 AHB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio4_qaccept_n_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio4_qaccept_n_SHIFT (30U) /*! gpio4_qaccept_n - GPIO4 AHB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio5_qaccept_n_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio5_qaccept_n_SHIFT (31U) /*! gpio5_qaccept_n - GPIO5 AHB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_0_gpio5_qaccept_n_MASK) /*! @} */ /*! @name QDENY_STATUS_0 - QDENY status register 0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can2_qdeny_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can2_qdeny_SHIFT (0U) /*! can2_qdeny - CAN2 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can2_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can2_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can2_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can3_qdeny_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can3_qdeny_SHIFT (1U) /*! can3_qdeny - CAN3 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can4_qdeny_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can4_qdeny_SHIFT (2U) /*! can4_qdeny - CAN4 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can5_qdeny_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can5_qdeny_SHIFT (3U) /*! can5_qdeny - CAN5 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_can5_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma2_qdeny_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma2_qdeny_SHIFT (4U) /*! edma2_qdeny - EDMA2 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma2_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma2_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma2_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma3_qdeny_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma3_qdeny_SHIFT (5U) /*! edma3_qdeny - EDMA3 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_edma3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio1_qdeny_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio1_qdeny_SHIFT (6U) /*! flexio1_qdeny - FlexIO1 flexio qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio1_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio1_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio1_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio2_qdeny_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio2_qdeny_SHIFT (7U) /*! flexio2_qdeny - FlexIO2 flexio qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio2_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio2_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexio2_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexspi1_qdeny_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexspi1_qdeny_SHIFT (8U) /*! flexspi1_qdeny - FlexSPI1 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexspi1_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexspi1_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_flexspi1_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c3_qdeny_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c3_qdeny_SHIFT (9U) /*! lpi2c3_qdeny - LPI2C3 lpi2c qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c4_qdeny_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c4_qdeny_SHIFT (10U) /*! lpi2c4_qdeny - LPI2C4 lpi2c qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c5_qdeny_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c5_qdeny_SHIFT (11U) /*! lpi2c5_qdeny - LPI2C5 lpi2c qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c5_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c6_qdeny_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c6_qdeny_SHIFT (12U) /*! lpi2c6_qdeny - LPI2C6 lpi2c qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c6_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c6_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c6_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c7_qdeny_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c7_qdeny_SHIFT (13U) /*! lpi2c7_qdeny - LPI2C7 lpi2c qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c7_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c7_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c7_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c8_qdeny_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c8_qdeny_SHIFT (14U) /*! lpi2c8_qdeny - LPI2C8 lpi2c qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c8_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c8_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpi2c8_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpit2_qdeny_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpit2_qdeny_SHIFT (15U) /*! lpit2_qdeny - LPIT2 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpit2_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpit2_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpit2_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi3_qdeny_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi3_qdeny_SHIFT (16U) /*! lpspi3_qdeny - LPSPI3 lpspi qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi4_qdeny_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi4_qdeny_SHIFT (17U) /*! lpspi4_qdeny - LPSPI4 lpspi qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi5_qdeny_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi5_qdeny_SHIFT (18U) /*! lpspi5_qdeny - LPSPI5 lpspi qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi5_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi6_qdeny_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi6_qdeny_SHIFT (19U) /*! lpspi6_qdeny - LPSPI6 lpspi qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi6_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi6_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi6_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi7_qdeny_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi7_qdeny_SHIFT (20U) /*! lpspi7_qdeny - LPSPI7 lpspi qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi7_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi7_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi7_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi8_qdeny_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi8_qdeny_SHIFT (21U) /*! lpspi8_qdeny - LPSPI8 lpspi qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi8_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi8_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpspi8_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart3_qdeny_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart3_qdeny_SHIFT (22U) /*! lpuart3_qdeny - LPUART3 lpuart qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart4_qdeny_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart4_qdeny_SHIFT (23U) /*! lpuart4_qdeny - LPUART4 lpuart qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart5_qdeny_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart5_qdeny_SHIFT (24U) /*! lpuart5_qdeny - LPUART5 lpuart qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart5_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart6_qdeny_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart6_qdeny_SHIFT (25U) /*! lpuart6_qdeny - LPUART6 lpuart qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart6_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart6_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart6_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart7_qdeny_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart7_qdeny_SHIFT (26U) /*! lpuart7_qdeny - LPUART7 lpuart qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart7_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart7_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart7_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart8_qdeny_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart8_qdeny_SHIFT (27U) /*! lpuart8_qdeny - LPUART8 lpuart qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart8_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart8_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_lpuart8_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio2_qdeny_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio2_qdeny_SHIFT (28U) /*! gpio2_qdeny - GPIO2 AHB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio2_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio2_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio2_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio3_qdeny_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio3_qdeny_SHIFT (29U) /*! gpio3_qdeny - GPIO3 AHB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio4_qdeny_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio4_qdeny_SHIFT (30U) /*! gpio4_qdeny - GPIO4 AHB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio5_qdeny_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio5_qdeny_SHIFT (31U) /*! gpio5_qdeny - GPIO5 AHB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_0_gpio5_qdeny_MASK) /*! @} */ /*! @name QACTIVE_STATUS_0 - QACTIVE status register 0 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can2_qactive_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can2_qactive_SHIFT (0U) /*! can2_qactive - CAN2 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can2_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can2_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can2_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can3_qactive_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can3_qactive_SHIFT (1U) /*! can3_qactive - CAN3 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can4_qactive_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can4_qactive_SHIFT (2U) /*! can4_qactive - CAN4 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can5_qactive_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can5_qactive_SHIFT (3U) /*! can5_qactive - CAN5 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_can5_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma2_qactive_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma2_qactive_SHIFT (4U) /*! edma2_qactive - EDMA2 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma2_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma2_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma2_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma3_qactive_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma3_qactive_SHIFT (5U) /*! edma3_qactive - EDMA3 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_edma3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio1_qactive_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio1_qactive_SHIFT (6U) /*! flexio1_qactive - FlexIO1 flexio qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio1_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio1_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio1_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio2_qactive_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio2_qactive_SHIFT (7U) /*! flexio2_qactive - FlexIO2 flexio qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio2_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio2_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexio2_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexspi1_qactive_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexspi1_qactive_SHIFT (8U) /*! flexspi1_qactive - FlexSPI1 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexspi1_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexspi1_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_flexspi1_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c3_qactive_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c3_qactive_SHIFT (9U) /*! lpi2c3_qactive - LPI2C3 lpi2c qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c4_qactive_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c4_qactive_SHIFT (10U) /*! lpi2c4_qactive - LPI2C4 lpi2c qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c5_qactive_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c5_qactive_SHIFT (11U) /*! lpi2c5_qactive - LPI2C5 lpi2c qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c5_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c6_qactive_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c6_qactive_SHIFT (12U) /*! lpi2c6_qactive - LPI2C6 lpi2c qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c6_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c6_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c6_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c7_qactive_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c7_qactive_SHIFT (13U) /*! lpi2c7_qactive - LPI2C7 lpi2c qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c7_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c7_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c7_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c8_qactive_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c8_qactive_SHIFT (14U) /*! lpi2c8_qactive - LPI2C8 lpi2c qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c8_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c8_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpi2c8_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpit2_qactive_MASK (0x8000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpit2_qactive_SHIFT (15U) /*! lpit2_qactive - LPIT2 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpit2_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpit2_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpit2_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi3_qactive_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi3_qactive_SHIFT (16U) /*! lpspi3_qactive - LPSPI3 lpspi qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi4_qactive_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi4_qactive_SHIFT (17U) /*! lpspi4_qactive - LPSPI4 lpspi qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi5_qactive_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi5_qactive_SHIFT (18U) /*! lpspi5_qactive - LPSPI5 lpspi qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi5_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi6_qactive_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi6_qactive_SHIFT (19U) /*! lpspi6_qactive - LPSPI6 lpspi qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi6_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi6_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi6_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi7_qactive_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi7_qactive_SHIFT (20U) /*! lpspi7_qactive - LPSPI7 lpspi qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi7_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi7_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi7_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi8_qactive_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi8_qactive_SHIFT (21U) /*! lpspi8_qactive - LPSPI8 lpspi qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi8_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi8_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpspi8_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart3_qactive_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart3_qactive_SHIFT (22U) /*! lpuart3_qactive - LPUART3 lpuart qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart4_qactive_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart4_qactive_SHIFT (23U) /*! lpuart4_qactive - LPUART4 lpuart qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart5_qactive_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart5_qactive_SHIFT (24U) /*! lpuart5_qactive - LPUART5 lpuart qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart5_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart6_qactive_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart6_qactive_SHIFT (25U) /*! lpuart6_qactive - LPUART6 lpuart qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart6_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart6_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart6_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart7_qactive_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart7_qactive_SHIFT (26U) /*! lpuart7_qactive - LPUART7 lpuart qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart7_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart7_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart7_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart8_qactive_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart8_qactive_SHIFT (27U) /*! lpuart8_qactive - LPUART8 lpuart qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart8_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart8_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_lpuart8_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio2_qactive_MASK (0x10000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio2_qactive_SHIFT (28U) /*! gpio2_qactive - GPIO2 AHB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio2_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio2_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio2_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio3_qactive_MASK (0x20000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio3_qactive_SHIFT (29U) /*! gpio3_qactive - GPIO3 AHB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio4_qactive_MASK (0x40000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio4_qactive_SHIFT (30U) /*! gpio4_qactive - GPIO4 AHB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio5_qactive_MASK (0x80000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio5_qactive_SHIFT (31U) /*! gpio5_qactive - GPIO5 AHB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_0_gpio5_qactive_MASK) /*! @} */ /*! @name QREQ_CTL_1 - QREQ control register 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai3_qreq_n_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai3_qreq_n_SHIFT (0U) /*! sai3_qreq_n - SAI3 sai qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai4_qreq_n_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai4_qreq_n_SHIFT (1U) /*! sai4_qreq_n - SAI4 sai qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai5_qreq_n_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai5_qreq_n_SHIFT (2U) /*! sai5_qreq_n - SAI5 sai qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_sai5_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm3_qreq_n_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm3_qreq_n_SHIFT (3U) /*! tpm3_qreq_n - TPM3 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm4_qreq_n_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm4_qreq_n_SHIFT (4U) /*! tpm4_qreq_n - TPM4 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm5_qreq_n_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm5_qreq_n_SHIFT (5U) /*! tpm5_qreq_n - TPM5 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm5_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm6_qreq_n_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm6_qreq_n_SHIFT (6U) /*! tpm6_qreq_n - TPM6 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm6_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm6_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_tpm6_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog3_qreq_n_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog3_qreq_n_SHIFT (7U) /*! wdog3_qreq_n - WDOG3 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog3_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog3_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog3_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog4_qreq_n_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog4_qreq_n_SHIFT (8U) /*! wdog4_qreq_n - WDOG4 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog4_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog4_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog4_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog5_qreq_n_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog5_qreq_n_SHIFT (9U) /*! wdog5_qreq_n - WDOG5 qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog5_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog5_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_1_wdog5_qreq_n_MASK) /*! @} */ /*! @name QACCEPT_STATUS_1 - QACCEPT status register 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai3_qaccept_n_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai3_qaccept_n_SHIFT (0U) /*! sai3_qaccept_n - SAI3 sai qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai4_qaccept_n_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai4_qaccept_n_SHIFT (1U) /*! sai4_qaccept_n - SAI4 sai qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai5_qaccept_n_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai5_qaccept_n_SHIFT (2U) /*! sai5_qaccept_n - SAI5 sai qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_sai5_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm3_qaccept_n_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm3_qaccept_n_SHIFT (3U) /*! tpm3_qaccept_n - TPM3 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm4_qaccept_n_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm4_qaccept_n_SHIFT (4U) /*! tpm4_qaccept_n - TPM4 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm5_qaccept_n_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm5_qaccept_n_SHIFT (5U) /*! tpm5_qaccept_n - TPM5 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm5_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm6_qaccept_n_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm6_qaccept_n_SHIFT (6U) /*! tpm6_qaccept_n - TPM6 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm6_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm6_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_tpm6_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog3_qaccept_n_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog3_qaccept_n_SHIFT (7U) /*! wdog3_qaccept_n - WDOG3 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog3_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog3_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog3_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog4_qaccept_n_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog4_qaccept_n_SHIFT (8U) /*! wdog4_qaccept_n - WDOG4 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog4_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog4_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog4_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog5_qaccept_n_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog5_qaccept_n_SHIFT (9U) /*! wdog5_qaccept_n - WDOG5 qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog5_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog5_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_1_wdog5_qaccept_n_MASK) /*! @} */ /*! @name QDENY_STATUS_1 - QDENY status register 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai3_qdeny_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai3_qdeny_SHIFT (0U) /*! sai3_qdeny - SAI3 sai qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai4_qdeny_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai4_qdeny_SHIFT (1U) /*! sai4_qdeny - SAI4 sai qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai5_qdeny_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai5_qdeny_SHIFT (2U) /*! sai5_qdeny - SAI5 sai qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_sai5_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm3_qdeny_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm3_qdeny_SHIFT (3U) /*! tpm3_qdeny - TPM3 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm4_qdeny_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm4_qdeny_SHIFT (4U) /*! tpm4_qdeny - TPM4 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm5_qdeny_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm5_qdeny_SHIFT (5U) /*! tpm5_qdeny - TPM5 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm5_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm6_qdeny_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm6_qdeny_SHIFT (6U) /*! tpm6_qdeny - TPM6 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm6_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm6_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_tpm6_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog3_qdeny_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog3_qdeny_SHIFT (7U) /*! wdog3_qdeny - WDOG3 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog3_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog3_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog3_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog4_qdeny_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog4_qdeny_SHIFT (8U) /*! wdog4_qdeny - WDOG4 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog4_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog4_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog4_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog5_qdeny_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog5_qdeny_SHIFT (9U) /*! wdog5_qdeny - WDOG5 qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog5_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog5_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_1_wdog5_qdeny_MASK) /*! @} */ /*! @name QACTIVE_STATUS_1 - QACTIVE status register 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai3_qactive_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai3_qactive_SHIFT (0U) /*! sai3_qactive - SAI3 sai qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai4_qactive_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai4_qactive_SHIFT (1U) /*! sai4_qactive - SAI4 sai qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai5_qactive_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai5_qactive_SHIFT (2U) /*! sai5_qactive - SAI5 sai qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_sai5_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm3_qactive_MASK (0x8U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm3_qactive_SHIFT (3U) /*! tpm3_qactive - TPM3 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm4_qactive_MASK (0x10U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm4_qactive_SHIFT (4U) /*! tpm4_qactive - TPM4 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm5_qactive_MASK (0x20U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm5_qactive_SHIFT (5U) /*! tpm5_qactive - TPM5 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm5_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm6_qactive_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm6_qactive_SHIFT (6U) /*! tpm6_qactive - TPM6 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm6_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm6_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_tpm6_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog3_qactive_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog3_qactive_SHIFT (7U) /*! wdog3_qactive - WDOG3 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog3_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog3_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog3_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog4_qactive_MASK (0x100U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog4_qactive_SHIFT (8U) /*! wdog4_qactive - WDOG4 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog4_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog4_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog4_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog5_qactive_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog5_qactive_SHIFT (9U) /*! wdog5_qactive - WDOG5 qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog5_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog5_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_1_wdog5_qactive_MASK) /*! @} */ /*! @name QREQ_CTL_2 - QREQ control register 2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio1_apb_qreq_n_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio1_apb_qreq_n_SHIFT (6U) /*! flexio1_apb_qreq_n - FlexIO1 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio1_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio1_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio1_apb_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio2_apb_qreq_n_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio2_apb_qreq_n_SHIFT (7U) /*! flexio2_apb_qreq_n - FlexIO2 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio2_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio2_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_flexio2_apb_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c3_ips_qreq_n_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c3_ips_qreq_n_SHIFT (9U) /*! lpi2c3_ips_qreq_n - LPI2C3 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c3_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c3_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c3_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c4_ips_qreq_n_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c4_ips_qreq_n_SHIFT (10U) /*! lpi2c4_ips_qreq_n - LPI2C4 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c4_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c4_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c4_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c5_ips_qreq_n_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c5_ips_qreq_n_SHIFT (11U) /*! lpi2c5_ips_qreq_n - LPI2C5 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c5_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c5_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c5_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c6_ips_qreq_n_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c6_ips_qreq_n_SHIFT (12U) /*! lpi2c6_ips_qreq_n - LPI2C6 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c6_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c6_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c6_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c7_ips_qreq_n_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c7_ips_qreq_n_SHIFT (13U) /*! lpi2c7_ips_qreq_n - LPI2C7 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c7_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c7_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c7_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c8_ips_qreq_n_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c8_ips_qreq_n_SHIFT (14U) /*! lpi2c8_ips_qreq_n - LPI2C8 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c8_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c8_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpi2c8_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi3_ips_qreq_n_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi3_ips_qreq_n_SHIFT (16U) /*! lpspi3_ips_qreq_n - LPSPI3 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi3_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi3_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi3_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi4_ips_qreq_n_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi4_ips_qreq_n_SHIFT (17U) /*! lpspi4_ips_qreq_n - LPSPI4 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi4_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi4_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi4_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi5_ips_qreq_n_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi5_ips_qreq_n_SHIFT (18U) /*! lpspi5_ips_qreq_n - LPSPI5 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi5_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi5_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi5_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi6_ips_qreq_n_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi6_ips_qreq_n_SHIFT (19U) /*! lpspi6_ips_qreq_n - LPSPI6 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi6_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi6_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi6_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi7_ips_qreq_n_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi7_ips_qreq_n_SHIFT (20U) /*! lpspi7_ips_qreq_n - LPSPI7 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi7_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi7_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi7_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi8_ips_qreq_n_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi8_ips_qreq_n_SHIFT (21U) /*! lpspi8_ips_qreq_n - LPSPI8 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi8_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi8_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpspi8_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart3_apb_qreq_n_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart3_apb_qreq_n_SHIFT (22U) /*! lpuart3_apb_qreq_n - LPUART3 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart3_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart3_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart3_apb_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart4_apb_qreq_n_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart4_apb_qreq_n_SHIFT (23U) /*! lpuart4_apb_qreq_n - LPUART4 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart4_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart4_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart4_apb_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart5_apb_qreq_n_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart5_apb_qreq_n_SHIFT (24U) /*! lpuart5_apb_qreq_n - LPUART5 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart5_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart5_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart5_apb_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart6_apb_qreq_n_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart6_apb_qreq_n_SHIFT (25U) /*! lpuart6_apb_qreq_n - LPUART6 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart6_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart6_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart6_apb_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart7_apb_qreq_n_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart7_apb_qreq_n_SHIFT (26U) /*! lpuart7_apb_qreq_n - LPUART7 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart7_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart7_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart7_apb_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart8_apb_qreq_n_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart8_apb_qreq_n_SHIFT (27U) /*! lpuart8_apb_qreq_n - LPUART8 APB qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart8_apb_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart8_apb_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_2_lpuart8_apb_qreq_n_MASK) /*! @} */ /*! @name QACCEPT_STATUS_2 - QACCEPT status register 2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio1_apb_qaccept_n_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio1_apb_qaccept_n_SHIFT (6U) /*! flexio1_apb_qaccept_n - FlexIO1 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio1_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio1_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio1_apb_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio2_apb_qaccept_n_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio2_apb_qaccept_n_SHIFT (7U) /*! flexio2_apb_qaccept_n - FlexIO2 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio2_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio2_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_flexio2_apb_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c3_ips_qaccept_n_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c3_ips_qaccept_n_SHIFT (9U) /*! lpi2c3_ips_qaccept_n - LPI2C3 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c3_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c3_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c3_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c4_ips_qaccept_n_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c4_ips_qaccept_n_SHIFT (10U) /*! lpi2c4_ips_qaccept_n - LPI2C4 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c4_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c4_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c4_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c5_ips_qaccept_n_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c5_ips_qaccept_n_SHIFT (11U) /*! lpi2c5_ips_qaccept_n - LPI2C5 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c5_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c5_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c5_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c6_ips_qaccept_n_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c6_ips_qaccept_n_SHIFT (12U) /*! lpi2c6_ips_qaccept_n - LPI2C6 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c6_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c6_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c6_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c7_ips_qaccept_n_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c7_ips_qaccept_n_SHIFT (13U) /*! lpi2c7_ips_qaccept_n - LPI2C7 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c7_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c7_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c7_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c8_ips_qaccept_n_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c8_ips_qaccept_n_SHIFT (14U) /*! lpi2c8_ips_qaccept_n - LPI2C8 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c8_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c8_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpi2c8_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi3_ips_qaccept_n_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi3_ips_qaccept_n_SHIFT (16U) /*! lpspi3_ips_qaccept_n - LPSPI3 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi3_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi3_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi3_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi4_ips_qaccept_n_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi4_ips_qaccept_n_SHIFT (17U) /*! lpspi4_ips_qaccept_n - LPSPI4 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi4_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi4_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi4_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi5_ips_qaccept_n_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi5_ips_qaccept_n_SHIFT (18U) /*! lpspi5_ips_qaccept_n - LPSPI5 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi5_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi5_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi5_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi6_ips_qaccept_n_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi6_ips_qaccept_n_SHIFT (19U) /*! lpspi6_ips_qaccept_n - LPSPI6 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi6_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi6_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi6_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi7_ips_qaccept_n_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi7_ips_qaccept_n_SHIFT (20U) /*! lpspi7_ips_qaccept_n - LPSPI7 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi7_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi7_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi7_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi8_ips_qaccept_n_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi8_ips_qaccept_n_SHIFT (21U) /*! lpspi8_ips_qaccept_n - LPSPI8 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi8_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi8_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpspi8_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart3_apb_qaccept_n_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart3_apb_qaccept_n_SHIFT (22U) /*! lpuart3_apb_qaccept_n - LPUART3 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart3_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart3_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart3_apb_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart4_apb_qaccept_n_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart4_apb_qaccept_n_SHIFT (23U) /*! lpuart4_apb_qaccept_n - LPUART4 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart4_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart4_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart4_apb_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart5_apb_qaccept_n_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart5_apb_qaccept_n_SHIFT (24U) /*! lpuart5_apb_qaccept_n - LPUART5 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart5_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart5_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart5_apb_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart6_apb_qaccept_n_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart6_apb_qaccept_n_SHIFT (25U) /*! lpuart6_apb_qaccept_n - LPUART6 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart6_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart6_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart6_apb_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart7_apb_qaccept_n_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart7_apb_qaccept_n_SHIFT (26U) /*! lpuart7_apb_qaccept_n - LPUART7 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart7_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart7_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart7_apb_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart8_apb_qaccept_n_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart8_apb_qaccept_n_SHIFT (27U) /*! lpuart8_apb_qaccept_n - LPUART8 APB qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart8_apb_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart8_apb_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_2_lpuart8_apb_qaccept_n_MASK) /*! @} */ /*! @name QDENY_STATUS_2 - QDENY status register 2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio1_apb_qdeny_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio1_apb_qdeny_SHIFT (6U) /*! flexio1_apb_qdeny - FlexIO1 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio1_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio1_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio1_apb_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio2_apb_qdeny_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio2_apb_qdeny_SHIFT (7U) /*! flexio2_apb_qdeny - FlexIO2 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio2_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio2_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_flexio2_apb_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c3_ips_qdeny_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c3_ips_qdeny_SHIFT (9U) /*! lpi2c3_ips_qdeny - LPI2C3 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c3_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c3_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c3_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c4_ips_qdeny_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c4_ips_qdeny_SHIFT (10U) /*! lpi2c4_ips_qdeny - LPI2C4 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c4_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c4_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c4_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c5_ips_qdeny_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c5_ips_qdeny_SHIFT (11U) /*! lpi2c5_ips_qdeny - LPI2C5 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c5_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c5_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c5_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c6_ips_qdeny_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c6_ips_qdeny_SHIFT (12U) /*! lpi2c6_ips_qdeny - LPI2C6 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c6_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c6_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c6_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c7_ips_qdeny_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c7_ips_qdeny_SHIFT (13U) /*! lpi2c7_ips_qdeny - LPI2C7 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c7_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c7_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c7_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c8_ips_qdeny_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c8_ips_qdeny_SHIFT (14U) /*! lpi2c8_ips_qdeny - LPI2C8 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c8_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c8_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpi2c8_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi3_ips_qdeny_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi3_ips_qdeny_SHIFT (16U) /*! lpspi3_ips_qdeny - LPSPI3 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi3_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi3_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi3_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi4_ips_qdeny_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi4_ips_qdeny_SHIFT (17U) /*! lpspi4_ips_qdeny - LPSPI4 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi4_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi4_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi4_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi5_ips_qdeny_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi5_ips_qdeny_SHIFT (18U) /*! lpspi5_ips_qdeny - LPSPI5 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi5_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi5_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi5_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi6_ips_qdeny_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi6_ips_qdeny_SHIFT (19U) /*! lpspi6_ips_qdeny - LPSPI6 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi6_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi6_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi6_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi7_ips_qdeny_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi7_ips_qdeny_SHIFT (20U) /*! lpspi7_ips_qdeny - LPSPI7 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi7_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi7_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi7_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi8_ips_qdeny_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi8_ips_qdeny_SHIFT (21U) /*! lpspi8_ips_qdeny - LPSPI8 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi8_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi8_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpspi8_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart3_apb_qdeny_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart3_apb_qdeny_SHIFT (22U) /*! lpuart3_apb_qdeny - LPUART3 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart3_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart3_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart3_apb_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart4_apb_qdeny_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart4_apb_qdeny_SHIFT (23U) /*! lpuart4_apb_qdeny - LPUART4 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart4_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart4_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart4_apb_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart5_apb_qdeny_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart5_apb_qdeny_SHIFT (24U) /*! lpuart5_apb_qdeny - LPUART5 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart5_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart5_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart5_apb_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart6_apb_qdeny_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart6_apb_qdeny_SHIFT (25U) /*! lpuart6_apb_qdeny - LPUART6 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart6_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart6_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart6_apb_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart7_apb_qdeny_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart7_apb_qdeny_SHIFT (26U) /*! lpuart7_apb_qdeny - LPUART7 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart7_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart7_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart7_apb_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart8_apb_qdeny_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart8_apb_qdeny_SHIFT (27U) /*! lpuart8_apb_qdeny - LPUART8 APB qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart8_apb_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart8_apb_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_2_lpuart8_apb_qdeny_MASK) /*! @} */ /*! @name QACTIVE_STATUS_2 - QACTIVE status register 2 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio1_apb_qactive_MASK (0x40U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio1_apb_qactive_SHIFT (6U) /*! flexio1_apb_qactive - FlexIO1 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio1_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio1_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio1_apb_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio2_apb_qactive_MASK (0x80U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio2_apb_qactive_SHIFT (7U) /*! flexio2_apb_qactive - FlexIO2 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio2_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio2_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_flexio2_apb_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c3_ips_qactive_MASK (0x200U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c3_ips_qactive_SHIFT (9U) /*! lpi2c3_ips_qactive - LPI2C3 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c3_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c3_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c3_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c4_ips_qactive_MASK (0x400U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c4_ips_qactive_SHIFT (10U) /*! lpi2c4_ips_qactive - LPI2C4 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c4_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c4_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c4_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c5_ips_qactive_MASK (0x800U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c5_ips_qactive_SHIFT (11U) /*! lpi2c5_ips_qactive - LPI2C5 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c5_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c5_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c5_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c6_ips_qactive_MASK (0x1000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c6_ips_qactive_SHIFT (12U) /*! lpi2c6_ips_qactive - LPI2C6 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c6_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c6_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c6_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c7_ips_qactive_MASK (0x2000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c7_ips_qactive_SHIFT (13U) /*! lpi2c7_ips_qactive - LPI2C7 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c7_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c7_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c7_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c8_ips_qactive_MASK (0x4000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c8_ips_qactive_SHIFT (14U) /*! lpi2c8_ips_qactive - LPI2C8 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c8_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c8_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpi2c8_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi3_ips_qactive_MASK (0x10000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi3_ips_qactive_SHIFT (16U) /*! lpspi3_ips_qactive - LPSPI3 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi3_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi3_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi3_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi4_ips_qactive_MASK (0x20000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi4_ips_qactive_SHIFT (17U) /*! lpspi4_ips_qactive - LPSPI4 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi4_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi4_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi4_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi5_ips_qactive_MASK (0x40000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi5_ips_qactive_SHIFT (18U) /*! lpspi5_ips_qactive - LPSPI5 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi5_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi5_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi5_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi6_ips_qactive_MASK (0x80000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi6_ips_qactive_SHIFT (19U) /*! lpspi6_ips_qactive - LPSPI6 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi6_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi6_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi6_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi7_ips_qactive_MASK (0x100000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi7_ips_qactive_SHIFT (20U) /*! lpspi7_ips_qactive - LPSPI7 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi7_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi7_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi7_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi8_ips_qactive_MASK (0x200000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi8_ips_qactive_SHIFT (21U) /*! lpspi8_ips_qactive - LPSPI8 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi8_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi8_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpspi8_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart3_apb_qactive_MASK (0x400000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart3_apb_qactive_SHIFT (22U) /*! lpuart3_apb_qactive - LPUART3 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart3_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart3_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart3_apb_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart4_apb_qactive_MASK (0x800000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart4_apb_qactive_SHIFT (23U) /*! lpuart4_apb_qactive - LPUART4 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart4_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart4_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart4_apb_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart5_apb_qactive_MASK (0x1000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart5_apb_qactive_SHIFT (24U) /*! lpuart5_apb_qactive - LPUART5 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart5_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart5_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart5_apb_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart6_apb_qactive_MASK (0x2000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart6_apb_qactive_SHIFT (25U) /*! lpuart6_apb_qactive - LPUART6 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart6_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart6_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart6_apb_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart7_apb_qactive_MASK (0x4000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart7_apb_qactive_SHIFT (26U) /*! lpuart7_apb_qactive - LPUART7 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart7_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart7_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart7_apb_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart8_apb_qactive_MASK (0x8000000U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart8_apb_qactive_SHIFT (27U) /*! lpuart8_apb_qactive - LPUART8 APB qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart8_apb_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart8_apb_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_2_lpuart8_apb_qactive_MASK) /*! @} */ /*! @name QREQ_CTL_3 - QREQ control register 3 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai3_ips_qreq_n_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai3_ips_qreq_n_SHIFT (0U) /*! sai3_ips_qreq_n - SAI3 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai3_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai3_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai3_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai4_ips_qreq_n_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai4_ips_qreq_n_SHIFT (1U) /*! sai4_ips_qreq_n - SAI4 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai4_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai4_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai4_ips_qreq_n_MASK) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai5_ips_qreq_n_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai5_ips_qreq_n_SHIFT (2U) /*! sai5_ips_qreq_n - SAI5 IPS qreq_n control */ #define BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai5_ips_qreq_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai5_ips_qreq_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QREQ_CTL_3_sai5_ips_qreq_n_MASK) /*! @} */ /*! @name QACCEPT_STATUS_3 - QACCEPT status register 1 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai3_ips_qaccept_n_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai3_ips_qaccept_n_SHIFT (0U) /*! sai3_ips_qaccept_n - SAI3 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai3_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai3_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai3_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai4_ips_qaccept_n_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai4_ips_qaccept_n_SHIFT (1U) /*! sai4_ips_qaccept_n - SAI4 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai4_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai4_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai4_ips_qaccept_n_MASK) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai5_ips_qaccept_n_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai5_ips_qaccept_n_SHIFT (2U) /*! sai5_ips_qaccept_n - SAI5 IPS qaccept_n status */ #define BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai5_ips_qaccept_n(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai5_ips_qaccept_n_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACCEPT_STATUS_3_sai5_ips_qaccept_n_MASK) /*! @} */ /*! @name QDENY_STATUS_3 - QDENY status register 3 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai3_ips_qdeny_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai3_ips_qdeny_SHIFT (0U) /*! sai3_ips_qdeny - SAI3 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai3_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai3_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai3_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai4_ips_qdeny_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai4_ips_qdeny_SHIFT (1U) /*! sai4_ips_qdeny - SAI4 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai4_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai4_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai4_ips_qdeny_MASK) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai5_ips_qdeny_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai5_ips_qdeny_SHIFT (2U) /*! sai5_ips_qdeny - SAI5 IPS qdeny status */ #define BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai5_ips_qdeny(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai5_ips_qdeny_SHIFT)) & BLK_CTRL_WAKEUPMIX_QDENY_STATUS_3_sai5_ips_qdeny_MASK) /*! @} */ /*! @name QACTIVE_STATUS_3 - QACTIVE status register 3 */ /*! @{ */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai3_ips_qactive_MASK (0x1U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai3_ips_qactive_SHIFT (0U) /*! sai3_ips_qactive - SAI3 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai3_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai3_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai3_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai4_ips_qactive_MASK (0x2U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai4_ips_qactive_SHIFT (1U) /*! sai4_ips_qactive - SAI4 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai4_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai4_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai4_ips_qactive_MASK) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai5_ips_qactive_MASK (0x4U) #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai5_ips_qactive_SHIFT (2U) /*! sai5_ips_qactive - SAI5 IPS qactive status */ #define BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai5_ips_qactive(x) (((uint32_t)(((uint32_t)(x)) << BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai5_ips_qactive_SHIFT)) & BLK_CTRL_WAKEUPMIX_QACTIVE_STATUS_3_sai5_ips_qactive_MASK) /*! @} */ /*! * @} */ /* end of group BLK_CTRL_WAKEUPMIX_Register_Masks */ /* BLK_CTRL_WAKEUPMIX - Peripheral instance base addresses */ /** Peripheral WAKEUP__BLK_CTRL_WAKEUPMIX base address */ #define WAKEUP__BLK_CTRL_WAKEUPMIX_BASE (0x42420000u) /** Peripheral WAKEUP__BLK_CTRL_WAKEUPMIX base pointer */ #define WAKEUP__BLK_CTRL_WAKEUPMIX ((BLK_CTRL_WAKEUPMIX_Type *)WAKEUP__BLK_CTRL_WAKEUPMIX_BASE) /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base addresses */ #define BLK_CTRL_WAKEUPMIX_BASE_ADDRS { WAKEUP__BLK_CTRL_WAKEUPMIX_BASE } /** Array initializer of BLK_CTRL_WAKEUPMIX peripheral base pointers */ #define BLK_CTRL_WAKEUPMIX_BASE_PTRS { WAKEUP__BLK_CTRL_WAKEUPMIX } /*! * @} */ /* end of group BLK_CTRL_WAKEUPMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- BNR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup BNR_Peripheral_Access_Layer BNR Peripheral Access Layer * @{ */ /** BNR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x68 */ __IO uint32_t CTRL_CAM; /**< Camera 0 BNR Control Register, array offset: 0x0, array step: 0x68 */ __IO uint32_t YPEAK_CAM; /**< Camera 0 BNR YPEAK register, array offset: 0x4, array step: 0x68 */ __IO uint32_t YEDGE_TH0_CAM; /**< Camera 0 BNR YEdge Threshold 0 Register, array offset: 0x8, array step: 0x68 */ __IO uint32_t YEDGE_SCALE_CAM; /**< Camera 0 BNR Long YEdge Scale Register, array offset: 0xC, array step: 0x68 */ __IO uint32_t YEDGES_TH0_CAM; /**< Camera 0 BNR Short Y Edge Threshold 0 Register, array offset: 0x10, array step: 0x68 */ __IO uint32_t YEDGES_SCALE_CAM; /**< Camera 0 BNR Short YEdge Scale Register, array offset: 0x14, array step: 0x68 */ __IO uint32_t YEDGEA_TH0_CAM; /**< Camera 0 BNR Alpha Y Edge Threshold 0 Register, array offset: 0x18, array step: 0x68 */ __IO uint32_t YEDGEA_SCALE_CAM; /**< Camera 0 BNR Alpha YEdge Scale Register, array offset: 0x1C, array step: 0x68 */ __IO uint32_t YLUMA_X_TH0_CAM; /**< Camera 0 BNR YLuma X Threshold 0 Register, array offset: 0x20, array step: 0x68 */ __IO uint32_t YLUMA_Y_TH_CAM; /**< Camera 0 BNR YLuma Y Threshold Register, array offset: 0x24, array step: 0x68 */ __IO uint32_t YLUMA_SCALE_CAM; /**< Camera 0 BNR YLuma Scale Register, array offset: 0x28, array step: 0x68 */ __IO uint32_t YALPHA_GAIN_CAM; /**< Camera 0 BNR YAlpha Gain Register, array offset: 0x2C, array step: 0x68 */ __IO uint32_t CPEAK_CAM; /**< Camera 0 BNR CPEAK register, array offset: 0x30, array step: 0x68 */ __IO uint32_t CEDGE_TH0_CAM; /**< Camera 0 BNR CEdge Threshold 0 Register, array offset: 0x34, array step: 0x68 */ __IO uint32_t CEDGE_SCALE_CAM; /**< Camera 0 BNR CEdge Scale Register, array offset: 0x38, array step: 0x68 */ __IO uint32_t CEDGES_TH0_CAM; /**< Camera 0 BNR Short CEdge Threshold 0 Register, array offset: 0x3C, array step: 0x68 */ __IO uint32_t CEDGES_SCALE_CAM; /**< Camera 0 BNR Short CEdge Scale Register, array offset: 0x40, array step: 0x68 */ __IO uint32_t CEDGEA_TH0_CAM; /**< Camera 0 BNR Alpha CEdge Threshold 0 Register, array offset: 0x44, array step: 0x68 */ __IO uint32_t CEDGEA_SCALE_CAM; /**< Camera 0 BNR Alpha CEdge Scale Register, array offset: 0x48, array step: 0x68 */ __IO uint32_t CLUMA_X_TH0_CAM; /**< Camera 0 BNR CLuma X Threshold 0 Register, array offset: 0x4C, array step: 0x68 */ __IO uint32_t CLUMA_Y_TH_CAM; /**< Camera 0 BNR CLuma Y Threshold Register, array offset: 0x50, array step: 0x68 */ __IO uint32_t CLUMA_SCALE_CAM; /**< Camera 0 BNR CLuma Scale Register, array offset: 0x54, array step: 0x68 */ __IO uint32_t CALPHA_GAIN_CAM; /**< Camera 0 BNR CAlpha Gain Register, array offset: 0x58, array step: 0x68 */ __I uint32_t EDGE_STAT_CAM; /**< Camera 0BNR Edge Pixel Counter Status Register for L Threshold, array offset: 0x5C, array step: 0x68 */ __I uint32_t EDGES_STAT_CAM; /**< Camera 0BNR Edge Pixel Counter Status Register for S Threshold, array offset: 0x60, array step: 0x68 */ __IO uint32_t STRETCH_CAM; /**< Camera 0 BNR Pixel Stretch (Gain) Register, array offset: 0x64, array step: 0x68 */ } NEO_PIPE1_BNR_CONF[1]; } BNR_Type; /* ---------------------------------------------------------------------------- -- BNR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup BNR_Register_Masks BNR Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 BNR Control Register */ /*! @{ */ #define BNR_CTRL_CAM_OBPP_MASK (0xCU) #define BNR_CTRL_CAM_OBPP_SHIFT (2U) /*! OBPP * 0b00..12 bpp * 0b01..14 bpp * 0b10..16 bpp * 0b11..20 bpp */ #define BNR_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << BNR_CTRL_CAM_OBPP_SHIFT)) & BNR_CTRL_CAM_OBPP_MASK) #define BNR_CTRL_CAM_DEBUG_MASK (0x700U) #define BNR_CTRL_CAM_DEBUG_SHIFT (8U) /*! DEBUG - Debug view for on-target tuning * 0b000..Off * 0b001..Final edge decision vs texture * 0b010..Final edge decision vs black * 0b011..Edge pixel decision according to L filter rule * 0b100..Edge pixel decision according to S filter rule * 0b101..L vs S decision */ #define BNR_CTRL_CAM_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << BNR_CTRL_CAM_DEBUG_SHIFT)) & BNR_CTRL_CAM_DEBUG_MASK) #define BNR_CTRL_CAM_NHOOD_MASK (0x10000U) #define BNR_CTRL_CAM_NHOOD_SHIFT (16U) /*! NHOOD * 0b0..2x2, NHOOD is 2 pixel positions * 0b1..1x1, NHOOD is 1 pixel position */ #define BNR_CTRL_CAM_NHOOD(x) (((uint32_t)(((uint32_t)(x)) << BNR_CTRL_CAM_NHOOD_SHIFT)) & BNR_CTRL_CAM_NHOOD_MASK) #define BNR_CTRL_CAM_ENABLE_MASK (0x80000000U) #define BNR_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..Disabled * 0b1..Enabled */ #define BNR_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BNR_CTRL_CAM_ENABLE_SHIFT)) & BNR_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of BNR_CTRL_CAM */ #define BNR_CTRL_CAM_COUNT (1U) /*! @name YPEAK_CAM - Camera 0 BNR YPEAK register */ /*! @{ */ #define BNR_YPEAK_CAM_PEAK_LOW_MASK (0xFFFU) #define BNR_YPEAK_CAM_PEAK_LOW_SHIFT (0U) #define BNR_YPEAK_CAM_PEAK_LOW(x) (((uint32_t)(((uint32_t)(x)) << BNR_YPEAK_CAM_PEAK_LOW_SHIFT)) & BNR_YPEAK_CAM_PEAK_LOW_MASK) #define BNR_YPEAK_CAM_PEAK_SEL_MASK (0xC000U) #define BNR_YPEAK_CAM_PEAK_SEL_SHIFT (14U) /*! PEAK_SEL * 0b00..Select pixel at 1 position away from the extreme * 0b01..Select pixel at 2 position away from the extreme * 0b10..Select pixel at 3 position away from the extreme * 0b11..Select pixel at 4 position from the extreme (that is median value) */ #define BNR_YPEAK_CAM_PEAK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BNR_YPEAK_CAM_PEAK_SEL_SHIFT)) & BNR_YPEAK_CAM_PEAK_SEL_MASK) #define BNR_YPEAK_CAM_PEAK_HIGH_MASK (0xFFF0000U) #define BNR_YPEAK_CAM_PEAK_HIGH_SHIFT (16U) #define BNR_YPEAK_CAM_PEAK_HIGH(x) (((uint32_t)(((uint32_t)(x)) << BNR_YPEAK_CAM_PEAK_HIGH_SHIFT)) & BNR_YPEAK_CAM_PEAK_HIGH_MASK) #define BNR_YPEAK_CAM_PEAK_OUTSEL_MASK (0x80000000U) #define BNR_YPEAK_CAM_PEAK_OUTSEL_SHIFT (31U) /*! PEAK_OUTSEL * 0b0..No scaling * 0b1..Enable scaling. The clipped output is scaled with either lower scale or higher scale value depending on the clipping level */ #define BNR_YPEAK_CAM_PEAK_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << BNR_YPEAK_CAM_PEAK_OUTSEL_SHIFT)) & BNR_YPEAK_CAM_PEAK_OUTSEL_MASK) /*! @} */ /* The count of BNR_YPEAK_CAM */ #define BNR_YPEAK_CAM_COUNT (1U) /*! @name YEDGE_TH0_CAM - Camera 0 BNR YEdge Threshold 0 Register */ /*! @{ */ #define BNR_YEDGE_TH0_CAM_EDGE_TH0_MASK (0xFFFFFU) #define BNR_YEDGE_TH0_CAM_EDGE_TH0_SHIFT (0U) #define BNR_YEDGE_TH0_CAM_EDGE_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGE_TH0_CAM_EDGE_TH0_SHIFT)) & BNR_YEDGE_TH0_CAM_EDGE_TH0_MASK) /*! @} */ /* The count of BNR_YEDGE_TH0_CAM */ #define BNR_YEDGE_TH0_CAM_COUNT (1U) /*! @name YEDGE_SCALE_CAM - Camera 0 BNR Long YEdge Scale Register */ /*! @{ */ #define BNR_YEDGE_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_YEDGE_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_YEDGE_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGE_SCALE_CAM_SCALE_SHIFT)) & BNR_YEDGE_SCALE_CAM_SCALE_MASK) #define BNR_YEDGE_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_YEDGE_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_YEDGE_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGE_SCALE_CAM_SHIFT_SHIFT)) & BNR_YEDGE_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_YEDGE_SCALE_CAM */ #define BNR_YEDGE_SCALE_CAM_COUNT (1U) /*! @name YEDGES_TH0_CAM - Camera 0 BNR Short Y Edge Threshold 0 Register */ /*! @{ */ #define BNR_YEDGES_TH0_CAM_EDGE_TH0_MASK (0xFFFFFU) #define BNR_YEDGES_TH0_CAM_EDGE_TH0_SHIFT (0U) #define BNR_YEDGES_TH0_CAM_EDGE_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGES_TH0_CAM_EDGE_TH0_SHIFT)) & BNR_YEDGES_TH0_CAM_EDGE_TH0_MASK) /*! @} */ /* The count of BNR_YEDGES_TH0_CAM */ #define BNR_YEDGES_TH0_CAM_COUNT (1U) /*! @name YEDGES_SCALE_CAM - Camera 0 BNR Short YEdge Scale Register */ /*! @{ */ #define BNR_YEDGES_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_YEDGES_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_YEDGES_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGES_SCALE_CAM_SCALE_SHIFT)) & BNR_YEDGES_SCALE_CAM_SCALE_MASK) #define BNR_YEDGES_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_YEDGES_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_YEDGES_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGES_SCALE_CAM_SHIFT_SHIFT)) & BNR_YEDGES_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_YEDGES_SCALE_CAM */ #define BNR_YEDGES_SCALE_CAM_COUNT (1U) /*! @name YEDGEA_TH0_CAM - Camera 0 BNR Alpha Y Edge Threshold 0 Register */ /*! @{ */ #define BNR_YEDGEA_TH0_CAM_EDGE_TH0_MASK (0xFFFFFU) #define BNR_YEDGEA_TH0_CAM_EDGE_TH0_SHIFT (0U) #define BNR_YEDGEA_TH0_CAM_EDGE_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGEA_TH0_CAM_EDGE_TH0_SHIFT)) & BNR_YEDGEA_TH0_CAM_EDGE_TH0_MASK) /*! @} */ /* The count of BNR_YEDGEA_TH0_CAM */ #define BNR_YEDGEA_TH0_CAM_COUNT (1U) /*! @name YEDGEA_SCALE_CAM - Camera 0 BNR Alpha YEdge Scale Register */ /*! @{ */ #define BNR_YEDGEA_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_YEDGEA_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_YEDGEA_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGEA_SCALE_CAM_SCALE_SHIFT)) & BNR_YEDGEA_SCALE_CAM_SCALE_MASK) #define BNR_YEDGEA_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_YEDGEA_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_YEDGEA_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_YEDGEA_SCALE_CAM_SHIFT_SHIFT)) & BNR_YEDGEA_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_YEDGEA_SCALE_CAM */ #define BNR_YEDGEA_SCALE_CAM_COUNT (1U) /*! @name YLUMA_X_TH0_CAM - Camera 0 BNR YLuma X Threshold 0 Register */ /*! @{ */ #define BNR_YLUMA_X_TH0_CAM_TH_MASK (0xFFFFFU) #define BNR_YLUMA_X_TH0_CAM_TH_SHIFT (0U) #define BNR_YLUMA_X_TH0_CAM_TH(x) (((uint32_t)(((uint32_t)(x)) << BNR_YLUMA_X_TH0_CAM_TH_SHIFT)) & BNR_YLUMA_X_TH0_CAM_TH_MASK) /*! @} */ /* The count of BNR_YLUMA_X_TH0_CAM */ #define BNR_YLUMA_X_TH0_CAM_COUNT (1U) /*! @name YLUMA_Y_TH_CAM - Camera 0 BNR YLuma Y Threshold Register */ /*! @{ */ #define BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH0_MASK (0x3FFU) #define BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH0_SHIFT (0U) #define BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH0_SHIFT)) & BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH0_MASK) #define BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH1_MASK (0x3FF0000U) #define BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH1_SHIFT (16U) #define BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH1(x) (((uint32_t)(((uint32_t)(x)) << BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH1_SHIFT)) & BNR_YLUMA_Y_TH_CAM_LUMA_Y_TH1_MASK) /*! @} */ /* The count of BNR_YLUMA_Y_TH_CAM */ #define BNR_YLUMA_Y_TH_CAM_COUNT (1U) /*! @name YLUMA_SCALE_CAM - Camera 0 BNR YLuma Scale Register */ /*! @{ */ #define BNR_YLUMA_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_YLUMA_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_YLUMA_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_YLUMA_SCALE_CAM_SCALE_SHIFT)) & BNR_YLUMA_SCALE_CAM_SCALE_MASK) #define BNR_YLUMA_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_YLUMA_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_YLUMA_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_YLUMA_SCALE_CAM_SHIFT_SHIFT)) & BNR_YLUMA_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_YLUMA_SCALE_CAM */ #define BNR_YLUMA_SCALE_CAM_COUNT (1U) /*! @name YALPHA_GAIN_CAM - Camera 0 BNR YAlpha Gain Register */ /*! @{ */ #define BNR_YALPHA_GAIN_CAM_GAIN_MASK (0xFFFFU) #define BNR_YALPHA_GAIN_CAM_GAIN_SHIFT (0U) #define BNR_YALPHA_GAIN_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << BNR_YALPHA_GAIN_CAM_GAIN_SHIFT)) & BNR_YALPHA_GAIN_CAM_GAIN_MASK) #define BNR_YALPHA_GAIN_CAM_OFFSET_MASK (0xFFFF0000U) #define BNR_YALPHA_GAIN_CAM_OFFSET_SHIFT (16U) #define BNR_YALPHA_GAIN_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << BNR_YALPHA_GAIN_CAM_OFFSET_SHIFT)) & BNR_YALPHA_GAIN_CAM_OFFSET_MASK) /*! @} */ /* The count of BNR_YALPHA_GAIN_CAM */ #define BNR_YALPHA_GAIN_CAM_COUNT (1U) /*! @name CPEAK_CAM - Camera 0 BNR CPEAK register */ /*! @{ */ #define BNR_CPEAK_CAM_PEAK_LOW_MASK (0xFFFU) #define BNR_CPEAK_CAM_PEAK_LOW_SHIFT (0U) #define BNR_CPEAK_CAM_PEAK_LOW(x) (((uint32_t)(((uint32_t)(x)) << BNR_CPEAK_CAM_PEAK_LOW_SHIFT)) & BNR_CPEAK_CAM_PEAK_LOW_MASK) #define BNR_CPEAK_CAM_PEAK_SEL_MASK (0xC000U) #define BNR_CPEAK_CAM_PEAK_SEL_SHIFT (14U) /*! PEAK_SEL * 0b00..Select pixel at 1 position away from the extreme * 0b01..Select pixel at 2 position away from the extreme * 0b10..Select pixel at 3 position away from the extreme * 0b11..Select pixel at 4 position from the extreme (that is median value) */ #define BNR_CPEAK_CAM_PEAK_SEL(x) (((uint32_t)(((uint32_t)(x)) << BNR_CPEAK_CAM_PEAK_SEL_SHIFT)) & BNR_CPEAK_CAM_PEAK_SEL_MASK) #define BNR_CPEAK_CAM_PEAK_HIGH_MASK (0xFFF0000U) #define BNR_CPEAK_CAM_PEAK_HIGH_SHIFT (16U) #define BNR_CPEAK_CAM_PEAK_HIGH(x) (((uint32_t)(((uint32_t)(x)) << BNR_CPEAK_CAM_PEAK_HIGH_SHIFT)) & BNR_CPEAK_CAM_PEAK_HIGH_MASK) #define BNR_CPEAK_CAM_PEAK_OUTSEL_MASK (0x80000000U) #define BNR_CPEAK_CAM_PEAK_OUTSEL_SHIFT (31U) /*! PEAK_OUTSEL * 0b0..No scaling * 0b1..Enable scaling. The clipped output is scaled with either lower scale or higher scale value depending on the clipping level */ #define BNR_CPEAK_CAM_PEAK_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << BNR_CPEAK_CAM_PEAK_OUTSEL_SHIFT)) & BNR_CPEAK_CAM_PEAK_OUTSEL_MASK) /*! @} */ /* The count of BNR_CPEAK_CAM */ #define BNR_CPEAK_CAM_COUNT (1U) /*! @name CEDGE_TH0_CAM - Camera 0 BNR CEdge Threshold 0 Register */ /*! @{ */ #define BNR_CEDGE_TH0_CAM_EDGE_TH0_MASK (0xFFFFFU) #define BNR_CEDGE_TH0_CAM_EDGE_TH0_SHIFT (0U) #define BNR_CEDGE_TH0_CAM_EDGE_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGE_TH0_CAM_EDGE_TH0_SHIFT)) & BNR_CEDGE_TH0_CAM_EDGE_TH0_MASK) /*! @} */ /* The count of BNR_CEDGE_TH0_CAM */ #define BNR_CEDGE_TH0_CAM_COUNT (1U) /*! @name CEDGE_SCALE_CAM - Camera 0 BNR CEdge Scale Register */ /*! @{ */ #define BNR_CEDGE_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_CEDGE_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_CEDGE_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGE_SCALE_CAM_SCALE_SHIFT)) & BNR_CEDGE_SCALE_CAM_SCALE_MASK) #define BNR_CEDGE_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_CEDGE_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_CEDGE_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGE_SCALE_CAM_SHIFT_SHIFT)) & BNR_CEDGE_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_CEDGE_SCALE_CAM */ #define BNR_CEDGE_SCALE_CAM_COUNT (1U) /*! @name CEDGES_TH0_CAM - Camera 0 BNR Short CEdge Threshold 0 Register */ /*! @{ */ #define BNR_CEDGES_TH0_CAM_EDGE_TH0_MASK (0xFFFFFU) #define BNR_CEDGES_TH0_CAM_EDGE_TH0_SHIFT (0U) #define BNR_CEDGES_TH0_CAM_EDGE_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGES_TH0_CAM_EDGE_TH0_SHIFT)) & BNR_CEDGES_TH0_CAM_EDGE_TH0_MASK) /*! @} */ /* The count of BNR_CEDGES_TH0_CAM */ #define BNR_CEDGES_TH0_CAM_COUNT (1U) /*! @name CEDGES_SCALE_CAM - Camera 0 BNR Short CEdge Scale Register */ /*! @{ */ #define BNR_CEDGES_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_CEDGES_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_CEDGES_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGES_SCALE_CAM_SCALE_SHIFT)) & BNR_CEDGES_SCALE_CAM_SCALE_MASK) #define BNR_CEDGES_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_CEDGES_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_CEDGES_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGES_SCALE_CAM_SHIFT_SHIFT)) & BNR_CEDGES_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_CEDGES_SCALE_CAM */ #define BNR_CEDGES_SCALE_CAM_COUNT (1U) /*! @name CEDGEA_TH0_CAM - Camera 0 BNR Alpha CEdge Threshold 0 Register */ /*! @{ */ #define BNR_CEDGEA_TH0_CAM_EDGE_TH0_MASK (0xFFFFFU) #define BNR_CEDGEA_TH0_CAM_EDGE_TH0_SHIFT (0U) #define BNR_CEDGEA_TH0_CAM_EDGE_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGEA_TH0_CAM_EDGE_TH0_SHIFT)) & BNR_CEDGEA_TH0_CAM_EDGE_TH0_MASK) /*! @} */ /* The count of BNR_CEDGEA_TH0_CAM */ #define BNR_CEDGEA_TH0_CAM_COUNT (1U) /*! @name CEDGEA_SCALE_CAM - Camera 0 BNR Alpha CEdge Scale Register */ /*! @{ */ #define BNR_CEDGEA_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_CEDGEA_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_CEDGEA_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGEA_SCALE_CAM_SCALE_SHIFT)) & BNR_CEDGEA_SCALE_CAM_SCALE_MASK) #define BNR_CEDGEA_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_CEDGEA_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_CEDGEA_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_CEDGEA_SCALE_CAM_SHIFT_SHIFT)) & BNR_CEDGEA_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_CEDGEA_SCALE_CAM */ #define BNR_CEDGEA_SCALE_CAM_COUNT (1U) /*! @name CLUMA_X_TH0_CAM - Camera 0 BNR CLuma X Threshold 0 Register */ /*! @{ */ #define BNR_CLUMA_X_TH0_CAM_TH_MASK (0xFFFFFU) #define BNR_CLUMA_X_TH0_CAM_TH_SHIFT (0U) #define BNR_CLUMA_X_TH0_CAM_TH(x) (((uint32_t)(((uint32_t)(x)) << BNR_CLUMA_X_TH0_CAM_TH_SHIFT)) & BNR_CLUMA_X_TH0_CAM_TH_MASK) /*! @} */ /* The count of BNR_CLUMA_X_TH0_CAM */ #define BNR_CLUMA_X_TH0_CAM_COUNT (1U) /*! @name CLUMA_Y_TH_CAM - Camera 0 BNR CLuma Y Threshold Register */ /*! @{ */ #define BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH0_MASK (0x3FFU) #define BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH0_SHIFT (0U) #define BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH0(x) (((uint32_t)(((uint32_t)(x)) << BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH0_SHIFT)) & BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH0_MASK) #define BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH1_MASK (0x3FF0000U) #define BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH1_SHIFT (16U) #define BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH1(x) (((uint32_t)(((uint32_t)(x)) << BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH1_SHIFT)) & BNR_CLUMA_Y_TH_CAM_LUMA_Y_TH1_MASK) /*! @} */ /* The count of BNR_CLUMA_Y_TH_CAM */ #define BNR_CLUMA_Y_TH_CAM_COUNT (1U) /*! @name CLUMA_SCALE_CAM - Camera 0 BNR CLuma Scale Register */ /*! @{ */ #define BNR_CLUMA_SCALE_CAM_SCALE_MASK (0xFFFFU) #define BNR_CLUMA_SCALE_CAM_SCALE_SHIFT (0U) #define BNR_CLUMA_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << BNR_CLUMA_SCALE_CAM_SCALE_SHIFT)) & BNR_CLUMA_SCALE_CAM_SCALE_MASK) #define BNR_CLUMA_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define BNR_CLUMA_SCALE_CAM_SHIFT_SHIFT (16U) #define BNR_CLUMA_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << BNR_CLUMA_SCALE_CAM_SHIFT_SHIFT)) & BNR_CLUMA_SCALE_CAM_SHIFT_MASK) /*! @} */ /* The count of BNR_CLUMA_SCALE_CAM */ #define BNR_CLUMA_SCALE_CAM_COUNT (1U) /*! @name CALPHA_GAIN_CAM - Camera 0 BNR CAlpha Gain Register */ /*! @{ */ #define BNR_CALPHA_GAIN_CAM_GAIN_MASK (0xFFFFU) #define BNR_CALPHA_GAIN_CAM_GAIN_SHIFT (0U) #define BNR_CALPHA_GAIN_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << BNR_CALPHA_GAIN_CAM_GAIN_SHIFT)) & BNR_CALPHA_GAIN_CAM_GAIN_MASK) #define BNR_CALPHA_GAIN_CAM_OFFSET_MASK (0xFFFF0000U) #define BNR_CALPHA_GAIN_CAM_OFFSET_SHIFT (16U) #define BNR_CALPHA_GAIN_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << BNR_CALPHA_GAIN_CAM_OFFSET_SHIFT)) & BNR_CALPHA_GAIN_CAM_OFFSET_MASK) /*! @} */ /* The count of BNR_CALPHA_GAIN_CAM */ #define BNR_CALPHA_GAIN_CAM_COUNT (1U) /*! @name EDGE_STAT_CAM - Camera 0BNR Edge Pixel Counter Status Register for L Threshold */ /*! @{ */ #define BNR_EDGE_STAT_CAM_EDGE_PIXELS_MASK (0xFFFFFFU) #define BNR_EDGE_STAT_CAM_EDGE_PIXELS_SHIFT (0U) #define BNR_EDGE_STAT_CAM_EDGE_PIXELS(x) (((uint32_t)(((uint32_t)(x)) << BNR_EDGE_STAT_CAM_EDGE_PIXELS_SHIFT)) & BNR_EDGE_STAT_CAM_EDGE_PIXELS_MASK) /*! @} */ /* The count of BNR_EDGE_STAT_CAM */ #define BNR_EDGE_STAT_CAM_COUNT (1U) /*! @name EDGES_STAT_CAM - Camera 0BNR Edge Pixel Counter Status Register for S Threshold */ /*! @{ */ #define BNR_EDGES_STAT_CAM_EDGE_PIXELS_MASK (0xFFFFFFU) #define BNR_EDGES_STAT_CAM_EDGE_PIXELS_SHIFT (0U) #define BNR_EDGES_STAT_CAM_EDGE_PIXELS(x) (((uint32_t)(((uint32_t)(x)) << BNR_EDGES_STAT_CAM_EDGE_PIXELS_SHIFT)) & BNR_EDGES_STAT_CAM_EDGE_PIXELS_MASK) /*! @} */ /* The count of BNR_EDGES_STAT_CAM */ #define BNR_EDGES_STAT_CAM_COUNT (1U) /*! @name STRETCH_CAM - Camera 0 BNR Pixel Stretch (Gain) Register */ /*! @{ */ #define BNR_STRETCH_CAM_GAIN_MASK (0xFFFFU) #define BNR_STRETCH_CAM_GAIN_SHIFT (0U) #define BNR_STRETCH_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << BNR_STRETCH_CAM_GAIN_SHIFT)) & BNR_STRETCH_CAM_GAIN_MASK) /*! @} */ /* The count of BNR_STRETCH_CAM */ #define BNR_STRETCH_CAM_COUNT (1U) /*! * @} */ /* end of group BNR_Register_Masks */ /* BNR - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__BNR base address */ #define CAMERA__ISP__BNR_BASE (0x4AE00800u) /** Peripheral CAMERA__ISP__BNR base pointer */ #define CAMERA__ISP__BNR ((BNR_Type *)CAMERA__ISP__BNR_BASE) /** Array initializer of BNR peripheral base addresses */ #define BNR_BASE_ADDRS { CAMERA__ISP__BNR_BASE } /** Array initializer of BNR peripheral base pointers */ #define BNR_BASE_PTRS { CAMERA__ISP__BNR } /*! * @} */ /* end of group BNR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CACHE_ECC_MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CACHE_ECC_MCM_Peripheral_Access_Layer CACHE_ECC_MCM Peripheral Access Layer * @{ */ /** CACHE_ECC_MCM - Register Layout Typedef */ typedef struct { __IO uint32_t CACHE_ECCR; /**< CACHE ECC Control, offset: 0x0 */ uint8_t RESERVED_0[28]; __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x20 */ __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable, offset: 0x24 */ __IO uint32_t INT_SIG_EN; /**< Interrupt Enable, offset: 0x28 */ uint8_t RESERVED_1[48]; __I uint32_t CODE_CACHE_ECC_SINGLE_ERROR_INFO; /**< Code Cache Single-Bit ECC Error Information, offset: 0x5C */ __I uint32_t CODE_CACHE_ECC_SINGLE_ERROR_ADDR; /**< Code Cache Single-Bit ECC Error Address, offset: 0x60 */ uint8_t RESERVED_2[4]; __I uint32_t CODE_CACHE_ECC_MULTI_ERROR_INFO; /**< Code Cache Multibit ECC Error Information, offset: 0x68 */ uint8_t RESERVED_3[8]; __I uint32_t SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO; /**< System Cache Single-Bit ECC Error Information, offset: 0x74 */ __I uint32_t SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR; /**< System Cache Single-Bit ECC Error Address, offset: 0x78 */ uint8_t RESERVED_4[4]; __I uint32_t SYSTEM_CACHE_ECC_MULTI_ERROR_INFO; /**< System Cache Multibit ECC Error Information, offset: 0x80 */ __I uint32_t SYSTEM_CACHE_ECC_MULTI_ERROR_DATA; /**< System Cache Multibit ECC Error Data, offset: 0x84 */ uint8_t RESERVED_5[4]; __IO uint32_t CODE_CACHE_TAG0_ECC_ERROR_INJEC; /**< Code Cache TAG0 ECC Error Injection, offset: 0x8C */ __IO uint32_t CODE_CACHE_TAG1_ECC_ERROR_INJEC; /**< Code Cache TAG1 ECC Error Injection, offset: 0x90 */ __IO uint32_t CODE_CACHE_DATA0_ECC_ERROR_INJEC; /**< Code Cache DATA0 ECC Error Injection, offset: 0x94 */ __IO uint32_t CODE_CACHE_DATA1_ECC_ERROR_INJEC; /**< Code Cache DATA1 ECC Error Injection, offset: 0x98 */ __IO uint32_t SYTEM_CACHE_TAG0_ECC_ERROR_INJEC; /**< System Cache TAG0 ECC Error Injection, offset: 0x9C */ __IO uint32_t SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC; /**< System Cache TAG1 ECC Error Injection, offset: 0xA0 */ __IO uint32_t SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC; /**< System Cache DATA0 ECC Error Injection, offset: 0xA4 */ __IO uint32_t STSTEM_CACHE_DATA1_ECC_ERROR_INJEC; /**< System Cache DATA1 ECC Error Injection, offset: 0xA8 */ __IO uint32_t FCCU_SW_FAULTS; /**< FCCU Software Faults, offset: 0xAC */ } CACHE_ECC_MCM_Type; /* ---------------------------------------------------------------------------- -- CACHE_ECC_MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CACHE_ECC_MCM_Register_Masks CACHE_ECC_MCM Register Masks * @{ */ /*! @name CACHE_ECCR - CACHE ECC Control */ /*! @{ */ #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_MASK (0x1U) #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_SHIFT (0U) /*! WECC_DIS - Disable CACHE ECC Write Generation * 0b1..Disable * 0b0..Enable */ #define CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_SHIFT)) & CACHE_ECC_MCM_CACHE_ECCR_WECC_DIS_MASK) #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_MASK (0x2U) #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_SHIFT (1U) /*! RECC_DIS - Disable Cache ECC Read Check * 0b1..Disable * 0b0..Enable */ #define CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_SHIFT)) & CACHE_ECC_MCM_CACHE_ECCR_RECC_DIS_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_MASK (0x100U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_SHIFT (8U) /*! CODE_CACHE_ECC_ERRM_INT - Code Cache Access Multibit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_MASK (0x200U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_SHIFT (9U) /*! CODE_CACHE_ECC_ERRS_INT - Code Cache Access Single-Bit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_MASK (0x400U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_SHIFT (10U) /*! CODE_CACHE_ECC_ERRM_OVER_INT - Code Cache Access Multiple Multibit ECC Error Interrupt Status * 0b0..Not more than one error * 0b1..Multiple errors * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRM_OVER_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_MASK (0x800U) #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_SHIFT (11U) /*! CODE_CACHE_ECC_ERRS_OVER_INT - Code Cache Access Multiple Single-Bit ECC Error Interrupt Status * 0b0..Not more than one error * 0b1..Multiple errors * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_CODE_CACHE_ECC_ERRS_OVER_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_MASK (0x1000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_SHIFT (12U) /*! SYSTEM_CACHE_ECC_ERRM_INT - System Cache Access Multibit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_MASK (0x2000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_SHIFT (13U) /*! SYSTEM_CACHE_ECC_ERRS_INT - System Cache Access Single-Bit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_MASK (0x4000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_SHIFT (14U) /*! SYSTEM_CACHE_ECC_ERRM_OVER_INT - System Cache Access Multiple Multibit ECC Error Interrupt Status * 0b0..Not more than one error * 0b1..Multiple errors * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRM_OVER_INT_MASK) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_MASK (0x8000U) #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_SHIFT (15U) /*! SYSTEM_CACHE_ECC_ERRS_OVER_INT - System Cache Access Multiple Single-Bit ECC Error Interrupt Status * 0b0..Not more than one error * 0b1..Multiple errors * 0b0..No effect * 0b1..Clear the flag */ #define CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_SHIFT)) & CACHE_ECC_MCM_INT_STATUS_SYSTEM_CACHE_ECC_ERRS_OVER_INT_MASK) /*! @} */ /*! @name INT_STAT_EN - Interrupt Status Enable */ /*! @{ */ #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_MASK (0x100U) #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_SHIFT (8U) /*! CODE_CACHE_ERRM_INT_EN - Code Cache Access Multibit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_INT_EN_MASK) #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_MASK (0x200U) #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_SHIFT (9U) /*! CODE_CACHE_ERRS_INT_EN - Code Cache Access Single-Bit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_INT_EN_MASK) #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_MASK (0x400U) #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_SHIFT (10U) /*! CODE_CACHE_ERRM_OVER_INT_EN - Code Cache Access Multiple Multibit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRM_OVER_INT_EN_MASK) #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_MASK (0x800U) #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_SHIFT (11U) /*! CODE_CACHE_ERRS_OVER_INT_EN - Code Cache Access Multiple Single-Bit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_CODE_CACHE_ERRS_OVER_INT_EN_MASK) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_MASK (0x1000U) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_SHIFT (12U) /*! SYSTEM_CACHE_ECC_ERRM_INT_EN - System Cache Access Multibit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_INT_EN_MASK) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_MASK (0x2000U) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_SHIFT (13U) /*! SYSTEM_CACHE_ECC_ERRS_INT_EN - System Cache Access Single-Bit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_INT_EN_MASK) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_MASK (0x4000U) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_SHIFT (14U) /*! SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN - System Cache Access Multiple Multibit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRM_OVER_INT_EN_MASK) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_MASK (0x8000U) #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_SHIFT (15U) /*! SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN - System Cache Access Multiple Single-Bit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_SHIFT)) & CACHE_ECC_MCM_INT_STAT_EN_SYSTEM_CACHE_ECC_ERRS_OVER_INT_EN_MASK) /*! @} */ /*! @name INT_SIG_EN - Interrupt Enable */ /*! @{ */ #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_MASK (0x100U) #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_SHIFT (8U) /*! CODE_CACHE_ERRM_INT_SIG_EN - Code Cache Access Multibit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_INT_SIG_EN_MASK) #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_MASK (0x200U) #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_SHIFT (9U) /*! CODE_CACHE_ERRS_INT_SIG_EN - Code Cache Access Single-Bit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_INT_SIG_EN_MASK) #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_MASK (0x400U) #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT (10U) /*! CODE_CACHE_ERRM_OVER_INT_SIG_EN - Code Cache Access Multiple Multibit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRM_OVER_INT_SIG_EN_MASK) #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_MASK (0x800U) #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT (11U) /*! CODE_CACHE_ERRS_OVER_INT_SIG_EN - Code Cache Access Multiple Single-Bit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_CODE_CACHE_ERRS_OVER_INT_SIG_EN_MASK) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_MASK (0x1000U) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_SHIFT (12U) /*! SYSTEM_CACHE_ERRM_INT_SIG_EN - System Cache Access Multibit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_INT_SIG_EN_MASK) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_MASK (0x2000U) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_SHIFT (13U) /*! SYSTEM_CACHE_ERRS_INT_SIG_EN - System Cache Access Single-Bit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_INT_SIG_EN_MASK) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_MASK (0x4000U) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT (14U) /*! SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN - System Cache Access Multiple Multibit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRM_OVER_INT_SIG_EN_MASK) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_MASK (0x8000U) #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT (15U) /*! SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN - System Cache Access Multiple Single-Bit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_SHIFT)) & CACHE_ECC_MCM_INT_SIG_EN_SYSTEM_CACHE_ERRS_OVER_INT_SIG_EN_MASK) /*! @} */ /*! @name CODE_CACHE_ECC_SINGLE_ERROR_INFO - Code Cache Single-Bit ECC Error Information */ /*! @{ */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_MASK (0x1U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_SHIFT (0U) /*! CODE_CACHE_ECCS_TAG - Code Cache Single-Bit ECC Error * 0b1..Tag * 0b0..Data */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_TAG_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_MASK (0x2U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_SHIFT (1U) /*! CODE_CACHE_ECCS_CMD - Code Cache Single-Bit ECC Error on Cache Command * 0b0..No error * 0b1..Error */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_CMD_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_MASK (0xF0U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_SHIFT (4U) /*! CODE_CACHE_ECCS_EFMST - Code Cache Single-Bit ECC Error Master Number */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFMST_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_MASK (0x3F00U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_SHIFT (8U) /*! CODE_CACHE_ECCS_EFPRT - Code Cache Single-Bit ECC Error Protection */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFPRT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_MASK (0x7F0000U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_SHIFT (16U) /*! CODE_CACHE_ECCS_EFSYN - Code Cache Single-Bit ECC Error Corresponding Syndrome */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_INFO_CODE_CACHE_ECCS_EFSYN_MASK) /*! @} */ /*! @name CODE_CACHE_ECC_SINGLE_ERROR_ADDR - Code Cache Single-Bit ECC Error Address */ /*! @{ */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_SHIFT (0U) /*! CODE_CACHE_ECCS_ERRED_ADDR - Code Cache Single-Bit ECC Error Address */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_SINGLE_ERROR_ADDR_CODE_CACHE_ECCS_ERRED_ADDR_MASK) /*! @} */ /*! @name CODE_CACHE_ECC_MULTI_ERROR_INFO - Code Cache Multibit ECC Error Information */ /*! @{ */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_MASK (0x1U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_SHIFT (0U) /*! CODE_CACHE_ECCM_TAG - Code Cache Multibit ECC Error * 0b1..Tag * 0b0..Data */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_TAG_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_MASK (0x2U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_SHIFT (1U) /*! CODE_CACHE_ECCM_CMD - Code Cache Multibit ECC Error on Code Cache Command * 0b0..No error * 0b1..Error */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_CMD_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_MASK (0xF0U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_SHIFT (4U) /*! CODE_CACHE_ECCM_EFMST - Code Cache Multibit ECC Error Master Number */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFMST_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_MASK (0x3F00U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_SHIFT (8U) /*! CODE_CACHE_ECCM_EFPRT - Code Cache Multibit ECC Error Protection */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFPRT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_MASK (0x7F0000U) #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_SHIFT (16U) /*! CODE_CACHE_ECCM_EFSYN - Code Cache Multibit ECC Error Corresponding Syndrome */ #define CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_ECC_MULTI_ERROR_INFO_CODE_CACHE_ECCM_EFSYN_MASK) /*! @} */ /*! @name SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO - System Cache Single-Bit ECC Error Information */ /*! @{ */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_MASK (0x1U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_SHIFT (0U) /*! SYSTEM_CACHE_ECCS_TAG - System Cache Single-Bit ECC Error * 0b1..Tag * 0b0..Data */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_TAG_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_MASK (0x2U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_SHIFT (1U) /*! SYSTEM_CACHE_ECCS_CMD - System Cache Single-Bit ECC Error on Cache Command * 0b0..No error * 0b1..Error */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_CMD_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_MASK (0xF0U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_SHIFT (4U) /*! SYSTEM_CACHE_ECCS_EFMST - System Cache Single-Bit ECC Error Master Number */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFMST_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_MASK (0x3F00U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_SHIFT (8U) /*! SYSTEM_CACHE_ECCS_EFPRT - System Cache Single-Bit ECC Error Protection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFPRT_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_MASK (0x7F0000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_SHIFT (16U) /*! SYSTEM_CACHE_ECCS_EFSYN - System Cache Single-Bit ECC Error Corresponding Syndrome */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_INFO_SYSTEM_CACHE_ECCS_EFSYN_MASK) /*! @} */ /*! @name SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR - System Cache Single-Bit ECC Error Address */ /*! @{ */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_SHIFT (0U) /*! SYSTEM_CACHE_ECCS_ERRED_ADDR - System Cache Single-Bit ECC Error Address */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_SINGLE_ERROR_ADDR_SYSTEM_CACHE_ECCS_ERRED_ADDR_MASK) /*! @} */ /*! @name SYSTEM_CACHE_ECC_MULTI_ERROR_INFO - System Cache Multibit ECC Error Information */ /*! @{ */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_MASK (0x1U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_SHIFT (0U) /*! SYSTEM_CACHE_ECCM_TAG - System Cache Multibit ECC Error * 0b1..Tag * 0b0..Data */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_TAG_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_MASK (0x2U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_SHIFT (1U) /*! SYSTEM_CACHE_ECCM_CMD - System Cache Multibit ECC Error on System Cache Command * 0b0..No error * 0b1..Error */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_CMD_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_MASK (0xF0U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_SHIFT (4U) /*! SYSTEM_CACHE_ECCM_EFMST - System Cache Multibit ECC Error Master Number */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFMST_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_MASK (0x3F00U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_SHIFT (8U) /*! SYSTEM_CACHE_ECCM_EFPRT - System Cache Multibit ECC Error Protection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFPRT_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_MASK (0x7F0000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_SHIFT (16U) /*! SYSTEM_CACHE_ECCM_EFSYN - System Cache Multibit ECC Error Corresponding Syndrome */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_INFO_SYSTEM_CACHE_ECCM_EFSYN_MASK) /*! @} */ /*! @name SYSTEM_CACHE_ECC_MULTI_ERROR_DATA - System Cache Multibit ECC Error Data */ /*! @{ */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU) #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_SHIFT (0U) /*! SYSTEM_CACHE_ECCM_ERRED_DATA - System Cache Multibit ECC Error Data */ #define CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_ECC_MULTI_ERROR_DATA_SYSTEM_CACHE_ECCM_ERRED_DATA_MASK) /*! @} */ /*! @name CODE_CACHE_TAG0_ECC_ERROR_INJEC - Code Cache TAG0 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_SHIFT (0U) /*! CODE_CACHE_TAG0_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR1BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_SHIFT (8U) /*! CODE_CACHE_TAG0_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_ERR2BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_SHIFT (16U) /*! CODE_CACHE_TAG0_FR11BI - Force One 1-Bit Data Inversion on Code Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR11BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_SHIFT (17U) /*! CODE_CACHE_TAG0_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FR1NCI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_SHIFT (18U) /*! CODE_CACHE_TAG0_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRC1BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_SHIFT (19U) /*! CODE_CACHE_TAG0_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG0_ECC_ERROR_INJEC_CODE_CACHE_TAG0_FRCNCI_MASK) /*! @} */ /*! @name CODE_CACHE_TAG1_ECC_ERROR_INJEC - Code Cache TAG1 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_SHIFT (0U) /*! CODE_CACHE_TAG1_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR1BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_SHIFT (8U) /*! CODE_CACHE_TAG1_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_ERR2BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_SHIFT (16U) /*! CODE_CACHE_TAG1_FR11BI - Force One 1-Bit Data Inversion on Code Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR11BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_SHIFT (17U) /*! CODE_CACHE_TAG1_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FR1NCI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_SHIFT (18U) /*! CODE_CACHE_TAG1_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRC1BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_SHIFT (19U) /*! CODE_CACHE_TAG1_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_TAG1_ECC_ERROR_INJEC_CODE_CACHE_TAG1_FRCNCI_MASK) /*! @} */ /*! @name CODE_CACHE_DATA0_ECC_ERROR_INJEC - Code Cache DATA0 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_SHIFT (0U) /*! CODE_CACHE_DATA0_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR1BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_SHIFT (8U) /*! CODE_CACHE_DATA0_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_ERR2BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_SHIFT (16U) /*! CODE_CACHE_DATA0_FR11BI - Force One 1-Bit Data Inversion on Code Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR11BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_SHIFT (17U) /*! CODE_CACHE_DATA0_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FR1NCI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_SHIFT (18U) /*! CODE_CACHE_DATA0_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRC1BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_SHIFT (19U) /*! CODE_CACHE_DATA0_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA0_ECC_ERROR_INJEC_CODE_CACHE_DATA0_FRCNCI_MASK) /*! @} */ /*! @name CODE_CACHE_DATA1_ECC_ERROR_INJEC - Code Cache DATA1 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_SHIFT (0U) /*! CODE_CACHE_DATA1_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR1BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_SHIFT (8U) /*! CODE_CACHE_DATA1_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_ERR2BIT_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_SHIFT (16U) /*! CODE_CACHE_DATA1_FR11BI - Force One 1-Bit Data Inversion on Code Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR11BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_SHIFT (17U) /*! CODE_CACHE_DATA1_FR1NCI - Force One Noncorrectable Data Inversion on Code Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FR1NCI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_SHIFT (18U) /*! CODE_CACHE_DATA1_FRC1BI - Force Continuous 1-Bit Data Inversions on Code Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRC1BI_MASK) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_SHIFT (19U) /*! CODE_CACHE_DATA1_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_CODE_CACHE_DATA1_ECC_ERROR_INJEC_CODE_CACHE_DATA1_FRCNCI_MASK) /*! @} */ /*! @name SYTEM_CACHE_TAG0_ECC_ERROR_INJEC - System Cache TAG0 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_SHIFT (0U) /*! SYSTEM_CACHE_TAG0_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR1BIT_MASK) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_SHIFT (8U) /*! SYSTEM_CACHE_TAG0_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_ERR2BIT_MASK) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_SHIFT (16U) /*! SYSTEM_CACHE_TAG0_FR11BI - Force One 1-Bit Data Inversion on System Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR11BI_MASK) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_SHIFT (17U) /*! SYSTEM_CACHE_TAG0_FR1NCI - Force One Noncorrectable Data Inversion on System Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FR1NCI_MASK) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_SHIFT (18U) /*! SYSTEM_CACHE_TAG0_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRC1BI_MASK) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_SHIFT (19U) /*! SYSTEM_CACHE_TAG0_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache TAG0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_SYTEM_CACHE_TAG0_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG0_FRCNCI_MASK) /*! @} */ /*! @name SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC - System Cache TAG1 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_SHIFT (0U) /*! SYSTEM_CACHE_TAG1_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_ERR1BIT_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_SHIFT (8U) /*! SYSTEMCACHE_TAG1_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEMCACHE_TAG1_ERR2BIT_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_SHIFT (16U) /*! SYSTEM_CACHE_TAG1_FR11BI - Force One 1-Bit Data Inversion on System Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR11BI_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_SHIFT (17U) /*! SYSTEM_CACHE_TAG1_FR1NCI - Force One Noncorrectable Data Inversion on System Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FR1NCI_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_SHIFT (18U) /*! SYSTEM_CACHE_TAG1_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRC1BI_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_SHIFT (19U) /*! SYSTEM_CACHE_TAG1_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache TAG1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_TAG1_ECC_ERROR_INJEC_SYSTEM_CACHE_TAG1_FRCNCI_MASK) /*! @} */ /*! @name SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC - System Cache DATA0 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_SHIFT (0U) /*! SYSTEM_CACHE_DATA0_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR1BIT_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_SHIFT (8U) /*! SYSTEM_CACHE_DATA0_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_ERR2BIT_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_SHIFT (16U) /*! SYSTEM_CACHE_DATA0_FR11BI - Force One 1-Bit Data Inversion on System Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR11BI_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_SHIFT (17U) /*! SYSTEM_CACHE_DATA0_FR1NCI - Force One Noncorrectable Data Inversion on System Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FR1NCI_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_SHIFT (18U) /*! SYSTEM_CACHE_DATA0_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRC1BI_MASK) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_SHIFT (19U) /*! SYSTEM_CACHE_DATA0_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache DATA0 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_SHIFT)) & CACHE_ECC_MCM_SYSTEM_CACHE_DATA0_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA0_FRCNCI_MASK) /*! @} */ /*! @name STSTEM_CACHE_DATA1_ECC_ERROR_INJEC - System Cache DATA1 ECC Error Injection */ /*! @{ */ #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_MASK (0x7FU) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_SHIFT (0U) /*! SYSTEM_CACHE_DATA1_ERR1BIT - Position of First Bit to Inject ECC Error */ #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR1BIT_MASK) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_MASK (0x7F00U) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_SHIFT (8U) /*! SYSTEM_CACHE_DATA1_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_ERR2BIT_MASK) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_MASK (0x10000U) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_SHIFT (16U) /*! SYSTEM_CACHE_DATA1_FR11BI - Force One 1-Bit Data Inversion on System Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR11BI_MASK) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_MASK (0x20000U) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_SHIFT (17U) /*! SYSTEM_CACHE_DATA1_FR1NCI - Force One Noncorrectable Data Inversion on System Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FR1NCI_MASK) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_MASK (0x40000U) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_SHIFT (18U) /*! SYSTEM_CACHE_DATA1_FRC1BI - Force Continuous 1-Bit Data Inversions on System Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRC1BI_MASK) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_MASK (0x80000U) #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_SHIFT (19U) /*! SYSTEM_CACHE_DATA1_FRCNCI - Force Continuous Noncorrectable Data Inversions on System Cache DATA1 Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_SHIFT)) & CACHE_ECC_MCM_STSTEM_CACHE_DATA1_ECC_ERROR_INJEC_SYSTEM_CACHE_DATA1_FRCNCI_MASK) /*! @} */ /*! @name FCCU_SW_FAULTS - FCCU Software Faults */ /*! @{ */ #define CACHE_ECC_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_MASK (0x3FU) #define CACHE_ECC_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_SHIFT (0U) /*! FCCU_SW_FAULTS - FCCU Software Faults */ #define CACHE_ECC_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS(x) (((uint32_t)(((uint32_t)(x)) << CACHE_ECC_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_SHIFT)) & CACHE_ECC_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_MASK) /*! @} */ /*! * @} */ /* end of group CACHE_ECC_MCM_Register_Masks */ /* CACHE_ECC_MCM - Peripheral instance base addresses */ /** Peripheral AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM base address */ #define AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM_BASE (0x44401000u) /** Peripheral AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM base pointer */ #define AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM ((CACHE_ECC_MCM_Type *)AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM_BASE) /** Array initializer of CACHE_ECC_MCM peripheral base addresses */ #define CACHE_ECC_MCM_BASE_ADDRS { AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM_BASE } /** Array initializer of CACHE_ECC_MCM peripheral base pointers */ #define CACHE_ECC_MCM_BASE_PTRS { AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM } /*! * @} */ /* end of group CACHE_ECC_MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_DSI_CAMID_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_CAMID_CSR_Peripheral_Access_Layer CAMERA_DSI_CAMID_CSR Peripheral Access Layer * @{ */ /** CAMERA_DSI_CAMID_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t ISP_CAMID; /**< ISP CAMID, offset: 0x0 */ } CAMERA_DSI_CAMID_CSR_Type; /* ---------------------------------------------------------------------------- -- CAMERA_DSI_CAMID_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_CAMID_CSR_Register_Masks CAMERA_DSI_CAMID_CSR Register Masks * @{ */ /*! @name ISP_CAMID - ISP CAMID */ /*! @{ */ #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER0_MASK (0x7U) #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER0_SHIFT (0U) /*! AWUSER0 - AXI USER setting - WRITE bus 0 */ #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER0_SHIFT)) & CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER0_MASK) #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER1_MASK (0x70U) #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER1_SHIFT (4U) /*! AWUSER1 - AXI USER setting - WRITE bus 1 */ #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER1_SHIFT)) & CAMERA_DSI_CAMID_CSR_ISP_CAMID_AWUSER1_MASK) #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER0_MASK (0x700U) #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER0_SHIFT (8U) /*! ARUSER0 - AXI USER setting - READ bus 0 */ #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER0_SHIFT)) & CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER0_MASK) #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER1_MASK (0x7000U) #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER1_SHIFT (12U) /*! ARUSER1 - AXI USER setting - READ bus 1 */ #define CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER1_SHIFT)) & CAMERA_DSI_CAMID_CSR_ISP_CAMID_ARUSER1_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_DSI_CAMID_CSR_Register_Masks */ /* CAMERA_DSI_CAMID_CSR - Peripheral instance base addresses */ /** Peripheral CAMERA__DSI_CAMID_CSR base address */ #define CAMERA__DSI_CAMID_CSR_BASE (0x4ADE0000u) /** Peripheral CAMERA__DSI_CAMID_CSR base pointer */ #define CAMERA__DSI_CAMID_CSR ((CAMERA_DSI_CAMID_CSR_Type *)CAMERA__DSI_CAMID_CSR_BASE) /** Array initializer of CAMERA_DSI_CAMID_CSR peripheral base addresses */ #define CAMERA_DSI_CAMID_CSR_BASE_ADDRS { CAMERA__DSI_CAMID_CSR_BASE } /** Array initializer of CAMERA_DSI_CAMID_CSR peripheral base pointers */ #define CAMERA_DSI_CAMID_CSR_BASE_PTRS { CAMERA__DSI_CAMID_CSR } /*! * @} */ /* end of group CAMERA_DSI_CAMID_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_DSI_MASTER_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_MASTER_CSR_Peripheral_Access_Layer CAMERA_DSI_MASTER_CSR Peripheral Access Layer * @{ */ /** CAMERA_DSI_MASTER_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t DSI_CLOCK_GATING_CONTROL; /**< DSI Clock Gating Control, offset: 0x0 */ __IO uint32_t DSI_PIXEL_LINK_CONTROL; /**< DSI Pixel Link Control, offset: 0x4 */ __IO uint32_t DSI_CLOCK_SETTING; /**< DSI Clock Setting, offset: 0x8 */ } CAMERA_DSI_MASTER_CSR_Type; /* ---------------------------------------------------------------------------- -- CAMERA_DSI_MASTER_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_MASTER_CSR_Register_Masks CAMERA_DSI_MASTER_CSR Register Masks * @{ */ /*! @name DSI_CLOCK_GATING_CONTROL - DSI Clock Gating Control */ /*! @{ */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_0_async_fifo_MASK (0x1U) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_0_async_fifo_SHIFT (0U) /*! Display_0_async_fifo - Controls the gating of the processing clock (pixel clock) of Pixel link slave. * 0b1..Pixel clock is disabled (gated) * 0b0..Pixel clock is enabled */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_0_async_fifo(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_0_async_fifo_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_0_async_fifo_MASK) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_1_async_fifo_MASK (0x2U) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_1_async_fifo_SHIFT (1U) /*! Display_1_async_fifo - Controls the gating of the processing clock (pixel clock) of Pixel link slave. * 0b0..Pixel clock is enabled * 0b1..Pixel clock is disabled (gated) */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_1_async_fifo(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_1_async_fifo_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Display_1_async_fifo_MASK) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkin_MASK (0x4U) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkin_SHIFT (2U) /*! Dphy_pll_clkin - Controls the clock gating of the DPHY PLL clkin. * 0b1..clkin is disabled (gated) * 0b0..clkin is enabled */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkin(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkin_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkin_MASK) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkout_MASK (0x8U) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkout_SHIFT (3U) /*! Dphy_pll_clkout - Controls the clock gating of the DPHY PLL clkout. * 0b1..clkout is disabled (gated) * 0b0..clkout is enabled */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkout(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkout_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkout_MASK) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkext_MASK (0x10U) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkext_SHIFT (4U) /*! Dphy_pll_clkext - Controls the clock gating of the DPHY PLL clkext. * 0b0..clkext is enabled * 0b1..clkext is disabled (gated) */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkext(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkext_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_GATING_CONTROL_Dphy_pll_clkext_MASK) /*! @} */ /*! @name DSI_PIXEL_LINK_CONTROL - DSI Pixel Link Control */ /*! @{ */ #define CAMERA_DSI_MASTER_CSR_DSI_PIXEL_LINK_CONTROL_Pixel_link_sel_MASK (0x1U) #define CAMERA_DSI_MASTER_CSR_DSI_PIXEL_LINK_CONTROL_Pixel_link_sel_SHIFT (0U) /*! Pixel_link_sel - Selects the pixel link connected to the DSI host controller. * 0b0..Pixel Link 0 * 0b1..Pixel Link 1 */ #define CAMERA_DSI_MASTER_CSR_DSI_PIXEL_LINK_CONTROL_Pixel_link_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_PIXEL_LINK_CONTROL_Pixel_link_sel_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_PIXEL_LINK_CONTROL_Pixel_link_sel_MASK) /*! @} */ /*! @name DSI_CLOCK_SETTING - DSI Clock Setting */ /*! @{ */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_div_MASK (0xFU) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_div_SHIFT (0U) /*! Dphy_ref_clock_div - Defines the division factor of the Pixel link clock (when used as PLL clock source). */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_div(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_div_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_div_MASK) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_source_MASK (0x80U) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_source_SHIFT (7U) /*! Dphy_ref_clock_source - Select the DPHY PLL clock source * 0b0..24 MHz * 0b1..Pixel link clock divided by 'Dphy_ref_clock_div' */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_source(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_source_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_ref_clock_source_MASK) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_pll_div_MASK (0xF00U) #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_pll_div_SHIFT (8U) /*! Dphy_pll_div - Defines the division factor of the DPHY_PLL clkout when used as display engine clock source. */ #define CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_pll_div(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_pll_div_SHIFT)) & CAMERA_DSI_MASTER_CSR_DSI_CLOCK_SETTING_Dphy_pll_div_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_DSI_MASTER_CSR_Register_Masks */ /* CAMERA_DSI_MASTER_CSR - Peripheral instance base addresses */ /** Peripheral CAMERA__DSI_MASTER_CSR base address */ #define CAMERA__DSI_MASTER_CSR_BASE (0x4AD10000u) /** Peripheral CAMERA__DSI_MASTER_CSR base pointer */ #define CAMERA__DSI_MASTER_CSR ((CAMERA_DSI_MASTER_CSR_Type *)CAMERA__DSI_MASTER_CSR_BASE) /** Array initializer of CAMERA_DSI_MASTER_CSR peripheral base addresses */ #define CAMERA_DSI_MASTER_CSR_BASE_ADDRS { CAMERA__DSI_MASTER_CSR_BASE } /** Array initializer of CAMERA_DSI_MASTER_CSR peripheral base pointers */ #define CAMERA_DSI_MASTER_CSR_BASE_PTRS { CAMERA__DSI_MASTER_CSR } /*! * @} */ /* end of group CAMERA_DSI_MASTER_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_DSI_OR_CSI_PHY_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_OR_CSI_PHY_CSR_Peripheral_Access_Layer CAMERA_DSI_OR_CSI_PHY_CSR Peripheral Access Layer * @{ */ /** CAMERA_DSI_OR_CSI_PHY_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t STANDALONE_PHY_MODE_CONTROL; /**< Rx DPHY mode control, offset: 0x0 */ __IO uint32_t STANDALONE_PHY_FREQ_CONTROL; /**< Rx DPHY frequency control, offset: 0x4 */ __IO uint32_t STANDALONE_PHY_TEST_MODE_CONTROL; /**< Rx DPHY test mode control, offset: 0x8 */ __I uint32_t STANDALONE_PHY_TEST_MODE_STATUS; /**< Rx DPHY test mode status, offset: 0xC */ __IO uint32_t STANDALONE_PHY_TEST_IO_CONT; /**< Rx DPHY test IO continuity, offset: 0x10 */ uint8_t RESERVED_0[236]; __IO uint32_t COMBO_PHY_MODE_CONTROL; /**< Rx/Tx DPHY mode control, offset: 0x100 */ __IO uint32_t COMBO_PHY_FREQ_CONTROL; /**< Rx/Tx DPHY frequency control, offset: 0x104 */ __IO uint32_t COMBO_PHY_TEST_MODE_CONTROL; /**< Rx/Tx DPHY test mode control, offset: 0x108 */ __I uint32_t COMBO_PHY_TEST_MODE_STATUS; /**< Rx/Tx DPHY test mode status, offset: 0x10C */ __IO uint32_t COMBO_PHY_TEST_IO_CONT; /**< Rx/Tx DPHY test IO continuity, offset: 0x110 */ } CAMERA_DSI_OR_CSI_PHY_CSR_Type; /* ---------------------------------------------------------------------------- -- CAMERA_DSI_OR_CSI_PHY_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_OR_CSI_PHY_CSR_Register_Masks CAMERA_DSI_OR_CSI_PHY_CSR Register Masks * @{ */ /*! @name STANDALONE_PHY_MODE_CONTROL - Rx DPHY mode control */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_MODE_CONTROL_PHY_ENABLE_EXT_MASK (0xF0U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_MODE_CONTROL_PHY_ENABLE_EXT_SHIFT (4U) /*! PHY_ENABLE_EXT - PHY lane enable for individual lane control * 0b0000..Disable individual lane control * 0b0001..Enable individual lane control */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_MODE_CONTROL_PHY_ENABLE_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_MODE_CONTROL_PHY_ENABLE_EXT_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_MODE_CONTROL_PHY_ENABLE_EXT_MASK) /*! @} */ /*! @name STANDALONE_PHY_FREQ_CONTROL - Rx DPHY frequency control */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_MASK (0x3FU) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_SHIFT (0U) /*! Phy_cfgclkfreqrange - System clock frequency configuration preset. */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_hsfreqrange_MASK (0x7F0000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_hsfreqrange_SHIFT (16U) /*! Phy_hsfreqrange - High-speed frequency range selection */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_hsfreqrange(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_hsfreqrange_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_FREQ_CONTROL_Phy_hsfreqrange_MASK) /*! @} */ /*! @name STANDALONE_PHY_TEST_MODE_CONTROL - Rx DPHY test mode control */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_basedir_0_MASK (0x1U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_basedir_0_SHIFT (0U) /*! basedir_0 - Base direction for lane 0 * 0b0..Configure lane as TX * 0b1..Configure lane as RX */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_basedir_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_basedir_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_basedir_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_MASK (0x10U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_SHIFT (4U) /*! forcetxstopmode_0 - Force lane module into transmit mode and generate Stop state for lane 0 */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcetxstopmode_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_0_MASK (0x100U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_0_SHIFT (8U) /*! forcerxmode_0 - Force lane module into receive mode/wait for Stop State for lane 0 */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_1_MASK (0x200U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_1_SHIFT (9U) /*! forcerxmode_1 - Force lane module into receive mode/wait for Stop State for lane 1 */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_2_MASK (0x400U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_2_SHIFT (10U) /*! forcerxmode_2 - Force lane module into receive mode/wait for Stop State for lane 2 */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_3_MASK (0x800U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_3_SHIFT (11U) /*! forcerxmode_3 - Force lane module into receive mode/wait for Stop State for lane 3 */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_forcerxmode_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_enableclk_ext_MASK (0x1000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_enableclk_ext_SHIFT (12U) /*! enableclk_ext * 0b0..Clock disabled * 0b1..Clock enabled */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_enableclk_ext(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_enableclk_ext_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_enableclk_ext_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turndisable_0_MASK (0x2000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turndisable_0_SHIFT (13U) /*! turndisable_0 - Disable Turn Around for Lane 0 * 0b1..Disable turn around * 0b0..Allow turn around */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turndisable_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turndisable_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turndisable_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_phy_enable_byp_MASK (0x4000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_phy_enable_byp_SHIFT (14U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_phy_enable_byp(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_phy_enable_byp_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_phy_enable_byp_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turnrequest_0_MASK (0x8000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turnrequest_0_SHIFT (15U) /*! turnrequest_0 - Turn around request. */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turnrequest_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turnrequest_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_CONTROL_turnrequest_0_MASK) /*! @} */ /*! @name STANDALONE_PHY_TEST_MODE_STATUS - Rx DPHY test mode status */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_0_MASK (0x1U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_0_SHIFT (0U) /*! ulpsactivenot_0 - Indicates lane 0 is in the Ultra Low Power (ULP) state * 0b0..Lane is in ULP state * 0b1..Lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_1_MASK (0x2U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_1_SHIFT (1U) /*! ulpsactivenot_1 - Indicates lane 1 is in the Ultra Low Power (ULP) state * 0b0..Lane is in ULP state * 0b1..Lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_2_MASK (0x4U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_2_SHIFT (2U) /*! ulpsactivenot_2 - Indicates lane 2 is in the Ultra Low Power (ULP) state * 0b0..Lane is in ULP state * 0b1..Lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_3_MASK (0x8U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_3_SHIFT (3U) /*! ulpsactivenot_3 - Indicates lane 3 is in the Ultra Low Power (ULP) state * 0b0..Lane is in ULP state * 0b1..Lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenot_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_0_MASK (0x10U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_0_SHIFT (4U) /*! errcontrol_0 - Indicates control error for lane 0 * 0b1..Control error detected * 0b0..No control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_1_MASK (0x20U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_1_SHIFT (5U) /*! errcontrol_1 - Indicates control error for lane 1 * 0b1..Control error detected * 0b0..No control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_2_MASK (0x40U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_2_SHIFT (6U) /*! errcontrol_2 - Indicates control error for lane 2 * 0b1..Control error detected * 0b0..No control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_3_MASK (0x80U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_3_SHIFT (7U) /*! errcontrol_3 - Indicates control error for lane 3 * 0b1..Control error detected * 0b0..No control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_errcontrol_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_direction_0_MASK (0x100U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_direction_0_SHIFT (8U) /*! direction_0 - Indicates the current direction of lane 0 * 0b0..The lane is in transmit mode * 0b1..The lane is in receive mode */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_direction_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_direction_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_direction_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenotclk_MASK (0x200U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenotclk_SHIFT (9U) /*! ulpsactivenotclk - Indicates that the clock lane is in the ULP state * 0b0..Clock lane is in ULP state * 0b1..Clock lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenotclk(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenotclk_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_MODE_STATUS_ulpsactivenotclk_MASK) /*! @} */ /*! @name STANDALONE_PHY_TEST_IO_CONT - Rx DPHY test IO continuity */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_Cont_en_MASK (0x1U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_Cont_en_SHIFT (0U) /*! Phy_Cont_en - IO continuity test mode enable * 0b1..Enable IO continuity test mode * 0b0..Disable IO continuity test mode */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_Cont_en(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_Cont_en_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_Cont_en_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_cont_data_MASK (0x7FF0000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_cont_data_SHIFT (16U) /*! Phy_cont_data - Continuity data signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_cont_data(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_cont_data_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_STANDALONE_PHY_TEST_IO_CONT_Phy_cont_data_MASK) /*! @} */ /*! @name COMBO_PHY_MODE_CONTROL - Rx/Tx DPHY mode control */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_Tx_Rxz_MASK (0x1U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_Tx_Rxz_SHIFT (0U) /*! Tx_Rxz - PHY configuration * 0b0..CSI mode * 0b1..DSI mode */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_Tx_Rxz(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_Tx_Rxz_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_Tx_Rxz_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_clksel_MASK (0x6U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_clksel_SHIFT (1U) /*! PLL_clksel - Control of PLL clock output selection * 0b00..Clocks stopped * 0b01..Clock generation * 0b10..Buffered clkext * 0b11..Reserved */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_clksel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_clksel_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_clksel_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_gp_clk_en_MASK (0x8U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_gp_clk_en_SHIFT (3U) /*! PLL_gp_clk_en - Enable signal for clkout_gp clock. * 0b0..Disable gp_clk_en * 0b1..Enable */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_gp_clk_en(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_gp_clk_en_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PLL_gp_clk_en_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PHY_enable_ext_MASK (0xF0U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PHY_enable_ext_SHIFT (4U) /*! PHY_enable_ext - PHY lane enable for individual lane control. */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PHY_enable_ext(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PHY_enable_ext_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_MODE_CONTROL_PHY_enable_ext_MASK) /*! @} */ /*! @name COMBO_PHY_FREQ_CONTROL - Rx/Tx DPHY frequency control */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_MASK (0xFFU) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_SHIFT (0U) /*! Phy_cfgclkfreqrange - System clock frequency configuration preset */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_cfgclkfreqrange_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_hsfreqrange_MASK (0x7F0000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_hsfreqrange_SHIFT (16U) /*! Phy_hsfreqrange - High-speed frequency range selection */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_hsfreqrange(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_hsfreqrange_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_FREQ_CONTROL_Phy_hsfreqrange_MASK) /*! @} */ /*! @name COMBO_PHY_TEST_MODE_CONTROL - Rx/Tx DPHY test mode control */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_0_MASK (0x1U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_0_SHIFT (0U) /*! basedir_0 - Base direction for lane 0 * 0b0..Configure lane as TX * 0b1..Configure lane as RX */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_1_MASK (0x2U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_1_SHIFT (1U) /*! basedir_1 - Base direction for lane 1 * 0b0..Configure lane as TX * 0b1..Configure lane as RX */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_2_MASK (0x4U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_2_SHIFT (2U) /*! basedir_2 - Base direction for lane 2 * 0b0..Configure lane as TX * 0b1..Configure lane as RX */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_3_MASK (0x8U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_3_SHIFT (3U) /*! basedir_3 - Base direction for lane 3 * 0b0..Configure lane as TX * 0b1..Configure lane as RX */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_basedir_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_MASK (0x10U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_SHIFT (4U) /*! forcetxstopmode_0 - Force lane module into transmit mode and generate Stop state for lane 0 * 0b0..Do not force lane module into transmit mode and Stop state following an error indication * 0b1..Force lane module into transmit mode and Stop state following an error indication */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_1_MASK (0x20U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_1_SHIFT (5U) /*! forcetxstopmode_1 - Force lane module into transmit mode and generate Stop state for lane 1 * 0b1..Force lane module into transmit mode and Stop state following an error indication * 0b0..Do not force lane module into transmit mode and Stop state following an error indication */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_2_MASK (0x40U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_2_SHIFT (6U) /*! forcetxstopmode_2 - Force lane module into transmit mode and generate Stop state for lane 2 * 0b1..Force lane module into transmit mode and Stop state following an error indication * 0b0..Do not force lane module into transmit mode and Stop state following an error indication */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_3_MASK (0x80U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_3_SHIFT (7U) /*! forcetxstopmode_3 - Force lane module into transmit mode and generate Stop state for lane 3 * 0b1..Force lane module into transmit mode and Stop state following an error indication * 0b0..Do not force lane module into transmit mode and Stop state following an error indication */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcetxstopmode_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_0_MASK (0x100U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_0_SHIFT (8U) /*! forcerxmode_0 - Force lane module into receive mode/wait for Stop State for lane 0 * 0b1..Force lane module into receive mode and wait for Stop state * 0b0..Do not force lane module into receive mode and wait for Stop state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_1_MASK (0x200U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_1_SHIFT (9U) /*! forcerxmode_1 - Force lane module into receive mode/wait for Stop State for lane 1 * 0b0..Do not force lane module into receive mode and wait for Stop state * 0b1..Force lane module into receive mode and wait for Stop state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_2_MASK (0x400U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_2_SHIFT (10U) /*! forcerxmode_2 - Force lane module into receive mode/wait for Stop State for lane 2 * 0b0..Do not force lane module into receive mode and wait for Stop state * 0b1..Force lane module into receive mode and wait for Stop state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_3_MASK (0x800U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_3_SHIFT (11U) /*! forcerxmode_3 - Force lane module into receive mode/wait for Stop State for lane 3 * 0b0..Do not force lane module into receive mode and wait for Stop state * 0b1..Force lane module into receive mode and wait for Stop state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_forcerxmode_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_enableclk_ext_MASK (0x1000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_enableclk_ext_SHIFT (12U) /*! enableclk_ext - Enable clock lane * 0b0..Disable clock lane * 0b1..Enable clock lane */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_enableclk_ext(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_enableclk_ext_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_enableclk_ext_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turndisable_0_MASK (0x2000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turndisable_0_SHIFT (13U) /*! turndisable_0 - Disable turn around for lane 0, Could be used only when the DSI/CSI complex is in DSI mode. * 0b0..Allow turn around * 0b1..Disable turn around */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turndisable_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turndisable_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turndisable_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_phy_enable_byp_MASK (0x4000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_phy_enable_byp_SHIFT (14U) /*! phy_enable_byp - Mux select between CSI/DSI controllers generated PHY enable signals and external phy_enable_ext * 0b0..Controller generated signals * 0b1..External signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_phy_enable_byp(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_phy_enable_byp_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_phy_enable_byp_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turnrequest_0_sel_MASK (0x8000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turnrequest_0_sel_SHIFT (15U) /*! turnrequest_0_sel - Mux select between controller generated and external turn around request signal * 0b0..Controller generated signals * 0b1..External signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turnrequest_0_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turnrequest_0_sel_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_turnrequest_0_sel_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txdatahs_sel_MASK (0x10000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txdatahs_sel_SHIFT (16U) /*! txdatahs_sel - Mux select between controller generated and external high-speed data lanes * 0b0..Controller generated signals * 0b1..External signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txdatahs_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txdatahs_sel_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txdatahs_sel_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txbyteclkhs_sel_MASK (0x20000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txbyteclkhs_sel_SHIFT (17U) /*! txbyteclkhs_sel - Mux select between controller generated and external high-speed transmit clock * 0b0..Controller generated signals * 0b1..External signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txbyteclkhs_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txbyteclkhs_sel_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txbyteclkhs_sel_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txulpsclk_sel_MASK (0x40000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txulpsclk_sel_SHIFT (18U) /*! txulpsclk_sel - Mux select between controller generated and external transmit ULP signals * 0b0..Controller generated signals * 0b1..External signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txulpsclk_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txulpsclk_sel_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txulpsclk_sel_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txlp_data_esc_sel_MASK (0x80000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txlp_data_esc_sel_SHIFT (19U) /*! txlp_data_esc_sel - Mux select between controller generated and external escape mode transmit data signals * 0b0..Controller generated signals * 0b1..External signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txlp_data_esc_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txlp_data_esc_sel_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txlp_data_esc_sel_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txclkesc_sel_MASK (0x100000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txclkesc_sel_SHIFT (20U) /*! txclkesc_sel - Mux select between controller generated and external escape mode transmit clock * 0b0..Controller generated signals * 0b1..External signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txclkesc_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txclkesc_sel_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_txclkesc_sel_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_biston_MASK (0x200000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_biston_SHIFT (21U) /*! biston - Starts the HS bist test. * 0b0..BIST off * 0b1..Start BIST */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_biston(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_biston_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_CONTROL_biston_MASK) /*! @} */ /*! @name COMBO_PHY_TEST_MODE_STATUS - Rx/Tx DPHY test mode status */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_0_MASK (0x1U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_0_SHIFT (0U) /*! ulpsactivenot_0 - Indicates lane 0 is in the Ultra Low Power (ULP) state * 0b0..Lane is in ULP state * 0b1..Lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_1_MASK (0x2U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_1_SHIFT (1U) /*! ulpsactivenot_1 - Indicates lane 1 is in the Ultra Low Power (ULP) state * 0b1..Lane is not in ULP state * 0b0..Lane is in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_2_MASK (0x4U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_2_SHIFT (2U) /*! ulpsactivenot_2 - Indicates lane 2 is in the Ultra Low Power (ULP) state * 0b0..Lane is in ULP state * 0b1..Lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_3_MASK (0x8U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_3_SHIFT (3U) /*! ulpsactivenot_3 - Indicates lane 3 is in the Ultra Low Power (ULP) state * 0b1..Lane is not in ULP state * 0b0..Lane is in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenot_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_0_MASK (0x10U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_0_SHIFT (4U) /*! errcontrol_0 - Indicates control error for lane 0 * 0b1..Control error detected * 0b0..No control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_0_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_0_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_1_MASK (0x20U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_1_SHIFT (5U) /*! errcontrol_1 - Indicates control error for lane 1 * 0b1..Control error detected * 0b0..No control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_1_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_1_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_2_MASK (0x40U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_2_SHIFT (6U) /*! errcontrol_2 - Indicates control error for lane 2 * 0b1..Control error detected * 0b0..No control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_2_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_2_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_3_MASK (0x80U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_3_SHIFT (7U) /*! errcontrol_3 - Indicates control error for lane 3 * 0b0..No control error detected * 0b1..Control error detected */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_3_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_errcontrol_3_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_rxulpsclknot_MASK (0x100U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_rxulpsclknot_SHIFT (8U) /*! rxulpsclknot - Indicates that the clock lane module has entered the ULP state * 0b1..Clock lane is not in ULP state * 0b0..Clock lane is in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_rxulpsclknot(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_rxulpsclknot_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_rxulpsclknot_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenotclk_MASK (0x200U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenotclk_SHIFT (9U) /*! ulpsactivenotclk - Indicates that the clock lane is in the ULP state * 0b0..Clock lane is in ULP state * 0b1..Clock lane is not in ULP state */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenotclk(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenotclk_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_ulpsactivenotclk_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_phy_lock_MASK (0x800U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_phy_lock_SHIFT (11U) /*! phy_lock - PLL lock indication * 0b0..PLL is not locked * 0b1..PLL is locked */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_phy_lock(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_phy_lock_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_phy_lock_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistDone_MASK (0x1000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistDone_SHIFT (12U) /*! BistDone - HS bist test done. * 0b0..HS bist test not done. * 0b1..HS bist test done. */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistDone(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistDone_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistDone_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistOK_MASK (0x2000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistOK_SHIFT (13U) /*! BistOK - Status of BIST test * 0b1..BIST test is OK * 0b0..BIST test completed with errors */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistOK(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistOK_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_MODE_STATUS_BistOK_MASK) /*! @} */ /*! @name COMBO_PHY_TEST_IO_CONT - Rx/Tx DPHY test IO continuity */ /*! @{ */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_Cont_en_MASK (0x1U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_Cont_en_SHIFT (0U) /*! Phy_Cont_en - IO continuity test mode enable * 0b1..Enable IO continuity test mode * 0b0..Disable IO continuity test mode */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_Cont_en(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_Cont_en_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_Cont_en_MASK) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_cont_data_MASK (0x7FF0000U) #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_cont_data_SHIFT (16U) /*! Phy_cont_data - Continuity data signals */ #define CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_cont_data(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_cont_data_SHIFT)) & CAMERA_DSI_OR_CSI_PHY_CSR_COMBO_PHY_TEST_IO_CONT_Phy_cont_data_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_DSI_OR_CSI_PHY_CSR_Register_Masks */ /* CAMERA_DSI_OR_CSI_PHY_CSR - Peripheral instance base addresses */ /** Peripheral CAMERA__DSI_OR_CSI_PHY_CSR base address */ #define CAMERA__DSI_OR_CSI_PHY_CSR_BASE (0x4AD20000u) /** Peripheral CAMERA__DSI_OR_CSI_PHY_CSR base pointer */ #define CAMERA__DSI_OR_CSI_PHY_CSR ((CAMERA_DSI_OR_CSI_PHY_CSR_Type *)CAMERA__DSI_OR_CSI_PHY_CSR_BASE) /** Array initializer of CAMERA_DSI_OR_CSI_PHY_CSR peripheral base addresses */ #define CAMERA_DSI_OR_CSI_PHY_CSR_BASE_ADDRS { CAMERA__DSI_OR_CSI_PHY_CSR_BASE } /** Array initializer of CAMERA_DSI_OR_CSI_PHY_CSR peripheral base pointers */ #define CAMERA_DSI_OR_CSI_PHY_CSR_BASE_PTRS { CAMERA__DSI_OR_CSI_PHY_CSR } /*! * @} */ /* end of group CAMERA_DSI_OR_CSI_PHY_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_DSI_PIXEL_FORMATTING Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_PIXEL_FORMATTING_Peripheral_Access_Layer CAMERA_DSI_PIXEL_FORMATTING Peripheral Access Layer * @{ */ /** CAMERA_DSI_PIXEL_FORMATTING - Register Layout Typedef */ typedef struct { __IO uint32_t DSI_HOST_CONFIGURATION; /**< DSI Host Configuration, offset: 0x0 */ __IO uint32_t DSI_PARITY_ERROR_STATUS; /**< DSI Parity Error Status, offset: 0x4 */ __IO uint32_t DSI_PARITY_ERR_THRESH; /**< DSI Parity Error Threshold, offset: 0x8 */ } CAMERA_DSI_PIXEL_FORMATTING_Type; /* ---------------------------------------------------------------------------- -- CAMERA_DSI_PIXEL_FORMATTING Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_PIXEL_FORMATTING_Register_Masks CAMERA_DSI_PIXEL_FORMATTING Register Masks * @{ */ /*! @name DSI_HOST_CONFIGURATION - DSI Host Configuration */ /*! @{ */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_HOST_CONFIGURATION_PIXEL_LINK_FORMAT_MASK (0x7U) #define CAMERA_DSI_PIXEL_FORMATTING_DSI_HOST_CONFIGURATION_PIXEL_LINK_FORMAT_SHIFT (0U) /*! PIXEL_LINK_FORMAT - Defines the pixel format transported on the pixel link * 0b000..RGB 24-bit * 0b001..RGB 20-bit * 0b010..RGB 18-bit * 0b011..RGB 16-bit * 0b100..20-bit YCbCr, 4:2:2 format * 0b101..16-bit YCbCr, 4:2:2 format */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_HOST_CONFIGURATION_PIXEL_LINK_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_PIXEL_FORMATTING_DSI_HOST_CONFIGURATION_PIXEL_LINK_FORMAT_SHIFT)) & CAMERA_DSI_PIXEL_FORMATTING_DSI_HOST_CONFIGURATION_PIXEL_LINK_FORMAT_MASK) /*! @} */ /*! @name DSI_PARITY_ERROR_STATUS - DSI Parity Error Status */ /*! @{ */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY0_ERROR_MASK (0x1U) #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY0_ERROR_SHIFT (0U) /*! PARITY0_ERROR - Detected parity[0] error has reached the PARITY0_ERROR_MAX * 0b0..Number of detected error on parity[0] is below PARITY0_ERR_MAX * 0b1..Number of detected error on parity[0] is above or equal to PARITY0_ERR_MAX */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY0_ERROR_SHIFT)) & CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY0_ERROR_MASK) #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY123_ERROR_MASK (0x2U) #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY123_ERROR_SHIFT (1U) /*! PARITY123_ERROR - Detected parity[3:1] error has reached the PARITY123_ERROR_MAX * 0b0..Number of detected error on parity[3:1] is below PARITY123_ERROR_MAX * 0b1..Number of detected error on parity[3:1] is above or equal to PARITY123_ERROR_MAX */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY123_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY123_ERROR_SHIFT)) & CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERROR_STATUS_PARITY123_ERROR_MASK) /*! @} */ /*! @name DSI_PARITY_ERR_THRESH - DSI Parity Error Threshold */ /*! @{ */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY0_ERR_MAX_MASK (0x3FFU) #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY0_ERR_MAX_SHIFT (0U) /*! PARITY0_ERR_MAX - Parity0_error max threshold * 0b0000000000-0b0000111111..Max parity error threshold */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY0_ERR_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY0_ERR_MAX_SHIFT)) & CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY0_ERR_MAX_MASK) #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY123_ERR_MAX_MASK (0x3FF0000U) #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY123_ERR_MAX_SHIFT (16U) /*! PARITY123_ERR_MAX - Parity123_error max threshold * 0b0000000000-0b0000111111..Max parity error threshold */ #define CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY123_ERR_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY123_ERR_MAX_SHIFT)) & CAMERA_DSI_PIXEL_FORMATTING_DSI_PARITY_ERR_THRESH_PARITY123_ERR_MAX_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_DSI_PIXEL_FORMATTING_Register_Masks */ /* CAMERA_DSI_PIXEL_FORMATTING - Peripheral instance base addresses */ /** Peripheral CAMERA__DSI_PIXEL_FORMATTING base address */ #define CAMERA__DSI_PIXEL_FORMATTING_BASE (0x4AC00000u) /** Peripheral CAMERA__DSI_PIXEL_FORMATTING base pointer */ #define CAMERA__DSI_PIXEL_FORMATTING ((CAMERA_DSI_PIXEL_FORMATTING_Type *)CAMERA__DSI_PIXEL_FORMATTING_BASE) /** Array initializer of CAMERA_DSI_PIXEL_FORMATTING peripheral base addresses */ #define CAMERA_DSI_PIXEL_FORMATTING_BASE_ADDRS { CAMERA__DSI_PIXEL_FORMATTING_BASE } /** Array initializer of CAMERA_DSI_PIXEL_FORMATTING peripheral base pointers */ #define CAMERA_DSI_PIXEL_FORMATTING_BASE_PTRS { CAMERA__DSI_PIXEL_FORMATTING } /*! * @} */ /* end of group CAMERA_DSI_PIXEL_FORMATTING_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_DSI_STREAM_CSR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_STREAM_CSR_Peripheral_Access_Layer CAMERA_DSI_STREAM_CSR Peripheral Access Layer * @{ */ /** CAMERA_DSI_STREAM_CSR - Register Layout Typedef */ typedef struct { __IO uint32_t DSI_HOST_CONFIGURATION; /**< DSI Host Configuration, offset: 0x0 */ __IO uint32_t DSI_PARITY_ERROR_STATUS; /**< DSI Parity Error Status, offset: 0x4 */ __IO uint32_t DSI_PARITY_ERROR_THRESHOLD; /**< DSI Parity Error Threshold, offset: 0x8 */ } CAMERA_DSI_STREAM_CSR_Type; /* ---------------------------------------------------------------------------- -- CAMERA_DSI_STREAM_CSR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_DSI_STREAM_CSR_Register_Masks CAMERA_DSI_STREAM_CSR Register Masks * @{ */ /*! @name DSI_HOST_CONFIGURATION - DSI Host Configuration */ /*! @{ */ #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_Pixel_link_format_MASK (0x7U) #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_Pixel_link_format_SHIFT (0U) /*! Pixel_link_format - Configures the pixel link format transported on the pixel link * 0b000..RGB 24-bit * 0b001..RGB 30-bit * 0b010..RGB 18-bit * 0b011..RGB 16-bit * 0b100..20-bit YCbCr, 4:2:2 format * 0b101..16-bit YCbCr, 4:2:2 format */ #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_Pixel_link_format(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_Pixel_link_format_SHIFT)) & CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_Pixel_link_format_MASK) #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_shutdown_MASK (0x10U) #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_shutdown_SHIFT (4U) /*! shutdown - That bit is directly connected to the dpishutdn input of the CSI2 host controller. * It's used to shutdown the distant DSI peripheral. * 0b0..'1' to '0': send a turn on peripheral command (short packet - 0x32) * 0b1..'0' to '1': send a shut down peripheral command (short packet - 0x22) */ #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_shutdown(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_shutdown_SHIFT)) & CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_shutdown_MASK) #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_colormode_MASK (0x20U) #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_colormode_SHIFT (5U) /*! colormode - That bit is directly connected to the dpicolorm input of the CSI2 host controller. * It's used to switch between normal color and reduced color mode. * 0b0..'1' to '0': Send a Color Mode Off Command (Short packet - 0x02) switches a Video Mode display module from * low-color mode to normal display operation. * 0b1..'0' to '1': Send a Color Mode On Command (Short packet - 0x12)switches a Video Mode display module to a low-color mode for power saving. */ #define CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_colormode(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_colormode_SHIFT)) & CAMERA_DSI_STREAM_CSR_DSI_HOST_CONFIGURATION_colormode_MASK) /*! @} */ /*! @name DSI_PARITY_ERROR_STATUS - DSI Parity Error Status */ /*! @{ */ #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity0_error_MASK (0x1U) #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity0_error_SHIFT (0U) /*! Parity0_error - Parity 0 error status * 0b1..The number of detected errors on parity 0 is equal to or above the DSI_PARITY_ERROR_THRESHOLD[parity0_error_max] * 0b0..The number of detected errors on parity 0 is below the DSI_PARITY_ERROR_THRESHOLD[parity0_error_max] */ #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity0_error(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity0_error_SHIFT)) & CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity0_error_MASK) #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity123_error_MASK (0x2U) #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity123_error_SHIFT (1U) /*! Parity123_error - Parity 123 error status * 0b0..The number of detected errors on parity 123 is below the DSI_PARITY_ERROR_THRESHOLD[parity123_error_max] * 0b1..The number of detected errors on parity 123 has reached the DSI_PARITY_ERROR_THRESHOLD[parity123_error_max] */ #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity123_error(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity123_error_SHIFT)) & CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_STATUS_Parity123_error_MASK) /*! @} */ /*! @name DSI_PARITY_ERROR_THRESHOLD - DSI Parity Error Threshold */ /*! @{ */ #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity0_error_max_MASK (0x3FFU) #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity0_error_max_SHIFT (0U) /*! parity0_error_max - Max parity 0 threshold * 0b0000000000..The error check for parity 0 is disabled. * 0b0000000001-0b1111111111..Maximum number of parity 0 errors. */ #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity0_error_max(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity0_error_max_SHIFT)) & CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity0_error_max_MASK) #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity123_error_max_MASK (0x3FF0000U) #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity123_error_max_SHIFT (16U) /*! parity123_error_max - Max parity 123 threshold * 0b0000000001-0b1111111111..Maximum number of parity 123 errors. * 0b0000000000..The error check for parity 123 is disabled. */ #define CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity123_error_max(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity123_error_max_SHIFT)) & CAMERA_DSI_STREAM_CSR_DSI_PARITY_ERROR_THRESHOLD_parity123_error_max_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_DSI_STREAM_CSR_Register_Masks */ /* CAMERA_DSI_STREAM_CSR - Peripheral instance base addresses */ /** Peripheral CAMERA__DSI_STREAM_CSR base address */ #define CAMERA__DSI_STREAM_CSR_BASE (0x4AD00000u) /** Peripheral CAMERA__DSI_STREAM_CSR base pointer */ #define CAMERA__DSI_STREAM_CSR ((CAMERA_DSI_STREAM_CSR_Type *)CAMERA__DSI_STREAM_CSR_BASE) /** Array initializer of CAMERA_DSI_STREAM_CSR peripheral base addresses */ #define CAMERA_DSI_STREAM_CSR_BASE_ADDRS { CAMERA__DSI_STREAM_CSR_BASE } /** Array initializer of CAMERA_DSI_STREAM_CSR peripheral base pointers */ #define CAMERA_DSI_STREAM_CSR_BASE_PTRS { CAMERA__DSI_STREAM_CSR } /*! * @} */ /* end of group CAMERA_DSI_STREAM_CSR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_MIPI_CSI2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_MIPI_CSI2_Peripheral_Access_Layer CAMERA_MIPI_CSI2 Peripheral Access Layer * @{ */ /** CAMERA_MIPI_CSI2 - Register Layout Typedef */ typedef struct { __I uint32_t VERSION; /**< Core version., offset: 0x0 */ __IO uint32_t N_LANES; /**< Number of lanes., offset: 0x4 */ __IO uint32_t CSI2_RESETN; /**< Logic Reset., offset: 0x8 */ __I uint32_t INT_ST_MAIN; /**< Main interrupt status., offset: 0xC */ __IO uint32_t DATA_IDS_1; /**< Data Type fields for Data ID Monitors 1., offset: 0x10 */ __IO uint32_t DATA_IDS_2; /**< Data Type fields for Data ID Monitors 2., offset: 0x14 */ uint8_t RESERVED_0[24]; __IO uint32_t DATA_IDS_VC_1; /**< Virtual Channel fields for Data ID Monitors 1., offset: 0x30 */ __IO uint32_t DATA_IDS_VC_2; /**< Virtual Channel fields for Data ID Monitors 2., offset: 0x34 */ uint8_t RESERVED_1[8]; __IO uint32_t PHY_SHUTDOWNZ; /**< PHY Shutdown., offset: 0x40 */ __IO uint32_t DPHY_RSTZ; /**< DPHY reset., offset: 0x44 */ __I uint32_t PHY_RX; /**< RX PHY status., offset: 0x48 */ __I uint32_t PHY_STOPSTATE; /**< STOPSTATE PHY status., offset: 0x4C */ __IO uint32_t PHY_TEST_CTRL0; /**< D-PHY Test and Control interface 0., offset: 0x50 */ __IO uint32_t PHY_TEST_CTRL1; /**< D-PHY Test and Control interface 1., offset: 0x54 */ uint8_t RESERVED_2[112]; __IO uint32_t VC_EXTENSION; /**< Virtual Channel Extension., offset: 0xC8 */ __I uint32_t PHY_CAL; /**< PHY Calibration., offset: 0xCC */ uint8_t RESERVED_3[16]; __I uint32_t INT_ST_PHY_FATAL; /**< Fatal interruption caused by PHY., offset: 0xE0 */ __IO uint32_t INT_MSK_PHY_FATAL; /**< Mask for fatal interruption caused by PHY., offset: 0xE4 */ __IO uint32_t INT_FORCE_PHY_FATAL; /**< Force for fatal interruption caused by PHY., offset: 0xE8 */ uint8_t RESERVED_4[4]; __I uint32_t INT_ST_PKT_FATAL; /**< Fatal interruption caused during Packet Construction., offset: 0xF0 */ __IO uint32_t INT_MSK_PKT_FATAL; /**< Mask for fatal interruption caused during Packet Construction., offset: 0xF4 */ __IO uint32_t INT_FORCE_PKT_FATAL; /**< Force for fatal interruption caused during Packet Construction., offset: 0xF8 */ uint8_t RESERVED_5[20]; __I uint32_t INT_ST_PHY; /**< Interruption caused by PHY., offset: 0x110 */ __IO uint32_t INT_MSK_PHY; /**< Mask for interruption caused by PHY., offset: 0x114 */ __IO uint32_t INT_FORCE_PHY; /**< Force for interruption caused by PHY., offset: 0x118 */ uint8_t RESERVED_6[20]; __I uint32_t INT_ST_LINE; /**< Interruption occurred during Line construction., offset: 0x130 */ __IO uint32_t INT_MSK_LINE; /**< Mask for interruption occurred during Line construction., offset: 0x134 */ __IO uint32_t INT_FORCE_LINE; /**< Force for interruption occurred during Line construction., offset: 0x138 */ uint8_t RESERVED_7[324]; __I uint32_t INT_ST_BNDRY_FRAME_FATAL; /**< Fatal Interruption caused by Frame Boundaries., offset: 0x280 */ __IO uint32_t INT_MSK_BNDRY_FRAME_FATAL; /**< Mask for fatal interruption caused by Frame Boundaries., offset: 0x284 */ __IO uint32_t INT_FORCE_BNDRY_FRAME_FATAL; /**< Force for fatal interruption caused by Frame Boundaries., offset: 0x288 */ uint8_t RESERVED_8[4]; __I uint32_t INT_ST_SEQ_FRAME_FATAL; /**< Fatal Interruption caused by Frame Sequence., offset: 0x290 */ __IO uint32_t INT_MSK_SEQ_FRAME_FATAL; /**< Mask for fatal interruption caused by Frame Sequence., offset: 0x294 */ __IO uint32_t INT_FORCE_SEQ_FRAME_FATAL; /**< Force for fatal interruption caused by Frame Sequence., offset: 0x298 */ uint8_t RESERVED_9[4]; __I uint32_t INT_ST_CRC_FRAME_FATAL; /**< Fatal Interruption caused by Frame CRC., offset: 0x2A0 */ __IO uint32_t INT_MSK_CRC_FRAME_FATAL; /**< Mask for fatal interruption caused by Frame CRC., offset: 0x2A4 */ __IO uint32_t INT_FORCE_CRC_FRAME_FATAL; /**< Force for fatal interruption caused by Frame CRC., offset: 0x2A8 */ uint8_t RESERVED_10[4]; __I uint32_t INT_ST_PLD_CRC_FATAL; /**< Fatal Interruption caused by Payload CRC., offset: 0x2B0 */ __IO uint32_t INT_MSK_PLD_CRC_FATAL; /**< Mask for fatal interruption caused by Payload CRC., offset: 0x2B4 */ __IO uint32_t INT_FORCE_PLD_CRC_FATAL; /**< Force for fatal interruption caused by Payload CRC., offset: 0x2B8 */ uint8_t RESERVED_11[4]; __I uint32_t INT_ST_DATA_ID; /**< Interruption caused by Data Type., offset: 0x2C0 */ __IO uint32_t INT_MSK_DATA_ID; /**< Mask for interruption caused by Data Type., offset: 0x2C4 */ __IO uint32_t INT_FORCE_DATA_ID; /**< Force for interruption caused by Data Type., offset: 0x2C8 */ uint8_t RESERVED_12[4]; __I uint32_t INT_ST_ECC_CORRECTED; /**< Interruption caused by Header single bit errors., offset: 0x2D0 */ __IO uint32_t INT_MSK_ECC_CORRECTED; /**< Mask for interruption caused by Header single bit errors., offset: 0x2D4 */ __IO uint32_t INT_FORCE_ECC_CORRECTED; /**< Force for interruption caused by Header single bit errors., offset: 0x2D8 */ uint8_t RESERVED_13[36]; __IO uint32_t SCRAMBLING; /**< Data De-Scrambling., offset: 0x300 */ __IO uint32_t SCRAMBLING_SEED1; /**< De-scrambler seed for lane1., offset: 0x304 */ __IO uint32_t SCRAMBLING_SEED2; /**< De-scrambler seed for lane2., offset: 0x308 */ __IO uint32_t SCRAMBLING_SEED3; /**< De-scrambler seed for lane3., offset: 0x30C */ __IO uint32_t SCRAMBLING_SEED4; /**< De-scrambler seed for lane4., offset: 0x310 */ } CAMERA_MIPI_CSI2_Type; /* ---------------------------------------------------------------------------- -- CAMERA_MIPI_CSI2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_MIPI_CSI2_Register_Masks CAMERA_MIPI_CSI2 Register Masks * @{ */ /*! @name VERSION - Core version. */ /*! @{ */ #define CAMERA_MIPI_CSI2_VERSION_version_MASK (0xFFFFFFFFU) #define CAMERA_MIPI_CSI2_VERSION_version_SHIFT (0U) /*! version - This field indicates the version of the MIPI CSI-2 host controller. */ #define CAMERA_MIPI_CSI2_VERSION_version(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_VERSION_version_SHIFT)) & CAMERA_MIPI_CSI2_VERSION_version_MASK) /*! @} */ /*! @name N_LANES - Number of lanes. */ /*! @{ */ #define CAMERA_MIPI_CSI2_N_LANES_n_lanes_MASK (0x7U) #define CAMERA_MIPI_CSI2_N_LANES_n_lanes_SHIFT (0U) /*! n_lanes - Number of active data lanes. * 0b000..1 Data Lane * 0b001..2 Data Lanes * 0b010..3 Data Lanes * 0b011..4 Data Lanes */ #define CAMERA_MIPI_CSI2_N_LANES_n_lanes(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_N_LANES_n_lanes_SHIFT)) & CAMERA_MIPI_CSI2_N_LANES_n_lanes_MASK) /*! @} */ /*! @name CSI2_RESETN - Logic Reset. */ /*! @{ */ #define CAMERA_MIPI_CSI2_CSI2_RESETN_csi2_resetn_MASK (0x1U) #define CAMERA_MIPI_CSI2_CSI2_RESETN_csi2_resetn_SHIFT (0U) /*! csi2_resetn - MIPI CSI-2 host controller reset. * 0b0..Put the CSI-2 internal logic in the reset state. * 0b1..Release the CSI-2 internal logic from the reset state. */ #define CAMERA_MIPI_CSI2_CSI2_RESETN_csi2_resetn(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_CSI2_RESETN_csi2_resetn_SHIFT)) & CAMERA_MIPI_CSI2_CSI2_RESETN_csi2_resetn_MASK) /*! @} */ /*! @name INT_ST_MAIN - Main interrupt status. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_fatal_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_fatal_SHIFT (0U) /*! status_int_st_phy_fatal - Status of int_st_phy_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PHY_FATAL is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_fatal(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_fatal_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_fatal_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pkt_fatal_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pkt_fatal_SHIFT (1U) /*! status_int_st_pkt_fatal - Status of int_st_pkt_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PKT_FATAL is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pkt_fatal(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pkt_fatal_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pkt_fatal_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_bndry_frame_fatal_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_bndry_frame_fatal_SHIFT (2U) /*! status_int_st_bndry_frame_fatal - Status of int_st_bndry_frame_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_BNDRY_FRAME_FATAL is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_bndry_frame_fatal(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_bndry_frame_fatal_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_bndry_frame_fatal_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_seq_frame_fatal_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_seq_frame_fatal_SHIFT (3U) /*! status_int_st_seq_frame_fatal - Status of int_st_seq_frame_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_SEQ_FRAME_FATAL is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_seq_frame_fatal(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_seq_frame_fatal_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_seq_frame_fatal_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_crc_frame_fatal_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_crc_frame_fatal_SHIFT (4U) /*! status_int_st_crc_frame_fatal - Status of int_st_crc_frame_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_CRC_FRAME_FATAL is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_crc_frame_fatal(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_crc_frame_fatal_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_crc_frame_fatal_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pld_crc_fatal_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pld_crc_fatal_SHIFT (5U) /*! status_int_st_pld_crc_fatal - Status of int_st_pld_crc_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PLD_CRC_FATAL is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pld_crc_fatal(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pld_crc_fatal_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_pld_crc_fatal_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_data_id_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_data_id_SHIFT (6U) /*! status_int_st_data_id - Status of int_st_data_id. * 0b0..No error. * 0b1..An interrupt source in INT_ST_DATA_ID is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_data_id(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_data_id_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_data_id_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_ecc_corrected_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_ecc_corrected_SHIFT (7U) /*! status_int_st_ecc_corrected - Status of int_st_ecc_corrected. * 0b0..No error. * 0b1..An interrupt source in INT_ST_ECC_CORRECTED is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_ecc_corrected(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_ecc_corrected_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_ecc_corrected_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_MASK (0x10000U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_SHIFT (16U) /*! status_int_st_phy - Status of int_st_phy. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PHY is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_phy_MASK) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_line_MASK (0x20000U) #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_line_SHIFT (17U) /*! status_int_st_line - Status of int_st_line * 0b0..No error. * 0b1..An interrupt source in INT_ST_LINE is set. */ #define CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_line(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_line_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_MAIN_status_int_st_line_MASK) /*! @} */ /*! @name DATA_IDS_1 - Data Type fields for Data ID Monitors 1. */ /*! @{ */ #define CAMERA_MIPI_CSI2_DATA_IDS_1_di0_dt_MASK (0x3FU) #define CAMERA_MIPI_CSI2_DATA_IDS_1_di0_dt_SHIFT (0U) /*! di0_dt - Data type for programmed data ID 0. */ #define CAMERA_MIPI_CSI2_DATA_IDS_1_di0_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_1_di0_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_1_di0_dt_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_1_di1_dt_MASK (0x3F00U) #define CAMERA_MIPI_CSI2_DATA_IDS_1_di1_dt_SHIFT (8U) /*! di1_dt - Data type for programmed data ID 1. */ #define CAMERA_MIPI_CSI2_DATA_IDS_1_di1_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_1_di1_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_1_di1_dt_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_1_di2_dt_MASK (0x3F0000U) #define CAMERA_MIPI_CSI2_DATA_IDS_1_di2_dt_SHIFT (16U) /*! di2_dt - Data type for programmed Data ID 2. */ #define CAMERA_MIPI_CSI2_DATA_IDS_1_di2_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_1_di2_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_1_di2_dt_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_1_di3_dt_MASK (0x3F000000U) #define CAMERA_MIPI_CSI2_DATA_IDS_1_di3_dt_SHIFT (24U) /*! di3_dt - Data type for programmed data ID 3. */ #define CAMERA_MIPI_CSI2_DATA_IDS_1_di3_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_1_di3_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_1_di3_dt_MASK) /*! @} */ /*! @name DATA_IDS_2 - Data Type fields for Data ID Monitors 2. */ /*! @{ */ #define CAMERA_MIPI_CSI2_DATA_IDS_2_di4_dt_MASK (0x3FU) #define CAMERA_MIPI_CSI2_DATA_IDS_2_di4_dt_SHIFT (0U) /*! di4_dt - Data type for programmed data ID 4. */ #define CAMERA_MIPI_CSI2_DATA_IDS_2_di4_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_2_di4_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_2_di4_dt_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_2_di5_dt_MASK (0x3F00U) #define CAMERA_MIPI_CSI2_DATA_IDS_2_di5_dt_SHIFT (8U) /*! di5_dt - Data type for programmed data ID 5. */ #define CAMERA_MIPI_CSI2_DATA_IDS_2_di5_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_2_di5_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_2_di5_dt_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_2_di6_dt_MASK (0x3F0000U) #define CAMERA_MIPI_CSI2_DATA_IDS_2_di6_dt_SHIFT (16U) /*! di6_dt - Data type for programmed data ID 6. */ #define CAMERA_MIPI_CSI2_DATA_IDS_2_di6_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_2_di6_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_2_di6_dt_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_2_di7_dt_MASK (0x3F000000U) #define CAMERA_MIPI_CSI2_DATA_IDS_2_di7_dt_SHIFT (24U) /*! di7_dt - Data type for programmed data ID 7. */ #define CAMERA_MIPI_CSI2_DATA_IDS_2_di7_dt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_2_di7_dt_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_2_di7_dt_MASK) /*! @} */ /*! @name DATA_IDS_VC_1 - Virtual Channel fields for Data ID Monitors 1. */ /*! @{ */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vc_MASK (0x3U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vc_SHIFT (0U) /*! di0_vc - Virtual channel for programmed data ID 0. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vcx_0_1_MASK (0xCU) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vcx_0_1_SHIFT (2U) /*! di0_vcx_0_1 - Virtual channel extension for programmed data ID 0. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di0_vcx_0_1_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vc_MASK (0x300U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vc_SHIFT (8U) /*! di1_vc - Virtual channel for programmed data ID 1. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vcx_0_1_MASK (0xC00U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vcx_0_1_SHIFT (10U) /*! di1_vcx_0_1 - Virtual channel extension for programmed data ID 1. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di1_vcx_0_1_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vc_MASK (0x30000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vc_SHIFT (16U) /*! di2_vc - Virtual channel for programmed data ID 2. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vcx_0_1_MASK (0xC0000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vcx_0_1_SHIFT (18U) /*! di2_vcx_0_1 - Virtual channel extension for programmed data ID 2. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di2_vcx_0_1_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vc_MASK (0x3000000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vc_SHIFT (24U) /*! di3_vc - Virtual channel for programmed data ID 3. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vcx_0_1_MASK (0xC000000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vcx_0_1_SHIFT (26U) /*! di3_vcx_0_1 - Virtual channel extension for programmed data ID 3. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_1_di3_vcx_0_1_MASK) /*! @} */ /*! @name DATA_IDS_VC_2 - Virtual Channel fields for Data ID Monitors 2. */ /*! @{ */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vc_MASK (0x3U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vc_SHIFT (0U) /*! di4_vc - Virtual channel for programmed data ID 4. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vcx_0_1_MASK (0xCU) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vcx_0_1_SHIFT (2U) /*! di4_vcx_0_1 - Virtual channel extension for programmed data ID 4. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di4_vcx_0_1_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vc_MASK (0x300U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vc_SHIFT (8U) /*! di5_vc - Virtual channel for programmed data ID 5. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vcx_0_1_MASK (0xC00U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vcx_0_1_SHIFT (10U) /*! di5_vcx_0_1 - Virtual channel extension for programmed data ID 5. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di5_vcx_0_1_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vc_MASK (0x30000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vc_SHIFT (16U) /*! di6_vc - Virtual channel for programmed data ID 6. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vcx_0_1_MASK (0xC0000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vcx_0_1_SHIFT (18U) /*! di6_vcx_0_1 - Virtual channel extension for programmed data ID 6. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di6_vcx_0_1_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vc_MASK (0x3000000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vc_SHIFT (24U) /*! di7_vc - Virtual channel for programmed data ID 7. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vc(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vc_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vc_MASK) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vcx_0_1_MASK (0xC000000U) #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vcx_0_1_SHIFT (26U) /*! di7_vcx_0_1 - Virtual channel extension for programmed data ID 7. */ #define CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vcx_0_1_SHIFT)) & CAMERA_MIPI_CSI2_DATA_IDS_VC_2_di7_vcx_0_1_MASK) /*! @} */ /*! @name PHY_SHUTDOWNZ - PHY Shutdown. */ /*! @{ */ #define CAMERA_MIPI_CSI2_PHY_SHUTDOWNZ_phy_shutdownz_MASK (0x1U) #define CAMERA_MIPI_CSI2_PHY_SHUTDOWNZ_phy_shutdownz_SHIFT (0U) /*! phy_shutdownz - Shutdown input. * 0b0..Enter power down mode. * 0b1..Exit from power down mode. */ #define CAMERA_MIPI_CSI2_PHY_SHUTDOWNZ_phy_shutdownz(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_SHUTDOWNZ_phy_shutdownz_SHIFT)) & CAMERA_MIPI_CSI2_PHY_SHUTDOWNZ_phy_shutdownz_MASK) /*! @} */ /*! @name DPHY_RSTZ - DPHY reset. */ /*! @{ */ #define CAMERA_MIPI_CSI2_DPHY_RSTZ_dphy_rstz_MASK (0x1U) #define CAMERA_MIPI_CSI2_DPHY_RSTZ_dphy_rstz_SHIFT (0U) /*! dphy_rstz - PHY reset. * 0b0..Put PHY in reset. * 0b1..Release PHY from reset. */ #define CAMERA_MIPI_CSI2_DPHY_RSTZ_dphy_rstz(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_DPHY_RSTZ_dphy_rstz_SHIFT)) & CAMERA_MIPI_CSI2_DPHY_RSTZ_dphy_rstz_MASK) /*! @} */ /*! @name PHY_RX - RX PHY status. */ /*! @{ */ #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_0_SHIFT (0U) /*! phy_rxulpsesc_0 - Lane module 0 has entered the Ultra Low Power mode. * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_0_SHIFT)) & CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_0_MASK) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_1_SHIFT (1U) /*! phy_rxulpsesc_1 - Lane module 1 has entered the Ultra Low Power mode * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_1_SHIFT)) & CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_1_MASK) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_2_SHIFT (2U) /*! phy_rxulpsesc_2 - Lane module 2 has entered the Ultra Low Power mode * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_2_SHIFT)) & CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_2_MASK) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_3_SHIFT (3U) /*! phy_rxulpsesc_3 - Lane module 3 has entered the Ultra Low Power mode * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_3_SHIFT)) & CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsesc_3_MASK) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsclknot_MASK (0x10000U) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsclknot_SHIFT (16U) /*! phy_rxulpsclknot - Indicates that D-PHY Clock Lane module has entered the Ultra Low Power state. * 0b0..Clock lane is detected in ULPM. * 0b1..Clock lane is not in ULPM. */ #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsclknot(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsclknot_SHIFT)) & CAMERA_MIPI_CSI2_PHY_RX_phy_rxulpsclknot_MASK) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxclkactivehs_MASK (0x20000U) #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxclkactivehs_SHIFT (17U) /*! phy_rxclkactivehs - Indicates that D-PHY clock lane is actively receiving a DDR clock * 0b0..No clock signal is received in the clock lane. * 0b1..High-speed clock signal is received in clock lane. */ #define CAMERA_MIPI_CSI2_PHY_RX_phy_rxclkactivehs(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_RX_phy_rxclkactivehs_SHIFT)) & CAMERA_MIPI_CSI2_PHY_RX_phy_rxclkactivehs_MASK) /*! @} */ /*! @name PHY_STOPSTATE - STOPSTATE PHY status. */ /*! @{ */ #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_0_SHIFT (0U) /*! phy_stopstatedata_0 - Data lane 0 in Stop state. * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_0_SHIFT)) & CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_0_MASK) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_1_SHIFT (1U) /*! phy_stopstatedata_1 - Data lane 1 in Stop state * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_1_SHIFT)) & CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_1_MASK) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_2_SHIFT (2U) /*! phy_stopstatedata_2 - Data lane 2 in Stop state * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_2_SHIFT)) & CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_2_MASK) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_3_SHIFT (3U) /*! phy_stopstatedata_3 - Data lane 3 in Stop state * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_3_SHIFT)) & CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstatedata_3_MASK) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstateclk_MASK (0x10000U) #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstateclk_SHIFT (16U) /*! phy_stopstateclk - D-PHY Clock lane in Stop state * 0b0..Clock lane is not in Stop state. * 0b1..Clock lane is in Stop state. */ #define CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstateclk(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstateclk_SHIFT)) & CAMERA_MIPI_CSI2_PHY_STOPSTATE_phy_stopstateclk_MASK) /*! @} */ /*! @name PHY_TEST_CTRL0 - D-PHY Test and Control interface 0. */ /*! @{ */ #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclr_MASK (0x1U) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclr_SHIFT (0U) /*! phy_testclr - Performs vendor specific interface initialization. */ #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclr(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclr_SHIFT)) & CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclr_MASK) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclk_MASK (0x2U) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclk_SHIFT (1U) /*! phy_testclk - Clock to capture testdin bus contents into the module, with testen signal controlling the operation selection. */ #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclk(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclk_SHIFT)) & CAMERA_MIPI_CSI2_PHY_TEST_CTRL0_phy_testclk_MASK) /*! @} */ /*! @name PHY_TEST_CTRL1 - D-PHY Test and Control interface 1. */ /*! @{ */ #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdin_MASK (0xFFU) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdin_SHIFT (0U) /*! phy_testdin - Test interface 8-bit data input for programming internal registers and accessing test functionalities. */ #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdin(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdin_SHIFT)) & CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdin_MASK) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdout_MASK (0xFF00U) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdout_SHIFT (8U) /*! phy_testdout - Vendor-specific 8-bit data output for reading data and other probing functionalities. */ #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdout(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdout_SHIFT)) & CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testdout_MASK) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testen_MASK (0x10000U) #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testen_SHIFT (16U) /*! phy_testen - Data write on the rising edge of TESTCLK or address write on the falling edge of TESTCLK * 0b0..Configures a data write operation on the rising edge of TESTCLK. * 0b1..Configures an address write operation on the falling edge of TESTCLK */ #define CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testen(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testen_SHIFT)) & CAMERA_MIPI_CSI2_PHY_TEST_CTRL1_phy_testen_MASK) /*! @} */ /*! @name VC_EXTENSION - Virtual Channel Extension. */ /*! @{ */ #define CAMERA_MIPI_CSI2_VC_EXTENSION_vcx_MASK (0x1U) #define CAMERA_MIPI_CSI2_VC_EXTENSION_vcx_SHIFT (0U) /*! vcx - Virtual channel extension * 0b0..Virtual channel extension is enabled. * 0b1..Legacy mode. Virtual channel extension is disabled. */ #define CAMERA_MIPI_CSI2_VC_EXTENSION_vcx(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_VC_EXTENSION_vcx_SHIFT)) & CAMERA_MIPI_CSI2_VC_EXTENSION_vcx_MASK) /*! @} */ /*! @name PHY_CAL - PHY Calibration. */ /*! @{ */ #define CAMERA_MIPI_CSI2_PHY_CAL_rxskewcalhs_MASK (0x1U) #define CAMERA_MIPI_CSI2_PHY_CAL_rxskewcalhs_SHIFT (0U) /*! rxskewcalhs - A low-to-high transition on rxskewcalhs signal means that the PHY has initiated the de-skew calibration. * 0b0..No calibration. * 0b1..PHY has initiated the de-skew calibration. */ #define CAMERA_MIPI_CSI2_PHY_CAL_rxskewcalhs(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_PHY_CAL_rxskewcalhs_SHIFT)) & CAMERA_MIPI_CSI2_PHY_CAL_rxskewcalhs_MASK) /*! @} */ /*! @name INT_ST_PHY_FATAL - Fatal interruption caused by PHY. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_0_SHIFT (0U) /*! phy_errsotsynchs_0 - Start of transmission error on data lane 0 (no synchronization achieved). * 0b0..No error * 0b1..Start of transmission error on data lane 0 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_1_SHIFT (1U) /*! phy_errsotsynchs_1 - Start of transmission error on data lane 1 (no synchronization achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 1 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_2_SHIFT (2U) /*! phy_errsotsynchs_2 - Start of transmission error on data lane 2 (no synchronization achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 2 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_3_SHIFT (3U) /*! phy_errsotsynchs_3 - Start of transmission error on data lane 3 (no synchronization achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 3 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_FATAL_phy_errsotsynchs_3_MASK) /*! @} */ /*! @name INT_MSK_PHY_FATAL - Mask for fatal interruption caused by PHY. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_SHIFT (0U) /*! mask_phy_errsotsynchs_0 - Mask for phy_errsotsynchs_0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_SHIFT (1U) /*! mask_phy_errsotsynchs_1 - Mask for phy_errsotsynchs_1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_SHIFT (2U) /*! mask_phy_errsotsynchs_2 - Mask for phy_errsotsynchs_2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_SHIFT (3U) /*! mask_phy_errsotsynchs_3 - Mask for phy_errsotsynchs_3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_MASK) /*! @} */ /*! @name INT_FORCE_PHY_FATAL - Force for fatal interruption caused by PHY. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_SHIFT (0U) /*! force_phy_errsotsynchs_0 - Force phy_errsotsynchs_0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_SHIFT (1U) /*! force_phy_errsotsynchs_1 - Force phy_errsotsynchs_1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_SHIFT (2U) /*! force_phy_errsotsynchs_2 - Force phy_errsotsynchs_2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_SHIFT (3U) /*! force_phy_errsotsynchs_3 - Force phy_errsotsynchs_3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_MASK) /*! @} */ /*! @name INT_ST_PKT_FATAL - Fatal interruption caused during Packet Construction. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_err_ecc_double_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_err_ecc_double_SHIFT (0U) /*! err_ecc_double - Header ECC contains at least 2 errors, unrecoverable. * 0b0..No error. * 0b1..Header ECC contains at least 2 errors, unrecoverable. */ #define CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_err_ecc_double(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_err_ecc_double_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_err_ecc_double_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_shorter_payload_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_shorter_payload_SHIFT (1U) /*! shorter_payload - Reported greater WC than received, unrecoverable. * 0b0..No error. * 0b1..Reported greater Word Count than received, unrecoverable. */ #define CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_shorter_payload(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_shorter_payload_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PKT_FATAL_shorter_payload_MASK) /*! @} */ /*! @name INT_MSK_PKT_FATAL - Mask for fatal interruption caused during Packet Construction. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_err_ecc_double_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_err_ecc_double_SHIFT (0U) /*! mask_err_ecc_double - Mask for err_ecc_double. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_err_ecc_double(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_err_ecc_double_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_err_ecc_double_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_shorter_payload_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_shorter_payload_SHIFT (1U) /*! mask_shorter_payload - Mask for shorter_payload. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_shorter_payload(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_shorter_payload_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PKT_FATAL_mask_shorter_payload_MASK) /*! @} */ /*! @name INT_FORCE_PKT_FATAL - Force for fatal interruption caused during Packet Construction. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_err_ecc_double_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_err_ecc_double_SHIFT (0U) /*! force_err_ecc_double - Force err_ecc_double. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_err_ecc_double(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_err_ecc_double_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_err_ecc_double_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_shorter_payload_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_shorter_payload_SHIFT (1U) /*! force_shorter_payload - Force shorter_payload. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_shorter_payload(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_shorter_payload_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PKT_FATAL_force_shorter_payload_MASK) /*! @} */ /*! @name INT_ST_PHY - Interruption caused by PHY. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_0_SHIFT (0U) /*! phy_errsoths_0 - Start of transmission error on data lane 0 (synchronization can still be achieved). * 0b0..No error * 0b1..Start of transmission error on data lane 0 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_1_SHIFT (1U) /*! phy_errsoths_1 - Start of transmission error on data lane 1 (synchronization can still be achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 1 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_2_SHIFT (2U) /*! phy_errsoths_2 - Start of transmission error on data lane 2 (synchronization can still be achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 2 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_3_SHIFT (3U) /*! phy_errsoths_3 - Start of transmission error on data lane 3 (synchronization can still be achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 3 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_errsoths_3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_0_MASK (0x10000U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_0_SHIFT (16U) /*! phy_erresc_0 - Escape Entry Error on data lane 0. * 0b1..Escape entry error on data lane 0 * 0b0..No error */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_1_MASK (0x20000U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_1_SHIFT (17U) /*! phy_erresc_1 - Escape Entry Error on data lane 1 * 0b0..No error * 0b1..Escape entry error on data lane 1 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_2_MASK (0x40000U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_2_SHIFT (18U) /*! phy_erresc_2 - Escape Entry Error on data lane 2 * 0b0..No error * 0b1..Escape entry error on data lane 2 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_3_MASK (0x80000U) #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_3_SHIFT (19U) /*! phy_erresc_3 - Escape Entry Error on data lane 3 * 0b0..No error * 0b1..Escape entry error on data lane 3 */ #define CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PHY_phy_erresc_3_MASK) /*! @} */ /*! @name INT_MSK_PHY - Mask for interruption caused by PHY. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_0_SHIFT (0U) /*! mask_phy_errsoths_0 - Mask for phy_errsoths_0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_1_SHIFT (1U) /*! mask_phy_errsoths_1 - Mask for phy_errsoths_1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_2_SHIFT (2U) /*! mask_phy_errsoths_2 - Mask for phy_errsoths_2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_3_SHIFT (3U) /*! mask_phy_errsoths_3 - Mask for phy_errsoths_3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_errsoths_3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_0_MASK (0x10000U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_0_SHIFT (16U) /*! mask_phy_erresc_0 - Mask for phy_erresc_0. * 0b1..Enable the interrupt source. * 0b0..Interrupt source is masked. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_1_MASK (0x20000U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_1_SHIFT (17U) /*! mask_phy_erresc_1 - Mask for phy_erresc_1 * 0b1..Enable the interrupt source. * 0b0..Interrupt source is masked. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_2_MASK (0x40000U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_2_SHIFT (18U) /*! mask_phy_erresc_2 - Mask for phy_erresc_2 * 0b1..Enable the interrupt source. * 0b0..Interrupt source is masked. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_3_MASK (0x80000U) #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_3_SHIFT (19U) /*! mask_phy_erresc_3 - Mask for phy_erresc_3 * 0b1..Enable the interrupt source. * 0b0..Interrupt source is masked. */ #define CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PHY_mask_phy_erresc_3_MASK) /*! @} */ /*! @name INT_FORCE_PHY - Force for interruption caused by PHY. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_0_SHIFT (0U) /*! force_phy_errsoths_0 - Force phy_errsoths_0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_1_SHIFT (1U) /*! force_phy_errsoths_1 - Force phy_errsoths_1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_2_SHIFT (2U) /*! force_phy_errsoths_2 - Force phy_errsoths_2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_3_SHIFT (3U) /*! force_phy_errsoths_3 - Force phy_errsoths_3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_errsoths_3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_0_MASK (0x10000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_0_SHIFT (16U) /*! force_phy_erresc_0 - Force phy_erresc_0 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_1_MASK (0x20000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_1_SHIFT (17U) /*! force_phy_erresc_1 - Force phy_erresc_1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_2_MASK (0x40000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_2_SHIFT (18U) /*! force_phy_erresc_2 - Force phy_erresc_2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_3_MASK (0x80000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_3_SHIFT (19U) /*! force_phy_erresc_3 - Force phy_erresc_3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PHY_force_phy_erresc_3_MASK) /*! @} */ /*! @name INT_ST_LINE - Interruption occurred during Line construction. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di0_SHIFT (0U) /*! err_l_bndry_match_di0 - Error matching line start with line end for vc0 and dt0 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di1_SHIFT (1U) /*! err_l_bndry_match_di1 - Error matching line start with line end for vc1 and dt1 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di2_SHIFT (2U) /*! err_l_bndry_match_di2 - Error matching line start with line end for vc2 and dt2 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di3_SHIFT (3U) /*! err_l_bndry_match_di3 - Error matching line start with line end for vc3 and dt3 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di4_SHIFT (4U) /*! err_l_bndry_match_di4 - Error matching line start with line end for vc4 and dt4 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di5_SHIFT (5U) /*! err_l_bndry_match_di5 - Error matching line start with line end for vc5 and dt5 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di6_SHIFT (6U) /*! err_l_bndry_match_di6 - Error matching line start with line end for vc6 and dt6 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di7_SHIFT (7U) /*! err_l_bndry_match_di7 - Error matching line start with line end for vc7 and dt7 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_bndry_match_di7_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di0_MASK (0x10000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di0_SHIFT (16U) /*! err_l_seq_di0 - Error in the sequence of lines for vc0 and dt0 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di1_MASK (0x20000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di1_SHIFT (17U) /*! err_l_seq_di1 - Error in the sequence of lines for vc1 and dt1 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di2_MASK (0x40000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di2_SHIFT (18U) /*! err_l_seq_di2 - Error in the sequence of lines for vc2 and dt2 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di3_MASK (0x80000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di3_SHIFT (19U) /*! err_l_seq_di3 - Error in the sequence of lines for vc3 and dt3 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di4_MASK (0x100000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di4_SHIFT (20U) /*! err_l_seq_di4 - Error in the sequence of lines for vc4 and dt4 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di5_MASK (0x200000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di5_SHIFT (21U) /*! err_l_seq_di5 - Error in the sequence of lines for vc5 and dt5 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di6_MASK (0x400000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di6_SHIFT (22U) /*! err_l_seq_di6 - Error in the sequence of lines for vc6 and dt6 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di7_MASK (0x800000U) #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di7_SHIFT (23U) /*! err_l_seq_di7 - Error in the sequence of lines for vc7 and dt7 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_LINE_err_l_seq_di7_MASK) /*! @} */ /*! @name INT_MSK_LINE - Mask for interruption occurred during Line construction. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di0_SHIFT (0U) /*! mask_err_l_bndry_match_di0 - Mask for err_l_bndry_match_di0 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di1_SHIFT (1U) /*! mask_err_l_bndry_match_di1 - Mask for err_l_bndry_match_di1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di2_SHIFT (2U) /*! mask_err_l_bndry_match_di2 - Mask for err_l_bndry_match_di2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di3_SHIFT (3U) /*! mask_err_l_bndry_match_di3 - Mask for err_l_bndry_match_di3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di4_SHIFT (4U) /*! mask_err_l_bndry_match_di4 - Mask for err_l_bndry_match_di4 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di5_SHIFT (5U) /*! mask_err_l_bndry_match_di5 - Mask for err_l_bndry_match_di5 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di6_SHIFT (6U) /*! mask_err_l_bndry_match_di6 - Mask for err_l_bndry_match_di6 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di7_SHIFT (7U) /*! mask_err_l_bndry_match_di7 - Mask for err_l_bndry_match_di7 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_bndry_match_di7_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di0_MASK (0x10000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di0_SHIFT (16U) /*! mask_err_l_seq_di0 - Mask for err_l_seq_di0 * 0b1..Enable the interrupt source. * 0b0..Interrupt source is masked. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di1_MASK (0x20000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di1_SHIFT (17U) /*! mask_err_l_seq_di1 - Mask for err_l_seq_di1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di2_MASK (0x40000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di2_SHIFT (18U) /*! mask_err_l_seq_di2 - Mask for err_l_seq_di2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di3_MASK (0x80000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di3_SHIFT (19U) /*! mask_err_l_seq_di3 - Mask for err_l_seq_di3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di4_MASK (0x100000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di4_SHIFT (20U) /*! mask_err_l_seq_di4 - Mask for err_l_seq_di4 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di5_MASK (0x200000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di5_SHIFT (21U) /*! mask_err_l_seq_di5 - Mask for err_l_seq_di5 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di6_MASK (0x400000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di6_SHIFT (22U) /*! mask_err_l_seq_di6 - Mask for err_l_seq_di6 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di7_MASK (0x800000U) #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di7_SHIFT (23U) /*! mask_err_l_seq_di7 - Mask for err_l_seq_di7 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_LINE_mask_err_l_seq_di7_MASK) /*! @} */ /*! @name INT_FORCE_LINE - Force for interruption occurred during Line construction. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di0_SHIFT (0U) /*! force_err_l_bndry_match_di0 - Force err_l_bndry_match_di0 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di1_SHIFT (1U) /*! force_err_l_bndry_match_di1 - Force err_l_bndry_match_di1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di2_SHIFT (2U) /*! force_err_l_bndry_match_di2 - Force err_l_bndry_match_di2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di3_SHIFT (3U) /*! force_err_l_bndry_match_di3 - Force err_l_bndry_match_di3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di4_SHIFT (4U) /*! force_err_l_bndry_match_di4 - Force err_l_bndry_match_di4 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di5_SHIFT (5U) /*! force_err_l_bndry_match_di5 - Force err_l_bndry_match_di5 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di6_SHIFT (6U) /*! force_err_l_bndry_match_di6 - Force err_l_bndry_match_di6 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di7_SHIFT (7U) /*! force_err_l_bndry_match_di7 - Force err_l_bndry_match_di7 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_bndry_match_di7_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di0_MASK (0x10000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di0_SHIFT (16U) /*! force_err_l_seq_di0 - Force err_l_seq_di0 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di1_MASK (0x20000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di1_SHIFT (17U) /*! force_err_l_seq_di1 - Force err_l_seq_di1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di2_MASK (0x40000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di2_SHIFT (18U) /*! force_err_l_seq_di2 - Force err_l_seq_di2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di3_MASK (0x80000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di3_SHIFT (19U) /*! force_err_l_seq_di3 - Force err_l_seq_di3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di4_MASK (0x100000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di4_SHIFT (20U) /*! force_err_l_seq_di4 - Force err_l_seq_di4 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di5_MASK (0x200000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di5_SHIFT (21U) /*! force_err_l_seq_di5 - Force err_l_seq_di5 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di6_MASK (0x400000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di6_SHIFT (22U) /*! force_err_l_seq_di6 - Force err_l_seq_di6 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di7_MASK (0x800000U) #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di7_SHIFT (23U) /*! force_err_l_seq_di7 - Force err_l_seq_di7 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_LINE_force_err_l_seq_di7_MASK) /*! @} */ /*! @name INT_ST_BNDRY_FRAME_FATAL - Fatal Interruption caused by Frame Boundaries. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT (0U) /*! err_f_bndry_match_vc0 - Error matching Frame Start with Frame End for virtual channel 0. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT (1U) /*! err_f_bndry_match_vc1 - Error matching Frame Start with Frame End for virtual channel 1. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT (2U) /*! err_f_bndry_match_vc2 - Error matching Frame Start with Frame End for virtual channel 2. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT (3U) /*! err_f_bndry_match_vc3 - Error matching Frame Start with Frame End for virtual channel 3. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT (4U) /*! err_f_bndry_match_vc4 - Error matching Frame Start with Frame End for virtual channel 4. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT (5U) /*! err_f_bndry_match_vc5 - Error matching Frame Start with Frame End for virtual channel 5. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT (6U) /*! err_f_bndry_match_vc6 - Error matching Frame Start with Frame End for virtual channel 6. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT (7U) /*! err_f_bndry_match_vc7 - Error matching Frame Start with Frame End for virtual channel 7. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT (8U) /*! err_f_bndry_match_vc8 - Error matching Frame Start with Frame End for virtual channel 8. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT (9U) /*! err_f_bndry_match_vc9 - Error matching Frame Start with Frame End for virtual channel 9. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT (10U) /*! err_f_bndry_match_vc10 - Error matching Frame Start with Frame End for virtual channel 10. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT (11U) /*! err_f_bndry_match_vc11 - Error matching Frame Start with Frame End for virtual channel 11. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT (12U) /*! err_f_bndry_match_vc12 - Error matching Frame Start with Frame End for virtual channel 12. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT (13U) /*! err_f_bndry_match_vc13 - Error matching Frame Start with Frame End for virtual channel 13. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT (14U) /*! err_f_bndry_match_vc14 - Error matching Frame Start with Frame End for virtual channel 14. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT (15U) /*! err_f_bndry_match_vc15 - Error matching Frame Start with Frame End for virtual channel 15. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK) /*! @} */ /*! @name INT_MSK_BNDRY_FRAME_FATAL - Mask for fatal interruption caused by Frame Boundaries. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT (0U) /*! err_f_bndry_match_vc0 - Mask for err_f_bndry_match_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT (1U) /*! err_f_bndry_match_vc1 - Mask for err_f_bndry_match_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT (2U) /*! err_f_bndry_match_vc2 - Mask for err_f_bndry_match_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT (3U) /*! err_f_bndry_match_vc3 - Mask for err_f_bndry_match_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT (4U) /*! err_f_bndry_match_vc4 - Mask for err_f_bndry_match_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT (5U) /*! err_f_bndry_match_vc5 - Mask for err_f_bndry_match_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT (6U) /*! err_f_bndry_match_vc6 - Mask for err_f_bndry_match_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT (7U) /*! err_f_bndry_match_vc7 - Mask for err_f_bndry_match_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT (8U) /*! err_f_bndry_match_vc8 - Mask for err_f_bndry_match_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT (9U) /*! err_f_bndry_match_vc9 - Mask for err_f_bndry_match_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT (10U) /*! err_f_bndry_match_vc10 - Mask for err_f_bndry_match_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT (11U) /*! err_f_bndry_match_vc11 - Mask for err_f_bndry_match_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT (12U) /*! err_f_bndry_match_vc12 - Mask for err_f_bndry_match_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT (13U) /*! err_f_bndry_match_vc13 - Mask for err_f_bndry_match_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT (14U) /*! err_f_bndry_match_vc14 - Mask for err_f_bndry_match_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT (15U) /*! err_f_bndry_match_vc15 - Mask for err_f_bndry_match_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK) /*! @} */ /*! @name INT_FORCE_BNDRY_FRAME_FATAL - Force for fatal interruption caused by Frame Boundaries. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT (0U) /*! err_f_bndry_match_vc0 - Force err_f_bndry_match_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT (1U) /*! err_f_bndry_match_vc1 - Force err_f_bndry_match_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT (2U) /*! err_f_bndry_match_vc2 - Force err_f_bndry_match_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT (3U) /*! err_f_bndry_match_vc3 - Force err_f_bndry_match_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT (4U) /*! err_f_bndry_match_vc4 - Force err_f_bndry_match_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT (5U) /*! err_f_bndry_match_vc5 - Force err_f_bndry_match_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT (6U) /*! err_f_bndry_match_vc6 - Force err_f_bndry_match_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT (7U) /*! err_f_bndry_match_vc7 - Force err_f_bndry_match_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT (8U) /*! err_f_bndry_match_vc8 - Force err_f_bndry_match_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT (9U) /*! err_f_bndry_match_vc9 - Force err_f_bndry_match_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT (10U) /*! err_f_bndry_match_vc10 - Force err_f_bndry_match_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT (11U) /*! err_f_bndry_match_vc11 - Force err_f_bndry_match_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT (12U) /*! err_f_bndry_match_vc12 - Force err_f_bndry_match_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT (13U) /*! err_f_bndry_match_vc13 - Force err_f_bndry_match_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT (14U) /*! err_f_bndry_match_vc14 - Force err_f_bndry_match_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT (15U) /*! err_f_bndry_match_vc15 - Force err_f_bndry_match_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK) /*! @} */ /*! @name INT_ST_SEQ_FRAME_FATAL - Fatal Interruption caused by Frame Sequence. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT (0U) /*! err_f_seq_vc0 - Incorrect Frame sequence detected in virtual channel 0. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT (1U) /*! err_f_seq_vc1 - Incorrect Frame sequence detected in virtual channel 1. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT (2U) /*! err_f_seq_vc2 - Incorrect Frame sequence detected in virtual channel 2. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT (3U) /*! err_f_seq_vc3 - Incorrect Frame sequence detected in virtual channel 3. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT (4U) /*! err_f_seq_vc4 - Incorrect Frame sequence detected in virtual channel 4. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT (5U) /*! err_f_seq_vc5 - Incorrect Frame sequence detected in virtual channel 5. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT (6U) /*! err_f_seq_vc6 - Incorrect Frame sequence detected in virtual channel 6. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT (7U) /*! err_f_seq_vc7 - Incorrect Frame sequence detected in virtual channel 7. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT (8U) /*! err_f_seq_vc8 - Incorrect Frame sequence detected in virtual channel 8. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT (9U) /*! err_f_seq_vc9 - Incorrect Frame sequence detected in virtual channel 9. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT (10U) /*! err_f_seq_vc10 - Incorrect Frame sequence detected in virtual channel 10. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT (11U) /*! err_f_seq_vc11 - Incorrect Frame sequence detected in virtual channel 11. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT (12U) /*! err_f_seq_vc12 - Incorrect Frame sequence detected in virtual channel 12. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT (13U) /*! err_f_seq_vc13 - Incorrect Frame sequence detected in virtual channel 13. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT (14U) /*! err_f_seq_vc14 - Incorrect Frame sequence detected in virtual channel 14. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT (15U) /*! err_f_seq_vc15 - Incorrect Frame sequence detected in virtual channel 15. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK) /*! @} */ /*! @name INT_MSK_SEQ_FRAME_FATAL - Mask for fatal interruption caused by Frame Sequence. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT (0U) /*! err_f_seq_vc0 - Mask for err_f_seq_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT (1U) /*! err_f_seq_vc1 - Mask for err_f_seq_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT (2U) /*! err_f_seq_vc2 - Mask for err_f_seq_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT (3U) /*! err_f_seq_vc3 - Mask for err_f_seq_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT (4U) /*! err_f_seq_vc4 - Mask for err_f_seq_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT (5U) /*! err_f_seq_vc5 - Mask for err_f_seq_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT (6U) /*! err_f_seq_vc6 - Mask for err_f_seq_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT (7U) /*! err_f_seq_vc7 - Mask for err_f_seq_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT (8U) /*! err_f_seq_vc8 - Mask for err_f_seq_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT (9U) /*! err_f_seq_vc9 - Mask for err_f_seq_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT (10U) /*! err_f_seq_vc10 - Mask for err_f_seq_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT (11U) /*! err_f_seq_vc11 - Mask for err_f_seq_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT (12U) /*! err_f_seq_vc12 - Mask for err_f_seq_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT (13U) /*! err_f_seq_vc13 - Mask for err_f_seq_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT (14U) /*! err_f_seq_vc14 - Mask for err_f_seq_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT (15U) /*! err_f_seq_vc15 - Mask for err_f_seq_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK) /*! @} */ /*! @name INT_FORCE_SEQ_FRAME_FATAL - Force for fatal interruption caused by Frame Sequence. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT (0U) /*! err_f_seq_vc0 - Force err_f_seq_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT (1U) /*! err_f_seq_vc1 - Force err_f_seq_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT (2U) /*! err_f_seq_vc2 - Force err_f_seq_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT (3U) /*! err_f_seq_vc3 - Force err_f_seq_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT (4U) /*! err_f_seq_vc4 - Force err_f_seq_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT (5U) /*! err_f_seq_vc5 - Force err_f_seq_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT (6U) /*! err_f_seq_vc6 - Force err_f_seq_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT (7U) /*! err_f_seq_vc7 - Force err_f_seq_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT (8U) /*! err_f_seq_vc8 - Force err_f_seq_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT (9U) /*! err_f_seq_vc9 - Force err_f_seq_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT (10U) /*! err_f_seq_vc10 - Force err_f_seq_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT (11U) /*! err_f_seq_vc11 - Force err_f_seq_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT (12U) /*! err_f_seq_vc12 - Force err_f_seq_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT (13U) /*! err_f_seq_vc13 - Force err_f_seq_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT (14U) /*! err_f_seq_vc14 - Force err_f_seq_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT (15U) /*! err_f_seq_vc15 - Force err_f_seq_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK) /*! @} */ /*! @name INT_ST_CRC_FRAME_FATAL - Fatal Interruption caused by Frame CRC. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT (0U) /*! err_frame_data_vc0 - Last received Frame in virtual channel 0, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT (1U) /*! err_frame_data_vc1 - Last received Frame in virtual channel 1, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT (2U) /*! err_frame_data_vc2 - Last received Frame in virtual channel 2, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT (3U) /*! err_frame_data_vc3 - Last received Frame in virtual channel 3, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT (4U) /*! err_frame_data_vc4 - Last received Frame in virtual channel 4, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT (5U) /*! err_frame_data_vc5 - Last received Frame in virtual channel 5, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT (6U) /*! err_frame_data_vc6 - Last received Frame in virtual channel 6, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT (7U) /*! err_frame_data_vc7 - Last received Frame in virtual channel 7, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT (8U) /*! err_frame_data_vc8 - Last received Frame in virtual channel 8, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT (9U) /*! err_frame_data_vc9 - Last received Frame in virtual channel 9, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT (10U) /*! err_frame_data_vc10 - Last received Frame in virtual channel 10, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT (11U) /*! err_frame_data_vc11 - Last received Frame in virtual channel 11, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT (12U) /*! err_frame_data_vc12 - Last received Frame in virtual channel 12, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT (13U) /*! err_frame_data_vc13 - Last received Frame in virtual channel 13, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT (14U) /*! err_frame_data_vc14 - Last received Frame in virtual channel 14, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT (15U) /*! err_frame_data_vc15 - Last received Frame in virtual channel 15, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_MASK) /*! @} */ /*! @name INT_MSK_CRC_FRAME_FATAL - Mask for fatal interruption caused by Frame CRC. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT (0U) /*! err_frame_data_vc0 - Mask for err_frame_data_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT (1U) /*! err_frame_data_vc1 - Mask for err_frame_data_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT (2U) /*! err_frame_data_vc2 - Mask for err_frame_data_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT (3U) /*! err_frame_data_vc3 - Mask for err_frame_data_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT (4U) /*! err_frame_data_vc4 - Mask for err_frame_data_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT (5U) /*! err_frame_data_vc5 - Mask for err_frame_data_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT (6U) /*! err_frame_data_vc6 - Mask for err_frame_data_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT (7U) /*! err_frame_data_vc7 - Mask for err_frame_data_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT (8U) /*! err_frame_data_vc8 - Mask for err_frame_data_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT (9U) /*! err_frame_data_vc9 - Mask for err_frame_data_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT (10U) /*! err_frame_data_vc10 - Mask for err_frame_data_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT (11U) /*! err_frame_data_vc11 - Mask for err_frame_data_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT (12U) /*! err_frame_data_vc12 - Mask for err_frame_data_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT (13U) /*! err_frame_data_vc13 - Mask for err_frame_data_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT (14U) /*! err_frame_data_vc14 - Mask for err_frame_data_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT (15U) /*! err_frame_data_vc15 - Mask for err_frame_data_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_MASK) /*! @} */ /*! @name INT_FORCE_CRC_FRAME_FATAL - Force for fatal interruption caused by Frame CRC. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT (0U) /*! err_frame_data_vc0 - Force err_frame_data_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT (1U) /*! err_frame_data_vc1 - Force err_frame_data_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT (2U) /*! err_frame_data_vc2 - Force err_frame_data_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT (3U) /*! err_frame_data_vc3 - Force err_frame_data_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT (4U) /*! err_frame_data_vc4 - Force err_frame_data_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT (5U) /*! err_frame_data_vc5 - Force err_frame_data_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT (6U) /*! err_frame_data_vc6 - Force err_frame_data_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT (7U) /*! err_frame_data_vc7 - Force err_frame_data_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT (8U) /*! err_frame_data_vc8 - Force err_frame_data_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT (9U) /*! err_frame_data_vc9 - Force err_frame_data_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT (10U) /*! err_frame_data_vc10 - Force err_frame_data_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT (11U) /*! err_frame_data_vc11 - Force err_frame_data_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT (12U) /*! err_frame_data_vc12 - Force err_frame_data_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT (13U) /*! err_frame_data_vc13 - Force err_frame_data_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT (14U) /*! err_frame_data_vc14 - Force err_frame_data_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT (15U) /*! err_frame_data_vc15 - Force err_frame_data_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_MASK) /*! @} */ /*! @name INT_ST_PLD_CRC_FATAL - Fatal Interruption caused by Payload CRC. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc0_SHIFT (0U) /*! err_crc_vc0 - Payload Checksum error detected on virtual channel 0. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc1_SHIFT (1U) /*! err_crc_vc1 - Payload Checksum error detected on virtual channel 1. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc2_SHIFT (2U) /*! err_crc_vc2 - Payload Checksum error detected on virtual channel 2. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc3_SHIFT (3U) /*! err_crc_vc3 - Payload Checksum error detected on virtual channel 3. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc4_SHIFT (4U) /*! err_crc_vc4 - Payload Checksum error detected on virtual channel 4. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc5_SHIFT (5U) /*! err_crc_vc5 - Payload Checksum error detected on virtual channel 5. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc6_SHIFT (6U) /*! err_crc_vc6 - Payload Checksum error detected on virtual channel 6. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc7_SHIFT (7U) /*! err_crc_vc7 - Payload Checksum error detected on virtual channel 7. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc8_SHIFT (8U) /*! err_crc_vc8 - Payload Checksum error detected on virtual channel 8. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc9_SHIFT (9U) /*! err_crc_vc9 - Payload Checksum error detected on virtual channel 9. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc10_SHIFT (10U) /*! err_crc_vc10 - Payload Checksum error detected on virtual channel 10. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc11_SHIFT (11U) /*! err_crc_vc11 - Payload Checksum error detected on virtual channel 11. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc12_SHIFT (12U) /*! err_crc_vc12 - Payload Checksum error detected on virtual channel 12. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc13_SHIFT (13U) /*! err_crc_vc13 - Payload Checksum error detected on virtual channel 13. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc14_SHIFT (14U) /*! err_crc_vc14 - Payload Checksum error detected on virtual channel 14. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc15_SHIFT (15U) /*! err_crc_vc15 - Payload Checksum error detected on virtual channel 15. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_PLD_CRC_FATAL_err_crc_vc15_MASK) /*! @} */ /*! @name INT_MSK_PLD_CRC_FATAL - Mask for fatal interruption caused by Payload CRC. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_SHIFT (0U) /*! err_crc_vc0 - Mask for err_crc_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_SHIFT (1U) /*! err_crc_vc1 - Mask for err_crc_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_SHIFT (2U) /*! err_crc_vc2 - Mask for err_crc_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_SHIFT (3U) /*! err_crc_vc3 - Mask for err_crc_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_SHIFT (4U) /*! err_crc_vc4 - Mask for err_crc_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_SHIFT (5U) /*! err_crc_vc5 - Mask for err_crc_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_SHIFT (6U) /*! err_crc_vc6 - Mask for err_crc_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_SHIFT (7U) /*! err_crc_vc7 - Mask for err_crc_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_SHIFT (8U) /*! err_crc_vc8 - Mask for err_crc_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_SHIFT (9U) /*! err_crc_vc9 - Mask for err_crc_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_SHIFT (10U) /*! err_crc_vc10 - Mask for err_crc_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_SHIFT (11U) /*! err_crc_vc11 - Mask for err_crc_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_SHIFT (12U) /*! err_crc_vc12 - Mask for err_crc_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_SHIFT (13U) /*! err_crc_vc13 - Mask for err_crc_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_SHIFT (14U) /*! err_crc_vc14 - Mask for err_crc_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_SHIFT (15U) /*! err_crc_vc15 - Mask for err_crc_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_MASK) /*! @} */ /*! @name INT_FORCE_PLD_CRC_FATAL - Force for fatal interruption caused by Payload CRC. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_SHIFT (0U) /*! err_crc_vc0 - Force err_crc_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_SHIFT (1U) /*! err_crc_vc1 - Force err_crc_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_SHIFT (2U) /*! err_crc_vc2 - Force err_crc_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_SHIFT (3U) /*! err_crc_vc3 - Force err_crc_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_SHIFT (4U) /*! err_crc_vc4 - Force err_crc_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_SHIFT (5U) /*! err_crc_vc5 - Force err_crc_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_SHIFT (6U) /*! err_crc_vc6 - Force err_crc_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_SHIFT (7U) /*! err_crc_vc7 - Force err_crc_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_SHIFT (8U) /*! err_crc_vc8 - Force err_crc_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_SHIFT (9U) /*! err_crc_vc9 - Force err_crc_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_SHIFT (10U) /*! err_crc_vc10 - Force err_crc_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_SHIFT (11U) /*! err_crc_vc11 - Force err_crc_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_SHIFT (12U) /*! err_crc_vc12 - Force err_crc_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_SHIFT (13U) /*! err_crc_vc13 - Force err_crc_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_SHIFT (14U) /*! err_crc_vc14 - Force err_crc_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_SHIFT (15U) /*! err_crc_vc15 - Force err_crc_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_MASK) /*! @} */ /*! @name INT_ST_DATA_ID - Interruption caused by Data Type. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc0_SHIFT (0U) /*! err_id_vc0 - Unrecognized or unimplemented data type detected in virtual channel 0. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc1_SHIFT (1U) /*! err_id_vc1 - Unrecognized or unimplemented data type detected in virtual channel 1. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc2_SHIFT (2U) /*! err_id_vc2 - Unrecognized or unimplemented data type detected in virtual channel 2. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc3_SHIFT (3U) /*! err_id_vc3 - Unrecognized or unimplemented data type detected in virtual channel 3. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc4_SHIFT (4U) /*! err_id_vc4 - Unrecognized or unimplemented data type detected in virtual channel 4. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc5_SHIFT (5U) /*! err_id_vc5 - Unrecognized or unimplemented data type detected in virtual channel 5. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc6_SHIFT (6U) /*! err_id_vc6 - Unrecognized or unimplemented data type detected in virtual channel 6. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc7_SHIFT (7U) /*! err_id_vc7 - Unrecognized or unimplemented data type detected in virtual channel 7. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc8_SHIFT (8U) /*! err_id_vc8 - Unrecognized or unimplemented data type detected in virtual channel 8. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc9_SHIFT (9U) /*! err_id_vc9 - Unrecognized or unimplemented data type detected in virtual channel 9. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc10_SHIFT (10U) /*! err_id_vc10 - Unrecognized or unimplemented data type detected in virtual channel 10. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc11_SHIFT (11U) /*! err_id_vc11 - Unrecognized or unimplemented data type detected in virtual channel 11. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc12_SHIFT (12U) /*! err_id_vc12 - Unrecognized or unimplemented data type detected in virtual channel 12. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc13_SHIFT (13U) /*! err_id_vc13 - Unrecognized or unimplemented data type detected in virtual channel 13. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc14_SHIFT (14U) /*! err_id_vc14 - Unrecognized or unimplemented data type detected in virtual channel 14. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc15_SHIFT (15U) /*! err_id_vc15 - Unrecognized or unimplemented data type detected in virtual channel 15. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_DATA_ID_err_id_vc15_MASK) /*! @} */ /*! @name INT_MSK_DATA_ID - Mask for interruption caused by Data Type. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc0_SHIFT (0U) /*! err_id_vc0 - Mask for err_id_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc1_SHIFT (1U) /*! err_id_vc1 - Mask for err_id_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc2_SHIFT (2U) /*! err_id_vc2 - Mask for err_id_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc3_SHIFT (3U) /*! err_id_vc3 - Mask for err_id_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc4_SHIFT (4U) /*! err_id_vc4 - Mask for err_id_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc5_SHIFT (5U) /*! err_id_vc5 - Mask for err_id_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc6_SHIFT (6U) /*! err_id_vc6 - Mask for err_id_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc7_SHIFT (7U) /*! err_id_vc7 - Mask for err_id_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc8_SHIFT (8U) /*! err_id_vc8 - Mask for err_id_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc9_SHIFT (9U) /*! err_id_vc9 - Mask for err_id_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc10_SHIFT (10U) /*! err_id_vc10 - Mask for err_id_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc11_SHIFT (11U) /*! err_id_vc11 - Mask for err_id_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc12_SHIFT (12U) /*! err_id_vc12 - Mask for err_id_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc13_SHIFT (13U) /*! err_id_vc13 - Mask for err_id_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc14_SHIFT (14U) /*! err_id_vc14 - Mask for err_id_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc15_SHIFT (15U) /*! err_id_vc15 - Mask for err_id_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_DATA_ID_err_id_vc15_MASK) /*! @} */ /*! @name INT_FORCE_DATA_ID - Force for interruption caused by Data Type. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc0_SHIFT (0U) /*! err_id_vc0 - Force err_id_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc1_SHIFT (1U) /*! err_id_vc1 - Force err_id_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc2_SHIFT (2U) /*! err_id_vc2 - Force err_id_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc3_SHIFT (3U) /*! err_id_vc3 - Force err_id_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc4_SHIFT (4U) /*! err_id_vc4 - Force err_id_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc5_SHIFT (5U) /*! err_id_vc5 - Force err_id_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc6_SHIFT (6U) /*! err_id_vc6 - Force err_id_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc7_SHIFT (7U) /*! err_id_vc7 - Force err_id_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc8_SHIFT (8U) /*! err_id_vc8 - Force err_id_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc9_SHIFT (9U) /*! err_id_vc9 - Force err_id_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc10_SHIFT (10U) /*! err_id_vc10 - Force err_id_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc11_SHIFT (11U) /*! err_id_vc11 - Force err_id_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc12_SHIFT (12U) /*! err_id_vc12 - Force err_id_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc13_SHIFT (13U) /*! err_id_vc13 - Force err_id_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc14_SHIFT (14U) /*! err_id_vc14 - Force err_id_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc15_SHIFT (15U) /*! err_id_vc15 - Force err_id_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_DATA_ID_err_id_vc15_MASK) /*! @} */ /*! @name INT_ST_ECC_CORRECTED - Interruption caused by Header single bit errors. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT (0U) /*! err_ecc_corrected_vc0 - D-PHY mode: Header error detected and corrected on virtual channel 0. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT (1U) /*! err_ecc_corrected_vc1 - D-PHY mode: Header error detected and corrected on virtual channel 1. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT (2U) /*! err_ecc_corrected_vc2 - D-PHY mode: Header error detected and corrected on virtual channel 2. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT (3U) /*! err_ecc_corrected_vc3 - D-PHY mode: Header error detected and corrected on virtual channel 3. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT (4U) /*! err_ecc_corrected_vc4 - D-PHY mode: Header error detected and corrected on virtual channel 4. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT (5U) /*! err_ecc_corrected_vc5 - D-PHY mode: Header error detected and corrected on virtual channel 5. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT (6U) /*! err_ecc_corrected_vc6 - D-PHY mode: Header error detected and corrected on virtual channel 6. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT (7U) /*! err_ecc_corrected_vc7 - D-PHY mode: Header error detected and corrected on virtual channel 7. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT (8U) /*! err_ecc_corrected_vc8 - D-PHY mode: Header error detected and corrected on virtual channel 8. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT (9U) /*! err_ecc_corrected_vc9 - D-PHY mode: Header error detected and corrected on virtual channel 9. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT (10U) /*! err_ecc_corrected_vc10 - D-PHY mode: Header error detected and corrected on virtual channel 10. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT (11U) /*! err_ecc_corrected_vc11 - D-PHY mode: Header error detected and corrected on virtual channel 11. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT (12U) /*! err_ecc_corrected_vc12 - D-PHY mode: Header error detected and corrected on virtual channel 12. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT (13U) /*! err_ecc_corrected_vc13 - D-PHY mode: Header error detected and corrected on virtual channel 13. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT (14U) /*! err_ecc_corrected_vc14 - D-PHY mode: Header error detected and corrected on virtual channel 14. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT (15U) /*! err_ecc_corrected_vc15 - D-PHY mode: Header error detected and corrected on virtual channel 15. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_MASK) /*! @} */ /*! @name INT_MSK_ECC_CORRECTED - Mask for interruption caused by Header single bit errors. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT (0U) /*! err_ecc_corrected_vc0 - Mask for err_ecc_corrected_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT (1U) /*! err_ecc_corrected_vc1 - Mask for err_ecc_corrected_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT (2U) /*! err_ecc_corrected_vc2 - Mask for err_ecc_corrected_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT (3U) /*! err_ecc_corrected_vc3 - Mask for err_ecc_corrected_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT (4U) /*! err_ecc_corrected_vc4 - Mask for err_ecc_corrected_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT (5U) /*! err_ecc_corrected_vc5 - Mask for err_ecc_corrected_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT (6U) /*! err_ecc_corrected_vc6 - Mask for err_ecc_corrected_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT (7U) /*! err_ecc_corrected_vc7 - Mask for err_ecc_corrected_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT (8U) /*! err_ecc_corrected_vc8 - Mask for err_ecc_corrected_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT (9U) /*! err_ecc_corrected_vc9 - Mask for err_ecc_corrected_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT (10U) /*! err_ecc_corrected_vc10 - Mask for err_ecc_corrected_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT (11U) /*! err_ecc_corrected_vc11 - Mask for err_ecc_corrected_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT (12U) /*! err_ecc_corrected_vc12 - Mask for err_ecc_corrected_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT (13U) /*! err_ecc_corrected_vc13 - Mask for err_ecc_corrected_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT (14U) /*! err_ecc_corrected_vc14 - Mask for err_ecc_corrected_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT (15U) /*! err_ecc_corrected_vc15 - Mask for err_ecc_corrected_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_MASK) /*! @} */ /*! @name INT_FORCE_ECC_CORRECTED - Force for interruption caused by Header single bit errors. */ /*! @{ */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_MASK (0x1U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT (0U) /*! err_ecc_corrected_vc0 - Force err_ecc_corrected_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_MASK (0x2U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT (1U) /*! err_ecc_corrected_vc1 - Force err_ecc_corrected_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_MASK (0x4U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT (2U) /*! err_ecc_corrected_vc2 - Force err_ecc_corrected_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_MASK (0x8U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT (3U) /*! err_ecc_corrected_vc3 - Force err_ecc_corrected_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_MASK (0x10U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT (4U) /*! err_ecc_corrected_vc4 - Force err_ecc_corrected_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_MASK (0x20U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT (5U) /*! err_ecc_corrected_vc5 - Force err_ecc_corrected_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_MASK (0x40U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT (6U) /*! err_ecc_corrected_vc6 - Force err_ecc_corrected_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_MASK (0x80U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT (7U) /*! err_ecc_corrected_vc7 - Force err_ecc_corrected_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_MASK (0x100U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT (8U) /*! err_ecc_corrected_vc8 - Force err_ecc_corrected_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_MASK (0x200U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT (9U) /*! err_ecc_corrected_vc9 - Force err_ecc_corrected_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_MASK (0x400U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT (10U) /*! err_ecc_corrected_vc10 - Force err_ecc_corrected_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_MASK (0x800U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT (11U) /*! err_ecc_corrected_vc11 - Force err_ecc_corrected_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_MASK (0x1000U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT (12U) /*! err_ecc_corrected_vc12 - Force err_ecc_corrected_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_MASK (0x2000U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT (13U) /*! err_ecc_corrected_vc13 - Force err_ecc_corrected_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_MASK (0x4000U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT (14U) /*! err_ecc_corrected_vc14 - Force err_ecc_corrected_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_MASK) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_MASK (0x8000U) #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT (15U) /*! err_ecc_corrected_vc15 - Force err_ecc_corrected_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT)) & CAMERA_MIPI_CSI2_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_MASK) /*! @} */ /*! @name SCRAMBLING - Data De-Scrambling. */ /*! @{ */ #define CAMERA_MIPI_CSI2_SCRAMBLING_scramble_enable_MASK (0x1U) #define CAMERA_MIPI_CSI2_SCRAMBLING_scramble_enable_SHIFT (0U) /*! scramble_enable - Enables data de-scrambling on the controller side. * 0b0..Disable data de-scrambling. * 0b1..Enable data de-scrambling. */ #define CAMERA_MIPI_CSI2_SCRAMBLING_scramble_enable(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_SCRAMBLING_scramble_enable_SHIFT)) & CAMERA_MIPI_CSI2_SCRAMBLING_scramble_enable_MASK) /*! @} */ /*! @name SCRAMBLING_SEED1 - De-scrambler seed for lane1. */ /*! @{ */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED1_scramble_seed_lane1_MASK (0xFFFFU) #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED1_scramble_seed_lane1_SHIFT (0U) /*! scramble_seed_lane1 - Seed used by De-scrambler block for lane 1 */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED1_scramble_seed_lane1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_SCRAMBLING_SEED1_scramble_seed_lane1_SHIFT)) & CAMERA_MIPI_CSI2_SCRAMBLING_SEED1_scramble_seed_lane1_MASK) /*! @} */ /*! @name SCRAMBLING_SEED2 - De-scrambler seed for lane2. */ /*! @{ */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED2_scramble_seed_lane2_MASK (0xFFFFU) #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED2_scramble_seed_lane2_SHIFT (0U) /*! scramble_seed_lane2 - Seed used by De-scrambler block for lane 2 */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED2_scramble_seed_lane2(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_SCRAMBLING_SEED2_scramble_seed_lane2_SHIFT)) & CAMERA_MIPI_CSI2_SCRAMBLING_SEED2_scramble_seed_lane2_MASK) /*! @} */ /*! @name SCRAMBLING_SEED3 - De-scrambler seed for lane3. */ /*! @{ */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED3_scramble_seed_lane3_MASK (0xFFFFU) #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED3_scramble_seed_lane3_SHIFT (0U) /*! scramble_seed_lane3 - Seed used by De-scrambler block for lane 3 */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED3_scramble_seed_lane3(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_SCRAMBLING_SEED3_scramble_seed_lane3_SHIFT)) & CAMERA_MIPI_CSI2_SCRAMBLING_SEED3_scramble_seed_lane3_MASK) /*! @} */ /*! @name SCRAMBLING_SEED4 - De-scrambler seed for lane4. */ /*! @{ */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED4_scramble_seed_lane4_MASK (0xFFFFU) #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED4_scramble_seed_lane4_SHIFT (0U) /*! scramble_seed_lane4 - Seed used by De-scrambler block for lane 4 */ #define CAMERA_MIPI_CSI2_SCRAMBLING_SEED4_scramble_seed_lane4(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_MIPI_CSI2_SCRAMBLING_SEED4_scramble_seed_lane4_SHIFT)) & CAMERA_MIPI_CSI2_SCRAMBLING_SEED4_scramble_seed_lane4_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_MIPI_CSI2_Register_Masks */ /* CAMERA_MIPI_CSI2 - Peripheral instance base addresses */ /** Peripheral MIPI_CSI2 base address */ #define MIPI_CSI2_BASE (0x4AD30000u) /** Peripheral MIPI_CSI2 base pointer */ #define MIPI_CSI2 ((CAMERA_MIPI_CSI2_Type *)MIPI_CSI2_BASE) /** Array initializer of CAMERA_MIPI_CSI2 peripheral base addresses */ #define CAMERA_MIPI_CSI2_BASE_ADDRS { MIPI_CSI2_BASE } /** Array initializer of CAMERA_MIPI_CSI2 peripheral base pointers */ #define CAMERA_MIPI_CSI2_BASE_PTRS { MIPI_CSI2 } /*! * @} */ /* end of group CAMERA_MIPI_CSI2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_OCRAM_MECC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_OCRAM_MECC_Peripheral_Access_Layer CAMERA_OCRAM_MECC Peripheral Access Layer * @{ */ /** CAMERA_OCRAM_MECC - Register Layout Typedef */ typedef struct { __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ __IO uint32_t RAMIAS; /**< RAM Initialization Address Start, offset: 0x4 */ __IO uint32_t RAMIAE; /**< RAM Initialization Address End, offset: 0x8 */ __IO uint32_t RAMSR; /**< RAM Status, offset: 0xC */ __I uint32_t RAMMEMA; /**< RAM ECC Address, offset: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t RAMSYSA; /**< RAM System Address, offset: 0x18 */ __IO uint32_t RAMECCNT; /**< RAM Correctable Error Count, offset: 0x1C */ __IO uint32_t RAMEID0; /**< RAM Error Injection Data 0, offset: 0x20 */ __IO uint32_t RAMEID1; /**< RAM Error Injection Data 1, offset: 0x24 */ __IO uint32_t RAMEIDC; /**< RAM Error Injection Data Control, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t RAMEIA; /**< RAM Error Injection Base Address, offset: 0x30 */ __IO uint32_t RAMEIAM; /**< RAM Error Injection Address Mask, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t RAMMAXA; /**< RAM Maximum-Value Address, offset: 0x40 */ uint8_t RESERVED_3[60]; __IO uint32_t RAMCR2; /**< RAM Control 2, offset: 0x80 */ } CAMERA_OCRAM_MECC_Type; /* ---------------------------------------------------------------------------- -- CAMERA_OCRAM_MECC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_OCRAM_MECC_Register_Masks CAMERA_OCRAM_MECC Register Masks * @{ */ /*! @name RAMCR - RAM Control */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMCR_INIT_MASK (0x1U) #define CAMERA_OCRAM_MECC_RAMCR_INIT_SHIFT (0U) /*! INIT - Initialization Request * 0b0..Not requested * 0b1..Requested */ #define CAMERA_OCRAM_MECC_RAMCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMCR_INIT_SHIFT)) & CAMERA_OCRAM_MECC_RAMCR_INIT_MASK) #define CAMERA_OCRAM_MECC_RAMCR_IWS_MASK (0x6U) #define CAMERA_OCRAM_MECC_RAMCR_IWS_SHIFT (1U) /*! IWS - Initialization Wait States * 0b00..Zero * 0b01..One * 0b10..Two * 0b11..Three */ #define CAMERA_OCRAM_MECC_RAMCR_IWS(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMCR_IWS_SHIFT)) & CAMERA_OCRAM_MECC_RAMCR_IWS_MASK) #define CAMERA_OCRAM_MECC_RAMCR_INIT_SYSA_MASK (0x100U) #define CAMERA_OCRAM_MECC_RAMCR_INIT_SYSA_SHIFT (8U) /*! INIT_SYSA - Initialize With System Address * 0b0..Local * 0b1..System */ #define CAMERA_OCRAM_MECC_RAMCR_INIT_SYSA(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMCR_INIT_SYSA_SHIFT)) & CAMERA_OCRAM_MECC_RAMCR_INIT_SYSA_MASK) /*! @} */ /*! @name RAMIAS - RAM Initialization Address Start */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMIAS_IAS_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMIAS_IAS_SHIFT (0U) /*! IAS - Initialization Address Start */ #define CAMERA_OCRAM_MECC_RAMIAS_IAS(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMIAS_IAS_SHIFT)) & CAMERA_OCRAM_MECC_RAMIAS_IAS_MASK) /*! @} */ /*! @name RAMIAE - RAM Initialization Address End */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMIAE_IAE_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMIAE_IAE_SHIFT (0U) /*! IAE - Initialization Address End */ #define CAMERA_OCRAM_MECC_RAMIAE_IAE(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMIAE_IAE_SHIFT)) & CAMERA_OCRAM_MECC_RAMIAE_IAE_MASK) /*! @} */ /*! @name RAMSR - RAM Status */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMSR_IDONE_MASK (0x1U) #define CAMERA_OCRAM_MECC_RAMSR_IDONE_SHIFT (0U) /*! IDONE - Initialization Done * 0b0..An initialization was not requested, is in progress, or did not complete * 0b1..An initialization completed successfully */ #define CAMERA_OCRAM_MECC_RAMSR_IDONE(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_IDONE_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_IDONE_MASK) #define CAMERA_OCRAM_MECC_RAMSR_BUSERR_MASK (0x2U) #define CAMERA_OCRAM_MECC_RAMSR_BUSERR_SHIFT (1U) /*! BUSERR - Bus Error * 0b0..No error occurred since the last time this field was cleared * 0b1..An error occurred */ #define CAMERA_OCRAM_MECC_RAMSR_BUSERR(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_BUSERR_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_BUSERR_MASK) #define CAMERA_OCRAM_MECC_RAMSR_IPEND_MASK (0x4U) #define CAMERA_OCRAM_MECC_RAMSR_IPEND_SHIFT (2U) /*! IPEND - Initialization Pending * 0b0..Not in progress * 0b1..In progress */ #define CAMERA_OCRAM_MECC_RAMSR_IPEND(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_IPEND_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_IPEND_MASK) #define CAMERA_OCRAM_MECC_RAMSR_AVALID_MASK (0x8U) #define CAMERA_OCRAM_MECC_RAMSR_AVALID_SHIFT (3U) /*! AVALID - Addresses Valid * 0b0..Addresses do not correspond to an event * 0b1..Addresses correspond to an event */ #define CAMERA_OCRAM_MECC_RAMSR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_AVALID_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_AVALID_MASK) #define CAMERA_OCRAM_MECC_RAMSR_AERR_MASK (0x20U) #define CAMERA_OCRAM_MECC_RAMSR_AERR_SHIFT (5U) /*! AERR - ECC Address Error * 0b0..No error occurred * 0b1..An error occurred */ #define CAMERA_OCRAM_MECC_RAMSR_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_AERR_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_AERR_MASK) #define CAMERA_OCRAM_MECC_RAMSR_MLTERR_MASK (0x40U) #define CAMERA_OCRAM_MECC_RAMSR_MLTERR_SHIFT (6U) /*! MLTERR - ECC Multi-Bit Error * 0b0..No error occurred * 0b1..An error occurred */ #define CAMERA_OCRAM_MECC_RAMSR_MLTERR(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_MLTERR_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_MLTERR_MASK) #define CAMERA_OCRAM_MECC_RAMSR_SGLERR_MASK (0x80U) #define CAMERA_OCRAM_MECC_RAMSR_SGLERR_SHIFT (7U) /*! SGLERR - ECC Single-Bit Error * 0b0..No error occurred * 0b1..An error occurred */ #define CAMERA_OCRAM_MECC_RAMSR_SGLERR(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_SGLERR_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_SGLERR_MASK) #define CAMERA_OCRAM_MECC_RAMSR_SYND_MASK (0xFF00U) #define CAMERA_OCRAM_MECC_RAMSR_SYND_SHIFT (8U) /*! SYND - ECC Syndrome Value */ #define CAMERA_OCRAM_MECC_RAMSR_SYND(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_SYND_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_SYND_MASK) #define CAMERA_OCRAM_MECC_RAMSR_EINFO_MASK (0xFF0000U) #define CAMERA_OCRAM_MECC_RAMSR_EINFO_SHIFT (16U) /*! EINFO - Event Information */ #define CAMERA_OCRAM_MECC_RAMSR_EINFO(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSR_EINFO_SHIFT)) & CAMERA_OCRAM_MECC_RAMSR_EINFO_MASK) /*! @} */ /*! @name RAMMEMA - RAM ECC Address */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMMEMA_MEMA_MASK (0x1FFFFU) #define CAMERA_OCRAM_MECC_RAMMEMA_MEMA_SHIFT (0U) /*! MEMA - RAM Bank Address */ #define CAMERA_OCRAM_MECC_RAMMEMA_MEMA(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMMEMA_MEMA_SHIFT)) & CAMERA_OCRAM_MECC_RAMMEMA_MEMA_MASK) #define CAMERA_OCRAM_MECC_RAMMEMA_BANK_MASK (0x1F00000U) #define CAMERA_OCRAM_MECC_RAMMEMA_BANK_SHIFT (20U) /*! BANK - RAM Bank ID */ #define CAMERA_OCRAM_MECC_RAMMEMA_BANK(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMMEMA_BANK_SHIFT)) & CAMERA_OCRAM_MECC_RAMMEMA_BANK_MASK) /*! @} */ /*! @name RAMSYSA - RAM System Address */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMSYSA_SYSA_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMSYSA_SYSA_SHIFT (0U) /*! SYSA - System Address */ #define CAMERA_OCRAM_MECC_RAMSYSA_SYSA(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMSYSA_SYSA_SHIFT)) & CAMERA_OCRAM_MECC_RAMSYSA_SYSA_MASK) /*! @} */ /*! @name RAMECCNT - RAM Correctable Error Count */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMECCNT_ECCNT_MASK (0xFFU) #define CAMERA_OCRAM_MECC_RAMECCNT_ECCNT_SHIFT (0U) /*! ECCNT - ECC Correctable Error Count */ #define CAMERA_OCRAM_MECC_RAMECCNT_ECCNT(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMECCNT_ECCNT_SHIFT)) & CAMERA_OCRAM_MECC_RAMECCNT_ECCNT_MASK) /*! @} */ /*! @name RAMEID0 - RAM Error Injection Data 0 */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMEID0_EID_W0_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMEID0_EID_W0_SHIFT (0U) /*! EID_W0 - Error Injection Data Word 0 */ #define CAMERA_OCRAM_MECC_RAMEID0_EID_W0(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEID0_EID_W0_SHIFT)) & CAMERA_OCRAM_MECC_RAMEID0_EID_W0_MASK) /*! @} */ /*! @name RAMEID1 - RAM Error Injection Data 1 */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMEID1_EID_W1_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMEID1_EID_W1_SHIFT (0U) /*! EID_W1 - Error Injection Data Word 1 */ #define CAMERA_OCRAM_MECC_RAMEID1_EID_W1(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEID1_EID_W1_SHIFT)) & CAMERA_OCRAM_MECC_RAMEID1_EID_W1_MASK) /*! @} */ /*! @name RAMEIDC - RAM Error Injection Data Control */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMEIDC_EID_CKB_MASK (0xFFU) #define CAMERA_OCRAM_MECC_RAMEIDC_EID_CKB_SHIFT (0U) /*! EID_CKB - Error Injection Data Checkbits */ #define CAMERA_OCRAM_MECC_RAMEIDC_EID_CKB(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEIDC_EID_CKB_SHIFT)) & CAMERA_OCRAM_MECC_RAMEIDC_EID_CKB_MASK) #define CAMERA_OCRAM_MECC_RAMEIDC_EIP_EN_MASK (0x1000000U) #define CAMERA_OCRAM_MECC_RAMEIDC_EIP_EN_SHIFT (24U) /*! EIP_EN - Error Injection Into Pipeline Enable * 0b0..No error injected * 0b1..Error injected */ #define CAMERA_OCRAM_MECC_RAMEIDC_EIP_EN(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEIDC_EIP_EN_SHIFT)) & CAMERA_OCRAM_MECC_RAMEIDC_EIP_EN_MASK) #define CAMERA_OCRAM_MECC_RAMEIDC_EIA_EN_MASK (0x40000000U) #define CAMERA_OCRAM_MECC_RAMEIDC_EIA_EN_SHIFT (30U) /*! EIA_EN - Error Injection Address Enable * 0b0..Ignore RAMEIA and RAMEIAM * 0b1..Enable RAMEIA and RAMEIAM */ #define CAMERA_OCRAM_MECC_RAMEIDC_EIA_EN(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEIDC_EIA_EN_SHIFT)) & CAMERA_OCRAM_MECC_RAMEIDC_EIA_EN_MASK) #define CAMERA_OCRAM_MECC_RAMEIDC_EID_EN_MASK (0x80000000U) #define CAMERA_OCRAM_MECC_RAMEIDC_EID_EN_SHIFT (31U) /*! EID_EN - Error Injection Data Enable * 0b0..No injection * 0b1..Local injection */ #define CAMERA_OCRAM_MECC_RAMEIDC_EID_EN(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEIDC_EID_EN_SHIFT)) & CAMERA_OCRAM_MECC_RAMEIDC_EID_EN_MASK) /*! @} */ /*! @name RAMEIA - RAM Error Injection Base Address */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMEIA_EIA_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMEIA_EIA_SHIFT (0U) /*! EIA - Error Injection Base Address */ #define CAMERA_OCRAM_MECC_RAMEIA_EIA(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEIA_EIA_SHIFT)) & CAMERA_OCRAM_MECC_RAMEIA_EIA_MASK) /*! @} */ /*! @name RAMEIAM - RAM Error Injection Address Mask */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMEIAM_EIAM_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMEIAM_EIAM_SHIFT (0U) /*! EIAM - Error Injection Address Mask */ #define CAMERA_OCRAM_MECC_RAMEIAM_EIAM(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMEIAM_EIAM_SHIFT)) & CAMERA_OCRAM_MECC_RAMEIAM_EIAM_MASK) /*! @} */ /*! @name RAMMAXA - RAM Maximum-Value Address */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMMAXA_MAXA_MASK (0xFFFFFFFFU) #define CAMERA_OCRAM_MECC_RAMMAXA_MAXA_SHIFT (0U) /*! MAXA - Maximum Address */ #define CAMERA_OCRAM_MECC_RAMMAXA_MAXA(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMMAXA_MAXA_SHIFT)) & CAMERA_OCRAM_MECC_RAMMAXA_MAXA_MASK) /*! @} */ /*! @name RAMCR2 - RAM Control 2 */ /*! @{ */ #define CAMERA_OCRAM_MECC_RAMCR2_WBUF_MASK (0x6U) #define CAMERA_OCRAM_MECC_RAMCR2_WBUF_SHIFT (1U) /*! WBUF - Write Buffer Control * 0b00..Disable write buffer for all write transactions * 0b01..Enable write buffer for write transactions that come with bufferable bus attribute * 0b10..Enable write buffer for write transactions that are not exclusive writes * 0b11..Reserved */ #define CAMERA_OCRAM_MECC_RAMCR2_WBUF(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_OCRAM_MECC_RAMCR2_WBUF_SHIFT)) & CAMERA_OCRAM_MECC_RAMCR2_WBUF_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_OCRAM_MECC_Register_Masks */ /* CAMERA_OCRAM_MECC - Peripheral instance base addresses */ /** Peripheral CAMERA__OCRAM_MECC base address */ #define CAMERA__OCRAM_MECC_BASE (0x4ADD0000u) /** Peripheral CAMERA__OCRAM_MECC base pointer */ #define CAMERA__OCRAM_MECC ((CAMERA_OCRAM_MECC_Type *)CAMERA__OCRAM_MECC_BASE) /** Array initializer of CAMERA_OCRAM_MECC peripheral base addresses */ #define CAMERA_OCRAM_MECC_BASE_ADDRS { CAMERA__OCRAM_MECC_BASE } /** Array initializer of CAMERA_OCRAM_MECC peripheral base pointers */ #define CAMERA_OCRAM_MECC_BASE_PTRS { CAMERA__OCRAM_MECC } /*! * @} */ /* end of group CAMERA_OCRAM_MECC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAMERA_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_TCU_Peripheral_Access_Layer CAMERA_TCU Peripheral Access Layer * @{ */ /** CAMERA_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[1036]; __IO uint32_t TCU_PIXEL_SLV_TEST_MODE; /**< PIXEL LINK slave test mode, offset: 0x820 */ __IO uint32_t TCU_PIXEL_SLV_TEST_INPUT_; /**< PIXEL LINK slave test input, offset: 0x824 */ __I uint32_t TCU_PIXEL_SLV_TEST_ERROR_BIT; /**< PIXEL LINK slave test error bits, offset: 0x828 */ uint8_t RESERVED_3[20]; __IO uint32_t TCU_DFT_PHY_BURNIN; /**< Controls PHY burnin test, offset: 0x840 */ uint8_t RESERVED_4[956]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_5[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } CAMERA_TCU_Type; /* ---------------------------------------------------------------------------- -- CAMERA_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAMERA_TCU_Register_Masks CAMERA_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & CAMERA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PIXEL_SLV_TEST_MODE - PIXEL LINK slave test mode */ /*! @{ */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_mode_MASK (0x1U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_mode_SHIFT (0U) /*! pixel_slv0_test_mode - pixel loop test production mode */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_mode(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_mode_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_mode_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_done_MASK (0x2U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_done_SHIFT (1U) /*! pixel_slv0_test_done - pixel loop test done indication */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_done(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_done_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_done_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_pass_fail_b_MASK (0x4U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_pass_fail_b_SHIFT (2U) /*! pixel_slv0_test_pass_fail_b - pixel loop test pass/fail indication */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_pass_fail_b(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_pass_fail_b_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv0_test_pass_fail_b_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_mode_MASK (0x8U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_mode_SHIFT (3U) /*! pixel_slv1_test_mode - pixel loop test production mode */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_mode(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_mode_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_mode_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_done_MASK (0x10U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_done_SHIFT (4U) /*! pixel_slv1_test_done - pixel loop test done indication */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_done(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_done_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_done_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_pass_fail_b_MASK (0x20U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_pass_fail_b_SHIFT (5U) /*! pixel_slv1_test_pass_fail_b - pixel loop test pass/fail indication */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_pass_fail_b(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_pass_fail_b_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv1_test_pass_fail_b_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_mode_MASK (0x40U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_mode_SHIFT (6U) /*! pixel_slv2_test_mode - pixel_slv2_test_mode */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_mode(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_mode_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_mode_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_done_MASK (0x80U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_done_SHIFT (7U) /*! pixel_slv2_test_done - pixel_slv2_test_done */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_done(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_done_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_done_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_pass_fail_b_MASK (0x100U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_pass_fail_b_SHIFT (8U) /*! pixel_slv2_test_pass_fail_b - pixel_slv2_test_pass_fail_b */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_pass_fail_b(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_pass_fail_b_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv2_test_pass_fail_b_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_mode_MASK (0x200U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_mode_SHIFT (9U) /*! pixel_slv3_test_mode - pixel_slv3_test_mode */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_mode(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_mode_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_mode_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_done_MASK (0x400U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_done_SHIFT (10U) /*! pixel_slv3_test_done - pixel_slv3_test_done */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_done(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_done_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_done_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_pass_fail_b_MASK (0x800U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_pass_fail_b_SHIFT (11U) /*! pixel_slv3_test_pass_fail_b - pixel_slv3_test_pass_fail_b */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_pass_fail_b(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_pass_fail_b_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv3_test_pass_fail_b_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_start_MASK (0x1000U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_start_SHIFT (12U) /*! pixel_slv_test_start - PIXEL SLV TEST START */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_start(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_start_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_start_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_load_MASK (0x2000U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_load_SHIFT (13U) /*! pixel_slv_test_load - PIXEL SLV TEST LOAD */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_load(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_load_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_load_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_error_valid_MASK (0x4000U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_error_valid_SHIFT (14U) /*! pixel_slv_test_error_valid - pixel loop test error valid */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_error_valid(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_error_valid_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_error_valid_MASK) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_unpause_MASK (0x8000U) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_unpause_SHIFT (15U) /*! pixel_slv_test_unpause - To drive pixel_slv_test_unpause signal */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_unpause(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_unpause_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_MODE_pixel_slv_test_unpause_MASK) /*! @} */ /*! @name TCU_PIXEL_SLV_TEST_INPUT_ - PIXEL LINK slave test input */ /*! @{ */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_INPUT__pixel_slv_test_input_MASK (0xFFFFFFFFU) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_INPUT__pixel_slv_test_input_SHIFT (0U) /*! pixel_slv_test_input - pixel link test inputs */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_INPUT__pixel_slv_test_input(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_INPUT__pixel_slv_test_input_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_INPUT__pixel_slv_test_input_MASK) /*! @} */ /*! @name TCU_PIXEL_SLV_TEST_ERROR_BIT - PIXEL LINK slave test error bits */ /*! @{ */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_ERROR_BIT_pixel_slv_test_error_bit_MASK (0xFFFFFFFFU) #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_ERROR_BIT_pixel_slv_test_error_bit_SHIFT (0U) /*! pixel_slv_test_error_bit - test error bits observation */ #define CAMERA_TCU_TCU_PIXEL_SLV_TEST_ERROR_BIT_pixel_slv_test_error_bit(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PIXEL_SLV_TEST_ERROR_BIT_pixel_slv_test_error_bit_SHIFT)) & CAMERA_TCU_TCU_PIXEL_SLV_TEST_ERROR_BIT_pixel_slv_test_error_bit_MASK) /*! @} */ /*! @name TCU_DFT_PHY_BURNIN - Controls PHY burnin test */ /*! @{ */ #define CAMERA_TCU_TCU_DFT_PHY_BURNIN_tcu_crr_dft_phy_bi_mon_en_MASK (0x7U) #define CAMERA_TCU_TCU_DFT_PHY_BURNIN_tcu_crr_dft_phy_bi_mon_en_SHIFT (0U) /*! tcu_crr_dft_phy_bi_mon_en - Control PHY mux for phy burnin test on the csi_complex */ #define CAMERA_TCU_TCU_DFT_PHY_BURNIN_tcu_crr_dft_phy_bi_mon_en(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_DFT_PHY_BURNIN_tcu_crr_dft_phy_bi_mon_en_SHIFT)) & CAMERA_TCU_TCU_DFT_PHY_BURNIN_tcu_crr_dft_phy_bi_mon_en_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & CAMERA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & CAMERA_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & CAMERA_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & CAMERA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & CAMERA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define CAMERA_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & CAMERA_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define CAMERA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define CAMERA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define CAMERA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & CAMERA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define CAMERA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x1EU) #define CAMERA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define CAMERA_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << CAMERA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & CAMERA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group CAMERA_TCU_Register_Masks */ /* CAMERA_TCU - Peripheral instance base addresses */ /** Peripheral CAMERA__TCU base address */ #define CAMERA__TCU_BASE (0x4AC00000u) /** Peripheral CAMERA__TCU base pointer */ #define CAMERA__TCU ((CAMERA_TCU_Type *)CAMERA__TCU_BASE) /** Array initializer of CAMERA_TCU peripheral base addresses */ #define CAMERA_TCU_BASE_ADDRS { CAMERA__TCU_BASE } /** Array initializer of CAMERA_TCU peripheral base pointers */ #define CAMERA_TCU_BASE_PTRS { CAMERA__TCU } /*! * @} */ /* end of group CAMERA_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAN Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer * @{ */ /** CAN - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ __IO uint32_t IMASK2; /**< Interrupt Masks 2, offset: 0x24 */ __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ __IO uint32_t IFLAG2; /**< Interrupt Flags 2, offset: 0x2C */ __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ uint8_t RESERVED_1[8]; __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ uint8_t RESERVED_2[24]; __IO uint32_t IMASK3; /**< Interrupt Masks 3, offset: 0x6C */ uint8_t RESERVED_3[4]; __IO uint32_t IFLAG3; /**< Interrupt Flags 3, offset: 0x74 */ uint8_t RESERVED_4[8]; union { /* offset: 0x80 */ struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 95 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 95 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 95 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ } MB_8B[96]; struct { /* offset: 0x80, array step: 0x18 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 62 CS Register, array offset: 0x80, array step: 0x18 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 62 ID Register, array offset: 0x84, array step: 0x18 */ __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 62 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ } MB_16B[63]; struct { /* offset: 0x80, array step: 0x28 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 35 CS Register, array offset: 0x80, array step: 0x28 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 35 ID Register, array offset: 0x84, array step: 0x28 */ __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 35 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ } MB_32B[36]; struct { /* offset: 0x80, array step: 0x48 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x48 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x48 */ __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 20 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ } MB_64B[21]; struct { /* offset: 0x80, array step: 0x10 */ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 95 CS Register, array offset: 0x80, array step: 0x10 */ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 95 ID Register, array offset: 0x84, array step: 0x10 */ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 95 WORD0 Register, array offset: 0x88, array step: 0x10 */ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 95 WORD1 Register, array offset: 0x8C, array step: 0x10 */ } MB[96]; }; uint8_t RESERVED_5[512]; __IO uint32_t RXIMR[96]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_6[224]; __IO uint32_t MECR; /**< Memory Error Control, offset: 0xAE0 */ __IO uint32_t ERRIAR; /**< Error Injection Address, offset: 0xAE4 */ __IO uint32_t ERRIDPR; /**< Error Injection Data Pattern, offset: 0xAE8 */ __IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern, offset: 0xAEC */ __I uint32_t RERRAR; /**< Error Report Address, offset: 0xAF0 */ __I uint32_t RERRDR; /**< Error Report Data, offset: 0xAF4 */ __I uint32_t RERRSYNR; /**< Error Report Syndrome, offset: 0xAF8 */ __IO uint32_t ERRSR; /**< Error Status, offset: 0xAFC */ uint8_t RESERVED_7[240]; __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ uint8_t RESERVED_8[24]; __IO uint32_t HR_TIME_STAMP[96]; /**< High-Resolution Timestamp, array offset: 0xC30, array step: 0x4 */ uint8_t RESERVED_9[8784]; __IO uint32_t ERFFEL[128]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ } CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /*! @name MCR - Module Configuration */ /*! @{ */ #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) /*! MAXMB - Number of the Last Message Buffer */ #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) /*! IDAM - ID Acceptance Mode * 0b00..Format A: One full ID (standard and extended) per ID filter table element. * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. * 0b11..Format D: All frames rejected. */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) /*! FDEN - CAN FD Operation Enable * 0b1..Enable * 0b0..Disable */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable * 0b0..Disabled * 0b1..Enabled */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) #define CAN_MCR_DMA_MASK (0x8000U) #define CAN_MCR_DMA_SHIFT (15U) /*! DMA - DMA Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) /*! IRMQ - Individual RX Masking and Queue Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) /*! SRXDIS - Self-Reception Disable * 0b0..Enable * 0b1..Disable */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) #define CAN_MCR_DOZE_MASK (0x40000U) #define CAN_MCR_DOZE_SHIFT (18U) /*! DOZE - Doze Mode Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) /*! WAKSRC - Wake-Up Source * 0b0..No filter applied * 0b1..Filter applied */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge * 0b0..Not in a low-power mode * 0b1..In a low-power mode */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) /*! SLFWAK - Self Wake-up * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) /*! SUPV - Supervisor Mode * 0b0..User mode * 0b1..Supervisor mode */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge * 0b0..Not in Freeze mode, prescaler running. * 0b1..In Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset * 0b0..No reset * 0b1..Soft reset affects reset registers */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) /*! WAKMSK - Wake-up Interrupt Mask * 0b0..Disabled * 0b1..Enabled */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. * 0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN * 0b0..No request * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) /*! RFEN - Legacy RX FIFO Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable * 0b0..Enable * 0b1..Disable */ #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) /*! @} */ /*! @name CTRL1 - Control 1 */ /*! @{ */ #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) /*! PROPSEG - Propagation Segment */ #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) /*! LOM - Listen-Only Mode * 0b0..Listen-Only mode is deactivated. * 0b1..FlexCAN module operates in Listen-Only mode. */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) /*! LBUF - Lowest Buffer Transmitted First * 0b0..Buffer with highest priority is transmitted first. * 0b1..Lowest number buffer is transmitted first. */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery * 0b0..Enabled * 0b1..Disabled */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling * 0b0..One sample is used to determine the bit value. * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two * preceding samples. A majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) /*! RWRNMSK - RX Warning Interrupt Mask * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) /*! TWRNMSK - TX Warning Interrupt Mask * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) /*! LPB - Loopback Mode * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) #define CAN_CTRL1_CLKSRC_MASK (0x2000U) #define CAN_CTRL1_CLKSRC_SHIFT (13U) /*! CLKSRC - CAN Engine Clock Source * 0b0..Peripheral clock * 0b1..Bus clock */ #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask * 0b0..Interrupt disabled * 0b1..Interrupt enabled */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) /*! PSEG2 - Phase Segment 2 */ #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) #define CAN_CTRL1_PSEG1_MASK (0x380000U) #define CAN_CTRL1_PSEG1_SHIFT (19U) /*! PSEG1 - Phase Segment 1 */ #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) #define CAN_CTRL1_RJW_MASK (0xC00000U) #define CAN_CTRL1_RJW_SHIFT (22U) /*! RJW - Resync Jump Width */ #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) /*! PRESDIV - Prescaler Division Factor */ #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) /*! @} */ /*! @name TIMER - Free-Running Timer */ /*! @{ */ #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) /*! TIMER - Timer Value */ #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) /*! @} */ /*! @name RXMGMASK - RX Message Buffers Global Mask */ /*! @{ */ #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) /*! MG - Global Mask for RX Message Buffers */ #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) /*! @} */ /*! @name RX14MASK - Receive 14 Mask */ /*! @{ */ #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) /*! RX14M - RX Buffer 14 Mask Bits */ #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) /*! @} */ /*! @name RX15MASK - Receive 15 Mask */ /*! @{ */ #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) /*! RX15M - RX Buffer 15 Mask Bits */ #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) /*! @} */ /*! @name ECR - Error Counter */ /*! @{ */ #define CAN_ECR_TXERRCNT_MASK (0xFFU) #define CAN_ECR_TXERRCNT_SHIFT (0U) /*! TXERRCNT - Transmit Error Counter */ #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) #define CAN_ECR_RXERRCNT_MASK (0xFF00U) #define CAN_ECR_RXERRCNT_SHIFT (8U) /*! RXERRCNT - Receive Error Counter */ #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) /*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) /*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) /*! @} */ /*! @name ESR1 - Error and Status 1 */ /*! @{ */ #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) /*! WAKINT - Wake-up Interrupt Flag * 0b0..No such occurrence. * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) /*! ERRINT - Error Interrupt Flag * 0b0..No such occurrence. * 0b1..Indicates setting of any error flag in the Error and Status register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) /*! BOFFINT - Bus Off Interrupt Flag * 0b0..No such occurrence. * 0b1..FlexCAN module entered Bus Off state. */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) /*! RX - FlexCAN in Reception Flag * 0b0..Not receiving * 0b1..Receiving */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) /*! FLTCONF - Fault Confinement State * 0b00..Error Active * 0b01..Error Passive * 0b1x..Bus Off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission * 0b0..Not transmitting * 0b1..Transmitting */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) /*! IDLE - Idle * 0b0..Not IDLE * 0b1..IDLE */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) /*! RXWRN - RX Error Warning Flag * 0b0..No such occurrence. * 0b1..RXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) /*! TXWRN - TX Error Warning Flag * 0b0..No such occurrence. * 0b1..TXERRCNT is 96 or greater. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) /*! STFERR - Stuffing Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) /*! FRMERR - Form Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) /*! CRCERR - Cyclic Redundancy Check Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) /*! ACKERR - Acknowledge Error Flag * 0b0..No error * 0b1..Error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) /*! BIT0ERR - Bit0 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) /*! BIT1ERR - Bit1 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) /*! RWRNINT - RX Warning Interrupt Flag * 0b0..No such occurrence * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) /*! TWRNINT - TX Warning Interrupt Flag * 0b0..No such occurrence * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) /*! SYNCH - CAN Synchronization Status Flag * 0b0..Not synchronized * 0b1..Synchronized */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) /*! BOFFDONEINT - Bus Off Done Interrupt Flag * 0b0..No such occurrence * 0b1..FlexCAN module has completed Bus Off process. */ #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) /*! ERRINT_FAST - Fast Error Interrupt Flag * 0b0..No such occurrence. * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. */ #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) #define CAN_ESR1_ERROVR_MASK (0x200000U) #define CAN_ESR1_ERROVR_SHIFT (21U) /*! ERROVR - Error Overrun Flag * 0b0..No overrun * 0b1..Overrun */ #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) /*! STFERR_FAST - Fast Stuffing Error Flag * 0b0..No such occurrence. * 0b1..A stuffing error occurred since last read of this register. */ #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) /*! FRMERR_FAST - Fast Form Error Flag * 0b0..No such occurrence. * 0b1..A form error occurred since last read of this register. */ #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) /*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag * 0b0..No such occurrence. * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) /*! BIT0ERR_FAST - Fast Bit0 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit transmitted as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) /*! BIT1ERR_FAST - Fast Bit1 Error Flag * 0b0..No such occurrence. * 0b1..At least one bit transmitted as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) /*! @} */ /*! @name IMASK2 - Interrupt Masks 2 */ /*! @{ */ #define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) #define CAN_IMASK2_BUF63TO32M_SHIFT (0U) /*! BUF63TO32M - Buffer MBi Mask */ #define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) /*! @} */ /*! @name IMASK1 - Interrupt Masks 1 */ /*! @{ */ #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) /*! BUF31TO0M - Buffer MBi Mask */ #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) /*! @} */ /*! @name IFLAG2 - Interrupt Flags 2 */ /*! @{ */ #define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) #define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) /*! BUF63TO32I - Buffer MBi Interrupt */ #define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) /*! @} */ /*! @name IFLAG1 - Interrupt Flags 1 */ /*! @{ */ #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) /*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit * 0b0..MB0 has no occurrence of successfully completed transmission or reception. * 0b1..MB0 has successfully completed transmission or reception. */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) /*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) /*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO * 0b0..No occurrence of completed transmission or reception, or no frames available * 0b1..MB5 completed transmission or reception, or frames available */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) /*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. * 0b1..MB6 completed transmission or reception, or FIFO almost full. */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) /*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. * 0b1..MB7 completed transmission or reception, or FIFO overflow. */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) /*! BUF31TO8I - Buffer MBi Interrupt */ #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) /*! @} */ /*! @name CTRL2 - Control 2 */ /*! @{ */ #define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U) #define CAN_CTRL2_TSTAMPCAP_SHIFT (6U) /*! TSTAMPCAP - Timestamp Capture Point * 0b00..Disabled * 0b01..End of the CAN frame * 0b10..Start of the CAN frame * 0b11..Start of frame for classical CAN frames; res bit for CAN FD frames */ #define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK) #define CAN_CTRL2_MBTSBASE_MASK (0x300U) #define CAN_CTRL2_MBTSBASE_SHIFT (8U) /*! MBTSBASE - Message Buffer Timestamp Base * 0b00..TIMER * 0b01..Lower 16 bits of high-resolution timer * 0b10..Upper 16 bits of high-resolution timer * 0b11..Reserved */ #define CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK) #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) /*! EDFLTDIS - Edge Filter Disable * 0b0..Enabled * 0b1..Disabled */ #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) /*! ISOCANFDEN - ISO CAN FD Enable * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) #define CAN_CTRL2_BTE_MASK (0x2000U) #define CAN_CTRL2_BTE_SHIFT (13U) /*! BTE - Bit Timing Expansion Enable * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) #define CAN_CTRL2_PREXCEN_MASK (0x4000U) #define CAN_CTRL2_PREXCEN_SHIFT (14U) /*! PREXCEN - Protocol Exception Enable * 0b0..Disabled * 0b1..Enabled */ #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) #define CAN_CTRL2_TIMER_SRC_MASK (0x8000U) #define CAN_CTRL2_TIMER_SRC_SHIFT (15U) /*! TIMER_SRC - Timer Source * 0b0..CAN bit clock * 0b1..External time tick */ #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) /*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing * 0b0..Generated * 0b1..Stored */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) /*! MRP - Message Buffers Reception Priority * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) /*! TASD - Transmission Arbitration Start Delay */ #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) /*! RFFN - Number of Legacy Receive FIFO Filters */ #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) #define CAN_CTRL2_WRMFRZ_SHIFT (28U) /*! WRMFRZ - Write Access to Memory in Freeze Mode * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) #define CAN_CTRL2_ECRWRE_MASK (0x20000000U) #define CAN_CTRL2_ECRWRE_SHIFT (29U) /*! ECRWRE - Error Correction Configuration Register Write Enable * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK) #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) /*! BOFFDONEMSK - Bus Off Done Interrupt Mask * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) /*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames * 0b0..Disable * 0b1..Enable */ #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) /*! @} */ /*! @name ESR2 - Error and Status 2 */ /*! @{ */ #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) /*! IMB - Inactive Message Buffer * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. * 0b1..At least one message buffer is inactive. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status * 0b0..Invalid * 0b1..Valid */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) /*! LPTM - Lowest Priority TX Message Buffer */ #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) /*! @} */ /*! @name CRCR - Cyclic Redundancy Check */ /*! @{ */ #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) /*! TXCRC - Transmitted CRC value */ #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) /*! MBCRC - CRC Message Buffer */ #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) /*! @} */ /*! @name RXFGMASK - Legacy RX FIFO Global Mask */ /*! @{ */ #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) /*! FGM - Legacy RX FIFO Global Mask Bits */ #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) /*! @} */ /*! @name RXFIR - Legacy RX FIFO Information */ /*! @{ */ #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) /*! IDHIT - Identifier Acceptance Filter Hit Indicator */ #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) /*! @} */ /*! @name CBT - CAN Bit Timing */ /*! @{ */ #define CAN_CBT_EPSEG2_MASK (0x1FU) #define CAN_CBT_EPSEG2_SHIFT (0U) /*! EPSEG2 - Extended Phase Segment 2 */ #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) #define CAN_CBT_EPSEG1_MASK (0x3E0U) #define CAN_CBT_EPSEG1_SHIFT (5U) /*! EPSEG1 - Extended Phase Segment 1 */ #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) #define CAN_CBT_EPROPSEG_MASK (0xFC00U) #define CAN_CBT_EPROPSEG_SHIFT (10U) /*! EPROPSEG - Extended Propagation Segment */ #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) #define CAN_CBT_ERJW_MASK (0x1F0000U) #define CAN_CBT_ERJW_SHIFT (16U) /*! ERJW - Extended Resync Jump Width */ #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) #define CAN_CBT_EPRESDIV_SHIFT (21U) /*! EPRESDIV - Extended Prescaler Division Factor */ #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) #define CAN_CBT_BTF_MASK (0x80000000U) #define CAN_CBT_BTF_SHIFT (31U) /*! BTF - Bit Timing Format Enable * 0b0..Disable * 0b1..Enable */ #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) /*! @} */ /*! @name IMASK3 - Interrupt Masks 3 */ /*! @{ */ #define CAN_IMASK3_BUF95TO64M_MASK (0xFFFFFFFFU) #define CAN_IMASK3_BUF95TO64M_SHIFT (0U) /*! BUF95TO64M - Buffer MBi Mask */ #define CAN_IMASK3_BUF95TO64M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK3_BUF95TO64M_SHIFT)) & CAN_IMASK3_BUF95TO64M_MASK) /*! @} */ /*! @name IFLAG3 - Interrupt Flags 3 */ /*! @{ */ #define CAN_IFLAG3_BUF95TO64_MASK (0xFFFFFFFFU) #define CAN_IFLAG3_BUF95TO64_SHIFT (0U) /*! BUF95TO64 - Buffer MBi Interrupt */ #define CAN_IFLAG3_BUF95TO64(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG3_BUF95TO64_SHIFT)) & CAN_IFLAG3_BUF95TO64_MASK) /*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT_MB8B (96U) /* The count of CAN_ID */ #define CAN_ID_COUNT_MB8B (96U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB8B (96U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB8B2 (2U) /* The count of CAN_CS */ #define CAN_CS_COUNT_MB16B (63U) /* The count of CAN_ID */ #define CAN_ID_COUNT_MB16B (63U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB16B (63U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB16B2 (4U) /* The count of CAN_CS */ #define CAN_CS_COUNT_MB32B (36U) /* The count of CAN_ID */ #define CAN_ID_COUNT_MB32B (36U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB32B (36U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB32B2 (8U) /*! @name CS - Message Buffer 0 CS Register..Message Buffer 20 CS Register */ /*! @{ */ #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field * appears on the CAN bus. */ #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) #define CAN_CS_DLC_MASK (0xF0000U) #define CAN_CS_DLC_SHIFT (16U) /*! DLC - Length of the data to be stored/transmitted. */ #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) #define CAN_CS_RTR_MASK (0x100000U) #define CAN_CS_RTR_SHIFT (20U) /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) #define CAN_CS_IDE_MASK (0x200000U) #define CAN_CS_IDE_SHIFT (21U) /*! IDE - ID Extended. One/zero for extended/standard format frame. */ #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) #define CAN_CS_SRR_MASK (0x400000U) #define CAN_CS_SRR_SHIFT (22U) /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by * the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) #define CAN_CS_ESI_MASK (0x20000000U) #define CAN_CS_ESI_SHIFT (29U) /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) #define CAN_CS_BRS_MASK (0x40000000U) #define CAN_CS_BRS_SHIFT (30U) /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) #define CAN_CS_EDL_MASK (0x80000000U) #define CAN_CS_EDL_SHIFT (31U) /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ #define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) /*! @} */ /* The count of CAN_CS */ #define CAN_CS_COUNT_MB64B (21U) /*! @name ID - Message Buffer 0 ID Register..Message Buffer 20 ID Register */ /*! @{ */ #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) /*! EXT - Contains extended (LOW word) identifier of message buffer. */ #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) #define CAN_ID_STD_MASK (0x1FFC0000U) #define CAN_ID_STD_SHIFT (18U) /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular * ID to define the transmission priority. */ #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) /*! @} */ /* The count of CAN_ID */ #define CAN_ID_COUNT_MB64B (21U) /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 20 WORD_64B Register */ /*! @{ */ #define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_3_SHIFT (0U) /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) #define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_7_SHIFT (0U) /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) #define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_11_SHIFT (0U) /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) #define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_15_SHIFT (0U) /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) #define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_19_SHIFT (0U) /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) #define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_23_SHIFT (0U) /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) #define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_27_SHIFT (0U) /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) #define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_31_SHIFT (0U) /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) #define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_35_SHIFT (0U) /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) #define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_39_SHIFT (0U) /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) #define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_43_SHIFT (0U) /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) #define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_47_SHIFT (0U) /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) #define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_51_SHIFT (0U) /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) #define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_55_SHIFT (0U) /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) #define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_59_SHIFT (0U) /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) #define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_63_SHIFT (0U) /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) #define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_2_SHIFT (8U) /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) #define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_6_SHIFT (8U) /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) #define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_10_SHIFT (8U) /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) #define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_14_SHIFT (8U) /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) #define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_18_SHIFT (8U) /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) #define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_22_SHIFT (8U) /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) #define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_26_SHIFT (8U) /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) #define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_30_SHIFT (8U) /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) #define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_34_SHIFT (8U) /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) #define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_38_SHIFT (8U) /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) #define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_42_SHIFT (8U) /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) #define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_46_SHIFT (8U) /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) #define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_50_SHIFT (8U) /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) #define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_54_SHIFT (8U) /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) #define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_58_SHIFT (8U) /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) #define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_62_SHIFT (8U) /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) #define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_1_SHIFT (16U) /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) #define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_5_SHIFT (16U) /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) #define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_9_SHIFT (16U) /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) #define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_13_SHIFT (16U) /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) #define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_17_SHIFT (16U) /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) #define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_21_SHIFT (16U) /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) #define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_25_SHIFT (16U) /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) #define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_29_SHIFT (16U) /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) #define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_33_SHIFT (16U) /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) #define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_37_SHIFT (16U) /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) #define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_41_SHIFT (16U) /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) #define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_45_SHIFT (16U) /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) #define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_49_SHIFT (16U) /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) #define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_53_SHIFT (16U) /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) #define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_57_SHIFT (16U) /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) #define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_61_SHIFT (16U) /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) #define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_0_SHIFT (24U) /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) #define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_4_SHIFT (24U) /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) #define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_8_SHIFT (24U) /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) #define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_12_SHIFT (24U) /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) #define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_16_SHIFT (24U) /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) #define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_20_SHIFT (24U) /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) #define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_24_SHIFT (24U) /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) #define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_28_SHIFT (24U) /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) #define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_32_SHIFT (24U) /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) #define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_36_SHIFT (24U) /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) #define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_40_SHIFT (24U) /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) #define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_44_SHIFT (24U) /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) #define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_48_SHIFT (24U) /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) #define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_52_SHIFT (24U) /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) #define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_56_SHIFT (24U) /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) #define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_60_SHIFT (24U) /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) /*! @} */ /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB64B (21U) /* The count of CAN_WORD */ #define CAN_WORD_COUNT_MB64B2 (16U) /* The count of CAN_CS */ #define CAN_CS_COUNT (96U) /* The count of CAN_ID */ #define CAN_ID_COUNT (96U) /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 95 WORD0 Register */ /*! @{ */ #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) /*! @} */ /* The count of CAN_WORD0 */ #define CAN_WORD0_COUNT (96U) /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 95 WORD1 Register */ /*! @{ */ #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) /*! @} */ /* The count of CAN_WORD1 */ #define CAN_WORD1_COUNT (96U) /*! @name RXIMR - Receive Individual Mask */ /*! @{ */ #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) /*! MI - Individual Mask Bits */ #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) /*! @} */ /* The count of CAN_RXIMR */ #define CAN_RXIMR_COUNT (96U) /*! @name MECR - Memory Error Control */ /*! @{ */ #define CAN_MECR_NCEFAFRZ_MASK (0x80U) #define CAN_MECR_NCEFAFRZ_SHIFT (7U) /*! NCEFAFRZ - Noncorrectable Errors in FlexCAN Access Put Chip in Freeze Mode * 0b0..Normal operation * 0b1..Freeze mode */ #define CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK) #define CAN_MECR_ECCDIS_MASK (0x100U) #define CAN_MECR_ECCDIS_SHIFT (8U) /*! ECCDIS - Error Correction Disable * 0b0..Enable * 0b1..Disable */ #define CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK) #define CAN_MECR_RERRDIS_MASK (0x200U) #define CAN_MECR_RERRDIS_SHIFT (9U) /*! RERRDIS - Error Report Disable * 0b0..Enable * 0b1..Disable */ #define CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK) #define CAN_MECR_EXTERRIE_MASK (0x2000U) #define CAN_MECR_EXTERRIE_SHIFT (13U) /*! EXTERRIE - Extended Error Injection Enable * 0b0..Disable. Apply error injection only to the 32-bit word. * 0b1..Enable. Apply error injection to the 64-bit word. */ #define CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK) #define CAN_MECR_FAERRIE_MASK (0x4000U) #define CAN_MECR_FAERRIE_SHIFT (14U) /*! FAERRIE - FlexCAN Access Error Injection Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK) #define CAN_MECR_HAERRIE_MASK (0x8000U) #define CAN_MECR_HAERRIE_SHIFT (15U) /*! HAERRIE - Host Access Error Injection Enable * 0b0..Disable * 0b1..Enable */ #define CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK) #define CAN_MECR_CEI_MSK_MASK (0x10000U) #define CAN_MECR_CEI_MSK_SHIFT (16U) /*! CEI_MSK - Correctable Errors Interrupt Mask * 0b0..Disable * 0b1..Enable */ #define CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK) #define CAN_MECR_FANCEI_MSK_MASK (0x40000U) #define CAN_MECR_FANCEI_MSK_SHIFT (18U) /*! FANCEI_MSK - FlexCAN Access with Noncorrectable Errors Interrupt Mask * 0b0..Disable * 0b1..Enable */ #define CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK) #define CAN_MECR_HANCEI_MSK_MASK (0x80000U) #define CAN_MECR_HANCEI_MSK_SHIFT (19U) /*! HANCEI_MSK - Host Access with Noncorrectable Errors Interrupt Mask * 0b0..Disable * 0b1..Enable */ #define CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK) #define CAN_MECR_ECRWRDIS_MASK (0x80000000U) #define CAN_MECR_ECRWRDIS_SHIFT (31U) /*! ECRWRDIS - Error Configuration Register Write Disable * 0b0..Enable * 0b1..Disable */ #define CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK) /*! @} */ /*! @name ERRIAR - Error Injection Address */ /*! @{ */ #define CAN_ERRIAR_INJADDR_L_MASK (0x3U) #define CAN_ERRIAR_INJADDR_L_SHIFT (0U) /*! INJADDR_L - Error Injection Address Low */ #define CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK) #define CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU) #define CAN_ERRIAR_INJADDR_H_SHIFT (2U) /*! INJADDR_H - Error Injection Address High */ #define CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK) /*! @} */ /*! @name ERRIDPR - Error Injection Data Pattern */ /*! @{ */ #define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU) #define CAN_ERRIDPR_DFLIP_SHIFT (0U) /*! DFLIP - Data Flip Pattern */ #define CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK) /*! @} */ /*! @name ERRIPPR - Error Injection Parity Pattern */ /*! @{ */ #define CAN_ERRIPPR_PFLIP0_MASK (0x1FU) #define CAN_ERRIPPR_PFLIP0_SHIFT (0U) /*! PFLIP0 - Parity Flip Pattern for Byte 0 (Least Significant) */ #define CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK) #define CAN_ERRIPPR_PFLIP1_MASK (0x1F00U) #define CAN_ERRIPPR_PFLIP1_SHIFT (8U) /*! PFLIP1 - Parity Flip Pattern for Byte 1 */ #define CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK) #define CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U) #define CAN_ERRIPPR_PFLIP2_SHIFT (16U) /*! PFLIP2 - Parity Flip Pattern for Byte 2 */ #define CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK) #define CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U) #define CAN_ERRIPPR_PFLIP3_SHIFT (24U) /*! PFLIP3 - Parity Flip Pattern for Byte 3 (Most Significant) */ #define CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK) /*! @} */ /*! @name RERRAR - Error Report Address */ /*! @{ */ #define CAN_RERRAR_ERRADDR_MASK (0x3FFFU) #define CAN_RERRAR_ERRADDR_SHIFT (0U) /*! ERRADDR - Address Where Error Detected */ #define CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK) #define CAN_RERRAR_SAID_MASK (0x70000U) #define CAN_RERRAR_SAID_SHIFT (16U) /*! SAID - SAID */ #define CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK) #define CAN_RERRAR_NCE_MASK (0x1000000U) #define CAN_RERRAR_NCE_SHIFT (24U) /*! NCE - Noncorrectable Error * 0b0..Reporting a correctable error * 0b1..Reporting a noncorrectable error */ #define CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK) /*! @} */ /*! @name RERRDR - Error Report Data */ /*! @{ */ #define CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU) #define CAN_RERRDR_RDATA_SHIFT (0U) /*! RDATA - Raw Data Word Read from Memory with Error */ #define CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK) /*! @} */ /*! @name RERRSYNR - Error Report Syndrome */ /*! @{ */ #define CAN_RERRSYNR_SYND0_MASK (0x1FU) #define CAN_RERRSYNR_SYND0_SHIFT (0U) /*! SYND0 - Error Syndrome for Byte 0 (Least Significant) */ #define CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK) #define CAN_RERRSYNR_BE0_MASK (0x80U) #define CAN_RERRSYNR_BE0_SHIFT (7U) /*! BE0 - Byte Enabled for Byte 0 (Least Significant) * 0b0..Byte was not read. * 0b1..Byte was read. */ #define CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK) #define CAN_RERRSYNR_SYND1_MASK (0x1F00U) #define CAN_RERRSYNR_SYND1_SHIFT (8U) /*! SYND1 - Error Syndrome for Byte 1 */ #define CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK) #define CAN_RERRSYNR_BE1_MASK (0x8000U) #define CAN_RERRSYNR_BE1_SHIFT (15U) /*! BE1 - Byte Enabled for Byte 1 * 0b0..Byte was not read. * 0b1..Byte was read. */ #define CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK) #define CAN_RERRSYNR_SYND2_MASK (0x1F0000U) #define CAN_RERRSYNR_SYND2_SHIFT (16U) /*! SYND2 - Error Syndrome for Byte 2 */ #define CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK) #define CAN_RERRSYNR_BE2_MASK (0x800000U) #define CAN_RERRSYNR_BE2_SHIFT (23U) /*! BE2 - Byte Enabled for Byte 2 * 0b0..Byte was not read. * 0b1..Byte was read. */ #define CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK) #define CAN_RERRSYNR_SYND3_MASK (0x1F000000U) #define CAN_RERRSYNR_SYND3_SHIFT (24U) /*! SYND3 - Error Syndrome for Byte 3 (Most Significant) */ #define CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK) #define CAN_RERRSYNR_BE3_MASK (0x80000000U) #define CAN_RERRSYNR_BE3_SHIFT (31U) /*! BE3 - Byte Enabled for Byte 3 (Most Significant) * 0b0..Byte was not read. * 0b1..Byte was read. */ #define CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK) /*! @} */ /*! @name ERRSR - Error Status */ /*! @{ */ #define CAN_ERRSR_CEIOF_MASK (0x1U) #define CAN_ERRSR_CEIOF_SHIFT (0U) /*! CEIOF - Correctable Error Interrupt Overrun Flag * 0b0..No errors detected * 0b1..Error detected */ #define CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK) #define CAN_ERRSR_FANCEIOF_MASK (0x4U) #define CAN_ERRSR_FANCEIOF_SHIFT (2U) /*! FANCEIOF - FlexCAN Access with Noncorrectable Error Interrupt Overrun Flag * 0b0..No errors detected * 0b1..Error detected */ #define CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK) #define CAN_ERRSR_HANCEIOF_MASK (0x8U) #define CAN_ERRSR_HANCEIOF_SHIFT (3U) /*! HANCEIOF - Host Access With Noncorrectable Error Interrupt Overrun Flag * 0b0..No errors detected * 0b1..Error detected */ #define CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK) #define CAN_ERRSR_CEIF_MASK (0x10000U) #define CAN_ERRSR_CEIF_SHIFT (16U) /*! CEIF - Correctable Error Interrupt Flag * 0b0..No errors detected * 0b1..Error detected */ #define CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK) #define CAN_ERRSR_FANCEIF_MASK (0x40000U) #define CAN_ERRSR_FANCEIF_SHIFT (18U) /*! FANCEIF - FlexCAN Access with Noncorrectable Error Interrupt Flag * 0b0..No errors detected * 0b1..Error detected */ #define CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK) #define CAN_ERRSR_HANCEIF_MASK (0x80000U) #define CAN_ERRSR_HANCEIF_SHIFT (19U) /*! HANCEIF - Host Access with Noncorrectable Error Interrupt Flag * 0b0..No errors detected * 0b1..Error detected */ #define CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK) /*! @} */ /*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ /*! @{ */ #define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) #define CAN_EPRS_ENPRESDIV_SHIFT (0U) /*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ #define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) #define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) #define CAN_EPRS_EDPRESDIV_SHIFT (16U) /*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ #define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) /*! @} */ /*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ /*! @{ */ #define CAN_ENCBT_NTSEG1_MASK (0xFFU) #define CAN_ENCBT_NTSEG1_SHIFT (0U) /*! NTSEG1 - Nominal Time Segment 1 */ #define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) #define CAN_ENCBT_NTSEG2_MASK (0x7F000U) #define CAN_ENCBT_NTSEG2_SHIFT (12U) /*! NTSEG2 - Nominal Time Segment 2 */ #define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) #define CAN_ENCBT_NRJW_MASK (0x1FC00000U) #define CAN_ENCBT_NRJW_SHIFT (22U) /*! NRJW - Nominal Resynchronization Jump Width */ #define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) /*! @} */ /*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ /*! @{ */ #define CAN_EDCBT_DTSEG1_MASK (0x1FU) #define CAN_EDCBT_DTSEG1_SHIFT (0U) /*! DTSEG1 - Data Phase Segment 1 */ #define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) #define CAN_EDCBT_DTSEG2_MASK (0xF000U) #define CAN_EDCBT_DTSEG2_SHIFT (12U) /*! DTSEG2 - Data Phase Time Segment 2 */ #define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) #define CAN_EDCBT_DRJW_MASK (0x3C00000U) #define CAN_EDCBT_DRJW_SHIFT (22U) /*! DRJW - Data Phase Resynchronization Jump Width */ #define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) /*! @} */ /*! @name ETDC - Enhanced Transceiver Delay Compensation */ /*! @{ */ #define CAN_ETDC_ETDCVAL_MASK (0xFFU) #define CAN_ETDC_ETDCVAL_SHIFT (0U) /*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ #define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) #define CAN_ETDC_ETDCFAIL_MASK (0x8000U) #define CAN_ETDC_ETDCFAIL_SHIFT (15U) /*! ETDCFAIL - Transceiver Delay Compensation Fail * 0b0..In range * 0b1..Out of range */ #define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) #define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) #define CAN_ETDC_ETDCOFF_SHIFT (16U) /*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ #define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) #define CAN_ETDC_TDMDIS_MASK (0x40000000U) #define CAN_ETDC_TDMDIS_SHIFT (30U) /*! TDMDIS - Transceiver Delay Measurement Disable * 0b0..Enable * 0b1..Disable */ #define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) #define CAN_ETDC_ETDCEN_MASK (0x80000000U) #define CAN_ETDC_ETDCEN_SHIFT (31U) /*! ETDCEN - Transceiver Delay Compensation Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) /*! @} */ /*! @name FDCTRL - CAN FD Control */ /*! @{ */ #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) #define CAN_FDCTRL_TDCVAL_SHIFT (0U) /*! TDCVAL - Transceiver Delay Compensation Value */ #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) #define CAN_FDCTRL_TDCOFF_SHIFT (8U) /*! TDCOFF - Transceiver Delay Compensation Offset */ #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) /*! TDCFAIL - Transceiver Delay Compensation Fail * 0b0..In range * 0b1..Out of range */ #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) #define CAN_FDCTRL_TDCEN_MASK (0x8000U) #define CAN_FDCTRL_TDCEN_SHIFT (15U) /*! TDCEN - Transceiver Delay Compensation Enable * 0b0..Disable * 0b1..Enable */ #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) #define CAN_FDCTRL_MBDSR0_SHIFT (16U) /*! MBDSR0 - Message Buffer Data Size for Region 0 * 0b00..8 bytes * 0b01..16 bytes * 0b10..32 bytes * 0b11..64 bytes */ #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) #define CAN_FDCTRL_MBDSR1_MASK (0x180000U) #define CAN_FDCTRL_MBDSR1_SHIFT (19U) /*! MBDSR1 - Message Buffer Data Size for Region 1 * 0b00..8 bytes * 0b01..16 bytes * 0b10..32 bytes * 0b11..64 bytes */ #define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) #define CAN_FDCTRL_MBDSR2_MASK (0xC00000U) #define CAN_FDCTRL_MBDSR2_SHIFT (22U) /*! MBDSR2 - Message Buffer Data Size for Region 2 * 0b00..8 bytes * 0b01..16 bytes * 0b10..32 bytes * 0b11..64 bytes */ #define CAN_FDCTRL_MBDSR2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR2_SHIFT)) & CAN_FDCTRL_MBDSR2_MASK) #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) #define CAN_FDCTRL_FDRATE_SHIFT (31U) /*! FDRATE - Bit Rate Switch Enable * 0b0..Disable * 0b1..Enable */ #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) /*! @} */ /*! @name FDCBT - CAN FD Bit Timing */ /*! @{ */ #define CAN_FDCBT_FPSEG2_MASK (0x7U) #define CAN_FDCBT_FPSEG2_SHIFT (0U) /*! FPSEG2 - Fast Phase Segment 2 */ #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) #define CAN_FDCBT_FPSEG1_MASK (0xE0U) #define CAN_FDCBT_FPSEG1_SHIFT (5U) /*! FPSEG1 - Fast Phase Segment 1 */ #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) #define CAN_FDCBT_FPROPSEG_SHIFT (10U) /*! FPROPSEG - Fast Propagation Segment */ #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) #define CAN_FDCBT_FRJW_MASK (0x70000U) #define CAN_FDCBT_FRJW_SHIFT (16U) /*! FRJW - Fast Resync Jump Width */ #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) #define CAN_FDCBT_FPRESDIV_SHIFT (20U) /*! FPRESDIV - Fast Prescaler Division Factor */ #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) /*! @} */ /*! @name FDCRC - CAN FD CRC */ /*! @{ */ #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) #define CAN_FDCRC_FD_TXCRC_SHIFT (0U) /*! FD_TXCRC - Extended Transmitted CRC value */ #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) /*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) /*! @} */ /*! @name ERFCR - Enhanced RX FIFO Control */ /*! @{ */ #define CAN_ERFCR_ERFWM_MASK (0x1FU) #define CAN_ERFCR_ERFWM_SHIFT (0U) /*! ERFWM - Enhanced RX FIFO Watermark */ #define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) #define CAN_ERFCR_NFE_MASK (0x3F00U) #define CAN_ERFCR_NFE_SHIFT (8U) /*! NFE - Number of Enhanced RX FIFO Filter Elements */ #define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) #define CAN_ERFCR_NEXIF_MASK (0x7F0000U) #define CAN_ERFCR_NEXIF_SHIFT (16U) /*! NEXIF - Number of Extended ID Filter Elements */ #define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) #define CAN_ERFCR_DMALW_MASK (0x7C000000U) #define CAN_ERFCR_DMALW_SHIFT (26U) /*! DMALW - DMA Last Word */ #define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) #define CAN_ERFCR_ERFEN_MASK (0x80000000U) #define CAN_ERFCR_ERFEN_SHIFT (31U) /*! ERFEN - Enhanced RX FIFO enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) /*! @} */ /*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ /*! @{ */ #define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) #define CAN_ERFIER_ERFDAIE_SHIFT (28U) /*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) #define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) #define CAN_ERFIER_ERFWMIIE_SHIFT (29U) /*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) #define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) #define CAN_ERFIER_ERFOVFIE_SHIFT (30U) /*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) #define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) #define CAN_ERFIER_ERFUFWIE_SHIFT (31U) /*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) /*! @} */ /*! @name ERFSR - Enhanced RX FIFO Status */ /*! @{ */ #define CAN_ERFSR_ERFEL_MASK (0x3FU) #define CAN_ERFSR_ERFEL_SHIFT (0U) /*! ERFEL - Enhanced RX FIFO Elements */ #define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) #define CAN_ERFSR_ERFF_MASK (0x10000U) #define CAN_ERFSR_ERFF_SHIFT (16U) /*! ERFF - Enhanced RX FIFO Full Flag * 0b0..Not full * 0b1..Full */ #define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) #define CAN_ERFSR_ERFE_MASK (0x20000U) #define CAN_ERFSR_ERFE_SHIFT (17U) /*! ERFE - Enhanced RX FIFO Empty Flag * 0b0..Not empty * 0b1..Empty */ #define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) #define CAN_ERFSR_ERFCLR_MASK (0x8000000U) #define CAN_ERFSR_ERFCLR_SHIFT (27U) /*! ERFCLR - Enhanced RX FIFO Clear * 0b0..No effect * 0b1..Clear enhanced RX FIFO content */ #define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) #define CAN_ERFSR_ERFDA_MASK (0x10000000U) #define CAN_ERFSR_ERFDA_SHIFT (28U) /*! ERFDA - Enhanced RX FIFO Data Available Flag * 0b0..No such occurrence * 0b1..At least one message stored in Enhanced RX FIFO */ #define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) #define CAN_ERFSR_ERFWMI_MASK (0x20000000U) #define CAN_ERFSR_ERFWMI_SHIFT (29U) /*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag * 0b0..No such occurrence * 0b1..Number of messages in FIFO is greater than the watermark */ #define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) #define CAN_ERFSR_ERFOVF_MASK (0x40000000U) #define CAN_ERFSR_ERFOVF_SHIFT (30U) /*! ERFOVF - Enhanced RX FIFO Overflow Flag * 0b0..No such occurrence * 0b1..Overflow */ #define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) #define CAN_ERFSR_ERFUFW_MASK (0x80000000U) #define CAN_ERFSR_ERFUFW_SHIFT (31U) /*! ERFUFW - Enhanced RX FIFO Underflow Flag * 0b0..No such occurrence * 0b1..Underflow */ #define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) /*! @} */ /*! @name HR_TIME_STAMP - High-Resolution Timestamp */ /*! @{ */ #define CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU) #define CAN_HR_TIME_STAMP_TS_SHIFT (0U) /*! TS - High-Resolution Timestamp */ #define CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK) /*! @} */ /* The count of CAN_HR_TIME_STAMP */ #define CAN_HR_TIME_STAMP_COUNT (96U) /*! @name ERFFEL - Enhanced RX FIFO Filter Element */ /*! @{ */ #define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) #define CAN_ERFFEL_FEL_SHIFT (0U) /*! FEL - Filter Element Bits */ #define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) /*! @} */ /* The count of CAN_ERFFEL */ #define CAN_ERFFEL_COUNT (128U) /*! * @} */ /* end of group CAN_Register_Masks */ /* CAN - Peripheral instance base addresses */ /** Peripheral CAN1 base address */ #define CAN1_BASE (0x443A0000u) /** Peripheral CAN1 base pointer */ #define CAN1 ((CAN_Type *)CAN1_BASE) /** Peripheral CAN2 base address */ #define CAN2_BASE (0x425B0000u) /** Peripheral CAN2 base pointer */ #define CAN2 ((CAN_Type *)CAN2_BASE) /** Peripheral CAN3 base address */ #define CAN3_BASE (0x42600000u) /** Peripheral CAN3 base pointer */ #define CAN3 ((CAN_Type *)CAN3_BASE) /** Peripheral CAN4 base address */ #define CAN4_BASE (0x427C0000u) /** Peripheral CAN4 base pointer */ #define CAN4 ((CAN_Type *)CAN4_BASE) /** Peripheral CAN5 base address */ #define CAN5_BASE (0x427D0000u) /** Peripheral CAN5 base pointer */ #define CAN5 ((CAN_Type *)CAN5_BASE) /** Array initializer of CAN peripheral base addresses */ #define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE, CAN4_BASE, CAN5_BASE } /** Array initializer of CAN peripheral base pointers */ #define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3, CAN4, CAN5 } /** Interrupt vectors for the CAN peripheral type */ #define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn, CAN4_IRQn, CAN5_IRQn } #define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn, CAN4_IRQn, CAN5_IRQn } #define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn, CAN4_IRQn, CAN5_IRQn } #define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn, CAN4_IRQn, CAN5_IRQn } #define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn, CAN4_IRQn, CAN5_IRQn } #define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn, CAN4_IRQn, CAN5_IRQn } /*! * @} */ /* end of group CAN_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CAS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CAS_Peripheral_Access_Layer CAS Peripheral Access Layer * @{ */ /** CAS - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ uint8_t RESERVED_0[4]; __IO uint32_t GAIN_CAM; /**< Camera 0 CAS Gain Register, array offset: 0x4, array step: 0x10 */ __IO uint32_t CORR_CAM; /**< Camera 0 CAS Correction Register, array offset: 0x8, array step: 0x10 */ __IO uint32_t OFFSET_CAM; /**< Camera 0 CAS Offset Register, array offset: 0xC, array step: 0x10 */ } NEO_PIPE2_CAS_CONF[1]; } CAS_Type; /* ---------------------------------------------------------------------------- -- CAS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAS_Register_Masks CAS Register Masks * @{ */ /*! @name GAIN_CAM - Camera 0 CAS Gain Register */ /*! @{ */ #define CAS_GAIN_CAM_SCALE_MASK (0xFFFFU) #define CAS_GAIN_CAM_SCALE_SHIFT (0U) #define CAS_GAIN_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << CAS_GAIN_CAM_SCALE_SHIFT)) & CAS_GAIN_CAM_SCALE_MASK) #define CAS_GAIN_CAM_SHIFT_MASK (0xFF0000U) #define CAS_GAIN_CAM_SHIFT_SHIFT (16U) #define CAS_GAIN_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << CAS_GAIN_CAM_SHIFT_SHIFT)) & CAS_GAIN_CAM_SHIFT_MASK) /*! @} */ /* The count of CAS_GAIN_CAM */ #define CAS_GAIN_CAM_COUNT (1U) /*! @name CORR_CAM - Camera 0 CAS Correction Register */ /*! @{ */ #define CAS_CORR_CAM_CORR_MASK (0xFFFFU) #define CAS_CORR_CAM_CORR_SHIFT (0U) #define CAS_CORR_CAM_CORR(x) (((uint32_t)(((uint32_t)(x)) << CAS_CORR_CAM_CORR_SHIFT)) & CAS_CORR_CAM_CORR_MASK) /*! @} */ /* The count of CAS_CORR_CAM */ #define CAS_CORR_CAM_COUNT (1U) /*! @name OFFSET_CAM - Camera 0 CAS Offset Register */ /*! @{ */ #define CAS_OFFSET_CAM_OFFSET_MASK (0xFFFFU) #define CAS_OFFSET_CAM_OFFSET_SHIFT (0U) #define CAS_OFFSET_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CAS_OFFSET_CAM_OFFSET_SHIFT)) & CAS_OFFSET_CAM_OFFSET_MASK) /*! @} */ /* The count of CAS_OFFSET_CAM */ #define CAS_OFFSET_CAM_COUNT (1U) /*! * @} */ /* end of group CAS_Register_Masks */ /* CAS - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__CAS base address */ #define CAMERA__ISP__CAS_BASE (0x4AE01500u) /** Peripheral CAMERA__ISP__CAS base pointer */ #define CAMERA__ISP__CAS ((CAS_Type *)CAMERA__ISP__CAS_BASE) /** Array initializer of CAS peripheral base addresses */ #define CAS_BASE_ADDRS { CAMERA__ISP__CAS_BASE } /** Array initializer of CAS peripheral base pointers */ #define CAS_BASE_PTRS { CAMERA__ISP__CAS } /*! * @} */ /* end of group CAS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer * @{ */ /** CCM - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x80 */ struct { /* offset: 0x0 */ __IO uint32_t RW; /**< Clock Root Control Register, offset: 0x0 */ __IO uint32_t SET; /**< Clock Root Control Register, offset: 0x4 */ __IO uint32_t CLR; /**< Clock Root Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< Clock Root Control Register, offset: 0xC */ } CLOCK_ROOT_CONTROL; uint8_t RESERVED_0[16]; __I uint32_t STATUS0; /**< Clock root working status, array offset: 0x20, array step: 0x80 */ uint8_t RESERVED_1[12]; __IO uint32_t AUTHEN; /**< Clock root access control, array offset: 0x30, array step: 0x80 */ uint8_t RESERVED_2[76]; } CLOCK_ROOT[123]; uint8_t RESERVED_0[2688]; struct { /* offset: 0x4800 */ uint32_t RW; /**< General Purpose Register, offset: 0x4800 */ uint32_t SET; /**< General Purpose Register, offset: 0x4804 */ uint32_t CLR; /**< General Purpose Register, offset: 0x4808 */ uint32_t TOG; /**< General Purpose Register, offset: 0x480C */ } GPR_SHARED0; struct { /* offset: 0x4810 */ __IO uint32_t RW; /**< GPR access control, offset: 0x4810 */ __IO uint32_t SET; /**< GPR access control, offset: 0x4814 */ __IO uint32_t CLR; /**< GPR access control, offset: 0x4818 */ __IO uint32_t TOG; /**< GPR access control, offset: 0x481C */ } GPR_SHARED0_AUTHEN; struct { /* offset: 0x4820 */ __IO uint32_t RW; /**< General Purpose Register, offset: 0x4820 */ __IO uint32_t SET; /**< General Purpose Register, offset: 0x4824 */ __IO uint32_t CLR; /**< General Purpose Register, offset: 0x4828 */ __IO uint32_t TOG; /**< General Purpose Register, offset: 0x482C */ } GPR_SHARED1; struct { /* offset: 0x4830 */ __IO uint32_t RW; /**< GPR access control, offset: 0x4830 */ __IO uint32_t SET; /**< GPR access control, offset: 0x4834 */ __IO uint32_t CLR; /**< GPR access control, offset: 0x4838 */ __IO uint32_t TOG; /**< GPR access control, offset: 0x483C */ } GPR_SHARED1_AUTHEN; struct { /* offset: 0x4840 */ __IO uint32_t RW; /**< General Purpose Register, offset: 0x4840 */ __IO uint32_t SET; /**< General Purpose Register, offset: 0x4844 */ __IO uint32_t CLR; /**< General Purpose Register, offset: 0x4848 */ __IO uint32_t TOG; /**< General Purpose Register, offset: 0x484C */ } GPR_SHARED2; struct { /* offset: 0x4850 */ __IO uint32_t RW; /**< GPR access control, offset: 0x4850 */ __IO uint32_t SET; /**< GPR access control, offset: 0x4854 */ __IO uint32_t CLR; /**< GPR access control, offset: 0x4858 */ __IO uint32_t TOG; /**< GPR access control, offset: 0x485C */ } GPR_SHARED2_AUTHEN; struct { /* offset: 0x4860, array step: 0x20 */ struct { /* offset: 0x4860 */ uint32_t RW; /**< General Purpose Register, offset: 0x4860 */ uint32_t SET; /**< General Purpose Register, offset: 0x4864 */ uint32_t CLR; /**< General Purpose Register, offset: 0x4868 */ uint32_t TOG; /**< General Purpose Register, offset: 0x486C */ } GPR_SHARED; struct { /* offset: 0x4870 */ __IO uint32_t RW; /**< GPR access control, offset: 0x4870 */ __IO uint32_t SET; /**< GPR access control, offset: 0x4874 */ __IO uint32_t CLR; /**< GPR access control, offset: 0x4878 */ __IO uint32_t TOG; /**< GPR access control, offset: 0x487C */ } GPR_SHARED_AUTHEN; } GPR_SHARED[5]; uint8_t RESERVED_1[768]; struct { /* offset: 0x4C00, array step: 0x20 */ struct { /* offset: 0x4C00 */ __IO uint32_t RW; /**< General purpose register, offset: 0x4C00 */ __IO uint32_t SET; /**< General purpose register, offset: 0x4C04 */ __IO uint32_t CLR; /**< General purpose register, offset: 0x4C08 */ __IO uint32_t TOG; /**< General purpose register, offset: 0x4C0C */ } GPR_PRIVATE; struct { /* offset: 0x4C10 */ __IO uint32_t RW; /**< GPR access control, offset: 0x4C10 */ __IO uint32_t SET; /**< GPR access control, offset: 0x4C14 */ __IO uint32_t CLR; /**< GPR access control, offset: 0x4C18 */ __IO uint32_t TOG; /**< GPR access control, offset: 0x4C1C */ } GPR_PRIVATE_AUTHEN; } GPR_PRIVATE[8]; uint8_t RESERVED_2[768]; struct { /* offset: 0x5000, array step: 0x40 */ __IO uint32_t DIRECT; /**< Clock source direct control, array offset: 0x5000, array step: 0x40 */ __I uint32_t LPM_STATUS0; /**< Low power mode information transfer status, array offset: 0x5004, array step: 0x40 */ __I uint32_t LPM_STATUS1; /**< Low power mode information transfer status, array offset: 0x5008, array step: 0x40 */ uint8_t RESERVED_0[4]; __IO uint32_t LPM0; /**< Clock source low power mode setting, array offset: 0x5010, array step: 0x40 */ __IO uint32_t LPM1; /**< clock source low power mode setting, array offset: 0x5014, array step: 0x40 */ uint8_t RESERVED_1[4]; __I uint32_t LPM_CUR; /**< LPM setting of current CPU domain, array offset: 0x501C, array step: 0x40 */ __I uint32_t STATUS0; /**< Clock source working status, array offset: 0x5020, array step: 0x40 */ __I uint32_t STATUS1; /**< Clock source domain status, array offset: 0x5024, array step: 0x40 */ uint8_t RESERVED_2[8]; __IO uint32_t AUTHEN; /**< Clock Source access control, array offset: 0x5030, array step: 0x40 */ uint8_t RESERVED_3[12]; } OSCPLL[39]; uint8_t RESERVED_3[9792]; struct { /* offset: 0x8000, array step: 0x40 */ __IO uint32_t DIRECT; /**< LPCG direct control, array offset: 0x8000, array step: 0x40 */ __I uint32_t LPM_STATUS0; /**< Low power mode information transfer status, array offset: 0x8004, array step: 0x40 */ __I uint32_t LPM_STATUS1; /**< Low power mode information transfer status, array offset: 0x8008, array step: 0x40 */ uint8_t RESERVED_0[4]; __IO uint32_t LPM0; /**< LPCG low power mode setting, array offset: 0x8010, array step: 0x40 */ __IO uint32_t LPM1; /**< LPCG low power mode setting, array offset: 0x8014, array step: 0x40 */ uint8_t RESERVED_1[4]; __IO uint32_t LPM_CUR; /**< LPM setting of current CPU domain, array offset: 0x801C, array step: 0x40 */ __I uint32_t STATUS0; /**< LPCG working status, array offset: 0x8020, array step: 0x40 */ __I uint32_t STATUS1; /**< LPCG domain status, array offset: 0x8024, array step: 0x40 */ uint8_t RESERVED_2[8]; __IO uint32_t AUTHEN; /**< LPCG access control, array offset: 0x8030, array step: 0x40 */ uint8_t RESERVED_3[12]; } LPCG[256]; } CCM_Type; /* ---------------------------------------------------------------------------- -- CCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCM_Register_Masks CCM Register Masks * @{ */ /*! @name CLOCK_ROOT - Clock Root Control Register */ /*! @{ */ #define CCM_CLOCK_ROOT_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_DIV_SHIFT (0U) /*! DIV - Clock division fraction. */ #define CCM_CLOCK_ROOT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_DIV_SHIFT)) & CCM_CLOCK_ROOT_DIV_MASK) #define CCM_CLOCK_ROOT_MUX_MASK (0x300U) #define CCM_CLOCK_ROOT_MUX_SHIFT (8U) /*! MUX - Clock multiplexer. * 0b10..Select clock source 2 * 0b00..Select clock source 0 * 0b01..Select clock source 1 * 0b11..Select clock source 3 */ #define CCM_CLOCK_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_MUX_SHIFT)) & CCM_CLOCK_ROOT_MUX_MASK) #define CCM_CLOCK_ROOT_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_OFF_SHIFT (24U) /*! OFF - Shutdown clock root. * 0b0..Clock is running. * 0b1..Turn off clock. */ #define CCM_CLOCK_ROOT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OFF_SHIFT)) & CCM_CLOCK_ROOT_OFF_MASK) /*! @} */ /*! @name CLOCK_ROOT_STATUS0 - Clock root working status */ /*! @{ */ #define CCM_CLOCK_ROOT_STATUS0_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT (0U) /*! DIV - Current clock root DIV setting */ #define CCM_CLOCK_ROOT_STATUS0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK) #define CCM_CLOCK_ROOT_STATUS0_MUX_MASK (0x300U) #define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT (8U) /*! MUX - Current clock root MUX setting */ #define CCM_CLOCK_ROOT_STATUS0_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK) #define CCM_CLOCK_ROOT_STATUS0_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT (24U) /*! OFF - Current clock root OFF setting * 0b0..Clock is running. * 0b1..Turn off clock. */ #define CCM_CLOCK_ROOT_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK) #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK (0x10000000U) #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT (28U) /*! SLICE_BUSY - Indication for clock generation logic is applying new setting. * 0b0..Clock generation logic is not busy. * 0b1..Clock generation logic is applying new setting. */ #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK) /*! @} */ /* The count of CCM_CLOCK_ROOT_STATUS0 */ #define CCM_CLOCK_ROOT_STATUS0_COUNT (123U) /*! @name CLOCK_ROOT_AUTHEN - Clock root access control */ /*! @{ */ #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..Clock Root settings can be changed in user mode. * 0b0..Clock Root settings cannot be changed in user mode. */ #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK) #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK (0x200U) #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK) #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK (0x800U) #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK) #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK (0x8000U) #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK) #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list settings */ #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) /*! @} */ /* The count of CCM_CLOCK_ROOT_AUTHEN */ #define CCM_CLOCK_ROOT_AUTHEN_COUNT (123U) /*! @name GPR_SHARED0_AUTHEN - GPR access control */ /*! @{ */ #define CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. */ #define CCM_GPR_SHARED0_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_USER_MASK) #define CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK (0x200U) #define CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_GPR_SHARED0_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_TZ_NS_MASK) #define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK (0x800U) #define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_GPR_SHARED0_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_TZ_MASK) #define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK (0x8000U) #define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_GPR_SHARED0_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_LOCK_LIST_MASK) #define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list settings */ #define CCM_GPR_SHARED0_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED0_AUTHEN_WHITE_LIST_MASK) /*! @} */ /*! @name GPR_SHARED1 - General Purpose Register */ /*! @{ */ #define CCM_GPR_SHARED1_CA55_CORE0_CLOCK_SELECT_MASK (0x1U) #define CCM_GPR_SHARED1_CA55_CORE0_CLOCK_SELECT_SHIFT (0U) /*! CA55_CORE0_CLOCK_SELECT - Clock select signal between ccm clock root and Arm PLL clock * 0b0..arm_a55_clk_root is used. * 0b1..The clock output of Arm PLL is selected. */ #define CCM_GPR_SHARED1_CA55_CORE0_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CORE0_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CORE0_CLOCK_SELECT_MASK) #define CCM_GPR_SHARED1_CA55_CORE1_CLOCK_SELECT_MASK (0x2U) #define CCM_GPR_SHARED1_CA55_CORE1_CLOCK_SELECT_SHIFT (1U) /*! CA55_CORE1_CLOCK_SELECT - Clock select signal between ccm clock root and Arm PLL clock * 0b0..arm_a55_clk_root is used. * 0b1..The clock output of Arm PLL is selected. */ #define CCM_GPR_SHARED1_CA55_CORE1_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CORE1_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CORE1_CLOCK_SELECT_MASK) #define CCM_GPR_SHARED1_CA55_CORE2_CLOCK_SELECT_MASK (0x4U) #define CCM_GPR_SHARED1_CA55_CORE2_CLOCK_SELECT_SHIFT (2U) /*! CA55_CORE2_CLOCK_SELECT - Clock select signal between ccm clock root and Arm PLL clock * 0b0..arm_a55_clk_root is used. * 0b1..The clock output of Arm PLL is selected. */ #define CCM_GPR_SHARED1_CA55_CORE2_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CORE2_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CORE2_CLOCK_SELECT_MASK) #define CCM_GPR_SHARED1_CA55_CORE3_CLOCK_SELECT_MASK (0x8U) #define CCM_GPR_SHARED1_CA55_CORE3_CLOCK_SELECT_SHIFT (3U) /*! CA55_CORE3_CLOCK_SELECT - Clock select signal between ccm clock root and Arm PLL clock * 0b0..arm_a55_clk_root is used. * 0b1..The clock output of Arm PLL is selected. */ #define CCM_GPR_SHARED1_CA55_CORE3_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CORE3_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CORE3_CLOCK_SELECT_MASK) #define CCM_GPR_SHARED1_CA55_CORE4_CLOCK_SELECT_MASK (0x10U) #define CCM_GPR_SHARED1_CA55_CORE4_CLOCK_SELECT_SHIFT (4U) /*! CA55_CORE4_CLOCK_SELECT - Clock select signal between ccm clock root and Arm PLL clock * 0b0..arm_a55_clk_root is used. * 0b1..The clock output of Arm PLL is selected. */ #define CCM_GPR_SHARED1_CA55_CORE4_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CORE4_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CORE4_CLOCK_SELECT_MASK) #define CCM_GPR_SHARED1_CA55_CORE5_CLOCK_SELECT_MASK (0x20U) #define CCM_GPR_SHARED1_CA55_CORE5_CLOCK_SELECT_SHIFT (5U) /*! CA55_CORE5_CLOCK_SELECT - Clock select signal between ccm clock root and Arm PLL clock * 0b0..arm_a55_clk_root is used. * 0b1..The clock output of Arm PLL is selected. */ #define CCM_GPR_SHARED1_CA55_CORE5_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_CORE5_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_CORE5_CLOCK_SELECT_MASK) #define CCM_GPR_SHARED1_CA55_PLATFORM_CLOCK_SELECT_MASK (0x40U) #define CCM_GPR_SHARED1_CA55_PLATFORM_CLOCK_SELECT_SHIFT (6U) /*! CA55_PLATFORM_CLOCK_SELECT - Clock select signal between ccm clock root and Arm PLL clock * 0b0..arm_a55_clk_root is used. * 0b1..The clock output of Arm PLL is selected. */ #define CCM_GPR_SHARED1_CA55_PLATFORM_CLOCK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_CA55_PLATFORM_CLOCK_SELECT_SHIFT)) & CCM_GPR_SHARED1_CA55_PLATFORM_CLOCK_SELECT_MASK) /*! @} */ /*! @name GPR_SHARED1_AUTHEN - GPR access control */ /*! @{ */ #define CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. */ #define CCM_GPR_SHARED1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_USER_MASK) #define CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK (0x200U) #define CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_GPR_SHARED1_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_TZ_NS_MASK) #define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK (0x800U) #define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_GPR_SHARED1_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_TZ_MASK) #define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK (0x8000U) #define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_GPR_SHARED1_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_LOCK_LIST_MASK) #define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list settings */ #define CCM_GPR_SHARED1_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED1_AUTHEN_WHITE_LIST_MASK) /*! @} */ /*! @name GPR_SHARED2 - General Purpose Register */ /*! @{ */ #define CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK (0x1U) #define CCM_GPR_SHARED2_DRAM_PLL_BYPASS_SHIFT (0U) /*! DRAM_PLL_BYPASS - Clock select signal between ccm clock root and DRAM PLL clock * 0b0..The clock output of DRAM PLL is selected. * 0b1..Dram_alt_clk_root is selected. */ #define CCM_GPR_SHARED2_DRAM_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_DRAM_PLL_BYPASS_SHIFT)) & CCM_GPR_SHARED2_DRAM_PLL_BYPASS_MASK) #define CCM_GPR_SHARED2_ANAMIX_TEMPSENSE_CLK_SEL_MASK (0x2U) #define CCM_GPR_SHARED2_ANAMIX_TEMPSENSE_CLK_SEL_SHIFT (1U) /*! ANAMIX_TEMPSENSE_CLK_SEL - Clock select signal between 24MHz oscillator clock and FRO clock * 0b0..24MHz oscillator clock is selected. * 0b1..FRO clock is selected. */ #define CCM_GPR_SHARED2_ANAMIX_TEMPSENSE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_ANAMIX_TEMPSENSE_CLK_SEL_SHIFT)) & CCM_GPR_SHARED2_ANAMIX_TEMPSENSE_CLK_SEL_MASK) /*! @} */ /*! @name GPR_SHARED2_AUTHEN - GPR access control */ /*! @{ */ #define CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. */ #define CCM_GPR_SHARED2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_USER_MASK) #define CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK (0x200U) #define CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_GPR_SHARED2_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_TZ_NS_MASK) #define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK (0x800U) #define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_GPR_SHARED2_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_TZ_MASK) #define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK (0x8000U) #define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_GPR_SHARED2_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_LOCK_LIST_MASK) #define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list settings */ #define CCM_GPR_SHARED2_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED2_AUTHEN_WHITE_LIST_MASK) /*! @} */ /*! @name GPR_SHARED - GPR access control */ /*! @{ */ #define CCM_GPR_SHARED_TZ_USER_MASK (0x100U) #define CCM_GPR_SHARED_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..Registers of shared GPR slice can be changed in user mode. * 0b0..Registers of shared GPR slice cannot be changed in user mode. */ #define CCM_GPR_SHARED_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TZ_USER_SHIFT)) & CCM_GPR_SHARED_TZ_USER_MASK) #define CCM_GPR_SHARED_TZ_NS_MASK (0x200U) #define CCM_GPR_SHARED_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_GPR_SHARED_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TZ_NS_SHIFT)) & CCM_GPR_SHARED_TZ_NS_MASK) #define CCM_GPR_SHARED_LOCK_TZ_MASK (0x800U) #define CCM_GPR_SHARED_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_GPR_SHARED_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_LOCK_TZ_MASK) #define CCM_GPR_SHARED_LOCK_LIST_MASK (0x8000U) #define CCM_GPR_SHARED_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_GPR_SHARED_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_LOCK_LIST_MASK) #define CCM_GPR_SHARED_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_GPR_SHARED_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list settings */ #define CCM_GPR_SHARED_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_WHITE_LIST_MASK) /*! @} */ /*! @name GPR_PRIVATE - General purpose register */ /*! @{ */ #define CCM_GPR_PRIVATE_GPR_MASK (0xFFFFFFFFU) #define CCM_GPR_PRIVATE_GPR_SHIFT (0U) /*! GPR - GP register */ #define CCM_GPR_PRIVATE_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_GPR_SHIFT)) & CCM_GPR_PRIVATE_GPR_MASK) /*! @} */ /*! @name GPR_PRIVATE - GPR access control */ /*! @{ */ #define CCM_GPR_PRIVATE_TZ_USER_MASK (0x100U) #define CCM_GPR_PRIVATE_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..Registers of private GPR can be changed in user mode. * 0b0..Registers of private GPR cannot be changed in user mode. */ #define CCM_GPR_PRIVATE_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_TZ_USER_MASK) #define CCM_GPR_PRIVATE_TZ_NS_MASK (0x200U) #define CCM_GPR_PRIVATE_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_GPR_PRIVATE_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_TZ_NS_MASK) #define CCM_GPR_PRIVATE_LOCK_TZ_MASK (0x800U) #define CCM_GPR_PRIVATE_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_GPR_PRIVATE_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_LOCK_TZ_MASK) #define CCM_GPR_PRIVATE_LOCK_LIST_MASK (0x8000U) #define CCM_GPR_PRIVATE_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_GPR_PRIVATE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_LOCK_LIST_MASK) #define CCM_GPR_PRIVATE_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_GPR_PRIVATE_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list settings */ #define CCM_GPR_PRIVATE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_WHITE_LIST_MASK) /*! @} */ /*! @name OSCPLL_DIRECT - Clock source direct control */ /*! @{ */ #define CCM_OSCPLL_DIRECT_ON_MASK (0x1U) #define CCM_OSCPLL_DIRECT_ON_SHIFT (0U) /*! ON - Turn on clock source * 0b0..Clock source is OFF. * 0b1..Clock source is ON. */ #define CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK) /*! @} */ /* The count of CCM_OSCPLL_DIRECT */ #define CCM_OSCPLL_DIRECT_COUNT (39U) /*! @name OSCPLL_LPM_STATUS0 - Low power mode information transfer status */ /*! @{ */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK (0x3U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT (0U) /*! CPU_MODE_DOMAIN0 - Current mode of CPU domain 0 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK (0x4U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT (2U) /*! TRANS_REQ_DOMAIN0 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK (0x30U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT (4U) /*! CPU_MODE_DOMAIN1 - Current mode of CPU domain 1 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK (0x40U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT (6U) /*! TRANS_REQ_DOMAIN1 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK (0x300U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT (8U) /*! CPU_MODE_DOMAIN2 - Current mode of CPU domain 2 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK (0x400U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT (10U) /*! TRANS_REQ_DOMAIN2 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK (0x3000U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT (12U) /*! CPU_MODE_DOMAIN3 - Current mode of CPU domain 3 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK (0x4000U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT (14U) /*! TRANS_REQ_DOMAIN3 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK (0x30000U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT (16U) /*! CPU_MODE_DOMAIN4 - Current mode of CPU domain 4 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK (0x40000U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT (18U) /*! TRANS_REQ_DOMAIN4 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK (0x300000U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT (20U) /*! CPU_MODE_DOMAIN5 - Current mode of CPU domain 5 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK (0x400000U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT (22U) /*! TRANS_REQ_DOMAIN5 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK (0x3000000U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT (24U) /*! CPU_MODE_DOMAIN6 - Current mode of CPU domain 6 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK (0x4000000U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT (26U) /*! TRANS_REQ_DOMAIN6 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK (0x30000000U) #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT (28U) /*! CPU_MODE_DOMAIN7 - Current mode of CPU domain 7 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK (0x40000000U) #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT (30U) /*! TRANS_REQ_DOMAIN7 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT)) & CCM_OSCPLL_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK) /*! @} */ /* The count of CCM_OSCPLL_LPM_STATUS0 */ #define CCM_OSCPLL_LPM_STATUS0_COUNT (39U) /*! @name OSCPLL_LPM_STATUS1 - Low power mode information transfer status */ /*! @{ */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK (0x3U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT (0U) /*! CPU_MODE_DOMAIN8 - Current mode of CPU domain 8 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK (0x4U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT (2U) /*! TRANS_REQ_DOMAIN8 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK (0x30U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT (4U) /*! CPU_MODE_DOMAIN9 - Current mode of CPU domain 9 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK (0x40U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT (6U) /*! TRANS_REQ_DOMAIN9 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK (0x300U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT (8U) /*! CPU_MODE_DOMAIN10 - Current mode of CPU domain 10 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK (0x400U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT (10U) /*! TRANS_REQ_DOMAIN10 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK (0x3000U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT (12U) /*! CPU_MODE_DOMAIN11 - Current mode of CPU domain 11 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK (0x4000U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT (14U) /*! TRANS_REQ_DOMAIN11 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK (0x30000U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT (16U) /*! CPU_MODE_DOMAIN12 - Current mode of CPU domain 12 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK (0x40000U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT (18U) /*! TRANS_REQ_DOMAIN12 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK (0x300000U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT (20U) /*! CPU_MODE_DOMAIN13 - Current mode of CPU domain 13 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK (0x400000U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT (22U) /*! TRANS_REQ_DOMAIN13 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK (0x3000000U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT (24U) /*! CPU_MODE_DOMAIN14 - Current mode of CPU domain 14 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK (0x4000000U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT (26U) /*! TRANS_REQ_DOMAIN14 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK (0x30000000U) #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT (28U) /*! CPU_MODE_DOMAIN15 - Current mode of CPU domain 15 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK (0x40000000U) #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT (30U) /*! TRANS_REQ_DOMAIN15 - GPC request CCM to enable or disable OSCPLL. This signal will turn to low once CCM complete response to GPC. */ #define CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT)) & CCM_OSCPLL_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK) /*! @} */ /* The count of CCM_OSCPLL_LPM_STATUS1 */ #define CCM_OSCPLL_LPM_STATUS1_COUNT (39U) /*! @name OSCPLL_LPM0 - Clock source low power mode setting */ /*! @{ */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK (0x7U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT (0U) /*! LPM_SETTING_D0 - Clock Source low power mode setting in DOMAIN0 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D0_MASK) #define CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK (0x70U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT (4U) /*! LPM_SETTING_D1 - Clock Source low power mode setting in DOMAIN1 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D1_MASK) #define CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK (0x700U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT (8U) /*! LPM_SETTING_D2 - Clock Source low power mode setting in DOMAIN2 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D2_MASK) #define CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK (0x7000U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT (12U) /*! LPM_SETTING_D3 - Clock Source low power mode setting in DOMAIN3 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D3_MASK) #define CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK (0x70000U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT (16U) /*! LPM_SETTING_D4 - Clock Source low power mode setting in DOMAIN4 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D4_MASK) #define CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK (0x700000U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT (20U) /*! LPM_SETTING_D5 - Clock Source low power mode setting in DOMAIN5 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D5_MASK) #define CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK (0x7000000U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT (24U) /*! LPM_SETTING_D6 - Clock Source low power mode setting in DOMAIN6 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D6_MASK) #define CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK (0x70000000U) #define CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT (28U) /*! LPM_SETTING_D7 - Clock Source low power mode setting in DOMAIN7 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND Mode. */ #define CCM_OSCPLL_LPM0_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_OSCPLL_LPM0_LPM_SETTING_D7_MASK) /*! @} */ /* The count of CCM_OSCPLL_LPM0 */ #define CCM_OSCPLL_LPM0_COUNT (39U) /*! @name OSCPLL_LPM1 - clock source low power mode setting */ /*! @{ */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK (0x7U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT (0U) /*! LPM_SETTING_D8 - Clock Source LPM in DOMAIN8 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D8_MASK) #define CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK (0x70U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT (4U) /*! LPM_SETTING_D9 - Clock Source LPM in DOMAIN9 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D9_MASK) #define CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK (0x700U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT (8U) /*! LPM_SETTING_D10 - Clock Source LPM in DOMAIN10 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D10_MASK) #define CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK (0x7000U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT (12U) /*! LPM_SETTING_D11 - Clock Source LPM in DOMAIN11 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D11_MASK) #define CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK (0x70000U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT (16U) /*! LPM_SETTING_D12 - Clock Source LPM in DOMAIN12 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D12_MASK) #define CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK (0x700000U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT (20U) /*! LPM_SETTING_D13 - Clock Source LPM in DOMAIN13 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D13_MASK) #define CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK (0x7000000U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT (24U) /*! LPM_SETTING_D14 - Clock Source LPM in DOMAIN14 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D14_MASK) #define CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK (0x70000000U) #define CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT (28U) /*! LPM_SETTING_D15 - Clock Source LPM in DOMAIN15 * 0b000..Clock Source will be OFF in any CPU mode. * 0b001..Clock Source will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b010..Clock Source will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b011..Clock Source will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. * 0b100..Clock Source will be ON in RUN/WAIT/STOP/SUSPEND mode. */ #define CCM_OSCPLL_LPM1_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_OSCPLL_LPM1_LPM_SETTING_D15_MASK) /*! @} */ /* The count of CCM_OSCPLL_LPM1 */ #define CCM_OSCPLL_LPM1_COUNT (39U) /*! @name OSCPLL_LPM_CUR - LPM setting of current CPU domain */ /*! @{ */ #define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK (0x7U) #define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT (0U) /*! LPM_SETTING_CUR - LPM SETTING of current CPU DOMAIN */ #define CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_OSCPLL_LPM_CUR_LPM_SETTING_CUR_MASK) /*! @} */ /* The count of CCM_OSCPLL_LPM_CUR */ #define CCM_OSCPLL_LPM_CUR_COUNT (39U) /*! @name OSCPLL_STATUS0 - Clock source working status */ /*! @{ */ #define CCM_OSCPLL_STATUS0_ON_MASK (0x1U) #define CCM_OSCPLL_STATUS0_ON_SHIFT (0U) /*! ON - Clock source current state * 0b0..Clock source is OFF. * 0b1..Clock source is ON. */ #define CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK) #define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U) #define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U) #define CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK) #define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U) #define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U) #define CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK) #define CCM_OSCPLL_STATUS0_IN_USE_MASK (0x1000U) #define CCM_OSCPLL_STATUS0_IN_USE_SHIFT (12U) /*! IN_USE - This Clock Source is being used or not. * 0b0..Clock Source is not being used. * 0b1..Clock Source is being used. */ #define CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK) /*! @} */ /* The count of CCM_OSCPLL_STATUS0 */ #define CCM_OSCPLL_STATUS0_COUNT (39U) /*! @name OSCPLL_STATUS1 - Clock source domain status */ /*! @{ */ #define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK (0xFFFFU) #define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT (0U) /*! DOMAIN_ACTIVE - Domain active */ #define CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ACTIVE_MASK) #define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK (0xFFFF0000U) #define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT (16U) /*! DOMAIN_ENABLE - Domain enable */ #define CCM_OSCPLL_STATUS1_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS1_DOMAIN_ENABLE_MASK) /*! @} */ /* The count of CCM_OSCPLL_STATUS1 */ #define CCM_OSCPLL_STATUS1_COUNT (39U) /*! @name OSCPLL_AUTHEN - Clock Source access control */ /*! @{ */ #define CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK (0x4U) #define CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT (2U) /*! CPULPM_MODE - CPULPM mode enable * 0b0..Disable CPULPM mode. * 0b1..Enable CPULPM mode. */ #define CCM_OSCPLL_AUTHEN_CPULPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MODE_MASK) #define CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK (0x8U) #define CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT (3U) /*! AUTO_CTRL - Auto mode enable * 0b0..Disable Auto mode * 0b1..Enable Auto mode */ #define CCM_OSCPLL_AUTHEN_AUTO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_AUTO_CTRL_SHIFT)) & CCM_OSCPLL_AUTHEN_AUTO_CTRL_MASK) #define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x80U) #define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (7U) /*! LOCK_MODE * 0b0..CPULPM_MODE and AUTO_CTRL is not locked. * 0b1..CPULPM_MODE and AUTO_CTRL is locked. */ #define CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK) #define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..Clock Source settings can be changed in user mode. * 0b0..Clock Source settings cannot be changed in user mode. */ #define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK) #define CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x200U) #define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK) #define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x800U) #define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK) #define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x8000U) #define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK) #define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list */ #define CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) /*! @} */ /* The count of CCM_OSCPLL_AUTHEN */ #define CCM_OSCPLL_AUTHEN_COUNT (39U) /*! @name LPCG_DIRECT - LPCG direct control */ /*! @{ */ #define CCM_LPCG_DIRECT_ON_MASK (0x1U) #define CCM_LPCG_DIRECT_ON_SHIFT (0U) /*! ON - Turn on LPCG * 0b0..LPCG is OFF. * 0b1..LPCG is ON. */ #define CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK) #define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK (0x4U) #define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT (2U) /*! CLKOFF_ACK_TIMEOUT_EN - Clock off handshake timeout enable * 0b0..disable * 0b1..enable */ #define CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_SHIFT)) & CCM_LPCG_DIRECT_CLKOFF_ACK_TIMEOUT_EN_MASK) /*! @} */ /* The count of CCM_LPCG_DIRECT */ #define CCM_LPCG_DIRECT_COUNT (256U) /*! @name LPCG_LPM_STATUS0 - Low power mode information transfer status */ /*! @{ */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK (0x3U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT (0U) /*! CPU_MODE_DOMAIN0 - Current mode of CPU domain 0 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN0_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK (0x4U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT (2U) /*! TRANS_REQ_DOMAIN0 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN0_MASK) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK (0x30U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT (4U) /*! CPU_MODE_DOMAIN1 - Current mode of CPU domain 1 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN1_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK (0x40U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT (6U) /*! TRANS_REQ_DOMAIN1 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN1_MASK) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK (0x300U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT (8U) /*! CPU_MODE_DOMAIN2 - Current mode of CPU domain 2 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN2_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK (0x400U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT (10U) /*! TRANS_REQ_DOMAIN2 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN2_MASK) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK (0x3000U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT (12U) /*! CPU_MODE_DOMAIN3 - Current mode of CPU domain 3 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN3_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK (0x4000U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT (14U) /*! TRANS_REQ_DOMAIN3 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN3_MASK) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK (0x30000U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT (16U) /*! CPU_MODE_DOMAIN4 - Current mode of CPU domain 4 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN4_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK (0x40000U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT (18U) /*! TRANS_REQ_DOMAIN4 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN4_MASK) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK (0x300000U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT (20U) /*! CPU_MODE_DOMAIN5 - Current mode of CPU domain 5 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN5_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK (0x400000U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT (22U) /*! TRANS_REQ_DOMAIN5 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN5_MASK) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK (0x3000000U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT (24U) /*! CPU_MODE_DOMAIN6 - Current mode of CPU domain 6 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN6_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK (0x4000000U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT (26U) /*! TRANS_REQ_DOMAIN6 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN6_MASK) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK (0x30000000U) #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT (28U) /*! CPU_MODE_DOMAIN7 - Current mode of CPU domain 7 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_SHIFT)) & CCM_LPCG_LPM_STATUS0_CPU_MODE_DOMAIN7_MASK) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK (0x40000000U) #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT (30U) /*! TRANS_REQ_DOMAIN7 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_SHIFT)) & CCM_LPCG_LPM_STATUS0_TRANS_REQ_DOMAIN7_MASK) /*! @} */ /* The count of CCM_LPCG_LPM_STATUS0 */ #define CCM_LPCG_LPM_STATUS0_COUNT (256U) /*! @name LPCG_LPM_STATUS1 - Low power mode information transfer status */ /*! @{ */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK (0x3U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT (0U) /*! CPU_MODE_DOMAIN8 - Current mode of CPU domain 8 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN8_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK (0x4U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT (2U) /*! TRANS_REQ_DOMAIN8 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN8_MASK) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK (0x30U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT (4U) /*! CPU_MODE_DOMAIN9 - Current mode of CPU domain 9 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN9_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK (0x40U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT (6U) /*! TRANS_REQ_DOMAIN9 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN9_MASK) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK (0x300U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT (8U) /*! CPU_MODE_DOMAIN10 - Current mode of CPU domain 10 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN10_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK (0x400U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT (10U) /*! TRANS_REQ_DOMAIN10 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN10_MASK) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK (0x3000U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT (12U) /*! CPU_MODE_DOMAIN11 - Current mode of CPU domain 11 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN11_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK (0x4000U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT (14U) /*! TRANS_REQ_DOMAIN11 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN11_MASK) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK (0x30000U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT (16U) /*! CPU_MODE_DOMAIN12 - Current mode of CPU domain 12 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN12_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK (0x40000U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT (18U) /*! TRANS_REQ_DOMAIN12 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN12_MASK) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK (0x300000U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT (20U) /*! CPU_MODE_DOMAIN13 - Current mode of CPU domain 13 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN13_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK (0x400000U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT (22U) /*! TRANS_REQ_DOMAIN13 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN13_MASK) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK (0x3000000U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT (24U) /*! CPU_MODE_DOMAIN14 - Current mode of CPU domain 14 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN14_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK (0x4000000U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT (26U) /*! TRANS_REQ_DOMAIN14 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN14_MASK) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK (0x30000000U) #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT (28U) /*! CPU_MODE_DOMAIN15 - Current mode of CPU domain 15 * 0b00..CPU is in RUN mode * 0b01..CPU is in WAIT mode * 0b10..CPU is in STOP mode * 0b11..CPU is in SUSPEND mode */ #define CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_SHIFT)) & CCM_LPCG_LPM_STATUS1_CPU_MODE_DOMAIN15_MASK) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK (0x40000000U) #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT (30U) /*! TRANS_REQ_DOMAIN15 - GPC request CCM to enable or disable LPCG. This signal will turn to low once CCM complete response to GPC. */ #define CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_SHIFT)) & CCM_LPCG_LPM_STATUS1_TRANS_REQ_DOMAIN15_MASK) /*! @} */ /* The count of CCM_LPCG_LPM_STATUS1 */ #define CCM_LPCG_LPM_STATUS1_COUNT (256U) /*! @name LPCG_LPM0 - LPCG low power mode setting */ /*! @{ */ #define CCM_LPCG_LPM0_LPM_SETTING_D0_MASK (0x3U) #define CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT (0U) /*! LPM_SETTING_D0 - LPCG low power mode setting in DOMAIN0 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D0_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D0_MASK) #define CCM_LPCG_LPM0_LPM_SETTING_D1_MASK (0x30U) #define CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT (4U) /*! LPM_SETTING_D1 - LPCG low power mode setting in DOMAIN1 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D1_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D1_MASK) #define CCM_LPCG_LPM0_LPM_SETTING_D2_MASK (0x300U) #define CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT (8U) /*! LPM_SETTING_D2 - LPCG low power mode setting in DOMAIN2 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D2_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D2_MASK) #define CCM_LPCG_LPM0_LPM_SETTING_D3_MASK (0x3000U) #define CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT (12U) /*! LPM_SETTING_D3 - LPCG low power mode setting in DOMAIN3 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D3_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D3_MASK) #define CCM_LPCG_LPM0_LPM_SETTING_D4_MASK (0x30000U) #define CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT (16U) /*! LPM_SETTING_D4 - LPCG low power mode setting in DOMAIN4 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D4_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D4_MASK) #define CCM_LPCG_LPM0_LPM_SETTING_D5_MASK (0x300000U) #define CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT (20U) /*! LPM_SETTING_D5 - LPCG low power mode setting in DOMAIN5 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D5_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D5_MASK) #define CCM_LPCG_LPM0_LPM_SETTING_D6_MASK (0x3000000U) #define CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT (24U) /*! LPM_SETTING_D6 - LPCG low power mode setting in DOMAIN6 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D6_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D6_MASK) #define CCM_LPCG_LPM0_LPM_SETTING_D7_MASK (0x30000000U) #define CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT (28U) /*! LPM_SETTING_D7 - LPCG low power mode setting in DOMAIN7 * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM0_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM0_LPM_SETTING_D7_SHIFT)) & CCM_LPCG_LPM0_LPM_SETTING_D7_MASK) /*! @} */ /* The count of CCM_LPCG_LPM0 */ #define CCM_LPCG_LPM0_COUNT (256U) /*! @name LPCG_LPM1 - LPCG low power mode setting */ /*! @{ */ #define CCM_LPCG_LPM1_LPM_SETTING_D8_MASK (0x3U) #define CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT (0U) /*! LPM_SETTING_D8 - LPCG low power mode setting in DOMAIN8. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D8_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D8_MASK) #define CCM_LPCG_LPM1_LPM_SETTING_D9_MASK (0x30U) #define CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT (4U) /*! LPM_SETTING_D9 - LPCG low power mode setting in DOMAIN9. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D9_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D9_MASK) #define CCM_LPCG_LPM1_LPM_SETTING_D10_MASK (0x300U) #define CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT (8U) /*! LPM_SETTING_D10 - LPCG low power mode setting in DOMAIN10. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D10_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D10_MASK) #define CCM_LPCG_LPM1_LPM_SETTING_D11_MASK (0x3000U) #define CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT (12U) /*! LPM_SETTING_D11 - LPCG low power mode setting in DOMAIN11. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D11_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D11_MASK) #define CCM_LPCG_LPM1_LPM_SETTING_D12_MASK (0x30000U) #define CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT (16U) /*! LPM_SETTING_D12 - LPCG low power mode setting in DOMAIN12. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D12_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D12_MASK) #define CCM_LPCG_LPM1_LPM_SETTING_D13_MASK (0x300000U) #define CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT (20U) /*! LPM_SETTING_D13 - LPCG low power mode setting in DOMAIN13. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D13_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D13_MASK) #define CCM_LPCG_LPM1_LPM_SETTING_D14_MASK (0x3000000U) #define CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT (24U) /*! LPM_SETTING_D14 - LPCG low power mode setting in DOMAIN14. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D14_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D14_MASK) #define CCM_LPCG_LPM1_LPM_SETTING_D15_MASK (0x30000000U) #define CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT (28U) /*! LPM_SETTING_D15 - LPCG low power mode setting in DOMAIN15. * 0b00..LPCG will be OFF in any CPU mode. * 0b01..LPCG will be ON in RUN mode, OFF in WAIT/STOP/SUSPEND mode. * 0b10..LPCG will be ON in RUN/WAIT mode, OFF in STOP/SUSPEND mode. * 0b11..LPCG will be ON in RUN/WAIT/STOP mode, OFF in SUSPEND mode. */ #define CCM_LPCG_LPM1_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM1_LPM_SETTING_D15_SHIFT)) & CCM_LPCG_LPM1_LPM_SETTING_D15_MASK) /*! @} */ /* The count of CCM_LPCG_LPM1 */ #define CCM_LPCG_LPM1_COUNT (256U) /*! @name LPCG_LPM_CUR - LPM setting of current CPU domain */ /*! @{ */ #define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK (0x3U) #define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT (0U) /*! LPM_SETTING_CUR - LPM SETTING of current CPU DOMAIN */ #define CCM_LPCG_LPM_CUR_LPM_SETTING_CUR(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_SHIFT)) & CCM_LPCG_LPM_CUR_LPM_SETTING_CUR_MASK) /*! @} */ /* The count of CCM_LPCG_LPM_CUR */ #define CCM_LPCG_LPM_CUR_COUNT (256U) /*! @name LPCG_STATUS0 - LPCG working status */ /*! @{ */ #define CCM_LPCG_STATUS0_ON_MASK (0x1U) #define CCM_LPCG_STATUS0_ON_SHIFT (0U) /*! ON - LPCG work status * 0b0..LPCG is OFF. * 0b1..LPCG is ON. */ #define CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK) /*! @} */ /* The count of CCM_LPCG_STATUS0 */ #define CCM_LPCG_STATUS0_COUNT (256U) /*! @name LPCG_STATUS1 - LPCG domain status */ /*! @{ */ #define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK (0xFFFFU) #define CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT (0U) /*! DOMAIN_ACTIVE - Domain active */ #define CCM_LPCG_STATUS1_DOMAIN_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ACTIVE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ACTIVE_MASK) #define CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK (0xFFFF0000U) #define CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT (16U) /*! DOMAIN_ENABLE - Domain enable */ #define CCM_LPCG_STATUS1_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS1_DOMAIN_ENABLE_MASK) /*! @} */ /* The count of CCM_LPCG_STATUS1 */ #define CCM_LPCG_STATUS1_COUNT (256U) /*! @name LPCG_AUTHEN - LPCG access control */ /*! @{ */ #define CCM_LPCG_AUTHEN_CPULPM_MODE_MASK (0x4U) #define CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT (2U) /*! CPULPM_MODE - CPULPM mode enable * 0b0..Disable CPULPM mode, this LPCG is in Direct Control mode. * 0b1..Enable CPULPM mode, this LPCG is in CPULPM mode. */ #define CCM_LPCG_AUTHEN_CPULPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_MODE_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MODE_MASK) #define CCM_LPCG_AUTHEN_ACK_MODE_MASK (0x10U) #define CCM_LPCG_AUTHEN_ACK_MODE_SHIFT (4U) /*! ACK_MODE - ACK mode enable * 0b0..Disable ACK mode. If this LPCG is in Direct Control mode, SSI Q-channel cannot be controlled by SW * 0b1..Enable ACK mode. If this LPCG is in Direct Control mode, SSI Q-channel can also be controlled by SW */ #define CCM_LPCG_AUTHEN_ACK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_ACK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_ACK_MODE_MASK) #define CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x80U) #define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (7U) /*! LOCK_MODE * 0b0..CPULPM_MODE and ACK_MODE is not locked. * 0b1..CPULPM_MODE and ACK_MODE is locked. */ #define CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK) #define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x100U) #define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (8U) /*! TZ_USER - User access permission * 0b1..LPCG settings can be changed in user mode. * 0b0..LPCG settings cannot be changed in user mode. */ #define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK) #define CCM_LPCG_AUTHEN_TZ_NS_MASK (0x200U) #define CCM_LPCG_AUTHEN_TZ_NS_SHIFT (9U) /*! TZ_NS - Non-secure access permission * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ #define CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK) #define CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x800U) #define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock Trustzone settings * 0b0..Trustzone settings is not locked. * 0b1..Trustzone settings is locked. */ #define CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK) #define CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x8000U) #define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - Lock white list * 0b0..White list is not locked. * 0b1..White list is locked. */ #define CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK) #define CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xFFFF0000U) #define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - White list */ #define CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK) /*! @} */ /* The count of CCM_LPCG_AUTHEN */ #define CCM_LPCG_AUTHEN_COUNT (256U) /*! * @} */ /* end of group CCM_Register_Masks */ /* CCM - Peripheral instance base addresses */ /** Peripheral CCM_CTRL base address */ #define CCM_CTRL_BASE (0x44450000u) /** Peripheral CCM_CTRL base pointer */ #define CCM_CTRL ((CCM_Type *)CCM_CTRL_BASE) /** Array initializer of CCM peripheral base addresses */ #define CCM_BASE_ADDRS { CCM_CTRL_BASE } /** Array initializer of CCM peripheral base pointers */ #define CCM_BASE_PTRS { CCM_CTRL } /*! * @} */ /* end of group CCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CCMSRCGPC_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CCMSRCGPC_TCU_Peripheral_Access_Layer CCMSRCGPC_TCU Peripheral Access Layer * @{ */ /** CCMSRCGPC_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_3[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } CCMSRCGPC_TCU_Type; /* ---------------------------------------------------------------------------- -- CCMSRCGPC_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCMSRCGPC_TCU_Register_Masks CCMSRCGPC_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & CCMSRCGPC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & CCMSRCGPC_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x7FEU) #define CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & CCMSRCGPC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group CCMSRCGPC_TCU_Register_Masks */ /* CCMSRCGPC_TCU - Peripheral instance base addresses */ /** Peripheral CCMSRCGPC__TCU base address */ #define CCMSRCGPC__TCU_BASE (0x444D0000u) /** Peripheral CCMSRCGPC__TCU base pointer */ #define CCMSRCGPC__TCU ((CCMSRCGPC_TCU_Type *)CCMSRCGPC__TCU_BASE) /** Array initializer of CCMSRCGPC_TCU peripheral base addresses */ #define CCMSRCGPC_TCU_BASE_ADDRS { CCMSRCGPC__TCU_BASE } /** Array initializer of CCMSRCGPC_TCU peripheral base pointers */ #define CCMSRCGPC_TCU_BASE_PTRS { CCMSRCGPC__TCU } /*! * @} */ /* end of group CCMSRCGPC_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CCONVMED Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CCONVMED_Peripheral_Access_Layer CCONVMED Peripheral Access Layer * @{ */ /** CCONVMED - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL_CAM[1]; /**< Camera 0 CCONVMED Control Register, array offset: 0x0, array step: 0x4 */ } CCONVMED_Type; /* ---------------------------------------------------------------------------- -- CCONVMED Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CCONVMED_Register_Masks CCONVMED Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 CCONVMED Control Register */ /*! @{ */ #define CCONVMED_CTRL_CAM_FLT_MASK (0x30U) #define CCONVMED_CTRL_CAM_FLT_SHIFT (4U) /*! FLT * 0b00..Bypassed * 0b01..Filter type is convolution (5x5 binomial) * 0b10..Filter type is median (5x5) * 0b11..Reserved */ #define CCONVMED_CTRL_CAM_FLT(x) (((uint32_t)(((uint32_t)(x)) << CCONVMED_CTRL_CAM_FLT_SHIFT)) & CCONVMED_CTRL_CAM_FLT_MASK) /*! @} */ /* The count of CCONVMED_CTRL_CAM */ #define CCONVMED_CTRL_CAM_COUNT (1U) /*! * @} */ /* end of group CCONVMED_Register_Masks */ /* CCONVMED - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__CCONVMED base address */ #define CAMERA__ISP__CCONVMED_BASE (0x4AE014C0u) /** Peripheral CAMERA__ISP__CCONVMED base pointer */ #define CAMERA__ISP__CCONVMED ((CCONVMED_Type *)CAMERA__ISP__CCONVMED_BASE) /** Array initializer of CCONVMED peripheral base addresses */ #define CCONVMED_BASE_ADDRS { CAMERA__ISP__CCONVMED_BASE } /** Array initializer of CCONVMED peripheral base pointers */ #define CCONVMED_BASE_PTRS { CAMERA__ISP__CCONVMED } /*! * @} */ /* end of group CCONVMED_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- COLOR_TEMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup COLOR_TEMP_Peripheral_Access_Layer COLOR_TEMP Peripheral Access Layer * @{ */ /** COLOR_TEMP - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x1A4 */ __IO uint32_t CTRL_CAM; /**< Camera 0 COLORTEMP Control Register, array offset: 0x0, array step: 0x1A4 */ __IO uint32_t ROI_POS_CAM; /**< Camera 0 COLORTEMP Region of Interest Position Register, array offset: 0x4, array step: 0x1A4 */ __IO uint32_t ROI_SIZE_CAM; /**< Camera 0 COLORTEMP Region of Interest Size Register, array offset: 0x8, array step: 0x1A4 */ __IO uint32_t REDGAIN_CAM; /**< Camera 0 COLORTEMP Red Gain Register, array offset: 0xC, array step: 0x1A4 */ __IO uint32_t BLUEGAIN_CAM; /**< Camera 0 COLORTEMP Blue Gain Register, array offset: 0x10, array step: 0x1A4 */ __IO uint32_t POINT1_CAM; /**< Camera 0 COLORTEMP Point1 Register, array offset: 0x14, array step: 0x1A4 */ __IO uint32_t POINT2_CAM; /**< Camera 0 COLORTEMP Point2 Register, array offset: 0x18, array step: 0x1A4 */ __IO uint32_t HOFFSET_CAM; /**< Camera 0 COLORTEMP Horizontal Offset Register, array offset: 0x1C, array step: 0x1A4 */ __IO uint32_t VOFFSET_CAM; /**< Camera 0 COLORTEMP Vertical Offset Register, array offset: 0x20, array step: 0x1A4 */ __IO uint32_t POINT1_SLOPE_CAM; /**< Camera 0 COLORTEMP Point 1 Slope Register, array offset: 0x24, array step: 0x1A4 */ __IO uint32_t POINT2_SLOPE_CAM; /**< Camera 0 COLORTEMP Point 2 Slope Register, array offset: 0x28, array step: 0x1A4 */ __IO uint32_t LUMA_TH_CAM; /**< Camera 0 COLORTEMP Luma Threshold Register, array offset: 0x2C, array step: 0x1A4 */ __IO uint32_t CSC_MAT0_CAM; /**< Camera 0 COLORTEMP Color Space Correction Matrix 0 Register, array offset: 0x30, array step: 0x1A4 */ __IO uint32_t CSC_MAT1_CAM; /**< Camera 0 COLORTEMP Color Space Correction Matrix 1 Register, array offset: 0x34, array step: 0x1A4 */ __IO uint32_t CSC_MAT2_CAM; /**< Camera 0 COLORTEMP Color Space Correction Matrix 2 Register, array offset: 0x38, array step: 0x1A4 */ __IO uint32_t CSC_MAT3_CAM; /**< Camera 0 COLORTEMP Color Space Correction Matrix 3 Register, array offset: 0x3C, array step: 0x1A4 */ __IO uint32_t CSC_MAT4_CAM; /**< Camera 0 COLORTEMP Color Space Correction Matrix 4 Register, array offset: 0x40, array step: 0x1A4 */ __IO uint32_t R_GR_OFFSET_CAM; /**< Camera 0 COLORTEMP R Gr Offset Register, array offset: 0x44, array step: 0x1A4 */ __IO uint32_t GB_B_OFFSET_CAM; /**< Camera 0 COLORTEMP Gb B Offset Register, array offset: 0x48, array step: 0x1A4 */ __I uint32_t CNT_WHITE_CAM; /**< Camera 0 COLORTEMP White Count Register, array offset: 0x4C, array step: 0x1A4 */ __I uint32_t SUMRL_CAM; /**< Camera 0 COLORTEMP Red Sum Low Register, array offset: 0x50, array step: 0x1A4 */ __I uint32_t SUMRH_CAM; /**< Camera 0 COLORTEMP Red Sum High Register, array offset: 0x54, array step: 0x1A4 */ __I uint32_t SUMGL_CAM; /**< Camera 0 COLORTEMP Green Sum Low Register, array offset: 0x58, array step: 0x1A4 */ __I uint32_t SUMGH_CAM; /**< Camera 0 COLORTEMP Green Sum High Register, array offset: 0x5C, array step: 0x1A4 */ __I uint32_t SUMBL_CAM; /**< Camera 0 COLORTEMP Blue Sum Low Register, array offset: 0x60, array step: 0x1A4 */ __I uint32_t SUMBH_CAM; /**< Camera 0 COLORTEMP Blue Sum High Register, array offset: 0x64, array step: 0x1A4 */ __I uint32_t SUMRGL_CAM; /**< Camera 0 COLORTEMP R/G Sum Low Register, array offset: 0x68, array step: 0x1A4 */ __I uint32_t SUMRGH_CAM; /**< Camera 0 COLORTEMP R/G Sum High Register, array offset: 0x6C, array step: 0x1A4 */ __I uint32_t SUMBGL_CAM; /**< Camera 0 COLORTEMP B/G Sum Low Register, array offset: 0x70, array step: 0x1A4 */ __I uint32_t SUMBGH_CAM; /**< Camera 0 COLORTEMP B/G Sum High Register, array offset: 0x74, array step: 0x1A4 */ uint8_t RESERVED_0[8]; __IO uint32_t STAT_BLK_SIZE; /**< Camera 0 COLORTEMP Statistics Block Size Register, array offset: 0x80, array step: 0x1A4 */ uint8_t RESERVED_1[4]; __I uint32_t STAT_CURR_BLK_Y; /**< Camera 0 COLORTEMP Statistics Block Y Status, array offset: 0x88, array step: 0x1A4 */ uint8_t RESERVED_2[4]; struct { /* offset: 0x90, array step: index*0x1A4, index2*0x18 */ __IO uint32_t CROI_POS_CAM; /**< Camera 0 Color ROI 0 Position Register..Camera 0 Color ROI 9 Position Register, array offset: 0x90, array step: index*0x1A4, index2*0x18 */ uint8_t RESERVED_0[4]; __I uint32_t CROI_PIXCNT_CAM; /**< Camera 0 Color ROI 0 Pixel Count Register..Camera 0 Color ROI 9 Pixel Count Register, array offset: 0x98, array step: index*0x1A4, index2*0x18 */ __I uint32_t CROI_SUMRED_CAM; /**< Camera 0 Color ROI 0 SUM Red Register..Camera 0 Color ROI 9 SUM Red Register, array offset: 0x9C, array step: index*0x1A4, index2*0x18 */ __I uint32_t CROI_SUMGREEN_CAM; /**< Camera 0 Color ROI 0 SUM Green Register..Camera 0 Color ROI 9 SUM Green Register, array offset: 0xA0, array step: index*0x1A4, index2*0x18 */ __I uint32_t CROI_SUMBLUE_CAM; /**< Camera 0 Color ROI 0 SUM Blue Register..Camera 0 Color ROI 9 SUM Blue Register, array offset: 0xA4, array step: index*0x1A4, index2*0x18 */ } ROI[10]; uint8_t RESERVED_3[4]; __IO uint32_t GR_AVG_IN_CAM; /**< Camera 0 GR average input value, array offset: 0x184, array step: 0x1A4 */ __IO uint32_t GB_AVG_IN_CAM; /**< Camera 0 GB average input value, array offset: 0x188, array step: 0x1A4 */ __I uint32_t GR_GB_CNT_CAM; /**< Camera 0 Pixel count for the GR vs GB sums, array offset: 0x18C, array step: 0x1A4 */ __I int32_t GR_SUM_CAM; /**< Camera 0 Sum of counted GR values, array offset: 0x190, array step: 0x1A4 */ __I int32_t GB_SUM_CAM; /**< Camera 0 Sum of counted GB values, array offset: 0x194, array step: 0x1A4 */ __I uint32_t GR2_SUM_CAM; /**< Camera 0 Sum of squared GR values, array offset: 0x198, array step: 0x1A4 */ __I uint32_t GB2_SUM_CAM; /**< Camera 0 Sum of squared GB values, array offset: 0x19C, array step: 0x1A4 */ __I int32_t GRGB_SUM_CAM; /**< Camera 0 Sum of GR*GB values, array offset: 0x1A0, array step: 0x1A4 */ } PIPE1_COLORTEMP_CONF[1]; } COLOR_TEMP_Type; /* ---------------------------------------------------------------------------- -- COLOR_TEMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup COLOR_TEMP_Register_Masks COLOR_TEMP Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 COLORTEMP Control Register */ /*! @{ */ #define COLOR_TEMP_CTRL_CAM_IBPP_MASK (0x3U) #define COLOR_TEMP_CTRL_CAM_IBPP_SHIFT (0U) /*! IBPP * 0b00..12 bpp * 0b01..14 bpp * 0b10..16 bpp * 0b11..20 bpp */ #define COLOR_TEMP_CTRL_CAM_IBPP(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CTRL_CAM_IBPP_SHIFT)) & COLOR_TEMP_CTRL_CAM_IBPP_MASK) #define COLOR_TEMP_CTRL_CAM_CSCON_MASK (0x10U) #define COLOR_TEMP_CTRL_CAM_CSCON_SHIFT (4U) /*! CSCON * 0b0..No color space correction * 0b1..Perform color space correction */ #define COLOR_TEMP_CTRL_CAM_CSCON(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CTRL_CAM_CSCON_SHIFT)) & COLOR_TEMP_CTRL_CAM_CSCON_MASK) #define COLOR_TEMP_CTRL_CAM_ENABLE_MASK (0x80000000U) #define COLOR_TEMP_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..Disabled. The input pixels are left unchanged and passed unchanged to the color temperature output. * 0b1..Enabled */ #define COLOR_TEMP_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CTRL_CAM_ENABLE_SHIFT)) & COLOR_TEMP_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of COLOR_TEMP_CTRL_CAM */ #define COLOR_TEMP_CTRL_CAM_COUNT (1U) /*! @name ROI_POS_CAM - Camera 0 COLORTEMP Region of Interest Position Register */ /*! @{ */ #define COLOR_TEMP_ROI_POS_CAM_XPOS_MASK (0xFFFFU) #define COLOR_TEMP_ROI_POS_CAM_XPOS_SHIFT (0U) #define COLOR_TEMP_ROI_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_ROI_POS_CAM_XPOS_SHIFT)) & COLOR_TEMP_ROI_POS_CAM_XPOS_MASK) #define COLOR_TEMP_ROI_POS_CAM_YPOS_MASK (0xFFFF0000U) #define COLOR_TEMP_ROI_POS_CAM_YPOS_SHIFT (16U) #define COLOR_TEMP_ROI_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_ROI_POS_CAM_YPOS_SHIFT)) & COLOR_TEMP_ROI_POS_CAM_YPOS_MASK) /*! @} */ /* The count of COLOR_TEMP_ROI_POS_CAM */ #define COLOR_TEMP_ROI_POS_CAM_COUNT (1U) /*! @name ROI_SIZE_CAM - Camera 0 COLORTEMP Region of Interest Size Register */ /*! @{ */ #define COLOR_TEMP_ROI_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define COLOR_TEMP_ROI_SIZE_CAM_WIDTH_SHIFT (0U) #define COLOR_TEMP_ROI_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_ROI_SIZE_CAM_WIDTH_SHIFT)) & COLOR_TEMP_ROI_SIZE_CAM_WIDTH_MASK) #define COLOR_TEMP_ROI_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define COLOR_TEMP_ROI_SIZE_CAM_HEIGHT_SHIFT (16U) #define COLOR_TEMP_ROI_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_ROI_SIZE_CAM_HEIGHT_SHIFT)) & COLOR_TEMP_ROI_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of COLOR_TEMP_ROI_SIZE_CAM */ #define COLOR_TEMP_ROI_SIZE_CAM_COUNT (1U) /*! @name REDGAIN_CAM - Camera 0 COLORTEMP Red Gain Register */ /*! @{ */ #define COLOR_TEMP_REDGAIN_CAM_MIN_MASK (0xFFU) #define COLOR_TEMP_REDGAIN_CAM_MIN_SHIFT (0U) #define COLOR_TEMP_REDGAIN_CAM_MIN(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_REDGAIN_CAM_MIN_SHIFT)) & COLOR_TEMP_REDGAIN_CAM_MIN_MASK) #define COLOR_TEMP_REDGAIN_CAM_MAX_MASK (0xFF0000U) #define COLOR_TEMP_REDGAIN_CAM_MAX_SHIFT (16U) #define COLOR_TEMP_REDGAIN_CAM_MAX(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_REDGAIN_CAM_MAX_SHIFT)) & COLOR_TEMP_REDGAIN_CAM_MAX_MASK) /*! @} */ /* The count of COLOR_TEMP_REDGAIN_CAM */ #define COLOR_TEMP_REDGAIN_CAM_COUNT (1U) /*! @name BLUEGAIN_CAM - Camera 0 COLORTEMP Blue Gain Register */ /*! @{ */ #define COLOR_TEMP_BLUEGAIN_CAM_MIN_MASK (0xFFU) #define COLOR_TEMP_BLUEGAIN_CAM_MIN_SHIFT (0U) #define COLOR_TEMP_BLUEGAIN_CAM_MIN(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_BLUEGAIN_CAM_MIN_SHIFT)) & COLOR_TEMP_BLUEGAIN_CAM_MIN_MASK) #define COLOR_TEMP_BLUEGAIN_CAM_MAX_MASK (0xFF0000U) #define COLOR_TEMP_BLUEGAIN_CAM_MAX_SHIFT (16U) #define COLOR_TEMP_BLUEGAIN_CAM_MAX(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_BLUEGAIN_CAM_MAX_SHIFT)) & COLOR_TEMP_BLUEGAIN_CAM_MAX_MASK) /*! @} */ /* The count of COLOR_TEMP_BLUEGAIN_CAM */ #define COLOR_TEMP_BLUEGAIN_CAM_COUNT (1U) /*! @name POINT1_CAM - Camera 0 COLORTEMP Point1 Register */ /*! @{ */ #define COLOR_TEMP_POINT1_CAM_BLUE_MASK (0xFFU) #define COLOR_TEMP_POINT1_CAM_BLUE_SHIFT (0U) #define COLOR_TEMP_POINT1_CAM_BLUE(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT1_CAM_BLUE_SHIFT)) & COLOR_TEMP_POINT1_CAM_BLUE_MASK) #define COLOR_TEMP_POINT1_CAM_RED_MASK (0xFF0000U) #define COLOR_TEMP_POINT1_CAM_RED_SHIFT (16U) #define COLOR_TEMP_POINT1_CAM_RED(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT1_CAM_RED_SHIFT)) & COLOR_TEMP_POINT1_CAM_RED_MASK) /*! @} */ /* The count of COLOR_TEMP_POINT1_CAM */ #define COLOR_TEMP_POINT1_CAM_COUNT (1U) /*! @name POINT2_CAM - Camera 0 COLORTEMP Point2 Register */ /*! @{ */ #define COLOR_TEMP_POINT2_CAM_BLUE_MASK (0xFFU) #define COLOR_TEMP_POINT2_CAM_BLUE_SHIFT (0U) #define COLOR_TEMP_POINT2_CAM_BLUE(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT2_CAM_BLUE_SHIFT)) & COLOR_TEMP_POINT2_CAM_BLUE_MASK) #define COLOR_TEMP_POINT2_CAM_RED_MASK (0xFF0000U) #define COLOR_TEMP_POINT2_CAM_RED_SHIFT (16U) #define COLOR_TEMP_POINT2_CAM_RED(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT2_CAM_RED_SHIFT)) & COLOR_TEMP_POINT2_CAM_RED_MASK) /*! @} */ /* The count of COLOR_TEMP_POINT2_CAM */ #define COLOR_TEMP_POINT2_CAM_COUNT (1U) /*! @name HOFFSET_CAM - Camera 0 COLORTEMP Horizontal Offset Register */ /*! @{ */ #define COLOR_TEMP_HOFFSET_CAM_RIGHT_MASK (0xFFU) #define COLOR_TEMP_HOFFSET_CAM_RIGHT_SHIFT (0U) #define COLOR_TEMP_HOFFSET_CAM_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_HOFFSET_CAM_RIGHT_SHIFT)) & COLOR_TEMP_HOFFSET_CAM_RIGHT_MASK) #define COLOR_TEMP_HOFFSET_CAM_LEFT_MASK (0xFF0000U) #define COLOR_TEMP_HOFFSET_CAM_LEFT_SHIFT (16U) #define COLOR_TEMP_HOFFSET_CAM_LEFT(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_HOFFSET_CAM_LEFT_SHIFT)) & COLOR_TEMP_HOFFSET_CAM_LEFT_MASK) /*! @} */ /* The count of COLOR_TEMP_HOFFSET_CAM */ #define COLOR_TEMP_HOFFSET_CAM_COUNT (1U) /*! @name VOFFSET_CAM - Camera 0 COLORTEMP Vertical Offset Register */ /*! @{ */ #define COLOR_TEMP_VOFFSET_CAM_UP_MASK (0xFFU) #define COLOR_TEMP_VOFFSET_CAM_UP_SHIFT (0U) #define COLOR_TEMP_VOFFSET_CAM_UP(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_VOFFSET_CAM_UP_SHIFT)) & COLOR_TEMP_VOFFSET_CAM_UP_MASK) #define COLOR_TEMP_VOFFSET_CAM_DOWN_MASK (0xFF0000U) #define COLOR_TEMP_VOFFSET_CAM_DOWN_SHIFT (16U) #define COLOR_TEMP_VOFFSET_CAM_DOWN(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_VOFFSET_CAM_DOWN_SHIFT)) & COLOR_TEMP_VOFFSET_CAM_DOWN_MASK) /*! @} */ /* The count of COLOR_TEMP_VOFFSET_CAM */ #define COLOR_TEMP_VOFFSET_CAM_COUNT (1U) /*! @name POINT1_SLOPE_CAM - Camera 0 COLORTEMP Point 1 Slope Register */ /*! @{ */ #define COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_L_MASK (0xFFFFU) #define COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_L_SHIFT (0U) #define COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_L(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_L_SHIFT)) & COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_L_MASK) #define COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_R_MASK (0xFFFF0000U) #define COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_R_SHIFT (16U) #define COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_R(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_R_SHIFT)) & COLOR_TEMP_POINT1_SLOPE_CAM_SLOPE_R_MASK) /*! @} */ /* The count of COLOR_TEMP_POINT1_SLOPE_CAM */ #define COLOR_TEMP_POINT1_SLOPE_CAM_COUNT (1U) /*! @name POINT2_SLOPE_CAM - Camera 0 COLORTEMP Point 2 Slope Register */ /*! @{ */ #define COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_L_MASK (0xFFFFU) #define COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_L_SHIFT (0U) #define COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_L(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_L_SHIFT)) & COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_L_MASK) #define COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_R_MASK (0xFFFF0000U) #define COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_R_SHIFT (16U) #define COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_R(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_R_SHIFT)) & COLOR_TEMP_POINT2_SLOPE_CAM_SLOPE_R_MASK) /*! @} */ /* The count of COLOR_TEMP_POINT2_SLOPE_CAM */ #define COLOR_TEMP_POINT2_SLOPE_CAM_COUNT (1U) /*! @name LUMA_TH_CAM - Camera 0 COLORTEMP Luma Threshold Register */ /*! @{ */ #define COLOR_TEMP_LUMA_TH_CAM_THL_MASK (0xFFFFU) #define COLOR_TEMP_LUMA_TH_CAM_THL_SHIFT (0U) #define COLOR_TEMP_LUMA_TH_CAM_THL(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_LUMA_TH_CAM_THL_SHIFT)) & COLOR_TEMP_LUMA_TH_CAM_THL_MASK) #define COLOR_TEMP_LUMA_TH_CAM_THH_MASK (0xFFFF0000U) #define COLOR_TEMP_LUMA_TH_CAM_THH_SHIFT (16U) #define COLOR_TEMP_LUMA_TH_CAM_THH(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_LUMA_TH_CAM_THH_SHIFT)) & COLOR_TEMP_LUMA_TH_CAM_THH_MASK) /*! @} */ /* The count of COLOR_TEMP_LUMA_TH_CAM */ #define COLOR_TEMP_LUMA_TH_CAM_COUNT (1U) /*! @name CSC_MAT0_CAM - Camera 0 COLORTEMP Color Space Correction Matrix 0 Register */ /*! @{ */ #define COLOR_TEMP_CSC_MAT0_CAM_R0C0_MASK (0xFFFFU) #define COLOR_TEMP_CSC_MAT0_CAM_R0C0_SHIFT (0U) #define COLOR_TEMP_CSC_MAT0_CAM_R0C0(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT0_CAM_R0C0_SHIFT)) & COLOR_TEMP_CSC_MAT0_CAM_R0C0_MASK) #define COLOR_TEMP_CSC_MAT0_CAM_R0C1_MASK (0xFFFF0000U) #define COLOR_TEMP_CSC_MAT0_CAM_R0C1_SHIFT (16U) #define COLOR_TEMP_CSC_MAT0_CAM_R0C1(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT0_CAM_R0C1_SHIFT)) & COLOR_TEMP_CSC_MAT0_CAM_R0C1_MASK) /*! @} */ /* The count of COLOR_TEMP_CSC_MAT0_CAM */ #define COLOR_TEMP_CSC_MAT0_CAM_COUNT (1U) /*! @name CSC_MAT1_CAM - Camera 0 COLORTEMP Color Space Correction Matrix 1 Register */ /*! @{ */ #define COLOR_TEMP_CSC_MAT1_CAM_R0C2_MASK (0xFFFFU) #define COLOR_TEMP_CSC_MAT1_CAM_R0C2_SHIFT (0U) #define COLOR_TEMP_CSC_MAT1_CAM_R0C2(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT1_CAM_R0C2_SHIFT)) & COLOR_TEMP_CSC_MAT1_CAM_R0C2_MASK) #define COLOR_TEMP_CSC_MAT1_CAM_R1C0_MASK (0xFFFF0000U) #define COLOR_TEMP_CSC_MAT1_CAM_R1C0_SHIFT (16U) #define COLOR_TEMP_CSC_MAT1_CAM_R1C0(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT1_CAM_R1C0_SHIFT)) & COLOR_TEMP_CSC_MAT1_CAM_R1C0_MASK) /*! @} */ /* The count of COLOR_TEMP_CSC_MAT1_CAM */ #define COLOR_TEMP_CSC_MAT1_CAM_COUNT (1U) /*! @name CSC_MAT2_CAM - Camera 0 COLORTEMP Color Space Correction Matrix 2 Register */ /*! @{ */ #define COLOR_TEMP_CSC_MAT2_CAM_R1C1_MASK (0xFFFFU) #define COLOR_TEMP_CSC_MAT2_CAM_R1C1_SHIFT (0U) #define COLOR_TEMP_CSC_MAT2_CAM_R1C1(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT2_CAM_R1C1_SHIFT)) & COLOR_TEMP_CSC_MAT2_CAM_R1C1_MASK) #define COLOR_TEMP_CSC_MAT2_CAM_R1C2_MASK (0xFFFF0000U) #define COLOR_TEMP_CSC_MAT2_CAM_R1C2_SHIFT (16U) #define COLOR_TEMP_CSC_MAT2_CAM_R1C2(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT2_CAM_R1C2_SHIFT)) & COLOR_TEMP_CSC_MAT2_CAM_R1C2_MASK) /*! @} */ /* The count of COLOR_TEMP_CSC_MAT2_CAM */ #define COLOR_TEMP_CSC_MAT2_CAM_COUNT (1U) /*! @name CSC_MAT3_CAM - Camera 0 COLORTEMP Color Space Correction Matrix 3 Register */ /*! @{ */ #define COLOR_TEMP_CSC_MAT3_CAM_R2C0_MASK (0xFFFFU) #define COLOR_TEMP_CSC_MAT3_CAM_R2C0_SHIFT (0U) #define COLOR_TEMP_CSC_MAT3_CAM_R2C0(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT3_CAM_R2C0_SHIFT)) & COLOR_TEMP_CSC_MAT3_CAM_R2C0_MASK) #define COLOR_TEMP_CSC_MAT3_CAM_R2C1_MASK (0xFFFF0000U) #define COLOR_TEMP_CSC_MAT3_CAM_R2C1_SHIFT (16U) #define COLOR_TEMP_CSC_MAT3_CAM_R2C1(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT3_CAM_R2C1_SHIFT)) & COLOR_TEMP_CSC_MAT3_CAM_R2C1_MASK) /*! @} */ /* The count of COLOR_TEMP_CSC_MAT3_CAM */ #define COLOR_TEMP_CSC_MAT3_CAM_COUNT (1U) /*! @name CSC_MAT4_CAM - Camera 0 COLORTEMP Color Space Correction Matrix 4 Register */ /*! @{ */ #define COLOR_TEMP_CSC_MAT4_CAM_R2C2_MASK (0xFFFFU) #define COLOR_TEMP_CSC_MAT4_CAM_R2C2_SHIFT (0U) #define COLOR_TEMP_CSC_MAT4_CAM_R2C2(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CSC_MAT4_CAM_R2C2_SHIFT)) & COLOR_TEMP_CSC_MAT4_CAM_R2C2_MASK) /*! @} */ /* The count of COLOR_TEMP_CSC_MAT4_CAM */ #define COLOR_TEMP_CSC_MAT4_CAM_COUNT (1U) /*! @name R_GR_OFFSET_CAM - Camera 0 COLORTEMP R Gr Offset Register */ /*! @{ */ #define COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET0_MASK (0xFFFFU) #define COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET0_SHIFT (0U) #define COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET0_SHIFT)) & COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET0_MASK) #define COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET1_MASK (0xFFFF0000U) #define COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET1_SHIFT (16U) #define COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET1_SHIFT)) & COLOR_TEMP_R_GR_OFFSET_CAM_OFFSET1_MASK) /*! @} */ /* The count of COLOR_TEMP_R_GR_OFFSET_CAM */ #define COLOR_TEMP_R_GR_OFFSET_CAM_COUNT (1U) /*! @name GB_B_OFFSET_CAM - Camera 0 COLORTEMP Gb B Offset Register */ /*! @{ */ #define COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET0_MASK (0xFFFFU) #define COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET0_SHIFT (0U) #define COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET0_SHIFT)) & COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET0_MASK) #define COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET1_MASK (0xFFFF0000U) #define COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET1_SHIFT (16U) #define COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET1_SHIFT)) & COLOR_TEMP_GB_B_OFFSET_CAM_OFFSET1_MASK) /*! @} */ /* The count of COLOR_TEMP_GB_B_OFFSET_CAM */ #define COLOR_TEMP_GB_B_OFFSET_CAM_COUNT (1U) /*! @name CNT_WHITE_CAM - Camera 0 COLORTEMP White Count Register */ /*! @{ */ #define COLOR_TEMP_CNT_WHITE_CAM_WHITE_MASK (0xFFFFFFFFU) #define COLOR_TEMP_CNT_WHITE_CAM_WHITE_SHIFT (0U) #define COLOR_TEMP_CNT_WHITE_CAM_WHITE(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CNT_WHITE_CAM_WHITE_SHIFT)) & COLOR_TEMP_CNT_WHITE_CAM_WHITE_MASK) /*! @} */ /* The count of COLOR_TEMP_CNT_WHITE_CAM */ #define COLOR_TEMP_CNT_WHITE_CAM_COUNT (1U) /*! @name SUMRL_CAM - Camera 0 COLORTEMP Red Sum Low Register */ /*! @{ */ #define COLOR_TEMP_SUMRL_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMRL_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMRL_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMRL_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMRL_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMRL_CAM */ #define COLOR_TEMP_SUMRL_CAM_COUNT (1U) /*! @name SUMRH_CAM - Camera 0 COLORTEMP Red Sum High Register */ /*! @{ */ #define COLOR_TEMP_SUMRH_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMRH_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMRH_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMRH_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMRH_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMRH_CAM */ #define COLOR_TEMP_SUMRH_CAM_COUNT (1U) /*! @name SUMGL_CAM - Camera 0 COLORTEMP Green Sum Low Register */ /*! @{ */ #define COLOR_TEMP_SUMGL_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMGL_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMGL_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMGL_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMGL_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMGL_CAM */ #define COLOR_TEMP_SUMGL_CAM_COUNT (1U) /*! @name SUMGH_CAM - Camera 0 COLORTEMP Green Sum High Register */ /*! @{ */ #define COLOR_TEMP_SUMGH_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMGH_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMGH_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMGH_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMGH_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMGH_CAM */ #define COLOR_TEMP_SUMGH_CAM_COUNT (1U) /*! @name SUMBL_CAM - Camera 0 COLORTEMP Blue Sum Low Register */ /*! @{ */ #define COLOR_TEMP_SUMBL_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMBL_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMBL_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMBL_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMBL_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMBL_CAM */ #define COLOR_TEMP_SUMBL_CAM_COUNT (1U) /*! @name SUMBH_CAM - Camera 0 COLORTEMP Blue Sum High Register */ /*! @{ */ #define COLOR_TEMP_SUMBH_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMBH_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMBH_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMBH_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMBH_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMBH_CAM */ #define COLOR_TEMP_SUMBH_CAM_COUNT (1U) /*! @name SUMRGL_CAM - Camera 0 COLORTEMP R/G Sum Low Register */ /*! @{ */ #define COLOR_TEMP_SUMRGL_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMRGL_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMRGL_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMRGL_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMRGL_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMRGL_CAM */ #define COLOR_TEMP_SUMRGL_CAM_COUNT (1U) /*! @name SUMRGH_CAM - Camera 0 COLORTEMP R/G Sum High Register */ /*! @{ */ #define COLOR_TEMP_SUMRGH_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMRGH_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMRGH_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMRGH_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMRGH_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMRGH_CAM */ #define COLOR_TEMP_SUMRGH_CAM_COUNT (1U) /*! @name SUMBGL_CAM - Camera 0 COLORTEMP B/G Sum Low Register */ /*! @{ */ #define COLOR_TEMP_SUMBGL_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMBGL_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMBGL_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMBGL_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMBGL_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMBGL_CAM */ #define COLOR_TEMP_SUMBGL_CAM_COUNT (1U) /*! @name SUMBGH_CAM - Camera 0 COLORTEMP B/G Sum High Register */ /*! @{ */ #define COLOR_TEMP_SUMBGH_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_SUMBGH_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_SUMBGH_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_SUMBGH_CAM_SUM_SHIFT)) & COLOR_TEMP_SUMBGH_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_SUMBGH_CAM */ #define COLOR_TEMP_SUMBGH_CAM_COUNT (1U) /*! @name STAT_BLK_SIZE - Camera 0 COLORTEMP Statistics Block Size Register */ /*! @{ */ #define COLOR_TEMP_STAT_BLK_SIZE_XSIZE_MASK (0xFFFFU) #define COLOR_TEMP_STAT_BLK_SIZE_XSIZE_SHIFT (0U) #define COLOR_TEMP_STAT_BLK_SIZE_XSIZE(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_STAT_BLK_SIZE_XSIZE_SHIFT)) & COLOR_TEMP_STAT_BLK_SIZE_XSIZE_MASK) #define COLOR_TEMP_STAT_BLK_SIZE_YSIZE_MASK (0xFFFF0000U) #define COLOR_TEMP_STAT_BLK_SIZE_YSIZE_SHIFT (16U) #define COLOR_TEMP_STAT_BLK_SIZE_YSIZE(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_STAT_BLK_SIZE_YSIZE_SHIFT)) & COLOR_TEMP_STAT_BLK_SIZE_YSIZE_MASK) /*! @} */ /* The count of COLOR_TEMP_STAT_BLK_SIZE */ #define COLOR_TEMP_STAT_BLK_SIZE_COUNT (1U) /*! @name STAT_CURR_BLK_Y - Camera 0 COLORTEMP Statistics Block Y Status */ /*! @{ */ #define COLOR_TEMP_STAT_CURR_BLK_Y_BLKLNE_MASK (0xFFFFU) #define COLOR_TEMP_STAT_CURR_BLK_Y_BLKLNE_SHIFT (0U) #define COLOR_TEMP_STAT_CURR_BLK_Y_BLKLNE(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_STAT_CURR_BLK_Y_BLKLNE_SHIFT)) & COLOR_TEMP_STAT_CURR_BLK_Y_BLKLNE_MASK) #define COLOR_TEMP_STAT_CURR_BLK_Y_BLKROW_MASK (0x70000U) #define COLOR_TEMP_STAT_CURR_BLK_Y_BLKROW_SHIFT (16U) #define COLOR_TEMP_STAT_CURR_BLK_Y_BLKROW(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_STAT_CURR_BLK_Y_BLKROW_SHIFT)) & COLOR_TEMP_STAT_CURR_BLK_Y_BLKROW_MASK) /*! @} */ /* The count of COLOR_TEMP_STAT_CURR_BLK_Y */ #define COLOR_TEMP_STAT_CURR_BLK_Y_COUNT (1U) /*! @name CROI_POS_CAM - Camera 0 Color ROI 0 Position Register..Camera 0 Color ROI 9 Position Register */ /*! @{ */ #define COLOR_TEMP_CROI_POS_CAM_ROVERG_LOW_MASK (0xFFU) #define COLOR_TEMP_CROI_POS_CAM_ROVERG_LOW_SHIFT (0U) #define COLOR_TEMP_CROI_POS_CAM_ROVERG_LOW(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_POS_CAM_ROVERG_LOW_SHIFT)) & COLOR_TEMP_CROI_POS_CAM_ROVERG_LOW_MASK) #define COLOR_TEMP_CROI_POS_CAM_ROVERG_HIGH_MASK (0xFF00U) #define COLOR_TEMP_CROI_POS_CAM_ROVERG_HIGH_SHIFT (8U) #define COLOR_TEMP_CROI_POS_CAM_ROVERG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_POS_CAM_ROVERG_HIGH_SHIFT)) & COLOR_TEMP_CROI_POS_CAM_ROVERG_HIGH_MASK) #define COLOR_TEMP_CROI_POS_CAM_BOVERG_LOW_MASK (0xFF0000U) #define COLOR_TEMP_CROI_POS_CAM_BOVERG_LOW_SHIFT (16U) #define COLOR_TEMP_CROI_POS_CAM_BOVERG_LOW(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_POS_CAM_BOVERG_LOW_SHIFT)) & COLOR_TEMP_CROI_POS_CAM_BOVERG_LOW_MASK) #define COLOR_TEMP_CROI_POS_CAM_BOVERG_HIGH_MASK (0xFF000000U) #define COLOR_TEMP_CROI_POS_CAM_BOVERG_HIGH_SHIFT (24U) #define COLOR_TEMP_CROI_POS_CAM_BOVERG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_POS_CAM_BOVERG_HIGH_SHIFT)) & COLOR_TEMP_CROI_POS_CAM_BOVERG_HIGH_MASK) /*! @} */ /* The count of COLOR_TEMP_CROI_POS_CAM */ #define COLOR_TEMP_CROI_POS_CAM_COUNT (1U) /* The count of COLOR_TEMP_CROI_POS_CAM */ #define COLOR_TEMP_CROI_POS_CAM_COUNT2 (10U) /*! @name CROI_PIXCNT_CAM - Camera 0 Color ROI 0 Pixel Count Register..Camera 0 Color ROI 9 Pixel Count Register */ /*! @{ */ #define COLOR_TEMP_CROI_PIXCNT_CAM_PIXCNT_MASK (0xFFFFFFU) #define COLOR_TEMP_CROI_PIXCNT_CAM_PIXCNT_SHIFT (0U) #define COLOR_TEMP_CROI_PIXCNT_CAM_PIXCNT(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_PIXCNT_CAM_PIXCNT_SHIFT)) & COLOR_TEMP_CROI_PIXCNT_CAM_PIXCNT_MASK) /*! @} */ /* The count of COLOR_TEMP_CROI_PIXCNT_CAM */ #define COLOR_TEMP_CROI_PIXCNT_CAM_COUNT (1U) /* The count of COLOR_TEMP_CROI_PIXCNT_CAM */ #define COLOR_TEMP_CROI_PIXCNT_CAM_COUNT2 (10U) /*! @name CROI_SUMRED_CAM - Camera 0 Color ROI 0 SUM Red Register..Camera 0 Color ROI 9 SUM Red Register */ /*! @{ */ #define COLOR_TEMP_CROI_SUMRED_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_CROI_SUMRED_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_CROI_SUMRED_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_SUMRED_CAM_SUM_SHIFT)) & COLOR_TEMP_CROI_SUMRED_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_CROI_SUMRED_CAM */ #define COLOR_TEMP_CROI_SUMRED_CAM_COUNT (1U) /* The count of COLOR_TEMP_CROI_SUMRED_CAM */ #define COLOR_TEMP_CROI_SUMRED_CAM_COUNT2 (10U) /*! @name CROI_SUMGREEN_CAM - Camera 0 Color ROI 0 SUM Green Register..Camera 0 Color ROI 9 SUM Green Register */ /*! @{ */ #define COLOR_TEMP_CROI_SUMGREEN_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_CROI_SUMGREEN_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_CROI_SUMGREEN_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_SUMGREEN_CAM_SUM_SHIFT)) & COLOR_TEMP_CROI_SUMGREEN_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_CROI_SUMGREEN_CAM */ #define COLOR_TEMP_CROI_SUMGREEN_CAM_COUNT (1U) /* The count of COLOR_TEMP_CROI_SUMGREEN_CAM */ #define COLOR_TEMP_CROI_SUMGREEN_CAM_COUNT2 (10U) /*! @name CROI_SUMBLUE_CAM - Camera 0 Color ROI 0 SUM Blue Register..Camera 0 Color ROI 9 SUM Blue Register */ /*! @{ */ #define COLOR_TEMP_CROI_SUMBLUE_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_CROI_SUMBLUE_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_CROI_SUMBLUE_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_CROI_SUMBLUE_CAM_SUM_SHIFT)) & COLOR_TEMP_CROI_SUMBLUE_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_CROI_SUMBLUE_CAM */ #define COLOR_TEMP_CROI_SUMBLUE_CAM_COUNT (1U) /* The count of COLOR_TEMP_CROI_SUMBLUE_CAM */ #define COLOR_TEMP_CROI_SUMBLUE_CAM_COUNT2 (10U) /*! @name GR_AVG_IN_CAM - Camera 0 GR average input value */ /*! @{ */ #define COLOR_TEMP_GR_AVG_IN_CAM_GR_AGV_MASK (0xFFFFFU) #define COLOR_TEMP_GR_AVG_IN_CAM_GR_AGV_SHIFT (0U) #define COLOR_TEMP_GR_AVG_IN_CAM_GR_AGV(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GR_AVG_IN_CAM_GR_AGV_SHIFT)) & COLOR_TEMP_GR_AVG_IN_CAM_GR_AGV_MASK) /*! @} */ /* The count of COLOR_TEMP_GR_AVG_IN_CAM */ #define COLOR_TEMP_GR_AVG_IN_CAM_COUNT (1U) /*! @name GB_AVG_IN_CAM - Camera 0 GB average input value */ /*! @{ */ #define COLOR_TEMP_GB_AVG_IN_CAM_GB_AGV_MASK (0xFFFFFU) #define COLOR_TEMP_GB_AVG_IN_CAM_GB_AGV_SHIFT (0U) #define COLOR_TEMP_GB_AVG_IN_CAM_GB_AGV(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GB_AVG_IN_CAM_GB_AGV_SHIFT)) & COLOR_TEMP_GB_AVG_IN_CAM_GB_AGV_MASK) /*! @} */ /* The count of COLOR_TEMP_GB_AVG_IN_CAM */ #define COLOR_TEMP_GB_AVG_IN_CAM_COUNT (1U) /*! @name GR_GB_CNT_CAM - Camera 0 Pixel count for the GR vs GB sums */ /*! @{ */ #define COLOR_TEMP_GR_GB_CNT_CAM_CNT_MASK (0xFFFFFFFFU) #define COLOR_TEMP_GR_GB_CNT_CAM_CNT_SHIFT (0U) #define COLOR_TEMP_GR_GB_CNT_CAM_CNT(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GR_GB_CNT_CAM_CNT_SHIFT)) & COLOR_TEMP_GR_GB_CNT_CAM_CNT_MASK) /*! @} */ /* The count of COLOR_TEMP_GR_GB_CNT_CAM */ #define COLOR_TEMP_GR_GB_CNT_CAM_COUNT (1U) /*! @name GR_SUM_CAM - Camera 0 Sum of counted GR values */ /*! @{ */ #define COLOR_TEMP_GR_SUM_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_GR_SUM_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_GR_SUM_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GR_SUM_CAM_SUM_SHIFT)) & COLOR_TEMP_GR_SUM_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_GR_SUM_CAM */ #define COLOR_TEMP_GR_SUM_CAM_COUNT (1U) /*! @name GB_SUM_CAM - Camera 0 Sum of counted GB values */ /*! @{ */ #define COLOR_TEMP_GB_SUM_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_GB_SUM_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_GB_SUM_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GB_SUM_CAM_SUM_SHIFT)) & COLOR_TEMP_GB_SUM_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_GB_SUM_CAM */ #define COLOR_TEMP_GB_SUM_CAM_COUNT (1U) /*! @name GR2_SUM_CAM - Camera 0 Sum of squared GR values */ /*! @{ */ #define COLOR_TEMP_GR2_SUM_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_GR2_SUM_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_GR2_SUM_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GR2_SUM_CAM_SUM_SHIFT)) & COLOR_TEMP_GR2_SUM_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_GR2_SUM_CAM */ #define COLOR_TEMP_GR2_SUM_CAM_COUNT (1U) /*! @name GB2_SUM_CAM - Camera 0 Sum of squared GB values */ /*! @{ */ #define COLOR_TEMP_GB2_SUM_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_GB2_SUM_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_GB2_SUM_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GB2_SUM_CAM_SUM_SHIFT)) & COLOR_TEMP_GB2_SUM_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_GB2_SUM_CAM */ #define COLOR_TEMP_GB2_SUM_CAM_COUNT (1U) /*! @name GRGB_SUM_CAM - Camera 0 Sum of GR*GB values */ /*! @{ */ #define COLOR_TEMP_GRGB_SUM_CAM_SUM_MASK (0xFFFFFFFFU) #define COLOR_TEMP_GRGB_SUM_CAM_SUM_SHIFT (0U) #define COLOR_TEMP_GRGB_SUM_CAM_SUM(x) (((uint32_t)(((uint32_t)(x)) << COLOR_TEMP_GRGB_SUM_CAM_SUM_SHIFT)) & COLOR_TEMP_GRGB_SUM_CAM_SUM_MASK) /*! @} */ /* The count of COLOR_TEMP_GRGB_SUM_CAM */ #define COLOR_TEMP_GRGB_SUM_CAM_COUNT (1U) /*! * @} */ /* end of group COLOR_TEMP_Register_Masks */ /* COLOR_TEMP - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__COLOR_TEMP base address */ #define CAMERA__ISP__COLOR_TEMP_BASE (0x4AE00400u) /** Peripheral CAMERA__ISP__COLOR_TEMP base pointer */ #define CAMERA__ISP__COLOR_TEMP ((COLOR_TEMP_Type *)CAMERA__ISP__COLOR_TEMP_BASE) /** Array initializer of COLOR_TEMP peripheral base addresses */ #define COLOR_TEMP_BASE_ADDRS { CAMERA__ISP__COLOR_TEMP_BASE } /** Array initializer of COLOR_TEMP peripheral base pointers */ #define COLOR_TEMP_BASE_PTRS { CAMERA__ISP__COLOR_TEMP } /*! * @} */ /* end of group COLOR_TEMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CORTEXA_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CORTEXA_TCU_Peripheral_Access_Layer CORTEXA_TCU Peripheral Access Layer * @{ */ /** CORTEXA_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_3[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } CORTEXA_TCU_Type; /* ---------------------------------------------------------------------------- -- CORTEXA_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CORTEXA_TCU_Register_Masks CORTEXA_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & CORTEXA_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & CORTEXA_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define CORTEXA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define CORTEXA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define CORTEXA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & CORTEXA_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define CORTEXA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x3FEU) #define CORTEXA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define CORTEXA_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << CORTEXA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & CORTEXA_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group CORTEXA_TCU_Register_Masks */ /* CORTEXA_TCU - Peripheral instance base addresses */ /** Peripheral CORTEXA__TCU base address */ #define CORTEXA__TCU_BASE (0x4A400000u) /** Peripheral CORTEXA__TCU base pointer */ #define CORTEXA__TCU ((CORTEXA_TCU_Type *)CORTEXA__TCU_BASE) /** Array initializer of CORTEXA_TCU peripheral base addresses */ #define CORTEXA_TCU_BASE_ADDRS { CORTEXA__TCU_BASE } /** Array initializer of CORTEXA_TCU peripheral base pointers */ #define CORTEXA_TCU_BASE_PTRS { CORTEXA__TCU } /*! * @} */ /* end of group CORTEXA_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CSI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer * @{ */ /** CSI - Register Layout Typedef */ typedef struct { __I uint32_t VERSION; /**< Core version., offset: 0x0 */ __IO uint32_t N_LANES; /**< Number of lanes., offset: 0x4 */ __IO uint32_t CSI2_RESETN; /**< Logic Reset., offset: 0x8 */ __I uint32_t INT_ST_MAIN; /**< Main interrupt status., offset: 0xC */ __IO uint32_t DATA_IDS_1; /**< Data Type fields for Data ID Monitors 1., offset: 0x10 */ __IO uint32_t DATA_IDS_2; /**< Data Type fields for Data ID Monitors 2., offset: 0x14 */ uint8_t RESERVED_0[24]; __IO uint32_t DATA_IDS_VC_1; /**< Virtual Channel fields for Data ID Monitors 1., offset: 0x30 */ __IO uint32_t DATA_IDS_VC_2; /**< Virtual Channel fields for Data ID Monitors 2., offset: 0x34 */ uint8_t RESERVED_1[8]; __IO uint32_t PHY_SHUTDOWNZ; /**< PHY Shutdown., offset: 0x40 */ __IO uint32_t DPHY_RSTZ; /**< DPHY reset., offset: 0x44 */ __I uint32_t PHY_RX; /**< RX PHY status., offset: 0x48 */ __I uint32_t PHY_STOPSTATE; /**< STOPSTATE PHY status., offset: 0x4C */ __IO uint32_t PHY_TEST_CTRL0; /**< PHY Test and Control interface 0., offset: 0x50 */ __IO uint32_t PHY_TEST_CTRL1; /**< PHY Test and Control interface 1., offset: 0x54 */ uint8_t RESERVED_2[112]; __IO uint32_t VC_EXTENSION; /**< Virtual Channel Extension., offset: 0xC8 */ __I uint32_t PHY_CAL; /**< PHY Calibration., offset: 0xCC */ uint8_t RESERVED_3[16]; __I uint32_t INT_ST_PHY_FATAL; /**< Fatal interruption caused by PHY., offset: 0xE0 */ __IO uint32_t INT_MSK_PHY_FATAL; /**< Mask for fatal interruption caused by PHY., offset: 0xE4 */ __IO uint32_t INT_FORCE_PHY_FATAL; /**< Force for fatal interruption caused by PHY., offset: 0xE8 */ uint8_t RESERVED_4[4]; __I uint32_t INT_ST_PKT_FATAL; /**< Fatal interruption caused during Packet Construction., offset: 0xF0 */ __IO uint32_t INT_MSK_PKT_FATAL; /**< Mask for fatal interruption caused during Packet Construction., offset: 0xF4 */ __IO uint32_t INT_FORCE_PKT_FATAL; /**< Force for fatal interruption caused during Packet Construction., offset: 0xF8 */ uint8_t RESERVED_5[20]; __I uint32_t INT_ST_PHY; /**< Interruption caused by PHY., offset: 0x110 */ __IO uint32_t INT_MSK_PHY; /**< Mask for interruption caused by PHY., offset: 0x114 */ __IO uint32_t INT_FORCE_PHY; /**< Force for interruption caused by PHY., offset: 0x118 */ uint8_t RESERVED_6[20]; __I uint32_t INT_ST_LINE; /**< Interruption occurred during Line construction., offset: 0x130 */ __IO uint32_t INT_MSK_LINE; /**< Mask for interruption occurred during Line construction., offset: 0x134 */ __IO uint32_t INT_FORCE_LINE; /**< Force for interruption occurred during Line construction., offset: 0x138 */ uint8_t RESERVED_7[324]; __I uint32_t INT_ST_BNDRY_FRAME_FATAL; /**< Fatal Interruption caused by Frame Boundaries., offset: 0x280 */ __IO uint32_t INT_MSK_BNDRY_FRAME_FATAL; /**< Mask for fatal interruption caused by Frame Boundaries., offset: 0x284 */ __IO uint32_t INT_FORCE_BNDRY_FRAME_FATAL; /**< Force for fatal interruption caused by Frame Boundaries., offset: 0x288 */ uint8_t RESERVED_8[4]; __I uint32_t INT_ST_SEQ_FRAME_FATAL; /**< Fatal Interruption caused by Frame Sequence., offset: 0x290 */ __IO uint32_t INT_MSK_SEQ_FRAME_FATAL; /**< Mask for fatal interruption caused by Frame Sequence., offset: 0x294 */ __IO uint32_t INT_FORCE_SEQ_FRAME_FATAL; /**< Force for fatal interruption caused by Frame Sequence., offset: 0x298 */ uint8_t RESERVED_9[4]; __I uint32_t INT_ST_CRC_FRAME_FATAL; /**< Fatal Interruption caused by Frame CRC., offset: 0x2A0 */ __IO uint32_t INT_MSK_CRC_FRAME_FATAL; /**< Mask for fatal interruption caused by Frame CRC., offset: 0x2A4 */ __IO uint32_t INT_FORCE_CRC_FRAME_FATAL; /**< Force for fatal interruption caused by Frame CRC., offset: 0x2A8 */ uint8_t RESERVED_10[4]; __I uint32_t INT_ST_PLD_CRC_FATAL; /**< Fatal Interruption caused by Payload CRC., offset: 0x2B0 */ __IO uint32_t INT_MSK_PLD_CRC_FATAL; /**< Mask for fatal interruption caused by Payload CRC., offset: 0x2B4 */ __IO uint32_t INT_FORCE_PLD_CRC_FATAL; /**< Force for fatal interruption caused by Payload CRC., offset: 0x2B8 */ uint8_t RESERVED_11[4]; __I uint32_t INT_ST_DATA_ID; /**< Interruption caused by Data Type., offset: 0x2C0 */ __IO uint32_t INT_MSK_DATA_ID; /**< Mask for interruption caused by Data Type., offset: 0x2C4 */ __IO uint32_t INT_FORCE_DATA_ID; /**< Force for interruption caused by Data Type., offset: 0x2C8 */ uint8_t RESERVED_12[4]; __I uint32_t INT_ST_ECC_CORRECTED; /**< Interruption caused by Header single bit errors., offset: 0x2D0 */ __IO uint32_t INT_MSK_ECC_CORRECTED; /**< Mask for interruption caused by Header single bit errors., offset: 0x2D4 */ __IO uint32_t INT_FORCE_ECC_CORRECTED; /**< Force for interruption caused by Header single bit errors., offset: 0x2D8 */ uint8_t RESERVED_13[36]; __IO uint32_t SCRAMBLING; /**< Data De-Scrambling., offset: 0x300 */ __IO uint32_t SCRAMBLING_SEED1; /**< De-scrambler seed for lane1., offset: 0x304 */ __IO uint32_t SCRAMBLING_SEED2; /**< De-scrambler seed for lane2., offset: 0x308 */ __IO uint32_t SCRAMBLING_SEED3; /**< De-scrambler seed for lane3., offset: 0x30C */ __IO uint32_t SCRAMBLING_SEED4; /**< De-scrambler seed for lane4., offset: 0x310 */ } CSI_Type; /* ---------------------------------------------------------------------------- -- CSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CSI_Register_Masks CSI Register Masks * @{ */ /*! @name VERSION - Core version. */ /*! @{ */ #define CSI_VERSION_version_MASK (0xFFFFFFFFU) #define CSI_VERSION_version_SHIFT (0U) /*! version - This field indicates the version of the CSI-2 host controller. */ #define CSI_VERSION_version(x) (((uint32_t)(((uint32_t)(x)) << CSI_VERSION_version_SHIFT)) & CSI_VERSION_version_MASK) /*! @} */ /*! @name N_LANES - Number of lanes. */ /*! @{ */ #define CSI_N_LANES_n_lanes_MASK (0x7U) #define CSI_N_LANES_n_lanes_SHIFT (0U) /*! n_lanes - Number of active data lanes. * 0b000..1 Data Lane * 0b001..2 Data Lanes * 0b010..3 Data Lanes * 0b011..4 Data Lanes */ #define CSI_N_LANES_n_lanes(x) (((uint32_t)(((uint32_t)(x)) << CSI_N_LANES_n_lanes_SHIFT)) & CSI_N_LANES_n_lanes_MASK) /*! @} */ /*! @name CSI2_RESETN - Logic Reset. */ /*! @{ */ #define CSI_CSI2_RESETN_csi2_resetn_MASK (0x1U) #define CSI_CSI2_RESETN_csi2_resetn_SHIFT (0U) /*! csi2_resetn - CSI-2 host controller reset. * 0b0..Put the CSI-2 internal logic in the reset state. * 0b1..Release the CSI-2 internal logic from the reset state. */ #define CSI_CSI2_RESETN_csi2_resetn(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSI2_RESETN_csi2_resetn_SHIFT)) & CSI_CSI2_RESETN_csi2_resetn_MASK) /*! @} */ /*! @name INT_ST_MAIN - Main interrupt status. */ /*! @{ */ #define CSI_INT_ST_MAIN_status_int_st_phy_fatal_MASK (0x1U) #define CSI_INT_ST_MAIN_status_int_st_phy_fatal_SHIFT (0U) /*! status_int_st_phy_fatal - Status of int_st_phy_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PHY_FATAL is set. */ #define CSI_INT_ST_MAIN_status_int_st_phy_fatal(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_phy_fatal_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_phy_fatal_MASK) #define CSI_INT_ST_MAIN_status_int_st_pkt_fatal_MASK (0x2U) #define CSI_INT_ST_MAIN_status_int_st_pkt_fatal_SHIFT (1U) /*! status_int_st_pkt_fatal - Status of int_st_pkt_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PKT_FATAL is set. */ #define CSI_INT_ST_MAIN_status_int_st_pkt_fatal(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_pkt_fatal_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_pkt_fatal_MASK) #define CSI_INT_ST_MAIN_status_int_st_bndry_frame_fatal_MASK (0x4U) #define CSI_INT_ST_MAIN_status_int_st_bndry_frame_fatal_SHIFT (2U) /*! status_int_st_bndry_frame_fatal - Status of int_st_bndry_frame_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_BNDRY_FRAME_FATAL is set. */ #define CSI_INT_ST_MAIN_status_int_st_bndry_frame_fatal(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_bndry_frame_fatal_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_bndry_frame_fatal_MASK) #define CSI_INT_ST_MAIN_status_int_st_seq_frame_fatal_MASK (0x8U) #define CSI_INT_ST_MAIN_status_int_st_seq_frame_fatal_SHIFT (3U) /*! status_int_st_seq_frame_fatal - Status of int_st_seq_frame_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_SEQ_FRAME_FATAL is set. */ #define CSI_INT_ST_MAIN_status_int_st_seq_frame_fatal(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_seq_frame_fatal_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_seq_frame_fatal_MASK) #define CSI_INT_ST_MAIN_status_int_st_crc_frame_fatal_MASK (0x10U) #define CSI_INT_ST_MAIN_status_int_st_crc_frame_fatal_SHIFT (4U) /*! status_int_st_crc_frame_fatal - Status of int_st_crc_frame_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_CRC_FRAME_FATAL is set. */ #define CSI_INT_ST_MAIN_status_int_st_crc_frame_fatal(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_crc_frame_fatal_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_crc_frame_fatal_MASK) #define CSI_INT_ST_MAIN_status_int_st_pld_crc_fatal_MASK (0x20U) #define CSI_INT_ST_MAIN_status_int_st_pld_crc_fatal_SHIFT (5U) /*! status_int_st_pld_crc_fatal - Status of int_st_pld_crc_fatal. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PLD_CRC_FATAL is set. */ #define CSI_INT_ST_MAIN_status_int_st_pld_crc_fatal(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_pld_crc_fatal_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_pld_crc_fatal_MASK) #define CSI_INT_ST_MAIN_status_int_st_data_id_MASK (0x40U) #define CSI_INT_ST_MAIN_status_int_st_data_id_SHIFT (6U) /*! status_int_st_data_id - Status of int_st_data_id. * 0b0..No error. * 0b1..An interrupt source in INT_ST_DATA_ID is set. */ #define CSI_INT_ST_MAIN_status_int_st_data_id(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_data_id_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_data_id_MASK) #define CSI_INT_ST_MAIN_status_int_st_ecc_corrected_MASK (0x80U) #define CSI_INT_ST_MAIN_status_int_st_ecc_corrected_SHIFT (7U) /*! status_int_st_ecc_corrected - Status of int_st_ecc_corrected. * 0b0..No error. * 0b1..An interrupt source in INT_ST_ECC_CORRECTED is set. */ #define CSI_INT_ST_MAIN_status_int_st_ecc_corrected(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_ecc_corrected_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_ecc_corrected_MASK) #define CSI_INT_ST_MAIN_status_int_st_phy_MASK (0x10000U) #define CSI_INT_ST_MAIN_status_int_st_phy_SHIFT (16U) /*! status_int_st_phy - Status of int_st_phy. * 0b0..No error. * 0b1..An interrupt source in INT_ST_PHY is set. */ #define CSI_INT_ST_MAIN_status_int_st_phy(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_phy_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_phy_MASK) #define CSI_INT_ST_MAIN_status_int_st_line_MASK (0x20000U) #define CSI_INT_ST_MAIN_status_int_st_line_SHIFT (17U) /*! status_int_st_line - Status of int_st_line * 0b0..No error. * 0b1..An interrupt source in INT_ST_LINE is set. */ #define CSI_INT_ST_MAIN_status_int_st_line(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_MAIN_status_int_st_line_SHIFT)) & CSI_INT_ST_MAIN_status_int_st_line_MASK) /*! @} */ /*! @name DATA_IDS_1 - Data Type fields for Data ID Monitors 1. */ /*! @{ */ #define CSI_DATA_IDS_1_di0_dt_MASK (0x3FU) #define CSI_DATA_IDS_1_di0_dt_SHIFT (0U) /*! di0_dt - Data type for programmed data ID 0. */ #define CSI_DATA_IDS_1_di0_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_1_di0_dt_SHIFT)) & CSI_DATA_IDS_1_di0_dt_MASK) #define CSI_DATA_IDS_1_di1_dt_MASK (0x3F00U) #define CSI_DATA_IDS_1_di1_dt_SHIFT (8U) /*! di1_dt - Data type for programmed data ID 1. */ #define CSI_DATA_IDS_1_di1_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_1_di1_dt_SHIFT)) & CSI_DATA_IDS_1_di1_dt_MASK) #define CSI_DATA_IDS_1_di2_dt_MASK (0x3F0000U) #define CSI_DATA_IDS_1_di2_dt_SHIFT (16U) /*! di2_dt - Data type for programmed Data ID 2. */ #define CSI_DATA_IDS_1_di2_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_1_di2_dt_SHIFT)) & CSI_DATA_IDS_1_di2_dt_MASK) #define CSI_DATA_IDS_1_di3_dt_MASK (0x3F000000U) #define CSI_DATA_IDS_1_di3_dt_SHIFT (24U) /*! di3_dt - Data type for programmed data ID 3. */ #define CSI_DATA_IDS_1_di3_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_1_di3_dt_SHIFT)) & CSI_DATA_IDS_1_di3_dt_MASK) /*! @} */ /*! @name DATA_IDS_2 - Data Type fields for Data ID Monitors 2. */ /*! @{ */ #define CSI_DATA_IDS_2_di4_dt_MASK (0x3FU) #define CSI_DATA_IDS_2_di4_dt_SHIFT (0U) /*! di4_dt - Data type for programmed data ID 4. */ #define CSI_DATA_IDS_2_di4_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_2_di4_dt_SHIFT)) & CSI_DATA_IDS_2_di4_dt_MASK) #define CSI_DATA_IDS_2_di5_dt_MASK (0x3F00U) #define CSI_DATA_IDS_2_di5_dt_SHIFT (8U) /*! di5_dt - Data type for programmed data ID 5. */ #define CSI_DATA_IDS_2_di5_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_2_di5_dt_SHIFT)) & CSI_DATA_IDS_2_di5_dt_MASK) #define CSI_DATA_IDS_2_di6_dt_MASK (0x3F0000U) #define CSI_DATA_IDS_2_di6_dt_SHIFT (16U) /*! di6_dt - Data type for programmed data ID 6. */ #define CSI_DATA_IDS_2_di6_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_2_di6_dt_SHIFT)) & CSI_DATA_IDS_2_di6_dt_MASK) #define CSI_DATA_IDS_2_di7_dt_MASK (0x3F000000U) #define CSI_DATA_IDS_2_di7_dt_SHIFT (24U) /*! di7_dt - Data type for programmed data ID 7. */ #define CSI_DATA_IDS_2_di7_dt(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_2_di7_dt_SHIFT)) & CSI_DATA_IDS_2_di7_dt_MASK) /*! @} */ /*! @name DATA_IDS_VC_1 - Virtual Channel fields for Data ID Monitors 1. */ /*! @{ */ #define CSI_DATA_IDS_VC_1_di0_vc_MASK (0x3U) #define CSI_DATA_IDS_VC_1_di0_vc_SHIFT (0U) /*! di0_vc - Virtual channel for programmed data ID 0. */ #define CSI_DATA_IDS_VC_1_di0_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di0_vc_SHIFT)) & CSI_DATA_IDS_VC_1_di0_vc_MASK) #define CSI_DATA_IDS_VC_1_di0_vcx_0_1_MASK (0xCU) #define CSI_DATA_IDS_VC_1_di0_vcx_0_1_SHIFT (2U) /*! di0_vcx_0_1 - Virtual channel extension for programmed data ID 0. */ #define CSI_DATA_IDS_VC_1_di0_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di0_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_1_di0_vcx_0_1_MASK) #define CSI_DATA_IDS_VC_1_di1_vc_MASK (0x300U) #define CSI_DATA_IDS_VC_1_di1_vc_SHIFT (8U) /*! di1_vc - Virtual channel for programmed data ID 1. */ #define CSI_DATA_IDS_VC_1_di1_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di1_vc_SHIFT)) & CSI_DATA_IDS_VC_1_di1_vc_MASK) #define CSI_DATA_IDS_VC_1_di1_vcx_0_1_MASK (0xC00U) #define CSI_DATA_IDS_VC_1_di1_vcx_0_1_SHIFT (10U) /*! di1_vcx_0_1 - Virtual channel extension for programmed data ID 1. */ #define CSI_DATA_IDS_VC_1_di1_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di1_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_1_di1_vcx_0_1_MASK) #define CSI_DATA_IDS_VC_1_di2_vc_MASK (0x30000U) #define CSI_DATA_IDS_VC_1_di2_vc_SHIFT (16U) /*! di2_vc - Virtual channel for programmed data ID 2. */ #define CSI_DATA_IDS_VC_1_di2_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di2_vc_SHIFT)) & CSI_DATA_IDS_VC_1_di2_vc_MASK) #define CSI_DATA_IDS_VC_1_di2_vcx_0_1_MASK (0xC0000U) #define CSI_DATA_IDS_VC_1_di2_vcx_0_1_SHIFT (18U) /*! di2_vcx_0_1 - Virtual channel extension for programmed data ID 2. */ #define CSI_DATA_IDS_VC_1_di2_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di2_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_1_di2_vcx_0_1_MASK) #define CSI_DATA_IDS_VC_1_di3_vc_MASK (0x3000000U) #define CSI_DATA_IDS_VC_1_di3_vc_SHIFT (24U) /*! di3_vc - Virtual channel for programmed data ID 3. */ #define CSI_DATA_IDS_VC_1_di3_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di3_vc_SHIFT)) & CSI_DATA_IDS_VC_1_di3_vc_MASK) #define CSI_DATA_IDS_VC_1_di3_vcx_0_1_MASK (0xC000000U) #define CSI_DATA_IDS_VC_1_di3_vcx_0_1_SHIFT (26U) /*! di3_vcx_0_1 - Virtual channel extension for programmed data ID 3. */ #define CSI_DATA_IDS_VC_1_di3_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_1_di3_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_1_di3_vcx_0_1_MASK) /*! @} */ /*! @name DATA_IDS_VC_2 - Virtual Channel fields for Data ID Monitors 2. */ /*! @{ */ #define CSI_DATA_IDS_VC_2_di4_vc_MASK (0x3U) #define CSI_DATA_IDS_VC_2_di4_vc_SHIFT (0U) /*! di4_vc - Virtual channel for programmed data ID 4. */ #define CSI_DATA_IDS_VC_2_di4_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di4_vc_SHIFT)) & CSI_DATA_IDS_VC_2_di4_vc_MASK) #define CSI_DATA_IDS_VC_2_di4_vcx_0_1_MASK (0xCU) #define CSI_DATA_IDS_VC_2_di4_vcx_0_1_SHIFT (2U) /*! di4_vcx_0_1 - Virtual channel extension for programmed data ID 4. */ #define CSI_DATA_IDS_VC_2_di4_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di4_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_2_di4_vcx_0_1_MASK) #define CSI_DATA_IDS_VC_2_di5_vc_MASK (0x300U) #define CSI_DATA_IDS_VC_2_di5_vc_SHIFT (8U) /*! di5_vc - Virtual channel for programmed data ID 5. */ #define CSI_DATA_IDS_VC_2_di5_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di5_vc_SHIFT)) & CSI_DATA_IDS_VC_2_di5_vc_MASK) #define CSI_DATA_IDS_VC_2_di5_vcx_0_1_MASK (0xC00U) #define CSI_DATA_IDS_VC_2_di5_vcx_0_1_SHIFT (10U) /*! di5_vcx_0_1 - Virtual channel extension for programmed data ID 5. */ #define CSI_DATA_IDS_VC_2_di5_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di5_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_2_di5_vcx_0_1_MASK) #define CSI_DATA_IDS_VC_2_di6_vc_MASK (0x30000U) #define CSI_DATA_IDS_VC_2_di6_vc_SHIFT (16U) /*! di6_vc - Virtual channel for programmed data ID 6. */ #define CSI_DATA_IDS_VC_2_di6_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di6_vc_SHIFT)) & CSI_DATA_IDS_VC_2_di6_vc_MASK) #define CSI_DATA_IDS_VC_2_di6_vcx_0_1_MASK (0xC0000U) #define CSI_DATA_IDS_VC_2_di6_vcx_0_1_SHIFT (18U) /*! di6_vcx_0_1 - Virtual channel extension for programmed data ID 6. */ #define CSI_DATA_IDS_VC_2_di6_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di6_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_2_di6_vcx_0_1_MASK) #define CSI_DATA_IDS_VC_2_di7_vc_MASK (0x3000000U) #define CSI_DATA_IDS_VC_2_di7_vc_SHIFT (24U) /*! di7_vc - Virtual channel for programmed data ID 7. */ #define CSI_DATA_IDS_VC_2_di7_vc(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di7_vc_SHIFT)) & CSI_DATA_IDS_VC_2_di7_vc_MASK) #define CSI_DATA_IDS_VC_2_di7_vcx_0_1_MASK (0xC000000U) #define CSI_DATA_IDS_VC_2_di7_vcx_0_1_SHIFT (26U) /*! di7_vcx_0_1 - Virtual channel extension for programmed data ID 7. */ #define CSI_DATA_IDS_VC_2_di7_vcx_0_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DATA_IDS_VC_2_di7_vcx_0_1_SHIFT)) & CSI_DATA_IDS_VC_2_di7_vcx_0_1_MASK) /*! @} */ /*! @name PHY_SHUTDOWNZ - PHY Shutdown. */ /*! @{ */ #define CSI_PHY_SHUTDOWNZ_phy_shutdownz_MASK (0x1U) #define CSI_PHY_SHUTDOWNZ_phy_shutdownz_SHIFT (0U) /*! phy_shutdownz - Shutdown input. * 0b0..Enter power down mode. * 0b1..Exit from power down mode. */ #define CSI_PHY_SHUTDOWNZ_phy_shutdownz(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_SHUTDOWNZ_phy_shutdownz_SHIFT)) & CSI_PHY_SHUTDOWNZ_phy_shutdownz_MASK) /*! @} */ /*! @name DPHY_RSTZ - DPHY reset. */ /*! @{ */ #define CSI_DPHY_RSTZ_dphy_rstz_MASK (0x1U) #define CSI_DPHY_RSTZ_dphy_rstz_SHIFT (0U) /*! dphy_rstz - PHY reset. * 0b0..Put PHY in reset. * 0b1..Release PHY from reset. */ #define CSI_DPHY_RSTZ_dphy_rstz(x) (((uint32_t)(((uint32_t)(x)) << CSI_DPHY_RSTZ_dphy_rstz_SHIFT)) & CSI_DPHY_RSTZ_dphy_rstz_MASK) /*! @} */ /*! @name PHY_RX - RX PHY status. */ /*! @{ */ #define CSI_PHY_RX_phy_rxulpsesc_0_MASK (0x1U) #define CSI_PHY_RX_phy_rxulpsesc_0_SHIFT (0U) /*! phy_rxulpsesc_0 - Lane module 0 has entered the Ultra Low Power mode. * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CSI_PHY_RX_phy_rxulpsesc_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_RX_phy_rxulpsesc_0_SHIFT)) & CSI_PHY_RX_phy_rxulpsesc_0_MASK) #define CSI_PHY_RX_phy_rxulpsesc_1_MASK (0x2U) #define CSI_PHY_RX_phy_rxulpsesc_1_SHIFT (1U) /*! phy_rxulpsesc_1 - Lane module 1 has entered the Ultra Low Power mode * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CSI_PHY_RX_phy_rxulpsesc_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_RX_phy_rxulpsesc_1_SHIFT)) & CSI_PHY_RX_phy_rxulpsesc_1_MASK) #define CSI_PHY_RX_phy_rxulpsesc_2_MASK (0x4U) #define CSI_PHY_RX_phy_rxulpsesc_2_SHIFT (2U) /*! phy_rxulpsesc_2 - Lane module 2 has entered the Ultra Low Power mode * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CSI_PHY_RX_phy_rxulpsesc_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_RX_phy_rxulpsesc_2_SHIFT)) & CSI_PHY_RX_phy_rxulpsesc_2_MASK) #define CSI_PHY_RX_phy_rxulpsesc_3_MASK (0x8U) #define CSI_PHY_RX_phy_rxulpsesc_3_SHIFT (3U) /*! phy_rxulpsesc_3 - Lane module 3 has entered the Ultra Low Power mode * 0b0..Data lane is not in ULPM. * 0b1..Data lane has entered ULPM. */ #define CSI_PHY_RX_phy_rxulpsesc_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_RX_phy_rxulpsesc_3_SHIFT)) & CSI_PHY_RX_phy_rxulpsesc_3_MASK) #define CSI_PHY_RX_phy_rxulpsclknot_MASK (0x10000U) #define CSI_PHY_RX_phy_rxulpsclknot_SHIFT (16U) /*! phy_rxulpsclknot - Indicates that D-PHY Clock Lane module has entered the Ultra Low Power state. * 0b0..Clock lane is detected in ULPM. * 0b1..Clock lane is not in ULPM. */ #define CSI_PHY_RX_phy_rxulpsclknot(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_RX_phy_rxulpsclknot_SHIFT)) & CSI_PHY_RX_phy_rxulpsclknot_MASK) #define CSI_PHY_RX_phy_rxclkactivehs_MASK (0x20000U) #define CSI_PHY_RX_phy_rxclkactivehs_SHIFT (17U) /*! phy_rxclkactivehs - Indicates that D-PHY clock lane is actively receiving a DDR clock * 0b0..No clock signal is received in the clock lane. * 0b1..High-speed clock signal is received in clock lane. */ #define CSI_PHY_RX_phy_rxclkactivehs(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_RX_phy_rxclkactivehs_SHIFT)) & CSI_PHY_RX_phy_rxclkactivehs_MASK) /*! @} */ /*! @name PHY_STOPSTATE - STOPSTATE PHY status. */ /*! @{ */ #define CSI_PHY_STOPSTATE_phy_stopstatedata_0_MASK (0x1U) #define CSI_PHY_STOPSTATE_phy_stopstatedata_0_SHIFT (0U) /*! phy_stopstatedata_0 - Data lane 0 in Stop state. * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CSI_PHY_STOPSTATE_phy_stopstatedata_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_STOPSTATE_phy_stopstatedata_0_SHIFT)) & CSI_PHY_STOPSTATE_phy_stopstatedata_0_MASK) #define CSI_PHY_STOPSTATE_phy_stopstatedata_1_MASK (0x2U) #define CSI_PHY_STOPSTATE_phy_stopstatedata_1_SHIFT (1U) /*! phy_stopstatedata_1 - Data lane 1 in Stop state * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CSI_PHY_STOPSTATE_phy_stopstatedata_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_STOPSTATE_phy_stopstatedata_1_SHIFT)) & CSI_PHY_STOPSTATE_phy_stopstatedata_1_MASK) #define CSI_PHY_STOPSTATE_phy_stopstatedata_2_MASK (0x4U) #define CSI_PHY_STOPSTATE_phy_stopstatedata_2_SHIFT (2U) /*! phy_stopstatedata_2 - Data lane 2 in Stop state * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CSI_PHY_STOPSTATE_phy_stopstatedata_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_STOPSTATE_phy_stopstatedata_2_SHIFT)) & CSI_PHY_STOPSTATE_phy_stopstatedata_2_MASK) #define CSI_PHY_STOPSTATE_phy_stopstatedata_3_MASK (0x8U) #define CSI_PHY_STOPSTATE_phy_stopstatedata_3_SHIFT (3U) /*! phy_stopstatedata_3 - Data lane 3 in Stop state * 0b0..Data lane is not in Stop state. * 0b1..Data lane is in Stop state. */ #define CSI_PHY_STOPSTATE_phy_stopstatedata_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_STOPSTATE_phy_stopstatedata_3_SHIFT)) & CSI_PHY_STOPSTATE_phy_stopstatedata_3_MASK) #define CSI_PHY_STOPSTATE_phy_stopstateclk_MASK (0x10000U) #define CSI_PHY_STOPSTATE_phy_stopstateclk_SHIFT (16U) /*! phy_stopstateclk - D-PHY Clock lane in Stop state * 0b0..Clock lane is not in Stop state. * 0b1..Clock lane is in Stop state. */ #define CSI_PHY_STOPSTATE_phy_stopstateclk(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_STOPSTATE_phy_stopstateclk_SHIFT)) & CSI_PHY_STOPSTATE_phy_stopstateclk_MASK) /*! @} */ /*! @name PHY_TEST_CTRL0 - PHY Test and Control interface 0. */ /*! @{ */ #define CSI_PHY_TEST_CTRL0_phy_testclr_MASK (0x1U) #define CSI_PHY_TEST_CTRL0_phy_testclr_SHIFT (0U) /*! phy_testclr - When active, performs vendor specific interface initialization. */ #define CSI_PHY_TEST_CTRL0_phy_testclr(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_TEST_CTRL0_phy_testclr_SHIFT)) & CSI_PHY_TEST_CTRL0_phy_testclr_MASK) #define CSI_PHY_TEST_CTRL0_phy_testclk_MASK (0x2U) #define CSI_PHY_TEST_CTRL0_phy_testclk_SHIFT (1U) /*! phy_testclk - Clock to capture testdin bus contents into the macro, with testen signal controlling the operation selection. */ #define CSI_PHY_TEST_CTRL0_phy_testclk(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_TEST_CTRL0_phy_testclk_SHIFT)) & CSI_PHY_TEST_CTRL0_phy_testclk_MASK) /*! @} */ /*! @name PHY_TEST_CTRL1 - PHY Test and Control interface 1. */ /*! @{ */ #define CSI_PHY_TEST_CTRL1_phy_testdin_MASK (0xFFU) #define CSI_PHY_TEST_CTRL1_phy_testdin_SHIFT (0U) /*! phy_testdin - Test interface 8-bit data input for programming internal registers and accessing test functionalities. */ #define CSI_PHY_TEST_CTRL1_phy_testdin(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_TEST_CTRL1_phy_testdin_SHIFT)) & CSI_PHY_TEST_CTRL1_phy_testdin_MASK) #define CSI_PHY_TEST_CTRL1_phy_testdout_MASK (0xFF00U) #define CSI_PHY_TEST_CTRL1_phy_testdout_SHIFT (8U) /*! phy_testdout - Vendor-specific 8-bit data output for reading data and other probing functionalities. */ #define CSI_PHY_TEST_CTRL1_phy_testdout(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_TEST_CTRL1_phy_testdout_SHIFT)) & CSI_PHY_TEST_CTRL1_phy_testdout_MASK) #define CSI_PHY_TEST_CTRL1_phy_testen_MASK (0x10000U) #define CSI_PHY_TEST_CTRL1_phy_testen_SHIFT (16U) /*! phy_testen - Data write on the rising edge of TESTCLK or address write on the falling edge of TESTCLK * 0b0..Configures a data write operation on the rising edge of TESTCLK. * 0b1..Configures an address write operation on the falling edge of TESTCLK */ #define CSI_PHY_TEST_CTRL1_phy_testen(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_TEST_CTRL1_phy_testen_SHIFT)) & CSI_PHY_TEST_CTRL1_phy_testen_MASK) /*! @} */ /*! @name VC_EXTENSION - Virtual Channel Extension. */ /*! @{ */ #define CSI_VC_EXTENSION_vcx_MASK (0x1U) #define CSI_VC_EXTENSION_vcx_SHIFT (0U) /*! vcx - Virtual channel extension * 0b0..Virtual channel extension is enabled. * 0b1..Legacy mode. Virtual channel extension is disabled. */ #define CSI_VC_EXTENSION_vcx(x) (((uint32_t)(((uint32_t)(x)) << CSI_VC_EXTENSION_vcx_SHIFT)) & CSI_VC_EXTENSION_vcx_MASK) /*! @} */ /*! @name PHY_CAL - PHY Calibration. */ /*! @{ */ #define CSI_PHY_CAL_rxskewcalhs_MASK (0x1U) #define CSI_PHY_CAL_rxskewcalhs_SHIFT (0U) /*! rxskewcalhs - A low-to-high transition on rxskewcalhs signal means that the PHY has initiated the de-skew calibration. * 0b0..No calibration. * 0b1..PHY has initiated the de-skew calibration. */ #define CSI_PHY_CAL_rxskewcalhs(x) (((uint32_t)(((uint32_t)(x)) << CSI_PHY_CAL_rxskewcalhs_SHIFT)) & CSI_PHY_CAL_rxskewcalhs_MASK) /*! @} */ /*! @name INT_ST_PHY_FATAL - Fatal interruption caused by PHY. */ /*! @{ */ #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_0_MASK (0x1U) #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_0_SHIFT (0U) /*! phy_errsotsynchs_0 - Start of transmission error on data lane 0 (no synchronization achieved). * 0b0..No error * 0b1..Start of transmission error on data lane 0 */ #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_0_SHIFT)) & CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_0_MASK) #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_1_MASK (0x2U) #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_1_SHIFT (1U) /*! phy_errsotsynchs_1 - Start of transmission error on data lane 1 (no synchronization achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 1 */ #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_1_SHIFT)) & CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_1_MASK) #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_2_MASK (0x4U) #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_2_SHIFT (2U) /*! phy_errsotsynchs_2 - Start of transmission error on data lane 2 (no synchronization achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 2 */ #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_2_SHIFT)) & CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_2_MASK) #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_3_MASK (0x8U) #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_3_SHIFT (3U) /*! phy_errsotsynchs_3 - Start of transmission error on data lane 3 (no synchronization achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 3 */ #define CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_3_SHIFT)) & CSI_INT_ST_PHY_FATAL_phy_errsotsynchs_3_MASK) /*! @} */ /*! @name INT_MSK_PHY_FATAL - Mask for fatal interruption caused by PHY. */ /*! @{ */ #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_MASK (0x1U) #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_SHIFT (0U) /*! mask_phy_errsotsynchs_0 - Mask for phy_errsotsynchs_0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_SHIFT)) & CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_0_MASK) #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_MASK (0x2U) #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_SHIFT (1U) /*! mask_phy_errsotsynchs_1 - Mask for phy_errsotsynchs_1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_SHIFT)) & CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_1_MASK) #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_MASK (0x4U) #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_SHIFT (2U) /*! mask_phy_errsotsynchs_2 - Mask for phy_errsotsynchs_2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_SHIFT)) & CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_2_MASK) #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_MASK (0x8U) #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_SHIFT (3U) /*! mask_phy_errsotsynchs_3 - Mask for phy_errsotsynchs_3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_SHIFT)) & CSI_INT_MSK_PHY_FATAL_mask_phy_errsotsynchs_3_MASK) /*! @} */ /*! @name INT_FORCE_PHY_FATAL - Force for fatal interruption caused by PHY. */ /*! @{ */ #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_MASK (0x1U) #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_SHIFT (0U) /*! force_phy_errsotsynchs_0 - Force phy_errsotsynchs_0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_SHIFT)) & CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_0_MASK) #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_MASK (0x2U) #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_SHIFT (1U) /*! force_phy_errsotsynchs_1 - Force phy_errsotsynchs_1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_SHIFT)) & CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_1_MASK) #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_MASK (0x4U) #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_SHIFT (2U) /*! force_phy_errsotsynchs_2 - Force phy_errsotsynchs_2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_SHIFT)) & CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_2_MASK) #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_MASK (0x8U) #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_SHIFT (3U) /*! force_phy_errsotsynchs_3 - Force phy_errsotsynchs_3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_SHIFT)) & CSI_INT_FORCE_PHY_FATAL_force_phy_errsotsynchs_3_MASK) /*! @} */ /*! @name INT_ST_PKT_FATAL - Fatal interruption caused during Packet Construction. */ /*! @{ */ #define CSI_INT_ST_PKT_FATAL_err_ecc_double_MASK (0x1U) #define CSI_INT_ST_PKT_FATAL_err_ecc_double_SHIFT (0U) /*! err_ecc_double - D-PHY mode: Header ECC contains at least 2 errors, unrecoverable. * 0b0..No error. * 0b1..Header ECC contains at least 2 errors, unrecoverable. */ #define CSI_INT_ST_PKT_FATAL_err_ecc_double(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PKT_FATAL_err_ecc_double_SHIFT)) & CSI_INT_ST_PKT_FATAL_err_ecc_double_MASK) #define CSI_INT_ST_PKT_FATAL_shorter_payload_MASK (0x2U) #define CSI_INT_ST_PKT_FATAL_shorter_payload_SHIFT (1U) /*! shorter_payload - D-PHY mode: Reported greater WC than received, unrecoverable. * 0b0..No error. * 0b1..Reported greater Word Count than received, unrecoverable. */ #define CSI_INT_ST_PKT_FATAL_shorter_payload(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PKT_FATAL_shorter_payload_SHIFT)) & CSI_INT_ST_PKT_FATAL_shorter_payload_MASK) /*! @} */ /*! @name INT_MSK_PKT_FATAL - Mask for fatal interruption caused during Packet Construction. */ /*! @{ */ #define CSI_INT_MSK_PKT_FATAL_mask_err_ecc_double_MASK (0x1U) #define CSI_INT_MSK_PKT_FATAL_mask_err_ecc_double_SHIFT (0U) /*! mask_err_ecc_double - Mask for err_ecc_double. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PKT_FATAL_mask_err_ecc_double(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PKT_FATAL_mask_err_ecc_double_SHIFT)) & CSI_INT_MSK_PKT_FATAL_mask_err_ecc_double_MASK) #define CSI_INT_MSK_PKT_FATAL_mask_shorter_payload_MASK (0x2U) #define CSI_INT_MSK_PKT_FATAL_mask_shorter_payload_SHIFT (1U) /*! mask_shorter_payload - Mask for shorter_payload. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PKT_FATAL_mask_shorter_payload(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PKT_FATAL_mask_shorter_payload_SHIFT)) & CSI_INT_MSK_PKT_FATAL_mask_shorter_payload_MASK) /*! @} */ /*! @name INT_FORCE_PKT_FATAL - Force for fatal interruption caused during Packet Construction. */ /*! @{ */ #define CSI_INT_FORCE_PKT_FATAL_force_err_ecc_double_MASK (0x1U) #define CSI_INT_FORCE_PKT_FATAL_force_err_ecc_double_SHIFT (0U) /*! force_err_ecc_double - Force err_ecc_double. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PKT_FATAL_force_err_ecc_double(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PKT_FATAL_force_err_ecc_double_SHIFT)) & CSI_INT_FORCE_PKT_FATAL_force_err_ecc_double_MASK) #define CSI_INT_FORCE_PKT_FATAL_force_shorter_payload_MASK (0x2U) #define CSI_INT_FORCE_PKT_FATAL_force_shorter_payload_SHIFT (1U) /*! force_shorter_payload - Force shorter_payload. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PKT_FATAL_force_shorter_payload(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PKT_FATAL_force_shorter_payload_SHIFT)) & CSI_INT_FORCE_PKT_FATAL_force_shorter_payload_MASK) /*! @} */ /*! @name INT_ST_PHY - Interruption caused by PHY. */ /*! @{ */ #define CSI_INT_ST_PHY_phy_errsoths_0_MASK (0x1U) #define CSI_INT_ST_PHY_phy_errsoths_0_SHIFT (0U) /*! phy_errsoths_0 - Start of transmission error on data lane 0 (synchronization can still be achieved). * 0b0..No error * 0b1..Start of transmission error on data lane 0 */ #define CSI_INT_ST_PHY_phy_errsoths_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_errsoths_0_SHIFT)) & CSI_INT_ST_PHY_phy_errsoths_0_MASK) #define CSI_INT_ST_PHY_phy_errsoths_1_MASK (0x2U) #define CSI_INT_ST_PHY_phy_errsoths_1_SHIFT (1U) /*! phy_errsoths_1 - Start of transmission error on data lane 1 (synchronization can still be achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 1 */ #define CSI_INT_ST_PHY_phy_errsoths_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_errsoths_1_SHIFT)) & CSI_INT_ST_PHY_phy_errsoths_1_MASK) #define CSI_INT_ST_PHY_phy_errsoths_2_MASK (0x4U) #define CSI_INT_ST_PHY_phy_errsoths_2_SHIFT (2U) /*! phy_errsoths_2 - Start of transmission error on data lane 2 (synchronization can still be achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 2 */ #define CSI_INT_ST_PHY_phy_errsoths_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_errsoths_2_SHIFT)) & CSI_INT_ST_PHY_phy_errsoths_2_MASK) #define CSI_INT_ST_PHY_phy_errsoths_3_MASK (0x8U) #define CSI_INT_ST_PHY_phy_errsoths_3_SHIFT (3U) /*! phy_errsoths_3 - Start of transmission error on data lane 3 (synchronization can still be achieved) * 0b0..No error * 0b1..Start of transmission error on data lane 3 */ #define CSI_INT_ST_PHY_phy_errsoths_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_errsoths_3_SHIFT)) & CSI_INT_ST_PHY_phy_errsoths_3_MASK) #define CSI_INT_ST_PHY_phy_erresc_0_MASK (0x10000U) #define CSI_INT_ST_PHY_phy_erresc_0_SHIFT (16U) /*! phy_erresc_0 - Escape Entry Error on data lane 0. * 0b1..Escape entry error on data lane 0 * 0b0..No error */ #define CSI_INT_ST_PHY_phy_erresc_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_erresc_0_SHIFT)) & CSI_INT_ST_PHY_phy_erresc_0_MASK) #define CSI_INT_ST_PHY_phy_erresc_1_MASK (0x20000U) #define CSI_INT_ST_PHY_phy_erresc_1_SHIFT (17U) /*! phy_erresc_1 - Escape Entry Error on data lane 1 * 0b0..No error * 0b1..Escape entry error on data lane 1 */ #define CSI_INT_ST_PHY_phy_erresc_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_erresc_1_SHIFT)) & CSI_INT_ST_PHY_phy_erresc_1_MASK) #define CSI_INT_ST_PHY_phy_erresc_2_MASK (0x40000U) #define CSI_INT_ST_PHY_phy_erresc_2_SHIFT (18U) /*! phy_erresc_2 - Escape Entry Error on data lane 2 * 0b0..No error * 0b1..Escape entry error on data lane 2 */ #define CSI_INT_ST_PHY_phy_erresc_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_erresc_2_SHIFT)) & CSI_INT_ST_PHY_phy_erresc_2_MASK) #define CSI_INT_ST_PHY_phy_erresc_3_MASK (0x80000U) #define CSI_INT_ST_PHY_phy_erresc_3_SHIFT (19U) /*! phy_erresc_3 - Escape Entry Error on data lane 3 * 0b0..No error * 0b1..Escape entry error on data lane 3 */ #define CSI_INT_ST_PHY_phy_erresc_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PHY_phy_erresc_3_SHIFT)) & CSI_INT_ST_PHY_phy_erresc_3_MASK) /*! @} */ /*! @name INT_MSK_PHY - Mask for interruption caused by PHY. */ /*! @{ */ #define CSI_INT_MSK_PHY_mask_phy_errsoths_0_MASK (0x1U) #define CSI_INT_MSK_PHY_mask_phy_errsoths_0_SHIFT (0U) /*! mask_phy_errsoths_0 - Mask for phy_errsoths_0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_mask_phy_errsoths_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_errsoths_0_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_errsoths_0_MASK) #define CSI_INT_MSK_PHY_mask_phy_errsoths_1_MASK (0x2U) #define CSI_INT_MSK_PHY_mask_phy_errsoths_1_SHIFT (1U) /*! mask_phy_errsoths_1 - Mask for phy_errsoths_1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_mask_phy_errsoths_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_errsoths_1_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_errsoths_1_MASK) #define CSI_INT_MSK_PHY_mask_phy_errsoths_2_MASK (0x4U) #define CSI_INT_MSK_PHY_mask_phy_errsoths_2_SHIFT (2U) /*! mask_phy_errsoths_2 - Mask for phy_errsoths_2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_mask_phy_errsoths_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_errsoths_2_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_errsoths_2_MASK) #define CSI_INT_MSK_PHY_mask_phy_errsoths_3_MASK (0x8U) #define CSI_INT_MSK_PHY_mask_phy_errsoths_3_SHIFT (3U) /*! mask_phy_errsoths_3 - Mask for phy_errsoths_3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_mask_phy_errsoths_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_errsoths_3_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_errsoths_3_MASK) #define CSI_INT_MSK_PHY_mask_phy_erresc_0_MASK (0x10000U) #define CSI_INT_MSK_PHY_mask_phy_erresc_0_SHIFT (16U) /*! mask_phy_erresc_0 - Mask for phy_erresc_0. * 0b1..Enable the interrupt source. * 0b0..Interrupt source is masked. */ #define CSI_INT_MSK_PHY_mask_phy_erresc_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_erresc_0_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_erresc_0_MASK) #define CSI_INT_MSK_PHY_mask_phy_erresc_1_MASK (0x20000U) #define CSI_INT_MSK_PHY_mask_phy_erresc_1_SHIFT (17U) /*! mask_phy_erresc_1 - Mask for phy_erresc_1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_mask_phy_erresc_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_erresc_1_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_erresc_1_MASK) #define CSI_INT_MSK_PHY_mask_phy_erresc_2_MASK (0x40000U) #define CSI_INT_MSK_PHY_mask_phy_erresc_2_SHIFT (18U) /*! mask_phy_erresc_2 - Mask for phy_erresc_2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_mask_phy_erresc_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_erresc_2_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_erresc_2_MASK) #define CSI_INT_MSK_PHY_mask_phy_erresc_3_MASK (0x80000U) #define CSI_INT_MSK_PHY_mask_phy_erresc_3_SHIFT (19U) /*! mask_phy_erresc_3 - Mask for phy_erresc_3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PHY_mask_phy_erresc_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PHY_mask_phy_erresc_3_SHIFT)) & CSI_INT_MSK_PHY_mask_phy_erresc_3_MASK) /*! @} */ /*! @name INT_FORCE_PHY - Force for interruption caused by PHY. */ /*! @{ */ #define CSI_INT_FORCE_PHY_force_phy_errsoths_0_MASK (0x1U) #define CSI_INT_FORCE_PHY_force_phy_errsoths_0_SHIFT (0U) /*! force_phy_errsoths_0 - Force phy_errsoths_0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_errsoths_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_errsoths_0_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_errsoths_0_MASK) #define CSI_INT_FORCE_PHY_force_phy_errsoths_1_MASK (0x2U) #define CSI_INT_FORCE_PHY_force_phy_errsoths_1_SHIFT (1U) /*! force_phy_errsoths_1 - Force phy_errsoths_1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_errsoths_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_errsoths_1_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_errsoths_1_MASK) #define CSI_INT_FORCE_PHY_force_phy_errsoths_2_MASK (0x4U) #define CSI_INT_FORCE_PHY_force_phy_errsoths_2_SHIFT (2U) /*! force_phy_errsoths_2 - Force phy_errsoths_2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_errsoths_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_errsoths_2_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_errsoths_2_MASK) #define CSI_INT_FORCE_PHY_force_phy_errsoths_3_MASK (0x8U) #define CSI_INT_FORCE_PHY_force_phy_errsoths_3_SHIFT (3U) /*! force_phy_errsoths_3 - Force phy_errsoths_3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_errsoths_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_errsoths_3_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_errsoths_3_MASK) #define CSI_INT_FORCE_PHY_force_phy_erresc_0_MASK (0x10000U) #define CSI_INT_FORCE_PHY_force_phy_erresc_0_SHIFT (16U) /*! force_phy_erresc_0 - Force phy_erresc_0 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_erresc_0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_erresc_0_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_erresc_0_MASK) #define CSI_INT_FORCE_PHY_force_phy_erresc_1_MASK (0x20000U) #define CSI_INT_FORCE_PHY_force_phy_erresc_1_SHIFT (17U) /*! force_phy_erresc_1 - Force phy_erresc_1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_erresc_1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_erresc_1_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_erresc_1_MASK) #define CSI_INT_FORCE_PHY_force_phy_erresc_2_MASK (0x40000U) #define CSI_INT_FORCE_PHY_force_phy_erresc_2_SHIFT (18U) /*! force_phy_erresc_2 - Force phy_erresc_2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_erresc_2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_erresc_2_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_erresc_2_MASK) #define CSI_INT_FORCE_PHY_force_phy_erresc_3_MASK (0x80000U) #define CSI_INT_FORCE_PHY_force_phy_erresc_3_SHIFT (19U) /*! force_phy_erresc_3 - Force phy_erresc_3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PHY_force_phy_erresc_3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PHY_force_phy_erresc_3_SHIFT)) & CSI_INT_FORCE_PHY_force_phy_erresc_3_MASK) /*! @} */ /*! @name INT_ST_LINE - Interruption occurred during Line construction. */ /*! @{ */ #define CSI_INT_ST_LINE_err_l_bndry_match_di0_MASK (0x1U) #define CSI_INT_ST_LINE_err_l_bndry_match_di0_SHIFT (0U) /*! err_l_bndry_match_di0 - Error matching line start with line end for vc0 and dt0 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di0_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di0_MASK) #define CSI_INT_ST_LINE_err_l_bndry_match_di1_MASK (0x2U) #define CSI_INT_ST_LINE_err_l_bndry_match_di1_SHIFT (1U) /*! err_l_bndry_match_di1 - Error matching line start with line end for vc1 and dt1 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di1_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di1_MASK) #define CSI_INT_ST_LINE_err_l_bndry_match_di2_MASK (0x4U) #define CSI_INT_ST_LINE_err_l_bndry_match_di2_SHIFT (2U) /*! err_l_bndry_match_di2 - Error matching line start with line end for vc2 and dt2 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di2_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di2_MASK) #define CSI_INT_ST_LINE_err_l_bndry_match_di3_MASK (0x8U) #define CSI_INT_ST_LINE_err_l_bndry_match_di3_SHIFT (3U) /*! err_l_bndry_match_di3 - Error matching line start with line end for vc3 and dt3 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di3_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di3_MASK) #define CSI_INT_ST_LINE_err_l_bndry_match_di4_MASK (0x10U) #define CSI_INT_ST_LINE_err_l_bndry_match_di4_SHIFT (4U) /*! err_l_bndry_match_di4 - Error matching line start with line end for vc4 and dt4 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di4_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di4_MASK) #define CSI_INT_ST_LINE_err_l_bndry_match_di5_MASK (0x20U) #define CSI_INT_ST_LINE_err_l_bndry_match_di5_SHIFT (5U) /*! err_l_bndry_match_di5 - Error matching line start with line end for vc5 and dt5 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di5_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di5_MASK) #define CSI_INT_ST_LINE_err_l_bndry_match_di6_MASK (0x40U) #define CSI_INT_ST_LINE_err_l_bndry_match_di6_SHIFT (6U) /*! err_l_bndry_match_di6 - Error matching line start with line end for vc6 and dt6 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di6_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di6_MASK) #define CSI_INT_ST_LINE_err_l_bndry_match_di7_MASK (0x80U) #define CSI_INT_ST_LINE_err_l_bndry_match_di7_SHIFT (7U) /*! err_l_bndry_match_di7 - Error matching line start with line end for vc7 and dt7 * 0b0..No error. * 0b1..Line start and line end mismatch error occurred. */ #define CSI_INT_ST_LINE_err_l_bndry_match_di7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_bndry_match_di7_SHIFT)) & CSI_INT_ST_LINE_err_l_bndry_match_di7_MASK) #define CSI_INT_ST_LINE_err_l_seq_di0_MASK (0x10000U) #define CSI_INT_ST_LINE_err_l_seq_di0_SHIFT (16U) /*! err_l_seq_di0 - Error in the sequence of lines for vc0 and dt0 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di0_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di0_MASK) #define CSI_INT_ST_LINE_err_l_seq_di1_MASK (0x20000U) #define CSI_INT_ST_LINE_err_l_seq_di1_SHIFT (17U) /*! err_l_seq_di1 - Error in the sequence of lines for vc1 and dt1 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di1_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di1_MASK) #define CSI_INT_ST_LINE_err_l_seq_di2_MASK (0x40000U) #define CSI_INT_ST_LINE_err_l_seq_di2_SHIFT (18U) /*! err_l_seq_di2 - Error in the sequence of lines for vc2 and dt2 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di2_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di2_MASK) #define CSI_INT_ST_LINE_err_l_seq_di3_MASK (0x80000U) #define CSI_INT_ST_LINE_err_l_seq_di3_SHIFT (19U) /*! err_l_seq_di3 - Error in the sequence of lines for vc3 and dt3 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di3_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di3_MASK) #define CSI_INT_ST_LINE_err_l_seq_di4_MASK (0x100000U) #define CSI_INT_ST_LINE_err_l_seq_di4_SHIFT (20U) /*! err_l_seq_di4 - Error in the sequence of lines for vc4 and dt4 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di4_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di4_MASK) #define CSI_INT_ST_LINE_err_l_seq_di5_MASK (0x200000U) #define CSI_INT_ST_LINE_err_l_seq_di5_SHIFT (21U) /*! err_l_seq_di5 - Error in the sequence of lines for vc5 and dt5 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di5_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di5_MASK) #define CSI_INT_ST_LINE_err_l_seq_di6_MASK (0x400000U) #define CSI_INT_ST_LINE_err_l_seq_di6_SHIFT (22U) /*! err_l_seq_di6 - Error in the sequence of lines for vc6 and dt6 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di6_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di6_MASK) #define CSI_INT_ST_LINE_err_l_seq_di7_MASK (0x800000U) #define CSI_INT_ST_LINE_err_l_seq_di7_SHIFT (23U) /*! err_l_seq_di7 - Error in the sequence of lines for vc7 and dt7 * 0b0..No error. * 0b1..Line sequence error occurred. */ #define CSI_INT_ST_LINE_err_l_seq_di7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_LINE_err_l_seq_di7_SHIFT)) & CSI_INT_ST_LINE_err_l_seq_di7_MASK) /*! @} */ /*! @name INT_MSK_LINE - Mask for interruption occurred during Line construction. */ /*! @{ */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di0_MASK (0x1U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di0_SHIFT (0U) /*! mask_err_l_bndry_match_di0 - Mask for err_l_bndry_match_di0 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di0_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di0_MASK) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di1_MASK (0x2U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di1_SHIFT (1U) /*! mask_err_l_bndry_match_di1 - Mask for err_l_bndry_match_di1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di1_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di1_MASK) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di2_MASK (0x4U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di2_SHIFT (2U) /*! mask_err_l_bndry_match_di2 - Mask for err_l_bndry_match_di2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di2_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di2_MASK) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di3_MASK (0x8U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di3_SHIFT (3U) /*! mask_err_l_bndry_match_di3 - Mask for err_l_bndry_match_di3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di3_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di3_MASK) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di4_MASK (0x10U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di4_SHIFT (4U) /*! mask_err_l_bndry_match_di4 - Mask for err_l_bndry_match_di4 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di4_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di4_MASK) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di5_MASK (0x20U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di5_SHIFT (5U) /*! mask_err_l_bndry_match_di5 - Mask for err_l_bndry_match_di5 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di5_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di5_MASK) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di6_MASK (0x40U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di6_SHIFT (6U) /*! mask_err_l_bndry_match_di6 - Mask for err_l_bndry_match_di6 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di6_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di6_MASK) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di7_MASK (0x80U) #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di7_SHIFT (7U) /*! mask_err_l_bndry_match_di7 - Mask for err_l_bndry_match_di7 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_bndry_match_di7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_bndry_match_di7_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_bndry_match_di7_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di0_MASK (0x10000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di0_SHIFT (16U) /*! mask_err_l_seq_di0 - Mask for err_l_seq_di0 * 0b1..Enable the interrupt source. * 0b0..Interrupt source is masked. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di0_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di0_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di1_MASK (0x20000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di1_SHIFT (17U) /*! mask_err_l_seq_di1 - Mask for err_l_seq_di1 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di1_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di1_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di2_MASK (0x40000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di2_SHIFT (18U) /*! mask_err_l_seq_di2 - Mask for err_l_seq_di2 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di2_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di2_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di3_MASK (0x80000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di3_SHIFT (19U) /*! mask_err_l_seq_di3 - Mask for err_l_seq_di3 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di3_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di3_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di4_MASK (0x100000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di4_SHIFT (20U) /*! mask_err_l_seq_di4 - Mask for err_l_seq_di4 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di4_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di4_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di5_MASK (0x200000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di5_SHIFT (21U) /*! mask_err_l_seq_di5 - Mask for err_l_seq_di5 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di5_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di5_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di6_MASK (0x400000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di6_SHIFT (22U) /*! mask_err_l_seq_di6 - Mask for err_l_seq_di6 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di6_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di6_MASK) #define CSI_INT_MSK_LINE_mask_err_l_seq_di7_MASK (0x800000U) #define CSI_INT_MSK_LINE_mask_err_l_seq_di7_SHIFT (23U) /*! mask_err_l_seq_di7 - Mask for err_l_seq_di7 * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_LINE_mask_err_l_seq_di7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_LINE_mask_err_l_seq_di7_SHIFT)) & CSI_INT_MSK_LINE_mask_err_l_seq_di7_MASK) /*! @} */ /*! @name INT_FORCE_LINE - Force for interruption occurred during Line construction. */ /*! @{ */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di0_MASK (0x1U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di0_SHIFT (0U) /*! force_err_l_bndry_match_di0 - Force err_l_bndry_match_di0 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di0_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di0_MASK) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di1_MASK (0x2U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di1_SHIFT (1U) /*! force_err_l_bndry_match_di1 - Force err_l_bndry_match_di1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di1_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di1_MASK) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di2_MASK (0x4U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di2_SHIFT (2U) /*! force_err_l_bndry_match_di2 - Force err_l_bndry_match_di2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di2_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di2_MASK) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di3_MASK (0x8U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di3_SHIFT (3U) /*! force_err_l_bndry_match_di3 - Force err_l_bndry_match_di3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di3_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di3_MASK) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di4_MASK (0x10U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di4_SHIFT (4U) /*! force_err_l_bndry_match_di4 - Force err_l_bndry_match_di4 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di4_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di4_MASK) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di5_MASK (0x20U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di5_SHIFT (5U) /*! force_err_l_bndry_match_di5 - Force err_l_bndry_match_di5 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di5_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di5_MASK) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di6_MASK (0x40U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di6_SHIFT (6U) /*! force_err_l_bndry_match_di6 - Force err_l_bndry_match_di6 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di6_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di6_MASK) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di7_MASK (0x80U) #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di7_SHIFT (7U) /*! force_err_l_bndry_match_di7 - Force err_l_bndry_match_di7 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_bndry_match_di7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_bndry_match_di7_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_bndry_match_di7_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di0_MASK (0x10000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di0_SHIFT (16U) /*! force_err_l_seq_di0 - Force err_l_seq_di0 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di0_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di0_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di1_MASK (0x20000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di1_SHIFT (17U) /*! force_err_l_seq_di1 - Force err_l_seq_di1 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di1_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di1_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di2_MASK (0x40000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di2_SHIFT (18U) /*! force_err_l_seq_di2 - Force err_l_seq_di2 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di2_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di2_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di3_MASK (0x80000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di3_SHIFT (19U) /*! force_err_l_seq_di3 - Force err_l_seq_di3 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di3_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di3_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di4_MASK (0x100000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di4_SHIFT (20U) /*! force_err_l_seq_di4 - Force err_l_seq_di4 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di4_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di4_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di5_MASK (0x200000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di5_SHIFT (21U) /*! force_err_l_seq_di5 - Force err_l_seq_di5 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di5_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di5_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di6_MASK (0x400000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di6_SHIFT (22U) /*! force_err_l_seq_di6 - Force err_l_seq_di6 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di6_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di6_MASK) #define CSI_INT_FORCE_LINE_force_err_l_seq_di7_MASK (0x800000U) #define CSI_INT_FORCE_LINE_force_err_l_seq_di7_SHIFT (23U) /*! force_err_l_seq_di7 - Force err_l_seq_di7 * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_LINE_force_err_l_seq_di7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_LINE_force_err_l_seq_di7_SHIFT)) & CSI_INT_FORCE_LINE_force_err_l_seq_di7_MASK) /*! @} */ /*! @name INT_ST_BNDRY_FRAME_FATAL - Fatal Interruption caused by Frame Boundaries. */ /*! @{ */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK (0x1U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT (0U) /*! err_f_bndry_match_vc0 - Error matching Frame Start with Frame End for virtual channel 0. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK (0x2U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT (1U) /*! err_f_bndry_match_vc1 - Error matching Frame Start with Frame End for virtual channel 1. * 0b0..No error. * 0b1..Matching frame start with frame end error is detected. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK (0x4U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT (2U) /*! err_f_bndry_match_vc2 - Error matching Frame Start with Frame End for virtual channel 2. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK (0x8U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT (3U) /*! err_f_bndry_match_vc3 - Error matching Frame Start with Frame End for virtual channel 3. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK (0x10U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT (4U) /*! err_f_bndry_match_vc4 - Error matching Frame Start with Frame End for virtual channel 4. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK (0x20U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT (5U) /*! err_f_bndry_match_vc5 - Error matching Frame Start with Frame End for virtual channel 5. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK (0x40U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT (6U) /*! err_f_bndry_match_vc6 - Error matching Frame Start with Frame End for virtual channel 6. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK (0x80U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT (7U) /*! err_f_bndry_match_vc7 - Error matching Frame Start with Frame End for virtual channel 7. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK (0x100U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT (8U) /*! err_f_bndry_match_vc8 - Error matching Frame Start with Frame End for virtual channel 8. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK (0x200U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT (9U) /*! err_f_bndry_match_vc9 - Error matching Frame Start with Frame End for virtual channel 9. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK (0x400U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT (10U) /*! err_f_bndry_match_vc10 - Error matching Frame Start with Frame End for virtual channel 10. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK (0x800U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT (11U) /*! err_f_bndry_match_vc11 - Error matching Frame Start with Frame End for virtual channel 11. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK (0x1000U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT (12U) /*! err_f_bndry_match_vc12 - Error matching Frame Start with Frame End for virtual channel 12. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK (0x2000U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT (13U) /*! err_f_bndry_match_vc13 - Error matching Frame Start with Frame End for virtual channel 13. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK (0x4000U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT (14U) /*! err_f_bndry_match_vc14 - Error matching Frame Start with Frame End for virtual channel 14. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK (0x8000U) #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT (15U) /*! err_f_bndry_match_vc15 - Error matching Frame Start with Frame End for virtual channel 15. * 0b1..Matching frame start with frame end error is detected. * 0b0..No error. */ #define CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT)) & CSI_INT_ST_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK) /*! @} */ /*! @name INT_MSK_BNDRY_FRAME_FATAL - Mask for fatal interruption caused by Frame Boundaries. */ /*! @{ */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK (0x1U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT (0U) /*! err_f_bndry_match_vc0 - Mask for err_f_bndry_match_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK (0x2U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT (1U) /*! err_f_bndry_match_vc1 - Mask for err_f_bndry_match_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK (0x4U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT (2U) /*! err_f_bndry_match_vc2 - Mask for err_f_bndry_match_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK (0x8U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT (3U) /*! err_f_bndry_match_vc3 - Mask for err_f_bndry_match_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK (0x10U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT (4U) /*! err_f_bndry_match_vc4 - Mask for err_f_bndry_match_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK (0x20U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT (5U) /*! err_f_bndry_match_vc5 - Mask for err_f_bndry_match_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK (0x40U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT (6U) /*! err_f_bndry_match_vc6 - Mask for err_f_bndry_match_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK (0x80U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT (7U) /*! err_f_bndry_match_vc7 - Mask for err_f_bndry_match_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK (0x100U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT (8U) /*! err_f_bndry_match_vc8 - Mask for err_f_bndry_match_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK (0x200U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT (9U) /*! err_f_bndry_match_vc9 - Mask for err_f_bndry_match_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK (0x400U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT (10U) /*! err_f_bndry_match_vc10 - Mask for err_f_bndry_match_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK (0x800U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT (11U) /*! err_f_bndry_match_vc11 - Mask for err_f_bndry_match_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK (0x1000U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT (12U) /*! err_f_bndry_match_vc12 - Mask for err_f_bndry_match_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK (0x2000U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT (13U) /*! err_f_bndry_match_vc13 - Mask for err_f_bndry_match_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK (0x4000U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT (14U) /*! err_f_bndry_match_vc14 - Mask for err_f_bndry_match_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK (0x8000U) #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT (15U) /*! err_f_bndry_match_vc15 - Mask for err_f_bndry_match_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT)) & CSI_INT_MSK_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK) /*! @} */ /*! @name INT_FORCE_BNDRY_FRAME_FATAL - Force for fatal interruption caused by Frame Boundaries. */ /*! @{ */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK (0x1U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT (0U) /*! err_f_bndry_match_vc0 - Force err_f_bndry_match_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc0_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK (0x2U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT (1U) /*! err_f_bndry_match_vc1 - Force err_f_bndry_match_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc1_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK (0x4U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT (2U) /*! err_f_bndry_match_vc2 - Force err_f_bndry_match_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc2_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK (0x8U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT (3U) /*! err_f_bndry_match_vc3 - Force err_f_bndry_match_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc3_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK (0x10U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT (4U) /*! err_f_bndry_match_vc4 - Force err_f_bndry_match_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc4_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK (0x20U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT (5U) /*! err_f_bndry_match_vc5 - Force err_f_bndry_match_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc5_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK (0x40U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT (6U) /*! err_f_bndry_match_vc6 - Force err_f_bndry_match_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc6_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK (0x80U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT (7U) /*! err_f_bndry_match_vc7 - Force err_f_bndry_match_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc7_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK (0x100U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT (8U) /*! err_f_bndry_match_vc8 - Force err_f_bndry_match_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc8_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK (0x200U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT (9U) /*! err_f_bndry_match_vc9 - Force err_f_bndry_match_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc9_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK (0x400U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT (10U) /*! err_f_bndry_match_vc10 - Force err_f_bndry_match_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc10_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK (0x800U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT (11U) /*! err_f_bndry_match_vc11 - Force err_f_bndry_match_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc11_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK (0x1000U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT (12U) /*! err_f_bndry_match_vc12 - Force err_f_bndry_match_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc12_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK (0x2000U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT (13U) /*! err_f_bndry_match_vc13 - Force err_f_bndry_match_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc13_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK (0x4000U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT (14U) /*! err_f_bndry_match_vc14 - Force err_f_bndry_match_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc14_MASK) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK (0x8000U) #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT (15U) /*! err_f_bndry_match_vc15 - Force err_f_bndry_match_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_SHIFT)) & CSI_INT_FORCE_BNDRY_FRAME_FATAL_err_f_bndry_match_vc15_MASK) /*! @} */ /*! @name INT_ST_SEQ_FRAME_FATAL - Fatal Interruption caused by Frame Sequence. */ /*! @{ */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK (0x1U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT (0U) /*! err_f_seq_vc0 - Incorrect Frame sequence detected in virtual channel 0. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK (0x2U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT (1U) /*! err_f_seq_vc1 - Incorrect Frame sequence detected in virtual channel 1. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK (0x4U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT (2U) /*! err_f_seq_vc2 - Incorrect Frame sequence detected in virtual channel 2. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK (0x8U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT (3U) /*! err_f_seq_vc3 - Incorrect Frame sequence detected in virtual channel 3. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK (0x10U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT (4U) /*! err_f_seq_vc4 - Incorrect Frame sequence detected in virtual channel 4. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK (0x20U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT (5U) /*! err_f_seq_vc5 - Incorrect Frame sequence detected in virtual channel 5. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK (0x40U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT (6U) /*! err_f_seq_vc6 - Incorrect Frame sequence detected in virtual channel 6. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK (0x80U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT (7U) /*! err_f_seq_vc7 - Incorrect Frame sequence detected in virtual channel 7. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK (0x100U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT (8U) /*! err_f_seq_vc8 - Incorrect Frame sequence detected in virtual channel 8. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK (0x200U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT (9U) /*! err_f_seq_vc9 - Incorrect Frame sequence detected in virtual channel 9. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK (0x400U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT (10U) /*! err_f_seq_vc10 - Incorrect Frame sequence detected in virtual channel 10. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK (0x800U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT (11U) /*! err_f_seq_vc11 - Incorrect Frame sequence detected in virtual channel 11. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK (0x1000U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT (12U) /*! err_f_seq_vc12 - Incorrect Frame sequence detected in virtual channel 12. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK (0x2000U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT (13U) /*! err_f_seq_vc13 - Incorrect Frame sequence detected in virtual channel 13. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK (0x4000U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT (14U) /*! err_f_seq_vc14 - Incorrect Frame sequence detected in virtual channel 14. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK (0x8000U) #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT (15U) /*! err_f_seq_vc15 - Incorrect Frame sequence detected in virtual channel 15. * 0b0..No error. * 0b1..Incorrect frame sequence error is detected. */ #define CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT)) & CSI_INT_ST_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK) /*! @} */ /*! @name INT_MSK_SEQ_FRAME_FATAL - Mask for fatal interruption caused by Frame Sequence. */ /*! @{ */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK (0x1U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT (0U) /*! err_f_seq_vc0 - Mask for err_f_seq_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK (0x2U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT (1U) /*! err_f_seq_vc1 - Mask for err_f_seq_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK (0x4U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT (2U) /*! err_f_seq_vc2 - Mask for err_f_seq_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK (0x8U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT (3U) /*! err_f_seq_vc3 - Mask for err_f_seq_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK (0x10U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT (4U) /*! err_f_seq_vc4 - Mask for err_f_seq_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK (0x20U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT (5U) /*! err_f_seq_vc5 - Mask for err_f_seq_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK (0x40U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT (6U) /*! err_f_seq_vc6 - Mask for err_f_seq_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK (0x80U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT (7U) /*! err_f_seq_vc7 - Mask for err_f_seq_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK (0x100U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT (8U) /*! err_f_seq_vc8 - Mask for err_f_seq_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK (0x200U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT (9U) /*! err_f_seq_vc9 - Mask for err_f_seq_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK (0x400U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT (10U) /*! err_f_seq_vc10 - Mask for err_f_seq_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK (0x800U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT (11U) /*! err_f_seq_vc11 - Mask for err_f_seq_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK (0x1000U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT (12U) /*! err_f_seq_vc12 - Mask for err_f_seq_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK (0x2000U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT (13U) /*! err_f_seq_vc13 - Mask for err_f_seq_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK (0x4000U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT (14U) /*! err_f_seq_vc14 - Mask for err_f_seq_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK (0x8000U) #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT (15U) /*! err_f_seq_vc15 - Mask for err_f_seq_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT)) & CSI_INT_MSK_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK) /*! @} */ /*! @name INT_FORCE_SEQ_FRAME_FATAL - Force for fatal interruption caused by Frame Sequence. */ /*! @{ */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK (0x1U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT (0U) /*! err_f_seq_vc0 - Force err_f_seq_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc0_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK (0x2U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT (1U) /*! err_f_seq_vc1 - Force err_f_seq_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc1_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK (0x4U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT (2U) /*! err_f_seq_vc2 - Force err_f_seq_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc2_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK (0x8U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT (3U) /*! err_f_seq_vc3 - Force err_f_seq_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc3_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK (0x10U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT (4U) /*! err_f_seq_vc4 - Force err_f_seq_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc4_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK (0x20U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT (5U) /*! err_f_seq_vc5 - Force err_f_seq_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc5_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK (0x40U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT (6U) /*! err_f_seq_vc6 - Force err_f_seq_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc6_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK (0x80U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT (7U) /*! err_f_seq_vc7 - Force err_f_seq_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc7_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK (0x100U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT (8U) /*! err_f_seq_vc8 - Force err_f_seq_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc8_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK (0x200U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT (9U) /*! err_f_seq_vc9 - Force err_f_seq_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc9_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK (0x400U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT (10U) /*! err_f_seq_vc10 - Force err_f_seq_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc10_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK (0x800U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT (11U) /*! err_f_seq_vc11 - Force err_f_seq_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc11_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK (0x1000U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT (12U) /*! err_f_seq_vc12 - Force err_f_seq_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc12_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK (0x2000U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT (13U) /*! err_f_seq_vc13 - Force err_f_seq_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc13_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK (0x4000U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT (14U) /*! err_f_seq_vc14 - Force err_f_seq_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc14_MASK) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK (0x8000U) #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT (15U) /*! err_f_seq_vc15 - Force err_f_seq_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_SHIFT)) & CSI_INT_FORCE_SEQ_FRAME_FATAL_err_f_seq_vc15_MASK) /*! @} */ /*! @name INT_ST_CRC_FRAME_FATAL - Fatal Interruption caused by Frame CRC. */ /*! @{ */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_MASK (0x1U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT (0U) /*! err_frame_data_vc0 - Last received Frame in virtual channel 0, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc0_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_MASK (0x2U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT (1U) /*! err_frame_data_vc1 - Last received Frame in virtual channel 1, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc1_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_MASK (0x4U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT (2U) /*! err_frame_data_vc2 - Last received Frame in virtual channel 2, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc2_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_MASK (0x8U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT (3U) /*! err_frame_data_vc3 - Last received Frame in virtual channel 3, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc3_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_MASK (0x10U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT (4U) /*! err_frame_data_vc4 - Last received Frame in virtual channel 4, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc4_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_MASK (0x20U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT (5U) /*! err_frame_data_vc5 - Last received Frame in virtual channel 5, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc5_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_MASK (0x40U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT (6U) /*! err_frame_data_vc6 - Last received Frame in virtual channel 6, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc6_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_MASK (0x80U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT (7U) /*! err_frame_data_vc7 - Last received Frame in virtual channel 7, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc7_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_MASK (0x100U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT (8U) /*! err_frame_data_vc8 - Last received Frame in virtual channel 8, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc8_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_MASK (0x200U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT (9U) /*! err_frame_data_vc9 - Last received Frame in virtual channel 9, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc9_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_MASK (0x400U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT (10U) /*! err_frame_data_vc10 - Last received Frame in virtual channel 10, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc10_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_MASK (0x800U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT (11U) /*! err_frame_data_vc11 - Last received Frame in virtual channel 11, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc11_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_MASK (0x1000U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT (12U) /*! err_frame_data_vc12 - Last received Frame in virtual channel 12, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc12_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_MASK (0x2000U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT (13U) /*! err_frame_data_vc13 - Last received Frame in virtual channel 13, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc13_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_MASK (0x4000U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT (14U) /*! err_frame_data_vc14 - Last received Frame in virtual channel 14, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc14_MASK) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_MASK (0x8000U) #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT (15U) /*! err_frame_data_vc15 - Last received Frame in virtual channel 15, had at least one CRC error. * 0b0..No error. * 0b1..Frame CRC error is detected. */ #define CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT)) & CSI_INT_ST_CRC_FRAME_FATAL_err_frame_data_vc15_MASK) /*! @} */ /*! @name INT_MSK_CRC_FRAME_FATAL - Mask for fatal interruption caused by Frame CRC. */ /*! @{ */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_MASK (0x1U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT (0U) /*! err_frame_data_vc0 - Mask for err_frame_data_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc0_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_MASK (0x2U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT (1U) /*! err_frame_data_vc1 - Mask for err_frame_data_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc1_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_MASK (0x4U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT (2U) /*! err_frame_data_vc2 - Mask for err_frame_data_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc2_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_MASK (0x8U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT (3U) /*! err_frame_data_vc3 - Mask for err_frame_data_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc3_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_MASK (0x10U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT (4U) /*! err_frame_data_vc4 - Mask for err_frame_data_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc4_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_MASK (0x20U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT (5U) /*! err_frame_data_vc5 - Mask for err_frame_data_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc5_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_MASK (0x40U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT (6U) /*! err_frame_data_vc6 - Mask for err_frame_data_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc6_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_MASK (0x80U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT (7U) /*! err_frame_data_vc7 - Mask for err_frame_data_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc7_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_MASK (0x100U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT (8U) /*! err_frame_data_vc8 - Mask for err_frame_data_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc8_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_MASK (0x200U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT (9U) /*! err_frame_data_vc9 - Mask for err_frame_data_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc9_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_MASK (0x400U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT (10U) /*! err_frame_data_vc10 - Mask for err_frame_data_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc10_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_MASK (0x800U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT (11U) /*! err_frame_data_vc11 - Mask for err_frame_data_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc11_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_MASK (0x1000U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT (12U) /*! err_frame_data_vc12 - Mask for err_frame_data_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc12_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_MASK (0x2000U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT (13U) /*! err_frame_data_vc13 - Mask for err_frame_data_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc13_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_MASK (0x4000U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT (14U) /*! err_frame_data_vc14 - Mask for err_frame_data_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc14_MASK) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_MASK (0x8000U) #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT (15U) /*! err_frame_data_vc15 - Mask for err_frame_data_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT)) & CSI_INT_MSK_CRC_FRAME_FATAL_err_frame_data_vc15_MASK) /*! @} */ /*! @name INT_FORCE_CRC_FRAME_FATAL - Force for fatal interruption caused by Frame CRC. */ /*! @{ */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_MASK (0x1U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT (0U) /*! err_frame_data_vc0 - Force err_frame_data_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc0_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_MASK (0x2U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT (1U) /*! err_frame_data_vc1 - Force err_frame_data_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc1_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_MASK (0x4U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT (2U) /*! err_frame_data_vc2 - Force err_frame_data_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc2_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_MASK (0x8U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT (3U) /*! err_frame_data_vc3 - Force err_frame_data_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc3_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_MASK (0x10U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT (4U) /*! err_frame_data_vc4 - Force err_frame_data_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc4_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_MASK (0x20U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT (5U) /*! err_frame_data_vc5 - Force err_frame_data_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc5_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_MASK (0x40U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT (6U) /*! err_frame_data_vc6 - Force err_frame_data_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc6_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_MASK (0x80U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT (7U) /*! err_frame_data_vc7 - Force err_frame_data_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc7_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_MASK (0x100U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT (8U) /*! err_frame_data_vc8 - Force err_frame_data_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc8_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_MASK (0x200U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT (9U) /*! err_frame_data_vc9 - Force err_frame_data_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc9_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_MASK (0x400U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT (10U) /*! err_frame_data_vc10 - Force err_frame_data_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc10_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_MASK (0x800U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT (11U) /*! err_frame_data_vc11 - Force err_frame_data_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc11_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_MASK (0x1000U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT (12U) /*! err_frame_data_vc12 - Force err_frame_data_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc12_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_MASK (0x2000U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT (13U) /*! err_frame_data_vc13 - Force err_frame_data_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc13_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_MASK (0x4000U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT (14U) /*! err_frame_data_vc14 - Force err_frame_data_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc14_MASK) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_MASK (0x8000U) #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT (15U) /*! err_frame_data_vc15 - Force err_frame_data_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_SHIFT)) & CSI_INT_FORCE_CRC_FRAME_FATAL_err_frame_data_vc15_MASK) /*! @} */ /*! @name INT_ST_PLD_CRC_FATAL - Fatal Interruption caused by Payload CRC. */ /*! @{ */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc0_MASK (0x1U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc0_SHIFT (0U) /*! err_crc_vc0 - Payload Checksum error detected on virtual channel 0. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc0_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc0_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc1_MASK (0x2U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc1_SHIFT (1U) /*! err_crc_vc1 - Payload Checksum error detected on virtual channel 1. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc1_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc1_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc2_MASK (0x4U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc2_SHIFT (2U) /*! err_crc_vc2 - Payload Checksum error detected on virtual channel 2. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc2_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc2_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc3_MASK (0x8U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc3_SHIFT (3U) /*! err_crc_vc3 - Payload Checksum error detected on virtual channel 3. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc3_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc3_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc4_MASK (0x10U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc4_SHIFT (4U) /*! err_crc_vc4 - Payload Checksum error detected on virtual channel 4. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc4_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc4_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc5_MASK (0x20U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc5_SHIFT (5U) /*! err_crc_vc5 - Payload Checksum error detected on virtual channel 5. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc5_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc5_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc6_MASK (0x40U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc6_SHIFT (6U) /*! err_crc_vc6 - Payload Checksum error detected on virtual channel 6. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc6_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc6_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc7_MASK (0x80U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc7_SHIFT (7U) /*! err_crc_vc7 - Payload Checksum error detected on virtual channel 7. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc7_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc7_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc8_MASK (0x100U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc8_SHIFT (8U) /*! err_crc_vc8 - Payload Checksum error detected on virtual channel 8. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc8_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc8_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc9_MASK (0x200U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc9_SHIFT (9U) /*! err_crc_vc9 - Payload Checksum error detected on virtual channel 9. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc9_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc9_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc10_MASK (0x400U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc10_SHIFT (10U) /*! err_crc_vc10 - Payload Checksum error detected on virtual channel 10. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc10_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc10_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc11_MASK (0x800U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc11_SHIFT (11U) /*! err_crc_vc11 - Payload Checksum error detected on virtual channel 11. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc11_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc11_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc12_MASK (0x1000U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc12_SHIFT (12U) /*! err_crc_vc12 - Payload Checksum error detected on virtual channel 12. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc12_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc12_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc13_MASK (0x2000U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc13_SHIFT (13U) /*! err_crc_vc13 - Payload Checksum error detected on virtual channel 13. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc13_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc13_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc14_MASK (0x4000U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc14_SHIFT (14U) /*! err_crc_vc14 - Payload Checksum error detected on virtual channel 14. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc14_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc14_MASK) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc15_MASK (0x8000U) #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc15_SHIFT (15U) /*! err_crc_vc15 - Payload Checksum error detected on virtual channel 15. * 0b0..No error. * 0b1..Payload checksum error is detected. */ #define CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc15_SHIFT)) & CSI_INT_ST_PLD_CRC_FATAL_err_crc_vc15_MASK) /*! @} */ /*! @name INT_MSK_PLD_CRC_FATAL - Mask for fatal interruption caused by Payload CRC. */ /*! @{ */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_MASK (0x1U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_SHIFT (0U) /*! err_crc_vc0 - Mask for err_crc_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc0_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_MASK (0x2U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_SHIFT (1U) /*! err_crc_vc1 - Mask for err_crc_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc1_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_MASK (0x4U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_SHIFT (2U) /*! err_crc_vc2 - Mask for err_crc_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc2_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_MASK (0x8U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_SHIFT (3U) /*! err_crc_vc3 - Mask for err_crc_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc3_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_MASK (0x10U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_SHIFT (4U) /*! err_crc_vc4 - Mask for err_crc_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc4_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_MASK (0x20U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_SHIFT (5U) /*! err_crc_vc5 - Mask for err_crc_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc5_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_MASK (0x40U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_SHIFT (6U) /*! err_crc_vc6 - Mask for err_crc_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc6_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_MASK (0x80U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_SHIFT (7U) /*! err_crc_vc7 - Mask for err_crc_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc7_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_MASK (0x100U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_SHIFT (8U) /*! err_crc_vc8 - Mask for err_crc_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc8_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_MASK (0x200U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_SHIFT (9U) /*! err_crc_vc9 - Mask for err_crc_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc9_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_MASK (0x400U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_SHIFT (10U) /*! err_crc_vc10 - Mask for err_crc_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc10_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_MASK (0x800U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_SHIFT (11U) /*! err_crc_vc11 - Mask for err_crc_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc11_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_MASK (0x1000U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_SHIFT (12U) /*! err_crc_vc12 - Mask for err_crc_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc12_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_MASK (0x2000U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_SHIFT (13U) /*! err_crc_vc13 - Mask for err_crc_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc13_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_MASK (0x4000U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_SHIFT (14U) /*! err_crc_vc14 - Mask for err_crc_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc14_MASK) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_MASK (0x8000U) #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_SHIFT (15U) /*! err_crc_vc15 - Mask for err_crc_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_SHIFT)) & CSI_INT_MSK_PLD_CRC_FATAL_err_crc_vc15_MASK) /*! @} */ /*! @name INT_FORCE_PLD_CRC_FATAL - Force for fatal interruption caused by Payload CRC. */ /*! @{ */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_MASK (0x1U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_SHIFT (0U) /*! err_crc_vc0 - Force err_crc_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc0_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_MASK (0x2U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_SHIFT (1U) /*! err_crc_vc1 - Force err_crc_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc1_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_MASK (0x4U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_SHIFT (2U) /*! err_crc_vc2 - Force err_crc_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc2_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_MASK (0x8U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_SHIFT (3U) /*! err_crc_vc3 - Force err_crc_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc3_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_MASK (0x10U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_SHIFT (4U) /*! err_crc_vc4 - Force err_crc_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc4_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_MASK (0x20U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_SHIFT (5U) /*! err_crc_vc5 - Force err_crc_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc5_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_MASK (0x40U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_SHIFT (6U) /*! err_crc_vc6 - Force err_crc_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc6_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_MASK (0x80U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_SHIFT (7U) /*! err_crc_vc7 - Force err_crc_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc7_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_MASK (0x100U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_SHIFT (8U) /*! err_crc_vc8 - Force err_crc_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc8_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_MASK (0x200U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_SHIFT (9U) /*! err_crc_vc9 - Force err_crc_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc9_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_MASK (0x400U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_SHIFT (10U) /*! err_crc_vc10 - Force err_crc_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc10_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_MASK (0x800U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_SHIFT (11U) /*! err_crc_vc11 - Force err_crc_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc11_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_MASK (0x1000U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_SHIFT (12U) /*! err_crc_vc12 - Force err_crc_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc12_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_MASK (0x2000U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_SHIFT (13U) /*! err_crc_vc13 - Force err_crc_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc13_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_MASK (0x4000U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_SHIFT (14U) /*! err_crc_vc14 - Force err_crc_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc14_MASK) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_MASK (0x8000U) #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_SHIFT (15U) /*! err_crc_vc15 - Force err_crc_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_SHIFT)) & CSI_INT_FORCE_PLD_CRC_FATAL_err_crc_vc15_MASK) /*! @} */ /*! @name INT_ST_DATA_ID - Interruption caused by Data Type. */ /*! @{ */ #define CSI_INT_ST_DATA_ID_err_id_vc0_MASK (0x1U) #define CSI_INT_ST_DATA_ID_err_id_vc0_SHIFT (0U) /*! err_id_vc0 - Unrecognized or unimplemented data type detected in virtual channel 0. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc0_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc0_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc1_MASK (0x2U) #define CSI_INT_ST_DATA_ID_err_id_vc1_SHIFT (1U) /*! err_id_vc1 - Unrecognized or unimplemented data type detected in virtual channel 1. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc1_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc1_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc2_MASK (0x4U) #define CSI_INT_ST_DATA_ID_err_id_vc2_SHIFT (2U) /*! err_id_vc2 - Unrecognized or unimplemented data type detected in virtual channel 2. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc2_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc2_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc3_MASK (0x8U) #define CSI_INT_ST_DATA_ID_err_id_vc3_SHIFT (3U) /*! err_id_vc3 - Unrecognized or unimplemented data type detected in virtual channel 3. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc3_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc3_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc4_MASK (0x10U) #define CSI_INT_ST_DATA_ID_err_id_vc4_SHIFT (4U) /*! err_id_vc4 - Unrecognized or unimplemented data type detected in virtual channel 4. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc4_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc4_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc5_MASK (0x20U) #define CSI_INT_ST_DATA_ID_err_id_vc5_SHIFT (5U) /*! err_id_vc5 - Unrecognized or unimplemented data type detected in virtual channel 5. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc5_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc5_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc6_MASK (0x40U) #define CSI_INT_ST_DATA_ID_err_id_vc6_SHIFT (6U) /*! err_id_vc6 - Unrecognized or unimplemented data type detected in virtual channel 6. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc6_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc6_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc7_MASK (0x80U) #define CSI_INT_ST_DATA_ID_err_id_vc7_SHIFT (7U) /*! err_id_vc7 - Unrecognized or unimplemented data type detected in virtual channel 7. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc7_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc7_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc8_MASK (0x100U) #define CSI_INT_ST_DATA_ID_err_id_vc8_SHIFT (8U) /*! err_id_vc8 - Unrecognized or unimplemented data type detected in virtual channel 8. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc8_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc8_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc9_MASK (0x200U) #define CSI_INT_ST_DATA_ID_err_id_vc9_SHIFT (9U) /*! err_id_vc9 - Unrecognized or unimplemented data type detected in virtual channel 9. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc9_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc9_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc10_MASK (0x400U) #define CSI_INT_ST_DATA_ID_err_id_vc10_SHIFT (10U) /*! err_id_vc10 - Unrecognized or unimplemented data type detected in virtual channel 10. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc10_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc10_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc11_MASK (0x800U) #define CSI_INT_ST_DATA_ID_err_id_vc11_SHIFT (11U) /*! err_id_vc11 - Unrecognized or unimplemented data type detected in virtual channel 11. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc11_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc11_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc12_MASK (0x1000U) #define CSI_INT_ST_DATA_ID_err_id_vc12_SHIFT (12U) /*! err_id_vc12 - Unrecognized or unimplemented data type detected in virtual channel 12. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc12_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc12_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc13_MASK (0x2000U) #define CSI_INT_ST_DATA_ID_err_id_vc13_SHIFT (13U) /*! err_id_vc13 - Unrecognized or unimplemented data type detected in virtual channel 13. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc13_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc13_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc14_MASK (0x4000U) #define CSI_INT_ST_DATA_ID_err_id_vc14_SHIFT (14U) /*! err_id_vc14 - Unrecognized or unimplemented data type detected in virtual channel 14. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc14_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc14_MASK) #define CSI_INT_ST_DATA_ID_err_id_vc15_MASK (0x8000U) #define CSI_INT_ST_DATA_ID_err_id_vc15_SHIFT (15U) /*! err_id_vc15 - Unrecognized or unimplemented data type detected in virtual channel 15. * 0b0..No error. * 0b1..Unrecognized or unimplemented data type error is detected. */ #define CSI_INT_ST_DATA_ID_err_id_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_DATA_ID_err_id_vc15_SHIFT)) & CSI_INT_ST_DATA_ID_err_id_vc15_MASK) /*! @} */ /*! @name INT_MSK_DATA_ID - Mask for interruption caused by Data Type. */ /*! @{ */ #define CSI_INT_MSK_DATA_ID_err_id_vc0_MASK (0x1U) #define CSI_INT_MSK_DATA_ID_err_id_vc0_SHIFT (0U) /*! err_id_vc0 - Mask for err_id_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc0_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc0_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc1_MASK (0x2U) #define CSI_INT_MSK_DATA_ID_err_id_vc1_SHIFT (1U) /*! err_id_vc1 - Mask for err_id_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc1_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc1_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc2_MASK (0x4U) #define CSI_INT_MSK_DATA_ID_err_id_vc2_SHIFT (2U) /*! err_id_vc2 - Mask for err_id_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc2_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc2_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc3_MASK (0x8U) #define CSI_INT_MSK_DATA_ID_err_id_vc3_SHIFT (3U) /*! err_id_vc3 - Mask for err_id_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc3_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc3_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc4_MASK (0x10U) #define CSI_INT_MSK_DATA_ID_err_id_vc4_SHIFT (4U) /*! err_id_vc4 - Mask for err_id_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc4_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc4_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc5_MASK (0x20U) #define CSI_INT_MSK_DATA_ID_err_id_vc5_SHIFT (5U) /*! err_id_vc5 - Mask for err_id_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc5_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc5_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc6_MASK (0x40U) #define CSI_INT_MSK_DATA_ID_err_id_vc6_SHIFT (6U) /*! err_id_vc6 - Mask for err_id_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc6_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc6_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc7_MASK (0x80U) #define CSI_INT_MSK_DATA_ID_err_id_vc7_SHIFT (7U) /*! err_id_vc7 - Mask for err_id_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc7_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc7_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc8_MASK (0x100U) #define CSI_INT_MSK_DATA_ID_err_id_vc8_SHIFT (8U) /*! err_id_vc8 - Mask for err_id_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc8_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc8_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc9_MASK (0x200U) #define CSI_INT_MSK_DATA_ID_err_id_vc9_SHIFT (9U) /*! err_id_vc9 - Mask for err_id_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc9_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc9_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc10_MASK (0x400U) #define CSI_INT_MSK_DATA_ID_err_id_vc10_SHIFT (10U) /*! err_id_vc10 - Mask for err_id_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc10_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc10_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc11_MASK (0x800U) #define CSI_INT_MSK_DATA_ID_err_id_vc11_SHIFT (11U) /*! err_id_vc11 - Mask for err_id_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc11_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc11_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc12_MASK (0x1000U) #define CSI_INT_MSK_DATA_ID_err_id_vc12_SHIFT (12U) /*! err_id_vc12 - Mask for err_id_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc12_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc12_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc13_MASK (0x2000U) #define CSI_INT_MSK_DATA_ID_err_id_vc13_SHIFT (13U) /*! err_id_vc13 - Mask for err_id_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc13_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc13_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc14_MASK (0x4000U) #define CSI_INT_MSK_DATA_ID_err_id_vc14_SHIFT (14U) /*! err_id_vc14 - Mask for err_id_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc14_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc14_MASK) #define CSI_INT_MSK_DATA_ID_err_id_vc15_MASK (0x8000U) #define CSI_INT_MSK_DATA_ID_err_id_vc15_SHIFT (15U) /*! err_id_vc15 - Mask for err_id_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_DATA_ID_err_id_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_DATA_ID_err_id_vc15_SHIFT)) & CSI_INT_MSK_DATA_ID_err_id_vc15_MASK) /*! @} */ /*! @name INT_FORCE_DATA_ID - Force for interruption caused by Data Type. */ /*! @{ */ #define CSI_INT_FORCE_DATA_ID_err_id_vc0_MASK (0x1U) #define CSI_INT_FORCE_DATA_ID_err_id_vc0_SHIFT (0U) /*! err_id_vc0 - Force err_id_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc0_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc0_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc1_MASK (0x2U) #define CSI_INT_FORCE_DATA_ID_err_id_vc1_SHIFT (1U) /*! err_id_vc1 - Force err_id_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc1_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc1_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc2_MASK (0x4U) #define CSI_INT_FORCE_DATA_ID_err_id_vc2_SHIFT (2U) /*! err_id_vc2 - Force err_id_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc2_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc2_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc3_MASK (0x8U) #define CSI_INT_FORCE_DATA_ID_err_id_vc3_SHIFT (3U) /*! err_id_vc3 - Force err_id_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc3_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc3_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc4_MASK (0x10U) #define CSI_INT_FORCE_DATA_ID_err_id_vc4_SHIFT (4U) /*! err_id_vc4 - Force err_id_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc4_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc4_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc5_MASK (0x20U) #define CSI_INT_FORCE_DATA_ID_err_id_vc5_SHIFT (5U) /*! err_id_vc5 - Force err_id_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc5_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc5_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc6_MASK (0x40U) #define CSI_INT_FORCE_DATA_ID_err_id_vc6_SHIFT (6U) /*! err_id_vc6 - Force err_id_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc6_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc6_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc7_MASK (0x80U) #define CSI_INT_FORCE_DATA_ID_err_id_vc7_SHIFT (7U) /*! err_id_vc7 - Force err_id_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc7_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc7_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc8_MASK (0x100U) #define CSI_INT_FORCE_DATA_ID_err_id_vc8_SHIFT (8U) /*! err_id_vc8 - Force err_id_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc8_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc8_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc9_MASK (0x200U) #define CSI_INT_FORCE_DATA_ID_err_id_vc9_SHIFT (9U) /*! err_id_vc9 - Force err_id_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc9_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc9_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc10_MASK (0x400U) #define CSI_INT_FORCE_DATA_ID_err_id_vc10_SHIFT (10U) /*! err_id_vc10 - Force err_id_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc10_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc10_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc11_MASK (0x800U) #define CSI_INT_FORCE_DATA_ID_err_id_vc11_SHIFT (11U) /*! err_id_vc11 - Force err_id_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc11_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc11_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc12_MASK (0x1000U) #define CSI_INT_FORCE_DATA_ID_err_id_vc12_SHIFT (12U) /*! err_id_vc12 - Force err_id_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc12_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc12_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc13_MASK (0x2000U) #define CSI_INT_FORCE_DATA_ID_err_id_vc13_SHIFT (13U) /*! err_id_vc13 - Force err_id_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc13_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc13_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc14_MASK (0x4000U) #define CSI_INT_FORCE_DATA_ID_err_id_vc14_SHIFT (14U) /*! err_id_vc14 - Force err_id_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc14_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc14_MASK) #define CSI_INT_FORCE_DATA_ID_err_id_vc15_MASK (0x8000U) #define CSI_INT_FORCE_DATA_ID_err_id_vc15_SHIFT (15U) /*! err_id_vc15 - Force err_id_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_DATA_ID_err_id_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_DATA_ID_err_id_vc15_SHIFT)) & CSI_INT_FORCE_DATA_ID_err_id_vc15_MASK) /*! @} */ /*! @name INT_ST_ECC_CORRECTED - Interruption caused by Header single bit errors. */ /*! @{ */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_MASK (0x1U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT (0U) /*! err_ecc_corrected_vc0 - Header error detected and corrected on virtual channel 0. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc0_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_MASK (0x2U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT (1U) /*! err_ecc_corrected_vc1 - Header error detected and corrected on virtual channel 1. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc1_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_MASK (0x4U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT (2U) /*! err_ecc_corrected_vc2 - Header error detected and corrected on virtual channel 2. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc2_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_MASK (0x8U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT (3U) /*! err_ecc_corrected_vc3 - Header error detected and corrected on virtual channel 3. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc3_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_MASK (0x10U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT (4U) /*! err_ecc_corrected_vc4 - Header error detected and corrected on virtual channel 4. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc4_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_MASK (0x20U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT (5U) /*! err_ecc_corrected_vc5 - Header error detected and corrected on virtual channel 5. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc5_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_MASK (0x40U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT (6U) /*! err_ecc_corrected_vc6 - Header error detected and corrected on virtual channel 6. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc6_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_MASK (0x80U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT (7U) /*! err_ecc_corrected_vc7 - Header error detected and corrected on virtual channel 7. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc7_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_MASK (0x100U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT (8U) /*! err_ecc_corrected_vc8 - Header error detected and corrected on virtual channel 8. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc8_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_MASK (0x200U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT (9U) /*! err_ecc_corrected_vc9 - Header error detected and corrected on virtual channel 9. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc9_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_MASK (0x400U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT (10U) /*! err_ecc_corrected_vc10 - Header error detected and corrected on virtual channel 10. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc10_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_MASK (0x800U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT (11U) /*! err_ecc_corrected_vc11 - Header error detected and corrected on virtual channel 11. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc11_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_MASK (0x1000U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT (12U) /*! err_ecc_corrected_vc12 - Header error detected and corrected on virtual channel 12. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc12_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_MASK (0x2000U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT (13U) /*! err_ecc_corrected_vc13 - Header error detected and corrected on virtual channel 13. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc13_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_MASK (0x4000U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT (14U) /*! err_ecc_corrected_vc14 - Header error detected and corrected on virtual channel 14. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc14_MASK) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_MASK (0x8000U) #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT (15U) /*! err_ecc_corrected_vc15 - Header error detected and corrected on virtual channel 15. * 0b0..No error. * 0b1..Header error detected and corrected. */ #define CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT)) & CSI_INT_ST_ECC_CORRECTED_err_ecc_corrected_vc15_MASK) /*! @} */ /*! @name INT_MSK_ECC_CORRECTED - Mask for interruption caused by Header single bit errors. */ /*! @{ */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_MASK (0x1U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT (0U) /*! err_ecc_corrected_vc0 - Mask for err_ecc_corrected_vc0. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc0_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_MASK (0x2U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT (1U) /*! err_ecc_corrected_vc1 - Mask for err_ecc_corrected_vc1. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc1_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_MASK (0x4U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT (2U) /*! err_ecc_corrected_vc2 - Mask for err_ecc_corrected_vc2. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc2_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_MASK (0x8U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT (3U) /*! err_ecc_corrected_vc3 - Mask for err_ecc_corrected_vc3. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc3_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_MASK (0x10U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT (4U) /*! err_ecc_corrected_vc4 - Mask for err_ecc_corrected_vc4. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc4_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_MASK (0x20U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT (5U) /*! err_ecc_corrected_vc5 - Mask for err_ecc_corrected_vc5. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc5_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_MASK (0x40U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT (6U) /*! err_ecc_corrected_vc6 - Mask for err_ecc_corrected_vc6. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc6_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_MASK (0x80U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT (7U) /*! err_ecc_corrected_vc7 - Mask for err_ecc_corrected_vc7. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc7_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_MASK (0x100U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT (8U) /*! err_ecc_corrected_vc8 - Mask for err_ecc_corrected_vc8. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc8_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_MASK (0x200U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT (9U) /*! err_ecc_corrected_vc9 - Mask for err_ecc_corrected_vc9. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc9_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_MASK (0x400U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT (10U) /*! err_ecc_corrected_vc10 - Mask for err_ecc_corrected_vc10. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc10_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_MASK (0x800U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT (11U) /*! err_ecc_corrected_vc11 - Mask for err_ecc_corrected_vc11. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc11_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_MASK (0x1000U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT (12U) /*! err_ecc_corrected_vc12 - Mask for err_ecc_corrected_vc12. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc12_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_MASK (0x2000U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT (13U) /*! err_ecc_corrected_vc13 - Mask for err_ecc_corrected_vc13. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc13_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_MASK (0x4000U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT (14U) /*! err_ecc_corrected_vc14 - Mask for err_ecc_corrected_vc14. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc14_MASK) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_MASK (0x8000U) #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT (15U) /*! err_ecc_corrected_vc15 - Mask for err_ecc_corrected_vc15. * 0b0..Interrupt source is masked. * 0b1..Enable the interrupt source. */ #define CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT)) & CSI_INT_MSK_ECC_CORRECTED_err_ecc_corrected_vc15_MASK) /*! @} */ /*! @name INT_FORCE_ECC_CORRECTED - Force for interruption caused by Header single bit errors. */ /*! @{ */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_MASK (0x1U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT (0U) /*! err_ecc_corrected_vc0 - Force err_ecc_corrected_vc0. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc0_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_MASK (0x2U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT (1U) /*! err_ecc_corrected_vc1 - Force err_ecc_corrected_vc1. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc1_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_MASK (0x4U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT (2U) /*! err_ecc_corrected_vc2 - Force err_ecc_corrected_vc2. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc2_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_MASK (0x8U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT (3U) /*! err_ecc_corrected_vc3 - Force err_ecc_corrected_vc3. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc3_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_MASK (0x10U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT (4U) /*! err_ecc_corrected_vc4 - Force err_ecc_corrected_vc4. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc4_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_MASK (0x20U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT (5U) /*! err_ecc_corrected_vc5 - Force err_ecc_corrected_vc5. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc5_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_MASK (0x40U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT (6U) /*! err_ecc_corrected_vc6 - Force err_ecc_corrected_vc6. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc6_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_MASK (0x80U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT (7U) /*! err_ecc_corrected_vc7 - Force err_ecc_corrected_vc7. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc7_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_MASK (0x100U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT (8U) /*! err_ecc_corrected_vc8 - Force err_ecc_corrected_vc8. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc8_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_MASK (0x200U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT (9U) /*! err_ecc_corrected_vc9 - Force err_ecc_corrected_vc9. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc9_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_MASK (0x400U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT (10U) /*! err_ecc_corrected_vc10 - Force err_ecc_corrected_vc10. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc10_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_MASK (0x800U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT (11U) /*! err_ecc_corrected_vc11 - Force err_ecc_corrected_vc11. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc11_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_MASK (0x1000U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT (12U) /*! err_ecc_corrected_vc12 - Force err_ecc_corrected_vc12. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc12_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_MASK (0x2000U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT (13U) /*! err_ecc_corrected_vc13 - Force err_ecc_corrected_vc13. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc13_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_MASK (0x4000U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT (14U) /*! err_ecc_corrected_vc14 - Force err_ecc_corrected_vc14. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc14_MASK) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_MASK (0x8000U) #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT (15U) /*! err_ecc_corrected_vc15 - Force err_ecc_corrected_vc15. * 0b0..Do not force the error event. * 0b1..Force the error event to trigger. */ #define CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15(x) (((uint32_t)(((uint32_t)(x)) << CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_SHIFT)) & CSI_INT_FORCE_ECC_CORRECTED_err_ecc_corrected_vc15_MASK) /*! @} */ /*! @name SCRAMBLING - Data De-Scrambling. */ /*! @{ */ #define CSI_SCRAMBLING_scramble_enable_MASK (0x1U) #define CSI_SCRAMBLING_scramble_enable_SHIFT (0U) /*! scramble_enable - Enables data de-scrambling on the controller side. * 0b1..Enable data de-scrambling * 0b0..Disable data de-scrambling */ #define CSI_SCRAMBLING_scramble_enable(x) (((uint32_t)(((uint32_t)(x)) << CSI_SCRAMBLING_scramble_enable_SHIFT)) & CSI_SCRAMBLING_scramble_enable_MASK) /*! @} */ /*! @name SCRAMBLING_SEED1 - De-scrambler seed for lane1. */ /*! @{ */ #define CSI_SCRAMBLING_SEED1_scramble_seed_lane1_MASK (0xFFFFU) #define CSI_SCRAMBLING_SEED1_scramble_seed_lane1_SHIFT (0U) /*! scramble_seed_lane1 - Seed used by De-scrambler block for lane 1 */ #define CSI_SCRAMBLING_SEED1_scramble_seed_lane1(x) (((uint32_t)(((uint32_t)(x)) << CSI_SCRAMBLING_SEED1_scramble_seed_lane1_SHIFT)) & CSI_SCRAMBLING_SEED1_scramble_seed_lane1_MASK) /*! @} */ /*! @name SCRAMBLING_SEED2 - De-scrambler seed for lane2. */ /*! @{ */ #define CSI_SCRAMBLING_SEED2_scramble_seed_lane2_MASK (0xFFFFU) #define CSI_SCRAMBLING_SEED2_scramble_seed_lane2_SHIFT (0U) /*! scramble_seed_lane2 - Seed used by De-scrambler block for lane 2 */ #define CSI_SCRAMBLING_SEED2_scramble_seed_lane2(x) (((uint32_t)(((uint32_t)(x)) << CSI_SCRAMBLING_SEED2_scramble_seed_lane2_SHIFT)) & CSI_SCRAMBLING_SEED2_scramble_seed_lane2_MASK) /*! @} */ /*! @name SCRAMBLING_SEED3 - De-scrambler seed for lane3. */ /*! @{ */ #define CSI_SCRAMBLING_SEED3_scramble_seed_lane3_MASK (0xFFFFU) #define CSI_SCRAMBLING_SEED3_scramble_seed_lane3_SHIFT (0U) /*! scramble_seed_lane3 - Seed used by De-scrambler block for lane 3 */ #define CSI_SCRAMBLING_SEED3_scramble_seed_lane3(x) (((uint32_t)(((uint32_t)(x)) << CSI_SCRAMBLING_SEED3_scramble_seed_lane3_SHIFT)) & CSI_SCRAMBLING_SEED3_scramble_seed_lane3_MASK) /*! @} */ /*! @name SCRAMBLING_SEED4 - De-scrambler seed for lane4. */ /*! @{ */ #define CSI_SCRAMBLING_SEED4_scramble_seed_lane4_MASK (0xFFFFU) #define CSI_SCRAMBLING_SEED4_scramble_seed_lane4_SHIFT (0U) /*! scramble_seed_lane4 - Seed used by De-scrambler block for lane 4 */ #define CSI_SCRAMBLING_SEED4_scramble_seed_lane4(x) (((uint32_t)(((uint32_t)(x)) << CSI_SCRAMBLING_SEED4_scramble_seed_lane4_SHIFT)) & CSI_SCRAMBLING_SEED4_scramble_seed_lane4_MASK) /*! @} */ /*! * @} */ /* end of group CSI_Register_Masks */ /* CSI - Peripheral instance base addresses */ /** Peripheral CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI base address */ #define CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI_BASE (0x4AD40000u) /** Peripheral CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI base pointer */ #define CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI ((CSI_Type *)CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI_BASE) /** Array initializer of CSI peripheral base addresses */ #define CSI_BASE_ADDRS { CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI_BASE } /** Array initializer of CSI peripheral base pointers */ #define CSI_BASE_PTRS { CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI } /*! * @} */ /* end of group CSI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDR_BLK_CTRL_DDRMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_BLK_CTRL_DDRMIX_Peripheral_Access_Layer DDR_BLK_CTRL_DDRMIX Peripheral Access Layer * @{ */ /** DDR_BLK_CTRL_DDRMIX - Register Layout Typedef */ typedef struct { __IO uint32_t HWFFC_CTRL; /**< DDRPHY DfiClk, DflCtlClk HWFFC Control, offset: 0x0 */ uint8_t RESERVED_0[8]; __IO uint32_t DDRC_STOP_CTRL; /**< DDR Controller ipg_stop SW control, offset: 0xC */ __IO uint32_t AUTO_CG_CTRL; /**< DDR Controller automatic clock gating control when no AXI transmit, offset: 0x10 */ uint8_t RESERVED_1[4]; __IO uint32_t DDRC_EXCLUSIVE_EN; /**< DDRC AXI exclusive access monitor enable, offset: 0x18 */ __IO uint32_t DDRC_URGENT_EN; /**< DDRC real_time read urgent and read urgent enable, offset: 0x1C */ __IO uint32_t RT_MASTER_ID_0_1; /**< DDRC real_time master 6bit extend-ID range 0 and range 1, offset: 0x20 */ __IO uint32_t RT_MASTER_ID_2_3; /**< DDRC real_time master 6bit extend-ID range 2 and range 3, offset: 0x24 */ uint8_t RESERVED_2[4]; __IO uint32_t AXI_PARITY_ERR_INJECT; /**< DDRMIX AXI parity error injection register, offset: 0x2C */ __IO uint32_t RT_MASTER_ID_4_5; /**< DDRC real_time master 6bit extend-ID range 4 and range 5, offset: 0x30 */ __IO uint32_t RT_MASTER_ID_6_7; /**< DDRC real_time master 6bit extend-ID range 6 and range 7, offset: 0x34 */ } DDR_BLK_CTRL_DDRMIX_Type; /* ---------------------------------------------------------------------------- -- DDR_BLK_CTRL_DDRMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_BLK_CTRL_DDRMIX_Register_Masks DDR_BLK_CTRL_DDRMIX Register Masks * @{ */ /*! @name HWFFC_CTRL - DDRPHY DfiClk, DflCtlClk HWFFC Control */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_MASK (0x1U) #define DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_SHIFT (0U) /*! HWFFC_EN - DDRPHY DfiClk, DfiCtlClk HWFFC Enable */ #define DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_EN_MASK) #define DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_MASK (0x2U) #define DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_SHIFT (1U) /*! HWFFC_SEL - DDRPHY DfiClk, DfiCtlClk HWFFC Select */ #define DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_SHIFT)) & DDR_BLK_CTRL_DDRMIX_HWFFC_CTRL_HWFFC_SEL_MASK) /*! @} */ /*! @name DDRC_STOP_CTRL - DDR Controller ipg_stop SW control */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_MASK (0x1U) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_SHIFT (0U) /*! DDRC_STOP - DDR Controller ipg_stop. */ #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_MASK) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_MASK (0x2U) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_SHIFT (1U) /*! DDRC_STOP_ACK - DDR Controller ipg_stop_ack. */ #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_ACK_MASK) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_DRAM_SELF_REFRESH_MASK (0x4U) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_DRAM_SELF_REFRESH_SHIFT (2U) /*! DDRC_DRAM_SELF_REFRESH - DDR Controller ddrc_dram_self_refresh. */ #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_DRAM_SELF_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_DRAM_SELF_REFRESH_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_DRAM_SELF_REFRESH_MASK) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_EN_MASK (0x10U) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_EN_SHIFT (4U) /*! DDRC_STOP_HOLD_EN - DDR Controller ipg_stop holds for a period of time before clearing. */ #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_EN_MASK) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_PERIOD_MASK (0xFFFFFF00U) #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_PERIOD_SHIFT (8U) /*! DDRC_STOP_HOLD_PERIOD - DDR Controller ipg_stop hold period before clearing. */ #define DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_PERIOD_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_STOP_CTRL_DDRC_STOP_HOLD_PERIOD_MASK) /*! @} */ /*! @name AUTO_CG_CTRL - DDR Controller automatic clock gating control when no AXI transmit */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_MASK (0xFFFFU) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_SHIFT (0U) /*! SSI_IDLE_STRAP - Number of cycles for SSI being idle before DDRC clock gating. */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_SSI_IDLE_STRAP_MASK) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_MASK (0x10000U) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_SHIFT (16U) /*! AUTO_CG_ENA - DDR Controller automatic clock gating enable bit. */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_AUTO_CG_ENA_MASK) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_MASK (0x20000U) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_SHIFT (17U) /*! HWFFC_ACG_FORCE_B - DDR Controller hwffc and auto CG send ipg_stop allow bit. Can only programmed once. */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_HWFFC_ACG_FORCE_B_MASK) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_CLK_MASK (0x1000000U) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_CLK_SHIFT (24U) /*! GATE_DDRC_CLK - DDR Auto Clock Gating is allowed for DDR Controller clock ipg_clk_ddrc. */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_CLK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_CLK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_CLK_MASK) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_IPS_CLK_MASK (0x4000000U) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_IPS_CLK_SHIFT (26U) /*! GATE_DDRC_IPS_CLK - DDR Auto Clock Gating is allowed for DDR Controller IPS clock ips_clk_ddrc. */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_IPS_CLK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_IPS_CLK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRC_IPS_CLK_MASK) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_DFICLK_MASK (0x10000000U) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_DFICLK_SHIFT (28U) /*! GATE_DDRPHY_DFICLK - DDR Auto Clock Gating is allowed for DDRPHY DfiClk clock. */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_DFICLK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_DFICLK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_DFICLK_MASK) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_APBCLK_MASK (0x40000000U) #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_APBCLK_SHIFT (30U) /*! GATE_DDRPHY_APBCLK - DDR Auto Clock Gating is allowed for DDRPHY APBCLK clock. */ #define DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_APBCLK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_APBCLK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AUTO_CG_CTRL_GATE_DDRPHY_APBCLK_MASK) /*! @} */ /*! @name DDRC_EXCLUSIVE_EN - DDRC AXI exclusive access monitor enable */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_DDRC_EXCLUSIVE_EN_EXCLUSIVE_EN_MASK (0x1U) #define DDR_BLK_CTRL_DDRMIX_DDRC_EXCLUSIVE_EN_EXCLUSIVE_EN_SHIFT (0U) /*! EXCLUSIVE_EN - DDRC AXI exclusive access monitor enable */ #define DDR_BLK_CTRL_DDRMIX_DDRC_EXCLUSIVE_EN_EXCLUSIVE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_EXCLUSIVE_EN_EXCLUSIVE_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_EXCLUSIVE_EN_EXCLUSIVE_EN_MASK) /*! @} */ /*! @name DDRC_URGENT_EN - DDRC real_time read urgent and read urgent enable */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_READ_URGENT_EN_MASK (0x1U) #define DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_READ_URGENT_EN_SHIFT (0U) /*! READ_URGENT_EN - DDRC ddrc_read_urgent is enabled */ #define DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_READ_URGENT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_READ_URGENT_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_READ_URGENT_EN_MASK) #define DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_AR_RT_URGENT_EN_MASK (0x2U) #define DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_AR_RT_URGENT_EN_SHIFT (1U) /*! AR_RT_URGENT_EN - DDRC ipa_ar_rt_urgent is enabled */ #define DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_AR_RT_URGENT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_AR_RT_URGENT_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_DDRC_URGENT_EN_AR_RT_URGENT_EN_MASK) /*! @} */ /*! @name RT_MASTER_ID_0_1 - DDRC real_time master 6bit extend-ID range 0 and range 1 */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_ID_MASK (0x3FU) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_ID_SHIFT (0U) /*! RANGE_0_ID - DDRC real_time master ID range 0 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_MASK_MASK (0x3F00U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_MASK_SHIFT (8U) /*! RANGE_0_MASK - DDRC real_time master ID range 0 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_EN_MASK (0x8000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_EN_SHIFT (15U) /*! RANGE_0_EN - DDRC real_time master ID range 0 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_0_EN_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_ID_MASK (0x3F0000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_ID_SHIFT (16U) /*! RANGE_1_ID - DDRC real_time master ID range 1 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_MASK_MASK (0x3F000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_MASK_SHIFT (24U) /*! RANGE_1_MASK - DDRC real_time master ID range 1 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_EN_MASK (0x80000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_EN_SHIFT (31U) /*! RANGE_1_EN - DDRC real_time master ID range 1 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_0_1_RANGE_1_EN_MASK) /*! @} */ /*! @name RT_MASTER_ID_2_3 - DDRC real_time master 6bit extend-ID range 2 and range 3 */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_ID_MASK (0x3FU) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_ID_SHIFT (0U) /*! RANGE_2_ID - DDRC real_time master ID range 2 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_MASK_MASK (0x3F00U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_MASK_SHIFT (8U) /*! RANGE_2_MASK - DDRC real_time master ID range 2 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_EN_MASK (0x8000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_EN_SHIFT (15U) /*! RANGE_2_EN - DDRC real_time master ID range 2 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_2_EN_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_ID_MASK (0x3F0000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_ID_SHIFT (16U) /*! RANGE_3_ID - DDRC real_time master ID range 3 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_MASK_MASK (0x3F000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_MASK_SHIFT (24U) /*! RANGE_3_MASK - DDRC real_time master ID range 3 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_EN_MASK (0x80000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_EN_SHIFT (31U) /*! RANGE_3_EN - DDRC real_time master ID range 3 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_2_3_RANGE_3_EN_MASK) /*! @} */ /*! @name AXI_PARITY_ERR_INJECT - DDRMIX AXI parity error injection register */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_WDATA_ERR_INJ_MASK (0x1U) #define DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_WDATA_ERR_INJ_SHIFT (0U) /*! WDATA_ERR_INJ - DDRMIX AXI parity error injection on wdatachk[0] */ #define DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_WDATA_ERR_INJ(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_WDATA_ERR_INJ_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_WDATA_ERR_INJ_MASK) #define DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_RDATA_ERR_INJ_MASK (0x10000U) #define DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_RDATA_ERR_INJ_SHIFT (16U) /*! RDATA_ERR_INJ - DDRMIX AXI parity error injection on rdatachk[0] */ #define DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_RDATA_ERR_INJ(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_RDATA_ERR_INJ_SHIFT)) & DDR_BLK_CTRL_DDRMIX_AXI_PARITY_ERR_INJECT_RDATA_ERR_INJ_MASK) /*! @} */ /*! @name RT_MASTER_ID_4_5 - DDRC real_time master 6bit extend-ID range 4 and range 5 */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_ID_MASK (0x3FU) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_ID_SHIFT (0U) /*! RANGE_4_ID - DDRC real_time master ID range 4 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_MASK_MASK (0x3F00U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_MASK_SHIFT (8U) /*! RANGE_4_MASK - DDRC real_time master ID range 4 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_EN_MASK (0x8000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_EN_SHIFT (15U) /*! RANGE_4_EN - DDRC real_time master ID range 4 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_4_EN_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_ID_MASK (0x3F0000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_ID_SHIFT (16U) /*! RANGE_5_ID - DDRC real_time master ID range 5 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_MASK_MASK (0x3F000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_MASK_SHIFT (24U) /*! RANGE_5_MASK - DDRC real_time master ID range 5 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_EN_MASK (0x80000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_EN_SHIFT (31U) /*! RANGE_5_EN - DDRC real_time master ID range 5 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_4_5_RANGE_5_EN_MASK) /*! @} */ /*! @name RT_MASTER_ID_6_7 - DDRC real_time master 6bit extend-ID range 6 and range 7 */ /*! @{ */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_ID_MASK (0x3FU) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_ID_SHIFT (0U) /*! RANGE_6_ID - DDRC real_time master ID range 6 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_MASK_MASK (0x3F00U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_MASK_SHIFT (8U) /*! RANGE_6_MASK - DDRC real_time master ID range 6 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_EN_MASK (0x8000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_EN_SHIFT (15U) /*! RANGE_6_EN - DDRC real_time master ID range 6 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_6_EN_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_ID_MASK (0x3F0000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_ID_SHIFT (16U) /*! RANGE_7_ID - DDRC real_time master ID range 7 ID */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_ID_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_ID_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_MASK_MASK (0x3F000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_MASK_SHIFT (24U) /*! RANGE_7_MASK - DDRC real_time master ID range 7 ID mask */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_MASK(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_MASK_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_MASK_MASK) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_EN_MASK (0x80000000U) #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_EN_SHIFT (31U) /*! RANGE_7_EN - DDRC real_time master ID range 7 enable */ #define DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_EN_SHIFT)) & DDR_BLK_CTRL_DDRMIX_RT_MASTER_ID_6_7_RANGE_7_EN_MASK) /*! @} */ /*! * @} */ /* end of group DDR_BLK_CTRL_DDRMIX_Register_Masks */ /* DDR_BLK_CTRL_DDRMIX - Peripheral instance base addresses */ /** Peripheral DDRC__BLK_CTRL_DDRMIX base address */ #define DDRC__BLK_CTRL_DDRMIX_BASE (0x4E010000u) /** Peripheral DDRC__BLK_CTRL_DDRMIX base pointer */ #define DDRC__BLK_CTRL_DDRMIX ((DDR_BLK_CTRL_DDRMIX_Type *)DDRC__BLK_CTRL_DDRMIX_BASE) /** Array initializer of DDR_BLK_CTRL_DDRMIX peripheral base addresses */ #define DDR_BLK_CTRL_DDRMIX_BASE_ADDRS { DDRC__BLK_CTRL_DDRMIX_BASE } /** Array initializer of DDR_BLK_CTRL_DDRMIX peripheral base pointers */ #define DDR_BLK_CTRL_DDRMIX_BASE_PTRS { DDRC__BLK_CTRL_DDRMIX } /*! * @} */ /* end of group DDR_BLK_CTRL_DDRMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDR_CMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_CMU_Peripheral_Access_Layer DDR_CMU Peripheral Access Layer * @{ */ /** DDR_CMU - Register Layout Typedef */ typedef struct { __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ __IO uint32_t SR; /**< Status Register, offset: 0x10 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ } DDR_CMU_Type; /* ---------------------------------------------------------------------------- -- DDR_CMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_CMU_Register_Masks DDR_CMU Register Masks * @{ */ /*! @name GCR - Global Configuration Register */ /*! @{ */ #define DDR_CMU_GCR_FCE_MASK (0x1U) #define DDR_CMU_GCR_FCE_SHIFT (0U) /*! FCE - Frequency Check Enable * 0b0..Stops frequency checking * 0b1..Starts frequency checking */ #define DDR_CMU_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_GCR_FCE_SHIFT)) & DDR_CMU_GCR_FCE_MASK) /*! @} */ /*! @name RCCR - Reference Count Configuration Register */ /*! @{ */ #define DDR_CMU_RCCR_REF_CNT_MASK (0xFFFFU) #define DDR_CMU_RCCR_REF_CNT_SHIFT (0U) /*! REF_CNT - Reference clock count */ #define DDR_CMU_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_RCCR_REF_CNT_SHIFT)) & DDR_CMU_RCCR_REF_CNT_MASK) /*! @} */ /*! @name HTCR - High Threshold Configuration Register */ /*! @{ */ #define DDR_CMU_HTCR_HFREF_MASK (0xFFFFFFU) #define DDR_CMU_HTCR_HFREF_SHIFT (0U) /*! HFREF - High frequency reference threshold */ #define DDR_CMU_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_HTCR_HFREF_SHIFT)) & DDR_CMU_HTCR_HFREF_MASK) /*! @} */ /*! @name LTCR - Low Threshold Configuration Register */ /*! @{ */ #define DDR_CMU_LTCR_LFREF_MASK (0xFFFFFFU) #define DDR_CMU_LTCR_LFREF_SHIFT (0U) /*! LFREF - Low Frequency Reference Threshold */ #define DDR_CMU_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_LTCR_LFREF_SHIFT)) & DDR_CMU_LTCR_LFREF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define DDR_CMU_SR_FLL_MASK (0x1U) #define DDR_CMU_SR_FLL_SHIFT (0U) /*! FLL - Frequency lower than low frequency reference threshold event status * 0b0..No FLL event * 0b1..FLL event occurred */ #define DDR_CMU_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_SR_FLL_SHIFT)) & DDR_CMU_SR_FLL_MASK) #define DDR_CMU_SR_FHH_MASK (0x2U) #define DDR_CMU_SR_FHH_SHIFT (1U) /*! FHH - Frequency higher than high frequency reference threshold event status * 0b0..No FHH event * 0b1..FHH event occurred */ #define DDR_CMU_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_SR_FHH_SHIFT)) & DDR_CMU_SR_FHH_MASK) #define DDR_CMU_SR_RS_MASK (0x10U) #define DDR_CMU_SR_RS_SHIFT (4U) /*! RS - Run Status * 0b0..Frequency check stopped * 0b1..Frequency check running */ #define DDR_CMU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_SR_RS_SHIFT)) & DDR_CMU_SR_RS_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define DDR_CMU_IER_FLLAIE_MASK (0x4U) #define DDR_CMU_IER_FLLAIE_SHIFT (2U) /*! FLLAIE - Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FLL event interrupt disabled * 0b1..Asynchronous FLL event interrupt enabled */ #define DDR_CMU_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_IER_FLLAIE_SHIFT)) & DDR_CMU_IER_FLLAIE_MASK) #define DDR_CMU_IER_FHHAIE_MASK (0x8U) #define DDR_CMU_IER_FHHAIE_SHIFT (3U) /*! FHHAIE - Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FHH event interrupt disabled * 0b1..Asynchronous FHH event interrupt enabled */ #define DDR_CMU_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << DDR_CMU_IER_FHHAIE_SHIFT)) & DDR_CMU_IER_FHHAIE_MASK) /*! @} */ /*! * @} */ /* end of group DDR_CMU_Register_Masks */ /* DDR_CMU - Peripheral instance base addresses */ /** Peripheral DDRC__CMU_1 base address */ #define DDRC__CMU_1_BASE (0x4E060000u) /** Peripheral DDRC__CMU_1 base pointer */ #define DDRC__CMU_1 ((DDR_CMU_Type *)DDRC__CMU_1_BASE) /** Peripheral DDRC__CMU_2 base address */ #define DDRC__CMU_2_BASE (0x4E070000u) /** Peripheral DDRC__CMU_2 base pointer */ #define DDRC__CMU_2 ((DDR_CMU_Type *)DDRC__CMU_2_BASE) /** Array initializer of DDR_CMU peripheral base addresses */ #define DDR_CMU_BASE_ADDRS { DDRC__CMU_1_BASE, DDRC__CMU_2_BASE } /** Array initializer of DDR_CMU peripheral base pointers */ #define DDR_CMU_BASE_PTRS { DDRC__CMU_1, DDRC__CMU_2 } /*! * @} */ /* end of group DDR_CMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDR_DDRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_DDRC_Peripheral_Access_Layer DDR_DDRC Peripheral Access Layer * @{ */ /** DDR_DDRC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x8 */ __IO uint32_t CS_BNDS; /**< Rank 0 Memory Bounds..Rank 1 Memory Bounds, array offset: 0x0, array step: 0x8 */ uint8_t RESERVED_0[4]; } CS_BNDS[2]; __IO uint32_t REMAP_EXT_0; /**< Remap Extended Region 0 Configuration, offset: 0x10 */ __IO uint32_t REMAP_EXT_1; /**< Remap Extended Region 1 Configuration, offset: 0x14 */ __IO uint32_t REMAP_EXT_2; /**< Remap Extended Region 2 Configuration, offset: 0x18 */ __IO uint32_t REMAP_EXT_3; /**< Remap Extended Region 3 Configuration, offset: 0x1C */ __IO uint32_t REMAP_0A; /**< Remap Region 0A Configuration, offset: 0x20 */ __IO uint32_t REMAP_0B; /**< Remap Region 0B Configuration, offset: 0x24 */ __IO uint32_t REMAP_1A; /**< Remap Region 1A Configuration, offset: 0x28 */ __IO uint32_t REMAP_1B; /**< Remap Region 1B Configuration, offset: 0x2C */ __IO uint32_t REMAP_2A; /**< Remap Region 2A Configuration, offset: 0x30 */ __IO uint32_t REMAP_2B; /**< Remap Region 2B Configuration, offset: 0x34 */ __IO uint32_t REMAP_3A; /**< Remap Region 3A Configuration, offset: 0x38 */ __IO uint32_t REMAP_3B; /**< Remap Region 3B Configuration, offset: 0x3C */ __IO uint32_t DDR_ADDR_DEC_0; /**< DDRC Address Decode 0, offset: 0x40 */ __IO uint32_t DDR_ADDR_DEC_1; /**< DDRC Address Decode 1, offset: 0x44 */ __IO uint32_t DDR_ADDR_DEC_2; /**< DDRC Address Decode 2, offset: 0x48 */ __IO uint32_t DDR_ADDR_DEC_3; /**< DDRC Address Decode 3, offset: 0x4C */ __IO uint32_t DDR_ADDR_DEC_4; /**< DDRC Address Decode 4, offset: 0x50 */ __IO uint32_t DDR_ADDR_DEC_5; /**< DDRC Address Decode 5, offset: 0x54 */ __IO uint32_t DDR_ADDR_DEC_6; /**< DDRC Address Decode 6, offset: 0x58 */ __IO uint32_t DDR_ADDR_DEC_7; /**< DDRC Address Decode 7, offset: 0x5C */ __IO uint32_t DDR_ADDR_DEC_8; /**< DDRC Address Decode 8, offset: 0x60 */ __IO uint32_t DDR_ADDR_DEC_9; /**< DDRC Address Decode 9, offset: 0x64 */ uint8_t RESERVED_0[24]; __IO uint32_t CS_CONFIG[2]; /**< Rank 0 Configuration..Rank 1 Configuration, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[120]; __IO uint32_t TIMING_CFG_3; /**< DDR SDRAM Timing Configuration 3, offset: 0x100 */ __IO uint32_t TIMING_CFG_0; /**< DDR SDRAM Timing Configuration 0, offset: 0x104 */ __IO uint32_t TIMING_CFG_1; /**< DDR SDRAM Timing Configuration 1, offset: 0x108 */ __IO uint32_t TIMING_CFG_2; /**< DDR SDRAM Timing Configuration 2, offset: 0x10C */ __IO uint32_t DDR_SDRAM_CFG; /**< DDR SDRAM Control Configuration, offset: 0x110 */ __IO uint32_t DDR_SDRAM_CFG_2; /**< DDR SDRAM Control Configuration 2, offset: 0x114 */ uint8_t RESERVED_2[8]; __IO uint32_t DDR_SDRAM_MD_CNTL; /**< DDR SDRAM Mode Control, offset: 0x120 */ __IO uint32_t DDR_SDRAM_INTERVAL; /**< DDR SDRAM Interval Configuration, offset: 0x124 */ __IO uint32_t DDR_DATA_INIT; /**< DDR SDRAM Data Initialization, offset: 0x128 */ uint8_t RESERVED_3[52]; __IO uint32_t TIMING_CFG_4; /**< DDR SDRAM Timing Configuration 4, offset: 0x160 */ uint8_t RESERVED_4[8]; __IO uint32_t TIMING_CFG_7; /**< DDR SDRAM Timing Configuration 7, offset: 0x16C */ __IO uint32_t DDR_ZQ_CNTL; /**< DDR SDRAM ZQ Calibration Control, offset: 0x170 */ uint8_t RESERVED_5[8]; __IO uint32_t DDR_SR_CNTR; /**< DDR SDRAM Self-Refresh Counter, offset: 0x17C */ uint8_t RESERVED_6[208]; __IO uint32_t TIMING_CFG_8; /**< DDR SDRAM Timing Configuration 8, offset: 0x250 */ __IO uint32_t TIMING_CFG_9; /**< DDR SDRAM timing configuration 9, offset: 0x254 */ __IO uint32_t TIMING_CFG_10; /**< DDR SDRAM Timing Configuration 10, offset: 0x258 */ __IO uint32_t TIMING_CFG_11; /**< DDR SDRAM Timing Configuration 11, offset: 0x25C */ __IO uint32_t DDR_SDRAM_CFG_3; /**< DDR SDRAM Control Configuration 3, offset: 0x260 */ __IO uint32_t DDR_SDRAM_CFG_4; /**< DDR SDRAM Control Configuration 4, offset: 0x264 */ __IO uint32_t DDR_SDRAM_CFG_5; /**< DDR SDRAM Control Configuration 5, offset: 0x268 */ __IO uint32_t DDR_SDRAM_CFG_6; /**< DDR SDRAM Control Configuration 6, offset: 0x26C */ __IO uint32_t DDR_SDRAM_MD_CNTL2; /**< DDR SDRAM mode control 2, offset: 0x270 */ uint8_t RESERVED_7[24]; __I uint32_t DDR_SDRAM_MPR4; /**< DDR SDRAM multi-purpose register 4, offset: 0x28C */ __IO uint32_t DDR_SDRAM_MPR5; /**< DDR SDRAM multi-purpose register 5, offset: 0x290 */ uint8_t RESERVED_8[44]; __I uint32_t DDR_SDRAM_REF_RATE; /**< DDR Refresh Rate, offset: 0x2C0 */ uint8_t RESERVED_9[60]; __IO uint32_t TIMING_CFG_12; /**< DDR SDRAM Timing Configuration 12, offset: 0x300 */ __IO uint32_t TIMING_CFG_13; /**< DDR SDRAM Timing Configuration 13, offset: 0x304 */ __IO uint32_t TIMING_CFG_14; /**< DDR SDRAM Timing Configuration 14, offset: 0x308 */ __IO uint32_t TIMING_CFG_15; /**< DDR SDRAM Timing Configuration 15, offset: 0x30C */ __IO uint32_t TIMING_CFG_16; /**< DDR SDRAM Timing Configuration 16, offset: 0x310 */ __IO uint32_t TIMING_CFG_17; /**< DDR SDRAM Timing Configuration 17, offset: 0x314 */ uint8_t RESERVED_10[1256]; __IO uint32_t TX_CFG_1; /**< Transaction Configuration Register 1, offset: 0x800 */ __IO uint32_t TX_CFG_2; /**< Transaction Configuration Register 2, offset: 0x804 */ uint8_t RESERVED_11[796]; __IO uint32_t DDRDSR_2; /**< DDR SDRAM Debug Status 2, offset: 0xB24 */ uint8_t RESERVED_12[208]; __I uint32_t DDR_IP_REV1; /**< DDRC Revision 1, offset: 0xBF8 */ uint8_t RESERVED_13[260]; __IO uint32_t DDR_MTCR; /**< DDR SDRAM Memory Test Control, offset: 0xD00 */ uint8_t RESERVED_14[28]; __IO uint32_t DDR_MTP[10]; /**< DDR SDRAM Memory Test Pattern n, array offset: 0xD20, array step: 0x4 */ uint8_t RESERVED_15[24]; __IO uint32_t DDR_MT_ST_EXT_ADDR; /**< DDR SDRAM Memory Test Start Extended Address, offset: 0xD60 */ __IO uint32_t DDR_MT_ST_ADDR; /**< DDR SDRAM Memory Test Start Address, offset: 0xD64 */ __IO uint32_t DDR_MT_END_EXT_ADDR; /**< DDR SDRAM Memory Test End Extended Address, offset: 0xD68 */ __IO uint32_t DDR_MT_END_ADDR; /**< DDR SDRAM Memory Test End Address, offset: 0xD6C */ uint8_t RESERVED_16[656]; __IO uint32_t ERR_EN; /**< Error Enable, offset: 0x1000 */ uint8_t RESERVED_17[252]; __IO uint32_t DATA_ERR_INJECT_HI; /**< Memory Data Path Error Injection Mask High, offset: 0x1100 */ __IO uint32_t DATA_ERR_INJECT_LO; /**< Memory Data Path Error Injection Mask Low, offset: 0x1104 */ __IO uint32_t ERR_INJECT; /**< Memory Data Path Error Injection Mask ECC, offset: 0x1108 */ __IO uint32_t ADDR_ERR_INJ; /**< Address Error Inject, offset: 0x110C */ __IO uint32_t EXT_ADDR_ERR_INJ; /**< Extended Address Error Inject, offset: 0x1110 */ uint8_t RESERVED_18[4]; __IO uint32_t CAPTURE_EXT_DATA_HI; /**< Memory Extended Data Path Read Capture High, offset: 0x1118 */ __IO uint32_t CAPTURE_EXT_DATA_LO; /**< Memory Extended Data Path Read Capture Low, offset: 0x111C */ __IO uint32_t CAPTURE_DATA_HI; /**< Memory Data Path Read Capture High, offset: 0x1120 */ __IO uint32_t CAPTURE_DATA_LO; /**< Memory Data Path Read Capture Low, offset: 0x1124 */ __IO uint32_t CAPTURE_ECC; /**< Memory Data Path Read Capture ECC, offset: 0x1128 */ uint8_t RESERVED_19[20]; __IO uint32_t ERR_DETECT; /**< Memory Error Detect, offset: 0x1140 */ __IO uint32_t ERR_DISABLE; /**< Memory Error Disable, offset: 0x1144 */ __IO uint32_t ERR_INT_EN; /**< Memory Error Interrupt Enable, offset: 0x1148 */ __IO uint32_t CAPTURE_ATTRIBUTES; /**< Memory Error Attributes Capture, offset: 0x114C */ __IO uint32_t CAPTURE_ADDRESS; /**< Memory Error Address Capture, offset: 0x1150 */ __IO uint32_t CAPTURE_EXT_ADDRESS; /**< Memory Error Extended Address Capture, offset: 0x1154 */ __IO uint32_t ERR_SBE; /**< Single-Bit ECC Memory Error Management, offset: 0x1158 */ uint8_t RESERVED_20[180]; __IO uint32_t REG_CRC_GRP_1; /**< Register CRC Code For Group 1, offset: 0x1210 */ __IO uint32_t REG_CRC_GRP_2; /**< Register CRC Code For Group 2, offset: 0x1214 */ uint8_t RESERVED_21[8]; __IO uint32_t ECC_EXT_REG_0; /**< ECC Extended Region 0 Configuration, offset: 0x1220 */ __IO uint32_t ECC_EXT_REG_1; /**< ECC Extended Region 1 Configuration, offset: 0x1224 */ __IO uint32_t ECC_EXT_REG_2; /**< ECC Extended Region 2 Configuration, offset: 0x1228 */ __IO uint32_t ECC_EXT_REG_3; /**< ECC Extended Region 3 Configuration, offset: 0x122C */ __IO uint32_t ECC_EXT_REG_4; /**< ECC Extended Region 4 Configuration, offset: 0x1230 */ __IO uint32_t ECC_EXT_REG_5; /**< ECC Extended Region 5 Configuration, offset: 0x1234 */ __IO uint32_t ECC_EXT_REG_6; /**< ECC Extended Region 6 Configuration, offset: 0x1238 */ __IO uint32_t ECC_EXT_REG_7; /**< ECC Extended Region 7 Configuration, offset: 0x123C */ __IO uint32_t ECC_REG_0; /**< ECC Region 0 Configuration, offset: 0x1240 */ __IO uint32_t ECC_REG_1; /**< ECC Region 1 Configuration, offset: 0x1244 */ __IO uint32_t ECC_REG_2; /**< ECC Region 2 Configuration, offset: 0x1248 */ __IO uint32_t ECC_REG_3; /**< ECC Region 3 Configuration, offset: 0x124C */ __IO uint32_t ECC_REG_4; /**< ECC Region 4 Configuration, offset: 0x1250 */ __IO uint32_t ECC_REG_5; /**< ECC Region 5 Configuration, offset: 0x1254 */ __IO uint32_t ECC_REG_6; /**< ECC Region 6 Configuration, offset: 0x1258 */ __IO uint32_t ECC_REG_7; /**< ECC Region 7 Configuration, offset: 0x125C */ uint8_t RESERVED_22[64416]; __IO uint32_t PMGC0; /**< Performance Monitor Global Control, offset: 0x10E00 */ uint8_t RESERVED_23[12]; __IO uint32_t PMLCA0; /**< Performance Monitor Local Control A0, offset: 0x10E10 */ __IO uint32_t PMLCB0; /**< Performance Monitor Local Control B0, offset: 0x10E14 */ __IO uint32_t PMC0A; /**< PMC 0a, offset: 0x10E18 */ __IO uint32_t PMC0B; /**< PMC 0b, offset: 0x10E1C */ __IO uint32_t PMLCA1; /**< Performance Monitor Local Control A, offset: 0x10E20 */ __IO uint32_t PMLCB1; /**< Performance Monitor Local Control B, offset: 0x10E24 */ __IO uint32_t PMC1; /**< Performance Monitor Counter, offset: 0x10E28 */ uint8_t RESERVED_24[4]; __IO uint32_t PMLCA2; /**< Performance Monitor Local Control A, offset: 0x10E30 */ __IO uint32_t PMLCB2; /**< Performance Monitor Local Control B, offset: 0x10E34 */ __IO uint32_t PMC2; /**< Performance Monitor Counter, offset: 0x10E38 */ uint8_t RESERVED_25[4]; __IO uint32_t PMLCA3; /**< Performance Monitor Local Control A, offset: 0x10E40 */ __IO uint32_t PMLCB3; /**< Performance Monitor Local Control B, offset: 0x10E44 */ __IO uint32_t PMC3; /**< Performance Monitor Counter, offset: 0x10E48 */ uint8_t RESERVED_26[4]; __IO uint32_t PMLCA4; /**< Performance Monitor Local Control A, offset: 0x10E50 */ __IO uint32_t PMLCB4; /**< Performance Monitor Local Control B, offset: 0x10E54 */ __IO uint32_t PMC4; /**< Performance Monitor Counter, offset: 0x10E58 */ uint8_t RESERVED_27[4]; __IO uint32_t PMLCA5; /**< Performance Monitor Local Control A, offset: 0x10E60 */ __IO uint32_t PMLCB5; /**< Performance Monitor Local Control B, offset: 0x10E64 */ __IO uint32_t PMC5; /**< Performance Monitor Counter, offset: 0x10E68 */ uint8_t RESERVED_28[4]; __IO uint32_t PMLCA6; /**< Performance Monitor Local Control A, offset: 0x10E70 */ __IO uint32_t PMLCB6; /**< Performance Monitor Local Control B, offset: 0x10E74 */ __IO uint32_t PMC6; /**< Performance Monitor Counter, offset: 0x10E78 */ uint8_t RESERVED_29[4]; __IO uint32_t PMLCA7; /**< Performance Monitor Local Control A, offset: 0x10E80 */ __IO uint32_t PMLCB7; /**< Performance Monitor Local Control B, offset: 0x10E84 */ __IO uint32_t PMC7; /**< Performance Monitor Counter, offset: 0x10E88 */ uint8_t RESERVED_30[4]; __IO uint32_t PMLCA8; /**< Performance Monitor Local Control A, offset: 0x10E90 */ __IO uint32_t PMLCB8; /**< Performance Monitor Local Control B, offset: 0x10E94 */ __IO uint32_t PMC8; /**< Performance Monitor Counter, offset: 0x10E98 */ uint8_t RESERVED_31[4]; __IO uint32_t PMLCA9; /**< Performance Monitor Local Control A, offset: 0x10EA0 */ __IO uint32_t PMLCB9; /**< Performance Monitor Local Control B, offset: 0x10EA4 */ __IO uint32_t PMC9; /**< Performance Monitor Counter, offset: 0x10EA8 */ uint8_t RESERVED_32[4]; __IO uint32_t PMLCA10; /**< Performance Monitor Local Control A, offset: 0x10EB0 */ __IO uint32_t PMLCB10; /**< Performance Monitor Local Control B, offset: 0x10EB4 */ __IO uint32_t PMC10; /**< Performance Monitor Counter, offset: 0x10EB8 */ } DDR_DDRC_Type; /* ---------------------------------------------------------------------------- -- DDR_DDRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_DDRC_Register_Masks DDR_DDRC Register Masks * @{ */ /*! @name CS_BNDS - Rank 0 Memory Bounds..Rank 1 Memory Bounds */ /*! @{ */ #define DDR_DDRC_CS_BNDS_EA_MASK (0xFFFFU) #define DDR_DDRC_CS_BNDS_EA_SHIFT (0U) /*! EA - Ending Address */ #define DDR_DDRC_CS_BNDS_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CS_BNDS_EA_SHIFT)) & DDR_DDRC_CS_BNDS_EA_MASK) #define DDR_DDRC_CS_BNDS_SA_MASK (0xFFFF0000U) #define DDR_DDRC_CS_BNDS_SA_SHIFT (16U) /*! SA - Starting Address */ #define DDR_DDRC_CS_BNDS_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CS_BNDS_SA_SHIFT)) & DDR_DDRC_CS_BNDS_SA_MASK) /*! @} */ /* The count of DDR_DDRC_CS_BNDS */ #define DDR_DDRC_CS_BNDS_COUNT (2U) /*! @name REMAP_EXT_0 - Remap Extended Region 0 Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_EXT_0_EXT_REG_0_EA_MASK (0xFFU) #define DDR_DDRC_REMAP_EXT_0_EXT_REG_0_EA_SHIFT (0U) /*! EXT_REG_0_EA - Region 0 Extended Ending Address */ #define DDR_DDRC_REMAP_EXT_0_EXT_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_0_EXT_REG_0_EA_SHIFT)) & DDR_DDRC_REMAP_EXT_0_EXT_REG_0_EA_MASK) #define DDR_DDRC_REMAP_EXT_0_EXT_REG_0_SA_MASK (0xFF00U) #define DDR_DDRC_REMAP_EXT_0_EXT_REG_0_SA_SHIFT (8U) /*! EXT_REG_0_SA - Region 0 Extended Starting Address */ #define DDR_DDRC_REMAP_EXT_0_EXT_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_0_EXT_REG_0_SA_SHIFT)) & DDR_DDRC_REMAP_EXT_0_EXT_REG_0_SA_MASK) #define DDR_DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_MASK (0xFF0000U) #define DDR_DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_SHIFT (16U) /*! REG_0_EXT_REMAP_ADDR - Region 0 Extended Remap Starting Address */ #define DDR_DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_EXT_0_REG_0_EXT_REMAP_ADDR_MASK) /*! @} */ /*! @name REMAP_EXT_1 - Remap Extended Region 1 Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_EXT_1_EXT_REG_1_EA_MASK (0xFFU) #define DDR_DDRC_REMAP_EXT_1_EXT_REG_1_EA_SHIFT (0U) /*! EXT_REG_1_EA - Region 1 Extended Ending Address */ #define DDR_DDRC_REMAP_EXT_1_EXT_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_1_EXT_REG_1_EA_SHIFT)) & DDR_DDRC_REMAP_EXT_1_EXT_REG_1_EA_MASK) #define DDR_DDRC_REMAP_EXT_1_EXT_REG_1_SA_MASK (0xFF00U) #define DDR_DDRC_REMAP_EXT_1_EXT_REG_1_SA_SHIFT (8U) /*! EXT_REG_1_SA - Region 1 Extended Starting Address */ #define DDR_DDRC_REMAP_EXT_1_EXT_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_1_EXT_REG_1_SA_SHIFT)) & DDR_DDRC_REMAP_EXT_1_EXT_REG_1_SA_MASK) #define DDR_DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_MASK (0xFF0000U) #define DDR_DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_SHIFT (16U) /*! REG_1_EXT_REMAP_ADDR - Region 1 Extended Remap Starting Address */ #define DDR_DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_EXT_1_REG_1_EXT_REMAP_ADDR_MASK) /*! @} */ /*! @name REMAP_EXT_2 - Remap Extended Region 2 Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_EXT_2_EXT_REG_2_EA_MASK (0xFFU) #define DDR_DDRC_REMAP_EXT_2_EXT_REG_2_EA_SHIFT (0U) /*! EXT_REG_2_EA - Region 2 Extended Ending Address */ #define DDR_DDRC_REMAP_EXT_2_EXT_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_2_EXT_REG_2_EA_SHIFT)) & DDR_DDRC_REMAP_EXT_2_EXT_REG_2_EA_MASK) #define DDR_DDRC_REMAP_EXT_2_EXT_REG_2_SA_MASK (0xFF00U) #define DDR_DDRC_REMAP_EXT_2_EXT_REG_2_SA_SHIFT (8U) /*! EXT_REG_2_SA - Region 2 Extended Starting Address */ #define DDR_DDRC_REMAP_EXT_2_EXT_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_2_EXT_REG_2_SA_SHIFT)) & DDR_DDRC_REMAP_EXT_2_EXT_REG_2_SA_MASK) #define DDR_DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_MASK (0xFF0000U) #define DDR_DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_SHIFT (16U) /*! REG_2_EXT_REMAP_ADDR - Region 2 Extended Remap Starting Address */ #define DDR_DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_EXT_2_REG_2_EXT_REMAP_ADDR_MASK) /*! @} */ /*! @name REMAP_EXT_3 - Remap Extended Region 3 Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_EXT_3_EXT_REG_3_EA_MASK (0xFFU) #define DDR_DDRC_REMAP_EXT_3_EXT_REG_3_EA_SHIFT (0U) /*! EXT_REG_3_EA - Region 3 Extended Ending Address */ #define DDR_DDRC_REMAP_EXT_3_EXT_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_3_EXT_REG_3_EA_SHIFT)) & DDR_DDRC_REMAP_EXT_3_EXT_REG_3_EA_MASK) #define DDR_DDRC_REMAP_EXT_3_EXT_REG_3_SA_MASK (0xFF00U) #define DDR_DDRC_REMAP_EXT_3_EXT_REG_3_SA_SHIFT (8U) /*! EXT_REG_3_SA - Region 3 Extended Starting Address */ #define DDR_DDRC_REMAP_EXT_3_EXT_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_3_EXT_REG_3_SA_SHIFT)) & DDR_DDRC_REMAP_EXT_3_EXT_REG_3_SA_MASK) #define DDR_DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_MASK (0xFF0000U) #define DDR_DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_SHIFT (16U) /*! REG_3_EXT_REMAP_ADDR - Region 3 Extended Remap Starting Address */ #define DDR_DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_EXT_3_REG_3_EXT_REMAP_ADDR_MASK) /*! @} */ /*! @name REMAP_0A - Remap Region 0A Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK (0xFFFU) #define DDR_DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT (0U) /*! REG_0_REMAP_ADDR - Region 0 Remap Starting Address */ #define DDR_DDRC_REMAP_0A_REG_0_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK) #define DDR_DDRC_REMAP_0A_REG_0_REMAP_EN_MASK (0x80000000U) #define DDR_DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT (31U) /*! REG_0_REMAP_EN - Region 0 Remap Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_REMAP_0A_REG_0_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT)) & DDR_DDRC_REMAP_0A_REG_0_REMAP_EN_MASK) /*! @} */ /*! @name REMAP_0B - Remap Region 0B Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_0B_REG_0_EA_MASK (0xFFFU) #define DDR_DDRC_REMAP_0B_REG_0_EA_SHIFT (0U) /*! REG_0_EA - Region 0 Ending Address */ #define DDR_DDRC_REMAP_0B_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_0B_REG_0_EA_SHIFT)) & DDR_DDRC_REMAP_0B_REG_0_EA_MASK) #define DDR_DDRC_REMAP_0B_REG_0_SA_MASK (0xFFF0000U) #define DDR_DDRC_REMAP_0B_REG_0_SA_SHIFT (16U) /*! REG_0_SA - Region 0 Starting Address */ #define DDR_DDRC_REMAP_0B_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_0B_REG_0_SA_SHIFT)) & DDR_DDRC_REMAP_0B_REG_0_SA_MASK) /*! @} */ /*! @name REMAP_1A - Remap Region 1A Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK (0xFFFU) #define DDR_DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT (0U) /*! REG_1_REMAP_ADDR - Region 1 Remap Starting Address */ #define DDR_DDRC_REMAP_1A_REG_1_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK) #define DDR_DDRC_REMAP_1A_REG_1_REMAP_EN_MASK (0x80000000U) #define DDR_DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT (31U) /*! REG_1_REMAP_EN - Region 1 Remap Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_REMAP_1A_REG_1_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT)) & DDR_DDRC_REMAP_1A_REG_1_REMAP_EN_MASK) /*! @} */ /*! @name REMAP_1B - Remap Region 1B Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_1B_REG_1_EA_MASK (0xFFFU) #define DDR_DDRC_REMAP_1B_REG_1_EA_SHIFT (0U) /*! REG_1_EA - Region 1 Ending Address */ #define DDR_DDRC_REMAP_1B_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_1B_REG_1_EA_SHIFT)) & DDR_DDRC_REMAP_1B_REG_1_EA_MASK) #define DDR_DDRC_REMAP_1B_REG_1_SA_MASK (0xFFF0000U) #define DDR_DDRC_REMAP_1B_REG_1_SA_SHIFT (16U) /*! REG_1_SA - Region 1 Starting Address */ #define DDR_DDRC_REMAP_1B_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_1B_REG_1_SA_SHIFT)) & DDR_DDRC_REMAP_1B_REG_1_SA_MASK) /*! @} */ /*! @name REMAP_2A - Remap Region 2A Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK (0xFFFU) #define DDR_DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT (0U) /*! REG_2_REMAP_ADDR - Region 2 Remap Starting Address */ #define DDR_DDRC_REMAP_2A_REG_2_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK) #define DDR_DDRC_REMAP_2A_REG_2_REMAP_EN_MASK (0x80000000U) #define DDR_DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT (31U) /*! REG_2_REMAP_EN - Region 2 Remap Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_REMAP_2A_REG_2_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT)) & DDR_DDRC_REMAP_2A_REG_2_REMAP_EN_MASK) /*! @} */ /*! @name REMAP_2B - Remap Region 2B Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_2B_REG_2_EA_MASK (0xFFFU) #define DDR_DDRC_REMAP_2B_REG_2_EA_SHIFT (0U) /*! REG_2_EA - Region 2 Ending Address */ #define DDR_DDRC_REMAP_2B_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_2B_REG_2_EA_SHIFT)) & DDR_DDRC_REMAP_2B_REG_2_EA_MASK) #define DDR_DDRC_REMAP_2B_REG_2_SA_MASK (0xFFF0000U) #define DDR_DDRC_REMAP_2B_REG_2_SA_SHIFT (16U) /*! REG_2_SA - Region 2 Starting Address */ #define DDR_DDRC_REMAP_2B_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_2B_REG_2_SA_SHIFT)) & DDR_DDRC_REMAP_2B_REG_2_SA_MASK) /*! @} */ /*! @name REMAP_3A - Remap Region 3A Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK (0xFFFU) #define DDR_DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT (0U) /*! REG_3_REMAP_ADDR - Region 3 Remap Starting Address */ #define DDR_DDRC_REMAP_3A_REG_3_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT)) & DDR_DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK) #define DDR_DDRC_REMAP_3A_REG_3_REMAP_EN_MASK (0x80000000U) #define DDR_DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT (31U) /*! REG_3_REMAP_EN - Region 3 Remap Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_REMAP_3A_REG_3_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT)) & DDR_DDRC_REMAP_3A_REG_3_REMAP_EN_MASK) /*! @} */ /*! @name REMAP_3B - Remap Region 3B Configuration */ /*! @{ */ #define DDR_DDRC_REMAP_3B_REG_3_EA_MASK (0xFFFU) #define DDR_DDRC_REMAP_3B_REG_3_EA_SHIFT (0U) /*! REG_3_EA - Region 3 Ending Address */ #define DDR_DDRC_REMAP_3B_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_3B_REG_3_EA_SHIFT)) & DDR_DDRC_REMAP_3B_REG_3_EA_MASK) #define DDR_DDRC_REMAP_3B_REG_3_SA_MASK (0xFFF0000U) #define DDR_DDRC_REMAP_3B_REG_3_SA_SHIFT (16U) /*! REG_3_SA - Region 3 Starting Address */ #define DDR_DDRC_REMAP_3B_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REMAP_3B_REG_3_SA_SHIFT)) & DDR_DDRC_REMAP_3B_REG_3_SA_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_0 - DDRC Address Decode 0 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT (2U) /*! ROW14_OVRD - Row 14 Override */ #define DDR_DDRC_DDR_ADDR_DEC_0_ROW14_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT (10U) /*! ROW15_OVRD - Row 15 Override */ #define DDR_DDRC_DDR_ADDR_DEC_0_ROW15_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT (18U) /*! ROW16_OVRD - Row 16 Override */ #define DDR_DDRC_DDR_ADDR_DEC_0_ROW16_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT (26U) /*! ROW17_OVRD - Row 17 Override */ #define DDR_DDRC_DDR_ADDR_DEC_0_ROW17_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_1 - DDRC Address Decode 1 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT (2U) /*! ROW10_OVRD - Row 10 Override */ #define DDR_DDRC_DDR_ADDR_DEC_1_ROW10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT (10U) /*! ROW11_OVRD - Row 11 Override */ #define DDR_DDRC_DDR_ADDR_DEC_1_ROW11_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT (18U) /*! ROW12_OVRD - Row 12 Override */ #define DDR_DDRC_DDR_ADDR_DEC_1_ROW12_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT (26U) /*! ROW13_OVRD - Row 13 Override */ #define DDR_DDRC_DDR_ADDR_DEC_1_ROW13_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_2 - DDRC Address Decode 2 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT (2U) /*! ROW6_OVRD - Row 6 Override */ #define DDR_DDRC_DDR_ADDR_DEC_2_ROW6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT (10U) /*! ROW7_OVRD - Row 7 Override */ #define DDR_DDRC_DDR_ADDR_DEC_2_ROW7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT (18U) /*! ROW8_OVRD - Row 8 Override */ #define DDR_DDRC_DDR_ADDR_DEC_2_ROW8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT (26U) /*! ROW9_OVRD - Row 9 Override */ #define DDR_DDRC_DDR_ADDR_DEC_2_ROW9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_3 - DDRC Address Decode 3 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT (2U) /*! ROW2_OVRD - Row 2 Override */ #define DDR_DDRC_DDR_ADDR_DEC_3_ROW2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT (10U) /*! ROW3_OVRD - Row 3 Override */ #define DDR_DDRC_DDR_ADDR_DEC_3_ROW3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT (18U) /*! ROW4_OVRD - Row 4 Override */ #define DDR_DDRC_DDR_ADDR_DEC_3_ROW4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT (26U) /*! ROW5_OVRD - Row 5 Override */ #define DDR_DDRC_DDR_ADDR_DEC_3_ROW5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_4 - DDRC Address Decode 4 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT (2U) /*! COL9_OVRD - Col 9 Override */ #define DDR_DDRC_DDR_ADDR_DEC_4_COL9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT (10U) /*! COL10_OVRD - Col 10 Override */ #define DDR_DDRC_DDR_ADDR_DEC_4_COL10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT (18U) /*! ROW0_OVRD - Row 0 Override */ #define DDR_DDRC_DDR_ADDR_DEC_4_ROW0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT (26U) /*! ROW1_OVRD - Row 1 Override */ #define DDR_DDRC_DDR_ADDR_DEC_4_ROW1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_5 - DDRC Address Decode 5 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT (2U) /*! COL5_OVRD - Col 5 Override */ #define DDR_DDRC_DDR_ADDR_DEC_5_COL5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT (10U) /*! COL6_OVRD - Col 6 Override */ #define DDR_DDRC_DDR_ADDR_DEC_5_COL6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT (18U) /*! COL7_OVRD - Col 7 Override */ #define DDR_DDRC_DDR_ADDR_DEC_5_COL7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT (26U) /*! COL8_OVRD - Col 8 Override */ #define DDR_DDRC_DDR_ADDR_DEC_5_COL8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_6 - DDRC Address Decode 6 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT (2U) /*! COL1_OVRD - Col 1 Override */ #define DDR_DDRC_DDR_ADDR_DEC_6_COL1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT (10U) /*! COL2_OVRD - Col 2 Override */ #define DDR_DDRC_DDR_ADDR_DEC_6_COL2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT (18U) /*! COL3_OVRD - Col 3 Override */ #define DDR_DDRC_DDR_ADDR_DEC_6_COL3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT (26U) /*! COL4_OVRD - Col 4 Override */ #define DDR_DDRC_DDR_ADDR_DEC_6_COL4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_7 - DDRC Address Decode 7 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT (2U) /*! CID1_OVRD - CID 1 Override */ #define DDR_DDRC_DDR_ADDR_DEC_7_CID1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT (10U) /*! BA0_OVRD - Bank 0 Override */ #define DDR_DDRC_DDR_ADDR_DEC_7_BA0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT (18U) /*! BA1_OVRD - Bank 1 Override */ #define DDR_DDRC_DDR_ADDR_DEC_7_BA1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT (26U) /*! COL0_OVRD - Col 0 Override */ #define DDR_DDRC_DDR_ADDR_DEC_7_COL0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_8 - DDRC Address Decode 8 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK (0xFCU) #define DDR_DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT (2U) /*! BG1_OVRD - Bank Group 1 Override */ #define DDR_DDRC_DDR_ADDR_DEC_8_BG1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK (0xFC00U) #define DDR_DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT (10U) /*! CS0_OVRD - Interleaved Rank 0 Override */ #define DDR_DDRC_DDR_ADDR_DEC_8_CS0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK (0xFC0000U) #define DDR_DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT (18U) /*! CS1_OVRD - Interleaved Rank 1 Override */ #define DDR_DDRC_DDR_ADDR_DEC_8_CS1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT (26U) /*! CID0_OVRD - CID 0 Override */ #define DDR_DDRC_DDR_ADDR_DEC_8_CID0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK) /*! @} */ /*! @name DDR_ADDR_DEC_9 - DDRC Address Decode 9 */ /*! @{ */ #define DDR_DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK (0x1U) #define DDR_DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT (0U) /*! ADDR_DEC_OVRD - Address Decode Override */ #define DDR_DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK) #define DDR_DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK (0xFC000000U) #define DDR_DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT (26U) /*! BG0_OVRD - Bank Group 0 Override */ #define DDR_DDRC_DDR_ADDR_DEC_9_BG0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT)) & DDR_DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK) /*! @} */ /*! @name CS_CONFIG - Rank 0 Configuration..Rank 1 Configuration */ /*! @{ */ #define DDR_DDRC_CS_CONFIG_COL_BITS_CS_MASK (0x7U) #define DDR_DDRC_CS_CONFIG_COL_BITS_CS_SHIFT (0U) /*! COL_BITS_CS - Column Bits * 0b000..8 * 0b001..9 * 0b010..10 * 0b011..11 * 0b111..7 * *.. */ #define DDR_DDRC_CS_CONFIG_COL_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CS_CONFIG_COL_BITS_CS_SHIFT)) & DDR_DDRC_CS_CONFIG_COL_BITS_CS_MASK) #define DDR_DDRC_CS_CONFIG_BG_BITS_CS_MASK (0x30U) #define DDR_DDRC_CS_CONFIG_BG_BITS_CS_SHIFT (4U) /*! BG_BITS_CS - Bank Group Bits * 0b00..0 * 0b01..Must be set to 1 to enable the 3rd bank address bit for LPDDR4x memories. * 0b10..Reserved */ #define DDR_DDRC_CS_CONFIG_BG_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CS_CONFIG_BG_BITS_CS_SHIFT)) & DDR_DDRC_CS_CONFIG_BG_BITS_CS_MASK) #define DDR_DDRC_CS_CONFIG_ROW_BITS_CS_MASK (0x700U) #define DDR_DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT (8U) /*! ROW_BITS_CS - Row Bits * 0b000..12 * 0b001..13 * 0b010..14 * 0b011..15 * 0b100..16 * 0b101..17 * 0b110..18 */ #define DDR_DDRC_CS_CONFIG_ROW_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT)) & DDR_DDRC_CS_CONFIG_ROW_BITS_CS_MASK) #define DDR_DDRC_CS_CONFIG_AP_EN_MASK (0x800000U) #define DDR_DDRC_CS_CONFIG_AP_EN_SHIFT (23U) /*! AP_EN - Auto-Precharge Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_CS_CONFIG_AP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CS_CONFIG_AP_EN_SHIFT)) & DDR_DDRC_CS_CONFIG_AP_EN_MASK) #define DDR_DDRC_CS_CONFIG_CS_EN_MASK (0x80000000U) #define DDR_DDRC_CS_CONFIG_CS_EN_SHIFT (31U) /*! CS_EN - Rank Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_CS_CONFIG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CS_CONFIG_CS_EN_SHIFT)) & DDR_DDRC_CS_CONFIG_CS_EN_MASK) /*! @} */ /* The count of DDR_DDRC_CS_CONFIG */ #define DDR_DDRC_CS_CONFIG_COUNT (2U) /*! @name TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_3_EXT_WRTORD_MASK (0x1U) #define DDR_DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT (0U) /*! EXT_WRTORD - Extended Write-To-Read Time */ #define DDR_DDRC_TIMING_CFG_3_EXT_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_WRTORD_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK (0x2U) #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT (1U) /*! EXT_ACTTOACT - Extended Activate-To-Activate Time */ #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK (0x8U) #define DDR_DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT (3U) /*! EXT_FOUR_ACT - Extended Four Activate */ #define DDR_DDRC_TIMING_CFG_3_EXT_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK (0x30U) #define DDR_DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT (4U) /*! EXT_CKE_PLS - Extended MCKE Pulse */ #define DDR_DDRC_TIMING_CFG_3_EXT_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_WRREC_MASK (0x300U) #define DDR_DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT (8U) /*! EXT_WRREC - Extended Write Recovery * 0b11.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_3_EXT_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_WRREC_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK (0x800U) #define DDR_DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT (11U) /*! EXT_WR_LAT_2 - Extended Write Latency 2 */ #define DDR_DDRC_TIMING_CFG_3_EXT_WR_LAT_2(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_CASLAT_MASK (0x7000U) #define DDR_DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT (12U) /*! EXT_CASLAT - Extended CAS Latency */ #define DDR_DDRC_TIMING_CFG_3_EXT_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_CASLAT_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_REFREC_MASK (0x3F0000U) #define DDR_DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT (16U) /*! EXT_REFREC - Extended Refresh Recovery */ #define DDR_DDRC_TIMING_CFG_3_EXT_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_REFREC_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK (0xC00000U) #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT (22U) /*! EXT_ACTTORW - Extended Activate To Read Or Write Time */ #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK (0x7000000U) #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT (24U) /*! EXT_ACTTOPRE - Extended Activate-To-Precharge Time */ #define DDR_DDRC_TIMING_CFG_3_EXT_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK) #define DDR_DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK (0x30000000U) #define DDR_DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT (28U) /*! EXT_PRETOACT - Extended Precharge-To-Activate Time */ #define DDR_DDRC_TIMING_CFG_3_EXT_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT)) & DDR_DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK) /*! @} */ /*! @name TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_0_MRS_CYC_MASK (0x3FU) #define DDR_DDRC_TIMING_CFG_0_MRS_CYC_SHIFT (0U) /*! MRS_CYC - MRW Cycle Time * 0b000000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_0_MRS_CYC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_MRS_CYC_SHIFT)) & DDR_DDRC_TIMING_CFG_0_MRS_CYC_MASK) #define DDR_DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK (0x1000U) #define DDR_DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT (12U) /*! EXT_ACT_PD_EXIT - Extended Active Power-Down Exit */ #define DDR_DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK) #define DDR_DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK (0xC000U) #define DDR_DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT (14U) /*! EXT_PRE_PD_EXIT - Extended Precharge Power-Down Exit */ #define DDR_DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK) #define DDR_DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK (0xF0000U) #define DDR_DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT (16U) /*! PRE_PD_EXIT - Precharge Power-Down Exit * 0b0000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_0_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK) #define DDR_DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK (0xF00000U) #define DDR_DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT (20U) /*! ACT_PD_EXIT - Active Powerdown Exit * 0b0000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_0_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK) #define DDR_DDRC_TIMING_CFG_0_WWT_MASK (0x3000000U) #define DDR_DDRC_TIMING_CFG_0_WWT_SHIFT (24U) /*! WWT - Write-To-Write Turnaround To Different Ranks */ #define DDR_DDRC_TIMING_CFG_0_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_WWT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_WWT_MASK) #define DDR_DDRC_TIMING_CFG_0_RRT_MASK (0xC000000U) #define DDR_DDRC_TIMING_CFG_0_RRT_SHIFT (26U) /*! RRT - Read-To-Read Turnaround To Different Ranks */ #define DDR_DDRC_TIMING_CFG_0_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_RRT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_RRT_MASK) #define DDR_DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) #define DDR_DDRC_TIMING_CFG_0_WRT_SHIFT (28U) /*! WRT - Write-To-Read Turnaround To Different Ranks */ #define DDR_DDRC_TIMING_CFG_0_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_WRT_MASK) #define DDR_DDRC_TIMING_CFG_0_RWT_MASK (0xC0000000U) #define DDR_DDRC_TIMING_CFG_0_RWT_SHIFT (30U) /*! RWT - Read-To-Write Turnaround To Different Ranks */ #define DDR_DDRC_TIMING_CFG_0_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_0_RWT_SHIFT)) & DDR_DDRC_TIMING_CFG_0_RWT_MASK) /*! @} */ /*! @name TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_1_WRTORD_MASK (0xFU) #define DDR_DDRC_TIMING_CFG_1_WRTORD_SHIFT (0U) /*! WRTORD - Write-To-Read Interval * 0b0000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_1_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_WRTORD_SHIFT)) & DDR_DDRC_TIMING_CFG_1_WRTORD_MASK) #define DDR_DDRC_TIMING_CFG_1_ACTTOACT_MASK (0xF0U) #define DDR_DDRC_TIMING_CFG_1_ACTTOACT_SHIFT (4U) /*! ACTTOACT - Activate-To-Activate Interval * 0b0000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_1_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_ACTTOACT_SHIFT)) & DDR_DDRC_TIMING_CFG_1_ACTTOACT_MASK) #define DDR_DDRC_TIMING_CFG_1_WRREC_MASK (0xF00U) #define DDR_DDRC_TIMING_CFG_1_WRREC_SHIFT (8U) /*! WRREC - Write Recovery */ #define DDR_DDRC_TIMING_CFG_1_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_WRREC_SHIFT)) & DDR_DDRC_TIMING_CFG_1_WRREC_MASK) #define DDR_DDRC_TIMING_CFG_1_REFREC_MASK (0xF000U) #define DDR_DDRC_TIMING_CFG_1_REFREC_SHIFT (12U) /*! REFREC - Refresh Recovery */ #define DDR_DDRC_TIMING_CFG_1_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_REFREC_SHIFT)) & DDR_DDRC_TIMING_CFG_1_REFREC_MASK) #define DDR_DDRC_TIMING_CFG_1_CASLAT_MASK (0xE0000U) #define DDR_DDRC_TIMING_CFG_1_CASLAT_SHIFT (17U) /*! CASLAT - CAS Latency */ #define DDR_DDRC_TIMING_CFG_1_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_CASLAT_SHIFT)) & DDR_DDRC_TIMING_CFG_1_CASLAT_MASK) #define DDR_DDRC_TIMING_CFG_1_ACTTORW_MASK (0xF00000U) #define DDR_DDRC_TIMING_CFG_1_ACTTORW_SHIFT (20U) /*! ACTTORW - Activate To Read Or Write * 0b0000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_1_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_ACTTORW_SHIFT)) & DDR_DDRC_TIMING_CFG_1_ACTTORW_MASK) #define DDR_DDRC_TIMING_CFG_1_ACTTOPRE_MASK (0xF000000U) #define DDR_DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT (24U) /*! ACTTOPRE - Activate-To-Precharge Time */ #define DDR_DDRC_TIMING_CFG_1_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT)) & DDR_DDRC_TIMING_CFG_1_ACTTOPRE_MASK) #define DDR_DDRC_TIMING_CFG_1_PRETOACT_MASK (0xF0000000U) #define DDR_DDRC_TIMING_CFG_1_PRETOACT_SHIFT (28U) /*! PRETOACT - Precharge-To-Activate Time * 0b0000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_1_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_1_PRETOACT_SHIFT)) & DDR_DDRC_TIMING_CFG_1_PRETOACT_MASK) /*! @} */ /*! @name TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_2_FOUR_ACT_MASK (0x3FU) #define DDR_DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT (0U) /*! FOUR_ACT - Four Activate */ #define DDR_DDRC_TIMING_CFG_2_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT)) & DDR_DDRC_TIMING_CFG_2_FOUR_ACT_MASK) #define DDR_DDRC_TIMING_CFG_2_CKE_PLS_MASK (0x1C0U) #define DDR_DDRC_TIMING_CFG_2_CKE_PLS_SHIFT (6U) /*! CKE_PLS - MCKE Pulse */ #define DDR_DDRC_TIMING_CFG_2_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_2_CKE_PLS_SHIFT)) & DDR_DDRC_TIMING_CFG_2_CKE_PLS_MASK) #define DDR_DDRC_TIMING_CFG_2_RD_TO_PRE_MASK (0x3E000U) #define DDR_DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT (13U) /*! RD_TO_PRE - Read-To-Precharge Time * 0b00000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_2_RD_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT)) & DDR_DDRC_TIMING_CFG_2_RD_TO_PRE_MASK) #define DDR_DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK (0x40000U) #define DDR_DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT (18U) /*! EXT_WR_LAT - Extended Write Latency */ #define DDR_DDRC_TIMING_CFG_2_EXT_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT)) & DDR_DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK) #define DDR_DDRC_TIMING_CFG_2_WR_LAT_MASK (0x780000U) #define DDR_DDRC_TIMING_CFG_2_WR_LAT_SHIFT (19U) /*! WR_LAT - Write Latency */ #define DDR_DDRC_TIMING_CFG_2_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_2_WR_LAT_SHIFT)) & DDR_DDRC_TIMING_CFG_2_WR_LAT_MASK) #define DDR_DDRC_TIMING_CFG_2_DERATE_VAL_MASK (0xF0000000U) #define DDR_DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT (28U) /*! DERATE_VAL - Derate Value */ #define DDR_DDRC_TIMING_CFG_2_DERATE_VAL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT)) & DDR_DDRC_TIMING_CFG_2_DERATE_VAL_MASK) /*! @} */ /*! @name DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_CFG_BI_MASK (0x1U) #define DDR_DDRC_DDR_SDRAM_CFG_BI_SHIFT (0U) /*! BI - Bypass Initialization * 0b0..Reserved; do not use * 0b1..Initialization routine is bypassed */ #define DDR_DDRC_DDR_SDRAM_CFG_BI(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_BI_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_BI_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK (0x2U) #define DDR_DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT (1U) /*! MEM_HALT - DDRC Halt * 0b0..Accepts new transactions * 0b1..Completes any remaining transactions and remains halted until you write 0 to this field */ #define DDR_DDRC_DDR_SDRAM_CFG_MEM_HALT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK (0x7F00U) #define DDR_DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT (8U) /*! BA_INTLV_CTL - Rank Interleaving Control * 0b0000000..No external ranks are interleaved. * 0b1000000..External ranks 0 and 1 are interleaved. * *.. */ #define DDR_DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_DC_EN_MASK (0x10000U) #define DDR_DDRC_DDR_SDRAM_CFG_DC_EN_SHIFT (16U) /*! DC_EN - Dual Channel Enable * 0b0..Dual independent 16-bit channels are not used * 0b1..Dual independent 16-bit channels are used */ #define DDR_DDRC_DDR_SDRAM_CFG_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_DC_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_DC_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_DBW_MASK (0x180000U) #define DDR_DDRC_DDR_SDRAM_CFG_DBW_SHIFT (19U) /*! DBW - DDR SDRAM Data Bus Width * 0b01..32 bits * 0b10..16 bits * *.. */ #define DDR_DDRC_DDR_SDRAM_CFG_DBW(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_DBW_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_DBW_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK (0x200000U) #define DDR_DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT (21U) /*! DYN_PWR - Dynamic Power Management * 0b0..No * 0b1..Yes */ #define DDR_DDRC_DDR_SDRAM_CFG_DYN_PWR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK (0x7000000U) #define DDR_DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT (24U) /*! SDRAM_TYPE - DDR SDRAM Type * 0b001..LPDDR5 SDRAM * 0b100..LPDDR4x SDRAM * *.. */ #define DDR_DDRC_DDR_SDRAM_CFG_SDRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_SREN_MASK (0x40000000U) #define DDR_DDRC_DDR_SDRAM_CFG_SREN_SHIFT (30U) /*! SREN - Self-Refresh Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_DDR_SDRAM_CFG_SREN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_SREN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_SREN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_MEM_EN_MASK (0x80000000U) #define DDR_DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT (31U) /*! MEM_EN - DDRC Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_DDR_SDRAM_CFG_MEM_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_MEM_EN_MASK) /*! @} */ /*! @name DDR_SDRAM_CFG_2 - DDR SDRAM Control Configuration 2 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK (0x10U) #define DDR_DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT (4U) /*! D_INIT - DDR SDRAM Data Initialization * 0b0..No data initialization in progress, and none scheduled * 0b1..DDRC to initialize the DDR SDRAM after DDRC is enabled */ #define DDR_DDRC_DDR_SDRAM_CFG_2_D_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK (0xF000U) #define DDR_DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT (12U) /*! NUM_PR - Number Of Posted Refreshes * 0b0000, 0b0001..1 * 0b0010..2 * 0b0011..3 * 0b0100..4 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * *.. */ #define DDR_DDRC_DDR_SDRAM_CFG_2_NUM_PR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK (0xF000000U) #define DDR_DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT (24U) /*! MCK_DIS - MCK Disable */ #define DDR_DDRC_DDR_SDRAM_CFG_2_MCK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK (0x80000000U) #define DDR_DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT (31U) /*! FRC_SR - Force Self-Refresh * 0b0..Normal mode * 0b1..Self-Refresh mode */ #define DDR_DDRC_DDR_SDRAM_CFG_2_FRC_SR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK) /*! @} */ /*! @name DDR_SDRAM_MD_CNTL - DDR SDRAM Mode Control */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK (0x3FFFFU) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT (0U) /*! MD_VALUE - Mode Register Value */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK (0x300000U) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT (20U) /*! CKE_CNTL - Clock Enable Control * 0b00..Not forced * 0b01..Forced to a lower value * 0b10..Forced to a higher value * 0b11..Force a powerdown exit command. You may only use this decoding when using LPDDR5 DDR SDRAM. If using * this setting before DDR_SDRAM_CFG[MEM_EN] is set, then you must first set DDR_SDRAM_CFG[BI] to allow the * powerdown exit command to be issued. */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC_MASK (0x400000U) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC_SHIFT (22U) /*! START_OSC - Start Oscillator * 0b0..No * 0b1..Yes */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC_MASK) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_MASK (0x800000U) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_SHIFT (23U) /*! START_OSC2 - Start Oscillator 2 * 0b0..No * 0b1..Yes */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC2(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL_START_OSC2_MASK) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK (0xF000000U) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT (24U) /*! MD_SEL - Mode Register Select * 0b0000..MR * 0b0001..EMR * 0b0010..EMR2 * 0b0011..EMR3 */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK (0x70000000U) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT (28U) /*! CS_SEL - Select Rank * 0b000..0 * 0b001..1 * 0b100..0 and 1 * *.. */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_CS_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK (0x80000000U) #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT (31U) /*! MD_EN - Mode Enable * 0b0..Does not need to be issued * 0b1..Valid data contained in the register ready to be issued as an MRW command */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK) /*! @} */ /*! @name DDR_SDRAM_INTERVAL - DDR SDRAM Interval Configuration */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK (0x3FFFU) #define DDR_DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT (0U) /*! BSTOPRE - Precharge Interval */ #define DDR_DDRC_DDR_SDRAM_INTERVAL_BSTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT)) & DDR_DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK) #define DDR_DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK (0xFFFF0000U) #define DDR_DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT (16U) /*! REFINT - Refresh Interval */ #define DDR_DDRC_DDR_SDRAM_INTERVAL_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT)) & DDR_DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK) /*! @} */ /*! @name DDR_DATA_INIT - DDR SDRAM Data Initialization */ /*! @{ */ #define DDR_DDRC_DDR_DATA_INIT_INIT_VALUE_MASK (0xFFFFFFFFU) #define DDR_DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT (0U) /*! INIT_VALUE - Initialization Value */ #define DDR_DDRC_DDR_DATA_INIT_INIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT)) & DDR_DDRC_DDR_DATA_INIT_INIT_VALUE_MASK) /*! @} */ /*! @name TIMING_CFG_4 - DDR SDRAM Timing Configuration 4 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_4_DLL_LOCK_MASK (0x3U) #define DDR_DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT (0U) /*! DLL_LOCK - DDR SDRAM DLL Lock Time * 0b10..1024 clocks * 0b11..2048 clocks * *.. */ #define DDR_DDRC_TIMING_CFG_4_DLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT)) & DDR_DDRC_TIMING_CFG_4_DLL_LOCK_MASK) #define DDR_DDRC_TIMING_CFG_4_EXT_REFINT_MASK (0x10U) #define DDR_DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT (4U) /*! EXT_REFINT - Extended Refresh Interval * 0b0..0 * 0b1..65,536 */ #define DDR_DDRC_TIMING_CFG_4_EXT_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_EXT_REFINT_MASK) #define DDR_DDRC_TIMING_CFG_4_EXT_WWT_MASK (0x300U) #define DDR_DDRC_TIMING_CFG_4_EXT_WWT_SHIFT (8U) /*! EXT_WWT - Extended Write-To-Write Turnaround */ #define DDR_DDRC_TIMING_CFG_4_EXT_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_EXT_WWT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_EXT_WWT_MASK) #define DDR_DDRC_TIMING_CFG_4_EXT_RRT_MASK (0xC00U) #define DDR_DDRC_TIMING_CFG_4_EXT_RRT_SHIFT (10U) /*! EXT_RRT - Extended Read-To-Read Turnaround */ #define DDR_DDRC_TIMING_CFG_4_EXT_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_EXT_RRT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_EXT_RRT_MASK) #define DDR_DDRC_TIMING_CFG_4_EXT_WRT_MASK (0x3000U) #define DDR_DDRC_TIMING_CFG_4_EXT_WRT_SHIFT (12U) /*! EXT_WRT - Extended Write-To-Read Turnaround */ #define DDR_DDRC_TIMING_CFG_4_EXT_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_EXT_WRT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_EXT_WRT_MASK) #define DDR_DDRC_TIMING_CFG_4_EXT_RWT_MASK (0xC000U) #define DDR_DDRC_TIMING_CFG_4_EXT_RWT_SHIFT (14U) /*! EXT_RWT - Extended Read-To-Write Turnaround */ #define DDR_DDRC_TIMING_CFG_4_EXT_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_EXT_RWT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_EXT_RWT_MASK) #define DDR_DDRC_TIMING_CFG_4_WWT_MASK (0xF0000U) #define DDR_DDRC_TIMING_CFG_4_WWT_SHIFT (16U) /*! WWT - Write-To-Write Turnaround For Same Rank */ #define DDR_DDRC_TIMING_CFG_4_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_WWT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_WWT_MASK) #define DDR_DDRC_TIMING_CFG_4_RRT_MASK (0xF00000U) #define DDR_DDRC_TIMING_CFG_4_RRT_SHIFT (20U) /*! RRT - Read-To-Read Turnaround For Same Rank */ #define DDR_DDRC_TIMING_CFG_4_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_RRT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_RRT_MASK) #define DDR_DDRC_TIMING_CFG_4_WRT_MASK (0xF000000U) #define DDR_DDRC_TIMING_CFG_4_WRT_SHIFT (24U) /*! WRT - Write-To-Read Turnaround For Same Rank */ #define DDR_DDRC_TIMING_CFG_4_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_WRT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_WRT_MASK) #define DDR_DDRC_TIMING_CFG_4_RWT_MASK (0xF0000000U) #define DDR_DDRC_TIMING_CFG_4_RWT_SHIFT (28U) /*! RWT - Read-To-Write Turnaround For Same Rank */ #define DDR_DDRC_TIMING_CFG_4_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_4_RWT_SHIFT)) & DDR_DDRC_TIMING_CFG_4_RWT_MASK) /*! @} */ /*! @name TIMING_CFG_7 - DDR SDRAM Timing Configuration 7 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_7_CKSRX_MASK (0xF00000U) #define DDR_DDRC_TIMING_CFG_7_CKSRX_SHIFT (20U) /*! CKSRX - Clock After Self-Refresh Exit * 0b0000, 0b1010..15 for LPDDR4x 19 for LPDDR5 * 0b0001..6 for LPDDR4x 10 for LPDDR5 * 0b0010..7 for LPDDR4x 11 for LPDDR5 * 0b0011..8 for LPDDR4x 12 for LPDDR5 * 0b0100..9 for LPDDR4x 13 for LPDDR5 * 0b0101..10 for LPDDR4x 14 for LPDDR5 * 0b0110..11 for LPDDR4x 15 for LPDDR5 * 0b0111..12 for LPDDR4x 16 for LPDDR5 * 0b1000..13 for LPDDR4x 17 for LPDDR5 * 0b1001..14 for LPDDR4x 18 for LPDDR5 * 0b1011..16 for LPDDR4x 20 for LPDDR5 * 0b1100..17 for LPDDR4x 21 for LPDDR5 * 0b1101..18 for LPDDR4x 22 for LPDDR5 * 0b1110..19 for LPDDR4x 23 for LPDDR5 * 0b1111..116 for LPDDR4x 31 for LPDDR5 */ #define DDR_DDRC_TIMING_CFG_7_CKSRX(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_7_CKSRX_SHIFT)) & DDR_DDRC_TIMING_CFG_7_CKSRX_MASK) #define DDR_DDRC_TIMING_CFG_7_CKSRE_MASK (0xF000000U) #define DDR_DDRC_TIMING_CFG_7_CKSRE_SHIFT (24U) /*! CKSRE - Clock After Self-Refresh Entry * 0b0000, 0b1010..15 for LPDDR4x 20 for LPDDR5 * 0b0001..6 for LPDDR4x 11 for LPDDR5 * 0b0010..7 for LPDDR4x 12 for LPDDR5 * 0b0011..8 for LPDDR4x 13 for LPDDR5 * 0b0100..9 for LPDDR4x 14 for LPDDR5 * 0b0101..10 for LPDDR4x 15 for LPDDR5 * 0b0110..11 for LPDDR4x 16 for LPDDR5 * 0b0111..12 for LPDDR4x 17 for LPDDR5 * 0b1000..13 for LPDDR4x 18 for LPDDR5 * 0b1001..14 for LPDDR4x 19 for LPDDR5 * 0b1011..16 for LPDDR4x 21 for LPDDR5 * 0b1100..17 for LPDDR4x 22 for LPDDR5 * 0b1101..18 for LPDDR4x 23 for LPDDR5 * 0b1110..19 for LPDDR4x 24 for LPDDR5 * 0b1111..32 for LPDDR4x 31 for LPDDR5 */ #define DDR_DDRC_TIMING_CFG_7_CKSRE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_7_CKSRE_SHIFT)) & DDR_DDRC_TIMING_CFG_7_CKSRE_MASK) #define DDR_DDRC_TIMING_CFG_7_CKE_RST_MASK (0x30000000U) #define DDR_DDRC_TIMING_CFG_7_CKE_RST_SHIFT (28U) /*! CKE_RST - MCKE Reset Time * 0b00..200 * 0b01..256 * 0b10..512 * 0b11..4096 */ #define DDR_DDRC_TIMING_CFG_7_CKE_RST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_7_CKE_RST_SHIFT)) & DDR_DDRC_TIMING_CFG_7_CKE_RST_MASK) /*! @} */ /*! @name DDR_ZQ_CNTL - DDR SDRAM ZQ Calibration Control */ /*! @{ */ #define DDR_DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK (0xFU) #define DDR_DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT (0U) /*! ZQCS_INT - ZQCS Interval * 0b0000..32 * 0b0001..64 * 0b0010..128 * 0b0011..256 * 0b0100..512 * 0b0101..1024 * 0b0110..2048 * 0b0111..4096 * 0b1000..8192 * 0b1001..16384 * 0b1010..32768 * 0b1111..ZQCS calibration disabled * *.. */ #define DDR_DDRC_DDR_ZQ_CNTL_ZQCS_INT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT)) & DDR_DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK) #define DDR_DDRC_DDR_ZQ_CNTL_ZQCS_MASK (0xF00U) #define DDR_DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT (8U) /*! ZQCS - ZQ Calibration Short Time * 0b0000..1 * 0b0001..2 * 0b0010..4 * 0b0011..8 * 0b0100..16 * 0b0101..32 * 0b0110..64 * 0b0111..128 * 0b1000..256 * 0b1001..512 */ #define DDR_DDRC_DDR_ZQ_CNTL_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT)) & DDR_DDRC_DDR_ZQ_CNTL_ZQCS_MASK) #define DDR_DDRC_DDR_ZQ_CNTL_ZQOPER_MASK (0xF0000U) #define DDR_DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT (16U) /*! ZQOPER - ZQ Calibration Operation Time * 0b0111..128 * 0b1000..256 * 0b1001..512 * 0b1010..1024 * 0b1011..2048 * 0b1110..2200 cycles when using LPDDR4x DDR_SDRAM; Reserved for LPDDR5 DDR_SDRAM * 0b1100..4096 * 0b1101..8192 */ #define DDR_DDRC_DDR_ZQ_CNTL_ZQOPER(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT)) & DDR_DDRC_DDR_ZQ_CNTL_ZQOPER_MASK) #define DDR_DDRC_DDR_ZQ_CNTL_ZQINIT_MASK (0xF000000U) #define DDR_DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT (24U) /*! ZQINIT - ZQ Calibration Initialization Time * 0b0111..128 * 0b1000..256 * 0b1001..512 * 0b1010..1024 * 0b1011..2048 * 0b1110..2200 cycles when using LPDDR4x DDR_SDRAM; Reserved for LPDDR5 DDR_SDRAM * 0b1100..4096 * 0b1101..8192 */ #define DDR_DDRC_DDR_ZQ_CNTL_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT)) & DDR_DDRC_DDR_ZQ_CNTL_ZQINIT_MASK) #define DDR_DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK (0x80000000U) #define DDR_DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT (31U) /*! ZQ_EN - ZQ Calibration Enable * 0b0..Used * 0b1..Not used */ #define DDR_DDRC_DDR_ZQ_CNTL_ZQ_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT)) & DDR_DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK) /*! @} */ /*! @name DDR_SR_CNTR - DDR SDRAM Self-Refresh Counter */ /*! @{ */ #define DDR_DDRC_DDR_SR_CNTR_SR_IT_MASK (0xF0000U) #define DDR_DDRC_DDR_SR_CNTR_SR_IT_SHIFT (16U) /*! SR_IT - Self-Refresh Idle Threshold */ #define DDR_DDRC_DDR_SR_CNTR_SR_IT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SR_CNTR_SR_IT_SHIFT)) & DDR_DDRC_DDR_SR_CNTR_SR_IT_MASK) /*! @} */ /*! @name TIMING_CFG_8 - DDR SDRAM Timing Configuration 8 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK (0x3FU) #define DDR_DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT (0U) /*! PRE_ALL_REC - Precharge All-To-Activate Interval */ #define DDR_DDRC_TIMING_CFG_8_PRE_ALL_REC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT)) & DDR_DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK) #define DDR_DDRC_TIMING_CFG_8_EXT_WRTORD_BG_MASK (0x80U) #define DDR_DDRC_TIMING_CFG_8_EXT_WRTORD_BG_SHIFT (7U) /*! EXT_WRTORD_BG - Extended Write-To-Read Same Bank Group * 0b0..0 * 0b1..16 */ #define DDR_DDRC_TIMING_CFG_8_EXT_WRTORD_BG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_EXT_WRTORD_BG_SHIFT)) & DDR_DDRC_TIMING_CFG_8_EXT_WRTORD_BG_MASK) #define DDR_DDRC_TIMING_CFG_8_WRTORD_BG_MASK (0xF00U) #define DDR_DDRC_TIMING_CFG_8_WRTORD_BG_SHIFT (8U) /*! WRTORD_BG - Write-To-Read Same Bank Group */ #define DDR_DDRC_TIMING_CFG_8_WRTORD_BG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_WRTORD_BG_SHIFT)) & DDR_DDRC_TIMING_CFG_8_WRTORD_BG_MASK) #define DDR_DDRC_TIMING_CFG_8_ACTTOACT_BG_MASK (0xF000U) #define DDR_DDRC_TIMING_CFG_8_ACTTOACT_BG_SHIFT (12U) /*! ACTTOACT_BG - Activate-To-Activate Same Bank Group */ #define DDR_DDRC_TIMING_CFG_8_ACTTOACT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_ACTTOACT_BG_SHIFT)) & DDR_DDRC_TIMING_CFG_8_ACTTOACT_BG_MASK) #define DDR_DDRC_TIMING_CFG_8_WWT_BG_MASK (0xF0000U) #define DDR_DDRC_TIMING_CFG_8_WWT_BG_SHIFT (16U) /*! WWT_BG - Write-To-Write Turnaround For Same CS And Bank Group */ #define DDR_DDRC_TIMING_CFG_8_WWT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_WWT_BG_SHIFT)) & DDR_DDRC_TIMING_CFG_8_WWT_BG_MASK) #define DDR_DDRC_TIMING_CFG_8_RRT_BG_MASK (0xF00000U) #define DDR_DDRC_TIMING_CFG_8_RRT_BG_SHIFT (20U) /*! RRT_BG - Read-To-Read Turnaround For Same Rank And Bank Group */ #define DDR_DDRC_TIMING_CFG_8_RRT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_RRT_BG_SHIFT)) & DDR_DDRC_TIMING_CFG_8_RRT_BG_MASK) #define DDR_DDRC_TIMING_CFG_8_WRT_BG_MASK (0xF000000U) #define DDR_DDRC_TIMING_CFG_8_WRT_BG_SHIFT (24U) /*! WRT_BG - Write-To-Read Turnaround For Same Rank And Bank Group */ #define DDR_DDRC_TIMING_CFG_8_WRT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_WRT_BG_SHIFT)) & DDR_DDRC_TIMING_CFG_8_WRT_BG_MASK) #define DDR_DDRC_TIMING_CFG_8_RWT_BG_MASK (0xF0000000U) #define DDR_DDRC_TIMING_CFG_8_RWT_BG_SHIFT (28U) /*! RWT_BG - Read-To-Write Turnaround For Same Rank And Bank Group */ #define DDR_DDRC_TIMING_CFG_8_RWT_BG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_8_RWT_BG_SHIFT)) & DDR_DDRC_TIMING_CFG_8_RWT_BG_MASK) /*! @} */ /*! @name TIMING_CFG_9 - DDR SDRAM timing configuration 9 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_9_REFTOREF_PB_MASK (0x3FFU) #define DDR_DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT (0U) /*! REFTOREF_PB - Refresh-to-refresh interval for per-bank refresh. * 0b0000000000..disable PB refresh * 0b0000000001..9 clocks * 0b0000000010..10 clocks * 0b1011111110..774 clocks * 0b1011111111..775 clocks */ #define DDR_DDRC_TIMING_CFG_9_REFTOREF_PB(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT)) & DDR_DDRC_TIMING_CFG_9_REFTOREF_PB_MASK) #define DDR_DDRC_TIMING_CFG_9_REFREC_PB_MASK (0x3FF0000U) #define DDR_DDRC_TIMING_CFG_9_REFREC_PB_SHIFT (16U) /*! REFREC_PB - Refresh Recovery Per-Bank Refresh * 0b0000000000..8 clocks * 0b0000000001..9 clocks * 0b0000000010..10 clocks * 0b1011111110..774 clocks * 0b1011111111..775 clocks */ #define DDR_DDRC_TIMING_CFG_9_REFREC_PB(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_9_REFREC_PB_SHIFT)) & DDR_DDRC_TIMING_CFG_9_REFREC_PB_MASK) /*! @} */ /*! @name TIMING_CFG_10 - DDR SDRAM Timing Configuration 10 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_10_T_STAB_MASK (0x7FFFU) #define DDR_DDRC_TIMING_CFG_10_T_STAB_SHIFT (0U) /*! T_STAB - Stabilization Wait Time */ #define DDR_DDRC_TIMING_CFG_10_T_STAB(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_10_T_STAB_SHIFT)) & DDR_DDRC_TIMING_CFG_10_T_STAB_MASK) #define DDR_DDRC_TIMING_CFG_10_PBRTOACT_MASK (0xF800000U) #define DDR_DDRC_TIMING_CFG_10_PBRTOACT_SHIFT (23U) /*! PBRTOACT - Per-Bank Refresh to Activate */ #define DDR_DDRC_TIMING_CFG_10_PBRTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_10_PBRTOACT_SHIFT)) & DDR_DDRC_TIMING_CFG_10_PBRTOACT_MASK) /*! @} */ /*! @name TIMING_CFG_11 - DDR SDRAM Timing Configuration 11 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_11_MWWT_MASK (0xFU) #define DDR_DDRC_TIMING_CFG_11_MWWT_SHIFT (0U) /*! MWWT - Masked Write-To-Write Turnaround (tCCDMW) */ #define DDR_DDRC_TIMING_CFG_11_MWWT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_11_MWWT_SHIFT)) & DDR_DDRC_TIMING_CFG_11_MWWT_MASK) #define DDR_DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK (0xF00U) #define DDR_DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT (8U) /*! PRE_TO_PRE - Precharge-To-Precharge Time * 0b0000, 0b0100..4 * 0b0001..1 * 0b0010..2 * 0b0011..3 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * 0b1001..9 * 0b1010..10 * 0b1011..11 * 0b1100..12 * 0b1101..13 * 0b1110..14 * 0b1111..15 */ #define DDR_DDRC_TIMING_CFG_11_PRE_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT)) & DDR_DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK) #define DDR_DDRC_TIMING_CFG_11_WCKEN_FS_MASK (0xF0000U) #define DDR_DDRC_TIMING_CFG_11_WCKEN_FS_SHIFT (16U) /*! WCKEN_FS - WCKEN FS Time * 0b0000, 0b0010..2 * 0b0001..1 * 0b0011..3 * 0b0100..4 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * 0b1001..9 * 0b1010..10 * 0b1011..11 * 0b1100..12 * 0b1101..13 * 0b1110..14 * 0b1111..15 */ #define DDR_DDRC_TIMING_CFG_11_WCKEN_FS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_11_WCKEN_FS_SHIFT)) & DDR_DDRC_TIMING_CFG_11_WCKEN_FS_MASK) #define DDR_DDRC_TIMING_CFG_11_WCK_STOP_MASK (0xF00000U) #define DDR_DDRC_TIMING_CFG_11_WCK_STOP_SHIFT (20U) /*! WCK_STOP - WCK Stop Time * 0b0000, 0b0111..7 * 0b0001..1 * 0b0010..2 * 0b0011..3 * 0b0100..4 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * 0b1001..9 * 0b1010..10 * *.. */ #define DDR_DDRC_TIMING_CFG_11_WCK_STOP(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_11_WCK_STOP_SHIFT)) & DDR_DDRC_TIMING_CFG_11_WCK_STOP_MASK) #define DDR_DDRC_TIMING_CFG_11_WS_OFF_MASK (0x7000000U) #define DDR_DDRC_TIMING_CFG_11_WS_OFF_SHIFT (24U) /*! WS_OFF - WS_OFF Wait Time * 0b000..0 extra cycles added * 0b001..1 * 0b010..2 * 0b011..3 * 0b100..4 * *.. */ #define DDR_DDRC_TIMING_CFG_11_WS_OFF(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_11_WS_OFF_SHIFT)) & DDR_DDRC_TIMING_CFG_11_WS_OFF_MASK) #define DDR_DDRC_TIMING_CFG_11_WCKPRE_STATIC_MASK (0xF0000000U) #define DDR_DDRC_TIMING_CFG_11_WCKPRE_STATIC_SHIFT (28U) /*! WCKPRE_STATIC - WCKPRE Static Time * 0b0000, 0b0100..4 * 0b0001..1 * 0b0010..2 * 0b0011..3 * 0b0101..5 * 0b0110..6 * 0b0111..7 * 0b1000..8 * 0b1001..9 * 0b1010..10 * 0b1011..11 * 0b1100..12 * 0b1101..13 * 0b1110..14 * 0b1111..15 */ #define DDR_DDRC_TIMING_CFG_11_WCKPRE_STATIC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_11_WCKPRE_STATIC_SHIFT)) & DDR_DDRC_TIMING_CFG_11_WCKPRE_STATIC_MASK) /*! @} */ /*! @name DDR_SDRAM_CFG_3 - DDR SDRAM Control Configuration 3 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK (0x2U) #define DDR_DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT (1U) /*! SR_FAST_WK_EN - Self Refresh Fast Wakeup Enable * 0b0..Slow * 0b1..Fast */ #define DDR_DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK (0x80U) #define DDR_DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT (7U) /*! DYN_REF_RATE_EN - Dynamic Refresh Rate Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK (0x800U) #define DDR_DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT (11U) /*! DRAIN_FOR_SR - Drain Queues For Self-Refresh * 0b0..Do not drain * 0b1..Drain */ #define DDR_DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK (0x7000U) #define DDR_DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT (12U) /*! DM_CFG - Data Mask Configuration * 0b000..Normal data masks based on the settings defined in DDR_SDRAM_CFG[SDRAM_TYPE] * 0b010..DBI * 0b011..Neither data masks nor DBI * 0b100..DBI with data masks * *.. */ #define DDR_DDRC_DDR_SDRAM_CFG_3_DM_CFG(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_MASK (0x10000U) #define DDR_DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_SHIFT (16U) /*! CHB_SWP_EN - Channel B Swap Enable * 0b0..Channel B is not byte swapped * 0b1..Channel B is byte swapped */ #define DDR_DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_CHB_SWP_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_MASK (0x20000U) #define DDR_DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_SHIFT (17U) /*! CHA_SWP_EN - Channel A Swap Enable * 0b0..Channel A is not byte swapped * 0b1..Channel A is byte swapped */ #define DDR_DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_CHA_SWP_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_HP_EN_MASK (0x80000U) #define DDR_DDRC_DDR_SDRAM_CFG_3_HP_EN_SHIFT (19U) /*! HP_EN - High Performance Enable * 0b0..Row hammering avoidance not enabled * 0b1..Row hammering avoidance enabled */ #define DDR_DDRC_DDR_SDRAM_CFG_3_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_HP_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_HP_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_MASK (0xF000000U) #define DDR_DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_SHIFT (24U) /*! ECC_SCRUB_INT - ECC Scrubbing Interval */ #define DDR_DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_ECC_SCRUB_INT_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_MASK (0x40000000U) #define DDR_DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_SHIFT (30U) /*! ECC_FIX_EN - ECC Fixing Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_ECC_FIX_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK (0x80000000U) #define DDR_DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT (31U) /*! DDRC_RST - DDRC Reset * 0b0..Operating normally * 0b1..Undergoing reset */ #define DDR_DDRC_DDR_SDRAM_CFG_3_DDRC_RST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK) /*! @} */ /*! @name DDR_SDRAM_CFG_4 - DDR SDRAM Control Configuration 4 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_MASK (0x1F000U) #define DDR_DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_SHIFT (12U) /*! FRQCH_RET - Frequency Change and Retention Setup */ #define DDR_DDRC_DDR_SDRAM_CFG_4_FRQCH_RET(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_4_FRQCH_RET_MASK) /*! @} */ /*! @name DDR_SDRAM_CFG_5 - DDR SDRAM Control Configuration 5 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_MASK (0x1U) #define DDR_DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_SHIFT (0U) /*! LNK_ECC_EN - Link ECC enable. * 0b0..Link ECC is disabled. * 0b1..Link ECC is enabled. */ #define DDR_DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_5_LNK_ECC_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_5_DSLP_EN_MASK (0x2U) #define DDR_DDRC_DDR_SDRAM_CFG_5_DSLP_EN_SHIFT (1U) /*! DSLP_EN - Deep sleep enable. * 0b0..Self-refresh requests do not cause the controller to enter Deep Sleep mode. * 0b1..Self-refresh requests cause the controller to enter Deep Sleep mode. */ #define DDR_DDRC_DDR_SDRAM_CFG_5_DSLP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_5_DSLP_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_5_DSLP_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_5_MED_PRIO_MASK (0xF000000U) #define DDR_DDRC_DDR_SDRAM_CFG_5_MED_PRIO_SHIFT (24U) /*! MED_PRIO - Medium Priority Level. */ #define DDR_DDRC_DDR_SDRAM_CFG_5_MED_PRIO(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_5_MED_PRIO_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_5_MED_PRIO_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_MASK (0xF0000000U) #define DDR_DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_SHIFT (28U) /*! HIGH_PRIO - High Priority Level. */ #define DDR_DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_5_HIGH_PRIO_MASK) /*! @} */ /*! @name DDR_SDRAM_CFG_6 - DDR SDRAM Control Configuration 6 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_CFG_6_MR28_VAL_MASK (0x3FU) #define DDR_DDRC_DDR_SDRAM_CFG_6_MR28_VAL_SHIFT (0U) /*! MR28_VAL - MR28 Value. */ #define DDR_DDRC_DDR_SDRAM_CFG_6_MR28_VAL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_6_MR28_VAL_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_6_MR28_VAL_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_6_RRO_MASK (0x40U) #define DDR_DDRC_DDR_SDRAM_CFG_6_RRO_SHIFT (6U) /*! RRO - Refresh rate option. */ #define DDR_DDRC_DDR_SDRAM_CFG_6_RRO(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_6_RRO_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_6_RRO_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_MASK (0x1000U) #define DDR_DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_SHIFT (12U) /*! ADDR_SZL_EN - Address swizzle enable. * 0b0..Do not enable address swizzling. * 0b1..Will move bit 6 of the incoming address of the DDRC to the bit dedicated to BG1 (assuming 10-bit column * address). Then, all bits from BG1 to bit 7 will be shifted right 1 bit. This will force 64-byte sequential * transactions to use different bank groups. Note that when this bit is set, any addresses captured in the * error capture registers will represent the address after this swizzle occurs. */ #define DDR_DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_6_ADDR_SZL_EN_MASK) #define DDR_DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_MASK (0x2000U) #define DDR_DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_SHIFT (13U) /*! RD_SPLT_EN - Read split enable. * 0b0..Read split feature is disabled. * 0b1..64-byte reads (or reads that cross a 32-byte boundary) will be split into 2 transactions within the scheduling. */ #define DDR_DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_SHIFT)) & DDR_DDRC_DDR_SDRAM_CFG_6_RD_SPLT_EN_MASK) /*! @} */ /*! @name DDR_SDRAM_MD_CNTL2 - DDR SDRAM mode control 2 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL2_MPRR_MASK (0x80000000U) #define DDR_DDRC_DDR_SDRAM_MD_CNTL2_MPRR_SHIFT (31U) /*! MPRR - Multi-purpose register read. * 0b0..A multi-purpose register read will not be issued. * 0b1..A multi-purpose register read will be issued after DDR_SDRAM_MD_CNTL[MD_EN] is set. */ #define DDR_DDRC_DDR_SDRAM_MD_CNTL2_MPRR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MD_CNTL2_MPRR_SHIFT)) & DDR_DDRC_DDR_SDRAM_MD_CNTL2_MPRR_MASK) /*! @} */ /*! @name DDR_SDRAM_MPR4 - DDR SDRAM multi-purpose register 4 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_MPR4_MPR_READ_MASK (0xFFFFFFFFU) #define DDR_DDRC_DDR_SDRAM_MPR4_MPR_READ_SHIFT (0U) /*! MPR_READ - MPR Read Value. */ #define DDR_DDRC_DDR_SDRAM_MPR4_MPR_READ(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MPR4_MPR_READ_SHIFT)) & DDR_DDRC_DDR_SDRAM_MPR4_MPR_READ_MASK) /*! @} */ /*! @name DDR_SDRAM_MPR5 - DDR SDRAM multi-purpose register 5 */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_MPR5_MPR_VLD_MASK (0x1U) #define DDR_DDRC_DDR_SDRAM_MPR5_MPR_VLD_SHIFT (0U) /*! MPR_VLD - MPR Valid. * 0b0..The multi-purpose register read data registers are not valid. * 0b1..The multi-purpose register read data registers are valid. */ #define DDR_DDRC_DDR_SDRAM_MPR5_MPR_VLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_MPR5_MPR_VLD_SHIFT)) & DDR_DDRC_DDR_SDRAM_MPR5_MPR_VLD_MASK) /*! @} */ /*! @name DDR_SDRAM_REF_RATE - DDR Refresh Rate */ /*! @{ */ #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK (0xFFU) #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT (0U) /*! REF_RATE_CS1 - Refresh Rate Rank 1 */ #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT)) & DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK) #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK (0xFF00U) #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT (8U) /*! REF_RATE_CS0 - Refresh Rate Rank 0 */ #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT)) & DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK) #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_MASK (0xFF0000U) #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_SHIFT (16U) /*! REF_RATE_CS1_CHB - Refresh Rate Rank 1 */ #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_SHIFT)) & DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_CHB_MASK) #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_MASK (0xFF000000U) #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_SHIFT (24U) /*! REF_RATE_CS0_CHB - Refresh Rate Rank 0 */ #define DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_SHIFT)) & DDR_DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_CHB_MASK) /*! @} */ /*! @name TIMING_CFG_12 - DDR SDRAM Timing Configuration 12 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_12_CASLAT_HS_MASK (0x3FU) #define DDR_DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT (0U) /*! CASLAT_HS - CAS Latency For Half Speed */ #define DDR_DDRC_TIMING_CFG_12_CASLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_12_CASLAT_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_12_CASLAT_HS_MASK) #define DDR_DDRC_TIMING_CFG_12_ACTTORW_HS_MASK (0x3F00U) #define DDR_DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT (8U) /*! ACTTORW_HS - Activate To Read Or Write For Half Speed * 0b000000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_12_ACTTORW_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_12_ACTTORW_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_12_ACTTORW_HS_MASK) #define DDR_DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK (0x7F0000U) #define DDR_DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT (16U) /*! ACTTOPRE_HS - Activate-To-Precharge Time For Half Speed */ #define DDR_DDRC_TIMING_CFG_12_ACTTOPRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_12_ACTTOPRE_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_12_ACTTOPRE_HS_MASK) #define DDR_DDRC_TIMING_CFG_12_PRETOACT_HS_MASK (0x3F000000U) #define DDR_DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT (24U) /*! PRETOACT_HS - Precharge-To-Activate Time For Half Speed * 0b000000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_12_PRETOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_12_PRETOACT_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_12_PRETOACT_HS_MASK) /*! @} */ /*! @name TIMING_CFG_13 - DDR SDRAM Timing Configuration 13 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK (0x1FU) #define DDR_DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT (0U) /*! ACTTOACT_HS - Activate-To-Activate Interval For Half Speed * 0b00000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_13_ACTTOACT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_13_ACTTOACT_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_13_ACTTOACT_HS_MASK) #define DDR_DDRC_TIMING_CFG_13_WRREC_HS_MASK (0x3F00U) #define DDR_DDRC_TIMING_CFG_13_WRREC_HS_SHIFT (8U) /*! WRREC_HS - Write Recovery For Half Speed * 0b000000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_13_WRREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_13_WRREC_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_13_WRREC_HS_MASK) #define DDR_DDRC_TIMING_CFG_13_REFREC_HS_MASK (0x3FF0000U) #define DDR_DDRC_TIMING_CFG_13_REFREC_HS_SHIFT (16U) /*! REFREC_HS - Refresh Recovery For Half Speed */ #define DDR_DDRC_TIMING_CFG_13_REFREC_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_13_REFREC_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_13_REFREC_HS_MASK) /*! @} */ /*! @name TIMING_CFG_14 - DDR SDRAM Timing Configuration 14 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_14_REFINT_HS_MASK (0x1FFFFU) #define DDR_DDRC_TIMING_CFG_14_REFINT_HS_SHIFT (0U) /*! REFINT_HS - Refresh Interval For Half Speed */ #define DDR_DDRC_TIMING_CFG_14_REFINT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_14_REFINT_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_14_REFINT_HS_MASK) #define DDR_DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK (0x7C0000U) #define DDR_DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT (18U) /*! RD_TO_PRE_HS - Read-To-Precharge Time For Half Speed * 0b00000.. * *..Clock cycles as defined in the description */ #define DDR_DDRC_TIMING_CFG_14_RD_TO_PRE_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_14_RD_TO_PRE_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_14_RD_TO_PRE_HS_MASK) #define DDR_DDRC_TIMING_CFG_14_WRLAT_HS_MASK (0x3F000000U) #define DDR_DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT (24U) /*! WRLAT_HS - Write Latency For Half Speed */ #define DDR_DDRC_TIMING_CFG_14_WRLAT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_14_WRLAT_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_14_WRLAT_HS_MASK) /*! @} */ /*! @name TIMING_CFG_15 - DDR SDRAM Timing Configuration 15 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_15_REFTOREF_PB_HS_MASK (0x3FFU) #define DDR_DDRC_TIMING_CFG_15_REFTOREF_PB_HS_SHIFT (0U) /*! REFTOREF_PB_HS - Refresh-to-refresh interval for per-bank refresh. * 0b0000000000..8 clocks * 0b0000000001..9 clocks * 0b0000000010..10 clocks * 0b1011111110..774 clocks * 0b1011111111..775 clocks */ #define DDR_DDRC_TIMING_CFG_15_REFTOREF_PB_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_15_REFTOREF_PB_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_15_REFTOREF_PB_HS_MASK) #define DDR_DDRC_TIMING_CFG_15_REFREC_PB_HS_MASK (0x3FF0000U) #define DDR_DDRC_TIMING_CFG_15_REFREC_PB_HS_SHIFT (16U) /*! REFREC_PB_HS - Refresh Recovery During Per-Bank Refresh. * 0b0000000000..8 clocks * 0b0000000001..9 clocks * 0b0000000010..10 clocks * 0b1011111110..774 clocks * 0b1011111111..775 clocks */ #define DDR_DDRC_TIMING_CFG_15_REFREC_PB_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_15_REFREC_PB_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_15_REFREC_PB_HS_MASK) /*! @} */ /*! @name TIMING_CFG_16 - DDR SDRAM Timing Configuration 16 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_16_T_STAB_HS_MASK (0x7FFFU) #define DDR_DDRC_TIMING_CFG_16_T_STAB_HS_SHIFT (0U) /*! T_STAB_HS - Stabilization Wait Time at Half Speed */ #define DDR_DDRC_TIMING_CFG_16_T_STAB_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_16_T_STAB_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_16_T_STAB_HS_MASK) #define DDR_DDRC_TIMING_CFG_16_WCK_CNFGS_HS_MASK (0xFFFF0000U) #define DDR_DDRC_TIMING_CFG_16_WCK_CNFGS_HS_SHIFT (16U) /*! WCK_CNFGS_HS - WCK Configuration Settings at Half Speed */ #define DDR_DDRC_TIMING_CFG_16_WCK_CNFGS_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_16_WCK_CNFGS_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_16_WCK_CNFGS_HS_MASK) /*! @} */ /*! @name TIMING_CFG_17 - DDR SDRAM Timing Configuration 17 */ /*! @{ */ #define DDR_DDRC_TIMING_CFG_17_ZQCS_INT_HS_MASK (0xFU) #define DDR_DDRC_TIMING_CFG_17_ZQCS_INT_HS_SHIFT (0U) /*! ZQCS_INT_HS - ZQCS Interval * 0b0000..32 * 0b0001..64 * 0b0010..128 * 0b0011..256 * 0b0100..512 * 0b0101..1024 * 0b0110..2048 * 0b0111..4096 * 0b1000..8192 * 0b1001..16384 * 0b1010..32768 * 0b1111..ZQCS calibration disabled * *.. */ #define DDR_DDRC_TIMING_CFG_17_ZQCS_INT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_17_ZQCS_INT_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_17_ZQCS_INT_HS_MASK) #define DDR_DDRC_TIMING_CFG_17_ZQCS_HS_MASK (0xF00U) #define DDR_DDRC_TIMING_CFG_17_ZQCS_HS_SHIFT (8U) /*! ZQCS_HS - ZQ Calibration Short Time * 0b0000..1 * 0b0001..2 * 0b0010..4 * 0b0011..8 * 0b0100..16 * 0b0101..32 * 0b0110..64 * 0b0111..128 * 0b1000..256 * 0b1001..512 */ #define DDR_DDRC_TIMING_CFG_17_ZQCS_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_17_ZQCS_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_17_ZQCS_HS_MASK) #define DDR_DDRC_TIMING_CFG_17_ZQOPER_HS_MASK (0xF0000U) #define DDR_DDRC_TIMING_CFG_17_ZQOPER_HS_SHIFT (16U) /*! ZQOPER_HS - ZQ Calibration Operation Time * 0b0111..128 * 0b1000..256 * 0b1001..512 * 0b1010..1024 * 0b1011..2048 */ #define DDR_DDRC_TIMING_CFG_17_ZQOPER_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_17_ZQOPER_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_17_ZQOPER_HS_MASK) #define DDR_DDRC_TIMING_CFG_17_ZQINIT_HS_MASK (0xF000000U) #define DDR_DDRC_TIMING_CFG_17_ZQINIT_HS_SHIFT (24U) /*! ZQINIT_HS - ZQ Calibration Initialization Time * 0b0111..128 * 0b1000..256 * 0b1001..512 * 0b1010..1024 * 0b1011..2048 */ #define DDR_DDRC_TIMING_CFG_17_ZQINIT_HS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TIMING_CFG_17_ZQINIT_HS_SHIFT)) & DDR_DDRC_TIMING_CFG_17_ZQINIT_HS_MASK) /*! @} */ /*! @name TX_CFG_1 - Transaction Configuration Register 1 */ /*! @{ */ #define DDR_DDRC_TX_CFG_1_WWATER_MASK (0xFU) #define DDR_DDRC_TX_CFG_1_WWATER_SHIFT (0U) /*! WWATER - Write Watermark. */ #define DDR_DDRC_TX_CFG_1_WWATER(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_1_WWATER_SHIFT)) & DDR_DDRC_TX_CFG_1_WWATER_MASK) #define DDR_DDRC_TX_CFG_1_TS_DEPTH_MASK (0xF80U) #define DDR_DDRC_TX_CFG_1_TS_DEPTH_SHIFT (7U) /*! TS_DEPTH - Transaction Scheduler Depth */ #define DDR_DDRC_TX_CFG_1_TS_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_1_TS_DEPTH_SHIFT)) & DDR_DDRC_TX_CFG_1_TS_DEPTH_MASK) #define DDR_DDRC_TX_CFG_1_HPR_MASK (0x200000U) #define DDR_DDRC_TX_CFG_1_HPR_SHIFT (21U) /*! HPR - High Priority Read. * 0b0..New high priority read does not truncate a write run. * 0b1..New high priority read can truncate a write run. */ #define DDR_DDRC_TX_CFG_1_HPR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_1_HPR_SHIFT)) & DDR_DDRC_TX_CFG_1_HPR_MASK) /*! @} */ /*! @name TX_CFG_2 - Transaction Configuration Register 2 */ /*! @{ */ #define DDR_DDRC_TX_CFG_2_WR_BONUS_MASK (0x1FU) #define DDR_DDRC_TX_CFG_2_WR_BONUS_SHIFT (0U) /*! WR_BONUS - Write Bandwidth Bonus Count. */ #define DDR_DDRC_TX_CFG_2_WR_BONUS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_2_WR_BONUS_SHIFT)) & DDR_DDRC_TX_CFG_2_WR_BONUS_MASK) #define DDR_DDRC_TX_CFG_2_WR_CNT_MASK (0x1F00U) #define DDR_DDRC_TX_CFG_2_WR_CNT_SHIFT (8U) /*! WR_CNT - Write Bandwidth Count. */ #define DDR_DDRC_TX_CFG_2_WR_CNT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_2_WR_CNT_SHIFT)) & DDR_DDRC_TX_CFG_2_WR_CNT_MASK) #define DDR_DDRC_TX_CFG_2_RD_BONUS_MASK (0x1F0000U) #define DDR_DDRC_TX_CFG_2_RD_BONUS_SHIFT (16U) /*! RD_BONUS - Read Bandwidth Bonus Count. */ #define DDR_DDRC_TX_CFG_2_RD_BONUS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_2_RD_BONUS_SHIFT)) & DDR_DDRC_TX_CFG_2_RD_BONUS_MASK) #define DDR_DDRC_TX_CFG_2_RD_CNT_MASK (0x1F000000U) #define DDR_DDRC_TX_CFG_2_RD_CNT_SHIFT (24U) /*! RD_CNT - Read Bandwidth Count. */ #define DDR_DDRC_TX_CFG_2_RD_CNT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_2_RD_CNT_SHIFT)) & DDR_DDRC_TX_CFG_2_RD_CNT_MASK) #define DDR_DDRC_TX_CFG_2_RD_EPA_DIS_MASK (0x40000000U) #define DDR_DDRC_TX_CFG_2_RD_EPA_DIS_SHIFT (30U) /*! RD_EPA_DIS - Read Precharge to Activate Disable. */ #define DDR_DDRC_TX_CFG_2_RD_EPA_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_2_RD_EPA_DIS_SHIFT)) & DDR_DDRC_TX_CFG_2_RD_EPA_DIS_MASK) #define DDR_DDRC_TX_CFG_2_WR_EPA_DIS_MASK (0x80000000U) #define DDR_DDRC_TX_CFG_2_WR_EPA_DIS_SHIFT (31U) /*! WR_EPA_DIS - Write Precharge to Activate Disable. */ #define DDR_DDRC_TX_CFG_2_WR_EPA_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_TX_CFG_2_WR_EPA_DIS_SHIFT)) & DDR_DDRC_TX_CFG_2_WR_EPA_DIS_MASK) /*! @} */ /*! @name DDRDSR_2 - DDR SDRAM Debug Status 2 */ /*! @{ */ #define DDR_DDRC_DDRDSR_2_RPD_END_MASK (0x1U) #define DDR_DDRC_DDRDSR_2_RPD_END_SHIFT (0U) /*! RPD_END - Rapid Clear Of Memory End * 0b0..Not complete * 0b1..Complete */ #define DDR_DDRC_DDRDSR_2_RPD_END(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDRDSR_2_RPD_END_SHIFT)) & DDR_DDRC_DDRDSR_2_RPD_END_MASK) #define DDR_DDRC_DDRDSR_2_RPD_ST_MASK (0x2U) #define DDR_DDRC_DDRDSR_2_RPD_ST_SHIFT (1U) /*! RPD_ST - Rapid Clear Of Memory Start * 0b0..Not started * 0b1..Started */ #define DDR_DDRC_DDRDSR_2_RPD_ST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDRDSR_2_RPD_ST_SHIFT)) & DDR_DDRC_DDRDSR_2_RPD_ST_MASK) #define DDR_DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK (0x4U) #define DDR_DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT (2U) /*! PHY_INIT_CMPLT - DDR PHY Initialization Complete * 0b0..Not complete * 0b1..Complete */ #define DDR_DDRC_DDRDSR_2_PHY_INIT_CMPLT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT)) & DDR_DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK) #define DDR_DDRC_DDRDSR_2_NML_MASK (0x40000000U) #define DDR_DDRC_DDRDSR_2_NML_SHIFT (30U) /*! NML - No Modified Lines * 0b0..Exist * 0b1..Do not exist */ #define DDR_DDRC_DDRDSR_2_NML(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDRDSR_2_NML_SHIFT)) & DDR_DDRC_DDRDSR_2_NML_MASK) #define DDR_DDRC_DDRDSR_2_IDLE_MASK (0x80000000U) #define DDR_DDRC_DDRDSR_2_IDLE_SHIFT (31U) /*! IDLE - Memory controller idle (read only). * 0b0..Memory controller is busy. * 0b1..Memory controller is idle. */ #define DDR_DDRC_DDRDSR_2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDRDSR_2_IDLE_SHIFT)) & DDR_DDRC_DDRDSR_2_IDLE_MASK) /*! @} */ /*! @name DDR_IP_REV1 - DDRC Revision 1 */ /*! @{ */ #define DDR_DDRC_DDR_IP_REV1_IP_MN_MASK (0xFFU) #define DDR_DDRC_DDR_IP_REV1_IP_MN_SHIFT (0U) /*! IP_MN - Minor Revision */ #define DDR_DDRC_DDR_IP_REV1_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_IP_REV1_IP_MN_SHIFT)) & DDR_DDRC_DDR_IP_REV1_IP_MN_MASK) #define DDR_DDRC_DDR_IP_REV1_IP_MJ_MASK (0xFF00U) #define DDR_DDRC_DDR_IP_REV1_IP_MJ_SHIFT (8U) /*! IP_MJ - Major Revision */ #define DDR_DDRC_DDR_IP_REV1_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_IP_REV1_IP_MJ_SHIFT)) & DDR_DDRC_DDR_IP_REV1_IP_MJ_MASK) #define DDR_DDRC_DDR_IP_REV1_IP_ID_MASK (0xFFFF0000U) #define DDR_DDRC_DDR_IP_REV1_IP_ID_SHIFT (16U) /*! IP_ID - IP Block ID */ #define DDR_DDRC_DDR_IP_REV1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_IP_REV1_IP_ID_SHIFT)) & DDR_DDRC_DDR_IP_REV1_IP_ID_MASK) /*! @} */ /*! @name DDR_MTCR - DDR SDRAM Memory Test Control */ /*! @{ */ #define DDR_DDRC_DDR_MTCR_MT_STAT_MASK (0x1U) #define DDR_DDRC_DDR_MTCR_MT_STAT_SHIFT (0U) /*! MT_STAT - Memory Test Status * 0b0..No fail detected * 0b1..Data miscompare detected */ #define DDR_DDRC_DDR_MTCR_MT_STAT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MTCR_MT_STAT_SHIFT)) & DDR_DDRC_DDR_MTCR_MT_STAT_MASK) #define DDR_DDRC_DDR_MTCR_MT_ADDR_EN_MASK (0x200U) #define DDR_DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT (9U) /*! MT_ADDR_EN - Memory Test Address Range Enable * 0b0..Memory range that the CSn_BNDS registers define * 0b1..Memory range that the DDR_MT_ST_EXT_ADDR, DDR_MT_ST_ADDR, DDR_MT_END_EXT_ADDR, and DDR_MT_END_ADDR registers define */ #define DDR_DDRC_DDR_MTCR_MT_ADDR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT)) & DDR_DDRC_DDR_MTCR_MT_ADDR_EN_MASK) #define DDR_DDRC_DDR_MTCR_MT_TRNARND_MASK (0xF0000U) #define DDR_DDRC_DDR_MTCR_MT_TRNARND_SHIFT (16U) /*! MT_TRNARND - Memory Test Turnaround * 0b0000..Entire memory is written to before read transactions are issued. * 0b0001..Total write and read streams are one transaction each. * 0b0010..Total write and read streams are two transactions each. * 0b0011..Total write and read streams are four transactions each. * *.. */ #define DDR_DDRC_DDR_MTCR_MT_TRNARND(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MTCR_MT_TRNARND_SHIFT)) & DDR_DDRC_DDR_MTCR_MT_TRNARND_MASK) #define DDR_DDRC_DDR_MTCR_MT_TYP_MASK (0x3000000U) #define DDR_DDRC_DDR_MTCR_MT_TYP_SHIFT (24U) /*! MT_TYP - Memory Test Type * 0b00..Both writes and reads * 0b01..Only writes * 0b10..Only reads * 0b11..Reserved */ #define DDR_DDRC_DDR_MTCR_MT_TYP(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MTCR_MT_TYP_SHIFT)) & DDR_DDRC_DDR_MTCR_MT_TYP_MASK) #define DDR_DDRC_DDR_MTCR_MT_EN_MASK (0x80000000U) #define DDR_DDRC_DDR_MTCR_MT_EN_SHIFT (31U) /*! MT_EN - Memory Test Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_DDR_MTCR_MT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MTCR_MT_EN_SHIFT)) & DDR_DDRC_DDR_MTCR_MT_EN_MASK) /*! @} */ /*! @name DDR_MTP - DDR SDRAM Memory Test Pattern n */ /*! @{ */ #define DDR_DDRC_DDR_MTP_DDR_PATT_MASK (0xFFFFFFFFU) #define DDR_DDRC_DDR_MTP_DDR_PATT_SHIFT (0U) /*! DDR_PATT - DDR SDRAM Pattern */ #define DDR_DDRC_DDR_MTP_DDR_PATT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MTP_DDR_PATT_SHIFT)) & DDR_DDRC_DDR_MTP_DDR_PATT_MASK) /*! @} */ /* The count of DDR_DDRC_DDR_MTP */ #define DDR_DDRC_DDR_MTP_COUNT (10U) /*! @name DDR_MT_ST_EXT_ADDR - DDR SDRAM Memory Test Start Extended Address */ /*! @{ */ #define DDR_DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK (0xFFU) #define DDR_DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT (0U) /*! MT_ST_EXT_ADDR - Memory Test Start Extended Address */ #define DDR_DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT)) & DDR_DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK) /*! @} */ /*! @name DDR_MT_ST_ADDR - DDR SDRAM Memory Test Start Address */ /*! @{ */ #define DDR_DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK (0xFFFFFFFFU) #define DDR_DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT (0U) /*! MT_ST_ADDR - Memory Test Start Address */ #define DDR_DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT)) & DDR_DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK) /*! @} */ /*! @name DDR_MT_END_EXT_ADDR - DDR SDRAM Memory Test End Extended Address */ /*! @{ */ #define DDR_DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK (0xFFU) #define DDR_DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT (0U) /*! MT_END_EXT_ADDR - Memory Test End Extended Address */ #define DDR_DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT)) & DDR_DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK) /*! @} */ /*! @name DDR_MT_END_ADDR - DDR SDRAM Memory Test End Address */ /*! @{ */ #define DDR_DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK (0xFFFFFFFFU) #define DDR_DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT (0U) /*! MT_END_ADDR - Memory Test End Address */ #define DDR_DDRC_DDR_MT_END_ADDR_MT_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT)) & DDR_DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK) /*! @} */ /*! @name ERR_EN - Error Enable */ /*! @{ */ #define DDR_DDRC_ERR_EN_WTE_EN_MASK (0x1U) #define DDR_DDRC_ERR_EN_WTE_EN_SHIFT (0U) /*! WTE_EN - Write Tag Error Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_WTE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_WTE_EN_SHIFT)) & DDR_DDRC_ERR_EN_WTE_EN_MASK) #define DDR_DDRC_ERR_EN_RTE_EN_MASK (0x2U) #define DDR_DDRC_ERR_EN_RTE_EN_SHIFT (1U) /*! RTE_EN - Read Tag Error Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_RTE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_RTE_EN_SHIFT)) & DDR_DDRC_ERR_EN_RTE_EN_MASK) #define DDR_DDRC_ERR_EN_PAR_1_EN_MASK (0x20U) #define DDR_DDRC_ERR_EN_PAR_1_EN_SHIFT (5U) /*! PAR_1_EN - Parity Enable For Internal Errors * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_PAR_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_PAR_1_EN_SHIFT)) & DDR_DDRC_ERR_EN_PAR_1_EN_MASK) #define DDR_DDRC_ERR_EN_ECC_EN_RAM_2_MASK (0x40U) #define DDR_DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT (6U) /*! ECC_EN_RAM_2 - ECC Enable For On-Chip RAM 2 * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_ECC_EN_RAM_2(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT)) & DDR_DDRC_ERR_EN_ECC_EN_RAM_2_MASK) #define DDR_DDRC_ERR_EN_ECC_EN_RAM_1_MASK (0x80U) #define DDR_DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT (7U) /*! ECC_EN_RAM_1 - ECC Enable For On-Chip RAM 1 * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_ECC_EN_RAM_1(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT)) & DDR_DDRC_ERR_EN_ECC_EN_RAM_1_MASK) #define DDR_DDRC_ERR_EN_CRC_2_EN_MASK (0x100U) #define DDR_DDRC_ERR_EN_CRC_2_EN_SHIFT (8U) /*! CRC_2_EN - CRC Enable For Group 2 Registers * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_CRC_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_CRC_2_EN_SHIFT)) & DDR_DDRC_ERR_EN_CRC_2_EN_MASK) #define DDR_DDRC_ERR_EN_CRC_1_EN_MASK (0x200U) #define DDR_DDRC_ERR_EN_CRC_1_EN_SHIFT (9U) /*! CRC_1_EN - CRC Enable For Group 1 Registers * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_CRC_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_CRC_1_EN_SHIFT)) & DDR_DDRC_ERR_EN_CRC_1_EN_MASK) #define DDR_DDRC_ERR_EN_INLINE_ECC_EN_MASK (0x40000000U) #define DDR_DDRC_ERR_EN_INLINE_ECC_EN_SHIFT (30U) /*! INLINE_ECC_EN - Inline ECC Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_INLINE_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_INLINE_ECC_EN_SHIFT)) & DDR_DDRC_ERR_EN_INLINE_ECC_EN_MASK) #define DDR_DDRC_ERR_EN_ECC_EN_MASK (0x80000000U) #define DDR_DDRC_ERR_EN_ECC_EN_SHIFT (31U) /*! ECC_EN - ECC Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_EN_ECC_EN_SHIFT)) & DDR_DDRC_ERR_EN_ECC_EN_MASK) /*! @} */ /*! @name DATA_ERR_INJECT_HI - Memory Data Path Error Injection Mask High */ /*! @{ */ #define DDR_DDRC_DATA_ERR_INJECT_HI_EIMH_MASK (0xFFFFFFFFU) #define DDR_DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT (0U) /*! EIMH - Error Injection Mask High Data Path */ #define DDR_DDRC_DATA_ERR_INJECT_HI_EIMH(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT)) & DDR_DDRC_DATA_ERR_INJECT_HI_EIMH_MASK) /*! @} */ /*! @name DATA_ERR_INJECT_LO - Memory Data Path Error Injection Mask Low */ /*! @{ */ #define DDR_DDRC_DATA_ERR_INJECT_LO_EIML_MASK (0xFFFFFFFFU) #define DDR_DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT (0U) /*! EIML - Error Injection Mask Low Data Bit */ #define DDR_DDRC_DATA_ERR_INJECT_LO_EIML(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT)) & DDR_DDRC_DATA_ERR_INJECT_LO_EIML_MASK) /*! @} */ /*! @name ERR_INJECT - Memory Data Path Error Injection Mask ECC */ /*! @{ */ #define DDR_DDRC_ERR_INJECT_EEIM_MASK (0xFFU) #define DDR_DDRC_ERR_INJECT_EEIM_SHIFT (0U) /*! EEIM - ECC Error Injection Mask */ #define DDR_DDRC_ERR_INJECT_EEIM(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_EEIM_SHIFT)) & DDR_DDRC_ERR_INJECT_EEIM_MASK) #define DDR_DDRC_ERR_INJECT_EIEN_MASK (0x100U) #define DDR_DDRC_ERR_INJECT_EIEN_SHIFT (8U) /*! EIEN - Error Injection Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_INJECT_EIEN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_EIEN_SHIFT)) & DDR_DDRC_ERR_INJECT_EIEN_MASK) #define DDR_DDRC_ERR_INJECT_NUM_ECC_INJ_MASK (0xF000U) #define DDR_DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT (12U) /*! NUM_ECC_INJ - Number Of ECC Errors Injected * 0b0000..ECC errors are injected until the error injection is disabled * 0b0001..4 * 0b0010..8 * 0b0011..16 * 0b0100..20 * 0b0101..24 * 0b0110..28 * 0b0111..32 * 0b1000..36 * 0b1001..40 * 0b1010..44 * 0b1011..48 * 0b1100..52 * 0b1101..56 * 0b1110..60 * 0b1111..64 */ #define DDR_DDRC_ERR_INJECT_NUM_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT)) & DDR_DDRC_ERR_INJECT_NUM_ECC_INJ_MASK) #define DDR_DDRC_ERR_INJECT_PIEN_MASK (0x10000U) #define DDR_DDRC_ERR_INJECT_PIEN_SHIFT (16U) /*! PIEN - Parity Error Injection Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_INJECT_PIEN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_PIEN_SHIFT)) & DDR_DDRC_ERR_INJECT_PIEN_MASK) #define DDR_DDRC_ERR_INJECT_INTEIN_MASK (0x20000U) #define DDR_DDRC_ERR_INJECT_INTEIN_SHIFT (17U) /*! INTEIN - Internal Error Injection Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_INJECT_INTEIN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_INTEIN_SHIFT)) & DDR_DDRC_ERR_INJECT_INTEIN_MASK) #define DDR_DDRC_ERR_INJECT_INTIES_MASK (0x1C0000U) #define DDR_DDRC_ERR_INJECT_INTIES_SHIFT (18U) /*! INTIES - Internal Error Injection Source * 0b000..Read tag * 0b001..Write tag * 0b010..Read tag timeout * 0b011..Write tag timeout * 0b100..Reserved * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define DDR_DDRC_ERR_INJECT_INTIES(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_INTIES_SHIFT)) & DDR_DDRC_ERR_INJECT_INTIES_MASK) #define DDR_DDRC_ERR_INJECT_ECC_INJ_SRC_MASK (0x600000U) #define DDR_DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT (21U) /*! ECC_INJ_SRC - ECC Injection Source * 0b00..DDR SDRAM ECC using programmed data and ECC injection masks * 0b01..On-chip RAM ECC 1 * 0b10..On-chip RAM ECC 2 * 0b11..DDR SDRAM ECC. This setting forces a 1 or 2-bit ECC syndrome error based on the value of FRC2B */ #define DDR_DDRC_ERR_INJECT_ECC_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT)) & DDR_DDRC_ERR_INJECT_ECC_INJ_SRC_MASK) #define DDR_DDRC_ERR_INJECT_FRC2B_MASK (0x800000U) #define DDR_DDRC_ERR_INJECT_FRC2B_SHIFT (23U) /*! FRC2B - Force 2-Bit Error * 0b0..SBE * 0b1..2-bit error */ #define DDR_DDRC_ERR_INJECT_FRC2B(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_FRC2B_SHIFT)) & DDR_DDRC_ERR_INJECT_FRC2B_MASK) #define DDR_DDRC_ERR_INJECT_PAR_INJ_SRC_MASK (0x3000000U) #define DDR_DDRC_ERR_INJECT_PAR_INJ_SRC_SHIFT (24U) /*! PAR_INJ_SRC - Parity Error Injection Source * 0b00..On-chip write buffer ECC * 0b01..On-chip parity 1 * 0b10..On-chip parity 2 * 0b11..On-chip parity 3 */ #define DDR_DDRC_ERR_INJECT_PAR_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_PAR_INJ_SRC_SHIFT)) & DDR_DDRC_ERR_INJECT_PAR_INJ_SRC_MASK) #define DDR_DDRC_ERR_INJECT_ADDR_TEN_MASK (0x80000000U) #define DDR_DDRC_ERR_INJECT_ADDR_TEN_SHIFT (31U) /*! ADDR_TEN - Address Trigger Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_INJECT_ADDR_TEN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INJECT_ADDR_TEN_SHIFT)) & DDR_DDRC_ERR_INJECT_ADDR_TEN_MASK) /*! @} */ /*! @name ADDR_ERR_INJ - Address Error Inject */ /*! @{ */ #define DDR_DDRC_ADDR_ERR_INJ_ADDR_MASK (0xFFFFFFFFU) #define DDR_DDRC_ADDR_ERR_INJ_ADDR_SHIFT (0U) /*! ADDR - Address */ #define DDR_DDRC_ADDR_ERR_INJ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ADDR_ERR_INJ_ADDR_SHIFT)) & DDR_DDRC_ADDR_ERR_INJ_ADDR_MASK) /*! @} */ /*! @name EXT_ADDR_ERR_INJ - Extended Address Error Inject */ /*! @{ */ #define DDR_DDRC_EXT_ADDR_ERR_INJ_EADDR_MASK (0xFFU) #define DDR_DDRC_EXT_ADDR_ERR_INJ_EADDR_SHIFT (0U) /*! EADDR - Extended Address */ #define DDR_DDRC_EXT_ADDR_ERR_INJ_EADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_EXT_ADDR_ERR_INJ_EADDR_SHIFT)) & DDR_DDRC_EXT_ADDR_ERR_INJ_EADDR_MASK) /*! @} */ /*! @name CAPTURE_EXT_DATA_HI - Memory Extended Data Path Read Capture High */ /*! @{ */ #define DDR_DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK (0xFFFFFFFFU) #define DDR_DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT (0U) /*! ECEHD - Error Capture Extended High Data Path */ #define DDR_DDRC_CAPTURE_EXT_DATA_HI_ECEHD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT)) & DDR_DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK) /*! @} */ /*! @name CAPTURE_EXT_DATA_LO - Memory Extended Data Path Read Capture Low */ /*! @{ */ #define DDR_DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK (0xFFFFFFFFU) #define DDR_DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT (0U) /*! ECELD - Error Capture Extended Low Data Path */ #define DDR_DDRC_CAPTURE_EXT_DATA_LO_ECELD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT)) & DDR_DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK) /*! @} */ /*! @name CAPTURE_DATA_HI - Memory Data Path Read Capture High */ /*! @{ */ #define DDR_DDRC_CAPTURE_DATA_HI_ECHD_MASK (0xFFFFFFFFU) #define DDR_DDRC_CAPTURE_DATA_HI_ECHD_SHIFT (0U) /*! ECHD - Error Capture High Data Path */ #define DDR_DDRC_CAPTURE_DATA_HI_ECHD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_DATA_HI_ECHD_SHIFT)) & DDR_DDRC_CAPTURE_DATA_HI_ECHD_MASK) /*! @} */ /*! @name CAPTURE_DATA_LO - Memory Data Path Read Capture Low */ /*! @{ */ #define DDR_DDRC_CAPTURE_DATA_LO_ECLD_MASK (0xFFFFFFFFU) #define DDR_DDRC_CAPTURE_DATA_LO_ECLD_SHIFT (0U) /*! ECLD - Error Capture Low Data Path */ #define DDR_DDRC_CAPTURE_DATA_LO_ECLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_DATA_LO_ECLD_SHIFT)) & DDR_DDRC_CAPTURE_DATA_LO_ECLD_MASK) /*! @} */ /*! @name CAPTURE_ECC - Memory Data Path Read Capture ECC */ /*! @{ */ #define DDR_DDRC_CAPTURE_ECC_ECE_MASK (0xFFFFFFFFU) #define DDR_DDRC_CAPTURE_ECC_ECE_SHIFT (0U) /*! ECE - Error Capture ECC */ #define DDR_DDRC_CAPTURE_ECC_ECE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_ECC_ECE_SHIFT)) & DDR_DDRC_CAPTURE_ECC_ECE_MASK) /*! @} */ /*! @name ERR_DETECT - Memory Error Detect */ /*! @{ */ #define DDR_DDRC_ERR_DETECT_MSE_MASK (0x1U) #define DDR_DDRC_ERR_DETECT_MSE_SHIFT (0U) /*! MSE - Memory-Select Error * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_MSE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_MSE_SHIFT)) & DDR_DDRC_ERR_DETECT_MSE_MASK) #define DDR_DDRC_ERR_DETECT_SBE_MASK (0x4U) #define DDR_DDRC_ERR_DETECT_SBE_SHIFT (2U) /*! SBE - Single-Bit ECC Errors * 0b0..Did not cross * 0b1..Crossed */ #define DDR_DDRC_ERR_DETECT_SBE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_SBE_SHIFT)) & DDR_DDRC_ERR_DETECT_SBE_MASK) #define DDR_DDRC_ERR_DETECT_MBE_MASK (0x8U) #define DDR_DDRC_ERR_DETECT_MBE_SHIFT (3U) /*! MBE - Multiple-Bit Error * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_MBE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_MBE_SHIFT)) & DDR_DDRC_ERR_DETECT_MBE_MASK) #define DDR_DDRC_ERR_DETECT_ILLTXNE_MASK (0x10U) #define DDR_DDRC_ERR_DETECT_ILLTXNE_SHIFT (4U) /*! ILLTXNE - Illegal transaction error. * 0b0..An illegal transaction has not been detected by the DDRC. * 0b1..A illegal transaction has been detected by the DDRC. */ #define DDR_DDRC_ERR_DETECT_ILLTXNE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_ILLTXNE_SHIFT)) & DDR_DDRC_ERR_DETECT_ILLTXNE_MASK) #define DDR_DDRC_ERR_DETECT_REFRATEE_MASK (0x80U) #define DDR_DDRC_ERR_DETECT_REFRATEE_SHIFT (7U) /*! REFRATEE - Refresh rate error. * 0b0..A refresh rate error has not been detected. * 0b1..A refresh rate error has been detected. */ #define DDR_DDRC_ERR_DETECT_REFRATEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_REFRATEE_SHIFT)) & DDR_DDRC_ERR_DETECT_REFRATEE_MASK) #define DDR_DDRC_ERR_DETECT_SSBE_MASK (0x1000U) #define DDR_DDRC_ERR_DETECT_SSBE_SHIFT (12U) /*! SSBE - Scrubbed Single-Bit ECC Error * 0b0..Did not cross * 0b1..Crossed */ #define DDR_DDRC_ERR_DETECT_SSBE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_SSBE_SHIFT)) & DDR_DDRC_ERR_DETECT_SSBE_MASK) #define DDR_DDRC_ERR_DETECT_LNKE_MASK (0x2000U) #define DDR_DDRC_ERR_DETECT_LNKE_SHIFT (13U) /*! LNKE - Link ECC Error * 0b0..Did not cross * 0b1..Crossed */ #define DDR_DDRC_ERR_DETECT_LNKE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_LNKE_SHIFT)) & DDR_DDRC_ERR_DETECT_LNKE_MASK) #define DDR_DDRC_ERR_DETECT_PHYE_MASK (0x10000U) #define DDR_DDRC_ERR_DETECT_PHYE_SHIFT (16U) /*! PHYE - PHY error. * 0b0..A DDR PHY error has not been detected. * 0b1..An error has been detected by the DDR PHY. */ #define DDR_DDRC_ERR_DETECT_PHYE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_PHYE_SHIFT)) & DDR_DDRC_ERR_DETECT_PHYE_MASK) #define DDR_DDRC_ERR_DETECT_IPE_MASK (0x80000U) #define DDR_DDRC_ERR_DETECT_IPE_SHIFT (19U) /*! IPE - Internal Parity Error * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_IPE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_IPE_SHIFT)) & DDR_DDRC_ERR_DETECT_IPE_MASK) #define DDR_DDRC_ERR_DETECT_UPDTMTE_MASK (0x100000U) #define DDR_DDRC_ERR_DETECT_UPDTMTE_SHIFT (20U) /*! UPDTMTE - Update Timeout Error * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_UPDTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_UPDTMTE_SHIFT)) & DDR_DDRC_ERR_DETECT_UPDTMTE_MASK) #define DDR_DDRC_ERR_DETECT_CRCE_MASK (0x200000U) #define DDR_DDRC_ERR_DETECT_CRCE_SHIFT (21U) /*! CRCE - Configuration CRC Error * 0b0..Did not occur * 0b1..Occurred */ #define DDR_DDRC_ERR_DETECT_CRCE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_CRCE_SHIFT)) & DDR_DDRC_ERR_DETECT_CRCE_MASK) #define DDR_DDRC_ERR_DETECT_SMBE2_MASK (0x400000U) #define DDR_DDRC_ERR_DETECT_SMBE2_SHIFT (22U) /*! SMBE2 - SRAM Multi-Bit Error 2 * 0b0..Did not occur * 0b1..Occurred */ #define DDR_DDRC_ERR_DETECT_SMBE2(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_SMBE2_SHIFT)) & DDR_DDRC_ERR_DETECT_SMBE2_MASK) #define DDR_DDRC_ERR_DETECT_SMBE1_MASK (0x800000U) #define DDR_DDRC_ERR_DETECT_SMBE1_SHIFT (23U) /*! SMBE1 - SRAM Multi-Bit Error 1 * 0b0..Did not occur * 0b1..Occurred */ #define DDR_DDRC_ERR_DETECT_SMBE1(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_SMBE1_SHIFT)) & DDR_DDRC_ERR_DETECT_SMBE1_MASK) #define DDR_DDRC_ERR_DETECT_SSBE2_MASK (0x1000000U) #define DDR_DDRC_ERR_DETECT_SSBE2_SHIFT (24U) /*! SSBE2 - SRAM SBE 2 * 0b0..Did not occur * 0b1..Occurred */ #define DDR_DDRC_ERR_DETECT_SSBE2(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_SSBE2_SHIFT)) & DDR_DDRC_ERR_DETECT_SSBE2_MASK) #define DDR_DDRC_ERR_DETECT_SSBE1_MASK (0x2000000U) #define DDR_DDRC_ERR_DETECT_SSBE1_SHIFT (25U) /*! SSBE1 - SRAM SBE 1 * 0b0..Did not occur * 0b1..Occurred */ #define DDR_DDRC_ERR_DETECT_SSBE1(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_SSBE1_SHIFT)) & DDR_DDRC_ERR_DETECT_SSBE1_MASK) #define DDR_DDRC_ERR_DETECT_WTAGE_MASK (0x4000000U) #define DDR_DDRC_ERR_DETECT_WTAGE_SHIFT (26U) /*! WTAGE - Write Tag Error * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_WTAGE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_WTAGE_SHIFT)) & DDR_DDRC_ERR_DETECT_WTAGE_MASK) #define DDR_DDRC_ERR_DETECT_RTAGE_MASK (0x8000000U) #define DDR_DDRC_ERR_DETECT_RTAGE_SHIFT (27U) /*! RTAGE - Read Tag Error * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_RTAGE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_RTAGE_SHIFT)) & DDR_DDRC_ERR_DETECT_RTAGE_MASK) #define DDR_DDRC_ERR_DETECT_WTTE_MASK (0x10000000U) #define DDR_DDRC_ERR_DETECT_WTTE_SHIFT (28U) /*! WTTE - Write Tag Timeout Error * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_DETECT_WTTE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_WTTE_SHIFT)) & DDR_DDRC_ERR_DETECT_WTTE_MASK) #define DDR_DDRC_ERR_DETECT_RTTE_MASK (0x20000000U) #define DDR_DDRC_ERR_DETECT_RTTE_SHIFT (29U) /*! RTTE - Read Tag Timeout Error * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_ERR_DETECT_RTTE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_RTTE_SHIFT)) & DDR_DDRC_ERR_DETECT_RTTE_MASK) #define DDR_DDRC_ERR_DETECT_RTMTE_MASK (0x40000000U) #define DDR_DDRC_ERR_DETECT_RTMTE_SHIFT (30U) /*! RTMTE - Read Timeout Error * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_RTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_RTMTE_SHIFT)) & DDR_DDRC_ERR_DETECT_RTMTE_MASK) #define DDR_DDRC_ERR_DETECT_MME_MASK (0x80000000U) #define DDR_DDRC_ERR_DETECT_MME_SHIFT (31U) /*! MME - Multiple Memory Errors * 0b0..Not detected * 0b1..Detected */ #define DDR_DDRC_ERR_DETECT_MME(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DETECT_MME_SHIFT)) & DDR_DDRC_ERR_DETECT_MME_MASK) /*! @} */ /*! @name ERR_DISABLE - Memory Error Disable */ /*! @{ */ #define DDR_DDRC_ERR_DISABLE_MSED_MASK (0x1U) #define DDR_DDRC_ERR_DISABLE_MSED_SHIFT (0U) /*! MSED - Memory-Select Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_MSED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_MSED_SHIFT)) & DDR_DDRC_ERR_DISABLE_MSED_MASK) #define DDR_DDRC_ERR_DISABLE_SBED_MASK (0x4U) #define DDR_DDRC_ERR_DISABLE_SBED_SHIFT (2U) /*! SBED - Single-Bit ECC Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_SBED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_SBED_SHIFT)) & DDR_DDRC_ERR_DISABLE_SBED_MASK) #define DDR_DDRC_ERR_DISABLE_MBED_MASK (0x8U) #define DDR_DDRC_ERR_DISABLE_MBED_SHIFT (3U) /*! MBED - Multiple-Bit ECC Error Disable * 0b0..Detected * 0b1..Not detected or reported */ #define DDR_DDRC_ERR_DISABLE_MBED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_MBED_SHIFT)) & DDR_DDRC_ERR_DISABLE_MBED_MASK) #define DDR_DDRC_ERR_DISABLE_ILLTXNED_MASK (0x10U) #define DDR_DDRC_ERR_DISABLE_ILLTXNED_SHIFT (4U) /*! ILLTXNED - Illegal Transaction Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_ILLTXNED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_ILLTXNED_SHIFT)) & DDR_DDRC_ERR_DISABLE_ILLTXNED_MASK) #define DDR_DDRC_ERR_DISABLE_REFRATEED_MASK (0x80U) #define DDR_DDRC_ERR_DISABLE_REFRATEED_SHIFT (7U) /*! REFRATEED - Refresh Rate Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_REFRATEED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_REFRATEED_SHIFT)) & DDR_DDRC_ERR_DISABLE_REFRATEED_MASK) #define DDR_DDRC_ERR_DISABLE_LNKED_MASK (0x100U) #define DDR_DDRC_ERR_DISABLE_LNKED_SHIFT (8U) /*! LNKED - Link ECC Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_LNKED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_LNKED_SHIFT)) & DDR_DDRC_ERR_DISABLE_LNKED_MASK) #define DDR_DDRC_ERR_DISABLE_SSBED_MASK (0x1000U) #define DDR_DDRC_ERR_DISABLE_SSBED_SHIFT (12U) /*! SSBED - Scrubbed Single-Bit ECC Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_SSBED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_SSBED_SHIFT)) & DDR_DDRC_ERR_DISABLE_SSBED_MASK) #define DDR_DDRC_ERR_DISABLE_PHYED_MASK (0x10000U) #define DDR_DDRC_ERR_DISABLE_PHYED_SHIFT (16U) /*! PHYED - PHY Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_PHYED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_PHYED_SHIFT)) & DDR_DDRC_ERR_DISABLE_PHYED_MASK) #define DDR_DDRC_ERR_DISABLE_UPDTMTED_MASK (0x100000U) #define DDR_DDRC_ERR_DISABLE_UPDTMTED_SHIFT (20U) /*! UPDTMTED - Update Timeout Error Disable * 0b0..Enables * 0b1..Disables */ #define DDR_DDRC_ERR_DISABLE_UPDTMTED(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_DISABLE_UPDTMTED_SHIFT)) & DDR_DDRC_ERR_DISABLE_UPDTMTED_MASK) /*! @} */ /*! @name ERR_INT_EN - Memory Error Interrupt Enable */ /*! @{ */ #define DDR_DDRC_ERR_INT_EN_MSEE_MASK (0x1U) #define DDR_DDRC_ERR_INT_EN_MSEE_SHIFT (0U) /*! MSEE - Memory-Select Error Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_MSEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_MSEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_MSEE_MASK) #define DDR_DDRC_ERR_INT_EN_SBEE_MASK (0x4U) #define DDR_DDRC_ERR_INT_EN_SBEE_SHIFT (2U) /*! SBEE - Single-Bit ECC Error Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_SBEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_SBEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_SBEE_MASK) #define DDR_DDRC_ERR_INT_EN_MBEE_MASK (0x8U) #define DDR_DDRC_ERR_INT_EN_MBEE_SHIFT (3U) /*! MBEE - Multiple-Bit ECC Error Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_MBEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_MBEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_MBEE_MASK) #define DDR_DDRC_ERR_INT_EN_SSBE12E_MASK (0x10U) #define DDR_DDRC_ERR_INT_EN_SSBE12E_SHIFT (4U) /*! SSBE12E - SRAM Single-Bit Error Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_SSBE12E(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_SSBE12E_SHIFT)) & DDR_DDRC_ERR_INT_EN_SSBE12E_MASK) #define DDR_DDRC_ERR_INT_EN_REFRATEEE_MASK (0x80U) #define DDR_DDRC_ERR_INT_EN_REFRATEEE_SHIFT (7U) /*! REFRATEEE - Refresh Rate Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_REFRATEEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_REFRATEEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_REFRATEEE_MASK) #define DDR_DDRC_ERR_INT_EN_ILLTXNEE_MASK (0x100U) #define DDR_DDRC_ERR_INT_EN_ILLTXNEE_SHIFT (8U) /*! ILLTXNEE - Illegal Transaction Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_ILLTXNEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_ILLTXNEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_ILLTXNEE_MASK) #define DDR_DDRC_ERR_INT_EN_LNKEE_MASK (0x200U) #define DDR_DDRC_ERR_INT_EN_LNKEE_SHIFT (9U) /*! LNKEE - Link ECC Error Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_LNKEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_LNKEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_LNKEE_MASK) #define DDR_DDRC_ERR_INT_EN_SSBEE_MASK (0x1000U) #define DDR_DDRC_ERR_INT_EN_SSBEE_SHIFT (12U) /*! SSBEE - Scrubbed Single-Bit ECC Error Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_SSBEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_SSBEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_SSBEE_MASK) #define DDR_DDRC_ERR_INT_EN_PHYEE_MASK (0x10000U) #define DDR_DDRC_ERR_INT_EN_PHYEE_SHIFT (16U) /*! PHYEE - PHY error interrupt enable. * 0b0..PHY errors cannot generate interrupts. * 0b1..PHY errors generate interrupts. */ #define DDR_DDRC_ERR_INT_EN_PHYEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_PHYEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_PHYEE_MASK) #define DDR_DDRC_ERR_INT_EN_UPDTMTEE_MASK (0x100000U) #define DDR_DDRC_ERR_INT_EN_UPDTMTEE_SHIFT (20U) /*! UPDTMTEE - Update Timeout Interrupt Enable * 0b0..No * 0b1..Yes */ #define DDR_DDRC_ERR_INT_EN_UPDTMTEE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_INT_EN_UPDTMTEE_SHIFT)) & DDR_DDRC_ERR_INT_EN_UPDTMTEE_MASK) /*! @} */ /*! @name CAPTURE_ATTRIBUTES - Memory Error Attributes Capture */ /*! @{ */ #define DDR_DDRC_CAPTURE_ATTRIBUTES_VLD_MASK (0x1U) #define DDR_DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT (0U) /*! VLD - Valid */ #define DDR_DDRC_CAPTURE_ATTRIBUTES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT)) & DDR_DDRC_CAPTURE_ATTRIBUTES_VLD_MASK) #define DDR_DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK (0x3000U) #define DDR_DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT (12U) /*! TTYP - Error Transaction Type * 0b00..Reserved * 0b01..Write * 0b10..Read * 0b11..Read-modify-write */ #define DDR_DDRC_CAPTURE_ATTRIBUTES_TTYP(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT)) & DDR_DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK) #define DDR_DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK (0x7000000U) #define DDR_DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT (24U) /*! TSIZ - Error Transaction Size * 0b000..8 * 0b001..1 * 0b010..2 * 0b011..3 * 0b100..4 * 0b101..5 * 0b110..6 * 0b111..7 */ #define DDR_DDRC_CAPTURE_ATTRIBUTES_TSIZ(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_ATTRIBUTES_TSIZ_SHIFT)) & DDR_DDRC_CAPTURE_ATTRIBUTES_TSIZ_MASK) #define DDR_DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK (0x70000000U) #define DDR_DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT (28U) /*! BNUM - Data Beat Number */ #define DDR_DDRC_CAPTURE_ATTRIBUTES_BNUM(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT)) & DDR_DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK) /*! @} */ /*! @name CAPTURE_ADDRESS - Memory Error Address Capture */ /*! @{ */ #define DDR_DDRC_CAPTURE_ADDRESS_CADDR_MASK (0xFFFFFFFFU) #define DDR_DDRC_CAPTURE_ADDRESS_CADDR_SHIFT (0U) /*! CADDR - Captured Address */ #define DDR_DDRC_CAPTURE_ADDRESS_CADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_ADDRESS_CADDR_SHIFT)) & DDR_DDRC_CAPTURE_ADDRESS_CADDR_MASK) /*! @} */ /*! @name CAPTURE_EXT_ADDRESS - Memory Error Extended Address Capture */ /*! @{ */ #define DDR_DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK (0xFFU) #define DDR_DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT (0U) /*! CEADDR - Captured Extended Address */ #define DDR_DDRC_CAPTURE_EXT_ADDRESS_CEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT)) & DDR_DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK) /*! @} */ /*! @name ERR_SBE - Single-Bit ECC Memory Error Management */ /*! @{ */ #define DDR_DDRC_ERR_SBE_SBEC_MASK (0xFFU) #define DDR_DDRC_ERR_SBE_SBEC_SHIFT (0U) /*! SBEC - SBE Counter */ #define DDR_DDRC_ERR_SBE_SBEC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_SBE_SBEC_SHIFT)) & DDR_DDRC_ERR_SBE_SBEC_MASK) #define DDR_DDRC_ERR_SBE_SSBEC_MASK (0xFF00U) #define DDR_DDRC_ERR_SBE_SSBEC_SHIFT (8U) /*! SSBEC - Scrubbed SBE Counter */ #define DDR_DDRC_ERR_SBE_SSBEC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_SBE_SSBEC_SHIFT)) & DDR_DDRC_ERR_SBE_SSBEC_MASK) #define DDR_DDRC_ERR_SBE_SBET_MASK (0xFF0000U) #define DDR_DDRC_ERR_SBE_SBET_SHIFT (16U) /*! SBET - SBE Threshold */ #define DDR_DDRC_ERR_SBE_SBET(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_SBE_SBET_SHIFT)) & DDR_DDRC_ERR_SBE_SBET_MASK) #define DDR_DDRC_ERR_SBE_SSBET_MASK (0xFF000000U) #define DDR_DDRC_ERR_SBE_SSBET_SHIFT (24U) /*! SSBET - Scrubbed SBE Threshold */ #define DDR_DDRC_ERR_SBE_SSBET(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ERR_SBE_SSBET_SHIFT)) & DDR_DDRC_ERR_SBE_SSBET_MASK) /*! @} */ /*! @name REG_CRC_GRP_1 - Register CRC Code For Group 1 */ /*! @{ */ #define DDR_DDRC_REG_CRC_GRP_1_CRC_1_MASK (0xFFFFFFFFU) #define DDR_DDRC_REG_CRC_GRP_1_CRC_1_SHIFT (0U) /*! CRC_1 - Programmed CRC Code */ #define DDR_DDRC_REG_CRC_GRP_1_CRC_1(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REG_CRC_GRP_1_CRC_1_SHIFT)) & DDR_DDRC_REG_CRC_GRP_1_CRC_1_MASK) /*! @} */ /*! @name REG_CRC_GRP_2 - Register CRC Code For Group 2 */ /*! @{ */ #define DDR_DDRC_REG_CRC_GRP_2_CRC_2_MASK (0xFFFFFFFFU) #define DDR_DDRC_REG_CRC_GRP_2_CRC_2_SHIFT (0U) /*! CRC_2 - Programmed CRC Code */ #define DDR_DDRC_REG_CRC_GRP_2_CRC_2(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_REG_CRC_GRP_2_CRC_2_SHIFT)) & DDR_DDRC_REG_CRC_GRP_2_CRC_2_MASK) /*! @} */ /*! @name ECC_EXT_REG_0 - ECC Extended Region 0 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_SHIFT (0U) /*! EXT_REG_0_EA - Extended Region 0 End Address */ #define DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_SHIFT (16U) /*! EXT_REG_0_SA - Extended Region 0 Start Address */ #define DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_0_EXT_REG_0_SA_MASK) /*! @} */ /*! @name ECC_EXT_REG_1 - ECC Extended Region 1 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_SHIFT (0U) /*! EXT_REG_1_EA - Extended Region 1 End Address */ #define DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_SHIFT (16U) /*! EXT_REG_1_SA - Extended Region 1 Start Address */ #define DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_1_EXT_REG_1_SA_MASK) /*! @} */ /*! @name ECC_EXT_REG_2 - ECC Extended Region 2 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_SHIFT (0U) /*! EXT_REG_2_EA - Extended Region 2 End Address */ #define DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_SHIFT (16U) /*! EXT_REG_2_SA - Extended Region 2 Start Address */ #define DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_2_EXT_REG_2_SA_MASK) /*! @} */ /*! @name ECC_EXT_REG_3 - ECC Extended Region 3 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_SHIFT (0U) /*! EXT_REG_3_EA - Extended Region 3 End Address */ #define DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_SHIFT (16U) /*! EXT_REG_3_SA - Extended Region 3 Start Address */ #define DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_3_EXT_REG_3_SA_MASK) /*! @} */ /*! @name ECC_EXT_REG_4 - ECC Extended Region 4 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_SHIFT (0U) /*! EXT_REG_4_EA - Extended Region 4 End Address */ #define DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_SHIFT (16U) /*! EXT_REG_4_SA - Extended Region 4 Start Address */ #define DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_4_EXT_REG_4_SA_MASK) /*! @} */ /*! @name ECC_EXT_REG_5 - ECC Extended Region 5 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_SHIFT (0U) /*! EXT_REG_5_EA - Extended Region 5 End Address */ #define DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_SHIFT (16U) /*! EXT_REG_5_SA - Extended Region 5 Start Address */ #define DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_5_EXT_REG_5_SA_MASK) /*! @} */ /*! @name ECC_EXT_REG_6 - ECC Extended Region 6 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_SHIFT (0U) /*! EXT_REG_6_EA - Extended Region 6 End Address */ #define DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_SHIFT (16U) /*! EXT_REG_6_SA - Extended Region 6 Start Address */ #define DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_6_EXT_REG_6_SA_MASK) /*! @} */ /*! @name ECC_EXT_REG_7 - ECC Extended Region 7 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_MASK (0xFFU) #define DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_SHIFT (0U) /*! EXT_REG_7_EA - Extended Region 7 End Address */ #define DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_EA_MASK) #define DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_MASK (0xFF0000U) #define DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_SHIFT (16U) /*! EXT_REG_7_SA - Extended Region 7 Start Address */ #define DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_SHIFT)) & DDR_DDRC_ECC_EXT_REG_7_EXT_REG_7_SA_MASK) /*! @} */ /*! @name ECC_REG_0 - ECC Region 0 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_0_REG_0_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_0_REG_0_EA_SHIFT (0U) /*! REG_0_EA - Region 0 End Address */ #define DDR_DDRC_ECC_REG_0_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_0_REG_0_EA_SHIFT)) & DDR_DDRC_ECC_REG_0_REG_0_EA_MASK) #define DDR_DDRC_ECC_REG_0_REG_0_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_0_REG_0_SA_SHIFT (16U) /*! REG_0_SA - Region 0 Start Address */ #define DDR_DDRC_ECC_REG_0_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_0_REG_0_SA_SHIFT)) & DDR_DDRC_ECC_REG_0_REG_0_SA_MASK) #define DDR_DDRC_ECC_REG_0_REG_0_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_0_REG_0_EN_SHIFT (31U) /*! REG_0_EN - Region 0 Enable * 0b0..Does not use region 0 for ECC enablement * 0b1..Protects addresses from region 0 with ECC */ #define DDR_DDRC_ECC_REG_0_REG_0_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_0_REG_0_EN_SHIFT)) & DDR_DDRC_ECC_REG_0_REG_0_EN_MASK) /*! @} */ /*! @name ECC_REG_1 - ECC Region 1 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_1_REG_1_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_1_REG_1_EA_SHIFT (0U) /*! REG_1_EA - Region 1 End Address */ #define DDR_DDRC_ECC_REG_1_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_1_REG_1_EA_SHIFT)) & DDR_DDRC_ECC_REG_1_REG_1_EA_MASK) #define DDR_DDRC_ECC_REG_1_REG_1_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_1_REG_1_SA_SHIFT (16U) /*! REG_1_SA - Region 1 Start Address */ #define DDR_DDRC_ECC_REG_1_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_1_REG_1_SA_SHIFT)) & DDR_DDRC_ECC_REG_1_REG_1_SA_MASK) #define DDR_DDRC_ECC_REG_1_REG_1_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_1_REG_1_EN_SHIFT (31U) /*! REG_1_EN - Region 1 Enable * 0b0..Does not use region 1 for ECC enablement * 0b1..Protects addresses from region 1 with ECC */ #define DDR_DDRC_ECC_REG_1_REG_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_1_REG_1_EN_SHIFT)) & DDR_DDRC_ECC_REG_1_REG_1_EN_MASK) /*! @} */ /*! @name ECC_REG_2 - ECC Region 2 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_2_REG_2_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_2_REG_2_EA_SHIFT (0U) /*! REG_2_EA - Region 2 End Address */ #define DDR_DDRC_ECC_REG_2_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_2_REG_2_EA_SHIFT)) & DDR_DDRC_ECC_REG_2_REG_2_EA_MASK) #define DDR_DDRC_ECC_REG_2_REG_2_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_2_REG_2_SA_SHIFT (16U) /*! REG_2_SA - Region 2 Start Address */ #define DDR_DDRC_ECC_REG_2_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_2_REG_2_SA_SHIFT)) & DDR_DDRC_ECC_REG_2_REG_2_SA_MASK) #define DDR_DDRC_ECC_REG_2_REG_2_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_2_REG_2_EN_SHIFT (31U) /*! REG_2_EN - Region 2 Enable * 0b0..Does not use region 2 for ECC enablement * 0b1..Protects addresses from region 2 with ECC */ #define DDR_DDRC_ECC_REG_2_REG_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_2_REG_2_EN_SHIFT)) & DDR_DDRC_ECC_REG_2_REG_2_EN_MASK) /*! @} */ /*! @name ECC_REG_3 - ECC Region 3 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_3_REG_3_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_3_REG_3_EA_SHIFT (0U) /*! REG_3_EA - Region 3 End Address */ #define DDR_DDRC_ECC_REG_3_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_3_REG_3_EA_SHIFT)) & DDR_DDRC_ECC_REG_3_REG_3_EA_MASK) #define DDR_DDRC_ECC_REG_3_REG_3_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_3_REG_3_SA_SHIFT (16U) /*! REG_3_SA - Region 3 Start Address */ #define DDR_DDRC_ECC_REG_3_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_3_REG_3_SA_SHIFT)) & DDR_DDRC_ECC_REG_3_REG_3_SA_MASK) #define DDR_DDRC_ECC_REG_3_REG_3_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_3_REG_3_EN_SHIFT (31U) /*! REG_3_EN - Region 3 Enable * 0b0..Does not use region 3 for ECC enablement * 0b1..Protects addresses from region 3 with ECC */ #define DDR_DDRC_ECC_REG_3_REG_3_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_3_REG_3_EN_SHIFT)) & DDR_DDRC_ECC_REG_3_REG_3_EN_MASK) /*! @} */ /*! @name ECC_REG_4 - ECC Region 4 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_4_REG_4_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_4_REG_4_EA_SHIFT (0U) /*! REG_4_EA - Region 4 End Address */ #define DDR_DDRC_ECC_REG_4_REG_4_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_4_REG_4_EA_SHIFT)) & DDR_DDRC_ECC_REG_4_REG_4_EA_MASK) #define DDR_DDRC_ECC_REG_4_REG_4_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_4_REG_4_SA_SHIFT (16U) /*! REG_4_SA - Region 4 Start Address */ #define DDR_DDRC_ECC_REG_4_REG_4_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_4_REG_4_SA_SHIFT)) & DDR_DDRC_ECC_REG_4_REG_4_SA_MASK) #define DDR_DDRC_ECC_REG_4_REG_4_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_4_REG_4_EN_SHIFT (31U) /*! REG_4_EN - Region 4 Enable * 0b0..Does not use region 4 for ECC enablement * 0b1..Protects addresses from region 4 with ECC */ #define DDR_DDRC_ECC_REG_4_REG_4_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_4_REG_4_EN_SHIFT)) & DDR_DDRC_ECC_REG_4_REG_4_EN_MASK) /*! @} */ /*! @name ECC_REG_5 - ECC Region 5 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_5_REG_5_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_5_REG_5_EA_SHIFT (0U) /*! REG_5_EA - Region 5 End Address */ #define DDR_DDRC_ECC_REG_5_REG_5_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_5_REG_5_EA_SHIFT)) & DDR_DDRC_ECC_REG_5_REG_5_EA_MASK) #define DDR_DDRC_ECC_REG_5_REG_5_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_5_REG_5_SA_SHIFT (16U) /*! REG_5_SA - Region 5 Start Address */ #define DDR_DDRC_ECC_REG_5_REG_5_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_5_REG_5_SA_SHIFT)) & DDR_DDRC_ECC_REG_5_REG_5_SA_MASK) #define DDR_DDRC_ECC_REG_5_REG_5_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_5_REG_5_EN_SHIFT (31U) /*! REG_5_EN - Region 5 Enable * 0b0..Does not use region 5 for ECC enablement * 0b1..Protects addresses from region 5 with ECC */ #define DDR_DDRC_ECC_REG_5_REG_5_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_5_REG_5_EN_SHIFT)) & DDR_DDRC_ECC_REG_5_REG_5_EN_MASK) /*! @} */ /*! @name ECC_REG_6 - ECC Region 6 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_6_REG_6_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_6_REG_6_EA_SHIFT (0U) /*! REG_6_EA - Region 6 End Address */ #define DDR_DDRC_ECC_REG_6_REG_6_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_6_REG_6_EA_SHIFT)) & DDR_DDRC_ECC_REG_6_REG_6_EA_MASK) #define DDR_DDRC_ECC_REG_6_REG_6_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_6_REG_6_SA_SHIFT (16U) /*! REG_6_SA - Region 6 Start Address */ #define DDR_DDRC_ECC_REG_6_REG_6_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_6_REG_6_SA_SHIFT)) & DDR_DDRC_ECC_REG_6_REG_6_SA_MASK) #define DDR_DDRC_ECC_REG_6_REG_6_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_6_REG_6_EN_SHIFT (31U) /*! REG_6_EN - Region 6 Enable * 0b0..Does not use region 6 for ECC enablement * 0b1..Protects addresses from region 6 with ECC */ #define DDR_DDRC_ECC_REG_6_REG_6_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_6_REG_6_EN_SHIFT)) & DDR_DDRC_ECC_REG_6_REG_6_EN_MASK) /*! @} */ /*! @name ECC_REG_7 - ECC Region 7 Configuration */ /*! @{ */ #define DDR_DDRC_ECC_REG_7_REG_7_EA_MASK (0xFFFU) #define DDR_DDRC_ECC_REG_7_REG_7_EA_SHIFT (0U) /*! REG_7_EA - Region 7 End Address */ #define DDR_DDRC_ECC_REG_7_REG_7_EA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_7_REG_7_EA_SHIFT)) & DDR_DDRC_ECC_REG_7_REG_7_EA_MASK) #define DDR_DDRC_ECC_REG_7_REG_7_SA_MASK (0xFFF0000U) #define DDR_DDRC_ECC_REG_7_REG_7_SA_SHIFT (16U) /*! REG_7_SA - Region 7 Start Address */ #define DDR_DDRC_ECC_REG_7_REG_7_SA(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_7_REG_7_SA_SHIFT)) & DDR_DDRC_ECC_REG_7_REG_7_SA_MASK) #define DDR_DDRC_ECC_REG_7_REG_7_EN_MASK (0x80000000U) #define DDR_DDRC_ECC_REG_7_REG_7_EN_SHIFT (31U) /*! REG_7_EN - Region 7 Enable * 0b0..Does not use region 7 for ECC enablement * 0b1..Protects addresses from region 7 with ECC */ #define DDR_DDRC_ECC_REG_7_REG_7_EN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_ECC_REG_7_REG_7_EN_SHIFT)) & DDR_DDRC_ECC_REG_7_REG_7_EN_MASK) /*! @} */ /*! @name PMGC0 - Performance Monitor Global Control */ /*! @{ */ #define DDR_DDRC_PMGC0_FCECE_MASK (0x20000000U) #define DDR_DDRC_PMGC0_FCECE_SHIFT (29U) /*! FCECE - Freeze Counters On Enabled Condition Or Event * 0b0..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. * 0b1..Enabled if PMLCAn[CE] = 1, until an event or condition occurs. At this point, if PMGC0[FAC] = 1, you must write 0 to it. */ #define DDR_DDRC_PMGC0_FCECE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMGC0_FCECE_SHIFT)) & DDR_DDRC_PMGC0_FCECE_MASK) #define DDR_DDRC_PMGC0_PMIE_MASK (0x40000000U) #define DDR_DDRC_PMGC0_PMIE_SHIFT (30U) /*! PMIE - Performance Monitor Interrupt Enable * 0b0..Disables * 0b1..Enables */ #define DDR_DDRC_PMGC0_PMIE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMGC0_PMIE_SHIFT)) & DDR_DDRC_PMGC0_PMIE_MASK) #define DDR_DDRC_PMGC0_FAC_MASK (0x80000000U) #define DDR_DDRC_PMGC0_FAC_SHIFT (31U) /*! FAC - Freeze All Counters * 0b0..Incremented * 0b1..Not incremented */ #define DDR_DDRC_PMGC0_FAC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMGC0_FAC_SHIFT)) & DDR_DDRC_PMGC0_FAC_MASK) /*! @} */ /*! @name PMLCA0 - Performance Monitor Local Control A0 */ /*! @{ */ #define DDR_DDRC_PMLCA0_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA0_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions for PMC0n cannot occur (PMC0n cannot cause interrupts or freeze counters) * 0b1..Counter overflow conditions occur when the most-significant bit of PMC0n is 1 */ #define DDR_DDRC_PMLCA0_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA0_CE_SHIFT)) & DDR_DDRC_PMLCA0_CE_MASK) #define DDR_DDRC_PMLCA0_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA0_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA0_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA0_FC_SHIFT)) & DDR_DDRC_PMLCA0_FC_MASK) /*! @} */ /*! @name PMLCB0 - Performance Monitor Local Control B0 */ /*! @{ */ #define DDR_DDRC_PMLCB0_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB0_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB0_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB0_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB0_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB0_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB0_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB0_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB0_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB0_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB0_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB0_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB0_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB0_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB0_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB0_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB0_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB0_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB0_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB0_TRIGONSEL_MASK) /*! @} */ /*! @name PMC0A - PMC 0a */ /*! @{ */ #define DDR_DDRC_PMC0A_PMC0_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC0A_PMC0_SHIFT (0U) /*! PMC0 - Counter 0 */ #define DDR_DDRC_PMC0A_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC0A_PMC0_SHIFT)) & DDR_DDRC_PMC0A_PMC0_MASK) /*! @} */ /*! @name PMC0B - PMC 0b */ /*! @{ */ #define DDR_DDRC_PMC0B_PMC0_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC0B_PMC0_SHIFT (0U) /*! PMC0 - Counter 0 */ #define DDR_DDRC_PMC0B_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC0B_PMC0_SHIFT)) & DDR_DDRC_PMC0B_PMC0_MASK) /*! @} */ /*! @name PMLCA1 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA1_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA1_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA1_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA1_BDIST_SHIFT)) & DDR_DDRC_PMLCA1_BDIST_MASK) #define DDR_DDRC_PMLCA1_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA1_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA1_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA1_BGRAN_SHIFT)) & DDR_DDRC_PMLCA1_BGRAN_MASK) #define DDR_DDRC_PMLCA1_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA1_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA1_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA1_BSIZE_SHIFT)) & DDR_DDRC_PMLCA1_BSIZE_MASK) #define DDR_DDRC_PMLCA1_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA1_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA1_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA1_EVENT_SHIFT)) & DDR_DDRC_PMLCA1_EVENT_MASK) #define DDR_DDRC_PMLCA1_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA1_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA1_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA1_CE_SHIFT)) & DDR_DDRC_PMLCA1_CE_MASK) #define DDR_DDRC_PMLCA1_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA1_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA1_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA1_FC_SHIFT)) & DDR_DDRC_PMLCA1_FC_MASK) /*! @} */ /*! @name PMLCB1 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB1_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB1_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB1_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB1_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB1_THRESHOLD_MASK) #define DDR_DDRC_PMLCB1_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB1_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB1_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB1_TBMULT_SHIFT)) & DDR_DDRC_PMLCB1_TBMULT_MASK) #define DDR_DDRC_PMLCB1_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB1_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB1_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB1_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB1_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB1_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB1_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB1_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB1_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB1_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB1_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB1_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB1_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB1_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB1_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB1_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB1_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB1_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB1_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB1_TRIGONSEL_MASK) /*! @} */ /*! @name PMC1 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC1_PMC1_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC1_PMC1_SHIFT (0U) /*! PMC1 - Event Count */ #define DDR_DDRC_PMC1_PMC1(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC1_PMC1_SHIFT)) & DDR_DDRC_PMC1_PMC1_MASK) /*! @} */ /*! @name PMLCA2 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA2_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA2_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA2_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA2_BDIST_SHIFT)) & DDR_DDRC_PMLCA2_BDIST_MASK) #define DDR_DDRC_PMLCA2_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA2_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA2_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA2_BGRAN_SHIFT)) & DDR_DDRC_PMLCA2_BGRAN_MASK) #define DDR_DDRC_PMLCA2_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA2_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA2_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA2_BSIZE_SHIFT)) & DDR_DDRC_PMLCA2_BSIZE_MASK) #define DDR_DDRC_PMLCA2_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA2_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA2_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA2_EVENT_SHIFT)) & DDR_DDRC_PMLCA2_EVENT_MASK) #define DDR_DDRC_PMLCA2_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA2_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA2_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA2_CE_SHIFT)) & DDR_DDRC_PMLCA2_CE_MASK) #define DDR_DDRC_PMLCA2_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA2_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA2_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA2_FC_SHIFT)) & DDR_DDRC_PMLCA2_FC_MASK) /*! @} */ /*! @name PMLCB2 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB2_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB2_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB2_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB2_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB2_THRESHOLD_MASK) #define DDR_DDRC_PMLCB2_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB2_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB2_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB2_TBMULT_SHIFT)) & DDR_DDRC_PMLCB2_TBMULT_MASK) #define DDR_DDRC_PMLCB2_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB2_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB2_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB2_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB2_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB2_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB2_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB2_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB2_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB2_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB2_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB2_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB2_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB2_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB2_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB2_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB2_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB2_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB2_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB2_TRIGONSEL_MASK) /*! @} */ /*! @name PMC2 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC2_PMC2_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC2_PMC2_SHIFT (0U) /*! PMC2 - Event Count */ #define DDR_DDRC_PMC2_PMC2(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC2_PMC2_SHIFT)) & DDR_DDRC_PMC2_PMC2_MASK) /*! @} */ /*! @name PMLCA3 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA3_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA3_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA3_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA3_BDIST_SHIFT)) & DDR_DDRC_PMLCA3_BDIST_MASK) #define DDR_DDRC_PMLCA3_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA3_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA3_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA3_BGRAN_SHIFT)) & DDR_DDRC_PMLCA3_BGRAN_MASK) #define DDR_DDRC_PMLCA3_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA3_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA3_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA3_BSIZE_SHIFT)) & DDR_DDRC_PMLCA3_BSIZE_MASK) #define DDR_DDRC_PMLCA3_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA3_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA3_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA3_EVENT_SHIFT)) & DDR_DDRC_PMLCA3_EVENT_MASK) #define DDR_DDRC_PMLCA3_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA3_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA3_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA3_CE_SHIFT)) & DDR_DDRC_PMLCA3_CE_MASK) #define DDR_DDRC_PMLCA3_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA3_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA3_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA3_FC_SHIFT)) & DDR_DDRC_PMLCA3_FC_MASK) /*! @} */ /*! @name PMLCB3 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB3_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB3_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB3_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB3_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB3_THRESHOLD_MASK) #define DDR_DDRC_PMLCB3_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB3_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB3_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB3_TBMULT_SHIFT)) & DDR_DDRC_PMLCB3_TBMULT_MASK) #define DDR_DDRC_PMLCB3_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB3_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB3_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB3_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB3_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB3_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB3_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB3_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB3_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB3_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB3_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB3_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB3_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB3_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB3_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB3_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB3_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB3_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB3_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB3_TRIGONSEL_MASK) /*! @} */ /*! @name PMC3 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC3_PMC3_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC3_PMC3_SHIFT (0U) /*! PMC3 - Event Count */ #define DDR_DDRC_PMC3_PMC3(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC3_PMC3_SHIFT)) & DDR_DDRC_PMC3_PMC3_MASK) /*! @} */ /*! @name PMLCA4 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA4_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA4_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA4_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA4_BDIST_SHIFT)) & DDR_DDRC_PMLCA4_BDIST_MASK) #define DDR_DDRC_PMLCA4_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA4_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA4_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA4_BGRAN_SHIFT)) & DDR_DDRC_PMLCA4_BGRAN_MASK) #define DDR_DDRC_PMLCA4_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA4_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA4_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA4_BSIZE_SHIFT)) & DDR_DDRC_PMLCA4_BSIZE_MASK) #define DDR_DDRC_PMLCA4_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA4_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA4_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA4_EVENT_SHIFT)) & DDR_DDRC_PMLCA4_EVENT_MASK) #define DDR_DDRC_PMLCA4_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA4_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA4_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA4_CE_SHIFT)) & DDR_DDRC_PMLCA4_CE_MASK) #define DDR_DDRC_PMLCA4_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA4_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA4_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA4_FC_SHIFT)) & DDR_DDRC_PMLCA4_FC_MASK) /*! @} */ /*! @name PMLCB4 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB4_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB4_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB4_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB4_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB4_THRESHOLD_MASK) #define DDR_DDRC_PMLCB4_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB4_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB4_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB4_TBMULT_SHIFT)) & DDR_DDRC_PMLCB4_TBMULT_MASK) #define DDR_DDRC_PMLCB4_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB4_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB4_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB4_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB4_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB4_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB4_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB4_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB4_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB4_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB4_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB4_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB4_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB4_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB4_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB4_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB4_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB4_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB4_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB4_TRIGONSEL_MASK) /*! @} */ /*! @name PMC4 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC4_PMC4_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC4_PMC4_SHIFT (0U) /*! PMC4 - Event Count */ #define DDR_DDRC_PMC4_PMC4(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC4_PMC4_SHIFT)) & DDR_DDRC_PMC4_PMC4_MASK) /*! @} */ /*! @name PMLCA5 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA5_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA5_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA5_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA5_BDIST_SHIFT)) & DDR_DDRC_PMLCA5_BDIST_MASK) #define DDR_DDRC_PMLCA5_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA5_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA5_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA5_BGRAN_SHIFT)) & DDR_DDRC_PMLCA5_BGRAN_MASK) #define DDR_DDRC_PMLCA5_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA5_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA5_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA5_BSIZE_SHIFT)) & DDR_DDRC_PMLCA5_BSIZE_MASK) #define DDR_DDRC_PMLCA5_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA5_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA5_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA5_EVENT_SHIFT)) & DDR_DDRC_PMLCA5_EVENT_MASK) #define DDR_DDRC_PMLCA5_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA5_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA5_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA5_CE_SHIFT)) & DDR_DDRC_PMLCA5_CE_MASK) #define DDR_DDRC_PMLCA5_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA5_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA5_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA5_FC_SHIFT)) & DDR_DDRC_PMLCA5_FC_MASK) /*! @} */ /*! @name PMLCB5 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB5_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB5_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB5_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB5_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB5_THRESHOLD_MASK) #define DDR_DDRC_PMLCB5_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB5_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB5_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB5_TBMULT_SHIFT)) & DDR_DDRC_PMLCB5_TBMULT_MASK) #define DDR_DDRC_PMLCB5_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB5_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB5_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB5_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB5_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB5_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB5_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB5_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB5_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB5_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB5_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB5_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB5_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB5_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB5_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB5_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB5_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB5_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB5_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB5_TRIGONSEL_MASK) /*! @} */ /*! @name PMC5 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC5_PMC5_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC5_PMC5_SHIFT (0U) /*! PMC5 - Event Count */ #define DDR_DDRC_PMC5_PMC5(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC5_PMC5_SHIFT)) & DDR_DDRC_PMC5_PMC5_MASK) /*! @} */ /*! @name PMLCA6 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA6_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA6_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA6_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA6_BDIST_SHIFT)) & DDR_DDRC_PMLCA6_BDIST_MASK) #define DDR_DDRC_PMLCA6_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA6_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA6_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA6_BGRAN_SHIFT)) & DDR_DDRC_PMLCA6_BGRAN_MASK) #define DDR_DDRC_PMLCA6_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA6_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA6_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA6_BSIZE_SHIFT)) & DDR_DDRC_PMLCA6_BSIZE_MASK) #define DDR_DDRC_PMLCA6_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA6_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA6_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA6_EVENT_SHIFT)) & DDR_DDRC_PMLCA6_EVENT_MASK) #define DDR_DDRC_PMLCA6_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA6_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA6_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA6_CE_SHIFT)) & DDR_DDRC_PMLCA6_CE_MASK) #define DDR_DDRC_PMLCA6_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA6_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA6_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA6_FC_SHIFT)) & DDR_DDRC_PMLCA6_FC_MASK) /*! @} */ /*! @name PMLCB6 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB6_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB6_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB6_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB6_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB6_THRESHOLD_MASK) #define DDR_DDRC_PMLCB6_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB6_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB6_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB6_TBMULT_SHIFT)) & DDR_DDRC_PMLCB6_TBMULT_MASK) #define DDR_DDRC_PMLCB6_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB6_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB6_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB6_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB6_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB6_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB6_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB6_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB6_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB6_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB6_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB6_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB6_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB6_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB6_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB6_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB6_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB6_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB6_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB6_TRIGONSEL_MASK) /*! @} */ /*! @name PMC6 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC6_PMC6_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC6_PMC6_SHIFT (0U) /*! PMC6 - Event Count */ #define DDR_DDRC_PMC6_PMC6(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC6_PMC6_SHIFT)) & DDR_DDRC_PMC6_PMC6_MASK) /*! @} */ /*! @name PMLCA7 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA7_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA7_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA7_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA7_BDIST_SHIFT)) & DDR_DDRC_PMLCA7_BDIST_MASK) #define DDR_DDRC_PMLCA7_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA7_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA7_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA7_BGRAN_SHIFT)) & DDR_DDRC_PMLCA7_BGRAN_MASK) #define DDR_DDRC_PMLCA7_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA7_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA7_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA7_BSIZE_SHIFT)) & DDR_DDRC_PMLCA7_BSIZE_MASK) #define DDR_DDRC_PMLCA7_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA7_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA7_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA7_EVENT_SHIFT)) & DDR_DDRC_PMLCA7_EVENT_MASK) #define DDR_DDRC_PMLCA7_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA7_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA7_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA7_CE_SHIFT)) & DDR_DDRC_PMLCA7_CE_MASK) #define DDR_DDRC_PMLCA7_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA7_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA7_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA7_FC_SHIFT)) & DDR_DDRC_PMLCA7_FC_MASK) /*! @} */ /*! @name PMLCB7 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB7_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB7_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB7_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB7_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB7_THRESHOLD_MASK) #define DDR_DDRC_PMLCB7_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB7_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB7_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB7_TBMULT_SHIFT)) & DDR_DDRC_PMLCB7_TBMULT_MASK) #define DDR_DDRC_PMLCB7_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB7_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB7_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB7_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB7_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB7_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB7_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB7_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB7_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB7_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB7_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB7_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB7_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB7_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB7_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB7_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB7_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB7_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB7_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB7_TRIGONSEL_MASK) /*! @} */ /*! @name PMC7 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC7_PMC7_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC7_PMC7_SHIFT (0U) /*! PMC7 - Event Count */ #define DDR_DDRC_PMC7_PMC7(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC7_PMC7_SHIFT)) & DDR_DDRC_PMC7_PMC7_MASK) /*! @} */ /*! @name PMLCA8 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA8_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA8_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA8_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA8_BDIST_SHIFT)) & DDR_DDRC_PMLCA8_BDIST_MASK) #define DDR_DDRC_PMLCA8_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA8_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA8_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA8_BGRAN_SHIFT)) & DDR_DDRC_PMLCA8_BGRAN_MASK) #define DDR_DDRC_PMLCA8_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA8_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA8_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA8_BSIZE_SHIFT)) & DDR_DDRC_PMLCA8_BSIZE_MASK) #define DDR_DDRC_PMLCA8_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA8_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA8_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA8_EVENT_SHIFT)) & DDR_DDRC_PMLCA8_EVENT_MASK) #define DDR_DDRC_PMLCA8_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA8_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA8_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA8_CE_SHIFT)) & DDR_DDRC_PMLCA8_CE_MASK) #define DDR_DDRC_PMLCA8_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA8_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA8_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA8_FC_SHIFT)) & DDR_DDRC_PMLCA8_FC_MASK) /*! @} */ /*! @name PMLCB8 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB8_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB8_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB8_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB8_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB8_THRESHOLD_MASK) #define DDR_DDRC_PMLCB8_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB8_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB8_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB8_TBMULT_SHIFT)) & DDR_DDRC_PMLCB8_TBMULT_MASK) #define DDR_DDRC_PMLCB8_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB8_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB8_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB8_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB8_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB8_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB8_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB8_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB8_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB8_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB8_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB8_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB8_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB8_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB8_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB8_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB8_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB8_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB8_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB8_TRIGONSEL_MASK) /*! @} */ /*! @name PMC8 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC8_PMC8_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC8_PMC8_SHIFT (0U) /*! PMC8 - Event Count */ #define DDR_DDRC_PMC8_PMC8(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC8_PMC8_SHIFT)) & DDR_DDRC_PMC8_PMC8_MASK) /*! @} */ /*! @name PMLCA9 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA9_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA9_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA9_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA9_BDIST_SHIFT)) & DDR_DDRC_PMLCA9_BDIST_MASK) #define DDR_DDRC_PMLCA9_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA9_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA9_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA9_BGRAN_SHIFT)) & DDR_DDRC_PMLCA9_BGRAN_MASK) #define DDR_DDRC_PMLCA9_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA9_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA9_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA9_BSIZE_SHIFT)) & DDR_DDRC_PMLCA9_BSIZE_MASK) #define DDR_DDRC_PMLCA9_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA9_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA9_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA9_EVENT_SHIFT)) & DDR_DDRC_PMLCA9_EVENT_MASK) #define DDR_DDRC_PMLCA9_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA9_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA9_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA9_CE_SHIFT)) & DDR_DDRC_PMLCA9_CE_MASK) #define DDR_DDRC_PMLCA9_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA9_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA9_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA9_FC_SHIFT)) & DDR_DDRC_PMLCA9_FC_MASK) /*! @} */ /*! @name PMLCB9 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB9_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB9_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB9_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB9_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB9_THRESHOLD_MASK) #define DDR_DDRC_PMLCB9_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB9_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB9_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB9_TBMULT_SHIFT)) & DDR_DDRC_PMLCB9_TBMULT_MASK) #define DDR_DDRC_PMLCB9_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB9_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB9_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB9_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB9_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB9_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB9_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB9_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB9_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB9_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB9_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB9_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB9_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB9_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB9_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB9_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB9_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB9_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB9_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB9_TRIGONSEL_MASK) /*! @} */ /*! @name PMC9 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC9_PMC9_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC9_PMC9_SHIFT (0U) /*! PMC9 - Event Count */ #define DDR_DDRC_PMC9_PMC9(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC9_PMC9_SHIFT)) & DDR_DDRC_PMC9_PMC9_MASK) /*! @} */ /*! @name PMLCA10 - Performance Monitor Local Control A */ /*! @{ */ #define DDR_DDRC_PMLCA10_BDIST_MASK (0x3FU) #define DDR_DDRC_PMLCA10_BDIST_SHIFT (0U) /*! BDIST - Burst Distance */ #define DDR_DDRC_PMLCA10_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA10_BDIST_SHIFT)) & DDR_DDRC_PMLCA10_BDIST_MASK) #define DDR_DDRC_PMLCA10_BGRAN_MASK (0x7C0U) #define DDR_DDRC_PMLCA10_BGRAN_SHIFT (6U) /*! BGRAN - Burst Granularity */ #define DDR_DDRC_PMLCA10_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA10_BGRAN_SHIFT)) & DDR_DDRC_PMLCA10_BGRAN_MASK) #define DDR_DDRC_PMLCA10_BSIZE_MASK (0xF800U) #define DDR_DDRC_PMLCA10_BSIZE_SHIFT (11U) /*! BSIZE - Burst Size */ #define DDR_DDRC_PMLCA10_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA10_BSIZE_SHIFT)) & DDR_DDRC_PMLCA10_BSIZE_MASK) #define DDR_DDRC_PMLCA10_EVENT_MASK (0x7F0000U) #define DDR_DDRC_PMLCA10_EVENT_SHIFT (16U) /*! EVENT - Event Selector */ #define DDR_DDRC_PMLCA10_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA10_EVENT_SHIFT)) & DDR_DDRC_PMLCA10_EVENT_MASK) #define DDR_DDRC_PMLCA10_CE_MASK (0x4000000U) #define DDR_DDRC_PMLCA10_CE_SHIFT (26U) /*! CE - Condition Enable * 0b0..Counter overflow conditions cannot occur * 0b1..Counter overflow conditions occur */ #define DDR_DDRC_PMLCA10_CE(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA10_CE_SHIFT)) & DDR_DDRC_PMLCA10_CE_MASK) #define DDR_DDRC_PMLCA10_FC_MASK (0x80000000U) #define DDR_DDRC_PMLCA10_FC_SHIFT (31U) /*! FC - Freeze Counter * 0b0..Enabled * 0b1..Disabled */ #define DDR_DDRC_PMLCA10_FC(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCA10_FC_SHIFT)) & DDR_DDRC_PMLCA10_FC_MASK) /*! @} */ /*! @name PMLCB10 - Performance Monitor Local Control B */ /*! @{ */ #define DDR_DDRC_PMLCB10_THRESHOLD_MASK (0x3FU) #define DDR_DDRC_PMLCB10_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define DDR_DDRC_PMLCB10_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB10_THRESHOLD_SHIFT)) & DDR_DDRC_PMLCB10_THRESHOLD_MASK) #define DDR_DDRC_PMLCB10_TBMULT_MASK (0x700U) #define DDR_DDRC_PMLCB10_TBMULT_SHIFT (8U) /*! TBMULT - Threshold And Burstiness Multiplier * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define DDR_DDRC_PMLCB10_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB10_TBMULT_SHIFT)) & DDR_DDRC_PMLCB10_TBMULT_MASK) #define DDR_DDRC_PMLCB10_TRIGOFFCNTL_MASK (0x30000U) #define DDR_DDRC_PMLCB10_TRIGOFFCNTL_SHIFT (16U) /*! TRIGOFFCNTL - Trigger-Off Control * 0b00..Trigger off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB10_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB10_TRIGOFFCNTL_SHIFT)) & DDR_DDRC_PMLCB10_TRIGOFFCNTL_MASK) #define DDR_DDRC_PMLCB10_TRIGONCNTL_MASK (0xC0000U) #define DDR_DDRC_PMLCB10_TRIGONCNTL_SHIFT (18U) /*! TRIGONCNTL - Trigger-On Control * 0b00..Triggering off (no triggering to start) * 0b01..Trigger on change * 0b10..Trigger on overflow * 0b11..Reserved */ #define DDR_DDRC_PMLCB10_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB10_TRIGONCNTL_SHIFT)) & DDR_DDRC_PMLCB10_TRIGONCNTL_MASK) #define DDR_DDRC_PMLCB10_TRIGOFFSEL_MASK (0xF00000U) #define DDR_DDRC_PMLCB10_TRIGOFFSEL_SHIFT (20U) /*! TRIGOFFSEL - Trigger-Off Select */ #define DDR_DDRC_PMLCB10_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB10_TRIGOFFSEL_SHIFT)) & DDR_DDRC_PMLCB10_TRIGOFFSEL_MASK) #define DDR_DDRC_PMLCB10_TRIGONSEL_MASK (0x3C000000U) #define DDR_DDRC_PMLCB10_TRIGONSEL_SHIFT (26U) /*! TRIGONSEL - Trigger-On Select */ #define DDR_DDRC_PMLCB10_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMLCB10_TRIGONSEL_SHIFT)) & DDR_DDRC_PMLCB10_TRIGONSEL_MASK) /*! @} */ /*! @name PMC10 - Performance Monitor Counter */ /*! @{ */ #define DDR_DDRC_PMC10_PMC10_MASK (0xFFFFFFFFU) #define DDR_DDRC_PMC10_PMC10_SHIFT (0U) /*! PMC10 - Event Count */ #define DDR_DDRC_PMC10_PMC10(x) (((uint32_t)(((uint32_t)(x)) << DDR_DDRC_PMC10_PMC10_SHIFT)) & DDR_DDRC_PMC10_PMC10_MASK) /*! @} */ /*! * @} */ /* end of group DDR_DDRC_Register_Masks */ /* DDR_DDRC - Peripheral instance base addresses */ /** Peripheral DDRC base address */ #define DDRC_BASE (0x4E080000u) /** Peripheral DDRC base pointer */ #define DDRC ((DDR_DDRC_Type *)DDRC_BASE) /** Array initializer of DDR_DDRC peripheral base addresses */ #define DDR_DDRC_BASE_ADDRS { DDRC_BASE } /** Array initializer of DDR_DDRC peripheral base pointers */ #define DDR_DDRC_BASE_PTRS { DDRC } /*! * @} */ /* end of group DDR_DDRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDR_LSTCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_LSTCU_Peripheral_Access_Layer DDR_LSTCU Peripheral Access Layer * @{ */ /** DDR_LSTCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x10 */ uint8_t RESERVED_2[76]; __I uint32_t MB_RSTAT0; /**< MBIST Run Status 0, offset: 0x60 */ uint8_t RESERVED_3[284]; __IO uint32_t MBFM0; /**< MBIST Fault Mapping 0, offset: 0x180 */ uint8_t RESERVED_4[220]; __IO uint32_t STAG; /**< Stagger, offset: 0x260 */ uint8_t RESERVED_5[12]; __IO uint32_t PH1_DUR; /**< Phase 1 Duration, offset: 0x270 */ uint8_t RESERVED_6[140]; __IO uint32_t MBPTR[1]; /**< MBIST Scheduler Pointer, array offset: 0x300, array step: 0x4 */ } DDR_LSTCU_Type; /* ---------------------------------------------------------------------------- -- DDR_LSTCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_LSTCU_Register_Masks DDR_LSTCU Register Masks * @{ */ /*! @name ERR_STAT - Error Status */ /*! @{ */ #define DDR_LSTCU_ERR_STAT_INVP_MB_MASK (0x2U) #define DDR_LSTCU_ERR_STAT_INVP_MB_SHIFT (1U) /*! INVP_MB - Invalid Pointer MBIST * 0b0..No invalid pointer * 0b1..Invalid BIST pointer specified */ #define DDR_LSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_ERR_STAT_INVP_MB_SHIFT)) & DDR_LSTCU_ERR_STAT_INVP_MB_MASK) #define DDR_LSTCU_ERR_STAT_UFSF_MASK (0x10000U) #define DDR_LSTCU_ERR_STAT_UFSF_SHIFT (16U) /*! UFSF - Unrecoverable Fault Status * 0b0..No unrecoverable fault * 0b1..Unrecoverable fault */ #define DDR_LSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_ERR_STAT_UFSF_SHIFT)) & DDR_LSTCU_ERR_STAT_UFSF_MASK) #define DDR_LSTCU_ERR_STAT_RFSF_MASK (0x20000U) #define DDR_LSTCU_ERR_STAT_RFSF_SHIFT (17U) /*! RFSF - Recoverable Fault Status * 0b0..No recoverable fault * 0b1..Recoverable fault */ #define DDR_LSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_ERR_STAT_RFSF_SHIFT)) & DDR_LSTCU_ERR_STAT_RFSF_MASK) /*! @} */ /*! @name ERR_FM - Error Fault Mapping */ /*! @{ */ #define DDR_LSTCU_ERR_FM_INVPFMMB_MASK (0x2U) #define DDR_LSTCU_ERR_FM_INVPFMMB_SHIFT (1U) /*! INVPFMMB - Invalid BIST Pointer Fault Mapping During MBIST Scheduling * 0b0..Recoverable * 0b1..Unrecoverable */ #define DDR_LSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_ERR_FM_INVPFMMB_SHIFT)) & DDR_LSTCU_ERR_FM_INVPFMMB_MASK) /*! @} */ /*! @name MB_RSTAT0 - MBIST Run Status 0 */ /*! @{ */ #define DDR_LSTCU_MB_RSTAT0_MBSTAT0_MASK (0x1U) #define DDR_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT (0U) /*! MBSTAT0 - MBIST Run Result Status 0 * 0b0..Pass * 0b1..Fail */ #define DDR_LSTCU_MB_RSTAT0_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT)) & DDR_LSTCU_MB_RSTAT0_MBSTAT0_MASK) /*! @} */ /*! @name MBFM0 - MBIST Fault Mapping 0 */ /*! @{ */ #define DDR_LSTCU_MBFM0_MBSTATFM0_MASK (0x1U) #define DDR_LSTCU_MBFM0_MBSTATFM0_SHIFT (0U) /*! MBSTATFM0 - MBIST Fault Mapping n * 0b0..Recoverable * 0b1..Unrecoverable */ #define DDR_LSTCU_MBFM0_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_MBFM0_MBSTATFM0_SHIFT)) & DDR_LSTCU_MBFM0_MBSTATFM0_MASK) /*! @} */ /*! @name STAG - Stagger */ /*! @{ */ #define DDR_LSTCU_STAG_MB_DELAY_MASK (0xFF00U) #define DDR_LSTCU_STAG_MB_DELAY_SHIFT (8U) /*! MB_DELAY - MBIST Delay */ #define DDR_LSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_STAG_MB_DELAY_SHIFT)) & DDR_LSTCU_STAG_MB_DELAY_MASK) /*! @} */ /*! @name PH1_DUR - Phase 1 Duration */ /*! @{ */ #define DDR_LSTCU_PH1_DUR_PH1DUR_MASK (0x3FFU) #define DDR_LSTCU_PH1_DUR_PH1DUR_SHIFT (0U) /*! PH1DUR - Phase 1 Duration */ #define DDR_LSTCU_PH1_DUR_PH1DUR(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_PH1_DUR_PH1DUR_SHIFT)) & DDR_LSTCU_PH1_DUR_PH1DUR_MASK) /*! @} */ /*! @name MBPTR - MBIST Scheduler Pointer */ /*! @{ */ #define DDR_LSTCU_MBPTR_MBPTR_MASK (0xFFU) #define DDR_LSTCU_MBPTR_MBPTR_SHIFT (0U) /*! MBPTR - MBIST Pointer */ #define DDR_LSTCU_MBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_MBPTR_MBPTR_SHIFT)) & DDR_LSTCU_MBPTR_MBPTR_MASK) #define DDR_LSTCU_MBPTR_MBCSM_MASK (0x100U) #define DDR_LSTCU_MBPTR_MBCSM_SHIFT (8U) /*! MBCSM - MBIST Mode * 0b0..Sequential * 0b1..Concurrent */ #define DDR_LSTCU_MBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_MBPTR_MBCSM_SHIFT)) & DDR_LSTCU_MBPTR_MBCSM_MASK) #define DDR_LSTCU_MBPTR_MBEOL_MASK (0x80000000U) #define DDR_LSTCU_MBPTR_MBEOL_SHIFT (31U) /*! MBEOL - MBIST End of List * 0b0..Not end of list * 0b1..End of list */ #define DDR_LSTCU_MBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << DDR_LSTCU_MBPTR_MBEOL_SHIFT)) & DDR_LSTCU_MBPTR_MBEOL_MASK) /*! @} */ /* The count of DDR_LSTCU_MBPTR */ #define DDR_LSTCU_MBPTR_COUNT (1U) /*! * @} */ /* end of group DDR_LSTCU_Register_Masks */ /* DDR_LSTCU - Peripheral instance base addresses */ /** Peripheral DDRC__LSTCU base address */ #define DDRC__LSTCU_BASE (0x4E050000u) /** Peripheral DDRC__LSTCU base pointer */ #define DDRC__LSTCU ((DDR_LSTCU_Type *)DDRC__LSTCU_BASE) /** Array initializer of DDR_LSTCU peripheral base addresses */ #define DDR_LSTCU_BASE_ADDRS { DDRC__LSTCU_BASE } /** Array initializer of DDR_LSTCU peripheral base pointers */ #define DDR_LSTCU_BASE_PTRS { DDRC__LSTCU } /*! * @} */ /* end of group DDR_LSTCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DDR_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_TCU_Peripheral_Access_Layer DDR_TCU Peripheral Access Layer * @{ */ /** DDR_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[332]; __IO uint32_t TCU_DFT_DIVIDER; /**< clk divider bypass control, offset: 0x560 */ uint8_t RESERVED_3[28]; __IO uint32_t TCU_DFT_PHY; /**< CRR control on TxBypassOE, offset: 0x580 */ uint8_t RESERVED_4[1532]; struct { /* offset: 0xB80 */ __IO uint32_t RW; /**< TCU DDR BSR control register, offset: 0xB80 */ __IO uint32_t SET; /**< TCU DDR BSR control register, offset: 0xB84 */ __IO uint32_t CLR; /**< TCU DDR BSR control register, offset: 0xB88 */ __IO uint32_t TOG; /**< TCU DDR BSR control register, offset: 0xB8C */ } TCU_DDR_BSR_CONTROL_; uint8_t RESERVED_5[112]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_6[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } DDR_TCU_Type; /* ---------------------------------------------------------------------------- -- DDR_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DDR_TCU_Register_Masks DDR_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define DDR_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define DDR_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define DDR_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & DDR_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define DDR_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define DDR_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define DDR_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & DDR_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_DFT_DIVIDER - clk divider bypass control */ /*! @{ */ #define DDR_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_MASK (0x1U) #define DDR_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_SHIFT (0U) /*! tcu_dft_divider_disable - dft divider disable */ #define DDR_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_SHIFT)) & DDR_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_MASK) /*! @} */ /*! @name TCU_DFT_PHY - CRR control on TxBypassOE */ /*! @{ */ #define DDR_TCU_TCU_DFT_PHY_tcu_crr_txbypassoe_MASK (0x1U) #define DDR_TCU_TCU_DFT_PHY_tcu_crr_txbypassoe_SHIFT (0U) /*! tcu_crr_txbypassoe - dft fuse disable */ #define DDR_TCU_TCU_DFT_PHY_tcu_crr_txbypassoe(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_DFT_PHY_tcu_crr_txbypassoe_SHIFT)) & DDR_TCU_TCU_DFT_PHY_tcu_crr_txbypassoe_MASK) /*! @} */ /*! @name TCU_DDR_BSR_CONTROL_ - TCU DDR BSR control register */ /*! @{ */ #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_mode_en_MASK (0x1U) #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_mode_en_SHIFT (0U) /*! ddr_io_bypass_mode_en - ddr_io_bypass_mode_en */ #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_mode_en(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_mode_en_SHIFT)) & DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_mode_en_MASK) #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_en_MASK (0x2U) #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_en_SHIFT (1U) /*! ddr_io_bypass_out_en - ddr_io_bypass_out_en */ #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_en(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_en_SHIFT)) & DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_en_MASK) #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_data_MASK (0x4U) #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_data_SHIFT (2U) /*! ddr_io_bypass_out_data - ddr_io_bypass_out_data */ #define DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_data(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_data_SHIFT)) & DDR_TCU_TCU_DDR_BSR_CONTROL__ddr_io_bypass_out_data_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define DDR_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define DDR_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & DDR_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define DDR_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & DDR_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define DDR_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & DDR_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define DDR_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & DDR_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define DDR_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & DDR_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define DDR_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define DDR_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & DDR_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define DDR_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define DDR_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define DDR_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & DDR_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define DDR_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x6U) #define DDR_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define DDR_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << DDR_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & DDR_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group DDR_TCU_Register_Masks */ /* DDR_TCU - Peripheral instance base addresses */ /** Peripheral DDRC__TCU base address */ #define DDRC__TCU_BASE (0x4E000000u) /** Peripheral DDRC__TCU base pointer */ #define DDRC__TCU ((DDR_TCU_Type *)DDRC__TCU_BASE) /** Array initializer of DDR_TCU peripheral base addresses */ #define DDR_TCU_BASE_ADDRS { DDRC__TCU_BASE } /** Array initializer of DDR_TCU peripheral base pointers */ #define DDR_TCU_BASE_PTRS { DDRC__TCU } /*! * @} */ /* end of group DDR_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DEMOSAIC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DEMOSAIC_Peripheral_Access_Layer DEMOSAIC Peripheral Access Layer * @{ */ /** DEMOSAIC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10 */ __IO uint32_t CTRL_CAM; /**< Camera 0 Demosaic Control Register, array offset: 0x0, array step: 0x10 */ __IO uint32_t ACTIVITY_CTL_CAM; /**< Camera 0 Demosaic Activity Control Register, array offset: 0x4, array step: 0x10 */ __IO uint32_t DYNAMICS_CTL0_CAM; /**< Camera 0 Demosaic Dynamics Control 0 Register, array offset: 0x8, array step: 0x10 */ __IO uint32_t DYNAMICS_CTL2_CAM; /**< Camera 0 Demosaic Dynamics Control 2 Register, array offset: 0xC, array step: 0x10 */ } NEO_PIPE2_DEMOSAIC_CONF[1]; } DEMOSAIC_Type; /* ---------------------------------------------------------------------------- -- DEMOSAIC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DEMOSAIC_Register_Masks DEMOSAIC Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 Demosaic Control Register */ /*! @{ */ #define DEMOSAIC_CTRL_CAM_FMT_MASK (0x30U) #define DEMOSAIC_CTRL_CAM_FMT_SHIFT (4U) /*! FMT * 0b00..Input image is RGGB Bayer image * 0b01..Input image is RCCC image * 0b10..Input image is Monochrome image */ #define DEMOSAIC_CTRL_CAM_FMT(x) (((uint32_t)(((uint32_t)(x)) << DEMOSAIC_CTRL_CAM_FMT_SHIFT)) & DEMOSAIC_CTRL_CAM_FMT_MASK) /*! @} */ /* The count of DEMOSAIC_CTRL_CAM */ #define DEMOSAIC_CTRL_CAM_COUNT (1U) /*! @name ACTIVITY_CTL_CAM - Camera 0 Demosaic Activity Control Register */ /*! @{ */ #define DEMOSAIC_ACTIVITY_CTL_CAM_ALPHA_MASK (0x1FFU) #define DEMOSAIC_ACTIVITY_CTL_CAM_ALPHA_SHIFT (0U) /*! ALPHA - Blending factor between block (0) and color (256) activity. */ #define DEMOSAIC_ACTIVITY_CTL_CAM_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << DEMOSAIC_ACTIVITY_CTL_CAM_ALPHA_SHIFT)) & DEMOSAIC_ACTIVITY_CTL_CAM_ALPHA_MASK) #define DEMOSAIC_ACTIVITY_CTL_CAM_ACT_RATIO_MASK (0xFFFF0000U) #define DEMOSAIC_ACTIVITY_CTL_CAM_ACT_RATIO_SHIFT (16U) /*! ACT_RATIO - Ratio from minimum activity to activity of direction for selecting the respective * green value of that direction for interpolation. */ #define DEMOSAIC_ACTIVITY_CTL_CAM_ACT_RATIO(x) (((uint32_t)(((uint32_t)(x)) << DEMOSAIC_ACTIVITY_CTL_CAM_ACT_RATIO_SHIFT)) & DEMOSAIC_ACTIVITY_CTL_CAM_ACT_RATIO_MASK) /*! @} */ /* The count of DEMOSAIC_ACTIVITY_CTL_CAM */ #define DEMOSAIC_ACTIVITY_CTL_CAM_COUNT (1U) /*! @name DYNAMICS_CTL0_CAM - Camera 0 Demosaic Dynamics Control 0 Register */ /*! @{ */ #define DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHG_MASK (0xFFFFU) #define DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHG_SHIFT (0U) #define DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHG(x) (((uint32_t)(((uint32_t)(x)) << DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHG_SHIFT)) & DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHG_MASK) #define DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHC_MASK (0xFFFF0000U) #define DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHC_SHIFT (16U) #define DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHC(x) (((uint32_t)(((uint32_t)(x)) << DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHC_SHIFT)) & DEMOSAIC_DYNAMICS_CTL0_CAM_STRENGTHC_MASK) /*! @} */ /* The count of DEMOSAIC_DYNAMICS_CTL0_CAM */ #define DEMOSAIC_DYNAMICS_CTL0_CAM_COUNT (1U) /*! @name DYNAMICS_CTL2_CAM - Camera 0 Demosaic Dynamics Control 2 Register */ /*! @{ */ #define DEMOSAIC_DYNAMICS_CTL2_CAM_MAX_IMPACT_MASK (0xFFFFU) #define DEMOSAIC_DYNAMICS_CTL2_CAM_MAX_IMPACT_SHIFT (0U) #define DEMOSAIC_DYNAMICS_CTL2_CAM_MAX_IMPACT(x) (((uint32_t)(((uint32_t)(x)) << DEMOSAIC_DYNAMICS_CTL2_CAM_MAX_IMPACT_SHIFT)) & DEMOSAIC_DYNAMICS_CTL2_CAM_MAX_IMPACT_MASK) /*! @} */ /* The count of DEMOSAIC_DYNAMICS_CTL2_CAM */ #define DEMOSAIC_DYNAMICS_CTL2_CAM_COUNT (1U) /*! * @} */ /* end of group DEMOSAIC_Register_Masks */ /* DEMOSAIC - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__DEMOSAIC base address */ #define CAMERA__ISP__DEMOSAIC_BASE (0x4AE01180u) /** Peripheral CAMERA__ISP__DEMOSAIC base pointer */ #define CAMERA__ISP__DEMOSAIC ((DEMOSAIC_Type *)CAMERA__ISP__DEMOSAIC_BASE) /** Array initializer of DEMOSAIC peripheral base addresses */ #define DEMOSAIC_BASE_ADDRS { CAMERA__ISP__DEMOSAIC_BASE } /** Array initializer of DEMOSAIC peripheral base pointers */ #define DEMOSAIC_BASE_PTRS { CAMERA__ISP__DEMOSAIC } /*! * @} */ /* end of group DEMOSAIC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DF_Peripheral_Access_Layer DF Peripheral Access Layer * @{ */ /** DF - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x14 */ __IO uint32_t CTRL_CAM; /**< Camera 0 DF Control Register, array offset: 0x0, array step: 0x14 */ __IO uint32_t TH_SCALE_CAM; /**< Camera 0 DF Blending Scale Register, array offset: 0x4, array step: 0x14 */ __IO uint32_t BLEND_SHIFT_CAM; /**< Camera 0 DF Blending Shift Register, array offset: 0x8, array step: 0x14 */ __IO uint32_t BLEND_TH0_CAM; /**< Camera 0 DF Blend Threshold 0 Register, array offset: 0xC, array step: 0x14 */ __I uint32_t EDGECNT_CAM; /**< Camera 0 DF Edge Count Register, array offset: 0x10, array step: 0x14 */ } NEO_PIPE2_DF_CONF[1]; } DF_Type; /* ---------------------------------------------------------------------------- -- DF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DF_Register_Masks DF Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 DF Control Register */ /*! @{ */ #define DF_CTRL_CAM_DEBUG_MASK (0x700U) #define DF_CTRL_CAM_DEBUG_SHIFT (8U) /*! DEBUG - Debug / Tuning view * 0b000..off * 0b001..filtered+texture * 0b010..filtered+white * 0b011..horizontal filtered + white * 0b100..vertical filtered + white * 0b101..diagonal1 filtered + white * 0b110..diagonal2 filtered + white */ #define DF_CTRL_CAM_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DF_CTRL_CAM_DEBUG_SHIFT)) & DF_CTRL_CAM_DEBUG_MASK) #define DF_CTRL_CAM_ENABLE_MASK (0x80000000U) #define DF_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..off * 0b1..on */ #define DF_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DF_CTRL_CAM_ENABLE_SHIFT)) & DF_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of DF_CTRL_CAM */ #define DF_CTRL_CAM_COUNT (1U) /*! @name TH_SCALE_CAM - Camera 0 DF Blending Scale Register */ /*! @{ */ #define DF_TH_SCALE_CAM_SCALE_MASK (0xFFFFFU) #define DF_TH_SCALE_CAM_SCALE_SHIFT (0U) #define DF_TH_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << DF_TH_SCALE_CAM_SCALE_SHIFT)) & DF_TH_SCALE_CAM_SCALE_MASK) /*! @} */ /* The count of DF_TH_SCALE_CAM */ #define DF_TH_SCALE_CAM_COUNT (1U) /*! @name BLEND_SHIFT_CAM - Camera 0 DF Blending Shift Register */ /*! @{ */ #define DF_BLEND_SHIFT_CAM_SHIFT_MASK (0x3FU) #define DF_BLEND_SHIFT_CAM_SHIFT_SHIFT (0U) #define DF_BLEND_SHIFT_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << DF_BLEND_SHIFT_CAM_SHIFT_SHIFT)) & DF_BLEND_SHIFT_CAM_SHIFT_MASK) /*! @} */ /* The count of DF_BLEND_SHIFT_CAM */ #define DF_BLEND_SHIFT_CAM_COUNT (1U) /*! @name BLEND_TH0_CAM - Camera 0 DF Blend Threshold 0 Register */ /*! @{ */ #define DF_BLEND_TH0_CAM_TH_MASK (0xFFFFFU) #define DF_BLEND_TH0_CAM_TH_SHIFT (0U) #define DF_BLEND_TH0_CAM_TH(x) (((uint32_t)(((uint32_t)(x)) << DF_BLEND_TH0_CAM_TH_SHIFT)) & DF_BLEND_TH0_CAM_TH_MASK) /*! @} */ /* The count of DF_BLEND_TH0_CAM */ #define DF_BLEND_TH0_CAM_COUNT (1U) /*! @name EDGECNT_CAM - Camera 0 DF Edge Count Register */ /*! @{ */ #define DF_EDGECNT_CAM_EDGE_PIXELS_MASK (0xFFFFFFU) #define DF_EDGECNT_CAM_EDGE_PIXELS_SHIFT (0U) #define DF_EDGECNT_CAM_EDGE_PIXELS(x) (((uint32_t)(((uint32_t)(x)) << DF_EDGECNT_CAM_EDGE_PIXELS_SHIFT)) & DF_EDGECNT_CAM_EDGE_PIXELS_MASK) /*! @} */ /* The count of DF_EDGECNT_CAM */ #define DF_EDGECNT_CAM_COUNT (1U) /*! * @} */ /* end of group DF_Register_Masks */ /* DF - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__DF base address */ #define CAMERA__ISP__DF_BASE (0x4AE01440u) /** Peripheral CAMERA__ISP__DF base pointer */ #define CAMERA__ISP__DF ((DF_Type *)CAMERA__ISP__DF_BASE) /** Array initializer of DF peripheral base addresses */ #define DF_BASE_ADDRS { CAMERA__ISP__DF_BASE } /** Array initializer of DF peripheral base pointers */ #define DF_BASE_PTRS { CAMERA__ISP__DF } /*! * @} */ /* end of group DF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DISPLAY_BLK_CTRL_DISPLAYMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_BLK_CTRL_DISPLAYMIX_Peripheral_Access_Layer DISPLAY_BLK_CTRL_DISPLAYMIX Peripheral Access Layer * @{ */ /** DISPLAY_BLK_CTRL_DISPLAYMIX - Register Layout Typedef */ typedef struct { __IO uint32_t DISPLAY_ENGINES_CLOCK_CONTROL; /**< Display engines clock control, offset: 0x0 */ __IO uint32_t PIXEL_INTERLEAVER_CONTROL; /**< Pixel interleaver control, offset: 0x4 */ __IO uint32_t PIXEL_LINK_CTRL; /**< Pixel Link Control, offset: 0x8 */ uint8_t RESERVED_0[12]; __IO uint32_t AXCACHE_CONTROL; /**< AxCache control, offset: 0x18 */ __IO uint32_t QOS_SETTING; /**< QoS setting, offset: 0x1C */ __IO uint32_t DISPLAYENGINE_PLANE_ASSOCIATION; /**< Display Engine Plane Association, offset: 0x20 */ } DISPLAY_BLK_CTRL_DISPLAYMIX_Type; /* ---------------------------------------------------------------------------- -- DISPLAY_BLK_CTRL_DISPLAYMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_BLK_CTRL_DISPLAYMIX_Register_Masks DISPLAY_BLK_CTRL_DISPLAYMIX Register Masks * @{ */ /*! @name DISPLAY_ENGINES_CLOCK_CONTROL - Display engines clock control */ /*! @{ */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK0_SEL_MASK (0x3U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK0_SEL_SHIFT (0U) /*! DSIP_CLK0_SEL - Select the clock feeding the display engine 0 * 0b11..Reserved * 0b10..LVDS PLL Div/7 clock * 0b01..DSI PLL Div clock * 0b00..CCM.video_pll_clk */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK0_SEL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK0_SEL_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK0_SEL_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK1_SEL_MASK (0xCU) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK1_SEL_SHIFT (2U) /*! DSIP_CLK1_SEL - Select the clock feeding the display engine 1 * 0b00..CCM.video_pll_clk * 0b01..DSI PLL Div clock * 0b10..LVDS PLL Div/7 clock * 0b11..Reserved */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK1_SEL_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAY_ENGINES_CLOCK_CONTROL_DSIP_CLK1_SEL_MASK) /*! @} */ /*! @name PIXEL_INTERLEAVER_CONTROL - Pixel interleaver control */ /*! @{ */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Mode_MASK (0x1U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Mode_SHIFT (0U) /*! Mode - Select the pixel interleaver mode * 0b0..Pixel interleaver is in bypass mode. * 0b1..Pixel interleaver is in split mode #2. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Mode_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Mode_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Disp_in_sel_MASK (0x2U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Disp_in_sel_SHIFT (1U) /*! Disp_in_sel - Select the input stream when mode is set in split mode #2 * 0b0..Display input stream 0 is interleaved. * 0b1..Display input stream 1 is interleaved. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Disp_in_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Disp_in_sel_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_INTERLEAVER_CONTROL_Disp_in_sel_MASK) /*! @} */ /*! @name PIXEL_LINK_CTRL - Pixel Link Control */ /*! @{ */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_enable_MASK (0x1U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_enable_SHIFT (0U) /*! PL0_enable - Start Pixel Link 0 * 0b1..Start Pixel Link 0 * 0b0..Do not start Pixel Link 0 */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_enable_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_enable_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_valid_MASK (0x2U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_valid_SHIFT (1U) /*! PL0_valid - Indicates valid pixels / control * 0b0..Not valid pixels/control * 0b1..Valid pixels/control */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_valid(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_valid_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL0_valid_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_enable_MASK (0x10U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_enable_SHIFT (4U) /*! PL1_enable - Start Pixel Link1 * 0b0..Do not start Pixel Link 1 * 0b1..Start Pixel Link 1 */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_enable_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_enable_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_valid_MASK (0x20U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_valid_SHIFT (5U) /*! PL1_valid - Indicates valid pixels / control * 0b1..Valid pixels/control * 0b0..Not valid pixels/control */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_valid(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_valid_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_PIXEL_LINK_CTRL_PL1_valid_MASK) /*! @} */ /*! @name AXCACHE_CONTROL - AxCache control */ /*! @{ */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_ArCache_MASK (0xFU) #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_ArCache_SHIFT (0U) /*! ArCache - Set the AXI ArCache signal for all AXI read master ports of the Display Controller except for the command sequencer one */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_ArCache(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_ArCache_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_ArCache_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_AwCache_MASK (0xF00U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_AwCache_SHIFT (8U) /*! AwCache - Set the AXI AwCache signal for the AXI write master port (blitter output) of the * Display Controller except for the command sequencer one */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_AwCache(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_AwCache_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_AwCache_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_ArCache_MASK (0xF0000U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_ArCache_SHIFT (16U) /*! CmdSeq_ArCache - Set the AXI ArCache signal for the 32-bit AXI read master ports (command sequencer) of the Display Controller */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_ArCache(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_ArCache_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_ArCache_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_AwCache_MASK (0xF00000U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_AwCache_SHIFT (20U) /*! CmdSeq_AwCache - Set the AXI AwCache signal for the 32-bit AXI write master parts (command sequencer) of the Display Controller */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_AwCache(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_AwCache_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_AXCACHE_CONTROL_CmdSeq_AwCache_MASK) /*! @} */ /*! @name QOS_SETTING - QoS setting */ /*! @{ */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_ArQoS_MASK (0x7U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_ArQoS_SHIFT (0U) /*! Display_ArQoS - Default priority level of the AXI read master ports of the Display controller when the Display FIFO panic is not active */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_ArQoS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_ArQoS_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_ArQoS_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_Panic_QoS_MASK (0x70U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_Panic_QoS_SHIFT (4U) /*! Display_Panic_QoS - Priority level when the Display FIFO panic is active */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_Panic_QoS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_Panic_QoS_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Display_Panic_QoS_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Blitter_AxQoS_MASK (0x700U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Blitter_AxQoS_SHIFT (8U) /*! Blitter_AxQoS - Defines the priority level of the AXI read and write master port of the Blitter * fetch units when the Display FIFO panic is not active */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Blitter_AxQoS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Blitter_AxQoS_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_Blitter_AxQoS_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_CmdSeq_QoS_MASK (0x70000U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_CmdSeq_QoS_SHIFT (16U) /*! CmdSeq_QoS - Defines the priority level of the AXI read and write master port of the command * sequencer when the Display FIFO panic is not active */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_CmdSeq_QoS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_CmdSeq_QoS_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_QOS_SETTING_CmdSeq_QoS_MASK) /*! @} */ /*! @name DISPLAYENGINE_PLANE_ASSOCIATION - Display Engine Plane Association */ /*! @{ */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_0_MASK (0x1U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_0_SHIFT (0U) /*! FracPlane_0 - FetchLayer#0 * 0b1..Fetch unit is associated with Display Engine 1. * 0b0..Fetch unit is associated with Display Engine 0. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_0_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_0_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_1_MASK (0x4U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_1_SHIFT (2U) /*! FracPlane_1 - FetchLayer#1 * 0b1..Fetch unit is associated with Display Engine 1. * 0b0..Fetch unit is associated with Display Engine 0. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_1_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_FracPlane_1_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_IntPlane_0_MASK (0x40U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_IntPlane_0_SHIFT (6U) /*! IntPlane_0 - FetchYUV#3 * 0b1..Fetch unit is associated with Display Engine 1. * 0b0..Fetch unit is associated with Display Engine 0. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_IntPlane_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_IntPlane_0_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_IntPlane_0_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_0_MASK (0x100U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_0_SHIFT (8U) /*! VideoPlane_0 - FetchYUV#0 + FetchEco#0 * 0b1..Fetch unit is associated with Display Engine 1. * 0b0..Fetch unit is associated with Display Engine 0. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_0_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_0_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_1_MASK (0x400U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_1_SHIFT (10U) /*! VideoPlane_1 - FetchYUV#1 + FetchEco#1 * 0b0..Fetch unit is associated with Display Engine 0. * 0b1..Fetch unit is associated with Display Engine 1. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_1_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_1_MASK) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_2_MASK (0x1000U) #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_2_SHIFT (12U) /*! VideoPlane_2 - FetchYUV#2 + FetchEco#2 * 0b1..Fetch unit is associated with Display Engine 1. * 0b0..Fetch unit is associated with Display Engine 0. */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_2_SHIFT)) & DISPLAY_BLK_CTRL_DISPLAYMIX_DISPLAYENGINE_PLANE_ASSOCIATION_VideoPlane_2_MASK) /*! @} */ /*! * @} */ /* end of group DISPLAY_BLK_CTRL_DISPLAYMIX_Register_Masks */ /* DISPLAY_BLK_CTRL_DISPLAYMIX - Peripheral instance base addresses */ /** Peripheral DISPLAY__BLK_CTRL_DISPLAYMIX base address */ #define DISPLAY__BLK_CTRL_DISPLAYMIX_BASE (0x4B010000u) /** Peripheral DISPLAY__BLK_CTRL_DISPLAYMIX base pointer */ #define DISPLAY__BLK_CTRL_DISPLAYMIX ((DISPLAY_BLK_CTRL_DISPLAYMIX_Type *)DISPLAY__BLK_CTRL_DISPLAYMIX_BASE) /** Array initializer of DISPLAY_BLK_CTRL_DISPLAYMIX peripheral base addresses */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_BASE_ADDRS { DISPLAY__BLK_CTRL_DISPLAYMIX_BASE } /** Array initializer of DISPLAY_BLK_CTRL_DISPLAYMIX peripheral base pointers */ #define DISPLAY_BLK_CTRL_DISPLAYMIX_BASE_PTRS { DISPLAY__BLK_CTRL_DISPLAYMIX } /*! * @} */ /* end of group DISPLAY_BLK_CTRL_DISPLAYMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DISPLAY_OCRAM_MECC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_OCRAM_MECC_Peripheral_Access_Layer DISPLAY_OCRAM_MECC Peripheral Access Layer * @{ */ /** DISPLAY_OCRAM_MECC - Register Layout Typedef */ typedef struct { __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ __IO uint32_t RAMIAS; /**< RAM Initialization Address Start, offset: 0x4 */ __IO uint32_t RAMIAE; /**< RAM Initialization Address End, offset: 0x8 */ __IO uint32_t RAMSR; /**< RAM Status, offset: 0xC */ __I uint32_t RAMMEMA; /**< RAM ECC Address, offset: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t RAMSYSA; /**< RAM System Address, offset: 0x18 */ __IO uint32_t RAMECCNT; /**< RAM Correctable Error Count, offset: 0x1C */ __IO uint32_t RAMEID0; /**< RAM Error Injection Data 0, offset: 0x20 */ __IO uint32_t RAMEID1; /**< RAM Error Injection Data 1, offset: 0x24 */ __IO uint32_t RAMEIDC; /**< RAM Error Injection Data Control, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t RAMEIA; /**< RAM Error Injection Base Address, offset: 0x30 */ __IO uint32_t RAMEIAM; /**< RAM Error Injection Address Mask, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t RAMMAXA; /**< RAM Maximum-Value Address, offset: 0x40 */ uint8_t RESERVED_3[60]; __IO uint32_t RAMCR2; /**< RAM Control 2, offset: 0x80 */ } DISPLAY_OCRAM_MECC_Type; /* ---------------------------------------------------------------------------- -- DISPLAY_OCRAM_MECC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_OCRAM_MECC_Register_Masks DISPLAY_OCRAM_MECC Register Masks * @{ */ /*! @name RAMCR - RAM Control */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMCR_INIT_MASK (0x1U) #define DISPLAY_OCRAM_MECC_RAMCR_INIT_SHIFT (0U) /*! INIT - Initialization Request * 0b0..Not requested * 0b1..Requested */ #define DISPLAY_OCRAM_MECC_RAMCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMCR_INIT_SHIFT)) & DISPLAY_OCRAM_MECC_RAMCR_INIT_MASK) #define DISPLAY_OCRAM_MECC_RAMCR_IWS_MASK (0x6U) #define DISPLAY_OCRAM_MECC_RAMCR_IWS_SHIFT (1U) /*! IWS - Initialization Wait States * 0b00..Zero * 0b01..One * 0b10..Two * 0b11..Three */ #define DISPLAY_OCRAM_MECC_RAMCR_IWS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMCR_IWS_SHIFT)) & DISPLAY_OCRAM_MECC_RAMCR_IWS_MASK) #define DISPLAY_OCRAM_MECC_RAMCR_INIT_SYSA_MASK (0x100U) #define DISPLAY_OCRAM_MECC_RAMCR_INIT_SYSA_SHIFT (8U) /*! INIT_SYSA - Initialize With System Address * 0b0..Local * 0b1..System */ #define DISPLAY_OCRAM_MECC_RAMCR_INIT_SYSA(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMCR_INIT_SYSA_SHIFT)) & DISPLAY_OCRAM_MECC_RAMCR_INIT_SYSA_MASK) /*! @} */ /*! @name RAMIAS - RAM Initialization Address Start */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMIAS_IAS_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMIAS_IAS_SHIFT (0U) /*! IAS - Initialization Address Start */ #define DISPLAY_OCRAM_MECC_RAMIAS_IAS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMIAS_IAS_SHIFT)) & DISPLAY_OCRAM_MECC_RAMIAS_IAS_MASK) /*! @} */ /*! @name RAMIAE - RAM Initialization Address End */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMIAE_IAE_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMIAE_IAE_SHIFT (0U) /*! IAE - Initialization Address End */ #define DISPLAY_OCRAM_MECC_RAMIAE_IAE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMIAE_IAE_SHIFT)) & DISPLAY_OCRAM_MECC_RAMIAE_IAE_MASK) /*! @} */ /*! @name RAMSR - RAM Status */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMSR_IDONE_MASK (0x1U) #define DISPLAY_OCRAM_MECC_RAMSR_IDONE_SHIFT (0U) /*! IDONE - Initialization Done * 0b0..An initialization was not requested, is in progress, or did not complete * 0b1..An initialization completed successfully */ #define DISPLAY_OCRAM_MECC_RAMSR_IDONE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_IDONE_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_IDONE_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_BUSERR_MASK (0x2U) #define DISPLAY_OCRAM_MECC_RAMSR_BUSERR_SHIFT (1U) /*! BUSERR - Bus Error * 0b0..No error occurred since the last time this field was cleared * 0b1..An error occurred */ #define DISPLAY_OCRAM_MECC_RAMSR_BUSERR(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_BUSERR_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_BUSERR_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_IPEND_MASK (0x4U) #define DISPLAY_OCRAM_MECC_RAMSR_IPEND_SHIFT (2U) /*! IPEND - Initialization Pending * 0b0..Not in progress * 0b1..In progress */ #define DISPLAY_OCRAM_MECC_RAMSR_IPEND(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_IPEND_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_IPEND_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_AVALID_MASK (0x8U) #define DISPLAY_OCRAM_MECC_RAMSR_AVALID_SHIFT (3U) /*! AVALID - Addresses Valid * 0b0..Addresses do not correspond to an event * 0b1..Addresses correspond to an event */ #define DISPLAY_OCRAM_MECC_RAMSR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_AVALID_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_AVALID_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_AERR_MASK (0x20U) #define DISPLAY_OCRAM_MECC_RAMSR_AERR_SHIFT (5U) /*! AERR - ECC Address Error * 0b0..No error occurred * 0b1..An error occurred */ #define DISPLAY_OCRAM_MECC_RAMSR_AERR(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_AERR_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_AERR_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_MLTERR_MASK (0x40U) #define DISPLAY_OCRAM_MECC_RAMSR_MLTERR_SHIFT (6U) /*! MLTERR - ECC Multi-Bit Error * 0b0..No error occurred * 0b1..An error occurred */ #define DISPLAY_OCRAM_MECC_RAMSR_MLTERR(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_MLTERR_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_MLTERR_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_SGLERR_MASK (0x80U) #define DISPLAY_OCRAM_MECC_RAMSR_SGLERR_SHIFT (7U) /*! SGLERR - ECC Single-Bit Error * 0b0..No error occurred * 0b1..An error occurred */ #define DISPLAY_OCRAM_MECC_RAMSR_SGLERR(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_SGLERR_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_SGLERR_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_SYND_MASK (0xFF00U) #define DISPLAY_OCRAM_MECC_RAMSR_SYND_SHIFT (8U) /*! SYND - ECC Syndrome Value */ #define DISPLAY_OCRAM_MECC_RAMSR_SYND(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_SYND_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_SYND_MASK) #define DISPLAY_OCRAM_MECC_RAMSR_EINFO_MASK (0xFF0000U) #define DISPLAY_OCRAM_MECC_RAMSR_EINFO_SHIFT (16U) /*! EINFO - Event Information */ #define DISPLAY_OCRAM_MECC_RAMSR_EINFO(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSR_EINFO_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSR_EINFO_MASK) /*! @} */ /*! @name RAMMEMA - RAM ECC Address */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMMEMA_MEMA_MASK (0x1FFFFU) #define DISPLAY_OCRAM_MECC_RAMMEMA_MEMA_SHIFT (0U) /*! MEMA - RAM Bank Address */ #define DISPLAY_OCRAM_MECC_RAMMEMA_MEMA(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMMEMA_MEMA_SHIFT)) & DISPLAY_OCRAM_MECC_RAMMEMA_MEMA_MASK) #define DISPLAY_OCRAM_MECC_RAMMEMA_BANK_MASK (0x1F00000U) #define DISPLAY_OCRAM_MECC_RAMMEMA_BANK_SHIFT (20U) /*! BANK - RAM Bank ID */ #define DISPLAY_OCRAM_MECC_RAMMEMA_BANK(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMMEMA_BANK_SHIFT)) & DISPLAY_OCRAM_MECC_RAMMEMA_BANK_MASK) /*! @} */ /*! @name RAMSYSA - RAM System Address */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMSYSA_SYSA_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMSYSA_SYSA_SHIFT (0U) /*! SYSA - System Address */ #define DISPLAY_OCRAM_MECC_RAMSYSA_SYSA(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMSYSA_SYSA_SHIFT)) & DISPLAY_OCRAM_MECC_RAMSYSA_SYSA_MASK) /*! @} */ /*! @name RAMECCNT - RAM Correctable Error Count */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMECCNT_ECCNT_MASK (0xFFU) #define DISPLAY_OCRAM_MECC_RAMECCNT_ECCNT_SHIFT (0U) /*! ECCNT - ECC Correctable Error Count */ #define DISPLAY_OCRAM_MECC_RAMECCNT_ECCNT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMECCNT_ECCNT_SHIFT)) & DISPLAY_OCRAM_MECC_RAMECCNT_ECCNT_MASK) /*! @} */ /*! @name RAMEID0 - RAM Error Injection Data 0 */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMEID0_EID_W0_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMEID0_EID_W0_SHIFT (0U) /*! EID_W0 - Error Injection Data Word 0 */ #define DISPLAY_OCRAM_MECC_RAMEID0_EID_W0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEID0_EID_W0_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEID0_EID_W0_MASK) /*! @} */ /*! @name RAMEID1 - RAM Error Injection Data 1 */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMEID1_EID_W1_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMEID1_EID_W1_SHIFT (0U) /*! EID_W1 - Error Injection Data Word 1 */ #define DISPLAY_OCRAM_MECC_RAMEID1_EID_W1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEID1_EID_W1_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEID1_EID_W1_MASK) /*! @} */ /*! @name RAMEIDC - RAM Error Injection Data Control */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMEIDC_EID_CKB_MASK (0xFFU) #define DISPLAY_OCRAM_MECC_RAMEIDC_EID_CKB_SHIFT (0U) /*! EID_CKB - Error Injection Data Checkbits */ #define DISPLAY_OCRAM_MECC_RAMEIDC_EID_CKB(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEIDC_EID_CKB_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEIDC_EID_CKB_MASK) #define DISPLAY_OCRAM_MECC_RAMEIDC_EIP_EN_MASK (0x1000000U) #define DISPLAY_OCRAM_MECC_RAMEIDC_EIP_EN_SHIFT (24U) /*! EIP_EN - Error Injection Into Pipeline Enable * 0b0..No error injected * 0b1..Error injected */ #define DISPLAY_OCRAM_MECC_RAMEIDC_EIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEIDC_EIP_EN_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEIDC_EIP_EN_MASK) #define DISPLAY_OCRAM_MECC_RAMEIDC_EIA_EN_MASK (0x40000000U) #define DISPLAY_OCRAM_MECC_RAMEIDC_EIA_EN_SHIFT (30U) /*! EIA_EN - Error Injection Address Enable * 0b0..Ignore RAMEIA and RAMEIAM * 0b1..Enable RAMEIA and RAMEIAM */ #define DISPLAY_OCRAM_MECC_RAMEIDC_EIA_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEIDC_EIA_EN_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEIDC_EIA_EN_MASK) #define DISPLAY_OCRAM_MECC_RAMEIDC_EID_EN_MASK (0x80000000U) #define DISPLAY_OCRAM_MECC_RAMEIDC_EID_EN_SHIFT (31U) /*! EID_EN - Error Injection Data Enable * 0b0..No injection * 0b1..Local injection */ #define DISPLAY_OCRAM_MECC_RAMEIDC_EID_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEIDC_EID_EN_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEIDC_EID_EN_MASK) /*! @} */ /*! @name RAMEIA - RAM Error Injection Base Address */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMEIA_EIA_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMEIA_EIA_SHIFT (0U) /*! EIA - Error Injection Base Address */ #define DISPLAY_OCRAM_MECC_RAMEIA_EIA(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEIA_EIA_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEIA_EIA_MASK) /*! @} */ /*! @name RAMEIAM - RAM Error Injection Address Mask */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMEIAM_EIAM_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMEIAM_EIAM_SHIFT (0U) /*! EIAM - Error Injection Address Mask */ #define DISPLAY_OCRAM_MECC_RAMEIAM_EIAM(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMEIAM_EIAM_SHIFT)) & DISPLAY_OCRAM_MECC_RAMEIAM_EIAM_MASK) /*! @} */ /*! @name RAMMAXA - RAM Maximum-Value Address */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMMAXA_MAXA_MASK (0xFFFFFFFFU) #define DISPLAY_OCRAM_MECC_RAMMAXA_MAXA_SHIFT (0U) /*! MAXA - Maximum Address */ #define DISPLAY_OCRAM_MECC_RAMMAXA_MAXA(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMMAXA_MAXA_SHIFT)) & DISPLAY_OCRAM_MECC_RAMMAXA_MAXA_MASK) /*! @} */ /*! @name RAMCR2 - RAM Control 2 */ /*! @{ */ #define DISPLAY_OCRAM_MECC_RAMCR2_WBUF_MASK (0x6U) #define DISPLAY_OCRAM_MECC_RAMCR2_WBUF_SHIFT (1U) /*! WBUF - Write Buffer Control * 0b00..Disable write buffer for all write transactions * 0b01..Enable write buffer for write transactions that come with bufferable bus attribute * 0b10..Enable write buffer for write transactions that are not exclusive writes * 0b11..Reserved */ #define DISPLAY_OCRAM_MECC_RAMCR2_WBUF(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_OCRAM_MECC_RAMCR2_WBUF_SHIFT)) & DISPLAY_OCRAM_MECC_RAMCR2_WBUF_MASK) /*! @} */ /*! * @} */ /* end of group DISPLAY_OCRAM_MECC_Register_Masks */ /* DISPLAY_OCRAM_MECC - Peripheral instance base addresses */ /** Peripheral DISPLAY__OCRAM_MECC base address */ #define DISPLAY__OCRAM_MECC_BASE (0x4B0F0000u) /** Peripheral DISPLAY__OCRAM_MECC base pointer */ #define DISPLAY__OCRAM_MECC ((DISPLAY_OCRAM_MECC_Type *)DISPLAY__OCRAM_MECC_BASE) /** Array initializer of DISPLAY_OCRAM_MECC peripheral base addresses */ #define DISPLAY_OCRAM_MECC_BASE_ADDRS { DISPLAY__OCRAM_MECC_BASE } /** Array initializer of DISPLAY_OCRAM_MECC peripheral base pointers */ #define DISPLAY_OCRAM_MECC_BASE_PTRS { DISPLAY__OCRAM_MECC } /*! * @} */ /* end of group DISPLAY_OCRAM_MECC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DISPLAY_PIXEL_INTERLEAVER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_PIXEL_INTERLEAVER_Peripheral_Access_Layer DISPLAY_PIXEL_INTERLEAVER Peripheral Access Layer * @{ */ /** DISPLAY_PIXEL_INTERLEAVER - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10000 */ __IO uint32_t CTRL; /**< DISP_IN0 Control Register..DISP_IN1 Control Register, array offset: 0x0, array step: 0x10000 */ uint8_t RESERVED_0[28]; __IO uint32_t SWRST; /**< DISP_IN0 Software Reset Control Register..DISP_IN1 Software Reset Control Register, array offset: 0x20, array step: 0x10000 */ uint8_t RESERVED_1[12]; __IO uint32_t IE; /**< DISP_IN0 Interrupt Enable Register..DISP_IN1 Interrupt Enable Register, array offset: 0x30, array step: 0x10000 */ uint8_t RESERVED_2[12]; __IO uint32_t IS; /**< DISP_IN0 Interrupt Status Register..DISP_IN1 Interrupt Status Register, array offset: 0x40, array step: 0x10000 */ uint8_t RESERVED_3[12]; __IO uint32_t ICTRL; /**< DISP_IN0 Interleaving Control Register..DISP_IN1 Interleaving Control Register, array offset: 0x50, array step: 0x10000 */ uint8_t RESERVED_4[65452]; } DISPLAY[2]; } DISPLAY_PIXEL_INTERLEAVER_Type; /* ---------------------------------------------------------------------------- -- DISPLAY_PIXEL_INTERLEAVER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_PIXEL_INTERLEAVER_Register_Masks DISPLAY_PIXEL_INTERLEAVER Register Masks * @{ */ /*! @name CTRL - DISP_IN0 Control Register..DISP_IN1 Control Register */ /*! @{ */ #define DISPLAY_PIXEL_INTERLEAVER_CTRL_HSYNC_POLARITY_MASK (0x200U) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_HSYNC_POLARITY_SHIFT (9U) /*! HSYNC_POLARITY - Hsync Polarity * 0b0..Active high * 0b1..Active low */ #define DISPLAY_PIXEL_INTERLEAVER_CTRL_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_CTRL_HSYNC_POLARITY_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_CTRL_HSYNC_POLARITY_MASK) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_VSYNC_POLARITY_MASK (0x400U) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_VSYNC_POLARITY_SHIFT (10U) /*! VSYNC_POLARITY - Vsync Polarity * 0b0..Active high * 0b1..Active low */ #define DISPLAY_PIXEL_INTERLEAVER_CTRL_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_CTRL_VSYNC_POLARITY_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_CTRL_VSYNC_POLARITY_MASK) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_DE_POLARITY_MASK (0x800U) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_DE_POLARITY_SHIFT (11U) /*! DE_POLARITY - DE Polarity * 0b0..Active high * 0b1..Active low */ #define DISPLAY_PIXEL_INTERLEAVER_CTRL_DE_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_CTRL_DE_POLARITY_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_CTRL_DE_POLARITY_MASK) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_PIXEL_FORMAT_MASK (0x1000U) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_PIXEL_FORMAT_SHIFT (12U) /*! PIXEL_FORMAT - Pixel Format * 0b0..RGB format * 0b1..YUV format */ #define DISPLAY_PIXEL_INTERLEAVER_CTRL_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_CTRL_PIXEL_FORMAT_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_CTRL_PIXEL_FORMAT_MASK) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_YUV_CONV_MASK (0x2000U) #define DISPLAY_PIXEL_INTERLEAVER_CTRL_YUV_CONV_SHIFT (13U) /*! YUV_CONV - YUV444 to YUV422 Conversion Enable * 0b0..Disable * 0b1..Enable */ #define DISPLAY_PIXEL_INTERLEAVER_CTRL_YUV_CONV(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_CTRL_YUV_CONV_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_CTRL_YUV_CONV_MASK) /*! @} */ /* The count of DISPLAY_PIXEL_INTERLEAVER_CTRL */ #define DISPLAY_PIXEL_INTERLEAVER_CTRL_COUNT (2U) /*! @name SWRST - DISP_IN0 Software Reset Control Register..DISP_IN1 Software Reset Control Register */ /*! @{ */ #define DISPLAY_PIXEL_INTERLEAVER_SWRST_SW_RST_MASK (0x2U) #define DISPLAY_PIXEL_INTERLEAVER_SWRST_SW_RST_SHIFT (1U) /*! SW_RST - Software Reset * 0b0..No action * 0b1..Software reset is available */ #define DISPLAY_PIXEL_INTERLEAVER_SWRST_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_SWRST_SW_RST_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_SWRST_SW_RST_MASK) /*! @} */ /* The count of DISPLAY_PIXEL_INTERLEAVER_SWRST */ #define DISPLAY_PIXEL_INTERLEAVER_SWRST_COUNT (2U) /*! @name IE - DISP_IN0 Interrupt Enable Register..DISP_IN1 Interrupt Enable Register */ /*! @{ */ #define DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE0_MASK (0x1U) #define DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE0_SHIFT (0U) /*! FOVF_IE0 - FIFO 0 Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE0_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE0_MASK) #define DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE1_MASK (0x2U) #define DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE1_SHIFT (1U) /*! FOVF_IE1 - FIFO 1 Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE1_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_IE_FOVF_IE1_MASK) /*! @} */ /* The count of DISPLAY_PIXEL_INTERLEAVER_IE */ #define DISPLAY_PIXEL_INTERLEAVER_IE_COUNT (2U) /*! @name IS - DISP_IN0 Interrupt Status Register..DISP_IN1 Interrupt Status Register */ /*! @{ */ #define DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS0_MASK (0x1U) #define DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS0_SHIFT (0U) /*! FOVF_IS0 - FIFO 0 Overflow Interrupt Status * 0b0..Did not occur * 0b1..Occurred */ #define DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS0_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS0_MASK) #define DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS1_MASK (0x2U) #define DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS1_SHIFT (1U) /*! FOVF_IS1 - FIFO 1 Overflow Interrupt Status * 0b0..Did not occur * 0b1..Occurred */ #define DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS1_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_IS_FOVF_IS1_MASK) /*! @} */ /* The count of DISPLAY_PIXEL_INTERLEAVER_IS */ #define DISPLAY_PIXEL_INTERLEAVER_IS_COUNT (2U) /*! @name ICTRL - DISP_IN0 Interleaving Control Register..DISP_IN1 Interleaving Control Register */ /*! @{ */ #define DISPLAY_PIXEL_INTERLEAVER_ICTRL_WIDTH_MASK (0xFFFU) #define DISPLAY_PIXEL_INTERLEAVER_ICTRL_WIDTH_SHIFT (0U) /*! WIDTH - Width Control for Interleaving Operation */ #define DISPLAY_PIXEL_INTERLEAVER_ICTRL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_INTERLEAVER_ICTRL_WIDTH_SHIFT)) & DISPLAY_PIXEL_INTERLEAVER_ICTRL_WIDTH_MASK) /*! @} */ /* The count of DISPLAY_PIXEL_INTERLEAVER_ICTRL */ #define DISPLAY_PIXEL_INTERLEAVER_ICTRL_COUNT (2U) /*! * @} */ /* end of group DISPLAY_PIXEL_INTERLEAVER_Register_Masks */ /* DISPLAY_PIXEL_INTERLEAVER - Peripheral instance base addresses */ /** Peripheral DISPLAY__PIXEL_INTERLEAVER1 base address */ #define DISPLAY__PIXEL_INTERLEAVER1_BASE (0x4B0D0000u) /** Peripheral DISPLAY__PIXEL_INTERLEAVER1 base pointer */ #define DISPLAY__PIXEL_INTERLEAVER1 ((DISPLAY_PIXEL_INTERLEAVER_Type *)DISPLAY__PIXEL_INTERLEAVER1_BASE) /** Array initializer of DISPLAY_PIXEL_INTERLEAVER peripheral base addresses */ #define DISPLAY_PIXEL_INTERLEAVER_BASE_ADDRS { DISPLAY__PIXEL_INTERLEAVER1_BASE } /** Array initializer of DISPLAY_PIXEL_INTERLEAVER peripheral base pointers */ #define DISPLAY_PIXEL_INTERLEAVER_BASE_PTRS { DISPLAY__PIXEL_INTERLEAVER1 } /*! * @} */ /* end of group DISPLAY_PIXEL_INTERLEAVER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DISPLAY_PIXEL_MAPPER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_PIXEL_MAPPER_Peripheral_Access_Layer DISPLAY_PIXEL_MAPPER Peripheral Access Layer * @{ */ /** DISPLAY_PIXEL_MAPPER - Register Layout Typedef */ typedef struct { __IO uint32_t LDB_CTRL; /**< LDB Control Register, offset: 0x0 */ } DISPLAY_PIXEL_MAPPER_Type; /* ---------------------------------------------------------------------------- -- DISPLAY_PIXEL_MAPPER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_PIXEL_MAPPER_Register_Masks DISPLAY_PIXEL_MAPPER Register Masks * @{ */ /*! @name LDB_CTRL - LDB Control Register */ /*! @{ */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ENABLE_MASK (0x1U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ENABLE_SHIFT (0U) /*! CH0_ENABLE - LVDS channel 0 enable * 0b0..Channel disabled * 0b1..Channel enabled */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ENABLE_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ENABLE_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DI_SELECT_MASK (0x2U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DI_SELECT_SHIFT (1U) /*! CH0_DI_SELECT - LVDS channel 0 source select * 0b0..From DI0 * 0b1..From DI1 */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DI_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DI_SELECT_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DI_SELECT_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ENABLE_MASK (0x4U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ENABLE_SHIFT (2U) /*! CH1_ENABLE - LVDS channel 1 enable * 0b0..Channel disabled * 0b1..Channel enabled */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ENABLE_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ENABLE_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DI_SELECT_MASK (0x8U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DI_SELECT_SHIFT (3U) /*! CH1_DI_SELECT - LVDS channel 1 source select * 0b0..From DI0 * 0b1..From DI1 */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DI_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DI_SELECT_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DI_SELECT_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_SPLIT_MODE_MASK (0x10U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_SPLIT_MODE_SHIFT (4U) /*! SPLIT_MODE - Enable split mode * 0b0..Split mode disabled * 0b1..Split mode enabled */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_SPLIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_SPLIT_MODE_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_SPLIT_MODE_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DATA_WIDTH_MASK (0x20U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DATA_WIDTH_SHIFT (5U) /*! CH0_DATA_WIDTH - Data width for LVDS channel 0. * 0b0..Data width is 18 bits wide(LVDS0_D3 is not used) * 0b1..Data width is 24 bits wide */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DATA_WIDTH_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_DATA_WIDTH_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_BIT_MAPPING_MASK (0x40U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_BIT_MAPPING_SHIFT (6U) /*! CH0_BIT_MAPPING - Data mapping for LVDS channel 0. * 0b0..Use SPWG standard. * 0b1..Use JEIDA standard. */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_BIT_MAPPING_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_BIT_MAPPING_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DATA_WIDTH_MASK (0x80U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DATA_WIDTH_SHIFT (7U) /*! CH1_DATA_WIDTH - Data width for LVDS channel 1. * 0b0..Data width is 18 bits wide(LVDS1_D3 is not used) * 0b1..Data width is 24 bits wide */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DATA_WIDTH_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_DATA_WIDTH_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_BIT_MAPPING_MASK (0x100U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_BIT_MAPPING_SHIFT (8U) /*! CH1_BIT_MAPPING - Data mapping for LVDS channel 1. * 0b0..Use SPWG standard. * 0b1..Use JEIDA standard. */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_BIT_MAPPING_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_BIT_MAPPING_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI0_VSYNC_POLARITY_MASK (0x200U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI0_VSYNC_POLARITY_SHIFT (9U) /*! DI0_VSYNC_POLARITY - VSYNC polarity select for DI0 * 0b0..VSYNC is active high * 0b1..VSYNC is active low */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI0_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI0_VSYNC_POLARITY_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI0_VSYNC_POLARITY_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI1_VSYNC_POLARITY_MASK (0x400U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI1_VSYNC_POLARITY_SHIFT (10U) /*! DI1_VSYNC_POLARITY - VSYNC polarity select for DI1 * 0b0..VSYNC is active high * 0b1..VSYNC is active low */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI1_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI1_VSYNC_POLARITY_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_DI1_VSYNC_POLARITY_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ASYNC_FIFO_RESET_MASK (0x800U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ASYNC_FIFO_RESET_SHIFT (11U) /*! CH0_ASYNC_FIFO_RESET - LVDS channel 0 async FIFO software reset * 0b0..No action * 0b1..Software reset */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ASYNC_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ASYNC_FIFO_RESET_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH0_ASYNC_FIFO_RESET_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ASYNC_FIFO_RESET_MASK (0x1000U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ASYNC_FIFO_RESET_SHIFT (12U) /*! CH1_ASYNC_FIFO_RESET - LVDS channel 1 async FIFO software reset * 0b0..No action * 0b1..Software reset */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ASYNC_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ASYNC_FIFO_RESET_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_CH1_ASYNC_FIFO_RESET_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_ENABLE_MASK (0x1000000U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_ENABLE_SHIFT (24U) /*! ASYNC_FIFO_ENABLE - Channel 0 and channel 1 async FIFO enable * 0b0..Disable * 0b1..Enable async FIFO to buffer RGB data */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_ENABLE_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_ENABLE_MASK) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK (0xE000000U) #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_THRESHOLD_SHIFT (25U) /*! ASYNC_FIFO_THRESHOLD - Channel 0 and channel 1 async FIFO enable */ #define DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_THRESHOLD_SHIFT)) & DISPLAY_PIXEL_MAPPER_LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK) /*! @} */ /*! * @} */ /* end of group DISPLAY_PIXEL_MAPPER_Register_Masks */ /* DISPLAY_PIXEL_MAPPER - Peripheral instance base addresses */ /** Peripheral DISPLAY__PIXEL_MAPPER base address */ #define DISPLAY__PIXEL_MAPPER_BASE (0x4B000000u) /** Peripheral DISPLAY__PIXEL_MAPPER base pointer */ #define DISPLAY__PIXEL_MAPPER ((DISPLAY_PIXEL_MAPPER_Type *)DISPLAY__PIXEL_MAPPER_BASE) /** Array initializer of DISPLAY_PIXEL_MAPPER peripheral base addresses */ #define DISPLAY_PIXEL_MAPPER_BASE_ADDRS { DISPLAY__PIXEL_MAPPER_BASE } /** Array initializer of DISPLAY_PIXEL_MAPPER peripheral base pointers */ #define DISPLAY_PIXEL_MAPPER_BASE_PTRS { DISPLAY__PIXEL_MAPPER } /*! * @} */ /* end of group DISPLAY_PIXEL_MAPPER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DISPLAY_SEERIS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_SEERIS_Peripheral_Access_Layer DISPLAY_SEERIS Peripheral Access Layer * @{ */ /** DISPLAY_SEERIS - Register Layout Typedef */ typedef struct { __IO uint32_t COMCTRL_IPIDENTIFIER; /**< IP Identifier for this SEERIS derivate., offset: 0x0 */ uint8_t RESERVED_0[4092]; __O uint32_t IRQ_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1000 */ __I uint32_t IRQ_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1004 */ __IO uint32_t IRQ_INTERRUPTENABLE0; /**< Interrupt Enable register 0., offset: 0x1008 */ __IO uint32_t IRQ_INTERRUPTENABLE1; /**< Interrupt Enable register 1., offset: 0x100C */ __IO uint32_t IRQ_INTERRUPTENABLE2; /**< Interrupt Enable register 2., offset: 0x1010 */ __O uint32_t IRQ_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x1014 */ __O uint32_t IRQ_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x1018 */ __O uint32_t IRQ_INTERRUPTPRESET2; /**< Interrupt Preset register 2, offset: 0x101C */ __O uint32_t IRQ_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x1020 */ __O uint32_t IRQ_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x1024 */ __O uint32_t IRQ_INTERRUPTCLEAR2; /**< Interrupt Clear register 2, offset: 0x1028 */ __I uint32_t IRQ_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x102C */ __I uint32_t IRQ_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x1030 */ __I uint32_t IRQ_INTERRUPTSTATUS2; /**< Interrupt Status register 2, offset: 0x1034 */ uint8_t RESERVED_1[4040]; __O uint32_t DOMAINMASK_MASKLOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2000 */ __I uint32_t DOMAINMASK_MASKLOCKSTATUS; /**< Protection status of this address block., offset: 0x2004 */ __IO uint32_t DOMAINMASK_STORE9_DOMAIN_MASK0; /**< Pixel Engine domain mask 0 for endpoint store9., offset: 0x2008 */ __IO uint32_t DOMAINMASK_EXTDST0_DOMAIN_MASK0; /**< Pixel Engine domain mask 0 for endpoint extdst0., offset: 0x200C */ __IO uint32_t DOMAINMASK_EXTDST4_DOMAIN_MASK0; /**< Pixel Engine domain mask 0 for endpoint extdst4., offset: 0x2010 */ __IO uint32_t DOMAINMASK_EXTDST1_DOMAIN_MASK0; /**< Pixel Engine domain mask 0 for endpoint extdst1., offset: 0x2014 */ __IO uint32_t DOMAINMASK_EXTDST5_DOMAIN_MASK0; /**< Pixel Engine domain mask 0 for endpoint extdst5., offset: 0x2018 */ __IO uint32_t DOMAINMASK_SEERIS_DISPLAY_STATIC; /**< Global settings for SEERIS Display configuration., offset: 0x201C */ __IO uint32_t DOMAINMASK_EXTDST0_STATIC; /**< Static pixel engine configuration for extdst0, offset: 0x2020 */ __IO uint32_t DOMAINMASK_EXTDST4_STATIC; /**< Static pixel engine configuration for extdst4, offset: 0x2024 */ __IO uint32_t DOMAINMASK_EXTDST1_STATIC; /**< Static pixel engine configuration for extdst1, offset: 0x2028 */ __IO uint32_t DOMAINMASK_EXTDST5_STATIC; /**< Static pixel engine configuration for extdst5, offset: 0x202C */ uint8_t RESERVED_2[4048]; __O uint32_t CMDSEQMASK_MASKLOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3000 */ __I uint32_t CMDSEQMASK_MASKLOCKSTATUS; /**< Protection status of this address block., offset: 0x3004 */ __IO uint32_t CMDSEQMASK_CMDSEQ_ACCESS_MASK0; /**< Each bit describes whether register in the corresponding 64kByte address block is allowed to be written from the command sequencer., offset: 0x3008 */ __IO uint32_t CMDSEQMASK_CMDSEQ_ACCESS_MASK1; /**< Each bit describes whether register in the corresponding 64kByte address block is allowed to be written from the command sequencer., offset: 0x300C */ uint8_t RESERVED_3[53232]; __IO uint32_t CMDSEQ_HIF[64]; /**< Command input buffer, array offset: 0x10000, array step: 0x4 */ __O uint32_t CMDSEQ_LOCKUNLOCKHIF; /**< Register to change the protection status of this address block., offset: 0x10100 */ __I uint32_t CMDSEQ_LOCKSTATUSHIF; /**< Protection status of this address block., offset: 0x10104 */ uint8_t RESERVED_4[120]; __O uint32_t CMDSEQ_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x10180 */ __I uint32_t CMDSEQ_LOCKSTATUS; /**< Protection status of this address block., offset: 0x10184 */ __IO uint32_t CMDSEQ_BUFFERADDRESS; /**< Command buffer address register, offset: 0x10188 */ __IO uint32_t CMDSEQ_BUFFERADDRESSMSB; /**< Command buffer address register, offset: 0x1018C */ __IO uint32_t CMDSEQ_BUFFERSIZE; /**< Command buffer size register, offset: 0x10190 */ __IO uint32_t CMDSEQ_WATERMARKCONTROL; /**< Watermark Control register, offset: 0x10194 */ __O uint32_t CMDSEQ_CONTROL; /**< Control register, offset: 0x10198 */ __I uint32_t CMDSEQ_STATUS; /**< Status register, offset: 0x1019C */ __IO uint32_t CMDSEQ_PREFETCHWINDOWSTART; /**< PrefetchWindowStart register, offset: 0x101A0 */ __IO uint32_t CMDSEQ_PREFETCHWINDOWSTARTMSB; /**< PrefetchWindowStart register MSB bits, offset: 0x101A4 */ __IO uint32_t CMDSEQ_PREFETCHWINDOWEND; /**< PrefetchWindowEnd register, offset: 0x101A8 */ __IO uint32_t CMDSEQ_PREFETCHWINDOWENDMSB; /**< PrefetchWindowEnd register MSB bits, offset: 0x101AC */ uint8_t RESERVED_5[3664]; __O uint32_t CMDSEQIRQ_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x11000 */ __I uint32_t CMDSEQIRQ_LOCKSTATUS; /**< Protection status of this address block., offset: 0x11004 */ __IO uint32_t CMDSEQIRQ_INTERRUPTENABLE0; /**< Interrupt Enable register 0., offset: 0x11008 */ __IO uint32_t CMDSEQIRQ_INTERRUPTENABLE1; /**< Interrupt Enable register 1., offset: 0x1100C */ __IO uint32_t CMDSEQIRQ_INTERRUPTENABLE2; /**< Interrupt Enable register 2., offset: 0x11010 */ __O uint32_t CMDSEQIRQ_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x11014 */ __O uint32_t CMDSEQIRQ_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x11018 */ __O uint32_t CMDSEQIRQ_INTERRUPTPRESET2; /**< Interrupt Preset register 2, offset: 0x1101C */ __O uint32_t CMDSEQIRQ_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x11020 */ __O uint32_t CMDSEQIRQ_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x11024 */ __O uint32_t CMDSEQIRQ_INTERRUPTCLEAR2; /**< Interrupt Clear register 2, offset: 0x11028 */ __I uint32_t CMDSEQIRQ_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x1102C */ __I uint32_t CMDSEQIRQ_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x11030 */ __I uint32_t CMDSEQIRQ_INTERRUPTSTATUS2; /**< Interrupt Status register 2, offset: 0x11034 */ uint8_t RESERVED_6[4040]; __IO uint32_t GENERALPURPOSE_GENERALPURPOSE[32]; /**< General purpose config memory, array offset: 0x12000, array step: 0x4 */ uint8_t RESERVED_7[57216]; __IO uint32_t XPC_CONTROL; /**< Global XPC control register, offset: 0x20000 */ __IO uint32_t XPC_TIMER; /**< Timer control register, offset: 0x20004 */ __IO uint32_t XPC_MEASUREMENTTIMECONTROL; /**< Timer divider control register, offset: 0x20008 */ __IO uint32_t XPC_SW_TAG; /**< Tag register, offset: 0x2000C */ __I uint32_t XPC_MEASUREMENTTIME; /**< Measurement time register, offset: 0x20010 */ __I uint32_t XPC_GLOBAL_COUNTER; /**< Global counter register, offset: 0x20014 */ __IO uint32_t XPC_MU00_SWITCH; /**< Measurement unit 00 switch register, offset: 0x20018 */ __I uint32_t XPC_MU00_DATA_COUNTER; /**< Measurement unit 00 data counter register, offset: 0x2001C */ __I uint32_t XPC_MU00_BUSY_COUNTER; /**< Measurement unit 00 busy counter register, offset: 0x20020 */ __I uint32_t XPC_MU00_TRANSFER_COUNTER; /**< Measurement unit 00 transfer counter register, offset: 0x20024 */ __I uint32_t XPC_MU00_ADDRBUSY_COUNTER; /**< Measurement unit 00 address busy counter register, offset: 0x20028 */ __I uint32_t XPC_MU00_LATENCY_COUNTER; /**< Measurement unit 00 latency counter register, offset: 0x2002C */ __IO uint32_t XPC_MU01_SWITCH; /**< Measurement unit 01 switch register, offset: 0x20030 */ __I uint32_t XPC_MU01_DATA_COUNTER; /**< Measurement unit 01 data counter register, offset: 0x20034 */ __I uint32_t XPC_MU01_BUSY_COUNTER; /**< Measurement unit 01 busy counter register, offset: 0x20038 */ __I uint32_t XPC_MU01_TRANSFER_COUNTER; /**< Measurement unit 01 transfer counter register, offset: 0x2003C */ __I uint32_t XPC_MU01_ADDRBUSY_COUNTER; /**< Measurement unit 01 address busy counter register, offset: 0x20040 */ __I uint32_t XPC_MU01_LATENCY_COUNTER; /**< Measurement unit 01 latency counter register, offset: 0x20044 */ __IO uint32_t XPC_MU02_SWITCH; /**< Measurement unit 02 switch register, offset: 0x20048 */ __I uint32_t XPC_MU02_DATA_COUNTER; /**< Measurement unit 02 data counter register, offset: 0x2004C */ __I uint32_t XPC_MU02_BUSY_COUNTER; /**< Measurement unit 02 busy counter register, offset: 0x20050 */ __I uint32_t XPC_MU02_TRANSFER_COUNTER; /**< Measurement unit 02 transfer counter register, offset: 0x20054 */ __I uint32_t XPC_MU02_ADDRBUSY_COUNTER; /**< Measurement unit 02 address busy counter register, offset: 0x20058 */ __I uint32_t XPC_MU02_LATENCY_COUNTER; /**< Measurement unit 02 latency counter register, offset: 0x2005C */ __IO uint32_t XPC_MU03_SWITCH; /**< Measurement unit 03 switch register, offset: 0x20060 */ __I uint32_t XPC_MU03_DATA_COUNTER; /**< Measurement unit 03 data counter register, offset: 0x20064 */ __I uint32_t XPC_MU03_BUSY_COUNTER; /**< Measurement unit 03 busy counter register, offset: 0x20068 */ __I uint32_t XPC_MU03_TRANSFER_COUNTER; /**< Measurement unit 03 transfer counter register, offset: 0x2006C */ __I uint32_t XPC_MU03_ADDRBUSY_COUNTER; /**< Measurement unit 03 address busy counter register, offset: 0x20070 */ __I uint32_t XPC_MU03_LATENCY_COUNTER; /**< Measurement unit 03 latency counter register, offset: 0x20074 */ __IO uint32_t XPC_MU04_SWITCH; /**< Measurement unit 04 switch register, offset: 0x20078 */ __I uint32_t XPC_MU04_DATA_COUNTER; /**< Measurement unit 04 data counter register, offset: 0x2007C */ __I uint32_t XPC_MU04_BUSY_COUNTER; /**< Measurement unit 04 busy counter register, offset: 0x20080 */ __I uint32_t XPC_MU04_TRANSFER_COUNTER; /**< Measurement unit 04 transfer counter register, offset: 0x20084 */ __I uint32_t XPC_MU04_ADDRBUSY_COUNTER; /**< Measurement unit 04 address busy counter register, offset: 0x20088 */ __I uint32_t XPC_MU04_LATENCY_COUNTER; /**< Measurement unit 04 latency counter register, offset: 0x2008C */ uint8_t RESERVED_8[69488]; __O uint32_t BLITIRQ_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x31000 */ __I uint32_t BLITIRQ_LOCKSTATUS; /**< Protection status of this address block., offset: 0x31004 */ __IO uint32_t BLITIRQ_INTERRUPTENABLE0; /**< Interrupt Enable register 0., offset: 0x31008 */ __IO uint32_t BLITIRQ_INTERRUPTENABLE1; /**< Interrupt Enable register 1., offset: 0x3100C */ __IO uint32_t BLITIRQ_INTERRUPTENABLE2; /**< Interrupt Enable register 2., offset: 0x31010 */ __O uint32_t BLITIRQ_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x31014 */ __O uint32_t BLITIRQ_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x31018 */ __O uint32_t BLITIRQ_INTERRUPTPRESET2; /**< Interrupt Preset register 2, offset: 0x3101C */ __O uint32_t BLITIRQ_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x31020 */ __O uint32_t BLITIRQ_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x31024 */ __O uint32_t BLITIRQ_INTERRUPTCLEAR2; /**< Interrupt Clear register 2, offset: 0x31028 */ __I uint32_t BLITIRQ_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x3102C */ __I uint32_t BLITIRQ_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x31030 */ __I uint32_t BLITIRQ_INTERRUPTSTATUS2; /**< Interrupt Status register 2, offset: 0x31034 */ uint8_t RESERVED_9[61384]; __O uint32_t PIXENG_ROP9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x40000 */ __I uint32_t PIXENG_ROP9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x40004 */ __IO uint32_t PIXENG_ROP9_STATICCONTROL; /**< Raster Operation static control register, offset: 0x40008 */ __IO uint32_t PIXENG_ROP9_CONTROL; /**< Raster Operation control register, offset: 0x4000C */ __IO uint32_t PIXENG_ROP9_RASTEROPERATIONINDICES; /**< ROP operation indices, offset: 0x40010 */ __I uint32_t PIXENG_ROP9_PRIMCONTROLWORD; /**< Value of last received primary control word, offset: 0x40014 */ __I uint32_t PIXENG_ROP9_SECCONTROLWORD; /**< Value of last received secondary control word, offset: 0x40018 */ __I uint32_t PIXENG_ROP9_TERTCONTROLWORD; /**< Value of last received tertiary control word, offset: 0x4001C */ uint8_t RESERVED_10[4064]; __O uint32_t PIXENG_ROP9CFG_ROP9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x41000 */ __I uint32_t PIXENG_ROP9CFG_ROP9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x41004 */ __IO uint32_t PIXENG_ROP9CFG_ROP9_DYNAMIC; /**< Dynamic pixel engine configuration for rop9, offset: 0x41008 */ __I uint32_t PIXENG_ROP9CFG_ROP9_STATUS; /**< Status information for pixel engine configuration of rop9, offset: 0x4100C */ uint8_t RESERVED_11[61424]; __O uint32_t PIXENG_CLUT9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x50000 */ __I uint32_t PIXENG_CLUT9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x50004 */ __IO uint32_t PIXENG_CLUT9_STATICCONTROL; /**< CLUT static control register, offset: 0x50008 */ __IO uint32_t PIXENG_CLUT9_UNSHADOWEDCONTROL; /**< CLUT unshadowed control register, offset: 0x5000C */ __IO uint32_t PIXENG_CLUT9_CONTROL; /**< CLUT control register, offset: 0x50010 */ __IO uint32_t PIXENG_CLUT9_STATUS; /**< CLUT status register, offset: 0x50014 */ __I uint32_t PIXENG_CLUT9_LASTCONTROLWORD; /**< Value of last received control word, for debugging, offset: 0x50018 */ uint8_t RESERVED_12[996]; __IO uint32_t PIXENG_CLUT9_LUT[256]; /**< Look Up Table, array offset: 0x50400, array step: 0x4 */ uint8_t RESERVED_13[2048]; __O uint32_t PIXENG_CLUT9CFG_CLUT9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x51000 */ __I uint32_t PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x51004 */ __IO uint32_t PIXENG_CLUT9CFG_CLUT9_DYNAMIC; /**< Dynamic pixel engine configuration for clut9, offset: 0x51008 */ __I uint32_t PIXENG_CLUT9CFG_CLUT9_STATUS; /**< Status information for pixel engine configuration of clut9, offset: 0x5100C */ uint8_t RESERVED_14[61424]; __O uint32_t PIXENG_MATRIX9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x60000 */ __I uint32_t PIXENG_MATRIX9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x60004 */ __IO uint32_t PIXENG_MATRIX9_STATICCONTROL; /**< Color Matrix static control register, offset: 0x60008 */ __IO uint32_t PIXENG_MATRIX9_CONTROL; /**< Color Matrix control register, offset: 0x6000C */ __IO uint32_t PIXENG_MATRIX9_RED0; /**< Matrix values for calculation of the red output value., offset: 0x60010 */ __IO uint32_t PIXENG_MATRIX9_RED1; /**< Matrix values for calculation of the red output value., offset: 0x60014 */ __IO uint32_t PIXENG_MATRIX9_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x60018 */ __IO uint32_t PIXENG_MATRIX9_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x6001C */ __IO uint32_t PIXENG_MATRIX9_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x60020 */ __IO uint32_t PIXENG_MATRIX9_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x60024 */ __IO uint32_t PIXENG_MATRIX9_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x60028 */ __IO uint32_t PIXENG_MATRIX9_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x6002C */ __IO uint32_t PIXENG_MATRIX9_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x60030 */ __IO uint32_t PIXENG_MATRIX9_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x60034 */ __I uint32_t PIXENG_MATRIX9_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x60038 */ uint8_t RESERVED_15[4036]; __O uint32_t PIXENG_MATRIX9CFG_MATRIX9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x61000 */ __I uint32_t PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x61004 */ __IO uint32_t PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC; /**< Dynamic pixel engine configuration for matrix9, offset: 0x61008 */ __I uint32_t PIXENG_MATRIX9CFG_MATRIX9_STATUS; /**< Status information for pixel engine configuration of matrix9, offset: 0x6100C */ uint8_t RESERVED_16[61424]; __O uint32_t PIXENG_BLITBLEND9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x70000 */ __I uint32_t PIXENG_BLITBLEND9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x70004 */ __IO uint32_t PIXENG_BLITBLEND9_STATICCONTROL; /**< BlitBlend static control register, offset: 0x70008 */ __IO uint32_t PIXENG_BLITBLEND9_CONTROL; /**< BlitBlend control register, offset: 0x7000C */ __IO uint32_t PIXENG_BLITBLEND9_NEUTRALBORDER; /**< Neutral border setup register, offset: 0x70010 */ __IO uint32_t PIXENG_BLITBLEND9_CONSTANTCOLOR; /**< Constant color register, offset: 0x70014 */ __IO uint32_t PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x70018 */ __IO uint32_t PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x7001C */ __IO uint32_t PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x70020 */ __IO uint32_t PIXENG_BLITBLEND9_ALPHABLENDFUNCTION; /**< Open GL alpha blending factors, offset: 0x70024 */ __IO uint32_t PIXENG_BLITBLEND9_BLENDMODE1; /**< Open GL and Open VG blending modes for colors red and green, offset: 0x70028 */ __IO uint32_t PIXENG_BLITBLEND9_BLENDMODE2; /**< Open GL and Open VG blending modes for color blue and alpha, offset: 0x7002C */ __IO uint32_t PIXENG_BLITBLEND9_DIRECTSETUP; /**< Direct Control of the BlitBlend Datapath multiplexers, do not change, offset: 0x70030 */ __I uint32_t PIXENG_BLITBLEND9_PRIMCONTROLWORD; /**< Value of last received primary control word, offset: 0x70034 */ __I uint32_t PIXENG_BLITBLEND9_SECCONTROLWORD; /**< Value of last received secondary control word, offset: 0x70038 */ uint8_t RESERVED_17[4036]; __O uint32_t PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x71000 */ __I uint32_t PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x71004 */ __IO uint32_t PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC; /**< Dynamic pixel engine configuration for blitblend9, offset: 0x71008 */ __I uint32_t PIXENG_BLITBLEND9CFG_BLITBLEND9_STATUS; /**< Status information for pixel engine configuration of blitblend9, offset: 0x7100C */ uint8_t RESERVED_18[61424]; __O uint32_t PIXENG_FETCHROT9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x80000 */ __I uint32_t PIXENG_FETCHROT9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x80004 */ __IO uint32_t PIXENG_FETCHROT9_STATICCONTROL; /**< Common static control options., offset: 0x80008 */ __IO uint32_t PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x8000C */ __IO uint32_t PIXENG_FETCHROT9_RINGBUFSTARTADDR0; /**< Ring buffer setup for layer 0., offset: 0x80010 */ __IO uint32_t PIXENG_FETCHROT9_RINGBUFSTARTADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x80014 */ __IO uint32_t PIXENG_FETCHROT9_RINGBUFWRAPADDR0; /**< Ring buffer setup for layer 0., offset: 0x80018 */ __IO uint32_t PIXENG_FETCHROT9_RINGBUFWRAPADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x8001C */ __IO uint32_t PIXENG_FETCHROT9_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x80020 */ __IO uint32_t PIXENG_FETCHROT9_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x80024 */ __IO uint32_t PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x80028 */ __IO uint32_t PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x8002C */ __IO uint32_t PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x80030 */ __IO uint32_t PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x80034 */ __IO uint32_t PIXENG_FETCHROT9_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x80038 */ __IO uint32_t PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8003C */ __IO uint32_t PIXENG_FETCHROT9_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x80040 */ __IO uint32_t PIXENG_FETCHROT9_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x80044 */ __IO uint32_t PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x80048 */ __IO uint32_t PIXENG_FETCHROT9_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x8004C */ __IO uint32_t PIXENG_FETCHROT9_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x80050 */ uint8_t RESERVED_19[4]; __IO uint32_t PIXENG_FETCHROT9_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x80058 */ __IO uint32_t PIXENG_FETCHROT9_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x8005C */ __IO uint32_t PIXENG_FETCHROT9_WARPCONTROL; /**< Warping control options., offset: 0x80060 */ __IO uint32_t PIXENG_FETCHROT9_AFFINESTARTX; /**< Start value X for affine warping., offset: 0x80064 */ __IO uint32_t PIXENG_FETCHROT9_AFFINESTARTY; /**< Start value Y for affine warping., offset: 0x80068 */ __IO uint32_t PIXENG_FETCHROT9_AFFINEDELTAXX; /**< DeltaXX increment for affine warping., offset: 0x8006C */ __IO uint32_t PIXENG_FETCHROT9_AFFINEDELTAXY; /**< DeltaXY increment for affine warping., offset: 0x80070 */ __IO uint32_t PIXENG_FETCHROT9_AFFINEDELTAYX; /**< DeltaYX increment for affine warping., offset: 0x80074 */ __IO uint32_t PIXENG_FETCHROT9_AFFINEDELTAYY; /**< DeltaYY increment for affine warping., offset: 0x80078 */ __IO uint32_t PIXENG_FETCHROT9_ARBSTARTX; /**< Start value X for arbitrary warping., offset: 0x8007C */ __IO uint32_t PIXENG_FETCHROT9_ARBSTARTY; /**< Start value Y for arbitrary warping., offset: 0x80080 */ __IO uint32_t PIXENG_FETCHROT9_ARBDELTA; /**< Start values for delta incrementation of arbitrary warping., offset: 0x80084 */ __IO uint32_t PIXENG_FETCHROT9_FIRPOSITIONS; /**< FIR sequence control register., offset: 0x80088 */ __IO uint32_t PIXENG_FETCHROT9_FIRCOEFFICIENTS; /**< FIR coefficients register., offset: 0x8008C */ __IO uint32_t PIXENG_FETCHROT9_CONTROL; /**< Shared common control settings for all layers., offset: 0x80090 */ __O uint32_t PIXENG_FETCHROT9_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x80094 */ __O uint32_t PIXENG_FETCHROT9_START; /**< Frame start trigger., offset: 0x80098 */ __I uint32_t PIXENG_FETCHROT9_FETCHTYPE; /**< Fetch unit type., offset: 0x8009C */ __I uint32_t PIXENG_FETCHROT9_READADDRESS0; /**< Ring buffer synchronization for layer 0., offset: 0x800A0 */ __I uint32_t PIXENG_FETCHROT9_READADDRESSMSB0; /**< Ring buffer synchronization for layer 0., offset: 0x800A4 */ __I uint32_t PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x800A8 */ __IO uint32_t PIXENG_FETCHROT9_STATUS; /**< Status informations., offset: 0x800AC */ __I uint32_t PIXENG_FETCHROT9_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x800B0 */ __I uint32_t PIXENG_FETCHROT9_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x800B4 */ __I uint32_t PIXENG_FETCHROT9_HIDDENSTATUS; /**< Hidden status informations., offset: 0x800B8 */ __I uint32_t PIXENG_FETCHROT9_WARPLINEOFFSET; /**< Offest between current used line and reference line., offset: 0x800BC */ uint8_t RESERVED_20[64]; __IO uint32_t PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0[64]; /**< Warp x interpolator table., array offset: 0x80100, array step: 0x4 */ __IO uint32_t PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1[64]; /**< Warp x interpolator table., array offset: 0x80200, array step: 0x4 */ uint8_t RESERVED_21[256]; __IO uint32_t PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0[65]; /**< Warp y interpolator table., array offset: 0x80400, array step: 0x4 */ uint8_t RESERVED_22[252]; __IO uint32_t PIXENG_FETCHROT9_WRPT_TBL_CONTROL; /**< Warping reference point table, write select., offset: 0x80600 */ uint8_t RESERVED_23[6652]; __IO uint32_t PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0[2048]; /**< Warp reference points table 0., array offset: 0x82000, array step: 0x4 */ __IO uint32_t PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1[2048]; /**< Warp reference points table 1., array offset: 0x84000, array step: 0x4 */ __O uint32_t PIXENG_FETCHROT9CFG_FETCHROT9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x86000 */ __I uint32_t PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x86004 */ __IO uint32_t PIXENG_FETCHROT9CFG_FETCHROT9_DYNAMIC; /**< Dynamic pixel engine configuration for fetchrot9, offset: 0x86008 */ __I uint32_t PIXENG_FETCHROT9CFG_FETCHROT9_STATUS; /**< Status information for pixel engine configuration of fetchrot9, offset: 0x8600C */ uint8_t RESERVED_24[40944]; __O uint32_t PIXENG_FETCHDECODE9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x90000 */ __I uint32_t PIXENG_FETCHDECODE9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x90004 */ __IO uint32_t PIXENG_FETCHDECODE9_STATICCONTROL; /**< Common static control options., offset: 0x90008 */ __IO uint32_t PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x9000C */ __IO uint32_t PIXENG_FETCHDECODE9_RINGBUFSTARTADDR0; /**< Ring buffer setup for layer 0., offset: 0x90010 */ __IO uint32_t PIXENG_FETCHDECODE9_RINGBUFSTARTADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x90014 */ __IO uint32_t PIXENG_FETCHDECODE9_RINGBUFWRAPADDR0; /**< Ring buffer setup for layer 0., offset: 0x90018 */ __IO uint32_t PIXENG_FETCHDECODE9_RINGBUFWRAPADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x9001C */ __IO uint32_t PIXENG_FETCHDECODE9_FRAMEPROPERTIES0; /**< Frame property setup for layer 0., offset: 0x90020 */ uint8_t RESERVED_25[4]; __IO uint32_t PIXENG_FETCHDECODE9_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x90028 */ __IO uint32_t PIXENG_FETCHDECODE9_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x9002C */ __IO uint32_t PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x90030 */ __IO uint32_t PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x90034 */ __IO uint32_t PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x90038 */ __IO uint32_t PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x9003C */ __IO uint32_t PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x90040 */ __IO uint32_t PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x90044 */ __IO uint32_t PIXENG_FETCHDECODE9_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x90048 */ __IO uint32_t PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x9004C */ __IO uint32_t PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x90050 */ __IO uint32_t PIXENG_FETCHDECODE9_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x90054 */ __IO uint32_t PIXENG_FETCHDECODE9_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x90058 */ uint8_t RESERVED_26[4]; __IO uint32_t PIXENG_FETCHDECODE9_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x90060 */ __IO uint32_t PIXENG_FETCHDECODE9_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x90064 */ __IO uint32_t PIXENG_FETCHDECODE9_DECODECONTROL; /**< Control options for RLAD decompression., offset: 0x90068 */ __IO uint32_t PIXENG_FETCHDECODE9_SOURCEBUFFERLENGTH; /**< Source buffer length for compressed data., offset: 0x9006C */ __IO uint32_t PIXENG_FETCHDECODE9_CONTROL; /**< Shared common control settings for all layers., offset: 0x90070 */ __O uint32_t PIXENG_FETCHDECODE9_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x90074 */ __O uint32_t PIXENG_FETCHDECODE9_START; /**< Frame start trigger., offset: 0x90078 */ __I uint32_t PIXENG_FETCHDECODE9_FETCHTYPE; /**< Fetch unit type., offset: 0x9007C */ __IO uint32_t PIXENG_FETCHDECODE9_DECODERSTATUS; /**< Status information of the RLAD decoder., offset: 0x90080 */ uint8_t RESERVED_27[4]; __I uint32_t PIXENG_FETCHDECODE9_READADDRESS0; /**< Ring buffer synchronization for layer 0., offset: 0x90088 */ __I uint32_t PIXENG_FETCHDECODE9_READADDRESSMSB0; /**< Ring buffer synchronization for layer 0., offset: 0x9008C */ __I uint32_t PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x90090 */ __IO uint32_t PIXENG_FETCHDECODE9_STATUS; /**< Status informations., offset: 0x90094 */ __I uint32_t PIXENG_FETCHDECODE9_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x90098 */ __I uint32_t PIXENG_FETCHDECODE9_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x9009C */ __I uint32_t PIXENG_FETCHDECODE9_HIDDENSTATUS; /**< Hidden status informations., offset: 0x900A0 */ uint8_t RESERVED_28[860]; __IO uint32_t PIXENG_FETCHDECODE9_COLORPALETTE[256]; /**< Color palette look up table., array offset: 0x90400, array step: 0x4 */ uint8_t RESERVED_29[2048]; __O uint32_t PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x91000 */ __I uint32_t PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x91004 */ __IO uint32_t PIXENG_FETCHDECODE9CFG_FETCHDECODE9_DYNAMIC; /**< Dynamic pixel engine configuration for fetchdecode9, offset: 0x91008 */ __I uint32_t PIXENG_FETCHDECODE9CFG_FETCHDECODE9_STATUS; /**< Status information for pixel engine configuration of fetchdecode9, offset: 0x9100C */ uint8_t RESERVED_30[61424]; __O uint32_t PIXENG_FETCHECO9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA0000 */ __I uint32_t PIXENG_FETCHECO9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA0004 */ __IO uint32_t PIXENG_FETCHECO9_STATICCONTROL; /**< Common static control options., offset: 0xA0008 */ __IO uint32_t PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0xA000C */ __IO uint32_t PIXENG_FETCHECO9_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0xA0010 */ __IO uint32_t PIXENG_FETCHECO9_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0xA0014 */ __IO uint32_t PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0xA0018 */ __IO uint32_t PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0xA001C */ __IO uint32_t PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0xA0020 */ __IO uint32_t PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0xA0024 */ __IO uint32_t PIXENG_FETCHECO9_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0xA0028 */ __IO uint32_t PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0xA002C */ __IO uint32_t PIXENG_FETCHECO9_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0xA0030 */ __IO uint32_t PIXENG_FETCHECO9_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0xA0034 */ __IO uint32_t PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0xA0038 */ __IO uint32_t PIXENG_FETCHECO9_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0xA003C */ __IO uint32_t PIXENG_FETCHECO9_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0xA0040 */ uint8_t RESERVED_31[4]; __IO uint32_t PIXENG_FETCHECO9_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0xA0048 */ __IO uint32_t PIXENG_FETCHECO9_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0xA004C */ __IO uint32_t PIXENG_FETCHECO9_CONTROL; /**< Shared common control settings for all layers., offset: 0xA0050 */ __O uint32_t PIXENG_FETCHECO9_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0xA0054 */ __O uint32_t PIXENG_FETCHECO9_START; /**< Frame start trigger., offset: 0xA0058 */ __I uint32_t PIXENG_FETCHECO9_FETCHTYPE; /**< Fetch unit type., offset: 0xA005C */ __I uint32_t PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0xA0060 */ uint8_t RESERVED_32[4]; __I uint32_t PIXENG_FETCHECO9_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0xA0068 */ __I uint32_t PIXENG_FETCHECO9_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0xA006C */ __I uint32_t PIXENG_FETCHECO9_HIDDENSTATUS; /**< Hidden status informations., offset: 0xA0070 */ uint8_t RESERVED_33[3980]; __O uint32_t PIXENG_FETCHECO9CFG_FETCHECO9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA1000 */ __I uint32_t PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA1004 */ __I uint32_t PIXENG_FETCHECO9CFG_FETCHECO9_STATUS; /**< Status information for pixel engine configuration of fetcheco9, offset: 0xA1008 */ uint8_t RESERVED_34[61428]; __O uint32_t PIXENG_HSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB0000 */ __I uint32_t PIXENG_HSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB0004 */ __IO uint32_t PIXENG_HSCALER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0xB0008 */ __IO uint32_t PIXENG_HSCALER9_SETUP1; /**< Phase interpolator setup., offset: 0xB000C */ __IO uint32_t PIXENG_HSCALER9_SETUP2; /**< Phase interpolator setup., offset: 0xB0010 */ __IO uint32_t PIXENG_HSCALER9_CONTROL; /**< Scaler operation control., offset: 0xB0014 */ uint8_t RESERVED_35[4072]; __O uint32_t PIXENG_HSCALER9CFG_HSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB1000 */ __I uint32_t PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB1004 */ __IO uint32_t PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler9, offset: 0xB1008 */ __I uint32_t PIXENG_HSCALER9CFG_HSCALER9_STATUS; /**< Status information for pixel engine configuration of hscaler9, offset: 0xB100C */ uint8_t RESERVED_36[61424]; __O uint32_t PIXENG_VSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC0000 */ __I uint32_t PIXENG_VSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC0004 */ __IO uint32_t PIXENG_VSCALER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0xC0008 */ __IO uint32_t PIXENG_VSCALER9_SETUP1; /**< Phase interpolator setup., offset: 0xC000C */ __IO uint32_t PIXENG_VSCALER9_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0xC0010 */ __IO uint32_t PIXENG_VSCALER9_CONTROL; /**< Scaler operation control., offset: 0xC0014 */ uint8_t RESERVED_37[4072]; __O uint32_t PIXENG_VSCALER9CFG_VSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC1000 */ __I uint32_t PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC1004 */ __IO uint32_t PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler9, offset: 0xC1008 */ __I uint32_t PIXENG_VSCALER9CFG_VSCALER9_STATUS; /**< Status information for pixel engine configuration of vscaler9, offset: 0xC100C */ uint8_t RESERVED_38[61424]; __O uint32_t PIXENG_FILTER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD0000 */ __I uint32_t PIXENG_FILTER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD0004 */ __IO uint32_t PIXENG_FILTER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0xD0008 */ __IO uint32_t PIXENG_FILTER9_CONTROL; /**< Filter operation main control., offset: 0xD000C */ __IO uint32_t PIXENG_FILTER9_FIR_CONTROL; /**< FIR filter operation control., offset: 0xD0010 */ __IO uint32_t PIXENG_FILTER9_COEFFICIENTS0; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0xD0014 */ __IO uint32_t PIXENG_FILTER9_COEFFICIENTS1; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0xD0018 */ __IO uint32_t PIXENG_FILTER9_COEFFICIENTS2; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0xD001C */ __IO uint32_t PIXENG_FILTER9_COEFFICIENTS3; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0xD0020 */ __IO uint32_t PIXENG_FILTER9_COEFFICIENTS4; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0xD0024 */ __IO uint32_t PIXENG_FILTER9_COEFFICIENTS5; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0xD0028 */ __IO uint32_t PIXENG_FILTER9_COEFFICIENTS6; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0xD002C */ uint8_t RESERVED_39[4048]; __O uint32_t PIXENG_FILTER9CFG_FILTER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD1000 */ __I uint32_t PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD1004 */ __IO uint32_t PIXENG_FILTER9CFG_FILTER9_DYNAMIC; /**< Dynamic pixel engine configuration for filter9, offset: 0xD1008 */ __I uint32_t PIXENG_FILTER9CFG_FILTER9_STATUS; /**< Status information for pixel engine configuration of filter9, offset: 0xD100C */ uint8_t RESERVED_40[61424]; __O uint32_t PIXENG_STORE9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xE0000 */ __I uint32_t PIXENG_STORE9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xE0004 */ __IO uint32_t PIXENG_STORE9_STATICCONTROL; /**< Store unit static control register., offset: 0xE0008 */ __IO uint32_t PIXENG_STORE9_BURSTBUFFERMANAGEMENT; /**< Burst Buffer setup register., offset: 0xE000C */ __IO uint32_t PIXENG_STORE9_RINGBUFSTARTADDR; /**< Ring buffer setup for destination., offset: 0xE0010 */ __IO uint32_t PIXENG_STORE9_RINGBUFSTARTADDRMSB; /**< Ring buffer setup for destination., offset: 0xE0014 */ __IO uint32_t PIXENG_STORE9_RINGBUFWRAPADDR; /**< Ring buffer setup for destination., offset: 0xE0018 */ __IO uint32_t PIXENG_STORE9_RINGBUFWRAPADDRMSB; /**< Ring buffer setup for destination., offset: 0xE001C */ __IO uint32_t PIXENG_STORE9_BASEADDRESS0; /**< Destination buffer 0 base address., offset: 0xE0020 */ __IO uint32_t PIXENG_STORE9_BASEADDRESSMSB0; /**< Destination buffer 0 base address., offset: 0xE0024 */ __IO uint32_t PIXENG_STORE9_AUTOUPDATEBASEADDRESS0; /**< Destination buffer 0 base address for auto update feature., offset: 0xE0028 */ __IO uint32_t PIXENG_STORE9_AUTOUPDATEBASEADDRESSMSB0; /**< Destination buffer 0 base address for auto update feature., offset: 0xE002C */ __IO uint32_t PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0; /**< Destination buffer 0 attributes., offset: 0xE0030 */ uint8_t RESERVED_41[4]; __IO uint32_t PIXENG_STORE9_BASEADDRESS1; /**< Destination buffer 1 base address., offset: 0xE0038 */ __IO uint32_t PIXENG_STORE9_BASEADDRESSMSB1; /**< Destination buffer 1 base address., offset: 0xE003C */ __IO uint32_t PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1; /**< Destination buffer 1 attributes., offset: 0xE0040 */ uint8_t RESERVED_42[4]; __IO uint32_t PIXENG_STORE9_BASEADDRESS2; /**< Destination buffer 2 base address., offset: 0xE0048 */ __IO uint32_t PIXENG_STORE9_BASEADDRESSMSB2; /**< Destination buffer 2 base address (upper 8 bits)., offset: 0xE004C */ __IO uint32_t PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2; /**< Destination buffer 2 attributes., offset: 0xE0050 */ __IO uint32_t PIXENG_STORE9_DESTINATIONBUFFERDIMENSION; /**< Destination buffer dimension., offset: 0xE0054 */ __IO uint32_t PIXENG_STORE9_FRAMEOFFSET; /**< Offset between destination frame and buffer., offset: 0xE0058 */ __IO uint32_t PIXENG_STORE9_COLORCOMPONENTBITS; /**< Color component size of destination buffer, offset: 0xE005C */ __IO uint32_t PIXENG_STORE9_COLORCOMPONENTSHIFT; /**< Color component offset of destination buffer., offset: 0xE0060 */ __IO uint32_t PIXENG_STORE9_CONTROL; /**< Store unit dynamic control register, offset: 0xE0064 */ __O uint32_t PIXENG_STORE9_START; /**< Store unit start register, offset: 0xE0068 */ uint8_t RESERVED_43[4]; __I uint32_t PIXENG_STORE9_WRITEADDRESS; /**< Ring buffer synchronization., offset: 0xE0070 */ __I uint32_t PIXENG_STORE9_WRITEADDRESSMSB; /**< Ring buffer synchronization., offset: 0xE0074 */ __I uint32_t PIXENG_STORE9_FRAMEPROPERTIES; /**< Ring buffer synchronization., offset: 0xE0078 */ __I uint32_t PIXENG_STORE9_BURSTBUFFERPROPERTIES; /**< Burst Buffer Property register, offset: 0xE007C */ __I uint32_t PIXENG_STORE9_LASTCONTROLWORD; /**< Shows the last control word received, offset: 0xE0080 */ __I uint32_t PIXENG_STORE9_PERFCOUNTER; /**< Performance counter result, offset: 0xE0084 */ __IO uint32_t PIXENG_STORE9_STATUS; /**< Shows status information, offset: 0xE0088 */ uint8_t RESERVED_44[3956]; __O uint32_t PIXENG_STORE9CFG_STORE9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xE1000 */ __I uint32_t PIXENG_STORE9CFG_STORE9_LOCKSTATUS; /**< Protection status of this address block., offset: 0xE1004 */ __IO uint32_t PIXENG_STORE9CFG_STORE9_STATIC; /**< Static pixel engine configuration for store9, offset: 0xE1008 */ __IO uint32_t PIXENG_STORE9CFG_STORE9_DYNAMIC; /**< Dynamic pixel engine configuration for store9, offset: 0xE100C */ __IO uint32_t PIXENG_STORE9CFG_STORE9_REQUEST; /**< ShadowLoadRequest register for endpoint store9, offset: 0xE1010 */ __O uint32_t PIXENG_STORE9CFG_STORE9_TRIGGER; /**< Trigger bits for pixel engine configuration of store9, offset: 0xE1014 */ __I uint32_t PIXENG_STORE9CFG_STORE9_STATUS; /**< Status information for pixel engine configuration of store9, offset: 0xE1018 */ uint8_t RESERVED_45[61412]; __O uint32_t PIXENG_CONSTFRAME0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xF0000 */ __I uint32_t PIXENG_CONSTFRAME0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xF0004 */ __IO uint32_t PIXENG_CONSTFRAME0_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0xF0008 */ __IO uint32_t PIXENG_CONSTFRAME0_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0xF000C */ __IO uint32_t PIXENG_CONSTFRAME0_CONSTANTCOLOR; /**< Color of output frame., offset: 0xF0010 */ __O uint32_t PIXENG_CONSTFRAME0_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0xF0014 */ __O uint32_t PIXENG_CONSTFRAME0_START; /**< ConstFrame unit start register, offset: 0xF0018 */ __I uint32_t PIXENG_CONSTFRAME0_STATUS; /**< Shows status information, offset: 0xF001C */ uint8_t RESERVED_46[4064]; __O uint32_t PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xF1000 */ __I uint32_t PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xF1004 */ __I uint32_t PIXENG_CONSTFRAME0CFG_CONSTFRAME0_STATUS; /**< Status information for pixel engine configuration of constframe0, offset: 0xF1008 */ uint8_t RESERVED_47[61428]; __O uint32_t PIXENG_CONSTFRAME4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x100000 */ __I uint32_t PIXENG_CONSTFRAME4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x100004 */ __IO uint32_t PIXENG_CONSTFRAME4_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x100008 */ __IO uint32_t PIXENG_CONSTFRAME4_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x10000C */ __IO uint32_t PIXENG_CONSTFRAME4_CONSTANTCOLOR; /**< Color of output frame., offset: 0x100010 */ __O uint32_t PIXENG_CONSTFRAME4_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x100014 */ __O uint32_t PIXENG_CONSTFRAME4_START; /**< ConstFrame unit start register, offset: 0x100018 */ __I uint32_t PIXENG_CONSTFRAME4_STATUS; /**< Shows status information, offset: 0x10001C */ uint8_t RESERVED_48[4064]; __O uint32_t PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x101000 */ __I uint32_t PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x101004 */ __I uint32_t PIXENG_CONSTFRAME4CFG_CONSTFRAME4_STATUS; /**< Status information for pixel engine configuration of constframe4, offset: 0x101008 */ uint8_t RESERVED_49[61428]; __O uint32_t PIXENG_EXTDST0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x110000 */ __I uint32_t PIXENG_EXTDST0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x110004 */ __IO uint32_t PIXENG_EXTDST0_STATICCONTROL; /**< External Destination static control register, offset: 0x110008 */ __IO uint32_t PIXENG_EXTDST0_CONTROL; /**< External Destination shadowed control register, offset: 0x11000C */ __O uint32_t PIXENG_EXTDST0_SOFTWAREKICK; /**< External Destination software kick, offset: 0x110010 */ __IO uint32_t PIXENG_EXTDST0_STATUS; /**< External Destination Unit current status, offset: 0x110014 */ __I uint32_t PIXENG_EXTDST0_CONTROLWORD; /**< Value of last received control word, offset: 0x110018 */ __I uint32_t PIXENG_EXTDST0_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x11001C */ __I uint32_t PIXENG_EXTDST0_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x110020 */ __I uint32_t PIXENG_EXTDST0_PERFCOUNTER; /**< Performance counter result, offset: 0x110024 */ uint8_t RESERVED_50[4056]; __O uint32_t PIXENG_EXTDST0CFG_EXTDST0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x111000 */ __I uint32_t PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x111004 */ __IO uint32_t PIXENG_EXTDST0CFG_EXTDST0_STATIC; /**< Static pixel engine configuration for extdst0, offset: 0x111008 */ __IO uint32_t PIXENG_EXTDST0CFG_EXTDST0_DYNAMIC; /**< Dynamic pixel engine configuration for extdst0, offset: 0x11100C */ __IO uint32_t PIXENG_EXTDST0CFG_EXTDST0_REQUEST; /**< ShadowLoadRequest register for endpoint extdst0, offset: 0x111010 */ __O uint32_t PIXENG_EXTDST0CFG_EXTDST0_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst0, offset: 0x111014 */ __I uint32_t PIXENG_EXTDST0CFG_EXTDST0_STATUS; /**< Status information for pixel engine configuration of extdst0, offset: 0x111018 */ uint8_t RESERVED_51[61412]; __O uint32_t PIXENG_EXTDST4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x120000 */ __I uint32_t PIXENG_EXTDST4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x120004 */ __IO uint32_t PIXENG_EXTDST4_STATICCONTROL; /**< External Destination static control register, offset: 0x120008 */ __IO uint32_t PIXENG_EXTDST4_CONTROL; /**< External Destination shadowed control register, offset: 0x12000C */ __O uint32_t PIXENG_EXTDST4_SOFTWAREKICK; /**< External Destination software kick, offset: 0x120010 */ __IO uint32_t PIXENG_EXTDST4_STATUS; /**< External Destination Unit current status, offset: 0x120014 */ __I uint32_t PIXENG_EXTDST4_CONTROLWORD; /**< Value of last received control word, offset: 0x120018 */ __I uint32_t PIXENG_EXTDST4_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x12001C */ __I uint32_t PIXENG_EXTDST4_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x120020 */ __I uint32_t PIXENG_EXTDST4_PERFCOUNTER; /**< Performance counter result, offset: 0x120024 */ uint8_t RESERVED_52[4056]; __O uint32_t PIXENG_EXTDST4CFG_EXTDST4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x121000 */ __I uint32_t PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x121004 */ __IO uint32_t PIXENG_EXTDST4CFG_EXTDST4_STATIC; /**< Static pixel engine configuration for extdst4, offset: 0x121008 */ __IO uint32_t PIXENG_EXTDST4CFG_EXTDST4_DYNAMIC; /**< Dynamic pixel engine configuration for extdst4, offset: 0x12100C */ __IO uint32_t PIXENG_EXTDST4CFG_EXTDST4_REQUEST; /**< ShadowLoadRequest register for endpoint extdst4, offset: 0x121010 */ __O uint32_t PIXENG_EXTDST4CFG_EXTDST4_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst4, offset: 0x121014 */ __I uint32_t PIXENG_EXTDST4CFG_EXTDST4_STATUS; /**< Status information for pixel engine configuration of extdst4, offset: 0x121018 */ uint8_t RESERVED_53[61412]; __O uint32_t PIXENG_CONSTFRAME1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x130000 */ __I uint32_t PIXENG_CONSTFRAME1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x130004 */ __IO uint32_t PIXENG_CONSTFRAME1_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x130008 */ __IO uint32_t PIXENG_CONSTFRAME1_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x13000C */ __IO uint32_t PIXENG_CONSTFRAME1_CONSTANTCOLOR; /**< Color of output frame., offset: 0x130010 */ __O uint32_t PIXENG_CONSTFRAME1_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x130014 */ __O uint32_t PIXENG_CONSTFRAME1_START; /**< ConstFrame unit start register, offset: 0x130018 */ __I uint32_t PIXENG_CONSTFRAME1_STATUS; /**< Shows status information, offset: 0x13001C */ uint8_t RESERVED_54[4064]; __O uint32_t PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x131000 */ __I uint32_t PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x131004 */ __I uint32_t PIXENG_CONSTFRAME1CFG_CONSTFRAME1_STATUS; /**< Status information for pixel engine configuration of constframe1, offset: 0x131008 */ uint8_t RESERVED_55[61428]; __O uint32_t PIXENG_CONSTFRAME5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x140000 */ __I uint32_t PIXENG_CONSTFRAME5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x140004 */ __IO uint32_t PIXENG_CONSTFRAME5_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x140008 */ __IO uint32_t PIXENG_CONSTFRAME5_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x14000C */ __IO uint32_t PIXENG_CONSTFRAME5_CONSTANTCOLOR; /**< Color of output frame., offset: 0x140010 */ __O uint32_t PIXENG_CONSTFRAME5_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x140014 */ __O uint32_t PIXENG_CONSTFRAME5_START; /**< ConstFrame unit start register, offset: 0x140018 */ __I uint32_t PIXENG_CONSTFRAME5_STATUS; /**< Shows status information, offset: 0x14001C */ uint8_t RESERVED_56[4064]; __O uint32_t PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x141000 */ __I uint32_t PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x141004 */ __I uint32_t PIXENG_CONSTFRAME5CFG_CONSTFRAME5_STATUS; /**< Status information for pixel engine configuration of constframe5, offset: 0x141008 */ uint8_t RESERVED_57[61428]; __O uint32_t PIXENG_EXTDST1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x150000 */ __I uint32_t PIXENG_EXTDST1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x150004 */ __IO uint32_t PIXENG_EXTDST1_STATICCONTROL; /**< External Destination static control register, offset: 0x150008 */ __IO uint32_t PIXENG_EXTDST1_CONTROL; /**< External Destination shadowed control register, offset: 0x15000C */ __O uint32_t PIXENG_EXTDST1_SOFTWAREKICK; /**< External Destination software kick, offset: 0x150010 */ __IO uint32_t PIXENG_EXTDST1_STATUS; /**< External Destination Unit current status, offset: 0x150014 */ __I uint32_t PIXENG_EXTDST1_CONTROLWORD; /**< Value of last received control word, offset: 0x150018 */ __I uint32_t PIXENG_EXTDST1_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x15001C */ __I uint32_t PIXENG_EXTDST1_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x150020 */ __I uint32_t PIXENG_EXTDST1_PERFCOUNTER; /**< Performance counter result, offset: 0x150024 */ uint8_t RESERVED_58[4056]; __O uint32_t PIXENG_EXTDST1CFG_EXTDST1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x151000 */ __I uint32_t PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x151004 */ __IO uint32_t PIXENG_EXTDST1CFG_EXTDST1_STATIC; /**< Static pixel engine configuration for extdst1, offset: 0x151008 */ __IO uint32_t PIXENG_EXTDST1CFG_EXTDST1_DYNAMIC; /**< Dynamic pixel engine configuration for extdst1, offset: 0x15100C */ __IO uint32_t PIXENG_EXTDST1CFG_EXTDST1_REQUEST; /**< ShadowLoadRequest register for endpoint extdst1, offset: 0x151010 */ __O uint32_t PIXENG_EXTDST1CFG_EXTDST1_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst1, offset: 0x151014 */ __I uint32_t PIXENG_EXTDST1CFG_EXTDST1_STATUS; /**< Status information for pixel engine configuration of extdst1, offset: 0x151018 */ uint8_t RESERVED_59[61412]; __O uint32_t PIXENG_EXTDST5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x160000 */ __I uint32_t PIXENG_EXTDST5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x160004 */ __IO uint32_t PIXENG_EXTDST5_STATICCONTROL; /**< External Destination static control register, offset: 0x160008 */ __IO uint32_t PIXENG_EXTDST5_CONTROL; /**< External Destination shadowed control register, offset: 0x16000C */ __O uint32_t PIXENG_EXTDST5_SOFTWAREKICK; /**< External Destination software kick, offset: 0x160010 */ __IO uint32_t PIXENG_EXTDST5_STATUS; /**< External Destination Unit current status, offset: 0x160014 */ __I uint32_t PIXENG_EXTDST5_CONTROLWORD; /**< Value of last received control word, offset: 0x160018 */ __I uint32_t PIXENG_EXTDST5_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x16001C */ __I uint32_t PIXENG_EXTDST5_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x160020 */ __I uint32_t PIXENG_EXTDST5_PERFCOUNTER; /**< Performance counter result, offset: 0x160024 */ uint8_t RESERVED_60[4056]; __O uint32_t PIXENG_EXTDST5CFG_EXTDST5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x161000 */ __I uint32_t PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x161004 */ __IO uint32_t PIXENG_EXTDST5CFG_EXTDST5_STATIC; /**< Static pixel engine configuration for extdst5, offset: 0x161008 */ __IO uint32_t PIXENG_EXTDST5CFG_EXTDST5_DYNAMIC; /**< Dynamic pixel engine configuration for extdst5, offset: 0x16100C */ __IO uint32_t PIXENG_EXTDST5CFG_EXTDST5_REQUEST; /**< ShadowLoadRequest register for endpoint extdst5, offset: 0x161010 */ __O uint32_t PIXENG_EXTDST5CFG_EXTDST5_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst5, offset: 0x161014 */ __I uint32_t PIXENG_EXTDST5CFG_EXTDST5_STATUS; /**< Status information for pixel engine configuration of extdst5, offset: 0x161018 */ uint8_t RESERVED_61[61412]; __O uint32_t PIXENG_LAYERBLEND1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x170000 */ __I uint32_t PIXENG_LAYERBLEND1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x170004 */ __IO uint32_t PIXENG_LAYERBLEND1_STATICCONTROL; /**< Static control settings., offset: 0x170008 */ __IO uint32_t PIXENG_LAYERBLEND1_CONTROL; /**< Common control settings., offset: 0x17000C */ __IO uint32_t PIXENG_LAYERBLEND1_BLENDCONTROL; /**< Options for blend operations, offset: 0x170010 */ __IO uint32_t PIXENG_LAYERBLEND1_POSITION; /**< Position of secondary (overlay) input frame, offset: 0x170014 */ __I uint32_t PIXENG_LAYERBLEND1_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0x170018 */ __I uint32_t PIXENG_LAYERBLEND1_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0x17001C */ uint8_t RESERVED_62[4064]; __O uint32_t PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x171000 */ __I uint32_t PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x171004 */ __IO uint32_t PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend1, offset: 0x171008 */ __I uint32_t PIXENG_LAYERBLEND1CFG_LAYERBLEND1_STATUS; /**< Status information for pixel engine configuration of layerblend1, offset: 0x17100C */ uint8_t RESERVED_63[61424]; __O uint32_t PIXENG_LAYERBLEND2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x180000 */ __I uint32_t PIXENG_LAYERBLEND2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x180004 */ __IO uint32_t PIXENG_LAYERBLEND2_STATICCONTROL; /**< Static control settings., offset: 0x180008 */ __IO uint32_t PIXENG_LAYERBLEND2_CONTROL; /**< Common control settings., offset: 0x18000C */ __IO uint32_t PIXENG_LAYERBLEND2_BLENDCONTROL; /**< Options for blend operations, offset: 0x180010 */ __IO uint32_t PIXENG_LAYERBLEND2_POSITION; /**< Position of secondary (overlay) input frame, offset: 0x180014 */ __I uint32_t PIXENG_LAYERBLEND2_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0x180018 */ __I uint32_t PIXENG_LAYERBLEND2_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0x18001C */ uint8_t RESERVED_64[4064]; __O uint32_t PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x181000 */ __I uint32_t PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x181004 */ __IO uint32_t PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend2, offset: 0x181008 */ __I uint32_t PIXENG_LAYERBLEND2CFG_LAYERBLEND2_STATUS; /**< Status information for pixel engine configuration of layerblend2, offset: 0x18100C */ uint8_t RESERVED_65[61424]; __O uint32_t PIXENG_LAYERBLEND3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x190000 */ __I uint32_t PIXENG_LAYERBLEND3_LOCKSTATUS; /**< Protection status of this address block., offset: 0x190004 */ __IO uint32_t PIXENG_LAYERBLEND3_STATICCONTROL; /**< Static control settings., offset: 0x190008 */ __IO uint32_t PIXENG_LAYERBLEND3_CONTROL; /**< Common control settings., offset: 0x19000C */ __IO uint32_t PIXENG_LAYERBLEND3_BLENDCONTROL; /**< Options for blend operations, offset: 0x190010 */ __IO uint32_t PIXENG_LAYERBLEND3_POSITION; /**< Position of secondary (overlay) input frame, offset: 0x190014 */ __I uint32_t PIXENG_LAYERBLEND3_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0x190018 */ __I uint32_t PIXENG_LAYERBLEND3_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0x19001C */ uint8_t RESERVED_66[4064]; __O uint32_t PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x191000 */ __I uint32_t PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS; /**< Protection status of this address block., offset: 0x191004 */ __IO uint32_t PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend3, offset: 0x191008 */ __I uint32_t PIXENG_LAYERBLEND3CFG_LAYERBLEND3_STATUS; /**< Status information for pixel engine configuration of layerblend3, offset: 0x19100C */ uint8_t RESERVED_67[61424]; __O uint32_t PIXENG_LAYERBLEND4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1A0000 */ __I uint32_t PIXENG_LAYERBLEND4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1A0004 */ __IO uint32_t PIXENG_LAYERBLEND4_STATICCONTROL; /**< Static control settings., offset: 0x1A0008 */ __IO uint32_t PIXENG_LAYERBLEND4_CONTROL; /**< Common control settings., offset: 0x1A000C */ __IO uint32_t PIXENG_LAYERBLEND4_BLENDCONTROL; /**< Options for blend operations, offset: 0x1A0010 */ __IO uint32_t PIXENG_LAYERBLEND4_POSITION; /**< Position of secondary (overlay) input frame, offset: 0x1A0014 */ __I uint32_t PIXENG_LAYERBLEND4_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0x1A0018 */ __I uint32_t PIXENG_LAYERBLEND4_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0x1A001C */ uint8_t RESERVED_68[4064]; __O uint32_t PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1A1000 */ __I uint32_t PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1A1004 */ __IO uint32_t PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend4, offset: 0x1A1008 */ __I uint32_t PIXENG_LAYERBLEND4CFG_LAYERBLEND4_STATUS; /**< Status information for pixel engine configuration of layerblend4, offset: 0x1A100C */ uint8_t RESERVED_69[61424]; __O uint32_t PIXENG_LAYERBLEND5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1B0000 */ __I uint32_t PIXENG_LAYERBLEND5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1B0004 */ __IO uint32_t PIXENG_LAYERBLEND5_STATICCONTROL; /**< Static control settings., offset: 0x1B0008 */ __IO uint32_t PIXENG_LAYERBLEND5_CONTROL; /**< Common control settings., offset: 0x1B000C */ __IO uint32_t PIXENG_LAYERBLEND5_BLENDCONTROL; /**< Options for blend operations, offset: 0x1B0010 */ __IO uint32_t PIXENG_LAYERBLEND5_POSITION; /**< Position of secondary (overlay) input frame, offset: 0x1B0014 */ __I uint32_t PIXENG_LAYERBLEND5_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0x1B0018 */ __I uint32_t PIXENG_LAYERBLEND5_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0x1B001C */ uint8_t RESERVED_70[4064]; __O uint32_t PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1B1000 */ __I uint32_t PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1B1004 */ __IO uint32_t PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend5, offset: 0x1B1008 */ __I uint32_t PIXENG_LAYERBLEND5CFG_LAYERBLEND5_STATUS; /**< Status information for pixel engine configuration of layerblend5, offset: 0x1B100C */ uint8_t RESERVED_71[61424]; __O uint32_t PIXENG_LAYERBLEND6_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1C0000 */ __I uint32_t PIXENG_LAYERBLEND6_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1C0004 */ __IO uint32_t PIXENG_LAYERBLEND6_STATICCONTROL; /**< Static control settings., offset: 0x1C0008 */ __IO uint32_t PIXENG_LAYERBLEND6_CONTROL; /**< Common control settings., offset: 0x1C000C */ __IO uint32_t PIXENG_LAYERBLEND6_BLENDCONTROL; /**< Options for blend operations, offset: 0x1C0010 */ __IO uint32_t PIXENG_LAYERBLEND6_POSITION; /**< Position of secondary (overlay) input frame, offset: 0x1C0014 */ __I uint32_t PIXENG_LAYERBLEND6_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0x1C0018 */ __I uint32_t PIXENG_LAYERBLEND6_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0x1C001C */ uint8_t RESERVED_72[4064]; __O uint32_t PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1C1000 */ __I uint32_t PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1C1004 */ __IO uint32_t PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend6, offset: 0x1C1008 */ __I uint32_t PIXENG_LAYERBLEND6CFG_LAYERBLEND6_STATUS; /**< Status information for pixel engine configuration of layerblend6, offset: 0x1C100C */ uint8_t RESERVED_73[61424]; __O uint32_t PIXENG_FETCHLAYER0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1D0000 */ __I uint32_t PIXENG_FETCHLAYER0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1D0004 */ __IO uint32_t PIXENG_FETCHLAYER0_STATICCONTROL; /**< Common static control options., offset: 0x1D0008 */ __IO uint32_t PIXENG_FETCHLAYER0_SHDLDREQCONTROL; /**< Shadow load request flags for each layer. Static control options., offset: 0x1D000C */ __IO uint32_t PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x1D0010 */ uint8_t RESERVED_74[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1D0018 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x1D001C */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1D0020 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x1D0024 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1D0028 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1D002C */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1D0030 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1D0034 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x1D0038 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x1D003C */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x1D0040 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x1D0044 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x1D0048 */ uint8_t RESERVED_75[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1D0050 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB1; /**< Source buffer base address of layer 1., offset: 0x1D0054 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1D0058 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB1; /**< Source buffer base address of layer 1., offset: 0x1D005C */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x1D0060 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1., offset: 0x1D0064 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x1D0068 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x1D006C */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x1D0070 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x1D0074 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x1D0078 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x1D007C */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x1D0080 */ uint8_t RESERVED_76[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1D0088 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB2; /**< Source buffer base address of layer 2., offset: 0x1D008C */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1D0090 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB2; /**< Source buffer base address of layer 2., offset: 0x1D0094 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x1D0098 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2; /**< Source buffer dimensions of layer 2., offset: 0x1D009C */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x1D00A0 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x1D00A4 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x1D00A8 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x1D00AC */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x1D00B0 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x1D00B4 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x1D00B8 */ uint8_t RESERVED_77[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1D00C0 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB3; /**< Source buffer base address of layer 3., offset: 0x1D00C4 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1D00C8 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB3; /**< Source buffer base address of layer 3., offset: 0x1D00CC */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x1D00D0 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3; /**< Source buffer dimensions of layer 3., offset: 0x1D00D4 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x1D00D8 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x1D00DC */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x1D00E0 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x1D00E4 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x1D00E8 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x1D00EC */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x1D00F0 */ uint8_t RESERVED_78[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x1D00F8 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB4; /**< Source buffer base address of layer 4., offset: 0x1D00FC */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x1D0100 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB4; /**< Source buffer base address of layer 4., offset: 0x1D0104 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x1D0108 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4; /**< Source buffer dimensions of layer 4., offset: 0x1D010C */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x1D0110 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x1D0114 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x1D0118 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x1D011C */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x1D0120 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x1D0124 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x1D0128 */ uint8_t RESERVED_79[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x1D0130 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB5; /**< Source buffer base address of layer 5., offset: 0x1D0134 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x1D0138 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB5; /**< Source buffer base address of layer 5., offset: 0x1D013C */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x1D0140 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5; /**< Source buffer dimensions of layer 5., offset: 0x1D0144 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x1D0148 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x1D014C */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x1D0150 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x1D0154 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x1D0158 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x1D015C */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x1D0160 */ uint8_t RESERVED_80[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1D0168 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB6; /**< Source buffer base address of layer 6., offset: 0x1D016C */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1D0170 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB6; /**< Source buffer base address of layer 6., offset: 0x1D0174 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x1D0178 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6; /**< Source buffer dimensions of layer 6., offset: 0x1D017C */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x1D0180 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x1D0184 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET6; /**< Position of layer 6 within the destination frame., offset: 0x1D0188 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x1D018C */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x1D0190 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x1D0194 */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x1D0198 */ uint8_t RESERVED_81[4]; __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1D01A0 */ __IO uint32_t PIXENG_FETCHLAYER0_BASEADDRESSMSB7; /**< Source buffer base address of layer 7., offset: 0x1D01A4 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1D01A8 */ __IO uint32_t PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB7; /**< Source buffer base address of layer 7., offset: 0x1D01AC */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7; /**< Source buffer attributes for layer 7., offset: 0x1D01B0 */ __IO uint32_t PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7; /**< Source buffer dimensions of layer 7., offset: 0x1D01B4 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x1D01B8 */ __IO uint32_t PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x1D01BC */ __IO uint32_t PIXENG_FETCHLAYER0_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x1D01C0 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x1D01C4 */ __IO uint32_t PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x1D01C8 */ __IO uint32_t PIXENG_FETCHLAYER0_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x1D01CC */ __IO uint32_t PIXENG_FETCHLAYER0_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x1D01D0 */ uint8_t RESERVED_82[4]; __IO uint32_t PIXENG_FETCHLAYER0_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x1D01D8 */ __IO uint32_t PIXENG_FETCHLAYER0_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x1D01DC */ __IO uint32_t PIXENG_FETCHLAYER0_CONTROL; /**< Shared common control settings for all layers., offset: 0x1D01E0 */ __IO uint32_t PIXENG_FETCHLAYER0_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x1D01E4 */ __O uint32_t PIXENG_FETCHLAYER0_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x1D01E8 */ __O uint32_t PIXENG_FETCHLAYER0_START; /**< Frame start trigger., offset: 0x1D01EC */ __I uint32_t PIXENG_FETCHLAYER0_FETCHTYPE; /**< Fetch unit type., offset: 0x1D01F0 */ uint8_t RESERVED_83[4]; __I uint32_t PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x1D01F8 */ __IO uint32_t PIXENG_FETCHLAYER0_STATUS; /**< Status informations., offset: 0x1D01FC */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x1D0200 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x1D0204 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1D0208 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB1; /**< MSB bits of Current Working BaseAddress for layer 1., offset: 0x1D020C */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1D0210 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB2; /**< MSB bits of Current Working BaseAddress for layer 2., offset: 0x1D0214 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1D0218 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB3; /**< MSB bits of Current Working BaseAddress for layer 3., offset: 0x1D021C */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x1D0220 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB4; /**< MSB bits of Current Working BaseAddress for layer 4., offset: 0x1D0224 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x1D0228 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB5; /**< MSB bits of Current Working BaseAddress for layer 5., offset: 0x1D022C */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1D0230 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB6; /**< MSB bits of Current Working BaseAddress for layer 6., offset: 0x1D0234 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1D0238 */ __I uint32_t PIXENG_FETCHLAYER0_CURBASEADDRESSMSB7; /**< MSB bits of Current Working BaseAddress for layer 7., offset: 0x1D023C */ __I uint32_t PIXENG_FETCHLAYER0_HIDDENSTATUS; /**< Hidden status informations., offset: 0x1D0240 */ uint8_t RESERVED_84[444]; __IO uint32_t PIXENG_FETCHLAYER0_COLORPALETTE[256]; /**< Color palette look up table., array offset: 0x1D0400, array step: 0x4 */ uint8_t RESERVED_85[2048]; __O uint32_t PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1D1000 */ __I uint32_t PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1D1004 */ __I uint32_t PIXENG_FETCHLAYER0CFG_FETCHLAYER0_STATUS; /**< Status information for pixel engine configuration of fetchlayer0, offset: 0x1D1008 */ uint8_t RESERVED_86[61428]; __O uint32_t PIXENG_FETCHLAYER1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1E0000 */ __I uint32_t PIXENG_FETCHLAYER1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1E0004 */ __IO uint32_t PIXENG_FETCHLAYER1_STATICCONTROL; /**< Common static control options., offset: 0x1E0008 */ __IO uint32_t PIXENG_FETCHLAYER1_SHDLDREQCONTROL; /**< Shadow load request flags for each layer. Static control options., offset: 0x1E000C */ __IO uint32_t PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x1E0010 */ uint8_t RESERVED_87[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1E0018 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x1E001C */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1E0020 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x1E0024 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1E0028 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1E002C */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1E0030 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1E0034 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x1E0038 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x1E003C */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x1E0040 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x1E0044 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x1E0048 */ uint8_t RESERVED_88[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1E0050 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB1; /**< Source buffer base address of layer 1., offset: 0x1E0054 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1E0058 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB1; /**< Source buffer base address of layer 1., offset: 0x1E005C */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x1E0060 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1., offset: 0x1E0064 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x1E0068 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x1E006C */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x1E0070 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x1E0074 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x1E0078 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x1E007C */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x1E0080 */ uint8_t RESERVED_89[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1E0088 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB2; /**< Source buffer base address of layer 2., offset: 0x1E008C */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1E0090 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB2; /**< Source buffer base address of layer 2., offset: 0x1E0094 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x1E0098 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2; /**< Source buffer dimensions of layer 2., offset: 0x1E009C */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x1E00A0 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x1E00A4 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x1E00A8 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x1E00AC */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x1E00B0 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x1E00B4 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x1E00B8 */ uint8_t RESERVED_90[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1E00C0 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB3; /**< Source buffer base address of layer 3., offset: 0x1E00C4 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1E00C8 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB3; /**< Source buffer base address of layer 3., offset: 0x1E00CC */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x1E00D0 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3; /**< Source buffer dimensions of layer 3., offset: 0x1E00D4 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x1E00D8 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x1E00DC */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x1E00E0 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x1E00E4 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x1E00E8 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x1E00EC */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x1E00F0 */ uint8_t RESERVED_91[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x1E00F8 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB4; /**< Source buffer base address of layer 4., offset: 0x1E00FC */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x1E0100 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB4; /**< Source buffer base address of layer 4., offset: 0x1E0104 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x1E0108 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4; /**< Source buffer dimensions of layer 4., offset: 0x1E010C */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x1E0110 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x1E0114 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x1E0118 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x1E011C */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x1E0120 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x1E0124 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x1E0128 */ uint8_t RESERVED_92[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x1E0130 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB5; /**< Source buffer base address of layer 5., offset: 0x1E0134 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x1E0138 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB5; /**< Source buffer base address of layer 5., offset: 0x1E013C */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x1E0140 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5; /**< Source buffer dimensions of layer 5., offset: 0x1E0144 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x1E0148 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x1E014C */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x1E0150 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x1E0154 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x1E0158 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x1E015C */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x1E0160 */ uint8_t RESERVED_93[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1E0168 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB6; /**< Source buffer base address of layer 6., offset: 0x1E016C */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1E0170 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB6; /**< Source buffer base address of layer 6., offset: 0x1E0174 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x1E0178 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6; /**< Source buffer dimensions of layer 6., offset: 0x1E017C */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x1E0180 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x1E0184 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET6; /**< Position of layer 6 within the destination frame., offset: 0x1E0188 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x1E018C */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x1E0190 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x1E0194 */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x1E0198 */ uint8_t RESERVED_94[4]; __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1E01A0 */ __IO uint32_t PIXENG_FETCHLAYER1_BASEADDRESSMSB7; /**< Source buffer base address of layer 7., offset: 0x1E01A4 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1E01A8 */ __IO uint32_t PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB7; /**< Source buffer base address of layer 7., offset: 0x1E01AC */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7; /**< Source buffer attributes for layer 7., offset: 0x1E01B0 */ __IO uint32_t PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7; /**< Source buffer dimensions of layer 7., offset: 0x1E01B4 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x1E01B8 */ __IO uint32_t PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x1E01BC */ __IO uint32_t PIXENG_FETCHLAYER1_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x1E01C0 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x1E01C4 */ __IO uint32_t PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x1E01C8 */ __IO uint32_t PIXENG_FETCHLAYER1_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x1E01CC */ __IO uint32_t PIXENG_FETCHLAYER1_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x1E01D0 */ uint8_t RESERVED_95[4]; __IO uint32_t PIXENG_FETCHLAYER1_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x1E01D8 */ __IO uint32_t PIXENG_FETCHLAYER1_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x1E01DC */ __IO uint32_t PIXENG_FETCHLAYER1_CONTROL; /**< Shared common control settings for all layers., offset: 0x1E01E0 */ __IO uint32_t PIXENG_FETCHLAYER1_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x1E01E4 */ __O uint32_t PIXENG_FETCHLAYER1_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x1E01E8 */ __O uint32_t PIXENG_FETCHLAYER1_START; /**< Frame start trigger., offset: 0x1E01EC */ __I uint32_t PIXENG_FETCHLAYER1_FETCHTYPE; /**< Fetch unit type., offset: 0x1E01F0 */ uint8_t RESERVED_96[4]; __I uint32_t PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x1E01F8 */ __IO uint32_t PIXENG_FETCHLAYER1_STATUS; /**< Status informations., offset: 0x1E01FC */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x1E0200 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x1E0204 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1E0208 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB1; /**< MSB bits of Current Working BaseAddress for layer 1., offset: 0x1E020C */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1E0210 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB2; /**< MSB bits of Current Working BaseAddress for layer 2., offset: 0x1E0214 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1E0218 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB3; /**< MSB bits of Current Working BaseAddress for layer 3., offset: 0x1E021C */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x1E0220 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB4; /**< MSB bits of Current Working BaseAddress for layer 4., offset: 0x1E0224 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x1E0228 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB5; /**< MSB bits of Current Working BaseAddress for layer 5., offset: 0x1E022C */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1E0230 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB6; /**< MSB bits of Current Working BaseAddress for layer 6., offset: 0x1E0234 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1E0238 */ __I uint32_t PIXENG_FETCHLAYER1_CURBASEADDRESSMSB7; /**< MSB bits of Current Working BaseAddress for layer 7., offset: 0x1E023C */ __I uint32_t PIXENG_FETCHLAYER1_HIDDENSTATUS; /**< Hidden status informations., offset: 0x1E0240 */ uint8_t RESERVED_97[444]; __IO uint32_t PIXENG_FETCHLAYER1_COLORPALETTE[256]; /**< Color palette look up table., array offset: 0x1E0400, array step: 0x4 */ uint8_t RESERVED_98[2048]; __O uint32_t PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1E1000 */ __I uint32_t PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1E1004 */ __I uint32_t PIXENG_FETCHLAYER1CFG_FETCHLAYER1_STATUS; /**< Status information for pixel engine configuration of fetchlayer1, offset: 0x1E1008 */ uint8_t RESERVED_99[61428]; __O uint32_t PIXENG_FETCHYUV3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1F0000 */ __I uint32_t PIXENG_FETCHYUV3_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1F0004 */ __IO uint32_t PIXENG_FETCHYUV3_STATICCONTROL; /**< Common static control options., offset: 0x1F0008 */ __IO uint32_t PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x1F000C */ __IO uint32_t PIXENG_FETCHYUV3_RINGBUFSTARTADDR0; /**< Ring buffer setup for layer 0., offset: 0x1F0010 */ __IO uint32_t PIXENG_FETCHYUV3_RINGBUFSTARTADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x1F0014 */ __IO uint32_t PIXENG_FETCHYUV3_RINGBUFWRAPADDR0; /**< Ring buffer setup for layer 0., offset: 0x1F0018 */ __IO uint32_t PIXENG_FETCHYUV3_RINGBUFWRAPADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x1F001C */ __IO uint32_t PIXENG_FETCHYUV3_FRAMEPROPERTIES0; /**< Frame property setup for layer 0., offset: 0x1F0020 */ uint8_t RESERVED_100[4]; __IO uint32_t PIXENG_FETCHYUV3_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1F0028 */ __IO uint32_t PIXENG_FETCHYUV3_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x1F002C */ __IO uint32_t PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1F0030 */ __IO uint32_t PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x1F0034 */ __IO uint32_t PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1F0038 */ __IO uint32_t PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1F003C */ __IO uint32_t PIXENG_FETCHYUV3_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1F0040 */ __IO uint32_t PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1F0044 */ __IO uint32_t PIXENG_FETCHYUV3_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x1F0048 */ __IO uint32_t PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x1F004C */ __IO uint32_t PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x1F0050 */ __IO uint32_t PIXENG_FETCHYUV3_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x1F0054 */ __IO uint32_t PIXENG_FETCHYUV3_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x1F0058 */ uint8_t RESERVED_101[4]; __IO uint32_t PIXENG_FETCHYUV3_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x1F0060 */ __IO uint32_t PIXENG_FETCHYUV3_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x1F0064 */ __IO uint32_t PIXENG_FETCHYUV3_CONTROL; /**< Shared common control settings for all layers., offset: 0x1F0068 */ __O uint32_t PIXENG_FETCHYUV3_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x1F006C */ __O uint32_t PIXENG_FETCHYUV3_START; /**< Frame start trigger., offset: 0x1F0070 */ __I uint32_t PIXENG_FETCHYUV3_FETCHTYPE; /**< Fetch unit type., offset: 0x1F0074 */ __I uint32_t PIXENG_FETCHYUV3_READADDRESS0; /**< Ring buffer synchronization for layer 0., offset: 0x1F0078 */ __I uint32_t PIXENG_FETCHYUV3_READADDRESSMSB0; /**< Ring buffer synchronization for layer 0., offset: 0x1F007C */ __I uint32_t PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x1F0080 */ __IO uint32_t PIXENG_FETCHYUV3_STATUS; /**< Status informations., offset: 0x1F0084 */ __I uint32_t PIXENG_FETCHYUV3_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x1F0088 */ __I uint32_t PIXENG_FETCHYUV3_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x1F008C */ __I uint32_t PIXENG_FETCHYUV3_HIDDENSTATUS; /**< Hidden status informations., offset: 0x1F0090 */ uint8_t RESERVED_102[3948]; __O uint32_t PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1F1000 */ __I uint32_t PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1F1004 */ __IO uint32_t PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC; /**< Dynamic pixel engine configuration for fetchyuv3, offset: 0x1F1008 */ __I uint32_t PIXENG_FETCHYUV3CFG_FETCHYUV3_STATUS; /**< Status information for pixel engine configuration of fetchyuv3, offset: 0x1F100C */ uint8_t RESERVED_103[61424]; __O uint32_t PIXENG_FETCHYUV0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x200000 */ __I uint32_t PIXENG_FETCHYUV0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x200004 */ __IO uint32_t PIXENG_FETCHYUV0_STATICCONTROL; /**< Common static control options., offset: 0x200008 */ __IO uint32_t PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x20000C */ __IO uint32_t PIXENG_FETCHYUV0_RINGBUFSTARTADDR0; /**< Ring buffer setup for layer 0., offset: 0x200010 */ __IO uint32_t PIXENG_FETCHYUV0_RINGBUFSTARTADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x200014 */ __IO uint32_t PIXENG_FETCHYUV0_RINGBUFWRAPADDR0; /**< Ring buffer setup for layer 0., offset: 0x200018 */ __IO uint32_t PIXENG_FETCHYUV0_RINGBUFWRAPADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x20001C */ __IO uint32_t PIXENG_FETCHYUV0_FRAMEPROPERTIES0; /**< Frame property setup for layer 0., offset: 0x200020 */ uint8_t RESERVED_104[4]; __IO uint32_t PIXENG_FETCHYUV0_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x200028 */ __IO uint32_t PIXENG_FETCHYUV0_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x20002C */ __IO uint32_t PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x200030 */ __IO uint32_t PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x200034 */ __IO uint32_t PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x200038 */ __IO uint32_t PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x20003C */ __IO uint32_t PIXENG_FETCHYUV0_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x200040 */ __IO uint32_t PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x200044 */ __IO uint32_t PIXENG_FETCHYUV0_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x200048 */ __IO uint32_t PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x20004C */ __IO uint32_t PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x200050 */ __IO uint32_t PIXENG_FETCHYUV0_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x200054 */ __IO uint32_t PIXENG_FETCHYUV0_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x200058 */ uint8_t RESERVED_105[4]; __IO uint32_t PIXENG_FETCHYUV0_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x200060 */ __IO uint32_t PIXENG_FETCHYUV0_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x200064 */ __IO uint32_t PIXENG_FETCHYUV0_CONTROL; /**< Shared common control settings for all layers., offset: 0x200068 */ __O uint32_t PIXENG_FETCHYUV0_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x20006C */ __O uint32_t PIXENG_FETCHYUV0_START; /**< Frame start trigger., offset: 0x200070 */ __I uint32_t PIXENG_FETCHYUV0_FETCHTYPE; /**< Fetch unit type., offset: 0x200074 */ __I uint32_t PIXENG_FETCHYUV0_READADDRESS0; /**< Ring buffer synchronization for layer 0., offset: 0x200078 */ __I uint32_t PIXENG_FETCHYUV0_READADDRESSMSB0; /**< Ring buffer synchronization for layer 0., offset: 0x20007C */ __I uint32_t PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x200080 */ __IO uint32_t PIXENG_FETCHYUV0_STATUS; /**< Status informations., offset: 0x200084 */ __I uint32_t PIXENG_FETCHYUV0_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x200088 */ __I uint32_t PIXENG_FETCHYUV0_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x20008C */ __I uint32_t PIXENG_FETCHYUV0_HIDDENSTATUS; /**< Hidden status informations., offset: 0x200090 */ uint8_t RESERVED_106[3948]; __O uint32_t PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x201000 */ __I uint32_t PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x201004 */ __IO uint32_t PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC; /**< Dynamic pixel engine configuration for fetchyuv0, offset: 0x201008 */ __I uint32_t PIXENG_FETCHYUV0CFG_FETCHYUV0_STATUS; /**< Status information for pixel engine configuration of fetchyuv0, offset: 0x20100C */ uint8_t RESERVED_107[61424]; __O uint32_t PIXENG_FETCHECO0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x210000 */ __I uint32_t PIXENG_FETCHECO0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x210004 */ __IO uint32_t PIXENG_FETCHECO0_STATICCONTROL; /**< Common static control options., offset: 0x210008 */ __IO uint32_t PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x21000C */ __IO uint32_t PIXENG_FETCHECO0_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x210010 */ __IO uint32_t PIXENG_FETCHECO0_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x210014 */ __IO uint32_t PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x210018 */ __IO uint32_t PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x21001C */ __IO uint32_t PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x210020 */ __IO uint32_t PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x210024 */ __IO uint32_t PIXENG_FETCHECO0_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x210028 */ __IO uint32_t PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x21002C */ __IO uint32_t PIXENG_FETCHECO0_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x210030 */ __IO uint32_t PIXENG_FETCHECO0_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x210034 */ __IO uint32_t PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x210038 */ __IO uint32_t PIXENG_FETCHECO0_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x21003C */ __IO uint32_t PIXENG_FETCHECO0_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x210040 */ uint8_t RESERVED_108[4]; __IO uint32_t PIXENG_FETCHECO0_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x210048 */ __IO uint32_t PIXENG_FETCHECO0_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x21004C */ __IO uint32_t PIXENG_FETCHECO0_CONTROL; /**< Shared common control settings for all layers., offset: 0x210050 */ __O uint32_t PIXENG_FETCHECO0_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x210054 */ __O uint32_t PIXENG_FETCHECO0_START; /**< Frame start trigger., offset: 0x210058 */ __I uint32_t PIXENG_FETCHECO0_FETCHTYPE; /**< Fetch unit type., offset: 0x21005C */ __I uint32_t PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x210060 */ uint8_t RESERVED_109[4]; __I uint32_t PIXENG_FETCHECO0_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x210068 */ __I uint32_t PIXENG_FETCHECO0_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x21006C */ __I uint32_t PIXENG_FETCHECO0_HIDDENSTATUS; /**< Hidden status informations., offset: 0x210070 */ uint8_t RESERVED_110[3980]; __O uint32_t PIXENG_FETCHECO0CFG_FETCHECO0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x211000 */ __I uint32_t PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x211004 */ __I uint32_t PIXENG_FETCHECO0CFG_FETCHECO0_STATUS; /**< Status information for pixel engine configuration of fetcheco0, offset: 0x211008 */ uint8_t RESERVED_111[61428]; __O uint32_t PIXENG_FETCHYUV1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x220000 */ __I uint32_t PIXENG_FETCHYUV1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x220004 */ __IO uint32_t PIXENG_FETCHYUV1_STATICCONTROL; /**< Common static control options., offset: 0x220008 */ __IO uint32_t PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x22000C */ __IO uint32_t PIXENG_FETCHYUV1_RINGBUFSTARTADDR0; /**< Ring buffer setup for layer 0., offset: 0x220010 */ __IO uint32_t PIXENG_FETCHYUV1_RINGBUFSTARTADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x220014 */ __IO uint32_t PIXENG_FETCHYUV1_RINGBUFWRAPADDR0; /**< Ring buffer setup for layer 0., offset: 0x220018 */ __IO uint32_t PIXENG_FETCHYUV1_RINGBUFWRAPADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x22001C */ __IO uint32_t PIXENG_FETCHYUV1_FRAMEPROPERTIES0; /**< Frame property setup for layer 0., offset: 0x220020 */ uint8_t RESERVED_112[4]; __IO uint32_t PIXENG_FETCHYUV1_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x220028 */ __IO uint32_t PIXENG_FETCHYUV1_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x22002C */ __IO uint32_t PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x220030 */ __IO uint32_t PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x220034 */ __IO uint32_t PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x220038 */ __IO uint32_t PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x22003C */ __IO uint32_t PIXENG_FETCHYUV1_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x220040 */ __IO uint32_t PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x220044 */ __IO uint32_t PIXENG_FETCHYUV1_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x220048 */ __IO uint32_t PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x22004C */ __IO uint32_t PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x220050 */ __IO uint32_t PIXENG_FETCHYUV1_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x220054 */ __IO uint32_t PIXENG_FETCHYUV1_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x220058 */ uint8_t RESERVED_113[4]; __IO uint32_t PIXENG_FETCHYUV1_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x220060 */ __IO uint32_t PIXENG_FETCHYUV1_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x220064 */ __IO uint32_t PIXENG_FETCHYUV1_CONTROL; /**< Shared common control settings for all layers., offset: 0x220068 */ __O uint32_t PIXENG_FETCHYUV1_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x22006C */ __O uint32_t PIXENG_FETCHYUV1_START; /**< Frame start trigger., offset: 0x220070 */ __I uint32_t PIXENG_FETCHYUV1_FETCHTYPE; /**< Fetch unit type., offset: 0x220074 */ __I uint32_t PIXENG_FETCHYUV1_READADDRESS0; /**< Ring buffer synchronization for layer 0., offset: 0x220078 */ __I uint32_t PIXENG_FETCHYUV1_READADDRESSMSB0; /**< Ring buffer synchronization for layer 0., offset: 0x22007C */ __I uint32_t PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x220080 */ __IO uint32_t PIXENG_FETCHYUV1_STATUS; /**< Status informations., offset: 0x220084 */ __I uint32_t PIXENG_FETCHYUV1_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x220088 */ __I uint32_t PIXENG_FETCHYUV1_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x22008C */ __I uint32_t PIXENG_FETCHYUV1_HIDDENSTATUS; /**< Hidden status informations., offset: 0x220090 */ uint8_t RESERVED_114[3948]; __O uint32_t PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x221000 */ __I uint32_t PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x221004 */ __IO uint32_t PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC; /**< Dynamic pixel engine configuration for fetchyuv1, offset: 0x221008 */ __I uint32_t PIXENG_FETCHYUV1CFG_FETCHYUV1_STATUS; /**< Status information for pixel engine configuration of fetchyuv1, offset: 0x22100C */ uint8_t RESERVED_115[61424]; __O uint32_t PIXENG_FETCHECO1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x230000 */ __I uint32_t PIXENG_FETCHECO1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x230004 */ __IO uint32_t PIXENG_FETCHECO1_STATICCONTROL; /**< Common static control options., offset: 0x230008 */ __IO uint32_t PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x23000C */ __IO uint32_t PIXENG_FETCHECO1_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x230010 */ __IO uint32_t PIXENG_FETCHECO1_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x230014 */ __IO uint32_t PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x230018 */ __IO uint32_t PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x23001C */ __IO uint32_t PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x230020 */ __IO uint32_t PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x230024 */ __IO uint32_t PIXENG_FETCHECO1_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x230028 */ __IO uint32_t PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x23002C */ __IO uint32_t PIXENG_FETCHECO1_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x230030 */ __IO uint32_t PIXENG_FETCHECO1_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x230034 */ __IO uint32_t PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x230038 */ __IO uint32_t PIXENG_FETCHECO1_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x23003C */ __IO uint32_t PIXENG_FETCHECO1_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x230040 */ uint8_t RESERVED_116[4]; __IO uint32_t PIXENG_FETCHECO1_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x230048 */ __IO uint32_t PIXENG_FETCHECO1_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x23004C */ __IO uint32_t PIXENG_FETCHECO1_CONTROL; /**< Shared common control settings for all layers., offset: 0x230050 */ __O uint32_t PIXENG_FETCHECO1_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x230054 */ __O uint32_t PIXENG_FETCHECO1_START; /**< Frame start trigger., offset: 0x230058 */ __I uint32_t PIXENG_FETCHECO1_FETCHTYPE; /**< Fetch unit type., offset: 0x23005C */ __I uint32_t PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x230060 */ uint8_t RESERVED_117[4]; __I uint32_t PIXENG_FETCHECO1_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x230068 */ __I uint32_t PIXENG_FETCHECO1_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x23006C */ __I uint32_t PIXENG_FETCHECO1_HIDDENSTATUS; /**< Hidden status informations., offset: 0x230070 */ uint8_t RESERVED_118[3980]; __O uint32_t PIXENG_FETCHECO1CFG_FETCHECO1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x231000 */ __I uint32_t PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x231004 */ __I uint32_t PIXENG_FETCHECO1CFG_FETCHECO1_STATUS; /**< Status information for pixel engine configuration of fetcheco1, offset: 0x231008 */ uint8_t RESERVED_119[61428]; __O uint32_t PIXENG_FETCHYUV2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x240000 */ __I uint32_t PIXENG_FETCHYUV2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x240004 */ __IO uint32_t PIXENG_FETCHYUV2_STATICCONTROL; /**< Common static control options., offset: 0x240008 */ __IO uint32_t PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x24000C */ __IO uint32_t PIXENG_FETCHYUV2_RINGBUFSTARTADDR0; /**< Ring buffer setup for layer 0., offset: 0x240010 */ __IO uint32_t PIXENG_FETCHYUV2_RINGBUFSTARTADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x240014 */ __IO uint32_t PIXENG_FETCHYUV2_RINGBUFWRAPADDR0; /**< Ring buffer setup for layer 0., offset: 0x240018 */ __IO uint32_t PIXENG_FETCHYUV2_RINGBUFWRAPADDRMSB0; /**< Ring buffer setup for layer 0., offset: 0x24001C */ __IO uint32_t PIXENG_FETCHYUV2_FRAMEPROPERTIES0; /**< Frame property setup for layer 0., offset: 0x240020 */ uint8_t RESERVED_120[4]; __IO uint32_t PIXENG_FETCHYUV2_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x240028 */ __IO uint32_t PIXENG_FETCHYUV2_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x24002C */ __IO uint32_t PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x240030 */ __IO uint32_t PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x240034 */ __IO uint32_t PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x240038 */ __IO uint32_t PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x24003C */ __IO uint32_t PIXENG_FETCHYUV2_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x240040 */ __IO uint32_t PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x240044 */ __IO uint32_t PIXENG_FETCHYUV2_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x240048 */ __IO uint32_t PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x24004C */ __IO uint32_t PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x240050 */ __IO uint32_t PIXENG_FETCHYUV2_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x240054 */ __IO uint32_t PIXENG_FETCHYUV2_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x240058 */ uint8_t RESERVED_121[4]; __IO uint32_t PIXENG_FETCHYUV2_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x240060 */ __IO uint32_t PIXENG_FETCHYUV2_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x240064 */ __IO uint32_t PIXENG_FETCHYUV2_CONTROL; /**< Shared common control settings for all layers., offset: 0x240068 */ __O uint32_t PIXENG_FETCHYUV2_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x24006C */ __O uint32_t PIXENG_FETCHYUV2_START; /**< Frame start trigger., offset: 0x240070 */ __I uint32_t PIXENG_FETCHYUV2_FETCHTYPE; /**< Fetch unit type., offset: 0x240074 */ __I uint32_t PIXENG_FETCHYUV2_READADDRESS0; /**< Ring buffer synchronization for layer 0., offset: 0x240078 */ __I uint32_t PIXENG_FETCHYUV2_READADDRESSMSB0; /**< Ring buffer synchronization for layer 0., offset: 0x24007C */ __I uint32_t PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x240080 */ __IO uint32_t PIXENG_FETCHYUV2_STATUS; /**< Status informations., offset: 0x240084 */ __I uint32_t PIXENG_FETCHYUV2_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x240088 */ __I uint32_t PIXENG_FETCHYUV2_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x24008C */ __I uint32_t PIXENG_FETCHYUV2_HIDDENSTATUS; /**< Hidden status informations., offset: 0x240090 */ uint8_t RESERVED_122[3948]; __O uint32_t PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x241000 */ __I uint32_t PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x241004 */ __IO uint32_t PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC; /**< Dynamic pixel engine configuration for fetchyuv2, offset: 0x241008 */ __I uint32_t PIXENG_FETCHYUV2CFG_FETCHYUV2_STATUS; /**< Status information for pixel engine configuration of fetchyuv2, offset: 0x24100C */ uint8_t RESERVED_123[61424]; __O uint32_t PIXENG_FETCHECO2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x250000 */ __I uint32_t PIXENG_FETCHECO2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x250004 */ __IO uint32_t PIXENG_FETCHECO2_STATICCONTROL; /**< Common static control options., offset: 0x250008 */ __IO uint32_t PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x25000C */ __IO uint32_t PIXENG_FETCHECO2_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x250010 */ __IO uint32_t PIXENG_FETCHECO2_BASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x250014 */ __IO uint32_t PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x250018 */ __IO uint32_t PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESSMSB0; /**< Source buffer base address of layer 0., offset: 0x25001C */ __IO uint32_t PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x250020 */ __IO uint32_t PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x250024 */ __IO uint32_t PIXENG_FETCHECO2_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x250028 */ __IO uint32_t PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x25002C */ __IO uint32_t PIXENG_FETCHECO2_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x250030 */ __IO uint32_t PIXENG_FETCHECO2_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x250034 */ __IO uint32_t PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x250038 */ __IO uint32_t PIXENG_FETCHECO2_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x25003C */ __IO uint32_t PIXENG_FETCHECO2_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x250040 */ uint8_t RESERVED_124[4]; __IO uint32_t PIXENG_FETCHECO2_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x250048 */ __IO uint32_t PIXENG_FETCHECO2_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x25004C */ __IO uint32_t PIXENG_FETCHECO2_CONTROL; /**< Shared common control settings for all layers., offset: 0x250050 */ __O uint32_t PIXENG_FETCHECO2_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x250054 */ __O uint32_t PIXENG_FETCHECO2_START; /**< Frame start trigger., offset: 0x250058 */ __I uint32_t PIXENG_FETCHECO2_FETCHTYPE; /**< Fetch unit type., offset: 0x25005C */ __I uint32_t PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x250060 */ uint8_t RESERVED_125[4]; __I uint32_t PIXENG_FETCHECO2_CURBASEADDRESS0; /**< Current Working BaseAddress for layer 0., offset: 0x250068 */ __I uint32_t PIXENG_FETCHECO2_CURBASEADDRESSMSB0; /**< MSB bits of Current Working BaseAddress for layer 0., offset: 0x25006C */ __I uint32_t PIXENG_FETCHECO2_HIDDENSTATUS; /**< Hidden status informations., offset: 0x250070 */ uint8_t RESERVED_126[3980]; __O uint32_t PIXENG_FETCHECO2CFG_FETCHECO2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x251000 */ __I uint32_t PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x251004 */ __I uint32_t PIXENG_FETCHECO2CFG_FETCHECO2_STATUS; /**< Status information for pixel engine configuration of fetcheco2, offset: 0x251008 */ uint8_t RESERVED_127[61428]; __O uint32_t PIXENG_MATRIX4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x260000 */ __I uint32_t PIXENG_MATRIX4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x260004 */ __IO uint32_t PIXENG_MATRIX4_STATICCONTROL; /**< Color Matrix static control register, offset: 0x260008 */ __IO uint32_t PIXENG_MATRIX4_CONTROL; /**< Color Matrix control register, offset: 0x26000C */ __IO uint32_t PIXENG_MATRIX4_RED0; /**< Matrix values for calculation of the red output value., offset: 0x260010 */ __IO uint32_t PIXENG_MATRIX4_RED1; /**< Matrix values for calculation of the red output value., offset: 0x260014 */ __IO uint32_t PIXENG_MATRIX4_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x260018 */ __IO uint32_t PIXENG_MATRIX4_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x26001C */ __IO uint32_t PIXENG_MATRIX4_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x260020 */ __IO uint32_t PIXENG_MATRIX4_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x260024 */ __IO uint32_t PIXENG_MATRIX4_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x260028 */ __IO uint32_t PIXENG_MATRIX4_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x26002C */ __IO uint32_t PIXENG_MATRIX4_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x260030 */ __IO uint32_t PIXENG_MATRIX4_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x260034 */ __I uint32_t PIXENG_MATRIX4_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x260038 */ uint8_t RESERVED_128[4036]; __O uint32_t PIXENG_MATRIX4CFG_MATRIX4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x261000 */ __I uint32_t PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x261004 */ __IO uint32_t PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC; /**< Dynamic pixel engine configuration for matrix4, offset: 0x261008 */ __I uint32_t PIXENG_MATRIX4CFG_MATRIX4_STATUS; /**< Status information for pixel engine configuration of matrix4, offset: 0x26100C */ uint8_t RESERVED_129[61424]; __O uint32_t PIXENG_HSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x270000 */ __I uint32_t PIXENG_HSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x270004 */ __IO uint32_t PIXENG_HSCALER4_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x270008 */ __IO uint32_t PIXENG_HSCALER4_SETUP1; /**< Phase interpolator setup., offset: 0x27000C */ __IO uint32_t PIXENG_HSCALER4_SETUP2; /**< Phase interpolator setup., offset: 0x270010 */ __IO uint32_t PIXENG_HSCALER4_CONTROL; /**< Scaler operation control., offset: 0x270014 */ uint8_t RESERVED_130[4072]; __O uint32_t PIXENG_HSCALER4CFG_HSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x271000 */ __I uint32_t PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x271004 */ __IO uint32_t PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler4, offset: 0x271008 */ __I uint32_t PIXENG_HSCALER4CFG_HSCALER4_STATUS; /**< Status information for pixel engine configuration of hscaler4, offset: 0x27100C */ uint8_t RESERVED_131[61424]; __O uint32_t PIXENG_VSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x280000 */ __I uint32_t PIXENG_VSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x280004 */ __IO uint32_t PIXENG_VSCALER4_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x280008 */ __IO uint32_t PIXENG_VSCALER4_SETUP1; /**< Phase interpolator setup., offset: 0x28000C */ __IO uint32_t PIXENG_VSCALER4_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0x280010 */ __IO uint32_t PIXENG_VSCALER4_CONTROL; /**< Scaler operation control., offset: 0x280014 */ uint8_t RESERVED_132[4072]; __O uint32_t PIXENG_VSCALER4CFG_VSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x281000 */ __I uint32_t PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x281004 */ __IO uint32_t PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler4, offset: 0x281008 */ __I uint32_t PIXENG_VSCALER4CFG_VSCALER4_STATUS; /**< Status information for pixel engine configuration of vscaler4, offset: 0x28100C */ uint8_t RESERVED_133[126960]; __O uint32_t DISENG_DOMAINBLEND0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2A0000 */ __I uint32_t DISENG_DOMAINBLEND0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2A0004 */ __IO uint32_t DISENG_DOMAINBLEND0_STATICCONTROL; /**< Static control settings., offset: 0x2A0008 */ __O uint32_t DISENG_DOMAINBLEND0_CONTROLTRIGGER; /**< Shadow load and sequence complete triggers., offset: 0x2A000C */ __IO uint32_t DISENG_DOMAINBLEND0_MODECONTROL; /**< Operation mode of the domainblend, offset: 0x2A0010 */ __IO uint32_t DISENG_DOMAINBLEND0_ALPHACONTROL; /**< Alpha mask settings., offset: 0x2A0014 */ __IO uint32_t DISENG_DOMAINBLEND0_BLENDCONTROL; /**< Options for blend operations, offset: 0x2A0018 */ __I uint32_t DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK; /**< The status of primary and secondary sources waiting for pixels., offset: 0x2A001C */ __O uint32_t DISENG_DOMAINBLEND0_LOCKUP_CLEAR; /**< The register can be used to internally reset domainblend if it gets stuck by pending pixels from one source., offset: 0x2A0020 */ __IO uint32_t DISENG_DOMAINBLEND0_DELAY_COUNTER_EN; /**< The register enables the delay and error counters that report on the delay on prim and sec sources., offset: 0x2A0024 */ __I uint32_t DISENG_DOMAINBLEND0_DELAY_COUNTER_PRIM; /**< The number of inavtive clock cycles during which the domainblend is waiting for pixels from primary source., offset: 0x2A0028 */ __I uint32_t DISENG_DOMAINBLEND0_DELAY_COUNTER_SEC; /**< The number of inavtive clock cycles during which the domainblend is waiting for pixels from secondary source., offset: 0x2A002C */ __I uint32_t DISENG_DOMAINBLEND0_ERROR_COUNTER_PRIM; /**< The number of inavtive clock cycles on the primary source till the synchronization loss of domainblend., offset: 0x2A0030 */ __I uint32_t DISENG_DOMAINBLEND0_ERROR_COUNTER_SEC; /**< The number of inavtive clock cycles on the secondary source till the synchronization loss of domainblend., offset: 0x2A0034 */ __I uint32_t DISENG_DOMAINBLEND0_SOURCE_STATUS; /**< Source protocol error detection for primary and secondary sources, offset: 0x2A0038 */ __O uint32_t DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR; /**< Clearing source protocol error status for both primary and secondary sources, offset: 0x2A003C */ __I uint32_t DISENG_DOMAINBLEND0_PRIMCONTROLWORD; /**< Value of last received primary control word, for debugging, offset: 0x2A0040 */ __I uint32_t DISENG_DOMAINBLEND0_SECCONTROLWORD; /**< Value of last received secondary control word, for debugging, offset: 0x2A0044 */ uint8_t RESERVED_134[65464]; __O uint32_t DISENG_FRAMEGEN0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2B0000 */ __I uint32_t DISENG_FRAMEGEN0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2B0004 */ __IO uint32_t DISENG_FRAMEGEN0_FGSTCTRL; /**< FrameGen Static Control Register, offset: 0x2B0008 */ __IO uint32_t DISENG_FRAMEGEN0_HTCFG1; /**< FrameGen Horizontal Timing Config Register 1, offset: 0x2B000C */ __IO uint32_t DISENG_FRAMEGEN0_HTCFG2; /**< FrameGen Horizontal Timing Config Register 2, offset: 0x2B0010 */ __IO uint32_t DISENG_FRAMEGEN0_VTCFG1; /**< FrameGen Vertical Timing Config Register 1, offset: 0x2B0014 */ __IO uint32_t DISENG_FRAMEGEN0_VTCFG2; /**< FrameGen Vertical Timing Config Register 2, offset: 0x2B0018 */ __IO uint32_t DISENG_FRAMEGEN0_INT0CONFIG; /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0x2B001C */ __IO uint32_t DISENG_FRAMEGEN0_INT1CONFIG; /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0x2B0020 */ __IO uint32_t DISENG_FRAMEGEN0_INT2CONFIG; /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0x2B0024 */ __IO uint32_t DISENG_FRAMEGEN0_INT3CONFIG; /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0x2B0028 */ __IO uint32_t DISENG_FRAMEGEN0_PKICKCONFIG; /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0x2B002C */ __IO uint32_t DISENG_FRAMEGEN0_SKICKCONFIG; /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0x2B0030 */ __IO uint32_t DISENG_FRAMEGEN0_SECSTATCONFIG; /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0x2B0034 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR1; /**< FrameGen Skew Regulation Control Register 1., offset: 0x2B0038 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR2; /**< FrameGen Skew Regulation Control Register 2, offset: 0x2B003C */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR3; /**< FrameGen Skew Regulation Control Register 3, offset: 0x2B0040 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR4; /**< FrameGen Skew Regulation Control Register 4, offset: 0x2B0044 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR5; /**< FrameGen Skew Regulation Control Register 5, offset: 0x2B0048 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR6; /**< FrameGen Skew Regulation Control Register 6, offset: 0x2B004C */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR7; /**< FrameGen Skew Regulation Control Register 7, offset: 0x2B0050 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR8; /**< FrameGen Skew Regulation Control Register 8, offset: 0x2B0054 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR9; /**< FrameGen Skew Regulation Control Register 9, offset: 0x2B0058 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR10; /**< FrameGen Skew Regulation Control Register 10, offset: 0x2B005C */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR11; /**< FrameGen Skew Regulation Control Register 11, offset: 0x2B0060 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR12; /**< FrameGen Skew Regulation Control Register 12, offset: 0x2B0064 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR13; /**< FrameGen Skew Regulation Control Register 13, offset: 0x2B0068 */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR14; /**< FrameGen Skew Regulation Control Register 14, offset: 0x2B006C */ __IO uint32_t DISENG_FRAMEGEN0_FGSRCR15; /**< FrameGen Skew Regulation Control Register 15, offset: 0x2B0070 */ __IO uint32_t DISENG_FRAMEGEN0_FGKSDR; /**< FrameGen Kick System Debug Register, offset: 0x2B0074 */ __IO uint32_t DISENG_FRAMEGEN0_PACFG; /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0x2B0078 */ __IO uint32_t DISENG_FRAMEGEN0_SACFG; /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0x2B007C */ __IO uint32_t DISENG_FRAMEGEN0_FGINCTRL; /**< FrameGen Input Control Register (shadowed), offset: 0x2B0080 */ __IO uint32_t DISENG_FRAMEGEN0_FGINCTRLPANIC; /**< FrameGen Input Control Panic Register (shadowed), offset: 0x2B0084 */ __IO uint32_t DISENG_FRAMEGEN0_FGCCR; /**< FrameGen Constant Color Register (shadowed), offset: 0x2B0088 */ __IO uint32_t DISENG_FRAMEGEN0_FGENABLE; /**< FrameGen Enable Register, offset: 0x2B008C */ __O uint32_t DISENG_FRAMEGEN0_FGSLR; /**< FrameGen Shadow Load Register, offset: 0x2B0090 */ __I uint32_t DISENG_FRAMEGEN0_FGENSTS; /**< FrameGen Enable Status Register, offset: 0x2B0094 */ __I uint32_t DISENG_FRAMEGEN0_FGTIMESTAMP; /**< Time stamp status., offset: 0x2B0098 */ __I uint32_t DISENG_FRAMEGEN0_FGCHSTAT; /**< FrameGen Channel Status Register, offset: 0x2B009C */ __O uint32_t DISENG_FRAMEGEN0_FGCHSTATCLR; /**< FrameGen Channel Status Clear Register, offset: 0x2B00A0 */ __I uint32_t DISENG_FRAMEGEN0_FGSKEWMON; /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0x2B00A4 */ __I uint32_t DISENG_FRAMEGEN0_FGPFIFOMIN; /**< FrameGen Primary FIFO Min Fill Register, offset: 0x2B00A8 */ __I uint32_t DISENG_FRAMEGEN0_FGPFIFOMAX; /**< FrameGen Primary FIFO Max Fill Register, offset: 0x2B00AC */ __O uint32_t DISENG_FRAMEGEN0_FGPFIFOFILLCLR; /**< FrameGen Primary FIFO Fill Clear Register, offset: 0x2B00B0 */ __IO uint32_t DISENG_FRAMEGEN0_FGPFIFOTRES; /**< FrameGen Primary FIFO Thresholds, offset: 0x2B00B4 */ __I uint32_t DISENG_FRAMEGEN0_FGSFIFOMIN; /**< FrameGen Secondary FIFO Min Fill Register, offset: 0x2B00B8 */ __I uint32_t DISENG_FRAMEGEN0_FGSFIFOMAX; /**< FrameGen Secondary FIFO Max Fill Register, offset: 0x2B00BC */ __O uint32_t DISENG_FRAMEGEN0_FGSFIFOFILLCLR; /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0x2B00C0 */ __I uint32_t DISENG_FRAMEGEN0_FGSREPD; /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0x2B00C4 */ __I uint32_t DISENG_FRAMEGEN0_FGSRFTD; /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0x2B00C8 */ __I uint32_t DISENG_FRAMEGEN0_FGSRCSHTOTAL; /**< FrameGen Skew Regulation External Sync HTotal Debug Register, offset: 0x2B00CC */ __I uint32_t DISENG_FRAMEGEN0_FGSRCLOCKDIV; /**< FrameGen Skew Regulation External PLL Clock divider, offset: 0x2B00D0 */ __I uint32_t DISENG_FRAMEGEN0_FGSL; /**< FrameGen Scanline Register, offset: 0x2B00D4 */ uint8_t RESERVED_135[65320]; __O uint32_t DISENG_IDHASH0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2C0000 */ __I uint32_t DISENG_IDHASH0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2C0004 */ __IO uint32_t DISENG_IDHASH0_STATICCONTROL; /**< Global configuration, offset: 0x2C0008 */ __IO uint32_t DISENG_IDHASH0_PANICTHRESHOLD; /**< Set and reset thresholds applying to Window_Panic interrupts and status bits, offset: 0x2C000C */ __IO uint32_t DISENG_IDHASH0_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode, offset: 0x2C0010 */ __IO uint32_t DISENG_IDHASH0_SHADOWLOAD; /**< Shadow load control register, offset: 0x2C0014 */ __IO uint32_t DISENG_IDHASH0_CONTINUOUSMODE; /**< Idhash operation mode control, offset: 0x2C0018 */ __I uint32_t DISENG_IDHASH0_IDHASH_STATUS; /**< Idhash status, offset: 0x2C001C */ __IO uint32_t DISENG_IDHASH0_RUN_STATUS; /**< Idhash evaluation status, offset: 0x2C0020 */ __IO uint32_t DISENG_IDHASH0_CONTROL_WINDOW0; /**< Window 0, Control settings, offset: 0x2C0024 */ __IO uint32_t DISENG_IDHASH0_UPPERLEFT_WINDOW0; /**< Window 0, Upper Left Coordinates, offset: 0x2C0028 */ __IO uint32_t DISENG_IDHASH0_LOWERRIGHT_WINDOW0; /**< Window 0, Lower Right Coordinates, offset: 0x2C002C */ __IO uint32_t DISENG_IDHASH0_TILE_WINDOW0; /**< Window 0, Tile dimensions, offset: 0x2C0030 */ __IO uint32_t DISENG_IDHASH0_ADDRESS_WINDOW0; /**< Window 0, Memory word Address for Idhash, offset: 0x2C0034 */ __IO uint32_t DISENG_IDHASH0_CONFIG_WINDOW0; /**< Window 0, Idhash Configuration settings, offset: 0x2C0038 */ __IO uint32_t DISENG_IDHASH0_LIMITS_WINDOW0; /**< Window 0, check Limit settings, offset: 0x2C003C */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_WINDOW0; /**< Window 0, Foregound 0 Color settings. Used for Telltale mode and Icon Mode., offset: 0x2C0040 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0; /**< Window 0, check Limit settings for Telltale mode or for foreground color 0 in icon mode., offset: 0x2C0044 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_WINDOW0; /**< Window 0, Foregound 1 Color settings, Used for Icon Mode., offset: 0x2C0048 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0; /**< Window 0, check Limit settings for foreground color 1 in icon mode., offset: 0x2C004C */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_WINDOW0; /**< Window 0, Foregound 2 Color settings, offset: 0x2C0050 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0; /**< Window 0, check Limit settings for foreground color 2 in icon mode., offset: 0x2C0054 */ __IO uint32_t DISENG_IDHASH0_IDX_TABLE_WINDOW0; /**< Window 0, Index Table, offset: 0x2C0058 */ __IO uint32_t DISENG_IDHASH0_CONTROL_WINDOW1; /**< Window 1, Control settings, offset: 0x2C005C */ __IO uint32_t DISENG_IDHASH0_UPPERLEFT_WINDOW1; /**< Window 1, Upper Left Coordinates, offset: 0x2C0060 */ __IO uint32_t DISENG_IDHASH0_LOWERRIGHT_WINDOW1; /**< Window 1, Lower Right Coordinates, offset: 0x2C0064 */ __IO uint32_t DISENG_IDHASH0_TILE_WINDOW1; /**< Window 1, Tile dimensions, offset: 0x2C0068 */ __IO uint32_t DISENG_IDHASH0_ADDRESS_WINDOW1; /**< Window 1, Memory word Address for Idhash, offset: 0x2C006C */ __IO uint32_t DISENG_IDHASH0_CONFIG_WINDOW1; /**< Window 1, Idhash Configuration settings, offset: 0x2C0070 */ __IO uint32_t DISENG_IDHASH0_LIMITS_WINDOW1; /**< Window 1, check Limit settings, offset: 0x2C0074 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_WINDOW1; /**< Window 1, Foregound 0 Color settings. Used for Telltale mode and Icon Mode., offset: 0x2C0078 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1; /**< Window 1, check Limit settings for Telltale mode or for foreground color 0 in icon mode., offset: 0x2C007C */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_WINDOW1; /**< Window 1, Foregound 1 Color settings, Used for Icon Mode., offset: 0x2C0080 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1; /**< Window 1, check Limit settings for foreground color 1 in icon mode., offset: 0x2C0084 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_WINDOW1; /**< Window 1, Foregound 2 Color settings, offset: 0x2C0088 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1; /**< Window 1, check Limit settings for foreground color 2 in icon mode., offset: 0x2C008C */ __IO uint32_t DISENG_IDHASH0_IDX_TABLE_WINDOW1; /**< Window 1, Index Table, offset: 0x2C0090 */ __IO uint32_t DISENG_IDHASH0_CONTROL_WINDOW2; /**< Window 2, Control settings, offset: 0x2C0094 */ __IO uint32_t DISENG_IDHASH0_UPPERLEFT_WINDOW2; /**< Window 2, Upper Left Coordinates, offset: 0x2C0098 */ __IO uint32_t DISENG_IDHASH0_LOWERRIGHT_WINDOW2; /**< Window 2, Lower Right Coordinates, offset: 0x2C009C */ __IO uint32_t DISENG_IDHASH0_TILE_WINDOW2; /**< Window 2, Tile dimensions, offset: 0x2C00A0 */ __IO uint32_t DISENG_IDHASH0_ADDRESS_WINDOW2; /**< Window 2, Memory word Address for Idhash, offset: 0x2C00A4 */ __IO uint32_t DISENG_IDHASH0_CONFIG_WINDOW2; /**< Window 2, Idhash Configuration settings, offset: 0x2C00A8 */ __IO uint32_t DISENG_IDHASH0_LIMITS_WINDOW2; /**< Window 2, check Limit settings, offset: 0x2C00AC */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_WINDOW2; /**< Window 2, Foregound 0 Color settings. Used for Telltale mode and Icon Mode., offset: 0x2C00B0 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2; /**< Window 2, check Limit settings for Telltale mode or for foreground color 0 in icon mode., offset: 0x2C00B4 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_WINDOW2; /**< Window 2, Foregound 1 Color settings, Used for Icon Mode., offset: 0x2C00B8 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2; /**< Window 2, check Limit settings for foreground color 1 in icon mode., offset: 0x2C00BC */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_WINDOW2; /**< Window 2, Foregound 2 Color settings, offset: 0x2C00C0 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2; /**< Window 2, check Limit settings for foreground color 2 in icon mode., offset: 0x2C00C4 */ __IO uint32_t DISENG_IDHASH0_IDX_TABLE_WINDOW2; /**< Window 2, Index Table, offset: 0x2C00C8 */ __IO uint32_t DISENG_IDHASH0_CONTROL_WINDOW3; /**< Window 3, Control settings, offset: 0x2C00CC */ __IO uint32_t DISENG_IDHASH0_UPPERLEFT_WINDOW3; /**< Window 3, Upper Left Coordinates, offset: 0x2C00D0 */ __IO uint32_t DISENG_IDHASH0_LOWERRIGHT_WINDOW3; /**< Window 3, Lower Right Coordinates, offset: 0x2C00D4 */ __IO uint32_t DISENG_IDHASH0_TILE_WINDOW3; /**< Window 3, Tile dimensions, offset: 0x2C00D8 */ __IO uint32_t DISENG_IDHASH0_ADDRESS_WINDOW3; /**< Window 3, Memory word Address for Idhash, offset: 0x2C00DC */ __IO uint32_t DISENG_IDHASH0_CONFIG_WINDOW3; /**< Window 3, Idhash Configuration settings, offset: 0x2C00E0 */ __IO uint32_t DISENG_IDHASH0_LIMITS_WINDOW3; /**< Window 3, check Limit settings, offset: 0x2C00E4 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_WINDOW3; /**< Window 3, Foregound 0 Color settings. Used for Telltale mode and Icon Mode., offset: 0x2C00E8 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3; /**< Window 3, check Limit settings for Telltale mode or for foreground color 0 in icon mode., offset: 0x2C00EC */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_WINDOW3; /**< Window 3, Foregound 1 Color settings, Used for Icon Mode., offset: 0x2C00F0 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3; /**< Window 3, check Limit settings for foreground color 1 in icon mode., offset: 0x2C00F4 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_WINDOW3; /**< Window 3, Foregound 2 Color settings, offset: 0x2C00F8 */ __IO uint32_t DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3; /**< Window 3, check Limit settings for foreground color 2 in icon mode., offset: 0x2C00FC */ __IO uint32_t DISENG_IDHASH0_IDX_TABLE_WINDOW3; /**< Window 3, Index Table, offset: 0x2C0100 */ uint8_t RESERVED_136[3836]; __IO uint32_t DISENG_IDHASH0_IDRAM[1024]; /**< SRAM, usage according to module register setup., array offset: 0x2C1000, array step: 0x4 */ uint8_t RESERVED_137[4096]; __O uint32_t DISENG_IDHASH0CFG_LOCKUNLOCK0; /**< Register to change the protection status of this address block., offset: 0x2C3000 */ __I uint32_t DISENG_IDHASH0CFG_LOCKSTATUS0; /**< Protection status of this address block., offset: 0x2C3004 */ __IO uint32_t DISENG_IDHASH0CFG_SRCSELECT; /**< Tap selection for IDHash0., offset: 0x2C3008 */ uint8_t RESERVED_138[53236]; __O uint32_t DISENG_SIG0_LOCKUNLOCK; /**< Register to change the protection status of this address block, offset: 0x2D0000 */ __I uint32_t DISENG_SIG0_LOCKSTATUS; /**< Protection status of this address block, offset: 0x2D0004 */ __IO uint32_t DISENG_SIG0_STATICCONTROL; /**< Global configuration, offset: 0x2D0008 */ __IO uint32_t DISENG_SIG0_ERRORTHRESHOLD; /**< Set and reset thresholds applying to Window_Error and Cluster_Error interrupts and status bits, offset: 0x2D000C */ __IO uint32_t DISENG_SIG0_MATCHTHRESHOLD; /**< Set and reset thresholds applying to Match interrupt and status bits, offset: 0x2D0010 */ __IO uint32_t DISENG_SIG0_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode, offset: 0x2D0014 */ __IO uint32_t DISENG_SIG0_SHADOWLOAD; /**< Shadow load control register, offset: 0x2D0018 */ __IO uint32_t DISENG_SIG0_CONTINUOUSMODE; /**< Signature operation mode control, offset: 0x2D001C */ __O uint32_t DISENG_SIG0_SOFTWAREKICK; /**< Signature measurement trigger, offset: 0x2D0020 */ __IO uint32_t DISENG_SIG0_SKIPWINDOW; /**< Enable skipping window feature., offset: 0x2D0024 */ __I uint32_t DISENG_SIG0_STATUS; /**< Signature evaluation status, offset: 0x2D0028 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW0; /**< Window 0, Control settings, offset: 0x2D002C */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW0; /**< Window 0, Upper Left Coordinates, offset: 0x2D0030 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW0; /**< Window 0, Lower Right Coordinates, offset: 0x2D0034 */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW0; /**< Window 0, Reference CRC Value of Red Channel, offset: 0x2D0038 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW0; /**< Window 0, Reference CRC Value of Green Channel, offset: 0x2D003C */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW0; /**< Window 0, Reference CRC Value of Blue Channel, offset: 0x2D0040 */ __IO uint32_t DISENG_SIG0_STATS0_WINDOW0; /**< Controls of Statistics Block 0, Window 0, offset: 0x2D0044 */ __IO uint32_t DISENG_SIG0_STATS1_WINDOW0; /**< Controls of Statistics Block 0, Window 0, offset: 0x2D0048 */ __IO uint32_t DISENG_SIG0_MIN_REDSUM_WINDOW0; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2D004C */ __IO uint32_t DISENG_SIG0_MIN_GREENSUM_WINDOW0; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2D0050 */ __IO uint32_t DISENG_SIG0_MIN_BLUESUM_WINDOW0; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2D0054 */ __IO uint32_t DISENG_SIG0_MIN_LUMSUM_WINDOW0; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2D0058 */ __IO uint32_t DISENG_SIG0_MAX_REDSUM_WINDOW0; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2D005C */ __IO uint32_t DISENG_SIG0_MAX_GREENSUM_WINDOW0; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2D0060 */ __IO uint32_t DISENG_SIG0_MAX_BLUESUM_WINDOW0; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2D0064 */ __IO uint32_t DISENG_SIG0_MAX_LUMSUM_WINDOW0; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2D0068 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW1; /**< Window 1, Control settings, offset: 0x2D006C */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW1; /**< Window 1, Upper Left Coordinates, offset: 0x2D0070 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW1; /**< Window 1, Lower Right Coordinates, offset: 0x2D0074 */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW1; /**< Window 1, Reference CRC Value of Red Channel, offset: 0x2D0078 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW1; /**< Window 1, Reference CRC Value of Green Channel, offset: 0x2D007C */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW1; /**< Window 1, Reference CRC Value of Blue Channel, offset: 0x2D0080 */ __IO uint32_t DISENG_SIG0_STATS0_WINDOW1; /**< Controls of Statistics Block 0, Window 1, offset: 0x2D0084 */ __IO uint32_t DISENG_SIG0_STATS1_WINDOW1; /**< Controls of Statistics Block 0, Window 1, offset: 0x2D0088 */ __IO uint32_t DISENG_SIG0_MIN_REDSUM_WINDOW1; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2D008C */ __IO uint32_t DISENG_SIG0_MIN_GREENSUM_WINDOW1; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2D0090 */ __IO uint32_t DISENG_SIG0_MIN_BLUESUM_WINDOW1; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2D0094 */ __IO uint32_t DISENG_SIG0_MIN_LUMSUM_WINDOW1; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2D0098 */ __IO uint32_t DISENG_SIG0_MAX_REDSUM_WINDOW1; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2D009C */ __IO uint32_t DISENG_SIG0_MAX_GREENSUM_WINDOW1; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2D00A0 */ __IO uint32_t DISENG_SIG0_MAX_BLUESUM_WINDOW1; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2D00A4 */ __IO uint32_t DISENG_SIG0_MAX_LUMSUM_WINDOW1; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2D00A8 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW2; /**< Window 2, Control settings, offset: 0x2D00AC */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW2; /**< Window 2, Upper Left Coordinates, offset: 0x2D00B0 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW2; /**< Window 2, Lower Right Coordinates, offset: 0x2D00B4 */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW2; /**< Window 2, Reference CRC Value of Red Channel, offset: 0x2D00B8 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW2; /**< Window 2, Reference CRC Value of Green Channel, offset: 0x2D00BC */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW2; /**< Window 2, Reference CRC Value of Blue Channel, offset: 0x2D00C0 */ __IO uint32_t DISENG_SIG0_STATS0_WINDOW2; /**< Controls of Statistics Block 0, Window 2, offset: 0x2D00C4 */ __IO uint32_t DISENG_SIG0_STATS1_WINDOW2; /**< Controls of Statistics Block 0, Window 2, offset: 0x2D00C8 */ __IO uint32_t DISENG_SIG0_MIN_REDSUM_WINDOW2; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2D00CC */ __IO uint32_t DISENG_SIG0_MIN_GREENSUM_WINDOW2; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2D00D0 */ __IO uint32_t DISENG_SIG0_MIN_BLUESUM_WINDOW2; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2D00D4 */ __IO uint32_t DISENG_SIG0_MIN_LUMSUM_WINDOW2; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2D00D8 */ __IO uint32_t DISENG_SIG0_MAX_REDSUM_WINDOW2; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2D00DC */ __IO uint32_t DISENG_SIG0_MAX_GREENSUM_WINDOW2; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2D00E0 */ __IO uint32_t DISENG_SIG0_MAX_BLUESUM_WINDOW2; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2D00E4 */ __IO uint32_t DISENG_SIG0_MAX_LUMSUM_WINDOW2; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2D00E8 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW3; /**< Window 3, Control settings, offset: 0x2D00EC */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW3; /**< Window 3, Upper Left Coordinates, offset: 0x2D00F0 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW3; /**< Window 3, Lower Right Coordinates, offset: 0x2D00F4 */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW3; /**< Window 3, Reference CRC Value of Red Channel, offset: 0x2D00F8 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW3; /**< Window 3, Reference CRC Value of Green Channel, offset: 0x2D00FC */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW3; /**< Window 3, Reference CRC Value of Blue Channel, offset: 0x2D0100 */ __IO uint32_t DISENG_SIG0_STATS0_WINDOW3; /**< Controls of Statistics Block 0, Window 3, offset: 0x2D0104 */ __IO uint32_t DISENG_SIG0_STATS1_WINDOW3; /**< Controls of Statistics Block 0, Window 3, offset: 0x2D0108 */ __IO uint32_t DISENG_SIG0_MIN_REDSUM_WINDOW3; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2D010C */ __IO uint32_t DISENG_SIG0_MIN_GREENSUM_WINDOW3; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2D0110 */ __IO uint32_t DISENG_SIG0_MIN_BLUESUM_WINDOW3; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2D0114 */ __IO uint32_t DISENG_SIG0_MIN_LUMSUM_WINDOW3; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2D0118 */ __IO uint32_t DISENG_SIG0_MAX_REDSUM_WINDOW3; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2D011C */ __IO uint32_t DISENG_SIG0_MAX_GREENSUM_WINDOW3; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2D0120 */ __IO uint32_t DISENG_SIG0_MAX_BLUESUM_WINDOW3; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2D0124 */ __IO uint32_t DISENG_SIG0_MAX_LUMSUM_WINDOW3; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2D0128 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW4; /**< Window 4, Control settings, offset: 0x2D012C */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW4; /**< Window 4, Upper Left Coordinates, offset: 0x2D0130 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW4; /**< Window 4, Lower Right Coordinates, offset: 0x2D0134 */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW4; /**< Window 4, Reference CRC Value of Red Channel, offset: 0x2D0138 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW4; /**< Window 4, Reference CRC Value of Green Channel, offset: 0x2D013C */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW4; /**< Window 4, Reference CRC Value of Blue Channel, offset: 0x2D0140 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW5; /**< Window 5, Control settings, offset: 0x2D0144 */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW5; /**< Window 5, Upper Left Coordinates, offset: 0x2D0148 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW5; /**< Window 5, Lower Right Coordinates, offset: 0x2D014C */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW5; /**< Window 5, Reference CRC Value of Red Channel, offset: 0x2D0150 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW5; /**< Window 5, Reference CRC Value of Green Channel, offset: 0x2D0154 */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW5; /**< Window 5, Reference CRC Value of Blue Channel, offset: 0x2D0158 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW6; /**< Window 6, Control settings, offset: 0x2D015C */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW6; /**< Window 6, Upper Left Coordinates, offset: 0x2D0160 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW6; /**< Window 6, Lower Right Coordinates, offset: 0x2D0164 */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW6; /**< Window 6, Reference CRC Value of Red Channel, offset: 0x2D0168 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW6; /**< Window 6, Reference CRC Value of Green Channel, offset: 0x2D016C */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW6; /**< Window 6, Reference CRC Value of Blue Channel, offset: 0x2D0170 */ __IO uint32_t DISENG_SIG0_CONTROL_WINDOW7; /**< Window 7, Control settings, offset: 0x2D0174 */ __IO uint32_t DISENG_SIG0_UPPERLEFT_WINDOW7; /**< Window 7, Upper Left Coordinates, offset: 0x2D0178 */ __IO uint32_t DISENG_SIG0_LOWERRIGHT_WINDOW7; /**< Window 7, Lower Right Coordinates, offset: 0x2D017C */ __IO uint32_t DISENG_SIG0_REF_R_WINDOW7; /**< Window 7, Reference CRC Value of Red Channel, offset: 0x2D0180 */ __IO uint32_t DISENG_SIG0_REF_G_WINDOW7; /**< Window 7, Reference CRC Value of Green Channel, offset: 0x2D0184 */ __IO uint32_t DISENG_SIG0_REF_B_WINDOW7; /**< Window 7, Reference CRC Value of Blue Channel, offset: 0x2D0188 */ __IO uint32_t DISENG_SIG0_CONTROL_CLUSTER0; /**< Cluster 0, Control settings, offset: 0x2D018C */ __IO uint32_t DISENG_SIG0_PIX0_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 0, offset: 0x2D0190 */ __IO uint32_t DISENG_SIG0_PIX1_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 1, offset: 0x2D0194 */ __IO uint32_t DISENG_SIG0_PIX2_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 2, offset: 0x2D0198 */ __IO uint32_t DISENG_SIG0_PIX3_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 3, offset: 0x2D019C */ __IO uint32_t DISENG_SIG0_REF0_CLUSTER0; /**< Cluster 0, Reference Vector 0, offset: 0x2D01A0 */ __IO uint32_t DISENG_SIG0_REF1_CLUSTER0; /**< Cluster 0, Reference Vector 1, offset: 0x2D01A4 */ __IO uint32_t DISENG_SIG0_CONTROL_CLUSTER1; /**< Cluster 1, Control settings, offset: 0x2D01A8 */ __IO uint32_t DISENG_SIG0_PIX0_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 0, offset: 0x2D01AC */ __IO uint32_t DISENG_SIG0_PIX1_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 1, offset: 0x2D01B0 */ __IO uint32_t DISENG_SIG0_PIX2_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 2, offset: 0x2D01B4 */ __IO uint32_t DISENG_SIG0_PIX3_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 3, offset: 0x2D01B8 */ __IO uint32_t DISENG_SIG0_REF0_CLUSTER1; /**< Cluster 1, Reference Vector 0, offset: 0x2D01BC */ __IO uint32_t DISENG_SIG0_REF1_CLUSTER1; /**< Cluster 1, Reference Vector 1, offset: 0x2D01C0 */ __IO uint32_t DISENG_SIG0_CONTROL_CLUSTER2; /**< Cluster 2, Control settings, offset: 0x2D01C4 */ __IO uint32_t DISENG_SIG0_PIX0_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 0, offset: 0x2D01C8 */ __IO uint32_t DISENG_SIG0_PIX1_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 1, offset: 0x2D01CC */ __IO uint32_t DISENG_SIG0_PIX2_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 2, offset: 0x2D01D0 */ __IO uint32_t DISENG_SIG0_PIX3_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 3, offset: 0x2D01D4 */ __IO uint32_t DISENG_SIG0_REF0_CLUSTER2; /**< Cluster 2, Reference Vector 0, offset: 0x2D01D8 */ __IO uint32_t DISENG_SIG0_REF1_CLUSTER2; /**< Cluster 2, Reference Vector 1, offset: 0x2D01DC */ __IO uint32_t DISENG_SIG0_CONTROL_CLUSTER3; /**< Cluster 3, Control settings, offset: 0x2D01E0 */ __IO uint32_t DISENG_SIG0_PIX0_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 0, offset: 0x2D01E4 */ __IO uint32_t DISENG_SIG0_PIX1_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 1, offset: 0x2D01E8 */ __IO uint32_t DISENG_SIG0_PIX2_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 2, offset: 0x2D01EC */ __IO uint32_t DISENG_SIG0_PIX3_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 3, offset: 0x2D01F0 */ __IO uint32_t DISENG_SIG0_REF0_CLUSTER3; /**< Cluster 3, Reference Vector 0, offset: 0x2D01F4 */ __IO uint32_t DISENG_SIG0_REF1_CLUSTER3; /**< Cluster 3, Reference Vector 1, offset: 0x2D01F8 */ uint8_t RESERVED_139[516]; __I uint32_t DISENG_SIG0_CRC_R_WINDOW0; /**< Window 0, Measured CRC Value of Red Channel, offset: 0x2D0400 */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW0; /**< Window 0, Measured CRC Value of Green Channel, offset: 0x2D0404 */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW0; /**< Window 0, Measured CRC Value of Blue Channel, offset: 0x2D0408 */ __I uint32_t DISENG_SIG0_CRC_R_WINDOW1; /**< Window 1, Measured CRC Value of Red Channel, offset: 0x2D040C */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW1; /**< Window 1, Measured CRC Value of Green Channel, offset: 0x2D0410 */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW1; /**< Window 1, Measured CRC Value of Blue Channel, offset: 0x2D0414 */ __I uint32_t DISENG_SIG0_CRC_R_WINDOW2; /**< Window 2, Measured CRC Value of Red Channel, offset: 0x2D0418 */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW2; /**< Window 2, Measured CRC Value of Green Channel, offset: 0x2D041C */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW2; /**< Window 2, Measured CRC Value of Blue Channel, offset: 0x2D0420 */ __I uint32_t DISENG_SIG0_CRC_R_WINDOW3; /**< Window 3, Measured CRC Value of Red Channel, offset: 0x2D0424 */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW3; /**< Window 3, Measured CRC Value of Green Channel, offset: 0x2D0428 */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW3; /**< Window 3, Measured CRC Value of Blue Channel, offset: 0x2D042C */ __I uint32_t DISENG_SIG0_CRC_R_WINDOW4; /**< Window 4, Measured CRC Value of Red Channel, offset: 0x2D0430 */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW4; /**< Window 4, Measured CRC Value of Green Channel, offset: 0x2D0434 */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW4; /**< Window 4, Measured CRC Value of Blue Channel, offset: 0x2D0438 */ __I uint32_t DISENG_SIG0_CRC_R_WINDOW5; /**< Window 5, Measured CRC Value of Red Channel, offset: 0x2D043C */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW5; /**< Window 5, Measured CRC Value of Green Channel, offset: 0x2D0440 */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW5; /**< Window 5, Measured CRC Value of Blue Channel, offset: 0x2D0444 */ __I uint32_t DISENG_SIG0_CRC_R_WINDOW6; /**< Window 6, Measured CRC Value of Red Channel, offset: 0x2D0448 */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW6; /**< Window 6, Measured CRC Value of Green Channel, offset: 0x2D044C */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW6; /**< Window 6, Measured CRC Value of Blue Channel, offset: 0x2D0450 */ __I uint32_t DISENG_SIG0_CRC_R_WINDOW7; /**< Window 7, Measured CRC Value of Red Channel, offset: 0x2D0454 */ __I uint32_t DISENG_SIG0_CRC_G_WINDOW7; /**< Window 7, Measured CRC Value of Green Channel, offset: 0x2D0458 */ __I uint32_t DISENG_SIG0_CRC_B_WINDOW7; /**< Window 7, Measured CRC Value of Blue Channel, offset: 0x2D045C */ __I uint32_t DISENG_SIG0_STATUS_CLUSTER0; /**< Cluster 0, Status, offset: 0x2D0460 */ __I uint32_t DISENG_SIG0_COUNTER_CLUSTER0; /**< Cluster 0, Match and Error Counters, offset: 0x2D0464 */ __I uint32_t DISENG_SIG0_VECTOR0_CLUSTER0; /**< Cluster 0, Result Vector 0, RGB bitslices[1:0], offset: 0x2D0468 */ __I uint32_t DISENG_SIG0_VECTOR1_CLUSTER0; /**< Cluster 0, Result Vector 1, RGB bitslices[3:2], offset: 0x2D046C */ __I uint32_t DISENG_SIG0_VECTOR2_CLUSTER0; /**< Cluster 0, Result Vector 2, RGB bitslices[5:4], offset: 0x2D0470 */ __I uint32_t DISENG_SIG0_VECTOR3_CLUSTER0; /**< Cluster 0, Result Vector 3, RGB bitslices[7:6], offset: 0x2D0474 */ __I uint32_t DISENG_SIG0_STATUS_CLUSTER1; /**< Cluster 1, Status, offset: 0x2D0478 */ __I uint32_t DISENG_SIG0_COUNTER_CLUSTER1; /**< Cluster 1, Match and Error Counters, offset: 0x2D047C */ __I uint32_t DISENG_SIG0_VECTOR0_CLUSTER1; /**< Cluster 1, Result Vector 0, RGB bitslices[1:0], offset: 0x2D0480 */ __I uint32_t DISENG_SIG0_VECTOR1_CLUSTER1; /**< Cluster 1, Result Vector 1, RGB bitslices[3:2], offset: 0x2D0484 */ __I uint32_t DISENG_SIG0_VECTOR2_CLUSTER1; /**< Cluster 1, Result Vector 2, RGB bitslices[5:4], offset: 0x2D0488 */ __I uint32_t DISENG_SIG0_VECTOR3_CLUSTER1; /**< Cluster 1, Result Vector 3, RGB bitslices[7:6], offset: 0x2D048C */ __I uint32_t DISENG_SIG0_STATUS_CLUSTER2; /**< Cluster 2, Status, offset: 0x2D0490 */ __I uint32_t DISENG_SIG0_COUNTER_CLUSTER2; /**< Cluster 2, Match and Error Counters, offset: 0x2D0494 */ __I uint32_t DISENG_SIG0_VECTOR0_CLUSTER2; /**< Cluster 2, Result Vector 0, RGB bitslices[1:0], offset: 0x2D0498 */ __I uint32_t DISENG_SIG0_VECTOR1_CLUSTER2; /**< Cluster 2, Result Vector 1, RGB bitslices[3:2], offset: 0x2D049C */ __I uint32_t DISENG_SIG0_VECTOR2_CLUSTER2; /**< Cluster 2, Result Vector 2, RGB bitslices[5:4], offset: 0x2D04A0 */ __I uint32_t DISENG_SIG0_VECTOR3_CLUSTER2; /**< Cluster 2, Result Vector 3, RGB bitslices[7:6], offset: 0x2D04A4 */ __I uint32_t DISENG_SIG0_STATUS_CLUSTER3; /**< Cluster 3, Status, offset: 0x2D04A8 */ __I uint32_t DISENG_SIG0_COUNTER_CLUSTER3; /**< Cluster 3, Match and Error Counters, offset: 0x2D04AC */ __I uint32_t DISENG_SIG0_VECTOR0_CLUSTER3; /**< Cluster 3, Result Vector 0, RGB bitslices[1:0], offset: 0x2D04B0 */ __I uint32_t DISENG_SIG0_VECTOR1_CLUSTER3; /**< Cluster 3, Result Vector 1, RGB bitslices[3:2], offset: 0x2D04B4 */ __I uint32_t DISENG_SIG0_VECTOR2_CLUSTER3; /**< Cluster 3, Result Vector 2, RGB bitslices[5:4], offset: 0x2D04B8 */ __I uint32_t DISENG_SIG0_VECTOR3_CLUSTER3; /**< Cluster 3, Result Vector 3, RGB bitslices[7:6], offset: 0x2D04BC */ __I uint32_t DISENG_SIG0_PIXCNT_STATS0_WIN0; /**< Pixel Counter Register, Statistics Block 0, Window 0, offset: 0x2D04C0 */ __I uint32_t DISENG_SIG0_PIXMAX_STATS0_WIN0; /**< Pixel Max Values Register, Statistics Block 0, Window 0, offset: 0x2D04C4 */ __I uint32_t DISENG_SIG0_PIXMIN_STATS0_WIN0; /**< Pixel Min Values Register, Statistics Block 0, Window 0, offset: 0x2D04C8 */ __I uint32_t DISENG_SIG0_REDSUM_STATS0_WIN0; /**< Red Component Sum Register, Statistics Block 0, Window 0, offset: 0x2D04CC */ __I uint32_t DISENG_SIG0_GREENSUM_STATS0_WIN0; /**< Green Component Sum Register, Statistics Block 0, Window 0, offset: 0x2D04D0 */ __I uint32_t DISENG_SIG0_BLUESUM_STATS0_WIN0; /**< Blue Component Sum Register, Statistics Block 0, Window 0, offset: 0x2D04D4 */ __I uint32_t DISENG_SIG0_LUMSUM_STATS0_WIN0; /**< Luminance Sum Register, Statistics Block 0, Window 0, offset: 0x2D04D8 */ __I uint32_t DISENG_SIG0_PIXCNT_STATS1_WIN0; /**< Pixel Counter Register, Statistics Block 1, Window 0, offset: 0x2D04DC */ __I uint32_t DISENG_SIG0_PIXMAX_STATS1_WIN0; /**< Pixel Max Values Register, Statistics Block 1, Window 0, offset: 0x2D04E0 */ __I uint32_t DISENG_SIG0_PIXMIN_STATS1_WIN0; /**< Pixel Min Values Register, Statistics Block 1, Window 0, offset: 0x2D04E4 */ __I uint32_t DISENG_SIG0_REDSUM_STATS1_WIN0; /**< Red Component Sum Register, Statistics Block 1, Window 0, offset: 0x2D04E8 */ __I uint32_t DISENG_SIG0_GREENSUM_STATS1_WIN0; /**< Green Component Sum Register, Statistics Block 1, Window 0, offset: 0x2D04EC */ __I uint32_t DISENG_SIG0_BLUESUM_STATS1_WIN0; /**< Blue Component Sum Register, Statistics Block 1, Window 0, offset: 0x2D04F0 */ __I uint32_t DISENG_SIG0_PIXCNT_STATS0_WIN1; /**< Pixel Counter Register, Statistics Block 0, Window 1, offset: 0x2D04F4 */ __I uint32_t DISENG_SIG0_PIXMAX_STATS0_WIN1; /**< Pixel Max Values Register, Statistics Block 0, Window 1, offset: 0x2D04F8 */ __I uint32_t DISENG_SIG0_PIXMIN_STATS0_WIN1; /**< Pixel Min Values Register, Statistics Block 0, Window 1, offset: 0x2D04FC */ __I uint32_t DISENG_SIG0_REDSUM_STATS0_WIN1; /**< Red Component Sum Register, Statistics Block 0, Window 1, offset: 0x2D0500 */ __I uint32_t DISENG_SIG0_GREENSUM_STATS0_WIN1; /**< Green Component Sum Register, Statistics Block 0, Window 1, offset: 0x2D0504 */ __I uint32_t DISENG_SIG0_BLUESUM_STATS0_WIN1; /**< Blue Component Sum Register, Statistics Block 0, Window 1, offset: 0x2D0508 */ __I uint32_t DISENG_SIG0_LUMSUM_STATS0_WIN1; /**< Luminance Sum Register, Statistics Block 0, Window 1, offset: 0x2D050C */ __I uint32_t DISENG_SIG0_PIXCNT_STATS1_WIN1; /**< Pixel Counter Register, Statistics Block 1, Window 1, offset: 0x2D0510 */ __I uint32_t DISENG_SIG0_PIXMAX_STATS1_WIN1; /**< Pixel Max Values Register, Statistics Block 1, Window 1, offset: 0x2D0514 */ __I uint32_t DISENG_SIG0_PIXMIN_STATS1_WIN1; /**< Pixel Min Values Register, Statistics Block 1, Window 1, offset: 0x2D0518 */ __I uint32_t DISENG_SIG0_REDSUM_STATS1_WIN1; /**< Red Component Sum Register, Statistics Block 1, Window 1, offset: 0x2D051C */ __I uint32_t DISENG_SIG0_GREENSUM_STATS1_WIN1; /**< Green Component Sum Register, Statistics Block 1, Window 1, offset: 0x2D0520 */ __I uint32_t DISENG_SIG0_BLUESUM_STATS1_WIN1; /**< Blue Component Sum Register, Statistics Block 1, Window 1, offset: 0x2D0524 */ __I uint32_t DISENG_SIG0_PIXCNT_STATS0_WIN2; /**< Pixel Counter Register, Statistics Block 0, Window 2, offset: 0x2D0528 */ __I uint32_t DISENG_SIG0_PIXMAX_STATS0_WIN2; /**< Pixel Max Values Register, Statistics Block 0, Window 2, offset: 0x2D052C */ __I uint32_t DISENG_SIG0_PIXMIN_STATS0_WIN2; /**< Pixel Min Values Register, Statistics Block 0, Window 2, offset: 0x2D0530 */ __I uint32_t DISENG_SIG0_REDSUM_STATS0_WIN2; /**< Red Component Sum Register, Statistics Block 0, Window 2, offset: 0x2D0534 */ __I uint32_t DISENG_SIG0_GREENSUM_STATS0_WIN2; /**< Green Component Sum Register, Statistics Block 0, Window 2, offset: 0x2D0538 */ __I uint32_t DISENG_SIG0_BLUESUM_STATS0_WIN2; /**< Blue Component Sum Register, Statistics Block 0, Window 2, offset: 0x2D053C */ __I uint32_t DISENG_SIG0_LUMSUM_STATS0_WIN2; /**< Luminance Sum Register, Statistics Block 0, Window 2, offset: 0x2D0540 */ __I uint32_t DISENG_SIG0_PIXCNT_STATS1_WIN2; /**< Pixel Counter Register, Statistics Block 1, Window 2, offset: 0x2D0544 */ __I uint32_t DISENG_SIG0_PIXMAX_STATS1_WIN2; /**< Pixel Max Values Register, Statistics Block 1, Window 2, offset: 0x2D0548 */ __I uint32_t DISENG_SIG0_PIXMIN_STATS1_WIN2; /**< Pixel Min Values Register, Statistics Block 1, Window 2, offset: 0x2D054C */ __I uint32_t DISENG_SIG0_REDSUM_STATS1_WIN2; /**< Red Component Sum Register, Statistics Block 1, Window 2, offset: 0x2D0550 */ __I uint32_t DISENG_SIG0_GREENSUM_STATS1_WIN2; /**< Green Component Sum Register, Statistics Block 1, Window 2, offset: 0x2D0554 */ __I uint32_t DISENG_SIG0_BLUESUM_STATS1_WIN2; /**< Blue Component Sum Register, Statistics Block 1, Window 2, offset: 0x2D0558 */ __I uint32_t DISENG_SIG0_PIXCNT_STATS0_WIN3; /**< Pixel Counter Register, Statistics Block 0, Window 3, offset: 0x2D055C */ __I uint32_t DISENG_SIG0_PIXMAX_STATS0_WIN3; /**< Pixel Max Values Register, Statistics Block 0, Window 3, offset: 0x2D0560 */ __I uint32_t DISENG_SIG0_PIXMIN_STATS0_WIN3; /**< Pixel Min Values Register, Statistics Block 0, Window 3, offset: 0x2D0564 */ __I uint32_t DISENG_SIG0_REDSUM_STATS0_WIN3; /**< Red Component Sum Register, Statistics Block 0, Window 3, offset: 0x2D0568 */ __I uint32_t DISENG_SIG0_GREENSUM_STATS0_WIN3; /**< Green Component Sum Register, Statistics Block 0, Window 3, offset: 0x2D056C */ __I uint32_t DISENG_SIG0_BLUESUM_STATS0_WIN3; /**< Blue Component Sum Register, Statistics Block 0, Window 3, offset: 0x2D0570 */ __I uint32_t DISENG_SIG0_LUMSUM_STATS0_WIN3; /**< Luminance Sum Register, Statistics Block 0, Window 3, offset: 0x2D0574 */ __I uint32_t DISENG_SIG0_PIXCNT_STATS1_WIN3; /**< Pixel Counter Register, Statistics Block 1, Window 3, offset: 0x2D0578 */ __I uint32_t DISENG_SIG0_PIXMAX_STATS1_WIN3; /**< Pixel Max Values Register, Statistics Block 1, Window 3, offset: 0x2D057C */ __I uint32_t DISENG_SIG0_PIXMIN_STATS1_WIN3; /**< Pixel Min Values Register, Statistics Block 1, Window 3, offset: 0x2D0580 */ __I uint32_t DISENG_SIG0_REDSUM_STATS1_WIN3; /**< Red Component Sum Register, Statistics Block 1, Window 3, offset: 0x2D0584 */ __I uint32_t DISENG_SIG0_GREENSUM_STATS1_WIN3; /**< Green Component Sum Register, Statistics Block 1, Window 3, offset: 0x2D0588 */ __I uint32_t DISENG_SIG0_BLUESUM_STATS1_WIN3; /**< Blue Component Sum Register, Statistics Block 1, Window 3, offset: 0x2D058C */ uint8_t RESERVED_140[2672]; __O uint32_t DISENG_SIG0CFG_LOCKUNLOCK0; /**< Register to change the protection status of this address block., offset: 0x2D1000 */ __I uint32_t DISENG_SIG0CFG_LOCKSTATUS0; /**< Protection status of this address block., offset: 0x2D1004 */ __IO uint32_t DISENG_SIG0CFG_SRCSELECT; /**< Tap selection for sig0., offset: 0x2D1008 */ uint8_t RESERVED_141[61428]; __O uint32_t DISENG_SIG2_LOCKUNLOCK; /**< Register to change the protection status of this address block, offset: 0x2E0000 */ __I uint32_t DISENG_SIG2_LOCKSTATUS; /**< Protection status of this address block, offset: 0x2E0004 */ __IO uint32_t DISENG_SIG2_STATICCONTROL; /**< Global configuration, offset: 0x2E0008 */ __IO uint32_t DISENG_SIG2_ERRORTHRESHOLD; /**< Set and reset thresholds applying to Window_Error and Cluster_Error interrupts and status bits, offset: 0x2E000C */ __IO uint32_t DISENG_SIG2_MATCHTHRESHOLD; /**< Set and reset thresholds applying to Match interrupt and status bits, offset: 0x2E0010 */ __IO uint32_t DISENG_SIG2_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode, offset: 0x2E0014 */ __IO uint32_t DISENG_SIG2_SHADOWLOAD; /**< Shadow load control register, offset: 0x2E0018 */ __IO uint32_t DISENG_SIG2_CONTINUOUSMODE; /**< Signature operation mode control, offset: 0x2E001C */ __O uint32_t DISENG_SIG2_SOFTWAREKICK; /**< Signature measurement trigger, offset: 0x2E0020 */ __IO uint32_t DISENG_SIG2_SKIPWINDOW; /**< Enable skipping window feature., offset: 0x2E0024 */ __I uint32_t DISENG_SIG2_STATUS; /**< Signature evaluation status, offset: 0x2E0028 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW0; /**< Window 0, Control settings, offset: 0x2E002C */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW0; /**< Window 0, Upper Left Coordinates, offset: 0x2E0030 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW0; /**< Window 0, Lower Right Coordinates, offset: 0x2E0034 */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW0; /**< Window 0, Reference CRC Value of Red Channel, offset: 0x2E0038 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW0; /**< Window 0, Reference CRC Value of Green Channel, offset: 0x2E003C */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW0; /**< Window 0, Reference CRC Value of Blue Channel, offset: 0x2E0040 */ __IO uint32_t DISENG_SIG2_STATS0_WINDOW0; /**< Controls of Statistics Block 0, Window 0, offset: 0x2E0044 */ __IO uint32_t DISENG_SIG2_STATS1_WINDOW0; /**< Controls of Statistics Block 0, Window 0, offset: 0x2E0048 */ __IO uint32_t DISENG_SIG2_MIN_REDSUM_WINDOW0; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2E004C */ __IO uint32_t DISENG_SIG2_MIN_GREENSUM_WINDOW0; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2E0050 */ __IO uint32_t DISENG_SIG2_MIN_BLUESUM_WINDOW0; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2E0054 */ __IO uint32_t DISENG_SIG2_MIN_LUMSUM_WINDOW0; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2E0058 */ __IO uint32_t DISENG_SIG2_MAX_REDSUM_WINDOW0; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2E005C */ __IO uint32_t DISENG_SIG2_MAX_GREENSUM_WINDOW0; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2E0060 */ __IO uint32_t DISENG_SIG2_MAX_BLUESUM_WINDOW0; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2E0064 */ __IO uint32_t DISENG_SIG2_MAX_LUMSUM_WINDOW0; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2E0068 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW1; /**< Window 1, Control settings, offset: 0x2E006C */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW1; /**< Window 1, Upper Left Coordinates, offset: 0x2E0070 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW1; /**< Window 1, Lower Right Coordinates, offset: 0x2E0074 */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW1; /**< Window 1, Reference CRC Value of Red Channel, offset: 0x2E0078 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW1; /**< Window 1, Reference CRC Value of Green Channel, offset: 0x2E007C */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW1; /**< Window 1, Reference CRC Value of Blue Channel, offset: 0x2E0080 */ __IO uint32_t DISENG_SIG2_STATS0_WINDOW1; /**< Controls of Statistics Block 0, Window 1, offset: 0x2E0084 */ __IO uint32_t DISENG_SIG2_STATS1_WINDOW1; /**< Controls of Statistics Block 0, Window 1, offset: 0x2E0088 */ __IO uint32_t DISENG_SIG2_MIN_REDSUM_WINDOW1; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2E008C */ __IO uint32_t DISENG_SIG2_MIN_GREENSUM_WINDOW1; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2E0090 */ __IO uint32_t DISENG_SIG2_MIN_BLUESUM_WINDOW1; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2E0094 */ __IO uint32_t DISENG_SIG2_MIN_LUMSUM_WINDOW1; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2E0098 */ __IO uint32_t DISENG_SIG2_MAX_REDSUM_WINDOW1; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2E009C */ __IO uint32_t DISENG_SIG2_MAX_GREENSUM_WINDOW1; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2E00A0 */ __IO uint32_t DISENG_SIG2_MAX_BLUESUM_WINDOW1; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2E00A4 */ __IO uint32_t DISENG_SIG2_MAX_LUMSUM_WINDOW1; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2E00A8 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW2; /**< Window 2, Control settings, offset: 0x2E00AC */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW2; /**< Window 2, Upper Left Coordinates, offset: 0x2E00B0 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW2; /**< Window 2, Lower Right Coordinates, offset: 0x2E00B4 */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW2; /**< Window 2, Reference CRC Value of Red Channel, offset: 0x2E00B8 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW2; /**< Window 2, Reference CRC Value of Green Channel, offset: 0x2E00BC */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW2; /**< Window 2, Reference CRC Value of Blue Channel, offset: 0x2E00C0 */ __IO uint32_t DISENG_SIG2_STATS0_WINDOW2; /**< Controls of Statistics Block 0, Window 2, offset: 0x2E00C4 */ __IO uint32_t DISENG_SIG2_STATS1_WINDOW2; /**< Controls of Statistics Block 0, Window 2, offset: 0x2E00C8 */ __IO uint32_t DISENG_SIG2_MIN_REDSUM_WINDOW2; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2E00CC */ __IO uint32_t DISENG_SIG2_MIN_GREENSUM_WINDOW2; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2E00D0 */ __IO uint32_t DISENG_SIG2_MIN_BLUESUM_WINDOW2; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2E00D4 */ __IO uint32_t DISENG_SIG2_MIN_LUMSUM_WINDOW2; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2E00D8 */ __IO uint32_t DISENG_SIG2_MAX_REDSUM_WINDOW2; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2E00DC */ __IO uint32_t DISENG_SIG2_MAX_GREENSUM_WINDOW2; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2E00E0 */ __IO uint32_t DISENG_SIG2_MAX_BLUESUM_WINDOW2; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2E00E4 */ __IO uint32_t DISENG_SIG2_MAX_LUMSUM_WINDOW2; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2E00E8 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW3; /**< Window 3, Control settings, offset: 0x2E00EC */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW3; /**< Window 3, Upper Left Coordinates, offset: 0x2E00F0 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW3; /**< Window 3, Lower Right Coordinates, offset: 0x2E00F4 */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW3; /**< Window 3, Reference CRC Value of Red Channel, offset: 0x2E00F8 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW3; /**< Window 3, Reference CRC Value of Green Channel, offset: 0x2E00FC */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW3; /**< Window 3, Reference CRC Value of Blue Channel, offset: 0x2E0100 */ __IO uint32_t DISENG_SIG2_STATS0_WINDOW3; /**< Controls of Statistics Block 0, Window 3, offset: 0x2E0104 */ __IO uint32_t DISENG_SIG2_STATS1_WINDOW3; /**< Controls of Statistics Block 0, Window 3, offset: 0x2E0108 */ __IO uint32_t DISENG_SIG2_MIN_REDSUM_WINDOW3; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x2E010C */ __IO uint32_t DISENG_SIG2_MIN_GREENSUM_WINDOW3; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x2E0110 */ __IO uint32_t DISENG_SIG2_MIN_BLUESUM_WINDOW3; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x2E0114 */ __IO uint32_t DISENG_SIG2_MIN_LUMSUM_WINDOW3; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x2E0118 */ __IO uint32_t DISENG_SIG2_MAX_REDSUM_WINDOW3; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x2E011C */ __IO uint32_t DISENG_SIG2_MAX_GREENSUM_WINDOW3; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x2E0120 */ __IO uint32_t DISENG_SIG2_MAX_BLUESUM_WINDOW3; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x2E0124 */ __IO uint32_t DISENG_SIG2_MAX_LUMSUM_WINDOW3; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x2E0128 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW4; /**< Window 4, Control settings, offset: 0x2E012C */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW4; /**< Window 4, Upper Left Coordinates, offset: 0x2E0130 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW4; /**< Window 4, Lower Right Coordinates, offset: 0x2E0134 */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW4; /**< Window 4, Reference CRC Value of Red Channel, offset: 0x2E0138 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW4; /**< Window 4, Reference CRC Value of Green Channel, offset: 0x2E013C */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW4; /**< Window 4, Reference CRC Value of Blue Channel, offset: 0x2E0140 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW5; /**< Window 5, Control settings, offset: 0x2E0144 */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW5; /**< Window 5, Upper Left Coordinates, offset: 0x2E0148 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW5; /**< Window 5, Lower Right Coordinates, offset: 0x2E014C */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW5; /**< Window 5, Reference CRC Value of Red Channel, offset: 0x2E0150 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW5; /**< Window 5, Reference CRC Value of Green Channel, offset: 0x2E0154 */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW5; /**< Window 5, Reference CRC Value of Blue Channel, offset: 0x2E0158 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW6; /**< Window 6, Control settings, offset: 0x2E015C */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW6; /**< Window 6, Upper Left Coordinates, offset: 0x2E0160 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW6; /**< Window 6, Lower Right Coordinates, offset: 0x2E0164 */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW6; /**< Window 6, Reference CRC Value of Red Channel, offset: 0x2E0168 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW6; /**< Window 6, Reference CRC Value of Green Channel, offset: 0x2E016C */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW6; /**< Window 6, Reference CRC Value of Blue Channel, offset: 0x2E0170 */ __IO uint32_t DISENG_SIG2_CONTROL_WINDOW7; /**< Window 7, Control settings, offset: 0x2E0174 */ __IO uint32_t DISENG_SIG2_UPPERLEFT_WINDOW7; /**< Window 7, Upper Left Coordinates, offset: 0x2E0178 */ __IO uint32_t DISENG_SIG2_LOWERRIGHT_WINDOW7; /**< Window 7, Lower Right Coordinates, offset: 0x2E017C */ __IO uint32_t DISENG_SIG2_REF_R_WINDOW7; /**< Window 7, Reference CRC Value of Red Channel, offset: 0x2E0180 */ __IO uint32_t DISENG_SIG2_REF_G_WINDOW7; /**< Window 7, Reference CRC Value of Green Channel, offset: 0x2E0184 */ __IO uint32_t DISENG_SIG2_REF_B_WINDOW7; /**< Window 7, Reference CRC Value of Blue Channel, offset: 0x2E0188 */ __IO uint32_t DISENG_SIG2_CONTROL_CLUSTER0; /**< Cluster 0, Control settings, offset: 0x2E018C */ __IO uint32_t DISENG_SIG2_PIX0_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 0, offset: 0x2E0190 */ __IO uint32_t DISENG_SIG2_PIX1_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 1, offset: 0x2E0194 */ __IO uint32_t DISENG_SIG2_PIX2_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 2, offset: 0x2E0198 */ __IO uint32_t DISENG_SIG2_PIX3_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 3, offset: 0x2E019C */ __IO uint32_t DISENG_SIG2_REF0_CLUSTER0; /**< Cluster 0, Reference Vector 0, offset: 0x2E01A0 */ __IO uint32_t DISENG_SIG2_REF1_CLUSTER0; /**< Cluster 0, Reference Vector 1, offset: 0x2E01A4 */ __IO uint32_t DISENG_SIG2_CONTROL_CLUSTER1; /**< Cluster 1, Control settings, offset: 0x2E01A8 */ __IO uint32_t DISENG_SIG2_PIX0_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 0, offset: 0x2E01AC */ __IO uint32_t DISENG_SIG2_PIX1_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 1, offset: 0x2E01B0 */ __IO uint32_t DISENG_SIG2_PIX2_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 2, offset: 0x2E01B4 */ __IO uint32_t DISENG_SIG2_PIX3_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 3, offset: 0x2E01B8 */ __IO uint32_t DISENG_SIG2_REF0_CLUSTER1; /**< Cluster 1, Reference Vector 0, offset: 0x2E01BC */ __IO uint32_t DISENG_SIG2_REF1_CLUSTER1; /**< Cluster 1, Reference Vector 1, offset: 0x2E01C0 */ __IO uint32_t DISENG_SIG2_CONTROL_CLUSTER2; /**< Cluster 2, Control settings, offset: 0x2E01C4 */ __IO uint32_t DISENG_SIG2_PIX0_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 0, offset: 0x2E01C8 */ __IO uint32_t DISENG_SIG2_PIX1_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 1, offset: 0x2E01CC */ __IO uint32_t DISENG_SIG2_PIX2_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 2, offset: 0x2E01D0 */ __IO uint32_t DISENG_SIG2_PIX3_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 3, offset: 0x2E01D4 */ __IO uint32_t DISENG_SIG2_REF0_CLUSTER2; /**< Cluster 2, Reference Vector 0, offset: 0x2E01D8 */ __IO uint32_t DISENG_SIG2_REF1_CLUSTER2; /**< Cluster 2, Reference Vector 1, offset: 0x2E01DC */ __IO uint32_t DISENG_SIG2_CONTROL_CLUSTER3; /**< Cluster 3, Control settings, offset: 0x2E01E0 */ __IO uint32_t DISENG_SIG2_PIX0_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 0, offset: 0x2E01E4 */ __IO uint32_t DISENG_SIG2_PIX1_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 1, offset: 0x2E01E8 */ __IO uint32_t DISENG_SIG2_PIX2_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 2, offset: 0x2E01EC */ __IO uint32_t DISENG_SIG2_PIX3_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 3, offset: 0x2E01F0 */ __IO uint32_t DISENG_SIG2_REF0_CLUSTER3; /**< Cluster 3, Reference Vector 0, offset: 0x2E01F4 */ __IO uint32_t DISENG_SIG2_REF1_CLUSTER3; /**< Cluster 3, Reference Vector 1, offset: 0x2E01F8 */ uint8_t RESERVED_142[516]; __I uint32_t DISENG_SIG2_CRC_R_WINDOW0; /**< Window 0, Measured CRC Value of Red Channel, offset: 0x2E0400 */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW0; /**< Window 0, Measured CRC Value of Green Channel, offset: 0x2E0404 */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW0; /**< Window 0, Measured CRC Value of Blue Channel, offset: 0x2E0408 */ __I uint32_t DISENG_SIG2_CRC_R_WINDOW1; /**< Window 1, Measured CRC Value of Red Channel, offset: 0x2E040C */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW1; /**< Window 1, Measured CRC Value of Green Channel, offset: 0x2E0410 */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW1; /**< Window 1, Measured CRC Value of Blue Channel, offset: 0x2E0414 */ __I uint32_t DISENG_SIG2_CRC_R_WINDOW2; /**< Window 2, Measured CRC Value of Red Channel, offset: 0x2E0418 */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW2; /**< Window 2, Measured CRC Value of Green Channel, offset: 0x2E041C */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW2; /**< Window 2, Measured CRC Value of Blue Channel, offset: 0x2E0420 */ __I uint32_t DISENG_SIG2_CRC_R_WINDOW3; /**< Window 3, Measured CRC Value of Red Channel, offset: 0x2E0424 */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW3; /**< Window 3, Measured CRC Value of Green Channel, offset: 0x2E0428 */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW3; /**< Window 3, Measured CRC Value of Blue Channel, offset: 0x2E042C */ __I uint32_t DISENG_SIG2_CRC_R_WINDOW4; /**< Window 4, Measured CRC Value of Red Channel, offset: 0x2E0430 */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW4; /**< Window 4, Measured CRC Value of Green Channel, offset: 0x2E0434 */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW4; /**< Window 4, Measured CRC Value of Blue Channel, offset: 0x2E0438 */ __I uint32_t DISENG_SIG2_CRC_R_WINDOW5; /**< Window 5, Measured CRC Value of Red Channel, offset: 0x2E043C */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW5; /**< Window 5, Measured CRC Value of Green Channel, offset: 0x2E0440 */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW5; /**< Window 5, Measured CRC Value of Blue Channel, offset: 0x2E0444 */ __I uint32_t DISENG_SIG2_CRC_R_WINDOW6; /**< Window 6, Measured CRC Value of Red Channel, offset: 0x2E0448 */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW6; /**< Window 6, Measured CRC Value of Green Channel, offset: 0x2E044C */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW6; /**< Window 6, Measured CRC Value of Blue Channel, offset: 0x2E0450 */ __I uint32_t DISENG_SIG2_CRC_R_WINDOW7; /**< Window 7, Measured CRC Value of Red Channel, offset: 0x2E0454 */ __I uint32_t DISENG_SIG2_CRC_G_WINDOW7; /**< Window 7, Measured CRC Value of Green Channel, offset: 0x2E0458 */ __I uint32_t DISENG_SIG2_CRC_B_WINDOW7; /**< Window 7, Measured CRC Value of Blue Channel, offset: 0x2E045C */ __I uint32_t DISENG_SIG2_STATUS_CLUSTER0; /**< Cluster 0, Status, offset: 0x2E0460 */ __I uint32_t DISENG_SIG2_COUNTER_CLUSTER0; /**< Cluster 0, Match and Error Counters, offset: 0x2E0464 */ __I uint32_t DISENG_SIG2_VECTOR0_CLUSTER0; /**< Cluster 0, Result Vector 0, RGB bitslices[1:0], offset: 0x2E0468 */ __I uint32_t DISENG_SIG2_VECTOR1_CLUSTER0; /**< Cluster 0, Result Vector 1, RGB bitslices[3:2], offset: 0x2E046C */ __I uint32_t DISENG_SIG2_VECTOR2_CLUSTER0; /**< Cluster 0, Result Vector 2, RGB bitslices[5:4], offset: 0x2E0470 */ __I uint32_t DISENG_SIG2_VECTOR3_CLUSTER0; /**< Cluster 0, Result Vector 3, RGB bitslices[7:6], offset: 0x2E0474 */ __I uint32_t DISENG_SIG2_STATUS_CLUSTER1; /**< Cluster 1, Status, offset: 0x2E0478 */ __I uint32_t DISENG_SIG2_COUNTER_CLUSTER1; /**< Cluster 1, Match and Error Counters, offset: 0x2E047C */ __I uint32_t DISENG_SIG2_VECTOR0_CLUSTER1; /**< Cluster 1, Result Vector 0, RGB bitslices[1:0], offset: 0x2E0480 */ __I uint32_t DISENG_SIG2_VECTOR1_CLUSTER1; /**< Cluster 1, Result Vector 1, RGB bitslices[3:2], offset: 0x2E0484 */ __I uint32_t DISENG_SIG2_VECTOR2_CLUSTER1; /**< Cluster 1, Result Vector 2, RGB bitslices[5:4], offset: 0x2E0488 */ __I uint32_t DISENG_SIG2_VECTOR3_CLUSTER1; /**< Cluster 1, Result Vector 3, RGB bitslices[7:6], offset: 0x2E048C */ __I uint32_t DISENG_SIG2_STATUS_CLUSTER2; /**< Cluster 2, Status, offset: 0x2E0490 */ __I uint32_t DISENG_SIG2_COUNTER_CLUSTER2; /**< Cluster 2, Match and Error Counters, offset: 0x2E0494 */ __I uint32_t DISENG_SIG2_VECTOR0_CLUSTER2; /**< Cluster 2, Result Vector 0, RGB bitslices[1:0], offset: 0x2E0498 */ __I uint32_t DISENG_SIG2_VECTOR1_CLUSTER2; /**< Cluster 2, Result Vector 1, RGB bitslices[3:2], offset: 0x2E049C */ __I uint32_t DISENG_SIG2_VECTOR2_CLUSTER2; /**< Cluster 2, Result Vector 2, RGB bitslices[5:4], offset: 0x2E04A0 */ __I uint32_t DISENG_SIG2_VECTOR3_CLUSTER2; /**< Cluster 2, Result Vector 3, RGB bitslices[7:6], offset: 0x2E04A4 */ __I uint32_t DISENG_SIG2_STATUS_CLUSTER3; /**< Cluster 3, Status, offset: 0x2E04A8 */ __I uint32_t DISENG_SIG2_COUNTER_CLUSTER3; /**< Cluster 3, Match and Error Counters, offset: 0x2E04AC */ __I uint32_t DISENG_SIG2_VECTOR0_CLUSTER3; /**< Cluster 3, Result Vector 0, RGB bitslices[1:0], offset: 0x2E04B0 */ __I uint32_t DISENG_SIG2_VECTOR1_CLUSTER3; /**< Cluster 3, Result Vector 1, RGB bitslices[3:2], offset: 0x2E04B4 */ __I uint32_t DISENG_SIG2_VECTOR2_CLUSTER3; /**< Cluster 3, Result Vector 2, RGB bitslices[5:4], offset: 0x2E04B8 */ __I uint32_t DISENG_SIG2_VECTOR3_CLUSTER3; /**< Cluster 3, Result Vector 3, RGB bitslices[7:6], offset: 0x2E04BC */ __I uint32_t DISENG_SIG2_PIXCNT_STATS0_WIN0; /**< Pixel Counter Register, Statistics Block 0, Window 0, offset: 0x2E04C0 */ __I uint32_t DISENG_SIG2_PIXMAX_STATS0_WIN0; /**< Pixel Max Values Register, Statistics Block 0, Window 0, offset: 0x2E04C4 */ __I uint32_t DISENG_SIG2_PIXMIN_STATS0_WIN0; /**< Pixel Min Values Register, Statistics Block 0, Window 0, offset: 0x2E04C8 */ __I uint32_t DISENG_SIG2_REDSUM_STATS0_WIN0; /**< Red Component Sum Register, Statistics Block 0, Window 0, offset: 0x2E04CC */ __I uint32_t DISENG_SIG2_GREENSUM_STATS0_WIN0; /**< Green Component Sum Register, Statistics Block 0, Window 0, offset: 0x2E04D0 */ __I uint32_t DISENG_SIG2_BLUESUM_STATS0_WIN0; /**< Blue Component Sum Register, Statistics Block 0, Window 0, offset: 0x2E04D4 */ __I uint32_t DISENG_SIG2_LUMSUM_STATS0_WIN0; /**< Luminance Sum Register, Statistics Block 0, Window 0, offset: 0x2E04D8 */ __I uint32_t DISENG_SIG2_PIXCNT_STATS1_WIN0; /**< Pixel Counter Register, Statistics Block 1, Window 0, offset: 0x2E04DC */ __I uint32_t DISENG_SIG2_PIXMAX_STATS1_WIN0; /**< Pixel Max Values Register, Statistics Block 1, Window 0, offset: 0x2E04E0 */ __I uint32_t DISENG_SIG2_PIXMIN_STATS1_WIN0; /**< Pixel Min Values Register, Statistics Block 1, Window 0, offset: 0x2E04E4 */ __I uint32_t DISENG_SIG2_REDSUM_STATS1_WIN0; /**< Red Component Sum Register, Statistics Block 1, Window 0, offset: 0x2E04E8 */ __I uint32_t DISENG_SIG2_GREENSUM_STATS1_WIN0; /**< Green Component Sum Register, Statistics Block 1, Window 0, offset: 0x2E04EC */ __I uint32_t DISENG_SIG2_BLUESUM_STATS1_WIN0; /**< Blue Component Sum Register, Statistics Block 1, Window 0, offset: 0x2E04F0 */ __I uint32_t DISENG_SIG2_PIXCNT_STATS0_WIN1; /**< Pixel Counter Register, Statistics Block 0, Window 1, offset: 0x2E04F4 */ __I uint32_t DISENG_SIG2_PIXMAX_STATS0_WIN1; /**< Pixel Max Values Register, Statistics Block 0, Window 1, offset: 0x2E04F8 */ __I uint32_t DISENG_SIG2_PIXMIN_STATS0_WIN1; /**< Pixel Min Values Register, Statistics Block 0, Window 1, offset: 0x2E04FC */ __I uint32_t DISENG_SIG2_REDSUM_STATS0_WIN1; /**< Red Component Sum Register, Statistics Block 0, Window 1, offset: 0x2E0500 */ __I uint32_t DISENG_SIG2_GREENSUM_STATS0_WIN1; /**< Green Component Sum Register, Statistics Block 0, Window 1, offset: 0x2E0504 */ __I uint32_t DISENG_SIG2_BLUESUM_STATS0_WIN1; /**< Blue Component Sum Register, Statistics Block 0, Window 1, offset: 0x2E0508 */ __I uint32_t DISENG_SIG2_LUMSUM_STATS0_WIN1; /**< Luminance Sum Register, Statistics Block 0, Window 1, offset: 0x2E050C */ __I uint32_t DISENG_SIG2_PIXCNT_STATS1_WIN1; /**< Pixel Counter Register, Statistics Block 1, Window 1, offset: 0x2E0510 */ __I uint32_t DISENG_SIG2_PIXMAX_STATS1_WIN1; /**< Pixel Max Values Register, Statistics Block 1, Window 1, offset: 0x2E0514 */ __I uint32_t DISENG_SIG2_PIXMIN_STATS1_WIN1; /**< Pixel Min Values Register, Statistics Block 1, Window 1, offset: 0x2E0518 */ __I uint32_t DISENG_SIG2_REDSUM_STATS1_WIN1; /**< Red Component Sum Register, Statistics Block 1, Window 1, offset: 0x2E051C */ __I uint32_t DISENG_SIG2_GREENSUM_STATS1_WIN1; /**< Green Component Sum Register, Statistics Block 1, Window 1, offset: 0x2E0520 */ __I uint32_t DISENG_SIG2_BLUESUM_STATS1_WIN1; /**< Blue Component Sum Register, Statistics Block 1, Window 1, offset: 0x2E0524 */ __I uint32_t DISENG_SIG2_PIXCNT_STATS0_WIN2; /**< Pixel Counter Register, Statistics Block 0, Window 2, offset: 0x2E0528 */ __I uint32_t DISENG_SIG2_PIXMAX_STATS0_WIN2; /**< Pixel Max Values Register, Statistics Block 0, Window 2, offset: 0x2E052C */ __I uint32_t DISENG_SIG2_PIXMIN_STATS0_WIN2; /**< Pixel Min Values Register, Statistics Block 0, Window 2, offset: 0x2E0530 */ __I uint32_t DISENG_SIG2_REDSUM_STATS0_WIN2; /**< Red Component Sum Register, Statistics Block 0, Window 2, offset: 0x2E0534 */ __I uint32_t DISENG_SIG2_GREENSUM_STATS0_WIN2; /**< Green Component Sum Register, Statistics Block 0, Window 2, offset: 0x2E0538 */ __I uint32_t DISENG_SIG2_BLUESUM_STATS0_WIN2; /**< Blue Component Sum Register, Statistics Block 0, Window 2, offset: 0x2E053C */ __I uint32_t DISENG_SIG2_LUMSUM_STATS0_WIN2; /**< Luminance Sum Register, Statistics Block 0, Window 2, offset: 0x2E0540 */ __I uint32_t DISENG_SIG2_PIXCNT_STATS1_WIN2; /**< Pixel Counter Register, Statistics Block 1, Window 2, offset: 0x2E0544 */ __I uint32_t DISENG_SIG2_PIXMAX_STATS1_WIN2; /**< Pixel Max Values Register, Statistics Block 1, Window 2, offset: 0x2E0548 */ __I uint32_t DISENG_SIG2_PIXMIN_STATS1_WIN2; /**< Pixel Min Values Register, Statistics Block 1, Window 2, offset: 0x2E054C */ __I uint32_t DISENG_SIG2_REDSUM_STATS1_WIN2; /**< Red Component Sum Register, Statistics Block 1, Window 2, offset: 0x2E0550 */ __I uint32_t DISENG_SIG2_GREENSUM_STATS1_WIN2; /**< Green Component Sum Register, Statistics Block 1, Window 2, offset: 0x2E0554 */ __I uint32_t DISENG_SIG2_BLUESUM_STATS1_WIN2; /**< Blue Component Sum Register, Statistics Block 1, Window 2, offset: 0x2E0558 */ __I uint32_t DISENG_SIG2_PIXCNT_STATS0_WIN3; /**< Pixel Counter Register, Statistics Block 0, Window 3, offset: 0x2E055C */ __I uint32_t DISENG_SIG2_PIXMAX_STATS0_WIN3; /**< Pixel Max Values Register, Statistics Block 0, Window 3, offset: 0x2E0560 */ __I uint32_t DISENG_SIG2_PIXMIN_STATS0_WIN3; /**< Pixel Min Values Register, Statistics Block 0, Window 3, offset: 0x2E0564 */ __I uint32_t DISENG_SIG2_REDSUM_STATS0_WIN3; /**< Red Component Sum Register, Statistics Block 0, Window 3, offset: 0x2E0568 */ __I uint32_t DISENG_SIG2_GREENSUM_STATS0_WIN3; /**< Green Component Sum Register, Statistics Block 0, Window 3, offset: 0x2E056C */ __I uint32_t DISENG_SIG2_BLUESUM_STATS0_WIN3; /**< Blue Component Sum Register, Statistics Block 0, Window 3, offset: 0x2E0570 */ __I uint32_t DISENG_SIG2_LUMSUM_STATS0_WIN3; /**< Luminance Sum Register, Statistics Block 0, Window 3, offset: 0x2E0574 */ __I uint32_t DISENG_SIG2_PIXCNT_STATS1_WIN3; /**< Pixel Counter Register, Statistics Block 1, Window 3, offset: 0x2E0578 */ __I uint32_t DISENG_SIG2_PIXMAX_STATS1_WIN3; /**< Pixel Max Values Register, Statistics Block 1, Window 3, offset: 0x2E057C */ __I uint32_t DISENG_SIG2_PIXMIN_STATS1_WIN3; /**< Pixel Min Values Register, Statistics Block 1, Window 3, offset: 0x2E0580 */ __I uint32_t DISENG_SIG2_REDSUM_STATS1_WIN3; /**< Red Component Sum Register, Statistics Block 1, Window 3, offset: 0x2E0584 */ __I uint32_t DISENG_SIG2_GREENSUM_STATS1_WIN3; /**< Green Component Sum Register, Statistics Block 1, Window 3, offset: 0x2E0588 */ __I uint32_t DISENG_SIG2_BLUESUM_STATS1_WIN3; /**< Blue Component Sum Register, Statistics Block 1, Window 3, offset: 0x2E058C */ uint8_t RESERVED_143[2672]; __O uint32_t DISENG_SIG2CFG_LOCKUNLOCK0; /**< Register to change the protection status of this address block., offset: 0x2E1000 */ __I uint32_t DISENG_SIG2CFG_LOCKSTATUS0; /**< Protection status of this address block., offset: 0x2E1004 */ __IO uint32_t DISENG_SIG2CFG_SRCSELECT; /**< Tap selection for sig2., offset: 0x2E1008 */ uint8_t RESERVED_144[61428]; __O uint32_t DISENG_MATRIX0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2F0000 */ __I uint32_t DISENG_MATRIX0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2F0004 */ __IO uint32_t DISENG_MATRIX0_STATICCONTROL; /**< Color Matrix static control register, offset: 0x2F0008 */ __IO uint32_t DISENG_MATRIX0_CONTROL; /**< Color Matrix control register, offset: 0x2F000C */ __IO uint32_t DISENG_MATRIX0_RED0; /**< Matrix values for calculation of the red output value., offset: 0x2F0010 */ __IO uint32_t DISENG_MATRIX0_RED1; /**< Matrix values for calculation of the red output value., offset: 0x2F0014 */ __IO uint32_t DISENG_MATRIX0_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x2F0018 */ __IO uint32_t DISENG_MATRIX0_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x2F001C */ __IO uint32_t DISENG_MATRIX0_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x2F0020 */ __IO uint32_t DISENG_MATRIX0_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x2F0024 */ uint8_t RESERVED_145[8]; __IO uint32_t DISENG_MATRIX0_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x2F0030 */ __IO uint32_t DISENG_MATRIX0_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x2F0034 */ __I uint32_t DISENG_MATRIX0_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x2F0038 */ uint8_t RESERVED_146[65476]; __O uint32_t DISENG_LUT3D0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x300000 */ __I uint32_t DISENG_LUT3D0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x300004 */ __IO uint32_t DISENG_LUT3D0_STATICCONTROL; /**< lut3d static control register, offset: 0x300008 */ __IO uint32_t DISENG_LUT3D0_CONTROL; /**< lut3d control register, offset: 0x30000C */ uint8_t RESERVED_147[8176]; __IO uint32_t DISENG_LUT3D0_LUT[2048]; /**< Look Up Table, array offset: 0x302000, array step: 0x4 */ uint8_t RESERVED_148[49152]; __O uint32_t DISENG_DITHER0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x310000 */ __I uint32_t DISENG_DITHER0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x310004 */ __IO uint32_t DISENG_DITHER0_CONTROL; /**< Dither Unit common control., offset: 0x310008 */ __IO uint32_t DISENG_DITHER0_DITHERCONTROL10BITS; /**< Dither Unit processing control., offset: 0x31000C */ __IO uint32_t DISENG_DITHER0_DITHERCONTROL12BITS; /**< Dither Unit processing control., offset: 0x310010 */ uint8_t RESERVED_149[4076]; __O uint32_t DISENG_DITHER0CFG_LOCKUNLOCK0; /**< Register to change the protection status of this address block., offset: 0x311000 */ __I uint32_t DISENG_DITHER0CFG_LOCKSTATUS0; /**< Protection status of this address block., offset: 0x311004 */ __IO uint32_t DISENG_DITHER0CFG_POLARITYCTRL0; /**< Polarity control for display stream #0., offset: 0x311008 */ uint8_t RESERVED_150[61428]; __O uint32_t DISENG_DOMAINBLEND1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x320000 */ __I uint32_t DISENG_DOMAINBLEND1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x320004 */ __IO uint32_t DISENG_DOMAINBLEND1_STATICCONTROL; /**< Static control settings., offset: 0x320008 */ __O uint32_t DISENG_DOMAINBLEND1_CONTROLTRIGGER; /**< Shadow load and sequence complete triggers., offset: 0x32000C */ __IO uint32_t DISENG_DOMAINBLEND1_MODECONTROL; /**< Operation mode of the domainblend, offset: 0x320010 */ __IO uint32_t DISENG_DOMAINBLEND1_ALPHACONTROL; /**< Alpha mask settings., offset: 0x320014 */ __IO uint32_t DISENG_DOMAINBLEND1_BLENDCONTROL; /**< Options for blend operations, offset: 0x320018 */ __I uint32_t DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK; /**< The status of primary and secondary sources waiting for pixels., offset: 0x32001C */ __O uint32_t DISENG_DOMAINBLEND1_LOCKUP_CLEAR; /**< The register can be used to internally reset domainblend if it gets stuck by pending pixels from one source., offset: 0x320020 */ __IO uint32_t DISENG_DOMAINBLEND1_DELAY_COUNTER_EN; /**< The register enables the delay and error counters that report on the delay on prim and sec sources., offset: 0x320024 */ __I uint32_t DISENG_DOMAINBLEND1_DELAY_COUNTER_PRIM; /**< The number of inavtive clock cycles during which the domainblend is waiting for pixels from primary source., offset: 0x320028 */ __I uint32_t DISENG_DOMAINBLEND1_DELAY_COUNTER_SEC; /**< The number of inavtive clock cycles during which the domainblend is waiting for pixels from secondary source., offset: 0x32002C */ __I uint32_t DISENG_DOMAINBLEND1_ERROR_COUNTER_PRIM; /**< The number of inavtive clock cycles on the primary source till the synchronization loss of domainblend., offset: 0x320030 */ __I uint32_t DISENG_DOMAINBLEND1_ERROR_COUNTER_SEC; /**< The number of inavtive clock cycles on the secondary source till the synchronization loss of domainblend., offset: 0x320034 */ __I uint32_t DISENG_DOMAINBLEND1_SOURCE_STATUS; /**< Source protocol error detection for primary and secondary sources, offset: 0x320038 */ __O uint32_t DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR; /**< Clearing source protocol error status for both primary and secondary sources, offset: 0x32003C */ __I uint32_t DISENG_DOMAINBLEND1_PRIMCONTROLWORD; /**< Value of last received primary control word, for debugging, offset: 0x320040 */ __I uint32_t DISENG_DOMAINBLEND1_SECCONTROLWORD; /**< Value of last received secondary control word, for debugging, offset: 0x320044 */ uint8_t RESERVED_151[65464]; __O uint32_t DISENG_FRAMEGEN1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x330000 */ __I uint32_t DISENG_FRAMEGEN1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x330004 */ __IO uint32_t DISENG_FRAMEGEN1_FGSTCTRL; /**< FrameGen Static Control Register, offset: 0x330008 */ __IO uint32_t DISENG_FRAMEGEN1_HTCFG1; /**< FrameGen Horizontal Timing Config Register 1, offset: 0x33000C */ __IO uint32_t DISENG_FRAMEGEN1_HTCFG2; /**< FrameGen Horizontal Timing Config Register 2, offset: 0x330010 */ __IO uint32_t DISENG_FRAMEGEN1_VTCFG1; /**< FrameGen Vertical Timing Config Register 1, offset: 0x330014 */ __IO uint32_t DISENG_FRAMEGEN1_VTCFG2; /**< FrameGen Vertical Timing Config Register 2, offset: 0x330018 */ __IO uint32_t DISENG_FRAMEGEN1_INT0CONFIG; /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0x33001C */ __IO uint32_t DISENG_FRAMEGEN1_INT1CONFIG; /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0x330020 */ __IO uint32_t DISENG_FRAMEGEN1_INT2CONFIG; /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0x330024 */ __IO uint32_t DISENG_FRAMEGEN1_INT3CONFIG; /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0x330028 */ __IO uint32_t DISENG_FRAMEGEN1_PKICKCONFIG; /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0x33002C */ __IO uint32_t DISENG_FRAMEGEN1_SKICKCONFIG; /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0x330030 */ __IO uint32_t DISENG_FRAMEGEN1_SECSTATCONFIG; /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0x330034 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR1; /**< FrameGen Skew Regulation Control Register 1., offset: 0x330038 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR2; /**< FrameGen Skew Regulation Control Register 2, offset: 0x33003C */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR3; /**< FrameGen Skew Regulation Control Register 3, offset: 0x330040 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR4; /**< FrameGen Skew Regulation Control Register 4, offset: 0x330044 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR5; /**< FrameGen Skew Regulation Control Register 5, offset: 0x330048 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR6; /**< FrameGen Skew Regulation Control Register 6, offset: 0x33004C */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR7; /**< FrameGen Skew Regulation Control Register 7, offset: 0x330050 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR8; /**< FrameGen Skew Regulation Control Register 8, offset: 0x330054 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR9; /**< FrameGen Skew Regulation Control Register 9, offset: 0x330058 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR10; /**< FrameGen Skew Regulation Control Register 10, offset: 0x33005C */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR11; /**< FrameGen Skew Regulation Control Register 11, offset: 0x330060 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR12; /**< FrameGen Skew Regulation Control Register 12, offset: 0x330064 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR13; /**< FrameGen Skew Regulation Control Register 13, offset: 0x330068 */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR14; /**< FrameGen Skew Regulation Control Register 14, offset: 0x33006C */ __IO uint32_t DISENG_FRAMEGEN1_FGSRCR15; /**< FrameGen Skew Regulation Control Register 15, offset: 0x330070 */ __IO uint32_t DISENG_FRAMEGEN1_FGKSDR; /**< FrameGen Kick System Debug Register, offset: 0x330074 */ __IO uint32_t DISENG_FRAMEGEN1_PACFG; /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0x330078 */ __IO uint32_t DISENG_FRAMEGEN1_SACFG; /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0x33007C */ __IO uint32_t DISENG_FRAMEGEN1_FGINCTRL; /**< FrameGen Input Control Register (shadowed), offset: 0x330080 */ __IO uint32_t DISENG_FRAMEGEN1_FGINCTRLPANIC; /**< FrameGen Input Control Panic Register (shadowed), offset: 0x330084 */ __IO uint32_t DISENG_FRAMEGEN1_FGCCR; /**< FrameGen Constant Color Register (shadowed), offset: 0x330088 */ __IO uint32_t DISENG_FRAMEGEN1_FGENABLE; /**< FrameGen Enable Register, offset: 0x33008C */ __O uint32_t DISENG_FRAMEGEN1_FGSLR; /**< FrameGen Shadow Load Register, offset: 0x330090 */ __I uint32_t DISENG_FRAMEGEN1_FGENSTS; /**< FrameGen Enable Status Register, offset: 0x330094 */ __I uint32_t DISENG_FRAMEGEN1_FGTIMESTAMP; /**< Time stamp status., offset: 0x330098 */ __I uint32_t DISENG_FRAMEGEN1_FGCHSTAT; /**< FrameGen Channel Status Register, offset: 0x33009C */ __O uint32_t DISENG_FRAMEGEN1_FGCHSTATCLR; /**< FrameGen Channel Status Clear Register, offset: 0x3300A0 */ __I uint32_t DISENG_FRAMEGEN1_FGSKEWMON; /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0x3300A4 */ __I uint32_t DISENG_FRAMEGEN1_FGPFIFOMIN; /**< FrameGen Primary FIFO Min Fill Register, offset: 0x3300A8 */ __I uint32_t DISENG_FRAMEGEN1_FGPFIFOMAX; /**< FrameGen Primary FIFO Max Fill Register, offset: 0x3300AC */ __O uint32_t DISENG_FRAMEGEN1_FGPFIFOFILLCLR; /**< FrameGen Primary FIFO Fill Clear Register, offset: 0x3300B0 */ __IO uint32_t DISENG_FRAMEGEN1_FGPFIFOTRES; /**< FrameGen Primary FIFO Thresholds, offset: 0x3300B4 */ __I uint32_t DISENG_FRAMEGEN1_FGSFIFOMIN; /**< FrameGen Secondary FIFO Min Fill Register, offset: 0x3300B8 */ __I uint32_t DISENG_FRAMEGEN1_FGSFIFOMAX; /**< FrameGen Secondary FIFO Max Fill Register, offset: 0x3300BC */ __O uint32_t DISENG_FRAMEGEN1_FGSFIFOFILLCLR; /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0x3300C0 */ __I uint32_t DISENG_FRAMEGEN1_FGSREPD; /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0x3300C4 */ __I uint32_t DISENG_FRAMEGEN1_FGSRFTD; /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0x3300C8 */ __I uint32_t DISENG_FRAMEGEN1_FGSRCSHTOTAL; /**< FrameGen Skew Regulation External Sync HTotal Debug Register, offset: 0x3300CC */ __I uint32_t DISENG_FRAMEGEN1_FGSRCLOCKDIV; /**< FrameGen Skew Regulation External PLL Clock divider, offset: 0x3300D0 */ __I uint32_t DISENG_FRAMEGEN1_FGSL; /**< FrameGen Scanline Register, offset: 0x3300D4 */ uint8_t RESERVED_152[65320]; __O uint32_t DISENG_SIG1_LOCKUNLOCK; /**< Register to change the protection status of this address block, offset: 0x340000 */ __I uint32_t DISENG_SIG1_LOCKSTATUS; /**< Protection status of this address block, offset: 0x340004 */ __IO uint32_t DISENG_SIG1_STATICCONTROL; /**< Global configuration, offset: 0x340008 */ __IO uint32_t DISENG_SIG1_ERRORTHRESHOLD; /**< Set and reset thresholds applying to Window_Error and Cluster_Error interrupts and status bits, offset: 0x34000C */ __IO uint32_t DISENG_SIG1_MATCHTHRESHOLD; /**< Set and reset thresholds applying to Match interrupt and status bits, offset: 0x340010 */ __IO uint32_t DISENG_SIG1_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode, offset: 0x340014 */ __IO uint32_t DISENG_SIG1_SHADOWLOAD; /**< Shadow load control register, offset: 0x340018 */ __IO uint32_t DISENG_SIG1_CONTINUOUSMODE; /**< Signature operation mode control, offset: 0x34001C */ __O uint32_t DISENG_SIG1_SOFTWAREKICK; /**< Signature measurement trigger, offset: 0x340020 */ __IO uint32_t DISENG_SIG1_SKIPWINDOW; /**< Enable skipping window feature., offset: 0x340024 */ __I uint32_t DISENG_SIG1_STATUS; /**< Signature evaluation status, offset: 0x340028 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW0; /**< Window 0, Control settings, offset: 0x34002C */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW0; /**< Window 0, Upper Left Coordinates, offset: 0x340030 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW0; /**< Window 0, Lower Right Coordinates, offset: 0x340034 */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW0; /**< Window 0, Reference CRC Value of Red Channel, offset: 0x340038 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW0; /**< Window 0, Reference CRC Value of Green Channel, offset: 0x34003C */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW0; /**< Window 0, Reference CRC Value of Blue Channel, offset: 0x340040 */ __IO uint32_t DISENG_SIG1_STATS0_WINDOW0; /**< Controls of Statistics Block 0, Window 0, offset: 0x340044 */ __IO uint32_t DISENG_SIG1_STATS1_WINDOW0; /**< Controls of Statistics Block 0, Window 0, offset: 0x340048 */ __IO uint32_t DISENG_SIG1_MIN_REDSUM_WINDOW0; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x34004C */ __IO uint32_t DISENG_SIG1_MIN_GREENSUM_WINDOW0; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x340050 */ __IO uint32_t DISENG_SIG1_MIN_BLUESUM_WINDOW0; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x340054 */ __IO uint32_t DISENG_SIG1_MIN_LUMSUM_WINDOW0; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x340058 */ __IO uint32_t DISENG_SIG1_MAX_REDSUM_WINDOW0; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x34005C */ __IO uint32_t DISENG_SIG1_MAX_GREENSUM_WINDOW0; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x340060 */ __IO uint32_t DISENG_SIG1_MAX_BLUESUM_WINDOW0; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x340064 */ __IO uint32_t DISENG_SIG1_MAX_LUMSUM_WINDOW0; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x340068 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW1; /**< Window 1, Control settings, offset: 0x34006C */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW1; /**< Window 1, Upper Left Coordinates, offset: 0x340070 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW1; /**< Window 1, Lower Right Coordinates, offset: 0x340074 */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW1; /**< Window 1, Reference CRC Value of Red Channel, offset: 0x340078 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW1; /**< Window 1, Reference CRC Value of Green Channel, offset: 0x34007C */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW1; /**< Window 1, Reference CRC Value of Blue Channel, offset: 0x340080 */ __IO uint32_t DISENG_SIG1_STATS0_WINDOW1; /**< Controls of Statistics Block 0, Window 1, offset: 0x340084 */ __IO uint32_t DISENG_SIG1_STATS1_WINDOW1; /**< Controls of Statistics Block 0, Window 1, offset: 0x340088 */ __IO uint32_t DISENG_SIG1_MIN_REDSUM_WINDOW1; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x34008C */ __IO uint32_t DISENG_SIG1_MIN_GREENSUM_WINDOW1; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x340090 */ __IO uint32_t DISENG_SIG1_MIN_BLUESUM_WINDOW1; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x340094 */ __IO uint32_t DISENG_SIG1_MIN_LUMSUM_WINDOW1; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x340098 */ __IO uint32_t DISENG_SIG1_MAX_REDSUM_WINDOW1; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x34009C */ __IO uint32_t DISENG_SIG1_MAX_GREENSUM_WINDOW1; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x3400A0 */ __IO uint32_t DISENG_SIG1_MAX_BLUESUM_WINDOW1; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x3400A4 */ __IO uint32_t DISENG_SIG1_MAX_LUMSUM_WINDOW1; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x3400A8 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW2; /**< Window 2, Control settings, offset: 0x3400AC */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW2; /**< Window 2, Upper Left Coordinates, offset: 0x3400B0 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW2; /**< Window 2, Lower Right Coordinates, offset: 0x3400B4 */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW2; /**< Window 2, Reference CRC Value of Red Channel, offset: 0x3400B8 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW2; /**< Window 2, Reference CRC Value of Green Channel, offset: 0x3400BC */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW2; /**< Window 2, Reference CRC Value of Blue Channel, offset: 0x3400C0 */ __IO uint32_t DISENG_SIG1_STATS0_WINDOW2; /**< Controls of Statistics Block 0, Window 2, offset: 0x3400C4 */ __IO uint32_t DISENG_SIG1_STATS1_WINDOW2; /**< Controls of Statistics Block 0, Window 2, offset: 0x3400C8 */ __IO uint32_t DISENG_SIG1_MIN_REDSUM_WINDOW2; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x3400CC */ __IO uint32_t DISENG_SIG1_MIN_GREENSUM_WINDOW2; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x3400D0 */ __IO uint32_t DISENG_SIG1_MIN_BLUESUM_WINDOW2; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x3400D4 */ __IO uint32_t DISENG_SIG1_MIN_LUMSUM_WINDOW2; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x3400D8 */ __IO uint32_t DISENG_SIG1_MAX_REDSUM_WINDOW2; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x3400DC */ __IO uint32_t DISENG_SIG1_MAX_GREENSUM_WINDOW2; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x3400E0 */ __IO uint32_t DISENG_SIG1_MAX_BLUESUM_WINDOW2; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x3400E4 */ __IO uint32_t DISENG_SIG1_MAX_LUMSUM_WINDOW2; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x3400E8 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW3; /**< Window 3, Control settings, offset: 0x3400EC */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW3; /**< Window 3, Upper Left Coordinates, offset: 0x3400F0 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW3; /**< Window 3, Lower Right Coordinates, offset: 0x3400F4 */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW3; /**< Window 3, Reference CRC Value of Red Channel, offset: 0x3400F8 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW3; /**< Window 3, Reference CRC Value of Green Channel, offset: 0x3400FC */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW3; /**< Window 3, Reference CRC Value of Blue Channel, offset: 0x340100 */ __IO uint32_t DISENG_SIG1_STATS0_WINDOW3; /**< Controls of Statistics Block 0, Window 3, offset: 0x340104 */ __IO uint32_t DISENG_SIG1_STATS1_WINDOW3; /**< Controls of Statistics Block 0, Window 3, offset: 0x340108 */ __IO uint32_t DISENG_SIG1_MIN_REDSUM_WINDOW3; /**< Minimum sum-threshold for red component of the pixels in a window., offset: 0x34010C */ __IO uint32_t DISENG_SIG1_MIN_GREENSUM_WINDOW3; /**< Minimum sum-threshold for green component of the pixels in a window., offset: 0x340110 */ __IO uint32_t DISENG_SIG1_MIN_BLUESUM_WINDOW3; /**< Minimum sum-threshold for blue component of the pixels in a window., offset: 0x340114 */ __IO uint32_t DISENG_SIG1_MIN_LUMSUM_WINDOW3; /**< Minimum sum-threshold for luminance of the pixels in a window., offset: 0x340118 */ __IO uint32_t DISENG_SIG1_MAX_REDSUM_WINDOW3; /**< Maximum sum-threshold for red component of the pixels in a window., offset: 0x34011C */ __IO uint32_t DISENG_SIG1_MAX_GREENSUM_WINDOW3; /**< Maximum sum-threshold for green component of the pixels in a window., offset: 0x340120 */ __IO uint32_t DISENG_SIG1_MAX_BLUESUM_WINDOW3; /**< Maximum sum-threshold for blue component of the pixels in a window., offset: 0x340124 */ __IO uint32_t DISENG_SIG1_MAX_LUMSUM_WINDOW3; /**< Maximum sum-threshold for luminance of the pixels in a window., offset: 0x340128 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW4; /**< Window 4, Control settings, offset: 0x34012C */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW4; /**< Window 4, Upper Left Coordinates, offset: 0x340130 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW4; /**< Window 4, Lower Right Coordinates, offset: 0x340134 */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW4; /**< Window 4, Reference CRC Value of Red Channel, offset: 0x340138 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW4; /**< Window 4, Reference CRC Value of Green Channel, offset: 0x34013C */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW4; /**< Window 4, Reference CRC Value of Blue Channel, offset: 0x340140 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW5; /**< Window 5, Control settings, offset: 0x340144 */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW5; /**< Window 5, Upper Left Coordinates, offset: 0x340148 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW5; /**< Window 5, Lower Right Coordinates, offset: 0x34014C */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW5; /**< Window 5, Reference CRC Value of Red Channel, offset: 0x340150 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW5; /**< Window 5, Reference CRC Value of Green Channel, offset: 0x340154 */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW5; /**< Window 5, Reference CRC Value of Blue Channel, offset: 0x340158 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW6; /**< Window 6, Control settings, offset: 0x34015C */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW6; /**< Window 6, Upper Left Coordinates, offset: 0x340160 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW6; /**< Window 6, Lower Right Coordinates, offset: 0x340164 */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW6; /**< Window 6, Reference CRC Value of Red Channel, offset: 0x340168 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW6; /**< Window 6, Reference CRC Value of Green Channel, offset: 0x34016C */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW6; /**< Window 6, Reference CRC Value of Blue Channel, offset: 0x340170 */ __IO uint32_t DISENG_SIG1_CONTROL_WINDOW7; /**< Window 7, Control settings, offset: 0x340174 */ __IO uint32_t DISENG_SIG1_UPPERLEFT_WINDOW7; /**< Window 7, Upper Left Coordinates, offset: 0x340178 */ __IO uint32_t DISENG_SIG1_LOWERRIGHT_WINDOW7; /**< Window 7, Lower Right Coordinates, offset: 0x34017C */ __IO uint32_t DISENG_SIG1_REF_R_WINDOW7; /**< Window 7, Reference CRC Value of Red Channel, offset: 0x340180 */ __IO uint32_t DISENG_SIG1_REF_G_WINDOW7; /**< Window 7, Reference CRC Value of Green Channel, offset: 0x340184 */ __IO uint32_t DISENG_SIG1_REF_B_WINDOW7; /**< Window 7, Reference CRC Value of Blue Channel, offset: 0x340188 */ __IO uint32_t DISENG_SIG1_CONTROL_CLUSTER0; /**< Cluster 0, Control settings, offset: 0x34018C */ __IO uint32_t DISENG_SIG1_PIX0_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 0, offset: 0x340190 */ __IO uint32_t DISENG_SIG1_PIX1_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 1, offset: 0x340194 */ __IO uint32_t DISENG_SIG1_PIX2_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 2, offset: 0x340198 */ __IO uint32_t DISENG_SIG1_PIX3_CLUSTER0; /**< Cluster 0, Coordinate of Pixel 3, offset: 0x34019C */ __IO uint32_t DISENG_SIG1_REF0_CLUSTER0; /**< Cluster 0, Reference Vector 0, offset: 0x3401A0 */ __IO uint32_t DISENG_SIG1_REF1_CLUSTER0; /**< Cluster 0, Reference Vector 1, offset: 0x3401A4 */ __IO uint32_t DISENG_SIG1_CONTROL_CLUSTER1; /**< Cluster 1, Control settings, offset: 0x3401A8 */ __IO uint32_t DISENG_SIG1_PIX0_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 0, offset: 0x3401AC */ __IO uint32_t DISENG_SIG1_PIX1_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 1, offset: 0x3401B0 */ __IO uint32_t DISENG_SIG1_PIX2_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 2, offset: 0x3401B4 */ __IO uint32_t DISENG_SIG1_PIX3_CLUSTER1; /**< Cluster 1, Coordinate of Pixel 3, offset: 0x3401B8 */ __IO uint32_t DISENG_SIG1_REF0_CLUSTER1; /**< Cluster 1, Reference Vector 0, offset: 0x3401BC */ __IO uint32_t DISENG_SIG1_REF1_CLUSTER1; /**< Cluster 1, Reference Vector 1, offset: 0x3401C0 */ __IO uint32_t DISENG_SIG1_CONTROL_CLUSTER2; /**< Cluster 2, Control settings, offset: 0x3401C4 */ __IO uint32_t DISENG_SIG1_PIX0_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 0, offset: 0x3401C8 */ __IO uint32_t DISENG_SIG1_PIX1_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 1, offset: 0x3401CC */ __IO uint32_t DISENG_SIG1_PIX2_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 2, offset: 0x3401D0 */ __IO uint32_t DISENG_SIG1_PIX3_CLUSTER2; /**< Cluster 2, Coordinate of Pixel 3, offset: 0x3401D4 */ __IO uint32_t DISENG_SIG1_REF0_CLUSTER2; /**< Cluster 2, Reference Vector 0, offset: 0x3401D8 */ __IO uint32_t DISENG_SIG1_REF1_CLUSTER2; /**< Cluster 2, Reference Vector 1, offset: 0x3401DC */ __IO uint32_t DISENG_SIG1_CONTROL_CLUSTER3; /**< Cluster 3, Control settings, offset: 0x3401E0 */ __IO uint32_t DISENG_SIG1_PIX0_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 0, offset: 0x3401E4 */ __IO uint32_t DISENG_SIG1_PIX1_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 1, offset: 0x3401E8 */ __IO uint32_t DISENG_SIG1_PIX2_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 2, offset: 0x3401EC */ __IO uint32_t DISENG_SIG1_PIX3_CLUSTER3; /**< Cluster 3, Coordinate of Pixel 3, offset: 0x3401F0 */ __IO uint32_t DISENG_SIG1_REF0_CLUSTER3; /**< Cluster 3, Reference Vector 0, offset: 0x3401F4 */ __IO uint32_t DISENG_SIG1_REF1_CLUSTER3; /**< Cluster 3, Reference Vector 1, offset: 0x3401F8 */ uint8_t RESERVED_153[516]; __I uint32_t DISENG_SIG1_CRC_R_WINDOW0; /**< Window 0, Measured CRC Value of Red Channel, offset: 0x340400 */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW0; /**< Window 0, Measured CRC Value of Green Channel, offset: 0x340404 */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW0; /**< Window 0, Measured CRC Value of Blue Channel, offset: 0x340408 */ __I uint32_t DISENG_SIG1_CRC_R_WINDOW1; /**< Window 1, Measured CRC Value of Red Channel, offset: 0x34040C */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW1; /**< Window 1, Measured CRC Value of Green Channel, offset: 0x340410 */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW1; /**< Window 1, Measured CRC Value of Blue Channel, offset: 0x340414 */ __I uint32_t DISENG_SIG1_CRC_R_WINDOW2; /**< Window 2, Measured CRC Value of Red Channel, offset: 0x340418 */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW2; /**< Window 2, Measured CRC Value of Green Channel, offset: 0x34041C */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW2; /**< Window 2, Measured CRC Value of Blue Channel, offset: 0x340420 */ __I uint32_t DISENG_SIG1_CRC_R_WINDOW3; /**< Window 3, Measured CRC Value of Red Channel, offset: 0x340424 */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW3; /**< Window 3, Measured CRC Value of Green Channel, offset: 0x340428 */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW3; /**< Window 3, Measured CRC Value of Blue Channel, offset: 0x34042C */ __I uint32_t DISENG_SIG1_CRC_R_WINDOW4; /**< Window 4, Measured CRC Value of Red Channel, offset: 0x340430 */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW4; /**< Window 4, Measured CRC Value of Green Channel, offset: 0x340434 */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW4; /**< Window 4, Measured CRC Value of Blue Channel, offset: 0x340438 */ __I uint32_t DISENG_SIG1_CRC_R_WINDOW5; /**< Window 5, Measured CRC Value of Red Channel, offset: 0x34043C */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW5; /**< Window 5, Measured CRC Value of Green Channel, offset: 0x340440 */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW5; /**< Window 5, Measured CRC Value of Blue Channel, offset: 0x340444 */ __I uint32_t DISENG_SIG1_CRC_R_WINDOW6; /**< Window 6, Measured CRC Value of Red Channel, offset: 0x340448 */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW6; /**< Window 6, Measured CRC Value of Green Channel, offset: 0x34044C */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW6; /**< Window 6, Measured CRC Value of Blue Channel, offset: 0x340450 */ __I uint32_t DISENG_SIG1_CRC_R_WINDOW7; /**< Window 7, Measured CRC Value of Red Channel, offset: 0x340454 */ __I uint32_t DISENG_SIG1_CRC_G_WINDOW7; /**< Window 7, Measured CRC Value of Green Channel, offset: 0x340458 */ __I uint32_t DISENG_SIG1_CRC_B_WINDOW7; /**< Window 7, Measured CRC Value of Blue Channel, offset: 0x34045C */ __I uint32_t DISENG_SIG1_STATUS_CLUSTER0; /**< Cluster 0, Status, offset: 0x340460 */ __I uint32_t DISENG_SIG1_COUNTER_CLUSTER0; /**< Cluster 0, Match and Error Counters, offset: 0x340464 */ __I uint32_t DISENG_SIG1_VECTOR0_CLUSTER0; /**< Cluster 0, Result Vector 0, RGB bitslices[1:0], offset: 0x340468 */ __I uint32_t DISENG_SIG1_VECTOR1_CLUSTER0; /**< Cluster 0, Result Vector 1, RGB bitslices[3:2], offset: 0x34046C */ __I uint32_t DISENG_SIG1_VECTOR2_CLUSTER0; /**< Cluster 0, Result Vector 2, RGB bitslices[5:4], offset: 0x340470 */ __I uint32_t DISENG_SIG1_VECTOR3_CLUSTER0; /**< Cluster 0, Result Vector 3, RGB bitslices[7:6], offset: 0x340474 */ __I uint32_t DISENG_SIG1_STATUS_CLUSTER1; /**< Cluster 1, Status, offset: 0x340478 */ __I uint32_t DISENG_SIG1_COUNTER_CLUSTER1; /**< Cluster 1, Match and Error Counters, offset: 0x34047C */ __I uint32_t DISENG_SIG1_VECTOR0_CLUSTER1; /**< Cluster 1, Result Vector 0, RGB bitslices[1:0], offset: 0x340480 */ __I uint32_t DISENG_SIG1_VECTOR1_CLUSTER1; /**< Cluster 1, Result Vector 1, RGB bitslices[3:2], offset: 0x340484 */ __I uint32_t DISENG_SIG1_VECTOR2_CLUSTER1; /**< Cluster 1, Result Vector 2, RGB bitslices[5:4], offset: 0x340488 */ __I uint32_t DISENG_SIG1_VECTOR3_CLUSTER1; /**< Cluster 1, Result Vector 3, RGB bitslices[7:6], offset: 0x34048C */ __I uint32_t DISENG_SIG1_STATUS_CLUSTER2; /**< Cluster 2, Status, offset: 0x340490 */ __I uint32_t DISENG_SIG1_COUNTER_CLUSTER2; /**< Cluster 2, Match and Error Counters, offset: 0x340494 */ __I uint32_t DISENG_SIG1_VECTOR0_CLUSTER2; /**< Cluster 2, Result Vector 0, RGB bitslices[1:0], offset: 0x340498 */ __I uint32_t DISENG_SIG1_VECTOR1_CLUSTER2; /**< Cluster 2, Result Vector 1, RGB bitslices[3:2], offset: 0x34049C */ __I uint32_t DISENG_SIG1_VECTOR2_CLUSTER2; /**< Cluster 2, Result Vector 2, RGB bitslices[5:4], offset: 0x3404A0 */ __I uint32_t DISENG_SIG1_VECTOR3_CLUSTER2; /**< Cluster 2, Result Vector 3, RGB bitslices[7:6], offset: 0x3404A4 */ __I uint32_t DISENG_SIG1_STATUS_CLUSTER3; /**< Cluster 3, Status, offset: 0x3404A8 */ __I uint32_t DISENG_SIG1_COUNTER_CLUSTER3; /**< Cluster 3, Match and Error Counters, offset: 0x3404AC */ __I uint32_t DISENG_SIG1_VECTOR0_CLUSTER3; /**< Cluster 3, Result Vector 0, RGB bitslices[1:0], offset: 0x3404B0 */ __I uint32_t DISENG_SIG1_VECTOR1_CLUSTER3; /**< Cluster 3, Result Vector 1, RGB bitslices[3:2], offset: 0x3404B4 */ __I uint32_t DISENG_SIG1_VECTOR2_CLUSTER3; /**< Cluster 3, Result Vector 2, RGB bitslices[5:4], offset: 0x3404B8 */ __I uint32_t DISENG_SIG1_VECTOR3_CLUSTER3; /**< Cluster 3, Result Vector 3, RGB bitslices[7:6], offset: 0x3404BC */ __I uint32_t DISENG_SIG1_PIXCNT_STATS0_WIN0; /**< Pixel Counter Register, Statistics Block 0, Window 0, offset: 0x3404C0 */ __I uint32_t DISENG_SIG1_PIXMAX_STATS0_WIN0; /**< Pixel Max Values Register, Statistics Block 0, Window 0, offset: 0x3404C4 */ __I uint32_t DISENG_SIG1_PIXMIN_STATS0_WIN0; /**< Pixel Min Values Register, Statistics Block 0, Window 0, offset: 0x3404C8 */ __I uint32_t DISENG_SIG1_REDSUM_STATS0_WIN0; /**< Red Component Sum Register, Statistics Block 0, Window 0, offset: 0x3404CC */ __I uint32_t DISENG_SIG1_GREENSUM_STATS0_WIN0; /**< Green Component Sum Register, Statistics Block 0, Window 0, offset: 0x3404D0 */ __I uint32_t DISENG_SIG1_BLUESUM_STATS0_WIN0; /**< Blue Component Sum Register, Statistics Block 0, Window 0, offset: 0x3404D4 */ __I uint32_t DISENG_SIG1_LUMSUM_STATS0_WIN0; /**< Luminance Sum Register, Statistics Block 0, Window 0, offset: 0x3404D8 */ __I uint32_t DISENG_SIG1_PIXCNT_STATS1_WIN0; /**< Pixel Counter Register, Statistics Block 1, Window 0, offset: 0x3404DC */ __I uint32_t DISENG_SIG1_PIXMAX_STATS1_WIN0; /**< Pixel Max Values Register, Statistics Block 1, Window 0, offset: 0x3404E0 */ __I uint32_t DISENG_SIG1_PIXMIN_STATS1_WIN0; /**< Pixel Min Values Register, Statistics Block 1, Window 0, offset: 0x3404E4 */ __I uint32_t DISENG_SIG1_REDSUM_STATS1_WIN0; /**< Red Component Sum Register, Statistics Block 1, Window 0, offset: 0x3404E8 */ __I uint32_t DISENG_SIG1_GREENSUM_STATS1_WIN0; /**< Green Component Sum Register, Statistics Block 1, Window 0, offset: 0x3404EC */ __I uint32_t DISENG_SIG1_BLUESUM_STATS1_WIN0; /**< Blue Component Sum Register, Statistics Block 1, Window 0, offset: 0x3404F0 */ __I uint32_t DISENG_SIG1_PIXCNT_STATS0_WIN1; /**< Pixel Counter Register, Statistics Block 0, Window 1, offset: 0x3404F4 */ __I uint32_t DISENG_SIG1_PIXMAX_STATS0_WIN1; /**< Pixel Max Values Register, Statistics Block 0, Window 1, offset: 0x3404F8 */ __I uint32_t DISENG_SIG1_PIXMIN_STATS0_WIN1; /**< Pixel Min Values Register, Statistics Block 0, Window 1, offset: 0x3404FC */ __I uint32_t DISENG_SIG1_REDSUM_STATS0_WIN1; /**< Red Component Sum Register, Statistics Block 0, Window 1, offset: 0x340500 */ __I uint32_t DISENG_SIG1_GREENSUM_STATS0_WIN1; /**< Green Component Sum Register, Statistics Block 0, Window 1, offset: 0x340504 */ __I uint32_t DISENG_SIG1_BLUESUM_STATS0_WIN1; /**< Blue Component Sum Register, Statistics Block 0, Window 1, offset: 0x340508 */ __I uint32_t DISENG_SIG1_LUMSUM_STATS0_WIN1; /**< Luminance Sum Register, Statistics Block 0, Window 1, offset: 0x34050C */ __I uint32_t DISENG_SIG1_PIXCNT_STATS1_WIN1; /**< Pixel Counter Register, Statistics Block 1, Window 1, offset: 0x340510 */ __I uint32_t DISENG_SIG1_PIXMAX_STATS1_WIN1; /**< Pixel Max Values Register, Statistics Block 1, Window 1, offset: 0x340514 */ __I uint32_t DISENG_SIG1_PIXMIN_STATS1_WIN1; /**< Pixel Min Values Register, Statistics Block 1, Window 1, offset: 0x340518 */ __I uint32_t DISENG_SIG1_REDSUM_STATS1_WIN1; /**< Red Component Sum Register, Statistics Block 1, Window 1, offset: 0x34051C */ __I uint32_t DISENG_SIG1_GREENSUM_STATS1_WIN1; /**< Green Component Sum Register, Statistics Block 1, Window 1, offset: 0x340520 */ __I uint32_t DISENG_SIG1_BLUESUM_STATS1_WIN1; /**< Blue Component Sum Register, Statistics Block 1, Window 1, offset: 0x340524 */ __I uint32_t DISENG_SIG1_PIXCNT_STATS0_WIN2; /**< Pixel Counter Register, Statistics Block 0, Window 2, offset: 0x340528 */ __I uint32_t DISENG_SIG1_PIXMAX_STATS0_WIN2; /**< Pixel Max Values Register, Statistics Block 0, Window 2, offset: 0x34052C */ __I uint32_t DISENG_SIG1_PIXMIN_STATS0_WIN2; /**< Pixel Min Values Register, Statistics Block 0, Window 2, offset: 0x340530 */ __I uint32_t DISENG_SIG1_REDSUM_STATS0_WIN2; /**< Red Component Sum Register, Statistics Block 0, Window 2, offset: 0x340534 */ __I uint32_t DISENG_SIG1_GREENSUM_STATS0_WIN2; /**< Green Component Sum Register, Statistics Block 0, Window 2, offset: 0x340538 */ __I uint32_t DISENG_SIG1_BLUESUM_STATS0_WIN2; /**< Blue Component Sum Register, Statistics Block 0, Window 2, offset: 0x34053C */ __I uint32_t DISENG_SIG1_LUMSUM_STATS0_WIN2; /**< Luminance Sum Register, Statistics Block 0, Window 2, offset: 0x340540 */ __I uint32_t DISENG_SIG1_PIXCNT_STATS1_WIN2; /**< Pixel Counter Register, Statistics Block 1, Window 2, offset: 0x340544 */ __I uint32_t DISENG_SIG1_PIXMAX_STATS1_WIN2; /**< Pixel Max Values Register, Statistics Block 1, Window 2, offset: 0x340548 */ __I uint32_t DISENG_SIG1_PIXMIN_STATS1_WIN2; /**< Pixel Min Values Register, Statistics Block 1, Window 2, offset: 0x34054C */ __I uint32_t DISENG_SIG1_REDSUM_STATS1_WIN2; /**< Red Component Sum Register, Statistics Block 1, Window 2, offset: 0x340550 */ __I uint32_t DISENG_SIG1_GREENSUM_STATS1_WIN2; /**< Green Component Sum Register, Statistics Block 1, Window 2, offset: 0x340554 */ __I uint32_t DISENG_SIG1_BLUESUM_STATS1_WIN2; /**< Blue Component Sum Register, Statistics Block 1, Window 2, offset: 0x340558 */ __I uint32_t DISENG_SIG1_PIXCNT_STATS0_WIN3; /**< Pixel Counter Register, Statistics Block 0, Window 3, offset: 0x34055C */ __I uint32_t DISENG_SIG1_PIXMAX_STATS0_WIN3; /**< Pixel Max Values Register, Statistics Block 0, Window 3, offset: 0x340560 */ __I uint32_t DISENG_SIG1_PIXMIN_STATS0_WIN3; /**< Pixel Min Values Register, Statistics Block 0, Window 3, offset: 0x340564 */ __I uint32_t DISENG_SIG1_REDSUM_STATS0_WIN3; /**< Red Component Sum Register, Statistics Block 0, Window 3, offset: 0x340568 */ __I uint32_t DISENG_SIG1_GREENSUM_STATS0_WIN3; /**< Green Component Sum Register, Statistics Block 0, Window 3, offset: 0x34056C */ __I uint32_t DISENG_SIG1_BLUESUM_STATS0_WIN3; /**< Blue Component Sum Register, Statistics Block 0, Window 3, offset: 0x340570 */ __I uint32_t DISENG_SIG1_LUMSUM_STATS0_WIN3; /**< Luminance Sum Register, Statistics Block 0, Window 3, offset: 0x340574 */ __I uint32_t DISENG_SIG1_PIXCNT_STATS1_WIN3; /**< Pixel Counter Register, Statistics Block 1, Window 3, offset: 0x340578 */ __I uint32_t DISENG_SIG1_PIXMAX_STATS1_WIN3; /**< Pixel Max Values Register, Statistics Block 1, Window 3, offset: 0x34057C */ __I uint32_t DISENG_SIG1_PIXMIN_STATS1_WIN3; /**< Pixel Min Values Register, Statistics Block 1, Window 3, offset: 0x340580 */ __I uint32_t DISENG_SIG1_REDSUM_STATS1_WIN3; /**< Red Component Sum Register, Statistics Block 1, Window 3, offset: 0x340584 */ __I uint32_t DISENG_SIG1_GREENSUM_STATS1_WIN3; /**< Green Component Sum Register, Statistics Block 1, Window 3, offset: 0x340588 */ __I uint32_t DISENG_SIG1_BLUESUM_STATS1_WIN3; /**< Blue Component Sum Register, Statistics Block 1, Window 3, offset: 0x34058C */ uint8_t RESERVED_154[2704]; __O uint32_t DISENG_SIG1CFG_LOCKUNLOCK1; /**< Register to change the protection status of this address block., offset: 0x341020 */ __I uint32_t DISENG_SIG1CFG_LOCKSTATUS1; /**< Protection status of this address block., offset: 0x341024 */ __IO uint32_t DISENG_SIG1CFG_SRCSELECT; /**< Tap selection for Signature1., offset: 0x341028 */ uint8_t RESERVED_155[61396]; __O uint32_t DISENG_LUT3D1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x350000 */ __I uint32_t DISENG_LUT3D1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x350004 */ __IO uint32_t DISENG_LUT3D1_STATICCONTROL; /**< lut3d static control register, offset: 0x350008 */ __IO uint32_t DISENG_LUT3D1_CONTROL; /**< lut3d control register, offset: 0x35000C */ uint8_t RESERVED_156[8176]; __IO uint32_t DISENG_LUT3D1_LUT[2048]; /**< Look Up Table, array offset: 0x352000, array step: 0x4 */ uint8_t RESERVED_157[49152]; __O uint32_t DISENG_MATRIX1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x360000 */ __I uint32_t DISENG_MATRIX1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x360004 */ __IO uint32_t DISENG_MATRIX1_STATICCONTROL; /**< Color Matrix static control register, offset: 0x360008 */ __IO uint32_t DISENG_MATRIX1_CONTROL; /**< Color Matrix control register, offset: 0x36000C */ __IO uint32_t DISENG_MATRIX1_RED0; /**< Matrix values for calculation of the red output value., offset: 0x360010 */ __IO uint32_t DISENG_MATRIX1_RED1; /**< Matrix values for calculation of the red output value., offset: 0x360014 */ __IO uint32_t DISENG_MATRIX1_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x360018 */ __IO uint32_t DISENG_MATRIX1_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x36001C */ __IO uint32_t DISENG_MATRIX1_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x360020 */ __IO uint32_t DISENG_MATRIX1_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x360024 */ uint8_t RESERVED_158[8]; __IO uint32_t DISENG_MATRIX1_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x360030 */ __IO uint32_t DISENG_MATRIX1_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x360034 */ __I uint32_t DISENG_MATRIX1_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x360038 */ uint8_t RESERVED_159[65476]; __O uint32_t DISENG_DITHER1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x370000 */ __I uint32_t DISENG_DITHER1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x370004 */ __IO uint32_t DISENG_DITHER1_CONTROL; /**< Dither Unit common control., offset: 0x370008 */ __IO uint32_t DISENG_DITHER1_DITHERCONTROL10BITS; /**< Dither Unit processing control., offset: 0x37000C */ __IO uint32_t DISENG_DITHER1_DITHERCONTROL12BITS; /**< Dither Unit processing control., offset: 0x370010 */ uint8_t RESERVED_160[4108]; __O uint32_t DISENG_DITHER1CFG_LOCKUNLOCK1; /**< Register to change the protection status of this address block., offset: 0x371020 */ __I uint32_t DISENG_DITHER1CFG_LOCKSTATUS1; /**< Protection status of this address block., offset: 0x371024 */ __IO uint32_t DISENG_DITHER1CFG_POLARITYCTRL1; /**< Polarity control for display stream #1., offset: 0x371028 */ uint8_t RESERVED_161[65492]; __O uint32_t DISPIRQ0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x381000 */ __I uint32_t DISPIRQ0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x381004 */ __IO uint32_t DISPIRQ0_INTERRUPTENABLE0; /**< Interrupt Enable register 0., offset: 0x381008 */ __IO uint32_t DISPIRQ0_INTERRUPTENABLE1; /**< Interrupt Enable register 1., offset: 0x38100C */ __IO uint32_t DISPIRQ0_INTERRUPTENABLE2; /**< Interrupt Enable register 2., offset: 0x381010 */ __O uint32_t DISPIRQ0_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x381014 */ __O uint32_t DISPIRQ0_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x381018 */ __O uint32_t DISPIRQ0_INTERRUPTPRESET2; /**< Interrupt Preset register 2, offset: 0x38101C */ __O uint32_t DISPIRQ0_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x381020 */ __O uint32_t DISPIRQ0_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x381024 */ __O uint32_t DISPIRQ0_INTERRUPTCLEAR2; /**< Interrupt Clear register 2, offset: 0x381028 */ __I uint32_t DISPIRQ0_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x38102C */ __I uint32_t DISPIRQ0_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x381030 */ __I uint32_t DISPIRQ0_INTERRUPTSTATUS2; /**< Interrupt Status register 2, offset: 0x381034 */ uint8_t RESERVED_162[65480]; __O uint32_t DISPIRQ1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x391000 */ __I uint32_t DISPIRQ1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x391004 */ __IO uint32_t DISPIRQ1_INTERRUPTENABLE0; /**< Interrupt Enable register 0., offset: 0x391008 */ __IO uint32_t DISPIRQ1_INTERRUPTENABLE1; /**< Interrupt Enable register 1., offset: 0x39100C */ __IO uint32_t DISPIRQ1_INTERRUPTENABLE2; /**< Interrupt Enable register 2., offset: 0x391010 */ __O uint32_t DISPIRQ1_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x391014 */ __O uint32_t DISPIRQ1_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x391018 */ __O uint32_t DISPIRQ1_INTERRUPTPRESET2; /**< Interrupt Preset register 2, offset: 0x39101C */ __O uint32_t DISPIRQ1_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x391020 */ __O uint32_t DISPIRQ1_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x391024 */ __O uint32_t DISPIRQ1_INTERRUPTCLEAR2; /**< Interrupt Clear register 2, offset: 0x391028 */ __I uint32_t DISPIRQ1_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x39102C */ __I uint32_t DISPIRQ1_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x391030 */ __I uint32_t DISPIRQ1_INTERRUPTSTATUS2; /**< Interrupt Status register 2, offset: 0x391034 */ uint8_t RESERVED_163[65480]; __O uint32_t DISPIRQ2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3A1000 */ __I uint32_t DISPIRQ2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3A1004 */ __IO uint32_t DISPIRQ2_INTERRUPTENABLE0; /**< Interrupt Enable register 0., offset: 0x3A1008 */ __IO uint32_t DISPIRQ2_INTERRUPTENABLE1; /**< Interrupt Enable register 1., offset: 0x3A100C */ __IO uint32_t DISPIRQ2_INTERRUPTENABLE2; /**< Interrupt Enable register 2., offset: 0x3A1010 */ __O uint32_t DISPIRQ2_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x3A1014 */ __O uint32_t DISPIRQ2_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x3A1018 */ __O uint32_t DISPIRQ2_INTERRUPTPRESET2; /**< Interrupt Preset register 2, offset: 0x3A101C */ __O uint32_t DISPIRQ2_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x3A1020 */ __O uint32_t DISPIRQ2_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x3A1024 */ __O uint32_t DISPIRQ2_INTERRUPTCLEAR2; /**< Interrupt Clear register 2, offset: 0x3A1028 */ __I uint32_t DISPIRQ2_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x3A102C */ __I uint32_t DISPIRQ2_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x3A1030 */ __I uint32_t DISPIRQ2_INTERRUPTSTATUS2; /**< Interrupt Status register 2, offset: 0x3A1034 */ uint8_t RESERVED_164[65480]; __O uint32_t DISPIRQ3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3B1000 */ __I uint32_t DISPIRQ3_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3B1004 */ __IO uint32_t DISPIRQ3_INTERRUPTENABLE0; /**< Interrupt Enable register 0., offset: 0x3B1008 */ __IO uint32_t DISPIRQ3_INTERRUPTENABLE1; /**< Interrupt Enable register 1., offset: 0x3B100C */ __IO uint32_t DISPIRQ3_INTERRUPTENABLE2; /**< Interrupt Enable register 2., offset: 0x3B1010 */ __O uint32_t DISPIRQ3_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x3B1014 */ __O uint32_t DISPIRQ3_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x3B1018 */ __O uint32_t DISPIRQ3_INTERRUPTPRESET2; /**< Interrupt Preset register 2, offset: 0x3B101C */ __O uint32_t DISPIRQ3_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x3B1020 */ __O uint32_t DISPIRQ3_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x3B1024 */ __O uint32_t DISPIRQ3_INTERRUPTCLEAR2; /**< Interrupt Clear register 2, offset: 0x3B1028 */ __I uint32_t DISPIRQ3_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x3B102C */ __I uint32_t DISPIRQ3_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x3B1030 */ __I uint32_t DISPIRQ3_INTERRUPTSTATUS2; /**< Interrupt Status register 2, offset: 0x3B1034 */ } DISPLAY_SEERIS_Type; /* ---------------------------------------------------------------------------- -- DISPLAY_SEERIS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_SEERIS_Register_Masks DISPLAY_SEERIS Register Masks * @{ */ /*! @name COMCTRL_IPIDENTIFIER - IP Identifier for this SEERIS derivate. */ /*! @{ */ #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_Reserved_MASK (0xFU) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_Reserved_SHIFT (0U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_Reserved(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_Reserved_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_Reserved_MASK) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignDeliveryID_MASK (0xF0U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignDeliveryID_SHIFT (4U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignDeliveryID(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignDeliveryID_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignDeliveryID_MASK) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignMaturityLevel_MASK (0xF00U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignMaturityLevel_SHIFT (8U) /*! comctrl_DesignMaturityLevel * 0b0001..Pre feasibility study. * 0b0010..Feasibility study. * 0b0011..Functionality complete. * 0b0100..Verification complete. */ #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignMaturityLevel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignMaturityLevel_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_DesignMaturityLevel_MASK) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPEvolution_MASK (0xF000U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPEvolution_SHIFT (12U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPEvolution(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPEvolution_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPEvolution_MASK) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFeatureSet_MASK (0xF0000U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFeatureSet_SHIFT (16U) /*! comctrl_IPFeatureSet * 0b0001..Minimal functionality (Eco). * 0b0010..Reduced functionality (Light). * 0b0100..Advanced functionality (Plus). * 0b0101..Extensive functionality (eXtensive). * 0b0110..Standard functionality (Regular). */ #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFeatureSet(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFeatureSet_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFeatureSet_MASK) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPApplication_MASK (0xF00000U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPApplication_SHIFT (20U) /*! comctrl_IPApplication * 0b0001..Blit Engine only. * 0b0010..Blit Engine and Display Controller. * 0b0011..Display Controller only (with direct capture). * 0b0100..Blit Engine, Display Controller (with direct capture), Capture Controller (buffered capture) and Drawing Engine. * 0b0101..Display Controller only. * 0b0110..Capture Controller only. */ #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPApplication(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPApplication_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPApplication_MASK) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPConfiguration_MASK (0xF000000U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPConfiguration_SHIFT (24U) /*! comctrl_IPConfiguration * 0b0001..Graphics core only (Module). * 0b0010..Subsystem including a graphics core (System). */ #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPConfiguration(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPConfiguration_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPConfiguration_MASK) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFamily_MASK (0xF0000000U) #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFamily_SHIFT (28U) /*! comctrl_IPFamily * 0b0000..SEERIS building block generation 2010. * 0b0001..SEERIS building block generation 2012. * 0b0010..SEERIS building block generation 2013. */ #define DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFamily(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFamily_SHIFT)) & DISPLAY_SEERIS_COMCTRL_IPIDENTIFIER_comctrl_IPFamily_MASK) /*! @} */ /*! @name IRQ_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_LOCKUNLOCK_irq_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_LOCKUNLOCK_irq_LockUnlock_SHIFT (0U) /*! irq_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_IRQ_LOCKUNLOCK_irq_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_LOCKUNLOCK_irq_LockUnlock_SHIFT)) & DISPLAY_SEERIS_IRQ_LOCKUNLOCK_irq_LockUnlock_MASK) /*! @} */ /*! @name IRQ_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_LockStatus_SHIFT)) & DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_LockStatus_MASK) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_IRQ_LOCKSTATUS_irq_FreezeStatus_MASK) /*! @} */ /*! @name IRQ_INTERRUPTENABLE0 - Interrupt Enable register 0. */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE0_irq_InterruptEnable0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE0_irq_InterruptEnable0_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE0_irq_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTENABLE0_irq_InterruptEnable0_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTENABLE0_irq_InterruptEnable0_MASK) /*! @} */ /*! @name IRQ_INTERRUPTENABLE1 - Interrupt Enable register 1. */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE1_irq_InterruptEnable1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE1_irq_InterruptEnable1_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE1_irq_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTENABLE1_irq_InterruptEnable1_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTENABLE1_irq_InterruptEnable1_MASK) /*! @} */ /*! @name IRQ_INTERRUPTENABLE2 - Interrupt Enable register 2. */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE2_irq_InterruptEnable2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE2_irq_InterruptEnable2_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTENABLE2_irq_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTENABLE2_irq_InterruptEnable2_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTENABLE2_irq_InterruptEnable2_MASK) /*! @} */ /*! @name IRQ_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET0_irq_InterruptPreset0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET0_irq_InterruptPreset0_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET0_irq_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTPRESET0_irq_InterruptPreset0_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTPRESET0_irq_InterruptPreset0_MASK) /*! @} */ /*! @name IRQ_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET1_irq_InterruptPreset1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET1_irq_InterruptPreset1_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET1_irq_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTPRESET1_irq_InterruptPreset1_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTPRESET1_irq_InterruptPreset1_MASK) /*! @} */ /*! @name IRQ_INTERRUPTPRESET2 - Interrupt Preset register 2 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET2_irq_InterruptPreset2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET2_irq_InterruptPreset2_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTPRESET2_irq_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTPRESET2_irq_InterruptPreset2_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTPRESET2_irq_InterruptPreset2_MASK) /*! @} */ /*! @name IRQ_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR0_irq_InterruptClear0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR0_irq_InterruptClear0_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR0_irq_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR0_irq_InterruptClear0_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR0_irq_InterruptClear0_MASK) /*! @} */ /*! @name IRQ_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR1_irq_InterruptClear1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR1_irq_InterruptClear1_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR1_irq_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR1_irq_InterruptClear1_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR1_irq_InterruptClear1_MASK) /*! @} */ /*! @name IRQ_INTERRUPTCLEAR2 - Interrupt Clear register 2 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR2_irq_InterruptClear2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR2_irq_InterruptClear2_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR2_irq_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR2_irq_InterruptClear2_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTCLEAR2_irq_InterruptClear2_MASK) /*! @} */ /*! @name IRQ_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS0_irq_InterruptStatus0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS0_irq_InterruptStatus0_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS0_irq_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS0_irq_InterruptStatus0_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS0_irq_InterruptStatus0_MASK) /*! @} */ /*! @name IRQ_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS1_irq_InterruptStatus1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS1_irq_InterruptStatus1_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS1_irq_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS1_irq_InterruptStatus1_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS1_irq_InterruptStatus1_MASK) /*! @} */ /*! @name IRQ_INTERRUPTSTATUS2 - Interrupt Status register 2 */ /*! @{ */ #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS2_irq_InterruptStatus2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS2_irq_InterruptStatus2_SHIFT (0U) #define DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS2_irq_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS2_irq_InterruptStatus2_SHIFT)) & DISPLAY_SEERIS_IRQ_INTERRUPTSTATUS2_irq_InterruptStatus2_MASK) /*! @} */ /*! @name DOMAINMASK_MASKLOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKUNLOCK_domainmask_MaskLockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKUNLOCK_domainmask_MaskLockUnlock_SHIFT (0U) /*! domainmask_MaskLockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKUNLOCK_domainmask_MaskLockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_MASKLOCKUNLOCK_domainmask_MaskLockUnlock_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_MASKLOCKUNLOCK_domainmask_MaskLockUnlock_MASK) /*! @} */ /*! @name DOMAINMASK_MASKLOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskLockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskLockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskLockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskLockStatus_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskLockStatus_MASK) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskPrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskPrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskPrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskPrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskPrivilegeStatus_MASK) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskFreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskFreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskFreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskFreezeStatus_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_MASKLOCKSTATUS_domainmask_MaskFreezeStatus_MASK) /*! @} */ /*! @name DOMAINMASK_STORE9_DOMAIN_MASK0 - Pixel Engine domain mask 0 for endpoint store9. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_rop9_MASK (0x1U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_rop9_SHIFT (0U) /*! domainmask_store9_dm_rop9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_rop9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_rop9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_rop9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_clut9_MASK (0x2U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_clut9_SHIFT (1U) /*! domainmask_store9_dm_clut9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_clut9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_clut9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_clut9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix9_MASK (0x4U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix9_SHIFT (2U) /*! domainmask_store9_dm_matrix9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_blitblend9_MASK (0x8U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_blitblend9_SHIFT (3U) /*! domainmask_store9_dm_blitblend9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_blitblend9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_blitblend9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_blitblend9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchrot9_MASK (0x10U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchrot9_SHIFT (4U) /*! domainmask_store9_dm_fetchrot9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchrot9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchrot9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchrot9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchdecode9_MASK (0x20U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchdecode9_SHIFT (5U) /*! domainmask_store9_dm_fetchdecode9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchdecode9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchdecode9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchdecode9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco9_MASK (0x40U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco9_SHIFT (6U) /*! domainmask_store9_dm_fetcheco9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler9_MASK (0x80U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler9_SHIFT (7U) /*! domainmask_store9_dm_hscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler9_MASK (0x100U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler9_SHIFT (8U) /*! domainmask_store9_dm_vscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_filter9_MASK (0x200U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_filter9_SHIFT (9U) /*! domainmask_store9_dm_filter9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_filter9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_filter9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_filter9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe0_MASK (0x400U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe0_SHIFT (10U) /*! domainmask_store9_dm_constframe0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe4_MASK (0x800U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe4_SHIFT (11U) /*! domainmask_store9_dm_constframe4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe1_MASK (0x1000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe1_SHIFT (12U) /*! domainmask_store9_dm_constframe1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe5_MASK (0x2000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe5_SHIFT (13U) /*! domainmask_store9_dm_constframe5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_constframe5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend1_MASK (0x4000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend1_SHIFT (14U) /*! domainmask_store9_dm_layerblend1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend2_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend2_SHIFT (15U) /*! domainmask_store9_dm_layerblend2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend3_MASK (0x10000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend3_SHIFT (16U) /*! domainmask_store9_dm_layerblend3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend4_MASK (0x20000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend4_SHIFT (17U) /*! domainmask_store9_dm_layerblend4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend5_MASK (0x40000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend5_SHIFT (18U) /*! domainmask_store9_dm_layerblend5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend6_MASK (0x80000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend6_SHIFT (19U) /*! domainmask_store9_dm_layerblend6 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend6_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_layerblend6_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer0_MASK (0x100000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer0_SHIFT (20U) /*! domainmask_store9_dm_fetchlayer0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer1_MASK (0x200000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer1_SHIFT (21U) /*! domainmask_store9_dm_fetchlayer1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchlayer1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv3_MASK (0x400000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv3_SHIFT (22U) /*! domainmask_store9_dm_fetchyuv3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv0_MASK (0x800000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv0_SHIFT (23U) /*! domainmask_store9_dm_fetchyuv0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco0_MASK (0x1000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco0_SHIFT (24U) /*! domainmask_store9_dm_fetcheco0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv1_MASK (0x2000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv1_SHIFT (25U) /*! domainmask_store9_dm_fetchyuv1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco1_MASK (0x4000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco1_SHIFT (26U) /*! domainmask_store9_dm_fetcheco1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv2_MASK (0x8000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv2_SHIFT (27U) /*! domainmask_store9_dm_fetchyuv2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetchyuv2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco2_MASK (0x10000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco2_SHIFT (28U) /*! domainmask_store9_dm_fetcheco2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_fetcheco2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix4_MASK (0x20000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix4_SHIFT (29U) /*! domainmask_store9_dm_matrix4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_matrix4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler4_MASK (0x40000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler4_SHIFT (30U) /*! domainmask_store9_dm_hscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_hscaler4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler4_MASK (0x80000000U) #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler4_SHIFT (31U) /*! domainmask_store9_dm_vscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_STORE9_DOMAIN_MASK0_domainmask_store9_dm_vscaler4_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST0_DOMAIN_MASK0 - Pixel Engine domain mask 0 for endpoint extdst0. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_rop9_MASK (0x1U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_rop9_SHIFT (0U) /*! domainmask_extdst0_dm_rop9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_rop9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_rop9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_rop9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_clut9_MASK (0x2U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_clut9_SHIFT (1U) /*! domainmask_extdst0_dm_clut9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_clut9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_clut9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_clut9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix9_MASK (0x4U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix9_SHIFT (2U) /*! domainmask_extdst0_dm_matrix9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_blitblend9_MASK (0x8U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_blitblend9_SHIFT (3U) /*! domainmask_extdst0_dm_blitblend9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_blitblend9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_blitblend9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_blitblend9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchrot9_MASK (0x10U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchrot9_SHIFT (4U) /*! domainmask_extdst0_dm_fetchrot9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchrot9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchrot9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchrot9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchdecode9_MASK (0x20U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchdecode9_SHIFT (5U) /*! domainmask_extdst0_dm_fetchdecode9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchdecode9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchdecode9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchdecode9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco9_MASK (0x40U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco9_SHIFT (6U) /*! domainmask_extdst0_dm_fetcheco9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler9_MASK (0x80U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler9_SHIFT (7U) /*! domainmask_extdst0_dm_hscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler9_MASK (0x100U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler9_SHIFT (8U) /*! domainmask_extdst0_dm_vscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_filter9_MASK (0x200U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_filter9_SHIFT (9U) /*! domainmask_extdst0_dm_filter9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_filter9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_filter9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_filter9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe0_MASK (0x400U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe0_SHIFT (10U) /*! domainmask_extdst0_dm_constframe0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe4_MASK (0x800U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe4_SHIFT (11U) /*! domainmask_extdst0_dm_constframe4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe1_MASK (0x1000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe1_SHIFT (12U) /*! domainmask_extdst0_dm_constframe1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe5_MASK (0x2000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe5_SHIFT (13U) /*! domainmask_extdst0_dm_constframe5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_constframe5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend1_MASK (0x4000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend1_SHIFT (14U) /*! domainmask_extdst0_dm_layerblend1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend2_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend2_SHIFT (15U) /*! domainmask_extdst0_dm_layerblend2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend3_MASK (0x10000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend3_SHIFT (16U) /*! domainmask_extdst0_dm_layerblend3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend4_MASK (0x20000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend4_SHIFT (17U) /*! domainmask_extdst0_dm_layerblend4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend5_MASK (0x40000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend5_SHIFT (18U) /*! domainmask_extdst0_dm_layerblend5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend6_MASK (0x80000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend6_SHIFT (19U) /*! domainmask_extdst0_dm_layerblend6 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend6_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_layerblend6_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer0_MASK (0x100000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer0_SHIFT (20U) /*! domainmask_extdst0_dm_fetchlayer0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer1_MASK (0x200000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer1_SHIFT (21U) /*! domainmask_extdst0_dm_fetchlayer1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchlayer1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv3_MASK (0x400000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv3_SHIFT (22U) /*! domainmask_extdst0_dm_fetchyuv3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv0_MASK (0x800000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv0_SHIFT (23U) /*! domainmask_extdst0_dm_fetchyuv0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco0_MASK (0x1000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco0_SHIFT (24U) /*! domainmask_extdst0_dm_fetcheco0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv1_MASK (0x2000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv1_SHIFT (25U) /*! domainmask_extdst0_dm_fetchyuv1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco1_MASK (0x4000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco1_SHIFT (26U) /*! domainmask_extdst0_dm_fetcheco1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv2_MASK (0x8000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv2_SHIFT (27U) /*! domainmask_extdst0_dm_fetchyuv2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetchyuv2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco2_MASK (0x10000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco2_SHIFT (28U) /*! domainmask_extdst0_dm_fetcheco2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_fetcheco2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix4_MASK (0x20000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix4_SHIFT (29U) /*! domainmask_extdst0_dm_matrix4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_matrix4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler4_MASK (0x40000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler4_SHIFT (30U) /*! domainmask_extdst0_dm_hscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_hscaler4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler4_MASK (0x80000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler4_SHIFT (31U) /*! domainmask_extdst0_dm_vscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_DOMAIN_MASK0_domainmask_extdst0_dm_vscaler4_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST4_DOMAIN_MASK0 - Pixel Engine domain mask 0 for endpoint extdst4. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_rop9_MASK (0x1U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_rop9_SHIFT (0U) /*! domainmask_extdst4_dm_rop9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_rop9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_rop9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_rop9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_clut9_MASK (0x2U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_clut9_SHIFT (1U) /*! domainmask_extdst4_dm_clut9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_clut9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_clut9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_clut9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix9_MASK (0x4U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix9_SHIFT (2U) /*! domainmask_extdst4_dm_matrix9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_blitblend9_MASK (0x8U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_blitblend9_SHIFT (3U) /*! domainmask_extdst4_dm_blitblend9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_blitblend9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_blitblend9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_blitblend9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchrot9_MASK (0x10U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchrot9_SHIFT (4U) /*! domainmask_extdst4_dm_fetchrot9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchrot9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchrot9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchrot9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchdecode9_MASK (0x20U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchdecode9_SHIFT (5U) /*! domainmask_extdst4_dm_fetchdecode9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchdecode9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchdecode9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchdecode9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco9_MASK (0x40U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco9_SHIFT (6U) /*! domainmask_extdst4_dm_fetcheco9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler9_MASK (0x80U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler9_SHIFT (7U) /*! domainmask_extdst4_dm_hscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler9_MASK (0x100U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler9_SHIFT (8U) /*! domainmask_extdst4_dm_vscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_filter9_MASK (0x200U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_filter9_SHIFT (9U) /*! domainmask_extdst4_dm_filter9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_filter9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_filter9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_filter9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe0_MASK (0x400U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe0_SHIFT (10U) /*! domainmask_extdst4_dm_constframe0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe4_MASK (0x800U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe4_SHIFT (11U) /*! domainmask_extdst4_dm_constframe4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe1_MASK (0x1000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe1_SHIFT (12U) /*! domainmask_extdst4_dm_constframe1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe5_MASK (0x2000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe5_SHIFT (13U) /*! domainmask_extdst4_dm_constframe5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_constframe5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend1_MASK (0x4000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend1_SHIFT (14U) /*! domainmask_extdst4_dm_layerblend1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend2_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend2_SHIFT (15U) /*! domainmask_extdst4_dm_layerblend2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend3_MASK (0x10000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend3_SHIFT (16U) /*! domainmask_extdst4_dm_layerblend3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend4_MASK (0x20000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend4_SHIFT (17U) /*! domainmask_extdst4_dm_layerblend4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend5_MASK (0x40000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend5_SHIFT (18U) /*! domainmask_extdst4_dm_layerblend5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend6_MASK (0x80000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend6_SHIFT (19U) /*! domainmask_extdst4_dm_layerblend6 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend6_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_layerblend6_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer0_MASK (0x100000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer0_SHIFT (20U) /*! domainmask_extdst4_dm_fetchlayer0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer1_MASK (0x200000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer1_SHIFT (21U) /*! domainmask_extdst4_dm_fetchlayer1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchlayer1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv3_MASK (0x400000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv3_SHIFT (22U) /*! domainmask_extdst4_dm_fetchyuv3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv0_MASK (0x800000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv0_SHIFT (23U) /*! domainmask_extdst4_dm_fetchyuv0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco0_MASK (0x1000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco0_SHIFT (24U) /*! domainmask_extdst4_dm_fetcheco0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv1_MASK (0x2000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv1_SHIFT (25U) /*! domainmask_extdst4_dm_fetchyuv1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco1_MASK (0x4000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco1_SHIFT (26U) /*! domainmask_extdst4_dm_fetcheco1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv2_MASK (0x8000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv2_SHIFT (27U) /*! domainmask_extdst4_dm_fetchyuv2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetchyuv2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco2_MASK (0x10000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco2_SHIFT (28U) /*! domainmask_extdst4_dm_fetcheco2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_fetcheco2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix4_MASK (0x20000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix4_SHIFT (29U) /*! domainmask_extdst4_dm_matrix4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_matrix4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler4_MASK (0x40000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler4_SHIFT (30U) /*! domainmask_extdst4_dm_hscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_hscaler4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler4_MASK (0x80000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler4_SHIFT (31U) /*! domainmask_extdst4_dm_vscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_DOMAIN_MASK0_domainmask_extdst4_dm_vscaler4_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST1_DOMAIN_MASK0 - Pixel Engine domain mask 0 for endpoint extdst1. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_rop9_MASK (0x1U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_rop9_SHIFT (0U) /*! domainmask_extdst1_dm_rop9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_rop9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_rop9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_rop9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_clut9_MASK (0x2U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_clut9_SHIFT (1U) /*! domainmask_extdst1_dm_clut9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_clut9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_clut9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_clut9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix9_MASK (0x4U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix9_SHIFT (2U) /*! domainmask_extdst1_dm_matrix9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_blitblend9_MASK (0x8U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_blitblend9_SHIFT (3U) /*! domainmask_extdst1_dm_blitblend9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_blitblend9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_blitblend9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_blitblend9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchrot9_MASK (0x10U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchrot9_SHIFT (4U) /*! domainmask_extdst1_dm_fetchrot9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchrot9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchrot9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchrot9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchdecode9_MASK (0x20U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchdecode9_SHIFT (5U) /*! domainmask_extdst1_dm_fetchdecode9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchdecode9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchdecode9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchdecode9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco9_MASK (0x40U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco9_SHIFT (6U) /*! domainmask_extdst1_dm_fetcheco9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler9_MASK (0x80U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler9_SHIFT (7U) /*! domainmask_extdst1_dm_hscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler9_MASK (0x100U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler9_SHIFT (8U) /*! domainmask_extdst1_dm_vscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_filter9_MASK (0x200U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_filter9_SHIFT (9U) /*! domainmask_extdst1_dm_filter9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_filter9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_filter9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_filter9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe0_MASK (0x400U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe0_SHIFT (10U) /*! domainmask_extdst1_dm_constframe0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe4_MASK (0x800U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe4_SHIFT (11U) /*! domainmask_extdst1_dm_constframe4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe1_MASK (0x1000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe1_SHIFT (12U) /*! domainmask_extdst1_dm_constframe1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe5_MASK (0x2000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe5_SHIFT (13U) /*! domainmask_extdst1_dm_constframe5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_constframe5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend1_MASK (0x4000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend1_SHIFT (14U) /*! domainmask_extdst1_dm_layerblend1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend2_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend2_SHIFT (15U) /*! domainmask_extdst1_dm_layerblend2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend3_MASK (0x10000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend3_SHIFT (16U) /*! domainmask_extdst1_dm_layerblend3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend4_MASK (0x20000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend4_SHIFT (17U) /*! domainmask_extdst1_dm_layerblend4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend5_MASK (0x40000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend5_SHIFT (18U) /*! domainmask_extdst1_dm_layerblend5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend6_MASK (0x80000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend6_SHIFT (19U) /*! domainmask_extdst1_dm_layerblend6 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend6_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_layerblend6_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer0_MASK (0x100000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer0_SHIFT (20U) /*! domainmask_extdst1_dm_fetchlayer0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer1_MASK (0x200000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer1_SHIFT (21U) /*! domainmask_extdst1_dm_fetchlayer1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchlayer1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv3_MASK (0x400000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv3_SHIFT (22U) /*! domainmask_extdst1_dm_fetchyuv3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv0_MASK (0x800000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv0_SHIFT (23U) /*! domainmask_extdst1_dm_fetchyuv0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco0_MASK (0x1000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco0_SHIFT (24U) /*! domainmask_extdst1_dm_fetcheco0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv1_MASK (0x2000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv1_SHIFT (25U) /*! domainmask_extdst1_dm_fetchyuv1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco1_MASK (0x4000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco1_SHIFT (26U) /*! domainmask_extdst1_dm_fetcheco1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv2_MASK (0x8000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv2_SHIFT (27U) /*! domainmask_extdst1_dm_fetchyuv2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetchyuv2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco2_MASK (0x10000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco2_SHIFT (28U) /*! domainmask_extdst1_dm_fetcheco2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_fetcheco2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix4_MASK (0x20000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix4_SHIFT (29U) /*! domainmask_extdst1_dm_matrix4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_matrix4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler4_MASK (0x40000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler4_SHIFT (30U) /*! domainmask_extdst1_dm_hscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_hscaler4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler4_MASK (0x80000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler4_SHIFT (31U) /*! domainmask_extdst1_dm_vscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_DOMAIN_MASK0_domainmask_extdst1_dm_vscaler4_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST5_DOMAIN_MASK0 - Pixel Engine domain mask 0 for endpoint extdst5. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_rop9_MASK (0x1U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_rop9_SHIFT (0U) /*! domainmask_extdst5_dm_rop9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_rop9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_rop9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_rop9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_clut9_MASK (0x2U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_clut9_SHIFT (1U) /*! domainmask_extdst5_dm_clut9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_clut9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_clut9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_clut9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix9_MASK (0x4U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix9_SHIFT (2U) /*! domainmask_extdst5_dm_matrix9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_blitblend9_MASK (0x8U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_blitblend9_SHIFT (3U) /*! domainmask_extdst5_dm_blitblend9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_blitblend9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_blitblend9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_blitblend9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchrot9_MASK (0x10U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchrot9_SHIFT (4U) /*! domainmask_extdst5_dm_fetchrot9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchrot9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchrot9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchrot9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchdecode9_MASK (0x20U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchdecode9_SHIFT (5U) /*! domainmask_extdst5_dm_fetchdecode9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchdecode9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchdecode9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchdecode9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco9_MASK (0x40U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco9_SHIFT (6U) /*! domainmask_extdst5_dm_fetcheco9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler9_MASK (0x80U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler9_SHIFT (7U) /*! domainmask_extdst5_dm_hscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler9_MASK (0x100U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler9_SHIFT (8U) /*! domainmask_extdst5_dm_vscaler9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_filter9_MASK (0x200U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_filter9_SHIFT (9U) /*! domainmask_extdst5_dm_filter9 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_filter9(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_filter9_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_filter9_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe0_MASK (0x400U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe0_SHIFT (10U) /*! domainmask_extdst5_dm_constframe0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe4_MASK (0x800U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe4_SHIFT (11U) /*! domainmask_extdst5_dm_constframe4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe1_MASK (0x1000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe1_SHIFT (12U) /*! domainmask_extdst5_dm_constframe1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe5_MASK (0x2000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe5_SHIFT (13U) /*! domainmask_extdst5_dm_constframe5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_constframe5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend1_MASK (0x4000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend1_SHIFT (14U) /*! domainmask_extdst5_dm_layerblend1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend2_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend2_SHIFT (15U) /*! domainmask_extdst5_dm_layerblend2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend3_MASK (0x10000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend3_SHIFT (16U) /*! domainmask_extdst5_dm_layerblend3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend4_MASK (0x20000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend4_SHIFT (17U) /*! domainmask_extdst5_dm_layerblend4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend5_MASK (0x40000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend5_SHIFT (18U) /*! domainmask_extdst5_dm_layerblend5 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend5_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend5_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend6_MASK (0x80000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend6_SHIFT (19U) /*! domainmask_extdst5_dm_layerblend6 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend6_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_layerblend6_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer0_MASK (0x100000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer0_SHIFT (20U) /*! domainmask_extdst5_dm_fetchlayer0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer1_MASK (0x200000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer1_SHIFT (21U) /*! domainmask_extdst5_dm_fetchlayer1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchlayer1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv3_MASK (0x400000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv3_SHIFT (22U) /*! domainmask_extdst5_dm_fetchyuv3 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv3_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv3_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv0_MASK (0x800000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv0_SHIFT (23U) /*! domainmask_extdst5_dm_fetchyuv0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco0_MASK (0x1000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco0_SHIFT (24U) /*! domainmask_extdst5_dm_fetcheco0 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco0_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco0_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv1_MASK (0x2000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv1_SHIFT (25U) /*! domainmask_extdst5_dm_fetchyuv1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco1_MASK (0x4000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco1_SHIFT (26U) /*! domainmask_extdst5_dm_fetcheco1 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco1_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco1_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv2_MASK (0x8000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv2_SHIFT (27U) /*! domainmask_extdst5_dm_fetchyuv2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetchyuv2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco2_MASK (0x10000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco2_SHIFT (28U) /*! domainmask_extdst5_dm_fetcheco2 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco2_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_fetcheco2_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix4_MASK (0x20000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix4_SHIFT (29U) /*! domainmask_extdst5_dm_matrix4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_matrix4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler4_MASK (0x40000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler4_SHIFT (30U) /*! domainmask_extdst5_dm_hscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_hscaler4_MASK) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler4_MASK (0x80000000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler4_SHIFT (31U) /*! domainmask_extdst5_dm_vscaler4 * 0b0..Module is prohibited. * 0b1..Module is allowed. */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler4_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_DOMAIN_MASK0_domainmask_extdst5_dm_vscaler4_MASK) /*! @} */ /*! @name DOMAINMASK_SEERIS_DISPLAY_STATIC - Global settings for SEERIS Display configuration. */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_SEERIS_DISPLAY_STATIC_domainmask_display_pipeline_synchronization_MASK (0x1U) #define DISPLAY_SEERIS_DOMAINMASK_SEERIS_DISPLAY_STATIC_domainmask_display_pipeline_synchronization_SHIFT (0U) /*! domainmask_display_pipeline_synchronization * 0b0..Display pipeline synchronization is disabled * 0b1..Display pipeline synchronization is enabled */ #define DISPLAY_SEERIS_DOMAINMASK_SEERIS_DISPLAY_STATIC_domainmask_display_pipeline_synchronization(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_SEERIS_DISPLAY_STATIC_domainmask_display_pipeline_synchronization_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_SEERIS_DISPLAY_STATIC_domainmask_display_pipeline_synchronization_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST0_STATIC - Static pixel engine configuration for extdst0 */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_STATIC_domainmask_extdst0_is_display_master_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_STATIC_domainmask_extdst0_is_display_master_SHIFT (15U) /*! domainmask_extdst0_is_display_master * 0b0..Slave Synchronizer * 0b1..Master Synchronizer */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST0_STATIC_domainmask_extdst0_is_display_master(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST0_STATIC_domainmask_extdst0_is_display_master_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST0_STATIC_domainmask_extdst0_is_display_master_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST4_STATIC - Static pixel engine configuration for extdst4 */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_STATIC_domainmask_extdst4_is_display_master_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_STATIC_domainmask_extdst4_is_display_master_SHIFT (15U) /*! domainmask_extdst4_is_display_master * 0b0..Slave Synchronizer * 0b1..Master Synchronizer */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST4_STATIC_domainmask_extdst4_is_display_master(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST4_STATIC_domainmask_extdst4_is_display_master_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST4_STATIC_domainmask_extdst4_is_display_master_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST1_STATIC - Static pixel engine configuration for extdst1 */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_STATIC_domainmask_extdst1_is_display_master_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_STATIC_domainmask_extdst1_is_display_master_SHIFT (15U) /*! domainmask_extdst1_is_display_master * 0b0..Slave Synchronizer * 0b1..Master Synchronizer */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST1_STATIC_domainmask_extdst1_is_display_master(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST1_STATIC_domainmask_extdst1_is_display_master_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST1_STATIC_domainmask_extdst1_is_display_master_MASK) /*! @} */ /*! @name DOMAINMASK_EXTDST5_STATIC - Static pixel engine configuration for extdst5 */ /*! @{ */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_STATIC_domainmask_extdst5_is_display_master_MASK (0x8000U) #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_STATIC_domainmask_extdst5_is_display_master_SHIFT (15U) /*! domainmask_extdst5_is_display_master * 0b0..Slave Synchronizer * 0b1..Master Synchronizer */ #define DISPLAY_SEERIS_DOMAINMASK_EXTDST5_STATIC_domainmask_extdst5_is_display_master(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DOMAINMASK_EXTDST5_STATIC_domainmask_extdst5_is_display_master_SHIFT)) & DISPLAY_SEERIS_DOMAINMASK_EXTDST5_STATIC_domainmask_extdst5_is_display_master_MASK) /*! @} */ /*! @name CMDSEQMASK_MASKLOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKUNLOCK_cmdseqmask_MaskLockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKUNLOCK_cmdseqmask_MaskLockUnlock_SHIFT (0U) /*! cmdseqmask_MaskLockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKUNLOCK_cmdseqmask_MaskLockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKUNLOCK_cmdseqmask_MaskLockUnlock_SHIFT)) & DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKUNLOCK_cmdseqmask_MaskLockUnlock_MASK) /*! @} */ /*! @name CMDSEQMASK_MASKLOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskLockStatus_MASK (0x1U) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskLockStatus_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskLockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskLockStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskLockStatus_MASK) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskPrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskPrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskPrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskPrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskPrivilegeStatus_MASK) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskFreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskFreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskFreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskFreezeStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQMASK_MASKLOCKSTATUS_cmdseqmask_MaskFreezeStatus_MASK) /*! @} */ /*! @name CMDSEQMASK_CMDSEQ_ACCESS_MASK0 - Each bit describes whether register in the corresponding 64kByte address block is allowed to be written from the command sequencer. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK0_cmdseqmask_cs_access_mask0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK0_cmdseqmask_cs_access_mask0_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK0_cmdseqmask_cs_access_mask0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK0_cmdseqmask_cs_access_mask0_SHIFT)) & DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK0_cmdseqmask_cs_access_mask0_MASK) /*! @} */ /*! @name CMDSEQMASK_CMDSEQ_ACCESS_MASK1 - Each bit describes whether register in the corresponding 64kByte address block is allowed to be written from the command sequencer. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK1_cmdseqmask_cs_access_mask1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK1_cmdseqmask_cs_access_mask1_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK1_cmdseqmask_cs_access_mask1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK1_cmdseqmask_cs_access_mask1_SHIFT)) & DISPLAY_SEERIS_CMDSEQMASK_CMDSEQ_ACCESS_MASK1_cmdseqmask_cs_access_mask1_MASK) /*! @} */ /*! @name CMDSEQ_HIF - Command input buffer */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_HIF_cmdseq_CommandFIFO_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQ_HIF_cmdseq_CommandFIFO_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_HIF_cmdseq_CommandFIFO(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_HIF_cmdseq_CommandFIFO_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_HIF_cmdseq_CommandFIFO_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_CMDSEQ_HIF */ #define DISPLAY_SEERIS_CMDSEQ_HIF_COUNT (64U) /*! @name CMDSEQ_LOCKUNLOCKHIF - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCKHIF_cmdseq_LockUnlockHIF_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCKHIF_cmdseq_LockUnlockHIF_SHIFT (0U) /*! cmdseq_LockUnlockHIF * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCKHIF_cmdseq_LockUnlockHIF(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCKHIF_cmdseq_LockUnlockHIF_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCKHIF_cmdseq_LockUnlockHIF_MASK) /*! @} */ /*! @name CMDSEQ_LOCKSTATUSHIF - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_LockStatusHIF_MASK (0x1U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_LockStatusHIF_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_LockStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_LockStatusHIF_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_LockStatusHIF_MASK) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_PrivilegeStatusHIF_MASK (0x10U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_PrivilegeStatusHIF_SHIFT (4U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_PrivilegeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_PrivilegeStatusHIF_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_PrivilegeStatusHIF_MASK) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_FreezeStatusHIF_MASK (0x100U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_FreezeStatusHIF_SHIFT (8U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_FreezeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_FreezeStatusHIF_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKSTATUSHIF_cmdseq_FreezeStatusHIF_MASK) /*! @} */ /*! @name CMDSEQ_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCK_cmdseq_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCK_cmdseq_LockUnlock_SHIFT (0U) /*! cmdseq_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCK_cmdseq_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCK_cmdseq_LockUnlock_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKUNLOCK_cmdseq_LockUnlock_MASK) /*! @} */ /*! @name CMDSEQ_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_LockStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_LockStatus_MASK) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_LOCKSTATUS_cmdseq_FreezeStatus_MASK) /*! @} */ /*! @name CMDSEQ_BUFFERADDRESS - Command buffer address register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Local_MASK (0x1U) #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Local_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Local(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Local_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Local_MASK) #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Addr_MASK (0xFFFFFFE0U) #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Addr_SHIFT (5U) #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Addr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Addr_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESS_cmdseq_Addr_MASK) /*! @} */ /*! @name CMDSEQ_BUFFERADDRESSMSB - Command buffer address register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESSMSB_cmdseq_AddrMSB_MASK (0xFFU) #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESSMSB_cmdseq_AddrMSB_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESSMSB_cmdseq_AddrMSB(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESSMSB_cmdseq_AddrMSB_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_BUFFERADDRESSMSB_cmdseq_AddrMSB_MASK) /*! @} */ /*! @name CMDSEQ_BUFFERSIZE - Command buffer size register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_BUFFERSIZE_cmdseq_Size_MASK (0xFFF8U) #define DISPLAY_SEERIS_CMDSEQ_BUFFERSIZE_cmdseq_Size_SHIFT (3U) #define DISPLAY_SEERIS_CMDSEQ_BUFFERSIZE_cmdseq_Size(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_BUFFERSIZE_cmdseq_Size_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_BUFFERSIZE_cmdseq_Size_MASK) /*! @} */ /*! @name CMDSEQ_WATERMARKCONTROL - Watermark Control register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_LowWM_MASK (0xFFFFU) #define DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_LowWM_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_LowWM(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_LowWM_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_LowWM_MASK) #define DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_HighWM_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_HighWM_SHIFT (16U) #define DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_HighWM(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_HighWM_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_WATERMARKCONTROL_cmdseq_HighWM_MASK) /*! @} */ /*! @name CMDSEQ_CONTROL - Control register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrAxiw_MASK (0x1U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrAxiw_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrAxiw(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrAxiw_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrAxiw_MASK) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrRbuf_MASK (0x4U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrRbuf_SHIFT (2U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrRbuf(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrRbuf_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrRbuf_MASK) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrCmdBuf_MASK (0x8U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrCmdBuf_SHIFT (3U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrCmdBuf(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrCmdBuf_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_ClrCmdBuf_MASK) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_Clear_MASK (0x10U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_Clear_SHIFT (4U) #define DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_Clear(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_Clear_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_CONTROL_cmdseq_Clear_MASK) /*! @} */ /*! @name CMDSEQ_STATUS - Status register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOSpace_MASK (0x1FFFFU) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOSpace_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOSpace(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOSpace_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOSpace_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOEmpty_MASK (0x1000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOEmpty_SHIFT (24U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOEmpty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOEmpty_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOEmpty_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOFull_MASK (0x2000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOFull_SHIFT (25U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOFull(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOFull_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOFull_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOWMState_MASK (0x4000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOWMState_SHIFT (26U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOWMState(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOWMState_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_FIFOWMState_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Watchdog_MASK (0x8000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Watchdog_SHIFT (27U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Watchdog(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Watchdog_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Watchdog_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ReadBusy_MASK (0x10000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ReadBusy_SHIFT (28U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ReadBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ReadBusy_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ReadBusy_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_WriteBusy_MASK (0x20000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_WriteBusy_SHIFT (29U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_WriteBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_WriteBusy_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_WriteBusy_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Idle_MASK (0x40000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Idle_SHIFT (30U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Idle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Idle_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_Idle_MASK) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ErrorHalt_MASK (0x80000000U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ErrorHalt_SHIFT (31U) #define DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ErrorHalt(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ErrorHalt_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_STATUS_cmdseq_ErrorHalt_MASK) /*! @} */ /*! @name CMDSEQ_PREFETCHWINDOWSTART - PrefetchWindowStart register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTART_cmdseq_PWStart_MASK (0xFFFFFFFCU) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTART_cmdseq_PWStart_SHIFT (2U) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTART_cmdseq_PWStart(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTART_cmdseq_PWStart_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTART_cmdseq_PWStart_MASK) /*! @} */ /*! @name CMDSEQ_PREFETCHWINDOWSTARTMSB - PrefetchWindowStart register MSB bits */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTARTMSB_cmdseq_PWStartMSB_MASK (0xFFU) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTARTMSB_cmdseq_PWStartMSB_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTARTMSB_cmdseq_PWStartMSB(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTARTMSB_cmdseq_PWStartMSB_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWSTARTMSB_cmdseq_PWStartMSB_MASK) /*! @} */ /*! @name CMDSEQ_PREFETCHWINDOWEND - PrefetchWindowEnd register */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWEND_cmdseq_PWEnd_MASK (0xFFFFFFFCU) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWEND_cmdseq_PWEnd_SHIFT (2U) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWEND_cmdseq_PWEnd(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWEND_cmdseq_PWEnd_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWEND_cmdseq_PWEnd_MASK) /*! @} */ /*! @name CMDSEQ_PREFETCHWINDOWENDMSB - PrefetchWindowEnd register MSB bits */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWENDMSB_cmdseq_PWEndMSB_MASK (0xFFU) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWENDMSB_cmdseq_PWEndMSB_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWENDMSB_cmdseq_PWEndMSB(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWENDMSB_cmdseq_PWEndMSB_SHIFT)) & DISPLAY_SEERIS_CMDSEQ_PREFETCHWINDOWENDMSB_cmdseq_PWEndMSB_MASK) /*! @} */ /*! @name CMDSEQIRQ_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKUNLOCK_cmdseqirq_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKUNLOCK_cmdseqirq_LockUnlock_SHIFT (0U) /*! cmdseqirq_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKUNLOCK_cmdseqirq_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_LOCKUNLOCK_cmdseqirq_LockUnlock_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_LOCKUNLOCK_cmdseqirq_LockUnlock_MASK) /*! @} */ /*! @name CMDSEQIRQ_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_LockStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_LockStatus_MASK) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_LOCKSTATUS_cmdseqirq_FreezeStatus_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTENABLE0 - Interrupt Enable register 0. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE0_cmdseqirq_InterruptEnable0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE0_cmdseqirq_InterruptEnable0_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE0_cmdseqirq_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE0_cmdseqirq_InterruptEnable0_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE0_cmdseqirq_InterruptEnable0_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTENABLE1 - Interrupt Enable register 1. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE1_cmdseqirq_InterruptEnable1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE1_cmdseqirq_InterruptEnable1_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE1_cmdseqirq_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE1_cmdseqirq_InterruptEnable1_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE1_cmdseqirq_InterruptEnable1_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTENABLE2 - Interrupt Enable register 2. */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE2_cmdseqirq_InterruptEnable2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE2_cmdseqirq_InterruptEnable2_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE2_cmdseqirq_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE2_cmdseqirq_InterruptEnable2_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTENABLE2_cmdseqirq_InterruptEnable2_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET0_cmdseqirq_InterruptPreset0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET0_cmdseqirq_InterruptPreset0_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET0_cmdseqirq_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET0_cmdseqirq_InterruptPreset0_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET0_cmdseqirq_InterruptPreset0_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET1_cmdseqirq_InterruptPreset1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET1_cmdseqirq_InterruptPreset1_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET1_cmdseqirq_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET1_cmdseqirq_InterruptPreset1_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET1_cmdseqirq_InterruptPreset1_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTPRESET2 - Interrupt Preset register 2 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET2_cmdseqirq_InterruptPreset2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET2_cmdseqirq_InterruptPreset2_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET2_cmdseqirq_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET2_cmdseqirq_InterruptPreset2_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTPRESET2_cmdseqirq_InterruptPreset2_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR0_cmdseqirq_InterruptClear0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR0_cmdseqirq_InterruptClear0_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR0_cmdseqirq_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR0_cmdseqirq_InterruptClear0_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR0_cmdseqirq_InterruptClear0_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR1_cmdseqirq_InterruptClear1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR1_cmdseqirq_InterruptClear1_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR1_cmdseqirq_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR1_cmdseqirq_InterruptClear1_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR1_cmdseqirq_InterruptClear1_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTCLEAR2 - Interrupt Clear register 2 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR2_cmdseqirq_InterruptClear2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR2_cmdseqirq_InterruptClear2_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR2_cmdseqirq_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR2_cmdseqirq_InterruptClear2_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTCLEAR2_cmdseqirq_InterruptClear2_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS0_cmdseqirq_InterruptStatus0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS0_cmdseqirq_InterruptStatus0_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS0_cmdseqirq_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS0_cmdseqirq_InterruptStatus0_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS0_cmdseqirq_InterruptStatus0_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS1_cmdseqirq_InterruptStatus1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS1_cmdseqirq_InterruptStatus1_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS1_cmdseqirq_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS1_cmdseqirq_InterruptStatus1_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS1_cmdseqirq_InterruptStatus1_MASK) /*! @} */ /*! @name CMDSEQIRQ_INTERRUPTSTATUS2 - Interrupt Status register 2 */ /*! @{ */ #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS2_cmdseqirq_InterruptStatus2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS2_cmdseqirq_InterruptStatus2_SHIFT (0U) #define DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS2_cmdseqirq_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS2_cmdseqirq_InterruptStatus2_SHIFT)) & DISPLAY_SEERIS_CMDSEQIRQ_INTERRUPTSTATUS2_cmdseqirq_InterruptStatus2_MASK) /*! @} */ /*! @name GENERALPURPOSE_GENERALPURPOSE - General purpose config memory */ /*! @{ */ #define DISPLAY_SEERIS_GENERALPURPOSE_GENERALPURPOSE_generalpurpose_GeneralPurpose_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_GENERALPURPOSE_GENERALPURPOSE_generalpurpose_GeneralPurpose_SHIFT (0U) #define DISPLAY_SEERIS_GENERALPURPOSE_GENERALPURPOSE_generalpurpose_GeneralPurpose(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_GENERALPURPOSE_GENERALPURPOSE_generalpurpose_GeneralPurpose_SHIFT)) & DISPLAY_SEERIS_GENERALPURPOSE_GENERALPURPOSE_generalpurpose_GeneralPurpose_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_GENERALPURPOSE_GENERALPURPOSE */ #define DISPLAY_SEERIS_GENERALPURPOSE_GENERALPURPOSE_COUNT (32U) /*! @name XPC_CONTROL - Global XPC control register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_CONTROL_xpc_Enable_MASK (0x1U) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_Enable_SHIFT (0U) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_CONTROL_xpc_Enable_SHIFT)) & DISPLAY_SEERIS_XPC_CONTROL_xpc_Enable_MASK) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_Mode_MASK (0x6U) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_Mode_SHIFT (1U) /*! xpc_Mode * 0b00..Manual measurement end * 0b01..Timer controlled measurement end * 0b10..Continuous measurement; retriggered by reading SW_Tag register */ #define DISPLAY_SEERIS_XPC_CONTROL_xpc_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_CONTROL_xpc_Mode_SHIFT)) & DISPLAY_SEERIS_XPC_CONTROL_xpc_Mode_MASK) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_IncrementMode_MASK (0x40000000U) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_IncrementMode_SHIFT (30U) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_IncrementMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_CONTROL_xpc_IncrementMode_SHIFT)) & DISPLAY_SEERIS_XPC_CONTROL_xpc_IncrementMode_MASK) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_OTCDisable_MASK (0x80000000U) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_OTCDisable_SHIFT (31U) #define DISPLAY_SEERIS_XPC_CONTROL_xpc_OTCDisable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_CONTROL_xpc_OTCDisable_SHIFT)) & DISPLAY_SEERIS_XPC_CONTROL_xpc_OTCDisable_MASK) /*! @} */ /*! @name XPC_TIMER - Timer control register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_TIMER_xpc_Load_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_XPC_TIMER_xpc_Load_SHIFT (0U) #define DISPLAY_SEERIS_XPC_TIMER_xpc_Load(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_TIMER_xpc_Load_SHIFT)) & DISPLAY_SEERIS_XPC_TIMER_xpc_Load_MASK) #define DISPLAY_SEERIS_XPC_TIMER_xpc_Divider_MASK (0xF0000000U) #define DISPLAY_SEERIS_XPC_TIMER_xpc_Divider_SHIFT (28U) #define DISPLAY_SEERIS_XPC_TIMER_xpc_Divider(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_TIMER_xpc_Divider_SHIFT)) & DISPLAY_SEERIS_XPC_TIMER_xpc_Divider_MASK) /*! @} */ /*! @name XPC_MEASUREMENTTIMECONTROL - Timer divider control register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTDivider_MASK (0xFFFFFU) #define DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTDivider_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTDivider(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTDivider_SHIFT)) & DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTDivider_MASK) #define DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTEnable_MASK (0x80000000U) #define DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTEnable_SHIFT (31U) #define DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTEnable_SHIFT)) & DISPLAY_SEERIS_XPC_MEASUREMENTTIMECONTROL_xpc_MTEnable_MASK) /*! @} */ /*! @name XPC_SW_TAG - Tag register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_SW_TAG_xpc_Tag_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_SW_TAG_xpc_Tag_SHIFT (0U) #define DISPLAY_SEERIS_XPC_SW_TAG_xpc_Tag(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_SW_TAG_xpc_Tag_SHIFT)) & DISPLAY_SEERIS_XPC_SW_TAG_xpc_Tag_MASK) /*! @} */ /*! @name XPC_MEASUREMENTTIME - Measurement time register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MEASUREMENTTIME_xpc_Time_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MEASUREMENTTIME_xpc_Time_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MEASUREMENTTIME_xpc_Time(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MEASUREMENTTIME_xpc_Time_SHIFT)) & DISPLAY_SEERIS_XPC_MEASUREMENTTIME_xpc_Time_MASK) /*! @} */ /*! @name XPC_GLOBAL_COUNTER - Global counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_GLOBAL_COUNTER_xpc_Global_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_GLOBAL_COUNTER_xpc_Global_SHIFT (0U) #define DISPLAY_SEERIS_XPC_GLOBAL_COUNTER_xpc_Global(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_GLOBAL_COUNTER_xpc_Global_SHIFT)) & DISPLAY_SEERIS_XPC_GLOBAL_COUNTER_xpc_Global_MASK) /*! @} */ /*! @name XPC_MU00_SWITCH - Measurement unit 00 switch register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU00_SWITCH_xpc_MU00_Select_MASK (0xFU) #define DISPLAY_SEERIS_XPC_MU00_SWITCH_xpc_MU00_Select_SHIFT (0U) /*! xpc_MU00_Select * 0b0000..fetchlayer0 read direction (ACLK clock) * 0b0001..fetchlayer1 read direction (ACLK clock) * 0b0010..fetchyuv3 read direction (ACLK clock) * 0b0011..fetchyuv0 read direction (ACLK clock) * 0b0100..fetchyuv1 read direction (ACLK clock) * 0b0101..fetchyuv2 read direction (ACLK clock) * 0b0110..fetcheco0 read direction (ACLK clock) * 0b0111..fetcheco1 read direction (ACLK clock) * 0b1000..fetcheco2 read direction (ACLK clock) * 0b1001..fetchdecode9 read direction (ACLK clock) * 0b1010..fetchrot9 read direction (ACLK clock) * 0b1011..fetcheco9 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b1101..cmdseq read direction (ACLK clock) * 0b1110..cmdseq write direction (ACLK clock) */ #define DISPLAY_SEERIS_XPC_MU00_SWITCH_xpc_MU00_Select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU00_SWITCH_xpc_MU00_Select_SHIFT)) & DISPLAY_SEERIS_XPC_MU00_SWITCH_xpc_MU00_Select_MASK) /*! @} */ /*! @name XPC_MU00_DATA_COUNTER - Measurement unit 00 data counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU00_DATA_COUNTER_xpc_MU00_Data_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU00_DATA_COUNTER_xpc_MU00_Data_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU00_DATA_COUNTER_xpc_MU00_Data(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU00_DATA_COUNTER_xpc_MU00_Data_SHIFT)) & DISPLAY_SEERIS_XPC_MU00_DATA_COUNTER_xpc_MU00_Data_MASK) /*! @} */ /*! @name XPC_MU00_BUSY_COUNTER - Measurement unit 00 busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU00_BUSY_COUNTER_xpc_MU00_Busy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU00_BUSY_COUNTER_xpc_MU00_Busy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU00_BUSY_COUNTER_xpc_MU00_Busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU00_BUSY_COUNTER_xpc_MU00_Busy_SHIFT)) & DISPLAY_SEERIS_XPC_MU00_BUSY_COUNTER_xpc_MU00_Busy_MASK) /*! @} */ /*! @name XPC_MU00_TRANSFER_COUNTER - Measurement unit 00 transfer counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU00_TRANSFER_COUNTER_xpc_MU00_Transfer_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU00_TRANSFER_COUNTER_xpc_MU00_Transfer_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU00_TRANSFER_COUNTER_xpc_MU00_Transfer(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU00_TRANSFER_COUNTER_xpc_MU00_Transfer_SHIFT)) & DISPLAY_SEERIS_XPC_MU00_TRANSFER_COUNTER_xpc_MU00_Transfer_MASK) /*! @} */ /*! @name XPC_MU00_ADDRBUSY_COUNTER - Measurement unit 00 address busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU00_ADDRBUSY_COUNTER_xpc_MU00_Addrbusy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU00_ADDRBUSY_COUNTER_xpc_MU00_Addrbusy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU00_ADDRBUSY_COUNTER_xpc_MU00_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU00_ADDRBUSY_COUNTER_xpc_MU00_Addrbusy_SHIFT)) & DISPLAY_SEERIS_XPC_MU00_ADDRBUSY_COUNTER_xpc_MU00_Addrbusy_MASK) /*! @} */ /*! @name XPC_MU00_LATENCY_COUNTER - Measurement unit 00 latency counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU00_LATENCY_COUNTER_xpc_MU00_Latency_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU00_LATENCY_COUNTER_xpc_MU00_Latency_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU00_LATENCY_COUNTER_xpc_MU00_Latency(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU00_LATENCY_COUNTER_xpc_MU00_Latency_SHIFT)) & DISPLAY_SEERIS_XPC_MU00_LATENCY_COUNTER_xpc_MU00_Latency_MASK) /*! @} */ /*! @name XPC_MU01_SWITCH - Measurement unit 01 switch register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU01_SWITCH_xpc_MU01_Select_MASK (0xFU) #define DISPLAY_SEERIS_XPC_MU01_SWITCH_xpc_MU01_Select_SHIFT (0U) /*! xpc_MU01_Select * 0b0000..fetchlayer0 read direction (ACLK clock) * 0b0001..fetchlayer1 read direction (ACLK clock) * 0b0010..fetchyuv3 read direction (ACLK clock) * 0b0011..fetchyuv0 read direction (ACLK clock) * 0b0100..fetchyuv1 read direction (ACLK clock) * 0b0101..fetchyuv2 read direction (ACLK clock) * 0b0110..fetcheco0 read direction (ACLK clock) * 0b0111..fetcheco1 read direction (ACLK clock) * 0b1000..fetcheco2 read direction (ACLK clock) * 0b1001..fetchdecode9 read direction (ACLK clock) * 0b1010..fetchrot9 read direction (ACLK clock) * 0b1011..fetcheco9 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b1101..cmdseq read direction (ACLK clock) * 0b1110..cmdseq write direction (ACLK clock) */ #define DISPLAY_SEERIS_XPC_MU01_SWITCH_xpc_MU01_Select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU01_SWITCH_xpc_MU01_Select_SHIFT)) & DISPLAY_SEERIS_XPC_MU01_SWITCH_xpc_MU01_Select_MASK) /*! @} */ /*! @name XPC_MU01_DATA_COUNTER - Measurement unit 01 data counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU01_DATA_COUNTER_xpc_MU01_Data_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU01_DATA_COUNTER_xpc_MU01_Data_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU01_DATA_COUNTER_xpc_MU01_Data(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU01_DATA_COUNTER_xpc_MU01_Data_SHIFT)) & DISPLAY_SEERIS_XPC_MU01_DATA_COUNTER_xpc_MU01_Data_MASK) /*! @} */ /*! @name XPC_MU01_BUSY_COUNTER - Measurement unit 01 busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU01_BUSY_COUNTER_xpc_MU01_Busy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU01_BUSY_COUNTER_xpc_MU01_Busy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU01_BUSY_COUNTER_xpc_MU01_Busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU01_BUSY_COUNTER_xpc_MU01_Busy_SHIFT)) & DISPLAY_SEERIS_XPC_MU01_BUSY_COUNTER_xpc_MU01_Busy_MASK) /*! @} */ /*! @name XPC_MU01_TRANSFER_COUNTER - Measurement unit 01 transfer counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU01_TRANSFER_COUNTER_xpc_MU01_Transfer_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU01_TRANSFER_COUNTER_xpc_MU01_Transfer_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU01_TRANSFER_COUNTER_xpc_MU01_Transfer(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU01_TRANSFER_COUNTER_xpc_MU01_Transfer_SHIFT)) & DISPLAY_SEERIS_XPC_MU01_TRANSFER_COUNTER_xpc_MU01_Transfer_MASK) /*! @} */ /*! @name XPC_MU01_ADDRBUSY_COUNTER - Measurement unit 01 address busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU01_ADDRBUSY_COUNTER_xpc_MU01_Addrbusy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU01_ADDRBUSY_COUNTER_xpc_MU01_Addrbusy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU01_ADDRBUSY_COUNTER_xpc_MU01_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU01_ADDRBUSY_COUNTER_xpc_MU01_Addrbusy_SHIFT)) & DISPLAY_SEERIS_XPC_MU01_ADDRBUSY_COUNTER_xpc_MU01_Addrbusy_MASK) /*! @} */ /*! @name XPC_MU01_LATENCY_COUNTER - Measurement unit 01 latency counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU01_LATENCY_COUNTER_xpc_MU01_Latency_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU01_LATENCY_COUNTER_xpc_MU01_Latency_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU01_LATENCY_COUNTER_xpc_MU01_Latency(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU01_LATENCY_COUNTER_xpc_MU01_Latency_SHIFT)) & DISPLAY_SEERIS_XPC_MU01_LATENCY_COUNTER_xpc_MU01_Latency_MASK) /*! @} */ /*! @name XPC_MU02_SWITCH - Measurement unit 02 switch register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU02_SWITCH_xpc_MU02_Select_MASK (0xFU) #define DISPLAY_SEERIS_XPC_MU02_SWITCH_xpc_MU02_Select_SHIFT (0U) /*! xpc_MU02_Select * 0b0000..fetchlayer0 read direction (ACLK clock) * 0b0001..fetchlayer1 read direction (ACLK clock) * 0b0010..fetchyuv3 read direction (ACLK clock) * 0b0011..fetchyuv0 read direction (ACLK clock) * 0b0100..fetchyuv1 read direction (ACLK clock) * 0b0101..fetchyuv2 read direction (ACLK clock) * 0b0110..fetcheco0 read direction (ACLK clock) * 0b0111..fetcheco1 read direction (ACLK clock) * 0b1000..fetcheco2 read direction (ACLK clock) * 0b1001..fetchdecode9 read direction (ACLK clock) * 0b1010..fetchrot9 read direction (ACLK clock) * 0b1011..fetcheco9 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b1101..cmdseq read direction (ACLK clock) * 0b1110..cmdseq write direction (ACLK clock) */ #define DISPLAY_SEERIS_XPC_MU02_SWITCH_xpc_MU02_Select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU02_SWITCH_xpc_MU02_Select_SHIFT)) & DISPLAY_SEERIS_XPC_MU02_SWITCH_xpc_MU02_Select_MASK) /*! @} */ /*! @name XPC_MU02_DATA_COUNTER - Measurement unit 02 data counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU02_DATA_COUNTER_xpc_MU02_Data_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU02_DATA_COUNTER_xpc_MU02_Data_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU02_DATA_COUNTER_xpc_MU02_Data(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU02_DATA_COUNTER_xpc_MU02_Data_SHIFT)) & DISPLAY_SEERIS_XPC_MU02_DATA_COUNTER_xpc_MU02_Data_MASK) /*! @} */ /*! @name XPC_MU02_BUSY_COUNTER - Measurement unit 02 busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU02_BUSY_COUNTER_xpc_MU02_Busy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU02_BUSY_COUNTER_xpc_MU02_Busy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU02_BUSY_COUNTER_xpc_MU02_Busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU02_BUSY_COUNTER_xpc_MU02_Busy_SHIFT)) & DISPLAY_SEERIS_XPC_MU02_BUSY_COUNTER_xpc_MU02_Busy_MASK) /*! @} */ /*! @name XPC_MU02_TRANSFER_COUNTER - Measurement unit 02 transfer counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU02_TRANSFER_COUNTER_xpc_MU02_Transfer_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU02_TRANSFER_COUNTER_xpc_MU02_Transfer_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU02_TRANSFER_COUNTER_xpc_MU02_Transfer(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU02_TRANSFER_COUNTER_xpc_MU02_Transfer_SHIFT)) & DISPLAY_SEERIS_XPC_MU02_TRANSFER_COUNTER_xpc_MU02_Transfer_MASK) /*! @} */ /*! @name XPC_MU02_ADDRBUSY_COUNTER - Measurement unit 02 address busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU02_ADDRBUSY_COUNTER_xpc_MU02_Addrbusy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU02_ADDRBUSY_COUNTER_xpc_MU02_Addrbusy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU02_ADDRBUSY_COUNTER_xpc_MU02_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU02_ADDRBUSY_COUNTER_xpc_MU02_Addrbusy_SHIFT)) & DISPLAY_SEERIS_XPC_MU02_ADDRBUSY_COUNTER_xpc_MU02_Addrbusy_MASK) /*! @} */ /*! @name XPC_MU02_LATENCY_COUNTER - Measurement unit 02 latency counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU02_LATENCY_COUNTER_xpc_MU02_Latency_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU02_LATENCY_COUNTER_xpc_MU02_Latency_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU02_LATENCY_COUNTER_xpc_MU02_Latency(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU02_LATENCY_COUNTER_xpc_MU02_Latency_SHIFT)) & DISPLAY_SEERIS_XPC_MU02_LATENCY_COUNTER_xpc_MU02_Latency_MASK) /*! @} */ /*! @name XPC_MU03_SWITCH - Measurement unit 03 switch register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU03_SWITCH_xpc_MU03_Select_MASK (0xFU) #define DISPLAY_SEERIS_XPC_MU03_SWITCH_xpc_MU03_Select_SHIFT (0U) /*! xpc_MU03_Select * 0b0000..fetchlayer0 read direction (ACLK clock) * 0b0001..fetchlayer1 read direction (ACLK clock) * 0b0010..fetchyuv3 read direction (ACLK clock) * 0b0011..fetchyuv0 read direction (ACLK clock) * 0b0100..fetchyuv1 read direction (ACLK clock) * 0b0101..fetchyuv2 read direction (ACLK clock) * 0b0110..fetcheco0 read direction (ACLK clock) * 0b0111..fetcheco1 read direction (ACLK clock) * 0b1000..fetcheco2 read direction (ACLK clock) * 0b1001..fetchdecode9 read direction (ACLK clock) * 0b1010..fetchrot9 read direction (ACLK clock) * 0b1011..fetcheco9 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b1101..cmdseq read direction (ACLK clock) * 0b1110..cmdseq write direction (ACLK clock) */ #define DISPLAY_SEERIS_XPC_MU03_SWITCH_xpc_MU03_Select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU03_SWITCH_xpc_MU03_Select_SHIFT)) & DISPLAY_SEERIS_XPC_MU03_SWITCH_xpc_MU03_Select_MASK) /*! @} */ /*! @name XPC_MU03_DATA_COUNTER - Measurement unit 03 data counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU03_DATA_COUNTER_xpc_MU03_Data_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU03_DATA_COUNTER_xpc_MU03_Data_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU03_DATA_COUNTER_xpc_MU03_Data(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU03_DATA_COUNTER_xpc_MU03_Data_SHIFT)) & DISPLAY_SEERIS_XPC_MU03_DATA_COUNTER_xpc_MU03_Data_MASK) /*! @} */ /*! @name XPC_MU03_BUSY_COUNTER - Measurement unit 03 busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU03_BUSY_COUNTER_xpc_MU03_Busy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU03_BUSY_COUNTER_xpc_MU03_Busy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU03_BUSY_COUNTER_xpc_MU03_Busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU03_BUSY_COUNTER_xpc_MU03_Busy_SHIFT)) & DISPLAY_SEERIS_XPC_MU03_BUSY_COUNTER_xpc_MU03_Busy_MASK) /*! @} */ /*! @name XPC_MU03_TRANSFER_COUNTER - Measurement unit 03 transfer counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU03_TRANSFER_COUNTER_xpc_MU03_Transfer_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU03_TRANSFER_COUNTER_xpc_MU03_Transfer_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU03_TRANSFER_COUNTER_xpc_MU03_Transfer(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU03_TRANSFER_COUNTER_xpc_MU03_Transfer_SHIFT)) & DISPLAY_SEERIS_XPC_MU03_TRANSFER_COUNTER_xpc_MU03_Transfer_MASK) /*! @} */ /*! @name XPC_MU03_ADDRBUSY_COUNTER - Measurement unit 03 address busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU03_ADDRBUSY_COUNTER_xpc_MU03_Addrbusy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU03_ADDRBUSY_COUNTER_xpc_MU03_Addrbusy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU03_ADDRBUSY_COUNTER_xpc_MU03_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU03_ADDRBUSY_COUNTER_xpc_MU03_Addrbusy_SHIFT)) & DISPLAY_SEERIS_XPC_MU03_ADDRBUSY_COUNTER_xpc_MU03_Addrbusy_MASK) /*! @} */ /*! @name XPC_MU03_LATENCY_COUNTER - Measurement unit 03 latency counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU03_LATENCY_COUNTER_xpc_MU03_Latency_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU03_LATENCY_COUNTER_xpc_MU03_Latency_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU03_LATENCY_COUNTER_xpc_MU03_Latency(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU03_LATENCY_COUNTER_xpc_MU03_Latency_SHIFT)) & DISPLAY_SEERIS_XPC_MU03_LATENCY_COUNTER_xpc_MU03_Latency_MASK) /*! @} */ /*! @name XPC_MU04_SWITCH - Measurement unit 04 switch register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU04_SWITCH_xpc_MU04_Select_MASK (0xFU) #define DISPLAY_SEERIS_XPC_MU04_SWITCH_xpc_MU04_Select_SHIFT (0U) /*! xpc_MU04_Select * 0b0000..fetchlayer0 read direction (ACLK clock) * 0b0001..fetchlayer1 read direction (ACLK clock) * 0b0010..fetchyuv3 read direction (ACLK clock) * 0b0011..fetchyuv0 read direction (ACLK clock) * 0b0100..fetchyuv1 read direction (ACLK clock) * 0b0101..fetchyuv2 read direction (ACLK clock) * 0b0110..fetcheco0 read direction (ACLK clock) * 0b0111..fetcheco1 read direction (ACLK clock) * 0b1000..fetcheco2 read direction (ACLK clock) * 0b1001..fetchdecode9 read direction (ACLK clock) * 0b1010..fetchrot9 read direction (ACLK clock) * 0b1011..fetcheco9 read direction (ACLK clock) * 0b1100..store9 write direction (ACLK clock) * 0b1101..cmdseq read direction (ACLK clock) * 0b1110..cmdseq write direction (ACLK clock) */ #define DISPLAY_SEERIS_XPC_MU04_SWITCH_xpc_MU04_Select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU04_SWITCH_xpc_MU04_Select_SHIFT)) & DISPLAY_SEERIS_XPC_MU04_SWITCH_xpc_MU04_Select_MASK) /*! @} */ /*! @name XPC_MU04_DATA_COUNTER - Measurement unit 04 data counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU04_DATA_COUNTER_xpc_MU04_Data_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU04_DATA_COUNTER_xpc_MU04_Data_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU04_DATA_COUNTER_xpc_MU04_Data(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU04_DATA_COUNTER_xpc_MU04_Data_SHIFT)) & DISPLAY_SEERIS_XPC_MU04_DATA_COUNTER_xpc_MU04_Data_MASK) /*! @} */ /*! @name XPC_MU04_BUSY_COUNTER - Measurement unit 04 busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU04_BUSY_COUNTER_xpc_MU04_Busy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU04_BUSY_COUNTER_xpc_MU04_Busy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU04_BUSY_COUNTER_xpc_MU04_Busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU04_BUSY_COUNTER_xpc_MU04_Busy_SHIFT)) & DISPLAY_SEERIS_XPC_MU04_BUSY_COUNTER_xpc_MU04_Busy_MASK) /*! @} */ /*! @name XPC_MU04_TRANSFER_COUNTER - Measurement unit 04 transfer counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU04_TRANSFER_COUNTER_xpc_MU04_Transfer_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU04_TRANSFER_COUNTER_xpc_MU04_Transfer_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU04_TRANSFER_COUNTER_xpc_MU04_Transfer(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU04_TRANSFER_COUNTER_xpc_MU04_Transfer_SHIFT)) & DISPLAY_SEERIS_XPC_MU04_TRANSFER_COUNTER_xpc_MU04_Transfer_MASK) /*! @} */ /*! @name XPC_MU04_ADDRBUSY_COUNTER - Measurement unit 04 address busy counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU04_ADDRBUSY_COUNTER_xpc_MU04_Addrbusy_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU04_ADDRBUSY_COUNTER_xpc_MU04_Addrbusy_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU04_ADDRBUSY_COUNTER_xpc_MU04_Addrbusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU04_ADDRBUSY_COUNTER_xpc_MU04_Addrbusy_SHIFT)) & DISPLAY_SEERIS_XPC_MU04_ADDRBUSY_COUNTER_xpc_MU04_Addrbusy_MASK) /*! @} */ /*! @name XPC_MU04_LATENCY_COUNTER - Measurement unit 04 latency counter register */ /*! @{ */ #define DISPLAY_SEERIS_XPC_MU04_LATENCY_COUNTER_xpc_MU04_Latency_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_XPC_MU04_LATENCY_COUNTER_xpc_MU04_Latency_SHIFT (0U) #define DISPLAY_SEERIS_XPC_MU04_LATENCY_COUNTER_xpc_MU04_Latency(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_XPC_MU04_LATENCY_COUNTER_xpc_MU04_Latency_SHIFT)) & DISPLAY_SEERIS_XPC_MU04_LATENCY_COUNTER_xpc_MU04_Latency_MASK) /*! @} */ /*! @name BLITIRQ_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_LOCKUNLOCK_blitirq_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_LOCKUNLOCK_blitirq_LockUnlock_SHIFT (0U) /*! blitirq_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_BLITIRQ_LOCKUNLOCK_blitirq_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_LOCKUNLOCK_blitirq_LockUnlock_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_LOCKUNLOCK_blitirq_LockUnlock_MASK) /*! @} */ /*! @name BLITIRQ_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_LockStatus_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_LockStatus_MASK) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_LOCKSTATUS_blitirq_FreezeStatus_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTENABLE0 - Interrupt Enable register 0. */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE0_blitirq_InterruptEnable0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE0_blitirq_InterruptEnable0_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE0_blitirq_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE0_blitirq_InterruptEnable0_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE0_blitirq_InterruptEnable0_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTENABLE1 - Interrupt Enable register 1. */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE1_blitirq_InterruptEnable1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE1_blitirq_InterruptEnable1_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE1_blitirq_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE1_blitirq_InterruptEnable1_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE1_blitirq_InterruptEnable1_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTENABLE2 - Interrupt Enable register 2. */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE2_blitirq_InterruptEnable2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE2_blitirq_InterruptEnable2_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE2_blitirq_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE2_blitirq_InterruptEnable2_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTENABLE2_blitirq_InterruptEnable2_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET0_blitirq_InterruptPreset0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET0_blitirq_InterruptPreset0_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET0_blitirq_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET0_blitirq_InterruptPreset0_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET0_blitirq_InterruptPreset0_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET1_blitirq_InterruptPreset1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET1_blitirq_InterruptPreset1_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET1_blitirq_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET1_blitirq_InterruptPreset1_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET1_blitirq_InterruptPreset1_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTPRESET2 - Interrupt Preset register 2 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET2_blitirq_InterruptPreset2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET2_blitirq_InterruptPreset2_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET2_blitirq_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET2_blitirq_InterruptPreset2_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTPRESET2_blitirq_InterruptPreset2_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR0_blitirq_InterruptClear0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR0_blitirq_InterruptClear0_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR0_blitirq_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR0_blitirq_InterruptClear0_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR0_blitirq_InterruptClear0_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR1_blitirq_InterruptClear1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR1_blitirq_InterruptClear1_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR1_blitirq_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR1_blitirq_InterruptClear1_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR1_blitirq_InterruptClear1_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTCLEAR2 - Interrupt Clear register 2 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR2_blitirq_InterruptClear2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR2_blitirq_InterruptClear2_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR2_blitirq_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR2_blitirq_InterruptClear2_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTCLEAR2_blitirq_InterruptClear2_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS0_blitirq_InterruptStatus0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS0_blitirq_InterruptStatus0_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS0_blitirq_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS0_blitirq_InterruptStatus0_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS0_blitirq_InterruptStatus0_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS1_blitirq_InterruptStatus1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS1_blitirq_InterruptStatus1_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS1_blitirq_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS1_blitirq_InterruptStatus1_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS1_blitirq_InterruptStatus1_MASK) /*! @} */ /*! @name BLITIRQ_INTERRUPTSTATUS2 - Interrupt Status register 2 */ /*! @{ */ #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS2_blitirq_InterruptStatus2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS2_blitirq_InterruptStatus2_SHIFT (0U) #define DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS2_blitirq_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS2_blitirq_InterruptStatus2_SHIFT)) & DISPLAY_SEERIS_BLITIRQ_INTERRUPTSTATUS2_blitirq_InterruptStatus2_MASK) /*! @} */ /*! @name PIXENG_ROP9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKUNLOCK_pixeng_rop9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKUNLOCK_pixeng_rop9_LockUnlock_SHIFT (0U) /*! pixeng_rop9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKUNLOCK_pixeng_rop9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_LOCKUNLOCK_pixeng_rop9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_LOCKUNLOCK_pixeng_rop9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_ROP9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_LOCKSTATUS_pixeng_rop9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_ROP9_STATICCONTROL - Raster Operation static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_STATICCONTROL_pixeng_rop9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_ROP9_STATICCONTROL_pixeng_rop9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_ROP9_STATICCONTROL_pixeng_rop9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_STATICCONTROL_pixeng_rop9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_STATICCONTROL_pixeng_rop9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_ROP9_CONTROL - Raster Operation control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_Mode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_Mode_SHIFT (0U) /*! pixeng_rop9_Mode * 0b0..Neutral mode * 0b1..Normal Operation */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_Mode_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_AlphaMode_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_AlphaMode_SHIFT (4U) /*! pixeng_rop9_AlphaMode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_AlphaMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_AlphaMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_AlphaMode_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_BlueMode_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_BlueMode_SHIFT (5U) /*! pixeng_rop9_BlueMode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_BlueMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_BlueMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_BlueMode_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_GreenMode_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_GreenMode_SHIFT (6U) /*! pixeng_rop9_GreenMode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_GreenMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_GreenMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_GreenMode_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_RedMode_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_RedMode_SHIFT (7U) /*! pixeng_rop9_RedMode * 0b0..Normal raster operation mode, using the operation index * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1 */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_RedMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_RedMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_RedMode_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_PrimDiv2_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_PrimDiv2_SHIFT (8U) /*! pixeng_rop9_PrimDiv2 * 0b0..No change to input * 0b1..Input is divided by two/shift to the right by one */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_PrimDiv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_PrimDiv2_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_PrimDiv2_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_SecDiv2_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_SecDiv2_SHIFT (9U) /*! pixeng_rop9_SecDiv2 * 0b0..No change to input * 0b1..Input is divided by two/shift to the right by one */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_SecDiv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_SecDiv2_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_SecDiv2_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_TertDiv2_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_TertDiv2_SHIFT (10U) /*! pixeng_rop9_TertDiv2 * 0b0..No change to input * 0b1..Input is divided by two/shift to the right by one */ #define DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_TertDiv2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_TertDiv2_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_CONTROL_pixeng_rop9_TertDiv2_MASK) /*! @} */ /*! @name PIXENG_ROP9_RASTEROPERATIONINDICES - ROP operation indices */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexBlue_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexGreen_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_RASTEROPERATIONINDICES_pixeng_rop9_OpIndexRed_MASK) /*! @} */ /*! @name PIXENG_ROP9_PRIMCONTROLWORD - Value of last received primary control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_PRIMCONTROLWORD_pixeng_rop9_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_ROP9_PRIMCONTROLWORD_pixeng_rop9_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_ROP9_PRIMCONTROLWORD_pixeng_rop9_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_PRIMCONTROLWORD_pixeng_rop9_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_PRIMCONTROLWORD_pixeng_rop9_P_VAL_MASK) /*! @} */ /*! @name PIXENG_ROP9_SECCONTROLWORD - Value of last received secondary control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_SECCONTROLWORD_pixeng_rop9_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_ROP9_SECCONTROLWORD_pixeng_rop9_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_ROP9_SECCONTROLWORD_pixeng_rop9_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_SECCONTROLWORD_pixeng_rop9_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_SECCONTROLWORD_pixeng_rop9_S_VAL_MASK) /*! @} */ /*! @name PIXENG_ROP9_TERTCONTROLWORD - Value of last received tertiary control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9_TERTCONTROLWORD_pixeng_rop9_T_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_ROP9_TERTCONTROLWORD_pixeng_rop9_T_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_ROP9_TERTCONTROLWORD_pixeng_rop9_T_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9_TERTCONTROLWORD_pixeng_rop9_T_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9_TERTCONTROLWORD_pixeng_rop9_T_VAL_MASK) /*! @} */ /*! @name PIXENG_ROP9CFG_ROP9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKUNLOCK_pixeng_rop9cfg_rop9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKUNLOCK_pixeng_rop9cfg_rop9_LockUnlock_SHIFT (0U) /*! pixeng_rop9cfg_rop9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKUNLOCK_pixeng_rop9cfg_rop9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKUNLOCK_pixeng_rop9cfg_rop9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKUNLOCK_pixeng_rop9cfg_rop9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_ROP9CFG_ROP9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_LOCKSTATUS_pixeng_rop9cfg_rop9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_ROP9CFG_ROP9_DYNAMIC - Dynamic pixel engine configuration for rop9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_prim_sel_SHIFT (0U) /*! pixeng_rop9cfg_rop9_prim_sel * 0b000000..Unit rop9 input port prim is disabled * 0b000101..Unit rop9 input port prim is connected to output of unit fetchrot9 * 0b000110..Unit rop9 input port prim is connected to output of unit fetchdecode9 */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_sec_sel_SHIFT (8U) /*! pixeng_rop9cfg_rop9_sec_sel * 0b000000..Unit rop9 input port sec is disabled * 0b000111..Unit rop9 input port sec is connected to output of unit fetcheco9 */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_tert_sel_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_tert_sel_SHIFT (16U) /*! pixeng_rop9cfg_rop9_tert_sel * 0b000000..Unit rop9 input port tert is disabled * 0b000101..Unit rop9 input port tert is connected to output of unit fetchrot9 * 0b000110..Unit rop9 input port tert is connected to output of unit fetchdecode9 */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_tert_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_tert_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_tert_sel_MASK) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_clken_SHIFT (24U) /*! pixeng_rop9cfg_rop9_clken * 0b00..Clock for rop9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for rop9 is without gating */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_DYNAMIC_pixeng_rop9cfg_rop9_clken_MASK) /*! @} */ /*! @name PIXENG_ROP9CFG_ROP9_STATUS - Status information for pixel engine configuration of rop9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_STATUS_pixeng_rop9cfg_rop9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_STATUS_pixeng_rop9cfg_rop9_sel_SHIFT (16U) /*! pixeng_rop9cfg_rop9_sel * 0b000..rop9 module is not used * 0b001..rop9 module is used from store9 processing path * 0b010..rop9 module is used from extdst0 processing path * 0b011..rop9 module is used from extdst4 processing path * 0b100..rop9 module is used from extdst1 processing path * 0b101..rop9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_STATUS_pixeng_rop9cfg_rop9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_STATUS_pixeng_rop9cfg_rop9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_ROP9CFG_ROP9_STATUS_pixeng_rop9cfg_rop9_sel_MASK) /*! @} */ /*! @name PIXENG_CLUT9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKUNLOCK_pixeng_clut9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKUNLOCK_pixeng_clut9_LockUnlock_SHIFT (0U) /*! pixeng_clut9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKUNLOCK_pixeng_clut9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LOCKUNLOCK_pixeng_clut9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LOCKUNLOCK_pixeng_clut9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CLUT9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LOCKSTATUS_pixeng_clut9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CLUT9_STATICCONTROL - CLUT static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_STATICCONTROL_pixeng_clut9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CLUT9_STATICCONTROL_pixeng_clut9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CLUT9_STATICCONTROL_pixeng_clut9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_STATICCONTROL_pixeng_clut9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_STATICCONTROL_pixeng_clut9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_CLUT9_UNSHADOWEDCONTROL - CLUT unshadowed control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_B_EN_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_B_EN_SHIFT (0U) /*! pixeng_clut9_B_EN * 0b0..disable * 0b1..enable */ #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_B_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_B_EN_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_B_EN_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_G_EN_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_G_EN_SHIFT (1U) /*! pixeng_clut9_G_EN * 0b0..disable * 0b1..enable */ #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_G_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_G_EN_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_G_EN_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_R_EN_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_R_EN_SHIFT (2U) /*! pixeng_clut9_R_EN * 0b0..disable * 0b1..enable */ #define DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_R_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_R_EN_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_UNSHADOWEDCONTROL_pixeng_clut9_R_EN_MASK) /*! @} */ /*! @name PIXENG_CLUT9_CONTROL - CLUT control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_MODE_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_MODE_SHIFT (0U) /*! pixeng_clut9_MODE * 0b00..Module in neutral mode, RGBA input data are bypassed to the output. * 0b01..Each RGB input is used as individual index into the respective LUT. Alpha channel is bypassed to output. * 0b10..Red input is used as common index into every RGB LUT. Alpha channel is bypassed to output. * 0b11..Red input is used as common index into every RGB LUT. The result is remapped and upconverted to RGBA. */ #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_COL_8BIT_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_COL_8BIT_SHIFT (4U) /*! pixeng_clut9_COL_8BIT * 0b0..color is 10bit output * 0b1..color is 8bit output (dithering of internal 10bit value) */ #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_COL_8BIT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_COL_8BIT_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_COL_8BIT_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaMask_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaMask_SHIFT (5U) /*! pixeng_clut9_AlphaMask * 0b0..Alpha mask mode disabled * 0b1..Alpha mask mode enabled */ #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaMask_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaMask_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaInvert_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaInvert_SHIFT (6U) /*! pixeng_clut9_AlphaInvert * 0b0..Disable computation for alpha smaller than 128 * 0b1..Disable computation for alpha greater than or equal to 128 */ #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaInvert_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_AlphaInvert_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_IDX_BITS_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_IDX_BITS_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_IDX_BITS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_IDX_BITS_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_CONTROL_pixeng_clut9_IDX_BITS_MASK) /*! @} */ /*! @name PIXENG_CLUT9_STATUS - CLUT status register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_WRITE_TIMEOUT_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_WRITE_TIMEOUT_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_WRITE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_WRITE_TIMEOUT_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_WRITE_TIMEOUT_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_READ_TIMEOUT_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_READ_TIMEOUT_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_READ_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_READ_TIMEOUT_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_STATUS_pixeng_clut9_READ_TIMEOUT_MASK) /*! @} */ /*! @name PIXENG_CLUT9_LASTCONTROLWORD - Value of last received control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_LASTCONTROLWORD_pixeng_clut9_L_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CLUT9_LASTCONTROLWORD_pixeng_clut9_L_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LASTCONTROLWORD_pixeng_clut9_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LASTCONTROLWORD_pixeng_clut9_L_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LASTCONTROLWORD_pixeng_clut9_L_VAL_MASK) /*! @} */ /*! @name PIXENG_CLUT9_LUT - Look Up Table */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_BLUE_MASK (0x3FFU) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_BLUE_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_BLUE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_BLUE_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_BLUE_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_GREEN_MASK (0xFFC00U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_GREEN_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_GREEN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_GREEN_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_GREEN_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_RED_MASK (0x3FF00000U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_RED_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_RED(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_RED_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9_LUT_pixeng_clut9_RED_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_CLUT9_LUT */ #define DISPLAY_SEERIS_PIXENG_CLUT9_LUT_COUNT (256U) /*! @name PIXENG_CLUT9CFG_CLUT9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKUNLOCK_pixeng_clut9cfg_clut9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKUNLOCK_pixeng_clut9cfg_clut9_LockUnlock_SHIFT (0U) /*! pixeng_clut9cfg_clut9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKUNLOCK_pixeng_clut9cfg_clut9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKUNLOCK_pixeng_clut9cfg_clut9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKUNLOCK_pixeng_clut9cfg_clut9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_LOCKSTATUS_pixeng_clut9cfg_clut9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CLUT9CFG_CLUT9_DYNAMIC - Dynamic pixel engine configuration for clut9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_DYNAMIC_pixeng_clut9cfg_clut9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_DYNAMIC_pixeng_clut9cfg_clut9_src_sel_SHIFT (0U) /*! pixeng_clut9cfg_clut9_src_sel * 0b000000..Unit clut9 input port src is disabled * 0b000001..Unit clut9 input port src is connected to output of unit rop9 * 0b000100..Unit clut9 input port src is connected to output of unit blitblend9 */ #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_DYNAMIC_pixeng_clut9cfg_clut9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_DYNAMIC_pixeng_clut9cfg_clut9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_DYNAMIC_pixeng_clut9cfg_clut9_src_sel_MASK) /*! @} */ /*! @name PIXENG_CLUT9CFG_CLUT9_STATUS - Status information for pixel engine configuration of clut9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_STATUS_pixeng_clut9cfg_clut9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_STATUS_pixeng_clut9cfg_clut9_sel_SHIFT (16U) /*! pixeng_clut9cfg_clut9_sel * 0b000..clut9 module is not used * 0b001..clut9 module is used from store9 processing path * 0b010..clut9 module is used from extdst0 processing path * 0b011..clut9 module is used from extdst4 processing path * 0b100..clut9 module is used from extdst1 processing path * 0b101..clut9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_STATUS_pixeng_clut9cfg_clut9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_STATUS_pixeng_clut9cfg_clut9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_CLUT9CFG_CLUT9_STATUS_pixeng_clut9cfg_clut9_sel_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKUNLOCK_pixeng_matrix9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKUNLOCK_pixeng_matrix9_LockUnlock_SHIFT (0U) /*! pixeng_matrix9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKUNLOCK_pixeng_matrix9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKUNLOCK_pixeng_matrix9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKUNLOCK_pixeng_matrix9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_LOCKSTATUS_pixeng_matrix9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_STATICCONTROL_pixeng_matrix9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_STATICCONTROL_pixeng_matrix9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_STATICCONTROL_pixeng_matrix9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_STATICCONTROL_pixeng_matrix9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_STATICCONTROL_pixeng_matrix9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_CONTROL - Color Matrix control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_MODE_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_MODE_SHIFT (0U) /*! pixeng_matrix9_MODE * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaMask_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaMask_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaMask_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaMask_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaInvert_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaInvert_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaInvert_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_CONTROL_pixeng_matrix9_AlphaInvert_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A11_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A11_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A11(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A11_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A11_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A12_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A12_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A12(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A12_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_RED0_pixeng_matrix9_A12_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A13_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A13_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A13(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A13_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A13_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A14_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A14_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A14(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A14_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_RED1_pixeng_matrix9_A14_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A21_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A21_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A21(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A21_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A21_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A22_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A22_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A22(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A22_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN0_pixeng_matrix9_A22_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A23_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A23_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A23(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A23_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A23_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A24_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A24_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A24(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A24_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_GREEN1_pixeng_matrix9_A24_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A31_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A31_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A31(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A31_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A31_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A32_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A32_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A32(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A32_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE0_pixeng_matrix9_A32_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A33_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A33_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A33(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A33_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A33_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A34_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A34_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A34(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A34_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_BLUE1_pixeng_matrix9_A34_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_ALPHA0 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A41_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A41_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A41(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A41_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A41_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A42_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A42_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A42(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A42_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA0_pixeng_matrix9_A42_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_ALPHA1 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A43_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A43_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A43(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A43_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A43_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A44_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A44_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A44(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A44_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_ALPHA1_pixeng_matrix9_A44_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C1_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C1_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C1_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C2_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C2_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR0_pixeng_matrix9_C2_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C3_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C3_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C3_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C4_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C4_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_OFFSETVECTOR1_pixeng_matrix9_C4_MASK) /*! @} */ /*! @name PIXENG_MATRIX9_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9_LASTCONTROLWORD_pixeng_matrix9_L_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LASTCONTROLWORD_pixeng_matrix9_L_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9_LASTCONTROLWORD_pixeng_matrix9_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9_LASTCONTROLWORD_pixeng_matrix9_L_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9_LASTCONTROLWORD_pixeng_matrix9_L_VAL_MASK) /*! @} */ /*! @name PIXENG_MATRIX9CFG_MATRIX9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKUNLOCK_pixeng_matrix9cfg_matrix9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKUNLOCK_pixeng_matrix9cfg_matrix9_LockUnlock_SHIFT (0U) /*! pixeng_matrix9cfg_matrix9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKUNLOCK_pixeng_matrix9cfg_matrix9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKUNLOCK_pixeng_matrix9cfg_matrix9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKUNLOCK_pixeng_matrix9cfg_matrix9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_LOCKSTATUS_pixeng_matrix9cfg_matrix9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC - Dynamic pixel engine configuration for matrix9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_src_sel_SHIFT (0U) /*! pixeng_matrix9cfg_matrix9_src_sel * 0b000000..Unit matrix9 input port src is disabled * 0b000001..Unit matrix9 input port src is connected to output of unit rop9 * 0b000010..Unit matrix9 input port src is connected to output of unit clut9 * 0b000100..Unit matrix9 input port src is connected to output of unit blitblend9 */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_clken_SHIFT (24U) /*! pixeng_matrix9cfg_matrix9_clken * 0b00..Clock for matrix9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for matrix9 is without gating */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_DYNAMIC_pixeng_matrix9cfg_matrix9_clken_MASK) /*! @} */ /*! @name PIXENG_MATRIX9CFG_MATRIX9_STATUS - Status information for pixel engine configuration of matrix9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_STATUS_pixeng_matrix9cfg_matrix9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_STATUS_pixeng_matrix9cfg_matrix9_sel_SHIFT (16U) /*! pixeng_matrix9cfg_matrix9_sel * 0b000..matrix9 module is not used * 0b001..matrix9 module is used from store9 processing path * 0b010..matrix9 module is used from extdst0 processing path * 0b011..matrix9 module is used from extdst4 processing path * 0b100..matrix9 module is used from extdst1 processing path * 0b101..matrix9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_STATUS_pixeng_matrix9cfg_matrix9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_STATUS_pixeng_matrix9cfg_matrix9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX9CFG_MATRIX9_STATUS_pixeng_matrix9cfg_matrix9_sel_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9_LockUnlock_SHIFT (0U) /*! pixeng_blitblend9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_STATICCONTROL - BlitBlend static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_STATICCONTROL_pixeng_blitblend9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_STATICCONTROL_pixeng_blitblend9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_STATICCONTROL_pixeng_blitblend9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_STATICCONTROL_pixeng_blitblend9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_STATICCONTROL_pixeng_blitblend9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_CONTROL - BlitBlend control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONTROL_pixeng_blitblend9_Mode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONTROL_pixeng_blitblend9_Mode_SHIFT (0U) /*! pixeng_blitblend9_Mode * 0b0..Neutral mode, only route pixels and commands from primary input to output * 0b1..Normal Operation */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONTROL_pixeng_blitblend9_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONTROL_pixeng_blitblend9_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONTROL_pixeng_blitblend9_Mode_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_NEUTRALBORDER - Neutral border setup register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderMode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderMode_SHIFT (0U) /*! pixeng_blitblend9_NeutralBorderMode * 0b0..Bypasses primary pixel * 0b1..Bypasses secondary pixel */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderMode_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderLeft_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderLeft_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderLeft(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderLeft_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderLeft_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderRight_MASK (0x7000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderRight_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderRight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderRight_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_NEUTRALBORDER_pixeng_blitblend9_NeutralBorderRight_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_CONSTANTCOLOR - Constant color register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantBlue_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantGreen_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_CONSTANTCOLOR_pixeng_blitblend9_ConstantRed_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION - Open GL RGB blending factors */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedSrc_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedSrc_SHIFT (0U) /*! pixeng_blitblend9_BlendFuncColorRedSrc * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedSrc(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedSrc_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedSrc_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedDst_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedDst_SHIFT (16U) /*! pixeng_blitblend9_BlendFuncColorRedDst * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedDst(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedDst_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORREDBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorRedDst_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION - Open GL RGB blending factors */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenSrc_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenSrc_SHIFT (0U) /*! pixeng_blitblend9_BlendFuncColorGreenSrc * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenSrc(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenSrc_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenSrc_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenDst_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenDst_SHIFT (16U) /*! pixeng_blitblend9_BlendFuncColorGreenDst * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenDst(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenDst_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORGREENBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorGreenDst_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION - Open GL RGB blending factors */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueSrc_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueSrc_SHIFT (0U) /*! pixeng_blitblend9_BlendFuncColorBlueSrc * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueSrc(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueSrc_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueSrc_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueDst_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueDst_SHIFT (16U) /*! pixeng_blitblend9_BlendFuncColorBlueDst * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueDst(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueDst_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_COLORBLUEBLENDFUNCTION_pixeng_blitblend9_BlendFuncColorBlueDst_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_ALPHABLENDFUNCTION - Open GL alpha blending factors */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaSrc_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaSrc_SHIFT (0U) /*! pixeng_blitblend9_BlendFuncAlphaSrc * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaSrc(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaSrc_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaSrc_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaDst_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaDst_SHIFT (16U) /*! pixeng_blitblend9_BlendFuncAlphaDst * 0b0000000000000000.. * 0b0000000000000001.. * 0b0000001100000000.. * 0b0000001100000001.. * 0b0000001100000010.. * 0b0000001100000011.. * 0b0000001100000100.. * 0b0000001100000101.. * 0b0000001100000110.. * 0b0000001100000111.. * 0b0000001100001000.. * 0b1000000000000001.. * 0b1000000000000010.. * 0b1000000000000011.. * 0b1000000000000100.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaDst(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaDst_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_ALPHABLENDFUNCTION_pixeng_blitblend9_BlendFuncAlphaDst_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_BLENDMODE1 - Open GL and Open VG blending modes for colors red and green */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorRed_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorRed_SHIFT (0U) /*! pixeng_blitblend9_BlendModeColorRed * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorRed_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorGreen_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorGreen_SHIFT (16U) /*! pixeng_blitblend9_BlendModeColorGreen * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE1_pixeng_blitblend9_BlendModeColorGreen_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_BLENDMODE2 - Open GL and Open VG blending modes for color blue and alpha */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeColorBlue_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeColorBlue_SHIFT (0U) /*! pixeng_blitblend9_BlendModeColorBlue * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeColorBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeColorBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeColorBlue_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeAlpha_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeAlpha_SHIFT (16U) /*! pixeng_blitblend9_BlendModeAlpha * 0b0010000000000000.. * 0b0010000000000001.. * 0b0010000000000010.. * 0b0010000000000011.. * 0b0010000000000100.. * 0b0010000000000101.. * 0b0010000000000110.. * 0b0010000000000111.. * 0b0010000000001000.. * 0b0010000000001001.. * 0b1000000000000110.. * 0b1000000000000111.. * 0b1000000000001000.. * 0b1000000000001010.. * 0b1000000000001011.. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_BLENDMODE2_pixeng_blitblend9_BlendModeAlpha_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_DIRECTSETUP - Direct Control of the BlitBlend Datapath multiplexers, do not change */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_ColorDebug_MASK (0x3FFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_ColorDebug_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_ColorDebug(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_ColorDebug_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_ColorDebug_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_AlphaDebug_MASK (0x3FF0000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_AlphaDebug_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_AlphaDebug(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_AlphaDebug_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_DIRECTSETUP_pixeng_blitblend9_AlphaDebug_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_PRIMCONTROLWORD - Value of last received primary control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_PRIMCONTROLWORD_pixeng_blitblend9_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_PRIMCONTROLWORD_pixeng_blitblend9_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_PRIMCONTROLWORD_pixeng_blitblend9_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_PRIMCONTROLWORD_pixeng_blitblend9_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_PRIMCONTROLWORD_pixeng_blitblend9_P_VAL_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9_SECCONTROLWORD - Value of last received secondary control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_SECCONTROLWORD_pixeng_blitblend9_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_SECCONTROLWORD_pixeng_blitblend9_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9_SECCONTROLWORD_pixeng_blitblend9_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9_SECCONTROLWORD_pixeng_blitblend9_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9_SECCONTROLWORD_pixeng_blitblend9_S_VAL_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9cfg_blitblend9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9cfg_blitblend9_LockUnlock_SHIFT (0U) /*! pixeng_blitblend9cfg_blitblend9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9cfg_blitblend9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9cfg_blitblend9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKUNLOCK_pixeng_blitblend9cfg_blitblend9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_LOCKSTATUS_pixeng_blitblend9cfg_blitblend9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC - Dynamic pixel engine configuration for blitblend9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_prim_sel_SHIFT (0U) /*! pixeng_blitblend9cfg_blitblend9_prim_sel * 0b000000..Unit blitblend9 input port prim is disabled * 0b000001..Unit blitblend9 input port prim is connected to output of unit rop9 * 0b001000..Unit blitblend9 input port prim is connected to output of unit hscaler9 * 0b001001..Unit blitblend9 input port prim is connected to output of unit vscaler9 * 0b001010..Unit blitblend9 input port prim is connected to output of unit filter9 */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_sec_sel_SHIFT (8U) /*! pixeng_blitblend9cfg_blitblend9_sec_sel * 0b000000..Unit blitblend9 input port sec is disabled * 0b000101..Unit blitblend9 input port sec is connected to output of unit fetchrot9 * 0b000110..Unit blitblend9 input port sec is connected to output of unit fetchdecode9 */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_clken_SHIFT (24U) /*! pixeng_blitblend9cfg_blitblend9_clken * 0b00..Clock for blitblend9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for blitblend9 is without gating */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_DYNAMIC_pixeng_blitblend9cfg_blitblend9_clken_MASK) /*! @} */ /*! @name PIXENG_BLITBLEND9CFG_BLITBLEND9_STATUS - Status information for pixel engine configuration of blitblend9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_STATUS_pixeng_blitblend9cfg_blitblend9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_STATUS_pixeng_blitblend9cfg_blitblend9_sel_SHIFT (16U) /*! pixeng_blitblend9cfg_blitblend9_sel * 0b000..blitblend9 module is not used * 0b001..blitblend9 module is used from store9 processing path * 0b010..blitblend9 module is used from extdst0 processing path * 0b011..blitblend9 module is used from extdst4 processing path * 0b100..blitblend9 module is used from extdst1 processing path * 0b101..blitblend9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_STATUS_pixeng_blitblend9cfg_blitblend9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_STATUS_pixeng_blitblend9cfg_blitblend9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_BLITBLEND9CFG_BLITBLEND9_STATUS_pixeng_blitblend9cfg_blitblend9_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9_LockUnlock_SHIFT (0U) /*! pixeng_fetchrot9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_BaseAddressSelect_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_BaseAddressSelect_SHIFT (4U) /*! pixeng_fetchrot9_BaseAddressSelect * 0b0..Use Baseaddress mechanism form current fetch unit. * 0b1..Use Baseaddress from external source (depends on system, e.g. from store unit). */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_BaseAddressSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_BaseAddressSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_STATICCONTROL_pixeng_fetchrot9_BaseAddressSelect_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_CombinerLineFlush_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_LineMode_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_LineMode_SHIFT (31U) /*! pixeng_fetchrot9_LineMode * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact. * 0b1..Recommended setting for operation in the Blit Engine. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_LineMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_LineMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERMANAGEMENT_pixeng_fetchrot9_LineMode_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDR0_pixeng_fetchrot9_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDR0_pixeng_fetchrot9_RingBufStartAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDR0_pixeng_fetchrot9_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDR0_pixeng_fetchrot9_RingBufStartAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDR0_pixeng_fetchrot9_RingBufStartAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_RINGBUFSTARTADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDRMSB0_pixeng_fetchrot9_RingBufStartAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDRMSB0_pixeng_fetchrot9_RingBufStartAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDRMSB0_pixeng_fetchrot9_RingBufStartAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDRMSB0_pixeng_fetchrot9_RingBufStartAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFSTARTADDRMSB0_pixeng_fetchrot9_RingBufStartAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDR0_pixeng_fetchrot9_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDR0_pixeng_fetchrot9_RingBufWrapAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDR0_pixeng_fetchrot9_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDR0_pixeng_fetchrot9_RingBufWrapAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDR0_pixeng_fetchrot9_RingBufWrapAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_RINGBUFWRAPADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDRMSB0_pixeng_fetchrot9_RingBufWrapAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDRMSB0_pixeng_fetchrot9_RingBufWrapAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDRMSB0_pixeng_fetchrot9_RingBufWrapAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDRMSB0_pixeng_fetchrot9_RingBufWrapAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_RINGBUFWRAPADDRMSB0_pixeng_fetchrot9_RingBufWrapAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESS0_pixeng_fetchrot9_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESS0_pixeng_fetchrot9_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESS0_pixeng_fetchrot9_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESS0_pixeng_fetchrot9_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESS0_pixeng_fetchrot9_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESSMSB0_pixeng_fetchrot9_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESSMSB0_pixeng_fetchrot9_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESSMSB0_pixeng_fetchrot9_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESSMSB0_pixeng_fetchrot9_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BASEADDRESSMSB0_pixeng_fetchrot9_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESS0_pixeng_fetchrot9_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESS0_pixeng_fetchrot9_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESS0_pixeng_fetchrot9_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESS0_pixeng_fetchrot9_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESS0_pixeng_fetchrot9_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchrot9_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchrot9_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchrot9_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchrot9_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchrot9_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchrot9_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_SOURCEBUFFERDIMENSION0_pixeng_fetchrot9_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTBITS0_pixeng_fetchrot9_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_COLORCOMPONENTSHIFT0_pixeng_fetchrot9_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYEROFFSET0_pixeng_fetchrot9_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWOFFSET0_pixeng_fetchrot9_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CLIPWINDOWDIMENSIONS0_pixeng_fetchrot9_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONSTANTCOLOR0_pixeng_fetchrot9_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_TileMode0_SHIFT (4U) /*! pixeng_fetchrot9_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaMaskEnable0_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaMaskEnable0_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaMaskEnable0_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaMaskEnable0_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchrot9_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_LAYERPROPERTY0_pixeng_fetchrot9_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMEDIMENSIONS_pixeng_fetchrot9_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FRAMERESAMPLING_pixeng_fetchrot9_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_WARPCONTROL - Warping control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpBitsPerPixel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpBitsPerPixel_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpBitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpBitsPerPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpBitsPerPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpCoordinateMode_MASK (0x300U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpCoordinateMode_SHIFT (8U) /*! pixeng_fetchrot9_WarpCoordinateMode * 0b00..x and y (sample points). * 0b01..dx and dy (vectors between adjacent sample points). * 0b10..ddx and ddy (deltas between adjacent vectors). */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpCoordinateMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpCoordinateMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpCoordinateMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpSymmetricOffset_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpSymmetricOffset_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpSymmetricOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpSymmetricOffset_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WarpSymmetricOffset_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_XRaster_MASK (0x30000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_XRaster_SHIFT (16U) /*! pixeng_fetchrot9_WRPT_XRaster * 0b00..X-Raster is 16 pixel. * 0b01..X-Raster is 32 pixel. * 0b10..X-Raster is 64 pixel. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_XRaster(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_XRaster_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_XRaster_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_YRaster_MASK (0xC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_YRaster_SHIFT (18U) /*! pixeng_fetchrot9_WRPT_YRaster * 0b00..Y-Raster is 16 pixel. * 0b01..Y-Raster is 32 pixel. * 0b10..Y-Raster is 64 pixel. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_YRaster(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_YRaster_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_YRaster_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_Select_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_Select_SHIFT (20U) /*! pixeng_fetchrot9_WRPT_Select * 0b0..Use WarpReferencePointsTable 0. * 0b1..Use WarpReferencePointsTable 1. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_Select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_Select_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPCONTROL_pixeng_fetchrot9_WRPT_Select_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AFFINESTARTX - Start value X for affine warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTX_pixeng_fetchrot9_AffineStartX_MASK (0xFFFFF800U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTX_pixeng_fetchrot9_AffineStartX_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTX_pixeng_fetchrot9_AffineStartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTX_pixeng_fetchrot9_AffineStartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTX_pixeng_fetchrot9_AffineStartX_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AFFINESTARTY - Start value Y for affine warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTY_pixeng_fetchrot9_AffineStartY_MASK (0xFFFFF800U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTY_pixeng_fetchrot9_AffineStartY_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTY_pixeng_fetchrot9_AffineStartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTY_pixeng_fetchrot9_AffineStartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINESTARTY_pixeng_fetchrot9_AffineStartY_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AFFINEDELTAXX - DeltaXX increment for affine warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXX_pixeng_fetchrot9_AffineDeltaXX_MASK (0x1FFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXX_pixeng_fetchrot9_AffineDeltaXX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXX_pixeng_fetchrot9_AffineDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXX_pixeng_fetchrot9_AffineDeltaXX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXX_pixeng_fetchrot9_AffineDeltaXX_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AFFINEDELTAXY - DeltaXY increment for affine warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXY_pixeng_fetchrot9_AffineDeltaXY_MASK (0x1FFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXY_pixeng_fetchrot9_AffineDeltaXY_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXY_pixeng_fetchrot9_AffineDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXY_pixeng_fetchrot9_AffineDeltaXY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAXY_pixeng_fetchrot9_AffineDeltaXY_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AFFINEDELTAYX - DeltaYX increment for affine warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYX_pixeng_fetchrot9_AffineDeltaYX_MASK (0x1FFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYX_pixeng_fetchrot9_AffineDeltaYX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYX_pixeng_fetchrot9_AffineDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYX_pixeng_fetchrot9_AffineDeltaYX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYX_pixeng_fetchrot9_AffineDeltaYX_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_AFFINEDELTAYY - DeltaYY increment for affine warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYY_pixeng_fetchrot9_AffineDeltaYY_MASK (0x1FFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYY_pixeng_fetchrot9_AffineDeltaYY_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYY_pixeng_fetchrot9_AffineDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYY_pixeng_fetchrot9_AffineDeltaYY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_AFFINEDELTAYY_pixeng_fetchrot9_AffineDeltaYY_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_ARBSTARTX - Start value X for arbitrary warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTX_pixeng_fetchrot9_ArbStartX_MASK (0x1FFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTX_pixeng_fetchrot9_ArbStartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTX_pixeng_fetchrot9_ArbStartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTX_pixeng_fetchrot9_ArbStartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTX_pixeng_fetchrot9_ArbStartX_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_ARBSTARTY - Start value Y for arbitrary warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTY_pixeng_fetchrot9_ArbStartY_MASK (0x1FFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTY_pixeng_fetchrot9_ArbStartY_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTY_pixeng_fetchrot9_ArbStartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTY_pixeng_fetchrot9_ArbStartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBSTARTY_pixeng_fetchrot9_ArbStartY_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_ARBDELTA - Start values for delta incrementation of arbitrary warping. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXX_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXY_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXY_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaXY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYX_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYX_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYY_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYY_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_ARBDELTA_pixeng_fetchrot9_ArbDeltaYY_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_FIRPOSITIONS - FIR sequence control register. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR0Position_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR0Position_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR0Position(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR0Position_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR0Position_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR1Position_MASK (0xF0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR1Position_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR1Position(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR1Position_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR1Position_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR2Position_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR2Position_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR2Position(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR2Position_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR2Position_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR3Position_MASK (0xF000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR3Position_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR3Position(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR3Position_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRPOSITIONS_pixeng_fetchrot9_FIR3Position_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_FIRCOEFFICIENTS - FIR coefficients register. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR0Coefficient_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR0Coefficient_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR0Coefficient(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR0Coefficient_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR0Coefficient_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR1Coefficient_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR1Coefficient_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR1Coefficient(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR1Coefficient_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR1Coefficient_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR2Coefficient_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR2Coefficient_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR2Coefficient(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR2Coefficient_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR2Coefficient_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR3Coefficient_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR3Coefficient_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR3Coefficient(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR3Coefficient_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FIRCOEFFICIENTS_pixeng_fetchrot9_FIR3Coefficient_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RasterMode_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RasterMode_SHIFT (0U) /*! pixeng_fetchrot9_RasterMode * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot only] Arbitrary warping (filter is active). Coordinates are read from frame input * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is U. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. * 0b110..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is V. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RasterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RasterMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_InputSelect_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_InputSelect_SHIFT (3U) /*! pixeng_fetchrot9_InputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_InputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_InputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUV422UpsamplingMode_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUV422UpsamplingMode_SHIFT (5U) /*! pixeng_fetchrot9_YUV422UpsamplingMode * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUV422UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUV422UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_ClipColor_SHIFT (16U) /*! pixeng_fetchrot9_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_ClipColor_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_FilterMode_MASK (0x1C00000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_FilterMode_SHIFT (22U) /*! pixeng_fetchrot9_FilterMode * 0b000..Chooses pixel closest to sample point * 0b001..Calculates result from 4 pixels closest to sample point * 0b010..FIR mode with 2 programmable pixel positions and coefficients * 0b011..FIR mode with 4 programmable pixel positions and coefficients * 0b100..Calculates result from 2 pixels closest to the sample point and on the same line */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_FilterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_FilterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_FilterMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_Sync_En_MASK (0x2000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_Sync_En_SHIFT (25U) /*! pixeng_fetchrot9_Sync_En * 0b0..Synchronization disabled. * 0b1..Synchronization enabled. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_Sync_En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_Sync_En_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_Sync_En_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_WRPT_En_MASK (0x4000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_WRPT_En_SHIFT (26U) /*! pixeng_fetchrot9_WRPT_En * 0b0..Warp reference points table disabled. * 0b1..Warp reference points table enabled. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_WRPT_En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_WRPT_En_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_WRPT_En_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_En_MASK (0x8000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_En_SHIFT (27U) /*! pixeng_fetchrot9_YUVRot_En * 0b0..YUV mode rotation is disabled. * 0b1..YUV mode rotation is enabled. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_En_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_En_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_Mode_MASK (0x30000000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_Mode_SHIFT (28U) /*! pixeng_fetchrot9_YUVRot_Mode * 0b00..With Y0 at LSBs, order is Y0 U0 Y1 V0 Y2 U1 Y3 V1... * 0b01..With U0 at LSBs, order is U0 Y0 V0 Y1 U1 Y2 V1 Y3... * 0b10..With Y0 at LSBs, order is Y0 V0 Y1 U0 Y2 V1 Y3 U1... * 0b11..With V0 at LSBs, order is V0 Y0 U0 Y1 V1 Y2 U1 Y3... */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROL_pixeng_fetchrot9_YUVRot_Mode_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROLTRIGGER_pixeng_fetchrot9_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROLTRIGGER_pixeng_fetchrot9_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROLTRIGGER_pixeng_fetchrot9_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROLTRIGGER_pixeng_fetchrot9_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CONTROLTRIGGER_pixeng_fetchrot9_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_START_pixeng_fetchrot9_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_START_pixeng_fetchrot9_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_START_pixeng_fetchrot9_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_START_pixeng_fetchrot9_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_START_pixeng_fetchrot9_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FETCHTYPE_pixeng_fetchrot9_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FETCHTYPE_pixeng_fetchrot9_FetchType_SHIFT (0U) /*! pixeng_fetchrot9_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_FETCHTYPE_pixeng_fetchrot9_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_FETCHTYPE_pixeng_fetchrot9_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_FETCHTYPE_pixeng_fetchrot9_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_READADDRESS0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESS0_pixeng_fetchrot9_ReadAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESS0_pixeng_fetchrot9_ReadAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESS0_pixeng_fetchrot9_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESS0_pixeng_fetchrot9_ReadAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESS0_pixeng_fetchrot9_ReadAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_READADDRESSMSB0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESSMSB0_pixeng_fetchrot9_ReadAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESSMSB0_pixeng_fetchrot9_ReadAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESSMSB0_pixeng_fetchrot9_ReadAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESSMSB0_pixeng_fetchrot9_ReadAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_READADDRESSMSB0_pixeng_fetchrot9_ReadAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_BURSTBUFFERPROPERTIES_pixeng_fetchrot9_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_STATUS_pixeng_fetchrot9_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESS0_pixeng_fetchrot9_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESS0_pixeng_fetchrot9_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESS0_pixeng_fetchrot9_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESS0_pixeng_fetchrot9_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESS0_pixeng_fetchrot9_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESSMSB0_pixeng_fetchrot9_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESSMSB0_pixeng_fetchrot9_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESSMSB0_pixeng_fetchrot9_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESSMSB0_pixeng_fetchrot9_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_CURBASEADDRESSMSB0_pixeng_fetchrot9_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_HIDDENSTATUS_pixeng_fetchrot9_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_WARPLINEOFFSET - Offest between current used line and reference line. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MinLineOffset_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MinLineOffset_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MinLineOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MinLineOffset_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MinLineOffset_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MaxLineOffset_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MaxLineOffset_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MaxLineOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MaxLineOffset_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPLINEOFFSET_pixeng_fetchrot9_MaxLineOffset_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0 - Warp x interpolator table. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tblm1_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tblm1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tblm1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tblm1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tblm1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tbl00_MASK (0x7FFFC000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tbl00_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tbl00(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tbl00_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_pixeng_fetchrot9_WINTP_X_Tbl00_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0 */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE0_COUNT (64U) /*! @name PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1 - Warp x interpolator table. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp1_MASK (0x1FFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp2_MASK (0x7FFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp2_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_pixeng_fetchrot9_WINTP_X_Tblp2_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1 */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_X_FILTERTABLE1_COUNT (64U) /*! @name PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0 - Warp y interpolator table. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tblm1_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tblm1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tblm1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tblm1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tblm1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tbl00_MASK (0x7FFFC000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tbl00_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tbl00(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tbl00_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_pixeng_fetchrot9_WINTP_Y_Tbl00_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0 */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPINTERPOLATER_Y_FILTERTABLE0_COUNT (65U) /*! @name PIXENG_FETCHROT9_WRPT_TBL_CONTROL - Warping reference point table, write select. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WRPT_TBL_CONTROL_pixeng_fetchrot9_WRPT_cfg_Select_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WRPT_TBL_CONTROL_pixeng_fetchrot9_WRPT_cfg_Select_SHIFT (0U) /*! pixeng_fetchrot9_WRPT_cfg_Select * 0b0..Use WarpReferencePointsTable 0. * 0b1..Use WarpReferencePointsTable 1. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WRPT_TBL_CONTROL_pixeng_fetchrot9_WRPT_cfg_Select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WRPT_TBL_CONTROL_pixeng_fetchrot9_WRPT_cfg_Select_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WRPT_TBL_CONTROL_pixeng_fetchrot9_WRPT_cfg_Select_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0 - Warp reference points table 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaY_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaY_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaX_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaX_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_pixeng_fetchrot9_WRPT0_deltaX_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0 */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE0_COUNT (2048U) /*! @name PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1 - Warp reference points table 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaY_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaY_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaX_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaX_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_pixeng_fetchrot9_WRPT1_deltaX_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1 */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9_WARPREFERENCEPOINTSTABLE1_COUNT (2048U) /*! @name PIXENG_FETCHROT9CFG_FETCHROT9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9cfg_fetchrot9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9cfg_fetchrot9_LockUnlock_SHIFT (0U) /*! pixeng_fetchrot9cfg_fetchrot9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9cfg_fetchrot9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9cfg_fetchrot9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKUNLOCK_pixeng_fetchrot9cfg_fetchrot9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_LOCKSTATUS_pixeng_fetchrot9cfg_fetchrot9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9CFG_FETCHROT9_DYNAMIC - Dynamic pixel engine configuration for fetchrot9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_DYNAMIC_pixeng_fetchrot9cfg_fetchrot9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_DYNAMIC_pixeng_fetchrot9cfg_fetchrot9_src_sel_SHIFT (0U) /*! pixeng_fetchrot9cfg_fetchrot9_src_sel * 0b000000..Unit fetchrot9 input port src is disabled * 0b000110..Unit fetchrot9 input port src is connected to output of unit fetchdecode9 * 0b000111..Unit fetchrot9 input port src is connected to output of unit fetcheco9 */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_DYNAMIC_pixeng_fetchrot9cfg_fetchrot9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_DYNAMIC_pixeng_fetchrot9cfg_fetchrot9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_DYNAMIC_pixeng_fetchrot9cfg_fetchrot9_src_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHROT9CFG_FETCHROT9_STATUS - Status information for pixel engine configuration of fetchrot9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_STATUS_pixeng_fetchrot9cfg_fetchrot9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_STATUS_pixeng_fetchrot9cfg_fetchrot9_sel_SHIFT (16U) /*! pixeng_fetchrot9cfg_fetchrot9_sel * 0b000..fetchrot9 module is not used * 0b001..fetchrot9 module is used from store9 processing path * 0b010..fetchrot9 module is used from extdst0 processing path * 0b011..fetchrot9 module is used from extdst4 processing path * 0b100..fetchrot9 module is used from extdst1 processing path * 0b101..fetchrot9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_STATUS_pixeng_fetchrot9cfg_fetchrot9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_STATUS_pixeng_fetchrot9cfg_fetchrot9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHROT9CFG_FETCHROT9_STATUS_pixeng_fetchrot9cfg_fetchrot9_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9_LockUnlock_SHIFT (0U) /*! pixeng_fetchdecode9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATICCONTROL_pixeng_fetchdecode9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATICCONTROL_pixeng_fetchdecode9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATICCONTROL_pixeng_fetchdecode9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATICCONTROL_pixeng_fetchdecode9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATICCONTROL_pixeng_fetchdecode9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERMANAGEMENT_pixeng_fetchdecode9_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDR0_pixeng_fetchdecode9_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDR0_pixeng_fetchdecode9_RingBufStartAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDR0_pixeng_fetchdecode9_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDR0_pixeng_fetchdecode9_RingBufStartAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDR0_pixeng_fetchdecode9_RingBufStartAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_RINGBUFSTARTADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDRMSB0_pixeng_fetchdecode9_RingBufStartAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDRMSB0_pixeng_fetchdecode9_RingBufStartAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDRMSB0_pixeng_fetchdecode9_RingBufStartAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDRMSB0_pixeng_fetchdecode9_RingBufStartAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFSTARTADDRMSB0_pixeng_fetchdecode9_RingBufStartAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDR0_pixeng_fetchdecode9_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDR0_pixeng_fetchdecode9_RingBufWrapAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDR0_pixeng_fetchdecode9_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDR0_pixeng_fetchdecode9_RingBufWrapAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDR0_pixeng_fetchdecode9_RingBufWrapAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_RINGBUFWRAPADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDRMSB0_pixeng_fetchdecode9_RingBufWrapAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDRMSB0_pixeng_fetchdecode9_RingBufWrapAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDRMSB0_pixeng_fetchdecode9_RingBufWrapAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDRMSB0_pixeng_fetchdecode9_RingBufWrapAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_RINGBUFWRAPADDRMSB0_pixeng_fetchdecode9_RingBufWrapAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_FRAMEPROPERTIES0 - Frame property setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEPROPERTIES0_pixeng_fetchdecode9_FieldId0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEPROPERTIES0_pixeng_fetchdecode9_FieldId0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEPROPERTIES0_pixeng_fetchdecode9_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEPROPERTIES0_pixeng_fetchdecode9_FieldId0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEPROPERTIES0_pixeng_fetchdecode9_FieldId0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESS0_pixeng_fetchdecode9_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESS0_pixeng_fetchdecode9_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESS0_pixeng_fetchdecode9_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESS0_pixeng_fetchdecode9_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESS0_pixeng_fetchdecode9_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESSMSB0_pixeng_fetchdecode9_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESSMSB0_pixeng_fetchdecode9_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESSMSB0_pixeng_fetchdecode9_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESSMSB0_pixeng_fetchdecode9_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BASEADDRESSMSB0_pixeng_fetchdecode9_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESS0_pixeng_fetchdecode9_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESS0_pixeng_fetchdecode9_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESS0_pixeng_fetchdecode9_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESS0_pixeng_fetchdecode9_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESS0_pixeng_fetchdecode9_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchdecode9_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchdecode9_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchdecode9_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchdecode9_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchdecode9_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_pixeng_fetchdecode9_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERDIMENSION0_pixeng_fetchdecode9_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTBITS0_pixeng_fetchdecode9_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORCOMPONENTSHIFT0_pixeng_fetchdecode9_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYEROFFSET0_pixeng_fetchdecode9_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWOFFSET0_pixeng_fetchdecode9_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_pixeng_fetchdecode9_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONSTANTCOLOR0_pixeng_fetchdecode9_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PaletteEnable0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PaletteEnable0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PaletteEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PaletteEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_TileMode0_SHIFT (4U) /*! pixeng_fetchdecode9_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaMaskEnable0_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaMaskEnable0_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaMaskEnable0_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaMaskEnable0_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchdecode9_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_LAYERPROPERTY0_pixeng_fetchdecode9_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMEDIMENSIONS_pixeng_fetchdecode9_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FRAMERESAMPLING_pixeng_fetchdecode9_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_DECODECONTROL - Control options for RLAD decompression. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_CompressionMode_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_CompressionMode_SHIFT (0U) /*! pixeng_fetchdecode9_CompressionMode * 0b00..Run-Length Adaptive Dithering (lossy compression). * 0b01..Run-Length Adaptive Dithering (lossy compression; uniform package size). * 0b10..Run-Length Adaptive (lossless compression). * 0b11..Standard Run-Length. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_CompressionMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_CompressionMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADEndianness_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADEndianness_SHIFT (15U) /*! pixeng_fetchdecode9_RLADEndianness * 0b0..Big endian format * 0b1..Little endian format */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADEndianness_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADEndianness_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsRed_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsRed_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsRed_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsGreen_MASK (0xF00000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsGreen_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsGreen_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsBlue_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsBlue_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsBlue_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsAlpha_MASK (0xF0000000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsAlpha_SHIFT (28U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODECONTROL_pixeng_fetchdecode9_RLADCompBitsAlpha_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_SOURCEBUFFERLENGTH - Source buffer length for compressed data. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERLENGTH_pixeng_fetchdecode9_RLEWords_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERLENGTH_pixeng_fetchdecode9_RLEWords_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERLENGTH_pixeng_fetchdecode9_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERLENGTH_pixeng_fetchdecode9_RLEWords_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_SOURCEBUFFERLENGTH_pixeng_fetchdecode9_RLEWords_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RasterMode_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RasterMode_SHIFT (0U) /*! pixeng_fetchdecode9_RasterMode * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot only] Arbitrary warping (filter is active). Coordinates are read from frame input * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is U. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. * 0b110..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is V. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RasterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RasterMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_InputSelect_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_InputSelect_SHIFT (3U) /*! pixeng_fetchdecode9_InputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_InputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_InputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_YUV422UpsamplingMode_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_YUV422UpsamplingMode_SHIFT (5U) /*! pixeng_fetchdecode9_YUV422UpsamplingMode * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_YUV422UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_YUV422UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_PaletteIdxWidth_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_PaletteIdxWidth_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_PaletteIdxWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_PaletteIdxWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_ClipColor_SHIFT (16U) /*! pixeng_fetchdecode9_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROL_pixeng_fetchdecode9_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROLTRIGGER_pixeng_fetchdecode9_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROLTRIGGER_pixeng_fetchdecode9_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROLTRIGGER_pixeng_fetchdecode9_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROLTRIGGER_pixeng_fetchdecode9_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CONTROLTRIGGER_pixeng_fetchdecode9_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_START_pixeng_fetchdecode9_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_START_pixeng_fetchdecode9_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_START_pixeng_fetchdecode9_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_START_pixeng_fetchdecode9_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_START_pixeng_fetchdecode9_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FETCHTYPE_pixeng_fetchdecode9_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FETCHTYPE_pixeng_fetchdecode9_FetchType_SHIFT (0U) /*! pixeng_fetchdecode9_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FETCHTYPE_pixeng_fetchdecode9_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FETCHTYPE_pixeng_fetchdecode9_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_FETCHTYPE_pixeng_fetchdecode9_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_DECODERSTATUS - Status information of the RLAD decoder. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooSmall_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooSmall_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooSmall_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooSmall_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooLarge_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooLarge_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooLarge_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_DECODERSTATUS_pixeng_fetchdecode9_BufferTooLarge_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_READADDRESS0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESS0_pixeng_fetchdecode9_ReadAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESS0_pixeng_fetchdecode9_ReadAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESS0_pixeng_fetchdecode9_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESS0_pixeng_fetchdecode9_ReadAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESS0_pixeng_fetchdecode9_ReadAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_READADDRESSMSB0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESSMSB0_pixeng_fetchdecode9_ReadAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESSMSB0_pixeng_fetchdecode9_ReadAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESSMSB0_pixeng_fetchdecode9_ReadAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESSMSB0_pixeng_fetchdecode9_ReadAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_READADDRESSMSB0_pixeng_fetchdecode9_ReadAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_BURSTBUFFERPROPERTIES_pixeng_fetchdecode9_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_STATUS_pixeng_fetchdecode9_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESS0_pixeng_fetchdecode9_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESS0_pixeng_fetchdecode9_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESS0_pixeng_fetchdecode9_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESS0_pixeng_fetchdecode9_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESS0_pixeng_fetchdecode9_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESSMSB0_pixeng_fetchdecode9_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESSMSB0_pixeng_fetchdecode9_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESSMSB0_pixeng_fetchdecode9_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESSMSB0_pixeng_fetchdecode9_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_CURBASEADDRESSMSB0_pixeng_fetchdecode9_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_HIDDENSTATUS_pixeng_fetchdecode9_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9_COLORPALETTE - Color palette look up table. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORPALETTE_pixeng_fetchdecode9_ColorPalette_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORPALETTE_pixeng_fetchdecode9_ColorPalette_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORPALETTE_pixeng_fetchdecode9_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORPALETTE_pixeng_fetchdecode9_ColorPalette_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORPALETTE_pixeng_fetchdecode9_ColorPalette_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORPALETTE */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9_COLORPALETTE_COUNT (256U) /*! @name PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9cfg_fetchdecode9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9cfg_fetchdecode9_LockUnlock_SHIFT (0U) /*! pixeng_fetchdecode9cfg_fetchdecode9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9cfg_fetchdecode9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9cfg_fetchdecode9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKUNLOCK_pixeng_fetchdecode9cfg_fetchdecode9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_LOCKSTATUS_pixeng_fetchdecode9cfg_fetchdecode9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9CFG_FETCHDECODE9_DYNAMIC - Dynamic pixel engine configuration for fetchdecode9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_DYNAMIC_pixeng_fetchdecode9cfg_fetchdecode9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_DYNAMIC_pixeng_fetchdecode9cfg_fetchdecode9_src_sel_SHIFT (0U) /*! pixeng_fetchdecode9cfg_fetchdecode9_src_sel * 0b000000..Unit fetchdecode9 input port src is disabled * 0b000101..Unit fetchdecode9 input port src is connected to output of unit fetchrot9 * 0b000111..Unit fetchdecode9 input port src is connected to output of unit fetcheco9 */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_DYNAMIC_pixeng_fetchdecode9cfg_fetchdecode9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_DYNAMIC_pixeng_fetchdecode9cfg_fetchdecode9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_DYNAMIC_pixeng_fetchdecode9cfg_fetchdecode9_src_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHDECODE9CFG_FETCHDECODE9_STATUS - Status information for pixel engine configuration of fetchdecode9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_STATUS_pixeng_fetchdecode9cfg_fetchdecode9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_STATUS_pixeng_fetchdecode9cfg_fetchdecode9_sel_SHIFT (16U) /*! pixeng_fetchdecode9cfg_fetchdecode9_sel * 0b000..fetchdecode9 module is not used * 0b001..fetchdecode9 module is used from store9 processing path * 0b010..fetchdecode9 module is used from extdst0 processing path * 0b011..fetchdecode9 module is used from extdst4 processing path * 0b100..fetchdecode9 module is used from extdst1 processing path * 0b101..fetchdecode9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_STATUS_pixeng_fetchdecode9cfg_fetchdecode9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_STATUS_pixeng_fetchdecode9cfg_fetchdecode9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHDECODE9CFG_FETCHDECODE9_STATUS_pixeng_fetchdecode9cfg_fetchdecode9_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_STATICCONTROL_pixeng_fetcheco9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_STATICCONTROL_pixeng_fetcheco9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_STATICCONTROL_pixeng_fetcheco9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_STATICCONTROL_pixeng_fetcheco9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_STATICCONTROL_pixeng_fetcheco9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERMANAGEMENT_pixeng_fetcheco9_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESS0_pixeng_fetcheco9_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESS0_pixeng_fetcheco9_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESS0_pixeng_fetcheco9_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESS0_pixeng_fetcheco9_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESS0_pixeng_fetcheco9_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESSMSB0_pixeng_fetcheco9_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESSMSB0_pixeng_fetcheco9_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESSMSB0_pixeng_fetcheco9_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESSMSB0_pixeng_fetcheco9_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BASEADDRESSMSB0_pixeng_fetcheco9_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco9_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco9_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco9_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco9_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco9_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco9_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco9_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco9_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco9_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco9_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco9_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_SOURCEBUFFERDIMENSION0_pixeng_fetcheco9_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTBITS0_pixeng_fetcheco9_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_COLORCOMPONENTSHIFT0_pixeng_fetcheco9_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYEROFFSET0_pixeng_fetcheco9_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWOFFSET0_pixeng_fetcheco9_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco9_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CONSTANTCOLOR0_pixeng_fetcheco9_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_TileMode0_SHIFT (4U) /*! pixeng_fetcheco9_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_LAYERPROPERTY0_pixeng_fetcheco9_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMEDIMENSIONS_pixeng_fetcheco9_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FRAMERESAMPLING_pixeng_fetcheco9_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_ClipColor_SHIFT (16U) /*! pixeng_fetcheco9_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROL_pixeng_fetcheco9_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROLTRIGGER_pixeng_fetcheco9_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROLTRIGGER_pixeng_fetcheco9_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROLTRIGGER_pixeng_fetcheco9_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROLTRIGGER_pixeng_fetcheco9_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CONTROLTRIGGER_pixeng_fetcheco9_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_START_pixeng_fetcheco9_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_START_pixeng_fetcheco9_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_START_pixeng_fetcheco9_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_START_pixeng_fetcheco9_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_START_pixeng_fetcheco9_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FETCHTYPE_pixeng_fetcheco9_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FETCHTYPE_pixeng_fetcheco9_FetchType_SHIFT (0U) /*! pixeng_fetcheco9_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_FETCHTYPE_pixeng_fetcheco9_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_FETCHTYPE_pixeng_fetcheco9_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_FETCHTYPE_pixeng_fetcheco9_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_BURSTBUFFERPROPERTIES_pixeng_fetcheco9_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESS0_pixeng_fetcheco9_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESS0_pixeng_fetcheco9_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESS0_pixeng_fetcheco9_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESS0_pixeng_fetcheco9_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESS0_pixeng_fetcheco9_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESSMSB0_pixeng_fetcheco9_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESSMSB0_pixeng_fetcheco9_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESSMSB0_pixeng_fetcheco9_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESSMSB0_pixeng_fetcheco9_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_CURBASEADDRESSMSB0_pixeng_fetcheco9_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9_HIDDENSTATUS_pixeng_fetcheco9_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9CFG_FETCHECO9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9cfg_fetcheco9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9cfg_fetcheco9_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco9cfg_fetcheco9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9cfg_fetcheco9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9cfg_fetcheco9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKUNLOCK_pixeng_fetcheco9cfg_fetcheco9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_LOCKSTATUS_pixeng_fetcheco9cfg_fetcheco9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO9CFG_FETCHECO9_STATUS - Status information for pixel engine configuration of fetcheco9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_STATUS_pixeng_fetcheco9cfg_fetcheco9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_STATUS_pixeng_fetcheco9cfg_fetcheco9_sel_SHIFT (16U) /*! pixeng_fetcheco9cfg_fetcheco9_sel * 0b000..fetcheco9 module is not used * 0b001..fetcheco9 module is used from store9 processing path * 0b010..fetcheco9 module is used from extdst0 processing path * 0b011..fetcheco9 module is used from extdst4 processing path * 0b100..fetcheco9 module is used from extdst1 processing path * 0b101..fetcheco9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_STATUS_pixeng_fetcheco9cfg_fetcheco9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_STATUS_pixeng_fetcheco9cfg_fetcheco9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO9CFG_FETCHECO9_STATUS_pixeng_fetcheco9cfg_fetcheco9_sel_MASK) /*! @} */ /*! @name PIXENG_HSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9_LockUnlock_SHIFT (0U) /*! pixeng_hscaler9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_HSCALER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_LOCKSTATUS_pixeng_hscaler9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_HSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_STATICCONTROL_pixeng_hscaler9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_STATICCONTROL_pixeng_hscaler9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_STATICCONTROL_pixeng_hscaler9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_STATICCONTROL_pixeng_hscaler9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_STATICCONTROL_pixeng_hscaler9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_HSCALER9_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP1_pixeng_hscaler9_scale_factor_MASK (0xFFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP1_pixeng_hscaler9_scale_factor_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP1_pixeng_hscaler9_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP1_pixeng_hscaler9_scale_factor_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP1_pixeng_hscaler9_scale_factor_MASK) /*! @} */ /*! @name PIXENG_HSCALER9_SETUP2 - Phase interpolator setup. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP2_pixeng_hscaler9_phase_offset_MASK (0x1FFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP2_pixeng_hscaler9_phase_offset_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP2_pixeng_hscaler9_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP2_pixeng_hscaler9_phase_offset_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_SETUP2_pixeng_hscaler9_phase_offset_MASK) /*! @} */ /*! @name PIXENG_HSCALER9_CONTROL - Scaler operation control. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_mode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_mode_SHIFT (0U) /*! pixeng_hscaler9_mode * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_mode_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_scale_mode_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_scale_mode_SHIFT (4U) /*! pixeng_hscaler9_scale_mode * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size) */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_scale_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_scale_mode_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_filter_mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_filter_mode_SHIFT (8U) /*! pixeng_hscaler9_filter_mode * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_filter_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_filter_mode_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_output_size_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_output_size_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_output_size(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_output_size_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9_CONTROL_pixeng_hscaler9_output_size_MASK) /*! @} */ /*! @name PIXENG_HSCALER9CFG_HSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9cfg_hscaler9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9cfg_hscaler9_LockUnlock_SHIFT (0U) /*! pixeng_hscaler9cfg_hscaler9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9cfg_hscaler9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9cfg_hscaler9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKUNLOCK_pixeng_hscaler9cfg_hscaler9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_LOCKSTATUS_pixeng_hscaler9cfg_hscaler9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC - Dynamic pixel engine configuration for hscaler9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_src_sel_SHIFT (0U) /*! pixeng_hscaler9cfg_hscaler9_src_sel * 0b000000..Unit hscaler9 input port src is disabled * 0b000011..Unit hscaler9 input port src is connected to output of unit matrix9 * 0b001001..Unit hscaler9 input port src is connected to output of unit vscaler9 * 0b001010..Unit hscaler9 input port src is connected to output of unit filter9 */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_clken_SHIFT (24U) /*! pixeng_hscaler9cfg_hscaler9_clken * 0b00..Clock for hscaler9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for hscaler9 is without gating */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_DYNAMIC_pixeng_hscaler9cfg_hscaler9_clken_MASK) /*! @} */ /*! @name PIXENG_HSCALER9CFG_HSCALER9_STATUS - Status information for pixel engine configuration of hscaler9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_STATUS_pixeng_hscaler9cfg_hscaler9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_STATUS_pixeng_hscaler9cfg_hscaler9_sel_SHIFT (16U) /*! pixeng_hscaler9cfg_hscaler9_sel * 0b000..hscaler9 module is not used * 0b001..hscaler9 module is used from store9 processing path * 0b010..hscaler9 module is used from extdst0 processing path * 0b011..hscaler9 module is used from extdst4 processing path * 0b100..hscaler9 module is used from extdst1 processing path * 0b101..hscaler9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_STATUS_pixeng_hscaler9cfg_hscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_STATUS_pixeng_hscaler9cfg_hscaler9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER9CFG_HSCALER9_STATUS_pixeng_hscaler9cfg_hscaler9_sel_MASK) /*! @} */ /*! @name PIXENG_VSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9_LockUnlock_SHIFT (0U) /*! pixeng_vscaler9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_VSCALER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_LOCKSTATUS_pixeng_vscaler9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_VSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_STATICCONTROL_pixeng_vscaler9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_STATICCONTROL_pixeng_vscaler9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_STATICCONTROL_pixeng_vscaler9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_STATICCONTROL_pixeng_vscaler9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_STATICCONTROL_pixeng_vscaler9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_VSCALER9_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP1_pixeng_vscaler9_scale_factor_MASK (0xFFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP1_pixeng_vscaler9_scale_factor_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP1_pixeng_vscaler9_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP1_pixeng_vscaler9_scale_factor_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP1_pixeng_vscaler9_scale_factor_MASK) /*! @} */ /*! @name PIXENG_VSCALER9_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP2_pixeng_vscaler9_phase_offset_MASK (0x1FFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP2_pixeng_vscaler9_phase_offset_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP2_pixeng_vscaler9_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP2_pixeng_vscaler9_phase_offset_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_SETUP2_pixeng_vscaler9_phase_offset_MASK) /*! @} */ /*! @name PIXENG_VSCALER9_CONTROL - Scaler operation control. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_mode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_mode_SHIFT (0U) /*! pixeng_vscaler9_mode * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_mode_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_scale_mode_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_scale_mode_SHIFT (4U) /*! pixeng_vscaler9_scale_mode * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size). */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_scale_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_scale_mode_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_filter_mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_filter_mode_SHIFT (8U) /*! pixeng_vscaler9_filter_mode * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_filter_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_filter_mode_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_output_size_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_output_size_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_output_size(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_output_size_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9_CONTROL_pixeng_vscaler9_output_size_MASK) /*! @} */ /*! @name PIXENG_VSCALER9CFG_VSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9cfg_vscaler9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9cfg_vscaler9_LockUnlock_SHIFT (0U) /*! pixeng_vscaler9cfg_vscaler9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9cfg_vscaler9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9cfg_vscaler9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKUNLOCK_pixeng_vscaler9cfg_vscaler9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_LOCKSTATUS_pixeng_vscaler9cfg_vscaler9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC - Dynamic pixel engine configuration for vscaler9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_src_sel_SHIFT (0U) /*! pixeng_vscaler9cfg_vscaler9_src_sel * 0b000000..Unit vscaler9 input port src is disabled * 0b000011..Unit vscaler9 input port src is connected to output of unit matrix9 * 0b001000..Unit vscaler9 input port src is connected to output of unit hscaler9 */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_clken_SHIFT (24U) /*! pixeng_vscaler9cfg_vscaler9_clken * 0b00..Clock for vscaler9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for vscaler9 is without gating */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_DYNAMIC_pixeng_vscaler9cfg_vscaler9_clken_MASK) /*! @} */ /*! @name PIXENG_VSCALER9CFG_VSCALER9_STATUS - Status information for pixel engine configuration of vscaler9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_STATUS_pixeng_vscaler9cfg_vscaler9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_STATUS_pixeng_vscaler9cfg_vscaler9_sel_SHIFT (16U) /*! pixeng_vscaler9cfg_vscaler9_sel * 0b000..vscaler9 module is not used * 0b001..vscaler9 module is used from store9 processing path * 0b010..vscaler9 module is used from extdst0 processing path * 0b011..vscaler9 module is used from extdst4 processing path * 0b100..vscaler9 module is used from extdst1 processing path * 0b101..vscaler9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_STATUS_pixeng_vscaler9cfg_vscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_STATUS_pixeng_vscaler9cfg_vscaler9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER9CFG_VSCALER9_STATUS_pixeng_vscaler9cfg_vscaler9_sel_MASK) /*! @} */ /*! @name PIXENG_FILTER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKUNLOCK_pixeng_filter9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKUNLOCK_pixeng_filter9_LockUnlock_SHIFT (0U) /*! pixeng_filter9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKUNLOCK_pixeng_filter9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_LOCKUNLOCK_pixeng_filter9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_LOCKUNLOCK_pixeng_filter9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FILTER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_LOCKSTATUS_pixeng_filter9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FILTER9_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_STATICCONTROL_pixeng_filter9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FILTER9_STATICCONTROL_pixeng_filter9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_STATICCONTROL_pixeng_filter9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_STATICCONTROL_pixeng_filter9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_STATICCONTROL_pixeng_filter9_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FILTER9_CONTROL - Filter operation main control. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_mode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_mode_SHIFT (0U) /*! pixeng_filter9_mode * 0b0..Neutral mode. Pixels by-pass the filter, all other settings are ignored. * 0b1..Filter is active. */ #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_mode_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_tile_mode_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_tile_mode_SHIFT (4U) /*! pixeng_filter9_tile_mode * 0b00..Samples outside the frame are padded with the last valid border pixels. * 0b01..Samples outside the frame are treated as zero pixel value. * 0b10..Applies tile mode PAD to RGB channels and tile mode ZERO to alpha channel. */ #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_tile_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_tile_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_tile_mode_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_filter_mode_MASK (0xFFFF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_filter_mode_SHIFT (8U) /*! pixeng_filter9_filter_mode * 0b0000000001010101..FIR filter 5x5 window. */ #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_filter_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_filter_mode_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_buffer_format_MASK (0x30000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_buffer_format_SHIFT (28U) /*! pixeng_filter9_buffer_format * 0b00..RGB888 format. Alpha is not filtered but set to constant value 255. * 0b01..RGBA5658 format. Alpha is filtered. * 0b10..RGBA8888 format. Alpha is filtered. The filter window is limited to 5x4. * 0b11..RGBA10.10.10.8 format. Alpha is filtered. The filter window is limited to 5x3. */ #define DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_buffer_format(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_buffer_format_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_CONTROL_pixeng_filter9_buffer_format_MASK) /*! @} */ /*! @name PIXENG_FILTER9_FIR_CONTROL - FIR filter operation control. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_component_select_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_component_select_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_component_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_component_select_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_component_select_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_exponent_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_exponent_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_exponent(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_exponent_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_FIR_CONTROL_pixeng_filter9_FIR_exponent_MASK) /*! @} */ /*! @name PIXENG_FILTER9_COEFFICIENTS0 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff0_0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff0_0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff0_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff0_0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff0_0_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff1_0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff1_0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff1_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff1_0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff1_0_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff2_0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff2_0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff2_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff2_0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff2_0_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff3_0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff3_0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff3_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff3_0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS0_pixeng_filter9_coeff3_0_MASK) /*! @} */ /*! @name PIXENG_FILTER9_COEFFICIENTS1 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff4_0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff4_0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff4_0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff4_0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff4_0_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff0_1_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff0_1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff0_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff0_1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff0_1_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff1_1_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff1_1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff1_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff1_1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff1_1_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff2_1_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff2_1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff2_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff2_1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS1_pixeng_filter9_coeff2_1_MASK) /*! @} */ /*! @name PIXENG_FILTER9_COEFFICIENTS2 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff3_1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff3_1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff3_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff3_1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff3_1_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff4_1_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff4_1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff4_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff4_1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff4_1_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff0_2_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff0_2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff0_2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff0_2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff0_2_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff1_2_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff1_2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff1_2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff1_2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS2_pixeng_filter9_coeff1_2_MASK) /*! @} */ /*! @name PIXENG_FILTER9_COEFFICIENTS3 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff2_2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff2_2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff2_2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff2_2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff2_2_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff3_2_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff3_2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff3_2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff3_2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff3_2_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff4_2_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff4_2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff4_2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff4_2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff4_2_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff0_3_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff0_3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff0_3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff0_3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS3_pixeng_filter9_coeff0_3_MASK) /*! @} */ /*! @name PIXENG_FILTER9_COEFFICIENTS4 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff1_3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff1_3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff1_3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff1_3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff1_3_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff2_3_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff2_3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff2_3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff2_3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff2_3_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff3_3_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff3_3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff3_3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff3_3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff3_3_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff4_3_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff4_3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff4_3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff4_3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS4_pixeng_filter9_coeff4_3_MASK) /*! @} */ /*! @name PIXENG_FILTER9_COEFFICIENTS5 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff0_4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff0_4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff0_4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff0_4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff0_4_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff1_4_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff1_4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff1_4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff1_4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff1_4_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff2_4_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff2_4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff2_4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff2_4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff2_4_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff3_4_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff3_4_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff3_4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff3_4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS5_pixeng_filter9_coeff3_4_MASK) /*! @} */ /*! @name PIXENG_FILTER9_COEFFICIENTS6 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS6_pixeng_filter9_coeff4_4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS6_pixeng_filter9_coeff4_4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS6_pixeng_filter9_coeff4_4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS6_pixeng_filter9_coeff4_4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9_COEFFICIENTS6_pixeng_filter9_coeff4_4_MASK) /*! @} */ /*! @name PIXENG_FILTER9CFG_FILTER9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKUNLOCK_pixeng_filter9cfg_filter9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKUNLOCK_pixeng_filter9cfg_filter9_LockUnlock_SHIFT (0U) /*! pixeng_filter9cfg_filter9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKUNLOCK_pixeng_filter9cfg_filter9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKUNLOCK_pixeng_filter9cfg_filter9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKUNLOCK_pixeng_filter9cfg_filter9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_LOCKSTATUS_pixeng_filter9cfg_filter9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FILTER9CFG_FILTER9_DYNAMIC - Dynamic pixel engine configuration for filter9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_src_sel_SHIFT (0U) /*! pixeng_filter9cfg_filter9_src_sel * 0b000000..Unit filter9 input port src is disabled * 0b000011..Unit filter9 input port src is connected to output of unit matrix9 * 0b001000..Unit filter9 input port src is connected to output of unit hscaler9 */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_clken_SHIFT (24U) /*! pixeng_filter9cfg_filter9_clken * 0b00..Clock for filter9 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for filter9 is without gating */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_DYNAMIC_pixeng_filter9cfg_filter9_clken_MASK) /*! @} */ /*! @name PIXENG_FILTER9CFG_FILTER9_STATUS - Status information for pixel engine configuration of filter9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_STATUS_pixeng_filter9cfg_filter9_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_STATUS_pixeng_filter9cfg_filter9_sel_SHIFT (16U) /*! pixeng_filter9cfg_filter9_sel * 0b000..filter9 module is not used * 0b001..filter9 module is used from store9 processing path * 0b010..filter9 module is used from extdst0 processing path * 0b011..filter9 module is used from extdst4 processing path * 0b100..filter9 module is used from extdst1 processing path * 0b101..filter9 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_STATUS_pixeng_filter9cfg_filter9_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_STATUS_pixeng_filter9cfg_filter9_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FILTER9CFG_FILTER9_STATUS_pixeng_filter9cfg_filter9_sel_MASK) /*! @} */ /*! @name PIXENG_STORE9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKUNLOCK_pixeng_store9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKUNLOCK_pixeng_store9_LockUnlock_SHIFT (0U) /*! pixeng_store9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKUNLOCK_pixeng_store9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_LOCKUNLOCK_pixeng_store9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_LOCKUNLOCK_pixeng_store9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_STORE9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_LOCKSTATUS_pixeng_store9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_STORE9_STATICCONTROL - Store unit static control register. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_BaseAddressAutoUpdate_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_BaseAddressAutoUpdate_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_BaseAddressAutoUpdate_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_STATICCONTROL_pixeng_store9_BaseAddressAutoUpdate_MASK) /*! @} */ /*! @name PIXENG_STORE9_BURSTBUFFERMANAGEMENT - Burst Buffer setup register. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_FlexibleBurstLengthMax_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_FlexibleBurstLengthMax_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_FlexibleBurstLengthMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_FlexibleBurstLengthMax_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_FlexibleBurstLengthMax_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimerEn_MASK (0x800000U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimerEn_SHIFT (23U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimerEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimerEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimerEn_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimeout_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimeout_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERMANAGEMENT_pixeng_store9_BurstTimeout_MASK) /*! @} */ /*! @name PIXENG_STORE9_RINGBUFSTARTADDR - Ring buffer setup for destination. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDR_pixeng_store9_RingBufStartAddr_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDR_pixeng_store9_RingBufStartAddr_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDR_pixeng_store9_RingBufStartAddr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDR_pixeng_store9_RingBufStartAddr_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDR_pixeng_store9_RingBufStartAddr_MASK) /*! @} */ /*! @name PIXENG_STORE9_RINGBUFSTARTADDRMSB - Ring buffer setup for destination. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDRMSB_pixeng_store9_RingBufStartAddrMSB_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDRMSB_pixeng_store9_RingBufStartAddrMSB_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDRMSB_pixeng_store9_RingBufStartAddrMSB(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDRMSB_pixeng_store9_RingBufStartAddrMSB_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFSTARTADDRMSB_pixeng_store9_RingBufStartAddrMSB_MASK) /*! @} */ /*! @name PIXENG_STORE9_RINGBUFWRAPADDR - Ring buffer setup for destination. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDR_pixeng_store9_RingBufWrapAddr_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDR_pixeng_store9_RingBufWrapAddr_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDR_pixeng_store9_RingBufWrapAddr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDR_pixeng_store9_RingBufWrapAddr_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDR_pixeng_store9_RingBufWrapAddr_MASK) /*! @} */ /*! @name PIXENG_STORE9_RINGBUFWRAPADDRMSB - Ring buffer setup for destination. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDRMSB_pixeng_store9_RingBufWrapAddrMSB_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDRMSB_pixeng_store9_RingBufWrapAddrMSB_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDRMSB_pixeng_store9_RingBufWrapAddrMSB(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDRMSB_pixeng_store9_RingBufWrapAddrMSB_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_RINGBUFWRAPADDRMSB_pixeng_store9_RingBufWrapAddrMSB_MASK) /*! @} */ /*! @name PIXENG_STORE9_BASEADDRESS0 - Destination buffer 0 base address. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS0_pixeng_store9_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS0_pixeng_store9_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS0_pixeng_store9_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS0_pixeng_store9_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS0_pixeng_store9_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_STORE9_BASEADDRESSMSB0 - Destination buffer 0 base address. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB0_pixeng_store9_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB0_pixeng_store9_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB0_pixeng_store9_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB0_pixeng_store9_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB0_pixeng_store9_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_STORE9_AUTOUPDATEBASEADDRESS0 - Destination buffer 0 base address for auto update feature. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESS0_pixeng_store9_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESS0_pixeng_store9_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESS0_pixeng_store9_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESS0_pixeng_store9_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESS0_pixeng_store9_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_STORE9_AUTOUPDATEBASEADDRESSMSB0 - Destination buffer 0 base address for auto update feature. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_store9_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_store9_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_store9_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_store9_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_AUTOUPDATEBASEADDRESSMSB0_pixeng_store9_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0 - Destination buffer 0 attributes. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_Stride0_MASK (0x1FFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_AlphaEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_AlphaEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_AlphaEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_AlphaEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_AlphaEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_RedEnable0_MASK (0x200000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_RedEnable0_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_RedEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_RedEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_RedEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_GreenEnable0_MASK (0x400000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_GreenEnable0_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_GreenEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_GreenEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_GreenEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BlueEnable0_MASK (0x800000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BlueEnable0_SHIFT (23U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BlueEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BlueEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BlueEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BitsPerPixel0_MASK (0x7F000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BitsPerPixel0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES0_pixeng_store9_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_STORE9_BASEADDRESS1 - Destination buffer 1 base address. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS1_pixeng_store9_BaseAddress1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS1_pixeng_store9_BaseAddress1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS1_pixeng_store9_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS1_pixeng_store9_BaseAddress1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS1_pixeng_store9_BaseAddress1_MASK) /*! @} */ /*! @name PIXENG_STORE9_BASEADDRESSMSB1 - Destination buffer 1 base address. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB1_pixeng_store9_BaseAddressMSB1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB1_pixeng_store9_BaseAddressMSB1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB1_pixeng_store9_BaseAddressMSB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB1_pixeng_store9_BaseAddressMSB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB1_pixeng_store9_BaseAddressMSB1_MASK) /*! @} */ /*! @name PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1 - Destination buffer 1 attributes. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_Stride1_MASK (0x1FFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_Stride1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_Stride1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_Stride1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_Stride1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_XDownscale1_MASK (0x20000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_XDownscale1_SHIFT (17U) /*! pixeng_store9_XDownscale1 * 0b0..write every pixel to buffer. * 0b1..write every second pixel to buffer. Enables YUV422Downsampling. Only for Rastermode = NORMAL. All * correlated widths and horizontal offsets must be even. */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_XDownscale1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_XDownscale1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_XDownscale1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_YDownscale1_MASK (0x40000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_YDownscale1_SHIFT (18U) /*! pixeng_store9_YDownscale1 * 0b0..write every line to buffer. * 0b1..write every second line to buffer. Enables YUV420Downsampling. All correlated heights and vertical offsets must be even. */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_YDownscale1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_YDownscale1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_YDownscale1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_AlphaEnable1_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_AlphaEnable1_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_AlphaEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_AlphaEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_AlphaEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_RedEnable1_MASK (0x200000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_RedEnable1_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_RedEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_RedEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_RedEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_GreenEnable1_MASK (0x400000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_GreenEnable1_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_GreenEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_GreenEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_GreenEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BlueEnable1_MASK (0x800000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BlueEnable1_SHIFT (23U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BlueEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BlueEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BlueEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BitsPerPixel1_MASK (0x3F000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BitsPerPixel1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BitsPerPixel1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_BitsPerPixel1_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_DWordByteSwap1_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_DWordByteSwap1_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_DWordByteSwap1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_DWordByteSwap1_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES1_pixeng_store9_DWordByteSwap1_MASK) /*! @} */ /*! @name PIXENG_STORE9_BASEADDRESS2 - Destination buffer 2 base address. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS2_pixeng_store9_BaseAddress2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS2_pixeng_store9_BaseAddress2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS2_pixeng_store9_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS2_pixeng_store9_BaseAddress2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESS2_pixeng_store9_BaseAddress2_MASK) /*! @} */ /*! @name PIXENG_STORE9_BASEADDRESSMSB2 - Destination buffer 2 base address (upper 8 bits). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB2_pixeng_store9_BaseAddressMSB2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB2_pixeng_store9_BaseAddressMSB2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB2_pixeng_store9_BaseAddressMSB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB2_pixeng_store9_BaseAddressMSB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BASEADDRESSMSB2_pixeng_store9_BaseAddressMSB2_MASK) /*! @} */ /*! @name PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2 - Destination buffer 2 attributes. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_Stride2_MASK (0x1FFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_Stride2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_Stride2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_Stride2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_Stride2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_XDownscale2_MASK (0x20000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_XDownscale2_SHIFT (17U) /*! pixeng_store9_XDownscale2 * 0b0..write every pixel to buffer. * 0b1..write every second pixel to buffer. Enables YUV422Downsampling. Only for Rastermode = NORMAL. All * correlated widths and horizontal offsets must be even. */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_XDownscale2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_XDownscale2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_XDownscale2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_YDownscale2_MASK (0x40000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_YDownscale2_SHIFT (18U) /*! pixeng_store9_YDownscale2 * 0b0..write every line to buffer. * 0b1..write every second line to buffer. Enables YUV420Downsampling. All correlated heights and vertical offsets must be even. */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_YDownscale2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_YDownscale2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_YDownscale2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_AlphaEnable2_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_AlphaEnable2_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_AlphaEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_AlphaEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_AlphaEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_RedEnable2_MASK (0x200000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_RedEnable2_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_RedEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_RedEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_RedEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_GreenEnable2_MASK (0x400000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_GreenEnable2_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_GreenEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_GreenEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_GreenEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BlueEnable2_MASK (0x800000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BlueEnable2_SHIFT (23U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BlueEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BlueEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BlueEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BitsPerPixel2_MASK (0x3F000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BitsPerPixel2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BitsPerPixel2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_BitsPerPixel2_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_DWordByteSwap2_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_DWordByteSwap2_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_DWordByteSwap2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_DWordByteSwap2_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERATTRIBUTES2_pixeng_store9_DWordByteSwap2_MASK) /*! @} */ /*! @name PIXENG_STORE9_DESTINATIONBUFFERDIMENSION - Destination buffer dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineWidth_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineCount_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineCount_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineCount(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineCount_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_DESTINATIONBUFFERDIMENSION_pixeng_store9_LineCount_MASK) /*! @} */ /*! @name PIXENG_STORE9_FRAMEOFFSET - Offset between destination frame and buffer. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameXOffset_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameXOffset_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameXOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameXOffset_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameXOffset_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameYOffset_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameYOffset_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameYOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameYOffset_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_FRAMEOFFSET_pixeng_store9_FrameYOffset_MASK) /*! @} */ /*! @name PIXENG_STORE9_COLORCOMPONENTBITS - Color component size of destination buffer */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsAlpha_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsBlue_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsBlue_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsGreen_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsGreen_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsRed_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTBITS_pixeng_store9_ComponentBitsRed_MASK) /*! @} */ /*! @name PIXENG_STORE9_COLORCOMPONENTSHIFT - Color component offset of destination buffer. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftAlpha_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftBlue_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftBlue_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftGreen_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftGreen_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftRed_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_COLORCOMPONENTSHIFT_pixeng_store9_ComponentShiftRed_MASK) /*! @} */ /*! @name PIXENG_STORE9_CONTROL - Store unit dynamic control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_ColorDitherEnable_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_ColorDitherEnable_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_ColorDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_ColorDitherEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_ColorDitherEnable_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_AlphaDitherEnable_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_AlphaDitherEnable_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_AlphaDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_AlphaDitherEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_AlphaDitherEnable_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_DitherOffset_MASK (0xF0U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_DitherOffset_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_DitherOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_DitherOffset_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_DitherOffset_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_GammaApplyEnable_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_GammaApplyEnable_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_GammaApplyEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_GammaApplyEnable_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUVConversionMode_MASK (0x30000U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUVConversionMode_SHIFT (16U) /*! pixeng_store9_YUVConversionMode * 0b00..No conversion. Input data must be RGB. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUVConversionMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUVConversionMode_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_RasterMode_MASK (0xC0000U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_RasterMode_SHIFT (18U) /*! pixeng_store9_RasterMode * 0b00..RGBA or YUV 4:4:4 pixel buffer. * 0b01..Packed YUV 4:2:2 pixel buffer. Effect is that U samples are written for pixels with even and V samples * for odd column index only. Enables YUV422Downsampling. So BitsPerPixel must be set to the size that a pair * of YU or YV has in memory (most typically 16 bits). All correlated widths and horizontal offsets must be * even. * 0b10..[Store derivate only] RLAD compressed bit stream. * 0b11..Packed YUV 4:2:2 pixel buffer. Effect is that V samples are written for pixels with even and U samples * for odd column index only. Enables YUV422Downsampling. So BitsPerPixel must be set to the size that a pair * of YU or YV has in memory (most typically 16 bits). All correlated widths and horizontal offsets must be * even. */ #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_RasterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_RasterMode_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV422DownsamplingMode_MASK (0x300000U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV422DownsamplingMode_SHIFT (20U) /*! pixeng_store9_YUV422DownsamplingMode * 0b00..Nearest mode. Discards all odd samples, outputs even samples. * 0b01..Linear coaligned mode. 3 nearest UV samples are combined in linear filter to get one output sample. * 0b10..Linear interspersed mode. 2 nearest UV samples are combined in linear filter to get one output sample. */ #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV422DownsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV422DownsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV422DownsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV420DownsamplingMode_MASK (0x400000U) #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV420DownsamplingMode_SHIFT (22U) /*! pixeng_store9_YUV420DownsamplingMode * 0b0..Nearest mode. Discards all odd samples, outputs even samples. * 0b1..Linear interspersed mode. 2 nearest UV samples are combined in linear filter to get one output sample. */ #define DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV420DownsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV420DownsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_CONTROL_pixeng_store9_YUV420DownsamplingMode_MASK) /*! @} */ /*! @name PIXENG_STORE9_START - Store unit start register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_START_pixeng_store9_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9_START_pixeng_store9_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_START_pixeng_store9_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_START_pixeng_store9_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_START_pixeng_store9_Start_MASK) /*! @} */ /*! @name PIXENG_STORE9_WRITEADDRESS - Ring buffer synchronization. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESS_pixeng_store9_WriteAddress_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESS_pixeng_store9_WriteAddress_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESS_pixeng_store9_WriteAddress(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESS_pixeng_store9_WriteAddress_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESS_pixeng_store9_WriteAddress_MASK) /*! @} */ /*! @name PIXENG_STORE9_WRITEADDRESSMSB - Ring buffer synchronization. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESSMSB_pixeng_store9_WriteAddressMSB_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESSMSB_pixeng_store9_WriteAddressMSB_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESSMSB_pixeng_store9_WriteAddressMSB(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESSMSB_pixeng_store9_WriteAddressMSB_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_WRITEADDRESSMSB_pixeng_store9_WriteAddressMSB_MASK) /*! @} */ /*! @name PIXENG_STORE9_FRAMEPROPERTIES - Ring buffer synchronization. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEPROPERTIES_pixeng_store9_FieldId_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEPROPERTIES_pixeng_store9_FieldId_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_FRAMEPROPERTIES_pixeng_store9_FieldId(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_FRAMEPROPERTIES_pixeng_store9_FieldId_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_FRAMEPROPERTIES_pixeng_store9_FieldId_MASK) /*! @} */ /*! @name PIXENG_STORE9_BURSTBUFFERPROPERTIES - Burst Buffer Property register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERPROPERTIES_pixeng_store9_MaxBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERPROPERTIES_pixeng_store9_MaxBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERPROPERTIES_pixeng_store9_MaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERPROPERTIES_pixeng_store9_MaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_BURSTBUFFERPROPERTIES_pixeng_store9_MaxBurstLength_MASK) /*! @} */ /*! @name PIXENG_STORE9_LASTCONTROLWORD - Shows the last control word received */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_LASTCONTROLWORD_pixeng_store9_L_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_LASTCONTROLWORD_pixeng_store9_L_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_LASTCONTROLWORD_pixeng_store9_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_LASTCONTROLWORD_pixeng_store9_L_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_LASTCONTROLWORD_pixeng_store9_L_VAL_MASK) /*! @} */ /*! @name PIXENG_STORE9_PERFCOUNTER - Performance counter result */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_PERFCOUNTER_pixeng_store9_PerfResult_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9_PERFCOUNTER_pixeng_store9_PerfResult_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_PERFCOUNTER_pixeng_store9_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_PERFCOUNTER_pixeng_store9_PerfResult_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_PERFCOUNTER_pixeng_store9_PerfResult_MASK) /*! @} */ /*! @name PIXENG_STORE9_STATUS - Shows status information */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_PixelbusError_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_PixelbusError_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_PixelbusError(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_PixelbusError_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9_STATUS_pixeng_store9_PixelbusError_MASK) /*! @} */ /*! @name PIXENG_STORE9CFG_STORE9_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKUNLOCK_pixeng_store9cfg_store9_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKUNLOCK_pixeng_store9cfg_store9_LockUnlock_SHIFT (0U) /*! pixeng_store9cfg_store9_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKUNLOCK_pixeng_store9cfg_store9_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKUNLOCK_pixeng_store9cfg_store9_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKUNLOCK_pixeng_store9cfg_store9_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_STORE9CFG_STORE9_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_LOCKSTATUS_pixeng_store9cfg_store9_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_STORE9CFG_STORE9_STATIC - Static pixel engine configuration for store9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_powerdown_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_powerdown_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_powerdown(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_powerdown_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_powerdown_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_Sync_Mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_Sync_Mode_SHIFT (8U) /*! pixeng_store9cfg_store9_Sync_Mode * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_Sync_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_Sync_Mode_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_SW_Reset_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_SW_Reset_SHIFT (11U) /*! pixeng_store9cfg_store9_SW_Reset * 0b0..Normal Operation * 0b1..Software Reset */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_SW_Reset_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_SW_Reset_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_div_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_div_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_div(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_div_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATIC_pixeng_store9cfg_store9_div_MASK) /*! @} */ /*! @name PIXENG_STORE9CFG_STORE9_DYNAMIC - Dynamic pixel engine configuration for store9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_DYNAMIC_pixeng_store9cfg_store9_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_DYNAMIC_pixeng_store9cfg_store9_src_sel_SHIFT (0U) /*! pixeng_store9cfg_store9_src_sel * 0b000000..Unit store9 input port src is disabled * 0b000100..Unit store9 input port src is connected to output of unit blitblend9 * 0b000101..Unit store9 input port src is connected to output of unit fetchrot9 * 0b000110..Unit store9 input port src is connected to output of unit fetchdecode9 * 0b001000..Unit store9 input port src is connected to output of unit hscaler9 * 0b001001..Unit store9 input port src is connected to output of unit vscaler9 * 0b001010..Unit store9 input port src is connected to output of unit filter9 */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_DYNAMIC_pixeng_store9cfg_store9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_DYNAMIC_pixeng_store9cfg_store9_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_DYNAMIC_pixeng_store9cfg_store9_src_sel_MASK) /*! @} */ /*! @name PIXENG_STORE9CFG_STORE9_REQUEST - ShadowLoadRequest register for endpoint store9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_sel_ShdLdReq_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_sel_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_sel_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_sel_ShdLdReq_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_ShdLdReq_MASK (0x1FFFEU) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_ShdLdReq_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_REQUEST_pixeng_store9cfg_store9_ShdLdReq_MASK) /*! @} */ /*! @name PIXENG_STORE9CFG_STORE9_TRIGGER - Trigger bits for pixel engine configuration of store9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_Sync_Trigger_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_Sync_Trigger_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_Sync_Trigger_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_Sync_Trigger_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_trigger_sequence_complete_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_trigger_sequence_complete_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_trigger_sequence_complete_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_TRIGGER_pixeng_store9cfg_store9_trigger_sequence_complete_MASK) /*! @} */ /*! @name PIXENG_STORE9CFG_STORE9_STATUS - Status information for pixel engine configuration of store9 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_pipeline_status_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_pipeline_status_SHIFT (0U) /*! pixeng_store9cfg_store9_pipeline_status * 0b00..Pipeline with endpoint store9 is empty * 0b01..Pipeline with endpoint store9 is currently processing one operation * 0b10..Pipeline with endpoint store9 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_pipeline_status_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_pipeline_status_MASK) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_sync_busy_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_sync_busy_SHIFT (8U) /*! pixeng_store9cfg_store9_sync_busy * 0b0..store9 synchronizer is idle * 0b1..store9 synchronizer is busy */ #define DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_sync_busy_SHIFT)) & DISPLAY_SEERIS_PIXENG_STORE9CFG_STORE9_STATUS_pixeng_store9cfg_store9_sync_busy_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0_LockUnlock_SHIFT (0U) /*! pixeng_constframe0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATICCONTROL_pixeng_constframe0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATICCONTROL_pixeng_constframe0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATICCONTROL_pixeng_constframe0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATICCONTROL_pixeng_constframe0_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATICCONTROL_pixeng_constframe0_ShdEn_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_FRAMEDIMENSIONS_pixeng_constframe0_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantBlue_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantGreen_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONSTANTCOLOR_pixeng_constframe0_ConstantRed_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONTROLTRIGGER_pixeng_constframe0_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONTROLTRIGGER_pixeng_constframe0_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONTROLTRIGGER_pixeng_constframe0_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONTROLTRIGGER_pixeng_constframe0_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_CONTROLTRIGGER_pixeng_constframe0_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_START - ConstFrame unit start register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_START_pixeng_constframe0_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_START_pixeng_constframe0_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_START_pixeng_constframe0_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_START_pixeng_constframe0_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_START_pixeng_constframe0_Start_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0_STATUS - Shows status information */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_ShadowStatus_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_ShadowStatus_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_ShadowStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0_STATUS_pixeng_constframe0_ShadowStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0cfg_constframe0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0cfg_constframe0_LockUnlock_SHIFT (0U) /*! pixeng_constframe0cfg_constframe0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0cfg_constframe0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0cfg_constframe0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKUNLOCK_pixeng_constframe0cfg_constframe0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_LOCKSTATUS_pixeng_constframe0cfg_constframe0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME0CFG_CONSTFRAME0_STATUS - Status information for pixel engine configuration of constframe0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_STATUS_pixeng_constframe0cfg_constframe0_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_STATUS_pixeng_constframe0cfg_constframe0_sel_SHIFT (16U) /*! pixeng_constframe0cfg_constframe0_sel * 0b000..constframe0 module is not used * 0b001..constframe0 module is used from store9 processing path * 0b010..constframe0 module is used from extdst0 processing path * 0b011..constframe0 module is used from extdst4 processing path * 0b100..constframe0 module is used from extdst1 processing path * 0b101..constframe0 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_STATUS_pixeng_constframe0cfg_constframe0_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_STATUS_pixeng_constframe0cfg_constframe0_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME0CFG_CONSTFRAME0_STATUS_pixeng_constframe0cfg_constframe0_sel_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4_LockUnlock_SHIFT (0U) /*! pixeng_constframe4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATICCONTROL_pixeng_constframe4_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATICCONTROL_pixeng_constframe4_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATICCONTROL_pixeng_constframe4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATICCONTROL_pixeng_constframe4_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATICCONTROL_pixeng_constframe4_ShdEn_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_FRAMEDIMENSIONS_pixeng_constframe4_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantBlue_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantGreen_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONSTANTCOLOR_pixeng_constframe4_ConstantRed_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONTROLTRIGGER_pixeng_constframe4_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONTROLTRIGGER_pixeng_constframe4_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONTROLTRIGGER_pixeng_constframe4_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONTROLTRIGGER_pixeng_constframe4_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_CONTROLTRIGGER_pixeng_constframe4_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_START - ConstFrame unit start register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_START_pixeng_constframe4_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_START_pixeng_constframe4_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_START_pixeng_constframe4_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_START_pixeng_constframe4_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_START_pixeng_constframe4_Start_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4_STATUS - Shows status information */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_ShadowStatus_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_ShadowStatus_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_ShadowStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4_STATUS_pixeng_constframe4_ShadowStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4cfg_constframe4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4cfg_constframe4_LockUnlock_SHIFT (0U) /*! pixeng_constframe4cfg_constframe4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4cfg_constframe4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4cfg_constframe4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKUNLOCK_pixeng_constframe4cfg_constframe4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_LOCKSTATUS_pixeng_constframe4cfg_constframe4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME4CFG_CONSTFRAME4_STATUS - Status information for pixel engine configuration of constframe4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_STATUS_pixeng_constframe4cfg_constframe4_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_STATUS_pixeng_constframe4cfg_constframe4_sel_SHIFT (16U) /*! pixeng_constframe4cfg_constframe4_sel * 0b000..constframe4 module is not used * 0b001..constframe4 module is used from store9 processing path * 0b010..constframe4 module is used from extdst0 processing path * 0b011..constframe4 module is used from extdst4 processing path * 0b100..constframe4 module is used from extdst1 processing path * 0b101..constframe4 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_STATUS_pixeng_constframe4cfg_constframe4_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_STATUS_pixeng_constframe4cfg_constframe4_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME4CFG_CONSTFRAME4_STATUS_pixeng_constframe4cfg_constframe4_sel_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKUNLOCK_pixeng_extdst0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKUNLOCK_pixeng_extdst0_LockUnlock_SHIFT (0U) /*! pixeng_extdst0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKUNLOCK_pixeng_extdst0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKUNLOCK_pixeng_extdst0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKUNLOCK_pixeng_extdst0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_LOCKSTATUS_pixeng_extdst0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_STATICCONTROL - External Destination static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_KICK_MODE_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_KICK_MODE_SHIFT (8U) /*! pixeng_extdst0_KICK_MODE * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_KICK_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_KICK_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_PerfCountMode_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_PerfCountMode_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_PerfCountMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_STATICCONTROL_pixeng_extdst0_PerfCountMode_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_CONTROL - External Destination shadowed control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROL_pixeng_extdst0_GammaApplyEnable_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROL_pixeng_extdst0_GammaApplyEnable_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROL_pixeng_extdst0_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROL_pixeng_extdst0_GammaApplyEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROL_pixeng_extdst0_GammaApplyEnable_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_SOFTWAREKICK_pixeng_extdst0_KICK_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_SOFTWAREKICK_pixeng_extdst0_KICK_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_SOFTWAREKICK_pixeng_extdst0_KICK(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_SOFTWAREKICK_pixeng_extdst0_KICK_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_SOFTWAREKICK_pixeng_extdst0_KICK_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_STATUS - External Destination Unit current status */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATUS_pixeng_extdst0_CNT_ERR_STS_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATUS_pixeng_extdst0_CNT_ERR_STS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_STATUS_pixeng_extdst0_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_STATUS_pixeng_extdst0_CNT_ERR_STS_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_STATUS_pixeng_extdst0_CNT_ERR_STS_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_CONTROLWORD - Value of last received control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROLWORD_pixeng_extdst0_CW_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROLWORD_pixeng_extdst0_CW_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROLWORD_pixeng_extdst0_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROLWORD_pixeng_extdst0_CW_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_CONTROLWORD_pixeng_extdst0_CW_VAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_CURPIXELCNT_pixeng_extdst0_C_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_LASTPIXELCNT_pixeng_extdst0_L_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST0_PERFCOUNTER - Performance counter result */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0_PERFCOUNTER_pixeng_extdst0_PerfResult_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST0_PERFCOUNTER_pixeng_extdst0_PerfResult_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0_PERFCOUNTER_pixeng_extdst0_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0_PERFCOUNTER_pixeng_extdst0_PerfResult_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0_PERFCOUNTER_pixeng_extdst0_PerfResult_MASK) /*! @} */ /*! @name PIXENG_EXTDST0CFG_EXTDST0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKUNLOCK_pixeng_extdst0cfg_extdst0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKUNLOCK_pixeng_extdst0cfg_extdst0_LockUnlock_SHIFT (0U) /*! pixeng_extdst0cfg_extdst0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKUNLOCK_pixeng_extdst0cfg_extdst0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKUNLOCK_pixeng_extdst0cfg_extdst0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKUNLOCK_pixeng_extdst0cfg_extdst0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_LOCKSTATUS_pixeng_extdst0cfg_extdst0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST0CFG_EXTDST0_STATIC - Static pixel engine configuration for extdst0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_powerdown_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_powerdown_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_powerdown(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_powerdown_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_powerdown_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_Sync_Mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_Sync_Mode_SHIFT (8U) /*! pixeng_extdst0cfg_extdst0_Sync_Mode * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_Sync_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_Sync_Mode_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_SW_Reset_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_SW_Reset_SHIFT (11U) /*! pixeng_extdst0cfg_extdst0_SW_Reset * 0b0..Normal Operation * 0b1..Software Reset */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_SW_Reset_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_SW_Reset_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_div_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_div_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_div(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_div_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATIC_pixeng_extdst0cfg_extdst0_div_MASK) /*! @} */ /*! @name PIXENG_EXTDST0CFG_EXTDST0_DYNAMIC - Dynamic pixel engine configuration for extdst0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_DYNAMIC_pixeng_extdst0cfg_extdst0_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_DYNAMIC_pixeng_extdst0cfg_extdst0_src_sel_SHIFT (0U) /*! pixeng_extdst0cfg_extdst0_src_sel * 0b000000..Unit extdst0 input port src is disabled * 0b010100..Unit extdst0 input port src is connected to output of unit layerblend1 * 0b010101..Unit extdst0 input port src is connected to output of unit layerblend2 * 0b010110..Unit extdst0 input port src is connected to output of unit layerblend3 * 0b010111..Unit extdst0 input port src is connected to output of unit layerblend4 * 0b011000..Unit extdst0 input port src is connected to output of unit layerblend5 * 0b011001..Unit extdst0 input port src is connected to output of unit layerblend6 */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_DYNAMIC_pixeng_extdst0cfg_extdst0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_DYNAMIC_pixeng_extdst0cfg_extdst0_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_DYNAMIC_pixeng_extdst0cfg_extdst0_src_sel_MASK) /*! @} */ /*! @name PIXENG_EXTDST0CFG_EXTDST0_REQUEST - ShadowLoadRequest register for endpoint extdst0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_sel_ShdLdReq_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_sel_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_sel_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_sel_ShdLdReq_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_ShdLdReq_MASK (0x1FFFEU) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_ShdLdReq_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_REQUEST_pixeng_extdst0cfg_extdst0_ShdLdReq_MASK) /*! @} */ /*! @name PIXENG_EXTDST0CFG_EXTDST0_TRIGGER - Trigger bits for pixel engine configuration of extdst0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_Sync_Trigger_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_Sync_Trigger_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_Sync_Trigger_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_Sync_Trigger_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_trigger_sequence_complete_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_trigger_sequence_complete_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_trigger_sequence_complete_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_TRIGGER_pixeng_extdst0cfg_extdst0_trigger_sequence_complete_MASK) /*! @} */ /*! @name PIXENG_EXTDST0CFG_EXTDST0_STATUS - Status information for pixel engine configuration of extdst0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_pipeline_status_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_pipeline_status_SHIFT (0U) /*! pixeng_extdst0cfg_extdst0_pipeline_status * 0b00..Pipeline with endpoint extdst0 is empty * 0b01..Pipeline with endpoint extdst0 is currently processing one operation * 0b10..Pipeline with endpoint extdst0 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_pipeline_status_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_pipeline_status_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_sync_busy_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_sync_busy_SHIFT (8U) /*! pixeng_extdst0cfg_extdst0_sync_busy * 0b0..extdst0 synchronizer is idle * 0b1..extdst0 synchronizer is busy */ #define DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_sync_busy_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST0CFG_EXTDST0_STATUS_pixeng_extdst0cfg_extdst0_sync_busy_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKUNLOCK_pixeng_extdst4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKUNLOCK_pixeng_extdst4_LockUnlock_SHIFT (0U) /*! pixeng_extdst4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKUNLOCK_pixeng_extdst4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKUNLOCK_pixeng_extdst4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKUNLOCK_pixeng_extdst4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_LOCKSTATUS_pixeng_extdst4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_STATICCONTROL - External Destination static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_KICK_MODE_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_KICK_MODE_SHIFT (8U) /*! pixeng_extdst4_KICK_MODE * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_KICK_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_KICK_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_PerfCountMode_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_PerfCountMode_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_PerfCountMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_STATICCONTROL_pixeng_extdst4_PerfCountMode_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_CONTROL - External Destination shadowed control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROL_pixeng_extdst4_GammaApplyEnable_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROL_pixeng_extdst4_GammaApplyEnable_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROL_pixeng_extdst4_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROL_pixeng_extdst4_GammaApplyEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROL_pixeng_extdst4_GammaApplyEnable_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_SOFTWAREKICK_pixeng_extdst4_KICK_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_SOFTWAREKICK_pixeng_extdst4_KICK_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_SOFTWAREKICK_pixeng_extdst4_KICK(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_SOFTWAREKICK_pixeng_extdst4_KICK_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_SOFTWAREKICK_pixeng_extdst4_KICK_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_STATUS - External Destination Unit current status */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATUS_pixeng_extdst4_CNT_ERR_STS_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATUS_pixeng_extdst4_CNT_ERR_STS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_STATUS_pixeng_extdst4_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_STATUS_pixeng_extdst4_CNT_ERR_STS_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_STATUS_pixeng_extdst4_CNT_ERR_STS_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_CONTROLWORD - Value of last received control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROLWORD_pixeng_extdst4_CW_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROLWORD_pixeng_extdst4_CW_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROLWORD_pixeng_extdst4_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROLWORD_pixeng_extdst4_CW_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_CONTROLWORD_pixeng_extdst4_CW_VAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_CURPIXELCNT_pixeng_extdst4_C_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_LASTPIXELCNT_pixeng_extdst4_L_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST4_PERFCOUNTER - Performance counter result */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4_PERFCOUNTER_pixeng_extdst4_PerfResult_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST4_PERFCOUNTER_pixeng_extdst4_PerfResult_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4_PERFCOUNTER_pixeng_extdst4_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4_PERFCOUNTER_pixeng_extdst4_PerfResult_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4_PERFCOUNTER_pixeng_extdst4_PerfResult_MASK) /*! @} */ /*! @name PIXENG_EXTDST4CFG_EXTDST4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKUNLOCK_pixeng_extdst4cfg_extdst4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKUNLOCK_pixeng_extdst4cfg_extdst4_LockUnlock_SHIFT (0U) /*! pixeng_extdst4cfg_extdst4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKUNLOCK_pixeng_extdst4cfg_extdst4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKUNLOCK_pixeng_extdst4cfg_extdst4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKUNLOCK_pixeng_extdst4cfg_extdst4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_LOCKSTATUS_pixeng_extdst4cfg_extdst4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST4CFG_EXTDST4_STATIC - Static pixel engine configuration for extdst4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_powerdown_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_powerdown_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_powerdown(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_powerdown_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_powerdown_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_Sync_Mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_Sync_Mode_SHIFT (8U) /*! pixeng_extdst4cfg_extdst4_Sync_Mode * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_Sync_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_Sync_Mode_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_SW_Reset_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_SW_Reset_SHIFT (11U) /*! pixeng_extdst4cfg_extdst4_SW_Reset * 0b0..Normal Operation * 0b1..Software Reset */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_SW_Reset_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_SW_Reset_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_div_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_div_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_div(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_div_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATIC_pixeng_extdst4cfg_extdst4_div_MASK) /*! @} */ /*! @name PIXENG_EXTDST4CFG_EXTDST4_DYNAMIC - Dynamic pixel engine configuration for extdst4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_DYNAMIC_pixeng_extdst4cfg_extdst4_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_DYNAMIC_pixeng_extdst4cfg_extdst4_src_sel_SHIFT (0U) /*! pixeng_extdst4cfg_extdst4_src_sel * 0b000000..Unit extdst4 input port src is disabled * 0b010100..Unit extdst4 input port src is connected to output of unit layerblend1 * 0b010101..Unit extdst4 input port src is connected to output of unit layerblend2 * 0b010110..Unit extdst4 input port src is connected to output of unit layerblend3 * 0b010111..Unit extdst4 input port src is connected to output of unit layerblend4 * 0b011000..Unit extdst4 input port src is connected to output of unit layerblend5 * 0b011001..Unit extdst4 input port src is connected to output of unit layerblend6 */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_DYNAMIC_pixeng_extdst4cfg_extdst4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_DYNAMIC_pixeng_extdst4cfg_extdst4_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_DYNAMIC_pixeng_extdst4cfg_extdst4_src_sel_MASK) /*! @} */ /*! @name PIXENG_EXTDST4CFG_EXTDST4_REQUEST - ShadowLoadRequest register for endpoint extdst4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_sel_ShdLdReq_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_sel_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_sel_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_sel_ShdLdReq_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_ShdLdReq_MASK (0x1FFFEU) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_ShdLdReq_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_REQUEST_pixeng_extdst4cfg_extdst4_ShdLdReq_MASK) /*! @} */ /*! @name PIXENG_EXTDST4CFG_EXTDST4_TRIGGER - Trigger bits for pixel engine configuration of extdst4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_Sync_Trigger_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_Sync_Trigger_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_Sync_Trigger_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_Sync_Trigger_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_trigger_sequence_complete_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_trigger_sequence_complete_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_trigger_sequence_complete_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_TRIGGER_pixeng_extdst4cfg_extdst4_trigger_sequence_complete_MASK) /*! @} */ /*! @name PIXENG_EXTDST4CFG_EXTDST4_STATUS - Status information for pixel engine configuration of extdst4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_pipeline_status_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_pipeline_status_SHIFT (0U) /*! pixeng_extdst4cfg_extdst4_pipeline_status * 0b00..Pipeline with endpoint extdst4 is empty * 0b01..Pipeline with endpoint extdst4 is currently processing one operation * 0b10..Pipeline with endpoint extdst4 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_pipeline_status_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_pipeline_status_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_sync_busy_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_sync_busy_SHIFT (8U) /*! pixeng_extdst4cfg_extdst4_sync_busy * 0b0..extdst4 synchronizer is idle * 0b1..extdst4 synchronizer is busy */ #define DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_sync_busy_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST4CFG_EXTDST4_STATUS_pixeng_extdst4cfg_extdst4_sync_busy_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1_LockUnlock_SHIFT (0U) /*! pixeng_constframe1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATICCONTROL_pixeng_constframe1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATICCONTROL_pixeng_constframe1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATICCONTROL_pixeng_constframe1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATICCONTROL_pixeng_constframe1_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATICCONTROL_pixeng_constframe1_ShdEn_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_FRAMEDIMENSIONS_pixeng_constframe1_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantBlue_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantGreen_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONSTANTCOLOR_pixeng_constframe1_ConstantRed_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONTROLTRIGGER_pixeng_constframe1_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONTROLTRIGGER_pixeng_constframe1_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONTROLTRIGGER_pixeng_constframe1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONTROLTRIGGER_pixeng_constframe1_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_CONTROLTRIGGER_pixeng_constframe1_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_START - ConstFrame unit start register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_START_pixeng_constframe1_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_START_pixeng_constframe1_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_START_pixeng_constframe1_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_START_pixeng_constframe1_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_START_pixeng_constframe1_Start_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1_STATUS - Shows status information */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_ShadowStatus_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_ShadowStatus_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_ShadowStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1_STATUS_pixeng_constframe1_ShadowStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1cfg_constframe1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1cfg_constframe1_LockUnlock_SHIFT (0U) /*! pixeng_constframe1cfg_constframe1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1cfg_constframe1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1cfg_constframe1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKUNLOCK_pixeng_constframe1cfg_constframe1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_LOCKSTATUS_pixeng_constframe1cfg_constframe1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME1CFG_CONSTFRAME1_STATUS - Status information for pixel engine configuration of constframe1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_STATUS_pixeng_constframe1cfg_constframe1_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_STATUS_pixeng_constframe1cfg_constframe1_sel_SHIFT (16U) /*! pixeng_constframe1cfg_constframe1_sel * 0b000..constframe1 module is not used * 0b001..constframe1 module is used from store9 processing path * 0b010..constframe1 module is used from extdst0 processing path * 0b011..constframe1 module is used from extdst4 processing path * 0b100..constframe1 module is used from extdst1 processing path * 0b101..constframe1 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_STATUS_pixeng_constframe1cfg_constframe1_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_STATUS_pixeng_constframe1cfg_constframe1_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME1CFG_CONSTFRAME1_STATUS_pixeng_constframe1cfg_constframe1_sel_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5_LockUnlock_SHIFT (0U) /*! pixeng_constframe5_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_STATICCONTROL - ConstFrame unit static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATICCONTROL_pixeng_constframe5_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATICCONTROL_pixeng_constframe5_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATICCONTROL_pixeng_constframe5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATICCONTROL_pixeng_constframe5_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATICCONTROL_pixeng_constframe5_ShdEn_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_FRAMEDIMENSIONS - Output frame dimensions. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_FRAMEDIMENSIONS_pixeng_constframe5_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_CONSTANTCOLOR - Color of output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantAlpha_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantAlpha_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantBlue_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantBlue_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantBlue_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantGreen_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantGreen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantGreen_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantRed_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantRed_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONSTANTCOLOR_pixeng_constframe5_ConstantRed_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_CONTROLTRIGGER - ConstFrame unit trigger register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONTROLTRIGGER_pixeng_constframe5_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONTROLTRIGGER_pixeng_constframe5_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONTROLTRIGGER_pixeng_constframe5_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONTROLTRIGGER_pixeng_constframe5_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_CONTROLTRIGGER_pixeng_constframe5_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_START - ConstFrame unit start register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_START_pixeng_constframe5_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_START_pixeng_constframe5_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_START_pixeng_constframe5_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_START_pixeng_constframe5_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_START_pixeng_constframe5_Start_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5_STATUS - Shows status information */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_ShadowStatus_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_ShadowStatus_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_ShadowStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5_STATUS_pixeng_constframe5_ShadowStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5cfg_constframe5_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5cfg_constframe5_LockUnlock_SHIFT (0U) /*! pixeng_constframe5cfg_constframe5_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5cfg_constframe5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5cfg_constframe5_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKUNLOCK_pixeng_constframe5cfg_constframe5_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_LOCKSTATUS_pixeng_constframe5cfg_constframe5_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_CONSTFRAME5CFG_CONSTFRAME5_STATUS - Status information for pixel engine configuration of constframe5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_STATUS_pixeng_constframe5cfg_constframe5_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_STATUS_pixeng_constframe5cfg_constframe5_sel_SHIFT (16U) /*! pixeng_constframe5cfg_constframe5_sel * 0b000..constframe5 module is not used * 0b001..constframe5 module is used from store9 processing path * 0b010..constframe5 module is used from extdst0 processing path * 0b011..constframe5 module is used from extdst4 processing path * 0b100..constframe5 module is used from extdst1 processing path * 0b101..constframe5 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_STATUS_pixeng_constframe5cfg_constframe5_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_STATUS_pixeng_constframe5cfg_constframe5_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_CONSTFRAME5CFG_CONSTFRAME5_STATUS_pixeng_constframe5cfg_constframe5_sel_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKUNLOCK_pixeng_extdst1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKUNLOCK_pixeng_extdst1_LockUnlock_SHIFT (0U) /*! pixeng_extdst1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKUNLOCK_pixeng_extdst1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKUNLOCK_pixeng_extdst1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKUNLOCK_pixeng_extdst1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_LOCKSTATUS_pixeng_extdst1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_STATICCONTROL - External Destination static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_KICK_MODE_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_KICK_MODE_SHIFT (8U) /*! pixeng_extdst1_KICK_MODE * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_KICK_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_KICK_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_PerfCountMode_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_PerfCountMode_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_PerfCountMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_STATICCONTROL_pixeng_extdst1_PerfCountMode_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_CONTROL - External Destination shadowed control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROL_pixeng_extdst1_GammaApplyEnable_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROL_pixeng_extdst1_GammaApplyEnable_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROL_pixeng_extdst1_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROL_pixeng_extdst1_GammaApplyEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROL_pixeng_extdst1_GammaApplyEnable_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_SOFTWAREKICK_pixeng_extdst1_KICK_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_SOFTWAREKICK_pixeng_extdst1_KICK_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_SOFTWAREKICK_pixeng_extdst1_KICK(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_SOFTWAREKICK_pixeng_extdst1_KICK_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_SOFTWAREKICK_pixeng_extdst1_KICK_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_STATUS - External Destination Unit current status */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATUS_pixeng_extdst1_CNT_ERR_STS_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATUS_pixeng_extdst1_CNT_ERR_STS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_STATUS_pixeng_extdst1_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_STATUS_pixeng_extdst1_CNT_ERR_STS_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_STATUS_pixeng_extdst1_CNT_ERR_STS_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_CONTROLWORD - Value of last received control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROLWORD_pixeng_extdst1_CW_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROLWORD_pixeng_extdst1_CW_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROLWORD_pixeng_extdst1_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROLWORD_pixeng_extdst1_CW_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_CONTROLWORD_pixeng_extdst1_CW_VAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_CURPIXELCNT_pixeng_extdst1_C_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_LASTPIXELCNT_pixeng_extdst1_L_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST1_PERFCOUNTER - Performance counter result */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1_PERFCOUNTER_pixeng_extdst1_PerfResult_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST1_PERFCOUNTER_pixeng_extdst1_PerfResult_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1_PERFCOUNTER_pixeng_extdst1_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1_PERFCOUNTER_pixeng_extdst1_PerfResult_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1_PERFCOUNTER_pixeng_extdst1_PerfResult_MASK) /*! @} */ /*! @name PIXENG_EXTDST1CFG_EXTDST1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKUNLOCK_pixeng_extdst1cfg_extdst1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKUNLOCK_pixeng_extdst1cfg_extdst1_LockUnlock_SHIFT (0U) /*! pixeng_extdst1cfg_extdst1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKUNLOCK_pixeng_extdst1cfg_extdst1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKUNLOCK_pixeng_extdst1cfg_extdst1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKUNLOCK_pixeng_extdst1cfg_extdst1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_LOCKSTATUS_pixeng_extdst1cfg_extdst1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST1CFG_EXTDST1_STATIC - Static pixel engine configuration for extdst1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_powerdown_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_powerdown_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_powerdown(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_powerdown_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_powerdown_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_Sync_Mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_Sync_Mode_SHIFT (8U) /*! pixeng_extdst1cfg_extdst1_Sync_Mode * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_Sync_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_Sync_Mode_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_SW_Reset_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_SW_Reset_SHIFT (11U) /*! pixeng_extdst1cfg_extdst1_SW_Reset * 0b0..Normal Operation * 0b1..Software Reset */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_SW_Reset_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_SW_Reset_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_div_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_div_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_div(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_div_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATIC_pixeng_extdst1cfg_extdst1_div_MASK) /*! @} */ /*! @name PIXENG_EXTDST1CFG_EXTDST1_DYNAMIC - Dynamic pixel engine configuration for extdst1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_DYNAMIC_pixeng_extdst1cfg_extdst1_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_DYNAMIC_pixeng_extdst1cfg_extdst1_src_sel_SHIFT (0U) /*! pixeng_extdst1cfg_extdst1_src_sel * 0b000000..Unit extdst1 input port src is disabled * 0b010100..Unit extdst1 input port src is connected to output of unit layerblend1 * 0b010101..Unit extdst1 input port src is connected to output of unit layerblend2 * 0b010110..Unit extdst1 input port src is connected to output of unit layerblend3 * 0b010111..Unit extdst1 input port src is connected to output of unit layerblend4 * 0b011000..Unit extdst1 input port src is connected to output of unit layerblend5 * 0b011001..Unit extdst1 input port src is connected to output of unit layerblend6 */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_DYNAMIC_pixeng_extdst1cfg_extdst1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_DYNAMIC_pixeng_extdst1cfg_extdst1_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_DYNAMIC_pixeng_extdst1cfg_extdst1_src_sel_MASK) /*! @} */ /*! @name PIXENG_EXTDST1CFG_EXTDST1_REQUEST - ShadowLoadRequest register for endpoint extdst1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_sel_ShdLdReq_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_sel_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_sel_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_sel_ShdLdReq_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_ShdLdReq_MASK (0x1FFFEU) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_ShdLdReq_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_REQUEST_pixeng_extdst1cfg_extdst1_ShdLdReq_MASK) /*! @} */ /*! @name PIXENG_EXTDST1CFG_EXTDST1_TRIGGER - Trigger bits for pixel engine configuration of extdst1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_Sync_Trigger_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_Sync_Trigger_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_Sync_Trigger_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_Sync_Trigger_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_trigger_sequence_complete_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_trigger_sequence_complete_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_trigger_sequence_complete_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_TRIGGER_pixeng_extdst1cfg_extdst1_trigger_sequence_complete_MASK) /*! @} */ /*! @name PIXENG_EXTDST1CFG_EXTDST1_STATUS - Status information for pixel engine configuration of extdst1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_pipeline_status_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_pipeline_status_SHIFT (0U) /*! pixeng_extdst1cfg_extdst1_pipeline_status * 0b00..Pipeline with endpoint extdst1 is empty * 0b01..Pipeline with endpoint extdst1 is currently processing one operation * 0b10..Pipeline with endpoint extdst1 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_pipeline_status_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_pipeline_status_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_sync_busy_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_sync_busy_SHIFT (8U) /*! pixeng_extdst1cfg_extdst1_sync_busy * 0b0..extdst1 synchronizer is idle * 0b1..extdst1 synchronizer is busy */ #define DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_sync_busy_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST1CFG_EXTDST1_STATUS_pixeng_extdst1cfg_extdst1_sync_busy_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKUNLOCK_pixeng_extdst5_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKUNLOCK_pixeng_extdst5_LockUnlock_SHIFT (0U) /*! pixeng_extdst5_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKUNLOCK_pixeng_extdst5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKUNLOCK_pixeng_extdst5_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKUNLOCK_pixeng_extdst5_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_LOCKSTATUS_pixeng_extdst5_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_STATICCONTROL - External Destination static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_KICK_MODE_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_KICK_MODE_SHIFT (8U) /*! pixeng_extdst5_KICK_MODE * 0b0..kick generation by KICK field only * 0b1..kick signal from external allowed */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_KICK_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_KICK_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_PerfCountMode_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_PerfCountMode_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_PerfCountMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_STATICCONTROL_pixeng_extdst5_PerfCountMode_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_CONTROL - External Destination shadowed control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROL_pixeng_extdst5_GammaApplyEnable_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROL_pixeng_extdst5_GammaApplyEnable_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROL_pixeng_extdst5_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROL_pixeng_extdst5_GammaApplyEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROL_pixeng_extdst5_GammaApplyEnable_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_SOFTWAREKICK - External Destination software kick */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_SOFTWAREKICK_pixeng_extdst5_KICK_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_SOFTWAREKICK_pixeng_extdst5_KICK_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_SOFTWAREKICK_pixeng_extdst5_KICK(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_SOFTWAREKICK_pixeng_extdst5_KICK_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_SOFTWAREKICK_pixeng_extdst5_KICK_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_STATUS - External Destination Unit current status */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATUS_pixeng_extdst5_CNT_ERR_STS_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATUS_pixeng_extdst5_CNT_ERR_STS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_STATUS_pixeng_extdst5_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_STATUS_pixeng_extdst5_CNT_ERR_STS_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_STATUS_pixeng_extdst5_CNT_ERR_STS_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_CONTROLWORD - Value of last received control word */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROLWORD_pixeng_extdst5_CW_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROLWORD_pixeng_extdst5_CW_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROLWORD_pixeng_extdst5_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROLWORD_pixeng_extdst5_CW_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_CONTROLWORD_pixeng_extdst5_CW_VAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_CURPIXELCNT - pixel count of currently running frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_CURPIXELCNT_pixeng_extdst5_C_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_LASTPIXELCNT - pixel count between last two control words */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_XVAL_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_XVAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_XVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_XVAL_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_YVAL_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_YVAL_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_YVAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_LASTPIXELCNT_pixeng_extdst5_L_YVAL_MASK) /*! @} */ /*! @name PIXENG_EXTDST5_PERFCOUNTER - Performance counter result */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5_PERFCOUNTER_pixeng_extdst5_PerfResult_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST5_PERFCOUNTER_pixeng_extdst5_PerfResult_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5_PERFCOUNTER_pixeng_extdst5_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5_PERFCOUNTER_pixeng_extdst5_PerfResult_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5_PERFCOUNTER_pixeng_extdst5_PerfResult_MASK) /*! @} */ /*! @name PIXENG_EXTDST5CFG_EXTDST5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKUNLOCK_pixeng_extdst5cfg_extdst5_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKUNLOCK_pixeng_extdst5cfg_extdst5_LockUnlock_SHIFT (0U) /*! pixeng_extdst5cfg_extdst5_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKUNLOCK_pixeng_extdst5cfg_extdst5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKUNLOCK_pixeng_extdst5cfg_extdst5_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKUNLOCK_pixeng_extdst5cfg_extdst5_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_LOCKSTATUS_pixeng_extdst5cfg_extdst5_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_EXTDST5CFG_EXTDST5_STATIC - Static pixel engine configuration for extdst5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_powerdown_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_powerdown_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_powerdown(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_powerdown_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_powerdown_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_Sync_Mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_Sync_Mode_SHIFT (8U) /*! pixeng_extdst5cfg_extdst5_Sync_Mode * 0b0..Reconfig pipeline after explicit trigger * 0b1..Reconfig pipeline after every kick when idle */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_Sync_Mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_Sync_Mode_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_SW_Reset_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_SW_Reset_SHIFT (11U) /*! pixeng_extdst5cfg_extdst5_SW_Reset * 0b0..Normal Operation * 0b1..Software Reset */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_SW_Reset_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_SW_Reset_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_div_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_div_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_div(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_div_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATIC_pixeng_extdst5cfg_extdst5_div_MASK) /*! @} */ /*! @name PIXENG_EXTDST5CFG_EXTDST5_DYNAMIC - Dynamic pixel engine configuration for extdst5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_DYNAMIC_pixeng_extdst5cfg_extdst5_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_DYNAMIC_pixeng_extdst5cfg_extdst5_src_sel_SHIFT (0U) /*! pixeng_extdst5cfg_extdst5_src_sel * 0b000000..Unit extdst5 input port src is disabled * 0b010100..Unit extdst5 input port src is connected to output of unit layerblend1 * 0b010101..Unit extdst5 input port src is connected to output of unit layerblend2 * 0b010110..Unit extdst5 input port src is connected to output of unit layerblend3 * 0b010111..Unit extdst5 input port src is connected to output of unit layerblend4 * 0b011000..Unit extdst5 input port src is connected to output of unit layerblend5 * 0b011001..Unit extdst5 input port src is connected to output of unit layerblend6 */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_DYNAMIC_pixeng_extdst5cfg_extdst5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_DYNAMIC_pixeng_extdst5cfg_extdst5_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_DYNAMIC_pixeng_extdst5cfg_extdst5_src_sel_MASK) /*! @} */ /*! @name PIXENG_EXTDST5CFG_EXTDST5_REQUEST - ShadowLoadRequest register for endpoint extdst5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_sel_ShdLdReq_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_sel_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_sel_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_sel_ShdLdReq_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_ShdLdReq_MASK (0x1FFFEU) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_ShdLdReq_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_REQUEST_pixeng_extdst5cfg_extdst5_ShdLdReq_MASK) /*! @} */ /*! @name PIXENG_EXTDST5CFG_EXTDST5_TRIGGER - Trigger bits for pixel engine configuration of extdst5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_Sync_Trigger_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_Sync_Trigger_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_Sync_Trigger_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_Sync_Trigger_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_trigger_sequence_complete_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_trigger_sequence_complete_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_trigger_sequence_complete_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_TRIGGER_pixeng_extdst5cfg_extdst5_trigger_sequence_complete_MASK) /*! @} */ /*! @name PIXENG_EXTDST5CFG_EXTDST5_STATUS - Status information for pixel engine configuration of extdst5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_pipeline_status_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_pipeline_status_SHIFT (0U) /*! pixeng_extdst5cfg_extdst5_pipeline_status * 0b00..Pipeline with endpoint extdst5 is empty * 0b01..Pipeline with endpoint extdst5 is currently processing one operation * 0b10..Pipeline with endpoint extdst5 is currently processing one operation with a second one already kicked to be processed afterwards * 0b11..reserved */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_pipeline_status_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_pipeline_status_MASK) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_sync_busy_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_sync_busy_SHIFT (8U) /*! pixeng_extdst5cfg_extdst5_sync_busy * 0b0..extdst5 synchronizer is idle * 0b1..extdst5 synchronizer is busy */ #define DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_sync_busy_SHIFT)) & DISPLAY_SEERIS_PIXENG_EXTDST5CFG_EXTDST5_STATUS_pixeng_extdst5cfg_extdst5_sync_busy_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1_LockUnlock_SHIFT (0U) /*! pixeng_layerblend1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdLdSel_MASK (0x6U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdLdSel_SHIFT (1U) /*! pixeng_layerblend1_ShdLdSel * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdLdSel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdTokSel_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdTokSel_SHIFT (3U) /*! pixeng_layerblend1_ShdTokSel * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_STATICCONTROL_pixeng_layerblend1_ShdTokSel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_CONTROL - Common control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_MODE_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_MODE_SHIFT (0U) /*! pixeng_layerblend1_MODE * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskEnable_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskEnable_SHIFT (2U) /*! pixeng_layerblend1_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskMode_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskMode_SHIFT (4U) /*! pixeng_layerblend1_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_AlphaMaskMode_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecLowPassEn_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecLowPassEn_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecLowPassEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecLowPassEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecReplicateEn_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecReplicateEn_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecReplicateEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecReplicateEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowEvenColDis_MASK (0x3C00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowEvenColDis_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowOddColDis_MASK (0x3C000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowOddColDis_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecEvenRowOddColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowEvenColDis_MASK (0x3C0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowEvenColDis_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowOddColDis_MASK (0x3C00000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowOddColDis_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_CONTROL_pixeng_layerblend1_SecOddRowOddColDis_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_C_BLD_FUNC_SHIFT (0U) /*! pixeng_layerblend1_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_C_BLD_FUNC_SHIFT (4U) /*! pixeng_layerblend1_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_A_BLD_FUNC_SHIFT (8U) /*! pixeng_layerblend1_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_A_BLD_FUNC_SHIFT (12U) /*! pixeng_layerblend1_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_BLENDCONTROL_pixeng_layerblend1_BlendAlpha_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_XPOS_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_XPOS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_XPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_XPOS_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_YPOS_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_YPOS_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_YPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_POSITION_pixeng_layerblend1_YPOS_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_PRIMCONTROLWORD_pixeng_layerblend1_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_PRIMCONTROLWORD_pixeng_layerblend1_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_PRIMCONTROLWORD_pixeng_layerblend1_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_PRIMCONTROLWORD_pixeng_layerblend1_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_PRIMCONTROLWORD_pixeng_layerblend1_P_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_SECCONTROLWORD_pixeng_layerblend1_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_SECCONTROLWORD_pixeng_layerblend1_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1_SECCONTROLWORD_pixeng_layerblend1_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1_SECCONTROLWORD_pixeng_layerblend1_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1_SECCONTROLWORD_pixeng_layerblend1_S_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1cfg_layerblend1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1cfg_layerblend1_LockUnlock_SHIFT (0U) /*! pixeng_layerblend1cfg_layerblend1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1cfg_layerblend1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1cfg_layerblend1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKUNLOCK_pixeng_layerblend1cfg_layerblend1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_LOCKSTATUS_pixeng_layerblend1cfg_layerblend1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC - Dynamic pixel engine configuration for layerblend1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_prim_sel_SHIFT (0U) /*! pixeng_layerblend1cfg_layerblend1_prim_sel * 0b000000..Unit layerblend1 input port prim is disabled * 0b001100..Unit layerblend1 input port prim is connected to output of unit constframe0 * 0b001101..Unit layerblend1 input port prim is connected to output of unit constframe4 * 0b010000..Unit layerblend1 input port prim is connected to output of unit constframe1 * 0b010001..Unit layerblend1 input port prim is connected to output of unit constframe5 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_sec_sel_SHIFT (8U) /*! pixeng_layerblend1cfg_layerblend1_sec_sel * 0b000000..Unit layerblend1 input port sec is disabled * 0b000101..Unit layerblend1 input port sec is connected to output of unit fetchrot9 * 0b011010..Unit layerblend1 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend1 input port sec is connected to output of unit fetchlayer1 * 0b011100..Unit layerblend1 input port sec is connected to output of unit fetchyuv3 * 0b011101..Unit layerblend1 input port sec is connected to output of unit fetchyuv0 * 0b011111..Unit layerblend1 input port sec is connected to output of unit fetchyuv1 * 0b100001..Unit layerblend1 input port sec is connected to output of unit fetchyuv2 * 0b100011..Unit layerblend1 input port sec is connected to output of unit matrix4 * 0b100100..Unit layerblend1 input port sec is connected to output of unit hscaler4 * 0b100101..Unit layerblend1 input port sec is connected to output of unit vscaler4 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_clken_SHIFT (24U) /*! pixeng_layerblend1cfg_layerblend1_clken * 0b00..Clock for layerblend1 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend1 is without gating */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_DYNAMIC_pixeng_layerblend1cfg_layerblend1_clken_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND1CFG_LAYERBLEND1_STATUS - Status information for pixel engine configuration of layerblend1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_STATUS_pixeng_layerblend1cfg_layerblend1_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_STATUS_pixeng_layerblend1cfg_layerblend1_sel_SHIFT (16U) /*! pixeng_layerblend1cfg_layerblend1_sel * 0b000..layerblend1 module is not used * 0b001..layerblend1 module is used from store9 processing path * 0b010..layerblend1 module is used from extdst0 processing path * 0b011..layerblend1 module is used from extdst4 processing path * 0b100..layerblend1 module is used from extdst1 processing path * 0b101..layerblend1 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_STATUS_pixeng_layerblend1cfg_layerblend1_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_STATUS_pixeng_layerblend1cfg_layerblend1_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND1CFG_LAYERBLEND1_STATUS_pixeng_layerblend1cfg_layerblend1_sel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2_LockUnlock_SHIFT (0U) /*! pixeng_layerblend2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdLdSel_MASK (0x6U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdLdSel_SHIFT (1U) /*! pixeng_layerblend2_ShdLdSel * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdLdSel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdTokSel_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdTokSel_SHIFT (3U) /*! pixeng_layerblend2_ShdTokSel * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_STATICCONTROL_pixeng_layerblend2_ShdTokSel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_CONTROL - Common control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_MODE_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_MODE_SHIFT (0U) /*! pixeng_layerblend2_MODE * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskEnable_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskEnable_SHIFT (2U) /*! pixeng_layerblend2_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskMode_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskMode_SHIFT (4U) /*! pixeng_layerblend2_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_AlphaMaskMode_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecLowPassEn_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecLowPassEn_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecLowPassEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecLowPassEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecReplicateEn_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecReplicateEn_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecReplicateEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecReplicateEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowEvenColDis_MASK (0x3C00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowEvenColDis_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowOddColDis_MASK (0x3C000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowOddColDis_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecEvenRowOddColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowEvenColDis_MASK (0x3C0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowEvenColDis_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowOddColDis_MASK (0x3C00000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowOddColDis_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_CONTROL_pixeng_layerblend2_SecOddRowOddColDis_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_C_BLD_FUNC_SHIFT (0U) /*! pixeng_layerblend2_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_C_BLD_FUNC_SHIFT (4U) /*! pixeng_layerblend2_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_A_BLD_FUNC_SHIFT (8U) /*! pixeng_layerblend2_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_A_BLD_FUNC_SHIFT (12U) /*! pixeng_layerblend2_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_BLENDCONTROL_pixeng_layerblend2_BlendAlpha_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_XPOS_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_XPOS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_XPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_XPOS_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_YPOS_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_YPOS_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_YPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_POSITION_pixeng_layerblend2_YPOS_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_PRIMCONTROLWORD_pixeng_layerblend2_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_PRIMCONTROLWORD_pixeng_layerblend2_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_PRIMCONTROLWORD_pixeng_layerblend2_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_PRIMCONTROLWORD_pixeng_layerblend2_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_PRIMCONTROLWORD_pixeng_layerblend2_P_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_SECCONTROLWORD_pixeng_layerblend2_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_SECCONTROLWORD_pixeng_layerblend2_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2_SECCONTROLWORD_pixeng_layerblend2_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2_SECCONTROLWORD_pixeng_layerblend2_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2_SECCONTROLWORD_pixeng_layerblend2_S_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2cfg_layerblend2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2cfg_layerblend2_LockUnlock_SHIFT (0U) /*! pixeng_layerblend2cfg_layerblend2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2cfg_layerblend2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2cfg_layerblend2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKUNLOCK_pixeng_layerblend2cfg_layerblend2_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_LOCKSTATUS_pixeng_layerblend2cfg_layerblend2_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC - Dynamic pixel engine configuration for layerblend2 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_prim_sel_SHIFT (0U) /*! pixeng_layerblend2cfg_layerblend2_prim_sel * 0b000000..Unit layerblend2 input port prim is disabled * 0b001100..Unit layerblend2 input port prim is connected to output of unit constframe0 * 0b001101..Unit layerblend2 input port prim is connected to output of unit constframe4 * 0b010000..Unit layerblend2 input port prim is connected to output of unit constframe1 * 0b010001..Unit layerblend2 input port prim is connected to output of unit constframe5 * 0b010100..Unit layerblend2 input port prim is connected to output of unit layerblend1 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_sec_sel_SHIFT (8U) /*! pixeng_layerblend2cfg_layerblend2_sec_sel * 0b000000..Unit layerblend2 input port sec is disabled * 0b000101..Unit layerblend2 input port sec is connected to output of unit fetchrot9 * 0b011010..Unit layerblend2 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend2 input port sec is connected to output of unit fetchlayer1 * 0b011100..Unit layerblend2 input port sec is connected to output of unit fetchyuv3 * 0b011101..Unit layerblend2 input port sec is connected to output of unit fetchyuv0 * 0b011111..Unit layerblend2 input port sec is connected to output of unit fetchyuv1 * 0b100001..Unit layerblend2 input port sec is connected to output of unit fetchyuv2 * 0b100011..Unit layerblend2 input port sec is connected to output of unit matrix4 * 0b100100..Unit layerblend2 input port sec is connected to output of unit hscaler4 * 0b100101..Unit layerblend2 input port sec is connected to output of unit vscaler4 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_clken_SHIFT (24U) /*! pixeng_layerblend2cfg_layerblend2_clken * 0b00..Clock for layerblend2 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend2 is without gating */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_DYNAMIC_pixeng_layerblend2cfg_layerblend2_clken_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND2CFG_LAYERBLEND2_STATUS - Status information for pixel engine configuration of layerblend2 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_STATUS_pixeng_layerblend2cfg_layerblend2_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_STATUS_pixeng_layerblend2cfg_layerblend2_sel_SHIFT (16U) /*! pixeng_layerblend2cfg_layerblend2_sel * 0b000..layerblend2 module is not used * 0b001..layerblend2 module is used from store9 processing path * 0b010..layerblend2 module is used from extdst0 processing path * 0b011..layerblend2 module is used from extdst4 processing path * 0b100..layerblend2 module is used from extdst1 processing path * 0b101..layerblend2 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_STATUS_pixeng_layerblend2cfg_layerblend2_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_STATUS_pixeng_layerblend2cfg_layerblend2_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND2CFG_LAYERBLEND2_STATUS_pixeng_layerblend2cfg_layerblend2_sel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3_LockUnlock_SHIFT (0U) /*! pixeng_layerblend3_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdLdSel_MASK (0x6U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdLdSel_SHIFT (1U) /*! pixeng_layerblend3_ShdLdSel * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdLdSel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdTokSel_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdTokSel_SHIFT (3U) /*! pixeng_layerblend3_ShdTokSel * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_STATICCONTROL_pixeng_layerblend3_ShdTokSel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_CONTROL - Common control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_MODE_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_MODE_SHIFT (0U) /*! pixeng_layerblend3_MODE * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskEnable_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskEnable_SHIFT (2U) /*! pixeng_layerblend3_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskMode_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskMode_SHIFT (4U) /*! pixeng_layerblend3_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_AlphaMaskMode_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecLowPassEn_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecLowPassEn_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecLowPassEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecLowPassEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecReplicateEn_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecReplicateEn_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecReplicateEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecReplicateEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowEvenColDis_MASK (0x3C00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowEvenColDis_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowOddColDis_MASK (0x3C000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowOddColDis_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecEvenRowOddColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowEvenColDis_MASK (0x3C0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowEvenColDis_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowOddColDis_MASK (0x3C00000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowOddColDis_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_CONTROL_pixeng_layerblend3_SecOddRowOddColDis_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_C_BLD_FUNC_SHIFT (0U) /*! pixeng_layerblend3_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_C_BLD_FUNC_SHIFT (4U) /*! pixeng_layerblend3_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_A_BLD_FUNC_SHIFT (8U) /*! pixeng_layerblend3_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_A_BLD_FUNC_SHIFT (12U) /*! pixeng_layerblend3_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_BLENDCONTROL_pixeng_layerblend3_BlendAlpha_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_XPOS_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_XPOS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_XPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_XPOS_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_YPOS_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_YPOS_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_YPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_POSITION_pixeng_layerblend3_YPOS_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_PRIMCONTROLWORD_pixeng_layerblend3_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_PRIMCONTROLWORD_pixeng_layerblend3_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_PRIMCONTROLWORD_pixeng_layerblend3_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_PRIMCONTROLWORD_pixeng_layerblend3_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_PRIMCONTROLWORD_pixeng_layerblend3_P_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_SECCONTROLWORD_pixeng_layerblend3_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_SECCONTROLWORD_pixeng_layerblend3_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3_SECCONTROLWORD_pixeng_layerblend3_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3_SECCONTROLWORD_pixeng_layerblend3_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3_SECCONTROLWORD_pixeng_layerblend3_S_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3cfg_layerblend3_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3cfg_layerblend3_LockUnlock_SHIFT (0U) /*! pixeng_layerblend3cfg_layerblend3_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3cfg_layerblend3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3cfg_layerblend3_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKUNLOCK_pixeng_layerblend3cfg_layerblend3_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_LOCKSTATUS_pixeng_layerblend3cfg_layerblend3_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC - Dynamic pixel engine configuration for layerblend3 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_prim_sel_SHIFT (0U) /*! pixeng_layerblend3cfg_layerblend3_prim_sel * 0b000000..Unit layerblend3 input port prim is disabled * 0b001100..Unit layerblend3 input port prim is connected to output of unit constframe0 * 0b001101..Unit layerblend3 input port prim is connected to output of unit constframe4 * 0b010000..Unit layerblend3 input port prim is connected to output of unit constframe1 * 0b010001..Unit layerblend3 input port prim is connected to output of unit constframe5 * 0b010100..Unit layerblend3 input port prim is connected to output of unit layerblend1 * 0b010101..Unit layerblend3 input port prim is connected to output of unit layerblend2 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_sec_sel_SHIFT (8U) /*! pixeng_layerblend3cfg_layerblend3_sec_sel * 0b000000..Unit layerblend3 input port sec is disabled * 0b000101..Unit layerblend3 input port sec is connected to output of unit fetchrot9 * 0b011010..Unit layerblend3 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend3 input port sec is connected to output of unit fetchlayer1 * 0b011100..Unit layerblend3 input port sec is connected to output of unit fetchyuv3 * 0b011101..Unit layerblend3 input port sec is connected to output of unit fetchyuv0 * 0b011111..Unit layerblend3 input port sec is connected to output of unit fetchyuv1 * 0b100001..Unit layerblend3 input port sec is connected to output of unit fetchyuv2 * 0b100011..Unit layerblend3 input port sec is connected to output of unit matrix4 * 0b100100..Unit layerblend3 input port sec is connected to output of unit hscaler4 * 0b100101..Unit layerblend3 input port sec is connected to output of unit vscaler4 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_clken_SHIFT (24U) /*! pixeng_layerblend3cfg_layerblend3_clken * 0b00..Clock for layerblend3 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend3 is without gating */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_DYNAMIC_pixeng_layerblend3cfg_layerblend3_clken_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND3CFG_LAYERBLEND3_STATUS - Status information for pixel engine configuration of layerblend3 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_STATUS_pixeng_layerblend3cfg_layerblend3_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_STATUS_pixeng_layerblend3cfg_layerblend3_sel_SHIFT (16U) /*! pixeng_layerblend3cfg_layerblend3_sel * 0b000..layerblend3 module is not used * 0b001..layerblend3 module is used from store9 processing path * 0b010..layerblend3 module is used from extdst0 processing path * 0b011..layerblend3 module is used from extdst4 processing path * 0b100..layerblend3 module is used from extdst1 processing path * 0b101..layerblend3 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_STATUS_pixeng_layerblend3cfg_layerblend3_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_STATUS_pixeng_layerblend3cfg_layerblend3_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND3CFG_LAYERBLEND3_STATUS_pixeng_layerblend3cfg_layerblend3_sel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4_LockUnlock_SHIFT (0U) /*! pixeng_layerblend4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdLdSel_MASK (0x6U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdLdSel_SHIFT (1U) /*! pixeng_layerblend4_ShdLdSel * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdLdSel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdTokSel_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdTokSel_SHIFT (3U) /*! pixeng_layerblend4_ShdTokSel * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_STATICCONTROL_pixeng_layerblend4_ShdTokSel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_CONTROL - Common control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_MODE_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_MODE_SHIFT (0U) /*! pixeng_layerblend4_MODE * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskEnable_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskEnable_SHIFT (2U) /*! pixeng_layerblend4_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskMode_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskMode_SHIFT (4U) /*! pixeng_layerblend4_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_AlphaMaskMode_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecLowPassEn_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecLowPassEn_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecLowPassEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecLowPassEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecReplicateEn_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecReplicateEn_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecReplicateEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecReplicateEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowEvenColDis_MASK (0x3C00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowEvenColDis_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowOddColDis_MASK (0x3C000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowOddColDis_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecEvenRowOddColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowEvenColDis_MASK (0x3C0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowEvenColDis_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowOddColDis_MASK (0x3C00000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowOddColDis_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_CONTROL_pixeng_layerblend4_SecOddRowOddColDis_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_C_BLD_FUNC_SHIFT (0U) /*! pixeng_layerblend4_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_C_BLD_FUNC_SHIFT (4U) /*! pixeng_layerblend4_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_A_BLD_FUNC_SHIFT (8U) /*! pixeng_layerblend4_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_A_BLD_FUNC_SHIFT (12U) /*! pixeng_layerblend4_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_BLENDCONTROL_pixeng_layerblend4_BlendAlpha_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_XPOS_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_XPOS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_XPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_XPOS_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_YPOS_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_YPOS_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_YPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_POSITION_pixeng_layerblend4_YPOS_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_PRIMCONTROLWORD_pixeng_layerblend4_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_PRIMCONTROLWORD_pixeng_layerblend4_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_PRIMCONTROLWORD_pixeng_layerblend4_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_PRIMCONTROLWORD_pixeng_layerblend4_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_PRIMCONTROLWORD_pixeng_layerblend4_P_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_SECCONTROLWORD_pixeng_layerblend4_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_SECCONTROLWORD_pixeng_layerblend4_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4_SECCONTROLWORD_pixeng_layerblend4_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4_SECCONTROLWORD_pixeng_layerblend4_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4_SECCONTROLWORD_pixeng_layerblend4_S_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4cfg_layerblend4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4cfg_layerblend4_LockUnlock_SHIFT (0U) /*! pixeng_layerblend4cfg_layerblend4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4cfg_layerblend4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4cfg_layerblend4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKUNLOCK_pixeng_layerblend4cfg_layerblend4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_LOCKSTATUS_pixeng_layerblend4cfg_layerblend4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC - Dynamic pixel engine configuration for layerblend4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_prim_sel_SHIFT (0U) /*! pixeng_layerblend4cfg_layerblend4_prim_sel * 0b000000..Unit layerblend4 input port prim is disabled * 0b001100..Unit layerblend4 input port prim is connected to output of unit constframe0 * 0b001101..Unit layerblend4 input port prim is connected to output of unit constframe4 * 0b010000..Unit layerblend4 input port prim is connected to output of unit constframe1 * 0b010001..Unit layerblend4 input port prim is connected to output of unit constframe5 * 0b010100..Unit layerblend4 input port prim is connected to output of unit layerblend1 * 0b010101..Unit layerblend4 input port prim is connected to output of unit layerblend2 * 0b010110..Unit layerblend4 input port prim is connected to output of unit layerblend3 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_sec_sel_SHIFT (8U) /*! pixeng_layerblend4cfg_layerblend4_sec_sel * 0b000000..Unit layerblend4 input port sec is disabled * 0b000101..Unit layerblend4 input port sec is connected to output of unit fetchrot9 * 0b011010..Unit layerblend4 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend4 input port sec is connected to output of unit fetchlayer1 * 0b011100..Unit layerblend4 input port sec is connected to output of unit fetchyuv3 * 0b011101..Unit layerblend4 input port sec is connected to output of unit fetchyuv0 * 0b011111..Unit layerblend4 input port sec is connected to output of unit fetchyuv1 * 0b100001..Unit layerblend4 input port sec is connected to output of unit fetchyuv2 * 0b100011..Unit layerblend4 input port sec is connected to output of unit matrix4 * 0b100100..Unit layerblend4 input port sec is connected to output of unit hscaler4 * 0b100101..Unit layerblend4 input port sec is connected to output of unit vscaler4 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_clken_SHIFT (24U) /*! pixeng_layerblend4cfg_layerblend4_clken * 0b00..Clock for layerblend4 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend4 is without gating */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_DYNAMIC_pixeng_layerblend4cfg_layerblend4_clken_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND4CFG_LAYERBLEND4_STATUS - Status information for pixel engine configuration of layerblend4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_STATUS_pixeng_layerblend4cfg_layerblend4_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_STATUS_pixeng_layerblend4cfg_layerblend4_sel_SHIFT (16U) /*! pixeng_layerblend4cfg_layerblend4_sel * 0b000..layerblend4 module is not used * 0b001..layerblend4 module is used from store9 processing path * 0b010..layerblend4 module is used from extdst0 processing path * 0b011..layerblend4 module is used from extdst4 processing path * 0b100..layerblend4 module is used from extdst1 processing path * 0b101..layerblend4 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_STATUS_pixeng_layerblend4cfg_layerblend4_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_STATUS_pixeng_layerblend4cfg_layerblend4_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND4CFG_LAYERBLEND4_STATUS_pixeng_layerblend4cfg_layerblend4_sel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5_LockUnlock_SHIFT (0U) /*! pixeng_layerblend5_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdLdSel_MASK (0x6U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdLdSel_SHIFT (1U) /*! pixeng_layerblend5_ShdLdSel * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdLdSel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdTokSel_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdTokSel_SHIFT (3U) /*! pixeng_layerblend5_ShdTokSel * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_STATICCONTROL_pixeng_layerblend5_ShdTokSel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_CONTROL - Common control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_MODE_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_MODE_SHIFT (0U) /*! pixeng_layerblend5_MODE * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskEnable_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskEnable_SHIFT (2U) /*! pixeng_layerblend5_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskMode_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskMode_SHIFT (4U) /*! pixeng_layerblend5_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_AlphaMaskMode_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecLowPassEn_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecLowPassEn_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecLowPassEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecLowPassEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecReplicateEn_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecReplicateEn_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecReplicateEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecReplicateEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowEvenColDis_MASK (0x3C00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowEvenColDis_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowOddColDis_MASK (0x3C000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowOddColDis_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecEvenRowOddColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowEvenColDis_MASK (0x3C0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowEvenColDis_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowOddColDis_MASK (0x3C00000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowOddColDis_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_CONTROL_pixeng_layerblend5_SecOddRowOddColDis_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_C_BLD_FUNC_SHIFT (0U) /*! pixeng_layerblend5_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_C_BLD_FUNC_SHIFT (4U) /*! pixeng_layerblend5_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_A_BLD_FUNC_SHIFT (8U) /*! pixeng_layerblend5_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_A_BLD_FUNC_SHIFT (12U) /*! pixeng_layerblend5_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_BLENDCONTROL_pixeng_layerblend5_BlendAlpha_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_XPOS_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_XPOS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_XPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_XPOS_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_YPOS_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_YPOS_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_YPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_POSITION_pixeng_layerblend5_YPOS_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_PRIMCONTROLWORD_pixeng_layerblend5_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_PRIMCONTROLWORD_pixeng_layerblend5_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_PRIMCONTROLWORD_pixeng_layerblend5_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_PRIMCONTROLWORD_pixeng_layerblend5_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_PRIMCONTROLWORD_pixeng_layerblend5_P_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_SECCONTROLWORD_pixeng_layerblend5_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_SECCONTROLWORD_pixeng_layerblend5_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5_SECCONTROLWORD_pixeng_layerblend5_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5_SECCONTROLWORD_pixeng_layerblend5_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5_SECCONTROLWORD_pixeng_layerblend5_S_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5cfg_layerblend5_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5cfg_layerblend5_LockUnlock_SHIFT (0U) /*! pixeng_layerblend5cfg_layerblend5_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5cfg_layerblend5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5cfg_layerblend5_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKUNLOCK_pixeng_layerblend5cfg_layerblend5_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_LOCKSTATUS_pixeng_layerblend5cfg_layerblend5_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC - Dynamic pixel engine configuration for layerblend5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_prim_sel_SHIFT (0U) /*! pixeng_layerblend5cfg_layerblend5_prim_sel * 0b000000..Unit layerblend5 input port prim is disabled * 0b001100..Unit layerblend5 input port prim is connected to output of unit constframe0 * 0b001101..Unit layerblend5 input port prim is connected to output of unit constframe4 * 0b010000..Unit layerblend5 input port prim is connected to output of unit constframe1 * 0b010001..Unit layerblend5 input port prim is connected to output of unit constframe5 * 0b010100..Unit layerblend5 input port prim is connected to output of unit layerblend1 * 0b010101..Unit layerblend5 input port prim is connected to output of unit layerblend2 * 0b010110..Unit layerblend5 input port prim is connected to output of unit layerblend3 * 0b010111..Unit layerblend5 input port prim is connected to output of unit layerblend4 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_sec_sel_SHIFT (8U) /*! pixeng_layerblend5cfg_layerblend5_sec_sel * 0b000000..Unit layerblend5 input port sec is disabled * 0b000101..Unit layerblend5 input port sec is connected to output of unit fetchrot9 * 0b011010..Unit layerblend5 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend5 input port sec is connected to output of unit fetchlayer1 * 0b011100..Unit layerblend5 input port sec is connected to output of unit fetchyuv3 * 0b011101..Unit layerblend5 input port sec is connected to output of unit fetchyuv0 * 0b011111..Unit layerblend5 input port sec is connected to output of unit fetchyuv1 * 0b100001..Unit layerblend5 input port sec is connected to output of unit fetchyuv2 * 0b100011..Unit layerblend5 input port sec is connected to output of unit matrix4 * 0b100100..Unit layerblend5 input port sec is connected to output of unit hscaler4 * 0b100101..Unit layerblend5 input port sec is connected to output of unit vscaler4 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_clken_SHIFT (24U) /*! pixeng_layerblend5cfg_layerblend5_clken * 0b00..Clock for layerblend5 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend5 is without gating */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_DYNAMIC_pixeng_layerblend5cfg_layerblend5_clken_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND5CFG_LAYERBLEND5_STATUS - Status information for pixel engine configuration of layerblend5 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_STATUS_pixeng_layerblend5cfg_layerblend5_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_STATUS_pixeng_layerblend5cfg_layerblend5_sel_SHIFT (16U) /*! pixeng_layerblend5cfg_layerblend5_sel * 0b000..layerblend5 module is not used * 0b001..layerblend5 module is used from store9 processing path * 0b010..layerblend5 module is used from extdst0 processing path * 0b011..layerblend5 module is used from extdst4 processing path * 0b100..layerblend5 module is used from extdst1 processing path * 0b101..layerblend5 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_STATUS_pixeng_layerblend5cfg_layerblend5_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_STATUS_pixeng_layerblend5cfg_layerblend5_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND5CFG_LAYERBLEND5_STATUS_pixeng_layerblend5cfg_layerblend5_sel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6_LockUnlock_SHIFT (0U) /*! pixeng_layerblend6_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdLdSel_MASK (0x6U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdLdSel_SHIFT (1U) /*! pixeng_layerblend6_ShdLdSel * 0b00..Load shadows with shadow load token on primary input (background plane). * 0b01..Load shadows with shadow load token on secondary input (foreground plane). * 0b10..Load shadows with shadow load token on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdLdSel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdTokSel_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdTokSel_SHIFT (3U) /*! pixeng_layerblend6_ShdTokSel * 0b00..When a token was received on the primary input (background plane). * 0b01..When a token was received on the secondary input (foreground plane). * 0b10..When a token was received on any input. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_STATICCONTROL_pixeng_layerblend6_ShdTokSel_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_CONTROL - Common control settings. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_MODE_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_MODE_SHIFT (0U) /*! pixeng_layerblend6_MODE * 0b0..Module is in neutral mode. Output is same as primary input. * 0b1..Module is in blending mode. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskEnable_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskEnable_SHIFT (2U) /*! pixeng_layerblend6_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskMode_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskMode_SHIFT (4U) /*! pixeng_layerblend6_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_AlphaMaskMode_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecLowPassEn_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecLowPassEn_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecLowPassEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecLowPassEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecLowPassEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecReplicateEn_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecReplicateEn_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecReplicateEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecReplicateEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecReplicateEn_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowEvenColDis_MASK (0x3C00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowEvenColDis_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowOddColDis_MASK (0x3C000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowOddColDis_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecEvenRowOddColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowEvenColDis_MASK (0x3C0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowEvenColDis_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowEvenColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowEvenColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowEvenColDis_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowOddColDis_MASK (0x3C00000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowOddColDis_SHIFT (22U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowOddColDis(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowOddColDis_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_CONTROL_pixeng_layerblend6_SecOddRowOddColDis_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_C_BLD_FUNC_SHIFT (0U) /*! pixeng_layerblend6_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_C_BLD_FUNC_SHIFT (4U) /*! pixeng_layerblend6_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_A_BLD_FUNC_SHIFT (8U) /*! pixeng_layerblend6_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_A_BLD_FUNC_SHIFT (12U) /*! pixeng_layerblend6_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_BLENDCONTROL_pixeng_layerblend6_BlendAlpha_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_POSITION - Position of secondary (overlay) input frame */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_XPOS_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_XPOS_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_XPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_XPOS_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_YPOS_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_YPOS_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_YPOS_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_POSITION_pixeng_layerblend6_YPOS_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_PRIMCONTROLWORD - Value of last received primary (background) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_PRIMCONTROLWORD_pixeng_layerblend6_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_PRIMCONTROLWORD_pixeng_layerblend6_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_PRIMCONTROLWORD_pixeng_layerblend6_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_PRIMCONTROLWORD_pixeng_layerblend6_P_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_PRIMCONTROLWORD_pixeng_layerblend6_P_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6_SECCONTROLWORD - Value of last received secondary (overlay) control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_SECCONTROLWORD_pixeng_layerblend6_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_SECCONTROLWORD_pixeng_layerblend6_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6_SECCONTROLWORD_pixeng_layerblend6_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6_SECCONTROLWORD_pixeng_layerblend6_S_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6_SECCONTROLWORD_pixeng_layerblend6_S_VAL_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6cfg_layerblend6_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6cfg_layerblend6_LockUnlock_SHIFT (0U) /*! pixeng_layerblend6cfg_layerblend6_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6cfg_layerblend6_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6cfg_layerblend6_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKUNLOCK_pixeng_layerblend6cfg_layerblend6_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_LOCKSTATUS_pixeng_layerblend6cfg_layerblend6_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC - Dynamic pixel engine configuration for layerblend6 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_prim_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_prim_sel_SHIFT (0U) /*! pixeng_layerblend6cfg_layerblend6_prim_sel * 0b000000..Unit layerblend6 input port prim is disabled * 0b001100..Unit layerblend6 input port prim is connected to output of unit constframe0 * 0b001101..Unit layerblend6 input port prim is connected to output of unit constframe4 * 0b010000..Unit layerblend6 input port prim is connected to output of unit constframe1 * 0b010001..Unit layerblend6 input port prim is connected to output of unit constframe5 * 0b010100..Unit layerblend6 input port prim is connected to output of unit layerblend1 * 0b010101..Unit layerblend6 input port prim is connected to output of unit layerblend2 * 0b010110..Unit layerblend6 input port prim is connected to output of unit layerblend3 * 0b010111..Unit layerblend6 input port prim is connected to output of unit layerblend4 * 0b011000..Unit layerblend6 input port prim is connected to output of unit layerblend5 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_prim_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_prim_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_sec_sel_SHIFT (8U) /*! pixeng_layerblend6cfg_layerblend6_sec_sel * 0b000000..Unit layerblend6 input port sec is disabled * 0b000101..Unit layerblend6 input port sec is connected to output of unit fetchrot9 * 0b011010..Unit layerblend6 input port sec is connected to output of unit fetchlayer0 * 0b011011..Unit layerblend6 input port sec is connected to output of unit fetchlayer1 * 0b011100..Unit layerblend6 input port sec is connected to output of unit fetchyuv3 * 0b011101..Unit layerblend6 input port sec is connected to output of unit fetchyuv0 * 0b011111..Unit layerblend6 input port sec is connected to output of unit fetchyuv1 * 0b100001..Unit layerblend6 input port sec is connected to output of unit fetchyuv2 * 0b100011..Unit layerblend6 input port sec is connected to output of unit matrix4 * 0b100100..Unit layerblend6 input port sec is connected to output of unit hscaler4 * 0b100101..Unit layerblend6 input port sec is connected to output of unit vscaler4 */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_sec_sel_MASK) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_clken_SHIFT (24U) /*! pixeng_layerblend6cfg_layerblend6_clken * 0b00..Clock for layerblend6 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for layerblend6 is without gating */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_DYNAMIC_pixeng_layerblend6cfg_layerblend6_clken_MASK) /*! @} */ /*! @name PIXENG_LAYERBLEND6CFG_LAYERBLEND6_STATUS - Status information for pixel engine configuration of layerblend6 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_STATUS_pixeng_layerblend6cfg_layerblend6_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_STATUS_pixeng_layerblend6cfg_layerblend6_sel_SHIFT (16U) /*! pixeng_layerblend6cfg_layerblend6_sel * 0b000..layerblend6 module is not used * 0b001..layerblend6 module is used from store9 processing path * 0b010..layerblend6 module is used from extdst0 processing path * 0b011..layerblend6 module is used from extdst4 processing path * 0b100..layerblend6 module is used from extdst1 processing path * 0b101..layerblend6 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_STATUS_pixeng_layerblend6cfg_layerblend6_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_STATUS_pixeng_layerblend6cfg_layerblend6_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_LAYERBLEND6CFG_LAYERBLEND6_STATUS_pixeng_layerblend6cfg_layerblend6_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0_LockUnlock_SHIFT (0U) /*! pixeng_fetchlayer0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATICCONTROL_pixeng_fetchlayer0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATICCONTROL_pixeng_fetchlayer0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATICCONTROL_pixeng_fetchlayer0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATICCONTROL_pixeng_fetchlayer0_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATICCONTROL_pixeng_fetchlayer0_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SHDLDREQCONTROL - Shadow load request flags for each layer. Static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky1_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky1_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky2_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky2_SHIFT (2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky3_MASK (0x8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky3_SHIFT (3U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky4_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky4_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky5_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky5_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky6_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky6_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky7_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky7_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SHDLDREQCONTROL_pixeng_fetchlayer0_ShdLdReqSticky7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer0_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS0_pixeng_fetchlayer0_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS0_pixeng_fetchlayer0_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS0_pixeng_fetchlayer0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS0_pixeng_fetchlayer0_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS0_pixeng_fetchlayer0_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB0_pixeng_fetchlayer0_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB0_pixeng_fetchlayer0_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB0_pixeng_fetchlayer0_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB0_pixeng_fetchlayer0_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB0_pixeng_fetchlayer0_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer0_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer0_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer0_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer0_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer0_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer0_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer0_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS0_pixeng_fetchlayer0_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT0_pixeng_fetchlayer0_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET0_pixeng_fetchlayer0_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET0_pixeng_fetchlayer0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer0_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR0_pixeng_fetchlayer0_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PaletteEnable0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PaletteEnable0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PaletteEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PaletteEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_TileMode0_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY0_pixeng_fetchlayer0_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS1_pixeng_fetchlayer0_BaseAddress1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS1_pixeng_fetchlayer0_BaseAddress1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS1_pixeng_fetchlayer0_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS1_pixeng_fetchlayer0_BaseAddress1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS1_pixeng_fetchlayer0_BaseAddress1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB1_pixeng_fetchlayer0_BaseAddressMSB1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB1_pixeng_fetchlayer0_BaseAddressMSB1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB1_pixeng_fetchlayer0_BaseAddressMSB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB1_pixeng_fetchlayer0_BaseAddressMSB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB1_pixeng_fetchlayer0_BaseAddressMSB1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer0_AutoUpdateBaseAddress1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer0_AutoUpdateBaseAddress1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer0_AutoUpdateBaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer0_AutoUpdateBaseAddress1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer0_AutoUpdateBaseAddress1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_Stride1_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_Stride1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_Stride1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_Stride1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_Stride1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BitsPerPixel1_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BitsPerPixel1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BitsPerPixel1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BitsPerPixel1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BaseAddressAutoUpdate1_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BaseAddressAutoUpdate1_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BaseAddressAutoUpdate1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BaseAddressAutoUpdate1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_BaseAddressAutoUpdate1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_DWordByteSwap1_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_DWordByteSwap1_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_DWordByteSwap1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_DWordByteSwap1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer0_DWordByteSwap1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineWidth1_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineWidth1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineWidth1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineWidth1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineCount1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineCount1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineCount1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer0_LineCount1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsAlpha1_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsAlpha1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsAlpha1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsAlpha1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsBlue1_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsBlue1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsBlue1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsBlue1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsGreen1_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsGreen1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsGreen1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsGreen1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsRed1_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsRed1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsRed1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ComponentBitsRed1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ITUFormat1_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ITUFormat1_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ITUFormat1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS1_pixeng_fetchlayer0_ITUFormat1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftAlpha1_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftAlpha1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftAlpha1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftAlpha1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftBlue1_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftBlue1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftBlue1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftBlue1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftGreen1_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftGreen1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftGreen1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftGreen1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftRed1_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftRed1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftRed1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT1_pixeng_fetchlayer0_ComponentShiftRed1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET1 - Position of layer 1 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerXOffset1_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerXOffset1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerXOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerXOffset1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerYOffset1_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerYOffset1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerYOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET1_pixeng_fetchlayer0_LayerYOffset1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowXOffset1_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowXOffset1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowXOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowXOffset1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowYOffset1_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowYOffset1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowYOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET1_pixeng_fetchlayer0_ClipWindowYOffset1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowWidth1_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowWidth1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowWidth1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowWidth1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowHeight1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowHeight1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowHeight1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer0_ClipWindowHeight1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR1 - Constant color for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantAlpha1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantAlpha1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantAlpha1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantAlpha1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantBlue1_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantBlue1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantBlue1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantBlue1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantGreen1_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantGreen1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantGreen1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantGreen1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantRed1_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantRed1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantRed1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR1_pixeng_fetchlayer0_ConstantRed1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY1 - Common properties of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PaletteEnable1_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PaletteEnable1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PaletteEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PaletteEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PaletteEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_TileMode1_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_TileMode1_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode1 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_TileMode1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_TileMode1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaSrcEnable1_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaSrcEnable1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaSrcEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaSrcEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaConstEnable1_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaConstEnable1_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaConstEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaConstEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaTransEnable1_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaTransEnable1_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaTransEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_AlphaTransEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaSrcEnable1_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaSrcEnable1_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaSrcEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaSrcEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaConstEnable1_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaConstEnable1_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaConstEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaConstEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaTransEnable1_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaTransEnable1_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaTransEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_RGBAlphaTransEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PremulConstRGB1_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PremulConstRGB1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PremulConstRGB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_PremulConstRGB1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_YUVConversionMode1_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_YUVConversionMode1_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode1 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_YUVConversionMode1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_YUVConversionMode1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_GammaRemoveEnable1_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_GammaRemoveEnable1_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_GammaRemoveEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_GammaRemoveEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_ClipWindowEnable1_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_ClipWindowEnable1_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_ClipWindowEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_ClipWindowEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_SourceBufferEnable1_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_SourceBufferEnable1_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_SourceBufferEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY1_pixeng_fetchlayer0_SourceBufferEnable1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS2_pixeng_fetchlayer0_BaseAddress2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS2_pixeng_fetchlayer0_BaseAddress2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS2_pixeng_fetchlayer0_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS2_pixeng_fetchlayer0_BaseAddress2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS2_pixeng_fetchlayer0_BaseAddress2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB2_pixeng_fetchlayer0_BaseAddressMSB2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB2_pixeng_fetchlayer0_BaseAddressMSB2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB2_pixeng_fetchlayer0_BaseAddressMSB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB2_pixeng_fetchlayer0_BaseAddressMSB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB2_pixeng_fetchlayer0_BaseAddressMSB2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer0_AutoUpdateBaseAddress2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer0_AutoUpdateBaseAddress2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer0_AutoUpdateBaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer0_AutoUpdateBaseAddress2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer0_AutoUpdateBaseAddress2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_Stride2_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_Stride2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_Stride2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_Stride2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_Stride2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BitsPerPixel2_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BitsPerPixel2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BitsPerPixel2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BitsPerPixel2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BaseAddressAutoUpdate2_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BaseAddressAutoUpdate2_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BaseAddressAutoUpdate2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BaseAddressAutoUpdate2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_BaseAddressAutoUpdate2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_DWordByteSwap2_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_DWordByteSwap2_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_DWordByteSwap2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_DWordByteSwap2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer0_DWordByteSwap2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2 - Source buffer dimensions of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineWidth2_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineWidth2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineWidth2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineWidth2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineCount2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineCount2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineCount2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer0_LineCount2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsAlpha2_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsAlpha2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsAlpha2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsAlpha2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsBlue2_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsBlue2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsBlue2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsBlue2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsGreen2_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsGreen2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsGreen2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsGreen2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsRed2_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsRed2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsRed2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ComponentBitsRed2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ITUFormat2_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ITUFormat2_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ITUFormat2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS2_pixeng_fetchlayer0_ITUFormat2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftAlpha2_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftAlpha2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftAlpha2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftAlpha2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftBlue2_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftBlue2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftBlue2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftBlue2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftGreen2_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftGreen2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftGreen2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftGreen2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftRed2_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftRed2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftRed2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT2_pixeng_fetchlayer0_ComponentShiftRed2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET2 - Position of layer 2 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerXOffset2_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerXOffset2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerXOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerXOffset2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerYOffset2_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerYOffset2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerYOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET2_pixeng_fetchlayer0_LayerYOffset2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowXOffset2_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowXOffset2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowXOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowXOffset2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowYOffset2_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowYOffset2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowYOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET2_pixeng_fetchlayer0_ClipWindowYOffset2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowWidth2_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowWidth2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowWidth2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowWidth2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowHeight2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowHeight2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowHeight2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer0_ClipWindowHeight2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR2 - Constant color for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantAlpha2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantAlpha2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantAlpha2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantAlpha2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantBlue2_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantBlue2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantBlue2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantBlue2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantGreen2_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantGreen2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantGreen2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantGreen2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantRed2_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantRed2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantRed2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR2_pixeng_fetchlayer0_ConstantRed2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY2 - Common properties of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PaletteEnable2_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PaletteEnable2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PaletteEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PaletteEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PaletteEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_TileMode2_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_TileMode2_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode2 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_TileMode2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_TileMode2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaSrcEnable2_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaSrcEnable2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaSrcEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaSrcEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaConstEnable2_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaConstEnable2_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaConstEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaConstEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaTransEnable2_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaTransEnable2_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaTransEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_AlphaTransEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaSrcEnable2_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaSrcEnable2_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaSrcEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaSrcEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaConstEnable2_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaConstEnable2_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaConstEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaConstEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaTransEnable2_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaTransEnable2_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaTransEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_RGBAlphaTransEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PremulConstRGB2_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PremulConstRGB2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PremulConstRGB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_PremulConstRGB2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_YUVConversionMode2_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_YUVConversionMode2_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode2 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_YUVConversionMode2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_YUVConversionMode2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_GammaRemoveEnable2_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_GammaRemoveEnable2_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_GammaRemoveEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_GammaRemoveEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_ClipWindowEnable2_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_ClipWindowEnable2_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_ClipWindowEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_ClipWindowEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_SourceBufferEnable2_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_SourceBufferEnable2_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_SourceBufferEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY2_pixeng_fetchlayer0_SourceBufferEnable2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS3_pixeng_fetchlayer0_BaseAddress3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS3_pixeng_fetchlayer0_BaseAddress3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS3_pixeng_fetchlayer0_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS3_pixeng_fetchlayer0_BaseAddress3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS3_pixeng_fetchlayer0_BaseAddress3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB3_pixeng_fetchlayer0_BaseAddressMSB3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB3_pixeng_fetchlayer0_BaseAddressMSB3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB3_pixeng_fetchlayer0_BaseAddressMSB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB3_pixeng_fetchlayer0_BaseAddressMSB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB3_pixeng_fetchlayer0_BaseAddressMSB3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer0_AutoUpdateBaseAddress3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer0_AutoUpdateBaseAddress3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer0_AutoUpdateBaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer0_AutoUpdateBaseAddress3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer0_AutoUpdateBaseAddress3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_Stride3_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_Stride3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_Stride3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_Stride3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_Stride3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BitsPerPixel3_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BitsPerPixel3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BitsPerPixel3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BitsPerPixel3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BaseAddressAutoUpdate3_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BaseAddressAutoUpdate3_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BaseAddressAutoUpdate3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BaseAddressAutoUpdate3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_BaseAddressAutoUpdate3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_DWordByteSwap3_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_DWordByteSwap3_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_DWordByteSwap3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_DWordByteSwap3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer0_DWordByteSwap3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3 - Source buffer dimensions of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineWidth3_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineWidth3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineWidth3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineWidth3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineCount3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineCount3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineCount3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer0_LineCount3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsAlpha3_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsAlpha3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsAlpha3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsAlpha3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsBlue3_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsBlue3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsBlue3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsBlue3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsGreen3_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsGreen3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsGreen3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsGreen3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsRed3_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsRed3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsRed3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ComponentBitsRed3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ITUFormat3_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ITUFormat3_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ITUFormat3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS3_pixeng_fetchlayer0_ITUFormat3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftAlpha3_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftAlpha3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftAlpha3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftAlpha3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftBlue3_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftBlue3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftBlue3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftBlue3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftGreen3_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftGreen3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftGreen3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftGreen3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftRed3_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftRed3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftRed3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT3_pixeng_fetchlayer0_ComponentShiftRed3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET3 - Position of layer 3 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerXOffset3_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerXOffset3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerXOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerXOffset3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerYOffset3_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerYOffset3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerYOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET3_pixeng_fetchlayer0_LayerYOffset3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowXOffset3_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowXOffset3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowXOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowXOffset3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowYOffset3_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowYOffset3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowYOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET3_pixeng_fetchlayer0_ClipWindowYOffset3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowWidth3_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowWidth3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowWidth3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowWidth3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowHeight3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowHeight3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowHeight3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer0_ClipWindowHeight3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR3 - Constant color for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantAlpha3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantAlpha3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantAlpha3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantAlpha3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantBlue3_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantBlue3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantBlue3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantBlue3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantGreen3_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantGreen3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantGreen3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantGreen3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantRed3_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantRed3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantRed3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR3_pixeng_fetchlayer0_ConstantRed3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY3 - Common properties of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PaletteEnable3_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PaletteEnable3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PaletteEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PaletteEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PaletteEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_TileMode3_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_TileMode3_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode3 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_TileMode3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_TileMode3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaSrcEnable3_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaSrcEnable3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaSrcEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaSrcEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaConstEnable3_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaConstEnable3_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaConstEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaConstEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaTransEnable3_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaTransEnable3_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaTransEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_AlphaTransEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaSrcEnable3_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaSrcEnable3_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaSrcEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaSrcEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaConstEnable3_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaConstEnable3_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaConstEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaConstEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaTransEnable3_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaTransEnable3_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaTransEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_RGBAlphaTransEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PremulConstRGB3_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PremulConstRGB3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PremulConstRGB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_PremulConstRGB3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_YUVConversionMode3_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_YUVConversionMode3_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode3 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_YUVConversionMode3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_YUVConversionMode3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_GammaRemoveEnable3_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_GammaRemoveEnable3_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_GammaRemoveEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_GammaRemoveEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_ClipWindowEnable3_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_ClipWindowEnable3_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_ClipWindowEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_ClipWindowEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_SourceBufferEnable3_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_SourceBufferEnable3_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_SourceBufferEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY3_pixeng_fetchlayer0_SourceBufferEnable3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS4_pixeng_fetchlayer0_BaseAddress4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS4_pixeng_fetchlayer0_BaseAddress4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS4_pixeng_fetchlayer0_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS4_pixeng_fetchlayer0_BaseAddress4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS4_pixeng_fetchlayer0_BaseAddress4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB4_pixeng_fetchlayer0_BaseAddressMSB4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB4_pixeng_fetchlayer0_BaseAddressMSB4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB4_pixeng_fetchlayer0_BaseAddressMSB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB4_pixeng_fetchlayer0_BaseAddressMSB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB4_pixeng_fetchlayer0_BaseAddressMSB4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer0_AutoUpdateBaseAddress4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer0_AutoUpdateBaseAddress4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer0_AutoUpdateBaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer0_AutoUpdateBaseAddress4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer0_AutoUpdateBaseAddress4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_Stride4_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_Stride4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_Stride4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_Stride4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_Stride4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BitsPerPixel4_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BitsPerPixel4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BitsPerPixel4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BitsPerPixel4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BaseAddressAutoUpdate4_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BaseAddressAutoUpdate4_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BaseAddressAutoUpdate4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BaseAddressAutoUpdate4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_BaseAddressAutoUpdate4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_DWordByteSwap4_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_DWordByteSwap4_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_DWordByteSwap4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_DWordByteSwap4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer0_DWordByteSwap4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4 - Source buffer dimensions of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineWidth4_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineWidth4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineWidth4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineWidth4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineCount4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineCount4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineCount4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer0_LineCount4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsAlpha4_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsAlpha4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsAlpha4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsAlpha4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsBlue4_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsBlue4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsBlue4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsBlue4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsGreen4_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsGreen4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsGreen4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsGreen4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsRed4_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsRed4_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsRed4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ComponentBitsRed4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ITUFormat4_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ITUFormat4_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ITUFormat4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS4_pixeng_fetchlayer0_ITUFormat4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftAlpha4_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftAlpha4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftAlpha4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftAlpha4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftBlue4_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftBlue4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftBlue4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftBlue4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftGreen4_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftGreen4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftGreen4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftGreen4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftRed4_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftRed4_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftRed4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT4_pixeng_fetchlayer0_ComponentShiftRed4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET4 - Position of layer 4 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerXOffset4_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerXOffset4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerXOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerXOffset4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerYOffset4_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerYOffset4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerYOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET4_pixeng_fetchlayer0_LayerYOffset4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowXOffset4_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowXOffset4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowXOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowXOffset4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowYOffset4_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowYOffset4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowYOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET4_pixeng_fetchlayer0_ClipWindowYOffset4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowWidth4_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowWidth4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowWidth4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowWidth4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowHeight4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowHeight4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowHeight4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer0_ClipWindowHeight4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR4 - Constant color for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantAlpha4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantAlpha4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantAlpha4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantAlpha4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantBlue4_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantBlue4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantBlue4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantBlue4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantGreen4_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantGreen4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantGreen4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantGreen4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantRed4_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantRed4_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantRed4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR4_pixeng_fetchlayer0_ConstantRed4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY4 - Common properties of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PaletteEnable4_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PaletteEnable4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PaletteEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PaletteEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PaletteEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_TileMode4_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_TileMode4_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode4 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_TileMode4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_TileMode4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaSrcEnable4_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaSrcEnable4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaSrcEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaSrcEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaConstEnable4_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaConstEnable4_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaConstEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaConstEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaTransEnable4_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaTransEnable4_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaTransEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_AlphaTransEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaSrcEnable4_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaSrcEnable4_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaSrcEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaSrcEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaConstEnable4_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaConstEnable4_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaConstEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaConstEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaTransEnable4_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaTransEnable4_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaTransEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_RGBAlphaTransEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PremulConstRGB4_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PremulConstRGB4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PremulConstRGB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_PremulConstRGB4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_YUVConversionMode4_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_YUVConversionMode4_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode4 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_YUVConversionMode4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_YUVConversionMode4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_GammaRemoveEnable4_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_GammaRemoveEnable4_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_GammaRemoveEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_GammaRemoveEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_ClipWindowEnable4_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_ClipWindowEnable4_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_ClipWindowEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_ClipWindowEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_SourceBufferEnable4_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_SourceBufferEnable4_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_SourceBufferEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY4_pixeng_fetchlayer0_SourceBufferEnable4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS5_pixeng_fetchlayer0_BaseAddress5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS5_pixeng_fetchlayer0_BaseAddress5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS5_pixeng_fetchlayer0_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS5_pixeng_fetchlayer0_BaseAddress5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS5_pixeng_fetchlayer0_BaseAddress5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB5_pixeng_fetchlayer0_BaseAddressMSB5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB5_pixeng_fetchlayer0_BaseAddressMSB5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB5_pixeng_fetchlayer0_BaseAddressMSB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB5_pixeng_fetchlayer0_BaseAddressMSB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB5_pixeng_fetchlayer0_BaseAddressMSB5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer0_AutoUpdateBaseAddress5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer0_AutoUpdateBaseAddress5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer0_AutoUpdateBaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer0_AutoUpdateBaseAddress5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer0_AutoUpdateBaseAddress5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_Stride5_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_Stride5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_Stride5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_Stride5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_Stride5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BitsPerPixel5_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BitsPerPixel5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BitsPerPixel5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BitsPerPixel5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BaseAddressAutoUpdate5_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BaseAddressAutoUpdate5_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BaseAddressAutoUpdate5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BaseAddressAutoUpdate5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_BaseAddressAutoUpdate5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_DWordByteSwap5_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_DWordByteSwap5_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_DWordByteSwap5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_DWordByteSwap5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer0_DWordByteSwap5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5 - Source buffer dimensions of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineWidth5_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineWidth5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineWidth5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineWidth5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineCount5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineCount5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineCount5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer0_LineCount5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsAlpha5_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsAlpha5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsAlpha5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsAlpha5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsBlue5_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsBlue5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsBlue5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsBlue5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsGreen5_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsGreen5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsGreen5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsGreen5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsRed5_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsRed5_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsRed5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ComponentBitsRed5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ITUFormat5_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ITUFormat5_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ITUFormat5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS5_pixeng_fetchlayer0_ITUFormat5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftAlpha5_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftAlpha5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftAlpha5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftAlpha5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftBlue5_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftBlue5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftBlue5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftBlue5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftGreen5_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftGreen5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftGreen5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftGreen5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftRed5_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftRed5_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftRed5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT5_pixeng_fetchlayer0_ComponentShiftRed5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET5 - Position of layer 5 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerXOffset5_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerXOffset5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerXOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerXOffset5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerYOffset5_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerYOffset5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerYOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET5_pixeng_fetchlayer0_LayerYOffset5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowXOffset5_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowXOffset5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowXOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowXOffset5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowYOffset5_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowYOffset5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowYOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET5_pixeng_fetchlayer0_ClipWindowYOffset5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowWidth5_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowWidth5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowWidth5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowWidth5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowHeight5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowHeight5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowHeight5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer0_ClipWindowHeight5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR5 - Constant color for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantAlpha5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantAlpha5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantAlpha5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantAlpha5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantBlue5_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantBlue5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantBlue5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantBlue5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantGreen5_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantGreen5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantGreen5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantGreen5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantRed5_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantRed5_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantRed5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR5_pixeng_fetchlayer0_ConstantRed5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY5 - Common properties of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PaletteEnable5_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PaletteEnable5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PaletteEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PaletteEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PaletteEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_TileMode5_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_TileMode5_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode5 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_TileMode5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_TileMode5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaSrcEnable5_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaSrcEnable5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaSrcEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaSrcEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaConstEnable5_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaConstEnable5_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaConstEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaConstEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaTransEnable5_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaTransEnable5_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaTransEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_AlphaTransEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaSrcEnable5_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaSrcEnable5_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaSrcEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaSrcEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaConstEnable5_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaConstEnable5_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaConstEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaConstEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaTransEnable5_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaTransEnable5_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaTransEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_RGBAlphaTransEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PremulConstRGB5_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PremulConstRGB5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PremulConstRGB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_PremulConstRGB5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_YUVConversionMode5_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_YUVConversionMode5_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode5 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_YUVConversionMode5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_YUVConversionMode5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_GammaRemoveEnable5_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_GammaRemoveEnable5_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_GammaRemoveEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_GammaRemoveEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_ClipWindowEnable5_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_ClipWindowEnable5_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_ClipWindowEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_ClipWindowEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_SourceBufferEnable5_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_SourceBufferEnable5_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_SourceBufferEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY5_pixeng_fetchlayer0_SourceBufferEnable5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS6_pixeng_fetchlayer0_BaseAddress6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS6_pixeng_fetchlayer0_BaseAddress6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS6_pixeng_fetchlayer0_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS6_pixeng_fetchlayer0_BaseAddress6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS6_pixeng_fetchlayer0_BaseAddress6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB6_pixeng_fetchlayer0_BaseAddressMSB6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB6_pixeng_fetchlayer0_BaseAddressMSB6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB6_pixeng_fetchlayer0_BaseAddressMSB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB6_pixeng_fetchlayer0_BaseAddressMSB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB6_pixeng_fetchlayer0_BaseAddressMSB6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer0_AutoUpdateBaseAddress6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer0_AutoUpdateBaseAddress6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer0_AutoUpdateBaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer0_AutoUpdateBaseAddress6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer0_AutoUpdateBaseAddress6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_Stride6_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_Stride6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_Stride6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_Stride6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_Stride6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BitsPerPixel6_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BitsPerPixel6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BitsPerPixel6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BitsPerPixel6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BaseAddressAutoUpdate6_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BaseAddressAutoUpdate6_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BaseAddressAutoUpdate6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BaseAddressAutoUpdate6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_BaseAddressAutoUpdate6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_DWordByteSwap6_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_DWordByteSwap6_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_DWordByteSwap6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_DWordByteSwap6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer0_DWordByteSwap6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6 - Source buffer dimensions of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineWidth6_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineWidth6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineWidth6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineWidth6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineCount6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineCount6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineCount6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer0_LineCount6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsAlpha6_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsAlpha6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsAlpha6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsAlpha6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsBlue6_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsBlue6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsBlue6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsBlue6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsGreen6_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsGreen6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsGreen6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsGreen6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsRed6_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsRed6_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsRed6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ComponentBitsRed6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ITUFormat6_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ITUFormat6_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ITUFormat6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS6_pixeng_fetchlayer0_ITUFormat6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftAlpha6_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftAlpha6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftAlpha6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftAlpha6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftBlue6_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftBlue6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftBlue6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftBlue6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftGreen6_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftGreen6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftGreen6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftGreen6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftRed6_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftRed6_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftRed6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT6_pixeng_fetchlayer0_ComponentShiftRed6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET6 - Position of layer 6 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerXOffset6_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerXOffset6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerXOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerXOffset6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerYOffset6_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerYOffset6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerYOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET6_pixeng_fetchlayer0_LayerYOffset6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowXOffset6_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowXOffset6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowXOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowXOffset6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowYOffset6_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowYOffset6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowYOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET6_pixeng_fetchlayer0_ClipWindowYOffset6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowWidth6_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowWidth6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowWidth6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowWidth6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowHeight6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowHeight6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowHeight6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer0_ClipWindowHeight6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR6 - Constant color for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantAlpha6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantAlpha6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantAlpha6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantAlpha6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantBlue6_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantBlue6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantBlue6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantBlue6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantGreen6_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantGreen6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantGreen6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantGreen6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantRed6_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantRed6_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantRed6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR6_pixeng_fetchlayer0_ConstantRed6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY6 - Common properties of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PaletteEnable6_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PaletteEnable6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PaletteEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PaletteEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PaletteEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_TileMode6_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_TileMode6_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode6 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_TileMode6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_TileMode6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaSrcEnable6_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaSrcEnable6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaSrcEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaSrcEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaConstEnable6_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaConstEnable6_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaConstEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaConstEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaTransEnable6_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaTransEnable6_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaTransEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_AlphaTransEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaSrcEnable6_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaSrcEnable6_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaSrcEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaSrcEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaConstEnable6_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaConstEnable6_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaConstEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaConstEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaTransEnable6_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaTransEnable6_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaTransEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_RGBAlphaTransEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PremulConstRGB6_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PremulConstRGB6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PremulConstRGB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_PremulConstRGB6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_YUVConversionMode6_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_YUVConversionMode6_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode6 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_YUVConversionMode6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_YUVConversionMode6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_GammaRemoveEnable6_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_GammaRemoveEnable6_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_GammaRemoveEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_GammaRemoveEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_ClipWindowEnable6_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_ClipWindowEnable6_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_ClipWindowEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_ClipWindowEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_SourceBufferEnable6_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_SourceBufferEnable6_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_SourceBufferEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY6_pixeng_fetchlayer0_SourceBufferEnable6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS7_pixeng_fetchlayer0_BaseAddress7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS7_pixeng_fetchlayer0_BaseAddress7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS7_pixeng_fetchlayer0_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS7_pixeng_fetchlayer0_BaseAddress7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESS7_pixeng_fetchlayer0_BaseAddress7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BASEADDRESSMSB7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB7_pixeng_fetchlayer0_BaseAddressMSB7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB7_pixeng_fetchlayer0_BaseAddressMSB7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB7_pixeng_fetchlayer0_BaseAddressMSB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB7_pixeng_fetchlayer0_BaseAddressMSB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BASEADDRESSMSB7_pixeng_fetchlayer0_BaseAddressMSB7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer0_AutoUpdateBaseAddress7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer0_AutoUpdateBaseAddress7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer0_AutoUpdateBaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer0_AutoUpdateBaseAddress7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer0_AutoUpdateBaseAddress7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer0_AutoUpdateBaseAddressMSB7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7 - Source buffer attributes for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_Stride7_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_Stride7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_Stride7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_Stride7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_Stride7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BitsPerPixel7_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BitsPerPixel7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BitsPerPixel7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BitsPerPixel7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BaseAddressAutoUpdate7_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BaseAddressAutoUpdate7_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BaseAddressAutoUpdate7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BaseAddressAutoUpdate7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_BaseAddressAutoUpdate7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_DWordByteSwap7_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_DWordByteSwap7_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_DWordByteSwap7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_DWordByteSwap7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer0_DWordByteSwap7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7 - Source buffer dimensions of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineWidth7_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineWidth7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineWidth7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineWidth7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineCount7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineCount7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineCount7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer0_LineCount7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsAlpha7_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsAlpha7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsAlpha7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsAlpha7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsBlue7_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsBlue7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsBlue7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsBlue7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsGreen7_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsGreen7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsGreen7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsGreen7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsRed7_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsRed7_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsRed7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ComponentBitsRed7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ITUFormat7_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ITUFormat7_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ITUFormat7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTBITS7_pixeng_fetchlayer0_ITUFormat7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftAlpha7_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftAlpha7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftAlpha7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftAlpha7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftBlue7_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftBlue7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftBlue7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftBlue7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftGreen7_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftGreen7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftGreen7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftGreen7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftRed7_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftRed7_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftRed7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORCOMPONENTSHIFT7_pixeng_fetchlayer0_ComponentShiftRed7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYEROFFSET7 - Position of layer 7 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerXOffset7_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerXOffset7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerXOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerXOffset7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerYOffset7_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerYOffset7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerYOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYEROFFSET7_pixeng_fetchlayer0_LayerYOffset7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowXOffset7_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowXOffset7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowXOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowXOffset7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowYOffset7_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowYOffset7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowYOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWOFFSET7_pixeng_fetchlayer0_ClipWindowYOffset7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowWidth7_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowWidth7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowWidth7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowWidth7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowHeight7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowHeight7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowHeight7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer0_ClipWindowHeight7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONSTANTCOLOR7 - Constant color for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantAlpha7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantAlpha7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantAlpha7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantAlpha7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantBlue7_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantBlue7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantBlue7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantBlue7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantGreen7_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantGreen7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantGreen7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantGreen7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantRed7_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantRed7_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantRed7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONSTANTCOLOR7_pixeng_fetchlayer0_ConstantRed7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_LAYERPROPERTY7 - Common properties of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PaletteEnable7_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PaletteEnable7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PaletteEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PaletteEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PaletteEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_TileMode7_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_TileMode7_SHIFT (4U) /*! pixeng_fetchlayer0_TileMode7 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_TileMode7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_TileMode7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaSrcEnable7_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaSrcEnable7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaSrcEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaSrcEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaConstEnable7_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaConstEnable7_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaConstEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaConstEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaTransEnable7_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaTransEnable7_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaTransEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_AlphaTransEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaSrcEnable7_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaSrcEnable7_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaSrcEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaSrcEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaConstEnable7_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaConstEnable7_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaConstEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaConstEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaTransEnable7_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaTransEnable7_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaTransEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_RGBAlphaTransEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PremulConstRGB7_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PremulConstRGB7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PremulConstRGB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_PremulConstRGB7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_YUVConversionMode7_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_YUVConversionMode7_SHIFT (17U) /*! pixeng_fetchlayer0_YUVConversionMode7 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_YUVConversionMode7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_YUVConversionMode7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_GammaRemoveEnable7_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_GammaRemoveEnable7_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_GammaRemoveEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_GammaRemoveEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_ClipWindowEnable7_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_ClipWindowEnable7_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_ClipWindowEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_ClipWindowEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_SourceBufferEnable7_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_SourceBufferEnable7_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_SourceBufferEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_LAYERPROPERTY7_pixeng_fetchlayer0_SourceBufferEnable7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMEDIMENSIONS_pixeng_fetchlayer0_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FRAMERESAMPLING_pixeng_fetchlayer0_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_PaletteIdxWidth_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_PaletteIdxWidth_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_PaletteIdxWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_PaletteIdxWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipColor_SHIFT (16U) /*! pixeng_fetchlayer0_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipColor_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipLayer_MASK (0x1E0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipLayer_SHIFT (17U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipLayer_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROL_pixeng_fetchlayer0_ClipLayer_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_TRIGGERENABLE - Shadow load enable flags for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq1_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq1_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq2_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq2_SHIFT (2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq3_MASK (0x8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq3_SHIFT (3U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq4_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq4_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq5_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq5_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq6_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq6_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq7_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq7_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_TRIGGERENABLE_pixeng_fetchlayer0_ShdLdReq7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROLTRIGGER_pixeng_fetchlayer0_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROLTRIGGER_pixeng_fetchlayer0_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROLTRIGGER_pixeng_fetchlayer0_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROLTRIGGER_pixeng_fetchlayer0_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CONTROLTRIGGER_pixeng_fetchlayer0_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_START_pixeng_fetchlayer0_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_START_pixeng_fetchlayer0_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_START_pixeng_fetchlayer0_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_START_pixeng_fetchlayer0_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_START_pixeng_fetchlayer0_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FETCHTYPE_pixeng_fetchlayer0_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FETCHTYPE_pixeng_fetchlayer0_FetchType_SHIFT (0U) /*! pixeng_fetchlayer0_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FETCHTYPE_pixeng_fetchlayer0_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FETCHTYPE_pixeng_fetchlayer0_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_FETCHTYPE_pixeng_fetchlayer0_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_BURSTBUFFERPROPERTIES_pixeng_fetchlayer0_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_STATUS_pixeng_fetchlayer0_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS0_pixeng_fetchlayer0_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS0_pixeng_fetchlayer0_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS0_pixeng_fetchlayer0_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS0_pixeng_fetchlayer0_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS0_pixeng_fetchlayer0_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB0_pixeng_fetchlayer0_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB0_pixeng_fetchlayer0_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB0_pixeng_fetchlayer0_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB0_pixeng_fetchlayer0_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB0_pixeng_fetchlayer0_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS1_pixeng_fetchlayer0_CurBaseAddress1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS1_pixeng_fetchlayer0_CurBaseAddress1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS1_pixeng_fetchlayer0_CurBaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS1_pixeng_fetchlayer0_CurBaseAddress1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS1_pixeng_fetchlayer0_CurBaseAddress1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB1 - MSB bits of Current Working BaseAddress for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB1_pixeng_fetchlayer0_CurBaseAddressMSB1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB1_pixeng_fetchlayer0_CurBaseAddressMSB1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB1_pixeng_fetchlayer0_CurBaseAddressMSB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB1_pixeng_fetchlayer0_CurBaseAddressMSB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB1_pixeng_fetchlayer0_CurBaseAddressMSB1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS2_pixeng_fetchlayer0_CurBaseAddress2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS2_pixeng_fetchlayer0_CurBaseAddress2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS2_pixeng_fetchlayer0_CurBaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS2_pixeng_fetchlayer0_CurBaseAddress2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS2_pixeng_fetchlayer0_CurBaseAddress2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB2 - MSB bits of Current Working BaseAddress for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB2_pixeng_fetchlayer0_CurBaseAddressMSB2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB2_pixeng_fetchlayer0_CurBaseAddressMSB2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB2_pixeng_fetchlayer0_CurBaseAddressMSB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB2_pixeng_fetchlayer0_CurBaseAddressMSB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB2_pixeng_fetchlayer0_CurBaseAddressMSB2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS3_pixeng_fetchlayer0_CurBaseAddress3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS3_pixeng_fetchlayer0_CurBaseAddress3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS3_pixeng_fetchlayer0_CurBaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS3_pixeng_fetchlayer0_CurBaseAddress3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS3_pixeng_fetchlayer0_CurBaseAddress3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB3 - MSB bits of Current Working BaseAddress for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB3_pixeng_fetchlayer0_CurBaseAddressMSB3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB3_pixeng_fetchlayer0_CurBaseAddressMSB3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB3_pixeng_fetchlayer0_CurBaseAddressMSB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB3_pixeng_fetchlayer0_CurBaseAddressMSB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB3_pixeng_fetchlayer0_CurBaseAddressMSB3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS4_pixeng_fetchlayer0_CurBaseAddress4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS4_pixeng_fetchlayer0_CurBaseAddress4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS4_pixeng_fetchlayer0_CurBaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS4_pixeng_fetchlayer0_CurBaseAddress4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS4_pixeng_fetchlayer0_CurBaseAddress4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB4 - MSB bits of Current Working BaseAddress for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB4_pixeng_fetchlayer0_CurBaseAddressMSB4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB4_pixeng_fetchlayer0_CurBaseAddressMSB4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB4_pixeng_fetchlayer0_CurBaseAddressMSB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB4_pixeng_fetchlayer0_CurBaseAddressMSB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB4_pixeng_fetchlayer0_CurBaseAddressMSB4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS5_pixeng_fetchlayer0_CurBaseAddress5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS5_pixeng_fetchlayer0_CurBaseAddress5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS5_pixeng_fetchlayer0_CurBaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS5_pixeng_fetchlayer0_CurBaseAddress5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS5_pixeng_fetchlayer0_CurBaseAddress5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB5 - MSB bits of Current Working BaseAddress for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB5_pixeng_fetchlayer0_CurBaseAddressMSB5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB5_pixeng_fetchlayer0_CurBaseAddressMSB5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB5_pixeng_fetchlayer0_CurBaseAddressMSB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB5_pixeng_fetchlayer0_CurBaseAddressMSB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB5_pixeng_fetchlayer0_CurBaseAddressMSB5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS6_pixeng_fetchlayer0_CurBaseAddress6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS6_pixeng_fetchlayer0_CurBaseAddress6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS6_pixeng_fetchlayer0_CurBaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS6_pixeng_fetchlayer0_CurBaseAddress6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS6_pixeng_fetchlayer0_CurBaseAddress6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB6 - MSB bits of Current Working BaseAddress for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB6_pixeng_fetchlayer0_CurBaseAddressMSB6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB6_pixeng_fetchlayer0_CurBaseAddressMSB6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB6_pixeng_fetchlayer0_CurBaseAddressMSB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB6_pixeng_fetchlayer0_CurBaseAddressMSB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB6_pixeng_fetchlayer0_CurBaseAddressMSB6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS7_pixeng_fetchlayer0_CurBaseAddress7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS7_pixeng_fetchlayer0_CurBaseAddress7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS7_pixeng_fetchlayer0_CurBaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS7_pixeng_fetchlayer0_CurBaseAddress7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESS7_pixeng_fetchlayer0_CurBaseAddress7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_CURBASEADDRESSMSB7 - MSB bits of Current Working BaseAddress for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB7_pixeng_fetchlayer0_CurBaseAddressMSB7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB7_pixeng_fetchlayer0_CurBaseAddressMSB7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB7_pixeng_fetchlayer0_CurBaseAddressMSB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB7_pixeng_fetchlayer0_CurBaseAddressMSB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_CURBASEADDRESSMSB7_pixeng_fetchlayer0_CurBaseAddressMSB7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus1_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus1_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus2_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus2_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus3_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus3_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus4_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus4_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus5_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus5_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus6_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus6_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus7_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus7_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_HIDDENSTATUS_pixeng_fetchlayer0_ShadowStatus7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0_COLORPALETTE - Color palette look up table. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORPALETTE_pixeng_fetchlayer0_ColorPalette_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORPALETTE_pixeng_fetchlayer0_ColorPalette_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORPALETTE_pixeng_fetchlayer0_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORPALETTE_pixeng_fetchlayer0_ColorPalette_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORPALETTE_pixeng_fetchlayer0_ColorPalette_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORPALETTE */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0_COLORPALETTE_COUNT (256U) /*! @name PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0cfg_fetchlayer0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0cfg_fetchlayer0_LockUnlock_SHIFT (0U) /*! pixeng_fetchlayer0cfg_fetchlayer0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0cfg_fetchlayer0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0cfg_fetchlayer0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKUNLOCK_pixeng_fetchlayer0cfg_fetchlayer0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_LOCKSTATUS_pixeng_fetchlayer0cfg_fetchlayer0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER0CFG_FETCHLAYER0_STATUS - Status information for pixel engine configuration of fetchlayer0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_STATUS_pixeng_fetchlayer0cfg_fetchlayer0_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_STATUS_pixeng_fetchlayer0cfg_fetchlayer0_sel_SHIFT (16U) /*! pixeng_fetchlayer0cfg_fetchlayer0_sel * 0b000..fetchlayer0 module is not used * 0b001..fetchlayer0 module is used from store9 processing path * 0b010..fetchlayer0 module is used from extdst0 processing path * 0b011..fetchlayer0 module is used from extdst4 processing path * 0b100..fetchlayer0 module is used from extdst1 processing path * 0b101..fetchlayer0 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_STATUS_pixeng_fetchlayer0cfg_fetchlayer0_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_STATUS_pixeng_fetchlayer0cfg_fetchlayer0_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER0CFG_FETCHLAYER0_STATUS_pixeng_fetchlayer0cfg_fetchlayer0_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1_LockUnlock_SHIFT (0U) /*! pixeng_fetchlayer1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATICCONTROL_pixeng_fetchlayer1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATICCONTROL_pixeng_fetchlayer1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATICCONTROL_pixeng_fetchlayer1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATICCONTROL_pixeng_fetchlayer1_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATICCONTROL_pixeng_fetchlayer1_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SHDLDREQCONTROL - Shadow load request flags for each layer. Static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky1_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky1_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky2_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky2_SHIFT (2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky3_MASK (0x8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky3_SHIFT (3U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky4_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky4_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky5_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky5_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky6_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky6_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky7_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky7_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SHDLDREQCONTROL_pixeng_fetchlayer1_ShdLdReqSticky7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERMANAGEMENT_pixeng_fetchlayer1_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS0_pixeng_fetchlayer1_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS0_pixeng_fetchlayer1_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS0_pixeng_fetchlayer1_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS0_pixeng_fetchlayer1_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS0_pixeng_fetchlayer1_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB0_pixeng_fetchlayer1_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB0_pixeng_fetchlayer1_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB0_pixeng_fetchlayer1_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB0_pixeng_fetchlayer1_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB0_pixeng_fetchlayer1_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer1_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer1_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer1_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer1_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS0_pixeng_fetchlayer1_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchlayer1_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION0_pixeng_fetchlayer1_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS0_pixeng_fetchlayer1_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT0_pixeng_fetchlayer1_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET0_pixeng_fetchlayer1_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET0_pixeng_fetchlayer1_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS0_pixeng_fetchlayer1_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR0_pixeng_fetchlayer1_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PaletteEnable0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PaletteEnable0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PaletteEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PaletteEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_TileMode0_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY0_pixeng_fetchlayer1_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS1_pixeng_fetchlayer1_BaseAddress1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS1_pixeng_fetchlayer1_BaseAddress1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS1_pixeng_fetchlayer1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS1_pixeng_fetchlayer1_BaseAddress1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS1_pixeng_fetchlayer1_BaseAddress1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB1_pixeng_fetchlayer1_BaseAddressMSB1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB1_pixeng_fetchlayer1_BaseAddressMSB1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB1_pixeng_fetchlayer1_BaseAddressMSB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB1_pixeng_fetchlayer1_BaseAddressMSB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB1_pixeng_fetchlayer1_BaseAddressMSB1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer1_AutoUpdateBaseAddress1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer1_AutoUpdateBaseAddress1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer1_AutoUpdateBaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer1_AutoUpdateBaseAddress1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS1_pixeng_fetchlayer1_AutoUpdateBaseAddress1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB1_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_Stride1_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_Stride1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_Stride1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_Stride1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BitsPerPixel1_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BitsPerPixel1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BitsPerPixel1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BitsPerPixel1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BaseAddressAutoUpdate1_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BaseAddressAutoUpdate1_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BaseAddressAutoUpdate1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BaseAddressAutoUpdate1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_BaseAddressAutoUpdate1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_DWordByteSwap1_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_DWordByteSwap1_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_DWordByteSwap1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_DWordByteSwap1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES1_pixeng_fetchlayer1_DWordByteSwap1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineWidth1_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineWidth1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineWidth1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineWidth1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineCount1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineCount1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineCount1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION1_pixeng_fetchlayer1_LineCount1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsAlpha1_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsAlpha1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsAlpha1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsAlpha1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsBlue1_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsBlue1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsBlue1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsBlue1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsGreen1_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsGreen1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsGreen1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsGreen1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsRed1_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsRed1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsRed1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ComponentBitsRed1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ITUFormat1_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ITUFormat1_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ITUFormat1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS1_pixeng_fetchlayer1_ITUFormat1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftAlpha1_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftAlpha1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftAlpha1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftAlpha1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftBlue1_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftBlue1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftBlue1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftBlue1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftGreen1_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftGreen1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftGreen1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftGreen1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftRed1_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftRed1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftRed1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT1_pixeng_fetchlayer1_ComponentShiftRed1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET1 - Position of layer 1 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerXOffset1_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerXOffset1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerXOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerXOffset1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerYOffset1_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerYOffset1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerYOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET1_pixeng_fetchlayer1_LayerYOffset1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowXOffset1_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowXOffset1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowXOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowXOffset1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowYOffset1_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowYOffset1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowYOffset1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET1_pixeng_fetchlayer1_ClipWindowYOffset1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowWidth1_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowWidth1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowWidth1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowWidth1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowHeight1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowHeight1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowHeight1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS1_pixeng_fetchlayer1_ClipWindowHeight1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR1 - Constant color for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantAlpha1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantAlpha1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantAlpha1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantAlpha1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantBlue1_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantBlue1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantBlue1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantBlue1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantGreen1_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantGreen1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantGreen1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantGreen1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantRed1_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantRed1_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantRed1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR1_pixeng_fetchlayer1_ConstantRed1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY1 - Common properties of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PaletteEnable1_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PaletteEnable1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PaletteEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PaletteEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PaletteEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_TileMode1_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_TileMode1_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode1 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_TileMode1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_TileMode1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaSrcEnable1_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaSrcEnable1_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaSrcEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaSrcEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaConstEnable1_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaConstEnable1_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaConstEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaConstEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaTransEnable1_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaTransEnable1_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaTransEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_AlphaTransEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaSrcEnable1_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaSrcEnable1_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaSrcEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaSrcEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaConstEnable1_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaConstEnable1_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaConstEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaConstEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaTransEnable1_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaTransEnable1_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaTransEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_RGBAlphaTransEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PremulConstRGB1_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PremulConstRGB1_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PremulConstRGB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_PremulConstRGB1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_YUVConversionMode1_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_YUVConversionMode1_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode1 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_YUVConversionMode1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_YUVConversionMode1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_GammaRemoveEnable1_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_GammaRemoveEnable1_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_GammaRemoveEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_GammaRemoveEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_ClipWindowEnable1_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_ClipWindowEnable1_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_ClipWindowEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_ClipWindowEnable1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_SourceBufferEnable1_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_SourceBufferEnable1_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_SourceBufferEnable1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY1_pixeng_fetchlayer1_SourceBufferEnable1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS2_pixeng_fetchlayer1_BaseAddress2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS2_pixeng_fetchlayer1_BaseAddress2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS2_pixeng_fetchlayer1_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS2_pixeng_fetchlayer1_BaseAddress2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS2_pixeng_fetchlayer1_BaseAddress2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB2_pixeng_fetchlayer1_BaseAddressMSB2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB2_pixeng_fetchlayer1_BaseAddressMSB2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB2_pixeng_fetchlayer1_BaseAddressMSB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB2_pixeng_fetchlayer1_BaseAddressMSB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB2_pixeng_fetchlayer1_BaseAddressMSB2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer1_AutoUpdateBaseAddress2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer1_AutoUpdateBaseAddress2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer1_AutoUpdateBaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer1_AutoUpdateBaseAddress2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS2_pixeng_fetchlayer1_AutoUpdateBaseAddress2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB2_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_Stride2_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_Stride2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_Stride2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_Stride2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_Stride2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BitsPerPixel2_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BitsPerPixel2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BitsPerPixel2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BitsPerPixel2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BaseAddressAutoUpdate2_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BaseAddressAutoUpdate2_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BaseAddressAutoUpdate2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BaseAddressAutoUpdate2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_BaseAddressAutoUpdate2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_DWordByteSwap2_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_DWordByteSwap2_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_DWordByteSwap2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_DWordByteSwap2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES2_pixeng_fetchlayer1_DWordByteSwap2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2 - Source buffer dimensions of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineWidth2_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineWidth2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineWidth2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineWidth2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineCount2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineCount2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineCount2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION2_pixeng_fetchlayer1_LineCount2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsAlpha2_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsAlpha2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsAlpha2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsAlpha2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsBlue2_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsBlue2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsBlue2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsBlue2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsGreen2_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsGreen2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsGreen2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsGreen2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsRed2_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsRed2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsRed2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ComponentBitsRed2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ITUFormat2_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ITUFormat2_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ITUFormat2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS2_pixeng_fetchlayer1_ITUFormat2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftAlpha2_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftAlpha2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftAlpha2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftAlpha2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftBlue2_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftBlue2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftBlue2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftBlue2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftGreen2_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftGreen2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftGreen2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftGreen2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftRed2_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftRed2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftRed2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT2_pixeng_fetchlayer1_ComponentShiftRed2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET2 - Position of layer 2 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerXOffset2_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerXOffset2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerXOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerXOffset2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerYOffset2_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerYOffset2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerYOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET2_pixeng_fetchlayer1_LayerYOffset2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowXOffset2_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowXOffset2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowXOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowXOffset2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowYOffset2_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowYOffset2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowYOffset2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET2_pixeng_fetchlayer1_ClipWindowYOffset2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowWidth2_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowWidth2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowWidth2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowWidth2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowHeight2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowHeight2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowHeight2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS2_pixeng_fetchlayer1_ClipWindowHeight2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR2 - Constant color for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantAlpha2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantAlpha2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantAlpha2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantAlpha2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantBlue2_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantBlue2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantBlue2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantBlue2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantGreen2_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantGreen2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantGreen2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantGreen2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantRed2_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantRed2_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantRed2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR2_pixeng_fetchlayer1_ConstantRed2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY2 - Common properties of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PaletteEnable2_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PaletteEnable2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PaletteEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PaletteEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PaletteEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_TileMode2_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_TileMode2_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode2 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_TileMode2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_TileMode2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaSrcEnable2_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaSrcEnable2_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaSrcEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaSrcEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaConstEnable2_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaConstEnable2_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaConstEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaConstEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaTransEnable2_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaTransEnable2_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaTransEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_AlphaTransEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaSrcEnable2_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaSrcEnable2_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaSrcEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaSrcEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaConstEnable2_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaConstEnable2_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaConstEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaConstEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaTransEnable2_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaTransEnable2_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaTransEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_RGBAlphaTransEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PremulConstRGB2_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PremulConstRGB2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PremulConstRGB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_PremulConstRGB2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_YUVConversionMode2_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_YUVConversionMode2_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode2 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_YUVConversionMode2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_YUVConversionMode2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_GammaRemoveEnable2_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_GammaRemoveEnable2_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_GammaRemoveEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_GammaRemoveEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_ClipWindowEnable2_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_ClipWindowEnable2_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_ClipWindowEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_ClipWindowEnable2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_SourceBufferEnable2_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_SourceBufferEnable2_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_SourceBufferEnable2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY2_pixeng_fetchlayer1_SourceBufferEnable2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS3_pixeng_fetchlayer1_BaseAddress3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS3_pixeng_fetchlayer1_BaseAddress3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS3_pixeng_fetchlayer1_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS3_pixeng_fetchlayer1_BaseAddress3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS3_pixeng_fetchlayer1_BaseAddress3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB3_pixeng_fetchlayer1_BaseAddressMSB3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB3_pixeng_fetchlayer1_BaseAddressMSB3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB3_pixeng_fetchlayer1_BaseAddressMSB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB3_pixeng_fetchlayer1_BaseAddressMSB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB3_pixeng_fetchlayer1_BaseAddressMSB3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer1_AutoUpdateBaseAddress3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer1_AutoUpdateBaseAddress3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer1_AutoUpdateBaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer1_AutoUpdateBaseAddress3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS3_pixeng_fetchlayer1_AutoUpdateBaseAddress3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB3_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_Stride3_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_Stride3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_Stride3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_Stride3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_Stride3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BitsPerPixel3_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BitsPerPixel3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BitsPerPixel3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BitsPerPixel3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BaseAddressAutoUpdate3_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BaseAddressAutoUpdate3_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BaseAddressAutoUpdate3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BaseAddressAutoUpdate3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_BaseAddressAutoUpdate3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_DWordByteSwap3_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_DWordByteSwap3_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_DWordByteSwap3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_DWordByteSwap3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES3_pixeng_fetchlayer1_DWordByteSwap3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3 - Source buffer dimensions of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineWidth3_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineWidth3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineWidth3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineWidth3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineCount3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineCount3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineCount3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION3_pixeng_fetchlayer1_LineCount3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsAlpha3_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsAlpha3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsAlpha3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsAlpha3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsBlue3_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsBlue3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsBlue3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsBlue3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsGreen3_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsGreen3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsGreen3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsGreen3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsRed3_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsRed3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsRed3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ComponentBitsRed3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ITUFormat3_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ITUFormat3_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ITUFormat3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS3_pixeng_fetchlayer1_ITUFormat3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftAlpha3_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftAlpha3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftAlpha3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftAlpha3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftBlue3_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftBlue3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftBlue3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftBlue3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftGreen3_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftGreen3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftGreen3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftGreen3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftRed3_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftRed3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftRed3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT3_pixeng_fetchlayer1_ComponentShiftRed3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET3 - Position of layer 3 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerXOffset3_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerXOffset3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerXOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerXOffset3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerYOffset3_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerYOffset3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerYOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET3_pixeng_fetchlayer1_LayerYOffset3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowXOffset3_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowXOffset3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowXOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowXOffset3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowYOffset3_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowYOffset3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowYOffset3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET3_pixeng_fetchlayer1_ClipWindowYOffset3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowWidth3_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowWidth3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowWidth3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowWidth3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowHeight3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowHeight3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowHeight3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS3_pixeng_fetchlayer1_ClipWindowHeight3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR3 - Constant color for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantAlpha3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantAlpha3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantAlpha3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantAlpha3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantBlue3_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantBlue3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantBlue3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantBlue3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantGreen3_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantGreen3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantGreen3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantGreen3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantRed3_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantRed3_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantRed3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR3_pixeng_fetchlayer1_ConstantRed3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY3 - Common properties of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PaletteEnable3_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PaletteEnable3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PaletteEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PaletteEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PaletteEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_TileMode3_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_TileMode3_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode3 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_TileMode3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_TileMode3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaSrcEnable3_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaSrcEnable3_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaSrcEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaSrcEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaConstEnable3_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaConstEnable3_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaConstEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaConstEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaTransEnable3_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaTransEnable3_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaTransEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_AlphaTransEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaSrcEnable3_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaSrcEnable3_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaSrcEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaSrcEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaConstEnable3_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaConstEnable3_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaConstEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaConstEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaTransEnable3_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaTransEnable3_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaTransEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_RGBAlphaTransEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PremulConstRGB3_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PremulConstRGB3_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PremulConstRGB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_PremulConstRGB3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_YUVConversionMode3_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_YUVConversionMode3_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode3 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_YUVConversionMode3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_YUVConversionMode3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_GammaRemoveEnable3_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_GammaRemoveEnable3_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_GammaRemoveEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_GammaRemoveEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_ClipWindowEnable3_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_ClipWindowEnable3_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_ClipWindowEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_ClipWindowEnable3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_SourceBufferEnable3_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_SourceBufferEnable3_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_SourceBufferEnable3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY3_pixeng_fetchlayer1_SourceBufferEnable3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS4_pixeng_fetchlayer1_BaseAddress4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS4_pixeng_fetchlayer1_BaseAddress4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS4_pixeng_fetchlayer1_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS4_pixeng_fetchlayer1_BaseAddress4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS4_pixeng_fetchlayer1_BaseAddress4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB4_pixeng_fetchlayer1_BaseAddressMSB4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB4_pixeng_fetchlayer1_BaseAddressMSB4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB4_pixeng_fetchlayer1_BaseAddressMSB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB4_pixeng_fetchlayer1_BaseAddressMSB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB4_pixeng_fetchlayer1_BaseAddressMSB4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer1_AutoUpdateBaseAddress4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer1_AutoUpdateBaseAddress4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer1_AutoUpdateBaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer1_AutoUpdateBaseAddress4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS4_pixeng_fetchlayer1_AutoUpdateBaseAddress4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB4_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_Stride4_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_Stride4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_Stride4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_Stride4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_Stride4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BitsPerPixel4_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BitsPerPixel4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BitsPerPixel4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BitsPerPixel4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BaseAddressAutoUpdate4_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BaseAddressAutoUpdate4_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BaseAddressAutoUpdate4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BaseAddressAutoUpdate4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_BaseAddressAutoUpdate4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_DWordByteSwap4_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_DWordByteSwap4_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_DWordByteSwap4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_DWordByteSwap4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES4_pixeng_fetchlayer1_DWordByteSwap4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4 - Source buffer dimensions of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineWidth4_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineWidth4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineWidth4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineWidth4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineCount4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineCount4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineCount4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION4_pixeng_fetchlayer1_LineCount4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsAlpha4_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsAlpha4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsAlpha4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsAlpha4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsBlue4_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsBlue4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsBlue4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsBlue4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsGreen4_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsGreen4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsGreen4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsGreen4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsRed4_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsRed4_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsRed4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ComponentBitsRed4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ITUFormat4_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ITUFormat4_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ITUFormat4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS4_pixeng_fetchlayer1_ITUFormat4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftAlpha4_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftAlpha4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftAlpha4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftAlpha4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftBlue4_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftBlue4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftBlue4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftBlue4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftGreen4_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftGreen4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftGreen4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftGreen4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftRed4_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftRed4_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftRed4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT4_pixeng_fetchlayer1_ComponentShiftRed4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET4 - Position of layer 4 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerXOffset4_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerXOffset4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerXOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerXOffset4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerYOffset4_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerYOffset4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerYOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET4_pixeng_fetchlayer1_LayerYOffset4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowXOffset4_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowXOffset4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowXOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowXOffset4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowYOffset4_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowYOffset4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowYOffset4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET4_pixeng_fetchlayer1_ClipWindowYOffset4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowWidth4_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowWidth4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowWidth4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowWidth4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowHeight4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowHeight4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowHeight4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS4_pixeng_fetchlayer1_ClipWindowHeight4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR4 - Constant color for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantAlpha4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantAlpha4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantAlpha4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantAlpha4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantBlue4_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantBlue4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantBlue4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantBlue4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantGreen4_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantGreen4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantGreen4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantGreen4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantRed4_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantRed4_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantRed4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR4_pixeng_fetchlayer1_ConstantRed4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY4 - Common properties of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PaletteEnable4_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PaletteEnable4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PaletteEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PaletteEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PaletteEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_TileMode4_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_TileMode4_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode4 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_TileMode4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_TileMode4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaSrcEnable4_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaSrcEnable4_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaSrcEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaSrcEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaConstEnable4_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaConstEnable4_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaConstEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaConstEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaTransEnable4_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaTransEnable4_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaTransEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_AlphaTransEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaSrcEnable4_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaSrcEnable4_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaSrcEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaSrcEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaConstEnable4_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaConstEnable4_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaConstEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaConstEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaTransEnable4_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaTransEnable4_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaTransEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_RGBAlphaTransEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PremulConstRGB4_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PremulConstRGB4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PremulConstRGB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_PremulConstRGB4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_YUVConversionMode4_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_YUVConversionMode4_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode4 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_YUVConversionMode4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_YUVConversionMode4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_GammaRemoveEnable4_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_GammaRemoveEnable4_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_GammaRemoveEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_GammaRemoveEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_ClipWindowEnable4_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_ClipWindowEnable4_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_ClipWindowEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_ClipWindowEnable4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_SourceBufferEnable4_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_SourceBufferEnable4_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_SourceBufferEnable4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY4_pixeng_fetchlayer1_SourceBufferEnable4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS5_pixeng_fetchlayer1_BaseAddress5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS5_pixeng_fetchlayer1_BaseAddress5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS5_pixeng_fetchlayer1_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS5_pixeng_fetchlayer1_BaseAddress5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS5_pixeng_fetchlayer1_BaseAddress5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB5_pixeng_fetchlayer1_BaseAddressMSB5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB5_pixeng_fetchlayer1_BaseAddressMSB5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB5_pixeng_fetchlayer1_BaseAddressMSB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB5_pixeng_fetchlayer1_BaseAddressMSB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB5_pixeng_fetchlayer1_BaseAddressMSB5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer1_AutoUpdateBaseAddress5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer1_AutoUpdateBaseAddress5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer1_AutoUpdateBaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer1_AutoUpdateBaseAddress5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS5_pixeng_fetchlayer1_AutoUpdateBaseAddress5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB5_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_Stride5_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_Stride5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_Stride5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_Stride5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_Stride5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BitsPerPixel5_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BitsPerPixel5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BitsPerPixel5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BitsPerPixel5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BaseAddressAutoUpdate5_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BaseAddressAutoUpdate5_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BaseAddressAutoUpdate5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BaseAddressAutoUpdate5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_BaseAddressAutoUpdate5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_DWordByteSwap5_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_DWordByteSwap5_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_DWordByteSwap5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_DWordByteSwap5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES5_pixeng_fetchlayer1_DWordByteSwap5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5 - Source buffer dimensions of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineWidth5_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineWidth5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineWidth5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineWidth5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineCount5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineCount5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineCount5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION5_pixeng_fetchlayer1_LineCount5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsAlpha5_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsAlpha5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsAlpha5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsAlpha5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsBlue5_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsBlue5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsBlue5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsBlue5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsGreen5_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsGreen5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsGreen5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsGreen5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsRed5_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsRed5_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsRed5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ComponentBitsRed5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ITUFormat5_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ITUFormat5_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ITUFormat5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS5_pixeng_fetchlayer1_ITUFormat5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftAlpha5_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftAlpha5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftAlpha5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftAlpha5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftBlue5_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftBlue5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftBlue5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftBlue5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftGreen5_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftGreen5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftGreen5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftGreen5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftRed5_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftRed5_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftRed5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT5_pixeng_fetchlayer1_ComponentShiftRed5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET5 - Position of layer 5 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerXOffset5_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerXOffset5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerXOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerXOffset5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerYOffset5_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerYOffset5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerYOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET5_pixeng_fetchlayer1_LayerYOffset5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowXOffset5_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowXOffset5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowXOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowXOffset5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowYOffset5_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowYOffset5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowYOffset5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET5_pixeng_fetchlayer1_ClipWindowYOffset5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowWidth5_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowWidth5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowWidth5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowWidth5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowHeight5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowHeight5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowHeight5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS5_pixeng_fetchlayer1_ClipWindowHeight5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR5 - Constant color for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantAlpha5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantAlpha5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantAlpha5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantAlpha5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantBlue5_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantBlue5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantBlue5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantBlue5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantGreen5_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantGreen5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantGreen5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantGreen5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantRed5_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantRed5_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantRed5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR5_pixeng_fetchlayer1_ConstantRed5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY5 - Common properties of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PaletteEnable5_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PaletteEnable5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PaletteEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PaletteEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PaletteEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_TileMode5_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_TileMode5_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode5 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_TileMode5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_TileMode5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaSrcEnable5_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaSrcEnable5_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaSrcEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaSrcEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaConstEnable5_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaConstEnable5_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaConstEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaConstEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaTransEnable5_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaTransEnable5_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaTransEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_AlphaTransEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaSrcEnable5_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaSrcEnable5_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaSrcEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaSrcEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaConstEnable5_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaConstEnable5_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaConstEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaConstEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaTransEnable5_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaTransEnable5_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaTransEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_RGBAlphaTransEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PremulConstRGB5_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PremulConstRGB5_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PremulConstRGB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_PremulConstRGB5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_YUVConversionMode5_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_YUVConversionMode5_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode5 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_YUVConversionMode5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_YUVConversionMode5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_GammaRemoveEnable5_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_GammaRemoveEnable5_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_GammaRemoveEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_GammaRemoveEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_ClipWindowEnable5_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_ClipWindowEnable5_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_ClipWindowEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_ClipWindowEnable5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_SourceBufferEnable5_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_SourceBufferEnable5_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_SourceBufferEnable5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY5_pixeng_fetchlayer1_SourceBufferEnable5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS6_pixeng_fetchlayer1_BaseAddress6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS6_pixeng_fetchlayer1_BaseAddress6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS6_pixeng_fetchlayer1_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS6_pixeng_fetchlayer1_BaseAddress6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS6_pixeng_fetchlayer1_BaseAddress6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB6_pixeng_fetchlayer1_BaseAddressMSB6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB6_pixeng_fetchlayer1_BaseAddressMSB6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB6_pixeng_fetchlayer1_BaseAddressMSB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB6_pixeng_fetchlayer1_BaseAddressMSB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB6_pixeng_fetchlayer1_BaseAddressMSB6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer1_AutoUpdateBaseAddress6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer1_AutoUpdateBaseAddress6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer1_AutoUpdateBaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer1_AutoUpdateBaseAddress6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS6_pixeng_fetchlayer1_AutoUpdateBaseAddress6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB6_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_Stride6_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_Stride6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_Stride6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_Stride6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_Stride6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BitsPerPixel6_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BitsPerPixel6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BitsPerPixel6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BitsPerPixel6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BaseAddressAutoUpdate6_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BaseAddressAutoUpdate6_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BaseAddressAutoUpdate6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BaseAddressAutoUpdate6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_BaseAddressAutoUpdate6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_DWordByteSwap6_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_DWordByteSwap6_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_DWordByteSwap6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_DWordByteSwap6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES6_pixeng_fetchlayer1_DWordByteSwap6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6 - Source buffer dimensions of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineWidth6_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineWidth6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineWidth6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineWidth6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineCount6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineCount6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineCount6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION6_pixeng_fetchlayer1_LineCount6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsAlpha6_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsAlpha6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsAlpha6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsAlpha6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsBlue6_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsBlue6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsBlue6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsBlue6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsGreen6_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsGreen6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsGreen6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsGreen6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsRed6_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsRed6_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsRed6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ComponentBitsRed6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ITUFormat6_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ITUFormat6_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ITUFormat6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS6_pixeng_fetchlayer1_ITUFormat6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftAlpha6_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftAlpha6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftAlpha6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftAlpha6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftBlue6_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftBlue6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftBlue6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftBlue6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftGreen6_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftGreen6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftGreen6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftGreen6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftRed6_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftRed6_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftRed6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT6_pixeng_fetchlayer1_ComponentShiftRed6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET6 - Position of layer 6 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerXOffset6_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerXOffset6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerXOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerXOffset6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerYOffset6_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerYOffset6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerYOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET6_pixeng_fetchlayer1_LayerYOffset6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowXOffset6_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowXOffset6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowXOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowXOffset6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowYOffset6_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowYOffset6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowYOffset6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET6_pixeng_fetchlayer1_ClipWindowYOffset6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowWidth6_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowWidth6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowWidth6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowWidth6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowHeight6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowHeight6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowHeight6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS6_pixeng_fetchlayer1_ClipWindowHeight6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR6 - Constant color for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantAlpha6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantAlpha6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantAlpha6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantAlpha6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantBlue6_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantBlue6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantBlue6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantBlue6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantGreen6_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantGreen6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantGreen6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantGreen6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantRed6_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantRed6_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantRed6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR6_pixeng_fetchlayer1_ConstantRed6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY6 - Common properties of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PaletteEnable6_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PaletteEnable6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PaletteEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PaletteEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PaletteEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_TileMode6_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_TileMode6_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode6 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_TileMode6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_TileMode6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaSrcEnable6_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaSrcEnable6_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaSrcEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaSrcEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaConstEnable6_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaConstEnable6_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaConstEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaConstEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaTransEnable6_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaTransEnable6_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaTransEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_AlphaTransEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaSrcEnable6_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaSrcEnable6_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaSrcEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaSrcEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaConstEnable6_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaConstEnable6_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaConstEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaConstEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaTransEnable6_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaTransEnable6_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaTransEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_RGBAlphaTransEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PremulConstRGB6_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PremulConstRGB6_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PremulConstRGB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_PremulConstRGB6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_YUVConversionMode6_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_YUVConversionMode6_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode6 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_YUVConversionMode6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_YUVConversionMode6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_GammaRemoveEnable6_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_GammaRemoveEnable6_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_GammaRemoveEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_GammaRemoveEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_ClipWindowEnable6_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_ClipWindowEnable6_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_ClipWindowEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_ClipWindowEnable6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_SourceBufferEnable6_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_SourceBufferEnable6_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_SourceBufferEnable6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY6_pixeng_fetchlayer1_SourceBufferEnable6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS7_pixeng_fetchlayer1_BaseAddress7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS7_pixeng_fetchlayer1_BaseAddress7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS7_pixeng_fetchlayer1_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS7_pixeng_fetchlayer1_BaseAddress7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESS7_pixeng_fetchlayer1_BaseAddress7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BASEADDRESSMSB7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB7_pixeng_fetchlayer1_BaseAddressMSB7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB7_pixeng_fetchlayer1_BaseAddressMSB7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB7_pixeng_fetchlayer1_BaseAddressMSB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB7_pixeng_fetchlayer1_BaseAddressMSB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BASEADDRESSMSB7_pixeng_fetchlayer1_BaseAddressMSB7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer1_AutoUpdateBaseAddress7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer1_AutoUpdateBaseAddress7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer1_AutoUpdateBaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer1_AutoUpdateBaseAddress7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESS7_pixeng_fetchlayer1_AutoUpdateBaseAddress7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_AUTOUPDATEBASEADDRESSMSB7_pixeng_fetchlayer1_AutoUpdateBaseAddressMSB7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7 - Source buffer attributes for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_Stride7_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_Stride7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_Stride7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_Stride7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_Stride7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BitsPerPixel7_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BitsPerPixel7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BitsPerPixel7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BitsPerPixel7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BaseAddressAutoUpdate7_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BaseAddressAutoUpdate7_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BaseAddressAutoUpdate7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BaseAddressAutoUpdate7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_BaseAddressAutoUpdate7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_DWordByteSwap7_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_DWordByteSwap7_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_DWordByteSwap7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_DWordByteSwap7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERATTRIBUTES7_pixeng_fetchlayer1_DWordByteSwap7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7 - Source buffer dimensions of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineWidth7_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineWidth7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineWidth7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineWidth7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineCount7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineCount7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineCount7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_SOURCEBUFFERDIMENSION7_pixeng_fetchlayer1_LineCount7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsAlpha7_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsAlpha7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsAlpha7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsAlpha7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsBlue7_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsBlue7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsBlue7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsBlue7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsGreen7_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsGreen7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsGreen7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsGreen7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsRed7_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsRed7_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsRed7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ComponentBitsRed7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ITUFormat7_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ITUFormat7_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ITUFormat7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTBITS7_pixeng_fetchlayer1_ITUFormat7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftAlpha7_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftAlpha7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftAlpha7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftAlpha7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftBlue7_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftBlue7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftBlue7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftBlue7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftGreen7_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftGreen7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftGreen7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftGreen7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftRed7_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftRed7_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftRed7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORCOMPONENTSHIFT7_pixeng_fetchlayer1_ComponentShiftRed7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYEROFFSET7 - Position of layer 7 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerXOffset7_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerXOffset7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerXOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerXOffset7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerYOffset7_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerYOffset7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerYOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYEROFFSET7_pixeng_fetchlayer1_LayerYOffset7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowXOffset7_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowXOffset7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowXOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowXOffset7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowYOffset7_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowYOffset7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowYOffset7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWOFFSET7_pixeng_fetchlayer1_ClipWindowYOffset7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowWidth7_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowWidth7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowWidth7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowWidth7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowHeight7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowHeight7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowHeight7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CLIPWINDOWDIMENSIONS7_pixeng_fetchlayer1_ClipWindowHeight7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONSTANTCOLOR7 - Constant color for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantAlpha7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantAlpha7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantAlpha7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantAlpha7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantBlue7_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantBlue7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantBlue7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantBlue7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantGreen7_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantGreen7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantGreen7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantGreen7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantRed7_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantRed7_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantRed7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONSTANTCOLOR7_pixeng_fetchlayer1_ConstantRed7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_LAYERPROPERTY7 - Common properties of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PaletteEnable7_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PaletteEnable7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PaletteEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PaletteEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PaletteEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_TileMode7_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_TileMode7_SHIFT (4U) /*! pixeng_fetchlayer1_TileMode7 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_TileMode7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_TileMode7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaSrcEnable7_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaSrcEnable7_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaSrcEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaSrcEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaConstEnable7_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaConstEnable7_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaConstEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaConstEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaTransEnable7_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaTransEnable7_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaTransEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_AlphaTransEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaSrcEnable7_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaSrcEnable7_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaSrcEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaSrcEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaConstEnable7_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaConstEnable7_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaConstEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaConstEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaTransEnable7_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaTransEnable7_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaTransEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_RGBAlphaTransEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PremulConstRGB7_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PremulConstRGB7_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PremulConstRGB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_PremulConstRGB7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_YUVConversionMode7_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_YUVConversionMode7_SHIFT (17U) /*! pixeng_fetchlayer1_YUVConversionMode7 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_YUVConversionMode7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_YUVConversionMode7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_GammaRemoveEnable7_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_GammaRemoveEnable7_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_GammaRemoveEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_GammaRemoveEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_ClipWindowEnable7_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_ClipWindowEnable7_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_ClipWindowEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_ClipWindowEnable7_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_SourceBufferEnable7_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_SourceBufferEnable7_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_SourceBufferEnable7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_LAYERPROPERTY7_pixeng_fetchlayer1_SourceBufferEnable7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMEDIMENSIONS_pixeng_fetchlayer1_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FRAMERESAMPLING_pixeng_fetchlayer1_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_PaletteIdxWidth_MASK (0x700U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_PaletteIdxWidth_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_PaletteIdxWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_PaletteIdxWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipColor_SHIFT (16U) /*! pixeng_fetchlayer1_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipColor_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipLayer_MASK (0x1E0000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipLayer_SHIFT (17U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipLayer_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROL_pixeng_fetchlayer1_ClipLayer_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_TRIGGERENABLE - Shadow load enable flags for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq1_MASK (0x2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq1_SHIFT (1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq2_MASK (0x4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq2_SHIFT (2U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq3_MASK (0x8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq3_SHIFT (3U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq4_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq4_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq5_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq5_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq6_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq6_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq7_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq7_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_TRIGGERENABLE_pixeng_fetchlayer1_ShdLdReq7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROLTRIGGER_pixeng_fetchlayer1_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROLTRIGGER_pixeng_fetchlayer1_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROLTRIGGER_pixeng_fetchlayer1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROLTRIGGER_pixeng_fetchlayer1_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CONTROLTRIGGER_pixeng_fetchlayer1_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_START_pixeng_fetchlayer1_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_START_pixeng_fetchlayer1_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_START_pixeng_fetchlayer1_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_START_pixeng_fetchlayer1_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_START_pixeng_fetchlayer1_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FETCHTYPE_pixeng_fetchlayer1_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FETCHTYPE_pixeng_fetchlayer1_FetchType_SHIFT (0U) /*! pixeng_fetchlayer1_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FETCHTYPE_pixeng_fetchlayer1_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FETCHTYPE_pixeng_fetchlayer1_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_FETCHTYPE_pixeng_fetchlayer1_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_BURSTBUFFERPROPERTIES_pixeng_fetchlayer1_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_STATUS_pixeng_fetchlayer1_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS0_pixeng_fetchlayer1_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS0_pixeng_fetchlayer1_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS0_pixeng_fetchlayer1_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS0_pixeng_fetchlayer1_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS0_pixeng_fetchlayer1_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB0_pixeng_fetchlayer1_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB0_pixeng_fetchlayer1_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB0_pixeng_fetchlayer1_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB0_pixeng_fetchlayer1_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB0_pixeng_fetchlayer1_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS1 - Source buffer base address of layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS1_pixeng_fetchlayer1_CurBaseAddress1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS1_pixeng_fetchlayer1_CurBaseAddress1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS1_pixeng_fetchlayer1_CurBaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS1_pixeng_fetchlayer1_CurBaseAddress1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS1_pixeng_fetchlayer1_CurBaseAddress1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB1 - MSB bits of Current Working BaseAddress for layer 1. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB1_pixeng_fetchlayer1_CurBaseAddressMSB1_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB1_pixeng_fetchlayer1_CurBaseAddressMSB1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB1_pixeng_fetchlayer1_CurBaseAddressMSB1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB1_pixeng_fetchlayer1_CurBaseAddressMSB1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB1_pixeng_fetchlayer1_CurBaseAddressMSB1_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS2 - Source buffer base address of layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS2_pixeng_fetchlayer1_CurBaseAddress2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS2_pixeng_fetchlayer1_CurBaseAddress2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS2_pixeng_fetchlayer1_CurBaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS2_pixeng_fetchlayer1_CurBaseAddress2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS2_pixeng_fetchlayer1_CurBaseAddress2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB2 - MSB bits of Current Working BaseAddress for layer 2. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB2_pixeng_fetchlayer1_CurBaseAddressMSB2_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB2_pixeng_fetchlayer1_CurBaseAddressMSB2_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB2_pixeng_fetchlayer1_CurBaseAddressMSB2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB2_pixeng_fetchlayer1_CurBaseAddressMSB2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB2_pixeng_fetchlayer1_CurBaseAddressMSB2_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS3 - Source buffer base address of layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS3_pixeng_fetchlayer1_CurBaseAddress3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS3_pixeng_fetchlayer1_CurBaseAddress3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS3_pixeng_fetchlayer1_CurBaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS3_pixeng_fetchlayer1_CurBaseAddress3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS3_pixeng_fetchlayer1_CurBaseAddress3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB3 - MSB bits of Current Working BaseAddress for layer 3. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB3_pixeng_fetchlayer1_CurBaseAddressMSB3_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB3_pixeng_fetchlayer1_CurBaseAddressMSB3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB3_pixeng_fetchlayer1_CurBaseAddressMSB3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB3_pixeng_fetchlayer1_CurBaseAddressMSB3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB3_pixeng_fetchlayer1_CurBaseAddressMSB3_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS4 - Source buffer base address of layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS4_pixeng_fetchlayer1_CurBaseAddress4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS4_pixeng_fetchlayer1_CurBaseAddress4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS4_pixeng_fetchlayer1_CurBaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS4_pixeng_fetchlayer1_CurBaseAddress4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS4_pixeng_fetchlayer1_CurBaseAddress4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB4 - MSB bits of Current Working BaseAddress for layer 4. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB4_pixeng_fetchlayer1_CurBaseAddressMSB4_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB4_pixeng_fetchlayer1_CurBaseAddressMSB4_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB4_pixeng_fetchlayer1_CurBaseAddressMSB4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB4_pixeng_fetchlayer1_CurBaseAddressMSB4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB4_pixeng_fetchlayer1_CurBaseAddressMSB4_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS5 - Source buffer base address of layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS5_pixeng_fetchlayer1_CurBaseAddress5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS5_pixeng_fetchlayer1_CurBaseAddress5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS5_pixeng_fetchlayer1_CurBaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS5_pixeng_fetchlayer1_CurBaseAddress5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS5_pixeng_fetchlayer1_CurBaseAddress5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB5 - MSB bits of Current Working BaseAddress for layer 5. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB5_pixeng_fetchlayer1_CurBaseAddressMSB5_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB5_pixeng_fetchlayer1_CurBaseAddressMSB5_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB5_pixeng_fetchlayer1_CurBaseAddressMSB5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB5_pixeng_fetchlayer1_CurBaseAddressMSB5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB5_pixeng_fetchlayer1_CurBaseAddressMSB5_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS6 - Source buffer base address of layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS6_pixeng_fetchlayer1_CurBaseAddress6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS6_pixeng_fetchlayer1_CurBaseAddress6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS6_pixeng_fetchlayer1_CurBaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS6_pixeng_fetchlayer1_CurBaseAddress6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS6_pixeng_fetchlayer1_CurBaseAddress6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB6 - MSB bits of Current Working BaseAddress for layer 6. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB6_pixeng_fetchlayer1_CurBaseAddressMSB6_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB6_pixeng_fetchlayer1_CurBaseAddressMSB6_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB6_pixeng_fetchlayer1_CurBaseAddressMSB6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB6_pixeng_fetchlayer1_CurBaseAddressMSB6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB6_pixeng_fetchlayer1_CurBaseAddressMSB6_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESS7 - Source buffer base address of layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS7_pixeng_fetchlayer1_CurBaseAddress7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS7_pixeng_fetchlayer1_CurBaseAddress7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS7_pixeng_fetchlayer1_CurBaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS7_pixeng_fetchlayer1_CurBaseAddress7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESS7_pixeng_fetchlayer1_CurBaseAddress7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_CURBASEADDRESSMSB7 - MSB bits of Current Working BaseAddress for layer 7. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB7_pixeng_fetchlayer1_CurBaseAddressMSB7_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB7_pixeng_fetchlayer1_CurBaseAddressMSB7_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB7_pixeng_fetchlayer1_CurBaseAddressMSB7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB7_pixeng_fetchlayer1_CurBaseAddressMSB7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_CURBASEADDRESSMSB7_pixeng_fetchlayer1_CurBaseAddressMSB7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus1_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus1_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus1_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus1_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus2_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus2_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus2_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus2_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus3_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus3_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus3_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus3_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus4_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus4_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus4_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus4_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus5_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus5_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus5_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus5_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus6_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus6_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus6_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus6_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus7_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus7_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus7_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_HIDDENSTATUS_pixeng_fetchlayer1_ShadowStatus7_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1_COLORPALETTE - Color palette look up table. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORPALETTE_pixeng_fetchlayer1_ColorPalette_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORPALETTE_pixeng_fetchlayer1_ColorPalette_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORPALETTE_pixeng_fetchlayer1_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORPALETTE_pixeng_fetchlayer1_ColorPalette_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORPALETTE_pixeng_fetchlayer1_ColorPalette_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORPALETTE */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1_COLORPALETTE_COUNT (256U) /*! @name PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1cfg_fetchlayer1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1cfg_fetchlayer1_LockUnlock_SHIFT (0U) /*! pixeng_fetchlayer1cfg_fetchlayer1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1cfg_fetchlayer1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1cfg_fetchlayer1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKUNLOCK_pixeng_fetchlayer1cfg_fetchlayer1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_LOCKSTATUS_pixeng_fetchlayer1cfg_fetchlayer1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHLAYER1CFG_FETCHLAYER1_STATUS - Status information for pixel engine configuration of fetchlayer1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_STATUS_pixeng_fetchlayer1cfg_fetchlayer1_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_STATUS_pixeng_fetchlayer1cfg_fetchlayer1_sel_SHIFT (16U) /*! pixeng_fetchlayer1cfg_fetchlayer1_sel * 0b000..fetchlayer1 module is not used * 0b001..fetchlayer1 module is used from store9 processing path * 0b010..fetchlayer1 module is used from extdst0 processing path * 0b011..fetchlayer1 module is used from extdst4 processing path * 0b100..fetchlayer1 module is used from extdst1 processing path * 0b101..fetchlayer1 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_STATUS_pixeng_fetchlayer1cfg_fetchlayer1_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_STATUS_pixeng_fetchlayer1cfg_fetchlayer1_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHLAYER1CFG_FETCHLAYER1_STATUS_pixeng_fetchlayer1cfg_fetchlayer1_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv3_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATICCONTROL_pixeng_fetchyuv3_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATICCONTROL_pixeng_fetchyuv3_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATICCONTROL_pixeng_fetchyuv3_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATICCONTROL_pixeng_fetchyuv3_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATICCONTROL_pixeng_fetchyuv3_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv3_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDR0_pixeng_fetchyuv3_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDR0_pixeng_fetchyuv3_RingBufStartAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDR0_pixeng_fetchyuv3_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDR0_pixeng_fetchyuv3_RingBufStartAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDR0_pixeng_fetchyuv3_RingBufStartAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_RINGBUFSTARTADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv3_RingBufStartAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv3_RingBufStartAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv3_RingBufStartAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv3_RingBufStartAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv3_RingBufStartAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDR0_pixeng_fetchyuv3_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDR0_pixeng_fetchyuv3_RingBufWrapAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDR0_pixeng_fetchyuv3_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDR0_pixeng_fetchyuv3_RingBufWrapAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDR0_pixeng_fetchyuv3_RingBufWrapAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_RINGBUFWRAPADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv3_RingBufWrapAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv3_RingBufWrapAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv3_RingBufWrapAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv3_RingBufWrapAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv3_RingBufWrapAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_FRAMEPROPERTIES0 - Frame property setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEPROPERTIES0_pixeng_fetchyuv3_FieldId0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEPROPERTIES0_pixeng_fetchyuv3_FieldId0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEPROPERTIES0_pixeng_fetchyuv3_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEPROPERTIES0_pixeng_fetchyuv3_FieldId0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEPROPERTIES0_pixeng_fetchyuv3_FieldId0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESS0_pixeng_fetchyuv3_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESS0_pixeng_fetchyuv3_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESS0_pixeng_fetchyuv3_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESS0_pixeng_fetchyuv3_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESS0_pixeng_fetchyuv3_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESSMSB0_pixeng_fetchyuv3_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESSMSB0_pixeng_fetchyuv3_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESSMSB0_pixeng_fetchyuv3_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESSMSB0_pixeng_fetchyuv3_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BASEADDRESSMSB0_pixeng_fetchyuv3_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv3_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv3_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv3_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv3_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv3_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv3_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv3_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv3_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv3_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv3_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv3_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv3_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTBITS0_pixeng_fetchyuv3_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_COLORCOMPONENTSHIFT0_pixeng_fetchyuv3_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYEROFFSET0_pixeng_fetchyuv3_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWOFFSET0_pixeng_fetchyuv3_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv3_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONSTANTCOLOR0_pixeng_fetchyuv3_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_TileMode0_SHIFT (4U) /*! pixeng_fetchyuv3_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaMaskEnable0_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaMaskEnable0_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaMaskEnable0_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaMaskEnable0_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchyuv3_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_LAYERPROPERTY0_pixeng_fetchyuv3_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMEDIMENSIONS_pixeng_fetchyuv3_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FRAMERESAMPLING_pixeng_fetchyuv3_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RasterMode_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RasterMode_SHIFT (0U) /*! pixeng_fetchyuv3_RasterMode * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot only] Arbitrary warping (filter is active). Coordinates are read from frame input * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is U. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. * 0b110..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RasterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RasterMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_InputSelect_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_InputSelect_SHIFT (3U) /*! pixeng_fetchyuv3_InputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_InputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_InputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV422UpsamplingMode_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV422UpsamplingMode_SHIFT (5U) /*! pixeng_fetchyuv3_YUV422UpsamplingMode * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV422UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV422UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ChromaHReplEn_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ChromaHReplEn_SHIFT (6U) /*! pixeng_fetchyuv3_ChromaHReplEn * 0b0..Not used. * 0b1..Replicate mode for input samples. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ChromaHReplEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ChromaHReplEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ChromaHReplEn_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_SecInputSelect_MASK (0x1800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_SecInputSelect_SHIFT (11U) /*! pixeng_fetchyuv3_SecInputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_SecInputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_SecInputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_SecInputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV420UpsamplingMode_MASK (0x6000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV420UpsamplingMode_SHIFT (13U) /*! pixeng_fetchyuv3_YUV420UpsamplingMode * 0b00..Not used. * 0b01..Replicate mode for interspersed samples (UV samples between Y samples). * 0b10..Interpolate mode for coaligned samples (UV samples at Y sample positions). * 0b11..Interpolate mode for interspersed interlaced samples (UV samples betwween Y samples). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV420UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV420UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_YUV420UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ClipColor_SHIFT (16U) /*! pixeng_fetchyuv3_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROL_pixeng_fetchyuv3_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROLTRIGGER_pixeng_fetchyuv3_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROLTRIGGER_pixeng_fetchyuv3_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROLTRIGGER_pixeng_fetchyuv3_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROLTRIGGER_pixeng_fetchyuv3_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CONTROLTRIGGER_pixeng_fetchyuv3_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_START_pixeng_fetchyuv3_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_START_pixeng_fetchyuv3_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_START_pixeng_fetchyuv3_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_START_pixeng_fetchyuv3_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_START_pixeng_fetchyuv3_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FETCHTYPE_pixeng_fetchyuv3_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FETCHTYPE_pixeng_fetchyuv3_FetchType_SHIFT (0U) /*! pixeng_fetchyuv3_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_FETCHTYPE_pixeng_fetchyuv3_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_FETCHTYPE_pixeng_fetchyuv3_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_FETCHTYPE_pixeng_fetchyuv3_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_READADDRESS0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESS0_pixeng_fetchyuv3_ReadAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESS0_pixeng_fetchyuv3_ReadAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESS0_pixeng_fetchyuv3_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESS0_pixeng_fetchyuv3_ReadAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESS0_pixeng_fetchyuv3_ReadAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_READADDRESSMSB0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESSMSB0_pixeng_fetchyuv3_ReadAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESSMSB0_pixeng_fetchyuv3_ReadAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESSMSB0_pixeng_fetchyuv3_ReadAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESSMSB0_pixeng_fetchyuv3_ReadAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_READADDRESSMSB0_pixeng_fetchyuv3_ReadAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_BURSTBUFFERPROPERTIES_pixeng_fetchyuv3_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_STATUS_pixeng_fetchyuv3_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESS0_pixeng_fetchyuv3_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESS0_pixeng_fetchyuv3_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESS0_pixeng_fetchyuv3_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESS0_pixeng_fetchyuv3_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESS0_pixeng_fetchyuv3_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESSMSB0_pixeng_fetchyuv3_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESSMSB0_pixeng_fetchyuv3_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESSMSB0_pixeng_fetchyuv3_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESSMSB0_pixeng_fetchyuv3_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_CURBASEADDRESSMSB0_pixeng_fetchyuv3_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3_HIDDENSTATUS_pixeng_fetchyuv3_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3cfg_fetchyuv3_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3cfg_fetchyuv3_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv3cfg_fetchyuv3_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3cfg_fetchyuv3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3cfg_fetchyuv3_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKUNLOCK_pixeng_fetchyuv3cfg_fetchyuv3_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_LOCKSTATUS_pixeng_fetchyuv3cfg_fetchyuv3_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC - Dynamic pixel engine configuration for fetchyuv3 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_src_sel_SHIFT (0U) /*! pixeng_fetchyuv3cfg_fetchyuv3_src_sel * 0b000000..Unit fetchyuv3 input port src is disabled * 0b000111..Unit fetchyuv3 input port src is connected to output of unit fetcheco9 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_sec_sel_SHIFT (8U) /*! pixeng_fetchyuv3cfg_fetchyuv3_sec_sel * 0b000000..Unit fetchyuv3 input port sec is disabled * 0b100001..Unit fetchyuv3 input port sec is connected to output of unit fetchyuv2 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_DYNAMIC_pixeng_fetchyuv3cfg_fetchyuv3_sec_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV3CFG_FETCHYUV3_STATUS - Status information for pixel engine configuration of fetchyuv3 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_STATUS_pixeng_fetchyuv3cfg_fetchyuv3_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_STATUS_pixeng_fetchyuv3cfg_fetchyuv3_sel_SHIFT (16U) /*! pixeng_fetchyuv3cfg_fetchyuv3_sel * 0b000..fetchyuv3 module is not used * 0b001..fetchyuv3 module is used from store9 processing path * 0b010..fetchyuv3 module is used from extdst0 processing path * 0b011..fetchyuv3 module is used from extdst4 processing path * 0b100..fetchyuv3 module is used from extdst1 processing path * 0b101..fetchyuv3 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_STATUS_pixeng_fetchyuv3cfg_fetchyuv3_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_STATUS_pixeng_fetchyuv3cfg_fetchyuv3_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV3CFG_FETCHYUV3_STATUS_pixeng_fetchyuv3cfg_fetchyuv3_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATICCONTROL_pixeng_fetchyuv0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATICCONTROL_pixeng_fetchyuv0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATICCONTROL_pixeng_fetchyuv0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATICCONTROL_pixeng_fetchyuv0_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATICCONTROL_pixeng_fetchyuv0_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv0_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDR0_pixeng_fetchyuv0_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDR0_pixeng_fetchyuv0_RingBufStartAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDR0_pixeng_fetchyuv0_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDR0_pixeng_fetchyuv0_RingBufStartAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDR0_pixeng_fetchyuv0_RingBufStartAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_RINGBUFSTARTADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv0_RingBufStartAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv0_RingBufStartAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv0_RingBufStartAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv0_RingBufStartAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv0_RingBufStartAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDR0_pixeng_fetchyuv0_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDR0_pixeng_fetchyuv0_RingBufWrapAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDR0_pixeng_fetchyuv0_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDR0_pixeng_fetchyuv0_RingBufWrapAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDR0_pixeng_fetchyuv0_RingBufWrapAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_RINGBUFWRAPADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv0_RingBufWrapAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv0_RingBufWrapAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv0_RingBufWrapAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv0_RingBufWrapAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv0_RingBufWrapAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_FRAMEPROPERTIES0 - Frame property setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEPROPERTIES0_pixeng_fetchyuv0_FieldId0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEPROPERTIES0_pixeng_fetchyuv0_FieldId0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEPROPERTIES0_pixeng_fetchyuv0_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEPROPERTIES0_pixeng_fetchyuv0_FieldId0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEPROPERTIES0_pixeng_fetchyuv0_FieldId0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESS0_pixeng_fetchyuv0_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESS0_pixeng_fetchyuv0_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESS0_pixeng_fetchyuv0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESS0_pixeng_fetchyuv0_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESS0_pixeng_fetchyuv0_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESSMSB0_pixeng_fetchyuv0_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESSMSB0_pixeng_fetchyuv0_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESSMSB0_pixeng_fetchyuv0_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESSMSB0_pixeng_fetchyuv0_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BASEADDRESSMSB0_pixeng_fetchyuv0_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv0_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv0_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv0_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv0_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv0_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv0_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv0_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv0_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv0_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv0_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv0_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv0_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTBITS0_pixeng_fetchyuv0_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_COLORCOMPONENTSHIFT0_pixeng_fetchyuv0_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYEROFFSET0_pixeng_fetchyuv0_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWOFFSET0_pixeng_fetchyuv0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv0_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONSTANTCOLOR0_pixeng_fetchyuv0_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_TileMode0_SHIFT (4U) /*! pixeng_fetchyuv0_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaMaskEnable0_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaMaskEnable0_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaMaskEnable0_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaMaskEnable0_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchyuv0_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_LAYERPROPERTY0_pixeng_fetchyuv0_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMEDIMENSIONS_pixeng_fetchyuv0_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FRAMERESAMPLING_pixeng_fetchyuv0_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RasterMode_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RasterMode_SHIFT (0U) /*! pixeng_fetchyuv0_RasterMode * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot only] Arbitrary warping (filter is active). Coordinates are read from frame input * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is U. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. * 0b110..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RasterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RasterMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_InputSelect_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_InputSelect_SHIFT (3U) /*! pixeng_fetchyuv0_InputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_InputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_InputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV422UpsamplingMode_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV422UpsamplingMode_SHIFT (5U) /*! pixeng_fetchyuv0_YUV422UpsamplingMode * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV422UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV422UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ChromaHReplEn_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ChromaHReplEn_SHIFT (6U) /*! pixeng_fetchyuv0_ChromaHReplEn * 0b0..Not used. * 0b1..Replicate mode for input samples. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ChromaHReplEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ChromaHReplEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ChromaHReplEn_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_SecInputSelect_MASK (0x1800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_SecInputSelect_SHIFT (11U) /*! pixeng_fetchyuv0_SecInputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_SecInputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_SecInputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_SecInputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV420UpsamplingMode_MASK (0x6000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV420UpsamplingMode_SHIFT (13U) /*! pixeng_fetchyuv0_YUV420UpsamplingMode * 0b00..Not used. * 0b01..Replicate mode for interspersed samples (UV samples between Y samples). * 0b10..Interpolate mode for coaligned samples (UV samples at Y sample positions). * 0b11..Interpolate mode for interspersed interlaced samples (UV samples betwween Y samples). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV420UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV420UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_YUV420UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ClipColor_SHIFT (16U) /*! pixeng_fetchyuv0_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROL_pixeng_fetchyuv0_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROLTRIGGER_pixeng_fetchyuv0_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROLTRIGGER_pixeng_fetchyuv0_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROLTRIGGER_pixeng_fetchyuv0_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROLTRIGGER_pixeng_fetchyuv0_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CONTROLTRIGGER_pixeng_fetchyuv0_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_START_pixeng_fetchyuv0_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_START_pixeng_fetchyuv0_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_START_pixeng_fetchyuv0_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_START_pixeng_fetchyuv0_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_START_pixeng_fetchyuv0_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FETCHTYPE_pixeng_fetchyuv0_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FETCHTYPE_pixeng_fetchyuv0_FetchType_SHIFT (0U) /*! pixeng_fetchyuv0_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_FETCHTYPE_pixeng_fetchyuv0_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_FETCHTYPE_pixeng_fetchyuv0_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_FETCHTYPE_pixeng_fetchyuv0_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_READADDRESS0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESS0_pixeng_fetchyuv0_ReadAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESS0_pixeng_fetchyuv0_ReadAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESS0_pixeng_fetchyuv0_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESS0_pixeng_fetchyuv0_ReadAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESS0_pixeng_fetchyuv0_ReadAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_READADDRESSMSB0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESSMSB0_pixeng_fetchyuv0_ReadAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESSMSB0_pixeng_fetchyuv0_ReadAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESSMSB0_pixeng_fetchyuv0_ReadAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESSMSB0_pixeng_fetchyuv0_ReadAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_READADDRESSMSB0_pixeng_fetchyuv0_ReadAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_BURSTBUFFERPROPERTIES_pixeng_fetchyuv0_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_STATUS_pixeng_fetchyuv0_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESS0_pixeng_fetchyuv0_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESS0_pixeng_fetchyuv0_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESS0_pixeng_fetchyuv0_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESS0_pixeng_fetchyuv0_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESS0_pixeng_fetchyuv0_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESSMSB0_pixeng_fetchyuv0_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESSMSB0_pixeng_fetchyuv0_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESSMSB0_pixeng_fetchyuv0_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESSMSB0_pixeng_fetchyuv0_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_CURBASEADDRESSMSB0_pixeng_fetchyuv0_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0_HIDDENSTATUS_pixeng_fetchyuv0_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0cfg_fetchyuv0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0cfg_fetchyuv0_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv0cfg_fetchyuv0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0cfg_fetchyuv0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0cfg_fetchyuv0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKUNLOCK_pixeng_fetchyuv0cfg_fetchyuv0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_LOCKSTATUS_pixeng_fetchyuv0cfg_fetchyuv0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC - Dynamic pixel engine configuration for fetchyuv0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_src_sel_SHIFT (0U) /*! pixeng_fetchyuv0cfg_fetchyuv0_src_sel * 0b000000..Unit fetchyuv0 input port src is disabled * 0b011110..Unit fetchyuv0 input port src is connected to output of unit fetcheco0 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_sec_sel_SHIFT (8U) /*! pixeng_fetchyuv0cfg_fetchyuv0_sec_sel * 0b000000..Unit fetchyuv0 input port sec is disabled * 0b011100..Unit fetchyuv0 input port sec is connected to output of unit fetchyuv3 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_DYNAMIC_pixeng_fetchyuv0cfg_fetchyuv0_sec_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV0CFG_FETCHYUV0_STATUS - Status information for pixel engine configuration of fetchyuv0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_STATUS_pixeng_fetchyuv0cfg_fetchyuv0_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_STATUS_pixeng_fetchyuv0cfg_fetchyuv0_sel_SHIFT (16U) /*! pixeng_fetchyuv0cfg_fetchyuv0_sel * 0b000..fetchyuv0 module is not used * 0b001..fetchyuv0 module is used from store9 processing path * 0b010..fetchyuv0 module is used from extdst0 processing path * 0b011..fetchyuv0 module is used from extdst4 processing path * 0b100..fetchyuv0 module is used from extdst1 processing path * 0b101..fetchyuv0 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_STATUS_pixeng_fetchyuv0cfg_fetchyuv0_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_STATUS_pixeng_fetchyuv0cfg_fetchyuv0_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV0CFG_FETCHYUV0_STATUS_pixeng_fetchyuv0cfg_fetchyuv0_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_STATICCONTROL_pixeng_fetcheco0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_STATICCONTROL_pixeng_fetcheco0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_STATICCONTROL_pixeng_fetcheco0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_STATICCONTROL_pixeng_fetcheco0_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_STATICCONTROL_pixeng_fetcheco0_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERMANAGEMENT_pixeng_fetcheco0_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESS0_pixeng_fetcheco0_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESS0_pixeng_fetcheco0_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESS0_pixeng_fetcheco0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESS0_pixeng_fetcheco0_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESS0_pixeng_fetcheco0_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESSMSB0_pixeng_fetcheco0_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESSMSB0_pixeng_fetcheco0_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESSMSB0_pixeng_fetcheco0_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESSMSB0_pixeng_fetcheco0_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BASEADDRESSMSB0_pixeng_fetcheco0_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco0_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco0_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco0_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco0_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco0_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco0_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco0_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco0_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco0_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco0_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco0_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_SOURCEBUFFERDIMENSION0_pixeng_fetcheco0_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTBITS0_pixeng_fetcheco0_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_COLORCOMPONENTSHIFT0_pixeng_fetcheco0_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYEROFFSET0_pixeng_fetcheco0_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWOFFSET0_pixeng_fetcheco0_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco0_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CONSTANTCOLOR0_pixeng_fetcheco0_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_TileMode0_SHIFT (4U) /*! pixeng_fetcheco0_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_LAYERPROPERTY0_pixeng_fetcheco0_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMEDIMENSIONS_pixeng_fetcheco0_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FRAMERESAMPLING_pixeng_fetcheco0_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_ClipColor_SHIFT (16U) /*! pixeng_fetcheco0_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROL_pixeng_fetcheco0_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROLTRIGGER_pixeng_fetcheco0_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROLTRIGGER_pixeng_fetcheco0_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROLTRIGGER_pixeng_fetcheco0_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROLTRIGGER_pixeng_fetcheco0_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CONTROLTRIGGER_pixeng_fetcheco0_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_START_pixeng_fetcheco0_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_START_pixeng_fetcheco0_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_START_pixeng_fetcheco0_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_START_pixeng_fetcheco0_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_START_pixeng_fetcheco0_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FETCHTYPE_pixeng_fetcheco0_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FETCHTYPE_pixeng_fetcheco0_FetchType_SHIFT (0U) /*! pixeng_fetcheco0_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_FETCHTYPE_pixeng_fetcheco0_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_FETCHTYPE_pixeng_fetcheco0_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_FETCHTYPE_pixeng_fetcheco0_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_BURSTBUFFERPROPERTIES_pixeng_fetcheco0_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESS0_pixeng_fetcheco0_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESS0_pixeng_fetcheco0_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESS0_pixeng_fetcheco0_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESS0_pixeng_fetcheco0_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESS0_pixeng_fetcheco0_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESSMSB0_pixeng_fetcheco0_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESSMSB0_pixeng_fetcheco0_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESSMSB0_pixeng_fetcheco0_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESSMSB0_pixeng_fetcheco0_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_CURBASEADDRESSMSB0_pixeng_fetcheco0_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0_HIDDENSTATUS_pixeng_fetcheco0_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0CFG_FETCHECO0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0cfg_fetcheco0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0cfg_fetcheco0_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco0cfg_fetcheco0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0cfg_fetcheco0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0cfg_fetcheco0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKUNLOCK_pixeng_fetcheco0cfg_fetcheco0_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_LOCKSTATUS_pixeng_fetcheco0cfg_fetcheco0_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO0CFG_FETCHECO0_STATUS - Status information for pixel engine configuration of fetcheco0 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_STATUS_pixeng_fetcheco0cfg_fetcheco0_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_STATUS_pixeng_fetcheco0cfg_fetcheco0_sel_SHIFT (16U) /*! pixeng_fetcheco0cfg_fetcheco0_sel * 0b000..fetcheco0 module is not used * 0b001..fetcheco0 module is used from store9 processing path * 0b010..fetcheco0 module is used from extdst0 processing path * 0b011..fetcheco0 module is used from extdst4 processing path * 0b100..fetcheco0 module is used from extdst1 processing path * 0b101..fetcheco0 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_STATUS_pixeng_fetcheco0cfg_fetcheco0_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_STATUS_pixeng_fetcheco0cfg_fetcheco0_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO0CFG_FETCHECO0_STATUS_pixeng_fetcheco0cfg_fetcheco0_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATICCONTROL_pixeng_fetchyuv1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATICCONTROL_pixeng_fetchyuv1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATICCONTROL_pixeng_fetchyuv1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATICCONTROL_pixeng_fetchyuv1_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATICCONTROL_pixeng_fetchyuv1_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv1_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDR0_pixeng_fetchyuv1_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDR0_pixeng_fetchyuv1_RingBufStartAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDR0_pixeng_fetchyuv1_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDR0_pixeng_fetchyuv1_RingBufStartAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDR0_pixeng_fetchyuv1_RingBufStartAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_RINGBUFSTARTADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv1_RingBufStartAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv1_RingBufStartAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv1_RingBufStartAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv1_RingBufStartAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv1_RingBufStartAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDR0_pixeng_fetchyuv1_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDR0_pixeng_fetchyuv1_RingBufWrapAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDR0_pixeng_fetchyuv1_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDR0_pixeng_fetchyuv1_RingBufWrapAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDR0_pixeng_fetchyuv1_RingBufWrapAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_RINGBUFWRAPADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv1_RingBufWrapAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv1_RingBufWrapAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv1_RingBufWrapAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv1_RingBufWrapAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv1_RingBufWrapAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_FRAMEPROPERTIES0 - Frame property setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEPROPERTIES0_pixeng_fetchyuv1_FieldId0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEPROPERTIES0_pixeng_fetchyuv1_FieldId0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEPROPERTIES0_pixeng_fetchyuv1_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEPROPERTIES0_pixeng_fetchyuv1_FieldId0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEPROPERTIES0_pixeng_fetchyuv1_FieldId0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESS0_pixeng_fetchyuv1_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESS0_pixeng_fetchyuv1_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESS0_pixeng_fetchyuv1_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESS0_pixeng_fetchyuv1_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESS0_pixeng_fetchyuv1_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESSMSB0_pixeng_fetchyuv1_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESSMSB0_pixeng_fetchyuv1_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESSMSB0_pixeng_fetchyuv1_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESSMSB0_pixeng_fetchyuv1_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BASEADDRESSMSB0_pixeng_fetchyuv1_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv1_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv1_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv1_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv1_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv1_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv1_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv1_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv1_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv1_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv1_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv1_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv1_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTBITS0_pixeng_fetchyuv1_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_COLORCOMPONENTSHIFT0_pixeng_fetchyuv1_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYEROFFSET0_pixeng_fetchyuv1_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWOFFSET0_pixeng_fetchyuv1_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv1_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONSTANTCOLOR0_pixeng_fetchyuv1_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_TileMode0_SHIFT (4U) /*! pixeng_fetchyuv1_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaMaskEnable0_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaMaskEnable0_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaMaskEnable0_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaMaskEnable0_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchyuv1_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_LAYERPROPERTY0_pixeng_fetchyuv1_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMEDIMENSIONS_pixeng_fetchyuv1_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FRAMERESAMPLING_pixeng_fetchyuv1_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RasterMode_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RasterMode_SHIFT (0U) /*! pixeng_fetchyuv1_RasterMode * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot only] Arbitrary warping (filter is active). Coordinates are read from frame input * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is U. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. * 0b110..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RasterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RasterMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_InputSelect_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_InputSelect_SHIFT (3U) /*! pixeng_fetchyuv1_InputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_InputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_InputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV422UpsamplingMode_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV422UpsamplingMode_SHIFT (5U) /*! pixeng_fetchyuv1_YUV422UpsamplingMode * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV422UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV422UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ChromaHReplEn_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ChromaHReplEn_SHIFT (6U) /*! pixeng_fetchyuv1_ChromaHReplEn * 0b0..Not used. * 0b1..Replicate mode for input samples. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ChromaHReplEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ChromaHReplEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ChromaHReplEn_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_SecInputSelect_MASK (0x1800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_SecInputSelect_SHIFT (11U) /*! pixeng_fetchyuv1_SecInputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_SecInputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_SecInputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_SecInputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV420UpsamplingMode_MASK (0x6000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV420UpsamplingMode_SHIFT (13U) /*! pixeng_fetchyuv1_YUV420UpsamplingMode * 0b00..Not used. * 0b01..Replicate mode for interspersed samples (UV samples between Y samples). * 0b10..Interpolate mode for coaligned samples (UV samples at Y sample positions). * 0b11..Interpolate mode for interspersed interlaced samples (UV samples betwween Y samples). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV420UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV420UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_YUV420UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ClipColor_SHIFT (16U) /*! pixeng_fetchyuv1_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROL_pixeng_fetchyuv1_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROLTRIGGER_pixeng_fetchyuv1_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROLTRIGGER_pixeng_fetchyuv1_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROLTRIGGER_pixeng_fetchyuv1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROLTRIGGER_pixeng_fetchyuv1_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CONTROLTRIGGER_pixeng_fetchyuv1_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_START_pixeng_fetchyuv1_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_START_pixeng_fetchyuv1_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_START_pixeng_fetchyuv1_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_START_pixeng_fetchyuv1_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_START_pixeng_fetchyuv1_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FETCHTYPE_pixeng_fetchyuv1_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FETCHTYPE_pixeng_fetchyuv1_FetchType_SHIFT (0U) /*! pixeng_fetchyuv1_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_FETCHTYPE_pixeng_fetchyuv1_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_FETCHTYPE_pixeng_fetchyuv1_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_FETCHTYPE_pixeng_fetchyuv1_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_READADDRESS0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESS0_pixeng_fetchyuv1_ReadAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESS0_pixeng_fetchyuv1_ReadAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESS0_pixeng_fetchyuv1_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESS0_pixeng_fetchyuv1_ReadAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESS0_pixeng_fetchyuv1_ReadAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_READADDRESSMSB0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESSMSB0_pixeng_fetchyuv1_ReadAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESSMSB0_pixeng_fetchyuv1_ReadAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESSMSB0_pixeng_fetchyuv1_ReadAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESSMSB0_pixeng_fetchyuv1_ReadAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_READADDRESSMSB0_pixeng_fetchyuv1_ReadAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_BURSTBUFFERPROPERTIES_pixeng_fetchyuv1_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_STATUS_pixeng_fetchyuv1_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESS0_pixeng_fetchyuv1_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESS0_pixeng_fetchyuv1_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESS0_pixeng_fetchyuv1_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESS0_pixeng_fetchyuv1_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESS0_pixeng_fetchyuv1_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESSMSB0_pixeng_fetchyuv1_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESSMSB0_pixeng_fetchyuv1_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESSMSB0_pixeng_fetchyuv1_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESSMSB0_pixeng_fetchyuv1_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_CURBASEADDRESSMSB0_pixeng_fetchyuv1_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1_HIDDENSTATUS_pixeng_fetchyuv1_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1cfg_fetchyuv1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1cfg_fetchyuv1_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv1cfg_fetchyuv1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1cfg_fetchyuv1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1cfg_fetchyuv1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKUNLOCK_pixeng_fetchyuv1cfg_fetchyuv1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_LOCKSTATUS_pixeng_fetchyuv1cfg_fetchyuv1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC - Dynamic pixel engine configuration for fetchyuv1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_src_sel_SHIFT (0U) /*! pixeng_fetchyuv1cfg_fetchyuv1_src_sel * 0b000000..Unit fetchyuv1 input port src is disabled * 0b100000..Unit fetchyuv1 input port src is connected to output of unit fetcheco1 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_sec_sel_SHIFT (8U) /*! pixeng_fetchyuv1cfg_fetchyuv1_sec_sel * 0b000000..Unit fetchyuv1 input port sec is disabled * 0b011101..Unit fetchyuv1 input port sec is connected to output of unit fetchyuv0 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_DYNAMIC_pixeng_fetchyuv1cfg_fetchyuv1_sec_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV1CFG_FETCHYUV1_STATUS - Status information for pixel engine configuration of fetchyuv1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_STATUS_pixeng_fetchyuv1cfg_fetchyuv1_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_STATUS_pixeng_fetchyuv1cfg_fetchyuv1_sel_SHIFT (16U) /*! pixeng_fetchyuv1cfg_fetchyuv1_sel * 0b000..fetchyuv1 module is not used * 0b001..fetchyuv1 module is used from store9 processing path * 0b010..fetchyuv1 module is used from extdst0 processing path * 0b011..fetchyuv1 module is used from extdst4 processing path * 0b100..fetchyuv1 module is used from extdst1 processing path * 0b101..fetchyuv1 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_STATUS_pixeng_fetchyuv1cfg_fetchyuv1_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_STATUS_pixeng_fetchyuv1cfg_fetchyuv1_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV1CFG_FETCHYUV1_STATUS_pixeng_fetchyuv1cfg_fetchyuv1_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_STATICCONTROL_pixeng_fetcheco1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_STATICCONTROL_pixeng_fetcheco1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_STATICCONTROL_pixeng_fetcheco1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_STATICCONTROL_pixeng_fetcheco1_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_STATICCONTROL_pixeng_fetcheco1_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERMANAGEMENT_pixeng_fetcheco1_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESS0_pixeng_fetcheco1_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESS0_pixeng_fetcheco1_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESS0_pixeng_fetcheco1_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESS0_pixeng_fetcheco1_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESS0_pixeng_fetcheco1_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESSMSB0_pixeng_fetcheco1_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESSMSB0_pixeng_fetcheco1_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESSMSB0_pixeng_fetcheco1_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESSMSB0_pixeng_fetcheco1_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BASEADDRESSMSB0_pixeng_fetcheco1_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco1_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco1_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco1_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco1_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco1_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco1_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco1_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco1_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco1_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco1_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco1_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_SOURCEBUFFERDIMENSION0_pixeng_fetcheco1_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTBITS0_pixeng_fetcheco1_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_COLORCOMPONENTSHIFT0_pixeng_fetcheco1_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYEROFFSET0_pixeng_fetcheco1_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWOFFSET0_pixeng_fetcheco1_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco1_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CONSTANTCOLOR0_pixeng_fetcheco1_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_TileMode0_SHIFT (4U) /*! pixeng_fetcheco1_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_LAYERPROPERTY0_pixeng_fetcheco1_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMEDIMENSIONS_pixeng_fetcheco1_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FRAMERESAMPLING_pixeng_fetcheco1_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_ClipColor_SHIFT (16U) /*! pixeng_fetcheco1_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROL_pixeng_fetcheco1_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROLTRIGGER_pixeng_fetcheco1_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROLTRIGGER_pixeng_fetcheco1_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROLTRIGGER_pixeng_fetcheco1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROLTRIGGER_pixeng_fetcheco1_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CONTROLTRIGGER_pixeng_fetcheco1_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_START_pixeng_fetcheco1_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_START_pixeng_fetcheco1_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_START_pixeng_fetcheco1_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_START_pixeng_fetcheco1_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_START_pixeng_fetcheco1_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FETCHTYPE_pixeng_fetcheco1_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FETCHTYPE_pixeng_fetcheco1_FetchType_SHIFT (0U) /*! pixeng_fetcheco1_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_FETCHTYPE_pixeng_fetcheco1_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_FETCHTYPE_pixeng_fetcheco1_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_FETCHTYPE_pixeng_fetcheco1_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_BURSTBUFFERPROPERTIES_pixeng_fetcheco1_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESS0_pixeng_fetcheco1_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESS0_pixeng_fetcheco1_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESS0_pixeng_fetcheco1_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESS0_pixeng_fetcheco1_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESS0_pixeng_fetcheco1_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESSMSB0_pixeng_fetcheco1_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESSMSB0_pixeng_fetcheco1_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESSMSB0_pixeng_fetcheco1_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESSMSB0_pixeng_fetcheco1_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_CURBASEADDRESSMSB0_pixeng_fetcheco1_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1_HIDDENSTATUS_pixeng_fetcheco1_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1CFG_FETCHECO1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1cfg_fetcheco1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1cfg_fetcheco1_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco1cfg_fetcheco1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1cfg_fetcheco1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1cfg_fetcheco1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKUNLOCK_pixeng_fetcheco1cfg_fetcheco1_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_LOCKSTATUS_pixeng_fetcheco1cfg_fetcheco1_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO1CFG_FETCHECO1_STATUS - Status information for pixel engine configuration of fetcheco1 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_STATUS_pixeng_fetcheco1cfg_fetcheco1_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_STATUS_pixeng_fetcheco1cfg_fetcheco1_sel_SHIFT (16U) /*! pixeng_fetcheco1cfg_fetcheco1_sel * 0b000..fetcheco1 module is not used * 0b001..fetcheco1 module is used from store9 processing path * 0b010..fetcheco1 module is used from extdst0 processing path * 0b011..fetcheco1 module is used from extdst4 processing path * 0b100..fetcheco1 module is used from extdst1 processing path * 0b101..fetcheco1 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_STATUS_pixeng_fetcheco1cfg_fetcheco1_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_STATUS_pixeng_fetcheco1cfg_fetcheco1_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO1CFG_FETCHECO1_STATUS_pixeng_fetcheco1cfg_fetcheco1_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATICCONTROL_pixeng_fetchyuv2_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATICCONTROL_pixeng_fetchyuv2_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATICCONTROL_pixeng_fetchyuv2_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATICCONTROL_pixeng_fetchyuv2_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATICCONTROL_pixeng_fetchyuv2_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERMANAGEMENT_pixeng_fetchyuv2_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_RINGBUFSTARTADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDR0_pixeng_fetchyuv2_RingBufStartAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDR0_pixeng_fetchyuv2_RingBufStartAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDR0_pixeng_fetchyuv2_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDR0_pixeng_fetchyuv2_RingBufStartAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDR0_pixeng_fetchyuv2_RingBufStartAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_RINGBUFSTARTADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv2_RingBufStartAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv2_RingBufStartAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv2_RingBufStartAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv2_RingBufStartAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFSTARTADDRMSB0_pixeng_fetchyuv2_RingBufStartAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_RINGBUFWRAPADDR0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDR0_pixeng_fetchyuv2_RingBufWrapAddr0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDR0_pixeng_fetchyuv2_RingBufWrapAddr0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDR0_pixeng_fetchyuv2_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDR0_pixeng_fetchyuv2_RingBufWrapAddr0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDR0_pixeng_fetchyuv2_RingBufWrapAddr0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_RINGBUFWRAPADDRMSB0 - Ring buffer setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv2_RingBufWrapAddrMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv2_RingBufWrapAddrMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv2_RingBufWrapAddrMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv2_RingBufWrapAddrMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_RINGBUFWRAPADDRMSB0_pixeng_fetchyuv2_RingBufWrapAddrMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_FRAMEPROPERTIES0 - Frame property setup for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEPROPERTIES0_pixeng_fetchyuv2_FieldId0_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEPROPERTIES0_pixeng_fetchyuv2_FieldId0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEPROPERTIES0_pixeng_fetchyuv2_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEPROPERTIES0_pixeng_fetchyuv2_FieldId0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEPROPERTIES0_pixeng_fetchyuv2_FieldId0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESS0_pixeng_fetchyuv2_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESS0_pixeng_fetchyuv2_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESS0_pixeng_fetchyuv2_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESS0_pixeng_fetchyuv2_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESS0_pixeng_fetchyuv2_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESSMSB0_pixeng_fetchyuv2_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESSMSB0_pixeng_fetchyuv2_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESSMSB0_pixeng_fetchyuv2_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESSMSB0_pixeng_fetchyuv2_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BASEADDRESSMSB0_pixeng_fetchyuv2_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv2_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv2_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv2_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv2_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESS0_pixeng_fetchyuv2_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv2_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv2_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv2_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv2_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetchyuv2_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERATTRIBUTES0_pixeng_fetchyuv2_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_SOURCEBUFFERDIMENSION0_pixeng_fetchyuv2_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTBITS0_pixeng_fetchyuv2_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_COLORCOMPONENTSHIFT0_pixeng_fetchyuv2_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYEROFFSET0_pixeng_fetchyuv2_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWOFFSET0_pixeng_fetchyuv2_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CLIPWINDOWDIMENSIONS0_pixeng_fetchyuv2_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONSTANTCOLOR0_pixeng_fetchyuv2_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_TileMode0_SHIFT (4U) /*! pixeng_fetchyuv2_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaSrcEnable0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaSrcEnable0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaConstEnable0_MASK (0x200U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaConstEnable0_SHIFT (9U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaMaskEnable0_MASK (0x400U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaMaskEnable0_SHIFT (10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaTransEnable0_MASK (0x800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaTransEnable0_SHIFT (11U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_AlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaSrcEnable0_MASK (0x1000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaSrcEnable0_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaSrcEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaSrcEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaConstEnable0_MASK (0x2000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaConstEnable0_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaConstEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaConstEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaMaskEnable0_MASK (0x4000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaMaskEnable0_SHIFT (14U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaMaskEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaMaskEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaTransEnable0_MASK (0x8000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaTransEnable0_SHIFT (15U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaTransEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_RGBAlphaTransEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_PremulConstRGB0_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_PremulConstRGB0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_PremulConstRGB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_PremulConstRGB0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_YUVConversionMode0_MASK (0x60000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_YUVConversionMode0_SHIFT (17U) /*! pixeng_fetchyuv2_YUVConversionMode0 * 0b00..No conversion. * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV). * Input range is 16..235 for Y and 16..240 for U/V. * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding). * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). * Input range is 16..235 for Y and 16..240 for U/V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_YUVConversionMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_YUVConversionMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_GammaRemoveEnable0_MASK (0x100000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_GammaRemoveEnable0_SHIFT (20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_GammaRemoveEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_GammaRemoveEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_LAYERPROPERTY0_pixeng_fetchyuv2_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMEDIMENSIONS_pixeng_fetchyuv2_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FRAMERESAMPLING_pixeng_fetchyuv2_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RasterMode_MASK (0x7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RasterMode_SHIFT (0U) /*! pixeng_fetchyuv2_RasterMode * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup. * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1). * 0b010..[FetchPersp/Warp/Rot only] Arbitrary warping (filter is active). Coordinates are read from frame input * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup. * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W. * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. * 0b100..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is U. * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates. * 0b110..[FetchPersp/Decode/YUV only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even. First Chroma * Sample is V. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RasterMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RasterMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_InputSelect_MASK (0x18U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_InputSelect_SHIFT (3U) /*! pixeng_fetchyuv2_InputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). * 0b11..Used for arbitrary warping (coordinate buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_InputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_InputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV422UpsamplingMode_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV422UpsamplingMode_SHIFT (5U) /*! pixeng_fetchyuv2_YUV422UpsamplingMode * 0b0..Replicate mode for interspersed samples (UV samples between Y samples). * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV422UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV422UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ChromaHReplEn_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ChromaHReplEn_SHIFT (6U) /*! pixeng_fetchyuv2_ChromaHReplEn * 0b0..Not used. * 0b1..Replicate mode for input samples. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ChromaHReplEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ChromaHReplEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ChromaHReplEn_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_SecInputSelect_MASK (0x1800U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_SecInputSelect_SHIFT (11U) /*! pixeng_fetchyuv2_SecInputSelect * 0b00..Not used. * 0b01..Used for component packing (e.g. UV or source alpha buffer). * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_SecInputSelect(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_SecInputSelect_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_SecInputSelect_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV420UpsamplingMode_MASK (0x6000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV420UpsamplingMode_SHIFT (13U) /*! pixeng_fetchyuv2_YUV420UpsamplingMode * 0b00..Not used. * 0b01..Replicate mode for interspersed samples (UV samples between Y samples). * 0b10..Interpolate mode for coaligned samples (UV samples at Y sample positions). * 0b11..Interpolate mode for interspersed interlaced samples (UV samples betwween Y samples). */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV420UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV420UpsamplingMode_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_YUV420UpsamplingMode_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ClipColor_SHIFT (16U) /*! pixeng_fetchyuv2_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROL_pixeng_fetchyuv2_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROLTRIGGER_pixeng_fetchyuv2_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROLTRIGGER_pixeng_fetchyuv2_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROLTRIGGER_pixeng_fetchyuv2_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROLTRIGGER_pixeng_fetchyuv2_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CONTROLTRIGGER_pixeng_fetchyuv2_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_START_pixeng_fetchyuv2_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_START_pixeng_fetchyuv2_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_START_pixeng_fetchyuv2_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_START_pixeng_fetchyuv2_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_START_pixeng_fetchyuv2_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FETCHTYPE_pixeng_fetchyuv2_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FETCHTYPE_pixeng_fetchyuv2_FetchType_SHIFT (0U) /*! pixeng_fetchyuv2_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_FETCHTYPE_pixeng_fetchyuv2_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_FETCHTYPE_pixeng_fetchyuv2_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_FETCHTYPE_pixeng_fetchyuv2_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_READADDRESS0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESS0_pixeng_fetchyuv2_ReadAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESS0_pixeng_fetchyuv2_ReadAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESS0_pixeng_fetchyuv2_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESS0_pixeng_fetchyuv2_ReadAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESS0_pixeng_fetchyuv2_ReadAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_READADDRESSMSB0 - Ring buffer synchronization for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESSMSB0_pixeng_fetchyuv2_ReadAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESSMSB0_pixeng_fetchyuv2_ReadAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESSMSB0_pixeng_fetchyuv2_ReadAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESSMSB0_pixeng_fetchyuv2_ReadAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_READADDRESSMSB0_pixeng_fetchyuv2_ReadAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_BURSTBUFFERPROPERTIES_pixeng_fetchyuv2_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_STATUS - Status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_WriteTimeout_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_WriteTimeout_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_WriteTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_WriteTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_ReadTimeout_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_ReadTimeout_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_ReadTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_STATUS_pixeng_fetchyuv2_ReadTimeout_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESS0_pixeng_fetchyuv2_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESS0_pixeng_fetchyuv2_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESS0_pixeng_fetchyuv2_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESS0_pixeng_fetchyuv2_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESS0_pixeng_fetchyuv2_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESSMSB0_pixeng_fetchyuv2_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESSMSB0_pixeng_fetchyuv2_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESSMSB0_pixeng_fetchyuv2_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESSMSB0_pixeng_fetchyuv2_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_CURBASEADDRESSMSB0_pixeng_fetchyuv2_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2_HIDDENSTATUS_pixeng_fetchyuv2_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2cfg_fetchyuv2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2cfg_fetchyuv2_LockUnlock_SHIFT (0U) /*! pixeng_fetchyuv2cfg_fetchyuv2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2cfg_fetchyuv2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2cfg_fetchyuv2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKUNLOCK_pixeng_fetchyuv2cfg_fetchyuv2_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_LOCKSTATUS_pixeng_fetchyuv2cfg_fetchyuv2_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC - Dynamic pixel engine configuration for fetchyuv2 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_src_sel_SHIFT (0U) /*! pixeng_fetchyuv2cfg_fetchyuv2_src_sel * 0b000000..Unit fetchyuv2 input port src is disabled * 0b100010..Unit fetchyuv2 input port src is connected to output of unit fetcheco2 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_sec_sel_MASK (0x3F00U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_sec_sel_SHIFT (8U) /*! pixeng_fetchyuv2cfg_fetchyuv2_sec_sel * 0b000000..Unit fetchyuv2 input port sec is disabled * 0b011111..Unit fetchyuv2 input port sec is connected to output of unit fetchyuv1 */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_sec_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_DYNAMIC_pixeng_fetchyuv2cfg_fetchyuv2_sec_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHYUV2CFG_FETCHYUV2_STATUS - Status information for pixel engine configuration of fetchyuv2 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_STATUS_pixeng_fetchyuv2cfg_fetchyuv2_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_STATUS_pixeng_fetchyuv2cfg_fetchyuv2_sel_SHIFT (16U) /*! pixeng_fetchyuv2cfg_fetchyuv2_sel * 0b000..fetchyuv2 module is not used * 0b001..fetchyuv2 module is used from store9 processing path * 0b010..fetchyuv2 module is used from extdst0 processing path * 0b011..fetchyuv2 module is used from extdst4 processing path * 0b100..fetchyuv2 module is used from extdst1 processing path * 0b101..fetchyuv2 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_STATUS_pixeng_fetchyuv2cfg_fetchyuv2_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_STATUS_pixeng_fetchyuv2cfg_fetchyuv2_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHYUV2CFG_FETCHYUV2_STATUS_pixeng_fetchyuv2cfg_fetchyuv2_sel_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_STATICCONTROL - Common static control options. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_STATICCONTROL_pixeng_fetcheco2_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_STATICCONTROL_pixeng_fetcheco2_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_STATICCONTROL_pixeng_fetcheco2_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_STATICCONTROL_pixeng_fetcheco2_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_STATICCONTROL_pixeng_fetcheco2_ShdEn_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetNumBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetNumBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetNumBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetNumBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetBurstLength_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetBurstLength_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetMaxBurstLength_MASK (0x1FE000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetMaxBurstLength_SHIFT (13U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetMaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetMaxBurstLength_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_SetMaxBurstLength_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_MASK (0x1FE00000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_SHIFT (21U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_Enable_MASK (0x20000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_Enable_SHIFT (29U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerTimeout_Enable_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerLineFlush_Enable_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerLineFlush_Enable_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerLineFlush_Enable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerLineFlush_Enable_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERMANAGEMENT_pixeng_fetcheco2_CombinerLineFlush_Enable_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_BASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESS0_pixeng_fetcheco2_BaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESS0_pixeng_fetcheco2_BaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESS0_pixeng_fetcheco2_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESS0_pixeng_fetcheco2_BaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESS0_pixeng_fetcheco2_BaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_BASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESSMSB0_pixeng_fetcheco2_BaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESSMSB0_pixeng_fetcheco2_BaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESSMSB0_pixeng_fetcheco2_BaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESSMSB0_pixeng_fetcheco2_BaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BASEADDRESSMSB0_pixeng_fetcheco2_BaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESS0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco2_AutoUpdateBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco2_AutoUpdateBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco2_AutoUpdateBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco2_AutoUpdateBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESS0_pixeng_fetcheco2_AutoUpdateBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESSMSB0 - Source buffer base address of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco2_AutoUpdateBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco2_AutoUpdateBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco2_AutoUpdateBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco2_AutoUpdateBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_AUTOUPDATEBASEADDRESSMSB0_pixeng_fetcheco2_AutoUpdateBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_Stride0_MASK (0xFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_Stride0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_Stride0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_Stride0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_Stride0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BitsPerPixel0_MASK (0x3F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BitsPerPixel0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BitsPerPixel0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BitsPerPixel0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BaseAddressAutoUpdate0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BaseAddressAutoUpdate0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BaseAddressAutoUpdate0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BaseAddressAutoUpdate0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_BaseAddressAutoUpdate0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_DWordByteSwap0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_DWordByteSwap0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_DWordByteSwap0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_DWordByteSwap0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERATTRIBUTES0_pixeng_fetcheco2_DWordByteSwap0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineCount0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineCount0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineCount0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_SOURCEBUFFERDIMENSION0_pixeng_fetcheco2_LineCount0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsAlpha0_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsBlue0_MASK (0xF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsGreen0_MASK (0xF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsRed0_MASK (0xF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ComponentBitsRed0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ITUFormat0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ITUFormat0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ITUFormat0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTBITS0_pixeng_fetcheco2_ITUFormat0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftAlpha0_MASK (0x1FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftBlue0_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftGreen0_MASK (0x1F0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftRed0_MASK (0x1F000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_COLORCOMPONENTSHIFT0_pixeng_fetcheco2_ComponentShiftRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_LAYEROFFSET0 - Position of layer 0 within the destination frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYEROFFSET0_pixeng_fetcheco2_LayerYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowXOffset0_MASK (0x7FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowXOffset0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowXOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowXOffset0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowYOffset0_MASK (0x7FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowYOffset0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowYOffset0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWOFFSET0_pixeng_fetcheco2_ClipWindowYOffset0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowWidth0_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowWidth0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowWidth0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowWidth0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowHeight0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowHeight0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowHeight0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CLIPWINDOWDIMENSIONS0_pixeng_fetcheco2_ClipWindowHeight0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_CONSTANTCOLOR0 - Constant color for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantAlpha0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantAlpha0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantAlpha0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantAlpha0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantBlue0_MASK (0xFF00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantBlue0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantBlue0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantBlue0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantGreen0_MASK (0xFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantGreen0_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantGreen0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantGreen0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantRed0_MASK (0xFF000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantRed0_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantRed0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CONSTANTCOLOR0_pixeng_fetcheco2_ConstantRed0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_LAYERPROPERTY0 - Common properties of layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_TileMode0_MASK (0x30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_TileMode0_SHIFT (4U) /*! pixeng_fetcheco2_TileMode0 * 0b00..Use zero value * 0b01..Use constant color register value * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0. * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422 * operations or when SourceBufferEnable is 0. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_TileMode0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_TileMode0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_ClipWindowEnable0_MASK (0x40000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_ClipWindowEnable0_SHIFT (30U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_ClipWindowEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_ClipWindowEnable0_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_SourceBufferEnable0_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_SourceBufferEnable0_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_SourceBufferEnable0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_LAYERPROPERTY0_pixeng_fetcheco2_SourceBufferEnable0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_FRAMEDIMENSIONS - Output frame dimension. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameWidth_MASK (0x3FFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameWidth_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameWidth_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameWidth_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameHeight_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameHeight_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameHeight_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_FrameHeight_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_EmptyFrame_MASK (0x80000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_EmptyFrame_SHIFT (31U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_EmptyFrame_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMEDIMENSIONS_pixeng_fetcheco2_EmptyFrame_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_FRAMERESAMPLING - Resampling options for output frame. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartX_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartX_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartY_MASK (0xFC0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartY_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_StartY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaX_MASK (0x3F000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaX_SHIFT (12U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaX_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaX_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaY_MASK (0xFC0000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaY_SHIFT (18U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaY_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_DeltaY_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_SwapDirection_MASK (0x1000000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_SwapDirection_SHIFT (24U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_SwapDirection_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FRAMERESAMPLING_pixeng_fetcheco2_SwapDirection_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_CONTROL - Shared common control settings for all layers. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_RawPixel_MASK (0x80U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_RawPixel_SHIFT (7U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_RawPixel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_RawPixel_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_ClipColor_MASK (0x10000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_ClipColor_SHIFT (16U) /*! pixeng_fetcheco2_ClipColor * 0b0..Null color. * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is * then the layer's source or tiling color. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_ClipColor_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROL_pixeng_fetcheco2_ClipColor_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_CONTROLTRIGGER - Shadow load trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROLTRIGGER_pixeng_fetcheco2_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROLTRIGGER_pixeng_fetcheco2_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROLTRIGGER_pixeng_fetcheco2_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROLTRIGGER_pixeng_fetcheco2_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CONTROLTRIGGER_pixeng_fetcheco2_ShdTokGen_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_START - Frame start trigger. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_START_pixeng_fetcheco2_Start_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_START_pixeng_fetcheco2_Start_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_START_pixeng_fetcheco2_Start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_START_pixeng_fetcheco2_Start_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_START_pixeng_fetcheco2_Start_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_FETCHTYPE - Fetch unit type. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FETCHTYPE_pixeng_fetcheco2_FetchType_MASK (0xFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FETCHTYPE_pixeng_fetcheco2_FetchType_SHIFT (0U) /*! pixeng_fetcheco2_FetchType * 0b0000..Fetch unit with RL and RLAD decoder. * 0b0001..Fetch unit with fractional plane (8 layers). * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers). * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes. * 0b0100..Fetch unit with affine, perspective and arbitrary warping. * 0b0101..Fetch unit with affine and arbitrary warping. * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set. * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set. * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set. * 0b1001..Fetch unit with reduced minimum feature set for alpha, chroma and coordinate planes. * 0b1010..Fetch unit with YUV420 upsampling support, without RL and RLAD decoder and palette. * 0b1011..Fetch unit with only RGB feature set. * 0b1100..Fetch unit with fractional plane (16 layers). * 0b1101..Fetch unit with RL and RLAD decoder, reduced feature set. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_FETCHTYPE_pixeng_fetcheco2_FetchType(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_FETCHTYPE_pixeng_fetcheco2_FetchType_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_FETCHTYPE_pixeng_fetcheco2_FetchType_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES - Burst buffer properties. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_ManagedBurstBuffers_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_ManagedBurstBuffers_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_ManagedBurstBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_ManagedBurstBuffers_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_BurstLengthForMaxBuffers_MASK (0x1F00U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_BurstLengthForMaxBuffers_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_BurstLengthForMaxBuffers_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_BURSTBUFFERPROPERTIES_pixeng_fetcheco2_BurstLengthForMaxBuffers_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_CURBASEADDRESS0 - Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESS0_pixeng_fetcheco2_CurBaseAddress0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESS0_pixeng_fetcheco2_CurBaseAddress0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESS0_pixeng_fetcheco2_CurBaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESS0_pixeng_fetcheco2_CurBaseAddress0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESS0_pixeng_fetcheco2_CurBaseAddress0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_CURBASEADDRESSMSB0 - MSB bits of Current Working BaseAddress for layer 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESSMSB0_pixeng_fetcheco2_CurBaseAddressMSB0_MASK (0xFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESSMSB0_pixeng_fetcheco2_CurBaseAddressMSB0_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESSMSB0_pixeng_fetcheco2_CurBaseAddressMSB0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESSMSB0_pixeng_fetcheco2_CurBaseAddressMSB0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_CURBASEADDRESSMSB0_pixeng_fetcheco2_CurBaseAddressMSB0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2_HIDDENSTATUS - Hidden status informations. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBusy_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBusy_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBusy_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBusy_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBuffersIdle_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBuffersIdle_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBuffersIdle_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusBuffersIdle_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusRequest_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusRequest_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusRequest_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusRequest_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusComplete_MASK (0x40U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusComplete_SHIFT (6U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusComplete_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_StatusComplete_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_ShadowStatus0_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_ShadowStatus0_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_ShadowStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_ShadowStatus0_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2_HIDDENSTATUS_pixeng_fetcheco2_ShadowStatus0_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2CFG_FETCHECO2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2cfg_fetcheco2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2cfg_fetcheco2_LockUnlock_SHIFT (0U) /*! pixeng_fetcheco2cfg_fetcheco2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2cfg_fetcheco2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2cfg_fetcheco2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKUNLOCK_pixeng_fetcheco2cfg_fetcheco2_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_LOCKSTATUS_pixeng_fetcheco2cfg_fetcheco2_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_FETCHECO2CFG_FETCHECO2_STATUS - Status information for pixel engine configuration of fetcheco2 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_STATUS_pixeng_fetcheco2cfg_fetcheco2_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_STATUS_pixeng_fetcheco2cfg_fetcheco2_sel_SHIFT (16U) /*! pixeng_fetcheco2cfg_fetcheco2_sel * 0b000..fetcheco2 module is not used * 0b001..fetcheco2 module is used from store9 processing path * 0b010..fetcheco2 module is used from extdst0 processing path * 0b011..fetcheco2 module is used from extdst4 processing path * 0b100..fetcheco2 module is used from extdst1 processing path * 0b101..fetcheco2 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_STATUS_pixeng_fetcheco2cfg_fetcheco2_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_STATUS_pixeng_fetcheco2cfg_fetcheco2_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_FETCHECO2CFG_FETCHECO2_STATUS_pixeng_fetcheco2cfg_fetcheco2_sel_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKUNLOCK_pixeng_matrix4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKUNLOCK_pixeng_matrix4_LockUnlock_SHIFT (0U) /*! pixeng_matrix4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKUNLOCK_pixeng_matrix4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKUNLOCK_pixeng_matrix4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKUNLOCK_pixeng_matrix4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_LOCKSTATUS_pixeng_matrix4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_STATICCONTROL_pixeng_matrix4_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_STATICCONTROL_pixeng_matrix4_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_STATICCONTROL_pixeng_matrix4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_STATICCONTROL_pixeng_matrix4_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_STATICCONTROL_pixeng_matrix4_ShdEn_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_CONTROL - Color Matrix control register */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_MODE_MASK (0x3U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_MODE_SHIFT (0U) /*! pixeng_matrix4_MODE * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_MODE_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_MODE_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaMask_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaMask_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaMask_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaMask_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaInvert_MASK (0x20U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaInvert_SHIFT (5U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaInvert_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_CONTROL_pixeng_matrix4_AlphaInvert_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A11_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A11_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A11(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A11_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A11_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A12_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A12_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A12(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A12_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_RED0_pixeng_matrix4_A12_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A13_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A13_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A13(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A13_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A13_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A14_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A14_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A14(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A14_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_RED1_pixeng_matrix4_A14_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A21_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A21_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A21(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A21_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A21_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A22_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A22_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A22(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A22_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN0_pixeng_matrix4_A22_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A23_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A23_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A23(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A23_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A23_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A24_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A24_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A24(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A24_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_GREEN1_pixeng_matrix4_A24_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A31_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A31_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A31(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A31_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A31_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A32_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A32_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A32(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A32_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE0_pixeng_matrix4_A32_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A33_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A33_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A33(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A33_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A33_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A34_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A34_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A34(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A34_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_BLUE1_pixeng_matrix4_A34_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_ALPHA0 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A41_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A41_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A41(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A41_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A41_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A42_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A42_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A42(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A42_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA0_pixeng_matrix4_A42_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_ALPHA1 - Matrix values for calculation of the alpha output value. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A43_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A43_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A43(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A43_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A43_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A44_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A44_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A44(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A44_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_ALPHA1_pixeng_matrix4_A44_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C1_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C1_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C1_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C1_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C2_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C2_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C2_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR0_pixeng_matrix4_C2_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C3_MASK (0x1FFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C3_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C3_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C3_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C4_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C4_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C4_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_OFFSETVECTOR1_pixeng_matrix4_C4_MASK) /*! @} */ /*! @name PIXENG_MATRIX4_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4_LASTCONTROLWORD_pixeng_matrix4_L_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LASTCONTROLWORD_pixeng_matrix4_L_VAL_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4_LASTCONTROLWORD_pixeng_matrix4_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4_LASTCONTROLWORD_pixeng_matrix4_L_VAL_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4_LASTCONTROLWORD_pixeng_matrix4_L_VAL_MASK) /*! @} */ /*! @name PIXENG_MATRIX4CFG_MATRIX4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKUNLOCK_pixeng_matrix4cfg_matrix4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKUNLOCK_pixeng_matrix4cfg_matrix4_LockUnlock_SHIFT (0U) /*! pixeng_matrix4cfg_matrix4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKUNLOCK_pixeng_matrix4cfg_matrix4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKUNLOCK_pixeng_matrix4cfg_matrix4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKUNLOCK_pixeng_matrix4cfg_matrix4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_LOCKSTATUS_pixeng_matrix4cfg_matrix4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC - Dynamic pixel engine configuration for matrix4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_src_sel_SHIFT (0U) /*! pixeng_matrix4cfg_matrix4_src_sel * 0b000000..Unit matrix4 input port src is disabled * 0b011100..Unit matrix4 input port src is connected to output of unit fetchyuv3 * 0b011101..Unit matrix4 input port src is connected to output of unit fetchyuv0 * 0b011111..Unit matrix4 input port src is connected to output of unit fetchyuv1 * 0b100001..Unit matrix4 input port src is connected to output of unit fetchyuv2 */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_clken_SHIFT (24U) /*! pixeng_matrix4cfg_matrix4_clken * 0b00..Clock for matrix4 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for matrix4 is without gating */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_DYNAMIC_pixeng_matrix4cfg_matrix4_clken_MASK) /*! @} */ /*! @name PIXENG_MATRIX4CFG_MATRIX4_STATUS - Status information for pixel engine configuration of matrix4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_STATUS_pixeng_matrix4cfg_matrix4_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_STATUS_pixeng_matrix4cfg_matrix4_sel_SHIFT (16U) /*! pixeng_matrix4cfg_matrix4_sel * 0b000..matrix4 module is not used * 0b001..matrix4 module is used from store9 processing path * 0b010..matrix4 module is used from extdst0 processing path * 0b011..matrix4 module is used from extdst4 processing path * 0b100..matrix4 module is used from extdst1 processing path * 0b101..matrix4 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_STATUS_pixeng_matrix4cfg_matrix4_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_STATUS_pixeng_matrix4cfg_matrix4_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_MATRIX4CFG_MATRIX4_STATUS_pixeng_matrix4cfg_matrix4_sel_MASK) /*! @} */ /*! @name PIXENG_HSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4_LockUnlock_SHIFT (0U) /*! pixeng_hscaler4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_HSCALER4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_LOCKSTATUS_pixeng_hscaler4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_HSCALER4_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_STATICCONTROL_pixeng_hscaler4_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_STATICCONTROL_pixeng_hscaler4_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_STATICCONTROL_pixeng_hscaler4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_STATICCONTROL_pixeng_hscaler4_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_STATICCONTROL_pixeng_hscaler4_ShdEn_MASK) /*! @} */ /*! @name PIXENG_HSCALER4_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP1_pixeng_hscaler4_scale_factor_MASK (0xFFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP1_pixeng_hscaler4_scale_factor_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP1_pixeng_hscaler4_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP1_pixeng_hscaler4_scale_factor_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP1_pixeng_hscaler4_scale_factor_MASK) /*! @} */ /*! @name PIXENG_HSCALER4_SETUP2 - Phase interpolator setup. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP2_pixeng_hscaler4_phase_offset_MASK (0x1FFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP2_pixeng_hscaler4_phase_offset_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP2_pixeng_hscaler4_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP2_pixeng_hscaler4_phase_offset_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_SETUP2_pixeng_hscaler4_phase_offset_MASK) /*! @} */ /*! @name PIXENG_HSCALER4_CONTROL - Scaler operation control. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_mode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_mode_SHIFT (0U) /*! pixeng_hscaler4_mode * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_mode_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_scale_mode_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_scale_mode_SHIFT (4U) /*! pixeng_hscaler4_scale_mode * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size) */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_scale_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_scale_mode_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_filter_mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_filter_mode_SHIFT (8U) /*! pixeng_hscaler4_filter_mode * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_filter_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_filter_mode_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_output_size_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_output_size_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_output_size(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_output_size_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4_CONTROL_pixeng_hscaler4_output_size_MASK) /*! @} */ /*! @name PIXENG_HSCALER4CFG_HSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4cfg_hscaler4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4cfg_hscaler4_LockUnlock_SHIFT (0U) /*! pixeng_hscaler4cfg_hscaler4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4cfg_hscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4cfg_hscaler4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKUNLOCK_pixeng_hscaler4cfg_hscaler4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_LOCKSTATUS_pixeng_hscaler4cfg_hscaler4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC - Dynamic pixel engine configuration for hscaler4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_src_sel_SHIFT (0U) /*! pixeng_hscaler4cfg_hscaler4_src_sel * 0b000000..Unit hscaler4 input port src is disabled * 0b011100..Unit hscaler4 input port src is connected to output of unit fetchyuv3 * 0b011101..Unit hscaler4 input port src is connected to output of unit fetchyuv0 * 0b011111..Unit hscaler4 input port src is connected to output of unit fetchyuv1 * 0b100001..Unit hscaler4 input port src is connected to output of unit fetchyuv2 * 0b100011..Unit hscaler4 input port src is connected to output of unit matrix4 * 0b100101..Unit hscaler4 input port src is connected to output of unit vscaler4 */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_clken_SHIFT (24U) /*! pixeng_hscaler4cfg_hscaler4_clken * 0b00..Clock for hscaler4 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for hscaler4 is without gating */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_DYNAMIC_pixeng_hscaler4cfg_hscaler4_clken_MASK) /*! @} */ /*! @name PIXENG_HSCALER4CFG_HSCALER4_STATUS - Status information for pixel engine configuration of hscaler4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_STATUS_pixeng_hscaler4cfg_hscaler4_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_STATUS_pixeng_hscaler4cfg_hscaler4_sel_SHIFT (16U) /*! pixeng_hscaler4cfg_hscaler4_sel * 0b000..hscaler4 module is not used * 0b001..hscaler4 module is used from store9 processing path * 0b010..hscaler4 module is used from extdst0 processing path * 0b011..hscaler4 module is used from extdst4 processing path * 0b100..hscaler4 module is used from extdst1 processing path * 0b101..hscaler4 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_STATUS_pixeng_hscaler4cfg_hscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_STATUS_pixeng_hscaler4cfg_hscaler4_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_HSCALER4CFG_HSCALER4_STATUS_pixeng_hscaler4cfg_hscaler4_sel_MASK) /*! @} */ /*! @name PIXENG_VSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4_LockUnlock_SHIFT (0U) /*! pixeng_vscaler4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_VSCALER4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_LOCKSTATUS_pixeng_vscaler4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_VSCALER4_STATICCONTROL - Static control settings that must typically be setup once only. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_STATICCONTROL_pixeng_vscaler4_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_STATICCONTROL_pixeng_vscaler4_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_STATICCONTROL_pixeng_vscaler4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_STATICCONTROL_pixeng_vscaler4_ShdEn_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_STATICCONTROL_pixeng_vscaler4_ShdEn_MASK) /*! @} */ /*! @name PIXENG_VSCALER4_SETUP1 - Phase interpolator setup. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP1_pixeng_vscaler4_scale_factor_MASK (0xFFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP1_pixeng_vscaler4_scale_factor_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP1_pixeng_vscaler4_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP1_pixeng_vscaler4_scale_factor_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP1_pixeng_vscaler4_scale_factor_MASK) /*! @} */ /*! @name PIXENG_VSCALER4_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP2_pixeng_vscaler4_phase_offset_MASK (0x1FFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP2_pixeng_vscaler4_phase_offset_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP2_pixeng_vscaler4_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP2_pixeng_vscaler4_phase_offset_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_SETUP2_pixeng_vscaler4_phase_offset_MASK) /*! @} */ /*! @name PIXENG_VSCALER4_CONTROL - Scaler operation control. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_mode_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_mode_SHIFT (0U) /*! pixeng_vscaler4_mode * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored. * 0b1..Scaler is active. */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_mode_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_scale_mode_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_scale_mode_SHIFT (4U) /*! pixeng_vscaler4_scale_mode * 0b0..Down-scaling (output size less or equal input size). * 0b1..Up-scaling (output size greater or equal input size). */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_scale_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_scale_mode_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_filter_mode_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_filter_mode_SHIFT (8U) /*! pixeng_vscaler4_filter_mode * 0b0..Nearest filter (point-sampling) * 0b1..Box filter (linear) */ #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_filter_mode_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_filter_mode_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_output_size_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_output_size_SHIFT (16U) #define DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_output_size(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_output_size_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4_CONTROL_pixeng_vscaler4_output_size_MASK) /*! @} */ /*! @name PIXENG_VSCALER4CFG_VSCALER4_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4cfg_vscaler4_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4cfg_vscaler4_LockUnlock_SHIFT (0U) /*! pixeng_vscaler4cfg_vscaler4_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4cfg_vscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4cfg_vscaler4_LockUnlock_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKUNLOCK_pixeng_vscaler4cfg_vscaler4_LockUnlock_MASK) /*! @} */ /*! @name PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_LockStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_LockStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_LOCKSTATUS_pixeng_vscaler4cfg_vscaler4_FreezeStatus_MASK) /*! @} */ /*! @name PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC - Dynamic pixel engine configuration for vscaler4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_src_sel_MASK (0x3FU) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_src_sel_SHIFT (0U) /*! pixeng_vscaler4cfg_vscaler4_src_sel * 0b000000..Unit vscaler4 input port src is disabled * 0b011100..Unit vscaler4 input port src is connected to output of unit fetchyuv3 * 0b011101..Unit vscaler4 input port src is connected to output of unit fetchyuv0 * 0b011111..Unit vscaler4 input port src is connected to output of unit fetchyuv1 * 0b100001..Unit vscaler4 input port src is connected to output of unit fetchyuv2 * 0b100011..Unit vscaler4 input port src is connected to output of unit matrix4 * 0b100100..Unit vscaler4 input port src is connected to output of unit hscaler4 */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_src_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_src_sel_MASK) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_clken_MASK (0x3000000U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_clken_SHIFT (24U) /*! pixeng_vscaler4cfg_vscaler4_clken * 0b00..Clock for vscaler4 is disabled * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register) * 0b11..Clock for vscaler4 is without gating */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_clken_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_DYNAMIC_pixeng_vscaler4cfg_vscaler4_clken_MASK) /*! @} */ /*! @name PIXENG_VSCALER4CFG_VSCALER4_STATUS - Status information for pixel engine configuration of vscaler4 */ /*! @{ */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_STATUS_pixeng_vscaler4cfg_vscaler4_sel_MASK (0x70000U) #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_STATUS_pixeng_vscaler4cfg_vscaler4_sel_SHIFT (16U) /*! pixeng_vscaler4cfg_vscaler4_sel * 0b000..vscaler4 module is not used * 0b001..vscaler4 module is used from store9 processing path * 0b010..vscaler4 module is used from extdst0 processing path * 0b011..vscaler4 module is used from extdst4 processing path * 0b100..vscaler4 module is used from extdst1 processing path * 0b101..vscaler4 module is used from extdst5 processing path */ #define DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_STATUS_pixeng_vscaler4cfg_vscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_STATUS_pixeng_vscaler4cfg_vscaler4_sel_SHIFT)) & DISPLAY_SEERIS_PIXENG_VSCALER4CFG_VSCALER4_STATUS_pixeng_vscaler4cfg_vscaler4_sel_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUNLOCK_diseng_domainblend0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUNLOCK_diseng_domainblend0_LockUnlock_SHIFT (0U) /*! diseng_domainblend0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUNLOCK_diseng_domainblend0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUNLOCK_diseng_domainblend0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUNLOCK_diseng_domainblend0_LockUnlock_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKSTATUS_diseng_domainblend0_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdEn_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdLdSel_MASK (0xEU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdLdSel_SHIFT (1U) /*! diseng_domainblend0_ShdLdSel * 0b000..Shadow loading not allowed * 0b001..Load shadows with shadow load token on primary input. * 0b010..Load shadows with shadow load token on secondary input. * 0b011..Load shadows with shadow load token on primary or secondary input. * 0b100..Load shadows with shadow load token from ControlTrigger register. * 0b101..Load shadows with shadow load token from ControlTrigger register or primary input. * 0b110..Load shadows with shadow load token from ControlTrigger register or secondary input. * 0b111..Load shadows with shadow load token from ControlTrigger register or primary or secondary input. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdLdSel_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdTokSel_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdTokSel_SHIFT (4U) /*! diseng_domainblend0_ShdTokSel * 0b000..Shadow load forwarding not allowed * 0b001..When a token was received on the primary input. * 0b010..When a token was received on the secondary input. * 0b011..When a token was received on the primary or secondary input. * 0b100..When a token was received from ControlTrigger register. * 0b101..When a token was received from ControlTrigger register or primary input. * 0b110..When a token was received from ControlTrigger register or secondary input. * 0b111..When a token was received from ControlTrigger register or primary or secondary input. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_STATICCONTROL_diseng_domainblend0_ShdTokSel_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_CONTROLTRIGGER - Shadow load and sequence complete triggers. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_ShdTokGen_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_Trigger_Sequence_Complete_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_Trigger_Sequence_Complete_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_Trigger_Sequence_Complete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_Trigger_Sequence_Complete_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_CONTROLTRIGGER_diseng_domainblend0_Trigger_Sequence_Complete_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_MODECONTROL - Operation mode of the domainblend */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_MODECONTROL_diseng_domainblend0_MODE_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_MODECONTROL_diseng_domainblend0_MODE_SHIFT (0U) /*! diseng_domainblend0_MODE * 0b00..Output is same as primary input. * 0b01..Output is same as secondary input. * 0b10..Module is in blending mode. * 0b11..Module is in side by side mode. The primary and secondary inputs are displayed side by side. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_MODECONTROL_diseng_domainblend0_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_MODECONTROL_diseng_domainblend0_MODE_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_MODECONTROL_diseng_domainblend0_MODE_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_ALPHACONTROL - Alpha mask settings. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskEnable_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskEnable_SHIFT (0U) /*! diseng_domainblend0_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskMode_MASK (0xEU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskMode_SHIFT (1U) /*! diseng_domainblend0_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ALPHACONTROL_diseng_domainblend0_AlphaMaskMode_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_C_BLD_FUNC_SHIFT (0U) /*! diseng_domainblend0_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_C_BLD_FUNC_SHIFT (4U) /*! diseng_domainblend0_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_A_BLD_FUNC_SHIFT (8U) /*! diseng_domainblend0_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_A_BLD_FUNC_SHIFT (12U) /*! diseng_domainblend0_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_BLENDCONTROL_diseng_domainblend0_BlendAlpha_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK - The status of primary and secondary sources waiting for pixels. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_PrimWait_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_PrimWait_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_PrimWait(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_PrimWait_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_PrimWait_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_SecWait_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_SecWait_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_SecWait(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_SecWait_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_TIMEOUT_FEEDBACK_diseng_domainblend0_SecWait_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_LOCKUP_CLEAR - The register can be used to internally reset domainblend if it gets stuck by pending pixels from one source. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUP_CLEAR_diseng_domainblend0_LockupClear_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUP_CLEAR_diseng_domainblend0_LockupClear_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUP_CLEAR_diseng_domainblend0_LockupClear(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUP_CLEAR_diseng_domainblend0_LockupClear_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_LOCKUP_CLEAR_diseng_domainblend0_LockupClear_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_DELAY_COUNTER_EN - The register enables the delay and error counters that report on the delay on prim and sec sources. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_EN_diseng_domainblend0_DelayCountEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_EN_diseng_domainblend0_DelayCountEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_EN_diseng_domainblend0_DelayCountEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_EN_diseng_domainblend0_DelayCountEn_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_EN_diseng_domainblend0_DelayCountEn_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_DELAY_COUNTER_PRIM - The number of inavtive clock cycles during which the domainblend is waiting for pixels from primary source. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_PRIM_diseng_domainblend0_DelayCountPrim_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_PRIM_diseng_domainblend0_DelayCountPrim_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_PRIM_diseng_domainblend0_DelayCountPrim(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_PRIM_diseng_domainblend0_DelayCountPrim_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_PRIM_diseng_domainblend0_DelayCountPrim_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_DELAY_COUNTER_SEC - The number of inavtive clock cycles during which the domainblend is waiting for pixels from secondary source. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_SEC_diseng_domainblend0_DelayCountSec_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_SEC_diseng_domainblend0_DelayCountSec_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_SEC_diseng_domainblend0_DelayCountSec(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_SEC_diseng_domainblend0_DelayCountSec_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_DELAY_COUNTER_SEC_diseng_domainblend0_DelayCountSec_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_ERROR_COUNTER_PRIM - The number of inavtive clock cycles on the primary source till the synchronization loss of domainblend. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_PRIM_diseng_domainblend0_ErrCountPrim_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_PRIM_diseng_domainblend0_ErrCountPrim_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_PRIM_diseng_domainblend0_ErrCountPrim(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_PRIM_diseng_domainblend0_ErrCountPrim_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_PRIM_diseng_domainblend0_ErrCountPrim_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_ERROR_COUNTER_SEC - The number of inavtive clock cycles on the secondary source till the synchronization loss of domainblend. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_SEC_diseng_domainblend0_ErrCountSec_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_SEC_diseng_domainblend0_ErrCountSec_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_SEC_diseng_domainblend0_ErrCountSec(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_SEC_diseng_domainblend0_ErrCountSec_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_ERROR_COUNTER_SEC_diseng_domainblend0_ErrCountSec_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_SOURCE_STATUS - Source protocol error detection for primary and secondary sources */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongCommandWord_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongCommandWord_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongCommandWord(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongCommandWord_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongCommandWord_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongPixelData_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongPixelData_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongPixelData(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongPixelData_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongPixelData_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongInput_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongInput_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongInput(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongInput_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_diseng_domainblend0_WrongInput_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR - Clearing source protocol error status for both primary and secondary sources */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongCommandWord_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongCommandWord_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongCommandWord(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongCommandWord_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongCommandWord_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongPixelData_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongPixelData_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongPixelData(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongPixelData_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongPixelData_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongInput_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongInput_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongInput(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongInput_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SOURCE_STATUS_CLEAR_diseng_domainblend0_ClearWrongInput_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_PRIMCONTROLWORD - Value of last received primary control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_PRIMCONTROLWORD_diseng_domainblend0_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_PRIMCONTROLWORD_diseng_domainblend0_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_PRIMCONTROLWORD_diseng_domainblend0_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_PRIMCONTROLWORD_diseng_domainblend0_P_VAL_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_PRIMCONTROLWORD_diseng_domainblend0_P_VAL_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND0_SECCONTROLWORD - Value of last received secondary control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SECCONTROLWORD_diseng_domainblend0_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SECCONTROLWORD_diseng_domainblend0_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SECCONTROLWORD_diseng_domainblend0_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SECCONTROLWORD_diseng_domainblend0_S_VAL_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND0_SECCONTROLWORD_diseng_domainblend0_S_VAL_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKUNLOCK_diseng_framegen0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKUNLOCK_diseng_framegen0_LockUnlock_SHIFT (0U) /*! diseng_framegen0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKUNLOCK_diseng_framegen0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKUNLOCK_diseng_framegen0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKUNLOCK_diseng_framegen0_LockUnlock_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_LOCKSTATUS_diseng_framegen0_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSTCTRL - FrameGen Static Control Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_ShdEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgSyncMode_MASK (0xEU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgSyncMode_SHIFT (1U) /*! diseng_framegen0_FgSyncMode * 0b000..No side-by-side synchronization. * 0b001..Framegen is master. * 0b010..Framegen is slave. Runs in cyclic synchronization mode. * 0b011..Framegen is slave. Runs in one time synchronization mode. * 0b110..Framegen is slave. Runs in cyclic synchronization mode. Size is adapted. * 0b111..Framegen is slave. Runs in one time synchronization mode. Size is adapted. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgSyncMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgSyncMode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgSyncMode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgShdTokGenSyncMode_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgShdTokGenSyncMode_SHIFT (4U) /*! diseng_framegen0_FgShdTokGenSyncMode * 0b0..Shadow token is generated by local FgSlr.ShdTokGen field. * 0b1..Shadow token is generated by FgSlr.ShdTokGen field of second framegenerator. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgShdTokGenSyncMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgShdTokGenSyncMode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_FgShdTokGenSyncMode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_Force_Disable_MASK (0x40000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_Force_Disable_SHIFT (30U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_Force_Disable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_Force_Disable_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSTCTRL_diseng_framegen0_Force_Disable_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_HTCFG1 - FrameGen Horizontal Timing Config Register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Hact_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Hact_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Hact(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Hact_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Hact_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Htotal_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Htotal_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Htotal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Htotal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG1_diseng_framegen0_Htotal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_HTCFG2 - FrameGen Horizontal Timing Config Register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsync_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsync_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsbp_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsbp_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsbp(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsbp_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_Hsbp_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_HsEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_HsEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_HTCFG2_diseng_framegen0_HsEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_VTCFG1 - FrameGen Vertical Timing Config Register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vact_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vact_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vact(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vact_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vact_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vtotal_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vtotal_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vtotal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vtotal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG1_diseng_framegen0_Vtotal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_VTCFG2 - FrameGen Vertical Timing Config Register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsync_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsync_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsbp_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsbp_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsbp(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsbp_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_Vsbp_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_VsEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_VsEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_VsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_VsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_VTCFG2_diseng_framegen0_VsEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_INT0CONFIG - Coordinates of the trigger point for generation of the Int0 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT0CONFIG_diseng_framegen0_Int0En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_INT1CONFIG - Coordinates of the trigger point for generation of the Int1 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT1CONFIG_diseng_framegen0_Int1En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_INT2CONFIG - Coordinates of the trigger point for generation of the Int2 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT2CONFIG_diseng_framegen0_Int2En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_INT3CONFIG - Coordinates of the trigger point for generation of the Int3 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_INT3CONFIG_diseng_framegen0_Int3En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_PKICKCONFIG - Coordinates of the trigger point for generation of the primary kick signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickCol_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickCol_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickCol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickCol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickCol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickInt0En_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickInt0En_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickInt0En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickInt0En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickInt0En_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickRow_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickRow_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickRow(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickRow_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickRow_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_PKICKCONFIG_diseng_framegen0_PKickEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_SKICKCONFIG - Coordinates of the trigger point for generation of the secondary kick signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickCol_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickCol_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickCol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickCol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickCol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickInt1En_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickInt1En_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickInt1En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickInt1En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickInt1En_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickRow_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickRow_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickRow(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickRow_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickRow_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickTrig_MASK (0x40000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickTrig_SHIFT (30U) /*! diseng_framegen0_SKickTrig * 0b0..Use internal skick signal, trigger point defined by SKickRow and SKickCol. * 0b1..Use external skick input as trigger. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickTrig(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickTrig_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickTrig_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SKICKCONFIG_diseng_framegen0_SKickEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_SECSTATCONFIG - Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevGoodFrames_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevGoodFrames_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevGoodFrames(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevGoodFrames_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevGoodFrames_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevBadFrames_MASK (0xF0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevBadFrames_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevBadFrames(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevBadFrames_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevBadFrames_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevSkewInRange_MASK (0xF00U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevSkewInRange_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevSkewInRange(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevSkewInRange_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SECSTATCONFIG_diseng_framegen0_LevSkewInRange_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR1 - FrameGen Skew Regulation Control Register 1. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRMode_MASK (0x6U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRMode_SHIFT (1U) /*! diseng_framegen0_SRMode * 0b00..Skew Regulation is off. * 0b01..Horizontal regulation enabled. * 0b10..Vertical regulation enabled. * 0b11..Both regulation modes are enabled. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRMode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRMode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRAdj_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRAdj_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRAdj(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRAdj_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRAdj_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREven_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREven_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREven(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREven_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREven_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRFastSync_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRFastSync_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRFastSync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRFastSync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRFastSync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQAlign_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQAlign_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQAlign(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQAlign_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQAlign_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQVal_MASK (0x180U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQVal_SHIFT (7U) /*! diseng_framegen0_SRQVal * 0b00..Fixed two LSB values of HTOTAL are 0b00. * 0b01..Fixed two LSB values of HTOTAL are 0b01. * 0b10..Fixed two LSB values of HTOTAL are 0b10. * 0b11..Fixed two LSB values of HTOTAL are 0b11. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQVal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQVal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRQVal_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRDbgDisp_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRDbgDisp_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRDbgDisp(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRDbgDisp_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRDbgDisp_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREpOff_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREpOff_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREpOff_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SREpOff_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRClock_Mode_MASK (0x1800U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRClock_Mode_SHIFT (11U) /*! diseng_framegen0_SRClock_Mode * 0b00..No clock regulation. * 0b01..Adapt clock frequency to input frame rate. Output alignment is done with h/vtotal regulation * 0b10..Start with CLKADAPT till in sync, switch to ONLY after in sync. * 0b11..Only clock regulation. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRClock_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRClock_Mode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRClock_Mode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRExt_MASK (0x2000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRExt_SHIFT (13U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRExt(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRExt_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_SRExt_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_CsSyncSel_MASK (0xC0000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_CsSyncSel_SHIFT (30U) /*! diseng_framegen0_CsSyncSel * 0b00..Use APIX control signals for external sync. * 0b01..Use HS VS for external sync. * 0b10..Use DSC control signals for external sync. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_CsSyncSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_CsSyncSel_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR1_diseng_framegen0_CsSyncSel_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR2 - FrameGen Skew Regulation Control Register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMin_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMin_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMax_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMax_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR2_diseng_framegen0_HTotalMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR3 - FrameGen Skew Regulation Control Register 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMin_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMin_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMax_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMax_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR3_diseng_framegen0_VTotalMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR4 - FrameGen Skew Regulation Control Register 4 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR4_diseng_framegen0_TargetSkew_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR4_diseng_framegen0_TargetSkew_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR4_diseng_framegen0_TargetSkew(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR4_diseng_framegen0_TargetSkew_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR4_diseng_framegen0_TargetSkew_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR5 - FrameGen Skew Regulation Control Register 5 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR5_diseng_framegen0_SyncRangeLow_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR5_diseng_framegen0_SyncRangeLow_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR5_diseng_framegen0_SyncRangeLow(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR5_diseng_framegen0_SyncRangeLow_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR5_diseng_framegen0_SyncRangeLow_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR6 - FrameGen Skew Regulation Control Register 6 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR6_diseng_framegen0_SyncRangeHigh_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR6_diseng_framegen0_SyncRangeHigh_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR6_diseng_framegen0_SyncRangeHigh(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR6_diseng_framegen0_SyncRangeHigh_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR6_diseng_framegen0_SyncRangeHigh_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR7 - FrameGen Skew Regulation Control Register 7 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_HorizontalIncrement_MASK (0x7FFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_HorizontalIncrement_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_HorizontalIncrement(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_HorizontalIncrement_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_HorizontalIncrement_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_VerticalIncrement_MASK (0xF8000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_VerticalIncrement_SHIFT (27U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_VerticalIncrement(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_VerticalIncrement_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR7_diseng_framegen0_VerticalIncrement_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR8 - FrameGen Skew Regulation Control Register 8 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR8_diseng_framegen0_StartOffset_MASK (0x3FFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR8_diseng_framegen0_StartOffset_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR8_diseng_framegen0_StartOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR8_diseng_framegen0_StartOffset_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR8_diseng_framegen0_StartOffset_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR9 - FrameGen Skew Regulation Control Register 9 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR9_diseng_framegen0_clockperiod_ref_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR9_diseng_framegen0_clockperiod_ref_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR9_diseng_framegen0_clockperiod_ref(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR9_diseng_framegen0_clockperiod_ref_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR9_diseng_framegen0_clockperiod_ref_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR10 - FrameGen Skew Regulation Control Register 10 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR10_diseng_framegen0_clockperiod_min_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR10_diseng_framegen0_clockperiod_min_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR10_diseng_framegen0_clockperiod_min(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR10_diseng_framegen0_clockperiod_min_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR10_diseng_framegen0_clockperiod_min_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR11 - FrameGen Skew Regulation Control Register 11 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR11_diseng_framegen0_clockperiod_max_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR11_diseng_framegen0_clockperiod_max_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR11_diseng_framegen0_clockperiod_max(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR11_diseng_framegen0_clockperiod_max_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR11_diseng_framegen0_clockperiod_max_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR12 - FrameGen Skew Regulation Control Register 12 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR12_diseng_framegen0_pixel_period_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR12_diseng_framegen0_pixel_period_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR12_diseng_framegen0_pixel_period(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR12_diseng_framegen0_pixel_period_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR12_diseng_framegen0_pixel_period_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR13 - FrameGen Skew Regulation Control Register 13 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_filterrate_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_filterrate_SHIFT (2U) /*! diseng_framegen0_CSR_filterrate * 0b00..Clock measurement update rate defined by CSR_updaterate, no additional filter used. * 0b01..Clock measurements update rate defined by CSR_updaterate filtered by 4. * 0b10..Clock measurements update rate defined by CSR_updaterate filtered by 16. * 0b11..Clock measurements update rate defined by CSR_updaterate filtered by 64. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_filterrate(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_filterrate_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_filterrate_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_updaterate_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_updaterate_SHIFT (4U) /*! diseng_framegen0_CSR_updaterate * 0b000..Clock measurement is off, reference value is used. * 0b100..Measured clock is averaged over 2^16 input clock cycles. * 0b101..Measured clock is averaged over 2^14 input clock cycles. * 0b110..Measured clock is averaged over 2^12 input clock cycles. * 0b111..Measured clock is averaged over 2^10 input clock cycles. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_updaterate(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_updaterate_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CSR_updaterate_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CMSyncSel_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CMSyncSel_SHIFT (7U) /*! diseng_framegen0_CMSyncSel * 0b0..Use APIX control signals for clock measurement. * 0b1..Use HS VS for clock measurement. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CMSyncSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CMSyncSel_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR13_diseng_framegen0_CMSyncSel_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR14 - FrameGen Skew Regulation Control Register 14 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_Clockperiod_val_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_Clockperiod_val_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_Clockperiod_val(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_Clockperiod_val_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_Clockperiod_val_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_SSCGTrack_en_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_SSCGTrack_en_SHIFT (3U) /*! diseng_framegen0_CSR_SSCGTrack_en * 0b0..Phase regulation does not take SSCG into account. * 0b1..Phase regulation does take SSCG into account. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_SSCGTrack_en(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_SSCGTrack_en_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_SSCGTrack_en_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_SHIFT (4U) /*! diseng_framegen0_CSR_ramprate * 0b000..Phase regulation uses phasegain for step. * 0b001..Phase regulation uses 1/2 of phasegain for step. * 0b010..Phase regulation uses 1/4 of phasegain for step. * 0b011..Phase regulation uses 1/8 of phasegain for step. * 0b100..Phase regulation uses 1/16 of phasegain for step. * 0b101..Phase regulation uses 1/32 of phasegain for step. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_en_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_en_SHIFT (7U) /*! diseng_framegen0_CSR_ramprate_en * 0b0..Phase regulation uses phasegain for step. * 0b1..Phase regulation uses CSR_ramprate of phasegain for step. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_en(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_en_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_ramprate_en_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegain_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegain_SHIFT (8U) /*! diseng_framegen0_CSR_phasegain * 0b000..Phase regulation uses 1/1024 of clock period. Htotal has to be bigger than 1025+32. * 0b001..Phase regulation uses 1/512 of clock period. Htotal has to be bigger than 513+32. * 0b010..Phase regulation uses 1/256 of clock period. Htotal has to be bigger than 257+32. * 0b011..Phase regulation uses 1/128 of clock period. Htotal has to be bigger than 129+32. * 0b100..Phase regulation uses 1/64 of clock period. Htotal has to be bigger than 65+32. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegain(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegain_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegain_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegainsync_MASK (0x7000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegainsync_SHIFT (12U) /*! diseng_framegen0_CSR_phasegainsync * 0b000..Phase regulation uses 1/1024 of clock period. Htotal has to be bigger than 1025+32. * 0b001..Phase regulation uses 1/512 of clock period. Htotal has to be bigger than 513+32. * 0b010..Phase regulation uses 1/256 of clock period. Htotal has to be bigger than 257+32. * 0b011..Phase regulation uses 1/128 of clock period. Htotal has to be bigger than 129+32. * 0b100..Phase regulation uses 1/64 of clock period. Htotal has to be bigger than 65+32. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegainsync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegainsync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_CSR_phasegainsync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_SkewOffset_Threshold_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_SkewOffset_Threshold_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_SkewOffset_Threshold(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_SkewOffset_Threshold_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR14_diseng_framegen0_SkewOffset_Threshold_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCR15 - FrameGen Skew Regulation Control Register 15 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsHsPol_MASK (0x4000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsHsPol_SHIFT (14U) /*! diseng_framegen0_CsHsPol * 0b0..HSYNC is low active. * 0b1..HSYNC is high active. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsHsPol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsHsPol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsHsPol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsVsPol_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsVsPol_SHIFT (15U) /*! diseng_framegen0_CsVsPol * 0b0..VSYNC is low active. * 0b1..VSYNC is high active. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsVsPol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsVsPol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsVsPol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsDelay_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsDelay_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsDelay(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsDelay_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCR15_diseng_framegen0_CsDelay_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGKSDR - FrameGen Kick System Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_PCntCplMax_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_PCntCplMax_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_PCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_PCntCplMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_PCntCplMax_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_SCntCplMax_MASK (0x70000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_SCntCplMax_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_SCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_SCntCplMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGKSDR_diseng_framegen0_SCntCplMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_PACFG - FrameGen Primary Area Config Register 1 (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstartx_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstartx_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstartx(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstartx_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstartx_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstarty_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstarty_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstarty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstarty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_PACFG_diseng_framegen0_Pstarty_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_SACFG - FrameGen Secondary Area Config Register 1 (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstartx_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstartx_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstartx(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstartx_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstartx_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstarty_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstarty_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstarty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstarty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_SACFG_diseng_framegen0_Sstarty_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGINCTRL - FrameGen Input Control Register (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_FgDm_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_FgDm_SHIFT (0U) /*! diseng_framegen0_FgDm * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_FgDm(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_FgDm_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_FgDm_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnPrimAlpha_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnPrimAlpha_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnPrimAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnPrimAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnPrimAlpha_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnSecAlpha_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnSecAlpha_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnSecAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnSecAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRL_diseng_framegen0_EnSecAlpha_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGINCTRLPANIC - FrameGen Input Control Panic Register (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_FgDmPanic_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_FgDmPanic_SHIFT (0U) /*! diseng_framegen0_FgDmPanic * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_FgDmPanic(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_FgDmPanic_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_FgDmPanic_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnPrimAlphaPanic_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnPrimAlphaPanic_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnPrimAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnPrimAlphaPanic_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnPrimAlphaPanic_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnSecAlphaPanic_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnSecAlphaPanic_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnSecAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnSecAlphaPanic_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGINCTRLPANIC_diseng_framegen0_EnSecAlphaPanic_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGCCR - FrameGen Constant Color Register (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcBlue_MASK (0x3FFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcBlue_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcBlue_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcBlue_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcGreen_MASK (0xFFC00U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcGreen_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcGreen_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcGreen_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcRed_MASK (0x3FF00000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcRed_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcRed_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcRed_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcAlpha_MASK (0xC0000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcAlpha_SHIFT (30U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCCR_diseng_framegen0_CcAlpha_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGENABLE - FrameGen Enable Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENABLE_diseng_framegen0_FgEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENABLE_diseng_framegen0_FgEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENABLE_diseng_framegen0_FgEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENABLE_diseng_framegen0_FgEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENABLE_diseng_framegen0_FgEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSLR - FrameGen Shadow Load Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSLR_diseng_framegen0_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSLR_diseng_framegen0_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSLR_diseng_framegen0_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSLR_diseng_framegen0_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSLR_diseng_framegen0_ShdTokGen_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGENSTS - FrameGen Enable Status Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_EnSts_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_EnSts_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_EnSts(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_EnSts_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_EnSts_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_PanicStat_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_PanicStat_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_PanicStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_PanicStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGENSTS_diseng_framegen0_PanicStat_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGTIMESTAMP - Time stamp status. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_LineIndex_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_LineIndex_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_LineIndex(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_LineIndex_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_LineIndex_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_FrameIndex_MASK (0xFFFFC000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_FrameIndex_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_FrameIndex(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_FrameIndex_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGTIMESTAMP_diseng_framegen0_FrameIndex_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGCHSTAT - FrameGen Channel Status Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PFifoEmpty_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PFifoEmpty_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PFifoEmpty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PFifoEmpty_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PrimSyncStat_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PrimSyncStat_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PrimSyncStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PrimSyncStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_PrimSyncStat_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SFifoEmpty_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SFifoEmpty_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SFifoEmpty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SFifoEmpty_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SkewRangeErr_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SkewRangeErr_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SkewRangeErr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SkewRangeErr_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SkewRangeErr_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SecSyncStat_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SecSyncStat_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SecSyncStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SecSyncStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTAT_diseng_framegen0_SecSyncStat_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGCHSTATCLR - FrameGen Channel Status Clear Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrPrimStat_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrPrimStat_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrPrimStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrPrimStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrPrimStat_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrSecStat_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrSecStat_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrSecStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrSecStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGCHSTATCLR_diseng_framegen0_ClrSecStat_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSKEWMON - FrameGen Skew Monitor Register for Secondary Channel Skew Control */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSKEWMON_diseng_framegen0_SkewMon_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSKEWMON_diseng_framegen0_SkewMon_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSKEWMON_diseng_framegen0_SkewMon(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSKEWMON_diseng_framegen0_SkewMon_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSKEWMON_diseng_framegen0_SkewMon_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGPFIFOMIN - FrameGen Primary FIFO Min Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMIN_diseng_framegen0_PFifoMin_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMIN_diseng_framegen0_PFifoMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMIN_diseng_framegen0_PFifoMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMIN_diseng_framegen0_PFifoMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMIN_diseng_framegen0_PFifoMin_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGPFIFOMAX - FrameGen Primary FIFO Max Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMAX_diseng_framegen0_PFifoMax_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMAX_diseng_framegen0_PFifoMax_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMAX_diseng_framegen0_PFifoMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMAX_diseng_framegen0_PFifoMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOMAX_diseng_framegen0_PFifoMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGPFIFOFILLCLR - FrameGen Primary FIFO Fill Clear Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOFILLCLR_diseng_framegen0_PFifoFillClr_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOFILLCLR_diseng_framegen0_PFifoFillClr_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOFILLCLR_diseng_framegen0_PFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOFILLCLR_diseng_framegen0_PFifoFillClr_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOFILLCLR_diseng_framegen0_PFifoFillClr_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGPFIFOTRES - FrameGen Primary FIFO Thresholds */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres0_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres0_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres0_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres1_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres1_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGPFIFOTRES_diseng_framegen0_PFifoTres1_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSFIFOMIN - FrameGen Secondary FIFO Min Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMIN_diseng_framegen0_SFifoMin_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMIN_diseng_framegen0_SFifoMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMIN_diseng_framegen0_SFifoMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMIN_diseng_framegen0_SFifoMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMIN_diseng_framegen0_SFifoMin_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSFIFOMAX - FrameGen Secondary FIFO Max Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMAX_diseng_framegen0_SFifoMax_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMAX_diseng_framegen0_SFifoMax_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMAX_diseng_framegen0_SFifoMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMAX_diseng_framegen0_SFifoMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOMAX_diseng_framegen0_SFifoMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSFIFOFILLCLR - FrameGen Secondary FIFO Fill Clear Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOFILLCLR_diseng_framegen0_SFifoFillClr_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOFILLCLR_diseng_framegen0_SFifoFillClr_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOFILLCLR_diseng_framegen0_SFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOFILLCLR_diseng_framegen0_SFifoFillClr_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSFIFOFILLCLR_diseng_framegen0_SFifoFillClr_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSREPD - FrameGen Skew Regulation ExtraPolation Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSREPD_diseng_framegen0_EpVal_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSREPD_diseng_framegen0_EpVal_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSREPD_diseng_framegen0_EpVal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSREPD_diseng_framegen0_EpVal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSREPD_diseng_framegen0_EpVal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRFTD - FrameGen Skew Regulation Frame Total Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRFTD_diseng_framegen0_FrTot_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRFTD_diseng_framegen0_FrTot_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRFTD_diseng_framegen0_FrTot(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRFTD_diseng_framegen0_FrTot_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRFTD_diseng_framegen0_FrTot_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCSHTOTAL - FrameGen Skew Regulation External Sync HTotal Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCSHTOTAL_diseng_framegen0_FrCSHTotal_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCSHTOTAL_diseng_framegen0_FrCSHTotal_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCSHTOTAL_diseng_framegen0_FrCSHTotal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCSHTOTAL_diseng_framegen0_FrCSHTotal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCSHTOTAL_diseng_framegen0_FrCSHTotal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSRCLOCKDIV - FrameGen Skew Regulation External PLL Clock divider */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCLOCKDIV_diseng_framegen0_FrClockDiv_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCLOCKDIV_diseng_framegen0_FrClockDiv_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCLOCKDIV_diseng_framegen0_FrClockDiv(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCLOCKDIV_diseng_framegen0_FrClockDiv_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSRCLOCKDIV_diseng_framegen0_FrClockDiv_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN0_FGSL - FrameGen Scanline Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_ScanLine_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_ScanLine_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_ScanLine(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_ScanLine_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_ScanLine_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_VBlank_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_VBlank_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_VBlank(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_VBlank_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN0_FGSL_diseng_framegen0_VBlank_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKUNLOCK_diseng_idhash0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKUNLOCK_diseng_idhash0_LockUnlock_SHIFT (0U) /*! diseng_idhash0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKUNLOCK_diseng_idhash0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOCKUNLOCK_diseng_idhash0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOCKUNLOCK_diseng_idhash0_LockUnlock_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOCKSTATUS_diseng_idhash0_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_IDHASH0_STATICCONTROL - Global configuration */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_EnCalc_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_EnCalc_SHIFT (0U) /*! diseng_idhash0_EnCalc * 0b0..bypass mode. the idhash calculation mode will be skipped and avoided. * 0b1..idhash perform the calculationmode/idhash extension mode. */ #define DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_EnCalc(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_EnCalc_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_EnCalc_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_ShdLdSel_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_ShdLdSel_SHIFT (4U) /*! diseng_idhash0_ShdLdSel * 0b0..Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. * 0b1..Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). */ #define DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_STATICCONTROL_diseng_idhash0_ShdLdSel_MASK) /*! @} */ /*! @name DISENG_IDHASH0_PANICTHRESHOLD - Set and reset thresholds applying to Window_Panic interrupts and status bits */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThres_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThres_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThres(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThres_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThres_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThresReset_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThresReset_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThresReset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThresReset_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_PANICTHRESHOLD_diseng_idhash0_PanicThresReset_MASK) /*! @} */ /*! @name DISENG_IDHASH0_PANICCOLOR - Overlay color for evaluation windows in panic mode */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicBlue_MASK (0x3FCU) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicBlue_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicBlue_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicBlue_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicGreen_MASK (0xFF000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicGreen_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicGreen_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicGreen_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicRed_MASK (0x3FC00000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicRed_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicRed_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicRed_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicAlpha_MASK (0xC0000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicAlpha_SHIFT (30U) #define DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_PANICCOLOR_diseng_idhash0_PanicAlpha_MASK) /*! @} */ /*! @name DISENG_IDHASH0_SHADOWLOAD - Shadow load control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_ShdLdReq_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_ShdLdReq_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_SetupID_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_SetupID_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_SetupID(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_SetupID_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_SHADOWLOAD_diseng_idhash0_SetupID_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONTINUOUSMODE - Idhash operation mode control */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTINUOUSMODE_diseng_idhash0_EnCont_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTINUOUSMODE_diseng_idhash0_EnCont_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTINUOUSMODE_diseng_idhash0_EnCont(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTINUOUSMODE_diseng_idhash0_EnCont_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTINUOUSMODE_diseng_idhash0_EnCont_MASK) /*! @} */ /*! @name DISENG_IDHASH0_IDHASH_STATUS - Idhash status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDHASH_STATUS_diseng_idhash0_IdhashState_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDHASH_STATUS_diseng_idhash0_IdhashState_SHIFT (0U) /*! diseng_idhash0_IdhashState * 0b0..Idhash is in idle state * 0b1..Idhash is in run state */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDHASH_STATUS_diseng_idhash0_IdhashState(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDHASH_STATUS_diseng_idhash0_IdhashState_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDHASH_STATUS_diseng_idhash0_IdhashState_MASK) /*! @} */ /*! @name DISENG_IDHASH0_RUN_STATUS - Idhash evaluation status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Error_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Error_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Error(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Error_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Error_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Panic_MASK (0xF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Panic_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Panic(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Panic_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_Window_Panic_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_IdhashValid_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_IdhashValid_SHIFT (16U) /*! diseng_idhash0_IdhashValid * 0b0..Idhash results are not valid * 0b1..Idhash results are valid */ #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_IdhashValid(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_IdhashValid_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_IdhashValid_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_ResultSetupID_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_ResultSetupID_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_ResultSetupID(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_ResultSetupID_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_RUN_STATUS_diseng_idhash0_ResultSetupID_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONTROL_WINDOW0 - Window 0, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_Mode_Window0_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_Mode_Window0_SHIFT (0U) /*! diseng_idhash0_Mode_Window0 * 0b000..Window is disabled. The internal status for this window is reset (Error bit and frame counters). * 0b001..Window operates in Telltale mode. * 0b010..Window operates in Icon mode. * 0b011..Window operates in RGB mode. * 0b100..1bit Alpha is inserted. * 0b101..2bit Alpha is inserted. */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_Mode_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_Mode_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_Mode_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaMask_Window0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaMask_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaMask_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaMask_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaMask_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaInv_Window0_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaInv_Window0_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaInv_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaInv_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaInv_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaSel_Window0_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaSel_Window0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaSel_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaSel_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_AlphaSel_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_LocalPanic_Window0_MASK (0xF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_LocalPanic_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_LocalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_LocalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_LocalPanic_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_GlobalPanic_Window0_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_GlobalPanic_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_GlobalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_GlobalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW0_diseng_idhash0_GlobalPanic_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_UPPERLEFT_WINDOW0 - Window 0, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW0_diseng_idhash0_UpperLeft_Y_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LOWERRIGHT_WINDOW0 - Window 0, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW0_diseng_idhash0_LowerRight_Y_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_TILE_WINDOW0 - Window 0, Tile dimensions */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_X_Window0_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_Y_Window0_MASK (0xF0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_Y_Window0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW0_diseng_idhash0_Tile_Y_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_ADDRESS_WINDOW0 - Window 0, Memory word Address for Idhash */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW0_diseng_idhash0_Address_Window0_MASK (0xFFCU) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW0_diseng_idhash0_Address_Window0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW0_diseng_idhash0_Address_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW0_diseng_idhash0_Address_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW0_diseng_idhash0_Address_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONFIG_WINDOW0 - Window 0, Idhash Configuration settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_FG_Window0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_FG_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_FG_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_FG_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_FG_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_BG_Window0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_BG_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_BG_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_BG_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Th_BG_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Tolerance_Window0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Tolerance_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Tolerance_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Tolerance_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_Tolerance_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_RGB_Th_Window0_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_RGB_Th_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_RGB_Th_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_RGB_Th_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW0_diseng_idhash0_RGB_Th_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LIMITS_WINDOW0 - Window 0, check Limit settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_SumLimit_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_SumLimit_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_SumLimit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_SumLimit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_SumLimit_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_SumLimit_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_SumLimit_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_SumLimit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_SumLimit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_SumLimit_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_WINDOW0 - Window 0, Foregound 0 Color settings. Used for Telltale mode and Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Blue_Window0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Blue_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Blue_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Blue_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Blue_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Green_Window0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Green_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Green_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Green_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Green_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Red_Window0_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Red_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Red_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Red_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW0_diseng_idhash0_Foreground0_Red_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0 - Window 0, check Limit settings for Telltale mode or for foreground color 0 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg0Limit_Window0_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg0Limit_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg0Limit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg0Limit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg0Limit_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg0Limit_Window0_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg0Limit_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg0Limit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg0Limit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg0Limit_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_WINDOW0 - Window 0, Foregound 1 Color settings, Used for Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Blue_Window0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Blue_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Blue_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Blue_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Blue_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Green_Window0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Green_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Green_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Green_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Green_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Red_Window0_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Red_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Red_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Red_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW0_diseng_idhash0_Foreground1_Red_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0 - Window 0, check Limit settings for foreground color 1 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg1Limit_Window0_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg1Limit_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg1Limit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg1Limit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg1Limit_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg1Limit_Window0_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg1Limit_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg1Limit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg1Limit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg1Limit_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_WINDOW0 - Window 0, Foregound 2 Color settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Blue_Window0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Blue_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Blue_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Blue_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Blue_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Green_Window0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Green_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Green_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Green_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Green_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Red_Window0_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Red_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Red_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Red_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW0_diseng_idhash0_Foreground2_Red_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0 - Window 0, check Limit settings for foreground color 2 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg2Limit_Window0_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg2Limit_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg2Limit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg2Limit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_FG_cnt_Fg2Limit_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg2Limit_Window0_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg2Limit_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg2Limit_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg2Limit_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW0_diseng_idhash0_Drop_cnt_Fg2Limit_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_IDX_TABLE_WINDOW0 - Window 0, Index Table */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_EN_Window0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_EN_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_FG_BGn_Window0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_FG_BGn_Window0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg0_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_EN_Window0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_EN_Window0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_FG_BGn_Window0_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_FG_BGn_Window0_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg1_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_EN_Window0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_EN_Window0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_FG_BGn_Window0_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_FG_BGn_Window0_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx0_fg2_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_EN_Window0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_EN_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_FG_BGn_Window0_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_FG_BGn_Window0_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg0_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_EN_Window0_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_EN_Window0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_FG_BGn_Window0_MASK (0x800U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_FG_BGn_Window0_SHIFT (11U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg1_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_EN_Window0_MASK (0x1000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_EN_Window0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_FG_BGn_Window0_MASK (0x2000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_FG_BGn_Window0_SHIFT (13U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx1_fg2_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_EN_Window0_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_EN_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_FG_BGn_Window0_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_FG_BGn_Window0_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg0_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_EN_Window0_MASK (0x40000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_EN_Window0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_FG_BGn_Window0_MASK (0x80000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_FG_BGn_Window0_SHIFT (19U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg1_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_EN_Window0_MASK (0x100000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_EN_Window0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_FG_BGn_Window0_MASK (0x200000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_FG_BGn_Window0_SHIFT (21U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx2_fg2_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_EN_Window0_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_EN_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_FG_BGn_Window0_MASK (0x2000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_FG_BGn_Window0_SHIFT (25U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg0_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_EN_Window0_MASK (0x4000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_EN_Window0_SHIFT (26U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_FG_BGn_Window0_MASK (0x8000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_FG_BGn_Window0_SHIFT (27U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg1_FG_BGn_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_EN_Window0_MASK (0x10000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_EN_Window0_SHIFT (28U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_EN_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_EN_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_EN_Window0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_FG_BGn_Window0_MASK (0x20000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_FG_BGn_Window0_SHIFT (29U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_FG_BGn_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_FG_BGn_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW0_diseng_idhash0_idx3_fg2_FG_BGn_Window0_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONTROL_WINDOW1 - Window 1, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_Mode_Window1_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_Mode_Window1_SHIFT (0U) /*! diseng_idhash0_Mode_Window1 * 0b000..Window is disabled. The internal status for this window is reset (Error bit and frame counters). * 0b001..Window operates in Telltale mode. * 0b010..Window operates in Icon mode. * 0b011..Window operates in RGB mode. * 0b100..1bit Alpha is inserted. * 0b101..2bit Alpha is inserted. */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_Mode_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_Mode_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_Mode_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaMask_Window1_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaMask_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaMask_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaMask_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaMask_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaInv_Window1_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaInv_Window1_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaInv_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaInv_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaInv_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaSel_Window1_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaSel_Window1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaSel_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaSel_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_AlphaSel_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_LocalPanic_Window1_MASK (0xF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_LocalPanic_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_LocalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_LocalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_LocalPanic_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_GlobalPanic_Window1_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_GlobalPanic_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_GlobalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_GlobalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW1_diseng_idhash0_GlobalPanic_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_UPPERLEFT_WINDOW1 - Window 1, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW1_diseng_idhash0_UpperLeft_Y_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LOWERRIGHT_WINDOW1 - Window 1, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW1_diseng_idhash0_LowerRight_Y_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_TILE_WINDOW1 - Window 1, Tile dimensions */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_X_Window1_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_Y_Window1_MASK (0xF0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_Y_Window1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW1_diseng_idhash0_Tile_Y_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_ADDRESS_WINDOW1 - Window 1, Memory word Address for Idhash */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW1_diseng_idhash0_Address_Window1_MASK (0xFFCU) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW1_diseng_idhash0_Address_Window1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW1_diseng_idhash0_Address_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW1_diseng_idhash0_Address_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW1_diseng_idhash0_Address_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONFIG_WINDOW1 - Window 1, Idhash Configuration settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_FG_Window1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_FG_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_FG_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_FG_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_FG_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_BG_Window1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_BG_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_BG_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_BG_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Th_BG_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Tolerance_Window1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Tolerance_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Tolerance_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Tolerance_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_Tolerance_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_RGB_Th_Window1_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_RGB_Th_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_RGB_Th_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_RGB_Th_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW1_diseng_idhash0_RGB_Th_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LIMITS_WINDOW1 - Window 1, check Limit settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_SumLimit_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_SumLimit_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_SumLimit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_SumLimit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_SumLimit_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_SumLimit_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_SumLimit_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_SumLimit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_SumLimit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_SumLimit_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_WINDOW1 - Window 1, Foregound 0 Color settings. Used for Telltale mode and Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Blue_Window1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Blue_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Blue_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Blue_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Blue_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Green_Window1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Green_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Green_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Green_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Green_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Red_Window1_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Red_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Red_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Red_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW1_diseng_idhash0_Foreground0_Red_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1 - Window 1, check Limit settings for Telltale mode or for foreground color 0 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg0Limit_Window1_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg0Limit_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg0Limit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg0Limit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg0Limit_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg0Limit_Window1_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg0Limit_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg0Limit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg0Limit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg0Limit_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_WINDOW1 - Window 1, Foregound 1 Color settings, Used for Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Blue_Window1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Blue_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Blue_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Blue_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Blue_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Green_Window1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Green_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Green_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Green_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Green_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Red_Window1_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Red_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Red_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Red_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW1_diseng_idhash0_Foreground1_Red_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1 - Window 1, check Limit settings for foreground color 1 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg1Limit_Window1_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg1Limit_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg1Limit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg1Limit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg1Limit_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg1Limit_Window1_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg1Limit_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg1Limit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg1Limit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg1Limit_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_WINDOW1 - Window 1, Foregound 2 Color settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Blue_Window1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Blue_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Blue_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Blue_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Blue_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Green_Window1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Green_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Green_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Green_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Green_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Red_Window1_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Red_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Red_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Red_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW1_diseng_idhash0_Foreground2_Red_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1 - Window 1, check Limit settings for foreground color 2 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg2Limit_Window1_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg2Limit_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg2Limit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg2Limit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_FG_cnt_Fg2Limit_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg2Limit_Window1_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg2Limit_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg2Limit_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg2Limit_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW1_diseng_idhash0_Drop_cnt_Fg2Limit_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_IDX_TABLE_WINDOW1 - Window 1, Index Table */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_EN_Window1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_EN_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_FG_BGn_Window1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_FG_BGn_Window1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg0_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_EN_Window1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_EN_Window1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_FG_BGn_Window1_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_FG_BGn_Window1_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg1_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_EN_Window1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_EN_Window1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_FG_BGn_Window1_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_FG_BGn_Window1_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx0_fg2_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_EN_Window1_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_EN_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_FG_BGn_Window1_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_FG_BGn_Window1_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg0_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_EN_Window1_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_EN_Window1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_FG_BGn_Window1_MASK (0x800U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_FG_BGn_Window1_SHIFT (11U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg1_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_EN_Window1_MASK (0x1000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_EN_Window1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_FG_BGn_Window1_MASK (0x2000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_FG_BGn_Window1_SHIFT (13U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx1_fg2_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_EN_Window1_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_EN_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_FG_BGn_Window1_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_FG_BGn_Window1_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg0_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_EN_Window1_MASK (0x40000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_EN_Window1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_FG_BGn_Window1_MASK (0x80000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_FG_BGn_Window1_SHIFT (19U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg1_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_EN_Window1_MASK (0x100000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_EN_Window1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_FG_BGn_Window1_MASK (0x200000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_FG_BGn_Window1_SHIFT (21U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx2_fg2_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_EN_Window1_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_EN_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_FG_BGn_Window1_MASK (0x2000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_FG_BGn_Window1_SHIFT (25U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg0_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_EN_Window1_MASK (0x4000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_EN_Window1_SHIFT (26U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_FG_BGn_Window1_MASK (0x8000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_FG_BGn_Window1_SHIFT (27U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg1_FG_BGn_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_EN_Window1_MASK (0x10000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_EN_Window1_SHIFT (28U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_EN_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_EN_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_EN_Window1_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_FG_BGn_Window1_MASK (0x20000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_FG_BGn_Window1_SHIFT (29U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_FG_BGn_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_FG_BGn_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW1_diseng_idhash0_idx3_fg2_FG_BGn_Window1_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONTROL_WINDOW2 - Window 2, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_Mode_Window2_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_Mode_Window2_SHIFT (0U) /*! diseng_idhash0_Mode_Window2 * 0b000..Window is disabled. The internal status for this window is reset (Error bit and frame counters). * 0b001..Window operates in Telltale mode. * 0b010..Window operates in Icon mode. * 0b011..Window operates in RGB mode. * 0b100..1bit Alpha is inserted. * 0b101..2bit Alpha is inserted. */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_Mode_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_Mode_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_Mode_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaMask_Window2_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaMask_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaMask_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaMask_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaMask_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaInv_Window2_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaInv_Window2_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaInv_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaInv_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaInv_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaSel_Window2_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaSel_Window2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaSel_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaSel_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_AlphaSel_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_LocalPanic_Window2_MASK (0xF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_LocalPanic_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_LocalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_LocalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_LocalPanic_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_GlobalPanic_Window2_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_GlobalPanic_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_GlobalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_GlobalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW2_diseng_idhash0_GlobalPanic_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_UPPERLEFT_WINDOW2 - Window 2, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW2_diseng_idhash0_UpperLeft_Y_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LOWERRIGHT_WINDOW2 - Window 2, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW2_diseng_idhash0_LowerRight_Y_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_TILE_WINDOW2 - Window 2, Tile dimensions */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_X_Window2_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_Y_Window2_MASK (0xF0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_Y_Window2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW2_diseng_idhash0_Tile_Y_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_ADDRESS_WINDOW2 - Window 2, Memory word Address for Idhash */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW2_diseng_idhash0_Address_Window2_MASK (0xFFCU) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW2_diseng_idhash0_Address_Window2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW2_diseng_idhash0_Address_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW2_diseng_idhash0_Address_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW2_diseng_idhash0_Address_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONFIG_WINDOW2 - Window 2, Idhash Configuration settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_FG_Window2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_FG_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_FG_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_FG_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_FG_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_BG_Window2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_BG_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_BG_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_BG_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Th_BG_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Tolerance_Window2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Tolerance_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Tolerance_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Tolerance_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_Tolerance_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_RGB_Th_Window2_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_RGB_Th_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_RGB_Th_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_RGB_Th_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW2_diseng_idhash0_RGB_Th_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LIMITS_WINDOW2 - Window 2, check Limit settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_SumLimit_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_SumLimit_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_SumLimit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_SumLimit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_SumLimit_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_SumLimit_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_SumLimit_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_SumLimit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_SumLimit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_SumLimit_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_WINDOW2 - Window 2, Foregound 0 Color settings. Used for Telltale mode and Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Blue_Window2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Blue_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Blue_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Blue_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Blue_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Green_Window2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Green_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Green_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Green_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Green_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Red_Window2_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Red_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Red_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Red_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW2_diseng_idhash0_Foreground0_Red_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2 - Window 2, check Limit settings for Telltale mode or for foreground color 0 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg0Limit_Window2_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg0Limit_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg0Limit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg0Limit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg0Limit_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg0Limit_Window2_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg0Limit_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg0Limit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg0Limit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg0Limit_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_WINDOW2 - Window 2, Foregound 1 Color settings, Used for Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Blue_Window2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Blue_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Blue_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Blue_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Blue_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Green_Window2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Green_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Green_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Green_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Green_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Red_Window2_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Red_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Red_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Red_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW2_diseng_idhash0_Foreground1_Red_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2 - Window 2, check Limit settings for foreground color 1 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg1Limit_Window2_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg1Limit_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg1Limit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg1Limit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg1Limit_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg1Limit_Window2_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg1Limit_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg1Limit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg1Limit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg1Limit_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_WINDOW2 - Window 2, Foregound 2 Color settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Blue_Window2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Blue_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Blue_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Blue_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Blue_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Green_Window2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Green_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Green_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Green_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Green_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Red_Window2_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Red_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Red_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Red_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW2_diseng_idhash0_Foreground2_Red_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2 - Window 2, check Limit settings for foreground color 2 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg2Limit_Window2_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg2Limit_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg2Limit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg2Limit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_FG_cnt_Fg2Limit_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg2Limit_Window2_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg2Limit_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg2Limit_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg2Limit_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW2_diseng_idhash0_Drop_cnt_Fg2Limit_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_IDX_TABLE_WINDOW2 - Window 2, Index Table */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_EN_Window2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_EN_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_FG_BGn_Window2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_FG_BGn_Window2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg0_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_EN_Window2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_EN_Window2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_FG_BGn_Window2_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_FG_BGn_Window2_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg1_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_EN_Window2_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_EN_Window2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_FG_BGn_Window2_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_FG_BGn_Window2_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx0_fg2_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_EN_Window2_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_EN_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_FG_BGn_Window2_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_FG_BGn_Window2_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg0_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_EN_Window2_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_EN_Window2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_FG_BGn_Window2_MASK (0x800U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_FG_BGn_Window2_SHIFT (11U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg1_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_EN_Window2_MASK (0x1000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_EN_Window2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_FG_BGn_Window2_MASK (0x2000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_FG_BGn_Window2_SHIFT (13U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx1_fg2_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_EN_Window2_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_EN_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_FG_BGn_Window2_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_FG_BGn_Window2_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg0_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_EN_Window2_MASK (0x40000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_EN_Window2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_FG_BGn_Window2_MASK (0x80000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_FG_BGn_Window2_SHIFT (19U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg1_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_EN_Window2_MASK (0x100000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_EN_Window2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_FG_BGn_Window2_MASK (0x200000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_FG_BGn_Window2_SHIFT (21U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx2_fg2_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_EN_Window2_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_EN_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_FG_BGn_Window2_MASK (0x2000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_FG_BGn_Window2_SHIFT (25U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg0_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_EN_Window2_MASK (0x4000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_EN_Window2_SHIFT (26U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_FG_BGn_Window2_MASK (0x8000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_FG_BGn_Window2_SHIFT (27U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg1_FG_BGn_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_EN_Window2_MASK (0x10000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_EN_Window2_SHIFT (28U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_EN_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_EN_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_EN_Window2_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_FG_BGn_Window2_MASK (0x20000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_FG_BGn_Window2_SHIFT (29U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_FG_BGn_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_FG_BGn_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW2_diseng_idhash0_idx3_fg2_FG_BGn_Window2_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONTROL_WINDOW3 - Window 3, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_Mode_Window3_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_Mode_Window3_SHIFT (0U) /*! diseng_idhash0_Mode_Window3 * 0b000..Window is disabled. The internal status for this window is reset (Error bit and frame counters). * 0b001..Window operates in Telltale mode. * 0b010..Window operates in Icon mode. * 0b011..Window operates in RGB mode. * 0b100..1bit Alpha is inserted. * 0b101..2bit Alpha is inserted. */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_Mode_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_Mode_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_Mode_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaMask_Window3_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaMask_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaMask_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaMask_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaMask_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaInv_Window3_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaInv_Window3_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaInv_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaInv_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaInv_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaSel_Window3_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaSel_Window3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaSel_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaSel_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_AlphaSel_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_LocalPanic_Window3_MASK (0xF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_LocalPanic_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_LocalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_LocalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_LocalPanic_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_GlobalPanic_Window3_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_GlobalPanic_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_GlobalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_GlobalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONTROL_WINDOW3_diseng_idhash0_GlobalPanic_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_UPPERLEFT_WINDOW3 - Window 3, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_UPPERLEFT_WINDOW3_diseng_idhash0_UpperLeft_Y_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LOWERRIGHT_WINDOW3 - Window 3, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LOWERRIGHT_WINDOW3_diseng_idhash0_LowerRight_Y_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_TILE_WINDOW3 - Window 3, Tile dimensions */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_X_Window3_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_Y_Window3_MASK (0xF0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_Y_Window3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_TILE_WINDOW3_diseng_idhash0_Tile_Y_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_ADDRESS_WINDOW3 - Window 3, Memory word Address for Idhash */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW3_diseng_idhash0_Address_Window3_MASK (0xFFCU) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW3_diseng_idhash0_Address_Window3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW3_diseng_idhash0_Address_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW3_diseng_idhash0_Address_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_ADDRESS_WINDOW3_diseng_idhash0_Address_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_CONFIG_WINDOW3 - Window 3, Idhash Configuration settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_FG_Window3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_FG_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_FG_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_FG_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_FG_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_BG_Window3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_BG_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_BG_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_BG_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Th_BG_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Tolerance_Window3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Tolerance_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Tolerance_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Tolerance_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_Tolerance_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_RGB_Th_Window3_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_RGB_Th_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_RGB_Th_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_RGB_Th_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_CONFIG_WINDOW3_diseng_idhash0_RGB_Th_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_LIMITS_WINDOW3 - Window 3, check Limit settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_SumLimit_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_SumLimit_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_SumLimit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_SumLimit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_SumLimit_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_SumLimit_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_SumLimit_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_SumLimit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_SumLimit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_SumLimit_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_WINDOW3 - Window 3, Foregound 0 Color settings. Used for Telltale mode and Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Blue_Window3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Blue_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Blue_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Blue_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Blue_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Green_Window3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Green_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Green_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Green_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Green_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Red_Window3_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Red_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Red_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Red_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_WINDOW3_diseng_idhash0_Foreground0_Red_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3 - Window 3, check Limit settings for Telltale mode or for foreground color 0 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg0Limit_Window3_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg0Limit_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg0Limit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg0Limit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg0Limit_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg0Limit_Window3_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg0Limit_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg0Limit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg0Limit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND0_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg0Limit_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_WINDOW3 - Window 3, Foregound 1 Color settings, Used for Icon Mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Blue_Window3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Blue_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Blue_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Blue_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Blue_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Green_Window3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Green_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Green_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Green_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Green_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Red_Window3_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Red_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Red_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Red_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_WINDOW3_diseng_idhash0_Foreground1_Red_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3 - Window 3, check Limit settings for foreground color 1 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg1Limit_Window3_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg1Limit_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg1Limit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg1Limit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg1Limit_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg1Limit_Window3_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg1Limit_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg1Limit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg1Limit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND1_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg1Limit_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_WINDOW3 - Window 3, Foregound 2 Color settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Blue_Window3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Blue_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Blue_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Blue_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Blue_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Green_Window3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Green_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Green_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Green_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Green_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Red_Window3_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Red_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Red_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Red_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_WINDOW3_diseng_idhash0_Foreground2_Red_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3 - Window 3, check Limit settings for foreground color 2 in icon mode. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg2Limit_Window3_MASK (0xFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg2Limit_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg2Limit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg2Limit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_FG_cnt_Fg2Limit_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg2Limit_Window3_MASK (0xFFF0000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg2Limit_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg2Limit_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg2Limit_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_FOREGROUND2_LIMITS_WINDOW3_diseng_idhash0_Drop_cnt_Fg2Limit_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_IDX_TABLE_WINDOW3 - Window 3, Index Table */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_EN_Window3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_EN_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_FG_BGn_Window3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_FG_BGn_Window3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg0_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_EN_Window3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_EN_Window3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_FG_BGn_Window3_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_FG_BGn_Window3_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg1_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_EN_Window3_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_EN_Window3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_FG_BGn_Window3_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_FG_BGn_Window3_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx0_fg2_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_EN_Window3_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_EN_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_FG_BGn_Window3_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_FG_BGn_Window3_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg0_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_EN_Window3_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_EN_Window3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_FG_BGn_Window3_MASK (0x800U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_FG_BGn_Window3_SHIFT (11U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg1_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_EN_Window3_MASK (0x1000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_EN_Window3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_FG_BGn_Window3_MASK (0x2000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_FG_BGn_Window3_SHIFT (13U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx1_fg2_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_EN_Window3_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_EN_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_FG_BGn_Window3_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_FG_BGn_Window3_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg0_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_EN_Window3_MASK (0x40000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_EN_Window3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_FG_BGn_Window3_MASK (0x80000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_FG_BGn_Window3_SHIFT (19U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg1_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_EN_Window3_MASK (0x100000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_EN_Window3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_FG_BGn_Window3_MASK (0x200000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_FG_BGn_Window3_SHIFT (21U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx2_fg2_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_EN_Window3_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_EN_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_FG_BGn_Window3_MASK (0x2000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_FG_BGn_Window3_SHIFT (25U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg0_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_EN_Window3_MASK (0x4000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_EN_Window3_SHIFT (26U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_FG_BGn_Window3_MASK (0x8000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_FG_BGn_Window3_SHIFT (27U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg1_FG_BGn_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_EN_Window3_MASK (0x10000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_EN_Window3_SHIFT (28U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_EN_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_EN_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_EN_Window3_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_FG_BGn_Window3_MASK (0x20000000U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_FG_BGn_Window3_SHIFT (29U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_FG_BGn_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_FG_BGn_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDX_TABLE_WINDOW3_diseng_idhash0_idx3_fg2_FG_BGn_Window3_MASK) /*! @} */ /*! @name DISENG_IDHASH0_IDRAM - SRAM, usage according to module register setup. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDRAM_diseng_idhash0_data_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDRAM_diseng_idhash0_data_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0_IDRAM_diseng_idhash0_data(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0_IDRAM_diseng_idhash0_data_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0_IDRAM_diseng_idhash0_data_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_DISENG_IDHASH0_IDRAM */ #define DISPLAY_SEERIS_DISENG_IDHASH0_IDRAM_COUNT (1024U) /*! @name DISENG_IDHASH0CFG_LOCKUNLOCK0 - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKUNLOCK0_diseng_idhash0cfg_LockUnlock0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKUNLOCK0_diseng_idhash0cfg_LockUnlock0_SHIFT (0U) /*! diseng_idhash0cfg_LockUnlock0 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKUNLOCK0_diseng_idhash0cfg_LockUnlock0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKUNLOCK0_diseng_idhash0cfg_LockUnlock0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKUNLOCK0_diseng_idhash0cfg_LockUnlock0_MASK) /*! @} */ /*! @name DISENG_IDHASH0CFG_LOCKSTATUS0 - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_LockStatus0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_LockStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_LockStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_LockStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_LockStatus0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_PrivilegeStatus0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_PrivilegeStatus0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_PrivilegeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_PrivilegeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_PrivilegeStatus0_MASK) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_FreezeStatus0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_FreezeStatus0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_FreezeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_FreezeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0CFG_LOCKSTATUS0_diseng_idhash0cfg_FreezeStatus0_MASK) /*! @} */ /*! @name DISENG_IDHASH0CFG_SRCSELECT - Tap selection for IDHash0. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_SRCSELECT_diseng_idhash0cfg_idhash0_select_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_SRCSELECT_diseng_idhash0cfg_idhash0_select_SHIFT (0U) /*! diseng_idhash0cfg_idhash0_select * 0b00..Source is FrameGen#0 output. * 0b01..Source is Matrix#0 output. * 0b10..Source is LuT3D#0 output. * 0b11..Source is Dither#0 output. */ #define DISPLAY_SEERIS_DISENG_IDHASH0CFG_SRCSELECT_diseng_idhash0cfg_idhash0_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_IDHASH0CFG_SRCSELECT_diseng_idhash0cfg_idhash0_select_SHIFT)) & DISPLAY_SEERIS_DISENG_IDHASH0CFG_SRCSELECT_diseng_idhash0cfg_idhash0_select_MASK) /*! @} */ /*! @name DISENG_SIG0_LOCKUNLOCK - Register to change the protection status of this address block */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOCKUNLOCK_diseng_sig0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKUNLOCK_diseng_sig0_LockUnlock_SHIFT (0U) /*! diseng_sig0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_SIG0_LOCKUNLOCK_diseng_sig0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOCKUNLOCK_diseng_sig0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOCKUNLOCK_diseng_sig0_LockUnlock_MASK) /*! @} */ /*! @name DISENG_SIG0_LOCKSTATUS - Protection status of this address block */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOCKSTATUS_diseng_sig0_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_SIG0_STATICCONTROL - Global configuration */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdEn_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdLdSel_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdLdSel_SHIFT (4U) /*! diseng_sig0_ShdLdSel * 0b0..Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. * 0b1..Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). */ #define DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATICCONTROL_diseng_sig0_ShdLdSel_MASK) /*! @} */ /*! @name DISENG_SIG0_ERRORTHRESHOLD - Set and reset thresholds applying to Window_Error and Cluster_Error interrupts and status bits */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThres_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThres_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThres(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThres_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThres_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThresReset_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThresReset_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThresReset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThresReset_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_ERRORTHRESHOLD_diseng_sig0_ErrThresReset_MASK) /*! @} */ /*! @name DISENG_SIG0_MATCHTHRESHOLD - Set and reset thresholds applying to Match interrupt and status bits */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThres_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThres_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThres(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThres_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThres_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThresReset_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThresReset_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThresReset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThresReset_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MATCHTHRESHOLD_diseng_sig0_MatchThresReset_MASK) /*! @} */ /*! @name DISENG_SIG0_PANICCOLOR - Overlay color for evaluation windows in panic mode */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicAlpha_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicAlpha_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicBlue_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicBlue_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicBlue_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicGreen_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicGreen_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicGreen_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicRed_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicRed_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PANICCOLOR_diseng_sig0_PanicRed_MASK) /*! @} */ /*! @name DISENG_SIG0_SHADOWLOAD - Shadow load control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_SHADOWLOAD_diseng_sig0_ShdLdReq_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_SHADOWLOAD_diseng_sig0_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_SHADOWLOAD_diseng_sig0_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_SHADOWLOAD_diseng_sig0_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_SHADOWLOAD_diseng_sig0_ShdLdReq_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTINUOUSMODE - Signature operation mode control */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTINUOUSMODE_diseng_sig0_EnCont_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTINUOUSMODE_diseng_sig0_EnCont_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTINUOUSMODE_diseng_sig0_EnCont(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTINUOUSMODE_diseng_sig0_EnCont_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTINUOUSMODE_diseng_sig0_EnCont_MASK) /*! @} */ /*! @name DISENG_SIG0_SOFTWAREKICK - Signature measurement trigger */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_SOFTWAREKICK_diseng_sig0_Kick_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_SOFTWAREKICK_diseng_sig0_Kick_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_SOFTWAREKICK_diseng_sig0_Kick(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_SOFTWAREKICK_diseng_sig0_Kick_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_SOFTWAREKICK_diseng_sig0_Kick_MASK) /*! @} */ /*! @name DISENG_SIG0_SKIPWINDOW - Enable skipping window feature. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_SKIPWINDOW_diseng_sig0_SkipWinEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_SKIPWINDOW_diseng_sig0_SkipWinEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_SKIPWINDOW_diseng_sig0_SkipWinEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_SKIPWINDOW_diseng_sig0_SkipWinEn_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_SKIPWINDOW_diseng_sig0_SkipWinEn_MASK) /*! @} */ /*! @name DISENG_SIG0_STATUS - Signature evaluation status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigState_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigState_SHIFT (0U) /*! diseng_sig0_SigState * 0b0..Signature is in idle state * 0b1..Signature is in run state */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigState(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigState_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigState_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigValid_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigValid_SHIFT (1U) /*! diseng_sig0_SigValid * 0b0..Signature results are not valid * 0b1..Signature results are valid */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigValid(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigValid_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_SigValid_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Window_Error_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Window_Error_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Window_Error(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Window_Error_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Window_Error_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Error_MASK (0xF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Error_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Error(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Error_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Error_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Match_MASK (0xF00000U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Match_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Match(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Match_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_diseng_sig0_Cluster_Match_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW0 - Window 0, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_En_Window0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_En_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_En_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_En_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_En_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_CRC_Window0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_CRC_Window0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_CRC_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_CRC_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_CRC_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaMask_Window0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaMask_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaMask_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaMask_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaMask_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaInv_Window0_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaInv_Window0_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaInv_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaInv_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaInv_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaSel_Window0_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaSel_Window0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaSel_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaSel_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_AlphaSel_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_LocalPanic_Window0_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_LocalPanic_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_LocalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_LocalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_LocalPanic_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_GlobalPanic_Window0_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_GlobalPanic_Window0_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_GlobalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_GlobalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_GlobalPanic_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_Sum_Window0_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_Sum_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_Sum_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_Sum_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW0_diseng_sig0_Sum_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW0 - Window 0, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW0_diseng_sig0_UpperLeft_Y_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW0 - Window 0, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW0_diseng_sig0_LowerRight_Y_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW0 - Window 0, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW0_diseng_sig0_Ref_R_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW0_diseng_sig0_Ref_R_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW0_diseng_sig0_Ref_R_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW0_diseng_sig0_Ref_R_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW0_diseng_sig0_Ref_R_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW0 - Window 0, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW0_diseng_sig0_Ref_G_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW0_diseng_sig0_Ref_G_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW0_diseng_sig0_Ref_G_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW0_diseng_sig0_Ref_G_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW0_diseng_sig0_Ref_G_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW0 - Window 0, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW0_diseng_sig0_Ref_B_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW0_diseng_sig0_Ref_B_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW0_diseng_sig0_Ref_B_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW0_diseng_sig0_Ref_B_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW0_diseng_sig0_Ref_B_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS0_WINDOW0 - Controls of Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaMask_S0_Win0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaMask_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaMask_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaMask_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaMask_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaInv_S0_Win0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaInv_S0_Win0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaInv_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaInv_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaInv_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaSel_S0_Win0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaSel_S0_Win0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaSel_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaSel_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW0_diseng_sig0_AlphaSel_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS1_WINDOW0 - Controls of Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaMask_S1_Win0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaMask_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaMask_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaMask_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaMask_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaInv_S1_Win0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaInv_S1_Win0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaInv_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaInv_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaInv_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaSel_S1_Win0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaSel_S1_Win0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaSel_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaSel_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW0_diseng_sig0_AlphaSel_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_REDSUM_WINDOW0 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW0_diseng_sig0_Min_RSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW0_diseng_sig0_Min_RSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW0_diseng_sig0_Min_RSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW0_diseng_sig0_Min_RSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW0_diseng_sig0_Min_RSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_GREENSUM_WINDOW0 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW0_diseng_sig0_Min_GSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW0_diseng_sig0_Min_GSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW0_diseng_sig0_Min_GSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW0_diseng_sig0_Min_GSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW0_diseng_sig0_Min_GSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_BLUESUM_WINDOW0 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW0_diseng_sig0_Min_BSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW0_diseng_sig0_Min_BSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW0_diseng_sig0_Min_BSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW0_diseng_sig0_Min_BSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW0_diseng_sig0_Min_BSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_LUMSUM_WINDOW0 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW0_diseng_sig0_Min_LSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW0_diseng_sig0_Min_LSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW0_diseng_sig0_Min_LSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW0_diseng_sig0_Min_LSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW0_diseng_sig0_Min_LSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_REDSUM_WINDOW0 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW0_diseng_sig0_Max_RSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW0_diseng_sig0_Max_RSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW0_diseng_sig0_Max_RSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW0_diseng_sig0_Max_RSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW0_diseng_sig0_Max_RSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_GREENSUM_WINDOW0 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW0_diseng_sig0_Max_GSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW0_diseng_sig0_Max_GSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW0_diseng_sig0_Max_GSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW0_diseng_sig0_Max_GSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW0_diseng_sig0_Max_GSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_BLUESUM_WINDOW0 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW0_diseng_sig0_Max_BSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW0_diseng_sig0_Max_BSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW0_diseng_sig0_Max_BSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW0_diseng_sig0_Max_BSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW0_diseng_sig0_Max_BSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_LUMSUM_WINDOW0 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW0_diseng_sig0_Max_LSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW0_diseng_sig0_Max_LSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW0_diseng_sig0_Max_LSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW0_diseng_sig0_Max_LSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW0_diseng_sig0_Max_LSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW1 - Window 1, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_En_Window1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_En_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_En_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_En_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_En_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_CRC_Window1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_CRC_Window1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_CRC_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_CRC_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_CRC_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaMask_Window1_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaMask_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaMask_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaMask_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaMask_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaInv_Window1_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaInv_Window1_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaInv_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaInv_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaInv_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaSel_Window1_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaSel_Window1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaSel_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaSel_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_AlphaSel_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_LocalPanic_Window1_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_LocalPanic_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_LocalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_LocalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_LocalPanic_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_GlobalPanic_Window1_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_GlobalPanic_Window1_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_GlobalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_GlobalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_GlobalPanic_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_Sum_Window1_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_Sum_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_Sum_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_Sum_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW1_diseng_sig0_Sum_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW1 - Window 1, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW1_diseng_sig0_UpperLeft_Y_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW1 - Window 1, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW1_diseng_sig0_LowerRight_Y_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW1 - Window 1, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW1_diseng_sig0_Ref_R_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW1_diseng_sig0_Ref_R_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW1_diseng_sig0_Ref_R_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW1_diseng_sig0_Ref_R_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW1_diseng_sig0_Ref_R_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW1 - Window 1, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW1_diseng_sig0_Ref_G_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW1_diseng_sig0_Ref_G_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW1_diseng_sig0_Ref_G_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW1_diseng_sig0_Ref_G_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW1_diseng_sig0_Ref_G_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW1 - Window 1, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW1_diseng_sig0_Ref_B_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW1_diseng_sig0_Ref_B_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW1_diseng_sig0_Ref_B_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW1_diseng_sig0_Ref_B_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW1_diseng_sig0_Ref_B_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS0_WINDOW1 - Controls of Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaMask_S0_Win1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaMask_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaMask_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaMask_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaMask_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaInv_S0_Win1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaInv_S0_Win1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaInv_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaInv_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaInv_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaSel_S0_Win1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaSel_S0_Win1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaSel_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaSel_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW1_diseng_sig0_AlphaSel_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS1_WINDOW1 - Controls of Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaMask_S1_Win1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaMask_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaMask_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaMask_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaMask_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaInv_S1_Win1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaInv_S1_Win1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaInv_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaInv_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaInv_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaSel_S1_Win1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaSel_S1_Win1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaSel_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaSel_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW1_diseng_sig0_AlphaSel_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_REDSUM_WINDOW1 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW1_diseng_sig0_Min_RSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW1_diseng_sig0_Min_RSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW1_diseng_sig0_Min_RSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW1_diseng_sig0_Min_RSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW1_diseng_sig0_Min_RSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_GREENSUM_WINDOW1 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW1_diseng_sig0_Min_GSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW1_diseng_sig0_Min_GSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW1_diseng_sig0_Min_GSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW1_diseng_sig0_Min_GSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW1_diseng_sig0_Min_GSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_BLUESUM_WINDOW1 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW1_diseng_sig0_Min_BSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW1_diseng_sig0_Min_BSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW1_diseng_sig0_Min_BSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW1_diseng_sig0_Min_BSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW1_diseng_sig0_Min_BSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_LUMSUM_WINDOW1 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW1_diseng_sig0_Min_LSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW1_diseng_sig0_Min_LSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW1_diseng_sig0_Min_LSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW1_diseng_sig0_Min_LSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW1_diseng_sig0_Min_LSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_REDSUM_WINDOW1 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW1_diseng_sig0_Max_RSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW1_diseng_sig0_Max_RSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW1_diseng_sig0_Max_RSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW1_diseng_sig0_Max_RSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW1_diseng_sig0_Max_RSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_GREENSUM_WINDOW1 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW1_diseng_sig0_Max_GSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW1_diseng_sig0_Max_GSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW1_diseng_sig0_Max_GSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW1_diseng_sig0_Max_GSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW1_diseng_sig0_Max_GSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_BLUESUM_WINDOW1 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW1_diseng_sig0_Max_BSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW1_diseng_sig0_Max_BSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW1_diseng_sig0_Max_BSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW1_diseng_sig0_Max_BSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW1_diseng_sig0_Max_BSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_LUMSUM_WINDOW1 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW1_diseng_sig0_Max_LSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW1_diseng_sig0_Max_LSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW1_diseng_sig0_Max_LSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW1_diseng_sig0_Max_LSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW1_diseng_sig0_Max_LSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW2 - Window 2, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_En_Window2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_En_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_En_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_En_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_En_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_CRC_Window2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_CRC_Window2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_CRC_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_CRC_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_CRC_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaMask_Window2_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaMask_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaMask_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaMask_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaMask_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaInv_Window2_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaInv_Window2_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaInv_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaInv_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaInv_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaSel_Window2_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaSel_Window2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaSel_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaSel_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_AlphaSel_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_LocalPanic_Window2_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_LocalPanic_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_LocalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_LocalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_LocalPanic_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_GlobalPanic_Window2_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_GlobalPanic_Window2_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_GlobalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_GlobalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_GlobalPanic_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_Sum_Window2_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_Sum_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_Sum_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_Sum_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW2_diseng_sig0_Sum_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW2 - Window 2, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW2_diseng_sig0_UpperLeft_Y_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW2 - Window 2, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW2_diseng_sig0_LowerRight_Y_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW2 - Window 2, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW2_diseng_sig0_Ref_R_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW2_diseng_sig0_Ref_R_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW2_diseng_sig0_Ref_R_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW2_diseng_sig0_Ref_R_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW2_diseng_sig0_Ref_R_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW2 - Window 2, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW2_diseng_sig0_Ref_G_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW2_diseng_sig0_Ref_G_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW2_diseng_sig0_Ref_G_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW2_diseng_sig0_Ref_G_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW2_diseng_sig0_Ref_G_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW2 - Window 2, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW2_diseng_sig0_Ref_B_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW2_diseng_sig0_Ref_B_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW2_diseng_sig0_Ref_B_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW2_diseng_sig0_Ref_B_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW2_diseng_sig0_Ref_B_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS0_WINDOW2 - Controls of Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaMask_S0_Win2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaMask_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaMask_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaMask_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaMask_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaInv_S0_Win2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaInv_S0_Win2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaInv_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaInv_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaInv_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaSel_S0_Win2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaSel_S0_Win2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaSel_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaSel_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW2_diseng_sig0_AlphaSel_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS1_WINDOW2 - Controls of Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaMask_S1_Win2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaMask_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaMask_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaMask_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaMask_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaInv_S1_Win2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaInv_S1_Win2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaInv_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaInv_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaInv_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaSel_S1_Win2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaSel_S1_Win2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaSel_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaSel_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW2_diseng_sig0_AlphaSel_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_REDSUM_WINDOW2 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW2_diseng_sig0_Min_RSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW2_diseng_sig0_Min_RSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW2_diseng_sig0_Min_RSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW2_diseng_sig0_Min_RSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW2_diseng_sig0_Min_RSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_GREENSUM_WINDOW2 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW2_diseng_sig0_Min_GSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW2_diseng_sig0_Min_GSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW2_diseng_sig0_Min_GSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW2_diseng_sig0_Min_GSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW2_diseng_sig0_Min_GSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_BLUESUM_WINDOW2 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW2_diseng_sig0_Min_BSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW2_diseng_sig0_Min_BSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW2_diseng_sig0_Min_BSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW2_diseng_sig0_Min_BSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW2_diseng_sig0_Min_BSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_LUMSUM_WINDOW2 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW2_diseng_sig0_Min_LSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW2_diseng_sig0_Min_LSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW2_diseng_sig0_Min_LSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW2_diseng_sig0_Min_LSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW2_diseng_sig0_Min_LSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_REDSUM_WINDOW2 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW2_diseng_sig0_Max_RSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW2_diseng_sig0_Max_RSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW2_diseng_sig0_Max_RSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW2_diseng_sig0_Max_RSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW2_diseng_sig0_Max_RSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_GREENSUM_WINDOW2 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW2_diseng_sig0_Max_GSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW2_diseng_sig0_Max_GSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW2_diseng_sig0_Max_GSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW2_diseng_sig0_Max_GSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW2_diseng_sig0_Max_GSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_BLUESUM_WINDOW2 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW2_diseng_sig0_Max_BSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW2_diseng_sig0_Max_BSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW2_diseng_sig0_Max_BSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW2_diseng_sig0_Max_BSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW2_diseng_sig0_Max_BSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_LUMSUM_WINDOW2 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW2_diseng_sig0_Max_LSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW2_diseng_sig0_Max_LSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW2_diseng_sig0_Max_LSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW2_diseng_sig0_Max_LSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW2_diseng_sig0_Max_LSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW3 - Window 3, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_En_Window3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_En_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_En_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_En_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_En_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_CRC_Window3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_CRC_Window3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_CRC_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_CRC_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_CRC_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaMask_Window3_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaMask_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaMask_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaMask_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaMask_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaInv_Window3_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaInv_Window3_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaInv_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaInv_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaInv_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaSel_Window3_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaSel_Window3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaSel_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaSel_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_AlphaSel_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_LocalPanic_Window3_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_LocalPanic_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_LocalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_LocalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_LocalPanic_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_GlobalPanic_Window3_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_GlobalPanic_Window3_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_GlobalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_GlobalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_GlobalPanic_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_Sum_Window3_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_Sum_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_Sum_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_Sum_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW3_diseng_sig0_Sum_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW3 - Window 3, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW3_diseng_sig0_UpperLeft_Y_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW3 - Window 3, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW3_diseng_sig0_LowerRight_Y_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW3 - Window 3, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW3_diseng_sig0_Ref_R_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW3_diseng_sig0_Ref_R_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW3_diseng_sig0_Ref_R_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW3_diseng_sig0_Ref_R_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW3_diseng_sig0_Ref_R_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW3 - Window 3, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW3_diseng_sig0_Ref_G_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW3_diseng_sig0_Ref_G_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW3_diseng_sig0_Ref_G_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW3_diseng_sig0_Ref_G_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW3_diseng_sig0_Ref_G_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW3 - Window 3, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW3_diseng_sig0_Ref_B_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW3_diseng_sig0_Ref_B_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW3_diseng_sig0_Ref_B_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW3_diseng_sig0_Ref_B_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW3_diseng_sig0_Ref_B_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS0_WINDOW3 - Controls of Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaMask_S0_Win3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaMask_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaMask_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaMask_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaMask_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaInv_S0_Win3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaInv_S0_Win3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaInv_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaInv_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaInv_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaSel_S0_Win3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaSel_S0_Win3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaSel_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaSel_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS0_WINDOW3_diseng_sig0_AlphaSel_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_STATS1_WINDOW3 - Controls of Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaMask_S1_Win3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaMask_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaMask_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaMask_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaMask_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaInv_S1_Win3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaInv_S1_Win3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaInv_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaInv_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaInv_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaSel_S1_Win3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaSel_S1_Win3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaSel_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaSel_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATS1_WINDOW3_diseng_sig0_AlphaSel_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_REDSUM_WINDOW3 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW3_diseng_sig0_Min_RSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW3_diseng_sig0_Min_RSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW3_diseng_sig0_Min_RSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW3_diseng_sig0_Min_RSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_REDSUM_WINDOW3_diseng_sig0_Min_RSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_GREENSUM_WINDOW3 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW3_diseng_sig0_Min_GSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW3_diseng_sig0_Min_GSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW3_diseng_sig0_Min_GSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW3_diseng_sig0_Min_GSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_GREENSUM_WINDOW3_diseng_sig0_Min_GSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_BLUESUM_WINDOW3 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW3_diseng_sig0_Min_BSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW3_diseng_sig0_Min_BSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW3_diseng_sig0_Min_BSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW3_diseng_sig0_Min_BSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_BLUESUM_WINDOW3_diseng_sig0_Min_BSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MIN_LUMSUM_WINDOW3 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW3_diseng_sig0_Min_LSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW3_diseng_sig0_Min_LSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW3_diseng_sig0_Min_LSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW3_diseng_sig0_Min_LSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MIN_LUMSUM_WINDOW3_diseng_sig0_Min_LSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_REDSUM_WINDOW3 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW3_diseng_sig0_Max_RSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW3_diseng_sig0_Max_RSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW3_diseng_sig0_Max_RSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW3_diseng_sig0_Max_RSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_REDSUM_WINDOW3_diseng_sig0_Max_RSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_GREENSUM_WINDOW3 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW3_diseng_sig0_Max_GSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW3_diseng_sig0_Max_GSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW3_diseng_sig0_Max_GSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW3_diseng_sig0_Max_GSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_GREENSUM_WINDOW3_diseng_sig0_Max_GSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_BLUESUM_WINDOW3 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW3_diseng_sig0_Max_BSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW3_diseng_sig0_Max_BSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW3_diseng_sig0_Max_BSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW3_diseng_sig0_Max_BSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_BLUESUM_WINDOW3_diseng_sig0_Max_BSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_MAX_LUMSUM_WINDOW3 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW3_diseng_sig0_Max_LSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW3_diseng_sig0_Max_LSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW3_diseng_sig0_Max_LSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW3_diseng_sig0_Max_LSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_MAX_LUMSUM_WINDOW3_diseng_sig0_Max_LSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW4 - Window 4, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_En_Window4_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_En_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_En_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_En_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_En_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_CRC_Window4_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_CRC_Window4_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_CRC_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_CRC_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_CRC_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaMask_Window4_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaMask_Window4_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaMask_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaMask_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaMask_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaInv_Window4_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaInv_Window4_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaInv_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaInv_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaInv_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaSel_Window4_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaSel_Window4_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaSel_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaSel_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_AlphaSel_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_LocalPanic_Window4_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_LocalPanic_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_LocalPanic_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_LocalPanic_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_LocalPanic_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_GlobalPanic_Window4_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_GlobalPanic_Window4_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_GlobalPanic_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_GlobalPanic_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW4_diseng_sig0_GlobalPanic_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW4 - Window 4, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_X_Window4_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_X_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_X_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_X_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_X_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_Y_Window4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_Y_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_Y_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_Y_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW4_diseng_sig0_UpperLeft_Y_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW4 - Window 4, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_X_Window4_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_X_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_X_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_X_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_X_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_Y_Window4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_Y_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_Y_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_Y_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW4_diseng_sig0_LowerRight_Y_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW4 - Window 4, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW4_diseng_sig0_Ref_R_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW4_diseng_sig0_Ref_R_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW4_diseng_sig0_Ref_R_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW4_diseng_sig0_Ref_R_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW4_diseng_sig0_Ref_R_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW4 - Window 4, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW4_diseng_sig0_Ref_G_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW4_diseng_sig0_Ref_G_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW4_diseng_sig0_Ref_G_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW4_diseng_sig0_Ref_G_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW4_diseng_sig0_Ref_G_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW4 - Window 4, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW4_diseng_sig0_Ref_B_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW4_diseng_sig0_Ref_B_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW4_diseng_sig0_Ref_B_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW4_diseng_sig0_Ref_B_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW4_diseng_sig0_Ref_B_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW5 - Window 5, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_En_Window5_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_En_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_En_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_En_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_En_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_CRC_Window5_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_CRC_Window5_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_CRC_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_CRC_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_CRC_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaMask_Window5_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaMask_Window5_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaMask_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaMask_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaMask_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaInv_Window5_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaInv_Window5_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaInv_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaInv_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaInv_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaSel_Window5_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaSel_Window5_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaSel_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaSel_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_AlphaSel_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_LocalPanic_Window5_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_LocalPanic_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_LocalPanic_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_LocalPanic_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_LocalPanic_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_GlobalPanic_Window5_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_GlobalPanic_Window5_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_GlobalPanic_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_GlobalPanic_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW5_diseng_sig0_GlobalPanic_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW5 - Window 5, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_X_Window5_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_X_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_X_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_X_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_X_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_Y_Window5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_Y_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_Y_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_Y_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW5_diseng_sig0_UpperLeft_Y_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW5 - Window 5, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_X_Window5_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_X_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_X_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_X_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_X_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_Y_Window5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_Y_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_Y_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_Y_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW5_diseng_sig0_LowerRight_Y_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW5 - Window 5, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW5_diseng_sig0_Ref_R_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW5_diseng_sig0_Ref_R_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW5_diseng_sig0_Ref_R_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW5_diseng_sig0_Ref_R_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW5_diseng_sig0_Ref_R_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW5 - Window 5, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW5_diseng_sig0_Ref_G_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW5_diseng_sig0_Ref_G_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW5_diseng_sig0_Ref_G_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW5_diseng_sig0_Ref_G_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW5_diseng_sig0_Ref_G_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW5 - Window 5, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW5_diseng_sig0_Ref_B_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW5_diseng_sig0_Ref_B_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW5_diseng_sig0_Ref_B_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW5_diseng_sig0_Ref_B_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW5_diseng_sig0_Ref_B_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW6 - Window 6, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_En_Window6_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_En_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_En_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_En_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_En_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_CRC_Window6_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_CRC_Window6_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_CRC_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_CRC_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_CRC_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaMask_Window6_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaMask_Window6_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaMask_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaMask_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaMask_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaInv_Window6_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaInv_Window6_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaInv_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaInv_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaInv_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaSel_Window6_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaSel_Window6_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaSel_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaSel_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_AlphaSel_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_LocalPanic_Window6_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_LocalPanic_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_LocalPanic_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_LocalPanic_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_LocalPanic_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_GlobalPanic_Window6_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_GlobalPanic_Window6_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_GlobalPanic_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_GlobalPanic_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW6_diseng_sig0_GlobalPanic_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW6 - Window 6, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_X_Window6_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_X_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_X_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_X_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_X_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_Y_Window6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_Y_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_Y_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_Y_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW6_diseng_sig0_UpperLeft_Y_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW6 - Window 6, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_X_Window6_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_X_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_X_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_X_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_X_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_Y_Window6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_Y_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_Y_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_Y_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW6_diseng_sig0_LowerRight_Y_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW6 - Window 6, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW6_diseng_sig0_Ref_R_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW6_diseng_sig0_Ref_R_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW6_diseng_sig0_Ref_R_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW6_diseng_sig0_Ref_R_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW6_diseng_sig0_Ref_R_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW6 - Window 6, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW6_diseng_sig0_Ref_G_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW6_diseng_sig0_Ref_G_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW6_diseng_sig0_Ref_G_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW6_diseng_sig0_Ref_G_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW6_diseng_sig0_Ref_G_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW6 - Window 6, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW6_diseng_sig0_Ref_B_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW6_diseng_sig0_Ref_B_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW6_diseng_sig0_Ref_B_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW6_diseng_sig0_Ref_B_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW6_diseng_sig0_Ref_B_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_WINDOW7 - Window 7, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_En_Window7_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_En_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_En_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_En_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_En_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_CRC_Window7_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_CRC_Window7_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_CRC_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_CRC_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_CRC_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaMask_Window7_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaMask_Window7_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaMask_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaMask_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaMask_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaInv_Window7_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaInv_Window7_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaInv_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaInv_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaInv_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaSel_Window7_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaSel_Window7_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaSel_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaSel_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_AlphaSel_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_LocalPanic_Window7_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_LocalPanic_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_LocalPanic_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_LocalPanic_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_LocalPanic_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_GlobalPanic_Window7_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_GlobalPanic_Window7_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_GlobalPanic_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_GlobalPanic_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_WINDOW7_diseng_sig0_GlobalPanic_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_UPPERLEFT_WINDOW7 - Window 7, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_X_Window7_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_X_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_X_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_X_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_X_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_Y_Window7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_Y_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_Y_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_Y_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_UPPERLEFT_WINDOW7_diseng_sig0_UpperLeft_Y_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_LOWERRIGHT_WINDOW7 - Window 7, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_X_Window7_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_X_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_X_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_X_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_X_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_Y_Window7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_Y_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_Y_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_Y_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LOWERRIGHT_WINDOW7_diseng_sig0_LowerRight_Y_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_R_WINDOW7 - Window 7, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW7_diseng_sig0_Ref_R_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW7_diseng_sig0_Ref_R_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW7_diseng_sig0_Ref_R_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW7_diseng_sig0_Ref_R_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_R_WINDOW7_diseng_sig0_Ref_R_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_G_WINDOW7 - Window 7, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW7_diseng_sig0_Ref_G_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW7_diseng_sig0_Ref_G_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW7_diseng_sig0_Ref_G_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW7_diseng_sig0_Ref_G_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_G_WINDOW7_diseng_sig0_Ref_G_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_REF_B_WINDOW7 - Window 7, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW7_diseng_sig0_Ref_B_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW7_diseng_sig0_Ref_B_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW7_diseng_sig0_Ref_B_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW7_diseng_sig0_Ref_B_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF_B_WINDOW7_diseng_sig0_Ref_B_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_CLUSTER0 - Cluster 0, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_En_Cluster0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_En_Cluster0_SHIFT (0U) /*! diseng_sig0_En_Cluster0 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix0_En_Cluster0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix0_En_Cluster0_SHIFT (4U) /*! diseng_sig0_Pix0_En_Cluster0 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix0_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix0_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix0_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix1_En_Cluster0_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix1_En_Cluster0_SHIFT (5U) /*! diseng_sig0_Pix1_En_Cluster0 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix1_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix1_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix1_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix2_En_Cluster0_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix2_En_Cluster0_SHIFT (6U) /*! diseng_sig0_Pix2_En_Cluster0 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix2_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix2_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix2_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix3_En_Cluster0_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix3_En_Cluster0_SHIFT (7U) /*! diseng_sig0_Pix3_En_Cluster0 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix3_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix3_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_Pix3_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskBlue_Cluster0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskBlue_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskBlue_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskBlue_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskBlue_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskGreen_Cluster0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskGreen_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskGreen_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskGreen_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskGreen_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskRed_Cluster0_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskRed_Cluster0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskRed_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskRed_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER0_diseng_sig0_MaskRed_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX0_CLUSTER0 - Cluster 0, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_X0_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_X0_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_X0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_X0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_X0_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_Y0_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_Y0_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_Y0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_Y0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER0_diseng_sig0_Y0_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX1_CLUSTER0 - Cluster 0, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_X1_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_X1_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_X1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_X1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_X1_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_Y1_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_Y1_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_Y1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_Y1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER0_diseng_sig0_Y1_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX2_CLUSTER0 - Cluster 0, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_X2_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_X2_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_X2_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_X2_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_X2_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_Y2_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_Y2_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_Y2_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_Y2_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER0_diseng_sig0_Y2_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX3_CLUSTER0 - Cluster 0, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_X3_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_X3_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_X3_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_X3_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_X3_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_Y3_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_Y3_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_Y3_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_Y3_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER0_diseng_sig0_Y3_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_REF0_CLUSTER0 - Cluster 0, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER0_diseng_sig0_Ref0_Cluster0_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER0_diseng_sig0_Ref0_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER0_diseng_sig0_Ref0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER0_diseng_sig0_Ref0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER0_diseng_sig0_Ref0_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_REF1_CLUSTER0 - Cluster 0, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER0_diseng_sig0_Ref1_Cluster0_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER0_diseng_sig0_Ref1_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER0_diseng_sig0_Ref1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER0_diseng_sig0_Ref1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER0_diseng_sig0_Ref1_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_CLUSTER1 - Cluster 1, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_En_Cluster1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_En_Cluster1_SHIFT (0U) /*! diseng_sig0_En_Cluster1 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix0_En_Cluster1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix0_En_Cluster1_SHIFT (4U) /*! diseng_sig0_Pix0_En_Cluster1 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix0_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix0_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix0_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix1_En_Cluster1_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix1_En_Cluster1_SHIFT (5U) /*! diseng_sig0_Pix1_En_Cluster1 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix1_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix1_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix1_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix2_En_Cluster1_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix2_En_Cluster1_SHIFT (6U) /*! diseng_sig0_Pix2_En_Cluster1 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix2_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix2_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix2_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix3_En_Cluster1_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix3_En_Cluster1_SHIFT (7U) /*! diseng_sig0_Pix3_En_Cluster1 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix3_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix3_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_Pix3_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskBlue_Cluster1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskBlue_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskBlue_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskBlue_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskBlue_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskGreen_Cluster1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskGreen_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskGreen_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskGreen_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskGreen_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskRed_Cluster1_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskRed_Cluster1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskRed_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskRed_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER1_diseng_sig0_MaskRed_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX0_CLUSTER1 - Cluster 1, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_X0_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_X0_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_X0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_X0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_X0_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_Y0_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_Y0_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_Y0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_Y0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER1_diseng_sig0_Y0_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX1_CLUSTER1 - Cluster 1, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_X1_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_X1_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_X1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_X1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_X1_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_Y1_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_Y1_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_Y1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_Y1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER1_diseng_sig0_Y1_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX2_CLUSTER1 - Cluster 1, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_X2_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_X2_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_X2_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_X2_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_X2_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_Y2_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_Y2_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_Y2_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_Y2_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER1_diseng_sig0_Y2_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX3_CLUSTER1 - Cluster 1, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_X3_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_X3_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_X3_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_X3_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_X3_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_Y3_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_Y3_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_Y3_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_Y3_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER1_diseng_sig0_Y3_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_REF0_CLUSTER1 - Cluster 1, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER1_diseng_sig0_Ref0_Cluster1_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER1_diseng_sig0_Ref0_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER1_diseng_sig0_Ref0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER1_diseng_sig0_Ref0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER1_diseng_sig0_Ref0_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_REF1_CLUSTER1 - Cluster 1, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER1_diseng_sig0_Ref1_Cluster1_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER1_diseng_sig0_Ref1_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER1_diseng_sig0_Ref1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER1_diseng_sig0_Ref1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER1_diseng_sig0_Ref1_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_CLUSTER2 - Cluster 2, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_En_Cluster2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_En_Cluster2_SHIFT (0U) /*! diseng_sig0_En_Cluster2 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix0_En_Cluster2_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix0_En_Cluster2_SHIFT (4U) /*! diseng_sig0_Pix0_En_Cluster2 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix0_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix0_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix0_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix1_En_Cluster2_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix1_En_Cluster2_SHIFT (5U) /*! diseng_sig0_Pix1_En_Cluster2 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix1_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix1_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix1_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix2_En_Cluster2_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix2_En_Cluster2_SHIFT (6U) /*! diseng_sig0_Pix2_En_Cluster2 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix2_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix2_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix2_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix3_En_Cluster2_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix3_En_Cluster2_SHIFT (7U) /*! diseng_sig0_Pix3_En_Cluster2 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix3_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix3_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_Pix3_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskBlue_Cluster2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskBlue_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskBlue_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskBlue_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskBlue_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskGreen_Cluster2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskGreen_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskGreen_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskGreen_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskGreen_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskRed_Cluster2_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskRed_Cluster2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskRed_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskRed_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER2_diseng_sig0_MaskRed_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX0_CLUSTER2 - Cluster 2, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_X0_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_X0_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_X0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_X0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_X0_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_Y0_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_Y0_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_Y0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_Y0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER2_diseng_sig0_Y0_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX1_CLUSTER2 - Cluster 2, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_X1_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_X1_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_X1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_X1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_X1_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_Y1_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_Y1_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_Y1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_Y1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER2_diseng_sig0_Y1_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX2_CLUSTER2 - Cluster 2, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_X2_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_X2_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_X2_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_X2_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_X2_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_Y2_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_Y2_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_Y2_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_Y2_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER2_diseng_sig0_Y2_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX3_CLUSTER2 - Cluster 2, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_X3_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_X3_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_X3_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_X3_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_X3_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_Y3_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_Y3_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_Y3_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_Y3_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER2_diseng_sig0_Y3_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_REF0_CLUSTER2 - Cluster 2, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER2_diseng_sig0_Ref0_Cluster2_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER2_diseng_sig0_Ref0_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER2_diseng_sig0_Ref0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER2_diseng_sig0_Ref0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER2_diseng_sig0_Ref0_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_REF1_CLUSTER2 - Cluster 2, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER2_diseng_sig0_Ref1_Cluster2_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER2_diseng_sig0_Ref1_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER2_diseng_sig0_Ref1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER2_diseng_sig0_Ref1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER2_diseng_sig0_Ref1_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_CONTROL_CLUSTER3 - Cluster 3, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_En_Cluster3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_En_Cluster3_SHIFT (0U) /*! diseng_sig0_En_Cluster3 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix0_En_Cluster3_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix0_En_Cluster3_SHIFT (4U) /*! diseng_sig0_Pix0_En_Cluster3 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix0_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix0_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix0_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix1_En_Cluster3_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix1_En_Cluster3_SHIFT (5U) /*! diseng_sig0_Pix1_En_Cluster3 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix1_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix1_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix1_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix2_En_Cluster3_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix2_En_Cluster3_SHIFT (6U) /*! diseng_sig0_Pix2_En_Cluster3 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix2_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix2_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix2_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix3_En_Cluster3_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix3_En_Cluster3_SHIFT (7U) /*! diseng_sig0_Pix3_En_Cluster3 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix3_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix3_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_Pix3_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskBlue_Cluster3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskBlue_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskBlue_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskBlue_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskBlue_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskGreen_Cluster3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskGreen_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskGreen_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskGreen_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskGreen_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskRed_Cluster3_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskRed_Cluster3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskRed_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskRed_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CONTROL_CLUSTER3_diseng_sig0_MaskRed_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX0_CLUSTER3 - Cluster 3, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_X0_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_X0_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_X0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_X0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_X0_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_Y0_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_Y0_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_Y0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_Y0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX0_CLUSTER3_diseng_sig0_Y0_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX1_CLUSTER3 - Cluster 3, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_X1_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_X1_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_X1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_X1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_X1_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_Y1_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_Y1_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_Y1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_Y1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX1_CLUSTER3_diseng_sig0_Y1_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX2_CLUSTER3 - Cluster 3, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_X2_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_X2_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_X2_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_X2_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_X2_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_Y2_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_Y2_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_Y2_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_Y2_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX2_CLUSTER3_diseng_sig0_Y2_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIX3_CLUSTER3 - Cluster 3, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_X3_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_X3_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_X3_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_X3_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_X3_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_Y3_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_Y3_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_Y3_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_Y3_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIX3_CLUSTER3_diseng_sig0_Y3_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_REF0_CLUSTER3 - Cluster 3, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER3_diseng_sig0_Ref0_Cluster3_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER3_diseng_sig0_Ref0_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER3_diseng_sig0_Ref0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER3_diseng_sig0_Ref0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF0_CLUSTER3_diseng_sig0_Ref0_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_REF1_CLUSTER3 - Cluster 3, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER3_diseng_sig0_Ref1_Cluster3_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER3_diseng_sig0_Ref1_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER3_diseng_sig0_Ref1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER3_diseng_sig0_Ref1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REF1_CLUSTER3_diseng_sig0_Ref1_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW0 - Window 0, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW0_diseng_sig0_CRC_R_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW0_diseng_sig0_CRC_R_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW0_diseng_sig0_CRC_R_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW0_diseng_sig0_CRC_R_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW0_diseng_sig0_CRC_R_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW0 - Window 0, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW0_diseng_sig0_CRC_G_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW0_diseng_sig0_CRC_G_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW0_diseng_sig0_CRC_G_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW0_diseng_sig0_CRC_G_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW0_diseng_sig0_CRC_G_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW0 - Window 0, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW0_diseng_sig0_CRC_B_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW0_diseng_sig0_CRC_B_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW0_diseng_sig0_CRC_B_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW0_diseng_sig0_CRC_B_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW0_diseng_sig0_CRC_B_Window0_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW1 - Window 1, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW1_diseng_sig0_CRC_R_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW1_diseng_sig0_CRC_R_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW1_diseng_sig0_CRC_R_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW1_diseng_sig0_CRC_R_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW1_diseng_sig0_CRC_R_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW1 - Window 1, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW1_diseng_sig0_CRC_G_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW1_diseng_sig0_CRC_G_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW1_diseng_sig0_CRC_G_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW1_diseng_sig0_CRC_G_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW1_diseng_sig0_CRC_G_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW1 - Window 1, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW1_diseng_sig0_CRC_B_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW1_diseng_sig0_CRC_B_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW1_diseng_sig0_CRC_B_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW1_diseng_sig0_CRC_B_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW1_diseng_sig0_CRC_B_Window1_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW2 - Window 2, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW2_diseng_sig0_CRC_R_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW2_diseng_sig0_CRC_R_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW2_diseng_sig0_CRC_R_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW2_diseng_sig0_CRC_R_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW2_diseng_sig0_CRC_R_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW2 - Window 2, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW2_diseng_sig0_CRC_G_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW2_diseng_sig0_CRC_G_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW2_diseng_sig0_CRC_G_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW2_diseng_sig0_CRC_G_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW2_diseng_sig0_CRC_G_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW2 - Window 2, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW2_diseng_sig0_CRC_B_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW2_diseng_sig0_CRC_B_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW2_diseng_sig0_CRC_B_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW2_diseng_sig0_CRC_B_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW2_diseng_sig0_CRC_B_Window2_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW3 - Window 3, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW3_diseng_sig0_CRC_R_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW3_diseng_sig0_CRC_R_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW3_diseng_sig0_CRC_R_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW3_diseng_sig0_CRC_R_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW3_diseng_sig0_CRC_R_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW3 - Window 3, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW3_diseng_sig0_CRC_G_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW3_diseng_sig0_CRC_G_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW3_diseng_sig0_CRC_G_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW3_diseng_sig0_CRC_G_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW3_diseng_sig0_CRC_G_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW3 - Window 3, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW3_diseng_sig0_CRC_B_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW3_diseng_sig0_CRC_B_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW3_diseng_sig0_CRC_B_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW3_diseng_sig0_CRC_B_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW3_diseng_sig0_CRC_B_Window3_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW4 - Window 4, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW4_diseng_sig0_CRC_R_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW4_diseng_sig0_CRC_R_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW4_diseng_sig0_CRC_R_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW4_diseng_sig0_CRC_R_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW4_diseng_sig0_CRC_R_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW4 - Window 4, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW4_diseng_sig0_CRC_G_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW4_diseng_sig0_CRC_G_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW4_diseng_sig0_CRC_G_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW4_diseng_sig0_CRC_G_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW4_diseng_sig0_CRC_G_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW4 - Window 4, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW4_diseng_sig0_CRC_B_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW4_diseng_sig0_CRC_B_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW4_diseng_sig0_CRC_B_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW4_diseng_sig0_CRC_B_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW4_diseng_sig0_CRC_B_Window4_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW5 - Window 5, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW5_diseng_sig0_CRC_R_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW5_diseng_sig0_CRC_R_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW5_diseng_sig0_CRC_R_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW5_diseng_sig0_CRC_R_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW5_diseng_sig0_CRC_R_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW5 - Window 5, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW5_diseng_sig0_CRC_G_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW5_diseng_sig0_CRC_G_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW5_diseng_sig0_CRC_G_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW5_diseng_sig0_CRC_G_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW5_diseng_sig0_CRC_G_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW5 - Window 5, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW5_diseng_sig0_CRC_B_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW5_diseng_sig0_CRC_B_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW5_diseng_sig0_CRC_B_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW5_diseng_sig0_CRC_B_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW5_diseng_sig0_CRC_B_Window5_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW6 - Window 6, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW6_diseng_sig0_CRC_R_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW6_diseng_sig0_CRC_R_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW6_diseng_sig0_CRC_R_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW6_diseng_sig0_CRC_R_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW6_diseng_sig0_CRC_R_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW6 - Window 6, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW6_diseng_sig0_CRC_G_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW6_diseng_sig0_CRC_G_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW6_diseng_sig0_CRC_G_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW6_diseng_sig0_CRC_G_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW6_diseng_sig0_CRC_G_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW6 - Window 6, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW6_diseng_sig0_CRC_B_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW6_diseng_sig0_CRC_B_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW6_diseng_sig0_CRC_B_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW6_diseng_sig0_CRC_B_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW6_diseng_sig0_CRC_B_Window6_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_R_WINDOW7 - Window 7, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW7_diseng_sig0_CRC_R_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW7_diseng_sig0_CRC_R_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW7_diseng_sig0_CRC_R_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW7_diseng_sig0_CRC_R_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_R_WINDOW7_diseng_sig0_CRC_R_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_G_WINDOW7 - Window 7, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW7_diseng_sig0_CRC_G_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW7_diseng_sig0_CRC_G_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW7_diseng_sig0_CRC_G_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW7_diseng_sig0_CRC_G_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_G_WINDOW7_diseng_sig0_CRC_G_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_CRC_B_WINDOW7 - Window 7, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW7_diseng_sig0_CRC_B_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW7_diseng_sig0_CRC_B_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW7_diseng_sig0_CRC_B_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW7_diseng_sig0_CRC_B_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_CRC_B_WINDOW7_diseng_sig0_CRC_B_Window7_MASK) /*! @} */ /*! @name DISENG_SIG0_STATUS_CLUSTER0 - Cluster 0, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts00_Cluster0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts00_Cluster0_SHIFT (0U) /*! diseng_sig0_Sts00_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts00_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts00_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts00_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts01_Cluster0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts01_Cluster0_SHIFT (1U) /*! diseng_sig0_Sts01_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts01_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts01_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts01_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts10_Cluster0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts10_Cluster0_SHIFT (2U) /*! diseng_sig0_Sts10_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts11_Cluster0_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts11_Cluster0_SHIFT (3U) /*! diseng_sig0_Sts11_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts11_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts11_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts11_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts20_Cluster0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts20_Cluster0_SHIFT (4U) /*! diseng_sig0_Sts20_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts20_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts20_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts20_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts21_Cluster0_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts21_Cluster0_SHIFT (5U) /*! diseng_sig0_Sts21_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts21_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts21_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts21_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts30_Cluster0_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts30_Cluster0_SHIFT (6U) /*! diseng_sig0_Sts30_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts30_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts30_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts30_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts31_Cluster0_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts31_Cluster0_SHIFT (7U) /*! diseng_sig0_Sts31_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts31_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts31_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER0_diseng_sig0_Sts31_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_COUNTER_CLUSTER0 - Cluster 0, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_MatchCount_Cluster0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_MatchCount_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_MatchCount_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_MatchCount_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_MatchCount_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_ErrorCount_Cluster0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_ErrorCount_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_ErrorCount_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_ErrorCount_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER0_diseng_sig0_ErrorCount_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR0_CLUSTER0 - Cluster 0, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_B10_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_B10_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_G10_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_G10_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_R10_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_R10_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix0_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_B10_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_B10_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_G10_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_G10_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_R10_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_R10_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix1_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_B10_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_B10_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_G10_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_G10_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_R10_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_R10_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix2_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_B10_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_B10_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_G10_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_G10_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_R10_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_R10_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER0_diseng_sig0_Pix3_R10_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR1_CLUSTER0 - Cluster 0, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_B32_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_B32_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_G32_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_G32_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_R32_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_R32_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix0_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_B32_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_B32_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_G32_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_G32_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_R32_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_R32_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix1_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_B32_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_B32_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_G32_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_G32_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_R32_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_R32_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix2_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_B32_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_B32_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_G32_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_G32_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_R32_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_R32_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER0_diseng_sig0_Pix3_R32_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR2_CLUSTER0 - Cluster 0, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_B54_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_B54_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_G54_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_G54_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_R54_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_R54_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix0_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_B54_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_B54_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_G54_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_G54_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_R54_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_R54_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix1_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_B54_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_B54_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_G54_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_G54_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_R54_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_R54_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix2_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_B54_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_B54_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_G54_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_G54_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_R54_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_R54_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER0_diseng_sig0_Pix3_R54_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR3_CLUSTER0 - Cluster 0, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_B76_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_B76_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_G76_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_G76_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_R76_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_R76_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix0_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_B76_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_B76_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_G76_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_G76_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_R76_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_R76_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix1_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_B76_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_B76_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_G76_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_G76_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_R76_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_R76_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix2_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_B76_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_B76_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_G76_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_G76_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_R76_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_R76_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER0_diseng_sig0_Pix3_R76_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG0_STATUS_CLUSTER1 - Cluster 1, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts00_Cluster1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts00_Cluster1_SHIFT (0U) /*! diseng_sig0_Sts00_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts00_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts00_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts00_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts01_Cluster1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts01_Cluster1_SHIFT (1U) /*! diseng_sig0_Sts01_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts01_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts01_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts01_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts10_Cluster1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts10_Cluster1_SHIFT (2U) /*! diseng_sig0_Sts10_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts11_Cluster1_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts11_Cluster1_SHIFT (3U) /*! diseng_sig0_Sts11_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts11_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts11_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts11_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts20_Cluster1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts20_Cluster1_SHIFT (4U) /*! diseng_sig0_Sts20_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts20_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts20_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts20_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts21_Cluster1_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts21_Cluster1_SHIFT (5U) /*! diseng_sig0_Sts21_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts21_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts21_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts21_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts30_Cluster1_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts30_Cluster1_SHIFT (6U) /*! diseng_sig0_Sts30_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts30_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts30_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts30_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts31_Cluster1_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts31_Cluster1_SHIFT (7U) /*! diseng_sig0_Sts31_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts31_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts31_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER1_diseng_sig0_Sts31_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_COUNTER_CLUSTER1 - Cluster 1, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_MatchCount_Cluster1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_MatchCount_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_MatchCount_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_MatchCount_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_MatchCount_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_ErrorCount_Cluster1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_ErrorCount_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_ErrorCount_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_ErrorCount_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER1_diseng_sig0_ErrorCount_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR0_CLUSTER1 - Cluster 1, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_B10_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_B10_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_G10_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_G10_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_R10_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_R10_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix0_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_B10_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_B10_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_G10_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_G10_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_R10_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_R10_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix1_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_B10_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_B10_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_G10_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_G10_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_R10_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_R10_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix2_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_B10_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_B10_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_G10_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_G10_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_R10_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_R10_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER1_diseng_sig0_Pix3_R10_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR1_CLUSTER1 - Cluster 1, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_B32_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_B32_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_G32_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_G32_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_R32_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_R32_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix0_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_B32_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_B32_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_G32_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_G32_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_R32_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_R32_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix1_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_B32_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_B32_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_G32_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_G32_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_R32_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_R32_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix2_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_B32_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_B32_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_G32_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_G32_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_R32_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_R32_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER1_diseng_sig0_Pix3_R32_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR2_CLUSTER1 - Cluster 1, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_B54_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_B54_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_G54_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_G54_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_R54_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_R54_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix0_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_B54_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_B54_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_G54_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_G54_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_R54_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_R54_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix1_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_B54_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_B54_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_G54_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_G54_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_R54_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_R54_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix2_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_B54_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_B54_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_G54_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_G54_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_R54_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_R54_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER1_diseng_sig0_Pix3_R54_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR3_CLUSTER1 - Cluster 1, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_B76_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_B76_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_G76_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_G76_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_R76_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_R76_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix0_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_B76_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_B76_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_G76_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_G76_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_R76_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_R76_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix1_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_B76_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_B76_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_G76_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_G76_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_R76_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_R76_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix2_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_B76_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_B76_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_G76_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_G76_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_R76_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_R76_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER1_diseng_sig0_Pix3_R76_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG0_STATUS_CLUSTER2 - Cluster 2, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts00_Cluster2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts00_Cluster2_SHIFT (0U) /*! diseng_sig0_Sts00_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts00_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts00_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts00_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts01_Cluster2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts01_Cluster2_SHIFT (1U) /*! diseng_sig0_Sts01_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts01_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts01_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts01_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts10_Cluster2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts10_Cluster2_SHIFT (2U) /*! diseng_sig0_Sts10_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts11_Cluster2_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts11_Cluster2_SHIFT (3U) /*! diseng_sig0_Sts11_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts11_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts11_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts11_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts20_Cluster2_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts20_Cluster2_SHIFT (4U) /*! diseng_sig0_Sts20_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts20_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts20_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts20_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts21_Cluster2_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts21_Cluster2_SHIFT (5U) /*! diseng_sig0_Sts21_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts21_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts21_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts21_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts30_Cluster2_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts30_Cluster2_SHIFT (6U) /*! diseng_sig0_Sts30_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts30_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts30_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts30_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts31_Cluster2_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts31_Cluster2_SHIFT (7U) /*! diseng_sig0_Sts31_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts31_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts31_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER2_diseng_sig0_Sts31_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_COUNTER_CLUSTER2 - Cluster 2, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_MatchCount_Cluster2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_MatchCount_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_MatchCount_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_MatchCount_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_MatchCount_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_ErrorCount_Cluster2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_ErrorCount_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_ErrorCount_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_ErrorCount_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER2_diseng_sig0_ErrorCount_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR0_CLUSTER2 - Cluster 2, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_B10_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_B10_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_G10_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_G10_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_R10_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_R10_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix0_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_B10_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_B10_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_G10_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_G10_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_R10_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_R10_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix1_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_B10_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_B10_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_G10_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_G10_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_R10_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_R10_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix2_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_B10_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_B10_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_G10_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_G10_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_R10_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_R10_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER2_diseng_sig0_Pix3_R10_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR1_CLUSTER2 - Cluster 2, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_B32_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_B32_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_G32_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_G32_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_R32_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_R32_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix0_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_B32_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_B32_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_G32_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_G32_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_R32_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_R32_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix1_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_B32_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_B32_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_G32_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_G32_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_R32_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_R32_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix2_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_B32_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_B32_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_G32_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_G32_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_R32_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_R32_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER2_diseng_sig0_Pix3_R32_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR2_CLUSTER2 - Cluster 2, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_B54_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_B54_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_G54_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_G54_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_R54_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_R54_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix0_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_B54_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_B54_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_G54_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_G54_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_R54_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_R54_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix1_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_B54_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_B54_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_G54_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_G54_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_R54_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_R54_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix2_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_B54_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_B54_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_G54_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_G54_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_R54_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_R54_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER2_diseng_sig0_Pix3_R54_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR3_CLUSTER2 - Cluster 2, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_B76_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_B76_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_G76_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_G76_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_R76_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_R76_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix0_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_B76_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_B76_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_G76_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_G76_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_R76_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_R76_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix1_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_B76_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_B76_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_G76_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_G76_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_R76_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_R76_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix2_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_B76_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_B76_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_G76_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_G76_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_R76_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_R76_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER2_diseng_sig0_Pix3_R76_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG0_STATUS_CLUSTER3 - Cluster 3, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts00_Cluster3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts00_Cluster3_SHIFT (0U) /*! diseng_sig0_Sts00_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts00_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts00_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts00_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts01_Cluster3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts01_Cluster3_SHIFT (1U) /*! diseng_sig0_Sts01_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts01_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts01_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts01_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts10_Cluster3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts10_Cluster3_SHIFT (2U) /*! diseng_sig0_Sts10_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts11_Cluster3_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts11_Cluster3_SHIFT (3U) /*! diseng_sig0_Sts11_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts11_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts11_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts11_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts20_Cluster3_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts20_Cluster3_SHIFT (4U) /*! diseng_sig0_Sts20_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts20_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts20_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts20_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts21_Cluster3_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts21_Cluster3_SHIFT (5U) /*! diseng_sig0_Sts21_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts21_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts21_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts21_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts30_Cluster3_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts30_Cluster3_SHIFT (6U) /*! diseng_sig0_Sts30_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts30_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts30_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts30_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts31_Cluster3_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts31_Cluster3_SHIFT (7U) /*! diseng_sig0_Sts31_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts31_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts31_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_STATUS_CLUSTER3_diseng_sig0_Sts31_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_COUNTER_CLUSTER3 - Cluster 3, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_MatchCount_Cluster3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_MatchCount_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_MatchCount_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_MatchCount_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_MatchCount_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_ErrorCount_Cluster3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_ErrorCount_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_ErrorCount_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_ErrorCount_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_COUNTER_CLUSTER3_diseng_sig0_ErrorCount_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR0_CLUSTER3 - Cluster 3, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_B10_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_B10_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_G10_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_G10_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_R10_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_R10_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix0_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_B10_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_B10_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_G10_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_G10_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_R10_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_R10_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix1_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_B10_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_B10_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_G10_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_G10_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_R10_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_R10_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix2_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_B10_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_B10_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_G10_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_G10_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_R10_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_R10_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR0_CLUSTER3_diseng_sig0_Pix3_R10_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR1_CLUSTER3 - Cluster 3, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_B32_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_B32_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_G32_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_G32_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_R32_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_R32_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix0_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_B32_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_B32_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_G32_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_G32_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_R32_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_R32_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix1_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_B32_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_B32_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_G32_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_G32_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_R32_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_R32_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix2_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_B32_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_B32_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_G32_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_G32_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_R32_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_R32_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR1_CLUSTER3_diseng_sig0_Pix3_R32_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR2_CLUSTER3 - Cluster 3, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_B54_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_B54_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_G54_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_G54_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_R54_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_R54_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix0_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_B54_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_B54_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_G54_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_G54_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_R54_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_R54_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix1_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_B54_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_B54_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_G54_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_G54_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_R54_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_R54_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix2_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_B54_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_B54_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_G54_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_G54_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_R54_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_R54_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR2_CLUSTER3_diseng_sig0_Pix3_R54_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_VECTOR3_CLUSTER3 - Cluster 3, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_B76_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_B76_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_G76_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_G76_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_R76_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_R76_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix0_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_B76_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_B76_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_G76_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_G76_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_R76_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_R76_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix1_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_B76_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_B76_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_G76_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_G76_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_R76_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_R76_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix2_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_B76_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_B76_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_G76_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_G76_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_R76_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_R76_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_VECTOR3_CLUSTER3_diseng_sig0_Pix3_R76_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS0_WIN0 - Pixel Counter Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN0_diseng_sig0_Px_Cnt_S0_Win0_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN0_diseng_sig0_Px_Cnt_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN0_diseng_sig0_Px_Cnt_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN0_diseng_sig0_Px_Cnt_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN0_diseng_sig0_Px_Cnt_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS0_WIN0 - Pixel Max Values Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Bl_Max_S0_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Bl_Max_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Bl_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Bl_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Bl_Max_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Gn_Max_S0_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Gn_Max_S0_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Gn_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Gn_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Gn_Max_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Rd_Max_S0_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Rd_Max_S0_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Rd_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Rd_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN0_diseng_sig0_Rd_Max_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS0_WIN0 - Pixel Min Values Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Bl_Min_S0_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Bl_Min_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Bl_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Bl_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Bl_Min_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Gn_Min_S0_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Gn_Min_S0_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Gn_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Gn_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Gn_Min_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Rd_Min_S0_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Rd_Min_S0_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Rd_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Rd_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN0_diseng_sig0_Rd_Min_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS0_WIN0 - Red Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN0_diseng_sig0_Rd_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN0_diseng_sig0_Rd_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN0_diseng_sig0_Rd_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN0_diseng_sig0_Rd_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN0_diseng_sig0_Rd_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS0_WIN0 - Green Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN0_diseng_sig0_Gn_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN0_diseng_sig0_Gn_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN0_diseng_sig0_Gn_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN0_diseng_sig0_Gn_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN0_diseng_sig0_Gn_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS0_WIN0 - Blue Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN0_diseng_sig0_Bl_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN0_diseng_sig0_Bl_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN0_diseng_sig0_Bl_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN0_diseng_sig0_Bl_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN0_diseng_sig0_Bl_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_LUMSUM_STATS0_WIN0 - Luminance Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN0_diseng_sig0_Lm_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN0_diseng_sig0_Lm_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN0_diseng_sig0_Lm_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN0_diseng_sig0_Lm_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN0_diseng_sig0_Lm_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS1_WIN0 - Pixel Counter Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN0_diseng_sig0_Px_Cnt_S1_Win0_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN0_diseng_sig0_Px_Cnt_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN0_diseng_sig0_Px_Cnt_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN0_diseng_sig0_Px_Cnt_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN0_diseng_sig0_Px_Cnt_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS1_WIN0 - Pixel Max Values Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Bl_Max_S1_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Bl_Max_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Bl_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Bl_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Bl_Max_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Gn_Max_S1_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Gn_Max_S1_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Gn_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Gn_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Gn_Max_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Rd_Max_S1_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Rd_Max_S1_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Rd_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Rd_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN0_diseng_sig0_Rd_Max_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS1_WIN0 - Pixel Min Values Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Bl_Min_S1_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Bl_Min_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Bl_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Bl_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Bl_Min_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Gn_Min_S1_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Gn_Min_S1_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Gn_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Gn_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Gn_Min_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Rd_Min_S1_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Rd_Min_S1_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Rd_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Rd_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN0_diseng_sig0_Rd_Min_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS1_WIN0 - Red Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN0_diseng_sig0_Rd_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN0_diseng_sig0_Rd_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN0_diseng_sig0_Rd_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN0_diseng_sig0_Rd_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN0_diseng_sig0_Rd_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS1_WIN0 - Green Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN0_diseng_sig0_Gn_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN0_diseng_sig0_Gn_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN0_diseng_sig0_Gn_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN0_diseng_sig0_Gn_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN0_diseng_sig0_Gn_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS1_WIN0 - Blue Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN0_diseng_sig0_Bl_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN0_diseng_sig0_Bl_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN0_diseng_sig0_Bl_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN0_diseng_sig0_Bl_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN0_diseng_sig0_Bl_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS0_WIN1 - Pixel Counter Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN1_diseng_sig0_Px_Cnt_S0_Win1_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN1_diseng_sig0_Px_Cnt_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN1_diseng_sig0_Px_Cnt_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN1_diseng_sig0_Px_Cnt_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN1_diseng_sig0_Px_Cnt_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS0_WIN1 - Pixel Max Values Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Bl_Max_S0_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Bl_Max_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Bl_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Bl_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Bl_Max_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Gn_Max_S0_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Gn_Max_S0_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Gn_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Gn_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Gn_Max_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Rd_Max_S0_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Rd_Max_S0_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Rd_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Rd_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN1_diseng_sig0_Rd_Max_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS0_WIN1 - Pixel Min Values Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Bl_Min_S0_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Bl_Min_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Bl_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Bl_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Bl_Min_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Gn_Min_S0_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Gn_Min_S0_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Gn_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Gn_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Gn_Min_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Rd_Min_S0_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Rd_Min_S0_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Rd_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Rd_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN1_diseng_sig0_Rd_Min_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS0_WIN1 - Red Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN1_diseng_sig0_Rd_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN1_diseng_sig0_Rd_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN1_diseng_sig0_Rd_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN1_diseng_sig0_Rd_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN1_diseng_sig0_Rd_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS0_WIN1 - Green Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN1_diseng_sig0_Gn_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN1_diseng_sig0_Gn_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN1_diseng_sig0_Gn_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN1_diseng_sig0_Gn_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN1_diseng_sig0_Gn_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS0_WIN1 - Blue Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN1_diseng_sig0_Bl_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN1_diseng_sig0_Bl_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN1_diseng_sig0_Bl_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN1_diseng_sig0_Bl_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN1_diseng_sig0_Bl_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_LUMSUM_STATS0_WIN1 - Luminance Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN1_diseng_sig0_Lm_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN1_diseng_sig0_Lm_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN1_diseng_sig0_Lm_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN1_diseng_sig0_Lm_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN1_diseng_sig0_Lm_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS1_WIN1 - Pixel Counter Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN1_diseng_sig0_Px_Cnt_S1_Win1_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN1_diseng_sig0_Px_Cnt_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN1_diseng_sig0_Px_Cnt_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN1_diseng_sig0_Px_Cnt_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN1_diseng_sig0_Px_Cnt_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS1_WIN1 - Pixel Max Values Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Bl_Max_S1_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Bl_Max_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Bl_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Bl_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Bl_Max_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Gn_Max_S1_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Gn_Max_S1_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Gn_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Gn_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Gn_Max_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Rd_Max_S1_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Rd_Max_S1_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Rd_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Rd_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN1_diseng_sig0_Rd_Max_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS1_WIN1 - Pixel Min Values Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Bl_Min_S1_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Bl_Min_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Bl_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Bl_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Bl_Min_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Gn_Min_S1_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Gn_Min_S1_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Gn_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Gn_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Gn_Min_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Rd_Min_S1_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Rd_Min_S1_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Rd_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Rd_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN1_diseng_sig0_Rd_Min_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS1_WIN1 - Red Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN1_diseng_sig0_Rd_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN1_diseng_sig0_Rd_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN1_diseng_sig0_Rd_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN1_diseng_sig0_Rd_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN1_diseng_sig0_Rd_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS1_WIN1 - Green Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN1_diseng_sig0_Gn_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN1_diseng_sig0_Gn_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN1_diseng_sig0_Gn_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN1_diseng_sig0_Gn_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN1_diseng_sig0_Gn_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS1_WIN1 - Blue Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN1_diseng_sig0_Bl_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN1_diseng_sig0_Bl_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN1_diseng_sig0_Bl_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN1_diseng_sig0_Bl_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN1_diseng_sig0_Bl_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS0_WIN2 - Pixel Counter Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN2_diseng_sig0_Px_Cnt_S0_Win2_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN2_diseng_sig0_Px_Cnt_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN2_diseng_sig0_Px_Cnt_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN2_diseng_sig0_Px_Cnt_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN2_diseng_sig0_Px_Cnt_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS0_WIN2 - Pixel Max Values Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Bl_Max_S0_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Bl_Max_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Bl_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Bl_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Bl_Max_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Gn_Max_S0_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Gn_Max_S0_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Gn_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Gn_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Gn_Max_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Rd_Max_S0_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Rd_Max_S0_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Rd_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Rd_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN2_diseng_sig0_Rd_Max_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS0_WIN2 - Pixel Min Values Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Bl_Min_S0_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Bl_Min_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Bl_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Bl_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Bl_Min_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Gn_Min_S0_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Gn_Min_S0_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Gn_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Gn_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Gn_Min_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Rd_Min_S0_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Rd_Min_S0_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Rd_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Rd_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN2_diseng_sig0_Rd_Min_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS0_WIN2 - Red Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN2_diseng_sig0_Rd_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN2_diseng_sig0_Rd_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN2_diseng_sig0_Rd_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN2_diseng_sig0_Rd_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN2_diseng_sig0_Rd_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS0_WIN2 - Green Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN2_diseng_sig0_Gn_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN2_diseng_sig0_Gn_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN2_diseng_sig0_Gn_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN2_diseng_sig0_Gn_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN2_diseng_sig0_Gn_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS0_WIN2 - Blue Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN2_diseng_sig0_Bl_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN2_diseng_sig0_Bl_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN2_diseng_sig0_Bl_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN2_diseng_sig0_Bl_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN2_diseng_sig0_Bl_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_LUMSUM_STATS0_WIN2 - Luminance Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN2_diseng_sig0_Lm_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN2_diseng_sig0_Lm_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN2_diseng_sig0_Lm_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN2_diseng_sig0_Lm_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN2_diseng_sig0_Lm_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS1_WIN2 - Pixel Counter Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN2_diseng_sig0_Px_Cnt_S1_Win2_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN2_diseng_sig0_Px_Cnt_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN2_diseng_sig0_Px_Cnt_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN2_diseng_sig0_Px_Cnt_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN2_diseng_sig0_Px_Cnt_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS1_WIN2 - Pixel Max Values Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Bl_Max_S1_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Bl_Max_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Bl_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Bl_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Bl_Max_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Gn_Max_S1_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Gn_Max_S1_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Gn_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Gn_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Gn_Max_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Rd_Max_S1_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Rd_Max_S1_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Rd_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Rd_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN2_diseng_sig0_Rd_Max_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS1_WIN2 - Pixel Min Values Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Bl_Min_S1_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Bl_Min_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Bl_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Bl_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Bl_Min_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Gn_Min_S1_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Gn_Min_S1_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Gn_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Gn_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Gn_Min_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Rd_Min_S1_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Rd_Min_S1_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Rd_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Rd_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN2_diseng_sig0_Rd_Min_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS1_WIN2 - Red Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN2_diseng_sig0_Rd_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN2_diseng_sig0_Rd_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN2_diseng_sig0_Rd_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN2_diseng_sig0_Rd_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN2_diseng_sig0_Rd_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS1_WIN2 - Green Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN2_diseng_sig0_Gn_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN2_diseng_sig0_Gn_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN2_diseng_sig0_Gn_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN2_diseng_sig0_Gn_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN2_diseng_sig0_Gn_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS1_WIN2 - Blue Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN2_diseng_sig0_Bl_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN2_diseng_sig0_Bl_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN2_diseng_sig0_Bl_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN2_diseng_sig0_Bl_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN2_diseng_sig0_Bl_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS0_WIN3 - Pixel Counter Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN3_diseng_sig0_Px_Cnt_S0_Win3_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN3_diseng_sig0_Px_Cnt_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN3_diseng_sig0_Px_Cnt_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN3_diseng_sig0_Px_Cnt_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS0_WIN3_diseng_sig0_Px_Cnt_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS0_WIN3 - Pixel Max Values Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Bl_Max_S0_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Bl_Max_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Bl_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Bl_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Bl_Max_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Gn_Max_S0_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Gn_Max_S0_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Gn_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Gn_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Gn_Max_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Rd_Max_S0_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Rd_Max_S0_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Rd_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Rd_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS0_WIN3_diseng_sig0_Rd_Max_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS0_WIN3 - Pixel Min Values Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Bl_Min_S0_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Bl_Min_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Bl_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Bl_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Bl_Min_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Gn_Min_S0_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Gn_Min_S0_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Gn_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Gn_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Gn_Min_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Rd_Min_S0_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Rd_Min_S0_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Rd_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Rd_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS0_WIN3_diseng_sig0_Rd_Min_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS0_WIN3 - Red Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN3_diseng_sig0_Rd_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN3_diseng_sig0_Rd_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN3_diseng_sig0_Rd_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN3_diseng_sig0_Rd_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS0_WIN3_diseng_sig0_Rd_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS0_WIN3 - Green Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN3_diseng_sig0_Gn_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN3_diseng_sig0_Gn_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN3_diseng_sig0_Gn_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN3_diseng_sig0_Gn_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS0_WIN3_diseng_sig0_Gn_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS0_WIN3 - Blue Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN3_diseng_sig0_Bl_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN3_diseng_sig0_Bl_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN3_diseng_sig0_Bl_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN3_diseng_sig0_Bl_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS0_WIN3_diseng_sig0_Bl_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_LUMSUM_STATS0_WIN3 - Luminance Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN3_diseng_sig0_Lm_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN3_diseng_sig0_Lm_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN3_diseng_sig0_Lm_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN3_diseng_sig0_Lm_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_LUMSUM_STATS0_WIN3_diseng_sig0_Lm_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXCNT_STATS1_WIN3 - Pixel Counter Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN3_diseng_sig0_Px_Cnt_S1_Win3_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN3_diseng_sig0_Px_Cnt_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN3_diseng_sig0_Px_Cnt_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN3_diseng_sig0_Px_Cnt_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXCNT_STATS1_WIN3_diseng_sig0_Px_Cnt_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMAX_STATS1_WIN3 - Pixel Max Values Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Bl_Max_S1_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Bl_Max_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Bl_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Bl_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Bl_Max_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Gn_Max_S1_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Gn_Max_S1_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Gn_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Gn_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Gn_Max_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Rd_Max_S1_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Rd_Max_S1_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Rd_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Rd_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMAX_STATS1_WIN3_diseng_sig0_Rd_Max_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_PIXMIN_STATS1_WIN3 - Pixel Min Values Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Bl_Min_S1_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Bl_Min_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Bl_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Bl_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Bl_Min_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Gn_Min_S1_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Gn_Min_S1_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Gn_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Gn_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Gn_Min_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Rd_Min_S1_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Rd_Min_S1_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Rd_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Rd_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_PIXMIN_STATS1_WIN3_diseng_sig0_Rd_Min_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_REDSUM_STATS1_WIN3 - Red Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN3_diseng_sig0_Rd_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN3_diseng_sig0_Rd_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN3_diseng_sig0_Rd_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN3_diseng_sig0_Rd_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_REDSUM_STATS1_WIN3_diseng_sig0_Rd_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_GREENSUM_STATS1_WIN3 - Green Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN3_diseng_sig0_Gn_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN3_diseng_sig0_Gn_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN3_diseng_sig0_Gn_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN3_diseng_sig0_Gn_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_GREENSUM_STATS1_WIN3_diseng_sig0_Gn_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0_BLUESUM_STATS1_WIN3 - Blue Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN3_diseng_sig0_Bl_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN3_diseng_sig0_Bl_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN3_diseng_sig0_Bl_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN3_diseng_sig0_Bl_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0_BLUESUM_STATS1_WIN3_diseng_sig0_Bl_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG0CFG_LOCKUNLOCK0 - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKUNLOCK0_diseng_sig0cfg_LockUnlock0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKUNLOCK0_diseng_sig0cfg_LockUnlock0_SHIFT (0U) /*! diseng_sig0cfg_LockUnlock0 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKUNLOCK0_diseng_sig0cfg_LockUnlock0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKUNLOCK0_diseng_sig0cfg_LockUnlock0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKUNLOCK0_diseng_sig0cfg_LockUnlock0_MASK) /*! @} */ /*! @name DISENG_SIG0CFG_LOCKSTATUS0 - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_LockStatus0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_LockStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_LockStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_LockStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_LockStatus0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_PrivilegeStatus0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_PrivilegeStatus0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_PrivilegeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_PrivilegeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_PrivilegeStatus0_MASK) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_FreezeStatus0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_FreezeStatus0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_FreezeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_FreezeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0CFG_LOCKSTATUS0_diseng_sig0cfg_FreezeStatus0_MASK) /*! @} */ /*! @name DISENG_SIG0CFG_SRCSELECT - Tap selection for sig0. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG0CFG_SRCSELECT_diseng_sig0cfg_sig0_select_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG0CFG_SRCSELECT_diseng_sig0cfg_sig0_select_SHIFT (0U) /*! diseng_sig0cfg_sig0_select * 0b00..Source is FrameGen#0 output. * 0b01..Source is Matrix#0 output. * 0b10..Source is LuT3D#0 output. * 0b11..Source is Dither#0 output. */ #define DISPLAY_SEERIS_DISENG_SIG0CFG_SRCSELECT_diseng_sig0cfg_sig0_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG0CFG_SRCSELECT_diseng_sig0cfg_sig0_select_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG0CFG_SRCSELECT_diseng_sig0cfg_sig0_select_MASK) /*! @} */ /*! @name DISENG_SIG2_LOCKUNLOCK - Register to change the protection status of this address block */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOCKUNLOCK_diseng_sig2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKUNLOCK_diseng_sig2_LockUnlock_SHIFT (0U) /*! diseng_sig2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_SIG2_LOCKUNLOCK_diseng_sig2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOCKUNLOCK_diseng_sig2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOCKUNLOCK_diseng_sig2_LockUnlock_MASK) /*! @} */ /*! @name DISENG_SIG2_LOCKSTATUS - Protection status of this address block */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOCKSTATUS_diseng_sig2_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_SIG2_STATICCONTROL - Global configuration */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdEn_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdLdSel_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdLdSel_SHIFT (4U) /*! diseng_sig2_ShdLdSel * 0b0..Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. * 0b1..Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). */ #define DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATICCONTROL_diseng_sig2_ShdLdSel_MASK) /*! @} */ /*! @name DISENG_SIG2_ERRORTHRESHOLD - Set and reset thresholds applying to Window_Error and Cluster_Error interrupts and status bits */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThres_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThres_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThres(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThres_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThres_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThresReset_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThresReset_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThresReset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThresReset_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_ERRORTHRESHOLD_diseng_sig2_ErrThresReset_MASK) /*! @} */ /*! @name DISENG_SIG2_MATCHTHRESHOLD - Set and reset thresholds applying to Match interrupt and status bits */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThres_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThres_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThres(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThres_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThres_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThresReset_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThresReset_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThresReset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThresReset_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MATCHTHRESHOLD_diseng_sig2_MatchThresReset_MASK) /*! @} */ /*! @name DISENG_SIG2_PANICCOLOR - Overlay color for evaluation windows in panic mode */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicAlpha_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicAlpha_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicBlue_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicBlue_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicBlue_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicGreen_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicGreen_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicGreen_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicRed_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicRed_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PANICCOLOR_diseng_sig2_PanicRed_MASK) /*! @} */ /*! @name DISENG_SIG2_SHADOWLOAD - Shadow load control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_SHADOWLOAD_diseng_sig2_ShdLdReq_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_SHADOWLOAD_diseng_sig2_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_SHADOWLOAD_diseng_sig2_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_SHADOWLOAD_diseng_sig2_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_SHADOWLOAD_diseng_sig2_ShdLdReq_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTINUOUSMODE - Signature operation mode control */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTINUOUSMODE_diseng_sig2_EnCont_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTINUOUSMODE_diseng_sig2_EnCont_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTINUOUSMODE_diseng_sig2_EnCont(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTINUOUSMODE_diseng_sig2_EnCont_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTINUOUSMODE_diseng_sig2_EnCont_MASK) /*! @} */ /*! @name DISENG_SIG2_SOFTWAREKICK - Signature measurement trigger */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_SOFTWAREKICK_diseng_sig2_Kick_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_SOFTWAREKICK_diseng_sig2_Kick_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_SOFTWAREKICK_diseng_sig2_Kick(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_SOFTWAREKICK_diseng_sig2_Kick_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_SOFTWAREKICK_diseng_sig2_Kick_MASK) /*! @} */ /*! @name DISENG_SIG2_SKIPWINDOW - Enable skipping window feature. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_SKIPWINDOW_diseng_sig2_SkipWinEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_SKIPWINDOW_diseng_sig2_SkipWinEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_SKIPWINDOW_diseng_sig2_SkipWinEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_SKIPWINDOW_diseng_sig2_SkipWinEn_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_SKIPWINDOW_diseng_sig2_SkipWinEn_MASK) /*! @} */ /*! @name DISENG_SIG2_STATUS - Signature evaluation status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigState_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigState_SHIFT (0U) /*! diseng_sig2_SigState * 0b0..Signature is in idle state * 0b1..Signature is in run state */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigState(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigState_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigState_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigValid_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigValid_SHIFT (1U) /*! diseng_sig2_SigValid * 0b0..Signature results are not valid * 0b1..Signature results are valid */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigValid(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigValid_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_SigValid_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Window_Error_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Window_Error_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Window_Error(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Window_Error_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Window_Error_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Error_MASK (0xF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Error_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Error(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Error_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Error_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Match_MASK (0xF00000U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Match_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Match(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Match_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_diseng_sig2_Cluster_Match_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW0 - Window 0, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_En_Window0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_En_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_En_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_En_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_En_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_CRC_Window0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_CRC_Window0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_CRC_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_CRC_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_CRC_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaMask_Window0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaMask_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaMask_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaMask_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaMask_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaInv_Window0_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaInv_Window0_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaInv_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaInv_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaInv_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaSel_Window0_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaSel_Window0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaSel_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaSel_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_AlphaSel_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_LocalPanic_Window0_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_LocalPanic_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_LocalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_LocalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_LocalPanic_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_GlobalPanic_Window0_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_GlobalPanic_Window0_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_GlobalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_GlobalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_GlobalPanic_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_Sum_Window0_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_Sum_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_Sum_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_Sum_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW0_diseng_sig2_Sum_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW0 - Window 0, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW0_diseng_sig2_UpperLeft_Y_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW0 - Window 0, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW0_diseng_sig2_LowerRight_Y_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW0 - Window 0, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW0_diseng_sig2_Ref_R_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW0_diseng_sig2_Ref_R_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW0_diseng_sig2_Ref_R_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW0_diseng_sig2_Ref_R_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW0_diseng_sig2_Ref_R_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW0 - Window 0, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW0_diseng_sig2_Ref_G_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW0_diseng_sig2_Ref_G_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW0_diseng_sig2_Ref_G_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW0_diseng_sig2_Ref_G_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW0_diseng_sig2_Ref_G_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW0 - Window 0, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW0_diseng_sig2_Ref_B_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW0_diseng_sig2_Ref_B_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW0_diseng_sig2_Ref_B_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW0_diseng_sig2_Ref_B_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW0_diseng_sig2_Ref_B_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS0_WINDOW0 - Controls of Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaMask_S0_Win0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaMask_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaMask_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaMask_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaMask_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaInv_S0_Win0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaInv_S0_Win0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaInv_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaInv_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaInv_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaSel_S0_Win0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaSel_S0_Win0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaSel_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaSel_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW0_diseng_sig2_AlphaSel_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS1_WINDOW0 - Controls of Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaMask_S1_Win0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaMask_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaMask_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaMask_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaMask_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaInv_S1_Win0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaInv_S1_Win0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaInv_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaInv_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaInv_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaSel_S1_Win0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaSel_S1_Win0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaSel_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaSel_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW0_diseng_sig2_AlphaSel_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_REDSUM_WINDOW0 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW0_diseng_sig2_Min_RSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW0_diseng_sig2_Min_RSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW0_diseng_sig2_Min_RSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW0_diseng_sig2_Min_RSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW0_diseng_sig2_Min_RSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_GREENSUM_WINDOW0 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW0_diseng_sig2_Min_GSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW0_diseng_sig2_Min_GSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW0_diseng_sig2_Min_GSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW0_diseng_sig2_Min_GSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW0_diseng_sig2_Min_GSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_BLUESUM_WINDOW0 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW0_diseng_sig2_Min_BSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW0_diseng_sig2_Min_BSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW0_diseng_sig2_Min_BSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW0_diseng_sig2_Min_BSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW0_diseng_sig2_Min_BSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_LUMSUM_WINDOW0 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW0_diseng_sig2_Min_LSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW0_diseng_sig2_Min_LSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW0_diseng_sig2_Min_LSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW0_diseng_sig2_Min_LSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW0_diseng_sig2_Min_LSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_REDSUM_WINDOW0 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW0_diseng_sig2_Max_RSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW0_diseng_sig2_Max_RSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW0_diseng_sig2_Max_RSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW0_diseng_sig2_Max_RSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW0_diseng_sig2_Max_RSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_GREENSUM_WINDOW0 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW0_diseng_sig2_Max_GSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW0_diseng_sig2_Max_GSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW0_diseng_sig2_Max_GSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW0_diseng_sig2_Max_GSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW0_diseng_sig2_Max_GSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_BLUESUM_WINDOW0 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW0_diseng_sig2_Max_BSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW0_diseng_sig2_Max_BSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW0_diseng_sig2_Max_BSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW0_diseng_sig2_Max_BSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW0_diseng_sig2_Max_BSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_LUMSUM_WINDOW0 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW0_diseng_sig2_Max_LSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW0_diseng_sig2_Max_LSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW0_diseng_sig2_Max_LSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW0_diseng_sig2_Max_LSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW0_diseng_sig2_Max_LSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW1 - Window 1, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_En_Window1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_En_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_En_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_En_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_En_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_CRC_Window1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_CRC_Window1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_CRC_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_CRC_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_CRC_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaMask_Window1_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaMask_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaMask_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaMask_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaMask_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaInv_Window1_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaInv_Window1_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaInv_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaInv_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaInv_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaSel_Window1_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaSel_Window1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaSel_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaSel_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_AlphaSel_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_LocalPanic_Window1_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_LocalPanic_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_LocalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_LocalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_LocalPanic_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_GlobalPanic_Window1_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_GlobalPanic_Window1_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_GlobalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_GlobalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_GlobalPanic_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_Sum_Window1_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_Sum_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_Sum_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_Sum_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW1_diseng_sig2_Sum_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW1 - Window 1, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW1_diseng_sig2_UpperLeft_Y_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW1 - Window 1, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW1_diseng_sig2_LowerRight_Y_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW1 - Window 1, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW1_diseng_sig2_Ref_R_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW1_diseng_sig2_Ref_R_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW1_diseng_sig2_Ref_R_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW1_diseng_sig2_Ref_R_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW1_diseng_sig2_Ref_R_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW1 - Window 1, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW1_diseng_sig2_Ref_G_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW1_diseng_sig2_Ref_G_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW1_diseng_sig2_Ref_G_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW1_diseng_sig2_Ref_G_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW1_diseng_sig2_Ref_G_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW1 - Window 1, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW1_diseng_sig2_Ref_B_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW1_diseng_sig2_Ref_B_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW1_diseng_sig2_Ref_B_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW1_diseng_sig2_Ref_B_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW1_diseng_sig2_Ref_B_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS0_WINDOW1 - Controls of Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaMask_S0_Win1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaMask_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaMask_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaMask_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaMask_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaInv_S0_Win1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaInv_S0_Win1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaInv_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaInv_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaInv_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaSel_S0_Win1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaSel_S0_Win1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaSel_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaSel_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW1_diseng_sig2_AlphaSel_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS1_WINDOW1 - Controls of Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaMask_S1_Win1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaMask_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaMask_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaMask_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaMask_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaInv_S1_Win1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaInv_S1_Win1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaInv_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaInv_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaInv_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaSel_S1_Win1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaSel_S1_Win1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaSel_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaSel_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW1_diseng_sig2_AlphaSel_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_REDSUM_WINDOW1 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW1_diseng_sig2_Min_RSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW1_diseng_sig2_Min_RSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW1_diseng_sig2_Min_RSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW1_diseng_sig2_Min_RSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW1_diseng_sig2_Min_RSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_GREENSUM_WINDOW1 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW1_diseng_sig2_Min_GSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW1_diseng_sig2_Min_GSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW1_diseng_sig2_Min_GSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW1_diseng_sig2_Min_GSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW1_diseng_sig2_Min_GSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_BLUESUM_WINDOW1 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW1_diseng_sig2_Min_BSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW1_diseng_sig2_Min_BSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW1_diseng_sig2_Min_BSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW1_diseng_sig2_Min_BSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW1_diseng_sig2_Min_BSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_LUMSUM_WINDOW1 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW1_diseng_sig2_Min_LSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW1_diseng_sig2_Min_LSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW1_diseng_sig2_Min_LSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW1_diseng_sig2_Min_LSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW1_diseng_sig2_Min_LSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_REDSUM_WINDOW1 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW1_diseng_sig2_Max_RSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW1_diseng_sig2_Max_RSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW1_diseng_sig2_Max_RSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW1_diseng_sig2_Max_RSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW1_diseng_sig2_Max_RSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_GREENSUM_WINDOW1 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW1_diseng_sig2_Max_GSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW1_diseng_sig2_Max_GSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW1_diseng_sig2_Max_GSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW1_diseng_sig2_Max_GSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW1_diseng_sig2_Max_GSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_BLUESUM_WINDOW1 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW1_diseng_sig2_Max_BSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW1_diseng_sig2_Max_BSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW1_diseng_sig2_Max_BSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW1_diseng_sig2_Max_BSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW1_diseng_sig2_Max_BSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_LUMSUM_WINDOW1 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW1_diseng_sig2_Max_LSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW1_diseng_sig2_Max_LSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW1_diseng_sig2_Max_LSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW1_diseng_sig2_Max_LSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW1_diseng_sig2_Max_LSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW2 - Window 2, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_En_Window2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_En_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_En_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_En_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_En_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_CRC_Window2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_CRC_Window2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_CRC_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_CRC_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_CRC_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaMask_Window2_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaMask_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaMask_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaMask_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaMask_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaInv_Window2_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaInv_Window2_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaInv_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaInv_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaInv_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaSel_Window2_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaSel_Window2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaSel_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaSel_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_AlphaSel_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_LocalPanic_Window2_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_LocalPanic_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_LocalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_LocalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_LocalPanic_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_GlobalPanic_Window2_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_GlobalPanic_Window2_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_GlobalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_GlobalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_GlobalPanic_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_Sum_Window2_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_Sum_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_Sum_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_Sum_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW2_diseng_sig2_Sum_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW2 - Window 2, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW2_diseng_sig2_UpperLeft_Y_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW2 - Window 2, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW2_diseng_sig2_LowerRight_Y_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW2 - Window 2, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW2_diseng_sig2_Ref_R_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW2_diseng_sig2_Ref_R_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW2_diseng_sig2_Ref_R_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW2_diseng_sig2_Ref_R_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW2_diseng_sig2_Ref_R_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW2 - Window 2, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW2_diseng_sig2_Ref_G_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW2_diseng_sig2_Ref_G_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW2_diseng_sig2_Ref_G_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW2_diseng_sig2_Ref_G_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW2_diseng_sig2_Ref_G_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW2 - Window 2, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW2_diseng_sig2_Ref_B_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW2_diseng_sig2_Ref_B_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW2_diseng_sig2_Ref_B_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW2_diseng_sig2_Ref_B_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW2_diseng_sig2_Ref_B_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS0_WINDOW2 - Controls of Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaMask_S0_Win2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaMask_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaMask_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaMask_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaMask_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaInv_S0_Win2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaInv_S0_Win2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaInv_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaInv_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaInv_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaSel_S0_Win2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaSel_S0_Win2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaSel_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaSel_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW2_diseng_sig2_AlphaSel_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS1_WINDOW2 - Controls of Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaMask_S1_Win2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaMask_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaMask_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaMask_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaMask_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaInv_S1_Win2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaInv_S1_Win2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaInv_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaInv_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaInv_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaSel_S1_Win2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaSel_S1_Win2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaSel_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaSel_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW2_diseng_sig2_AlphaSel_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_REDSUM_WINDOW2 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW2_diseng_sig2_Min_RSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW2_diseng_sig2_Min_RSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW2_diseng_sig2_Min_RSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW2_diseng_sig2_Min_RSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW2_diseng_sig2_Min_RSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_GREENSUM_WINDOW2 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW2_diseng_sig2_Min_GSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW2_diseng_sig2_Min_GSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW2_diseng_sig2_Min_GSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW2_diseng_sig2_Min_GSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW2_diseng_sig2_Min_GSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_BLUESUM_WINDOW2 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW2_diseng_sig2_Min_BSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW2_diseng_sig2_Min_BSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW2_diseng_sig2_Min_BSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW2_diseng_sig2_Min_BSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW2_diseng_sig2_Min_BSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_LUMSUM_WINDOW2 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW2_diseng_sig2_Min_LSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW2_diseng_sig2_Min_LSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW2_diseng_sig2_Min_LSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW2_diseng_sig2_Min_LSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW2_diseng_sig2_Min_LSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_REDSUM_WINDOW2 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW2_diseng_sig2_Max_RSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW2_diseng_sig2_Max_RSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW2_diseng_sig2_Max_RSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW2_diseng_sig2_Max_RSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW2_diseng_sig2_Max_RSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_GREENSUM_WINDOW2 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW2_diseng_sig2_Max_GSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW2_diseng_sig2_Max_GSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW2_diseng_sig2_Max_GSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW2_diseng_sig2_Max_GSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW2_diseng_sig2_Max_GSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_BLUESUM_WINDOW2 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW2_diseng_sig2_Max_BSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW2_diseng_sig2_Max_BSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW2_diseng_sig2_Max_BSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW2_diseng_sig2_Max_BSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW2_diseng_sig2_Max_BSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_LUMSUM_WINDOW2 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW2_diseng_sig2_Max_LSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW2_diseng_sig2_Max_LSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW2_diseng_sig2_Max_LSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW2_diseng_sig2_Max_LSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW2_diseng_sig2_Max_LSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW3 - Window 3, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_En_Window3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_En_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_En_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_En_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_En_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_CRC_Window3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_CRC_Window3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_CRC_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_CRC_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_CRC_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaMask_Window3_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaMask_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaMask_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaMask_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaMask_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaInv_Window3_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaInv_Window3_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaInv_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaInv_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaInv_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaSel_Window3_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaSel_Window3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaSel_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaSel_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_AlphaSel_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_LocalPanic_Window3_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_LocalPanic_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_LocalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_LocalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_LocalPanic_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_GlobalPanic_Window3_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_GlobalPanic_Window3_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_GlobalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_GlobalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_GlobalPanic_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_Sum_Window3_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_Sum_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_Sum_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_Sum_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW3_diseng_sig2_Sum_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW3 - Window 3, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW3_diseng_sig2_UpperLeft_Y_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW3 - Window 3, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW3_diseng_sig2_LowerRight_Y_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW3 - Window 3, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW3_diseng_sig2_Ref_R_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW3_diseng_sig2_Ref_R_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW3_diseng_sig2_Ref_R_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW3_diseng_sig2_Ref_R_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW3_diseng_sig2_Ref_R_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW3 - Window 3, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW3_diseng_sig2_Ref_G_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW3_diseng_sig2_Ref_G_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW3_diseng_sig2_Ref_G_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW3_diseng_sig2_Ref_G_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW3_diseng_sig2_Ref_G_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW3 - Window 3, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW3_diseng_sig2_Ref_B_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW3_diseng_sig2_Ref_B_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW3_diseng_sig2_Ref_B_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW3_diseng_sig2_Ref_B_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW3_diseng_sig2_Ref_B_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS0_WINDOW3 - Controls of Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaMask_S0_Win3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaMask_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaMask_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaMask_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaMask_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaInv_S0_Win3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaInv_S0_Win3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaInv_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaInv_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaInv_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaSel_S0_Win3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaSel_S0_Win3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaSel_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaSel_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS0_WINDOW3_diseng_sig2_AlphaSel_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_STATS1_WINDOW3 - Controls of Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaMask_S1_Win3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaMask_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaMask_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaMask_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaMask_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaInv_S1_Win3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaInv_S1_Win3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaInv_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaInv_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaInv_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaSel_S1_Win3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaSel_S1_Win3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaSel_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaSel_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATS1_WINDOW3_diseng_sig2_AlphaSel_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_REDSUM_WINDOW3 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW3_diseng_sig2_Min_RSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW3_diseng_sig2_Min_RSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW3_diseng_sig2_Min_RSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW3_diseng_sig2_Min_RSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_REDSUM_WINDOW3_diseng_sig2_Min_RSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_GREENSUM_WINDOW3 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW3_diseng_sig2_Min_GSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW3_diseng_sig2_Min_GSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW3_diseng_sig2_Min_GSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW3_diseng_sig2_Min_GSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_GREENSUM_WINDOW3_diseng_sig2_Min_GSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_BLUESUM_WINDOW3 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW3_diseng_sig2_Min_BSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW3_diseng_sig2_Min_BSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW3_diseng_sig2_Min_BSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW3_diseng_sig2_Min_BSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_BLUESUM_WINDOW3_diseng_sig2_Min_BSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MIN_LUMSUM_WINDOW3 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW3_diseng_sig2_Min_LSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW3_diseng_sig2_Min_LSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW3_diseng_sig2_Min_LSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW3_diseng_sig2_Min_LSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MIN_LUMSUM_WINDOW3_diseng_sig2_Min_LSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_REDSUM_WINDOW3 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW3_diseng_sig2_Max_RSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW3_diseng_sig2_Max_RSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW3_diseng_sig2_Max_RSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW3_diseng_sig2_Max_RSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_REDSUM_WINDOW3_diseng_sig2_Max_RSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_GREENSUM_WINDOW3 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW3_diseng_sig2_Max_GSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW3_diseng_sig2_Max_GSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW3_diseng_sig2_Max_GSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW3_diseng_sig2_Max_GSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_GREENSUM_WINDOW3_diseng_sig2_Max_GSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_BLUESUM_WINDOW3 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW3_diseng_sig2_Max_BSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW3_diseng_sig2_Max_BSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW3_diseng_sig2_Max_BSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW3_diseng_sig2_Max_BSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_BLUESUM_WINDOW3_diseng_sig2_Max_BSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_MAX_LUMSUM_WINDOW3 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW3_diseng_sig2_Max_LSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW3_diseng_sig2_Max_LSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW3_diseng_sig2_Max_LSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW3_diseng_sig2_Max_LSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_MAX_LUMSUM_WINDOW3_diseng_sig2_Max_LSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW4 - Window 4, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_En_Window4_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_En_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_En_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_En_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_En_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_CRC_Window4_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_CRC_Window4_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_CRC_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_CRC_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_CRC_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaMask_Window4_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaMask_Window4_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaMask_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaMask_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaMask_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaInv_Window4_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaInv_Window4_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaInv_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaInv_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaInv_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaSel_Window4_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaSel_Window4_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaSel_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaSel_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_AlphaSel_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_LocalPanic_Window4_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_LocalPanic_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_LocalPanic_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_LocalPanic_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_LocalPanic_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_GlobalPanic_Window4_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_GlobalPanic_Window4_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_GlobalPanic_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_GlobalPanic_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW4_diseng_sig2_GlobalPanic_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW4 - Window 4, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_X_Window4_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_X_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_X_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_X_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_X_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_Y_Window4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_Y_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_Y_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_Y_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW4_diseng_sig2_UpperLeft_Y_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW4 - Window 4, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_X_Window4_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_X_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_X_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_X_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_X_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_Y_Window4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_Y_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_Y_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_Y_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW4_diseng_sig2_LowerRight_Y_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW4 - Window 4, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW4_diseng_sig2_Ref_R_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW4_diseng_sig2_Ref_R_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW4_diseng_sig2_Ref_R_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW4_diseng_sig2_Ref_R_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW4_diseng_sig2_Ref_R_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW4 - Window 4, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW4_diseng_sig2_Ref_G_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW4_diseng_sig2_Ref_G_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW4_diseng_sig2_Ref_G_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW4_diseng_sig2_Ref_G_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW4_diseng_sig2_Ref_G_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW4 - Window 4, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW4_diseng_sig2_Ref_B_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW4_diseng_sig2_Ref_B_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW4_diseng_sig2_Ref_B_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW4_diseng_sig2_Ref_B_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW4_diseng_sig2_Ref_B_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW5 - Window 5, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_En_Window5_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_En_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_En_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_En_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_En_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_CRC_Window5_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_CRC_Window5_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_CRC_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_CRC_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_CRC_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaMask_Window5_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaMask_Window5_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaMask_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaMask_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaMask_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaInv_Window5_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaInv_Window5_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaInv_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaInv_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaInv_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaSel_Window5_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaSel_Window5_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaSel_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaSel_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_AlphaSel_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_LocalPanic_Window5_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_LocalPanic_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_LocalPanic_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_LocalPanic_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_LocalPanic_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_GlobalPanic_Window5_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_GlobalPanic_Window5_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_GlobalPanic_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_GlobalPanic_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW5_diseng_sig2_GlobalPanic_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW5 - Window 5, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_X_Window5_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_X_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_X_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_X_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_X_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_Y_Window5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_Y_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_Y_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_Y_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW5_diseng_sig2_UpperLeft_Y_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW5 - Window 5, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_X_Window5_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_X_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_X_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_X_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_X_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_Y_Window5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_Y_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_Y_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_Y_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW5_diseng_sig2_LowerRight_Y_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW5 - Window 5, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW5_diseng_sig2_Ref_R_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW5_diseng_sig2_Ref_R_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW5_diseng_sig2_Ref_R_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW5_diseng_sig2_Ref_R_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW5_diseng_sig2_Ref_R_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW5 - Window 5, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW5_diseng_sig2_Ref_G_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW5_diseng_sig2_Ref_G_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW5_diseng_sig2_Ref_G_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW5_diseng_sig2_Ref_G_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW5_diseng_sig2_Ref_G_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW5 - Window 5, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW5_diseng_sig2_Ref_B_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW5_diseng_sig2_Ref_B_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW5_diseng_sig2_Ref_B_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW5_diseng_sig2_Ref_B_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW5_diseng_sig2_Ref_B_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW6 - Window 6, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_En_Window6_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_En_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_En_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_En_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_En_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_CRC_Window6_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_CRC_Window6_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_CRC_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_CRC_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_CRC_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaMask_Window6_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaMask_Window6_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaMask_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaMask_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaMask_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaInv_Window6_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaInv_Window6_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaInv_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaInv_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaInv_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaSel_Window6_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaSel_Window6_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaSel_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaSel_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_AlphaSel_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_LocalPanic_Window6_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_LocalPanic_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_LocalPanic_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_LocalPanic_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_LocalPanic_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_GlobalPanic_Window6_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_GlobalPanic_Window6_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_GlobalPanic_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_GlobalPanic_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW6_diseng_sig2_GlobalPanic_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW6 - Window 6, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_X_Window6_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_X_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_X_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_X_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_X_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_Y_Window6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_Y_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_Y_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_Y_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW6_diseng_sig2_UpperLeft_Y_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW6 - Window 6, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_X_Window6_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_X_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_X_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_X_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_X_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_Y_Window6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_Y_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_Y_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_Y_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW6_diseng_sig2_LowerRight_Y_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW6 - Window 6, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW6_diseng_sig2_Ref_R_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW6_diseng_sig2_Ref_R_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW6_diseng_sig2_Ref_R_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW6_diseng_sig2_Ref_R_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW6_diseng_sig2_Ref_R_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW6 - Window 6, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW6_diseng_sig2_Ref_G_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW6_diseng_sig2_Ref_G_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW6_diseng_sig2_Ref_G_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW6_diseng_sig2_Ref_G_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW6_diseng_sig2_Ref_G_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW6 - Window 6, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW6_diseng_sig2_Ref_B_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW6_diseng_sig2_Ref_B_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW6_diseng_sig2_Ref_B_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW6_diseng_sig2_Ref_B_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW6_diseng_sig2_Ref_B_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_WINDOW7 - Window 7, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_En_Window7_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_En_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_En_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_En_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_En_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_CRC_Window7_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_CRC_Window7_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_CRC_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_CRC_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_CRC_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaMask_Window7_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaMask_Window7_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaMask_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaMask_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaMask_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaInv_Window7_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaInv_Window7_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaInv_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaInv_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaInv_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaSel_Window7_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaSel_Window7_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaSel_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaSel_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_AlphaSel_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_LocalPanic_Window7_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_LocalPanic_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_LocalPanic_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_LocalPanic_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_LocalPanic_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_GlobalPanic_Window7_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_GlobalPanic_Window7_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_GlobalPanic_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_GlobalPanic_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_WINDOW7_diseng_sig2_GlobalPanic_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_UPPERLEFT_WINDOW7 - Window 7, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_X_Window7_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_X_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_X_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_X_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_X_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_Y_Window7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_Y_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_Y_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_Y_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_UPPERLEFT_WINDOW7_diseng_sig2_UpperLeft_Y_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_LOWERRIGHT_WINDOW7 - Window 7, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_X_Window7_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_X_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_X_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_X_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_X_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_Y_Window7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_Y_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_Y_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_Y_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LOWERRIGHT_WINDOW7_diseng_sig2_LowerRight_Y_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_R_WINDOW7 - Window 7, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW7_diseng_sig2_Ref_R_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW7_diseng_sig2_Ref_R_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW7_diseng_sig2_Ref_R_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW7_diseng_sig2_Ref_R_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_R_WINDOW7_diseng_sig2_Ref_R_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_G_WINDOW7 - Window 7, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW7_diseng_sig2_Ref_G_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW7_diseng_sig2_Ref_G_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW7_diseng_sig2_Ref_G_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW7_diseng_sig2_Ref_G_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_G_WINDOW7_diseng_sig2_Ref_G_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_REF_B_WINDOW7 - Window 7, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW7_diseng_sig2_Ref_B_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW7_diseng_sig2_Ref_B_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW7_diseng_sig2_Ref_B_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW7_diseng_sig2_Ref_B_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF_B_WINDOW7_diseng_sig2_Ref_B_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_CLUSTER0 - Cluster 0, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_En_Cluster0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_En_Cluster0_SHIFT (0U) /*! diseng_sig2_En_Cluster0 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix0_En_Cluster0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix0_En_Cluster0_SHIFT (4U) /*! diseng_sig2_Pix0_En_Cluster0 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix0_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix0_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix0_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix1_En_Cluster0_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix1_En_Cluster0_SHIFT (5U) /*! diseng_sig2_Pix1_En_Cluster0 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix1_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix1_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix1_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix2_En_Cluster0_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix2_En_Cluster0_SHIFT (6U) /*! diseng_sig2_Pix2_En_Cluster0 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix2_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix2_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix2_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix3_En_Cluster0_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix3_En_Cluster0_SHIFT (7U) /*! diseng_sig2_Pix3_En_Cluster0 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix3_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix3_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_Pix3_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskBlue_Cluster0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskBlue_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskBlue_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskBlue_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskBlue_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskGreen_Cluster0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskGreen_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskGreen_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskGreen_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskGreen_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskRed_Cluster0_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskRed_Cluster0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskRed_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskRed_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER0_diseng_sig2_MaskRed_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX0_CLUSTER0 - Cluster 0, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_X0_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_X0_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_X0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_X0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_X0_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_Y0_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_Y0_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_Y0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_Y0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER0_diseng_sig2_Y0_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX1_CLUSTER0 - Cluster 0, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_X1_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_X1_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_X1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_X1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_X1_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_Y1_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_Y1_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_Y1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_Y1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER0_diseng_sig2_Y1_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX2_CLUSTER0 - Cluster 0, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_X2_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_X2_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_X2_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_X2_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_X2_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_Y2_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_Y2_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_Y2_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_Y2_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER0_diseng_sig2_Y2_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX3_CLUSTER0 - Cluster 0, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_X3_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_X3_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_X3_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_X3_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_X3_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_Y3_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_Y3_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_Y3_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_Y3_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER0_diseng_sig2_Y3_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_REF0_CLUSTER0 - Cluster 0, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER0_diseng_sig2_Ref0_Cluster0_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER0_diseng_sig2_Ref0_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER0_diseng_sig2_Ref0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER0_diseng_sig2_Ref0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER0_diseng_sig2_Ref0_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_REF1_CLUSTER0 - Cluster 0, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER0_diseng_sig2_Ref1_Cluster0_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER0_diseng_sig2_Ref1_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER0_diseng_sig2_Ref1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER0_diseng_sig2_Ref1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER0_diseng_sig2_Ref1_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_CLUSTER1 - Cluster 1, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_En_Cluster1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_En_Cluster1_SHIFT (0U) /*! diseng_sig2_En_Cluster1 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix0_En_Cluster1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix0_En_Cluster1_SHIFT (4U) /*! diseng_sig2_Pix0_En_Cluster1 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix0_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix0_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix0_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix1_En_Cluster1_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix1_En_Cluster1_SHIFT (5U) /*! diseng_sig2_Pix1_En_Cluster1 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix1_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix1_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix1_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix2_En_Cluster1_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix2_En_Cluster1_SHIFT (6U) /*! diseng_sig2_Pix2_En_Cluster1 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix2_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix2_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix2_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix3_En_Cluster1_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix3_En_Cluster1_SHIFT (7U) /*! diseng_sig2_Pix3_En_Cluster1 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix3_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix3_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_Pix3_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskBlue_Cluster1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskBlue_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskBlue_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskBlue_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskBlue_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskGreen_Cluster1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskGreen_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskGreen_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskGreen_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskGreen_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskRed_Cluster1_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskRed_Cluster1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskRed_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskRed_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER1_diseng_sig2_MaskRed_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX0_CLUSTER1 - Cluster 1, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_X0_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_X0_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_X0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_X0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_X0_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_Y0_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_Y0_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_Y0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_Y0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER1_diseng_sig2_Y0_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX1_CLUSTER1 - Cluster 1, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_X1_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_X1_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_X1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_X1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_X1_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_Y1_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_Y1_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_Y1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_Y1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER1_diseng_sig2_Y1_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX2_CLUSTER1 - Cluster 1, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_X2_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_X2_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_X2_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_X2_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_X2_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_Y2_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_Y2_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_Y2_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_Y2_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER1_diseng_sig2_Y2_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX3_CLUSTER1 - Cluster 1, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_X3_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_X3_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_X3_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_X3_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_X3_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_Y3_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_Y3_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_Y3_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_Y3_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER1_diseng_sig2_Y3_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_REF0_CLUSTER1 - Cluster 1, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER1_diseng_sig2_Ref0_Cluster1_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER1_diseng_sig2_Ref0_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER1_diseng_sig2_Ref0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER1_diseng_sig2_Ref0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER1_diseng_sig2_Ref0_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_REF1_CLUSTER1 - Cluster 1, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER1_diseng_sig2_Ref1_Cluster1_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER1_diseng_sig2_Ref1_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER1_diseng_sig2_Ref1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER1_diseng_sig2_Ref1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER1_diseng_sig2_Ref1_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_CLUSTER2 - Cluster 2, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_En_Cluster2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_En_Cluster2_SHIFT (0U) /*! diseng_sig2_En_Cluster2 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix0_En_Cluster2_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix0_En_Cluster2_SHIFT (4U) /*! diseng_sig2_Pix0_En_Cluster2 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix0_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix0_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix0_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix1_En_Cluster2_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix1_En_Cluster2_SHIFT (5U) /*! diseng_sig2_Pix1_En_Cluster2 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix1_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix1_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix1_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix2_En_Cluster2_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix2_En_Cluster2_SHIFT (6U) /*! diseng_sig2_Pix2_En_Cluster2 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix2_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix2_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix2_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix3_En_Cluster2_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix3_En_Cluster2_SHIFT (7U) /*! diseng_sig2_Pix3_En_Cluster2 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix3_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix3_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_Pix3_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskBlue_Cluster2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskBlue_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskBlue_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskBlue_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskBlue_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskGreen_Cluster2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskGreen_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskGreen_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskGreen_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskGreen_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskRed_Cluster2_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskRed_Cluster2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskRed_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskRed_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER2_diseng_sig2_MaskRed_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX0_CLUSTER2 - Cluster 2, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_X0_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_X0_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_X0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_X0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_X0_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_Y0_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_Y0_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_Y0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_Y0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER2_diseng_sig2_Y0_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX1_CLUSTER2 - Cluster 2, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_X1_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_X1_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_X1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_X1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_X1_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_Y1_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_Y1_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_Y1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_Y1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER2_diseng_sig2_Y1_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX2_CLUSTER2 - Cluster 2, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_X2_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_X2_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_X2_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_X2_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_X2_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_Y2_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_Y2_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_Y2_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_Y2_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER2_diseng_sig2_Y2_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX3_CLUSTER2 - Cluster 2, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_X3_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_X3_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_X3_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_X3_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_X3_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_Y3_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_Y3_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_Y3_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_Y3_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER2_diseng_sig2_Y3_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_REF0_CLUSTER2 - Cluster 2, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER2_diseng_sig2_Ref0_Cluster2_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER2_diseng_sig2_Ref0_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER2_diseng_sig2_Ref0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER2_diseng_sig2_Ref0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER2_diseng_sig2_Ref0_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_REF1_CLUSTER2 - Cluster 2, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER2_diseng_sig2_Ref1_Cluster2_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER2_diseng_sig2_Ref1_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER2_diseng_sig2_Ref1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER2_diseng_sig2_Ref1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER2_diseng_sig2_Ref1_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_CONTROL_CLUSTER3 - Cluster 3, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_En_Cluster3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_En_Cluster3_SHIFT (0U) /*! diseng_sig2_En_Cluster3 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix0_En_Cluster3_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix0_En_Cluster3_SHIFT (4U) /*! diseng_sig2_Pix0_En_Cluster3 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix0_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix0_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix0_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix1_En_Cluster3_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix1_En_Cluster3_SHIFT (5U) /*! diseng_sig2_Pix1_En_Cluster3 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix1_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix1_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix1_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix2_En_Cluster3_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix2_En_Cluster3_SHIFT (6U) /*! diseng_sig2_Pix2_En_Cluster3 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix2_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix2_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix2_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix3_En_Cluster3_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix3_En_Cluster3_SHIFT (7U) /*! diseng_sig2_Pix3_En_Cluster3 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix3_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix3_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_Pix3_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskBlue_Cluster3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskBlue_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskBlue_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskBlue_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskBlue_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskGreen_Cluster3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskGreen_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskGreen_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskGreen_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskGreen_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskRed_Cluster3_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskRed_Cluster3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskRed_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskRed_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CONTROL_CLUSTER3_diseng_sig2_MaskRed_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX0_CLUSTER3 - Cluster 3, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_X0_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_X0_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_X0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_X0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_X0_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_Y0_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_Y0_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_Y0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_Y0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX0_CLUSTER3_diseng_sig2_Y0_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX1_CLUSTER3 - Cluster 3, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_X1_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_X1_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_X1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_X1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_X1_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_Y1_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_Y1_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_Y1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_Y1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX1_CLUSTER3_diseng_sig2_Y1_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX2_CLUSTER3 - Cluster 3, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_X2_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_X2_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_X2_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_X2_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_X2_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_Y2_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_Y2_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_Y2_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_Y2_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX2_CLUSTER3_diseng_sig2_Y2_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIX3_CLUSTER3 - Cluster 3, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_X3_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_X3_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_X3_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_X3_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_X3_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_Y3_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_Y3_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_Y3_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_Y3_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIX3_CLUSTER3_diseng_sig2_Y3_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_REF0_CLUSTER3 - Cluster 3, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER3_diseng_sig2_Ref0_Cluster3_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER3_diseng_sig2_Ref0_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER3_diseng_sig2_Ref0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER3_diseng_sig2_Ref0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF0_CLUSTER3_diseng_sig2_Ref0_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_REF1_CLUSTER3 - Cluster 3, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER3_diseng_sig2_Ref1_Cluster3_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER3_diseng_sig2_Ref1_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER3_diseng_sig2_Ref1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER3_diseng_sig2_Ref1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REF1_CLUSTER3_diseng_sig2_Ref1_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW0 - Window 0, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW0_diseng_sig2_CRC_R_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW0_diseng_sig2_CRC_R_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW0_diseng_sig2_CRC_R_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW0_diseng_sig2_CRC_R_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW0_diseng_sig2_CRC_R_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW0 - Window 0, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW0_diseng_sig2_CRC_G_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW0_diseng_sig2_CRC_G_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW0_diseng_sig2_CRC_G_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW0_diseng_sig2_CRC_G_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW0_diseng_sig2_CRC_G_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW0 - Window 0, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW0_diseng_sig2_CRC_B_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW0_diseng_sig2_CRC_B_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW0_diseng_sig2_CRC_B_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW0_diseng_sig2_CRC_B_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW0_diseng_sig2_CRC_B_Window0_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW1 - Window 1, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW1_diseng_sig2_CRC_R_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW1_diseng_sig2_CRC_R_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW1_diseng_sig2_CRC_R_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW1_diseng_sig2_CRC_R_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW1_diseng_sig2_CRC_R_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW1 - Window 1, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW1_diseng_sig2_CRC_G_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW1_diseng_sig2_CRC_G_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW1_diseng_sig2_CRC_G_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW1_diseng_sig2_CRC_G_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW1_diseng_sig2_CRC_G_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW1 - Window 1, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW1_diseng_sig2_CRC_B_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW1_diseng_sig2_CRC_B_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW1_diseng_sig2_CRC_B_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW1_diseng_sig2_CRC_B_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW1_diseng_sig2_CRC_B_Window1_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW2 - Window 2, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW2_diseng_sig2_CRC_R_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW2_diseng_sig2_CRC_R_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW2_diseng_sig2_CRC_R_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW2_diseng_sig2_CRC_R_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW2_diseng_sig2_CRC_R_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW2 - Window 2, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW2_diseng_sig2_CRC_G_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW2_diseng_sig2_CRC_G_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW2_diseng_sig2_CRC_G_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW2_diseng_sig2_CRC_G_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW2_diseng_sig2_CRC_G_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW2 - Window 2, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW2_diseng_sig2_CRC_B_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW2_diseng_sig2_CRC_B_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW2_diseng_sig2_CRC_B_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW2_diseng_sig2_CRC_B_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW2_diseng_sig2_CRC_B_Window2_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW3 - Window 3, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW3_diseng_sig2_CRC_R_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW3_diseng_sig2_CRC_R_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW3_diseng_sig2_CRC_R_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW3_diseng_sig2_CRC_R_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW3_diseng_sig2_CRC_R_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW3 - Window 3, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW3_diseng_sig2_CRC_G_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW3_diseng_sig2_CRC_G_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW3_diseng_sig2_CRC_G_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW3_diseng_sig2_CRC_G_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW3_diseng_sig2_CRC_G_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW3 - Window 3, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW3_diseng_sig2_CRC_B_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW3_diseng_sig2_CRC_B_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW3_diseng_sig2_CRC_B_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW3_diseng_sig2_CRC_B_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW3_diseng_sig2_CRC_B_Window3_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW4 - Window 4, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW4_diseng_sig2_CRC_R_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW4_diseng_sig2_CRC_R_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW4_diseng_sig2_CRC_R_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW4_diseng_sig2_CRC_R_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW4_diseng_sig2_CRC_R_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW4 - Window 4, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW4_diseng_sig2_CRC_G_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW4_diseng_sig2_CRC_G_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW4_diseng_sig2_CRC_G_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW4_diseng_sig2_CRC_G_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW4_diseng_sig2_CRC_G_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW4 - Window 4, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW4_diseng_sig2_CRC_B_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW4_diseng_sig2_CRC_B_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW4_diseng_sig2_CRC_B_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW4_diseng_sig2_CRC_B_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW4_diseng_sig2_CRC_B_Window4_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW5 - Window 5, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW5_diseng_sig2_CRC_R_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW5_diseng_sig2_CRC_R_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW5_diseng_sig2_CRC_R_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW5_diseng_sig2_CRC_R_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW5_diseng_sig2_CRC_R_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW5 - Window 5, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW5_diseng_sig2_CRC_G_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW5_diseng_sig2_CRC_G_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW5_diseng_sig2_CRC_G_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW5_diseng_sig2_CRC_G_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW5_diseng_sig2_CRC_G_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW5 - Window 5, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW5_diseng_sig2_CRC_B_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW5_diseng_sig2_CRC_B_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW5_diseng_sig2_CRC_B_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW5_diseng_sig2_CRC_B_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW5_diseng_sig2_CRC_B_Window5_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW6 - Window 6, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW6_diseng_sig2_CRC_R_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW6_diseng_sig2_CRC_R_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW6_diseng_sig2_CRC_R_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW6_diseng_sig2_CRC_R_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW6_diseng_sig2_CRC_R_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW6 - Window 6, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW6_diseng_sig2_CRC_G_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW6_diseng_sig2_CRC_G_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW6_diseng_sig2_CRC_G_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW6_diseng_sig2_CRC_G_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW6_diseng_sig2_CRC_G_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW6 - Window 6, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW6_diseng_sig2_CRC_B_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW6_diseng_sig2_CRC_B_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW6_diseng_sig2_CRC_B_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW6_diseng_sig2_CRC_B_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW6_diseng_sig2_CRC_B_Window6_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_R_WINDOW7 - Window 7, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW7_diseng_sig2_CRC_R_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW7_diseng_sig2_CRC_R_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW7_diseng_sig2_CRC_R_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW7_diseng_sig2_CRC_R_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_R_WINDOW7_diseng_sig2_CRC_R_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_G_WINDOW7 - Window 7, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW7_diseng_sig2_CRC_G_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW7_diseng_sig2_CRC_G_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW7_diseng_sig2_CRC_G_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW7_diseng_sig2_CRC_G_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_G_WINDOW7_diseng_sig2_CRC_G_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_CRC_B_WINDOW7 - Window 7, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW7_diseng_sig2_CRC_B_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW7_diseng_sig2_CRC_B_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW7_diseng_sig2_CRC_B_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW7_diseng_sig2_CRC_B_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_CRC_B_WINDOW7_diseng_sig2_CRC_B_Window7_MASK) /*! @} */ /*! @name DISENG_SIG2_STATUS_CLUSTER0 - Cluster 0, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts00_Cluster0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts00_Cluster0_SHIFT (0U) /*! diseng_sig2_Sts00_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts00_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts00_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts00_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts01_Cluster0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts01_Cluster0_SHIFT (1U) /*! diseng_sig2_Sts01_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts01_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts01_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts01_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts10_Cluster0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts10_Cluster0_SHIFT (2U) /*! diseng_sig2_Sts10_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts11_Cluster0_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts11_Cluster0_SHIFT (3U) /*! diseng_sig2_Sts11_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts11_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts11_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts11_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts20_Cluster0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts20_Cluster0_SHIFT (4U) /*! diseng_sig2_Sts20_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts20_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts20_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts20_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts21_Cluster0_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts21_Cluster0_SHIFT (5U) /*! diseng_sig2_Sts21_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts21_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts21_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts21_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts30_Cluster0_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts30_Cluster0_SHIFT (6U) /*! diseng_sig2_Sts30_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts30_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts30_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts30_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts31_Cluster0_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts31_Cluster0_SHIFT (7U) /*! diseng_sig2_Sts31_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts31_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts31_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER0_diseng_sig2_Sts31_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_COUNTER_CLUSTER0 - Cluster 0, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_MatchCount_Cluster0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_MatchCount_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_MatchCount_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_MatchCount_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_MatchCount_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_ErrorCount_Cluster0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_ErrorCount_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_ErrorCount_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_ErrorCount_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER0_diseng_sig2_ErrorCount_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR0_CLUSTER0 - Cluster 0, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_B10_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_B10_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_G10_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_G10_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_R10_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_R10_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix0_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_B10_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_B10_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_G10_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_G10_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_R10_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_R10_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix1_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_B10_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_B10_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_G10_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_G10_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_R10_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_R10_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix2_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_B10_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_B10_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_G10_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_G10_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_R10_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_R10_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER0_diseng_sig2_Pix3_R10_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR1_CLUSTER0 - Cluster 0, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_B32_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_B32_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_G32_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_G32_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_R32_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_R32_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix0_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_B32_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_B32_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_G32_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_G32_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_R32_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_R32_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix1_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_B32_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_B32_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_G32_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_G32_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_R32_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_R32_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix2_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_B32_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_B32_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_G32_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_G32_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_R32_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_R32_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER0_diseng_sig2_Pix3_R32_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR2_CLUSTER0 - Cluster 0, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_B54_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_B54_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_G54_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_G54_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_R54_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_R54_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix0_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_B54_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_B54_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_G54_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_G54_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_R54_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_R54_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix1_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_B54_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_B54_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_G54_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_G54_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_R54_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_R54_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix2_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_B54_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_B54_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_G54_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_G54_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_R54_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_R54_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER0_diseng_sig2_Pix3_R54_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR3_CLUSTER0 - Cluster 0, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_B76_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_B76_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_G76_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_G76_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_R76_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_R76_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix0_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_B76_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_B76_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_G76_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_G76_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_R76_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_R76_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix1_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_B76_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_B76_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_G76_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_G76_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_R76_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_R76_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix2_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_B76_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_B76_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_G76_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_G76_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_R76_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_R76_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER0_diseng_sig2_Pix3_R76_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG2_STATUS_CLUSTER1 - Cluster 1, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts00_Cluster1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts00_Cluster1_SHIFT (0U) /*! diseng_sig2_Sts00_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts00_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts00_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts00_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts01_Cluster1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts01_Cluster1_SHIFT (1U) /*! diseng_sig2_Sts01_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts01_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts01_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts01_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts10_Cluster1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts10_Cluster1_SHIFT (2U) /*! diseng_sig2_Sts10_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts11_Cluster1_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts11_Cluster1_SHIFT (3U) /*! diseng_sig2_Sts11_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts11_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts11_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts11_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts20_Cluster1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts20_Cluster1_SHIFT (4U) /*! diseng_sig2_Sts20_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts20_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts20_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts20_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts21_Cluster1_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts21_Cluster1_SHIFT (5U) /*! diseng_sig2_Sts21_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts21_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts21_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts21_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts30_Cluster1_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts30_Cluster1_SHIFT (6U) /*! diseng_sig2_Sts30_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts30_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts30_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts30_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts31_Cluster1_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts31_Cluster1_SHIFT (7U) /*! diseng_sig2_Sts31_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts31_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts31_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER1_diseng_sig2_Sts31_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_COUNTER_CLUSTER1 - Cluster 1, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_MatchCount_Cluster1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_MatchCount_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_MatchCount_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_MatchCount_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_MatchCount_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_ErrorCount_Cluster1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_ErrorCount_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_ErrorCount_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_ErrorCount_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER1_diseng_sig2_ErrorCount_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR0_CLUSTER1 - Cluster 1, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_B10_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_B10_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_G10_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_G10_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_R10_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_R10_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix0_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_B10_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_B10_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_G10_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_G10_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_R10_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_R10_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix1_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_B10_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_B10_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_G10_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_G10_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_R10_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_R10_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix2_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_B10_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_B10_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_G10_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_G10_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_R10_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_R10_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER1_diseng_sig2_Pix3_R10_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR1_CLUSTER1 - Cluster 1, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_B32_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_B32_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_G32_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_G32_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_R32_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_R32_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix0_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_B32_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_B32_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_G32_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_G32_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_R32_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_R32_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix1_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_B32_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_B32_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_G32_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_G32_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_R32_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_R32_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix2_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_B32_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_B32_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_G32_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_G32_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_R32_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_R32_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER1_diseng_sig2_Pix3_R32_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR2_CLUSTER1 - Cluster 1, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_B54_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_B54_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_G54_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_G54_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_R54_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_R54_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix0_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_B54_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_B54_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_G54_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_G54_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_R54_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_R54_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix1_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_B54_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_B54_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_G54_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_G54_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_R54_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_R54_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix2_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_B54_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_B54_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_G54_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_G54_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_R54_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_R54_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER1_diseng_sig2_Pix3_R54_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR3_CLUSTER1 - Cluster 1, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_B76_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_B76_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_G76_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_G76_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_R76_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_R76_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix0_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_B76_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_B76_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_G76_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_G76_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_R76_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_R76_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix1_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_B76_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_B76_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_G76_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_G76_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_R76_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_R76_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix2_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_B76_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_B76_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_G76_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_G76_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_R76_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_R76_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER1_diseng_sig2_Pix3_R76_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG2_STATUS_CLUSTER2 - Cluster 2, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts00_Cluster2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts00_Cluster2_SHIFT (0U) /*! diseng_sig2_Sts00_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts00_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts00_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts00_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts01_Cluster2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts01_Cluster2_SHIFT (1U) /*! diseng_sig2_Sts01_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts01_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts01_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts01_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts10_Cluster2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts10_Cluster2_SHIFT (2U) /*! diseng_sig2_Sts10_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts11_Cluster2_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts11_Cluster2_SHIFT (3U) /*! diseng_sig2_Sts11_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts11_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts11_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts11_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts20_Cluster2_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts20_Cluster2_SHIFT (4U) /*! diseng_sig2_Sts20_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts20_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts20_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts20_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts21_Cluster2_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts21_Cluster2_SHIFT (5U) /*! diseng_sig2_Sts21_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts21_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts21_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts21_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts30_Cluster2_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts30_Cluster2_SHIFT (6U) /*! diseng_sig2_Sts30_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts30_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts30_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts30_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts31_Cluster2_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts31_Cluster2_SHIFT (7U) /*! diseng_sig2_Sts31_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts31_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts31_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER2_diseng_sig2_Sts31_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_COUNTER_CLUSTER2 - Cluster 2, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_MatchCount_Cluster2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_MatchCount_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_MatchCount_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_MatchCount_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_MatchCount_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_ErrorCount_Cluster2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_ErrorCount_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_ErrorCount_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_ErrorCount_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER2_diseng_sig2_ErrorCount_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR0_CLUSTER2 - Cluster 2, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_B10_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_B10_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_G10_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_G10_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_R10_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_R10_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix0_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_B10_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_B10_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_G10_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_G10_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_R10_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_R10_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix1_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_B10_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_B10_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_G10_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_G10_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_R10_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_R10_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix2_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_B10_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_B10_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_G10_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_G10_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_R10_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_R10_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER2_diseng_sig2_Pix3_R10_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR1_CLUSTER2 - Cluster 2, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_B32_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_B32_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_G32_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_G32_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_R32_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_R32_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix0_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_B32_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_B32_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_G32_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_G32_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_R32_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_R32_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix1_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_B32_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_B32_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_G32_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_G32_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_R32_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_R32_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix2_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_B32_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_B32_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_G32_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_G32_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_R32_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_R32_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER2_diseng_sig2_Pix3_R32_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR2_CLUSTER2 - Cluster 2, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_B54_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_B54_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_G54_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_G54_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_R54_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_R54_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix0_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_B54_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_B54_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_G54_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_G54_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_R54_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_R54_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix1_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_B54_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_B54_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_G54_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_G54_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_R54_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_R54_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix2_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_B54_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_B54_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_G54_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_G54_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_R54_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_R54_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER2_diseng_sig2_Pix3_R54_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR3_CLUSTER2 - Cluster 2, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_B76_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_B76_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_G76_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_G76_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_R76_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_R76_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix0_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_B76_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_B76_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_G76_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_G76_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_R76_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_R76_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix1_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_B76_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_B76_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_G76_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_G76_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_R76_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_R76_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix2_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_B76_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_B76_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_G76_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_G76_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_R76_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_R76_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER2_diseng_sig2_Pix3_R76_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG2_STATUS_CLUSTER3 - Cluster 3, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts00_Cluster3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts00_Cluster3_SHIFT (0U) /*! diseng_sig2_Sts00_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts00_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts00_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts00_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts01_Cluster3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts01_Cluster3_SHIFT (1U) /*! diseng_sig2_Sts01_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts01_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts01_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts01_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts10_Cluster3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts10_Cluster3_SHIFT (2U) /*! diseng_sig2_Sts10_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts11_Cluster3_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts11_Cluster3_SHIFT (3U) /*! diseng_sig2_Sts11_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts11_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts11_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts11_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts20_Cluster3_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts20_Cluster3_SHIFT (4U) /*! diseng_sig2_Sts20_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts20_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts20_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts20_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts21_Cluster3_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts21_Cluster3_SHIFT (5U) /*! diseng_sig2_Sts21_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts21_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts21_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts21_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts30_Cluster3_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts30_Cluster3_SHIFT (6U) /*! diseng_sig2_Sts30_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts30_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts30_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts30_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts31_Cluster3_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts31_Cluster3_SHIFT (7U) /*! diseng_sig2_Sts31_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts31_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts31_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_STATUS_CLUSTER3_diseng_sig2_Sts31_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_COUNTER_CLUSTER3 - Cluster 3, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_MatchCount_Cluster3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_MatchCount_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_MatchCount_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_MatchCount_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_MatchCount_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_ErrorCount_Cluster3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_ErrorCount_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_ErrorCount_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_ErrorCount_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_COUNTER_CLUSTER3_diseng_sig2_ErrorCount_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR0_CLUSTER3 - Cluster 3, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_B10_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_B10_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_G10_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_G10_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_R10_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_R10_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix0_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_B10_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_B10_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_G10_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_G10_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_R10_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_R10_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix1_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_B10_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_B10_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_G10_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_G10_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_R10_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_R10_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix2_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_B10_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_B10_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_G10_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_G10_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_R10_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_R10_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR0_CLUSTER3_diseng_sig2_Pix3_R10_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR1_CLUSTER3 - Cluster 3, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_B32_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_B32_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_G32_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_G32_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_R32_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_R32_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix0_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_B32_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_B32_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_G32_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_G32_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_R32_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_R32_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix1_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_B32_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_B32_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_G32_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_G32_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_R32_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_R32_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix2_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_B32_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_B32_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_G32_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_G32_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_R32_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_R32_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR1_CLUSTER3_diseng_sig2_Pix3_R32_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR2_CLUSTER3 - Cluster 3, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_B54_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_B54_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_G54_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_G54_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_R54_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_R54_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix0_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_B54_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_B54_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_G54_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_G54_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_R54_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_R54_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix1_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_B54_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_B54_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_G54_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_G54_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_R54_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_R54_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix2_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_B54_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_B54_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_G54_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_G54_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_R54_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_R54_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR2_CLUSTER3_diseng_sig2_Pix3_R54_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_VECTOR3_CLUSTER3 - Cluster 3, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_B76_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_B76_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_G76_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_G76_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_R76_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_R76_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix0_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_B76_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_B76_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_G76_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_G76_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_R76_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_R76_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix1_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_B76_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_B76_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_G76_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_G76_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_R76_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_R76_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix2_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_B76_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_B76_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_G76_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_G76_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_R76_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_R76_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_VECTOR3_CLUSTER3_diseng_sig2_Pix3_R76_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS0_WIN0 - Pixel Counter Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN0_diseng_sig2_Px_Cnt_S0_Win0_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN0_diseng_sig2_Px_Cnt_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN0_diseng_sig2_Px_Cnt_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN0_diseng_sig2_Px_Cnt_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN0_diseng_sig2_Px_Cnt_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS0_WIN0 - Pixel Max Values Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Bl_Max_S0_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Bl_Max_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Bl_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Bl_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Bl_Max_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Gn_Max_S0_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Gn_Max_S0_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Gn_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Gn_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Gn_Max_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Rd_Max_S0_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Rd_Max_S0_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Rd_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Rd_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN0_diseng_sig2_Rd_Max_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS0_WIN0 - Pixel Min Values Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Bl_Min_S0_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Bl_Min_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Bl_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Bl_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Bl_Min_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Gn_Min_S0_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Gn_Min_S0_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Gn_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Gn_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Gn_Min_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Rd_Min_S0_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Rd_Min_S0_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Rd_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Rd_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN0_diseng_sig2_Rd_Min_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS0_WIN0 - Red Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN0_diseng_sig2_Rd_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN0_diseng_sig2_Rd_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN0_diseng_sig2_Rd_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN0_diseng_sig2_Rd_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN0_diseng_sig2_Rd_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS0_WIN0 - Green Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN0_diseng_sig2_Gn_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN0_diseng_sig2_Gn_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN0_diseng_sig2_Gn_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN0_diseng_sig2_Gn_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN0_diseng_sig2_Gn_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS0_WIN0 - Blue Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN0_diseng_sig2_Bl_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN0_diseng_sig2_Bl_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN0_diseng_sig2_Bl_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN0_diseng_sig2_Bl_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN0_diseng_sig2_Bl_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_LUMSUM_STATS0_WIN0 - Luminance Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN0_diseng_sig2_Lm_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN0_diseng_sig2_Lm_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN0_diseng_sig2_Lm_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN0_diseng_sig2_Lm_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN0_diseng_sig2_Lm_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS1_WIN0 - Pixel Counter Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN0_diseng_sig2_Px_Cnt_S1_Win0_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN0_diseng_sig2_Px_Cnt_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN0_diseng_sig2_Px_Cnt_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN0_diseng_sig2_Px_Cnt_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN0_diseng_sig2_Px_Cnt_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS1_WIN0 - Pixel Max Values Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Bl_Max_S1_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Bl_Max_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Bl_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Bl_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Bl_Max_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Gn_Max_S1_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Gn_Max_S1_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Gn_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Gn_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Gn_Max_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Rd_Max_S1_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Rd_Max_S1_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Rd_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Rd_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN0_diseng_sig2_Rd_Max_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS1_WIN0 - Pixel Min Values Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Bl_Min_S1_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Bl_Min_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Bl_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Bl_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Bl_Min_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Gn_Min_S1_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Gn_Min_S1_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Gn_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Gn_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Gn_Min_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Rd_Min_S1_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Rd_Min_S1_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Rd_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Rd_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN0_diseng_sig2_Rd_Min_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS1_WIN0 - Red Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN0_diseng_sig2_Rd_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN0_diseng_sig2_Rd_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN0_diseng_sig2_Rd_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN0_diseng_sig2_Rd_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN0_diseng_sig2_Rd_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS1_WIN0 - Green Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN0_diseng_sig2_Gn_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN0_diseng_sig2_Gn_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN0_diseng_sig2_Gn_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN0_diseng_sig2_Gn_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN0_diseng_sig2_Gn_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS1_WIN0 - Blue Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN0_diseng_sig2_Bl_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN0_diseng_sig2_Bl_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN0_diseng_sig2_Bl_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN0_diseng_sig2_Bl_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN0_diseng_sig2_Bl_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS0_WIN1 - Pixel Counter Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN1_diseng_sig2_Px_Cnt_S0_Win1_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN1_diseng_sig2_Px_Cnt_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN1_diseng_sig2_Px_Cnt_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN1_diseng_sig2_Px_Cnt_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN1_diseng_sig2_Px_Cnt_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS0_WIN1 - Pixel Max Values Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Bl_Max_S0_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Bl_Max_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Bl_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Bl_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Bl_Max_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Gn_Max_S0_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Gn_Max_S0_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Gn_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Gn_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Gn_Max_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Rd_Max_S0_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Rd_Max_S0_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Rd_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Rd_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN1_diseng_sig2_Rd_Max_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS0_WIN1 - Pixel Min Values Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Bl_Min_S0_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Bl_Min_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Bl_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Bl_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Bl_Min_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Gn_Min_S0_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Gn_Min_S0_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Gn_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Gn_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Gn_Min_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Rd_Min_S0_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Rd_Min_S0_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Rd_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Rd_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN1_diseng_sig2_Rd_Min_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS0_WIN1 - Red Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN1_diseng_sig2_Rd_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN1_diseng_sig2_Rd_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN1_diseng_sig2_Rd_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN1_diseng_sig2_Rd_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN1_diseng_sig2_Rd_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS0_WIN1 - Green Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN1_diseng_sig2_Gn_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN1_diseng_sig2_Gn_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN1_diseng_sig2_Gn_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN1_diseng_sig2_Gn_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN1_diseng_sig2_Gn_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS0_WIN1 - Blue Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN1_diseng_sig2_Bl_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN1_diseng_sig2_Bl_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN1_diseng_sig2_Bl_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN1_diseng_sig2_Bl_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN1_diseng_sig2_Bl_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_LUMSUM_STATS0_WIN1 - Luminance Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN1_diseng_sig2_Lm_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN1_diseng_sig2_Lm_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN1_diseng_sig2_Lm_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN1_diseng_sig2_Lm_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN1_diseng_sig2_Lm_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS1_WIN1 - Pixel Counter Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN1_diseng_sig2_Px_Cnt_S1_Win1_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN1_diseng_sig2_Px_Cnt_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN1_diseng_sig2_Px_Cnt_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN1_diseng_sig2_Px_Cnt_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN1_diseng_sig2_Px_Cnt_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS1_WIN1 - Pixel Max Values Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Bl_Max_S1_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Bl_Max_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Bl_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Bl_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Bl_Max_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Gn_Max_S1_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Gn_Max_S1_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Gn_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Gn_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Gn_Max_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Rd_Max_S1_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Rd_Max_S1_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Rd_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Rd_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN1_diseng_sig2_Rd_Max_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS1_WIN1 - Pixel Min Values Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Bl_Min_S1_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Bl_Min_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Bl_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Bl_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Bl_Min_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Gn_Min_S1_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Gn_Min_S1_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Gn_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Gn_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Gn_Min_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Rd_Min_S1_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Rd_Min_S1_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Rd_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Rd_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN1_diseng_sig2_Rd_Min_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS1_WIN1 - Red Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN1_diseng_sig2_Rd_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN1_diseng_sig2_Rd_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN1_diseng_sig2_Rd_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN1_diseng_sig2_Rd_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN1_diseng_sig2_Rd_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS1_WIN1 - Green Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN1_diseng_sig2_Gn_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN1_diseng_sig2_Gn_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN1_diseng_sig2_Gn_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN1_diseng_sig2_Gn_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN1_diseng_sig2_Gn_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS1_WIN1 - Blue Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN1_diseng_sig2_Bl_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN1_diseng_sig2_Bl_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN1_diseng_sig2_Bl_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN1_diseng_sig2_Bl_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN1_diseng_sig2_Bl_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS0_WIN2 - Pixel Counter Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN2_diseng_sig2_Px_Cnt_S0_Win2_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN2_diseng_sig2_Px_Cnt_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN2_diseng_sig2_Px_Cnt_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN2_diseng_sig2_Px_Cnt_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN2_diseng_sig2_Px_Cnt_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS0_WIN2 - Pixel Max Values Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Bl_Max_S0_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Bl_Max_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Bl_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Bl_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Bl_Max_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Gn_Max_S0_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Gn_Max_S0_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Gn_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Gn_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Gn_Max_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Rd_Max_S0_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Rd_Max_S0_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Rd_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Rd_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN2_diseng_sig2_Rd_Max_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS0_WIN2 - Pixel Min Values Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Bl_Min_S0_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Bl_Min_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Bl_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Bl_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Bl_Min_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Gn_Min_S0_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Gn_Min_S0_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Gn_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Gn_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Gn_Min_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Rd_Min_S0_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Rd_Min_S0_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Rd_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Rd_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN2_diseng_sig2_Rd_Min_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS0_WIN2 - Red Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN2_diseng_sig2_Rd_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN2_diseng_sig2_Rd_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN2_diseng_sig2_Rd_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN2_diseng_sig2_Rd_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN2_diseng_sig2_Rd_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS0_WIN2 - Green Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN2_diseng_sig2_Gn_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN2_diseng_sig2_Gn_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN2_diseng_sig2_Gn_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN2_diseng_sig2_Gn_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN2_diseng_sig2_Gn_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS0_WIN2 - Blue Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN2_diseng_sig2_Bl_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN2_diseng_sig2_Bl_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN2_diseng_sig2_Bl_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN2_diseng_sig2_Bl_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN2_diseng_sig2_Bl_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_LUMSUM_STATS0_WIN2 - Luminance Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN2_diseng_sig2_Lm_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN2_diseng_sig2_Lm_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN2_diseng_sig2_Lm_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN2_diseng_sig2_Lm_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN2_diseng_sig2_Lm_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS1_WIN2 - Pixel Counter Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN2_diseng_sig2_Px_Cnt_S1_Win2_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN2_diseng_sig2_Px_Cnt_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN2_diseng_sig2_Px_Cnt_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN2_diseng_sig2_Px_Cnt_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN2_diseng_sig2_Px_Cnt_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS1_WIN2 - Pixel Max Values Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Bl_Max_S1_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Bl_Max_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Bl_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Bl_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Bl_Max_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Gn_Max_S1_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Gn_Max_S1_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Gn_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Gn_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Gn_Max_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Rd_Max_S1_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Rd_Max_S1_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Rd_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Rd_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN2_diseng_sig2_Rd_Max_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS1_WIN2 - Pixel Min Values Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Bl_Min_S1_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Bl_Min_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Bl_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Bl_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Bl_Min_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Gn_Min_S1_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Gn_Min_S1_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Gn_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Gn_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Gn_Min_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Rd_Min_S1_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Rd_Min_S1_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Rd_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Rd_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN2_diseng_sig2_Rd_Min_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS1_WIN2 - Red Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN2_diseng_sig2_Rd_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN2_diseng_sig2_Rd_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN2_diseng_sig2_Rd_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN2_diseng_sig2_Rd_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN2_diseng_sig2_Rd_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS1_WIN2 - Green Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN2_diseng_sig2_Gn_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN2_diseng_sig2_Gn_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN2_diseng_sig2_Gn_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN2_diseng_sig2_Gn_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN2_diseng_sig2_Gn_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS1_WIN2 - Blue Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN2_diseng_sig2_Bl_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN2_diseng_sig2_Bl_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN2_diseng_sig2_Bl_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN2_diseng_sig2_Bl_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN2_diseng_sig2_Bl_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS0_WIN3 - Pixel Counter Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN3_diseng_sig2_Px_Cnt_S0_Win3_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN3_diseng_sig2_Px_Cnt_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN3_diseng_sig2_Px_Cnt_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN3_diseng_sig2_Px_Cnt_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS0_WIN3_diseng_sig2_Px_Cnt_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS0_WIN3 - Pixel Max Values Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Bl_Max_S0_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Bl_Max_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Bl_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Bl_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Bl_Max_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Gn_Max_S0_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Gn_Max_S0_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Gn_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Gn_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Gn_Max_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Rd_Max_S0_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Rd_Max_S0_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Rd_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Rd_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS0_WIN3_diseng_sig2_Rd_Max_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS0_WIN3 - Pixel Min Values Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Bl_Min_S0_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Bl_Min_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Bl_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Bl_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Bl_Min_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Gn_Min_S0_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Gn_Min_S0_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Gn_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Gn_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Gn_Min_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Rd_Min_S0_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Rd_Min_S0_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Rd_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Rd_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS0_WIN3_diseng_sig2_Rd_Min_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS0_WIN3 - Red Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN3_diseng_sig2_Rd_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN3_diseng_sig2_Rd_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN3_diseng_sig2_Rd_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN3_diseng_sig2_Rd_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS0_WIN3_diseng_sig2_Rd_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS0_WIN3 - Green Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN3_diseng_sig2_Gn_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN3_diseng_sig2_Gn_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN3_diseng_sig2_Gn_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN3_diseng_sig2_Gn_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS0_WIN3_diseng_sig2_Gn_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS0_WIN3 - Blue Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN3_diseng_sig2_Bl_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN3_diseng_sig2_Bl_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN3_diseng_sig2_Bl_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN3_diseng_sig2_Bl_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS0_WIN3_diseng_sig2_Bl_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_LUMSUM_STATS0_WIN3 - Luminance Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN3_diseng_sig2_Lm_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN3_diseng_sig2_Lm_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN3_diseng_sig2_Lm_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN3_diseng_sig2_Lm_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_LUMSUM_STATS0_WIN3_diseng_sig2_Lm_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXCNT_STATS1_WIN3 - Pixel Counter Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN3_diseng_sig2_Px_Cnt_S1_Win3_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN3_diseng_sig2_Px_Cnt_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN3_diseng_sig2_Px_Cnt_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN3_diseng_sig2_Px_Cnt_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXCNT_STATS1_WIN3_diseng_sig2_Px_Cnt_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMAX_STATS1_WIN3 - Pixel Max Values Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Bl_Max_S1_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Bl_Max_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Bl_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Bl_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Bl_Max_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Gn_Max_S1_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Gn_Max_S1_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Gn_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Gn_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Gn_Max_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Rd_Max_S1_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Rd_Max_S1_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Rd_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Rd_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMAX_STATS1_WIN3_diseng_sig2_Rd_Max_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_PIXMIN_STATS1_WIN3 - Pixel Min Values Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Bl_Min_S1_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Bl_Min_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Bl_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Bl_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Bl_Min_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Gn_Min_S1_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Gn_Min_S1_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Gn_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Gn_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Gn_Min_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Rd_Min_S1_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Rd_Min_S1_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Rd_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Rd_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_PIXMIN_STATS1_WIN3_diseng_sig2_Rd_Min_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_REDSUM_STATS1_WIN3 - Red Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN3_diseng_sig2_Rd_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN3_diseng_sig2_Rd_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN3_diseng_sig2_Rd_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN3_diseng_sig2_Rd_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_REDSUM_STATS1_WIN3_diseng_sig2_Rd_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_GREENSUM_STATS1_WIN3 - Green Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN3_diseng_sig2_Gn_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN3_diseng_sig2_Gn_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN3_diseng_sig2_Gn_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN3_diseng_sig2_Gn_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_GREENSUM_STATS1_WIN3_diseng_sig2_Gn_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2_BLUESUM_STATS1_WIN3 - Blue Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN3_diseng_sig2_Bl_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN3_diseng_sig2_Bl_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN3_diseng_sig2_Bl_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN3_diseng_sig2_Bl_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2_BLUESUM_STATS1_WIN3_diseng_sig2_Bl_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG2CFG_LOCKUNLOCK0 - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKUNLOCK0_diseng_sig2cfg_LockUnlock0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKUNLOCK0_diseng_sig2cfg_LockUnlock0_SHIFT (0U) /*! diseng_sig2cfg_LockUnlock0 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKUNLOCK0_diseng_sig2cfg_LockUnlock0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKUNLOCK0_diseng_sig2cfg_LockUnlock0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKUNLOCK0_diseng_sig2cfg_LockUnlock0_MASK) /*! @} */ /*! @name DISENG_SIG2CFG_LOCKSTATUS0 - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_LockStatus0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_LockStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_LockStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_LockStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_LockStatus0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_PrivilegeStatus0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_PrivilegeStatus0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_PrivilegeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_PrivilegeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_PrivilegeStatus0_MASK) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_FreezeStatus0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_FreezeStatus0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_FreezeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_FreezeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2CFG_LOCKSTATUS0_diseng_sig2cfg_FreezeStatus0_MASK) /*! @} */ /*! @name DISENG_SIG2CFG_SRCSELECT - Tap selection for sig2. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG2CFG_SRCSELECT_diseng_sig2cfg_sig2_select_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG2CFG_SRCSELECT_diseng_sig2cfg_sig2_select_SHIFT (0U) /*! diseng_sig2cfg_sig2_select * 0b00..Source is FrameGen#0 output. * 0b01..Source is Matrix#0 output. * 0b10..Source is LuT3D#0 output. * 0b11..Source is Dither#0 output. */ #define DISPLAY_SEERIS_DISENG_SIG2CFG_SRCSELECT_diseng_sig2cfg_sig2_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG2CFG_SRCSELECT_diseng_sig2cfg_sig2_select_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG2CFG_SRCSELECT_diseng_sig2cfg_sig2_select_MASK) /*! @} */ /*! @name DISENG_MATRIX0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKUNLOCK_diseng_matrix0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKUNLOCK_diseng_matrix0_LockUnlock_SHIFT (0U) /*! diseng_matrix0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKUNLOCK_diseng_matrix0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_LOCKUNLOCK_diseng_matrix0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_LOCKUNLOCK_diseng_matrix0_LockUnlock_MASK) /*! @} */ /*! @name DISENG_MATRIX0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_LOCKSTATUS_diseng_matrix0_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_MATRIX0_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_STATICCONTROL_diseng_matrix0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_MATRIX0_STATICCONTROL_diseng_matrix0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_STATICCONTROL_diseng_matrix0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_STATICCONTROL_diseng_matrix0_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_STATICCONTROL_diseng_matrix0_ShdEn_MASK) /*! @} */ /*! @name DISENG_MATRIX0_CONTROL - Color Matrix control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_MODE_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_MODE_SHIFT (0U) /*! diseng_matrix0_MODE * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_MODE_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_MODE_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaMask_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaMask_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaMask_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaMask_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaInvert_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaInvert_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaInvert_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_CONTROL_diseng_matrix0_AlphaInvert_MASK) /*! @} */ /*! @name DISENG_MATRIX0_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A11_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A11_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A11(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A11_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A11_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A12_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A12_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A12(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A12_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_RED0_diseng_matrix0_A12_MASK) /*! @} */ /*! @name DISENG_MATRIX0_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_RED1_diseng_matrix0_A13_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_RED1_diseng_matrix0_A13_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_RED1_diseng_matrix0_A13(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_RED1_diseng_matrix0_A13_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_RED1_diseng_matrix0_A13_MASK) /*! @} */ /*! @name DISENG_MATRIX0_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A21_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A21_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A21(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A21_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A21_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A22_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A22_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A22(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A22_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_GREEN0_diseng_matrix0_A22_MASK) /*! @} */ /*! @name DISENG_MATRIX0_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN1_diseng_matrix0_A23_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN1_diseng_matrix0_A23_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_GREEN1_diseng_matrix0_A23(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_GREEN1_diseng_matrix0_A23_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_GREEN1_diseng_matrix0_A23_MASK) /*! @} */ /*! @name DISENG_MATRIX0_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A31_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A31_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A31(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A31_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A31_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A32_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A32_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A32(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A32_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_BLUE0_diseng_matrix0_A32_MASK) /*! @} */ /*! @name DISENG_MATRIX0_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE1_diseng_matrix0_A33_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE1_diseng_matrix0_A33_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_BLUE1_diseng_matrix0_A33(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_BLUE1_diseng_matrix0_A33_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_BLUE1_diseng_matrix0_A33_MASK) /*! @} */ /*! @name DISENG_MATRIX0_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C1_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C1_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C1_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C2_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C2_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR0_diseng_matrix0_C2_MASK) /*! @} */ /*! @name DISENG_MATRIX0_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR1_diseng_matrix0_C3_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR1_diseng_matrix0_C3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR1_diseng_matrix0_C3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR1_diseng_matrix0_C3_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_OFFSETVECTOR1_diseng_matrix0_C3_MASK) /*! @} */ /*! @name DISENG_MATRIX0_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX0_LASTCONTROLWORD_diseng_matrix0_L_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_MATRIX0_LASTCONTROLWORD_diseng_matrix0_L_VAL_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX0_LASTCONTROLWORD_diseng_matrix0_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX0_LASTCONTROLWORD_diseng_matrix0_L_VAL_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX0_LASTCONTROLWORD_diseng_matrix0_L_VAL_MASK) /*! @} */ /*! @name DISENG_LUT3D0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKUNLOCK_diseng_lut3d0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKUNLOCK_diseng_lut3d0_LockUnlock_SHIFT (0U) /*! diseng_lut3d0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKUNLOCK_diseng_lut3d0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_LOCKUNLOCK_diseng_lut3d0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_LOCKUNLOCK_diseng_lut3d0_LockUnlock_MASK) /*! @} */ /*! @name DISENG_LUT3D0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_LOCKSTATUS_diseng_lut3d0_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_LUT3D0_STATICCONTROL - lut3d static control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D0_STATICCONTROL_diseng_lut3d0_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_LUT3D0_STATICCONTROL_diseng_lut3d0_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_LUT3D0_STATICCONTROL_diseng_lut3d0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_STATICCONTROL_diseng_lut3d0_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_STATICCONTROL_diseng_lut3d0_ShdEn_MASK) /*! @} */ /*! @name DISENG_LUT3D0_CONTROL - lut3d control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_MODE_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_MODE_SHIFT (0U) /*! diseng_lut3d0_MODE * 0b000..Module in neutral mode, RGBA input data is bypassed to the output unchanged. * 0b001..LUT operates in 3D mode. * 0b010..Each RGB input is used as individual index into the respective LUT. Alpha channel is bypassed to output. * 0b011..Red input is used as common index for any RGB LUT. The alpha channel is bypassed to output. * 0b100..Red input is used as common index for any RGB LUT. The result is remapped and upconverted to RGBA. */ #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_MODE_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_MODE_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_DITH_EN_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_DITH_EN_SHIFT (3U) /*! diseng_lut3d0_DITH_EN * 0b0..Output is 10bit. If LUT_DATA_WIDTH == MODE_12BIT then 2 LSB are truncated. * 0b1..If LUT_DATA_WIDTH == MODE_12BIT then 12bit value is dithered to 10bit. if LUT_DATA_WIDTH == MODE_10BIT then 10bit value is dithered to 8bit. */ #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_DITH_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_DITH_EN_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_DITH_EN_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaMask_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaMask_SHIFT (5U) /*! diseng_lut3d0_AlphaMask * 0b0..Alpha mask mode disabled * 0b1..Alpha mask mode enabled */ #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaMask_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaMask_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaInvert_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaInvert_SHIFT (6U) /*! diseng_lut3d0_AlphaInvert * 0b0..Disable computation for alpha smaller than 128 * 0b1..Disable computation for alpha greater than or equal to 128 */ #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaInvert_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_AlphaInvert_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_IDX_BITS_MASK (0xF00U) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_IDX_BITS_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_IDX_BITS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_IDX_BITS_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_CONTROL_diseng_lut3d0_IDX_BITS_MASK) /*! @} */ /*! @name DISENG_LUT3D0_LUT - Look Up Table */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D0_LUT_diseng_lut3d0_DATA_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_LUT3D0_LUT_diseng_lut3d0_DATA_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_LUT3D0_LUT_diseng_lut3d0_DATA(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D0_LUT_diseng_lut3d0_DATA_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D0_LUT_diseng_lut3d0_DATA_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_DISENG_LUT3D0_LUT */ #define DISPLAY_SEERIS_DISENG_LUT3D0_LUT_COUNT (2048U) /*! @name DISENG_DITHER0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKUNLOCK_diseng_dither0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKUNLOCK_diseng_dither0_LockUnlock_SHIFT (0U) /*! diseng_dither0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKUNLOCK_diseng_dither0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_LOCKUNLOCK_diseng_dither0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_LOCKUNLOCK_diseng_dither0_LockUnlock_MASK) /*! @} */ /*! @name DISENG_DITHER0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_LOCKSTATUS_diseng_dither0_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_DITHER0_CONTROL - Dither Unit common control. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0_CONTROL_diseng_dither0_mode_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_DITHER0_CONTROL_diseng_dither0_mode_SHIFT (0U) /*! diseng_dither0_mode * 0b00..Neutral mode. Pixels by-pass the Dither Unit, all other settings are ignored. * 0b01..Dither Unit is active (uses 10bit input). * 0b10..Dither Unit is active (uses 12bit input). */ #define DISPLAY_SEERIS_DISENG_DITHER0_CONTROL_diseng_dither0_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_CONTROL_diseng_dither0_mode_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_CONTROL_diseng_dither0_mode_MASK) /*! @} */ /*! @name DISENG_DITHER0_DITHERCONTROL10BITS - Dither Unit processing control. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_blue_range_select_10bit_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_blue_range_select_10bit_SHIFT (0U) /*! diseng_dither0_blue_range_select_10bit * 0b010..Reduces blue component width from 10 bit to 8bit. * 0b011..Reduces blue component width from 10 bit to 7bit. * 0b100..Reduces blue component width from 10 bit to 6bit. * 0b101..Reduces blue component width from 10 bit to 5bit. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_blue_range_select_10bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_blue_range_select_10bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_blue_range_select_10bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_green_range_select_10bit_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_green_range_select_10bit_SHIFT (4U) /*! diseng_dither0_green_range_select_10bit * 0b010..Reduces green component width from 10 bit to 8bit. * 0b011..Reduces green component width from 10 bit to 7bit. * 0b100..Reduces green component width from 10 bit to 6bit. * 0b101..Reduces green component width from 10 bit to 5bit. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_green_range_select_10bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_green_range_select_10bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_green_range_select_10bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_red_range_select_10bit_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_red_range_select_10bit_SHIFT (8U) /*! diseng_dither0_red_range_select_10bit * 0b010..Reduces red component width from 10 bit to 8bit. * 0b011..Reduces red component width from 10 bit to 7bit. * 0b100..Reduces red component width from 10 bit to 6bit. * 0b101..Reduces red component width from 10 bit to 5bit. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_red_range_select_10bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_red_range_select_10bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL10BITS_diseng_dither0_red_range_select_10bit_MASK) /*! @} */ /*! @name DISENG_DITHER0_DITHERCONTROL12BITS - Dither Unit processing control. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_blue_range_select_12bit_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_blue_range_select_12bit_SHIFT (0U) /*! diseng_dither0_blue_range_select_12bit * 0b010..Reduces blue component width from 12 bit to 10bit. * 0b011..Reduces blue component width from 12 bit to 9bit. * 0b100..Reduces blue component width from 12 bit to 8bit. * 0b110..Reduces blue component width from 12 bit to 6bit. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_blue_range_select_12bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_blue_range_select_12bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_blue_range_select_12bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_green_range_select_12bit_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_green_range_select_12bit_SHIFT (4U) /*! diseng_dither0_green_range_select_12bit * 0b010..Reduces green component width from 12 bit to 10bit. * 0b011..Reduces green component width from 12 bit to 9bit. * 0b100..Reduces green component width from 12 bit to 8bit. * 0b110..Reduces green component width from 12 bit to 6bit. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_green_range_select_12bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_green_range_select_12bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_green_range_select_12bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_red_range_select_12bit_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_red_range_select_12bit_SHIFT (8U) /*! diseng_dither0_red_range_select_12bit * 0b010..Reduces red component width from 12 bit to 10bit. * 0b011..Reduces red component width from 12 bit to 9bit. * 0b100..Reduces red component width from 12 bit to 8bit. * 0b110..Reduces red component width from 12 bit to 6bit. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_red_range_select_12bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_red_range_select_12bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_red_range_select_12bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_offset_select_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_offset_select_SHIFT (16U) /*! diseng_dither0_offset_select * 0b0..Offset is a bayer matrix value, which is selected according to pixel frame position. * 0b1..Offset is the sum from a bayer matrix value, which is selected according to pixel frame position, and a * value from a regular sequence, which changes each frame. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_offset_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_offset_select_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_offset_select_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_algo_select_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_algo_select_SHIFT (20U) /*! diseng_dither0_algo_select * 0b01..Best possible resolution for most dark colors. Adds a diminutive offset to overall image brightness. * 0b10..Preserves overall image brightness. Cannot resolve most dark and most bright colors. All codes in-between are distributed perfectly smooth. * 0b11..Preserves overall image brightness. Best possible distribution of color codes over complete range. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_algo_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_algo_select_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_algo_select_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_alpha_mode_MASK (0x3000000U) #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_alpha_mode_SHIFT (24U) /*! diseng_dither0_alpha_mode * 0b00..The alpha bit is not considered. * 0b01..Red, green and blue components are only dithered, if the alpha bit is 1. * 0b10..Red, green and blue components are only dithered, if the alpha bit is 0. */ #define DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_alpha_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_alpha_mode_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0_DITHERCONTROL12BITS_diseng_dither0_alpha_mode_MASK) /*! @} */ /*! @name DISENG_DITHER0CFG_LOCKUNLOCK0 - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKUNLOCK0_diseng_dither0cfg_LockUnlock0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKUNLOCK0_diseng_dither0cfg_LockUnlock0_SHIFT (0U) /*! diseng_dither0cfg_LockUnlock0 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKUNLOCK0_diseng_dither0cfg_LockUnlock0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKUNLOCK0_diseng_dither0cfg_LockUnlock0_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKUNLOCK0_diseng_dither0cfg_LockUnlock0_MASK) /*! @} */ /*! @name DISENG_DITHER0CFG_LOCKSTATUS0 - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_LockStatus0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_LockStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_LockStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_LockStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_LockStatus0_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_PrivilegeStatus0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_PrivilegeStatus0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_PrivilegeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_PrivilegeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_PrivilegeStatus0_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_FreezeStatus0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_FreezeStatus0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_FreezeStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_FreezeStatus0_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0CFG_LOCKSTATUS0_diseng_dither0cfg_FreezeStatus0_MASK) /*! @} */ /*! @name DISENG_DITHER0CFG_POLARITYCTRL0 - Polarity control for display stream #0. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolHs0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolHs0_SHIFT (0U) /*! diseng_dither0cfg_PolHs0 * 0b0..Low active * 0b1..High active */ #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolHs0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolHs0_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolHs0_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolVs0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolVs0_SHIFT (1U) /*! diseng_dither0cfg_PolVs0 * 0b0..Low active * 0b1..High active */ #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolVs0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolVs0_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolVs0_MASK) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolEn0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolEn0_SHIFT (2U) /*! diseng_dither0cfg_PolEn0 * 0b0..Low active * 0b1..High active */ #define DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolEn0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolEn0_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER0CFG_POLARITYCTRL0_diseng_dither0cfg_PolEn0_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUNLOCK_diseng_domainblend1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUNLOCK_diseng_domainblend1_LockUnlock_SHIFT (0U) /*! diseng_domainblend1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUNLOCK_diseng_domainblend1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUNLOCK_diseng_domainblend1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUNLOCK_diseng_domainblend1_LockUnlock_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKSTATUS_diseng_domainblend1_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_STATICCONTROL - Static control settings. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdEn_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdLdSel_MASK (0xEU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdLdSel_SHIFT (1U) /*! diseng_domainblend1_ShdLdSel * 0b000..Shadow loading not allowed * 0b001..Load shadows with shadow load token on primary input. * 0b010..Load shadows with shadow load token on secondary input. * 0b011..Load shadows with shadow load token on primary or secondary input. * 0b100..Load shadows with shadow load token from ControlTrigger register. * 0b101..Load shadows with shadow load token from ControlTrigger register or primary input. * 0b110..Load shadows with shadow load token from ControlTrigger register or secondary input. * 0b111..Load shadows with shadow load token from ControlTrigger register or primary or secondary input. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdLdSel_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdTokSel_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdTokSel_SHIFT (4U) /*! diseng_domainblend1_ShdTokSel * 0b000..Shadow load forwarding not allowed * 0b001..When a token was received on the primary input. * 0b010..When a token was received on the secondary input. * 0b011..When a token was received on the primary or secondary input. * 0b100..When a token was received from ControlTrigger register. * 0b101..When a token was received from ControlTrigger register or primary input. * 0b110..When a token was received from ControlTrigger register or secondary input. * 0b111..When a token was received from ControlTrigger register or primary or secondary input. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdTokSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdTokSel_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_STATICCONTROL_diseng_domainblend1_ShdTokSel_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_CONTROLTRIGGER - Shadow load and sequence complete triggers. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_ShdTokGen_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_Trigger_Sequence_Complete_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_Trigger_Sequence_Complete_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_Trigger_Sequence_Complete(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_Trigger_Sequence_Complete_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_CONTROLTRIGGER_diseng_domainblend1_Trigger_Sequence_Complete_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_MODECONTROL - Operation mode of the domainblend */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_MODECONTROL_diseng_domainblend1_MODE_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_MODECONTROL_diseng_domainblend1_MODE_SHIFT (0U) /*! diseng_domainblend1_MODE * 0b00..Output is same as primary input. * 0b01..Output is same as secondary input. * 0b10..Module is in blending mode. * 0b11..Module is in side by side mode. The primary and secondary inputs are displayed side by side. */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_MODECONTROL_diseng_domainblend1_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_MODECONTROL_diseng_domainblend1_MODE_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_MODECONTROL_diseng_domainblend1_MODE_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_ALPHACONTROL - Alpha mask settings. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskEnable_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskEnable_SHIFT (0U) /*! diseng_domainblend1_AlphaMaskEnable * 0b0..AlphaMask feature disabled * 0b1..AlphaMask feature enabled */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskEnable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskEnable_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskEnable_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskMode_MASK (0xEU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskMode_SHIFT (1U) /*! diseng_domainblend1_AlphaMaskMode * 0b000..Areas with primary input alpha > 128 will be mapped to 255 and the rest will have an alpha value of 0 * 0b001..The area of the secondary input will get an alpha value of 255 and the rest will be 0 * 0b010..Behaves as if the output of modes PRIM and SEC would be ORed together * 0b011..Behaves as if the output of modes PRIM and SEC would be ANDed together * 0b100..Behaves as if the output of mode PRIM would be inverted * 0b101..Behaves as if the output of mode SEC would be inverted * 0b110..Behaves as if the output of modes PRIM and SEC_INV would be ORed together * 0b111..Behaves as if the output of modes PRIM and SEC_INV would be ANDed together */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskMode_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ALPHACONTROL_diseng_domainblend1_AlphaMaskMode_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_BLENDCONTROL - Options for blend operations */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_C_BLD_FUNC_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_C_BLD_FUNC_SHIFT (0U) /*! diseng_domainblend1_PRIM_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_C_BLD_FUNC_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_C_BLD_FUNC_SHIFT (4U) /*! diseng_domainblend1_SEC_C_BLD_FUNC * 0b000..Cout = Cin * 0 * 0b001..Cout = Cin * 1 * 0b010..Cout = Cin * ALPHA_prim * 0b011..Cout = Cin * (1 - ALPHA_prim) * 0b100..Cout = Cin * ALPHA_sec * 0b101..Cout = Cin * (1 - ALPHA_sec) * 0b110..Cout = Cin * ALPHA_const * 0b111..Cout = Cin * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_C_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_C_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_C_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_A_BLD_FUNC_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_A_BLD_FUNC_SHIFT (8U) /*! diseng_domainblend1_PRIM_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_PRIM_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_A_BLD_FUNC_MASK (0x7000U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_A_BLD_FUNC_SHIFT (12U) /*! diseng_domainblend1_SEC_A_BLD_FUNC * 0b000..Aout = Ain * 0 * 0b001..Aout = Ain * 1 * 0b010..Aout = Ain * ALPHA_prim * 0b011..Aout = Ain * (1 - ALPHA_prim) * 0b100..Aout = Ain * ALPHA_sec * 0b101..Aout = Ain * (1 - ALPHA_sec) * 0b110..Aout = Ain * ALPHA_const * 0b111..Aout = Ain * (1 - ALPHA_const) */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_A_BLD_FUNC(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_A_BLD_FUNC_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_SEC_A_BLD_FUNC_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_BlendAlpha_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_BlendAlpha_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_BlendAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_BlendAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_BLENDCONTROL_diseng_domainblend1_BlendAlpha_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK - The status of primary and secondary sources waiting for pixels. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_PrimWait_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_PrimWait_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_PrimWait(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_PrimWait_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_PrimWait_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_SecWait_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_SecWait_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_SecWait(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_SecWait_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_TIMEOUT_FEEDBACK_diseng_domainblend1_SecWait_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_LOCKUP_CLEAR - The register can be used to internally reset domainblend if it gets stuck by pending pixels from one source. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUP_CLEAR_diseng_domainblend1_LockupClear_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUP_CLEAR_diseng_domainblend1_LockupClear_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUP_CLEAR_diseng_domainblend1_LockupClear(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUP_CLEAR_diseng_domainblend1_LockupClear_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_LOCKUP_CLEAR_diseng_domainblend1_LockupClear_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_DELAY_COUNTER_EN - The register enables the delay and error counters that report on the delay on prim and sec sources. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_EN_diseng_domainblend1_DelayCountEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_EN_diseng_domainblend1_DelayCountEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_EN_diseng_domainblend1_DelayCountEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_EN_diseng_domainblend1_DelayCountEn_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_EN_diseng_domainblend1_DelayCountEn_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_DELAY_COUNTER_PRIM - The number of inavtive clock cycles during which the domainblend is waiting for pixels from primary source. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_PRIM_diseng_domainblend1_DelayCountPrim_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_PRIM_diseng_domainblend1_DelayCountPrim_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_PRIM_diseng_domainblend1_DelayCountPrim(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_PRIM_diseng_domainblend1_DelayCountPrim_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_PRIM_diseng_domainblend1_DelayCountPrim_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_DELAY_COUNTER_SEC - The number of inavtive clock cycles during which the domainblend is waiting for pixels from secondary source. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_SEC_diseng_domainblend1_DelayCountSec_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_SEC_diseng_domainblend1_DelayCountSec_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_SEC_diseng_domainblend1_DelayCountSec(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_SEC_diseng_domainblend1_DelayCountSec_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_DELAY_COUNTER_SEC_diseng_domainblend1_DelayCountSec_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_ERROR_COUNTER_PRIM - The number of inavtive clock cycles on the primary source till the synchronization loss of domainblend. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_PRIM_diseng_domainblend1_ErrCountPrim_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_PRIM_diseng_domainblend1_ErrCountPrim_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_PRIM_diseng_domainblend1_ErrCountPrim(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_PRIM_diseng_domainblend1_ErrCountPrim_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_PRIM_diseng_domainblend1_ErrCountPrim_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_ERROR_COUNTER_SEC - The number of inavtive clock cycles on the secondary source till the synchronization loss of domainblend. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_SEC_diseng_domainblend1_ErrCountSec_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_SEC_diseng_domainblend1_ErrCountSec_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_SEC_diseng_domainblend1_ErrCountSec(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_SEC_diseng_domainblend1_ErrCountSec_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_ERROR_COUNTER_SEC_diseng_domainblend1_ErrCountSec_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_SOURCE_STATUS - Source protocol error detection for primary and secondary sources */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongCommandWord_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongCommandWord_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongCommandWord(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongCommandWord_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongCommandWord_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongPixelData_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongPixelData_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongPixelData(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongPixelData_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongPixelData_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongInput_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongInput_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongInput(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongInput_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_diseng_domainblend1_WrongInput_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR - Clearing source protocol error status for both primary and secondary sources */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongCommandWord_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongCommandWord_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongCommandWord(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongCommandWord_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongCommandWord_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongPixelData_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongPixelData_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongPixelData(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongPixelData_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongPixelData_MASK) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongInput_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongInput_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongInput(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongInput_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SOURCE_STATUS_CLEAR_diseng_domainblend1_ClearWrongInput_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_PRIMCONTROLWORD - Value of last received primary control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_PRIMCONTROLWORD_diseng_domainblend1_P_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_PRIMCONTROLWORD_diseng_domainblend1_P_VAL_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_PRIMCONTROLWORD_diseng_domainblend1_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_PRIMCONTROLWORD_diseng_domainblend1_P_VAL_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_PRIMCONTROLWORD_diseng_domainblend1_P_VAL_MASK) /*! @} */ /*! @name DISENG_DOMAINBLEND1_SECCONTROLWORD - Value of last received secondary control word, for debugging */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SECCONTROLWORD_diseng_domainblend1_S_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SECCONTROLWORD_diseng_domainblend1_S_VAL_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SECCONTROLWORD_diseng_domainblend1_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SECCONTROLWORD_diseng_domainblend1_S_VAL_SHIFT)) & DISPLAY_SEERIS_DISENG_DOMAINBLEND1_SECCONTROLWORD_diseng_domainblend1_S_VAL_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKUNLOCK_diseng_framegen1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKUNLOCK_diseng_framegen1_LockUnlock_SHIFT (0U) /*! diseng_framegen1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKUNLOCK_diseng_framegen1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKUNLOCK_diseng_framegen1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKUNLOCK_diseng_framegen1_LockUnlock_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_LOCKSTATUS_diseng_framegen1_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSTCTRL - FrameGen Static Control Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_ShdEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgSyncMode_MASK (0xEU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgSyncMode_SHIFT (1U) /*! diseng_framegen1_FgSyncMode * 0b000..No side-by-side synchronization. * 0b001..Framegen is master. * 0b010..Framegen is slave. Runs in cyclic synchronization mode. * 0b011..Framegen is slave. Runs in one time synchronization mode. * 0b110..Framegen is slave. Runs in cyclic synchronization mode. Size is adapted. * 0b111..Framegen is slave. Runs in one time synchronization mode. Size is adapted. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgSyncMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgSyncMode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgSyncMode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgShdTokGenSyncMode_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgShdTokGenSyncMode_SHIFT (4U) /*! diseng_framegen1_FgShdTokGenSyncMode * 0b0..Shadow token is generated by local FgSlr.ShdTokGen field. * 0b1..Shadow token is generated by FgSlr.ShdTokGen field of second framegenerator. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgShdTokGenSyncMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgShdTokGenSyncMode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_FgShdTokGenSyncMode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_Force_Disable_MASK (0x40000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_Force_Disable_SHIFT (30U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_Force_Disable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_Force_Disable_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSTCTRL_diseng_framegen1_Force_Disable_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_HTCFG1 - FrameGen Horizontal Timing Config Register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Hact_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Hact_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Hact(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Hact_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Hact_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Htotal_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Htotal_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Htotal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Htotal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG1_diseng_framegen1_Htotal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_HTCFG2 - FrameGen Horizontal Timing Config Register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsync_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsync_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsbp_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsbp_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsbp(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsbp_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_Hsbp_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_HsEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_HsEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_HTCFG2_diseng_framegen1_HsEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_VTCFG1 - FrameGen Vertical Timing Config Register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vact_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vact_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vact(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vact_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vact_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vtotal_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vtotal_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vtotal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vtotal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG1_diseng_framegen1_Vtotal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_VTCFG2 - FrameGen Vertical Timing Config Register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsync_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsync_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsbp_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsbp_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsbp(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsbp_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_Vsbp_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_VsEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_VsEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_VsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_VsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_VTCFG2_diseng_framegen1_VsEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_INT0CONFIG - Coordinates of the trigger point for generation of the Int0 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT0CONFIG_diseng_framegen1_Int0En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_INT1CONFIG - Coordinates of the trigger point for generation of the Int1 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT1CONFIG_diseng_framegen1_Int1En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_INT2CONFIG - Coordinates of the trigger point for generation of the Int2 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT2CONFIG_diseng_framegen1_Int2En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_INT3CONFIG - Coordinates of the trigger point for generation of the Int3 interrupt signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Col_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Col_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Col(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Col_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Col_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3HsEn_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3HsEn_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3HsEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3HsEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3HsEn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Row_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Row_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Row(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Row_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3Row_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3En_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3En_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_INT3CONFIG_diseng_framegen1_Int3En_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_PKICKCONFIG - Coordinates of the trigger point for generation of the primary kick signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickCol_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickCol_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickCol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickCol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickCol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickInt0En_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickInt0En_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickInt0En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickInt0En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickInt0En_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickRow_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickRow_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickRow(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickRow_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickRow_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_PKICKCONFIG_diseng_framegen1_PKickEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_SKICKCONFIG - Coordinates of the trigger point for generation of the secondary kick signal */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickCol_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickCol_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickCol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickCol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickCol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickInt1En_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickInt1En_SHIFT (15U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickInt1En(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickInt1En_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickInt1En_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickRow_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickRow_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickRow(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickRow_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickRow_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickTrig_MASK (0x40000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickTrig_SHIFT (30U) /*! diseng_framegen1_SKickTrig * 0b0..Use internal skick signal, trigger point defined by SKickRow and SKickCol. * 0b1..Use external skick input as trigger. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickTrig(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickTrig_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickTrig_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickEn_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickEn_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SKICKCONFIG_diseng_framegen1_SKickEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_SECSTATCONFIG - Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevGoodFrames_MASK (0xFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevGoodFrames_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevGoodFrames(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevGoodFrames_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevGoodFrames_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevBadFrames_MASK (0xF0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevBadFrames_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevBadFrames(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevBadFrames_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevBadFrames_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevSkewInRange_MASK (0xF00U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevSkewInRange_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevSkewInRange(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevSkewInRange_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SECSTATCONFIG_diseng_framegen1_LevSkewInRange_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR1 - FrameGen Skew Regulation Control Register 1. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREn_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRMode_MASK (0x6U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRMode_SHIFT (1U) /*! diseng_framegen1_SRMode * 0b00..Skew Regulation is off. * 0b01..Horizontal regulation enabled. * 0b10..Vertical regulation enabled. * 0b11..Both regulation modes are enabled. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRMode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRMode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRMode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRAdj_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRAdj_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRAdj(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRAdj_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRAdj_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREven_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREven_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREven(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREven_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREven_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRFastSync_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRFastSync_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRFastSync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRFastSync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRFastSync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQAlign_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQAlign_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQAlign(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQAlign_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQAlign_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQVal_MASK (0x180U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQVal_SHIFT (7U) /*! diseng_framegen1_SRQVal * 0b00..Fixed two LSB values of HTOTAL are 0b00. * 0b01..Fixed two LSB values of HTOTAL are 0b01. * 0b10..Fixed two LSB values of HTOTAL are 0b10. * 0b11..Fixed two LSB values of HTOTAL are 0b11. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQVal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQVal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRQVal_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRDbgDisp_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRDbgDisp_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRDbgDisp(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRDbgDisp_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRDbgDisp_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREpOff_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREpOff_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREpOff_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SREpOff_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRClock_Mode_MASK (0x1800U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRClock_Mode_SHIFT (11U) /*! diseng_framegen1_SRClock_Mode * 0b00..No clock regulation. * 0b01..Adapt clock frequency to input frame rate. Output alignment is done with h/vtotal regulation * 0b10..Start with CLKADAPT till in sync, switch to ONLY after in sync. * 0b11..Only clock regulation. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRClock_Mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRClock_Mode_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRClock_Mode_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRExt_MASK (0x2000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRExt_SHIFT (13U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRExt(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRExt_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_SRExt_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_CsSyncSel_MASK (0xC0000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_CsSyncSel_SHIFT (30U) /*! diseng_framegen1_CsSyncSel * 0b00..Use APIX control signals for external sync. * 0b01..Use HS VS for external sync. * 0b10..Use DSC control signals for external sync. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_CsSyncSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_CsSyncSel_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR1_diseng_framegen1_CsSyncSel_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR2 - FrameGen Skew Regulation Control Register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMin_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMin_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMax_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMax_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR2_diseng_framegen1_HTotalMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR3 - FrameGen Skew Regulation Control Register 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMin_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMin_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMax_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMax_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR3_diseng_framegen1_VTotalMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR4 - FrameGen Skew Regulation Control Register 4 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR4_diseng_framegen1_TargetSkew_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR4_diseng_framegen1_TargetSkew_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR4_diseng_framegen1_TargetSkew(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR4_diseng_framegen1_TargetSkew_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR4_diseng_framegen1_TargetSkew_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR5 - FrameGen Skew Regulation Control Register 5 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR5_diseng_framegen1_SyncRangeLow_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR5_diseng_framegen1_SyncRangeLow_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR5_diseng_framegen1_SyncRangeLow(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR5_diseng_framegen1_SyncRangeLow_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR5_diseng_framegen1_SyncRangeLow_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR6 - FrameGen Skew Regulation Control Register 6 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR6_diseng_framegen1_SyncRangeHigh_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR6_diseng_framegen1_SyncRangeHigh_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR6_diseng_framegen1_SyncRangeHigh(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR6_diseng_framegen1_SyncRangeHigh_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR6_diseng_framegen1_SyncRangeHigh_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR7 - FrameGen Skew Regulation Control Register 7 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_HorizontalIncrement_MASK (0x7FFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_HorizontalIncrement_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_HorizontalIncrement(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_HorizontalIncrement_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_HorizontalIncrement_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_VerticalIncrement_MASK (0xF8000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_VerticalIncrement_SHIFT (27U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_VerticalIncrement(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_VerticalIncrement_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR7_diseng_framegen1_VerticalIncrement_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR8 - FrameGen Skew Regulation Control Register 8 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR8_diseng_framegen1_StartOffset_MASK (0x3FFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR8_diseng_framegen1_StartOffset_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR8_diseng_framegen1_StartOffset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR8_diseng_framegen1_StartOffset_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR8_diseng_framegen1_StartOffset_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR9 - FrameGen Skew Regulation Control Register 9 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR9_diseng_framegen1_clockperiod_ref_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR9_diseng_framegen1_clockperiod_ref_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR9_diseng_framegen1_clockperiod_ref(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR9_diseng_framegen1_clockperiod_ref_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR9_diseng_framegen1_clockperiod_ref_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR10 - FrameGen Skew Regulation Control Register 10 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR10_diseng_framegen1_clockperiod_min_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR10_diseng_framegen1_clockperiod_min_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR10_diseng_framegen1_clockperiod_min(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR10_diseng_framegen1_clockperiod_min_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR10_diseng_framegen1_clockperiod_min_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR11 - FrameGen Skew Regulation Control Register 11 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR11_diseng_framegen1_clockperiod_max_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR11_diseng_framegen1_clockperiod_max_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR11_diseng_framegen1_clockperiod_max(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR11_diseng_framegen1_clockperiod_max_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR11_diseng_framegen1_clockperiod_max_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR12 - FrameGen Skew Regulation Control Register 12 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR12_diseng_framegen1_pixel_period_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR12_diseng_framegen1_pixel_period_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR12_diseng_framegen1_pixel_period(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR12_diseng_framegen1_pixel_period_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR12_diseng_framegen1_pixel_period_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR13 - FrameGen Skew Regulation Control Register 13 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_filterrate_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_filterrate_SHIFT (2U) /*! diseng_framegen1_CSR_filterrate * 0b00..Clock measurement update rate defined by CSR_updaterate, no additional filter used. * 0b01..Clock measurements update rate defined by CSR_updaterate filtered by 4. * 0b10..Clock measurements update rate defined by CSR_updaterate filtered by 16. * 0b11..Clock measurements update rate defined by CSR_updaterate filtered by 64. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_filterrate(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_filterrate_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_filterrate_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_updaterate_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_updaterate_SHIFT (4U) /*! diseng_framegen1_CSR_updaterate * 0b000..Clock measurement is off, reference value is used. * 0b100..Measured clock is averaged over 2^16 input clock cycles. * 0b101..Measured clock is averaged over 2^14 input clock cycles. * 0b110..Measured clock is averaged over 2^12 input clock cycles. * 0b111..Measured clock is averaged over 2^10 input clock cycles. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_updaterate(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_updaterate_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CSR_updaterate_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CMSyncSel_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CMSyncSel_SHIFT (7U) /*! diseng_framegen1_CMSyncSel * 0b0..Use APIX control signals for clock measurement. * 0b1..Use HS VS for clock measurement. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CMSyncSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CMSyncSel_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR13_diseng_framegen1_CMSyncSel_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR14 - FrameGen Skew Regulation Control Register 14 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_Clockperiod_val_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_Clockperiod_val_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_Clockperiod_val(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_Clockperiod_val_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_Clockperiod_val_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_SSCGTrack_en_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_SSCGTrack_en_SHIFT (3U) /*! diseng_framegen1_CSR_SSCGTrack_en * 0b0..Phase regulation does not take SSCG into account. * 0b1..Phase regulation does take SSCG into account. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_SSCGTrack_en(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_SSCGTrack_en_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_SSCGTrack_en_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_SHIFT (4U) /*! diseng_framegen1_CSR_ramprate * 0b000..Phase regulation uses phasegain for step. * 0b001..Phase regulation uses 1/2 of phasegain for step. * 0b010..Phase regulation uses 1/4 of phasegain for step. * 0b011..Phase regulation uses 1/8 of phasegain for step. * 0b100..Phase regulation uses 1/16 of phasegain for step. * 0b101..Phase regulation uses 1/32 of phasegain for step. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_en_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_en_SHIFT (7U) /*! diseng_framegen1_CSR_ramprate_en * 0b0..Phase regulation uses phasegain for step. * 0b1..Phase regulation uses CSR_ramprate of phasegain for step. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_en(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_en_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_ramprate_en_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegain_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegain_SHIFT (8U) /*! diseng_framegen1_CSR_phasegain * 0b000..Phase regulation uses 1/1024 of clock period. Htotal has to be bigger than 1025+32. * 0b001..Phase regulation uses 1/512 of clock period. Htotal has to be bigger than 513+32. * 0b010..Phase regulation uses 1/256 of clock period. Htotal has to be bigger than 257+32. * 0b011..Phase regulation uses 1/128 of clock period. Htotal has to be bigger than 129+32. * 0b100..Phase regulation uses 1/64 of clock period. Htotal has to be bigger than 65+32. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegain(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegain_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegain_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegainsync_MASK (0x7000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegainsync_SHIFT (12U) /*! diseng_framegen1_CSR_phasegainsync * 0b000..Phase regulation uses 1/1024 of clock period. Htotal has to be bigger than 1025+32. * 0b001..Phase regulation uses 1/512 of clock period. Htotal has to be bigger than 513+32. * 0b010..Phase regulation uses 1/256 of clock period. Htotal has to be bigger than 257+32. * 0b011..Phase regulation uses 1/128 of clock period. Htotal has to be bigger than 129+32. * 0b100..Phase regulation uses 1/64 of clock period. Htotal has to be bigger than 65+32. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegainsync(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegainsync_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_CSR_phasegainsync_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_SkewOffset_Threshold_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_SkewOffset_Threshold_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_SkewOffset_Threshold(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_SkewOffset_Threshold_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR14_diseng_framegen1_SkewOffset_Threshold_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCR15 - FrameGen Skew Regulation Control Register 15 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsHsPol_MASK (0x4000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsHsPol_SHIFT (14U) /*! diseng_framegen1_CsHsPol * 0b0..HSYNC is low active. * 0b1..HSYNC is high active. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsHsPol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsHsPol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsHsPol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsVsPol_MASK (0x8000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsVsPol_SHIFT (15U) /*! diseng_framegen1_CsVsPol * 0b0..VSYNC is low active. * 0b1..VSYNC is high active. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsVsPol(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsVsPol_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsVsPol_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsDelay_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsDelay_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsDelay(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsDelay_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCR15_diseng_framegen1_CsDelay_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGKSDR - FrameGen Kick System Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_PCntCplMax_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_PCntCplMax_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_PCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_PCntCplMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_PCntCplMax_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_SCntCplMax_MASK (0x70000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_SCntCplMax_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_SCntCplMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_SCntCplMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGKSDR_diseng_framegen1_SCntCplMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_PACFG - FrameGen Primary Area Config Register 1 (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstartx_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstartx_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstartx(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstartx_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstartx_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstarty_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstarty_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstarty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstarty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_PACFG_diseng_framegen1_Pstarty_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_SACFG - FrameGen Secondary Area Config Register 1 (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstartx_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstartx_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstartx(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstartx_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstartx_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstarty_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstarty_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstarty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstarty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_SACFG_diseng_framegen1_Sstarty_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGINCTRL - FrameGen Input Control Register (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_FgDm_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_FgDm_SHIFT (0U) /*! diseng_framegen1_FgDm * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_FgDm(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_FgDm_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_FgDm_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnPrimAlpha_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnPrimAlpha_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnPrimAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnPrimAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnPrimAlpha_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnSecAlpha_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnSecAlpha_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnSecAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnSecAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRL_diseng_framegen1_EnSecAlpha_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGINCTRLPANIC - FrameGen Input Control Panic Register (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_FgDmPanic_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_FgDmPanic_SHIFT (0U) /*! diseng_framegen1_FgDmPanic * 0b000..Black Color Background is shown. * 0b001..Constant Color Background is shown. * 0b010..Primary input only is shown. * 0b011..Secondary input only is shown. * 0b100..Both inputs overlaid with primary on top. * 0b101..Both inputs overlaid with secondary on top. * 0b110..White color background with test pattern is shown. */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_FgDmPanic(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_FgDmPanic_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_FgDmPanic_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnPrimAlphaPanic_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnPrimAlphaPanic_SHIFT (3U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnPrimAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnPrimAlphaPanic_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnPrimAlphaPanic_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnSecAlphaPanic_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnSecAlphaPanic_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnSecAlphaPanic(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnSecAlphaPanic_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGINCTRLPANIC_diseng_framegen1_EnSecAlphaPanic_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGCCR - FrameGen Constant Color Register (shadowed) */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcBlue_MASK (0x3FFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcBlue_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcBlue_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcBlue_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcGreen_MASK (0xFFC00U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcGreen_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcGreen_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcGreen_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcRed_MASK (0x3FF00000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcRed_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcRed_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcRed_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcAlpha_MASK (0xC0000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcAlpha_SHIFT (30U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCCR_diseng_framegen1_CcAlpha_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGENABLE - FrameGen Enable Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENABLE_diseng_framegen1_FgEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENABLE_diseng_framegen1_FgEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENABLE_diseng_framegen1_FgEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENABLE_diseng_framegen1_FgEn_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENABLE_diseng_framegen1_FgEn_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSLR - FrameGen Shadow Load Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSLR_diseng_framegen1_ShdTokGen_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSLR_diseng_framegen1_ShdTokGen_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSLR_diseng_framegen1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSLR_diseng_framegen1_ShdTokGen_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSLR_diseng_framegen1_ShdTokGen_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGENSTS - FrameGen Enable Status Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_EnSts_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_EnSts_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_EnSts(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_EnSts_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_EnSts_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_PanicStat_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_PanicStat_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_PanicStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_PanicStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGENSTS_diseng_framegen1_PanicStat_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGTIMESTAMP - Time stamp status. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_LineIndex_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_LineIndex_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_LineIndex(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_LineIndex_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_LineIndex_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_FrameIndex_MASK (0xFFFFC000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_FrameIndex_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_FrameIndex(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_FrameIndex_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGTIMESTAMP_diseng_framegen1_FrameIndex_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGCHSTAT - FrameGen Channel Status Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PFifoEmpty_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PFifoEmpty_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PFifoEmpty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PFifoEmpty_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PrimSyncStat_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PrimSyncStat_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PrimSyncStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PrimSyncStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_PrimSyncStat_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SFifoEmpty_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SFifoEmpty_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SFifoEmpty(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SFifoEmpty_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SFifoEmpty_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SkewRangeErr_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SkewRangeErr_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SkewRangeErr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SkewRangeErr_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SkewRangeErr_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SecSyncStat_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SecSyncStat_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SecSyncStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SecSyncStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTAT_diseng_framegen1_SecSyncStat_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGCHSTATCLR - FrameGen Channel Status Clear Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrPrimStat_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrPrimStat_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrPrimStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrPrimStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrPrimStat_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrSecStat_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrSecStat_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrSecStat(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrSecStat_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGCHSTATCLR_diseng_framegen1_ClrSecStat_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSKEWMON - FrameGen Skew Monitor Register for Secondary Channel Skew Control */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSKEWMON_diseng_framegen1_SkewMon_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSKEWMON_diseng_framegen1_SkewMon_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSKEWMON_diseng_framegen1_SkewMon(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSKEWMON_diseng_framegen1_SkewMon_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSKEWMON_diseng_framegen1_SkewMon_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGPFIFOMIN - FrameGen Primary FIFO Min Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMIN_diseng_framegen1_PFifoMin_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMIN_diseng_framegen1_PFifoMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMIN_diseng_framegen1_PFifoMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMIN_diseng_framegen1_PFifoMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMIN_diseng_framegen1_PFifoMin_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGPFIFOMAX - FrameGen Primary FIFO Max Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMAX_diseng_framegen1_PFifoMax_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMAX_diseng_framegen1_PFifoMax_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMAX_diseng_framegen1_PFifoMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMAX_diseng_framegen1_PFifoMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOMAX_diseng_framegen1_PFifoMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGPFIFOFILLCLR - FrameGen Primary FIFO Fill Clear Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOFILLCLR_diseng_framegen1_PFifoFillClr_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOFILLCLR_diseng_framegen1_PFifoFillClr_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOFILLCLR_diseng_framegen1_PFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOFILLCLR_diseng_framegen1_PFifoFillClr_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOFILLCLR_diseng_framegen1_PFifoFillClr_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGPFIFOTRES - FrameGen Primary FIFO Thresholds */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres0_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres0_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres0_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres1_MASK (0xFFFF0000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres1_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGPFIFOTRES_diseng_framegen1_PFifoTres1_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSFIFOMIN - FrameGen Secondary FIFO Min Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMIN_diseng_framegen1_SFifoMin_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMIN_diseng_framegen1_SFifoMin_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMIN_diseng_framegen1_SFifoMin(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMIN_diseng_framegen1_SFifoMin_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMIN_diseng_framegen1_SFifoMin_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSFIFOMAX - FrameGen Secondary FIFO Max Fill Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMAX_diseng_framegen1_SFifoMax_MASK (0xFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMAX_diseng_framegen1_SFifoMax_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMAX_diseng_framegen1_SFifoMax(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMAX_diseng_framegen1_SFifoMax_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOMAX_diseng_framegen1_SFifoMax_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSFIFOFILLCLR - FrameGen Secondary FIFO Fill Clear Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOFILLCLR_diseng_framegen1_SFifoFillClr_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOFILLCLR_diseng_framegen1_SFifoFillClr_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOFILLCLR_diseng_framegen1_SFifoFillClr(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOFILLCLR_diseng_framegen1_SFifoFillClr_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSFIFOFILLCLR_diseng_framegen1_SFifoFillClr_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSREPD - FrameGen Skew Regulation ExtraPolation Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSREPD_diseng_framegen1_EpVal_MASK (0x1FFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSREPD_diseng_framegen1_EpVal_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSREPD_diseng_framegen1_EpVal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSREPD_diseng_framegen1_EpVal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSREPD_diseng_framegen1_EpVal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRFTD - FrameGen Skew Regulation Frame Total Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRFTD_diseng_framegen1_FrTot_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRFTD_diseng_framegen1_FrTot_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRFTD_diseng_framegen1_FrTot(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRFTD_diseng_framegen1_FrTot_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRFTD_diseng_framegen1_FrTot_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCSHTOTAL - FrameGen Skew Regulation External Sync HTotal Debug Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCSHTOTAL_diseng_framegen1_FrCSHTotal_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCSHTOTAL_diseng_framegen1_FrCSHTotal_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCSHTOTAL_diseng_framegen1_FrCSHTotal(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCSHTOTAL_diseng_framegen1_FrCSHTotal_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCSHTOTAL_diseng_framegen1_FrCSHTotal_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSRCLOCKDIV - FrameGen Skew Regulation External PLL Clock divider */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCLOCKDIV_diseng_framegen1_FrClockDiv_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCLOCKDIV_diseng_framegen1_FrClockDiv_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCLOCKDIV_diseng_framegen1_FrClockDiv(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCLOCKDIV_diseng_framegen1_FrClockDiv_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSRCLOCKDIV_diseng_framegen1_FrClockDiv_MASK) /*! @} */ /*! @name DISENG_FRAMEGEN1_FGSL - FrameGen Scanline Register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_ScanLine_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_ScanLine_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_ScanLine(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_ScanLine_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_ScanLine_MASK) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_VBlank_MASK (0x80000000U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_VBlank_SHIFT (31U) #define DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_VBlank(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_VBlank_SHIFT)) & DISPLAY_SEERIS_DISENG_FRAMEGEN1_FGSL_diseng_framegen1_VBlank_MASK) /*! @} */ /*! @name DISENG_SIG1_LOCKUNLOCK - Register to change the protection status of this address block */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOCKUNLOCK_diseng_sig1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKUNLOCK_diseng_sig1_LockUnlock_SHIFT (0U) /*! diseng_sig1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_SIG1_LOCKUNLOCK_diseng_sig1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOCKUNLOCK_diseng_sig1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOCKUNLOCK_diseng_sig1_LockUnlock_MASK) /*! @} */ /*! @name DISENG_SIG1_LOCKSTATUS - Protection status of this address block */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOCKSTATUS_diseng_sig1_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_SIG1_STATICCONTROL - Global configuration */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdEn_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdLdSel_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdLdSel_SHIFT (4U) /*! diseng_sig1_ShdLdSel * 0b0..Shadows are loaded at start of frame for each evaluation window for which ShdLdReq has been set. * 0b1..Shadows of all evaluation windows are loaded synchronous to the display stream (shadow load token received on frame input port). */ #define DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdLdSel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdLdSel_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATICCONTROL_diseng_sig1_ShdLdSel_MASK) /*! @} */ /*! @name DISENG_SIG1_ERRORTHRESHOLD - Set and reset thresholds applying to Window_Error and Cluster_Error interrupts and status bits */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThres_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThres_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThres(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThres_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThres_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThresReset_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThresReset_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThresReset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThresReset_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_ERRORTHRESHOLD_diseng_sig1_ErrThresReset_MASK) /*! @} */ /*! @name DISENG_SIG1_MATCHTHRESHOLD - Set and reset thresholds applying to Match interrupt and status bits */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThres_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThres_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThres(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThres_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThres_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThresReset_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThresReset_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThresReset(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThresReset_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MATCHTHRESHOLD_diseng_sig1_MatchThresReset_MASK) /*! @} */ /*! @name DISENG_SIG1_PANICCOLOR - Overlay color for evaluation windows in panic mode */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicAlpha_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicAlpha_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicAlpha(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicAlpha_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicAlpha_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicBlue_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicBlue_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicBlue(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicBlue_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicBlue_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicGreen_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicGreen_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicGreen(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicGreen_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicGreen_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicRed_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicRed_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicRed(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicRed_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PANICCOLOR_diseng_sig1_PanicRed_MASK) /*! @} */ /*! @name DISENG_SIG1_SHADOWLOAD - Shadow load control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_SHADOWLOAD_diseng_sig1_ShdLdReq_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_SHADOWLOAD_diseng_sig1_ShdLdReq_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_SHADOWLOAD_diseng_sig1_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_SHADOWLOAD_diseng_sig1_ShdLdReq_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_SHADOWLOAD_diseng_sig1_ShdLdReq_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTINUOUSMODE - Signature operation mode control */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTINUOUSMODE_diseng_sig1_EnCont_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTINUOUSMODE_diseng_sig1_EnCont_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTINUOUSMODE_diseng_sig1_EnCont(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTINUOUSMODE_diseng_sig1_EnCont_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTINUOUSMODE_diseng_sig1_EnCont_MASK) /*! @} */ /*! @name DISENG_SIG1_SOFTWAREKICK - Signature measurement trigger */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_SOFTWAREKICK_diseng_sig1_Kick_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_SOFTWAREKICK_diseng_sig1_Kick_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_SOFTWAREKICK_diseng_sig1_Kick(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_SOFTWAREKICK_diseng_sig1_Kick_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_SOFTWAREKICK_diseng_sig1_Kick_MASK) /*! @} */ /*! @name DISENG_SIG1_SKIPWINDOW - Enable skipping window feature. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_SKIPWINDOW_diseng_sig1_SkipWinEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_SKIPWINDOW_diseng_sig1_SkipWinEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_SKIPWINDOW_diseng_sig1_SkipWinEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_SKIPWINDOW_diseng_sig1_SkipWinEn_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_SKIPWINDOW_diseng_sig1_SkipWinEn_MASK) /*! @} */ /*! @name DISENG_SIG1_STATUS - Signature evaluation status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigState_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigState_SHIFT (0U) /*! diseng_sig1_SigState * 0b0..Signature is in idle state * 0b1..Signature is in run state */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigState(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigState_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigState_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigValid_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigValid_SHIFT (1U) /*! diseng_sig1_SigValid * 0b0..Signature results are not valid * 0b1..Signature results are valid */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigValid(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigValid_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_SigValid_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Window_Error_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Window_Error_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Window_Error(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Window_Error_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Window_Error_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Error_MASK (0xF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Error_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Error(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Error_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Error_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Match_MASK (0xF00000U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Match_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Match(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Match_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_diseng_sig1_Cluster_Match_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW0 - Window 0, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_En_Window0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_En_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_En_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_En_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_En_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_CRC_Window0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_CRC_Window0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_CRC_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_CRC_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_CRC_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaMask_Window0_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaMask_Window0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaMask_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaMask_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaMask_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaInv_Window0_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaInv_Window0_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaInv_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaInv_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaInv_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaSel_Window0_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaSel_Window0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaSel_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaSel_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_AlphaSel_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_LocalPanic_Window0_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_LocalPanic_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_LocalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_LocalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_LocalPanic_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_GlobalPanic_Window0_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_GlobalPanic_Window0_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_GlobalPanic_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_GlobalPanic_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_GlobalPanic_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_Sum_Window0_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_Sum_Window0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_Sum_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_Sum_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW0_diseng_sig1_Sum_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW0 - Window 0, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW0_diseng_sig1_UpperLeft_Y_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW0 - Window 0, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_X_Window0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_X_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_X_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_X_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_X_Window0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_Y_Window0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_Y_Window0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_Y_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_Y_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW0_diseng_sig1_LowerRight_Y_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW0 - Window 0, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW0_diseng_sig1_Ref_R_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW0_diseng_sig1_Ref_R_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW0_diseng_sig1_Ref_R_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW0_diseng_sig1_Ref_R_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW0_diseng_sig1_Ref_R_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW0 - Window 0, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW0_diseng_sig1_Ref_G_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW0_diseng_sig1_Ref_G_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW0_diseng_sig1_Ref_G_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW0_diseng_sig1_Ref_G_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW0_diseng_sig1_Ref_G_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW0 - Window 0, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW0_diseng_sig1_Ref_B_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW0_diseng_sig1_Ref_B_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW0_diseng_sig1_Ref_B_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW0_diseng_sig1_Ref_B_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW0_diseng_sig1_Ref_B_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS0_WINDOW0 - Controls of Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaMask_S0_Win0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaMask_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaMask_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaMask_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaMask_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaInv_S0_Win0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaInv_S0_Win0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaInv_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaInv_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaInv_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaSel_S0_Win0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaSel_S0_Win0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaSel_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaSel_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW0_diseng_sig1_AlphaSel_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS1_WINDOW0 - Controls of Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaMask_S1_Win0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaMask_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaMask_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaMask_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaMask_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaInv_S1_Win0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaInv_S1_Win0_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaInv_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaInv_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaInv_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaSel_S1_Win0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaSel_S1_Win0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaSel_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaSel_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW0_diseng_sig1_AlphaSel_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_REDSUM_WINDOW0 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW0_diseng_sig1_Min_RSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW0_diseng_sig1_Min_RSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW0_diseng_sig1_Min_RSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW0_diseng_sig1_Min_RSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW0_diseng_sig1_Min_RSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_GREENSUM_WINDOW0 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW0_diseng_sig1_Min_GSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW0_diseng_sig1_Min_GSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW0_diseng_sig1_Min_GSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW0_diseng_sig1_Min_GSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW0_diseng_sig1_Min_GSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_BLUESUM_WINDOW0 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW0_diseng_sig1_Min_BSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW0_diseng_sig1_Min_BSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW0_diseng_sig1_Min_BSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW0_diseng_sig1_Min_BSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW0_diseng_sig1_Min_BSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_LUMSUM_WINDOW0 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW0_diseng_sig1_Min_LSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW0_diseng_sig1_Min_LSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW0_diseng_sig1_Min_LSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW0_diseng_sig1_Min_LSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW0_diseng_sig1_Min_LSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_REDSUM_WINDOW0 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW0_diseng_sig1_Max_RSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW0_diseng_sig1_Max_RSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW0_diseng_sig1_Max_RSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW0_diseng_sig1_Max_RSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW0_diseng_sig1_Max_RSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_GREENSUM_WINDOW0 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW0_diseng_sig1_Max_GSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW0_diseng_sig1_Max_GSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW0_diseng_sig1_Max_GSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW0_diseng_sig1_Max_GSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW0_diseng_sig1_Max_GSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_BLUESUM_WINDOW0 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW0_diseng_sig1_Max_BSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW0_diseng_sig1_Max_BSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW0_diseng_sig1_Max_BSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW0_diseng_sig1_Max_BSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW0_diseng_sig1_Max_BSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_LUMSUM_WINDOW0 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW0_diseng_sig1_Max_LSum_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW0_diseng_sig1_Max_LSum_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW0_diseng_sig1_Max_LSum_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW0_diseng_sig1_Max_LSum_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW0_diseng_sig1_Max_LSum_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW1 - Window 1, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_En_Window1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_En_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_En_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_En_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_En_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_CRC_Window1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_CRC_Window1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_CRC_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_CRC_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_CRC_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaMask_Window1_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaMask_Window1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaMask_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaMask_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaMask_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaInv_Window1_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaInv_Window1_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaInv_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaInv_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaInv_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaSel_Window1_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaSel_Window1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaSel_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaSel_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_AlphaSel_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_LocalPanic_Window1_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_LocalPanic_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_LocalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_LocalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_LocalPanic_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_GlobalPanic_Window1_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_GlobalPanic_Window1_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_GlobalPanic_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_GlobalPanic_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_GlobalPanic_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_Sum_Window1_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_Sum_Window1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_Sum_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_Sum_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW1_diseng_sig1_Sum_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW1 - Window 1, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW1_diseng_sig1_UpperLeft_Y_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW1 - Window 1, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_X_Window1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_X_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_X_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_X_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_X_Window1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_Y_Window1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_Y_Window1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_Y_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_Y_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW1_diseng_sig1_LowerRight_Y_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW1 - Window 1, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW1_diseng_sig1_Ref_R_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW1_diseng_sig1_Ref_R_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW1_diseng_sig1_Ref_R_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW1_diseng_sig1_Ref_R_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW1_diseng_sig1_Ref_R_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW1 - Window 1, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW1_diseng_sig1_Ref_G_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW1_diseng_sig1_Ref_G_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW1_diseng_sig1_Ref_G_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW1_diseng_sig1_Ref_G_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW1_diseng_sig1_Ref_G_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW1 - Window 1, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW1_diseng_sig1_Ref_B_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW1_diseng_sig1_Ref_B_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW1_diseng_sig1_Ref_B_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW1_diseng_sig1_Ref_B_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW1_diseng_sig1_Ref_B_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS0_WINDOW1 - Controls of Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaMask_S0_Win1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaMask_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaMask_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaMask_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaMask_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaInv_S0_Win1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaInv_S0_Win1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaInv_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaInv_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaInv_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaSel_S0_Win1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaSel_S0_Win1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaSel_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaSel_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW1_diseng_sig1_AlphaSel_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS1_WINDOW1 - Controls of Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaMask_S1_Win1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaMask_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaMask_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaMask_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaMask_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaInv_S1_Win1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaInv_S1_Win1_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaInv_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaInv_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaInv_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaSel_S1_Win1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaSel_S1_Win1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaSel_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaSel_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW1_diseng_sig1_AlphaSel_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_REDSUM_WINDOW1 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW1_diseng_sig1_Min_RSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW1_diseng_sig1_Min_RSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW1_diseng_sig1_Min_RSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW1_diseng_sig1_Min_RSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW1_diseng_sig1_Min_RSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_GREENSUM_WINDOW1 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW1_diseng_sig1_Min_GSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW1_diseng_sig1_Min_GSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW1_diseng_sig1_Min_GSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW1_diseng_sig1_Min_GSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW1_diseng_sig1_Min_GSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_BLUESUM_WINDOW1 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW1_diseng_sig1_Min_BSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW1_diseng_sig1_Min_BSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW1_diseng_sig1_Min_BSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW1_diseng_sig1_Min_BSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW1_diseng_sig1_Min_BSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_LUMSUM_WINDOW1 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW1_diseng_sig1_Min_LSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW1_diseng_sig1_Min_LSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW1_diseng_sig1_Min_LSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW1_diseng_sig1_Min_LSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW1_diseng_sig1_Min_LSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_REDSUM_WINDOW1 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW1_diseng_sig1_Max_RSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW1_diseng_sig1_Max_RSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW1_diseng_sig1_Max_RSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW1_diseng_sig1_Max_RSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW1_diseng_sig1_Max_RSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_GREENSUM_WINDOW1 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW1_diseng_sig1_Max_GSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW1_diseng_sig1_Max_GSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW1_diseng_sig1_Max_GSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW1_diseng_sig1_Max_GSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW1_diseng_sig1_Max_GSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_BLUESUM_WINDOW1 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW1_diseng_sig1_Max_BSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW1_diseng_sig1_Max_BSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW1_diseng_sig1_Max_BSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW1_diseng_sig1_Max_BSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW1_diseng_sig1_Max_BSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_LUMSUM_WINDOW1 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW1_diseng_sig1_Max_LSum_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW1_diseng_sig1_Max_LSum_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW1_diseng_sig1_Max_LSum_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW1_diseng_sig1_Max_LSum_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW1_diseng_sig1_Max_LSum_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW2 - Window 2, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_En_Window2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_En_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_En_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_En_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_En_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_CRC_Window2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_CRC_Window2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_CRC_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_CRC_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_CRC_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaMask_Window2_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaMask_Window2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaMask_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaMask_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaMask_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaInv_Window2_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaInv_Window2_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaInv_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaInv_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaInv_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaSel_Window2_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaSel_Window2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaSel_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaSel_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_AlphaSel_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_LocalPanic_Window2_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_LocalPanic_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_LocalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_LocalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_LocalPanic_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_GlobalPanic_Window2_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_GlobalPanic_Window2_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_GlobalPanic_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_GlobalPanic_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_GlobalPanic_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_Sum_Window2_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_Sum_Window2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_Sum_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_Sum_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW2_diseng_sig1_Sum_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW2 - Window 2, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW2_diseng_sig1_UpperLeft_Y_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW2 - Window 2, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_X_Window2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_X_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_X_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_X_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_X_Window2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_Y_Window2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_Y_Window2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_Y_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_Y_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW2_diseng_sig1_LowerRight_Y_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW2 - Window 2, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW2_diseng_sig1_Ref_R_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW2_diseng_sig1_Ref_R_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW2_diseng_sig1_Ref_R_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW2_diseng_sig1_Ref_R_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW2_diseng_sig1_Ref_R_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW2 - Window 2, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW2_diseng_sig1_Ref_G_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW2_diseng_sig1_Ref_G_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW2_diseng_sig1_Ref_G_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW2_diseng_sig1_Ref_G_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW2_diseng_sig1_Ref_G_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW2 - Window 2, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW2_diseng_sig1_Ref_B_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW2_diseng_sig1_Ref_B_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW2_diseng_sig1_Ref_B_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW2_diseng_sig1_Ref_B_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW2_diseng_sig1_Ref_B_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS0_WINDOW2 - Controls of Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaMask_S0_Win2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaMask_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaMask_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaMask_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaMask_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaInv_S0_Win2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaInv_S0_Win2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaInv_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaInv_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaInv_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaSel_S0_Win2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaSel_S0_Win2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaSel_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaSel_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW2_diseng_sig1_AlphaSel_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS1_WINDOW2 - Controls of Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaMask_S1_Win2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaMask_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaMask_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaMask_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaMask_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaInv_S1_Win2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaInv_S1_Win2_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaInv_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaInv_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaInv_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaSel_S1_Win2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaSel_S1_Win2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaSel_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaSel_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW2_diseng_sig1_AlphaSel_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_REDSUM_WINDOW2 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW2_diseng_sig1_Min_RSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW2_diseng_sig1_Min_RSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW2_diseng_sig1_Min_RSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW2_diseng_sig1_Min_RSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW2_diseng_sig1_Min_RSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_GREENSUM_WINDOW2 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW2_diseng_sig1_Min_GSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW2_diseng_sig1_Min_GSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW2_diseng_sig1_Min_GSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW2_diseng_sig1_Min_GSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW2_diseng_sig1_Min_GSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_BLUESUM_WINDOW2 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW2_diseng_sig1_Min_BSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW2_diseng_sig1_Min_BSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW2_diseng_sig1_Min_BSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW2_diseng_sig1_Min_BSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW2_diseng_sig1_Min_BSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_LUMSUM_WINDOW2 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW2_diseng_sig1_Min_LSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW2_diseng_sig1_Min_LSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW2_diseng_sig1_Min_LSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW2_diseng_sig1_Min_LSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW2_diseng_sig1_Min_LSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_REDSUM_WINDOW2 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW2_diseng_sig1_Max_RSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW2_diseng_sig1_Max_RSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW2_diseng_sig1_Max_RSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW2_diseng_sig1_Max_RSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW2_diseng_sig1_Max_RSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_GREENSUM_WINDOW2 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW2_diseng_sig1_Max_GSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW2_diseng_sig1_Max_GSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW2_diseng_sig1_Max_GSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW2_diseng_sig1_Max_GSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW2_diseng_sig1_Max_GSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_BLUESUM_WINDOW2 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW2_diseng_sig1_Max_BSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW2_diseng_sig1_Max_BSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW2_diseng_sig1_Max_BSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW2_diseng_sig1_Max_BSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW2_diseng_sig1_Max_BSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_LUMSUM_WINDOW2 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW2_diseng_sig1_Max_LSum_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW2_diseng_sig1_Max_LSum_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW2_diseng_sig1_Max_LSum_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW2_diseng_sig1_Max_LSum_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW2_diseng_sig1_Max_LSum_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW3 - Window 3, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_En_Window3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_En_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_En_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_En_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_En_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_CRC_Window3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_CRC_Window3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_CRC_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_CRC_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_CRC_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaMask_Window3_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaMask_Window3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaMask_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaMask_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaMask_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaInv_Window3_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaInv_Window3_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaInv_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaInv_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaInv_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaSel_Window3_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaSel_Window3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaSel_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaSel_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_AlphaSel_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_LocalPanic_Window3_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_LocalPanic_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_LocalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_LocalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_LocalPanic_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_GlobalPanic_Window3_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_GlobalPanic_Window3_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_GlobalPanic_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_GlobalPanic_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_GlobalPanic_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_Sum_Window3_MASK (0x1000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_Sum_Window3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_Sum_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_Sum_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW3_diseng_sig1_Sum_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW3 - Window 3, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW3_diseng_sig1_UpperLeft_Y_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW3 - Window 3, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_X_Window3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_X_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_X_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_X_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_X_Window3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_Y_Window3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_Y_Window3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_Y_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_Y_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW3_diseng_sig1_LowerRight_Y_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW3 - Window 3, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW3_diseng_sig1_Ref_R_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW3_diseng_sig1_Ref_R_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW3_diseng_sig1_Ref_R_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW3_diseng_sig1_Ref_R_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW3_diseng_sig1_Ref_R_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW3 - Window 3, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW3_diseng_sig1_Ref_G_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW3_diseng_sig1_Ref_G_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW3_diseng_sig1_Ref_G_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW3_diseng_sig1_Ref_G_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW3_diseng_sig1_Ref_G_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW3 - Window 3, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW3_diseng_sig1_Ref_B_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW3_diseng_sig1_Ref_B_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW3_diseng_sig1_Ref_B_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW3_diseng_sig1_Ref_B_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW3_diseng_sig1_Ref_B_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS0_WINDOW3 - Controls of Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaMask_S0_Win3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaMask_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaMask_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaMask_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaMask_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaInv_S0_Win3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaInv_S0_Win3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaInv_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaInv_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaInv_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaSel_S0_Win3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaSel_S0_Win3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaSel_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaSel_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS0_WINDOW3_diseng_sig1_AlphaSel_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_STATS1_WINDOW3 - Controls of Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaMask_S1_Win3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaMask_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaMask_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaMask_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaMask_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaInv_S1_Win3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaInv_S1_Win3_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaInv_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaInv_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaInv_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaSel_S1_Win3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaSel_S1_Win3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaSel_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaSel_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATS1_WINDOW3_diseng_sig1_AlphaSel_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_REDSUM_WINDOW3 - Minimum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW3_diseng_sig1_Min_RSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW3_diseng_sig1_Min_RSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW3_diseng_sig1_Min_RSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW3_diseng_sig1_Min_RSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_REDSUM_WINDOW3_diseng_sig1_Min_RSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_GREENSUM_WINDOW3 - Minimum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW3_diseng_sig1_Min_GSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW3_diseng_sig1_Min_GSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW3_diseng_sig1_Min_GSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW3_diseng_sig1_Min_GSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_GREENSUM_WINDOW3_diseng_sig1_Min_GSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_BLUESUM_WINDOW3 - Minimum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW3_diseng_sig1_Min_BSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW3_diseng_sig1_Min_BSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW3_diseng_sig1_Min_BSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW3_diseng_sig1_Min_BSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_BLUESUM_WINDOW3_diseng_sig1_Min_BSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MIN_LUMSUM_WINDOW3 - Minimum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW3_diseng_sig1_Min_LSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW3_diseng_sig1_Min_LSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW3_diseng_sig1_Min_LSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW3_diseng_sig1_Min_LSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MIN_LUMSUM_WINDOW3_diseng_sig1_Min_LSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_REDSUM_WINDOW3 - Maximum sum-threshold for red component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW3_diseng_sig1_Max_RSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW3_diseng_sig1_Max_RSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW3_diseng_sig1_Max_RSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW3_diseng_sig1_Max_RSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_REDSUM_WINDOW3_diseng_sig1_Max_RSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_GREENSUM_WINDOW3 - Maximum sum-threshold for green component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW3_diseng_sig1_Max_GSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW3_diseng_sig1_Max_GSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW3_diseng_sig1_Max_GSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW3_diseng_sig1_Max_GSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_GREENSUM_WINDOW3_diseng_sig1_Max_GSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_BLUESUM_WINDOW3 - Maximum sum-threshold for blue component of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW3_diseng_sig1_Max_BSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW3_diseng_sig1_Max_BSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW3_diseng_sig1_Max_BSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW3_diseng_sig1_Max_BSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_BLUESUM_WINDOW3_diseng_sig1_Max_BSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_MAX_LUMSUM_WINDOW3 - Maximum sum-threshold for luminance of the pixels in a window. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW3_diseng_sig1_Max_LSum_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW3_diseng_sig1_Max_LSum_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW3_diseng_sig1_Max_LSum_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW3_diseng_sig1_Max_LSum_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_MAX_LUMSUM_WINDOW3_diseng_sig1_Max_LSum_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW4 - Window 4, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_En_Window4_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_En_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_En_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_En_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_En_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_CRC_Window4_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_CRC_Window4_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_CRC_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_CRC_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_CRC_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaMask_Window4_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaMask_Window4_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaMask_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaMask_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaMask_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaInv_Window4_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaInv_Window4_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaInv_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaInv_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaInv_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaSel_Window4_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaSel_Window4_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaSel_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaSel_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_AlphaSel_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_LocalPanic_Window4_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_LocalPanic_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_LocalPanic_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_LocalPanic_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_LocalPanic_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_GlobalPanic_Window4_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_GlobalPanic_Window4_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_GlobalPanic_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_GlobalPanic_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW4_diseng_sig1_GlobalPanic_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW4 - Window 4, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_X_Window4_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_X_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_X_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_X_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_X_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_Y_Window4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_Y_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_Y_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_Y_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW4_diseng_sig1_UpperLeft_Y_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW4 - Window 4, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_X_Window4_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_X_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_X_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_X_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_X_Window4_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_Y_Window4_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_Y_Window4_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_Y_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_Y_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW4_diseng_sig1_LowerRight_Y_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW4 - Window 4, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW4_diseng_sig1_Ref_R_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW4_diseng_sig1_Ref_R_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW4_diseng_sig1_Ref_R_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW4_diseng_sig1_Ref_R_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW4_diseng_sig1_Ref_R_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW4 - Window 4, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW4_diseng_sig1_Ref_G_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW4_diseng_sig1_Ref_G_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW4_diseng_sig1_Ref_G_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW4_diseng_sig1_Ref_G_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW4_diseng_sig1_Ref_G_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW4 - Window 4, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW4_diseng_sig1_Ref_B_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW4_diseng_sig1_Ref_B_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW4_diseng_sig1_Ref_B_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW4_diseng_sig1_Ref_B_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW4_diseng_sig1_Ref_B_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW5 - Window 5, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_En_Window5_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_En_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_En_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_En_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_En_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_CRC_Window5_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_CRC_Window5_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_CRC_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_CRC_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_CRC_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaMask_Window5_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaMask_Window5_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaMask_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaMask_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaMask_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaInv_Window5_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaInv_Window5_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaInv_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaInv_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaInv_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaSel_Window5_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaSel_Window5_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaSel_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaSel_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_AlphaSel_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_LocalPanic_Window5_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_LocalPanic_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_LocalPanic_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_LocalPanic_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_LocalPanic_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_GlobalPanic_Window5_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_GlobalPanic_Window5_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_GlobalPanic_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_GlobalPanic_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW5_diseng_sig1_GlobalPanic_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW5 - Window 5, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_X_Window5_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_X_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_X_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_X_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_X_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_Y_Window5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_Y_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_Y_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_Y_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW5_diseng_sig1_UpperLeft_Y_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW5 - Window 5, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_X_Window5_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_X_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_X_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_X_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_X_Window5_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_Y_Window5_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_Y_Window5_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_Y_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_Y_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW5_diseng_sig1_LowerRight_Y_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW5 - Window 5, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW5_diseng_sig1_Ref_R_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW5_diseng_sig1_Ref_R_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW5_diseng_sig1_Ref_R_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW5_diseng_sig1_Ref_R_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW5_diseng_sig1_Ref_R_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW5 - Window 5, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW5_diseng_sig1_Ref_G_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW5_diseng_sig1_Ref_G_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW5_diseng_sig1_Ref_G_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW5_diseng_sig1_Ref_G_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW5_diseng_sig1_Ref_G_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW5 - Window 5, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW5_diseng_sig1_Ref_B_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW5_diseng_sig1_Ref_B_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW5_diseng_sig1_Ref_B_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW5_diseng_sig1_Ref_B_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW5_diseng_sig1_Ref_B_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW6 - Window 6, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_En_Window6_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_En_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_En_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_En_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_En_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_CRC_Window6_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_CRC_Window6_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_CRC_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_CRC_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_CRC_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaMask_Window6_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaMask_Window6_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaMask_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaMask_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaMask_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaInv_Window6_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaInv_Window6_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaInv_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaInv_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaInv_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaSel_Window6_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaSel_Window6_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaSel_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaSel_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_AlphaSel_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_LocalPanic_Window6_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_LocalPanic_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_LocalPanic_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_LocalPanic_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_LocalPanic_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_GlobalPanic_Window6_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_GlobalPanic_Window6_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_GlobalPanic_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_GlobalPanic_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW6_diseng_sig1_GlobalPanic_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW6 - Window 6, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_X_Window6_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_X_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_X_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_X_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_X_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_Y_Window6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_Y_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_Y_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_Y_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW6_diseng_sig1_UpperLeft_Y_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW6 - Window 6, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_X_Window6_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_X_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_X_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_X_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_X_Window6_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_Y_Window6_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_Y_Window6_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_Y_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_Y_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW6_diseng_sig1_LowerRight_Y_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW6 - Window 6, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW6_diseng_sig1_Ref_R_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW6_diseng_sig1_Ref_R_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW6_diseng_sig1_Ref_R_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW6_diseng_sig1_Ref_R_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW6_diseng_sig1_Ref_R_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW6 - Window 6, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW6_diseng_sig1_Ref_G_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW6_diseng_sig1_Ref_G_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW6_diseng_sig1_Ref_G_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW6_diseng_sig1_Ref_G_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW6_diseng_sig1_Ref_G_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW6 - Window 6, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW6_diseng_sig1_Ref_B_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW6_diseng_sig1_Ref_B_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW6_diseng_sig1_Ref_B_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW6_diseng_sig1_Ref_B_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW6_diseng_sig1_Ref_B_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_WINDOW7 - Window 7, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_En_Window7_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_En_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_En_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_En_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_En_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_CRC_Window7_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_CRC_Window7_SHIFT (1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_CRC_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_CRC_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_CRC_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaMask_Window7_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaMask_Window7_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaMask_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaMask_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaMask_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaInv_Window7_MASK (0x200U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaInv_Window7_SHIFT (9U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaInv_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaInv_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaInv_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaSel_Window7_MASK (0x400U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaSel_Window7_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaSel_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaSel_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_AlphaSel_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_LocalPanic_Window7_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_LocalPanic_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_LocalPanic_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_LocalPanic_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_LocalPanic_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_GlobalPanic_Window7_MASK (0x20000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_GlobalPanic_Window7_SHIFT (17U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_GlobalPanic_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_GlobalPanic_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_WINDOW7_diseng_sig1_GlobalPanic_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_UPPERLEFT_WINDOW7 - Window 7, Upper Left Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_X_Window7_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_X_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_X_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_X_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_X_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_Y_Window7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_Y_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_Y_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_Y_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_UPPERLEFT_WINDOW7_diseng_sig1_UpperLeft_Y_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_LOWERRIGHT_WINDOW7 - Window 7, Lower Right Coordinates */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_X_Window7_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_X_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_X_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_X_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_X_Window7_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_Y_Window7_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_Y_Window7_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_Y_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_Y_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LOWERRIGHT_WINDOW7_diseng_sig1_LowerRight_Y_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_R_WINDOW7 - Window 7, Reference CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW7_diseng_sig1_Ref_R_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW7_diseng_sig1_Ref_R_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW7_diseng_sig1_Ref_R_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW7_diseng_sig1_Ref_R_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_R_WINDOW7_diseng_sig1_Ref_R_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_G_WINDOW7 - Window 7, Reference CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW7_diseng_sig1_Ref_G_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW7_diseng_sig1_Ref_G_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW7_diseng_sig1_Ref_G_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW7_diseng_sig1_Ref_G_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_G_WINDOW7_diseng_sig1_Ref_G_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_REF_B_WINDOW7 - Window 7, Reference CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW7_diseng_sig1_Ref_B_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW7_diseng_sig1_Ref_B_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW7_diseng_sig1_Ref_B_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW7_diseng_sig1_Ref_B_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF_B_WINDOW7_diseng_sig1_Ref_B_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_CLUSTER0 - Cluster 0, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_En_Cluster0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_En_Cluster0_SHIFT (0U) /*! diseng_sig1_En_Cluster0 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix0_En_Cluster0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix0_En_Cluster0_SHIFT (4U) /*! diseng_sig1_Pix0_En_Cluster0 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix0_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix0_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix0_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix1_En_Cluster0_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix1_En_Cluster0_SHIFT (5U) /*! diseng_sig1_Pix1_En_Cluster0 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix1_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix1_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix1_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix2_En_Cluster0_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix2_En_Cluster0_SHIFT (6U) /*! diseng_sig1_Pix2_En_Cluster0 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix2_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix2_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix2_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix3_En_Cluster0_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix3_En_Cluster0_SHIFT (7U) /*! diseng_sig1_Pix3_En_Cluster0 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix3_En_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix3_En_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_Pix3_En_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskBlue_Cluster0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskBlue_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskBlue_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskBlue_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskBlue_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskGreen_Cluster0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskGreen_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskGreen_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskGreen_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskGreen_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskRed_Cluster0_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskRed_Cluster0_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskRed_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskRed_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER0_diseng_sig1_MaskRed_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX0_CLUSTER0 - Cluster 0, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_X0_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_X0_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_X0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_X0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_X0_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_Y0_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_Y0_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_Y0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_Y0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER0_diseng_sig1_Y0_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX1_CLUSTER0 - Cluster 0, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_X1_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_X1_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_X1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_X1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_X1_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_Y1_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_Y1_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_Y1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_Y1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER0_diseng_sig1_Y1_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX2_CLUSTER0 - Cluster 0, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_X2_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_X2_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_X2_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_X2_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_X2_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_Y2_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_Y2_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_Y2_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_Y2_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER0_diseng_sig1_Y2_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX3_CLUSTER0 - Cluster 0, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_X3_Cluster0_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_X3_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_X3_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_X3_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_X3_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_Y3_Cluster0_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_Y3_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_Y3_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_Y3_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER0_diseng_sig1_Y3_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_REF0_CLUSTER0 - Cluster 0, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER0_diseng_sig1_Ref0_Cluster0_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER0_diseng_sig1_Ref0_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER0_diseng_sig1_Ref0_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER0_diseng_sig1_Ref0_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER0_diseng_sig1_Ref0_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_REF1_CLUSTER0 - Cluster 0, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER0_diseng_sig1_Ref1_Cluster0_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER0_diseng_sig1_Ref1_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER0_diseng_sig1_Ref1_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER0_diseng_sig1_Ref1_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER0_diseng_sig1_Ref1_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_CLUSTER1 - Cluster 1, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_En_Cluster1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_En_Cluster1_SHIFT (0U) /*! diseng_sig1_En_Cluster1 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix0_En_Cluster1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix0_En_Cluster1_SHIFT (4U) /*! diseng_sig1_Pix0_En_Cluster1 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix0_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix0_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix0_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix1_En_Cluster1_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix1_En_Cluster1_SHIFT (5U) /*! diseng_sig1_Pix1_En_Cluster1 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix1_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix1_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix1_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix2_En_Cluster1_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix2_En_Cluster1_SHIFT (6U) /*! diseng_sig1_Pix2_En_Cluster1 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix2_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix2_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix2_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix3_En_Cluster1_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix3_En_Cluster1_SHIFT (7U) /*! diseng_sig1_Pix3_En_Cluster1 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix3_En_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix3_En_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_Pix3_En_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskBlue_Cluster1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskBlue_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskBlue_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskBlue_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskBlue_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskGreen_Cluster1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskGreen_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskGreen_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskGreen_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskGreen_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskRed_Cluster1_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskRed_Cluster1_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskRed_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskRed_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER1_diseng_sig1_MaskRed_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX0_CLUSTER1 - Cluster 1, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_X0_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_X0_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_X0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_X0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_X0_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_Y0_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_Y0_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_Y0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_Y0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER1_diseng_sig1_Y0_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX1_CLUSTER1 - Cluster 1, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_X1_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_X1_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_X1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_X1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_X1_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_Y1_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_Y1_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_Y1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_Y1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER1_diseng_sig1_Y1_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX2_CLUSTER1 - Cluster 1, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_X2_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_X2_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_X2_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_X2_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_X2_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_Y2_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_Y2_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_Y2_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_Y2_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER1_diseng_sig1_Y2_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX3_CLUSTER1 - Cluster 1, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_X3_Cluster1_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_X3_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_X3_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_X3_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_X3_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_Y3_Cluster1_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_Y3_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_Y3_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_Y3_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER1_diseng_sig1_Y3_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_REF0_CLUSTER1 - Cluster 1, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER1_diseng_sig1_Ref0_Cluster1_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER1_diseng_sig1_Ref0_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER1_diseng_sig1_Ref0_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER1_diseng_sig1_Ref0_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER1_diseng_sig1_Ref0_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_REF1_CLUSTER1 - Cluster 1, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER1_diseng_sig1_Ref1_Cluster1_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER1_diseng_sig1_Ref1_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER1_diseng_sig1_Ref1_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER1_diseng_sig1_Ref1_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER1_diseng_sig1_Ref1_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_CLUSTER2 - Cluster 2, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_En_Cluster2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_En_Cluster2_SHIFT (0U) /*! diseng_sig1_En_Cluster2 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix0_En_Cluster2_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix0_En_Cluster2_SHIFT (4U) /*! diseng_sig1_Pix0_En_Cluster2 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix0_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix0_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix0_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix1_En_Cluster2_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix1_En_Cluster2_SHIFT (5U) /*! diseng_sig1_Pix1_En_Cluster2 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix1_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix1_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix1_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix2_En_Cluster2_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix2_En_Cluster2_SHIFT (6U) /*! diseng_sig1_Pix2_En_Cluster2 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix2_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix2_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix2_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix3_En_Cluster2_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix3_En_Cluster2_SHIFT (7U) /*! diseng_sig1_Pix3_En_Cluster2 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix3_En_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix3_En_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_Pix3_En_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskBlue_Cluster2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskBlue_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskBlue_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskBlue_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskBlue_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskGreen_Cluster2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskGreen_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskGreen_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskGreen_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskGreen_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskRed_Cluster2_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskRed_Cluster2_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskRed_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskRed_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER2_diseng_sig1_MaskRed_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX0_CLUSTER2 - Cluster 2, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_X0_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_X0_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_X0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_X0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_X0_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_Y0_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_Y0_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_Y0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_Y0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER2_diseng_sig1_Y0_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX1_CLUSTER2 - Cluster 2, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_X1_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_X1_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_X1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_X1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_X1_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_Y1_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_Y1_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_Y1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_Y1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER2_diseng_sig1_Y1_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX2_CLUSTER2 - Cluster 2, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_X2_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_X2_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_X2_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_X2_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_X2_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_Y2_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_Y2_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_Y2_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_Y2_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER2_diseng_sig1_Y2_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX3_CLUSTER2 - Cluster 2, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_X3_Cluster2_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_X3_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_X3_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_X3_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_X3_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_Y3_Cluster2_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_Y3_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_Y3_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_Y3_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER2_diseng_sig1_Y3_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_REF0_CLUSTER2 - Cluster 2, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER2_diseng_sig1_Ref0_Cluster2_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER2_diseng_sig1_Ref0_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER2_diseng_sig1_Ref0_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER2_diseng_sig1_Ref0_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER2_diseng_sig1_Ref0_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_REF1_CLUSTER2 - Cluster 2, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER2_diseng_sig1_Ref1_Cluster2_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER2_diseng_sig1_Ref1_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER2_diseng_sig1_Ref1_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER2_diseng_sig1_Ref1_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER2_diseng_sig1_Ref1_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_CONTROL_CLUSTER3 - Cluster 3, Control settings */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_En_Cluster3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_En_Cluster3_SHIFT (0U) /*! diseng_sig1_En_Cluster3 * 0b0..Cluster is disabled and all Status flags are cleared * 0b1..Cluster is enabled and reference checking is executed */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix0_En_Cluster3_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix0_En_Cluster3_SHIFT (4U) /*! diseng_sig1_Pix0_En_Cluster3 * 0b0..Pixel 0 will not be evaluated * 0b1..Pixel 0 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix0_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix0_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix0_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix1_En_Cluster3_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix1_En_Cluster3_SHIFT (5U) /*! diseng_sig1_Pix1_En_Cluster3 * 0b0..Pixel 1 will not be evaluated * 0b1..Pixel 1 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix1_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix1_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix1_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix2_En_Cluster3_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix2_En_Cluster3_SHIFT (6U) /*! diseng_sig1_Pix2_En_Cluster3 * 0b0..Pixel 2 will not be evaluated * 0b1..Pixel 2 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix2_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix2_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix2_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix3_En_Cluster3_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix3_En_Cluster3_SHIFT (7U) /*! diseng_sig1_Pix3_En_Cluster3 * 0b0..Pixel 3 will not be evaluated * 0b1..Pixel 3 will be evaluated */ #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix3_En_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix3_En_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_Pix3_En_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskBlue_Cluster3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskBlue_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskBlue_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskBlue_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskBlue_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskGreen_Cluster3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskGreen_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskGreen_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskGreen_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskGreen_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskRed_Cluster3_MASK (0xFF000000U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskRed_Cluster3_SHIFT (24U) #define DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskRed_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskRed_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CONTROL_CLUSTER3_diseng_sig1_MaskRed_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX0_CLUSTER3 - Cluster 3, Coordinate of Pixel 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_X0_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_X0_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_X0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_X0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_X0_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_Y0_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_Y0_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_Y0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_Y0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX0_CLUSTER3_diseng_sig1_Y0_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX1_CLUSTER3 - Cluster 3, Coordinate of Pixel 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_X1_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_X1_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_X1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_X1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_X1_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_Y1_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_Y1_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_Y1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_Y1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX1_CLUSTER3_diseng_sig1_Y1_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX2_CLUSTER3 - Cluster 3, Coordinate of Pixel 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_X2_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_X2_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_X2_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_X2_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_X2_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_Y2_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_Y2_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_Y2_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_Y2_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX2_CLUSTER3_diseng_sig1_Y2_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIX3_CLUSTER3 - Cluster 3, Coordinate of Pixel 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_X3_Cluster3_MASK (0x3FFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_X3_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_X3_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_X3_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_X3_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_Y3_Cluster3_MASK (0x3FFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_Y3_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_Y3_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_Y3_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIX3_CLUSTER3_diseng_sig1_Y3_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_REF0_CLUSTER3 - Cluster 3, Reference Vector 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER3_diseng_sig1_Ref0_Cluster3_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER3_diseng_sig1_Ref0_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER3_diseng_sig1_Ref0_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER3_diseng_sig1_Ref0_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF0_CLUSTER3_diseng_sig1_Ref0_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_REF1_CLUSTER3 - Cluster 3, Reference Vector 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER3_diseng_sig1_Ref1_Cluster3_MASK (0xFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER3_diseng_sig1_Ref1_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER3_diseng_sig1_Ref1_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER3_diseng_sig1_Ref1_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REF1_CLUSTER3_diseng_sig1_Ref1_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW0 - Window 0, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW0_diseng_sig1_CRC_R_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW0_diseng_sig1_CRC_R_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW0_diseng_sig1_CRC_R_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW0_diseng_sig1_CRC_R_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW0_diseng_sig1_CRC_R_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW0 - Window 0, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW0_diseng_sig1_CRC_G_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW0_diseng_sig1_CRC_G_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW0_diseng_sig1_CRC_G_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW0_diseng_sig1_CRC_G_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW0_diseng_sig1_CRC_G_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW0 - Window 0, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW0_diseng_sig1_CRC_B_Window0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW0_diseng_sig1_CRC_B_Window0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW0_diseng_sig1_CRC_B_Window0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW0_diseng_sig1_CRC_B_Window0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW0_diseng_sig1_CRC_B_Window0_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW1 - Window 1, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW1_diseng_sig1_CRC_R_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW1_diseng_sig1_CRC_R_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW1_diseng_sig1_CRC_R_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW1_diseng_sig1_CRC_R_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW1_diseng_sig1_CRC_R_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW1 - Window 1, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW1_diseng_sig1_CRC_G_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW1_diseng_sig1_CRC_G_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW1_diseng_sig1_CRC_G_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW1_diseng_sig1_CRC_G_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW1_diseng_sig1_CRC_G_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW1 - Window 1, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW1_diseng_sig1_CRC_B_Window1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW1_diseng_sig1_CRC_B_Window1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW1_diseng_sig1_CRC_B_Window1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW1_diseng_sig1_CRC_B_Window1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW1_diseng_sig1_CRC_B_Window1_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW2 - Window 2, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW2_diseng_sig1_CRC_R_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW2_diseng_sig1_CRC_R_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW2_diseng_sig1_CRC_R_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW2_diseng_sig1_CRC_R_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW2_diseng_sig1_CRC_R_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW2 - Window 2, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW2_diseng_sig1_CRC_G_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW2_diseng_sig1_CRC_G_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW2_diseng_sig1_CRC_G_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW2_diseng_sig1_CRC_G_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW2_diseng_sig1_CRC_G_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW2 - Window 2, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW2_diseng_sig1_CRC_B_Window2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW2_diseng_sig1_CRC_B_Window2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW2_diseng_sig1_CRC_B_Window2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW2_diseng_sig1_CRC_B_Window2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW2_diseng_sig1_CRC_B_Window2_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW3 - Window 3, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW3_diseng_sig1_CRC_R_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW3_diseng_sig1_CRC_R_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW3_diseng_sig1_CRC_R_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW3_diseng_sig1_CRC_R_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW3_diseng_sig1_CRC_R_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW3 - Window 3, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW3_diseng_sig1_CRC_G_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW3_diseng_sig1_CRC_G_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW3_diseng_sig1_CRC_G_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW3_diseng_sig1_CRC_G_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW3_diseng_sig1_CRC_G_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW3 - Window 3, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW3_diseng_sig1_CRC_B_Window3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW3_diseng_sig1_CRC_B_Window3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW3_diseng_sig1_CRC_B_Window3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW3_diseng_sig1_CRC_B_Window3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW3_diseng_sig1_CRC_B_Window3_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW4 - Window 4, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW4_diseng_sig1_CRC_R_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW4_diseng_sig1_CRC_R_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW4_diseng_sig1_CRC_R_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW4_diseng_sig1_CRC_R_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW4_diseng_sig1_CRC_R_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW4 - Window 4, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW4_diseng_sig1_CRC_G_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW4_diseng_sig1_CRC_G_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW4_diseng_sig1_CRC_G_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW4_diseng_sig1_CRC_G_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW4_diseng_sig1_CRC_G_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW4 - Window 4, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW4_diseng_sig1_CRC_B_Window4_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW4_diseng_sig1_CRC_B_Window4_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW4_diseng_sig1_CRC_B_Window4(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW4_diseng_sig1_CRC_B_Window4_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW4_diseng_sig1_CRC_B_Window4_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW5 - Window 5, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW5_diseng_sig1_CRC_R_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW5_diseng_sig1_CRC_R_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW5_diseng_sig1_CRC_R_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW5_diseng_sig1_CRC_R_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW5_diseng_sig1_CRC_R_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW5 - Window 5, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW5_diseng_sig1_CRC_G_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW5_diseng_sig1_CRC_G_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW5_diseng_sig1_CRC_G_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW5_diseng_sig1_CRC_G_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW5_diseng_sig1_CRC_G_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW5 - Window 5, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW5_diseng_sig1_CRC_B_Window5_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW5_diseng_sig1_CRC_B_Window5_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW5_diseng_sig1_CRC_B_Window5(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW5_diseng_sig1_CRC_B_Window5_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW5_diseng_sig1_CRC_B_Window5_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW6 - Window 6, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW6_diseng_sig1_CRC_R_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW6_diseng_sig1_CRC_R_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW6_diseng_sig1_CRC_R_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW6_diseng_sig1_CRC_R_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW6_diseng_sig1_CRC_R_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW6 - Window 6, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW6_diseng_sig1_CRC_G_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW6_diseng_sig1_CRC_G_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW6_diseng_sig1_CRC_G_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW6_diseng_sig1_CRC_G_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW6_diseng_sig1_CRC_G_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW6 - Window 6, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW6_diseng_sig1_CRC_B_Window6_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW6_diseng_sig1_CRC_B_Window6_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW6_diseng_sig1_CRC_B_Window6(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW6_diseng_sig1_CRC_B_Window6_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW6_diseng_sig1_CRC_B_Window6_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_R_WINDOW7 - Window 7, Measured CRC Value of Red Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW7_diseng_sig1_CRC_R_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW7_diseng_sig1_CRC_R_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW7_diseng_sig1_CRC_R_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW7_diseng_sig1_CRC_R_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_R_WINDOW7_diseng_sig1_CRC_R_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_G_WINDOW7 - Window 7, Measured CRC Value of Green Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW7_diseng_sig1_CRC_G_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW7_diseng_sig1_CRC_G_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW7_diseng_sig1_CRC_G_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW7_diseng_sig1_CRC_G_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_G_WINDOW7_diseng_sig1_CRC_G_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_CRC_B_WINDOW7 - Window 7, Measured CRC Value of Blue Channel */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW7_diseng_sig1_CRC_B_Window7_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW7_diseng_sig1_CRC_B_Window7_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW7_diseng_sig1_CRC_B_Window7(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW7_diseng_sig1_CRC_B_Window7_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_CRC_B_WINDOW7_diseng_sig1_CRC_B_Window7_MASK) /*! @} */ /*! @name DISENG_SIG1_STATUS_CLUSTER0 - Cluster 0, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts00_Cluster0_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts00_Cluster0_SHIFT (0U) /*! diseng_sig1_Sts00_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts00_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts00_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts00_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts01_Cluster0_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts01_Cluster0_SHIFT (1U) /*! diseng_sig1_Sts01_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts01_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts01_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts01_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts10_Cluster0_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts10_Cluster0_SHIFT (2U) /*! diseng_sig1_Sts10_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts11_Cluster0_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts11_Cluster0_SHIFT (3U) /*! diseng_sig1_Sts11_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts11_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts11_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts11_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts20_Cluster0_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts20_Cluster0_SHIFT (4U) /*! diseng_sig1_Sts20_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts20_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts20_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts20_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts21_Cluster0_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts21_Cluster0_SHIFT (5U) /*! diseng_sig1_Sts21_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts21_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts21_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts21_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts30_Cluster0_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts30_Cluster0_SHIFT (6U) /*! diseng_sig1_Sts30_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts30_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts30_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts30_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts31_Cluster0_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts31_Cluster0_SHIFT (7U) /*! diseng_sig1_Sts31_Cluster0 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts31_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts31_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER0_diseng_sig1_Sts31_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_COUNTER_CLUSTER0 - Cluster 0, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_MatchCount_Cluster0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_MatchCount_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_MatchCount_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_MatchCount_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_MatchCount_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_ErrorCount_Cluster0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_ErrorCount_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_ErrorCount_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_ErrorCount_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER0_diseng_sig1_ErrorCount_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR0_CLUSTER0 - Cluster 0, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_B10_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_B10_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_G10_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_G10_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_R10_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_R10_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix0_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_B10_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_B10_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_G10_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_G10_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_R10_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_R10_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix1_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_B10_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_B10_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_G10_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_G10_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_R10_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_R10_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix2_R10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_B10_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_B10_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_B10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_B10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_B10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_G10_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_G10_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_G10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_G10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_G10_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_R10_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_R10_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_R10_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_R10_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER0_diseng_sig1_Pix3_R10_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR1_CLUSTER0 - Cluster 0, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_B32_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_B32_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_G32_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_G32_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_R32_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_R32_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix0_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_B32_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_B32_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_G32_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_G32_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_R32_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_R32_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix1_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_B32_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_B32_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_G32_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_G32_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_R32_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_R32_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix2_R32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_B32_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_B32_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_B32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_B32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_B32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_G32_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_G32_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_G32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_G32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_G32_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_R32_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_R32_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_R32_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_R32_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER0_diseng_sig1_Pix3_R32_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR2_CLUSTER0 - Cluster 0, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_B54_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_B54_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_G54_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_G54_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_R54_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_R54_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix0_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_B54_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_B54_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_G54_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_G54_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_R54_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_R54_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix1_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_B54_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_B54_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_G54_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_G54_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_R54_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_R54_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix2_R54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_B54_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_B54_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_B54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_B54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_B54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_G54_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_G54_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_G54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_G54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_G54_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_R54_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_R54_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_R54_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_R54_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER0_diseng_sig1_Pix3_R54_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR3_CLUSTER0 - Cluster 0, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_B76_Cluster0_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_B76_Cluster0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_G76_Cluster0_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_G76_Cluster0_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_R76_Cluster0_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_R76_Cluster0_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix0_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_B76_Cluster0_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_B76_Cluster0_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_G76_Cluster0_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_G76_Cluster0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_R76_Cluster0_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_R76_Cluster0_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix1_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_B76_Cluster0_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_B76_Cluster0_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_G76_Cluster0_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_G76_Cluster0_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_R76_Cluster0_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_R76_Cluster0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix2_R76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_B76_Cluster0_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_B76_Cluster0_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_B76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_B76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_B76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_G76_Cluster0_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_G76_Cluster0_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_G76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_G76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_G76_Cluster0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_R76_Cluster0_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_R76_Cluster0_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_R76_Cluster0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_R76_Cluster0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER0_diseng_sig1_Pix3_R76_Cluster0_MASK) /*! @} */ /*! @name DISENG_SIG1_STATUS_CLUSTER1 - Cluster 1, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts00_Cluster1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts00_Cluster1_SHIFT (0U) /*! diseng_sig1_Sts00_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts00_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts00_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts00_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts01_Cluster1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts01_Cluster1_SHIFT (1U) /*! diseng_sig1_Sts01_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts01_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts01_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts01_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts10_Cluster1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts10_Cluster1_SHIFT (2U) /*! diseng_sig1_Sts10_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts11_Cluster1_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts11_Cluster1_SHIFT (3U) /*! diseng_sig1_Sts11_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts11_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts11_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts11_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts20_Cluster1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts20_Cluster1_SHIFT (4U) /*! diseng_sig1_Sts20_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts20_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts20_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts20_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts21_Cluster1_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts21_Cluster1_SHIFT (5U) /*! diseng_sig1_Sts21_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts21_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts21_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts21_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts30_Cluster1_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts30_Cluster1_SHIFT (6U) /*! diseng_sig1_Sts30_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts30_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts30_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts30_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts31_Cluster1_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts31_Cluster1_SHIFT (7U) /*! diseng_sig1_Sts31_Cluster1 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts31_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts31_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER1_diseng_sig1_Sts31_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_COUNTER_CLUSTER1 - Cluster 1, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_MatchCount_Cluster1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_MatchCount_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_MatchCount_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_MatchCount_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_MatchCount_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_ErrorCount_Cluster1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_ErrorCount_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_ErrorCount_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_ErrorCount_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER1_diseng_sig1_ErrorCount_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR0_CLUSTER1 - Cluster 1, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_B10_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_B10_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_G10_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_G10_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_R10_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_R10_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix0_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_B10_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_B10_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_G10_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_G10_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_R10_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_R10_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix1_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_B10_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_B10_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_G10_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_G10_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_R10_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_R10_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix2_R10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_B10_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_B10_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_B10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_B10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_B10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_G10_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_G10_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_G10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_G10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_G10_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_R10_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_R10_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_R10_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_R10_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER1_diseng_sig1_Pix3_R10_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR1_CLUSTER1 - Cluster 1, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_B32_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_B32_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_G32_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_G32_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_R32_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_R32_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix0_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_B32_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_B32_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_G32_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_G32_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_R32_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_R32_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix1_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_B32_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_B32_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_G32_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_G32_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_R32_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_R32_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix2_R32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_B32_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_B32_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_B32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_B32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_B32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_G32_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_G32_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_G32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_G32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_G32_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_R32_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_R32_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_R32_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_R32_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER1_diseng_sig1_Pix3_R32_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR2_CLUSTER1 - Cluster 1, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_B54_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_B54_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_G54_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_G54_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_R54_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_R54_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix0_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_B54_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_B54_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_G54_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_G54_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_R54_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_R54_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix1_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_B54_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_B54_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_G54_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_G54_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_R54_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_R54_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix2_R54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_B54_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_B54_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_B54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_B54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_B54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_G54_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_G54_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_G54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_G54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_G54_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_R54_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_R54_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_R54_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_R54_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER1_diseng_sig1_Pix3_R54_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR3_CLUSTER1 - Cluster 1, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_B76_Cluster1_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_B76_Cluster1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_G76_Cluster1_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_G76_Cluster1_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_R76_Cluster1_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_R76_Cluster1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix0_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_B76_Cluster1_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_B76_Cluster1_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_G76_Cluster1_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_G76_Cluster1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_R76_Cluster1_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_R76_Cluster1_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix1_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_B76_Cluster1_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_B76_Cluster1_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_G76_Cluster1_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_G76_Cluster1_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_R76_Cluster1_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_R76_Cluster1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix2_R76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_B76_Cluster1_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_B76_Cluster1_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_B76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_B76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_B76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_G76_Cluster1_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_G76_Cluster1_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_G76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_G76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_G76_Cluster1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_R76_Cluster1_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_R76_Cluster1_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_R76_Cluster1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_R76_Cluster1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER1_diseng_sig1_Pix3_R76_Cluster1_MASK) /*! @} */ /*! @name DISENG_SIG1_STATUS_CLUSTER2 - Cluster 2, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts00_Cluster2_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts00_Cluster2_SHIFT (0U) /*! diseng_sig1_Sts00_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts00_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts00_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts00_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts01_Cluster2_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts01_Cluster2_SHIFT (1U) /*! diseng_sig1_Sts01_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts01_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts01_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts01_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts10_Cluster2_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts10_Cluster2_SHIFT (2U) /*! diseng_sig1_Sts10_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts11_Cluster2_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts11_Cluster2_SHIFT (3U) /*! diseng_sig1_Sts11_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts11_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts11_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts11_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts20_Cluster2_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts20_Cluster2_SHIFT (4U) /*! diseng_sig1_Sts20_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts20_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts20_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts20_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts21_Cluster2_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts21_Cluster2_SHIFT (5U) /*! diseng_sig1_Sts21_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts21_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts21_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts21_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts30_Cluster2_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts30_Cluster2_SHIFT (6U) /*! diseng_sig1_Sts30_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts30_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts30_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts30_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts31_Cluster2_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts31_Cluster2_SHIFT (7U) /*! diseng_sig1_Sts31_Cluster2 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts31_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts31_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER2_diseng_sig1_Sts31_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_COUNTER_CLUSTER2 - Cluster 2, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_MatchCount_Cluster2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_MatchCount_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_MatchCount_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_MatchCount_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_MatchCount_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_ErrorCount_Cluster2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_ErrorCount_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_ErrorCount_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_ErrorCount_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER2_diseng_sig1_ErrorCount_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR0_CLUSTER2 - Cluster 2, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_B10_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_B10_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_G10_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_G10_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_R10_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_R10_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix0_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_B10_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_B10_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_G10_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_G10_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_R10_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_R10_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix1_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_B10_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_B10_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_G10_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_G10_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_R10_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_R10_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix2_R10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_B10_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_B10_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_B10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_B10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_B10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_G10_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_G10_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_G10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_G10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_G10_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_R10_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_R10_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_R10_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_R10_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER2_diseng_sig1_Pix3_R10_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR1_CLUSTER2 - Cluster 2, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_B32_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_B32_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_G32_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_G32_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_R32_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_R32_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix0_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_B32_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_B32_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_G32_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_G32_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_R32_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_R32_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix1_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_B32_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_B32_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_G32_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_G32_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_R32_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_R32_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix2_R32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_B32_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_B32_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_B32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_B32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_B32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_G32_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_G32_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_G32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_G32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_G32_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_R32_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_R32_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_R32_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_R32_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER2_diseng_sig1_Pix3_R32_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR2_CLUSTER2 - Cluster 2, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_B54_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_B54_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_G54_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_G54_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_R54_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_R54_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix0_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_B54_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_B54_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_G54_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_G54_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_R54_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_R54_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix1_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_B54_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_B54_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_G54_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_G54_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_R54_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_R54_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix2_R54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_B54_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_B54_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_B54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_B54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_B54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_G54_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_G54_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_G54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_G54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_G54_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_R54_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_R54_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_R54_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_R54_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER2_diseng_sig1_Pix3_R54_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR3_CLUSTER2 - Cluster 2, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_B76_Cluster2_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_B76_Cluster2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_G76_Cluster2_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_G76_Cluster2_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_R76_Cluster2_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_R76_Cluster2_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix0_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_B76_Cluster2_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_B76_Cluster2_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_G76_Cluster2_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_G76_Cluster2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_R76_Cluster2_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_R76_Cluster2_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix1_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_B76_Cluster2_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_B76_Cluster2_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_G76_Cluster2_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_G76_Cluster2_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_R76_Cluster2_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_R76_Cluster2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix2_R76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_B76_Cluster2_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_B76_Cluster2_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_B76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_B76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_B76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_G76_Cluster2_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_G76_Cluster2_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_G76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_G76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_G76_Cluster2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_R76_Cluster2_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_R76_Cluster2_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_R76_Cluster2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_R76_Cluster2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER2_diseng_sig1_Pix3_R76_Cluster2_MASK) /*! @} */ /*! @name DISENG_SIG1_STATUS_CLUSTER3 - Cluster 3, Status */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts00_Cluster3_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts00_Cluster3_SHIFT (0U) /*! diseng_sig1_Sts00_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts00_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts00_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts00_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts01_Cluster3_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts01_Cluster3_SHIFT (1U) /*! diseng_sig1_Sts01_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts01_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts01_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts01_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts10_Cluster3_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts10_Cluster3_SHIFT (2U) /*! diseng_sig1_Sts10_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts11_Cluster3_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts11_Cluster3_SHIFT (3U) /*! diseng_sig1_Sts11_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts11_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts11_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts11_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts20_Cluster3_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts20_Cluster3_SHIFT (4U) /*! diseng_sig1_Sts20_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts20_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts20_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts20_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts21_Cluster3_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts21_Cluster3_SHIFT (5U) /*! diseng_sig1_Sts21_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts21_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts21_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts21_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts30_Cluster3_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts30_Cluster3_SHIFT (6U) /*! diseng_sig1_Sts30_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts30_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts30_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts30_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts31_Cluster3_MASK (0x80U) #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts31_Cluster3_SHIFT (7U) /*! diseng_sig1_Sts31_Cluster3 * 0b0..Measurement value and reference are equal * 0b1..Measurement value and reference are not equal */ #define DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts31_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts31_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_STATUS_CLUSTER3_diseng_sig1_Sts31_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_COUNTER_CLUSTER3 - Cluster 3, Match and Error Counters */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_MatchCount_Cluster3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_MatchCount_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_MatchCount_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_MatchCount_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_MatchCount_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_ErrorCount_Cluster3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_ErrorCount_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_ErrorCount_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_ErrorCount_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_COUNTER_CLUSTER3_diseng_sig1_ErrorCount_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR0_CLUSTER3 - Cluster 3, Result Vector 0, RGB bitslices[1:0] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_B10_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_B10_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_G10_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_G10_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_R10_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_R10_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix0_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_B10_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_B10_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_G10_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_G10_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_R10_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_R10_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix1_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_B10_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_B10_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_G10_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_G10_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_R10_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_R10_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix2_R10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_B10_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_B10_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_B10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_B10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_B10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_G10_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_G10_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_G10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_G10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_G10_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_R10_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_R10_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_R10_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_R10_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR0_CLUSTER3_diseng_sig1_Pix3_R10_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR1_CLUSTER3 - Cluster 3, Result Vector 1, RGB bitslices[3:2] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_B32_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_B32_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_G32_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_G32_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_R32_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_R32_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix0_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_B32_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_B32_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_G32_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_G32_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_R32_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_R32_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix1_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_B32_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_B32_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_G32_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_G32_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_R32_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_R32_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix2_R32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_B32_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_B32_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_B32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_B32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_B32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_G32_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_G32_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_G32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_G32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_G32_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_R32_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_R32_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_R32_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_R32_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR1_CLUSTER3_diseng_sig1_Pix3_R32_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR2_CLUSTER3 - Cluster 3, Result Vector 2, RGB bitslices[5:4] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_B54_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_B54_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_G54_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_G54_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_R54_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_R54_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix0_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_B54_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_B54_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_G54_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_G54_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_R54_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_R54_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix1_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_B54_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_B54_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_G54_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_G54_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_R54_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_R54_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix2_R54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_B54_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_B54_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_B54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_B54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_B54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_G54_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_G54_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_G54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_G54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_G54_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_R54_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_R54_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_R54_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_R54_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR2_CLUSTER3_diseng_sig1_Pix3_R54_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_VECTOR3_CLUSTER3 - Cluster 3, Result Vector 3, RGB bitslices[7:6] */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_B76_Cluster3_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_B76_Cluster3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_G76_Cluster3_MASK (0xCU) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_G76_Cluster3_SHIFT (2U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_R76_Cluster3_MASK (0x30U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_R76_Cluster3_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix0_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_B76_Cluster3_MASK (0xC0U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_B76_Cluster3_SHIFT (6U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_G76_Cluster3_MASK (0x300U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_G76_Cluster3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_R76_Cluster3_MASK (0xC00U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_R76_Cluster3_SHIFT (10U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix1_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_B76_Cluster3_MASK (0x3000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_B76_Cluster3_SHIFT (12U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_G76_Cluster3_MASK (0xC000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_G76_Cluster3_SHIFT (14U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_R76_Cluster3_MASK (0x30000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_R76_Cluster3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix2_R76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_B76_Cluster3_MASK (0xC0000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_B76_Cluster3_SHIFT (18U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_B76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_B76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_B76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_G76_Cluster3_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_G76_Cluster3_SHIFT (20U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_G76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_G76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_G76_Cluster3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_R76_Cluster3_MASK (0xC00000U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_R76_Cluster3_SHIFT (22U) #define DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_R76_Cluster3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_R76_Cluster3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_VECTOR3_CLUSTER3_diseng_sig1_Pix3_R76_Cluster3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS0_WIN0 - Pixel Counter Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN0_diseng_sig1_Px_Cnt_S0_Win0_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN0_diseng_sig1_Px_Cnt_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN0_diseng_sig1_Px_Cnt_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN0_diseng_sig1_Px_Cnt_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN0_diseng_sig1_Px_Cnt_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS0_WIN0 - Pixel Max Values Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Bl_Max_S0_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Bl_Max_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Bl_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Bl_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Bl_Max_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Gn_Max_S0_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Gn_Max_S0_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Gn_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Gn_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Gn_Max_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Rd_Max_S0_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Rd_Max_S0_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Rd_Max_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Rd_Max_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN0_diseng_sig1_Rd_Max_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS0_WIN0 - Pixel Min Values Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Bl_Min_S0_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Bl_Min_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Bl_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Bl_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Bl_Min_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Gn_Min_S0_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Gn_Min_S0_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Gn_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Gn_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Gn_Min_S0_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Rd_Min_S0_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Rd_Min_S0_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Rd_Min_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Rd_Min_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN0_diseng_sig1_Rd_Min_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS0_WIN0 - Red Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN0_diseng_sig1_Rd_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN0_diseng_sig1_Rd_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN0_diseng_sig1_Rd_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN0_diseng_sig1_Rd_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN0_diseng_sig1_Rd_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS0_WIN0 - Green Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN0_diseng_sig1_Gn_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN0_diseng_sig1_Gn_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN0_diseng_sig1_Gn_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN0_diseng_sig1_Gn_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN0_diseng_sig1_Gn_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS0_WIN0 - Blue Component Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN0_diseng_sig1_Bl_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN0_diseng_sig1_Bl_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN0_diseng_sig1_Bl_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN0_diseng_sig1_Bl_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN0_diseng_sig1_Bl_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_LUMSUM_STATS0_WIN0 - Luminance Sum Register, Statistics Block 0, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN0_diseng_sig1_Lm_Sum_S0_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN0_diseng_sig1_Lm_Sum_S0_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN0_diseng_sig1_Lm_Sum_S0_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN0_diseng_sig1_Lm_Sum_S0_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN0_diseng_sig1_Lm_Sum_S0_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS1_WIN0 - Pixel Counter Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN0_diseng_sig1_Px_Cnt_S1_Win0_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN0_diseng_sig1_Px_Cnt_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN0_diseng_sig1_Px_Cnt_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN0_diseng_sig1_Px_Cnt_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN0_diseng_sig1_Px_Cnt_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS1_WIN0 - Pixel Max Values Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Bl_Max_S1_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Bl_Max_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Bl_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Bl_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Bl_Max_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Gn_Max_S1_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Gn_Max_S1_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Gn_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Gn_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Gn_Max_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Rd_Max_S1_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Rd_Max_S1_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Rd_Max_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Rd_Max_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN0_diseng_sig1_Rd_Max_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS1_WIN0 - Pixel Min Values Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Bl_Min_S1_Win0_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Bl_Min_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Bl_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Bl_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Bl_Min_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Gn_Min_S1_Win0_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Gn_Min_S1_Win0_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Gn_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Gn_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Gn_Min_S1_Win0_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Rd_Min_S1_Win0_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Rd_Min_S1_Win0_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Rd_Min_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Rd_Min_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN0_diseng_sig1_Rd_Min_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS1_WIN0 - Red Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN0_diseng_sig1_Rd_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN0_diseng_sig1_Rd_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN0_diseng_sig1_Rd_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN0_diseng_sig1_Rd_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN0_diseng_sig1_Rd_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS1_WIN0 - Green Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN0_diseng_sig1_Gn_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN0_diseng_sig1_Gn_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN0_diseng_sig1_Gn_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN0_diseng_sig1_Gn_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN0_diseng_sig1_Gn_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS1_WIN0 - Blue Component Sum Register, Statistics Block 1, Window 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN0_diseng_sig1_Bl_Sum_S1_Win0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN0_diseng_sig1_Bl_Sum_S1_Win0_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN0_diseng_sig1_Bl_Sum_S1_Win0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN0_diseng_sig1_Bl_Sum_S1_Win0_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN0_diseng_sig1_Bl_Sum_S1_Win0_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS0_WIN1 - Pixel Counter Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN1_diseng_sig1_Px_Cnt_S0_Win1_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN1_diseng_sig1_Px_Cnt_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN1_diseng_sig1_Px_Cnt_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN1_diseng_sig1_Px_Cnt_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN1_diseng_sig1_Px_Cnt_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS0_WIN1 - Pixel Max Values Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Bl_Max_S0_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Bl_Max_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Bl_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Bl_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Bl_Max_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Gn_Max_S0_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Gn_Max_S0_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Gn_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Gn_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Gn_Max_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Rd_Max_S0_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Rd_Max_S0_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Rd_Max_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Rd_Max_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN1_diseng_sig1_Rd_Max_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS0_WIN1 - Pixel Min Values Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Bl_Min_S0_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Bl_Min_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Bl_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Bl_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Bl_Min_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Gn_Min_S0_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Gn_Min_S0_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Gn_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Gn_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Gn_Min_S0_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Rd_Min_S0_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Rd_Min_S0_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Rd_Min_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Rd_Min_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN1_diseng_sig1_Rd_Min_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS0_WIN1 - Red Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN1_diseng_sig1_Rd_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN1_diseng_sig1_Rd_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN1_diseng_sig1_Rd_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN1_diseng_sig1_Rd_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN1_diseng_sig1_Rd_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS0_WIN1 - Green Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN1_diseng_sig1_Gn_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN1_diseng_sig1_Gn_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN1_diseng_sig1_Gn_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN1_diseng_sig1_Gn_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN1_diseng_sig1_Gn_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS0_WIN1 - Blue Component Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN1_diseng_sig1_Bl_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN1_diseng_sig1_Bl_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN1_diseng_sig1_Bl_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN1_diseng_sig1_Bl_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN1_diseng_sig1_Bl_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_LUMSUM_STATS0_WIN1 - Luminance Sum Register, Statistics Block 0, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN1_diseng_sig1_Lm_Sum_S0_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN1_diseng_sig1_Lm_Sum_S0_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN1_diseng_sig1_Lm_Sum_S0_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN1_diseng_sig1_Lm_Sum_S0_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN1_diseng_sig1_Lm_Sum_S0_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS1_WIN1 - Pixel Counter Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN1_diseng_sig1_Px_Cnt_S1_Win1_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN1_diseng_sig1_Px_Cnt_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN1_diseng_sig1_Px_Cnt_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN1_diseng_sig1_Px_Cnt_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN1_diseng_sig1_Px_Cnt_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS1_WIN1 - Pixel Max Values Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Bl_Max_S1_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Bl_Max_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Bl_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Bl_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Bl_Max_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Gn_Max_S1_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Gn_Max_S1_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Gn_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Gn_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Gn_Max_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Rd_Max_S1_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Rd_Max_S1_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Rd_Max_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Rd_Max_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN1_diseng_sig1_Rd_Max_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS1_WIN1 - Pixel Min Values Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Bl_Min_S1_Win1_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Bl_Min_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Bl_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Bl_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Bl_Min_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Gn_Min_S1_Win1_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Gn_Min_S1_Win1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Gn_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Gn_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Gn_Min_S1_Win1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Rd_Min_S1_Win1_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Rd_Min_S1_Win1_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Rd_Min_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Rd_Min_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN1_diseng_sig1_Rd_Min_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS1_WIN1 - Red Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN1_diseng_sig1_Rd_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN1_diseng_sig1_Rd_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN1_diseng_sig1_Rd_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN1_diseng_sig1_Rd_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN1_diseng_sig1_Rd_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS1_WIN1 - Green Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN1_diseng_sig1_Gn_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN1_diseng_sig1_Gn_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN1_diseng_sig1_Gn_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN1_diseng_sig1_Gn_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN1_diseng_sig1_Gn_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS1_WIN1 - Blue Component Sum Register, Statistics Block 1, Window 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN1_diseng_sig1_Bl_Sum_S1_Win1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN1_diseng_sig1_Bl_Sum_S1_Win1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN1_diseng_sig1_Bl_Sum_S1_Win1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN1_diseng_sig1_Bl_Sum_S1_Win1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN1_diseng_sig1_Bl_Sum_S1_Win1_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS0_WIN2 - Pixel Counter Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN2_diseng_sig1_Px_Cnt_S0_Win2_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN2_diseng_sig1_Px_Cnt_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN2_diseng_sig1_Px_Cnt_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN2_diseng_sig1_Px_Cnt_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN2_diseng_sig1_Px_Cnt_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS0_WIN2 - Pixel Max Values Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Bl_Max_S0_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Bl_Max_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Bl_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Bl_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Bl_Max_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Gn_Max_S0_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Gn_Max_S0_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Gn_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Gn_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Gn_Max_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Rd_Max_S0_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Rd_Max_S0_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Rd_Max_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Rd_Max_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN2_diseng_sig1_Rd_Max_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS0_WIN2 - Pixel Min Values Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Bl_Min_S0_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Bl_Min_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Bl_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Bl_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Bl_Min_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Gn_Min_S0_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Gn_Min_S0_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Gn_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Gn_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Gn_Min_S0_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Rd_Min_S0_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Rd_Min_S0_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Rd_Min_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Rd_Min_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN2_diseng_sig1_Rd_Min_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS0_WIN2 - Red Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN2_diseng_sig1_Rd_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN2_diseng_sig1_Rd_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN2_diseng_sig1_Rd_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN2_diseng_sig1_Rd_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN2_diseng_sig1_Rd_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS0_WIN2 - Green Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN2_diseng_sig1_Gn_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN2_diseng_sig1_Gn_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN2_diseng_sig1_Gn_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN2_diseng_sig1_Gn_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN2_diseng_sig1_Gn_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS0_WIN2 - Blue Component Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN2_diseng_sig1_Bl_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN2_diseng_sig1_Bl_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN2_diseng_sig1_Bl_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN2_diseng_sig1_Bl_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN2_diseng_sig1_Bl_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_LUMSUM_STATS0_WIN2 - Luminance Sum Register, Statistics Block 0, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN2_diseng_sig1_Lm_Sum_S0_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN2_diseng_sig1_Lm_Sum_S0_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN2_diseng_sig1_Lm_Sum_S0_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN2_diseng_sig1_Lm_Sum_S0_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN2_diseng_sig1_Lm_Sum_S0_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS1_WIN2 - Pixel Counter Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN2_diseng_sig1_Px_Cnt_S1_Win2_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN2_diseng_sig1_Px_Cnt_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN2_diseng_sig1_Px_Cnt_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN2_diseng_sig1_Px_Cnt_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN2_diseng_sig1_Px_Cnt_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS1_WIN2 - Pixel Max Values Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Bl_Max_S1_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Bl_Max_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Bl_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Bl_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Bl_Max_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Gn_Max_S1_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Gn_Max_S1_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Gn_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Gn_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Gn_Max_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Rd_Max_S1_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Rd_Max_S1_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Rd_Max_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Rd_Max_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN2_diseng_sig1_Rd_Max_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS1_WIN2 - Pixel Min Values Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Bl_Min_S1_Win2_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Bl_Min_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Bl_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Bl_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Bl_Min_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Gn_Min_S1_Win2_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Gn_Min_S1_Win2_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Gn_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Gn_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Gn_Min_S1_Win2_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Rd_Min_S1_Win2_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Rd_Min_S1_Win2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Rd_Min_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Rd_Min_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN2_diseng_sig1_Rd_Min_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS1_WIN2 - Red Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN2_diseng_sig1_Rd_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN2_diseng_sig1_Rd_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN2_diseng_sig1_Rd_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN2_diseng_sig1_Rd_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN2_diseng_sig1_Rd_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS1_WIN2 - Green Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN2_diseng_sig1_Gn_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN2_diseng_sig1_Gn_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN2_diseng_sig1_Gn_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN2_diseng_sig1_Gn_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN2_diseng_sig1_Gn_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS1_WIN2 - Blue Component Sum Register, Statistics Block 1, Window 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN2_diseng_sig1_Bl_Sum_S1_Win2_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN2_diseng_sig1_Bl_Sum_S1_Win2_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN2_diseng_sig1_Bl_Sum_S1_Win2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN2_diseng_sig1_Bl_Sum_S1_Win2_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN2_diseng_sig1_Bl_Sum_S1_Win2_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS0_WIN3 - Pixel Counter Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN3_diseng_sig1_Px_Cnt_S0_Win3_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN3_diseng_sig1_Px_Cnt_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN3_diseng_sig1_Px_Cnt_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN3_diseng_sig1_Px_Cnt_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS0_WIN3_diseng_sig1_Px_Cnt_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS0_WIN3 - Pixel Max Values Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Bl_Max_S0_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Bl_Max_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Bl_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Bl_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Bl_Max_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Gn_Max_S0_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Gn_Max_S0_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Gn_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Gn_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Gn_Max_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Rd_Max_S0_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Rd_Max_S0_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Rd_Max_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Rd_Max_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS0_WIN3_diseng_sig1_Rd_Max_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS0_WIN3 - Pixel Min Values Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Bl_Min_S0_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Bl_Min_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Bl_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Bl_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Bl_Min_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Gn_Min_S0_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Gn_Min_S0_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Gn_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Gn_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Gn_Min_S0_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Rd_Min_S0_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Rd_Min_S0_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Rd_Min_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Rd_Min_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS0_WIN3_diseng_sig1_Rd_Min_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS0_WIN3 - Red Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN3_diseng_sig1_Rd_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN3_diseng_sig1_Rd_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN3_diseng_sig1_Rd_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN3_diseng_sig1_Rd_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS0_WIN3_diseng_sig1_Rd_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS0_WIN3 - Green Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN3_diseng_sig1_Gn_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN3_diseng_sig1_Gn_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN3_diseng_sig1_Gn_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN3_diseng_sig1_Gn_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS0_WIN3_diseng_sig1_Gn_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS0_WIN3 - Blue Component Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN3_diseng_sig1_Bl_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN3_diseng_sig1_Bl_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN3_diseng_sig1_Bl_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN3_diseng_sig1_Bl_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS0_WIN3_diseng_sig1_Bl_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_LUMSUM_STATS0_WIN3 - Luminance Sum Register, Statistics Block 0, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN3_diseng_sig1_Lm_Sum_S0_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN3_diseng_sig1_Lm_Sum_S0_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN3_diseng_sig1_Lm_Sum_S0_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN3_diseng_sig1_Lm_Sum_S0_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_LUMSUM_STATS0_WIN3_diseng_sig1_Lm_Sum_S0_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXCNT_STATS1_WIN3 - Pixel Counter Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN3_diseng_sig1_Px_Cnt_S1_Win3_MASK (0xFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN3_diseng_sig1_Px_Cnt_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN3_diseng_sig1_Px_Cnt_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN3_diseng_sig1_Px_Cnt_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXCNT_STATS1_WIN3_diseng_sig1_Px_Cnt_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMAX_STATS1_WIN3 - Pixel Max Values Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Bl_Max_S1_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Bl_Max_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Bl_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Bl_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Bl_Max_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Gn_Max_S1_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Gn_Max_S1_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Gn_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Gn_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Gn_Max_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Rd_Max_S1_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Rd_Max_S1_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Rd_Max_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Rd_Max_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMAX_STATS1_WIN3_diseng_sig1_Rd_Max_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_PIXMIN_STATS1_WIN3 - Pixel Min Values Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Bl_Min_S1_Win3_MASK (0xFFU) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Bl_Min_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Bl_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Bl_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Bl_Min_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Gn_Min_S1_Win3_MASK (0xFF00U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Gn_Min_S1_Win3_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Gn_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Gn_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Gn_Min_S1_Win3_MASK) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Rd_Min_S1_Win3_MASK (0xFF0000U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Rd_Min_S1_Win3_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Rd_Min_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Rd_Min_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_PIXMIN_STATS1_WIN3_diseng_sig1_Rd_Min_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_REDSUM_STATS1_WIN3 - Red Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN3_diseng_sig1_Rd_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN3_diseng_sig1_Rd_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN3_diseng_sig1_Rd_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN3_diseng_sig1_Rd_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_REDSUM_STATS1_WIN3_diseng_sig1_Rd_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_GREENSUM_STATS1_WIN3 - Green Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN3_diseng_sig1_Gn_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN3_diseng_sig1_Gn_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN3_diseng_sig1_Gn_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN3_diseng_sig1_Gn_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_GREENSUM_STATS1_WIN3_diseng_sig1_Gn_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1_BLUESUM_STATS1_WIN3 - Blue Component Sum Register, Statistics Block 1, Window 3 */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN3_diseng_sig1_Bl_Sum_S1_Win3_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN3_diseng_sig1_Bl_Sum_S1_Win3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN3_diseng_sig1_Bl_Sum_S1_Win3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN3_diseng_sig1_Bl_Sum_S1_Win3_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1_BLUESUM_STATS1_WIN3_diseng_sig1_Bl_Sum_S1_Win3_MASK) /*! @} */ /*! @name DISENG_SIG1CFG_LOCKUNLOCK1 - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKUNLOCK1_diseng_sig1cfg_LockUnlock1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKUNLOCK1_diseng_sig1cfg_LockUnlock1_SHIFT (0U) /*! diseng_sig1cfg_LockUnlock1 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKUNLOCK1_diseng_sig1cfg_LockUnlock1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKUNLOCK1_diseng_sig1cfg_LockUnlock1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKUNLOCK1_diseng_sig1cfg_LockUnlock1_MASK) /*! @} */ /*! @name DISENG_SIG1CFG_LOCKSTATUS1 - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_LockStatus1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_LockStatus1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_LockStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_LockStatus1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_LockStatus1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_PrivilegeStatus1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_PrivilegeStatus1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_PrivilegeStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_PrivilegeStatus1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_PrivilegeStatus1_MASK) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_FreezeStatus1_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_FreezeStatus1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_FreezeStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_FreezeStatus1_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1CFG_LOCKSTATUS1_diseng_sig1cfg_FreezeStatus1_MASK) /*! @} */ /*! @name DISENG_SIG1CFG_SRCSELECT - Tap selection for Signature1. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_SIG1CFG_SRCSELECT_diseng_sig1cfg_sig1_select_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_SIG1CFG_SRCSELECT_diseng_sig1cfg_sig1_select_SHIFT (0U) /*! diseng_sig1cfg_sig1_select * 0b00..Source is FrameGen#1 output. * 0b01..Source is Matrix#1 output. * 0b10..Source is LuT3D#1 output. * 0b11..Source is Dither#1 output. */ #define DISPLAY_SEERIS_DISENG_SIG1CFG_SRCSELECT_diseng_sig1cfg_sig1_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_SIG1CFG_SRCSELECT_diseng_sig1cfg_sig1_select_SHIFT)) & DISPLAY_SEERIS_DISENG_SIG1CFG_SRCSELECT_diseng_sig1cfg_sig1_select_MASK) /*! @} */ /*! @name DISENG_LUT3D1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKUNLOCK_diseng_lut3d1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKUNLOCK_diseng_lut3d1_LockUnlock_SHIFT (0U) /*! diseng_lut3d1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKUNLOCK_diseng_lut3d1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_LOCKUNLOCK_diseng_lut3d1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_LOCKUNLOCK_diseng_lut3d1_LockUnlock_MASK) /*! @} */ /*! @name DISENG_LUT3D1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_LOCKSTATUS_diseng_lut3d1_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_LUT3D1_STATICCONTROL - lut3d static control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D1_STATICCONTROL_diseng_lut3d1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_LUT3D1_STATICCONTROL_diseng_lut3d1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_LUT3D1_STATICCONTROL_diseng_lut3d1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_STATICCONTROL_diseng_lut3d1_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_STATICCONTROL_diseng_lut3d1_ShdEn_MASK) /*! @} */ /*! @name DISENG_LUT3D1_CONTROL - lut3d control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_MODE_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_MODE_SHIFT (0U) /*! diseng_lut3d1_MODE * 0b000..Module in neutral mode, RGBA input data is bypassed to the output unchanged. * 0b001..LUT operates in 3D mode. * 0b010..Each RGB input is used as individual index into the respective LUT. Alpha channel is bypassed to output. * 0b011..Red input is used as common index for any RGB LUT. The alpha channel is bypassed to output. * 0b100..Red input is used as common index for any RGB LUT. The result is remapped and upconverted to RGBA. */ #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_MODE_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_MODE_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_DITH_EN_MASK (0x8U) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_DITH_EN_SHIFT (3U) /*! diseng_lut3d1_DITH_EN * 0b0..Output is 10bit. If LUT_DATA_WIDTH == MODE_12BIT then 2 LSB are truncated. * 0b1..If LUT_DATA_WIDTH == MODE_12BIT then 12bit value is dithered to 10bit. if LUT_DATA_WIDTH == MODE_10BIT then 10bit value is dithered to 8bit. */ #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_DITH_EN(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_DITH_EN_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_DITH_EN_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaMask_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaMask_SHIFT (5U) /*! diseng_lut3d1_AlphaMask * 0b0..Alpha mask mode disabled * 0b1..Alpha mask mode enabled */ #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaMask_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaMask_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaInvert_MASK (0x40U) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaInvert_SHIFT (6U) /*! diseng_lut3d1_AlphaInvert * 0b0..Disable computation for alpha smaller than 128 * 0b1..Disable computation for alpha greater than or equal to 128 */ #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaInvert_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_AlphaInvert_MASK) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_IDX_BITS_MASK (0xF00U) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_IDX_BITS_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_IDX_BITS(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_IDX_BITS_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_CONTROL_diseng_lut3d1_IDX_BITS_MASK) /*! @} */ /*! @name DISENG_LUT3D1_LUT - Look Up Table */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_LUT3D1_LUT_diseng_lut3d1_DATA_MASK (0xFFFFFU) #define DISPLAY_SEERIS_DISENG_LUT3D1_LUT_diseng_lut3d1_DATA_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_LUT3D1_LUT_diseng_lut3d1_DATA(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_LUT3D1_LUT_diseng_lut3d1_DATA_SHIFT)) & DISPLAY_SEERIS_DISENG_LUT3D1_LUT_diseng_lut3d1_DATA_MASK) /*! @} */ /* The count of DISPLAY_SEERIS_DISENG_LUT3D1_LUT */ #define DISPLAY_SEERIS_DISENG_LUT3D1_LUT_COUNT (2048U) /*! @name DISENG_MATRIX1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKUNLOCK_diseng_matrix1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKUNLOCK_diseng_matrix1_LockUnlock_SHIFT (0U) /*! diseng_matrix1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKUNLOCK_diseng_matrix1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_LOCKUNLOCK_diseng_matrix1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_LOCKUNLOCK_diseng_matrix1_LockUnlock_MASK) /*! @} */ /*! @name DISENG_MATRIX1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_LOCKSTATUS_diseng_matrix1_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_MATRIX1_STATICCONTROL - Color Matrix static control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_STATICCONTROL_diseng_matrix1_ShdEn_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_MATRIX1_STATICCONTROL_diseng_matrix1_ShdEn_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_STATICCONTROL_diseng_matrix1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_STATICCONTROL_diseng_matrix1_ShdEn_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_STATICCONTROL_diseng_matrix1_ShdEn_MASK) /*! @} */ /*! @name DISENG_MATRIX1_CONTROL - Color Matrix control register */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_MODE_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_MODE_SHIFT (0U) /*! diseng_matrix1_MODE * 0b00..Module in neutral mode, input data is bypassed * 0b01..Module in matrix mode, input data is multiplied with matrix values * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha * 0b11..Reserved, do not use */ #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_MODE(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_MODE_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_MODE_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaMask_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaMask_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaMask_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaMask_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaInvert_MASK (0x20U) #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaInvert_SHIFT (5U) #define DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaInvert_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_CONTROL_diseng_matrix1_AlphaInvert_MASK) /*! @} */ /*! @name DISENG_MATRIX1_RED0 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A11_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A11_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A11(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A11_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A11_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A12_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A12_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A12(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A12_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_RED0_diseng_matrix1_A12_MASK) /*! @} */ /*! @name DISENG_MATRIX1_RED1 - Matrix values for calculation of the red output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_RED1_diseng_matrix1_A13_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_RED1_diseng_matrix1_A13_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_RED1_diseng_matrix1_A13(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_RED1_diseng_matrix1_A13_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_RED1_diseng_matrix1_A13_MASK) /*! @} */ /*! @name DISENG_MATRIX1_GREEN0 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A21_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A21_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A21(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A21_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A21_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A22_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A22_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A22(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A22_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_GREEN0_diseng_matrix1_A22_MASK) /*! @} */ /*! @name DISENG_MATRIX1_GREEN1 - Matrix values for calculation of the green output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN1_diseng_matrix1_A23_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN1_diseng_matrix1_A23_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_GREEN1_diseng_matrix1_A23(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_GREEN1_diseng_matrix1_A23_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_GREEN1_diseng_matrix1_A23_MASK) /*! @} */ /*! @name DISENG_MATRIX1_BLUE0 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A31_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A31_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A31(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A31_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A31_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A32_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A32_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A32(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A32_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_BLUE0_diseng_matrix1_A32_MASK) /*! @} */ /*! @name DISENG_MATRIX1_BLUE1 - Matrix values for calculation of the blue output value. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE1_diseng_matrix1_A33_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE1_diseng_matrix1_A33_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_BLUE1_diseng_matrix1_A33(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_BLUE1_diseng_matrix1_A33_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_BLUE1_diseng_matrix1_A33_MASK) /*! @} */ /*! @name DISENG_MATRIX1_OFFSETVECTOR0 - Offset vectors for red and green output. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C1_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C1_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C1_MASK) #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C2_MASK (0x1FFF0000U) #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C2_SHIFT (16U) #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C2_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR0_diseng_matrix1_C2_MASK) /*! @} */ /*! @name DISENG_MATRIX1_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR1_diseng_matrix1_C3_MASK (0x1FFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR1_diseng_matrix1_C3_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR1_diseng_matrix1_C3(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR1_diseng_matrix1_C3_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_OFFSETVECTOR1_diseng_matrix1_C3_MASK) /*! @} */ /*! @name DISENG_MATRIX1_LASTCONTROLWORD - Value of last received control word, for debugging. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_MATRIX1_LASTCONTROLWORD_diseng_matrix1_L_VAL_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_MATRIX1_LASTCONTROLWORD_diseng_matrix1_L_VAL_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_MATRIX1_LASTCONTROLWORD_diseng_matrix1_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_MATRIX1_LASTCONTROLWORD_diseng_matrix1_L_VAL_SHIFT)) & DISPLAY_SEERIS_DISENG_MATRIX1_LASTCONTROLWORD_diseng_matrix1_L_VAL_MASK) /*! @} */ /*! @name DISENG_DITHER1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKUNLOCK_diseng_dither1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKUNLOCK_diseng_dither1_LockUnlock_SHIFT (0U) /*! diseng_dither1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKUNLOCK_diseng_dither1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_LOCKUNLOCK_diseng_dither1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_LOCKUNLOCK_diseng_dither1_LockUnlock_MASK) /*! @} */ /*! @name DISENG_DITHER1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_LockStatus_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_LOCKSTATUS_diseng_dither1_FreezeStatus_MASK) /*! @} */ /*! @name DISENG_DITHER1_CONTROL - Dither Unit common control. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1_CONTROL_diseng_dither1_mode_MASK (0x3U) #define DISPLAY_SEERIS_DISENG_DITHER1_CONTROL_diseng_dither1_mode_SHIFT (0U) /*! diseng_dither1_mode * 0b00..Neutral mode. Pixels by-pass the Dither Unit, all other settings are ignored. * 0b01..Dither Unit is active (uses 10bit input). * 0b10..Dither Unit is active (uses 12bit input). */ #define DISPLAY_SEERIS_DISENG_DITHER1_CONTROL_diseng_dither1_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_CONTROL_diseng_dither1_mode_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_CONTROL_diseng_dither1_mode_MASK) /*! @} */ /*! @name DISENG_DITHER1_DITHERCONTROL10BITS - Dither Unit processing control. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_blue_range_select_10bit_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_blue_range_select_10bit_SHIFT (0U) /*! diseng_dither1_blue_range_select_10bit * 0b010..Reduces blue component width from 10 bit to 8bit. * 0b011..Reduces blue component width from 10 bit to 7bit. * 0b100..Reduces blue component width from 10 bit to 6bit. * 0b101..Reduces blue component width from 10 bit to 5bit. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_blue_range_select_10bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_blue_range_select_10bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_blue_range_select_10bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_green_range_select_10bit_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_green_range_select_10bit_SHIFT (4U) /*! diseng_dither1_green_range_select_10bit * 0b010..Reduces green component width from 10 bit to 8bit. * 0b011..Reduces green component width from 10 bit to 7bit. * 0b100..Reduces green component width from 10 bit to 6bit. * 0b101..Reduces green component width from 10 bit to 5bit. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_green_range_select_10bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_green_range_select_10bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_green_range_select_10bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_red_range_select_10bit_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_red_range_select_10bit_SHIFT (8U) /*! diseng_dither1_red_range_select_10bit * 0b010..Reduces red component width from 10 bit to 8bit. * 0b011..Reduces red component width from 10 bit to 7bit. * 0b100..Reduces red component width from 10 bit to 6bit. * 0b101..Reduces red component width from 10 bit to 5bit. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_red_range_select_10bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_red_range_select_10bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL10BITS_diseng_dither1_red_range_select_10bit_MASK) /*! @} */ /*! @name DISENG_DITHER1_DITHERCONTROL12BITS - Dither Unit processing control. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_blue_range_select_12bit_MASK (0x7U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_blue_range_select_12bit_SHIFT (0U) /*! diseng_dither1_blue_range_select_12bit * 0b010..Reduces blue component width from 12 bit to 10bit. * 0b011..Reduces blue component width from 12 bit to 9bit. * 0b100..Reduces blue component width from 12 bit to 8bit. * 0b110..Reduces blue component width from 12 bit to 6bit. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_blue_range_select_12bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_blue_range_select_12bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_blue_range_select_12bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_green_range_select_12bit_MASK (0x70U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_green_range_select_12bit_SHIFT (4U) /*! diseng_dither1_green_range_select_12bit * 0b010..Reduces green component width from 12 bit to 10bit. * 0b011..Reduces green component width from 12 bit to 9bit. * 0b100..Reduces green component width from 12 bit to 8bit. * 0b110..Reduces green component width from 12 bit to 6bit. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_green_range_select_12bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_green_range_select_12bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_green_range_select_12bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_red_range_select_12bit_MASK (0x700U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_red_range_select_12bit_SHIFT (8U) /*! diseng_dither1_red_range_select_12bit * 0b010..Reduces red component width from 12 bit to 10bit. * 0b011..Reduces red component width from 12 bit to 9bit. * 0b100..Reduces red component width from 12 bit to 8bit. * 0b110..Reduces red component width from 12 bit to 6bit. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_red_range_select_12bit(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_red_range_select_12bit_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_red_range_select_12bit_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_offset_select_MASK (0x10000U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_offset_select_SHIFT (16U) /*! diseng_dither1_offset_select * 0b0..Offset is a bayer matrix value, which is selected according to pixel frame position. * 0b1..Offset is the sum from a bayer matrix value, which is selected according to pixel frame position, and a * value from a regular sequence, which changes each frame. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_offset_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_offset_select_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_offset_select_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_algo_select_MASK (0x300000U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_algo_select_SHIFT (20U) /*! diseng_dither1_algo_select * 0b01..Best possible resolution for most dark colors. Adds a diminutive offset to overall image brightness. * 0b10..Preserves overall image brightness. Cannot resolve most dark and most bright colors. All codes in-between are distributed perfectly smooth. * 0b11..Preserves overall image brightness. Best possible distribution of color codes over complete range. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_algo_select(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_algo_select_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_algo_select_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_alpha_mode_MASK (0x3000000U) #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_alpha_mode_SHIFT (24U) /*! diseng_dither1_alpha_mode * 0b00..The alpha bit is not considered. * 0b01..Red, green and blue components are only dithered, if the alpha bit is 1. * 0b10..Red, green and blue components are only dithered, if the alpha bit is 0. */ #define DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_alpha_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_alpha_mode_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1_DITHERCONTROL12BITS_diseng_dither1_alpha_mode_MASK) /*! @} */ /*! @name DISENG_DITHER1CFG_LOCKUNLOCK1 - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKUNLOCK1_diseng_dither1cfg_LockUnlock1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKUNLOCK1_diseng_dither1cfg_LockUnlock1_SHIFT (0U) /*! diseng_dither1cfg_LockUnlock1 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKUNLOCK1_diseng_dither1cfg_LockUnlock1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKUNLOCK1_diseng_dither1cfg_LockUnlock1_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKUNLOCK1_diseng_dither1cfg_LockUnlock1_MASK) /*! @} */ /*! @name DISENG_DITHER1CFG_LOCKSTATUS1 - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_LockStatus1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_LockStatus1_SHIFT (0U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_LockStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_LockStatus1_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_LockStatus1_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_PrivilegeStatus1_MASK (0x10U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_PrivilegeStatus1_SHIFT (4U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_PrivilegeStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_PrivilegeStatus1_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_PrivilegeStatus1_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_FreezeStatus1_MASK (0x100U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_FreezeStatus1_SHIFT (8U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_FreezeStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_FreezeStatus1_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1CFG_LOCKSTATUS1_diseng_dither1cfg_FreezeStatus1_MASK) /*! @} */ /*! @name DISENG_DITHER1CFG_POLARITYCTRL1 - Polarity control for display stream #1. */ /*! @{ */ #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolHs1_MASK (0x1U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolHs1_SHIFT (0U) /*! diseng_dither1cfg_PolHs1 * 0b0..Low active * 0b1..High active */ #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolHs1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolHs1_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolHs1_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolVs1_MASK (0x2U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolVs1_SHIFT (1U) /*! diseng_dither1cfg_PolVs1 * 0b0..Low active * 0b1..High active */ #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolVs1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolVs1_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolVs1_MASK) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolEn1_MASK (0x4U) #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolEn1_SHIFT (2U) /*! diseng_dither1cfg_PolEn1 * 0b0..Low active * 0b1..High active */ #define DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolEn1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolEn1_SHIFT)) & DISPLAY_SEERIS_DISENG_DITHER1CFG_POLARITYCTRL1_diseng_dither1cfg_PolEn1_MASK) /*! @} */ /*! @name DISPIRQ0_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_LOCKUNLOCK_dispirq0_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_LOCKUNLOCK_dispirq0_LockUnlock_SHIFT (0U) /*! dispirq0_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISPIRQ0_LOCKUNLOCK_dispirq0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_LOCKUNLOCK_dispirq0_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_LOCKUNLOCK_dispirq0_LockUnlock_MASK) /*! @} */ /*! @name DISPIRQ0_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_LockStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_LOCKSTATUS_dispirq0_FreezeStatus_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTENABLE0 - Interrupt Enable register 0. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE0_dispirq0_InterruptEnable0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE0_dispirq0_InterruptEnable0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE0_dispirq0_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE0_dispirq0_InterruptEnable0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE0_dispirq0_InterruptEnable0_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTENABLE1 - Interrupt Enable register 1. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE1_dispirq0_InterruptEnable1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE1_dispirq0_InterruptEnable1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE1_dispirq0_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE1_dispirq0_InterruptEnable1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE1_dispirq0_InterruptEnable1_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTENABLE2 - Interrupt Enable register 2. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE2_dispirq0_InterruptEnable2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE2_dispirq0_InterruptEnable2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE2_dispirq0_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE2_dispirq0_InterruptEnable2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTENABLE2_dispirq0_InterruptEnable2_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET0_dispirq0_InterruptPreset0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET0_dispirq0_InterruptPreset0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET0_dispirq0_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET0_dispirq0_InterruptPreset0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET0_dispirq0_InterruptPreset0_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET1_dispirq0_InterruptPreset1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET1_dispirq0_InterruptPreset1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET1_dispirq0_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET1_dispirq0_InterruptPreset1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET1_dispirq0_InterruptPreset1_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTPRESET2 - Interrupt Preset register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET2_dispirq0_InterruptPreset2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET2_dispirq0_InterruptPreset2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET2_dispirq0_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET2_dispirq0_InterruptPreset2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTPRESET2_dispirq0_InterruptPreset2_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR0_dispirq0_InterruptClear0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR0_dispirq0_InterruptClear0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR0_dispirq0_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR0_dispirq0_InterruptClear0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR0_dispirq0_InterruptClear0_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR1_dispirq0_InterruptClear1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR1_dispirq0_InterruptClear1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR1_dispirq0_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR1_dispirq0_InterruptClear1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR1_dispirq0_InterruptClear1_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTCLEAR2 - Interrupt Clear register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR2_dispirq0_InterruptClear2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR2_dispirq0_InterruptClear2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR2_dispirq0_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR2_dispirq0_InterruptClear2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTCLEAR2_dispirq0_InterruptClear2_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS0_dispirq0_InterruptStatus0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS0_dispirq0_InterruptStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS0_dispirq0_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS0_dispirq0_InterruptStatus0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS0_dispirq0_InterruptStatus0_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS1_dispirq0_InterruptStatus1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS1_dispirq0_InterruptStatus1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS1_dispirq0_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS1_dispirq0_InterruptStatus1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS1_dispirq0_InterruptStatus1_MASK) /*! @} */ /*! @name DISPIRQ0_INTERRUPTSTATUS2 - Interrupt Status register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS2_dispirq0_InterruptStatus2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS2_dispirq0_InterruptStatus2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS2_dispirq0_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS2_dispirq0_InterruptStatus2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ0_INTERRUPTSTATUS2_dispirq0_InterruptStatus2_MASK) /*! @} */ /*! @name DISPIRQ1_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_LOCKUNLOCK_dispirq1_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_LOCKUNLOCK_dispirq1_LockUnlock_SHIFT (0U) /*! dispirq1_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISPIRQ1_LOCKUNLOCK_dispirq1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_LOCKUNLOCK_dispirq1_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_LOCKUNLOCK_dispirq1_LockUnlock_MASK) /*! @} */ /*! @name DISPIRQ1_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_LockStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_LOCKSTATUS_dispirq1_FreezeStatus_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTENABLE0 - Interrupt Enable register 0. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE0_dispirq1_InterruptEnable0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE0_dispirq1_InterruptEnable0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE0_dispirq1_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE0_dispirq1_InterruptEnable0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE0_dispirq1_InterruptEnable0_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTENABLE1 - Interrupt Enable register 1. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE1_dispirq1_InterruptEnable1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE1_dispirq1_InterruptEnable1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE1_dispirq1_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE1_dispirq1_InterruptEnable1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE1_dispirq1_InterruptEnable1_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTENABLE2 - Interrupt Enable register 2. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE2_dispirq1_InterruptEnable2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE2_dispirq1_InterruptEnable2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE2_dispirq1_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE2_dispirq1_InterruptEnable2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTENABLE2_dispirq1_InterruptEnable2_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET0_dispirq1_InterruptPreset0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET0_dispirq1_InterruptPreset0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET0_dispirq1_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET0_dispirq1_InterruptPreset0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET0_dispirq1_InterruptPreset0_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET1_dispirq1_InterruptPreset1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET1_dispirq1_InterruptPreset1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET1_dispirq1_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET1_dispirq1_InterruptPreset1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET1_dispirq1_InterruptPreset1_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTPRESET2 - Interrupt Preset register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET2_dispirq1_InterruptPreset2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET2_dispirq1_InterruptPreset2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET2_dispirq1_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET2_dispirq1_InterruptPreset2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTPRESET2_dispirq1_InterruptPreset2_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR0_dispirq1_InterruptClear0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR0_dispirq1_InterruptClear0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR0_dispirq1_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR0_dispirq1_InterruptClear0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR0_dispirq1_InterruptClear0_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR1_dispirq1_InterruptClear1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR1_dispirq1_InterruptClear1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR1_dispirq1_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR1_dispirq1_InterruptClear1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR1_dispirq1_InterruptClear1_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTCLEAR2 - Interrupt Clear register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR2_dispirq1_InterruptClear2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR2_dispirq1_InterruptClear2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR2_dispirq1_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR2_dispirq1_InterruptClear2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTCLEAR2_dispirq1_InterruptClear2_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS0_dispirq1_InterruptStatus0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS0_dispirq1_InterruptStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS0_dispirq1_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS0_dispirq1_InterruptStatus0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS0_dispirq1_InterruptStatus0_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS1_dispirq1_InterruptStatus1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS1_dispirq1_InterruptStatus1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS1_dispirq1_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS1_dispirq1_InterruptStatus1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS1_dispirq1_InterruptStatus1_MASK) /*! @} */ /*! @name DISPIRQ1_INTERRUPTSTATUS2 - Interrupt Status register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS2_dispirq1_InterruptStatus2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS2_dispirq1_InterruptStatus2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS2_dispirq1_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS2_dispirq1_InterruptStatus2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ1_INTERRUPTSTATUS2_dispirq1_InterruptStatus2_MASK) /*! @} */ /*! @name DISPIRQ2_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_LOCKUNLOCK_dispirq2_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_LOCKUNLOCK_dispirq2_LockUnlock_SHIFT (0U) /*! dispirq2_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISPIRQ2_LOCKUNLOCK_dispirq2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_LOCKUNLOCK_dispirq2_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_LOCKUNLOCK_dispirq2_LockUnlock_MASK) /*! @} */ /*! @name DISPIRQ2_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_LockStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_LOCKSTATUS_dispirq2_FreezeStatus_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTENABLE0 - Interrupt Enable register 0. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE0_dispirq2_InterruptEnable0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE0_dispirq2_InterruptEnable0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE0_dispirq2_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE0_dispirq2_InterruptEnable0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE0_dispirq2_InterruptEnable0_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTENABLE1 - Interrupt Enable register 1. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE1_dispirq2_InterruptEnable1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE1_dispirq2_InterruptEnable1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE1_dispirq2_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE1_dispirq2_InterruptEnable1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE1_dispirq2_InterruptEnable1_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTENABLE2 - Interrupt Enable register 2. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE2_dispirq2_InterruptEnable2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE2_dispirq2_InterruptEnable2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE2_dispirq2_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE2_dispirq2_InterruptEnable2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTENABLE2_dispirq2_InterruptEnable2_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET0_dispirq2_InterruptPreset0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET0_dispirq2_InterruptPreset0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET0_dispirq2_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET0_dispirq2_InterruptPreset0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET0_dispirq2_InterruptPreset0_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET1_dispirq2_InterruptPreset1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET1_dispirq2_InterruptPreset1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET1_dispirq2_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET1_dispirq2_InterruptPreset1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET1_dispirq2_InterruptPreset1_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTPRESET2 - Interrupt Preset register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET2_dispirq2_InterruptPreset2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET2_dispirq2_InterruptPreset2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET2_dispirq2_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET2_dispirq2_InterruptPreset2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTPRESET2_dispirq2_InterruptPreset2_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR0_dispirq2_InterruptClear0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR0_dispirq2_InterruptClear0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR0_dispirq2_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR0_dispirq2_InterruptClear0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR0_dispirq2_InterruptClear0_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR1_dispirq2_InterruptClear1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR1_dispirq2_InterruptClear1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR1_dispirq2_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR1_dispirq2_InterruptClear1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR1_dispirq2_InterruptClear1_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTCLEAR2 - Interrupt Clear register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR2_dispirq2_InterruptClear2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR2_dispirq2_InterruptClear2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR2_dispirq2_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR2_dispirq2_InterruptClear2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTCLEAR2_dispirq2_InterruptClear2_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS0_dispirq2_InterruptStatus0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS0_dispirq2_InterruptStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS0_dispirq2_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS0_dispirq2_InterruptStatus0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS0_dispirq2_InterruptStatus0_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS1_dispirq2_InterruptStatus1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS1_dispirq2_InterruptStatus1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS1_dispirq2_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS1_dispirq2_InterruptStatus1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS1_dispirq2_InterruptStatus1_MASK) /*! @} */ /*! @name DISPIRQ2_INTERRUPTSTATUS2 - Interrupt Status register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS2_dispirq2_InterruptStatus2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS2_dispirq2_InterruptStatus2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS2_dispirq2_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS2_dispirq2_InterruptStatus2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ2_INTERRUPTSTATUS2_dispirq2_InterruptStatus2_MASK) /*! @} */ /*! @name DISPIRQ3_LOCKUNLOCK - Register to change the protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_LOCKUNLOCK_dispirq3_LockUnlock_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_LOCKUNLOCK_dispirq3_LockUnlock_SHIFT (0U) /*! dispirq3_LockUnlock * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1. * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15. * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset. * 0b10110101111000100100011001101110..Disables privilege protection. * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset. */ #define DISPLAY_SEERIS_DISPIRQ3_LOCKUNLOCK_dispirq3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_LOCKUNLOCK_dispirq3_LockUnlock_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_LOCKUNLOCK_dispirq3_LockUnlock_MASK) /*! @} */ /*! @name DISPIRQ3_LOCKSTATUS - Protection status of this address block. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_LockStatus_MASK (0x1U) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_LockStatus_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_LockStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_LockStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_PrivilegeStatus_MASK (0x10U) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_PrivilegeStatus_SHIFT (4U) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_PrivilegeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_PrivilegeStatus_MASK) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_FreezeStatus_MASK (0x100U) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_FreezeStatus_SHIFT (8U) #define DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_FreezeStatus_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_LOCKSTATUS_dispirq3_FreezeStatus_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTENABLE0 - Interrupt Enable register 0. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE0_dispirq3_InterruptEnable0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE0_dispirq3_InterruptEnable0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE0_dispirq3_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE0_dispirq3_InterruptEnable0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE0_dispirq3_InterruptEnable0_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTENABLE1 - Interrupt Enable register 1. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE1_dispirq3_InterruptEnable1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE1_dispirq3_InterruptEnable1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE1_dispirq3_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE1_dispirq3_InterruptEnable1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE1_dispirq3_InterruptEnable1_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTENABLE2 - Interrupt Enable register 2. */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE2_dispirq3_InterruptEnable2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE2_dispirq3_InterruptEnable2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE2_dispirq3_InterruptEnable2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE2_dispirq3_InterruptEnable2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTENABLE2_dispirq3_InterruptEnable2_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTPRESET0 - Interrupt Preset register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET0_dispirq3_InterruptPreset0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET0_dispirq3_InterruptPreset0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET0_dispirq3_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET0_dispirq3_InterruptPreset0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET0_dispirq3_InterruptPreset0_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTPRESET1 - Interrupt Preset register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET1_dispirq3_InterruptPreset1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET1_dispirq3_InterruptPreset1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET1_dispirq3_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET1_dispirq3_InterruptPreset1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET1_dispirq3_InterruptPreset1_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTPRESET2 - Interrupt Preset register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET2_dispirq3_InterruptPreset2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET2_dispirq3_InterruptPreset2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET2_dispirq3_InterruptPreset2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET2_dispirq3_InterruptPreset2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTPRESET2_dispirq3_InterruptPreset2_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTCLEAR0 - Interrupt Clear register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR0_dispirq3_InterruptClear0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR0_dispirq3_InterruptClear0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR0_dispirq3_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR0_dispirq3_InterruptClear0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR0_dispirq3_InterruptClear0_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTCLEAR1 - Interrupt Clear register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR1_dispirq3_InterruptClear1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR1_dispirq3_InterruptClear1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR1_dispirq3_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR1_dispirq3_InterruptClear1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR1_dispirq3_InterruptClear1_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTCLEAR2 - Interrupt Clear register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR2_dispirq3_InterruptClear2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR2_dispirq3_InterruptClear2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR2_dispirq3_InterruptClear2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR2_dispirq3_InterruptClear2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTCLEAR2_dispirq3_InterruptClear2_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTSTATUS0 - Interrupt Status register 0 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS0_dispirq3_InterruptStatus0_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS0_dispirq3_InterruptStatus0_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS0_dispirq3_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS0_dispirq3_InterruptStatus0_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS0_dispirq3_InterruptStatus0_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTSTATUS1 - Interrupt Status register 1 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS1_dispirq3_InterruptStatus1_MASK (0xFFFFFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS1_dispirq3_InterruptStatus1_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS1_dispirq3_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS1_dispirq3_InterruptStatus1_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS1_dispirq3_InterruptStatus1_MASK) /*! @} */ /*! @name DISPIRQ3_INTERRUPTSTATUS2 - Interrupt Status register 2 */ /*! @{ */ #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS2_dispirq3_InterruptStatus2_MASK (0x3FFFFFU) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS2_dispirq3_InterruptStatus2_SHIFT (0U) #define DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS2_dispirq3_InterruptStatus2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS2_dispirq3_InterruptStatus2_SHIFT)) & DISPLAY_SEERIS_DISPIRQ3_INTERRUPTSTATUS2_dispirq3_InterruptStatus2_MASK) /*! @} */ /*! * @} */ /* end of group DISPLAY_SEERIS_Register_Masks */ /* DISPLAY_SEERIS - Peripheral instance base addresses */ /** Peripheral DISPLAY_SEERIS base address */ #define DISPLAY_SEERIS_BASE (0x4B400000u) /** Peripheral DISPLAY_SEERIS base pointer */ #define DISPLAY_SEERIS ((DISPLAY_SEERIS_Type *)DISPLAY_SEERIS_BASE) /** Array initializer of DISPLAY_SEERIS peripheral base addresses */ #define DISPLAY_SEERIS_BASE_ADDRS { DISPLAY_SEERIS_BASE } /** Array initializer of DISPLAY_SEERIS peripheral base pointers */ #define DISPLAY_SEERIS_BASE_PTRS { DISPLAY_SEERIS } /*! * @} */ /* end of group DISPLAY_SEERIS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DISPLAY_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_TCU_Peripheral_Access_Layer DISPLAY_TCU Peripheral Access Layer * @{ */ /** DISPLAY_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[1020]; __IO uint32_t TCU_PIXEL_MST_TEST_MODE; /**< PIXEL LINK master test mode, offset: 0x810 */ __IO uint32_t TCU_PIXEL_MST_TEST_INPUT_; /**< PIXEL LINK master test input, offset: 0x814 */ uint8_t RESERVED_3[1000]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_4[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } DISPLAY_TCU_Type; /* ---------------------------------------------------------------------------- -- DISPLAY_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DISPLAY_TCU_Register_Masks DISPLAY_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & DISPLAY_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PIXEL_MST_TEST_MODE - PIXEL LINK master test mode */ /*! @{ */ #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst0_test_mode_MASK (0x1U) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst0_test_mode_SHIFT (0U) /*! pixel_mst0_test_mode - pixel loop test production mode */ #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst0_test_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst0_test_mode_SHIFT)) & DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst0_test_mode_MASK) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst1_test_mode_MASK (0x2U) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst1_test_mode_SHIFT (1U) /*! pixel_mst1_test_mode - pixel loop test production mode */ #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst1_test_mode(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst1_test_mode_SHIFT)) & DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst1_test_mode_MASK) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_start_MASK (0x4U) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_start_SHIFT (2U) /*! pixel_mst_test_start - pixel link test start */ #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_start_SHIFT)) & DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_start_MASK) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_load_MASK (0x8U) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_load_SHIFT (3U) /*! pixel_mst_test_load - pixel link test load */ #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_load(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_load_SHIFT)) & DISPLAY_TCU_TCU_PIXEL_MST_TEST_MODE_pixel_mst_test_load_MASK) /*! @} */ /*! @name TCU_PIXEL_MST_TEST_INPUT_ - PIXEL LINK master test input */ /*! @{ */ #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_INPUT__pixel_mst_test_input_MASK (0xFFFFFFFFU) #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_INPUT__pixel_mst_test_input_SHIFT (0U) /*! pixel_mst_test_input - pixel link test inputs */ #define DISPLAY_TCU_TCU_PIXEL_MST_TEST_INPUT__pixel_mst_test_input(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PIXEL_MST_TEST_INPUT__pixel_mst_test_input_SHIFT)) & DISPLAY_TCU_TCU_PIXEL_MST_TEST_INPUT__pixel_mst_test_input_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & DISPLAY_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & DISPLAY_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_MASK (0x2U) #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_SHIFT (1U) /*! tcu_fuse_obs_1 - fuse observation */ #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_SHIFT)) & DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_MASK) #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_2_MASK (0x4U) #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_2_SHIFT (2U) /*! tcu_fuse_obs_2 - fuse observation */ #define DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_2(x) (((uint32_t)(((uint32_t)(x)) << DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_2_SHIFT)) & DISPLAY_TCU_TCU_DFT_FUSE_tcu_fuse_obs_2_MASK) /*! @} */ /*! * @} */ /* end of group DISPLAY_TCU_Register_Masks */ /* DISPLAY_TCU - Peripheral instance base addresses */ /** Peripheral DISPLAY__TCU base address */ #define DISPLAY__TCU_BASE (0x4B000000u) /** Peripheral DISPLAY__TCU base pointer */ #define DISPLAY__TCU ((DISPLAY_TCU_Type *)DISPLAY__TCU_BASE) /** Array initializer of DISPLAY_TCU peripheral base addresses */ #define DISPLAY_TCU_BASE_ADDRS { DISPLAY__TCU_BASE } /** Array initializer of DISPLAY_TCU peripheral base pointers */ #define DISPLAY_TCU_BASE_PTRS { DISPLAY__TCU } /*! * @} */ /* end of group DISPLAY_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ uint8_t RESERVED_0[240]; __IO uint32_t CH_GRPRI[32]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_1[65152]; struct { /* offset: 0x10000, array step: 0x10000 */ __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */ __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */ uint8_t RESERVED_0[12]; __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x10020, array step: 0x10000 */ __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x10024, array step: 0x10000 */ __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x10026, array step: 0x10000 */ union { /* offset: 0x10028, array step: 0x10000 */ __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */ __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x10028, array step: 0x10000 */ }; __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x1002C, array step: 0x10000 */ __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x10030, array step: 0x10000 */ __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x10034, array step: 0x10000 */ union { /* offset: 0x10036, array step: 0x10000 */ __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x10036, array step: 0x10000 */ __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x10036, array step: 0x10000 */ }; __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10038, array step: 0x10000 */ __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x1003C, array step: 0x10000 */ union { /* offset: 0x1003E, array step: 0x10000 */ __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1003E, array step: 0x10000 */ __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1003E, array step: 0x10000 */ }; uint8_t RESERVED_1[65472]; } CH[32]; } DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /*! @name MP_CSR - Management Page Control */ /*! @{ */ #define DMA_MP_CSR_EDBG_MASK (0x2U) #define DMA_MP_CSR_EDBG_SHIFT (1U) /*! EDBG - Enable Debug * 0b0..Debug mode disabled * 0b1..Debug mode is enabled. */ #define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) #define DMA_MP_CSR_ERCA_MASK (0x4U) #define DMA_MP_CSR_ERCA_SHIFT (2U) /*! ERCA - Enable Round Robin Channel Arbitration * 0b0..Round-robin channel arbitration disabled * 0b1..Round-robin channel arbitration enabled */ #define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) #define DMA_MP_CSR_HAE_MASK (0x10U) #define DMA_MP_CSR_HAE_SHIFT (4U) /*! HAE - Halt After Error * 0b0..Normal operation * 0b1..Any error causes the HALT field to be set to 1 */ #define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) #define DMA_MP_CSR_HALT_MASK (0x20U) #define DMA_MP_CSR_HALT_SHIFT (5U) /*! HALT - Halt DMA Operations * 0b0..Normal operation * 0b1..Stall the start of any new channels */ #define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) #define DMA_MP_CSR_GCLC_MASK (0x40U) #define DMA_MP_CSR_GCLC_SHIFT (6U) /*! GCLC - Global Channel Linking Control * 0b0..Channel linking disabled for all channels * 0b1..Channel linking available and controlled by each channel's link settings */ #define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) #define DMA_MP_CSR_GMRC_MASK (0x80U) #define DMA_MP_CSR_GMRC_SHIFT (7U) /*! GMRC - Global Master ID Replication Control * 0b0..Master ID replication disabled for all channels * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting */ #define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) #define DMA_MP_CSR_ECX_MASK (0x100U) #define DMA_MP_CSR_ECX_SHIFT (8U) /*! ECX - Cancel Transfer With Error * 0b0..Normal operation * 0b1..Cancel the remaining data transfer */ #define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) #define DMA_MP_CSR_CX_MASK (0x200U) #define DMA_MP_CSR_CX_SHIFT (9U) /*! CX - Cancel Transfer * 0b0..Normal operation * 0b1..Cancel the remaining data transfer */ #define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) #define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) #define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) /*! ACTIVE_ID - Active Channel ID */ #define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) #define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) #define DMA_MP_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - DMA Active Status * 0b0..eDMA is idle * 0b1..eDMA is executing a channel */ #define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) /*! @} */ /*! @name MP_ES - Management Page Error Status */ /*! @{ */ #define DMA_MP_ES_DBE_MASK (0x1U) #define DMA_MP_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..Last recorded error was a bus error on a destination write */ #define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) #define DMA_MP_ES_SBE_MASK (0x2U) #define DMA_MP_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..Last recorded error was a bus error on a source read */ #define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) #define DMA_MP_ES_SGE_MASK (0x4U) #define DMA_MP_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field */ #define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) #define DMA_MP_ES_NCE_MASK (0x8U) #define DMA_MP_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error */ #define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) #define DMA_MP_ES_DOE_MASK (0x10U) #define DMA_MP_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field */ #define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) #define DMA_MP_ES_DAE_MASK (0x20U) #define DMA_MP_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field */ #define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) #define DMA_MP_ES_SOE_MASK (0x40U) #define DMA_MP_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field */ #define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) #define DMA_MP_ES_SAE_MASK (0x80U) #define DMA_MP_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field */ #define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) #define DMA_MP_ES_ECX_MASK (0x100U) #define DMA_MP_ES_ECX_SHIFT (8U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input */ #define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) #define DMA_MP_ES_ERRCHN_MASK (0x1F000000U) #define DMA_MP_ES_ERRCHN_SHIFT (24U) /*! ERRCHN - Error Channel Number or Canceled Channel Number */ #define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) #define DMA_MP_ES_VLD_MASK (0x80000000U) #define DMA_MP_ES_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..No CHn_ES[ERR] fields are set to 1 * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared */ #define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) /*! @} */ /*! @name MP_INT - Management Page Interrupt Request Status */ /*! @{ */ #define DMA_MP_INT_INT_MASK (0xFFFFFFFFU) #define DMA_MP_INT_INT_SHIFT (0U) /*! INT - Interrupt Request Status */ #define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) /*! @} */ /*! @name MP_HRS - Management Page Hardware Request Status */ /*! @{ */ #define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) #define DMA_MP_HRS_HRS_SHIFT (0U) /*! HRS - Hardware Request Status */ #define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) /*! @} */ /*! @name CH_GRPRI - Channel Arbitration Group */ /*! @{ */ #define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) #define DMA_CH_GRPRI_GRPRI_SHIFT (0U) /*! GRPRI - Arbitration Group For Channel n */ #define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) /*! @} */ /* The count of DMA_CH_GRPRI */ #define DMA_CH_GRPRI_COUNT (32U) /*! @name CH_CSR - Channel Control and Status */ /*! @{ */ #define DMA_CH_CSR_ERQ_MASK (0x1U) #define DMA_CH_CSR_ERQ_SHIFT (0U) /*! ERQ - Enable DMA Request * 0b0..DMA hardware request signal for corresponding channel disabled * 0b1..DMA hardware request signal for corresponding channel enabled */ #define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) #define DMA_CH_CSR_EARQ_MASK (0x2U) #define DMA_CH_CSR_EARQ_SHIFT (1U) /*! EARQ - Enable Asynchronous DMA Request * 0b0..Disable asynchronous DMA request for the channel * 0b1..Enable asynchronous DMA request for the channel */ #define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) #define DMA_CH_CSR_EEI_MASK (0x4U) #define DMA_CH_CSR_EEI_SHIFT (2U) /*! EEI - Enable Error Interrupt * 0b0..Error signal for corresponding channel does not generate error interrupt * 0b1..Assertion of error signal for corresponding channel generates error interrupt request */ #define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) #define DMA_CH_CSR_EBW_MASK (0x8U) #define DMA_CH_CSR_EBW_SHIFT (3U) /*! EBW - Enable Buffered Writes * 0b0..Buffered writes on system bus disabled * 0b1..Buffered writes on system bus enabled */ #define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) #define DMA_CH_CSR_DONE_MASK (0x40000000U) #define DMA_CH_CSR_DONE_SHIFT (30U) /*! DONE - Channel Done */ #define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) #define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) #define DMA_CH_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - Channel Active */ #define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) /*! @} */ /* The count of DMA_CH_CSR */ #define DMA_CH_CSR_COUNT (32U) /*! @name CH_ES - Channel Error Status */ /*! @{ */ #define DMA_CH_ES_DBE_MASK (0x1U) #define DMA_CH_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No destination bus error * 0b1..Last recorded error was bus error on destination write */ #define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) #define DMA_CH_ES_SBE_MASK (0x2U) #define DMA_CH_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No source bus error * 0b1..Last recorded error was bus error on source read */ #define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) #define DMA_CH_ES_SGE_MASK (0x4U) #define DMA_CH_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No scatter/gather configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field */ #define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) #define DMA_CH_ES_NCE_MASK (0x8U) #define DMA_CH_ES_NCE_SHIFT (3U) /*! NCE - NBYTES/CITER Configuration Error * 0b0..No NBYTES/CITER configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields */ #define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) #define DMA_CH_ES_DOE_MASK (0x10U) #define DMA_CH_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No destination offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field */ #define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) #define DMA_CH_ES_DAE_MASK (0x20U) #define DMA_CH_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No destination address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field */ #define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) #define DMA_CH_ES_SOE_MASK (0x40U) #define DMA_CH_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No source offset configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field */ #define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) #define DMA_CH_ES_SAE_MASK (0x80U) #define DMA_CH_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No source address configuration error * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field */ #define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) #define DMA_CH_ES_ERR_MASK (0x80000000U) #define DMA_CH_ES_ERR_SHIFT (31U) /*! ERR - Error In Channel * 0b0..An error in this channel has not occurred * 0b1..An error in this channel has occurred */ #define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) /*! @} */ /* The count of DMA_CH_ES */ #define DMA_CH_ES_COUNT (32U) /*! @name CH_INT - Channel Interrupt Status */ /*! @{ */ #define DMA_CH_INT_INT_MASK (0x1U) #define DMA_CH_INT_INT_SHIFT (0U) /*! INT - Interrupt Request * 0b0..Interrupt request for corresponding channel cleared * 0b1..Interrupt request for corresponding channel active */ #define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) /*! @} */ /* The count of DMA_CH_INT */ #define DMA_CH_INT_COUNT (32U) /*! @name CH_SBR - Channel System Bus */ /*! @{ */ #define DMA_CH_SBR_MID_MASK (0xFU) #define DMA_CH_SBR_MID_SHIFT (0U) /*! MID - Master ID */ #define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) #define DMA_CH_SBR_SEC_MASK (0x4000U) #define DMA_CH_SBR_SEC_SHIFT (14U) /*! SEC - Security Level * 0b0..Nonsecure protection level for DMA transfers * 0b1..Secure protection level for DMA transfers */ #define DMA_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK) #define DMA_CH_SBR_PAL_MASK (0x8000U) #define DMA_CH_SBR_PAL_SHIFT (15U) /*! PAL - Privileged Access Level * 0b0..User protection level for DMA transfers * 0b1..Privileged protection level for DMA transfers */ #define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) #define DMA_CH_SBR_EMI_MASK (0x10000U) #define DMA_CH_SBR_EMI_SHIFT (16U) /*! EMI - Enable Master ID Replication * 0b0..Master ID replication is disabled * 0b1..Master ID replication is enabled */ #define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) #define DMA_CH_SBR_ATTR_MASK (0x7E0000U) #define DMA_CH_SBR_ATTR_SHIFT (17U) /*! ATTR - Attribute Output */ #define DMA_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK) /*! @} */ /* The count of DMA_CH_SBR */ #define DMA_CH_SBR_COUNT (32U) /*! @name CH_PRI - Channel Priority */ /*! @{ */ #define DMA_CH_PRI_APL_MASK (0x7U) #define DMA_CH_PRI_APL_SHIFT (0U) /*! APL - Arbitration Priority Level */ #define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) #define DMA_CH_PRI_DPA_MASK (0x40000000U) #define DMA_CH_PRI_DPA_SHIFT (30U) /*! DPA - Disable Preempt Ability * 0b0..Channel can suspend a lower-priority channel * 0b1..Channel cannot suspend any other channel, regardless of channel priority */ #define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) #define DMA_CH_PRI_ECP_MASK (0x80000000U) #define DMA_CH_PRI_ECP_SHIFT (31U) /*! ECP - Enable Channel Preemption * 0b0..Channel cannot be suspended by a higher-priority channel's service request * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request */ #define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) /*! @} */ /* The count of DMA_CH_PRI */ #define DMA_CH_PRI_COUNT (32U) /*! @name TCD_SADDR - TCD Source Address */ /*! @{ */ #define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_SADDR_SADDR_SHIFT (0U) /*! SADDR - Source Address */ #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) /*! @} */ /* The count of DMA_TCD_SADDR */ #define DMA_TCD_SADDR_COUNT (32U) /*! @name TCD_SOFF - TCD Signed Source Address Offset */ /*! @{ */ #define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) #define DMA_TCD_SOFF_SOFF_SHIFT (0U) /*! SOFF - Source Address Signed Offset */ #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) /*! @} */ /* The count of DMA_TCD_SOFF */ #define DMA_TCD_SOFF_COUNT (32U) /*! @name TCD_ATTR - TCD Transfer Attributes */ /*! @{ */ #define DMA_TCD_ATTR_DSIZE_MASK (0x7U) #define DMA_TCD_ATTR_DSIZE_SHIFT (0U) /*! DSIZE - Destination Data Transfer Size */ #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) #define DMA_TCD_ATTR_DMOD_MASK (0xF8U) #define DMA_TCD_ATTR_DMOD_SHIFT (3U) /*! DMOD - Destination Address Modulo */ #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) #define DMA_TCD_ATTR_SSIZE_MASK (0x700U) #define DMA_TCD_ATTR_SSIZE_SHIFT (8U) /*! SSIZE - Source Data Transfer Size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100..16-byte * 0b101..32-byte * 0b110..64-byte * 0b111.. */ #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) #define DMA_TCD_ATTR_SMOD_MASK (0xF800U) #define DMA_TCD_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source Address Modulo * 0b00000..Source address modulo feature disabled * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] */ #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) /*! @} */ /* The count of DMA_TCD_ATTR */ #define DMA_TCD_ATTR_COUNT (32U) /*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes To Transfer Per Service Request */ #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..Minor loop offset not applied to DADDR * 0b1..Minor loop offset applied to DADDR */ #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..Minor loop offset not applied to SADDR * 0b1..Minor loop offset applied to SADDR */ #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFNO */ #define DMA_TCD_NBYTES_MLOFFNO_COUNT (32U) /*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ /*! @{ */ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes To Transfer Per Service Request */ #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) /*! MLOFF - Minor Loop Offset */ #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..Minor loop offset not applied to DADDR * 0b1..Minor loop offset applied to DADDR */ #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..Minor loop offset not applied to SADDR * 0b1..Minor loop offset applied to SADDR */ #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) /*! @} */ /* The count of DMA_TCD_NBYTES_MLOFFYES */ #define DMA_TCD_NBYTES_MLOFFYES_COUNT (32U) /*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ /*! @{ */ #define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) #define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) /*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ #define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) /*! @} */ /* The count of DMA_TCD_SLAST_SDA */ #define DMA_TCD_SLAST_SDA_COUNT (32U) /*! @name TCD_DADDR - TCD Destination Address */ /*! @{ */ #define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA_TCD_DADDR_DADDR_SHIFT (0U) /*! DADDR - Destination Address */ #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) /*! @} */ /* The count of DMA_TCD_DADDR */ #define DMA_TCD_DADDR_COUNT (32U) /*! @name TCD_DOFF - TCD Signed Destination Address Offset */ /*! @{ */ #define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) #define DMA_TCD_DOFF_DOFF_SHIFT (0U) /*! DOFF - Destination Address Signed Offset */ #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) /*! @} */ /* The count of DMA_TCD_DOFF */ #define DMA_TCD_DOFF_COUNT (32U) /*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) #define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enable Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKNO */ #define DMA_TCD_CITER_ELINKNO_COUNT (32U) /*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Minor Loop Link Channel Number */ #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) #define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_CITER_ELINKYES */ #define DMA_TCD_CITER_ELINKYES_COUNT (32U) /*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ /*! @{ */ #define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) #define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) /*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ #define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) /*! @} */ /* The count of DMA_TCD_DLAST_SGA */ #define DMA_TCD_DLAST_SGA_COUNT (32U) /*! @name TCD_CSR - TCD Control and Status */ /*! @{ */ #define DMA_TCD_CSR_START_MASK (0x1U) #define DMA_TCD_CSR_START_SHIFT (0U) /*! START - Channel Start * 0b0..Channel not explicitly started * 0b1..Channel explicitly started via a software-initiated service request */ #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) #define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) #define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) /*! INTMAJOR - Enable Interrupt If Major count complete * 0b0..End-of-major loop interrupt disabled * 0b1..End-of-major loop interrupt enabled */ #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) #define DMA_TCD_CSR_INTHALF_MASK (0x4U) #define DMA_TCD_CSR_INTHALF_SHIFT (2U) /*! INTHALF - Enable Interrupt If Major Counter Half-complete * 0b0..Halfway point interrupt disabled * 0b1..Halfway point interrupt enabled */ #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) #define DMA_TCD_CSR_DREQ_MASK (0x8U) #define DMA_TCD_CSR_DREQ_SHIFT (3U) /*! DREQ - Disable Request * 0b0..No operation * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests */ #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) #define DMA_TCD_CSR_ESG_MASK (0x10U) #define DMA_TCD_CSR_ESG_SHIFT (4U) /*! ESG - Enable Scatter/Gather Processing * 0b0..Current channel's TCD is normal format * 0b1..Current channel's TCD specifies scatter/gather format. */ #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) #define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) #define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) /*! MAJORELINK - Enable Link When Major Loop Complete * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) #define DMA_TCD_CSR_EEOP_MASK (0x40U) #define DMA_TCD_CSR_EEOP_SHIFT (6U) /*! EEOP - Enable End-Of-Packet Processing * 0b0..End-of-packet operation disabled * 0b1..End-of-packet hardware input signal enabled */ #define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) #define DMA_TCD_CSR_ESDA_MASK (0x80U) #define DMA_TCD_CSR_ESDA_SHIFT (7U) /*! ESDA - Enable Store Destination Address * 0b0..Ability to store destination address to system memory disabled * 0b1..Ability to store destination address to system memory enabled */ #define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) #define DMA_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) #define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) /*! MAJORLINKCH - Major Loop Link Channel Number */ #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) #define DMA_TCD_CSR_BWC_MASK (0xC000U) #define DMA_TCD_CSR_BWC_SHIFT (14U) /*! BWC - Bandwidth Control * 0b00..No eDMA engine stalls * 0b01.. * 0b10..eDMA engine stalls for 4 cycles after each R/W * 0b11..eDMA engine stalls for 8 cycles after each R/W */ #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) /*! @} */ /* The count of DMA_TCD_CSR */ #define DMA_TCD_CSR_COUNT (32U) /*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) #define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enables Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKNO */ #define DMA_TCD_BITER_ELINKNO_COUNT (32U) /*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Link Channel Number */ #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) #define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable Link * 0b0..Channel-to-channel linking disabled * 0b1..Channel-to-channel linking enabled */ #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA_TCD_BITER_ELINKYES */ #define DMA_TCD_BITER_ELINKYES_COUNT (32U) /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ /** Peripheral DMA3 base address */ #define DMA3_BASE (0x44000000u) /** Peripheral DMA3 base pointer */ #define DMA3 ((DMA_Type *)DMA3_BASE) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { DMA3_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA3 } /** Interrupt vectors for the DMA peripheral type */ #define DMA_ERROR_IRQS { { DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn, DMA3_ERROR_IRQn } } /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA5_Peripheral_Access_Layer DMA5 Peripheral Access Layer * @{ */ /** DMA5 - Register Layout Typedef */ typedef struct { __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ __I uint32_t MP_INT_LOW; /**< Management Page Interrupt Request Status, offset: 0x8 */ __I uint32_t MP_INT_HIGH; /**< Management Page Interrupt Request Status, offset: 0xC, available only on: WAKEUP.EDMA5_MP2/EDMA5_2, WAKEUP.EDMA5_MP3/EDMA5_3 (missing on CAMERA.EDMA5_MPC/EDMA5_4) */ __I uint32_t MP_HRS_LOW; /**< Hardware Request Status, offset: 0x10 */ __I uint32_t MP_HRS_HIGH; /**< Hardware Request Status, offset: 0x14, available only on: WAKEUP.EDMA5_MP2/EDMA5_2, WAKEUP.EDMA5_MP3/EDMA5_3 (missing on CAMERA.EDMA5_MPC/EDMA5_4) */ uint8_t RESERVED_0[8]; __IO uint32_t MP_STOPCH; /**< Stop Channel, offset: 0x20 */ uint8_t RESERVED_1[12]; __I uint32_t MP_SSR_LOW; /**< Stop Status, offset: 0x30 */ __I uint32_t MP_SSR_HIGH; /**< Stop Status, offset: 0x34, available only on: WAKEUP.EDMA5_MP2/EDMA5_2, WAKEUP.EDMA5_MP3/EDMA5_3 (missing on CAMERA.EDMA5_MPC/EDMA5_4) */ uint8_t RESERVED_2[200]; __IO uint32_t CH_GRPRI[64]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4, irregular array, not all indices are valid */ __IO uint32_t CH_MUX[64]; /**< Channel Multiplexor Configuration, array offset: 0x200, array step: 0x4, available only on: WAKEUP.EDMA5_MP2/EDMA5_2, WAKEUP.EDMA5_MP3/EDMA5_3 (missing on CAMERA.EDMA5_MPC/EDMA5_4) */ uint8_t RESERVED_3[256]; __IO uint32_t CH_PROT[64]; /**< Channel Protection, array offset: 0x400, array step: 0x4, irregular array, not all indices are valid */ uint8_t RESERVED_4[64256]; struct { /* offset: 0x10000, array step: 0x8000 */ __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x8000, irregular array, not all indices are valid */ uint8_t RESERVED_0[4]; __IO uint32_t CH_MATTR; /**< Memory Attributes, array offset: 0x10018, array step: 0x8000, irregular array, not all indices are valid */ uint8_t RESERVED_1[4]; __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x10020, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t SADDR_HIGH; /**< TCD Source Address, array offset: 0x10024, array step: 0x8000, irregular array, not all indices are valid */ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x10028, array step: 0x8000, irregular array, not all indices are valid */ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1002A, array step: 0x8000, irregular array, not all indices are valid */ union { /* offset: 0x1002C, array step: 0x8000 */ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Transfer Size without Minor Loop Offsets, array offset: 0x1002C, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1002C, array step: 0x8000, irregular array, not all indices are valid */ }; __IO uint32_t SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x10030, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t SLAST_SDA_HIGH; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x10034, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x10038, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t DADDR_HIGH; /**< TCD Destination Address, array offset: 0x1003C, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x10040, array step: 0x8000, irregular array, not all indices are valid */ __IO uint32_t DLAST_SGA_HIGH; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10044, array step: 0x8000, irregular array, not all indices are valid */ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x10048, array step: 0x8000, irregular array, not all indices are valid */ union { /* offset: 0x1004A, array step: 0x8000 */ __IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1004A, array step: 0x8000, irregular array, not all indices are valid */ __IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1004A, array step: 0x8000, irregular array, not all indices are valid */ }; __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x1004C, array step: 0x8000, irregular array, not all indices are valid */ union { /* offset: 0x1004E, array step: 0x8000 */ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1004E, array step: 0x8000, irregular array, not all indices are valid */ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1004E, array step: 0x8000, irregular array, not all indices are valid */ }; uint8_t RESERVED_2[32688]; } TCD[64]; } DMA5_Type; /* ---------------------------------------------------------------------------- -- DMA5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA5_Register_Masks DMA5 Register Masks * @{ */ /*! @name MP_CSR - Management Page Control */ /*! @{ */ #define DMA5_MP_CSR_EDBG_MASK (0x2U) #define DMA5_MP_CSR_EDBG_SHIFT (1U) /*! EDBG - Enable Debug * 0b0..Disable * 0b1..Enable */ #define DMA5_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_EDBG_SHIFT)) & DMA5_MP_CSR_EDBG_MASK) #define DMA5_MP_CSR_ERCA_MASK (0x4U) #define DMA5_MP_CSR_ERCA_SHIFT (2U) /*! ERCA - Enable Round Robin Channel Arbitration * 0b0..Disable * 0b1..Enable */ #define DMA5_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_ERCA_SHIFT)) & DMA5_MP_CSR_ERCA_MASK) #define DMA5_MP_CSR_GCPC_MASK (0x8U) #define DMA5_MP_CSR_GCPC_SHIFT (3U) /*! GCPC - Global Channel Preemption Control * 0b1..Available for each channel group * 0b0..Disabled for all channels */ #define DMA5_MP_CSR_GCPC(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_GCPC_SHIFT)) & DMA5_MP_CSR_GCPC_MASK) #define DMA5_MP_CSR_HAE_MASK (0x10U) #define DMA5_MP_CSR_HAE_SHIFT (4U) /*! HAE - Halt After Error * 0b0..Normal operation * 0b1..Halt */ #define DMA5_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_HAE_SHIFT)) & DMA5_MP_CSR_HAE_MASK) #define DMA5_MP_CSR_HALT_MASK (0x20U) #define DMA5_MP_CSR_HALT_SHIFT (5U) /*! HALT - Halt DMA Operations * 0b0..Normal operation * 0b1..Halt operation */ #define DMA5_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_HALT_SHIFT)) & DMA5_MP_CSR_HALT_MASK) #define DMA5_MP_CSR_GCLC_MASK (0x40U) #define DMA5_MP_CSR_GCLC_SHIFT (6U) /*! GCLC - Global Channel Linking Control * 0b0..Disabled * 0b1..Available */ #define DMA5_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_GCLC_SHIFT)) & DMA5_MP_CSR_GCLC_MASK) #define DMA5_MP_CSR_GMRC_MASK (0x80U) #define DMA5_MP_CSR_GMRC_SHIFT (7U) /*! GMRC - Global Master ID Replication Control * 0b0..Disabled * 0b1..Available */ #define DMA5_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_GMRC_SHIFT)) & DMA5_MP_CSR_GMRC_MASK) #define DMA5_MP_CSR_VER_MASK (0xFF0000U) #define DMA5_MP_CSR_VER_SHIFT (16U) /*! VER - eDMA Version */ #define DMA5_MP_CSR_VER(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_VER_SHIFT)) & DMA5_MP_CSR_VER_MASK) #define DMA5_MP_CSR_ACTIVE_ID_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_MP_CSR_ACTIVE_ID_SHIFT (24U) /*! ACTIVE_ID - Active Channel ID */ #define DMA5_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_ACTIVE_ID_SHIFT)) & DMA5_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_MP_CSR_ACTIVE_MASK (0x80000000U) #define DMA5_MP_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - DMA Active Status * 0b0..Idle * 0b1..Executing */ #define DMA5_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_CSR_ACTIVE_SHIFT)) & DMA5_MP_CSR_ACTIVE_MASK) /*! @} */ /*! @name MP_ES - Management Page Error Status */ /*! @{ */ #define DMA5_MP_ES_DBE_MASK (0x1U) #define DMA5_MP_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No error * 0b1..Error */ #define DMA5_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_DBE_SHIFT)) & DMA5_MP_ES_DBE_MASK) #define DMA5_MP_ES_SBE_MASK (0x2U) #define DMA5_MP_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No error * 0b1..Error */ #define DMA5_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_SBE_SHIFT)) & DMA5_MP_ES_SBE_MASK) #define DMA5_MP_ES_SGE_MASK (0x4U) #define DMA5_MP_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No error detected * 0b1..Error detected */ #define DMA5_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_SGE_SHIFT)) & DMA5_MP_ES_SGE_MASK) #define DMA5_MP_ES_NCE_MASK (0x8U) #define DMA5_MP_ES_NCE_SHIFT (3U) /*! NCE - NBYTES or CITER Configuration Error * 0b0..No error detected * 0b1..Error detected */ #define DMA5_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_NCE_SHIFT)) & DMA5_MP_ES_NCE_MASK) #define DMA5_MP_ES_DOE_MASK (0x10U) #define DMA5_MP_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No error detected * 0b1..Error detected */ #define DMA5_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_DOE_SHIFT)) & DMA5_MP_ES_DOE_MASK) #define DMA5_MP_ES_DAE_MASK (0x20U) #define DMA5_MP_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No error detected * 0b1..Error detected */ #define DMA5_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_DAE_SHIFT)) & DMA5_MP_ES_DAE_MASK) #define DMA5_MP_ES_SOE_MASK (0x40U) #define DMA5_MP_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No error detected * 0b1..Error detected */ #define DMA5_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_SOE_SHIFT)) & DMA5_MP_ES_SOE_MASK) #define DMA5_MP_ES_SAE_MASK (0x80U) #define DMA5_MP_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No error detected * 0b1..Error detected */ #define DMA5_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_SAE_SHIFT)) & DMA5_MP_ES_SAE_MASK) #define DMA5_MP_ES_ECX_MASK (0x100U) #define DMA5_MP_ES_ECX_SHIFT (8U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..Canceled transfer */ #define DMA5_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_ECX_SHIFT)) & DMA5_MP_ES_ECX_MASK) #define DMA5_MP_ES_UCE_MASK (0x200U) #define DMA5_MP_ES_UCE_SHIFT (9U) /*! UCE - Uncorrectable TCD Error during Channel Execution * 0b0..No error * 0b1..TCD RAM error */ #define DMA5_MP_ES_UCE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_UCE_SHIFT)) & DMA5_MP_ES_UCE_MASK) #define DMA5_MP_ES_ERRCHN_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_MP_ES_ERRCHN_SHIFT (24U) /*! ERRCHN - Error Channel Number or Canceled Channel Number */ #define DMA5_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_ERRCHN_SHIFT)) & DMA5_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_MP_ES_VLD_MASK (0x80000000U) #define DMA5_MP_ES_VLD_SHIFT (31U) /*! VLD - Valid * 0b0..No bits are set * 0b1..At least one bit is set */ #define DMA5_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_ES_VLD_SHIFT)) & DMA5_MP_ES_VLD_MASK) /*! @} */ /*! @name MP_INT_LOW - Management Page Interrupt Request Status */ /*! @{ */ #define DMA5_MP_INT_LOW_INT_MASK (0xFFFFFFFFU) #define DMA5_MP_INT_LOW_INT_SHIFT (0U) /*! INT - Interrupt Request Status */ #define DMA5_MP_INT_LOW_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_INT_LOW_INT_SHIFT)) & DMA5_MP_INT_LOW_INT_MASK) /*! @} */ /*! @name MP_INT_HIGH - Management Page Interrupt Request Status */ /*! @{ */ #define DMA5_MP_INT_HIGH_INT_MASK (0xFFFFFFFFU) #define DMA5_MP_INT_HIGH_INT_SHIFT (0U) /*! INT - Interrupt Request Status */ #define DMA5_MP_INT_HIGH_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_INT_HIGH_INT_SHIFT)) & DMA5_MP_INT_HIGH_INT_MASK) /*! @} */ /*! @name MP_HRS_LOW - Hardware Request Status */ /*! @{ */ #define DMA5_MP_HRS_LOW_HRS_MASK (0xFFFFFFFFU) #define DMA5_MP_HRS_LOW_HRS_SHIFT (0U) /*! HRS - Hardware Request Status */ #define DMA5_MP_HRS_LOW_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_HRS_LOW_HRS_SHIFT)) & DMA5_MP_HRS_LOW_HRS_MASK) /*! @} */ /*! @name MP_HRS_HIGH - Hardware Request Status */ /*! @{ */ #define DMA5_MP_HRS_HIGH_HRS_MASK (0xFFFFFFFFU) #define DMA5_MP_HRS_HIGH_HRS_SHIFT (0U) /*! HRS - Hardware Request Status */ #define DMA5_MP_HRS_HIGH_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_HRS_HIGH_HRS_SHIFT)) & DMA5_MP_HRS_HIGH_HRS_MASK) /*! @} */ /*! @name MP_STOPCH - Stop Channel */ /*! @{ */ #define DMA5_MP_STOPCH_STOPCH_MASK (0x3FU) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_MP_STOPCH_STOPCH_SHIFT (0U) /*! STOPCH - Stop Channel */ #define DMA5_MP_STOPCH_STOPCH(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_STOPCH_STOPCH_SHIFT)) & DMA5_MP_STOPCH_STOPCH_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_MP_STOPCH_ERR_MASK (0x80U) #define DMA5_MP_STOPCH_ERR_SHIFT (7U) /*! ERR - Stop Channel with Error Exit * 0b0..Disable * 0b1..Enable */ #define DMA5_MP_STOPCH_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_STOPCH_ERR_SHIFT)) & DMA5_MP_STOPCH_ERR_MASK) /*! @} */ /*! @name MP_SSR_LOW - Stop Status */ /*! @{ */ #define DMA5_MP_SSR_LOW_CSS_MASK (0xFFFFFFFFU) #define DMA5_MP_SSR_LOW_CSS_SHIFT (0U) /*! CSS - Channel Stop Status */ #define DMA5_MP_SSR_LOW_CSS(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_SSR_LOW_CSS_SHIFT)) & DMA5_MP_SSR_LOW_CSS_MASK) /*! @} */ /*! @name MP_SSR_HIGH - Stop Status */ /*! @{ */ #define DMA5_MP_SSR_HIGH_CSS_MASK (0xFFFFFFFFU) #define DMA5_MP_SSR_HIGH_CSS_SHIFT (0U) /*! CSS - Channel Stop Status */ #define DMA5_MP_SSR_HIGH_CSS(x) (((uint32_t)(((uint32_t)(x)) << DMA5_MP_SSR_HIGH_CSS_SHIFT)) & DMA5_MP_SSR_HIGH_CSS_MASK) /*! @} */ /*! @name CH_GRPRI - Channel Arbitration Group */ /*! @{ */ #define DMA5_CH_GRPRI_GRPRI_MASK (0x3FU) #define DMA5_CH_GRPRI_GRPRI_SHIFT (0U) /*! GRPRI - Arbitration Group Per Channel */ #define DMA5_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_GRPRI_GRPRI_SHIFT)) & DMA5_CH_GRPRI_GRPRI_MASK) /*! @} */ /* The count of DMA5_CH_GRPRI */ #define DMA5_CH_GRPRI_COUNT (64U) /*! @name CH_MUX - Channel Multiplexor Configuration */ /*! @{ */ #define DMA5_CH_MUX_SRC_MASK (0x7FU) #define DMA5_CH_MUX_SRC_SHIFT (0U) /*! SRC - Service Request Source */ #define DMA5_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MUX_SRC_SHIFT)) & DMA5_CH_MUX_SRC_MASK) /*! @} */ /* The count of DMA5_CH_MUX */ #define DMA5_CH_MUX_COUNT (64U) /*! @name CH_PROT - Channel Protection */ /*! @{ */ #define DMA5_CH_PROT_MID_MASK (0x1FU) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ #define DMA5_CH_PROT_MID_SHIFT (0U) /*! MID - Master ID */ #define DMA5_CH_PROT_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PROT_MID_SHIFT)) & DMA5_CH_PROT_MID_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ #define DMA5_CH_PROT_INSTR_MASK (0x2000U) #define DMA5_CH_PROT_INSTR_SHIFT (13U) /*! INSTR - Instruction or Data Access * 0b0..Data access * 0b1..Instruction access */ #define DMA5_CH_PROT_INSTR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PROT_INSTR_SHIFT)) & DMA5_CH_PROT_INSTR_MASK) #define DMA5_CH_PROT_SEC_MASK (0x4000U) #define DMA5_CH_PROT_SEC_SHIFT (14U) /*! SEC - Security Level * 0b0..Nonsecure * 0b1..Secure */ #define DMA5_CH_PROT_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PROT_SEC_SHIFT)) & DMA5_CH_PROT_SEC_MASK) #define DMA5_CH_PROT_PAL_MASK (0x8000U) #define DMA5_CH_PROT_PAL_SHIFT (15U) /*! PAL - Privileged Access Level * 0b0..User * 0b1..Privileged */ #define DMA5_CH_PROT_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PROT_PAL_SHIFT)) & DMA5_CH_PROT_PAL_MASK) #define DMA5_CH_PROT_EMI_MASK (0x10000U) #define DMA5_CH_PROT_EMI_SHIFT (16U) /*! EMI - Enable Master ID Replication * 0b0..Disable * 0b1..Enable */ #define DMA5_CH_PROT_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PROT_EMI_SHIFT)) & DMA5_CH_PROT_EMI_MASK) /*! @} */ /* The count of DMA5_CH_PROT */ #define DMA5_CH_PROT_COUNT (64U) /*! @name CH_CSR - Channel Control and Status */ /*! @{ */ #define DMA5_CH_CSR_ERQ_MASK (0x1U) #define DMA5_CH_CSR_ERQ_SHIFT (0U) /*! ERQ - Enable DMA Request * 0b0..Disable * 0b1..Enable */ #define DMA5_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_ERQ_SHIFT)) & DMA5_CH_CSR_ERQ_MASK) #define DMA5_CH_CSR_EARQ_MASK (0x2U) #define DMA5_CH_CSR_EARQ_SHIFT (1U) /*! EARQ - Enable Asynchronous DMA Request in Stop Mode for Channel * 0b0..Disable * 0b1..Enable */ #define DMA5_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_EARQ_SHIFT)) & DMA5_CH_CSR_EARQ_MASK) #define DMA5_CH_CSR_EEI_MASK (0x4U) #define DMA5_CH_CSR_EEI_SHIFT (2U) /*! EEI - Enable Error Interrupt * 0b0..Do not generate * 0b1..Generate */ #define DMA5_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_EEI_SHIFT)) & DMA5_CH_CSR_EEI_MASK) #define DMA5_CH_CSR_CX_MASK (0x40U) #define DMA5_CH_CSR_CX_SHIFT (6U) /*! CX - Stop Transferring Data * 0b0..No operation * 0b1..Stop the channel; no error reporting */ #define DMA5_CH_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_CX_SHIFT)) & DMA5_CH_CSR_CX_MASK) #define DMA5_CH_CSR_ECX_MASK (0x80U) #define DMA5_CH_CSR_ECX_SHIFT (7U) /*! ECX - Stop Transferring Data and Set an Error Flag * 0b0..No operation * 0b1..Stop the channel with error reporting */ #define DMA5_CH_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_ECX_SHIFT)) & DMA5_CH_CSR_ECX_MASK) #define DMA5_CH_CSR_SWAP_MASK (0xF000U) #define DMA5_CH_CSR_SWAP_SHIFT (12U) /*! SWAP - Swap Size * 0b0000..Disabled * 0b0001..Read with 8-bit swap * 0b0010..Read with 16-bit swap * 0b0011..Read with 32-bit swap * 0b0100..Read with 64-bit swap * 0b0101-0b1000..Reserved * 0b1001..Write with 8-bit swap * 0b1010..Write with 16-bit swap * 0b1011..Write with 32-bit swap * 0b1100..Write with 64-bit swap * 0b1101-0b1111..Reserved */ #define DMA5_CH_CSR_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_SWAP_SHIFT)) & DMA5_CH_CSR_SWAP_MASK) #define DMA5_CH_CSR_SIGNEXT_MASK (0x7F0000U) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define DMA5_CH_CSR_SIGNEXT_SHIFT (16U) /*! SIGNEXT - Sign Extension * 0b0000000..Sign extension disabled * 0b0000001..Nonzero value specifying the sign extend bit position */ #define DMA5_CH_CSR_SIGNEXT(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_SIGNEXT_SHIFT)) & DMA5_CH_CSR_SIGNEXT_MASK) /* Merged from fields with different position or width, of widths (6, 7), largest definition used */ #define DMA5_CH_CSR_DONE_MASK (0x40000000U) #define DMA5_CH_CSR_DONE_SHIFT (30U) /*! DONE - Channel Done Flag * 0b0..Not done * 0b1..Done * 0b0..No effect * 0b1..Clear the flag */ #define DMA5_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_DONE_SHIFT)) & DMA5_CH_CSR_DONE_MASK) #define DMA5_CH_CSR_ACTIVE_MASK (0x80000000U) #define DMA5_CH_CSR_ACTIVE_SHIFT (31U) /*! ACTIVE - Channel Active */ #define DMA5_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_CSR_ACTIVE_SHIFT)) & DMA5_CH_CSR_ACTIVE_MASK) /*! @} */ /* The count of DMA5_CH_CSR */ #define DMA5_CH_CSR_COUNT (64U) /*! @name CH_ES - Channel Error Status */ /*! @{ */ #define DMA5_CH_ES_DBE_MASK (0x1U) #define DMA5_CH_ES_DBE_SHIFT (0U) /*! DBE - Destination Bus Error * 0b0..No error * 0b1..Error */ #define DMA5_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_DBE_SHIFT)) & DMA5_CH_ES_DBE_MASK) #define DMA5_CH_ES_SBE_MASK (0x2U) #define DMA5_CH_ES_SBE_SHIFT (1U) /*! SBE - Source Bus Error * 0b0..No error * 0b1..Error */ #define DMA5_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_SBE_SHIFT)) & DMA5_CH_ES_SBE_MASK) #define DMA5_CH_ES_SGE_MASK (0x4U) #define DMA5_CH_ES_SGE_SHIFT (2U) /*! SGE - Scatter/Gather Configuration Error * 0b0..No error * 0b1..Error detected */ #define DMA5_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_SGE_SHIFT)) & DMA5_CH_ES_SGE_MASK) #define DMA5_CH_ES_NCE_MASK (0x8U) #define DMA5_CH_ES_NCE_SHIFT (3U) /*! NCE - NBYTES or CITER Configuration Error * 0b0..No error * 0b1..Error detected */ #define DMA5_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_NCE_SHIFT)) & DMA5_CH_ES_NCE_MASK) #define DMA5_CH_ES_DOE_MASK (0x10U) #define DMA5_CH_ES_DOE_SHIFT (4U) /*! DOE - Destination Offset Error * 0b0..No error * 0b1..Error detected */ #define DMA5_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_DOE_SHIFT)) & DMA5_CH_ES_DOE_MASK) #define DMA5_CH_ES_DAE_MASK (0x20U) #define DMA5_CH_ES_DAE_SHIFT (5U) /*! DAE - Destination Address Error * 0b0..No error * 0b1..Error detected */ #define DMA5_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_DAE_SHIFT)) & DMA5_CH_ES_DAE_MASK) #define DMA5_CH_ES_SOE_MASK (0x40U) #define DMA5_CH_ES_SOE_SHIFT (6U) /*! SOE - Source Offset Error * 0b0..No error * 0b1..Error detected */ #define DMA5_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_SOE_SHIFT)) & DMA5_CH_ES_SOE_MASK) #define DMA5_CH_ES_SAE_MASK (0x80U) #define DMA5_CH_ES_SAE_SHIFT (7U) /*! SAE - Source Address Error * 0b0..No error * 0b1..Error detected */ #define DMA5_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_SAE_SHIFT)) & DMA5_CH_ES_SAE_MASK) #define DMA5_CH_ES_ECX_MASK (0x100U) #define DMA5_CH_ES_ECX_SHIFT (8U) /*! ECX - Transfer Canceled * 0b0..No canceled transfers * 0b1..Canceled transfer */ #define DMA5_CH_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_ECX_SHIFT)) & DMA5_CH_ES_ECX_MASK) #define DMA5_CH_ES_UCE_MASK (0x200U) #define DMA5_CH_ES_UCE_SHIFT (9U) /*! UCE - Uncorrectable TCD Error During Channel Execution * 0b0..Not an error * 0b1..Error */ #define DMA5_CH_ES_UCE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_UCE_SHIFT)) & DMA5_CH_ES_UCE_MASK) #define DMA5_CH_ES_ERR_MASK (0x80000000U) #define DMA5_CH_ES_ERR_SHIFT (31U) /*! ERR - Error in Channel * 0b0..Not occurred * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define DMA5_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_ES_ERR_SHIFT)) & DMA5_CH_ES_ERR_MASK) /*! @} */ /* The count of DMA5_CH_ES */ #define DMA5_CH_ES_COUNT (64U) /*! @name CH_INT - Channel Interrupt Status */ /*! @{ */ #define DMA5_CH_INT_INT_MASK (0x1U) #define DMA5_CH_INT_INT_SHIFT (0U) /*! INT - Interrupt Request * 0b0..Cleared * 0b1..Active * 0b0..No effect * 0b1..Clear the flag */ #define DMA5_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_INT_INT_SHIFT)) & DMA5_CH_INT_INT_MASK) /*! @} */ /* The count of DMA5_CH_INT */ #define DMA5_CH_INT_COUNT (64U) /*! @name CH_SBR - Channel System Bus */ /*! @{ */ #define DMA5_CH_SBR_MID_MASK (0x1FU) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ #define DMA5_CH_SBR_MID_SHIFT (0U) /*! MID - Master ID */ #define DMA5_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_SBR_MID_SHIFT)) & DMA5_CH_SBR_MID_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ #define DMA5_CH_SBR_INSTR_MASK (0x2000U) #define DMA5_CH_SBR_INSTR_SHIFT (13U) /*! INSTR - Instruction or Data Access * 0b0..Data access * 0b1..Instruction access */ #define DMA5_CH_SBR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_SBR_INSTR_SHIFT)) & DMA5_CH_SBR_INSTR_MASK) #define DMA5_CH_SBR_PAL_MASK (0x8000U) #define DMA5_CH_SBR_PAL_SHIFT (15U) /*! PAL - Privileged Access Level * 0b0..User protection * 0b1..Privileged protection */ #define DMA5_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_SBR_PAL_SHIFT)) & DMA5_CH_SBR_PAL_MASK) #define DMA5_CH_SBR_EMI_MASK (0x10000U) #define DMA5_CH_SBR_EMI_SHIFT (16U) /*! EMI - Enable Master ID Replication * 0b0..Disable * 0b1..Enable */ #define DMA5_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_SBR_EMI_SHIFT)) & DMA5_CH_SBR_EMI_MASK) #define DMA5_CH_SBR_ATTR_MASK (0x7E0000U) /* Merged from fields with different position or width, of widths (4, 6), largest definition used */ #define DMA5_CH_SBR_ATTR_SHIFT (17U) /*! ATTR - Attribute Output */ #define DMA5_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_SBR_ATTR_SHIFT)) & DMA5_CH_SBR_ATTR_MASK) /* Merged from fields with different position or width, of widths (4, 6), largest definition used */ /*! @} */ /* The count of DMA5_CH_SBR */ #define DMA5_CH_SBR_COUNT (64U) /*! @name CH_PRI - Channel Priority */ /*! @{ */ #define DMA5_CH_PRI_APL_MASK (0x7U) #define DMA5_CH_PRI_APL_SHIFT (0U) /*! APL - Arbitration Priority Level */ #define DMA5_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PRI_APL_SHIFT)) & DMA5_CH_PRI_APL_MASK) #define DMA5_CH_PRI_DPA_MASK (0x40000000U) #define DMA5_CH_PRI_DPA_SHIFT (30U) /*! DPA - Disable Preempt Ability * 0b0..Can suspend a lower priority channel * 0b1..Cannot suspend */ #define DMA5_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PRI_DPA_SHIFT)) & DMA5_CH_PRI_DPA_MASK) #define DMA5_CH_PRI_ECP_MASK (0x80000000U) #define DMA5_CH_PRI_ECP_SHIFT (31U) /*! ECP - Enable Channel Preemption * 0b0..Cannot be suspended * 0b1..Can be temporarily suspended */ #define DMA5_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_PRI_ECP_SHIFT)) & DMA5_CH_PRI_ECP_MASK) /*! @} */ /* The count of DMA5_CH_PRI */ #define DMA5_CH_PRI_COUNT (64U) /*! @name CH_MATTR - Memory Attributes */ /*! @{ */ #define DMA5_CH_MATTR_RCACHE_MASK (0xFU) #define DMA5_CH_MATTR_RCACHE_SHIFT (0U) /*! RCACHE - Read Cache Attributes */ #define DMA5_CH_MATTR_RCACHE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_RCACHE_SHIFT)) & DMA5_CH_MATTR_RCACHE_MASK) #define DMA5_CH_MATTR_WCACHE_MASK (0xF0U) #define DMA5_CH_MATTR_WCACHE_SHIFT (4U) /*! WCACHE - Write Cache Attributes */ #define DMA5_CH_MATTR_WCACHE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_WCACHE_SHIFT)) & DMA5_CH_MATTR_WCACHE_MASK) #define DMA5_CH_MATTR_RDOMAINS_MASK (0x300U) #define DMA5_CH_MATTR_RDOMAINS_SHIFT (8U) /*! RDOMAINS - Read Domain * 0b00..Domain is Non-shareable * 0b01..Domain is Inner shareable * 0b10..Domain is Outer Shareable * 0b11..Reserved */ #define DMA5_CH_MATTR_RDOMAINS(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_RDOMAINS_SHIFT)) & DMA5_CH_MATTR_RDOMAINS_MASK) #define DMA5_CH_MATTR_WDOMAINS_MASK (0xC00U) #define DMA5_CH_MATTR_WDOMAINS_SHIFT (10U) /*! WDOMAINS - Write Domain * 0b00..Domain is Non-shareable * 0b01..Domain is Inner shareable * 0b10..Domain is Outer Shareable * 0b11..Reserved */ #define DMA5_CH_MATTR_WDOMAINS(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_WDOMAINS_SHIFT)) & DMA5_CH_MATTR_WDOMAINS_MASK) #define DMA5_CH_MATTR_WSNOOPS_MASK (0xF000U) #define DMA5_CH_MATTR_WSNOOPS_SHIFT (12U) /*! WSNOOPS - Write Snoop Transaction Type */ #define DMA5_CH_MATTR_WSNOOPS(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_WSNOOPS_SHIFT)) & DMA5_CH_MATTR_WSNOOPS_MASK) #define DMA5_CH_MATTR_WSENB_MASK (0x10000U) #define DMA5_CH_MATTR_WSENB_SHIFT (16U) /*! WSENB - Stash Local Processor Enable * 0b0..Write stash target is disabled * 0b1..Write stash target is enabled */ #define DMA5_CH_MATTR_WSENB(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_WSENB_SHIFT)) & DMA5_CH_MATTR_WSENB_MASK) #define DMA5_CH_MATTR_WSTHRD_MASK (0x20000U) #define DMA5_CH_MATTR_WSTHRD_SHIFT (17U) /*! WSTHRD - Stash Local Processor Thread */ #define DMA5_CH_MATTR_WSTHRD(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_WSTHRD_SHIFT)) & DMA5_CH_MATTR_WSTHRD_MASK) #define DMA5_CH_MATTR_WSCORE_MASK (0x3C0000U) #define DMA5_CH_MATTR_WSCORE_SHIFT (18U) /*! WSCORE - Stash Local Processor ID */ #define DMA5_CH_MATTR_WSCORE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_CH_MATTR_WSCORE_SHIFT)) & DMA5_CH_MATTR_WSCORE_MASK) /*! @} */ /* The count of DMA5_CH_MATTR */ #define DMA5_CH_MATTR_COUNT (64U) /*! @name SADDR - TCD Source Address */ /*! @{ */ #define DMA5_SADDR_SADDR_MASK (0xFFFFFFFFU) #define DMA5_SADDR_SADDR_SHIFT (0U) /*! SADDR - Source Address bits */ #define DMA5_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_SADDR_SADDR_SHIFT)) & DMA5_SADDR_SADDR_MASK) /*! @} */ /* The count of DMA5_SADDR */ #define DMA5_SADDR_COUNT (64U) /*! @name SADDR_HIGH - TCD Source Address */ /*! @{ */ #define DMA5_SADDR_HIGH_SADDR_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ #define DMA5_SADDR_HIGH_SADDR_SHIFT (0U) /*! SADDR - Source Address */ #define DMA5_SADDR_HIGH_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_SADDR_HIGH_SADDR_SHIFT)) & DMA5_SADDR_HIGH_SADDR_MASK) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ /*! @} */ /* The count of DMA5_SADDR_HIGH */ #define DMA5_SADDR_HIGH_COUNT (64U) /*! @name SOFF - TCD Signed Source Address Offset */ /*! @{ */ #define DMA5_SOFF_SOFF_MASK (0xFFFFU) #define DMA5_SOFF_SOFF_SHIFT (0U) /*! SOFF - Source Address Signed Offset */ #define DMA5_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA5_SOFF_SOFF_SHIFT)) & DMA5_SOFF_SOFF_MASK) /*! @} */ /* The count of DMA5_SOFF */ #define DMA5_SOFF_COUNT (64U) /*! @name ATTR - TCD Transfer Attributes */ /*! @{ */ #define DMA5_ATTR_DSIZE_MASK (0x7U) #define DMA5_ATTR_DSIZE_SHIFT (0U) /*! DSIZE - Destination Data Transfer Size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100..16-byte * 0b101..32-byte * 0b110..64-byte * 0b111..128-byte */ #define DMA5_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA5_ATTR_DSIZE_SHIFT)) & DMA5_ATTR_DSIZE_MASK) #define DMA5_ATTR_DMOD_MASK (0xF8U) #define DMA5_ATTR_DMOD_SHIFT (3U) /*! DMOD - Destination Address Modulo */ #define DMA5_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA5_ATTR_DMOD_SHIFT)) & DMA5_ATTR_DMOD_MASK) #define DMA5_ATTR_SSIZE_MASK (0x700U) #define DMA5_ATTR_SSIZE_SHIFT (8U) /*! SSIZE - Source Data Transfer Size * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100..16-byte * 0b101..32-byte * 0b110..64-byte * 0b111..128-byte */ #define DMA5_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA5_ATTR_SSIZE_SHIFT)) & DMA5_ATTR_SSIZE_MASK) #define DMA5_ATTR_SMOD_MASK (0xF800U) #define DMA5_ATTR_SMOD_SHIFT (11U) /*! SMOD - Source Address Modulo * 0b00000..Disable * 0b00001..Enable */ #define DMA5_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA5_ATTR_SMOD_SHIFT)) & DMA5_ATTR_SMOD_MASK) /*! @} */ /* The count of DMA5_ATTR */ #define DMA5_ATTR_COUNT (64U) /*! @name NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets */ /*! @{ */ #define DMA5_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) #define DMA5_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes to Transfer Per Service Request */ #define DMA5_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA5_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA5_NBYTES_MLOFFNO_NBYTES_MASK) #define DMA5_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) #define DMA5_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..Do not apply * 0b1..Apply */ #define DMA5_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA5_NBYTES_MLOFFNO_DMLOE_MASK) #define DMA5_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) #define DMA5_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..Do not apply * 0b1..Apply */ #define DMA5_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA5_NBYTES_MLOFFNO_SMLOE_MASK) /*! @} */ /* The count of DMA5_NBYTES_MLOFFNO */ #define DMA5_NBYTES_MLOFFNO_COUNT (64U) /*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ /*! @{ */ #define DMA5_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) #define DMA5_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) /*! NBYTES - Number of Bytes to Transfer Per Service Request */ #define DMA5_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA5_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA5_NBYTES_MLOFFYES_NBYTES_MASK) #define DMA5_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) #define DMA5_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) /*! MLOFF - Minor Loop Offset */ #define DMA5_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA5_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA5_NBYTES_MLOFFYES_MLOFF_MASK) #define DMA5_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) #define DMA5_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) /*! DMLOE - Destination Minor Loop Offset Enable * 0b0..Do not apply * 0b1..Apply */ #define DMA5_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA5_NBYTES_MLOFFYES_DMLOE_MASK) #define DMA5_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) #define DMA5_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) /*! SMLOE - Source Minor Loop Offset Enable * 0b0..Do not apply * 0b1..Apply */ #define DMA5_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA5_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA5_NBYTES_MLOFFYES_SMLOE_MASK) /*! @} */ /* The count of DMA5_NBYTES_MLOFFYES */ #define DMA5_NBYTES_MLOFFYES_COUNT (64U) /*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ /*! @{ */ #define DMA5_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) #define DMA5_SLAST_SDA_SLAST_SDA_SHIFT (0U) /*! SLAST_SDA - Last Source Address Adjustment and Store DADDR Address */ #define DMA5_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA5_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA5_SLAST_SDA_SLAST_SDA_MASK) /*! @} */ /* The count of DMA5_SLAST_SDA */ #define DMA5_SLAST_SDA_COUNT (64U) /*! @name SLAST_SDA_HIGH - TCD Last Source Address Adjustment / Store DADDR Address */ /*! @{ */ #define DMA5_SLAST_SDA_HIGH_SLAST_SDA_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ #define DMA5_SLAST_SDA_HIGH_SLAST_SDA_SHIFT (0U) /*! SLAST_SDA - Last Source Address Adjustment and Store DADDR Address */ #define DMA5_SLAST_SDA_HIGH_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA5_SLAST_SDA_HIGH_SLAST_SDA_SHIFT)) & DMA5_SLAST_SDA_HIGH_SLAST_SDA_MASK) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ /*! @} */ /* The count of DMA5_SLAST_SDA_HIGH */ #define DMA5_SLAST_SDA_HIGH_COUNT (64U) /*! @name DADDR - TCD Destination Address */ /*! @{ */ #define DMA5_DADDR_DADDR_MASK (0xFFFFFFFFU) #define DMA5_DADDR_DADDR_SHIFT (0U) /*! DADDR - Destination Address */ #define DMA5_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_DADDR_DADDR_SHIFT)) & DMA5_DADDR_DADDR_MASK) /*! @} */ /* The count of DMA5_DADDR */ #define DMA5_DADDR_COUNT (64U) /*! @name DADDR_HIGH - TCD Destination Address */ /*! @{ */ #define DMA5_DADDR_HIGH_DADDR_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ #define DMA5_DADDR_HIGH_DADDR_SHIFT (0U) /*! DADDR - Destination Address */ #define DMA5_DADDR_HIGH_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA5_DADDR_HIGH_DADDR_SHIFT)) & DMA5_DADDR_HIGH_DADDR_MASK) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ /*! @} */ /* The count of DMA5_DADDR_HIGH */ #define DMA5_DADDR_HIGH_COUNT (64U) /*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */ /*! @{ */ #define DMA5_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) #define DMA5_DLAST_SGA_DLAST_SGA_SHIFT (0U) /*! DLAST_SGA - Final Destination Address Adjustment and Scatter Gather Address */ #define DMA5_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA5_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA5_DLAST_SGA_DLAST_SGA_MASK) /*! @} */ /* The count of DMA5_DLAST_SGA */ #define DMA5_DLAST_SGA_COUNT (64U) /*! @name DLAST_SGA_HIGH - TCD Last Destination Address Adjustment / Scatter Gather Address */ /*! @{ */ #define DMA5_DLAST_SGA_HIGH_DLAST_SGA_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ #define DMA5_DLAST_SGA_HIGH_DLAST_SGA_SHIFT (0U) /*! DLAST_SGA - Final Destination Address Adjustment and Scatter Gather Address */ #define DMA5_DLAST_SGA_HIGH_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA5_DLAST_SGA_HIGH_DLAST_SGA_SHIFT)) & DMA5_DLAST_SGA_HIGH_DLAST_SGA_MASK) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ /*! @} */ /* The count of DMA5_DLAST_SGA_HIGH */ #define DMA5_DLAST_SGA_HIGH_COUNT (64U) /*! @name DOFF - TCD Signed Destination Address Offset */ /*! @{ */ #define DMA5_DOFF_DOFF_MASK (0xFFFFU) #define DMA5_DOFF_DOFF_SHIFT (0U) /*! DOFF - Destination Address Signed Offset */ #define DMA5_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA5_DOFF_DOFF_SHIFT)) & DMA5_DOFF_DOFF_MASK) /*! @} */ /* The count of DMA5_DOFF */ #define DMA5_DOFF_COUNT (64U) /*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA5_CITER_ELINKNO_CITER_MASK (0x7FFFU) #define DMA5_CITER_ELINKNO_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA5_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CITER_ELINKNO_CITER_SHIFT)) & DMA5_CITER_ELINKNO_CITER_MASK) #define DMA5_CITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA5_CITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enable Channel-to-Channel Linking on Minor-Loop Completion * 0b0..Disable * 0b1..Enable */ #define DMA5_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CITER_ELINKNO_ELINK_SHIFT)) & DMA5_CITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA5_CITER_ELINKNO */ #define DMA5_CITER_ELINKNO_COUNT (64U) /*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA5_CITER_ELINKYES_CITER_MASK (0x1FFU) #define DMA5_CITER_ELINKYES_CITER_SHIFT (0U) /*! CITER - Current Major Iteration Count */ #define DMA5_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CITER_ELINKYES_CITER_SHIFT)) & DMA5_CITER_ELINKYES_CITER_MASK) #define DMA5_CITER_ELINKYES_LINKCH_MASK (0x7E00U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_CITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Minor Loop Link Channel Number */ #define DMA5_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CITER_ELINKYES_LINKCH_SHIFT)) & DMA5_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_CITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA5_CITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enable Channel-to-Channel Linking on Minor-Loop Complete * 0b0..Disable * 0b1..Enable */ #define DMA5_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CITER_ELINKYES_ELINK_SHIFT)) & DMA5_CITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA5_CITER_ELINKYES */ #define DMA5_CITER_ELINKYES_COUNT (64U) /*! @name CSR - TCD Control and Status */ /*! @{ */ #define DMA5_CSR_START_MASK (0x1U) #define DMA5_CSR_START_SHIFT (0U) /*! START - Channel Start * 0b0..Not started * 0b1..Started */ #define DMA5_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_START_SHIFT)) & DMA5_CSR_START_MASK) #define DMA5_CSR_INTMAJOR_MASK (0x2U) #define DMA5_CSR_INTMAJOR_SHIFT (1U) /*! INTMAJOR - Enable an Interrupt when Major Iteration Count Completes * 0b0..Disable * 0b1..Enable */ #define DMA5_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_INTMAJOR_SHIFT)) & DMA5_CSR_INTMAJOR_MASK) #define DMA5_CSR_INTHALF_MASK (0x4U) #define DMA5_CSR_INTHALF_SHIFT (2U) /*! INTHALF - Enable an Interrupt when Major Counter is Half Complete * 0b0..Disable * 0b1..Enable */ #define DMA5_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_INTHALF_SHIFT)) & DMA5_CSR_INTHALF_MASK) #define DMA5_CSR_DREQ_MASK (0x8U) #define DMA5_CSR_DREQ_SHIFT (3U) /*! DREQ - Disable Request * 0b0..No operation * 0b1..Clear ERQ */ #define DMA5_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_DREQ_SHIFT)) & DMA5_CSR_DREQ_MASK) #define DMA5_CSR_ESG_MASK (0x10U) #define DMA5_CSR_ESG_SHIFT (4U) /*! ESG - Enable Scatter/Gather Processing * 0b0..Normal format * 0b1..Scatter/gather format */ #define DMA5_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_ESG_SHIFT)) & DMA5_CSR_ESG_MASK) #define DMA5_CSR_MAJORELINK_MASK (0x20U) #define DMA5_CSR_MAJORELINK_SHIFT (5U) /*! MAJORELINK - Enable Channel-to-Channel Linking on Major Loop Complete * 0b0..Disable * 0b1..Enable */ #define DMA5_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_MAJORELINK_SHIFT)) & DMA5_CSR_MAJORELINK_MASK) #define DMA5_CSR_EEOP_MASK (0x40U) #define DMA5_CSR_EEOP_SHIFT (6U) /*! EEOP - Enable End-of-Packet Processing * 0b0..Disable * 0b1..Enable */ #define DMA5_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_EEOP_SHIFT)) & DMA5_CSR_EEOP_MASK) #define DMA5_CSR_ESDA_MASK (0x80U) #define DMA5_CSR_ESDA_SHIFT (7U) /*! ESDA - Enable Store Destination Address * 0b0..Disable * 0b1..Enable */ #define DMA5_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_ESDA_SHIFT)) & DMA5_CSR_ESDA_MASK) #define DMA5_CSR_MAJORLINKCH_MASK (0x3F00U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_CSR_MAJORLINKCH_SHIFT (8U) /*! MAJORLINKCH - Major Loop Link Channel Number */ #define DMA5_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_MAJORLINKCH_SHIFT)) & DMA5_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_CSR_TMC_MASK (0xC000U) #define DMA5_CSR_TMC_SHIFT (14U) /*! TMC - Transfer Mode Control * 0b00..Read/Write * 0b01..Read-Only * 0b10..Write-Only * 0b11..Reserved */ #define DMA5_CSR_TMC(x) (((uint16_t)(((uint16_t)(x)) << DMA5_CSR_TMC_SHIFT)) & DMA5_CSR_TMC_MASK) /*! @} */ /* The count of DMA5_CSR */ #define DMA5_CSR_COUNT (64U) /*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ /*! @{ */ #define DMA5_BITER_ELINKNO_BITER_MASK (0x7FFFU) #define DMA5_BITER_ELINKNO_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA5_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA5_BITER_ELINKNO_BITER_SHIFT)) & DMA5_BITER_ELINKNO_BITER_MASK) #define DMA5_BITER_ELINKNO_ELINK_MASK (0x8000U) #define DMA5_BITER_ELINKNO_ELINK_SHIFT (15U) /*! ELINK - Enables Channel-to-Channel Linking on Minor Loop Complete * 0b0..Disable * 0b1..Enable */ #define DMA5_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA5_BITER_ELINKNO_ELINK_SHIFT)) & DMA5_BITER_ELINKNO_ELINK_MASK) /*! @} */ /* The count of DMA5_BITER_ELINKNO */ #define DMA5_BITER_ELINKNO_COUNT (64U) /*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ /*! @{ */ #define DMA5_BITER_ELINKYES_BITER_MASK (0x1FFU) #define DMA5_BITER_ELINKYES_BITER_SHIFT (0U) /*! BITER - Starting Major Iteration Count */ #define DMA5_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA5_BITER_ELINKYES_BITER_SHIFT)) & DMA5_BITER_ELINKYES_BITER_MASK) #define DMA5_BITER_ELINKYES_LINKCH_MASK (0x7E00U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_BITER_ELINKYES_LINKCH_SHIFT (9U) /*! LINKCH - Link Channel Number */ #define DMA5_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA5_BITER_ELINKYES_LINKCH_SHIFT)) & DMA5_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ #define DMA5_BITER_ELINKYES_ELINK_MASK (0x8000U) #define DMA5_BITER_ELINKYES_ELINK_SHIFT (15U) /*! ELINK - Enables Channel-to-Channel Linking on Minor Loop Complete * 0b0..Disable * 0b1..Enable */ #define DMA5_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA5_BITER_ELINKYES_ELINK_SHIFT)) & DMA5_BITER_ELINKYES_ELINK_MASK) /*! @} */ /* The count of DMA5_BITER_ELINKYES */ #define DMA5_BITER_ELINKYES_COUNT (64U) /*! * @} */ /* end of group DMA5_Register_Masks */ /* DMA5 - Peripheral instance base addresses */ /** Peripheral EDMA5_2 base address */ #define EDMA5_2_BASE (0x42000000u) /** Peripheral EDMA5_2 base pointer */ #define EDMA5_2 ((DMA5_Type *)EDMA5_2_BASE) /** Peripheral EDMA5_3 base address */ #define EDMA5_3_BASE (0x42210000u) /** Peripheral EDMA5_3 base pointer */ #define EDMA5_3 ((DMA5_Type *)EDMA5_3_BASE) /** Peripheral EDMA5_4 base address */ #define EDMA5_4_BASE (0x4AE10000u) /** Peripheral EDMA5_4 base pointer */ #define EDMA5_4 ((DMA5_Type *)EDMA5_4_BASE) /** Array initializer of DMA5 peripheral base addresses */ #define DMA5_BASE_ADDRS { 0u, 0u, EDMA5_2_BASE, EDMA5_3_BASE, EDMA5_4_BASE } /** Array initializer of DMA5 peripheral base pointers */ #define DMA5_BASE_PTRS { (DMA5_Type *)0u, (DMA5_Type *)0u, EDMA5_2, EDMA5_3, EDMA5_4 } /*! * @} */ /* end of group DMA5_Peripheral_Access_Layer */ /*! * @brief DPU IRQn. */ typedef enum DPU_IRQSTEER_IRQn { /* DISPLAY_INT_OUT0 */ CmdSeqError_DPU_IRQn = 0, SoftwareInt0_DPU_IRQn = 1, SoftwareInt1_DPU_IRQn = 2, SoftwareInt2_DPU_IRQn = 3, SoftwareInt3_DPU_IRQn = 4, /* DISPLAY_INT_OUT1 */ ExtDst0ShadowLoad_DPU_IRQn = 64, ExtDst0FrameComplete_DPU_IRQn = 65, ExtDst0SeqComplete_DPU_IRQn = 66, ExtDst4ShadowLoad_DPU_IRQn = 67, ExtDst4FrameComplete_DPU_IRQn = 68, ExtDst4SeqComplete_DPU_IRQn = 69, DomainBlend0_ShdLoad_DPU_IRQn = 70, DomainBlend0_FrameComplete_DPU_IRQn = 71, DomainBlend0_SeqComplete_DPU_IRQn = 72, Display0ShadowLoad_DPU_IRQn = 73, Display0FrameComplete_DPU_IRQn = 74, Display0SeqComplete_DPU_IRQn = 75, FrameGen0Int0_DPU_IRQn = 76, FrameGen0Int1_DPU_IRQn = 77, FrameGen0Int2_DPU_IRQn = 78, FrameGen0Int3_DPU_IRQn = 79, Sig0ShadowLoad_DPU_IRQn = 80, Sig0Valid_DPU_IRQn = 81, Sig0Error_DPU_IRQn = 82, FrameGen0PrimSyncOn_DPU_IRQn = 93, FrameGen0PrimSyncOff_DPU_IRQn = 94, /* DISPLAY_INT_OUT3 */ ExtDst1ShadowLoad_DPU_IRQn = 192, ExtDst1FrameComplete_DPU_IRQn = 193, ExtDst1SeqComplete_DPU_IRQn = 194, ExtDst5ShadowLoad_DPU_IRQn = 195, ExtDst5FrameComplete_DPU_IRQn = 196, ExtDst5SeqComplete_DPU_IRQn = 197, Display1ShadowLoad_DPU_IRQn = 201, Display1FrameComplete_DPU_IRQn = 202, Display1SeqComplete_DPU_IRQn = 203, FrameGen1Int0_DPU_IRQn = 204, FrameGen1Int1_DPU_IRQn = 205, FrameGen1Int2_DPU_IRQn = 206, FrameGen1Int3_DPU_IRQn = 207, Sig1ShadowLoad_DPU_IRQn = 208, Sig1Valid_DPU_IRQn = 209, Sig1Error_DPU_IRQn = 210, FrameGen1PrimSyncOn_DPU_IRQn = 213, FrameGen1PrimSyncOff_DPU_IRQn = 214, /* DISPLAY_INT_OUT7 */ Store9ShadowLoad_DPU_IRQn = 448, Store9FrameComplete_DPU_IRQn = 449, Store9SeqComplete_DPU_IRQn = 450, } DPU_IRQSTEER_IRQn_Type; /* ---------------------------------------------------------------------------- -- DPU_IRQSTEER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DPU_IRQSTEER_Peripheral_Access_Layer DPU_IRQSTEER Peripheral Access Layer * @{ */ /** DPU_IRQSTEER - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t CHN_MASK[16]; /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */ __IO uint32_t CHN_SET[16]; /**< Channel n Interrupt Set Register, array offset: 0x44, array step: 0x4 */ __I uint32_t CHN_STATUS[16]; /**< Channel n Interrupt Status Register, array offset: 0x84, array step: 0x4 */ __IO uint32_t CHN_MINTDIS; /**< Channel n Master Interrupt Disable Register., offset: 0xC4 */ __I uint32_t CHN_MSTRSTAT; /**< Channel n Master Status Register, offset: 0xC8 */ } DPU_IRQSTEER_Type; /* ---------------------------------------------------------------------------- -- DPU_IRQSTEER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DPU_IRQSTEER_Register_Masks DPU_IRQSTEER Register Masks * @{ */ /*! @name CHN_MASK - Channel n Interrupt Mask Register */ /*! @{ */ #define DPU_IRQSTEER_CHN_MASK_MASKFLD_MASK (0xFFFFFFFFU) #define DPU_IRQSTEER_CHN_MASK_MASKFLD_SHIFT (0U) /*! MASKFLD - Mask bits * 0b00000000000000000000000000000000..Mask interrupt * 0b00000000000000000000000000000001..Do not mask interrupt */ #define DPU_IRQSTEER_CHN_MASK_MASKFLD(x) (((uint32_t)(((uint32_t)(x)) << DPU_IRQSTEER_CHN_MASK_MASKFLD_SHIFT)) & DPU_IRQSTEER_CHN_MASK_MASKFLD_MASK) /*! @} */ /* The count of DPU_IRQSTEER_CHN_MASK */ #define DPU_IRQSTEER_CHN_MASK_COUNT (16U) /*! @name CHN_SET - Channel n Interrupt Set Register */ /*! @{ */ #define DPU_IRQSTEER_CHN_SET_FORCEFLD_MASK (0xFFFFFFFFU) #define DPU_IRQSTEER_CHN_SET_FORCEFLD_SHIFT (0U) /*! FORCEFLD - Force interrupt. * 0b00000000000000000000000000000000..Normal operation * 0b00000000000000000000000000000001..Force interrupt */ #define DPU_IRQSTEER_CHN_SET_FORCEFLD(x) (((uint32_t)(((uint32_t)(x)) << DPU_IRQSTEER_CHN_SET_FORCEFLD_SHIFT)) & DPU_IRQSTEER_CHN_SET_FORCEFLD_MASK) /*! @} */ /* The count of DPU_IRQSTEER_CHN_SET */ #define DPU_IRQSTEER_CHN_SET_COUNT (16U) /*! @name CHN_STATUS - Channel n Interrupt Status Register */ /*! @{ */ #define DPU_IRQSTEER_CHN_STATUS_STATUS_MASK (0xFFFFFFFFU) #define DPU_IRQSTEER_CHN_STATUS_STATUS_SHIFT (0U) /*! STATUS - Status of an interrupt * 0b00000000000000000000000000000000..Interrupt is not set. * 0b00000000000000000000000000000001..Interrupt is set. */ #define DPU_IRQSTEER_CHN_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DPU_IRQSTEER_CHN_STATUS_STATUS_SHIFT)) & DPU_IRQSTEER_CHN_STATUS_STATUS_MASK) /*! @} */ /* The count of DPU_IRQSTEER_CHN_STATUS */ #define DPU_IRQSTEER_CHN_STATUS_COUNT (16U) /*! @name CHN_MINTDIS - Channel n Master Interrupt Disable Register. */ /*! @{ */ #define DPU_IRQSTEER_CHN_MINTDIS_DISABLE_MASK (0xFFU) #define DPU_IRQSTEER_CHN_MINTDIS_DISABLE_SHIFT (0U) /*! DISABLE - Each bit of this field disables the corresponding interrupts in table above. * 0b00000000..Enable interrupts * 0b00000001..Disable interrupts */ #define DPU_IRQSTEER_CHN_MINTDIS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DPU_IRQSTEER_CHN_MINTDIS_DISABLE_SHIFT)) & DPU_IRQSTEER_CHN_MINTDIS_DISABLE_MASK) /*! @} */ /*! @name CHN_MSTRSTAT - Channel n Master Status Register */ /*! @{ */ #define DPU_IRQSTEER_CHN_MSTRSTAT_STATUS_MASK (0x1U) #define DPU_IRQSTEER_CHN_MSTRSTAT_STATUS_SHIFT (0U) /*! STATUS - Status of all interrupts * 0b0..No interrupts are asserted. * 0b1..At least one interrupt is asserted. */ #define DPU_IRQSTEER_CHN_MSTRSTAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DPU_IRQSTEER_CHN_MSTRSTAT_STATUS_SHIFT)) & DPU_IRQSTEER_CHN_MSTRSTAT_STATUS_MASK) /*! @} */ /*! * @} */ /* end of group DPU_IRQSTEER_Register_Masks */ /* DPU_IRQSTEER - Peripheral instance base addresses */ /** Peripheral DPU_IRQSTEER base address */ #define DPU_IRQSTEER_BASE (0x4B0B0000u) /** Peripheral DPU_IRQSTEER base pointer */ #define DPU_IRQSTEER ((DPU_IRQSTEER_Type *)DPU_IRQSTEER_BASE) /** Array initializer of DPU_IRQSTEER peripheral base addresses */ #define DPU_IRQSTEER_BASE_ADDRS { DPU_IRQSTEER_BASE } /** Array initializer of DPU_IRQSTEER peripheral base pointers */ #define DPU_IRQSTEER_BASE_PTRS { DPU_IRQSTEER } /* Backward compatibility */ #define DPU_IRQSTEER_IRQS { DISP_IRQSTEER0_IRQn, DISP_IRQSTEER1_IRQn, DISP_IRQSTEER2_IRQn, DISP_IRQSTEER3_IRQn, DISP_IRQSTEER4_IRQn, DISP_IRQSTEER7_IRQn } /*! * @} */ /* end of group DPU_IRQSTEER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_Peripheral_Access_Layer DRC Peripheral Access Layer * @{ */ /** DRC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x58 */ __IO uint32_t ROI0_POS_CAM; /**< Camera 0 DRC Region of Interest 0 Position Register, array offset: 0x0, array step: 0x58 */ __IO uint32_t ROI0_SIZE_CAM; /**< Camera 0 DRC Region of Interest 0 Size Register, array offset: 0x4, array step: 0x58 */ __IO uint32_t ROI1_POS_CAM; /**< Camera 0 DRC Region of Interest 1 Position Register, array offset: 0x8, array step: 0x58 */ __IO uint32_t ROI1_SIZE_CAM; /**< Camera 0 DRC Region of Interest 1 Size Register, array offset: 0xC, array step: 0x58 */ __IO uint32_t GROI_SUM_SHIFT_CAM; /**< Camera 0 DRC Global ROI 0,1 Sum Shift Register, array offset: 0x10, array step: 0x58 */ __IO uint32_t GBL_GAIN_CAM; /**< Camera 0 DRC Global Gain Register, array offset: 0x14, array step: 0x58 */ uint8_t RESERVED_0[8]; __IO uint32_t LCL_BLK_SIZE_CAM; /**< Camera 0 DRC Local Block Size Register, array offset: 0x20, array step: 0x58 */ __IO uint32_t LCL_STRETCH_CAM; /**< Camera 0 DRC Local Stretch and Offset Register, array offset: 0x24, array step: 0x58 */ __IO uint32_t LCL_BLK_STEPY_CAM; /**< Camera 0 DRC Local Block Y Step Register, array offset: 0x28, array step: 0x58 */ __IO uint32_t LCL_BLK_STEPX_CAM; /**< Camera 0 DRC Local Block X Step Register, array offset: 0x2C, array step: 0x58 */ __IO uint32_t LCL_SUM_SHIFT_CAM; /**< Camera 0 DRC Local Sum Shift Register, array offset: 0x30, array step: 0x58 */ __IO uint32_t ALPHA_CAM; /**< Camera 0 DRC Alpha Blending Register, array offset: 0x34, array step: 0x58 */ uint8_t RESERVED_1[8]; __I uint32_t GROI0_SUM_CAM; /**< Camera 0 DRC Global ROI0 Sum Register, array offset: 0x40, array step: 0x58 */ __I uint32_t GROI1_SUM_CAM; /**< Camera 0 DRC Global ROI1 Sum Register, array offset: 0x44, array step: 0x58 */ uint8_t RESERVED_2[8]; __I uint32_t STAT_BLK_Y_CAM; /**< Camera 0 DRC Current Local Block Y Status, array offset: 0x50, array step: 0x58 */ __I uint32_t CURR_YFRACT_CAM; /**< Camera 0 DRC Current Local Block Y Fraction, array offset: 0x54, array step: 0x58 */ } NEO_PIPE2_DRC_CONF[1]; } DRC_Type; /* ---------------------------------------------------------------------------- -- DRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DRC_Register_Masks DRC Register Masks * @{ */ /*! @name ROI0_POS_CAM - Camera 0 DRC Region of Interest 0 Position Register */ /*! @{ */ #define DRC_ROI0_POS_CAM_XPOS_MASK (0xFFFFU) #define DRC_ROI0_POS_CAM_XPOS_SHIFT (0U) #define DRC_ROI0_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI0_POS_CAM_XPOS_SHIFT)) & DRC_ROI0_POS_CAM_XPOS_MASK) #define DRC_ROI0_POS_CAM_YPOS_MASK (0xFFFF0000U) #define DRC_ROI0_POS_CAM_YPOS_SHIFT (16U) #define DRC_ROI0_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI0_POS_CAM_YPOS_SHIFT)) & DRC_ROI0_POS_CAM_YPOS_MASK) /*! @} */ /* The count of DRC_ROI0_POS_CAM */ #define DRC_ROI0_POS_CAM_COUNT (1U) /*! @name ROI0_SIZE_CAM - Camera 0 DRC Region of Interest 0 Size Register */ /*! @{ */ #define DRC_ROI0_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define DRC_ROI0_SIZE_CAM_WIDTH_SHIFT (0U) #define DRC_ROI0_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI0_SIZE_CAM_WIDTH_SHIFT)) & DRC_ROI0_SIZE_CAM_WIDTH_MASK) #define DRC_ROI0_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define DRC_ROI0_SIZE_CAM_HEIGHT_SHIFT (16U) #define DRC_ROI0_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI0_SIZE_CAM_HEIGHT_SHIFT)) & DRC_ROI0_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of DRC_ROI0_SIZE_CAM */ #define DRC_ROI0_SIZE_CAM_COUNT (1U) /*! @name ROI1_POS_CAM - Camera 0 DRC Region of Interest 1 Position Register */ /*! @{ */ #define DRC_ROI1_POS_CAM_XPOS_MASK (0xFFFFU) #define DRC_ROI1_POS_CAM_XPOS_SHIFT (0U) #define DRC_ROI1_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI1_POS_CAM_XPOS_SHIFT)) & DRC_ROI1_POS_CAM_XPOS_MASK) #define DRC_ROI1_POS_CAM_YPOS_MASK (0xFFFF0000U) #define DRC_ROI1_POS_CAM_YPOS_SHIFT (16U) #define DRC_ROI1_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI1_POS_CAM_YPOS_SHIFT)) & DRC_ROI1_POS_CAM_YPOS_MASK) /*! @} */ /* The count of DRC_ROI1_POS_CAM */ #define DRC_ROI1_POS_CAM_COUNT (1U) /*! @name ROI1_SIZE_CAM - Camera 0 DRC Region of Interest 1 Size Register */ /*! @{ */ #define DRC_ROI1_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define DRC_ROI1_SIZE_CAM_WIDTH_SHIFT (0U) #define DRC_ROI1_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI1_SIZE_CAM_WIDTH_SHIFT)) & DRC_ROI1_SIZE_CAM_WIDTH_MASK) #define DRC_ROI1_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define DRC_ROI1_SIZE_CAM_HEIGHT_SHIFT (16U) #define DRC_ROI1_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << DRC_ROI1_SIZE_CAM_HEIGHT_SHIFT)) & DRC_ROI1_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of DRC_ROI1_SIZE_CAM */ #define DRC_ROI1_SIZE_CAM_COUNT (1U) /*! @name GROI_SUM_SHIFT_CAM - Camera 0 DRC Global ROI 0,1 Sum Shift Register */ /*! @{ */ #define DRC_GROI_SUM_SHIFT_CAM_SHIFT0_MASK (0x1FU) #define DRC_GROI_SUM_SHIFT_CAM_SHIFT0_SHIFT (0U) #define DRC_GROI_SUM_SHIFT_CAM_SHIFT0(x) (((uint32_t)(((uint32_t)(x)) << DRC_GROI_SUM_SHIFT_CAM_SHIFT0_SHIFT)) & DRC_GROI_SUM_SHIFT_CAM_SHIFT0_MASK) #define DRC_GROI_SUM_SHIFT_CAM_SHIFT1_MASK (0x1F0000U) #define DRC_GROI_SUM_SHIFT_CAM_SHIFT1_SHIFT (16U) #define DRC_GROI_SUM_SHIFT_CAM_SHIFT1(x) (((uint32_t)(((uint32_t)(x)) << DRC_GROI_SUM_SHIFT_CAM_SHIFT1_SHIFT)) & DRC_GROI_SUM_SHIFT_CAM_SHIFT1_MASK) /*! @} */ /* The count of DRC_GROI_SUM_SHIFT_CAM */ #define DRC_GROI_SUM_SHIFT_CAM_COUNT (1U) /*! @name GBL_GAIN_CAM - Camera 0 DRC Global Gain Register */ /*! @{ */ #define DRC_GBL_GAIN_CAM_GAIN_MASK (0xFFFFU) #define DRC_GBL_GAIN_CAM_GAIN_SHIFT (0U) #define DRC_GBL_GAIN_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DRC_GBL_GAIN_CAM_GAIN_SHIFT)) & DRC_GBL_GAIN_CAM_GAIN_MASK) /*! @} */ /* The count of DRC_GBL_GAIN_CAM */ #define DRC_GBL_GAIN_CAM_COUNT (1U) /*! @name LCL_BLK_SIZE_CAM - Camera 0 DRC Local Block Size Register */ /*! @{ */ #define DRC_LCL_BLK_SIZE_CAM_XSIZE_MASK (0xFFFFU) #define DRC_LCL_BLK_SIZE_CAM_XSIZE_SHIFT (0U) #define DRC_LCL_BLK_SIZE_CAM_XSIZE(x) (((uint32_t)(((uint32_t)(x)) << DRC_LCL_BLK_SIZE_CAM_XSIZE_SHIFT)) & DRC_LCL_BLK_SIZE_CAM_XSIZE_MASK) #define DRC_LCL_BLK_SIZE_CAM_YSIZE_MASK (0xFFFF0000U) #define DRC_LCL_BLK_SIZE_CAM_YSIZE_SHIFT (16U) #define DRC_LCL_BLK_SIZE_CAM_YSIZE(x) (((uint32_t)(((uint32_t)(x)) << DRC_LCL_BLK_SIZE_CAM_YSIZE_SHIFT)) & DRC_LCL_BLK_SIZE_CAM_YSIZE_MASK) /*! @} */ /* The count of DRC_LCL_BLK_SIZE_CAM */ #define DRC_LCL_BLK_SIZE_CAM_COUNT (1U) /*! @name LCL_STRETCH_CAM - Camera 0 DRC Local Stretch and Offset Register */ /*! @{ */ #define DRC_LCL_STRETCH_CAM_STRETCH_MASK (0xFFFFU) #define DRC_LCL_STRETCH_CAM_STRETCH_SHIFT (0U) #define DRC_LCL_STRETCH_CAM_STRETCH(x) (((uint32_t)(((uint32_t)(x)) << DRC_LCL_STRETCH_CAM_STRETCH_SHIFT)) & DRC_LCL_STRETCH_CAM_STRETCH_MASK) #define DRC_LCL_STRETCH_CAM_OFFSET_MASK (0xFFFF0000U) #define DRC_LCL_STRETCH_CAM_OFFSET_SHIFT (16U) #define DRC_LCL_STRETCH_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DRC_LCL_STRETCH_CAM_OFFSET_SHIFT)) & DRC_LCL_STRETCH_CAM_OFFSET_MASK) /*! @} */ /* The count of DRC_LCL_STRETCH_CAM */ #define DRC_LCL_STRETCH_CAM_COUNT (1U) /*! @name LCL_BLK_STEPY_CAM - Camera 0 DRC Local Block Y Step Register */ /*! @{ */ #define DRC_LCL_BLK_STEPY_CAM_STEP_MASK (0xFFFFU) #define DRC_LCL_BLK_STEPY_CAM_STEP_SHIFT (0U) #define DRC_LCL_BLK_STEPY_CAM_STEP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LCL_BLK_STEPY_CAM_STEP_SHIFT)) & DRC_LCL_BLK_STEPY_CAM_STEP_MASK) /*! @} */ /* The count of DRC_LCL_BLK_STEPY_CAM */ #define DRC_LCL_BLK_STEPY_CAM_COUNT (1U) /*! @name LCL_BLK_STEPX_CAM - Camera 0 DRC Local Block X Step Register */ /*! @{ */ #define DRC_LCL_BLK_STEPX_CAM_STEP_MASK (0xFFFFU) #define DRC_LCL_BLK_STEPX_CAM_STEP_SHIFT (0U) #define DRC_LCL_BLK_STEPX_CAM_STEP(x) (((uint32_t)(((uint32_t)(x)) << DRC_LCL_BLK_STEPX_CAM_STEP_SHIFT)) & DRC_LCL_BLK_STEPX_CAM_STEP_MASK) /*! @} */ /* The count of DRC_LCL_BLK_STEPX_CAM */ #define DRC_LCL_BLK_STEPX_CAM_COUNT (1U) /*! @name LCL_SUM_SHIFT_CAM - Camera 0 DRC Local Sum Shift Register */ /*! @{ */ #define DRC_LCL_SUM_SHIFT_CAM_SHIFT_MASK (0x1FU) #define DRC_LCL_SUM_SHIFT_CAM_SHIFT_SHIFT (0U) #define DRC_LCL_SUM_SHIFT_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << DRC_LCL_SUM_SHIFT_CAM_SHIFT_SHIFT)) & DRC_LCL_SUM_SHIFT_CAM_SHIFT_MASK) /*! @} */ /* The count of DRC_LCL_SUM_SHIFT_CAM */ #define DRC_LCL_SUM_SHIFT_CAM_COUNT (1U) /*! @name ALPHA_CAM - Camera 0 DRC Alpha Blending Register */ /*! @{ */ #define DRC_ALPHA_CAM_ALPHA_MASK (0x1FFU) #define DRC_ALPHA_CAM_ALPHA_SHIFT (0U) #define DRC_ALPHA_CAM_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << DRC_ALPHA_CAM_ALPHA_SHIFT)) & DRC_ALPHA_CAM_ALPHA_MASK) /*! @} */ /* The count of DRC_ALPHA_CAM */ #define DRC_ALPHA_CAM_COUNT (1U) /*! @name GROI0_SUM_CAM - Camera 0 DRC Global ROI0 Sum Register */ /*! @{ */ #define DRC_GROI0_SUM_CAM_VAL_MASK (0xFFFFFFFFU) #define DRC_GROI0_SUM_CAM_VAL_SHIFT (0U) #define DRC_GROI0_SUM_CAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << DRC_GROI0_SUM_CAM_VAL_SHIFT)) & DRC_GROI0_SUM_CAM_VAL_MASK) /*! @} */ /* The count of DRC_GROI0_SUM_CAM */ #define DRC_GROI0_SUM_CAM_COUNT (1U) /*! @name GROI1_SUM_CAM - Camera 0 DRC Global ROI1 Sum Register */ /*! @{ */ #define DRC_GROI1_SUM_CAM_VAL_MASK (0xFFFFFFFFU) #define DRC_GROI1_SUM_CAM_VAL_SHIFT (0U) #define DRC_GROI1_SUM_CAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << DRC_GROI1_SUM_CAM_VAL_SHIFT)) & DRC_GROI1_SUM_CAM_VAL_MASK) /*! @} */ /* The count of DRC_GROI1_SUM_CAM */ #define DRC_GROI1_SUM_CAM_COUNT (1U) /*! @name STAT_BLK_Y_CAM - Camera 0 DRC Current Local Block Y Status */ /*! @{ */ #define DRC_STAT_BLK_Y_CAM_BLKLNE_MASK (0xFFFFU) #define DRC_STAT_BLK_Y_CAM_BLKLNE_SHIFT (0U) #define DRC_STAT_BLK_Y_CAM_BLKLNE(x) (((uint32_t)(((uint32_t)(x)) << DRC_STAT_BLK_Y_CAM_BLKLNE_SHIFT)) & DRC_STAT_BLK_Y_CAM_BLKLNE_MASK) #define DRC_STAT_BLK_Y_CAM_BLKROW_MASK (0xFF0000U) #define DRC_STAT_BLK_Y_CAM_BLKROW_SHIFT (16U) #define DRC_STAT_BLK_Y_CAM_BLKROW(x) (((uint32_t)(((uint32_t)(x)) << DRC_STAT_BLK_Y_CAM_BLKROW_SHIFT)) & DRC_STAT_BLK_Y_CAM_BLKROW_MASK) /*! @} */ /* The count of DRC_STAT_BLK_Y_CAM */ #define DRC_STAT_BLK_Y_CAM_COUNT (1U) /*! @name CURR_YFRACT_CAM - Camera 0 DRC Current Local Block Y Fraction */ /*! @{ */ #define DRC_CURR_YFRACT_CAM_FRACT_MASK (0xFFFFFFFFU) #define DRC_CURR_YFRACT_CAM_FRACT_SHIFT (0U) #define DRC_CURR_YFRACT_CAM_FRACT(x) (((uint32_t)(((uint32_t)(x)) << DRC_CURR_YFRACT_CAM_FRACT_SHIFT)) & DRC_CURR_YFRACT_CAM_FRACT_MASK) /*! @} */ /* The count of DRC_CURR_YFRACT_CAM */ #define DRC_CURR_YFRACT_CAM_COUNT (1U) /*! * @} */ /* end of group DRC_Register_Masks */ /* DRC - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__DRC base address */ #define CAMERA__ISP__DRC_BASE (0x4AE01300u) /** Peripheral CAMERA__ISP__DRC base pointer */ #define CAMERA__ISP__DRC ((DRC_Type *)CAMERA__ISP__DRC_BASE) /** Array initializer of DRC peripheral base addresses */ #define DRC_BASE_ADDRS { CAMERA__ISP__DRC_BASE } /** Array initializer of DRC peripheral base pointers */ #define DRC_BASE_PTRS { CAMERA__ISP__DRC } /*! * @} */ /* end of group DRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- EE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup EE_Peripheral_Access_Layer EE Peripheral Access Layer * @{ */ /** EE - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x14 */ __IO uint32_t CTRL_CAM; /**< Camera 0 EE Control Register, array offset: 0x0, array step: 0x14 */ __IO uint32_t CORING_CAM; /**< Camera 0 EE Coring Register, array offset: 0x4, array step: 0x14 */ __IO uint32_t CLIP_CAM; /**< Camera 0 EE Clip Register, array offset: 0x8, array step: 0x14 */ __IO uint32_t MASKGAIN_CAM; /**< Camera 0 EE Mask Gain Register, array offset: 0xC, array step: 0x14 */ __I uint32_t EDGECNT_CAM; /**< Camera 0 EE Edge Count Register, array offset: 0x10, array step: 0x14 */ } NEO_PIPE2_EE_CONF[1]; } EE_Type; /* ---------------------------------------------------------------------------- -- EE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EE_Register_Masks EE Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 EE Control Register */ /*! @{ */ #define EE_CTRL_CAM_DEBUG_MASK (0x300U) #define EE_CTRL_CAM_DEBUG_SHIFT (8U) /*! DEBUG - Debug / Tuning view * 0b00..off * 0b01..edge pixels+texture * 0b10..edge pixels+black */ #define EE_CTRL_CAM_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << EE_CTRL_CAM_DEBUG_SHIFT)) & EE_CTRL_CAM_DEBUG_MASK) #define EE_CTRL_CAM_ENABLE_MASK (0x80000000U) #define EE_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..off * 0b1..on */ #define EE_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << EE_CTRL_CAM_ENABLE_SHIFT)) & EE_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of EE_CTRL_CAM */ #define EE_CTRL_CAM_COUNT (1U) /*! @name CORING_CAM - Camera 0 EE Coring Register */ /*! @{ */ #define EE_CORING_CAM_CORING_MASK (0xFFFFFU) #define EE_CORING_CAM_CORING_SHIFT (0U) #define EE_CORING_CAM_CORING(x) (((uint32_t)(((uint32_t)(x)) << EE_CORING_CAM_CORING_SHIFT)) & EE_CORING_CAM_CORING_MASK) /*! @} */ /* The count of EE_CORING_CAM */ #define EE_CORING_CAM_COUNT (1U) /*! @name CLIP_CAM - Camera 0 EE Clip Register */ /*! @{ */ #define EE_CLIP_CAM_CLIP_MASK (0xFFFFFU) #define EE_CLIP_CAM_CLIP_SHIFT (0U) #define EE_CLIP_CAM_CLIP(x) (((uint32_t)(((uint32_t)(x)) << EE_CLIP_CAM_CLIP_SHIFT)) & EE_CLIP_CAM_CLIP_MASK) /*! @} */ /* The count of EE_CLIP_CAM */ #define EE_CLIP_CAM_COUNT (1U) /*! @name MASKGAIN_CAM - Camera 0 EE Mask Gain Register */ /*! @{ */ #define EE_MASKGAIN_CAM_GAIN_MASK (0xFFU) #define EE_MASKGAIN_CAM_GAIN_SHIFT (0U) #define EE_MASKGAIN_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << EE_MASKGAIN_CAM_GAIN_SHIFT)) & EE_MASKGAIN_CAM_GAIN_MASK) /*! @} */ /* The count of EE_MASKGAIN_CAM */ #define EE_MASKGAIN_CAM_COUNT (1U) /*! @name EDGECNT_CAM - Camera 0 EE Edge Count Register */ /*! @{ */ #define EE_EDGECNT_CAM_EDGE_PIXELS_MASK (0xFFFFFFU) #define EE_EDGECNT_CAM_EDGE_PIXELS_SHIFT (0U) #define EE_EDGECNT_CAM_EDGE_PIXELS(x) (((uint32_t)(((uint32_t)(x)) << EE_EDGECNT_CAM_EDGE_PIXELS_SHIFT)) & EE_EDGECNT_CAM_EDGE_PIXELS_MASK) /*! @} */ /* The count of EE_EDGECNT_CAM */ #define EE_EDGECNT_CAM_COUNT (1U) /*! * @} */ /* end of group EE_Register_Masks */ /* EE - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__EE base address */ #define CAMERA__ISP__EE_BASE (0x4AE01480u) /** Peripheral CAMERA__ISP__EE base pointer */ #define CAMERA__ISP__EE ((EE_Type *)CAMERA__ISP__EE_BASE) /** Array initializer of EE peripheral base addresses */ #define EE_BASE_ADDRS { CAMERA__ISP__EE_BASE } /** Array initializer of EE peripheral base pointers */ #define EE_BASE_PTRS { CAMERA__ISP__EE } /*! * @} */ /* end of group EE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENETC_GLOBAL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_GLOBAL_Peripheral_Access_Layer ENETC_GLOBAL Peripheral Access Layer * @{ */ /** ENETC_GLOBAL - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __I uint32_t SMDTR; /**< Shared memory depletion threshold register, offset: 0x4 */ __I uint32_t SMACR; /**< Shared memory available count register, offset: 0x8 */ uint8_t RESERVED_1[4]; __I uint32_t SMCLWMR; /**< Shared memory count low watermark register, offset: 0x10 */ __I uint32_t SMBUCR; /**< Shared memory buffer unassigned count register, offset: 0x14 */ __I uint32_t SMBUCHWMR; /**< Shared memory buffer unassigned count high watermark register, offset: 0x18 */ __I uint32_t SMLCR; /**< Shared memory loss count register, offset: 0x1C */ __I uint32_t HBTCAPR; /**< Hash bucket table capability register, offset: 0x20 */ __I uint32_t HBTOR0; /**< Hash bucket table operational register 0, offset: 0x24 */ uint8_t RESERVED_2[4]; __I uint32_t HBTOR2; /**< Hash bucket table operational register 2, offset: 0x2C */ uint8_t RESERVED_3[16]; __I uint32_t SMERBCAPR; /**< Shared memory ENETC receive buffer capability register, offset: 0x40 */ __I uint32_t SMERBOR0; /**< Shared memory ENETC receive buffer operational register 0, offset: 0x44 */ __I uint32_t SMERBOR1; /**< Shared memory ENETC receive buffer operational 1, offset: 0x48 */ uint8_t RESERVED_4[180]; struct { /* offset: 0x100, array step: 0x8 */ __I uint32_t PCEOR; /**< PCE 0 operational register, array offset: 0x100, array step: 0x8 */ __I uint32_t RFEOR; /**< Replication Forwarding Engine 0 operational register, array offset: 0x104, array step: 0x8 */ } PCE_SL[1]; uint8_t RESERVED_5[92]; __I uint32_t NETCCLKR; /**< NETC clock register, offset: 0x164 */ uint8_t RESERVED_6[152]; struct { /* offset: 0x200, array step: 0x28 */ __I uint32_t HTACAPR; /**< HTA 0 capability register, array offset: 0x200, array step: 0x28 */ __I uint32_t HTARFCOR; /**< HTA 0 receive frame count operational register, array offset: 0x204, array step: 0x28 */ __I uint32_t HTAHPBCOR; /**< HTA 0 high priority byte count operational register, array offset: 0x208, array step: 0x28 */ __I uint32_t HTALPBCOR; /**< HTA 0 low priority byte count operational register, array offset: 0x20C, array step: 0x28 */ uint8_t RESERVED_0[20]; __I uint32_t HTATFCOR; /**< HTA 0 transmit frame count operational register, array offset: 0x224, array step: 0x28 */ } HTA_LOOP[1]; uint8_t RESERVED_7[216]; struct { /* offset: 0x300, array step: 0x10 */ __IO uint32_t RCSBRLAR; /**< Root complex 0 system bus read latency average register, array offset: 0x300, array step: 0x10 */ __I uint32_t RCSBRLHWMR; /**< Root complex 0 system bus read latency high watermark register, array offset: 0x304, array step: 0x10 */ __IO uint32_t RCSBWLAR; /**< Root complex 0 system bus write latency average register, array offset: 0x308, array step: 0x10 */ __I uint32_t RCSBWLHWMR; /**< Root complex 0 system bus write latency high watermark register, array offset: 0x30C, array step: 0x10 */ } ARRAY_NUM_RC[1]; uint8_t RESERVED_8[2280]; __I uint32_t IPBRR0; /**< IP block revision register 0, offset: 0xBF8 */ __I uint32_t IPBRR1; /**< IP block revision register 1, offset: 0xBFC */ uint8_t RESERVED_9[256]; __I uint32_t FBLPR[2]; /**< Function boot loader parameter register 0..Function boot loader parameter register 1, array offset: 0xD00, array step: 0x4 */ uint8_t RESERVED_10[280]; union { /* offset: 0xE20 */ struct { /* offset: 0xE20 */ __IO uint32_t EMDIOUFSBECR; /**< EMDIO uncorrectable fatal system bus error configuration register, offset: 0xE20, not available in all instances (available on 6 out of 30) */ __IO uint32_t EMDIOUFSBESR; /**< EMDIO uncorrectable fatal system bus error status register, offset: 0xE24, not available in all instances (available on 6 out of 30) */ } EMDIO; struct { /* offset: 0xE20 */ __IO uint32_t TUFSBECR; /**< Timer uncorrectable fatal system bus error configuration register, offset: 0xE20, not available in all instances (available on 6 out of 30) */ __IO uint32_t TUFSBESR; /**< Timer uncorrectable fatal system bus error status register, offset: 0xE24, not available in all instances (available on 6 out of 30) */ } TIMER; }; } ENETC_GLOBAL_Type; /* ---------------------------------------------------------------------------- -- ENETC_GLOBAL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_GLOBAL_Register_Masks ENETC_GLOBAL Register Masks * @{ */ /*! @name SMDTR - Shared memory depletion threshold register */ /*! @{ */ #define ENETC_GLOBAL_SMDTR_THRESH_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMDTR_THRESH_SHIFT (0U) /*! THRESH - Shared memory depletion threshold in Words */ #define ENETC_GLOBAL_SMDTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMDTR_THRESH_SHIFT)) & ENETC_GLOBAL_SMDTR_THRESH_MASK) /*! @} */ /*! @name SMACR - Shared memory available count register */ /*! @{ */ #define ENETC_GLOBAL_SMACR_COUNT_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMACR_COUNT_SHIFT (0U) #define ENETC_GLOBAL_SMACR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMACR_COUNT_SHIFT)) & ENETC_GLOBAL_SMACR_COUNT_MASK) /*! @} */ /*! @name SMCLWMR - Shared memory count low watermark register */ /*! @{ */ #define ENETC_GLOBAL_SMCLWMR_WATERMARK_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMCLWMR_WATERMARK_SHIFT (0U) /*! WATERMARK - Watermark for shared memory in words */ #define ENETC_GLOBAL_SMCLWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMCLWMR_WATERMARK_SHIFT)) & ENETC_GLOBAL_SMCLWMR_WATERMARK_MASK) /*! @} */ /*! @name SMBUCR - Shared memory buffer unassigned count register */ /*! @{ */ #define ENETC_GLOBAL_SMBUCR_COUNT_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMBUCR_COUNT_SHIFT (0U) /*! COUNT - Shows the current amount of unassigned shared memory buffer in words */ #define ENETC_GLOBAL_SMBUCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMBUCR_COUNT_SHIFT)) & ENETC_GLOBAL_SMBUCR_COUNT_MASK) /*! @} */ /*! @name SMBUCHWMR - Shared memory buffer unassigned count high watermark register */ /*! @{ */ #define ENETC_GLOBAL_SMBUCHWMR_WATERMARK_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT (0U) /*! WATERMARK - Shows the high watermark for unassigned memory */ #define ENETC_GLOBAL_SMBUCHWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT)) & ENETC_GLOBAL_SMBUCHWMR_WATERMARK_MASK) /*! @} */ /*! @name SMLCR - Shared memory loss count register */ /*! @{ */ #define ENETC_GLOBAL_SMLCR_COUNT_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMLCR_COUNT_SHIFT (0U) /*! COUNT - Determinate number of lost words */ #define ENETC_GLOBAL_SMLCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMLCR_COUNT_SHIFT)) & ENETC_GLOBAL_SMLCR_COUNT_MASK) #define ENETC_GLOBAL_SMLCR_IFLC_MASK (0x40000000U) #define ENETC_GLOBAL_SMLCR_IFLC_SHIFT (30U) /*! IFLC - Indeterminate free list corruption */ #define ENETC_GLOBAL_SMLCR_IFLC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMLCR_IFLC_SHIFT)) & ENETC_GLOBAL_SMLCR_IFLC_MASK) #define ENETC_GLOBAL_SMLCR_IFDC_MASK (0x80000000U) #define ENETC_GLOBAL_SMLCR_IFDC_SHIFT (31U) /*! IFDC - Indeterminate frame descriptor corruption */ #define ENETC_GLOBAL_SMLCR_IFDC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMLCR_IFDC_SHIFT)) & ENETC_GLOBAL_SMLCR_IFDC_MASK) /*! @} */ /*! @name HBTCAPR - Hash bucket table capability register */ /*! @{ */ #define ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK (0xFFFFU) #define ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT (0U) /*! NUM_ENTRIES - Number of allocated bucket entries */ #define ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT)) & ENETC_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK) #define ENETC_GLOBAL_HBTCAPR_MAX_COL_MASK (0x7000000U) #define ENETC_GLOBAL_HBTCAPR_MAX_COL_SHIFT (24U) /*! MAX_COL - Maximum hash table collision chain length */ #define ENETC_GLOBAL_HBTCAPR_MAX_COL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTCAPR_MAX_COL_SHIFT)) & ENETC_GLOBAL_HBTCAPR_MAX_COL_MASK) #define ENETC_GLOBAL_HBTCAPR_MAX_VISITS_MASK (0xF0000000U) #define ENETC_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT (28U) /*! MAX_VISITS - Maximum number of table entry visits */ #define ENETC_GLOBAL_HBTCAPR_MAX_VISITS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT)) & ENETC_GLOBAL_HBTCAPR_MAX_VISITS_MASK) /*! @} */ /*! @name HBTOR0 - Hash bucket table operational register 0 */ /*! @{ */ #define ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_MASK (0xFFFFU) #define ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT (0U) #define ENETC_GLOBAL_HBTOR0_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT)) & ENETC_GLOBAL_HBTOR0_NUM_ENTRIES_MASK) #define ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_MASK (0xFFFF0000U) #define ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT (16U) #define ENETC_GLOBAL_HBTOR0_HWM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT)) & ENETC_GLOBAL_HBTOR0_HWM_ENTRIES_MASK) /*! @} */ /*! @name HBTOR2 - Hash bucket table operational register 2 */ /*! @{ */ #define ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK (0xFFU) #define ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT (0U) /*! RUN_AVG_FRACT - Fractional portion of the running average length of hash lookup */ #define ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT)) & ENETC_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK) #define ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_MASK (0xFF00U) #define ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT (8U) /*! RUN_AVG_INT - Integer portion of the running average length of hash lookup */ #define ENETC_GLOBAL_HBTOR2_RUN_AVG_INT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT)) & ENETC_GLOBAL_HBTOR2_RUN_AVG_INT_MASK) #define ENETC_GLOBAL_HBTOR2_HWM_COL_MASK (0xF0000U) #define ENETC_GLOBAL_HBTOR2_HWM_COL_SHIFT (16U) #define ENETC_GLOBAL_HBTOR2_HWM_COL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HBTOR2_HWM_COL_SHIFT)) & ENETC_GLOBAL_HBTOR2_HWM_COL_MASK) /*! @} */ /*! @name SMERBCAPR - Shared memory ENETC receive buffer capability register */ /*! @{ */ #define ENETC_GLOBAL_SMERBCAPR_THRESH_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMERBCAPR_THRESH_SHIFT (0U) /*! THRESH - Receive buffer memory threshold */ #define ENETC_GLOBAL_SMERBCAPR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBCAPR_THRESH_SHIFT)) & ENETC_GLOBAL_SMERBCAPR_THRESH_MASK) #define ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_MASK (0x30000000U) #define ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT (28U) /*! WORD_SIZE - Word Size */ #define ENETC_GLOBAL_SMERBCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT)) & ENETC_GLOBAL_SMERBCAPR_WORD_SIZE_MASK) #define ENETC_GLOBAL_SMERBCAPR_MLOC_MASK (0xC0000000U) #define ENETC_GLOBAL_SMERBCAPR_MLOC_SHIFT (30U) /*! MLOC - Memory Location */ #define ENETC_GLOBAL_SMERBCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBCAPR_MLOC_SHIFT)) & ENETC_GLOBAL_SMERBCAPR_MLOC_MASK) /*! @} */ /*! @name SMERBOR0 - Shared memory ENETC receive buffer operational register 0 */ /*! @{ */ #define ENETC_GLOBAL_SMERBOR0_AMOUNT_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMERBOR0_AMOUNT_SHIFT (0U) #define ENETC_GLOBAL_SMERBOR0_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBOR0_AMOUNT_SHIFT)) & ENETC_GLOBAL_SMERBOR0_AMOUNT_MASK) /*! @} */ /*! @name SMERBOR1 - Shared memory ENETC receive buffer operational 1 */ /*! @{ */ #define ENETC_GLOBAL_SMERBOR1_WATERMARK_MASK (0xFFFFFFU) #define ENETC_GLOBAL_SMERBOR1_WATERMARK_SHIFT (0U) /*! WATERMARK - High Watermark */ #define ENETC_GLOBAL_SMERBOR1_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_SMERBOR1_WATERMARK_SHIFT)) & ENETC_GLOBAL_SMERBOR1_WATERMARK_MASK) /*! @} */ /*! @name PCEOR - PCE 0 operational register */ /*! @{ */ #define ENETC_GLOBAL_PCEOR_NUM_FRAMES_MASK (0x3FU) #define ENETC_GLOBAL_PCEOR_NUM_FRAMES_SHIFT (0U) #define ENETC_GLOBAL_PCEOR_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_PCEOR_NUM_FRAMES_SHIFT)) & ENETC_GLOBAL_PCEOR_NUM_FRAMES_MASK) #define ENETC_GLOBAL_PCEOR_HWM_FRAMES_MASK (0x3F00U) #define ENETC_GLOBAL_PCEOR_HWM_FRAMES_SHIFT (8U) #define ENETC_GLOBAL_PCEOR_HWM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_PCEOR_HWM_FRAMES_SHIFT)) & ENETC_GLOBAL_PCEOR_HWM_FRAMES_MASK) #define ENETC_GLOBAL_PCEOR_MAX_FRAMES_MASK (0x3F0000U) #define ENETC_GLOBAL_PCEOR_MAX_FRAMES_SHIFT (16U) /*! MAX_FRAMES - Maximum number of concurrent frames that can be processed by the PCE block */ #define ENETC_GLOBAL_PCEOR_MAX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_PCEOR_MAX_FRAMES_SHIFT)) & ENETC_GLOBAL_PCEOR_MAX_FRAMES_MASK) /*! @} */ /* The count of ENETC_GLOBAL_PCEOR */ #define ENETC_GLOBAL_PCEOR_COUNT (1U) /*! @name RFEOR - Replication Forwarding Engine 0 operational register */ /*! @{ */ #define ENETC_GLOBAL_RFEOR_NUM_FRAMES_MASK (0x3FU) #define ENETC_GLOBAL_RFEOR_NUM_FRAMES_SHIFT (0U) #define ENETC_GLOBAL_RFEOR_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RFEOR_NUM_FRAMES_SHIFT)) & ENETC_GLOBAL_RFEOR_NUM_FRAMES_MASK) #define ENETC_GLOBAL_RFEOR_HWM_FRAMES_MASK (0x3F00U) #define ENETC_GLOBAL_RFEOR_HWM_FRAMES_SHIFT (8U) #define ENETC_GLOBAL_RFEOR_HWM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RFEOR_HWM_FRAMES_SHIFT)) & ENETC_GLOBAL_RFEOR_HWM_FRAMES_MASK) #define ENETC_GLOBAL_RFEOR_MAX_FRAMES_MASK (0x3F0000U) #define ENETC_GLOBAL_RFEOR_MAX_FRAMES_SHIFT (16U) /*! MAX_FRAMES - Maximum number of concurrent frames that can be processed by the RFE block. */ #define ENETC_GLOBAL_RFEOR_MAX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RFEOR_MAX_FRAMES_SHIFT)) & ENETC_GLOBAL_RFEOR_MAX_FRAMES_MASK) /*! @} */ /* The count of ENETC_GLOBAL_RFEOR */ #define ENETC_GLOBAL_RFEOR_COUNT (1U) /*! @name NETCCLKR - NETC clock register */ /*! @{ */ #define ENETC_GLOBAL_NETCCLKR_FREQ_MASK (0x7FFU) #define ENETC_GLOBAL_NETCCLKR_FREQ_SHIFT (0U) /*! FREQ - Frequency */ #define ENETC_GLOBAL_NETCCLKR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_NETCCLKR_FREQ_SHIFT)) & ENETC_GLOBAL_NETCCLKR_FREQ_MASK) /*! @} */ /*! @name HTACAPR - HTA 0 capability register */ /*! @{ */ #define ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK (0xFFU) #define ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT (0U) #define ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT)) & ENETC_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK) #define ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK (0xFF00U) #define ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT (8U) #define ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT)) & ENETC_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK) /*! @} */ /* The count of ENETC_GLOBAL_HTACAPR */ #define ENETC_GLOBAL_HTACAPR_COUNT (1U) /*! @name HTARFCOR - HTA 0 receive frame count operational register */ /*! @{ */ #define ENETC_GLOBAL_HTARFCOR_HP_COUNT_MASK (0xFFU) #define ENETC_GLOBAL_HTARFCOR_HP_COUNT_SHIFT (0U) #define ENETC_GLOBAL_HTARFCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_HP_COUNT_SHIFT)) & ENETC_GLOBAL_HTARFCOR_HP_COUNT_MASK) #define ENETC_GLOBAL_HTARFCOR_HP_HWM_MASK (0xFF00U) #define ENETC_GLOBAL_HTARFCOR_HP_HWM_SHIFT (8U) #define ENETC_GLOBAL_HTARFCOR_HP_HWM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_HP_HWM_SHIFT)) & ENETC_GLOBAL_HTARFCOR_HP_HWM_MASK) #define ENETC_GLOBAL_HTARFCOR_LP_COUNT_MASK (0xFF0000U) #define ENETC_GLOBAL_HTARFCOR_LP_COUNT_SHIFT (16U) #define ENETC_GLOBAL_HTARFCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_LP_COUNT_SHIFT)) & ENETC_GLOBAL_HTARFCOR_LP_COUNT_MASK) #define ENETC_GLOBAL_HTARFCOR_LP_HWM_MASK (0xFF000000U) #define ENETC_GLOBAL_HTARFCOR_LP_HWM_SHIFT (24U) #define ENETC_GLOBAL_HTARFCOR_LP_HWM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTARFCOR_LP_HWM_SHIFT)) & ENETC_GLOBAL_HTARFCOR_LP_HWM_MASK) /*! @} */ /* The count of ENETC_GLOBAL_HTARFCOR */ #define ENETC_GLOBAL_HTARFCOR_COUNT (1U) /*! @name HTAHPBCOR - HTA 0 high priority byte count operational register */ /*! @{ */ #define ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_MASK (0xFFFFU) #define ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT (0U) #define ENETC_GLOBAL_HTAHPBCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT)) & ENETC_GLOBAL_HTAHPBCOR_HP_COUNT_MASK) #define ENETC_GLOBAL_HTAHPBCOR_HWM_MASK (0xFFFF0000U) #define ENETC_GLOBAL_HTAHPBCOR_HWM_SHIFT (16U) #define ENETC_GLOBAL_HTAHPBCOR_HWM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTAHPBCOR_HWM_SHIFT)) & ENETC_GLOBAL_HTAHPBCOR_HWM_MASK) /*! @} */ /* The count of ENETC_GLOBAL_HTAHPBCOR */ #define ENETC_GLOBAL_HTAHPBCOR_COUNT (1U) /*! @name HTALPBCOR - HTA 0 low priority byte count operational register */ /*! @{ */ #define ENETC_GLOBAL_HTALPBCOR_LP_COUNT_MASK (0xFFFFU) #define ENETC_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT (0U) #define ENETC_GLOBAL_HTALPBCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT)) & ENETC_GLOBAL_HTALPBCOR_LP_COUNT_MASK) #define ENETC_GLOBAL_HTALPBCOR_HWM_MASK (0xFFFF0000U) #define ENETC_GLOBAL_HTALPBCOR_HWM_SHIFT (16U) #define ENETC_GLOBAL_HTALPBCOR_HWM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTALPBCOR_HWM_SHIFT)) & ENETC_GLOBAL_HTALPBCOR_HWM_MASK) /*! @} */ /* The count of ENETC_GLOBAL_HTALPBCOR */ #define ENETC_GLOBAL_HTALPBCOR_COUNT (1U) /*! @name HTATFCOR - HTA 0 transmit frame count operational register */ /*! @{ */ #define ENETC_GLOBAL_HTATFCOR_HP_COUNT_MASK (0xFFU) #define ENETC_GLOBAL_HTATFCOR_HP_COUNT_SHIFT (0U) #define ENETC_GLOBAL_HTATFCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_HP_COUNT_SHIFT)) & ENETC_GLOBAL_HTATFCOR_HP_COUNT_MASK) #define ENETC_GLOBAL_HTATFCOR_HP_HWM_MASK (0xFF00U) #define ENETC_GLOBAL_HTATFCOR_HP_HWM_SHIFT (8U) #define ENETC_GLOBAL_HTATFCOR_HP_HWM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_HP_HWM_SHIFT)) & ENETC_GLOBAL_HTATFCOR_HP_HWM_MASK) #define ENETC_GLOBAL_HTATFCOR_LP_COUNT_MASK (0xFF0000U) #define ENETC_GLOBAL_HTATFCOR_LP_COUNT_SHIFT (16U) #define ENETC_GLOBAL_HTATFCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_LP_COUNT_SHIFT)) & ENETC_GLOBAL_HTATFCOR_LP_COUNT_MASK) #define ENETC_GLOBAL_HTATFCOR_LP_HWM_MASK (0xFF000000U) #define ENETC_GLOBAL_HTATFCOR_LP_HWM_SHIFT (24U) #define ENETC_GLOBAL_HTATFCOR_LP_HWM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_HTATFCOR_LP_HWM_SHIFT)) & ENETC_GLOBAL_HTATFCOR_LP_HWM_MASK) /*! @} */ /* The count of ENETC_GLOBAL_HTATFCOR */ #define ENETC_GLOBAL_HTATFCOR_COUNT (1U) /*! @name RCSBRLAR - Root complex 0 system bus read latency average register */ /*! @{ */ #define ENETC_GLOBAL_RCSBRLAR_FRACT_MASK (0xFFU) #define ENETC_GLOBAL_RCSBRLAR_FRACT_SHIFT (0U) #define ENETC_GLOBAL_RCSBRLAR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLAR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBRLAR_FRACT_MASK) #define ENETC_GLOBAL_RCSBRLAR_INT_MASK (0xFFF00U) #define ENETC_GLOBAL_RCSBRLAR_INT_SHIFT (8U) #define ENETC_GLOBAL_RCSBRLAR_INT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLAR_INT_SHIFT)) & ENETC_GLOBAL_RCSBRLAR_INT_MASK) /*! @} */ /* The count of ENETC_GLOBAL_RCSBRLAR */ #define ENETC_GLOBAL_RCSBRLAR_COUNT (1U) /*! @name RCSBRLHWMR - Root complex 0 system bus read latency high watermark register */ /*! @{ */ #define ENETC_GLOBAL_RCSBRLHWMR_FRACT_MASK (0xFFU) #define ENETC_GLOBAL_RCSBRLHWMR_FRACT_SHIFT (0U) #define ENETC_GLOBAL_RCSBRLHWMR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLHWMR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBRLHWMR_FRACT_MASK) #define ENETC_GLOBAL_RCSBRLHWMR_INT_MASK (0xFFF00U) #define ENETC_GLOBAL_RCSBRLHWMR_INT_SHIFT (8U) #define ENETC_GLOBAL_RCSBRLHWMR_INT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBRLHWMR_INT_SHIFT)) & ENETC_GLOBAL_RCSBRLHWMR_INT_MASK) /*! @} */ /* The count of ENETC_GLOBAL_RCSBRLHWMR */ #define ENETC_GLOBAL_RCSBRLHWMR_COUNT (1U) /*! @name RCSBWLAR - Root complex 0 system bus write latency average register */ /*! @{ */ #define ENETC_GLOBAL_RCSBWLAR_FRACT_MASK (0xFFU) #define ENETC_GLOBAL_RCSBWLAR_FRACT_SHIFT (0U) #define ENETC_GLOBAL_RCSBWLAR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLAR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBWLAR_FRACT_MASK) #define ENETC_GLOBAL_RCSBWLAR_INT_MASK (0xFFF00U) #define ENETC_GLOBAL_RCSBWLAR_INT_SHIFT (8U) #define ENETC_GLOBAL_RCSBWLAR_INT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLAR_INT_SHIFT)) & ENETC_GLOBAL_RCSBWLAR_INT_MASK) /*! @} */ /* The count of ENETC_GLOBAL_RCSBWLAR */ #define ENETC_GLOBAL_RCSBWLAR_COUNT (1U) /*! @name RCSBWLHWMR - Root complex 0 system bus write latency high watermark register */ /*! @{ */ #define ENETC_GLOBAL_RCSBWLHWMR_FRACT_MASK (0xFFU) #define ENETC_GLOBAL_RCSBWLHWMR_FRACT_SHIFT (0U) #define ENETC_GLOBAL_RCSBWLHWMR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLHWMR_FRACT_SHIFT)) & ENETC_GLOBAL_RCSBWLHWMR_FRACT_MASK) #define ENETC_GLOBAL_RCSBWLHWMR_INT_MASK (0xFFF00U) #define ENETC_GLOBAL_RCSBWLHWMR_INT_SHIFT (8U) #define ENETC_GLOBAL_RCSBWLHWMR_INT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_RCSBWLHWMR_INT_SHIFT)) & ENETC_GLOBAL_RCSBWLHWMR_INT_MASK) /*! @} */ /* The count of ENETC_GLOBAL_RCSBWLHWMR */ #define ENETC_GLOBAL_RCSBWLHWMR_COUNT (1U) /*! @name IPBRR0 - IP block revision register 0 */ /*! @{ */ #define ENETC_GLOBAL_IPBRR0_IP_MN_MASK (0xFFU) #define ENETC_GLOBAL_IPBRR0_IP_MN_SHIFT (0U) #define ENETC_GLOBAL_IPBRR0_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR0_IP_MN_SHIFT)) & ENETC_GLOBAL_IPBRR0_IP_MN_MASK) #define ENETC_GLOBAL_IPBRR0_IP_MJ_MASK (0xFF00U) #define ENETC_GLOBAL_IPBRR0_IP_MJ_SHIFT (8U) #define ENETC_GLOBAL_IPBRR0_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR0_IP_MJ_SHIFT)) & ENETC_GLOBAL_IPBRR0_IP_MJ_MASK) /*! @} */ /*! @name IPBRR1 - IP block revision register 1 */ /*! @{ */ #define ENETC_GLOBAL_IPBRR1_IP_CFG_MASK (0xFFU) #define ENETC_GLOBAL_IPBRR1_IP_CFG_SHIFT (0U) #define ENETC_GLOBAL_IPBRR1_IP_CFG(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR1_IP_CFG_SHIFT)) & ENETC_GLOBAL_IPBRR1_IP_CFG_MASK) #define ENETC_GLOBAL_IPBRR1_IP_MNT_MASK (0xFF00U) #define ENETC_GLOBAL_IPBRR1_IP_MNT_SHIFT (8U) #define ENETC_GLOBAL_IPBRR1_IP_MNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR1_IP_MNT_SHIFT)) & ENETC_GLOBAL_IPBRR1_IP_MNT_MASK) #define ENETC_GLOBAL_IPBRR1_IP_INT_MASK (0xFF0000U) #define ENETC_GLOBAL_IPBRR1_IP_INT_SHIFT (16U) #define ENETC_GLOBAL_IPBRR1_IP_INT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_IPBRR1_IP_INT_SHIFT)) & ENETC_GLOBAL_IPBRR1_IP_INT_MASK) /*! @} */ /*! @name FBLPR - Function boot loader parameter register 0..Function boot loader parameter register 1 */ /*! @{ */ #define ENETC_GLOBAL_FBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) #define ENETC_GLOBAL_FBLPR_PARAM_VAL_SHIFT (0U) #define ENETC_GLOBAL_FBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_FBLPR_PARAM_VAL_SHIFT)) & ENETC_GLOBAL_FBLPR_PARAM_VAL_MASK) /*! @} */ /* The count of ENETC_GLOBAL_FBLPR */ #define ENETC_GLOBAL_FBLPR_COUNT (2U) /*! @name EMDIOUFSBECR - EMDIO uncorrectable fatal system bus error configuration register */ /*! @{ */ #define ENETC_GLOBAL_EMDIOUFSBECR_RD_MASK (0x80000000U) #define ENETC_GLOBAL_EMDIOUFSBECR_RD_SHIFT (31U) /*! RD - Report disable */ #define ENETC_GLOBAL_EMDIOUFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBECR_RD_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBECR_RD_MASK) /*! @} */ /*! @name EMDIOUFSBESR - EMDIO uncorrectable fatal system bus error status register */ /*! @{ */ #define ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_MASK (0xFU) #define ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_SHIFT (0U) /*! SB_ID - System Bus ID */ #define ENETC_GLOBAL_EMDIOUFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBESR_SB_ID_MASK) #define ENETC_GLOBAL_EMDIOUFSBESR_M_MASK (0x40000000U) #define ENETC_GLOBAL_EMDIOUFSBESR_M_SHIFT (30U) /*! M - Multiple */ #define ENETC_GLOBAL_EMDIOUFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBESR_M_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBESR_M_MASK) #define ENETC_GLOBAL_EMDIOUFSBESR_SBE_MASK (0x80000000U) #define ENETC_GLOBAL_EMDIOUFSBESR_SBE_SHIFT (31U) /*! SBE - System bus error */ #define ENETC_GLOBAL_EMDIOUFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_EMDIOUFSBESR_SBE_SHIFT)) & ENETC_GLOBAL_EMDIOUFSBESR_SBE_MASK) /*! @} */ /*! @name TUFSBECR - Timer uncorrectable fatal system bus error configuration register */ /*! @{ */ #define ENETC_GLOBAL_TUFSBECR_RD_MASK (0x80000000U) #define ENETC_GLOBAL_TUFSBECR_RD_SHIFT (31U) /*! RD - Report disable */ #define ENETC_GLOBAL_TUFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBECR_RD_SHIFT)) & ENETC_GLOBAL_TUFSBECR_RD_MASK) /*! @} */ /*! @name TUFSBESR - Timer uncorrectable fatal system bus error status register */ /*! @{ */ #define ENETC_GLOBAL_TUFSBESR_SB_ID_MASK (0xFU) #define ENETC_GLOBAL_TUFSBESR_SB_ID_SHIFT (0U) /*! SB_ID - System Bus ID */ #define ENETC_GLOBAL_TUFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBESR_SB_ID_SHIFT)) & ENETC_GLOBAL_TUFSBESR_SB_ID_MASK) #define ENETC_GLOBAL_TUFSBESR_M_MASK (0x40000000U) #define ENETC_GLOBAL_TUFSBESR_M_SHIFT (30U) /*! M - Multiple */ #define ENETC_GLOBAL_TUFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBESR_M_SHIFT)) & ENETC_GLOBAL_TUFSBESR_M_MASK) #define ENETC_GLOBAL_TUFSBESR_SBE_MASK (0x80000000U) #define ENETC_GLOBAL_TUFSBESR_SBE_SHIFT (31U) /*! SBE - System bus error */ #define ENETC_GLOBAL_TUFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_GLOBAL_TUFSBESR_SBE_SHIFT)) & ENETC_GLOBAL_TUFSBESR_SBE_MASK) /*! @} */ /*! * @} */ /* end of group ENETC_GLOBAL_Register_Masks */ /* ENETC_GLOBAL - Peripheral instance base addresses */ /** Peripheral EMDIO_GLOBAL base address */ #define EMDIO_GLOBAL_BASE (0x4CCF0000u) /** Peripheral EMDIO_GLOBAL base pointer */ #define EMDIO_GLOBAL ((ENETC_GLOBAL_Type *)EMDIO_GLOBAL_BASE) /** Peripheral ENETC0_GLOBAL base address */ #define ENETC0_GLOBAL_BASE (0x4CC20000u) /** Peripheral ENETC0_GLOBAL base pointer */ #define ENETC0_GLOBAL ((ENETC_GLOBAL_Type *)ENETC0_GLOBAL_BASE) /** Peripheral ENETC1_GLOBAL base address */ #define ENETC1_GLOBAL_BASE (0x4CC60000u) /** Peripheral ENETC1_GLOBAL base pointer */ #define ENETC1_GLOBAL ((ENETC_GLOBAL_Type *)ENETC1_GLOBAL_BASE) /** Peripheral ENETC2_GLOBAL base address */ #define ENETC2_GLOBAL_BASE (0x4CCA0000u) /** Peripheral ENETC2_GLOBAL base pointer */ #define ENETC2_GLOBAL ((ENETC_GLOBAL_Type *)ENETC2_GLOBAL_BASE) /** Peripheral TMR0_GLOBAL base address */ #define TMR0_GLOBAL_BASE (0x4CCD0000u) /** Peripheral TMR0_GLOBAL base pointer */ #define TMR0_GLOBAL ((ENETC_GLOBAL_Type *)TMR0_GLOBAL_BASE) /** Array initializer of ENETC_GLOBAL peripheral base addresses */ #define ENETC_GLOBAL_BASE_ADDRS { EMDIO_GLOBAL_BASE, ENETC0_GLOBAL_BASE, ENETC1_GLOBAL_BASE, ENETC2_GLOBAL_BASE, TMR0_GLOBAL_BASE } /** Array initializer of ENETC_GLOBAL peripheral base pointers */ #define ENETC_GLOBAL_BASE_PTRS { EMDIO_GLOBAL, ENETC0_GLOBAL, ENETC1_GLOBAL, ENETC2_GLOBAL, TMR0_GLOBAL } /*! * @} */ /* end of group ENETC_GLOBAL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENETC_PCI_TYPE0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_PCI_TYPE0_Peripheral_Access_Layer ENETC_PCI_TYPE0 Peripheral Access Layer * @{ */ /** ENETC_PCI_TYPE0 - Register Layout Typedef */ typedef struct { __I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset: 0x0 */ __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */ __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */ __I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offset: 0x8 */ __IO uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */ uint8_t RESERVED_0[1]; __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */ uint8_t RESERVED_1[1]; __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */ __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */ __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */ __I uint32_t PCI_CFH_BAR3; /**< PCI base address register 3, offset: 0x1C */ __I uint32_t PCI_CFH_BAR4; /**< PCI base address register 4, offset: 0x20 */ __I uint32_t PCI_CFH_BAR5; /**< PCI base address register 5, offset: 0x24 */ uint8_t RESERVED_2[4]; __I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x2C */ __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */ uint8_t RESERVED_3[4]; __I uint8_t PCI_CFH_CAP_PTR; /**< PCI capabilities pointer register, offset: 0x34 */ uint8_t RESERVED_4[11]; __I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset: 0x40 */ __I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42 */ __I uint32_t PCI_CFC_PCIE_DEV_CAP; /**< PCI PCIe device capabilities register, offset: 0x44 */ __IO uint16_t PCI_CFC_PCIE_DEV_CTL; /**< PCI PCIe device control register, offset: 0x48 */ __I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4A */ uint8_t RESERVED_5[24]; __I uint32_t PCI_CFC_PCIE_DEV_CAP2; /**< PCI PCIe device capabilities 2 register, offset: 0x64 */ __I uint16_t PCI_CFC_PCIE_DEV_CTL2; /**< PCI PCIe device control 2 register, offset: 0x68 */ uint8_t RESERVED_6[22]; __I uint16_t PCI_CFC_MSIX_CAP_LIST; /**< PCI MSI-X capabilities list register, offset: 0x80 */ __IO uint16_t PCI_CFC_MSIX_MSG_CTL; /**< PCI MSI-X message control register, offset: 0x82 */ __I uint32_t PCI_CFC_MSIX_TABLE_OFF_BIR; /**< PCI MSI-X table offset/BIR register, offset: 0x84 */ __I uint32_t PCI_CFC_MSIX_PBA_OFF_BIR; /**< PCI MSI-X PBA offset/BIR register, offset: 0x88 */ uint8_t RESERVED_7[4]; __I uint16_t PCI_CFC_PCIPM_CAP_LIST; /**< PCI PCI-PM capabilities list register, offset: 0x90 */ __I uint16_t PCI_CFC_PCIPM_CAP; /**< PCI PCI-PM capabilities register, offset: 0x92 */ __IO uint16_t PCI_CFC_PCIPM_CTL_STAT; /**< PCI PCI-PM control and status register, offset: 0x94 */ uint8_t RESERVED_8[1]; uint8_t PCI_CFC_PCIPM_DATA; /**< PCI PCI-PM capabilities data register, offset: 0x97 */ uint8_t RESERVED_9[4]; __I uint16_t PCI_CFC_EA_CAP_LIST; /**< PCI EA capabilities list register, offset: 0x9C */ __I uint16_t PCI_CFC_EA_CAP; /**< PCI EA capabilities register, offset: 0x9E */ struct { /* offset: 0xA0, array step: 0x10 */ __I uint32_t PCI_CFC_EA_PE_FMT; /**< PCI EA per-entry 0 format register..PCI EA per-entry 2 format register, array offset: 0xA0, array step: 0x10, irregular array, not all indices are valid */ __I uint32_t PCI_CFC_EA_PE_BASE; /**< PCI EA per-entry 0 base register..PCI EA per-entry 2 base register, array offset: 0xA4, array step: 0x10, irregular array, not all indices are valid */ __I uint32_t PCI_CFC_EA_PE_MAXOFF; /**< PCI EA per-entry 0 max offset register..PCI EA per-entry 2 max offset register, array offset: 0xA8, array step: 0x10, irregular array, not all indices are valid */ __I uint32_t PCI_CFC_EA_PE_EXT_BASE; /**< PCI EA per-entry 0 extended base register..PCI EA per-entry 2 extended base register, array offset: 0xAC, array step: 0x10, irregular array, not all indices are valid */ } NUM_EA[3]; uint8_t RESERVED_10[48]; __I uint32_t PCIE_CFC_AER_EXT_CAP_HDR; /**< PCIe AER extended capability header, offset: 0x100 */ __IO uint32_t PCIE_CFC_AER_UCORR_ERR_STAT; /**< PCIe AER uncorrectable error status register, offset: 0x104 */ __IO uint32_t PCIE_CFC_AER_UCORR_ERR_MASK; /**< PCIe AER uncorrectable error mask register, offset: 0x108 */ __IO uint32_t PCIE_CFC_AER_UCORR_ERR_SEV; /**< PCIe AER uncorrectable error severity register, offset: 0x10C */ __IO uint32_t PCIE_CFC_AER_CORR_ERR_STAT; /**< PCIe AER correctable error status register, offset: 0x110 */ __IO uint32_t PCIE_CFC_AER_CORR_ERR_MASK; /**< PCIe AER correctable error mask register, offset: 0x114 */ __I uint32_t PCIE_CFC_AER_CAP_CTL; /**< PCIe AER capabilities and control register, offset: 0x118 */ uint8_t RESERVED_11[20]; __I uint32_t PCIE_CFC_ACS_CAP_HDR; /**< PCIe ACS capability header, offset: 0x130 */ __I uint16_t PCIE_CFC_ACS_CAP; /**< PCIe ACS capability register, offset: 0x134 */ __I uint16_t PCIE_CFC_ACS_CTL; /**< PCIe ACS control register, offset: 0x136 */ uint8_t RESERVED_12[8]; __I uint32_t PCIE_CFC_RTR_CAP_HDR; /**< PCIe readiness time reporting capability header, offset: 0x140 */ __I uint32_t PCIE_CFC_RTR_RTR1; /**< PCIe RTR readiness time reporting 1 register, offset: 0x144 */ __I uint32_t PCIE_CFC_RTR_RTR2; /**< PCIe RTR readiness time reporting 2 register, offset: 0x148 */ uint8_t RESERVED_13[4]; __I uint32_t PCIE_CFC_SRIOV_CAP_HDR; /**< PCIe SR-IOV capability header, offset: 0x150, not available in all instances (available on 18 out of 30) */ __I uint32_t PCIE_CFC_SRIOV_CAP; /**< PCIe SR-IOV capability register, offset: 0x154, not available in all instances (available on 18 out of 30) */ __IO uint16_t PCIE_CFC_SRIOV_CTL; /**< PCIe SR-IOV control register, offset: 0x158, not available in all instances (available on 18 out of 30) */ __I uint16_t PCIE_CFC_SRIOV_STAT; /**< PCIe SR-IOV status register, offset: 0x15A, not available in all instances (available on 18 out of 30) */ __I uint16_t PCIE_CFC_SRIOV_INIT_VFS; /**< PCIe SR-IOV initial VFs register, offset: 0x15C, not available in all instances (available on 18 out of 30) */ __I uint16_t PCIE_CFC_SRIOV_TOTAL_VFS; /**< PCIe SR-IOV total VFs register, offset: 0x15E, not available in all instances (available on 18 out of 30) */ __IO uint16_t PCIE_CFC_SRIOV_NUM_VFS; /**< PCIe SR-IOV num VFs register, offset: 0x160, not available in all instances (available on 18 out of 30) */ __I uint16_t PCIE_CFC_SRIOV_FUNC_DEP_LIST; /**< PCIe SR-IOV function dependency list register, offset: 0x162, not available in all instances (available on 18 out of 30) */ __I uint16_t PCIE_CFC_SRIOV_FIRST_VF_OFF; /**< PCIe SR-IOV first VF offset register, offset: 0x164, not available in all instances (available on 18 out of 30) */ __I uint16_t PCIE_CFC_SRIOV_VF_STRIDE; /**< PCIe SR-IOV VF stride register, offset: 0x166, not available in all instances (available on 18 out of 30) */ uint8_t RESERVED_14[2]; __I uint16_t PCIE_CFC_SRIOV_VF_DEV_ID; /**< PCIe SR-IOV VF device ID register, offset: 0x16A, not available in all instances (available on 18 out of 30) */ __I uint32_t PCIE_CFC_SRIOV_SUP_PAGE_SIZES; /**< PCIe SR-IOV supported page sizes ID register, offset: 0x16C, not available in all instances (available on 18 out of 30) */ __I uint32_t PCIE_CFC_SRIOV_SYS_PAGE_SIZE; /**< PCIe SR-IOV system page size ID register, offset: 0x170, not available in all instances (available on 18 out of 30) */ __I uint32_t PCIE_CFC_VF_BAR[6]; /**< PCIe SR-IOV VF base address register 0..PCIe SR-IOV VF base address register 5, array offset: 0x174, array step: 0x4, not available in all instances (available on 18 out of 30) */ __I uint32_t PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF; /**< PCIe SR-IOV VF migration state array offset register, offset: 0x18C, not available in all instances (available on 18 out of 30) */ } ENETC_PCI_TYPE0_Type; /* ---------------------------------------------------------------------------- -- ENETC_PCI_TYPE0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_PCI_TYPE0_Register_Masks ENETC_PCI_TYPE0 Register Masks * @{ */ /*! @name PCI_CFH_DID_VID - PCI device ID and vendor ID register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK (0xFFFF0000U) #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT (16U) #define ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK) /*! @} */ /*! @name PCI_CFH_CMD - PCI command register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK (0x2U) #define ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CMD_MEM_ACCESS_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK (0x4U) #define ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT (2U) #define ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK) /*! @} */ /*! @name PCI_CFH_STAT - PCI status register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK (0x10U) #define ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK) /*! @} */ /*! @name PCI_CFH_REVID_CLASSCODE - PCI revision ID and classcode register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK (0xFFU) #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK (0xFFFFFF00U) #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT (8U) #define ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK) /*! @} */ /*! @name PCI_CFH_CL_SIZE - PCI cache line size register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK (0xFFU) #define ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK) /*! @} */ /*! @name PCI_CFH_HDR_TYPE - PCI header type register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK (0x7FU) #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK (0x80U) #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT (7U) #define ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK) /*! @} */ /*! @name PCI_CFH_BAR0 - PCI base address register 0 */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK (0x1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK (0x6U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK (0x8U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK (0xFFFFFFF0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR1 - PCI base address register 1 */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK (0x1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK (0x6U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK (0x8U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK (0xFFFFFFF0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR2 - PCI base address register 2 */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK (0x1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK (0x6U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK (0x8U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK (0xFFFFFFF0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR3 - PCI base address register 3 */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK (0x1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK (0x6U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK (0x8U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK (0xFFFFFFF0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR4 - PCI base address register 4 */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK (0x1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK (0x6U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK (0x8U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK (0xFFFFFFF0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR5 - PCI base address register 5 */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK (0x1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK (0x6U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK (0x8U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK (0xFFFFFFF0U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_SUBSYS_VID - PCI subsystem vendor ID register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK) /*! @} */ /*! @name PCI_CFH_SUBSYS_ID - PCI subsystem ID register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK) /*! @} */ /*! @name PCI_CFH_CAP_PTR - PCI capabilities pointer register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK (0xFFU) #define ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR(x) (((uint8_t)(((uint8_t)(x)) << ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_CAP_LIST - PCI PCIe capabilities list register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK (0xFFU) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_CAP - PCI PCIe capabilities register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK (0xFU) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK (0xF0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK (0x3E00U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT (9U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CAP - PCI PCIe device capabilities register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK (0x10000000U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT (28U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CTL - PCI PCIe device control register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK (0x8000U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT (15U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_STAT - PCI PCIe device status register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK (0x20U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT (5U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CAP2 - PCI PCIe device capabilities 2 register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK (0xFU) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK (0x10U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CTL2 - PCI PCIe device control 2 register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK (0xFU) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK (0x10U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_CAP_LIST - PCI MSI-X capabilities list register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK (0xFFU) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_MSG_CTL - PCI MSI-X message control register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK (0x7FFU) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK (0x4000U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT (14U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK (0x8000U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT (15U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_TABLE_OFF_BIR - PCI MSI-X table offset/BIR register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK (0x7U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK (0xFFFFFFF8U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_PBA_OFF_BIR - PCI MSI-X PBA offset/BIR register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK (0x7U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK (0xFFFFFFF8U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK) /*! @} */ /*! @name PCI_CFC_PCIPM_CAP_LIST - PCI PCI-PM capabilities list register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK (0xFFU) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_PCIPM_CAP - PCI PCI-PM capabilities register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_MASK (0x7U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_VERSION_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK (0xF800U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT (11U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK) /*! @} */ /*! @name PCI_CFC_PCIPM_CTL_STAT - PCI PCI-PM control and status register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK (0x3U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK (0x8U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT (3U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_MASK (0x100U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_SHIFT (8U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_EN_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_MASK (0x8000U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_SHIFT (15U) #define ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_PCIPM_CTL_STAT_PME_STATUS_MASK) /*! @} */ /*! @name PCI_CFC_EA_CAP_LIST - PCI EA capabilities list register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_MASK (0xFFU) #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_EA_CAP - PCI EA capabilities register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_MASK (0x3FU) #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_CAP_NUM_ENTRIES_MASK) /*! @} */ /*! @name PCI_CFC_EA_PE_FMT - PCI EA per-entry 0 format register..PCI EA per-entry 2 format register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_MASK (0x7U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENTRY_SIZE_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_MASK (0xF0U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_SHIFT (4U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_BEI_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_MASK (0xFF00U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_SHIFT (8U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_PRIM_PROP_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_MASK (0xFF0000U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_SHIFT (16U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_SEC_PROP_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_MASK (0x40000000U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_SHIFT (30U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_WRITABLE_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_MASK (0x80000000U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_SHIFT (31U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_ENABLE_MASK) /*! @} */ /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_FMT_COUNT (3U) /*! @name PCI_CFC_EA_PE_BASE - PCI EA per-entry 0 base register..PCI EA per-entry 2 base register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_MASK (0x2U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_S_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_MASK (0xFFFFFFFCU) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_SHIFT (2U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_BASE_MASK) /*! @} */ /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_BASE_COUNT (3U) /*! @name PCI_CFC_EA_PE_MAXOFF - PCI EA per-entry 0 max offset register..PCI EA per-entry 2 max offset register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_MASK (0x2U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_SHIFT (1U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_S_MASK) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_MASK (0xFFFFFFFCU) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_SHIFT (2U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_MAX_OFFSET_MASK) /*! @} */ /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_MAXOFF_COUNT (3U) /*! @name PCI_CFC_EA_PE_EXT_BASE - PCI EA per-entry 0 extended base register..PCI EA per-entry 2 extended base register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_MASK (0xFFFFFFFFU) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_SHIFT)) & ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_BASE_MASK) /*! @} */ /* The count of ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE */ #define ENETC_PCI_TYPE0_PCI_CFC_EA_PE_EXT_BASE_COUNT (3U) /*! @name PCIE_CFC_AER_EXT_CAP_HDR - PCIe AER extended capability header */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT (16U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_AER_UCORR_ERR_STAT - PCIe AER uncorrectable error status register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_MASK (0x200000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_SHIFT (21U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_ACS_VIOLATION_STAT_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK (0x400000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT (22U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK) /*! @} */ /*! @name PCIE_CFC_AER_UCORR_ERR_MASK - PCIe AER uncorrectable error mask register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK (0x400000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT (22U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK) /*! @} */ /*! @name PCIE_CFC_AER_UCORR_ERR_SEV - PCIe AER uncorrectable error severity register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK (0x400000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT (22U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK) /*! @} */ /*! @name PCIE_CFC_AER_CORR_ERR_STAT - PCIe AER correctable error status register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK (0x4000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT (14U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK) /*! @} */ /*! @name PCIE_CFC_AER_CORR_ERR_MASK - PCIe AER correctable error mask register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK (0x4000U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT (14U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK) /*! @} */ /*! @name PCIE_CFC_AER_CAP_CTL - PCIe AER capabilities and control register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK (0x1FU) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK) /*! @} */ /*! @name PCIE_CFC_ACS_CAP_HDR - PCIe ACS capability header */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT (16U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_ACS_CAP - PCIe ACS capability register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK (0x2U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT (1U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK (0x4U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT (2U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK (0x40U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT (6U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK) /*! @} */ /*! @name PCIE_CFC_ACS_CTL - PCIe ACS control register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK (0x2U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT (1U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK (0x4U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT (2U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK (0x40U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT (6U) #define ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK) /*! @} */ /*! @name PCIE_CFC_RTR_CAP_HDR - PCIe readiness time reporting capability header */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT (16U) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_RTR_RTR1 - PCIe RTR readiness time reporting 1 register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK (0xFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT (0U) /*! RESET_TIME - Reset Time */ #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK (0x80000000U) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT (31U) /*! VALID - Valid */ #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK) /*! @} */ /*! @name PCIE_CFC_RTR_RTR2 - PCIe RTR readiness time reporting 2 register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK (0xFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT (0U) /*! FLR_TIME - FLR Time */ #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK (0xFFF000U) #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT (12U) /*! D3HOT_D0_TIME - D3 hot to D0 time */ #define ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_CAP_HDR - PCIe SR-IOV capability header */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_SHIFT (16U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_CAP_VER_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_CAP - PCIe SR-IOV capability register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_MASK (0x1U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_CAP_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_MASK (0x2U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_SHIFT (1U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_ARI_CAP_HIER_PRSV_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_MASK (0xFFE00000U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_SHIFT (21U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CAP_VF_MIGRATION_ING_MSG_NUM_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_CTL - PCIe SR-IOV control register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_MASK (0x1U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_ENABLE_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_MASK (0x2U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_ENABLE_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_MASK (0x4U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_SHIFT (2U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MIGRATION_INT_ENABLE_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_MASK (0x8U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_SHIFT (3U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_VF_MSE_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_MASK (0x10U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_SHIFT (4U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_ARI_CAP_HIERARCHY_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_MASK (0x400U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_SHIFT (10U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_D2_SUPPORT_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_MASK (0xF800U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_SHIFT (11U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_CTL_PME_SUPPORT_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_STAT - PCIe SR-IOV status register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_MASK (0x1U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_STAT_VF_MIGRATION_STATUS_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_INIT_VFS - PCIe SR-IOV initial VFs register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_INIT_VFS_INITIAL_VFS_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_TOTAL_VFS - PCIe SR-IOV total VFs register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_TOTAL_VFS_TOTAL_VFS_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_NUM_VFS - PCIe SR-IOV num VFs register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_NUM_VFS_NUM_VFS_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_FUNC_DEP_LIST - PCIe SR-IOV function dependency list register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FUNC_DEP_LIST_FUNC_DEP_LIST_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_FIRST_VF_OFF - PCIe SR-IOV first VF offset register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_FIRST_VF_OFF_FIRST_VF_OFFSET_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_VF_STRIDE - PCIe SR-IOV VF stride register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_STRIDE_VF_STRIDE_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_VF_DEV_ID - PCIe SR-IOV VF device ID register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_MASK (0xFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_DEV_ID_VF_DEVICE_ID_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_SUP_PAGE_SIZES - PCIe SR-IOV supported page sizes ID register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_MASK (0xFFFFFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SUP_PAGE_SIZES_SUP_PAGE_SIZES_MASK) /*! @} */ /*! @name PCIE_CFC_SRIOV_SYS_PAGE_SIZE - PCIe SR-IOV system page size ID register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_MASK (0xFFFFFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_SYS_PAGE_SIZE_SYS_PAGE_SIZE_MASK) /*! @} */ /*! @name PCIE_CFC_VF_BAR - PCIe SR-IOV VF base address register 0..PCIe SR-IOV VF base address register 5 */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_MASK (0x1U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_IO_IND_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_MASK (0x6U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_SHIFT (1U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_MEM_TYPE_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_MASK (0x8U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_SHIFT (3U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_PF_MEM_MASK) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_MASK (0xFFFFFFF0U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_SHIFT (4U) #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_ADDR_MASK) /*! @} */ /* The count of ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR */ #define ENETC_PCI_TYPE0_PCIE_CFC_VF_BAR_COUNT (6U) /*! @name PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF - PCIe SR-IOV VF migration state array offset register */ /*! @{ */ #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_MASK (0xFFFFFFFFU) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_SHIFT (0U) #define ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_SHIFT)) & ENETC_PCI_TYPE0_PCIE_CFC_SRIOV_VF_MIG_STATE_ARR_OFF_VF_MIG_STATE_ARR_OFF_MASK) /*! @} */ /*! * @} */ /* end of group ENETC_PCI_TYPE0_Register_Masks */ /* ENETC_PCI_TYPE0 - Peripheral instance base addresses */ /** Peripheral EMDIO0_PCI_HDR_TYPE0 base address */ #define EMDIO0_PCI_HDR_TYPE0_BASE (0x4CB00000u) /** Peripheral EMDIO0_PCI_HDR_TYPE0 base pointer */ #define EMDIO0_PCI_HDR_TYPE0 ((ENETC_PCI_TYPE0_Type *)EMDIO0_PCI_HDR_TYPE0_BASE) /** Peripheral ENETC0_PCI_HDR_TYPE0 base address */ #define ENETC0_PCI_HDR_TYPE0_BASE (0x4CA00000u) /** Peripheral ENETC0_PCI_HDR_TYPE0 base pointer */ #define ENETC0_PCI_HDR_TYPE0 ((ENETC_PCI_TYPE0_Type *)ENETC0_PCI_HDR_TYPE0_BASE) /** Peripheral ENETC1_PCI_HDR_TYPE0 base address */ #define ENETC1_PCI_HDR_TYPE0_BASE (0x4CA40000u) /** Peripheral ENETC1_PCI_HDR_TYPE0 base pointer */ #define ENETC1_PCI_HDR_TYPE0 ((ENETC_PCI_TYPE0_Type *)ENETC1_PCI_HDR_TYPE0_BASE) /** Peripheral ENETC2_PCI_HDR_TYPE0 base address */ #define ENETC2_PCI_HDR_TYPE0_BASE (0x4CA80000u) /** Peripheral ENETC2_PCI_HDR_TYPE0 base pointer */ #define ENETC2_PCI_HDR_TYPE0 ((ENETC_PCI_TYPE0_Type *)ENETC2_PCI_HDR_TYPE0_BASE) /** Peripheral TMR0_PCI_HDR_TYPE0 base address */ #define TMR0_PCI_HDR_TYPE0_BASE (0x4CAC0000u) /** Peripheral TMR0_PCI_HDR_TYPE0 base pointer */ #define TMR0_PCI_HDR_TYPE0 ((ENETC_PCI_TYPE0_Type *)TMR0_PCI_HDR_TYPE0_BASE) /** Array initializer of ENETC_PCI_TYPE0 peripheral base addresses */ #define ENETC_PCI_TYPE0_BASE_ADDRS { EMDIO0_PCI_HDR_TYPE0_BASE, ENETC0_PCI_HDR_TYPE0_BASE, ENETC1_PCI_HDR_TYPE0_BASE, ENETC2_PCI_HDR_TYPE0_BASE, TMR0_PCI_HDR_TYPE0_BASE } /** Array initializer of ENETC_PCI_TYPE0 peripheral base pointers */ #define ENETC_PCI_TYPE0_BASE_PTRS { EMDIO0_PCI_HDR_TYPE0, ENETC0_PCI_HDR_TYPE0, ENETC1_PCI_HDR_TYPE0, ENETC2_PCI_HDR_TYPE0, TMR0_PCI_HDR_TYPE0 } /*! * @} */ /* end of group ENETC_PCI_TYPE0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENETC_PF_EMDIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_PF_EMDIO_Peripheral_Access_Layer ENETC_PF_EMDIO Peripheral Access Layer * @{ */ /** ENETC_PF_EMDIO - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[7168]; __IO uint32_t EMDIO_CFG; /**< External MDIO configuration register, offset: 0x1C00 */ __IO uint32_t EMDIO_CTL; /**< External MDIO interface control register, offset: 0x1C04 */ __IO uint32_t EMDIO_DATA; /**< External MDIO interface data register, offset: 0x1C08 */ __IO uint32_t EMDIO_ADDR; /**< External MDIO register address register, offset: 0x1C0C */ __I uint32_t EMDIO_STAT; /**< External MDIO status register, offset: 0x1C10 */ uint8_t RESERVED_1[12]; __IO uint32_t PHY_STATUS_CFG; /**< PHY status configuration register, offset: 0x1C20 */ __IO uint32_t PHY_STATUS_CTL; /**< PHY status control register, offset: 0x1C24 */ __I uint32_t PHY_STATUS_DATA; /**< PHY status data register, offset: 0x1C28 */ __IO uint32_t PHY_STATUS_ADDR; /**< PHY status register address register, offset: 0x1C2C */ __IO uint32_t PHY_STATUS_EVENT; /**< PHY status event register, offset: 0x1C30 */ __IO uint32_t PHY_STATUS_MASK; /**< PHY status mask register, offset: 0x1C34 */ uint8_t RESERVED_2[8]; __I uint32_t MDIO_CFG; /**< MDIO configuration register, offset: 0x1C40 */ } ENETC_PF_EMDIO_Type; /* ---------------------------------------------------------------------------- -- ENETC_PF_EMDIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_PF_EMDIO_Register_Masks ENETC_PF_EMDIO Register Masks * @{ */ /*! @name EMDIO_CFG - External MDIO configuration register */ /*! @{ */ #define ENETC_PF_EMDIO_EMDIO_CFG_BSY2_MASK (0x1U) #define ENETC_PF_EMDIO_EMDIO_CFG_BSY2_SHIFT (0U) /*! BSY2 - Busy 2 (same as bit 31) * 0b0..An MDIO transaction is not occurring; software may access other MDIO registers. * 0b1..An MDIO transaction is occurring. */ #define ENETC_PF_EMDIO_EMDIO_CFG_BSY2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_BSY2_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_BSY2_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_MASK (0x2U) #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_SHIFT (1U) /*! MDIO_RD_ER * 0b0..No error * 0b1..The last read transaction received no response from a PHY; any data read should be considered invalid * (for example, the PHY address does not match any PHY available on the MDIO bus). */ #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_MDIO_RD_ER_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_MASK (0x1CU) #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_SHIFT (2U) /*! MDIO_HOLD * 0b000..1 NETC cycle * 0b001..3 NETC cycles * 0b010..5 NETC cycles (default - recommended value) * 0b011..7 NETC cycles * 0b100..9 NETC cycles * 0b101..11 NETC cycles * 0b110..13 NETC cycles * 0b111..15 NETC cycles */ #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_MDIO_HOLD_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_MASK (0x20U) #define ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_SHIFT (5U) /*! PRE_DIS * 0b0..Generation of MDIO preamble is enabled (default operation). * 0b1..Generation of MDIO preamble is disabled. */ #define ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_PRE_DIS_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_ENC45_MASK (0x40U) #define ENETC_PF_EMDIO_EMDIO_CFG_ENC45_SHIFT (6U) /*! ENC45 * 0b0..Clause 22 transactions are used. * 0b1..Clause 45 transactions are used. */ #define ENETC_PF_EMDIO_EMDIO_CFG_ENC45(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_ENC45_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_ENC45_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_MASK (0xFF80U) #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_SHIFT (7U) /*! MDIO_CLK_DIV - MDIO Clock Divisor */ #define ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_MDIO_CLK_DIV_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_MASK (0x70000U) #define ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_SHIFT (16U) /*! WHOAMI - Returns the virtual port ID. */ #define ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_WHOAMI_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_MASK (0x400000U) #define ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_SHIFT (22U) /*! EHOLD * 0b0..Normal operation. * 0b1..Extended operation */ #define ENETC_PF_EMDIO_EMDIO_CFG_EHOLD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_EHOLD_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_NEG_MASK (0x800000U) #define ENETC_PF_EMDIO_EMDIO_CFG_NEG_SHIFT (23U) /*! NEG * 0b0..Normal operation - positive edge * 0b1..MDIO is driven by master on MDC negative edge (default for external MDIOs). */ #define ENETC_PF_EMDIO_EMDIO_CFG_NEG(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_NEG_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_NEG_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_MASK (0x10000000U) #define ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_SHIFT (28U) /*! ADDR_ERR * 0b0..Normal * 0b1..Error. An access control violation has occurred. The request address used does not match the MDIO PHY's * address (clause 22) or MDIO port address (clause 45) assigned. */ #define ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_ADDR_ERR_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_CIM_MASK (0x20000000U) #define ENETC_PF_EMDIO_EMDIO_CFG_CIM_SHIFT (29U) /*! CIM * 0b0..Masked * 0b1..Enabled */ #define ENETC_PF_EMDIO_EMDIO_CFG_CIM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_CIM_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_CIM_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_CMP_MASK (0x40000000U) #define ENETC_PF_EMDIO_EMDIO_CFG_CMP_SHIFT (30U) /*! CMP * 0b0..An MDIO command completion did not occur. * 0b1..An MDIO command completion occurred. */ #define ENETC_PF_EMDIO_EMDIO_CFG_CMP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_CMP_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_CMP_MASK) #define ENETC_PF_EMDIO_EMDIO_CFG_BSY1_MASK (0x80000000U) #define ENETC_PF_EMDIO_EMDIO_CFG_BSY1_SHIFT (31U) /*! BSY1 - Busy 1 * 0b0..An MDIO transaction is not occurring; software may access other MDIO registers. * 0b1..An MDIO transaction is occurring. */ #define ENETC_PF_EMDIO_EMDIO_CFG_BSY1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CFG_BSY1_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CFG_BSY1_MASK) /*! @} */ /*! @name EMDIO_CTL - External MDIO interface control register */ /*! @{ */ #define ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_MASK (0x1FU) #define ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_SHIFT (0U) /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */ #define ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_DEV_ADDR_MASK) #define ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_MASK (0x3E0U) #define ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_SHIFT (5U) /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */ #define ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_PORT_ADDR_MASK) #define ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_MASK (0x4000U) #define ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_SHIFT (14U) /*! POST_INC - MDIO read with address post-increment initiation. Self-clearing once transaction is complete. */ #define ENETC_PF_EMDIO_EMDIO_CTL_POST_INC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_POST_INC_MASK) #define ENETC_PF_EMDIO_EMDIO_CTL_READ_MASK (0x8000U) #define ENETC_PF_EMDIO_EMDIO_CTL_READ_SHIFT (15U) /*! READ - MDIO read initiation. */ #define ENETC_PF_EMDIO_EMDIO_CTL_READ(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_READ_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_READ_MASK) #define ENETC_PF_EMDIO_EMDIO_CTL_BSY_MASK (0x80000000U) #define ENETC_PF_EMDIO_EMDIO_CTL_BSY_SHIFT (31U) /*! BSY - MDIO busy */ #define ENETC_PF_EMDIO_EMDIO_CTL_BSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_CTL_BSY_SHIFT)) & ENETC_PF_EMDIO_EMDIO_CTL_BSY_MASK) /*! @} */ /*! @name EMDIO_DATA - External MDIO interface data register */ /*! @{ */ #define ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_MASK (0xFFFFU) #define ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_SHIFT (0U) /*! MDIO_DATA - 16-bit MDIO data. */ #define ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_SHIFT)) & ENETC_PF_EMDIO_EMDIO_DATA_MDIO_DATA_MASK) /*! @} */ /*! @name EMDIO_ADDR - External MDIO register address register */ /*! @{ */ #define ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_MASK (0xFFFFU) #define ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_SHIFT (0U) /*! REGADDR - MDIO PHY register address. */ #define ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_SHIFT)) & ENETC_PF_EMDIO_EMDIO_ADDR_REGADDR_MASK) /*! @} */ /*! @name EMDIO_STAT - External MDIO status register */ /*! @{ */ #define ENETC_PF_EMDIO_EMDIO_STAT_BSY_MASK (0x1U) #define ENETC_PF_EMDIO_EMDIO_STAT_BSY_SHIFT (0U) /*! BSY - Global MDIO busy */ #define ENETC_PF_EMDIO_EMDIO_STAT_BSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_BSY_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_BSY_MASK) #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_MASK (0x1F00U) #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_SHIFT (8U) /*! WHT_LIST - PHY white list */ #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_MASK) #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_MASK (0x8000U) #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_SHIFT (15U) /*! WHT_LIST_ENA - PHY white list enable */ #define ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_WHT_LIST_ENA_MASK) #define ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_MASK (0x70000U) #define ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_SHIFT (16U) /*! PORT_ID - Port ID */ #define ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_PORT_ID_MASK) #define ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_MASK (0x80000U) #define ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_SHIFT (19U) /*! REQ_TYPE - Port ID */ #define ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_SHIFT)) & ENETC_PF_EMDIO_EMDIO_STAT_REQ_TYPE_MASK) /*! @} */ /*! @name PHY_STATUS_CFG - PHY status configuration register */ /*! @{ */ #define ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_MASK (0x1U) #define ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_SHIFT (0U) /*! BSY - MDIO busy */ #define ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CFG_BSY_MASK) #define ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_MASK (0x2U) #define ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_SHIFT (1U) /*! MDIO_RD_ER - MDIO read error */ #define ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CFG_MDIO_RD_ER_MASK) #define ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_MASK (0xFFFF0000U) #define ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_SHIFT (16U) /*! STATUS_INTERVAL - PHY status read interval */ #define ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CFG_STATUS_INTERVAL_MASK) /*! @} */ /*! @name PHY_STATUS_CTL - PHY status control register */ /*! @{ */ #define ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_MASK (0x1FU) #define ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_SHIFT (0U) /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */ #define ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CTL_DEV_ADDR_MASK) #define ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_MASK (0x3E0U) #define ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_SHIFT (5U) /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */ #define ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_CTL_PORT_ADDR_MASK) /*! @} */ /*! @name PHY_STATUS_DATA - PHY status data register */ /*! @{ */ #define ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_MASK (0xFFFFU) #define ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_SHIFT (0U) /*! MDIO_DATA - 16-bit MDIO data */ #define ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_DATA_MDIO_DATA_MASK) #define ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_MASK (0xFFFF0000U) #define ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_SHIFT (16U) /*! CURR_CNT - Current count */ #define ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_DATA_CURR_CNT_MASK) /*! @} */ /*! @name PHY_STATUS_ADDR - PHY status register address register */ /*! @{ */ #define ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_MASK (0xFFFFU) #define ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_SHIFT (0U) /*! REGADDR - MDIO PHY register address. Address of the register within the Clause 45 PHY device from which data is to be read. */ #define ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_ADDR_REGADDR_MASK) /*! @} */ /*! @name PHY_STATUS_EVENT - PHY status event register */ /*! @{ */ #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_MASK (0xFFFFU) #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_SHIFT (0U) /*! STATUS_EVENT_HL - Status event high-to-low. Set to 1 if a 1->0 transition on a corresponding data bit has occurred. Write 1 to clear. */ #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_HL_MASK) #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_MASK (0xFFFF0000U) #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_SHIFT (16U) /*! STATUS_EVENT_LH - Status event low-to-high. Set to 1 if a 0->1 transition on a corresponding data bit has occurred. Write 1 to clear. */ #define ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_EVENT_STATUS_EVENT_LH_MASK) /*! @} */ /*! @name PHY_STATUS_MASK - PHY status mask register */ /*! @{ */ #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_MASK (0xFFFFU) #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_SHIFT (0U) /*! STATUS_MASK_HL - Status high-to-low mask. If set to 1, assert an interrupt if the corresponding event bit is set. */ #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_HL_MASK) #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_MASK (0xFFFF0000U) #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_SHIFT (16U) /*! STATUS_MASK_LH - Status mask low-to-high. If set to 1, assert an interrupt if the corresponding event bit is set. */ #define ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_SHIFT)) & ENETC_PF_EMDIO_PHY_STATUS_MASK_STATUS_MASK_LH_MASK) /*! @} */ /*! @name MDIO_CFG - MDIO configuration register */ /*! @{ */ #define ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_MASK (0x10U) #define ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_SHIFT (4U) /*! MDIO_MODE - MDIO pin mode */ #define ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_SHIFT)) & ENETC_PF_EMDIO_MDIO_CFG_MDIO_MODE_MASK) #define ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_MASK (0x20U) #define ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_SHIFT (5U) /*! MDC_MODE - MDC pin mode */ #define ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_SHIFT)) & ENETC_PF_EMDIO_MDIO_CFG_MDC_MODE_MASK) /*! @} */ /*! * @} */ /* end of group ENETC_PF_EMDIO_Register_Masks */ /* ENETC_PF_EMDIO - Peripheral instance base addresses */ /** Peripheral EMDIO_BASE base address */ #define EMDIO_BASE_BASE (0x4CCE0000u) /** Peripheral EMDIO_BASE base pointer */ #define EMDIO_BASE ((ENETC_PF_EMDIO_Type *)EMDIO_BASE_BASE) /** Array initializer of ENETC_PF_EMDIO peripheral base addresses */ #define ENETC_PF_EMDIO_BASE_ADDRS { EMDIO_BASE_BASE } /** Array initializer of ENETC_PF_EMDIO peripheral base pointers */ #define ENETC_PF_EMDIO_BASE_PTRS { EMDIO_BASE } /*! * @} */ /* end of group ENETC_PF_EMDIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENETC_PF_TMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_PF_TMR_Peripheral_Access_Layer ENETC_PF_TMR Peripheral Access Layer * @{ */ /** ENETC_PF_TMR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0xFC */ __I uint32_t TMR_ID; /**< Module ID, array offset: 0x0, array step: 0xFC */ uint8_t RESERVED_0[4]; __I uint32_t TMR_CAPR; /**< Timer Capability, array offset: 0x8, array step: 0xFC */ uint8_t RESERVED_1[20]; __I uint32_t TMR_FRT_L; /**< Timer Free Running Time Low, array offset: 0x20, array step: 0xFC */ __I uint32_t TMR_FRT_H; /**< Timer Free Running Time High, array offset: 0x24, array step: 0xFC */ __I uint32_t TMR_SRT_L; /**< Timer Synchronous Time Low, array offset: 0x28, array step: 0xFC */ __I uint32_t TMR_SRT_H; /**< Timer Synchronous Time High, array offset: 0x2C, array step: 0xFC */ __I uint32_t TMR_DEF_CNT_L; /**< Default ns Timer Counter Low, array offset: 0x30, array step: 0xFC */ __I uint32_t TMR_DEF_CNT_H; /**< Default ns Timer Counter High, array offset: 0x34, array step: 0xFC */ uint8_t RESERVED_2[72]; __IO uint32_t TMR_CTRL; /**< Timer Control, array offset: 0x80, array step: 0xFC */ __IO uint32_t TMR_TEVENT; /**< Timer Event, array offset: 0x84, array step: 0xFC */ __IO uint32_t TMR_TEMASK; /**< Timer Event Mask, array offset: 0x88, array step: 0xFC */ __IO uint32_t TMR_MSIVEC; /**< Timer MSI-X Vector, array offset: 0x8C, array step: 0xFC */ uint8_t RESERVED_3[4]; __I uint32_t TMR_STAT; /**< Timer Status, array offset: 0x94, array step: 0xFC */ __IO uint32_t TMR_CNT_L; /**< Timer Counter Low, array offset: 0x98, array step: 0xFC */ __IO uint32_t TMR_CNT_H; /**< Timer Counter High, array offset: 0x9C, array step: 0xFC */ __IO uint32_t TMR_ADD; /**< Timer Addend, array offset: 0xA0, array step: 0xFC */ __I uint32_t TMR_ACC; /**< Timer Accumulator, array offset: 0xA4, array step: 0xFC */ __IO uint32_t TMR_PRSC; /**< Timer Prescale, array offset: 0xA8, array step: 0xFC */ __IO uint32_t TMR_ECTRL; /**< Extended Timer Control, array offset: 0xAC, array step: 0xFC */ __IO uint32_t TMROFF_L; /**< Timer Offset Low, array offset: 0xB0, array step: 0xFC */ __IO uint32_t TMROFF_H; /**< Timer Offset High, array offset: 0xB4, array step: 0xFC */ struct { /* offset: 0xB8, array step: index*0xFC, index2*0x8 */ __IO uint32_t TMR_ALARM_L; /**< Alarm Time Comparator Low, array offset: 0xB8, array step: index*0xFC, index2*0x8 */ __IO uint32_t TMR_ALARM_H; /**< Alarm Time Comparator High, array offset: 0xBC, array step: index*0xFC, index2*0x8 */ } TMR_ALARMM[2]; uint8_t RESERVED_4[4]; __IO uint32_t TMR_ALARM_CTRL; /**< Timer Alarm Control, array offset: 0xCC, array step: 0xFC */ __IO uint32_t TMR_FIPER[3]; /**< Timer Fixed Interval Period, array offset: 0xD0, array step: index*0xFC, index2*0x4 */ __IO uint32_t TMR_FIPER_CTRL; /**< Timer FIPER Control, array offset: 0xDC, array step: 0xFC */ struct { /* offset: 0xE0, array step: index*0xFC, index2*0x8 */ __I uint32_t TMR_ETTS_L; /**< External Trigger Stamp, array offset: 0xE0, array step: index*0xFC, index2*0x8 */ __I uint32_t TMR_ETTS_H; /**< External Trigger Stamp, array offset: 0xE4, array step: index*0xFC, index2*0x8 */ } TMR_ETTSN[2]; __I uint32_t TMR_CUR_TIME_L; /**< Timer Current Time Low, array offset: 0xF0, array step: 0xFC */ __I uint32_t TMR_CUR_TIME_H; /**< Timer Current Time High, array offset: 0xF4, array step: 0xFC */ __IO uint32_t TMR_PARAM; /**< Timer Parameter, array offset: 0xF8, array step: 0xFC */ } ALL_REG_ARRAYS[1]; } ENETC_PF_TMR_Type; /* ---------------------------------------------------------------------------- -- ENETC_PF_TMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_PF_TMR_Register_Masks ENETC_PF_TMR Register Masks * @{ */ /*! @name TMR_ID - Module ID */ /*! @{ */ #define ENETC_PF_TMR_TMR_ID_REV_MN_MASK (0xFFU) #define ENETC_PF_TMR_TMR_ID_REV_MN_SHIFT (0U) /*! REV_MN - Minor revision */ #define ENETC_PF_TMR_TMR_ID_REV_MN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ID_REV_MN_SHIFT)) & ENETC_PF_TMR_TMR_ID_REV_MN_MASK) #define ENETC_PF_TMR_TMR_ID_REV_MJ_MASK (0xFF00U) #define ENETC_PF_TMR_TMR_ID_REV_MJ_SHIFT (8U) /*! REV_MJ - Major revision */ #define ENETC_PF_TMR_TMR_ID_REV_MJ(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ID_REV_MJ_SHIFT)) & ENETC_PF_TMR_TMR_ID_REV_MJ_MASK) #define ENETC_PF_TMR_TMR_ID_TMR_ID_MASK (0xFFFF0000U) #define ENETC_PF_TMR_TMR_ID_TMR_ID_SHIFT (16U) /*! TMR_ID - Timer IP ID */ #define ENETC_PF_TMR_TMR_ID_TMR_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ID_TMR_ID_SHIFT)) & ENETC_PF_TMR_TMR_ID_TMR_ID_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ID */ #define ENETC_PF_TMR_TMR_ID_COUNT (1U) /*! @name TMR_CAPR - Timer Capability */ /*! @{ */ #define ENETC_PF_TMR_TMR_CAPR_IEEE_1722_MASK (0x1U) #define ENETC_PF_TMR_TMR_CAPR_IEEE_1722_SHIFT (0U) /*! IEEE_1722 * 0b0..Not supported * 0b1..Supported */ #define ENETC_PF_TMR_TMR_CAPR_IEEE_1722(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_IEEE_1722_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_IEEE_1722_MASK) #define ENETC_PF_TMR_TMR_CAPR_ECADJ_MASK (0x2U) #define ENETC_PF_TMR_TMR_CAPR_ECADJ_SHIFT (1U) #define ENETC_PF_TMR_TMR_CAPR_ECADJ(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_ECADJ_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_ECADJ_MASK) #define ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_MASK (0x4U) #define ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_SHIFT (2U) #define ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_IEEE_8021AS_REV_MASK) #define ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_MASK (0x10000U) #define ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_SHIFT (16U) #define ENETC_PF_TMR_TMR_CAPR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_SHIFT)) & ENETC_PF_TMR_TMR_CAPR_NUM_MSIX_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_CAPR */ #define ENETC_PF_TMR_TMR_CAPR_COUNT (1U) /*! @name TMR_FRT_L - Timer Free Running Time Low */ /*! @{ */ #define ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_SHIFT (0U) #define ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_SHIFT)) & ENETC_PF_TMR_TMR_FRT_L_TMR_FRT_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_FRT_L */ #define ENETC_PF_TMR_TMR_FRT_L_COUNT (1U) /*! @name TMR_FRT_H - Timer Free Running Time High */ /*! @{ */ #define ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_SHIFT (0U) #define ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_SHIFT)) & ENETC_PF_TMR_TMR_FRT_H_TMR_FRT_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_FRT_H */ #define ENETC_PF_TMR_TMR_FRT_H_COUNT (1U) /*! @name TMR_SRT_L - Timer Synchronous Time Low */ /*! @{ */ #define ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_SHIFT (0U) #define ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_SHIFT)) & ENETC_PF_TMR_TMR_SRT_L_TMR_SRT_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_SRT_L */ #define ENETC_PF_TMR_TMR_SRT_L_COUNT (1U) /*! @name TMR_SRT_H - Timer Synchronous Time High */ /*! @{ */ #define ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_SHIFT (0U) #define ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_SHIFT)) & ENETC_PF_TMR_TMR_SRT_H_TMR_SRT_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_SRT_H */ #define ENETC_PF_TMR_TMR_SRT_H_COUNT (1U) /*! @name TMR_DEF_CNT_L - Default ns Timer Counter Low */ /*! @{ */ #define ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_SHIFT (0U) #define ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_SHIFT)) & ENETC_PF_TMR_TMR_DEF_CNT_L_TMR_DEF_CNT_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_DEF_CNT_L */ #define ENETC_PF_TMR_TMR_DEF_CNT_L_COUNT (1U) /*! @name TMR_DEF_CNT_H - Default ns Timer Counter High */ /*! @{ */ #define ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_SHIFT (0U) #define ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_SHIFT)) & ENETC_PF_TMR_TMR_DEF_CNT_H_TMR_DEF_CNT_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_DEF_CNT_H */ #define ENETC_PF_TMR_TMR_DEF_CNT_H_COUNT (1U) /*! @name TMR_CTRL - Timer Control */ /*! @{ */ #define ENETC_PF_TMR_TMR_CTRL_CK_SEL_MASK (0x3U) #define ENETC_PF_TMR_TMR_CTRL_CK_SEL_SHIFT (0U) /*! CK_SEL - Timer Reference Clock Source Select */ #define ENETC_PF_TMR_TMR_CTRL_CK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_CK_SEL_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_CK_SEL_MASK) #define ENETC_PF_TMR_TMR_CTRL_TE_MASK (0x4U) #define ENETC_PF_TMR_TMR_CTRL_TE_SHIFT (2U) /*! TE - Timer enable */ #define ENETC_PF_TMR_TMR_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_TE_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_TE_MASK) #define ENETC_PF_TMR_TMR_CTRL_CIPH_MASK (0x40U) #define ENETC_PF_TMR_TMR_CTRL_CIPH_SHIFT (6U) /*! CIPH - External oscillator input clock phase */ #define ENETC_PF_TMR_TMR_CTRL_CIPH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_CIPH_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_CIPH_MASK) #define ENETC_PF_TMR_TMR_CTRL_COPH_MASK (0x80U) #define ENETC_PF_TMR_TMR_CTRL_COPH_SHIFT (7U) /*! COPH - Generated clock (TMR_GCLK) output phase. */ #define ENETC_PF_TMR_TMR_CTRL_COPH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_COPH_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_COPH_MASK) #define ENETC_PF_TMR_TMR_CTRL_ETEP1_MASK (0x100U) #define ENETC_PF_TMR_TMR_CTRL_ETEP1_SHIFT (8U) /*! ETEP1 - External trigger 1 edge polarity */ #define ENETC_PF_TMR_TMR_CTRL_ETEP1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ETEP1_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ETEP1_MASK) #define ENETC_PF_TMR_TMR_CTRL_ETEP2_MASK (0x200U) #define ENETC_PF_TMR_TMR_CTRL_ETEP2_SHIFT (9U) /*! ETEP2 - External trigger 2 edge polarity */ #define ENETC_PF_TMR_TMR_CTRL_ETEP2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ETEP2_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ETEP2_MASK) #define ENETC_PF_TMR_TMR_CTRL_COMP_MODE_MASK (0x8000U) #define ENETC_PF_TMR_TMR_CTRL_COMP_MODE_SHIFT (15U) /*! COMP_MODE - Mode bit to allow atomic writes to TCLK_PERIOD and TMR_ADD */ #define ENETC_PF_TMR_TMR_CTRL_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_COMP_MODE_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_COMP_MODE_MASK) #define ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_MASK (0x3FF0000U) #define ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_SHIFT (16U) /*! TCLK_PERIOD - Timer reference clock period */ #define ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_TCLK_PERIOD_MASK) #define ENETC_PF_TMR_TMR_CTRL_PP2L_MASK (0x4000000U) #define ENETC_PF_TMR_TMR_CTRL_PP2L_SHIFT (26U) /*! PP2L - Fiper2 pulse loop back mode enabled */ #define ENETC_PF_TMR_TMR_CTRL_PP2L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_PP2L_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_PP2L_MASK) #define ENETC_PF_TMR_TMR_CTRL_PP1L_MASK (0x8000000U) #define ENETC_PF_TMR_TMR_CTRL_PP1L_SHIFT (27U) /*! PP1L - Fiper1 pulse loop back mode enabled */ #define ENETC_PF_TMR_TMR_CTRL_PP1L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_PP1L_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_PP1L_MASK) #define ENETC_PF_TMR_TMR_CTRL_FS_MASK (0x10000000U) #define ENETC_PF_TMR_TMR_CTRL_FS_SHIFT (28U) /*! FS - FIPER start indication */ #define ENETC_PF_TMR_TMR_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_FS_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_FS_MASK) #define ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_MASK (0x20000000U) #define ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_SHIFT (29U) /*! SHADOW_DIS - shadow Register disable */ #define ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_SHADOW_DIS_MASK) #define ENETC_PF_TMR_TMR_CTRL_ALM2P_MASK (0x40000000U) #define ENETC_PF_TMR_TMR_CTRL_ALM2P_SHIFT (30U) /*! ALM2P - Alarm2 output polarity */ #define ENETC_PF_TMR_TMR_CTRL_ALM2P(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ALM2P_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ALM2P_MASK) #define ENETC_PF_TMR_TMR_CTRL_ALM1P_MASK (0x80000000U) #define ENETC_PF_TMR_TMR_CTRL_ALM1P_SHIFT (31U) /*! ALM1P - Alarm1 output polarity */ #define ENETC_PF_TMR_TMR_CTRL_ALM1P(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CTRL_ALM1P_SHIFT)) & ENETC_PF_TMR_TMR_CTRL_ALM1P_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_CTRL */ #define ENETC_PF_TMR_TMR_CTRL_COUNT (1U) /*! @name TMR_TEVENT - Timer Event */ /*! @{ */ #define ENETC_PF_TMR_TMR_TEVENT_PP3EN_MASK (0x20U) #define ENETC_PF_TMR_TMR_TEVENT_PP3EN_SHIFT (5U) #define ENETC_PF_TMR_TMR_TEVENT_PP3EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_PP3EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_PP3EN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_PP2EN_MASK (0x40U) #define ENETC_PF_TMR_TMR_TEVENT_PP2EN_SHIFT (6U) #define ENETC_PF_TMR_TMR_TEVENT_PP2EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_PP2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_PP2EN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_PP1EN_MASK (0x80U) #define ENETC_PF_TMR_TMR_TEVENT_PP1EN_SHIFT (7U) #define ENETC_PF_TMR_TMR_TEVENT_PP1EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_PP1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_PP1EN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ALM1EN_MASK (0x10000U) #define ENETC_PF_TMR_TMR_TEVENT_ALM1EN_SHIFT (16U) #define ENETC_PF_TMR_TMR_TEVENT_ALM1EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ALM1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ALM1EN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ALM2EN_MASK (0x20000U) #define ENETC_PF_TMR_TMR_TEVENT_ALM2EN_SHIFT (17U) #define ENETC_PF_TMR_TMR_TEVENT_ALM2EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ALM2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ALM2EN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_MASK (0x100000U) #define ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_SHIFT (20U) #define ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS1_THREN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_MASK (0x200000U) #define ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_SHIFT (21U) #define ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ETS1EN_MASK (0x1000000U) #define ENETC_PF_TMR_TMR_TEVENT_ETS1EN_SHIFT (24U) /*! ETS1EN - External trigger 1 new timestamp sample event available */ #define ENETC_PF_TMR_TMR_TEVENT_ETS1EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS1EN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ETS2EN_MASK (0x2000000U) #define ENETC_PF_TMR_TMR_TEVENT_ETS2EN_SHIFT (25U) /*! ETS2EN - External trigger 2 new timestamp sample event available */ #define ENETC_PF_TMR_TMR_TEVENT_ETS2EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS2EN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_MASK (0x10000000U) #define ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_SHIFT (28U) /*! ETS1_OVEN - External trigger 1 timestamp FIFO Overflow event occurred */ #define ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_MASK) #define ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_MASK (0x20000000U) #define ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_SHIFT (29U) /*! ETS2_OVEN - External trigger 2 timestamp FIFO Overflow event occurred */ #define ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_TEVENT */ #define ENETC_PF_TMR_TMR_TEVENT_COUNT (1U) /*! @name TMR_TEMASK - Timer Event Mask */ /*! @{ */ #define ENETC_PF_TMR_TMR_TEMASK_PP3EN_MASK (0x20U) #define ENETC_PF_TMR_TMR_TEMASK_PP3EN_SHIFT (5U) #define ENETC_PF_TMR_TMR_TEMASK_PP3EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_PP3EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_PP3EN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_PP2EN_MASK (0x40U) #define ENETC_PF_TMR_TMR_TEMASK_PP2EN_SHIFT (6U) #define ENETC_PF_TMR_TMR_TEMASK_PP2EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_PP2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_PP2EN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_PP1EN_MASK (0x80U) #define ENETC_PF_TMR_TMR_TEMASK_PP1EN_SHIFT (7U) #define ENETC_PF_TMR_TMR_TEMASK_PP1EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_PP1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_PP1EN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ALM1EN_MASK (0x10000U) #define ENETC_PF_TMR_TMR_TEMASK_ALM1EN_SHIFT (16U) #define ENETC_PF_TMR_TMR_TEMASK_ALM1EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ALM1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ALM1EN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ALM2EN_MASK (0x20000U) #define ENETC_PF_TMR_TMR_TEMASK_ALM2EN_SHIFT (17U) #define ENETC_PF_TMR_TMR_TEMASK_ALM2EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ALM2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ALM2EN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_MASK (0x100000U) #define ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_SHIFT (20U) #define ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_MASK (0x200000U) #define ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_SHIFT (21U) #define ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ETS1EN_MASK (0x1000000U) #define ENETC_PF_TMR_TMR_TEMASK_ETS1EN_SHIFT (24U) #define ENETC_PF_TMR_TMR_TEMASK_ETS1EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS1EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS1EN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ETS2EN_MASK (0x2000000U) #define ENETC_PF_TMR_TMR_TEMASK_ETS2EN_SHIFT (25U) #define ENETC_PF_TMR_TMR_TEMASK_ETS2EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS2EN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS2EN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_MASK (0x10000000U) #define ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_SHIFT (28U) #define ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_MASK) #define ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_MASK (0x20000000U) #define ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_SHIFT (29U) #define ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_SHIFT)) & ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_TEMASK */ #define ENETC_PF_TMR_TMR_TEMASK_COUNT (1U) /*! @name TMR_MSIVEC - Timer MSI-X Vector */ /*! @{ */ #define ENETC_PF_TMR_TMR_MSIVEC_VECTOR_MASK (0x1U) #define ENETC_PF_TMR_TMR_MSIVEC_VECTOR_SHIFT (0U) /*! VECTOR - Vector */ #define ENETC_PF_TMR_TMR_MSIVEC_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_MSIVEC_VECTOR_SHIFT)) & ENETC_PF_TMR_TMR_MSIVEC_VECTOR_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_MSIVEC */ #define ENETC_PF_TMR_TMR_MSIVEC_COUNT (1U) /*! @name TMR_STAT - Timer Status */ /*! @{ */ #define ENETC_PF_TMR_TMR_STAT_ETS1_VLD_MASK (0x1000000U) #define ENETC_PF_TMR_TMR_STAT_ETS1_VLD_SHIFT (24U) #define ENETC_PF_TMR_TMR_STAT_ETS1_VLD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_STAT_ETS1_VLD_SHIFT)) & ENETC_PF_TMR_TMR_STAT_ETS1_VLD_MASK) #define ENETC_PF_TMR_TMR_STAT_ETS2_VLD_MASK (0x2000000U) #define ENETC_PF_TMR_TMR_STAT_ETS2_VLD_SHIFT (25U) #define ENETC_PF_TMR_TMR_STAT_ETS2_VLD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_STAT_ETS2_VLD_SHIFT)) & ENETC_PF_TMR_TMR_STAT_ETS2_VLD_MASK) #define ENETC_PF_TMR_TMR_STAT_RCD_MASK (0x80000000U) #define ENETC_PF_TMR_TMR_STAT_RCD_SHIFT (31U) /*! RCD - Timer Reference Clock Detected * 0b0..Reference Clock has not been detected as active. Registers in timer clock domain are not allowed to be * accessed; reads return 0, writes are ignored. * 0b1..Reference Clock has been detected as active. Registers in timer clock domain are allowed to be accessed. */ #define ENETC_PF_TMR_TMR_STAT_RCD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_STAT_RCD_SHIFT)) & ENETC_PF_TMR_TMR_STAT_RCD_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_STAT */ #define ENETC_PF_TMR_TMR_STAT_COUNT (1U) /*! @name TMR_CNT_L - Timer Counter Low */ /*! @{ */ #define ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_SHIFT (0U) /*! TMR_CNT_L - Timer counter register. */ #define ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_SHIFT)) & ENETC_PF_TMR_TMR_CNT_L_TMR_CNT_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_CNT_L */ #define ENETC_PF_TMR_TMR_CNT_L_COUNT (1U) /*! @name TMR_CNT_H - Timer Counter High */ /*! @{ */ #define ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_SHIFT (0U) /*! TMR_CNT_H - Timer counter register. */ #define ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_SHIFT)) & ENETC_PF_TMR_TMR_CNT_H_TMR_CNT_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_CNT_H */ #define ENETC_PF_TMR_TMR_CNT_H_COUNT (1U) /*! @name TMR_ADD - Timer Addend */ /*! @{ */ #define ENETC_PF_TMR_TMR_ADD_ADDEND_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_ADD_ADDEND_SHIFT (0U) /*! ADDEND - Timer addend. */ #define ENETC_PF_TMR_TMR_ADD_ADDEND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ADD_ADDEND_SHIFT)) & ENETC_PF_TMR_TMR_ADD_ADDEND_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ADD */ #define ENETC_PF_TMR_TMR_ADD_COUNT (1U) /*! @name TMR_ACC - Timer Accumulator */ /*! @{ */ #define ENETC_PF_TMR_TMR_ACC_TMR_ACC_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_ACC_TMR_ACC_SHIFT (0U) /*! TMR_ACC - 32-bit timer accumulator register */ #define ENETC_PF_TMR_TMR_ACC_TMR_ACC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ACC_TMR_ACC_SHIFT)) & ENETC_PF_TMR_TMR_ACC_TMR_ACC_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ACC */ #define ENETC_PF_TMR_TMR_ACC_COUNT (1U) /*! @name TMR_PRSC - Timer Prescale */ /*! @{ */ #define ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_MASK (0xFFFFU) #define ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_SHIFT (0U) /*! PRSC_OCK - Output clock division prescale factor. */ #define ENETC_PF_TMR_TMR_PRSC_PRSC_OCK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_SHIFT)) & ENETC_PF_TMR_TMR_PRSC_PRSC_OCK_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_PRSC */ #define ENETC_PF_TMR_TMR_PRSC_COUNT (1U) /*! @name TMR_ECTRL - Extended Timer Control */ /*! @{ */ #define ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_MASK (0xFU) #define ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_SHIFT (0U) /*! ETFF_THR - External trigger FIFO threshold. */ #define ENETC_PF_TMR_TMR_ECTRL_ETFF_THR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_SHIFT)) & ENETC_PF_TMR_TMR_ECTRL_ETFF_THR_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ECTRL */ #define ENETC_PF_TMR_TMR_ECTRL_COUNT (1U) /*! @name TMROFF_L - Timer Offset Low */ /*! @{ */ #define ENETC_PF_TMR_TMROFF_L_TMROFF_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMROFF_L_TMROFF_L_SHIFT (0U) /*! TMROFF_L - Offset value of the clock counter. */ #define ENETC_PF_TMR_TMROFF_L_TMROFF_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMROFF_L_TMROFF_L_SHIFT)) & ENETC_PF_TMR_TMROFF_L_TMROFF_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMROFF_L */ #define ENETC_PF_TMR_TMROFF_L_COUNT (1U) /*! @name TMROFF_H - Timer Offset High */ /*! @{ */ #define ENETC_PF_TMR_TMROFF_H_TMROFF_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMROFF_H_TMROFF_H_SHIFT (0U) /*! TMROFF_H - Offset value of the clock counter. */ #define ENETC_PF_TMR_TMROFF_H_TMROFF_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMROFF_H_TMROFF_H_SHIFT)) & ENETC_PF_TMR_TMROFF_H_TMROFF_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMROFF_H */ #define ENETC_PF_TMR_TMROFF_H_COUNT (1U) /*! @name TMR_ALARM_L - Alarm Time Comparator Low */ /*! @{ */ #define ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_SHIFT (0U) /*! ALARM_L - Alarm time comparator register. */ #define ENETC_PF_TMR_TMR_ALARM_L_ALARM_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_L_ALARM_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ALARM_L */ #define ENETC_PF_TMR_TMR_ALARM_L_COUNT (1U) /* The count of ENETC_PF_TMR_TMR_ALARM_L */ #define ENETC_PF_TMR_TMR_ALARM_L_COUNT2 (2U) /*! @name TMR_ALARM_H - Alarm Time Comparator High */ /*! @{ */ #define ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_SHIFT (0U) /*! ALARM_H - Alarm time comparator register. */ #define ENETC_PF_TMR_TMR_ALARM_H_ALARM_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_H_ALARM_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ALARM_H */ #define ENETC_PF_TMR_TMR_ALARM_H_COUNT (1U) /* The count of ENETC_PF_TMR_TMR_ALARM_H */ #define ENETC_PF_TMR_TMR_ALARM_H_COUNT2 (2U) /*! @name TMR_ALARM_CTRL - Timer Alarm Control */ /*! @{ */ #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_MASK (0x1FU) #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_SHIFT (0U) /*! ALARM1_PW - ALARM 1 pulse width selector */ #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM1_PW_MASK) #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_MASK (0x80U) #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_SHIFT (7U) /*! PG1 - Alarm1 pulse generation time */ #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_PG1_MASK) #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_MASK (0x1F00U) #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_SHIFT (8U) /*! ALARM2_PW - ALARM 2 pulse width selector */ #define ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_ALARM2_PW_MASK) #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_MASK (0x8000U) #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_SHIFT (15U) /*! PG2 - Alarm2 pulse generation time */ #define ENETC_PF_TMR_TMR_ALARM_CTRL_PG2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_SHIFT)) & ENETC_PF_TMR_TMR_ALARM_CTRL_PG2_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ALARM_CTRL */ #define ENETC_PF_TMR_TMR_ALARM_CTRL_COUNT (1U) /*! @name TMR_FIPER - Timer Fixed Interval Period */ /*! @{ */ #define ENETC_PF_TMR_TMR_FIPER_FIPER_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_FIPER_FIPER_SHIFT (0U) /*! FIPER - Fixed Interval Pulse Period */ #define ENETC_PF_TMR_TMR_FIPER_FIPER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_FIPER_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_FIPER_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_FIPER */ #define ENETC_PF_TMR_TMR_FIPER_COUNT (1U) /* The count of ENETC_PF_TMR_TMR_FIPER */ #define ENETC_PF_TMR_TMR_FIPER_COUNT2 (3U) /*! @name TMR_FIPER_CTRL - Timer FIPER Control */ /*! @{ */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_MASK (0x1FU) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_SHIFT (0U) /*! FIPER1_PW - FIPER 1 pulse width selection */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_PW_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_MASK (0x40U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_SHIFT (6U) /*! PG1 - FIPER1 pulse generation select */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_PG1_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_MASK (0x80U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_SHIFT (7U) /*! FIPER1_DIS - FIPER1 disable */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER1_DIS_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_MASK (0x1F00U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_SHIFT (8U) /*! FIPER2_PW - FIPER 2 pulse width selection */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_PW_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_MASK (0x4000U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_SHIFT (14U) /*! PG2 - FIPER2 pulse generation time */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_PG2_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_MASK (0x8000U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_SHIFT (15U) /*! FIPER2_DIS - FIPER2 disable */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER2_DIS_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_MASK (0x1F0000U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_SHIFT (16U) /*! FIPER3_PW - FIPER 3 Pulse Width Selection */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_PW_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_MASK (0x400000U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_SHIFT (22U) /*! PG3 - FIPER3 pulse generation time */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_PG3(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_PG3_MASK) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_MASK (0x800000U) #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_SHIFT (23U) /*! FIPER3_DIS - FIPER3 disable */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_SHIFT)) & ENETC_PF_TMR_TMR_FIPER_CTRL_FIPER3_DIS_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_FIPER_CTRL */ #define ENETC_PF_TMR_TMR_FIPER_CTRL_COUNT (1U) /*! @name TMR_ETTS_L - External Trigger Stamp */ /*! @{ */ #define ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_SHIFT (0U) #define ENETC_PF_TMR_TMR_ETTS_L_ETTS_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_SHIFT)) & ENETC_PF_TMR_TMR_ETTS_L_ETTS_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ETTS_L */ #define ENETC_PF_TMR_TMR_ETTS_L_COUNT (1U) /* The count of ENETC_PF_TMR_TMR_ETTS_L */ #define ENETC_PF_TMR_TMR_ETTS_L_COUNT2 (2U) /*! @name TMR_ETTS_H - External Trigger Stamp */ /*! @{ */ #define ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_SHIFT (0U) #define ENETC_PF_TMR_TMR_ETTS_H_ETTS_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_SHIFT)) & ENETC_PF_TMR_TMR_ETTS_H_ETTS_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_ETTS_H */ #define ENETC_PF_TMR_TMR_ETTS_H_COUNT (1U) /* The count of ENETC_PF_TMR_TMR_ETTS_H */ #define ENETC_PF_TMR_TMR_ETTS_H_COUNT2 (2U) /*! @name TMR_CUR_TIME_L - Timer Current Time Low */ /*! @{ */ #define ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_SHIFT (0U) #define ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_SHIFT)) & ENETC_PF_TMR_TMR_CUR_TIME_L_TMR_CUR_TIME_L_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_CUR_TIME_L */ #define ENETC_PF_TMR_TMR_CUR_TIME_L_COUNT (1U) /*! @name TMR_CUR_TIME_H - Timer Current Time High */ /*! @{ */ #define ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_MASK (0xFFFFFFFFU) #define ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_SHIFT (0U) #define ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_SHIFT)) & ENETC_PF_TMR_TMR_CUR_TIME_H_TMR_CUR_TIME_H_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_CUR_TIME_H */ #define ENETC_PF_TMR_TMR_CUR_TIME_H_COUNT (1U) /*! @name TMR_PARAM - Timer Parameter */ /*! @{ */ #define ENETC_PF_TMR_TMR_PARAM_SYNC_MASK (0x1U) #define ENETC_PF_TMR_TMR_PARAM_SYNC_SHIFT (0U) /*! SYNC - Timer synchronization * 0b0..Timer is not synchronized with grandmaster * 0b1..Timer is synchronized with grandmaster */ #define ENETC_PF_TMR_TMR_PARAM_SYNC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_PARAM_SYNC_SHIFT)) & ENETC_PF_TMR_TMR_PARAM_SYNC_MASK) #define ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_MASK (0xFFFFFFFEU) #define ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_SHIFT (1U) /*! PARAM_VAL - User specific parameter values */ #define ENETC_PF_TMR_TMR_PARAM_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_SHIFT)) & ENETC_PF_TMR_TMR_PARAM_PARAM_VAL_MASK) /*! @} */ /* The count of ENETC_PF_TMR_TMR_PARAM */ #define ENETC_PF_TMR_TMR_PARAM_COUNT (1U) /*! * @} */ /* end of group ENETC_PF_TMR_Register_Masks */ /* ENETC_PF_TMR - Peripheral instance base addresses */ /** Peripheral TMR0_BASE base address */ #define TMR0_BASE_BASE (0x4CCC0000u) /** Peripheral TMR0_BASE base pointer */ #define TMR0_BASE ((ENETC_PF_TMR_Type *)TMR0_BASE_BASE) /** Array initializer of ENETC_PF_TMR peripheral base addresses */ #define ENETC_PF_TMR_BASE_ADDRS { TMR0_BASE_BASE } /** Array initializer of ENETC_PF_TMR peripheral base pointers */ #define ENETC_PF_TMR_BASE_PTRS { TMR0_BASE } /*! * @} */ /* end of group ENETC_PF_TMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENETC_SI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_SI_Peripheral_Access_Layer ENETC_SI Peripheral Access Layer * @{ */ /** ENETC_SI - Register Layout Typedef */ typedef struct { __IO uint32_t SIMR; /**< Station interface mode register, offset: 0x0 */ __I uint32_t SISR; /**< Station interface status register, offset: 0x4 */ uint8_t RESERVED_0[16]; __I uint32_t SICTR[2]; /**< Station interface current time register 0..Station interface current time register 1, array offset: 0x18, array step: 0x4 */ __I uint32_t SIPCAPR0; /**< Station interface port capability register 0, offset: 0x20 */ __I uint32_t SIPCAPR1; /**< Station interface port capability register 1, offset: 0x24 */ uint8_t RESERVED_1[8]; __I uint32_t SITSR; /**< Station interface timer status register, offset: 0x30 */ uint8_t RESERVED_2[4]; __IO uint32_t SIRBGCR; /**< Station interface receive BDR group control register, offset: 0x38 */ uint8_t RESERVED_3[4]; __IO uint32_t SIBCAR; /**< Station interface buffer cache attribute register, offset: 0x40 */ __IO uint32_t SIMCAR; /**< Station interface message cache attribute register, offset: 0x44, not available in all instances (available on 18 out of 54) */ __IO uint32_t SICCAR; /**< Station interface command cache attribute register, offset: 0x48 */ uint8_t RESERVED_4[52]; __I uint32_t SIPMAR0; /**< Station interface primary MAC address register 0, offset: 0x80 */ __I uint32_t SIPMAR1; /**< Station interface primary MAC address register 1, offset: 0x84 */ uint8_t RESERVED_5[8]; __I uint32_t SICVLANR1; /**< Station interface custom VLAN register 1, offset: 0x90 */ __I uint32_t SICVLANR2; /**< Station interface custom VLAN register 2, offset: 0x94 */ uint8_t RESERVED_6[104]; __IO uint32_t SIVLANIPVMR0; /**< Station interface VLAN to IPV mapping register 0, offset: 0x100 */ __IO uint32_t SIVLANIPVMR1; /**< Station interface VLAN to IPV mapping register 1, offset: 0x104 */ uint8_t RESERVED_7[72]; __IO uint32_t SIIPVBDRMR0; /**< Station interface IPV to ring mapping register, offset: 0x150 */ uint8_t RESERVED_8[176]; union { /* offset: 0x204 */ struct { /* offset: 0x204 */ __IO uint32_t PSIMSGRR; /**< Physical station interface message receive register, offset: 0x204, not available in all instances (available on 18 out of 54) */ __IO uint32_t PSIMSGSR; /**< Physical station interface message send register, offset: 0x208, not available in all instances (available on 18 out of 54) */ uint8_t RESERVED_0[4]; struct { /* offset: 0x210, array step: 0x8 */ __IO uint32_t PSIVMSGRCVAR0; /**< PSI VSI 1 message receive address register 0..PSI VSI 2 message receive address register 0, array offset: 0x210, array step: 0x8, not available in all instances (available on 18 out of 54) */ __IO uint32_t PSIVMSGRCVAR1; /**< PSI VSI 1 message receive address register 1..PSI VSI 2 message receive address register 1, array offset: 0x214, array step: 0x8, not available in all instances (available on 18 out of 54) */ } VSI_NUM[2]; } PSI_A; struct { /* offset: 0x204 */ __I uint32_t VSIMSGSR; /**< Virtual station interface message send register, offset: 0x204, not available in all instances (available on 36 out of 54) */ __I uint32_t VSIMSGRR; /**< Virtual station interface message receive register, offset: 0x208, not available in all instances (available on 36 out of 54) */ uint8_t RESERVED_0[4]; __IO uint32_t VSIMSGSNDAR0; /**< Virtual station interface message address send register 0, offset: 0x210, not available in all instances (available on 36 out of 54) */ __IO uint32_t VSIMSGSNDAR1; /**< Virtual station interface message send address register 1, offset: 0x214, not available in all instances (available on 36 out of 54) */ } VSI_A; }; uint8_t RESERVED_9[224]; __I uint32_t SIROCT0; /**< Station interface receive octets counter (ifInOctets) 0, offset: 0x300 */ __I uint32_t SIROCT1; /**< Station interface receive octets counter (ifInOctets) 1, offset: 0x304 */ __I uint32_t SIRFRM0; /**< Station interface receive frame counter (aFrameReceivedOK) 0, offset: 0x308 */ __I uint32_t SIRFRM1; /**< Station interface receive frame counter (aFrameReceivedOK) 1, offset: 0x30C */ __I uint32_t SIRUCA0; /**< Station interface receive unicast frame counter (ifInUcastPkts) 0, offset: 0x310 */ __I uint32_t SIRUCA1; /**< Station interface receive unicast frame counter (ifInUcastPkts) 1, offset: 0x314 */ __I uint32_t SIRMCA0; /**< Station interface receive multicast frame counter (ifInMulticastPkts) 0, offset: 0x318 */ __I uint32_t SIRMCA1; /**< Station interface receive multicast frame counter (ifInMulticastPkts) 1, offset: 0x31C */ __I uint32_t SITOCT0; /**< Station interface transmit octets counter (ifOutOctets) 0, offset: 0x320 */ __I uint32_t SITOCT1; /**< Station interface transmit octets counter (ifOutOctets) 1, offset: 0x324 */ __I uint32_t SITFRM0; /**< Station interface transmit frame counter (aFrameTransmittedOK) 0, offset: 0x328 */ __I uint32_t SITFRM1; /**< Station interface transmit frame counter (aFrameTransmittedOK) 1, offset: 0x32C */ __I uint32_t SITUCA0; /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 0, offset: 0x330 */ __I uint32_t SITUCA1; /**< Station interface transmit unicast frame counter (ifOutUcastPkts) 1, offset: 0x334 */ __I uint32_t SITMCA0; /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 0, offset: 0x338 */ __I uint32_t SITMCA1; /**< Station interface transmit multicast frame counter (ifOutMulticastPkts) 1, offset: 0x33C */ __I uint32_t SITDFCR; /**< Station interface transmit discard frame counter, offset: 0x340 */ uint8_t RESERVED_10[172]; __I uint32_t SIBLPR[2]; /**< Station interface boot loader parameter register 0..Station interface boot loader parameter register 1, array offset: 0x3F0, array step: 0x4, not available in all instances (available on 36 out of 54) */ uint8_t RESERVED_11[1032]; __IO uint32_t SICBDRMR; /**< Station interface command BDR mode register, offset: 0x800 */ __I uint32_t SICBDRSR; /**< Station interface command BDR status register, offset: 0x804 */ uint8_t RESERVED_12[8]; __IO uint32_t SICBDRBAR0; /**< Station interface command BDR base address register 0, offset: 0x810 */ __IO uint32_t SICBDRBAR1; /**< Station interface command BDR base address register 1, offset: 0x814 */ __IO uint32_t SICBDRPIR; /**< Station interface command BDR producer index register, offset: 0x818 */ __IO uint32_t SICBDRCIR; /**< Station interface command BDR consumer index register, offset: 0x81C */ __IO uint32_t SICBDRLENR; /**< Station interface command BDR length register, offset: 0x820 */ uint8_t RESERVED_13[124]; __IO uint32_t SICBDRIER; /**< Station interface command BDR interrupt enable register, offset: 0x8A0 */ __IO uint32_t SICBDRIDR; /**< Station interface command BDR interrupt detect register, offset: 0x8A4 */ uint8_t RESERVED_14[88]; __I uint32_t SICAPR0; /**< Station interface capability register 0, offset: 0x900 */ __I uint32_t SICAPR1; /**< Station interface capability register 1, offset: 0x904 */ __I uint32_t SICAPR2; /**< Station interface capability register 2, offset: 0x908 */ uint8_t RESERVED_15[244]; union { /* offset: 0xA00 */ struct { /* offset: 0xA00 */ __IO uint32_t PSIIER; /**< Physical station interface interrupt enable register, offset: 0xA00, not available in all instances (available on 18 out of 54) */ uint8_t RESERVED_0[4]; __IO uint32_t PSIIDR; /**< Physical station interface interrupt detect register, offset: 0xA08, not available in all instances (available on 18 out of 54) */ } PSI; struct { /* offset: 0xA00 */ __IO uint32_t VSIIER; /**< Virtual station interface interrupt enable register, offset: 0xA00, not available in all instances (available on 36 out of 54) */ uint8_t RESERVED_0[4]; __IO uint32_t VSIIDR; /**< Virtual station interface interrupt detect register, offset: 0xA08, not available in all instances (available on 36 out of 54) */ } VSI; }; uint8_t RESERVED_16[12]; __IO uint32_t SITXIDR0; /**< Station interface transmit interrupt detect register 0, offset: 0xA18 */ __IO uint32_t SITXIDR1; /**< Station interface transmit interrupt detect register 1, offset: 0xA1C */ uint8_t RESERVED_17[8]; __IO uint32_t SIRXIDR0; /**< Station interface receive interrupt detect register 0, offset: 0xA28 */ uint8_t RESERVED_18[4]; __IO uint32_t SIMSIVR; /**< Station interface MSI-X vector register, offset: 0xA30 */ __IO uint32_t SICMSIVR; /**< Station interface command MSI-X vector register, offset: 0xA34 */ uint8_t RESERVED_19[8]; __IO uint32_t SITMRIER; /**< Station interface timer interrupt enable register, offset: 0xA40 */ __IO uint32_t SITMRIDR; /**< Station interface timer interrupt detect register, offset: 0xA44 */ uint8_t RESERVED_20[4]; __IO uint32_t SITMRMSIVR; /**< Station interface timer MSI-X vector register, offset: 0xA4C */ uint8_t RESERVED_21[176]; __IO uint32_t SIMSITRVR[8]; /**< Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 7 vector register, array offset: 0xB00, array step: 0x4 */ uint8_t RESERVED_22[96]; __IO uint32_t SIMSIRRVR[8]; /**< Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 7 vector register, array offset: 0xB80, array step: 0x4 */ uint8_t RESERVED_23[608]; __IO uint32_t SICMECR; /**< Station interface correctable memory error configuration register, offset: 0xE00 */ __IO uint32_t SICMESR; /**< Station interface correctable memory error status register, offset: 0xE04 */ uint8_t RESERVED_24[4]; __I uint32_t SICMECTR; /**< Station interface correctable memory error count register, offset: 0xE0C */ __IO uint32_t SIUPECR; /**< Station interface uncorrectable programming error configuration register, offset: 0xE10 */ __IO uint32_t SIUPESR; /**< Station interface uncorrectable programming error status register, offset: 0xE14 */ uint8_t RESERVED_25[4]; __I uint32_t SIUPECTR; /**< Station interface uncorrectable programming error count register, offset: 0xE1C */ __IO uint32_t SIUNSBECR; /**< Station interface uncorrectable non-fatal system bus error configuration register, offset: 0xE20 */ __IO uint32_t SIUNSBESR; /**< Station interface uncorrectable non-fatal system bus error status register, offset: 0xE24 */ uint8_t RESERVED_26[4]; __I uint32_t SIUNSBECTR; /**< Station interface uncorrectable non-fatal system bus error count register, offset: 0xE2C */ __IO uint32_t SIUFSBECR; /**< Station interface uncorrectable fatal system bus error configuration register, offset: 0xE30 */ __IO uint32_t SIUFSBESR; /**< Station interface uncorrectable fatal system bus error status register, offset: 0xE34 */ uint8_t RESERVED_27[8]; __IO uint32_t SIUNMECR; /**< Station interface uncorrectable non-fatal memory error configuration register, offset: 0xE40 */ __IO uint32_t SIUNMESR0; /**< Station interface uncorrectable non-fatal memory error status register 0, offset: 0xE44 */ __I uint32_t SIUNMESR1; /**< Station interface uncorrectable non-fatal memory error status register 1, offset: 0xE48 */ __I uint32_t SIUNMECTR; /**< Station interface uncorrectable non-fatal memory error count register, offset: 0xE4C */ __IO uint32_t SIUFMECR; /**< Station interface uncorrectable fatal memory error configuration register, offset: 0xE50 */ __IO uint32_t SIUFMESR0; /**< Station interface uncorrectable fatal memory error status register 0, offset: 0xE54 */ __I uint32_t SIUFMESR1; /**< Station interface uncorrectable fatal memory error status register 1, offset: 0xE58 */ uint8_t RESERVED_28[420]; __I uint32_t SIMAFTCAPR; /**< Station interface MAC address filter table capability register, offset: 0x1000 */ uint8_t RESERVED_29[252]; __I uint32_t SIVFTCAPR; /**< Station interface VLAN filter table capability register, offset: 0x1100 */ uint8_t RESERVED_30[508]; __IO uint32_t SILSOSFMR0; /**< Station interface LSO segmentation flag mask register 0, offset: 0x1300 */ __IO uint32_t SILSOSFMR1; /**< Station interface LSO segmentation flag mask register 1, offset: 0x1304 */ uint8_t RESERVED_31[760]; __I uint32_t SIRSSCAPR; /**< Station interface RSS capability register, offset: 0x1600 */ uint8_t RESERVED_32[27132]; struct { /* offset: 0x8000, array step: 0x200 */ __IO uint32_t TBMR; /**< Tx BDR 0 mode register..Tx BDR 7 mode register, array offset: 0x8000, array step: 0x200 */ __IO uint32_t TBSR; /**< Tx BDR 0 status register..Tx BDR 7 status register, array offset: 0x8004, array step: 0x200 */ uint8_t RESERVED_0[8]; __IO uint32_t TBBAR0; /**< Tx BDR 0 base address register 0..Tx BDR 7 base address register 0, array offset: 0x8010, array step: 0x200 */ __IO uint32_t TBBAR1; /**< Tx BDR 0 base address register 1..Tx BDR 7 base address register 1, array offset: 0x8014, array step: 0x200 */ __IO uint32_t TBPIR; /**< Tx BDR 0 producer index register..Tx BDR 7 producer index register, array offset: 0x8018, array step: 0x200 */ __IO uint32_t TBCIR; /**< Tx BDR 0 consumer index register..Tx BDR 7 consumer index register, array offset: 0x801C, array step: 0x200 */ __IO uint32_t TBLENR; /**< Tx BDR 0 length register..Tx BDR 7 length register, array offset: 0x8020, array step: 0x200 */ uint8_t RESERVED_1[124]; __IO uint32_t TBIER; /**< Tx BDR 0 interrupt enable register..Tx BDR 7 interrupt enable register, array offset: 0x80A0, array step: 0x200 */ __I uint32_t TBIDR; /**< Tx BDR 0 interrupt detect register..Tx BDR 7 interrupt detect register, array offset: 0x80A4, array step: 0x200 */ __IO uint32_t TBICR0; /**< Tx BDR 0 interrupt coalescing register 0..Tx BDR 7 interrupt coalescing register 0, array offset: 0x80A8, array step: 0x200 */ __IO uint32_t TBICR1; /**< Tx BDR 0 interrupt coalescing register 1..Tx BDR 7 interrupt coalescing register 1, array offset: 0x80AC, array step: 0x200 */ uint8_t RESERVED_2[80]; __IO uint32_t RBMR; /**< Rx BDR 0 mode register..Rx BDR 7 mode register, array offset: 0x8100, array step: 0x200 */ __IO uint32_t RBSR; /**< Rx BDR 0 status register..Rx BDR 7 status register, array offset: 0x8104, array step: 0x200 */ __IO uint32_t RBBSR; /**< Rx BDR 0 buffer size register..Rx BDR 7 buffer size register, array offset: 0x8108, array step: 0x200 */ __IO uint32_t RBCIR; /**< Rx BDR 0 consumer index register..Rx BDR 7 consumer index register, array offset: 0x810C, array step: 0x200 */ __IO uint32_t RBBAR0; /**< Rx BDR 0 base address register 0..Rx BDR 7 base address register 0, array offset: 0x8110, array step: 0x200 */ __IO uint32_t RBBAR1; /**< Rx BDR 0 base address register 1..Rx BDR 7 base address register 1, array offset: 0x8114, array step: 0x200 */ __IO uint32_t RBPIR; /**< Rx BDR 0 producer index register..Rx BDR 7 producer index register, array offset: 0x8118, array step: 0x200 */ uint8_t RESERVED_3[4]; __IO uint32_t RBLENR; /**< Rx BDR 0 length register..Rx BDR 7 length register, array offset: 0x8120, array step: 0x200 */ uint8_t RESERVED_4[12]; __IO uint32_t RBRSCR; /**< Rx BDR 0 RSC register..Rx BDR 7 RSC register, array offset: 0x8130, array step: 0x200 */ uint8_t RESERVED_5[76]; __I uint32_t RBDCR; /**< Rx BDR 0 drop count register..Rx BDR 7 drop count register, array offset: 0x8180, array step: 0x200 */ uint8_t RESERVED_6[28]; __IO uint32_t RBIER; /**< Rx BDR 0 interrupt enable register..Rx BDR 7 interrupt enable register, array offset: 0x81A0, array step: 0x200 */ __I uint32_t RBIDR; /**< Rx BDR 0 interrupt detect register..Rx BDR 7 interrupt detect register, array offset: 0x81A4, array step: 0x200 */ __IO uint32_t RBICR0; /**< Rx BDR 0 interrupt coalescing register 0..Rx BDR 7 interrupt coalescing register 0, array offset: 0x81A8, array step: 0x200 */ __IO uint32_t RBICR1; /**< Rx BDR 0 interrupt coalescing register 1..Rx BDR 7 interrupt coalescing register 1, array offset: 0x81AC, array step: 0x200 */ uint8_t RESERVED_7[80]; } BDR[8]; } ENETC_SI_Type; /* ---------------------------------------------------------------------------- -- ENETC_SI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_SI_Register_Masks ENETC_SI Register Masks * @{ */ /*! @name SIMR - Station interface mode register */ /*! @{ */ #define ENETC_SI_SIMR_RSSE_MASK (0x1U) #define ENETC_SI_SIMR_RSSE_SHIFT (0U) /*! RSSE - RSS classification enable * 0b0..RSS classification is disabled * 0b1..RSS classification is enabled */ #define ENETC_SI_SIMR_RSSE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RSSE_SHIFT)) & ENETC_SI_SIMR_RSSE_MASK) #define ENETC_SI_SIMR_RNUM_MASK (0x2U) #define ENETC_SI_SIMR_RNUM_SHIFT (1U) /*! RNUM - Receive no unicast mode * 0b0..Disabled * 0b1..Enabled */ #define ENETC_SI_SIMR_RNUM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RNUM_SHIFT)) & ENETC_SI_SIMR_RNUM_MASK) #define ENETC_SI_SIMR_RNMM_MASK (0x4U) #define ENETC_SI_SIMR_RNMM_SHIFT (2U) /*! RNMM - Receive no multicast mode * 0b0..Disabled * 0b1..Enabled */ #define ENETC_SI_SIMR_RNMM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RNMM_SHIFT)) & ENETC_SI_SIMR_RNMM_MASK) #define ENETC_SI_SIMR_RNBM_MASK (0x8U) #define ENETC_SI_SIMR_RNBM_SHIFT (3U) /*! RNBM - Receive no broadcast mode * 0b0..Disabled * 0b1..Enabled */ #define ENETC_SI_SIMR_RNBM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_RNBM_SHIFT)) & ENETC_SI_SIMR_RNBM_MASK) #define ENETC_SI_SIMR_V2IPVE_MASK (0x10U) #define ENETC_SI_SIMR_V2IPVE_SHIFT (4U) /*! V2IPVE - VLAN to IPV mapping enable * 0b0..Disabled. Default IPV is selected from PQOSMR[DIPV]. * 0b1..Enabled */ #define ENETC_SI_SIMR_V2IPVE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_V2IPVE_SHIFT)) & ENETC_SI_SIMR_V2IPVE_MASK) #define ENETC_SI_SIMR_DEFAULT_RX_GROUP_MASK (0x70000U) #define ENETC_SI_SIMR_DEFAULT_RX_GROUP_SHIFT (16U) #define ENETC_SI_SIMR_DEFAULT_RX_GROUP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_DEFAULT_RX_GROUP_SHIFT)) & ENETC_SI_SIMR_DEFAULT_RX_GROUP_MASK) #define ENETC_SI_SIMR_EN_MASK (0x80000000U) #define ENETC_SI_SIMR_EN_SHIFT (31U) /*! EN - Enable station interface. * 0b0..Station interface is disabled. * 0b1..Station interface is enabled. */ #define ENETC_SI_SIMR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMR_EN_SHIFT)) & ENETC_SI_SIMR_EN_MASK) /*! @} */ /*! @name SISR - Station interface status register */ /*! @{ */ #define ENETC_SI_SISR_TX_BUSY_MASK (0x1U) #define ENETC_SI_SISR_TX_BUSY_SHIFT (0U) #define ENETC_SI_SISR_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_TX_BUSY_SHIFT)) & ENETC_SI_SISR_TX_BUSY_MASK) #define ENETC_SI_SISR_MAC_UP_MASK (0x2U) #define ENETC_SI_SISR_MAC_UP_SHIFT (1U) #define ENETC_SI_SISR_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_MAC_UP_SHIFT)) & ENETC_SI_SISR_MAC_UP_MASK) #define ENETC_SI_SISR_MAC_MP_MASK (0x4U) #define ENETC_SI_SISR_MAC_MP_SHIFT (2U) #define ENETC_SI_SISR_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_MAC_MP_SHIFT)) & ENETC_SI_SISR_MAC_MP_MASK) #define ENETC_SI_SISR_VLAN_P_MASK (0x8U) #define ENETC_SI_SISR_VLAN_P_SHIFT (3U) #define ENETC_SI_SISR_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_VLAN_P_SHIFT)) & ENETC_SI_SISR_VLAN_P_MASK) #define ENETC_SI_SISR_VLAN_UTA_MASK (0x10U) #define ENETC_SI_SISR_VLAN_UTA_SHIFT (4U) #define ENETC_SI_SISR_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SISR_VLAN_UTA_SHIFT)) & ENETC_SI_SISR_VLAN_UTA_MASK) /*! @} */ /*! @name SICTR - Station interface current time register 0..Station interface current time register 1 */ /*! @{ */ #define ENETC_SI_SICTR_CURR_TIME_MASK (0xFFFFFFFFU) #define ENETC_SI_SICTR_CURR_TIME_SHIFT (0U) #define ENETC_SI_SICTR_CURR_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICTR_CURR_TIME_SHIFT)) & ENETC_SI_SICTR_CURR_TIME_MASK) /*! @} */ /* The count of ENETC_SI_SICTR */ #define ENETC_SI_SICTR_COUNT (2U) /*! @name SIPCAPR0 - Station interface port capability register 0 */ /*! @{ */ #define ENETC_SI_SIPCAPR0_RSC_MASK (0x1U) #define ENETC_SI_SIPCAPR0_RSC_SHIFT (0U) /*! RSC * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_RSC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_RSC_SHIFT)) & ENETC_SI_SIPCAPR0_RSC_MASK) #define ENETC_SI_SIPCAPR0_LSO_MASK (0x2U) #define ENETC_SI_SIPCAPR0_LSO_SHIFT (1U) /*! LSO * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_LSO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_LSO_SHIFT)) & ENETC_SI_SIPCAPR0_LSO_MASK) #define ENETC_SI_SIPCAPR0_RFS_MASK (0x4U) #define ENETC_SI_SIPCAPR0_RFS_SHIFT (2U) /*! RFS * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_RFS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_RFS_SHIFT)) & ENETC_SI_SIPCAPR0_RFS_MASK) #define ENETC_SI_SIPCAPR0_FP_MASK (0x8U) #define ENETC_SI_SIPCAPR0_FP_SHIFT (3U) /*! FP * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_FP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_FP_SHIFT)) & ENETC_SI_SIPCAPR0_FP_MASK) #define ENETC_SI_SIPCAPR0_TGS_MASK (0x10U) #define ENETC_SI_SIPCAPR0_TGS_SHIFT (4U) /*! TGS * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_TGS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_TGS_SHIFT)) & ENETC_SI_SIPCAPR0_TGS_MASK) #define ENETC_SI_SIPCAPR0_TSD_MASK (0x20U) #define ENETC_SI_SIPCAPR0_TSD_SHIFT (5U) /*! TSD * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_TSD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_TSD_SHIFT)) & ENETC_SI_SIPCAPR0_TSD_MASK) #define ENETC_SI_SIPCAPR0_CBS_MASK (0x40U) #define ENETC_SI_SIPCAPR0_CBS_SHIFT (6U) /*! CBS * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_CBS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_CBS_SHIFT)) & ENETC_SI_SIPCAPR0_CBS_MASK) #define ENETC_SI_SIPCAPR0_RSS_MASK (0x100U) #define ENETC_SI_SIPCAPR0_RSS_SHIFT (8U) /*! RSS * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_RSS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_RSS_SHIFT)) & ENETC_SI_SIPCAPR0_RSS_MASK) #define ENETC_SI_SIPCAPR0_PSFP_MASK (0x200U) #define ENETC_SI_SIPCAPR0_PSFP_SHIFT (9U) /*! PSFP * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_PSFP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_PSFP_SHIFT)) & ENETC_SI_SIPCAPR0_PSFP_MASK) #define ENETC_SI_SIPCAPR0_IPFLT_MASK (0x400U) #define ENETC_SI_SIPCAPR0_IPFLT_SHIFT (10U) /*! IPFLT * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_IPFLT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_IPFLT_SHIFT)) & ENETC_SI_SIPCAPR0_IPFLT_MASK) #define ENETC_SI_SIPCAPR0_RP_MASK (0x800U) #define ENETC_SI_SIPCAPR0_RP_SHIFT (11U) /*! RP * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_RP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_RP_SHIFT)) & ENETC_SI_SIPCAPR0_RP_MASK) #define ENETC_SI_SIPCAPR0_WO_MASK (0x2000U) #define ENETC_SI_SIPCAPR0_WO_SHIFT (13U) /*! WO * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_WO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_WO_SHIFT)) & ENETC_SI_SIPCAPR0_WO_MASK) #define ENETC_SI_SIPCAPR0_FS_MASK (0x10000U) #define ENETC_SI_SIPCAPR0_FS_SHIFT (16U) /*! FS - Functional Safety (FS) supported. * 0b0..Not supported * 0b1..Supported */ #define ENETC_SI_SIPCAPR0_FS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR0_FS_SHIFT)) & ENETC_SI_SIPCAPR0_FS_MASK) /*! @} */ /*! @name SIPCAPR1 - Station interface port capability register 1 */ /*! @{ */ #define ENETC_SI_SIPCAPR1_NUM_TCS_MASK (0x70U) #define ENETC_SI_SIPCAPR1_NUM_TCS_SHIFT (4U) #define ENETC_SI_SIPCAPR1_NUM_TCS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_TCS_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_TCS_MASK) #define ENETC_SI_SIPCAPR1_NUM_MCH_MASK (0x300U) #define ENETC_SI_SIPCAPR1_NUM_MCH_SHIFT (8U) #define ENETC_SI_SIPCAPR1_NUM_MCH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_MCH_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_MCH_MASK) #define ENETC_SI_SIPCAPR1_NUM_UCH_MASK (0xC00U) #define ENETC_SI_SIPCAPR1_NUM_UCH_SHIFT (10U) #define ENETC_SI_SIPCAPR1_NUM_UCH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_UCH_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_UCH_MASK) #define ENETC_SI_SIPCAPR1_NUM_MSIX_MASK (0x3F000U) #define ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT (12U) #define ENETC_SI_SIPCAPR1_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_MSIX_MASK) #define ENETC_SI_SIPCAPR1_NUM_IPV_MASK (0x80000000U) #define ENETC_SI_SIPCAPR1_NUM_IPV_SHIFT (31U) #define ENETC_SI_SIPCAPR1_NUM_IPV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPCAPR1_NUM_IPV_SHIFT)) & ENETC_SI_SIPCAPR1_NUM_IPV_MASK) /*! @} */ /*! @name SITSR - Station interface timer status register */ /*! @{ */ #define ENETC_SI_SITSR_SYNC_MASK (0x1U) #define ENETC_SI_SITSR_SYNC_SHIFT (0U) /*! SYNC - Timer synchronization */ #define ENETC_SI_SITSR_SYNC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITSR_SYNC_SHIFT)) & ENETC_SI_SITSR_SYNC_MASK) #define ENETC_SI_SITSR_PARAM_VAL_MASK (0xFFFFFFFEU) #define ENETC_SI_SITSR_PARAM_VAL_SHIFT (1U) /*! PARAM_VAL - User specific parameter values */ #define ENETC_SI_SITSR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITSR_PARAM_VAL_SHIFT)) & ENETC_SI_SITSR_PARAM_VAL_MASK) /*! @} */ /*! @name SIRBGCR - Station interface receive BDR group control register */ /*! @{ */ #define ENETC_SI_SIRBGCR_NUM_GROUPS_MASK (0x7U) #define ENETC_SI_SIRBGCR_NUM_GROUPS_SHIFT (0U) /*! NUM_GROUPS - Number of groups */ #define ENETC_SI_SIRBGCR_NUM_GROUPS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRBGCR_NUM_GROUPS_SHIFT)) & ENETC_SI_SIRBGCR_NUM_GROUPS_MASK) #define ENETC_SI_SIRBGCR_RINGS_PER_GROUP_MASK (0x70000U) #define ENETC_SI_SIRBGCR_RINGS_PER_GROUP_SHIFT (16U) /*! RINGS_PER_GROUP - Number of rings per group */ #define ENETC_SI_SIRBGCR_RINGS_PER_GROUP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRBGCR_RINGS_PER_GROUP_SHIFT)) & ENETC_SI_SIRBGCR_RINGS_PER_GROUP_MASK) /*! @} */ /*! @name SIBCAR - Station interface buffer cache attribute register */ /*! @{ */ #define ENETC_SI_SIBCAR_BD_WRCACHE_MASK (0xFU) #define ENETC_SI_SIBCAR_BD_WRCACHE_SHIFT (0U) #define ENETC_SI_SIBCAR_BD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_WRCACHE_SHIFT)) & ENETC_SI_SIBCAR_BD_WRCACHE_MASK) #define ENETC_SI_SIBCAR_BD_WRDOMAIN_MASK (0x30U) #define ENETC_SI_SIBCAR_BD_WRDOMAIN_SHIFT (4U) #define ENETC_SI_SIBCAR_BD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_WRDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_BD_WRDOMAIN_MASK) #define ENETC_SI_SIBCAR_BD_WRSNP_MASK (0xC0U) #define ENETC_SI_SIBCAR_BD_WRSNP_SHIFT (6U) #define ENETC_SI_SIBCAR_BD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_WRSNP_SHIFT)) & ENETC_SI_SIBCAR_BD_WRSNP_MASK) #define ENETC_SI_SIBCAR_WRCACHE_MASK (0xF00U) #define ENETC_SI_SIBCAR_WRCACHE_SHIFT (8U) #define ENETC_SI_SIBCAR_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_WRCACHE_SHIFT)) & ENETC_SI_SIBCAR_WRCACHE_MASK) #define ENETC_SI_SIBCAR_WRDOMAIN_MASK (0x3000U) #define ENETC_SI_SIBCAR_WRDOMAIN_SHIFT (12U) #define ENETC_SI_SIBCAR_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_WRDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_WRDOMAIN_MASK) #define ENETC_SI_SIBCAR_WRSNP_MASK (0xC000U) #define ENETC_SI_SIBCAR_WRSNP_SHIFT (14U) #define ENETC_SI_SIBCAR_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_WRSNP_SHIFT)) & ENETC_SI_SIBCAR_WRSNP_MASK) #define ENETC_SI_SIBCAR_BD_RDCACHE_MASK (0xF0000U) #define ENETC_SI_SIBCAR_BD_RDCACHE_SHIFT (16U) #define ENETC_SI_SIBCAR_BD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_RDCACHE_SHIFT)) & ENETC_SI_SIBCAR_BD_RDCACHE_MASK) #define ENETC_SI_SIBCAR_BD_RDDOMAIN_MASK (0x300000U) #define ENETC_SI_SIBCAR_BD_RDDOMAIN_SHIFT (20U) #define ENETC_SI_SIBCAR_BD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_RDDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_BD_RDDOMAIN_MASK) #define ENETC_SI_SIBCAR_BD_RDSNP_MASK (0xC00000U) #define ENETC_SI_SIBCAR_BD_RDSNP_SHIFT (22U) #define ENETC_SI_SIBCAR_BD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_BD_RDSNP_SHIFT)) & ENETC_SI_SIBCAR_BD_RDSNP_MASK) #define ENETC_SI_SIBCAR_RDCACHE_MASK (0xF000000U) #define ENETC_SI_SIBCAR_RDCACHE_SHIFT (24U) #define ENETC_SI_SIBCAR_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_RDCACHE_SHIFT)) & ENETC_SI_SIBCAR_RDCACHE_MASK) #define ENETC_SI_SIBCAR_RDDOMAIN_MASK (0x30000000U) #define ENETC_SI_SIBCAR_RDDOMAIN_SHIFT (28U) #define ENETC_SI_SIBCAR_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_RDDOMAIN_SHIFT)) & ENETC_SI_SIBCAR_RDDOMAIN_MASK) #define ENETC_SI_SIBCAR_RDSNP_MASK (0xC0000000U) #define ENETC_SI_SIBCAR_RDSNP_SHIFT (30U) #define ENETC_SI_SIBCAR_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBCAR_RDSNP_SHIFT)) & ENETC_SI_SIBCAR_RDSNP_MASK) /*! @} */ /*! @name SIMCAR - Station interface message cache attribute register */ /*! @{ */ #define ENETC_SI_SIMCAR_MSG_WRCACHE_MASK (0xFU) #define ENETC_SI_SIMCAR_MSG_WRCACHE_SHIFT (0U) #define ENETC_SI_SIMCAR_MSG_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_WRCACHE_SHIFT)) & ENETC_SI_SIMCAR_MSG_WRCACHE_MASK) #define ENETC_SI_SIMCAR_MSG_WRDOMAIN_MASK (0x30U) #define ENETC_SI_SIMCAR_MSG_WRDOMAIN_SHIFT (4U) #define ENETC_SI_SIMCAR_MSG_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_WRDOMAIN_SHIFT)) & ENETC_SI_SIMCAR_MSG_WRDOMAIN_MASK) #define ENETC_SI_SIMCAR_MSG_WRSNP_MASK (0xC0U) #define ENETC_SI_SIMCAR_MSG_WRSNP_SHIFT (6U) #define ENETC_SI_SIMCAR_MSG_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_WRSNP_SHIFT)) & ENETC_SI_SIMCAR_MSG_WRSNP_MASK) #define ENETC_SI_SIMCAR_MSG_RDCACHE_MASK (0xF0000U) #define ENETC_SI_SIMCAR_MSG_RDCACHE_SHIFT (16U) #define ENETC_SI_SIMCAR_MSG_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_RDCACHE_SHIFT)) & ENETC_SI_SIMCAR_MSG_RDCACHE_MASK) #define ENETC_SI_SIMCAR_MSG_RDDOMAIN_MASK (0x300000U) #define ENETC_SI_SIMCAR_MSG_RDDOMAIN_SHIFT (20U) #define ENETC_SI_SIMCAR_MSG_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_RDDOMAIN_SHIFT)) & ENETC_SI_SIMCAR_MSG_RDDOMAIN_MASK) #define ENETC_SI_SIMCAR_MSG_RDSNP_MASK (0xC00000U) #define ENETC_SI_SIMCAR_MSG_RDSNP_SHIFT (22U) #define ENETC_SI_SIMCAR_MSG_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMCAR_MSG_RDSNP_SHIFT)) & ENETC_SI_SIMCAR_MSG_RDSNP_MASK) /*! @} */ /*! @name SICCAR - Station interface command cache attribute register */ /*! @{ */ #define ENETC_SI_SICCAR_CBD_WRCACHE_MASK (0xFU) #define ENETC_SI_SICCAR_CBD_WRCACHE_SHIFT (0U) #define ENETC_SI_SICCAR_CBD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_WRCACHE_SHIFT)) & ENETC_SI_SICCAR_CBD_WRCACHE_MASK) #define ENETC_SI_SICCAR_CBD_WRDOMAIN_MASK (0x30U) #define ENETC_SI_SICCAR_CBD_WRDOMAIN_SHIFT (4U) #define ENETC_SI_SICCAR_CBD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_WRDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CBD_WRDOMAIN_MASK) #define ENETC_SI_SICCAR_CBD_WRSNP_MASK (0xC0U) #define ENETC_SI_SICCAR_CBD_WRSNP_SHIFT (6U) #define ENETC_SI_SICCAR_CBD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_WRSNP_SHIFT)) & ENETC_SI_SICCAR_CBD_WRSNP_MASK) #define ENETC_SI_SICCAR_CWRCACHE_MASK (0xF00U) #define ENETC_SI_SICCAR_CWRCACHE_SHIFT (8U) #define ENETC_SI_SICCAR_CWRCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CWRCACHE_SHIFT)) & ENETC_SI_SICCAR_CWRCACHE_MASK) #define ENETC_SI_SICCAR_CWRDOMAIN_MASK (0x3000U) #define ENETC_SI_SICCAR_CWRDOMAIN_SHIFT (12U) #define ENETC_SI_SICCAR_CWRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CWRDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CWRDOMAIN_MASK) #define ENETC_SI_SICCAR_CWRSNP_MASK (0xC000U) #define ENETC_SI_SICCAR_CWRSNP_SHIFT (14U) #define ENETC_SI_SICCAR_CWRSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CWRSNP_SHIFT)) & ENETC_SI_SICCAR_CWRSNP_MASK) #define ENETC_SI_SICCAR_CBD_RDCACHE_MASK (0xF0000U) #define ENETC_SI_SICCAR_CBD_RDCACHE_SHIFT (16U) #define ENETC_SI_SICCAR_CBD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_RDCACHE_SHIFT)) & ENETC_SI_SICCAR_CBD_RDCACHE_MASK) #define ENETC_SI_SICCAR_CBD_RDDOMAIN_MASK (0x300000U) #define ENETC_SI_SICCAR_CBD_RDDOMAIN_SHIFT (20U) #define ENETC_SI_SICCAR_CBD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_RDDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CBD_RDDOMAIN_MASK) #define ENETC_SI_SICCAR_CBD_RDSNP_MASK (0xC00000U) #define ENETC_SI_SICCAR_CBD_RDSNP_SHIFT (22U) #define ENETC_SI_SICCAR_CBD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CBD_RDSNP_SHIFT)) & ENETC_SI_SICCAR_CBD_RDSNP_MASK) #define ENETC_SI_SICCAR_CRDCACHE_MASK (0xF000000U) #define ENETC_SI_SICCAR_CRDCACHE_SHIFT (24U) #define ENETC_SI_SICCAR_CRDCACHE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CRDCACHE_SHIFT)) & ENETC_SI_SICCAR_CRDCACHE_MASK) #define ENETC_SI_SICCAR_CRDDOMAIN_MASK (0x30000000U) #define ENETC_SI_SICCAR_CRDDOMAIN_SHIFT (28U) #define ENETC_SI_SICCAR_CRDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CRDDOMAIN_SHIFT)) & ENETC_SI_SICCAR_CRDDOMAIN_MASK) #define ENETC_SI_SICCAR_CRDSNP_MASK (0xC0000000U) #define ENETC_SI_SICCAR_CRDSNP_SHIFT (30U) #define ENETC_SI_SICCAR_CRDSNP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICCAR_CRDSNP_SHIFT)) & ENETC_SI_SICCAR_CRDSNP_MASK) /*! @} */ /*! @name SIPMAR0 - Station interface primary MAC address register 0 */ /*! @{ */ #define ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) #define ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_SHIFT (0U) #define ENETC_SI_SIPMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_SHIFT)) & ENETC_SI_SIPMAR0_PRIM_MAC_ADDR_MASK) /*! @} */ /*! @name SIPMAR1 - Station interface primary MAC address register 1 */ /*! @{ */ #define ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) #define ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_SHIFT (0U) #define ENETC_SI_SIPMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_SHIFT)) & ENETC_SI_SIPMAR1_PRIM_MAC_ADDR_MASK) /*! @} */ /*! @name SICVLANR1 - Station interface custom VLAN register 1 */ /*! @{ */ #define ENETC_SI_SICVLANR1_ETYPE_MASK (0xFFFFU) #define ENETC_SI_SICVLANR1_ETYPE_SHIFT (0U) #define ENETC_SI_SICVLANR1_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR1_ETYPE_SHIFT)) & ENETC_SI_SICVLANR1_ETYPE_MASK) #define ENETC_SI_SICVLANR1_V_MASK (0x80000000U) #define ENETC_SI_SICVLANR1_V_SHIFT (31U) #define ENETC_SI_SICVLANR1_V(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR1_V_SHIFT)) & ENETC_SI_SICVLANR1_V_MASK) /*! @} */ /*! @name SICVLANR2 - Station interface custom VLAN register 2 */ /*! @{ */ #define ENETC_SI_SICVLANR2_ETYPE_MASK (0xFFFFU) #define ENETC_SI_SICVLANR2_ETYPE_SHIFT (0U) #define ENETC_SI_SICVLANR2_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR2_ETYPE_SHIFT)) & ENETC_SI_SICVLANR2_ETYPE_MASK) #define ENETC_SI_SICVLANR2_V_MASK (0x80000000U) #define ENETC_SI_SICVLANR2_V_SHIFT (31U) #define ENETC_SI_SICVLANR2_V(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICVLANR2_V_SHIFT)) & ENETC_SI_SICVLANR2_V_MASK) /*! @} */ /*! @name SIVLANIPVMR0 - Station interface VLAN to IPV mapping register 0 */ /*! @{ */ #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_MASK (0xFU) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_SHIFT (0U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_0_MASK) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_MASK (0xF0U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_SHIFT (4U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_1_MASK) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_MASK (0xF00U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_SHIFT (8U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_2_MASK) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_MASK (0xF000U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_SHIFT (12U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_3_MASK) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_MASK (0xF0000U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_SHIFT (16U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_4_MASK) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_MASK (0xF00000U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_SHIFT (20U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_5_MASK) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_MASK (0xF000000U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_SHIFT (24U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_6_MASK) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_MASK (0xF0000000U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_SHIFT (28U) #define ENETC_SI_SIVLANIPVMR0_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_SHIFT)) & ENETC_SI_SIVLANIPVMR0_PCP_DEI_7_MASK) /*! @} */ /*! @name SIVLANIPVMR1 - Station interface VLAN to IPV mapping register 1 */ /*! @{ */ #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_MASK (0xFU) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_SHIFT (0U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_8_MASK) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_MASK (0xF0U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_SHIFT (4U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_9_MASK) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_MASK (0xF00U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_SHIFT (8U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_10_MASK) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_MASK (0xF000U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_SHIFT (12U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_11_MASK) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_MASK (0xF0000U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_SHIFT (16U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_12_MASK) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_MASK (0xF00000U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_SHIFT (20U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_13_MASK) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_MASK (0xF000000U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_SHIFT (24U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_14_MASK) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_MASK (0xF0000000U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_SHIFT (28U) #define ENETC_SI_SIVLANIPVMR1_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_SHIFT)) & ENETC_SI_SIVLANIPVMR1_PCP_DEI_15_MASK) /*! @} */ /*! @name SIIPVBDRMR0 - Station interface IPV to ring mapping register */ /*! @{ */ #define ENETC_SI_SIIPVBDRMR0_IPV0BDR_MASK (0x7U) #define ENETC_SI_SIIPVBDRMR0_IPV0BDR_SHIFT (0U) #define ENETC_SI_SIIPVBDRMR0_IPV0BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV0BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV0BDR_MASK) #define ENETC_SI_SIIPVBDRMR0_IPV1BDR_MASK (0x70U) #define ENETC_SI_SIIPVBDRMR0_IPV1BDR_SHIFT (4U) #define ENETC_SI_SIIPVBDRMR0_IPV1BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV1BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV1BDR_MASK) #define ENETC_SI_SIIPVBDRMR0_IPV2BDR_MASK (0x700U) #define ENETC_SI_SIIPVBDRMR0_IPV2BDR_SHIFT (8U) #define ENETC_SI_SIIPVBDRMR0_IPV2BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV2BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV2BDR_MASK) #define ENETC_SI_SIIPVBDRMR0_IPV3BDR_MASK (0x7000U) #define ENETC_SI_SIIPVBDRMR0_IPV3BDR_SHIFT (12U) #define ENETC_SI_SIIPVBDRMR0_IPV3BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV3BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV3BDR_MASK) #define ENETC_SI_SIIPVBDRMR0_IPV4BDR_MASK (0x70000U) #define ENETC_SI_SIIPVBDRMR0_IPV4BDR_SHIFT (16U) #define ENETC_SI_SIIPVBDRMR0_IPV4BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV4BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV4BDR_MASK) #define ENETC_SI_SIIPVBDRMR0_IPV5BDR_MASK (0x700000U) #define ENETC_SI_SIIPVBDRMR0_IPV5BDR_SHIFT (20U) #define ENETC_SI_SIIPVBDRMR0_IPV5BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV5BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV5BDR_MASK) #define ENETC_SI_SIIPVBDRMR0_IPV6BDR_MASK (0x7000000U) #define ENETC_SI_SIIPVBDRMR0_IPV6BDR_SHIFT (24U) #define ENETC_SI_SIIPVBDRMR0_IPV6BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV6BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV6BDR_MASK) #define ENETC_SI_SIIPVBDRMR0_IPV7BDR_MASK (0x70000000U) #define ENETC_SI_SIIPVBDRMR0_IPV7BDR_SHIFT (28U) #define ENETC_SI_SIIPVBDRMR0_IPV7BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIIPVBDRMR0_IPV7BDR_SHIFT)) & ENETC_SI_SIIPVBDRMR0_IPV7BDR_MASK) /*! @} */ /*! @name PSIMSGRR - Physical station interface message receive register */ /*! @{ */ #define ENETC_SI_PSIMSGRR_MR1_MASK (0x2U) #define ENETC_SI_PSIMSGRR_MR1_SHIFT (1U) #define ENETC_SI_PSIMSGRR_MR1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGRR_MR1_SHIFT)) & ENETC_SI_PSIMSGRR_MR1_MASK) #define ENETC_SI_PSIMSGRR_MR2_MASK (0x4U) #define ENETC_SI_PSIMSGRR_MR2_SHIFT (2U) #define ENETC_SI_PSIMSGRR_MR2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGRR_MR2_SHIFT)) & ENETC_SI_PSIMSGRR_MR2_MASK) #define ENETC_SI_PSIMSGRR_MC_MASK (0xFFFF0000U) #define ENETC_SI_PSIMSGRR_MC_SHIFT (16U) #define ENETC_SI_PSIMSGRR_MC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGRR_MC_SHIFT)) & ENETC_SI_PSIMSGRR_MC_MASK) /*! @} */ /*! @name PSIMSGSR - Physical station interface message send register */ /*! @{ */ #define ENETC_SI_PSIMSGSR_MS1_MASK (0x2U) #define ENETC_SI_PSIMSGSR_MS1_SHIFT (1U) #define ENETC_SI_PSIMSGSR_MS1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGSR_MS1_SHIFT)) & ENETC_SI_PSIMSGSR_MS1_MASK) #define ENETC_SI_PSIMSGSR_MS2_MASK (0x4U) #define ENETC_SI_PSIMSGSR_MS2_SHIFT (2U) #define ENETC_SI_PSIMSGSR_MS2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGSR_MS2_SHIFT)) & ENETC_SI_PSIMSGSR_MS2_MASK) #define ENETC_SI_PSIMSGSR_MC_MASK (0xFFFF0000U) #define ENETC_SI_PSIMSGSR_MC_SHIFT (16U) #define ENETC_SI_PSIMSGSR_MC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIMSGSR_MC_SHIFT)) & ENETC_SI_PSIMSGSR_MC_MASK) /*! @} */ /*! @name PSIVMSGRCVAR0 - PSI VSI 1 message receive address register 0..PSI VSI 2 message receive address register 0 */ /*! @{ */ #define ENETC_SI_PSIVMSGRCVAR0_MSIZE_MASK (0x1FU) #define ENETC_SI_PSIVMSGRCVAR0_MSIZE_SHIFT (0U) #define ENETC_SI_PSIVMSGRCVAR0_MSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIVMSGRCVAR0_MSIZE_SHIFT)) & ENETC_SI_PSIVMSGRCVAR0_MSIZE_MASK) #define ENETC_SI_PSIVMSGRCVAR0_ADDRL_MASK (0xFFFFFFC0U) #define ENETC_SI_PSIVMSGRCVAR0_ADDRL_SHIFT (6U) #define ENETC_SI_PSIVMSGRCVAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIVMSGRCVAR0_ADDRL_SHIFT)) & ENETC_SI_PSIVMSGRCVAR0_ADDRL_MASK) /*! @} */ /* The count of ENETC_SI_PSIVMSGRCVAR0 */ #define ENETC_SI_PSIVMSGRCVAR0_COUNT (2U) /*! @name PSIVMSGRCVAR1 - PSI VSI 1 message receive address register 1..PSI VSI 2 message receive address register 1 */ /*! @{ */ #define ENETC_SI_PSIVMSGRCVAR1_ADDRH_MASK (0xFFFFFFFFU) #define ENETC_SI_PSIVMSGRCVAR1_ADDRH_SHIFT (0U) #define ENETC_SI_PSIVMSGRCVAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIVMSGRCVAR1_ADDRH_SHIFT)) & ENETC_SI_PSIVMSGRCVAR1_ADDRH_MASK) /*! @} */ /* The count of ENETC_SI_PSIVMSGRCVAR1 */ #define ENETC_SI_PSIVMSGRCVAR1_COUNT (2U) /*! @name VSIMSGSR - Virtual station interface message send register */ /*! @{ */ #define ENETC_SI_VSIMSGSR_MB_MASK (0x1U) #define ENETC_SI_VSIMSGSR_MB_SHIFT (0U) #define ENETC_SI_VSIMSGSR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSR_MB_SHIFT)) & ENETC_SI_VSIMSGSR_MB_MASK) #define ENETC_SI_VSIMSGSR_MS_MASK (0x2U) #define ENETC_SI_VSIMSGSR_MS_SHIFT (1U) #define ENETC_SI_VSIMSGSR_MS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSR_MS_SHIFT)) & ENETC_SI_VSIMSGSR_MS_MASK) #define ENETC_SI_VSIMSGSR_MC_MASK (0xFFFF0000U) #define ENETC_SI_VSIMSGSR_MC_SHIFT (16U) #define ENETC_SI_VSIMSGSR_MC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSR_MC_SHIFT)) & ENETC_SI_VSIMSGSR_MC_MASK) /*! @} */ /*! @name VSIMSGRR - Virtual station interface message receive register */ /*! @{ */ #define ENETC_SI_VSIMSGRR_MR_MASK (0x1U) #define ENETC_SI_VSIMSGRR_MR_SHIFT (0U) #define ENETC_SI_VSIMSGRR_MR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGRR_MR_SHIFT)) & ENETC_SI_VSIMSGRR_MR_MASK) #define ENETC_SI_VSIMSGRR_MC_MASK (0xFFFF0000U) #define ENETC_SI_VSIMSGRR_MC_SHIFT (16U) #define ENETC_SI_VSIMSGRR_MC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGRR_MC_SHIFT)) & ENETC_SI_VSIMSGRR_MC_MASK) /*! @} */ /*! @name VSIMSGSNDAR0 - Virtual station interface message address send register 0 */ /*! @{ */ #define ENETC_SI_VSIMSGSNDAR0_MSIZE_MASK (0x1FU) #define ENETC_SI_VSIMSGSNDAR0_MSIZE_SHIFT (0U) #define ENETC_SI_VSIMSGSNDAR0_MSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSNDAR0_MSIZE_SHIFT)) & ENETC_SI_VSIMSGSNDAR0_MSIZE_MASK) #define ENETC_SI_VSIMSGSNDAR0_ADDRL_MASK (0xFFFFFFC0U) #define ENETC_SI_VSIMSGSNDAR0_ADDRL_SHIFT (6U) #define ENETC_SI_VSIMSGSNDAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSNDAR0_ADDRL_SHIFT)) & ENETC_SI_VSIMSGSNDAR0_ADDRL_MASK) /*! @} */ /*! @name VSIMSGSNDAR1 - Virtual station interface message send address register 1 */ /*! @{ */ #define ENETC_SI_VSIMSGSNDAR1_ADDRH_MASK (0xFFFFFFFFU) #define ENETC_SI_VSIMSGSNDAR1_ADDRH_SHIFT (0U) #define ENETC_SI_VSIMSGSNDAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIMSGSNDAR1_ADDRH_SHIFT)) & ENETC_SI_VSIMSGSNDAR1_ADDRH_MASK) /*! @} */ /*! @name SIROCT0 - Station interface receive octets counter (ifInOctets) 0 */ /*! @{ */ #define ENETC_SI_SIROCT0_ROCT_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SIROCT0_ROCT_LOW_SHIFT (0U) #define ENETC_SI_SIROCT0_ROCT_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIROCT0_ROCT_LOW_SHIFT)) & ENETC_SI_SIROCT0_ROCT_LOW_MASK) /*! @} */ /*! @name SIROCT1 - Station interface receive octets counter (ifInOctets) 1 */ /*! @{ */ #define ENETC_SI_SIROCT1_ROCT_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SIROCT1_ROCT_HIGH_SHIFT (0U) #define ENETC_SI_SIROCT1_ROCT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIROCT1_ROCT_HIGH_SHIFT)) & ENETC_SI_SIROCT1_ROCT_HIGH_MASK) /*! @} */ /*! @name SIRFRM0 - Station interface receive frame counter (aFrameReceivedOK) 0 */ /*! @{ */ #define ENETC_SI_SIRFRM0_RFRM_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SIRFRM0_RFRM_LOW_SHIFT (0U) #define ENETC_SI_SIRFRM0_RFRM_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRFRM0_RFRM_LOW_SHIFT)) & ENETC_SI_SIRFRM0_RFRM_LOW_MASK) /*! @} */ /*! @name SIRFRM1 - Station interface receive frame counter (aFrameReceivedOK) 1 */ /*! @{ */ #define ENETC_SI_SIRFRM1_RFRM_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SIRFRM1_RFRM_HIGH_SHIFT (0U) #define ENETC_SI_SIRFRM1_RFRM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRFRM1_RFRM_HIGH_SHIFT)) & ENETC_SI_SIRFRM1_RFRM_HIGH_MASK) /*! @} */ /*! @name SIRUCA0 - Station interface receive unicast frame counter (ifInUcastPkts) 0 */ /*! @{ */ #define ENETC_SI_SIRUCA0_RUCA_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SIRUCA0_RUCA_LOW_SHIFT (0U) #define ENETC_SI_SIRUCA0_RUCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRUCA0_RUCA_LOW_SHIFT)) & ENETC_SI_SIRUCA0_RUCA_LOW_MASK) /*! @} */ /*! @name SIRUCA1 - Station interface receive unicast frame counter (ifInUcastPkts) 1 */ /*! @{ */ #define ENETC_SI_SIRUCA1_RUCA_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SIRUCA1_RUCA_HIGH_SHIFT (0U) #define ENETC_SI_SIRUCA1_RUCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRUCA1_RUCA_HIGH_SHIFT)) & ENETC_SI_SIRUCA1_RUCA_HIGH_MASK) /*! @} */ /*! @name SIRMCA0 - Station interface receive multicast frame counter (ifInMulticastPkts) 0 */ /*! @{ */ #define ENETC_SI_SIRMCA0_RMCA_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SIRMCA0_RMCA_LOW_SHIFT (0U) #define ENETC_SI_SIRMCA0_RMCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRMCA0_RMCA_LOW_SHIFT)) & ENETC_SI_SIRMCA0_RMCA_LOW_MASK) /*! @} */ /*! @name SIRMCA1 - Station interface receive multicast frame counter (ifInMulticastPkts) 1 */ /*! @{ */ #define ENETC_SI_SIRMCA1_RMCA_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SIRMCA1_RMCA_HIGH_SHIFT (0U) #define ENETC_SI_SIRMCA1_RMCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRMCA1_RMCA_HIGH_SHIFT)) & ENETC_SI_SIRMCA1_RMCA_HIGH_MASK) /*! @} */ /*! @name SITOCT0 - Station interface transmit octets counter (ifOutOctets) 0 */ /*! @{ */ #define ENETC_SI_SITOCT0_TOCT_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SITOCT0_TOCT_LOW_SHIFT (0U) #define ENETC_SI_SITOCT0_TOCT_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITOCT0_TOCT_LOW_SHIFT)) & ENETC_SI_SITOCT0_TOCT_LOW_MASK) /*! @} */ /*! @name SITOCT1 - Station interface transmit octets counter (ifOutOctets) 1 */ /*! @{ */ #define ENETC_SI_SITOCT1_TOCT_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SITOCT1_TOCT_HIGH_SHIFT (0U) #define ENETC_SI_SITOCT1_TOCT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITOCT1_TOCT_HIGH_SHIFT)) & ENETC_SI_SITOCT1_TOCT_HIGH_MASK) /*! @} */ /*! @name SITFRM0 - Station interface transmit frame counter (aFrameTransmittedOK) 0 */ /*! @{ */ #define ENETC_SI_SITFRM0_TFRM_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SITFRM0_TFRM_LOW_SHIFT (0U) #define ENETC_SI_SITFRM0_TFRM_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITFRM0_TFRM_LOW_SHIFT)) & ENETC_SI_SITFRM0_TFRM_LOW_MASK) /*! @} */ /*! @name SITFRM1 - Station interface transmit frame counter (aFrameTransmittedOK) 1 */ /*! @{ */ #define ENETC_SI_SITFRM1_TFRM_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SITFRM1_TFRM_HIGH_SHIFT (0U) #define ENETC_SI_SITFRM1_TFRM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITFRM1_TFRM_HIGH_SHIFT)) & ENETC_SI_SITFRM1_TFRM_HIGH_MASK) /*! @} */ /*! @name SITUCA0 - Station interface transmit unicast frame counter (ifOutUcastPkts) 0 */ /*! @{ */ #define ENETC_SI_SITUCA0_TUCA_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SITUCA0_TUCA_LOW_SHIFT (0U) #define ENETC_SI_SITUCA0_TUCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITUCA0_TUCA_LOW_SHIFT)) & ENETC_SI_SITUCA0_TUCA_LOW_MASK) /*! @} */ /*! @name SITUCA1 - Station interface transmit unicast frame counter (ifOutUcastPkts) 1 */ /*! @{ */ #define ENETC_SI_SITUCA1_TUCA_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SITUCA1_TUCA_HIGH_SHIFT (0U) #define ENETC_SI_SITUCA1_TUCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITUCA1_TUCA_HIGH_SHIFT)) & ENETC_SI_SITUCA1_TUCA_HIGH_MASK) /*! @} */ /*! @name SITMCA0 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 0 */ /*! @{ */ #define ENETC_SI_SITMCA0_TMCA_LOW_MASK (0xFFFFFFFFU) #define ENETC_SI_SITMCA0_TMCA_LOW_SHIFT (0U) #define ENETC_SI_SITMCA0_TMCA_LOW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMCA0_TMCA_LOW_SHIFT)) & ENETC_SI_SITMCA0_TMCA_LOW_MASK) /*! @} */ /*! @name SITMCA1 - Station interface transmit multicast frame counter (ifOutMulticastPkts) 1 */ /*! @{ */ #define ENETC_SI_SITMCA1_TMCA_HIGH_MASK (0xFFFFFFFFU) #define ENETC_SI_SITMCA1_TMCA_HIGH_SHIFT (0U) #define ENETC_SI_SITMCA1_TMCA_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMCA1_TMCA_HIGH_SHIFT)) & ENETC_SI_SITMCA1_TMCA_HIGH_MASK) /*! @} */ /*! @name SITDFCR - Station interface transmit discard frame counter */ /*! @{ */ #define ENETC_SI_SITDFCR_COUNT_MASK (0xFFFFFFFFU) #define ENETC_SI_SITDFCR_COUNT_SHIFT (0U) /*! COUNT - Counter */ #define ENETC_SI_SITDFCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITDFCR_COUNT_SHIFT)) & ENETC_SI_SITDFCR_COUNT_MASK) /*! @} */ /*! @name SIBLPR - Station interface boot loader parameter register 0..Station interface boot loader parameter register 1 */ /*! @{ */ #define ENETC_SI_SIBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) #define ENETC_SI_SIBLPR_PARAM_VAL_SHIFT (0U) #define ENETC_SI_SIBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIBLPR_PARAM_VAL_SHIFT)) & ENETC_SI_SIBLPR_PARAM_VAL_MASK) /*! @} */ /* The count of ENETC_SI_SIBLPR */ #define ENETC_SI_SIBLPR_COUNT (2U) /*! @name SICBDRMR - Station interface command BDR mode register */ /*! @{ */ #define ENETC_SI_SICBDRMR_EN_MASK (0x80000000U) #define ENETC_SI_SICBDRMR_EN_SHIFT (31U) #define ENETC_SI_SICBDRMR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRMR_EN_SHIFT)) & ENETC_SI_SICBDRMR_EN_MASK) /*! @} */ /*! @name SICBDRSR - Station interface command BDR status register */ /*! @{ */ #define ENETC_SI_SICBDRSR_BUSY_MASK (0x1U) #define ENETC_SI_SICBDRSR_BUSY_SHIFT (0U) #define ENETC_SI_SICBDRSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRSR_BUSY_SHIFT)) & ENETC_SI_SICBDRSR_BUSY_MASK) /*! @} */ /*! @name SICBDRBAR0 - Station interface command BDR base address register 0 */ /*! @{ */ #define ENETC_SI_SICBDRBAR0_ADDRL_MASK (0xFFFFFF80U) #define ENETC_SI_SICBDRBAR0_ADDRL_SHIFT (7U) #define ENETC_SI_SICBDRBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRBAR0_ADDRL_SHIFT)) & ENETC_SI_SICBDRBAR0_ADDRL_MASK) /*! @} */ /*! @name SICBDRBAR1 - Station interface command BDR base address register 1 */ /*! @{ */ #define ENETC_SI_SICBDRBAR1_ADDRH_MASK (0xFFFFFFFFU) #define ENETC_SI_SICBDRBAR1_ADDRH_SHIFT (0U) #define ENETC_SI_SICBDRBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRBAR1_ADDRH_SHIFT)) & ENETC_SI_SICBDRBAR1_ADDRH_MASK) /*! @} */ /*! @name SICBDRPIR - Station interface command BDR producer index register */ /*! @{ */ #define ENETC_SI_SICBDRPIR_BDR_INDEX_MASK (0x3FFU) #define ENETC_SI_SICBDRPIR_BDR_INDEX_SHIFT (0U) #define ENETC_SI_SICBDRPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRPIR_BDR_INDEX_SHIFT)) & ENETC_SI_SICBDRPIR_BDR_INDEX_MASK) /*! @} */ /*! @name SICBDRCIR - Station interface command BDR consumer index register */ /*! @{ */ #define ENETC_SI_SICBDRCIR_BDR_INDEX_MASK (0x3FFU) #define ENETC_SI_SICBDRCIR_BDR_INDEX_SHIFT (0U) #define ENETC_SI_SICBDRCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRCIR_BDR_INDEX_SHIFT)) & ENETC_SI_SICBDRCIR_BDR_INDEX_MASK) #define ENETC_SI_SICBDRCIR_SBE_MASK (0x80000000U) #define ENETC_SI_SICBDRCIR_SBE_SHIFT (31U) #define ENETC_SI_SICBDRCIR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRCIR_SBE_SHIFT)) & ENETC_SI_SICBDRCIR_SBE_MASK) /*! @} */ /*! @name SICBDRLENR - Station interface command BDR length register */ /*! @{ */ #define ENETC_SI_SICBDRLENR_LENGTH_MASK (0x7F8U) #define ENETC_SI_SICBDRLENR_LENGTH_SHIFT (3U) #define ENETC_SI_SICBDRLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRLENR_LENGTH_SHIFT)) & ENETC_SI_SICBDRLENR_LENGTH_MASK) /*! @} */ /*! @name SICBDRIER - Station interface command BDR interrupt enable register */ /*! @{ */ #define ENETC_SI_SICBDRIER_CBDCIE_MASK (0x1U) #define ENETC_SI_SICBDRIER_CBDCIE_SHIFT (0U) #define ENETC_SI_SICBDRIER_CBDCIE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRIER_CBDCIE_SHIFT)) & ENETC_SI_SICBDRIER_CBDCIE_MASK) /*! @} */ /*! @name SICBDRIDR - Station interface command BDR interrupt detect register */ /*! @{ */ #define ENETC_SI_SICBDRIDR_CBDC_MASK (0x1U) #define ENETC_SI_SICBDRIDR_CBDC_SHIFT (0U) #define ENETC_SI_SICBDRIDR_CBDC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICBDRIDR_CBDC_SHIFT)) & ENETC_SI_SICBDRIDR_CBDC_MASK) /*! @} */ /*! @name SICAPR0 - Station interface capability register 0 */ /*! @{ */ #define ENETC_SI_SICAPR0_NUM_TX_BDR_MASK (0xFFU) #define ENETC_SI_SICAPR0_NUM_TX_BDR_SHIFT (0U) #define ENETC_SI_SICAPR0_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR0_NUM_TX_BDR_SHIFT)) & ENETC_SI_SICAPR0_NUM_TX_BDR_MASK) #define ENETC_SI_SICAPR0_NUM_RX_BDR_MASK (0xFF0000U) #define ENETC_SI_SICAPR0_NUM_RX_BDR_SHIFT (16U) #define ENETC_SI_SICAPR0_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR0_NUM_RX_BDR_SHIFT)) & ENETC_SI_SICAPR0_NUM_RX_BDR_MASK) /*! @} */ /*! @name SICAPR1 - Station interface capability register 1 */ /*! @{ */ #define ENETC_SI_SICAPR1_NUM_RX_GRP_MASK (0xFF0000U) #define ENETC_SI_SICAPR1_NUM_RX_GRP_SHIFT (16U) #define ENETC_SI_SICAPR1_NUM_RX_GRP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR1_NUM_RX_GRP_SHIFT)) & ENETC_SI_SICAPR1_NUM_RX_GRP_MASK) /*! @} */ /*! @name SICAPR2 - Station interface capability register 2 */ /*! @{ */ #define ENETC_SI_SICAPR2_VTP_MASK (0xFU) #define ENETC_SI_SICAPR2_VTP_SHIFT (0U) #define ENETC_SI_SICAPR2_VTP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICAPR2_VTP_SHIFT)) & ENETC_SI_SICAPR2_VTP_MASK) /*! @} */ /*! @name PSIIER - Physical station interface interrupt enable register */ /*! @{ */ #define ENETC_SI_PSIIER_MR1IE_MASK (0x2U) #define ENETC_SI_PSIIER_MR1IE_SHIFT (1U) #define ENETC_SI_PSIIER_MR1IE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIER_MR1IE_SHIFT)) & ENETC_SI_PSIIER_MR1IE_MASK) #define ENETC_SI_PSIIER_MR2IE_MASK (0x4U) #define ENETC_SI_PSIIER_MR2IE_SHIFT (2U) #define ENETC_SI_PSIIER_MR2IE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIER_MR2IE_SHIFT)) & ENETC_SI_PSIIER_MR2IE_MASK) #define ENETC_SI_PSIIER_FLR1IE_MASK (0x20000U) #define ENETC_SI_PSIIER_FLR1IE_SHIFT (17U) #define ENETC_SI_PSIIER_FLR1IE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIER_FLR1IE_SHIFT)) & ENETC_SI_PSIIER_FLR1IE_MASK) #define ENETC_SI_PSIIER_FLR2IE_MASK (0x40000U) #define ENETC_SI_PSIIER_FLR2IE_SHIFT (18U) #define ENETC_SI_PSIIER_FLR2IE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIER_FLR2IE_SHIFT)) & ENETC_SI_PSIIER_FLR2IE_MASK) /*! @} */ /*! @name PSIIDR - Physical station interface interrupt detect register */ /*! @{ */ #define ENETC_SI_PSIIDR_TXR_MASK (0x1U) #define ENETC_SI_PSIIDR_TXR_SHIFT (0U) #define ENETC_SI_PSIIDR_TXR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_TXR_SHIFT)) & ENETC_SI_PSIIDR_TXR_MASK) #define ENETC_SI_PSIIDR_MR1_MASK (0x2U) #define ENETC_SI_PSIIDR_MR1_SHIFT (1U) #define ENETC_SI_PSIIDR_MR1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_MR1_SHIFT)) & ENETC_SI_PSIIDR_MR1_MASK) #define ENETC_SI_PSIIDR_MR2_MASK (0x4U) #define ENETC_SI_PSIIDR_MR2_SHIFT (2U) #define ENETC_SI_PSIIDR_MR2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_MR2_SHIFT)) & ENETC_SI_PSIIDR_MR2_MASK) #define ENETC_SI_PSIIDR_RXR_MASK (0x10000U) #define ENETC_SI_PSIIDR_RXR_SHIFT (16U) #define ENETC_SI_PSIIDR_RXR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_RXR_SHIFT)) & ENETC_SI_PSIIDR_RXR_MASK) #define ENETC_SI_PSIIDR_FLR1_MASK (0x20000U) #define ENETC_SI_PSIIDR_FLR1_SHIFT (17U) #define ENETC_SI_PSIIDR_FLR1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_FLR1_SHIFT)) & ENETC_SI_PSIIDR_FLR1_MASK) #define ENETC_SI_PSIIDR_FLR2_MASK (0x40000U) #define ENETC_SI_PSIIDR_FLR2_SHIFT (18U) #define ENETC_SI_PSIIDR_FLR2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_PSIIDR_FLR2_SHIFT)) & ENETC_SI_PSIIDR_FLR2_MASK) /*! @} */ /*! @name VSIIER - Virtual station interface interrupt enable register */ /*! @{ */ #define ENETC_SI_VSIIER_MSIE_MASK (0x100U) #define ENETC_SI_VSIIER_MSIE_SHIFT (8U) #define ENETC_SI_VSIIER_MSIE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIER_MSIE_SHIFT)) & ENETC_SI_VSIIER_MSIE_MASK) #define ENETC_SI_VSIIER_MRIE_MASK (0x200U) #define ENETC_SI_VSIIER_MRIE_SHIFT (9U) #define ENETC_SI_VSIIER_MRIE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIER_MRIE_SHIFT)) & ENETC_SI_VSIIER_MRIE_MASK) /*! @} */ /*! @name VSIIDR - Virtual station interface interrupt detect register */ /*! @{ */ #define ENETC_SI_VSIIDR_TXR_MASK (0x1U) #define ENETC_SI_VSIIDR_TXR_SHIFT (0U) #define ENETC_SI_VSIIDR_TXR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_TXR_SHIFT)) & ENETC_SI_VSIIDR_TXR_MASK) #define ENETC_SI_VSIIDR_MS_MASK (0x100U) #define ENETC_SI_VSIIDR_MS_SHIFT (8U) #define ENETC_SI_VSIIDR_MS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_MS_SHIFT)) & ENETC_SI_VSIIDR_MS_MASK) #define ENETC_SI_VSIIDR_MR_MASK (0x200U) #define ENETC_SI_VSIIDR_MR_SHIFT (9U) #define ENETC_SI_VSIIDR_MR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_MR_SHIFT)) & ENETC_SI_VSIIDR_MR_MASK) #define ENETC_SI_VSIIDR_RXR_MASK (0x10000U) #define ENETC_SI_VSIIDR_RXR_SHIFT (16U) #define ENETC_SI_VSIIDR_RXR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_VSIIDR_RXR_SHIFT)) & ENETC_SI_VSIIDR_RXR_MASK) /*! @} */ /*! @name SITXIDR0 - Station interface transmit interrupt detect register 0 */ /*! @{ */ #define ENETC_SI_SITXIDR0_TXT0_MASK (0x1U) #define ENETC_SI_SITXIDR0_TXT0_SHIFT (0U) #define ENETC_SI_SITXIDR0_TXT0(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT0_SHIFT)) & ENETC_SI_SITXIDR0_TXT0_MASK) #define ENETC_SI_SITXIDR0_TXT1_MASK (0x2U) #define ENETC_SI_SITXIDR0_TXT1_SHIFT (1U) #define ENETC_SI_SITXIDR0_TXT1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT1_SHIFT)) & ENETC_SI_SITXIDR0_TXT1_MASK) #define ENETC_SI_SITXIDR0_TXT2_MASK (0x4U) #define ENETC_SI_SITXIDR0_TXT2_SHIFT (2U) #define ENETC_SI_SITXIDR0_TXT2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT2_SHIFT)) & ENETC_SI_SITXIDR0_TXT2_MASK) #define ENETC_SI_SITXIDR0_TXT3_MASK (0x8U) #define ENETC_SI_SITXIDR0_TXT3_SHIFT (3U) #define ENETC_SI_SITXIDR0_TXT3(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT3_SHIFT)) & ENETC_SI_SITXIDR0_TXT3_MASK) #define ENETC_SI_SITXIDR0_TXT4_MASK (0x10U) #define ENETC_SI_SITXIDR0_TXT4_SHIFT (4U) #define ENETC_SI_SITXIDR0_TXT4(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT4_SHIFT)) & ENETC_SI_SITXIDR0_TXT4_MASK) #define ENETC_SI_SITXIDR0_TXT5_MASK (0x20U) #define ENETC_SI_SITXIDR0_TXT5_SHIFT (5U) #define ENETC_SI_SITXIDR0_TXT5(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT5_SHIFT)) & ENETC_SI_SITXIDR0_TXT5_MASK) #define ENETC_SI_SITXIDR0_TXT6_MASK (0x40U) #define ENETC_SI_SITXIDR0_TXT6_SHIFT (6U) #define ENETC_SI_SITXIDR0_TXT6(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT6_SHIFT)) & ENETC_SI_SITXIDR0_TXT6_MASK) #define ENETC_SI_SITXIDR0_TXT7_MASK (0x80U) #define ENETC_SI_SITXIDR0_TXT7_SHIFT (7U) #define ENETC_SI_SITXIDR0_TXT7(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT7_SHIFT)) & ENETC_SI_SITXIDR0_TXT7_MASK) #define ENETC_SI_SITXIDR0_TXT8_MASK (0x100U) #define ENETC_SI_SITXIDR0_TXT8_SHIFT (8U) #define ENETC_SI_SITXIDR0_TXT8(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT8_SHIFT)) & ENETC_SI_SITXIDR0_TXT8_MASK) #define ENETC_SI_SITXIDR0_TXT9_MASK (0x200U) #define ENETC_SI_SITXIDR0_TXT9_SHIFT (9U) #define ENETC_SI_SITXIDR0_TXT9(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT9_SHIFT)) & ENETC_SI_SITXIDR0_TXT9_MASK) #define ENETC_SI_SITXIDR0_TXT10_MASK (0x400U) #define ENETC_SI_SITXIDR0_TXT10_SHIFT (10U) #define ENETC_SI_SITXIDR0_TXT10(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT10_SHIFT)) & ENETC_SI_SITXIDR0_TXT10_MASK) #define ENETC_SI_SITXIDR0_TXT11_MASK (0x800U) #define ENETC_SI_SITXIDR0_TXT11_SHIFT (11U) #define ENETC_SI_SITXIDR0_TXT11(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT11_SHIFT)) & ENETC_SI_SITXIDR0_TXT11_MASK) #define ENETC_SI_SITXIDR0_TXT12_MASK (0x1000U) #define ENETC_SI_SITXIDR0_TXT12_SHIFT (12U) #define ENETC_SI_SITXIDR0_TXT12(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT12_SHIFT)) & ENETC_SI_SITXIDR0_TXT12_MASK) #define ENETC_SI_SITXIDR0_TXT13_MASK (0x2000U) #define ENETC_SI_SITXIDR0_TXT13_SHIFT (13U) #define ENETC_SI_SITXIDR0_TXT13(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT13_SHIFT)) & ENETC_SI_SITXIDR0_TXT13_MASK) #define ENETC_SI_SITXIDR0_TXT14_MASK (0x4000U) #define ENETC_SI_SITXIDR0_TXT14_SHIFT (14U) #define ENETC_SI_SITXIDR0_TXT14(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT14_SHIFT)) & ENETC_SI_SITXIDR0_TXT14_MASK) #define ENETC_SI_SITXIDR0_TXT15_MASK (0x8000U) #define ENETC_SI_SITXIDR0_TXT15_SHIFT (15U) #define ENETC_SI_SITXIDR0_TXT15(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXT15_SHIFT)) & ENETC_SI_SITXIDR0_TXT15_MASK) #define ENETC_SI_SITXIDR0_TXF0_MASK (0x10000U) #define ENETC_SI_SITXIDR0_TXF0_SHIFT (16U) #define ENETC_SI_SITXIDR0_TXF0(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF0_SHIFT)) & ENETC_SI_SITXIDR0_TXF0_MASK) #define ENETC_SI_SITXIDR0_TXF1_MASK (0x20000U) #define ENETC_SI_SITXIDR0_TXF1_SHIFT (17U) #define ENETC_SI_SITXIDR0_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF1_SHIFT)) & ENETC_SI_SITXIDR0_TXF1_MASK) #define ENETC_SI_SITXIDR0_TXF2_MASK (0x40000U) #define ENETC_SI_SITXIDR0_TXF2_SHIFT (18U) #define ENETC_SI_SITXIDR0_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF2_SHIFT)) & ENETC_SI_SITXIDR0_TXF2_MASK) #define ENETC_SI_SITXIDR0_TXF3_MASK (0x80000U) #define ENETC_SI_SITXIDR0_TXF3_SHIFT (19U) #define ENETC_SI_SITXIDR0_TXF3(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF3_SHIFT)) & ENETC_SI_SITXIDR0_TXF3_MASK) #define ENETC_SI_SITXIDR0_TXF4_MASK (0x100000U) #define ENETC_SI_SITXIDR0_TXF4_SHIFT (20U) #define ENETC_SI_SITXIDR0_TXF4(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF4_SHIFT)) & ENETC_SI_SITXIDR0_TXF4_MASK) #define ENETC_SI_SITXIDR0_TXF5_MASK (0x200000U) #define ENETC_SI_SITXIDR0_TXF5_SHIFT (21U) #define ENETC_SI_SITXIDR0_TXF5(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF5_SHIFT)) & ENETC_SI_SITXIDR0_TXF5_MASK) #define ENETC_SI_SITXIDR0_TXF6_MASK (0x400000U) #define ENETC_SI_SITXIDR0_TXF6_SHIFT (22U) #define ENETC_SI_SITXIDR0_TXF6(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF6_SHIFT)) & ENETC_SI_SITXIDR0_TXF6_MASK) #define ENETC_SI_SITXIDR0_TXF7_MASK (0x800000U) #define ENETC_SI_SITXIDR0_TXF7_SHIFT (23U) #define ENETC_SI_SITXIDR0_TXF7(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF7_SHIFT)) & ENETC_SI_SITXIDR0_TXF7_MASK) #define ENETC_SI_SITXIDR0_TXF8_MASK (0x1000000U) #define ENETC_SI_SITXIDR0_TXF8_SHIFT (24U) #define ENETC_SI_SITXIDR0_TXF8(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF8_SHIFT)) & ENETC_SI_SITXIDR0_TXF8_MASK) #define ENETC_SI_SITXIDR0_TXF9_MASK (0x2000000U) #define ENETC_SI_SITXIDR0_TXF9_SHIFT (25U) #define ENETC_SI_SITXIDR0_TXF9(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF9_SHIFT)) & ENETC_SI_SITXIDR0_TXF9_MASK) #define ENETC_SI_SITXIDR0_TXF10_MASK (0x4000000U) #define ENETC_SI_SITXIDR0_TXF10_SHIFT (26U) #define ENETC_SI_SITXIDR0_TXF10(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF10_SHIFT)) & ENETC_SI_SITXIDR0_TXF10_MASK) #define ENETC_SI_SITXIDR0_TXF11_MASK (0x8000000U) #define ENETC_SI_SITXIDR0_TXF11_SHIFT (27U) #define ENETC_SI_SITXIDR0_TXF11(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF11_SHIFT)) & ENETC_SI_SITXIDR0_TXF11_MASK) #define ENETC_SI_SITXIDR0_TXF12_MASK (0x10000000U) #define ENETC_SI_SITXIDR0_TXF12_SHIFT (28U) #define ENETC_SI_SITXIDR0_TXF12(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF12_SHIFT)) & ENETC_SI_SITXIDR0_TXF12_MASK) #define ENETC_SI_SITXIDR0_TXF13_MASK (0x20000000U) #define ENETC_SI_SITXIDR0_TXF13_SHIFT (29U) #define ENETC_SI_SITXIDR0_TXF13(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF13_SHIFT)) & ENETC_SI_SITXIDR0_TXF13_MASK) #define ENETC_SI_SITXIDR0_TXF14_MASK (0x40000000U) #define ENETC_SI_SITXIDR0_TXF14_SHIFT (30U) #define ENETC_SI_SITXIDR0_TXF14(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF14_SHIFT)) & ENETC_SI_SITXIDR0_TXF14_MASK) #define ENETC_SI_SITXIDR0_TXF15_MASK (0x80000000U) #define ENETC_SI_SITXIDR0_TXF15_SHIFT (31U) #define ENETC_SI_SITXIDR0_TXF15(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR0_TXF15_SHIFT)) & ENETC_SI_SITXIDR0_TXF15_MASK) /*! @} */ /*! @name SITXIDR1 - Station interface transmit interrupt detect register 1 */ /*! @{ */ #define ENETC_SI_SITXIDR1_TXT16_MASK (0x1U) #define ENETC_SI_SITXIDR1_TXT16_SHIFT (0U) #define ENETC_SI_SITXIDR1_TXT16(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT16_SHIFT)) & ENETC_SI_SITXIDR1_TXT16_MASK) #define ENETC_SI_SITXIDR1_TXT17_MASK (0x2U) #define ENETC_SI_SITXIDR1_TXT17_SHIFT (1U) #define ENETC_SI_SITXIDR1_TXT17(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT17_SHIFT)) & ENETC_SI_SITXIDR1_TXT17_MASK) #define ENETC_SI_SITXIDR1_TXT18_MASK (0x4U) #define ENETC_SI_SITXIDR1_TXT18_SHIFT (2U) #define ENETC_SI_SITXIDR1_TXT18(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT18_SHIFT)) & ENETC_SI_SITXIDR1_TXT18_MASK) #define ENETC_SI_SITXIDR1_TXT19_MASK (0x8U) #define ENETC_SI_SITXIDR1_TXT19_SHIFT (3U) #define ENETC_SI_SITXIDR1_TXT19(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT19_SHIFT)) & ENETC_SI_SITXIDR1_TXT19_MASK) #define ENETC_SI_SITXIDR1_TXT20_MASK (0x10U) #define ENETC_SI_SITXIDR1_TXT20_SHIFT (4U) #define ENETC_SI_SITXIDR1_TXT20(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT20_SHIFT)) & ENETC_SI_SITXIDR1_TXT20_MASK) #define ENETC_SI_SITXIDR1_TXT21_MASK (0x20U) #define ENETC_SI_SITXIDR1_TXT21_SHIFT (5U) #define ENETC_SI_SITXIDR1_TXT21(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT21_SHIFT)) & ENETC_SI_SITXIDR1_TXT21_MASK) #define ENETC_SI_SITXIDR1_TXT22_MASK (0x40U) #define ENETC_SI_SITXIDR1_TXT22_SHIFT (6U) #define ENETC_SI_SITXIDR1_TXT22(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT22_SHIFT)) & ENETC_SI_SITXIDR1_TXT22_MASK) #define ENETC_SI_SITXIDR1_TXT23_MASK (0x80U) #define ENETC_SI_SITXIDR1_TXT23_SHIFT (7U) #define ENETC_SI_SITXIDR1_TXT23(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXT23_SHIFT)) & ENETC_SI_SITXIDR1_TXT23_MASK) #define ENETC_SI_SITXIDR1_TXF16_MASK (0x10000U) #define ENETC_SI_SITXIDR1_TXF16_SHIFT (16U) #define ENETC_SI_SITXIDR1_TXF16(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF16_SHIFT)) & ENETC_SI_SITXIDR1_TXF16_MASK) #define ENETC_SI_SITXIDR1_TXF17_MASK (0x20000U) #define ENETC_SI_SITXIDR1_TXF17_SHIFT (17U) #define ENETC_SI_SITXIDR1_TXF17(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF17_SHIFT)) & ENETC_SI_SITXIDR1_TXF17_MASK) #define ENETC_SI_SITXIDR1_TXF18_MASK (0x40000U) #define ENETC_SI_SITXIDR1_TXF18_SHIFT (18U) #define ENETC_SI_SITXIDR1_TXF18(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF18_SHIFT)) & ENETC_SI_SITXIDR1_TXF18_MASK) #define ENETC_SI_SITXIDR1_TXF19_MASK (0x80000U) #define ENETC_SI_SITXIDR1_TXF19_SHIFT (19U) #define ENETC_SI_SITXIDR1_TXF19(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF19_SHIFT)) & ENETC_SI_SITXIDR1_TXF19_MASK) #define ENETC_SI_SITXIDR1_TXF20_MASK (0x100000U) #define ENETC_SI_SITXIDR1_TXF20_SHIFT (20U) #define ENETC_SI_SITXIDR1_TXF20(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF20_SHIFT)) & ENETC_SI_SITXIDR1_TXF20_MASK) #define ENETC_SI_SITXIDR1_TXF21_MASK (0x200000U) #define ENETC_SI_SITXIDR1_TXF21_SHIFT (21U) #define ENETC_SI_SITXIDR1_TXF21(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF21_SHIFT)) & ENETC_SI_SITXIDR1_TXF21_MASK) #define ENETC_SI_SITXIDR1_TXF22_MASK (0x400000U) #define ENETC_SI_SITXIDR1_TXF22_SHIFT (22U) #define ENETC_SI_SITXIDR1_TXF22(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF22_SHIFT)) & ENETC_SI_SITXIDR1_TXF22_MASK) #define ENETC_SI_SITXIDR1_TXF23_MASK (0x800000U) #define ENETC_SI_SITXIDR1_TXF23_SHIFT (23U) #define ENETC_SI_SITXIDR1_TXF23(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITXIDR1_TXF23_SHIFT)) & ENETC_SI_SITXIDR1_TXF23_MASK) /*! @} */ /*! @name SIRXIDR0 - Station interface receive interrupt detect register 0 */ /*! @{ */ #define ENETC_SI_SIRXIDR0_RX0_MASK (0x1U) #define ENETC_SI_SIRXIDR0_RX0_SHIFT (0U) #define ENETC_SI_SIRXIDR0_RX0(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX0_SHIFT)) & ENETC_SI_SIRXIDR0_RX0_MASK) #define ENETC_SI_SIRXIDR0_RX1_MASK (0x2U) #define ENETC_SI_SIRXIDR0_RX1_SHIFT (1U) #define ENETC_SI_SIRXIDR0_RX1(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX1_SHIFT)) & ENETC_SI_SIRXIDR0_RX1_MASK) #define ENETC_SI_SIRXIDR0_RX2_MASK (0x4U) #define ENETC_SI_SIRXIDR0_RX2_SHIFT (2U) #define ENETC_SI_SIRXIDR0_RX2(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX2_SHIFT)) & ENETC_SI_SIRXIDR0_RX2_MASK) #define ENETC_SI_SIRXIDR0_RX3_MASK (0x8U) #define ENETC_SI_SIRXIDR0_RX3_SHIFT (3U) #define ENETC_SI_SIRXIDR0_RX3(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX3_SHIFT)) & ENETC_SI_SIRXIDR0_RX3_MASK) #define ENETC_SI_SIRXIDR0_RX4_MASK (0x10U) #define ENETC_SI_SIRXIDR0_RX4_SHIFT (4U) #define ENETC_SI_SIRXIDR0_RX4(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX4_SHIFT)) & ENETC_SI_SIRXIDR0_RX4_MASK) #define ENETC_SI_SIRXIDR0_RX5_MASK (0x20U) #define ENETC_SI_SIRXIDR0_RX5_SHIFT (5U) #define ENETC_SI_SIRXIDR0_RX5(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX5_SHIFT)) & ENETC_SI_SIRXIDR0_RX5_MASK) #define ENETC_SI_SIRXIDR0_RX6_MASK (0x40U) #define ENETC_SI_SIRXIDR0_RX6_SHIFT (6U) #define ENETC_SI_SIRXIDR0_RX6(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX6_SHIFT)) & ENETC_SI_SIRXIDR0_RX6_MASK) #define ENETC_SI_SIRXIDR0_RX7_MASK (0x80U) #define ENETC_SI_SIRXIDR0_RX7_SHIFT (7U) #define ENETC_SI_SIRXIDR0_RX7(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX7_SHIFT)) & ENETC_SI_SIRXIDR0_RX7_MASK) #define ENETC_SI_SIRXIDR0_RX8_MASK (0x100U) #define ENETC_SI_SIRXIDR0_RX8_SHIFT (8U) #define ENETC_SI_SIRXIDR0_RX8(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX8_SHIFT)) & ENETC_SI_SIRXIDR0_RX8_MASK) #define ENETC_SI_SIRXIDR0_RX9_MASK (0x200U) #define ENETC_SI_SIRXIDR0_RX9_SHIFT (9U) #define ENETC_SI_SIRXIDR0_RX9(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX9_SHIFT)) & ENETC_SI_SIRXIDR0_RX9_MASK) #define ENETC_SI_SIRXIDR0_RX10_MASK (0x400U) #define ENETC_SI_SIRXIDR0_RX10_SHIFT (10U) #define ENETC_SI_SIRXIDR0_RX10(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX10_SHIFT)) & ENETC_SI_SIRXIDR0_RX10_MASK) #define ENETC_SI_SIRXIDR0_RX11_MASK (0x800U) #define ENETC_SI_SIRXIDR0_RX11_SHIFT (11U) #define ENETC_SI_SIRXIDR0_RX11(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX11_SHIFT)) & ENETC_SI_SIRXIDR0_RX11_MASK) #define ENETC_SI_SIRXIDR0_RX12_MASK (0x1000U) #define ENETC_SI_SIRXIDR0_RX12_SHIFT (12U) #define ENETC_SI_SIRXIDR0_RX12(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX12_SHIFT)) & ENETC_SI_SIRXIDR0_RX12_MASK) #define ENETC_SI_SIRXIDR0_RX13_MASK (0x2000U) #define ENETC_SI_SIRXIDR0_RX13_SHIFT (13U) #define ENETC_SI_SIRXIDR0_RX13(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX13_SHIFT)) & ENETC_SI_SIRXIDR0_RX13_MASK) #define ENETC_SI_SIRXIDR0_RX14_MASK (0x4000U) #define ENETC_SI_SIRXIDR0_RX14_SHIFT (14U) #define ENETC_SI_SIRXIDR0_RX14(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX14_SHIFT)) & ENETC_SI_SIRXIDR0_RX14_MASK) #define ENETC_SI_SIRXIDR0_RX15_MASK (0x8000U) #define ENETC_SI_SIRXIDR0_RX15_SHIFT (15U) #define ENETC_SI_SIRXIDR0_RX15(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX15_SHIFT)) & ENETC_SI_SIRXIDR0_RX15_MASK) #define ENETC_SI_SIRXIDR0_RX16_MASK (0x10000U) #define ENETC_SI_SIRXIDR0_RX16_SHIFT (16U) #define ENETC_SI_SIRXIDR0_RX16(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX16_SHIFT)) & ENETC_SI_SIRXIDR0_RX16_MASK) #define ENETC_SI_SIRXIDR0_RX17_MASK (0x20000U) #define ENETC_SI_SIRXIDR0_RX17_SHIFT (17U) #define ENETC_SI_SIRXIDR0_RX17(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX17_SHIFT)) & ENETC_SI_SIRXIDR0_RX17_MASK) #define ENETC_SI_SIRXIDR0_RX18_MASK (0x40000U) #define ENETC_SI_SIRXIDR0_RX18_SHIFT (18U) #define ENETC_SI_SIRXIDR0_RX18(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX18_SHIFT)) & ENETC_SI_SIRXIDR0_RX18_MASK) #define ENETC_SI_SIRXIDR0_RX19_MASK (0x80000U) #define ENETC_SI_SIRXIDR0_RX19_SHIFT (19U) #define ENETC_SI_SIRXIDR0_RX19(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX19_SHIFT)) & ENETC_SI_SIRXIDR0_RX19_MASK) #define ENETC_SI_SIRXIDR0_RX20_MASK (0x100000U) #define ENETC_SI_SIRXIDR0_RX20_SHIFT (20U) #define ENETC_SI_SIRXIDR0_RX20(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX20_SHIFT)) & ENETC_SI_SIRXIDR0_RX20_MASK) #define ENETC_SI_SIRXIDR0_RX21_MASK (0x200000U) #define ENETC_SI_SIRXIDR0_RX21_SHIFT (21U) #define ENETC_SI_SIRXIDR0_RX21(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX21_SHIFT)) & ENETC_SI_SIRXIDR0_RX21_MASK) #define ENETC_SI_SIRXIDR0_RX22_MASK (0x400000U) #define ENETC_SI_SIRXIDR0_RX22_SHIFT (22U) #define ENETC_SI_SIRXIDR0_RX22(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX22_SHIFT)) & ENETC_SI_SIRXIDR0_RX22_MASK) #define ENETC_SI_SIRXIDR0_RX23_MASK (0x800000U) #define ENETC_SI_SIRXIDR0_RX23_SHIFT (23U) #define ENETC_SI_SIRXIDR0_RX23(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRXIDR0_RX23_SHIFT)) & ENETC_SI_SIRXIDR0_RX23_MASK) /*! @} */ /*! @name SIMSIVR - Station interface MSI-X vector register */ /*! @{ */ #define ENETC_SI_SIMSIVR_VECTOR_MASK (0x3FU) #define ENETC_SI_SIMSIVR_VECTOR_SHIFT (0U) #define ENETC_SI_SIMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMSIVR_VECTOR_SHIFT)) & ENETC_SI_SIMSIVR_VECTOR_MASK) /*! @} */ /*! @name SICMSIVR - Station interface command MSI-X vector register */ /*! @{ */ #define ENETC_SI_SICMSIVR_VECTOR_MASK (0x3FU) #define ENETC_SI_SICMSIVR_VECTOR_SHIFT (0U) #define ENETC_SI_SICMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMSIVR_VECTOR_SHIFT)) & ENETC_SI_SICMSIVR_VECTOR_MASK) /*! @} */ /*! @name SITMRIER - Station interface timer interrupt enable register */ /*! @{ */ #define ENETC_SI_SITMRIER_SYNCE_MASK (0x1U) #define ENETC_SI_SITMRIER_SYNCE_SHIFT (0U) #define ENETC_SI_SITMRIER_SYNCE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMRIER_SYNCE_SHIFT)) & ENETC_SI_SITMRIER_SYNCE_MASK) /*! @} */ /*! @name SITMRIDR - Station interface timer interrupt detect register */ /*! @{ */ #define ENETC_SI_SITMRIDR_SYNC_MASK (0x1U) #define ENETC_SI_SITMRIDR_SYNC_SHIFT (0U) #define ENETC_SI_SITMRIDR_SYNC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMRIDR_SYNC_SHIFT)) & ENETC_SI_SITMRIDR_SYNC_MASK) /*! @} */ /*! @name SITMRMSIVR - Station interface timer MSI-X vector register */ /*! @{ */ #define ENETC_SI_SITMRMSIVR_VECTOR_MASK (0x3FU) #define ENETC_SI_SITMRMSIVR_VECTOR_SHIFT (0U) #define ENETC_SI_SITMRMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SITMRMSIVR_VECTOR_SHIFT)) & ENETC_SI_SITMRMSIVR_VECTOR_MASK) /*! @} */ /*! @name SIMSITRVR - Station interface MSI-X transmit ring 0 vector register..Station interface MSI-X transmit ring 7 vector register */ /*! @{ */ #define ENETC_SI_SIMSITRVR_VECTOR_MASK (0x3FU) #define ENETC_SI_SIMSITRVR_VECTOR_SHIFT (0U) #define ENETC_SI_SIMSITRVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMSITRVR_VECTOR_SHIFT)) & ENETC_SI_SIMSITRVR_VECTOR_MASK) /*! @} */ /* The count of ENETC_SI_SIMSITRVR */ #define ENETC_SI_SIMSITRVR_COUNT (8U) /*! @name SIMSIRRVR - Station interface MSI-X receive ring 0 vector register..Station interface MSI-X receive ring 7 vector register */ /*! @{ */ #define ENETC_SI_SIMSIRRVR_VECTOR_MASK (0x3FU) #define ENETC_SI_SIMSIRRVR_VECTOR_SHIFT (0U) #define ENETC_SI_SIMSIRRVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMSIRRVR_VECTOR_SHIFT)) & ENETC_SI_SIMSIRRVR_VECTOR_MASK) /*! @} */ /* The count of ENETC_SI_SIMSIRRVR */ #define ENETC_SI_SIMSIRRVR_COUNT (8U) /*! @name SICMECR - Station interface correctable memory error configuration register */ /*! @{ */ #define ENETC_SI_SICMECR_THRESHOLD_MASK (0xFFU) #define ENETC_SI_SICMECR_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define ENETC_SI_SICMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMECR_THRESHOLD_SHIFT)) & ENETC_SI_SICMECR_THRESHOLD_MASK) /*! @} */ /*! @name SICMESR - Station interface correctable memory error status register */ /*! @{ */ #define ENETC_SI_SICMESR_LINK_SLICE_ID_MASK (0x1FU) #define ENETC_SI_SICMESR_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define ENETC_SI_SICMESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMESR_LINK_SLICE_ID_SHIFT)) & ENETC_SI_SICMESR_LINK_SLICE_ID_MASK) #define ENETC_SI_SICMESR_MEM_ID_MASK (0x1F00U) #define ENETC_SI_SICMESR_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define ENETC_SI_SICMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMESR_MEM_ID_SHIFT)) & ENETC_SI_SICMESR_MEM_ID_MASK) #define ENETC_SI_SICMESR_SBEE_MASK (0x80000000U) #define ENETC_SI_SICMESR_SBEE_SHIFT (31U) /*! SBEE - Single-bit ECC error */ #define ENETC_SI_SICMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMESR_SBEE_SHIFT)) & ENETC_SI_SICMESR_SBEE_MASK) /*! @} */ /*! @name SICMECTR - Station interface correctable memory error count register */ /*! @{ */ #define ENETC_SI_SICMECTR_COUNT_MASK (0xFFU) #define ENETC_SI_SICMECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENETC_SI_SICMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SICMECTR_COUNT_SHIFT)) & ENETC_SI_SICMECTR_COUNT_MASK) /*! @} */ /*! @name SIUPECR - Station interface uncorrectable programming error configuration register */ /*! @{ */ #define ENETC_SI_SIUPECR_RD_MASK (0x80000000U) #define ENETC_SI_SIUPECR_RD_SHIFT (31U) /*! RD - Report disable */ #define ENETC_SI_SIUPECR_RD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPECR_RD_SHIFT)) & ENETC_SI_SIUPECR_RD_MASK) /*! @} */ /*! @name SIUPESR - Station interface uncorrectable programming error status register */ /*! @{ */ #define ENETC_SI_SIUPESR_DROP_SI_EN_MASK (0x1U) #define ENETC_SI_SIUPESR_DROP_SI_EN_SHIFT (0U) #define ENETC_SI_SIUPESR_DROP_SI_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_DROP_SI_EN_SHIFT)) & ENETC_SI_SIUPESR_DROP_SI_EN_MASK) #define ENETC_SI_SIUPESR_DROP_RING_EN_MASK (0x2U) #define ENETC_SI_SIUPESR_DROP_RING_EN_SHIFT (1U) #define ENETC_SI_SIUPESR_DROP_RING_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_DROP_RING_EN_SHIFT)) & ENETC_SI_SIUPESR_DROP_RING_EN_MASK) #define ENETC_SI_SIUPESR_DROP_GRP_SEL_MASK (0x4U) #define ENETC_SI_SIUPESR_DROP_GRP_SEL_SHIFT (2U) #define ENETC_SI_SIUPESR_DROP_GRP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_DROP_GRP_SEL_SHIFT)) & ENETC_SI_SIUPESR_DROP_GRP_SEL_MASK) #define ENETC_SI_SIUPESR_DROP_RING_SEL_MASK (0x8U) #define ENETC_SI_SIUPESR_DROP_RING_SEL_SHIFT (3U) #define ENETC_SI_SIUPESR_DROP_RING_SEL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_DROP_RING_SEL_SHIFT)) & ENETC_SI_SIUPESR_DROP_RING_SEL_MASK) #define ENETC_SI_SIUPESR_M_MASK (0x40000000U) #define ENETC_SI_SIUPESR_M_SHIFT (30U) /*! M - Multiple */ #define ENETC_SI_SIUPESR_M(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_M_SHIFT)) & ENETC_SI_SIUPESR_M_MASK) #define ENETC_SI_SIUPESR_PE_MASK (0x80000000U) #define ENETC_SI_SIUPESR_PE_SHIFT (31U) /*! PE - Programming error */ #define ENETC_SI_SIUPESR_PE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPESR_PE_SHIFT)) & ENETC_SI_SIUPESR_PE_MASK) /*! @} */ /*! @name SIUPECTR - Station interface uncorrectable programming error count register */ /*! @{ */ #define ENETC_SI_SIUPECTR_COUNT_MASK (0xFFFFFFFFU) #define ENETC_SI_SIUPECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENETC_SI_SIUPECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUPECTR_COUNT_SHIFT)) & ENETC_SI_SIUPECTR_COUNT_MASK) /*! @} */ /*! @name SIUNSBECR - Station interface uncorrectable non-fatal system bus error configuration register */ /*! @{ */ #define ENETC_SI_SIUNSBECR_THRESHOLD_MASK (0xFFU) #define ENETC_SI_SIUNSBECR_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define ENETC_SI_SIUNSBECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBECR_THRESHOLD_SHIFT)) & ENETC_SI_SIUNSBECR_THRESHOLD_MASK) /*! @} */ /*! @name SIUNSBESR - Station interface uncorrectable non-fatal system bus error status register */ /*! @{ */ #define ENETC_SI_SIUNSBESR_SB_ID_MASK (0xF00U) #define ENETC_SI_SIUNSBESR_SB_ID_SHIFT (8U) /*! SB_ID - System Bus ID */ #define ENETC_SI_SIUNSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBESR_SB_ID_SHIFT)) & ENETC_SI_SIUNSBESR_SB_ID_MASK) #define ENETC_SI_SIUNSBESR_SBE_MASK (0x80000000U) #define ENETC_SI_SIUNSBESR_SBE_SHIFT (31U) /*! SBE - System bus error */ #define ENETC_SI_SIUNSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBESR_SBE_SHIFT)) & ENETC_SI_SIUNSBESR_SBE_MASK) /*! @} */ /*! @name SIUNSBECTR - Station interface uncorrectable non-fatal system bus error count register */ /*! @{ */ #define ENETC_SI_SIUNSBECTR_COUNT_MASK (0xFFU) #define ENETC_SI_SIUNSBECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENETC_SI_SIUNSBECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNSBECTR_COUNT_SHIFT)) & ENETC_SI_SIUNSBECTR_COUNT_MASK) /*! @} */ /*! @name SIUFSBECR - Station interface uncorrectable fatal system bus error configuration register */ /*! @{ */ #define ENETC_SI_SIUFSBECR_RD_MASK (0x80000000U) #define ENETC_SI_SIUFSBECR_RD_SHIFT (31U) /*! RD - Report disable */ #define ENETC_SI_SIUFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBECR_RD_SHIFT)) & ENETC_SI_SIUFSBECR_RD_MASK) /*! @} */ /*! @name SIUFSBESR - Station interface uncorrectable fatal system bus error status register */ /*! @{ */ #define ENETC_SI_SIUFSBESR_SB_ID_MASK (0xF00U) #define ENETC_SI_SIUFSBESR_SB_ID_SHIFT (8U) /*! SB_ID - System Bus ID */ #define ENETC_SI_SIUFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBESR_SB_ID_SHIFT)) & ENETC_SI_SIUFSBESR_SB_ID_MASK) #define ENETC_SI_SIUFSBESR_M_MASK (0x40000000U) #define ENETC_SI_SIUFSBESR_M_SHIFT (30U) /*! M - Multiple */ #define ENETC_SI_SIUFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBESR_M_SHIFT)) & ENETC_SI_SIUFSBESR_M_MASK) #define ENETC_SI_SIUFSBESR_SBE_MASK (0x80000000U) #define ENETC_SI_SIUFSBESR_SBE_SHIFT (31U) /*! SBE - System bus error */ #define ENETC_SI_SIUFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFSBESR_SBE_SHIFT)) & ENETC_SI_SIUFSBESR_SBE_MASK) /*! @} */ /*! @name SIUNMECR - Station interface uncorrectable non-fatal memory error configuration register */ /*! @{ */ #define ENETC_SI_SIUNMECR_THRESHOLD_MASK (0xFFU) #define ENETC_SI_SIUNMECR_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define ENETC_SI_SIUNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMECR_THRESHOLD_SHIFT)) & ENETC_SI_SIUNMECR_THRESHOLD_MASK) #define ENETC_SI_SIUNMECR_RD_MASK (0x80000000U) #define ENETC_SI_SIUNMECR_RD_SHIFT (31U) /*! RD - Report disable */ #define ENETC_SI_SIUNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMECR_RD_SHIFT)) & ENETC_SI_SIUNMECR_RD_MASK) /*! @} */ /*! @name SIUNMESR0 - Station interface uncorrectable non-fatal memory error status register 0 */ /*! @{ */ #define ENETC_SI_SIUNMESR0_MEM_ID_MASK (0x1F00U) #define ENETC_SI_SIUNMESR0_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define ENETC_SI_SIUNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR0_MEM_ID_SHIFT)) & ENETC_SI_SIUNMESR0_MEM_ID_MASK) #define ENETC_SI_SIUNMESR0_SYNDROME_MASK (0x7FF0000U) #define ENETC_SI_SIUNMESR0_SYNDROME_SHIFT (16U) /*! SYNDROME - Syndrome */ #define ENETC_SI_SIUNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR0_SYNDROME_SHIFT)) & ENETC_SI_SIUNMESR0_SYNDROME_MASK) #define ENETC_SI_SIUNMESR0_MBEE_MASK (0x80000000U) #define ENETC_SI_SIUNMESR0_MBEE_SHIFT (31U) /*! MBEE - Multi-bit ECC error */ #define ENETC_SI_SIUNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR0_MBEE_SHIFT)) & ENETC_SI_SIUNMESR0_MBEE_MASK) /*! @} */ /*! @name SIUNMESR1 - Station interface uncorrectable non-fatal memory error status register 1 */ /*! @{ */ #define ENETC_SI_SIUNMESR1_ADDR_MASK (0xFFFFFFFFU) #define ENETC_SI_SIUNMESR1_ADDR_SHIFT (0U) /*! ADDR - Address */ #define ENETC_SI_SIUNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMESR1_ADDR_SHIFT)) & ENETC_SI_SIUNMESR1_ADDR_MASK) /*! @} */ /*! @name SIUNMECTR - Station interface uncorrectable non-fatal memory error count register */ /*! @{ */ #define ENETC_SI_SIUNMECTR_COUNT_MASK (0xFFU) #define ENETC_SI_SIUNMECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define ENETC_SI_SIUNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUNMECTR_COUNT_SHIFT)) & ENETC_SI_SIUNMECTR_COUNT_MASK) /*! @} */ /*! @name SIUFMECR - Station interface uncorrectable fatal memory error configuration register */ /*! @{ */ #define ENETC_SI_SIUFMECR_RD_MASK (0x80000000U) #define ENETC_SI_SIUFMECR_RD_SHIFT (31U) /*! RD - Report disable */ #define ENETC_SI_SIUFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMECR_RD_SHIFT)) & ENETC_SI_SIUFMECR_RD_MASK) /*! @} */ /*! @name SIUFMESR0 - Station interface uncorrectable fatal memory error status register 0 */ /*! @{ */ #define ENETC_SI_SIUFMESR0_LINK_SLICE_ID_MASK (0x1FU) #define ENETC_SI_SIUFMESR0_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define ENETC_SI_SIUFMESR0_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_LINK_SLICE_ID_SHIFT)) & ENETC_SI_SIUFMESR0_LINK_SLICE_ID_MASK) #define ENETC_SI_SIUFMESR0_MEM_ID_MASK (0x1F00U) #define ENETC_SI_SIUFMESR0_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define ENETC_SI_SIUFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_MEM_ID_SHIFT)) & ENETC_SI_SIUFMESR0_MEM_ID_MASK) #define ENETC_SI_SIUFMESR0_SYNDROME_MASK (0x7FF0000U) #define ENETC_SI_SIUFMESR0_SYNDROME_SHIFT (16U) /*! SYNDROME - Syndrome */ #define ENETC_SI_SIUFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_SYNDROME_SHIFT)) & ENETC_SI_SIUFMESR0_SYNDROME_MASK) #define ENETC_SI_SIUFMESR0_M_MASK (0x40000000U) #define ENETC_SI_SIUFMESR0_M_SHIFT (30U) /*! M - Multiple */ #define ENETC_SI_SIUFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_M_SHIFT)) & ENETC_SI_SIUFMESR0_M_MASK) #define ENETC_SI_SIUFMESR0_MBEE_MASK (0x80000000U) #define ENETC_SI_SIUFMESR0_MBEE_SHIFT (31U) /*! MBEE - Multi-bit ECC error */ #define ENETC_SI_SIUFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR0_MBEE_SHIFT)) & ENETC_SI_SIUFMESR0_MBEE_MASK) /*! @} */ /*! @name SIUFMESR1 - Station interface uncorrectable fatal memory error status register 1 */ /*! @{ */ #define ENETC_SI_SIUFMESR1_ADDR_MASK (0xFFFFFFFFU) #define ENETC_SI_SIUFMESR1_ADDR_SHIFT (0U) /*! ADDR - Address */ #define ENETC_SI_SIUFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIUFMESR1_ADDR_SHIFT)) & ENETC_SI_SIUFMESR1_ADDR_MASK) /*! @} */ /*! @name SIMAFTCAPR - Station interface MAC address filter table capability register */ /*! @{ */ #define ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_MASK (0xFFU) #define ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT (0U) #define ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_SHIFT)) & ENETC_SI_SIMAFTCAPR_NUM_MAC_AFTE_MASK) /*! @} */ /*! @name SIVFTCAPR - Station interface VLAN filter table capability register */ /*! @{ */ #define ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_MASK (0xFFU) #define ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_SHIFT (0U) #define ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_SHIFT)) & ENETC_SI_SIVFTCAPR_NUM_VLAN_FTE_MASK) /*! @} */ /*! @name SILSOSFMR0 - Station interface LSO segmentation flag mask register 0 */ /*! @{ */ #define ENETC_SI_SILSOSFMR0_TCP_1ST_SEG_MASK (0xFFFU) #define ENETC_SI_SILSOSFMR0_TCP_1ST_SEG_SHIFT (0U) #define ENETC_SI_SILSOSFMR0_TCP_1ST_SEG(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SILSOSFMR0_TCP_1ST_SEG_SHIFT)) & ENETC_SI_SILSOSFMR0_TCP_1ST_SEG_MASK) #define ENETC_SI_SILSOSFMR0_TCP_MID_SEG_MASK (0xFFF0000U) #define ENETC_SI_SILSOSFMR0_TCP_MID_SEG_SHIFT (16U) #define ENETC_SI_SILSOSFMR0_TCP_MID_SEG(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SILSOSFMR0_TCP_MID_SEG_SHIFT)) & ENETC_SI_SILSOSFMR0_TCP_MID_SEG_MASK) /*! @} */ /*! @name SILSOSFMR1 - Station interface LSO segmentation flag mask register 1 */ /*! @{ */ #define ENETC_SI_SILSOSFMR1_TCP_LAST_SEG_MASK (0xFFFU) #define ENETC_SI_SILSOSFMR1_TCP_LAST_SEG_SHIFT (0U) #define ENETC_SI_SILSOSFMR1_TCP_LAST_SEG(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SILSOSFMR1_TCP_LAST_SEG_SHIFT)) & ENETC_SI_SILSOSFMR1_TCP_LAST_SEG_MASK) /*! @} */ /*! @name SIRSSCAPR - Station interface RSS capability register */ /*! @{ */ #define ENETC_SI_SIRSSCAPR_NUM_RSS_MASK (0xFU) #define ENETC_SI_SIRSSCAPR_NUM_RSS_SHIFT (0U) #define ENETC_SI_SIRSSCAPR_NUM_RSS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_SIRSSCAPR_NUM_RSS_SHIFT)) & ENETC_SI_SIRSSCAPR_NUM_RSS_MASK) /*! @} */ /*! @name TBMR - Tx BDR 0 mode register..Tx BDR 7 mode register */ /*! @{ */ #define ENETC_SI_TBMR_PRIO_MASK (0x7U) #define ENETC_SI_TBMR_PRIO_SHIFT (0U) /*! PRIO - Priority * 0b000..Lowest priority * 0b001..Next lowest priority * 0b010..Next lowest priority * 0b011..Next lowest priority * 0b100..Next lowest priority * 0b101..Next highest priority * 0b110..Next highest priority * 0b111..Highest priority */ #define ENETC_SI_TBMR_PRIO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_PRIO_SHIFT)) & ENETC_SI_TBMR_PRIO_MASK) #define ENETC_SI_TBMR_WRR_MASK (0x70U) #define ENETC_SI_TBMR_WRR_SHIFT (4U) /*! WRR - Weighted Round Robin (WRR) * 0b000..Weight of 1 * 0b001..Weight of 2 * 0b010..Weight of 3 * 0b011..Weight of 4 * 0b100..Weight of 5 * 0b101..Weight of 6 * 0b110..Weight of 7 * 0b111..Weight of 8 */ #define ENETC_SI_TBMR_WRR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_WRR_SHIFT)) & ENETC_SI_TBMR_WRR_MASK) #define ENETC_SI_TBMR_CRC_MASK (0x100U) #define ENETC_SI_TBMR_CRC_SHIFT (8U) /*! CRC - Cyclic Redundancy Check (CRC) * 0b0..FCS is not present in the frame provided by SW (calculated and appended by the HW). * 0b1..FCS is present in the frame provided by SW. */ #define ENETC_SI_TBMR_CRC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_CRC_SHIFT)) & ENETC_SI_TBMR_CRC_MASK) #define ENETC_SI_TBMR_VIH_MASK (0x200U) #define ENETC_SI_TBMR_VIH_SHIFT (9U) /*! VIH - VLAN Insert Hint * 0b0..Calculations performed by HW in the transmit scheduler will not account for the extra 4 bytes of the VLAN * tag added to the frame when descriptor-based VLAN insertion offload is used. * 0b1..Calculations performed by HW in the transmit scheduler involving the size of the frame will always * account for an extra 4 bytes to the frame regardless of whether descriptor-based VLAN insertion offload is used * or not. */ #define ENETC_SI_TBMR_VIH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_VIH_SHIFT)) & ENETC_SI_TBMR_VIH_MASK) #define ENETC_SI_TBMR_FWB_MASK (0x1000000U) #define ENETC_SI_TBMR_FWB_SHIFT (24U) /*! FWB - Force Writeback * 0b0..Disabled. * 0b1..Enabled. */ #define ENETC_SI_TBMR_FWB(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_FWB_SHIFT)) & ENETC_SI_TBMR_FWB_MASK) #define ENETC_SI_TBMR_EN_MASK (0x80000000U) #define ENETC_SI_TBMR_EN_SHIFT (31U) /*! EN - Enables and disables the Tx BD ring. * 0b0..Disabled. * 0b1..Enabled. When the ring is non-empty, transmit packets will be processed. */ #define ENETC_SI_TBMR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBMR_EN_SHIFT)) & ENETC_SI_TBMR_EN_MASK) /*! @} */ /* The count of ENETC_SI_TBMR */ #define ENETC_SI_TBMR_COUNT (8U) /*! @name TBSR - Tx BDR 0 status register..Tx BDR 7 status register */ /*! @{ */ #define ENETC_SI_TBSR_BUSY_MASK (0x1U) #define ENETC_SI_TBSR_BUSY_SHIFT (0U) #define ENETC_SI_TBSR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBSR_BUSY_SHIFT)) & ENETC_SI_TBSR_BUSY_MASK) #define ENETC_SI_TBSR_SBE_MASK (0x10000U) #define ENETC_SI_TBSR_SBE_SHIFT (16U) #define ENETC_SI_TBSR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBSR_SBE_SHIFT)) & ENETC_SI_TBSR_SBE_MASK) /*! @} */ /* The count of ENETC_SI_TBSR */ #define ENETC_SI_TBSR_COUNT (8U) /*! @name TBBAR0 - Tx BDR 0 base address register 0..Tx BDR 7 base address register 0 */ /*! @{ */ #define ENETC_SI_TBBAR0_ADDRL_MASK (0xFFFFFF80U) #define ENETC_SI_TBBAR0_ADDRL_SHIFT (7U) #define ENETC_SI_TBBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBBAR0_ADDRL_SHIFT)) & ENETC_SI_TBBAR0_ADDRL_MASK) /*! @} */ /* The count of ENETC_SI_TBBAR0 */ #define ENETC_SI_TBBAR0_COUNT (8U) /*! @name TBBAR1 - Tx BDR 0 base address register 1..Tx BDR 7 base address register 1 */ /*! @{ */ #define ENETC_SI_TBBAR1_ADDRH_MASK (0xFFFFFFFFU) #define ENETC_SI_TBBAR1_ADDRH_SHIFT (0U) #define ENETC_SI_TBBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBBAR1_ADDRH_SHIFT)) & ENETC_SI_TBBAR1_ADDRH_MASK) /*! @} */ /* The count of ENETC_SI_TBBAR1 */ #define ENETC_SI_TBBAR1_COUNT (8U) /*! @name TBPIR - Tx BDR 0 producer index register..Tx BDR 7 producer index register */ /*! @{ */ #define ENETC_SI_TBPIR_BDR_INDEX_MASK (0xFFFFU) #define ENETC_SI_TBPIR_BDR_INDEX_SHIFT (0U) #define ENETC_SI_TBPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBPIR_BDR_INDEX_SHIFT)) & ENETC_SI_TBPIR_BDR_INDEX_MASK) /*! @} */ /* The count of ENETC_SI_TBPIR */ #define ENETC_SI_TBPIR_COUNT (8U) /*! @name TBCIR - Tx BDR 0 consumer index register..Tx BDR 7 consumer index register */ /*! @{ */ #define ENETC_SI_TBCIR_BDR_INDEX_MASK (0xFFFFU) #define ENETC_SI_TBCIR_BDR_INDEX_SHIFT (0U) #define ENETC_SI_TBCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBCIR_BDR_INDEX_SHIFT)) & ENETC_SI_TBCIR_BDR_INDEX_MASK) #define ENETC_SI_TBCIR_STAT_ID_MASK (0x7FFF0000U) #define ENETC_SI_TBCIR_STAT_ID_SHIFT (16U) #define ENETC_SI_TBCIR_STAT_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBCIR_STAT_ID_SHIFT)) & ENETC_SI_TBCIR_STAT_ID_MASK) #define ENETC_SI_TBCIR_SBE_MASK (0x80000000U) #define ENETC_SI_TBCIR_SBE_SHIFT (31U) #define ENETC_SI_TBCIR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBCIR_SBE_SHIFT)) & ENETC_SI_TBCIR_SBE_MASK) /*! @} */ /* The count of ENETC_SI_TBCIR */ #define ENETC_SI_TBCIR_COUNT (8U) /*! @name TBLENR - Tx BDR 0 length register..Tx BDR 7 length register */ /*! @{ */ #define ENETC_SI_TBLENR_LENGTH_MASK (0x1FFF8U) #define ENETC_SI_TBLENR_LENGTH_SHIFT (3U) #define ENETC_SI_TBLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBLENR_LENGTH_SHIFT)) & ENETC_SI_TBLENR_LENGTH_MASK) /*! @} */ /* The count of ENETC_SI_TBLENR */ #define ENETC_SI_TBLENR_COUNT (8U) /*! @name TBIER - Tx BDR 0 interrupt enable register..Tx BDR 7 interrupt enable register */ /*! @{ */ #define ENETC_SI_TBIER_TXTIE_MASK (0x1U) #define ENETC_SI_TBIER_TXTIE_SHIFT (0U) #define ENETC_SI_TBIER_TXTIE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIER_TXTIE_SHIFT)) & ENETC_SI_TBIER_TXTIE_MASK) #define ENETC_SI_TBIER_TXFIE_MASK (0x2U) #define ENETC_SI_TBIER_TXFIE_SHIFT (1U) #define ENETC_SI_TBIER_TXFIE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIER_TXFIE_SHIFT)) & ENETC_SI_TBIER_TXFIE_MASK) /*! @} */ /* The count of ENETC_SI_TBIER */ #define ENETC_SI_TBIER_COUNT (8U) /*! @name TBIDR - Tx BDR 0 interrupt detect register..Tx BDR 7 interrupt detect register */ /*! @{ */ #define ENETC_SI_TBIDR_TXT_MASK (0x1U) #define ENETC_SI_TBIDR_TXT_SHIFT (0U) #define ENETC_SI_TBIDR_TXT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIDR_TXT_SHIFT)) & ENETC_SI_TBIDR_TXT_MASK) #define ENETC_SI_TBIDR_TXF_MASK (0x2U) #define ENETC_SI_TBIDR_TXF_SHIFT (1U) #define ENETC_SI_TBIDR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBIDR_TXF_SHIFT)) & ENETC_SI_TBIDR_TXF_MASK) /*! @} */ /* The count of ENETC_SI_TBIDR */ #define ENETC_SI_TBIDR_COUNT (8U) /*! @name TBICR0 - Tx BDR 0 interrupt coalescing register 0..Tx BDR 7 interrupt coalescing register 0 */ /*! @{ */ #define ENETC_SI_TBICR0_ICPT_MASK (0xFU) #define ENETC_SI_TBICR0_ICPT_SHIFT (0U) #define ENETC_SI_TBICR0_ICPT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBICR0_ICPT_SHIFT)) & ENETC_SI_TBICR0_ICPT_MASK) #define ENETC_SI_TBICR0_ICEN_MASK (0x80000000U) #define ENETC_SI_TBICR0_ICEN_SHIFT (31U) #define ENETC_SI_TBICR0_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBICR0_ICEN_SHIFT)) & ENETC_SI_TBICR0_ICEN_MASK) /*! @} */ /* The count of ENETC_SI_TBICR0 */ #define ENETC_SI_TBICR0_COUNT (8U) /*! @name TBICR1 - Tx BDR 0 interrupt coalescing register 1..Tx BDR 7 interrupt coalescing register 1 */ /*! @{ */ #define ENETC_SI_TBICR1_ICTT_MASK (0xFFFFFFFFU) #define ENETC_SI_TBICR1_ICTT_SHIFT (0U) #define ENETC_SI_TBICR1_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_TBICR1_ICTT_SHIFT)) & ENETC_SI_TBICR1_ICTT_MASK) /*! @} */ /* The count of ENETC_SI_TBICR1 */ #define ENETC_SI_TBICR1_COUNT (8U) /*! @name RBMR - Rx BDR 0 mode register..Rx BDR 7 mode register */ /*! @{ */ #define ENETC_SI_RBMR_AL_MASK (0x1U) #define ENETC_SI_RBMR_AL_SHIFT (0U) /*! AL - Alignment * 0b0..No alignment applied * 0b1..2-byte alignment applied to the start of the frame */ #define ENETC_SI_RBMR_AL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_AL_SHIFT)) & ENETC_SI_RBMR_AL_MASK) #define ENETC_SI_RBMR_BDS_MASK (0x4U) #define ENETC_SI_RBMR_BDS_SHIFT (2U) /*! BDS - BD Size * 0b0..16B buffer descriptors format * 0b1..32B buffer descriptors format */ #define ENETC_SI_RBMR_BDS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_BDS_SHIFT)) & ENETC_SI_RBMR_BDS_MASK) #define ENETC_SI_RBMR_CM_MASK (0x10U) #define ENETC_SI_RBMR_CM_SHIFT (4U) /*! CM - Congestion mode * 0b0..Lossy * 0b1..Lossless */ #define ENETC_SI_RBMR_CM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_CM_SHIFT)) & ENETC_SI_RBMR_CM_MASK) #define ENETC_SI_RBMR_VTE_MASK (0x20U) #define ENETC_SI_RBMR_VTE_SHIFT (5U) /*! VTE - VLAN tag extract enable * 0b0..Disabled * 0b1..Enabled */ #define ENETC_SI_RBMR_VTE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_VTE_SHIFT)) & ENETC_SI_RBMR_VTE_MASK) #define ENETC_SI_RBMR_VTPD_MASK (0x40U) #define ENETC_SI_RBMR_VTPD_SHIFT (6U) /*! VTPD - VLAN tag presentation disable * 0b0..Extracted VLAN is presented * 0b1..Extracted VLAN is not presented */ #define ENETC_SI_RBMR_VTPD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_VTPD_SHIFT)) & ENETC_SI_RBMR_VTPD_MASK) #define ENETC_SI_RBMR_CRC_MASK (0x100U) #define ENETC_SI_RBMR_CRC_SHIFT (8U) /*! CRC - Cyclic Redundancy Check (CRC) * 0b0..FCS is removed * 0b1..FCS is preserved */ #define ENETC_SI_RBMR_CRC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_CRC_SHIFT)) & ENETC_SI_RBMR_CRC_MASK) #define ENETC_SI_RBMR_EN_MASK (0x80000000U) #define ENETC_SI_RBMR_EN_SHIFT (31U) /*! EN * 0b0..Disabled * 0b1..Enabled */ #define ENETC_SI_RBMR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBMR_EN_SHIFT)) & ENETC_SI_RBMR_EN_MASK) /*! @} */ /* The count of ENETC_SI_RBMR */ #define ENETC_SI_RBMR_COUNT (8U) /*! @name RBSR - Rx BDR 0 status register..Rx BDR 7 status register */ /*! @{ */ #define ENETC_SI_RBSR_EMPTY_MASK (0x1U) #define ENETC_SI_RBSR_EMPTY_SHIFT (0U) #define ENETC_SI_RBSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBSR_EMPTY_SHIFT)) & ENETC_SI_RBSR_EMPTY_MASK) #define ENETC_SI_RBSR_SBE_MASK (0x10000U) #define ENETC_SI_RBSR_SBE_SHIFT (16U) #define ENETC_SI_RBSR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBSR_SBE_SHIFT)) & ENETC_SI_RBSR_SBE_MASK) /*! @} */ /* The count of ENETC_SI_RBSR */ #define ENETC_SI_RBSR_COUNT (8U) /*! @name RBBSR - Rx BDR 0 buffer size register..Rx BDR 7 buffer size register */ /*! @{ */ #define ENETC_SI_RBBSR_BSIZE_MASK (0xFFFFU) #define ENETC_SI_RBBSR_BSIZE_SHIFT (0U) #define ENETC_SI_RBBSR_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBBSR_BSIZE_SHIFT)) & ENETC_SI_RBBSR_BSIZE_MASK) /*! @} */ /* The count of ENETC_SI_RBBSR */ #define ENETC_SI_RBBSR_COUNT (8U) /*! @name RBCIR - Rx BDR 0 consumer index register..Rx BDR 7 consumer index register */ /*! @{ */ #define ENETC_SI_RBCIR_BDR_INDEX_MASK (0xFFFFU) #define ENETC_SI_RBCIR_BDR_INDEX_SHIFT (0U) #define ENETC_SI_RBCIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBCIR_BDR_INDEX_SHIFT)) & ENETC_SI_RBCIR_BDR_INDEX_MASK) /*! @} */ /* The count of ENETC_SI_RBCIR */ #define ENETC_SI_RBCIR_COUNT (8U) /*! @name RBBAR0 - Rx BDR 0 base address register 0..Rx BDR 7 base address register 0 */ /*! @{ */ #define ENETC_SI_RBBAR0_ADDRL_MASK (0xFFFFFF80U) #define ENETC_SI_RBBAR0_ADDRL_SHIFT (7U) #define ENETC_SI_RBBAR0_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBBAR0_ADDRL_SHIFT)) & ENETC_SI_RBBAR0_ADDRL_MASK) /*! @} */ /* The count of ENETC_SI_RBBAR0 */ #define ENETC_SI_RBBAR0_COUNT (8U) /*! @name RBBAR1 - Rx BDR 0 base address register 1..Rx BDR 7 base address register 1 */ /*! @{ */ #define ENETC_SI_RBBAR1_ADDRH_MASK (0xFFFFFFFFU) #define ENETC_SI_RBBAR1_ADDRH_SHIFT (0U) #define ENETC_SI_RBBAR1_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBBAR1_ADDRH_SHIFT)) & ENETC_SI_RBBAR1_ADDRH_MASK) /*! @} */ /* The count of ENETC_SI_RBBAR1 */ #define ENETC_SI_RBBAR1_COUNT (8U) /*! @name RBPIR - Rx BDR 0 producer index register..Rx BDR 7 producer index register */ /*! @{ */ #define ENETC_SI_RBPIR_BDR_INDEX_MASK (0xFFFFU) #define ENETC_SI_RBPIR_BDR_INDEX_SHIFT (0U) #define ENETC_SI_RBPIR_BDR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBPIR_BDR_INDEX_SHIFT)) & ENETC_SI_RBPIR_BDR_INDEX_MASK) #define ENETC_SI_RBPIR_SBE_MASK (0x80000000U) #define ENETC_SI_RBPIR_SBE_SHIFT (31U) #define ENETC_SI_RBPIR_SBE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBPIR_SBE_SHIFT)) & ENETC_SI_RBPIR_SBE_MASK) /*! @} */ /* The count of ENETC_SI_RBPIR */ #define ENETC_SI_RBPIR_COUNT (8U) /*! @name RBLENR - Rx BDR 0 length register..Rx BDR 7 length register */ /*! @{ */ #define ENETC_SI_RBLENR_LENGTH_MASK (0x1FFF8U) #define ENETC_SI_RBLENR_LENGTH_SHIFT (3U) #define ENETC_SI_RBLENR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBLENR_LENGTH_SHIFT)) & ENETC_SI_RBLENR_LENGTH_MASK) /*! @} */ /* The count of ENETC_SI_RBLENR */ #define ENETC_SI_RBLENR_COUNT (8U) /*! @name RBRSCR - Rx BDR 0 RSC register..Rx BDR 7 RSC register */ /*! @{ */ #define ENETC_SI_RBRSCR_SIZE_MASK (0xFFFFU) #define ENETC_SI_RBRSCR_SIZE_SHIFT (0U) /*! SIZE - Size */ #define ENETC_SI_RBRSCR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBRSCR_SIZE_SHIFT)) & ENETC_SI_RBRSCR_SIZE_MASK) #define ENETC_SI_RBRSCR_CT_MASK (0x20000000U) #define ENETC_SI_RBRSCR_CT_SHIFT (29U) /*! CT - Coalesce Timestamp * 0b0..Not permitted; a segment containing the TCP timestamp option terminates the coalesce operation * 0b1..Permitted */ #define ENETC_SI_RBRSCR_CT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBRSCR_CT_SHIFT)) & ENETC_SI_RBRSCR_CT_MASK) #define ENETC_SI_RBRSCR_EN_MASK (0x80000000U) #define ENETC_SI_RBRSCR_EN_SHIFT (31U) /*! EN - Enable * 0b0..Disabled * 0b1..Enabled */ #define ENETC_SI_RBRSCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBRSCR_EN_SHIFT)) & ENETC_SI_RBRSCR_EN_MASK) /*! @} */ /* The count of ENETC_SI_RBRSCR */ #define ENETC_SI_RBRSCR_COUNT (8U) /*! @name RBDCR - Rx BDR 0 drop count register..Rx BDR 7 drop count register */ /*! @{ */ #define ENETC_SI_RBDCR_COUNT_MASK (0xFFFFFFFFU) #define ENETC_SI_RBDCR_COUNT_SHIFT (0U) #define ENETC_SI_RBDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBDCR_COUNT_SHIFT)) & ENETC_SI_RBDCR_COUNT_MASK) /*! @} */ /* The count of ENETC_SI_RBDCR */ #define ENETC_SI_BDR_RBDCR_COUNT (8U) /*! @name RBIER - Rx BDR 0 interrupt enable register..Rx BDR 7 interrupt enable register */ /*! @{ */ #define ENETC_SI_RBIER_RXTIE_MASK (0x1U) #define ENETC_SI_RBIER_RXTIE_SHIFT (0U) #define ENETC_SI_RBIER_RXTIE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBIER_RXTIE_SHIFT)) & ENETC_SI_RBIER_RXTIE_MASK) /*! @} */ /* The count of ENETC_SI_RBIER */ #define ENETC_SI_RBIER_COUNT (8U) /*! @name RBIDR - Rx BDR 0 interrupt detect register..Rx BDR 7 interrupt detect register */ /*! @{ */ #define ENETC_SI_RBIDR_RXT_MASK (0x1U) #define ENETC_SI_RBIDR_RXT_SHIFT (0U) #define ENETC_SI_RBIDR_RXT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBIDR_RXT_SHIFT)) & ENETC_SI_RBIDR_RXT_MASK) /*! @} */ /* The count of ENETC_SI_RBIDR */ #define ENETC_SI_RBIDR_COUNT (8U) /*! @name RBICR0 - Rx BDR 0 interrupt coalescing register 0..Rx BDR 7 interrupt coalescing register 0 */ /*! @{ */ #define ENETC_SI_RBICR0_ICPT_MASK (0x1FFU) #define ENETC_SI_RBICR0_ICPT_SHIFT (0U) #define ENETC_SI_RBICR0_ICPT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBICR0_ICPT_SHIFT)) & ENETC_SI_RBICR0_ICPT_MASK) #define ENETC_SI_RBICR0_ICEN_MASK (0x80000000U) #define ENETC_SI_RBICR0_ICEN_SHIFT (31U) #define ENETC_SI_RBICR0_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBICR0_ICEN_SHIFT)) & ENETC_SI_RBICR0_ICEN_MASK) /*! @} */ /* The count of ENETC_SI_RBICR0 */ #define ENETC_SI_RBICR0_COUNT (8U) /*! @name RBICR1 - Rx BDR 0 interrupt coalescing register 1..Rx BDR 7 interrupt coalescing register 1 */ /*! @{ */ #define ENETC_SI_RBICR1_ICTT_MASK (0xFFFFFFFFU) #define ENETC_SI_RBICR1_ICTT_SHIFT (0U) #define ENETC_SI_RBICR1_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_SI_RBICR1_ICTT_SHIFT)) & ENETC_SI_RBICR1_ICTT_MASK) /*! @} */ /* The count of ENETC_SI_RBICR1 */ #define ENETC_SI_RBICR1_COUNT (8U) /*! * @} */ /* end of group ENETC_SI_Register_Masks */ /* ENETC_SI - Peripheral instance base addresses */ /** Peripheral ENETC0_PSI base address */ #define ENETC0_PSI_BASE (0x4CC00000u) /** Peripheral ENETC0_PSI base pointer */ #define ENETC0_PSI ((ENETC_SI_Type *)ENETC0_PSI_BASE) /** Peripheral ENETC1_PSI base address */ #define ENETC1_PSI_BASE (0x4CC40000u) /** Peripheral ENETC1_PSI base pointer */ #define ENETC1_PSI ((ENETC_SI_Type *)ENETC1_PSI_BASE) /** Peripheral ENETC2_PSI base address */ #define ENETC2_PSI_BASE (0x4CC80000u) /** Peripheral ENETC2_PSI base pointer */ #define ENETC2_PSI ((ENETC_SI_Type *)ENETC2_PSI_BASE) /** Peripheral ENETC_VSI0 base address */ #define ENETC_VSI0_BASE (0x4CD20000u) /** Peripheral ENETC_VSI0 base pointer */ #define ENETC_VSI0 ((ENETC_SI_Type *)ENETC_VSI0_BASE) /** Peripheral ENETC_VSI1 base address */ #define ENETC_VSI1_BASE (0x4CD30000u) /** Peripheral ENETC_VSI1 base pointer */ #define ENETC_VSI1 ((ENETC_SI_Type *)ENETC_VSI1_BASE) /** Peripheral ENETC_VSI2 base address */ #define ENETC_VSI2_BASE (0x4CD40000u) /** Peripheral ENETC_VSI2 base pointer */ #define ENETC_VSI2 ((ENETC_SI_Type *)ENETC_VSI2_BASE) /** Peripheral ENETC_VSI3 base address */ #define ENETC_VSI3_BASE (0x4CD50000u) /** Peripheral ENETC_VSI3 base pointer */ #define ENETC_VSI3 ((ENETC_SI_Type *)ENETC_VSI3_BASE) /** Peripheral ENETC_VSI4 base address */ #define ENETC_VSI4_BASE (0x4CD60000u) /** Peripheral ENETC_VSI4 base pointer */ #define ENETC_VSI4 ((ENETC_SI_Type *)ENETC_VSI4_BASE) /** Peripheral ENETC_VSI5 base address */ #define ENETC_VSI5_BASE (0x4CD70000u) /** Peripheral ENETC_VSI5 base pointer */ #define ENETC_VSI5 ((ENETC_SI_Type *)ENETC_VSI5_BASE) /** Array initializer of ENETC_SI peripheral base addresses */ #define ENETC_SI_BASE_ADDRS { ENETC0_PSI_BASE, ENETC1_PSI_BASE, ENETC2_PSI_BASE, ENETC_VSI0_BASE, ENETC_VSI1_BASE, ENETC_VSI2_BASE, ENETC_VSI3_BASE, ENETC_VSI4_BASE, ENETC_VSI5_BASE } /** Array initializer of ENETC_SI peripheral base pointers */ #define ENETC_SI_BASE_PTRS { ENETC0_PSI, ENETC1_PSI, ENETC2_PSI, ENETC_VSI0, ENETC_VSI1, ENETC_VSI2, ENETC_VSI3, ENETC_VSI4, ENETC_VSI5 } /*! * @} */ /* end of group ENETC_SI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENETC_VF_PCI_TYPE0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_VF_PCI_TYPE0_Peripheral_Access_Layer ENETC_VF_PCI_TYPE0 Peripheral Access Layer * @{ */ /** ENETC_VF_PCI_TYPE0 - Register Layout Typedef */ typedef struct { __I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset: 0x0 */ __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */ __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */ __I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offset: 0x8 */ __I uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */ __I uint8_t PCI_CFH_LAT_TIMER; /**< PCI latency timer register, offset: 0xD */ __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */ __I uint8_t PCI_CFH_BIST; /**< PCI BIST register, offset: 0xF */ __I uint32_t PCI_CFH_BAR0; /**< PCI base address register 0, offset: 0x10 */ __I uint32_t PCI_CFH_BAR1; /**< PCI base address register 1, offset: 0x14 */ __I uint32_t PCI_CFH_BAR2; /**< PCI base address register 2, offset: 0x18 */ __I uint32_t PCI_CFH_BAR3; /**< PCI base address register 3, offset: 0x1C */ __I uint32_t PCI_CFH_BAR4; /**< PCI base address register 4, offset: 0x20 */ __I uint32_t PCI_CFH_BAR5; /**< PCI base address register 5, offset: 0x24 */ __I uint32_t PCI_CFH_CARDBUS_CIS; /**< PCI cardbus CIS register, offset: 0x28 */ __I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x2C */ __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */ __I uint32_t PCI_CFH_EXP_ROM_BA; /**< PCI expansion ROM base address register, offset: 0x30 */ __I uint8_t PCI_CFH_CAP_PTR; /**< PCI capabilities pointer register, offset: 0x34 */ uint8_t RESERVED_0[11]; __I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset: 0x40 */ __I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42 */ __I uint32_t PCI_CFC_PCIE_DEV_CAP; /**< PCI PCIe device capabilities register, offset: 0x44 */ __IO uint16_t PCI_CFC_PCIE_DEV_CTL; /**< PCI PCIe device control register, offset: 0x48 */ __I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4A */ uint8_t RESERVED_1[24]; __I uint32_t PCI_CFC_PCIE_DEV_CAP2; /**< PCI PCIe device capabilities 2 register, offset: 0x64 */ __I uint16_t PCI_CFC_PCIE_DEV_CTL2; /**< PCI PCIe device control 2 register, offset: 0x68 */ uint8_t RESERVED_2[22]; __I uint16_t PCI_CFC_MSIX_CAP_LIST; /**< PCI MSI-X capabilities list register, offset: 0x80 */ __IO uint16_t PCI_CFC_MSIX_MSG_CTL; /**< PCI MSI-X message control register, offset: 0x82 */ __I uint32_t PCI_CFC_MSIX_TABLE_OFF_BIR; /**< PCI MSI-X table offset/BIR register, offset: 0x84 */ __I uint32_t PCI_CFC_MSIX_PBA_OFF_BIR; /**< PCI MSI-X PBA offset/BIR register, offset: 0x88 */ uint8_t RESERVED_3[116]; __I uint32_t PCIE_CFC_AER_EXT_CAP_HDR; /**< PCIe AER extended capability header, offset: 0x100 */ __IO uint32_t PCIE_CFC_AER_UCORR_ERR_STAT; /**< PCIe AER uncorrectable error status register, offset: 0x104 */ __IO uint32_t PCIE_CFC_AER_UCORR_ERR_MASK; /**< PCIe AER uncorrectable error mask register, offset: 0x108 */ __IO uint32_t PCIE_CFC_AER_UCORR_ERR_SEV; /**< PCIe AER uncorrectable error severity register, offset: 0x10C */ __IO uint32_t PCIE_CFC_AER_CORR_ERR_STAT; /**< PCIe AER correctable error status register, offset: 0x110 */ __IO uint32_t PCIE_CFC_AER_CORR_ERR_MASK; /**< PCIe AER correctable error mask register, offset: 0x114 */ __I uint32_t PCIE_CFC_AER_CAP_CTL; /**< PCIe AER capabilities and control register, offset: 0x118 */ uint8_t RESERVED_4[20]; __I uint32_t PCIE_CFC_ACS_CAP_HDR; /**< PCIe ACS capability header, offset: 0x130 */ __I uint16_t PCIE_CFC_ACS_CAP; /**< PCIe ACS capability register, offset: 0x134 */ __I uint16_t PCIE_CFC_ACS_CTL; /**< PCIe ACS control register, offset: 0x136 */ uint8_t RESERVED_5[8]; __I uint32_t PCIE_CFC_RTR_CAP_HDR; /**< PCIe readiness time reporting capability header, offset: 0x140 */ __I uint32_t PCIE_CFC_RTR_RTR1; /**< PCIe RTR readiness time reporting 1 register, offset: 0x144 */ __I uint32_t PCIE_CFC_RTR_RTR2; /**< PCIe RTR readiness time reporting 2 register, offset: 0x148 */ } ENETC_VF_PCI_TYPE0_Type; /* ---------------------------------------------------------------------------- -- ENETC_VF_PCI_TYPE0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENETC_VF_PCI_TYPE0_Register_Masks ENETC_VF_PCI_TYPE0 Register Masks * @{ */ /*! @name PCI_CFH_DID_VID - PCI device ID and vendor ID register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK (0xFFFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_VENDOR_ID_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK (0xFFFF0000U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT (16U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_DID_VID_DEVICE_ID_MASK) /*! @} */ /*! @name PCI_CFH_CMD - PCI command register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK (0x4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT (2U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CMD_BUS_MASTER_EN_MASK) /*! @} */ /*! @name PCI_CFH_STAT - PCI status register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK (0x10U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_STAT_CAP_LIST_MASK) /*! @} */ /*! @name PCI_CFH_REVID_CLASSCODE - PCI revision ID and classcode register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK (0xFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK (0xFFFFFF00U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT (8U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK) /*! @} */ /*! @name PCI_CFH_CL_SIZE - PCI cache line size register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK (0xFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK) /*! @} */ /*! @name PCI_CFH_LAT_TIMER - PCI latency timer register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_MASK (0xFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_LAT_TIMER_LATENCY_TIMER_MASK) /*! @} */ /*! @name PCI_CFH_HDR_TYPE - PCI header type register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK (0x7FU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK (0x80U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT (7U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK) /*! @} */ /*! @name PCI_CFH_BIST - PCI BIST register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_MASK (0xFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BIST_BIST_MASK) /*! @} */ /*! @name PCI_CFH_BAR0 - PCI base address register 0 */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK (0x1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_IO_IND_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK (0x6U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_MEM_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK (0x8U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_PF_MEM_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK (0xFFFFFFF0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR0_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR1 - PCI base address register 1 */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK (0x1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_IO_IND_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK (0x6U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_MEM_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK (0x8U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_PF_MEM_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK (0xFFFFFFF0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR1_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR2 - PCI base address register 2 */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK (0x1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_IO_IND_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK (0x6U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_MEM_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK (0x8U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_PF_MEM_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK (0xFFFFFFF0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR2_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR3 - PCI base address register 3 */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK (0x1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_IO_IND_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK (0x6U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_MEM_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK (0x8U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_PF_MEM_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK (0xFFFFFFF0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR3_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR4 - PCI base address register 4 */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK (0x1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_IO_IND_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK (0x6U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_MEM_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK (0x8U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_PF_MEM_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK (0xFFFFFFF0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR4_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_BAR5 - PCI base address register 5 */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK (0x1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_IO_IND_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK (0x6U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_MEM_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK (0x8U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_PF_MEM_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK (0xFFFFFFF0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_BAR5_ADDR_MASK) /*! @} */ /*! @name PCI_CFH_CARDBUS_CIS - PCI cardbus CIS register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_MASK (0xFFFFFFFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CARDBUS_CIS_CARDBUS_CIS_PTR_MASK) /*! @} */ /*! @name PCI_CFH_SUBSYS_VID - PCI subsystem vendor ID register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_MASK (0xFFFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_VID_SYBSYSTEM_VENDOR_ID_MASK) /*! @} */ /*! @name PCI_CFH_SUBSYS_ID - PCI subsystem ID register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_MASK (0xFFFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_SUBSYS_ID_SYBSYSTEM_ID_MASK) /*! @} */ /*! @name PCI_CFH_EXP_ROM_BA - PCI expansion ROM base address register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_MASK (0xFFFFFFFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_EXP_ROM_BA_EXP_ROM_BA_MASK) /*! @} */ /*! @name PCI_CFH_CAP_PTR - PCI capabilities pointer register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK (0xFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR(x) (((uint8_t)(((uint8_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFH_CAP_PTR_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_CAP_LIST - PCI PCIe capabilities list register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK (0xFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_CAP - PCI PCIe capabilities register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK (0xFU) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_CAP_VER_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK (0xF0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK (0x3E00U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT (9U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CAP - PCI PCIe device capabilities register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK (0x10000000U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT (28U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CTL - PCI PCIe device control register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK (0x8000U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT (15U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_STAT - PCI PCIe device status register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK (0x20U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT (5U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CAP2 - PCI PCIe device capabilities 2 register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK (0xFU) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_RNG_SUPP_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK (0x10U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CAP2_CMPL_TO_DIS_SUPP_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CTL2 - PCI PCIe device control 2 register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK (0xFU) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_VALUE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK (0x10U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT (4U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL2_CMPL_TO_EN_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_CAP_LIST - PCI MSI-X capabilities list register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK (0xFFU) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_CAP_ID_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_MSG_CTL - PCI MSI-X message control register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK (0x7FFU) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_TABLE_SIZE_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK (0x4000U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT (14U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_FUNC_MASK_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK (0x8000U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT (15U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_MSG_CTL_MSIX_EN_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_TABLE_OFF_BIR - PCI MSI-X table offset/BIR register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK (0x7U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_BIR_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK (0xFFFFFFF8U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_TABLE_OFF_BIR_TABLE_OFFSET_MASK) /*! @} */ /*! @name PCI_CFC_MSIX_PBA_OFF_BIR - PCI MSI-X PBA offset/BIR register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK (0x7U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_BIR_MASK) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK (0xFFFFFFF8U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT (3U) #define ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_SHIFT)) & ENETC_VF_PCI_TYPE0_PCI_CFC_MSIX_PBA_OFF_BIR_PBA_OFFSET_MASK) /*! @} */ /*! @name PCIE_CFC_AER_EXT_CAP_HDR - PCIe AER extended capability header */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT (16U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_AER_UCORR_ERR_STAT - PCIe AER uncorrectable error status register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK (0x400000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT (22U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_STAT_UCORR_INT_ERR_MASK) /*! @} */ /*! @name PCIE_CFC_AER_UCORR_ERR_MASK - PCIe AER uncorrectable error mask register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK (0x400000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT (22U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_MASK_UCORR_INT_ERR_MASK_MASK) /*! @} */ /*! @name PCIE_CFC_AER_UCORR_ERR_SEV - PCIe AER uncorrectable error severity register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK (0x400000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT (22U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_UCORR_ERR_SEV_UCORR_INT_SEV_MASK) /*! @} */ /*! @name PCIE_CFC_AER_CORR_ERR_STAT - PCIe AER correctable error status register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK (0x4000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT (14U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_STAT_CORR_INT_ERR_MASK) /*! @} */ /*! @name PCIE_CFC_AER_CORR_ERR_MASK - PCIe AER correctable error mask register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK (0x4000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT (14U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CORR_ERR_MASK_CORR_INT_MASK_MASK) /*! @} */ /*! @name PCIE_CFC_AER_CAP_CTL - PCIe AER capabilities and control register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK (0x1FU) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_AER_CAP_CTL_FIRST_ERR_PTR_MASK) /*! @} */ /*! @name PCIE_CFC_ACS_CAP_HDR - PCIe ACS capability header */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT (16U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_CAP_VER_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_ACS_CAP - PCIe ACS capability register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK (0x2U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_TRANS_BLOCK_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK (0x4U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT (2U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_P2P_REQ_REDIR_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK (0x40U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT (6U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CAP_ACS_DIR_TRANS_P2P_MASK) /*! @} */ /*! @name PCIE_CFC_ACS_CTL - PCIe ACS control register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK (0x2U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT (1U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_TRANS_BLOCK_EN_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK (0x4U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT (2U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_P2P_REQ_REDIR_EN_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK (0x40U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT (6U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN(x) (((uint16_t)(((uint16_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_ACS_CTL_ACS_DIR_TRANS_P2P_EN_MASK) /*! @} */ /*! @name PCIE_CFC_RTR_CAP_HDR - PCIe readiness time reporting capability header */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT (16U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_CAP_VER_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_RTR_RTR1 - PCIe RTR readiness time reporting 1 register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK (0xFFFU) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT (0U) /*! RESET_TIME - Reset Time */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_RESET_TIME_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK (0x80000000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT (31U) /*! VALID - Valid */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR1_VALID_MASK) /*! @} */ /*! @name PCIE_CFC_RTR_RTR2 - PCIe RTR readiness time reporting 2 register */ /*! @{ */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK (0xFFFU) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT (0U) /*! FLR_TIME - FLR Time */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_FLR_TIME_MASK) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK (0xFFF000U) #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT (12U) /*! D3HOT_D0_TIME - D3 hot to D0 time */ #define ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_SHIFT)) & ENETC_VF_PCI_TYPE0_PCIE_CFC_RTR_RTR2_D3HOT_D0_TIME_MASK) /*! @} */ /*! * @} */ /* end of group ENETC_VF_PCI_TYPE0_Register_Masks */ /* ENETC_VF_PCI_TYPE0 - Peripheral instance base addresses */ /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base address */ #define NETC_VF1_PCI_HDR_TYPE0_BASE (0x4CA10000u) /** Peripheral NETC_VF1_PCI_HDR_TYPE0 base pointer */ #define NETC_VF1_PCI_HDR_TYPE0 ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF1_PCI_HDR_TYPE0_BASE) /** Peripheral NETC_VF2_PCI_HDR_TYPE0 base address */ #define NETC_VF2_PCI_HDR_TYPE0_BASE (0x4CA20000u) /** Peripheral NETC_VF2_PCI_HDR_TYPE0 base pointer */ #define NETC_VF2_PCI_HDR_TYPE0 ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF2_PCI_HDR_TYPE0_BASE) /** Peripheral NETC_VF3_PCI_HDR_TYPE0 base address */ #define NETC_VF3_PCI_HDR_TYPE0_BASE (0x4CA50000u) /** Peripheral NETC_VF3_PCI_HDR_TYPE0 base pointer */ #define NETC_VF3_PCI_HDR_TYPE0 ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF3_PCI_HDR_TYPE0_BASE) /** Peripheral NETC_VF4_PCI_HDR_TYPE0 base address */ #define NETC_VF4_PCI_HDR_TYPE0_BASE (0x4CA60000u) /** Peripheral NETC_VF4_PCI_HDR_TYPE0 base pointer */ #define NETC_VF4_PCI_HDR_TYPE0 ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF4_PCI_HDR_TYPE0_BASE) /** Peripheral NETC_VF5_PCI_HDR_TYPE0 base address */ #define NETC_VF5_PCI_HDR_TYPE0_BASE (0x4CA90000u) /** Peripheral NETC_VF5_PCI_HDR_TYPE0 base pointer */ #define NETC_VF5_PCI_HDR_TYPE0 ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF5_PCI_HDR_TYPE0_BASE) /** Peripheral NETC_VF6_PCI_HDR_TYPE0 base address */ #define NETC_VF6_PCI_HDR_TYPE0_BASE (0x4CAA0000u) /** Peripheral NETC_VF6_PCI_HDR_TYPE0 base pointer */ #define NETC_VF6_PCI_HDR_TYPE0 ((ENETC_VF_PCI_TYPE0_Type *)NETC_VF6_PCI_HDR_TYPE0_BASE) /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base addresses */ #define ENETC_VF_PCI_TYPE0_BASE_ADDRS { NETC_VF1_PCI_HDR_TYPE0_BASE, NETC_VF2_PCI_HDR_TYPE0_BASE, NETC_VF3_PCI_HDR_TYPE0_BASE, NETC_VF4_PCI_HDR_TYPE0_BASE, NETC_VF5_PCI_HDR_TYPE0_BASE, NETC_VF6_PCI_HDR_TYPE0_BASE } /** Array initializer of ENETC_VF_PCI_TYPE0 peripheral base pointers */ #define ENETC_VF_PCI_TYPE0_BASE_PTRS { NETC_VF1_PCI_HDR_TYPE0, NETC_VF2_PCI_HDR_TYPE0, NETC_VF3_PCI_HDR_TYPE0, NETC_VF4_PCI_HDR_TYPE0, NETC_VF5_PCI_HDR_TYPE0, NETC_VF6_PCI_HDR_TYPE0 } /*! * @} */ /* end of group ENETC_VF_PCI_TYPE0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET_PHY Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_Peripheral_Access_Layer ENET_PHY Peripheral Access Layer * @{ */ /** ENET_PHY - Register Layout Typedef */ typedef struct { __I uint16_t SUP_DIG_IDCODE_LO; /**< Low 16 Bits of IDCODE, offset: 0x0 */ uint8_t RESERVED_0[2]; __I uint16_t SUP_DIG_IDCODE_HI; /**< High 16 Bits of IDCODE, offset: 0x4 */ uint8_t RESERVED_1[2]; __IO uint16_t SUP_DIG_REFCLK_OVRD_IN; /**< Override Values for Incoming REFCLK and RESET Controls from ASIC, offset: 0x8 */ uint8_t RESERVED_2[2]; __IO uint16_t SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN; /**< Override Values for Incoming MPLLA_B_DIV_CLK Controls from ASIC, offset: 0xC */ uint8_t RESERVED_3[2]; __IO uint16_t SUP_DIG_SUP_OVRD_IN_0; /**< Override Values for Support Block ASIC Inputs 0, offset: 0x10 */ uint8_t RESERVED_4[2]; __IO uint16_t SUP_DIG_SUP_OVRD_IN_1; /**< Override Values for Support Block ASIC Inputs 1, offset: 0x14 */ uint8_t RESERVED_5[2]; __IO uint16_t SUP_DIG_SUP_OVRD_IN_2; /**< Override Values for Support Block ASIC Inputs 2, offset: 0x18 */ uint8_t RESERVED_6[2]; __IO uint16_t SUP_DIG_SUP_OVRD_OUT; /**< Override Values for Support Block ASIC Outputs, offset: 0x1C */ uint8_t RESERVED_7[2]; __IO uint16_t SUP_DIG_LVL_OVRD_IN; /**< Override Values for Level Settings, offset: 0x20 */ uint8_t RESERVED_8[2]; __IO uint16_t SUP_DIG_DEBUG; /**< Debug Controls, offset: 0x24 */ uint8_t RESERVED_9[2]; __I uint16_t SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN; /**< Current Values for Incoming MPLLA_B_DIV_CLK Controls from ASIC, offset: 0x28 */ uint8_t RESERVED_10[2]; __I uint16_t SUP_DIG_ASIC_IN; /**< Current Values for Incoming SUP Control Signals from ASIC, offset: 0x2C */ uint8_t RESERVED_11[2]; __I uint16_t SUP_DIG_LVL_ASIC_IN; /**< Current Values for Incoming Level Controls from ASIC, offset: 0x30 */ uint8_t RESERVED_12[2]; __IO uint16_t SUP_DIG_SUP_OVRD_MISC; /**< Override Values for Incoming SUP MISC BUS from ASIC, offset: 0x34 */ uint8_t RESERVED_13[2]; __IO uint16_t SUP_DIG_CLK_RST_BG_PWRUP_TIME_0; /**< BG Power UP Time 0, offset: 0x38 */ uint8_t RESERVED_14[2]; __IO uint16_t SUP_DIG_CLK_RST_BG_PWRUP_TIME_1; /**< BG Power UP Time 1, offset: 0x3C */ uint8_t RESERVED_15[2]; __IO uint16_t SUP_ANA_RTUNE_CTRL; /**< RTUNE_CTRL, offset: 0x40 */ uint8_t RESERVED_16[2]; __IO uint16_t SUP_ANA_SWITCH_PWR_MEAS; /**< SWITCH_PWR_MEAS, offset: 0x44 */ uint8_t RESERVED_17[2]; __IO uint16_t SUP_ANA_SWITCH_MISC_MEAS; /**< SWITCH_MISC_MEAS, offset: 0x48 */ uint8_t RESERVED_18[2]; __IO uint16_t SUP_ANA_BG; /**< BG, offset: 0x4C */ uint8_t RESERVED_19[2]; __IO uint16_t SUP_DIG_RTUNE_DEBUG; /**< Resistor Tuning Debug Controls, offset: 0x50 */ uint8_t RESERVED_20[2]; __IO uint16_t SUP_DIG_RTUNE_CONFIG; /**< Configure Rtune Operation, offset: 0x54 */ uint8_t RESERVED_21[2]; __I uint16_t SUP_DIG_RTUNE_STAT; /**< Resistor Tuning Register Status, offset: 0x58 */ uint8_t RESERVED_22[2]; __IO uint16_t SUP_DIG_RTUNE_RX_SET_VAL; /**< Set Value of RX Resistor, offset: 0x5C */ uint8_t RESERVED_23[2]; __IO uint16_t SUP_DIG_RTUNE_TXDN_SET_VAL; /**< Set Value of TX-DN Resistor, offset: 0x60 */ uint8_t RESERVED_24[2]; __IO uint16_t SUP_DIG_RTUNE_TXUP_SET_VAL; /**< Set Value of TX-UP Resistor, offset: 0x64 */ uint8_t RESERVED_25[2]; __I uint16_t SUP_DIG_RTUNE_RX_STAT; /**< RX Resistor Tuning Register Status, offset: 0x68 */ uint8_t RESERVED_26[2]; __I uint16_t SUP_DIG_RTUNE_TXDN_STAT; /**< TX-DN Resistor Tuning Register Status, offset: 0x6C */ uint8_t RESERVED_27[2]; __I uint16_t SUP_DIG_RTUNE_TXUP_STAT; /**< TX-UP Resistor Tuning Register Status, offset: 0x70 */ uint8_t RESERVED_28[2]; __IO uint16_t SUP_DIG_ANA_RTUNE_OVRD_OUT; /**< Override Value for RTUNE Signals Going to ANA, offset: 0x74 */ uint8_t RESERVED_29[2]; __IO uint16_t SUP_DIG_ANA_RX_TERM_OVRD_OUT; /**< Override Value for RX Termination Signals Going to ANA, offset: 0x78 */ uint8_t RESERVED_30[2]; __I uint16_t SUP_DIG_ANA_STAT; /**< SUP Input Status Register for SUP ANA Outputs, offset: 0x7C */ uint8_t RESERVED_31[2]; __IO uint16_t SUP_DIG_ANA_BG_OVRD_OUT; /**< Override Values for Bandgap Signals Going to ANA, offset: 0x80 */ uint8_t RESERVED_32[2]; __I uint16_t SUP_DIG_FREQ_CNT_PEAK_ASIC_IN; /**< Current Values for Incoming Level Controls from ASIC, offset: 0x84 */ uint8_t RESERVED_33[2]; __I uint16_t SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN; /**< Current Values for Incoming Level Controls from ASIC, offset: 0x88 */ uint8_t RESERVED_34[2]; __I uint16_t SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN; /**< Current Values for Incoming Level Controls from ASIC, offset: 0x8C */ uint8_t RESERVED_35[2]; __I uint16_t SUP_DIG_MISC_ASIC_IN; /**< Current Values for Incoming Level Controls from ASIC, offset: 0x90 */ uint8_t RESERVED_36[2]; __IO uint16_t RAWCMN_DIG_CMN_CTL; /**< Common Control, offset: 0x94 */ uint8_t RESERVED_37[2]; __IO uint16_t RAWCMN_DIG_LANE_FSM_OP_XTND; /**< Lane FSM OP XTND Control, offset: 0x98 */ uint8_t RESERVED_38[2]; __IO uint16_t RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0; /**< Override Values for Incoming TX Term Offset, offset: 0x9C */ uint8_t RESERVED_39[2]; __IO uint16_t RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1; /**< Override Values for Incoming TX/RX Term Offset, offset: 0xA0 */ uint8_t RESERVED_40[2]; __IO uint16_t RAWCMN_DIG_CMN_CTL_1; /**< Common Control 1, offset: 0xA4 */ uint8_t RESERVED_41[2]; __IO uint16_t RAWCMN_DIG_MPLL_OFF_TIME; /**< Wait Time for Turning MPLL Off, offset: 0xA8 */ uint8_t RESERVED_42[2]; __IO uint16_t RAWCMN_DIG_ATE_ALU_CTRL; /**< ATE ALU Module Control, offset: 0xAC */ uint8_t RESERVED_43[2]; __IO uint16_t RAWCMN_DIG_ATE_ALU_ADDR; /**< Address for Read and Write Command for ATE ALU Module, offset: 0xB0 */ uint8_t RESERVED_44[2]; __IO uint16_t RAWCMN_DIG_ATE_ALU_DATA; /**< Data for Write Command for ATE ALU Module, offset: 0xB4 */ uint8_t RESERVED_45[2]; __I uint16_t RAWCMN_DIG_ATE_ALU_FLAGS; /**< Flags from ATE ALU Module, offset: 0xB8 */ uint8_t RESERVED_46[2]; __I uint16_t RAWCMN_DIG_ATE_ALU_ACCUM; /**< Stores the ATE ALU Accumulator Result, offset: 0xBC */ uint8_t RESERVED_47[2]; __I uint16_t RAWCMN_DIG_MPLL_IN; /**< Current Values for Incoming MPLL Controls from PCS (Pre-Override Input Monitor), offset: 0xC0 */ uint8_t RESERVED_48[2]; __IO uint16_t RAWCMN_DIG_FW_PWRUP_DONE; /**< Firmware Power-up Done Status, offset: 0xC4 */ uint8_t RESERVED_49[2]; __IO uint16_t RAWCMN_DIG_MPLL_CLK_ASYNC_EN; /**< MPLL Output Clocks Asynchronous Control, offset: 0xC8 */ uint8_t RESERVED_50[2]; __IO uint16_t RAWCMN_DIG_ATE_ALU_SPARE_0; /**< Spare Register 1 for ATE ALU Operations, offset: 0xCC */ uint8_t RESERVED_51[2]; __IO uint16_t RAWCMN_DIG_ATE_ALU_SPARE_1; /**< Spare Register 2 for ATE ALU Operations, offset: 0xD0 */ uint8_t RESERVED_52[2]; __IO uint16_t RAWCMN_DIG_MPLL_STATE_OVRD_IN; /**< Override for MPLLA/B State Outputs, offset: 0xD4 */ uint8_t RESERVED_53[2]; __IO uint16_t RAWCMN_DIG_AON_SRAM_PGATE_BL_EN; /**< Enable SRAM Bootloader on Power-Gated Exit, offset: 0xD8 */ uint8_t RESERVED_54[2]; __IO uint16_t RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD; /**< Override Incoming MPLLA/B_RECAL_BANK_SEL Input, offset: 0xDC */ uint8_t RESERVED_55[2]; __IO uint16_t RAWCMN_DIG_AON_PG_OVRD_IN; /**< Override Values for Incoming Power-Gating Signals, offset: 0xE0 */ uint8_t RESERVED_56[2]; __IO uint16_t RAWCMN_DIG_AON_PG_OVRD_OUT; /**< Override Values for Outgoing Power-Gating Signals, offset: 0xE4 */ uint8_t RESERVED_57[2]; __IO uint16_t RAWCMN_DIG_AON_SUP_OVRD_IN; /**< Override Values for Incoming Support Block Signals, offset: 0xE8 */ uint8_t RESERVED_58[2]; __IO uint16_t RAWCMN_DIG_AON_SUP_OVRD_OUT; /**< Override Values for Out-going Support Block Signals, offset: 0xEC */ uint8_t RESERVED_59[2]; __IO uint16_t RAWCMN_DIG_AON_RTUNE_RX_VAL; /**< Resistor Tune RX Value, offset: 0xF0 */ uint8_t RESERVED_60[2]; __IO uint16_t RAWCMN_DIG_AON_RTUNE_TXDN_VAL; /**< Resistor Tune TX Down Value, offset: 0xF4 */ uint8_t RESERVED_61[2]; __IO uint16_t RAWCMN_DIG_AON_RTUNE_TXUP_VAL; /**< Resistor Tune TX Up Value, offset: 0xF8 */ uint8_t RESERVED_62[2]; __IO uint16_t RAWCMN_DIG_AON_CMNCAL_STATUS; /**< Common Calibration Status, offset: 0xFC */ uint8_t RESERVED_63[2]; __IO uint16_t RAWCMN_DIG_AON_SRAM_OVRD_IN; /**< Override for Incoming SRAM Inputs, offset: 0x100 */ uint8_t RESERVED_64[2]; __I uint16_t RAWCMN_DIG_AON_SRAM_IN; /**< Monitor for SRAM Inputs, offset: 0x104 */ uint8_t RESERVED_65[2]; __I uint16_t RAWCMN_DIG_AON_SRAM_OUT; /**< Monitor for SRAM Outputs, offset: 0x108 */ uint8_t RESERVED_66[2]; __IO uint16_t RAWCMN_DIG_AON_FW_VERSION_0; /**< Firmware Version 0, offset: 0x10C */ uint8_t RESERVED_67[2]; __IO uint16_t RAWCMN_DIG_AON_FW_VERSION_1; /**< Firmware Version 1, offset: 0x110 */ uint8_t RESERVED_68[130798]; __IO uint16_t SUP_DIG_MPLLA_OVRD_IN_0; /**< Override Values for Incoming MPLLA Controls from ASIC 0, offset: 0x20000 */ uint8_t RESERVED_69[2]; __IO uint16_t SUP_DIG_MPLLA_OVRD_IN_1; /**< Override Values for Incoming MPLLA Controls from ASIC 1, offset: 0x20004 */ uint8_t RESERVED_70[2]; __IO uint16_t SUP_DIG_MPLLA_OVRD_IN_2; /**< Override Values for Incoming MPLLA Controls from ASIC 2, offset: 0x20008 */ uint8_t RESERVED_71[2]; __IO uint16_t SUP_DIG_MPLLA_OVRD_IN_3; /**< Override Values for Incoming MPLLA Controls from ASIC 3, offset: 0x2000C */ uint8_t RESERVED_72[2]; __IO uint16_t SUP_DIG_MPLLA_OVRD_IN_4; /**< Override Values for Incoming MPLLA Controls from ASIC 4, offset: 0x20010 */ uint8_t RESERVED_73[2]; __I uint16_t SUP_DIG_MPLLA_ASIC_IN_0; /**< Current Values for Incoming MPLLA Controls from ASIC 0, offset: 0x20014 */ uint8_t RESERVED_74[2]; __I uint16_t SUP_DIG_MPLLA_ASIC_IN_1; /**< Current Values for Incoming MPLLA Controls from ASIC 1, offset: 0x20018 */ uint8_t RESERVED_75[2]; __I uint16_t SUP_DIG_MPLLA_ASIC_IN_2; /**< Current Values for Incoming MPLLA Controls from ASIC 2, offset: 0x2001C */ uint8_t RESERVED_76[2]; __I uint16_t SUP_DIG_MPLLA_FREQ_CNT_INIT_ASIC_IN; /**< Current Values for Incoming Level Controls from ASIC, offset: 0x20020 */ uint8_t RESERVED_77[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL; /**< MPLL Calibration Controls, offset: 0x20024 */ uint8_t RESERVED_78[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD; /**< MPLL Override Controls, offset: 0x20028 */ uint8_t RESERVED_79[2]; __I uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT; /**< MPLL Status, offset: 0x2002C */ uint8_t RESERVED_80[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD; /**< Thresholds for MPLL CAL Update Timer and MPLL VCO Stabilization Timer, offset: 0x20030 */ uint8_t RESERVED_81[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD; /**< Thresholds for PCLK Enable and MPLL VCO Clock Stabilization Timer, offset: 0x20034 */ uint8_t RESERVED_82[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH; /**< Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer, offset: 0x20038 */ uint8_t RESERVED_83[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH; /**< Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer, offset: 0x2003C */ uint8_t RESERVED_84[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD; /**< Thresholds for MPLL Feedback Clock Enable and MPLL Feedback Digital Clock Disable Timer, offset: 0x20040 */ uint8_t RESERVED_85[2]; __I uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL; /**< MPLL coarse_tune Value, offset: 0x20044 */ uint8_t RESERVED_86[2]; __IO uint16_t SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE; /**< Value for MPLL coarse_tune When Skipping Calibration, offset: 0x20048 */ uint8_t RESERVED_87[2]; __IO uint16_t SUP_DIG_MPLLA_SSC_SS_PHASE; /**< Current MPLL Phase Selector Value, offset: 0x2004C */ uint8_t RESERVED_88[2]; __IO uint16_t SUP_DIG_MPLLA_SSC_SS_FREQ_0; /**< Frequency Control for Spread Spectrum 0, offset: 0x20050 */ uint8_t RESERVED_89[2]; __IO uint16_t SUP_DIG_MPLLA_SSC_SS_FREQ_1; /**< Frequency Control for Spread Spectrum 1, offset: 0x20054 */ uint8_t RESERVED_90[2]; __IO uint16_t SUP_ANA_MPLLA_LOOP_CTRL; /**< MPLLA_LOOP_CTRL, offset: 0x20058 */ uint8_t RESERVED_91[2]; __IO uint16_t SUP_ANA_MPLLA_OVRD; /**< MPLLA_OVRD, offset: 0x2005C */ uint8_t RESERVED_92[14]; __IO uint16_t SUP_DIG_ANA_MPLLA_OVRD_OUT; /**< Override Value for MPLLA Signals Going to ANA, offset: 0x2006C */ uint8_t RESERVED_93[2]; __IO uint16_t SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT; /**< Override Value for MPLLA PMIX Signals Going to ANA, offset: 0x20070 */ uint8_t RESERVED_94[2]; __IO uint16_t RAWCMN_DIG_MPLLA_BW_OVRD_IN; /**< Override Values for Incoming MPLLA Bandwidth, offset: 0x20074 */ uint8_t RESERVED_95[2]; __IO uint16_t RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN; /**< Override Values for Incoming MPLLA SSC Control Settings, offset: 0x20078 */ uint8_t RESERVED_96[2]; __IO uint16_t RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN; /**< Override Values for Incoming MPLLA SSC Input Signals, offset: 0x2007C */ uint8_t RESERVED_97[2]; __IO uint16_t RAWCMN_DIG_MPLLA_MISC_OVRD_IN; /**< Override Values for Incoming MPLLA-Related Input Signals, offset: 0x20080 */ uint8_t RESERVED_98[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0; /**< MPLLA Coarse Tune Value for Bank 0, offset: 0x20084 */ uint8_t RESERVED_99[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1; /**< MPLLA Coarse Tune Value for Bank 1, offset: 0x20088 */ uint8_t RESERVED_100[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2; /**< MPLLA Coarse Tune Value for Bank 2, offset: 0x2008C */ uint8_t RESERVED_101[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3; /**< MPLLA Coarse Tune Value for Bank 3, offset: 0x20090 */ uint8_t RESERVED_102[2]; __I uint16_t RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL; /**< Value for MPLLA Bank Select, offset: 0x20094 */ uint8_t RESERVED_103[2]; __I uint16_t RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_DONE; /**< Valid Calibrated Value for MPLLA Calibration Bank, offset: 0x20098 */ uint8_t RESERVED_104[2]; __I uint16_t RAWCMN_DIG_AON_MPLLA_COARSE_TUNE; /**< Selected COARSE TUNE Value for MPLLA, offset: 0x2009C */ uint8_t RESERVED_105[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLA_IN_RECAL; /**< MPLLA Re-Calibration, offset: 0x200A0 */ uint8_t RESERVED_106[2]; __IO uint16_t RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL; /**< Current Bank Selected for MPLLA Coarse Tune in PMA, offset: 0x200A4 */ uint8_t RESERVED_107[2]; __I uint16_t RAWCMN_DIG_AON_MPLLA_BANK_SEL_DONE; /**< Status for MPLLA Re-Calibration or Switching, offset: 0x200A8 */ uint8_t RESERVED_108[130902]; __IO uint16_t SUP_DIG_MPLLB_OVRD_IN_0; /**< Override Values for Incoming MPLLB Controls from ASIC 0, offset: 0x40000 */ uint8_t RESERVED_109[2]; __IO uint16_t SUP_DIG_MPLLB_OVRD_IN_1; /**< Override Values for Incoming MPLLB Controls from ASIC 1, offset: 0x40004 */ uint8_t RESERVED_110[2]; __IO uint16_t SUP_DIG_MPLLB_OVRD_IN_2; /**< Override Values for Incoming MPLLB Controls from ASIC 2, offset: 0x40008 */ uint8_t RESERVED_111[2]; __IO uint16_t SUP_DIG_MPLLB_OVRD_IN_3; /**< Override Values for Incoming MPLLB Controls from ASIC 3, offset: 0x4000C */ uint8_t RESERVED_112[2]; __IO uint16_t SUP_DIG_MPLLB_OVRD_IN_4; /**< Override Values for Incoming MPLLB Controls from ASIC 4, offset: 0x40010 */ uint8_t RESERVED_113[2]; __I uint16_t SUP_DIG_MPLLB_ASIC_IN_0; /**< Current Values for Incoming MPLLB Controls from ASIC 0, offset: 0x40014 */ uint8_t RESERVED_114[2]; __I uint16_t SUP_DIG_MPLLB_ASIC_IN_1; /**< Current Values for Incoming MPLLB Controls from ASIC 1, offset: 0x40018 */ uint8_t RESERVED_115[2]; __I uint16_t SUP_DIG_MPLLB_ASIC_IN_2; /**< Current Values for Incoming MPLLB Controls from ASIC 2, offset: 0x4001C */ uint8_t RESERVED_116[2]; __I uint16_t SUP_DIG_MPLLB_FREQ_CNT_INIT_ASIC_IN; /**< Current Values for Incoming Level Controls from ASIC, offset: 0x40020 */ uint8_t RESERVED_117[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL; /**< MPLL Calibration Controls, offset: 0x40024 */ uint8_t RESERVED_118[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD; /**< MPLL Override Controls, offset: 0x40028 */ uint8_t RESERVED_119[2]; __I uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT; /**< MPLL Status, offset: 0x4002C */ uint8_t RESERVED_120[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD; /**< Thresholds for MPLL CAL Update Timer and MPLL VCO Stabilization Timer, offset: 0x40030 */ uint8_t RESERVED_121[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD; /**< Thresholds for PCLK Enable and MPLL VCO Clock Stabilization Timer, offset: 0x40034 */ uint8_t RESERVED_122[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH; /**< Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer, offset: 0x40038 */ uint8_t RESERVED_123[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH; /**< Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer, offset: 0x4003C */ uint8_t RESERVED_124[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD; /**< Thresholds for MPLL Feedback Clock Enable and MPLL Feedback Digital Clock Disable Timer, offset: 0x40040 */ uint8_t RESERVED_125[2]; __I uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL; /**< MPLL coarse_tune Value, offset: 0x40044 */ uint8_t RESERVED_126[2]; __IO uint16_t SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE; /**< Value for MPLL coarse_tune When Skipping Calibration, offset: 0x40048 */ uint8_t RESERVED_127[2]; __IO uint16_t SUP_DIG_MPLLB_SSC_SS_PHASE; /**< Current MPLL Phase Selector Value, offset: 0x4004C */ uint8_t RESERVED_128[2]; __IO uint16_t SUP_DIG_MPLLB_SSC_SS_FREQ_0; /**< Frequency Control for Spread Spectrum 0, offset: 0x40050 */ uint8_t RESERVED_129[2]; __IO uint16_t SUP_DIG_MPLLB_SSC_SS_FREQ_1; /**< Frequency Control for Spread Spectrum 1, offset: 0x40054 */ uint8_t RESERVED_130[2]; __IO uint16_t SUP_ANA_MPLLB_LOOP_CTRL; /**< MPLLB_LOOP_CTRL, offset: 0x40058 */ uint8_t RESERVED_131[2]; __IO uint16_t SUP_ANA_MPLLB_OVRD; /**< MPLLB_OVRD, offset: 0x4005C */ uint8_t RESERVED_132[14]; __IO uint16_t SUP_DIG_ANA_MPLLB_OVRD_OUT; /**< Override Value for MPLLB Signals Going to ANA, offset: 0x4006C */ uint8_t RESERVED_133[2]; __IO uint16_t SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT; /**< Override Value for MPLLB PMIX Signals Going to ANA, offset: 0x40070 */ uint8_t RESERVED_134[2]; __IO uint16_t RAWCMN_DIG_MPLLB_BW_OVRD_IN; /**< Override Values for Incoming MPLLB Bandwidth, offset: 0x40074 */ uint8_t RESERVED_135[2]; __IO uint16_t RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN; /**< Override Values for Incoming MPLLB SSC Control Settings, offset: 0x40078 */ uint8_t RESERVED_136[2]; __IO uint16_t RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN; /**< Override Values for Incoming MPLLB SSC Input Signals, offset: 0x4007C */ uint8_t RESERVED_137[2]; __IO uint16_t RAWCMN_DIG_MPLLB_MISC_OVRD_IN; /**< Override Values for Incoming MPLLB-Related Input Signals, offset: 0x40080 */ uint8_t RESERVED_138[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0; /**< MPLLB Coarse Tune Value for Bank 0, offset: 0x40084 */ uint8_t RESERVED_139[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1; /**< MPLLB Coarse Tune Value for Bank 1, offset: 0x40088 */ uint8_t RESERVED_140[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2; /**< MPLLB Coarse Tune Value for Bank 2, offset: 0x4008C */ uint8_t RESERVED_141[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3; /**< MPLLB Coarse Tune Value for Bank 3, offset: 0x40090 */ uint8_t RESERVED_142[2]; __I uint16_t RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL; /**< Value for MPLLB Bank Select, offset: 0x40094 */ uint8_t RESERVED_143[2]; __I uint16_t RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_DONE; /**< Valid Calibrated Value for MPLLB Calibration Bank, offset: 0x40098 */ uint8_t RESERVED_144[2]; __I uint16_t RAWCMN_DIG_AON_MPLLB_COARSE_TUNE; /**< Selected COARSE TUNE Value for MPLLB, offset: 0x4009C */ uint8_t RESERVED_145[2]; __IO uint16_t RAWCMN_DIG_AON_MPLLB_IN_RECAL; /**< MPLLB Re-Calibration, offset: 0x400A0 */ uint8_t RESERVED_146[2]; __IO uint16_t RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL; /**< Current Bank Selected for MPLLB Coarse Tune in PMA, offset: 0x400A4 */ uint8_t RESERVED_147[2]; __I uint16_t RAWCMN_DIG_AON_MPLLB_BANK_SEL_DONE; /**< Status for MPLLB Re-Calibration or Switching, offset: 0x400A8 */ uint8_t RESERVED_148[130902]; __IO uint16_t LANE0_DIG_ASIC_LANE_OVRD_IN; /**< Override Values for Incoming LANE Controls from ASIC, offset: 0x60000 */ uint8_t RESERVED_149[2]; __IO uint16_t LANE0_DIG_ASIC_TX_OVRD_IN_0; /**< Override Values for Incoming TX Controls from ASIC 0, offset: 0x60004 */ uint8_t RESERVED_150[2]; __IO uint16_t LANE0_DIG_ASIC_TX_OVRD_IN_1; /**< Override Values for Incoming TX Drive Controls from ASIC 1, offset: 0x60008 */ uint8_t RESERVED_151[2]; __IO uint16_t LANE0_DIG_ASIC_TX_OVRD_IN_2; /**< Override Values for Incoming TX Drive Controls from ASIC 2, offset: 0x6000C */ uint8_t RESERVED_152[2]; __IO uint16_t LANE0_DIG_ASIC_TX_OVRD_OUT; /**< Override Values for Outgoing TX Controls to ASIC, offset: 0x60010 */ uint8_t RESERVED_153[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_IN_0; /**< Override Values for Incoming RX Controls from ASIC 0, offset: 0x60014 */ uint8_t RESERVED_154[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_IN_1; /**< Override Values for Incoming RX Controls from ASIC 1, offset: 0x60018 */ uint8_t RESERVED_155[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_IN_2; /**< Override Values for Incoming RX Controls from ASIC 2, offset: 0x6001C */ uint8_t RESERVED_156[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_IN_3; /**< Override Values for Incoming RX Controls from ASIC 3, offset: 0x60020 */ uint8_t RESERVED_157[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0; /**< Override Values for Incoming RX EQ Controls from ASIC 0, offset: 0x60024 */ uint8_t RESERVED_158[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1; /**< Override Values for Incoming RX EQ Controls from ASIC 1, offset: 0x60028 */ uint8_t RESERVED_159[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_OUT_0; /**< Override Values for Outgoing RX controls to ASIC 0, offset: 0x6002C */ uint8_t RESERVED_160[2]; __I uint16_t LANE0_DIG_ASIC_LANE_ASIC_IN; /**< Current Values for Incoming LANE Controls from ASIC, offset: 0x60030 */ uint8_t RESERVED_161[2]; __I uint16_t LANE0_DIG_ASIC_TX_ASIC_IN_0; /**< Current Values for Incoming TX Controls from ASIC 0, offset: 0x60034 */ uint8_t RESERVED_162[2]; __I uint16_t LANE0_DIG_ASIC_TX_ASIC_IN_1; /**< Current Values for Incoming TX Controls from ASIC 1, offset: 0x60038 */ uint8_t RESERVED_163[2]; __I uint16_t LANE0_DIG_ASIC_TX_ASIC_IN_2; /**< Current Values for Incoming TX Controls from ASIC 2, offset: 0x6003C */ uint8_t RESERVED_164[2]; __I uint16_t LANE0_DIG_ASIC_TX_ASIC_OUT; /**< Current Values for Outgoing TX Status Controls from PHY, offset: 0x60040 */ uint8_t RESERVED_165[2]; __I uint16_t LANE0_DIG_ASIC_RX_ASIC_IN_0; /**< Current Values for Incoming RX Controls from ASIC 0, offset: 0x60044 */ uint8_t RESERVED_166[2]; __I uint16_t LANE0_DIG_ASIC_RX_ASIC_IN_1; /**< Current Values for Incoming RX Controls from ASIC 1, offset: 0x60048 */ uint8_t RESERVED_167[2]; __I uint16_t LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0; /**< Current Values for Incoming RX EQ Controls from ASIC 0, offset: 0x6004C */ uint8_t RESERVED_168[2]; __I uint16_t LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1; /**< Current Values for Incoming RX EQ Controls from ASIC 1, offset: 0x60050 */ uint8_t RESERVED_169[2]; __I uint16_t LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0; /**< Current Values for Incoming RX CDR VCO Controls from ASIC 0, offset: 0x60054 */ uint8_t RESERVED_170[2]; __I uint16_t LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1; /**< Current Values for Incoming RX CDR VCO Controls from ASIC 1, offset: 0x60058 */ uint8_t RESERVED_171[2]; __I uint16_t LANE0_DIG_ASIC_RX_ASIC_OUT_0; /**< Current Values for Outgoing RX Status Controls from PHY 0, offset: 0x6005C */ uint8_t RESERVED_172[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2; /**< Override Values for Incoming RX EQ Controls from ASIC 2, offset: 0x60060 */ uint8_t RESERVED_173[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3; /**< Override Values for Incoming RX EQ Controls from ASIC 3, offset: 0x60064 */ uint8_t RESERVED_174[2]; __IO uint16_t LANE0_DIG_ASIC_TX_OVRD_MISC; /**< Override Values for Incoming TX MISC BUS from ASIC, offset: 0x60068 */ uint8_t RESERVED_175[2]; __IO uint16_t LANE0_DIG_ASIC_RX_OVRD_MISC; /**< Override Values for Incoming RX MISC BUS from ASIC, offset: 0x6006C */ uint8_t RESERVED_176[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0; /**< TX Power State Control for P0, offset: 0x60070 */ uint8_t RESERVED_177[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S; /**< TX Power State Control for P0S, offset: 0x60074 */ uint8_t RESERVED_178[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1; /**< TX Power State Control for P1, offset: 0x60078 */ uint8_t RESERVED_179[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2; /**< TX Power State Control for P2, offset: 0x6007C */ uint8_t RESERVED_180[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0; /**< TX Power UP Time 0, offset: 0x60080 */ uint8_t RESERVED_181[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1; /**< TX Power UP Time 1, offset: 0x60084 */ uint8_t RESERVED_182[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2; /**< TX Power UP Time 2, offset: 0x60088 */ uint8_t RESERVED_183[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3; /**< TX Power UP Time 3, offset: 0x6008C */ uint8_t RESERVED_184[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4; /**< TX Power UP Time 4, offset: 0x60090 */ uint8_t RESERVED_185[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_FIFO_BYPASS; /**< TX FIFO Bypass, offset: 0x60094 */ uint8_t RESERVED_186[2]; __IO uint16_t LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5; /**< TX Power UP Time 4, offset: 0x60098 */ uint8_t RESERVED_187[2]; __IO uint16_t LANE0_DIG_TX_LBERT_CTL; /**< Pattern Generator Controls, offset: 0x6009C */ uint8_t RESERVED_188[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0; /**< RX Power State Control for P0, offset: 0x600A0 */ uint8_t RESERVED_189[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S; /**< RX Power State Control for P0S, offset: 0x600A4 */ uint8_t RESERVED_190[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1; /**< RX Power State Control for P1, offset: 0x600A8 */ uint8_t RESERVED_191[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2; /**< RX Power State Control for P2, offset: 0x600AC */ uint8_t RESERVED_192[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0; /**< RX Power UP Time 0, offset: 0x600B0 */ uint8_t RESERVED_193[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1; /**< RX Power UP Time 1, offset: 0x600B4 */ uint8_t RESERVED_194[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2; /**< RX Power UP Time 2, offset: 0x600B8 */ uint8_t RESERVED_195[2]; __IO uint16_t LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3; /**< RX Power UP Control 0, offset: 0x600BC */ uint8_t RESERVED_196[2]; __IO uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0; /**< RX VCO Calibration Controls 0, offset: 0x600C0 */ uint8_t RESERVED_197[2]; __IO uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1; /**< RX VCO Calibration Controls 1, offset: 0x600C4 */ uint8_t RESERVED_198[2]; __IO uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2; /**< RX VCO Calibration Controls 2, offset: 0x600C8 */ uint8_t RESERVED_199[2]; __IO uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0; /**< RX Power UP Time 0, offset: 0x600CC */ uint8_t RESERVED_200[2]; __IO uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1; /**< RX Power UP Time 1, offset: 0x600D0 */ uint8_t RESERVED_201[2]; __I uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0; /**< RX VCO Status 0, offset: 0x600D4 */ uint8_t RESERVED_202[2]; __I uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1; /**< RX VCO Status 1, offset: 0x600D8 */ uint8_t RESERVED_203[2]; __I uint16_t LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2; /**< RX VCO Status 2, offset: 0x600DC */ uint8_t RESERVED_204[6]; __IO uint16_t LANE0_DIG_RX_LBERT_CTL; /**< Pattern Matcher Controls, offset: 0x600E4 */ uint8_t RESERVED_205[2]; __IO uint16_t LANE0_DIG_RX_LBERT_ERR; /**< Pattern Match Error Counter, offset: 0x600E8 */ uint8_t RESERVED_206[2]; __IO uint16_t LANE0_DIG_RX_CDR_CDR_CTL_0; /**< Control Bits for Receiver in Recovered Domain, offset: 0x600EC */ uint8_t RESERVED_207[2]; __IO uint16_t LANE0_DIG_RX_CDR_CDR_CTL_1; /**< CDR Control 1, offset: 0x600F0 */ uint8_t RESERVED_208[2]; __IO uint16_t LANE0_DIG_RX_CDR_CDR_CTL_2; /**< CDR Control 2, offset: 0x600F4 */ uint8_t RESERVED_209[2]; __IO uint16_t LANE0_DIG_RX_CDR_CDR_CTL_3; /**< CDR Control 3, offset: 0x600F8 */ uint8_t RESERVED_210[2]; __IO uint16_t LANE0_DIG_RX_CDR_CDR_CTL_4; /**< CDR Control 4, offset: 0x600FC */ uint8_t RESERVED_211[2]; __I uint16_t LANE0_DIG_RX_CDR_STAT; /**< Current Output Values to DPLL (PHUG, FRUG), offset: 0x60100 */ uint8_t RESERVED_212[2]; __IO uint16_t LANE0_DIG_RX_DPLL_FREQ; /**< Current Frequency Integrator Value, offset: 0x60104 */ uint8_t RESERVED_213[2]; __IO uint16_t LANE0_DIG_RX_DPLL_FREQ_BOUND_0; /**< Frequency Bounds for Incoming Data Stream 0, offset: 0x60108 */ uint8_t RESERVED_214[2]; __IO uint16_t LANE0_DIG_RX_DPLL_FREQ_BOUND_1; /**< Frequency Bounds for Incoming Data Stream 1, offset: 0x6010C */ uint8_t RESERVED_215[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0; /**< Adaptation Configuration 0, offset: 0x60110 */ uint8_t RESERVED_216[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1; /**< Adaptation Configuration 1, offset: 0x60114 */ uint8_t RESERVED_217[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2; /**< Adaptation Configuration 2, offset: 0x60118 */ uint8_t RESERVED_218[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3; /**< Adaptation Configuration 3, offset: 0x6011C */ uint8_t RESERVED_219[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4; /**< Adaptation Configuration 4, offset: 0x60120 */ uint8_t RESERVED_220[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5; /**< Adaptation Configuration 5, offset: 0x60124 */ uint8_t RESERVED_221[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6; /**< Adaptation Configuration 6, offset: 0x60128 */ uint8_t RESERVED_222[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7; /**< Adaptation Configuration 7, offset: 0x6012C */ uint8_t RESERVED_223[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8; /**< Adaptation Configuration 8, offset: 0x60130 */ uint8_t RESERVED_224[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9; /**< Adaptation Configuration 9, offset: 0x60134 */ uint8_t RESERVED_225[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG; /**< Reset Adaptation Configuration, offset: 0x60138 */ uint8_t RESERVED_226[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_ATT_STATUS; /**< Value of ATT Adaptation code, offset: 0x6013C */ uint8_t RESERVED_227[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_VGA_STATUS; /**< Value of VGA Adaptation Code, offset: 0x60140 */ uint8_t RESERVED_228[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_CTLE_STATUS; /**< Value of CTLE Adaptation Code, offset: 0x60144 */ uint8_t RESERVED_229[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS; /**< Value of DFE Tap1 Adaptation Code, offset: 0x60148 */ uint8_t RESERVED_230[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS; /**< Value of DFE Tap2 Adaptation Code, offset: 0x6014C */ uint8_t RESERVED_231[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS; /**< Value of DFE Tap3 Adaptation Code, offset: 0x60150 */ uint8_t RESERVED_232[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS; /**< Value of DFE Tap4 Adaptation Code, offset: 0x60154 */ uint8_t RESERVED_233[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS; /**< Value of DFE Tap5 Adaptation Code, offset: 0x60158 */ uint8_t RESERVED_234[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST; /**< Offset Values for RX DFE Data Even High vDAC, offset: 0x6015C */ uint8_t RESERVED_235[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST; /**< Offset Values for RX DFE Data Even Low vDAC, offset: 0x60160 */ uint8_t RESERVED_236[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST; /**< Offset Values for RX DFE Data Odd High vDAC, offset: 0x60164 */ uint8_t RESERVED_237[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST; /**< Offset Values for RX DFE Data Odd Low vDAC, offset: 0x60168 */ uint8_t RESERVED_238[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN; /**< Sets Values for RX SLICER CTRL EVEN Signals Going to ANA, offset: 0x6016C */ uint8_t RESERVED_239[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD; /**< Sets Values for RX SLICER CTRL ODD Signals Going to ANA, offset: 0x60170 */ uint8_t RESERVED_240[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST; /**< Offset Values for RX DFE Error Even vDAC, offset: 0x60174 */ uint8_t RESERVED_241[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST; /**< Offset Values for RX DFE Error Odd vDAC, offset: 0x60178 */ uint8_t RESERVED_242[2]; __I uint16_t LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL; /**< Value of Error Slicer Level, offset: 0x6017C */ uint8_t RESERVED_243[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST; /**< Offset Values for RX DFE By-Pass Even vDAC, offset: 0x60180 */ uint8_t RESERVED_244[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST; /**< Offset Values for RX DFE By-Pass Odd vDAC, offset: 0x60184 */ uint8_t RESERVED_245[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_RESET; /**< Adaptation Reset, offset: 0x60188 */ uint8_t RESERVED_246[2]; __IO uint16_t LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10; /**< Adaptation Configuration 10, offset: 0x6018C */ uint8_t RESERVED_247[2]; __IO uint16_t LANE0_DIG_RX_STAT_LD_VAL_1; /**< Stat Load Value for the Sample Counter 1, offset: 0x60190 */ uint8_t RESERVED_248[2]; __IO uint16_t LANE0_DIG_RX_STAT_DATA_MSK; /**< Stat Data Mask Bits [15:0], offset: 0x60194 */ uint8_t RESERVED_249[2]; __IO uint16_t LANE0_DIG_RX_STAT_MATCH_CTL0; /**< Stat Match Controls 0, offset: 0x60198 */ uint8_t RESERVED_250[2]; __IO uint16_t LANE0_DIG_RX_STAT_MATCH_CTL1; /**< Stat Match Controls 1, offset: 0x6019C */ uint8_t RESERVED_251[2]; __IO uint16_t LANE0_DIG_RX_STAT_STAT_CTL0; /**< Stat Controls 0, offset: 0x601A0 */ uint8_t RESERVED_252[2]; __IO uint16_t LANE0_DIG_RX_STAT_STAT_CTL1; /**< Stat Controls 1, offset: 0x601A4 */ uint8_t RESERVED_253[2]; __I uint16_t LANE0_DIG_RX_STAT_SMPL_CNT1; /**< Sample Counter 1 Status, offset: 0x601A8 */ uint8_t RESERVED_254[2]; __I uint16_t LANE0_DIG_RX_STAT_STAT_CNT_0; /**< Stat Counter 0 Status, offset: 0x601AC */ uint8_t RESERVED_255[2]; __I uint16_t LANE0_DIG_RX_STAT_STAT_CNT_1; /**< Stat Counter 1 Status, offset: 0x601B0 */ uint8_t RESERVED_256[2]; __I uint16_t LANE0_DIG_RX_STAT_STAT_CNT_2; /**< Stat Counter 2 Status, offset: 0x601B4 */ uint8_t RESERVED_257[2]; __I uint16_t LANE0_DIG_RX_STAT_STAT_CNT_3; /**< Stat Counter 3 Status, offset: 0x601B8 */ uint8_t RESERVED_258[2]; __I uint16_t LANE0_DIG_RX_STAT_STAT_CNT_4; /**< Stat Counter 4 Status, offset: 0x601BC */ uint8_t RESERVED_259[2]; __I uint16_t LANE0_DIG_RX_STAT_STAT_CNT_5; /**< Stat Counter 5 Status, offset: 0x601C0 */ uint8_t RESERVED_260[2]; __I uint16_t LANE0_DIG_RX_STAT_STAT_CNT_6; /**< Stat Counter 6 Status, offset: 0x601C4 */ uint8_t RESERVED_261[2]; __IO uint16_t LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL; /**< Calibration Comparator Control, offset: 0x601C8 */ uint8_t RESERVED_262[2]; __IO uint16_t LANE0_DIG_RX_STAT_MATCH_CTL2; /**< Stat Match Controls 2, offset: 0x601CC */ uint8_t RESERVED_263[2]; __IO uint16_t LANE0_DIG_RX_STAT_MATCH_CTL3; /**< Stat Match Controls 3, offset: 0x601D0 */ uint8_t RESERVED_264[2]; __IO uint16_t LANE0_DIG_RX_STAT_MATCH_CTL4; /**< Stat Match Controls 4, offset: 0x601D4 */ uint8_t RESERVED_265[2]; __IO uint16_t LANE0_DIG_RX_STAT_MATCH_CTL5; /**< Stat Match Controls 5, offset: 0x601D8 */ uint8_t RESERVED_266[2]; __IO uint16_t LANE0_DIG_RX_STAT_STAT_CTL2; /**< Stat Controls 2, offset: 0x601DC */ uint8_t RESERVED_267[2]; __IO uint16_t LANE0_DIG_RX_STAT_STAT_STOP; /**< Stat Stop, offset: 0x601E0 */ uint8_t RESERVED_268[2]; __IO uint16_t LANE0_DIG_ANA_TX_OVRD_OUT; /**< Override Values for TX Signals Going to ANA, offset: 0x601E4 */ uint8_t RESERVED_269[2]; __IO uint16_t LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT; /**< Override Value for TX termination Code Up Going to ANA, offset: 0x601E8 */ uint8_t RESERVED_270[2]; __IO uint16_t LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT; /**< Override Value for TX termination Down Code Going to ANA, offset: 0x601EC */ uint8_t RESERVED_271[2]; __IO uint16_t LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0; /**< Override Values for TX EQ Signals Going to ANA 0, offset: 0x601F0 */ uint8_t RESERVED_272[2]; __IO uint16_t LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1; /**< Override Values for TX EQ Signals Going to ANA 1, offset: 0x601F4 */ uint8_t RESERVED_273[2]; __IO uint16_t LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2; /**< Override Values for TX EQ Signals Going to ANA 2, offset: 0x601F8 */ uint8_t RESERVED_274[2]; __IO uint16_t LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3; /**< Override Values for TX EQ Signals Going to ANA 3, offset: 0x601FC */ uint8_t RESERVED_275[2]; __IO uint16_t LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4; /**< Override Values for TX EQ Signals Going to ANA 4, offset: 0x60200 */ uint8_t RESERVED_276[2]; __IO uint16_t LANE0_DIG_ANA_RX_CTL_OVRD_OUT; /**< Override Values for RX Control Signals Going to ANA, offset: 0x60204 */ uint8_t RESERVED_277[2]; __IO uint16_t LANE0_DIG_ANA_RX_PWR_OVRD_OUT; /**< Override Values for RX PWR UP/DN Signals Going to ANA, offset: 0x60208 */ uint8_t RESERVED_278[2]; __IO uint16_t LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0; /**< Override Values for RX VCO Signals Going to ANA 0, offset: 0x6020C */ uint8_t RESERVED_279[2]; __IO uint16_t LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1; /**< Override Values for RX VCO Signals Going to ANA 1, offset: 0x60210 */ uint8_t RESERVED_280[2]; __IO uint16_t LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2; /**< Override Values for RX VCO Signals Going to ANA 2, offset: 0x60214 */ uint8_t RESERVED_281[2]; __IO uint16_t LANE0_DIG_ANA_RX_CAL; /**< Sets Values for RX CAL Signals Going to ANA, offset: 0x60218 */ uint8_t RESERVED_282[2]; __IO uint16_t LANE0_DIG_ANA_RX_VDAC_RANGE_SEL; /**< Sets Values for RX DAC CTRL Value Going to ANA, offset: 0x6021C */ uint8_t RESERVED_283[2]; __IO uint16_t LANE0_DIG_ANA_RX_DAC_CTRL; /**< Sets Values for RX DAC CTRL Value Going to ANA, offset: 0x60220 */ uint8_t RESERVED_284[2]; __IO uint16_t LANE0_DIG_ANA_RX_ANA_RTRIM; /**< Set Value for RX RTRIM Going to ANA, offset: 0x60224 */ uint8_t RESERVED_285[2]; __IO uint16_t LANE0_DIG_ANA_RX_DAC_CTRL_OVRD; /**< Overrides RX DAC CTRL Bus (EN/VAL/SEL) Going to ANA, offset: 0x60228 */ uint8_t RESERVED_286[2]; __IO uint16_t LANE0_DIG_ANA_RX_DAC_CTRL_SEL; /**< Sets Values for RX DAC CTRL Select Signal Going to ANA, offset: 0x6022C */ uint8_t RESERVED_287[2]; __IO uint16_t LANE0_DIG_ANA_RX_AFE_ATT_VGA; /**< Value for RX AFE ATT & VGA Signals Going to ANA, offset: 0x60230 */ uint8_t RESERVED_288[2]; __IO uint16_t LANE0_DIG_ANA_RX_AFE_CTLE; /**< Values for RX AFE CTLE Signals Going to ANA, offset: 0x60234 */ uint8_t RESERVED_289[2]; __IO uint16_t LANE0_DIG_ANA_RX_SCOPE; /**< Values for RX SCOPE Signals Going to ANA, offset: 0x60238 */ uint8_t RESERVED_290[2]; __IO uint16_t LANE0_DIG_ANA_RX_SLICER_CTRL; /**< Sets Values for RX Slicer Ctrl Signals Going to ANA, offset: 0x6023C */ uint8_t RESERVED_291[2]; __IO uint16_t LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST; /**< Sets Values for RX ANA IQ PHASE Adjust Signal Going to ANA, offset: 0x60240 */ uint8_t RESERVED_292[2]; __IO uint16_t LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN; /**< Sets Values for RX ANA IQ SENSE Signal, offset: 0x60244 */ uint8_t RESERVED_293[2]; __IO uint16_t LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN; /**< DAC Control Enable Signal, offset: 0x60248 */ uint8_t RESERVED_294[2]; __IO uint16_t LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE; /**< AFE Update Enable Signal, offset: 0x6024C */ uint8_t RESERVED_295[2]; __IO uint16_t LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK; /**< Phase Adjust Clock Signal, offset: 0x60250 */ uint8_t RESERVED_296[2]; __I uint16_t LANE0_DIG_ANA_STATUS_0; /**< Lane Input Status 0, offset: 0x60254 */ uint8_t RESERVED_297[2]; __I uint16_t LANE0_DIG_ANA_STATUS_1; /**< Lane Input Status 1, offset: 0x60258 */ uint8_t RESERVED_298[2]; __IO uint16_t LANE0_ANA_TX_OVRD_MEAS; /**< TX_OVRD_MEAS, offset: 0x6025C */ uint8_t RESERVED_299[2]; __IO uint16_t LANE0_ANA_TX_PWR_OVRD; /**< TX_PWR_OVRD, offset: 0x60260 */ uint8_t RESERVED_300[2]; __IO uint16_t LANE0_ANA_TX_ALT_BUS; /**< TX_ALT_BUS, offset: 0x60264 */ uint8_t RESERVED_301[10]; __IO uint16_t LANE0_ANA_TX_VBOOST; /**< TX_VBOOST, offset: 0x60270 */ uint8_t RESERVED_302[2]; __IO uint16_t LANE0_ANA_TX_TERM_CODE_DN; /**< TX_TERM_CODE_DN, offset: 0x60274 */ uint8_t RESERVED_303[2]; __IO uint16_t LANE0_ANA_TX_TERM_CODE_UP; /**< TX_TERM_CODE_UP, offset: 0x60278 */ uint8_t RESERVED_304[2]; __IO uint16_t LANE0_ANA_TX_IBOOST_CODE; /**< TX_IBOOST_CODE, offset: 0x6027C */ uint8_t RESERVED_305[2]; __IO uint16_t LANE0_ANA_TX_OVRD_CLK; /**< TX_OVRD_CLK, offset: 0x60280 */ uint8_t RESERVED_306[2]; __IO uint16_t LANE0_ANA_TX_MISC; /**< TX_MISC, offset: 0x60284 */ uint8_t RESERVED_307[6]; __IO uint16_t LANE0_ANA_RX_DCC_OVRD; /**< RX_DCC_OVRD, offset: 0x6028C */ uint8_t RESERVED_308[2]; __IO uint16_t LANE0_ANA_RX_PWR_CTRL1; /**< RX_PWR_CTRL1, offset: 0x60290 */ uint8_t RESERVED_309[6]; __IO uint16_t LANE0_ANA_RX_CDR_AFE; /**< RX_CDR_AFE, offset: 0x60298 */ uint8_t RESERVED_310[2]; __IO uint16_t LANE0_ANA_RX_PWR_CTRL2; /**< RX_PWR_CTRL2, offset: 0x6029C */ uint8_t RESERVED_311[2]; __IO uint16_t LANE0_ANA_RX_MISC_OVRD; /**< RX_MISC_OVRD, offset: 0x602A0 */ uint8_t RESERVED_312[2]; __IO uint16_t LANE0_ANA_RX_CAL_MUXA; /**< RX_CAL_MUXA, offset: 0x602A4 */ uint8_t RESERVED_313[10]; __IO uint16_t LANE0_ANA_RX_CAL_MUXB; /**< RX_CAL_MUXB, offset: 0x602B0 */ uint8_t RESERVED_314[2]; __IO uint16_t LANE0_ANA_RX_TERM; /**< RX_TERM, offset: 0x602B4 */ uint8_t RESERVED_315[2]; __IO uint16_t LANE0_ANA_RX_SLC_CTRL; /**< RX_SLC_CTRL, offset: 0x602B8 */ uint8_t RESERVED_316[6]; __IO uint16_t LANE0_ANA_RX_CDR_VCO_CTRL; /**< RX_CDR_VCO_CTRL, offset: 0x602C0 */ uint8_t RESERVED_317[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_TX_OVRD_IN; /**< Override Values for Incoming TX Controls from PCS, offset: 0x602C4 */ uint8_t RESERVED_318[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1; /**< Override Values for Incoming TX Controls from PCS 1, offset: 0x602C8 */ uint8_t RESERVED_319[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_TX_PCS_IN; /**< Current Values for Incoming TX Controls from PCS (Pre-Override Input Monitor), offset: 0x602CC */ uint8_t RESERVED_320[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT; /**< Override Values for Outgoing TX Controls to PCS, offset: 0x602D0 */ uint8_t RESERVED_321[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_TX_PCS_OUT; /**< Current Values for Outgoing TX Status Controls from Raw PCS (Pre-Override Output Monitor), offset: 0x602D4 */ uint8_t RESERVED_322[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN; /**< Override Values for Incoming RX Controls from PCS, offset: 0x602D8 */ uint8_t RESERVED_323[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1; /**< Override Values for Incoming RX Controls from PCS 1, offset: 0x602DC */ uint8_t RESERVED_324[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2; /**< Override Values for Incoming RX Controls from PCS 2, offset: 0x602E0 */ uint8_t RESERVED_325[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2; /**< ATE Override Input to Control Top-Level Inputs 3, offset: 0x602E4 */ uint8_t RESERVED_326[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_IN; /**< Current Values for Incoming RX Controls from PCS (Monitor on Post ATE Override), offset: 0x602E8 */ uint8_t RESERVED_327[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1; /**< Current Values for Incoming RX Controls from PCS 1 (Monitor on Pre-Override Signals), offset: 0x602EC */ uint8_t RESERVED_328[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2; /**< Current Values for Incoming RX Controls from PCS 2 (Monitor on the Pre-Override Signals), offset: 0x602F0 */ uint8_t RESERVED_329[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3; /**< Current Values for Incoming RX Controls from PCS 3 (Monitor on the Pre-Override Signals), offset: 0x602F4 */ uint8_t RESERVED_330[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4; /**< Current Values for Incoming RX Controls from PCS 4 (Monitor on the Pre-Override Signals), offset: 0x602F8 */ uint8_t RESERVED_331[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT; /**< Override Values for Outgoing RX Controls to PCS, offset: 0x602FC */ uint8_t RESERVED_332[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_OUT; /**< Current Values for Outgoing RX Status Controls from Raw PCS, offset: 0x60300 */ uint8_t RESERVED_333[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK; /**< RX Adaptation Acknowledge, offset: 0x60304 */ uint8_t RESERVED_334[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM; /**< RX Adaptation Figure of Merit, offset: 0x60308 */ uint8_t RESERVED_335[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR; /**< RX Calculated Direction for TX-Pre, offset: 0x6030C */ uint8_t RESERVED_336[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR; /**< RX Calculated Direction for TX-Main, offset: 0x60310 */ uint8_t RESERVED_337[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR; /**< RX Calculated Direction for TX-Post, offset: 0x60314 */ uint8_t RESERVED_338[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_LANE_NUMBER; /**< Current Lane Number, offset: 0x60318 */ uint8_t RESERVED_339[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN; /**< ATE Override Input to Control Top-Level Inputs 1, offset: 0x6031C */ uint8_t RESERVED_340[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1; /**< Overrides the RX Output Clocks during the PHY Initialization 1, offset: 0x60320 */ uint8_t RESERVED_341[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4; /**< Override Values for Incoming RX Controls from PCS 4, offset: 0x60324 */ uint8_t RESERVED_342[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5; /**< RX Adaptation Mode Override, offset: 0x60328 */ uint8_t RESERVED_343[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5; /**< Current Values for Incoming RX Controls from PCS 5, offset: 0x6032C */ uint8_t RESERVED_344[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6; /**< Override Register for RX IQ Setting, offset: 0x60330 */ uint8_t RESERVED_345[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1; /**< Override Values for Incoming RX EQ Controls from PCS 1, offset: 0x60334 */ uint8_t RESERVED_346[2]; __I uint16_t RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6; /**< Current Values for Incoming RX Controls from PCS 6, offset: 0x60338 */ uint8_t RESERVED_347[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1; /**< ATE Override Input to Control Top-Level Inputs 2, offset: 0x6033C */ uint8_t RESERVED_348[2]; __IO uint16_t RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2; /**< Override Values for Incoming RX EQ Controls from PCS 2, offset: 0x60340 */ uint8_t RESERVED_349[2]; __IO uint16_t RAWLANE0_DIG_FSM_FSM_OVRD_CTL; /**< FSM Override Control, offset: 0x60344 */ uint8_t RESERVED_350[2]; __IO uint16_t RAWLANE0_DIG_FSM_FSM_JMP_BANK; /**< FSM Jump Bank, offset: 0x60348 */ uint8_t RESERVED_351[2]; __IO uint16_t RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0; /**< FSM Breakpoint 0 on SRAM Address for Debugging, offset: 0x6034C */ uint8_t RESERVED_352[2]; __IO uint16_t RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1; /**< FSM Breakpoint 1 on SRAM Address for Debugging, offset: 0x60350 */ uint8_t RESERVED_353[2]; __I uint16_t RAWLANE0_DIG_FSM_MEM_ADDR_MON; /**< Memory Address Monitor, offset: 0x60354 */ uint8_t RESERVED_354[2]; __I uint16_t RAWLANE0_DIG_FSM_STATUS_MON; /**< FSM Status Monitor, offset: 0x60358 */ uint8_t RESERVED_355[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL; /**< Status of Fast RX Start Up Calibration, offset: 0x6035C */ uint8_t RESERVED_356[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_RX_ADAPT; /**< Status of Fast RX Adaptation, offset: 0x60360 */ uint8_t RESERVED_357[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_SUP; /**< Status of Fast Support Block, offset: 0x60364 */ uint8_t RESERVED_358[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE; /**< Status of Fast TX Common-Mode Charge-Up, offset: 0x60368 */ uint8_t RESERVED_359[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_TX_RXDET; /**< Status of Fast TX Detect RX, offset: 0x6036C */ uint8_t RESERVED_360[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_RX_PWRUP; /**< Status of Fast RX Power-Up, offset: 0x60370 */ uint8_t RESERVED_361[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT; /**< Status of Fast RX VCO Wait Times, offset: 0x60374 */ uint8_t RESERVED_362[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL; /**< Status of Fast RX VCO Calibration, offset: 0x60378 */ uint8_t RESERVED_363[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT; /**< Status of Fast RX Continuous Calibration/Adaptation, offset: 0x6037C */ uint8_t RESERVED_364[2]; __I uint16_t RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT; /**< Status of Fast RX Continuous Adaptation, offset: 0x60380 */ uint8_t RESERVED_365[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL; /**< Status of RX AFE Startup Calibration, offset: 0x60384 */ uint8_t RESERVED_366[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL; /**< Status of RX DFE Startup Calibration, offset: 0x60388 */ uint8_t RESERVED_367[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL; /**< Status of DFE Extended Startup Calibration, offset: 0x6038C */ uint8_t RESERVED_368[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP; /**< Status of RX IQ Fixed Offset, offset: 0x60390 */ uint8_t RESERVED_369[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL; /**< Status of RX IQ Startup Calibration, offset: 0x60394 */ uint8_t RESERVED_370[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT; /**< Status of RX AFE Startup Adaptation, offset: 0x60398 */ uint8_t RESERVED_371[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT; /**< Status of RX DFE Startup Adaptation, offset: 0x6039C */ uint8_t RESERVED_372[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT; /**< Status of RX IO Startup Adaptation, offset: 0x603A0 */ uint8_t RESERVED_373[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL; /**< Status of RX Continuous Phase Calibration, offset: 0x603A4 */ uint8_t RESERVED_374[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL; /**< Status of RX AFE Continuous Calibration, offset: 0x603A8 */ uint8_t RESERVED_375[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT; /**< Status of RX Reference Level Continuous Adaptation, offset: 0x603AC */ uint8_t RESERVED_376[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT; /**< Status of RX VGA Continuous Adaptation, offset: 0x603B0 */ uint8_t RESERVED_377[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL; /**< Status of RX Phase Startup Calibration, offset: 0x603B4 */ uint8_t RESERVED_378[2]; __I uint16_t RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL; /**< Status of RX Phase Extended Startup Calibration, offset: 0x603B8 */ uint8_t RESERVED_379[2]; __IO uint16_t RAWLANE0_DIG_FSM_FW_STATES_1; /**< Stores Various States for Firmware - 2, offset: 0x603BC */ uint8_t RESERVED_380[2]; __IO uint16_t RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST; /**< Offset Value for RX AFE ATT iDAC, offset: 0x603C0 */ uint8_t RESERVED_381[2]; __IO uint16_t RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST; /**< Offset Value for RX AFE CTLE iDAC, offset: 0x603C4 */ uint8_t RESERVED_382[2]; __IO uint16_t RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST; /**< Offset Values for RX AFE VGA1 iDAC, offset: 0x603C8 */ uint8_t RESERVED_383[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST; /**< Offset Values for RX DFE Phase Even vDAC, offset: 0x603CC */ uint8_t RESERVED_384[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST; /**< Offset Values for RX DFE Phase Odd vDAC, offset: 0x603D0 */ uint8_t RESERVED_385[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST; /**< Offset Values for RX DFE Phase Even Low vDAC, offset: 0x603D4 */ uint8_t RESERVED_386[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST; /**< Offset Values for RX DFE Phase Odd Low vDAC, offset: 0x603D8 */ uint8_t RESERVED_387[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_PHSADJ_LIN; /**< RX Phase Adjust Linear Value, offset: 0x603DC */ uint8_t RESERVED_388[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST; /**< Offset Values for RX DFE Data Even High vDAC, offset: 0x603E0 */ uint8_t RESERVED_389[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST; /**< Offset Values for RX DFE Data Even Low vDAC, offset: 0x603E4 */ uint8_t RESERVED_390[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST; /**< Offset Values for RX DFE Data Odd High vDAC, offset: 0x603E8 */ uint8_t RESERVED_391[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST; /**< Offset Values for RX DFE Data Odd Low vDAC, offset: 0x603EC */ uint8_t RESERVED_392[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST; /**< Offset Values for RX DFE By-Pass Even vDAC, offset: 0x603F0 */ uint8_t RESERVED_393[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST; /**< Offset Values for RX DFE By-Pass Odd vDAC, offset: 0x603F4 */ uint8_t RESERVED_394[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST; /**< Offset Values for RX DFE Error Even vDAC, offset: 0x603F8 */ uint8_t RESERVED_395[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST; /**< Offset Values for RX DFE Error Odd vDAC, offset: 0x603FC */ uint8_t RESERVED_396[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_CAL_IQ; /**< Value for RX Calibrated IQ Phase, offset: 0x60400 */ uint8_t RESERVED_397[6]; __IO uint16_t RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL; /**< Set to Skip Firmware Mission-Mode Algorithms, offset: 0x60408 */ uint8_t RESERVED_398[2]; __IO uint16_t RAWLANE0_DIG_AON_INIT_PWRUP_DONE; /**< Initial Power-Up Done Status, offset: 0x6040C */ uint8_t RESERVED_399[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_ATT; /**< RX Adapted Value of ATT, offset: 0x60410 */ uint8_t RESERVED_400[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_VGA; /**< RX Adapted Value of VGA, offset: 0x60414 */ uint8_t RESERVED_401[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_CTLE; /**< RX Adapted Value of CTLE, offset: 0x60418 */ uint8_t RESERVED_402[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1; /**< RX Adapted Value of DFE TAP1, offset: 0x6041C */ uint8_t RESERVED_403[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2; /**< RX Adapted Value of DFE TAP2, offset: 0x60420 */ uint8_t RESERVED_404[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3; /**< RX Adapted Value of DFE TAP3, offset: 0x60424 */ uint8_t RESERVED_405[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4; /**< RX Adapted Value of DFE TAP4, offset: 0x60428 */ uint8_t RESERVED_406[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5; /**< RX Adapted Value of DFE TAP5, offset: 0x6042C */ uint8_t RESERVED_407[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_IQ; /**< RX Adapted Value of IQ for Bank 0, offset: 0x60430 */ uint8_t RESERVED_408[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_REF_ERR; /**< RX Adapted Value of Reference Level for Error Slicer for Bank 0, offset: 0x60434 */ uint8_t RESERVED_409[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADAPT_DONE; /**< RX Adaptation Done Status, offset: 0x60438 */ uint8_t RESERVED_410[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_ATT_B1; /**< RX Adapted Value of ATT for Bank 1, offset: 0x6043C */ uint8_t RESERVED_411[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_VGA_B1; /**< RX Adapted Value of VGA for Bank 1, offset: 0x60440 */ uint8_t RESERVED_412[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1; /**< RX Adapted Value of CTLE for Bank 1, offset: 0x60444 */ uint8_t RESERVED_413[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_B1; /**< RX Adapted Value of DFE TAP1 for Bank 1, offset: 0x60448 */ uint8_t RESERVED_414[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_B1; /**< RX Adapted Value of DFE TAP2 for Bank 1, offset: 0x6044C */ uint8_t RESERVED_415[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_B1; /**< RX Adapted Value of DFE TAP3 for Bank 1, offset: 0x60450 */ uint8_t RESERVED_416[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_B1; /**< RX Adapted Value of DFE TAP4 for Bank 1, offset: 0x60454 */ uint8_t RESERVED_417[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_B1; /**< RX Adapted Value of DFE TAP5 for Bank 1, offset: 0x60458 */ uint8_t RESERVED_418[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_IQ_B1; /**< RX Adapted Value of IQ for Bank 1, offset: 0x6045C */ uint8_t RESERVED_419[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1; /**< RX Adapted Value of Reference Level for Error Slicer for Bank 1, offset: 0x60460 */ uint8_t RESERVED_420[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1; /**< RX Adaptation Done Status for Bank 1, offset: 0x60464 */ uint8_t RESERVED_421[6]; __IO uint16_t RAWLANE0_DIG_AON_FW_STATES_0; /**< Stores Various States for Firmware - 1, offset: 0x6046C */ uint8_t RESERVED_422[2]; __IO uint16_t RAWLANE0_DIG_AON_TXRX_OVRD_IN; /**< Override Values for Incoming AON TX/RX Controls from PCS, offset: 0x60470 */ uint8_t RESERVED_423[2]; __IO uint16_t RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL; /**< Equalization Direction Polarity Setting in PCS RAW, offset: 0x60474 */ uint8_t RESERVED_424[2]; __IO uint16_t RAWLANE0_DIG_AON_TX_PRE_DIV; /**< TX Pre Threshold Div, offset: 0x60478 */ uint8_t RESERVED_425[2]; __IO uint16_t RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD; /**< TX Main ATT High and Low Threshold, offset: 0x6047C */ uint8_t RESERVED_426[2]; __IO uint16_t RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD; /**< TX Main VGA High and Low Threshold, offset: 0x60480 */ uint8_t RESERVED_427[2]; __IO uint16_t RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD; /**< TX Post Boost High and Low Threshold, offset: 0x60484 */ uint8_t RESERVED_428[2]; __IO uint16_t RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD; /**< TX Post Tap1 High and Low Threshold, offset: 0x60488 */ uint8_t RESERVED_429[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_CAL_REF_EE_VDAC_OFST; /**< Value for Reference Level Error Even Slicer, offset: 0x6048C */ uint8_t RESERVED_430[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_CAL_REF_EO_VDAC_OFST; /**< Value for Reference Level Error Odd Slicer, offset: 0x60490 */ uint8_t RESERVED_431[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST; /**< Value for DFE Error Even Low and High Slicer in Mission Mode, offset: 0x60494 */ uint8_t RESERVED_432[2]; __IO uint16_t RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST; /**< Value for DFE Error Odd Low and High Slicer in Mission Mode, offset: 0x60498 */ uint8_t RESERVED_433[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_ERR_SLC_MODE; /**< RX Adaptation Error Slicer Mode for Reference-Level Calibration, offset: 0x6049C */ uint8_t RESERVED_434[2]; __IO uint16_t RAWLANE0_DIG_AON_SETUP_REF_CTLE_IDAC_OFST; /**< Offset Value for AFE CTLE IDAC During Reference-Level Calibration, offset: 0x604A0 */ uint8_t RESERVED_435[2]; __IO uint16_t RAWLANE0_DIG_AON_SETUP_REF_VGA1_IDAC_OFST; /**< Offset Value for AFE VGA1 IDAC During Reference-Level Calibration, offset: 0x604A4 */ uint8_t RESERVED_436[2]; __IO uint16_t RAWLANE0_DIG_AON_SETUP_SLC_VGA1_IDAC_OFST; /**< Offset Value for AFE VGA1 for Slicer Setup Calibration, offset: 0x604A8 */ uint8_t RESERVED_437[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL; /**< RX CDR Detector Control, offset: 0x604AC */ uint8_t RESERVED_438[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_CDR_RECOVERY_TIME; /**< RX CDR Recovery Time in Reference Clock for the Intended PPM, offset: 0x604B0 */ uint8_t RESERVED_439[2]; __IO uint16_t RAWLANE0_DIG_AON_MEM_BREAKPOINT_2; /**< FSM Breakpoint 2 on SRAM Address for Debugging, offset: 0x604B4 */ uint8_t RESERVED_440[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_0; /**< Adaptation Control 0, offset: 0x604B8 */ uint8_t RESERVED_441[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_1; /**< Adaptation Control 1, offset: 0x604BC */ uint8_t RESERVED_442[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ; /**< Reset Routine Request, offset: 0x604C0 */ uint8_t RESERVED_443[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ; /**< RX Reset Interrupt, offset: 0x604C4 */ uint8_t RESERVED_444[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ; /**< RX Request Interrupt, offset: 0x604C8 */ uint8_t RESERVED_445[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ; /**< RX Rate Change Interrupt Request, offset: 0x604CC */ uint8_t RESERVED_446[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ; /**< RX P-State Change Interrupt Request, offset: 0x604D0 */ uint8_t RESERVED_447[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ; /**< RX Adaptation Request Interrupt, offset: 0x604D4 */ uint8_t RESERVED_448[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ; /**< RX Adaptation Disable Interrupt, offset: 0x604D8 */ uint8_t RESERVED_449[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR; /**< RX-Reset Interrupt Clear, offset: 0x604DC */ uint8_t RESERVED_450[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR; /**< RX Request Interrupt Clear, offset: 0x604E0 */ uint8_t RESERVED_451[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR; /**< RX Rate Change Interrupt Clear, offset: 0x604E4 */ uint8_t RESERVED_452[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR; /**< RX P-State Change Interrupt Clear, offset: 0x604E8 */ uint8_t RESERVED_453[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR; /**< RX Adaptation Request Interrupt Clear, offset: 0x604EC */ uint8_t RESERVED_454[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR; /**< RX Adaptation Disable Interrupt Clear, offset: 0x604F0 */ uint8_t RESERVED_455[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_IRQ_MASK; /**< Interrupt Mask, offset: 0x604F4 */ uint8_t RESERVED_456[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ; /**< MPLLA/B Re-Calibration Interrupt, offset: 0x604F8 */ uint8_t RESERVED_457[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_CLR; /**< MPLL Re-Calibration Interrupt Clear, offset: 0x604FC */ uint8_t RESERVED_458[2]; __I uint16_t RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ; /**< RX IQ Interrupt, offset: 0x60500 */ uint8_t RESERVED_459[2]; __IO uint16_t RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_CLR; /**< RX IQ Interrupt Clear, offset: 0x60504 */ uint8_t RESERVED_460[2]; __IO uint16_t RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN; /**< Override Values for Incoming LANE Controls, offset: 0x60508 */ uint8_t RESERVED_461[2]; __IO uint16_t RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT; /**< Override Values for Outgoing LANE Controls, offset: 0x6050C */ uint8_t RESERVED_462[2]; __IO uint16_t RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN; /**< Override Values for Incoming SUP Controls from PMA, offset: 0x60510 */ uint8_t RESERVED_463[2]; __I uint16_t RAWLANE0_DIG_PMA_XF_SUP_PMA_IN; /**< Current Values for Coming SUP Status Controls from PMA, offset: 0x60514 */ uint8_t RESERVED_464[2]; __IO uint16_t RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT; /**< Override Values for Outgoing TX Controls to PMA, offset: 0x60518 */ uint8_t RESERVED_465[2]; __I uint16_t RAWLANE0_DIG_PMA_XF_TX_PMA_IN; /**< Current Values for Coming TX Status Controls from PMA, offset: 0x6051C */ uint8_t RESERVED_466[2]; __IO uint16_t RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT; /**< Override Values for Outgoing RX Controls to PMA, offset: 0x60520 */ uint8_t RESERVED_467[2]; __I uint16_t RAWLANE0_DIG_PMA_XF_RX_PMA_IN; /**< Current Values for coming RX Status Controls from PMA, offset: 0x60524 */ uint8_t RESERVED_468[2]; __IO uint16_t RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL; /**< Lane Rtune Controls, offset: 0x60528 */ uint8_t RESERVED_469[2]; __IO uint16_t RAWLANE0_DIG_PMA_XF_RX_OVRD_IN; /**< Override Values for Incoming RX Controls from PMA, offset: 0x6052C */ uint8_t RESERVED_470[2]; __I uint16_t RAWLANE0_DIG_PMA_XF_SRAM_REC_EN; /**< SRAM Record Enable, offset: 0x60530 */ uint8_t RESERVED_471[2]; __IO uint16_t RAWLANE0_DIG_TX_CTL_TX_FSM_CTL; /**< TX FSM Control, offset: 0x60534 */ uint8_t RESERVED_472[2]; __IO uint16_t RAWLANE0_DIG_TX_CTL_TX_CLK_CTL; /**< Select Clock to Act as TX Input Clock, offset: 0x60538 */ uint8_t RESERVED_473[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_FSM_CTL; /**< RX FSM Control, offset: 0x6053C */ uint8_t RESERVED_474[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL; /**< RX LOS Mask Control, offset: 0x60540 */ uint8_t RESERVED_475[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL; /**< RX Data Enable Override Control, offset: 0x60544 */ uint8_t RESERVED_476[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS; /**< RX Continuous Offset Cancellation Status, offset: 0x60548 */ uint8_t RESERVED_477[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS; /**< RX Continuous Adaptation Status, offset: 0x6054C */ uint8_t RESERVED_478[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE; /**< RX Adaptation Mode, offset: 0x60550 */ uint8_t RESERVED_479[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_RX_ADAPT_SEL; /**< Select Between Two Banks Adaptation Settings for RX Adaptation, offset: 0x60554 */ uint8_t RESERVED_480[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT; /**< RX CDR PPM Drift on RX Clock, offset: 0x60558 */ uint8_t RESERVED_481[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_RX_CDR_DET_STATUS; /**< RX CDR Detector Status, offset: 0x6055C */ uint8_t RESERVED_482[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL; /**< Values for Outgoing RX Controls to PMA, offset: 0x60560 */ uint8_t RESERVED_483[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_RX_PMA_EQ_IQ; /**< RX PMA Equalization IQ Phase Value, offset: 0x60564 */ uint8_t RESERVED_484[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN; /**< Enable RX Adapt Mode Override, offset: 0x60568 */ uint8_t RESERVED_485[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_EN; /**< Enable Using Four Different RX Adaptation Modes, offset: 0x6056C */ uint8_t RESERVED_486[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_ADAPT_MM_FOM; /**< RX Adaptation Mission-Mode Figure of Merit, offset: 0x60570 */ uint8_t RESERVED_487[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_ADAPT_STARTUP_FOM; /**< RX Adaptation Startup Figure of Merit (Base Mode or Extended Mode), offset: 0x60574 */ uint8_t RESERVED_488[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_EVEN; /**< RX Adapted Value of Reference Level for Error Even Slicer, offset: 0x60578 */ uint8_t RESERVED_489[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_ODD; /**< RX Adapted Value of Reference Level for Error Odd Slicer, offset: 0x6057C */ uint8_t RESERVED_490[2]; __I uint16_t RAWLANE0_DIG_RX_CTL_RX_PHSADJ_MAP; /**< RX Phase Adjust Mapped Value, offset: 0x60580 */ uint8_t RESERVED_491[2]; __IO uint16_t RAWLANE0_DIG_RX_CTL_RX_DAC_IN_USE; /**< State of the DAC Interface, offset: 0x60584 */ uint8_t RESERVED_492[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_2; /**< Adaptation Control 2, offset: 0x60588 */ uint8_t RESERVED_493[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_3; /**< Adaptation Control 3, offset: 0x6058C */ uint8_t RESERVED_494[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_4; /**< Adaptation Control 4, offset: 0x60590 */ uint8_t RESERVED_495[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_5; /**< Adaptation Control 5, offset: 0x60594 */ uint8_t RESERVED_496[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_6; /**< Adaptation Control 6, offset: 0x60598 */ uint8_t RESERVED_497[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_7; /**< Adaptation Control 7, offset: 0x6059C */ uint8_t RESERVED_498[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_8; /**< Adaptation Control 8, offset: 0x605A0 */ uint8_t RESERVED_499[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_9; /**< Adaptation Control 9, offset: 0x605A4 */ uint8_t RESERVED_500[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_10; /**< Adaptation Control 10, offset: 0x605A8 */ uint8_t RESERVED_501[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_11; /**< Adaptation Control 11, offset: 0x605AC */ uint8_t RESERVED_502[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_12; /**< Adaptation Control 12, offset: 0x605B0 */ uint8_t RESERVED_503[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_13; /**< Adaptation Control 13, offset: 0x605B4 */ uint8_t RESERVED_504[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_14; /**< Adaptation Control 14, offset: 0x605B8 */ uint8_t RESERVED_505[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_15; /**< Adaptation Control 15, offset: 0x605BC */ uint8_t RESERVED_506[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_16; /**< Adaptation Control 16, offset: 0x605C0 */ uint8_t RESERVED_507[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_17; /**< Adaptation Control 17, offset: 0x605C4 */ uint8_t RESERVED_508[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_18; /**< Adaptation Control 18, offset: 0x605C8 */ uint8_t RESERVED_509[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_19; /**< Adaptation Control 19, offset: 0x605CC */ uint8_t RESERVED_510[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_20; /**< Adaptation Control 20, offset: 0x605D0 */ uint8_t RESERVED_511[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_21; /**< Adaptation Control 21, offset: 0x605D4 */ uint8_t RESERVED_512[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_22; /**< Adaptation Control 22, offset: 0x605D8 */ uint8_t RESERVED_513[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_23; /**< Adaptation Control 23, offset: 0x605DC */ uint8_t RESERVED_514[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_24; /**< Adaptation Control 24, offset: 0x605E0 */ uint8_t RESERVED_515[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_25; /**< Adaptation Control 25, offset: 0x605E4 */ uint8_t RESERVED_516[2]; __IO uint16_t RAWLANE0_DIG_AON_ADPT_CTL_26; /**< Adaptation Control 26, offset: 0x605E8 */ uint8_t RESERVED_517[2]; __IO uint16_t RAWLANE0_DIG_AON_SRAM_REC_CTRL; /**< SRAM Record Control, offset: 0x605EC */ uint8_t RESERVED_518[2]; __IO uint16_t RAWLANE0_DIG_AON_SRAM_REC_ADDR; /**< Current SRAM Recording Address, offset: 0x605F0 */ uint8_t RESERVED_519[2]; __IO uint16_t RAWLANE0_DIG_AON_SRAM_REC_ITER; /**< Current Iteration Count for SRAM Recording, offset: 0x605F4 */ uint8_t RESERVED_520[6]; __IO uint16_t RAWLANE0_DIG_AON_RX_IQ_CTL; /**< RX IQ Adaptation Control 1, offset: 0x605FC */ uint8_t RESERVED_521[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_IQ_CTL_1; /**< RX IQ Adaptation Control 2, offset: 0x60600 */ uint8_t RESERVED_522[2]; __IO uint16_t RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT; /**< RX IQ Adaptation Offset Limit, offset: 0x60604 */ uint8_t RESERVED_523[129530]; struct { /* offset: 0x80000, array step: index*0x400, index2*0x80, index3*0x4 */ __I uint16_t RAWMEM_D_ROM_CMN_B_R; /**< Common Memory #0, Bank #0, Reg #0..Common Memory #63, Bank #7, Reg #31, array offset: 0x80000, array step: index*0x400, index2*0x80, index3*0x4 */ uint8_t RESERVED_0[2]; } RAWMEM_D_ROM_CMNX_BY_RZ[64][8][32]; uint8_t RESERVED_524[65536]; struct { /* offset: 0xA0000, array step: index*0x400, index2*0x80, index3*0x4 */ __IO uint16_t RAWMEM_D_RAM_CMN_B_R; /**< Common Memory #0, Bank #0, Reg #0..Common Memory #63, Bank #7, Reg #31, array offset: 0xA0000, array step: index*0x400, index2*0x80, index3*0x4 */ uint8_t RESERVED_0[2]; } RAWMEM_D_RAM_CMNX_BY_RZ[64][8][32]; } ENET_PHY_Type; /* ---------------------------------------------------------------------------- -- ENET_PHY Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_Register_Masks ENET_PHY Register Masks * @{ */ /*! @name SUP_DIG_IDCODE_LO - Low 16 Bits of IDCODE */ /*! @{ */ #define ENET_PHY_SUP_DIG_IDCODE_LO_VAL_MASK (0xFFFFU) #define ENET_PHY_SUP_DIG_IDCODE_LO_VAL_SHIFT (0U) /*! VAL - VAL */ #define ENET_PHY_SUP_DIG_IDCODE_LO_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_IDCODE_LO_VAL_SHIFT)) & ENET_PHY_SUP_DIG_IDCODE_LO_VAL_MASK) /*! @} */ /*! @name SUP_DIG_IDCODE_HI - High 16 Bits of IDCODE */ /*! @{ */ #define ENET_PHY_SUP_DIG_IDCODE_HI_VAL_MASK (0xFFFFU) #define ENET_PHY_SUP_DIG_IDCODE_HI_VAL_SHIFT (0U) /*! VAL - VAL */ #define ENET_PHY_SUP_DIG_IDCODE_HI_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_IDCODE_HI_VAL_SHIFT)) & ENET_PHY_SUP_DIG_IDCODE_HI_VAL_MASK) /*! @} */ /*! @name SUP_DIG_REFCLK_OVRD_IN - Override Values for Incoming REFCLK and RESET Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_EN_SHIFT (0U) /*! REF_CLK_EN - Override Value for ref_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_DIV2_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_DIV2_EN_SHIFT (1U) /*! REF_CLK_DIV2_EN - Override Value for ref_clk_div2_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_DIV2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_DIV2_EN_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_DIV2_EN_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_USE_PAD_MASK (0x4U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_USE_PAD_SHIFT (2U) /*! REF_USE_PAD - Override Value for ref_use_pad * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_USE_PAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_USE_PAD_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_USE_PAD_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_REPEAT_CLK_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_REPEAT_CLK_EN_SHIFT (3U) /*! REF_REPEAT_CLK_EN - Override Value for ref_repeat_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_REPEAT_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_REPEAT_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_REPEAT_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_RANGE_MASK (0x70U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_RANGE_SHIFT (4U) /*! REF_CLK_RANGE - Override Value for ref_range */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_RANGE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_RANGE_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLK_RANGE_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_VPH_NOMINAL_MASK (0x180U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_VPH_NOMINAL_SHIFT (7U) /*! VPH_NOMINAL - Override Value for vph_nominal */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_VPH_NOMINAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_VPH_NOMINAL_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_VPH_NOMINAL_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_BG_EN_MASK (0x400U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_BG_EN_SHIFT (10U) /*! BG_EN - Override Value for bg_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_BG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_BG_EN_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_BG_EN_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLKDET_EN_MASK (0x800U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLKDET_EN_SHIFT (11U) /*! REF_CLKDET_EN - Override Value for ref_clkdet_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLKDET_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLKDET_EN_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_REF_CLKDET_EN_MASK) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_OVRD_EN_MASK (0x1000U) #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_OVRD_EN_SHIFT (12U) /*! OVRD_EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_REFCLK_OVRD_IN_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN - Override Values for Incoming MPLLA_B_DIV_CLK Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_CLK_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_CLK_EN_SHIFT (0U) /*! MPLLA_DIV_CLK_EN - Override Value for mplla_div_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_MULTIPLIER_MASK (0xFEU) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_MULTIPLIER_SHIFT (1U) /*! MPLLA_DIV_MULTIPLIER - Override Value for mplla_div_multiplier */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLA_DIV_MULTIPLIER_MASK) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_CLK_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_CLK_EN_SHIFT (8U) /*! MPLLB_DIV_CLK_EN - Override Value for mpllb_div_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_MULTIPLIER_MASK (0xFE00U) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_MULTIPLIER_SHIFT (9U) /*! MPLLB_DIV_MULTIPLIER - Override Value for mpllb_div_multiplier */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_MPLLB_DIV_MULTIPLIER_MASK) /*! @} */ /*! @name SUP_DIG_SUP_OVRD_IN_0 - Override Values for Support Block ASIC Inputs 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_REQ_MASK (0x1U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_REQ_SHIFT (0U) /*! RTUNE_REQ - Override Value for rtune_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_REQ_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_REQ_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_OVRD_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_OVRD_EN_SHIFT (1U) /*! RTUNE_OVRD_EN - Enable override of rtune_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RTUNE_OVRD_EN_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_REQ_IN_MASK (0x4U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_REQ_IN_SHIFT (2U) /*! RES_REQ_IN - Override Value for res_req_in * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_REQ_IN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_REQ_IN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_REQ_IN_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_ACK_IN_MASK (0x8U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_ACK_IN_SHIFT (3U) /*! RES_ACK_IN - Override Value for res_ack_in * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_ACK_IN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_ACK_IN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_ACK_IN_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_OVRD_EN_MASK (0x10U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_OVRD_EN_SHIFT (4U) /*! RES_OVRD_EN - Enable override of res_req_in and res_ack_in * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_0_RES_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_SUP_OVRD_IN_1 - Override Values for Support Block ASIC Inputs 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_SHIFT (0U) /*! TXUP_TERM_OFFSET - Offset value for TXUP termination */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_OVRD_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_OVRD_EN_SHIFT (9U) /*! TXUP_TERM_OFFSET_OVRD_EN - Offset enable for TXUP termination * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_TXUP_TERM_OFFSET_OVRD_EN_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_MASK (0x7C00U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_SHIFT (10U) /*! RX_TERM_OFFSET - Offset value for RX termination */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_MASK (0x8000U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_SHIFT (15U) /*! RX_TERM_OFFSET_OVRD_EN - Offset enable for RX termination * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_SUP_OVRD_IN_2 - Override Values for Support Block ASIC Inputs 2 */ /*! @{ */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_SHIFT (0U) /*! TXDN_TERM_OFFSET - Offset value for TXDN termination */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_OVRD_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_OVRD_EN_SHIFT (9U) /*! TXDN_TERM_OFFSET_OVRD_EN - Offset enable for TXDN termination * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_IN_2_TXDN_TERM_OFFSET_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_SUP_OVRD_OUT - Override Values for Support Block ASIC Outputs */ /*! @{ */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RTUNE_ACK_MASK (0x1U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RTUNE_ACK_SHIFT (0U) /*! RTUNE_ACK - Override Value for rtune_ack output * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RTUNE_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RTUNE_ACK_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RTUNE_ACK_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_REQ_OUT_MASK (0x2U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_REQ_OUT_SHIFT (1U) /*! RES_REQ_OUT - Override Value for res_req_out output * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_REQ_OUT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_REQ_OUT_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_REQ_OUT_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_ACK_OUT_MASK (0x4U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_ACK_OUT_SHIFT (2U) /*! RES_ACK_OUT - Override Value for res_ack_out output * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_ACK_OUT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_ACK_OUT_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_RES_ACK_OUT_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLA_STATE_MASK (0x8U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLA_STATE_SHIFT (3U) /*! MPLLA_STATE - Override Value for mplla_state output * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLA_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLA_STATE_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLA_STATE_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLB_STATE_MASK (0x10U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLB_STATE_SHIFT (4U) /*! MPLLB_STATE - Override Value for mpllb_state output * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLB_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLB_STATE_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_MPLLB_STATE_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_OVRD_EN_MASK (0x20U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_OVRD_EN_SHIFT (5U) /*! OVRD_EN - Enable override values for all outputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_OVRD_EN_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_STATE_OVRD_MASK (0x40U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_STATE_OVRD_SHIFT (6U) /*! BG_LANE_STATE_OVRD - Override Value for bg_lane_state signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_STATE_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_STATE_OVRD_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_STATE_OVRD_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_OVRD_EN_MASK (0x80U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_OVRD_EN_SHIFT (7U) /*! BG_LANE_OVRD_EN - Enable override value for bg_lane_state signal * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_LANE_OVRD_EN_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_STATE_OVRD_MASK (0x100U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_STATE_OVRD_SHIFT (8U) /*! BG_SUP_STATE_OVRD - Override Value for bg_sup_state signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_STATE_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_STATE_OVRD_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_STATE_OVRD_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_OVRD_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_OVRD_EN_SHIFT (9U) /*! BG_SUP_OVRD_EN - Enable override value for bg_sup_state signal * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_OUT_BG_SUP_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_LVL_OVRD_IN - Override Values for Level Settings */ /*! @{ */ #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_MASK (0x1FU) #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_SHIFT (0U) /*! RX_VREF_CTRL - Override Value for rx_vref_ctrl */ #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_SHIFT)) & ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_MASK) #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_EN_MASK (0x20U) #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_EN_SHIFT (5U) /*! RX_VREF_CTRL_EN - Enable override value for rx_vref_ctrl * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_EN_SHIFT)) & ENET_PHY_SUP_DIG_LVL_OVRD_IN_RX_VREF_CTRL_EN_MASK) #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_MASK (0x1C0U) #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_SHIFT (6U) /*! TX_VBOOST_LVL - Override Value for tx_vboost_lvl */ #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_SHIFT)) & ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_MASK) #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_EN_SHIFT (9U) /*! TX_VBOOST_LVL_EN - Enable override value for tx_vboost_lvl * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_EN_SHIFT)) & ENET_PHY_SUP_DIG_LVL_OVRD_IN_TX_VBOOST_LVL_EN_MASK) /*! @} */ /*! @name SUP_DIG_DEBUG - Debug Controls */ /*! @{ */ #define ENET_PHY_SUP_DIG_DEBUG_DTB_SEL_MASK (0x7U) #define ENET_PHY_SUP_DIG_DEBUG_DTB_SEL_SHIFT (0U) /*! DTB_SEL - The lane DTB's are OR'd together with the support DTB signals selected with the below encodings. * 0b000..None * 0b001..MPLLA DTB output * 0b010..MPLLB DTB output * 0b011..RTUNE DTB output */ #define ENET_PHY_SUP_DIG_DEBUG_DTB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_DEBUG_DTB_SEL_SHIFT)) & ENET_PHY_SUP_DIG_DEBUG_DTB_SEL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN - Current Values for Incoming MPLLA_B_DIV_CLK Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_CLK_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_CLK_EN_SHIFT (0U) /*! MPLLA_DIV_CLK_EN - Value from mplla_div_clk_en */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_MULTIPLIER_MASK (0xFEU) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_MULTIPLIER_SHIFT (1U) /*! MPLLA_DIV_MULTIPLIER - Value from mplla_div_multiplier */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLA_DIV_MULTIPLIER_MASK) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_CLK_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_CLK_EN_SHIFT (8U) /*! MPLLB_DIV_CLK_EN - Value from mpllb_div_clk_en */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_MULTIPLIER_MASK (0xFE00U) #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_MULTIPLIER_SHIFT (9U) /*! MPLLB_DIV_MULTIPLIER - Value from mpllb_div_multiplier */ #define ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_MPLLB_DIV_MULTIPLIER_MASK) /*! @} */ /*! @name SUP_DIG_ASIC_IN - Current Values for Incoming SUP Control Signals from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_ASIC_IN_PHY_RESET_MASK (0x1U) #define ENET_PHY_SUP_DIG_ASIC_IN_PHY_RESET_SHIFT (0U) /*! PHY_RESET - Value from ASIC for phy_reset */ #define ENET_PHY_SUP_DIG_ASIC_IN_PHY_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_PHY_RESET_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_PHY_RESET_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_EN_SHIFT (1U) /*! REF_CLK_EN - Value from ASIC for ref_clk_en */ #define ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_DIV2_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_DIV2_EN_SHIFT (2U) /*! REF_CLK_DIV2_EN - Value from ASIC for ref_clk_div2_en */ #define ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_DIV2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_DIV2_EN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_REF_CLK_DIV2_EN_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_REPEAT_CLK_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_REPEAT_CLK_EN_SHIFT (3U) /*! REF_REPEAT_CLK_EN - Value from ASIC for ref_repeat_clk_en */ #define ENET_PHY_SUP_DIG_ASIC_IN_REF_REPEAT_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_REF_REPEAT_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_REF_REPEAT_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_USE_PAD_MASK (0x10U) #define ENET_PHY_SUP_DIG_ASIC_IN_REF_USE_PAD_SHIFT (4U) /*! REF_USE_PAD - Value from ASIC for ref_use_pad */ #define ENET_PHY_SUP_DIG_ASIC_IN_REF_USE_PAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_REF_USE_PAD_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_REF_USE_PAD_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_TEST_BURNIN_MASK (0x20U) #define ENET_PHY_SUP_DIG_ASIC_IN_TEST_BURNIN_SHIFT (5U) /*! TEST_BURNIN - Value from ASIC for test_burnin */ #define ENET_PHY_SUP_DIG_ASIC_IN_TEST_BURNIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_TEST_BURNIN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_TEST_BURNIN_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_TEST_POWERDOWN_MASK (0x40U) #define ENET_PHY_SUP_DIG_ASIC_IN_TEST_POWERDOWN_SHIFT (6U) /*! TEST_POWERDOWN - Value from ASIC for test_powerdown */ #define ENET_PHY_SUP_DIG_ASIC_IN_TEST_POWERDOWN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_TEST_POWERDOWN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_TEST_POWERDOWN_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_REQ_MASK (0x80U) #define ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_REQ_SHIFT (7U) /*! RTUNE_REQ - Value from ASIC for rtune_req */ #define ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_REQ_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_REQ_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_ACK_MASK (0x100U) #define ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_ACK_SHIFT (8U) /*! RTUNE_ACK - Value to ASIC for rtune_ack_i */ #define ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_ACK_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_RTUNE_ACK_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_IN_MASK (0x200U) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_IN_SHIFT (9U) /*! RES_REQ_IN - Value from ASIC for res_req_in */ #define ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_IN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_IN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_IN_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_OUT_MASK (0x400U) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_OUT_SHIFT (10U) /*! RES_REQ_OUT - Value to ASIC for res_ack_out_i */ #define ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_OUT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_OUT_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_RES_REQ_OUT_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_IN_MASK (0x800U) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_IN_SHIFT (11U) /*! RES_ACK_IN - Value from ASIC for res_req_in */ #define ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_IN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_IN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_IN_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_OUT_MASK (0x1000U) #define ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_OUT_SHIFT (12U) /*! RES_ACK_OUT - Value to ASIC for res_ack_out_i */ #define ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_OUT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_OUT_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_RES_ACK_OUT_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_MPLLA_STATE_MASK (0x2000U) #define ENET_PHY_SUP_DIG_ASIC_IN_MPLLA_STATE_SHIFT (13U) /*! MPLLA_STATE - Value to ASIC for mplla_state_i */ #define ENET_PHY_SUP_DIG_ASIC_IN_MPLLA_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_MPLLA_STATE_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_MPLLA_STATE_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_MPLLB_STATE_MASK (0x4000U) #define ENET_PHY_SUP_DIG_ASIC_IN_MPLLB_STATE_SHIFT (14U) /*! MPLLB_STATE - Value to ASIC for mpllb_state_i */ #define ENET_PHY_SUP_DIG_ASIC_IN_MPLLB_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_MPLLB_STATE_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_MPLLB_STATE_MASK) #define ENET_PHY_SUP_DIG_ASIC_IN_BG_EN_MASK (0x8000U) #define ENET_PHY_SUP_DIG_ASIC_IN_BG_EN_SHIFT (15U) /*! BG_EN - Value from ASIC for bg_en */ #define ENET_PHY_SUP_DIG_ASIC_IN_BG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ASIC_IN_BG_EN_SHIFT)) & ENET_PHY_SUP_DIG_ASIC_IN_BG_EN_MASK) /*! @} */ /*! @name SUP_DIG_LVL_ASIC_IN - Current Values for Incoming Level Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_VREF_CTRL_MASK (0x1FU) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_VREF_CTRL_SHIFT (0U) /*! RX_VREF_CTRL - Value from ASIC for rx_vref_ctrl */ #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_VREF_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_VREF_CTRL_SHIFT)) & ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_VREF_CTRL_MASK) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_TX_VBOOST_LVL_MASK (0xE0U) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_TX_VBOOST_LVL_SHIFT (5U) /*! TX_VBOOST_LVL - Value from ASIC for tx_vboost_lvl */ #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_TX_VBOOST_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_ASIC_IN_TX_VBOOST_LVL_SHIFT)) & ENET_PHY_SUP_DIG_LVL_ASIC_IN_TX_VBOOST_LVL_MASK) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_RESULT_MASK (0x100U) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_RESULT_SHIFT (8U) /*! REF_CLKDET_RESULT - Value from ASIC for ref_clkdet_result */ #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_RESULT_SHIFT)) & ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_RESULT_MASK) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_EN_SHIFT (9U) /*! REF_CLKDET_EN - Value from ASIC for ref_clkdet_en */ #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_EN_SHIFT)) & ENET_PHY_SUP_DIG_LVL_ASIC_IN_REF_CLKDET_EN_MASK) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_TERM_OFFSET_MASK (0x7C00U) #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_TERM_OFFSET_SHIFT (10U) /*! RX_TERM_OFFSET - Value from ASIC for */ #define ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_TERM_OFFSET_SHIFT)) & ENET_PHY_SUP_DIG_LVL_ASIC_IN_RX_TERM_OFFSET_MASK) /*! @} */ /*! @name SUP_DIG_SUP_OVRD_MISC - Override Values for Incoming SUP MISC BUS from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_VAL_MASK (0xFFU) #define ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_VAL_SHIFT (0U) /*! SUP_MISC_OVRD_VAL - Override Value for sup_misc[7:0] */ #define ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_VAL_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_VAL_MASK) #define ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_EN_SHIFT (8U) /*! SUP_MISC_OVRD_EN - Override Enable for sup_misc[7:0] * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_SUP_OVRD_MISC_SUP_MISC_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_CLK_RST_BG_PWRUP_TIME_0 - BG Power UP Time 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_BG_SUP_EN_TIME_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_BG_SUP_EN_TIME_SHIFT (0U) /*! BG_SUP_EN_TIME - Power up time (in ref_range cycles) for bandgap in SUP (spec >= 5 us) */ #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_BG_SUP_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_BG_SUP_EN_TIME_SHIFT)) & ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_BG_SUP_EN_TIME_MASK) #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_FAST_BG_WAIT_MASK (0x200U) #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_FAST_BG_WAIT_SHIFT (9U) /*! FAST_BG_WAIT - Enable fast BG times (simulation only) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_FAST_BG_WAIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_FAST_BG_WAIT_SHIFT)) & ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0_FAST_BG_WAIT_MASK) /*! @} */ /*! @name SUP_DIG_CLK_RST_BG_PWRUP_TIME_1 - BG Power UP Time 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1_BG_LANE_EN_TIME_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1_BG_LANE_EN_TIME_SHIFT (0U) /*! BG_LANE_EN_TIME - Power up time (in ref_range cycles) for bandgap in LANE (spec >= 5 us) */ #define ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1_BG_LANE_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1_BG_LANE_EN_TIME_SHIFT)) & ENET_PHY_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1_BG_LANE_EN_TIME_MASK) /*! @} */ /*! @name SUP_ANA_RTUNE_CTRL - RTUNE_CTRL */ /*! @{ */ #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_chop_MASK (0x8U) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_chop_SHIFT (3U) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_chop(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_chop_SHIFT)) & ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_chop_MASK) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_mode_MASK (0x30U) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_mode_SHIFT (4U) /*! rt_dac_mode - Margin DAC Mode Control */ #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_mode(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_mode_SHIFT)) & ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_dac_mode_MASK) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_ibias_1p5x_MASK (0x40U) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_ibias_1p5x_SHIFT (6U) /*! rt_ibias_1p5x - Increase Bias Current */ #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_ibias_1p5x(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_ibias_1p5x_SHIFT)) & ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_ibias_1p5x_MASK) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_en_frcon_MASK (0x80U) #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_en_frcon_SHIFT (7U) /*! rt_en_frcon - Local Rtune Block Enable Control */ #define ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_en_frcon(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_en_frcon_SHIFT)) & ENET_PHY_SUP_ANA_RTUNE_CTRL_rt_en_frcon_MASK) /*! @} */ /*! @name SUP_ANA_SWITCH_PWR_MEAS - SWITCH_PWR_MEAS */ /*! @{ */ #define ENET_PHY_SUP_ANA_SWITCH_PWR_MEAS_temp_meas_MASK (0x80U) #define ENET_PHY_SUP_ANA_SWITCH_PWR_MEAS_temp_meas_SHIFT (7U) /*! temp_meas - Measure bandgap's PNP diode voltage (temperature) * 0b0..Doesn't measure * 0b1..Measures */ #define ENET_PHY_SUP_ANA_SWITCH_PWR_MEAS_temp_meas(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_SWITCH_PWR_MEAS_temp_meas_SHIFT)) & ENET_PHY_SUP_ANA_SWITCH_PWR_MEAS_temp_meas_MASK) /*! @} */ /*! @name SUP_ANA_SWITCH_MISC_MEAS - SWITCH_MISC_MEAS */ /*! @{ */ #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_hyst_ref_MASK (0x3U) #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_hyst_ref_SHIFT (0U) /*! hyst_ref - Sets Prescaler Input Buffer Hysteresis * 0b00..No hysteresis * 0b01..18 mVpp hysteresis * 0b10..35 mVpp hysteresis * 0b11..50 mVpp hysteresis */ #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_hyst_ref(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_hyst_ref_SHIFT)) & ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_hyst_ref_MASK) #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p5_MASK (0x1CU) #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p5_SHIFT (2U) /*! vref_sel_slowreg_vph1p5 - Sets value of slowreg_vref for VPH=1.5 or 1.8 V * 0b000..300 mV * 0b001..325 mV * 0b010..350 mV * 0b011..375 mV * 0b100..400 mV * 0b101..425 mV * 0b110..450 mV * 0b111..475 mV */ #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p5_SHIFT)) & ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p5_MASK) #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p2_MASK (0xE0U) #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p2_SHIFT (5U) /*! vref_sel_slowreg_vph1p2 - Sets value of slowreg_vref for VPH=1.2 V * 0b000..300 mV * 0b001..325 mV * 0b010..350 mV * 0b011..375 mV * 0b100..400 mV * 0b101..425 mV * 0b110..450 mV * 0b111..475 mV */ #define ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p2_SHIFT)) & ENET_PHY_SUP_ANA_SWITCH_MISC_MEAS_vref_sel_slowreg_vph1p2_MASK) /*! @} */ /*! @name SUP_ANA_BG - BG */ /*! @{ */ #define ENET_PHY_SUP_ANA_BG_bypass_bg_MASK (0x1U) #define ENET_PHY_SUP_ANA_BG_bypass_bg_SHIFT (0U) /*! bypass_bg - Bypass Bandgap with VP * 0b0..No bypass * 0b1..Bypass */ #define ENET_PHY_SUP_ANA_BG_bypass_bg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_BG_bypass_bg_SHIFT)) & ENET_PHY_SUP_ANA_BG_bypass_bg_MASK) #define ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p5_MASK (0x6U) #define ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p5_SHIFT (1U) /*! vref_sel_fastreg_vph1p5 - Sets value of fastreg_vref for VPH=1.5 or 1.8 V * 0b00..525 mV * 0b01..550 mV * 0b10..575 mV * 0b11..600 mV */ #define ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p5_SHIFT)) & ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p5_MASK) #define ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p2_MASK (0x18U) #define ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p2_SHIFT (3U) /*! vref_sel_fastreg_vph1p2 - Sets value of fastreg_vref for VPH=1.2 V * 0b00..525 mV * 0b01..550 mV * 0b10..575 mV * 0b11..600 mV */ #define ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p2_SHIFT)) & ENET_PHY_SUP_ANA_BG_vref_sel_fastreg_vph1p2_MASK) #define ENET_PHY_SUP_ANA_BG_chop_en_int_MASK (0x20U) #define ENET_PHY_SUP_ANA_BG_chop_en_int_SHIFT (5U) /*! chop_en_int - Enable chopper clock for bandgap * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_BG_chop_en_int(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_BG_chop_en_int_SHIFT)) & ENET_PHY_SUP_ANA_BG_chop_en_int_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_DEBUG - Resistor Tuning Debug Controls */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_FLIP_COMP_MASK (0x1U) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_FLIP_COMP_SHIFT (0U) /*! FLIP_COMP - Invert Analog Comparator Output * 0b0..No invert * 0b1..Invert */ #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_FLIP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_DEBUG_FLIP_COMP_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_DEBUG_FLIP_COMP_MASK) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_MAN_TUNE_MASK (0x2U) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_MAN_TUNE_SHIFT (1U) /*! MAN_TUNE - Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune * while a tune is currently running can cause unpredictable results. For use only when you know * what the part is doing (w.r.t. resistor tuning) */ #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_MAN_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_DEBUG_MAN_TUNE_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_DEBUG_MAN_TUNE_MASK) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_SET_VAL_MASK (0x4U) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_SET_VAL_SHIFT (2U) /*! SET_VAL - Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field * 0b0..Not set * 0b1..Set */ #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_SET_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_DEBUG_SET_VAL_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_DEBUG_SET_VAL_MASK) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_TYPE_MASK (0x18U) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_TYPE_SHIFT (3U) /*! TYPE - Type of manual tuning or register read/write to execute 0 - ADC, or read/write rt_value * 0b01..RX tune, or read/write rx_cal_val (only 6 bits) * 0b10..TX-DN tune, or read/write txdn_cal_val (10 bits) * 0b11..TX-UP tune, or read/write txup_cal_val (10 bits) or Resref detect (no affect when triggering SET_VAL field) */ #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_TYPE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_DEBUG_TYPE_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_DEBUG_TYPE_MASK) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_VALUE_MASK (0x7FE0U) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_VALUE_SHIFT (5U) /*! VALUE - Value to use when triggering SET_VAL field only the 6 LSB's are used when setting RX or TX cal values */ #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_DEBUG_VALUE_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_DEBUG_VALUE_MASK) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_TXUP_GO_MASK (0x8000U) #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_TXUP_GO_SHIFT (15U) /*! TXUP_GO - Enable TX-UP tune to continue in manual tune mode when TYPE is TX-UP tune * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_RTUNE_DEBUG_TXUP_GO(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_DEBUG_TXUP_GO_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_DEBUG_TXUP_GO_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_CONFIG - Configure Rtune Operation */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_CONFIG_SKIP_RX_CAL_MASK (0x1U) #define ENET_PHY_SUP_DIG_RTUNE_CONFIG_SKIP_RX_CAL_SHIFT (0U) /*! SKIP_RX_CAL - Skip Calibration of RX Resistor * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_SUP_DIG_RTUNE_CONFIG_SKIP_RX_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_CONFIG_SKIP_RX_CAL_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_CONFIG_SKIP_RX_CAL_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_STAT - Resistor Tuning Register Status */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_STAT_STAT_MASK (0x3FFU) #define ENET_PHY_SUP_DIG_RTUNE_STAT_STAT_SHIFT (0U) /*! STAT - Current value of the register specified by the DEBUG.TYPE field */ #define ENET_PHY_SUP_DIG_RTUNE_STAT_STAT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_STAT_STAT_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_STAT_STAT_MASK) #define ENET_PHY_SUP_DIG_RTUNE_STAT_DTB_RTUNE_MASK (0xC00U) #define ENET_PHY_SUP_DIG_RTUNE_STAT_DTB_RTUNE_SHIFT (10U) /*! DTB_RTUNE - DTB Sampling for Rtune */ #define ENET_PHY_SUP_DIG_RTUNE_STAT_DTB_RTUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_STAT_DTB_RTUNE_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_STAT_DTB_RTUNE_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_RX_SET_VAL - Set Value of RX Resistor */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_RX_SET_VAL_RX_SET_VAL_MASK (0x3FU) #define ENET_PHY_SUP_DIG_RTUNE_RX_SET_VAL_RX_SET_VAL_SHIFT (0U) /*! RX_SET_VAL - Set Value of RX Resistor */ #define ENET_PHY_SUP_DIG_RTUNE_RX_SET_VAL_RX_SET_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_RX_SET_VAL_RX_SET_VAL_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_RX_SET_VAL_RX_SET_VAL_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_TXDN_SET_VAL - Set Value of TX-DN Resistor */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_TXDN_SET_VAL_TXDN_SET_VAL_MASK (0x3FFU) #define ENET_PHY_SUP_DIG_RTUNE_TXDN_SET_VAL_TXDN_SET_VAL_SHIFT (0U) /*! TXDN_SET_VAL - Set Value of TX-DN Resistor */ #define ENET_PHY_SUP_DIG_RTUNE_TXDN_SET_VAL_TXDN_SET_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_TXDN_SET_VAL_TXDN_SET_VAL_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_TXDN_SET_VAL_TXDN_SET_VAL_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_TXUP_SET_VAL - Set Value of TX-UP Resistor */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_TXUP_SET_VAL_TXUP_SET_VAL_MASK (0x3FFU) #define ENET_PHY_SUP_DIG_RTUNE_TXUP_SET_VAL_TXUP_SET_VAL_SHIFT (0U) /*! TXUP_SET_VAL - Set Value of TX-UP Resistor */ #define ENET_PHY_SUP_DIG_RTUNE_TXUP_SET_VAL_TXUP_SET_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_TXUP_SET_VAL_TXUP_SET_VAL_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_TXUP_SET_VAL_TXUP_SET_VAL_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_RX_STAT - RX Resistor Tuning Register Status */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_RX_STAT_RX_STAT_MASK (0x3FU) #define ENET_PHY_SUP_DIG_RTUNE_RX_STAT_RX_STAT_SHIFT (0U) /*! RX_STAT - Current value of the RX resistor tuning register */ #define ENET_PHY_SUP_DIG_RTUNE_RX_STAT_RX_STAT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_RX_STAT_RX_STAT_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_RX_STAT_RX_STAT_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_TXDN_STAT - TX-DN Resistor Tuning Register Status */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_TXDN_STAT_TXDN_STAT_MASK (0x3FFU) #define ENET_PHY_SUP_DIG_RTUNE_TXDN_STAT_TXDN_STAT_SHIFT (0U) /*! TXDN_STAT - Current value of the TX-DN resistor tuning register */ #define ENET_PHY_SUP_DIG_RTUNE_TXDN_STAT_TXDN_STAT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_TXDN_STAT_TXDN_STAT_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_TXDN_STAT_TXDN_STAT_MASK) /*! @} */ /*! @name SUP_DIG_RTUNE_TXUP_STAT - TX-UP Resistor Tuning Register Status */ /*! @{ */ #define ENET_PHY_SUP_DIG_RTUNE_TXUP_STAT_TXUP_STAT_MASK (0x3FFU) #define ENET_PHY_SUP_DIG_RTUNE_TXUP_STAT_TXUP_STAT_SHIFT (0U) /*! TXUP_STAT - Current value of the TX-UP resistor tuning register */ #define ENET_PHY_SUP_DIG_RTUNE_TXUP_STAT_TXUP_STAT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_RTUNE_TXUP_STAT_TXUP_STAT_SHIFT)) & ENET_PHY_SUP_DIG_RTUNE_TXUP_STAT_TXUP_STAT_MASK) /*! @} */ /*! @name SUP_DIG_ANA_RTUNE_OVRD_OUT - Override Value for RTUNE Signals Going to ANA */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_COMP_RST_MASK (0x1U) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_COMP_RST_SHIFT (0U) /*! RTUNE_COMP_RST - Overrides the rt_ana_comp_rst signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_COMP_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_COMP_RST_SHIFT)) & ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_COMP_RST_MASK) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_MODE_MASK (0x6U) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_MODE_SHIFT (1U) /*! RTUNE_MODE - Overrides the rt_ana_mode[1:0] signal */ #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_MODE_SHIFT)) & ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_MODE_MASK) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_EN_SHIFT (3U) /*! RTUNE_EN - Overrides the rt_ana_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_VALUE_MASK (0x3FF0U) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_VALUE_SHIFT (4U) /*! RTUNE_VALUE - Overrides the rt_ana_value[9:0] signal */ #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_VALUE_SHIFT)) & ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_VALUE_MASK) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_OVRD_EN_MASK (0x4000U) #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_OVRD_EN_SHIFT (14U) /*! RTUNE_OVRD_EN - Override bit for rtune (rt_ana_* and term) outputs * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_RTUNE_OVRD_OUT_RTUNE_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_ANA_RX_TERM_OVRD_OUT - Override Value for RX Termination Signals Going to ANA */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_RX_TERM_OVRD_OUT_RX_TERM_VAL_MASK (0x3FU) #define ENET_PHY_SUP_DIG_ANA_RX_TERM_OVRD_OUT_RX_TERM_VAL_SHIFT (0U) /*! RX_TERM_VAL - Overrides the rx_ana_term_val[5:0] signal */ #define ENET_PHY_SUP_DIG_ANA_RX_TERM_OVRD_OUT_RX_TERM_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_RX_TERM_OVRD_OUT_RX_TERM_VAL_SHIFT)) & ENET_PHY_SUP_DIG_ANA_RX_TERM_OVRD_OUT_RX_TERM_VAL_MASK) /*! @} */ /*! @name SUP_DIG_ANA_STAT - SUP Input Status Register for SUP ANA Outputs */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_STAT_RT_ANA_COMP_RESULT_MASK (0x1U) #define ENET_PHY_SUP_DIG_ANA_STAT_RT_ANA_COMP_RESULT_SHIFT (0U) /*! RT_ANA_COMP_RESULT - Value from ANA for rt_ana_comp_result */ #define ENET_PHY_SUP_DIG_ANA_STAT_RT_ANA_COMP_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_STAT_RT_ANA_COMP_RESULT_SHIFT)) & ENET_PHY_SUP_DIG_ANA_STAT_RT_ANA_COMP_RESULT_MASK) #define ENET_PHY_SUP_DIG_ANA_STAT_REF_ANA_CLKDET_RESULT_MASK (0x2U) #define ENET_PHY_SUP_DIG_ANA_STAT_REF_ANA_CLKDET_RESULT_SHIFT (1U) /*! REF_ANA_CLKDET_RESULT - Value from ANA for ref_ana_clkdet_result */ #define ENET_PHY_SUP_DIG_ANA_STAT_REF_ANA_CLKDET_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_STAT_REF_ANA_CLKDET_RESULT_SHIFT)) & ENET_PHY_SUP_DIG_ANA_STAT_REF_ANA_CLKDET_RESULT_MASK) /*! @} */ /*! @name SUP_DIG_ANA_BG_OVRD_OUT - Override Values for Bandgap Signals Going to ANA */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_FAST_START_MASK (0x1U) #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_FAST_START_SHIFT (0U) /*! BG_FAST_START - Overrides the bg_ana_vref_fast_start signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_FAST_START(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_FAST_START_SHIFT)) & ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_FAST_START_MASK) #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_EN_SHIFT (1U) /*! BG_EN - Overrides the bg_ana_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_OVRD_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_OVRD_EN_SHIFT (2U) /*! BG_OVRD_EN - Override bit for bandgap outputs * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_BG_OVRD_OUT_BG_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_FREQ_CNT_PEAK_ASIC_IN - Current Values for Incoming Level Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLB_SSC_FREQ_CNT_PEAK_MASK (0xFFU) #define ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLB_SSC_FREQ_CNT_PEAK_SHIFT (0U) /*! MPLLB_SSC_FREQ_CNT_PEAK - Value from ASIC for MPLLB_SSC_FREQ_CNT_PEAK */ #define ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLB_SSC_FREQ_CNT_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLB_SSC_FREQ_CNT_PEAK_SHIFT)) & ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLB_SSC_FREQ_CNT_PEAK_MASK) #define ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLA_SSC_FREQ_CNT_PEAK_MASK (0xFF00U) #define ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLA_SSC_FREQ_CNT_PEAK_SHIFT (8U) /*! MPLLA_SSC_FREQ_CNT_PEAK - Value from ASIC for MPLLA_SSC_FREQ_CNT_PEAK */ #define ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLA_SSC_FREQ_CNT_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLA_SSC_FREQ_CNT_PEAK_SHIFT)) & ENET_PHY_SUP_DIG_FREQ_CNT_PEAK_ASIC_IN_MPLLA_SSC_FREQ_CNT_PEAK_MASK) /*! @} */ /*! @name SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN - Current Values for Incoming Level Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN_TXUP_TERM_OFFSET_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN_TXUP_TERM_OFFSET_SHIFT (0U) /*! TXUP_TERM_OFFSET - Value from ASIC for txup_term_offset */ #define ENET_PHY_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN_TXUP_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN_TXUP_TERM_OFFSET_SHIFT)) & ENET_PHY_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN_TXUP_TERM_OFFSET_MASK) /*! @} */ /*! @name SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN - Current Values for Incoming Level Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN_TXDN_TERM_OFFSET_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN_TXDN_TERM_OFFSET_SHIFT (0U) /*! TXDN_TERM_OFFSET - Value from ASIC for txup_term_offset */ #define ENET_PHY_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN_TXDN_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN_TXDN_TERM_OFFSET_SHIFT)) & ENET_PHY_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN_TXDN_TERM_OFFSET_MASK) /*! @} */ /*! @name SUP_DIG_MISC_ASIC_IN - Current Values for Incoming Level Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_SUP_MISC_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_SUP_MISC_SHIFT (0U) /*! SUP_MISC - Value from ASIC for sup_misc */ #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_SUP_MISC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MISC_ASIC_IN_SUP_MISC_SHIFT)) & ENET_PHY_SUP_DIG_MISC_ASIC_IN_SUP_MISC_MASK) #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_STOP_CLK_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_STOP_CLK_EN_SHIFT (8U) /*! TEST_STOP_CLK_EN - Value from ASIC for test_stop_clk_en */ #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_STOP_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_STOP_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_STOP_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_FLYOVER_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_FLYOVER_EN_SHIFT (9U) /*! TEST_FLYOVER_EN - Value from ASIC for test_flyover_en */ #define ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_FLYOVER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_FLYOVER_EN_SHIFT)) & ENET_PHY_SUP_DIG_MISC_ASIC_IN_TEST_FLYOVER_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_CMN_CTL - Common Control */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_PHY_FUNC_RST_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_PHY_FUNC_RST_SHIFT (0U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_PHY_FUNC_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_CMN_CTL_PHY_FUNC_RST_SHIFT)) & ENET_PHY_RAWCMN_DIG_CMN_CTL_PHY_FUNC_RST_MASK) /*! @} */ /*! @name RAWCMN_DIG_LANE_FSM_OP_XTND - Lane FSM OP XTND Control */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_LANE_FSM_OP_XTND_VAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_LANE_FSM_OP_XTND_VAL_SHIFT (0U) /*! VAL - Required when accessing the analog CREGs in firmware to prevent timing violations across ANA-DIG interface */ #define ENET_PHY_RAWCMN_DIG_LANE_FSM_OP_XTND_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_LANE_FSM_OP_XTND_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_LANE_FSM_OP_XTND_VAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0 - Override Values for Incoming TX Term Offset */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_VAL_MASK (0x1FFU) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_VAL_SHIFT (0U) /*! TXUP_TERM_OFFSET_OVRD_VAL - Override Value for txup_term_offset[8:0] */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_EN_MASK (0x200U) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_EN_SHIFT (9U) /*! TXUP_TERM_OFFSET_OVRD_EN - Override Enable for txup_term_offset[8:0] * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_0_TXUP_TERM_OFFSET_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1 - Override Values for Incoming TX/RX Term Offset */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_VAL_MASK (0x1FFU) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_VAL_SHIFT (0U) /*! TXDN_TERM_OFFSET_OVRD_VAL - Override Value for txdn_term_offset[8:0] */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_EN_MASK (0x200U) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_EN_SHIFT (9U) /*! TXDN_TERM_OFFSET_OVRD_EN - Override Enable for txdn_term_offset[8:0] * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_TXDN_TERM_OFFSET_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_VAL_MASK (0x7C00U) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_VAL_SHIFT (10U) /*! RX_TERM_OFFSET_OVRD_VAL - Override Value for rx_term_offset[4:0] */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_MASK (0x8000U) #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_SHIFT (15U) /*! RX_TERM_OFFSET_OVRD_EN - Override Enable for rx_term_offset[4:0] * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_TERM_OFFSET_OVRD_IN_1_RX_TERM_OFFSET_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_CMN_CTL_1 - Common Control 1 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_VAL_SHIFT (0U) /*! MPLLA_INIT_CAL_DISABLE_OVRD_VAL - Override Value for mplla_init_cal_disable * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_EN_SHIFT (1U) /*! MPLLA_INIT_CAL_DISABLE_OVRD_EN - Override Enable for mplla_init_cal_disable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_VAL_SHIFT (2U) /*! MPLLB_INIT_CAL_DISABLE_OVRD_VAL - Override Value for mpllb_init_cal_disable * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_EN_SHIFT (3U) /*! MPLLB_INIT_CAL_DISABLE_OVRD_EN - Override Enable for mpllb_init_cal_disable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_CMN_CTL_1_MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_VAL_MASK (0x10U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_VAL_SHIFT (4U) /*! RTUNE_REQ_OVRD_VAL - Override Value for rtune_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_EN_MASK (0x20U) #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_EN_SHIFT (5U) /*! RTUNE_REQ_OVRD_EN - Override Enable for rtune_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_CMN_CTL_1_RTUNE_REQ_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLL_OFF_TIME - Wait Time for Turning MPLL Off */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLL_OFF_TIME_MPLLA_OFF_TIME_MASK (0x3FU) #define ENET_PHY_RAWCMN_DIG_MPLL_OFF_TIME_MPLLA_OFF_TIME_SHIFT (0U) /*! MPLLA_OFF_TIME - Wait counter for turning off MPLL */ #define ENET_PHY_RAWCMN_DIG_MPLL_OFF_TIME_MPLLA_OFF_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_OFF_TIME_MPLLA_OFF_TIME_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_OFF_TIME_MPLLA_OFF_TIME_MASK) /*! @} */ /*! @name RAWCMN_DIG_ATE_ALU_CTRL - ATE ALU Module Control */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_CTRL_ATE_ALU_OPCODE_MASK (0xFU) #define ENET_PHY_RAWCMN_DIG_ATE_ALU_CTRL_ATE_ALU_OPCODE_SHIFT (0U) /*! ATE_ALU_OPCODE - OPCode for ATE ALU Module * 0b0000..ZERO * 0b0001..ADD_RD_DATA * 0b0010..ADD_DATA * 0b0011..SHL1 * 0b0100..SHR1 * 0b0101..ASHR1 * 0b0110..INV * 0b0111..NEG * 0b1000..ABS * 0b1110..READ * 0b1111..WRITE */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_CTRL_ATE_ALU_OPCODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_ATE_ALU_CTRL_ATE_ALU_OPCODE_SHIFT)) & ENET_PHY_RAWCMN_DIG_ATE_ALU_CTRL_ATE_ALU_OPCODE_MASK) /*! @} */ /*! @name RAWCMN_DIG_ATE_ALU_ADDR - Address for Read and Write Command for ATE ALU Module */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_ADDR_ADDR_MASK (0xFFFFU) #define ENET_PHY_RAWCMN_DIG_ATE_ALU_ADDR_ADDR_SHIFT (0U) /*! ADDR - Address for read and write command for ATE ALU module */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_ADDR_ADDR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_ATE_ALU_ADDR_ADDR_SHIFT)) & ENET_PHY_RAWCMN_DIG_ATE_ALU_ADDR_ADDR_MASK) /*! @} */ /*! @name RAWCMN_DIG_ATE_ALU_DATA - Data for Write Command for ATE ALU Module */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_DATA_DATA_MASK (0xFFFFU) #define ENET_PHY_RAWCMN_DIG_ATE_ALU_DATA_DATA_SHIFT (0U) /*! DATA - Data for read and write command for ATE ALU module */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_DATA_DATA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_ATE_ALU_DATA_DATA_SHIFT)) & ENET_PHY_RAWCMN_DIG_ATE_ALU_DATA_DATA_MASK) /*! @} */ /*! @name RAWCMN_DIG_ATE_ALU_FLAGS - Flags from ATE ALU Module */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_FLAGS_ATE_ALU_ACCUM_SIGN_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_ATE_ALU_FLAGS_ATE_ALU_ACCUM_SIGN_SHIFT (0U) /*! ATE_ALU_ACCUM_SIGN - Indicate the sign of the accumulator in ATE ALU */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_FLAGS_ATE_ALU_ACCUM_SIGN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_ATE_ALU_FLAGS_ATE_ALU_ACCUM_SIGN_SHIFT)) & ENET_PHY_RAWCMN_DIG_ATE_ALU_FLAGS_ATE_ALU_ACCUM_SIGN_MASK) /*! @} */ /*! @name RAWCMN_DIG_ATE_ALU_ACCUM - Stores the ATE ALU Accumulator Result */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_ACCUM_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWCMN_DIG_ATE_ALU_ACCUM_VAL_SHIFT (0U) /*! VAL - Stores the ATE ALU accumulator result */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_ACCUM_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_ATE_ALU_ACCUM_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_ATE_ALU_ACCUM_VAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLL_IN - Current Values for Incoming MPLL Controls from PCS (Pre-Override Input Monitor) */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLA_INIT_CAL_DISABLE_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLA_INIT_CAL_DISABLE_SHIFT (0U) /*! MPLLA_INIT_CAL_DISABLE - Value from PCS for mplla_init_cal_disable */ #define ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLA_INIT_CAL_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLA_INIT_CAL_DISABLE_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLA_INIT_CAL_DISABLE_MASK) #define ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLB_INIT_CAL_DISABLE_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLB_INIT_CAL_DISABLE_SHIFT (1U) /*! MPLLB_INIT_CAL_DISABLE - Value from PCS for mpllb_init_cal_disable */ #define ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLB_INIT_CAL_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLB_INIT_CAL_DISABLE_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_IN_MPLLB_INIT_CAL_DISABLE_MASK) /*! @} */ /*! @name RAWCMN_DIG_FW_PWRUP_DONE - Firmware Power-up Done Status */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_FW_PWRUP_DONE_DONE_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_FW_PWRUP_DONE_DONE_SHIFT (0U) /*! DONE - Firmware power-up status for phy_reset and pg_reset */ #define ENET_PHY_RAWCMN_DIG_FW_PWRUP_DONE_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_FW_PWRUP_DONE_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_FW_PWRUP_DONE_DONE_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLL_CLK_ASYNC_EN - MPLL Output Clocks Asynchronous Control */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLA_CLK_EN_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLA_CLK_EN_SHIFT (0U) /*! MPLLA_CLK_EN - MPLLA Output Clocks Asynchronous Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLA_CLK_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLA_CLK_EN_MASK) #define ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLB_CLK_EN_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLB_CLK_EN_SHIFT (1U) /*! MPLLB_CLK_EN - MPLLB Output Clocks Asynchronous Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLB_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLB_CLK_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_CLK_ASYNC_EN_MPLLB_CLK_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_ATE_ALU_SPARE_0 - Spare Register 1 for ATE ALU Operations */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_0_DATA_MASK (0xFFFFU) #define ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_0_DATA_SHIFT (0U) /*! DATA - Spare for ATE ALU operations */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_0_DATA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_0_DATA_SHIFT)) & ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_0_DATA_MASK) /*! @} */ /*! @name RAWCMN_DIG_ATE_ALU_SPARE_1 - Spare Register 2 for ATE ALU Operations */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_1_DATA_MASK (0xFFFFU) #define ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_1_DATA_SHIFT (0U) /*! DATA - Spare for ATE ALU operations */ #define ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_1_DATA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_1_DATA_SHIFT)) & ENET_PHY_RAWCMN_DIG_ATE_ALU_SPARE_1_DATA_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLL_STATE_OVRD_IN - Override for MPLLA/B State Outputs */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_VAL_SHIFT (0U) /*! MPLLA_STATE_OVRD_VAL - Override Value for mplla_state * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_EN_SHIFT (1U) /*! MPLLA_STATE_OVRD_EN - Override Enable for mplla_state * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLA_STATE_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_VAL_SHIFT (2U) /*! MPLLB_STATE_OVRD_VAL - Override Value for mpllb_state * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_EN_SHIFT (3U) /*! MPLLB_STATE_OVRD_EN - Override Enable for mpllb_state * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLL_STATE_OVRD_IN_MPLLB_STATE_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_SRAM_PGATE_BL_EN - Enable SRAM Bootloader on Power-Gated Exit */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN_SRAM_PGATE_BL_EN_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN_SRAM_PGATE_BL_EN_SHIFT (0U) /*! SRAM_PGATE_BL_EN - Enable SRAM bootloader on power-gated exit * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN_SRAM_PGATE_BL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN_SRAM_PGATE_BL_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN_SRAM_PGATE_BL_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD - Override Incoming MPLLA/B_RECAL_BANK_SEL Input */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_VAL_MASK (0x3U) #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_VAL_SHIFT (0U) /*! MPLLA_CAL_BANK_SEL_OVRD_VAL - Override Value for incoming input mplla_recal_bank_sel */ #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_EN_MASK (0x4U) #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_EN_SHIFT (2U) /*! MPLLA_CAL_BANK_SEL_OVRD_EN - Enable Override for mplla_recal_bank_sel * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLA_CAL_BANK_SEL_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_VAL_MASK (0x18U) #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_VAL_SHIFT (3U) /*! MPLLB_CAL_BANK_SEL_OVRD_VAL - Override Value for incoming input mpllb_recal_bank_sel */ #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_EN_MASK (0x20U) #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_EN_SHIFT (5U) /*! MPLLB_CAL_BANK_SEL_OVRD_EN - Enable Override for mplla_cal_bank_sel * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLL_CAL_BANK_SEL_OVRD_MPLLB_CAL_BANK_SEL_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_PG_OVRD_IN - Override Values for Incoming Power-Gating Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PMA_PWR_STABLE_OVRD_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PMA_PWR_STABLE_OVRD_SHIFT (0U) /*! PMA_PWR_STABLE_OVRD - Enable overriding value for pma_pwr_stable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PMA_PWR_STABLE_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PMA_PWR_STABLE_OVRD_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PMA_PWR_STABLE_OVRD_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PCS_PWR_STABLE_OVRD_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PCS_PWR_STABLE_OVRD_SHIFT (1U) /*! PCS_PWR_STABLE_OVRD - Enable overriding value for pcs_pwr_stable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PCS_PWR_STABLE_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PCS_PWR_STABLE_OVRD_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PCS_PWR_STABLE_OVRD_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_VAL_SHIFT (2U) /*! PG_RESET_OVRD_VAL - Override Value for pg_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_EN_SHIFT (3U) /*! PG_RESET_OVRD_EN - Override Enable for pg_reset * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_RESET_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_VAL_MASK (0x10U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_VAL_SHIFT (4U) /*! PG_MODE_EN_OVRD_VAL - Override Value for pg_mode_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_EN_MASK (0x20U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_EN_SHIFT (5U) /*! PG_MODE_EN_OVRD_EN - Override Enable for pg_mode_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_PG_MODE_EN_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_VAL_MASK (0x40U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_VAL_SHIFT (6U) /*! BG_EN_OVRD_VAL - Override Value for bg_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_EN_MASK (0x80U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_EN_SHIFT (7U) /*! BG_EN_OVRD_EN - Override Enable for bg_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_IN_BG_EN_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_PG_OVRD_OUT - Override Values for Outgoing Power-Gating Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PMA_PWR_EN_OVRD_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PMA_PWR_EN_OVRD_SHIFT (0U) /*! PMA_PWR_EN_OVRD - Enable overriding value for pma_pwr_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PMA_PWR_EN_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PMA_PWR_EN_OVRD_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PMA_PWR_EN_OVRD_MASK) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PCS_PWR_EN_OVRD_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PCS_PWR_EN_OVRD_SHIFT (1U) /*! PCS_PWR_EN_OVRD - Enable overriding value for pcs_pwr_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PCS_PWR_EN_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PCS_PWR_EN_OVRD_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PG_OVRD_OUT_PCS_PWR_EN_OVRD_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_SUP_OVRD_IN - Override Values for Incoming Support Block Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_VAL_SHIFT (0U) /*! MPLLA_FORCE_EN_OVRD_VAL - Override Value for mplla_force_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_EN_SHIFT (1U) /*! MPLLA_FORCE_EN_OVRD_EN - Override Enable for mplla_force_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLA_FORCE_EN_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_VAL_SHIFT (2U) /*! MPLLB_FORCE_EN_OVRD_VAL - Override Value for mpllb_force_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_EN_SHIFT (3U) /*! MPLLB_FORCE_EN_OVRD_EN - Override Enable for mpllb_force_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_MPLLB_FORCE_EN_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_VAL_MASK (0x10U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_VAL_SHIFT (4U) /*! REF_CLK_EN_OVRD_VAL - Override Value for ref_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_EN_MASK (0x20U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_EN_SHIFT (5U) /*! REF_CLK_EN_OVRD_EN - Override Enable for ref_clk_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_IN_REF_CLK_EN_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_SUP_OVRD_OUT - Override Values for Out-going Support Block Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_VAL_SHIFT (0U) /*! MPLLA_FORCE_ACK_OVRD_VAL - Override Value for Output mplla_force_ack * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_EN_SHIFT (1U) /*! MPLLA_FORCE_ACK_OVRD_EN - Override Enable for Output mplla_force_ack * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLA_FORCE_ACK_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_VAL_SHIFT (2U) /*! MPLLB_FORCE_ACK_OVRD_VAL - Override Value for Output mpllb_force_ack * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_EN_SHIFT (3U) /*! MPLLB_FORCE_ACK_OVRD_EN - Override Enable for Output mpllb_force_ack * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SUP_OVRD_OUT_MPLLB_FORCE_ACK_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_RTUNE_RX_VAL - Resistor Tune RX Value */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_RX_VAL_RTUNE_RX_VAL_MASK (0x3FU) #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_RX_VAL_RTUNE_RX_VAL_SHIFT (0U) /*! RTUNE_RX_VAL - Stored resister tune RX value */ #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_RX_VAL_RTUNE_RX_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_RTUNE_RX_VAL_RTUNE_RX_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_RTUNE_RX_VAL_RTUNE_RX_VAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_RTUNE_TXDN_VAL - Resistor Tune TX Down Value */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_RTUNE_TXDN_VAL_MASK (0x3FFU) #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_RTUNE_TXDN_VAL_SHIFT (0U) /*! RTUNE_TXDN_VAL - Stored resister tune TX down value */ #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_RTUNE_TXDN_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_RTUNE_TXDN_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_RTUNE_TXDN_VAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_RTUNE_TXUP_VAL - Resistor Tune TX Up Value */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXUP_VAL_RTUNE_TXUP_VAL_MASK (0x3FFU) #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXUP_VAL_RTUNE_TXUP_VAL_SHIFT (0U) /*! RTUNE_TXUP_VAL - Stored resister tune TX up value */ #define ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXUP_VAL_RTUNE_TXUP_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXUP_VAL_RTUNE_TXUP_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_RTUNE_TXUP_VAL_RTUNE_TXUP_VAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_CMNCAL_STATUS - Common Calibration Status */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_INIT_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_INIT_SHIFT (0U) /*! CMNCAL_INIT - Indicates whether common calibration (mpll and rtune) has been started by this lane or not * 0b0..Not started * 0b1..Started */ #define ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_INIT_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_INIT_MASK) #define ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_DONE_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_DONE_SHIFT (1U) /*! CMNCAL_DONE - Indicates whether common calibration (mpll and rtune) has been completed by this lane or not * 0b0..Not completed * 0b1..Completed */ #define ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_CMNCAL_STATUS_CMNCAL_DONE_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_SRAM_OVRD_IN - Override for Incoming SRAM Inputs */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_VAL_SHIFT (0U) /*! SRAM_EXT_LD_DONE_OVRD_VAL - Override Value for input sram_ext_ld_done * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_EN_SHIFT (1U) /*! SRAM_EXT_LD_DONE_OVRD_EN - Override Enable for Input sram_ext_ld_done * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_EXT_LD_DONE_OVRD_EN_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_VAL_SHIFT (2U) /*! SRAM_BYPASS_OVRD_VAL - Override Value for Input sram_bypass * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_EN_SHIFT (3U) /*! SRAM_BYPASS_OVRD_EN - Override Enable for Input sram_bypass * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_OVRD_IN_SRAM_BYPASS_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_SRAM_IN - Monitor for SRAM Inputs */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_BYPASS_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_BYPASS_SHIFT (0U) /*! SRAM_BYPASS - Value from RAW PCS for sram_bypass */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_BYPASS_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_BYPASS_MASK) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_EXT_LD_DONE_MASK (0x2U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_EXT_LD_DONE_SHIFT (1U) /*! SRAM_EXT_LD_DONE - Value from RAW PCS for sram_ext_ld_done */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_EXT_LD_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_EXT_LD_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_IN_SRAM_EXT_LD_DONE_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_SRAM_OUT - Monitor for SRAM Outputs */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OUT_SRAM_INIT_DONE_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OUT_SRAM_INIT_DONE_SHIFT (0U) /*! SRAM_INIT_DONE - Value from RAW PCS for sram_init_done */ #define ENET_PHY_RAWCMN_DIG_AON_SRAM_OUT_SRAM_INIT_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_SRAM_OUT_SRAM_INIT_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_SRAM_OUT_SRAM_INIT_DONE_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_FW_VERSION_0 - Firmware Version 0 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_BRANCH_MASK (0xFU) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_BRANCH_SHIFT (0U) /*! BRANCH - BRANCH */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_BRANCH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_BRANCH_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_BRANCH_MASK) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MINOR_VER_MASK (0xFF0U) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MINOR_VER_SHIFT (4U) /*! MINOR_VER - Minor update in firmware for any bug fixes of function enhancement */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MINOR_VER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MINOR_VER_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MINOR_VER_MASK) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MAJOR_VER_MASK (0xF000U) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MAJOR_VER_SHIFT (12U) /*! MAJOR_VER - A major firmware label which corresponds to significant change in PCS RAW, PMA or firmware algorithm or structure */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MAJOR_VER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MAJOR_VER_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_0_MAJOR_VER_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_FW_VERSION_1 - Firmware Version 1 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_YEAR_MASK (0x7U) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_YEAR_SHIFT (0U) /*! YEAR - Year */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_YEAR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_YEAR_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_YEAR_MASK) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_MONTH_MASK (0x78U) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_MONTH_SHIFT (3U) /*! MONTH - Month (1-12) */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_MONTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_MONTH_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_MONTH_MASK) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_DAY_MASK (0xF80U) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_DAY_SHIFT (7U) /*! DAY - Day (1-31) */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_DAY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_DAY_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_DAY_MASK) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_FW_EN_MASK (0xF000U) #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_FW_EN_SHIFT (12U) /*! FW_EN - Selectively enable or disable certain FW features for the same branch */ #define ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_FW_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_FW_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_FW_VERSION_1_FW_EN_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_OVRD_IN_0 - Override Values for Incoming MPLLA Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_EN_SHIFT (0U) /*! MPLLA_EN - Override Value for mplla_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_REF_CLK_MPLLA_DIV2_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_REF_CLK_MPLLA_DIV2_EN_SHIFT (1U) /*! REF_CLK_MPLLA_DIV2_EN - Override Value for ref_clk_mplla_div2_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_REF_CLK_MPLLA_DIV2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_REF_CLK_MPLLA_DIV2_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_REF_CLK_MPLLA_DIV2_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV8_CLK_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV8_CLK_EN_SHIFT (2U) /*! MPLLA_DIV8_CLK_EN - Override Value for mplla_div8_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV8_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV8_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV10_CLK_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV10_CLK_EN_SHIFT (3U) /*! MPLLA_DIV10_CLK_EN - Override Value for mplla_div10_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV10_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV10_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV16P5_CLK_EN_MASK (0x10U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV16P5_CLK_EN_SHIFT (4U) /*! MPLLA_DIV16P5_CLK_EN - Override Value for mplla_div16p5_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_MULTIPLIER_MASK (0x1FE0U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_MULTIPLIER_SHIFT (5U) /*! MPLLA_MULTIPLIER - Override Value for mplla_multiplier */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_MULTIPLIER_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_TX_CLK_DIV_MASK (0x6000U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_TX_CLK_DIV_SHIFT (13U) /*! MPLLA_TX_CLK_DIV - Override Value for mplla_tx_clk_div */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_TX_CLK_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_TX_CLK_DIV_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_MPLLA_TX_CLK_DIV_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_OVRD_EN_MASK (0x8000U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_OVRD_EN_SHIFT (15U) /*! OVRD_EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_0_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_OVRD_IN_1 - Override Values for Incoming MPLLA Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_EN_SHIFT (0U) /*! MPLLA_SSC_EN - Override Value for mplla_ssc_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_UP_SPREAD_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_UP_SPREAD_SHIFT (1U) /*! MPLLA_SSC_UP_SPREAD - Override Value for mplla_ssc_up_spread * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_UP_SPREAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_UP_SPREAD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_UP_SPREAD_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_FRACN_CTRL_MASK (0x1FFCU) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_FRACN_CTRL_SHIFT (2U) /*! MPLLA_FRACN_CTRL - Override Value for mplla_fracn_ctrl */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_FRACN_CTRL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_FRACN_CTRL_MASK) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_CLK_SEL_MASK (0x2000U) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_CLK_SEL_SHIFT (13U) /*! MPLLA_SSC_CLK_SEL - Override Value for mplla_ssc_clk_sel[2:0] * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_CLK_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_1_MPLLA_SSC_CLK_SEL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_OVRD_IN_2 - Override Values for Incoming MPLLA Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_2_MPLLA_SSC_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_2_MPLLA_SSC_FREQ_CNT_INIT_SHIFT (0U) /*! MPLLA_SSC_FREQ_CNT_INIT - Override Value for mplla_ssc_freq_cnt_init[11:0] */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_2_MPLLA_SSC_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_2_MPLLA_SSC_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_2_MPLLA_SSC_FREQ_CNT_INIT_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_OVRD_IN_3 - Override Values for Incoming MPLLA Controls from ASIC 3 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_3_MPLLA_SSC_FREQ_CNT_PEAK_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_3_MPLLA_SSC_FREQ_CNT_PEAK_SHIFT (0U) /*! MPLLA_SSC_FREQ_CNT_PEAK - Override Value for mplla_ssc_freq_cnt_peak[7:0] */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_3_MPLLA_SSC_FREQ_CNT_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_3_MPLLA_SSC_FREQ_CNT_PEAK_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_3_MPLLA_SSC_FREQ_CNT_PEAK_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_OVRD_IN_4 - Override Values for Incoming MPLLA Controls from ASIC 4 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_4_MPLLA_BANDWIDTH_MASK (0xFFFFU) #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_4_MPLLA_BANDWIDTH_SHIFT (0U) /*! MPLLA_BANDWIDTH - Override Value for mplla_bandwidth[15:0] */ #define ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_4_MPLLA_BANDWIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_4_MPLLA_BANDWIDTH_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_OVRD_IN_4_MPLLA_BANDWIDTH_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_ASIC_IN_0 - Current Values for Incoming MPLLA Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_EN_SHIFT (0U) /*! MPLLA_EN - Value from ASIC for mplla_en */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_REF_CLK_MPLLA_DIV2_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_REF_CLK_MPLLA_DIV2_EN_SHIFT (1U) /*! REF_CLK_MPLLA_DIV2_EN - Value from ASIC for ref_clk_mplla_div2_en */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_REF_CLK_MPLLA_DIV2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_REF_CLK_MPLLA_DIV2_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_REF_CLK_MPLLA_DIV2_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV8_CLK_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV8_CLK_EN_SHIFT (2U) /*! MPLLA_DIV8_CLK_EN - Value from ASIC for mplla_div8_clk_en */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV8_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV8_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV10_CLK_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV10_CLK_EN_SHIFT (3U) /*! MPLLA_DIV10_CLK_EN - Value from ASIC for mplla_div10_clk_en */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV10_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV10_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV16P5_CLK_EN_MASK (0x10U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV16P5_CLK_EN_SHIFT (4U) /*! MPLLA_DIV16P5_CLK_EN - Value from ASIC for mplla_div16p5_clk_en */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_MULTIPLIER_MASK (0x1FE0U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_MULTIPLIER_SHIFT (5U) /*! MPLLA_MULTIPLIER - Value from ASIC for mplla_multiplier */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_MULTIPLIER_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_TX_CLK_DIV_MASK (0x6000U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_TX_CLK_DIV_SHIFT (13U) /*! MPLLA_TX_CLK_DIV - Value from ASIC for mplla_tx_clk_div */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_TX_CLK_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_TX_CLK_DIV_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_0_MPLLA_TX_CLK_DIV_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_ASIC_IN_1 - Current Values for Incoming MPLLA Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_EN_SHIFT (0U) /*! MPLLA_SSC_EN - Value from mplla_ssc_en */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_UP_SPREAD_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_UP_SPREAD_SHIFT (1U) /*! MPLLA_SSC_UP_SPREAD - Value from mplla_ssc_up_spread */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_UP_SPREAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_UP_SPREAD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_UP_SPREAD_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_FRACN_CTRL_MASK (0x1FFCU) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_FRACN_CTRL_SHIFT (2U) /*! MPLLA_FRACN_CTRL - Value from mplla_fracn_ctrl */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_FRACN_CTRL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_FRACN_CTRL_MASK) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_CLK_SEL_MASK (0x2000U) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_CLK_SEL_SHIFT (13U) /*! MPLLA_SSC_CLK_SEL - Value from mplla_ssc_clk_sel */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_CLK_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_1_MPLLA_SSC_CLK_SEL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_ASIC_IN_2 - Current Values for Incoming MPLLA Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_2_MPLLA_BANDWIDTH_MASK (0xFFFFU) #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_2_MPLLA_BANDWIDTH_SHIFT (0U) /*! MPLLA_BANDWIDTH - Value from ASIC for mplla_bandwidth */ #define ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_2_MPLLA_BANDWIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_2_MPLLA_BANDWIDTH_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_ASIC_IN_2_MPLLA_BANDWIDTH_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_FREQ_CNT_INIT_ASIC_IN - Current Values for Incoming Level Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_FREQ_CNT_INIT_ASIC_IN_MPLLA_SSC_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_SUP_DIG_MPLLA_FREQ_CNT_INIT_ASIC_IN_MPLLA_SSC_FREQ_CNT_INIT_SHIFT (0U) /*! MPLLA_SSC_FREQ_CNT_INIT - Value from ASIC for MPLLA_SSC_FREQ_CNT_INIT */ #define ENET_PHY_SUP_DIG_MPLLA_FREQ_CNT_INIT_ASIC_IN_MPLLA_SSC_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_FREQ_CNT_INIT_ASIC_IN_MPLLA_SSC_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_FREQ_CNT_INIT_ASIC_IN_MPLLA_SSC_FREQ_CNT_INIT_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL - MPLL Calibration Controls */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_MASK (0xFU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_SHIFT (0U) /*! LOAD_CNT - MSBs for the CHKFRQ FSM ld_val[10:0] load value * 0b0000..Gives a ld_val of 0, no PPM difference can be detected * 0b1000..Gives a load value of 1024, 3000 PPM resolution possible * 0b1010..Gives a load value of 1280, 2343 PPM resolution possible * 0b1011..Gives a load value of 1408, 2130 PPM resolution possible * 0b1100..Gives a load value of 1536, 1953 PPM resolution possible * 0b1111..Gives a load value of 1920, 1600 PPM resolution possible */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_MASK (0x10U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_SHIFT (4U) /*! MPLL_SKIPCAL - Skip Automatic (Internal) Calibration of MPLL (and also skip external calibration if it is enabled) * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_MASK (0x20U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_SHIFT (5U) /*! MPLL_EXTCAL - Enable external calibration of MPLL * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_MASK (0x40U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_SHIFT (6U) /*! EXT_CHKFRQ_EN - Check the frequency of the MPLL */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_MASK (0x7F80U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_SHIFT (7U) /*! EXT_COARSE_TUNE - Value of mpll_ana_coarse_tune_i[7:0] in external calibration mode */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_MASK (0x8000U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_SHIFT (15U) /*! EXT_CAL_DONE - Set the external calibration status to done * 0b0..Not set * 0b1..Set to done */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD - MPLL Override Controls */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_SHIFT (0U) /*! OVRD_SEL - Override enable bit * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_SHIFT (1U) /*! MPLL_FBDIGCLK_EN - Overrides the PWR FSM mpll_fb_dig_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_SHIFT (2U) /*! MPLL_PCLK_EN - Overrides the PWR FSM mpll_pclk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_MASK (0x3E0U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_SHIFT (5U) /*! DTB_SEL - DTB select for MPLL dtb signals possible values are: * 0b00001..> {mpll_fb_clk & ~scan_mode_i,ref_dig_clk & ~scan_mode_i} * 0b00010..> {mpll_ana_output_en_i,mpll_pclk_en} * 0b00100..> {mpll_cal_rdy,mpll_state} * 0b01000..> {mpll_chkfrq_done,mpll_tooslow} * 0b10000..> {curr_state[0], mpll_cnt[0]} */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT - MPLL Status */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_FSM_STATE_MASK (0xFU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_FSM_STATE_SHIFT (0U) /*! FSM_STATE - Current value of the PWR FSM state register */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_FSM_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_FSM_STATE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_FSM_STATE_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_MASK (0x10U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_SHIFT (4U) /*! MPLL_TOOSLOW - Current value of mpll_tooslow */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_MASK (0x20U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_SHIFT (5U) /*! CHKFRQ_DONE - Current value of mpll_chkfrq_done */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_CHKFRQ_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_MASK (0x40U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_SHIFT (6U) /*! MPLL_CAL_RDY - Current value of mpll_cal_rdy */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_R_LANES_MASK (0x80U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_R_LANES_SHIFT (7U) /*! MPLL_R_LANES - Current value of lane_mpll_r */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_R_LANES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_R_LANES_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_R_LANES_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_L_LANES_MASK (0x100U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_L_LANES_SHIFT (8U) /*! MPLL_L_LANES - Current value of lane_mpll_l */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_L_LANES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_L_LANES_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_L_LANES_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_SHIFT (9U) /*! MPLL_PCLK_EN - Current value of mpll_pclk_en */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_MASK (0x400U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_SHIFT (10U) /*! MPLL_OUTPUT_EN - Current value of mpll_ana_output_en_i */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_MASK (0x800U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_SHIFT (11U) /*! MPLL_FBCLK_EN - Current value of mpll_ana_fb_clk_en_i */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_MASK (0x1000U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_SHIFT (12U) /*! MPLL_CAL - Current value of mpll_ana_cal_i */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_CAL_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_RST_MASK (0x2000U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_RST_SHIFT (13U) /*! MPLL_RST - Current value of mpll_ana_rst_i */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_RST_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_RST_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_MASK (0x4000U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_SHIFT (14U) /*! MPLL_ANA_EN - Current value of mpll_ana_en_i */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_ANA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD - Thresholds for MPLL CAL Update Timer and MPLL VCO Stabilization Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_SHIFT (0U) /*! VCO_STABILIZATION_TIME_THRESHOLD - Threshold for the VCO stabilization timer in terms of number * of reference clock cycles. Here the reference clock means the one that is fed to the phase * detector of the corresponding PLL, not the raw reference clock */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK (0x1E00U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_SHIFT (9U) /*! MPLL_CAL_UPDATE_TIME_THRESHOLD - Threshold for the MPLL calibration control word update timer in terms of number of ref_rang_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD - Thresholds for PCLK Enable and MPLL VCO Clock Stabilization Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK (0x7FFU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_SHIFT (0U) /*! VCO_CLK_STABILIZATION_TIME_THRESHOLD - Threshold for the VCO clock stabilization timer in terms * of number of reference clock cycles. Here the reference clock means the one that is fed to the * phase detector of the corresponding PLL, not the raw reference clock */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_MASK (0xF800U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_SHIFT (11U) /*! PCLK_EN_TIME_THRESHOLD - Threshold for the PCLK enable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH - Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_MASK (0x1FU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_SHIFT (0U) /*! PCLK_DIS_TIME_THRESHOLD - Threshold for the PCLK disable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK (0x3E0U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_SHIFT (5U) /*! MPLL_VCO_PWRDN_TIME_THRESHOLD - Threshold for the MPLL VCO power down timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH - Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK (0x7FU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_SHIFT (0U) /*! MPLL_ANA_PWRUP_TIME_THRESHOLD - Threshold for the MPLL analog power up timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD - Thresholds for MPLL Feedback Clock Enable and MPLL Feedback Digital Clock Disable Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_MASK (0xFU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_SHIFT (0U) /*! MPLL_FBCLK_EN_TIME_THRESHOLD - Threshold for the MPLL feedback clock enable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK (0xF0U) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_SHIFT (4U) /*! MPLL_FBDIGCLK_DIS_TIME_THRESHOLD - Threshold for the MPLL feedback digital clock disable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL - MPLL coarse_tune Value */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_SHIFT (0U) /*! MPLL_COARSE_TUNE_VAL - Current value of mpll_ana_coarse_tune_i */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE - Value for MPLL coarse_tune When Skipping Calibration */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_SHIFT (0U) /*! MPLL_SKIPCAL_COARSE_TUNE - Value for MPLL coarse_tune when calibration is skipped */ #define ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_SSC_SS_PHASE - Current MPLL Phase Selector Value */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_DTHR_MASK (0x3U) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_DTHR_SHIFT (0U) /*! DTHR - Bits below the useful resolution (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_DTHR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_DTHR_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_DTHR_MASK) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_VAL_MASK (0x7FCU) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_VAL_SHIFT (2U) /*! VAL - Phase value from zero reference (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_VAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_VAL_MASK) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_ZERO_FREQ_MASK (0x800U) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_ZERO_FREQ_SHIFT (11U) /*! ZERO_FREQ - Zero Frequency Register */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_ZERO_FREQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_ZERO_FREQ_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_ZERO_FREQ_MASK) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_FRACN_CTRL_DIV_MASK (0xF000U) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_FRACN_CTRL_DIV_SHIFT (12U) /*! FRACN_CTRL_DIV - FracN Control Divisor */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_FRACN_CTRL_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_FRACN_CTRL_DIV_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_PHASE_FRACN_CTRL_DIV_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_SSC_SS_FREQ_0 - Frequency Control for Spread Spectrum 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_CNT_INIT_SHIFT (0U) /*! FREQ_CNT_INIT - Initial Frequency Counter Value (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_CNT_INIT_MASK) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_0_OVRD_MASK (0x1000U) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_0_OVRD_SHIFT (12U) /*! FREQ_0_OVRD - Frequency Register Override */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_0_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_0_OVRD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_0_FREQ_0_OVRD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLA_SSC_SS_FREQ_1 - Frequency Control for Spread Spectrum 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_PEAK_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_PEAK_SHIFT (0U) /*! FREQ_PEAK - Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_PEAK_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_PEAK_MASK) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_1_OVRD_MASK (0x100U) #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_1_OVRD_SHIFT (8U) /*! FREQ_1_OVRD - Frequency Register Override */ #define ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_1_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_1_OVRD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLA_SSC_SS_FREQ_1_FREQ_1_OVRD_MASK) /*! @} */ /*! @name SUP_ANA_MPLLA_LOOP_CTRL - MPLLA_LOOP_CTRL */ /*! @{ */ #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_ovrd_pr_bypass_MASK (0x2U) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_ovrd_pr_bypass_SHIFT (1U) /*! ovrd_pr_bypass - Enable local control of PR bypass signal * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_ovrd_pr_bypass(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_ovrd_pr_bypass_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_ovrd_pr_bypass_MASK) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_mode_old_ssc_MASK (0x4U) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_mode_old_ssc_SHIFT (2U) /*! mode_old_ssc - Switch back to 2-bit ssc * 0b0..No switch * 0b1..Switch back */ #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_mode_old_ssc(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_mode_old_ssc_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_mode_old_ssc_MASK) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pr_bypass_MASK (0x8U) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pr_bypass_SHIFT (3U) /*! pr_bypass - Set local pr bypass control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pr_bypass(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pr_bypass_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pr_bypass_MASK) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_meas_iv_23_MASK (0x10U) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_meas_iv_23_SHIFT (4U) /*! meas_iv_23 - VCO control buffer bypass (active high) */ #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_meas_iv_23(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_meas_iv_23_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_meas_iv_23_MASK) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_lpn_vreg_MASK (0x20U) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_lpn_vreg_SHIFT (5U) /*! lpn_vreg - vreg_vco draws power from vph instead of vp when asserted */ #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_lpn_vreg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_lpn_vreg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_lpn_vreg_MASK) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pfd_pw_ctrl_MASK (0xC0U) #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pfd_pw_ctrl_SHIFT (6U) /*! pfd_pw_ctrl - PFD Reset Pulse Width Control * 0b11..Maximum pulse width * 0b00..Minimum pulse width */ #define ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pfd_pw_ctrl(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pfd_pw_ctrl_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_LOOP_CTRL_pfd_pw_ctrl_MASK) /*! @} */ /*! @name SUP_ANA_MPLLA_OVRD - MPLLA_OVRD */ /*! @{ */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_enable_MASK (0x1U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_enable_SHIFT (0U) /*! ovrd_enable - Enable local control of enable signal (mpll_en) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_enable(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_enable_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_enable_MASK) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_enable_reg_MASK (0x2U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_enable_reg_SHIFT (1U) /*! enable_reg - Set local enable control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_enable_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_enable_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_enable_reg_MASK) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_cal_MASK (0x4U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_cal_SHIFT (2U) /*! ovrd_cal - Enable local control of calibration signal (mpll_cal) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_cal(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_cal_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_cal_MASK) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_cal_reg_MASK (0x8U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_cal_reg_SHIFT (3U) /*! cal_reg - Set local calibration control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_cal_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_cal_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_cal_reg_MASK) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_fb_clk_en_MASK (0x10U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_fb_clk_en_SHIFT (4U) /*! ovrd_fb_clk_en - Enable local control of feedback clock control signal (mpll_fb_clk_en) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_fb_clk_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_fb_clk_en_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_fb_clk_en_MASK) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_fb_clk_en_reg_MASK (0x20U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_fb_clk_en_reg_SHIFT (5U) /*! fb_clk_en_reg - Set local feedback clock control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_fb_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_fb_clk_en_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_fb_clk_en_reg_MASK) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_reset_MASK (0x40U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_reset_SHIFT (6U) /*! ovrd_reset - Enable local control of reset signal (mpll_rst) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_reset(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_reset_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_ovrd_reset_MASK) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_reset_reg_MASK (0x80U) #define ENET_PHY_SUP_ANA_MPLLA_OVRD_reset_reg_SHIFT (7U) /*! reset_reg - Set local reset control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLA_OVRD_reset_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLA_OVRD_reset_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLA_OVRD_reset_reg_MASK) /*! @} */ /*! @name SUP_DIG_ANA_MPLLA_OVRD_OUT - Override Value for MPLLA Signals Going to ANA */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_ANA_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_ANA_EN_SHIFT (0U) /*! MPLLA_ANA_EN - Overrides the mplla_ana_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_ANA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_ANA_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_ANA_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_RST_MASK (0x2U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_RST_SHIFT (1U) /*! MPLLA_RST - Overrides the mplla_ana_rst signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_RST_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_RST_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_CAL_MASK (0x4U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_CAL_SHIFT (2U) /*! MPLLA_CAL - Overrides the mplla_ana_cal signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_CAL_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_CAL_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_EN_SHIFT (3U) /*! MPLLA_OUTPUT_EN - Overrides the mplla_ana_output_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_L_EN_MASK (0x10U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_L_EN_SHIFT (4U) /*! MPLLA_OUTPUT_L_EN - Overrides the mplla_ana_output_l_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_L_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_L_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_L_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_R_EN_MASK (0x20U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_R_EN_SHIFT (5U) /*! MPLLA_OUTPUT_R_EN - Overrides the mplla_ana_output_r_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_R_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_R_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_OUTPUT_R_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV8_CLK_EN_MASK (0x40U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV8_CLK_EN_SHIFT (6U) /*! MPLLA_DIV8_CLK_EN - Overrides the mplla_ana_div8_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV8_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV8_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV10_CLK_EN_MASK (0x80U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV10_CLK_EN_SHIFT (7U) /*! MPLLA_DIV10_CLK_EN - Overrides the mplla_ana_div10_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV10_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV10_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_FBCLK_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_FBCLK_EN_SHIFT (8U) /*! MPLLA_FBCLK_EN - Overrides the mplla_fb_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_FBCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_FBCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_FBCLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV16P5_CLK_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV16P5_CLK_EN_SHIFT (9U) /*! MPLLA_DIV16P5_CLK_EN - Overrides the mplla_ana_div16p5_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV_CLK_EN_MASK (0x400U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV_CLK_EN_SHIFT (10U) /*! MPLLA_DIV_CLK_EN - Overrides the mplla_ana_div_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_MPLLA_DIV_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_OVRD_SEL_MASK (0x800U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_OVRD_SEL_SHIFT (11U) /*! OVRD_SEL - Override bit for mplla_ana outputs * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_OVRD_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_OVRD_SEL_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_OVRD_OUT_OVRD_SEL_MASK) /*! @} */ /*! @name SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT - Override Value for MPLLA PMIX Signals Going to ANA */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_MASK (0xFFU) #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_SHIFT (0U) /*! MPLLA_PMIX_SEL - Overrides the mplla_ana_pmix_sel signal */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_OVRD_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_OVRD_EN_SHIFT (8U) /*! MPLLA_PMIX_SEL_OVRD_EN - Override bit for mplla_ana_pmix_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_SEL_OVRD_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_EN_SHIFT (9U) /*! MPLLA_PMIX_EN - Override bit for mplla_ana_pmix_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_OVRD_EN_MASK (0x400U) #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_OVRD_EN_SHIFT (10U) /*! MPLLA_PMIX_OVRD_EN - Override bit for mplla_ana_pmix_sel signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT_MPLLA_PMIX_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLA_BW_OVRD_IN - Override Values for Incoming MPLLA Bandwidth */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLA_BW_OVRD_IN_MPLLA_BW_OVRD_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWCMN_DIG_MPLLA_BW_OVRD_IN_MPLLA_BW_OVRD_VAL_SHIFT (0U) /*! MPLLA_BW_OVRD_VAL - Override Value for mplla_bandwidth[15:0] */ #define ENET_PHY_RAWCMN_DIG_MPLLA_BW_OVRD_IN_MPLLA_BW_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_BW_OVRD_IN_MPLLA_BW_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_BW_OVRD_IN_MPLLA_BW_OVRD_VAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN - Override Values for Incoming MPLLA SSC Control Settings */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_FRACN_CTRL_MASK (0x7FFU) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_FRACN_CTRL_SHIFT (0U) /*! MPLLA_FRACN_CTRL - Override Value for mplla_fracn_ctrl[10:0] */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_FRACN_CTRL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_FRACN_CTRL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_UP_SPREAD_MASK (0x800U) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_UP_SPREAD_SHIFT (11U) /*! MPLLA_SSC_UP_SPREAD - Override Value for mplla_ssc_up_spread * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_UP_SPREAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_UP_SPREAD_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_UP_SPREAD_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CLK_SEL_MASK (0x1000U) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CLK_SEL_SHIFT (12U) /*! MPLLA_SSC_CLK_SEL - Override Value for mplla_ssc_clk_sel * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CLK_SEL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CLK_SEL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CTL_OVRD_EN_MASK (0x2000U) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CTL_OVRD_EN_SHIFT (13U) /*! MPLLA_SSC_CTL_OVRD_EN - Override Value for MPLLA SSC control settings * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CTL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CTL_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_MPLLA_SSC_CTL_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN - Override Values for Incoming MPLLA SSC Input Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_SHIFT (0U) /*! MPLLA_SSC_FREQ_CNT_INIT - Override Value for mplla_ssc_freq_cnt_init */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_EN_MASK (0x1000U) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_EN_SHIFT (12U) /*! MPLLA_SSC_FREQ_CNT_INIT_EN - Override Value for mplla_ssc_freq_cnt_init * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_FREQ_CNT_INIT_EN_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_VAL_MASK (0x2000U) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_VAL_SHIFT (13U) /*! MPLLA_SSC_EN_OVRD_VAL - Override Value for MPLLA SSC enable * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_EN_MASK (0x4000U) #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_EN_SHIFT (14U) /*! MPLLA_SSC_EN_OVRD_EN - Override Enable for MPLLA SSC Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_MPLLA_SSC_EN_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLA_MISC_OVRD_IN - Override Values for Incoming MPLLA-Related Input Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_SHIFT (0U) /*! MPLLA_SSC_FREQ_CNT_PEAK - Override Value for mplla_ssc_freq_cnt_peak[7:0] */ #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_EN_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_EN_SHIFT (8U) /*! MPLLA_SSC_FREQ_CNT_PEAK_EN - Override Value for mplla_ssc_freq_cnt_peak * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_SSC_FREQ_CNT_PEAK_EN_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_TX_CLK_DIV_OVRD_VAL_MASK (0x600U) #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_TX_CLK_DIV_OVRD_VAL_SHIFT (9U) /*! MPLLA_TX_CLK_DIV_OVRD_VAL - Override Value for MPLLA SSC enable */ #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_TX_CLK_DIV_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_TX_CLK_DIV_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_TX_CLK_DIV_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_OVRD_EN_MASK (0x800U) #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_OVRD_EN_SHIFT (11U) /*! MPLLA_OVRD_EN - Override Enable for mplla_bandwidth and mplla_tx_clk_div * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLA_MISC_OVRD_IN_MPLLA_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0 - MPLLA Coarse Tune Value for Bank 0 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_BANK_0_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_BANK_0_SHIFT (0U) /*! MPLLA_COARSE_TUNE_BANK_0 - Stored bank0 coarse tune value for MPLLA */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_BANK_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_BANK_0_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_BANK_0_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_DONE_BANK_0_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_DONE_BANK_0_SHIFT (8U) /*! MPLLA_COARSE_TUNE_DONE_BANK_0 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_DONE_BANK_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_DONE_BANK_0_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_0_MPLLA_COARSE_TUNE_DONE_BANK_0_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1 - MPLLA Coarse Tune Value for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_BANK_1_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_BANK_1_SHIFT (0U) /*! MPLLA_COARSE_TUNE_BANK_1 - Stored bank 1 coarse tune value for MPLLA */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_BANK_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_BANK_1_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_BANK_1_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_DONE_BANK_1_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_DONE_BANK_1_SHIFT (8U) /*! MPLLA_COARSE_TUNE_DONE_BANK_1 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_DONE_BANK_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_DONE_BANK_1_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_1_MPLLA_COARSE_TUNE_DONE_BANK_1_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2 - MPLLA Coarse Tune Value for Bank 2 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_BANK_2_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_BANK_2_SHIFT (0U) /*! MPLLA_COARSE_TUNE_BANK_2 - Stored bank 2 coarse tune value for MPLLA */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_BANK_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_BANK_2_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_BANK_2_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_DONE_BANK_2_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_DONE_BANK_2_SHIFT (8U) /*! MPLLA_COARSE_TUNE_DONE_BANK_2 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_DONE_BANK_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_DONE_BANK_2_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_2_MPLLA_COARSE_TUNE_DONE_BANK_2_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3 - MPLLA Coarse Tune Value for Bank 3 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_BANK_3_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_BANK_3_SHIFT (0U) /*! MPLLA_COARSE_TUNE_BANK_3 - Stored bank 3 coarse tune value for MPLLA */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_BANK_3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_BANK_3_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_BANK_3_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_DONE_BANK_3_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_DONE_BANK_3_SHIFT (8U) /*! MPLLA_COARSE_TUNE_DONE_BANK_3 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_DONE_BANK_3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_DONE_BANK_3_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_BANK_3_MPLLA_COARSE_TUNE_DONE_BANK_3_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL - Value for MPLLA Bank Select */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL_MPLLA_CAL_BANK_SEL_MASK (0x3U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL_MPLLA_CAL_BANK_SEL_SHIFT (0U) /*! MPLLA_CAL_BANK_SEL - Value for MPLLA Bank select */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL_MPLLA_CAL_BANK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL_MPLLA_CAL_BANK_SEL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL_MPLLA_CAL_BANK_SEL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_DONE - Valid Calibrated Value for MPLLA Calibration Bank */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_DONE_MPLLA_COARSE_TUNE_DONE_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_DONE_MPLLA_COARSE_TUNE_DONE_SHIFT (0U) /*! MPLLA_COARSE_TUNE_DONE - Indicates if the selected MPLLA Calibration bank has the valid calibrated value * 0b0..Invalid * 0b1..Valid */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_DONE_MPLLA_COARSE_TUNE_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_DONE_MPLLA_COARSE_TUNE_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_DONE_MPLLA_COARSE_TUNE_DONE_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_COARSE_TUNE - Selected COARSE TUNE Value for MPLLA */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_MPLLA_COARSE_TUNE_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_MPLLA_COARSE_TUNE_SHIFT (0U) /*! MPLLA_COARSE_TUNE - Selected coarse tune value for MPLLA */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_MPLLA_COARSE_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_MPLLA_COARSE_TUNE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_COARSE_TUNE_MPLLA_COARSE_TUNE_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_IN_RECAL - MPLLA Re-Calibration */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_IN_RECAL_MPLLA_IN_RECAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_IN_RECAL_MPLLA_IN_RECAL_SHIFT (0U) /*! MPLLA_IN_RECAL - Indicates if MPLLA is in re-calibration * 0b0..Not in re-calibration * 0b1..In re-calibration */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_IN_RECAL_MPLLA_IN_RECAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_IN_RECAL_MPLLA_IN_RECAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_IN_RECAL_MPLLA_IN_RECAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL - Current Bank Selected for MPLLA Coarse Tune in PMA */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL_PMA_MPLLA_RECAL_BANK_SEL_MASK (0x3U) #define ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL_PMA_MPLLA_RECAL_BANK_SEL_SHIFT (0U) /*! PMA_MPLLA_RECAL_BANK_SEL - Current bank selected for MPLLA coarse tune in PMA */ #define ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL_PMA_MPLLA_RECAL_BANK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL_PMA_MPLLA_RECAL_BANK_SEL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL_PMA_MPLLA_RECAL_BANK_SEL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLA_BANK_SEL_DONE - Status for MPLLA Re-Calibration or Switching */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_BANK_SEL_DONE_DONE_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_BANK_SEL_DONE_DONE_SHIFT (0U) /*! DONE - Status for MPLLA re-calibration or switching */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLA_BANK_SEL_DONE_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLA_BANK_SEL_DONE_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLA_BANK_SEL_DONE_DONE_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_OVRD_IN_0 - Override Values for Incoming MPLLB Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_EN_SHIFT (0U) /*! MPLLB_EN - Override Value for mpllb_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_REF_CLK_MPLLB_DIV2_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_REF_CLK_MPLLB_DIV2_EN_SHIFT (1U) /*! REF_CLK_MPLLB_DIV2_EN - Override Value for ref_clk_mpllb_div2_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_REF_CLK_MPLLB_DIV2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_REF_CLK_MPLLB_DIV2_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_REF_CLK_MPLLB_DIV2_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV8_CLK_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV8_CLK_EN_SHIFT (2U) /*! MPLLB_DIV8_CLK_EN - Override Value for mpllb_div8_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV8_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV8_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV10_CLK_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV10_CLK_EN_SHIFT (3U) /*! MPLLB_DIV10_CLK_EN - Override Value for mpllb_div10_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV10_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_DIV10_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_MULTIPLIER_MASK (0xFF0U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_MULTIPLIER_SHIFT (4U) /*! MPLLB_MULTIPLIER - Override Value for mpllb_multiplier */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_MULTIPLIER_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_TX_CLK_DIV_MASK (0x3000U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_TX_CLK_DIV_SHIFT (12U) /*! MPLLB_TX_CLK_DIV - Override Value for mpllb_tx_clk_div */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_TX_CLK_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_TX_CLK_DIV_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_MPLLB_TX_CLK_DIV_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_OVRD_EN_MASK (0x4000U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_OVRD_EN_SHIFT (14U) /*! OVRD_EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_0_OVRD_EN_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_OVRD_IN_1 - Override Values for Incoming MPLLB Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_EN_SHIFT (0U) /*! MPLLB_SSC_EN - Override Value for mpllb_ssc_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_UP_SPREAD_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_UP_SPREAD_SHIFT (1U) /*! MPLLB_SSC_UP_SPREAD - Override Value for mpllb_ssc_up_spread * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_UP_SPREAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_UP_SPREAD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_UP_SPREAD_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_FRACN_CTRL_MASK (0x1FFCU) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_FRACN_CTRL_SHIFT (2U) /*! MPLLB_FRACN_CTRL - Override Value for mpllb_fracn_ctrl */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_FRACN_CTRL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_FRACN_CTRL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_CLK_SEL_MASK (0x2000U) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_CLK_SEL_SHIFT (13U) /*! MPLLB_SSC_CLK_SEL - Override Value for mpllb_ssc_clk_sel[2:0] * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_CLK_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_1_MPLLB_SSC_CLK_SEL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_OVRD_IN_2 - Override Values for Incoming MPLLB Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_2_MPLLB_SSC_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_2_MPLLB_SSC_FREQ_CNT_INIT_SHIFT (0U) /*! MPLLB_SSC_FREQ_CNT_INIT - Override Value for mpllb_ssc_freq_cnt_init[11:0] */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_2_MPLLB_SSC_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_2_MPLLB_SSC_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_2_MPLLB_SSC_FREQ_CNT_INIT_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_OVRD_IN_3 - Override Values for Incoming MPLLB Controls from ASIC 3 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_3_MPLLB_SSC_FREQ_CNT_PEAK_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_3_MPLLB_SSC_FREQ_CNT_PEAK_SHIFT (0U) /*! MPLLB_SSC_FREQ_CNT_PEAK - Override Value for mpllb_ssc_freq_cnt_peak[7:0] */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_3_MPLLB_SSC_FREQ_CNT_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_3_MPLLB_SSC_FREQ_CNT_PEAK_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_3_MPLLB_SSC_FREQ_CNT_PEAK_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_OVRD_IN_4 - Override Values for Incoming MPLLB Controls from ASIC 4 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_4_MPLLB_BANDWIDTH_MASK (0xFFFFU) #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_4_MPLLB_BANDWIDTH_SHIFT (0U) /*! MPLLB_BANDWIDTH - Override Value for mpllb_bandwidth[15:0] */ #define ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_4_MPLLB_BANDWIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_4_MPLLB_BANDWIDTH_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_OVRD_IN_4_MPLLB_BANDWIDTH_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_ASIC_IN_0 - Current Values for Incoming MPLLB Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_EN_SHIFT (0U) /*! MPLLB_EN - Value from ASIC for mpllb_en */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_REF_CLK_MPLLB_DIV2_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_REF_CLK_MPLLB_DIV2_EN_SHIFT (1U) /*! REF_CLK_MPLLB_DIV2_EN - Value from ASIC for ref_clk_mpllb_div2_en */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_REF_CLK_MPLLB_DIV2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_REF_CLK_MPLLB_DIV2_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_REF_CLK_MPLLB_DIV2_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV8_CLK_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV8_CLK_EN_SHIFT (2U) /*! MPLLB_DIV8_CLK_EN - Value from ASIC for mpllb_div8_clk_en */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV8_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV8_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV10_CLK_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV10_CLK_EN_SHIFT (3U) /*! MPLLB_DIV10_CLK_EN - Value from ASIC for mpllb_div10_clk_en */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV10_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_DIV10_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_MULTIPLIER_MASK (0xFF0U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_MULTIPLIER_SHIFT (4U) /*! MPLLB_MULTIPLIER - Value from ASIC for mpllb_multiplier */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_MULTIPLIER_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_MULTIPLIER_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_TX_CLK_DIV_MASK (0x3000U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_TX_CLK_DIV_SHIFT (12U) /*! MPLLB_TX_CLK_DIV - Value from ASIC for mpllb_tx_clk_div */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_TX_CLK_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_TX_CLK_DIV_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_0_MPLLB_TX_CLK_DIV_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_ASIC_IN_1 - Current Values for Incoming MPLLB Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_EN_SHIFT (0U) /*! MPLLB_SSC_EN - Value from mpllb_ssc_en */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_UP_SPREAD_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_UP_SPREAD_SHIFT (1U) /*! MPLLB_SSC_UP_SPREAD - Value from mpllb_ssc_up_spread */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_UP_SPREAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_UP_SPREAD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_UP_SPREAD_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_FRACN_CTRL_MASK (0x1FFCU) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_FRACN_CTRL_SHIFT (2U) /*! MPLLB_FRACN_CTRL - Value from mpllb_fracn_ctrl */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_FRACN_CTRL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_FRACN_CTRL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_CLK_SEL_MASK (0x2000U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_CLK_SEL_SHIFT (13U) /*! MPLLB_SSC_CLK_SEL - Value from mpllb_ssc_clk_sel[2:0] */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_CLK_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_MPLLB_SSC_CLK_SEL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_VPH_NOMINAL_MASK (0xC000U) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_VPH_NOMINAL_SHIFT (14U) /*! VPH_NOMINAL - Value from vph_nominal */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_VPH_NOMINAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_VPH_NOMINAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_1_VPH_NOMINAL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_ASIC_IN_2 - Current Values for Incoming MPLLB Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_2_MPLLB_BANDWIDTH_MASK (0xFFFFU) #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_2_MPLLB_BANDWIDTH_SHIFT (0U) /*! MPLLB_BANDWIDTH - Value from ASIC for mpllb_bandwidth */ #define ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_2_MPLLB_BANDWIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_2_MPLLB_BANDWIDTH_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_ASIC_IN_2_MPLLB_BANDWIDTH_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_FREQ_CNT_INIT_ASIC_IN - Current Values for Incoming Level Controls from ASIC */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_FREQ_CNT_INIT_ASIC_IN_MPLLB_SSC_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_SUP_DIG_MPLLB_FREQ_CNT_INIT_ASIC_IN_MPLLB_SSC_FREQ_CNT_INIT_SHIFT (0U) /*! MPLLB_SSC_FREQ_CNT_INIT - Value from ASIC for MPLLB_SSC_FREQ_CNT_INIT */ #define ENET_PHY_SUP_DIG_MPLLB_FREQ_CNT_INIT_ASIC_IN_MPLLB_SSC_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_FREQ_CNT_INIT_ASIC_IN_MPLLB_SSC_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_FREQ_CNT_INIT_ASIC_IN_MPLLB_SSC_FREQ_CNT_INIT_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL - MPLL Calibration Controls */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_MASK (0xFU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_SHIFT (0U) /*! LOAD_CNT - MSBs for the CHKFRQ FSM ld_val[10:0] load value * 0b0000..Gives a ld_val of 0, no PPM difference can be detected * 0b1000..Gives a load value of 1024, 3000PPM resolution possible * 0b1010..Gives a load value of 1280, 2343PPM resolution possible * 0b1011..Gives a load value of 1408, 2130PPM resolution possible * 0b1100..Gives a load value of 1536, 1953PPM resolution possible * 0b1111..Gives a load value of 1920, 1600PPM resolution possible */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_LOAD_CNT_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_MASK (0x10U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_SHIFT (4U) /*! MPLL_SKIPCAL - Skip Automatic (Internal) Calibration of MPLL (and also skip external calibration if it is enabled) * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_SKIPCAL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_MASK (0x20U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_SHIFT (5U) /*! MPLL_EXTCAL - Enable external calibration of MPLL * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_MPLL_EXTCAL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_MASK (0x40U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_SHIFT (6U) /*! EXT_CHKFRQ_EN - Check the frequency of the MPLL */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CHKFRQ_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_MASK (0x7F80U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_SHIFT (7U) /*! EXT_COARSE_TUNE - Value of mpll_ana_coarse_tune_i[7:0] in external calibration mode */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_COARSE_TUNE_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_MASK (0x8000U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_SHIFT (15U) /*! EXT_CAL_DONE - Set the external calibration status to done * 0b0..Not set * 0b1..Set to done */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_EXT_CAL_DONE_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD - MPLL Override Controls */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_MASK (0x1U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_SHIFT (0U) /*! OVRD_SEL - Override enable bit * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_OVRD_SEL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_MASK (0x2U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_SHIFT (1U) /*! MPLL_FBDIGCLK_EN - Overrides the PWR FSM mpll_fb_dig_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_FBDIGCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_MASK (0x4U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_SHIFT (2U) /*! MPLL_PCLK_EN - Overrides the PWR FSM mpll_pclk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_MPLL_PCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_MASK (0x3E0U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_SHIFT (5U) /*! DTB_SEL - DTB select for MPLL dtb signals possible values are: * 0b00001..> {mpll_fb_clk & ~scan_mode_i,ref_dig_clk & ~scan_mode_i} * 0b00010..> {mpll_ana_output_en_i,mpll_pclk_en} * 0b00100..> {mpll_cal_rdy,mpll_state} * 0b01000..> {mpll_chkfrq_done,mpll_tooslow} * 0b10000..> {curr_state[0], mpll_cnt[0]} */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DTB_SEL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT - MPLL Status */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_FSM_STATE_MASK (0xFU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_FSM_STATE_SHIFT (0U) /*! FSM_STATE - Current value of the PWR FSM state register */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_FSM_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_FSM_STATE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_FSM_STATE_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_MASK (0x10U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_SHIFT (4U) /*! MPLL_TOOSLOW - Current value of mpll_tooslow */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_TOOSLOW_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_MASK (0x20U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_SHIFT (5U) /*! CHKFRQ_DONE - Current value of mpll_chkfrq_done */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_CHKFRQ_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_CHKFRQ_DONE_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_MASK (0x40U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_SHIFT (6U) /*! MPLL_CAL_RDY - Current value of mpll_cal_rdy */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_RDY_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_R_LANES_MASK (0x80U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_R_LANES_SHIFT (7U) /*! MPLL_R_LANES - Current value of lane_mpll_r */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_R_LANES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_R_LANES_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_R_LANES_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_L_LANES_MASK (0x100U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_L_LANES_SHIFT (8U) /*! MPLL_L_LANES - Current value of lane_mpll_l */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_L_LANES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_L_LANES_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_L_LANES_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_SHIFT (9U) /*! MPLL_PCLK_EN - Current value of mpll_pclk_en */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_PCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_MASK (0x400U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_SHIFT (10U) /*! MPLL_OUTPUT_EN - Current value of mpll_ana_output_en_i */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_OUTPUT_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_MASK (0x800U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_SHIFT (11U) /*! MPLL_FBCLK_EN - Current value of mpll_ana_fb_clk_en_i */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_FBCLK_EN_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_MASK (0x1000U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_SHIFT (12U) /*! MPLL_CAL - Current value of mpll_ana_cal_i */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_CAL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_RST_MASK (0x2000U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_RST_SHIFT (13U) /*! MPLL_RST - Current value of mpll_ana_rst_i */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_RST_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_RST_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_MASK (0x4000U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_SHIFT (14U) /*! MPLL_ANA_EN - Current value of mpll_ana_en_i */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_ANA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_MPLL_ANA_EN_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD - Thresholds for MPLL CAL Update Timer and MPLL VCO Stabilization Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_MASK (0x1FFU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_SHIFT (0U) /*! VCO_STABILIZATION_TIME_THRESHOLD - Threshold for the VCO stabilization timer in terms of number * of reference clock cycles. Here the reference clock means the one that is fed to the phase * detector of the corresponding PLL, not the raw reference clock */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_VCO_STABILIZATION_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK (0x1E00U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_SHIFT (9U) /*! MPLL_CAL_UPDATE_TIME_THRESHOLD - Threshold for the MPLL calibration control word update timer in terms of number of ref_rang_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD - Thresholds for PCLK Enable and MPLL VCO Clock Stabilization Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK (0x7FFU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_SHIFT (0U) /*! VCO_CLK_STABILIZATION_TIME_THRESHOLD - Threshold for the VCO clock stabilization timer in terms * of number of reference clock cycles. Here the reference clock means the one that is fed to the * phase detector of the corresponding PLL, not the raw reference clock */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_MASK (0xF800U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_SHIFT (11U) /*! PCLK_EN_TIME_THRESHOLD - Threshold for the PCLK enable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_PCLK_EN_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH - Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_MASK (0x1FU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_SHIFT (0U) /*! PCLK_DIS_TIME_THRESHOLD - Threshold for the PCLK disable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_PCLK_DIS_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK (0x3E0U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_SHIFT (5U) /*! MPLL_VCO_PWRDN_TIME_THRESHOLD - Threshold for the MPLL VCO power down timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESH_MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH - Thresholds for PCLK Disable and MPLL VCO POWER DOWN and MPLL ANA POWER UP Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK (0x7FU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_SHIFT (0U) /*! MPLL_ANA_PWRUP_TIME_THRESHOLD - Threshold for the MPLL analog power up timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_PWRUP_TIME_THRESH_MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD - Thresholds for MPLL Feedback Clock Enable and MPLL Feedback Digital Clock Disable Timer */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_MASK (0xFU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_SHIFT (0U) /*! MPLL_FBCLK_EN_TIME_THRESHOLD - Threshold for the MPLL feedback clock enable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBCLK_EN_TIME_THRESHOLD_MASK) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK (0xF0U) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_SHIFT (4U) /*! MPLL_FBDIGCLK_DIS_TIME_THRESHOLD - Threshold for the MPLL feedback digital clock disable timer in terms of number of ref_range_clk cycles */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL - MPLL coarse_tune Value */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_SHIFT (0U) /*! MPLL_COARSE_TUNE_VAL - Current value of mpll_ana_coarse_tune_i */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_MPLL_COARSE_TUNE_VAL_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE - Value for MPLL coarse_tune When Skipping Calibration */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_SHIFT (0U) /*! MPLL_SKIPCAL_COARSE_TUNE - Value for MPLL coarse_tune when calibration is skipped */ #define ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_MPLL_SKIPCAL_COARSE_TUNE_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_SSC_SS_PHASE - Current MPLL Phase Selector Value */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_DTHR_MASK (0x3U) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_DTHR_SHIFT (0U) /*! DTHR - Bits below the useful resolution (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_DTHR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_DTHR_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_DTHR_MASK) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_VAL_MASK (0x7FCU) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_VAL_SHIFT (2U) /*! VAL - Phase value from zero reference (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_VAL_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_VAL_MASK) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_ZERO_FREQ_MASK (0x800U) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_ZERO_FREQ_SHIFT (11U) /*! ZERO_FREQ - Zero Frequency Register */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_ZERO_FREQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_ZERO_FREQ_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_ZERO_FREQ_MASK) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_FRACN_CTRL_DIV_MASK (0xF000U) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_FRACN_CTRL_DIV_SHIFT (12U) /*! FRACN_CTRL_DIV - FracN Control Divisor */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_FRACN_CTRL_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_FRACN_CTRL_DIV_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_PHASE_FRACN_CTRL_DIV_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_SSC_SS_FREQ_0 - Frequency Control for Spread Spectrum 0 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_CNT_INIT_SHIFT (0U) /*! FREQ_CNT_INIT - Initial Frequency Counter Value (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_CNT_INIT_MASK) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_0_OVRD_MASK (0x1000U) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_0_OVRD_SHIFT (12U) /*! FREQ_0_OVRD - Frequency Register Override */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_0_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_0_OVRD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_0_FREQ_0_OVRD_MASK) /*! @} */ /*! @name SUP_DIG_MPLLB_SSC_SS_FREQ_1 - Frequency Control for Spread Spectrum 1 */ /*! @{ */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_PEAK_MASK (0xFFU) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_PEAK_SHIFT (0U) /*! FREQ_PEAK - Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value) */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_PEAK_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_PEAK_MASK) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_1_OVRD_MASK (0x100U) #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_1_OVRD_SHIFT (8U) /*! FREQ_1_OVRD - Frequency Register Override */ #define ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_1_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_1_OVRD_SHIFT)) & ENET_PHY_SUP_DIG_MPLLB_SSC_SS_FREQ_1_FREQ_1_OVRD_MASK) /*! @} */ /*! @name SUP_ANA_MPLLB_LOOP_CTRL - MPLLB_LOOP_CTRL */ /*! @{ */ #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_ovrd_pr_bypass_MASK (0x2U) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_ovrd_pr_bypass_SHIFT (1U) /*! ovrd_pr_bypass - Enable local control of PR bypass signal * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_ovrd_pr_bypass(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_ovrd_pr_bypass_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_ovrd_pr_bypass_MASK) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_mode_old_ssc_MASK (0x4U) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_mode_old_ssc_SHIFT (2U) /*! mode_old_ssc - Switch back to 2-bit ssc * 0b0..No switch * 0b1..Switch back */ #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_mode_old_ssc(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_mode_old_ssc_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_mode_old_ssc_MASK) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pr_bypass_MASK (0x8U) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pr_bypass_SHIFT (3U) /*! pr_bypass - Set local pr bypass control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pr_bypass(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pr_bypass_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pr_bypass_MASK) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_meas_iv_23_MASK (0x10U) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_meas_iv_23_SHIFT (4U) /*! meas_iv_23 - VCO control buffer bypass (active high) */ #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_meas_iv_23(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_meas_iv_23_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_meas_iv_23_MASK) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_lpn_vreg_MASK (0x20U) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_lpn_vreg_SHIFT (5U) /*! lpn_vreg - vreg_vco draws power from vph instead of vp when asserted */ #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_lpn_vreg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_lpn_vreg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_lpn_vreg_MASK) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pfd_pw_ctrl_MASK (0xC0U) #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pfd_pw_ctrl_SHIFT (6U) /*! pfd_pw_ctrl - PFD Reset Pulse Width Control * 0b11..Maximum pulse width * 0b00..Minimum pulse width */ #define ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pfd_pw_ctrl(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pfd_pw_ctrl_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_LOOP_CTRL_pfd_pw_ctrl_MASK) /*! @} */ /*! @name SUP_ANA_MPLLB_OVRD - MPLLB_OVRD */ /*! @{ */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_enable_MASK (0x1U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_enable_SHIFT (0U) /*! ovrd_enable - Enable local control of enable signal (mpll_en) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_enable(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_enable_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_enable_MASK) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_enable_reg_MASK (0x2U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_enable_reg_SHIFT (1U) /*! enable_reg - Set local enable control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_enable_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_enable_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_enable_reg_MASK) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_cal_MASK (0x4U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_cal_SHIFT (2U) /*! ovrd_cal - Enable local control of calibration signal (mpll_cal) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_cal(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_cal_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_cal_MASK) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_cal_reg_MASK (0x8U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_cal_reg_SHIFT (3U) /*! cal_reg - Set local calibration control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_cal_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_cal_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_cal_reg_MASK) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_fb_clk_en_MASK (0x10U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_fb_clk_en_SHIFT (4U) /*! ovrd_fb_clk_en - Enable local control of feedback clock control signal (mpll_fb_clk_en) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_fb_clk_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_fb_clk_en_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_fb_clk_en_MASK) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_fb_clk_en_reg_MASK (0x20U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_fb_clk_en_reg_SHIFT (5U) /*! fb_clk_en_reg - Set local feedback clock control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_fb_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_fb_clk_en_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_fb_clk_en_reg_MASK) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_reset_MASK (0x40U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_reset_SHIFT (6U) /*! ovrd_reset - Enable local control of reset signal (mpll_rst) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_reset(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_reset_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_ovrd_reset_MASK) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_reset_reg_MASK (0x80U) #define ENET_PHY_SUP_ANA_MPLLB_OVRD_reset_reg_SHIFT (7U) /*! reset_reg - Set local reset control to ON * 0b0..Not set * 0b1..Set to ON */ #define ENET_PHY_SUP_ANA_MPLLB_OVRD_reset_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_ANA_MPLLB_OVRD_reset_reg_SHIFT)) & ENET_PHY_SUP_ANA_MPLLB_OVRD_reset_reg_MASK) /*! @} */ /*! @name SUP_DIG_ANA_MPLLB_OVRD_OUT - Override Value for MPLLB Signals Going to ANA */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_ANA_EN_MASK (0x1U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_ANA_EN_SHIFT (0U) /*! MPLLB_ANA_EN - Overrides the mpllb_ana_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_ANA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_ANA_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_ANA_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_RST_MASK (0x2U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_RST_SHIFT (1U) /*! MPLLB_RST - Overrides the mpllb_ana_rst signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_RST_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_RST_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_CAL_MASK (0x4U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_CAL_SHIFT (2U) /*! MPLLB_CAL - Overrides the mpllb_ana_cal signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_CAL_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_CAL_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_EN_MASK (0x8U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_EN_SHIFT (3U) /*! MPLLB_OUTPUT_EN - Overrides the mpllb_ana_output_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_L_EN_MASK (0x10U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_L_EN_SHIFT (4U) /*! MPLLB_OUTPUT_L_EN - Overrides the mpllb_ana_output_l_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_L_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_L_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_L_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_R_EN_MASK (0x20U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_R_EN_SHIFT (5U) /*! MPLLB_OUTPUT_R_EN - Overrides the mpllb_ana_output_r_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_R_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_R_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_OUTPUT_R_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV8_CLK_EN_MASK (0x40U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV8_CLK_EN_SHIFT (6U) /*! MPLLB_DIV8_CLK_EN - Overrides the mpllb_ana_div8_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV8_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV8_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV10_CLK_EN_MASK (0x80U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV10_CLK_EN_SHIFT (7U) /*! MPLLB_DIV10_CLK_EN - Overrides the mpllb_ana_div10_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV10_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV10_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_FBCLK_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_FBCLK_EN_SHIFT (8U) /*! MPLLB_FBCLK_EN - Overrides the mpllb_fb_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_FBCLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_FBCLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_FBCLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV_CLK_EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV_CLK_EN_SHIFT (9U) /*! MPLLB_DIV_CLK_EN - Overrides the mpllb_ana_div_clk_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV_CLK_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_MPLLB_DIV_CLK_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_OVRD_SEL_MASK (0x400U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_OVRD_SEL_SHIFT (10U) /*! OVRD_SEL - Override bit for mpllb_ana outputs * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_OVRD_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_OVRD_SEL_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_OVRD_OUT_OVRD_SEL_MASK) /*! @} */ /*! @name SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT - Override Value for MPLLB PMIX Signals Going to ANA */ /*! @{ */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_MASK (0xFFU) #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_SHIFT (0U) /*! MPLLB_PMIX_SEL - Overrides the mpllb_ana_pmix_sel signal */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_OVRD_EN_MASK (0x100U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_OVRD_EN_SHIFT (8U) /*! MPLLB_PMIX_SEL_OVRD_EN - Override bit for mplla_ana_pmix_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_SEL_OVRD_EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX__EN_MASK (0x200U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX__EN_SHIFT (9U) /*! MPLLB_PMIX__EN - Override bit for mpllb_ana_pmix_en signal * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX__EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX__EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX__EN_MASK) #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_OVRD_EN_MASK (0x400U) #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_OVRD_EN_SHIFT (10U) /*! MPLLB_PMIX_OVRD_EN - Override bit for mpllb_ana_pmix_sel/en signals * 0b0..No override * 0b1..Override */ #define ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_OVRD_EN_SHIFT)) & ENET_PHY_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT_MPLLB_PMIX_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLB_BW_OVRD_IN - Override Values for Incoming MPLLB Bandwidth */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLB_BW_OVRD_IN_MPLLB_BW_OVRD_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWCMN_DIG_MPLLB_BW_OVRD_IN_MPLLB_BW_OVRD_VAL_SHIFT (0U) /*! MPLLB_BW_OVRD_VAL - Override Value for mpllb_bandwidth[15:0] */ #define ENET_PHY_RAWCMN_DIG_MPLLB_BW_OVRD_IN_MPLLB_BW_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_BW_OVRD_IN_MPLLB_BW_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_BW_OVRD_IN_MPLLB_BW_OVRD_VAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN - Override Values for Incoming MPLLB SSC Control Settings */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_FRACN_CTRL_MASK (0x7FFU) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_FRACN_CTRL_SHIFT (0U) /*! MPLLB_FRACN_CTRL - Override Value for mpllb_fracn_ctrl[10:0] */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_FRACN_CTRL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_FRACN_CTRL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_UP_SPREAD_MASK (0x800U) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_UP_SPREAD_SHIFT (11U) /*! MPLLB_SSC_UP_SPREAD - Override Value for mpllb_ssc_up_spread * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_UP_SPREAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_UP_SPREAD_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_UP_SPREAD_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CLK_SEL_MASK (0x1000U) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CLK_SEL_SHIFT (12U) /*! MPLLB_SSC_CLK_SEL - Override Value for mpllb_ssc_clk_sel * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CLK_SEL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CLK_SEL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CTL_OVRD_EN_MASK (0x2000U) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CTL_OVRD_EN_SHIFT (13U) /*! MPLLB_SSC_CTL_OVRD_EN - Override Value for MPLLB SSC control settings * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CTL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CTL_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_MPLLB_SSC_CTL_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN - Override Values for Incoming MPLLB SSC Input Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_MASK (0xFFFU) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_SHIFT (0U) /*! MPLLB_SSC_FREQ_CNT_INIT - Override Value for mpllb_ssc_freq_cnt_init */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_EN_MASK (0x1000U) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_EN_SHIFT (12U) /*! MPLLB_SSC_FREQ_CNT_INIT_EN - Override Value for mpllb_ssc_freq_cnt_init * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_FREQ_CNT_INIT_EN_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_VAL_MASK (0x2000U) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_VAL_SHIFT (13U) /*! MPLLB_SSC_EN_OVRD_VAL - Override Value for MPLLB SSC enable * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_EN_MASK (0x4000U) #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_EN_SHIFT (14U) /*! MPLLB_SSC_EN_OVRD_EN - Override Enable for MPLLB SSC Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_MPLLB_SSC_EN_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_MPLLB_MISC_OVRD_IN - Override Values for Incoming MPLLB-Related Input Signals */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_SHIFT (0U) /*! MPLLB_SSC_FREQ_CNT_PEAK - Override Value for mpllb_ssc_freq_cnt_peak[7:0] */ #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_EN_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_EN_SHIFT (8U) /*! MPLLB_SSC_FREQ_CNT_PEAK_EN - Override Value for mpllb_ssc_freq_cnt_peak * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_SSC_FREQ_CNT_PEAK_EN_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_TX_CLK_DIV_OVRD_VAL_MASK (0x600U) #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_TX_CLK_DIV_OVRD_VAL_SHIFT (9U) /*! MPLLB_TX_CLK_DIV_OVRD_VAL - Override Value for mpllb_tx_clk_div */ #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_TX_CLK_DIV_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_TX_CLK_DIV_OVRD_VAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_TX_CLK_DIV_OVRD_VAL_MASK) #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_OVRD_EN_MASK (0x800U) #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_OVRD_EN_SHIFT (11U) /*! MPLLB_OVRD_EN - Override Enable for mpllb_bandwidth and mpllb_tx_clk_div * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_OVRD_EN_SHIFT)) & ENET_PHY_RAWCMN_DIG_MPLLB_MISC_OVRD_IN_MPLLB_OVRD_EN_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0 - MPLLB Coarse Tune Value for Bank 0 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_BANK_0_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_BANK_0_SHIFT (0U) /*! MPLLB_COARSE_TUNE_BANK_0 - Stored bank0 coarse tune value for MPLLB */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_BANK_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_BANK_0_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_BANK_0_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_DONE_BANK_0_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_DONE_BANK_0_SHIFT (8U) /*! MPLLB_COARSE_TUNE_DONE_BANK_0 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_DONE_BANK_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_DONE_BANK_0_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_0_MPLLB_COARSE_TUNE_DONE_BANK_0_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1 - MPLLB Coarse Tune Value for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_BANK_1_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_BANK_1_SHIFT (0U) /*! MPLLB_COARSE_TUNE_BANK_1 - Stored bank 1 coarse tune value for MPLLB */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_BANK_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_BANK_1_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_BANK_1_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_DONE_BANK_1_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_DONE_BANK_1_SHIFT (8U) /*! MPLLB_COARSE_TUNE_DONE_BANK_1 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_DONE_BANK_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_DONE_BANK_1_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_1_MPLLB_COARSE_TUNE_DONE_BANK_1_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2 - MPLLB Coarse Tune Value for Bank 2 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_BANK_2_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_BANK_2_SHIFT (0U) /*! MPLLB_COARSE_TUNE_BANK_2 - Stored bank 2 coarse tune value for MPLLB */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_BANK_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_BANK_2_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_BANK_2_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_DONE_BANK_2_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_DONE_BANK_2_SHIFT (8U) /*! MPLLB_COARSE_TUNE_DONE_BANK_2 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_DONE_BANK_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_DONE_BANK_2_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_2_MPLLB_COARSE_TUNE_DONE_BANK_2_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3 - MPLLB Coarse Tune Value for Bank 3 */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_BANK_3_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_BANK_3_SHIFT (0U) /*! MPLLB_COARSE_TUNE_BANK_3 - Stored bank 3 coarse tune value for MPLLB */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_BANK_3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_BANK_3_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_BANK_3_MASK) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_DONE_BANK_3_MASK (0x100U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_DONE_BANK_3_SHIFT (8U) /*! MPLLB_COARSE_TUNE_DONE_BANK_3 - Indicates if the coarse tune value is calibrated value * 0b0..Not calibrated * 0b1..Calibrated */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_DONE_BANK_3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_DONE_BANK_3_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_BANK_3_MPLLB_COARSE_TUNE_DONE_BANK_3_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL - Value for MPLLB Bank Select */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL_MPLLB_CAL_BANK_SEL_MASK (0x3U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL_MPLLB_CAL_BANK_SEL_SHIFT (0U) /*! MPLLB_CAL_BANK_SEL - Value for MPLL B Bank Select */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL_MPLLB_CAL_BANK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL_MPLLB_CAL_BANK_SEL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL_MPLLB_CAL_BANK_SEL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_DONE - Valid Calibrated Value for MPLLB Calibration Bank */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_DONE_MPLLB_COARSE_TUNE_DONE_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_DONE_MPLLB_COARSE_TUNE_DONE_SHIFT (0U) /*! MPLLB_COARSE_TUNE_DONE - Indicates if the selected MPLLB calibration bank has the valid calibrated value * 0b0..Invalid * 0b1..Valid */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_DONE_MPLLB_COARSE_TUNE_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_DONE_MPLLB_COARSE_TUNE_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_DONE_MPLLB_COARSE_TUNE_DONE_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_COARSE_TUNE - Selected COARSE TUNE Value for MPLLB */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_MPLLB_COARSE_TUNE_MASK (0xFFU) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_MPLLB_COARSE_TUNE_SHIFT (0U) /*! MPLLB_COARSE_TUNE - Selected coarse tune value for MPLLB */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_MPLLB_COARSE_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_MPLLB_COARSE_TUNE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_COARSE_TUNE_MPLLB_COARSE_TUNE_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_IN_RECAL - MPLLB Re-Calibration */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_IN_RECAL_MPLLB_IN_RECAL_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_IN_RECAL_MPLLB_IN_RECAL_SHIFT (0U) /*! MPLLB_IN_RECAL - Indicates if MPLLB is in re-calibration * 0b0..Not in re-calibration * 0b1..In re-calibration */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_IN_RECAL_MPLLB_IN_RECAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_IN_RECAL_MPLLB_IN_RECAL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_IN_RECAL_MPLLB_IN_RECAL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL - Current Bank Selected for MPLLB Coarse Tune in PMA */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL_PMA_MPLLB_RECAL_BANK_SEL_MASK (0x3U) #define ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL_PMA_MPLLB_RECAL_BANK_SEL_SHIFT (0U) /*! PMA_MPLLB_RECAL_BANK_SEL - Current bank selected for MPLLB coarse tune in PMA */ #define ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL_PMA_MPLLB_RECAL_BANK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL_PMA_MPLLB_RECAL_BANK_SEL_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL_PMA_MPLLB_RECAL_BANK_SEL_MASK) /*! @} */ /*! @name RAWCMN_DIG_AON_MPLLB_BANK_SEL_DONE - Status for MPLLB Re-Calibration or Switching */ /*! @{ */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_BANK_SEL_DONE_DONE_MASK (0x1U) #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_BANK_SEL_DONE_DONE_SHIFT (0U) /*! DONE - Status for MPLLB re-calibration or switching */ #define ENET_PHY_RAWCMN_DIG_AON_MPLLB_BANK_SEL_DONE_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWCMN_DIG_AON_MPLLB_BANK_SEL_DONE_DONE_SHIFT)) & ENET_PHY_RAWCMN_DIG_AON_MPLLB_BANK_SEL_DONE_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_LANE_OVRD_IN - Override Values for Incoming LANE Controls from ASIC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_TX2RX_SER_LB_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_TX2RX_SER_LB_SHIFT (0U) /*! LANE_TX2RX_SER_LB - Override Value for lane_tx2rx_ser_lb_en_r * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_TX2RX_SER_LB(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_TX2RX_SER_LB_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_TX2RX_SER_LB_MASK) #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_RX2TX_PAR_LB_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_RX2TX_PAR_LB_SHIFT (1U) /*! LANE_RX2TX_PAR_LB - Override Value for lane_rx2tx_par_lb_en_r * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_RX2TX_PAR_LB(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_RX2TX_PAR_LB_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_LANE_RX2TX_PAR_LB_MASK) #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_EN_SHIFT (2U) /*! EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_LANE_OVRD_IN_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_OVRD_IN_0 - Override Values for Incoming TX Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_CLK_RDY_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_CLK_RDY_SHIFT (0U) /*! CLK_RDY - Override Value for tx_clk_rdy * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_CLK_RDY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_CLK_RDY_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_CLK_RDY_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RESET_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RESET_SHIFT (1U) /*! RESET - Override Value for tx_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RESET_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_INVERT_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_INVERT_SHIFT (2U) /*! INVERT - Override Value for tx_invert * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_INVERT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_INVERT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_INVERT_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DATA_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DATA_EN_SHIFT (3U) /*! DATA_EN - Override Value for tx_data_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_REQ_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_REQ_SHIFT (4U) /*! REQ - Override Value for tx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_REQ_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_REQ_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_LPD_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_LPD_SHIFT (5U) /*! LPD - Override Value for tx_lpd * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_LPD_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_LPD_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_PSTATE_MASK (0xC0U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_PSTATE_SHIFT (6U) /*! PSTATE - Override Value for tx_pstate[1:0] */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_PSTATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_PSTATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RATE_MASK (0x700U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RATE_SHIFT (8U) /*! RATE - Override Value for tx_rate[2:0] */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_RATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_WIDTH_MASK (0x1800U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_WIDTH_SHIFT (11U) /*! WIDTH - Override Value for tx_width[1:0] */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_WIDTH_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_WIDTH_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_MPLLB_SEL_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_MPLLB_SEL_SHIFT (13U) /*! MPLLB_SEL - Override Value for tx_mpllb_sel * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_MPLLB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_MPLLB_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_MPLLB_SEL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DETECT_RX_REQ_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DETECT_RX_REQ_SHIFT (14U) /*! DETECT_RX_REQ - Override Value for tx_detrx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DETECT_RX_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DETECT_RX_REQ_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_DETECT_RX_REQ_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_EN_SHIFT (15U) /*! EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_0_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_OVRD_IN_1 - Override Values for Incoming TX Drive Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_NYQUIST_DATA_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_NYQUIST_DATA_SHIFT (0U) /*! NYQUIST_DATA - Override incoming data to nyquist * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_NYQUIST_DATA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_NYQUIST_DATA_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_NYQUIST_DATA_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_DISABLE_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_DISABLE_SHIFT (1U) /*! DISABLE - Override Value for tx_disable * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_DISABLE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_DISABLE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_BEACON_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_BEACON_EN_SHIFT (2U) /*! BEACON_EN - Override Value for tx_beacon_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_BEACON_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_BEACON_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_BEACON_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_IBOOST_LVL_MASK (0x78U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_IBOOST_LVL_SHIFT (3U) /*! IBOOST_LVL - Override Value for tx_iboost_lvl */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_IBOOST_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_IBOOST_LVL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_IBOOST_LVL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_VBOOST_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_VBOOST_EN_SHIFT (7U) /*! VBOOST_EN - Override Value for tx_vboost_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_VBOOST_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_VBOOST_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_VBOOST_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_EN_SHIFT (8U) /*! EN - Enable override values for inputs below controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_TX_MAIN_CURSOR_MASK (0x7E00U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_TX_MAIN_CURSOR_SHIFT (9U) /*! TX_MAIN_CURSOR - Override Value for tx_eq_main */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_TX_MAIN_CURSOR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_TX_MAIN_CURSOR_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_TX_MAIN_CURSOR_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_MAIN_OVRD_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_MAIN_OVRD_EN_SHIFT (15U) /*! MAIN_OVRD_EN - Enable override values for TX EQ main input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_MAIN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_MAIN_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_1_MAIN_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_OVRD_IN_2 - Override Values for Incoming TX Drive Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_PRE_CURSOR_MASK (0x3FU) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_PRE_CURSOR_SHIFT (0U) /*! TX_PRE_CURSOR - Override Value for tx_eq_pre */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_PRE_CURSOR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_PRE_CURSOR_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_PRE_CURSOR_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_PRE_OVRD_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_PRE_OVRD_EN_SHIFT (6U) /*! PRE_OVRD_EN - Enable override values for TX EQ pre input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_PRE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_PRE_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_PRE_OVRD_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_POST_CURSOR_MASK (0x1F80U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_POST_CURSOR_SHIFT (7U) /*! TX_POST_CURSOR - Override Value for tx_eq_post */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_POST_CURSOR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_POST_CURSOR_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_TX_POST_CURSOR_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_POST_OVRD_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_POST_OVRD_EN_SHIFT (13U) /*! POST_OVRD_EN - Enable override values for TX EQ post input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_POST_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_POST_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_IN_2_POST_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_OVRD_OUT - Override Values for Outgoing TX Controls to ASIC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_TX_ACK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_TX_ACK_SHIFT (0U) /*! TX_ACK - Override Value for tx_ack * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_TX_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_TX_ACK_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_TX_ACK_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_TX_ACK_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_TX_ACK_SHIFT (1U) /*! EN_TX_ACK - Enable for override value for tx_ack * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_TX_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_TX_ACK_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_TX_ACK_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_DETRX_RESULT_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_DETRX_RESULT_SHIFT (2U) /*! DETRX_RESULT - Override Value for tx_detrx_result * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_DETRX_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_DETRX_RESULT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_DETRX_RESULT_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_DETRX_RESULT_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_DETRX_RESULT_SHIFT (3U) /*! EN_DETRX_RESULT - Enable for override value for tx_detrx_result * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_DETRX_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_DETRX_RESULT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_OUT_EN_DETRX_RESULT_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_IN_0 - Override Values for Incoming RX Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RESET_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RESET_SHIFT (0U) /*! RESET - Override Value for rx_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RESET_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_INVERT_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_INVERT_SHIFT (1U) /*! INVERT - Override Value for rx_invert * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_INVERT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_INVERT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_INVERT_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DATA_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DATA_EN_SHIFT (2U) /*! DATA_EN - Override Value for rx_data_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_REQ_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_REQ_SHIFT (3U) /*! REQ - Override Value for rx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_REQ_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_REQ_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_LPD_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_LPD_SHIFT (4U) /*! LPD - Override Value for rx_lpd * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_LPD_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_LPD_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_PSTATE_MASK (0x60U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_PSTATE_SHIFT (5U) /*! PSTATE - Override Value for rx_pstate */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_PSTATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_PSTATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RATE_MASK (0x180U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RATE_SHIFT (7U) /*! RATE - Override Value for rx_rate */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_WIDTH_MASK (0x600U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_WIDTH_SHIFT (9U) /*! WIDTH - Override Value for rx_width */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_WIDTH_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_WIDTH_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DIV16P5_CLK_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DIV16P5_CLK_EN_SHIFT (11U) /*! DIV16P5_CLK_EN - Override Value for rx_div16p5_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_DIV16P5_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RX_DFE_BYPASS_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RX_DFE_BYPASS_SHIFT (12U) /*! RX_DFE_BYPASS - Override Value for rx_dfe_bypass * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RX_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RX_DFE_BYPASS_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_RX_DFE_BYPASS_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_EN_SHIFT (13U) /*! EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_0_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_IN_1 - Override Values for Incoming RX Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_REF_LD_VAL_MASK (0x7FU) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_REF_LD_VAL_SHIFT (0U) /*! RX_REF_LD_VAL - Override Value for rx_ref_ld_val[6:0] */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_REF_LD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_REF_LD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_REF_LD_VAL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_FREQBAND_1_0_MASK (0x180U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_FREQBAND_1_0_SHIFT (7U) /*! RX_CDR_VCO_FREQBAND_1_0 - Override Value for rx_cdr_vco_freqband */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_FREQBAND_1_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_FREQBAND_1_0_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_FREQBAND_1_0_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_EN_MASK (0x200U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_EN_SHIFT (9U) /*! EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_TEMP_COMP_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_TEMP_COMP_EN_SHIFT (10U) /*! RX_CDR_VCO_TEMP_COMP_EN - Override Value for rx_cdr_vco_temp_comp_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_TEMP_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_TEMP_COMP_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_TEMP_COMP_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_STEP_CTRL_MASK (0x800U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_STEP_CTRL_SHIFT (11U) /*! RX_CDR_VCO_STEP_CTRL - Override Value for rx_cdr_vco_step_ctrl * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_STEP_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_STEP_CTRL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_1_RX_CDR_VCO_STEP_CTRL_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_IN_2 - Override Values for Incoming RX Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_RX_VCO_LD_VAL_MASK (0x1FFFU) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_RX_VCO_LD_VAL_SHIFT (0U) /*! RX_VCO_LD_VAL - Override Value for rx_vco_ld_val */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_RX_VCO_LD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_RX_VCO_LD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_RX_VCO_LD_VAL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_EN_SHIFT (13U) /*! EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_2_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_IN_3 - Override Values for Incoming RX Controls from ASIC 3 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_TRACK_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_TRACK_EN_SHIFT (0U) /*! CDR_TRACK_EN - Override Value for rx_cdr_track_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_TRACK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_TRACK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_TRACK_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_SSC_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_SSC_EN_SHIFT (1U) /*! CDR_SSC_EN - Override Value for rx_cdr_ssc_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_SSC_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CDR_SSC_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_ALIGN_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_ALIGN_EN_SHIFT (2U) /*! ALIGN_EN - Override Value for rx_align_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_ALIGN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_ALIGN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_ALIGN_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CLK_SHIFT_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CLK_SHIFT_SHIFT (3U) /*! CLK_SHIFT - Override Value for rx_clk_shift * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CLK_SHIFT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CLK_SHIFT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_CLK_SHIFT_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_DISABLE_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_DISABLE_SHIFT (4U) /*! DISABLE - Override Value for rx_disable * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_DISABLE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_DISABLE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_THRSHLD_MASK (0xE0U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_THRSHLD_SHIFT (5U) /*! LOS_THRSHLD - Override Value for rx_los_threshold */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_THRSHLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_THRSHLD_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_THRSHLD_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_LPFS_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_LPFS_EN_SHIFT (8U) /*! LOS_LPFS_EN - Override Value for rx_los_lfps_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_LPFS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_LPFS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_LOS_LPFS_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_EN_MASK (0x200U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_EN_SHIFT (9U) /*! TERM_EN - Override Value for rx_term_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_ACDC_MASK (0x400U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_ACDC_SHIFT (10U) /*! TERM_ACDC - Override Value for rx_term_acdc * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_ACDC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_ACDC_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_TERM_ACDC_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_EN_SHIFT (11U) /*! EN - Enable override values for all inputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_IN_3_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0 - Override Values for Incoming RX EQ Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_ATT_LVL_MASK (0x7U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_ATT_LVL_SHIFT (0U) /*! EQ_ATT_LVL - Override Value for rx_eq_att_lvl */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_ATT_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_ATT_LVL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_ATT_LVL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA1_GAIN_MASK (0x38U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA1_GAIN_SHIFT (3U) /*! EQ_VGA1_GAIN - Override Value for rx_eq_vga1_gain */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA1_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA1_GAIN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA1_GAIN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA2_GAIN_MASK (0x1C0U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA2_GAIN_SHIFT (6U) /*! EQ_VGA2_GAIN - Override Value for rx_eq_vga2_gain */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA2_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA2_GAIN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_VGA2_GAIN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_CTLE_BOOST_MASK (0x3E00U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_CTLE_BOOST_SHIFT (9U) /*! EQ_CTLE_BOOST - Override Value for rx_eq_ctle_boost */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_CTLE_BOOST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_CTLE_BOOST_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_EQ_CTLE_BOOST_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1 - Override Values for Incoming RX EQ Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_CTLE_POLE_MASK (0x3U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_CTLE_POLE_SHIFT (0U) /*! EQ_CTLE_POLE - Override Value for rx_eq_ctle_pole */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_CTLE_POLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_CTLE_POLE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_CTLE_POLE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_DFE_TAP1_MASK (0x3FCU) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_DFE_TAP1_SHIFT (2U) /*! EQ_DFE_TAP1 - Override Value for rx_eq_dfe_tap1 */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_DFE_TAP1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_DFE_TAP1_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_DFE_TAP1_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_OVRD_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_OVRD_EN_SHIFT (10U) /*! EQ_OVRD_EN - Enable override value for rx_eq_* inputs * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_EQ_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_OUT_0 - Override Values for Outgoing RX controls to ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ACK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ACK_SHIFT (0U) /*! ACK - Override Value for rx_ack * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ACK_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ACK_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_LOS_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_LOS_SHIFT (1U) /*! LOS - Override Value for rx_los * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_LOS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_LOS_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_LOS_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ADAPT_STS_MASK (0xCU) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ADAPT_STS_SHIFT (2U) /*! ADAPT_STS - Override Value for rx_adapt_sts */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ADAPT_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ADAPT_STS_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_ADAPT_STS_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_EN_CTL_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_EN_CTL_SHIFT (4U) /*! EN_CTL - Enable override values for all control outputs of this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_EN_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_EN_CTL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_OUT_0_EN_CTL_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_LANE_ASIC_IN - Current Values for Incoming LANE Controls from ASIC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_TX2RX_SER_LB_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_TX2RX_SER_LB_SHIFT (0U) /*! LANE_TX2RX_SER_LB - Value from ASIC for lane_tx2rx_ser_lb_en_r */ #define ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_TX2RX_SER_LB(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_TX2RX_SER_LB_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_TX2RX_SER_LB_MASK) #define ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_RX2TX_PAR_LB_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_RX2TX_PAR_LB_SHIFT (1U) /*! LANE_RX2TX_PAR_LB - Value from ASIC for lane_rx2tx_par_lb_en_r */ #define ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_RX2TX_PAR_LB(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_RX2TX_PAR_LB_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_LANE_ASIC_IN_LANE_RX2TX_PAR_LB_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_ASIC_IN_0 - Current Values for Incoming TX Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_CLK_RDY_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_CLK_RDY_SHIFT (0U) /*! CLK_RDY - Value from ASIC for tx_clk_rdy */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_CLK_RDY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_CLK_RDY_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_CLK_RDY_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RESET_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RESET_SHIFT (1U) /*! RESET - Value from ASIC for tx_reset */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RESET_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_INVERT_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_INVERT_SHIFT (2U) /*! INVERT - Value from ASIC for tx_invert */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_INVERT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_INVERT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_INVERT_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DATA_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DATA_EN_SHIFT (3U) /*! DATA_EN - Value from ASIC for tx_data_en */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_REQ_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_REQ_SHIFT (4U) /*! REQ - Value from ASIC for tx_req */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_REQ_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_REQ_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_LPD_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_LPD_SHIFT (5U) /*! LPD - Value from ASIC for tx_lpd */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_LPD_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_LPD_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_PSTATE_MASK (0xC0U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_PSTATE_SHIFT (6U) /*! PSTATE - Value from ASIC for tx_pstate[1:0] */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_PSTATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_PSTATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RATE_MASK (0x700U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RATE_SHIFT (8U) /*! RATE - Value from ASIC for tx_rate[2:0] */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_RATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_WIDTH_MASK (0x1800U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_WIDTH_SHIFT (11U) /*! WIDTH - Value from ASIC for tx_width[1:0] */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_WIDTH_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_WIDTH_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_MPLLB_SEL_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_MPLLB_SEL_SHIFT (13U) /*! MPLLB_SEL - Value from ASIC for tx_mpllb_sel */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_MPLLB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_MPLLB_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_MPLLB_SEL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DETECT_RX_REQ_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DETECT_RX_REQ_SHIFT (14U) /*! DETECT_RX_REQ - Value from ASIC for tx_detrx_req */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DETECT_RX_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DETECT_RX_REQ_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DETECT_RX_REQ_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DISABLE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DISABLE_SHIFT (15U) /*! DISABLE - Value from ASIC for tx_disable */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DISABLE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_0_DISABLE_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_ASIC_IN_1 - Current Values for Incoming TX Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_BEACON_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_BEACON_EN_SHIFT (0U) /*! BEACON_EN - Value from ASIC for tx_beacon_en */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_BEACON_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_BEACON_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_BEACON_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_IBOOST_LVL_MASK (0x1EU) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_IBOOST_LVL_SHIFT (1U) /*! IBOOST_LVL - Value from ASIC for tx_iboost_lvl */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_IBOOST_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_IBOOST_LVL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_IBOOST_LVL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_VBOOST_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_VBOOST_EN_SHIFT (5U) /*! VBOOST_EN - Value from ASIC for tx_vboost_en */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_VBOOST_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_VBOOST_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_VBOOST_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_TX_MAIN_CURSOR_MASK (0xFC0U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_TX_MAIN_CURSOR_SHIFT (6U) /*! TX_MAIN_CURSOR - Value from ASIC for tx_eq_main */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_TX_MAIN_CURSOR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_TX_MAIN_CURSOR_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_1_TX_MAIN_CURSOR_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_ASIC_IN_2 - Current Values for Incoming TX Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_PRE_CURSOR_MASK (0x3FU) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_PRE_CURSOR_SHIFT (0U) /*! TX_PRE_CURSOR - Value from ASIC for tx_eq_pre */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_PRE_CURSOR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_PRE_CURSOR_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_PRE_CURSOR_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_POST_CURSOR_MASK (0xFC0U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_POST_CURSOR_SHIFT (6U) /*! TX_POST_CURSOR - Value from ASIC for tx_eq_post */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_POST_CURSOR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_POST_CURSOR_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_IN_2_TX_POST_CURSOR_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_ASIC_OUT - Current Values for Outgoing TX Status Controls from PHY */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_TX_ACK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_TX_ACK_SHIFT (0U) /*! TX_ACK - Value from PHY for tx_ack */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_TX_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_TX_ACK_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_TX_ACK_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_DETRX_RESULT_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_DETRX_RESULT_SHIFT (1U) /*! DETRX_RESULT - Value from PHY for tx_detrx_result */ #define ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_DETRX_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_DETRX_RESULT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_ASIC_OUT_DETRX_RESULT_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_ASIC_IN_0 - Current Values for Incoming RX Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RESET_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RESET_SHIFT (0U) /*! RESET - Value from ASIC for rx_reset */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RESET_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_INVERT_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_INVERT_SHIFT (1U) /*! INVERT - Value from ASIC for rx_invert */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_INVERT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_INVERT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_INVERT_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DATA_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DATA_EN_SHIFT (2U) /*! DATA_EN - Value from ASIC for rx_data_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_REQ_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_REQ_SHIFT (3U) /*! REQ - Value from ASIC for rx_req */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_REQ_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_REQ_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_LPD_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_LPD_SHIFT (4U) /*! LPD - Value from ASIC for rx_lpd */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_LPD_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_LPD_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_PSTATE_MASK (0x60U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_PSTATE_SHIFT (5U) /*! PSTATE - Value from ASIC for rx_pstate */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_PSTATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_PSTATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RATE_MASK (0x180U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RATE_SHIFT (7U) /*! RATE - Value from ASIC for rx_rate */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RATE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RATE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_WIDTH_MASK (0x600U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_WIDTH_SHIFT (9U) /*! WIDTH - Value from ASIC for rx_width */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_WIDTH_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_WIDTH_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DIV16P5_CLK_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DIV16P5_CLK_EN_SHIFT (11U) /*! DIV16P5_CLK_EN - Value from ASIC for rx_div16p5_clk_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_DIV16P5_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RX_DFE_BYPASS_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RX_DFE_BYPASS_SHIFT (12U) /*! RX_DFE_BYPASS - Value from ASIC for rx_dfe_bypass */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RX_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RX_DFE_BYPASS_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_RX_DFE_BYPASS_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_CDR_TRACK_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_CDR_TRACK_EN_SHIFT (13U) /*! CDR_TRACK_EN - Value from ASIC for rx_cdr_track_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_CDR_TRACK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_CDR_TRACK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_0_CDR_TRACK_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_ASIC_IN_1 - Current Values for Incoming RX Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CDR_SSC_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CDR_SSC_EN_SHIFT (0U) /*! CDR_SSC_EN - Value from ASIC for rx_cdr_ssc_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CDR_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CDR_SSC_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CDR_SSC_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_ALIGN_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_ALIGN_EN_SHIFT (1U) /*! ALIGN_EN - Value from ASIC for rx_align_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_ALIGN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_ALIGN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_ALIGN_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CLK_SHIFT_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CLK_SHIFT_SHIFT (2U) /*! CLK_SHIFT - Value from ASIC for rx_clk_shift */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CLK_SHIFT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CLK_SHIFT_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_CLK_SHIFT_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_DISABLE_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_DISABLE_SHIFT (3U) /*! DISABLE - Value from ASIC for rx_disable */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_DISABLE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_DISABLE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_THRSHLD_MASK (0x70U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_THRSHLD_SHIFT (4U) /*! LOS_THRSHLD - Value from ASIC for rx_los_threshold */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_THRSHLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_THRSHLD_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_THRSHLD_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_LPFS_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_LPFS_EN_SHIFT (7U) /*! LOS_LPFS_EN - Value from ASIC for rx_los_lfps_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_LPFS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_LPFS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_LOS_LPFS_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_EN_SHIFT (8U) /*! RX_TERM_EN - Value from ASIC for rx_term_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_ACDC_MASK (0x200U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_ACDC_SHIFT (9U) /*! RX_TERM_ACDC - Value from ASIC for rx_term_acdc */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_ACDC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_ACDC_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_IN_1_RX_TERM_ACDC_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0 - Current Values for Incoming RX EQ Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_ATT_LVL_MASK (0x7U) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_ATT_LVL_SHIFT (0U) /*! EQ_ATT_LVL - Value from ASIC for rx_eq_att_lvl */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_ATT_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_ATT_LVL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_ATT_LVL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA1_GAIN_MASK (0x38U) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA1_GAIN_SHIFT (3U) /*! EQ_VGA1_GAIN - Value from ASIC for rx_eq_vga1_gain */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA1_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA1_GAIN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA1_GAIN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA2_GAIN_MASK (0x1C0U) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA2_GAIN_SHIFT (6U) /*! EQ_VGA2_GAIN - Value from ASIC for rx_eq_vga2_gain */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA2_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA2_GAIN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_VGA2_GAIN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_CTLE_BOOST_MASK (0x3E00U) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_CTLE_BOOST_SHIFT (9U) /*! EQ_CTLE_BOOST - Value from ASIC for rx_eq_ctle_boost */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_CTLE_BOOST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_CTLE_BOOST_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_EQ_CTLE_BOOST_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1 - Current Values for Incoming RX EQ Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_CTLE_POLE_MASK (0x3U) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_CTLE_POLE_SHIFT (0U) /*! EQ_CTLE_POLE - Value from ASIC for rx_eq_ctle_pole */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_CTLE_POLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_CTLE_POLE_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_CTLE_POLE_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_DFE_TAP1_MASK (0x3FCU) #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_DFE_TAP1_SHIFT (2U) /*! EQ_DFE_TAP1 - Value from ASIC for rx_eq_dfe_tap1 */ #define ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_DFE_TAP1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_DFE_TAP1_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_EQ_DFE_TAP1_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0 - Current Values for Incoming RX CDR VCO Controls from ASIC 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_TEMP_COMP_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_TEMP_COMP_EN_SHIFT (0U) /*! RX_CDR_VCO_TEMP_COMP_EN - Value from ASIC for rx_cdr_vco_temp_comp_en */ #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_TEMP_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_TEMP_COMP_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_TEMP_COMP_EN_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_STEP_CTRL_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_STEP_CTRL_SHIFT (1U) /*! RX_CDR_VCO_STEP_CTRL - Value from ASIC for rx_cdr_vco_step_ctrl */ #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_STEP_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_STEP_CTRL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_STEP_CTRL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_FREQBAND_MASK (0xCU) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_FREQBAND_SHIFT (2U) /*! RX_CDR_VCO_FREQBAND - Value from ASIC for rx_cdr_vco_freqband */ #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_FREQBAND(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_FREQBAND_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_CDR_VCO_FREQBAND_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_REF_LD_VAL_MASK (0x7F0U) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_REF_LD_VAL_SHIFT (4U) /*! RX_REF_LD_VAL - Value from ASIC for rx_ref_ld_val */ #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_REF_LD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_REF_LD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_RX_REF_LD_VAL_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1 - Current Values for Incoming RX CDR VCO Controls from ASIC 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_RX_VCO_LD_VAL_MASK (0x1FFFU) #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_RX_VCO_LD_VAL_SHIFT (0U) /*! RX_VCO_LD_VAL - Value from ASIC for rx_vco_ld_val */ #define ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_RX_VCO_LD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_RX_VCO_LD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_RX_VCO_LD_VAL_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_ASIC_OUT_0 - Current Values for Outgoing RX Status Controls from PHY 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ACK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ACK_SHIFT (0U) /*! ACK - Value from PHY for rx_ack */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ACK_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ACK_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_LOS_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_LOS_SHIFT (1U) /*! LOS - Value from PHY for rx_los */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_LOS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_LOS_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_LOS_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_VALID_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_VALID_SHIFT (2U) /*! VALID - Value from PHY for rx_valid */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_VALID(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_VALID_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_VALID_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ADAPT_STS_MASK (0x18U) #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ADAPT_STS_SHIFT (3U) /*! ADAPT_STS - Value from PHY for rx_adapt_sts */ #define ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ADAPT_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ADAPT_STS_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_ASIC_OUT_0_ADAPT_STS_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2 - Override Values for Incoming RX EQ Controls from ASIC 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP2_MASK (0x7FU) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP2_SHIFT (0U) /*! EQ_DFE_TAP2 - Override Value for rx_eq_dfe_tap2 */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP2_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP2_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP3_MASK (0x3F80U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP3_SHIFT (7U) /*! EQ_DFE_TAP3 - Override Value for rx_eq_dfe_tap3 */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP3_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_EQ_DFE_TAP3_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3 - Override Values for Incoming RX EQ Controls from ASIC 3 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP4_MASK (0x7FU) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP4_SHIFT (0U) /*! EQ_DFE_TAP4 - Override Value for rx_eq_dfe_tap4 */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP4(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP4_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP4_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP5_MASK (0x3F80U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP5_SHIFT (7U) /*! EQ_DFE_TAP5 - Override Value for rx_eq_dfe_tap5 */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP5_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_EQ_DFE_TAP5_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_TX_OVRD_MISC - Override Values for Incoming TX MISC BUS from ASIC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_VAL_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_VAL_SHIFT (0U) /*! TX_MISC_OVRD_VAL - Override Value for tx_misc[7:0] */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_VAL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_EN_SHIFT (8U) /*! TX_MISC_OVRD_EN - Override Enable for tx_misc[7:0] * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_TX_OVRD_MISC_TX_MISC_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ASIC_RX_OVRD_MISC - Override Values for Incoming RX MISC BUS from ASIC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_VAL_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_VAL_SHIFT (0U) /*! RX_MISC_OVRD_VAL - Override Value for rx_misc[7:0] */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_VAL_MASK) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_EN_SHIFT (8U) /*! RX_MISC_OVRD_EN - Override Enable for rx_misc[7:0] * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ASIC_RX_OVRD_MISC_RX_MISC_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0 - TX Power State Control for P0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_REFGEN_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_REFGEN_EN_SHIFT (0U) /*! TX_P0_ANA_REFGEN_EN - Value of TX ANA refgen_en in P0 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_REFGEN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_REFGEN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_REFGEN_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_VCM_HOLD_MASK (0x2U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_VCM_HOLD_SHIFT (1U) /*! TX_P0_ANA_VCM_HOLD - Value of TX ANA vcm_hold in P0 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_VCM_HOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_VCM_HOLD_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_VCM_HOLD_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_CLK_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_CLK_EN_SHIFT (2U) /*! TX_P0_ANA_CLK_EN - Value of TX ANA clk_en in P0 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_WORD_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_WORD_CLK_EN_SHIFT (3U) /*! TX_P0_ANA_WORD_CLK_EN - Value of TX ANA word_clk_en in P0 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_WORD_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_WORD_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_WORD_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_RESET_MASK (0x10U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_RESET_SHIFT (4U) /*! TX_P0_ANA_RESET - Value of TX ANA reset in P0 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_RESET_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_SERIAL_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_SERIAL_EN_SHIFT (5U) /*! TX_P0_ANA_SERIAL_EN - Value of TX ANA serial_en in P0 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_SERIAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_SERIAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ANA_SERIAL_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DIG_CLK_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DIG_CLK_EN_SHIFT (6U) /*! TX_P0_DIG_CLK_EN - Enable/Disable TX digital clocks in P0 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DATA_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DATA_EN_SHIFT (7U) /*! TX_P0_DATA_EN - This is ANDed with top-level tx_data_en asic input */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ALLOW_RXDET_MASK (0x100U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ALLOW_RXDET_SHIFT (8U) /*! TX_P0_ALLOW_RXDET - If asserted, then rxdet request is allowed in P0 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ALLOW_RXDET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_TX_P0_ALLOW_RXDET_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S - TX Power State Control for P0S */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_REFGEN_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_REFGEN_EN_SHIFT (0U) /*! TX_P0S_ANA_REFGEN_EN - Value of TX ANA refgen_en in P0S */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_REFGEN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_REFGEN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_REFGEN_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_VCM_HOLD_MASK (0x2U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_VCM_HOLD_SHIFT (1U) /*! TX_P0S_ANA_VCM_HOLD - Value of TX ANA vcm_hold in P0S */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_VCM_HOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_VCM_HOLD_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_VCM_HOLD_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_CLK_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_CLK_EN_SHIFT (2U) /*! TX_P0S_ANA_CLK_EN - Value of TX ANA clk_en in P0S */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_WORD_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_WORD_CLK_EN_SHIFT (3U) /*! TX_P0S_ANA_WORD_CLK_EN - Value of TX ANA word_clk_en in P0S */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_WORD_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_WORD_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_WORD_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_RESET_MASK (0x10U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_RESET_SHIFT (4U) /*! TX_P0S_ANA_RESET - Value of TX ANA reset in P0S */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_RESET_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_SERIAL_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_SERIAL_EN_SHIFT (5U) /*! TX_P0S_ANA_SERIAL_EN - Value of TX ANA serial_en in P0S */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_SERIAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_SERIAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ANA_SERIAL_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DIG_CLK_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DIG_CLK_EN_SHIFT (6U) /*! TX_P0S_DIG_CLK_EN - Enable/Disable TX digital clocks in P0S * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DATA_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DATA_EN_SHIFT (7U) /*! TX_P0S_DATA_EN - This is ANDed with top-level tx_data_en asic input */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ALLOW_RXDET_MASK (0x100U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ALLOW_RXDET_SHIFT (8U) /*! TX_P0S_ALLOW_RXDET - If asserted, then rxdet request is allowed in P0S */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ALLOW_RXDET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_TX_P0S_ALLOW_RXDET_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1 - TX Power State Control for P1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_REFGEN_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_REFGEN_EN_SHIFT (0U) /*! TX_P1_ANA_REFGEN_EN - Value of TX ANA refgen_en in P1 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_REFGEN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_REFGEN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_REFGEN_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_VCM_HOLD_MASK (0x2U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_VCM_HOLD_SHIFT (1U) /*! TX_P1_ANA_VCM_HOLD - Value of TX ANA vcm_hold in P1 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_VCM_HOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_VCM_HOLD_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_VCM_HOLD_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_CLK_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_CLK_EN_SHIFT (2U) /*! TX_P1_ANA_CLK_EN - Value of TX ANA clk_en in P1 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_WORD_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_WORD_CLK_EN_SHIFT (3U) /*! TX_P1_ANA_WORD_CLK_EN - Value of TX ANA word_clk_en in P1 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_WORD_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_WORD_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_WORD_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_RESET_MASK (0x10U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_RESET_SHIFT (4U) /*! TX_P1_ANA_RESET - Value of TX ANA reset in P1 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_RESET_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_SERIAL_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_SERIAL_EN_SHIFT (5U) /*! TX_P1_ANA_SERIAL_EN - Value of TX ANA serial_en in P1 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_SERIAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_SERIAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ANA_SERIAL_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DIG_CLK_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DIG_CLK_EN_SHIFT (6U) /*! TX_P1_DIG_CLK_EN - Enable/Disable TX digital clocks in P1 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DATA_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DATA_EN_SHIFT (7U) /*! TX_P1_DATA_EN - This is ANDed with top-level tx_data_en asic input */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ALLOW_RXDET_MASK (0x100U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ALLOW_RXDET_SHIFT (8U) /*! TX_P1_ALLOW_RXDET - If asserted, then rxdet request is allowed in P1 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ALLOW_RXDET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_TX_P1_ALLOW_RXDET_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2 - TX Power State Control for P2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_REFGEN_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_REFGEN_EN_SHIFT (0U) /*! TX_P2_ANA_REFGEN_EN - Value of TX ANA refgen_en in P2 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_REFGEN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_REFGEN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_REFGEN_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_VCM_HOLD_MASK (0x2U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_VCM_HOLD_SHIFT (1U) /*! TX_P2_ANA_VCM_HOLD - Value of TX ANA vcm_hold in P2 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_VCM_HOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_VCM_HOLD_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_VCM_HOLD_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_CLK_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_CLK_EN_SHIFT (2U) /*! TX_P2_ANA_CLK_EN - Value of TX ANA clk_en in P2 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_WORD_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_WORD_CLK_EN_SHIFT (3U) /*! TX_P2_ANA_WORD_CLK_EN - Value of TX ANA word_clk_en in P2 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_WORD_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_WORD_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_WORD_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_RESET_MASK (0x10U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_RESET_SHIFT (4U) /*! TX_P2_ANA_RESET - Value of TX ANA reset in P2 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_RESET_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_SERIAL_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_SERIAL_EN_SHIFT (5U) /*! TX_P2_ANA_SERIAL_EN - Value of TX ANA serial_en in P2 */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_SERIAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_SERIAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ANA_SERIAL_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DIG_CLK_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DIG_CLK_EN_SHIFT (6U) /*! TX_P2_DIG_CLK_EN - Enable/Disable TX digital clocks in P2 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DATA_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DATA_EN_SHIFT (7U) /*! TX_P2_DATA_EN - This is ANDed with top-level tx_data_en asic input */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ALLOW_RXDET_MASK (0x100U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ALLOW_RXDET_SHIFT (8U) /*! TX_P2_ALLOW_RXDET - If asserted, then rxdet request is allowed */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ALLOW_RXDET_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_TX_P2_ALLOW_RXDET_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0 - TX Power UP Time 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_REFGEN_EN_TIME_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_REFGEN_EN_TIME_SHIFT (0U) /*! TX_REFGEN_EN_TIME - Power up time (in ref_range cycles) for TX ANA refgen enable (spec: >= 1 us) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_REFGEN_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_REFGEN_EN_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_REFGEN_EN_TIME_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_CLK_EN_MASK (0xFF00U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_CLK_EN_SHIFT (8U) /*! TX_CLK_EN - Power up time (in ref_range cycles) for TX ANA clock enable (spec: >= 1 us) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_TX_CLK_EN_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1 - TX Power UP Time 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_TX_VCM_HOLD_TIME_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_TX_VCM_HOLD_TIME_SHIFT (0U) /*! TX_VCM_HOLD_TIME - Power up time (in ref_range cycles) for TX ANA vreg enable (spec: >= 800 us) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_TX_VCM_HOLD_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_TX_VCM_HOLD_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_TX_VCM_HOLD_TIME_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_SKIP_TX_VCM_HOLD_WAIT_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_SKIP_TX_VCM_HOLD_WAIT_SHIFT (15U) /*! SKIP_TX_VCM_HOLD_WAIT - Skip wait for TX common mode hold power up * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_SKIP_TX_VCM_HOLD_WAIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_SKIP_TX_VCM_HOLD_WAIT_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_SKIP_TX_VCM_HOLD_WAIT_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2 - TX Power UP Time 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_TX_VBOOST_DIS_TIME_MASK (0x1FFFU) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_TX_VBOOST_DIS_TIME_SHIFT (0U) /*! TX_VBOOST_DIS_TIME - TX vboost disable time (in ref_range cycles) (spec: >= 160 us) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_TX_VBOOST_DIS_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_TX_VBOOST_DIS_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_TX_VBOOST_DIS_TIME_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DTB_SEL_MASK (0xE000U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DTB_SEL_SHIFT (13U) /*! DTB_SEL - Selects data to drive on DTB * 0b000..Disabled * 0b001..tx_ack and tx_pwrsm_state[0] * 0b010..tx_ana_rxdetp_result_i, tx_ana_rxdetm_result_i * 0b011..tx_ana_reset_i, tx_ana_clk_en_i * 0b100..Analog/ASIC clocks * 0b101..ASIC early signal / clock aligner shift * 0b110..tx_clk_state counter / lbert strobe * 0b111..ref_dig_rst/tx_dig_rst */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DTB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DTB_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DTB_SEL_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3 - TX Power UP Time 3 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RXDET_TIME_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RXDET_TIME_SHIFT (0U) /*! TX_RXDET_TIME - RX Detect up time (in ref_range cycles), starting from asserting rxdet_en (spec: 12 us < time < 26 us) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RXDET_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RXDET_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RXDET_TIME_MASK) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RESET_TIME_MASK (0x1800U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RESET_TIME_SHIFT (11U) /*! TX_RESET_TIME - TX Reset deassertion time (in ref_range cycles) (spec: >= 50 ns) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RESET_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RESET_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_TX_RESET_TIME_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4 - TX Power UP Time 4 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4_TX_SERIAL_EN_TIME_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4_TX_SERIAL_EN_TIME_SHIFT (0U) /*! TX_SERIAL_EN_TIME - Power up time (in ref_range cycles) for TX ANA serial enable (spec: 130 ns < time < 1 us) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4_TX_SERIAL_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4_TX_SERIAL_EN_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4_TX_SERIAL_EN_TIME_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_FIFO_BYPASS - TX FIFO Bypass */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_FIFO_BYPASS_TX_FIFO_BYPASS_MASK (0x1U) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_FIFO_BYPASS_TX_FIFO_BYPASS_SHIFT (0U) /*! TX_FIFO_BYPASS - Bypass TX datapath FIFO * 0b0..No bypass * 0b1..Bypass */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_FIFO_BYPASS_TX_FIFO_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_FIFO_BYPASS_TX_FIFO_BYPASS_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_FIFO_BYPASS_TX_FIFO_BYPASS_MASK) /*! @} */ /*! @name LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5 - TX Power UP Time 4 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5_TX_VCM_HOLD_GS_TIME_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5_TX_VCM_HOLD_GS_TIME_SHIFT (0U) /*! TX_VCM_HOLD_GS_TIME - TX common mode gear-shift time (in ref range cycles) (spec: >= 400 us) */ #define ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5_TX_VCM_HOLD_GS_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5_TX_VCM_HOLD_GS_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5_TX_VCM_HOLD_GS_TIME_MASK) /*! @} */ /*! @name LANE0_DIG_TX_LBERT_CTL - Pattern Generator Controls */ /*! @{ */ #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_MODE_MASK (0xFU) #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_MODE_SHIFT (0U) /*! MODE - Pattern to Generate * 0b0000..Disabled * 0b0001..lfsr31: X^31 + X^28 + 1 * 0b0010..lfsr23: X^23 + X^18 + 1 * 0b0011..lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 * 0b0100..lfsr16: x^16 + x^5 + x^4 + x^3 + 1 * 0b0101..lfsr15: X^15 + X^14 + 1 * 0b0110..lfsr11: X^11 + X^9 + 1 * 0b0111..lfsr9: X^9 + X^5 + 1 * 0b1000..lfsr7: X^7 + X^6 + 1 * 0b1001..Fixed word (PAT0) * 0b1010..DC balanced word (PAT0, ~PAT0) * 0b1011..Fixed pattern: (000, PAT0, 3ff, ~PAT0) */ #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_LBERT_CTL_MODE_SHIFT)) & ENET_PHY_LANE0_DIG_TX_LBERT_CTL_MODE_MASK) #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_TRIGGER_ERR_MASK (0x10U) #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_TRIGGER_ERR_SHIFT (4U) /*! TRIGGER_ERR - Insert a Single Error into a lsb */ #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_TRIGGER_ERR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_LBERT_CTL_TRIGGER_ERR_SHIFT)) & ENET_PHY_LANE0_DIG_TX_LBERT_CTL_TRIGGER_ERR_MASK) #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_PAT0_MASK (0x7FE0U) #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_PAT0_SHIFT (5U) /*! PAT0 - Pattern for modes 3-5 */ #define ENET_PHY_LANE0_DIG_TX_LBERT_CTL_PAT0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_TX_LBERT_CTL_PAT0_SHIFT)) & ENET_PHY_LANE0_DIG_TX_LBERT_CTL_PAT0_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0 - RX Power State Control for P0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_LOS_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_LOS_EN_SHIFT (0U) /*! RX_P0_ANA_LOS_EN - Value of RX ANA los_en in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_LOS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_LOS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_LOS_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_AFE_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_AFE_EN_SHIFT (1U) /*! RX_P0_ANA_AFE_EN - Value of RX ANA afe_en in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_AFE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_AFE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_AFE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_VREG_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_VREG_EN_SHIFT (2U) /*! RX_P0_ANA_CLK_VREG_EN - Value of RX ANA clk_vreg_en in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_VREG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_VREG_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_VREG_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DIV16P5_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DIV16P5_CLK_EN_SHIFT (3U) /*! RX_P0_ANA_DIV16P5_CLK_EN - Value of RX ANA div16p5_clk_en in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_EN_SHIFT (4U) /*! RX_P0_ANA_CLK_EN - Value of RX ANA clk_en in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_DCC_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_DCC_EN_SHIFT (5U) /*! RX_P0_ANA_CLK_DCC_EN - Value of RX ANA CLK_DCC_EN in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_DCC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_DCC_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CLK_DCC_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DESER_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DESER_EN_SHIFT (6U) /*! RX_P0_ANA_DESER_EN - Value of RX ANA deserial_en in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DESER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DESER_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_DESER_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CDR_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CDR_EN_SHIFT (7U) /*! RX_P0_ANA_CDR_EN - Value of RX ANA cdr_en in P0 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CDR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CDR_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_ANA_CDR_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_FREQ_RST_MASK (0x100U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_FREQ_RST_SHIFT (8U) /*! RX_P0_VCO_FREQ_RST - Enable/Disable resetting the RX VCO frequency in P0 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_FREQ_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_FREQ_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_FREQ_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CAL_RST_MASK (0x200U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CAL_RST_SHIFT (9U) /*! RX_P0_VCO_CAL_RST - Enable/Disable resetting the RX VCO in P0 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CAL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CAL_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CAL_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CONTCAL_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CONTCAL_EN_SHIFT (10U) /*! RX_P0_VCO_CONTCAL_EN - Enable/Disable continuous calibration of the RX VCO in P0 If * RX_P0_DIG_CLK_EN and the top-level rx_data_en are both asserted, then continuous calibration is turned off * and this value is ignored * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CONTCAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CONTCAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_VCO_CONTCAL_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_DIG_CLK_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_DIG_CLK_EN_SHIFT (11U) /*! RX_P0_DIG_CLK_EN - Enable/Disable RX digital clocks in P0 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_FORCE_DFE_BYPASS_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_FORCE_DFE_BYPASS_SHIFT (12U) /*! RX_P0_FORCE_DFE_BYPASS - Enable/Disable RX DFE in P0 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_FORCE_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_FORCE_DFE_BYPASS_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_RX_P0_FORCE_DFE_BYPASS_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S - RX Power State Control for P0S */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_LOS_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_LOS_EN_SHIFT (0U) /*! RX_P0S_ANA_LOS_EN - Value of RX ANA los_en in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_LOS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_LOS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_LOS_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_AFE_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_AFE_EN_SHIFT (1U) /*! RX_P0S_ANA_AFE_EN - Value of RX ANA afe_en in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_AFE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_AFE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_AFE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_VREG_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_VREG_EN_SHIFT (2U) /*! RX_P0S_ANA_CLK_VREG_EN - Value of RX ANA clk_vreg_en in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_VREG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_VREG_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_VREG_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DIV16P5_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DIV16P5_CLK_EN_SHIFT (3U) /*! RX_P0S_ANA_DIV16P5_CLK_EN - Value of RX ANA div16p5_clk_en in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_EN_SHIFT (4U) /*! RX_P0S_ANA_CLK_EN - Value of RX ANA clk_en in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_DCC_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_DCC_EN_SHIFT (5U) /*! RX_P0S_ANA_CLK_DCC_EN - Value of RX ANA CLK_DCC_EN in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_DCC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_DCC_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CLK_DCC_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DESER_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DESER_EN_SHIFT (6U) /*! RX_P0S_ANA_DESER_EN - Value of RX ANA deserial_en in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DESER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DESER_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_DESER_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CDR_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CDR_EN_SHIFT (7U) /*! RX_P0S_ANA_CDR_EN - Value of RX ANA cdr_en in P0S */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CDR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CDR_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_ANA_CDR_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_FREQ_RST_MASK (0x100U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_FREQ_RST_SHIFT (8U) /*! RX_P0S_VCO_FREQ_RST - Enable/Disable resetting the RX VCO frequency in P0S * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_FREQ_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_FREQ_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_FREQ_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CAL_RST_MASK (0x200U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CAL_RST_SHIFT (9U) /*! RX_P0S_VCO_CAL_RST - Enable/Disable resetting the RX VCO in P0S * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CAL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CAL_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CAL_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CONTCAL_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CONTCAL_EN_SHIFT (10U) /*! RX_P0S_VCO_CONTCAL_EN - Enable/Disable continuous calibration of the RX VCO in P0S If * RX_P0S_DIG_CLK_EN and the top-level rx_data_en are both asserted, then continuous calibration is turned * off and this value is ignored * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CONTCAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CONTCAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_VCO_CONTCAL_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_DIG_CLK_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_DIG_CLK_EN_SHIFT (11U) /*! RX_P0S_DIG_CLK_EN - Enable/Disable RX digital clocks in P0S * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0S_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0s_FORCE_DFE_BYPASS_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0s_FORCE_DFE_BYPASS_SHIFT (12U) /*! RX_P0s_FORCE_DFE_BYPASS - Enable/Disable RX DFE in P0s * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0s_FORCE_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0s_FORCE_DFE_BYPASS_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_RX_P0s_FORCE_DFE_BYPASS_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1 - RX Power State Control for P1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_LOS_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_LOS_EN_SHIFT (0U) /*! RX_P1_ANA_LOS_EN - Value of RX ANA los_en in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_LOS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_LOS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_LOS_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_AFE_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_AFE_EN_SHIFT (1U) /*! RX_P1_ANA_AFE_EN - Value of RX ANA afe_en in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_AFE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_AFE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_AFE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_VREG_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_VREG_EN_SHIFT (2U) /*! RX_P1_ANA_CLK_VREG_EN - Value of RX ANA clk_vreg_en in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_VREG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_VREG_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_VREG_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DIV16P5_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DIV16P5_CLK_EN_SHIFT (3U) /*! RX_P1_ANA_DIV16P5_CLK_EN - Value of RX ANA div16p5_clk_en in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_EN_SHIFT (4U) /*! RX_P1_ANA_CLK_EN - Value of RX ANA clk_en in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_DCC_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_DCC_EN_SHIFT (5U) /*! RX_P1_ANA_CLK_DCC_EN - Value of RX ANA CLK_DCC_EN in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_DCC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_DCC_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CLK_DCC_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DESER_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DESER_EN_SHIFT (6U) /*! RX_P1_ANA_DESER_EN - Value of RX ANA deserial_en in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DESER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DESER_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_DESER_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CDR_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CDR_EN_SHIFT (7U) /*! RX_P1_ANA_CDR_EN - Value of RX ANA cdr_en in P1 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CDR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CDR_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_ANA_CDR_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_FREQ_RST_MASK (0x100U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_FREQ_RST_SHIFT (8U) /*! RX_P1_VCO_FREQ_RST - Enable/Disable resetting the RX VCO frequency in P1 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_FREQ_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_FREQ_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_FREQ_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CAL_RST_MASK (0x200U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CAL_RST_SHIFT (9U) /*! RX_P1_VCO_CAL_RST - Enable/Disable resetting the RX VCO in P1 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CAL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CAL_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CAL_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CONTCAL_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CONTCAL_EN_SHIFT (10U) /*! RX_P1_VCO_CONTCAL_EN - Enable/Disable continuous calibration of the RX VCO in P1 If * RX_P1_DIG_CLK_EN and the top-level rx_data_en are both asserted, then continuous calibration is turned off * and this value is ignored * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CONTCAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CONTCAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_VCO_CONTCAL_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_DIG_CLK_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_DIG_CLK_EN_SHIFT (11U) /*! RX_P1_DIG_CLK_EN - Enable/Disable RX digital clocks in P1 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_FORCE_DFE_BYPASS_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_FORCE_DFE_BYPASS_SHIFT (12U) /*! RX_P1_FORCE_DFE_BYPASS - Enable/Disable RX DFE in P1 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_FORCE_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_FORCE_DFE_BYPASS_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_RX_P1_FORCE_DFE_BYPASS_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2 - RX Power State Control for P2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_LOS_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_LOS_EN_SHIFT (0U) /*! RX_P2_ANA_LOS_EN - Value of RX ANA los_en in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_LOS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_LOS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_LOS_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_AFE_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_AFE_EN_SHIFT (1U) /*! RX_P2_ANA_AFE_EN - Value of RX ANA afe_en in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_AFE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_AFE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_AFE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_VREG_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_VREG_EN_SHIFT (2U) /*! RX_P2_ANA_CLK_VREG_EN - Value of RX ANA clk_vreg_en in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_VREG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_VREG_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_VREG_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DIV16P5_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DIV16P5_CLK_EN_SHIFT (3U) /*! RX_P2_ANA_DIV16P5_CLK_EN - Value of RX ANA div16p5_clk_en in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_EN_SHIFT (4U) /*! RX_P2_ANA_CLK_EN - Value of RX ANA clk_en in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_DCC_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_DCC_EN_SHIFT (5U) /*! RX_P2_ANA_CLK_DCC_EN - Value of RX ANA CLK_DCC_EN in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_DCC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_DCC_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CLK_DCC_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DESER_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DESER_EN_SHIFT (6U) /*! RX_P2_ANA_DESER_EN - Value of RX ANA deserial_en in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DESER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DESER_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_DESER_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CDR_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CDR_EN_SHIFT (7U) /*! RX_P2_ANA_CDR_EN - Value of RX ANA cdr_en in P2 */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CDR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CDR_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_ANA_CDR_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_FREQ_RST_MASK (0x100U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_FREQ_RST_SHIFT (8U) /*! RX_P2_VCO_FREQ_RST - Enable/Disable resetting the RX VCO frequency in P2 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_FREQ_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_FREQ_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_FREQ_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CAL_RST_MASK (0x200U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CAL_RST_SHIFT (9U) /*! RX_P2_VCO_CAL_RST - Enable/Disable resetting the RX VCO in P2 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CAL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CAL_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CAL_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CONTCAL_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CONTCAL_EN_SHIFT (10U) /*! RX_P2_VCO_CONTCAL_EN - Enable/Disable continuous calibration of the RX VCO in P2 If * RX_P2_DIG_CLK_EN and the top-level rx_data_en are both asserted, then continuous calibration is turned off * and this value is ignored * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CONTCAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CONTCAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_VCO_CONTCAL_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_DIG_CLK_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_DIG_CLK_EN_SHIFT (11U) /*! RX_P2_DIG_CLK_EN - Enable/Disable RX digital clocks in P2 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_DIG_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_DIG_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_DIG_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_FORCE_DFE_BYPASS_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_FORCE_DFE_BYPASS_SHIFT (12U) /*! RX_P2_FORCE_DFE_BYPASS - Enable/Disable RX DFE in P2 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_FORCE_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_FORCE_DFE_BYPASS_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_RX_P2_FORCE_DFE_BYPASS_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0 - RX Power UP Time 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_RX_LOS_EN_TIME_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_RX_LOS_EN_TIME_SHIFT (0U) /*! RX_LOS_EN_TIME - Power up time (in ref_range cycles) for RX ANA los enable (spec >= 1.1 us) */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_RX_LOS_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_RX_LOS_EN_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_RX_LOS_EN_TIME_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_FAST_RX_LOS_EN_WAIT_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_FAST_RX_LOS_EN_WAIT_SHIFT (10U) /*! FAST_RX_LOS_EN_WAIT - Enable fast wait for RX LOS enable (simulation only) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_FAST_RX_LOS_EN_WAIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_FAST_RX_LOS_EN_WAIT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_FAST_RX_LOS_EN_WAIT_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1 - RX Power UP Time 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_RATE_TIME_MASK (0x3U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_RATE_TIME_SHIFT (0U) /*! RX_RATE_TIME - Power up time (in ref_range cycles) for RX ANA rate or width change */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_RATE_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_RATE_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_RATE_TIME_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_VREG_EN_TIME_MASK (0x1FCU) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_VREG_EN_TIME_SHIFT (2U) /*! RX_VREG_EN_TIME - Power up time (in ref_range cycles divided by 2) for RX ANA vreg enable (spec > 2 us) */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_VREG_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_VREG_EN_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_RX_VREG_EN_TIME_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2 - RX Power UP Time 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_CDR_EN_TIME_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_CDR_EN_TIME_SHIFT (0U) /*! RX_CDR_EN_TIME - Power up time (in ref_range cycles) for RX ANA CDR (or dfe/dfe_taps) enable (spec 200 ns) */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_CDR_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_CDR_EN_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_CDR_EN_TIME_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_EN_TIME_MASK (0x60U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_EN_TIME_SHIFT (5U) /*! RX_DESER_EN_TIME - Power up time (in ref_range cycles) for RX ANA deserial enable */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_EN_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_EN_TIME_MASK) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_DIS_TIME_MASK (0x180U) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_DIS_TIME_SHIFT (7U) /*! RX_DESER_DIS_TIME - Power down time in (ref_range cycles) for RX ANA deserial enable */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_DIS_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_DIS_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_RX_DESER_DIS_TIME_MASK) /*! @} */ /*! @name LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3 - RX Power UP Control 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3_RX_CLK_DCC_EN_TIME_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3_RX_CLK_DCC_EN_TIME_SHIFT (0U) /*! RX_CLK_DCC_EN_TIME - Power up time (in ref_range cycles) for RX ANA clk dcc enable (spec > 1 us) */ #define ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3_RX_CLK_DCC_EN_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3_RX_CLK_DCC_EN_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3_RX_CLK_DCC_EN_TIME_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0 - RX VCO Calibration Controls 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_INT_GAIN_CAL_BOUNCE_CNT_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_INT_GAIN_CAL_BOUNCE_CNT_SHIFT (0U) /*! INT_GAIN_CAL_BOUNCE_CNT - Number of bounces (i.e. direction changes) on the int_gain code before indicating that the RX VCO calibration is done */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_INT_GAIN_CAL_BOUNCE_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_INT_GAIN_CAL_BOUNCE_CNT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_INT_GAIN_CAL_BOUNCE_CNT_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1 - RX VCO Calibration Controls 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_OVRD_SEL_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_OVRD_SEL_SHIFT (0U) /*! RX_VCO_OVRD_SEL - Override the calibration Controls from the RX PWRSM * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_OVRD_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_OVRD_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_OVRD_SEL_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_FREQ_RST_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_FREQ_RST_SHIFT (1U) /*! RX_VCO_FREQ_RST - Override Value for the frequency reset from the RX PWRSM * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_FREQ_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_FREQ_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_FREQ_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CAL_RST_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CAL_RST_SHIFT (2U) /*! RX_VCO_CAL_RST - Override Value for the calibration reset from the RX PWRSM * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CAL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CAL_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CAL_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CONTCAL_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CONTCAL_EN_SHIFT (3U) /*! RX_VCO_CONTCAL_EN - Override Value for the continuous calibration enable from the RX PWRSM * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CONTCAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CONTCAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_RX_VCO_CONTCAL_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DISABLE_INT_CAL_MODE_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DISABLE_INT_CAL_MODE_SHIFT (4U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DISABLE_INT_CAL_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DISABLE_INT_CAL_MODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DISABLE_INT_CAL_MODE_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DPLL_CAL_UG_MASK (0x1E0U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DPLL_CAL_UG_SHIFT (5U) /*! DPLL_CAL_UG - DPLL Calibration Update on int_gain code * 0b0000..0 * *..(1/16)*2^(DPLL_CAL_UG-1) LSB/update */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DPLL_CAL_UG(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DPLL_CAL_UG_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DPLL_CAL_UG_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DTB_SEL_MASK (0xFE00U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DTB_SEL_SHIFT (9U) /*! DTB_SEL - DTB Select for RX VCO DTB Signals * 0b0000001..{chkfrq_en, ref_dig_clk} * 0b0000010..{rx_ana_cdr_vco_en_i, rx_ana_cdr_startup_i} * 0b0000100..{rx_vco_up, dpll_freq_rst} * 0b0001000..{rx_vco_contcal_en, rx_vco_cal_rst} * 0b0010000..{chkfrq_done, vcoclk_too_fast} * 0b0100000..{cal_dir, rx_vco_cal_done} * 0b1000000..{curr_state[0], rx_vco_cnt[0]} */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DTB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DTB_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DTB_SEL_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 - RX VCO Calibration Controls 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_START_VAL_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_START_VAL_SHIFT (0U) /*! FREG_TUNE_START_VAL - Starting value of freq tune code */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_START_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_START_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_START_VAL_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_CAL_STEPS_MASK (0x3C00U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_CAL_STEPS_SHIFT (10U) /*! FREG_TUNE_CAL_STEPS - Number of cal steps of freq tune */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_CAL_STEPS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_CAL_STEPS_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_FREG_TUNE_CAL_STEPS_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0 - RX Power UP Time 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_UPDATE_TIME_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_UPDATE_TIME_SHIFT (0U) /*! RX_VCO_UPDATE_TIME - Settle time in (ref_range cycles) for RX ANA VCO update (freq_tune or int_gain) (spec > 350 ns) */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_UPDATE_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_UPDATE_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_UPDATE_TIME_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_CNTR_PWRUP_TIME_MASK (0xFF0U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_CNTR_PWRUP_TIME_SHIFT (4U) /*! RX_VCO_CNTR_PWRUP_TIME - Power up time for RX ANA VCO counter (spec: > 2 us) */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_CNTR_PWRUP_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_CNTR_PWRUP_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_RX_VCO_CNTR_PWRUP_TIME_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_FAST_RX_VCO_WAIT_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_FAST_RX_VCO_WAIT_SHIFT (12U) /*! FAST_RX_VCO_WAIT - Enable fast RX VCO wait times (simulation only) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_FAST_RX_VCO_WAIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_FAST_RX_VCO_WAIT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_FAST_RX_VCO_WAIT_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1 - RX Power UP Time 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_CNTR_SETTLE_TIME_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_CNTR_SETTLE_TIME_SHIFT (0U) /*! RX_VCO_CNTR_SETTLE_TIME - RX VCO counter value settling time in (ref_dig_clk cycles) (spec: 1 ref_dig_clk cycle) */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_CNTR_SETTLE_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_CNTR_SETTLE_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_CNTR_SETTLE_TIME_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_FAST_RX_VCO_CAL_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_FAST_RX_VCO_CAL_SHIFT (3U) /*! FAST_RX_VCO_CAL - Enable fast RX VCO calibration (skips calibration) (simulation only) * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_FAST_RX_VCO_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_FAST_RX_VCO_CAL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_FAST_RX_VCO_CAL_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_STARTUP_TIME_MASK (0x7F0U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_STARTUP_TIME_SHIFT (4U) /*! RX_VCO_STARTUP_TIME - Power up time in ref_range cycles for RX ANA VCO startup (spec > 250 ns) */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_STARTUP_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_STARTUP_TIME_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_RX_VCO_STARTUP_TIME_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0 - RX VCO Status 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_FREQ_TUNE_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_FREQ_TUNE_SHIFT (0U) /*! RX_ANA_CDR_FREQ_TUNE - Current value of rx_ana_cdr_freq_tune_i */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_FREQ_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_FREQ_TUNE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_FREQ_TUNE_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_PD_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_PD_SHIFT (10U) /*! RX_ANA_VCO_CNTR_PD - Current value of rx_ana_vco_cntr_pd_i */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_PD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_PD_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_PD_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_EN_SHIFT (11U) /*! RX_ANA_VCO_CNTR_EN - Current value of rx_ana_vco_cntr_en_i */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_VCO_CNTR_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_STARTUP_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_STARTUP_SHIFT (12U) /*! RX_ANA_CDR_STARTUP - Current value of rx_ana_cdr_startup_i */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_STARTUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_STARTUP_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_STARTUP_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_VCO_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_VCO_EN_SHIFT (13U) /*! RX_ANA_CDR_VCO_EN - Current value of rx_ana_cdr_vco_en_i */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_VCO_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_VCO_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CDR_VCO_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CLK_EN_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CLK_EN_SHIFT (14U) /*! RX_ANA_CLK_EN - Current value of rx_ana_clk_en_i */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_RX_ANA_CLK_EN_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1 - RX VCO Status 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FSM_STATE_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FSM_STATE_SHIFT (0U) /*! RX_VCO_FSM_STATE - Value of the RX VCO CAL FSM */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FSM_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FSM_STATE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FSM_STATE_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FREQ_RST_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FREQ_RST_SHIFT (4U) /*! RX_VCO_FREQ_RST - Value of the RX VCO frequency reset from the RX PWRSM */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FREQ_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FREQ_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_FREQ_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_RST_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_RST_SHIFT (5U) /*! RX_VCO_CAL_RST - Value of the calibration reset from the RX PWRSM */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_RST_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CONTCAL_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CONTCAL_EN_SHIFT (6U) /*! RX_VCO_CONTCAL_EN - Value of the continuous calibration enable from the RX PWRSM */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CONTCAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CONTCAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CONTCAL_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_DONE_MASK (0x80U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_DONE_SHIFT (7U) /*! RX_VCO_CAL_DONE - Indicates that the RX VCO has completed calibration * 0b0..Not completed * 0b1..Completed */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_RX_VCO_CAL_DONE_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DPLL_FREQ_RST_MASK (0x100U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DPLL_FREQ_RST_SHIFT (8U) /*! DPLL_FREQ_RST - Indicates that the RX integral frequency is reset or not * 0b0..Not reset * 0b1..Reset */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DPLL_FREQ_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DPLL_FREQ_RST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DPLL_FREQ_RST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2 - RX VCO Status 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCO_CNTR_FINAL_MASK (0x1FFFU) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCO_CNTR_FINAL_SHIFT (0U) /*! VCO_CNTR_FINAL - Value of RX VCO counter when refclk counter expired */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCO_CNTR_FINAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCO_CNTR_FINAL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCO_CNTR_FINAL_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCOCLK_TOO_FAST_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCOCLK_TOO_FAST_SHIFT (13U) /*! VCOCLK_TOO_FAST - Indicates that the RX VCO clock frequency is too fast * 0b0..Not too fast * 0b1..Too fast */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCOCLK_TOO_FAST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCOCLK_TOO_FAST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_VCOCLK_TOO_FAST_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_CORRECT_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_CORRECT_SHIFT (14U) /*! RX_VCO_CORRECT - Indicates that the RX VCO clock has the correct frequency * 0b0..Incorrect * 0b1..Correct */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_CORRECT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_CORRECT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_CORRECT_MASK) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_UP_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_UP_SHIFT (15U) /*! RX_VCO_UP - Indicates that the RX VCO is ready * 0b0..Not ready * 0b1..Ready */ #define ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_UP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_UP_SHIFT)) & ENET_PHY_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_RX_VCO_UP_MASK) /*! @} */ /*! @name LANE0_DIG_RX_LBERT_CTL - Pattern Matcher Controls */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_LBERT_CTL_MODE_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_LBERT_CTL_MODE_SHIFT (0U) /*! MODE - Pattern to Match * 0b0000..Disabled * 0b0001..lfsr31: X^31 + X^28 + 1 * 0b0010..lfsr23: X^23 + X^18 + 1 * 0b0011..lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 * 0b0100..lfsr16: x^16 + x^5 + x^4 + x^3 + 1 * 0b0101..lfsr15: X^15 + X^14 + 1 * 0b0110..lfsr11: X^11 + X^9 + 1 * 0b0111..lfsr9: X^9 + X^5 + 1 * 0b1000..lfsr7: X^7 + X^6 + 1 * 0b1001..d[n] = d[n-10] * 0b1010..d[n] = !d[n-10] * 0b1011..d[n] = !d[n-20] */ #define ENET_PHY_LANE0_DIG_RX_LBERT_CTL_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_LBERT_CTL_MODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_LBERT_CTL_MODE_MASK) #define ENET_PHY_LANE0_DIG_RX_LBERT_CTL_SYNC_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_LBERT_CTL_SYNC_SHIFT (4U) /*! SYNC - Synchronize Pattern Matcher LFSR with Incoming Data */ #define ENET_PHY_LANE0_DIG_RX_LBERT_CTL_SYNC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_LBERT_CTL_SYNC_SHIFT)) & ENET_PHY_LANE0_DIG_RX_LBERT_CTL_SYNC_MASK) /*! @} */ /*! @name LANE0_DIG_RX_LBERT_ERR - Pattern Match Error Counter */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_LBERT_ERR_COUNT_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_LBERT_ERR_COUNT_SHIFT (0U) #define ENET_PHY_LANE0_DIG_RX_LBERT_ERR_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_LBERT_ERR_COUNT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_LBERT_ERR_COUNT_MASK) #define ENET_PHY_LANE0_DIG_RX_LBERT_ERR_OV14_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_LBERT_ERR_OV14_SHIFT (15U) #define ENET_PHY_LANE0_DIG_RX_LBERT_ERR_OV14(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_LBERT_ERR_OV14_SHIFT)) & ENET_PHY_LANE0_DIG_RX_LBERT_ERR_OV14_MASK) /*! @} */ /*! @name LANE0_DIG_RX_CDR_CDR_CTL_0 - Control Bits for Receiver in Recovered Domain */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_MASK (0x3U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_SHIFT (0U) /*! PHDET_EN - Enable Phase Detector */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EDGE_MASK (0xCU) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EDGE_SHIFT (2U) /*! PHDET_EDGE - Edges to Use for Phase Detection * 0b10..Use both edges * 0b01..Use rising edges only * 0b11..Use falling edges only * 0b00..Ignore all edges */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EDGE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EDGE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EDGE_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_POL_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_POL_SHIFT (4U) /*! PHDET_POL - Reverse polarity of phase error * 0b0..No reverse * 0b1..Reverse */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_POL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_POL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_POL_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_PR_MODE_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_PR_MODE_SHIFT (5U) /*! PHDET_EN_PR_MODE - Enable partial response phase detector mode * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_PR_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_PR_MODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_PHDET_EN_PR_MODE_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_ALWAYS_REALIGN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_ALWAYS_REALIGN_SHIFT (6U) /*! ALWAYS_REALIGN - Realign on any misaligned comma */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_ALWAYS_REALIGN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_ALWAYS_REALIGN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_ALWAYS_REALIGN_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_DTB_SEL_MASK (0x780U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_DTB_SEL_SHIFT (7U) /*! DTB_SEL - Select to Drive Various Signals onto the DTB * 0b0000..Disabled * 0b0001..rx_pr_stable, rx_afe_stable from rx_ana_ctl * 0b0010..com_good, com_bad from rx_align * 0b0011..shift_in_prog, ana_odd_data from rx_align * 0b0110..error_high, low from lbert_pm * 0b0111..ana_los, los_filter from los block * 0b1000..eios_state[0], eios_det from los block * 0b1001..cdr_valid, msb of FSM state from cdr_ctl * 0b1010..2 lsb's of FSM state from cdr_ctl * 0b1011..rx_dig_rst,rx_dig_en * 0b1100..rx_ana_word_clk_i, rx_ana_dword_clk_i */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_DTB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_DTB_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_0_DTB_SEL_MASK) /*! @} */ /*! @name LANE0_DIG_RX_CDR_CDR_CTL_1 - CDR Control 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT0_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT0_SHIFT (0U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT0_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT1_MASK (0xFC00U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT1_SHIFT (10U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_1_SSC_OFF_CNT1_MASK) /*! @} */ /*! @name LANE0_DIG_RX_CDR_CDR_CTL_2 - CDR Control 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT0_MASK (0x1FFU) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT0_SHIFT (0U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT0_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT1_MASK (0xFE00U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT1_SHIFT (9U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_2_SSC_ON_CNT1_MASK) /*! @} */ /*! @name LANE0_DIG_RX_CDR_CDR_CTL_3 - CDR Control 3 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG0_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG0_SHIFT (0U) /*! SSC_OFF_PHUG0 - When SSC mode is disabled, the PHUG value in gain stage 0 is SSC_OFF_PHUG0 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG0_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG1_MASK (0x38U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG1_SHIFT (3U) /*! SSC_OFF_PHUG1 - When SSC mode is disabled, the PHUG value in gain stage 1 is SSC_OFF_PHUG1 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_PHUG1_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_FRUG0_MASK (0x1C0U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_FRUG0_SHIFT (6U) /*! SSC_OFF_FRUG0 - When SSC mode is disabled, the drug value in gain stage 0 is SSC_OFF_FRUG0 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_FRUG0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_FRUG0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_SSC_OFF_FRUG0_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_OVRD_DPLL_GAIN_MASK (0x200U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_OVRD_DPLL_GAIN_SHIFT (9U) /*! OVRD_DPLL_GAIN - Override PHUG and FRUG values * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_OVRD_DPLL_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_OVRD_DPLL_GAIN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_OVRD_DPLL_GAIN_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_PHUG_OVRD_VALUE_MASK (0x1C00U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_PHUG_OVRD_VALUE_SHIFT (10U) /*! PHUG_OVRD_VALUE - Override Value for PHUG (Phase Update Gain) * 0b000..0 * 0b001..1000 ppm * 0b010..2000 ppm * 0b011..3000 ppm * 0b100..4000 ppm * 0b101..5000 ppm * 0b110..6000 ppm * 0b111..7000 ppm */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_PHUG_OVRD_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_PHUG_OVRD_VALUE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_PHUG_OVRD_VALUE_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_FRUG_OVRD_VALUE_MASK (0xE000U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_FRUG_OVRD_VALUE_SHIFT (13U) /*! FRUG_OVRD_VALUE - Override Value for FRUG (Frequency Update Gain) * 0b000..0 * 0b001..1/16 LSB/update * 0b010..1/8 LSB/update * 0b011..1/4 LSB/update * 0b100..1/2 LSB/update * 0b101..1 LSB/update * 0b110..2 LSB/update * 0b111..4 LSB/update */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_FRUG_OVRD_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_FRUG_OVRD_VALUE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_3_FRUG_OVRD_VALUE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_CDR_CDR_CTL_4 - CDR Control 4 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_OFF_FRUG1_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_OFF_FRUG1_SHIFT (0U) /*! SSC_OFF_FRUG1 - When SSC mode is disabled, the FRUG value in gain stage 1 is SSC_OFF_FRUG1 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_OFF_FRUG1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_OFF_FRUG1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_OFF_FRUG1_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG0_MASK (0x38U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG0_SHIFT (3U) /*! SSC_ON_FRUG0 - When SSC mode is enabled, the FRUG value in gain stage 0 is SSC_ON_FRUG0 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG0_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG1_MASK (0x1C0U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG1_SHIFT (6U) /*! SSC_ON_FRUG1 - When SSC mode is enabled, the FRUG value in gain stage 1 is SSC_ON_FRUG1 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_FRUG1_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG0_MASK (0xE00U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG0_SHIFT (9U) /*! SSC_ON_PHUG0 - When SSC mode is enabled, the PHUG value in gain stage 0 is SSC_ON_PHUG0 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG0_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG1_MASK (0x7000U) #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG1_SHIFT (12U) /*! SSC_ON_PHUG1 - When SSC mode is enabled, the PHUG value in gain stage 1 is SSC_ON_PHUG1 */ #define ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_CDR_CTL_4_SSC_ON_PHUG1_MASK) /*! @} */ /*! @name LANE0_DIG_RX_CDR_STAT - Current Output Values to DPLL (PHUG, FRUG) */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_CDR_STAT_PHUG_VALUE_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_CDR_STAT_PHUG_VALUE_SHIFT (0U) /*! PHUG_VALUE - Current value for dpll_phug[2:0] */ #define ENET_PHY_LANE0_DIG_RX_CDR_STAT_PHUG_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_STAT_PHUG_VALUE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_STAT_PHUG_VALUE_MASK) #define ENET_PHY_LANE0_DIG_RX_CDR_STAT_FRUG_VALUE_MASK (0x38U) #define ENET_PHY_LANE0_DIG_RX_CDR_STAT_FRUG_VALUE_SHIFT (3U) /*! FRUG_VALUE - Current value for dpll_frug[2:0] */ #define ENET_PHY_LANE0_DIG_RX_CDR_STAT_FRUG_VALUE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_CDR_STAT_FRUG_VALUE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_CDR_STAT_FRUG_VALUE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_DPLL_FREQ - Current Frequency Integrator Value */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_VAL_MASK (0x3FFFU) #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_VAL_SHIFT (0U) /*! VAL - Freq is 125*VAL ppm from the reference (volatile and 2 reads needed to read value) */ #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_VAL_MASK) /*! @} */ /*! @name LANE0_DIG_RX_DPLL_FREQ_BOUND_0 - Frequency Bounds for Incoming Data Stream 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_FREQ_BOUND_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_FREQ_BOUND_EN_SHIFT (0U) /*! FREQ_BOUND_EN - Enable the frequency bounds feature * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_FREQ_BOUND_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_FREQ_BOUND_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_FREQ_BOUND_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_UPPER_FREQ_BOUND_MASK (0x7FEU) #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_UPPER_FREQ_BOUND_SHIFT (1U) /*! UPPER_FREQ_BOUND - Upper frequency bound in terms of LSBs of the integral control code */ #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_UPPER_FREQ_BOUND(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_UPPER_FREQ_BOUND_SHIFT)) & ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_UPPER_FREQ_BOUND_MASK) /*! @} */ /*! @name LANE0_DIG_RX_DPLL_FREQ_BOUND_1 - Frequency Bounds for Incoming Data Stream 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_LOWER_FREQ_BOUND_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_LOWER_FREQ_BOUND_SHIFT (0U) /*! LOWER_FREQ_BOUND - Lower frequency bound in terms of LSBs of the integral control code */ #define ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_LOWER_FREQ_BOUND(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_LOWER_FREQ_BOUND_SHIFT)) & ENET_PHY_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_LOWER_FREQ_BOUND_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0 - Adaptation Configuration 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TOP_ASM1_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TOP_ASM1_SHIFT (0U) /*! N_TOP_ASM1 - Number of top level loop iterations for ASM1 */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TOP_ASM1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TOP_ASM1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TOP_ASM1_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TGG_ASM1_MASK (0x3C00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TGG_ASM1_SHIFT (10U) /*! N_TGG_ASM1 - Number of toggle loop iterations for ASM1 */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TGG_ASM1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TGG_ASM1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_N_TGG_ASM1_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_START_ASM1_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_START_ASM1_SHIFT (14U) /*! START_ASM1 - Start adaptation state machine #1 (VGA, CTLE, DFE, EYEH) * 0b0..Doesn't start * 0b1..Starts */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_START_ASM1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_START_ASM1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_START_ASM1_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_ADPT_CLK_DIV4_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_ADPT_CLK_DIV4_EN_SHIFT (15U) /*! ADPT_CLK_DIV4_EN - Set the adaptation clock to be divided by 4 (default is div2) * 0b0..Not set * 0b1..Set */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_ADPT_CLK_DIV4_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_ADPT_CLK_DIV4_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_ADPT_CLK_DIV4_EN_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1 - Adaptation Configuration 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_N_WAIT_ASM1_MASK (0x7FU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_N_WAIT_ASM1_SHIFT (0U) /*! N_WAIT_ASM1 - Number of wait cycles for Adaptation SM #1 */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_N_WAIT_ASM1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_N_WAIT_ASM1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_N_WAIT_ASM1_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_VAL_MASK (0x300U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_VAL_SHIFT (8U) /*! CTLE_POLE_OVRD_VAL - CTLE Pole override value to load at start of adaptation */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_VAL_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_EN_SHIFT (10U) /*! CTLE_POLE_OVRD_EN - Override CTLE pole value (only valid if adaptation is run) * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_CTLE_POLE_OVRD_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DFE_T1_ANA_DIS_MASK (0x800U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DFE_T1_ANA_DIS_SHIFT (11U) /*! DFE_T1_ANA_DIS - Disable updating DFE tap1 analog values during adaptation * 0b0..Not disable * 0b1..Disable */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DFE_T1_ANA_DIS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DFE_T1_ANA_DIS_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DFE_T1_ANA_DIS_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2 - Adaptation Configuration 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_0_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_0_SHIFT (0U) /*! TGG_PTTRN_0 - Pattern for the First Toggle Loop */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_0_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_1_MASK (0x3E0U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_1_SHIFT (5U) /*! TGG_PTTRN_1 - Pattern for the Second Toggle Loop */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_TGG_PTTRN_1_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3 - Adaptation Configuration 3 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_CTLE_EN_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_CTLE_EN_SHIFT (0U) /*! CTLE_EN - Enable CTLE Boost Adaptation */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_CTLE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_CTLE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_CTLE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_VGA_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_VGA_EN_SHIFT (5U) /*! VGA_EN - Enable VGA adaptation * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_VGA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_VGA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_VGA_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ATT_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ATT_EN_SHIFT (6U) /*! ATT_EN - Enable ATT adaptation * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ATT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ATT_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ATT_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DFE_EN_MASK (0xF80U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DFE_EN_SHIFT (7U) /*! DFE_EN - Enable DFE adaptation for taps 5-1 */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DFE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DFE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DFE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHE_EN_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHE_EN_SHIFT (12U) /*! EYEHE_EN - Enable eye height measurement using even error slicer * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHO_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHO_EN_SHIFT (13U) /*! EYEHO_EN - Enable eye height measurement using odd error slicer * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHO_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHO_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_EYEHO_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_TGG_EN_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_TGG_EN_SHIFT (14U) /*! TGG_EN - Enable toggling of the error slicer * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_TGG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_TGG_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_TGG_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ESL_TWICE_DSL_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ESL_TWICE_DSL_SHIFT (15U) /*! ESL_TWICE_DSL - Assert if error slicer has twice the voltage range as the data slicer (for the same 8 bits) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ESL_TWICE_DSL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ESL_TWICE_DSL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_ESL_TWICE_DSL_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4 - Adaptation Configuration 4 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_CTLE_TH_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_CTLE_TH_SHIFT (0U) /*! CTLE_TH - CTLE correlation decision threshold (2^N-1) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_CTLE_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_CTLE_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_CTLE_TH_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_VGA_TH_MASK (0xF0U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_VGA_TH_SHIFT (4U) /*! VGA_TH - VGA Correlation Decision Threshold (2^N-1) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_VGA_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_VGA_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_VGA_TH_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE1_TH_MASK (0xF00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE1_TH_SHIFT (8U) /*! DFE1_TH - DFE Tap1 correlation decision threshold (2^N-1) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE1_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE1_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE1_TH_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE2_TH_MASK (0xF000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE2_TH_SHIFT (12U) /*! DFE2_TH - DFE Tap2 correlation decision threshold (2^N-1) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE2_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE2_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DFE2_TH_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5 - Adaptation Configuration 5 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE3_TH_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE3_TH_SHIFT (0U) /*! DFE3_TH - DFE Tap3 correlation decision threshold (2^N-1) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE3_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE3_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE3_TH_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE4_TH_MASK (0xF0U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE4_TH_SHIFT (4U) /*! DFE4_TH - DFE Tap4 correlation decision threshold (2^N-1) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE4_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE4_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE4_TH_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE5_TH_MASK (0xF00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE5_TH_SHIFT (8U) /*! DFE5_TH - DFE Tap5 correlation decision threshold (2^N-1) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE5_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE5_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DFE5_TH_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_TH_OFFSET_MASK (0xF000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_TH_OFFSET_SHIFT (12U) /*! TH_OFFSET - Apply an offset to the decision threshold */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_TH_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_TH_OFFSET_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_TH_OFFSET_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6 - Adaptation Configuration 6 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_CTLE_MU_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_CTLE_MU_SHIFT (0U) /*! CTLE_MU - CTLE boost code update gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_CTLE_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_CTLE_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_CTLE_MU_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_MU_MASK (0x38U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_MU_SHIFT (3U) /*! VGA_MU - VGA Gain Code Update Gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_MU_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_MU_MASK (0x1C0U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_MU_SHIFT (6U) /*! ATT_MU - ATT gain code update gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_MU_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_MASK (0xE00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_SHIFT (9U) /*! VGA_SAT_CNT - VGA saturation count */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_STICKY_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_STICKY_SHIFT (12U) /*! VGA_SAT_CNT_STICKY - If deasserted, then VGA saturation counts must be consecutive to change ATT */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_STICKY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_STICKY_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_VGA_SAT_CNT_STICKY_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_LOW_TH_MASK (0xE000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_LOW_TH_SHIFT (13U) /*! ATT_LOW_TH - ATT low threshold */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_LOW_TH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_LOW_TH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_ATT_LOW_TH_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7 - Adaptation Configuration 7 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_MIN_SAT_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_MIN_SAT_SHIFT (0U) /*! VGA_MIN_SAT - VGA minimum saturation limit */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_MIN_SAT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_MIN_SAT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_MIN_SAT_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_HIGH_MASK (0xF0U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_HIGH_SHIFT (4U) /*! VGA_LEV_HIGH - VGA level high saturation limit */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_HIGH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_HIGH_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_HIGH_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_LOW_MASK (0xF00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_LOW_SHIFT (8U) /*! VGA_LEV_LOW - VGA level low saturation limit */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_LOW(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_LOW_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_VGA_LEV_LOW_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8 - Adaptation Configuration 8 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE1_MU_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE1_MU_SHIFT (0U) /*! DFE1_MU - DFE tap1 code update gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE1_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE1_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE1_MU_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE2_MU_MASK (0x38U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE2_MU_SHIFT (3U) /*! DFE2_MU - DFE tap2 code update gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE2_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE2_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE2_MU_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE3_MU_MASK (0x1C0U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE3_MU_SHIFT (6U) /*! DFE3_MU - DFE tap3 code update gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE3_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE3_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE3_MU_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE4_MU_MASK (0xE00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE4_MU_SHIFT (9U) /*! DFE4_MU - DFE tap4 code update gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE4_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE4_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE4_MU_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE5_MU_MASK (0x7000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE5_MU_SHIFT (12U) /*! DFE5_MU - DFE tap5 code update gain (2^N) */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE5_MU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE5_MU_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DFE5_MU_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9 - Adaptation Configuration 9 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLE_ADPT_INIT_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLE_ADPT_INIT_SHIFT (0U) /*! ERR_SLE_ADPT_INIT - The error even slicer is initialized to this value at the start of a new adaptation request */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLE_ADPT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLE_ADPT_INIT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLE_ADPT_INIT_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLO_ADPT_INIT_MASK (0xFF00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLO_ADPT_INIT_SHIFT (8U) /*! ERR_SLO_ADPT_INIT - The error odd slicer is initialized to this value at the start of a new adaptation request */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLO_ADPT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLO_ADPT_INIT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_ERR_SLO_ADPT_INIT_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG - Reset Adaptation Configuration */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_ATT_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_ATT_SHIFT (0U) /*! RST_ADPT_ATT - Reset ATT when turning off AFE adaptation * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_ATT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_ATT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_ATT_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_VGA_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_VGA_SHIFT (1U) /*! RST_ADPT_VGA - Reset VGA when turning off AFE adaptation * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_VGA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_VGA_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_VGA_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_BOOST_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_BOOST_SHIFT (2U) /*! RST_ADPT_CTLE_BOOST - Reset CTLE Boost when turning off AFE adaptation * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_BOOST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_BOOST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_BOOST_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_POLE_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_POLE_SHIFT (3U) /*! RST_ADPT_CTLE_POLE - Reset CTLE Pole when turning off AFE adaptation * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_POLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_POLE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_CTLE_POLE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_TAP1_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_TAP1_SHIFT (4U) /*! RST_ADPT_TAP1 - Reset Data Tap1 when turning off DFE adaptation (Taps 2-5 are always turned off when DFE adaptation is turned off) * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_TAP1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_TAP1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_RST_ADPT_TAP1_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ATT_STATUS - Value of ATT Adaptation code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ATT_ADPT_CODE_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ATT_ADPT_CODE_SHIFT (0U) /*! ATT_ADPT_CODE - Value of ATT adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ATT_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ATT_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ATT_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ASM1_DON_MASK (0x100U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ASM1_DON_SHIFT (8U) /*! ASM1_DON - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ASM1_DON(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ASM1_DON_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_ASM1_DON_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_VGA_STATUS - Value of VGA Adaptation Code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_VGA_ADPT_CODE_MASK (0x1FFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_VGA_ADPT_CODE_SHIFT (0U) /*! VGA_ADPT_CODE - Value of VGA adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_VGA_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_VGA_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_VGA_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_ASM1_DONE_MASK (0x200U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_ASM1_DONE_SHIFT (9U) /*! ASM1_DONE - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_ASM1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_ASM1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_ASM1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_CTLE_STATUS - Value of CTLE Adaptation Code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_BOOST_ADPT_CODE_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_BOOST_ADPT_CODE_SHIFT (0U) /*! CTLE_BOOST_ADPT_CODE - Value of CTLE boost adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_BOOST_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_BOOST_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_BOOST_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_POLE_ADPT_CODE_MASK (0xC00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_POLE_ADPT_CODE_SHIFT (10U) /*! CTLE_POLE_ADPT_CODE - Value of CTLE pole adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_POLE_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_POLE_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_CTLE_POLE_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_ASM1_DONE_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_ASM1_DONE_SHIFT (12U) /*! ASM1_DONE - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_ASM1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_ASM1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_ASM1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS - Value of DFE Tap1 Adaptation Code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DFE_TAP1_ADPT_CODE_MASK (0x1FFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DFE_TAP1_ADPT_CODE_SHIFT (0U) /*! DFE_TAP1_ADPT_CODE - Value of DFE tap1 adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DFE_TAP1_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DFE_TAP1_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DFE_TAP1_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_ASM1_DONE_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_ASM1_DONE_SHIFT (13U) /*! ASM1_DONE - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_ASM1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_ASM1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_ASM1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS - Value of DFE Tap2 Adaptation Code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DFE_TAP2_ADPT_CODE_MASK (0xFFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DFE_TAP2_ADPT_CODE_SHIFT (0U) /*! DFE_TAP2_ADPT_CODE - Value of DFE tap2 adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DFE_TAP2_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DFE_TAP2_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DFE_TAP2_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_ASM1_DONE_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_ASM1_DONE_SHIFT (12U) /*! ASM1_DONE - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_ASM1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_ASM1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_ASM1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS - Value of DFE Tap3 Adaptation Code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DFE_TAP3_ADPT_CODE_MASK (0xFFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DFE_TAP3_ADPT_CODE_SHIFT (0U) /*! DFE_TAP3_ADPT_CODE - Value of DFE tap3 adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DFE_TAP3_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DFE_TAP3_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DFE_TAP3_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_ASM1_DONE_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_ASM1_DONE_SHIFT (12U) /*! ASM1_DONE - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_ASM1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_ASM1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_ASM1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS - Value of DFE Tap4 Adaptation Code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DFE_TAP4_ADPT_CODE_MASK (0xFFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DFE_TAP4_ADPT_CODE_SHIFT (0U) /*! DFE_TAP4_ADPT_CODE - Value of DFE tap4 adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DFE_TAP4_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DFE_TAP4_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DFE_TAP4_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_ASM1_DONE_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_ASM1_DONE_SHIFT (12U) /*! ASM1_DONE - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_ASM1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_ASM1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_ASM1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS - Value of DFE Tap5 Adaptation Code */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DFE_TAP5_ADPT_CODE_MASK (0xFFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DFE_TAP5_ADPT_CODE_SHIFT (0U) /*! DFE_TAP5_ADPT_CODE - Value of DFE tap5 adaptation code */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DFE_TAP5_ADPT_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DFE_TAP5_ADPT_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DFE_TAP5_ADPT_CODE_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_ASM1_DONE_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_ASM1_DONE_SHIFT (12U) /*! ASM1_DONE - Asserts when adaptation state machine #1 is done * 0b0..Not done * 0b1..Done */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_ASM1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_ASM1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_ASM1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST - Offset Values for RX DFE Data Even High vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_EVEN_HIGH_VDAC_OFST - Offset value for DFE Data Even High vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST - Offset Values for RX DFE Data Even Low vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_EVEN_LOW_VDAC_OFST - Offset value for DFE Data Even Low vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST - Offset Values for RX DFE Data Odd High vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_ODD_HIGH_VDAC_OFST - Offset value for DFE Data Odd High vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST - Offset Values for RX DFE Data Odd Low vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_ODD_LOW_VDAC_OFST - Offset value for DFE Data Odd Low vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN - Sets Values for RX SLICER CTRL EVEN Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_RX_ANA_SLICER_CTRL_E_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_RX_ANA_SLICER_CTRL_E_SHIFT (0U) /*! RX_ANA_SLICER_CTRL_E - Value for rx_ana_slicer_ctrl_e[3:0] */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_RX_ANA_SLICER_CTRL_E(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_RX_ANA_SLICER_CTRL_E_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_RX_ANA_SLICER_CTRL_E_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD - Sets Values for RX SLICER CTRL ODD Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_RX_ANA_SLICER_CTRL_O_MASK (0xFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_RX_ANA_SLICER_CTRL_O_SHIFT (0U) /*! RX_ANA_SLICER_CTRL_O - Value for rx_ana_slicer_ctrl_o[3:0] */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_RX_ANA_SLICER_CTRL_O(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_RX_ANA_SLICER_CTRL_O_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_RX_ANA_SLICER_CTRL_O_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST - Offset Values for RX DFE Error Even vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_SHIFT (0U) /*! DFE_ERROR_EVEN_VDAC_OFST - Offset value for DFE Error Even vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST - Offset Values for RX DFE Error Odd vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_SHIFT (0U) /*! DFE_ERROR_ODD_VDAC_OFST - Offset value for DFE Error Odd vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL - Value of Error Slicer Level */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLO_LVL_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLO_LVL_SHIFT (0U) /*! E_SLO_LVL - Odd Error Slicer Level */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLO_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLO_LVL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLO_LVL_MASK) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLE_LVL_MASK (0xFF00U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLE_LVL_SHIFT (8U) /*! E_SLE_LVL - Even Error Slicer Level */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLE_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLE_LVL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_E_SLE_LVL_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST - Offset Values for RX DFE By-Pass Even vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_SHIFT (0U) /*! DFE_BYPASS_EVEN_VDAC_OFST - Offset value for DFE By-Pass Even vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST - Offset Values for RX DFE By-Pass Odd vDAC */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_SHIFT (0U) /*! DFE_BYPASS_ODD_VDAC_OFST - Offset value for DFE By-Pass Odd vDAC */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_RESET - Adaptation Reset */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_RESET_RESET_ASM1_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_RESET_RESET_ASM1_SHIFT (0U) /*! RESET_ASM1 - Resets adaptation state machine (ASM1) as well as the stats capture block * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_RESET_RESET_ASM1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_RESET_RESET_ASM1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_RESET_RESET_ASM1_MASK) /*! @} */ /*! @name LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10 - Adaptation Configuration 10 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10_CTLE_T1_WT_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10_CTLE_T1_WT_SHIFT (0U) /*! CTLE_T1_WT - When calculating CTLE correlation, tap1 correlation will be right shifted by CTLE_T1_WT before being used */ #define ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10_CTLE_T1_WT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10_CTLE_T1_WT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10_CTLE_T1_WT_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_LD_VAL_1 - Stat Load Value for the Sample Counter 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_LD_VAL_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_LD_VAL_SHIFT (0U) /*! SC1_LD_VAL - Sample counter #1 load value */ #define ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_LD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_LD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_LD_VAL_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_START_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_START_SHIFT (15U) /*! SC1_START - Start Sample Counter #1 * 0b0..Doesn't start * 0b1..Starts */ #define ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_START(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_START_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_LD_VAL_1_SC1_START_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_DATA_MSK - Stat Data Mask Bits [15:0] */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_DATA_MSK_DATA_MSK_15_0_MASK (0xFFFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_DATA_MSK_DATA_MSK_15_0_SHIFT (0U) /*! DATA_MSK_15_0 - Value of data_msk_r[15:0] */ #define ENET_PHY_LANE0_DIG_RX_STAT_DATA_MSK_DATA_MSK_15_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_DATA_MSK_DATA_MSK_15_0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_DATA_MSK_DATA_MSK_15_0_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_MATCH_CTL0 - Stat Match Controls 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_MSK_CR1A_4_0_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_MSK_CR1A_4_0_SHIFT (0U) /*! PTTRN_MSK_CR1A_4_0 - Value of pattern A mask for 1st correlator (bits 4:0) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_MSK_CR1A_4_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_MSK_CR1A_4_0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_MSK_CR1A_4_0_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_CR1A_4_0_MASK (0x3E0U) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_CR1A_4_0_SHIFT (5U) /*! PTTRN_CR1A_4_0 - Value of pattern A for 1st correlator (bits 4:0) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_CR1A_4_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_CR1A_4_0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_PTTRN_CR1A_4_0_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_DATA_MSK_19_16_MASK (0x3C00U) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_DATA_MSK_19_16_SHIFT (10U) /*! DATA_MSK_19_16 - Value of data_msk_r[19:16] */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_DATA_MSK_19_16(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_DATA_MSK_19_16_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_DATA_MSK_19_16_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_SCOPE_DLY_MASK (0xC000U) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_SCOPE_DLY_SHIFT (14U) /*! SCOPE_DLY - Number of clock cycle delays on scope_data_rx_clk An additional MSB is added in SCOPE_DLY_2 */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_SCOPE_DLY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_SCOPE_DLY_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL0_SCOPE_DLY_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_MATCH_CTL1 - Stat Match Controls 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_EN_SHIFT (0U) /*! PTTRN_CR1B_EN - Enable pattern B matching for 1st correlator * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_MSK_CR1B_4_0_MASK (0x3EU) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_MSK_CR1B_4_0_SHIFT (1U) /*! PTTRN_MSK_CR1B_4_0 - Value of pattern B mask for 1st correlator (bits 4:0) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_MSK_CR1B_4_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_MSK_CR1B_4_0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_MSK_CR1B_4_0_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_4_0_MASK (0x7C0U) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_4_0_SHIFT (6U) /*! PTTRN_CR1B_4_0 - Value of pattern B for 1st correlator (bits 4:0) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_4_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_4_0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1B_4_0_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1A_ADPT_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1A_ADPT_EN_SHIFT (11U) /*! PTTRN_CR1A_ADPT_EN - Enable ORing of adaptation pattern with pattern CR1A * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1A_ADPT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1A_ADPT_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL1_PTTRN_CR1A_ADPT_EN_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CTL0 - Stat Controls 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_VGA_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_VGA_SHIFT (1U) /*! CORR_SHFT_SEL_VGA - Select Shift for Error Going to VGA * 0b0..None * 0b1..>> 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_VGA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_VGA_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_VGA_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_SHIFT (2U) /*! CORR_SHFT_SEL - Select Shift for Phase * 0b0..None * 0b1..>> 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SHFT_SEL_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SRC_SEL_MASK (0x18U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SRC_SEL_SHIFT (3U) /*! CORR_SRC_SEL - Select Correlation Input Source * 0b00..rx_error[39:0] * 0b01..rx_phase[39:0] * 0b10..{{20{scope_data_rxclk_dly_s01}},{20{scope_data_rxclk_dly}}} * 0b11..No correlation */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SRC_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SRC_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_SRC_SEL_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_MODE_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_MODE_EN_SHIFT (5U) /*! CORR_MODE_EN - Enable correlation mode * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_MODE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_MODE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_CORR_MODE_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SHFT_SEL_MASK (0x3C0U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SHFT_SEL_SHIFT (6U) /*! STAT_SHFT_SEL - Select Stat Source Shift Value * 0b0000..Correlate N-1 -> N+3 (use N for offset calibration) * 0b0001..Correlate N+1 -> N+5 (for taps1-5) * 0b0010..Correlate N+6 -> N+10 * 0b0011..Correlate N+11 -> N+15 * 0b0100..Correlate N+16 -> N+20 * 0b0101..Correlate N+21 -> N+25 * 0b0110..Correlate N+26 -> N+30 * 0b0111..Correlate N+31 -> N+35 * 0b1000..Correlate N+36 -> N+39 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SHFT_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SHFT_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SHFT_SEL_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SRC_SEL_MASK (0x1C00U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SRC_SEL_SHIFT (10U) /*! STAT_SRC_SEL - Select Stat Source Input * 0b000..{20{rx_cal_result}} * 0b001..{{20{scope_data_rxclk_dly_s01}},{20{scope_data_rxclk_dly}}} * 0b010..rx_phase[39:0] * 0b011..rx_error[39:0] * 0b100..rx_data[39:0] * 0b101..rx_phdir[39:0] * 0b110..40'hFF_FFFF_FFFF */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SRC_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SRC_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_SRC_SEL_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_RXCLK_SEL_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_RXCLK_SEL_SHIFT (13U) /*! STAT_RXCLK_SEL - Select Stat Clock * 0b0..ref_range_clk * 0b1..rx_dig_clk (i.e. RX dword clk) */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_RXCLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_RXCLK_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_STAT_RXCLK_SEL_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SC_TIMER_MODE_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SC_TIMER_MODE_SHIFT (14U) /*! SC_TIMER_MODE - Sample Counter Operation Mode * 0b0..Counts number of matched samples * 0b1..Counts clock cycles (i.e. a timer) */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SC_TIMER_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SC_TIMER_MODE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SC_TIMER_MODE_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SKIP_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SKIP_EN_SHIFT (15U) /*! SKIP_EN - Value of skip_en_r */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SKIP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SKIP_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL0_SKIP_EN_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CTL1 - Stat Controls 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_0_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_0_EN_SHIFT (0U) /*! STAT_CNT_0_EN - Enable for stat counter 0 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_0_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_0_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_0_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_1_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_1_EN_SHIFT (1U) /*! STAT_CNT_1_EN - Enable for stat counter 1 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_1_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_1_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_1_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_2_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_2_EN_SHIFT (2U) /*! STAT_CNT_2_EN - Enable for stat counter 2 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_2_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_2_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_3_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_3_EN_SHIFT (3U) /*! STAT_CNT_3_EN - Enable for stat counter 3 Only counter to be enabled by default, since used for offset calibration * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_3_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_3_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_3_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_4_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_4_EN_SHIFT (4U) /*! STAT_CNT_4_EN - Enable for stat counter 4 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_4_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_4_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_4_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_5_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_5_EN_SHIFT (5U) /*! STAT_CNT_5_EN - Enable for stat counter 5 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_5_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_5_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_5_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_6_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_6_EN_SHIFT (6U) /*! STAT_CNT_6_EN - Enable for stat counter 6 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_6_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_6_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CNT_6_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_SC_PAUSE_MASK (0x200U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_SC_PAUSE_SHIFT (9U) /*! SC_PAUSE - Pause the sample counter and stat counters * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_SC_PAUSE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_SC_PAUSE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_SC_PAUSE_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CLK_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CLK_EN_SHIFT (10U) /*! STAT_CLK_EN - Clock gate enable for stat clock * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_STAT_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_DATA_DLY_SEL_MASK (0x1800U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_DATA_DLY_SEL_SHIFT (11U) /*! DATA_DLY_SEL - Number of clock cycle delays on rx_data[19:0] An additional MSB is added in DATA_DLY_SEL_2 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_DATA_DLY_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_DATA_DLY_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_DATA_DLY_SEL_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_LOSS_CLR_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_LOSS_CLR_SHIFT (13U) /*! VLD_LOSS_CLR - Clearing of Stats Collection upon Loss of Valid * 0b0..Hold sample and stat counters * 0b1..Clear sample and stat counters */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_LOSS_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_LOSS_CLR_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_LOSS_CLR_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_CTL_MASK (0xC000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_CTL_SHIFT (14U) /*! VLD_CTL - Gating Configuration of Stats Collection * 0b00..Ignore both cdr_valid and rx_valid * 0b01..Gate stats collection with cdr_valid * 0b10..Gate stats collection with rx_valid * 0b11..Ignore both cdr_valid and rx_valid */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_CTL_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL1_VLD_CTL_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_SMPL_CNT1 - Sample Counter 1 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_SHIFT (0U) /*! SMPL_CNT1 - Current value of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_SMPL_CNT1_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CNT_0 - Stat Counter 0 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_STAT_CNT_0_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_STAT_CNT_0_SHIFT (0U) /*! STAT_CNT_0 - Current value of stat counter 0 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_STAT_CNT_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_STAT_CNT_0_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_STAT_CNT_0_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_0_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CNT_1 - Stat Counter 1 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_STAT_CNT_1_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_STAT_CNT_1_SHIFT (0U) /*! STAT_CNT_1 - Current value of stat counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_STAT_CNT_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_STAT_CNT_1_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_STAT_CNT_1_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_1_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CNT_2 - Stat Counter 2 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_STAT_CNT_2_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_STAT_CNT_2_SHIFT (0U) /*! STAT_CNT_2 - Current value of stat counter 2 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_STAT_CNT_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_STAT_CNT_2_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_STAT_CNT_2_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_2_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CNT_3 - Stat Counter 3 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_STAT_CNT_3_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_STAT_CNT_3_SHIFT (0U) /*! STAT_CNT_3 - Current value of stat counter 3 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_STAT_CNT_3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_STAT_CNT_3_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_STAT_CNT_3_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_3_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CNT_4 - Stat Counter 4 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_STAT_CNT_4_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_STAT_CNT_4_SHIFT (0U) /*! STAT_CNT_4 - Current value of stat counter 4 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_STAT_CNT_4(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_STAT_CNT_4_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_STAT_CNT_4_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_4_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CNT_5 - Stat Counter 5 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_STAT_CNT_5_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_STAT_CNT_5_SHIFT (0U) /*! STAT_CNT_5 - Current value of stat counter 5 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_STAT_CNT_5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_STAT_CNT_5_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_STAT_CNT_5_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_5_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CNT_6 - Stat Counter 6 Status */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_STAT_CNT_6_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_STAT_CNT_6_SHIFT (0U) /*! STAT_CNT_6 - Current value of stat counter 6 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_STAT_CNT_6(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_STAT_CNT_6_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_STAT_CNT_6_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_SMPL_CNT1_DONE_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_SMPL_CNT1_DONE_SHIFT (15U) /*! SMPL_CNT1_DONE - Status of sample counter 1 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_SMPL_CNT1_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_SMPL_CNT1_DONE_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CNT_6_SMPL_CNT1_DONE_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL - Calibration Comparator Control */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_PRECHRGE_CNT_MASK (0x7U) #define ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_PRECHRGE_CNT_SHIFT (0U) /*! PRECHRGE_CNT - Precharge Count */ #define ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_PRECHRGE_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_PRECHRGE_CNT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_PRECHRGE_CNT_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_REF_DIV_CNT_MASK (0x38U) #define ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_REF_DIV_CNT_SHIFT (3U) /*! REF_DIV_CNT - Ref Range Clock Count */ #define ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_REF_DIV_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_REF_DIV_CNT_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_REF_DIV_CNT_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_MATCH_CTL2 - Stat Match Controls 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL2_PTTRN_CR1A_19_5_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL2_PTTRN_CR1A_19_5_SHIFT (0U) /*! PTTRN_CR1A_19_5 - Value of pattern A for 1st correlator (bits 19:5) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL2_PTTRN_CR1A_19_5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL2_PTTRN_CR1A_19_5_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL2_PTTRN_CR1A_19_5_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_MATCH_CTL3 - Stat Match Controls 3 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL3_PTTRN_MSK_CR1A_19_5_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL3_PTTRN_MSK_CR1A_19_5_SHIFT (0U) /*! PTTRN_MSK_CR1A_19_5 - Value of pattern A mask for 1st correlator (bits 19:5) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL3_PTTRN_MSK_CR1A_19_5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL3_PTTRN_MSK_CR1A_19_5_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL3_PTTRN_MSK_CR1A_19_5_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_MATCH_CTL4 - Stat Match Controls 4 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL4_PTTRN_CR1B_19_5_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL4_PTTRN_CR1B_19_5_SHIFT (0U) /*! PTTRN_CR1B_19_5 - Value of pattern B for 1st correlator (bits 19:5) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL4_PTTRN_CR1B_19_5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL4_PTTRN_CR1B_19_5_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL4_PTTRN_CR1B_19_5_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_MATCH_CTL5 - Stat Match Controls 5 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL5_PTTRN_MSK_CR1B_19_5_MASK (0x7FFFU) #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL5_PTTRN_MSK_CR1B_19_5_SHIFT (0U) /*! PTTRN_MSK_CR1B_19_5 - Value of pattern B mask for 1st correlator (bits 19:5) */ #define ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL5_PTTRN_MSK_CR1B_19_5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL5_PTTRN_MSK_CR1B_19_5_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_MATCH_CTL5_PTTRN_MSK_CR1B_19_5_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_CTL2 - Stat Controls 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_DATA_DLY_SEL_2_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_DATA_DLY_SEL_2_SHIFT (0U) /*! DATA_DLY_SEL_2 - Additional MSB bit for DATA_DLY_SEL to extend the delay range to 0 -> 7 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_DATA_DLY_SEL_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_DATA_DLY_SEL_2_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_DATA_DLY_SEL_2_MASK) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_SCOPE_DLY_2_MASK (0x2U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_SCOPE_DLY_2_SHIFT (1U) /*! SCOPE_DLY_2 - Additional MSB bit for SCOPE_DLY to extend the delay range to 0 -> 7 */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_SCOPE_DLY_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_SCOPE_DLY_2_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_CTL2_SCOPE_DLY_2_MASK) /*! @} */ /*! @name LANE0_DIG_RX_STAT_STAT_STOP - Stat Stop */ /*! @{ */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_STOP_SC1_STOP_MASK (0x1U) #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_STOP_SC1_STOP_SHIFT (0U) /*! SC1_STOP - Stop Sample Counters 1 and Associated Stat Counters * 0b0..Doesn't stop * 0b1..Stops */ #define ENET_PHY_LANE0_DIG_RX_STAT_STAT_STOP_SC1_STOP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_RX_STAT_STAT_STOP_SC1_STOP_SHIFT)) & ENET_PHY_LANE0_DIG_RX_STAT_STAT_STOP_SC1_STOP_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_OVRD_OUT - Override Values for TX Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_SHIFT_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_SHIFT_SHIFT (0U) /*! TX_ANA_CLK_SHIFT - Override Value for tx_ana_clk_shift * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_SHIFT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_SHIFT_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_SHIFT_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_EN_SHIFT (1U) /*! TX_ANA_DATA_EN - Override Value for tx_ana_data_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_REFGEN_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_REFGEN_EN_SHIFT (2U) /*! TX_ANA_REFGEN_EN - Override Value for tx_ana_refgen_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_REFGEN_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_REFGEN_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_REFGEN_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_VCM_HOLD_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_VCM_HOLD_SHIFT (3U) /*! TX_ANA_VCM_HOLD - Override Value for tx_ana_vcm_hold * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_VCM_HOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_VCM_HOLD_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_VCM_HOLD_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_EN_SHIFT (4U) /*! TX_ANA_CLK_EN - Override Value for tx_ana_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_WORD_CLK_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_WORD_CLK_EN_SHIFT (5U) /*! TX_ANA_WORD_CLK_EN - Override Value for tx_ana_word_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_WORD_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_WORD_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_WORD_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLA_CLK_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLA_CLK_EN_SHIFT (6U) /*! TX_ANA_MPLLA_CLK_EN - Override Value for tx_ana_mplla_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLB_CLK_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLB_CLK_EN_SHIFT (7U) /*! TX_ANA_MPLLB_CLK_EN - Override Value for tx_ana_mpllb_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLB_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLB_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_MPLLB_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_RESET_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_RESET_SHIFT (8U) /*! TX_ANA_RESET - Override Value for tx_ana_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_RESET_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_RESET_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_SERIAL_EN_MASK (0x200U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_SERIAL_EN_SHIFT (9U) /*! TX_ANA_SERIAL_EN - Override Value for tx_ana_serial_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_SERIAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_SERIAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_SERIAL_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_RATE_MASK (0x1C00U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_RATE_SHIFT (10U) /*! TX_ANA_DATA_RATE - Override Value for tx_ana_data_rate */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_RATE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_ANA_DATA_RATE_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_DIV4_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_DIV4_EN_SHIFT (13U) /*! TX_DIV4_EN - Override Value for tx_ana_div4_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_DIV4_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_DIV4_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_DIV4_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_RXDET_EN_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_RXDET_EN_SHIFT (14U) /*! TX_RXDET_EN - Override Value for tx_ana_rxdet_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_RXDET_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_RXDET_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_RXDET_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_OVRD_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_OVRD_EN_SHIFT (15U) /*! TX_OVRD_EN - Enable override values for all outputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_OVRD_OUT_TX_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT - Override Value for TX termination Code Up Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_CODEP_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_CODEP_SHIFT (0U) /*! TX_TERM_UP_CODEP - Overrides the tx_ana_term_code_up[9:0] signal */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_CODEP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_CODEP_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_CODEP_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_OVRD_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_OVRD_EN_SHIFT (10U) /*! TX_TERM_UP_OVRD_EN - Overrides enable for the tx_ana_term_code_up[9:0] signal * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_TERM_UP_OVRD_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_CLK_LB_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_CLK_LB_EN_SHIFT (11U) /*! TX_CLK_LB_EN - Override Value for tx_ana_clk_lb_en (override enabled by TX_OVRD_EN) * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_CLK_LB_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_CLK_LB_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_CLK_LB_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_ANA_VCM_HOLD_GS_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_ANA_VCM_HOLD_GS_SHIFT (12U) /*! TX_ANA_VCM_HOLD_GS - Override Value for tx_ana_vcm_hold_gs * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_ANA_VCM_HOLD_GS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_ANA_VCM_HOLD_GS_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_TX_ANA_VCM_HOLD_GS_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT - Override Value for TX termination Down Code Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_CODE_MASK (0x3FFU) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_CODE_SHIFT (0U) /*! TX_TERM_DN_CODE - Overrides the tx_ana_term_code_dn[9:0] signal */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_CODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_CODE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_CODE_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_OVRD_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_OVRD_EN_SHIFT (10U) /*! TX_TERM_DN_OVRD_EN - Overrides enable for the tx_ana_term_code_dn[9:0] signal * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_TX_TERM_DN_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0 - Override Values for TX EQ Signals Going to ANA 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_LOAD_CLK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_LOAD_CLK_SHIFT (0U) /*! TX_ANA_LOAD_CLK - Override Value for tx_ana_load_clk * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_LOAD_CLK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_LOAD_CLK_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_LOAD_CLK_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_CTRL_ATTEN_13_0_MASK (0x7FFEU) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_CTRL_ATTEN_13_0_SHIFT (1U) /*! TX_ANA_CTRL_ATTEN_13_0 - Override Value for tx_ana_ctrl_atten[13:0] */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_CTRL_ATTEN_13_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_CTRL_ATTEN_13_0_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_ANA_CTRL_ATTEN_13_0_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_EQ_OVRD_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_EQ_OVRD_EN_SHIFT (15U) /*! TX_EQ_OVRD_EN - Override Enable for TX EQ Signals * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_EQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_EQ_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_TX_EQ_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1 - Override Values for TX EQ Signals Going to ANA 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_TX_ANA_CTRL_ATTEN_29_14_MASK (0xFFFFU) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_TX_ANA_CTRL_ATTEN_29_14_SHIFT (0U) /*! TX_ANA_CTRL_ATTEN_29_14 - Override Value for tx_ana_ctrl_atten[29:14] */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_TX_ANA_CTRL_ATTEN_29_14(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_TX_ANA_CTRL_ATTEN_29_14_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_TX_ANA_CTRL_ATTEN_29_14_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2 - Override Values for TX EQ Signals Going to ANA 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_ATTEN_34_30_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_ATTEN_34_30_SHIFT (0U) /*! TX_ANA_CTRL_ATTEN_34_30 - Override Value for tx_ana_ctrl_atten[34:30] */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_ATTEN_34_30(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_ATTEN_34_30_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_ATTEN_34_30_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_UP_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_UP_SHIFT (5U) /*! TX_ANA_CTRL_HALF_UP - Override Value for tx_ana_ctrl_half_up * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_UP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_UP_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_UP_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_DN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_DN_SHIFT (6U) /*! TX_ANA_CTRL_HALF_DN - Override Value for tx_ana_ctrl_half_dn * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_DN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_DN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_HALF_DN_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_PRE_MASK (0xFF80U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_PRE_SHIFT (7U) /*! TX_ANA_CTRL_PRE - Override Value for tx_ana_ctrl_pre[8:0] */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_PRE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_PRE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_TX_ANA_CTRL_PRE_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3 - Override Values for TX EQ Signals Going to ANA 3 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_HALF_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_HALF_SHIFT (0U) /*! TX_ANA_CTRL_PRE_HALF - Override Value for tx_ana_ctrl_pre_half * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_HALF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_HALF_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_HALF_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_QTR_MASK (0x6U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_QTR_SHIFT (1U) /*! TX_ANA_CTRL_PRE_QTR - Override Value for tx_ana_ctrl_pre_qtr[1:0] */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_QTR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_QTR_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_PRE_QTR_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_HALF_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_HALF_SHIFT (3U) /*! TX_ANA_CTRL_POST_HALF - Override Value for tx_ana_ctrl_post_half * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_HALF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_HALF_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_HALF_MASK) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_QTR_MASK (0x30U) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_QTR_SHIFT (4U) /*! TX_ANA_CTRL_POST_QTR - Override Value for tx_ana_ctrl_post_qtr[1:0] */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_QTR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_QTR_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_TX_ANA_CTRL_POST_QTR_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4 - Override Values for TX EQ Signals Going to ANA 4 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_TX_ANA_CTRL_POST_MASK (0x3FFFU) #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_TX_ANA_CTRL_POST_SHIFT (0U) /*! TX_ANA_CTRL_POST - Override Value for tx_ana_ctrl_post[13:0] */ #define ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_TX_ANA_CTRL_POST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_TX_ANA_CTRL_POST_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_TX_ANA_CTRL_POST_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_CTL_OVRD_OUT - Override Values for RX Control Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV16P5_CLK_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV16P5_CLK_EN_SHIFT (0U) /*! RX_ANA_DIV16P5_CLK_EN - Override Value for rx_ana_div16p5_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DATA_RATE_MASK (0x6U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DATA_RATE_SHIFT (1U) /*! RX_ANA_DATA_RATE - Override Value for rx_ana_data_rate */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DATA_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DATA_RATE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DATA_RATE_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_WORD_CLK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_WORD_CLK_EN_SHIFT (3U) /*! RX_ANA_WORD_CLK_EN - Override Value for rx_ana_word_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_WORD_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_WORD_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_WORD_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV4_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV4_EN_SHIFT (4U) /*! RX_ANA_DIV4_EN - Override Value for rx_ana_div4_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV4_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV4_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DIV4_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_TAPS_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_TAPS_EN_SHIFT (5U) /*! RX_ANA_DFE_TAPS_EN - Override Value for rx_ana_dfe_taps_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_TAPS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_TAPS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_TAPS_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_BYPASS_N_MASK (0x40U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_BYPASS_N_SHIFT (6U) /*! RX_ANA_DFE_BYPASS_N - Override Value for rx_ana_dfe_bypass_n * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_BYPASS_N(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_BYPASS_N_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_ANA_DFE_BYPASS_N_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_LBK_CLK_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_LBK_CLK_EN_SHIFT (7U) /*! RX_LBK_CLK_EN - Override Value for rx_ana_loopback_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_LBK_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_LBK_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_LBK_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_CTL_OVRD_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_CTL_OVRD_EN_SHIFT (8U) /*! RX_CTL_OVRD_EN - Enable override values for outputs [8-0] below * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_CTL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_CTL_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_RX_CTL_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_PWR_OVRD_OUT - Override Values for RX PWR UP/DN Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_LOS_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_LOS_EN_SHIFT (0U) /*! RX_ANA_LOS_EN - Override Value for rx_ana_los_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_LOS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_LOS_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_LOS_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_AFE_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_AFE_EN_SHIFT (1U) /*! RX_ANA_AFE_EN - Override Value for rx_ana_afe_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_AFE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_AFE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_AFE_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_VREG_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_VREG_EN_SHIFT (2U) /*! RX_ANA_CLK_VREG_EN - Override Value for rx_ana_clk_vreg_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_VREG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_VREG_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_VREG_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_DCC_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_DCC_EN_SHIFT (3U) /*! RX_ANA_CLK_DCC_EN - Override Value for rx_ana_clk_dcc_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_DCC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_DCC_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_DCC_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_EN_SHIFT (4U) /*! RX_ANA_CLK_EN - Override Value for rx_ana_clk_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CLK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CDR_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CDR_EN_SHIFT (5U) /*! RX_ANA_CDR_EN - Override Value for rx_ana_cdr_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CDR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CDR_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_CDR_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_DESERIAL_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_DESERIAL_EN_SHIFT (6U) /*! RX_ANA_DESERIAL_EN - Override Value for rx_ana_deserial_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_DESERIAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_DESERIAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_ANA_DESERIAL_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_PWR_OVRD_EN_MASK (0x80U) #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_PWR_OVRD_EN_SHIFT (7U) /*! RX_PWR_OVRD_EN - Enable override values for all outputs controlled by this register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_PWR_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_PWR_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_RX_PWR_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0 - Override Values for RX VCO Signals Going to ANA 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_VCO_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_VCO_EN_SHIFT (0U) /*! RX_ANA_CDR_VCO_EN - Override Value for rx_ana_cdr_vco_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_VCO_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_VCO_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_VCO_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_STARTUP_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_STARTUP_SHIFT (1U) /*! RX_ANA_CDR_STARTUP - Override Value for rx_ana_cdr_startup * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_STARTUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_STARTUP_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_STARTUP_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_VCO_CDR_OVRD_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_VCO_CDR_OVRD_EN_SHIFT (2U) /*! RX_VCO_CDR_OVRD_EN - Enable override values for cdr_vco_en and cdr_startup * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_VCO_CDR_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_VCO_CDR_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_VCO_CDR_OVRD_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_MASK (0x1FF8U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_SHIFT (3U) /*! RX_ANA_CDR_FREQ_TUNE - Override Value for rx_ana_cdr_freq_tune */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_EN_MASK (0x2000U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_EN_SHIFT (13U) /*! RX_ANA_VCO_CNTR_EN - Override Value for rx_ana_vco_cntr_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_CLK_MASK (0x4000U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_CLK_SHIFT (14U) /*! RX_ANA_VCO_CNTR_CLK - Override Value for rx_ana_vco_cntr_clk * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_CLK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_CLK_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_VCO_CNTR_CLK_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN_SHIFT (15U) /*! RX_CDR_FREQ_TUNE_OVRD_EN - Enable override value for rx_ana_cdr_freq_tune * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1 - Override Values for RX VCO Signals Going to ANA 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_MASK (0x3U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_SHIFT (0U) /*! RX_ANA_CDR_VCO_FREQBAND - Override Value for rx_ana_cdr_vco_freqband */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_OVRD_EN_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_OVRD_EN_SHIFT (2U) /*! RX_ANA_CDR_VCO_FREQBAND_OVRD_EN - Override Enable for rx_ana_cdr_vco_freqband * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_FREQBAND_OVRD_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_PD_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_PD_SHIFT (3U) /*! RX_ANA_VCO_CNTR_PD - Override Value for rx_ana_vco_cntr_pd * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_PD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_PD_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_PD_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_OVER_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_OVER_EN_SHIFT (4U) /*! RX_ANA_VCO_CNTR_OVER_EN - Override Enable for rx_ana_vco_cntr_pd * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_OVER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_OVER_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_VCO_CNTR_OVER_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_EN_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_EN_SHIFT (5U) /*! RX_ANA_CDR_VCO_TEMP_COMP_EN - Override Value for rx_ana_cdr_vco_temp_comp * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_OVRD_EN_MASK (0x40U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_OVRD_EN_SHIFT (6U) /*! RX_ANA_CDR_VCO_TEMP_COMP_OVRD_EN - Override Enable for rx_ana_cdr_vco_temp_comp_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_TEMP_COMP_OVRD_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_MASK (0x80U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_SHIFT (7U) /*! RX_ANA_CDR_VCO_STEP_CTRL - Override Value for rx_ana_cdr_vco_step_ctrl * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_OVRD_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_OVRD_EN_SHIFT (8U) /*! RX_ANA_CDR_VCO_STEP_CTRL_OVRD_EN - Override Enable for rx_ana_cdr_vco_step_ctrl * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_RX_ANA_CDR_VCO_STEP_CTRL_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2 - Override Values for RX VCO Signals Going to ANA 2 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK_SHIFT (0U) /*! RX_ANA_CDR_FREQ_TUNE_CLK - Override Value for rx_ana_cdr_freq_tune_clk * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_CAL - Sets Values for RX CAL Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXA_SEL_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXA_SEL_SHIFT (0U) /*! RX_ANA_CAL_MUXA_SEL - Value for rx_ana_cal_muxa_sel[4:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXA_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXA_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXA_SEL_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXB_SEL_MASK (0x3E0U) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXB_SEL_SHIFT (5U) /*! RX_ANA_CAL_MUXB_SEL - Value for rx_ana_cal_muxb_sel[4:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXB_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MUXB_SEL_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_LPFBYP_EN_MASK (0x400U) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_LPFBYP_EN_SHIFT (10U) /*! RX_ANA_CAL_LPFBYP_EN - Value for rx_ana_cal_lpfbyp_en */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_LPFBYP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_LPFBYP_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_LPFBYP_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_SHORT_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_SHORT_EN_SHIFT (11U) /*! RX_ANA_CAL_SHORT_EN - Value for rx_ana_cal_short_en */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_SHORT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_SHORT_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_SHORT_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_SLICER_CAL_EN_MASK (0x1000U) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_SLICER_CAL_EN_SHIFT (12U) /*! RX_ANA_SLICER_CAL_EN - Value for rx_ana_slicer_cal_en */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_SLICER_CAL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_SLICER_CAL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_SLICER_CAL_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MODE_MASK (0x6000U) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MODE_SHIFT (13U) /*! RX_ANA_CAL_MODE - Value for rx_ana_cal_mode[1:0] * 0b00..Differential comparison * 0b01..Single-ended, positive node to positive node * 0b10..Single-ended, negative node to negative node * 0b11..Common mode comparison */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MODE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_MODE_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_COMP_EN_MASK (0x8000U) #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_COMP_EN_SHIFT (15U) /*! RX_ANA_CAL_COMP_EN - Value for rx_ana_cal_comp_en */ #define ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_COMP_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_CAL_RX_ANA_CAL_COMP_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_VDAC_RANGE_SEL - Sets Values for RX DAC CTRL Value Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_PRANGE_SEL_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_PRANGE_SEL_SHIFT (0U) /*! RX_ANA_CAL_VDAC_PRANGE_SEL - Value for rx_ana_cal_vdac_prange */ #define ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_PRANGE_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_PRANGE_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_PRANGE_SEL_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_DERANGE_SEL_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_DERANGE_SEL_SHIFT (1U) /*! RX_ANA_CAL_VDAC_DERANGE_SEL - Value for rx_ana_cal_vdac_derange */ #define ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_DERANGE_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_DERANGE_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_VDAC_RANGE_SEL_RX_ANA_CAL_VDAC_DERANGE_SEL_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_DAC_CTRL - Sets Values for RX DAC CTRL Value Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_RX_ANA_CAL_DAC_CTRL_MASK (0xFFU) #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_RX_ANA_CAL_DAC_CTRL_SHIFT (0U) /*! RX_ANA_CAL_DAC_CTRL - Value for rx_ana_cal_dac_ctrl[7:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_RX_ANA_CAL_DAC_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_RX_ANA_CAL_DAC_CTRL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_RX_ANA_CAL_DAC_CTRL_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_ANA_RTRIM - Set Value for RX RTRIM Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_VAL_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_VAL_SHIFT (0U) /*! RX_ANA_AFE_TRIM_OVRD_VAL - Override Value for rx_ana_afe_trim_ovrd_val * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_VAL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_VAL_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_EN_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_EN_SHIFT (1U) /*! RX_ANA_AFE_TRIM_OVRD_EN - Override enable rx_ana_afe_trim_ovrd_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_OVRD_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_THRESH_R_MASK (0xFCU) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_THRESH_R_SHIFT (2U) /*! RX_ANA_AFE_TRIM_THRESH_R - Threshold value for rx_ana_afe_trim */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_THRESH_R(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_THRESH_R_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_ANA_AFE_TRIM_THRESH_R_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_AFE_TRIM_EN_R_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_AFE_TRIM_EN_R_SHIFT (8U) /*! RX_AFE_TRIM_EN_R - Enable for signal rx_afe_trim_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_AFE_TRIM_EN_R(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_AFE_TRIM_EN_R_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_RTRIM_RX_AFE_TRIM_EN_R_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_DAC_CTRL_OVRD - Overrides RX DAC CTRL Bus (EN/VAL/SEL) Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_RX_CAL_DAC_CTRL_OVRD_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_RX_CAL_DAC_CTRL_OVRD_SHIFT (0U) /*! RX_CAL_DAC_CTRL_OVRD - Override Enable for Cal DAC Control * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_RX_CAL_DAC_CTRL_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_RX_CAL_DAC_CTRL_OVRD_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_RX_CAL_DAC_CTRL_OVRD_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_DAC_CTRL_SEL - Sets Values for RX DAC CTRL Select Signal Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_RX_ANA_CAL_DAC_CTRL_SEL_MASK (0x1FU) #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_RX_ANA_CAL_DAC_CTRL_SEL_SHIFT (0U) /*! RX_ANA_CAL_DAC_CTRL_SEL - Value for rx_ana_cal_dac_ctrl_sel[4:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_RX_ANA_CAL_DAC_CTRL_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_RX_ANA_CAL_DAC_CTRL_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_RX_ANA_CAL_DAC_CTRL_SEL_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_AFE_ATT_VGA - Value for RX AFE ATT & VGA Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_ATT_LVL_MASK (0x7U) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_ATT_LVL_SHIFT (0U) /*! RX_ANA_AFE_ATT_LVL - Value for rx_ana_afe_att_lvl[2:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_ATT_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_ATT_LVL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_ATT_LVL_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA1_GAIN_MASK (0x38U) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA1_GAIN_SHIFT (3U) /*! RX_ANA_AFE_VGA1_GAIN - Value for rx_ana_afe_vga1_gain[2:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA1_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA1_GAIN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA1_GAIN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA2_GAIN_MASK (0x1C0U) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA2_GAIN_SHIFT (6U) /*! RX_ANA_AFE_VGA2_GAIN - Value for rx_ana_afe_vga2_gain[2:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA2_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA2_GAIN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_ANA_AFE_VGA2_GAIN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_AFE_OVRD_EN_MASK (0x200U) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_AFE_OVRD_EN_SHIFT (9U) /*! RX_AFE_OVRD_EN - Override Enable for AFE Control * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_AFE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_AFE_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_AFE_ATT_VGA_RX_AFE_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_AFE_CTLE - Values for RX AFE CTLE Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_POLE_MASK (0x3U) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_POLE_SHIFT (0U) /*! RX_ANA_AFE_CTLE_POLE - Value for rx_ana_afe_ctle_pole[14:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_POLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_POLE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_POLE_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_BOOST_MASK (0x7CU) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_BOOST_SHIFT (2U) /*! RX_ANA_AFE_CTLE_BOOST - Value for rx_ana_afe_ctle_boost[30:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_BOOST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_BOOST_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_CTLE_BOOST_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_BIAS_MT_MASK (0x180U) #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_BIAS_MT_SHIFT (7U) /*! RX_ANA_AFE_BIAS_MT - Value for rx_ana_afe_bias_mt[1:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_BIAS_MT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_BIAS_MT_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_AFE_CTLE_RX_ANA_AFE_BIAS_MT_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_SCOPE - Values for RX SCOPE Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_EN_SHIFT (0U) /*! RX_ANA_SCOPE_EN - Sets value for rx_ana_scope_en * 0b0..Not set * 0b1..Set */ #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_SEL_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_SEL_SHIFT (1U) /*! RX_ANA_SCOPE_SEL - Sets value for rx_ana_scope_sel * 0b0..Not set * 0b1..Set */ #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_SEL_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_SEL_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PH_CLK_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PH_CLK_SHIFT (2U) /*! RX_ANA_SCOPE_PH_CLK - Sets Value for rx_ana_scope_ph_clk * 0b0..Not set * 0b1..Set */ #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PH_CLK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PH_CLK_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PH_CLK_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PHASE_MASK (0x7F8U) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PHASE_SHIFT (3U) /*! RX_ANA_SCOPE_PHASE - Sets value for rx_ana_scope_phase[7:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PHASE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PHASE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_PHASE_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_CLK_EN_MASK (0x800U) #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_CLK_EN_SHIFT (11U) /*! RX_ANA_SCOPE_CLK_EN - Enable the scope clocks going to the scope slicer and the lane digital part * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_CLK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SCOPE_RX_ANA_SCOPE_CLK_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_SLICER_CTRL - Sets Values for RX Slicer Ctrl Signals Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_E_MASK (0xFU) #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_E_SHIFT (0U) /*! RX_ANA_SLICER_CTRL_E - Value for rx_ana_slicer_ctrl_e[3:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_E(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_E_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_E_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_O_MASK (0xF0U) #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_O_SHIFT (4U) /*! RX_ANA_SLICER_CTRL_O - Value for rx_ana_slicer_ctrl_o[3:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_O(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_O_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_O_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_OVRD_EN_MASK (0x100U) #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_OVRD_EN_SHIFT (8U) /*! RX_ANA_SLICER_CTRL_OVRD_EN - Override Enable for RX ANA Slicer Control * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_OVRD_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_SLICER_CTRL_RX_ANA_SLICER_CTRL_OVRD_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST - Sets Values for RX ANA IQ PHASE Adjust Signal Going to ANA */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_RX_ANA_IQ_PHASE_ADJUST_MASK (0x7FU) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_RX_ANA_IQ_PHASE_ADJUST_SHIFT (0U) /*! RX_ANA_IQ_PHASE_ADJUST - Value for rx_ana_iq_phase_adjust[6:0] */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_RX_ANA_IQ_PHASE_ADJUST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_RX_ANA_IQ_PHASE_ADJUST_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_RX_ANA_IQ_PHASE_ADJUST_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN - Sets Values for RX ANA IQ SENSE Signal */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_RX_ANA_IQ_SENSE_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_RX_ANA_IQ_SENSE_EN_SHIFT (0U) /*! RX_ANA_IQ_SENSE_EN - Value for rx_ana_iq_sense_en */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_RX_ANA_IQ_SENSE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_RX_ANA_IQ_SENSE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_RX_ANA_IQ_SENSE_EN_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN - DAC Control Enable Signal */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_RX_ANA_CAL_DAC_CTRL_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_RX_ANA_CAL_DAC_CTRL_EN_SHIFT (0U) /*! RX_ANA_CAL_DAC_CTRL_EN - Value for rx_ana_cal_dac_ctrl_en */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_RX_ANA_CAL_DAC_CTRL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_RX_ANA_CAL_DAC_CTRL_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_RX_ANA_CAL_DAC_CTRL_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DAC_CTRL_SELF_CLEAR_DISABLE_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DAC_CTRL_SELF_CLEAR_DISABLE_SHIFT (1U) /*! DAC_CTRL_SELF_CLEAR_DISABLE - Disable self-clearing for the rx_ana_cal_dac_ctrl_en register * 0b0..Not disable * 0b1..Disable */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DAC_CTRL_SELF_CLEAR_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DAC_CTRL_SELF_CLEAR_DISABLE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DAC_CTRL_SELF_CLEAR_DISABLE_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE - AFE Update Enable Signal */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_RX_ANA_AFE_UPDATE_EN_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_RX_ANA_AFE_UPDATE_EN_SHIFT (0U) /*! RX_ANA_AFE_UPDATE_EN - Value for rx_ana_afe_update_en */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_RX_ANA_AFE_UPDATE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_RX_ANA_AFE_UPDATE_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_RX_ANA_AFE_UPDATE_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_AFE_UPDATE_SELF_CLEAR_DISABLE_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_AFE_UPDATE_SELF_CLEAR_DISABLE_SHIFT (1U) /*! AFE_UPDATE_SELF_CLEAR_DISABLE - Disable self-clearing for the rx_ana_afe_update_en register * 0b0..Not disable * 0b1..Disable */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_AFE_UPDATE_SELF_CLEAR_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_AFE_UPDATE_SELF_CLEAR_DISABLE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_AFE_UPDATE_SELF_CLEAR_DISABLE_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK - Phase Adjust Clock Signal */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_RX_ANA_IQ_PHASE_ADJUST_CLK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_RX_ANA_IQ_PHASE_ADJUST_CLK_SHIFT (0U) /*! RX_ANA_IQ_PHASE_ADJUST_CLK - Value for rx_ana_iq_phase_adjust_clk */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_RX_ANA_IQ_PHASE_ADJUST_CLK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_RX_ANA_IQ_PHASE_ADJUST_CLK_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_RX_ANA_IQ_PHASE_ADJUST_CLK_MASK) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_PHASE_ADJUST_SELF_CLEAR_DISABLE_SHIFT (1U) /*! PHASE_ADJUST_SELF_CLEAR_DISABLE - Disable self-clearing for the rx_ana_iq_phase_adjust_clk register * 0b0..Not disable * 0b1..Disable */ #define ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_PHASE_ADJUST_SELF_CLEAR_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_PHASE_ADJUST_SELF_CLEAR_DISABLE_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_STATUS_0 - Lane Input Status 0 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_SHIFT_ACK_MASK (0x1U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_SHIFT_ACK_SHIFT (0U) /*! TX_ANA_CLK_SHIFT_ACK - Value from ANA for tx_ana_clk_shift_ack */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_SHIFT_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_SHIFT_ACK_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_SHIFT_ACK_MASK) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETP_RESULT_MASK (0x2U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETP_RESULT_SHIFT (1U) /*! TX_ANA_RXDETP_RESULT - Value from ANA for tx_ana_rxdetp_result */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETP_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETP_RESULT_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETP_RESULT_MASK) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETM_RESULT_MASK (0x4U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETM_RESULT_SHIFT (2U) /*! TX_ANA_RXDETM_RESULT - Value from ANA for tx_ana_rxdetm_result */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETM_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETM_RESULT_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_RXDETM_RESULT_MASK) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_LOOPBACK_EN_MASK (0x8U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_LOOPBACK_EN_SHIFT (3U) /*! TX_ANA_LOOPBACK_EN - Value of tx_ana_loopback_en */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_LOOPBACK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_LOOPBACK_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_LOOPBACK_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_LB_EN_MASK (0x10U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_LB_EN_SHIFT (4U) /*! TX_ANA_CLK_LB_EN - Value of tx_ana_clk_lb_en */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_LB_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_LB_EN_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_TX_ANA_CLK_LB_EN_MASK) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_LOS_MASK (0x20U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_LOS_SHIFT (5U) /*! RX_ANA_LOS - Value from ANA for rx_ana_los */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_LOS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_LOS_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_LOS_MASK) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_CAL_RESULT_MASK (0x40U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_CAL_RESULT_SHIFT (6U) /*! RX_ANA_CAL_RESULT - Value from ANA for rx_ana_cal_result */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_CAL_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_CAL_RESULT_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_CAL_RESULT_MASK) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_SCOPE_DATA_MASK (0x80U) #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_SCOPE_DATA_SHIFT (7U) /*! RX_ANA_SCOPE_DATA - Value from ANA for rx_ana_scope_data */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_SCOPE_DATA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_SCOPE_DATA_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_0_RX_ANA_SCOPE_DATA_MASK) /*! @} */ /*! @name LANE0_DIG_ANA_STATUS_1 - Lane Input Status 1 */ /*! @{ */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_1_RX_ANA_VCO_CNTR_MASK (0x1FFFU) #define ENET_PHY_LANE0_DIG_ANA_STATUS_1_RX_ANA_VCO_CNTR_SHIFT (0U) /*! RX_ANA_VCO_CNTR - Value from ANA for rx_ana_vco_cntr */ #define ENET_PHY_LANE0_DIG_ANA_STATUS_1_RX_ANA_VCO_CNTR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_DIG_ANA_STATUS_1_RX_ANA_VCO_CNTR_SHIFT)) & ENET_PHY_LANE0_DIG_ANA_STATUS_1_RX_ANA_VCO_CNTR_MASK) /*! @} */ /*! @name LANE0_ANA_TX_OVRD_MEAS - TX_OVRD_MEAS */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_clk_shift_MASK (0x1U) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_clk_shift_SHIFT (0U) /*! ovrd_clk_shift - If asserted, allow analog register to control clock shift function */ #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_clk_shift(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_clk_shift_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_clk_shift_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_clk_shift_reg_MASK (0x2U) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_clk_shift_reg_SHIFT (1U) /*! clk_shift_reg - Controls clock shift if asserted with bit 0 */ #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_clk_shift_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_clk_shift_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_clk_shift_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_vcm_hold_MASK (0x10U) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_vcm_hold_SHIFT (4U) /*! ovrd_vcm_hold - If asserted, bit 5 takes effect on control TX common mode */ #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_vcm_hold(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_vcm_hold_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_ovrd_vcm_hold_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_vcm_hold_reg_MASK (0x20U) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_vcm_hold_reg_SHIFT (5U) /*! vcm_hold_reg - Set TX in common mode if asserted together with bit4 */ #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_vcm_hold_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_vcm_hold_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_vcm_hold_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_up_reg_MASK (0x40U) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_up_reg_SHIFT (6U) /*! pull_up_reg - Pull up TX output if asserted */ #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_up_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_up_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_up_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_dn_reg_MASK (0x80U) #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_dn_reg_SHIFT (7U) /*! pull_dn_reg - Pull down TX output if asserted */ #define ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_dn_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_dn_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_MEAS_pull_dn_reg_MASK) /*! @} */ /*! @name LANE0_ANA_TX_PWR_OVRD - TX_PWR_OVRD */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_tx_loopback_MASK (0x1U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_tx_loopback_SHIFT (0U) /*! ovrd_tx_loopback - Enables TX loopback mode over ridden by analog register if asserted * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_tx_loopback(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_tx_loopback_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_tx_loopback_MASK) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_loopback_en_reg_MASK (0x2U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_loopback_en_reg_SHIFT (1U) /*! loopback_en_reg - Enables TX loopback path to RX if asserted along with bit 0 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_loopback_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_loopback_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_loopback_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_refgen_en_reg_MASK (0x4U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_refgen_en_reg_SHIFT (2U) /*! refgen_en_reg - Enable TX biasing if asserted with bit 7 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_refgen_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_refgen_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_refgen_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_div_en_reg_MASK (0x8U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_div_en_reg_SHIFT (3U) /*! clk_div_en_reg - Enable TX divider if asserted with bit 7, overrides !tx_reset * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_div_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_div_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_div_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_data_en_reg_int_MASK (0x10U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_data_en_reg_int_SHIFT (4U) /*! data_en_reg_int - Enable TX driver data path if asserted with bit 7 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_data_en_reg_int(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_data_en_reg_int_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_data_en_reg_int_MASK) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_en_reg_MASK (0x20U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_en_reg_SHIFT (5U) /*! clk_en_reg - Enable TX clock if asserted with bit 7 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_clk_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_serial_en_reg_MASK (0x40U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_serial_en_reg_SHIFT (6U) /*! serial_en_reg - Enable TX serializer if asserted with bit 7 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_serial_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_serial_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_serial_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_en_MASK (0x80U) #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_en_SHIFT (7U) /*! ovrd_en - Enable analog register to take control TX power state if asserted * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_en_SHIFT)) & ENET_PHY_LANE0_ANA_TX_PWR_OVRD_ovrd_en_MASK) /*! @} */ /*! @name LANE0_ANA_TX_ALT_BUS - TX_ALT_BUS */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_drv_source_reg_MASK (0x3U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_drv_source_reg_SHIFT (0U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_drv_source_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_ALT_BUS_drv_source_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_ALT_BUS_drv_source_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_ovrd_alt_bus_MASK (0x4U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_ovrd_alt_bus_SHIFT (2U) /*! ovrd_alt_bus - JTAG data and TX data source selection function is controlled by bit[1:0] and 7 when asserted */ #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_ovrd_alt_bus(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_ALT_BUS_ovrd_alt_bus_SHIFT)) & ENET_PHY_LANE0_ANA_TX_ALT_BUS_ovrd_alt_bus_MASK) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vph_MASK (0x8U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vph_SHIFT (3U) /*! osc_vph - VPH powered I/O device ring oscillator outputs from TX when asserted */ #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vph(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vph_SHIFT)) & ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vph_MASK) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vptx_MASK (0x10U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vptx_SHIFT (4U) /*! osc_vptx - VPTX powered core device ring oscillator outputs from TX when asserted */ #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vptx(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vptx_SHIFT)) & ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vptx_MASK) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_lvt_MASK (0x20U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_lvt_SHIFT (5U) /*! osc_vp_lvt - VP powered low threshold core device ring oscillator outputs from TX when asserted */ #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_lvt(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_lvt_SHIFT)) & ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_lvt_MASK) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_MASK (0x40U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_SHIFT (6U) /*! osc_vp - VP powered high threshold core device ring oscillator outputs from TX when asserted */ #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_SHIFT)) & ENET_PHY_LANE0_ANA_TX_ALT_BUS_osc_vp_MASK) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_jtag_data_reg_MASK (0x80U) #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_jtag_data_reg_SHIFT (7U) /*! jtag_data_reg - When bit 2 is asserted, it replace JTAG data */ #define ENET_PHY_LANE0_ANA_TX_ALT_BUS_jtag_data_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_ALT_BUS_jtag_data_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_ALT_BUS_jtag_data_reg_MASK) /*! @} */ /*! @name LANE0_ANA_TX_VBOOST - TX_VBOOST */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_VBOOST_boost_vptx_mode_n_MASK (0x20U) #define ENET_PHY_LANE0_ANA_TX_VBOOST_boost_vptx_mode_n_SHIFT (5U) /*! boost_vptx_mode_n - If asserted, TX boost mode becomes a direct boost mode */ #define ENET_PHY_LANE0_ANA_TX_VBOOST_boost_vptx_mode_n(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_VBOOST_boost_vptx_mode_n_SHIFT)) & ENET_PHY_LANE0_ANA_TX_VBOOST_boost_vptx_mode_n_MASK) #define ENET_PHY_LANE0_ANA_TX_VBOOST_vboost_en_reg_MASK (0x40U) #define ENET_PHY_LANE0_ANA_TX_VBOOST_vboost_en_reg_SHIFT (6U) /*! vboost_en_reg - If bit 7 is set to 1, analog register takes control of TX vboost enable/disable */ #define ENET_PHY_LANE0_ANA_TX_VBOOST_vboost_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_VBOOST_vboost_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_VBOOST_vboost_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_VBOOST_ovrd_vboost_en_MASK (0x80U) #define ENET_PHY_LANE0_ANA_TX_VBOOST_ovrd_vboost_en_SHIFT (7U) /*! ovrd_vboost_en - Enable TX boost mode to be override by bit 6 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_VBOOST_ovrd_vboost_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_VBOOST_ovrd_vboost_en_SHIFT)) & ENET_PHY_LANE0_ANA_TX_VBOOST_ovrd_vboost_en_MASK) /*! @} */ /*! @name LANE0_ANA_TX_TERM_CODE_DN - TX_TERM_CODE_DN */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_ovrd_MASK (0x1U) #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_ovrd_SHIFT (0U) /*! term_code_dn_ovrd - Enable analog register to overdrive TX nmos leg biasing * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_ovrd(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_ovrd_SHIFT)) & ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_ovrd_MASK) #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_reg_MASK (0xFEU) #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_reg_SHIFT (1U) /*! term_code_dn_reg - TX nmos leg biasing register (7 MSBs),this is Term_code_dn_reg[9:3] */ #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_TERM_CODE_DN_term_code_dn_reg_MASK) /*! @} */ /*! @name LANE0_ANA_TX_TERM_CODE_UP - TX_TERM_CODE_UP */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_ovrd_MASK (0x1U) #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_ovrd_SHIFT (0U) /*! term_code_up_ovrd - Enable analog register to overdrive TX pmos leg biasing * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_ovrd(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_ovrd_SHIFT)) & ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_ovrd_MASK) #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_reg_MASK (0xFEU) #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_reg_SHIFT (1U) /*! term_code_up_reg - TX pmos leg biasing register (7 MSBs), this is Term_code_up_reg[9:3] */ #define ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_TERM_CODE_UP_term_code_up_reg_MASK) /*! @} */ /*! @name LANE0_ANA_TX_IBOOST_CODE - TX_IBOOST_CODE */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_lfps_high_priority_MASK (0x1U) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_lfps_high_priority_SHIFT (0U) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_lfps_high_priority(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_lfps_high_priority_SHIFT)) & ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_lfps_high_priority_MASK) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_up_reg_2_MASK (0x2U) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_up_reg_2_SHIFT (1U) /*! term_code_up_reg_2 - TX pmos leg biasing register bit 2, this is Term_code_up_reg[2] */ #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_up_reg_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_up_reg_2_SHIFT)) & ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_up_reg_2_MASK) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_dn_reg_2_MASK (0x4U) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_dn_reg_2_SHIFT (2U) /*! term_code_dn_reg_2 - TX nmos leg biasing register bit 2, this is Term_code_dn_reg[2] */ #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_dn_reg_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_dn_reg_2_SHIFT)) & ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_term_code_dn_reg_2_MASK) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_ovrd_MASK (0x8U) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_ovrd_SHIFT (3U) /*! iboost_code_ovrd - Enable analog register overdrive for TX boost * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_ovrd(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_ovrd_SHIFT)) & ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_ovrd_MASK) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_reg_MASK (0xF0U) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_reg_SHIFT (4U) #define ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_IBOOST_CODE_iboost_code_reg_MASK) /*! @} */ /*! @name LANE0_ANA_TX_OVRD_CLK - TX_OVRD_CLK */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_clk_lb_en_reg_MASK (0x2U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_clk_lb_en_reg_SHIFT (1U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_clk_lb_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_CLK_clk_lb_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_CLK_clk_lb_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_lb_en_MASK (0x4U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_lb_en_SHIFT (2U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_lb_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_lb_en_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_lb_en_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mpllb_clk_en_reg_MASK (0x8U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mpllb_clk_en_reg_SHIFT (3U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mpllb_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mpllb_clk_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mpllb_clk_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mplla_clk_en_reg_MASK (0x10U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mplla_clk_en_reg_SHIFT (4U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mplla_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mplla_clk_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_CLK_mplla_clk_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_mpllab_en_MASK (0x20U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_mpllab_en_SHIFT (5U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_mpllab_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_mpllab_en_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_mpllab_en_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_word_clk_en_reg_MASK (0x40U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_word_clk_en_reg_SHIFT (6U) /*! word_clk_en_reg - TX word clock enable/disable when bit 7 is asserted * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_word_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_CLK_word_clk_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_CLK_word_clk_en_reg_MASK) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_word_clk_en_MASK (0x80U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_word_clk_en_SHIFT (7U) #define ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_word_clk_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_word_clk_en_SHIFT)) & ENET_PHY_LANE0_ANA_TX_OVRD_CLK_ovrd_word_clk_en_MASK) /*! @} */ /*! @name LANE0_ANA_TX_MISC - TX_MISC */ /*! @{ */ #define ENET_PHY_LANE0_ANA_TX_MISC_osc_pmos_MASK (0x10U) #define ENET_PHY_LANE0_ANA_TX_MISC_osc_pmos_SHIFT (4U) /*! osc_pmos - PMOS device ring oscillator outputs from TX when asserted */ #define ENET_PHY_LANE0_ANA_TX_MISC_osc_pmos(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_MISC_osc_pmos_SHIFT)) & ENET_PHY_LANE0_ANA_TX_MISC_osc_pmos_MASK) #define ENET_PHY_LANE0_ANA_TX_MISC_osc_nmos_MASK (0x20U) #define ENET_PHY_LANE0_ANA_TX_MISC_osc_nmos_SHIFT (5U) /*! osc_nmos - NMOS device ring oscillator outputs from TX when asserted */ #define ENET_PHY_LANE0_ANA_TX_MISC_osc_nmos(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_TX_MISC_osc_nmos_SHIFT)) & ENET_PHY_LANE0_ANA_TX_MISC_osc_nmos_MASK) /*! @} */ /*! @name LANE0_ANA_RX_DCC_OVRD - RX_DCC_OVRD */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_afe_rate_reg_MASK (0x3U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_afe_rate_reg_SHIFT (0U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_afe_rate_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_DCC_OVRD_afe_rate_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_DCC_OVRD_afe_rate_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_word_clk_en_MASK (0x10U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_word_clk_en_SHIFT (4U) /*! ovrd_word_clk_en - RX word clock enable/disable when bit 5 is asserted * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_word_clk_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_word_clk_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_word_clk_en_MASK) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_word_clk_en_reg_MASK (0x20U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_word_clk_en_reg_SHIFT (5U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_word_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_DCC_OVRD_word_clk_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_DCC_OVRD_word_clk_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_dccandafe_en_MASK (0x40U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_dccandafe_en_SHIFT (6U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_dccandafe_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_dccandafe_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_DCC_OVRD_ovrd_dccandafe_en_MASK) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_dcc_en_reg_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_dcc_en_reg_SHIFT (7U) #define ENET_PHY_LANE0_ANA_RX_DCC_OVRD_dcc_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_DCC_OVRD_dcc_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_DCC_OVRD_dcc_en_reg_MASK) /*! @} */ /*! @name LANE0_ANA_RX_PWR_CTRL1 - RX_PWR_CTRL1 */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_acjt_en_MASK (0x1U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_acjt_en_SHIFT (0U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_acjt_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_acjt_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_acjt_en_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_acjt_en_reg_MASK (0x2U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_acjt_en_reg_SHIFT (1U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_acjt_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_acjt_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_acjt_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_clk_en_MASK (0x4U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_clk_en_SHIFT (2U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_clk_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_clk_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_clk_en_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_clk_en_reg_MASK (0x8U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_clk_en_reg_SHIFT (3U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_clk_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_clk_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_los_en_MASK (0x10U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_los_en_SHIFT (4U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_los_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_los_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_los_en_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_los_en_reg_MASK (0x20U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_los_en_reg_SHIFT (5U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_los_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_los_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_los_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_pwron_MASK (0x40U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_pwron_SHIFT (6U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_pwron(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_pwron_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_ovrd_pwron_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_pwron_reg_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_pwron_reg_SHIFT (7U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_pwron_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_pwron_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL1_pwron_reg_MASK) /*! @} */ /*! @name LANE0_ANA_RX_CDR_AFE - RX_CDR_AFE */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_odd_reg_MASK (0x40U) #define ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_odd_reg_SHIFT (6U) /*! phdet_odd_reg - If asserted, CDR phase detector uses odd data path */ #define ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_odd_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_odd_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_odd_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_even_reg_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_even_reg_SHIFT (7U) /*! phdet_even_reg - If asserted, CDR phase detector uses even data path */ #define ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_even_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_even_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CDR_AFE_phdet_even_reg_MASK) /*! @} */ /*! @name LANE0_ANA_RX_PWR_CTRL2 - RX_PWR_CTRL2 */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_afe_bias_cc_MASK (0x3U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_afe_bias_cc_SHIFT (0U) /*! afe_bias_cc - Setting of the biasing current for neg-c peaking circuit in AFE */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_afe_bias_cc(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_afe_bias_cc_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_afe_bias_cc_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_dfe_en_MASK (0x4U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_dfe_en_SHIFT (2U) /*! ovrd_dfe_en - If asserted, bit 3 takes control of RX DFE enable/disable */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_dfe_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_dfe_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_dfe_en_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_dfe_en_reg_MASK (0x8U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_dfe_en_reg_SHIFT (3U) /*! dfe_en_reg - If asserted with bit 2, enables RX DFE */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_dfe_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_dfe_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_dfe_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_des_en_MASK (0x10U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_des_en_SHIFT (4U) /*! ovrd_des_en - If asserted, bit 5 takes control of RX deserializer enable/disable */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_des_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_des_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_des_en_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_deserial_en_reg_MASK (0x20U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_deserial_en_reg_SHIFT (5U) /*! deserial_en_reg - If asserted with bit 4, enables RX deserializer */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_deserial_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_deserial_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_deserial_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_loopback_en_MASK (0x40U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_loopback_en_SHIFT (6U) /*! ovrd_loopback_en - If asserted, bit 7 takes control of TX to RX data loopback enable/disable */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_loopback_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_loopback_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_ovrd_loopback_en_MASK) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_loopback_en_reg_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_loopback_en_reg_SHIFT (7U) /*! loopback_en_reg - If asserted with bit 6, enables TX to RX data loopback */ #define ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_loopback_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_loopback_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_PWR_CTRL2_loopback_en_reg_MASK) /*! @} */ /*! @name LANE0_ANA_RX_MISC_OVRD - RX_MISC_OVRD */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_loopback_clk_en_MASK (0x1U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_loopback_clk_en_SHIFT (0U) /*! ovrd_rx_loopback_clk_en - Overrides loopback en from digital and selects loopback_clk_en from regs * 0b0..No override * 0b1..Override */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_loopback_clk_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_loopback_clk_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_loopback_clk_en_MASK) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_loopback_clk_en_reg_MASK (0x2U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_loopback_clk_en_reg_SHIFT (1U) /*! rx_loopback_clk_en_reg - Loopback Clock Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_loopback_clk_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_loopback_clk_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_loopback_clk_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_loopback_clk_sel_reg_MASK (0x4U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_loopback_clk_sel_reg_SHIFT (2U) /*! loopback_clk_sel_reg - Selects b/w and qv phase for loopback clocks */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_loopback_clk_sel_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_loopback_clk_sel_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_loopback_clk_sel_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_afe_ibias_inc_0_MASK (0x8U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_afe_ibias_inc_0_SHIFT (3U) /*! afe_ibias_inc_0 - Bit 0 of the two bit control of the AFE main bias currents */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_afe_ibias_inc_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_afe_ibias_inc_0_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_afe_ibias_inc_0_MASK) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_los_lfps_en_reg_MASK (0x10U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_los_lfps_en_reg_SHIFT (4U) /*! rx_los_lfps_en_reg - If asserted with bit 5, enables true LFPS detection */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_los_lfps_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_los_lfps_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_rx_los_lfps_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_los_lfps_en_MASK (0x20U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_los_lfps_en_SHIFT (5U) /*! ovrd_rx_los_lfps_en - If asserted, bit 4 enable/disables RX true LFPS detection */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_los_lfps_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_los_lfps_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_rx_los_lfps_en_MASK) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_shor_en_reg_MASK (0x40U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_shor_en_reg_SHIFT (6U) /*! shor_en_reg - If asserted with bit 7, RX input is shorted */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_shor_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_shor_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_shor_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_short_en_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_short_en_SHIFT (7U) /*! ovrd_short_en - If asserted, bit 6 enable/disables RX front short function */ #define ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_short_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_short_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_MISC_OVRD_ovrd_short_en_MASK) /*! @} */ /*! @name LANE0_ANA_RX_CAL_MUXA - RX_CAL_MUXA */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXA_cal_muxa_sel_reg_MASK (0x7CU) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXA_cal_muxa_sel_reg_SHIFT (2U) /*! cal_muxa_sel_reg - Analog Registers to Control RX Calibration Path A */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXA_cal_muxa_sel_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CAL_MUXA_cal_muxa_sel_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CAL_MUXA_cal_muxa_sel_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXA_ovrd_cal_muxa_sel_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXA_ovrd_cal_muxa_sel_SHIFT (7U) /*! ovrd_cal_muxa_sel - If asserted, selects analog register setting to control RX calibration path A */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXA_ovrd_cal_muxa_sel(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CAL_MUXA_ovrd_cal_muxa_sel_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CAL_MUXA_ovrd_cal_muxa_sel_MASK) /*! @} */ /*! @name LANE0_ANA_RX_CAL_MUXB - RX_CAL_MUXB */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_dfe_taps_en_reg_MASK (0x1U) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_dfe_taps_en_reg_SHIFT (0U) /*! dfe_taps_en_reg - If bit 1 is asserted, controls DFE tap2 to tap5 */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_dfe_taps_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CAL_MUXB_dfe_taps_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CAL_MUXB_dfe_taps_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_pwron_taps_MASK (0x2U) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_pwron_taps_SHIFT (1U) /*! ovrd_pwron_taps - If 1, allows for bit 0 to control DFE tap2 to tap5 currents */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_pwron_taps(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_pwron_taps_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_pwron_taps_MASK) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_cal_muxb_sel_reg_MASK (0x7CU) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_cal_muxb_sel_reg_SHIFT (2U) /*! cal_muxb_sel_reg - Analog Registers to Control RX Calibration Path B */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_cal_muxb_sel_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CAL_MUXB_cal_muxb_sel_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CAL_MUXB_cal_muxb_sel_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_cal_muxb_sel_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_cal_muxb_sel_SHIFT (7U) /*! ovrd_cal_muxb_sel - If asserted, selects analog register setting to control RX calibration path B */ #define ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_cal_muxb_sel(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_cal_muxb_sel_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CAL_MUXB_ovrd_cal_muxb_sel_MASK) /*! @} */ /*! @name LANE0_ANA_RX_TERM - RX_TERM */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_TERM_afe_att_cm_regs_MASK (0x3U) #define ENET_PHY_LANE0_ANA_RX_TERM_afe_att_cm_regs_SHIFT (0U) /*! afe_att_cm_regs - 2 bit control of the vcm_eq voltage to be used as the ATT common mode reference voltage */ #define ENET_PHY_LANE0_ANA_RX_TERM_afe_att_cm_regs(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_TERM_afe_att_cm_regs_SHIFT)) & ENET_PHY_LANE0_ANA_RX_TERM_afe_att_cm_regs_MASK) #define ENET_PHY_LANE0_ANA_RX_TERM_afe_ibias_inc_1_MASK (0x4U) #define ENET_PHY_LANE0_ANA_RX_TERM_afe_ibias_inc_1_SHIFT (2U) /*! afe_ibias_inc_1 - Bit 1 of the two bit control of the AFE main bias currents */ #define ENET_PHY_LANE0_ANA_RX_TERM_afe_ibias_inc_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_TERM_afe_ibias_inc_1_SHIFT)) & ENET_PHY_LANE0_ANA_RX_TERM_afe_ibias_inc_1_MASK) #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_iq_phase_adjust_MASK (0x8U) #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_iq_phase_adjust_SHIFT (3U) /*! ovrd_iq_phase_adjust - If asserted the iq_phase_adjust value is controlled via registers */ #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_iq_phase_adjust(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_TERM_ovrd_iq_phase_adjust_SHIFT)) & ENET_PHY_LANE0_ANA_RX_TERM_ovrd_iq_phase_adjust_MASK) #define ENET_PHY_LANE0_ANA_RX_TERM_rx_term_gd_en_reg_MASK (0x10U) #define ENET_PHY_LANE0_ANA_RX_TERM_rx_term_gd_en_reg_SHIFT (4U) /*! rx_term_gd_en_reg - If termination override is asserted, controls the ground termination enable */ #define ENET_PHY_LANE0_ANA_RX_TERM_rx_term_gd_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_TERM_rx_term_gd_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_TERM_rx_term_gd_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_gd_en_MASK (0x20U) #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_gd_en_SHIFT (5U) /*! ovrd_rx_term_gd_en - If asserted the ground termination enable value is controlled via registers */ #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_gd_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_gd_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_gd_en_MASK) #define ENET_PHY_LANE0_ANA_RX_TERM_rx_term_dc_en_reg_MASK (0x40U) #define ENET_PHY_LANE0_ANA_RX_TERM_rx_term_dc_en_reg_SHIFT (6U) /*! rx_term_dc_en_reg - If termination override is asserted, controls the DC termination enable */ #define ENET_PHY_LANE0_ANA_RX_TERM_rx_term_dc_en_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_TERM_rx_term_dc_en_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_TERM_rx_term_dc_en_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_dc_en_MASK (0x80U) #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_dc_en_SHIFT (7U) /*! ovrd_rx_term_dc_en - If asserted the DC termination enable value is controlled via registers */ #define ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_dc_en(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_dc_en_SHIFT)) & ENET_PHY_LANE0_ANA_RX_TERM_ovrd_rx_term_dc_en_MASK) /*! @} */ /*! @name LANE0_ANA_RX_SLC_CTRL - RX_SLC_CTRL */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_o_reg_MASK (0xFU) #define ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_o_reg_SHIFT (0U) /*! rx_slicer_ctrl_o_reg - If ovrd_rx_slicer_ctrl_reg is asserted, controls the odd slicer configuration */ #define ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_o_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_o_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_o_reg_MASK) #define ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_e_reg_MASK (0xF0U) #define ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_e_reg_SHIFT (4U) /*! rx_slicer_ctrl_e_reg - If ovrd_rx_slicer_ctrl_reg is asserted, controls the even slicer configuration */ #define ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_e_reg(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_e_reg_SHIFT)) & ENET_PHY_LANE0_ANA_RX_SLC_CTRL_rx_slicer_ctrl_e_reg_MASK) /*! @} */ /*! @name LANE0_ANA_RX_CDR_VCO_CTRL - RX_CDR_VCO_CTRL */ /*! @{ */ #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_afe_att_cm_regs_ovrd_MASK (0x1U) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_afe_att_cm_regs_ovrd_SHIFT (0U) /*! afe_att_cm_regs_ovrd - If asserted, the rx_misc[4:3] is overridden by the afe_att_cm_regs for setting the vcm_eq level */ #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_afe_att_cm_regs_ovrd(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_afe_att_cm_regs_ovrd_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_afe_att_cm_regs_ovrd_MASK) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_rx_vco_vreg_bypass_MASK (0x2U) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_rx_vco_vreg_bypass_SHIFT (1U) /*! creg_rx_vco_vreg_bypass - Forces vreg_rx_vco to vph (regulator bypass) when asserted */ #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_rx_vco_vreg_bypass(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_rx_vco_vreg_bypass_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_rx_vco_vreg_bypass_MASK) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_lowfreq_MASK (0xCU) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_lowfreq_SHIFT (2U) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_lowfreq(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_lowfreq_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_lowfreq_MASK) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_misc_ctrl_MASK (0xF0U) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_misc_ctrl_SHIFT (4U) #define ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_misc_ctrl(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_misc_ctrl_SHIFT)) & ENET_PHY_LANE0_ANA_RX_CDR_VCO_CTRL_creg_cdr_vco_misc_ctrl_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_TX_OVRD_IN - Override Values for Incoming TX Controls from PCS */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_PSTATE_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_PSTATE_SHIFT (0U) /*! PSTATE - Override Value for tx_pstate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_PSTATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_PSTATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_LPD_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_LPD_SHIFT (2U) /*! LPD - Override Value for tx_lpd * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_LPD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_LPD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_WIDTH_MASK (0x18U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_WIDTH_SHIFT (3U) /*! WIDTH - Override Value for tx_width */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_WIDTH_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_WIDTH_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_RATE_MASK (0xE0U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_RATE_SHIFT (5U) /*! RATE - Override Value for tx_rate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_RATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_RATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLLB_SEL_MASK (0x100U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLLB_SEL_SHIFT (8U) /*! MPLLB_SEL - Override Value for tx_mpllb_sel * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLLB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLLB_SEL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLLB_SEL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLL_EN_MASK (0x200U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLL_EN_SHIFT (9U) /*! MPLL_EN - Override Value for tx_mpll_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLL_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MPLL_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_MASK (0x400U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_SHIFT (10U) /*! MSTR_MPLLA_STATE - Override Value for tx_master_mplla_state * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_MASK (0x800U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_SHIFT (11U) /*! MSTR_MPLLB_STATE - Override Value for tx_master_mpllb_state * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_OVRD_EN_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_OVRD_EN_SHIFT (12U) /*! OVRD_EN - Override Enable for All Input Signals Below * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_OVRD_EN_MASK (0x2000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_OVRD_EN_SHIFT (13U) /*! MSTR_MPLLA_STATE_OVRD_EN - Override Enable for tx_master_mplla_state * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLA_STATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_OVRD_EN_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_OVRD_EN_SHIFT (14U) /*! MSTR_MPLLB_STATE_OVRD_EN - Override Enable for tx_master_mpllb_state * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_MSTR_MPLLB_STATE_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1 - Override Values for Incoming TX Controls from PCS 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_VAL_SHIFT (0U) /*! RESET_OVRD_VAL - Override Value for tx_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_EN_SHIFT (1U) /*! RESET_OVRD_EN - Override Enable for tx_reset * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_RESET_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_VAL_SHIFT (2U) /*! REQ_OVRD_VAL - Override Value for tx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_EN_SHIFT (3U) /*! REQ_OVRD_EN - Override Enable for tx_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_REQ_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_VAL_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_VAL_SHIFT (4U) /*! DETRX_REQ_OVRD_VAL - Override Value for tx_detrx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_EN_MASK (0x20U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_EN_SHIFT (5U) /*! DETRX_REQ_OVRD_EN - Override Enable for tx_detrx_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DETRX_REQ_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_VAL_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_VAL_SHIFT (6U) /*! VBOOST_EN_OVRD_VAL - Override Value for tx_vboost_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_EN_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_EN_SHIFT (7U) /*! VBOOST_EN_OVRD_EN - Override Enable for tx_vboost_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_VBOOST_EN_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_VAL_MASK (0xF00U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_VAL_SHIFT (8U) /*! IBOOST_LVL_OVRD_VAL - Override Value for tx_iboost_lvl[3:0] */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_EN_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_EN_SHIFT (12U) /*! IBOOST_LVL_OVRD_EN - Override Enable for tx_iboost_lvl[3:0] * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_IBOOST_LVL_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_TX_PCS_IN - Current Values for Incoming TX Controls from PCS (Pre-Override Input Monitor) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RESET_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RESET_SHIFT (0U) /*! RESET - Value from PCS for tx_reset */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RESET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RESET_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_REQ_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_REQ_SHIFT (1U) /*! REQ - Value from PCS for tx_req */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_REQ_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_PSTATE_MASK (0xCU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_PSTATE_SHIFT (2U) /*! PSTATE - Value from PCS for tx_pstate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_PSTATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_PSTATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_LPD_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_LPD_SHIFT (4U) /*! LPD - Value from PCS for tx_lpd */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_LPD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_LPD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_WIDTH_MASK (0x60U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_WIDTH_SHIFT (5U) /*! WIDTH - Value from PCS for tx_width */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_WIDTH_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_WIDTH_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RATE_MASK (0x380U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RATE_SHIFT (7U) /*! RATE - Value from PCS for tx_rate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_RATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLLB_SEL_MASK (0x400U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLLB_SEL_SHIFT (10U) /*! MPLLB_SEL - Value from PCS for tx_mpllb_sel */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLLB_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLLB_SEL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLLB_SEL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLL_EN_MASK (0x800U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLL_EN_SHIFT (11U) /*! MPLL_EN - Value from PCS for tx_mpll_en */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLL_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLL_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MPLL_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLB_STATE_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLB_STATE_SHIFT (12U) /*! MSTR_MPLLB_STATE - Value from PCS for tx_master_mpllb_state */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLB_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLB_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLB_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLA_STATE_MASK (0x2000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLA_STATE_SHIFT (13U) /*! MSTR_MPLLA_STATE - Value from PCS for tx_master_mplla_state */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLA_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLA_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_MSTR_MPLLA_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DETRX_REQ_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DETRX_REQ_SHIFT (14U) /*! DETRX_REQ - Value from PCS for tx_detrx_req */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DETRX_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DETRX_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DETRX_REQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT - Override Values for Outgoing TX Controls to PCS */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_ACK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_ACK_SHIFT (0U) /*! ACK - Override Value for tx_ack * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_ACK_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DETRX_RESULT_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DETRX_RESULT_SHIFT (1U) /*! DETRX_RESULT - Override Value for tx_detrx_result * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DETRX_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DETRX_RESULT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DETRX_RESULT_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_EN_CTL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_EN_CTL_SHIFT (2U) /*! EN_CTL - Enable Override Values for All Control Outputs of this Register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_EN_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_EN_CTL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_EN_CTL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_TX_PCS_OUT - Current Values for Outgoing TX Status Controls from Raw PCS (Pre-Override Output Monitor) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_ACK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_ACK_SHIFT (0U) /*! ACK - Value from Raw PCS for tx_ack */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_ACK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_IN - Override Values for Incoming RX Controls from PCS */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_RATE_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_RATE_SHIFT (0U) /*! RATE - Override Value for rx_rate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_RATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_RATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_WIDTH_MASK (0xCU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_WIDTH_SHIFT (2U) /*! WIDTH - Override Value for rx_width */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_WIDTH_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_WIDTH_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_PSTATE_MASK (0x30U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_PSTATE_SHIFT (4U) /*! PSTATE - Override Value for rx_pstate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_PSTATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_PSTATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_LPD_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_LPD_SHIFT (6U) /*! LPD - Override Value for rx_lpd * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_LPD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_LPD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_OVRD_EN_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_OVRD_EN_SHIFT (7U) /*! OVRD_EN - Enable Override Values for All Fields in this Register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DFE_BYPASS_MASK (0x100U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DFE_BYPASS_SHIFT (8U) /*! DFE_BYPASS - Override Value for rx_dfe_bypass * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DFE_BYPASS_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DFE_BYPASS_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1 - Override Values for Incoming RX Controls from PCS 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_VAL_SHIFT (0U) /*! RESET_OVRD_VAL - Override Value for rx_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_EN_SHIFT (1U) /*! RESET_OVRD_EN - Override Enable for rx_reset * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_RESET_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_VAL_SHIFT (2U) /*! REQ_OVRD_VAL - Override Value for rx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_EN_SHIFT (3U) /*! REQ_OVRD_EN - Override Enable for rx_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_REQ_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2 - Override Values for Incoming RX Controls from PCS 2 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_MASK (0x1FFFU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_SHIFT (0U) /*! VCO_LD_VAL_OVRD - Override Value for rx_vco_ld_val */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_EN_MASK (0x2000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_EN_SHIFT (13U) /*! VCO_LD_VAL_OVRD_EN - Enable Override for rx_vco_ld_val * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_VCO_LD_VAL_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2 - ATE Override Input to Control Top-Level Inputs 3 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_VAL_MASK (0x7U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_VAL_SHIFT (0U) /*! RX_LOS_THRSHLD_OVRD_VAL - Override Value for rx_los_threshold */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_EN_SHIFT (3U) /*! RX_LOS_THRSHLD_OVRD_EN - Enable Override for rx_los_threshold * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_RX_LOS_THRSHLD_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_SHIFT (4U) /*! ADAPT_REQ - Override Value for rx_adapt_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_OVRD_EN_MASK (0x20U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_OVRD_EN_SHIFT (5U) /*! ADAPT_REQ_OVRD_EN - Enable Override Values for rx_adapt_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_REQ_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_CONT_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_CONT_SHIFT (6U) /*! ADAPT_CONT - Override Value for rx_adapt_cont * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_ADAPT_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_OFFCAN_CONT_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_OFFCAN_CONT_SHIFT (7U) /*! OFFCAN_CONT - Override Value for rx_offcan_cont * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_OFFCAN_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_OFFCAN_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_OFFCAN_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_CONT_OVRD_EN_MASK (0x100U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_CONT_OVRD_EN_SHIFT (8U) /*! CONT_OVRD_EN - Enable Override Values for rx_adapt_cont and rx_offcan_cont * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_CONT_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_CONT_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_2_CONT_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_IN - Current Values for Incoming RX Controls from PCS (Monitor on Post ATE Override) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_REQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_REQ_SHIFT (0U) /*! REQ - Value from PCS for rx_req */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_REQ_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RATE_MASK (0x6U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RATE_SHIFT (1U) /*! RATE - Value from PCS for rx_rate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_WIDTH_MASK (0x18U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_WIDTH_SHIFT (3U) /*! WIDTH - Value from PCS for rx_width */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_WIDTH_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_WIDTH_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_PSTATE_MASK (0x60U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_PSTATE_SHIFT (5U) /*! PSTATE - Value from PCS for rx_pstate */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_PSTATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_PSTATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_LPD_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_LPD_SHIFT (7U) /*! LPD - Value from PCS for rx_lpd */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_LPD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_LPD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_LPD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_CDR_VCO_FREQBAND_MASK (0x300U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_CDR_VCO_FREQBAND_SHIFT (8U) /*! CDR_VCO_FREQBAND - Value from PCS for rx_cdr_vco_freqband */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_CDR_VCO_FREQBAND(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_CDR_VCO_FREQBAND_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_CDR_VCO_FREQBAND_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RX_DFE_BYPASS_MASK (0x400U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RX_DFE_BYPASS_SHIFT (10U) /*! RX_DFE_BYPASS - Value from PCS for rx_dfe_bypass */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RX_DFE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RX_DFE_BYPASS_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RX_DFE_BYPASS_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_REQ_MASK (0x800U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_REQ_SHIFT (11U) /*! ADAPT_REQ - Value from PCS for rx_adapt_req */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_REQ_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_CONT_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_CONT_SHIFT (12U) /*! ADAPT_CONT - Value from PCS for rx_adapt_cont */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_ADAPT_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_OFFCAN_CONT_MASK (0x2000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_OFFCAN_CONT_SHIFT (13U) /*! OFFCAN_CONT - Value from PCS for rx_offcan_cont */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_OFFCAN_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_OFFCAN_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_OFFCAN_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RESET_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RESET_SHIFT (14U) /*! RESET - Value from PCS for rx_reset */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RESET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_RESET_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1 - Current Values for Incoming RX Controls from PCS 1 (Monitor on Pre-Override Signals) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_REF_LD_VAL_MASK (0x7FU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_REF_LD_VAL_SHIFT (0U) /*! REF_LD_VAL - Value from PCS for rx_ref_ld_val */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_REF_LD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_REF_LD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_REF_LD_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2 - Current Values for Incoming RX Controls from PCS 2 (Monitor on the Pre-Override Signals) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_VCO_LD_VAL_MASK (0x1FFFU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_VCO_LD_VAL_SHIFT (0U) /*! VCO_LD_VAL - Value from PCS for rx_vco_ld_val */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_VCO_LD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_VCO_LD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_VCO_LD_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3 - Current Values for Incoming RX Controls from PCS 3 (Monitor on the Pre-Override Signals) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_ATT_LVL_MASK (0x7U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_ATT_LVL_SHIFT (0U) /*! EQ_ATT_LVL - Value from ASIC for rx_eq_att_lvl */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_ATT_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_ATT_LVL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_ATT_LVL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA1_GAIN_MASK (0x38U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA1_GAIN_SHIFT (3U) /*! EQ_VGA1_GAIN - Value from ASIC for rx_eq_vga1_gain */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA1_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA1_GAIN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA1_GAIN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA2_GAIN_MASK (0x1C0U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA2_GAIN_SHIFT (6U) /*! EQ_VGA2_GAIN - Value from ASIC for rx_eq_vga2_gain */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA2_GAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA2_GAIN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_VGA2_GAIN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_CTLE_BOOST_MASK (0x3E00U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_CTLE_BOOST_SHIFT (9U) /*! EQ_CTLE_BOOST - Value from ASIC for rx_eq_ctle_boost */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_CTLE_BOOST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_CTLE_BOOST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_EQ_CTLE_BOOST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4 - Current Values for Incoming RX Controls from PCS 4 (Monitor on the Pre-Override Signals) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_CTLE_POLE_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_CTLE_POLE_SHIFT (0U) /*! EQ_CTLE_POLE - Value from ASIC for rx_eq_ctle_pole */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_CTLE_POLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_CTLE_POLE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_CTLE_POLE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_DFE_TAP1_MASK (0x3FCU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_DFE_TAP1_SHIFT (2U) /*! EQ_DFE_TAP1 - Value from ASIC for rx_eq_dfe_tap1 */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_DFE_TAP1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_DFE_TAP1_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_EQ_DFE_TAP1_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT - Override Values for Outgoing RX Controls to PCS */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_ACK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_ACK_SHIFT (0U) /*! ACK - Override value for rx_ack * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_ACK_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_EN_CTL_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_EN_CTL_SHIFT (1U) /*! EN_CTL - Enable Override Values for All Control Outputs of this Register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_EN_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_EN_CTL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_EN_CTL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_OUT - Current Values for Outgoing RX Status Controls from Raw PCS */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_ACK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_ACK_SHIFT (0U) /*! ACK - Value from Raw PCS for rx_ack */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_ACK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK - RX Adaptation Acknowledge */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_RX_ADAPT_ACK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_RX_ADAPT_ACK_SHIFT (0U) /*! RX_ADAPT_ACK - RX Adaptation Acknowledge */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_RX_ADAPT_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_RX_ADAPT_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_RX_ADAPT_ACK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM - RX Adaptation Figure of Merit */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_RX_ADAPT_FOM_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_RX_ADAPT_FOM_SHIFT (0U) /*! RX_ADAPT_FOM - RX Adaptation Figure of Merit */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_RX_ADAPT_FOM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_RX_ADAPT_FOM_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_RX_ADAPT_FOM_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR - RX Calculated Direction for TX-Pre */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_RX_TXPRE_DIR_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_RX_TXPRE_DIR_SHIFT (0U) /*! RX_TXPRE_DIR - RX Calculated Direction for TX-Pre * 0b00..No change * 0b01..Increment * 0b10..Decrement * 0b11..Reserved */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_RX_TXPRE_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_RX_TXPRE_DIR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_RX_TXPRE_DIR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR - RX Calculated Direction for TX-Main */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_RX_TXMAIN_DIR_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_RX_TXMAIN_DIR_SHIFT (0U) /*! RX_TXMAIN_DIR - RX Calculated Direction for TX-Main * 0b00..No change * 0b01..Increment * 0b10..Decrement * 0b11..Reserved */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_RX_TXMAIN_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_RX_TXMAIN_DIR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_RX_TXMAIN_DIR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR - RX Calculated Direction for TX-Post */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_RX_TXPOST_DIR_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_RX_TXPOST_DIR_SHIFT (0U) /*! RX_TXPOST_DIR - RX Calculated Direction for TX-Post * 0b00..No change * 0b01..Increment * 0b10..Decrement * 0b11..Reserved */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_RX_TXPOST_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_RX_TXPOST_DIR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_RX_TXPOST_DIR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_LANE_NUMBER - Current Lane Number */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_LANE_NUMBER_MASK (0xFU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_LANE_NUMBER_SHIFT (0U) /*! LANE_NUMBER - Current Lane Number */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_LANE_NUMBER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_LANE_NUMBER_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_LANE_NUMBER_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN - ATE Override Input to Control Top-Level Inputs 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_VAL_SHIFT (0U) /*! RX_RESET_ATE_OVRD_VAL - ATE Override Value for Top-Level rx_reset Input * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_EN_SHIFT (1U) /*! RX_RESET_ATE_OVRD_EN - Enable ATE Override Value for rx_reset Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RESET_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_VAL_SHIFT (2U) /*! TX_RESET_ATE_OVRD_VAL - ATE Override Value for Top-Level tx_reset Input * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_EN_SHIFT (3U) /*! TX_RESET_ATE_OVRD_EN - Enable ATE Override Value for tx_reset Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_RESET_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_VAL_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_VAL_SHIFT (4U) /*! RX_REQ_ATE_OVRD_VAL - ATE Override Value for Top-Level rx_req Input * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_EN_MASK (0x20U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_EN_SHIFT (5U) /*! RX_REQ_ATE_OVRD_EN - Enable ATE Override Value for rx_req Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_REQ_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_VAL_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_VAL_SHIFT (6U) /*! TX_REQ_ATE_OVRD_VAL - ATE Override Value for Top-Level tx_req Input * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_EN_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_EN_SHIFT (7U) /*! TX_REQ_ATE_OVRD_EN - Enable ATE Override Value for tx_req Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_TX_REQ_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_VAL_MASK (0x100U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_VAL_SHIFT (8U) /*! RX_DFE_BYPASS_ATE_OVRD_VAL - ATE Override Value for rx_dfe_bypass Input * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_EN_MASK (0x200U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_EN_SHIFT (9U) /*! RX_DFE_BYPASS_ATE_OVRD_EN - Enable ATE Override Value for rx_dfe_bypass Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_DFE_BYPASS_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_VAL_MASK (0xC00U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_VAL_SHIFT (10U) /*! RX_RATE_ATE_OVRD_VAL - ATE Override Value for rx_rate Input */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_EN_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_EN_SHIFT (12U) /*! RX_RATE_ATE_OVRD_EN - Enable ATE Override Value for rx_rate Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_RATE_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_VAL_MASK (0x6000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_VAL_SHIFT (13U) /*! RX_WIDTH_ATE_OVRD_VAL - ATE Override Value for rx_width Input */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_EN_MASK (0x8000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_EN_SHIFT (15U) /*! RX_WIDTH_ATE_OVRD_EN - Enable ATE Override Value for rx_width Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_RX_WIDTH_ATE_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1 - Overrides the RX Output Clocks during the PHY Initialization 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_CLK_EN_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_CLK_EN_SHIFT (0U) /*! RX_CLK_EN - Enable the Outgoing rx_clk * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_CLK_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_CLK_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_DIV16P5_CLK_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_DIV16P5_CLK_EN_SHIFT (1U) /*! RX_DIV16P5_CLK_EN - Enable the Outgoing rx_div16p5_clk * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1_RX_DIV16P5_CLK_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4 - Override Values for Incoming RX Controls from PCS 4 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_VAL_SHIFT (0U) /*! RX_CDR_VCO_STEP_CTRL_OVRD_VAL - Override Value for rx_cdr_vco_step_ctrl * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_EN_SHIFT (1U) /*! RX_CDR_VCO_STEP_CTRL_OVRD_EN - Enable Override for rx_cdr_vco_step_ctrl * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_STEP_CTRL_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_VAL_SHIFT (2U) /*! RX_CDR_VCO_TEMP_COMP_EN_OVRD_VAL - Override Value for rx_cdr_vco_temp_comp_en * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_EN_SHIFT (3U) /*! RX_CDR_VCO_TEMP_COMP_EN_OVRD_EN - Enable Override for rx_cdr_vco_temp_comp_en * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_RX_CDR_VCO_TEMP_COMP_EN_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_MASK (0x30U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_SHIFT (4U) /*! VCO_FREQBAND_VAL_OVRD - Override Value for rx_cdr_vco_freqband */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_EN_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_EN_SHIFT (6U) /*! VCO_FREQBAND_VAL_OVRD_EN - Enable Override for rx_cdr_vco_freqband * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_VCO_FREQBAND_VAL_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_MASK (0x3F80U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_SHIFT (7U) /*! REF_LD_VAL_OVRD - Override Value for rx_ref_ld_val */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_EN_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_EN_SHIFT (14U) /*! REF_LD_VAL_OVRD_EN - Enable Override for rx_ref_ld_val * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_4_REF_LD_VAL_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5 - RX Adaptation Mode Override */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_SHIFT (0U) /*! RX_ADAPT_SEL_OVRD - Overridden Value for the RX Adaptation Setting */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_EN_SHIFT (1U) /*! RX_ADAPT_SEL_OVRD_EN - Enable Override the RX Adaptation Setting * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_SEL_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_MASK (0xCU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_SHIFT (2U) /*! RX_ADAPT_MODE - Overridden Value for RX Adaptation Mode */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_OVRD_EN_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_OVRD_EN_SHIFT (4U) /*! RX_ADAPT_MODE_OVRD_EN - Enable Override for the RX Adaptation Mode * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_MODE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_MASK (0x3E0U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_SHIFT (5U) /*! RX_CDR_PPM_MAX_OVRD - Overridden Value for RX CDR PPM Max */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_EN_MASK (0x400U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_EN_SHIFT (10U) /*! RX_CDR_PPM_MAX_OVRD_EN - Enable Override for the RX CDR PPM Max * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_CDR_PPM_MAX_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_MASK (0x800U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_SHIFT (11U) /*! RX_ADAPT_IN_PROG_OVRD - Overridden Value for the RX Adaptation in Progress */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_EN_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_EN_SHIFT (12U) /*! RX_ADAPT_IN_PROG_OVRD_EN - Enable Override for RX Adaptation in Progress * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_RX_ADAPT_IN_PROG_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_MASK (0x2000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_SHIFT (13U) /*! ADAPT_REQ - Override Value for rx_adapt_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_OVRD_EN_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_OVRD_EN_SHIFT (14U) /*! ADAPT_REQ_OVRD_EN - Enable Override Values for rx_adapt_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_5_ADAPT_REQ_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5 - Current Values for Incoming RX Controls from PCS 5 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_ADAPT_MODE_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_ADAPT_MODE_SHIFT (0U) /*! ADAPT_MODE - Value from ASIC for rx_adapt_mode */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_ADAPT_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_ADAPT_MODE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_ADAPT_MODE_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_SEL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_SEL_SHIFT (2U) /*! RX_ADAPT_SEL - Value from ASIC for rx_adapt_sel */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_SEL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_SEL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_DELTA_IQ_MASK (0x78U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_DELTA_IQ_SHIFT (3U) /*! RX_DELTA_IQ - Value from ASIC for rx_delta_iq */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_DELTA_IQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_DELTA_IQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_DELTA_IQ_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_MARGIN_IQ_MASK (0x3F80U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_MARGIN_IQ_SHIFT (7U) /*! RX_MARGIN_IQ - Value from ASIC for rx_margin_iq */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_MARGIN_IQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_MARGIN_IQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_MARGIN_IQ_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_IN_PROG_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_IN_PROG_SHIFT (14U) /*! RX_ADAPT_IN_PROG - Value from ASIC for rx_adapt_in_prog */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_IN_PROG(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_IN_PROG_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_5_RX_ADAPT_IN_PROG_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6 - Override Register for RX IQ Setting */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_MASK (0xFU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_SHIFT (0U) /*! RX_DELTA_IQ_OVRD - Override the RX Delta IQ Setting */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_EN_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_EN_SHIFT (4U) /*! RX_DELTA_IQ_OVRD_EN - Enable Override the RX Delta IQ Setting * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_DELTA_IQ_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_MASK (0xFE0U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_SHIFT (5U) /*! RX_MARGIN_DELTA_OVRD - Override the RX margin IQ Setting */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_EN_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_EN_SHIFT (12U) /*! RX_MARGIN_DELTA_OVRD_EN - Enable Override the RX Margin IQ Setting * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_6_RX_MARGIN_DELTA_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1 - Override Values for Incoming RX EQ Controls from PCS 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA1_GAIN_OVRD_VAL_MASK (0x7U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA1_GAIN_OVRD_VAL_SHIFT (0U) /*! RX_EQ_VGA1_GAIN_OVRD_VAL - Override Value for rx_eq_vga1_gain[3:0] */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA1_GAIN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA1_GAIN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA1_GAIN_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA2_GAIN_OVRD_VAL_MASK (0x38U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA2_GAIN_OVRD_VAL_SHIFT (3U) /*! RX_EQ_VGA2_GAIN_OVRD_VAL - Override Value for rx_eq_vga2_gain[3:0] */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA2_GAIN_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA2_GAIN_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_VGA2_GAIN_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_ATT_LVL_OVRD_VAL_MASK (0x1C0U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_ATT_LVL_OVRD_VAL_SHIFT (6U) /*! RX_EQ_ATT_LVL_OVRD_VAL - Override Value for rx_eq_att_lvl[2:0] */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_ATT_LVL_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_ATT_LVL_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_ATT_LVL_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_OVRD_EN_MASK (0x200U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_OVRD_EN_SHIFT (9U) /*! RX_EQ_OVRD_EN - Enable Override Values for all RX EQ settings * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1_RX_EQ_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6 - Current Values for Incoming RX Controls from PCS 6 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_CDR_PPM_MAX_MASK (0x1FU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_CDR_PPM_MAX_SHIFT (0U) /*! RX_CDR_PPM_MAX - Value from ASIC for rx_cdr_ppm_max */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_CDR_PPM_MAX(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_CDR_PPM_MAX_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_CDR_PPM_MAX_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_MISC_MASK (0x1FE0U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_MISC_SHIFT (5U) /*! RX_MISC - Value from ASIC fro rx_misc */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_MISC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_MISC_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_6_RX_MISC_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1 - ATE Override Input to Control Top-Level Inputs 2 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_VAL_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_VAL_SHIFT (0U) /*! RX_PSTATE_ATE_OVRD_VAL - ATE Override Value for Top-Level rx_pstate Input */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_EN_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_EN_SHIFT (2U) /*! RX_PSTATE_ATE_OVRD_EN - Enable ATE Override Value for rx_pstate Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_PSTATE_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_VAL_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_VAL_SHIFT (3U) /*! RX_LPD_ATE_OVRD_VAL - ATE Override Value for Top-Level rx_lpd Input * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_EN_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_EN_SHIFT (4U) /*! RX_LPD_ATE_OVRD_EN - Enable ATE Override Value for rx_lpd Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_LPD_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_VAL_MASK (0x1E0U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_VAL_SHIFT (5U) /*! RX_DELTA_IQ_ATE_OVRD_VAL - ATE Override Value for Top-Level rx_delta_iq Input */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_EN_MASK (0x200U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_EN_SHIFT (9U) /*! RX_DELTA_IQ_ATE_OVRD_EN - Enable ATE Override Value for rx_delta_iq Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_DELTA_IQ_ATE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_VAL_MASK (0x400U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_VAL_SHIFT (10U) /*! RX_ADAPT_SEL_ATE_OVRD_VAL - ATE Override Value for Top-Level rx_adapt_sel Input * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_EN_MASK (0x800U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_EN_SHIFT (11U) /*! RX_ADAPT_SEL_ATE_OVRD_EN - Enable ATE Override Value for rx_adapt_sel Input * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN_1_RX_ADAPT_SEL_ATE_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2 - Override Values for Incoming RX EQ Controls from PCS 2 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_DFE_TAP1_OVRD_VAL_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_DFE_TAP1_OVRD_VAL_SHIFT (0U) /*! RX_EQ_DFE_TAP1_OVRD_VAL - Override value for rx_eq_dfe_tap1[7:0] */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_DFE_TAP1_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_DFE_TAP1_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_DFE_TAP1_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_BOOST_OVRD_VAL_MASK (0x1F00U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_BOOST_OVRD_VAL_SHIFT (8U) /*! RX_EQ_CTLE_BOOST_OVRD_VAL - Override Value for rx_eq_ctle_boost[4:0] */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_BOOST_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_BOOST_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_BOOST_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_POLE_OVRD_VAL_MASK (0x6000U) #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_POLE_OVRD_VAL_SHIFT (13U) /*! RX_EQ_CTLE_POLE_OVRD_VAL - Override Value for rx_eq_ctle_pole[2:0] */ #define ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_POLE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_POLE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2_RX_EQ_CTLE_POLE_OVRD_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FSM_OVRD_CTL - FSM Override Control */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_ADDR_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_ADDR_SHIFT (0U) /*! FSM_JMP_ADDR - The jump address used when FSM_JUMP_EN=1. The address is encoded as follows: [11:8] mem_lane, [7:5] bank, [4:0] register */ #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_ADDR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_ADDR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_ADDR_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_EN_MASK (0x1000U) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_EN_SHIFT (12U) /*! FSM_JMP_EN - Force the FSM to jump to FSM_JMP_ADDR in the program memory. Is applied when FSM_CMD_START is pulsed */ #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_JMP_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_CMD_START_MASK (0x2000U) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_CMD_START_SHIFT (13U) /*! FSM_CMD_START - Execute the current command or resume from breakpoint. This is a self-clearing bit */ #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_CMD_START(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_CMD_START_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_CMD_START_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_OVRD_EN_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_OVRD_EN_SHIFT (14U) /*! FSM_OVRD_EN - Enable overriding the FSM execution of commands. Must be asserted to use FSM_CMD_START and FSM_JMP_EN features * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_FSM_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FSM_JMP_BANK - FSM Jump Bank */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_JMP_BANK_BANK_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_JMP_BANK_BANK_SHIFT (0U) #define ENET_PHY_RAWLANE0_DIG_FSM_FSM_JMP_BANK_BANK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FSM_JMP_BANK_BANK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FSM_JMP_BANK_BANK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0 - FSM Breakpoint 0 on SRAM Address for Debugging */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_ADDR_MASK (0x3FFFU) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_ADDR_SHIFT (0U) /*! BREAKPOINT_ADDR - Memory Address for Breakpoint 0 */ #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_ADDR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_ADDR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_ADDR_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_EN_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_EN_SHIFT (14U) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0_BREAKPOINT_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1 - FSM Breakpoint 1 on SRAM Address for Debugging */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_ADDR_MASK (0x3FFFU) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_ADDR_SHIFT (0U) /*! BREAKPOINT_ADDR - Memory Address for Breakpoint 1 */ #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_ADDR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_ADDR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_ADDR_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_EN_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_EN_SHIFT (14U) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1_BREAKPOINT_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_MEM_ADDR_MON - Memory Address Monitor */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_ADDR_MON_MEM_ADDR_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_ADDR_MON_MEM_ADDR_SHIFT (0U) /*! MEM_ADDR - Current value of memory address used in Lane FSM */ #define ENET_PHY_RAWLANE0_DIG_FSM_MEM_ADDR_MON_MEM_ADDR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_MEM_ADDR_MON_MEM_ADDR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_MEM_ADDR_MON_MEM_ADDR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_STATUS_MON - FSM Status Monitor */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_STATE_MASK (0x1FU) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_STATE_SHIFT (0U) /*! STATE - Current state of Lane FSM */ #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_CMD_RDY_MASK (0x20U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_CMD_RDY_SHIFT (5U) /*! CMD_RDY - New command is ready for execution (applicable when FSM_OVRD_EN=1) */ #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_CMD_RDY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_CMD_RDY_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_CMD_RDY_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_OVFLW_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_OVFLW_SHIFT (6U) /*! ALU_OVFLW - Current value of ALU overflow bit */ #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_OVFLW(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_OVFLW_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_OVFLW_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_RES_EQ0_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_RES_EQ0_SHIFT (7U) /*! ALU_RES_EQ0 - Check if ALU result register currently equals zero */ #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_RES_EQ0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_RES_EQ0_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_ALU_RES_EQ0_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WAIT_CNT_EQ0_MASK (0x100U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WAIT_CNT_EQ0_SHIFT (8U) /*! WAIT_CNT_EQ0 - Check if wait counter currently equals zero */ #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WAIT_CNT_EQ0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WAIT_CNT_EQ0_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WAIT_CNT_EQ0_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WRMSK_DISABLED_MASK (0x200U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WRMSK_DISABLED_SHIFT (9U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WRMSK_DISABLED(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WRMSK_DISABLED_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_WRMSK_DISABLED_MASK) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_RDMSK_DISABLED_MASK (0x400U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_RDMSK_DISABLED_SHIFT (10U) #define ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_RDMSK_DISABLED(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_RDMSK_DISABLED_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_STATUS_MON_RDMSK_DISABLED_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL - Status of Fast RX Start Up Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_FAST_RX_STARTUP_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_FAST_RX_STARTUP_CAL_SHIFT (0U) /*! FAST_RX_STARTUP_CAL - Status of Fast RX Start Up Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_FAST_RX_STARTUP_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_FAST_RX_STARTUP_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_FAST_RX_STARTUP_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_RX_ADAPT - Status of Fast RX Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_FAST_RX_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_FAST_RX_ADAPT_SHIFT (0U) /*! FAST_RX_ADAPT - Status of Fast RX Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_FAST_RX_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_FAST_RX_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_FAST_RX_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_SUP - Status of Fast Support Block */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_SUP_FAST_SUP_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_SUP_FAST_SUP_SHIFT (0U) /*! FAST_SUP - Status of Fast Support Block (MPLL and Rtune) */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_SUP_FAST_SUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_SUP_FAST_SUP_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_SUP_FAST_SUP_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE - Status of Fast TX Common-Mode Charge-Up */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_FAST_TX_CMN_MODE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_FAST_TX_CMN_MODE_SHIFT (0U) /*! FAST_TX_CMN_MODE - Status of Fast TX Common-Mode Charge-Up */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_FAST_TX_CMN_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_FAST_TX_CMN_MODE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_FAST_TX_CMN_MODE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_TX_RXDET - Status of Fast TX Detect RX */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_RXDET_FAST_TX_RXDET_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_RXDET_FAST_TX_RXDET_SHIFT (0U) /*! FAST_TX_RXDET - Status of Fast TX Detect RX */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_RXDET_FAST_TX_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_RXDET_FAST_TX_RXDET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_TX_RXDET_FAST_TX_RXDET_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_RX_PWRUP - Status of Fast RX Power-Up */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_FAST_RX_PWRUP_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_FAST_RX_PWRUP_SHIFT (0U) /*! FAST_RX_PWRUP - Status of Fast RX Power-Up (LOS, VREG/AFE and DCC) */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_FAST_RX_PWRUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_FAST_RX_PWRUP_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_FAST_RX_PWRUP_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT - Status of Fast RX VCO Wait Times */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_FAST_RX_VCO_WAIT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_FAST_RX_VCO_WAIT_SHIFT (0U) /*! FAST_RX_VCO_WAIT - Status of Fast RX VCO Wait Times */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_FAST_RX_VCO_WAIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_FAST_RX_VCO_WAIT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_FAST_RX_VCO_WAIT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL - Status of Fast RX VCO Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_FAST_RX_VCO_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_FAST_RX_VCO_CAL_SHIFT (0U) /*! FAST_RX_VCO_CAL - Status of Fast RX VCO Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_FAST_RX_VCO_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_FAST_RX_VCO_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_FAST_RX_VCO_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT - Status of Fast RX Continuous Calibration/Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT_FAST_RX_CONT_CAL_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT_FAST_RX_CONT_CAL_ADAPT_SHIFT (0U) /*! FAST_RX_CONT_CAL_ADAPT - Status of Fast RX Continuous Calibration/Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT_FAST_RX_CONT_CAL_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT_FAST_RX_CONT_CAL_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT_FAST_RX_CONT_CAL_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT - Status of Fast RX Continuous Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT_FAST_RX_CONT_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT_FAST_RX_CONT_ADAPT_SHIFT (0U) /*! FAST_RX_CONT_ADAPT - Status of Fast RX Continuous Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT_FAST_RX_CONT_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT_FAST_RX_CONT_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT_FAST_RX_CONT_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL - Status of RX AFE Startup Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL_SKIP_RX_AFE_STARTUP_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL_SKIP_RX_AFE_STARTUP_CAL_SHIFT (0U) /*! SKIP_RX_AFE_STARTUP_CAL - Status of RX AFE start-up calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL_SKIP_RX_AFE_STARTUP_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL_SKIP_RX_AFE_STARTUP_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL_SKIP_RX_AFE_STARTUP_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL - Status of RX DFE Startup Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL_SKIP_RX_DFE_STARTUP_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL_SKIP_RX_DFE_STARTUP_CAL_SHIFT (0U) /*! SKIP_RX_DFE_STARTUP_CAL - Status of RX DFE Startup Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL_SKIP_RX_DFE_STARTUP_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL_SKIP_RX_DFE_STARTUP_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL_SKIP_RX_DFE_STARTUP_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL - Status of DFE Extended Startup Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL_SKIP_RX_DFE_EXT_STARTUP_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL_SKIP_RX_DFE_EXT_STARTUP_CAL_SHIFT (0U) /*! SKIP_RX_DFE_EXT_STARTUP_CAL - Status of DFE Extended Startup Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL_SKIP_RX_DFE_EXT_STARTUP_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL_SKIP_RX_DFE_EXT_STARTUP_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL_SKIP_RX_DFE_EXT_STARTUP_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP - Status of RX IQ Fixed Offset */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP_SKIP_RX_IQ_DELTA_STARTUP_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP_SKIP_RX_IQ_DELTA_STARTUP_SHIFT (0U) /*! SKIP_RX_IQ_DELTA_STARTUP - Status of RX IQ Fixed Offset */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP_SKIP_RX_IQ_DELTA_STARTUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP_SKIP_RX_IQ_DELTA_STARTUP_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP_SKIP_RX_IQ_DELTA_STARTUP_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL - Status of RX IQ Startup Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL_SKIP_RX_IQ_STARTUP_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL_SKIP_RX_IQ_STARTUP_CAL_SHIFT (0U) /*! SKIP_RX_IQ_STARTUP_CAL - Status of RX IQ Startup Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL_SKIP_RX_IQ_STARTUP_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL_SKIP_RX_IQ_STARTUP_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL_SKIP_RX_IQ_STARTUP_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT - Status of RX AFE Startup Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT_SKIP_RX_AFE_STARTUP_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT_SKIP_RX_AFE_STARTUP_ADAPT_SHIFT (0U) /*! SKIP_RX_AFE_STARTUP_ADAPT - Status of RX AFE DAC Startup Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT_SKIP_RX_AFE_STARTUP_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT_SKIP_RX_AFE_STARTUP_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT_SKIP_RX_AFE_STARTUP_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT - Status of RX DFE Startup Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT_SKIP_RX_DFE_STARTUP_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT_SKIP_RX_DFE_STARTUP_ADAPT_SHIFT (0U) /*! SKIP_RX_DFE_STARTUP_ADAPT - Status of RX DFE DAC Startup Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT_SKIP_RX_DFE_STARTUP_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT_SKIP_RX_DFE_STARTUP_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT_SKIP_RX_DFE_STARTUP_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT - Status of RX IO Startup Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT_SKIP_RX_IQ_STARTUP_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT_SKIP_RX_IQ_STARTUP_ADAPT_SHIFT (0U) /*! SKIP_RX_IQ_STARTUP_ADAPT - Status of RX IQ Startup Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT_SKIP_RX_IQ_STARTUP_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT_SKIP_RX_IQ_STARTUP_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT_SKIP_RX_IQ_STARTUP_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL - Status of RX Continuous Phase Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL_SKIP_RX_CONT_PHASE_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL_SKIP_RX_CONT_PHASE_CAL_SHIFT (0U) /*! SKIP_RX_CONT_PHASE_CAL - Status of RX Continuous Phase Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL_SKIP_RX_CONT_PHASE_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL_SKIP_RX_CONT_PHASE_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL_SKIP_RX_CONT_PHASE_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL - Status of RX AFE Continuous Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL_SKIP_RX_AFE_CONT_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL_SKIP_RX_AFE_CONT_CAL_SHIFT (0U) /*! SKIP_RX_AFE_CONT_CAL - Status of RX AFE Continuous Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL_SKIP_RX_AFE_CONT_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL_SKIP_RX_AFE_CONT_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL_SKIP_RX_AFE_CONT_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT - Status of RX Reference Level Continuous Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT_SKIP_RX_REFLVL_CONT_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT_SKIP_RX_REFLVL_CONT_ADAPT_SHIFT (0U) /*! SKIP_RX_REFLVL_CONT_ADAPT - Status of RX Reference Level Continuous Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT_SKIP_RX_REFLVL_CONT_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT_SKIP_RX_REFLVL_CONT_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT_SKIP_RX_REFLVL_CONT_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT - Status of RX VGA Continuous Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT_SKIP_RX_VGA_CONT_ADAPT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT_SKIP_RX_VGA_CONT_ADAPT_SHIFT (0U) /*! SKIP_RX_VGA_CONT_ADAPT - Status of RX VGA Continuous Adaptation */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT_SKIP_RX_VGA_CONT_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT_SKIP_RX_VGA_CONT_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT_SKIP_RX_VGA_CONT_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL - Status of RX Phase Startup Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL_SKIP_RX_PHS_STARTUP_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL_SKIP_RX_PHS_STARTUP_CAL_SHIFT (0U) /*! SKIP_RX_PHS_STARTUP_CAL - Status of RX Phase Startup Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL_SKIP_RX_PHS_STARTUP_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL_SKIP_RX_PHS_STARTUP_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL_SKIP_RX_PHS_STARTUP_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL - Status of RX Phase Extended Startup Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL_SKIP_RX_PHS_EXT_STARTUP_CAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL_SKIP_RX_PHS_EXT_STARTUP_CAL_SHIFT (0U) /*! SKIP_RX_PHS_EXT_STARTUP_CAL - Status of RX Phase Extended Startup Calibration */ #define ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL_SKIP_RX_PHS_EXT_STARTUP_CAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL_SKIP_RX_PHS_EXT_STARTUP_CAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL_SKIP_RX_PHS_EXT_STARTUP_CAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_FSM_FW_STATES_1 - Stores Various States for Firmware - 2 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_FSM_FW_STATES_1_SPARE_STATE_0_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_FSM_FW_STATES_1_SPARE_STATE_0_SHIFT (0U) /*! SPARE_STATE_0 - Spare Fields to be Used by Firmware */ #define ENET_PHY_RAWLANE0_DIG_FSM_FW_STATES_1_SPARE_STATE_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_FSM_FW_STATES_1_SPARE_STATE_0_SHIFT)) & ENET_PHY_RAWLANE0_DIG_FSM_FW_STATES_1_SPARE_STATE_0_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST - Offset Value for RX AFE ATT iDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_AFE_ATT_IDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_AFE_ATT_IDAC_OFST_SHIFT (0U) /*! AFE_ATT_IDAC_OFST - Offset Value for AFE ATT iDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_AFE_ATT_IDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_AFE_ATT_IDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_AFE_ATT_IDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST - Offset Value for RX AFE CTLE iDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_AFE_CTLE_IDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_AFE_CTLE_IDAC_OFST_SHIFT (0U) /*! AFE_CTLE_IDAC_OFST - Offset Value for AFE CTLE iDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_AFE_CTLE_IDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_AFE_CTLE_IDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_AFE_CTLE_IDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST - Offset Values for RX AFE VGA1 iDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_AFE_VGA1_IDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_AFE_VGA1_IDAC_OFST_SHIFT (0U) /*! AFE_VGA1_IDAC_OFST - Offset Value for AFE VGA1 iDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_AFE_VGA1_IDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_AFE_VGA1_IDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_AFE_VGA1_IDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST - Offset Values for RX DFE Phase Even vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DFE_PHASE_EVEN_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DFE_PHASE_EVEN_VDAC_OFST_SHIFT (0U) /*! DFE_PHASE_EVEN_VDAC_OFST - Offset Value for DFE Phase Even vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DFE_PHASE_EVEN_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DFE_PHASE_EVEN_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DFE_PHASE_EVEN_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST - Offset Values for RX DFE Phase Odd vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DFE_PHASE_ODD_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DFE_PHASE_ODD_VDAC_OFST_SHIFT (0U) /*! DFE_PHASE_ODD_VDAC_OFST - Offset Value for DFE Phase Odd vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DFE_PHASE_ODD_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DFE_PHASE_ODD_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DFE_PHASE_ODD_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST - Offset Values for RX DFE Phase Even Low vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DFE_PHASE_EVEN_LOW_VDAC_OFST_SHIFT (0U) /*! DFE_PHASE_EVEN_LOW_VDAC_OFST - Offset Value for DFE Phase Even Low vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DFE_PHASE_EVEN_LOW_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DFE_PHASE_EVEN_LOW_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST - Offset Values for RX DFE Phase Odd Low vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DFE_PHASE_ODD_LOW_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DFE_PHASE_ODD_LOW_VDAC_OFST_SHIFT (0U) /*! DFE_PHASE_ODD_LOW_VDAC_OFST - Offset Value for DFE Phase Odd Low vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DFE_PHASE_ODD_LOW_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DFE_PHASE_ODD_LOW_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DFE_PHASE_ODD_LOW_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_PHSADJ_LIN - RX Phase Adjust Linear Value */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_RX_PHSADJ_LIN_MASK (0x3FU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_RX_PHSADJ_LIN_SHIFT (0U) /*! RX_PHSADJ_LIN - Linear Value for RX Phase Adjust */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_RX_PHSADJ_LIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_RX_PHSADJ_LIN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_RX_PHSADJ_LIN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST - Offset Values for RX DFE Data Even High vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_EVEN_HIGH_VDAC_OFST - Offset Value for DFE Data Even High vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST - Offset Values for RX DFE Data Even Low vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_EVEN_LOW_VDAC_OFST - Offset Value for DFE Data Even Low vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DFE_DATA_EVEN_LOW_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST - Offset Values for RX DFE Data Odd High vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_ODD_HIGH_VDAC_OFST - Offset Value for DFE Data Odd High vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DFE_DATA_ODD_HIGH_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST - Offset Values for RX DFE Data Odd Low vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_SHIFT (0U) /*! DFE_DATA_ODD_LOW_VDAC_OFST - Offset Value for DFE Data Odd Low vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DFE_DATA_ODD_LOW_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST - Offset Values for RX DFE By-Pass Even vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_SHIFT (0U) /*! DFE_BYPASS_EVEN_VDAC_OFST - Offset Value for DFE By-Pass Even vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DFE_BYPASS_EVEN_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST - Offset Values for RX DFE By-Pass Odd vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_SHIFT (0U) /*! DFE_BYPASS_ODD_VDAC_OFST - Offset Value for DFE By-Pass Odd vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DFE_BYPASS_ODD_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST - Offset Values for RX DFE Error Even vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_SHIFT (0U) /*! DFE_ERROR_EVEN_VDAC_OFST - Offset Value for DFE Error Even vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DFE_ERROR_EVEN_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST - Offset Values for RX DFE Error Odd vDAC */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_SHIFT (0U) /*! DFE_ERROR_ODD_VDAC_OFST - Offset Value for DFE Error Odd vDAC */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DFE_ERROR_ODD_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_CAL_IQ - Value for RX Calibrated IQ Phase */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_IQ_RX_CAL_IQ_MASK (0x7FU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_IQ_RX_CAL_IQ_SHIFT (0U) /*! RX_CAL_IQ - Value for RX Calibrated IQ Phase */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_IQ_RX_CAL_IQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_IQ_RX_CAL_IQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_IQ_RX_CAL_IQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL - Set to Skip Firmware Mission-Mode Algorithms */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_FOM_CONT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_FOM_CONT_SHIFT (0U) /*! SKIP_RX_FOM_CONT - Skip RX Continuous FOM Measurement * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_FOM_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_FOM_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_FOM_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_REFLVL_ADAPT_CONT_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_REFLVL_ADAPT_CONT_SHIFT (1U) /*! SKIP_RX_REFLVL_ADAPT_CONT - Skip RX REF Continuous Adaptation * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_REFLVL_ADAPT_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_REFLVL_ADAPT_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_REFLVL_ADAPT_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_VGA_ADAPT_CONT_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_VGA_ADAPT_CONT_SHIFT (2U) /*! SKIP_RX_VGA_ADAPT_CONT - Skip RX VGA Continuous Adaptation * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_VGA_ADAPT_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_VGA_ADAPT_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_VGA_ADAPT_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_PHS_CAL_CONT_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_PHS_CAL_CONT_SHIFT (3U) /*! SKIP_RX_PHS_CAL_CONT - Skip RX Phase Slicer Offset Calibration * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_PHS_CAL_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_PHS_CAL_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_PHS_CAL_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_AFE_CAL_CONT_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_AFE_CAL_CONT_SHIFT (4U) /*! SKIP_RX_AFE_CAL_CONT - Skip RX AFE DAC Continuous Calibration * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_AFE_CAL_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_AFE_CAL_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_AFE_CAL_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_CAL_CONT_MASK (0x20U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_CAL_CONT_SHIFT (5U) /*! SKIP_RX_DFE_CAL_CONT - Skip RX DFE Slicer Continuous Calibration * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_CAL_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_CAL_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_CAL_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT25_CONT_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT25_CONT_SHIFT (6U) /*! SKIP_RX_DFE_ADAPT25_CONT - Skip RX DFE DAC Continuous Adaptation for Tap2 - Tap5 * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT25_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT25_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT25_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT1_CONT_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT1_CONT_SHIFT (7U) /*! SKIP_RX_DFE_ADAPT1_CONT - Skip RX DFE DAC Continuous Adaptation for Tap1 * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT1_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT1_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_DFE_ADAPT1_CONT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_CTLE_BOOST_CONT_MASK (0x100U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_CTLE_BOOST_CONT_SHIFT (8U) /*! SKIP_RX_CTLE_BOOST_CONT - Skip RX CTLE Boost Continuous Adaptation * 0b0..No skip * 0b1..Skip */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_CTLE_BOOST_CONT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_CTLE_BOOST_CONT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CONT_ALGO_CTL_SKIP_RX_CTLE_BOOST_CONT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_INIT_PWRUP_DONE - Initial Power-Up Done Status */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_INIT_PWRUP_DONE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_INIT_PWRUP_DONE_SHIFT (0U) /*! INIT_PWRUP_DONE - Indicates whether initial power-up has completed or not * 0b0..Not completed * 0b1..Completed */ #define ENET_PHY_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_INIT_PWRUP_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_INIT_PWRUP_DONE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_INIT_PWRUP_DONE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_ATT - RX Adapted Value of ATT */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_ATT_ADPT_VAL_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_ATT_ADPT_VAL_SHIFT (0U) /*! ATT_ADPT_VAL - Stored RX Adapted ATT Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_ATT_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_ATT_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_ATT_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_VGA - RX Adapted Value of VGA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_VGA_ADPT_VAL_MASK (0x1FFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_VGA_ADPT_VAL_SHIFT (0U) /*! VGA_ADPT_VAL - Stored RX Adapted VGA Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_VGA_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_VGA_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_VGA_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_CTLE - RX Adapted Value of CTLE */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_BOOST_ADPT_VAL_MASK (0x3FFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_BOOST_ADPT_VAL_SHIFT (0U) /*! CTLE_BOOST_ADPT_VAL - Stored RX Adapted CTLE Boost Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_BOOST_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_BOOST_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_BOOST_ADPT_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_POLE_ADPT_VAL_MASK (0xC00U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_POLE_ADPT_VAL_SHIFT (10U) /*! CTLE_POLE_ADPT_VAL - Stored RX Adapted CTLE Pole Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_POLE_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_POLE_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_CTLE_POLE_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1 - RX Adapted Value of DFE TAP1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DFE_TAP1_ADPT_VAL_MASK (0x1FFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DFE_TAP1_ADPT_VAL_SHIFT (0U) /*! DFE_TAP1_ADPT_VAL - Stored RX Adapted DFE TAP1 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DFE_TAP1_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DFE_TAP1_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DFE_TAP1_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2 - RX Adapted Value of DFE TAP2 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DFE_TAP2_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DFE_TAP2_ADPT_VAL_SHIFT (0U) /*! DFE_TAP2_ADPT_VAL - Stored RX Adapted DFE TAP2 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DFE_TAP2_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DFE_TAP2_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DFE_TAP2_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3 - RX Adapted Value of DFE TAP3 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DFE_TAP3_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DFE_TAP3_ADPT_VAL_SHIFT (0U) /*! DFE_TAP3_ADPT_VAL - Stored DFE TAP3 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DFE_TAP3_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DFE_TAP3_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DFE_TAP3_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4 - RX Adapted Value of DFE TAP4 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DFE_TAP4_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DFE_TAP4_ADPT_VAL_SHIFT (0U) /*! DFE_TAP4_ADPT_VAL - Stored RX Adapted DFE TAP4 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DFE_TAP4_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DFE_TAP4_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DFE_TAP4_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5 - RX Adapted Value of DFE TAP5 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DFE_TAP5_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DFE_TAP5_ADPT_VAL_SHIFT (0U) /*! DFE_TAP5_ADPT_VAL - Stored RX Adapted DFE TAP5 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DFE_TAP5_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DFE_TAP5_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DFE_TAP5_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_IQ - RX Adapted Value of IQ for Bank 0 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_RX_ADPT_IQ_MASK (0x7FU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_RX_ADPT_IQ_SHIFT (0U) /*! RX_ADPT_IQ - RX Adapted Value of IQ for Bank 0 */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_RX_ADPT_IQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_RX_ADPT_IQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_RX_ADPT_IQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_REF_ERR - RX Adapted Value of Reference Level for Error Slicer for Bank 0 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_EVEN_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_EVEN_SHIFT (0U) /*! RX_ADPT_REF_ERR_EVEN - RX Adapted Value of Reference Level for Error Even Slicer for Bank 0 */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_EVEN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_EVEN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_EVEN_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_ODD_MASK (0xFF00U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_ODD_SHIFT (8U) /*! RX_ADPT_REF_ERR_ODD - RX Adapted Value of Reference Level for Error Odd Slicer for Bank 0 */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_ODD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_ODD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_RX_ADPT_REF_ERR_ODD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADAPT_DONE - RX Adaptation Done Status */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADAPT_DONE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADAPT_DONE_SHIFT (0U) /*! RX_ADAPT_DONE - Indicates whether RX adaptation has completed or not * 0b0..Not completed * 0b1..Completed */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADAPT_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADAPT_DONE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADAPT_DONE_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADPT_IQ_VLD_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADPT_IQ_VLD_SHIFT (1U) /*! RX_ADPT_IQ_VLD - Indicates if the RX adapted value of IQ for bank 0 is valid * 0b0..Invalid * 0b1..Valid */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADPT_IQ_VLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADPT_IQ_VLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_RX_ADPT_IQ_VLD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_ATT_B1 - RX Adapted Value of ATT for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_B1_ATT_ADPT_VAL_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_B1_ATT_ADPT_VAL_SHIFT (0U) /*! ATT_ADPT_VAL - Stored RX Adapted ATT Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_B1_ATT_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_B1_ATT_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ATT_B1_ATT_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_VGA_B1 - RX Adapted Value of VGA for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_B1_VGA_ADPT_VAL_MASK (0x1FFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_B1_VGA_ADPT_VAL_SHIFT (0U) /*! VGA_ADPT_VAL - Stored RX Adapted VGA Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_B1_VGA_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_B1_VGA_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_VGA_B1_VGA_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1 - RX Adapted Value of CTLE for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_BOOST_ADPT_VAL_MASK (0x3FFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_BOOST_ADPT_VAL_SHIFT (0U) /*! CTLE_BOOST_ADPT_VAL - Stored RX Adapted CTLE boost Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_BOOST_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_BOOST_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_BOOST_ADPT_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_POLE_ADPT_VAL_MASK (0xC00U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_POLE_ADPT_VAL_SHIFT (10U) /*! CTLE_POLE_ADPT_VAL - Stored RX Adapted CTLE Pole Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_POLE_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_POLE_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_CTLE_B1_CTLE_POLE_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_B1 - RX Adapted Value of DFE TAP1 for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_B1_DFE_TAP1_ADPT_VAL_MASK (0x1FFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_B1_DFE_TAP1_ADPT_VAL_SHIFT (0U) /*! DFE_TAP1_ADPT_VAL - Stored RX Adapted DFE TAP1 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_B1_DFE_TAP1_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_B1_DFE_TAP1_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_B1_DFE_TAP1_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_B1 - RX Adapted Value of DFE TAP2 for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_B1_DFE_TAP2_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_B1_DFE_TAP2_ADPT_VAL_SHIFT (0U) /*! DFE_TAP2_ADPT_VAL - Stored RX Adapted DFE TAP2 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_B1_DFE_TAP2_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_B1_DFE_TAP2_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_B1_DFE_TAP2_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_B1 - RX Adapted Value of DFE TAP3 for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_B1_DFE_TAP3_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_B1_DFE_TAP3_ADPT_VAL_SHIFT (0U) /*! DFE_TAP3_ADPT_VAL - Stored RX Adapted DFE TAP3 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_B1_DFE_TAP3_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_B1_DFE_TAP3_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_B1_DFE_TAP3_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_B1 - RX Adapted Value of DFE TAP4 for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_B1_DFE_TAP4_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_B1_DFE_TAP4_ADPT_VAL_SHIFT (0U) /*! DFE_TAP4_ADPT_VAL - Stored RX Adapted DFE TAP4 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_B1_DFE_TAP4_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_B1_DFE_TAP4_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_B1_DFE_TAP4_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_B1 - RX Adapted Value of DFE TAP5 for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_B1_DFE_TAP5_ADPT_VAL_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_B1_DFE_TAP5_ADPT_VAL_SHIFT (0U) /*! DFE_TAP5_ADPT_VAL - Stored RX Adapted DFE TAP5 Value */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_B1_DFE_TAP5_ADPT_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_B1_DFE_TAP5_ADPT_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_B1_DFE_TAP5_ADPT_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_IQ_B1 - RX Adapted Value of IQ for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_B1_RX_ADPT_IQ_B1_MASK (0x7FU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_B1_RX_ADPT_IQ_B1_SHIFT (0U) /*! RX_ADPT_IQ_B1 - RX Adapted Value of IQ for Bank 1 */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_B1_RX_ADPT_IQ_B1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_B1_RX_ADPT_IQ_B1_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_B1_RX_ADPT_IQ_B1_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1 - RX Adapted Value of Reference Level for Error Slicer for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_EVEN_B1_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_EVEN_B1_SHIFT (0U) /*! RX_ADPT_REF_ERR_EVEN_B1 - RX Adapted Value of Reference Level for Error Even Slicer for Bank 1 */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_EVEN_B1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_EVEN_B1_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_EVEN_B1_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_ODD_B1_MASK (0xFF00U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_ODD_B1_SHIFT (8U) /*! RX_ADPT_REF_ERR_ODD_B1 - RX Adapted Value of Reference Level for Error Odd Slicer for Bank 1 */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_ODD_B1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_ODD_B1_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_REF_ERR_B1_RX_ADPT_REF_ERR_ODD_B1_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1 - RX Adaptation Done Status for Bank 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADAPT_DONE_B1_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADAPT_DONE_B1_SHIFT (0U) /*! RX_ADAPT_DONE_B1 - Indicates whether bank 1 RX adaptation has completed or not * 0b0..Not completed * 0b1..Completed */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADAPT_DONE_B1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADAPT_DONE_B1_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADAPT_DONE_B1_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADPT_IQ_VLD_B1_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADPT_IQ_VLD_B1_SHIFT (1U) /*! RX_ADPT_IQ_VLD_B1 - Indicates if the RX adapted value of IQ for bank 1 is valid * 0b0..Invalid * 0b1..Valid */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADPT_IQ_VLD_B1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADPT_IQ_VLD_B1_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADAPT_DONE_B1_RX_ADPT_IQ_VLD_B1_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_FW_STATES_0 - Stores Various States for Firmware - 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_FW_STATES_0_SPARE_STATE_0_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_FW_STATES_0_SPARE_STATE_0_SHIFT (0U) /*! SPARE_STATE_0 - Spare Fields to be Used by Firmware */ #define ENET_PHY_RAWLANE0_DIG_AON_FW_STATES_0_SPARE_STATE_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_FW_STATES_0_SPARE_STATE_0_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_FW_STATES_0_SPARE_STATE_0_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_TXRX_OVRD_IN - Override Values for Incoming AON TX/RX Controls from PCS */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_VAL_SHIFT (0U) /*! RX_DISABLE_OVRD_VAL - Override Value for rx_disable * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_EN_SHIFT (1U) /*! RX_DISABLE_OVRD_EN - Override Enable for rx_disable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_RX_DISABLE_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_VAL_SHIFT (2U) /*! TX_DISABLE_OVRD_VAL - Override Value for tx_disable * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_EN_SHIFT (3U) /*! TX_DISABLE_OVRD_EN - Override Enable for tx_disable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TXRX_OVRD_IN_TX_DISABLE_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL - Equalization Direction Polarity Setting in PCS RAW */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXMAIN_DIR_INV_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXMAIN_DIR_INV_SHIFT (0U) /*! TXMAIN_DIR_INV - Invert the txmain_dir polarity * 0b0..No invert * 0b1..Invert */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXMAIN_DIR_INV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXMAIN_DIR_INV_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXMAIN_DIR_INV_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPRE_DIR_INV_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPRE_DIR_INV_SHIFT (1U) /*! TXPRE_DIR_INV - Invert the txpre_dir polarity * 0b0..No invert * 0b1..Invert */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPRE_DIR_INV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPRE_DIR_INV_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPRE_DIR_INV_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPOST_DIR_INV_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPOST_DIR_INV_SHIFT (2U) /*! TXPOST_DIR_INV - Invert the txpost_dir polarity * 0b0..No invert * 0b1..Invert */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPOST_DIR_INV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPOST_DIR_INV_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_EQ_DIR_POLARITY_CTL_TXPOST_DIR_INV_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_TX_PRE_DIV - TX Pre Threshold Div */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_OFF_MULT_MASK (0x1FU) #define ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_OFF_MULT_SHIFT (0U) /*! TX_PRE_OFF_MULT - TX Pre Offset Mult */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_OFF_MULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_OFF_MULT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_OFF_MULT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_THRESH_DIV_MASK (0x1E0U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_THRESH_DIV_SHIFT (5U) /*! TX_PRE_THRESH_DIV - TX Pre Threshold Div */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_THRESH_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_THRESH_DIV_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_PRE_DIV_TX_PRE_THRESH_DIV_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD - TX Main ATT High and Low Threshold */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_LOW_THRESHOLD_MASK (0x7U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_LOW_THRESHOLD_SHIFT (0U) /*! TX_MAIN_ATT_LOW_THRESHOLD - TX Main ATT Low Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_LOW_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_LOW_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_LOW_THRESHOLD_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_HIGH_THRESHOLD_MASK (0x38U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_HIGH_THRESHOLD_SHIFT (3U) /*! TX_MAIN_ATT_HIGH_THRESHOLD - TX Main ATT High Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_HIGH_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_HIGH_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_ATT_THRESHOLD_TX_MAIN_ATT_HIGH_THRESHOLD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD - TX Main VGA High and Low Threshold */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_LOW_THRESHOLD_MASK (0xFU) #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_LOW_THRESHOLD_SHIFT (0U) /*! TX_MAIN_VGA_LOW_THRESHOLD - TX Main VGA Low Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_LOW_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_LOW_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_LOW_THRESHOLD_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_HIGH_THRESHOLD_MASK (0xF0U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_HIGH_THRESHOLD_SHIFT (4U) /*! TX_MAIN_VGA_HIGH_THRESHOLD - TX Main VGA High Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_HIGH_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_HIGH_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_MAIN_VGA_THRESHOLD_TX_MAIN_VGA_HIGH_THRESHOLD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD - TX Post Boost High and Low Threshold */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_LOW_THRESHOLD_MASK (0x1FU) #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_LOW_THRESHOLD_SHIFT (0U) /*! TX_POST_BOOST_LOW_THRESHOLD - TX Post Boost Low Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_LOW_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_LOW_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_LOW_THRESHOLD_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_HIGH_THRESHOLD_MASK (0x3E0U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_HIGH_THRESHOLD_SHIFT (5U) /*! TX_POST_BOOST_HIGH_THRESHOLD - TX Post Boost High Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_HIGH_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_HIGH_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_POST_BOOST_THRESHOLD_TX_POST_BOOST_HIGH_THRESHOLD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD - TX Post Tap1 High and Low Threshold */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_LOW_THRESHOLD_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_LOW_THRESHOLD_SHIFT (0U) /*! TX_POST_TAP1_LOW_THRESHOLD - TX Post Tap1 Low Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_LOW_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_LOW_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_LOW_THRESHOLD_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_HIGH_THRESHOLD_MASK (0xFF00U) #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_HIGH_THRESHOLD_SHIFT (8U) /*! TX_POST_TAP1_HIGH_THRESHOLD - TX Post Tap1 High Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_HIGH_THRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_HIGH_THRESHOLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_TX_POST_TAP1_THRESHOLD_TX_POST_TAP1_HIGH_THRESHOLD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_CAL_REF_EE_VDAC_OFST - Value for Reference Level Error Even Slicer */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EE_VDAC_OFST_RX_CAL_REF_EE_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EE_VDAC_OFST_RX_CAL_REF_EE_VDAC_OFST_SHIFT (0U) /*! RX_CAL_REF_EE_VDAC_OFST - Value for Reference Level Error Even Slicer */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EE_VDAC_OFST_RX_CAL_REF_EE_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EE_VDAC_OFST_RX_CAL_REF_EE_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EE_VDAC_OFST_RX_CAL_REF_EE_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_CAL_REF_EO_VDAC_OFST - Value for Reference Level Error Odd Slicer */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EO_VDAC_OFST_RX_CAL_REF_EO_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EO_VDAC_OFST_RX_CAL_REF_EO_VDAC_OFST_SHIFT (0U) /*! RX_CAL_REF_EO_VDAC_OFST - Value for Reference Level Error Odd Slicer */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EO_VDAC_OFST_RX_CAL_REF_EO_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EO_VDAC_OFST_RX_CAL_REF_EO_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CAL_REF_EO_VDAC_OFST_RX_CAL_REF_EO_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST - Value for DFE Error Even Low and High Slicer in Mission Mode */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEH_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEH_VDAC_OFST_SHIFT (0U) /*! DFE_EEH_VDAC_OFST - Value for DFE Error Even High Slicer in Mission Mode */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEH_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEH_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEH_VDAC_OFST_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEL_VDAC_OFST_MASK (0xFF00U) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEL_VDAC_OFST_SHIFT (8U) /*! DFE_EEL_VDAC_OFST - Value for DFE Error Even Low Slicer in Mission Mode */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEL_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEL_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_EE_VDAC_OFST_DFE_EEL_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST - Value for DFE Error Odd Low and High Slicer in Mission Mode */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOH_VDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOH_VDAC_OFST_SHIFT (0U) /*! DFE_EOH_VDAC_OFST - Value for DFE Error Odd High Slicer in Mission Mode */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOH_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOH_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOH_VDAC_OFST_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOL_VDAC_OFST_MASK (0xFF00U) #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOL_VDAC_OFST_SHIFT (8U) /*! DFE_EOL_VDAC_OFST - Value for DFE Error Odd Low Slicer in Mission Mode */ #define ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOL_VDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOL_VDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_DFE_EO_VDAC_OFST_DFE_EOL_VDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_ERR_SLC_MODE - RX Adaptation Error Slicer Mode for Reference-Level Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ERR_SLC_MODE_RX_ADPT_ERR_SLC_MODE_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ERR_SLC_MODE_RX_ADPT_ERR_SLC_MODE_SHIFT (0U) /*! RX_ADPT_ERR_SLC_MODE - RX Adaptation Error Slicer Mode for Reference-Level Calibration */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ERR_SLC_MODE_RX_ADPT_ERR_SLC_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ERR_SLC_MODE_RX_ADPT_ERR_SLC_MODE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_ERR_SLC_MODE_RX_ADPT_ERR_SLC_MODE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_SETUP_REF_CTLE_IDAC_OFST - Offset Value for AFE CTLE IDAC During Reference-Level Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_CTLE_IDAC_OFST_SETUP_REF_CTLE_IDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_CTLE_IDAC_OFST_SETUP_REF_CTLE_IDAC_OFST_SHIFT (0U) /*! SETUP_REF_CTLE_IDAC_OFST - Offset Value for AFE CTLE iDAC During Reference-Level Calibration */ #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_CTLE_IDAC_OFST_SETUP_REF_CTLE_IDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_CTLE_IDAC_OFST_SETUP_REF_CTLE_IDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_CTLE_IDAC_OFST_SETUP_REF_CTLE_IDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_SETUP_REF_VGA1_IDAC_OFST - Offset Value for AFE VGA1 IDAC During Reference-Level Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_VGA1_IDAC_OFST_SETUP_REF_VGA1_IDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_VGA1_IDAC_OFST_SETUP_REF_VGA1_IDAC_OFST_SHIFT (0U) /*! SETUP_REF_VGA1_IDAC_OFST - Offset Value for AFE CTLE VGA1 During Reference-Level Calibration */ #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_VGA1_IDAC_OFST_SETUP_REF_VGA1_IDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_VGA1_IDAC_OFST_SETUP_REF_VGA1_IDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SETUP_REF_VGA1_IDAC_OFST_SETUP_REF_VGA1_IDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_SETUP_SLC_VGA1_IDAC_OFST - Offset Value for AFE VGA1 for Slicer Setup Calibration */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_SLC_VGA1_IDAC_OFST_SETUP_SLC_VGA1_IDAC_OFST_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_SLC_VGA1_IDAC_OFST_SETUP_SLC_VGA1_IDAC_OFST_SHIFT (0U) /*! SETUP_SLC_VGA1_IDAC_OFST - Offset Value for AFE VGA1 for Slicer Setup Calibration */ #define ENET_PHY_RAWLANE0_DIG_AON_SETUP_SLC_VGA1_IDAC_OFST_SETUP_SLC_VGA1_IDAC_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SETUP_SLC_VGA1_IDAC_OFST_SETUP_SLC_VGA1_IDAC_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SETUP_SLC_VGA1_IDAC_OFST_SETUP_SLC_VGA1_IDAC_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL - RX CDR Detector Control */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_DETECTOR_EN_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_DETECTOR_EN_SHIFT (0U) /*! RX_CDR_DETECTOR_EN - Enable the CDR Detector in Detector Mode * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_DETECTOR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_DETECTOR_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_DETECTOR_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_PPM_MONITOR_MODE_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_PPM_MONITOR_MODE_SHIFT (1U) /*! RX_CDR_PPM_MONITOR_MODE - Enable the CDR Detector in Monitor Mode * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_PPM_MONITOR_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_PPM_MONITOR_MODE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_RX_CDR_PPM_MONITOR_MODE_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_DIS_IN_ADAPT_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_DIS_IN_ADAPT_SHIFT (2U) /*! DIS_IN_ADAPT - Disable the CDR Detector State Machine for During Adaptation * 0b0..Not disable * 0b1..Disable */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_DIS_IN_ADAPT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_DIS_IN_ADAPT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_DETECTOR_CTL_DIS_IN_ADAPT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_CDR_RECOVERY_TIME - RX CDR Recovery Time in Reference Clock for the Intended PPM */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_RECOVERY_TIME_RX_CDR_RECOVERY_TIME_MASK (0xFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_RECOVERY_TIME_RX_CDR_RECOVERY_TIME_SHIFT (0U) /*! RX_CDR_RECOVERY_TIME - RX CDR Recovery Time in Reference Clock for Intended PPM */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_RECOVERY_TIME_RX_CDR_RECOVERY_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_RECOVERY_TIME_RX_CDR_RECOVERY_TIME_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_CDR_RECOVERY_TIME_RX_CDR_RECOVERY_TIME_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_MEM_BREAKPOINT_2 - FSM Breakpoint 2 on SRAM Address for Debugging */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_ADDR_MASK (0x3FFFU) #define ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_ADDR_SHIFT (0U) /*! BREAKPOINT_ADDR - Memory Address for Breakpoint 2 */ #define ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_ADDR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_ADDR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_ADDR_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_EN_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_EN_SHIFT (14U) /*! BREAKPOINT_EN - Enables the Breakpoint 2 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_MEM_BREAKPOINT_2_BREAKPOINT_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_0 - Adaptation Control 0 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_0_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_0_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_0_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_0_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_0_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_1 - Adaptation Control 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_1_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_1_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_1_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_1_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_1_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ - Reset Routine Request */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_RESET_RTN_REQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_RESET_RTN_REQ_SHIFT (0U) /*! RESET_RTN_REQ - Reset Routine Request * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_RESET_RTN_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_RESET_RTN_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_RESET_RTN_REQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ - RX Reset Interrupt */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_RX_RESET_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_RX_RESET_SHIFT (0U) /*! RX_RESET - RX Reset Interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_RX_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_RX_RESET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_RX_RESET_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ - RX Request Interrupt */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_RX_REQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_RX_REQ_SHIFT (0U) /*! RX_REQ - RX Request Interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_RX_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_RX_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_RX_REQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ - RX Rate Change Interrupt Request */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_RX_RATE_IRQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_RX_RATE_IRQ_SHIFT (0U) /*! RX_RATE_IRQ - RX Rate Change Interrupt Request */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_RX_RATE_IRQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_RX_RATE_IRQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_RX_RATE_IRQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ - RX P-State Change Interrupt Request */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_RX_PSTATE_IRQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_RX_PSTATE_IRQ_SHIFT (0U) /*! RX_PSTATE_IRQ - RX P-State Change Interrupt Request */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_RX_PSTATE_IRQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_RX_PSTATE_IRQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_RX_PSTATE_IRQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ - RX Adaptation Request Interrupt */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_RX_ADAPT_REQ_IRQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_RX_ADAPT_REQ_IRQ_SHIFT (0U) /*! RX_ADAPT_REQ_IRQ - RX Adaptation Request Interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_RX_ADAPT_REQ_IRQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_RX_ADAPT_REQ_IRQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_RX_ADAPT_REQ_IRQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ - RX Adaptation Disable Interrupt */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_RX_ADAPT_DIS_IRQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_RX_ADAPT_DIS_IRQ_SHIFT (0U) /*! RX_ADAPT_DIS_IRQ - RX Adaptation Disable Interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_RX_ADAPT_DIS_IRQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_RX_ADAPT_DIS_IRQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_RX_ADAPT_DIS_IRQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR - RX-Reset Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_RX_RESET_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_RX_RESET_IRQ_CLR_SHIFT (0U) /*! RX_RESET_IRQ_CLR - RX Reset Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_RX_RESET_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_RX_RESET_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_RX_RESET_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR - RX Request Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_RX_REQ_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_RX_REQ_IRQ_CLR_SHIFT (0U) /*! RX_REQ_IRQ_CLR - RX Request Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_RX_REQ_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_RX_REQ_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_RX_REQ_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR - RX Rate Change Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_RX_RATE_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_RX_RATE_IRQ_CLR_SHIFT (0U) /*! RX_RATE_IRQ_CLR - RX Rate Change Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_RX_RATE_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_RX_RATE_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_RX_RATE_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR - RX P-State Change Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_RX_PSTATE_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_RX_PSTATE_IRQ_CLR_SHIFT (0U) /*! RX_PSTATE_IRQ_CLR - RX P-State Change Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_RX_PSTATE_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_RX_PSTATE_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_RX_PSTATE_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR - RX Adaptation Request Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_RX_ADAPT_REQ_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_RX_ADAPT_REQ_IRQ_CLR_SHIFT (0U) /*! RX_ADAPT_REQ_IRQ_CLR - RX Adaptation Request Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_RX_ADAPT_REQ_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_RX_ADAPT_REQ_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_RX_ADAPT_REQ_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR - RX Adaptation Disable Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_RX_ADAPT_DIS_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_RX_ADAPT_DIS_IRQ_CLR_SHIFT (0U) /*! RX_ADAPT_DIS_IRQ_CLR - RX Adaptation Disable Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_RX_ADAPT_DIS_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_RX_ADAPT_DIS_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_RX_ADAPT_DIS_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_IRQ_MASK - Interrupt Mask */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_REQ_IRQ_MSK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_REQ_IRQ_MSK_SHIFT (0U) /*! RX_REQ_IRQ_MSK - Mask for RX Request Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_REQ_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_REQ_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_REQ_IRQ_MSK_MASK) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RATE_IRQ_MSK_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RATE_IRQ_MSK_SHIFT (1U) /*! RX_RATE_IRQ_MSK - Mask for RX Rate Change Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RATE_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RATE_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RATE_IRQ_MSK_MASK) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_PSTATE_IRQ_MSK_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_PSTATE_IRQ_MSK_SHIFT (2U) /*! RX_PSTATE_IRQ_MSK - Mask for RX P-State Change Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_PSTATE_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_PSTATE_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_PSTATE_IRQ_MSK_MASK) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_REQ_IRQ_MSK_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_REQ_IRQ_MSK_SHIFT (3U) /*! RX_ADAPT_REQ_IRQ_MSK - Mask for RX Adaptation Request Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_REQ_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_REQ_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_REQ_IRQ_MSK_MASK) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_DIS_IRQ_MSK_MASK (0x10U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_DIS_IRQ_MSK_SHIFT (4U) /*! RX_ADAPT_DIS_IRQ_MSK - Mask for RX Adaptation Disable Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_DIS_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_DIS_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_ADAPT_DIS_IRQ_MSK_MASK) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RESET_IRQ_MSK_MASK (0x20U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RESET_IRQ_MSK_SHIFT (5U) /*! RX_RESET_IRQ_MSK - Mask for RX Reset Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RESET_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RESET_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_RESET_IRQ_MSK_MASK) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_MPLL_RECAL_IRQ_MSK_MASK (0x40U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_MPLL_RECAL_IRQ_MSK_SHIFT (6U) /*! MPLL_RECAL_IRQ_MSK - Mask for MPLL Re-Calibration Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_MPLL_RECAL_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_MPLL_RECAL_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_MPLL_RECAL_IRQ_MSK_MASK) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_IQ_IRQ_MSK_MASK (0x80U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_IQ_IRQ_MSK_SHIFT (7U) /*! RX_IQ_IRQ_MSK - Mask for RX IQ Interrupt * 0b0..Cannot interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_IQ_IRQ_MSK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_IQ_IRQ_MSK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_RX_IQ_IRQ_MSK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ - MPLLA/B Re-Calibration Interrupt */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_MPLL_RECAL_IRQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_MPLL_RECAL_IRQ_SHIFT (0U) /*! MPLL_RECAL_IRQ - MPLLA/B Re-Calibration Interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_MPLL_RECAL_IRQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_MPLL_RECAL_IRQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_MPLL_RECAL_IRQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_CLR - MPLL Re-Calibration Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_CLR_MPLL_RECAL_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_CLR_MPLL_RECAL_IRQ_CLR_SHIFT (0U) /*! MPLL_RECAL_IRQ_CLR - MPLL Re-Calibration Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_CLR_MPLL_RECAL_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_CLR_MPLL_RECAL_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_MPLL_RECAL_IRQ_CLR_MPLL_RECAL_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ - RX IQ Interrupt */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_RX_IQ_IRQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_RX_IQ_IRQ_SHIFT (0U) /*! RX_IQ_IRQ - RX IQ Interrupt */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_RX_IQ_IRQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_RX_IQ_IRQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_RX_IQ_IRQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_CLR - RX IQ Interrupt Clear */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_CLR_RX_IQ_IRQ_CLR_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_CLR_RX_IQ_IRQ_CLR_SHIFT (0U) /*! RX_IQ_IRQ_CLR - RX IQ Interrupt Clear (Self-Clearing) */ #define ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_CLR_RX_IQ_IRQ_CLR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_CLR_RX_IQ_IRQ_CLR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_IRQ_CTL_RX_IQ_IRQ_CLR_RX_IQ_IRQ_CLR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN - Override Values for Incoming LANE Controls */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLA_EN_IN_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLA_EN_IN_SHIFT (0U) /*! LANE_MPLLA_EN_IN - Override Value for lane_mplla_en_in * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLA_EN_IN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLA_EN_IN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLA_EN_IN_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLB_EN_IN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLB_EN_IN_SHIFT (1U) /*! LANE_MPLLB_EN_IN - Override Value for lane_mpllb_en_in * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLB_EN_IN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLB_EN_IN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_MPLLB_EN_IN_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_OVRD_EN_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_OVRD_EN_SHIFT (2U) /*! LANE_OVRD_EN - Override Enable for Signals in this Register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_LANE_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT - Override Values for Outgoing LANE Controls */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLA_EN_OUT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLA_EN_OUT_SHIFT (0U) /*! LANE_MPLLA_EN_OUT - Override Value for lane_mplla_en_out * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLA_EN_OUT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLA_EN_OUT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLA_EN_OUT_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLB_EN_OUT_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLB_EN_OUT_SHIFT (1U) /*! LANE_MPLLB_EN_OUT - Override Value for lane_mpllb_en_out * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLB_EN_OUT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLB_EN_OUT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_MPLLB_EN_OUT_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_OVRD_EN_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_OVRD_EN_SHIFT (2U) /*! LANE_OVRD_EN - Override Enable for Signals in this Register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_LANE_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN - Override Values for Incoming SUP Controls from PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLA_STATE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLA_STATE_SHIFT (0U) /*! MPLLA_STATE - Override Value for mplla_state * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLA_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLA_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLA_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLB_STATE_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLB_STATE_SHIFT (1U) /*! MPLLB_STATE - Override Value for mpllb_state * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLB_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLB_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_MPLLB_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_SUP_STATE_OVRD_EN_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_SUP_STATE_OVRD_EN_SHIFT (2U) /*! SUP_STATE_OVRD_EN - Override Enable for Signals in this Register * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_SUP_STATE_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_SUP_STATE_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_SUP_STATE_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_SUP_PMA_IN - Current Values for Coming SUP Status Controls from PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLA_STATE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLA_STATE_SHIFT (0U) /*! MPLLA_STATE - Value from PMA for mplla_state */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLA_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLA_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLA_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLB_STATE_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLB_STATE_SHIFT (1U) /*! MPLLB_STATE - Value from PMA for mpllb_state */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLB_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLB_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_MPLLB_STATE_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_RTUNE_ACK_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_RTUNE_ACK_SHIFT (2U) /*! RTUNE_ACK - Value from PMA for rtune_ack */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_RTUNE_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_RTUNE_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_RTUNE_ACK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT - Override Values for Outgoing TX Controls to PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_VAL_SHIFT (0U) /*! TX_REQ_OVRD_VAL - Override Value for tx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_EN_SHIFT (1U) /*! TX_REQ_OVRD_EN - Override Enable for tx_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_REQ_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_VAL_SHIFT (2U) /*! TX_RESET_OVRD_VAL - Override Value for tx_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_EN_SHIFT (3U) /*! TX_RESET_OVRD_EN - Override Enable for tx_reset * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_TX_RESET_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_TX_PMA_IN - Current Values for Coming TX Status Controls from PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_ACK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_ACK_SHIFT (0U) /*! ACK - Value from PMA for tx_ack */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_ACK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT - Override Values for Outgoing RX Controls to PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_VAL_SHIFT (0U) /*! RX_REQ_OVRD_VAL - Override Value for rx_req * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_EN_SHIFT (1U) /*! RX_REQ_OVRD_EN - Override Enable for rx_req * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_REQ_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_VAL_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_VAL_SHIFT (2U) /*! RX_RESET_OVRD_VAL - Override Value for rx_reset * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_EN_SHIFT (3U) /*! RX_RESET_OVRD_EN - Override Enable for rx_reset * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_RX_RESET_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_RX_PMA_IN - Current Values for coming RX Status Controls from PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_ACK_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_ACK_SHIFT (0U) /*! ACK - Value from PMA for rx_ack */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_ACK_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_ACK_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL - Lane Rtune Controls */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_LANE_RTUNE_REQ_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_LANE_RTUNE_REQ_SHIFT (0U) /*! LANE_RTUNE_REQ - Lane Value for rtune_req */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_LANE_RTUNE_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_LANE_RTUNE_REQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_LANE_RTUNE_REQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_RX_OVRD_IN - Override Values for Incoming RX Controls from PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_VAL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_VAL_SHIFT (0U) /*! RX_ACK_OVRD_VAL - Override Value for rx_ack * 0b0..No override * 0b1..Override */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_VAL_MASK) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_EN_SHIFT (1U) /*! RX_ACK_OVRD_EN - Override Enable for rx_ack * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_RX_OVRD_IN_RX_ACK_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_PMA_XF_SRAM_REC_EN - SRAM Record Enable */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SRAM_REC_EN_REC_EN_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SRAM_REC_EN_REC_EN_SHIFT (0U) /*! REC_EN - Enable the SRAM Recording * 0b0..Disabled * 0b1..Enabled */ #define ENET_PHY_RAWLANE0_DIG_PMA_XF_SRAM_REC_EN_REC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_PMA_XF_SRAM_REC_EN_REC_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_PMA_XF_SRAM_REC_EN_REC_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_TX_CTL_TX_FSM_CTL - TX FSM Control */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P2_ALLOW_RXDET_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P2_ALLOW_RXDET_SHIFT (0U) /*! TX_P2_ALLOW_RXDET - If asserted, then rxdet request is allowed in P2 */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P2_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P2_ALLOW_RXDET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P2_ALLOW_RXDET_MASK) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P1_ALLOW_RXDET_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P1_ALLOW_RXDET_SHIFT (1U) /*! TX_P1_ALLOW_RXDET - If asserted, then rxdet request is allowed in P1 */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P1_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P1_ALLOW_RXDET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P1_ALLOW_RXDET_MASK) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0S_ALLOW_RXDET_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0S_ALLOW_RXDET_SHIFT (2U) /*! TX_P0S_ALLOW_RXDET - If asserted, then rxdet request is allowed in P0S */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0S_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0S_ALLOW_RXDET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0S_ALLOW_RXDET_MASK) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0_ALLOW_RXDET_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0_ALLOW_RXDET_SHIFT (3U) /*! TX_P0_ALLOW_RXDET - If asserted, then rxdet request is allowed in P0 */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0_ALLOW_RXDET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0_ALLOW_RXDET_SHIFT)) & ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_TX_P0_ALLOW_RXDET_MASK) /*! @} */ /*! @name RAWLANE0_DIG_TX_CTL_TX_CLK_CTL - Select Clock to Act as TX Input Clock */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_EN_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_EN_SHIFT (0U) /*! TX_CLK_EN - Enable the tx_clk to pma TX lane TX_CLK_EN must be de-asserted when switching TX_CLK_SEL * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_SEL_MASK (0x1EU) #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_SEL_SHIFT (1U) /*! TX_CLK_SEL - Select Clock Source for tx_pma_clk * 0b0000..tx_pcs_clk (input clock from PCS) * 0b0001..mplla_word_clk * 0b0010..mplla_dword_clk * 0b0011..mplla_qword_clk * 0b0100..mplla_oword_clk * 0b0101..mplla_div16p5_clk * 0b0110..mplla_div33_clk * 0b0111..mplla_div66_clk * 0b1000..mplla_div_clk * 0b1001..mpllb_word_clk * 0b1010..mpllb_dword_clk * 0b1011..mpllb_qword_clk * 0b1100..mpllb_oword_clk * 0b1101..mpllb_div_clk * 0b1110..rx_clk (from pma) */ #define ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_SEL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_TX_CLK_SEL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_FSM_CTL - RX FSM Control */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_EN_RX_CTL_FSM_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_EN_RX_CTL_FSM_SHIFT (0U) /*! EN_RX_CTL_FSM - Enable the RX Control FSM in the Raw PCS * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_EN_RX_CTL_FSM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_EN_RX_CTL_FSM_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_EN_RX_CTL_FSM_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_RATE_CHG_IN_P1_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_RATE_CHG_IN_P1_SHIFT (1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_RATE_CHG_IN_P1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_RATE_CHG_IN_P1_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_RATE_CHG_IN_P1_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL - RX LOS Mask Control */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_RX_LOS_MASK_CNT_MASK (0x1FFU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_RX_LOS_MASK_CNT_SHIFT (0U) /*! RX_LOS_MASK_CNT - Number of Cycles (ref_range_clk) */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_RX_LOS_MASK_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_RX_LOS_MASK_CNT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_RX_LOS_MASK_CNT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL - RX Data Enable Override Control */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_RX_DATA_EN_OVRD_CNT_MASK (0x1FU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_RX_DATA_EN_OVRD_CNT_SHIFT (0U) /*! RX_DATA_EN_OVRD_CNT - Number of ref_range cycles to override rx_data_en to 1 */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_RX_DATA_EN_OVRD_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_RX_DATA_EN_OVRD_CNT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_RX_DATA_EN_OVRD_CNT_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_INT_REF_TRCK_CNT_MASK (0xFFE0U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_INT_REF_TRCK_CNT_SHIFT (5U) /*! INT_REF_TRCK_CNT - Number of ref_range cycles to wait for integral reference tracking to settle */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_INT_REF_TRCK_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_INT_REF_TRCK_CNT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_INT_REF_TRCK_CNT_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS - RX Continuous Offset Cancellation Status */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_ENABLE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_ENABLE_SHIFT (0U) /*! ENABLE - Enable Status for RX Continuous Offset Cancellation * 0b0..Disabled * 0b1..Enabled */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_ENABLE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_ENABLE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS - RX Continuous Adaptation Status */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_ENABLE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_ENABLE_SHIFT (0U) /*! ENABLE - Enable Status for RX Continuous Adaptation * 0b0..Disabled * 0b1..Enabled */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_ENABLE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_ENABLE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE - RX Adaptation Mode */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_ADAPT_MODE_MASK (0x3U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_ADAPT_MODE_SHIFT (0U) /*! ADAPT_MODE - RX Adaptation Mode */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_ADAPT_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_ADAPT_MODE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_ADAPT_MODE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADAPT_SEL - Select Between Two Banks Adaptation Settings for RX Adaptation */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_SEL_RX_ADAPT_SEL_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_SEL_RX_ADAPT_SEL_SHIFT (0U) /*! RX_ADAPT_SEL - Select Between Two Banks Adaptation Settings for RX Adaptation */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_SEL_RX_ADAPT_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_SEL_RX_ADAPT_SEL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_SEL_RX_ADAPT_SEL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT - RX CDR PPM Drift on RX Clock */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_MASK (0x3FFFU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_SHIFT (0U) /*! RX_PPM_DRIFT - Indicates the amount of drift on RX clock when RX_PPM_DRIFT_VLD is asserted */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_VLD_MASK (0x4000U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_VLD_SHIFT (14U) /*! RX_PPM_DRIFT_VLD - Indicates if the PPM Drift is valid * 0b0..Invalid * 0b1..Valid */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_VLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_VLD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PPM_DRIFT_RX_PPM_DRIFT_VLD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_CDR_DET_STATUS - RX CDR Detector Status */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_CDR_DET_STATUS_CDR_DET_STATE_MASK (0x7U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_CDR_DET_STATUS_CDR_DET_STATE_SHIFT (0U) /*! CDR_DET_STATE - Indicate the current state for the state machine in CDR Detector */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_CDR_DET_STATUS_CDR_DET_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_CDR_DET_STATUS_CDR_DET_STATE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_CDR_DET_STATUS_CDR_DET_STATE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL - Values for Outgoing RX Controls to PMA */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CLK_SHIFT_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CLK_SHIFT_SHIFT (0U) /*! RX_CLK_SHIFT - Value for rx_clk_shift to PMA */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CLK_SHIFT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CLK_SHIFT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CLK_SHIFT_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_ALIGH_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_ALIGH_EN_SHIFT (1U) /*! RX_ALIGH_EN - Value for rx_align_en to PMA */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_ALIGH_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_ALIGH_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_ALIGH_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CDR_TRACK_EN_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CDR_TRACK_EN_SHIFT (2U) /*! RX_CDR_TRACK_EN - Value for rx_cdr_track_en to PMA */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CDR_TRACK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CDR_TRACK_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_CDR_TRACK_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_DFE_TAP1_ADAPT_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_DFE_TAP1_ADAPT_OVRD_EN_SHIFT (3U) /*! RX_DFE_TAP1_ADAPT_OVRD_EN - Enable override the DFE Tap1 to zero during RX Adaptation * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_DFE_TAP1_ADAPT_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_DFE_TAP1_ADAPT_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_MISC_CTL_RX_DFE_TAP1_ADAPT_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_PMA_EQ_IQ - RX PMA Equalization IQ Phase Value */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_EQ_IQ_RX_PMA_EQ_IQ_MASK (0x3FU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_EQ_IQ_RX_PMA_EQ_IQ_SHIFT (0U) /*! RX_PMA_EQ_IQ - RX PMA Equalization IQ Phase Value */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_EQ_IQ_RX_PMA_EQ_IQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_EQ_IQ_RX_PMA_EQ_IQ_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PMA_EQ_IQ_RX_PMA_EQ_IQ_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN - Enable RX Adapt Mode Override */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_0_OVRD_EN_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_0_OVRD_EN_SHIFT (0U) /*! RX_ADAPT_MODE_0_OVRD_EN - Enables RX adapt mode override when adapt_mode is 2'b00 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_0_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_0_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_0_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_1_OVRD_EN_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_1_OVRD_EN_SHIFT (1U) /*! RX_ADAPT_MODE_1_OVRD_EN - Enables RX adapt mode override when adapt_mode is 2'b01 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_1_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_1_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_1_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_2_OVRD_EN_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_2_OVRD_EN_SHIFT (2U) /*! RX_ADAPT_MODE_2_OVRD_EN - Enables RX adapt mode override when adapt_mode is 2'b10 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_2_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_2_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_2_OVRD_EN_MASK) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_3_OVRD_EN_MASK (0x8U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_3_OVRD_EN_SHIFT (3U) /*! RX_ADAPT_MODE_3_OVRD_EN - Enables RX adapt mode override when adapt_mode is 2'b11 * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_3_OVRD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_3_OVRD_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_OVRD_EN_RX_ADAPT_MODE_3_OVRD_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_EN - Enable Using Four Different RX Adaptation Modes */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_EN_RX_ADAPT_MODE_EN_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_EN_RX_ADAPT_MODE_EN_SHIFT (0U) /*! RX_ADAPT_MODE_EN - Enable Using Four Different RX Adaptation Modes * 0b0..Disabled * 0b1..Enabled */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_EN_RX_ADAPT_MODE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_EN_RX_ADAPT_MODE_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MODE_EN_RX_ADAPT_MODE_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADAPT_MM_FOM - RX Adaptation Mission-Mode Figure of Merit */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MM_FOM_RX_ADAPT_MM_FOM_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MM_FOM_RX_ADAPT_MM_FOM_SHIFT (0U) /*! RX_ADAPT_MM_FOM - RX Adaptation Mission-Mode Figure of Merit */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MM_FOM_RX_ADAPT_MM_FOM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MM_FOM_RX_ADAPT_MM_FOM_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_MM_FOM_RX_ADAPT_MM_FOM_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADAPT_STARTUP_FOM - RX Adaptation Startup Figure of Merit (Base Mode or Extended Mode) */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_STARTUP_FOM_RX_ADAPT_STARTUP_FOM_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_STARTUP_FOM_RX_ADAPT_STARTUP_FOM_SHIFT (0U) /*! RX_ADAPT_STARTUP_FOM - RX Adaptation Startup Figure of Merit (Base Mode or Extended Mode) */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_STARTUP_FOM_RX_ADAPT_STARTUP_FOM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_STARTUP_FOM_RX_ADAPT_STARTUP_FOM_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADAPT_STARTUP_FOM_RX_ADAPT_STARTUP_FOM_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_EVEN - RX Adapted Value of Reference Level for Error Even Slicer */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_EVEN_RX_ADPT_REF_ERR_EVEN_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_EVEN_RX_ADPT_REF_ERR_EVEN_SHIFT (0U) /*! RX_ADPT_REF_ERR_EVEN - RX Adapted Value of Reference Level for Error Even Slicer for Bank 0 */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_EVEN_RX_ADPT_REF_ERR_EVEN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_EVEN_RX_ADPT_REF_ERR_EVEN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_EVEN_RX_ADPT_REF_ERR_EVEN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_ODD - RX Adapted Value of Reference Level for Error Odd Slicer */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_ODD_RX_ADPT_REF_ERR_ODD_MASK (0xFFU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_ODD_RX_ADPT_REF_ERR_ODD_SHIFT (0U) /*! RX_ADPT_REF_ERR_ODD - RX Adapted Value of Reference Level for Error Odd Slicer */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_ODD_RX_ADPT_REF_ERR_ODD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_ODD_RX_ADPT_REF_ERR_ODD_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_ADPT_REF_ERR_ODD_RX_ADPT_REF_ERR_ODD_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_PHSADJ_MAP - RX Phase Adjust Mapped Value */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PHSADJ_MAP_RX_PHSADJ_MAP_MASK (0x3FU) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PHSADJ_MAP_RX_PHSADJ_MAP_SHIFT (0U) /*! RX_PHSADJ_MAP - Mapped Value for RX Phase Adjust */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PHSADJ_MAP_RX_PHSADJ_MAP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PHSADJ_MAP_RX_PHSADJ_MAP_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_PHSADJ_MAP_RX_PHSADJ_MAP_MASK) /*! @} */ /*! @name RAWLANE0_DIG_RX_CTL_RX_DAC_IN_USE - State of the DAC Interface */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DAC_IN_USE_DAC_IN_USE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DAC_IN_USE_DAC_IN_USE_SHIFT (0U) /*! DAC_IN_USE - State of the DAC Interface */ #define ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DAC_IN_USE_DAC_IN_USE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DAC_IN_USE_DAC_IN_USE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_RX_CTL_RX_DAC_IN_USE_DAC_IN_USE_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_2 - Adaptation Control 2 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_2_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_2_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_2_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_2_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_2_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_3 - Adaptation Control 3 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_3_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_3_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_3_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_3_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_3_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_4 - Adaptation Control 4 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_4_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_4_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_4_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_4_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_4_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_5 - Adaptation Control 5 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_5_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_5_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_5_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_5_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_5_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_6 - Adaptation Control 6 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_6_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_6_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_6_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_6_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_6_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_7 - Adaptation Control 7 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_7_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_7_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_7_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_7_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_7_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_8 - Adaptation Control 8 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_8_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_8_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_8_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_8_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_8_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_9 - Adaptation Control 9 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_9_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_9_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_9_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_9_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_9_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_10 - Adaptation Control 10 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_10_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_10_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_10_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_10_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_10_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_11 - Adaptation Control 11 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_11_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_11_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_11_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_11_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_11_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_12 - Adaptation Control 12 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_12_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_12_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_12_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_12_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_12_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_13 - Adaptation Control 13 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_13_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_13_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_13_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_13_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_13_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_14 - Adaptation Control 14 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_14_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_14_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_14_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_14_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_14_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_15 - Adaptation Control 15 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_15_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_15_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_15_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_15_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_15_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_16 - Adaptation Control 16 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_16_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_16_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_16_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_16_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_16_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_17 - Adaptation Control 17 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_17_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_17_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_17_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_17_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_17_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_18 - Adaptation Control 18 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_18_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_18_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_18_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_18_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_18_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_19 - Adaptation Control 19 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_19_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_19_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_19_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_19_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_19_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_20 - Adaptation Control 20 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_20_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_20_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_20_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_20_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_20_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_21 - Adaptation Control 21 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_21_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_21_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_21_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_21_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_21_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_22 - Adaptation Control 22 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_22_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_22_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_22_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_22_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_22_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_23 - Adaptation Control 23 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_23_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_23_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_23_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_23_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_23_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_24 - Adaptation Control 24 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_24_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_24_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_24_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_24_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_24_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_25 - Adaptation Control 25 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_25_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_25_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_25_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_25_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_25_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_ADPT_CTL_26 - Adaptation Control 26 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_26_VAL_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_26_VAL_SHIFT (0U) /*! VAL - Value of Adaptation Control */ #define ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_26_VAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_26_VAL_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_ADPT_CTL_26_VAL_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_SRAM_REC_CTRL - SRAM Record Control */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_INIT_DONE_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_INIT_DONE_SHIFT (0U) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_INIT_DONE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_INIT_DONE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_INIT_DONE_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_MODE_MASK (0x2U) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_MODE_SHIFT (1U) /*! REC_MODE - SRAM Recording Mode * 0b0..Only the first 16 records will be stored in SRAM * 0b1..The most recent 16 records (if there are) will be stored in SRAM */ #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_MODE_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_MODE_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_EN_MASK (0x4U) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_EN_SHIFT (2U) /*! REC_EN - Enable the SRAM Recording * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_EN_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_CTRL_REC_EN_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_SRAM_REC_ADDR - Current SRAM Recording Address */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ADDR_SRAM_REC_ADDR_MASK (0xFFFFU) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ADDR_SRAM_REC_ADDR_SHIFT (0U) /*! SRAM_REC_ADDR - Current SRAM Recording Address */ #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ADDR_SRAM_REC_ADDR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ADDR_SRAM_REC_ADDR_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ADDR_SRAM_REC_ADDR_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_SRAM_REC_ITER - Current Iteration Count for SRAM Recording */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ITER_SRAM_REC_ITER_MASK (0x3FFU) #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ITER_SRAM_REC_ITER_SHIFT (0U) /*! SRAM_REC_ITER - Current Iteration Count for SRAM Recording */ #define ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ITER_SRAM_REC_ITER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ITER_SRAM_REC_ITER_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_SRAM_REC_ITER_SRAM_REC_ITER_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_IQ_CTL - RX IQ Adaptation Control 1 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_IQ_ADPT_OFST_MASK (0xFU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_IQ_ADPT_OFST_SHIFT (0U) /*! IQ_ADPT_OFST - Initial IQ Offset for IQ Adaptation */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_IQ_ADPT_OFST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_IQ_ADPT_OFST_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_IQ_ADPT_OFST_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_IQ_CTL_1 - RX IQ Adaptation Control 2 */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_CENTER_MASK (0x1U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_CENTER_SHIFT (0U) /*! DPLL_THRESH_CENTER - Center of the DPLL Threshold Value * 0b0..Center is relative to the current value of DPLL frequency * 0b1..Absolute center (for example 'h8192) */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_CENTER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_CENTER_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_CENTER_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_MASK (0xFFFEU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_SHIFT (1U) /*! DPLL_THRESH - DPLL Frequency Threshold */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_IQ_CTL_1_DPLL_THRESH_MASK) /*! @} */ /*! @name RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT - RX IQ Adaptation Offset Limit */ /*! @{ */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_LEFT_LIMIT_MASK (0x1FU) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_LEFT_LIMIT_SHIFT (0U) /*! LEFT_LIMIT - Max IQ Offset from Calibrated IQ for Left-Side IQ Sweep */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_LEFT_LIMIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_LEFT_LIMIT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_LEFT_LIMIT_MASK) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_RIGHT_LIMIT_MASK (0x3E0U) #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_RIGHT_LIMIT_SHIFT (5U) /*! RIGHT_LIMIT - Max IQ Offset from Calibrated IQ for Right-Side IQ Sweep */ #define ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_RIGHT_LIMIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_RIGHT_LIMIT_SHIFT)) & ENET_PHY_RAWLANE0_DIG_AON_RX_ADPT_IQ_LIMIT_RIGHT_LIMIT_MASK) /*! @} */ /*! @name RAWMEM_D_ROM_CMN_B_R - Common Memory #0, Bank #0, Reg #0..Common Memory #63, Bank #7, Reg #31 */ /*! @{ */ #define ENET_PHY_RAWMEM_D_ROM_CMN_B_R_DAT_MASK (0xFFFFU) #define ENET_PHY_RAWMEM_D_ROM_CMN_B_R_DAT_SHIFT (0U) /*! DAT - Memory Data */ #define ENET_PHY_RAWMEM_D_ROM_CMN_B_R_DAT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWMEM_D_ROM_CMN_B_R_DAT_SHIFT)) & ENET_PHY_RAWMEM_D_ROM_CMN_B_R_DAT_MASK) /*! @} */ /* The count of ENET_PHY_RAWMEM_D_ROM_CMN_B_R */ #define ENET_PHY_RAWMEM_D_ROM_CMN_B_R_COUNT (64U) /* The count of ENET_PHY_RAWMEM_D_ROM_CMN_B_R */ #define ENET_PHY_RAWMEM_D_ROM_CMN_B_R_COUNT2 (8U) /* The count of ENET_PHY_RAWMEM_D_ROM_CMN_B_R */ #define ENET_PHY_RAWMEM_D_ROM_CMN_B_R_COUNT3 (32U) /*! @name RAWMEM_D_RAM_CMN_B_R - Common Memory #0, Bank #0, Reg #0..Common Memory #63, Bank #7, Reg #31 */ /*! @{ */ #define ENET_PHY_RAWMEM_D_RAM_CMN_B_R_DAT_MASK (0xFFFFU) #define ENET_PHY_RAWMEM_D_RAM_CMN_B_R_DAT_SHIFT (0U) /*! DAT - Memory Data */ #define ENET_PHY_RAWMEM_D_RAM_CMN_B_R_DAT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_RAWMEM_D_RAM_CMN_B_R_DAT_SHIFT)) & ENET_PHY_RAWMEM_D_RAM_CMN_B_R_DAT_MASK) /*! @} */ /* The count of ENET_PHY_RAWMEM_D_RAM_CMN_B_R */ #define ENET_PHY_RAWMEM_D_RAM_CMN_B_R_COUNT (64U) /* The count of ENET_PHY_RAWMEM_D_RAM_CMN_B_R */ #define ENET_PHY_RAWMEM_D_RAM_CMN_B_R_COUNT2 (8U) /* The count of ENET_PHY_RAWMEM_D_RAM_CMN_B_R */ #define ENET_PHY_RAWMEM_D_RAM_CMN_B_R_COUNT3 (32U) /*! * @} */ /* end of group ENET_PHY_Register_Masks */ #define ENET_PHY_BASE (0x0u) #define ENET_PHY ((ENET_PHY_Type *)ENET_PHY_BASE) #define ENET_PHY_BASE_ADDRS { ENET_PHY_BASE } #define ENET_PHY_BASE_PTRS { ENET_PHY } /*! * @} */ /* end of group ENET_PHY_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET_PHY_CTRL_EX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_CTRL_EX_Peripheral_Access_Layer ENET_PHY_CTRL_EX Peripheral Access Layer * @{ */ /** ENET_PHY_CTRL_EX - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[276]; __IO uint16_t GLOBAL_CTRL_EX_0; /**< PHY Global Extra Control 0, offset: 0x114 */ uint8_t RESERVED_1[2]; __IO uint16_t GLOBAL_CTRL_EX_1; /**< PHY Global Extra Control 1, offset: 0x118 */ uint8_t RESERVED_2[10]; __IO uint16_t GLOBAL_CTRL_EX_4; /**< PHY Global Extra Control 2, offset: 0x124 */ uint8_t RESERVED_3[130950]; __IO uint16_t MPLLA_CTRL_EX_0; /**< MPLLA Extra Control, offset: 0x200AC */ uint8_t RESERVED_4[131070]; __IO uint16_t MPLLB_CTRL_EX_0; /**< MPLLB Extra Control, offset: 0x400AC */ } ENET_PHY_CTRL_EX_Type; /* ---------------------------------------------------------------------------- -- ENET_PHY_CTRL_EX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_CTRL_EX_Register_Masks ENET_PHY_CTRL_EX Register Masks * @{ */ /*! @name GLOBAL_CTRL_EX_0 - PHY Global Extra Control 0 */ /*! @{ */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS_MASK (0x1U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS_SHIFT (0U) /*! PHY_SRAM_BYPASS - SRAM Bypass * 0b0..No bypass * 0b1..Bypass */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS_MASK) /*! @} */ /*! @name GLOBAL_CTRL_EX_1 - PHY Global Extra Control 1 */ /*! @{ */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_FLYOVER_EN_MASK (0x1U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_FLYOVER_EN_SHIFT (0U) /*! PHY_TEST_FLYOVER_EN - Enable Flyover Test Mode * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_FLYOVER_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_FLYOVER_EN_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_FLYOVER_EN_MASK) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_STOP_CLK_EN_MASK (0x10U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_STOP_CLK_EN_SHIFT (4U) /*! PHY_TEST_STOP_CLK_EN - Stop Clock Test Mode Enable */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_STOP_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_STOP_CLK_EN_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_1_PHY_TEST_STOP_CLK_EN_MASK) /*! @} */ /*! @name GLOBAL_CTRL_EX_4 - PHY Global Extra Control 2 */ /*! @{ */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_VPH_NOMINAL_MASK (0x3U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_VPH_NOMINAL_SHIFT (0U) /*! PHY_VPH_NOMINAL - VPH Nominal Selection * 0b00, 0b01..Reserved * 0b10..1.5 V * 0b11..1.8 V */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_VPH_NOMINAL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_VPH_NOMINAL_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_VPH_NOMINAL_MASK) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PCS_PWR_STABLE_MASK (0x100U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PCS_PWR_STABLE_SHIFT (8U) /*! PHY_PCS_PWR_STABLE - Power Stable for Raw PCS * 0b0..Not stable * 0b1..Stable */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PCS_PWR_STABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PCS_PWR_STABLE_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PCS_PWR_STABLE_MASK) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_MODE_EN_MASK (0x400U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_MODE_EN_SHIFT (10U) /*! PHY_PG_MODE_EN - Power Gating Support Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_MODE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_MODE_EN_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_MODE_EN_MASK) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_RESET_MASK (0x1000U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_RESET_SHIFT (12U) /*! PHY_PG_RESET - Power Gated Reset * 0b0..No reset * 0b1..Reset */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_RESET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_RESET_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PG_RESET_MASK) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PMA_PWR_STABLE_MASK (0x4000U) #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PMA_PWR_STABLE_SHIFT (14U) /*! PHY_PMA_PWR_STABLE - Power Stable for PMA * 0b0..Not stable * 0b1..Stable */ #define ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PMA_PWR_STABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PMA_PWR_STABLE_SHIFT)) & ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_4_PHY_PMA_PWR_STABLE_MASK) /*! @} */ /*! @name MPLLA_CTRL_EX_0 - MPLLA Extra Control */ /*! @{ */ #define ENET_PHY_CTRL_EX_MPLLA_CTRL_EX_0_PHY_MPLLA_FORCE_EN_MASK (0x1U) #define ENET_PHY_CTRL_EX_MPLLA_CTRL_EX_0_PHY_MPLLA_FORCE_EN_SHIFT (0U) /*! PHY_MPLLA_FORCE_EN - MPLLA Force Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_CTRL_EX_MPLLA_CTRL_EX_0_PHY_MPLLA_FORCE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_MPLLA_CTRL_EX_0_PHY_MPLLA_FORCE_EN_SHIFT)) & ENET_PHY_CTRL_EX_MPLLA_CTRL_EX_0_PHY_MPLLA_FORCE_EN_MASK) /*! @} */ /*! @name MPLLB_CTRL_EX_0 - MPLLB Extra Control */ /*! @{ */ #define ENET_PHY_CTRL_EX_MPLLB_CTRL_EX_0_PHY_MPLLB_FORCE_EN_MASK (0x1U) #define ENET_PHY_CTRL_EX_MPLLB_CTRL_EX_0_PHY_MPLLB_FORCE_EN_SHIFT (0U) /*! PHY_MPLLB_FORCE_EN - MPLLA Force Enable * 0b0..Disables * 0b1..Enables */ #define ENET_PHY_CTRL_EX_MPLLB_CTRL_EX_0_PHY_MPLLB_FORCE_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_CTRL_EX_MPLLB_CTRL_EX_0_PHY_MPLLB_FORCE_EN_SHIFT)) & ENET_PHY_CTRL_EX_MPLLB_CTRL_EX_0_PHY_MPLLB_FORCE_EN_MASK) /*! @} */ /*! * @} */ /* end of group ENET_PHY_CTRL_EX_Register_Masks */ #define ENET_PHY_CTRL_EX_BASE (0x0u) #define ENET_PHY_CTRL_EX ((ENET_PHY_CTRL_EX_Type *)ENET_PHY_CTRL_EX_BASE) #define ENET_PHY_CTRL_EX_BASE_ADDRS { ENET_PHY_CTRL_EX_BASE } #define ENET_PHY_CTRL_EX_BASE_PTRS { ENET_PHY_CTRL_EX } /*! * @} */ /* end of group ENET_PHY_CTRL_EX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET_PHY_MAC_ADAPTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_MAC_ADAPTER_Peripheral_Access_Layer ENET_PHY_MAC_ADAPTER Peripheral Access Layer * @{ */ /** ENET_PHY_MAC_ADAPTER - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[512]; __IO uint16_t MAC_ADAPTER_LOCK_PHY; /**< PHY Lock, offset: 0x200 */ uint8_t RESERVED_1[2]; __IO uint16_t MAC_ADAPTER_LOCK_MPLLA; /**< MPLLA Lock, offset: 0x204 */ uint8_t RESERVED_2[2]; __IO uint16_t MAC_ADAPTER_LOCK_MPLLB; /**< MPLLB Lock, offset: 0x208 */ uint8_t RESERVED_3[2]; __IO uint16_t MAC_ADAPTER_LOCK_ROM; /**< ROM Lock, offset: 0x20C */ uint8_t RESERVED_4[2]; __IO uint16_t MAC_ADAPTER_LOCK_RAM; /**< RAM Lock, offset: 0x210 */ uint8_t RESERVED_5[2]; __IO uint16_t MAC_ADAPTER_ERROR_EVENT; /**< Error Event for FIFO, offset: 0x214 */ } ENET_PHY_MAC_ADAPTER_Type; /* ---------------------------------------------------------------------------- -- ENET_PHY_MAC_ADAPTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_MAC_ADAPTER_Register_Masks ENET_PHY_MAC_ADAPTER Register Masks * @{ */ /*! @name MAC_ADAPTER_LOCK_PHY - PHY Lock */ /*! @{ */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_OWNER_MASK (0xFU) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_OWNER_SHIFT (0U) /*! LOCK_OWNER - Lock Owner */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_OWNER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_OWNER_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_OWNER_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_MASK (0x80U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_SHIFT (7U) /*! LOCK - Lock Bit * 0b0..Unlocked * 0b1..Locked */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_WHOAMI_MASK (0xF000U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_WHOAMI_SHIFT (12U) /*! WHOAMI - Port ID */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_WHOAMI(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_WHOAMI_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_WHOAMI_MASK) /*! @} */ /*! @name MAC_ADAPTER_LOCK_MPLLA - MPLLA Lock */ /*! @{ */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_OWNER_MASK (0xFU) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_OWNER_SHIFT (0U) /*! LOCK_OWNER - Lock Owner */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_OWNER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_OWNER_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_OWNER_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_MASK (0x80U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_SHIFT (7U) /*! LOCK - Lock Bit * 0b0..Unlocked * 0b1..Locked */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_WHOAMI_MASK (0xF000U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_WHOAMI_SHIFT (12U) /*! WHOAMI - Port ID */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_WHOAMI(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_WHOAMI_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_WHOAMI_MASK) /*! @} */ /*! @name MAC_ADAPTER_LOCK_MPLLB - MPLLB Lock */ /*! @{ */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_OWNER_MASK (0xFU) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_OWNER_SHIFT (0U) /*! LOCK_OWNER - Lock Owner */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_OWNER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_OWNER_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_OWNER_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_MASK (0x80U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_SHIFT (7U) /*! LOCK - Lock Bit * 0b0..Unlocked * 0b1..Locked */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_WHOAMI_MASK (0xF000U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_WHOAMI_SHIFT (12U) /*! WHOAMI - Port ID */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_WHOAMI(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_WHOAMI_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_WHOAMI_MASK) /*! @} */ /*! @name MAC_ADAPTER_LOCK_ROM - ROM Lock */ /*! @{ */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_OWNER_MASK (0xFU) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_OWNER_SHIFT (0U) /*! LOCK_OWNER - Lock Owner */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_OWNER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_OWNER_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_OWNER_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_MASK (0x80U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_SHIFT (7U) /*! LOCK - Lock Bit * 0b0..Unlocked * 0b1..Locked */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_WHOAMI_MASK (0xF000U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_WHOAMI_SHIFT (12U) /*! WHOAMI - Port ID */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_WHOAMI(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_WHOAMI_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_WHOAMI_MASK) /*! @} */ /*! @name MAC_ADAPTER_LOCK_RAM - RAM Lock */ /*! @{ */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_OWNER_MASK (0xFU) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_OWNER_SHIFT (0U) /*! LOCK_OWNER - Lock Owner */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_OWNER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_OWNER_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_OWNER_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_MASK (0x80U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_SHIFT (7U) /*! LOCK - Lock Bit * 0b0..Unlocked * 0b1..Locked */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_WHOAMI_MASK (0xF000U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_WHOAMI_SHIFT (12U) /*! WHOAMI - Port ID */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_WHOAMI(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_WHOAMI_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_WHOAMI_MASK) /*! @} */ /*! @name MAC_ADAPTER_ERROR_EVENT - Error Event for FIFO */ /*! @{ */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_RX_FIFO_OVF_MASK (0x1U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_RX_FIFO_OVF_SHIFT (0U) /*! SGMII_RX_FIFO_OVF - FIFO Overflow for SGMII RX Path * 0b0..No event * 0b1..Overflow detected */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_RX_FIFO_OVF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_RX_FIFO_OVF_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_RX_FIFO_OVF_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_TX_FIFO_UDF_MASK (0x10U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_TX_FIFO_UDF_SHIFT (4U) /*! SGMII_TX_FIFO_UDF - FIFO Underflow for SGMII TX Path * 0b0..No event * 0b1..Underflow detected */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_TX_FIFO_UDF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_TX_FIFO_UDF_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_SGMII_TX_FIFO_UDF_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_RX_FIFO_OVF_MASK (0x100U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_RX_FIFO_OVF_SHIFT (8U) /*! XGMII_RX_FIFO_OVF - FIFO Overflow for XGMII RX Path * 0b0..No event * 0b1..Overflow detected */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_RX_FIFO_OVF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_RX_FIFO_OVF_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_RX_FIFO_OVF_MASK) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_TX_FIFO_UDF_MASK (0x1000U) #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_TX_FIFO_UDF_SHIFT (12U) /*! XGMII_TX_FIFO_UDF - FIFO Underflow for XGMII TX Path * 0b0..No event * 0b1..Underflow detected */ #define ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_TX_FIFO_UDF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_TX_FIFO_UDF_SHIFT)) & ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_ERROR_EVENT_XGMII_TX_FIFO_UDF_MASK) /*! @} */ /*! * @} */ /* end of group ENET_PHY_MAC_ADAPTER_Register_Masks */ /* ENET_PHY_MAC_ADAPTER - Peripheral instance base addresses */ /** Peripheral ENET_PHY_MAC_ADAPTER base address */ #define ENET_PHY_MAC_ADAPTER_BASE (0x3E0000u) /** Peripheral ENET_PHY_MAC_ADAPTER base pointer */ #define ENET_PHY_MAC_ADAPTER ((ENET_PHY_MAC_ADAPTER_Type *)ENET_PHY_MAC_ADAPTER_BASE) /** Array initializer of ENET_PHY_MAC_ADAPTER peripheral base addresses */ #define ENET_PHY_MAC_ADAPTER_BASE_ADDRS { ENET_PHY_MAC_ADAPTER_BASE } /** Array initializer of ENET_PHY_MAC_ADAPTER peripheral base pointers */ #define ENET_PHY_MAC_ADAPTER_BASE_PTRS { ENET_PHY_MAC_ADAPTER } /*! * @} */ /* end of group ENET_PHY_MAC_ADAPTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET_PHY_PMA_MMD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_PMA_MMD_Peripheral_Access_Layer ENET_PHY_PMA_MMD Peripheral Access Layer * @{ */ /** ENET_PHY_PMA_MMD - Register Layout Typedef */ typedef struct { __IO uint16_t SR_PMA_CTRL1; /**< SR PMA MMD Control 1, offset: 0x0 */ __I uint16_t SR_PMA_STATUS1; /**< SR PMA MMD Status1, offset: 0x2 */ __I uint16_t SR_PMA_DEV_ID_1; /**< SR PMA MMD Device Identifier 1, offset: 0x4 */ __I uint16_t SR_PMA_DEV_ID_2; /**< SR PMA MMD Device Identifier 2, offset: 0x6 */ __I uint16_t SR_PMA_SPD_ABL; /**< SR PMA MMD Speed Ability, offset: 0x8 */ __I uint16_t SR_PMA_DEV_PKG1; /**< SR PMA MMD Devices in Package 1, offset: 0xA */ __I uint16_t SR_PMA_DEV_PKG2; /**< SR PMA MMD Devices in Package 2, offset: 0xC */ uint8_t RESERVED_0[2]; __I uint16_t SR_PMA_STATUS2; /**< SR PMA MMD Status 2, offset: 0x10 */ __IO uint16_t SR_PMA_TX_DIS; /**< SR PMA MMD Transmit Disable, offset: 0x12 */ __I uint16_t SR_PMA_RX_SIG_DET; /**< SR PMA MMD Receive Signal Detect, offset: 0x14 */ __I uint16_t SR_PMA_EXT_ABL; /**< SR PMA or PMD Extended Ability, offset: 0x16 */ uint8_t RESERVED_1[4]; __I uint16_t SR_PMA_PKG1; /**< SR PMA MMD Package Identifier 1, offset: 0x1C */ __I uint16_t SR_PMA_PKG2; /**< SR PMA MMD Package Identifier 2, offset: 0x1E */ uint8_t RESERVED_2[10]; __I uint16_t SR_PMA_2PT5G_5G_EXT_ABL; /**< SR PMA MMD 2.5G/5G Extended Ability, offset: 0x2A */ uint8_t RESERVED_3[3556]; __I uint16_t SR_PMA_TIME_SYNC_PMA_ABL; /**< SR PMA MMD Time Sync Capability, offset: 0xE10 */ __I uint16_t SR_PMA_TIME_SYNC_TX_MAX_DLY_LWR; /**< SR PMA MMD Time Sync TX Max Delay Lower, offset: 0xE12 */ __I uint16_t SR_PMA_TIME_SYNC_TX_MAX_DLY_UPR; /**< SR PMA MMD Time Sync TX Max Delay Upper, offset: 0xE14 */ __I uint16_t SR_PMA_TIME_SYNC_TX_MIN_DLY_LWR; /**< SR PMA MMD Time Sync TX Min Delay Lower, offset: 0xE16 */ __I uint16_t SR_PMA_TIME_SYNC_TX_MIN_DLY_UPR; /**< SR PMA MMD Time Sync TX Min Delay Upper, offset: 0xE18 */ __I uint16_t SR_PMA_TIME_SYNC_RX_MAX_DLY_LWR; /**< SR PMA MMD Time Sync RX Max Delay Lower, offset: 0xE1A */ __I uint16_t SR_PMA_TIME_SYNC_RX_MAX_DLY_UPR; /**< SR PMA MMD Time Sync RX Max Delay Upper, offset: 0xE1C */ __I uint16_t SR_PMA_TIME_SYNC_RX_MIN_DLY_LWR; /**< SR PMA MMD Time Sync RX Min Delay Lower, offset: 0xE1E */ __I uint16_t SR_PMA_TIME_SYNC_RX_MIN_DLY_UPR; /**< SR PMA MMD Time Sync RX Min Delay Upper, offset: 0xE20 */ uint8_t RESERVED_4[61918]; __IO uint16_t VR_PMA_DIG_CTRL1; /**< VR PMA MMD Digital Control 1, offset: 0x10000 */ uint8_t RESERVED_5[30]; __I uint16_t VR_PMA_DIG_STS; /**< VR PMA MMD Digital Status, offset: 0x10020 */ uint8_t RESERVED_6[30]; __I uint16_t VR_XS_PMA_RX_LSTS; /**< VR XS or PMA PHY RX Lane Status, offset: 0x10040 */ uint8_t RESERVED_7[30]; __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX General 0, offset: 0x10060 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX General 1, offset: 0x10062 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_TX_GENCTRL2; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY TX General 2, offset: 0x10064 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Boost Control, offset: 0x10066 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Rate Control, offset: 0x10068 */ __IO uint16_t MP_12G_16G_25G_TX_POWER_STATE_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Power State, offset: 0x1006A */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Equalization Control 0, offset: 0x1006C */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Equalization Control 1, offset: 0x1006E */ uint8_t RESERVED_8[8]; __IO uint16_t VR_XS_PMA_MP_16G_25G_TX_GENCTRL3; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY TX General Control 3, offset: 0x10078 */ __IO uint16_t VR_XS_PMA_MP_16G_25G_TX_GENCTRL4; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY TX General Control 4, offset: 0x1007A */ __IO uint16_t VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY TX Miscellaneous Control 0, offset: 0x1007C */ uint8_t RESERVED_9[2]; __I uint16_t VR_XS_PMA_MP_12G_16G_25G_TX_STS; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Status, offset: 0x10080 */ uint8_t RESERVED_10[30]; __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX General Control 0, offset: 0x100A0 */ __IO uint16_t MP_12G_16G_25G_RX_GENCTRL1; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX General Control 1, offset: 0x100A2 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_RX_GENCTRL2; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY RX General Control 2, offset: 0x100A4 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_RX_GENCTRL3; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY RX General Control 3, offset: 0x100A6 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Rate Control, offset: 0x100A8 */ __IO uint16_t MP_12G_16G_25G_RX_POWER_STATE_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Power State, offset: 0x100AA */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX CDR Control, offset: 0x100AC */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Attenuation Control, offset: 0x100AE */ __IO uint16_t VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX Equalization Control 0, offset: 0x100B0 */ uint8_t RESERVED_11[6]; __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Equalization Control 4, offset: 0x100B8 */ __IO uint16_t VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX Equalization Control 5, offset: 0x100BA */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY DFE Tap Control 0, offset: 0x100BC */ uint8_t RESERVED_12[2]; __I uint16_t VR_XS_PMA_MP_12G_16G_25G_RX_STS; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Status, offset: 0x100C0 */ __I uint16_t VR_XS_PMA_MP_16G_25G_RX_PPM_STS0; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX PPM Status 0, offset: 0x100C2 */ uint8_t RESERVED_13[4]; __IO uint16_t VR_XS_PMA_MP_16G_RX_CDR_CTRL1; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY RX CDR Control 1, offset: 0x100C8 */ __IO uint16_t VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX PPM Control 0, offset: 0x100CA */ uint8_t RESERVED_14[4]; __IO uint16_t VR_XS_PMA_MP_16G_25G_RX_GENCTRL4; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX General Control 4, offset: 0x100D0 */ __IO uint16_t VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX Miscellaneous Control 0, offset: 0x100D2 */ uint8_t RESERVED_15[2]; __IO uint16_t VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX IQ Control 0, offset: 0x100D6 */ uint8_t RESERVED_16[8]; __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY MPLL Common Control, offset: 0x100E0 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLA Control 0, offset: 0x100E2 */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLA_CTRL1; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 1, offset: 0x100E4 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLA Control 2, offset: 0x100E6 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLB Control 0, offset: 0x100E8 */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLB_CTRL1; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 1, offset: 0x100EA */ __IO uint16_t VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLB Control 2, offset: 0x100EC */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLA_CTRL3; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 3, offset: 0x100EE */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLB_CTRL3; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 3, offset: 0x100F0 */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLA_CTRL4; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 4, offset: 0x100F2 */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLA_CTRL5; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 5, offset: 0x100F4 */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLB_CTRL4; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 4, offset: 0x100F6 */ __IO uint16_t VR_XS_PMA_MP_16G_MPLLB_CTRL5; /**< VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 5, offset: 0x100F8 */ uint8_t RESERVED_17[38]; __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Miscellaneous Control 0, offset: 0x10120 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Reference Control, offset: 0x10122 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY VCO Calibration Load 0, offset: 0x10124 */ uint8_t RESERVED_18[6]; __IO uint16_t VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY VCO Calibration Reference 0, offset: 0x1012C */ uint8_t RESERVED_19[2]; __I uint16_t VR_XS_PMA_MP_12G_16G_25G_MISC_STS; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Miscellaneous Status, offset: 0x10130 */ __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL1; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Miscellaneous Control 1, offset: 0x10132 */ uint8_t RESERVED_20[2]; __IO uint16_t VR_XS_PMA_MP_12G_16G_25G_SRAM; /**< VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY SRAM, offset: 0x10136 */ __IO uint16_t VR_XS_PMA_MP_16G_25G_MISC_CTRL2; /**< VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY Miscellaneous Control 2, offset: 0x10138 */ uint8_t RESERVED_21[6]; __IO uint16_t VR_XS_PMA_SNPS_CR_CTRL; /**< VR XS or PMA Synopsys PHY CR Control, offset: 0x10140 */ __IO uint16_t VR_XS_PMA_SNPS_CR_ADDR; /**< VR XS or PMA Synopsys PHY CR Address, offset: 0x10142 */ __IO uint16_t VR_XS_PMA_SNPS_CR_DATA; /**< VR XS or PMA Synopsys CR Data, offset: 0x10144 */ } ENET_PHY_PMA_MMD_Type; /* ---------------------------------------------------------------------------- -- ENET_PHY_PMA_MMD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_PMA_MMD_Register_Masks ENET_PHY_PMA_MMD Register Masks * @{ */ /*! @name SR_PMA_CTRL1 - SR PMA MMD Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LB_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LB_SHIFT (0U) /*! LB - Loopback Enable * 0b0..DWC_XPCS de-asserts the xgxs_loopback_en_o{lane} signal * 0b1..DWC_XPCS asserts the xgxs_loopback_en_o{lane} signal */ #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LB(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LB_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LB_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS_5_2_MASK (0x3CU) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS_5_2_SHIFT (2U) /*! SS_5_2 - Speed Selection Bits[5:2] */ #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS_5_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS_5_2_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS_5_2_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS6_MASK (0x40U) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS6_SHIFT (6U) /*! SS6 - Speed Selection Bit 6 */ #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS6(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS6_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS6_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LPM_MASK (0x800U) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LPM_SHIFT (11U) /*! LPM - Low-Power Enable * 0b0..Normal operation * 0b1..DWC_XPCS enters power-down mode along with the PHY */ #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LPM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LPM_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_CTRL1_LPM_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS13_MASK (0x2000U) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS13_SHIFT (13U) /*! SS13 - Speed Selection * 0b0..DWC_XPCS is in the 1000BASEX-Only PCS mode (1G speed) * 0b1..DWC_XPCS is in the 10GBASE-X PCS mode (10G speed) */ #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS13(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS13_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_CTRL1_SS13_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_RST_MASK (0x8000U) #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_RST_SHIFT (15U) /*! RST - Soft Reset (RW, SC Type) */ #define ENET_PHY_PMA_MMD_SR_PMA_CTRL1_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_CTRL1_RST_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_CTRL1_RST_MASK) /*! @} */ /*! @name SR_PMA_STATUS1 - SR PMA MMD Status1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_LPMS_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_LPMS_SHIFT (1U) /*! LPMS - Low-Power Mode Support */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_LPMS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS1_LPMS_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS1_LPMS_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_RLU_MASK (0x4U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_RLU_SHIFT (2U) /*! RLU - RX Link Up (RO,LL Type) * 0b0..Goes low when the CDR status of the PHY goes low (indicated by xgxs_rx_valid_i{lane}) * 0b1..Set when the CDR status of the PHY goes high (indicated by xgxs_rx_valid_i{lane}) */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_RLU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS1_RLU_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS1_RLU_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_FLT_MASK (0x80U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_FLT_SHIFT (7U) /*! FLT - Fault Condition Detected */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS1_FLT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS1_FLT_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS1_FLT_MASK) /*! @} */ /*! @name SR_PMA_DEV_ID_1 - SR PMA MMD Device Identifier 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_1_PMA_DEV_OUI_3_18_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_1_PMA_DEV_OUI_3_18_SHIFT (0U) /*! PMA_DEV_OUI_3_18 - Organizationally Unique Identifier [3:18] */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_1_PMA_DEV_OUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_1_PMA_DEV_OUI_3_18_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_1_PMA_DEV_OUI_3_18_MASK) /*! @} */ /*! @name SR_PMA_DEV_ID_2 - SR PMA MMD Device Identifier 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_RN_3_0_MASK (0xFU) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_RN_3_0_SHIFT (0U) /*! PMA_DEV_RN_3_0 - Revision Number */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_RN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_RN_3_0_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_RN_3_0_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_MMN_5_0_MASK (0x3F0U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_MMN_5_0_SHIFT (4U) /*! PMA_DEV_MMN_5_0 - Model Number */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_MMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_MMN_5_0_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_MMN_5_0_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_OUI_19_24_MASK (0xFC00U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_OUI_19_24_SHIFT (10U) /*! PMA_DEV_OUI_19_24 - Organizationally Unique Identifier [19:24] */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_OUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_OUI_19_24_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_ID_2_PMA_DEV_OUI_19_24_MASK) /*! @} */ /*! @name SR_PMA_SPD_ABL - SR PMA MMD Speed Ability */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_XGC_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_XGC_SHIFT (0U) /*! XGC - 10G Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_XGC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_XGC_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_XGC_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_GC_MASK (0x10U) #define ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_GC_SHIFT (4U) /*! GC - 1G Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_GC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_GC_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_SPD_ABL_GC_MASK) /*! @} */ /*! @name SR_PMA_DEV_PKG1 - SR PMA MMD Devices in Package 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_CLS22_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_CLS22_SHIFT (0U) /*! CLS22 - Clause 22 Register Support */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_CLS22(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_CLS22_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_CLS22_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PMA_PMD_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PMA_PMD_SHIFT (1U) /*! PMA_PMD - PMA or PMD MMD * 0b1..10GBASE-X PCS for Synopsys PHY, 10GBASE-R PCS for Synopsys PHY * 0b0..All other configurations */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PMA_PMD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PMA_PMD_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PMA_PMD_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_WIS_MASK (0x4U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_WIS_SHIFT (2U) /*! WIS - WIS MMD */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_WIS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_WIS_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_WIS_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PCS_MASK (0x8U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PCS_SHIFT (3U) /*! PCS - PCS MMD * 0b1..MAIN_MODE = 10GBASE-X PCS, or 10GBASE-R PCS * 0b0..All other configurations */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PCS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PCS_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PCS_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PHYXS_MASK (0x10U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PHYXS_SHIFT (4U) /*! PHYXS - PHY XGXS MMD */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PHYXS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PHYXS_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_PHYXS_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_DTEXS_MASK (0x20U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_DTEXS_SHIFT (5U) /*! DTEXS - DTE XGXS MMD */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_DTEXS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_DTEXS_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_DTEXS_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_TC_MASK (0x40U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_TC_SHIFT (6U) /*! TC - TC MMD */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_TC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_TC_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_TC_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_AN_MASK (0x80U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_AN_SHIFT (7U) /*! AN - Auto-Negotiation MMD */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_AN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_AN_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG1_AN_MASK) /*! @} */ /*! @name SR_PMA_DEV_PKG2 - SR PMA MMD Devices in Package 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD1_MASK (0x4000U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD1_SHIFT (14U) /*! VSD1 - Vendor-Specific Device 1 */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD1_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD1_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD2_MASK (0x8000U) #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD2_SHIFT (15U) /*! VSD2 - Vendor-Specific Device 2 */ #define ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD2_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_DEV_PKG2_VSD2_MASK) /*! @} */ /*! @name SR_PMA_STATUS2 - SR PMA MMD Status 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PMA_LOOP_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PMA_LOOP_SHIFT (0U) /*! PMA_LOOP - PMA Loopback Ability */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PMA_LOOP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PMA_LOOP_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PMA_LOOP_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGEWEN_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGEWEN_SHIFT (1U) /*! XGEWEN - 10GBASE-EW Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGEWEN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGEWEN_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGEWEN_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGLWEN_MASK (0x4U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGLWEN_SHIFT (2U) /*! XGLWEN - 10GBASE-LW Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGLWEN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGLWEN_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGLWEN_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGSWEN_MASK (0x8U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGSWEN_SHIFT (3U) /*! XGSWEN - 10GBASE-SW Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGSWEN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGSWEN_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_XGSWEN_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LX4_ABL_MASK (0x10U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LX4_ABL_SHIFT (4U) /*! LX4_ABL - 10GBASE-LX4 Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LX4_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LX4_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LX4_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_ER_ABL_MASK (0x20U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_ER_ABL_SHIFT (5U) /*! ER_ABL - 10GBASE-ER Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_ER_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_ER_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_ER_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LR_ABL_MASK (0x40U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LR_ABL_SHIFT (6U) /*! LR_ABL - 10GBASE-LR Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LR_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LR_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_LR_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_SR_ABL_MASK (0x80U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_SR_ABL_SHIFT (7U) /*! SR_ABL - 10GBASE-SR Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_SR_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_SR_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_SR_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TD_ABL_MASK (0x100U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TD_ABL_SHIFT (8U) /*! TD_ABL - PMA TX Disable Ability */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TD_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TD_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TD_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_EXT_ABL_MASK (0x200U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_EXT_ABL_SHIFT (9U) /*! EXT_ABL - Extended Ability */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_EXT_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_EXT_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_EXT_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_RF_MASK (0x400U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_RF_SHIFT (10U) /*! RF - Receiver Fault (LH Type) */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_RF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_RF_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_RF_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TF_MASK (0x800U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TF_SHIFT (11U) /*! TF - Transmitter Fault */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TF_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_TF_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PRFA_MASK (0x1000U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PRFA_SHIFT (12U) /*! PRFA - PMA RX Fault Ability */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PRFA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PRFA_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PRFA_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PTFA_MASK (0x2000U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PTFA_SHIFT (13U) /*! PTFA - PMA TX Fault Ability */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PTFA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PTFA_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_PTFA_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_DP_MASK (0xC000U) #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_DP_SHIFT (14U) /*! DP - Device Present Status * 0b10..PMA MMD is present and responding to this register address * *..PMA MMD is not present or not functioning properly */ #define ENET_PHY_PMA_MMD_SR_PMA_STATUS2_DP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_STATUS2_DP_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_STATUS2_DP_MASK) /*! @} */ /*! @name SR_PMA_TX_DIS - SR PMA MMD Transmit Disable */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_GTD_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_GTD_SHIFT (0U) /*! GTD - Global Transmit Disable */ #define ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_GTD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_GTD_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_GTD_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_PMA_TX_DIS_0_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_PMA_TX_DIS_0_SHIFT (1U) /*! PMA_TX_DIS_0 - Transmit Disable on Lane 0 */ #define ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_PMA_TX_DIS_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_PMA_TX_DIS_0_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TX_DIS_PMA_TX_DIS_0_MASK) /*! @} */ /*! @name SR_PMA_RX_SIG_DET - SR PMA MMD Receive Signal Detect */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_RX_DET_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_RX_DET_SHIFT (0U) /*! RX_DET - Global Receive Signal Detect */ #define ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_RX_DET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_RX_DET_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_RX_DET_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_PMA_RX_DET_0_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_PMA_RX_DET_0_SHIFT (1U) /*! PMA_RX_DET_0 - Receive Signal Detect on Lane 0 */ #define ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_PMA_RX_DET_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_PMA_RX_DET_0_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_RX_SIG_DET_PMA_RX_DET_0_MASK) /*! @} */ /*! @name SR_PMA_EXT_ABL - SR PMA or PMD Extended Ability */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBCX4_ABL_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBCX4_ABL_SHIFT (0U) /*! XGBCX4_ABL - 10GBASE-CX4 Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBCX4_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBCX4_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBCX4_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBLRM_ABL_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBLRM_ABL_SHIFT (1U) /*! XGBLRM_ABL - 10GBASE-LRM Capable * 0b1..10GBASE-R PCS configuration * 0b0..All other configurations */ #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBLRM_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBLRM_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBLRM_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBT_ABL_MASK (0x4U) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBT_ABL_SHIFT (2U) /*! XGBT_ABL - 10GBASE-T Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBT_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBT_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_XGBT_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_GBT_ABL_MASK (0x20U) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_GBT_ABL_SHIFT (5U) /*! GBT_ABL - 1000BASE-T Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_GBT_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_GBT_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_GBT_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_100BT_ABL_MASK (0x80U) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_100BT_ABL_SHIFT (7U) /*! R_100BT_ABL - 100BASE-T Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_100BT_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_100BT_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_100BT_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_10BT_ABL_MASK (0x100U) #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_10BT_ABL_SHIFT (8U) /*! R_10BT_ABL - 10BASE-T Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_10BT_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_10BT_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_EXT_ABL_R_10BT_ABL_MASK) /*! @} */ /*! @name SR_PMA_PKG1 - SR PMA MMD Package Identifier 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_PKG1_PMA_PKG_OUI_3_18_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_PKG1_PMA_PKG_OUI_3_18_SHIFT (0U) /*! PMA_PKG_OUI_3_18 - Organizationally Unique Identifier */ #define ENET_PHY_PMA_MMD_SR_PMA_PKG1_PMA_PKG_OUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_PKG1_PMA_PKG_OUI_3_18_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_PKG1_PMA_PKG_OUI_3_18_MASK) /*! @} */ /*! @name SR_PMA_PKG2 - SR PMA MMD Package Identifier 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_RN_3_0_MASK (0xFU) #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_RN_3_0_SHIFT (0U) /*! PMA_PKG_RN_3_0 - Revision Number */ #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_RN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_RN_3_0_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_RN_3_0_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_MMN_5_0_MASK (0x3F0U) #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_MMN_5_0_SHIFT (4U) /*! PMA_PKG_MMN_5_0 - Model Number */ #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_MMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_MMN_5_0_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_MMN_5_0_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_OUI_19_24_MASK (0xFC00U) #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_OUI_19_24_SHIFT (10U) /*! PMA_PKG_OUI_19_24 - Organizationally Unique Identifier */ #define ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_OUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_OUI_19_24_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_PKG2_PMA_PKG_OUI_19_24_MASK) /*! @} */ /*! @name SR_PMA_2PT5G_5G_EXT_ABL - SR PMA MMD 2.5G/5G Extended Ability */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_2PT5GT_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_2PT5GT_SHIFT (0U) /*! ABL_2PT5GT - 2.5GBASE-T Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_2PT5GT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_2PT5GT_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_2PT5GT_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_5GT_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_5GT_SHIFT (1U) /*! ABL_5GT - 5GBASE-T Capable */ #define ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_5GT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_5GT_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_2PT5G_5G_EXT_ABL_ABL_5GT_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_PMA_ABL - SR PMA MMD Time Sync Capability */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_RX_DLY_ABL_MASK (0x1U) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_RX_DLY_ABL_SHIFT (0U) /*! PMA_RX_DLY_ABL - PMA Receive Path Data Delay Information Available */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_RX_DLY_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_RX_DLY_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_RX_DLY_ABL_MASK) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_TX_DLY_ABL_MASK (0x2U) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_TX_DLY_ABL_SHIFT (1U) /*! PMA_TX_DLY_ABL - PMA Transmit Path Data Delay Information Available */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_TX_DLY_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_TX_DLY_ABL_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_PMA_ABL_PMA_TX_DLY_ABL_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_TX_MAX_DLY_LWR - SR PMA MMD Time Sync TX Max Delay Lower */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_LWR_PMA_TX_MAX_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_LWR_PMA_TX_MAX_DLY_LWR_SHIFT (0U) /*! PMA_TX_MAX_DLY_LWR - Maximum Data Delay in TX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_LWR_PMA_TX_MAX_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_LWR_PMA_TX_MAX_DLY_LWR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_LWR_PMA_TX_MAX_DLY_LWR_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_TX_MAX_DLY_UPR - SR PMA MMD Time Sync TX Max Delay Upper */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_UPR_PMA_TX_MAX_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_UPR_PMA_TX_MAX_DLY_UPR_SHIFT (0U) /*! PMA_TX_MAX_DLY_UPR - Maximum Data Delay in TX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_UPR_PMA_TX_MAX_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_UPR_PMA_TX_MAX_DLY_UPR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MAX_DLY_UPR_PMA_TX_MAX_DLY_UPR_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_TX_MIN_DLY_LWR - SR PMA MMD Time Sync TX Min Delay Lower */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_LWR_PMA_TX_MIN_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_LWR_PMA_TX_MIN_DLY_LWR_SHIFT (0U) /*! PMA_TX_MIN_DLY_LWR - Minimum Data Delay in TX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_LWR_PMA_TX_MIN_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_LWR_PMA_TX_MIN_DLY_LWR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_LWR_PMA_TX_MIN_DLY_LWR_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_TX_MIN_DLY_UPR - SR PMA MMD Time Sync TX Min Delay Upper */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_UPR_PMA_TX_MIN_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_UPR_PMA_TX_MIN_DLY_UPR_SHIFT (0U) /*! PMA_TX_MIN_DLY_UPR - Minimum Data Delay in TX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_UPR_PMA_TX_MIN_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_UPR_PMA_TX_MIN_DLY_UPR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_TX_MIN_DLY_UPR_PMA_TX_MIN_DLY_UPR_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_RX_MAX_DLY_LWR - SR PMA MMD Time Sync RX Max Delay Lower */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_LWR_PMA_RX_MAX_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_LWR_PMA_RX_MAX_DLY_LWR_SHIFT (0U) /*! PMA_RX_MAX_DLY_LWR - Maximum Data Delay in RX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_LWR_PMA_RX_MAX_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_LWR_PMA_RX_MAX_DLY_LWR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_LWR_PMA_RX_MAX_DLY_LWR_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_RX_MAX_DLY_UPR - SR PMA MMD Time Sync RX Max Delay Upper */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_UPR_PMA_RX_MAX_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_UPR_PMA_RX_MAX_DLY_UPR_SHIFT (0U) /*! PMA_RX_MAX_DLY_UPR - Maximum Data Delay in RX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_UPR_PMA_RX_MAX_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_UPR_PMA_RX_MAX_DLY_UPR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MAX_DLY_UPR_PMA_RX_MAX_DLY_UPR_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_RX_MIN_DLY_LWR - SR PMA MMD Time Sync RX Min Delay Lower */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_LWR_PMA_RX_MIN_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_LWR_PMA_RX_MIN_DLY_LWR_SHIFT (0U) /*! PMA_RX_MIN_DLY_LWR - Minimum Data Delay in RX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_LWR_PMA_RX_MIN_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_LWR_PMA_RX_MIN_DLY_LWR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_LWR_PMA_RX_MIN_DLY_LWR_MASK) /*! @} */ /*! @name SR_PMA_TIME_SYNC_RX_MIN_DLY_UPR - SR PMA MMD Time Sync RX Min Delay Upper */ /*! @{ */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_UPR_PMA_RX_MIN_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_UPR_PMA_RX_MIN_DLY_UPR_SHIFT (0U) /*! PMA_RX_MIN_DLY_UPR - Minimum Data Delay in RX Path */ #define ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_UPR_PMA_RX_MIN_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_UPR_PMA_RX_MIN_DLY_UPR_SHIFT)) & ENET_PHY_PMA_MMD_SR_PMA_TIME_SYNC_RX_MIN_DLY_UPR_PMA_RX_MIN_DLY_UPR_MASK) /*! @} */ /*! @name VR_PMA_DIG_CTRL1 - VR PMA MMD Digital Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_BYP_PWRUP_MASK (0x2U) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_BYP_PWRUP_SHIFT (1U) /*! BYP_PWRUP - Bypass Power-Up Sequence * 0b1..DWC_XPCS bypasses the normal flow of the power-up sequence and reaches the Power_Good state to enable transmission or reception * 0b0..DWC_XPCS waits for the MPLL, TX, or RX PLL status from the Synopsys PHY before resuming the normal transmission and reception */ #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_BYP_PWRUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_BYP_PWRUP_SHIFT)) & ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_BYP_PWRUP_MASK) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_DTXLANED_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_DTXLANED_0_SHIFT (4U) /*! DTXLANED_0 - TX Disable on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_DTXLANED_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_DTXLANED_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_DTXLANED_0_MASK) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_PWRSV_MASK (0x800U) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_PWRSV_SHIFT (11U) /*! PWRSV - Power Save * 0b0..Normal operation * 0b1..DWC_XPCS and the PHY enter the power-save mode */ #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_PWRSV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_PWRSV_SHIFT)) & ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_PWRSV_MASK) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_VR_RST_MASK (0x8000U) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_VR_RST_SHIFT (15U) /*! VR_RST - Vendor-specific Soft Reset (RW, SC Type) * 0b1..DWC_XPCS initiates the reset for all the internal blocks except the Management Interface block and the CSR block */ #define ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_VR_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_VR_RST_SHIFT)) & ENET_PHY_PMA_MMD_VR_PMA_DIG_CTRL1_VR_RST_MASK) /*! @} */ /*! @name VR_PMA_DIG_STS - VR PMA MMD Digital Status */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_PMA_DIG_STS_PSEQ_STATE_MASK (0x1CU) #define ENET_PHY_PMA_MMD_VR_PMA_DIG_STS_PSEQ_STATE_SHIFT (2U) /*! PSEQ_STATE - Power Up Sequence State * 0b000..Wait for MPLL ON (for Synopsys multi-protocol 6G PHY), Wait for ACK High 0 (for Synopsys multi-protocol 12G/16G/25G/32G PHY) * 0b001..Wait for TX up (6G PHY), Wait for ACK Low 0 (12G/16G/25G/32G PHY) * 0b010..Wait for RX up (6G PHY), Wait for ACK High 1 (12G/16G/25G/32G PHY) * 0b011..TX/RX Stable (Power_Good state) (6G PHY), Wait for ACK Low 1 (12G/16G/25G/32G PHY) * 0b100..TX/RX Stable (Power_Good state) * 0b101..Wait for RX down (MPLL still ON) (6G PHY), Power Save state (12G/16G/25G/32G PHY) * 0b110..MPLL OFF (6G PHY), Power Down state (12G/16G/25G/32G PHY) * 0b111..Other intermediate states (valid only for 32G PHY configurations) */ #define ENET_PHY_PMA_MMD_VR_PMA_DIG_STS_PSEQ_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_PMA_DIG_STS_PSEQ_STATE_SHIFT)) & ENET_PHY_PMA_MMD_VR_PMA_DIG_STS_PSEQ_STATE_MASK) /*! @} */ /*! @name VR_XS_PMA_RX_LSTS - VR XS or PMA PHY RX Lane Status */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_SIG_DET_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_SIG_DET_0_SHIFT (4U) /*! SIG_DET_0 - RX Signal Detect for Lane 0 * 0b1..Lane 0 signal is detected */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_SIG_DET_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_SIG_DET_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_SIG_DET_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_PLL_STATE_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_PLL_STATE_0_SHIFT (8U) /*! RX_PLL_STATE_0 - RX DPLL State for Lane 0 * 0b1..Lane 0 RX is successful */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_PLL_STATE_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_PLL_STATE_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_PLL_STATE_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0_SHIFT (12U) /*! RX_VALID_0 - DPLL Lock Status for Lane 0 * 0b1..Lane 0 DPLL bit is locked */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_3_1_MASK (0xE000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_3_1_SHIFT (13U) /*! RX_VALID_3_1 - DPLL Lock Status for Lanes [3:1] * 0bxx1..Lane 1 DPLL bit is locked * 0bx1x..Lane 2 DPLL bit is locked * 0b1xx..Lane 3 DPLL bit is locked */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_3_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_3_1_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_3_1_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX General 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TXBCN_EN_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TXBCN_EN_0_SHIFT (0U) /*! TXBCN_EN_0 - TX Beaconing Enable on lane 0 of PHY * 0b1..PHY enables transmitter beaconing (LFPS) */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TXBCN_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TXBCN_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TXBCN_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_INV_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_INV_0_SHIFT (4U) /*! TX_INV_0 - TX Invert on Lane 0 of PHY * 0b1..The data on PHY TX serial lines are logically inverted */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_INV_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_INV_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_INV_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_SHIFT (8U) /*! TX_RST_0 - TX Reset on Lane 0 of PHY * 0b1..PHY transmitter is reset, including common-mode adjustment and receiver detection state machines */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_SHIFT (12U) /*! TX_DT_EN_0 - TX Data Enable on Lane 0 of PHY * 0b1..Transmit Output Driver in the PHY is enabled */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX General 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_DET_RX_REQ_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_DET_RX_REQ_0_SHIFT (0U) /*! DET_RX_REQ_0 - Transmitter RX-Detection Request on Lane 0 of PHY * 0b1..A receiver detection request is made towards the PHY on lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_DET_RX_REQ_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_DET_RX_REQ_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_DET_RX_REQ_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_SHIFT (4U) /*! VBOOST_EN_0 - TX Voltage Boost Enable on Lane 0 of PHY * 0b1..The current mode TX Swing boost in the PHY is enabled */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL_MASK (0x700U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL_SHIFT (8U) /*! VBOOST_LVL - TX Voltage Boost Maximum Level */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_SHIFT (12U) /*! TX_CLK_RDY_0 - Transmitter Input Clock Ready on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_TX_GENCTRL2 - VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY TX General 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_SHIFT (0U) /*! TX_REQ_0 - Transmitter Operation Request on Lane 0 of E12G/E16G PHY (RW, SC Type) */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_LPD_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_LPD_0_SHIFT (4U) /*! TX_LPD_0 - Transmitter Lane Power Down on Lane 0 of PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_LPD_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_LPD_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_LPD_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK (0x300U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_SHIFT (8U) /*! TX0_WIDTH - TX Datapath Width on Lane 0 of the PHY * 0b00..8-bit * 0b01..10-bit * 0b10..16-bit * 0b11..20-bit */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Boost Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST_MASK (0xFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST_SHIFT (0U) /*! TX0_IBOOST - TX Current Boost Level on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Rate Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK (0x7U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_SHIFT (0U) /*! TX0_RATE - TX Date Rate on Lane 0 of the PHY * 0b000..Baud * 0b001..Baud/2 * 0b010..Baud/4 * 0b011..Baud/8 * 0b111..Baud/10 * 0b100-0b110..Not supported */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK) /*! @} */ /*! @name MP_12G_16G_25G_TX_POWER_STATE_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Power State */ /*! @{ */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK (0x3U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_SHIFT (0U) /*! TX0_PSTATE - TX Power State Control for Lane 0 of PHY * 0b00..P0 * 0b01..P0s * 0b10..P1 * 0b11..P2 */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0_SHIFT (8U) /*! TX_DISABLE_0 - Transmitter Disable on Lane 0 */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Equalization Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE_MASK (0x3FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE_SHIFT (0U) /*! TX_EQ_PRE - TX Pre-Emphasis Level Adjustment Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN_MASK (0x3F00U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN_SHIFT (8U) /*! TX_EQ_MAIN - Control for Setting TX Driver Output Amplitude */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Equalization Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST_MASK (0x3FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST_SHIFT (0U) /*! TX_EQ_POST - TX Post-Emphasis Level Adjustment Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_TX_GENCTRL3 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY TX General Control 3 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL3_TXUP_TERM_OFFSET_MASK (0x1FFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL3_TXUP_TERM_OFFSET_SHIFT (0U) /*! TXUP_TERM_OFFSET - Offset for TX Up Termination */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL3_TXUP_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL3_TXUP_TERM_OFFSET_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL3_TXUP_TERM_OFFSET_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_TX_GENCTRL4 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY TX General Control 4 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL4_TXDN_TERM_OFFSET_MASK (0x1FFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL4_TXDN_TERM_OFFSET_SHIFT (0U) /*! TXDN_TERM_OFFSET - Offset for TX Down Termination */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL4_TXDN_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL4_TXDN_TERM_OFFSET_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_GENCTRL4_TXDN_TERM_OFFSET_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY TX Miscellaneous Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC_SHIFT (0U) /*! TX0_MISC - TX Miscellaneous Control for Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_TX_STS - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY TX Status */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_TX_ACK_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_TX_ACK_0_SHIFT (0U) /*! TX_ACK_0 - TX Acknowledge on Lane 0 of PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_TX_ACK_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_TX_ACK_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_TX_ACK_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_DETRX_RSLT_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_DETRX_RSLT_0_SHIFT (4U) /*! DETRX_RSLT_0 - Receiver Detection Result on Lane 0 of PHY * 0b0..Receiver not detected * 0b1..Receiver detected */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_DETRX_RSLT_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_DETRX_RSLT_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_STS_DETRX_RSLT_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX General Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_TERM_EN_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_TERM_EN_0_SHIFT (0U) /*! RX_TERM_EN_0 - RX Termination Enable on Lane 0 of PHY * 0b0..The termination is in high impedance * 0b1..PHY RX is terminated with a nominal 50 ohm resistance */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_TERM_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_TERM_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_TERM_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_0_SHIFT (4U) /*! RX_ALIGN_EN_0 - RX Data Alignment Enable on Lane 0 of Multi-Protocol 12G PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_3_1_MASK (0xE0U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_3_1_SHIFT (5U) /*! RX_ALIGN_EN_3_1 - RX Data Alignment Enable on Lanes [3:1] of Multi-Protocol 12G PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_3_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_3_1_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_ALIGN_EN_3_1_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_SHIFT (8U) /*! RX_DT_EN_0 - RX Data Enable on Lane 0 of PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_0_SHIFT (12U) /*! RX_CLKSFT_0 - RX Clock Shift on Lane 0 of Multi-Protocol 12G PHY * 0b1..1-bit shift of receive data happens relate to receive clock */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_3_1_MASK (0xE000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_3_1_SHIFT (13U) /*! RX_CLKSFT_3_1 - RX Clock Shift on Lanes [3:1] of Multi-Protocol 12G PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_3_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_3_1_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_CLKSFT_3_1_MASK) /*! @} */ /*! @name MP_12G_16G_25G_RX_GENCTRL1 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX General Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_INV_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_INV_0_SHIFT (0U) /*! RX_INV_0 - RX Data Invert on Lane 0 of PHY * 0b1..The data on PHY RX serial lines are logically inverted */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_INV_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_INV_0_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_INV_0_MASK) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_SHIFT (4U) /*! RX_RST_0 - RX Reset on Lane 0 of PHY * 0b1..RX data path, all the receiver settings and state machines of the PHY are reset */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0_SHIFT (8U) /*! RX_TERM_ACDC_0 - RX Termination Control on Lane 0 of PHY * 0b0..DC Termination (Floating RX) * 0b1..AC Termination (Grounded RX) */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0_MASK) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0_SHIFT (12U) /*! RX_DIV16P5_CLK_EN_0 - Receiver Divide by 16 * 0b1..Enables the divide by 16.5 RX VCO recovered clock of the PHY */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_RX_GENCTRL2 - VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY RX General Control 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_SHIFT (0U) /*! RX_REQ_0 - Receiver Operation Request on Lane 0 of PHY (RW, SC Type) * 0b1..A new receiver setting request is made towards the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_LPD_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_LPD_0_SHIFT (4U) /*! RX_LPD_0 - Receiver Lane Power Down on Lane 0 of PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_LPD_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_LPD_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_LPD_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK (0x300U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_SHIFT (8U) /*! RX0_WIDTH - RX Datapath Width on Lane 0 of the PHY * 0b00..8-bit * 0b01..10-bit * 0b10..16-bit * 0b11..20-bit */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_RX_GENCTRL3 - VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY RX General Control 3 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0_MASK (0x7U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0_SHIFT (0U) /*! LOS_TRSHLD_0 - Loss of Signal Threshold on Lane 0 of PHY * 0b000..Reserved * 0b001..90 mVpp * 0b010..120 mVpp * 0b011..150 mVpp * 0b100..180 mVpp * 0b101..210 mVpp * 0b110..240 mVpp * 0b111..270 mVpp */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0_SHIFT (12U) /*! LOS_LFPS_EN_0 - RX LOS LFPS Enable on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Rate Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK (0x3U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_SHIFT (0U) /*! RX0_RATE - RX Date Rate on Lane 0 of the PHY * 0b00..Baud * 0b01..Baud/2 * 0b10..Baud/4 * 0b11..Baud/8 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK) /*! @} */ /*! @name MP_12G_16G_25G_RX_POWER_STATE_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Power State */ /*! @{ */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK (0x3U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_SHIFT (0U) /*! RX0_PSTATE - RX Power State Control for Lane 0 of PHY * 0b00..P0 * 0b01..P0s * 0b10..P1 * 0b11..P2 */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_SHIFT (8U) /*! RX_DISABLE_0 - Receiver Disable on Lane 0 */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_EEE_OVR_RIDE_MASK (0x1000U) #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_EEE_OVR_RIDE_SHIFT (12U) /*! EEE_OVR_RIDE - RX Power State Override Control During EEE * 0b1..Override the behavior of DWC_XPCS */ #define ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_EEE_OVR_RIDE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_EEE_OVR_RIDE_SHIFT)) & ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_EEE_OVR_RIDE_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX CDR Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0_SHIFT (4U) /*! CDR_SSC_EN_0 - RX CDR SSC Mode Enable on Lane 0 of the PHY * 0b1..Receive data has a spread spectrum clock * 0b0..Receive data does not have SSC */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Attenuation Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK (0x7U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_SHIFT (0U) /*! RX0_EQ_ATT_LVL - RX Equalization Attenuation Level for Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX Equalization Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK (0x1FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_SHIFT (0U) /*! CTLE_BOOST_0 - RX Equalization CTLE Boost Value on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0_MASK (0x60U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0_SHIFT (5U) /*! CTLE_POLE_0 - RX Equalization CTLE Pole Value on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0_MASK (0x700U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0_SHIFT (8U) /*! VGA2_GAIN_0 - RX Equalization VGA2 Gain on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0_MASK (0x7000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0_SHIFT (12U) /*! VGA1_GAIN_0 - RX Equalization VGA1 Gain on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Equalization Control 4 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0_SHIFT (0U) /*! CONT_ADAPT_0 - Receiver Adaptation Continuous Operation on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_OFF_CAN_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_OFF_CAN_0_SHIFT (4U) /*! CONT_OFF_CAN_0 - Receiver Offset Cancellation Continuous Operation on Lane 0 * 0b0..Offset cancellation runs when receiver exits P2 power state * 0b1..Continuous receiver offset cancellation enabled */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_OFF_CAN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_OFF_CAN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_OFF_CAN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_SHIFT (12U) /*! RX_AD_REQ - Receive Adaptation Request */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX Equalization Control 5 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0_SHIFT (0U) /*! RX_ADPT_SEL_0 - Select Storage Bank for RX Adaptation on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK (0x30U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_SHIFT (4U) /*! RX0_ADPT_MODE - RX Adaptation for Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_PROG_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_PROG_0_SHIFT (12U) /*! RX_ADPT_PROG_0 - Receiver Adaptation in Progress - Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_PROG_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_PROG_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_PROG_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_AD_PROG_3_1_MASK (0xE000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_AD_PROG_3_1_SHIFT (13U) /*! RX_AD_PROG_3_1 - Receiver Adaptation in Progress - Lanes 3 to 1 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_AD_PROG_3_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_AD_PROG_3_1_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_AD_PROG_3_1_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY DFE Tap Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0_SHIFT (0U) /*! DFE_TAP1_0 - RX Equalization DFE Tap1 Value on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_RX_STS - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY RX Status */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_RX_ACK_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_RX_ACK_0_SHIFT (0U) /*! RX_ACK_0 - RX Acknowledge on Lane 0 of PHY * 0b1..The requested receiver setting is complete */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_RX_ACK_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_RX_ACK_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_RX_ACK_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_0_SHIFT (4U) /*! LF_SD_0 - Low-Frequency Signal Detect on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_3_1_MASK (0xE0U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_3_1_SHIFT (5U) /*! LF_SD_3_1 - Low-Frequency Signal Detect on Lanes 1-3 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_3_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_3_1_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_LF_SD_3_1_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_0_SHIFT (8U) /*! HF_SD_0 - High-Frequency Signal Detect on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_3_1_MASK (0xE00U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_3_1_SHIFT (9U) /*! HF_SD_3_1 - High-Frequency Signal Detect on Lanes 1-3 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_3_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_3_1_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_STS_HF_SD_3_1_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_RX_PPM_STS0 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX PPM Status 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_MASK (0x3FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_SHIFT (0U) /*! RX0_PPM_DRIFT - RX CDR PPM Drift on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_VLD_MASK (0x80U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_VLD_SHIFT (7U) /*! RX0_PPM_DRIFT_VLD - RX CDR PPM Drift Valid on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_VLD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_VLD_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_STS0_RX0_PPM_DRIFT_VLD_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_RX_CDR_CTRL1 - VR XS or PMA Synopsys Multi-Protocol 16G PHY RX CDR Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_SHIFT (0U) /*! VCO_TEMP_COMP_EN_0 - RX_CDR VCO Temperature Compensation Enable Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_SHIFT (4U) /*! VCO_STEP_CTRL_0 - RX_CDR VCO Step Control Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK (0x300U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_SHIFT (8U) /*! VCO_FRQBAND_0 - RX CDR VCO Frequency Band Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX PPM Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK (0x1FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_SHIFT (0U) /*! RX0_CDR_PPM_MAX - Maximum Allowed PPM on the RX0 CDR Clock */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_RX_GENCTRL4 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX General Control 4 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_TERM_OFFSET_MASK (0x1FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_TERM_OFFSET_SHIFT (0U) /*! RX_TERM_OFFSET - Offset for RX Termination */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_TERM_OFFSET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_TERM_OFFSET_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_TERM_OFFSET_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_SHIFT (8U) /*! RX_DFE_BYP_0 - RX DFE Bypass Enable on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_0_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_0_SHIFT (12U) /*! RX_125MHZ_CLK_EN_0 - RX 125 MHz Clock Generation Enable on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_3_1_MASK (0xE000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_3_1_SHIFT (13U) /*! RX_125MHZ_CLK_EN_3_1 - RX 125MHz clock generation Enable on Lane 3 to 1 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_3_1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_3_1_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_125MHZ_CLK_EN_3_1_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX Miscellaneous Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_SHIFT (0U) /*! RX0_MISC - RX Miscellaneous Control for Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY RX IQ Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_MARGIN_IQ_MASK (0x7FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_MARGIN_IQ_SHIFT (0U) /*! RX0_MARGIN_IQ - Value of RX IQ Margining on Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_MARGIN_IQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_MARGIN_IQ_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_MARGIN_IQ_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK (0xF00U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_SHIFT (8U) /*! RX0_DELTA_IQ - RX IQ Offset Value for Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY MPLL Common Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_SHIFT (0U) /*! MPLL_EN_0 - TX MPLL Enable - Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0_SHIFT (4U) /*! MPLLB_SEL_0 - TX MPLLB Select - Lane 0 * 0b1..Multi-protocol 12G/16G/25G PHYs select MPLLB to generate TX analog clocks on lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLA Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_SHIFT (0U) /*! MPLLA_MULTIPLIER - MPLLA frequency Multiplier Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_SSC_CLK_SEL_MASK (0x700U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_SSC_CLK_SEL_SHIFT (8U) /*! MPLLA_SSC_CLK_SEL - MPLLA Spread-Spectrum Clock Select */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_SSC_CLK_SEL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_SSC_CLK_SEL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_CAL_DISABLE_MASK (0x8000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_CAL_DISABLE_SHIFT (15U) /*! MPLLA_CAL_DISABLE - MPLLA Calibration Disable * 0b1..Disable calibration of MPLLA by PHY firmware */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_CAL_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_CAL_DISABLE_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_CAL_DISABLE_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLA_CTRL1 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN_SHIFT (0U) /*! MPLLA_SSC_EN - MPLLA SSC Enable * 0b1..Enable spread-spectrum generation on mplla_div_clk output */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL_SHIFT (4U) /*! MPLLA_SSC_CLK_SEL - MPLLA SSC Clock Select */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK (0xFFE0U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL_SHIFT (5U) /*! MPLLA_FRACN_CTRL - MPLLA Fractional Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2 - VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLA Control 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK (0x7FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT_SHIFT (0U) /*! MPLLA_DIV_MULT - MPLLA Output Frequency Multiplier Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN_MASK (0x80U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN_SHIFT (7U) /*! MPLLA_DIV_CLK_EN - Enable mplla_div_clk from PHY * 0b1..The frequency of mplla_div_clk from PHY is the MPLLA frequency divided by 'mplla_div_multiplier' */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_SHIFT (8U) /*! MPLLA_DIV8_CLK_EN - MPLLA Divide by 8 Enable * 0b1..The frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 8 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK (0x200U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_SHIFT (9U) /*! MPLLA_DIV10_CLK_EN - MPLLA Divide by 10 Enable * 0b1..The frequency of the mplla_word_clk output clock from PHY is MPLLA frequency divided by 10 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK (0x400U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_SHIFT (10U) /*! MPLLA_DIV16P5_CLK_EN - MPLLA Divide by 16.5 Enable * 0b1..Enable output clocks derived from MPLLA based on 16.5, 33 and 66 division ratios */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK (0x1800U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_SHIFT (11U) /*! MPLLA_TX_CLK_DIV - MPLLA TX Clock Divider */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_RECAL_BANK_SEL_MASK (0x6000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_RECAL_BANK_SEL_SHIFT (13U) /*! MPLLA_RECAL_BANK_SEL - MPLLA Re-calibration Bank Select */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_RECAL_BANK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_RECAL_BANK_SEL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_RECAL_BANK_SEL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_WRD_DIV2_EN_MASK (0x8000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_WRD_DIV2_EN_SHIFT (15U) /*! MPLLA_WRD_DIV2_EN - MPLLA Word Clock Divide by 2 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_WRD_DIV2_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_WRD_DIV2_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_WRD_DIV2_EN_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLB Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_MULTIPLIER_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_MULTIPLIER_SHIFT (0U) /*! MPLLB_MULTIPLIER - MPLLB Frequency Multiplier Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_MULTIPLIER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_MULTIPLIER_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_MULTIPLIER_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_SSC_CLK_SEL_MASK (0x700U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_SSC_CLK_SEL_SHIFT (8U) /*! MPLLB_SSC_CLK_SEL - MPLLB Spread-Spectrum Clock Select */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_SSC_CLK_SEL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_SSC_CLK_SEL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_CAL_DISABLE_MASK (0x8000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_CAL_DISABLE_SHIFT (15U) /*! MPLLB_CAL_DISABLE - MPLLB Calibration Disable * 0b1..Disable calibration of MPLLB by PHY firmware */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_CAL_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_CAL_DISABLE_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL0_MPLLB_CAL_DISABLE_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLB_CTRL1 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_EN_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_EN_SHIFT (0U) /*! MPLLB_SSC_EN - MPLLB Spread Spectrum Enable * 0b1..Enable spread-spectrum generation on mpllb_div_clk output */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_CLK_SEL_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_CLK_SEL_SHIFT (4U) /*! MPLLB_SSC_CLK_SEL - MPLLB Spread Spectrum Clock Select */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_CLK_SEL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_SSC_CLK_SEL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_FRACN_CTRL_MASK (0xFFE0U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_FRACN_CTRL_SHIFT (5U) /*! MPLLB_FRACN_CTRL - MPLLB Fractional Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_FRACN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_FRACN_CTRL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL1_MPLLB_FRACN_CTRL_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2 - VR XS or PMA Synopsys Multi-Protocol 12G/16G PHY MPLLB Control 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_MULT_MASK (0x7FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_MULT_SHIFT (0U) /*! MPLLB_DIV_MULT - MPLLB Output Frequency Multiplier Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_MULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_MULT_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_MULT_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_CLK_EN_MASK (0x80U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_CLK_EN_SHIFT (7U) /*! MPLLB_DIV_CLK_EN - Enable mpllb_div_clk from PHY * 0b1..The frequency of mpllb_div_clk output from PHY is MPLLB frequency divided by 'mpllb_div_multiplier' */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV8_CLK_EN_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV8_CLK_EN_SHIFT (8U) /*! MPLLB_DIV8_CLK_EN - MPLLB Divide by 8 Enable * 0b1..The frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 8 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV8_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV8_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV8_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV10_CLK_EN_MASK (0x200U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV10_CLK_EN_SHIFT (9U) /*! MPLLB_DIV10_CLK_EN - MPLLB Divide by 10 Enable * 0b1..The frequency of the mpllb_word_clk output clock from PHY is MPLLB frequency divided by 10 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV10_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV10_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_DIV10_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_TX_CLK_DIV_MASK (0x1800U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_TX_CLK_DIV_SHIFT (11U) /*! MPLLB_TX_CLK_DIV - MPLLB TX Clock Divider */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_TX_CLK_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_TX_CLK_DIV_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_TX_CLK_DIV_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_RECAL_BANK_SEL_MASK (0x6000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_RECAL_BANK_SEL_SHIFT (13U) /*! MPLLB_RECAL_BANK_SEL - MPLLB Re-Calibration Bank Select */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_RECAL_BANK_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_RECAL_BANK_SEL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLB_CTRL2_MPLLB_RECAL_BANK_SEL_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLA_CTRL3 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 3 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_SHIFT (0U) /*! MPLLA_BANDWIDTH - MPLLA Bandwidth Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLB_CTRL3 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 3 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL3_MPLLB_BANDWIDTH_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL3_MPLLB_BANDWIDTH_SHIFT (0U) /*! MPLLB_BANDWIDTH - MPLLB Bandwidth Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL3_MPLLB_BANDWIDTH(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL3_MPLLB_BANDWIDTH_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL3_MPLLB_BANDWIDTH_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLA_CTRL4 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 4 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK (0xFFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_SHIFT (0U) /*! MPLLA_SSC_FRQ_CNT_INT - MPLLA SSC Frequency Counter Initialization */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLA_CTRL5 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLA Control 5 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_SHIFT (0U) /*! MPLLA_SSC_FRQ_CNT_PK - MPLLA SSC Frequency Counter Peak */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN_SHIFT (8U) /*! MPLLA_SSC_SPD_EN - MPLLA SSC Up Spread Enable */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLB_CTRL4 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 4 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL4_MPLLB_SSC_FRQ_CNT_INT_MASK (0xFFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL4_MPLLB_SSC_FRQ_CNT_INT_SHIFT (0U) /*! MPLLB_SSC_FRQ_CNT_INT - MPLLB SSC Frequency Counter Initialization */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL4_MPLLB_SSC_FRQ_CNT_INT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL4_MPLLB_SSC_FRQ_CNT_INT_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL4_MPLLB_SSC_FRQ_CNT_INT_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_MPLLB_CTRL5 - VR XS or PMA Synopsys Multi-Protocol 16G PHY MPLLB Control 5 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_FRQ_CNT_PK_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_FRQ_CNT_PK_SHIFT (0U) /*! MPLLB_SSC_FRQ_CNT_PK - MPLLB SSC Frequency Counter Peak */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_FRQ_CNT_PK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_FRQ_CNT_PK_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_FRQ_CNT_PK_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_SPD_EN_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_SPD_EN_SHIFT (8U) /*! MPLLB_SSC_SPD_EN - MPLLB SSC Up Spread Enable */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_SPD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_SPD_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLB_CTRL5_MPLLB_SSC_SPD_EN_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Miscellaneous Control 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_TX2RX_LB_EN_0_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_TX2RX_LB_EN_0_SHIFT (0U) /*! TX2RX_LB_EN_0 - Enable Analog TX-to-RX Serial Loopback on Lane 0 * 0b1..Enable serial loopback in the PHY from TX pre-driver to RX analog front-end */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_TX2RX_LB_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_TX2RX_LB_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_TX2RX_LB_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX2TX_LB_EN_0_MASK (0x10U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX2TX_LB_EN_0_SHIFT (4U) /*! RX2TX_LB_EN_0 - Enable Parallel RX-to-TX Loopback on Lane 0 * 0b1..Recovered parallel data from PHY receiver is looped back to the transmit serializer */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX2TX_LB_EN_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX2TX_LB_EN_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX2TX_LB_EN_0_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL_MASK (0x1F00U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL_SHIFT (8U) /*! RX_VREF_CTRL - RX Biasing Current Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RTUNE_REQ_MASK (0x2000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RTUNE_REQ_SHIFT (13U) /*! RTUNE_REQ - Resistor Tuning Request * 0b1..Trigger a resistor tune request to the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RTUNE_REQ(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RTUNE_REQ_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RTUNE_REQ_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_CR_PARA_SEL_MASK (0x4000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_CR_PARA_SEL_SHIFT (14U) /*! CR_PARA_SEL - Select CR Para/APB3 Port * 0b0..JTAG * 0b1..CR parallel port */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_CR_PARA_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_CR_PARA_SEL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_CR_PARA_SEL_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_PLL_CTRL_MASK (0x8000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_PLL_CTRL_SHIFT (15U) /*! PLL_CTRL - PLL Re-Initialization Control */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_PLL_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_PLL_CTRL_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_PLL_CTRL_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Reference Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_EN_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_EN_SHIFT (0U) /*! REF_CLK_EN - Reference Clock Enable * 0b1..Enable reference clock to the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_USE_PAD_MASK (0x2U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_USE_PAD_SHIFT (1U) /*! REF_USE_PAD - Use Pad Clk as Reference Clock * 0b1..PHY selects the clock connected to ref_pad_clk_p/m as its reference clock * 0b0..PHY selects the clock connected to ref_alt_clk_p/m */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_USE_PAD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_USE_PAD_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_USE_PAD_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2_MASK (0x4U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2_SHIFT (2U) /*! REF_CLK_DIV2 - Reference Clock Divide by 2 * 0b1..Reference clock provided to PHY gets divided by 2 internally in the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE_MASK (0x38U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE_SHIFT (3U) /*! REF_RANGE - Input Reference Clock Range * 0b000..20 - 26 MHz * 0b001..26.1 - 52 MHz * 0b010..52.1 - 78 MHz * 0b011..78.1 - 104 MHz * 0b100..104.1 - 130 MHz * 0b101..130.1 - 156 MHz * 0b110..156.1 - 182 MHz * 0b111..182.1 - 200 MHz */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2_MASK (0x40U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2_SHIFT (6U) /*! REF_MPLLA_DIV2 - MPLLA Reference Clock Divider Control * 0b1..The reference clock used for MPLLA calibration and locking can be divided by 2 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV2_MASK (0x80U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV2_SHIFT (7U) /*! REF_MPLLB_DIV2 - MPLLB Reference Clock Divider Control * 0b1..The reference clock used for MPLLB calibration and locking can be divided by 2 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV2_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV2_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RPT_CLK_EN_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RPT_CLK_EN_SHIFT (8U) /*! REF_RPT_CLK_EN - Repeat Reference Clock Enable * 0b1..'ref_repeat_clk_{p,m}' clock from PHY is enabled */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RPT_CLK_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RPT_CLK_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RPT_CLK_EN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV_MASK (0x1C00U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV_SHIFT (10U) /*! REF_MPLLA_DIV - MPLLA Reference Clock Division */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV_MASK (0xE000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV_SHIFT (13U) /*! REF_MPLLB_DIV - MPLLB Reference Clock Division */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLB_DIV_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY VCO Calibration Load 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK (0x1FFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_SHIFT (0U) /*! VCO_LD_VAL_0 - RX VCO Calibration Load Value on Lane 0 of the PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY VCO Calibration Reference 0 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK (0x7FU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_SHIFT (0U) /*! VCO_REF_LD_0 - RX VCO Calibration Reference Load Value - Lane 0 */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_MISC_STS - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Miscellaneous Status */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_FOM_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_FOM_SHIFT (0U) /*! FOM - Figure of Merit (FOM) */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_FOM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_FOM_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_FOM_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RTUNE_ACK_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RTUNE_ACK_SHIFT (8U) /*! RTUNE_ACK - Acknowledgment for Resistor Tune Request */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RTUNE_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RTUNE_ACK_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RTUNE_ACK_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLA_STS_MASK (0x200U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLA_STS_SHIFT (9U) /*! MPLLA_STS - Status of MPLLA from PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLA_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLA_STS_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLA_STS_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLB_STS_MASK (0x400U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLB_STS_SHIFT (10U) /*! MPLLB_STS - Status of MPLLB from PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLB_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLB_STS_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_MPLLB_STS_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_REF_CLKDET_RESULT_MASK (0x800U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_REF_CLKDET_RESULT_SHIFT (11U) /*! REF_CLKDET_RESULT - Reference Clock Detection Result */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_REF_CLKDET_RESULT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_REF_CLKDET_RESULT_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_REF_CLKDET_RESULT_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK_MASK (0x1000U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK_SHIFT (12U) /*! RX_ADPT_ACK - Receive Adaptation Acknowledgment from PHY */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL1 - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY Miscellaneous Control 1 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL1_RX_LNK_UP_TIME_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL1_RX_LNK_UP_TIME_SHIFT (0U) /*! RX_LNK_UP_TIME - Wait Time Before PLL Re-Initialization */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL1_RX_LNK_UP_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL1_RX_LNK_UP_TIME_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL1_RX_LNK_UP_TIME_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_12G_16G_25G_SRAM - VR XS or PMA Synopsys Multi-Protocol 12G/16G/25G PHY SRAM */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_SHIFT (0U) /*! INIT_DN - SRAM Initialization Done */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN_MASK (0x2U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN_SHIFT (1U) /*! EXT_LD_DN - SRAM External Loading Done */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_BTLD_BYP_MASK (0x4U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_BTLD_BYP_SHIFT (2U) /*! BTLD_BYP - SRAM Boatload Bypass */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_BTLD_BYP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_BTLD_BYP_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_BTLD_BYP_MASK) /*! @} */ /*! @name VR_XS_PMA_MP_16G_25G_MISC_CTRL2 - VR XS or PMA Synopsys Multi-Protocol 16G/25G PHY Miscellaneous Control 2 */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC_MASK (0xFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC_SHIFT (0U) /*! SUP_MISC - Support Miscellaneous Controls */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_REF_CLK_DET_EN_MASK (0x100U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_REF_CLK_DET_EN_SHIFT (8U) /*! REF_CLK_DET_EN - Reference Clock Detect Enable */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_REF_CLK_DET_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_REF_CLK_DET_EN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_REF_CLK_DET_EN_MASK) /*! @} */ /*! @name VR_XS_PMA_SNPS_CR_CTRL - VR XS or PMA Synopsys PHY CR Control */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_START_BUSY_MASK (0x1U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_START_BUSY_SHIFT (0U) /*! START_BUSY - Start CR Port Access or Busy Indicator (WS, SC Type) * 0b0..CR port not busy * 0b1..CR port busy */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_START_BUSY(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_START_BUSY_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_START_BUSY_MASK) #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_WR_RDN_MASK (0x2U) #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_WR_RDN_SHIFT (1U) /*! WR_RDN - Write or Read Indicator * 0b0..Read * 0b1..Write */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_WR_RDN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_WR_RDN_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_CTRL_WR_RDN_MASK) /*! @} */ /*! @name VR_XS_PMA_SNPS_CR_ADDR - VR XS or PMA Synopsys PHY CR Address */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_ADDR_ADDRESS_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_ADDR_ADDRESS_SHIFT (0U) /*! ADDRESS - CR Port Address */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_ADDR_ADDRESS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_ADDR_ADDRESS_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_ADDR_ADDRESS_MASK) /*! @} */ /*! @name VR_XS_PMA_SNPS_CR_DATA - VR XS or PMA Synopsys CR Data */ /*! @{ */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_DATA_DATA_MASK (0xFFFFU) #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_DATA_DATA_SHIFT (0U) /*! DATA - CR Port Data */ #define ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_DATA_DATA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_DATA_DATA_SHIFT)) & ENET_PHY_PMA_MMD_VR_XS_PMA_SNPS_CR_DATA_DATA_MASK) /*! @} */ /*! * @} */ /* end of group ENET_PHY_PMA_MMD_Register_Masks */ /* ENET_PHY_PMA_MMD - Peripheral instance base addresses */ /** Peripheral ENET_PHY_PMA_MMD base address */ #define ENET_PHY_PMA_MMD_BASE (0x20000u) /** Peripheral ENET_PHY_PMA_MMD base pointer */ #define ENET_PHY_PMA_MMD ((ENET_PHY_PMA_MMD_Type *)ENET_PHY_PMA_MMD_BASE) /** Array initializer of ENET_PHY_PMA_MMD peripheral base addresses */ #define ENET_PHY_PMA_MMD_BASE_ADDRS { ENET_PHY_PMA_MMD_BASE } /** Array initializer of ENET_PHY_PMA_MMD peripheral base pointers */ #define ENET_PHY_PMA_MMD_BASE_PTRS { ENET_PHY_PMA_MMD } /*! * @} */ /* end of group ENET_PHY_PMA_MMD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET_PHY_VS_MII_MMD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_VS_MII_MMD_Peripheral_Access_Layer ENET_PHY_VS_MII_MMD Peripheral Access Layer * @{ */ /** ENET_PHY_VS_MII_MMD - Register Layout Typedef */ typedef struct { __IO uint16_t SR_MII_CTRL; /**< SR MII MMD Control, offset: 0x0 */ __I uint16_t SR_MII_STS; /**< SR MII MMD Status, offset: 0x2 */ __I uint16_t SR_MII_DEV_ID1; /**< SR MII MMD Device Identifier 1, offset: 0x4 */ __I uint16_t SR_MII_DEV_ID2; /**< SR MII MMD Device Identifier 2, offset: 0x6 */ __IO uint16_t SR_MII_AN_ADV; /**< SR MII MMD AN Advertisement, offset: 0x8 */ __I uint16_t SR_MII_LP_BABL; /**< SR MII MMD AN Link Partner Base Ability, offset: 0xA */ __I uint16_t SR_MII_AN_EXPN; /**< SR MII MMD AN Expansion, offset: 0xC */ uint8_t RESERVED_0[16]; __I uint16_t SR_MII_EXT_STS; /**< SR MII MMD Extended Status, offset: 0x1E */ uint8_t RESERVED_1[65504]; __IO uint16_t VR_MII_DIG_CTRL1; /**< VR MII MMD Digital Control 1, offset: 0x10000 */ __IO uint16_t VR_MII_AN_CTRL; /**< VR MII MMD AN Control, offset: 0x10002 */ __IO uint16_t VR_MII_AN_INTR_STS; /**< VR MII MMD AN Interrupt and Status, offset: 0x10004 */ uint8_t RESERVED_2[14]; __IO uint16_t VR_MII_LINK_TIMER_CTRL; /**< VR MII MMD Link Timer Control, offset: 0x10014 */ } ENET_PHY_VS_MII_MMD_Type; /* ---------------------------------------------------------------------------- -- ENET_PHY_VS_MII_MMD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_VS_MII_MMD_Register_Masks ENET_PHY_VS_MII_MMD Register Masks * @{ */ /*! @name SR_MII_CTRL - SR MII MMD Control */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5_MASK (0x20U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5_SHIFT (5U) /*! SS5 - Speed Selection */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6_MASK (0x40U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6_SHIFT (6U) /*! SS6 - Speed Selection */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_DUPLEX_MODE_MASK (0x100U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_DUPLEX_MODE_SHIFT (8U) /*! DUPLEX_MODE - Duplex Mode * 0b0..Half duplex * 0b1..Full duplex */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_DUPLEX_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_DUPLEX_MODE_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_DUPLEX_MODE_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RESTART_AN_MASK (0x200U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RESTART_AN_SHIFT (9U) /*! RESTART_AN - Restart Auto-Negotiation (RW, SC Type) */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RESTART_AN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RESTART_AN_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RESTART_AN_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LPM_MASK (0x800U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LPM_SHIFT (11U) /*! LPM - Power-Down Mode * 0b0..Normal operation * 0b1..DWC_XPCS goes to the power-down mode along with the PHY */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LPM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LPM_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LPM_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK (0x1000U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_SHIFT (12U) /*! AN_ENABLE - Enable Auto-Negotiation * 0b1..Enables the Clause 37 auto-negotiation process */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13_MASK (0x2000U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13_SHIFT (13U) /*! SS13 - Speed Selection (LSB) */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LBE_MASK (0x4000U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LBE_SHIFT (14U) /*! LBE - Loopback Enable * 0b1..DWC_XPCS asserts xpcs_loopback_en_o signal * 0b0..DWC_XPCS de-asserts xpcs_loopback_en_o signal */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LBE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LBE_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_LBE_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RST_MASK (0x8000U) #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RST_SHIFT (15U) /*! RST - Soft Reset (RW, SC Type) */ #define ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RST_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_CTRL_RST_MASK) /*! @} */ /*! @name SR_MII_STS - SR MII MMD Status */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_REG_CAP_MASK (0x1U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_REG_CAP_SHIFT (0U) /*! EXT_REG_CAP - Extended Register Capability * 0b1..Extended Register capability exists * 0b0..Extended Register capability does not exist */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_REG_CAP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_REG_CAP_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_REG_CAP_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_LINK_STS_MASK (0x4U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_LINK_STS_SHIFT (2U) /*! LINK_STS - Link Status (RO, LL Type) * 0b1..Link up * 0b0..Link down */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_LINK_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_LINK_STS_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_LINK_STS_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_ABL_MASK (0x8U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_ABL_SHIFT (3U) /*! AN_ABL - Auto-Negotiation Ability * 0b1..DWC_XPCS is able to perform auto-negotiation * 0b0..DWC_XPCS is not able to perform auto-negotiation */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_ABL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_RF_MASK (0x10U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_RF_SHIFT (4U) /*! RF - Remote Fault (RO, LH Type) * 0b1..DWC_XPCS detected a remote fault * 0b0..DWC_XPCS did not detect a remote fault */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_RF_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_RF_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_CMPL_MASK (0x20U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_CMPL_SHIFT (5U) /*! AN_CMPL - Auto-Negotiation Complete * 0b1..The AN process is complete * 0b0..The AN process is not complete */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_CMPL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_CMPL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_AN_CMPL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_MF_PRE_SUP_MASK (0x40U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_MF_PRE_SUP_SHIFT (6U) /*! MF_PRE_SUP - MF Preamble Suppression * 0b1..DWC_XPCS accepts the MDIO frames with preamble suppressed * 0b0..DWC_XPCS does not accept the MDIO frames with preamble suppressed */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_MF_PRE_SUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_MF_PRE_SUP_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_MF_PRE_SUP_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_UN_DIR_ABL_MASK (0x80U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_UN_DIR_ABL_SHIFT (7U) /*! UN_DIR_ABL - Unidirectional Ability * 0b1..DWC_XPCS is able to transmit GMII irrespective of whether device has determined the valid link or not * 0b0..DWC_XPCS is able to transmit GMII only when the device has determined the valid link */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_UN_DIR_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_UN_DIR_ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_UN_DIR_ABL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_STS_ABL_MASK (0x100U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_STS_ABL_SHIFT (8U) /*! EXT_STS_ABL - Extended Status Information * 0b1..Extended Status information is present at register address 16'h000F of this MMD device * 0b0..No Extended Status information is present at register address 16'h000F of this MMD device */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_STS_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_STS_ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_EXT_STS_ABL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100T_MASK (0x200U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100T_SHIFT (9U) /*! HD100T - 100BASE-T2 Half-Duplex Ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100T(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100T_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100T_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100T_MASK (0x400U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100T_SHIFT (10U) /*! FD100T - 100BASE-T2 Full-Duplex Ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100T(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100T_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100T_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD10ABL_MASK (0x800U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD10ABL_SHIFT (11U) /*! HD10ABL - 10 Mbit/s Half-Duplex Ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD10ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_HD10ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_HD10ABL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD10ABL_MASK (0x1000U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD10ABL_SHIFT (12U) /*! FD10ABL - 10 Mbit/s Full-Duplex Ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD10ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_FD10ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_FD10ABL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100ABL_MASK (0x2000U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100ABL_SHIFT (13U) /*! HD100ABL - 100BASE-X Half-Duplex Ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_HD100ABL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100ABL_MASK (0x4000U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100ABL_SHIFT (14U) /*! FD100ABL - 100BASE-X Full-Duplex Ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_FD100ABL_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_ABL100T4_MASK (0x8000U) #define ENET_PHY_VS_MII_MMD_SR_MII_STS_ABL100T4_SHIFT (15U) /*! ABL100T4 - 100BASE-T4 Ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_STS_ABL100T4(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_STS_ABL100T4_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_STS_ABL100T4_MASK) /*! @} */ /*! @name SR_MII_DEV_ID1 - SR MII MMD Device Identifier 1 */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID1_VS_MII_DEV_OUI_3_18_MASK (0xFFFFU) #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID1_VS_MII_DEV_OUI_3_18_SHIFT (0U) /*! VS_MII_DEV_OUI_3_18 - Organizationally Unique Identifier [3:18] */ #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID1_VS_MII_DEV_OUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID1_VS_MII_DEV_OUI_3_18_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID1_VS_MII_DEV_OUI_3_18_MASK) /*! @} */ /*! @name SR_MII_DEV_ID2 - SR MII MMD Device Identifier 2 */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_RN_3_0_MASK (0xFU) #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_RN_3_0_SHIFT (0U) /*! VS_MMD_DEV_RN_3_0 - Revision Number */ #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_RN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_RN_3_0_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_RN_3_0_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_MMN_5_0_MASK (0x3F0U) #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_MMN_5_0_SHIFT (4U) /*! VS_MMD_DEV_MMN_5_0 - Model Number */ #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_MMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_MMN_5_0_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_MMN_5_0_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_OUI_19_24_MASK (0xFC00U) #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_OUI_19_24_SHIFT (10U) /*! VS_MMD_DEV_OUI_19_24 - Organizationally Unique Identifier [19:24] */ #define ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_OUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_OUI_19_24_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_DEV_ID2_VS_MMD_DEV_OUI_19_24_MASK) /*! @} */ /*! @name SR_MII_AN_ADV - SR MII MMD AN Advertisement */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_FD_MASK (0x20U) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_FD_SHIFT (5U) /*! FD - Full Duplex */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_FD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_FD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_FD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_HD_MASK (0x40U) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_HD_SHIFT (6U) /*! HD - Half Duplex */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_HD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_HD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_HD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_PAUSE_MASK (0x180U) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_PAUSE_SHIFT (7U) /*! PAUSE - Pause Ability * 0b00..No pause * 0b01..Asymmetric pause towards the link partner * 0b10..Symmetric pause * 0b11..Symmetric pause and asymmetric pause towards the local device */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_PAUSE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_PAUSE_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_PAUSE_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_RF_MASK (0x3000U) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_RF_SHIFT (12U) /*! RF - Remote Fault * 0b00..No error * 0b01..Offline * 0b10..Link failure * 0b11..Auto-negotiation error */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_RF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_RF_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_RF_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_NP_MASK (0x8000U) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_NP_SHIFT (15U) /*! NP - Next Page */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_NP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_NP_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_AN_ADV_NP_MASK) /*! @} */ /*! @name SR_MII_LP_BABL - SR MII MMD AN Link Partner Base Ability */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_FD_MASK (0x20U) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_FD_SHIFT (5U) /*! LP_FD - Full Duplex */ #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_FD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_FD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_FD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_HD_MASK (0x40U) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_HD_SHIFT (6U) /*! LP_HD - Half Duplex */ #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_HD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_HD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_HD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_PAUSE_MASK (0x180U) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_PAUSE_SHIFT (7U) /*! LP_PAUSE - Pause Ability * 0b00..No pause * 0b01..Asymmetric pause towards the link partner * 0b10..Symmetric pause * 0b11..Both symmetric pause and asymmetric pause towards the local device */ #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_PAUSE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_PAUSE_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_PAUSE_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_RF_MASK (0x3000U) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_RF_SHIFT (12U) /*! LP_RF - Remote Fault * 0b00..No error * 0b01..Offline * 0b10..Link failure * 0b11..Auto-negotiation error */ #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_RF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_RF_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_RF_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_ACK_MASK (0x4000U) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_ACK_SHIFT (14U) /*! LP_ACK - ACK Bit from the Link Partner */ #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_ACK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_ACK_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_ACK_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_NP_MASK (0x8000U) #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_NP_SHIFT (15U) /*! LP_NP - Next Page */ #define ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_NP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_NP_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_LP_BABL_LP_NP_MASK) /*! @} */ /*! @name SR_MII_AN_EXPN - SR MII MMD AN Expansion */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_PG_RCVD_MASK (0x2U) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_PG_RCVD_SHIFT (1U) /*! PG_RCVD - Page Received (RO, LH Type) * 0b1..The local device received a new page * 0b0..The local device did not receive a new page */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_PG_RCVD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_PG_RCVD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_PG_RCVD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_LD_NP_ABL_MASK (0x4U) #define ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_LD_NP_ABL_SHIFT (2U) /*! LD_NP_ABL - Local Device NP Able * 0b1..The local device has the next page ability * 0b0..The local device does not have the next page ability */ #define ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_LD_NP_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_LD_NP_ABL_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_AN_EXPN_LD_NP_ABL_MASK) /*! @} */ /*! @name SR_MII_EXT_STS - SR MII MMD Extended Status */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_HD_MASK (0x1000U) #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_HD_SHIFT (12U) /*! CAP_1G_T_HD - 1000BASE-T Half-Duplex Capable * 0b1..1000BASE-T half-duplex capable * 0b0..Not 1000BASE-T half-duplex capable */ #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_HD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_HD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_HD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_FD_MASK (0x2000U) #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_FD_SHIFT (13U) /*! CAP_1G_T_FD - 1000BASE-T Full-Duplex Capable * 0b1..1000BASE-T full-duplex capable * 0b0..Not 1000BASE-T full-duplex capable */ #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_FD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_FD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_T_FD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_HD_MASK (0x4000U) #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_HD_SHIFT (14U) /*! CAP_1G_X_HD - 1000BASE-X Half-Duplex Capable * 0b1..1000BASE-X half-duplex capable * 0b0..Not 1000BASE-X half-duplex capable */ #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_HD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_HD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_HD_MASK) #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_FD_MASK (0x8000U) #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_FD_SHIFT (15U) /*! CAP_1G_X_FD - 1000BASE-X Full-Duplex Capable * 0b1..1000BASE-X full-duplex capable * 0b0..Not 1000BASE-X full-duplex capable */ #define ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_FD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_FD_SHIFT)) & ENET_PHY_VS_MII_MMD_SR_MII_EXT_STS_CAP_1G_X_FD_MASK) /*! @} */ /*! @name VR_MII_DIG_CTRL1 - VR MII MMD Digital Control 1 */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PHY_MODE_CTRL_MASK (0x1U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PHY_MODE_CTRL_SHIFT (0U) /*! PHY_MODE_CTRL - PHY Mode Control */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PHY_MODE_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PHY_MODE_CTRL_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PHY_MODE_CTRL_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_BYP_PWRUP_MASK (0x2U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_BYP_PWRUP_SHIFT (1U) /*! BYP_PWRUP - Bypass Power-Up Sequence */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_BYP_PWRUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_BYP_PWRUP_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_BYP_PWRUP_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_MASK (0x8U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_SHIFT (3U) /*! CL37_TMR_OVR_RIDE - Over-Ride Control for CL37 Link Timer */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_DTXLANED_0_MASK (0x10U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_DTXLANED_0_SHIFT (4U) /*! DTXLANED_0 - TX Lane 0 Disable */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_DTXLANED_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_DTXLANED_0_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_DTXLANED_0_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_100M_MASK (0x20U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_100M_SHIFT (5U) /*! EN_100M - Enable 100Mbit/s PCS Mode */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_100M(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_100M_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_100M_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PRE_EMP_MASK (0x40U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PRE_EMP_SHIFT (6U) /*! PRE_EMP - Pre-emption Packet Enable */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PRE_EMP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PRE_EMP_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PRE_EMP_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_MAC_AUTO_SW_MASK (0x200U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_MAC_AUTO_SW_SHIFT (9U) /*! MAC_AUTO_SW - Automatic Speed Mode Change After CL37 AN */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_MAC_AUTO_SW(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_MAC_AUTO_SW_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_MAC_AUTO_SW_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PWRSV_MASK (0x800U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PWRSV_SHIFT (11U) /*! PWRSV - Power Save * 0b0..Normal operation * 0b1..DWC_XPCS and the PHY enter the power-save mode */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PWRSV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PWRSV_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_PWRSV_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_VSMMD1_MASK (0x2000U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_VSMMD1_SHIFT (13U) /*! EN_VSMMD1 - Enable Vendor-Specific MMD1 */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_VSMMD1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_VSMMD1_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_EN_VSMMD1_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_R2TLBE_MASK (0x4000U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_R2TLBE_SHIFT (14U) /*! R2TLBE - RX to TX Loopback Enable * 0b0..Loopback path is disabled * 0b1..Loopback path is enabled */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_R2TLBE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_R2TLBE_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_R2TLBE_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_VR_RST_MASK (0x8000U) #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_VR_RST_SHIFT (15U) /*! VR_RST - Vendor-Specific Soft Reset (RW, SC Type) */ #define ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_VR_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_VR_RST_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_VR_RST_MASK) /*! @} */ /*! @name VR_MII_AN_CTRL - VR MII MMD AN Control */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN_MASK (0x1U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN_SHIFT (0U) /*! MII_AN_INTR_EN - Clause 37 AN Complete Interrupt Enable * 0b1..Enables the generation of Clause 37 auto-negotiation complete interrupt output * 0b0..Disables the generation of Clause 37 auto-negotiation complete interrupt */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_PCS_MODE_MASK (0x6U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_PCS_MODE_SHIFT (1U) /*! PCS_MODE - PCS Mode * 0b00..1000BASE-X mode (clause 37 auto-negotiation is as per 1000BaseX) * 0b10..SGMII mode (clause 37 auto-negotiation is as per SGMII) */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_PCS_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_PCS_MODE_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_PCS_MODE_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG_MASK (0x8U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG_SHIFT (3U) /*! TX_CONFIG - Transmit Configuration * 0b1..Configures DWC_XPCS as the PHY side SGMII/USXGMII * 0b0..Configures DWC_XPCS as the MAC side SGMII/USXGMII */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_SGMII_LINK_STS_MASK (0x10U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_SGMII_LINK_STS_SHIFT (4U) /*! SGMII_LINK_STS - SGMII Link Status / USXGMII Link Status * 0b0..Link down * 0b1..Link up */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_SGMII_LINK_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_SGMII_LINK_STS_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_SGMII_LINK_STS_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_CTRL_MASK (0x100U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_CTRL_SHIFT (8U) /*! MII_CTRL - MII Control * 0b0..4-bit MII * 0b1..8-bit MII */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_CTRL_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_CTRL_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_IND_TX_EN_MASK (0x200U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_IND_TX_EN_SHIFT (9U) /*! IND_TX_EN - Independent Transmit Enable in 1000BASE-X Mode * 0b1..DWC_XPCS transmits the GMII TX data, irrespective of its receive link status (provided auto-negotiation is not enabled) * 0b0..DWC_XPCS sends IDLE till its receiver has attained synchronization */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_IND_TX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_IND_TX_EN_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_IND_TX_EN_MASK) /*! @} */ /*! @name VR_MII_AN_INTR_STS - VR MII MMD AN Interrupt and Status */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK (0x1U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_SHIFT (0U) /*! CL37_ANCMPLT_INTR - Clause 37 AN Complete Interrupt (SS, WC Type) */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANSGM_STS_MASK (0x1EU) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANSGM_STS_SHIFT (1U) /*! CL37_ANSGM_STS - Clause 37 AN SGMII Status * 0bxxx0..Half Duplex * 0bxxx1..Full Duplex * 0bx01x..100 Mbit/s speed link * 0bx10x..1000 Mbit/s speed link * 0b0xxx..Link is Down * 0b1xxx..Link is Up */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANSGM_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANSGM_STS_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANSGM_STS_MASK) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS_MASK (0x7F00U) #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS_SHIFT (8U) /*! USXG_AN_STS - USXGMII Clause 37 AN Status * 0bxxxxxx0..EEE clock-stop not supported * 0bxxxxxx1..EEE clock-stop supported * 0bxxxxx1x..EEE supported * 0bxxxxx0x..EEE not supported * 0bxx001xx..100 Mbit/s speed link * 0bxx010xx..1000 Mbit/s speed link * 0bxx011xx..10 Gbit/s speed link * 0bxx100xx..2.5 Gbit/s speed link * 0bxx101xx..5 Gbit/s speed link * 0bx0xxxxx..Half Duplex * 0bx1xxxxx..Full Duplex * 0b0xxxxxx..Link is Down * 0b1xxxxxx..Link is Up */ #define ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS_MASK) /*! @} */ /*! @name VR_MII_LINK_TIMER_CTRL - VR MII MMD Link Timer Control */ /*! @{ */ #define ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK (0xFFFFU) #define ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME_SHIFT (0U) /*! CL37_LINK_TIME - Programmable Link Timer Value for Clause 37 Auto-Negotiation */ #define ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME_SHIFT)) & ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK) /*! @} */ /*! * @} */ /* end of group ENET_PHY_VS_MII_MMD_Register_Masks */ /* ENET_PHY_VS_MII_MMD - Peripheral instance base addresses */ /** Peripheral ENET_PHY_VS_MII_MMD base address */ #define ENET_PHY_VS_MII_MMD_BASE (0x3E0000u) /** Peripheral ENET_PHY_VS_MII_MMD base pointer */ #define ENET_PHY_VS_MII_MMD ((ENET_PHY_VS_MII_MMD_Type *)ENET_PHY_VS_MII_MMD_BASE) /** Array initializer of ENET_PHY_VS_MII_MMD peripheral base addresses */ #define ENET_PHY_VS_MII_MMD_BASE_ADDRS { ENET_PHY_VS_MII_MMD_BASE } /** Array initializer of ENET_PHY_VS_MII_MMD peripheral base pointers */ #define ENET_PHY_VS_MII_MMD_BASE_PTRS { ENET_PHY_VS_MII_MMD } /*! * @} */ /* end of group ENET_PHY_VS_MII_MMD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET_PHY_VS_MMD1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_VS_MMD1_Peripheral_Access_Layer ENET_PHY_VS_MMD1 Peripheral Access Layer * @{ */ /** ENET_PHY_VS_MMD1 - Register Layout Typedef */ typedef struct { __I uint16_t SR_VSMMD_PMA_ID1; /**< SR Control MMD PMA Device Identifier 1, offset: 0x0 */ __I uint16_t SR_VSMMD_PMA_ID2; /**< SR Control MMD PMA Device Identifier 2, offset: 0x2 */ __I uint16_t SR_VSMMD_DEV_ID1; /**< SR Control MMD Device Identifier 1, offset: 0x4 */ __I uint16_t SR_VSMMD_DEV_ID2; /**< SR Control MMD Device Identifier 2, offset: 0x6 */ __I uint16_t SR_VSMMD_PCS_ID1; /**< SR Control MMD PCS Device Identifier 1, offset: 0x8 */ __I uint16_t SR_VSMMD_PCS_ID2; /**< SR Control MMD PCS Device Identifier 2, offset: 0xA */ uint16_t SR_VSMMD_AN_ID1; /**< SR Control MMD AN Device Identifier 1, offset: 0xC */ uint16_t SR_VSMMD_AN_ID2; /**< SR Control MMD AN Device Identifier 2, offset: 0xE */ __I uint16_t SR_VSMMD_STS; /**< SR Control MMD Status, offset: 0x10 */ __IO uint16_t SR_VSMMD_CTRL; /**< SR Control MMD Control, offset: 0x12 */ uint8_t RESERVED_0[8]; __I uint16_t SR_VSMMD_PKGID1; /**< SR Control MMD Package Identifier 1, offset: 0x1C */ __I uint16_t SR_VSMMD_PKGID2; /**< SR Control MMD Package Identifier 2, offset: 0x1E */ } ENET_PHY_VS_MMD1_Type; /* ---------------------------------------------------------------------------- -- ENET_PHY_VS_MMD1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_VS_MMD1_Register_Masks ENET_PHY_VS_MMD1 Register Masks * @{ */ /*! @name SR_VSMMD_PMA_ID1 - SR Control MMD PMA Device Identifier 1 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID1_PMADOUI_3_18_MASK (0xFFFFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID1_PMADOUI_3_18_SHIFT (0U) /*! PMADOUI_3_18 - Organizationally Unique Identifier [3:18] for PMA MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID1_PMADOUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID1_PMADOUI_3_18_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID1_PMADOUI_3_18_MASK) /*! @} */ /*! @name SR_VSMMD_PMA_ID2 - SR Control MMD PMA Device Identifier 2 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADRN_3_0_MASK (0xFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADRN_3_0_SHIFT (0U) /*! PMADRN_3_0 - Revision Number for PMA MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADRN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADRN_3_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADRN_3_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADMMN_5_0_MASK (0x3F0U) #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADMMN_5_0_SHIFT (4U) /*! PMADMMN_5_0 - Model Number for PMA MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADMMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADMMN_5_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADMMN_5_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADOUI_19_24_MASK (0xFC00U) #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADOUI_19_24_SHIFT (10U) /*! PMADOUI_19_24 - Organizationally Unique Identifier [19:24] for PMA MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADOUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADOUI_19_24_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PMA_ID2_PMADOUI_19_24_MASK) /*! @} */ /*! @name SR_VSMMD_DEV_ID1 - SR Control MMD Device Identifier 1 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID1_VSDOUI_3_18_MASK (0xFFFFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID1_VSDOUI_3_18_SHIFT (0U) /*! VSDOUI_3_18 - Organizationally Unique Identifier [3:18] for Vendor-Specific MMD1 */ #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID1_VSDOUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID1_VSDOUI_3_18_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID1_VSDOUI_3_18_MASK) /*! @} */ /*! @name SR_VSMMD_DEV_ID2 - SR Control MMD Device Identifier 2 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDRN_3_0_MASK (0xFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDRN_3_0_SHIFT (0U) /*! VSDRN_3_0 - Revision Number for Vendor-Specific MMD1 */ #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDRN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDRN_3_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDRN_3_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDMMN_5_0_MASK (0x3F0U) #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDMMN_5_0_SHIFT (4U) /*! VSDMMN_5_0 - Model Number for Vendor-Specific MMD1 */ #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDMMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDMMN_5_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDMMN_5_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDOUI_19_24_MASK (0xFC00U) #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDOUI_19_24_SHIFT (10U) /*! VSDOUI_19_24 - Organizationally Unique Identifier [19:24] for Vendor-Specific MMD1 */ #define ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDOUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDOUI_19_24_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_DEV_ID2_VSDOUI_19_24_MASK) /*! @} */ /*! @name SR_VSMMD_PCS_ID1 - SR Control MMD PCS Device Identifier 1 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID1_PCSDOUI_3_18_MASK (0xFFFFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID1_PCSDOUI_3_18_SHIFT (0U) /*! PCSDOUI_3_18 - Organizationally Unique Identifier [3:18] for PCS MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID1_PCSDOUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID1_PCSDOUI_3_18_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID1_PCSDOUI_3_18_MASK) /*! @} */ /*! @name SR_VSMMD_PCS_ID2 - SR Control MMD PCS Device Identifier 2 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDRN_3_0_MASK (0xFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDRN_3_0_SHIFT (0U) /*! PCSDRN_3_0 - Revision Number for XS or PCS MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDRN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDRN_3_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDRN_3_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDMMN_5_0_MASK (0x3F0U) #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDMMN_5_0_SHIFT (4U) /*! PCSDMMN_5_0 - Model Number for XS or PCS MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDMMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDMMN_5_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDMMN_5_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDOUI_19_24_MASK (0xFC00U) #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDOUI_19_24_SHIFT (10U) /*! PCSDOUI_19_24 - Organizationally Unique Identifier[19:24] for PCS MMD */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDOUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDOUI_19_24_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PCS_ID2_PCSDOUI_19_24_MASK) /*! @} */ /*! @name SR_VSMMD_STS - SR Control MMD Status */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_STS_VSDP_MASK (0xC000U) #define ENET_PHY_VS_MMD1_SR_VSMMD_STS_VSDP_SHIFT (14U) /*! VSDP - Control MMD Device Present * 0b10..Device responding at this address * 0b00, 0b11, 0b11..No device responding at this address */ #define ENET_PHY_VS_MMD1_SR_VSMMD_STS_VSDP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_STS_VSDP_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_STS_VSDP_MASK) /*! @} */ /*! @name SR_VSMMD_CTRL - SR Control MMD Control */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PCS_XS_MMD_EN_MASK (0x2U) #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PCS_XS_MMD_EN_SHIFT (1U) /*! PCS_XS_MMD_EN - PCS MMD Enable */ #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PCS_XS_MMD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PCS_XS_MMD_EN_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PCS_XS_MMD_EN_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_MII_MMD_EN_MASK (0x4U) #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_MII_MMD_EN_SHIFT (2U) /*! MII_MMD_EN - VS MMD Enable */ #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_MII_MMD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_MII_MMD_EN_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_MII_MMD_EN_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PMA_MMD_EN_MASK (0x8U) #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PMA_MMD_EN_SHIFT (3U) /*! PMA_MMD_EN - PMA MMD Enable */ #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PMA_MMD_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PMA_MMD_EN_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_PMA_MMD_EN_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_FASTSIM_MASK (0x10U) #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_FASTSIM_SHIFT (4U) /*! FASTSIM - Fast Simulation Enable */ #define ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_FASTSIM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_FASTSIM_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_CTRL_FASTSIM_MASK) /*! @} */ /*! @name SR_VSMMD_PKGID1 - SR Control MMD Package Identifier 1 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID1_MMDPOUI_3_18_MASK (0xFFFFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID1_MMDPOUI_3_18_SHIFT (0U) /*! MMDPOUI_3_18 - Organizationally Unique Identifier */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID1_MMDPOUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PKGID1_MMDPOUI_3_18_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PKGID1_MMDPOUI_3_18_MASK) /*! @} */ /*! @name SR_VSMMD_PKGID2 - SR Control MMD Package Identifier 2 */ /*! @{ */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPRN_3_0_MASK (0xFU) #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPRN_3_0_SHIFT (0U) /*! MMDPRN_3_0 - Revision Number */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPRN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPRN_3_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPRN_3_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPMMN_5_0_MASK (0x3F0U) #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPMMN_5_0_SHIFT (4U) /*! MMDPMMN_5_0 - Model Number */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPMMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPMMN_5_0_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPMMN_5_0_MASK) #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPOUI_19_24_MASK (0xFC00U) #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPOUI_19_24_SHIFT (10U) /*! MMDPOUI_19_24 - Organizationally Unique Identifier */ #define ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPOUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPOUI_19_24_SHIFT)) & ENET_PHY_VS_MMD1_SR_VSMMD_PKGID2_MMDPOUI_19_24_MASK) /*! @} */ /*! * @} */ /* end of group ENET_PHY_VS_MMD1_Register_Masks */ /* ENET_PHY_VS_MMD1 - Peripheral instance base addresses */ /** Peripheral ENET_PHY_VS_MMD1 base address */ #define ENET_PHY_VS_MMD1_BASE (0x3C0000u) /** Peripheral ENET_PHY_VS_MMD1 base pointer */ #define ENET_PHY_VS_MMD1 ((ENET_PHY_VS_MMD1_Type *)ENET_PHY_VS_MMD1_BASE) /** Array initializer of ENET_PHY_VS_MMD1 peripheral base addresses */ #define ENET_PHY_VS_MMD1_BASE_ADDRS { ENET_PHY_VS_MMD1_BASE } /** Array initializer of ENET_PHY_VS_MMD1 peripheral base pointers */ #define ENET_PHY_VS_MMD1_BASE_PTRS { ENET_PHY_VS_MMD1 } /*! * @} */ /* end of group ENET_PHY_VS_MMD1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ENET_PHY_XS_PCS_MMD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_XS_PCS_MMD_Peripheral_Access_Layer ENET_PHY_XS_PCS_MMD Peripheral Access Layer * @{ */ /** ENET_PHY_XS_PCS_MMD - Register Layout Typedef */ typedef struct { __IO uint16_t SR_XS_PCS_CTRL1; /**< SR XS or PCS MMD Control 1, offset: 0x0 */ __I uint16_t SR_XS_PCS_STS1; /**< SR XS or PCS MMD Status1, offset: 0x2 */ __I uint16_t SR_XS_PCS_DEV_ID1; /**< SR XS or PCS MMD Device Identifier 1, offset: 0x4 */ __I uint16_t SR_XS_PCS_DEV_ID2; /**< SR XS or PCS MMD Device Identifier 2, offset: 0x6 */ __I uint16_t SR_XS_PCS_SPD_ABL; /**< SR XS or PCS MMD Speed Ability, offset: 0x8 */ __I uint16_t SR_XS_PCS_DEV_PKG1; /**< SR XS or PCS MMD Devices in Package 1, offset: 0xA */ __I uint16_t SR_XS_PCS_DEV_PKG2; /**< SR XS or PCS MMD Devices in Package 2, offset: 0xC */ __IO uint16_t SR_XS_PCS_CTRL2; /**< SR PCS Control 2, offset: 0xE */ __I uint16_t SR_XS_PCS_STS2; /**< SR XS or PCS MMD Status 2, offset: 0x10 */ __I uint16_t SR_XS_PCS_STS3; /**< SR PCS MMD Status 3, offset: 0x12 */ uint8_t RESERVED_0[8]; __I uint16_t SR_XS_PCS_PKG1; /**< SR XS or PCS MMD Package Identifier 1, offset: 0x1C */ __I uint16_t SR_XS_PCS_PKG2; /**< SR XS or PCS MMD Package Identifier 2, offset: 0x1E */ uint8_t RESERVED_1[8]; __I uint16_t SR_XS_PCS_EEE_ABL; /**< SR XS or PCS MMD EEE Capability, offset: 0x28 */ __I uint16_t SR_XS_PCS_EEE_ABL2; /**< SR PCS MMD EEE Control and Capability 2, offset: 0x2A */ __I uint16_t SR_XS_PCS_EEE_WKERR; /**< SR XS or PCS MMD EEE Wake Error Counter, offset: 0x2C */ uint8_t RESERVED_2[2]; __I uint16_t SR_XS_PCS_LSTS; /**< SR XS or PCS MMD 10GBASE-X Lane Status, offset: 0x30 */ __IO uint16_t SR_XS_PCS_TCTRL; /**< SR XS or PCS MMD 10GBASE-X Test Control, offset: 0x32 */ uint8_t RESERVED_3[12]; __I uint16_t SR_XS_PCS_KR_STS1; /**< SR PCS MMD 10GBASE-R Status 1, offset: 0x40 */ __I uint16_t SR_XS_PCS_KR_STS2; /**< SR PCS MMD 10GBASE-R Status 2, offset: 0x42 */ __IO uint16_t SR_XS_PCS_TP_A0; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A0, offset: 0x44 */ __IO uint16_t SR_XS_PCS_TP_A1; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A1, offset: 0x46 */ __IO uint16_t SR_XS_PCS_TP_A2; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A2 Register, offset: 0x48 */ __IO uint16_t SR_XS_PCS_TP_A3; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A3 Register, offset: 0x4A */ __IO uint16_t SR_XS_PCS_TP_B0; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B0, offset: 0x4C */ __IO uint16_t SR_XS_PCS_TP_B1; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B1, offset: 0x4E */ __IO uint16_t SR_XS_PCS_TP_B2; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B2, offset: 0x50 */ __IO uint16_t SR_XS_PCS_TP_B3; /**< SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B3, offset: 0x52 */ __IO uint16_t SR_XS_PCS_TP_CTRL; /**< SR PCS BASE-R Test Pattern Control, offset: 0x54 */ __I uint16_t SR_XS_PCS_TP_ERRCTR; /**< SR PCS BASE-R Test Pattern Error Counter, offset: 0x56 */ uint8_t RESERVED_4[3512]; __I uint16_t SR_PCS_TIME_SYNC_PCS_ABL; /**< SR PCS MMD Time Sync Capability, offset: 0xE10 */ __I uint16_t SR_PCS_TIME_SYNC_TX_MAX_DLY_LWR; /**< SR PCS MMD Time Sync TX Max Delay Lower, offset: 0xE12 */ __I uint16_t SR_PCS_TIME_SYNC_TX_MAX_DLY_UPR; /**< SR PCS MMD Time Sync TX Max Delay Upper, offset: 0xE14 */ __I uint16_t SR_PCS_TIME_SYNC_TX_MIN_DLY_LWR; /**< SR PCS MMD Time Sync TX Min Delay Lower, offset: 0xE16 */ __I uint16_t SR_PCS_TIME_SYNC_TX_MIN_DLY_UPR; /**< SR PCS MMD Time Sync TX Min Delay Upper, offset: 0xE18 */ __I uint16_t SR_PCS_TIME_SYNC_RX_MAX_DLY_LWR; /**< SR PCS MMD Time Sync RX Max Delay Lower, offset: 0xE1A */ __I uint16_t SR_PCS_TIME_SYNC_RX_MAX_DLY_UPR; /**< SR PCS MMD Time Sync RX Max Delay Upper, offset: 0xE1C */ __I uint16_t SR_PCS_TIME_SYNC_RX_MIN_DLY_LWR; /**< SR PCS MMD Time Sync RX Min Delay Lower, offset: 0xE1E */ __I uint16_t SR_PCS_TIME_SYNC_RX_MIN_DLY_UPR; /**< SR PCS MMD Time Sync RX Min Delay Upper, offset: 0xE20 */ uint8_t RESERVED_5[61918]; __IO uint16_t VR_XS_PCS_DIG_CTRL1; /**< VR XS or PCS MMD Digital Control 1, offset: 0x10000 */ __IO uint16_t VR_XS_PCS_DIG_CTRL2; /**< VR XS or PCS MMD Digital Control 2, offset: 0x10002 */ __IO uint16_t VR_XS_PCS_DIG_ERRCNT_SEL; /**< VR XS or PCS MMD Digital Error Count Select, offset: 0x10004 */ uint8_t RESERVED_6[2]; __I uint16_t VR_XS_PCS_XAUI_CTRL; /**< VR XS or PCS MMD XAUI Mode Control, offset: 0x10008 */ __IO uint16_t VR_XS_PCS_DEBUG_CTRL; /**< VR XS or PCS MMD Debug Control, offset: 0x1000A */ __IO uint16_t VR_XS_PCS_EEE_MCTRL0; /**< VR XS or PCS MMD EEE Mode Control, offset: 0x1000C */ __IO uint16_t VR_XS_PCS_KR_CTRL; /**< VR PCS 10GBASE-R Control, offset: 0x1000E */ __IO uint16_t VR_XS_PCS_EEE_TXTIMER; /**< VR XS or PCS MMD EEE TX Timer, offset: 0x10010 */ __IO uint16_t VR_XS_PCS_EEE_RXTIMER; /**< VR XS or PCS MMD EEE RX Timer, offset: 0x10012 */ uint8_t RESERVED_7[2]; __IO uint16_t VR_XS_PCS_EEE_MCTRL1; /**< VR XS or PCS MMD EEE Mode Control 1, offset: 0x10016 */ uint8_t RESERVED_8[8]; __I uint16_t VR_XS_PCS_DIG_STS; /**< VR XS or PCS MMD Digital Status, offset: 0x10020 */ __I uint16_t VR_XS_PCS_ICG_ERRCNT1; /**< VR XS or PCS MMD Invalid Code Group Error Count 1, offset: 0x10022 */ } ENET_PHY_XS_PCS_MMD_Type; /* ---------------------------------------------------------------------------- -- ENET_PHY_XS_PCS_MMD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_PHY_XS_PCS_MMD_Register_Masks ENET_PHY_XS_PCS_MMD Register Masks * @{ */ /*! @name SR_XS_PCS_CTRL1 - SR XS or PCS MMD Control 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS_5_2_MASK (0x3CU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS_5_2_SHIFT (2U) /*! SS_5_2 - Speed Selection Bits [5:2] */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS_5_2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS_5_2_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS_5_2_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS6_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS6_SHIFT (6U) /*! SS6 - Speed Selection Bit 6 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS6(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS6_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS6_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_CS_EN_MASK (0x400U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_CS_EN_SHIFT (10U) /*! CS_EN - CS_EN */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_CS_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_CS_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_CS_EN_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_LPM_MASK (0x800U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_LPM_SHIFT (11U) /*! LPM - Low-Power Enable * 0b0..Normal operation * 0b1..DWC_XPCS goes to power-down mode along with the PHY */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_LPM(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_LPM_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_LPM_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS13_MASK (0x2000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS13_SHIFT (13U) /*! SS13 - Speed Selection * 0b0..DWC_XPCS is in 1G speed * 0b1..DWC_XPCS is in 10G speed */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS13(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS13_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_SS13_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST_MASK (0x8000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST_SHIFT (15U) /*! RST - Soft Reset (RW, SC Type) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST_MASK) /*! @} */ /*! @name SR_XS_PCS_STS1 - SR XS or PCS MMD Status1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_LPMS_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_LPMS_SHIFT (1U) /*! LPMS - Low-Power Mode Support */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_LPMS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_LPMS_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_LPMS_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RLU_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RLU_SHIFT (2U) /*! RLU - RX Link Up (RO, LL Type) * 0b0..Not successful * 0b1..Successful */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RLU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RLU_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RLU_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_CSC_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_CSC_SHIFT (6U) /*! CSC - Clock Stop Capable * 0b1..The MAC can stop the clock during the LPI mode * 0b0..The MAC cannot stop the clock during the LPI mode */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_CSC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_CSC_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_CSC_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_FLT_MASK (0x80U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_FLT_SHIFT (7U) /*! FLT - Fault Condition Detected */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_FLT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_FLT_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_FLT_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPII_MASK (0x100U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPII_SHIFT (8U) /*! RXLPII - RX LPI Indication * 0b1..DWC_XPCS RX is currently receiving LPI * 0b0..DWC_XPCS RX is currently not receiving LPI */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPII(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPII_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPII_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPII_MASK (0x200U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPII_SHIFT (9U) /*! TXLPII - TX LPI Indication * 0b1..DWC_XPCS TX is currently receiving LPI * 0b0..DWC_XPCS TX is currently not receiving LPI */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPII(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPII_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPII_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPIR_MASK (0x400U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPIR_SHIFT (10U) /*! RXLPIR - RX LPI Received (RO, LH Type) * 0b1..LPI received * 0b0..LPI not received */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPIR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPIR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_RXLPIR_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPIR_MASK (0x800U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPIR_SHIFT (11U) /*! TXLPIR - TX LPI Received (RO, LH Type) * 0b1..LPI received * 0b0..LPI not received */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPIR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPIR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS1_TXLPIR_MASK) /*! @} */ /*! @name SR_XS_PCS_DEV_ID1 - SR XS or PCS MMD Device Identifier 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID1_PCS_DEV_OUI_3_18_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID1_PCS_DEV_OUI_3_18_SHIFT (0U) /*! PCS_DEV_OUI_3_18 - Organizationally Unique Identifier [3:18] */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID1_PCS_DEV_OUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID1_PCS_DEV_OUI_3_18_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID1_PCS_DEV_OUI_3_18_MASK) /*! @} */ /*! @name SR_XS_PCS_DEV_ID2 - SR XS or PCS MMD Device Identifier 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_RN_3_0_MASK (0xFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_RN_3_0_SHIFT (0U) /*! PCS_DEV_RN_3_0 - Revision Number */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_RN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_RN_3_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_RN_3_0_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_MMN_5_0_MASK (0x3F0U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_MMN_5_0_SHIFT (4U) /*! PCS_DEV_MMN_5_0 - Model Number */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_MMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_MMN_5_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_MMN_5_0_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_OUI_19_24_MASK (0xFC00U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_OUI_19_24_SHIFT (10U) /*! PCS_DEV_OUI_19_24 - Organizationally Unique Identifier [19:24] */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_OUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_OUI_19_24_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_ID2_PCS_DEV_OUI_19_24_MASK) /*! @} */ /*! @name SR_XS_PCS_SPD_ABL - SR XS or PCS MMD Speed Ability */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_SPD_ABL_XGC_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_SPD_ABL_XGC_SHIFT (0U) /*! XGC - 10G Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_SPD_ABL_XGC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_SPD_ABL_XGC_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_SPD_ABL_XGC_MASK) /*! @} */ /*! @name SR_XS_PCS_DEV_PKG1 - SR XS or PCS MMD Devices in Package 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_CLS22_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_CLS22_SHIFT (0U) /*! CLS22 - Clause 22 Register Support */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_CLS22(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_CLS22_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_CLS22_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PMA_PMD_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PMA_PMD_SHIFT (1U) /*! PMA_PMD - PMA or PMD MMD */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PMA_PMD(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PMA_PMD_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PMA_PMD_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_WIS_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_WIS_SHIFT (2U) /*! WIS - WIS MMD */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_WIS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_WIS_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_WIS_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PCS_MASK (0x8U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PCS_SHIFT (3U) /*! PCS - PCS MMD */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PCS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PCS_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PCS_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PHYXS_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PHYXS_SHIFT (4U) /*! PHYXS - PHY XGXS MMD */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PHYXS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PHYXS_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_PHYXS_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_DTEXS_MASK (0x20U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_DTEXS_SHIFT (5U) /*! DTEXS - DTE XGXS MMD */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_DTEXS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_DTEXS_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_DTEXS_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_TC_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_TC_SHIFT (6U) /*! TC - TC MMD */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_TC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_TC_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_TC_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_AN_MASK (0x80U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_AN_SHIFT (7U) /*! AN - Auto-Negotiation MMD */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_AN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_AN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG1_AN_MASK) /*! @} */ /*! @name SR_XS_PCS_DEV_PKG2 - SR XS or PCS MMD Devices in Package 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD1_MASK (0x4000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD1_SHIFT (14U) /*! VSD1 - Vendor-specific Device 1 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD1_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD1_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD2_MASK (0x8000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD2_SHIFT (15U) /*! VSD2 - Vendor-Specific Device 2 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD2_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_DEV_PKG2_VSD2_MASK) /*! @} */ /*! @name SR_XS_PCS_CTRL2 - SR PCS Control 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK (0xFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_SHIFT (0U) /*! PCS_TYPE_SEL - PCS Type Select * 0b0001..Select 10GBASE-X PCS Type * *..Reserved */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK) /*! @} */ /*! @name SR_XS_PCS_STS2 - SR XS or PCS MMD Status 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_EN_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_EN_SHIFT (0U) /*! CAP_EN - 10GBASE-R Capable * 0b1..DWC_XPCS can support 10GBASE-R PCS type * 0b0..DWC_XPCS cannot support 10GBASE-R PCS type */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_EN_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10_1GC_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10_1GC_SHIFT (1U) /*! CAP_10_1GC - 10GBASE-X Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10_1GC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10_1GC_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10_1GC_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBW_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBW_SHIFT (2U) /*! CAP_10GBW - 10GBASE-W Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBW(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBW_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBW_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBT_MASK (0x8U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBT_SHIFT (3U) /*! CAP_10GBT - 10GBASE-T Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBT_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_CAP_10GBT_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_RF_MASK (0x400U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_RF_SHIFT (10U) /*! RF - Receiver Fault (LH Type) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_RF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_RF_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_RF_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_TF_MASK (0x800U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_TF_SHIFT (11U) /*! TF - Transmitter Fault (LH Type) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_TF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_TF_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_TF_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_DS_MASK (0xC000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_DS_SHIFT (14U) /*! DS - Device Present Status * 0b10..MMD is present and responding to this register address * *..MMD is not present or not functioning properly */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_DS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_DS_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS2_DS_MASK) /*! @} */ /*! @name SR_XS_PCS_STS3 - SR PCS MMD Status 3 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_200GR_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_200GR_SHIFT (0U) /*! CAP_200GR - 200GBASE-R Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_200GR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_200GR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_200GR_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_400GR_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_400GR_SHIFT (1U) /*! CAP_400GR - 400GBASE-R Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_400GR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_400GR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_400GR_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_2PT5GX_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_2PT5GX_SHIFT (2U) /*! CAP_2PT5GX - 2.5GBASE-X Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_2PT5GX(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_2PT5GX_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_2PT5GX_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_5GR_MASK (0x8U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_5GR_SHIFT (3U) /*! CAP_5GR - 5GBASE-R Capable */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_5GR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_5GR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_STS3_CAP_5GR_MASK) /*! @} */ /*! @name SR_XS_PCS_PKG1 - SR XS or PCS MMD Package Identifier 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG1_PCS_PKG_OUI_3_18_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG1_PCS_PKG_OUI_3_18_SHIFT (0U) /*! PCS_PKG_OUI_3_18 - Organizationally Unique Identifier */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG1_PCS_PKG_OUI_3_18(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG1_PCS_PKG_OUI_3_18_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG1_PCS_PKG_OUI_3_18_MASK) /*! @} */ /*! @name SR_XS_PCS_PKG2 - SR XS or PCS MMD Package Identifier 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_RN_3_0_MASK (0xFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_RN_3_0_SHIFT (0U) /*! PCS_PKG_RN_3_0 - Revision Number */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_RN_3_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_RN_3_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_RN_3_0_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_MMN_5_0_MASK (0x3F0U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_MMN_5_0_SHIFT (4U) /*! PCS_PKG_MMN_5_0 - Model Number */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_MMN_5_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_MMN_5_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_MMN_5_0_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_OUI_19_24_MASK (0xFC00U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_OUI_19_24_SHIFT (10U) /*! PCS_PKG_OUI_19_24 - Organizationally Unique Identifier */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_OUI_19_24(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_OUI_19_24_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_PKG2_PCS_PKG_OUI_19_24_MASK) /*! @} */ /*! @name SR_XS_PCS_EEE_ABL - SR XS or PCS MMD EEE Capability */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_100TEE_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_100TEE_SHIFT (1U) /*! EN_100TEE - 100BASE-T Mode EEE Support * 0b0..EEE is not supported in the 100BASE-T mode * 0b1..EEE is supported in the 100BASE-T mode */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_100TEE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_100TEE_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_100TEE_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_1GTEEE_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_1GTEEE_SHIFT (2U) /*! EN_1GTEEE - 1000BASE-T Mode EEE Support * 0b0..EEE is not supported in the 1000BASE-T mode * 0b1..EEE is supported in the 1000BASE-T mode */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_1GTEEE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_1GTEEE_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_EN_1GTEEE_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_TEEE_MASK (0x8U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_TEEE_SHIFT (3U) /*! TEEE - 10GBASE-T Mode EEE Support * 0b0..EEE is not supported in the 10GBASE-T mode * 0b1..EEE is supported in the 10GBASE-T mode */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_TEEE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_TEEE_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_TEEE_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KXEEE_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KXEEE_SHIFT (4U) /*! KXEEE - XGXS, or 1G EEE Support */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KXEEE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KXEEE_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KXEEE_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KX4EEE_MASK (0x20U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KX4EEE_SHIFT (5U) /*! KX4EEE - 10GBASE-X PCS EEE Support * 0b0..EEE is not supported in 10GBASE-X PCS mode * 0b1..EE is supported in 10GBASE-X PCS mode */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KX4EEE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KX4EEE_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KX4EEE_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KREEE_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KREEE_SHIFT (6U) /*! KREEE - 10GBASE-R PCS Mode EEE Support * 0b0..EEE is not supported in 10GBASE-R PCS mode * 0b1..EEE is supported in 10GBASE-R PCS or mode */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KREEE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KREEE_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL_KREEE_MASK) /*! @} */ /*! @name SR_XS_PCS_EEE_ABL2 - SR PCS MMD EEE Control and Capability 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_2PT5GT_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_2PT5GT_SHIFT (0U) /*! EEE_2PT5GT - 2.5GBASE-T EEE Mode Support */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_2PT5GT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_2PT5GT_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_2PT5GT_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_5GT_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_5GT_SHIFT (1U) /*! EEE_5GT - 5GBASE-T EEE Mode Support */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_5GT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_5GT_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_5GT_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_25GT_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_25GT_SHIFT (2U) /*! EEE_25GT - 25GBASE-T EEE Mode Support */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_25GT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_25GT_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_ABL2_EEE_25GT_MASK) /*! @} */ /*! @name SR_XS_PCS_EEE_WKERR - SR XS or PCS MMD EEE Wake Error Counter */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_WKERR_EEE_WEC_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_WKERR_EEE_WEC_SHIFT (0U) /*! EEE_WEC - EEE Wake Error Counter */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_WKERR_EEE_WEC(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_WKERR_EEE_WEC_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_EEE_WKERR_EEE_WEC_MASK) /*! @} */ /*! @name SR_XS_PCS_LSTS - SR XS or PCS MMD 10GBASE-X Lane Status */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LNS_MASK (0xFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LNS_SHIFT (0U) /*! LNS - Lane Synchronization */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LNS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LNS_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LNS_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LBA_MASK (0x400U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LBA_SHIFT (10U) /*! LBA - LBA */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LBA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LBA_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LBA_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_TPA_MASK (0x800U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_TPA_SHIFT (11U) /*! TPA - Test Pattern Ability */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_TPA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_TPA_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_TPA_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LA_MASK (0x1000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LA_SHIFT (12U) /*! LA - Receiver Lanes are Aligned * 0b0..RX lanes are not deskewed * 0b1..RX lanes are deskewed */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LA_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_LSTS_LA_MASK) /*! @} */ /*! @name SR_XS_PCS_TCTRL - SR XS or PCS MMD 10GBASE-X Test Control */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TP_MASK (0x3U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TP_SHIFT (0U) /*! TP - Test Pattern Select * 0b00..High Frequency Test Pattern * 0b01..Low Frequency Test Pattern * 0b10..Mixed Frequency Test Pattern * 0b11..Continuous Test Pattern (CJPAT or CRPAT) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TP_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TP_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TPE_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TPE_SHIFT (2U) /*! TPE - Test Pattern Enable Lanes * 0b0..Test pattern disabled * 0b1..Test pattern enabled */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TPE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TPE_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TCTRL_TPE_MASK) /*! @} */ /*! @name SR_XS_PCS_KR_STS1 - SR PCS MMD 10GBASE-R Status 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_BKLK_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_BKLK_SHIFT (0U) /*! RPCS_BKLK - 10GBASE-R Block Lock * 0b0..10GBASE-R is not locked to received blocks * 0b1..10GBASE-R is locked (Block Alignment Success) to received blocks */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_BKLK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_BKLK_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_BKLK_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_HIBER_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_HIBER_SHIFT (1U) /*! RPCS_HIBER - 10GBASE-R PCS High Bit Error Rate * 0b0..10GBASE-R PCS not reporting a high BER * 0b1..10GBASE-R PCS reporting a high BER */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_HIBER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_HIBER_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_RPCS_HIBER_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS31ABL_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS31ABL_SHIFT (2U) /*! PRBS31ABL - PRBS31 Testing Ability * 0b0..DWC_XPCS does not support the PRBS31 pattern testing * 0b1..DWC_XPCS supports the PRBS31 pattern testing */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS31ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS31ABL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS31ABL_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS9ABL_MASK (0x8U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS9ABL_SHIFT (3U) /*! PRBS9ABL - PRBS9 Testing Ability * 0b0..DWC_XPCS does not support the PRBS9 pattern testing * 0b1..DWC_XPCS supports the PRBS9 pattern testing */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS9ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS9ABL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PRBS9ABL_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PLU_MASK (0x1000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PLU_SHIFT (12U) /*! PLU - RPCS Link Up * 0b1..10GBASE-R PCS receive link is up * 0b0..10GBASE-R PCS receive link is down */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PLU(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PLU_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS1_PLU_MASK) /*! @} */ /*! @name SR_XS_PCS_KR_STS2 - SR PCS MMD 10GBASE-R Status 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_ERR_BLK_MASK (0xFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_ERR_BLK_SHIFT (0U) /*! ERR_BLK - Error Block Counter Value (RO, COR Type) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_ERR_BLK(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_ERR_BLK_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_ERR_BLK_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_BER_CNT_MASK (0x3F00U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_BER_CNT_SHIFT (8U) /*! BER_CNT - Bit Error Rate Counter Value (RO, COR Type) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_BER_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_BER_CNT_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_BER_CNT_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_HBER_MASK (0x4000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_HBER_SHIFT (14U) /*! LAT_HBER - Latched High Bit Error Rate (RO, LH Type) * 0b1..10GBASE-R PCS is reporting a high BER * 0b0..10GBASE-R PCS is not reporting a high BER */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_HBER(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_HBER_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_HBER_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_BL_MASK (0x8000U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_BL_SHIFT (15U) /*! LAT_BL - Latched Block Lock (RO, LL Type) * 0b1..10GBASE-R PCS achieved the 66-bit code group alignment * 0b0..10GBASE-R PCS did not achieve the 66-bit code group alignment */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_BL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_BL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_KR_STS2_LAT_BL_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_A0 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A0 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A0_TP_SA0_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A0_TP_SA0_SHIFT (0U) /*! TP_SA0 - Test Pattern Seed A0 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A0_TP_SA0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A0_TP_SA0_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A0_TP_SA0_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_A1 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A1_TP_SA1_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A1_TP_SA1_SHIFT (0U) /*! TP_SA1 - Test Pattern Seed A1 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A1_TP_SA1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A1_TP_SA1_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A1_TP_SA1_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_A2 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A2 Register */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A2_TP_SA2_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A2_TP_SA2_SHIFT (0U) /*! TP_SA2 - Test Pattern Seed A2 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A2_TP_SA2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A2_TP_SA2_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A2_TP_SA2_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_A3 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed A3 Register */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A3_TP_SA3_MASK (0x3FFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A3_TP_SA3_SHIFT (0U) /*! TP_SA3 - Test Pattern Seed A3 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A3_TP_SA3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A3_TP_SA3_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_A3_TP_SA3_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_B0 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B0 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B0_TP_SB0_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B0_TP_SB0_SHIFT (0U) /*! TP_SB0 - Test Pattern Seed B0 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B0_TP_SB0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B0_TP_SB0_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B0_TP_SB0_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_B1 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B1_TP_SB1_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B1_TP_SB1_SHIFT (0U) /*! TP_SB1 - Test Pattern Seed B1 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B1_TP_SB1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B1_TP_SB1_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B1_TP_SB1_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_B2 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B2_TP_SB2_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B2_TP_SB2_SHIFT (0U) /*! TP_SB2 - Test Pattern Seed B2 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B2_TP_SB2(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B2_TP_SB2_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B2_TP_SB2_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_B3 - SR PCS MMD 5G/10GBASE-R Pseudo-Random Test Pattern Seed B3 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B3_TP_SB3_MASK (0x3FFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B3_TP_SB3_SHIFT (0U) /*! TP_SB3 - Test Pattern Seed B3 */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B3_TP_SB3(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B3_TP_SB3_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_B3_TP_SB3_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_CTRL - SR PCS BASE-R Test Pattern Control */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_DP_SEL_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_DP_SEL_SHIFT (0U) /*! DP_SEL - Data Pattern Select for Pseudo-Random Testing * 0b1..All-zero * 0b0..Encoded local-fault pattern (LF) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_DP_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_DP_SEL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_DP_SEL_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TP_SEL_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TP_SEL_SHIFT (1U) /*! TP_SEL - Transmit Test Pattern Select */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TP_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TP_SEL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TP_SEL_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_RTP_EN_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_RTP_EN_SHIFT (2U) /*! RTP_EN - Receive Test Pattern Enable * 0b1..Enables receive pseudo-random test pattern when bit 1 (TP_SEL) is set to 0 * 0b0..Disables receive pseudo-random test pattern */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_RTP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_RTP_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_RTP_EN_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TTP_EN_MASK (0x8U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TTP_EN_SHIFT (3U) /*! TTP_EN - Transmit Pseudo-Random or Square Wave Test Pattern Enable * 0b1..Enables pseudo-random or square wave test pattern depending on bit 1 (TP_SEL) * 0b0..Disables pseudo-random or square wave test patterns */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TTP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TTP_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_TTP_EN_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31T_EN_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31T_EN_SHIFT (4U) /*! PRBS31T_EN - PRBS31 Transmit Pattern Enable * 0b1..Enable PRBS31 test pattern on the Transmit path when bit 3 (TTP_EN) and bit 1 (TP_SEL) of this register is set to 0 * 0b0..Disable PRBS31 test-pattern mode on the Transmit path */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31T_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31T_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31T_EN_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31R_EN_MASK (0x20U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31R_EN_SHIFT (5U) /*! PRBS31R_EN - PRBS31 Receive Test Pattern Enable * 0b1..Enable PRBS31 test pattern checking on the Receive path when bit 2 (RTP_EN) is set to 0 * 0b0..Disable PRBS31 test pattern checking on the Receive path */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31R_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31R_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS31R_EN_MASK) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS9T_EN_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS9T_EN_SHIFT (6U) /*! PRBS9T_EN - PRBS9 Transmit Test Pattern Enable * 0b1..Enable PRBS9 test pattern on the Transmit path when bit 3 (TTP_EN), bit 1 (TP_SEL), and bit 4 (PRBS31T_EN) are set to 0 * 0b0..Disable PRBS9 test-pattern mode on the Transmit path */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS9T_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS9T_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_CTRL_PRBS9T_EN_MASK) /*! @} */ /*! @name SR_XS_PCS_TP_ERRCTR - SR PCS BASE-R Test Pattern Error Counter */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_ERRCTR_TP_ERR_CNT_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_ERRCTR_TP_ERR_CNT_SHIFT (0U) /*! TP_ERR_CNT - Test Pattern Error Counter (RO, COR Type) */ #define ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_ERRCTR_TP_ERR_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_ERRCTR_TP_ERR_CNT_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_XS_PCS_TP_ERRCTR_TP_ERR_CNT_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_PCS_ABL - SR PCS MMD Time Sync Capability */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_RX_DLY_ABL_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_RX_DLY_ABL_SHIFT (0U) /*! PCS_RX_DLY_ABL - PCS Receive Path Data Delay Information Available */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_RX_DLY_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_RX_DLY_ABL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_RX_DLY_ABL_MASK) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_TX_DLY_ABL_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_TX_DLY_ABL_SHIFT (1U) /*! PCS_TX_DLY_ABL - PCS Transmit Path Data Delay Information Available */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_TX_DLY_ABL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_TX_DLY_ABL_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_PCS_ABL_PCS_TX_DLY_ABL_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_TX_MAX_DLY_LWR - SR PCS MMD Time Sync TX Max Delay Lower */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_LWR_PCS_TX_MAX_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_LWR_PCS_TX_MAX_DLY_LWR_SHIFT (0U) /*! PCS_TX_MAX_DLY_LWR - PCS Transmit Max Delay Lower */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_LWR_PCS_TX_MAX_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_LWR_PCS_TX_MAX_DLY_LWR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_LWR_PCS_TX_MAX_DLY_LWR_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_TX_MAX_DLY_UPR - SR PCS MMD Time Sync TX Max Delay Upper */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_UPR_PCS_TX_MAX_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_UPR_PCS_TX_MAX_DLY_UPR_SHIFT (0U) /*! PCS_TX_MAX_DLY_UPR - PCS Transmit Max Delay Upper */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_UPR_PCS_TX_MAX_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_UPR_PCS_TX_MAX_DLY_UPR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MAX_DLY_UPR_PCS_TX_MAX_DLY_UPR_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_TX_MIN_DLY_LWR - SR PCS MMD Time Sync TX Min Delay Lower */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_LWR_PCS_TX_MIN_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_LWR_PCS_TX_MIN_DLY_LWR_SHIFT (0U) /*! PCS_TX_MIN_DLY_LWR - PCS Transmit Min Delay Lower */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_LWR_PCS_TX_MIN_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_LWR_PCS_TX_MIN_DLY_LWR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_LWR_PCS_TX_MIN_DLY_LWR_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_TX_MIN_DLY_UPR - SR PCS MMD Time Sync TX Min Delay Upper */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_UPR_PCS_TX_MIN_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_UPR_PCS_TX_MIN_DLY_UPR_SHIFT (0U) /*! PCS_TX_MIN_DLY_UPR - PCS Transmit Min Delay Upper */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_UPR_PCS_TX_MIN_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_UPR_PCS_TX_MIN_DLY_UPR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_TX_MIN_DLY_UPR_PCS_TX_MIN_DLY_UPR_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_RX_MAX_DLY_LWR - SR PCS MMD Time Sync RX Max Delay Lower */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_LWR_PCS_RX_MAX_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_LWR_PCS_RX_MAX_DLY_LWR_SHIFT (0U) /*! PCS_RX_MAX_DLY_LWR - PCS Receive Max Delay Lower */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_LWR_PCS_RX_MAX_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_LWR_PCS_RX_MAX_DLY_LWR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_LWR_PCS_RX_MAX_DLY_LWR_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_RX_MAX_DLY_UPR - SR PCS MMD Time Sync RX Max Delay Upper */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_UPR_PCS_RX_MAX_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_UPR_PCS_RX_MAX_DLY_UPR_SHIFT (0U) /*! PCS_RX_MAX_DLY_UPR - PCS Receive Max Delay Upper */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_UPR_PCS_RX_MAX_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_UPR_PCS_RX_MAX_DLY_UPR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MAX_DLY_UPR_PCS_RX_MAX_DLY_UPR_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_RX_MIN_DLY_LWR - SR PCS MMD Time Sync RX Min Delay Lower */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_LWR_PCS_RX_MIN_DLY_LWR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_LWR_PCS_RX_MIN_DLY_LWR_SHIFT (0U) /*! PCS_RX_MIN_DLY_LWR - PCS Receive Min Delay Lower */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_LWR_PCS_RX_MIN_DLY_LWR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_LWR_PCS_RX_MIN_DLY_LWR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_LWR_PCS_RX_MIN_DLY_LWR_MASK) /*! @} */ /*! @name SR_PCS_TIME_SYNC_RX_MIN_DLY_UPR - SR PCS MMD Time Sync RX Min Delay Upper */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_UPR_PCS_RX_MIN_DLY_UPR_MASK (0xFFFFU) #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_UPR_PCS_RX_MIN_DLY_UPR_SHIFT (0U) /*! PCS_RX_MIN_DLY_UPR - PCS Receive Min Delay Upper */ #define ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_UPR_PCS_RX_MIN_DLY_UPR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_UPR_PCS_RX_MIN_DLY_UPR_SHIFT)) & ENET_PHY_XS_PCS_MMD_SR_PCS_TIME_SYNC_RX_MIN_DLY_UPR_PCS_RX_MIN_DLY_UPR_MASK) /*! @} */ /*! @name VR_XS_PCS_DIG_CTRL1 - VR XS or PCS MMD Digital Control 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DSKBYP_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DSKBYP_SHIFT (0U) /*! DSKBYP - DSKBYP */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DSKBYP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DSKBYP_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DSKBYP_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_SHIFT (1U) /*! BYP_PWRUP - Bypass Power-Up Sequence */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_BYP_PWRUP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_BYP_PWRUP_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_SHIFT (2U) /*! EN_2_5G_MODE - Enable 2.5G GMII Mode */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_2_5G_MODE_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DTXLANED_0_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DTXLANED_0_SHIFT (4U) /*! DTXLANED_0 - TX Disable on Lane 0 */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DTXLANED_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DTXLANED_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_DTXLANED_0_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_INIT_MASK (0x100U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_INIT_SHIFT (8U) /*! INIT - Datapath Initialization Control */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_INIT_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_INIT_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN_MASK (0x200U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN_SHIFT (9U) /*! USXG_EN - USXGMII Mode Enable */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK (0x400U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_SHIFT (10U) /*! USRA_RST - USXGMII Rate Adaptor Reset (Port 0) */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_PWRSV_MASK (0x800U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_PWRSV_SHIFT (11U) /*! PWRSV - Power Save * 0b0..Normal operation * 0b1..DWC_XPCS and the PHY enter the power-save mode */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_PWRSV(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_PWRSV_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_PWRSV_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_MASK (0x2000U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_SHIFT (13U) /*! EN_VSMMD1 - Enable Vendor-Specific MMD1 */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_VSMMD1(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_EN_VSMMD1_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_R2TLBE_MASK (0x4000U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_R2TLBE_SHIFT (14U) /*! R2TLBE - RX to TX Loopback Enable * 0b0..Loopback path is disabled * 0b1..Loopback path is enabled */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_R2TLBE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_R2TLBE_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_R2TLBE_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK (0x8000U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_SHIFT (15U) /*! VR_RST - Vendor-Specific Soft Reset (RW, SC Type) */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK) /*! @} */ /*! @name VR_XS_PCS_DIG_CTRL2 - VR XS or PCS MMD Digital Control 2 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_RX_POL_INV_0_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_RX_POL_INV_0_SHIFT (0U) /*! RX_POL_INV_0 - RX Polarity Invert on Lane 0 */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_RX_POL_INV_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_RX_POL_INV_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_RX_POL_INV_0_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_TX_POL_INV_0_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_TX_POL_INV_0_SHIFT (4U) /*! TX_POL_INV_0 - TX Polarity Invert on Lane 0 */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_TX_POL_INV_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_TX_POL_INV_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL2_TX_POL_INV_0_MASK) /*! @} */ /*! @name VR_XS_PCS_DIG_ERRCNT_SEL - VR XS or PCS MMD Digital Error Count Select */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_COR_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_COR_SHIFT (0U) /*! COR - Clear on Read * 0b0..Normal operation * 0b1..Clear any error counter that is read */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_COR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_COR_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_COR_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_INV_EC_EN_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_INV_EC_EN_SHIFT (4U) /*! INV_EC_EN - Invalid Code Group Error Counter Enable * 0b0..The counting of errors is disabled * 0b1..The counting of errors is enabled */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_INV_EC_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_INV_EC_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_ERRCNT_SEL_INV_EC_EN_MASK) /*! @} */ /*! @name VR_XS_PCS_XAUI_CTRL - VR XS or PCS MMD XAUI Mode Control */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_XAUI_MODE_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_XAUI_MODE_SHIFT (0U) /*! XAUI_MODE - Reserved */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_XAUI_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_XAUI_MODE_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_XAUI_MODE_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_MRVL_RXAUI_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_MRVL_RXAUI_SHIFT (1U) /*! MRVL_RXAUI - Reserved */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_MRVL_RXAUI(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_MRVL_RXAUI_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_XAUI_CTRL_MRVL_RXAUI_MASK) /*! @} */ /*! @name VR_XS_PCS_DEBUG_CTRL - VR XS or PCS MMD Debug Control */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RESTAR_SYNC_0_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RESTAR_SYNC_0_SHIFT (0U) /*! RESTAR_SYNC_0 - Restart Synchronization on Lane 0 */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RESTAR_SYNC_0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RESTAR_SYNC_0_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RESTAR_SYNC_0_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET_SHIFT (4U) /*! SUPRESS_LOS_DET - Suppress Loss of Signal Detection */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_EEE_LOS_DET_MASK (0x20U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_EEE_LOS_DET_SHIFT (5U) /*! SUPRESS_EEE_LOS_DET - Suppress EEE Loss of Signal Detection */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_EEE_LOS_DET(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_EEE_LOS_DET_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_EEE_LOS_DET_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL_SHIFT (6U) /*! RX_DT_EN_CTL - RX Data Enable Control */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_SYNC_CTL_MASK (0x80U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_SYNC_CTL_SHIFT (7U) /*! RX_SYNC_CTL - Receive Synchronization Control */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_SYNC_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_SYNC_CTL_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_SYNC_CTL_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL_MASK (0x100U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL_SHIFT (8U) /*! TX_PMBL_CTL - Transmit Preamble Control */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_PMBL_CTL_MASK (0x200U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_PMBL_CTL_SHIFT (9U) /*! RX_PMBL_CTL - Receive Preamble Control */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_PMBL_CTL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_PMBL_CTL_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_PMBL_CTL_MASK) /*! @} */ /*! @name VR_XS_PCS_EEE_MCTRL0 - VR XS or PCS MMD EEE Mode Control */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LTX_EN_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LTX_EN_SHIFT (0U) /*! LTX_EN - LPI TX Enable * 0b0..Disables the support for Energy Efficient Ethernet in DWC_XPCS Transmit path * 0b1..Enables the Energy Efficient Ethernet support in DWC_XPCS Transmit path */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LTX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LTX_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LTX_EN_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LRX_EN_MASK (0x2U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LRX_EN_SHIFT (1U) /*! LRX_EN - LPI RX Enable * 0b0..Disables the support for Energy Efficient Ethernet in DWC_XPCS Receive path * 0b1..Enables the Energy Efficient Ethernet support in DWC_XPCS Receive path */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LRX_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LRX_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_LRX_EN_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_QUIET_EN_MASK (0x4U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_QUIET_EN_SHIFT (2U) /*! TX_QUIET_EN - TX Quiet Enable * 0b0..The xpcs_lpitx_quiet_o output is not set to 1 * 0b1..The xpcs_lpitx_quiet_o output is set to 1 when the EEE transmit controller reaches the Quiet state */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_QUIET_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_QUIET_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_QUIET_EN_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_QUIET_EN_MASK (0x8U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_QUIET_EN_SHIFT (3U) /*! RX_QUIET_EN - RX Quiet Enable * 0b0..The xpcs_lpirx_quiet_o output is not set to 1 * 0b1..The xpcs_lpirx_quiet_o output is set to 1 when the EEE receive controller reaches the Quiet state */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_QUIET_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_QUIET_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_QUIET_EN_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_EN_CTRL_MASK (0x10U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_EN_CTRL_SHIFT (4U) /*! TX_EN_CTRL - TX Control Enable * 0b0..The xgxs_tx{lane}_en_o or xpcs_tx_en_o{lane} signal is not de-asserted when the EEE transmit controller reaches the Quiet state * 0b1..The xgxs_tx{lane}_en_o or xpcs_tx_en_o{lane} signal is de-asserted when the EEE transmit controller reaches the Quiet state */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_EN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_EN_CTRL_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_TX_EN_CTRL_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_EEE_SLR_BYP_MASK (0x20U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_EEE_SLR_BYP_SHIFT (5U) /*! EEE_SLR_BYP - Scrambler Bypass * 0b0..The scrambler is not bypassed * 0b1..The scrambler is bypassed in PCS-R during EEE TX mode */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_EEE_SLR_BYP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_EEE_SLR_BYP_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_EEE_SLR_BYP_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_SIGN_BIT_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_SIGN_BIT_SHIFT (6U) /*! SIGN_BIT - Effective 100 ns Tic Value */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_SIGN_BIT(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_SIGN_BIT_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_SIGN_BIT_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_EN_CTRL_MASK (0x80U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_EN_CTRL_SHIFT (7U) /*! RX_EN_CTRL - RX Control Enable * 0b0..The xpcs_rx_en_o signal is not de-asserted when the EEE transmit controller reaches the Quiet state * 0b1..The xpcs_rx_en_o signal is de-asserted when the EEE receive controller reaches the Quiet state */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_EN_CTRL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_EN_CTRL_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_RX_EN_CTRL_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_MULT_FACT_100NS_MASK (0xF00U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_MULT_FACT_100NS_SHIFT (8U) /*! MULT_FACT_100NS - 100 ns Clock Tic Multiplying Factor */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_MULT_FACT_100NS(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_MULT_FACT_100NS_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_MULT_FACT_100NS_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_CLKSTOP_MASK (0xF000U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_CLKSTOP_SHIFT (12U) /*! CLKSTOP - Clock Stop */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_CLKSTOP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_CLKSTOP_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL0_CLKSTOP_MASK) /*! @} */ /*! @name VR_XS_PCS_KR_CTRL - VR PCS 10GBASE-R Control */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_VR_TP_EN_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_VR_TP_EN_SHIFT (0U) /*! VR_TP_EN - PCS-R Vendor-Specific Test Pattern Enable */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_VR_TP_EN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_VR_TP_EN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_VR_TP_EN_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PR_DATA_MASK (0xEU) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PR_DATA_SHIFT (1U) /*! PR_DATA - Pseudo-Random Test Pattern Data * 0b000..Data = All zero (0x00); IEEE specified * 0b001..Data = XGMII local fault (encoded version); IEEE specified * 0b010..Data = All five (0x55); HFTP * 0b011..Data = All A (0xAA); HFTP * 0b100..Data = All ones (0xFF); LFTP * 0b101..Data = All three (0x33); MFTP * 0b110..Data = All C (0xCC); MFTP * 0b111..Reserved */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PR_DATA(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PR_DATA_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PR_DATA_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_NVAL_SEL_MASK (0x70U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_NVAL_SEL_SHIFT (4U) /*! NVAL_SEL - Square Wave Control * 0b000..4 * 0b001..5 * 0b010..6 * 0b011..7 * 0b100..8 * 0b101..9 * 0b110..10 * 0b111..11 */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_NVAL_SEL(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_NVAL_SEL_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_NVAL_SEL_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PRBS9RXEN_MASK (0x80U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PRBS9RXEN_SHIFT (7U) /*! PRBS9RXEN - Enable PRBS9 Testing in Receive Path */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PRBS9RXEN(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PRBS9RXEN_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_PRBS9RXEN_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_SCR_MASK (0x100U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_SCR_SHIFT (8U) /*! DIS_SCR - Disable Scrambler */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_SCR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_SCR_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_SCR_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_DESCR_MASK (0x200U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_DESCR_SHIFT (9U) /*! DIS_DESCR - Disable Descrambler */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_DESCR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_DESCR_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_DIS_DESCR_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE_MASK (0x1C00U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE_SHIFT (10U) /*! USXG_MODE - USXGMII Mode Select * 0b000..10G-SXGMII * 0b001..5G-SXGMII * 0b010..2.5G-SXGMII * 0b011..10G-DXGMII * 0b100..5G-DXGMII * 0b101..10G-QXGMII * 0b110, 0b111..Reserved */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_2PT5G_GMII_MASK (0x2000U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_2PT5G_GMII_SHIFT (13U) /*! USXG_2PT5G_GMII - MAC/PCS Interface Select in USXGMII 2.5G Mode * 0b0..Use XGMII interface * 0b1..Use GMII interface */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_2PT5G_GMII(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_2PT5G_GMII_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_2PT5G_GMII_MASK) /*! @} */ /*! @name VR_XS_PCS_EEE_TXTIMER - VR XS or PCS MMD EEE TX Timer */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TSL_RES_MASK (0x3FU) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TSL_RES_SHIFT (0U) /*! TSL_RES - TSL Resolution */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TSL_RES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TSL_RES_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TSL_RES_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_T1U_RES_MASK (0xC0U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_T1U_RES_SHIFT (6U) /*! T1U_RES - T1u Resolution */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_T1U_RES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_T1U_RES_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_T1U_RES_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TWL_RES_MASK (0x1F00U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TWL_RES_SHIFT (8U) /*! TWL_RES - TWL Resolution */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TWL_RES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TWL_RES_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_TXTIMER_TWL_RES_MASK) /*! @} */ /*! @name VR_XS_PCS_EEE_RXTIMER - VR XS or PCS MMD EEE RX Timer */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_RES_100U_MASK (0xFFU) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_RES_100U_SHIFT (0U) /*! RES_100U - 100 us Resolution */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_RES_100U(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_RES_100U_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_RES_100U_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_TWR_RES_MASK (0x3F00U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_TWR_RES_SHIFT (8U) /*! TWR_RES - TWR Resolution */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_TWR_RES(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_TWR_RES_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_RXTIMER_TWR_RES_MASK) /*! @} */ /*! @name VR_XS_PCS_EEE_MCTRL1 - VR XS or PCS MMD EEE Mode Control 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL1_TRN_LPI_MASK (0x1U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL1_TRN_LPI_SHIFT (0U) /*! TRN_LPI - Transparent TX LPI Mode Enable */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL1_TRN_LPI(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL1_TRN_LPI_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_EEE_MCTRL1_TRN_LPI_MASK) /*! @} */ /*! @name VR_XS_PCS_DIG_STS - VR XS or PCS MMD Digital Status */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_PSEQ_STATE_MASK (0x1CU) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_PSEQ_STATE_SHIFT (2U) /*! PSEQ_STATE - Power Up Sequence State * 0b000..Wait for MPLL ON (for Synopsys multi-protocol 6G PHY), Wait for ACK High 0 (for Synopsys multi-protocol 12G/16G PHY) * 0b001..Wait for TX up (6G PHY), Wait for ACK Low 0 (12G/16G/ PHY) * 0b010..Wait for RX up (6G PHY), Wait for ACK High 1 (12G/16G PHY) * 0b011..TX/RX Stable (Power_Good state) (6G PHY), Wait for ACK Low 1 (12G/16G PHY) * 0b100..TX/RX Stable (Power_Good state) * 0b101..Wait for RX down (MPLL still ON) (6G PHY), Power Save state (12G/16G PHY) * 0b110..MPLL OFF (6G PHY), Power Down state (12G/16G PHY) */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_PSEQ_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_PSEQ_STATE_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_PSEQ_STATE_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_UNDF_MASK (0x20U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_UNDF_SHIFT (5U) /*! RXFIFO_UNDF - RX FIFO Underflow (RO, LH Type) * 0b0..Normal operation * 0b1..FIFO underflow */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_UNDF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_UNDF_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_UNDF_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_OVF_MASK (0x40U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_OVF_SHIFT (6U) /*! RXFIFO_OVF - RX FIFO Overflow (RO, LH Type) * 0b0..Normal operation * 0b1..FIFO overflow */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_OVF(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_OVF_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_RXFIFO_OVF_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_SOP_MASK (0x80U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_SOP_SHIFT (7U) /*! INV_XGM_SOP - Invalid XGMII Start Character (RO, LH Type) * 0b0..Normal operation * 0b1..Invalid SOP character */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_SOP(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_SOP_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_SOP_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_T_MASK (0x100U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_T_SHIFT (8U) /*! INV_XGM_T - Invalid XGMII T Character (RO, LH Type) * 0b0..Normal operation * 0b1..Invalid Terminate character */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_T(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_T_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_T_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_CHAR_MASK (0x200U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_CHAR_SHIFT (9U) /*! INV_XGM_CHAR - Invalid XGMII Character (RO, LH Type) * 0b0..No Invalid XGMII character * 0b1..Invalid character */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_CHAR(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_CHAR_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_INV_XGM_CHAR_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LRX_STATE_MASK (0x1C00U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LRX_STATE_SHIFT (10U) /*! LRX_STATE - LPI Receive State * 0b000..LRX_ACTIVE * 0b001..LRX_SLEEP * 0b010..LRX_QUIET * 0b011..LRX_WAKE * 0b100..LRX_WTF * 0b101..LRX_LINK_FAIL * 0b110..LRX_LPI_K (present only in configurations with 1G speed) */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LRX_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LRX_STATE_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LRX_STATE_MASK) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LTX_STATE_MASK (0xE000U) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LTX_STATE_SHIFT (13U) /*! LTX_STATE - LPI Transmit State * 0b000..LTX_ACTIVE * 0b001..LTX_SLEEP * 0b010..LTX_QUIET * 0b011..LTX_REF_WAKE * 0b100..LTX_ALERT (valid only if PCS-R is present) * 0b101..LTX_SCR_BYP (valid only if PCS-R is present) */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LTX_STATE(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LTX_STATE_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_STS_LTX_STATE_MASK) /*! @} */ /*! @name VR_XS_PCS_ICG_ERRCNT1 - VR XS or PCS MMD Invalid Code Group Error Count 1 */ /*! @{ */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_ICG_ERRCNT1_EC0_MASK (0xFFU) #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_ICG_ERRCNT1_EC0_SHIFT (0U) /*! EC0 - Error Count 0: Invalid Code Group Count on Lane 0 (RO, COR Type) */ #define ENET_PHY_XS_PCS_MMD_VR_XS_PCS_ICG_ERRCNT1_EC0(x) (((uint16_t)(((uint16_t)(x)) << ENET_PHY_XS_PCS_MMD_VR_XS_PCS_ICG_ERRCNT1_EC0_SHIFT)) & ENET_PHY_XS_PCS_MMD_VR_XS_PCS_ICG_ERRCNT1_EC0_MASK) /*! @} */ /*! * @} */ /* end of group ENET_PHY_XS_PCS_MMD_Register_Masks */ /* ENET_PHY_XS_PCS_MMD - Peripheral instance base addresses */ /** Peripheral ENET_PHY_XS_PCS_MMD base address */ #define ENET_PHY_XS_PCS_MMD_BASE (0x60000u) /** Peripheral ENET_PHY_XS_PCS_MMD base pointer */ #define ENET_PHY_XS_PCS_MMD ((ENET_PHY_XS_PCS_MMD_Type *)ENET_PHY_XS_PCS_MMD_BASE) /** Array initializer of ENET_PHY_XS_PCS_MMD peripheral base addresses */ #define ENET_PHY_XS_PCS_MMD_BASE_ADDRS { ENET_PHY_XS_PCS_MMD_BASE } /** Array initializer of ENET_PHY_XS_PCS_MMD peripheral base pointers */ #define ENET_PHY_XS_PCS_MMD_BASE_PTRS { ENET_PHY_XS_PCS_MMD } /*! * @} */ /* end of group ENET_PHY_XS_PCS_MMD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer * @{ */ /** FLEXIO - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ __I uint32_t PIN; /**< Pin State, offset: 0xC */ __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ uint8_t RESERVED_2[4]; __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ uint8_t RESERVED_3[4]; __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ uint8_t RESERVED_4[4]; __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ uint8_t RESERVED_5[8]; __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_6[96]; __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_7[224]; __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_8[96]; __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_9[96]; __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_10[96]; __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ uint8_t RESERVED_11[96]; __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_12[96]; __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_13[96]; __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ uint8_t RESERVED_14[352]; __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ uint8_t RESERVED_15[96]; __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ uint8_t RESERVED_16[96]; __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ uint8_t RESERVED_17[96]; __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ uint8_t RESERVED_18[96]; __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ uint8_t RESERVED_19[96]; __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ } FLEXIO_Type; /* ---------------------------------------------------------------------------- -- FLEXIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard features implemented * 0b0000000000000001..State, logic, and parallel modes supported * 0b0000000000000010..Pin control registers supported * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) #define FLEXIO_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) /*! SHIFTER - Shifter Number */ #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) #define FLEXIO_PARAM_TIMER_SHIFT (8U) /*! TIMER - Timer Number */ #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) #define FLEXIO_PARAM_PIN_SHIFT (16U) /*! PIN - Pin Number */ #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) /*! TRIGGER - Trigger Number */ #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) /*! @} */ /*! @name CTRL - FLEXIO Control */ /*! @{ */ #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) /*! FLEXEN - FLEXIO Enable * 0b0..Disable * 0b1..Enable */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) /*! SWRST - Software Reset * 0b0..Disabled * 0b1..Enabled */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) /*! FASTACC - Fast Access * 0b0..Normal * 0b1..Fast */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) /*! DBGE - Debug Enable * 0b0..Disable * 0b1..Enable */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) /*! DOZEN - Doze Enable * 0b0..Enable * 0b1..Disable */ #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) /*! @} */ /*! @name PIN - Pin State */ /*! @{ */ #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) /*! PDI - Pin Data Input */ #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /*! @} */ /*! @name SHIFTSTAT - Shifter Status */ /*! @{ */ #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) /*! SSF - Shifter Status Flag * 0b00000000..Clear * 0b00000001..Set * 0b00000000..No effect * 0b00000001..Clear the flag */ #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) /*! @} */ /*! @name SHIFTERR - Shifter Error */ /*! @{ */ #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) /*! SEF - Shifter Error Flag * 0b00000000..Clear * 0b00000001..Set * 0b00000000..No effect * 0b00000001..Clear the flag */ #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) /*! @} */ /*! @name TIMSTAT - Timer Status Flag */ /*! @{ */ #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) /*! TSF - Timer Status Flag * 0b00000000..Clear * 0b00000001..Set * 0b00000000..No effect * 0b00000001..Clear the flag */ #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) /*! @} */ /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) /*! SSIE - Shifter Status Interrupt Enable */ #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) /*! @} */ /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ /*! @{ */ #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) /*! SEIE - Shifter Error Interrupt Enable */ #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) /*! @} */ /*! @name TIMIEN - Timer Interrupt Enable */ /*! @{ */ #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) /*! TEIE - Timer Status Interrupt Enable */ #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) /*! @} */ /*! @name SHIFTSDEN - Shifter Status DMA Enable */ /*! @{ */ #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) /*! SSDE - Shifter Status DMA Enable */ #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) /*! @} */ /*! @name TIMERSDEN - Timer Status DMA Enable */ /*! @{ */ #define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) #define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) /*! TSDE - Timer Status DMA Enable */ #define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) /*! @} */ /*! @name SHIFTSTATE - Shifter State */ /*! @{ */ #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) /*! STATE - Current State Pointer */ #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) /*! @} */ /*! @name TRGSTAT - Trigger Status */ /*! @{ */ #define FLEXIO_TRGSTAT_ETSF_MASK (0xFU) #define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) /*! ETSF - External Trigger Status Flag * 0b0000..Clear * 0b0001..Set * 0b0000..No effect * 0b0001..Clear the flag */ #define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) /*! @} */ /*! @name TRIGIEN - External Trigger Interrupt Enable */ /*! @{ */ #define FLEXIO_TRIGIEN_TRIE_MASK (0xFU) #define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) /*! TRIE - External Trigger Interrupt Enable */ #define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) /*! @} */ /*! @name PINSTAT - Pin Status */ /*! @{ */ #define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) #define FLEXIO_PINSTAT_PSF_SHIFT (0U) /*! PSF - Pin Status Flag * 0b00000000000000000000000000000000..Clear * 0b00000000000000000000000000000001..Set * 0b00000000000000000000000000000000..No effect * 0b00000000000000000000000000000001..Clear the flag */ #define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) /*! @} */ /*! @name PINIEN - Pin Interrupt Enable */ /*! @{ */ #define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) #define FLEXIO_PINIEN_PSIE_SHIFT (0U) /*! PSIE - Pin Status Interrupt Enable */ #define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) /*! @} */ /*! @name PINREN - Pin Rising Edge Enable */ /*! @{ */ #define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) #define FLEXIO_PINREN_PRE_SHIFT (0U) /*! PRE - Pin Rising Edge */ #define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) /*! @} */ /*! @name PINFEN - Pin Falling Edge Enable */ /*! @{ */ #define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) #define FLEXIO_PINFEN_PFE_SHIFT (0U) /*! PFE - Pin Falling Edge */ #define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) /*! @} */ /*! @name PINOUTD - Pin Output Data */ /*! @{ */ #define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTD_OUTD_SHIFT (0U) /*! OUTD - Output Data */ #define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) /*! @} */ /*! @name PINOUTE - Pin Output Enable */ /*! @{ */ #define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTE_OUTE_SHIFT (0U) /*! OUTE - Output Enable */ #define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) /*! @} */ /*! @name PINOUTDIS - Pin Output Disable */ /*! @{ */ #define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) /*! OUTDIS - Output Disable */ #define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) /*! @} */ /*! @name PINOUTCLR - Pin Output Clear */ /*! @{ */ #define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) /*! OUTCLR - Output Clear */ #define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) /*! @} */ /*! @name PINOUTSET - Pin Output Set */ /*! @{ */ #define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) /*! OUTSET - Output Set */ #define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) /*! @} */ /*! @name PINOUTTOG - Pin Output Toggle */ /*! @{ */ #define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) #define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) /*! OUTTOG - Output Toggle */ #define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) /*! @} */ /*! @name SHIFTCTL - Shifter Control */ /*! @{ */ #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) /*! SMOD - Shifter Mode * 0b000..Disable * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer * 0b011..Reserved * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents * 0b110..State mode; SHIFTBUF contents store programmable state attributes * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) /*! PINPOL - Shifter Pin Polarity * 0b0..Active high * 0b1..Active low */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) /*! PINSEL - Shifter Pin Select */ #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) /*! PINCFG - Shifter Pin Configuration * 0b00..Shifter pin output disabled * 0b01..Shifter pin open-drain or bidirectional output enable * 0b10..Shifter pin bidirectional output data * 0b11..Shifter pin output */ #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) /*! TIMPOL - Timer Polarity * 0b0..Positive edge * 0b1..Negative edge */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) /*! TIMSEL - Timer Select */ #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCTL */ #define FLEXIO_SHIFTCTL_COUNT (8U) /*! @name SHIFTCFG - Shifter Configuration */ /*! @{ */ #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) /*! SSTART - Shifter Start * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, * Receiver and Match Store modes set error flag * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, * Receiver and Match Store modes set error flag */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) /*! SSTOP - Shifter Stop * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, * Receiver and Match Store modes store receive data on the configured shift edge * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the * configured shift edge) * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the * configured shift edge) */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) /*! INSRC - Input Source * 0b0..Pin * 0b1..Shifter n+1 output */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) #define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) #define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) /*! LATST - Late Store * 0b0..Store the pre-shift register state * 0b1..Store the post-shift register state */ #define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) #define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) #define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) /*! SSIZE - Shifter Size * 0b0..32-bit * 0b1..24-bit */ #define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) /*! PWIDTH - Parallel Width */ #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /*! @} */ /* The count of FLEXIO_SHIFTCFG */ #define FLEXIO_SHIFTCFG_COUNT (8U) /*! @name SHIFTBUF - Shifter Buffer */ /*! @{ */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) /*! SHIFTBUF - Shift Buffer */ #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUF */ #define FLEXIO_SHIFTBUF_COUNT (8U) /*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) /*! SHIFTBUFBIS - Shift Buffer */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBIS */ #define FLEXIO_SHIFTBUFBIS_COUNT (8U) /*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) /*! SHIFTBUFBYS - Shift Buffer */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBYS */ #define FLEXIO_SHIFTBUFBYS_COUNT (8U) /*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) /*! SHIFTBUFBBS - Shift Buffer */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFBBS */ #define FLEXIO_SHIFTBUFBBS_COUNT (8U) /*! @name TIMCTL - Timer Control */ /*! @{ */ #define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) /*! TIMOD - Timer Mode * 0b000..Timer disabled * 0b001..Dual 8-bit counters baud mode * 0b010..Dual 8-bit counters PWM high mode * 0b011..Single 16-bit counter mode * 0b100..Single 16-bit counter disable mode * 0b101..Dual 8-bit counters word mode * 0b110..Dual 8-bit counters PWM low mode * 0b111..Single 16-bit input capture mode */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) #define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) /*! ONETIM - Timer One Time Operation * 0b0..Generate the timer enable event as normal * 0b1..Block the timer enable event unless the timer status flag is clear */ #define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) #define FLEXIO_TIMCTL_PININS_MASK (0x40U) #define FLEXIO_TIMCTL_PININS_SHIFT (6U) /*! PININS - Timer Pin Input Select * 0b0..PINSEL selects timer pin input and output * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL */ #define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) /*! PINPOL - Timer Pin Polarity * 0b0..Active high * 0b1..Active low */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) /*! PINSEL - Timer Pin Select */ #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) /*! PINCFG - Timer Pin Configuration * 0b00..Timer pin output disabled * 0b01..Timer pin open-drain or bidirectional output enable * 0b10..Timer pin bidirectional output data * 0b11..Timer pin output */ #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) /*! TRGSRC - Trigger Source * 0b0..External * 0b1..Internal */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) /*! TRGPOL - Trigger Polarity * 0b0..Active high * 0b1..Active low */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select */ #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /*! @} */ /* The count of FLEXIO_TIMCTL */ #define FLEXIO_TIMCTL_COUNT (8U) /*! @name TIMCFG - Timer Configuration */ /*! @{ */ #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) /*! TSTART - Timer Start * 0b0..Disabled * 0b1..Enabled */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) /*! TSTOP - Timer Stop * 0b00..Disabled * 0b01..Enabled on timer compare * 0b10..Enabled on timer disable * 0b11..Enabled on timer compare and timer disable */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) /*! TIMENA - Timer Enable * 0b000..Timer always enabled * 0b001..Timer enabled on timer n-1 enable * 0b010..Timer enabled on trigger high * 0b011..Timer enabled on trigger high and pin high * 0b100..Timer enabled on pin rising edge * 0b101..Timer enabled on pin rising edge and trigger high * 0b110..Timer enabled on trigger rising edge * 0b111..Timer enabled on trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) /*! TIMDIS - Timer Disable * 0b000..Timer never disabled * 0b001..Timer disabled on timer n-1 disable * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low * 0b100..Timer disabled on pin rising or falling edge * 0b101..Timer disabled on pin rising or falling edge provided trigger is high * 0b110..Timer disabled on trigger falling edge * 0b111..Reserved */ #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) /*! TIMRST - Timer Reset * 0b000..Never reset timer * 0b001..Timer reset on timer output high. * 0b010..Timer reset on timer pin equal to timer output * 0b011..Timer reset on timer trigger equal to timer output * 0b100..Timer reset on timer pin rising edge * 0b101..Reserved * 0b110..Timer reset on trigger rising edge * 0b111..Timer reset on trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) #define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) /*! TIMDEC - Timer Decrement * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) /*! TIMOUT - Timer Output * 0b00..Logic one when enabled; not affected by timer reset * 0b01..Logic zero when enabled; not affected by timer reset * 0b10..Logic one when enabled and on timer reset * 0b11..Logic zero when enabled and on timer reset */ #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) /*! @} */ /* The count of FLEXIO_TIMCFG */ #define FLEXIO_TIMCFG_COUNT (8U) /*! @name TIMCMP - Timer Compare */ /*! @{ */ #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) /*! CMP - Timer Compare Value */ #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) /*! @} */ /* The count of FLEXIO_TIMCMP */ #define FLEXIO_TIMCMP_COUNT (8U) /*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) /*! SHIFTBUFNBS - Shift Buffer */ #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFNBS */ #define FLEXIO_SHIFTBUFNBS_COUNT (8U) /*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) /*! SHIFTBUFHWS - Shift Buffer */ #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFHWS */ #define FLEXIO_SHIFTBUFHWS_COUNT (8U) /*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) /*! SHIFTBUFNIS - Shift Buffer */ #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFNIS */ #define FLEXIO_SHIFTBUFNIS_COUNT (8U) /*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) /*! SHIFTBUFOES - Shift Buffer */ #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFOES */ #define FLEXIO_SHIFTBUFOES_COUNT (8U) /*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) /*! SHIFTBUFEOS - Shift Buffer */ #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFEOS */ #define FLEXIO_SHIFTBUFEOS_COUNT (8U) /*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ /*! @{ */ #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) /*! SHIFTBUFHBS - Shift Buffer */ #define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) /*! @} */ /* The count of FLEXIO_SHIFTBUFHBS */ #define FLEXIO_SHIFTBUFHBS_COUNT (8U) /*! * @} */ /* end of group FLEXIO_Register_Masks */ /* FLEXIO - Peripheral instance base addresses */ /** Peripheral FLEXIO1 base address */ #define FLEXIO1_BASE (0x425C0000u) /** Peripheral FLEXIO1 base pointer */ #define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) /** Peripheral FLEXIO2 base address */ #define FLEXIO2_BASE (0x425D0000u) /** Peripheral FLEXIO2 base pointer */ #define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) /** Array initializer of FLEXIO peripheral base addresses */ #define FLEXIO_BASE_ADDRS { FLEXIO1_BASE, FLEXIO2_BASE } /** Array initializer of FLEXIO peripheral base pointers */ #define FLEXIO_BASE_PTRS { FLEXIO1, FLEXIO2 } /** Interrupt vectors for the FLEXIO peripheral type */ #define FLEXIO_IRQS { FLEXIO1_IRQn, FLEXIO2_IRQn } /*! * @} */ /* end of group FLEXIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer * @{ */ /** FLEXSPI - Register Layout Typedef */ typedef struct { __IO uint32_t MCR0; /**< Module Control 0, offset: 0x0 */ __IO uint32_t MCR1; /**< Module Control 1, offset: 0x4 */ __IO uint32_t MCR2; /**< Module Control 2, offset: 0x8 */ __IO uint32_t AHBCR; /**< AHB Bus Control, offset: 0xC */ __IO uint32_t INTEN; /**< Interrupt Enable, offset: 0x10 */ __IO uint32_t INTR; /**< Interrupt, offset: 0x14 */ __IO uint32_t LUTKEY; /**< LUT Key, offset: 0x18 */ __IO uint32_t LUTCR; /**< LUT Control, offset: 0x1C */ __IO uint32_t AHBRXBUFCR0[8]; /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[32]; __IO uint32_t FLSHCR0[4]; /**< Flash Control 0, array offset: 0x60, array step: 0x4 */ __IO uint32_t FLSHCR1[4]; /**< Flash Control 1, array offset: 0x70, array step: 0x4 */ __IO uint32_t FLSHCR2[4]; /**< Flash Control 2, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t FLSHCR4; /**< Flash Control 4, offset: 0x94 */ uint8_t RESERVED_2[8]; __IO uint32_t IPCR0; /**< IP Control 0, offset: 0xA0 */ __IO uint32_t IPCR1; /**< IP Control 1, offset: 0xA4 */ __IO uint32_t IPCR2; /**< IP Control 2, offset: 0xA8 */ uint8_t RESERVED_3[4]; __O uint32_t IPCMD; /**< IP Command, offset: 0xB0 */ __IO uint32_t DLPR; /**< Data Learning Pattern, offset: 0xB4 */ __IO uint32_t IPRXFCR; /**< IP Receive FIFO Control, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ __IO uint32_t DLLCR[2]; /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[24]; __I uint32_t STS0; /**< Status 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status 1, offset: 0xE4 */ __I uint32_t STS2; /**< Status 2, offset: 0xE8 */ __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status, offset: 0xEC */ __I uint32_t IPRXFSTS; /**< IP Receive FIFO Status, offset: 0xF0 */ __I uint32_t IPTXFSTS; /**< IP Transmit FIFO Status, offset: 0xF4 */ uint8_t RESERVED_5[8]; __I uint32_t RFDR[32]; /**< IP Receive FIFO Data 0..IP Receive FIFO Data 31, array offset: 0x100, array step: 0x4 */ __O uint32_t TFDR[32]; /**< IP TX FIFO Data 0..IP TX FIFO Data 31, array offset: 0x180, array step: 0x4 */ __IO uint32_t LUT[128]; /**< Lookup Table 0..Lookup Table 127, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_6[48]; __IO uint32_t IPSNSZSTART0; /**< IPS Nonsecure Region 0 Start Address, offset: 0x430 */ __IO uint32_t IPSNSZEND0; /**< IPS Nonsecure Region 0 End Address, offset: 0x434 */ __IO uint32_t IPSNSZSTART1; /**< IPS Nonsecure Region 1 Start Address, offset: 0x438 */ __IO uint32_t IPSNSZEND1; /**< IPS Nonsecure Region 1 End Address, offset: 0x43C */ __IO uint32_t AHBBUFREGIONSTART0; /**< Receive Buffer Start Address of Region 0, offset: 0x440 */ __IO uint32_t AHBBUFREGIONEND0; /**< Receive Buffer Region 0 End Address, offset: 0x444 */ __IO uint32_t AHBBUFREGIONSTART1; /**< Receive Buffer Start Address of Region 1, offset: 0x448 */ __IO uint32_t AHBBUFREGIONEND1; /**< Receive Buffer Region 1 End Address, offset: 0x44C */ __IO uint32_t AHBBUFREGIONSTART2; /**< Receive Buffer Start Address of Region 2, offset: 0x450 */ __IO uint32_t AHBBUFREGIONEND2; /**< Receive Buffer Region 2 End Address, offset: 0x454 */ __IO uint32_t AHBBUFREGIONSTART3; /**< Receive Buffer Start Address of Region 3, offset: 0x458 */ __IO uint32_t AHBBUFREGIONEND3; /**< Receive Buffer Region 3 End Address, offset: 0x45C */ } FLEXSPI_Type; /* ---------------------------------------------------------------------------- -- FLEXSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks * @{ */ /*! @name MCR0 - Module Control 0 */ /*! @{ */ #define FLEXSPI_MCR0_SWRESET_MASK (0x1U) #define FLEXSPI_MCR0_SWRESET_SHIFT (0U) /*! SWRESET - Software Reset * 0b0..No impact * 0b1..Software reset */ #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) #define FLEXSPI_MCR0_MDIS_MASK (0x2U) #define FLEXSPI_MCR0_MDIS_SHIFT (1U) /*! MDIS - Module Disable * 0b0..No impact * 0b1..Module disable */ #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock Source for Flash Reading * 0b00..Dummy Read strobe that FlexSPI generates, looped back internally * 0b01..Dummy Read strobe that FlexSPI generates, looped back from DQS pad * 0b10..SCLK output clock and looped back from SCLK pad * 0b11..Flash-memory-provided read strobe and input from DQS pad */ #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) /*! ARDFEN - AHB Read Access to IP Receive FIFO Enable * 0b0..AHB read access disabled. IP bus reads IP receive FIFO. AHB Bus read access to IP receive FIFO memory space produces bus error. * 0b1..AHB read access enabled. AHB bus reads IP receive FIFO. IP Bus read access to IP receive FIFO memory * space returns data zero and causes no bus error. */ #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) /*! ATDFEN - AHB Write Access to IP Transmit FIFO Enable * 0b0..AHB write access disabled. IP bus writes to IP transmit FIFO. AHB bus write access to IP transmit FIFO memory space produces bus error. * 0b1..AHB write access enabled. AHB bus writes to IP transmit FIFO. IP Bus write access to IP transmit FIFO * memory space is ignored and causes no bus error. */ #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) #define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) #define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) /*! SERCLKDIV - Serial Root Clock Divider * 0b000..Divided by 1 * 0b001..Divided by 2 * 0b010..Divided by 3 * 0b011..Divided by 4 * 0b100..Divided by 5 * 0b101..Divided by 6 * 0b110..Divided by 7 * 0b111..Divided by 8 */ #define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) #define FLEXSPI_MCR0_HSEN_MASK (0x800U) #define FLEXSPI_MCR0_HSEN_SHIFT (11U) /*! HSEN - Half Speed Serial Flash Memory Access Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) /*! DOZEEN - Doze Mode Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) /*! SCKFREERUNEN - SCLK Free-running Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) #define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) #define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) /*! LEARNEN - Data Learning Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) /*! IPGRANTWAIT - Timeout Wait Cycle for IP Command Grant */ #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) /*! AHBGRANTWAIT - Timeouts Wait Cycle for AHB command Grant */ #define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) /*! @} */ /*! @name MCR1 - Module Control 1 */ /*! @{ */ #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) /*! AHBBUSWAIT - AHB Bus Wait */ #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) /*! SEQWAIT - Command Sequence Wait */ #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) /*! @} */ /*! @name MCR2 - Module Control 2 */ /*! @{ */ #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) /*! CLRAHBBUFOPT - Clear AHB Buffer * 0b0..Not cleared automatically * 0b1..Cleared automatically */ #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) #define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) #define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) /*! CLRLEARNPHASE - Clear Learn Phase Selection * 0b0..No impact * 0b1..Reset sample clock phase selection to 0 */ #define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) /*! SAMEDEVICEEN - Same Device Enable * 0b0..In Individual mode, FLSHA1CRx and FLSHA2CRx, FLSHB1CRx and FLSHB2CRx settings are applied to Flash A1, A2, B1, B2 separately. * 0b1..FLSHA1CR0, FLSHA1CR1, and FLSHA1CR2 register settings are applied to Flash A1, A2, B1, B2. FLSHA2CRx, * FLSHB1CRx, and FLSHB2CRx settings are ignored. */ #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) /*! RESUMEWAIT - Resume Wait Duration */ #define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) /*! @} */ /*! @name AHBCR - AHB Bus Control */ /*! @{ */ #define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) #define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) /*! CLRAHBTXBUF - Clear AHB Transmit Buffer * 0b0..No impact. * 0b1..Enable clear operation. */ #define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) /*! CACHABLEEN - Cacheable Read Access Enable * 0b0..Disabled. When an AHB bus cacheable read access occurs, FlexSPI does not check whether it hit the AHB transmit buffer. * 0b1..Enabled. When an AHB bus cacheable read access occurs, FlexSPI first checks whether the access hit the AHB transmit buffer. */ #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) /*! BUFFERABLEEN - Bufferable Write Access Enable * 0b0..Disabled. For all AHB write accesses (bufferable or nonbufferable), FlexSPI returns AHB Bus Ready after * transmitting all data and finishing command. * 0b1..Enabled. For AHB bufferable write access, FlexSPI returns AHB Bus Ready when the arbitrator grants the * AHB command. FlexSPI does not wait for the AHB command to finish. */ #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) /*! PREFETCHEN - AHB Read Prefetch Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) /*! READADDROPT - AHB Read Address Option * 0b0..AHB read burst start address alignment is limited when flash memory is accessed in flash is word-addressable. * 0b1..AHB read burst start address alignment is not limited. FlexSPI fetches more data than the AHB burst requires for address alignment. */ #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) #define FLEXSPI_AHBCR_RESUMEDISABLE_MASK (0x80U) #define FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT (7U) /*! RESUMEDISABLE - AHB Read Resume Disable * 0b0..Suspended AHB read prefetch resumes when AHB is IDLE. * 0b1..Suspended AHB read prefetch does not resume once aborted. */ #define FLEXSPI_AHBCR_RESUMEDISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_RESUMEDISABLE_SHIFT)) & FLEXSPI_AHBCR_RESUMEDISABLE_MASK) #define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) #define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) /*! READSZALIGN - AHB Read Size Alignment * 0b0..Register settings such as PREFETCH_EN and OTFAD_EN determine AHB read size. * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching */ #define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) #define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) #define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) /*! ALIGNMENT - AHB Boundary Alignment * 0b00..No limit * 0b01..1 KB * 0b10..512 bytes * 0b11..256 bytes */ #define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) #define FLEXSPI_AHBCR_AFLASHBASE_MASK (0xF8000000U) #define FLEXSPI_AHBCR_AFLASHBASE_SHIFT (27U) /*! AFLASHBASE - AHB Memory-Mapped Flash Base Address */ #define FLEXSPI_AHBCR_AFLASHBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ /*! @{ */ #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) /*! IPCMDDONEEN - IP-Triggered Command Sequences Execution Finished Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) #define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) /*! IPCMDGEEN - IP-Triggered Command Sequences Grant Timeout Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) #define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) /*! AHBCMDGEEN - AHB-Triggered Command Sequences Grant Timeout Interrupt Enable. * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) #define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) #define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) /*! IPCMDERREN - IP-Triggered Command Sequences Error Detected Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) #define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) /*! AHBCMDERREN - AHB-Triggered Command Sequences Error Detected Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) #define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) #define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) /*! IPRXWAEN - IP Receive FIFO Watermark Available Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) #define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) #define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) /*! IPTXWEEN - IP Transmit FIFO Watermark Empty Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) #define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) #define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) /*! DATALEARNFAILEN - Data Learning Failed Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) /*! SCKSTOPBYRDEN - SCLK Stopped By Read Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) /*! SCKSTOPBYWREN - SCLK Stopped By Write Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) #define FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U) #define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U) /*! AHBBUSERROREN - AHB Bus Error Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) /*! SEQTIMEOUTEN - Sequence execution Timeout Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) #define FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U) #define FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U) /*! KEYDONEEN - OTFAD Key Blob Processing Done Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) #define FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U) #define FLEXSPI_INTEN_KEYERROREN_SHIFT (13U) /*! KEYERROREN - OTFAD Key Blob Processing Error Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) #define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) /*! IPCMDSECUREVIOEN - IP Command Security Violation Interrupt Enable * 0b0..Disable interrupt or no impact * 0b1..Enable interrupt */ #define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) /*! @} */ /*! @name INTR - Interrupt */ /*! @{ */ #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) #define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) /*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) /*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) #define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) /*! IPCMDERR - IP-Triggered Command Sequences Error * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) #define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) /*! AHBCMDERR - AHB-Triggered Command Sequences Error * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) #define FLEXSPI_INTR_IPRXWA_MASK (0x20U) #define FLEXSPI_INTR_IPRXWA_SHIFT (5U) /*! IPRXWA - IP Receive FIFO Watermark Available * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) #define FLEXSPI_INTR_IPTXWE_MASK (0x40U) #define FLEXSPI_INTR_IPTXWE_SHIFT (6U) /*! IPTXWE - IP Transmit FIFO Watermark Empty * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) #define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) #define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) /*! DATALEARNFAIL - Data Learning Failed * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) #define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) /*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) #define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) /*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) #define FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U) #define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) /*! AHBBUSERROR - AHB Bus Error * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) /*! SEQTIMEOUT - Sequence Execution Timeout * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) #define FLEXSPI_INTR_KEYDONE_MASK (0x1000U) #define FLEXSPI_INTR_KEYDONE_SHIFT (12U) /*! KEYDONE - OTFAD key blob processing done interrupt. */ #define FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) #define FLEXSPI_INTR_KEYERROR_MASK (0x2000U) #define FLEXSPI_INTR_KEYERROR_SHIFT (13U) /*! KEYERROR - OTFAD Key Blob Processing Error * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) #define FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) #define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) /*! IPCMDSECUREVIO - IP Command Security Violation * 0b0..Interrupt condition has not occurred * 0b1..Interrupt condition has occurred * 0b0..No effect * 0b1..Clear the flag */ #define FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) /*! @} */ /*! @name LUTKEY - LUT Key */ /*! @{ */ #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FLEXSPI_LUTKEY_KEY_SHIFT (0U) /*! KEY - LUT Key */ #define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) /*! @} */ /*! @name LUTCR - LUT Control */ /*! @{ */ #define FLEXSPI_LUTCR_LOCK_MASK (0x1U) #define FLEXSPI_LUTCR_LOCK_SHIFT (0U) /*! LOCK - Lock LUT * 0b0..LUT is unlocked (LUTCR[UNLOCK] must be 1) * 0b1..LUT is locked and cannot be written */ #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) /*! UNLOCK - Unlock LUT * 0b0..LUT is locked (LUTCR[LOCK] must be 1) * 0b1..LUT is unlocked and can be written */ #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) #define FLEXSPI_LUTCR_PROTECT_MASK (0x4U) #define FLEXSPI_LUTCR_PROTECT_SHIFT (2U) /*! PROTECT - LUT Protection * 0b0..Not protected. All IPS controllers can access LUTCR and LUT memory. * 0b1..Protected. Only secure IPS controller can change the value of LUTCR and write to LUT memory. */ #define FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) /*! @} */ /*! @name AHBRXBUFCR0 - AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0 */ /*! @{ */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) /*! BUFSZ - AHB Receive Buffer Size */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) /*! MSTRID - AHB Controller ID */ #define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) /*! PRIORITY - AHB Controller Read Priority */ #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) #define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) #define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) /*! REGIONEN - AHB Receive Buffer Address Region Enable * 0b0..Disabled. The buffer hit is based on the value of MSTRID only. * 0b1..Enabled. The buffer hit is based on the value of MSTRID and the address within AHBBUFREGIONSTARTn and AHBREGIONENDn. */ #define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) /*! PREFETCHEN - AHB Read Prefetch Enable * 0b0..Disabled * 0b1..Enabled when is enabled. */ #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) /*! @} */ /* The count of FLEXSPI_AHBRXBUFCR0 */ #define FLEXSPI_AHBRXBUFCR0_COUNT (8U) /*! @name FLSHCR0 - Flash Control 0 */ /*! @{ */ #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) /*! FLSHSZ - Flash Size in KB */ #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) #define FLEXSPI_FLSHCR0_ADDRSHIFT_MASK (0x20000000U) #define FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT (29U) /*! ADDRSHIFT - AHB Address Shift Function control * 0b0..Disabled * 0b1..Enabled */ #define FLEXSPI_FLSHCR0_ADDRSHIFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_ADDRSHIFT_SHIFT)) & FLEXSPI_FLSHCR0_ADDRSHIFT_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR0 */ #define FLEXSPI_FLSHCR0_COUNT (4U) /*! @name FLSHCR1 - Flash Control 1 */ /*! @{ */ #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) /*! TCSS - Serial Flash CS Setup Time */ #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) #define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) #define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) /*! TCSH - Serial Flash CS Hold Time */ #define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) #define FLEXSPI_FLSHCR1_WA_MASK (0x400U) #define FLEXSPI_FLSHCR1_WA_SHIFT (10U) /*! WA - Word-Addressable * 0b0..Byte-addressable * 0b1..Word-addressable */ #define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) #define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) #define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) /*! CAS - Column Address Size */ #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) /*! CSINTERVALUNIT - Chip Select Interval Unit * 0b0..1 serial clock cycle * 0b1..256 serial clock cycles */ #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) /*! CSINTERVAL - Chip Select Interval */ #define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR1 */ #define FLEXSPI_FLSHCR1_COUNT (4U) /*! @name FLSHCR2 - Flash Control 2 */ /*! @{ */ #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) /*! ARDSEQID - Sequence Index for AHB Read-Triggered Command in LUT */ #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) /*! ARDSEQNUM - Sequence Number for AHB Read-Triggered Command */ #define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) #define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) /*! AWRSEQID - Sequence Index for AHB Write-Triggered Command */ #define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) /*! AWRSEQNUM - Sequence Number for AHB Write-Triggered Command */ #define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) /*! AWRWAIT - AHB Write Wait */ #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT Unit * 0b000..2 * 0b001..8 * 0b010..32 * 0b011..128 * 0b100..512 * 0b101..2048 * 0b110..8192 * 0b111..32768 */ #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) /*! CLRINSTRPTR - Clear Instruction Pointer */ #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR2 */ #define FLEXSPI_FLSHCR2_COUNT (4U) /*! @name FLSHCR4 - Flash Control 4 */ /*! @{ */ #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) /*! WMOPT1 - Write Mask Option 1 * 0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in * individual mode, AHB or IP write burst start address alignment is not limited. * 0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in * individual mode, AHB or IP write burst start address alignment is limited. */ #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) #define FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U) #define FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U) /*! WMOPT2 - Write Mask Option 2 * 0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in * individual mode, AHB or IP write burst length is not limited. * 0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in * individual mode, AHB or IP write burst length is limited. The minimum write burst length should be 4. */ #define FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write Mask Enable for Port A * 0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven. * 0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output. */ #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) /*! @} */ /*! @name IPCR0 - IP Control 0 */ /*! @{ */ #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FLEXSPI_IPCR0_SFAR_SHIFT (0U) /*! SFAR - Serial Flash Address */ #define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) /*! @} */ /*! @name IPCR1 - IP Control 1 */ /*! @{ */ #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) /*! IDATSZ - Flash Read/Program Data Size (in bytes) for IP command. */ #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) #define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U) #define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) /*! ISEQID - Sequence Index in LUT for IP command. */ #define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) #define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) #define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) /*! @} */ /*! @name IPCR2 - IP Control 2 */ /*! @{ */ #define FLEXSPI_IPCR2_IPBLKAHBREQ_MASK (0x1U) #define FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT (0U) /*! IPBLKAHBREQ - IP Command Blocking AHB Command Request Enable * 0b0..IP commands do not block AHB command requests. * 0b1..IP commands block AHB command requests. */ #define FLEXSPI_IPCR2_IPBLKAHBREQ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBREQ_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBREQ_MASK) #define FLEXSPI_IPCR2_IPBLKAHBACK_MASK (0x2U) #define FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT (1U) /*! IPBLKAHBACK - IP Command Blocking AHB Command Acknowledgment Enable * 0b0..IP commands do not block AHB command acknowledgment. * 0b1..IP commands block AHB command acknowledgment. */ #define FLEXSPI_IPCR2_IPBLKAHBACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKAHBACK_SHIFT)) & FLEXSPI_IPCR2_IPBLKAHBACK_MASK) #define FLEXSPI_IPCR2_IPBLKALLAHB_MASK (0x4U) #define FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT (2U) /*! IPBLKALLAHB - IP Command Blocking All AHB Command Enable * 0b0.. * 0b1..IP commands block all AHB commands. */ #define FLEXSPI_IPCR2_IPBLKALLAHB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR2_IPBLKALLAHB_SHIFT)) & FLEXSPI_IPCR2_IPBLKALLAHB_MASK) /*! @} */ /*! @name IPCMD - IP Command */ /*! @{ */ #define FLEXSPI_IPCMD_TRG_MASK (0x1U) #define FLEXSPI_IPCMD_TRG_SHIFT (0U) /*! TRG - Command Trigger * 0b0..No action * 0b1..Start the IP command that the IPCR0 and IPCR1 registers define. */ #define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) /*! @} */ /*! @name DLPR - Data Learning Pattern */ /*! @{ */ #define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) #define FLEXSPI_DLPR_DLP_SHIFT (0U) /*! DLP - Data Learning Pattern */ #define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) /*! @} */ /*! @name IPRXFCR - IP Receive FIFO Control */ /*! @{ */ #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) /*! CLRIPRXF - Clear IP Receive FIFO * 0b0..No function * 0b1..A clock cycle pulse clears all valid data entries in IP receive FIFO. */ #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) /*! RXDMAEN - IP Receive FIFO Reading by DMA Enable * 0b0..Disabled. The processor reads the FIFO. * 0b1..Enabled. DMA reads the FIFO. */ #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) /*! RXWMRK - IP Receive FIFO Watermark Level */ #define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) /*! @} */ /*! @name IPTXFCR - IP Transmit FIFO Control */ /*! @{ */ #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) /*! CLRIPTXF - Clear IP Transmit FIFO * 0b0..No function * 0b1..A clock cycle pulse clears all valid data entries in the IP transmit FIFO. */ #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) /*! TXDMAEN - Transmit FIFO DMA Enable * 0b0..Processor * 0b1..DMA */ #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) /*! TXWMRK - Transmit Watermark Level */ #define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) /*! @} */ /*! @name DLLCR - DLL Control 0 */ /*! @{ */ #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) /*! DLLEN - DLL Calibration Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) /*! DLLRESET - DLL reset * 0b0..No function * 0b1..Force DLL reset. */ #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) /*! SLVDLYTARGET - Target Delay Line */ #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) #define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) /*! OVRDEN - Target Clock Delay Line Override Value Enable * 0b0..Disable * 0b1..Enable */ #define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Target Clock Delay Line Override Value */ #define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) #define FLEXSPI_DLLCR_REFPHASEGAP_MASK (0x18000U) #define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT (15U) /*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */ #define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) /*! @} */ /* The count of FLEXSPI_DLLCR */ #define FLEXSPI_DLLCR_COUNT (2U) /*! @name STS0 - Status 0 */ /*! @{ */ #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) /*! SEQIDLE - SEQ_CTL State Machine Idle * 0b0..Not idle * 0b1..Idle */ #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) #define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) #define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) /*! ARBIDLE - ARB_CTL State Machine Idle * 0b0..Not idle * 0b1..Idle */ #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - ARB Command Source * 0b00..Trigger source is AHB read command. * 0b01..Trigger source is AHB write command. * 0b10..Trigger source is IP command (by writing 1 to IPCMD[TRG]). * 0b11..Trigger source is a suspended command that has resumed. */ #define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) #define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) #define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) /*! DATALEARNPHASEA - Data Learning Phase Selection on Port A */ #define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) /*! @} */ /*! @name STS1 - Status 1 */ /*! @{ */ #define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU) #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) /*! AHBCMDERRID - AHB Command Error ID */ #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - AHB Command Error Code * 0b0000..No error * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence * 0b0011..Unknown instruction opcode in the sequence * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence * 0b1110..Sequence execution timeout */ #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) #define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U) #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) /*! IPCMDERRID - IP Command Error ID */ #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) /*! IPCMDERRCODE - IP Command Error Code * 0b0000..No error * 0b0010..IP command with JMP_ON_CS instruction used in the sequence * 0b0011..Unknown instruction opcode in the sequence * 0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence * 0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence * 0b0110..Flash memory access start address exceeds entire flash address range (A1, A2, B1, and B2) * 0b1110..Sequence execution timeout * 0b1111..Flash boundary crossed */ #define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) /*! @} */ /*! @name STS2 - Status 2 */ /*! @{ */ #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) /*! ASLVLOCK - Flash A Sample Target Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) #define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) #define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) /*! AREFLOCK - Flash A Sample Clock Reference Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) #define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) #define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) /*! ASLVSEL - Flash A Sample Clock Target Delay Line Delay Cell Number */ #define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) #define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) #define FLEXSPI_STS2_AREFSEL_SHIFT (8U) /*! AREFSEL - Flash A Sample Clock Reference Delay Line Delay Cell Number */ #define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) #define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) #define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) /*! BSLVLOCK - Flash B Sample Target Reference Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) #define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) #define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) /*! BREFLOCK - Flash B Sample Clock Reference Delay Line Locked * 0b0..Not locked * 0b1..Locked */ #define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) #define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) #define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) /*! BSLVSEL - Flash B Sample Clock Target Delay Line Delay Cell Number */ #define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FLEXSPI_STS2_BREFSEL_SHIFT (24U) /*! BREFSEL - Flash B Sample Clock Reference Delay Line Delay Cell Number */ #define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) /*! @} */ /*! @name AHBSPNDSTS - AHB Suspend Status */ /*! @{ */ #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) /*! ACTIVE - Active AHB Read Prefetch Suspended * 0b0..No suspended AHB read prefetch command. * 0b1..An AHB read prefetch command sequence has been suspended. */ #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) #define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) /*! BUFID - AHB Receive Buffer ID for Suspended Command Sequence */ #define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) /*! DATLFT - Data Left */ #define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) /*! @} */ /*! @name IPRXFSTS - IP Receive FIFO Status */ /*! @{ */ #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) /*! FILL - Fill Level of IP Receive FIFO */ #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) /*! RDCNTR - Read Data Counter */ #define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) /*! @} */ /*! @name IPTXFSTS - IP Transmit FIFO Status */ /*! @{ */ #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) /*! FILL - Fill Level of IP Transmit FIFO */ #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) /*! WRCNTR - Write Data Counter */ #define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) /*! @} */ /*! @name RFDR - IP Receive FIFO Data 0..IP Receive FIFO Data 31 */ /*! @{ */ #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_RFDR_RXDATA_SHIFT (0U) /*! RXDATA - Receive Data */ #define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) /*! @} */ /* The count of FLEXSPI_RFDR */ #define FLEXSPI_RFDR_COUNT (32U) /*! @name TFDR - IP TX FIFO Data 0..IP TX FIFO Data 31 */ /*! @{ */ #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_TFDR_TXDATA_SHIFT (0U) /*! TXDATA - Transmit Data */ #define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) /*! @} */ /* The count of FLEXSPI_TFDR */ #define FLEXSPI_TFDR_COUNT (32U) /*! @name LUT - Lookup Table 0..Lookup Table 127 */ /*! @{ */ #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) #define FLEXSPI_LUT_OPERAND0_SHIFT (0U) /*! OPERAND0 - OPERAND0 */ #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) #define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) #define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) /*! NUM_PADS0 - NUM_PADS0 */ #define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) #define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) #define FLEXSPI_LUT_OPCODE0_SHIFT (10U) /*! OPCODE0 - OPCODE */ #define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) #define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) #define FLEXSPI_LUT_OPERAND1_SHIFT (16U) /*! OPERAND1 - OPERAND1 */ #define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) #define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) #define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) /*! NUM_PADS1 - NUM_PADS1 */ #define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FLEXSPI_LUT_OPCODE1_SHIFT (26U) /*! OPCODE1 - OPCODE1 */ #define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) /*! @} */ /* The count of FLEXSPI_LUT */ #define FLEXSPI_LUT_COUNT (128U) /*! @name IPSNSZSTART0 - IPS Nonsecure Region 0 Start Address */ /*! @{ */ #define FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U) /*! start_address - Start Address of Nonsecure Region */ #define FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) /*! @} */ /*! @name IPSNSZEND0 - IPS Nonsecure Region 0 End Address */ /*! @{ */ #define FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U) /*! end_address - End Address of Nonsecure Region */ #define FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) /*! @} */ /*! @name IPSNSZSTART1 - IPS Nonsecure Region 1 Start Address */ /*! @{ */ #define FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U) /*! start_address - Start Address of Nonsecure Region */ #define FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) /*! @} */ /*! @name IPSNSZEND1 - IPS Nonsecure Region 1 End Address */ /*! @{ */ #define FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U) #define FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U) /*! end_address - End Address of Nonsecure Region */ #define FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART0 - Receive Buffer Start Address of Region 0 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND0 - Receive Buffer Region 0 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_END_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART1 - Receive Buffer Start Address of Region 1 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND1 - Receive Buffer Region 1 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_END_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART2 - Receive Buffer Start Address of Region 2 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND2 - Receive Buffer Region 2 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_END_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONSTART3 - Receive Buffer Start Address of Region 3 */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT (12U) /*! START_ADDRESS - Start Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_START_ADDRESS_MASK) /*! @} */ /*! @name AHBBUFREGIONEND3 - Receive Buffer Region 3 End Address */ /*! @{ */ #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK (0xFFFFF000U) #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT (12U) /*! END_ADDRESS - End Address of Prefetch Sub-Buffer Region */ #define FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_END_ADDRESS_MASK) /*! @} */ /*! * @} */ /* end of group FLEXSPI_Register_Masks */ /* FLEXSPI - Peripheral instance base addresses */ /** Peripheral FLEXSPI base address */ #define FLEXSPI_BASE (0x425E0000u) /** Peripheral FLEXSPI base pointer */ #define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) /** Array initializer of FLEXSPI peripheral base addresses */ #define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } /** Array initializer of FLEXSPI peripheral base pointers */ #define FLEXSPI_BASE_PTRS { FLEXSPI } /** Interrupt vectors for the FLEXSPI peripheral type */ #define FLEXSPI_IRQS { FlexSPI1_IRQn } /* FlexSPI AMBA address. */ #define FlexSPI_AMBA_BASE (0x38000000U) /* FlexSPI ASFM address. */ #define FlexSPI_ASFM_BASE (0x38000000U) /* Base Address of AHB address space mapped to IP RX FIFO. */ #define FlexSPI_ARDF_BASE (0x57420000U) /* Base Address of AHB address space mapped to IP TX FIFO. */ #define FlexSPI_ATDF_BASE (0x57430000U) /*! * @} */ /* end of group FLEXSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GCM_Peripheral_Access_Layer GCM Peripheral Access Layer * @{ */ /** GCM - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x84 */ __IO uint32_t IMAT0_CAM; /**< Camera 0 GCM Input Matrix 0 Register, array offset: 0x0, array step: 0x84 */ __IO uint32_t IMAT1_CAM; /**< Camera 0 GCM Input Matrix 1 Register, array offset: 0x4, array step: 0x84 */ uint8_t RESERVED_0[4]; __IO uint32_t IMAT2_CAM; /**< Camera 0 GCM Input Matrix 2 Register, array offset: 0xC, array step: 0x84 */ __IO uint32_t IMAT3_CAM; /**< Camera 0 GCM Input Matrix 3 Register, array offset: 0x10, array step: 0x84 */ uint8_t RESERVED_1[4]; __IO uint32_t IMAT4_CAM; /**< Camera 0 GCM Input Matrix 4 Register, array offset: 0x18, array step: 0x84 */ __IO uint32_t IMAT5_CAM; /**< Camera 0 GCM Input Matrix 5 Register, array offset: 0x1C, array step: 0x84 */ __IO uint32_t IOFFSET0_CAM; /**< Camera 0 GCM Input Offset0 Register, array offset: 0x20, array step: 0x84 */ __IO uint32_t IOFFSET1_CAM; /**< Camera 0 GCM Input Offset1 Register, array offset: 0x24, array step: 0x84 */ __IO uint32_t IOFFSET2_CAM; /**< Camera 0 GCM Input Offset2 Register, array offset: 0x28, array step: 0x84 */ uint8_t RESERVED_2[4]; __IO uint32_t OMAT0_CAM; /**< Camera 0 GCM Output Matrix 0 Register, array offset: 0x30, array step: 0x84 */ __IO uint32_t OMAT1_CAM; /**< Camera 0 GCM Output Matrix 1 Register, array offset: 0x34, array step: 0x84 */ __IO uint32_t OMAT2_CAM; /**< Camera 0 GCM Output Matrix 2 Register, array offset: 0x38, array step: 0x84 */ __IO uint32_t OMAT3_CAM; /**< Camera 0 GCM Output Matrix 3 Register, array offset: 0x3C, array step: 0x84 */ __IO uint32_t OMAT4_CAM; /**< Camera 0 GCM Output Matrix 4 Register, array offset: 0x40, array step: 0x84 */ __IO uint32_t OMAT5_CAM; /**< Camera 0 GCM Output Matrix 5 Register, array offset: 0x44, array step: 0x84 */ __IO uint32_t OOFFSET0_CAM; /**< Camera 0 GCM Output Offset 0 Register, array offset: 0x48, array step: 0x84 */ __IO uint32_t OOFFSET1_CAM; /**< Camera 0 GCM Output Offset 1 Register, array offset: 0x4C, array step: 0x84 */ __IO uint32_t OOFFSET2_CAM; /**< Camera 0 GCM Output Offset 2 Register, array offset: 0x50, array step: 0x84 */ uint8_t RESERVED_3[12]; __IO uint32_t GAMMA0_CAM; /**< Camera 0 GCM Gamma 0 Register, array offset: 0x60, array step: 0x84 */ __IO uint32_t GAMMA1_CAM; /**< Camera 0 GCM Gamma 1 Register, array offset: 0x64, array step: 0x84 */ __IO uint32_t GAMMA2_CAM; /**< Camera 0 GCM Gamma 2 Register, array offset: 0x68, array step: 0x84 */ __IO uint32_t BLKLVL0_CTRL_CAM; /**< Camera 0 Linear 0 Control, array offset: 0x6C, array step: 0x84 */ __IO uint32_t BLKLVL1_CTRL_CAM; /**< Camera 0 Linear 1 Control, array offset: 0x70, array step: 0x84 */ __IO uint32_t BLKLVL2_CTRL_CAM; /**< Camera 0 Linear 2 Control, array offset: 0x74, array step: 0x84 */ __IO uint32_t LOWTH_CTRL01_CAM; /**< Camera 0 Linear Threshold channel 0 and 1, array offset: 0x78, array step: 0x84 */ __IO uint32_t LOWTH_CTRL2_CAM; /**< Camera 0 Threshold channel 2, array offset: 0x7C, array step: 0x84 */ __IO uint32_t MAT_CONFG_CAM; /**< Camera 0 GCM Configuration Register, array offset: 0x80, array step: 0x84 */ } NEO_PIPE2_GCM_CONF[1]; } GCM_Type; /* ---------------------------------------------------------------------------- -- GCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GCM_Register_Masks GCM Register Masks * @{ */ /*! @name IMAT0_CAM - Camera 0 GCM Input Matrix 0 Register */ /*! @{ */ #define GCM_IMAT0_CAM_R0C0_MASK (0xFFFFU) #define GCM_IMAT0_CAM_R0C0_SHIFT (0U) #define GCM_IMAT0_CAM_R0C0(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT0_CAM_R0C0_SHIFT)) & GCM_IMAT0_CAM_R0C0_MASK) #define GCM_IMAT0_CAM_R0C1_MASK (0xFFFF0000U) #define GCM_IMAT0_CAM_R0C1_SHIFT (16U) #define GCM_IMAT0_CAM_R0C1(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT0_CAM_R0C1_SHIFT)) & GCM_IMAT0_CAM_R0C1_MASK) /*! @} */ /* The count of GCM_IMAT0_CAM */ #define GCM_IMAT0_CAM_COUNT (1U) /*! @name IMAT1_CAM - Camera 0 GCM Input Matrix 1 Register */ /*! @{ */ #define GCM_IMAT1_CAM_R0C2_MASK (0xFFFFU) #define GCM_IMAT1_CAM_R0C2_SHIFT (0U) #define GCM_IMAT1_CAM_R0C2(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT1_CAM_R0C2_SHIFT)) & GCM_IMAT1_CAM_R0C2_MASK) /*! @} */ /* The count of GCM_IMAT1_CAM */ #define GCM_IMAT1_CAM_COUNT (1U) /*! @name IMAT2_CAM - Camera 0 GCM Input Matrix 2 Register */ /*! @{ */ #define GCM_IMAT2_CAM_R1C0_MASK (0xFFFFU) #define GCM_IMAT2_CAM_R1C0_SHIFT (0U) #define GCM_IMAT2_CAM_R1C0(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT2_CAM_R1C0_SHIFT)) & GCM_IMAT2_CAM_R1C0_MASK) #define GCM_IMAT2_CAM_R1C1_MASK (0xFFFF0000U) #define GCM_IMAT2_CAM_R1C1_SHIFT (16U) #define GCM_IMAT2_CAM_R1C1(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT2_CAM_R1C1_SHIFT)) & GCM_IMAT2_CAM_R1C1_MASK) /*! @} */ /* The count of GCM_IMAT2_CAM */ #define GCM_IMAT2_CAM_COUNT (1U) /*! @name IMAT3_CAM - Camera 0 GCM Input Matrix 3 Register */ /*! @{ */ #define GCM_IMAT3_CAM_R1C2_MASK (0xFFFFU) #define GCM_IMAT3_CAM_R1C2_SHIFT (0U) #define GCM_IMAT3_CAM_R1C2(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT3_CAM_R1C2_SHIFT)) & GCM_IMAT3_CAM_R1C2_MASK) /*! @} */ /* The count of GCM_IMAT3_CAM */ #define GCM_IMAT3_CAM_COUNT (1U) /*! @name IMAT4_CAM - Camera 0 GCM Input Matrix 4 Register */ /*! @{ */ #define GCM_IMAT4_CAM_R2C0_MASK (0xFFFFU) #define GCM_IMAT4_CAM_R2C0_SHIFT (0U) #define GCM_IMAT4_CAM_R2C0(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT4_CAM_R2C0_SHIFT)) & GCM_IMAT4_CAM_R2C0_MASK) #define GCM_IMAT4_CAM_R2C1_MASK (0xFFFF0000U) #define GCM_IMAT4_CAM_R2C1_SHIFT (16U) #define GCM_IMAT4_CAM_R2C1(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT4_CAM_R2C1_SHIFT)) & GCM_IMAT4_CAM_R2C1_MASK) /*! @} */ /* The count of GCM_IMAT4_CAM */ #define GCM_IMAT4_CAM_COUNT (1U) /*! @name IMAT5_CAM - Camera 0 GCM Input Matrix 5 Register */ /*! @{ */ #define GCM_IMAT5_CAM_R2C2_MASK (0xFFFFU) #define GCM_IMAT5_CAM_R2C2_SHIFT (0U) #define GCM_IMAT5_CAM_R2C2(x) (((uint32_t)(((uint32_t)(x)) << GCM_IMAT5_CAM_R2C2_SHIFT)) & GCM_IMAT5_CAM_R2C2_MASK) /*! @} */ /* The count of GCM_IMAT5_CAM */ #define GCM_IMAT5_CAM_COUNT (1U) /*! @name IOFFSET0_CAM - Camera 0 GCM Input Offset0 Register */ /*! @{ */ #define GCM_IOFFSET0_CAM_OFFSET0_MASK (0xFFFFU) #define GCM_IOFFSET0_CAM_OFFSET0_SHIFT (0U) #define GCM_IOFFSET0_CAM_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << GCM_IOFFSET0_CAM_OFFSET0_SHIFT)) & GCM_IOFFSET0_CAM_OFFSET0_MASK) /*! @} */ /* The count of GCM_IOFFSET0_CAM */ #define GCM_IOFFSET0_CAM_COUNT (1U) /*! @name IOFFSET1_CAM - Camera 0 GCM Input Offset1 Register */ /*! @{ */ #define GCM_IOFFSET1_CAM_OFFSET1_MASK (0xFFFFU) #define GCM_IOFFSET1_CAM_OFFSET1_SHIFT (0U) #define GCM_IOFFSET1_CAM_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << GCM_IOFFSET1_CAM_OFFSET1_SHIFT)) & GCM_IOFFSET1_CAM_OFFSET1_MASK) /*! @} */ /* The count of GCM_IOFFSET1_CAM */ #define GCM_IOFFSET1_CAM_COUNT (1U) /*! @name IOFFSET2_CAM - Camera 0 GCM Input Offset2 Register */ /*! @{ */ #define GCM_IOFFSET2_CAM_OFFSET2_MASK (0xFFFFU) #define GCM_IOFFSET2_CAM_OFFSET2_SHIFT (0U) #define GCM_IOFFSET2_CAM_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << GCM_IOFFSET2_CAM_OFFSET2_SHIFT)) & GCM_IOFFSET2_CAM_OFFSET2_MASK) /*! @} */ /* The count of GCM_IOFFSET2_CAM */ #define GCM_IOFFSET2_CAM_COUNT (1U) /*! @name OMAT0_CAM - Camera 0 GCM Output Matrix 0 Register */ /*! @{ */ #define GCM_OMAT0_CAM_R0C0_MASK (0xFFFFU) #define GCM_OMAT0_CAM_R0C0_SHIFT (0U) #define GCM_OMAT0_CAM_R0C0(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT0_CAM_R0C0_SHIFT)) & GCM_OMAT0_CAM_R0C0_MASK) #define GCM_OMAT0_CAM_R0C1_MASK (0xFFFF0000U) #define GCM_OMAT0_CAM_R0C1_SHIFT (16U) #define GCM_OMAT0_CAM_R0C1(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT0_CAM_R0C1_SHIFT)) & GCM_OMAT0_CAM_R0C1_MASK) /*! @} */ /* The count of GCM_OMAT0_CAM */ #define GCM_OMAT0_CAM_COUNT (1U) /*! @name OMAT1_CAM - Camera 0 GCM Output Matrix 1 Register */ /*! @{ */ #define GCM_OMAT1_CAM_R0C2_MASK (0xFFFFU) #define GCM_OMAT1_CAM_R0C2_SHIFT (0U) #define GCM_OMAT1_CAM_R0C2(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT1_CAM_R0C2_SHIFT)) & GCM_OMAT1_CAM_R0C2_MASK) /*! @} */ /* The count of GCM_OMAT1_CAM */ #define GCM_OMAT1_CAM_COUNT (1U) /*! @name OMAT2_CAM - Camera 0 GCM Output Matrix 2 Register */ /*! @{ */ #define GCM_OMAT2_CAM_R1C0_MASK (0xFFFFU) #define GCM_OMAT2_CAM_R1C0_SHIFT (0U) #define GCM_OMAT2_CAM_R1C0(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT2_CAM_R1C0_SHIFT)) & GCM_OMAT2_CAM_R1C0_MASK) #define GCM_OMAT2_CAM_R1C1_MASK (0xFFFF0000U) #define GCM_OMAT2_CAM_R1C1_SHIFT (16U) #define GCM_OMAT2_CAM_R1C1(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT2_CAM_R1C1_SHIFT)) & GCM_OMAT2_CAM_R1C1_MASK) /*! @} */ /* The count of GCM_OMAT2_CAM */ #define GCM_OMAT2_CAM_COUNT (1U) /*! @name OMAT3_CAM - Camera 0 GCM Output Matrix 3 Register */ /*! @{ */ #define GCM_OMAT3_CAM_R1C2_MASK (0xFFFFU) #define GCM_OMAT3_CAM_R1C2_SHIFT (0U) #define GCM_OMAT3_CAM_R1C2(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT3_CAM_R1C2_SHIFT)) & GCM_OMAT3_CAM_R1C2_MASK) /*! @} */ /* The count of GCM_OMAT3_CAM */ #define GCM_OMAT3_CAM_COUNT (1U) /*! @name OMAT4_CAM - Camera 0 GCM Output Matrix 4 Register */ /*! @{ */ #define GCM_OMAT4_CAM_R2C0_MASK (0xFFFFU) #define GCM_OMAT4_CAM_R2C0_SHIFT (0U) #define GCM_OMAT4_CAM_R2C0(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT4_CAM_R2C0_SHIFT)) & GCM_OMAT4_CAM_R2C0_MASK) #define GCM_OMAT4_CAM_R2C1_MASK (0xFFFF0000U) #define GCM_OMAT4_CAM_R2C1_SHIFT (16U) #define GCM_OMAT4_CAM_R2C1(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT4_CAM_R2C1_SHIFT)) & GCM_OMAT4_CAM_R2C1_MASK) /*! @} */ /* The count of GCM_OMAT4_CAM */ #define GCM_OMAT4_CAM_COUNT (1U) /*! @name OMAT5_CAM - Camera 0 GCM Output Matrix 5 Register */ /*! @{ */ #define GCM_OMAT5_CAM_R2C2_MASK (0xFFFFU) #define GCM_OMAT5_CAM_R2C2_SHIFT (0U) #define GCM_OMAT5_CAM_R2C2(x) (((uint32_t)(((uint32_t)(x)) << GCM_OMAT5_CAM_R2C2_SHIFT)) & GCM_OMAT5_CAM_R2C2_MASK) /*! @} */ /* The count of GCM_OMAT5_CAM */ #define GCM_OMAT5_CAM_COUNT (1U) /*! @name OOFFSET0_CAM - Camera 0 GCM Output Offset 0 Register */ /*! @{ */ #define GCM_OOFFSET0_CAM_OFFSET0_MASK (0x1FFFU) #define GCM_OOFFSET0_CAM_OFFSET0_SHIFT (0U) #define GCM_OOFFSET0_CAM_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << GCM_OOFFSET0_CAM_OFFSET0_SHIFT)) & GCM_OOFFSET0_CAM_OFFSET0_MASK) /*! @} */ /* The count of GCM_OOFFSET0_CAM */ #define GCM_OOFFSET0_CAM_COUNT (1U) /*! @name OOFFSET1_CAM - Camera 0 GCM Output Offset 1 Register */ /*! @{ */ #define GCM_OOFFSET1_CAM_OFFSET1_MASK (0x1FFFU) #define GCM_OOFFSET1_CAM_OFFSET1_SHIFT (0U) #define GCM_OOFFSET1_CAM_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << GCM_OOFFSET1_CAM_OFFSET1_SHIFT)) & GCM_OOFFSET1_CAM_OFFSET1_MASK) /*! @} */ /* The count of GCM_OOFFSET1_CAM */ #define GCM_OOFFSET1_CAM_COUNT (1U) /*! @name OOFFSET2_CAM - Camera 0 GCM Output Offset 2 Register */ /*! @{ */ #define GCM_OOFFSET2_CAM_OFFSET2_MASK (0x1FFFU) #define GCM_OOFFSET2_CAM_OFFSET2_SHIFT (0U) #define GCM_OOFFSET2_CAM_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << GCM_OOFFSET2_CAM_OFFSET2_SHIFT)) & GCM_OOFFSET2_CAM_OFFSET2_MASK) /*! @} */ /* The count of GCM_OOFFSET2_CAM */ #define GCM_OOFFSET2_CAM_COUNT (1U) /*! @name GAMMA0_CAM - Camera 0 GCM Gamma 0 Register */ /*! @{ */ #define GCM_GAMMA0_CAM_GAMMA0_MASK (0x1FFU) #define GCM_GAMMA0_CAM_GAMMA0_SHIFT (0U) #define GCM_GAMMA0_CAM_GAMMA0(x) (((uint32_t)(((uint32_t)(x)) << GCM_GAMMA0_CAM_GAMMA0_SHIFT)) & GCM_GAMMA0_CAM_GAMMA0_MASK) #define GCM_GAMMA0_CAM_OFFSET0_MASK (0xFFF0000U) #define GCM_GAMMA0_CAM_OFFSET0_SHIFT (16U) #define GCM_GAMMA0_CAM_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << GCM_GAMMA0_CAM_OFFSET0_SHIFT)) & GCM_GAMMA0_CAM_OFFSET0_MASK) /*! @} */ /* The count of GCM_GAMMA0_CAM */ #define GCM_GAMMA0_CAM_COUNT (1U) /*! @name GAMMA1_CAM - Camera 0 GCM Gamma 1 Register */ /*! @{ */ #define GCM_GAMMA1_CAM_GAMMA1_MASK (0x1FFU) #define GCM_GAMMA1_CAM_GAMMA1_SHIFT (0U) #define GCM_GAMMA1_CAM_GAMMA1(x) (((uint32_t)(((uint32_t)(x)) << GCM_GAMMA1_CAM_GAMMA1_SHIFT)) & GCM_GAMMA1_CAM_GAMMA1_MASK) #define GCM_GAMMA1_CAM_OFFSET1_MASK (0xFFF0000U) #define GCM_GAMMA1_CAM_OFFSET1_SHIFT (16U) #define GCM_GAMMA1_CAM_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << GCM_GAMMA1_CAM_OFFSET1_SHIFT)) & GCM_GAMMA1_CAM_OFFSET1_MASK) /*! @} */ /* The count of GCM_GAMMA1_CAM */ #define GCM_GAMMA1_CAM_COUNT (1U) /*! @name GAMMA2_CAM - Camera 0 GCM Gamma 2 Register */ /*! @{ */ #define GCM_GAMMA2_CAM_GAMMA2_MASK (0x1FFU) #define GCM_GAMMA2_CAM_GAMMA2_SHIFT (0U) #define GCM_GAMMA2_CAM_GAMMA2(x) (((uint32_t)(((uint32_t)(x)) << GCM_GAMMA2_CAM_GAMMA2_SHIFT)) & GCM_GAMMA2_CAM_GAMMA2_MASK) #define GCM_GAMMA2_CAM_OFFSET2_MASK (0xFFF0000U) #define GCM_GAMMA2_CAM_OFFSET2_SHIFT (16U) #define GCM_GAMMA2_CAM_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << GCM_GAMMA2_CAM_OFFSET2_SHIFT)) & GCM_GAMMA2_CAM_OFFSET2_MASK) /*! @} */ /* The count of GCM_GAMMA2_CAM */ #define GCM_GAMMA2_CAM_COUNT (1U) /*! @name BLKLVL0_CTRL_CAM - Camera 0 Linear 0 Control */ /*! @{ */ #define GCM_BLKLVL0_CTRL_CAM_OFFSET0_MASK (0xFFFFU) #define GCM_BLKLVL0_CTRL_CAM_OFFSET0_SHIFT (0U) #define GCM_BLKLVL0_CTRL_CAM_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << GCM_BLKLVL0_CTRL_CAM_OFFSET0_SHIFT)) & GCM_BLKLVL0_CTRL_CAM_OFFSET0_MASK) #define GCM_BLKLVL0_CTRL_CAM_GAIN0_MASK (0xFFFF0000U) #define GCM_BLKLVL0_CTRL_CAM_GAIN0_SHIFT (16U) #define GCM_BLKLVL0_CTRL_CAM_GAIN0(x) (((uint32_t)(((uint32_t)(x)) << GCM_BLKLVL0_CTRL_CAM_GAIN0_SHIFT)) & GCM_BLKLVL0_CTRL_CAM_GAIN0_MASK) /*! @} */ /* The count of GCM_BLKLVL0_CTRL_CAM */ #define GCM_BLKLVL0_CTRL_CAM_COUNT (1U) /*! @name BLKLVL1_CTRL_CAM - Camera 0 Linear 1 Control */ /*! @{ */ #define GCM_BLKLVL1_CTRL_CAM_OFFSET1_MASK (0xFFFFU) #define GCM_BLKLVL1_CTRL_CAM_OFFSET1_SHIFT (0U) #define GCM_BLKLVL1_CTRL_CAM_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << GCM_BLKLVL1_CTRL_CAM_OFFSET1_SHIFT)) & GCM_BLKLVL1_CTRL_CAM_OFFSET1_MASK) #define GCM_BLKLVL1_CTRL_CAM_GAIN1_MASK (0xFFFF0000U) #define GCM_BLKLVL1_CTRL_CAM_GAIN1_SHIFT (16U) #define GCM_BLKLVL1_CTRL_CAM_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << GCM_BLKLVL1_CTRL_CAM_GAIN1_SHIFT)) & GCM_BLKLVL1_CTRL_CAM_GAIN1_MASK) /*! @} */ /* The count of GCM_BLKLVL1_CTRL_CAM */ #define GCM_BLKLVL1_CTRL_CAM_COUNT (1U) /*! @name BLKLVL2_CTRL_CAM - Camera 0 Linear 2 Control */ /*! @{ */ #define GCM_BLKLVL2_CTRL_CAM_OFFSET2_MASK (0xFFFFU) #define GCM_BLKLVL2_CTRL_CAM_OFFSET2_SHIFT (0U) #define GCM_BLKLVL2_CTRL_CAM_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << GCM_BLKLVL2_CTRL_CAM_OFFSET2_SHIFT)) & GCM_BLKLVL2_CTRL_CAM_OFFSET2_MASK) #define GCM_BLKLVL2_CTRL_CAM_GAIN2_MASK (0xFFFF0000U) #define GCM_BLKLVL2_CTRL_CAM_GAIN2_SHIFT (16U) #define GCM_BLKLVL2_CTRL_CAM_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << GCM_BLKLVL2_CTRL_CAM_GAIN2_SHIFT)) & GCM_BLKLVL2_CTRL_CAM_GAIN2_MASK) /*! @} */ /* The count of GCM_BLKLVL2_CTRL_CAM */ #define GCM_BLKLVL2_CTRL_CAM_COUNT (1U) /*! @name LOWTH_CTRL01_CAM - Camera 0 Linear Threshold channel 0 and 1 */ /*! @{ */ #define GCM_LOWTH_CTRL01_CAM_THRESHOLD0_MASK (0xFFFFU) #define GCM_LOWTH_CTRL01_CAM_THRESHOLD0_SHIFT (0U) #define GCM_LOWTH_CTRL01_CAM_THRESHOLD0(x) (((uint32_t)(((uint32_t)(x)) << GCM_LOWTH_CTRL01_CAM_THRESHOLD0_SHIFT)) & GCM_LOWTH_CTRL01_CAM_THRESHOLD0_MASK) #define GCM_LOWTH_CTRL01_CAM_THRESHOLD1_MASK (0xFFFF0000U) #define GCM_LOWTH_CTRL01_CAM_THRESHOLD1_SHIFT (16U) #define GCM_LOWTH_CTRL01_CAM_THRESHOLD1(x) (((uint32_t)(((uint32_t)(x)) << GCM_LOWTH_CTRL01_CAM_THRESHOLD1_SHIFT)) & GCM_LOWTH_CTRL01_CAM_THRESHOLD1_MASK) /*! @} */ /* The count of GCM_LOWTH_CTRL01_CAM */ #define GCM_LOWTH_CTRL01_CAM_COUNT (1U) /*! @name LOWTH_CTRL2_CAM - Camera 0 Threshold channel 2 */ /*! @{ */ #define GCM_LOWTH_CTRL2_CAM_THRESHOLD2_MASK (0xFFFFU) #define GCM_LOWTH_CTRL2_CAM_THRESHOLD2_SHIFT (0U) #define GCM_LOWTH_CTRL2_CAM_THRESHOLD2(x) (((uint32_t)(((uint32_t)(x)) << GCM_LOWTH_CTRL2_CAM_THRESHOLD2_SHIFT)) & GCM_LOWTH_CTRL2_CAM_THRESHOLD2_MASK) /*! @} */ /* The count of GCM_LOWTH_CTRL2_CAM */ #define GCM_LOWTH_CTRL2_CAM_COUNT (1U) /*! @name MAT_CONFG_CAM - Camera 0 GCM Configuration Register */ /*! @{ */ #define GCM_MAT_CONFG_CAM_SIGN_CONFG_MASK (0x1U) #define GCM_MAT_CONFG_CAM_SIGN_CONFG_SHIFT (0U) /*! SIGN_CONFG * 0b0..Signed * 0b1..Unsigned */ #define GCM_MAT_CONFG_CAM_SIGN_CONFG(x) (((uint32_t)(((uint32_t)(x)) << GCM_MAT_CONFG_CAM_SIGN_CONFG_SHIFT)) & GCM_MAT_CONFG_CAM_SIGN_CONFG_MASK) /*! @} */ /* The count of GCM_MAT_CONFG_CAM */ #define GCM_MAT_CONFG_CAM_COUNT (1U) /*! * @} */ /* end of group GCM_Register_Masks */ /* GCM - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__GCM base address */ #define CAMERA__ISP__GCM_BASE (0x4AE01600u) /** Peripheral CAMERA__ISP__GCM base pointer */ #define CAMERA__ISP__GCM ((GCM_Type *)CAMERA__ISP__GCM_BASE) /** Array initializer of GCM peripheral base addresses */ #define GCM_BASE_ADDRS { CAMERA__ISP__GCM_BASE } /** Array initializer of GCM peripheral base pointers */ #define GCM_BASE_PTRS { CAMERA__ISP__GCM } /*! * @} */ /* end of group GCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer * @{ */ /** GPC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t CMC_AUTHEN_CTRL; /**< CMC Authentication Control, offset: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t CMC_MISC; /**< Miscellaneous, offset: 0xC */ __IO uint32_t CMC_MODE_CTRL; /**< CPU mode control, offset: 0x10 */ __I uint32_t CMC_MODE_STAT; /**< CPU mode Status, offset: 0x14 */ __I uint32_t CMC_PIN_STAT; /**< CMC pin Status, offset: 0x18 */ uint8_t RESERVED_2[228]; __IO uint32_t CMC_IRQ_WAKEUP_MASK[12]; /**< IRQ wake-up mask register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_3[16]; __IO uint32_t CMC_NON_IRQ_WAKEUP_MASK; /**< CMC non-IRQ wakeup mask, offset: 0x140 */ uint8_t RESERVED_4[12]; __I uint32_t CMC_IRQ_WAKEUP_STAT[12]; /**< IRQ status register, array offset: 0x150, array step: 0x4 */ uint8_t RESERVED_5[16]; __I uint32_t CMC_NON_IRQ_WAKEUP_STAT; /**< CMC non-IRQ wakeup status, offset: 0x190 */ uint8_t RESERVED_6[108]; __IO uint32_t CMC_SLEEP_A55_HDSK_CTRL; /**< CMC sleep A55_HDSK control, offset: 0x200 */ __I uint32_t CMC_SLEEP_A55_HDSK_STAT; /**< CMC sleep A55_HDSK status, offset: 0x204 */ __IO uint32_t CMC_SLEEP_SSAR_CTRL; /**< CMC sleep SSAR control, offset: 0x208 */ __I uint32_t CMC_SLEEP_SSAR_STAT; /**< CMC sleep SSAR status, offset: 0x20C */ uint8_t RESERVED_7[32]; __IO uint32_t CMC_SLEEP_RESET_CTRL; /**< CMC sleep reset control, offset: 0x230 */ __I uint32_t CMC_SLEEP_RESET_STAT; /**< CMC sleep reset status, offset: 0x234 */ uint8_t RESERVED_8[16]; __IO uint32_t CMC_SLEEP_SYSMAN_CTRL; /**< CMC sleep Sysman control, offset: 0x248 */ __I uint32_t CMC_SLEEP_SYSMAN_STAT; /**< CMC Sleep Sysman status, offset: 0x24C */ uint8_t RESERVED_9[64]; __IO uint32_t CMC_WAKEUP_POWER_CTRL; /**< CMC wakeup power control, offset: 0x290 */ __I uint32_t CMC_WAKEUP_POWER_STAT; /**< CMC wakeup power status, offset: 0x294 */ uint8_t RESERVED_10[48]; __IO uint32_t CMC_WAKEUP_SSAR_CTRL; /**< CMC wakeup SSAR control, offset: 0x2C8 */ __I uint32_t CMC_WAKEUP_SSAR_STAT; /**< CMC wakeup SSAR status, offset: 0x2CC */ __IO uint32_t CMC_WAKEUP_A55_HDSK_CTRL; /**< CMC wakeup A55_HDSK control, offset: 0x2D0 */ __I uint32_t CMC_WAKEUP_A55_HDSK_STAT; /**< CMC wakeup A55_HDSK status, offset: 0x2D4 */ __IO uint32_t CMC_WAKEUP_SYSMAN_CTRL; /**< CMC wakeup Sysman control, offset: 0x2D8 */ __I uint32_t CMC_WAKEUP_SYSMAN_STAT; /**< CMC wakeup Sysman status, offset: 0x2DC */ uint8_t RESERVED_11[160]; __IO uint32_t CMC_SYS_SLEEP_CTRL; /**< CMC system sleep control, offset: 0x380 */ uint8_t RESERVED_12[12]; __IO uint32_t CMC_DEBUG; /**< CMC debug, offset: 0x390 */ } GPC_Type; /* ---------------------------------------------------------------------------- -- GPC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_Register_Masks GPC Register Masks * @{ */ /*! @name CMC_AUTHEN_CTRL - CMC Authentication Control */ /*! @{ */ #define GPC_CMC_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) #define GPC_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) /*! LOCK_CFG - Configuration lock * 0b0..The value of low power configuration fields are not locked. * 0b1..The value of low power configuration fields are locked. It locks the CPUx_CM registers which are marked * as "Locked by LOCK_CFG field" in the function field. */ #define GPC_CMC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CMC_AUTHEN_CTRL_LOCK_CFG_MASK) #define GPC_CMC_AUTHEN_CTRL_USER_MASK (0x100U) #define GPC_CMC_AUTHEN_CTRL_USER_SHIFT (8U) /*! USER - Allow user mode access * 0b0..Allow only privilege mode to access CPU mode control registers * 0b1..Allow both privilege and user mode to access CPU mode control registers */ #define GPC_CMC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_AUTHEN_CTRL_USER_SHIFT)) & GPC_CMC_AUTHEN_CTRL_USER_MASK) #define GPC_CMC_AUTHEN_CTRL_NONSECURE_MASK (0x200U) #define GPC_CMC_AUTHEN_CTRL_NONSECURE_SHIFT (9U) /*! NONSECURE - Allow non-secure mode access * 0b0..Allow only secure mode to access CPU mode control * 0b1..Allow both secure and non-secure mode to access CPU mode control registers */ #define GPC_CMC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CMC_AUTHEN_CTRL_NONSECURE_MASK) #define GPC_CMC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U) #define GPC_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U) /*! LOCK_SETTING - Lock NONSECURE and USER * 0b0..NONSECURE and USER fields are not locked * 0b1..NONSECURE and USER fields are locked */ #define GPC_CMC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CMC_AUTHEN_CTRL_LOCK_SETTING_MASK) #define GPC_CMC_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) #define GPC_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - White list lock * 0b0..WHITE_LIST is not locked * 0b1..WHITE_LIST is locked */ #define GPC_CMC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CMC_AUTHEN_CTRL_LOCK_LIST_MASK) #define GPC_CMC_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) #define GPC_CMC_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define GPC_CMC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CMC_AUTHEN_CTRL_WHITE_LIST_MASK) /*! @} */ /*! @name CMC_MISC - Miscellaneous */ /*! @{ */ #define GPC_CMC_MISC_NMI_STAT_MASK (0x1U) #define GPC_CMC_MISC_NMI_STAT_SHIFT (0U) /*! NMI_STAT - Non-masked interrupt status * 0b0..NMI is not asserted * 0b1..NMI is asserted */ #define GPC_CMC_MISC_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MISC_NMI_STAT_SHIFT)) & GPC_CMC_MISC_NMI_STAT_MASK) #define GPC_CMC_MISC_SLEEP_HOLD_EN_MASK (0x2U) #define GPC_CMC_MISC_SLEEP_HOLD_EN_SHIFT (1U) /*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status * 0b0..Disable cpu_sleep_hold_req * 0b1..Allow cpu_sleep_hold_req to assert during CPU low power status */ #define GPC_CMC_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CMC_MISC_SLEEP_HOLD_EN_MASK) #define GPC_CMC_MISC_SLEEP_HOLD_STAT_MASK (0x4U) #define GPC_CMC_MISC_SLEEP_HOLD_STAT_SHIFT (2U) /*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b * 0b0..CPU sleep hold is acknowledged * 0b1..CPU is not in sleep hold */ #define GPC_CMC_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CMC_MISC_SLEEP_HOLD_STAT_MASK) #define GPC_CMC_MISC_GIC_WAKEUP_STAT_MASK (0x10U) #define GPC_CMC_MISC_GIC_WAKEUP_STAT_SHIFT (4U) /*! GIC_WAKEUP_STAT - GIC wakeup request status * 0b0..GIC wakeup is not asserted * 0b1..GIC wakeup is asserted */ #define GPC_CMC_MISC_GIC_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MISC_GIC_WAKEUP_STAT_SHIFT)) & GPC_CMC_MISC_GIC_WAKEUP_STAT_MASK) #define GPC_CMC_MISC_IRQ_MUX_MASK (0x20U) #define GPC_CMC_MISC_IRQ_MUX_SHIFT (5U) /*! IRQ_MUX - IRQ select * 0b0..From raw IRQ * 0b1..From GIC */ #define GPC_CMC_MISC_IRQ_MUX(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MISC_IRQ_MUX_SHIFT)) & GPC_CMC_MISC_IRQ_MUX_MASK) #define GPC_CMC_MISC_SW_WAKEUP_MASK (0x40U) #define GPC_CMC_MISC_SW_WAKEUP_SHIFT (6U) /*! SW_WAKEUP - Software wakeup. Used for CPU hotplug. * 0b0..Software wakeup is not asserted * 0b1..Software wakeup is asserted */ #define GPC_CMC_MISC_SW_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MISC_SW_WAKEUP_SHIFT)) & GPC_CMC_MISC_SW_WAKEUP_MASK) /*! @} */ /*! @name CMC_MODE_CTRL - CPU mode control */ /*! @{ */ #define GPC_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U) #define GPC_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U) /*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event * 0b00..Stay in RUN mode * 0b01..Transit to WAIT mode * 0b10..Transit to STOP mode * 0b11..Transit to SUSPEND mode */ #define GPC_CMC_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK) #define GPC_CMC_MODE_CTRL_WFE_EN_MASK (0x10U) #define GPC_CMC_MODE_CTRL_WFE_EN_SHIFT (4U) /*! WFE_EN - WFE assertion can be sleep event * 0b0..WFE assertion can not trigger low power * 0b1..WFE assertion can trigger low power */ #define GPC_CMC_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CMC_MODE_CTRL_WFE_EN_MASK) /*! @} */ /*! @name CMC_MODE_STAT - CPU mode Status */ /*! @{ */ #define GPC_CMC_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U) #define GPC_CMC_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U) /*! CPU_MODE_CURRENT - Current CPU mode * 0b00..CPU is currently in RUN mode * 0b01..CPU is currently in WAIT mode * 0b10..CPU is currently in STOP mode * 0b11..CPU is currently in SUSPEND mode */ #define GPC_CMC_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CMC_MODE_STAT_CPU_MODE_CURRENT_MASK) #define GPC_CMC_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU) #define GPC_CMC_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U) /*! CPU_MODE_PREVIOUS - Previous CPU mode * 0b00..CPU was previously in RUN mode * 0b01..CPU was previously in WAIT mode * 0b10..CPU was previously in STOP mode * 0b11..CPU was previously in SUSPEND mode */ #define GPC_CMC_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CMC_MODE_STAT_CPU_MODE_PREVIOUS_MASK) #define GPC_CMC_MODE_STAT_SLEEP_TRANS_BUSY_MASK (0x100U) #define GPC_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT (8U) /*! SLEEP_TRANS_BUSY - Busy on CPU mode transition of sleep, not include set point trans busy. * 0b0..Sleep transition not busy * 0b1..Sleep transition busy */ #define GPC_CMC_MODE_STAT_SLEEP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT)) & GPC_CMC_MODE_STAT_SLEEP_TRANS_BUSY_MASK) #define GPC_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_MASK (0x200U) #define GPC_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT (9U) /*! WAKEUP_TRANS_BUSY - Busy on CPU mode transition of wakeup, not include set point trans busy. * 0b1..Wakeup transition busy * 0b0..Wakeup transition not busy */ #define GPC_CMC_MODE_STAT_WAKEUP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT)) & GPC_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_MASK) #define GPC_CMC_MODE_STAT_SLEEPING_IDLE_MASK (0x400U) #define GPC_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT (10U) /*! SLEEPING_IDLE - Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. * 0b1..In sleeping idle state * 0b0..Not in sleeping idle state */ #define GPC_CMC_MODE_STAT_SLEEPING_IDLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT)) & GPC_CMC_MODE_STAT_SLEEPING_IDLE_MASK) #define GPC_CMC_MODE_STAT_SLEEP_REQUEST_MASK (0x10000U) #define GPC_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT (16U) /*! SLEEP_REQUEST - Status of sleep_request input port * 0b1..Sleep request is asserted * 0b0..Sleep request is not asserted */ #define GPC_CMC_MODE_STAT_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT)) & GPC_CMC_MODE_STAT_SLEEP_REQUEST_MASK) #define GPC_CMC_MODE_STAT_WFE_REQUEST_MASK (0x20000U) #define GPC_CMC_MODE_STAT_WFE_REQUEST_SHIFT (17U) /*! WFE_REQUEST - Status of standby_wfe input port * 0b0..WFE request is not asserted * 0b1..WFE request is asserted */ #define GPC_CMC_MODE_STAT_WFE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_WFE_REQUEST_SHIFT)) & GPC_CMC_MODE_STAT_WFE_REQUEST_MASK) #define GPC_CMC_MODE_STAT_WAKEUP_REQUEST_MASK (0x40000U) #define GPC_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT (18U) /*! WAKEUP_REQUEST - "ORed" of all unmasked IRQ */ #define GPC_CMC_MODE_STAT_WAKEUP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT)) & GPC_CMC_MODE_STAT_WAKEUP_REQUEST_MASK) #define GPC_CMC_MODE_STAT_FSM_STATE_MASK (0x1F000000U) #define GPC_CMC_MODE_STAT_FSM_STATE_SHIFT (24U) /*! FSM_STATE - CPU mode trans FSM state. * 0b00010..SLEEP_SYSMAN * 0b00000..IDLE_RUN * 0b00001..SLEEP_A55_HDSK * 0b00011..SLEEP_SSAR * 0b01000..SLEEP_RESET * 0b01011..SLEEP_SYS * 0b01100..IDLE_SLEEP * 0b01101..WAKEUP_SYS * 0b01111..WAKEUP_POWER * 0b10110..WAKEUP_SSAR * 0b10111..WAKEUP_SYSMAN * 0b11000..WAKEUP_A55_HDSK */ #define GPC_CMC_MODE_STAT_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_MODE_STAT_FSM_STATE_SHIFT)) & GPC_CMC_MODE_STAT_FSM_STATE_MASK) /*! @} */ /*! @name CMC_PIN_STAT - CMC pin Status */ /*! @{ */ #define GPC_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_MASK (0x1U) #define GPC_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT (0U) /*! A55_HDSK_REQUEST_STAT - cpu_mode_trans_a55_hdsk_request pin status */ #define GPC_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT)) & GPC_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_MASK) #define GPC_CMC_PIN_STAT_SSAR_REQUEST_STAT_MASK (0x2U) #define GPC_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT (1U) /*! SSAR_REQUEST_STAT - cpu_mode_trans_ssar_request pin status */ #define GPC_CMC_PIN_STAT_SSAR_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT)) & GPC_CMC_PIN_STAT_SSAR_REQUEST_STAT_MASK) #define GPC_CMC_PIN_STAT_RESET_REQUEST_STAT_MASK (0x40U) #define GPC_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT (6U) /*! RESET_REQUEST_STAT - cpu_mode_trans_reset_request pin status */ #define GPC_CMC_PIN_STAT_RESET_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT)) & GPC_CMC_PIN_STAT_RESET_REQUEST_STAT_MASK) #define GPC_CMC_PIN_STAT_POWER_REQUEST_STAT_MASK (0x80U) #define GPC_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT (7U) /*! POWER_REQUEST_STAT - cpu_mode_trans_power_request pin status */ #define GPC_CMC_PIN_STAT_POWER_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT)) & GPC_CMC_PIN_STAT_POWER_REQUEST_STAT_MASK) #define GPC_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_MASK (0x200U) #define GPC_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT (9U) /*! SYSMAN_REQUEST_STAT - cpu_mode_trans_sysman_request pin status */ #define GPC_CMC_PIN_STAT_SYSMAN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT)) & GPC_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_MASK) #define GPC_CMC_PIN_STAT_A55_HDSK_DONE_STAT_MASK (0x10000U) #define GPC_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT (16U) /*! A55_HDSK_DONE_STAT - cpu_mode_trans_a55_hdsk_done pin status */ #define GPC_CMC_PIN_STAT_A55_HDSK_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT)) & GPC_CMC_PIN_STAT_A55_HDSK_DONE_STAT_MASK) #define GPC_CMC_PIN_STAT_SSAR_DONE_STAT_MASK (0x20000U) #define GPC_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT (17U) /*! SSAR_DONE_STAT - cpu_mode_trans_ssar_done pin status */ #define GPC_CMC_PIN_STAT_SSAR_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT)) & GPC_CMC_PIN_STAT_SSAR_DONE_STAT_MASK) #define GPC_CMC_PIN_STAT_RESET_DONE_STAT_MASK (0x400000U) #define GPC_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT (22U) /*! RESET_DONE_STAT - cpu_mode_trans_reset_done pin status */ #define GPC_CMC_PIN_STAT_RESET_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT)) & GPC_CMC_PIN_STAT_RESET_DONE_STAT_MASK) #define GPC_CMC_PIN_STAT_POWER_DONE_STAT_MASK (0x800000U) #define GPC_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT (23U) /*! POWER_DONE_STAT - cpu_mode_trans_power_done pin status */ #define GPC_CMC_PIN_STAT_POWER_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT)) & GPC_CMC_PIN_STAT_POWER_DONE_STAT_MASK) #define GPC_CMC_PIN_STAT_SYSMAN_DONE_STAT_MASK (0x2000000U) #define GPC_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT (25U) /*! SYSMAN_DONE_STAT - cpu_mode_trans_sysman_done pin status. */ #define GPC_CMC_PIN_STAT_SYSMAN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT)) & GPC_CMC_PIN_STAT_SYSMAN_DONE_STAT_MASK) #define GPC_CMC_PIN_STAT_CPU_MODE_STAT_MASK (0x60000000U) #define GPC_CMC_PIN_STAT_CPU_MODE_STAT_SHIFT (29U) /*! CPU_MODE_STAT - cpu_power_mode pin status * 0b00..RUN mode * 0b01..WAIT mode * 0b10..STOP mode * 0b11..SUSPEND mode */ #define GPC_CMC_PIN_STAT_CPU_MODE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_CPU_MODE_STAT_SHIFT)) & GPC_CMC_PIN_STAT_CPU_MODE_STAT_MASK) #define GPC_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK (0x80000000U) #define GPC_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT (31U) /*! DEBUG_WAKEUP_ACK_STAT - Debug wakeup acknowledge pin status */ #define GPC_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT)) & GPC_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK) /*! @} */ /*! @name CMC_IRQ_WAKEUP_MASK - IRQ wake-up mask register */ /*! @{ */ #define GPC_CMC_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_MASK (0xFFFFFFFFU) #define GPC_CMC_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_SHIFT (0U) /*! IRQ_WAKEUP_MASK - IRQ Wake-up mask */ #define GPC_CMC_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_SHIFT)) & GPC_CMC_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_MASK) /*! @} */ /* The count of GPC_CMC_IRQ_WAKEUP_MASK */ #define GPC_CMC_IRQ_WAKEUP_MASK_COUNT (12U) /*! @name CMC_NON_IRQ_WAKEUP_MASK - CMC non-IRQ wakeup mask */ /*! @{ */ #define GPC_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U) #define GPC_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U) /*! EVENT_WAKEUP_MASK - "1" means the event cannot wakeup CPU platform */ #define GPC_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK) #define GPC_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U) #define GPC_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U) /*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform */ #define GPC_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK) /*! @} */ /*! @name CMC_IRQ_WAKEUP_STAT - IRQ status register */ /*! @{ */ #define GPC_CMC_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_MASK (0xFFFFFFFFU) #define GPC_CMC_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_SHIFT (0U) /*! IRQ_WAKEUP_STAT - IRQ status */ #define GPC_CMC_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_SHIFT)) & GPC_CMC_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_MASK) /*! @} */ /* The count of GPC_CMC_IRQ_WAKEUP_STAT */ #define GPC_CMC_IRQ_WAKEUP_STAT_COUNT (12U) /*! @name CMC_NON_IRQ_WAKEUP_STAT - CMC non-IRQ wakeup status */ /*! @{ */ #define GPC_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U) #define GPC_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U) /*! EVENT_WAKEUP_STAT - Event wakeup status * 0b0..No event wakeup is requested * 0b1..Event wakeup is requested */ #define GPC_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK) #define GPC_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U) #define GPC_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U) /*! DEBUG_WAKEUP_STAT - Debug wakeup status * 0b0..No debug wakeup is requested * 0b1..Debug wakeup is requested */ #define GPC_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK) /*! @} */ /*! @name CMC_SLEEP_A55_HDSK_CTRL - CMC sleep A55_HDSK control */ /*! @{ */ #define GPC_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ #define GPC_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK) #define GPC_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK) #define GPC_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_SLEEP_A55_HDSK_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT)) & GPC_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_SLEEP_A55_HDSK_STAT - CMC sleep A55_HDSK status */ /*! @{ */ #define GPC_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_SHIFT)) & GPC_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_SLEEP_SSAR_CTRL - CMC sleep SSAR control */ /*! @{ */ #define GPC_CMC_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ #define GPC_CMC_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_SLEEP_SSAR_CTRL_STEP_CNT_MASK) #define GPC_CMC_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_SLEEP_SSAR_CTRL_CNT_MODE_MASK) #define GPC_CMC_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CMC_SLEEP_SSAR_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_SLEEP_SSAR_STAT - CMC sleep SSAR status */ /*! @{ */ #define GPC_CMC_SLEEP_SSAR_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_SSAR_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_SLEEP_SSAR_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SSAR_STAT_RSP_CNT_SHIFT)) & GPC_CMC_SLEEP_SSAR_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_SLEEP_RESET_CTRL - CMC sleep reset control */ /*! @{ */ #define GPC_CMC_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ #define GPC_CMC_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_SLEEP_RESET_CTRL_STEP_CNT_MASK) #define GPC_CMC_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_SLEEP_RESET_CTRL_CNT_MODE_MASK) #define GPC_CMC_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CMC_SLEEP_RESET_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_SLEEP_RESET_STAT - CMC sleep reset status */ /*! @{ */ #define GPC_CMC_SLEEP_RESET_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_RESET_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_SLEEP_RESET_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_RESET_STAT_RSP_CNT_SHIFT)) & GPC_CMC_SLEEP_RESET_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_SLEEP_SYSMAN_CTRL - CMC sleep Sysman control */ /*! @{ */ #define GPC_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ #define GPC_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_MASK) #define GPC_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_MASK) #define GPC_CMC_SLEEP_SYSMAN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_SLEEP_SYSMAN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT)) & GPC_CMC_SLEEP_SYSMAN_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_SLEEP_SYSMAN_STAT - CMC Sleep Sysman status */ /*! @{ */ #define GPC_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_SLEEP_SYSMAN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_SHIFT)) & GPC_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_WAKEUP_POWER_CTRL - CMC wakeup power control */ /*! @{ */ #define GPC_CMC_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ #define GPC_CMC_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_WAKEUP_POWER_CTRL_STEP_CNT_MASK) #define GPC_CMC_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_WAKEUP_POWER_CTRL_CNT_MODE_MASK) #define GPC_CMC_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CMC_WAKEUP_POWER_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_WAKEUP_POWER_STAT - CMC wakeup power status */ /*! @{ */ #define GPC_CMC_WAKEUP_POWER_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_POWER_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_WAKEUP_POWER_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_POWER_STAT_RSP_CNT_SHIFT)) & GPC_CMC_WAKEUP_POWER_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_WAKEUP_SSAR_CTRL - CMC wakeup SSAR control */ /*! @{ */ #define GPC_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ #define GPC_CMC_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_MASK) #define GPC_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_MASK) #define GPC_CMC_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CMC_WAKEUP_SSAR_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_WAKEUP_SSAR_STAT - CMC wakeup SSAR status */ /*! @{ */ #define GPC_CMC_WAKEUP_SSAR_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_SSAR_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_WAKEUP_SSAR_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SSAR_STAT_RSP_CNT_SHIFT)) & GPC_CMC_WAKEUP_SSAR_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_WAKEUP_A55_HDSK_CTRL - CMC wakeup A55_HDSK control */ /*! @{ */ #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK) #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK) #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT)) & GPC_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_WAKEUP_A55_HDSK_STAT - CMC wakeup A55_HDSK status */ /*! @{ */ #define GPC_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_SHIFT)) & GPC_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_WAKEUP_SYSMAN_CTRL - CMC wakeup Sysman control */ /*! @{ */ #define GPC_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ #define GPC_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_SHIFT)) & GPC_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_MASK) #define GPC_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - (keep==0 and invisible on customer RM)Count mode * 0b00..Counter disable mode: not use step counter, step completes once receiving step_done * 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT * 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_SHIFT)) & GPC_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_MASK) #define GPC_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step * 0b0..This step is enabled. * 0b1..This step is disabled. GPC will skip this step and not send any request. */ #define GPC_CMC_WAKEUP_SYSMAN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT)) & GPC_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_MASK) /*! @} */ /*! @name CMC_WAKEUP_SYSMAN_STAT - CMC wakeup Sysman status */ /*! @{ */ #define GPC_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_MASK (0xFFFFFFU) #define GPC_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_SHIFT (0U) /*! RSP_CNT - Response count, record the delay from step start to step_done received */ #define GPC_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_SHIFT)) & GPC_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_MASK) /*! @} */ /*! @name CMC_SYS_SLEEP_CTRL - CMC system sleep control */ /*! @{ */ #define GPC_CMC_SYS_SLEEP_CTRL_SS_WAIT_MASK (0x1U) #define GPC_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT (0U) /*! SS_WAIT - Request system sleep when CPU is in WAIT mode * 0b0..Do not request system sleep when CPU is in WAIT mode * 0b1..Request system sleep when CPU is in WAIT mode */ #define GPC_CMC_SYS_SLEEP_CTRL_SS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT)) & GPC_CMC_SYS_SLEEP_CTRL_SS_WAIT_MASK) #define GPC_CMC_SYS_SLEEP_CTRL_SS_STOP_MASK (0x2U) #define GPC_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT (1U) /*! SS_STOP - Request system sleep when CPU is in STOP mode * 0b0..Do not request system sleep when CPU is in STOP mode * 0b1..Request system sleep when CPU is in STOP mode */ #define GPC_CMC_SYS_SLEEP_CTRL_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT)) & GPC_CMC_SYS_SLEEP_CTRL_SS_STOP_MASK) #define GPC_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_MASK (0x4U) #define GPC_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT (2U) /*! SS_SUSPEND - Request system sleep when CPU is in SUSPEND mode * 0b0..Do not request system sleep when CPU is in SUSPEND mode * 0b1..Request system sleep when CPU is in SUSPEND mode */ #define GPC_CMC_SYS_SLEEP_CTRL_SS_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT)) & GPC_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_MASK) #define GPC_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_MASK (0x10000U) #define GPC_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT (16U) /*! SYS_SLEEP_BUSY - Indicates the CPU is busy entering system sleep mode. */ #define GPC_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT)) & GPC_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_MASK) #define GPC_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_MASK (0x20000U) #define GPC_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT (17U) /*! SYS_WAKEUP_BUSY - Indicates the CPU is busy exiting system sleep mode. */ #define GPC_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT)) & GPC_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_MASK) /*! @} */ /*! @name CMC_DEBUG - CMC debug */ /*! @{ */ #define GPC_CMC_DEBUG_PRETEND_SLEEP_MASK (0x1U) #define GPC_CMC_DEBUG_PRETEND_SLEEP_SHIFT (0U) /*! PRETEND_SLEEP - Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */ #define GPC_CMC_DEBUG_PRETEND_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CMC_DEBUG_PRETEND_SLEEP_SHIFT)) & GPC_CMC_DEBUG_PRETEND_SLEEP_MASK) /*! @} */ /*! * @} */ /* end of group GPC_Register_Masks */ /* GPC - Peripheral instance base addresses */ /** Peripheral GPC_CTRL_CM33 base address */ #define GPC_CTRL_CM33_BASE (0x44470000u) /** Peripheral GPC_CTRL_CM33 base pointer */ #define GPC_CTRL_CM33 ((GPC_Type *)GPC_CTRL_CM33_BASE) /** Peripheral GPC_CTRL_CM7 base address */ #define GPC_CTRL_CM7_BASE (0x44470800u) /** Peripheral GPC_CTRL_CM7 base pointer */ #define GPC_CTRL_CM7 ((GPC_Type *)GPC_CTRL_CM7_BASE) /** Peripheral GPC_CTRL_CA55_0 base address */ #define GPC_CTRL_CA55_0_BASE (0x44471000u) /** Peripheral GPC_CTRL_CA55_0 base pointer */ #define GPC_CTRL_CA55_0 ((GPC_Type *)GPC_CTRL_CA55_0_BASE) /** Peripheral GPC_CTRL_CA55_1 base address */ #define GPC_CTRL_CA55_1_BASE (0x44471800u) /** Peripheral GPC_CTRL_CA55_1 base pointer */ #define GPC_CTRL_CA55_1 ((GPC_Type *)GPC_CTRL_CA55_1_BASE) /** Peripheral GPC_CTRL_CA55_2 base address */ #define GPC_CTRL_CA55_2_BASE (0x44472000u) /** Peripheral GPC_CTRL_CA55_2 base pointer */ #define GPC_CTRL_CA55_2 ((GPC_Type *)GPC_CTRL_CA55_2_BASE) /** Peripheral GPC_CTRL_CA55_3 base address */ #define GPC_CTRL_CA55_3_BASE (0x44472800u) /** Peripheral GPC_CTRL_CA55_3 base pointer */ #define GPC_CTRL_CA55_3 ((GPC_Type *)GPC_CTRL_CA55_3_BASE) /** Peripheral GPC_CTRL_CA55_4 base address */ #define GPC_CTRL_CA55_4_BASE (0x44473000u) /** Peripheral GPC_CTRL_CA55_4 base pointer */ #define GPC_CTRL_CA55_4 ((GPC_Type *)GPC_CTRL_CA55_4_BASE) /** Peripheral GPC_CTRL_CA55_5 base address */ #define GPC_CTRL_CA55_5_BASE (0x44473800u) /** Peripheral GPC_CTRL_CA55_5 base pointer */ #define GPC_CTRL_CA55_5 ((GPC_Type *)GPC_CTRL_CA55_5_BASE) /** Peripheral GPC_CTRL_CA55_CLUSTER base address */ #define GPC_CTRL_CA55_CLUSTER_BASE (0x44474000u) /** Peripheral GPC_CTRL_CA55_CLUSTER base pointer */ #define GPC_CTRL_CA55_CLUSTER ((GPC_Type *)GPC_CTRL_CA55_CLUSTER_BASE) /** Array initializer of GPC peripheral base addresses */ #define GPC_BASE_ADDRS { GPC_CTRL_CM33_BASE, GPC_CTRL_CM7_BASE, GPC_CTRL_CA55_0_BASE, GPC_CTRL_CA55_1_BASE, GPC_CTRL_CA55_2_BASE, GPC_CTRL_CA55_3_BASE, GPC_CTRL_CA55_4_BASE, GPC_CTRL_CA55_5_BASE, GPC_CTRL_CA55_CLUSTER_BASE } /** Array initializer of GPC peripheral base pointers */ #define GPC_BASE_PTRS { GPC_CTRL_CM33, GPC_CTRL_CM7, GPC_CTRL_CA55_0, GPC_CTRL_CA55_1, GPC_CTRL_CA55_2, GPC_CTRL_CA55_3, GPC_CTRL_CA55_4, GPC_CTRL_CA55_5, GPC_CTRL_CA55_CLUSTER } /*! * @} */ /* end of group GPC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPC_GLOBAL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_GLOBAL_Peripheral_Access_Layer GPC_GLOBAL Peripheral Access Layer * @{ */ /** GPC_GLOBAL - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t GPC_GLOB_AUTHEN_CTRL; /**< GPC Global Authentication Control, offset: 0x4 */ uint8_t RESERVED_1[20]; __IO uint32_t GPC_MASTER; /**< GPC master CPU configuration, offset: 0x1C */ uint8_t RESERVED_2[32]; __IO uint32_t GPC_SYS_SLEEP; /**< GPC system sleep control, offset: 0x40 */ uint8_t RESERVED_3[12]; __IO uint32_t GPC_CPU_DOMAIN_ASSIGNMENT[9]; /**< GPC domain assignment, array offset: 0x50, array step: 0x4 */ uint8_t RESERVED_4[140]; __IO uint32_t GPC_PMIC_CTRL; /**< PMIC standby control from GPC, offset: 0x100 */ uint8_t RESERVED_5[4]; __IO uint32_t GPC_PMIC_STBY_ACK_CTRL; /**< PMIC standby acknowledge control, offset: 0x108 */ uint8_t RESERVED_6[244]; __IO uint32_t GPC_ROSC_CTRL; /**< RCOSC control, offset: 0x200 */ uint8_t RESERVED_7[4]; __IO uint32_t GPC_EFUSE_CTRL; /**< eFUSE control, offset: 0x208 */ __IO uint32_t GPC_ELE_HDSK_CTRL; /**< ELE Handshake control, offset: 0x20C */ } GPC_GLOBAL_Type; /* ---------------------------------------------------------------------------- -- GPC_GLOBAL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPC_GLOBAL_Register_Masks GPC_GLOBAL Register Masks * @{ */ /*! @name GPC_GLOB_AUTHEN_CTRL - GPC Global Authentication Control */ /*! @{ */ #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) /*! LOCK_CFG - Configuration lock * 0b0..The value of low power configuration fields are not locked. * 0b1..The value of low power configuration fields are locked. Refer to the function field of each gpc_global registers. */ #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_CFG_MASK) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_USER_MASK (0x100U) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_USER_SHIFT (8U) /*! USER - Allow user mode access * 0b0..Allow only privilege mode to access CPU mode control registers * 0b1..Allow both privilege and user mode to access CPU mode control registers */ #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_USER_SHIFT)) & GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_USER_MASK) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_NONSECURE_MASK (0x200U) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_NONSECURE_SHIFT (9U) /*! NONSECURE - Allow non-secure mode access * 0b0..Allow only secure mode to access CPU mode registers * 0b1..Allow both secure and non-secure mode to access CPU mode control registers. */ #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_NONSECURE_MASK) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_SETTING_MASK (0x800U) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_SETTING_SHIFT (11U) /*! LOCK_SETTING - Lock NONSECURE and USER * 0b0..NONSECURE and USER fields are not locked * 0b1..NONSECURE and USER fields are locked */ #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_SETTING_MASK) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - White list lock * 0b0..WHITE_LIST is not locked * 0b1..WHITE_LIST is locked */ #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_LOCK_LIST_MASK) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_GLOBAL_GPC_GLOB_AUTHEN_CTRL_WHITE_LIST_MASK) /*! @} */ /*! @name GPC_MASTER - GPC master CPU configuration */ /*! @{ */ #define GPC_GLOBAL_GPC_MASTER_CPU_MASTER_MASK (0x1FFU) #define GPC_GLOBAL_GPC_MASTER_CPU_MASTER_SHIFT (0U) /*! CPU_MASTER - Setting to 1 means CPU is the master CPU of its domain */ #define GPC_GLOBAL_GPC_MASTER_CPU_MASTER(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_MASTER_CPU_MASTER_SHIFT)) & GPC_GLOBAL_GPC_MASTER_CPU_MASTER_MASK) /*! @} */ /*! @name GPC_SYS_SLEEP - GPC system sleep control */ /*! @{ */ #define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU_DISABLE_MASK (0x1FF0000U) #define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU_DISABLE_SHIFT (16U) /*! FORCE_CPU_DISABLE - Force CPU into a system sleep status */ #define GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU_DISABLE_SHIFT)) & GPC_GLOBAL_GPC_SYS_SLEEP_FORCE_CPU_DISABLE_MASK) /*! @} */ /*! @name GPC_CPU_DOMAIN_ASSIGNMENT - GPC domain assignment */ /*! @{ */ #define GPC_GLOBAL_GPC_CPU_DOMAIN_ASSIGNMENT_CPU_DOMAIN_MASK (0xFU) #define GPC_GLOBAL_GPC_CPU_DOMAIN_ASSIGNMENT_CPU_DOMAIN_SHIFT (0U) /*! CPU_DOMAIN - CPU domain assignment * 0b0000..Domain 0 * 0b0001..Domain 1 * 0b0010..Domain 2 * 0b0011..Domain 3 * 0b0100..Domain 4 * 0b0101..Domain 5 * 0b0110..Domain 6 * 0b0111..Domain 7 * 0b1000..Domain 8 * 0b1001..Domain 9 * 0b1010..Domain 10 * 0b1011..Domain 11 * 0b1100..Domain 12 * 0b1101..Domain 13 * 0b1110..Domain 14 * 0b1111..Domain 15 */ #define GPC_GLOBAL_GPC_CPU_DOMAIN_ASSIGNMENT_CPU_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_CPU_DOMAIN_ASSIGNMENT_CPU_DOMAIN_SHIFT)) & GPC_GLOBAL_GPC_CPU_DOMAIN_ASSIGNMENT_CPU_DOMAIN_MASK) /*! @} */ /* The count of GPC_GLOBAL_GPC_CPU_DOMAIN_ASSIGNMENT */ #define GPC_GLOBAL_GPC_CPU_DOMAIN_ASSIGNMENT_COUNT (9U) /*! @name GPC_PMIC_CTRL - PMIC standby control from GPC */ /*! @{ */ #define GPC_GLOBAL_GPC_PMIC_CTRL_PMIC_STBY_EN_MASK (0x1U) #define GPC_GLOBAL_GPC_PMIC_CTRL_PMIC_STBY_EN_SHIFT (0U) /*! PMIC_STBY_EN - Assert the PMIC_STBY_REQ when system sleep * 0b1..Enter PMIC standby request * 0b0..Exit PMIC standby request */ #define GPC_GLOBAL_GPC_PMIC_CTRL_PMIC_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_PMIC_CTRL_PMIC_STBY_EN_SHIFT)) & GPC_GLOBAL_GPC_PMIC_CTRL_PMIC_STBY_EN_MASK) /*! @} */ /*! @name GPC_PMIC_STBY_ACK_CTRL - PMIC standby acknowledge control */ /*! @{ */ #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK (0xFFFU) #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT (0U) /*! STBY_ON_CNT_CFG - PMIC standby on acknowledge count configure. Usage depends on STBY_ON_CNT_MODE. Locked by LOCK_CFG field. */ #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT)) & GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK) #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK (0xC000U) #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT (14U) /*! STBY_ON_CNT_MODE - PMIC standby on acknowledge count mode. Locked by LOCK_CFG field. * 0b00..Finish the process once pmic_standby signal changes * 0b01..Finish the process once getting acknowledge from PMIC * 0b10..Ignore PMIC acknowledge, the delay counter starts to count once pmic_standby changes * 0b11..Time out mode, the counter starts to count once pmic_standby changes, then finishes the process when * either acknowledge received or counting to CNT_CFG value */ #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT)) & GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK) #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK (0xFFF0000U) #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT (16U) /*! STBY_OFF_CNT_CFG - PMIC standby off acknowledge count configure. Usage depends on STBY_OFF_CNT_MODE. Locked by LOCK_CFG field. */ #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT)) & GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK) #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK (0xC0000000U) #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT (30U) /*! STBY_OFF_CNT_MODE - PMIC standby off acknowledge count mode. Locked by LOCK_CFG field. * 0b00..Finish the process once pmic_standby signal changes * 0b01..Finish the process once getting acknowledge from PMIC * 0b10..Ignore PMIC acknowledge, the delay counter starts to count once pmic_standby changes * 0b11..Time out mode, the counter starts to count once pmic_standby changes, then finishes the process when * either acknowledge received or counting to CNT_CFG value */ #define GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT)) & GPC_GLOBAL_GPC_PMIC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK) /*! @} */ /*! @name GPC_ROSC_CTRL - RCOSC control */ /*! @{ */ #define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK (0x1U) #define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT (0U) /*! ROSC_OFF_EN - Shut off the 24 MHz RCOSC clock when system sleep * 0b0..Keep 24 MHz ROSC clock running during system sleep * 0b1..Shut off 24 MHz ROSC clock during system sleep */ #define GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_SHIFT)) & GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK) /*! @} */ /*! @name GPC_EFUSE_CTRL - eFUSE control */ /*! @{ */ #define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_MASK (0x1U) #define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_SHIFT (0U) /*! EFUSE_PD_EN - eFUSE power down enable * 0b0..Do not Power Down efuse during system sleep * 0b1..Power Down efuse during system sleep */ #define GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_SHIFT)) & GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_MASK) /*! @} */ /*! @name GPC_ELE_HDSK_CTRL - ELE Handshake control */ /*! @{ */ #define GPC_GLOBAL_GPC_ELE_HDSK_CTRL_ELE_HDSK_EN_MASK (0x1U) #define GPC_GLOBAL_GPC_ELE_HDSK_CTRL_ELE_HDSK_EN_SHIFT (0U) /*! ELE_HDSK_EN - GPC-to-ELE handshake enable * 0b0..Disable GPC-to-ELE handshake during system sleep sequence * 0b1..Enable GPC-to-ELE handshake during system sleep sequence */ #define GPC_GLOBAL_GPC_ELE_HDSK_CTRL_ELE_HDSK_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_GLOBAL_GPC_ELE_HDSK_CTRL_ELE_HDSK_EN_SHIFT)) & GPC_GLOBAL_GPC_ELE_HDSK_CTRL_ELE_HDSK_EN_MASK) /*! @} */ /*! * @} */ /* end of group GPC_GLOBAL_Register_Masks */ /* GPC_GLOBAL - Peripheral instance base addresses */ /** Peripheral CCMSRCGPC__GPC__GPC_GLOBAL base address */ #define CCMSRCGPC__GPC__GPC_GLOBAL_BASE (0x44474800u) /** Peripheral CCMSRCGPC__GPC__GPC_GLOBAL base pointer */ #define CCMSRCGPC__GPC__GPC_GLOBAL ((GPC_GLOBAL_Type *)CCMSRCGPC__GPC__GPC_GLOBAL_BASE) /** Array initializer of GPC_GLOBAL peripheral base addresses */ #define GPC_GLOBAL_BASE_ADDRS { CCMSRCGPC__GPC__GPC_GLOBAL_BASE } /** Array initializer of GPC_GLOBAL peripheral base pointers */ #define GPC_GLOBAL_BASE_PTRS { CCMSRCGPC__GPC__GPC_GLOBAL } /*! * @} */ /* end of group GPC_GLOBAL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPU_BLK_CTRL_GPUMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_BLK_CTRL_GPUMIX_Peripheral_Access_Layer GPU_BLK_CTRL_GPUMIX Peripheral Access Layer * @{ */ /** GPU_BLK_CTRL_GPUMIX - Register Layout Typedef */ typedef struct { __IO uint32_t STRIPING_GRANULE; /**< Striping Granule Register, offset: 0x0 */ __IO uint32_t TEXFMTENABLE; /**< TEXFMT Enable Register, offset: 0x4 */ __IO uint32_t GPURESET; /**< GPU Reset Release Register, offset: 0x8 */ } GPU_BLK_CTRL_GPUMIX_Type; /* ---------------------------------------------------------------------------- -- GPU_BLK_CTRL_GPUMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_BLK_CTRL_GPUMIX_Register_Masks GPU_BLK_CTRL_GPUMIX Register Masks * @{ */ /*! @name STRIPING_GRANULE - Striping Granule Register */ /*! @{ */ #define GPU_BLK_CTRL_GPUMIX_STRIPING_GRANULE_STRIPING_GRANULE_MASK (0xFU) #define GPU_BLK_CTRL_GPUMIX_STRIPING_GRANULE_STRIPING_GRANULE_SHIFT (0U) /*! STRIPING_GRANULE - Striping Granule */ #define GPU_BLK_CTRL_GPUMIX_STRIPING_GRANULE_STRIPING_GRANULE(x) (((uint32_t)(((uint32_t)(x)) << GPU_BLK_CTRL_GPUMIX_STRIPING_GRANULE_STRIPING_GRANULE_SHIFT)) & GPU_BLK_CTRL_GPUMIX_STRIPING_GRANULE_STRIPING_GRANULE_MASK) /*! @} */ /*! @name TEXFMTENABLE - TEXFMT Enable Register */ /*! @{ */ #define GPU_BLK_CTRL_GPUMIX_TEXFMTENABLE_TEXFMTENABLE_MASK (0xFFFFFFFFU) #define GPU_BLK_CTRL_GPUMIX_TEXFMTENABLE_TEXFMTENABLE_SHIFT (0U) /*! TEXFMTENABLE - TEXFMT Enable */ #define GPU_BLK_CTRL_GPUMIX_TEXFMTENABLE_TEXFMTENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPU_BLK_CTRL_GPUMIX_TEXFMTENABLE_TEXFMTENABLE_SHIFT)) & GPU_BLK_CTRL_GPUMIX_TEXFMTENABLE_TEXFMTENABLE_MASK) /*! @} */ /*! @name GPURESET - GPU Reset Release Register */ /*! @{ */ #define GPU_BLK_CTRL_GPUMIX_GPURESET_GPURR_MASK (0x1U) #define GPU_BLK_CTRL_GPUMIX_GPURESET_GPURR_SHIFT (0U) /*! GPURR - GPU Reset Release */ #define GPU_BLK_CTRL_GPUMIX_GPURESET_GPURR(x) (((uint32_t)(((uint32_t)(x)) << GPU_BLK_CTRL_GPUMIX_GPURESET_GPURR_SHIFT)) & GPU_BLK_CTRL_GPUMIX_GPURESET_GPURR_MASK) /*! @} */ /*! * @} */ /* end of group GPU_BLK_CTRL_GPUMIX_Register_Masks */ /* GPU_BLK_CTRL_GPUMIX - Peripheral instance base addresses */ /** Peripheral GPU__BLK_CTRL_GPUMIX base address */ #define GPU__BLK_CTRL_GPUMIX_BASE (0x4D810000u) /** Peripheral GPU__BLK_CTRL_GPUMIX base pointer */ #define GPU__BLK_CTRL_GPUMIX ((GPU_BLK_CTRL_GPUMIX_Type *)GPU__BLK_CTRL_GPUMIX_BASE) /** Array initializer of GPU_BLK_CTRL_GPUMIX peripheral base addresses */ #define GPU_BLK_CTRL_GPUMIX_BASE_ADDRS { GPU__BLK_CTRL_GPUMIX_BASE } /** Array initializer of GPU_BLK_CTRL_GPUMIX peripheral base pointers */ #define GPU_BLK_CTRL_GPUMIX_BASE_PTRS { GPU__BLK_CTRL_GPUMIX } /*! * @} */ /* end of group GPU_BLK_CTRL_GPUMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPU_MALI_DOORBELLS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_DOORBELLS_Peripheral_Access_Layer GPU_MALI_DOORBELLS Peripheral Access Layer * @{ */ /** GPU_MALI_DOORBELLS - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x10000 */ __O uint32_t DOORBELL; /**< DOORBELL, array offset: 0x0, array step: 0x10000 */ uint8_t RESERVED_0[65532]; } DOORBELL[64]; } GPU_MALI_DOORBELLS_Type; /* ---------------------------------------------------------------------------- -- GPU_MALI_DOORBELLS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_DOORBELLS_Register_Masks GPU_MALI_DOORBELLS Register Masks * @{ */ /*! @name DOORBELL - DOORBELL */ /*! @{ */ #define GPU_MALI_DOORBELLS_DOORBELL_MASK_MASK (0xFFFFFFFFU) #define GPU_MALI_DOORBELLS_DOORBELL_MASK_SHIFT (0U) /*! MASK - MASK */ #define GPU_MALI_DOORBELLS_DOORBELL_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_DOORBELLS_DOORBELL_MASK_SHIFT)) & GPU_MALI_DOORBELLS_DOORBELL_MASK_MASK) /*! @} */ /* The count of GPU_MALI_DOORBELLS_DOORBELL */ #define GPU_MALI_DOORBELLS_DOORBELL_COUNT (64U) /*! * @} */ /* end of group GPU_MALI_DOORBELLS_Register_Masks */ /* GPU_MALI_DOORBELLS - Peripheral instance base addresses */ /** Peripheral GPU__REG__GPU_MALI_DOORBELLS base address */ #define GPU__REG__GPU_MALI_DOORBELLS_BASE (0x4D980000u) /** Peripheral GPU__REG__GPU_MALI_DOORBELLS base pointer */ #define GPU__REG__GPU_MALI_DOORBELLS ((GPU_MALI_DOORBELLS_Type *)GPU__REG__GPU_MALI_DOORBELLS_BASE) /** Array initializer of GPU_MALI_DOORBELLS peripheral base addresses */ #define GPU_MALI_DOORBELLS_BASE_ADDRS { GPU__REG__GPU_MALI_DOORBELLS_BASE } /** Array initializer of GPU_MALI_DOORBELLS peripheral base pointers */ #define GPU_MALI_DOORBELLS_BASE_PTRS { GPU__REG__GPU_MALI_DOORBELLS } /*! * @} */ /* end of group GPU_MALI_DOORBELLS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPU_MALI_GPU_REGISTERS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_GPU_REGISTERS_Peripheral_Access_Layer GPU_MALI_GPU_REGISTERS Peripheral Access Layer * @{ */ /** GPU_MALI_GPU_REGISTERS - Register Layout Typedef */ typedef struct { __I uint32_t GPU_ID; /**< GPU_ID, offset: 0x0 */ __I uint32_t L2_FEATURES; /**< L2_FEATURES, offset: 0x4 */ __I uint32_t CORE_FEATURES; /**< CORE_FEATURES, offset: 0x8 */ __I uint32_t TILER_FEATURES; /**< TILER_FEATURES, offset: 0xC */ __I uint32_t MEM_FEATURES; /**< MEM_FEATURES, offset: 0x10 */ __I uint32_t MMU_FEATURES; /**< MMU_FEATURES, offset: 0x14 */ __I uint32_t AS_PRESENT; /**< AS_PRESENT, offset: 0x18 */ __I uint32_t CSF_ID; /**< CSF_ID, offset: 0x1C */ __IO uint32_t GPU_IRQ_RAWSTAT; /**< GPU_IRQ_RAWSTAT, offset: 0x20 */ __IO uint32_t GPU_IRQ_CLEAR; /**< GPU_IRQ_CLEAR, offset: 0x24 */ __IO uint32_t GPU_IRQ_MASK; /**< GPU_IRQ_MASK, offset: 0x28 */ __I uint32_t GPU_IRQ_STATUS; /**< GPU_IRQ_STATUS, offset: 0x2C */ __O uint32_t GPU_COMMAND; /**< GPU_COMMAND, offset: 0x30 */ __I uint32_t GPU_STATUS; /**< GPU_STATUS, offset: 0x34 */ uint8_t RESERVED_0[4]; __I uint32_t GPU_FAULTSTATUS; /**< GPU_FAULTSTATUS, offset: 0x3C */ __I uint32_t GPU_FAULTADDRESS_LO; /**< GPU_FAULTADDRESS_LO, offset: 0x40 */ __I uint32_t GPU_FAULTADDRESS_HI; /**< GPU_FAULTADDRESS_HI, offset: 0x44 */ __IO uint32_t L2_CONFIG; /**< L2_CONFIG, offset: 0x48 */ uint8_t RESERVED_1[4]; __O uint32_t PWR_KEY; /**< PWR_KEY, offset: 0x50 */ __IO uint32_t PWR_OVERRIDE0; /**< PWR_OVERRIDE0, offset: 0x54 */ __IO uint32_t PWR_OVERRIDE1; /**< PWR_OVERRIDE1, offset: 0x58 */ uint8_t RESERVED_2[44]; __IO uint32_t TIMESTAMP_OFFSET_LO; /**< TIMESTAMP_OFFSET_LO, offset: 0x88 */ __IO uint32_t TIMESTAMP_OFFSET_HI; /**< TIMESTAMP_OFFSET_HI, offset: 0x8C */ __I uint32_t CYCLE_COUNT_LO; /**< CYCLE_COUNT_LO, offset: 0x90 */ __I uint32_t CYCLE_COUNT_HI; /**< CYCLE_COUNT_HI, offset: 0x94 */ __I uint32_t TIMESTAMP_LO; /**< TIMESTAMP_LO, offset: 0x98 */ __I uint32_t TIMESTAMP_HI; /**< TIMESTAMP_HI, offset: 0x9C */ __I uint32_t THREAD_MAX_THREADS; /**< THREAD_MAX_THREADS, offset: 0xA0 */ __I uint32_t THREAD_MAX_WORKGROUP_SIZE; /**< THREAD_MAX_WORKGROUP_SIZE, offset: 0xA4 */ __I uint32_t THREAD_MAX_BARRIER_SIZE; /**< THREAD_MAX_BARRIER_SIZE, offset: 0xA8 */ __I uint32_t THREAD_FEATURES; /**< THREAD_FEATURES, offset: 0xAC */ __I uint32_t TEXTURE_FEATURES_0; /**< TEXTURE_FEATURES_0, offset: 0xB0 */ __I uint32_t TEXTURE_FEATURES_1; /**< TEXTURE_FEATURES_1, offset: 0xB4 */ __I uint32_t TEXTURE_FEATURES_2; /**< TEXTURE_FEATURES_2, offset: 0xB8 */ __I uint32_t TEXTURE_FEATURES_3; /**< TEXTURE_FEATURES_3, offset: 0xBC */ uint8_t RESERVED_3[64]; __I uint32_t SHADER_PRESENT_LO; /**< SHADER_PRESENT_LO, offset: 0x100 */ __I uint32_t SHADER_PRESENT_HI; /**< SHADER_PRESENT_HI, offset: 0x104 */ uint8_t RESERVED_4[8]; __I uint32_t TILER_PRESENT_LO; /**< TILER_PRESENT_LO, offset: 0x110 */ __I uint32_t TILER_PRESENT_HI; /**< TILER_PRESENT_HI, offset: 0x114 */ uint8_t RESERVED_5[8]; __I uint32_t L2_PRESENT_LO; /**< L2_PRESENT_LO, offset: 0x120 */ __I uint32_t L2_PRESENT_HI; /**< L2_PRESENT_HI, offset: 0x124 */ uint8_t RESERVED_6[24]; __I uint32_t SHADER_READY_LO; /**< SHADER_READY_LO, offset: 0x140 */ __I uint32_t SHADER_READY_HI; /**< SHADER_READY_HI, offset: 0x144 */ uint8_t RESERVED_7[8]; __I uint32_t TILER_READY_LO; /**< TILER_READY_LO, offset: 0x150 */ __I uint32_t TILER_READY_HI; /**< TILER_READY_HI, offset: 0x154 */ uint8_t RESERVED_8[8]; __I uint32_t L2_READY_LO; /**< L2_READY_LO, offset: 0x160 */ __I uint32_t L2_READY_HI; /**< L2_READY_HI, offset: 0x164 */ uint8_t RESERVED_9[24]; __O uint32_t SHADER_PWRON_LO; /**< SHADER_PWRON_LO, offset: 0x180 */ __O uint32_t SHADER_PWRON_HI; /**< SHADER_PWRON_HI, offset: 0x184 */ uint8_t RESERVED_10[8]; __O uint32_t TILER_PWRON_LO; /**< TILER_PWRON_LO, offset: 0x190 */ __O uint32_t TILER_PWRON_HI; /**< TILER_PWRON_HI, offset: 0x194 */ uint8_t RESERVED_11[8]; __O uint32_t L2_PWRON_LO; /**< L2_PWRON_LO, offset: 0x1A0 */ __O uint32_t L2_PWRON_HI; /**< L2_PWRON_HI, offset: 0x1A4 */ uint8_t RESERVED_12[24]; __O uint32_t SHADER_PWROFF_LO; /**< SHADER_PWROFF_LO, offset: 0x1C0 */ __O uint32_t SHADER_PWROFF_HI; /**< SHADER_PWROFF_HI, offset: 0x1C4 */ uint8_t RESERVED_13[8]; __O uint32_t TILER_PWROFF_LO; /**< TILER_PWROFF_LO, offset: 0x1D0 */ __O uint32_t TILER_PWROFF_HI; /**< TILER_PWROFF_HI, offset: 0x1D4 */ uint8_t RESERVED_14[8]; __O uint32_t L2_PWROFF_LO; /**< L2_PWROFF_LO, offset: 0x1E0 */ __O uint32_t L2_PWROFF_HI; /**< L2_PWROFF_HI, offset: 0x1E4 */ uint8_t RESERVED_15[24]; __I uint32_t SHADER_PWRTRANS_LO; /**< SHADER_PWRTRANS_LO, offset: 0x200 */ __I uint32_t SHADER_PWRTRANS_HI; /**< SHADER_PWRTRANS_HI, offset: 0x204 */ uint8_t RESERVED_16[8]; __I uint32_t TILER_PWRTRANS_LO; /**< TILER_PWRTRANS_LO, offset: 0x210 */ __I uint32_t TILER_PWRTRANS_HI; /**< TILER_PWRTRANS_HI, offset: 0x214 */ uint8_t RESERVED_17[8]; __I uint32_t L2_PWRTRANS_LO; /**< L2_PWRTRANS_LO, offset: 0x220 */ __I uint32_t L2_PWRTRANS_HI; /**< L2_PWRTRANS_HI, offset: 0x224 */ uint8_t RESERVED_18[24]; __I uint32_t SHADER_PWRACTIVE_LO; /**< SHADER_PWRACTIVE_LO, offset: 0x240 */ __I uint32_t SHADER_PWRACTIVE_HI; /**< SHADER_PWRACTIVE_HI, offset: 0x244 */ uint8_t RESERVED_19[8]; __I uint32_t TILER_PWRACTIVE_LO; /**< TILER_PWRACTIVE_LO, offset: 0x250 */ __I uint32_t TILER_PWRACTIVE_HI; /**< TILER_PWRACTIVE_HI, offset: 0x254 */ uint8_t RESERVED_20[8]; __I uint32_t L2_PWRACTIVE_LO; /**< L2_PWRACTIVE_LO, offset: 0x260 */ __I uint32_t L2_PWRACTIVE_HI; /**< L2_PWRACTIVE_HI, offset: 0x264 */ uint8_t RESERVED_21[24]; __I uint32_t REVIDR; /**< REVIDR, offset: 0x280 */ uint8_t RESERVED_22[124]; __I uint32_t COHERENCY_FEATURES; /**< COHERENCY_FEATURES, offset: 0x300 */ __IO uint32_t COHERENCY_ENABLE; /**< COHERENCY_ENABLE, offset: 0x304 */ uint8_t RESERVED_23[1016]; __IO uint32_t MCU_CONTROL; /**< MCU_CONTROL, offset: 0x700 */ __I uint32_t MCU_STATUS; /**< MCU_STATUS, offset: 0x704 */ uint8_t RESERVED_24[2296]; __IO uint32_t JOB_IRQ_RAWSTAT; /**< JOB_IRQ_RAWSTAT, offset: 0x1000 */ __O uint32_t JOB_IRQ_CLEAR; /**< JOB_IRQ_CLEAR, offset: 0x1004 */ __IO uint32_t JOB_IRQ_MASK; /**< JOB_IRQ_MASK, offset: 0x1008 */ __I uint32_t JOB_IRQ_STATUS; /**< JOB_IRQ_STATUS, offset: 0x100C */ uint8_t RESERVED_25[4080]; __IO uint32_t IRQ_RAWSTAT; /**< IRQ_RAWSTAT, offset: 0x2000 */ __O uint32_t IRQ_CLEAR; /**< IRQ_CLEAR, offset: 0x2004 */ __IO uint32_t IRQ_MASK; /**< IRQ_MASK, offset: 0x2008 */ __I uint32_t IRQ_STATUS; /**< IRQ_STATUS, offset: 0x200C */ uint8_t RESERVED_26[1008]; struct { /* offset: 0x2400, array step: 0x40 */ __IO uint32_t TRANSTAB_LO; /**< TRANSTAB_LO, array offset: 0x2400, array step: 0x40 */ __IO uint32_t TRANSTAB_HI; /**< TRANSTAB_HI, array offset: 0x2404, array step: 0x40 */ __IO uint32_t MEMATTR_LO; /**< MEMATTR_LO, array offset: 0x2408, array step: 0x40 */ __IO uint32_t MEMATTR_HI; /**< MEMATTR_HI, array offset: 0x240C, array step: 0x40 */ __IO uint32_t LOCKADDR_LO; /**< LOCKADDR_LO, array offset: 0x2410, array step: 0x40 */ __IO uint32_t LOCKADDR_HI; /**< LOCKADDR_HI, array offset: 0x2414, array step: 0x40 */ __O uint32_t COMMAND; /**< COMMAND, array offset: 0x2418, array step: 0x40 */ __I uint32_t FAULTSTATUS; /**< FAULTSTATUS, array offset: 0x241C, array step: 0x40 */ __I uint32_t FAULTADDRESS_LO; /**< FAULTADDRESS_LO, array offset: 0x2420, array step: 0x40 */ __I uint32_t FAULTADDRESS_HI; /**< FAULTADDRESS_HI, array offset: 0x2424, array step: 0x40 */ __I uint32_t STATUS; /**< STATUS, array offset: 0x2428, array step: 0x40 */ uint8_t RESERVED_0[4]; __IO uint32_t TRANSCFG_LO; /**< TRANSCFG_LO, array offset: 0x2430, array step: 0x40 */ __IO uint32_t TRANSCFG_HI; /**< TRANSCFG_HI, array offset: 0x2434, array step: 0x40 */ __I uint32_t FAULTEXTRA_LO; /**< FAULTEXTRA_LO, array offset: 0x2438, array step: 0x40 */ __I uint32_t FAULTEXTRA_HI; /**< FAULTEXTRA_HI, array offset: 0x243C, array step: 0x40 */ } AS[8]; } GPU_MALI_GPU_REGISTERS_Type; /* ---------------------------------------------------------------------------- -- GPU_MALI_GPU_REGISTERS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_GPU_REGISTERS_Register_Masks GPU_MALI_GPU_REGISTERS Register Masks * @{ */ /*! @name GPU_ID - GPU_ID */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_STATUS_MASK (0xFU) #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_STATUS_SHIFT (0U) /*! VERSION_STATUS - VERSION_STATUS * 0b0000.. * 0b0001.. */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_STATUS_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_STATUS_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MINOR_MASK (0xFF0U) #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MINOR_SHIFT (4U) /*! VERSION_MINOR - VERSION_MINOR */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MINOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MINOR_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MAJOR_MASK (0xF000U) #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MAJOR_SHIFT (12U) /*! VERSION_MAJOR - VERSION_MAJOR */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MAJOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_ID_VERSION_MAJOR_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_ID_PRODUCT_MAJOR_MASK (0xF0000U) #define GPU_MALI_GPU_REGISTERS_GPU_ID_PRODUCT_MAJOR_SHIFT (16U) /*! PRODUCT_MAJOR - PRODUCT_MAJOR */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_PRODUCT_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_ID_PRODUCT_MAJOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_ID_PRODUCT_MAJOR_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_REV_MASK (0xF00000U) #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_REV_SHIFT (20U) /*! ARCH_REV - ARCH_REV */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_REV(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_REV_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_REV_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MINOR_MASK (0xF000000U) #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MINOR_SHIFT (24U) /*! ARCH_MINOR - ARCH_MINOR */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MINOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MINOR_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MAJOR_MASK (0xF0000000U) #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MAJOR_SHIFT (28U) /*! ARCH_MAJOR - ARCH_MAJOR */ #define GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MAJOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_ID_ARCH_MAJOR_MASK) /*! @} */ /*! @name L2_FEATURES - L2_FEATURES */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_LINE_SIZE_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_LINE_SIZE_SHIFT (0U) /*! LINE_SIZE - LINE_SIZE */ #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_LINE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_FEATURES_LINE_SIZE_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_FEATURES_LINE_SIZE_MASK) #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_ASSOCIATIVITY_MASK (0xFF00U) #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_ASSOCIATIVITY_SHIFT (8U) /*! ASSOCIATIVITY - ASSOCIATIVITY */ #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_ASSOCIATIVITY(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_FEATURES_ASSOCIATIVITY_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_FEATURES_ASSOCIATIVITY_MASK) #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_CACHE_SIZE_MASK (0xFF0000U) #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_CACHE_SIZE_SHIFT (16U) /*! CACHE_SIZE - CACHE_SIZE */ #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_CACHE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_FEATURES_CACHE_SIZE_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_FEATURES_CACHE_SIZE_MASK) #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_BUS_WIDTH_MASK (0xFF000000U) #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_BUS_WIDTH_SHIFT (24U) /*! BUS_WIDTH - BUS_WIDTH */ #define GPU_MALI_GPU_REGISTERS_L2_FEATURES_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_FEATURES_BUS_WIDTH_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_FEATURES_BUS_WIDTH_MASK) /*! @} */ /*! @name CORE_FEATURES - CORE_FEATURES */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_CORE_FEATURES_CORE_VARIANT_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_CORE_FEATURES_CORE_VARIANT_SHIFT (0U) /*! CORE_VARIANT - CORE_VARIANT * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. */ #define GPU_MALI_GPU_REGISTERS_CORE_FEATURES_CORE_VARIANT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CORE_FEATURES_CORE_VARIANT_SHIFT)) & GPU_MALI_GPU_REGISTERS_CORE_FEATURES_CORE_VARIANT_MASK) #define GPU_MALI_GPU_REGISTERS_CORE_FEATURES_reserved_word0_bit8_width24_MASK (0xFFFFFF00U) #define GPU_MALI_GPU_REGISTERS_CORE_FEATURES_reserved_word0_bit8_width24_SHIFT (8U) /*! reserved_word0_bit8_width24 - reserved_word0_bit8_width24 */ #define GPU_MALI_GPU_REGISTERS_CORE_FEATURES_reserved_word0_bit8_width24(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CORE_FEATURES_reserved_word0_bit8_width24_SHIFT)) & GPU_MALI_GPU_REGISTERS_CORE_FEATURES_reserved_word0_bit8_width24_MASK) /*! @} */ /*! @name TILER_FEATURES - TILER_FEATURES */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_BIN_SIZE_MASK (0x3FU) #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_BIN_SIZE_SHIFT (0U) /*! BIN_SIZE - BIN_SIZE */ #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_BIN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_FEATURES_BIN_SIZE_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_FEATURES_BIN_SIZE_MASK) #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit6_width2_MASK (0xC0U) #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit6_width2_SHIFT (6U) /*! reserved_word0_bit6_width2 - reserved_word0_bit6_width2 */ #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit6_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit6_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit6_width2_MASK) #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_MAX_LEVELS_MASK (0xF00U) #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_MAX_LEVELS_SHIFT (8U) /*! MAX_LEVELS - MAX_LEVELS */ #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_MAX_LEVELS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_FEATURES_MAX_LEVELS_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_FEATURES_MAX_LEVELS_MASK) #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit12_width20_MASK (0xFFFFF000U) #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit12_width20_SHIFT (12U) /*! reserved_word0_bit12_width20 - reserved_word0_bit12_width20 */ #define GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit12_width20(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit12_width20_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_FEATURES_reserved_word0_bit12_width20_MASK) /*! @} */ /*! @name MEM_FEATURES - MEM_FEATURES */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_CORE_GROUP_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_CORE_GROUP_SHIFT (0U) /*! COHERENT_CORE_GROUP - COHERENT_CORE_GROUP */ #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_CORE_GROUP(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_CORE_GROUP_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_CORE_GROUP_MASK) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_SUPER_GROUP_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_SUPER_GROUP_SHIFT (1U) /*! COHERENT_SUPER_GROUP - COHERENT_SUPER_GROUP */ #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_SUPER_GROUP(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_SUPER_GROUP_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEM_FEATURES_COHERENT_SUPER_GROUP_MASK) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit2_width6_MASK (0xFCU) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit2_width6_SHIFT (2U) /*! reserved_word0_bit2_width6 - reserved_word0_bit2_width6 */ #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit2_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit2_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit2_width6_MASK) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_L2_SLICES_MASK (0xF00U) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_L2_SLICES_SHIFT (8U) /*! L2_SLICES - L2_SLICES */ #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_L2_SLICES(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEM_FEATURES_L2_SLICES_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEM_FEATURES_L2_SLICES_MASK) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit12_width20_MASK (0xFFFFF000U) #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit12_width20_SHIFT (12U) /*! reserved_word0_bit12_width20 - reserved_word0_bit12_width20 */ #define GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit12_width20(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit12_width20_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEM_FEATURES_reserved_word0_bit12_width20_MASK) /*! @} */ /*! @name MMU_FEATURES - MMU_FEATURES */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_VA_BITS_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_VA_BITS_SHIFT (0U) /*! VA_BITS - VA_BITS */ #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_VA_BITS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MMU_FEATURES_VA_BITS_SHIFT)) & GPU_MALI_GPU_REGISTERS_MMU_FEATURES_VA_BITS_MASK) #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_PA_BITS_MASK (0xFF00U) #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_PA_BITS_SHIFT (8U) /*! PA_BITS - PA_BITS */ #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_PA_BITS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MMU_FEATURES_PA_BITS_SHIFT)) & GPU_MALI_GPU_REGISTERS_MMU_FEATURES_PA_BITS_MASK) #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_reserved_word0_bit16_width16_MASK (0xFFFF0000U) #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_reserved_word0_bit16_width16_SHIFT (16U) /*! reserved_word0_bit16_width16 - reserved_word0_bit16_width16 */ #define GPU_MALI_GPU_REGISTERS_MMU_FEATURES_reserved_word0_bit16_width16(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MMU_FEATURES_reserved_word0_bit16_width16_SHIFT)) & GPU_MALI_GPU_REGISTERS_MMU_FEATURES_reserved_word0_bit16_width16_MASK) /*! @} */ /*! @name AS_PRESENT - AS_PRESENT */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_AS_PRESENT_present_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_AS_PRESENT_present_SHIFT (0U) /*! present - present */ #define GPU_MALI_GPU_REGISTERS_AS_PRESENT_present(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_AS_PRESENT_present_SHIFT)) & GPU_MALI_GPU_REGISTERS_AS_PRESENT_present_MASK) /*! @} */ /*! @name CSF_ID - CSF_ID */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_REV_MASK (0xFU) #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_REV_SHIFT (0U) /*! MCU_REV - MCU_REV */ #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_REV(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_REV_SHIFT)) & GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_REV_MASK) #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MINOR_MASK (0x3F0U) #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MINOR_SHIFT (4U) /*! MCU_MINOR - MCU_MINOR */ #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MINOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MINOR_MASK) #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MAJOR_MASK (0xFC00U) #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MAJOR_SHIFT (10U) /*! MCU_MAJOR - MCU_MAJOR */ #define GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MAJOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_CSF_ID_MCU_MAJOR_MASK) #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_REV_MASK (0xF0000U) #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_REV_SHIFT (16U) /*! CSHW_REV - CSHW_REV */ #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_REV(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_REV_SHIFT)) & GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_REV_MASK) #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MINOR_MASK (0x3F00000U) #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MINOR_SHIFT (20U) /*! CSHW_MINOR - CSHW_MINOR */ #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MINOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MINOR_MASK) #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MAJOR_MASK (0xFC000000U) #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MAJOR_SHIFT (26U) /*! CSHW_MAJOR - CSHW_MAJOR */ #define GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MAJOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_CSF_ID_CSHW_MAJOR_MASK) /*! @} */ /*! @name GPU_IRQ_RAWSTAT - GPU_IRQ_RAWSTAT */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_FAULT_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_FAULT_SHIFT (0U) /*! GPU_FAULT - GPU_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_PROTECTED_FAULT_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_PROTECTED_FAULT_SHIFT (1U) /*! GPU_PROTECTED_FAULT - GPU_PROTECTED_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_PROTECTED_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_PROTECTED_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_GPU_PROTECTED_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit2_width6_MASK (0xFCU) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit2_width6_SHIFT (2U) /*! reserved_word0_bit2_width6 - reserved_word0_bit2_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit2_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit2_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit2_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_RESET_COMPLETED_MASK (0x100U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_RESET_COMPLETED_SHIFT (8U) /*! RESET_COMPLETED - RESET_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_RESET_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_RESET_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_RESET_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE_MASK (0x200U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE_SHIFT (9U) /*! POWER_CHANGED_SINGLE - POWER_CHANGED_SINGLE */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_SINGLE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL_MASK (0x400U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL_SHIFT (10U) /*! POWER_CHANGED_ALL - POWER_CHANGED_ALL */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_POWER_CHANGED_ALL_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit11_width6_MASK (0x1F800U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit11_width6_SHIFT (11U) /*! reserved_word0_bit11_width6 - reserved_word0_bit11_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit11_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit11_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit11_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED_MASK (0x20000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED_SHIFT (17U) /*! CLEAN_CACHES_COMPLETED - CLEAN_CACHES_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_CLEAN_CACHES_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_DOORBELL_MIRROR_MASK (0x40000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_DOORBELL_MIRROR_SHIFT (18U) /*! DOORBELL_MIRROR - DOORBELL_MIRROR */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_DOORBELL_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_DOORBELL_MIRROR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_DOORBELL_MIRROR_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_MCU_STATUS_MASK (0x80000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_MCU_STATUS_SHIFT (19U) /*! MCU_STATUS - MCU_STATUS */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_MCU_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_MCU_STATUS_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_MCU_STATUS_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit20_width12_MASK (0xFFF00000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit20_width12_SHIFT (20U) /*! reserved_word0_bit20_width12 - reserved_word0_bit20_width12 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit20_width12(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit20_width12_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_RAWSTAT_reserved_word0_bit20_width12_MASK) /*! @} */ /*! @name GPU_IRQ_CLEAR - GPU_IRQ_CLEAR */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_FAULT_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_FAULT_SHIFT (0U) /*! GPU_FAULT - GPU_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_PROTECTED_FAULT_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_PROTECTED_FAULT_SHIFT (1U) /*! GPU_PROTECTED_FAULT - GPU_PROTECTED_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_PROTECTED_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_PROTECTED_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_GPU_PROTECTED_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit2_width6_MASK (0xFCU) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit2_width6_SHIFT (2U) /*! reserved_word0_bit2_width6 - reserved_word0_bit2_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit2_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit2_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit2_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_RESET_COMPLETED_MASK (0x100U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_RESET_COMPLETED_SHIFT (8U) /*! RESET_COMPLETED - RESET_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_RESET_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_RESET_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_RESET_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_SINGLE_MASK (0x200U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_SINGLE_SHIFT (9U) /*! POWER_CHANGED_SINGLE - POWER_CHANGED_SINGLE */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_SINGLE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_SINGLE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_SINGLE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_ALL_MASK (0x400U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_ALL_SHIFT (10U) /*! POWER_CHANGED_ALL - POWER_CHANGED_ALL */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_ALL(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_ALL_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_POWER_CHANGED_ALL_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit11_width6_MASK (0x1F800U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit11_width6_SHIFT (11U) /*! reserved_word0_bit11_width6 - reserved_word0_bit11_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit11_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit11_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit11_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_CLEAN_CACHES_COMPLETED_MASK (0x20000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_CLEAN_CACHES_COMPLETED_SHIFT (17U) /*! CLEAN_CACHES_COMPLETED - CLEAN_CACHES_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_CLEAN_CACHES_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_CLEAN_CACHES_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_CLEAN_CACHES_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit18_width1_MASK (0x40000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit18_width1_SHIFT (18U) /*! reserved_word0_bit18_width1 - reserved_word0_bit18_width1 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit18_width1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit18_width1_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit18_width1_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_MCU_STATUS_MASK (0x80000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_MCU_STATUS_SHIFT (19U) /*! MCU_STATUS - MCU_STATUS */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_MCU_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_MCU_STATUS_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_MCU_STATUS_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit20_width12_MASK (0xFFF00000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit20_width12_SHIFT (20U) /*! reserved_word0_bit20_width12 - reserved_word0_bit20_width12 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit20_width12(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit20_width12_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_CLEAR_reserved_word0_bit20_width12_MASK) /*! @} */ /*! @name GPU_IRQ_MASK - GPU_IRQ_MASK */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_FAULT_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_FAULT_SHIFT (0U) /*! GPU_FAULT - GPU_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_PROTECTED_FAULT_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_PROTECTED_FAULT_SHIFT (1U) /*! GPU_PROTECTED_FAULT - GPU_PROTECTED_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_PROTECTED_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_PROTECTED_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_GPU_PROTECTED_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit2_width6_MASK (0xFCU) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit2_width6_SHIFT (2U) /*! reserved_word0_bit2_width6 - reserved_word0_bit2_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit2_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit2_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit2_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_RESET_COMPLETED_MASK (0x100U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_RESET_COMPLETED_SHIFT (8U) /*! RESET_COMPLETED - RESET_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_RESET_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_RESET_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_RESET_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_SINGLE_MASK (0x200U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_SINGLE_SHIFT (9U) /*! POWER_CHANGED_SINGLE - POWER_CHANGED_SINGLE */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_SINGLE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_SINGLE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_SINGLE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_ALL_MASK (0x400U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_ALL_SHIFT (10U) /*! POWER_CHANGED_ALL - POWER_CHANGED_ALL */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_ALL(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_ALL_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_POWER_CHANGED_ALL_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit11_width6_MASK (0x1F800U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit11_width6_SHIFT (11U) /*! reserved_word0_bit11_width6 - reserved_word0_bit11_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit11_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit11_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit11_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_CLEAN_CACHES_COMPLETED_MASK (0x20000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_CLEAN_CACHES_COMPLETED_SHIFT (17U) /*! CLEAN_CACHES_COMPLETED - CLEAN_CACHES_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_CLEAN_CACHES_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_CLEAN_CACHES_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_CLEAN_CACHES_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_DOORBELL_MIRROR_MASK (0x40000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_DOORBELL_MIRROR_SHIFT (18U) /*! DOORBELL_MIRROR - DOORBELL_MIRROR */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_DOORBELL_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_DOORBELL_MIRROR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_DOORBELL_MIRROR_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_MCU_STATUS_MASK (0x80000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_MCU_STATUS_SHIFT (19U) /*! MCU_STATUS - MCU_STATUS */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_MCU_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_MCU_STATUS_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_MCU_STATUS_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit20_width12_MASK (0xFFF00000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit20_width12_SHIFT (20U) /*! reserved_word0_bit20_width12 - reserved_word0_bit20_width12 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit20_width12(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit20_width12_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_MASK_reserved_word0_bit20_width12_MASK) /*! @} */ /*! @name GPU_IRQ_STATUS - GPU_IRQ_STATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_FAULT_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_FAULT_SHIFT (0U) /*! GPU_FAULT - GPU_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_PROTECTED_FAULT_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_PROTECTED_FAULT_SHIFT (1U) /*! GPU_PROTECTED_FAULT - GPU_PROTECTED_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_PROTECTED_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_PROTECTED_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_GPU_PROTECTED_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit2_width6_MASK (0xFCU) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit2_width6_SHIFT (2U) /*! reserved_word0_bit2_width6 - reserved_word0_bit2_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit2_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit2_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit2_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_RESET_COMPLETED_MASK (0x100U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_RESET_COMPLETED_SHIFT (8U) /*! RESET_COMPLETED - RESET_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_RESET_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_RESET_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_RESET_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_SINGLE_MASK (0x200U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_SINGLE_SHIFT (9U) /*! POWER_CHANGED_SINGLE - POWER_CHANGED_SINGLE */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_SINGLE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_SINGLE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_SINGLE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_ALL_MASK (0x400U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_ALL_SHIFT (10U) /*! POWER_CHANGED_ALL - POWER_CHANGED_ALL */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_ALL(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_ALL_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_POWER_CHANGED_ALL_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit11_width6_MASK (0x1F800U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit11_width6_SHIFT (11U) /*! reserved_word0_bit11_width6 - reserved_word0_bit11_width6 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit11_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit11_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit11_width6_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_CLEAN_CACHES_COMPLETED_MASK (0x20000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_CLEAN_CACHES_COMPLETED_SHIFT (17U) /*! CLEAN_CACHES_COMPLETED - CLEAN_CACHES_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_CLEAN_CACHES_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_CLEAN_CACHES_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_CLEAN_CACHES_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_DOORBELL_MIRROR_MASK (0x40000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_DOORBELL_MIRROR_SHIFT (18U) /*! DOORBELL_MIRROR - DOORBELL_MIRROR */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_DOORBELL_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_DOORBELL_MIRROR_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_DOORBELL_MIRROR_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_MCU_STATUS_MASK (0x80000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_MCU_STATUS_SHIFT (19U) /*! MCU_STATUS - MCU_STATUS */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_MCU_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_MCU_STATUS_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_MCU_STATUS_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit20_width12_MASK (0xFFF00000U) #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit20_width12_SHIFT (20U) /*! reserved_word0_bit20_width12 - reserved_word0_bit20_width12 */ #define GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit20_width12(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit20_width12_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_IRQ_STATUS_reserved_word0_bit20_width12_MASK) /*! @} */ /*! @name GPU_COMMAND - GPU_COMMAND */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_COMMAND_command_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_GPU_COMMAND_command_SHIFT (0U) /*! command - command * 0b00000000.. * 0b00000001.. * 0b00000100.. * 0b00000111.. */ #define GPU_MALI_GPU_REGISTERS_GPU_COMMAND_command(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_COMMAND_command_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_COMMAND_command_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_COMMAND_payload_MASK (0xFFFFFF00U) #define GPU_MALI_GPU_REGISTERS_GPU_COMMAND_payload_SHIFT (8U) /*! payload - payload */ #define GPU_MALI_GPU_REGISTERS_GPU_COMMAND_payload(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_COMMAND_payload_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_COMMAND_payload_MASK) /*! @} */ /*! @name GPU_STATUS - GPU_STATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_ACTIVE_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_ACTIVE_SHIFT (0U) /*! GPU_ACTIVE - GPU_ACTIVE */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_ACTIVE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_ACTIVE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PWR_ACTIVE_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PWR_ACTIVE_SHIFT (1U) /*! PWR_ACTIVE - PWR_ACTIVE */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PWR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_PWR_ACTIVE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_PWR_ACTIVE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit2_width2_MASK (0xCU) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit2_width2_SHIFT (2U) /*! reserved_word0_bit2_width2 - reserved_word0_bit2_width2 */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit2_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit2_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit2_width2_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PAGE_FAULT_MASK (0x10U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PAGE_FAULT_SHIFT (4U) /*! PAGE_FAULT - PAGE_FAULT */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PAGE_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_PAGE_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_PAGE_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit5_width2_MASK (0x60U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit5_width2_SHIFT (5U) /*! reserved_word0_bit5_width2 - reserved_word0_bit5_width2 */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit5_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit5_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit5_width2_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PROTECTED_MODE_ACTIVE_MASK (0x80U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PROTECTED_MODE_ACTIVE_SHIFT (7U) /*! PROTECTED_MODE_ACTIVE - PROTECTED_MODE_ACTIVE */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_PROTECTED_MODE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_PROTECTED_MODE_ACTIVE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_PROTECTED_MODE_ACTIVE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_DBG_ENABLED_MASK (0x100U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_DBG_ENABLED_SHIFT (8U) /*! GPU_DBG_ENABLED - GPU_DBG_ENABLED */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_DBG_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_DBG_ENABLED_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_GPU_DBG_ENABLED_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit9_width22_MASK (0x7FFFFE00U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit9_width22_SHIFT (9U) /*! reserved_word0_bit9_width22 - reserved_word0_bit9_width22 */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit9_width22(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit9_width22_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit9_width22_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit31_width1_MASK (0x80000000U) #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit31_width1_SHIFT (31U) /*! reserved_word0_bit31_width1 - reserved_word0_bit31_width1 */ #define GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit31_width1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit31_width1_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_STATUS_reserved_word0_bit31_width1_MASK) /*! @} */ /*! @name GPU_FAULTSTATUS - GPU_FAULTSTATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT (0U) /*! EXCEPTION_TYPE - EXCEPTION_TYPE * 0b00000000.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00001000.. * 0b00001111.. * 0b01000000.. * 0b01000100.. * 0b01001000.. * 0b01001001.. * 0b01001010.. * 0b01001011.. * 0b01010000.. * 0b01010001.. * 0b01010101.. * 0b01011000.. * 0b01011001.. * 0b01011010.. * 0b01011011.. * 0b01100000.. * 0b01101000.. * 0b01101001.. * 0b01110000.. * 0b01110001.. * 0b01110010.. * 0b01110011.. * 0b01110100.. * 0b01110101.. * 0b01110110.. * 0b01110111.. * 0b01111000.. * 0b01111001.. * 0b01111010.. * 0b01111011.. * 0b01111100.. * 0b01111101.. * 0b01111110.. * 0b01111111.. * 0b10000000.. * 0b10001000.. * 0b10001001.. * 0b10001010.. * 0b11000000.. * 0b11000001.. * 0b11000010.. * 0b11000011.. * 0b11000100.. * 0b11001000.. * 0b11001001.. * 0b11001010.. * 0b11001011.. * 0b11011001.. * 0b11011010.. * 0b11011011.. * 0b11100000.. * 0b11100100.. * 0b11100101.. * 0b11100110.. * 0b11100111.. * 0b11101000.. * 0b11101001.. * 0b11101010.. * 0b11101011.. */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_EXCEPTION_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ACCESS_TYPE_MASK (0x300U) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT (8U) /*! ACCESS_TYPE - ACCESS_TYPE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ACCESS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ACCESS_TYPE_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ADDRESS_VALID_MASK (0x400U) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT (10U) /*! ADDRESS_VALID - ADDRESS_VALID */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ADDRESS_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_ADDRESS_VALID_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_VALID_MASK (0x800U) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_VALID_SHIFT (11U) /*! JASID_VALID - JASID_VALID */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_VALID_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_VALID_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_MASK (0xF000U) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_SHIFT (12U) /*! JASID - JASID */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_JASID_MASK) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_SOURCE_ID_MASK (0xFFFF0000U) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_SOURCE_ID_SHIFT (16U) /*! SOURCE_ID - SOURCE_ID */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_SOURCE_ID_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTSTATUS_SOURCE_ID_MASK) /*! @} */ /*! @name GPU_FAULTADDRESS_LO - GPU_FAULTADDRESS_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_LO_pointer_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_LO_pointer_SHIFT (0U) /*! pointer - pointer */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_LO_pointer(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_LO_pointer_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_LO_pointer_MASK) /*! @} */ /*! @name GPU_FAULTADDRESS_HI - GPU_FAULTADDRESS_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_HI_pointer_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_HI_pointer_SHIFT (0U) /*! pointer - pointer */ #define GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_HI_pointer(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_HI_pointer_SHIFT)) & GPU_MALI_GPU_REGISTERS_GPU_FAULTADDRESS_HI_pointer_MASK) /*! @} */ /*! @name L2_CONFIG - L2_CONFIG */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_reserved_word0_bit0_width16_MASK (0xFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_reserved_word0_bit0_width16_SHIFT (0U) /*! reserved_word0_bit0_width16 - reserved_word0_bit0_width16 */ #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_reserved_word0_bit0_width16(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_CONFIG_reserved_word0_bit0_width16_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_CONFIG_reserved_word0_bit0_width16_MASK) #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_CACHE_SIZE_MASK (0xFF0000U) #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_CACHE_SIZE_SHIFT (16U) /*! CACHE_SIZE - CACHE_SIZE */ #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_CACHE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_CONFIG_CACHE_SIZE_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_CONFIG_CACHE_SIZE_MASK) #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_HASH_FUNCTION_MASK (0xFF000000U) #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_HASH_FUNCTION_SHIFT (24U) /*! HASH_FUNCTION - HASH_FUNCTION */ #define GPU_MALI_GPU_REGISTERS_L2_CONFIG_HASH_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_CONFIG_HASH_FUNCTION_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_CONFIG_HASH_FUNCTION_MASK) /*! @} */ /*! @name PWR_KEY - PWR_KEY */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_PWR_KEY_key_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_PWR_KEY_key_SHIFT (0U) /*! key - key */ #define GPU_MALI_GPU_REGISTERS_PWR_KEY_key(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_KEY_key_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_KEY_key_MASK) /*! @} */ /*! @name PWR_OVERRIDE0 - PWR_OVERRIDE0 */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_OVERRIDE_MASK (0x3U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_OVERRIDE_SHIFT (0U) /*! PWRUP_OVERRIDE - PWRUP_OVERRIDE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_OVERRIDE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_OVERRIDE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_OVERRIDE_MASK (0xCU) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_OVERRIDE_SHIFT (2U) /*! ISOLATE_OVERRIDE - ISOLATE_OVERRIDE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_OVERRIDE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_OVERRIDE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_RESET_OVERRIDE_MASK (0x30U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_RESET_OVERRIDE_SHIFT (4U) /*! RESET_OVERRIDE - RESET_OVERRIDE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_RESET_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_RESET_OVERRIDE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_RESET_OVERRIDE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit6_width2_MASK (0xC0U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit6_width2_SHIFT (6U) /*! reserved_word0_bit6_width2 - reserved_word0_bit6_width2 */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit6_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit6_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit6_width2_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_ACK_OVERRIDE_MASK (0x300U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_ACK_OVERRIDE_SHIFT (8U) /*! PWRUP_ACK_OVERRIDE - PWRUP_ACK_OVERRIDE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_ACK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_ACK_OVERRIDE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRUP_ACK_OVERRIDE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_ACK_OVERRIDE_MASK (0xC00U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_ACK_OVERRIDE_SHIFT (10U) /*! ISOLATE_ACK_OVERRIDE - ISOLATE_ACK_OVERRIDE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_ACK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_ACK_OVERRIDE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_ISOLATE_ACK_OVERRIDE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_OVERRIDE_MASK (0x3000U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_OVERRIDE_SHIFT (12U) /*! FUNC_ISO_OVERRIDE - FUNC_ISO_OVERRIDE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_OVERRIDE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_OVERRIDE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_ACK_OVERRIDE_MASK (0xC000U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_ACK_OVERRIDE_SHIFT (14U) /*! FUNC_ISO_ACK_OVERRIDE - FUNC_ISO_ACK_OVERRIDE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_ACK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_ACK_OVERRIDE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_FUNC_ISO_ACK_OVERRIDE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRTRANS_LIMIT_MASK (0x3F0000U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRTRANS_LIMIT_SHIFT (16U) /*! PWRTRANS_LIMIT - PWRTRANS_LIMIT */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRTRANS_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRTRANS_LIMIT_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_PWRTRANS_LIMIT_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit22_width1_MASK (0x400000U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit22_width1_SHIFT (22U) /*! reserved_word0_bit22_width1 - reserved_word0_bit22_width1 */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit22_width1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit22_width1_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit22_width1_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_ENABLE_MASK (0x800000U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_ENABLE_SHIFT (23U) /*! THROTTLE_ENABLE - THROTTLE_ENABLE */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_ENABLE_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_ENABLE_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_LIMIT_MASK (0x3F000000U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_LIMIT_SHIFT (24U) /*! THROTTLE_LIMIT - THROTTLE_LIMIT */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_LIMIT_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_THROTTLE_LIMIT_MASK) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit30_width2_MASK (0xC0000000U) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit30_width2_SHIFT (30U) /*! reserved_word0_bit30_width2 - reserved_word0_bit30_width2 */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit30_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit30_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE0_reserved_word0_bit30_width2_MASK) /*! @} */ /*! @name PWR_OVERRIDE1 - PWR_OVERRIDE1 */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE1_PWRTRANS_VENDOR_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE1_PWRTRANS_VENDOR_SHIFT (0U) /*! PWRTRANS_VENDOR - PWRTRANS_VENDOR */ #define GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE1_PWRTRANS_VENDOR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE1_PWRTRANS_VENDOR_SHIFT)) & GPU_MALI_GPU_REGISTERS_PWR_OVERRIDE1_PWRTRANS_VENDOR_MASK) /*! @} */ /*! @name TIMESTAMP_OFFSET_LO - TIMESTAMP_OFFSET_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_LO_offset_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_LO_offset_SHIFT (0U) /*! offset - offset */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_LO_offset(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_LO_offset_SHIFT)) & GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_LO_offset_MASK) /*! @} */ /*! @name TIMESTAMP_OFFSET_HI - TIMESTAMP_OFFSET_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_HI_offset_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_HI_offset_SHIFT (0U) /*! offset - offset */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_HI_offset(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_HI_offset_SHIFT)) & GPU_MALI_GPU_REGISTERS_TIMESTAMP_OFFSET_HI_offset_MASK) /*! @} */ /*! @name CYCLE_COUNT_LO - CYCLE_COUNT_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_LO_count_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_LO_count_SHIFT (0U) /*! count - count */ #define GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_LO_count(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_LO_count_SHIFT)) & GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_LO_count_MASK) /*! @} */ /*! @name CYCLE_COUNT_HI - CYCLE_COUNT_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_HI_count_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_HI_count_SHIFT (0U) /*! count - count */ #define GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_HI_count(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_HI_count_SHIFT)) & GPU_MALI_GPU_REGISTERS_CYCLE_COUNT_HI_count_MASK) /*! @} */ /*! @name TIMESTAMP_LO - TIMESTAMP_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_LO_timestamp_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_LO_timestamp_SHIFT (0U) /*! timestamp - timestamp */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_LO_timestamp(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TIMESTAMP_LO_timestamp_SHIFT)) & GPU_MALI_GPU_REGISTERS_TIMESTAMP_LO_timestamp_MASK) /*! @} */ /*! @name TIMESTAMP_HI - TIMESTAMP_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_HI_timestamp_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_HI_timestamp_SHIFT (0U) /*! timestamp - timestamp */ #define GPU_MALI_GPU_REGISTERS_TIMESTAMP_HI_timestamp(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TIMESTAMP_HI_timestamp_SHIFT)) & GPU_MALI_GPU_REGISTERS_TIMESTAMP_HI_timestamp_MASK) /*! @} */ /*! @name THREAD_MAX_THREADS - THREAD_MAX_THREADS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_THREADS_threads_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_THREADS_threads_SHIFT (0U) /*! threads - threads */ #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_THREADS_threads(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_THREAD_MAX_THREADS_threads_SHIFT)) & GPU_MALI_GPU_REGISTERS_THREAD_MAX_THREADS_threads_MASK) /*! @} */ /*! @name THREAD_MAX_WORKGROUP_SIZE - THREAD_MAX_WORKGROUP_SIZE */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_WORKGROUP_SIZE_threads_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_WORKGROUP_SIZE_threads_SHIFT (0U) /*! threads - threads */ #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_WORKGROUP_SIZE_threads(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_THREAD_MAX_WORKGROUP_SIZE_threads_SHIFT)) & GPU_MALI_GPU_REGISTERS_THREAD_MAX_WORKGROUP_SIZE_threads_MASK) /*! @} */ /*! @name THREAD_MAX_BARRIER_SIZE - THREAD_MAX_BARRIER_SIZE */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_BARRIER_SIZE_threads_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_BARRIER_SIZE_threads_SHIFT (0U) /*! threads - threads */ #define GPU_MALI_GPU_REGISTERS_THREAD_MAX_BARRIER_SIZE_threads(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_THREAD_MAX_BARRIER_SIZE_threads_SHIFT)) & GPU_MALI_GPU_REGISTERS_THREAD_MAX_BARRIER_SIZE_threads_MASK) /*! @} */ /*! @name THREAD_FEATURES - THREAD_FEATURES */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_REGISTERS_MASK (0x3FFFFFU) #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_REGISTERS_SHIFT (0U) /*! MAX_REGISTERS - MAX_REGISTERS */ #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_REGISTERS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_REGISTERS_SHIFT)) & GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_REGISTERS_MASK) #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_MASK (0xC00000U) #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_SHIFT (22U) /*! IMPLEMENTATION_TECHNOLOGY - IMPLEMENTATION_TECHNOLOGY * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_SHIFT)) & GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_IMPLEMENTATION_TECHNOLOGY_MASK) #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_TASK_QUEUE_MASK (0xFF000000U) #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_TASK_QUEUE_SHIFT (24U) /*! MAX_TASK_QUEUE - MAX_TASK_QUEUE */ #define GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_TASK_QUEUE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_TASK_QUEUE_SHIFT)) & GPU_MALI_GPU_REGISTERS_THREAD_FEATURES_MAX_TASK_QUEUE_MASK) /*! @} */ /*! @name TEXTURE_FEATURES_0 - TEXTURE_FEATURES_0 */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_0_format_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_0_format_SHIFT (0U) /*! format - format */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_0_format(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_0_format_SHIFT)) & GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_0_format_MASK) /*! @} */ /*! @name TEXTURE_FEATURES_1 - TEXTURE_FEATURES_1 */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_1_reserved_word0_bit0_width32_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_1_reserved_word0_bit0_width32_SHIFT (0U) /*! reserved_word0_bit0_width32 - reserved_word0_bit0_width32 */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_1_reserved_word0_bit0_width32(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_1_reserved_word0_bit0_width32_SHIFT)) & GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_1_reserved_word0_bit0_width32_MASK) /*! @} */ /*! @name TEXTURE_FEATURES_2 - TEXTURE_FEATURES_2 */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_2_reserved_word0_bit0_width32_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_2_reserved_word0_bit0_width32_SHIFT (0U) /*! reserved_word0_bit0_width32 - reserved_word0_bit0_width32 */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_2_reserved_word0_bit0_width32(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_2_reserved_word0_bit0_width32_SHIFT)) & GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_2_reserved_word0_bit0_width32_MASK) /*! @} */ /*! @name TEXTURE_FEATURES_3 - TEXTURE_FEATURES_3 */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_3_reserved_word0_bit0_width32_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_3_reserved_word0_bit0_width32_SHIFT (0U) /*! reserved_word0_bit0_width32 - reserved_word0_bit0_width32 */ #define GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_3_reserved_word0_bit0_width32(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_3_reserved_word0_bit0_width32_SHIFT)) & GPU_MALI_GPU_REGISTERS_TEXTURE_FEATURES_3_reserved_word0_bit0_width32_MASK) /*! @} */ /*! @name SHADER_PRESENT_LO - SHADER_PRESENT_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_LO_present_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_LO_present_SHIFT (0U) /*! present - present */ #define GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_LO_present(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_LO_present_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_LO_present_MASK) /*! @} */ /*! @name SHADER_PRESENT_HI - SHADER_PRESENT_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_HI_present_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_HI_present_SHIFT (0U) /*! present - present */ #define GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_HI_present(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_HI_present_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PRESENT_HI_present_MASK) /*! @} */ /*! @name TILER_PRESENT_LO - TILER_PRESENT_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PRESENT_LO_present_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PRESENT_LO_present_SHIFT (0U) /*! present - present */ #define GPU_MALI_GPU_REGISTERS_TILER_PRESENT_LO_present(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PRESENT_LO_present_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PRESENT_LO_present_MASK) /*! @} */ /*! @name TILER_PRESENT_HI - TILER_PRESENT_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PRESENT_HI_present_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PRESENT_HI_present_SHIFT (0U) /*! present - present */ #define GPU_MALI_GPU_REGISTERS_TILER_PRESENT_HI_present(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PRESENT_HI_present_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PRESENT_HI_present_MASK) /*! @} */ /*! @name L2_PRESENT_LO - L2_PRESENT_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PRESENT_LO_present_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PRESENT_LO_present_SHIFT (0U) /*! present - present */ #define GPU_MALI_GPU_REGISTERS_L2_PRESENT_LO_present(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PRESENT_LO_present_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PRESENT_LO_present_MASK) /*! @} */ /*! @name L2_PRESENT_HI - L2_PRESENT_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PRESENT_HI_present_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PRESENT_HI_present_SHIFT (0U) /*! present - present */ #define GPU_MALI_GPU_REGISTERS_L2_PRESENT_HI_present(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PRESENT_HI_present_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PRESENT_HI_present_MASK) /*! @} */ /*! @name SHADER_READY_LO - SHADER_READY_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_READY_LO_ready_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_READY_LO_ready_SHIFT (0U) /*! ready - ready */ #define GPU_MALI_GPU_REGISTERS_SHADER_READY_LO_ready(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_READY_LO_ready_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_READY_LO_ready_MASK) /*! @} */ /*! @name SHADER_READY_HI - SHADER_READY_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_READY_HI_ready_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_READY_HI_ready_SHIFT (0U) /*! ready - ready */ #define GPU_MALI_GPU_REGISTERS_SHADER_READY_HI_ready(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_READY_HI_ready_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_READY_HI_ready_MASK) /*! @} */ /*! @name TILER_READY_LO - TILER_READY_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_READY_LO_ready_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_READY_LO_ready_SHIFT (0U) /*! ready - ready */ #define GPU_MALI_GPU_REGISTERS_TILER_READY_LO_ready(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_READY_LO_ready_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_READY_LO_ready_MASK) /*! @} */ /*! @name TILER_READY_HI - TILER_READY_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_READY_HI_ready_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_READY_HI_ready_SHIFT (0U) /*! ready - ready */ #define GPU_MALI_GPU_REGISTERS_TILER_READY_HI_ready(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_READY_HI_ready_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_READY_HI_ready_MASK) /*! @} */ /*! @name L2_READY_LO - L2_READY_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_READY_LO_ready_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_READY_LO_ready_SHIFT (0U) /*! ready - ready */ #define GPU_MALI_GPU_REGISTERS_L2_READY_LO_ready(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_READY_LO_ready_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_READY_LO_ready_MASK) /*! @} */ /*! @name L2_READY_HI - L2_READY_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_READY_HI_ready_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_READY_HI_ready_SHIFT (0U) /*! ready - ready */ #define GPU_MALI_GPU_REGISTERS_L2_READY_HI_ready(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_READY_HI_ready_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_READY_HI_ready_MASK) /*! @} */ /*! @name SHADER_PWRON_LO - SHADER_PWRON_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRON_LO_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWRON_LO_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRON_LO_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWRON_LO_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWRON_LO_request_MASK) /*! @} */ /*! @name SHADER_PWRON_HI - SHADER_PWRON_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRON_HI_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWRON_HI_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRON_HI_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWRON_HI_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWRON_HI_request_MASK) /*! @} */ /*! @name TILER_PWRON_LO - TILER_PWRON_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRON_LO_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWRON_LO_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRON_LO_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWRON_LO_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWRON_LO_request_MASK) /*! @} */ /*! @name TILER_PWRON_HI - TILER_PWRON_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRON_HI_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWRON_HI_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRON_HI_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWRON_HI_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWRON_HI_request_MASK) /*! @} */ /*! @name L2_PWRON_LO - L2_PWRON_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWRON_LO_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWRON_LO_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_L2_PWRON_LO_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWRON_LO_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWRON_LO_request_MASK) /*! @} */ /*! @name L2_PWRON_HI - L2_PWRON_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWRON_HI_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWRON_HI_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_L2_PWRON_HI_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWRON_HI_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWRON_HI_request_MASK) /*! @} */ /*! @name SHADER_PWROFF_LO - SHADER_PWROFF_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_LO_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_LO_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_LO_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_LO_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_LO_request_MASK) /*! @} */ /*! @name SHADER_PWROFF_HI - SHADER_PWROFF_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_HI_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_HI_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_HI_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_HI_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWROFF_HI_request_MASK) /*! @} */ /*! @name TILER_PWROFF_LO - TILER_PWROFF_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWROFF_LO_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWROFF_LO_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_TILER_PWROFF_LO_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWROFF_LO_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWROFF_LO_request_MASK) /*! @} */ /*! @name TILER_PWROFF_HI - TILER_PWROFF_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWROFF_HI_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWROFF_HI_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_TILER_PWROFF_HI_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWROFF_HI_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWROFF_HI_request_MASK) /*! @} */ /*! @name L2_PWROFF_LO - L2_PWROFF_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWROFF_LO_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWROFF_LO_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_L2_PWROFF_LO_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWROFF_LO_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWROFF_LO_request_MASK) /*! @} */ /*! @name L2_PWROFF_HI - L2_PWROFF_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWROFF_HI_request_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWROFF_HI_request_SHIFT (0U) /*! request - request */ #define GPU_MALI_GPU_REGISTERS_L2_PWROFF_HI_request(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWROFF_HI_request_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWROFF_HI_request_MASK) /*! @} */ /*! @name SHADER_PWRTRANS_LO - SHADER_PWRTRANS_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_LO_changing_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_LO_changing_SHIFT (0U) /*! changing - changing */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_LO_changing(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_LO_changing_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_LO_changing_MASK) /*! @} */ /*! @name SHADER_PWRTRANS_HI - SHADER_PWRTRANS_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_HI_changing_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_HI_changing_SHIFT (0U) /*! changing - changing */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_HI_changing(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_HI_changing_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWRTRANS_HI_changing_MASK) /*! @} */ /*! @name TILER_PWRTRANS_LO - TILER_PWRTRANS_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_LO_changing_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_LO_changing_SHIFT (0U) /*! changing - changing */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_LO_changing(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_LO_changing_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_LO_changing_MASK) /*! @} */ /*! @name TILER_PWRTRANS_HI - TILER_PWRTRANS_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_HI_changing_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_HI_changing_SHIFT (0U) /*! changing - changing */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_HI_changing(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_HI_changing_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWRTRANS_HI_changing_MASK) /*! @} */ /*! @name L2_PWRTRANS_LO - L2_PWRTRANS_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_LO_changing_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_LO_changing_SHIFT (0U) /*! changing - changing */ #define GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_LO_changing(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_LO_changing_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_LO_changing_MASK) /*! @} */ /*! @name L2_PWRTRANS_HI - L2_PWRTRANS_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_HI_changing_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_HI_changing_SHIFT (0U) /*! changing - changing */ #define GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_HI_changing(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_HI_changing_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWRTRANS_HI_changing_MASK) /*! @} */ /*! @name SHADER_PWRACTIVE_LO - SHADER_PWRACTIVE_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_LO_active_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_LO_active_SHIFT (0U) /*! active - active */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_LO_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_LO_active_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_LO_active_MASK) /*! @} */ /*! @name SHADER_PWRACTIVE_HI - SHADER_PWRACTIVE_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_HI_active_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_HI_active_SHIFT (0U) /*! active - active */ #define GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_HI_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_HI_active_SHIFT)) & GPU_MALI_GPU_REGISTERS_SHADER_PWRACTIVE_HI_active_MASK) /*! @} */ /*! @name TILER_PWRACTIVE_LO - TILER_PWRACTIVE_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_LO_active_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_LO_active_SHIFT (0U) /*! active - active */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_LO_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_LO_active_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_LO_active_MASK) /*! @} */ /*! @name TILER_PWRACTIVE_HI - TILER_PWRACTIVE_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_HI_active_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_HI_active_SHIFT (0U) /*! active - active */ #define GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_HI_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_HI_active_SHIFT)) & GPU_MALI_GPU_REGISTERS_TILER_PWRACTIVE_HI_active_MASK) /*! @} */ /*! @name L2_PWRACTIVE_LO - L2_PWRACTIVE_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_LO_active_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_LO_active_SHIFT (0U) /*! active - active */ #define GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_LO_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_LO_active_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_LO_active_MASK) /*! @} */ /*! @name L2_PWRACTIVE_HI - L2_PWRACTIVE_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_HI_active_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_HI_active_SHIFT (0U) /*! active - active */ #define GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_HI_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_HI_active_SHIFT)) & GPU_MALI_GPU_REGISTERS_L2_PWRACTIVE_HI_active_MASK) /*! @} */ /*! @name REVIDR - REVIDR */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_REVIDR_revision_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_REVIDR_revision_SHIFT (0U) /*! revision - revision */ #define GPU_MALI_GPU_REGISTERS_REVIDR_revision(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_REVIDR_revision_SHIFT)) & GPU_MALI_GPU_REGISTERS_REVIDR_revision_MASK) /*! @} */ /*! @name COHERENCY_FEATURES - COHERENCY_FEATURES */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_lite_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_lite_SHIFT (0U) /*! ace_lite - ace_lite */ #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_lite(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_lite_SHIFT)) & GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_lite_MASK) #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_SHIFT (1U) /*! ace - ace */ #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_SHIFT)) & GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_ace_MASK) #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_reserved_word0_bit2_width30_MASK (0xFFFFFFFCU) #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_reserved_word0_bit2_width30_SHIFT (2U) /*! reserved_word0_bit2_width30 - reserved_word0_bit2_width30 */ #define GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_reserved_word0_bit2_width30(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_reserved_word0_bit2_width30_SHIFT)) & GPU_MALI_GPU_REGISTERS_COHERENCY_FEATURES_reserved_word0_bit2_width30_MASK) /*! @} */ /*! @name COHERENCY_ENABLE - COHERENCY_ENABLE */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_COHERENCY_ENABLE_l2_cache_protocol_select_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_COHERENCY_ENABLE_l2_cache_protocol_select_SHIFT (0U) /*! l2_cache_protocol_select - l2_cache_protocol_select * 0b00000000000000000000000000000000.. * 0b00000000000000000000000000000001.. * 0b00000000000000000000000000011111.. */ #define GPU_MALI_GPU_REGISTERS_COHERENCY_ENABLE_l2_cache_protocol_select(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_COHERENCY_ENABLE_l2_cache_protocol_select_SHIFT)) & GPU_MALI_GPU_REGISTERS_COHERENCY_ENABLE_l2_cache_protocol_select_MASK) /*! @} */ /*! @name MCU_CONTROL - MCU_CONTROL */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_MCU_CONTROL_REQ_MASK (0x3U) #define GPU_MALI_GPU_REGISTERS_MCU_CONTROL_REQ_SHIFT (0U) /*! REQ - REQ * 0b00.. * 0b01.. * 0b10.. */ #define GPU_MALI_GPU_REGISTERS_MCU_CONTROL_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MCU_CONTROL_REQ_SHIFT)) & GPU_MALI_GPU_REGISTERS_MCU_CONTROL_REQ_MASK) #define GPU_MALI_GPU_REGISTERS_MCU_CONTROL_reserved_word0_bit2_width30_MASK (0xFFFFFFFCU) #define GPU_MALI_GPU_REGISTERS_MCU_CONTROL_reserved_word0_bit2_width30_SHIFT (2U) /*! reserved_word0_bit2_width30 - reserved_word0_bit2_width30 */ #define GPU_MALI_GPU_REGISTERS_MCU_CONTROL_reserved_word0_bit2_width30(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MCU_CONTROL_reserved_word0_bit2_width30_SHIFT)) & GPU_MALI_GPU_REGISTERS_MCU_CONTROL_reserved_word0_bit2_width30_MASK) /*! @} */ /*! @name MCU_STATUS - MCU_STATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_MCU_STATUS_VALUE_MASK (0x3U) #define GPU_MALI_GPU_REGISTERS_MCU_STATUS_VALUE_SHIFT (0U) /*! VALUE - VALUE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_MCU_STATUS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MCU_STATUS_VALUE_SHIFT)) & GPU_MALI_GPU_REGISTERS_MCU_STATUS_VALUE_MASK) #define GPU_MALI_GPU_REGISTERS_MCU_STATUS_reserved_word0_bit2_width30_MASK (0xFFFFFFFCU) #define GPU_MALI_GPU_REGISTERS_MCU_STATUS_reserved_word0_bit2_width30_SHIFT (2U) /*! reserved_word0_bit2_width30 - reserved_word0_bit2_width30 */ #define GPU_MALI_GPU_REGISTERS_MCU_STATUS_reserved_word0_bit2_width30(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MCU_STATUS_reserved_word0_bit2_width30_SHIFT)) & GPU_MALI_GPU_REGISTERS_MCU_STATUS_reserved_word0_bit2_width30_MASK) /*! @} */ /*! @name JOB_IRQ_RAWSTAT - JOB_IRQ_RAWSTAT */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_csg_MASK (0x7FFFFFFFU) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_csg_SHIFT (0U) /*! csg - csg */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_csg(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_csg_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_csg_MASK) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_glb_MASK (0x80000000U) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_glb_SHIFT (31U) /*! glb - glb */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_glb(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_glb_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_RAWSTAT_glb_MASK) /*! @} */ /*! @name JOB_IRQ_CLEAR - JOB_IRQ_CLEAR */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_csg_MASK (0x7FFFFFFFU) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_csg_SHIFT (0U) /*! csg - csg */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_csg(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_csg_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_csg_MASK) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_glb_MASK (0x80000000U) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_glb_SHIFT (31U) /*! glb - glb */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_glb(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_glb_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_CLEAR_glb_MASK) /*! @} */ /*! @name JOB_IRQ_MASK - JOB_IRQ_MASK */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_csg_MASK (0x7FFFFFFFU) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_csg_SHIFT (0U) /*! csg - csg */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_csg(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_csg_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_csg_MASK) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_glb_MASK (0x80000000U) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_glb_SHIFT (31U) /*! glb - glb */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_glb(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_glb_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_MASK_glb_MASK) /*! @} */ /*! @name JOB_IRQ_STATUS - JOB_IRQ_STATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_csg_MASK (0x7FFFFFFFU) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_csg_SHIFT (0U) /*! csg - csg */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_csg(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_csg_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_csg_MASK) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_glb_MASK (0x80000000U) #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_glb_SHIFT (31U) /*! glb - glb */ #define GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_glb(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_glb_SHIFT)) & GPU_MALI_GPU_REGISTERS_JOB_IRQ_STATUS_glb_MASK) /*! @} */ /*! @name IRQ_RAWSTAT - IRQ_RAWSTAT */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_PAGE_FAULT_MASK (0xFFFFU) #define GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_PAGE_FAULT_SHIFT (0U) /*! PAGE_FAULT - PAGE_FAULT */ #define GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_PAGE_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_PAGE_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_PAGE_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_COMMAND_COMPLETED_MASK (0xFFFF0000U) #define GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_COMMAND_COMPLETED_SHIFT (16U) /*! COMMAND_COMPLETED - COMMAND_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_COMMAND_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_COMMAND_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_RAWSTAT_COMMAND_COMPLETED_MASK) /*! @} */ /*! @name IRQ_CLEAR - IRQ_CLEAR */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_PAGE_FAULT_MASK (0xFFFFU) #define GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_PAGE_FAULT_SHIFT (0U) /*! PAGE_FAULT - PAGE_FAULT */ #define GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_PAGE_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_PAGE_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_PAGE_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_COMMAND_COMPLETED_MASK (0xFFFF0000U) #define GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_COMMAND_COMPLETED_SHIFT (16U) /*! COMMAND_COMPLETED - COMMAND_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_COMMAND_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_COMMAND_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_CLEAR_COMMAND_COMPLETED_MASK) /*! @} */ /*! @name IRQ_MASK - IRQ_MASK */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_SHIFT (0U) /*! PAGE_FAULT - PAGE_FAULT */ #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_RESERVED_MASK (0xFF00U) #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_RESERVED_SHIFT (8U) /*! PAGE_FAULT_RESERVED - PAGE_FAULT_RESERVED */ #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_RESERVED_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_MASK_PAGE_FAULT_RESERVED_MASK) #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_MASK (0xFF0000U) #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_SHIFT (16U) /*! COMMAND_COMPLETED - COMMAND_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_MASK) #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_RESERVED_MASK (0xFF000000U) #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_RESERVED_SHIFT (24U) /*! COMMAND_COMPLETED_RESERVED - COMMAND_COMPLETED_RESERVED */ #define GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_RESERVED_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_MASK_COMMAND_COMPLETED_RESERVED_MASK) /*! @} */ /*! @name IRQ_STATUS - IRQ_STATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_IRQ_STATUS_PAGE_FAULT_MASK (0xFFFFU) #define GPU_MALI_GPU_REGISTERS_IRQ_STATUS_PAGE_FAULT_SHIFT (0U) /*! PAGE_FAULT - PAGE_FAULT */ #define GPU_MALI_GPU_REGISTERS_IRQ_STATUS_PAGE_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_STATUS_PAGE_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_STATUS_PAGE_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_IRQ_STATUS_COMMAND_COMPLETED_MASK (0xFFFF0000U) #define GPU_MALI_GPU_REGISTERS_IRQ_STATUS_COMMAND_COMPLETED_SHIFT (16U) /*! COMMAND_COMPLETED - COMMAND_COMPLETED */ #define GPU_MALI_GPU_REGISTERS_IRQ_STATUS_COMMAND_COMPLETED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_IRQ_STATUS_COMMAND_COMPLETED_SHIFT)) & GPU_MALI_GPU_REGISTERS_IRQ_STATUS_COMMAND_COMPLETED_MASK) /*! @} */ /*! @name TRANSTAB_LO - TRANSTAB_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_RESERVED_MASK (0xFU) #define GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_RESERVED_SHIFT (0U) /*! BASE_RESERVED - BASE_RESERVED */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_RESERVED_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_RESERVED_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_MASK (0xFFFFFFF0U) #define GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_SHIFT (4U) /*! BASE - BASE */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_BASE_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_TRANSTAB_LO */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_LO_COUNT (8U) /*! @name TRANSTAB_HI - TRANSTAB_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_SHIFT (0U) /*! BASE - BASE */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_RESERVED_MASK (0xFFFFFF00U) #define GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_RESERVED_SHIFT (8U) /*! BASE_RESERVED - BASE_RESERVED */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_RESERVED_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_BASE_RESERVED_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_TRANSTAB_HI */ #define GPU_MALI_GPU_REGISTERS_TRANSTAB_HI_COUNT (8U) /*! @name MEMATTR_LO - MEMATTR_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE0_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE0_SHIFT (0U) /*! ATTRIBUTE0 - ATTRIBUTE0 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE0(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE0_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE0_MASK) #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE1_MASK (0xFF00U) #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE1_SHIFT (8U) /*! ATTRIBUTE1 - ATTRIBUTE1 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE1_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE1_MASK) #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE2_MASK (0xFF0000U) #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE2_SHIFT (16U) /*! ATTRIBUTE2 - ATTRIBUTE2 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE2_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE2_MASK) #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE3_MASK (0xFF000000U) #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE3_SHIFT (24U) /*! ATTRIBUTE3 - ATTRIBUTE3 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE3(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE3_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_LO_ATTRIBUTE3_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_MEMATTR_LO */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_LO_COUNT (8U) /*! @name MEMATTR_HI - MEMATTR_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE4_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE4_SHIFT (0U) /*! ATTRIBUTE4 - ATTRIBUTE4 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE4(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE4_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE4_MASK) #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE5_MASK (0xFF00U) #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE5_SHIFT (8U) /*! ATTRIBUTE5 - ATTRIBUTE5 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE5(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE5_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE5_MASK) #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE6_MASK (0xFF0000U) #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE6_SHIFT (16U) /*! ATTRIBUTE6 - ATTRIBUTE6 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE6_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE6_MASK) #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE7_MASK (0xFF000000U) #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE7_SHIFT (24U) /*! ATTRIBUTE7 - ATTRIBUTE7 */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE7(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE7_SHIFT)) & GPU_MALI_GPU_REGISTERS_MEMATTR_HI_ATTRIBUTE7_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_MEMATTR_HI */ #define GPU_MALI_GPU_REGISTERS_MEMATTR_HI_COUNT (8U) /*! @name LOCKADDR_LO - LOCKADDR_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_SIZE_MASK (0x3FU) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_SIZE_SHIFT (0U) /*! LOCKADDR_SIZE - LOCKADDR_SIZE */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_SIZE_SHIFT)) & GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_SIZE_MASK) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_reserved_word0_bit6_width6_MASK (0xFC0U) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_reserved_word0_bit6_width6_SHIFT (6U) /*! reserved_word0_bit6_width6 - reserved_word0_bit6_width6 */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_reserved_word0_bit6_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_reserved_word0_bit6_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_reserved_word0_bit6_width6_MASK) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_BASE_MASK (0xFFFFF000U) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_BASE_SHIFT (12U) /*! LOCKADDR_BASE - LOCKADDR_BASE */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_BASE_SHIFT)) & GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_LOCKADDR_BASE_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_LOCKADDR_LO */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_LO_COUNT (8U) /*! @name LOCKADDR_HI - LOCKADDR_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_MASK (0xFFFFU) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_SHIFT (0U) /*! LOCKADDR_BASE - LOCKADDR_BASE */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_SHIFT)) & GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_MASK) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_RESERVED_MASK (0xFFFF0000U) #define GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_RESERVED_SHIFT (16U) /*! LOCKADDR_BASE_RESERVED - LOCKADDR_BASE_RESERVED */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_RESERVED_SHIFT)) & GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_LOCKADDR_BASE_RESERVED_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_LOCKADDR_HI */ #define GPU_MALI_GPU_REGISTERS_LOCKADDR_HI_COUNT (8U) /*! @name COMMAND - COMMAND */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_COMMAND_command_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_COMMAND_command_SHIFT (0U) /*! command - command * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. */ #define GPU_MALI_GPU_REGISTERS_COMMAND_command(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_COMMAND_command_SHIFT)) & GPU_MALI_GPU_REGISTERS_COMMAND_command_MASK) #define GPU_MALI_GPU_REGISTERS_COMMAND_reserved_word0_bit8_width24_MASK (0xFFFFFF00U) #define GPU_MALI_GPU_REGISTERS_COMMAND_reserved_word0_bit8_width24_SHIFT (8U) /*! reserved_word0_bit8_width24 - reserved_word0_bit8_width24 */ #define GPU_MALI_GPU_REGISTERS_COMMAND_reserved_word0_bit8_width24(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_COMMAND_reserved_word0_bit8_width24_SHIFT)) & GPU_MALI_GPU_REGISTERS_COMMAND_reserved_word0_bit8_width24_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_COMMAND */ #define GPU_MALI_GPU_REGISTERS_COMMAND_COUNT (8U) /*! @name FAULTSTATUS - FAULTSTATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFFU) #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT (0U) /*! EXCEPTION_TYPE - EXCEPTION_TYPE * 0b00000000.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00001000.. * 0b00001111.. * 0b01000000.. * 0b01000100.. * 0b01001000.. * 0b01001001.. * 0b01001010.. * 0b01001011.. * 0b01010000.. * 0b01010001.. * 0b01010101.. * 0b01011000.. * 0b01011001.. * 0b01011010.. * 0b01011011.. * 0b01100000.. * 0b01101000.. * 0b01101001.. * 0b01110000.. * 0b01110001.. * 0b01110010.. * 0b01110011.. * 0b01110100.. * 0b01110101.. * 0b01110110.. * 0b01110111.. * 0b01111000.. * 0b01111001.. * 0b01111010.. * 0b01111011.. * 0b01111100.. * 0b01111101.. * 0b01111110.. * 0b01111111.. * 0b10000000.. * 0b10001000.. * 0b10001001.. * 0b10001010.. * 0b11000000.. * 0b11000001.. * 0b11000010.. * 0b11000011.. * 0b11000100.. * 0b11001000.. * 0b11001001.. * 0b11001010.. * 0b11001011.. * 0b11011001.. * 0b11011010.. * 0b11011011.. * 0b11100000.. * 0b11100100.. * 0b11100101.. * 0b11100110.. * 0b11100111.. * 0b11101000.. * 0b11101001.. * 0b11101010.. * 0b11101011.. */ #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_EXCEPTION_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTSTATUS_EXCEPTION_TYPE_MASK) #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_ACCESS_TYPE_MASK (0x300U) #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_ACCESS_TYPE_SHIFT (8U) /*! ACCESS_TYPE - ACCESS_TYPE * 0b00.. * 0b01.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_ACCESS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTSTATUS_ACCESS_TYPE_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTSTATUS_ACCESS_TYPE_MASK) #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_reserved_word0_bit10_width6_MASK (0xFC00U) #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_reserved_word0_bit10_width6_SHIFT (10U) /*! reserved_word0_bit10_width6 - reserved_word0_bit10_width6 */ #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_reserved_word0_bit10_width6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTSTATUS_reserved_word0_bit10_width6_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTSTATUS_reserved_word0_bit10_width6_MASK) #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_SOURCE_ID_MASK (0xFFFF0000U) #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_SOURCE_ID_SHIFT (16U) /*! SOURCE_ID - SOURCE_ID */ #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTSTATUS_SOURCE_ID_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTSTATUS_SOURCE_ID_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_FAULTSTATUS */ #define GPU_MALI_GPU_REGISTERS_FAULTSTATUS_COUNT (8U) /*! @name FAULTADDRESS_LO - FAULTADDRESS_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_LO_FAULT_ADDRESS_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_LO_FAULT_ADDRESS_SHIFT (0U) /*! FAULT_ADDRESS - FAULT_ADDRESS */ #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_LO_FAULT_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTADDRESS_LO_FAULT_ADDRESS_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTADDRESS_LO_FAULT_ADDRESS_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_FAULTADDRESS_LO */ #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_LO_COUNT (8U) /*! @name FAULTADDRESS_HI - FAULTADDRESS_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_HI_FAULT_ADDRESS_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_HI_FAULT_ADDRESS_SHIFT (0U) /*! FAULT_ADDRESS - FAULT_ADDRESS */ #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_HI_FAULT_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTADDRESS_HI_FAULT_ADDRESS_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTADDRESS_HI_FAULT_ADDRESS_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_FAULTADDRESS_HI */ #define GPU_MALI_GPU_REGISTERS_FAULTADDRESS_HI_COUNT (8U) /*! @name STATUS - STATUS */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_EXT_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_EXT_SHIFT (0U) /*! AS_ACTIVE_EXT - AS_ACTIVE_EXT */ #define GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_EXT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_EXT_SHIFT)) & GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_EXT_MASK) #define GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_INT_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_INT_SHIFT (1U) /*! AS_ACTIVE_INT - AS_ACTIVE_INT */ #define GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_INT_SHIFT)) & GPU_MALI_GPU_REGISTERS_STATUS_AS_ACTIVE_INT_MASK) #define GPU_MALI_GPU_REGISTERS_STATUS_reserved_word0_bit2_width30_MASK (0xFFFFFFFCU) #define GPU_MALI_GPU_REGISTERS_STATUS_reserved_word0_bit2_width30_SHIFT (2U) /*! reserved_word0_bit2_width30 - reserved_word0_bit2_width30 */ #define GPU_MALI_GPU_REGISTERS_STATUS_reserved_word0_bit2_width30(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_STATUS_reserved_word0_bit2_width30_SHIFT)) & GPU_MALI_GPU_REGISTERS_STATUS_reserved_word0_bit2_width30_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_STATUS */ #define GPU_MALI_GPU_REGISTERS_STATUS_COUNT (8U) /*! @name TRANSCFG_LO - TRANSCFG_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_MODE_MASK (0xFU) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_MODE_SHIFT (0U) /*! MODE - MODE * 0b0001.. * 0b0010.. * 0b0110.. * 0b1000.. */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_MODE_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_MODE_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit4_width2_MASK (0x30U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit4_width2_SHIFT (4U) /*! reserved_word0_bit4_width2 - reserved_word0_bit4_width2 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit4_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit4_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit4_width2_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_INA_BITS_MASK (0x7C0U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_INA_BITS_SHIFT (6U) /*! INA_BITS - INA_BITS * 0b00111.. * 0b01000.. * 0b01001.. * 0b01010.. * 0b01011.. * 0b01100.. * 0b01101.. * 0b01110.. * 0b01111.. * 0b10000.. * 0b10001.. * 0b10010.. * 0b10011.. * 0b10100.. * 0b10101.. * 0b10110.. * 0b10111.. * 0b11000.. * 0b11001.. * 0b11010.. * 0b11011.. * 0b11100.. * 0b11101.. * 0b11110.. */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_INA_BITS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_INA_BITS_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_INA_BITS_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit11_width3_MASK (0x3800U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit11_width3_SHIFT (11U) /*! reserved_word0_bit11_width3 - reserved_word0_bit11_width3 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit11_width3(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit11_width3_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit11_width3_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_OUTA_BITS_MASK (0x7C000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_OUTA_BITS_SHIFT (14U) /*! OUTA_BITS - OUTA_BITS */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_OUTA_BITS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_OUTA_BITS_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_OUTA_BITS_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit19_width3_MASK (0x380000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit19_width3_SHIFT (19U) /*! reserved_word0_bit19_width3 - reserved_word0_bit19_width3 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit19_width3(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit19_width3_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit19_width3_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_SL_CONCAT_EN_MASK (0x400000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_SL_CONCAT_EN_SHIFT (22U) /*! SL_CONCAT_EN - SL_CONCAT_EN */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_SL_CONCAT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_SL_CONCAT_EN_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_SL_CONCAT_EN_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit23_width1_MASK (0x800000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit23_width1_SHIFT (23U) /*! reserved_word0_bit23_width1 - reserved_word0_bit23_width1 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit23_width1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit23_width1_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit23_width1_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_MEMATTR_MASK (0x3000000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_MEMATTR_SHIFT (24U) /*! PTW_MEMATTR - PTW_MEMATTR * 0b01.. * 0b10.. */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_MEMATTR(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_MEMATTR_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_MEMATTR_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit26_width2_MASK (0xC000000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit26_width2_SHIFT (26U) /*! reserved_word0_bit26_width2 - reserved_word0_bit26_width2 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit26_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit26_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit26_width2_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_SH_MASK (0x30000000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_SH_SHIFT (28U) /*! PTW_SH - PTW_SH * 0b00.. * 0b10.. * 0b11.. */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_SH(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_SH_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_PTW_SH_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_R_ALLOCATE_MASK (0x40000000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_R_ALLOCATE_SHIFT (30U) /*! R_ALLOCATE - R_ALLOCATE * 0b0.. * 0b1.. */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_R_ALLOCATE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_R_ALLOCATE_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_R_ALLOCATE_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit31_width2_MASK (0x80000000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit31_width2_SHIFT (31U) /*! reserved_word0_bit31_width2 - reserved_word0_bit31_width2 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit31_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit31_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_reserved_word0_bit31_width2_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_TRANSCFG_LO */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_LO_COUNT (8U) /*! @name TRANSCFG_HI - TRANSCFG_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit31_width2_MASK (0x1U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit31_width2_SHIFT (0U) /*! reserved_word0_bit31_width2 - reserved_word0_bit31_width2 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit31_width2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit31_width2_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit31_width2_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_HIER_AP_MASK (0x2U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_HIER_AP_SHIFT (1U) /*! DISABLE_HIER_AP - DISABLE_HIER_AP */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_HIER_AP(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_HIER_AP_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_HIER_AP_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_AF_FAULT_MASK (0x4U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_AF_FAULT_SHIFT (2U) /*! DISABLE_AF_FAULT - DISABLE_AF_FAULT */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_AF_FAULT(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_AF_FAULT_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_DISABLE_AF_FAULT_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_WXN_MASK (0x8U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_WXN_SHIFT (3U) /*! WXN - WXN */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_WXN(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_WXN_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_WXN_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_XREADABLE_MASK (0x10U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_XREADABLE_SHIFT (4U) /*! XREADABLE - XREADABLE */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_XREADABLE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_XREADABLE_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_XREADABLE_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit37_width23_MASK (0xFFFFFE0U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit37_width23_SHIFT (5U) /*! reserved_word0_bit37_width23 - reserved_word0_bit37_width23 */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit37_width23(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit37_width23_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_reserved_word0_bit37_width23_MASK) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_PTW_PBHA_MASK (0xF0000000U) #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_PTW_PBHA_SHIFT (28U) /*! PTW_PBHA - PTW_PBHA */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_PTW_PBHA(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_PTW_PBHA_SHIFT)) & GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_PTW_PBHA_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_TRANSCFG_HI */ #define GPU_MALI_GPU_REGISTERS_TRANSCFG_HI_COUNT (8U) /*! @name FAULTEXTRA_LO - FAULTEXTRA_LO */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_LO_FAULT_ADDRESS_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_LO_FAULT_ADDRESS_SHIFT (0U) /*! FAULT_ADDRESS - FAULT_ADDRESS */ #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_LO_FAULT_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTEXTRA_LO_FAULT_ADDRESS_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTEXTRA_LO_FAULT_ADDRESS_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_FAULTEXTRA_LO */ #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_LO_COUNT (8U) /*! @name FAULTEXTRA_HI - FAULTEXTRA_HI */ /*! @{ */ #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_HI_FAULT_ADDRESS_MASK (0xFFFFFFFFU) #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_HI_FAULT_ADDRESS_SHIFT (0U) /*! FAULT_ADDRESS - FAULT_ADDRESS */ #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_HI_FAULT_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_GPU_REGISTERS_FAULTEXTRA_HI_FAULT_ADDRESS_SHIFT)) & GPU_MALI_GPU_REGISTERS_FAULTEXTRA_HI_FAULT_ADDRESS_MASK) /*! @} */ /* The count of GPU_MALI_GPU_REGISTERS_FAULTEXTRA_HI */ #define GPU_MALI_GPU_REGISTERS_FAULTEXTRA_HI_COUNT (8U) /*! * @} */ /* end of group GPU_MALI_GPU_REGISTERS_Register_Masks */ /* GPU_MALI_GPU_REGISTERS - Peripheral instance base addresses */ /** Peripheral GPU__REG__GPU_MALI_GPU_REGISTERS base address */ #define GPU__REG__GPU_MALI_GPU_REGISTERS_BASE (0x4D900000u) /** Peripheral GPU__REG__GPU_MALI_GPU_REGISTERS base pointer */ #define GPU__REG__GPU_MALI_GPU_REGISTERS ((GPU_MALI_GPU_REGISTERS_Type *)GPU__REG__GPU_MALI_GPU_REGISTERS_BASE) /** Array initializer of GPU_MALI_GPU_REGISTERS peripheral base addresses */ #define GPU_MALI_GPU_REGISTERS_BASE_ADDRS { GPU__REG__GPU_MALI_GPU_REGISTERS_BASE } /** Array initializer of GPU_MALI_GPU_REGISTERS peripheral base pointers */ #define GPU_MALI_GPU_REGISTERS_BASE_PTRS { GPU__REG__GPU_MALI_GPU_REGISTERS } /*! * @} */ /* end of group GPU_MALI_GPU_REGISTERS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPU_MALI_IPA_CONTROL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_IPA_CONTROL_Peripheral_Access_Layer GPU_MALI_IPA_CONTROL Peripheral Access Layer * @{ */ /** GPU_MALI_IPA_CONTROL - Register Layout Typedef */ typedef struct { __IO uint32_t COMMAND; /**< COMMAND, offset: 0x0 */ __I uint32_t STATUS; /**< STATUS, offset: 0x4 */ __IO uint32_t TIMER; /**< TIMER, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t SELECT_CSHW_LO; /**< SELECT_CSHW_LO, offset: 0x10 */ __IO uint32_t SELECT_CSHW_HI; /**< SELECT_CSHW_HI, offset: 0x14 */ __IO uint32_t SELECT_MEMSYS_LO; /**< SELECT_MEMSYS_LO, offset: 0x18 */ __IO uint32_t SELECT_MEMSYS_HI; /**< SELECT_MEMSYS_HI, offset: 0x1C */ __IO uint32_t SELECT_TILER_LO; /**< SELECT_TILER_LO, offset: 0x20 */ __IO uint32_t SELECT_TILER_HI; /**< SELECT_TILER_HI, offset: 0x24 */ __IO uint32_t SELECT_SHADER_LO; /**< SELECT_SHADER_LO, offset: 0x28 */ __IO uint32_t SELECT_SHADER_HI; /**< SELECT_SHADER_HI, offset: 0x2C */ uint8_t RESERVED_1[208]; __I uint32_t VALUE_CSHW_N_LO_0; /**< VALUE_CSHW_N_LO_0, offset: 0x100 */ __I uint32_t VALUE_CSHW_N_HI_0; /**< VALUE_CSHW_N_HI_0, offset: 0x104 */ __I uint32_t VALUE_CSHW_N_LO_1; /**< VALUE_CSHW_N_LO_1, offset: 0x108 */ __I uint32_t VALUE_CSHW_N_HI_1; /**< VALUE_CSHW_N_HI_1, offset: 0x10C */ __I uint32_t VALUE_CSHW_N_LO_2; /**< VALUE_CSHW_N_LO_2, offset: 0x110 */ __I uint32_t VALUE_CSHW_N_HI_2; /**< VALUE_CSHW_N_HI_2, offset: 0x114 */ __I uint32_t VALUE_CSHW_N_LO_3; /**< VALUE_CSHW_N_LO_3, offset: 0x118 */ __I uint32_t VALUE_CSHW_N_HI_3; /**< VALUE_CSHW_N_HI_3, offset: 0x11C */ __I uint32_t VALUE_CSHW_N_LO_4; /**< VALUE_CSHW_N_LO_4, offset: 0x120 */ __I uint32_t VALUE_CSHW_N_HI_4; /**< VALUE_CSHW_N_HI_4, offset: 0x124 */ __I uint32_t VALUE_CSHW_N_LO_5; /**< VALUE_CSHW_N_LO_5, offset: 0x128 */ __I uint32_t VALUE_CSHW_N_HI_5; /**< VALUE_CSHW_N_HI_5, offset: 0x12C */ __I uint32_t VALUE_CSHW_N_LO_6; /**< VALUE_CSHW_N_LO_6, offset: 0x130 */ __I uint32_t VALUE_CSHW_N_HI_6; /**< VALUE_CSHW_N_HI_6, offset: 0x134 */ __I uint32_t VALUE_CSHW_N_LO_7; /**< VALUE_CSHW_N_LO_7, offset: 0x138 */ __I uint32_t VALUE_CSHW_N_HI_7; /**< VALUE_CSHW_N_HI_7, offset: 0x13C */ __I uint32_t VALUE_MEMSYS_N_LO_0; /**< VALUE_MEMSYS_N_LO_0, offset: 0x140 */ __I uint32_t VALUE_MEMSYS_N_HI_0; /**< VALUE_MEMSYS_N_HI_0, offset: 0x144 */ __I uint32_t VALUE_MEMSYS_N_LO_1; /**< VALUE_MEMSYS_N_LO_1, offset: 0x148 */ __I uint32_t VALUE_MEMSYS_N_HI_1; /**< VALUE_MEMSYS_N_HI_1, offset: 0x14C */ __I uint32_t VALUE_MEMSYS_N_LO_2; /**< VALUE_MEMSYS_N_LO_2, offset: 0x150 */ __I uint32_t VALUE_MEMSYS_N_HI_2; /**< VALUE_MEMSYS_N_HI_2, offset: 0x154 */ __I uint32_t VALUE_MEMSYS_N_LO_3; /**< VALUE_MEMSYS_N_LO_3, offset: 0x158 */ __I uint32_t VALUE_MEMSYS_N_HI_3; /**< VALUE_MEMSYS_N_HI_3, offset: 0x15C */ __I uint32_t VALUE_MEMSYS_N_LO_4; /**< VALUE_MEMSYS_N_LO_4, offset: 0x160 */ __I uint32_t VALUE_MEMSYS_N_HI_4; /**< VALUE_MEMSYS_N_HI_4, offset: 0x164 */ __I uint32_t VALUE_MEMSYS_N_LO_5; /**< VALUE_MEMSYS_N_LO_5, offset: 0x168 */ __I uint32_t VALUE_MEMSYS_N_HI_5; /**< VALUE_MEMSYS_N_HI_5, offset: 0x16C */ __I uint32_t VALUE_MEMSYS_N_LO_6; /**< VALUE_MEMSYS_N_LO_6, offset: 0x170 */ __I uint32_t VALUE_MEMSYS_N_HI_6; /**< VALUE_MEMSYS_N_HI_6, offset: 0x174 */ __I uint32_t VALUE_MEMSYS_N_LO_7; /**< VALUE_MEMSYS_N_LO_7, offset: 0x178 */ __I uint32_t VALUE_MEMSYS_N_HI_7; /**< VALUE_MEMSYS_N_HI_7, offset: 0x17C */ __I uint32_t VALUE_TILER_N_LO_0; /**< VALUE_TILER_N_LO_0, offset: 0x180 */ __I uint32_t VALUE_TILER_N_HI_0; /**< VALUE_TILER_N_HI_0, offset: 0x184 */ __I uint32_t VALUE_TILER_N_LO_1; /**< VALUE_TILER_N_LO_1, offset: 0x188 */ __I uint32_t VALUE_TILER_N_HI_1; /**< VALUE_TILER_N_HI_1, offset: 0x18C */ __I uint32_t VALUE_TILER_N_LO_2; /**< VALUE_TILER_N_LO_2, offset: 0x190 */ __I uint32_t VALUE_TILER_N_HI_2; /**< VALUE_TILER_N_HI_2, offset: 0x194 */ __I uint32_t VALUE_TILER_N_LO_3; /**< VALUE_TILER_N_LO_3, offset: 0x198 */ __I uint32_t VALUE_TILER_N_HI_3; /**< VALUE_TILER_N_HI_3, offset: 0x19C */ __I uint32_t VALUE_TILER_N_LO_4; /**< VALUE_TILER_N_LO_4, offset: 0x1A0 */ __I uint32_t VALUE_TILER_N_HI_4; /**< VALUE_TILER_N_HI_4, offset: 0x1A4 */ __I uint32_t VALUE_TILER_N_LO_5; /**< VALUE_TILER_N_LO_5, offset: 0x1A8 */ __I uint32_t VALUE_TILER_N_HI_5; /**< VALUE_TILER_N_HI_5, offset: 0x1AC */ __I uint32_t VALUE_TILER_N_LO_6; /**< VALUE_TILER_N_LO_6, offset: 0x1B0 */ __I uint32_t VALUE_TILER_N_HI_6; /**< VALUE_TILER_N_HI_6, offset: 0x1B4 */ __I uint32_t VALUE_TILER_N_LO_7; /**< VALUE_TILER_N_LO_7, offset: 0x1B8 */ __I uint32_t VALUE_TILER_N_HI_7; /**< VALUE_TILER_N_HI_7, offset: 0x1BC */ __I uint32_t VALUE_SHADER_N_LO_0; /**< VALUE_SHADER_N_LO_0, offset: 0x1C0 */ __I uint32_t VALUE_SHADER_N_HI_0; /**< VALUE_SHADER_N_HI_0, offset: 0x1C4 */ __I uint32_t VALUE_SHADER_N_LO_1; /**< VALUE_SHADER_N_LO_1, offset: 0x1C8 */ __I uint32_t VALUE_SHADER_N_HI_1; /**< VALUE_SHADER_N_HI_1, offset: 0x1CC */ __I uint32_t VALUE_SHADER_N_LO_2; /**< VALUE_SHADER_N_LO_2, offset: 0x1D0 */ __I uint32_t VALUE_SHADER_N_HI_2; /**< VALUE_SHADER_N_HI_2, offset: 0x1D4 */ __I uint32_t VALUE_SHADER_N_LO_3; /**< VALUE_SHADER_N_LO_3, offset: 0x1D8 */ __I uint32_t VALUE_SHADER_N_HI_3; /**< VALUE_SHADER_N_HI_3, offset: 0x1DC */ __I uint32_t VALUE_SHADER_N_LO_4; /**< VALUE_SHADER_N_LO_4, offset: 0x1E0 */ __I uint32_t VALUE_SHADER_N_HI_4; /**< VALUE_SHADER_N_HI_4, offset: 0x1E4 */ __I uint32_t VALUE_SHADER_N_LO_5; /**< VALUE_SHADER_N_LO_5, offset: 0x1E8 */ __I uint32_t VALUE_SHADER_N_HI_5; /**< VALUE_SHADER_N_HI_5, offset: 0x1EC */ __I uint32_t VALUE_SHADER_N_LO_6; /**< VALUE_SHADER_N_LO_6, offset: 0x1F0 */ __I uint32_t VALUE_SHADER_N_HI_6; /**< VALUE_SHADER_N_HI_6, offset: 0x1F4 */ __I uint32_t VALUE_SHADER_N_LO_7; /**< VALUE_SHADER_N_LO_7, offset: 0x1F8 */ __I uint32_t VALUE_SHADER_N_HI_7; /**< VALUE_SHADER_N_HI_7, offset: 0x1FC */ } GPU_MALI_IPA_CONTROL_Type; /* ---------------------------------------------------------------------------- -- GPU_MALI_IPA_CONTROL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_IPA_CONTROL_Register_Masks GPU_MALI_IPA_CONTROL Register Masks * @{ */ /*! @name COMMAND - COMMAND */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_COMMAND_command_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_COMMAND_command_SHIFT (0U) /*! command - command * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. */ #define GPU_MALI_IPA_CONTROL_COMMAND_command(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_COMMAND_command_SHIFT)) & GPU_MALI_IPA_CONTROL_COMMAND_command_MASK) #define GPU_MALI_IPA_CONTROL_COMMAND_reserved_word0_bit8_width24_MASK (0xFFFFFF00U) #define GPU_MALI_IPA_CONTROL_COMMAND_reserved_word0_bit8_width24_SHIFT (8U) /*! reserved_word0_bit8_width24 - reserved_word0_bit8_width24 */ #define GPU_MALI_IPA_CONTROL_COMMAND_reserved_word0_bit8_width24(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_COMMAND_reserved_word0_bit8_width24_SHIFT)) & GPU_MALI_IPA_CONTROL_COMMAND_reserved_word0_bit8_width24_MASK) /*! @} */ /*! @name STATUS - STATUS */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_STATUS_command_active_MASK (0x1U) #define GPU_MALI_IPA_CONTROL_STATUS_command_active_SHIFT (0U) /*! command_active - command_active */ #define GPU_MALI_IPA_CONTROL_STATUS_command_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_command_active_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_command_active_MASK) #define GPU_MALI_IPA_CONTROL_STATUS_timer_active_MASK (0x2U) #define GPU_MALI_IPA_CONTROL_STATUS_timer_active_SHIFT (1U) /*! timer_active - timer_active */ #define GPU_MALI_IPA_CONTROL_STATUS_timer_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_timer_active_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_timer_active_MASK) #define GPU_MALI_IPA_CONTROL_STATUS_auto_active_MASK (0x4U) #define GPU_MALI_IPA_CONTROL_STATUS_auto_active_SHIFT (2U) /*! auto_active - auto_active */ #define GPU_MALI_IPA_CONTROL_STATUS_auto_active(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_auto_active_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_auto_active_MASK) #define GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit3_width5_MASK (0xF8U) #define GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit3_width5_SHIFT (3U) /*! reserved_word0_bit3_width5 - reserved_word0_bit3_width5 */ #define GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit3_width5(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit3_width5_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit3_width5_MASK) #define GPU_MALI_IPA_CONTROL_STATUS_protected_mode_MASK (0x100U) #define GPU_MALI_IPA_CONTROL_STATUS_protected_mode_SHIFT (8U) /*! protected_mode - protected_mode */ #define GPU_MALI_IPA_CONTROL_STATUS_protected_mode(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_protected_mode_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_protected_mode_MASK) #define GPU_MALI_IPA_CONTROL_STATUS_reset_MASK (0x200U) #define GPU_MALI_IPA_CONTROL_STATUS_reset_SHIFT (9U) /*! reset - reset */ #define GPU_MALI_IPA_CONTROL_STATUS_reset(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_reset_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_reset_MASK) #define GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit10_width21_MASK (0x7FFFFC00U) #define GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit10_width21_SHIFT (10U) /*! reserved_word0_bit10_width21 - reserved_word0_bit10_width21 */ #define GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit10_width21(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit10_width21_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_reserved_word0_bit10_width21_MASK) #define GPU_MALI_IPA_CONTROL_STATUS_timer_enabled_MASK (0x80000000U) #define GPU_MALI_IPA_CONTROL_STATUS_timer_enabled_SHIFT (31U) /*! timer_enabled - timer_enabled */ #define GPU_MALI_IPA_CONTROL_STATUS_timer_enabled(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_STATUS_timer_enabled_SHIFT)) & GPU_MALI_IPA_CONTROL_STATUS_timer_enabled_MASK) /*! @} */ /*! @name TIMER - TIMER */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_TIMER_timeout_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_TIMER_timeout_SHIFT (0U) /*! timeout - timeout */ #define GPU_MALI_IPA_CONTROL_TIMER_timeout(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_TIMER_timeout_SHIFT)) & GPU_MALI_IPA_CONTROL_TIMER_timeout_MASK) /*! @} */ /*! @name SELECT_CSHW_LO - SELECT_CSHW_LO */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select0_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select0_SHIFT (0U) /*! select0 - select0 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select0(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select0_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select0_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select1_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select1_SHIFT (8U) /*! select1 - select1 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select1_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select1_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select2_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select2_SHIFT (16U) /*! select2 - select2 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select2_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select2_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select3_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select3_SHIFT (24U) /*! select3 - select3 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select3(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select3_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_LO_select3_MASK) /*! @} */ /*! @name SELECT_CSHW_HI - SELECT_CSHW_HI */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select4_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select4_SHIFT (0U) /*! select4 - select4 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select4(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select4_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select4_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select5_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select5_SHIFT (8U) /*! select5 - select5 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select5(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select5_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select5_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select6_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select6_SHIFT (16U) /*! select6 - select6 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select6_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select6_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select7_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select7_SHIFT (24U) /*! select7 - select7 */ #define GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select7(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select7_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_CSHW_HI_select7_MASK) /*! @} */ /*! @name SELECT_MEMSYS_LO - SELECT_MEMSYS_LO */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select0_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select0_SHIFT (0U) /*! select0 - select0 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select0(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select0_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select0_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select1_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select1_SHIFT (8U) /*! select1 - select1 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select1_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select1_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select2_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select2_SHIFT (16U) /*! select2 - select2 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select2_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select2_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select3_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select3_SHIFT (24U) /*! select3 - select3 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select3(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select3_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_LO_select3_MASK) /*! @} */ /*! @name SELECT_MEMSYS_HI - SELECT_MEMSYS_HI */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select4_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select4_SHIFT (0U) /*! select4 - select4 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select4(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select4_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select4_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select5_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select5_SHIFT (8U) /*! select5 - select5 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select5(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select5_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select5_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select6_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select6_SHIFT (16U) /*! select6 - select6 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select6_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select6_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select7_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select7_SHIFT (24U) /*! select7 - select7 */ #define GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select7(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select7_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_MEMSYS_HI_select7_MASK) /*! @} */ /*! @name SELECT_TILER_LO - SELECT_TILER_LO */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select0_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select0_SHIFT (0U) /*! select0 - select0 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select0(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select0_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select0_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select1_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select1_SHIFT (8U) /*! select1 - select1 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select1_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select1_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select2_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select2_SHIFT (16U) /*! select2 - select2 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select2_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select2_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select3_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select3_SHIFT (24U) /*! select3 - select3 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select3(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select3_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_LO_select3_MASK) /*! @} */ /*! @name SELECT_TILER_HI - SELECT_TILER_HI */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select4_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select4_SHIFT (0U) /*! select4 - select4 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select4(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select4_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select4_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select5_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select5_SHIFT (8U) /*! select5 - select5 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select5(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select5_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select5_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select6_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select6_SHIFT (16U) /*! select6 - select6 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select6_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select6_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select7_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select7_SHIFT (24U) /*! select7 - select7 */ #define GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select7(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select7_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_TILER_HI_select7_MASK) /*! @} */ /*! @name SELECT_SHADER_LO - SELECT_SHADER_LO */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select0_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select0_SHIFT (0U) /*! select0 - select0 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select0(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select0_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select0_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select1_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select1_SHIFT (8U) /*! select1 - select1 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select1(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select1_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select1_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select2_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select2_SHIFT (16U) /*! select2 - select2 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select2(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select2_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select2_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select3_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select3_SHIFT (24U) /*! select3 - select3 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select3(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select3_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_LO_select3_MASK) /*! @} */ /*! @name SELECT_SHADER_HI - SELECT_SHADER_HI */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select4_MASK (0xFFU) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select4_SHIFT (0U) /*! select4 - select4 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select4(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select4_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select4_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select5_MASK (0xFF00U) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select5_SHIFT (8U) /*! select5 - select5 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select5(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select5_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select5_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select6_MASK (0xFF0000U) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select6_SHIFT (16U) /*! select6 - select6 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select6(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select6_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select6_MASK) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select7_MASK (0xFF000000U) #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select7_SHIFT (24U) /*! select7 - select7 */ #define GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select7(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select7_SHIFT)) & GPU_MALI_IPA_CONTROL_SELECT_SHADER_HI_select7_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_0 - VALUE_CSHW_N_LO_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_0_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_0 - VALUE_CSHW_N_HI_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_0_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_1 - VALUE_CSHW_N_LO_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_1_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_1 - VALUE_CSHW_N_HI_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_1_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_2 - VALUE_CSHW_N_LO_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_2_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_2 - VALUE_CSHW_N_HI_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_2_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_3 - VALUE_CSHW_N_LO_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_3_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_3 - VALUE_CSHW_N_HI_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_3_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_4 - VALUE_CSHW_N_LO_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_4_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_4 - VALUE_CSHW_N_HI_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_4_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_5 - VALUE_CSHW_N_LO_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_5_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_5 - VALUE_CSHW_N_HI_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_5_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_6 - VALUE_CSHW_N_LO_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_6_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_6 - VALUE_CSHW_N_HI_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_6_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_LO_7 - VALUE_CSHW_N_LO_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_LO_7_value_MASK) /*! @} */ /*! @name VALUE_CSHW_N_HI_7 - VALUE_CSHW_N_HI_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_CSHW_N_HI_7_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_0 - VALUE_MEMSYS_N_LO_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_0_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_0 - VALUE_MEMSYS_N_HI_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_0_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_1 - VALUE_MEMSYS_N_LO_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_1_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_1 - VALUE_MEMSYS_N_HI_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_1_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_2 - VALUE_MEMSYS_N_LO_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_2_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_2 - VALUE_MEMSYS_N_HI_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_2_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_3 - VALUE_MEMSYS_N_LO_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_3_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_3 - VALUE_MEMSYS_N_HI_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_3_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_4 - VALUE_MEMSYS_N_LO_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_4_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_4 - VALUE_MEMSYS_N_HI_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_4_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_5 - VALUE_MEMSYS_N_LO_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_5_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_5 - VALUE_MEMSYS_N_HI_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_5_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_6 - VALUE_MEMSYS_N_LO_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_6_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_6 - VALUE_MEMSYS_N_HI_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_6_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_LO_7 - VALUE_MEMSYS_N_LO_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_LO_7_value_MASK) /*! @} */ /*! @name VALUE_MEMSYS_N_HI_7 - VALUE_MEMSYS_N_HI_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_MEMSYS_N_HI_7_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_0 - VALUE_TILER_N_LO_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_0_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_0 - VALUE_TILER_N_HI_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_0_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_1 - VALUE_TILER_N_LO_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_1_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_1 - VALUE_TILER_N_HI_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_1_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_2 - VALUE_TILER_N_LO_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_2_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_2 - VALUE_TILER_N_HI_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_2_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_3 - VALUE_TILER_N_LO_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_3_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_3 - VALUE_TILER_N_HI_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_3_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_4 - VALUE_TILER_N_LO_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_4_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_4 - VALUE_TILER_N_HI_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_4_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_5 - VALUE_TILER_N_LO_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_5_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_5 - VALUE_TILER_N_HI_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_5_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_6 - VALUE_TILER_N_LO_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_6_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_6 - VALUE_TILER_N_HI_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_6_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_LO_7 - VALUE_TILER_N_LO_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_LO_7_value_MASK) /*! @} */ /*! @name VALUE_TILER_N_HI_7 - VALUE_TILER_N_HI_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_TILER_N_HI_7_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_0 - VALUE_SHADER_N_LO_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_0_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_0 - VALUE_SHADER_N_HI_0 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_0_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_0_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_0_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_0_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_0_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_1 - VALUE_SHADER_N_LO_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_1_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_1 - VALUE_SHADER_N_HI_1 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_1_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_1_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_1_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_1_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_1_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_2 - VALUE_SHADER_N_LO_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_2_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_2 - VALUE_SHADER_N_HI_2 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_2_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_2_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_2_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_2_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_2_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_3 - VALUE_SHADER_N_LO_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_3_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_3 - VALUE_SHADER_N_HI_3 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_3_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_3_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_3_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_3_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_3_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_4 - VALUE_SHADER_N_LO_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_4_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_4 - VALUE_SHADER_N_HI_4 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_4_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_4_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_4_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_4_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_4_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_5 - VALUE_SHADER_N_LO_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_5_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_5 - VALUE_SHADER_N_HI_5 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_5_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_5_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_5_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_5_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_5_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_6 - VALUE_SHADER_N_LO_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_6_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_6 - VALUE_SHADER_N_HI_6 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_6_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_6_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_6_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_6_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_6_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_LO_7 - VALUE_SHADER_N_LO_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_LO_7_value_MASK) /*! @} */ /*! @name VALUE_SHADER_N_HI_7 - VALUE_SHADER_N_HI_7 */ /*! @{ */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_7_value_MASK (0xFFFFFFFFU) #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_7_value_SHIFT (0U) /*! value - value */ #define GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_7_value(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_7_value_SHIFT)) & GPU_MALI_IPA_CONTROL_VALUE_SHADER_N_HI_7_value_MASK) /*! @} */ /*! * @} */ /* end of group GPU_MALI_IPA_CONTROL_Register_Masks */ /* GPU_MALI_IPA_CONTROL - Peripheral instance base addresses */ /** Peripheral GPU__REG__GPU_MALI_IPA_CONTROL base address */ #define GPU__REG__GPU_MALI_IPA_CONTROL_BASE (0x4D940000u) /** Peripheral GPU__REG__GPU_MALI_IPA_CONTROL base pointer */ #define GPU__REG__GPU_MALI_IPA_CONTROL ((GPU_MALI_IPA_CONTROL_Type *)GPU__REG__GPU_MALI_IPA_CONTROL_BASE) /** Array initializer of GPU_MALI_IPA_CONTROL peripheral base addresses */ #define GPU_MALI_IPA_CONTROL_BASE_ADDRS { GPU__REG__GPU_MALI_IPA_CONTROL_BASE } /** Array initializer of GPU_MALI_IPA_CONTROL peripheral base pointers */ #define GPU_MALI_IPA_CONTROL_BASE_PTRS { GPU__REG__GPU_MALI_IPA_CONTROL } /*! * @} */ /* end of group GPU_MALI_IPA_CONTROL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPU_MALI_USER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_USER_Peripheral_Access_Layer GPU_MALI_USER Peripheral Access Layer * @{ */ /** GPU_MALI_USER - Register Layout Typedef */ typedef struct { __I uint32_t LATEST_FLUSH; /**< LATEST_FLUSH, offset: 0x0 */ } GPU_MALI_USER_Type; /* ---------------------------------------------------------------------------- -- GPU_MALI_USER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_MALI_USER_Register_Masks GPU_MALI_USER Register Masks * @{ */ /*! @name LATEST_FLUSH - LATEST_FLUSH */ /*! @{ */ #define GPU_MALI_USER_LATEST_FLUSH_flush_id_MASK (0xFFFFFFU) #define GPU_MALI_USER_LATEST_FLUSH_flush_id_SHIFT (0U) /*! flush_id - flush_id */ #define GPU_MALI_USER_LATEST_FLUSH_flush_id(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_USER_LATEST_FLUSH_flush_id_SHIFT)) & GPU_MALI_USER_LATEST_FLUSH_flush_id_MASK) #define GPU_MALI_USER_LATEST_FLUSH_reserved_word0_bit24_width7_MASK (0x7F000000U) #define GPU_MALI_USER_LATEST_FLUSH_reserved_word0_bit24_width7_SHIFT (24U) /*! reserved_word0_bit24_width7 - reserved_word0_bit24_width7 */ #define GPU_MALI_USER_LATEST_FLUSH_reserved_word0_bit24_width7(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_USER_LATEST_FLUSH_reserved_word0_bit24_width7_SHIFT)) & GPU_MALI_USER_LATEST_FLUSH_reserved_word0_bit24_width7_MASK) #define GPU_MALI_USER_LATEST_FLUSH_ACTIVE_MASK (0x80000000U) #define GPU_MALI_USER_LATEST_FLUSH_ACTIVE_SHIFT (31U) /*! ACTIVE - ACTIVE */ #define GPU_MALI_USER_LATEST_FLUSH_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPU_MALI_USER_LATEST_FLUSH_ACTIVE_SHIFT)) & GPU_MALI_USER_LATEST_FLUSH_ACTIVE_MASK) /*! @} */ /*! * @} */ /* end of group GPU_MALI_USER_Register_Masks */ /* GPU_MALI_USER - Peripheral instance base addresses */ /** Peripheral GPU__REG__GPU_MALI_USER base address */ #define GPU__REG__GPU_MALI_USER_BASE (0x4D910000u) /** Peripheral GPU__REG__GPU_MALI_USER base pointer */ #define GPU__REG__GPU_MALI_USER ((GPU_MALI_USER_Type *)GPU__REG__GPU_MALI_USER_BASE) /** Array initializer of GPU_MALI_USER peripheral base addresses */ #define GPU_MALI_USER_BASE_ADDRS { GPU__REG__GPU_MALI_USER_BASE } /** Array initializer of GPU_MALI_USER peripheral base pointers */ #define GPU_MALI_USER_BASE_PTRS { GPU__REG__GPU_MALI_USER } /*! * @} */ /* end of group GPU_MALI_USER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPU_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_TCU_Peripheral_Access_Layer GPU_TCU Peripheral Access Layer * @{ */ /** GPU_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_3[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } GPU_TCU_Type; /* ---------------------------------------------------------------------------- -- GPU_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPU_TCU_Register_Masks GPU_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define GPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define GPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define GPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & GPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define GPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define GPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define GPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & GPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define GPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define GPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & GPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define GPU_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & GPU_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define GPU_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & GPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define GPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & GPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define GPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & GPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define GPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define GPU_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & GPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define GPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define GPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define GPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & GPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define GPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x2U) #define GPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define GPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << GPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & GPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group GPU_TCU_Register_Masks */ /* GPU_TCU - Peripheral instance base addresses */ /** Peripheral GPU__TCU base address */ #define GPU__TCU_BASE (0x4D800000u) /** Peripheral GPU__TCU base pointer */ #define GPU__TCU ((GPU_TCU_Type *)GPU__TCU_BASE) /** Array initializer of GPU_TCU peripheral base addresses */ #define GPU_TCU_BASE_ADDRS { GPU__TCU_BASE } /** Array initializer of GPU_TCU peripheral base pointers */ #define GPU_TCU_BASE_PTRS { GPU__TCU } /*! * @} */ /* end of group GPU_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HC_Peripheral_Access_Layer HC Peripheral Access Layer * @{ */ /** HC - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL_CAM[1]; /**< Camera 0 Head Color Control, array offset: 0x0, array step: 0x4 */ } HC_Type; /* ---------------------------------------------------------------------------- -- HC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HC_Register_Masks HC Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 Head Color Control */ /*! @{ */ #define HC_CTRL_CAM_HOFFSET_MASK (0x3U) #define HC_CTRL_CAM_HOFFSET_SHIFT (0U) /*! HOFFSET * 0b00..RED component is at 0 th pixel position. * 0b01..RED component is at 1 st pixel position. * 0b10..RED component is at 2 nd pixel position. * 0b11..RED component is at 3 rd pixel position. */ #define HC_CTRL_CAM_HOFFSET(x) (((uint32_t)(((uint32_t)(x)) << HC_CTRL_CAM_HOFFSET_SHIFT)) & HC_CTRL_CAM_HOFFSET_MASK) #define HC_CTRL_CAM_VOFFSET_MASK (0xCU) #define HC_CTRL_CAM_VOFFSET_SHIFT (2U) /*! VOFFSET * 0b00..RED component line is at 0 th image line. * 0b01..RED component line is at 1 st image line. * 0b10..RED component line is at 2 nd image line. * 0b11..RED component line is at 3 rd image line. */ #define HC_CTRL_CAM_VOFFSET(x) (((uint32_t)(((uint32_t)(x)) << HC_CTRL_CAM_VOFFSET_SHIFT)) & HC_CTRL_CAM_VOFFSET_MASK) /*! @} */ /* The count of HC_CTRL_CAM */ #define HC_CTRL_CAM_COUNT (1U) /*! * @} */ /* end of group HC_Register_Masks */ /* HC - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__HC base address */ #define CAMERA__ISP__HC_BASE (0x4AE000C0u) /** Peripheral CAMERA__ISP__HC base pointer */ #define CAMERA__ISP__HC ((HC_Type *)CAMERA__ISP__HC_BASE) /** Array initializer of HC peripheral base addresses */ #define HC_BASE_ADDRS { CAMERA__ISP__HC_BASE } /** Array initializer of HC peripheral base pointers */ #define HC_BASE_PTRS { CAMERA__ISP__HC } /*! * @} */ /* end of group HC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HDR_DECOMPRESS0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HDR_DECOMPRESS0_Peripheral_Access_Layer HDR_DECOMPRESS0 Peripheral Access Layer * @{ */ /** HDR_DECOMPRESS0 - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x48 */ __IO uint32_t CTRL_CAM; /**< Camera 0 HDR Decompress Control, array offset: 0x0, array step: 0x48 */ __IO uint32_t KNEE_POINT1_CAM; /**< Camera 0 HDR Decompress KneePoint 1, array offset: 0x4, array step: 0x48 */ __IO uint32_t KNEE_POINT2_CAM; /**< Camera 0 HDR Decompress KneePoint 2, array offset: 0x8, array step: 0x48 */ __IO uint32_t KNEE_POINT3_CAM; /**< Camera 0 HDR Decompress KneePoint 3, array offset: 0xC, array step: 0x48 */ __IO uint32_t KNEE_POINT4_CAM; /**< Camera 0 HDR Decompress KneePoint 4, array offset: 0x10, array step: 0x48 */ __IO uint32_t KNEE_OFFSET0_CAM; /**< Camera 0 HDR Decompress Knee Offset 0, array offset: 0x14, array step: 0x48 */ __IO uint32_t KNEE_OFFSET1_CAM; /**< Camera 0 HDR Decompress Knee Offset 1, array offset: 0x18, array step: 0x48 */ __IO uint32_t KNEE_OFFSET2_CAM; /**< Camera 0 HDR Decompress Knee Offset 2, array offset: 0x1C, array step: 0x48 */ __IO uint32_t KNEE_OFFSET3_CAM; /**< Camera 0 HDR Decompress Knee Offset 3, array offset: 0x20, array step: 0x48 */ __IO uint32_t KNEE_OFFSET4_CAM; /**< Camera 0 HDR Decompress Knee Offset 4, array offset: 0x24, array step: 0x48 */ __IO uint32_t KNEE_RATIO01_CAM; /**< Camera 0 HDR Decompress Knee Ratio 01, array offset: 0x28, array step: 0x48 */ __IO uint32_t KNEE_RATIO23_CAM; /**< Camera 0 HDR Decompress Knee Ratio 23, array offset: 0x2C, array step: 0x48 */ __IO uint32_t KNEE_RATIO4_CAM; /**< Camera 0 HDR Decompress Knee Ratio 4, array offset: 0x30, array step: 0x48 */ __IO uint32_t KNEE_NPOINT0_CAM; /**< Camera 0 HDR Decompress New KneePoint 0, array offset: 0x34, array step: 0x48 */ __IO uint32_t KNEE_NPOINT1_CAM; /**< Camera 0 HDR Decompress New KneePoint 1, array offset: 0x38, array step: 0x48 */ __IO uint32_t KNEE_NPOINT2_CAM; /**< Camera 0 HDR Decompress New KneePoint 2, array offset: 0x3C, array step: 0x48 */ __IO uint32_t KNEE_NPOINT3_CAM; /**< Camera 0 HDR Decompress New KneePoint 3, array offset: 0x40, array step: 0x48 */ __IO uint32_t KNEE_NPOINT4_CAM; /**< Camera 0 HDR Decompress New KneePoint 4, array offset: 0x44, array step: 0x48 */ } PIPE1_HDR_DECOMP[1]; } HDR_DECOMPRESS0_Type; /* ---------------------------------------------------------------------------- -- HDR_DECOMPRESS0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HDR_DECOMPRESS0_Register_Masks HDR_DECOMPRESS0 Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 HDR Decompress Control */ /*! @{ */ #define HDR_DECOMPRESS0_CTRL_CAM_ENABLE_MASK (0x80000000U) #define HDR_DECOMPRESS0_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..HDR decompression operation is disabled. The contents of input image 0 is provided at the output as is. * 0b1..HDR decompression operation is enabled. In that case the decompression calculates: if (In < Knee[X+1]) * Out = (In - Offset[X]) * Ratio[X] + New[X] */ #define HDR_DECOMPRESS0_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_CTRL_CAM_ENABLE_SHIFT)) & HDR_DECOMPRESS0_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_CTRL_CAM */ #define HDR_DECOMPRESS0_CTRL_CAM_COUNT (1U) /*! @name KNEE_POINT1_CAM - Camera 0 HDR Decompress KneePoint 1 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_POINT1_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_POINT1_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_POINT1_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_POINT1_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_POINT1_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_POINT1_CAM */ #define HDR_DECOMPRESS0_KNEE_POINT1_CAM_COUNT (1U) /*! @name KNEE_POINT2_CAM - Camera 0 HDR Decompress KneePoint 2 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_POINT2_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_POINT2_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_POINT2_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_POINT2_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_POINT2_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_POINT2_CAM */ #define HDR_DECOMPRESS0_KNEE_POINT2_CAM_COUNT (1U) /*! @name KNEE_POINT3_CAM - Camera 0 HDR Decompress KneePoint 3 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_POINT3_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_POINT3_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_POINT3_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_POINT3_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_POINT3_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_POINT3_CAM */ #define HDR_DECOMPRESS0_KNEE_POINT3_CAM_COUNT (1U) /*! @name KNEE_POINT4_CAM - Camera 0 HDR Decompress KneePoint 4 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_POINT4_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_POINT4_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_POINT4_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_POINT4_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_POINT4_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_POINT4_CAM */ #define HDR_DECOMPRESS0_KNEE_POINT4_CAM_COUNT (1U) /*! @name KNEE_OFFSET0_CAM - Camera 0 HDR Decompress Knee Offset 0 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_OFFSET0_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_OFFSET0_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_OFFSET0_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_OFFSET0_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS0_KNEE_OFFSET0_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_OFFSET0_CAM */ #define HDR_DECOMPRESS0_KNEE_OFFSET0_CAM_COUNT (1U) /*! @name KNEE_OFFSET1_CAM - Camera 0 HDR Decompress Knee Offset 1 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_OFFSET1_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_OFFSET1_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_OFFSET1_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_OFFSET1_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS0_KNEE_OFFSET1_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_OFFSET1_CAM */ #define HDR_DECOMPRESS0_KNEE_OFFSET1_CAM_COUNT (1U) /*! @name KNEE_OFFSET2_CAM - Camera 0 HDR Decompress Knee Offset 2 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_OFFSET2_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_OFFSET2_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_OFFSET2_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_OFFSET2_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS0_KNEE_OFFSET2_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_OFFSET2_CAM */ #define HDR_DECOMPRESS0_KNEE_OFFSET2_CAM_COUNT (1U) /*! @name KNEE_OFFSET3_CAM - Camera 0 HDR Decompress Knee Offset 3 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_OFFSET3_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_OFFSET3_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_OFFSET3_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_OFFSET3_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS0_KNEE_OFFSET3_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_OFFSET3_CAM */ #define HDR_DECOMPRESS0_KNEE_OFFSET3_CAM_COUNT (1U) /*! @name KNEE_OFFSET4_CAM - Camera 0 HDR Decompress Knee Offset 4 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_OFFSET4_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS0_KNEE_OFFSET4_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_OFFSET4_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_OFFSET4_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS0_KNEE_OFFSET4_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_OFFSET4_CAM */ #define HDR_DECOMPRESS0_KNEE_OFFSET4_CAM_COUNT (1U) /*! @name KNEE_RATIO01_CAM - Camera 0 HDR Decompress Knee Ratio 01 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO0_MASK (0xFFFU) #define HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO0_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO0(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO0_SHIFT)) & HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO0_MASK) #define HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO1_MASK (0xFFF0000U) #define HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO1_SHIFT (16U) #define HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO1(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO1_SHIFT)) & HDR_DECOMPRESS0_KNEE_RATIO01_CAM_RATIO1_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_RATIO01_CAM */ #define HDR_DECOMPRESS0_KNEE_RATIO01_CAM_COUNT (1U) /*! @name KNEE_RATIO23_CAM - Camera 0 HDR Decompress Knee Ratio 23 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO2_MASK (0xFFFU) #define HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO2_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO2(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO2_SHIFT)) & HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO2_MASK) #define HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO3_MASK (0xFFF0000U) #define HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO3_SHIFT (16U) #define HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO3(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO3_SHIFT)) & HDR_DECOMPRESS0_KNEE_RATIO23_CAM_RATIO3_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_RATIO23_CAM */ #define HDR_DECOMPRESS0_KNEE_RATIO23_CAM_COUNT (1U) /*! @name KNEE_RATIO4_CAM - Camera 0 HDR Decompress Knee Ratio 4 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_RATIO4_CAM_RATIO4_MASK (0xFFFU) #define HDR_DECOMPRESS0_KNEE_RATIO4_CAM_RATIO4_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_RATIO4_CAM_RATIO4(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_RATIO4_CAM_RATIO4_SHIFT)) & HDR_DECOMPRESS0_KNEE_RATIO4_CAM_RATIO4_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_RATIO4_CAM */ #define HDR_DECOMPRESS0_KNEE_RATIO4_CAM_COUNT (1U) /*! @name KNEE_NPOINT0_CAM - Camera 0 HDR Decompress New KneePoint 0 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_NPOINT0_CAM_KNEEPOINT_MASK (0xFFFFFU) #define HDR_DECOMPRESS0_KNEE_NPOINT0_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_NPOINT0_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_NPOINT0_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_NPOINT0_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_NPOINT0_CAM */ #define HDR_DECOMPRESS0_KNEE_NPOINT0_CAM_COUNT (1U) /*! @name KNEE_NPOINT1_CAM - Camera 0 HDR Decompress New KneePoint 1 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_NPOINT1_CAM_KNEEPOINT_MASK (0xFFFFFU) #define HDR_DECOMPRESS0_KNEE_NPOINT1_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_NPOINT1_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_NPOINT1_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_NPOINT1_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_NPOINT1_CAM */ #define HDR_DECOMPRESS0_KNEE_NPOINT1_CAM_COUNT (1U) /*! @name KNEE_NPOINT2_CAM - Camera 0 HDR Decompress New KneePoint 2 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_NPOINT2_CAM_KNEEPOINT_MASK (0xFFFFFU) #define HDR_DECOMPRESS0_KNEE_NPOINT2_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_NPOINT2_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_NPOINT2_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_NPOINT2_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_NPOINT2_CAM */ #define HDR_DECOMPRESS0_KNEE_NPOINT2_CAM_COUNT (1U) /*! @name KNEE_NPOINT3_CAM - Camera 0 HDR Decompress New KneePoint 3 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_NPOINT3_CAM_KNEEPOINT_MASK (0xFFFFFU) #define HDR_DECOMPRESS0_KNEE_NPOINT3_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_NPOINT3_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_NPOINT3_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_NPOINT3_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_NPOINT3_CAM */ #define HDR_DECOMPRESS0_KNEE_NPOINT3_CAM_COUNT (1U) /*! @name KNEE_NPOINT4_CAM - Camera 0 HDR Decompress New KneePoint 4 */ /*! @{ */ #define HDR_DECOMPRESS0_KNEE_NPOINT4_CAM_KNEEPOINT_MASK (0xFFFFFU) #define HDR_DECOMPRESS0_KNEE_NPOINT4_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS0_KNEE_NPOINT4_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS0_KNEE_NPOINT4_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS0_KNEE_NPOINT4_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS0_KNEE_NPOINT4_CAM */ #define HDR_DECOMPRESS0_KNEE_NPOINT4_CAM_COUNT (1U) /*! * @} */ /* end of group HDR_DECOMPRESS0_Register_Masks */ /* HDR_DECOMPRESS0 - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__HDR_DECOMPRESS0 base address */ #define CAMERA__ISP__HDR_DECOMPRESS0_BASE (0x4AE00100u) /** Peripheral CAMERA__ISP__HDR_DECOMPRESS0 base pointer */ #define CAMERA__ISP__HDR_DECOMPRESS0 ((HDR_DECOMPRESS0_Type *)CAMERA__ISP__HDR_DECOMPRESS0_BASE) /** Array initializer of HDR_DECOMPRESS0 peripheral base addresses */ #define HDR_DECOMPRESS0_BASE_ADDRS { CAMERA__ISP__HDR_DECOMPRESS0_BASE } /** Array initializer of HDR_DECOMPRESS0 peripheral base pointers */ #define HDR_DECOMPRESS0_BASE_PTRS { CAMERA__ISP__HDR_DECOMPRESS0 } /*! * @} */ /* end of group HDR_DECOMPRESS0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HDR_DECOMPRESS1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HDR_DECOMPRESS1_Peripheral_Access_Layer HDR_DECOMPRESS1 Peripheral Access Layer * @{ */ /** HDR_DECOMPRESS1 - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x48 */ __IO uint32_t CTRL_CAM; /**< Camera 0 HDR Decompress Control, array offset: 0x0, array step: 0x48 */ __IO uint32_t KNEE_POINT1_CAM; /**< Camera 0 HDR Decompress KneePoint 1, array offset: 0x4, array step: 0x48 */ __IO uint32_t KNEE_POINT2_CAM; /**< Camera 0 HDR Decompress KneePoint 2, array offset: 0x8, array step: 0x48 */ __IO uint32_t KNEE_POINT3_CAM; /**< Camera 0 HDR Decompress KneePoint 3, array offset: 0xC, array step: 0x48 */ __IO uint32_t KNEE_POINT4_CAM; /**< Camera 0 HDR Decompress KneePoint 4, array offset: 0x10, array step: 0x48 */ __IO uint32_t KNEE_OFFSET0_CAM; /**< Camera 0 HDR Decompress Knee Offset 0, array offset: 0x14, array step: 0x48 */ __IO uint32_t KNEE_OFFSET1_CAM; /**< Camera 0 HDR Decompress Knee Offset 1, array offset: 0x18, array step: 0x48 */ __IO uint32_t KNEE_OFFSET2_CAM; /**< Camera 0 HDR Decompress Knee Offset 2, array offset: 0x1C, array step: 0x48 */ __IO uint32_t KNEE_OFFSET3_CAM; /**< Camera 0 HDR Decompress Knee Offset 3, array offset: 0x20, array step: 0x48 */ __IO uint32_t KNEE_OFFSET4_CAM; /**< Camera 0 HDR Decompress Knee Offset 4, array offset: 0x24, array step: 0x48 */ __IO uint32_t KNEE_RATIO01_CAM; /**< Camera 0 HDR Decompress Knee Ratio 01, array offset: 0x28, array step: 0x48 */ __IO uint32_t KNEE_RATIO23_CAM; /**< Camera 0 HDR Decompress Knee Ratio 23, array offset: 0x2C, array step: 0x48 */ __IO uint32_t KNEE_RATIO4_CAM; /**< Camera 0 HDR Decompress Knee Ratio 4, array offset: 0x30, array step: 0x48 */ __IO uint32_t KNEE_NPOINT0_CAM; /**< Camera 0 HDR Decompress New KneePoint 0, array offset: 0x34, array step: 0x48 */ __IO uint32_t KNEE_NPOINT1_CAM; /**< Camera 0 HDR Decompress New KneePoint 1, array offset: 0x38, array step: 0x48 */ __IO uint32_t KNEE_NPOINT2_CAM; /**< Camera 0 HDR Decompress New KneePoint 2, array offset: 0x3C, array step: 0x48 */ __IO uint32_t KNEE_NPOINT3_CAM; /**< Camera 0 HDR Decompress New KneePoint 3, array offset: 0x40, array step: 0x48 */ __IO uint32_t KNEE_NPOINT4_CAM; /**< Camera 0 HDR Decompress New KneePoint 4, array offset: 0x44, array step: 0x48 */ } PIPE1_HDR_DECOMP[1]; } HDR_DECOMPRESS1_Type; /* ---------------------------------------------------------------------------- -- HDR_DECOMPRESS1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HDR_DECOMPRESS1_Register_Masks HDR_DECOMPRESS1 Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 HDR Decompress Control */ /*! @{ */ #define HDR_DECOMPRESS1_CTRL_CAM_ENABLE_MASK (0x80000000U) #define HDR_DECOMPRESS1_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..HDR decompression operation is disabled. The contents of input image 0 is provided at the output as is. * 0b1..HDR decompression operation is enabled. In that case the decompression calculates: if (In < Knee[X+1]) * Out = (In - Offset[X]) * Ratio[X] + New[X] */ #define HDR_DECOMPRESS1_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_CTRL_CAM_ENABLE_SHIFT)) & HDR_DECOMPRESS1_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_CTRL_CAM */ #define HDR_DECOMPRESS1_CTRL_CAM_COUNT (1U) /*! @name KNEE_POINT1_CAM - Camera 0 HDR Decompress KneePoint 1 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_POINT1_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_POINT1_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_POINT1_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_POINT1_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_POINT1_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_POINT1_CAM */ #define HDR_DECOMPRESS1_KNEE_POINT1_CAM_COUNT (1U) /*! @name KNEE_POINT2_CAM - Camera 0 HDR Decompress KneePoint 2 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_POINT2_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_POINT2_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_POINT2_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_POINT2_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_POINT2_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_POINT2_CAM */ #define HDR_DECOMPRESS1_KNEE_POINT2_CAM_COUNT (1U) /*! @name KNEE_POINT3_CAM - Camera 0 HDR Decompress KneePoint 3 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_POINT3_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_POINT3_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_POINT3_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_POINT3_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_POINT3_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_POINT3_CAM */ #define HDR_DECOMPRESS1_KNEE_POINT3_CAM_COUNT (1U) /*! @name KNEE_POINT4_CAM - Camera 0 HDR Decompress KneePoint 4 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_POINT4_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_POINT4_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_POINT4_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_POINT4_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_POINT4_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_POINT4_CAM */ #define HDR_DECOMPRESS1_KNEE_POINT4_CAM_COUNT (1U) /*! @name KNEE_OFFSET0_CAM - Camera 0 HDR Decompress Knee Offset 0 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_OFFSET0_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_OFFSET0_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_OFFSET0_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_OFFSET0_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS1_KNEE_OFFSET0_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_OFFSET0_CAM */ #define HDR_DECOMPRESS1_KNEE_OFFSET0_CAM_COUNT (1U) /*! @name KNEE_OFFSET1_CAM - Camera 0 HDR Decompress Knee Offset 1 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_OFFSET1_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_OFFSET1_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_OFFSET1_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_OFFSET1_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS1_KNEE_OFFSET1_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_OFFSET1_CAM */ #define HDR_DECOMPRESS1_KNEE_OFFSET1_CAM_COUNT (1U) /*! @name KNEE_OFFSET2_CAM - Camera 0 HDR Decompress Knee Offset 2 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_OFFSET2_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_OFFSET2_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_OFFSET2_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_OFFSET2_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS1_KNEE_OFFSET2_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_OFFSET2_CAM */ #define HDR_DECOMPRESS1_KNEE_OFFSET2_CAM_COUNT (1U) /*! @name KNEE_OFFSET3_CAM - Camera 0 HDR Decompress Knee Offset 3 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_OFFSET3_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_OFFSET3_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_OFFSET3_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_OFFSET3_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS1_KNEE_OFFSET3_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_OFFSET3_CAM */ #define HDR_DECOMPRESS1_KNEE_OFFSET3_CAM_COUNT (1U) /*! @name KNEE_OFFSET4_CAM - Camera 0 HDR Decompress Knee Offset 4 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_OFFSET4_CAM_OFFSET_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_OFFSET4_CAM_OFFSET_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_OFFSET4_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_OFFSET4_CAM_OFFSET_SHIFT)) & HDR_DECOMPRESS1_KNEE_OFFSET4_CAM_OFFSET_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_OFFSET4_CAM */ #define HDR_DECOMPRESS1_KNEE_OFFSET4_CAM_COUNT (1U) /*! @name KNEE_RATIO01_CAM - Camera 0 HDR Decompress Knee Ratio 01 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO0_MASK (0xFFFU) #define HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO0_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO0(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO0_SHIFT)) & HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO0_MASK) #define HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO1_MASK (0xFFF0000U) #define HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO1_SHIFT (16U) #define HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO1(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO1_SHIFT)) & HDR_DECOMPRESS1_KNEE_RATIO01_CAM_RATIO1_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_RATIO01_CAM */ #define HDR_DECOMPRESS1_KNEE_RATIO01_CAM_COUNT (1U) /*! @name KNEE_RATIO23_CAM - Camera 0 HDR Decompress Knee Ratio 23 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO2_MASK (0xFFFU) #define HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO2_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO2(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO2_SHIFT)) & HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO2_MASK) #define HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO3_MASK (0xFFF0000U) #define HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO3_SHIFT (16U) #define HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO3(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO3_SHIFT)) & HDR_DECOMPRESS1_KNEE_RATIO23_CAM_RATIO3_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_RATIO23_CAM */ #define HDR_DECOMPRESS1_KNEE_RATIO23_CAM_COUNT (1U) /*! @name KNEE_RATIO4_CAM - Camera 0 HDR Decompress Knee Ratio 4 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_RATIO4_CAM_RATIO4_MASK (0xFFFU) #define HDR_DECOMPRESS1_KNEE_RATIO4_CAM_RATIO4_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_RATIO4_CAM_RATIO4(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_RATIO4_CAM_RATIO4_SHIFT)) & HDR_DECOMPRESS1_KNEE_RATIO4_CAM_RATIO4_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_RATIO4_CAM */ #define HDR_DECOMPRESS1_KNEE_RATIO4_CAM_COUNT (1U) /*! @name KNEE_NPOINT0_CAM - Camera 0 HDR Decompress New KneePoint 0 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_NPOINT0_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_NPOINT0_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_NPOINT0_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_NPOINT0_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_NPOINT0_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_NPOINT0_CAM */ #define HDR_DECOMPRESS1_KNEE_NPOINT0_CAM_COUNT (1U) /*! @name KNEE_NPOINT1_CAM - Camera 0 HDR Decompress New KneePoint 1 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_NPOINT1_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_NPOINT1_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_NPOINT1_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_NPOINT1_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_NPOINT1_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_NPOINT1_CAM */ #define HDR_DECOMPRESS1_KNEE_NPOINT1_CAM_COUNT (1U) /*! @name KNEE_NPOINT2_CAM - Camera 0 HDR Decompress New KneePoint 2 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_NPOINT2_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_NPOINT2_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_NPOINT2_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_NPOINT2_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_NPOINT2_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_NPOINT2_CAM */ #define HDR_DECOMPRESS1_KNEE_NPOINT2_CAM_COUNT (1U) /*! @name KNEE_NPOINT3_CAM - Camera 0 HDR Decompress New KneePoint 3 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_NPOINT3_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_NPOINT3_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_NPOINT3_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_NPOINT3_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_NPOINT3_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_NPOINT3_CAM */ #define HDR_DECOMPRESS1_KNEE_NPOINT3_CAM_COUNT (1U) /*! @name KNEE_NPOINT4_CAM - Camera 0 HDR Decompress New KneePoint 4 */ /*! @{ */ #define HDR_DECOMPRESS1_KNEE_NPOINT4_CAM_KNEEPOINT_MASK (0xFFFFU) #define HDR_DECOMPRESS1_KNEE_NPOINT4_CAM_KNEEPOINT_SHIFT (0U) #define HDR_DECOMPRESS1_KNEE_NPOINT4_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << HDR_DECOMPRESS1_KNEE_NPOINT4_CAM_KNEEPOINT_SHIFT)) & HDR_DECOMPRESS1_KNEE_NPOINT4_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of HDR_DECOMPRESS1_KNEE_NPOINT4_CAM */ #define HDR_DECOMPRESS1_KNEE_NPOINT4_CAM_COUNT (1U) /*! * @} */ /* end of group HDR_DECOMPRESS1_Register_Masks */ /* HDR_DECOMPRESS1 - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__HDR_DECOMPRESS1 base address */ #define CAMERA__ISP__HDR_DECOMPRESS1_BASE (0x4AE00180u) /** Peripheral CAMERA__ISP__HDR_DECOMPRESS1 base pointer */ #define CAMERA__ISP__HDR_DECOMPRESS1 ((HDR_DECOMPRESS1_Type *)CAMERA__ISP__HDR_DECOMPRESS1_BASE) /** Array initializer of HDR_DECOMPRESS1 peripheral base addresses */ #define HDR_DECOMPRESS1_BASE_ADDRS { CAMERA__ISP__HDR_DECOMPRESS1_BASE } /** Array initializer of HDR_DECOMPRESS1 peripheral base pointers */ #define HDR_DECOMPRESS1_BASE_PTRS { CAMERA__ISP__HDR_DECOMPRESS1 } /*! * @} */ /* end of group HDR_DECOMPRESS1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HDR_MERGE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HDR_MERGE_Peripheral_Access_Layer HDR_MERGE Peripheral Access Layer * @{ */ /** HDR_MERGE - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x24 */ __IO uint32_t CTRL_CAM; /**< Camera 0 HDR Merge Control Register, array offset: 0x0, array step: 0x24 */ __IO uint32_t GAIN_OFFSET_CAM; /**< Camera 0 HDR Merge Gain Offset Register, array offset: 0x4, array step: 0x24 */ __IO uint32_t GAIN_SCALE_CAM; /**< Camera 0 HDR Merge Gain Scale Register, array offset: 0x8, array step: 0x24 */ __IO uint32_t GAIN_SHIFT_CAM; /**< Camera 0 HDR Merge Gain Shift Register, array offset: 0xC, array step: 0x24 */ __IO uint32_t LUMA_TH_CAM; /**< Camera 0 HDR Merge Luma Threshold Register, array offset: 0x10, array step: 0x24 */ __IO uint32_t LUMA_SCALE_CAM; /**< Camera 0 HDR Merge Luma Scale Register, array offset: 0x14, array step: 0x24 */ __IO uint32_t DOWNSCALE_CAM; /**< Camera 0 HDR Merge Down Scale Register, array offset: 0x18, array step: 0x24 */ __IO uint32_t UPSCALE_CAM; /**< Camera 0 HDR Merge Up Scale Register, array offset: 0x1C, array step: 0x24 */ __IO uint32_t POST_SCALE_CAM; /**< Camera 0 HDR Merge Post Scale Register, array offset: 0x20, array step: 0x24 */ } NEO_PIPE1_HDR_MERGE_CONF[1]; } HDR_MERGE_Type; /* ---------------------------------------------------------------------------- -- HDR_MERGE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HDR_MERGE_Register_Masks HDR_MERGE Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 HDR Merge Control Register */ /*! @{ */ #define HDR_MERGE_CTRL_CAM_OBPP_MASK (0xCU) #define HDR_MERGE_CTRL_CAM_OBPP_SHIFT (2U) /*! OBPP * 0b00..12 bpp * 0b01..14 bpp * 0b10..16 bpp * 0b11..20 bpp */ #define HDR_MERGE_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_CTRL_CAM_OBPP_SHIFT)) & HDR_MERGE_CTRL_CAM_OBPP_MASK) #define HDR_MERGE_CTRL_CAM_SAFETY_ON_MASK (0x10U) #define HDR_MERGE_CTRL_CAM_SAFETY_ON_SHIFT (4U) /*! SAFETY_ON * 0b0..Off * 0b1..On */ #define HDR_MERGE_CTRL_CAM_SAFETY_ON(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_CTRL_CAM_SAFETY_ON_SHIFT)) & HDR_MERGE_CTRL_CAM_SAFETY_ON_MASK) #define HDR_MERGE_CTRL_CAM_MOTION_FIX_EN_MASK (0x100U) #define HDR_MERGE_CTRL_CAM_MOTION_FIX_EN_SHIFT (8U) /*! MOTION_FIX_EN - Enable fixing of HDR artifacts due to motion * 0b0..Off * 0b1..On */ #define HDR_MERGE_CTRL_CAM_MOTION_FIX_EN(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_CTRL_CAM_MOTION_FIX_EN_SHIFT)) & HDR_MERGE_CTRL_CAM_MOTION_FIX_EN_MASK) #define HDR_MERGE_CTRL_CAM_BLEND_3X3_MASK (0x200U) #define HDR_MERGE_CTRL_CAM_BLEND_3X3_SHIFT (9U) /*! BLEND_3X3 - Selects the HDR blending mode * 0b0..1x1 * 0b1..3x3 */ #define HDR_MERGE_CTRL_CAM_BLEND_3X3(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_CTRL_CAM_BLEND_3X3_SHIFT)) & HDR_MERGE_CTRL_CAM_BLEND_3X3_MASK) #define HDR_MERGE_CTRL_CAM_GAIN0BPP_MASK (0x30000U) #define HDR_MERGE_CTRL_CAM_GAIN0BPP_SHIFT (16U) /*! GAIN0BPP * 0b00..12 bpp * 0b01..14 bpp * 0b10..16 bpp * 0b11..20 bpp */ #define HDR_MERGE_CTRL_CAM_GAIN0BPP(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_CTRL_CAM_GAIN0BPP_SHIFT)) & HDR_MERGE_CTRL_CAM_GAIN0BPP_MASK) #define HDR_MERGE_CTRL_CAM_GAIN1BPP_MASK (0xC0000U) #define HDR_MERGE_CTRL_CAM_GAIN1BPP_SHIFT (18U) /*! GAIN1BPP * 0b00..12 bpp * 0b01..14 bpp * 0b10..16 bpp * 0b11..20 bpp */ #define HDR_MERGE_CTRL_CAM_GAIN1BPP(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_CTRL_CAM_GAIN1BPP_SHIFT)) & HDR_MERGE_CTRL_CAM_GAIN1BPP_MASK) #define HDR_MERGE_CTRL_CAM_ENABLE_MASK (0x80000000U) #define HDR_MERGE_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE - HDR Enable * 0b0..off * 0b1..on */ #define HDR_MERGE_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_CTRL_CAM_ENABLE_SHIFT)) & HDR_MERGE_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of HDR_MERGE_CTRL_CAM */ #define HDR_MERGE_CTRL_CAM_COUNT (1U) /*! @name GAIN_OFFSET_CAM - Camera 0 HDR Merge Gain Offset Register */ /*! @{ */ #define HDR_MERGE_GAIN_OFFSET_CAM_OFFSET0_MASK (0xFFFFU) #define HDR_MERGE_GAIN_OFFSET_CAM_OFFSET0_SHIFT (0U) #define HDR_MERGE_GAIN_OFFSET_CAM_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_GAIN_OFFSET_CAM_OFFSET0_SHIFT)) & HDR_MERGE_GAIN_OFFSET_CAM_OFFSET0_MASK) #define HDR_MERGE_GAIN_OFFSET_CAM_OFFSET1_MASK (0xFFFF0000U) #define HDR_MERGE_GAIN_OFFSET_CAM_OFFSET1_SHIFT (16U) #define HDR_MERGE_GAIN_OFFSET_CAM_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_GAIN_OFFSET_CAM_OFFSET1_SHIFT)) & HDR_MERGE_GAIN_OFFSET_CAM_OFFSET1_MASK) /*! @} */ /* The count of HDR_MERGE_GAIN_OFFSET_CAM */ #define HDR_MERGE_GAIN_OFFSET_CAM_COUNT (1U) /*! @name GAIN_SCALE_CAM - Camera 0 HDR Merge Gain Scale Register */ /*! @{ */ #define HDR_MERGE_GAIN_SCALE_CAM_SCALE0_MASK (0xFFFFU) #define HDR_MERGE_GAIN_SCALE_CAM_SCALE0_SHIFT (0U) #define HDR_MERGE_GAIN_SCALE_CAM_SCALE0(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_GAIN_SCALE_CAM_SCALE0_SHIFT)) & HDR_MERGE_GAIN_SCALE_CAM_SCALE0_MASK) #define HDR_MERGE_GAIN_SCALE_CAM_SCALE1_MASK (0xFFFF0000U) #define HDR_MERGE_GAIN_SCALE_CAM_SCALE1_SHIFT (16U) #define HDR_MERGE_GAIN_SCALE_CAM_SCALE1(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_GAIN_SCALE_CAM_SCALE1_SHIFT)) & HDR_MERGE_GAIN_SCALE_CAM_SCALE1_MASK) /*! @} */ /* The count of HDR_MERGE_GAIN_SCALE_CAM */ #define HDR_MERGE_GAIN_SCALE_CAM_COUNT (1U) /*! @name GAIN_SHIFT_CAM - Camera 0 HDR Merge Gain Shift Register */ /*! @{ */ #define HDR_MERGE_GAIN_SHIFT_CAM_SHIFT0_MASK (0x1FU) #define HDR_MERGE_GAIN_SHIFT_CAM_SHIFT0_SHIFT (0U) #define HDR_MERGE_GAIN_SHIFT_CAM_SHIFT0(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_GAIN_SHIFT_CAM_SHIFT0_SHIFT)) & HDR_MERGE_GAIN_SHIFT_CAM_SHIFT0_MASK) #define HDR_MERGE_GAIN_SHIFT_CAM_SHIFT1_MASK (0x1F0000U) #define HDR_MERGE_GAIN_SHIFT_CAM_SHIFT1_SHIFT (16U) #define HDR_MERGE_GAIN_SHIFT_CAM_SHIFT1(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_GAIN_SHIFT_CAM_SHIFT1_SHIFT)) & HDR_MERGE_GAIN_SHIFT_CAM_SHIFT1_MASK) /*! @} */ /* The count of HDR_MERGE_GAIN_SHIFT_CAM */ #define HDR_MERGE_GAIN_SHIFT_CAM_COUNT (1U) /*! @name LUMA_TH_CAM - Camera 0 HDR Merge Luma Threshold Register */ /*! @{ */ #define HDR_MERGE_LUMA_TH_CAM_TH0_MASK (0xFFFFU) #define HDR_MERGE_LUMA_TH_CAM_TH0_SHIFT (0U) #define HDR_MERGE_LUMA_TH_CAM_TH0(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_LUMA_TH_CAM_TH0_SHIFT)) & HDR_MERGE_LUMA_TH_CAM_TH0_MASK) /*! @} */ /* The count of HDR_MERGE_LUMA_TH_CAM */ #define HDR_MERGE_LUMA_TH_CAM_COUNT (1U) /*! @name LUMA_SCALE_CAM - Camera 0 HDR Merge Luma Scale Register */ /*! @{ */ #define HDR_MERGE_LUMA_SCALE_CAM_SCALE_MASK (0xFFFFU) #define HDR_MERGE_LUMA_SCALE_CAM_SCALE_SHIFT (0U) #define HDR_MERGE_LUMA_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_LUMA_SCALE_CAM_SCALE_SHIFT)) & HDR_MERGE_LUMA_SCALE_CAM_SCALE_MASK) #define HDR_MERGE_LUMA_SCALE_CAM_SHIFT_MASK (0x1F0000U) #define HDR_MERGE_LUMA_SCALE_CAM_SHIFT_SHIFT (16U) #define HDR_MERGE_LUMA_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_LUMA_SCALE_CAM_SHIFT_SHIFT)) & HDR_MERGE_LUMA_SCALE_CAM_SHIFT_MASK) #define HDR_MERGE_LUMA_SCALE_CAM_THSHIFT_MASK (0x1F000000U) #define HDR_MERGE_LUMA_SCALE_CAM_THSHIFT_SHIFT (24U) #define HDR_MERGE_LUMA_SCALE_CAM_THSHIFT(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_LUMA_SCALE_CAM_THSHIFT_SHIFT)) & HDR_MERGE_LUMA_SCALE_CAM_THSHIFT_MASK) /*! @} */ /* The count of HDR_MERGE_LUMA_SCALE_CAM */ #define HDR_MERGE_LUMA_SCALE_CAM_COUNT (1U) /*! @name DOWNSCALE_CAM - Camera 0 HDR Merge Down Scale Register */ /*! @{ */ #define HDR_MERGE_DOWNSCALE_CAM_IMGSCALE0_MASK (0x1FU) #define HDR_MERGE_DOWNSCALE_CAM_IMGSCALE0_SHIFT (0U) #define HDR_MERGE_DOWNSCALE_CAM_IMGSCALE0(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_DOWNSCALE_CAM_IMGSCALE0_SHIFT)) & HDR_MERGE_DOWNSCALE_CAM_IMGSCALE0_MASK) #define HDR_MERGE_DOWNSCALE_CAM_IMGSCALE1_MASK (0x1F0000U) #define HDR_MERGE_DOWNSCALE_CAM_IMGSCALE1_SHIFT (16U) #define HDR_MERGE_DOWNSCALE_CAM_IMGSCALE1(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_DOWNSCALE_CAM_IMGSCALE1_SHIFT)) & HDR_MERGE_DOWNSCALE_CAM_IMGSCALE1_MASK) /*! @} */ /* The count of HDR_MERGE_DOWNSCALE_CAM */ #define HDR_MERGE_DOWNSCALE_CAM_COUNT (1U) /*! @name UPSCALE_CAM - Camera 0 HDR Merge Up Scale Register */ /*! @{ */ #define HDR_MERGE_UPSCALE_CAM_IMGSCALE0_MASK (0xFU) #define HDR_MERGE_UPSCALE_CAM_IMGSCALE0_SHIFT (0U) #define HDR_MERGE_UPSCALE_CAM_IMGSCALE0(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_UPSCALE_CAM_IMGSCALE0_SHIFT)) & HDR_MERGE_UPSCALE_CAM_IMGSCALE0_MASK) #define HDR_MERGE_UPSCALE_CAM_IMGSCALE1_MASK (0xF0000U) #define HDR_MERGE_UPSCALE_CAM_IMGSCALE1_SHIFT (16U) #define HDR_MERGE_UPSCALE_CAM_IMGSCALE1(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_UPSCALE_CAM_IMGSCALE1_SHIFT)) & HDR_MERGE_UPSCALE_CAM_IMGSCALE1_MASK) /*! @} */ /* The count of HDR_MERGE_UPSCALE_CAM */ #define HDR_MERGE_UPSCALE_CAM_COUNT (1U) /*! @name POST_SCALE_CAM - Camera 0 HDR Merge Post Scale Register */ /*! @{ */ #define HDR_MERGE_POST_SCALE_CAM_SCALE_MASK (0x1FU) #define HDR_MERGE_POST_SCALE_CAM_SCALE_SHIFT (0U) #define HDR_MERGE_POST_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << HDR_MERGE_POST_SCALE_CAM_SCALE_SHIFT)) & HDR_MERGE_POST_SCALE_CAM_SCALE_MASK) /*! @} */ /* The count of HDR_MERGE_POST_SCALE_CAM */ #define HDR_MERGE_POST_SCALE_CAM_COUNT (1U) /*! * @} */ /* end of group HDR_MERGE_Register_Masks */ /* HDR_MERGE - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__HDR_MERGE base address */ #define CAMERA__ISP__HDR_MERGE_BASE (0x4AE00300u) /** Peripheral CAMERA__ISP__HDR_MERGE base pointer */ #define CAMERA__ISP__HDR_MERGE ((HDR_MERGE_Type *)CAMERA__ISP__HDR_MERGE_BASE) /** Array initializer of HDR_MERGE peripheral base addresses */ #define HDR_MERGE_BASE_ADDRS { CAMERA__ISP__HDR_MERGE_BASE } /** Array initializer of HDR_MERGE peripheral base pointers */ #define HDR_MERGE_BASE_PTRS { CAMERA__ISP__HDR_MERGE } /*! * @} */ /* end of group HDR_MERGE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HSIO_BLK_CTRL_HSIOMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_BLK_CTRL_HSIOMIX_Peripheral_Access_Layer HSIO_BLK_CTRL_HSIOMIX Peripheral Access Layer * @{ */ /** HSIO_BLK_CTRL_HSIOMIX - Register Layout Typedef */ typedef struct { __IO uint32_t GPR_REG0; /**< GPR Register 0, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t USB1_WAKEUP_CTRL; /**< USB1 Wakeup Control, offset: 0x10 */ __IO uint32_t USB2_WAKEUP_CTRL; /**< USB2 Wakeup Control, offset: 0x14 */ __I uint32_t USB1_WAKEUP_STATUS; /**< USB1 Wakeup Status, offset: 0x18 */ __I uint32_t USB2_WAKEUP_STATUS; /**< USB2 Wakeup Status, offset: 0x1C */ __IO uint32_t USB1_AXQOS_DEFAULT; /**< USB1 AXi master QoS programmable register, offset: 0x20 */ __IO uint32_t USB1_AXQOS_PANIC; /**< USB1 AXi master QoS (panic mode) programmable register, offset: 0x24 */ __IO uint32_t USB2_AXQOS_DEFAULT; /**< USB2 AXi master QoS programmable register, offset: 0x28 */ __IO uint32_t USB2_AXQOS_PANIC; /**< USB2 AXi master QoS (panic mode) programmable register, offset: 0x2C */ __IO uint32_t PCIE1_AXQOS_DEFAULT; /**< PCIE1 AXi master QoS programmable register, offset: 0x30 */ __IO uint32_t PCIE1_AXQOS_PANIC; /**< PCIE1 AXi master QoS (panic mode) programmable register, offset: 0x34 */ __IO uint32_t PCIE2_AXQOS_DEFAULT; /**< PCIE2 AXi master QoS programmable register, offset: 0x38 */ __IO uint32_t PCIE2_AXQOS_PANIC; /**< PCIE2 AXi master QoS (panic mode) programmable register, offset: 0x3C */ __IO uint32_t PCIE1_DMA_XFER_GO_TOGG; /**< PCIE1 DMA engine descriptor transfer go toggle register., offset: 0x40 */ __IO uint32_t PCIE2_DMA_XFER_GO_TOGG; /**< PCIE2 DMA engine descriptor transfer go toggle register., offset: 0x44 */ uint8_t RESERVED_1[8]; __IO uint32_t PCIE1_REG; /**< PCIe1 register, offset: 0x50 */ __IO uint32_t PCIE2_REG; /**< PCIe2 register, offset: 0x54 */ uint8_t RESERVED_2[104]; __IO uint32_t LFAST_IO_REG; /**< GPR registers for LFAST IO, offset: 0xC0 */ } HSIO_BLK_CTRL_HSIOMIX_Type; /* ---------------------------------------------------------------------------- -- HSIO_BLK_CTRL_HSIOMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_BLK_CTRL_HSIOMIX_Register_Masks HSIO_BLK_CTRL_HSIOMIX Register Masks * @{ */ /*! @name GPR_REG0 - GPR Register 0 */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE1_PERST_N_MASK (0x1U) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE1_PERST_N_SHIFT (0U) /*! PCIE1_PERST_N - PCIE1_PERST_N */ #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE1_PERST_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE1_PERST_N_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE1_PERST_N_MASK) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE2_PERST_N_MASK (0x2U) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE2_PERST_N_SHIFT (1U) /*! PCIE2_PERST_N - PCIE2_PERST_N */ #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE2_PERST_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE2_PERST_N_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_PCIE2_PERST_N_MASK) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB2_BYPASS_LOGIC_SEL_MASK (0x20U) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB2_BYPASS_LOGIC_SEL_SHIFT (5U) /*! USB2_BYPASS_LOGIC_SEL - USB2 AUTO_RESUME LOGIC SELECTION */ #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB2_BYPASS_LOGIC_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB2_BYPASS_LOGIC_SEL_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB2_BYPASS_LOGIC_SEL_MASK) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB_PHY_REF_CLK_SEL_MASK (0x40U) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB_PHY_REF_CLK_SEL_SHIFT (6U) /*! USB_PHY_REF_CLK_SEL - USB 3.0 PHY ref clock selection * 0b1..100 MHz high performance PLL * 0b0..24 MHz external oscillator */ #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB_PHY_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB_PHY_REF_CLK_SEL_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_USB_PHY_REF_CLK_SEL_MASK) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CFG_READY_MASK (0x80U) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CFG_READY_SHIFT (7U) /*! CFG_READY - Configuration ready */ #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CFG_READY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CFG_READY_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CFG_READY_MASK) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CRS_CLEAR_MASK (0x100U) #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CRS_CLEAR_SHIFT (8U) /*! CRS_CLEAR - Clear Configuration Retry Status interrupt */ #define HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CRS_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CRS_CLEAR_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_GPR_REG0_CRS_CLEAR_MASK) /*! @} */ /*! @name USB1_WAKEUP_CTRL - USB1 Wakeup Control */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK (0x1U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT (0U) /*! OTG_WKDPDMCHG_EN - Enable signal for wake up from dp/dm change. * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK (0x2U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT (1U) /*! OTG_VBUS_WAKE_EN - Enable signal for wake up from vbus valid or session valid changes * 0b0..Disable * 0b1..Enable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK (0x4U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT (2U) /*! OTG_ID_WAKEUP_EN - Enable signal for wake up from id change * 0b0..Disable * 0b1..Enable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK (0x8U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT (3U) /*! OTG_U3_WAKE_EN - Enable signal for wake up from u3 state, only for super-speed * 0b0..Disable * 0b1..Enable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK (0x10U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT (4U) /*! OTG_VBUS_SOURCE_SEL - otg_vbus_source_sel * 0b0..Select vbus_valid * 0b1..Select sessvld */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK (0x20U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT (5U) /*! OTG_CONN_WAKEUP_EN - Enable signal for wakeup from connection or disconnection, only for super-speed. * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_EN_MASK (0x100U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_EN_SHIFT (8U) /*! AUTORESUME_EN - Enable auto-resume feature. When using phy_bypass signal, this bit should be 1'b0. * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK (0x200U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT (9U) /*! AUTORESUME_DATADLY - Please refer to the bit field description for AUTORESUME_ENDLY. */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK (0x400U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT (10U) /*! AUTORESUME_ENDLY - Tuning the timing between dp/dm data and enable signal when auto-resume finish. */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_LOWSPEED_EN_MASK (0x800U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_LOWSPEED_EN_SHIFT (11U) /*! LOWSPEED_EN - Enable low-speed auto-resume feature * 0b1..Low speed * 0b0..Full/high speed */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_LOWSPEED_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_LOWSPEED_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK (0x1000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT (12U) /*! PHY_BYPASSDMDATA - Data for DM Transmitter Digital Bypass */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK (0x2000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT (13U) /*! PHY_BYPASSDMEN - DM Transmitter Digital Bypass Enable * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK (0x4000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT (14U) /*! PHY_BYPASSDPDATA - Data for DP Transmitter Digital Bypass */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK (0x8000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT (15U) /*! PHY_BYPASSDPEN - DP Transmitter Digital Bypass Enable * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_MASK (0x10000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT (16U) /*! PHY_BYPASSSEL - Transmitter Digital Bypass Select */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSSEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK (0x80000000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT (31U) /*! OTG_WAKE_ENABLE - Global wakeup interrupt enable. Used to clear interrupt. Default 0, same as WIE before. * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK) /*! @} */ /*! @name USB2_WAKEUP_CTRL - USB2 Wakeup Control */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK (0x1U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT (0U) /*! OTG_WKDPDMCHG_EN - Enable signal for wake up from dp/dm change * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK (0x2U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT (1U) /*! OTG_VBUS_WAKE_EN - Enable signal for wake up from vbus valid or session valid changes * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK (0x4U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT (2U) /*! OTG_ID_WAKEUP_EN - Enable signal for wake up from id change * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK (0x8U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT (3U) /*! OTG_U3_WAKE_EN - Enable signal for wake up from u3 state, only for super-speed * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK (0x10U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT (4U) /*! OTG_VBUS_SOURCE_SEL - otg_vbus_source_sel * 0b1..Select ssvld * 0b0..Select vbus_valid */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK (0x20U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT (5U) /*! OTG_CONN_WAKEUP_EN - Enable signal for wakeup from connection or disconnection, only for super-speed. */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_EN_MASK (0x100U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_EN_SHIFT (8U) /*! AUTORESUME_EN - Enable auto-resume feature. When using phy_bypass signal, this bit should be 1'b0. * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK (0x200U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT (9U) /*! AUTORESUME_DATADLY - Please refer to the bitfield description for AUTORESUME_ENDLY. */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK (0x400U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT (10U) /*! AUTORESUME_ENDLY - Tuning the timing between dp/dm data and enable signal when auto-resume finish. */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_LOWSPEED_EN_MASK (0x800U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_LOWSPEED_EN_SHIFT (11U) /*! LOWSPEED_EN - Enable low-speed auto-resume feature * 0b0..Full/high speed * 0b1..Low speed */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_LOWSPEED_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_LOWSPEED_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK (0x1000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT (12U) /*! PHY_BYPASSDMDATA - Data for DM Transmitter Digital Bypass */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK (0x2000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT (13U) /*! PHY_BYPASSDMEN - DM Transmitter Digital Bypass Enable * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK (0x4000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT (14U) /*! PHY_BYPASSDPDATA - Data for DP Transmitter Digital Bypass */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK (0x8000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT (15U) /*! PHY_BYPASSDPEN - DP Transmitter Digital Bypass Enable * 0b1..Enable * 0b0..Disable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_MASK (0x10000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT (16U) /*! PHY_BYPASSSEL - Transmitter Digital Bypass Select */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSSEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK (0x80000000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT (31U) /*! OTG_WAKE_ENABLE - Global wakeup interrupt enable. Used to clear interrupt. Default 0, same as WIE before. * 0b0..Disable * 0b1..Enable */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK) /*! @} */ /*! @name USB1_WAKEUP_STATUS - USB1 Wakeup Status */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK (0x1U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT (0U) /*! OTG_DP_DM_WAKEUP_INTERRUPT - Interrupt status of dm or dp, otg_dp_wakeup_interrupt | otg_dm_wakeup_interrupt */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK (0x2U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT (1U) /*! OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT - Interrupt status of vbus or session valid signal. otg_vbus_wakeup_interrupt | otg_sessvld_wakeup_interrupt */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK (0x4U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT (2U) /*! OTG_ID_WAKEUP_INTERRUPT - Interrupt status of wakeup from id */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK (0x8U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT (3U) /*! OTG_U3_WAKEUP_INTERRUP - Interrupt status of wakeup from u3 state */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK (0x10U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT (4U) /*! OTG_PHY_LINESTATE0_0 - linestate[0], wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK (0x20U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT (5U) /*! OTG_PHY_LINESTATE0_1 - linestate[1], wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK (0x40U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT (6U) /*! OTG_PHY_IDDIG0 - ID status, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK (0x80U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT (7U) /*! OTG_PHY_VBUSVALID0 - vbus valid, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK (0x100U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT (8U) /*! OTG_PHY_OTGSESSVLD0 - session valid, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK (0x200U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT (9U) /*! PIPE_RXELECIDLE - pipe_rxelecidel, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_HOST_MODE_MASK (0x400U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT (10U) /*! OTG_HOST_MODE - USB drd mode * 0b0..host mode * 0b1..device mode */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_HOST_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_HOST_MODE_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK (0x1800U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT (11U) /*! PIPE3_POWERDOWN - Pipe power-down */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK (0x2000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT (13U) /*! OTG_CONN_WAKEUP_INTERRUPT - Interrupt status of connection */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK (0x80000000U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT (31U) /*! OTG_WAKEUP_INTERRUPT - Same as WIR before, it's OR of all wakeup interrupt, then AND with otg_wakeup_enable. */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK) /*! @} */ /*! @name USB2_WAKEUP_STATUS - USB2 Wakeup Status */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK (0x1U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT (0U) /*! OTG_DP_DM_WAKEUP_INTERRUPT - Interrupt status of dm or dp, otg_dp_wakeup_interrupt | otg_dm_wakeup_interrupt */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK (0x2U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT (1U) /*! OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT - Interrupt status of vbus or session valid signal. otg_vbus_wakeup_interrupt | otg_sessvld_wakeup_interrupt */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK (0x4U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT (2U) /*! OTG_ID_WAKEUP_INTERRUPT - Interrupt status of wakeup from id */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK (0x8U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT (3U) /*! OTG_U3_WAKEUP_INTERRUP - Interrupt status of wakeup from u3 state */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK (0x10U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT (4U) /*! OTG_PHY_LINESTATE0_0 - linestate[0], wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK (0x20U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT (5U) /*! OTG_PHY_LINESTATE0_1 - linestate[1], wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK (0x40U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT (6U) /*! OTG_PHY_IDDIG0 - ID status, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK (0x80U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT (7U) /*! OTG_PHY_VBUSVALID0 - vbus valid, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK (0x100U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT (8U) /*! OTG_PHY_OTGSESSVLD0 - session valid, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK (0x200U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT (9U) /*! PIPE_RXELECIDLE - pipe_rxelecidel, wakeup source */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_HOST_MODE_MASK (0x400U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT (10U) /*! OTG_HOST_MODE - USB drd mode indicator * 0b0..Device mode * 0b1..Host mode */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_HOST_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_HOST_MODE_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK (0x1800U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT (11U) /*! PIPE3_POWERDOWN - Pipe power-down */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK (0x2000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT (13U) /*! OTG_CONN_WAKEUP_INTERRUPT - Interrupt status of connection */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK (0x80000000U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT (31U) /*! OTG_WAKEUP_INTERRUPT - Same as WIR before, it's OR of all wakeup interrupt, then AND with otg_wakeup_enable. */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK) /*! @} */ /*! @name USB1_AXQOS_DEFAULT - USB1 AXi master QoS programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT (0U) /*! AW_QOS_DEFAULT - write channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AW_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT (8U) /*! AR_QOS_DEFAULT - Read channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AR_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK) /*! @} */ /*! @name USB1_AXQOS_PANIC - USB1 AXi master QoS (panic mode) programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AW_QOS_PANIC_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AW_QOS_PANIC_SHIFT (0U) /*! AW_QOS_PANIC - write channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AW_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AW_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AW_QOS_PANIC_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AR_QOS_PANIC_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AR_QOS_PANIC_SHIFT (8U) /*! AR_QOS_PANIC - Read channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AR_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AR_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB1_AXQOS_PANIC_AR_QOS_PANIC_MASK) /*! @} */ /*! @name USB2_AXQOS_DEFAULT - USB2 AXi master QoS programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT (0U) /*! AW_QOS_DEFAULT - write channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AW_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT (8U) /*! AR_QOS_DEFAULT - Read channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AR_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK) /*! @} */ /*! @name USB2_AXQOS_PANIC - USB2 AXi master QoS (panic mode) programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AW_QOS_PANIC_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AW_QOS_PANIC_SHIFT (0U) /*! AW_QOS_PANIC - write channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AW_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AW_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AW_QOS_PANIC_MASK) #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AR_QOS_PANIC_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AR_QOS_PANIC_SHIFT (8U) /*! AR_QOS_PANIC - Read channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AR_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AR_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_USB2_AXQOS_PANIC_AR_QOS_PANIC_MASK) /*! @} */ /*! @name PCIE1_AXQOS_DEFAULT - PCIE1 AXi master QoS programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT (0U) /*! AW_QOS_DEFAULT - write channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AW_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT (8U) /*! AR_QOS_DEFAULT - Read channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AR_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK) /*! @} */ /*! @name PCIE1_AXQOS_PANIC - PCIE1 AXi master QoS (panic mode) programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AW_QOS_PANIC_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AW_QOS_PANIC_SHIFT (0U) /*! AW_QOS_PANIC - write channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AW_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AW_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AW_QOS_PANIC_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AR_QOS_PANIC_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AR_QOS_PANIC_SHIFT (8U) /*! AR_QOS_PANIC - Read channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AR_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AR_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_AXQOS_PANIC_AR_QOS_PANIC_MASK) /*! @} */ /*! @name PCIE2_AXQOS_DEFAULT - PCIE2 AXi master QoS programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT (0U) /*! AW_QOS_DEFAULT - write channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AW_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AW_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AW_QOS_DEFAULT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT (8U) /*! AR_QOS_DEFAULT - Read channel Qos default value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AR_QOS_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AR_QOS_DEFAULT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_DEFAULT_AR_QOS_DEFAULT_MASK) /*! @} */ /*! @name PCIE2_AXQOS_PANIC - PCIE2 AXi master QoS (panic mode) programmable register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AW_QOS_PANIC_MASK (0x7U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AW_QOS_PANIC_SHIFT (0U) /*! AW_QOS_PANIC - write channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AW_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AW_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AW_QOS_PANIC_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AR_QOS_PANIC_MASK (0x700U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AR_QOS_PANIC_SHIFT (8U) /*! AR_QOS_PANIC - Read channel Qos panic value register */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AR_QOS_PANIC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AR_QOS_PANIC_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_AXQOS_PANIC_AR_QOS_PANIC_MASK) /*! @} */ /*! @name PCIE1_DMA_XFER_GO_TOGG - PCIE1 DMA engine descriptor transfer go toggle register. */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_MASK (0xFU) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_SHIFT (0U) /*! DMA_RDXFER_GO_TOGG - DMA read engine descriptor transfer go toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_MASK (0xF00U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_SHIFT (8U) /*! DMA_WDXFER_GO_TOGG - DMA write engine descriptor transfer go toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_MASK (0xF0000U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_SHIFT (16U) /*! DMA_RDXFER_DONE_TOGG - DMA read engine descriptor transfer done toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_MASK (0xF000000U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_SHIFT (24U) /*! DMA_WDXFER_DONE_TOGG - DMA write engine descriptor transfer done toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_MASK) /*! @} */ /*! @name PCIE2_DMA_XFER_GO_TOGG - PCIE2 DMA engine descriptor transfer go toggle register. */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_MASK (0xFU) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_SHIFT (0U) /*! DMA_RDXFER_GO_TOGG - DMA read engine descriptor transfer go toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_GO_TOGG_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_MASK (0xF00U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_SHIFT (8U) /*! DMA_WDXFER_GO_TOGG - DMA write engine descriptor transfer go toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_GO_TOGG_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_MASK (0xF0000U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_SHIFT (16U) /*! DMA_RDXFER_DONE_TOGG - DMA read engine descriptor transfer done toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_RDXFER_DONE_TOGG_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_MASK (0xF000000U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_SHIFT (24U) /*! DMA_WDXFER_DONE_TOGG - DMA write engine descriptor transfer done toggle */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_DMA_XFER_GO_TOGG_DMA_WDXFER_DONE_TOGG_MASK) /*! @} */ /*! @name PCIE1_REG - PCIe1 register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_RADM_CPL_TIMEOUT_MASK (0x1U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_RADM_CPL_TIMEOUT_SHIFT (0U) /*! RADM_CPL_TIMEOUT - Indicates that the completion TLP for a request has not been received within the expected time window. */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_RADM_CPL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_RADM_CPL_TIMEOUT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_RADM_CPL_TIMEOUT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_PHY_LANE0_POWER_PRESENT_MASK (0x2U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_PHY_LANE0_POWER_PRESENT_SHIFT (1U) /*! PHY_LANE0_POWER_PRESENT - Power present indicator for lane 0 */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_PHY_LANE0_POWER_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_PHY_LANE0_POWER_PRESENT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE1_REG_PHY_LANE0_POWER_PRESENT_MASK) /*! @} */ /*! @name PCIE2_REG - PCIe2 register */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_RADM_CPL_TIMEOUT_MASK (0x1U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_RADM_CPL_TIMEOUT_SHIFT (0U) /*! RADM_CPL_TIMEOUT - Indicates that the completion TLP for a request has not been received within the expected time window. */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_RADM_CPL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_RADM_CPL_TIMEOUT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_RADM_CPL_TIMEOUT_MASK) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_PHY_LANE0_POWER_PRESENT_MASK (0x2U) #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_PHY_LANE0_POWER_PRESENT_SHIFT (1U) /*! PHY_LANE0_POWER_PRESENT - Power present indicator for lane 0 */ #define HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_PHY_LANE0_POWER_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_PHY_LANE0_POWER_PRESENT_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_PCIE2_REG_PHY_LANE0_POWER_PRESENT_MASK) /*! @} */ /*! @name LFAST_IO_REG - GPR registers for LFAST IO */ /*! @{ */ #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_CREF_EN_MASK (0x40U) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_CREF_EN_SHIFT (6U) /*! CREF_EN - Enable current reference control signal */ #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_CREF_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_CREF_EN_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_CREF_EN_MASK) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT1_MASK (0x80U) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT1_SHIFT (7U) /*! IREF_TX_OPT1 - Control signal to adjust/boost transmitter current reference by 16% . Must be programmed through Fuse */ #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT1_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT1_MASK) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT2_MASK (0x100U) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT2_SHIFT (8U) /*! IREF_TX_OPT2 - Control signal to adjust/boost transmitter current reference by 17% . Must be programmed through Fuse */ #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT2(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT2_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT2_MASK) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT3_MASK (0x200U) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT3_SHIFT (9U) /*! IREF_TX_OPT3 - Control signal to adjust/boost transmitter current reference by 18% . Must be programmed through Fuse */ #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT3(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT3_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT3_MASK) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT4_MASK (0x400U) #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT4_SHIFT (10U) /*! IREF_TX_OPT4 - Control signal to adjust/boost transmitter current reference by 19% . Must be programmed through Fuse */ #define HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT4(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT4_SHIFT)) & HSIO_BLK_CTRL_HSIOMIX_LFAST_IO_REG_IREF_TX_OPT4_MASK) /*! @} */ /*! * @} */ /* end of group HSIO_BLK_CTRL_HSIOMIX_Register_Masks */ /* HSIO_BLK_CTRL_HSIOMIX - Peripheral instance base addresses */ /** Peripheral HSIO__BLK_CTRL_HSIOMIX base address */ #define HSIO__BLK_CTRL_HSIOMIX_BASE (0x4C010000u) /** Peripheral HSIO__BLK_CTRL_HSIOMIX base pointer */ #define HSIO__BLK_CTRL_HSIOMIX ((HSIO_BLK_CTRL_HSIOMIX_Type *)HSIO__BLK_CTRL_HSIOMIX_BASE) /** Array initializer of HSIO_BLK_CTRL_HSIOMIX peripheral base addresses */ #define HSIO_BLK_CTRL_HSIOMIX_BASE_ADDRS { HSIO__BLK_CTRL_HSIOMIX_BASE } /** Array initializer of HSIO_BLK_CTRL_HSIOMIX peripheral base pointers */ #define HSIO_BLK_CTRL_HSIOMIX_BASE_PTRS { HSIO__BLK_CTRL_HSIOMIX } /*! * @} */ /* end of group HSIO_BLK_CTRL_HSIOMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HSIO_GHZ_LN_PLL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_GHZ_LN_PLL_Peripheral_Access_Layer HSIO_GHZ_LN_PLL Peripheral Access Layer * @{ */ /** HSIO_GHZ_LN_PLL - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< PLL Control, offset: 0x0 */ __IO uint32_t SET; /**< PLL Control, offset: 0x4 */ __IO uint32_t CLR; /**< PLL Control, offset: 0x8 */ __IO uint32_t TOG; /**< PLL Control, offset: 0xC */ } CTRL; uint8_t RESERVED_0[32]; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< Spread Spectrum, offset: 0x30 */ __IO uint32_t SET; /**< Spread Spectrum, offset: 0x34 */ __IO uint32_t CLR; /**< Spread Spectrum, offset: 0x38 */ __IO uint32_t TOG; /**< Spread Spectrum, offset: 0x3C */ } SPREAD_SPECTRUM; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< Numerator, offset: 0x40 */ __IO uint32_t SET; /**< Numerator, offset: 0x44 */ __IO uint32_t CLR; /**< Numerator, offset: 0x48 */ __IO uint32_t TOG; /**< Numerator, offset: 0x4C */ } NUMERATOR; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< Denominator, offset: 0x50 */ __IO uint32_t SET; /**< Denominator, offset: 0x54 */ __IO uint32_t CLR; /**< Denominator, offset: 0x58 */ __IO uint32_t TOG; /**< Denominator, offset: 0x5C */ } DENOMINATOR; struct { /* offset: 0x60 */ __IO uint32_t RW; /**< PLL Dividers, offset: 0x60 */ __IO uint32_t SET; /**< PLL Dividers, offset: 0x64 */ __IO uint32_t CLR; /**< PLL Dividers, offset: 0x68 */ __IO uint32_t TOG; /**< PLL Dividers, offset: 0x6C */ } DIV; uint8_t RESERVED_1[128]; __I uint32_t PLL_STATUS; /**< PLL Status, offset: 0xF0 */ } HSIO_GHZ_LN_PLL_Type; /* ---------------------------------------------------------------------------- -- HSIO_GHZ_LN_PLL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_GHZ_LN_PLL_Register_Masks HSIO_GHZ_LN_PLL Register Masks * @{ */ /*! @name CTRL - PLL Control */ /*! @{ */ #define HSIO_GHZ_LN_PLL_CTRL_POWERUP_MASK (0x1U) #define HSIO_GHZ_LN_PLL_CTRL_POWERUP_SHIFT (0U) /*! POWERUP - Power Up * 0b0..Disables PLL. * 0b1..Enables PLL */ #define HSIO_GHZ_LN_PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_CTRL_POWERUP_SHIFT)) & HSIO_GHZ_LN_PLL_CTRL_POWERUP_MASK) #define HSIO_GHZ_LN_PLL_CTRL_CLKMUX_EN_MASK (0x2U) #define HSIO_GHZ_LN_PLL_CTRL_CLKMUX_EN_SHIFT (1U) /*! CLKMUX_EN - CLKMUX Enable * 0b0..Disables output clock mux. * 0b1..Enables output clock mux. */ #define HSIO_GHZ_LN_PLL_CTRL_CLKMUX_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_CTRL_CLKMUX_EN_SHIFT)) & HSIO_GHZ_LN_PLL_CTRL_CLKMUX_EN_MASK) #define HSIO_GHZ_LN_PLL_CTRL_CLKMUX_BYPASS_MASK (0x4U) #define HSIO_GHZ_LN_PLL_CTRL_CLKMUX_BYPASS_SHIFT (2U) /*! CLKMUX_BYPASS - CLKMUX_Bypass * 0b0..Normal mode * 0b1..PLL bypass mode */ #define HSIO_GHZ_LN_PLL_CTRL_CLKMUX_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_CTRL_CLKMUX_BYPASS_SHIFT)) & HSIO_GHZ_LN_PLL_CTRL_CLKMUX_BYPASS_MASK) #define HSIO_GHZ_LN_PLL_CTRL_SPREADCTL_MASK (0x100U) #define HSIO_GHZ_LN_PLL_CTRL_SPREADCTL_SHIFT (8U) /*! SPREADCTL - Modulation Type Select * 0b0..Modulation is centered around nominal frequency. * 0b1..Modulation is spread below nominal frequency. */ #define HSIO_GHZ_LN_PLL_CTRL_SPREADCTL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_CTRL_SPREADCTL_SHIFT)) & HSIO_GHZ_LN_PLL_CTRL_SPREADCTL_MASK) #define HSIO_GHZ_LN_PLL_CTRL_HW_CTRL_SEL_MASK (0x10000U) #define HSIO_GHZ_LN_PLL_CTRL_HW_CTRL_SEL_SHIFT (16U) /*! HW_CTRL_SEL - Hardware Control Select * 0b0..Disables hardware control. PLL is controlled by register. * 0b1..Enables hardware control. PLL is controlled by hardware inputs. In this case, NUMERATOR[MFN] cannot be changed dynamically. */ #define HSIO_GHZ_LN_PLL_CTRL_HW_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_CTRL_HW_CTRL_SEL_SHIFT)) & HSIO_GHZ_LN_PLL_CTRL_HW_CTRL_SEL_MASK) #define HSIO_GHZ_LN_PLL_CTRL_LOCK_BYPASS_MASK (0x80000000U) #define HSIO_GHZ_LN_PLL_CTRL_LOCK_BYPASS_SHIFT (31U) /*! LOCK_BYPASS - Lock Bypass * 0b0..Disables bypass for the lock detector. * 0b1..Enables bypass for the lock detector. */ #define HSIO_GHZ_LN_PLL_CTRL_LOCK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_CTRL_LOCK_BYPASS_SHIFT)) & HSIO_GHZ_LN_PLL_CTRL_LOCK_BYPASS_MASK) /*! @} */ /*! @name SPREAD_SPECTRUM - Spread Spectrum */ /*! @{ */ #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) /*! STEP - Step */ #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STEP_MASK) #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) /*! ENABLE - Enable * 0b0..Disables the spread spectrum modulation. * 0b1..Enables the spread spectrum modulation. */ #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_ENABLE_MASK) #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) /*! STOP - Stop */ #define HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & HSIO_GHZ_LN_PLL_SPREAD_SPECTRUM_STOP_MASK) /*! @} */ /*! @name NUMERATOR - Numerator */ /*! @{ */ #define HSIO_GHZ_LN_PLL_NUMERATOR_MFN_MASK (0xFFFFFFFCU) #define HSIO_GHZ_LN_PLL_NUMERATOR_MFN_SHIFT (2U) /*! MFN - Numerator */ #define HSIO_GHZ_LN_PLL_NUMERATOR_MFN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_NUMERATOR_MFN_SHIFT)) & HSIO_GHZ_LN_PLL_NUMERATOR_MFN_MASK) /*! @} */ /*! @name DENOMINATOR - Denominator */ /*! @{ */ #define HSIO_GHZ_LN_PLL_DENOMINATOR_MFD_MASK (0x3FFFFFFFU) #define HSIO_GHZ_LN_PLL_DENOMINATOR_MFD_SHIFT (0U) /*! MFD - Denominator */ #define HSIO_GHZ_LN_PLL_DENOMINATOR_MFD(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_DENOMINATOR_MFD_SHIFT)) & HSIO_GHZ_LN_PLL_DENOMINATOR_MFD_MASK) /*! @} */ /*! @name DIV - PLL Dividers */ /*! @{ */ #define HSIO_GHZ_LN_PLL_DIV_ODIV_MASK (0xFFU) #define HSIO_GHZ_LN_PLL_DIV_ODIV_SHIFT (0U) /*! ODIV - Output Frequency Divider for Clock Output * 0b00000000..Divide by 2 * 0b00000001..Divide by 3 * 0b00000010..Divide by 2 * 0b00000011..Divide by 3 * 0b00000100..Divide by 4 * 0b00000101..Divide by 5 * 0b00000110..Divide by 6 * 0b00001010..Divide by 10 * 0b10000010..Divide by 130 * 0b11111111..Divide by 255 */ #define HSIO_GHZ_LN_PLL_DIV_ODIV(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_DIV_ODIV_SHIFT)) & HSIO_GHZ_LN_PLL_DIV_ODIV_MASK) #define HSIO_GHZ_LN_PLL_DIV_RDIV_MASK (0xE000U) #define HSIO_GHZ_LN_PLL_DIV_RDIV_SHIFT (13U) /*! RDIV - Input Clock Predivider * 0b000..Divide by 1 * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 3 * 0b100..Divide by 4 * 0b101..Divide by 5 * 0b110..Divide by 6 * 0b111..Divide by 7 */ #define HSIO_GHZ_LN_PLL_DIV_RDIV(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_DIV_RDIV_SHIFT)) & HSIO_GHZ_LN_PLL_DIV_RDIV_MASK) #define HSIO_GHZ_LN_PLL_DIV_MFI_MASK (0x1FF0000U) #define HSIO_GHZ_LN_PLL_DIV_MFI_SHIFT (16U) /*! MFI - Integer Portion of Loop Divider */ #define HSIO_GHZ_LN_PLL_DIV_MFI(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_DIV_MFI_SHIFT)) & HSIO_GHZ_LN_PLL_DIV_MFI_MASK) /*! @} */ /*! @name PLL_STATUS - PLL Status */ /*! @{ */ #define HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOCK_MASK (0x1U) #define HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOCK_SHIFT (0U) /*! PLL_LOCK - PLL_LOCK */ #define HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOCK_SHIFT)) & HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOCK_MASK) #define HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOL_MASK (0x2U) #define HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOL_SHIFT (1U) /*! PLL_LOL - PLL_LOL */ #define HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOL_SHIFT)) & HSIO_GHZ_LN_PLL_PLL_STATUS_PLL_LOL_MASK) #define HSIO_GHZ_LN_PLL_PLL_STATUS_ANA_MFN_MASK (0xFFFFFFFCU) #define HSIO_GHZ_LN_PLL_PLL_STATUS_ANA_MFN_SHIFT (2U) /*! ANA_MFN - ANA_MFN */ #define HSIO_GHZ_LN_PLL_PLL_STATUS_ANA_MFN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_GHZ_LN_PLL_PLL_STATUS_ANA_MFN_SHIFT)) & HSIO_GHZ_LN_PLL_PLL_STATUS_ANA_MFN_MASK) /*! @} */ /*! * @} */ /* end of group HSIO_GHZ_LN_PLL_Register_Masks */ /* HSIO_GHZ_LN_PLL - Peripheral instance base addresses */ /** Peripheral HSIO__GHZ_LN_PLL base address */ #define HSIO__GHZ_LN_PLL_BASE (0x44481800u) /** Peripheral HSIO__GHZ_LN_PLL base pointer */ #define HSIO__GHZ_LN_PLL ((HSIO_GHZ_LN_PLL_Type *)HSIO__GHZ_LN_PLL_BASE) /** Array initializer of HSIO_GHZ_LN_PLL peripheral base addresses */ #define HSIO_GHZ_LN_PLL_BASE_ADDRS { HSIO__GHZ_LN_PLL_BASE } /** Array initializer of HSIO_GHZ_LN_PLL peripheral base pointers */ #define HSIO_GHZ_LN_PLL_BASE_PTRS { HSIO__GHZ_LN_PLL } /*! * @} */ /* end of group HSIO_GHZ_LN_PLL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- HSIO_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_TCU_Peripheral_Access_Layer HSIO_TCU Peripheral Access Layer * @{ */ /** HSIO_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[1276]; struct { /* offset: 0x910 */ __IO uint32_t RW; /**< TCU PCIE0 PHY test control register, offset: 0x910 */ __IO uint32_t SET; /**< TCU PCIE0 PHY test control register, offset: 0x914 */ __IO uint32_t CLR; /**< TCU PCIE0 PHY test control register, offset: 0x918 */ __IO uint32_t TOG; /**< TCU PCIE0 PHY test control register, offset: 0x91C */ } TCU_PCIE0_PHY_CONTROL_; __IO uint32_t TCU_PCIE1_PHY_CONTROL_; /**< TCU PCIE0 PHY test control register, offset: 0x920 */ uint8_t RESERVED_3[12]; __IO uint32_t TCU_DFT_BS; /**< PCIE PHY boundary scan control, offset: 0x930 */ uint8_t RESERVED_4[220]; struct { /* offset: 0xA10 */ __IO uint32_t RW; /**< TCU USB2 PHY control register, offset: 0xA10 */ __IO uint32_t SET; /**< TCU USB2 PHY control register, offset: 0xA14 */ __IO uint32_t CLR; /**< TCU USB2 PHY control register, offset: 0xA18 */ __IO uint32_t TOG; /**< TCU USB2 PHY control register, offset: 0xA1C */ } TCU_USB2_PHY_CONTROL_; struct { /* offset: 0xA20 */ __I uint32_t RW; /**< test data out for usb2, offset: 0xA20 */ __I uint32_t SET; /**< test data out for usb2, offset: 0xA24 */ __I uint32_t CLR; /**< test data out for usb2, offset: 0xA28 */ __I uint32_t TOG; /**< test data out for usb2, offset: 0xA2C */ } USB2_PHY_TESTDATA; struct { /* offset: 0xA30 */ __IO uint32_t RW; /**< TCU USB3 PHY control register, offset: 0xA30 */ __IO uint32_t SET; /**< TCU USB3 PHY control register, offset: 0xA34 */ __IO uint32_t CLR; /**< TCU USB3 PHY control register, offset: 0xA38 */ __IO uint32_t TOG; /**< TCU USB3 PHY control register, offset: 0xA3C */ } TCU_USB3_PHY_CONTROL_; struct { /* offset: 0xA40 */ __I uint32_t RW; /**< test data out for usb3, offset: 0xA40 */ __I uint32_t SET; /**< test data out for usb3, offset: 0xA44 */ __I uint32_t CLR; /**< test data out for usb3, offset: 0xA48 */ __I uint32_t TOG; /**< test data out for usb3, offset: 0xA4C */ } USB3_PHY_TESTDATA; uint8_t RESERVED_5[432]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_6[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } HSIO_TCU_Type; /* ---------------------------------------------------------------------------- -- HSIO_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup HSIO_TCU_Register_Masks HSIO_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & HSIO_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PCIE0_PHY_CONTROL_ - TCU PCIE0 PHY test control register */ /*! @{ */ #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_burnin_MASK (0x1U) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_burnin_SHIFT (0U) /*! test_burnin - testburnin functional for USB PHY stress test */ #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_burnin(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_burnin_SHIFT)) & HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_burnin_MASK) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_powerdown_MASK (0x2U) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_powerdown_SHIFT (1U) /*! test_powerdown - powers down all circuit */ #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_powerdown(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_powerdown_SHIFT)) & HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_powerdown_MASK) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_stop_clk_en_MASK (0x4U) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_stop_clk_en_SHIFT (2U) /*! test_stop_clk_en - Test stop clock */ #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_stop_clk_en(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_stop_clk_en_SHIFT)) & HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_stop_clk_en_MASK) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_tx_ref_clk_en_MASK (0x8U) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_tx_ref_clk_en_SHIFT (3U) /*! test_tx_ref_clk_en - Test ref clock enable */ #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_tx_ref_clk_en(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_tx_ref_clk_en_SHIFT)) & HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_tx_ref_clk_en_MASK) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_mode_MASK (0x10U) #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_mode_SHIFT (4U) /*! test_mode - test mode */ #define HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_mode(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_mode_SHIFT)) & HSIO_TCU_TCU_PCIE0_PHY_CONTROL__test_mode_MASK) /*! @} */ /*! @name TCU_PCIE1_PHY_CONTROL_ - TCU PCIE0 PHY test control register */ /*! @{ */ #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_burnin_MASK (0x1U) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_burnin_SHIFT (0U) /*! test_burnin - testburnin functional for USB PHY stress test */ #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_burnin(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_burnin_SHIFT)) & HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_burnin_MASK) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_powerdown_MASK (0x2U) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_powerdown_SHIFT (1U) /*! test_powerdown - enable signal for usb loopback test */ #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_powerdown(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_powerdown_SHIFT)) & HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_powerdown_MASK) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_stop_clk_en_MASK (0x4U) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_stop_clk_en_SHIFT (2U) /*! test_stop_clk_en - Test clock stop */ #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_stop_clk_en(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_stop_clk_en_SHIFT)) & HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_stop_clk_en_MASK) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_tx_ref_clk_en_MASK (0x8U) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_tx_ref_clk_en_SHIFT (3U) /*! test_tx_ref_clk_en - Ref test clock enable */ #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_tx_ref_clk_en(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_tx_ref_clk_en_SHIFT)) & HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_tx_ref_clk_en_MASK) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_mode_MASK (0x10U) #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_mode_SHIFT (4U) /*! test_mode - test mode */ #define HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_mode(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_mode_SHIFT)) & HSIO_TCU_TCU_PCIE1_PHY_CONTROL__test_mode_MASK) /*! @} */ /*! @name TCU_DFT_BS - PCIE PHY boundary scan control */ /*! @{ */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdi_MASK (0x1U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdi_SHIFT (0U) /*! pcie0_bs_tdi - BS TDI */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdi(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdi_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdi_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_acmode_MASK (0x2U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_acmode_SHIFT (1U) /*! pcie0_bs_acmode - BS ACMODE */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_acmode(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_acmode_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_acmode_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_actest_MASK (0x4U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_actest_SHIFT (2U) /*! pcie0_bs_actest - BS ACTEST */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_actest(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_actest_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_actest_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_cdr_MASK (0x8U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_cdr_SHIFT (3U) /*! pcie0_bs_cdr - BS CDR */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_cdr(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_cdr_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_cdr_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_ce_MASK (0x10U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_ce_SHIFT (4U) /*! pcie0_bs_ce - BS CE */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_ce(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_ce_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_ce_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_rxinit_MASK (0x20U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_rxinit_SHIFT (5U) /*! pcie0_bs_rxinit - BS RX-INIT */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_rxinit(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_rxinit_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_rxinit_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_sdr_MASK (0x40U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_sdr_SHIFT (6U) /*! pcie0_bs_sdr - BS SDR */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_sdr(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_sdr_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_sdr_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_udr_MASK (0x80U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_udr_SHIFT (7U) /*! pcie0_bs_udr - BS UDR */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_udr(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_udr_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_udr_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdo_MASK (0x100U) #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdo_SHIFT (8U) /*! pcie0_bs_tdo - BS TDO */ #define HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdo(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdo_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie0_bs_tdo_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdi_MASK (0x10000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdi_SHIFT (16U) /*! pcie1_bs_tdi - BS TDI */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdi(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdi_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdi_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_acmode_MASK (0x20000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_acmode_SHIFT (17U) /*! pcie1_bs_acmode - BS ACMODE */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_acmode(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_acmode_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_acmode_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_actest_MASK (0x40000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_actest_SHIFT (18U) /*! pcie1_bs_actest - BS ACTEST */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_actest(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_actest_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_actest_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_cdr_MASK (0x80000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_cdr_SHIFT (19U) /*! pcie1_bs_cdr - BS CDR */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_cdr(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_cdr_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_cdr_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_ce_MASK (0x100000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_ce_SHIFT (20U) /*! pcie1_bs_ce - BS CE */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_ce(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_ce_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_ce_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_rxinit_MASK (0x200000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_rxinit_SHIFT (21U) /*! pcie1_bs_rxinit - BS RX-INIT */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_rxinit(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_rxinit_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_rxinit_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_sdr_MASK (0x400000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_sdr_SHIFT (22U) /*! pcie1_bs_sdr - BS SDR */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_sdr(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_sdr_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_sdr_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_udr_MASK (0x800000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_udr_SHIFT (23U) /*! pcie1_bs_udr - BS UDR */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_udr(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_udr_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_udr_MASK) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdo_MASK (0x1000000U) #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdo_SHIFT (24U) /*! pcie1_bs_tdo - BS TDO */ #define HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdo(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdo_SHIFT)) & HSIO_TCU_TCU_DFT_BS_pcie1_bs_tdo_MASK) /*! @} */ /*! @name TCU_USB2_PHY_CONTROL_ - TCU USB2 PHY control register */ /*! @{ */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__test_mode_MASK (0x1U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__test_mode_SHIFT (0U) /*! test_mode - usb_phy_test_mode */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__test_mode(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__test_mode_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__test_mode_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testburnin_MASK (0x2U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testburnin_SHIFT (1U) /*! testburnin - testburnin functional for USB PHY stress test */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testburnin(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__testburnin_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__testburnin_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__loopbackenb_MASK (0x4U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__loopbackenb_SHIFT (2U) /*! loopbackenb - enable signal for usb loopback test */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__loopbackenb(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__loopbackenb_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__loopbackenb_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__vatestenb_MASK (0x18U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__vatestenb_SHIFT (3U) /*! vatestenb - Analog probes selection */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__vatestenb(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__vatestenb_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__vatestenb_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__suspendm0_MASK (0x20U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__suspendm0_SHIFT (5U) /*! suspendm0 - suspend mode */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__suspendm0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__suspendm0_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__suspendm0_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testclk_MASK (0x10000U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testclk_SHIFT (16U) /*! testclk - testclk for advanced USB test interface */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testclk(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__testclk_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__testclk_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testaddr_MASK (0x1E0000U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testaddr_SHIFT (17U) /*! testaddr - testaddr[3:0] for advanced USB test interface */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testaddr(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__testaddr_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__testaddr_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testdatain_MASK (0x1FE00000U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testdatain_SHIFT (21U) /*! testdatain - testdatain[7:0] for advanced USB test interface */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testdatain(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__testdatain_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__testdatain_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testdataoutsel_MASK (0x20000000U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testdataoutsel_SHIFT (29U) /*! testdataoutsel - testdataoutsel for advanced USB test interface */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__testdataoutsel(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__testdataoutsel_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__testdataoutsel_MASK) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__atereset_MASK (0x40000000U) #define HSIO_TCU_TCU_USB2_PHY_CONTROL__atereset_SHIFT (30U) /*! atereset - atereset for advanced USB test interface */ #define HSIO_TCU_TCU_USB2_PHY_CONTROL__atereset(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB2_PHY_CONTROL__atereset_SHIFT)) & HSIO_TCU_TCU_USB2_PHY_CONTROL__atereset_MASK) /*! @} */ /*! @name USB2_PHY_TESTDATA - test data out for usb2 */ /*! @{ */ #define HSIO_TCU_USB2_PHY_TESTDATA_out_MASK (0xFU) #define HSIO_TCU_USB2_PHY_TESTDATA_out_SHIFT (0U) /*! out - bit output for status monitor */ #define HSIO_TCU_USB2_PHY_TESTDATA_out(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_USB2_PHY_TESTDATA_out_SHIFT)) & HSIO_TCU_USB2_PHY_TESTDATA_out_MASK) /*! @} */ /*! @name TCU_USB3_PHY_CONTROL_ - TCU USB3 PHY control register */ /*! @{ */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_mode_MASK (0x1U) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_mode_SHIFT (0U) /*! test_mode - usb_phy_test_mode */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_mode(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB3_PHY_CONTROL__test_mode_SHIFT)) & HSIO_TCU_TCU_USB3_PHY_CONTROL__test_mode_MASK) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__testburnin_MASK (0x2U) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__testburnin_SHIFT (1U) /*! testburnin - testburnin functional for USB PHY stress test */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__testburnin(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB3_PHY_CONTROL__testburnin_SHIFT)) & HSIO_TCU_TCU_USB3_PHY_CONTROL__testburnin_MASK) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__loopbackenb_MASK (0x4U) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__loopbackenb_SHIFT (2U) /*! loopbackenb - enable signal for usb loopback test */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__loopbackenb(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB3_PHY_CONTROL__loopbackenb_SHIFT)) & HSIO_TCU_TCU_USB3_PHY_CONTROL__loopbackenb_MASK) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__vatestenb_MASK (0x8U) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__vatestenb_SHIFT (3U) /*! vatestenb - Analog probes selection */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__vatestenb(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB3_PHY_CONTROL__vatestenb_SHIFT)) & HSIO_TCU_TCU_USB3_PHY_CONTROL__vatestenb_MASK) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_hsp_MASK (0x10U) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_hsp_SHIFT (4U) /*! test_powerdown_hsp - HS power down */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_hsp(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_hsp_SHIFT)) & HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_hsp_MASK) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_ssp_MASK (0x20U) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_ssp_SHIFT (5U) /*! test_powerdown_ssp - SS power down */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_ssp(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_ssp_SHIFT)) & HSIO_TCU_TCU_USB3_PHY_CONTROL__test_powerdown_ssp_MASK) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__atereset_MASK (0x40000000U) #define HSIO_TCU_TCU_USB3_PHY_CONTROL__atereset_SHIFT (30U) /*! atereset - ate reset */ #define HSIO_TCU_TCU_USB3_PHY_CONTROL__atereset(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_USB3_PHY_CONTROL__atereset_SHIFT)) & HSIO_TCU_TCU_USB3_PHY_CONTROL__atereset_MASK) /*! @} */ /*! @name USB3_PHY_TESTDATA - test data out for usb3 */ /*! @{ */ #define HSIO_TCU_USB3_PHY_TESTDATA_out_MASK (0xFU) #define HSIO_TCU_USB3_PHY_TESTDATA_out_SHIFT (0U) /*! out - bit output for status monitor */ #define HSIO_TCU_USB3_PHY_TESTDATA_out(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_USB3_PHY_TESTDATA_out_SHIFT)) & HSIO_TCU_USB3_PHY_TESTDATA_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & HSIO_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & HSIO_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & HSIO_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x78U) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & HSIO_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & HSIO_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define HSIO_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & HSIO_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define HSIO_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define HSIO_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define HSIO_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & HSIO_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define HSIO_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x1EU) #define HSIO_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define HSIO_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << HSIO_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & HSIO_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group HSIO_TCU_Register_Masks */ /* HSIO_TCU - Peripheral instance base addresses */ /** Peripheral HSIO__TCU base address */ #define HSIO__TCU_BASE (0x4C000000u) /** Peripheral HSIO__TCU base pointer */ #define HSIO__TCU ((HSIO_TCU_Type *)HSIO__TCU_BASE) /** Array initializer of HSIO_TCU peripheral base addresses */ #define HSIO_TCU_BASE_ADDRS { HSIO__TCU_BASE } /** Array initializer of HSIO_TCU peripheral base pointers */ #define HSIO_TCU_BASE_PTRS { HSIO__TCU } /*! * @} */ /* end of group HSIO_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer * @{ */ /** I2S - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ __O uint32_t TDR[8]; /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */ __I uint32_t TFR[8]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4, irregular array, not all indices are valid */ __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ uint8_t RESERVED_0[12]; __IO uint32_t TTCR; /**< Transmit Timestamp Control, offset: 0x70 */ __I uint32_t TTSR; /**< Transmit Timestamp, offset: 0x74 */ __I uint32_t TBCR; /**< Transmit Bit Count, offset: 0x78 */ __I uint32_t TBCTR; /**< Transmit Bit Count Timestamp, offset: 0x7C */ uint8_t RESERVED_1[8]; __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ __I uint32_t RDR[8]; /**< Receive Data, array offset: 0xA0, array step: 0x4, irregular array, not all indices are valid */ __I uint32_t RFR[8]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4, irregular array, not all indices are valid */ __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ uint8_t RESERVED_2[12]; __IO uint32_t RTCR; /**< Receive Timestamp Control, offset: 0xF0 */ __I uint32_t RTSR; /**< Receive Timestamp, offset: 0xF4 */ __I uint32_t RBCR; /**< Receive Bit Count, offset: 0xF8 */ __I uint32_t RBCTR; /**< Receive Bit Count Timestamp, offset: 0xFC */ __IO uint32_t MCR; /**< MCLK Control, offset: 0x100 */ } I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard feature set * 0b0000000000000010..Standard feature set with timestamp registers */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) #define I2S_VERID_MINOR_MASK (0xFF0000U) #define I2S_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) /*! DATALINE - Number of Data Lines */ #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) #define I2S_PARAM_FIFO_MASK (0xF00U) #define I2S_PARAM_FIFO_SHIFT (8U) /*! FIFO - FIFO Size */ #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) /*! FRAME - Frame Size */ #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) /*! @} */ /*! @name TCSR - Transmit Control */ /*! @{ */ #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Watermark not reached * 0b1..Watermark reached */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..Not empty * 0b1..Empty */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect * 0b1..Software reset */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect * 0b1..FIFO reset */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable * 0b0..Disable * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) */ #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ /*! @name TCR1 - Transmit Configuration 1 */ /*! @{ */ #define I2S_TCR1_TFW_MASK (0x7FU) /* Merged from fields with different position or width, of widths (5, 7), largest definition used */ #define I2S_TCR1_TFW_SHIFT (0U) /*! TFW - Transmit FIFO Watermark * 0b0000000..1 * 0b0000001..2 * 0b0000010-0b1111110..(TFW +1) * 0b1111111..128 */ #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /* Merged from fields with different position or width, of widths (5, 7), largest definition used */ /*! @} */ /*! @name TCR2 - Transmit Configuration 2 */ /*! @{ */ #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) #define I2S_TCR2_BYP_MASK (0x800000U) #define I2S_TCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass * 0b0..Disable * 0b1..Enable */ #define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Generate externally in Target mode * 0b1..Generate internally in Controller mode */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus clock * 0b01..Controller clock (MCLK) option 1 * 0b10..Controller clock (MCLK) option 2 * 0b11..Controller clock (MCLK) option 3 */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..Disable * 0b1..Enable */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source * 0b1..Swap the bit clock source */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) #define I2S_TCR2_SYNC_MASK (0x40000000U) #define I2S_TCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b0..Asynchronous mode * 0b1..Synchronous with receiver */ #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) /*! @} */ /*! @name TCR3 - Transmit Configuration 3 */ /*! @{ */ #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) #define I2S_TCR3_TCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 2, 4, 8), largest definition used */ #define I2S_TCR3_TCE_SHIFT (16U) /*! TCE - Transmit Channel Enable */ #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 2, 4, 8), largest definition used */ #define I2S_TCR3_CFR_MASK (0xFF000000U) /* Merged from fields with different position or width, of widths (2, 4, 8), largest definition used */ #define I2S_TCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset */ #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) /* Merged from fields with different position or width, of widths (2, 4, 8), largest definition used */ /*! @} */ /*! @name TCR4 - Transmit Configuration 4 */ /*! @{ */ #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Generated externally in Target mode * 0b1..Generated internally in Controller mode */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) /*! ONDEM - On-Demand Mode * 0b0..Generated continuously * 0b1..Generated after the FIFO warning flag is cleared */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..First bit of the frame * 0b1..One bit before the first bit of the frame */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB * 0b1..MSB */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) /*! CHMOD - Channel Mode * 0b0..TDM mode * 0b1..Output mode */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size */ #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..Disable FIFO packing * 0b01..Reserved * 0b10..Enable 8-bit FIFO packing * 0b11..Enable 16-bit FIFO packing */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..Disable * 0b01..Enable on FIFO reads (from transmit shift registers) * 0b10..Enable on FIFO writes (by software) * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..Continue from the start of the next frame * 0b1..Continue from the same word that caused the FIFO error */ #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ /*! @name TCR5 - Transmit Configuration 5 */ /*! @{ */ #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted * 0b00000..0 * 0b00001-0b11110..FBT * 0b11111..31 */ #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width * 0b00111..8 * 0b01000..9 * 0b01001-0b11110..(W0W value + 1) * 0b11111..32 */ #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) /*! WNW - Word N Width * 0b00111..8 * 0b01000..9 * 0b01001-0b11110..(WNW value + 1) * 0b11111..32 */ #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ /*! @name TDR - Transmit Data */ /*! @{ */ #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) /*! TDR - Transmit Data */ #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) /*! @} */ /* The count of I2S_TDR */ #define I2S_TDR_COUNT (8U) /*! @name TFR - Transmit FIFO */ /*! @{ */ #define I2S_TFR_RFP_MASK (0xFFU) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ #define I2S_TFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ #define I2S_TFR_WFP_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ #define I2S_TFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) /*! WCP - Write Channel Pointer * 0b0..No effect * 0b1..Next FIFO to be written */ #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) /*! @} */ /* The count of I2S_TFR */ #define I2S_TFR_COUNT (8U) /*! @name TMR - Transmit Mask */ /*! @{ */ #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask * 0b00000000000000000000000000000000..Enable * 0b00000000000000000000000000000001..Mask */ #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @} */ /*! @name TTCR - Transmit Timestamp Control */ /*! @{ */ #define I2S_TTCR_TSEN_MASK (0x1U) #define I2S_TTCR_TSEN_SHIFT (0U) /*! TSEN - Timestamp Enable * 0b0..Disable * 0b1..Enable */ #define I2S_TTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK) #define I2S_TTCR_TSINC_MASK (0x2U) #define I2S_TTCR_TSINC_SHIFT (1U) /*! TSINC - Timestamp Increment * 0b0..When enabled and after the bit counter has incremented * 0b1..When enabled */ #define I2S_TTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK) #define I2S_TTCR_TSSEL_MASK (0xCU) #define I2S_TTCR_TSSEL_SHIFT (2U) /*! TSSEL - Timestamp Select * 0b00..Increment when enabled * 0b01..Increment when the receive timestamp counter is enabled * 0b10..Increment when the transmit timestamp counter on another instance is enabled * 0b11..Increment when the receive timestamp counter on another instance is enabled */ #define I2S_TTCR_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSSEL_SHIFT)) & I2S_TTCR_TSSEL_MASK) #define I2S_TTCR_RTSC_MASK (0x100U) #define I2S_TTCR_RTSC_SHIFT (8U) /*! RTSC - Reset Timestamp Counter * 0b0..No effect * 0b1..Reset */ #define I2S_TTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK) #define I2S_TTCR_RBC_MASK (0x200U) #define I2S_TTCR_RBC_SHIFT (9U) /*! RBC - Reset Bit Counter * 0b0..No effect * 0b1..Reset */ #define I2S_TTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK) /*! @} */ /*! @name TTSR - Transmit Timestamp */ /*! @{ */ #define I2S_TTSR_TSC_MASK (0xFFFFFFFFU) #define I2S_TTSR_TSC_SHIFT (0U) /*! TSC - Timestamp Counter */ #define I2S_TTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK) /*! @} */ /*! @name TBCR - Transmit Bit Count */ /*! @{ */ #define I2S_TBCR_BCNT_MASK (0xFFFFFFFFU) #define I2S_TBCR_BCNT_SHIFT (0U) /*! BCNT - Bit Counter */ #define I2S_TBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK) /*! @} */ /*! @name TBCTR - Transmit Bit Count Timestamp */ /*! @{ */ #define I2S_TBCTR_BCTS_MASK (0xFFFFFFFFU) #define I2S_TBCTR_BCTS_SHIFT (0U) /*! BCTS - Bit Timestamp */ #define I2S_TBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK) /*! @} */ /*! @name RCSR - Receive Control */ /*! @{ */ #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag * 0b0..Watermark not reached * 0b1..Watermark reached */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag * 0b0..Not full * 0b1..Full */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag * 0b0..No error * 0b1..Receive overflow detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset * 0b0..No effect * 0b1..Software reset */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset * 0b0..No effect * 0b1..Reset */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable * 0b0..Disable after completing the current frame * 0b1..Enable */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable * 0b0..Disable * 0b1..Enable (or receiver disabled and not yet reached end of frame) */ #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ /*! @name RCR1 - Receive Configuration 1 */ /*! @{ */ #define I2S_RCR1_RFW_MASK (0x7FU) /* Merged from fields with different position or width, of widths (5, 7), largest definition used */ #define I2S_RCR1_RFW_SHIFT (0U) /*! RFW - Receive FIFO Watermark * 0b0000000..1 * 0b0000001..2 * 0b0000010-0b1111110..(RFW value + 1) * 0b1111111..128 */ #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /* Merged from fields with different position or width, of widths (5, 7), largest definition used */ /*! @} */ /*! @name RCR2 - Receive Configuration 2 */ /*! @{ */ #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) #define I2S_RCR2_BYP_MASK (0x800000U) #define I2S_RCR2_BYP_SHIFT (23U) /*! BYP - Bit Clock Bypass * 0b0..Disable * 0b1..Enable */ #define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction * 0b0..Generated externally in Target mode * 0b1..Generated internally in Controller mode */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select * 0b00..Bus clock * 0b01..Controller clock (MCLK) option 1 * 0b10..Controller clock (MCLK) option 2 * 0b11..Controller clock (MCLK) option 3 */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input * 0b0..Disable * 0b1..Enable */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap * 0b0..Use the normal bit clock source * 0b1..Swap the bit clock source */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) #define I2S_RCR2_SYNC_MASK (0x40000000U) #define I2S_RCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode * 0b0..Asynchronous mode * 0b1..Synchronous with transmitter */ #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) /*! @} */ /*! @name RCR3 - Receive Configuration 3 */ /*! @{ */ #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration * 0b00000..Word 1 * 0b00001..Word 2 * 0b00010-0b11110..Word (WDFL value + 1) * 0b11111..Word 32 */ #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) #define I2S_RCR3_RCE_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (1, 2, 4, 8), largest definition used */ #define I2S_RCR3_RCE_SHIFT (16U) /*! RCE - Receive Channel Enable */ #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 2, 4, 8), largest definition used */ #define I2S_RCR3_CFR_MASK (0xFF000000U) /* Merged from fields with different position or width, of widths (2, 4, 8), largest definition used */ #define I2S_RCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset */ #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) /* Merged from fields with different position or width, of widths (2, 4, 8), largest definition used */ /*! @} */ /*! @name RCR4 - Receive Configuration 4 */ /*! @{ */ #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction * 0b0..Generated externally in Target mode * 0b1..Generated internally in Controller mode */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity * 0b0..Active high * 0b1..Active low */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) /*! ONDEM - On-Demand Mode * 0b0..Generated continuously * 0b1..Generated when the FIFO warning flag is 0 */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early * 0b0..First bit of the frame * 0b1..One bit before the first bit of the frame */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First * 0b0..LSB * 0b1..MSB */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width * 0b00000..1 * 0b00001..2 * 0b00010-0b11110..(SYWD value + 1) * 0b11111..32 */ #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size * 0b00000..1 * 0b00001..2 * 0b00010-0b11110..(FRSZ value + 1) * 0b11111..32 */ #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode * 0b00..Disable * 0b01..Reserved * 0b10..Enable 8-bit FIFO packing * 0b11..Enable 16-bit FIFO packing */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode * 0b00..Disable * 0b01..Enable on FIFO writes (from receive shift registers) * 0b10..Enable on FIFO reads (by software) * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error * 0b0..From the start of the next frame after the FIFO error flag is cleared * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared */ #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ /*! @name RCR5 - Receive Configuration 5 */ /*! @{ */ #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted * 0b00000..0 * 0b00001-0b11110..FBT value * 0b11111..31 */ #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width * 0b00000..1 * 0b00001..2 * 0b00010-0b11110..(W0W value + 1) * 0b11111..32 */ #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) /*! WNW - Word N Width * 0b00111..8 * 0b01000..9 * 0b01001-0b11110..(WNW value + 1) * 0b11111..32 */ #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ /*! @name RDR - Receive Data */ /*! @{ */ #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) /*! RDR - Receive Data */ #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) /*! @} */ /* The count of I2S_RDR */ #define I2S_RDR_COUNT (8U) /*! @name RFR - Receive FIFO */ /*! @{ */ #define I2S_RFR_RFP_MASK (0xFFU) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ #define I2S_RFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) /*! RCP - Read Channel Pointer * 0b0..No effect * 0b1..Next FIFO to be read */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) #define I2S_RFR_WFP_MASK (0xFF0000U) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ #define I2S_RFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) /* Merged from fields with different position or width, of widths (6, 8), largest definition used */ /*! @} */ /* The count of I2S_RFR */ #define I2S_RFR_COUNT (8U) /*! @name RMR - Receive Mask */ /*! @{ */ #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask * 0b00000000000000000000000000000000..Enable * 0b00000000000000000000000000000001..Mask */ #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /*! @} */ /*! @name RTCR - Receive Timestamp Control */ /*! @{ */ #define I2S_RTCR_TSEN_MASK (0x1U) #define I2S_RTCR_TSEN_SHIFT (0U) /*! TSEN - Timestamp Enable * 0b0..Disable * 0b1..Enable */ #define I2S_RTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK) #define I2S_RTCR_TSINC_MASK (0x2U) #define I2S_RTCR_TSINC_SHIFT (1U) /*! TSINC - Timestamp Increment * 0b0..When enabled and after the bit counter has incremented * 0b1..When enabled */ #define I2S_RTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK) #define I2S_RTCR_TSSEL_MASK (0xCU) #define I2S_RTCR_TSSEL_SHIFT (2U) /*! TSSEL - Timestamp Select * 0b00..Increment when enabled * 0b01..Increment when the transmit timestamp counter is enabled * 0b10..Increment when the receive timestamp counter on another instance is enabled * 0b11..Increment when the transmit timestamp counter on another instance is enabled */ #define I2S_RTCR_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSSEL_SHIFT)) & I2S_RTCR_TSSEL_MASK) #define I2S_RTCR_RTSC_MASK (0x100U) #define I2S_RTCR_RTSC_SHIFT (8U) /*! RTSC - Reset Timestamp Counter * 0b0..No effect * 0b1..Reset */ #define I2S_RTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK) #define I2S_RTCR_RBC_MASK (0x200U) #define I2S_RTCR_RBC_SHIFT (9U) /*! RBC - Reset Bit Counter * 0b0..No effect * 0b1..Reset */ #define I2S_RTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK) /*! @} */ /*! @name RTSR - Receive Timestamp */ /*! @{ */ #define I2S_RTSR_TSC_MASK (0xFFFFFFFFU) #define I2S_RTSR_TSC_SHIFT (0U) /*! TSC - Timestamp Counter */ #define I2S_RTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK) /*! @} */ /*! @name RBCR - Receive Bit Count */ /*! @{ */ #define I2S_RBCR_BCNT_MASK (0xFFFFFFFFU) #define I2S_RBCR_BCNT_SHIFT (0U) /*! BCNT - Bit Counter */ #define I2S_RBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK) /*! @} */ /*! @name RBCTR - Receive Bit Count Timestamp */ /*! @{ */ #define I2S_RBCTR_BCTS_MASK (0xFFFFFFFFU) #define I2S_RBCTR_BCTS_SHIFT (0U) /*! BCTS - Bit Timestamp */ #define I2S_RBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK) /*! @} */ /*! @name MCR - MCLK Control */ /*! @{ */ #define I2S_MCR_DIV_MASK (0xFFU) #define I2S_MCR_DIV_SHIFT (0U) /*! DIV - MCLK Post Divide */ #define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) #define I2S_MCR_DIVEN_MASK (0x800000U) #define I2S_MCR_DIVEN_SHIFT (23U) /*! DIVEN - MCLK Post Divide Enable * 0b0..Disable * 0b1..Enable */ #define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) #define I2S_MCR_MSEL_MASK (0x3000000U) #define I2S_MCR_MSEL_SHIFT (24U) /*! MSEL - MCLK Select * 0b00..Controller clock (MCLK) option 1 * 0b01..Reserved * 0b10..Controller clock (MCLK) option 2 * 0b11..Controller clock (MCLK) option 3 */ #define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) #define I2S_MCR_MOE_MASK (0x40000000U) #define I2S_MCR_MOE_SHIFT (30U) /*! MOE - MCLK Output Enable * 0b0..Input * 0b1..Output */ #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) /*! @} */ /*! * @} */ /* end of group I2S_Register_Masks */ /* I2S - Peripheral instance base addresses */ /** Peripheral SAI1 base address */ #define SAI1_BASE (0x443B0000u) /** Peripheral SAI1 base pointer */ #define SAI1 ((I2S_Type *)SAI1_BASE) /** Peripheral SAI2 base address */ #define SAI2_BASE (0x4C880000u) /** Peripheral SAI2 base pointer */ #define SAI2 ((I2S_Type *)SAI2_BASE) /** Peripheral SAI3 base address */ #define SAI3_BASE (0x42650000u) /** Peripheral SAI3 base pointer */ #define SAI3 ((I2S_Type *)SAI3_BASE) /** Peripheral SAI4 base address */ #define SAI4_BASE (0x42660000u) /** Peripheral SAI4 base pointer */ #define SAI4 ((I2S_Type *)SAI4_BASE) /** Peripheral SAI5 base address */ #define SAI5_BASE (0x42670000u) /** Peripheral SAI5 base pointer */ #define SAI5 ((I2S_Type *)SAI5_BASE) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE, SAI5_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4, SAI5 } /** Interrupt vectors for the I2S peripheral type */ #define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn, SAI5_IRQn } #define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_IRQn, SAI4_IRQn, SAI5_IRQn } /*! * @} */ /* end of group I2S_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I3C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer * @{ */ /** I3C - Register Layout Typedef */ typedef struct { __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ uint8_t RESERVED_0[8]; __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ uint8_t RESERVED_1[4]; __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ uint8_t RESERVED_2[8]; union { /* offset: 0x54 */ __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ }; uint8_t RESERVED_3[4]; __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ uint8_t RESERVED_4[4]; __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ uint8_t RESERVED_5[8]; __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ uint8_t RESERVED_6[4]; __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ union { /* offset: 0xCC */ __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ }; union { /* offset: 0xD0 */ __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ }; __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ union { /* offset: 0xD8 */ __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ }; __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ uint8_t RESERVED_7[4]; __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ uint8_t RESERVED_8[24]; __IO uint32_t SRSTACTTIME; /**< Timing Rules for Target Reset Recovery, offset: 0x100 */ uint8_t RESERVED_9[8]; __IO uint32_t SCCCMASK; /**< CCC Mask for Unhandled CCCs, offset: 0x10C */ __IO uint32_t SERRWARNMASK; /**< Target Errors and Warnings Mask, offset: 0x110 */ uint8_t RESERVED_10[8]; __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ __IO uint32_t SMAPCTRL1; /**< Map Feature Control 1, offset: 0x120 */ uint8_t RESERVED_11[28]; __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ uint8_t RESERVED_12[3752]; __IO uint32_t SELFRESET; /**< Self Reset, offset: 0xFF0 */ } I3C_Type; /* ---------------------------------------------------------------------------- -- I3C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I3C_Register_Masks I3C Register Masks * @{ */ /*! @name MCONFIG - Controller Configuration */ /*! @{ */ #define I3C_MCONFIG_MSTENA_MASK (0x3U) #define I3C_MCONFIG_MSTENA_SHIFT (0U) /*! MSTENA - Controller Enable * 0b00..CONTROLLER_OFF * 0b01..CONTROLLER_ON * 0b10..CONTROLLER_CAPABLE * 0b11.. */ #define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) #define I3C_MCONFIG_DISTO_MASK (0x8U) #define I3C_MCONFIG_DISTO_SHIFT (3U) /*! DISTO - Disable Timeout * 0b1..Disabled, if configured * 0b0..Enabled */ #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) #define I3C_MCONFIG_HKEEP_MASK (0x30U) #define I3C_MCONFIG_HKEEP_SHIFT (4U) /*! HKEEP - High-Keeper * 0b00..None * 0b01..WIRED_IN * 0b10..PASSIVE_SDA * 0b11..PASSIVE_ON_SDA_SCL */ #define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) #define I3C_MCONFIG_ODSTOP_MASK (0x40U) #define I3C_MCONFIG_ODSTOP_SHIFT (6U) /*! ODSTOP - Open Drain Stop * 0b1..Enable * 0b0..Disable */ #define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) #define I3C_MCONFIG_PPBAUD_MASK (0xF00U) #define I3C_MCONFIG_PPBAUD_SHIFT (8U) /*! PPBAUD - Push-Pull Baud Rate */ #define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) #define I3C_MCONFIG_PPLOW_MASK (0xF000U) #define I3C_MCONFIG_PPLOW_SHIFT (12U) /*! PPLOW - Push-Pull Low */ #define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) #define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) #define I3C_MCONFIG_ODBAUD_SHIFT (16U) /*! ODBAUD - Open Drain Baud Rate */ #define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) #define I3C_MCONFIG_ODHPP_SHIFT (24U) /*! ODHPP - Open Drain High Push-Pull * 0b1..Enable * 0b0..Disable */ #define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) #define I3C_MCONFIG_SKEW_MASK (0xE000000U) #define I3C_MCONFIG_SKEW_SHIFT (25U) /*! SKEW - Skew */ #define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) #define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) #define I3C_MCONFIG_I2CBAUD_SHIFT (28U) /*! I2CBAUD - I2C Baud Rate */ #define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) /*! @} */ /*! @name SCONFIG - Target Configuration */ /*! @{ */ #define I3C_SCONFIG_SLVENA_MASK (0x1U) #define I3C_SCONFIG_SLVENA_SHIFT (0U) /*! SLVENA - Target Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) #define I3C_SCONFIG_NACK_MASK (0x2U) #define I3C_SCONFIG_NACK_SHIFT (1U) /*! NACK - Not Acknowledge * 0b1..Always enable NACK mode (works normally) * 0b0..Always disable NACK mode */ #define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) #define I3C_SCONFIG_MATCHSS_MASK (0x4U) #define I3C_SCONFIG_MATCHSS_SHIFT (2U) /*! MATCHSS - Match Start or Stop * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) #define I3C_SCONFIG_S0IGNORE_MASK (0x8U) #define I3C_SCONFIG_S0IGNORE_SHIFT (3U) /*! S0IGNORE - Ignore TE0 or TE1 Errors * 0b1..Ignore TE0 or TE1 errors * 0b0..Do not ignore TE0 or TE1 errors */ #define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) #define I3C_SCONFIG_HDROK_MASK (0x10U) #define I3C_SCONFIG_HDROK_SHIFT (4U) /*! HDROK - HDR OK * 0b1..Enable HDR OK * 0b0..Disable HDR OK */ #define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) #define I3C_SCONFIG_OFFLINE_MASK (0x200U) #define I3C_SCONFIG_OFFLINE_SHIFT (9U) /*! OFFLINE - Offline * 0b1..Enable * 0b0..Disable */ #define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) #define I3C_SCONFIG_BAMATCH_MASK (0x3F0000U) #define I3C_SCONFIG_BAMATCH_SHIFT (16U) /*! BAMATCH - Bus Available Match */ #define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) #define I3C_SCONFIG_SADDR_MASK (0xFE000000U) #define I3C_SCONFIG_SADDR_SHIFT (25U) /*! SADDR - Static Address */ #define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) /*! @} */ /*! @name SSTATUS - Target Status */ /*! @{ */ #define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) #define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) /*! STNOTSTOP - Status not Stop * 0b1..Busy * 0b0..In STOP condition */ #define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) #define I3C_SSTATUS_STMSG_MASK (0x2U) #define I3C_SSTATUS_STMSG_SHIFT (1U) /*! STMSG - Status Message * 0b1..Busy * 0b0..Idle */ #define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) #define I3C_SSTATUS_STCCCH_MASK (0x4U) #define I3C_SSTATUS_STCCCH_SHIFT (2U) /*! STCCCH - Status Common Command Code Handler * 0b1..Handled automatically * 0b0..No CCC message handled */ #define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) #define I3C_SSTATUS_STREQRD_MASK (0x8U) #define I3C_SSTATUS_STREQRD_SHIFT (3U) /*! STREQRD - Status Request Read * 0b1..SDR read from this target or an IBI is being pushed out * 0b0..Not an SDR read */ #define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) #define I3C_SSTATUS_STREQWR_MASK (0x10U) #define I3C_SSTATUS_STREQWR_SHIFT (4U) /*! STREQWR - Status Request Write * 0b1..SDR write data from the controller, but not in ENTDAA mode * 0b0..Not an SDR write */ #define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) #define I3C_SSTATUS_STDAA_MASK (0x20U) #define I3C_SSTATUS_STDAA_SHIFT (5U) /*! STDAA - Status Dynamic Address Assignment * 0b1..In ENTDAA mode * 0b0..Not in ENTDAA mode */ #define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) #define I3C_SSTATUS_STHDR_MASK (0x40U) #define I3C_SSTATUS_STHDR_SHIFT (6U) /*! STHDR - Status High Data Rate * 0b1..I3C bus in HDR-DDR mode * 0b0..I3C bus not in HDR-DDR mode */ #define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) #define I3C_SSTATUS_START_MASK (0x100U) #define I3C_SSTATUS_START_SHIFT (8U) /*! START - Start * 0b1..Detected * 0b0..Not detected * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) #define I3C_SSTATUS_MATCHED_MASK (0x200U) #define I3C_SSTATUS_MATCHED_SHIFT (9U) /*! MATCHED - Matched * 0b1..Header matched * 0b0..Header not matched * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) #define I3C_SSTATUS_STOP_MASK (0x400U) #define I3C_SSTATUS_STOP_SHIFT (10U) /*! STOP - Stop * 0b1..Stopped state detected * 0b0..No Stopped state detected * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) #define I3C_SSTATUS_RX_PEND_MASK (0x800U) #define I3C_SSTATUS_RX_PEND_SHIFT (11U) /*! RX_PEND - Received Message Pending * 0b1..Received message pending * 0b0..No received message pending */ #define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) #define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - Transmit Buffer Not Full * 0b1..Transmit buffer not full * 0b0..Transmit buffer full */ #define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) #define I3C_SSTATUS_DACHG_MASK (0x2000U) #define I3C_SSTATUS_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change * 0b1..DA change detected * 0b0..No DA change detected * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) #define I3C_SSTATUS_CCC_MASK (0x4000U) #define I3C_SSTATUS_CCC_SHIFT (14U) /*! CCC - Common Command Code * 0b1..CCC received * 0b0..CCC not received * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) #define I3C_SSTATUS_ERRWARN_MASK (0x8000U) #define I3C_SSTATUS_ERRWARN_SHIFT (15U) /*! ERRWARN - Error Warning */ #define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) #define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) #define I3C_SSTATUS_HDRMATCH_SHIFT (16U) /*! HDRMATCH - High Data Rate Command Match * 0b1..Matched the I3C dynamic address * 0b0..Did not match * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) #define I3C_SSTATUS_CHANDLED_MASK (0x20000U) #define I3C_SSTATUS_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code Handled * 0b1..CCC handling in progress * 0b0..CCC handling not in progress * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) #define I3C_SSTATUS_EVENT_MASK (0x40000U) #define I3C_SSTATUS_EVENT_SHIFT (18U) /*! EVENT - Event * 0b1..IBI, CR, or HJ occurred * 0b0..No event occurred * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) #define I3C_SSTATUS_SLVRST_MASK (0x80000U) #define I3C_SSTATUS_SLVRST_SHIFT (19U) /*! SLVRST - Target Reset */ #define I3C_SSTATUS_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_SLVRST_SHIFT)) & I3C_SSTATUS_SLVRST_MASK) #define I3C_SSTATUS_EVDET_MASK (0x300000U) #define I3C_SSTATUS_EVDET_SHIFT (20U) /*! EVDET - Event Details * 0b00..NONE (no event or no pending event) * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) */ #define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) #define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) #define I3C_SSTATUS_IBIDIS_SHIFT (24U) /*! IBIDIS - In-Band Interrupts Disable * 0b1..Disabled * 0b0..Enabled */ #define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) #define I3C_SSTATUS_MRDIS_MASK (0x2000000U) #define I3C_SSTATUS_MRDIS_SHIFT (25U) /*! MRDIS - Controller Requests Disable * 0b1..Disabled * 0b0..Enabled */ #define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) #define I3C_SSTATUS_HJDIS_MASK (0x8000000U) #define I3C_SSTATUS_HJDIS_SHIFT (27U) /*! HJDIS - Hot-Join Disabled * 0b1..Disabled * 0b0..Enabled */ #define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) #define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) #define I3C_SSTATUS_ACTSTATE_SHIFT (28U) /*! ACTSTATE - Activity State from Common Command Codes (CCC) * 0b00..NO_LATENCY (normal bus operations) * 0b01..LATENCY_1MS (1 ms of latency) * 0b10..LATENCY_100MS (100 ms of latency) * 0b11..LATENCY_10S (10 seconds of latency) */ #define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) #define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) #define I3C_SSTATUS_TIMECTRL_SHIFT (30U) /*! TIMECTRL - Time Control * 0b00..NO_TIME_CONTROL (no time control is enabled) * 0b01..SYNC_MODE (Synchronous mode is enabled) * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) */ #define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) /*! @} */ /*! @name SCTRL - Target Control */ /*! @{ */ #define I3C_SCTRL_EVENT_MASK (0x3U) #define I3C_SCTRL_EVENT_SHIFT (0U) /*! EVENT - Event * 0b00..NORMAL_MODE * 0b01..IBI * 0b10..CONTROLLER_REQUEST * 0b11..HOT_JOIN_REQUEST */ #define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) #define I3C_SCTRL_EXTDATA_MASK (0x8U) #define I3C_SCTRL_EXTDATA_SHIFT (3U) /*! EXTDATA - Extended Data * 0b1..Enable * 0b0..Disable */ #define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) #define I3C_SCTRL_MAPIDX_MASK (0x10U) #define I3C_SCTRL_MAPIDX_SHIFT (4U) /*! MAPIDX - Map Index */ #define I3C_SCTRL_MAPIDX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_MAPIDX_SHIFT)) & I3C_SCTRL_MAPIDX_MASK) #define I3C_SCTRL_IBIDATA_MASK (0xFF00U) #define I3C_SCTRL_IBIDATA_SHIFT (8U) /*! IBIDATA - In-Band Interrupt Data */ #define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) #define I3C_SCTRL_PENDINT_MASK (0xF0000U) #define I3C_SCTRL_PENDINT_SHIFT (16U) /*! PENDINT - Pending Interrupt */ #define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) #define I3C_SCTRL_ACTSTATE_MASK (0x300000U) #define I3C_SCTRL_ACTSTATE_SHIFT (20U) /*! ACTSTATE - Activity State of Target */ #define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) #define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) #define I3C_SCTRL_VENDINFO_SHIFT (24U) /*! VENDINFO - Vendor Information */ #define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) /*! @} */ /*! @name SINTSET - Target Interrupt Set */ /*! @{ */ #define I3C_SINTSET_START_MASK (0x100U) #define I3C_SINTSET_START_SHIFT (8U) /*! START - Start Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) #define I3C_SINTSET_MATCHED_MASK (0x200U) #define I3C_SINTSET_MATCHED_SHIFT (9U) /*! MATCHED - Match Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) #define I3C_SINTSET_STOP_MASK (0x400U) #define I3C_SINTSET_STOP_SHIFT (10U) /*! STOP - Stop Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) #define I3C_SINTSET_RXPEND_MASK (0x800U) #define I3C_SINTSET_RXPEND_SHIFT (11U) /*! RXPEND - Receive Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) #define I3C_SINTSET_TXSEND_MASK (0x1000U) #define I3C_SINTSET_TXSEND_SHIFT (12U) /*! TXSEND - Transmit Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) #define I3C_SINTSET_DACHG_MASK (0x2000U) #define I3C_SINTSET_DACHG_SHIFT (13U) /*! DACHG - Dynamic Address Change Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) #define I3C_SINTSET_CCC_MASK (0x4000U) #define I3C_SINTSET_CCC_SHIFT (14U) /*! CCC - Common Command Code (CCC) Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) #define I3C_SINTSET_ERRWARN_MASK (0x8000U) #define I3C_SINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) #define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) #define I3C_SINTSET_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - Double Data Rate Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) #define I3C_SINTSET_CHANDLED_MASK (0x20000U) #define I3C_SINTSET_CHANDLED_SHIFT (17U) /*! CHANDLED - Common Command Code (CCC) Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) #define I3C_SINTSET_EVENT_MASK (0x40000U) #define I3C_SINTSET_EVENT_SHIFT (18U) /*! EVENT - Event Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) #define I3C_SINTSET_SLVRST_MASK (0x80000U) #define I3C_SINTSET_SLVRST_SHIFT (19U) /*! SLVRST - Target Reset * 0b1..Enable * 0b0..Disable */ #define I3C_SINTSET_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_SLVRST_SHIFT)) & I3C_SINTSET_SLVRST_MASK) /*! @} */ /*! @name SINTCLR - Target Interrupt Clear */ /*! @{ */ #define I3C_SINTCLR_START_MASK (0x100U) #define I3C_SINTCLR_START_SHIFT (8U) /*! START - START Interrupt Enable Clear */ #define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) #define I3C_SINTCLR_MATCHED_MASK (0x200U) #define I3C_SINTCLR_MATCHED_SHIFT (9U) /*! MATCHED - Matched Interrupt Enable Clear */ #define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) #define I3C_SINTCLR_STOP_MASK (0x400U) #define I3C_SINTCLR_STOP_SHIFT (10U) /*! STOP - STOP Interrupt Enable Clear */ #define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) #define I3C_SINTCLR_RXPEND_MASK (0x800U) #define I3C_SINTCLR_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Enable Clear */ #define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) #define I3C_SINTCLR_TXSEND_MASK (0x1000U) #define I3C_SINTCLR_TXSEND_SHIFT (12U) /*! TXSEND - TXSEND Interrupt Enable Clear */ #define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) #define I3C_SINTCLR_DACHG_MASK (0x2000U) #define I3C_SINTCLR_DACHG_SHIFT (13U) /*! DACHG - DACHG Interrupt Enable Clear */ #define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) #define I3C_SINTCLR_CCC_MASK (0x4000U) #define I3C_SINTCLR_CCC_SHIFT (14U) /*! CCC - CCC Interrupt Enable Clear */ #define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) #define I3C_SINTCLR_ERRWARN_MASK (0x8000U) #define I3C_SINTCLR_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Enable Clear */ #define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) #define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) #define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */ #define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) #define I3C_SINTCLR_CHANDLED_MASK (0x20000U) #define I3C_SINTCLR_CHANDLED_SHIFT (17U) /*! CHANDLED - CHANDLED Interrupt Enable Clear */ #define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) #define I3C_SINTCLR_EVENT_MASK (0x40000U) #define I3C_SINTCLR_EVENT_SHIFT (18U) /*! EVENT - EVENT Interrupt Enable Clear */ #define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) #define I3C_SINTCLR_SLVRST_MASK (0x80000U) #define I3C_SINTCLR_SLVRST_SHIFT (19U) /*! SLVRST - Target Reset (SLVRST Interrupt Enable Clear) */ #define I3C_SINTCLR_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_SLVRST_SHIFT)) & I3C_SINTCLR_SLVRST_MASK) /*! @} */ /*! @name SINTMASKED - Target Interrupt Mask */ /*! @{ */ #define I3C_SINTMASKED_START_MASK (0x100U) #define I3C_SINTMASKED_START_SHIFT (8U) /*! START - START Interrupt Mask */ #define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) #define I3C_SINTMASKED_MATCHED_MASK (0x200U) #define I3C_SINTMASKED_MATCHED_SHIFT (9U) /*! MATCHED - MATCHED Interrupt Mask */ #define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) #define I3C_SINTMASKED_STOP_MASK (0x400U) #define I3C_SINTMASKED_STOP_SHIFT (10U) /*! STOP - STOP Interrupt Mask */ #define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) #define I3C_SINTMASKED_RXPEND_MASK (0x800U) #define I3C_SINTMASKED_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Mask */ #define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) #define I3C_SINTMASKED_TXSEND_MASK (0x1000U) #define I3C_SINTMASKED_TXSEND_SHIFT (12U) /*! TXSEND - TXSEND Interrupt Mask */ #define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) #define I3C_SINTMASKED_DACHG_MASK (0x2000U) #define I3C_SINTMASKED_DACHG_SHIFT (13U) /*! DACHG - DACHG Interrupt Mask */ #define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) #define I3C_SINTMASKED_CCC_MASK (0x4000U) #define I3C_SINTMASKED_CCC_SHIFT (14U) /*! CCC - CCC Interrupt Mask */ #define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) #define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_SINTMASKED_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Mask */ #define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) #define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) #define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) /*! DDRMATCHED - DDRMATCHED Interrupt Mask */ #define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) #define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) #define I3C_SINTMASKED_CHANDLED_SHIFT (17U) /*! CHANDLED - CHANDLED Interrupt Mask */ #define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) #define I3C_SINTMASKED_EVENT_MASK (0x40000U) #define I3C_SINTMASKED_EVENT_SHIFT (18U) /*! EVENT - EVENT Interrupt Mask */ #define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) #define I3C_SINTMASKED_SLVRST_MASK (0x80000U) #define I3C_SINTMASKED_SLVRST_SHIFT (19U) /*! SLVRST - Target Reset Interrupt Mask */ #define I3C_SINTMASKED_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_SLVRST_SHIFT)) & I3C_SINTMASKED_SLVRST_MASK) /*! @} */ /*! @name SERRWARN - Target Errors and Warnings */ /*! @{ */ #define I3C_SERRWARN_ORUN_MASK (0x1U) #define I3C_SERRWARN_ORUN_SHIFT (0U) /*! ORUN - Overrun Error * 0b1..Overrun error * 0b0..No overrun error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) #define I3C_SERRWARN_URUN_MASK (0x2U) #define I3C_SERRWARN_URUN_SHIFT (1U) /*! URUN - Underrun Error * 0b1..Underrun error * 0b0..No underrun error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) #define I3C_SERRWARN_URUNNACK_MASK (0x4U) #define I3C_SERRWARN_URUNNACK_SHIFT (2U) /*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error * 0b1..Underrun; not acknowledged error * 0b0..No underrun; not acknowledged error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) #define I3C_SERRWARN_TERM_MASK (0x8U) #define I3C_SERRWARN_TERM_SHIFT (3U) /*! TERM - Terminated Error * 0b1..Terminated error * 0b0..No terminated error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) #define I3C_SERRWARN_INVSTART_MASK (0x10U) #define I3C_SERRWARN_INVSTART_SHIFT (4U) /*! INVSTART - Invalid Start Error * 0b1..Invalid start error * 0b0..No invalid start error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) #define I3C_SERRWARN_SPAR_MASK (0x100U) #define I3C_SERRWARN_SPAR_SHIFT (8U) /*! SPAR - SDR Parity Error * 0b1..SDR parity error * 0b0..No SDR parity error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) #define I3C_SERRWARN_HPAR_MASK (0x200U) #define I3C_SERRWARN_HPAR_SHIFT (9U) /*! HPAR - HDR Parity Error * 0b1..HDR parity error * 0b0..No HDR parity error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) #define I3C_SERRWARN_HCRC_MASK (0x400U) #define I3C_SERRWARN_HCRC_SHIFT (10U) /*! HCRC - HDR-DDR CRC Error * 0b1..HDR-DDR CRC error occurred * 0b0..No HDR-DDR CRC error occurred * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) #define I3C_SERRWARN_S0S1_MASK (0x800U) #define I3C_SERRWARN_S0S1_SHIFT (11U) /*! S0S1 - TE0 or TE1 Error * 0b1..TE0 or TE1 error occurred * 0b0..No TE0 or TE1 error occurred * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) #define I3C_SERRWARN_OREAD_MASK (0x10000U) #define I3C_SERRWARN_OREAD_SHIFT (16U) /*! OREAD - Over-Read Error * 0b1..Over-read error * 0b0..No over-read error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) #define I3C_SERRWARN_OWRITE_MASK (0x20000U) #define I3C_SERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Over-Write Error * 0b1..Overwrite error * 0b0..No overwrite error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) /*! @} */ /*! @name SDMACTRL - Target DMA Control */ /*! @{ */ #define I3C_SDMACTRL_DMAFB_MASK (0x3U) #define I3C_SDMACTRL_DMAFB_SHIFT (0U) /*! DMAFB - DMA Read (From-Bus) Trigger * 0b00..DMA not used * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ #define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) #define I3C_SDMACTRL_DMATB_MASK (0xCU) #define I3C_SDMACTRL_DMATB_SHIFT (2U) /*! DMATB - DMA Write (To-Bus) Trigger * 0b00..DMA not used * 0b01..DMA enabled for one frame * 0b10..DMA enabled until turned off * 0b11.. */ #define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) #define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) #define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) /*! DMAWIDTH - Width of DMA Operations * 0b00, 0b01..Byte * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) * 0b11.. */ #define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) /*! @} */ /*! @name SDATACTRL - Target Data Control */ /*! @{ */ #define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) /*! FLUSHTB - Flush To-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) #define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) /*! FLUSHFB - Flush From-Bus Buffer or FIFO */ #define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) #define I3C_SDATACTRL_UNLOCK_MASK (0x8U) #define I3C_SDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock * 0b0..Cannot be changed * 0b1..Can be changed */ #define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) #define I3C_SDATACTRL_TXTRIG_MASK (0x30U) #define I3C_SDATACTRL_TXTRIG_SHIFT (4U) /*! TXTRIG - Transmit Trigger Level * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less * 0b11..Default (trigger when 1 less than full or less) */ #define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) #define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) #define I3C_SDATACTRL_RXTRIG_SHIFT (6U) /*! RXTRIG - Receive Trigger Level * 0b00..Trigger when not empty * 0b01..Trigger when 1/4 or more full * 0b10..Trigger when 1/2 or more full * 0b11..Trigger when 3/4 or more full */ #define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) #define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) #define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) /*! TXCOUNT - Count of Bytes in Transmit */ #define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) #define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) #define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Count of Bytes in Receive */ #define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) #define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_SDATACTRL_TXFULL_SHIFT (30U) /*! TXFULL - Transmit is Full * 0b1..Full * 0b0..Not full */ #define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) #define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) /*! RXEMPTY - Receive is Empty * 0b1..Empty * 0b0..Not empty */ #define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) /*! @} */ /*! @name SWDATAB - Target Write Data Byte */ /*! @{ */ #define I3C_SWDATAB_DATA_MASK (0xFFU) #define I3C_SWDATAB_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) #define I3C_SWDATAB_END_MASK (0x100U) #define I3C_SWDATAB_END_SHIFT (8U) /*! END - End * 0b1..End * 0b0..Not the end */ #define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) #define I3C_SWDATAB_END_ALSO_MASK (0x10000U) #define I3C_SWDATAB_END_ALSO_SHIFT (16U) /*! END_ALSO - End Also * 0b1..End * 0b0..Not the end */ #define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) /*! @} */ /*! @name SWDATABE - Target Write Data Byte End */ /*! @{ */ #define I3C_SWDATABE_DATA_MASK (0xFFU) #define I3C_SWDATABE_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) /*! @} */ /*! @name SWDATAH - Target Write Data Halfword */ /*! @{ */ #define I3C_SWDATAH_DATA0_MASK (0xFFU) #define I3C_SWDATAH_DATA0_SHIFT (0U) /*! DATA0 - Data 0 */ #define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) #define I3C_SWDATAH_DATA1_MASK (0xFF00U) #define I3C_SWDATAH_DATA1_SHIFT (8U) /*! DATA1 - Data 1 */ #define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) #define I3C_SWDATAH_END_MASK (0x10000U) #define I3C_SWDATAH_END_SHIFT (16U) /*! END - End of Message * 0b1..End * 0b0..Not the end */ #define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) /*! @} */ /*! @name SWDATAHE - Target Write Data Halfword End */ /*! @{ */ #define I3C_SWDATAHE_DATA0_MASK (0xFFU) #define I3C_SWDATAHE_DATA0_SHIFT (0U) /*! DATA0 - Data 0 */ #define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) #define I3C_SWDATAHE_DATA1_MASK (0xFF00U) #define I3C_SWDATAHE_DATA1_SHIFT (8U) /*! DATA1 - Data 1 */ #define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) /*! @} */ /*! @name SRDATAB - Target Read Data Byte */ /*! @{ */ #define I3C_SRDATAB_DATA0_MASK (0xFFU) #define I3C_SRDATAB_DATA0_SHIFT (0U) /*! DATA0 - Data 0 */ #define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) /*! @} */ /*! @name SRDATAH - Target Read Data Halfword */ /*! @{ */ #define I3C_SRDATAH_LSB_MASK (0xFFU) #define I3C_SRDATAH_LSB_SHIFT (0U) /*! LSB - Low Byte */ #define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) #define I3C_SRDATAH_MSB_MASK (0xFF00U) #define I3C_SRDATAH_MSB_SHIFT (8U) /*! MSB - High Byte */ #define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) /*! @} */ /*! @name SWDATAB1 - Target Write Data Byte */ /*! @{ */ #define I3C_SWDATAB1_DATA_MASK (0xFFU) #define I3C_SWDATAB1_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) /*! @} */ /*! @name SWDATAH1 - Target Write Data Halfword */ /*! @{ */ #define I3C_SWDATAH1_DATA_MASK (0xFFFFU) #define I3C_SWDATAH1_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) /*! @} */ /*! @name SCAPABILITIES2 - Target Capabilities 2 */ /*! @{ */ #define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) #define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) /*! MAPCNT - Map Count */ #define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) #define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) #define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) /*! I2C10B - I2C 10-bit Address * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) #define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) #define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) /*! I2CRST - I2C Software Reset * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) #define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) /*! I2CDEVID - I2C Device ID * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) #define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) #define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) /*! IBIEXT - In-Band Interrupt EXTDATA * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) #define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) #define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) /*! IBIXREG - In-Band Interrupt Extended Register * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) #define I3C_SCAPABILITIES2_V1_1_MASK (0x10000U) #define I3C_SCAPABILITIES2_V1_1_SHIFT (16U) /*! V1_1 - Version 1.1 * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_V1_1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_V1_1_SHIFT)) & I3C_SCAPABILITIES2_V1_1_MASK) #define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) #define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) /*! SLVRST - Target Reset * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) #define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) #define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) /*! GROUP - Group * 0b00..v1.1 group addressing not supported * 0b01..One group supported * 0b10..Two groups supported * 0b11..Three groups supported */ #define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) #define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) #define I3C_SCAPABILITIES2_AASA_SHIFT (21U) /*! AASA - SETAASA * 0b1..SETAASA supported * 0b0..SETAASA not supported */ #define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) #define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) #define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) /*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable * 0b1..Subscriber capable * 0b0..Not subscriber capable */ #define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) #define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) #define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) /*! SSTWR - Target-Target(s)-Tunnel Write Capable * 0b1..Write capable * 0b0..Not write capable */ #define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) /*! @} */ /*! @name SCAPABILITIES - Target Capabilities */ /*! @{ */ #define I3C_SCAPABILITIES_IDENA_MASK (0x3U) #define I3C_SCAPABILITIES_IDENA_SHIFT (0U) /*! IDENA - ID 48b Handler * 0b00..Application * 0b01..Hardware * 0b10..Hardware, but the I3C module instance handles ID 48b * 0b11..A part number register (PARTNO) */ #define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) #define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) #define I3C_SCAPABILITIES_IDREG_SHIFT (2U) /*! IDREG - ID Register * 0b0000..All ID register features disabled * 0bxxx1..ID Instance is a register; used if there is no PARTNO register * 0bxx1x..An ID Random field is available * 0bx1xx..A Device Characteristic Register (DCR) is available * 0b1xxx..A Bus Characteristics Register (BCR) is available */ #define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) #define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) #define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) /*! HDRSUPP - High Data Rate Support * 0b00..No HDR modes supported * 0b01..DDR mode supported * *.. */ #define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) #define I3C_SCAPABILITIES_MASTER_MASK (0x200U) #define I3C_SCAPABILITIES_MASTER_SHIFT (9U) /*! MASTER - Controller * 0b0..Not supported * 0b1..Supported */ #define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) #define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) #define I3C_SCAPABILITIES_SADDR_SHIFT (10U) /*! SADDR - Static Address * 0b00..No static address * 0b01..Static address is fixed in hardware * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) * 0b11..SCONFIG register supplies the static address */ #define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) #define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) #define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) /*! CCCHANDLE - Common Command Codes Handling * 0b0000..All handling features disabled * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] */ #define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) #define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) #define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) /*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events * 0b00000..Application cannot generate IBI, CR, or HJ * 0bxxxx1..Application can generate an IBI * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register * 0bxx1xx..Application can generate a controller request for a secondary controller * 0bx1xxx..Application can generate a Hot-Join event * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing */ #define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) #define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) #define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) /*! TIMECTRL - Time Control * 0b0..No time control supported * 0b1..At least one time-control type supported */ #define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) #define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) #define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) /*! EXTFIFO - External FIFO * 0b000..No external FIFO available * 0b001..Standard available or free external FIFO * 0b010..Request track external FIFO * *.. */ #define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) #define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) #define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) /*! FIFOTX - FIFO Transmit * 0b00..Two * 0b01..Four * 0b10..Eight * 0b11..16 or larger */ #define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) #define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) #define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) /*! FIFORX - FIFO Receive * 0b00..Two or three * 0b01..Four * 0b10..Eight * 0b11..16 or larger */ #define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) #define I3C_SCAPABILITIES_INT_MASK (0x40000000U) #define I3C_SCAPABILITIES_INT_SHIFT (30U) /*! INT - Interrupts * 0b1..Supported * 0b0..Not supported */ #define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) #define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) #define I3C_SCAPABILITIES_DMA_SHIFT (31U) /*! DMA - Direct Memory Access * 0b1..Supported * 0b0..Not supported */ #define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) /*! @} */ /*! @name SMAXLIMITS - Target Maximum Limits */ /*! @{ */ #define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) #define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) /*! MAXRD - Maximum Read Length */ #define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) #define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) #define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) /*! MAXWR - Maximum Write Length */ #define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) /*! @} */ /*! @name SIDPARTNO - Target ID Part Number */ /*! @{ */ #define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) #define I3C_SIDPARTNO_PARTNO_SHIFT (0U) /*! PARTNO - Part Number */ #define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) /*! @} */ /*! @name SIDEXT - Target ID Extension */ /*! @{ */ #define I3C_SIDEXT_DCR_MASK (0xFF00U) #define I3C_SIDEXT_DCR_SHIFT (8U) /*! DCR - Device Characteristic Register */ #define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) #define I3C_SIDEXT_BCR_MASK (0xFF0000U) #define I3C_SIDEXT_BCR_SHIFT (16U) /*! BCR - Bus Characteristics Register */ #define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) /*! @} */ /*! @name SVENDORID - Target Vendor ID */ /*! @{ */ #define I3C_SVENDORID_VID_MASK (0x7FFFU) #define I3C_SVENDORID_VID_SHIFT (0U) /*! VID - Vendor ID */ #define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) /*! @} */ /*! @name STCCLOCK - Target Time Control Clock */ /*! @{ */ #define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) #define I3C_STCCLOCK_ACCURACY_SHIFT (0U) /*! ACCURACY - Clock Accuracy */ #define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) #define I3C_STCCLOCK_FREQ_MASK (0xFF00U) #define I3C_STCCLOCK_FREQ_SHIFT (8U) /*! FREQ - Clock Frequency */ #define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) /*! @} */ /*! @name SMSGMAPADDR - Target Message Map Address */ /*! @{ */ #define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) #define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) /*! MAPLAST - Matched Address Index */ #define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) #define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) #define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) /*! LASTSTATIC - Last Static Address Matched * 0b1..I2C static address * 0b0..I3C dynamic address */ #define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) #define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) #define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) /*! MAPLASTM1 - Matched Previous Address Index 1 */ #define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) #define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) #define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) /*! MAPLASTM2 - Matched Previous Index 2 */ #define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) /*! @} */ /*! @name MCONFIG_EXT - Controller Extended Configuration */ /*! @{ */ #define I3C_MCONFIG_EXT_I2CBLOW_MASK (0xFU) #define I3C_MCONFIG_EXT_I2CBLOW_SHIFT (0U) /*! I2CBLOW - I2C Baud Low */ #define I3C_MCONFIG_EXT_I2CBLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2CBLOW_SHIFT)) & I3C_MCONFIG_EXT_I2CBLOW_MASK) #define I3C_MCONFIG_EXT_I2CHS_MASK (0x10U) #define I3C_MCONFIG_EXT_I2CHS_SHIFT (4U) /*! I2CHS - I2C HS */ #define I3C_MCONFIG_EXT_I2CHS(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2CHS_SHIFT)) & I3C_MCONFIG_EXT_I2CHS_MASK) #define I3C_MCONFIG_EXT_I2C_A10B_MASK (0x100U) #define I3C_MCONFIG_EXT_I2C_A10B_SHIFT (8U) /*! I2C_A10B - I2C_A10B * 0b0..Disable * 0b1..Enable */ #define I3C_MCONFIG_EXT_I2C_A10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2C_A10B_SHIFT)) & I3C_MCONFIG_EXT_I2C_A10B_MASK) #define I3C_MCONFIG_EXT_I2C_A10BEXT_MASK (0xE00U) #define I3C_MCONFIG_EXT_I2C_A10BEXT_SHIFT (9U) /*! I2C_A10BEXT - I2C_A10BEXT */ #define I3C_MCONFIG_EXT_I2C_A10BEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I2C_A10BEXT_SHIFT)) & I3C_MCONFIG_EXT_I2C_A10BEXT_MASK) #define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) #define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) /*! I3C_CAS_DEL - I3C CAS Delay After START * 0b00..No delay * 0b01..Increases SCL clock period by 1/2 * 0b10..Increases SCL clock period by 1 * 0b11..Increases SCL clock period by 3/2 */ #define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) #define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) #define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) /*! I3C_CASR_DEL - I3C CAS Delay After Repeated START * 0b00..No delay * 0b01..Increases SCL clock period by 1/2 * 0b10..Increases SCL clock period by 1 * 0b11..Increases SCL clock period by 1 1/2 */ #define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) /*! @} */ /*! @name MCTRL - Controller Control */ /*! @{ */ #define I3C_MCTRL_REQUEST_MASK (0x7U) #define I3C_MCTRL_REQUEST_SHIFT (0U) /*! REQUEST - Request * 0b000..NONE * 0b001..EMITSTARTADDR * 0b010..EMITSTOP * 0b011..IBIACKNACK * 0b100..PROCESSDAA * 0b101.. * 0b110..Force Exit and Target Reset * 0b111..AUTOIBI */ #define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) #define I3C_MCTRL_TYPE_MASK (0x30U) #define I3C_MCTRL_TYPE_SHIFT (4U) /*! TYPE - Bus Type with EmitStartAddr * 0b00..I3C * 0b01..I2C * 0b10..DDR * 0b11.. */ #define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) #define I3C_MCTRL_IBIRESP_MASK (0xC0U) #define I3C_MCTRL_IBIRESP_SHIFT (6U) /*! IBIRESP - In-Band Interrupt Response * 0b00..ACK (acknowledge) * 0b01..NACK (reject) * 0b10..Acknowledge with mandatory byte * 0b11..Manual */ #define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) #define I3C_MCTRL_DIR_MASK (0x100U) #define I3C_MCTRL_DIR_SHIFT (8U) /*! DIR - Direction * 0b0..Write * 0b1..Read */ #define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) #define I3C_MCTRL_ADDR_MASK (0xFE00U) #define I3C_MCTRL_ADDR_SHIFT (9U) /*! ADDR - Address */ #define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) #define I3C_MCTRL_RDTERM_MASK (0xFF0000U) #define I3C_MCTRL_RDTERM_SHIFT (16U) /*! RDTERM - Read Terminate Counter */ #define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) /*! @} */ /*! @name MSTATUS - Controller Status */ /*! @{ */ #define I3C_MSTATUS_STATE_MASK (0x7U) #define I3C_MSTATUS_STATE_SHIFT (0U) /*! STATE - State of the Controller * 0b000..IDLE (bus has stopped) * 0b001..SLVREQ (target request) * 0b010..MSGSDR * 0b011..NORMACT * 0b100..MSGDDR * 0b101..DAA * 0b110..IBIACK * 0b111..IBIRCV */ #define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) #define I3C_MSTATUS_BETWEEN_MASK (0x10U) #define I3C_MSTATUS_BETWEEN_SHIFT (4U) /*! BETWEEN - Between * 0b0..Inactive (for other cases) * 0b1..Active */ #define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) #define I3C_MSTATUS_NACKED_MASK (0x20U) #define I3C_MSTATUS_NACKED_SHIFT (5U) /*! NACKED - Not Acknowledged * 0b1..NACKed (not acknowledged) * 0b0..Not NACKed */ #define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) #define I3C_MSTATUS_IBITYPE_MASK (0xC0U) #define I3C_MSTATUS_IBITYPE_SHIFT (6U) /*! IBITYPE - In-Band Interrupt (IBI) Type * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) * 0b01..IBI * 0b10..CR * 0b11..HJ */ #define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) #define I3C_MSTATUS_SLVSTART_MASK (0x100U) #define I3C_MSTATUS_SLVSTART_SHIFT (8U) /*! SLVSTART - Target Start * 0b1..Target requesting START * 0b0..Target not requesting START * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) #define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) #define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - Controller Control Done * 0b1..Done * 0b0..Not done * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) #define I3C_MSTATUS_COMPLETE_MASK (0x400U) #define I3C_MSTATUS_COMPLETE_SHIFT (10U) /*! COMPLETE - Complete * 0b1..Complete * 0b0..Not complete * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) #define I3C_MSTATUS_RXPEND_MASK (0x800U) #define I3C_MSTATUS_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND * 0b1..Receive message pending * 0b0..No receive message pending */ #define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) #define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TX Buffer or FIFO Not Full * 0b1..Receive buffer or FIFO not full * 0b0..Receive buffer or FIFO full */ #define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) #define I3C_MSTATUS_IBIWON_MASK (0x2000U) #define I3C_MSTATUS_IBIWON_SHIFT (13U) /*! IBIWON - In-Band Interrupt (IBI) Won * 0b1..IBI arbitration won * 0b0..No IBI arbitration won * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) #define I3C_MSTATUS_ERRWARN_MASK (0x8000U) #define I3C_MSTATUS_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning * 0b1..Error or warning * 0b0..No error or warning */ #define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) #define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) #define I3C_MSTATUS_NOWMASTER_SHIFT (19U) /*! NOWMASTER - Module is now Controller * 0b1..Controller * 0b0..Not a controller * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) #define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) #define I3C_MSTATUS_IBIADDR_SHIFT (24U) /*! IBIADDR - IBI Address */ #define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) /*! @} */ /*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ /*! @{ */ #define I3C_MIBIRULES_ADDR0_MASK (0x3FU) #define I3C_MIBIRULES_ADDR0_SHIFT (0U) /*! ADDR0 - ADDR0 */ #define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) #define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) #define I3C_MIBIRULES_ADDR1_SHIFT (6U) /*! ADDR1 - ADDR1 */ #define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) #define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) #define I3C_MIBIRULES_ADDR2_SHIFT (12U) /*! ADDR2 - ADDR2 */ #define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) #define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) #define I3C_MIBIRULES_ADDR3_SHIFT (18U) /*! ADDR3 - ADDR3 */ #define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) #define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) #define I3C_MIBIRULES_ADDR4_SHIFT (24U) /*! ADDR4 - ADDR4 */ #define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) #define I3C_MIBIRULES_MSB0_MASK (0x40000000U) #define I3C_MIBIRULES_MSB0_SHIFT (30U) /*! MSB0 - Most Significant Address Bit is 0 * 0b1..MSB is 0 * 0b0..MSB is not 0 */ #define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) #define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) #define I3C_MIBIRULES_NOBYTE_SHIFT (31U) /*! NOBYTE - No IBI byte * 0b1..Without mandatory IBI byte * 0b0..With mandatory IBI byte */ #define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) /*! @} */ /*! @name MINTSET - Controller Interrupt Set */ /*! @{ */ #define I3C_MINTSET_SLVSTART_MASK (0x100U) #define I3C_MINTSET_SLVSTART_SHIFT (8U) /*! SLVSTART - Target Start Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) #define I3C_MINTSET_MCTRLDONE_MASK (0x200U) #define I3C_MINTSET_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - Controller Control Done Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) #define I3C_MINTSET_COMPLETE_MASK (0x400U) #define I3C_MINTSET_COMPLETE_SHIFT (10U) /*! COMPLETE - Completed Message Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) #define I3C_MINTSET_RXPEND_MASK (0x800U) #define I3C_MINTSET_RXPEND_SHIFT (11U) /*! RXPEND - Receive Pending Interrupt Enable */ #define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) #define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) #define I3C_MINTSET_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) #define I3C_MINTSET_IBIWON_MASK (0x2000U) #define I3C_MINTSET_IBIWON_SHIFT (13U) /*! IBIWON - IBI Won Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) #define I3C_MINTSET_ERRWARN_MASK (0x8000U) #define I3C_MINTSET_ERRWARN_SHIFT (15U) /*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) #define I3C_MINTSET_NOWMASTER_MASK (0x80000U) #define I3C_MINTSET_NOWMASTER_SHIFT (19U) /*! NOWMASTER - Now Controller Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) /*! @} */ /*! @name MINTCLR - Controller Interrupt Clear */ /*! @{ */ #define I3C_MINTCLR_SLVSTART_MASK (0x100U) #define I3C_MINTCLR_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) #define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) #define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) #define I3C_MINTCLR_COMPLETE_MASK (0x400U) #define I3C_MINTCLR_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) #define I3C_MINTCLR_RXPEND_MASK (0x800U) #define I3C_MINTCLR_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) #define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) #define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) #define I3C_MINTCLR_IBIWON_MASK (0x2000U) #define I3C_MINTCLR_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) #define I3C_MINTCLR_ERRWARN_MASK (0x8000U) #define I3C_MINTCLR_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) #define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) #define I3C_MINTCLR_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear * 0b1..Interrupt enable cleared * 0b0..No effect * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) /*! @} */ /*! @name MINTMASKED - Controller Interrupt Mask */ /*! @{ */ #define I3C_MINTMASKED_SLVSTART_MASK (0x100U) #define I3C_MINTMASKED_SLVSTART_SHIFT (8U) /*! SLVSTART - SLVSTART Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) #define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) #define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) /*! MCTRLDONE - MCTRLDONE Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) #define I3C_MINTMASKED_COMPLETE_MASK (0x400U) #define I3C_MINTMASKED_COMPLETE_SHIFT (10U) /*! COMPLETE - COMPLETE Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) #define I3C_MINTMASKED_RXPEND_MASK (0x800U) #define I3C_MINTMASKED_RXPEND_SHIFT (11U) /*! RXPEND - RXPEND Interrupt Mask */ #define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) #define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) #define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) /*! TXNOTFULL - TXNOTFULL Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) #define I3C_MINTMASKED_IBIWON_MASK (0x2000U) #define I3C_MINTMASKED_IBIWON_SHIFT (13U) /*! IBIWON - IBIWON Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) #define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_MINTMASKED_ERRWARN_SHIFT (15U) /*! ERRWARN - ERRWARN Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) #define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) #define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) /*! NOWMASTER - NOWCONTROLLER Interrupt Mask * 0b1..Enabled * 0b0..Disabled */ #define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) /*! @} */ /*! @name MERRWARN - Controller Errors and Warnings */ /*! @{ */ #define I3C_MERRWARN_URUN_MASK (0x2U) #define I3C_MERRWARN_URUN_SHIFT (1U) /*! URUN - Underrun Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) #define I3C_MERRWARN_NACK_MASK (0x4U) #define I3C_MERRWARN_NACK_SHIFT (2U) /*! NACK - Not Acknowledge Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) #define I3C_MERRWARN_WRABT_MASK (0x8U) #define I3C_MERRWARN_WRABT_SHIFT (3U) /*! WRABT - Write Abort Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) #define I3C_MERRWARN_TERM_MASK (0x10U) #define I3C_MERRWARN_TERM_SHIFT (4U) /*! TERM - Terminate Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) #define I3C_MERRWARN_HPAR_MASK (0x200U) #define I3C_MERRWARN_HPAR_SHIFT (9U) /*! HPAR - High Data Rate Parity * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) #define I3C_MERRWARN_HCRC_MASK (0x400U) #define I3C_MERRWARN_HCRC_SHIFT (10U) /*! HCRC - High Data Rate CRC Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) #define I3C_MERRWARN_OREAD_MASK (0x10000U) #define I3C_MERRWARN_OREAD_SHIFT (16U) /*! OREAD - Overread Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) #define I3C_MERRWARN_OWRITE_MASK (0x20000U) #define I3C_MERRWARN_OWRITE_SHIFT (17U) /*! OWRITE - Overwrite Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) #define I3C_MERRWARN_MSGERR_MASK (0x40000U) #define I3C_MERRWARN_MSGERR_SHIFT (18U) /*! MSGERR - Message Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) #define I3C_MERRWARN_INVREQ_MASK (0x80000U) #define I3C_MERRWARN_INVREQ_SHIFT (19U) /*! INVREQ - Invalid Request Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) #define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) #define I3C_MERRWARN_TIMEOUT_SHIFT (20U) /*! TIMEOUT - Timeout Error * 0b1..Error * 0b0..No error * 0b0..No effect * 0b1..Clear the flag */ #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) /*! @} */ /*! @name MDMACTRL - Controller DMA Control */ /*! @{ */ #define I3C_MDMACTRL_DMAFB_MASK (0x3U) #define I3C_MDMACTRL_DMAFB_SHIFT (0U) /*! DMAFB - DMA from Bus * 0b00..DMA not used * 0b01..Enable DMA for one frame * 0b10..Enable DMA until DMA is turned off * 0b11.. */ #define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) #define I3C_MDMACTRL_DMATB_MASK (0xCU) #define I3C_MDMACTRL_DMATB_SHIFT (2U) /*! DMATB - DMA to Bus * 0b00..DMA not used * 0b01..Enable DMA for one frame (ended by DMA or terminated) * 0b10..Enable DMA until DMA is turned off * 0b11.. */ #define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) #define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) #define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) /*! DMAWIDTH - DMA Width * 0b00, 0b01..Byte * 0b10..Halfword (16 bits) * 0b11.. */ #define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) /*! @} */ /*! @name MDATACTRL - Controller Data Control */ /*! @{ */ #define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) /*! FLUSHTB - Flush To-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ #define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) #define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) /*! FLUSHFB - Flush From-Bus Buffer or FIFO * 0b1..Flush the buffer * 0b0..No action */ #define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) #define I3C_MDATACTRL_UNLOCK_MASK (0x8U) #define I3C_MDATACTRL_UNLOCK_SHIFT (3U) /*! UNLOCK - Unlock * 0b0..Locked * 0b1..Unlocked */ #define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) #define I3C_MDATACTRL_TXTRIG_MASK (0x30U) #define I3C_MDATACTRL_TXTRIG_SHIFT (4U) /*! TXTRIG - Transmit Trigger Level * 0b00..Trigger when empty * 0b01..Trigger when 1/4 full or less * 0b10..Trigger when 1/2 full or less * 0b11..Trigger when 1 less than full or less (default) */ #define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) #define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) #define I3C_MDATACTRL_RXTRIG_SHIFT (6U) /*! RXTRIG - Receive Trigger Level * 0b00..Trigger when not empty * 0b01..Trigger when 1/4 full or more * 0b10..Trigger when 1/2 full or more * 0b11..Trigger when 3/4 full or more */ #define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) #define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) #define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) /*! TXCOUNT - Transmit Byte Count */ #define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) #define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) #define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Byte Count */ #define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) #define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_MDATACTRL_TXFULL_SHIFT (30U) /*! TXFULL - Transmit is Full * 0b0..Not full * 0b1..Full */ #define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) #define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) /*! RXEMPTY - Receive is Empty * 0b0..Not empty * 0b1..Empty */ #define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) /*! @} */ /*! @name MWDATAB - Controller Write Data Byte */ /*! @{ */ #define I3C_MWDATAB_VALUE_MASK (0xFFU) #define I3C_MWDATAB_VALUE_SHIFT (0U) /*! VALUE - Data Byte */ #define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) #define I3C_MWDATAB_END_MASK (0x100U) #define I3C_MWDATAB_END_SHIFT (8U) /*! END - End of Message * 0b0..Not the end * 0b1..End */ #define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) #define I3C_MWDATAB_END_ALSO_MASK (0x10000U) #define I3C_MWDATAB_END_ALSO_SHIFT (16U) /*! END_ALSO - End of Message ALSO * 0b0..Not the end * 0b1..End */ #define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) /*! @} */ /*! @name MWDATABE - Controller Write Data Byte End */ /*! @{ */ #define I3C_MWDATABE_VALUE_MASK (0xFFU) #define I3C_MWDATABE_VALUE_SHIFT (0U) /*! VALUE - Data */ #define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) /*! @} */ /*! @name MWDATAH - Controller Write Data Halfword */ /*! @{ */ #define I3C_MWDATAH_DATA0_MASK (0xFFU) #define I3C_MWDATAH_DATA0_SHIFT (0U) /*! DATA0 - Data Byte 0 */ #define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) #define I3C_MWDATAH_DATA1_MASK (0xFF00U) #define I3C_MWDATAH_DATA1_SHIFT (8U) /*! DATA1 - Data Byte 1 */ #define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) #define I3C_MWDATAH_END_MASK (0x10000U) #define I3C_MWDATAH_END_SHIFT (16U) /*! END - End of Message * 0b0..Not the end * 0b1..End */ #define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) /*! @} */ /*! @name MWDATAHE - Controller Write Data Halfword End */ /*! @{ */ #define I3C_MWDATAHE_DATA0_MASK (0xFFU) #define I3C_MWDATAHE_DATA0_SHIFT (0U) /*! DATA0 - Data Byte 0 */ #define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) #define I3C_MWDATAHE_DATA1_MASK (0xFF00U) #define I3C_MWDATAHE_DATA1_SHIFT (8U) /*! DATA1 - Data Byte 1 */ #define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) /*! @} */ /*! @name MRDATAB - Controller Read Data Byte */ /*! @{ */ #define I3C_MRDATAB_VALUE_MASK (0xFFU) #define I3C_MRDATAB_VALUE_SHIFT (0U) /*! VALUE - Value */ #define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) /*! @} */ /*! @name MRDATAH - Controller Read Data Halfword */ /*! @{ */ #define I3C_MRDATAH_LSB_MASK (0xFFU) #define I3C_MRDATAH_LSB_SHIFT (0U) /*! LSB - Low Byte */ #define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) #define I3C_MRDATAH_MSB_MASK (0xFF00U) #define I3C_MRDATAH_MSB_SHIFT (8U) /*! MSB - High Byte */ #define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) /*! @} */ /*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ /*! @{ */ #define I3C_MWDATAB1_VALUE_MASK (0xFFU) #define I3C_MWDATAB1_VALUE_SHIFT (0U) /*! VALUE - Value */ #define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) /*! @} */ /*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ /*! @{ */ #define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) #define I3C_MWDATAH1_VALUE_SHIFT (0U) /*! VALUE - Value */ #define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) /*! @} */ /*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ /*! @{ */ #define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) #define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) /*! DIR - Direction * 0b0..Write * 0b1..Read */ #define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) #define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) #define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) /*! ADDR - Address */ #define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) #define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) #define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) /*! END - End of SDR Message * 0b0..Not the end * 0b1..End */ #define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) #define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) #define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) /*! I2C - I2C * 0b0..I3C message * 0b1..I2C message */ #define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) #define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) #define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) /*! LEN - Length */ #define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) /*! @} */ /*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ /*! @{ */ #define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) #define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) /*! DATA16B - Data */ #define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) /*! @} */ /*! @name MRMSG_SDR - Controller Read Message in SDR mode */ /*! @{ */ #define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) #define I3C_MRMSG_SDR_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) /*! @} */ /*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ /*! @{ */ #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) #define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) /*! ADDRCMD - Address Command */ #define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) /*! @} */ /*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ /*! @{ */ #define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) #define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) /*! LEN - Length of Message */ #define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) #define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) #define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) /*! END - End of Message * 0b1..End * 0b0..Not the end */ #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) /*! @} */ /*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ /*! @{ */ #define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) #define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) /*! DATA16B - Data */ #define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) /*! @} */ /*! @name MRMSG_DDR - Controller Read Message in DDR mode */ /*! @{ */ #define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) #define I3C_MRMSG_DDR_DATA_SHIFT (0U) /*! DATA - Data */ #define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) /*! @} */ /*! @name MDYNADDR - Controller Dynamic Address */ /*! @{ */ #define I3C_MDYNADDR_DAVALID_MASK (0x1U) #define I3C_MDYNADDR_DAVALID_SHIFT (0U) /*! DAVALID - Dynamic Address Valid * 0b1..Valid DA assigned * 0b0..No valid DA assigned */ #define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) #define I3C_MDYNADDR_DADDR_MASK (0xFEU) #define I3C_MDYNADDR_DADDR_SHIFT (1U) /*! DADDR - Dynamic Address */ #define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) /*! @} */ /*! @name SRSTACTTIME - Timing Rules for Target Reset Recovery */ /*! @{ */ #define I3C_SRSTACTTIME_PERRSTTIM_MASK (0xFFU) #define I3C_SRSTACTTIME_PERRSTTIM_SHIFT (0U) /*! PERRSTTIM - Time to Recover from the I3C Peripheral */ #define I3C_SRSTACTTIME_PERRSTTIM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_PERRSTTIM_SHIFT)) & I3C_SRSTACTTIME_PERRSTTIM_MASK) #define I3C_SRSTACTTIME_SYSRSTTIM_MASK (0xFF00U) #define I3C_SRSTACTTIME_SYSRSTTIM_SHIFT (8U) /*! SYSRSTTIM - Time to Recover from Chip Reset */ #define I3C_SRSTACTTIME_SYSRSTTIM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRSTACTTIME_SYSRSTTIM_SHIFT)) & I3C_SRSTACTTIME_SYSRSTTIM_MASK) /*! @} */ /*! @name SCCCMASK - CCC Mask for Unhandled CCCs */ /*! @{ */ #define I3C_SCCCMASK_BASE_MASK (0x1U) #define I3C_SCCCMASK_BASE_SHIFT (0U) /*! BASE - Base * 0b0..Suppressed * 0b1..Passed to application */ #define I3C_SCCCMASK_BASE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASE_SHIFT)) & I3C_SCCCMASK_BASE_MASK) #define I3C_SCCCMASK_BASEBX_MASK (0x2U) #define I3C_SCCCMASK_BASEBX_SHIFT (1U) /*! BASEBX - BASEBX * 0b0..Suppressed * 0b1..Passed to application */ #define I3C_SCCCMASK_BASEBX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEBX_SHIFT)) & I3C_SCCCMASK_BASEBX_MASK) #define I3C_SCCCMASK_BASEDX_MASK (0x4U) #define I3C_SCCCMASK_BASEDX_SHIFT (2U) /*! BASEDX - BASEDX * 0b0..Suppressed * 0b1..Passed to application */ #define I3C_SCCCMASK_BASEDX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_BASEDX_SHIFT)) & I3C_SCCCMASK_BASEDX_MASK) #define I3C_SCCCMASK_MEXTB_MASK (0x8U) #define I3C_SCCCMASK_MEXTB_SHIFT (3U) /*! MEXTB - MEXTB * 0b0..Suppressed * 0b1..Passed to application */ #define I3C_SCCCMASK_MEXTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTB_SHIFT)) & I3C_SCCCMASK_MEXTB_MASK) #define I3C_SCCCMASK_MEXTD_MASK (0x10U) #define I3C_SCCCMASK_MEXTD_SHIFT (4U) /*! MEXTD - MEXTD * 0b0..Suppressed * 0b1..Passed to application */ #define I3C_SCCCMASK_MEXTD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_MEXTD_SHIFT)) & I3C_SCCCMASK_MEXTD_MASK) #define I3C_SCCCMASK_VENDB_MASK (0x20U) #define I3C_SCCCMASK_VENDB_SHIFT (5U) /*! VENDB - VENDB * 0b0..Suppressed * 0b1..Passed to application */ #define I3C_SCCCMASK_VENDB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDB_SHIFT)) & I3C_SCCCMASK_VENDB_MASK) #define I3C_SCCCMASK_VENDD_MASK (0x40U) #define I3C_SCCCMASK_VENDD_SHIFT (6U) /*! VENDD - VENDD * 0b0..Suppressed * 0b1..Passed to application */ #define I3C_SCCCMASK_VENDD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCCCMASK_VENDD_SHIFT)) & I3C_SCCCMASK_VENDD_MASK) /*! @} */ /*! @name SERRWARNMASK - Target Errors and Warnings Mask */ /*! @{ */ #define I3C_SERRWARNMASK_ORUN_MASK (0x1U) #define I3C_SERRWARNMASK_ORUN_SHIFT (0U) /*! ORUN - ORUN Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_ORUN_SHIFT)) & I3C_SERRWARNMASK_ORUN_MASK) #define I3C_SERRWARNMASK_URUN_MASK (0x2U) #define I3C_SERRWARNMASK_URUN_SHIFT (1U) /*! URUN - URUN Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUN_SHIFT)) & I3C_SERRWARNMASK_URUN_MASK) #define I3C_SERRWARNMASK_URUNNACK_MASK (0x4U) #define I3C_SERRWARNMASK_URUNNACK_SHIFT (2U) /*! URUNNACK - URUNNACK Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_URUNNACK_SHIFT)) & I3C_SERRWARNMASK_URUNNACK_MASK) #define I3C_SERRWARNMASK_TERM_MASK (0x8U) #define I3C_SERRWARNMASK_TERM_SHIFT (3U) /*! TERM - TERM Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_TERM_SHIFT)) & I3C_SERRWARNMASK_TERM_MASK) #define I3C_SERRWARNMASK_INVSTART_MASK (0x10U) #define I3C_SERRWARNMASK_INVSTART_SHIFT (4U) /*! INVSTART - INVSTART Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_INVSTART_SHIFT)) & I3C_SERRWARNMASK_INVSTART_MASK) #define I3C_SERRWARNMASK_SPAR_MASK (0x100U) #define I3C_SERRWARNMASK_SPAR_SHIFT (8U) /*! SPAR - SPAR Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_SPAR_SHIFT)) & I3C_SERRWARNMASK_SPAR_MASK) #define I3C_SERRWARNMASK_HPAR_MASK (0x200U) #define I3C_SERRWARNMASK_HPAR_SHIFT (9U) /*! HPAR - HPAR Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HPAR_SHIFT)) & I3C_SERRWARNMASK_HPAR_MASK) #define I3C_SERRWARNMASK_HCRC_MASK (0x400U) #define I3C_SERRWARNMASK_HCRC_SHIFT (10U) /*! HCRC - HCRC Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_HCRC_SHIFT)) & I3C_SERRWARNMASK_HCRC_MASK) #define I3C_SERRWARNMASK_S0S1_MASK (0x800U) #define I3C_SERRWARNMASK_S0S1_SHIFT (11U) /*! S0S1 - S0S1 Mask * 0b1..Allow * 0b0..Deny */ #define I3C_SERRWARNMASK_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARNMASK_S0S1_SHIFT)) & I3C_SERRWARNMASK_S0S1_MASK) /*! @} */ /*! @name SMAPCTRL0 - Map Feature Control 0 */ /*! @{ */ #define I3C_SMAPCTRL0_ENA_MASK (0x1U) #define I3C_SMAPCTRL0_ENA_SHIFT (0U) /*! ENA - Enable Primary Dynamic Address * 0b0..Disabled * 0b1..Enabled */ #define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) #define I3C_SMAPCTRL0_DA_MASK (0xFEU) #define I3C_SMAPCTRL0_DA_SHIFT (1U) /*! DA - Dynamic Address */ #define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) #define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) #define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) /*! CAUSE - Cause * 0b000..No information (this value occurs when not configured to write DA) * 0b001..Set using ENTDAA * 0b010..Set using SETDASA, SETAASA, or SETNEWDA * 0b011..Cleared using RSTDAA * 0b100..Auto MAP change happened last * *.. */ #define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) /*! @} */ /*! @name SMAPCTRL1 - Map Feature Control 1 */ /*! @{ */ #define I3C_SMAPCTRL1_ENA_MASK (0x1U) #define I3C_SMAPCTRL1_ENA_SHIFT (0U) /*! ENA - Enable * 0b0..Disable * 0b1..Enable */ #define I3C_SMAPCTRL1_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ENA_SHIFT)) & I3C_SMAPCTRL1_ENA_MASK) #define I3C_SMAPCTRL1_ADDR_MASK (0xFEU) #define I3C_SMAPCTRL1_ADDR_SHIFT (1U) /*! ADDR - Address */ #define I3C_SMAPCTRL1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ADDR_SHIFT)) & I3C_SMAPCTRL1_ADDR_MASK) #define I3C_SMAPCTRL1_MAPSA_MASK (0x100U) #define I3C_SMAPCTRL1_MAPSA_SHIFT (8U) /*! MAPSA - MAP Static Address * 0b0..I3C dynamic address * 0b1..Static address (I2C style) */ #define I3C_SMAPCTRL1_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_MAPSA_SHIFT)) & I3C_SMAPCTRL1_MAPSA_MASK) #define I3C_SMAPCTRL1_SA10B_MASK (0xE00U) #define I3C_SMAPCTRL1_SA10B_SHIFT (9U) /*! SA10B - Static Address 10-Bit Extension */ #define I3C_SMAPCTRL1_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_SA10B_SHIFT)) & I3C_SMAPCTRL1_SA10B_MASK) #define I3C_SMAPCTRL1_NACK_MASK (0x1000U) #define I3C_SMAPCTRL1_NACK_SHIFT (12U) /*! NACK - Not Acknowledged * 0b0..Do not always NACK messages * 0b1..Always NACK messages */ #define I3C_SMAPCTRL1_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_NACK_SHIFT)) & I3C_SMAPCTRL1_NACK_MASK) #define I3C_SMAPCTRL1_AUTO_MASK (0x2000U) #define I3C_SMAPCTRL1_AUTO_SHIFT (13U) /*! AUTO - Auto DAA * 0b0..Disabled * 0b1..Enabled */ #define I3C_SMAPCTRL1_AUTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_AUTO_SHIFT)) & I3C_SMAPCTRL1_AUTO_MASK) #define I3C_SMAPCTRL1_DCR_MASK (0xFF000000U) #define I3C_SMAPCTRL1_DCR_SHIFT (24U) /*! DCR - DCR */ #define I3C_SMAPCTRL1_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_DCR_SHIFT)) & I3C_SMAPCTRL1_DCR_MASK) /*! @} */ /*! @name IBIEXT1 - Extended IBI Data 1 */ /*! @{ */ #define I3C_IBIEXT1_CNT_MASK (0x7U) #define I3C_IBIEXT1_CNT_SHIFT (0U) /*! CNT - Count */ #define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) #define I3C_IBIEXT1_MAX_MASK (0x70U) #define I3C_IBIEXT1_MAX_SHIFT (4U) /*! MAX - Maximum */ #define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) #define I3C_IBIEXT1_EXT1_MASK (0xFF00U) #define I3C_IBIEXT1_EXT1_SHIFT (8U) /*! EXT1 - Extra Byte 1 */ #define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) #define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) #define I3C_IBIEXT1_EXT2_SHIFT (16U) /*! EXT2 - Extra Byte 2 */ #define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) #define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) #define I3C_IBIEXT1_EXT3_SHIFT (24U) /*! EXT3 - Extra Byte 3 */ #define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) /*! @} */ /*! @name IBIEXT2 - Extended IBI Data 2 */ /*! @{ */ #define I3C_IBIEXT2_EXT4_MASK (0xFFU) #define I3C_IBIEXT2_EXT4_SHIFT (0U) /*! EXT4 - Extra Byte 4 */ #define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) #define I3C_IBIEXT2_EXT5_MASK (0xFF00U) #define I3C_IBIEXT2_EXT5_SHIFT (8U) /*! EXT5 - Extra Byte 5 */ #define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) #define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) #define I3C_IBIEXT2_EXT6_SHIFT (16U) /*! EXT6 - Extra Byte 6 */ #define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) #define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) #define I3C_IBIEXT2_EXT7_SHIFT (24U) /*! EXT7 - Extra Byte 7 */ #define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) /*! @} */ /*! @name SELFRESET - Self Reset */ /*! @{ */ #define I3C_SELFRESET_RST_MASK (0x1U) #define I3C_SELFRESET_RST_SHIFT (0U) /*! RST - Reset * 0b0..No reset * 0b1..Reset */ #define I3C_SELFRESET_RST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_RST_SHIFT)) & I3C_SELFRESET_RST_MASK) #define I3C_SELFRESET_KEY_MASK (0xFFFFFF00U) #define I3C_SELFRESET_KEY_SHIFT (8U) /*! KEY - Key */ #define I3C_SELFRESET_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_KEY_SHIFT)) & I3C_SELFRESET_KEY_MASK) /*! @} */ /*! * @} */ /* end of group I3C_Register_Masks */ /* I3C - Peripheral instance base addresses */ /** Peripheral I3C1 base address */ #define I3C1_BASE (0x44330000u) /** Peripheral I3C1 base pointer */ #define I3C1 ((I3C_Type *)I3C1_BASE) /** Peripheral I3C2 base address */ #define I3C2_BASE (0x42520000u) /** Peripheral I3C2 base pointer */ #define I3C2 ((I3C_Type *)I3C2_BASE) /** Array initializer of I3C peripheral base addresses */ #define I3C_BASE_ADDRS { 0u, I3C1_BASE, I3C2_BASE } /** Array initializer of I3C peripheral base pointers */ #define I3C_BASE_PTRS { (I3C_Type *)0u, I3C1, I3C2 } /** Interrupt vectors for the I3C peripheral type */ #define I3C_IRQS { NotAvail_IRQn, I3C1_IRQn, I3C2_IRQn } /*! * @} */ /* end of group I3C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IDBG1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IDBG1_Peripheral_Access_Layer IDBG1 Peripheral Access Layer * @{ */ /** IDBG1 - Register Layout Typedef */ typedef struct { __IO uint32_t LINE_NUM; /**< IMA Debug Line Number Register, offset: 0x0 */ __I uint32_t CURR_LINE_NUM; /**< IMA Debug Current Line Number Register, offset: 0x4 */ __IO uint32_t IMA; /**< IMA Debug Address Register, offset: 0x8 */ __IO uint32_t IMD; /**< IMA Debug Data Register, offset: 0xC */ __I uint32_t DONE_STAT; /**< Debug Line Done Status Register, offset: 0x10 */ } IDBG1_Type; /* ---------------------------------------------------------------------------- -- IDBG1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IDBG1_Register_Masks IDBG1 Register Masks * @{ */ /*! @name LINE_NUM - IMA Debug Line Number Register */ /*! @{ */ #define IDBG1_LINE_NUM_LINE_NUM_MASK (0x1FFFFU) #define IDBG1_LINE_NUM_LINE_NUM_SHIFT (0U) #define IDBG1_LINE_NUM_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_LINE_NUM_LINE_NUM_SHIFT)) & IDBG1_LINE_NUM_LINE_NUM_MASK) /*! @} */ /*! @name CURR_LINE_NUM - IMA Debug Current Line Number Register */ /*! @{ */ #define IDBG1_CURR_LINE_NUM_CURR_LINE_NUM_MASK (0x1FFFFU) #define IDBG1_CURR_LINE_NUM_CURR_LINE_NUM_SHIFT (0U) #define IDBG1_CURR_LINE_NUM_CURR_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_CURR_LINE_NUM_CURR_LINE_NUM_SHIFT)) & IDBG1_CURR_LINE_NUM_CURR_LINE_NUM_MASK) #define IDBG1_CURR_LINE_NUM_DBG_HIT_MASK (0x80000000U) #define IDBG1_CURR_LINE_NUM_DBG_HIT_SHIFT (31U) #define IDBG1_CURR_LINE_NUM_DBG_HIT(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_CURR_LINE_NUM_DBG_HIT_SHIFT)) & IDBG1_CURR_LINE_NUM_DBG_HIT_MASK) /*! @} */ /*! @name IMA - IMA Debug Address Register */ /*! @{ */ #define IDBG1_IMA_ADDR_MASK (0xFFFU) #define IDBG1_IMA_ADDR_SHIFT (0U) #define IDBG1_IMA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_IMA_ADDR_SHIFT)) & IDBG1_IMA_ADDR_MASK) #define IDBG1_IMA_NAME_MASK (0x1F0000U) #define IDBG1_IMA_NAME_SHIFT (16U) #define IDBG1_IMA_NAME(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_IMA_NAME_SHIFT)) & IDBG1_IMA_NAME_MASK) #define IDBG1_IMA_RDWF_MASK (0x30000000U) #define IDBG1_IMA_RDWF_SHIFT (28U) /*! RDWF * 0b00..4 Reads are required before incrementing line buffer address index * 0b01..3 Reads are required before incrementing line buffer address index * 0b10..2 Reads are required before incrementing line buffer address index * 0b11..Next read will increment line buffer address index */ #define IDBG1_IMA_RDWF(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_IMA_RDWF_SHIFT)) & IDBG1_IMA_RDWF_MASK) #define IDBG1_IMA_WDWF_MASK (0xC0000000U) #define IDBG1_IMA_WDWF_SHIFT (30U) /*! WDWF * 0b00..4 Writes are required before incrementing line buffer address index * 0b01..3 Writes are required before incrementing line buffer address index * 0b10..2 Writes are required before incrementing line buffer address index * 0b11..Next write will increment line buffer address index */ #define IDBG1_IMA_WDWF(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_IMA_WDWF_SHIFT)) & IDBG1_IMA_WDWF_MASK) /*! @} */ /*! @name IMD - IMA Debug Data Register */ /*! @{ */ #define IDBG1_IMD_DATA_MASK (0xFFFFFFFFU) #define IDBG1_IMD_DATA_SHIFT (0U) #define IDBG1_IMD_DATA(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_IMD_DATA_SHIFT)) & IDBG1_IMD_DATA_MASK) /*! @} */ /*! @name DONE_STAT - Debug Line Done Status Register */ /*! @{ */ #define IDBG1_DONE_STAT_VIG_MASK (0x1U) #define IDBG1_DONE_STAT_VIG_SHIFT (0U) #define IDBG1_DONE_STAT_VIG(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_VIG_SHIFT)) & IDBG1_DONE_STAT_VIG_MASK) #define IDBG1_DONE_STAT_IRCOMP_MASK (0x2U) #define IDBG1_DONE_STAT_IRCOMP_SHIFT (1U) #define IDBG1_DONE_STAT_IRCOMP(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_IRCOMP_SHIFT)) & IDBG1_DONE_STAT_IRCOMP_MASK) #define IDBG1_DONE_STAT_HDRMERGE_MASK (0x4U) #define IDBG1_DONE_STAT_HDRMERGE_SHIFT (2U) #define IDBG1_DONE_STAT_HDRMERGE(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_HDRMERGE_SHIFT)) & IDBG1_DONE_STAT_HDRMERGE_MASK) #define IDBG1_DONE_STAT_BNR0_MASK (0x8U) #define IDBG1_DONE_STAT_BNR0_SHIFT (3U) #define IDBG1_DONE_STAT_BNR0(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_BNR0_SHIFT)) & IDBG1_DONE_STAT_BNR0_MASK) #define IDBG1_DONE_STAT_STAT_MASK (0x10U) #define IDBG1_DONE_STAT_STAT_SHIFT (4U) #define IDBG1_DONE_STAT_STAT(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_STAT_SHIFT)) & IDBG1_DONE_STAT_STAT_MASK) #define IDBG1_DONE_STAT_CTEMP_MASK (0x20U) #define IDBG1_DONE_STAT_CTEMP_SHIFT (5U) #define IDBG1_DONE_STAT_CTEMP(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_CTEMP_SHIFT)) & IDBG1_DONE_STAT_CTEMP_MASK) #define IDBG1_DONE_STAT_OB_WB2_MASK (0x40U) #define IDBG1_DONE_STAT_OB_WB2_SHIFT (6U) #define IDBG1_DONE_STAT_OB_WB2(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_OB_WB2_SHIFT)) & IDBG1_DONE_STAT_OB_WB2_MASK) #define IDBG1_DONE_STAT_OBWB1_MASK (0x80U) #define IDBG1_DONE_STAT_OBWB1_SHIFT (7U) #define IDBG1_DONE_STAT_OBWB1(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_OBWB1_SHIFT)) & IDBG1_DONE_STAT_OBWB1_MASK) #define IDBG1_DONE_STAT_OBWB0_MASK (0x100U) #define IDBG1_DONE_STAT_OBWB0_SHIFT (8U) #define IDBG1_DONE_STAT_OBWB0(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_OBWB0_SHIFT)) & IDBG1_DONE_STAT_OBWB0_MASK) #define IDBG1_DONE_STAT_HDRDECOMP1_MASK (0x200U) #define IDBG1_DONE_STAT_HDRDECOMP1_SHIFT (9U) #define IDBG1_DONE_STAT_HDRDECOMP1(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_HDRDECOMP1_SHIFT)) & IDBG1_DONE_STAT_HDRDECOMP1_MASK) #define IDBG1_DONE_STAT_HDRDECOMP0_MASK (0x400U) #define IDBG1_DONE_STAT_HDRDECOMP0_SHIFT (10U) #define IDBG1_DONE_STAT_HDRDECOMP0(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_HDRDECOMP0_SHIFT)) & IDBG1_DONE_STAT_HDRDECOMP0_MASK) #define IDBG1_DONE_STAT_HC_MASK (0x800U) #define IDBG1_DONE_STAT_HC_SHIFT (11U) #define IDBG1_DONE_STAT_HC(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_HC_SHIFT)) & IDBG1_DONE_STAT_HC_MASK) #define IDBG1_DONE_STAT_RGBIR_MASK (0x1000U) #define IDBG1_DONE_STAT_RGBIR_SHIFT (12U) #define IDBG1_DONE_STAT_RGBIR(x) (((uint32_t)(((uint32_t)(x)) << IDBG1_DONE_STAT_RGBIR_SHIFT)) & IDBG1_DONE_STAT_RGBIR_MASK) /*! @} */ /*! * @} */ /* end of group IDBG1_Register_Masks */ /* IDBG1 - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__IDBG1 base address */ #define CAMERA__ISP__IDBG1_BASE (0x4AE00FC0u) /** Peripheral CAMERA__ISP__IDBG1 base pointer */ #define CAMERA__ISP__IDBG1 ((IDBG1_Type *)CAMERA__ISP__IDBG1_BASE) /** Array initializer of IDBG1 peripheral base addresses */ #define IDBG1_BASE_ADDRS { CAMERA__ISP__IDBG1_BASE } /** Array initializer of IDBG1 peripheral base pointers */ #define IDBG1_BASE_PTRS { CAMERA__ISP__IDBG1 } /*! * @} */ /* end of group IDBG1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IDBG2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IDBG2_Peripheral_Access_Layer IDBG2 Peripheral Access Layer * @{ */ /** IDBG2 - Register Layout Typedef */ typedef struct { __IO uint32_t LINE_NUM; /**< IMA Debug Line Number Register, offset: 0x0 */ __I uint32_t CURR_LINE_NUM; /**< IMA Debug Current Line Number Register, offset: 0x4 */ __IO uint32_t IMA; /**< IMA Debug Address Register, offset: 0x8 */ __IO uint32_t IMD; /**< IMA Debug Data Register, offset: 0xC */ __I uint32_t DONE_STAT; /**< Debug Line Done Status Register, offset: 0x10 */ } IDBG2_Type; /* ---------------------------------------------------------------------------- -- IDBG2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IDBG2_Register_Masks IDBG2 Register Masks * @{ */ /*! @name LINE_NUM - IMA Debug Line Number Register */ /*! @{ */ #define IDBG2_LINE_NUM_LINE_NUM_MASK (0x1FFFFU) #define IDBG2_LINE_NUM_LINE_NUM_SHIFT (0U) #define IDBG2_LINE_NUM_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_LINE_NUM_LINE_NUM_SHIFT)) & IDBG2_LINE_NUM_LINE_NUM_MASK) /*! @} */ /*! @name CURR_LINE_NUM - IMA Debug Current Line Number Register */ /*! @{ */ #define IDBG2_CURR_LINE_NUM_CURR_LINE_NUM_MASK (0x1FFFFU) #define IDBG2_CURR_LINE_NUM_CURR_LINE_NUM_SHIFT (0U) #define IDBG2_CURR_LINE_NUM_CURR_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_CURR_LINE_NUM_CURR_LINE_NUM_SHIFT)) & IDBG2_CURR_LINE_NUM_CURR_LINE_NUM_MASK) #define IDBG2_CURR_LINE_NUM_DBG_HIT_MASK (0x80000000U) #define IDBG2_CURR_LINE_NUM_DBG_HIT_SHIFT (31U) #define IDBG2_CURR_LINE_NUM_DBG_HIT(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_CURR_LINE_NUM_DBG_HIT_SHIFT)) & IDBG2_CURR_LINE_NUM_DBG_HIT_MASK) /*! @} */ /*! @name IMA - IMA Debug Address Register */ /*! @{ */ #define IDBG2_IMA_ADDR_MASK (0xFFFU) #define IDBG2_IMA_ADDR_SHIFT (0U) #define IDBG2_IMA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_IMA_ADDR_SHIFT)) & IDBG2_IMA_ADDR_MASK) #define IDBG2_IMA_NAME_MASK (0x3F0000U) #define IDBG2_IMA_NAME_SHIFT (16U) #define IDBG2_IMA_NAME(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_IMA_NAME_SHIFT)) & IDBG2_IMA_NAME_MASK) #define IDBG2_IMA_RDWF_MASK (0x30000000U) #define IDBG2_IMA_RDWF_SHIFT (28U) /*! RDWF * 0b00..4 Reads are required before incrementing line buffer address index * 0b01..3 Reads are required before incrementing line buffer address index * 0b10..2 Reads are required before incrementing line buffer address index * 0b11..Next read will increment line buffer address index */ #define IDBG2_IMA_RDWF(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_IMA_RDWF_SHIFT)) & IDBG2_IMA_RDWF_MASK) #define IDBG2_IMA_WDWF_MASK (0xC0000000U) #define IDBG2_IMA_WDWF_SHIFT (30U) /*! WDWF * 0b00..4 Writes are required before incrementing line buffer address index * 0b01..3 Writes are required before incrementing line buffer address index * 0b10..2 Writes are required before incrementing line buffer address index * 0b11..Next write will increment line buffer address index */ #define IDBG2_IMA_WDWF(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_IMA_WDWF_SHIFT)) & IDBG2_IMA_WDWF_MASK) /*! @} */ /*! @name IMD - IMA Debug Data Register */ /*! @{ */ #define IDBG2_IMD_DATA_MASK (0xFFFFFFFFU) #define IDBG2_IMD_DATA_SHIFT (0U) #define IDBG2_IMD_DATA(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_IMD_DATA_SHIFT)) & IDBG2_IMD_DATA_MASK) /*! @} */ /*! @name DONE_STAT - Debug Line Done Status Register */ /*! @{ */ #define IDBG2_DONE_STAT_AF_MASK (0x1U) #define IDBG2_DONE_STAT_AF_SHIFT (0U) #define IDBG2_DONE_STAT_AF(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_AF_SHIFT)) & IDBG2_DONE_STAT_AF_MASK) #define IDBG2_DONE_STAT_GCM_MASK (0x2U) #define IDBG2_DONE_STAT_GCM_SHIFT (1U) #define IDBG2_DONE_STAT_GCM(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_GCM_SHIFT)) & IDBG2_DONE_STAT_GCM_MASK) #define IDBG2_DONE_STAT_CAS_MASK (0x4U) #define IDBG2_DONE_STAT_CAS_SHIFT (2U) #define IDBG2_DONE_STAT_CAS(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_CAS_SHIFT)) & IDBG2_DONE_STAT_CAS_MASK) #define IDBG2_DONE_STAT_CCONVMED_MASK (0x8U) #define IDBG2_DONE_STAT_CCONVMED_SHIFT (3U) #define IDBG2_DONE_STAT_CCONVMED(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_CCONVMED_SHIFT)) & IDBG2_DONE_STAT_CCONVMED_MASK) #define IDBG2_DONE_STAT_EE_MASK (0x10U) #define IDBG2_DONE_STAT_EE_SHIFT (4U) #define IDBG2_DONE_STAT_EE(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_EE_SHIFT)) & IDBG2_DONE_STAT_EE_MASK) #define IDBG2_DONE_STAT_DF_MASK (0x20U) #define IDBG2_DONE_STAT_DF_SHIFT (5U) #define IDBG2_DONE_STAT_DF(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_DF_SHIFT)) & IDBG2_DONE_STAT_DF_MASK) #define IDBG2_DONE_STAT_DMAP_MASK (0x40U) #define IDBG2_DONE_STAT_DMAP_SHIFT (6U) #define IDBG2_DONE_STAT_DMAP(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_DMAP_SHIFT)) & IDBG2_DONE_STAT_DMAP_MASK) #define IDBG2_DONE_STAT_NR_MASK (0x80U) #define IDBG2_DONE_STAT_NR_SHIFT (7U) #define IDBG2_DONE_STAT_NR(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_NR_SHIFT)) & IDBG2_DONE_STAT_NR_MASK) #define IDBG2_DONE_STAT_DEMOSAIC_MASK (0x100U) #define IDBG2_DONE_STAT_DEMOSAIC_SHIFT (8U) #define IDBG2_DONE_STAT_DEMOSAIC(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_DEMOSAIC_SHIFT)) & IDBG2_DONE_STAT_DEMOSAIC_MASK) #define IDBG2_DONE_STAT_CSC_MASK (0x200U) #define IDBG2_DONE_STAT_CSC_SHIFT (9U) #define IDBG2_DONE_STAT_CSC(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_CSC_SHIFT)) & IDBG2_DONE_STAT_CSC_MASK) #define IDBG2_DONE_STAT_DRC_MASK (0x400U) #define IDBG2_DONE_STAT_DRC_SHIFT (10U) #define IDBG2_DONE_STAT_DRC(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_DRC_SHIFT)) & IDBG2_DONE_STAT_DRC_MASK) #define IDBG2_DONE_STAT_PKT_MASK (0x800U) #define IDBG2_DONE_STAT_PKT_SHIFT (11U) #define IDBG2_DONE_STAT_PKT(x) (((uint32_t)(((uint32_t)(x)) << IDBG2_DONE_STAT_PKT_SHIFT)) & IDBG2_DONE_STAT_PKT_MASK) /*! @} */ /*! * @} */ /* end of group IDBG2_Register_Masks */ /* IDBG2 - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__IDBG2 base address */ #define CAMERA__ISP__IDBG2_BASE (0x4AE01FC0u) /** Peripheral CAMERA__ISP__IDBG2 base pointer */ #define CAMERA__ISP__IDBG2 ((IDBG2_Type *)CAMERA__ISP__IDBG2_BASE) /** Array initializer of IDBG2 peripheral base addresses */ #define IDBG2_BASE_ADDRS { CAMERA__ISP__IDBG2_BASE } /** Array initializer of IDBG2 peripheral base pointers */ #define IDBG2_BASE_PTRS { CAMERA__ISP__IDBG2 } /*! * @} */ /* end of group IDBG2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer * @{ */ /** IOMUXC - Register Layout Typedef */ typedef struct { __IO uint32_t SW_MUX_CTL_PAD[128]; /**< SW_MUX_CTL_PAD_DAP_TDI SW MUX Control Register..SW_MUX_CTL_PAD_WDOG_ANY SW MUX Control Register, array offset: 0x0, array step: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t SW_PAD_CTL_PAD[128]; /**< SW_PAD_CTL_PAD_DAP_TDI SW PAD Control Register..SW_PAD_CTL_PAD_WDOG_ANY SW PAD Control Register, array offset: 0x204, array step: 0x4 */ __IO uint32_t SW_PAD_CTL_PAD_FCCU_ERR0; /**< SW_PAD_CTL_PAD_FCCU_ERR0 SW PAD Control Register, offset: 0x404 */ __IO uint32_t SELECT_INPUT[132]; /**< CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..JTAG_MUX_TMS_SELECT_INPUT DAISY Register, array offset: 0x408, array step: 0x4 */ } IOMUXC_Type; /* ---------------------------------------------------------------------------- -- IOMUXC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks * @{ */ /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_DAP_TDI SW MUX Control Register..SW_MUX_CTL_PAD_WDOG_ANY SW MUX Control Register */ /*! @{ */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. * 0b000..Select mux mode: ALT0 mux port: GPIO2_IO19 of instance: imx95_wakeupmix_top * 0b001..Select mux mode: ALT1 mux port: SAI3_RX_SYNC of instance: imx95_wakeupmix_top * 0b010..Select mux mode: ALT2 mux port: PDM_BIT_STREAM03 of instance: imx95_aonmix_top * 0b011..Select mux mode: ALT3 mux port: FLEXIO1_FLEXIO19 of instance: imx95_wakeupmix_top * 0b100..Select mux mode: ALT4 mux port: LPSPI5_SIN of instance: imx95_wakeupmix_top * 0b101..Select mux mode: ALT5 mux port: LPSPI4_SIN of instance: imx95_wakeupmix_top * 0b110..Select mux mode: ALT6 mux port: TPM6_CH2 of instance: imx95_wakeupmix_top * 0b111..Select mux mode: ALT7 mux port: SAI3_TX_DATA00 of instance: imx95_wakeupmix_top */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION - Software Input On Field. * 0b1..Force input path of pad DAP_TDO_TRACESWO * 0b0..Input Path is determined by functionality */ #define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) /*! @} */ /* The count of IOMUXC_SW_MUX_CTL_PAD */ #define IOMUXC_SW_MUX_CTL_PAD_COUNT (128U) /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_DAP_TDI SW PAD Control Register..SW_PAD_CTL_PAD_WDOG_ANY SW PAD Control Register */ /*! @{ */ #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x7EU) #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (1U) /*! DSE - Drive Strength Field * 0b000000..No drive * 0b000001..x1 * 0b000011..x2 * 0b000111..x3 * 0b001111..x4 * 0b011111..x5 * 0b111111..X6 */ #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FSEL1_MASK (0x180U) #define IOMUXC_SW_PAD_CTL_PAD_FSEL1_SHIFT (7U) /*! FSEL1 - Slew Rate Field * 0b00.. * 0b01.. * 0b10..Slight Fast Slew Rate * 0b11..Fast Slew Rate */ #define IOMUXC_SW_PAD_CTL_PAD_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FSEL1_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FSEL1_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PU_MASK (0x200U) #define IOMUXC_SW_PAD_CTL_PAD_PU_SHIFT (9U) /*! PU - Pull Up Field * 0b0..No pull up * 0b1..Pull up */ #define IOMUXC_SW_PAD_CTL_PAD_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PU_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PU_MASK) #define IOMUXC_SW_PAD_CTL_PAD_PD_MASK (0x400U) #define IOMUXC_SW_PAD_CTL_PAD_PD_SHIFT (10U) /*! PD - Pull Down Field * 0b0..Not pull down * 0b1..Pull down */ #define IOMUXC_SW_PAD_CTL_PAD_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PD_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PD_MASK) #define IOMUXC_SW_PAD_CTL_PAD_OD_MASK (0x800U) #define IOMUXC_SW_PAD_CTL_PAD_OD_SHIFT (11U) /*! OD - Open Drain Field * 0b0..Open Drain Disable * 0b1..Open Drain Enable */ #define IOMUXC_SW_PAD_CTL_PAD_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_OD_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_OD_MASK) #define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x1000U) #define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (12U) /*! HYS - Schmitt trigger Field * 0b0..No Schmitt input * 0b1..Schmitt input */ #define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) #define IOMUXC_SW_PAD_CTL_PAD_SMC_MASK (0xE000U) #define IOMUXC_SW_PAD_CTL_PAD_SMC_SHIFT (13U) /*! SMC - Safe Mode Control * 0b000..Disabled on all four application domains * 0b001..Enabled safe stating for application domain 1 * 0b010..Enabled safe stating for application domain 2 * 0b011..Enabled safe stating for application domain 1 and application domain 2 * 0b100..Enabled safe stating for application domain 3 * 0b101..Enabled safe stating for application domain 1 and application domain 3 * 0b110..Enabled safe stating for application domain 2 and application domain 3 * 0b111..Enabled safe stating for all application domains */ #define IOMUXC_SW_PAD_CTL_PAD_SMC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SMC_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SMC_MASK) #define IOMUXC_SW_PAD_CTL_PAD_APC_MASK (0xF000000U) #define IOMUXC_SW_PAD_CTL_PAD_APC_SHIFT (24U) /*! APC - Domain Access Field */ #define IOMUXC_SW_PAD_CTL_PAD_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_APC_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_APC_MASK) #define IOMUXC_SW_PAD_CTL_PAD_APC_LCK_MASK (0xF0000000U) #define IOMUXC_SW_PAD_CTL_PAD_APC_LCK_SHIFT (28U) /*! APC_LCK - APC lock bits */ #define IOMUXC_SW_PAD_CTL_PAD_APC_LCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_APC_LCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_APC_LCK_MASK) /*! @} */ /* The count of IOMUXC_SW_PAD_CTL_PAD */ #define IOMUXC_SW_PAD_CTL_PAD_COUNT (128U) /*! @name SW_PAD_CTL_PAD_FCCU_ERR0 - SW_PAD_CTL_PAD_FCCU_ERR0 SW PAD Control Register */ /*! @{ */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_DSE_MASK (0x7EU) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_DSE_SHIFT (1U) /*! DSE - Drive Strength Field * 0b000000..No drive * 0b000001..x1 * 0b000011..x2 * 0b000111..x3 * 0b001111..x4 * 0b011111..x5 * 0b111111..X6 */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_DSE_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_FSEL1_MASK (0x180U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_FSEL1_SHIFT (7U) /*! FSEL1 - Slew Rate Field * 0b00.. * 0b01.. * 0b10..Slight Fast Slew Rate * 0b11..Fast Slew Rate */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_FSEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_FSEL1_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_FSEL1_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PU_MASK (0x200U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PU_SHIFT (9U) /*! PU - Pull Up Field * 0b0..No pull up * 0b1..Pull up */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PU(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PU_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PU_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PD_MASK (0x400U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PD_SHIFT (10U) /*! PD - Pull Down Field * 0b0..Not pull down * 0b1..Pull down */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PD_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_PD_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_OD_MASK (0x800U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_OD_SHIFT (11U) /*! OD - Open Drain Field * 0b0..Open Drain Disable * 0b1..Open Drain Enable */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_OD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_OD_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_OD_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_HYS_MASK (0x1000U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_HYS_SHIFT (12U) /*! HYS - Schmitt trigger Field * 0b0..No Schmitt input * 0b1..Schmitt input */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_HYS_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_SMC_MASK (0xE000U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_SMC_SHIFT (13U) /*! SMC - Safe Mode Control * 0b000..Disabled on all four application domains * 0b001..Enabled safe stating for application domain 1 * 0b010..Enabled safe stating for application domain 2 * 0b011..Enabled safe stating for application domain 1 and application domain 2 * 0b100..Enabled safe stating for application domain 3 * 0b101..Enabled safe stating for application domain 1 and application domain 3 * 0b110..Enabled safe stating for application domain 2 and application domain 3 * 0b111..Enabled safe stating for all application domains */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_SMC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_SMC_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_SMC_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_MASK (0xF000000U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_SHIFT (24U) /*! APC - Domain Access Field */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_MASK) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_LCK_MASK (0xF0000000U) #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_LCK_SHIFT (28U) /*! APC_LCK - APC lock bits */ #define IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_LCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_LCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FCCU_ERR0_APC_LCK_MASK) /*! @} */ /*! @name SELECT_INPUT - CAN1_IPP_IND_CANRX_SELECT_INPUT DAISY Register..JTAG_MUX_TMS_SELECT_INPUT DAISY Register */ /*! @{ */ #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) /*! DAISY - Selecting Pads Involved in Daisy Chain. * 0b00..Selecting Pad: DAP_TDO_TRACESWO for Mode: ALT3 * 0b01..Selecting Pad: ENET1_TD2 for Mode: ALT2 * 0b10..Selecting Pad: GPIO_IO27 for Mode: ALT2 * 0b11..Selecting Pad: SD2_DATA1 for Mode: ALT2 */ #define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ /*! @} */ /* The count of IOMUXC_SELECT_INPUT */ #define IOMUXC_SELECT_INPUT_COUNT (132U) /*! * @} */ /* end of group IOMUXC_Register_Masks */ /* IOMUXC - Peripheral instance base addresses */ /** Peripheral IOMUXC base address */ #define IOMUXC_BASE (0x443C0000u) /** Peripheral IOMUXC base pointer */ #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) /** Array initializer of IOMUXC peripheral base addresses */ #define IOMUXC_BASE_ADDRS { IOMUXC_BASE } /** Array initializer of IOMUXC peripheral base pointers */ #define IOMUXC_BASE_PTRS { IOMUXC } /*! * @} */ /* end of group IOMUXC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer * @{ */ /** IOMUXC_GPR - Register Layout Typedef */ typedef struct { __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ } IOMUXC_GPR_Type; /* ---------------------------------------------------------------------------- -- IOMUXC_GPR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks * @{ */ /*! @name GPR0 - GPR0 General Purpose Register */ /*! @{ */ #define IOMUXC_GPR_GPR0_GPR_MASK (0xFFFFU) #define IOMUXC_GPR_GPR0_GPR_SHIFT (0U) /*! GPR - General purpose bits */ #define IOMUXC_GPR_GPR0_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_GPR_SHIFT)) & IOMUXC_GPR_GPR0_GPR_MASK) #define IOMUXC_GPR_GPR0_GPR_LCK_MASK (0xFFFF0000U) #define IOMUXC_GPR_GPR0_GPR_LCK_SHIFT (16U) /*! GPR_LCK - GPR lock bits */ #define IOMUXC_GPR_GPR0_GPR_LCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_GPR_LCK_SHIFT)) & IOMUXC_GPR_GPR0_GPR_LCK_MASK) /*! @} */ /*! * @} */ /* end of group IOMUXC_GPR_Register_Masks */ /* IOMUXC_GPR - Peripheral instance base addresses */ /** Peripheral AON__IOMUXC0__IOMUXC_GPR base address */ #define AON__IOMUXC0__IOMUXC_GPR_BASE (0x443D0000u) /** Peripheral AON__IOMUXC0__IOMUXC_GPR base pointer */ #define AON__IOMUXC0__IOMUXC_GPR ((IOMUXC_GPR_Type *)AON__IOMUXC0__IOMUXC_GPR_BASE) /** Array initializer of IOMUXC_GPR peripheral base addresses */ #define IOMUXC_GPR_BASE_ADDRS { AON__IOMUXC0__IOMUXC_GPR_BASE } /** Array initializer of IOMUXC_GPR peripheral base pointers */ #define IOMUXC_GPR_BASE_PTRS { AON__IOMUXC0__IOMUXC_GPR } /*! * @} */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IRQSTEER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IRQSTEER_Peripheral_Access_Layer IRQSTEER Peripheral Access Layer * @{ */ /** IRQSTEER - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t CHn_MASK[20]; /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */ __IO uint32_t CHn_SET[20]; /**< Channel n Interrupt Set Register, array offset: 0x54, array step: 0x4 */ __I uint32_t CHn_STATUS[20]; /**< Channel n Interrupt Status Register, array offset: 0xA4, array step: 0x4 */ __IO uint32_t CHn_MINTDIS; /**< Channel n Master Interrupt Disable Register., offset: 0xF4 */ __I uint32_t CHn_MSTRSTAT; /**< Channel n Master Status Register, offset: 0xF8 */ } IRQSTEER_Type; /* ---------------------------------------------------------------------------- -- IRQSTEER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IRQSTEER_Register_Masks IRQSTEER Register Masks * @{ */ /*! @name CHn_MASK - Channel n Interrupt Mask Register */ /*! @{ */ #define IRQSTEER_CHn_MASK_MASKFLD_MASK (0xFFFFFFFFU) #define IRQSTEER_CHn_MASK_MASKFLD_SHIFT (0U) /*! MASKFLD - Mask bits * 0b00000000000000000000000000000000..Mask interrupt * 0b00000000000000000000000000000001..Do not mask interrupt */ #define IRQSTEER_CHn_MASK_MASKFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MASK_MASKFLD_SHIFT)) & IRQSTEER_CHn_MASK_MASKFLD_MASK) /*! @} */ /* The count of IRQSTEER_CHn_MASK */ #define IRQSTEER_CHn_MASK_COUNT (20U) /*! @name CHn_SET - Channel n Interrupt Set Register */ /*! @{ */ #define IRQSTEER_CHn_SET_FORCEFLD_MASK (0xFFFFFFFFU) #define IRQSTEER_CHn_SET_FORCEFLD_SHIFT (0U) /*! FORCEFLD - Force interrupt. * 0b00000000000000000000000000000000..Normal operation * 0b00000000000000000000000000000001..Force interrupt */ #define IRQSTEER_CHn_SET_FORCEFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_SET_FORCEFLD_SHIFT)) & IRQSTEER_CHn_SET_FORCEFLD_MASK) /*! @} */ /* The count of IRQSTEER_CHn_SET */ #define IRQSTEER_CHn_SET_COUNT (20U) /*! @name CHn_STATUS - Channel n Interrupt Status Register */ /*! @{ */ #define IRQSTEER_CHn_STATUS_STATUS_MASK (0xFFFFFFFFU) #define IRQSTEER_CHn_STATUS_STATUS_SHIFT (0U) /*! STATUS - Status of an interrupt * 0b00000000000000000000000000000000..Interrupt is not set. * 0b00000000000000000000000000000001..Interrupt is set. */ #define IRQSTEER_CHn_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_STATUS_STATUS_SHIFT)) & IRQSTEER_CHn_STATUS_STATUS_MASK) /*! @} */ /* The count of IRQSTEER_CHn_STATUS */ #define IRQSTEER_CHn_STATUS_COUNT (20U) /*! @name CHn_MINTDIS - Channel n Master Interrupt Disable Register. */ /*! @{ */ #define IRQSTEER_CHn_MINTDIS_DISABLE_MASK (0x3FFU) #define IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT (0U) /*! DISABLE - Each bit of this field disables the corresponding interrupts in table above. * 0b0000000000..Enable interrupts * 0b0000000001..Disable interrupts */ #define IRQSTEER_CHn_MINTDIS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MINTDIS_DISABLE_SHIFT)) & IRQSTEER_CHn_MINTDIS_DISABLE_MASK) /*! @} */ /*! @name CHn_MSTRSTAT - Channel n Master Status Register */ /*! @{ */ #define IRQSTEER_CHn_MSTRSTAT_STATUS_MASK (0x1U) #define IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT (0U) /*! STATUS - Status of all interrupts * 0b0..No interrupts are asserted. * 0b1..At least one interrupt is asserted. */ #define IRQSTEER_CHn_MSTRSTAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHn_MSTRSTAT_STATUS_SHIFT)) & IRQSTEER_CHn_MSTRSTAT_STATUS_MASK) /*! @} */ /*! * @} */ /* end of group IRQSTEER_Register_Masks */ /* IRQSTEER - Peripheral instance base addresses */ /** Peripheral IRQSTEER base address */ #define IRQSTEER_BASE (0x44680000u) /** Peripheral IRQSTEER base pointer */ #define IRQSTEER ((IRQSTEER_Type *)IRQSTEER_BASE) /** Array initializer of IRQSTEER peripheral base addresses */ #define IRQSTEER_BASE_ADDRS { IRQSTEER_BASE } /** Array initializer of IRQSTEER peripheral base pointers */ #define IRQSTEER_BASE_PTRS { IRQSTEER } /* Backward compatibility */ #define IRQSTEER_IRQS { IRQSTEER_0_IRQn, IRQSTEER_1_IRQn, IRQSTEER_2_IRQn, IRQSTEER_3_IRQn, IRQSTEER_4_IRQn, IRQSTEER_5_IRQn, IRQSTEER_6_IRQn, IRQSTEER_7_IRQn, IRQSTEER_8_IRQn, IRQSTEER_9_IRQn} /*! * @} */ /* end of group IRQSTEER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- IR_COMPRESS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup IR_COMPRESS_Peripheral_Access_Layer IR_COMPRESS Peripheral Access Layer * @{ */ /** IR_COMPRESS - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x48 */ __IO uint32_t CTRL_CAM; /**< Camera 0 IR Compress Control Register, array offset: 0x0, array step: 0x48 */ __IO uint32_t KNEE_POINT1_CAM; /**< Camera 0 IR Compress KneePoint 1 Register, array offset: 0x4, array step: 0x48 */ __IO uint32_t KNEE_POINT2_CAM; /**< Camera 0 IR Compress KneePoint 2 Register, array offset: 0x8, array step: 0x48 */ __IO uint32_t KNEE_POINT3_CAM; /**< Camera 0 IR Compress KneePoint 3 Register, array offset: 0xC, array step: 0x48 */ __IO uint32_t KNEE_POINT4_CAM; /**< Camera 0 IR Compress KneePoint 4 Register, array offset: 0x10, array step: 0x48 */ __IO uint32_t KNEE_OFFSET0_CAM; /**< Camera 0 IR Compress Knee Offset 0 Register, array offset: 0x14, array step: 0x48 */ __IO uint32_t KNEE_OFFSET1_CAM; /**< Camera 0 IR Compress Knee Offset 1 Register, array offset: 0x18, array step: 0x48 */ __IO uint32_t KNEE_OFFSET2_CAM; /**< Camera 0 IR Compress Knee Offset 2 Register, array offset: 0x1C, array step: 0x48 */ __IO uint32_t KNEE_OFFSET3_CAM; /**< Camera 0 IR Compress Knee Offset 3 Register, array offset: 0x20, array step: 0x48 */ __IO uint32_t KNEE_OFFSET4_CAM; /**< Camera 0 IR Compress Knee Offset 4 Register, array offset: 0x24, array step: 0x48 */ __IO uint32_t KNEE_RATIO01_CAM; /**< Camera 0 IR Compress Knee Ratio 01 Register, array offset: 0x28, array step: 0x48 */ __IO uint32_t KNEE_RATIO23_CAM; /**< Camera 0 IR Compress Knee Ratio 23 Register, array offset: 0x2C, array step: 0x48 */ __IO uint32_t KNEE_RATIO4_CAM; /**< Camera 0 IR Compress Knee Ratio 4 Register, array offset: 0x30, array step: 0x48 */ __IO uint32_t KNEE_NPOINT0_CAM; /**< Camera 0 IR Compress New KneePoint 0 Register, array offset: 0x34, array step: 0x48 */ __IO uint32_t KNEE_NPOINT1_CAM; /**< Camera 0 IR Compress New KneePoint 1 Register, array offset: 0x38, array step: 0x48 */ __IO uint32_t KNEE_NPOINT2_CAM; /**< Camera 0 IR Compress New KneePoint 2 Register, array offset: 0x3C, array step: 0x48 */ __IO uint32_t KNEE_NPOINT3_CAM; /**< Camera 0 IR Compress New KneePoint 3 Register, array offset: 0x40, array step: 0x48 */ __IO uint32_t KNEE_NPOINT4_CAM; /**< Camera 0 IR Compress New KneePoint 4 Register, array offset: 0x44, array step: 0x48 */ } NEO_PIPE1_IR_COMP_CONF[1]; } IR_COMPRESS_Type; /* ---------------------------------------------------------------------------- -- IR_COMPRESS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup IR_COMPRESS_Register_Masks IR_COMPRESS Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 IR Compress Control Register */ /*! @{ */ #define IR_COMPRESS_CTRL_CAM_OBPP_MASK (0x1U) #define IR_COMPRESS_CTRL_CAM_OBPP_SHIFT (0U) /*! OBPP * 0b0..8bpp output * 0b1..16bpp output */ #define IR_COMPRESS_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_CTRL_CAM_OBPP_SHIFT)) & IR_COMPRESS_CTRL_CAM_OBPP_MASK) #define IR_COMPRESS_CTRL_CAM_ENABLE_MASK (0x80000000U) #define IR_COMPRESS_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..IR compression operation is disabled, and the corresponding pipeline 1 output is not written to memory. * 0b1..IR compression operation is enabled. */ #define IR_COMPRESS_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_CTRL_CAM_ENABLE_SHIFT)) & IR_COMPRESS_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of IR_COMPRESS_CTRL_CAM */ #define IR_COMPRESS_CTRL_CAM_COUNT (1U) /*! @name KNEE_POINT1_CAM - Camera 0 IR Compress KneePoint 1 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_POINT1_CAM_KNEEPOINT_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_POINT1_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_POINT1_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_POINT1_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_POINT1_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_POINT1_CAM */ #define IR_COMPRESS_KNEE_POINT1_CAM_COUNT (1U) /*! @name KNEE_POINT2_CAM - Camera 0 IR Compress KneePoint 2 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_POINT2_CAM_KNEEPOINT_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_POINT2_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_POINT2_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_POINT2_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_POINT2_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_POINT2_CAM */ #define IR_COMPRESS_KNEE_POINT2_CAM_COUNT (1U) /*! @name KNEE_POINT3_CAM - Camera 0 IR Compress KneePoint 3 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_POINT3_CAM_KNEEPOINT_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_POINT3_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_POINT3_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_POINT3_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_POINT3_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_POINT3_CAM */ #define IR_COMPRESS_KNEE_POINT3_CAM_COUNT (1U) /*! @name KNEE_POINT4_CAM - Camera 0 IR Compress KneePoint 4 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_POINT4_CAM_KNEEPOINT_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_POINT4_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_POINT4_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_POINT4_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_POINT4_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_POINT4_CAM */ #define IR_COMPRESS_KNEE_POINT4_CAM_COUNT (1U) /*! @name KNEE_OFFSET0_CAM - Camera 0 IR Compress Knee Offset 0 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_OFFSET0_CAM_OFFSET_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_OFFSET0_CAM_OFFSET_SHIFT (0U) #define IR_COMPRESS_KNEE_OFFSET0_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_OFFSET0_CAM_OFFSET_SHIFT)) & IR_COMPRESS_KNEE_OFFSET0_CAM_OFFSET_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_OFFSET0_CAM */ #define IR_COMPRESS_KNEE_OFFSET0_CAM_COUNT (1U) /*! @name KNEE_OFFSET1_CAM - Camera 0 IR Compress Knee Offset 1 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_OFFSET1_CAM_OFFSET_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_OFFSET1_CAM_OFFSET_SHIFT (0U) #define IR_COMPRESS_KNEE_OFFSET1_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_OFFSET1_CAM_OFFSET_SHIFT)) & IR_COMPRESS_KNEE_OFFSET1_CAM_OFFSET_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_OFFSET1_CAM */ #define IR_COMPRESS_KNEE_OFFSET1_CAM_COUNT (1U) /*! @name KNEE_OFFSET2_CAM - Camera 0 IR Compress Knee Offset 2 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_OFFSET2_CAM_OFFSET_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_OFFSET2_CAM_OFFSET_SHIFT (0U) #define IR_COMPRESS_KNEE_OFFSET2_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_OFFSET2_CAM_OFFSET_SHIFT)) & IR_COMPRESS_KNEE_OFFSET2_CAM_OFFSET_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_OFFSET2_CAM */ #define IR_COMPRESS_KNEE_OFFSET2_CAM_COUNT (1U) /*! @name KNEE_OFFSET3_CAM - Camera 0 IR Compress Knee Offset 3 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_OFFSET3_CAM_OFFSET_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_OFFSET3_CAM_OFFSET_SHIFT (0U) #define IR_COMPRESS_KNEE_OFFSET3_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_OFFSET3_CAM_OFFSET_SHIFT)) & IR_COMPRESS_KNEE_OFFSET3_CAM_OFFSET_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_OFFSET3_CAM */ #define IR_COMPRESS_KNEE_OFFSET3_CAM_COUNT (1U) /*! @name KNEE_OFFSET4_CAM - Camera 0 IR Compress Knee Offset 4 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_OFFSET4_CAM_OFFSET_MASK (0xFFFFFU) #define IR_COMPRESS_KNEE_OFFSET4_CAM_OFFSET_SHIFT (0U) #define IR_COMPRESS_KNEE_OFFSET4_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_OFFSET4_CAM_OFFSET_SHIFT)) & IR_COMPRESS_KNEE_OFFSET4_CAM_OFFSET_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_OFFSET4_CAM */ #define IR_COMPRESS_KNEE_OFFSET4_CAM_COUNT (1U) /*! @name KNEE_RATIO01_CAM - Camera 0 IR Compress Knee Ratio 01 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_RATIO01_CAM_RATIO0_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_RATIO01_CAM_RATIO0_SHIFT (0U) #define IR_COMPRESS_KNEE_RATIO01_CAM_RATIO0(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_RATIO01_CAM_RATIO0_SHIFT)) & IR_COMPRESS_KNEE_RATIO01_CAM_RATIO0_MASK) #define IR_COMPRESS_KNEE_RATIO01_CAM_RATIO1_MASK (0xFFFF0000U) #define IR_COMPRESS_KNEE_RATIO01_CAM_RATIO1_SHIFT (16U) #define IR_COMPRESS_KNEE_RATIO01_CAM_RATIO1(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_RATIO01_CAM_RATIO1_SHIFT)) & IR_COMPRESS_KNEE_RATIO01_CAM_RATIO1_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_RATIO01_CAM */ #define IR_COMPRESS_KNEE_RATIO01_CAM_COUNT (1U) /*! @name KNEE_RATIO23_CAM - Camera 0 IR Compress Knee Ratio 23 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_RATIO23_CAM_RATIO2_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_RATIO23_CAM_RATIO2_SHIFT (0U) #define IR_COMPRESS_KNEE_RATIO23_CAM_RATIO2(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_RATIO23_CAM_RATIO2_SHIFT)) & IR_COMPRESS_KNEE_RATIO23_CAM_RATIO2_MASK) #define IR_COMPRESS_KNEE_RATIO23_CAM_RATIO3_MASK (0xFFFF0000U) #define IR_COMPRESS_KNEE_RATIO23_CAM_RATIO3_SHIFT (16U) #define IR_COMPRESS_KNEE_RATIO23_CAM_RATIO3(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_RATIO23_CAM_RATIO3_SHIFT)) & IR_COMPRESS_KNEE_RATIO23_CAM_RATIO3_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_RATIO23_CAM */ #define IR_COMPRESS_KNEE_RATIO23_CAM_COUNT (1U) /*! @name KNEE_RATIO4_CAM - Camera 0 IR Compress Knee Ratio 4 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_RATIO4_CAM_RATIO4_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_RATIO4_CAM_RATIO4_SHIFT (0U) #define IR_COMPRESS_KNEE_RATIO4_CAM_RATIO4(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_RATIO4_CAM_RATIO4_SHIFT)) & IR_COMPRESS_KNEE_RATIO4_CAM_RATIO4_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_RATIO4_CAM */ #define IR_COMPRESS_KNEE_RATIO4_CAM_COUNT (1U) /*! @name KNEE_NPOINT0_CAM - Camera 0 IR Compress New KneePoint 0 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_NPOINT0_CAM_KNEEPOINT_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_NPOINT0_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_NPOINT0_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_NPOINT0_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_NPOINT0_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_NPOINT0_CAM */ #define IR_COMPRESS_KNEE_NPOINT0_CAM_COUNT (1U) /*! @name KNEE_NPOINT1_CAM - Camera 0 IR Compress New KneePoint 1 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_NPOINT1_CAM_KNEEPOINT_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_NPOINT1_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_NPOINT1_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_NPOINT1_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_NPOINT1_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_NPOINT1_CAM */ #define IR_COMPRESS_KNEE_NPOINT1_CAM_COUNT (1U) /*! @name KNEE_NPOINT2_CAM - Camera 0 IR Compress New KneePoint 2 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_NPOINT2_CAM_KNEEPOINT_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_NPOINT2_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_NPOINT2_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_NPOINT2_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_NPOINT2_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_NPOINT2_CAM */ #define IR_COMPRESS_KNEE_NPOINT2_CAM_COUNT (1U) /*! @name KNEE_NPOINT3_CAM - Camera 0 IR Compress New KneePoint 3 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_NPOINT3_CAM_KNEEPOINT_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_NPOINT3_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_NPOINT3_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_NPOINT3_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_NPOINT3_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_NPOINT3_CAM */ #define IR_COMPRESS_KNEE_NPOINT3_CAM_COUNT (1U) /*! @name KNEE_NPOINT4_CAM - Camera 0 IR Compress New KneePoint 4 Register */ /*! @{ */ #define IR_COMPRESS_KNEE_NPOINT4_CAM_KNEEPOINT_MASK (0xFFFFU) #define IR_COMPRESS_KNEE_NPOINT4_CAM_KNEEPOINT_SHIFT (0U) #define IR_COMPRESS_KNEE_NPOINT4_CAM_KNEEPOINT(x) (((uint32_t)(((uint32_t)(x)) << IR_COMPRESS_KNEE_NPOINT4_CAM_KNEEPOINT_SHIFT)) & IR_COMPRESS_KNEE_NPOINT4_CAM_KNEEPOINT_MASK) /*! @} */ /* The count of IR_COMPRESS_KNEE_NPOINT4_CAM */ #define IR_COMPRESS_KNEE_NPOINT4_CAM_COUNT (1U) /*! * @} */ /* end of group IR_COMPRESS_Register_Masks */ /* IR_COMPRESS - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__IR_COMPRESS base address */ #define CAMERA__ISP__IR_COMPRESS_BASE (0x4AE00780u) /** Peripheral CAMERA__ISP__IR_COMPRESS base pointer */ #define CAMERA__ISP__IR_COMPRESS ((IR_COMPRESS_Type *)CAMERA__ISP__IR_COMPRESS_BASE) /** Array initializer of IR_COMPRESS peripheral base addresses */ #define IR_COMPRESS_BASE_ADDRS { CAMERA__ISP__IR_COMPRESS_BASE } /** Array initializer of IR_COMPRESS peripheral base pointers */ #define IR_COMPRESS_BASE_PTRS { CAMERA__ISP__IR_COMPRESS } /*! * @} */ /* end of group IR_COMPRESS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ISI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer * @{ */ /** ISI - Register Layout Typedef */ typedef struct { __IO uint32_t CHNL_CTRL; /**< Channel Control, offset: 0x0 */ __IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control, offset: 0x4 */ __IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control, offset: 0x8 */ __IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */ __IO uint32_t CHNL_IER; /**< Channel Interrupt Enable, offset: 0x10 */ __IO uint32_t CHNL_STS; /**< Channel Status, offset: 0x14 */ __IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor, offset: 0x18 */ __IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset, offset: 0x1C */ __IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate, offset: 0x20 */ __IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate, offset: 0x24 */ __IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient 0, offset: 0x28 */ __IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient 1, offset: 0x2C */ __IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient 2, offset: 0x30 */ __IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient 3, offset: 0x34 */ __IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient 4, offset: 0x38 */ __IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient 5, offset: 0x3C */ struct { /* offset: 0x40, array step: 0xC */ __IO uint32_t CHNL_ROI_ALPHA; /**< Channel Alpha Value for ROI 0..Channel Alpha Value for ROI 3, array offset: 0x40, array step: 0xC */ __IO uint32_t CHNL_ROI_ULC; /**< Channel Upper Left Coordinate for ROI 0..Channel Upper Left Coordinate for ROI 3, array offset: 0x44, array step: 0xC */ __IO uint32_t CHNL_ROI_LRC; /**< Channel Lower Right Coordinate for ROI 0..Channel Lower Right Coordinate for ROI 3, array offset: 0x48, array step: 0xC */ } ROI[4]; __IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */ __IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */ __IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */ __IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */ __IO uint32_t CHNL_IN_BUF_ADDR; /**< Channel Input Buffer Address, offset: 0x80 */ __IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */ __IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */ __IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */ __IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */ __IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */ __IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */ __IO uint32_t CHNL_FLOW_CTRL; /**< Channel Flow Control, offset: 0x9C */ __IO uint32_t CHNL_Y_BUF1_XTND_ADDR; /**< Channel Output Y-Buffer 1 Extended Address, offset: 0xA0 */ __IO uint32_t CHNL_U_BUF1_XTND_ADDR; /**< Channel Output U-Buffer 1 Extended Address, offset: 0xA4 */ __IO uint32_t CHNL_V_BUF1_XTND_ADDR; /**< Channel Output V-Buffer 1 Extended Address, offset: 0xA8 */ __IO uint32_t CHNL_Y_BUF2_XTND_ADDR; /**< Channel Output Y-Buffer 2 Extended Address, offset: 0xAC */ __IO uint32_t CHNL_U_BUF2_XTND_ADDR; /**< Channel Output U-Buffer 2 Extended Address, offset: 0xB0 */ __IO uint32_t CHNL_V_BUF2_XTND_ADDR; /**< Channel Output V-Buffer 2 Extended Address, offset: 0xB4 */ __IO uint32_t CHNL_IN_BUF_XTND_ADDR; /**< Channel Input Buffer Extended Address, offset: 0xB8 */ uint8_t RESERVED_0[4]; __IO uint32_t PIXEL_DATA_ADDR_OFFSET; /**< RAW32 Pixel Data Offset, offset: 0xC0 */ __IO uint32_t STAT_DATA_ADDR_OFFSET; /**< RAW32 Statistics Data Offset, offset: 0xC4 */ __IO uint32_t CHNL_IMG_CFG2; /**< Channel Image Configuration 2, offset: 0xC8 */ __IO uint32_t CHNL_IMG_CFG3; /**< Channel Image Configuration 3, offset: 0xCC */ __IO uint32_t CHNL_OUT_BUF_MAX_SIZE_Y; /**< Channel RGB or Luma (Y) Output Buffer Max Size, offset: 0xD0 */ __IO uint32_t CHNL_OUT_BUF_MAX_SIZE_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer Max Size, offset: 0xD4 */ __IO uint32_t CHNL_OUT_BUF_MAX_SIZE_V; /**< Channel Chroma (V/Cr) Output Buffer Max Size, offset: 0xD8 */ } ISI_Type; /* ---------------------------------------------------------------------------- -- ISI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ISI_Register_Masks ISI Register Masks * @{ */ /*! @name CHNL_CTRL - Channel Control */ /*! @{ */ #define ISI_CHNL_CTRL_SRC_MASK (0x7U) #define ISI_CHNL_CTRL_SRC_SHIFT (0U) /*! SRC - Input Image Source Port Selection * 0b000..Port 0 * 0b001..Port 1 * 0b010..Port 2 * 0b011..Port 3 * 0b100..Port 4 (input port 4 is connected to AXI read) */ #define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK) #define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U) #define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U) /*! SRC_TYPE - Type of Selected Input Image Source * 0b0..Pixel link * 0b1..Memory */ #define ISI_CHNL_CTRL_SRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK) #define ISI_CHNL_CTRL_VC_ID_0_MASK (0xC0U) #define ISI_CHNL_CTRL_VC_ID_0_SHIFT (6U) /*! VC_ID_0 - Virtual Channel ID * 0b00..Virtual channel 0 selected or no virtual channel used * 0b01..Virtual channel 1 selected * 0b10..Virtual channel 2 selected * 0b11..Virtual channel 3 selected */ #define ISI_CHNL_CTRL_VC_ID_0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VC_ID_0_SHIFT)) & ISI_CHNL_CTRL_VC_ID_0_MASK) #define ISI_CHNL_CTRL_SEC_LB_SRC_MASK (0x700U) #define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT (8U) /*! SEC_LB_SRC - Secondary Line Buffer Source */ #define ISI_CHNL_CTRL_SEC_LB_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK) #define ISI_CHNL_CTRL_VC_ID_1_MASK (0x10000U) #define ISI_CHNL_CTRL_VC_ID_1_SHIFT (16U) /*! VC_ID_1 - Virtual Channel ID * 0b0..Virtual channel 0 to 3 selected * 0b1..Virtual channel 4 to 7 selected */ #define ISI_CHNL_CTRL_VC_ID_1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VC_ID_1_SHIFT)) & ISI_CHNL_CTRL_VC_ID_1_MASK) #define ISI_CHNL_CTRL_VER_ID_MASK (0x3C0000U) #define ISI_CHNL_CTRL_VER_ID_SHIFT (18U) /*! VER_ID - Version ID */ #define ISI_CHNL_CTRL_VER_ID(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VER_ID_SHIFT)) & ISI_CHNL_CTRL_VER_ID_MASK) #define ISI_CHNL_CTRL_RAW_MSB_ALIGN_MASK (0x400000U) #define ISI_CHNL_CTRL_RAW_MSB_ALIGN_SHIFT (22U) /*! RAW_MSB_ALIGN - RAW to MSB Align * 0b0..LSB aligned selection * 0b1..MSB aligned selection */ #define ISI_CHNL_CTRL_RAW_MSB_ALIGN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_RAW_MSB_ALIGN_SHIFT)) & ISI_CHNL_CTRL_RAW_MSB_ALIGN_MASK) #define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U) #define ISI_CHNL_CTRL_SW_RST_SHIFT (24U) /*! SW_RST - Software Reset * 0b0..No reset * 0b1..Software reset */ #define ISI_CHNL_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK) #define ISI_CHNL_CTRL_CHAIN_BUF_MASK (0x6000000U) #define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT (25U) /*! CHAIN_BUF - Chain Line Buffer Control * 0b00..No line buffers chained (supports 2048 or less horizontal resolution) * 0b01..Two line buffers chained (supports 4096 horizontal resolution) * 0b10.. * 0b11.. */ #define ISI_CHNL_CTRL_CHAIN_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK) #define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U) #define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U) /*! CHNL_BYPASS - Channel Bypass Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_CTRL_CHNL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK) #define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U) #define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U) /*! CLK_EN - Channel Clock Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK) #define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U) #define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U) /*! CHNL_EN - Enable Channel Processing * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_CTRL_CHNL_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK) /*! @} */ /*! @name CHNL_IMG_CTRL - Channel Image Control */ /*! @{ */ #define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U) #define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U) /*! CSC_BYP - Color Space Conversion Bypass Control * 0b0..CSC operational * 0b1..CSC bypassed */ #define ISI_CHNL_IMG_CTRL_CSC_BYP(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK) #define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U) #define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U) /*! CSC_MODE - Color Space Conversion Operating Mode * 0b00..Convert from YUV to RGB * 0b01..Convert from YCbCr to RGB * 0b10..Convert from RGB to YUV * 0b11..Convert from RGB to YCbCr */ #define ISI_CHNL_IMG_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK) #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U) #define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U) /*! YCBCR_MODE - YCbCr Mode * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK) #define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U) #define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U) /*! HFLIP_EN - Horizontal Flip Control * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK) #define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U) #define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U) /*! VFLIP_EN - Vertical Flip Control * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK) #define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U) #define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U) /*! CROP_EN - Output Image Cropping Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IMG_CTRL_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK) #define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U) #define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U) /*! DEC_Y - Vertical Pre-Decimation Control * 0b00..Disabled * 0b01..Decimate by 2 * 0b10..Decimate by 4 * 0b11..Decimate by 8 */ #define ISI_CHNL_IMG_CTRL_DEC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK) #define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U) #define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U) /*! DEC_X - Horizontal Pre-Decimation Control * 0b00..Disabled * 0b01..Decimate by 2 * 0b10..Decimate by 4 * 0b11..Decimate by 8 */ #define ISI_CHNL_IMG_CTRL_DEC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK) #define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U) #define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U) /*! DEINT - Deinterlace Control * 0b000, 0b001..No deinterlacing * 0b010..Weave deinterlacing (odd, even) * 0b011..Weave deinterlacing (even, odd) * 0b100..Blending or linear interpolation (odd + even) * 0b101..Blending or linear interpolation (even + odd) * 0b110, 0b111..Line doubling (both odd and even fields are doubled) */ #define ISI_CHNL_IMG_CTRL_DEINT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U) /*! GBL_ALPHA_EN - Global Alpha Value Insertion Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U) #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U) /*! GBL_ALPHA_VAL - Global Alpha Value * 0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels */ #define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK) #define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x7F000000U) #define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U) /*! FORMAT - Output Image Format */ #define ISI_CHNL_IMG_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control */ /*! @{ */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U) /*! PANIC_SET_THD_Y - Overflow Panic Set Threshold Value for Y or RGB Output Buffer * 0b0000..No panic alert * 0b0001-0b1111..Panic asserts */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U) /*! PANIC_SET_THD_U - Overflow Panic Set Threshold Value for U Output Buffer * 0b0000..No panic alert * 0b0001-0b1111..Panic asserts */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U) /*! LOAD_BUF1_ADDR - Load Buffer 1 Address */ #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U) #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U) /*! LOAD_BUF2_ADDR - Load Buffer 2 Address */ #define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U) #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U) /*! PANIC_SET_THD_V - Overflow Panic Set Threshold Value for V Output Buffer * 0b0000..No panic alert * 0b0001-0b1111..Panic asserts */ #define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U) /*! MAX_WR_BEATS_UV - Maximum AXI Write Beats for U- and V-Buffers * 0b0..8 beats per write (128 bytes) * 0b1..16 beats per write (256 bytes) */ #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U) #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U) /*! MAX_WR_BEATS_Y - Maximum AXI Write Beats for Y-Buffer * 0b0..8 beats per write (128 bytes) * 0b1..16 beats per write (256 bytes) */ #define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK) /*! @} */ /*! @name CHNL_IMG_CFG - Channel Image Configuration */ /*! @{ */ #define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU) #define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U) /*! WIDTH - Input Image Width */ #define ISI_CHNL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK) #define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x3FFF0000U) #define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U) /*! HEIGHT - Input Image Height */ #define ISI_CHNL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK) /*! @} */ /*! @name CHNL_IER - Channel Interrupt Enable */ /*! @{ */ #define ISI_CHNL_IER_LINE_NO_PIXEL_ERR_EN_MASK (0x1U) #define ISI_CHNL_IER_LINE_NO_PIXEL_ERR_EN_SHIFT (0U) /*! LINE_NO_PIXEL_ERR_EN - No Pixel Data Detected in a Line Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_LINE_NO_PIXEL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_NO_PIXEL_ERR_EN_SHIFT)) & ISI_CHNL_IER_LINE_NO_PIXEL_ERR_EN_MASK) #define ISI_CHNL_IER_FRAME_NO_PIXEL_ERR_EN_MASK (0x2U) #define ISI_CHNL_IER_FRAME_NO_PIXEL_ERR_EN_SHIFT (1U) /*! FRAME_NO_PIXEL_ERR_EN - No Pixel Data is Detected in a Frame Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_FRAME_NO_PIXEL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRAME_NO_PIXEL_ERR_EN_SHIFT)) & ISI_CHNL_IER_FRAME_NO_PIXEL_ERR_EN_MASK) #define ISI_CHNL_IER_LATE_HSYNC2_ERR_EN_MASK (0x4U) #define ISI_CHNL_IER_LATE_HSYNC2_ERR_EN_SHIFT (2U) /*! LATE_HSYNC2_ERR_EN - HSYNC Timing (Late) Error Interrupt Enable for RAW32 staggered pixel lines * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_LATE_HSYNC2_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_HSYNC2_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_HSYNC2_ERR_EN_MASK) #define ISI_CHNL_IER_LATE_HSYNC_ERR_EN_MASK (0x8U) #define ISI_CHNL_IER_LATE_HSYNC_ERR_EN_SHIFT (3U) /*! LATE_HSYNC_ERR_EN - HSYNC Timing (Late) Error Interrupt Flag Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_LATE_HSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_HSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_HSYNC_ERR_EN_MASK) #define ISI_CHNL_IER_OUT_MEM_LOC_Y_EN_MASK (0x10U) #define ISI_CHNL_IER_OUT_MEM_LOC_Y_EN_SHIFT (4U) /*! OUT_MEM_LOC_Y_EN - Tentative Write Out of Valid Channel RGB or Luma (Y) Output Buffer Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_OUT_MEM_LOC_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OUT_MEM_LOC_Y_EN_SHIFT)) & ISI_CHNL_IER_OUT_MEM_LOC_Y_EN_MASK) #define ISI_CHNL_IER_OUT_MEM_LOC_U_EN_MASK (0x20U) #define ISI_CHNL_IER_OUT_MEM_LOC_U_EN_SHIFT (5U) /*! OUT_MEM_LOC_U_EN - Tentative Write Out of Valid Channel Chroma (U/Cb/UV/CbCr) Output Buffer Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_OUT_MEM_LOC_U_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OUT_MEM_LOC_U_EN_SHIFT)) & ISI_CHNL_IER_OUT_MEM_LOC_U_EN_MASK) #define ISI_CHNL_IER_OUT_MEM_LOC_V_EN_MASK (0x40U) #define ISI_CHNL_IER_OUT_MEM_LOC_V_EN_SHIFT (6U) /*! OUT_MEM_LOC_V_EN - Tentative Write Out of Valid Channel Chroma (V/Cr) Output Buffer Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_OUT_MEM_LOC_V_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OUT_MEM_LOC_V_EN_SHIFT)) & ISI_CHNL_IER_OUT_MEM_LOC_V_EN_MASK) #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x10000U) #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (16U) /*! LATE_VSYNC_ERR_EN - VSYNC Timing (Late) Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK) #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x20000U) #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (17U) /*! EARLY_VSYNC_ERR_EN - VSYNC Timing (Early) Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK) #define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x40000U) #define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (18U) /*! OFLW_Y_BUF_EN - Y Output Buffer Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK) #define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK (0x80000U) #define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT (19U) /*! PANIC_Y_BUF_EN - Y Output Buffer Potential Overflow Panic Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_PANIC_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x100000U) #define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (20U) /*! OFLW_U_BUF_EN - U Output Buffer Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK) #define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK (0x200000U) #define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT (21U) /*! PANIC_U_BUF_EN - U Output Buffer Potential Overflow Panic Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_PANIC_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK) #define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x400000U) #define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (22U) /*! OFLW_V_BUF_EN - V Output Buffer Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK) #define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK (0x800000U) #define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT (23U) /*! PANIC_V_BUF_EN - V Output Buffer Potential Overflow Panic Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_PANIC_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK) #define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U) #define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U) /*! AXI_RD_ERR_EN - AXI Bus Read Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_AXI_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U) #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U) /*! AXI_WR_ERR_Y_EN - AXI Bus Read Error Interrupt Enable for Y and RGB Data Buffer * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U) #define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U) /*! AXI_WR_ERR_U_EN - AXI Bus Read Error Interrupt Enable for U Data Buffer * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK) #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U) #define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U) /*! AXI_WR_ERR_V_EN - AXI Bus Read Error Interrupt Enable for V Data Buffer * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK) #define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U) #define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U) /*! FRM_RCVD_EN - Frame Received Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_FRM_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK) #define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U) #define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U) /*! LINE_RCVD_EN - Line Received Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_LINE_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK) #define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U) #define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U) /*! MEM_RD_DONE_EN - Memory Read Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_IER_MEM_RD_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK) /*! @} */ /*! @name CHNL_STS - Channel Status */ /*! @{ */ #define ISI_CHNL_STS_LINE_NO_PIXEL_MASK (0x1U) #define ISI_CHNL_STS_LINE_NO_PIXEL_SHIFT (0U) /*! LINE_NO_PIXEL - No Pixel Data Detected in Line * 0b0..No error * 0b1..No pixel detected */ #define ISI_CHNL_STS_LINE_NO_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_NO_PIXEL_SHIFT)) & ISI_CHNL_STS_LINE_NO_PIXEL_MASK) #define ISI_CHNL_STS_FRAME_NO_PIXEL_MASK (0x2U) #define ISI_CHNL_STS_FRAME_NO_PIXEL_SHIFT (1U) /*! FRAME_NO_PIXEL - No Pixel Data in Frame * 0b0..No error * 0b1..No pixel detected */ #define ISI_CHNL_STS_FRAME_NO_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRAME_NO_PIXEL_SHIFT)) & ISI_CHNL_STS_FRAME_NO_PIXEL_MASK) #define ISI_CHNL_STS_LATE_HSYNC2_ERR_MASK (0x4U) #define ISI_CHNL_STS_LATE_HSYNC2_ERR_SHIFT (2U) /*! LATE_HSYNC2_ERR - HSYNC Timing (Late) Error Interrupt Flag for RAW32 Staggered Pixel Lines * 0b0..No error * 0b1..HSYNC detected later */ #define ISI_CHNL_STS_LATE_HSYNC2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_HSYNC2_ERR_SHIFT)) & ISI_CHNL_STS_LATE_HSYNC2_ERR_MASK) #define ISI_CHNL_STS_LATE_HSYNC_ERR_MASK (0x8U) #define ISI_CHNL_STS_LATE_HSYNC_ERR_SHIFT (3U) /*! LATE_HSYNC_ERR - HSYNC Timing (Late) Error Interrupt flag * 0b0..No error * 0b1..HSYNC detected later */ #define ISI_CHNL_STS_LATE_HSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_HSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_HSYNC_ERR_MASK) #define ISI_CHNL_STS_OUT_MEM_LOC_Y_MASK (0x10U) #define ISI_CHNL_STS_OUT_MEM_LOC_Y_SHIFT (4U) /*! OUT_MEM_LOC_Y - Tentative Write Detected Out of valid Channel RGB or Luma (Y) Output Buffer * 0b0..No error * 0b1..Tentative write is detected */ #define ISI_CHNL_STS_OUT_MEM_LOC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OUT_MEM_LOC_Y_SHIFT)) & ISI_CHNL_STS_OUT_MEM_LOC_Y_MASK) #define ISI_CHNL_STS_OUT_MEM_LOC_U_MASK (0x20U) #define ISI_CHNL_STS_OUT_MEM_LOC_U_SHIFT (5U) /*! OUT_MEM_LOC_U - Tentative Write Detected Out of Valid Channel Chroma (U/Cb/UV/CbCr) Output Buffer * 0b0..No error * 0b1..Tentative write is detected */ #define ISI_CHNL_STS_OUT_MEM_LOC_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OUT_MEM_LOC_U_SHIFT)) & ISI_CHNL_STS_OUT_MEM_LOC_U_MASK) #define ISI_CHNL_STS_OUT_MEM_LOC_V_MASK (0x40U) #define ISI_CHNL_STS_OUT_MEM_LOC_V_SHIFT (6U) /*! OUT_MEM_LOC_V - Tentative Write Detected Out of Valid Channel Chroma (V/Cr) Output Buffer * 0b0..No error * 0b1..Tentative write is detected */ #define ISI_CHNL_STS_OUT_MEM_LOC_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OUT_MEM_LOC_V_SHIFT)) & ISI_CHNL_STS_OUT_MEM_LOC_V_MASK) #define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U) #define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U) /*! BUF1_ACTIVE - Current Frame Stored in Buffer 1 Address * 0b0..Buffer 1 address inactive * 0b1..Buffer 1 address in use */ #define ISI_CHNL_STS_BUF1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK) #define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U) #define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U) /*! BUF2_ACTIVE - Current Frame Stored in Buffer 2 Address * 0b0..Buffer 2 address inactive * 0b1..Buffer 2 address in use */ #define ISI_CHNL_STS_BUF2_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK) #define ISI_CHNL_STS_MEM_RD_OFLOW_MASK (0x400U) #define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT (10U) /*! MEM_RD_OFLOW - Memory Read FIFO Overflow Error Status * 0b0..No overflow * 0b1..FIFO overflow */ #define ISI_CHNL_STS_MEM_RD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK) #define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x10000U) #define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (16U) /*! LATE_VSYNC_ERR - VSYNC Timing (Late) Error Interrupt flag * 0b0..No error * 0b1..VSYNC detected later */ #define ISI_CHNL_STS_LATE_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK) #define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x20000U) #define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (17U) /*! EARLY_VSYNC_ERR - VSYNC Timing (Early) Error Interrupt flag * 0b0..No error * 0b1..VSYNC detected earlier */ #define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK) #define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x40000U) #define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (18U) /*! OFLW_Y_BUF - Overflow in Y or RGB Output Buffer Interrupt Flag * 0b0..No overflow * 0b1..Overflow */ #define ISI_CHNL_STS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK) #define ISI_CHNL_STS_PANIC_Y_BUF_MASK (0x80000U) #define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT (19U) /*! PANIC_Y_BUF - Y or RGB Output Buffer Potential Overflow Panic Alert Interrupt Flag * 0b0..Threshold limit not crossed * 0b1..Threshold limit crossed */ #define ISI_CHNL_STS_PANIC_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK) #define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x100000U) #define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (20U) /*! OFLW_U_BUF - Overflow in U Output Buffer Interrupt Flag * 0b0..No overflow * 0b1..Overflow */ #define ISI_CHNL_STS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK) #define ISI_CHNL_STS_PANIC_U_BUF_MASK (0x200000U) #define ISI_CHNL_STS_PANIC_U_BUF_SHIFT (21U) /*! PANIC_U_BUF - U Output Buffer Potential Overflow Panic Alert Interrupt Flag * 0b0..Threshold limit not crossed * 0b1..Threshold limit crossed */ #define ISI_CHNL_STS_PANIC_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK) #define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U) #define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U) /*! OFLW_V_BUF - Overflow in V Output Buffer Interrupt Flag * 0b0..No overflow * 0b1..Overflow */ #define ISI_CHNL_STS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK) #define ISI_CHNL_STS_PANIC_V_BUF_MASK (0x800000U) #define ISI_CHNL_STS_PANIC_V_BUF_SHIFT (23U) /*! PANIC_V_BUF - V Output Buffer Potential Overflow Panic Alert Interrupt Flag * 0b0..Threshold limit not crossed * 0b1..Threshold limit crossed */ #define ISI_CHNL_STS_PANIC_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK) #define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U) #define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U) /*! AXI_RD_ERR - AXI Bus Read Error Interrupt Flag * 0b0..No error * 0b1..Error occurred */ #define ISI_CHNL_STS_AXI_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U) #define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U) /*! AXI_WR_ERR_Y - AXI Bus Write Error Interrupt Flag for Y/RGB Data Buffer * 0b0..No error * 0b1..Error occurred */ #define ISI_CHNL_STS_AXI_WR_ERR_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U) #define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U) /*! AXI_WR_ERR_U - AXI Bus Write Error Interrupt Flag for U Data Buffer * 0b0..No error * 0b1..Error occurred */ #define ISI_CHNL_STS_AXI_WR_ERR_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK) #define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U) #define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U) /*! AXI_WR_ERR_V - AXI Bus Write Error Interrupt Flag for V Data Buffer * 0b0..No error * 0b1..Error occurred */ #define ISI_CHNL_STS_AXI_WR_ERR_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK) #define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U) #define ISI_CHNL_STS_FRM_STRD_SHIFT (29U) /*! FRM_STRD - Frame Stored Successfully Interrupt Flag * 0b0..Not received or in progress * 0b1..Received and stored */ #define ISI_CHNL_STS_FRM_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK) #define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U) #define ISI_CHNL_STS_LINE_STRD_SHIFT (30U) /*! LINE_STRD - Line Received and Stored Interrupt Flag * 0b0..Not received * 0b1..Received and stored */ #define ISI_CHNL_STS_LINE_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK) #define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U) #define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U) /*! MEM_RD_DONE - Memory Read Complete Interrupt Flag * 0b0..Not complete or not started * 0b1..Completed */ #define ISI_CHNL_STS_MEM_RD_DONE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK) /*! @} */ /*! @name CHNL_SCALE_FACTOR - Channel Scale Factor */ /*! @{ */ #define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU) #define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U) /*! X_SCALE - Horizontal Scaling Factor */ #define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK) #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U) #define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U) /*! Y_SCALE - Vertical Scaling Factor */ #define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK) /*! @} */ /*! @name CHNL_SCALE_OFFSET - Channel Scale Offset */ /*! @{ */ #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU) #define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U) /*! X_OFFSET - Horizontal Scaling Offset */ #define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK) #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U) #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U) /*! Y_OFFSET - Vertical Scaling Offset */ #define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK) /*! @} */ /*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate */ /*! @{ */ #define ISI_CHNL_CROP_ULC_Y_MASK (0x1FFFU) #define ISI_CHNL_CROP_ULC_Y_SHIFT (0U) /*! Y - Upper Left Y-Coordinate */ #define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK) #define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_CROP_ULC_X_SHIFT (16U) /*! X - Upper Left X-Coordinate */ #define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK) /*! @} */ /*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate */ /*! @{ */ #define ISI_CHNL_CROP_LRC_Y_MASK (0x1FFFU) #define ISI_CHNL_CROP_LRC_Y_SHIFT (0U) /*! Y - Lower Right Y-Coordinate */ #define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK) #define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_CROP_LRC_X_SHIFT (16U) /*! X - Lower Right X-Coordinate */ #define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient 0 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U) /*! A1 - CSC Coefficient A1 Value */ #define ISI_CHNL_CSC_COEFF0_A1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK) #define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U) /*! A2 - CSC Coefficient A2 Value */ #define ISI_CHNL_CSC_COEFF0_A2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient 1 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U) /*! A3 - CSC Coefficient A3 Value */ #define ISI_CHNL_CSC_COEFF1_A3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK) #define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U) /*! B1 - CSC Coefficient B1 Value */ #define ISI_CHNL_CSC_COEFF1_B1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient 2 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U) /*! B2 - CSC Coefficient B2 Value */ #define ISI_CHNL_CSC_COEFF2_B2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK) #define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U) /*! B3 - CSC Coefficient B3 Value */ #define ISI_CHNL_CSC_COEFF2_B3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient 3 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U) /*! C1 - CSC Coefficient C1 Value */ #define ISI_CHNL_CSC_COEFF3_C1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK) #define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U) #define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U) /*! C2 - CSC Coefficient C2 Value */ #define ISI_CHNL_CSC_COEFF3_C2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient 4 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU) #define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U) /*! C3 - CSC Coefficient C3 Value */ #define ISI_CHNL_CSC_COEFF4_C3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK) #define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U) #define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U) /*! D1 - CSC Coefficient D1 Value */ #define ISI_CHNL_CSC_COEFF4_D1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK) /*! @} */ /*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient 5 */ /*! @{ */ #define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU) #define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U) /*! D2 - CSC Coefficient D2 Value */ #define ISI_CHNL_CSC_COEFF5_D2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK) #define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U) #define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U) /*! D3 - CSC Coefficient D3 Value */ #define ISI_CHNL_CSC_COEFF5_D3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK) /*! @} */ /*! @name CHNL_ROI_ALPHA - Channel Alpha Value for ROI 0..Channel Alpha Value for ROI 3 */ /*! @{ */ #define ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK (0x10000U) #define ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT (16U) /*! ALPHA_EN - Alpha Value Insertion Enable * 0b0..Disable * 0b1..Enable */ #define ISI_CHNL_ROI_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_EN_MASK) #define ISI_CHNL_ROI_ALPHA_ALPHA_MASK (0xFF000000U) #define ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT (24U) /*! ALPHA - Alpha Value */ #define ISI_CHNL_ROI_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_ALPHA_ALPHA_MASK) /*! @} */ /* The count of ISI_CHNL_ROI_ALPHA */ #define ISI_CHNL_ROI_ALPHA_COUNT (4U) /*! @name CHNL_ROI_ULC - Channel Upper Left Coordinate for ROI 0..Channel Upper Left Coordinate for ROI 3 */ /*! @{ */ #define ISI_CHNL_ROI_ULC_Y_MASK (0x1FFFU) #define ISI_CHNL_ROI_ULC_Y_SHIFT (0U) /*! Y - Upper Left Y-Coordinate */ #define ISI_CHNL_ROI_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_Y_SHIFT)) & ISI_CHNL_ROI_ULC_Y_MASK) #define ISI_CHNL_ROI_ULC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_ULC_X_SHIFT (16U) /*! X - Upper Left X-Coordinate */ #define ISI_CHNL_ROI_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_ULC_X_SHIFT)) & ISI_CHNL_ROI_ULC_X_MASK) /*! @} */ /* The count of ISI_CHNL_ROI_ULC */ #define ISI_CHNL_ROI_ULC_COUNT (4U) /*! @name CHNL_ROI_LRC - Channel Lower Right Coordinate for ROI 0..Channel Lower Right Coordinate for ROI 3 */ /*! @{ */ #define ISI_CHNL_ROI_LRC_Y_MASK (0x1FFFU) #define ISI_CHNL_ROI_LRC_Y_SHIFT (0U) /*! Y - Lower Right Y-Coordinate */ #define ISI_CHNL_ROI_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_Y_SHIFT)) & ISI_CHNL_ROI_LRC_Y_MASK) #define ISI_CHNL_ROI_LRC_X_MASK (0xFFF0000U) #define ISI_CHNL_ROI_LRC_X_SHIFT (16U) /*! X - Lower Right X-Coordinate */ #define ISI_CHNL_ROI_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_LRC_X_SHIFT)) & ISI_CHNL_ROI_LRC_X_MASK) /*! @} */ /* The count of ISI_CHNL_ROI_LRC */ #define ISI_CHNL_ROI_LRC_COUNT (4U) /*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U) /*! ADDR - Address for RGB or Y (Luma) */ #define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U) /*! ADDR - Address for U/Cb/UV/CbCr */ #define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U) /*! ADDR - Address for V or Cr */ #define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */ /*! @{ */ #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U) /*! LINE_PITCH - Output Buffer Line Pitch */ #define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK) /*! @} */ /*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */ /*! @{ */ #define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT (0U) /*! ADDR - Starting Address */ #define ISI_CHNL_IN_BUF_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK) /*! @} */ /*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */ /*! @{ */ #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U) /*! LINE_PITCH - Line Pitch */ #define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK) #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U) #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U) /*! FRM_PITCH - Frame Pitch */ #define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK) /*! @} */ /*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */ /*! @{ */ #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U) #define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U) /*! READ_MEM - Initiate Read from Memory * 0b0..No reads * 0b1..Reads initiated */ #define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK) #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U) #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U) /*! IMG_TYPE - Input Image Format */ #define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U) /*! ADDR - Starting Address for RGB or Y */ #define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U) /*! ADDR - Starting Address for U/Cb or 2-plane UV/CbCr */ #define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK) /*! @} */ /*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */ /*! @{ */ #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U) /*! ADDR - Starting Address for V or Cr */ #define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK) /*! @} */ /*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */ /*! @{ */ #define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU) #define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U) /*! WIDTH - Scaled Image Width (Pixels) */ #define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK) #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x3FFF0000U) #define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U) /*! HEIGHT - Scaled Image Height (Lines) */ #define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK) /*! @} */ /*! @name CHNL_FLOW_CTRL - Channel Flow Control */ /*! @{ */ #define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK (0xFFU) #define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT (0U) /*! FC_DENOM - Denominator Value of Fraction of Usable Bandwidth * 0b00000000..Invalid value (flow control disabled) */ #define ISI_CHNL_FLOW_CTRL_FC_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK) #define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK (0xFF0000U) #define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT (16U) /*! FC_NUMER - Numerator Value of Fraction of Usable Bandwidth * 0b00000000..Invalid value (flow control disabled) */ #define ISI_CHNL_FLOW_CTRL_FC_NUMER(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK) /*! @} */ /*! @name CHNL_Y_BUF1_XTND_ADDR - Channel Output Y-Buffer 1 Extended Address */ /*! @{ */ #define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_MASK (0xFFFU) #define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_SHIFT (0U) /*! Y1ADDR_MSB - Extended Address Most Significant Bits */ #define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_SHIFT)) & ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_MASK) /*! @} */ /*! @name CHNL_U_BUF1_XTND_ADDR - Channel Output U-Buffer 1 Extended Address */ /*! @{ */ #define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_MASK (0xFFFU) #define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_SHIFT (0U) /*! U1ADDR_MSB - Extended Address Most Significant Bits */ #define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_SHIFT)) & ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_MASK) /*! @} */ /*! @name CHNL_V_BUF1_XTND_ADDR - Channel Output V-Buffer 1 Extended Address */ /*! @{ */ #define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_MASK (0xFFFU) #define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_SHIFT (0U) /*! V1ADDR_MSB - Extended Address Most Significant Bits */ #define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_SHIFT)) & ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_MASK) /*! @} */ /*! @name CHNL_Y_BUF2_XTND_ADDR - Channel Output Y-Buffer 2 Extended Address */ /*! @{ */ #define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_MASK (0xFFFU) #define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_SHIFT (0U) /*! Y2ADDR_MSB - Extended Address Most Significant Bits */ #define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_SHIFT)) & ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_MASK) /*! @} */ /*! @name CHNL_U_BUF2_XTND_ADDR - Channel Output U-Buffer 2 Extended Address */ /*! @{ */ #define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_MASK (0xFFFU) #define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_SHIFT (0U) /*! U2ADDR_MSB - Extended Address Most Significant Bits */ #define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_SHIFT)) & ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_MASK) /*! @} */ /*! @name CHNL_V_BUF2_XTND_ADDR - Channel Output V-Buffer 2 Extended Address */ /*! @{ */ #define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_MASK (0xFFFU) #define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_SHIFT (0U) /*! V2ADDR_MSB - Extended Address Most Significant Bits */ #define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_SHIFT)) & ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_MASK) /*! @} */ /*! @name CHNL_IN_BUF_XTND_ADDR - Channel Input Buffer Extended Address */ /*! @{ */ #define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_MASK (0xFFFU) #define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_SHIFT (0U) /*! XADDR_MSB - Extended Address Most Significant Bits */ #define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_SHIFT)) & ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_MASK) /*! @} */ /*! @name PIXEL_DATA_ADDR_OFFSET - RAW32 Pixel Data Offset */ /*! @{ */ #define ISI_PIXEL_DATA_ADDR_OFFSET_PIXEL_OFFSET_MASK (0xFFFFFFFFU) #define ISI_PIXEL_DATA_ADDR_OFFSET_PIXEL_OFFSET_SHIFT (0U) /*! PIXEL_OFFSET - Pixel Data Offset */ #define ISI_PIXEL_DATA_ADDR_OFFSET_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_PIXEL_DATA_ADDR_OFFSET_PIXEL_OFFSET_SHIFT)) & ISI_PIXEL_DATA_ADDR_OFFSET_PIXEL_OFFSET_MASK) /*! @} */ /*! @name STAT_DATA_ADDR_OFFSET - RAW32 Statistics Data Offset */ /*! @{ */ #define ISI_STAT_DATA_ADDR_OFFSET_STAT_OFFSET_MASK (0xFFFFFFFFU) #define ISI_STAT_DATA_ADDR_OFFSET_STAT_OFFSET_SHIFT (0U) /*! STAT_OFFSET - Statistics Data Offset */ #define ISI_STAT_DATA_ADDR_OFFSET_STAT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_STAT_DATA_ADDR_OFFSET_STAT_OFFSET_SHIFT)) & ISI_STAT_DATA_ADDR_OFFSET_STAT_OFFSET_MASK) /*! @} */ /*! @name CHNL_IMG_CFG2 - Channel Image Configuration 2 */ /*! @{ */ #define ISI_CHNL_IMG_CFG2_WIDTH_MASK (0x1FFFU) #define ISI_CHNL_IMG_CFG2_WIDTH_SHIFT (0U) /*! WIDTH - Input Image Width (Pixels) */ #define ISI_CHNL_IMG_CFG2_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG2_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG2_WIDTH_MASK) /*! @} */ /*! @name CHNL_IMG_CFG3 - Channel Image Configuration 3 */ /*! @{ */ #define ISI_CHNL_IMG_CFG3_HEIGHT_MASK (0x1FFFU) #define ISI_CHNL_IMG_CFG3_HEIGHT_SHIFT (0U) /*! HEIGHT - Non-Pixel Data Height */ #define ISI_CHNL_IMG_CFG3_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG3_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG3_HEIGHT_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_MAX_SIZE_Y - Channel RGB or Luma (Y) Output Buffer Max Size */ /*! @{ */ #define ISI_CHNL_OUT_BUF_MAX_SIZE_Y_MS_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF_MAX_SIZE_Y_MS_SHIFT (0U) /*! MS - Max Size */ #define ISI_CHNL_OUT_BUF_MAX_SIZE_Y_MS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_MAX_SIZE_Y_MS_SHIFT)) & ISI_CHNL_OUT_BUF_MAX_SIZE_Y_MS_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_MAX_SIZE_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer Max Size */ /*! @{ */ #define ISI_CHNL_OUT_BUF_MAX_SIZE_U_MS_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF_MAX_SIZE_U_MS_SHIFT (0U) /*! MS - Max Size */ #define ISI_CHNL_OUT_BUF_MAX_SIZE_U_MS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_MAX_SIZE_U_MS_SHIFT)) & ISI_CHNL_OUT_BUF_MAX_SIZE_U_MS_MASK) /*! @} */ /*! @name CHNL_OUT_BUF_MAX_SIZE_V - Channel Chroma (V/Cr) Output Buffer Max Size */ /*! @{ */ #define ISI_CHNL_OUT_BUF_MAX_SIZE_V_MS_MASK (0xFFFFFFFFU) #define ISI_CHNL_OUT_BUF_MAX_SIZE_V_MS_SHIFT (0U) /*! MS - Max Size */ #define ISI_CHNL_OUT_BUF_MAX_SIZE_V_MS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_MAX_SIZE_V_MS_SHIFT)) & ISI_CHNL_OUT_BUF_MAX_SIZE_V_MS_MASK) /*! @} */ /*! * @} */ /* end of group ISI_Register_Masks */ /* ISI - Peripheral instance base addresses */ /** Peripheral CAMERA__ISI base address */ #define CAMERA__ISI_BASE (0x4AD50000u) /** Peripheral CAMERA__ISI base pointer */ #define CAMERA__ISI ((ISI_Type *)CAMERA__ISI_BASE) /** Array initializer of ISI peripheral base addresses */ #define ISI_BASE_ADDRS { CAMERA__ISI_BASE } /** Array initializer of ISI peripheral base pointers */ #define ISI_BASE_PTRS { CAMERA__ISI } /*! * @} */ /* end of group ISI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- JPEG_DEC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_Peripheral_Access_Layer JPEG_DEC Peripheral Access Layer * @{ */ /** JPEG_DEC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[52]; __IO uint32_t CTRL; /**< Control, offset: 0x34 */ } JPEG_DEC_Type; /* ---------------------------------------------------------------------------- -- JPEG_DEC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_Register_Masks JPEG_DEC Register Masks * @{ */ /*! @name CTRL - Control */ /*! @{ */ #define JPEG_DEC_CTRL_LP_MASK (0x1U) #define JPEG_DEC_CTRL_LP_SHIFT (0U) /*! LP - Low Power * 0b0..No effect * 0b1..Enable */ #define JPEG_DEC_CTRL_LP(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_LP_SHIFT)) & JPEG_DEC_CTRL_LP_MASK) #define JPEG_DEC_CTRL_SWR_MASK (0x2U) #define JPEG_DEC_CTRL_SWR_SHIFT (1U) /*! SWR - Soft Reset * 0b0..No effect * 0b1..Enable */ #define JPEG_DEC_CTRL_SWR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_SWR_SHIFT)) & JPEG_DEC_CTRL_SWR_MASK) #define JPEG_DEC_CTRL_GO_MASK (0x4U) #define JPEG_DEC_CTRL_GO_SHIFT (2U) /*! GO - Go * 0b0..No effect * 0b1..Enable */ #define JPEG_DEC_CTRL_GO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_CTRL_GO_SHIFT)) & JPEG_DEC_CTRL_GO_MASK) /*! @} */ /*! * @} */ /* end of group JPEG_DEC_Register_Masks */ /* JPEG_DEC - Peripheral instance base addresses */ /** Peripheral VPU__JPEG_DEC base address */ #define VPU__JPEG_DEC_BASE (0x4C500100u) /** Peripheral VPU__JPEG_DEC base pointer */ #define VPU__JPEG_DEC ((JPEG_DEC_Type *)VPU__JPEG_DEC_BASE) /** Array initializer of JPEG_DEC peripheral base addresses */ #define JPEG_DEC_BASE_ADDRS { VPU__JPEG_DEC_BASE } /** Array initializer of JPEG_DEC peripheral base pointers */ #define JPEG_DEC_BASE_PTRS { VPU__JPEG_DEC } /*! * @} */ /* end of group JPEG_DEC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- JPEG_DEC_WRAP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_WRAP_Peripheral_Access_Layer JPEG_DEC_WRAP Peripheral Access Layer * @{ */ /** JPEG_DEC_WRAP - Register Layout Typedef */ typedef struct { __IO uint32_t GLB_CTRL; /**< Global Control, offset: 0x0 */ __I uint32_t COM_STATUS; /**< Common Status, offset: 0x4 */ uint8_t RESERVED_0[12]; __IO uint32_t OUT_BUF_BASE0; /**< Output Image Frame Buffer0 Base Address, offset: 0x14 */ __IO uint32_t OUT_BUF_BASE1; /**< Output Image Frame Buffer1 Base Address, offset: 0x18 */ __IO uint32_t OUT_PITCH; /**< Image Output Buffer Pitch, offset: 0x1C */ __IO uint32_t STM_BUFBASE; /**< Input JPEG Stream Buffer Base Address, offset: 0x20 */ __IO uint32_t STM_BUFSIZE; /**< Input JPEG Stream Buffer Size, offset: 0x24 */ __IO uint32_t IMGSIZE; /**< Image Resolution, offset: 0x28 */ __IO uint32_t STM_CTRL; /**< Bit Stream and Switching Control, offset: 0x2C */ uint8_t RESERVED_1[65488]; struct { /* offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_STATUS; /**< Bit Stream Status, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_IRQ_EN; /**< Bit Stream Interrupt Enable, array offset: 0x10004, array step: 0x10000 */ __I uint32_t SLOT_BUF_PTR; /**< Bit Stream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */ __I uint32_t SLOT_CUR_DESCPT_PTR; /**< Current Descriptors, array offset: 0x1000C, array step: 0x10000 */ __IO uint32_t SLOT_NXT_DESCPT_PTR; /**< Next Descriptors, array offset: 0x10010, array step: 0x10000 */ uint8_t RESERVED_0[65516]; } BITSTRM_SLOT_REGS[4]; } JPEG_DEC_WRAP_Type; /* ---------------------------------------------------------------------------- -- JPEG_DEC_WRAP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup JPEG_DEC_WRAP_Register_Masks JPEG_DEC_WRAP Register Masks * @{ */ /*! @name GLB_CTRL - Global Control */ /*! @{ */ #define JPEG_DEC_WRAP_GLB_CTRL_JPG_DEC_EN_MASK (0x1U) #define JPEG_DEC_WRAP_GLB_CTRL_JPG_DEC_EN_SHIFT (0U) /*! JPG_DEC_EN - JPEGDEC and JPGDECWRP Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_GLB_CTRL_JPG_DEC_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_GLB_CTRL_JPG_DEC_EN_SHIFT)) & JPEG_DEC_WRAP_GLB_CTRL_JPG_DEC_EN_MASK) #define JPEG_DEC_WRAP_GLB_CTRL_SFTRST_MASK (0x2U) #define JPEG_DEC_WRAP_GLB_CTRL_SFTRST_SHIFT (1U) /*! SFTRST - Engine Soft Reset * 0b0..No effect * 0b1..Performs a soft reset. */ #define JPEG_DEC_WRAP_GLB_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_GLB_CTRL_SFTRST_SHIFT)) & JPEG_DEC_WRAP_GLB_CTRL_SFTRST_MASK) #define JPEG_DEC_WRAP_GLB_CTRL_DEC_GO_MASK (0x4U) #define JPEG_DEC_WRAP_GLB_CTRL_DEC_GO_SHIFT (2U) /*! DEC_GO - Start Decoding * 0b0..Do not start decoding manually. * 0b1..Starts decoding manually. */ #define JPEG_DEC_WRAP_GLB_CTRL_DEC_GO(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_GLB_CTRL_DEC_GO_SHIFT)) & JPEG_DEC_WRAP_GLB_CTRL_DEC_GO_MASK) #define JPEG_DEC_WRAP_GLB_CTRL_L_ENDIAN_MASK (0x8U) #define JPEG_DEC_WRAP_GLB_CTRL_L_ENDIAN_SHIFT (3U) /*! L_ENDIAN - Little-Endian Enable * 0b0..Big-Endian * 0b1..Little-Endian */ #define JPEG_DEC_WRAP_GLB_CTRL_L_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_GLB_CTRL_L_ENDIAN_SHIFT)) & JPEG_DEC_WRAP_GLB_CTRL_L_ENDIAN_MASK) #define JPEG_DEC_WRAP_GLB_CTRL_SLOT_EN_MASK (0xF0U) #define JPEG_DEC_WRAP_GLB_CTRL_SLOT_EN_SHIFT (4U) /*! SLOT_EN - Slots Enable * 0b0000..Disables all slots. * 0b0001..Enables SLOT0. * 0b0010..Enables SLOT1. * 0b0100..Enables SLOT2. * 0b1000..Enables SLOT3. * *.. */ #define JPEG_DEC_WRAP_GLB_CTRL_SLOT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_GLB_CTRL_SLOT_EN_SHIFT)) & JPEG_DEC_WRAP_GLB_CTRL_SLOT_EN_MASK) /*! @} */ /*! @name COM_STATUS - Common Status */ /*! @{ */ #define JPEG_DEC_WRAP_COM_STATUS_CUR_SLOT_MASK (0x60000000U) #define JPEG_DEC_WRAP_COM_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current Slot */ #define JPEG_DEC_WRAP_COM_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_COM_STATUS_CUR_SLOT_SHIFT)) & JPEG_DEC_WRAP_COM_STATUS_CUR_SLOT_MASK) #define JPEG_DEC_WRAP_COM_STATUS_DEC_ONGOING_MASK (0x80000000U) #define JPEG_DEC_WRAP_COM_STATUS_DEC_ONGOING_SHIFT (31U) /*! DEC_ONGOING - Decoding Ongoing */ #define JPEG_DEC_WRAP_COM_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_COM_STATUS_DEC_ONGOING_SHIFT)) & JPEG_DEC_WRAP_COM_STATUS_DEC_ONGOING_MASK) /*! @} */ /*! @name OUT_BUF_BASE0 - Output Image Frame Buffer0 Base Address */ /*! @{ */ #define JPEG_DEC_WRAP_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK (0xFFFFFFF0U) #define JPEG_DEC_WRAP_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT (4U) /*! OUT_BUF_BASE0 - Pixel Frame Buffer0 Base */ #define JPEG_DEC_WRAP_OUT_BUF_BASE0_OUT_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT)) & JPEG_DEC_WRAP_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK) /*! @} */ /*! @name OUT_BUF_BASE1 - Output Image Frame Buffer1 Base Address */ /*! @{ */ #define JPEG_DEC_WRAP_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK (0xFFFFFFF0U) #define JPEG_DEC_WRAP_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT (4U) /*! OUT_BUF_BASE1 - Pixel Frame Buffer1 Base */ #define JPEG_DEC_WRAP_OUT_BUF_BASE1_OUT_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT)) & JPEG_DEC_WRAP_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK) /*! @} */ /*! @name OUT_PITCH - Image Output Buffer Pitch */ /*! @{ */ #define JPEG_DEC_WRAP_OUT_PITCH_OUT_PITCH_MASK (0xFFFFU) #define JPEG_DEC_WRAP_OUT_PITCH_OUT_PITCH_SHIFT (0U) /*! OUT_PITCH - Output Image Pitch */ #define JPEG_DEC_WRAP_OUT_PITCH_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_OUT_PITCH_OUT_PITCH_SHIFT)) & JPEG_DEC_WRAP_OUT_PITCH_OUT_PITCH_MASK) /*! @} */ /*! @name STM_BUFBASE - Input JPEG Stream Buffer Base Address */ /*! @{ */ #define JPEG_DEC_WRAP_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U) #define JPEG_DEC_WRAP_STM_BUFBASE_STM_BUFBASE_SHIFT (4U) /*! STM_BUFBASE - Bit Stream Buffer Base */ #define JPEG_DEC_WRAP_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPEG_DEC_WRAP_STM_BUFBASE_STM_BUFBASE_MASK) /*! @} */ /*! @name STM_BUFSIZE - Input JPEG Stream Buffer Size */ /*! @{ */ #define JPEG_DEC_WRAP_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U) #define JPEG_DEC_WRAP_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U) /*! STM_BUFSIZE - Bit Stream Buffer Size */ #define JPEG_DEC_WRAP_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPEG_DEC_WRAP_STM_BUFSIZE_STM_BUFSIZE_MASK) /*! @} */ /*! @name IMGSIZE - Image Resolution */ /*! @{ */ #define JPEG_DEC_WRAP_IMGSIZE_IMG_HEIGHT_MASK (0x3FFFU) #define JPEG_DEC_WRAP_IMGSIZE_IMG_HEIGHT_SHIFT (0U) /*! IMG_HEIGHT - Image Height */ #define JPEG_DEC_WRAP_IMGSIZE_IMG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_IMGSIZE_IMG_HEIGHT_SHIFT)) & JPEG_DEC_WRAP_IMGSIZE_IMG_HEIGHT_MASK) #define JPEG_DEC_WRAP_IMGSIZE_IMG_WIDTH_MASK (0x3FFF0000U) #define JPEG_DEC_WRAP_IMGSIZE_IMG_WIDTH_SHIFT (16U) /*! IMG_WIDTH - Image Width */ #define JPEG_DEC_WRAP_IMGSIZE_IMG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_IMGSIZE_IMG_WIDTH_SHIFT)) & JPEG_DEC_WRAP_IMGSIZE_IMG_WIDTH_MASK) /*! @} */ /*! @name STM_CTRL - Bit Stream and Switching Control */ /*! @{ */ #define JPEG_DEC_WRAP_STM_CTRL_PIXEL_PRECISION_MASK (0x4U) #define JPEG_DEC_WRAP_STM_CTRL_PIXEL_PRECISION_SHIFT (2U) /*! PIXEL_PRECISION - Pixel Precision * 0b0..8-bit * 0b1..12-bit */ #define JPEG_DEC_WRAP_STM_CTRL_PIXEL_PRECISION(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_STM_CTRL_PIXEL_PRECISION_SHIFT)) & JPEG_DEC_WRAP_STM_CTRL_PIXEL_PRECISION_MASK) #define JPEG_DEC_WRAP_STM_CTRL_IMAGE_FORMAT_MASK (0x78U) #define JPEG_DEC_WRAP_STM_CTRL_IMAGE_FORMAT_SHIFT (3U) /*! IMAGE_FORMAT - Image Format * 0b0000..YUV420 (2-planar, Y at the first planar, and UV at the second planar) * 0b0001..YUV422 (1-planar in the YUYV sequence) * 0b0010..RGB (BGRBGR packed format) * 0b0011..YUV444 (first planar in the YUVYUV sequence) * 0b0100..Gray (Y8 or Y12) or single component * 0b0101.. * 0b0110..ARGB */ #define JPEG_DEC_WRAP_STM_CTRL_IMAGE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_STM_CTRL_IMAGE_FORMAT_SHIFT)) & JPEG_DEC_WRAP_STM_CTRL_IMAGE_FORMAT_MASK) #define JPEG_DEC_WRAP_STM_CTRL_BITBUF_PTR_CLR_MASK (0x80U) #define JPEG_DEC_WRAP_STM_CTRL_BITBUF_PTR_CLR_SHIFT (7U) /*! BITBUF_PTR_CLR - Bit Buffer Pointer Clear * 0b0..Restores the bit stream buffer pointer from the save pointer. * 0b1..Clears the bit stream buffer pointer from the save pointer. */ #define JPEG_DEC_WRAP_STM_CTRL_BITBUF_PTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & JPEG_DEC_WRAP_STM_CTRL_BITBUF_PTR_CLR_MASK) #define JPEG_DEC_WRAP_STM_CTRL_AUTO_START_MASK (0x100U) #define JPEG_DEC_WRAP_STM_CTRL_AUTO_START_SHIFT (8U) /*! AUTO_START - Auto Start * 0b0..Do not write 1 to CTRL[GO] in JPEGDEC. * 0b1..Writes 1 to CTRL[GO] in JPEGDEC. */ #define JPEG_DEC_WRAP_STM_CTRL_AUTO_START(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_STM_CTRL_AUTO_START_SHIFT)) & JPEG_DEC_WRAP_STM_CTRL_AUTO_START_MASK) /*! @} */ /*! @name SLOT_STATUS - Bit Stream Status */ /*! @{ */ #define JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_HALF_MASK (0x1U) #define JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_HALF_SHIFT (0U) /*! STMBUF_HALF - Stream Buffer Half Flag * 0b0..The bit stream buffer pointer for the current slot has not passed half of the buffer size. * 0b1..The bit stream buffer pointer for the current slot passed half of the buffer size. * 0b0..No effect * 0b1..Clears the flag. */ #define JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_HALF_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_RTND_MASK (0x2U) #define JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_RTND_SHIFT (1U) /*! STMBUF_RTND - Stream Buffer Returned Flag * 0b0..The bit stream buffer pointer for the current slot has not passed the top mark of the buffer. * 0b1..The bit stream buffer pointer for the current slot passed the top mark of the buffer. * 0b0..No effect * 0b1..Clears the flag. */ #define JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_STMBUF_RTND_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_SWITCHED_IN_MASK (0x4U) #define JPEG_DEC_WRAP_SLOT_STATUS_SWITCHED_IN_SHIFT (2U) /*! SWITCHED_IN - Switched In Flag * 0b0..The current slot is not switched in during context switching. * 0b1..The current slot is switched in during context switching. * 0b0..No effect * 0b1..Clears the flag. */ #define JPEG_DEC_WRAP_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_SWITCHED_IN_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_FRMDONE_MASK (0x8U) #define JPEG_DEC_WRAP_SLOT_STATUS_FRMDONE_SHIFT (3U) /*! FRMDONE - Frame Done Flag * 0b0..Decoding is not completed. * 0b1..Decoding is completed. * 0b0..No effect * 0b1..Clears the flag. */ #define JPEG_DEC_WRAP_SLOT_STATUS_FRMDONE(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_FRMDONE_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_FRMDONE_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_DECERR_MASK (0x100U) #define JPEG_DEC_WRAP_SLOT_STATUS_DECERR_SHIFT (8U) /*! DECERR - Decoding Error Flag * 0b0..No decoding error occurred. * 0b1..A decoding error occurred. * 0b0..No effect * 0b1..Clears the flag. */ #define JPEG_DEC_WRAP_SLOT_STATUS_DECERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_DECERR_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_DECERR_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_DES_RD_ERR_MASK (0x200U) #define JPEG_DEC_WRAP_SLOT_STATUS_DES_RD_ERR_SHIFT (9U) /*! DES_RD_ERR - Descriptor Read Error Flag * 0b0..No descriptor read error occurred. * 0b1..A descriptor read error occurred. * 0b0..No effect * 0b1..Clears the flag. */ #define JPEG_DEC_WRAP_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_DES_RD_ERR_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_BIT_RD_ERR_MASK (0x400U) #define JPEG_DEC_WRAP_SLOT_STATUS_BIT_RD_ERR_SHIFT (10U) /*! BIT_RD_ERR - Bit Read Error Flag * 0b0..No bit read error occurred. * 0b1..A bit read error occurred. * 0b0..No effect * 0b1..Clear the flag */ #define JPEG_DEC_WRAP_SLOT_STATUS_BIT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_BIT_RD_ERR_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_BIT_RD_ERR_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_PIXEL_WT_ERR_MASK (0x800U) #define JPEG_DEC_WRAP_SLOT_STATUS_PIXEL_WT_ERR_SHIFT (11U) /*! PIXEL_WT_ERR - Pixel Write Error Flag * 0b0..No pixel write error occurred. * 0b1..A pixel write error occurred. * 0b0..No effect * 0b1..Clears the flag. */ #define JPEG_DEC_WRAP_SLOT_STATUS_PIXEL_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_PIXEL_WT_ERR_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_PIXEL_WT_ERR_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U) #define JPEG_DEC_WRAP_SLOT_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current Slot */ #define JPEG_DEC_WRAP_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_CUR_SLOT_MASK) #define JPEG_DEC_WRAP_SLOT_STATUS_DEC_ONGOING_MASK (0x80000000U) #define JPEG_DEC_WRAP_SLOT_STATUS_DEC_ONGOING_SHIFT (31U) /*! DEC_ONGOING - Decoding Ongoing * 0b0..Paused or stopped * 0b1..Ongoing */ #define JPEG_DEC_WRAP_SLOT_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_STATUS_DEC_ONGOING_SHIFT)) & JPEG_DEC_WRAP_SLOT_STATUS_DEC_ONGOING_MASK) /*! @} */ /* The count of JPEG_DEC_WRAP_SLOT_STATUS */ #define JPEG_DEC_WRAP_SLOT_STATUS_COUNT (4U) /*! @name SLOT_IRQ_EN - Bit Stream Interrupt Enable */ /*! @{ */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U) /*! STMBUF_HALF_IRQ_EN - Stream Buffer Half Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U) /*! STMBUF_RTND_IRQ_EN - Stream Buffer Returned Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK (0x4U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT (2U) /*! SWITCHED_IN_IRQ_EN - Switched In Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK (0x8U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U) /*! FRMDONE_IRQ_EN - Frame Done Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_DECERR_IRQ_EN_MASK (0x100U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_DECERR_IRQ_EN_SHIFT (8U) /*! DECERR_IRQ_EN - Decoding Error Status Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_DECERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_DECERR_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_DECERR_IRQ_EN_MASK) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK (0x200U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT (9U) /*! DES_RD_ERR_IRQ_EN - Descriptor Read Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_MASK (0x400U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_SHIFT (10U) /*! BIT_RD_ERR_IRQ_EN - Bit Read Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_MASK) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_MASK (0x800U) #define JPEG_DEC_WRAP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_SHIFT (11U) /*! PIXEL_WT_ERR_IRQ_EN - Pixel Write Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_MASK) /*! @} */ /* The count of JPEG_DEC_WRAP_SLOT_IRQ_EN */ #define JPEG_DEC_WRAP_SLOT_IRQ_EN_COUNT (4U) /*! @name SLOT_BUF_PTR - Bit Stream Buffer Pointer */ /*! @{ */ #define JPEG_DEC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_MASK (0xFFFFFFFFU) #define JPEG_DEC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_SHIFT (0U) /*! STMBUF_PTR - Stream Buffer Pointer */ #define JPEG_DEC_WRAP_SLOT_BUF_PTR_STMBUF_PTR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_SHIFT)) & JPEG_DEC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_MASK) /*! @} */ /* The count of JPEG_DEC_WRAP_SLOT_BUF_PTR */ #define JPEG_DEC_WRAP_SLOT_BUF_PTR_COUNT (4U) /*! @name SLOT_CUR_DESCPT_PTR - Current Descriptors */ /*! @{ */ #define JPEG_DEC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU) #define JPEG_DEC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U) /*! CUR_DESCPT_PRT - Current Decoding Descriptor Pointer */ #define JPEG_DEC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPEG_DEC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK) /*! @} */ /* The count of JPEG_DEC_WRAP_SLOT_CUR_DESCPT_PTR */ #define JPEG_DEC_WRAP_SLOT_CUR_DESCPT_PTR_COUNT (4U) /*! @name SLOT_NXT_DESCPT_PTR - Next Descriptors */ /*! @{ */ #define JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK (0x1U) #define JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT (0U) /*! NXT_DESCPT_EN - Next Stream Descriptor Pointer Enable * 0b0..Disable * 0b1..Enable */ #define JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT)) & JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK) #define JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_MASK (0xFFFFFFFCU) #define JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_SHIFT (2U) /*! NXT_DESCPT_PTR - Next Descriptor Pointer */ #define JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR(x) (((uint32_t)(((uint32_t)(x)) << JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_SHIFT)) & JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_MASK) /*! @} */ /* The count of JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR */ #define JPEG_DEC_WRAP_SLOT_NXT_DESCPT_PTR_COUNT (4U) /*! * @} */ /* end of group JPEG_DEC_WRAP_Register_Masks */ /* JPEG_DEC_WRAP - Peripheral instance base addresses */ /** Peripheral VPU__JPEG_DEC_WRAP base address */ #define VPU__JPEG_DEC_WRAP_BASE (0x4C500000u) /** Peripheral VPU__JPEG_DEC_WRAP base pointer */ #define VPU__JPEG_DEC_WRAP ((JPEG_DEC_WRAP_Type *)VPU__JPEG_DEC_WRAP_BASE) /** Array initializer of JPEG_DEC_WRAP peripheral base addresses */ #define JPEG_DEC_WRAP_BASE_ADDRS { VPU__JPEG_DEC_WRAP_BASE } /** Array initializer of JPEG_DEC_WRAP peripheral base pointers */ #define JPEG_DEC_WRAP_BASE_PTRS { VPU__JPEG_DEC_WRAP } /*! * @} */ /* end of group JPEG_DEC_WRAP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LDB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LDB_Peripheral_Access_Layer LDB Peripheral Access Layer * @{ */ /** LDB - Register Layout Typedef */ typedef struct { __IO uint32_t LVDS_PHY_CLOCK_CONTROL; /**< LVDS PHY Clock Control, offset: 0x0 */ __IO uint32_t PIXEL_MAPPER_CONTROL; /**< Pixel mapper control, offset: 0x4 */ __IO uint32_t LVDS0_CONTROL; /**< LVDS0 control, offset: 0x8 */ __IO uint32_t LVDS1_CONTROL; /**< LVDS1 Control, offset: 0xC */ } LDB_Type; /* ---------------------------------------------------------------------------- -- LDB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LDB_Register_Masks LDB Register Masks * @{ */ /*! @name LVDS_PHY_CLOCK_CONTROL - LVDS PHY Clock Control */ /*! @{ */ #define LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PHY_DIV_MASK (0x1U) #define LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PHY_DIV_SHIFT (0U) /*! LVDS_PHY_DIV - Defines the PHY clock divider ratio * 0b1..PHY clock frequency is equal to PLL clock frequency / 2 * 0b0..PHY clock frequency is equal to PLL clock frequency */ #define LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PHY_DIV(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PHY_DIV_SHIFT)) & LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PHY_DIV_MASK) #define LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch0_clock_Ctrl_MASK (0x2U) #define LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch0_clock_Ctrl_SHIFT (1U) /*! Serializer_Ch0_clock_Ctrl - LVDS serializer channel 0 clock gate control * 0b0..LVDS serializer channel 0 are clocked * 0b1..LVDS serializer channel 0 are not clocked */ #define LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch0_clock_Ctrl(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch0_clock_Ctrl_SHIFT)) & LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch0_clock_Ctrl_MASK) #define LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch1_clock_Ctrl_MASK (0x4U) #define LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch1_clock_Ctrl_SHIFT (2U) /*! Serializer_Ch1_clock_Ctrl - LVDS serializer channel 1 clock gate control * 0b1..LVDS serializer channel 1 are not clocked * 0b0..LVDS serializer channel 1 are clocked */ #define LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch1_clock_Ctrl(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch1_clock_Ctrl_SHIFT)) & LDB_LVDS_PHY_CLOCK_CONTROL_Serializer_Ch1_clock_Ctrl_MASK) #define LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di0_clock_Ctrl_MASK (0x8U) #define LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di0_clock_Ctrl_SHIFT (3U) /*! PixelMapper_Di0_clock_Ctrl - LVDS pixel mapper Di0 clock gate control * 0b0..LVDS pixel mapper Di0 are clocked * 0b1..LVDS pixel mapper Di0 are not clocked */ #define LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di0_clock_Ctrl(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di0_clock_Ctrl_SHIFT)) & LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di0_clock_Ctrl_MASK) #define LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di1_clock_Ctrl_MASK (0x10U) #define LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di1_clock_Ctrl_SHIFT (4U) /*! PixelMapper_Di1_clock_Ctrl - LVDS pixel mapper Di1 clock gate control * 0b0..LVDS pixel mapper Di1 are clocked * 0b1..LVDS pixel mapper Di1 are not clocked */ #define LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di1_clock_Ctrl(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di1_clock_Ctrl_SHIFT)) & LDB_LVDS_PHY_CLOCK_CONTROL_PixelMapper_Di1_clock_Ctrl_MASK) #define LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PLL_clock_ctrl_MASK (0x20U) #define LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PLL_clock_ctrl_SHIFT (5U) /*! LVDS_PLL_clock_ctrl - Control the clock gating logic of the LVDS PLL input clock * 0b1..LVDS PLL input clock are not clocked * 0b0..LVDS PLL input clock are clocked */ #define LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PLL_clock_ctrl(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PLL_clock_ctrl_SHIFT)) & LDB_LVDS_PHY_CLOCK_CONTROL_LVDS_PLL_clock_ctrl_MASK) /*! @} */ /*! @name PIXEL_MAPPER_CONTROL - Pixel mapper control */ /*! @{ */ #define LDB_PIXEL_MAPPER_CONTROL_CH0_MODE_MASK (0x3U) #define LDB_PIXEL_MAPPER_CONTROL_CH0_MODE_SHIFT (0U) /*! CH0_MODE - LVDS channel 0 operation mode * 0b01..Channel enabled, routed to DI0 * 0b00..Channel disabled * 0b10..Channel disabled * 0b11..Channel enabled, routed to DI1 */ #define LDB_PIXEL_MAPPER_CONTROL_CH0_MODE(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH0_MODE_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH0_MODE_MASK) #define LDB_PIXEL_MAPPER_CONTROL_CH1_MODE_MASK (0xCU) #define LDB_PIXEL_MAPPER_CONTROL_CH1_MODE_SHIFT (2U) /*! CH1_MODE - LVDS channel 1 operation mode * 0b01..Channel enabled, routed to DI0 * 0b00..Channel disabled * 0b10..Channel disabled * 0b11..Channel enabled, routed to DI1 */ #define LDB_PIXEL_MAPPER_CONTROL_CH1_MODE(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH1_MODE_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH1_MODE_MASK) #define LDB_PIXEL_MAPPER_CONTROL_SPLIT_MODE_MASK (0x10U) #define LDB_PIXEL_MAPPER_CONTROL_SPLIT_MODE_SHIFT (4U) /*! SPLIT_MODE - Enable split mode * 0b1..Split mode is enabled. In this mode both channels should be enabled and working with the same DI. * 0b0..Split mode is disabled. */ #define LDB_PIXEL_MAPPER_CONTROL_SPLIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_SPLIT_MODE_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_SPLIT_MODE_MASK) #define LDB_PIXEL_MAPPER_CONTROL_CH0_DATA_WIDTH_MASK (0x20U) #define LDB_PIXEL_MAPPER_CONTROL_CH0_DATA_WIDTH_SHIFT (5U) /*! CH0_DATA_WIDTH - Data width for LVDS channel 0 * 0b0..Data width is 18 bits wide * 0b1..Data width is 24 bits wide */ #define LDB_PIXEL_MAPPER_CONTROL_CH0_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH0_DATA_WIDTH_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH0_DATA_WIDTH_MASK) #define LDB_PIXEL_MAPPER_CONTROL_CH0_BIT_MAPPING_MASK (0x40U) #define LDB_PIXEL_MAPPER_CONTROL_CH0_BIT_MAPPING_SHIFT (6U) /*! CH0_BIT_MAPPING - Data mapping for LVDS channel 0 * 0b1..Use JEIDA standard * 0b0..Use SPWG standard */ #define LDB_PIXEL_MAPPER_CONTROL_CH0_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH0_BIT_MAPPING_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH0_BIT_MAPPING_MASK) #define LDB_PIXEL_MAPPER_CONTROL_CH1_DATA_WIDTH_MASK (0x80U) #define LDB_PIXEL_MAPPER_CONTROL_CH1_DATA_WIDTH_SHIFT (7U) /*! CH1_DATA_WIDTH - Data width for LVDS channel 1 * 0b1..Data width is 24 bits wide * 0b0..Data width is 18 bits wide */ #define LDB_PIXEL_MAPPER_CONTROL_CH1_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH1_DATA_WIDTH_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH1_DATA_WIDTH_MASK) #define LDB_PIXEL_MAPPER_CONTROL_CH1_BIT_MAPPING_MASK (0x100U) #define LDB_PIXEL_MAPPER_CONTROL_CH1_BIT_MAPPING_SHIFT (8U) /*! CH1_BIT_MAPPING - Data mapping for LVDS channel 1 * 0b0..Use SPWG standard * 0b1..Use JEIDA standard */ #define LDB_PIXEL_MAPPER_CONTROL_CH1_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH1_BIT_MAPPING_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH1_BIT_MAPPING_MASK) #define LDB_PIXEL_MAPPER_CONTROL_DI0_VSYNC_POLARITY_MASK (0x200U) #define LDB_PIXEL_MAPPER_CONTROL_DI0_VSYNC_POLARITY_SHIFT (9U) /*! DI0_VSYNC_POLARITY - VSYNC polarity select for DI0 * 0b1..VSYNC is active low * 0b0..VSYNC is active high */ #define LDB_PIXEL_MAPPER_CONTROL_DI0_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_DI0_VSYNC_POLARITY_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_DI0_VSYNC_POLARITY_MASK) #define LDB_PIXEL_MAPPER_CONTROL_DI1_VSYNC_POLARITY_MASK (0x400U) #define LDB_PIXEL_MAPPER_CONTROL_DI1_VSYNC_POLARITY_SHIFT (10U) /*! DI1_VSYNC_POLARITY - VSYNC polarity select for DI1 * 0b0..VSYNC is active high * 0b1..VSYNC is active low */ #define LDB_PIXEL_MAPPER_CONTROL_DI1_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_DI1_VSYNC_POLARITY_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_DI1_VSYNC_POLARITY_MASK) #define LDB_PIXEL_MAPPER_CONTROL_CH0_ASYNC_FIFO_RESET_MASK (0x800U) #define LDB_PIXEL_MAPPER_CONTROL_CH0_ASYNC_FIFO_RESET_SHIFT (11U) /*! CH0_ASYNC_FIFO_RESET - LVDS channel 0 async FIFO software reset * 0b1..Software reset * 0b0..No action */ #define LDB_PIXEL_MAPPER_CONTROL_CH0_ASYNC_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH0_ASYNC_FIFO_RESET_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH0_ASYNC_FIFO_RESET_MASK) #define LDB_PIXEL_MAPPER_CONTROL_CH1_ASYNC_FIFO_RESET_MASK (0x1000U) #define LDB_PIXEL_MAPPER_CONTROL_CH1_ASYNC_FIFO_RESET_SHIFT (12U) /*! CH1_ASYNC_FIFO_RESET - LVDS channel 1 async FIFO software reset * 0b0..No action * 0b1..Software reset */ #define LDB_PIXEL_MAPPER_CONTROL_CH1_ASYNC_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_CH1_ASYNC_FIFO_RESET_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_CH1_ASYNC_FIFO_RESET_MASK) #define LDB_PIXEL_MAPPER_CONTROL_BGREF_RRMODE_MASK (0x8000U) #define LDB_PIXEL_MAPPER_CONTROL_BGREF_RRMODE_SHIFT (15U) /*! BGREF_RRMODE - Select reference resistor for bandgap * 0b0..External resistor of 29kOhm is selected * 0b1..Internal resistor is selected */ #define LDB_PIXEL_MAPPER_CONTROL_BGREF_RRMODE(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_BGREF_RRMODE_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_BGREF_RRMODE_MASK) #define LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_ENABLE_MASK (0x1000000U) #define LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_ENABLE_SHIFT (24U) /*! ASYNC_FIFO_ENABLE - Channel 0 and channel 1 async FIFO enable * 0b0..Disable * 0b1..Enable async FIFO to buffer RGB data */ #define LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_ENABLE_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_ENABLE_MASK) #define LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_THRESHOLD_MASK (0xE000000U) #define LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_THRESHOLD_SHIFT (25U) /*! ASYNC_FIFO_THRESHOLD - Reset value for the LDB counter which determines when the shift registers are loaded with data. */ #define LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_THRESHOLD_SHIFT)) & LDB_PIXEL_MAPPER_CONTROL_ASYNC_FIFO_THRESHOLD_MASK) /*! @} */ /*! @name LVDS0_CONTROL - LVDS0 control */ /*! @{ */ #define LDB_LVDS0_CONTROL_CH0_EN_MASK (0x1U) #define LDB_LVDS0_CONTROL_CH0_EN_SHIFT (0U) /*! CH0_EN - Channel 0 enable * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS0_CONTROL_CH0_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_CH0_EN_SHIFT)) & LDB_LVDS0_CONTROL_CH0_EN_MASK) #define LDB_LVDS0_CONTROL_LVDS_EN_MASK (0x2U) #define LDB_LVDS0_CONTROL_LVDS_EN_SHIFT (1U) /*! LVDS_EN - LVDS PHY enable * 0b0..Enable. LVDS function is normal. * 0b1..Disable */ #define LDB_LVDS0_CONTROL_LVDS_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_LVDS_EN_SHIFT)) & LDB_LVDS0_CONTROL_LVDS_EN_MASK) #define LDB_LVDS0_CONTROL_BG_EN_MASK (0x4U) #define LDB_LVDS0_CONTROL_BG_EN_SHIFT (2U) /*! BG_EN - Bandgap enable * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS0_CONTROL_BG_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_BG_EN_SHIFT)) & LDB_LVDS0_CONTROL_BG_EN_MASK) #define LDB_LVDS0_CONTROL_HS_EN_MASK (0x8U) #define LDB_LVDS0_CONTROL_HS_EN_SHIFT (3U) /*! HS_EN - Enable 100 ohm termination in the chip enable which also doubles power dissipation. * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS0_CONTROL_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_HS_EN_SHIFT)) & LDB_LVDS0_CONTROL_HS_EN_MASK) #define LDB_LVDS0_CONTROL_PRE_EMPH_EN_MASK (0x10U) #define LDB_LVDS0_CONTROL_PRE_EMPH_EN_SHIFT (4U) /*! PRE_EMPH_EN - Enable pre-emphasis * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS0_CONTROL_PRE_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_PRE_EMPH_EN_SHIFT)) & LDB_LVDS0_CONTROL_PRE_EMPH_EN_MASK) #define LDB_LVDS0_CONTROL_PRE_EMPH_ADJ_MASK (0xE0U) #define LDB_LVDS0_CONTROL_PRE_EMPH_ADJ_SHIFT (5U) /*! PRE_EMPH_ADJ - Pre-emphasis adjustment. */ #define LDB_LVDS0_CONTROL_PRE_EMPH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_PRE_EMPH_ADJ_SHIFT)) & LDB_LVDS0_CONTROL_PRE_EMPH_ADJ_MASK) #define LDB_LVDS0_CONTROL_CM_ADJ_MASK (0x700U) #define LDB_LVDS0_CONTROL_CM_ADJ_SHIFT (8U) /*! CM_ADJ - Output common mode (Vos) adjustment */ #define LDB_LVDS0_CONTROL_CM_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_CM_ADJ_SHIFT)) & LDB_LVDS0_CONTROL_CM_ADJ_MASK) #define LDB_LVDS0_CONTROL_CC_ADJ_MASK (0x3800U) #define LDB_LVDS0_CONTROL_CC_ADJ_SHIFT (11U) /*! CC_ADJ - Output current adjustment */ #define LDB_LVDS0_CONTROL_CC_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_CC_ADJ_SHIFT)) & LDB_LVDS0_CONTROL_CC_ADJ_MASK) #define LDB_LVDS0_CONTROL_SLEW_ADJ_MASK (0x1C000U) #define LDB_LVDS0_CONTROL_SLEW_ADJ_SHIFT (14U) /*! SLEW_ADJ - Output transition time adjustment */ #define LDB_LVDS0_CONTROL_SLEW_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_SLEW_ADJ_SHIFT)) & LDB_LVDS0_CONTROL_SLEW_ADJ_MASK) #define LDB_LVDS0_CONTROL_VBG_ADJ_MASK (0xE0000U) #define LDB_LVDS0_CONTROL_VBG_ADJ_SHIFT (17U) /*! VBG_ADJ - Bandgap adjustment */ #define LDB_LVDS0_CONTROL_VBG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_VBG_ADJ_SHIFT)) & LDB_LVDS0_CONTROL_VBG_ADJ_MASK) #define LDB_LVDS0_CONTROL_TEST_DIV4_MASK (0x100000U) #define LDB_LVDS0_CONTROL_TEST_DIV4_SHIFT (20U) /*! TEST_DIV4 - Divide the input signal/clock by 4. * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS0_CONTROL_TEST_DIV4(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_TEST_DIV4_SHIFT)) & LDB_LVDS0_CONTROL_TEST_DIV4_MASK) #define LDB_LVDS0_CONTROL_TEST_EN_MASK (0x200000U) #define LDB_LVDS0_CONTROL_TEST_EN_SHIFT (21U) /*! TEST_EN - Test enable * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS0_CONTROL_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_TEST_EN_SHIFT)) & LDB_LVDS0_CONTROL_TEST_EN_MASK) #define LDB_LVDS0_CONTROL_TEST_MUX_SRC_MASK (0xC00000U) #define LDB_LVDS0_CONTROL_TEST_MUX_SRC_SHIFT (22U) /*! TEST_MUX_SRC - Select which signals to test * 0b11..LVDS0_D3_P/N * 0b10..LVDS0_D2_P/N * 0b00..LVDS0_D0_P/N * 0b01..LVDS0_D1_P/N */ #define LDB_LVDS0_CONTROL_TEST_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_TEST_MUX_SRC_SHIFT)) & LDB_LVDS0_CONTROL_TEST_MUX_SRC_MASK) #define LDB_LVDS0_CONTROL_TEST_RANDOM_NUM_EN_MASK (0x1000000U) #define LDB_LVDS0_CONTROL_TEST_RANDOM_NUM_EN_SHIFT (24U) /*! TEST_RANDOM_NUM_EN - Random number generator enable * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS0_CONTROL_TEST_RANDOM_NUM_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_TEST_RANDOM_NUM_EN_SHIFT)) & LDB_LVDS0_CONTROL_TEST_RANDOM_NUM_EN_MASK) #define LDB_LVDS0_CONTROL_SPARE_IN_MASK (0xE000000U) #define LDB_LVDS0_CONTROL_SPARE_IN_SHIFT (25U) /*! SPARE_IN - Spare ports */ #define LDB_LVDS0_CONTROL_SPARE_IN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS0_CONTROL_SPARE_IN_SHIFT)) & LDB_LVDS0_CONTROL_SPARE_IN_MASK) /*! @} */ /*! @name LVDS1_CONTROL - LVDS1 Control */ /*! @{ */ #define LDB_LVDS1_CONTROL_CH0_EN_MASK (0x1U) #define LDB_LVDS1_CONTROL_CH0_EN_SHIFT (0U) /*! CH0_EN - Channel 0 enable * 0b0..Disable * 0b1..Enable */ #define LDB_LVDS1_CONTROL_CH0_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_CH0_EN_SHIFT)) & LDB_LVDS1_CONTROL_CH0_EN_MASK) #define LDB_LVDS1_CONTROL_LVDS_EN_MASK (0x2U) #define LDB_LVDS1_CONTROL_LVDS_EN_SHIFT (1U) /*! LVDS_EN - LVDS PHY enable * 0b1..Disable * 0b0..Enable. LVDS function is normal. */ #define LDB_LVDS1_CONTROL_LVDS_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_LVDS_EN_SHIFT)) & LDB_LVDS1_CONTROL_LVDS_EN_MASK) #define LDB_LVDS1_CONTROL_BG_EN_MASK (0x4U) #define LDB_LVDS1_CONTROL_BG_EN_SHIFT (2U) /*! BG_EN - Bandgap enable * 0b1..Enable * 0b0..Disable */ #define LDB_LVDS1_CONTROL_BG_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_BG_EN_SHIFT)) & LDB_LVDS1_CONTROL_BG_EN_MASK) #define LDB_LVDS1_CONTROL_HS_EN_MASK (0x8U) #define LDB_LVDS1_CONTROL_HS_EN_SHIFT (3U) /*! HS_EN - Enable 100 ohm termination in the chip enable which also doubles power dissipation. * 0b1..Enable * 0b0..Disable */ #define LDB_LVDS1_CONTROL_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_HS_EN_SHIFT)) & LDB_LVDS1_CONTROL_HS_EN_MASK) #define LDB_LVDS1_CONTROL_PRE_EMPH_EN_MASK (0x10U) #define LDB_LVDS1_CONTROL_PRE_EMPH_EN_SHIFT (4U) /*! PRE_EMPH_EN - Enable pre-emphasis * 0b1..Enable * 0b0..Disable */ #define LDB_LVDS1_CONTROL_PRE_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_PRE_EMPH_EN_SHIFT)) & LDB_LVDS1_CONTROL_PRE_EMPH_EN_MASK) #define LDB_LVDS1_CONTROL_PRE_EMPH_ADJ_MASK (0xE0U) #define LDB_LVDS1_CONTROL_PRE_EMPH_ADJ_SHIFT (5U) /*! PRE_EMPH_ADJ - Pre-emphasis adjustment. */ #define LDB_LVDS1_CONTROL_PRE_EMPH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_PRE_EMPH_ADJ_SHIFT)) & LDB_LVDS1_CONTROL_PRE_EMPH_ADJ_MASK) #define LDB_LVDS1_CONTROL_CM_ADJ_MASK (0x700U) #define LDB_LVDS1_CONTROL_CM_ADJ_SHIFT (8U) /*! CM_ADJ - Output common mode (Vos) adjustment */ #define LDB_LVDS1_CONTROL_CM_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_CM_ADJ_SHIFT)) & LDB_LVDS1_CONTROL_CM_ADJ_MASK) #define LDB_LVDS1_CONTROL_CC_ADJ_MASK (0x3800U) #define LDB_LVDS1_CONTROL_CC_ADJ_SHIFT (11U) /*! CC_ADJ - Output current adjustment */ #define LDB_LVDS1_CONTROL_CC_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_CC_ADJ_SHIFT)) & LDB_LVDS1_CONTROL_CC_ADJ_MASK) #define LDB_LVDS1_CONTROL_SLEW_ADJ_MASK (0x1C000U) #define LDB_LVDS1_CONTROL_SLEW_ADJ_SHIFT (14U) /*! SLEW_ADJ - Output transition time adjustment */ #define LDB_LVDS1_CONTROL_SLEW_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_SLEW_ADJ_SHIFT)) & LDB_LVDS1_CONTROL_SLEW_ADJ_MASK) #define LDB_LVDS1_CONTROL_VBG_ADJ_MASK (0xE0000U) #define LDB_LVDS1_CONTROL_VBG_ADJ_SHIFT (17U) /*! VBG_ADJ - Bandgap adjustment */ #define LDB_LVDS1_CONTROL_VBG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_VBG_ADJ_SHIFT)) & LDB_LVDS1_CONTROL_VBG_ADJ_MASK) #define LDB_LVDS1_CONTROL_TEST_DIV4_MASK (0x100000U) #define LDB_LVDS1_CONTROL_TEST_DIV4_SHIFT (20U) /*! TEST_DIV4 - Divide the input signal/clock by 4. * 0b1..Enable * 0b0..Disable */ #define LDB_LVDS1_CONTROL_TEST_DIV4(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_TEST_DIV4_SHIFT)) & LDB_LVDS1_CONTROL_TEST_DIV4_MASK) #define LDB_LVDS1_CONTROL_TEST_EN_MASK (0x200000U) #define LDB_LVDS1_CONTROL_TEST_EN_SHIFT (21U) /*! TEST_EN - Test enable * 0b1..Enable * 0b0..Disable */ #define LDB_LVDS1_CONTROL_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_TEST_EN_SHIFT)) & LDB_LVDS1_CONTROL_TEST_EN_MASK) #define LDB_LVDS1_CONTROL_TEST_MUX_SRC_MASK (0xC00000U) #define LDB_LVDS1_CONTROL_TEST_MUX_SRC_SHIFT (22U) /*! TEST_MUX_SRC - Select which signals to test * 0b01..LVDS1_D1_P/N * 0b00..LVDS1_D0_P/N * 0b10..LVDS1_D2_P/N * 0b11..LVDS1_D3_P/N */ #define LDB_LVDS1_CONTROL_TEST_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_TEST_MUX_SRC_SHIFT)) & LDB_LVDS1_CONTROL_TEST_MUX_SRC_MASK) #define LDB_LVDS1_CONTROL_TEST_RANDOM_NUM_EN_MASK (0x1000000U) #define LDB_LVDS1_CONTROL_TEST_RANDOM_NUM_EN_SHIFT (24U) /*! TEST_RANDOM_NUM_EN - Random number generator enable * 0b1..Enable * 0b0..Disable */ #define LDB_LVDS1_CONTROL_TEST_RANDOM_NUM_EN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_TEST_RANDOM_NUM_EN_SHIFT)) & LDB_LVDS1_CONTROL_TEST_RANDOM_NUM_EN_MASK) #define LDB_LVDS1_CONTROL_SPARE_IN_MASK (0xE000000U) #define LDB_LVDS1_CONTROL_SPARE_IN_SHIFT (25U) /*! SPARE_IN - Spare ports */ #define LDB_LVDS1_CONTROL_SPARE_IN(x) (((uint32_t)(((uint32_t)(x)) << LDB_LVDS1_CONTROL_SPARE_IN_SHIFT)) & LDB_LVDS1_CONTROL_SPARE_IN_MASK) /*! @} */ /*! * @} */ /* end of group LDB_Register_Masks */ /* LDB - Peripheral instance base addresses */ /** Peripheral LVDS base address */ #define LVDS_BASE (0x4B0C0000u) /** Peripheral LVDS base pointer */ #define LVDS ((LDB_Type *)LVDS_BASE) /** Array initializer of LDB peripheral base addresses */ #define LDB_BASE_ADDRS { LVDS_BASE } /** Array initializer of LDB peripheral base pointers */ #define LDB_BASE_PTRS { LVDS } /*! * @} */ /* end of group LDB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPI2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer * @{ */ /** LPI2C - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ uint8_t RESERVED_1[16]; __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ uint8_t RESERVED_3[4]; __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ uint8_t RESERVED_4[4]; __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ uint8_t RESERVED_5[12]; __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ uint8_t RESERVED_6[4]; __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ uint8_t RESERVED_7[148]; __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ uint8_t RESERVED_8[20]; __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ uint8_t RESERVED_9[12]; __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ uint8_t RESERVED_10[8]; __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ uint8_t RESERVED_11[12]; __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ uint8_t RESERVED_12[4]; __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ uint8_t RESERVED_13[132]; __O uint32_t MTCBR[128]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ __O uint32_t MTDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ } LPI2C_Type; /* ---------------------------------------------------------------------------- -- LPI2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPI2C_Register_Masks LPI2C Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000010..Controller only, with standard feature set * 0b0000000000000011..Controller and target, with standard feature set */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) /*! MTXFIFO - Controller Transmit FIFO Size */ #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) /*! MRXFIFO - Controller Receive FIFO Size */ #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) /*! @} */ /*! @name MCR - Controller Control */ /*! @{ */ #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Controller Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..No effect * 0b1..Reset */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) /*! DOZEN - Doze Mode Enable * 0b0..Enable * 0b1..Disable */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Reset transmit FIFO */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Reset receive FIFO */ #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ /*! @name MSR - Controller Status */ /*! @{ */ #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data requested */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data not ready * 0b1..Receive data ready */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag * 0b0..No Stop or repeated Start generated * 0b1..Stop or repeated Start generated * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) /*! SDF - Stop Detect Flag * 0b0..No Stop condition generated * 0b1..Stop condition generated * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag * 0b0..No unexpected NACK detected * 0b1..Unexpected NACK detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag * 0b0..Controller did not lose arbitration * 0b1..Controller lost arbitration * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag * 0b0..No FIFO error * 0b1..FIFO error * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag * 0b0..Pin low timeout did not occur * 0b1..Pin low timeout occurred * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag * 0b0..Matching data not received * 0b1..Matching data received * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) #define LPI2C_MSR_STF_MASK (0x8000U) #define LPI2C_MSR_STF_SHIFT (15U) /*! STF - Start Flag * 0b0..Start condition not detected * 0b1..Start condition detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) /*! MBF - Controller Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) /*! @} */ /*! @name MIER - Controller Interrupt Enable */ /*! @{ */ #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) /*! SDIE - Stop Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) #define LPI2C_MIER_STIE_MASK (0x8000U) #define LPI2C_MIER_STIE_SHIFT (15U) /*! STIE - Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) /*! @} */ /*! @name MDER - Controller DMA Enable */ /*! @{ */ #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ /*! @name MCFGR0 - Controller Configuration 0 */ /*! @{ */ #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity * 0b0..Active low * 0b1..Active high */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select * 0b0.. * 0b1..Host request input is input trigger */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO * 0b1..Received data is discarded unless MSR[DMF] is set */ #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) #define LPI2C_MCFGR0_RELAX_MASK (0x10000U) #define LPI2C_MCFGR0_RELAX_SHIFT (16U) /*! RELAX - Relaxed Mode * 0b0..Normal transfer * 0b1..Relaxed transfer */ #define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) #define LPI2C_MCFGR0_ABORT_MASK (0x20000U) #define LPI2C_MCFGR0_ABORT_SHIFT (17U) /*! ABORT - Abort Transfer * 0b0..Normal transfer * 0b1..Abort existing transfer and do not start a new one */ #define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) /*! @} */ /*! @name MCFGR1 - Controller Configuration 1 */ /*! @{ */ #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) /*! PRESCALE - Prescaler * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) /*! AUTOSTOP - Automatic Stop Generation * 0b0..No effect * 0b1..Stop automatically generated */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK - Ignore NACK * 0b0..No effect * 0b1..Treat a received NACK as an ACK */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration * 0b0..SCL * 0b1..SCL or SDA */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) #define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) #define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) /*! STOPCFG - Stop Configuration * 0b0..Any Stop condition * 0b1..Last Stop condition */ #define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) #define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) #define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) /*! STARTCFG - Start Configuration * 0b0..Sets when both I2C bus and LPI2C controller are idle * 0b1..Sets when I2C bus is idle */ #define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b000..Two-pin open drain mode * 0b001..Two-pin output only mode (Ultra-Fast mode) * 0b010..Two-pin push-pull mode * 0b011..Four-pin push-pull mode * 0b100..Two-pin open-drain mode with separate LPI2C target * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target * 0b110..Two-pin push-pull mode with separate LPI2C target * 0b111..Four-pin push-pull mode (inverted outputs) */ #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) /*! @} */ /*! @name MCFGR2 - Controller Configuration 2 */ /*! @{ */ #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) /*! BUSIDLE - Bus Idle Timeout */ #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) /*! @} */ /*! @name MCFGR3 - Controller Configuration 3 */ /*! @{ */ #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) /*! PINLOW - Pin Low Timeout */ #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ /*! @name MDMR - Controller Data Match */ /*! @{ */ #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) /*! MATCH1 - Match 1 Value */ #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) /*! @} */ /*! @name MCCR0 - Controller Clock Configuration 0 */ /*! @{ */ #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR0_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) /*! @} */ /*! @name MCCR1 - Controller Clock Configuration 1 */ /*! @{ */ #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR1_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay */ #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) /*! @} */ /*! @name MFCR - Controller FIFO Control */ /*! @{ */ #define LPI2C_MFCR_TXWATER_MASK (0x7U) #define LPI2C_MFCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) #define LPI2C_MFCR_RXWATER_MASK (0x70000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) /*! @} */ /*! @name MFSR - Controller FIFO Status */ /*! @{ */ #define LPI2C_MFSR_TXCOUNT_MASK (0xFU) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) #define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) /*! @} */ /*! @name MTDR - Controller Transmit Data */ /*! @{ */ #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data * 0b000..Transmit the value in DATA[7:0] * 0b001..Receive (DATA[7:0] + 1) bytes * 0b010..Generate Stop condition on I2C bus * 0b011..Receive and discard (DATA[7:0] + 1) bytes * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) */ #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ /*! @name MRDR - Controller Receive Data */ /*! @{ */ #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ /*! @name MRDROR - Controller Receive Data Read Only */ /*! @{ */ #define LPI2C_MRDROR_DATA_MASK (0xFFU) #define LPI2C_MRDROR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) #define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) /*! @} */ /*! @name SCR - Target Control */ /*! @{ */ #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Target Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Not reset * 0b1..Reset */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) /*! FILTEN - Filter Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) /*! FILTDZ - Filter Doze Enable * 0b0..Enable * 0b1..Disable */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..STDR is now empty */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..SRDR is now empty */ #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ /*! @name SSR - Target Status */ /*! @{ */ #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data is requested */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Not ready * 0b1..Ready */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) /*! AVF - Address Valid Flag * 0b0..Not valid * 0b1..Valid */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) /*! TAF - Transmit ACK Flag * 0b0..Not required * 0b1..Required */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag * 0b0..No repeated Start detected * 0b1..Repeated Start detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) /*! SDF - Stop Detect Flag * 0b0..No Stop detected * 0b1..Stop detected * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) /*! BEF - Bit Error Flag * 0b0..No bit error occurred * 0b1..Bit error occurred * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) /*! FEF - FIFO Error Flag * 0b0..No FIFO error * 0b1..FIFO error * 0b0..No effect * 0b1..Clear the flag */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) /*! AM0F - Address Match 0 Flag * 0b0..ADDR0 matching address not received * 0b1..ADDR0 matching address received */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Flag * 0b0..Matching address not received * 0b1..Matching address received */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) /*! GCF - General Call Flag * 0b0..General call address disabled or not detected * 0b1..General call address detected */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) /*! SARF - SMBus Alert Response Flag * 0b0..Disabled or not detected * 0b1..Enabled and detected */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) /*! SBF - Target Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag * 0b0..Idle * 0b1..Busy */ #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ /*! @name SIER - Target Interrupt Enable */ /*! @{ */ #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) /*! AVIE - Address Valid Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) /*! TAIE - Transmit ACK Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) /*! RSIE - Repeated Start Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) /*! SDIE - Stop Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) /*! BEIE - Bit Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) /*! FEIE - FIFO Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) /*! AM0IE - Address Match 0 Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) #define LPI2C_SIER_AM1IE_MASK (0x2000U) #define LPI2C_SIER_AM1IE_SHIFT (13U) /*! AM1IE - Address Match 1 Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) /*! GCIE - General Call Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) /*! SARIE - SMBus Alert Response Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ /*! @name SDER - Target DMA Enable */ /*! @{ */ #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..Disable DMA request * 0b1..Enable DMA request */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) /*! AVDE - Address Valid DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) #define LPI2C_SDER_RSDE_MASK (0x100U) #define LPI2C_SDER_RSDE_SHIFT (8U) /*! RSDE - Repeated Start DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) #define LPI2C_SDER_SDDE_MASK (0x200U) #define LPI2C_SDER_SDDE_SHIFT (9U) /*! SDDE - Stop Detect DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) /*! @} */ /*! @name SCFGR0 - Target Configuration 0 */ /*! @{ */ #define LPI2C_SCFGR0_RDREQ_MASK (0x1U) #define LPI2C_SCFGR0_RDREQ_SHIFT (0U) /*! RDREQ - Read Request * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) #define LPI2C_SCFGR0_RDACK_MASK (0x2U) #define LPI2C_SCFGR0_RDACK_SHIFT (1U) /*! RDACK - Read Acknowledge Flag * 0b0..Read Request not acknowledged * 0b1..Read Request acknowledged */ #define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) /*! @} */ /*! @name SCFGR1 - Target Configuration 1 */ /*! @{ */ #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) /*! ADRSTALL - Address SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) /*! RXSTALL - RX SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) /*! TXDSTALL - Transmit Data SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) /*! ACKSTALL - ACK SCL Stall * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) #define LPI2C_SCFGR1_RXNACK_MASK (0x10U) #define LPI2C_SCFGR1_RXNACK_SHIFT (4U) /*! RXNACK - Receive NACK * 0b0..ACK or NACK always determined by STAR[TXNACK] * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] */ #define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) /*! GCEN - General Call Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) /*! SAEN - SMBus Alert Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty * 0b1..MSR[TDF] is set whenever STDR is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration * 0b0..Return received data, clear MSR[RDF] * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK * 0b0..End transfer on NACK * 0b1..Do not end transfer on NACK */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) /*! HSMEN - HS Mode Enable * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) /*! ADDRCFG - Address Configuration * 0b000..Address match 0 (7-bit) * 0b001..Address match 0 (10-bit) * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) */ #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) #define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) #define LPI2C_SCFGR1_RXALL_SHIFT (24U) /*! RXALL - Receive All * 0b0..Disable * 0b1..Enable */ #define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) #define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) #define LPI2C_SCFGR1_RSCFG_SHIFT (25U) /*! RSCFG - Repeated Start Configuration * 0b0..Any repeated Start condition following an address match * 0b1..Any repeated Start condition */ #define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) #define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) #define LPI2C_SCFGR1_SDCFG_SHIFT (26U) /*! SDCFG - Stop Detect Configuration * 0b0..Any Stop condition following an address match * 0b1..Any Stop condition */ #define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) /*! @} */ /*! @name SCFGR2 - Target Configuration 2 */ /*! @{ */ #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) /*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) /*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA */ #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ /*! @name SAMR - Target Address Match */ /*! @{ */ #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) /*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) /*! ADDR1 - Address 1 Value */ #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ /*! @name SASR - Target Address Status */ /*! @{ */ #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) /*! RADDR - Received Address */ #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) /*! ANV - Address Not Valid * 0b0..Valid * 0b1..Not valid */ #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ /*! @name STAR - Target Transmit ACK */ /*! @{ */ #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK * 0b0..Transmit ACK * 0b1..Transmit NACK */ #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ /*! @name STDR - Target Transmit Data */ /*! @{ */ #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ /*! @name SRDR - Target Receive Data */ /*! @{ */ #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) /*! DATA - Received Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) #define LPI2C_SRDR_RADDR_MASK (0x700U) #define LPI2C_SRDR_RADDR_SHIFT (8U) /*! RADDR - Received Address */ #define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) /*! SOF - Start of Frame * 0b0..Not first * 0b1..First */ #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) /*! @} */ /*! @name SRDROR - Target Receive Data Read Only */ /*! @{ */ #define LPI2C_SRDROR_DATA_MASK (0xFFU) #define LPI2C_SRDROR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) #define LPI2C_SRDROR_RADDR_MASK (0x700U) #define LPI2C_SRDROR_RADDR_SHIFT (8U) /*! RADDR - Received Address */ #define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) #define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - Receive Empty * 0b0..Not empty * 0b1..Empty */ #define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) #define LPI2C_SRDROR_SOF_MASK (0x8000U) #define LPI2C_SRDROR_SOF_SHIFT (15U) /*! SOF - Start of Frame * 0b0..Not the first * 0b1..First */ #define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) /*! @} */ /*! @name MTCBR - Controller Transmit Command Burst */ /*! @{ */ #define LPI2C_MTCBR_DATA_MASK (0xFFU) #define LPI2C_MTCBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) #define LPI2C_MTCBR_CMD_MASK (0x700U) #define LPI2C_MTCBR_CMD_SHIFT (8U) /*! CMD - Command */ #define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) /*! @} */ /* The count of LPI2C_MTCBR */ #define LPI2C_MTCBR_COUNT (128U) /*! @name MTDBR - Transmit Data Burst */ /*! @{ */ #define LPI2C_MTDBR_DATA0_MASK (0xFFU) #define LPI2C_MTDBR_DATA0_SHIFT (0U) /*! DATA0 - Data */ #define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) #define LPI2C_MTDBR_DATA1_MASK (0xFF00U) #define LPI2C_MTDBR_DATA1_SHIFT (8U) /*! DATA1 - Data */ #define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) #define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) #define LPI2C_MTDBR_DATA2_SHIFT (16U) /*! DATA2 - Data */ #define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) #define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) #define LPI2C_MTDBR_DATA3_SHIFT (24U) /*! DATA3 - Data */ #define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) /*! @} */ /* The count of LPI2C_MTDBR */ #define LPI2C_MTDBR_COUNT (256U) /*! * @} */ /* end of group LPI2C_Register_Masks */ /* LPI2C - Peripheral instance base addresses */ /** Peripheral LPI2C1 base address */ #define LPI2C1_BASE (0x44340000u) /** Peripheral LPI2C1 base pointer */ #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) /** Peripheral LPI2C2 base address */ #define LPI2C2_BASE (0x44350000u) /** Peripheral LPI2C2 base pointer */ #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) /** Peripheral LPI2C3 base address */ #define LPI2C3_BASE (0x42530000u) /** Peripheral LPI2C3 base pointer */ #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) /** Peripheral LPI2C4 base address */ #define LPI2C4_BASE (0x42540000u) /** Peripheral LPI2C4 base pointer */ #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) /** Peripheral LPI2C5 base address */ #define LPI2C5_BASE (0x426B0000u) /** Peripheral LPI2C5 base pointer */ #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) /** Peripheral LPI2C6 base address */ #define LPI2C6_BASE (0x426C0000u) /** Peripheral LPI2C6 base pointer */ #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) /** Peripheral LPI2C7 base address */ #define LPI2C7_BASE (0x426D0000u) /** Peripheral LPI2C7 base pointer */ #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) /** Peripheral LPI2C8 base address */ #define LPI2C8_BASE (0x426E0000u) /** Peripheral LPI2C8 base pointer */ #define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) /** Array initializer of LPI2C peripheral base addresses */ #define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE, LPI2C8_BASE } /** Array initializer of LPI2C peripheral base pointers */ #define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8 } /** Interrupt vectors for the LPI2C peripheral type */ #define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn, NotAvail_IRQn, LPI2C8_IRQn } /*! * @} */ /* end of group LPI2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer * @{ */ /** LPIT - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t MCR; /**< Module Control, offset: 0x8 */ __IO uint32_t MSR; /**< Module Status, offset: 0xC */ __IO uint32_t MIER; /**< Module Interrupt Enable, offset: 0x10 */ __IO uint32_t SETTEN; /**< Set Timer Enable, offset: 0x14 */ __O uint32_t CLRTEN; /**< Clear Timer Enable, offset: 0x18 */ uint8_t RESERVED_0[4]; struct { /* offset: 0x20, array step: 0x10 */ __IO uint32_t TVAL; /**< Timer Value, array offset: 0x20, array step: 0x10 */ __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ __IO uint32_t TCTRL; /**< Timer Control, array offset: 0x28, array step: 0x10 */ uint8_t RESERVED_0[4]; } CHANNEL[4]; } LPIT_Type; /* ---------------------------------------------------------------------------- -- LPIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPIT_Register_Masks LPIT Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPIT_VERID_FEATURE_MASK (0xFFFFU) #define LPIT_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Number */ #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) #define LPIT_VERID_MINOR_MASK (0xFF0000U) #define LPIT_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) #define LPIT_VERID_MAJOR_MASK (0xFF000000U) #define LPIT_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPIT_PARAM_CHANNEL_MASK (0xFFU) #define LPIT_PARAM_CHANNEL_SHIFT (0U) /*! CHANNEL - Number of Timer Channels */ #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) #define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) #define LPIT_PARAM_EXT_TRIG_SHIFT (8U) /*! EXT_TRIG - Number of External Trigger Inputs */ #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) /*! @} */ /*! @name MCR - Module Control */ /*! @{ */ #define LPIT_MCR_M_CEN_MASK (0x1U) #define LPIT_MCR_M_CEN_SHIFT (0U) /*! M_CEN - Module Clock Enable * 0b0..Disable * 0b1..Enable */ #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) #define LPIT_MCR_SW_RST_MASK (0x2U) #define LPIT_MCR_SW_RST_SHIFT (1U) /*! SW_RST - Software Reset * 0b0..Does not reset * 0b1..Resets */ #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) #define LPIT_MCR_DOZE_EN_MASK (0x4U) #define LPIT_MCR_DOZE_EN_SHIFT (2U) /*! DOZE_EN - DOZE Mode Enable * 0b0..Stops timer channels * 0b1..Allows timer channels to continue running */ #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) #define LPIT_MCR_DBG_EN_MASK (0x8U) #define LPIT_MCR_DBG_EN_SHIFT (3U) /*! DBG_EN - Debug Mode Enable * 0b0..Stops timer channels * 0b1..Allows timer channels to continue running */ #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) /*! @} */ /*! @name MSR - Module Status */ /*! @{ */ #define LPIT_MSR_TIF0_MASK (0x1U) #define LPIT_MSR_TIF0_SHIFT (0U) /*! TIF0 - Channel 0 Timer Interrupt Flag * 0b0..Not timed out * 0b1..Timed out * 0b0..No effect * 0b1..Clear the flag */ #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) #define LPIT_MSR_TIF1_MASK (0x2U) #define LPIT_MSR_TIF1_SHIFT (1U) /*! TIF1 - Channel 1 Timer Interrupt Flag * 0b0..Not timed out * 0b1..Timed out * 0b0..No effect * 0b1..Clear the flag */ #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) #define LPIT_MSR_TIF2_MASK (0x4U) #define LPIT_MSR_TIF2_SHIFT (2U) /*! TIF2 - Channel 2 Timer Interrupt Flag * 0b0..Not timed out * 0b1..Timed out * 0b0..No effect * 0b1..Clear the flag */ #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) #define LPIT_MSR_TIF3_MASK (0x8U) #define LPIT_MSR_TIF3_SHIFT (3U) /*! TIF3 - Channel 3 Timer Interrupt Flag * 0b0..Not timed out * 0b1..Timed out * 0b0..No effect * 0b1..Clear the flag */ #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) /*! @} */ /*! @name MIER - Module Interrupt Enable */ /*! @{ */ #define LPIT_MIER_TIE0_MASK (0x1U) #define LPIT_MIER_TIE0_SHIFT (0U) /*! TIE0 - Channel 0 Timer Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) #define LPIT_MIER_TIE1_MASK (0x2U) #define LPIT_MIER_TIE1_SHIFT (1U) /*! TIE1 - Channel 1 Timer Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) #define LPIT_MIER_TIE2_MASK (0x4U) #define LPIT_MIER_TIE2_SHIFT (2U) /*! TIE2 - Channel 2 Timer Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) #define LPIT_MIER_TIE3_MASK (0x8U) #define LPIT_MIER_TIE3_SHIFT (3U) /*! TIE3 - Channel 3 Timer Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) /*! @} */ /*! @name SETTEN - Set Timer Enable */ /*! @{ */ #define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) #define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) /*! SET_T_EN_0 - Set Timer 0 Enable * 0b0..No effect * 0b1..Enables timer channel 0 */ #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) #define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) #define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) /*! SET_T_EN_1 - Set Timer 1 Enable * 0b0..No Effect * 0b1..Enables timer channel 1 */ #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) #define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) #define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) /*! SET_T_EN_2 - Set Timer 2 Enable * 0b0..No Effect * 0b1..Enables timer channel 2 */ #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) #define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) #define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) /*! SET_T_EN_3 - Set Timer 3 Enable * 0b0..No effect * 0b1..Enables timer channel 3 */ #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) /*! @} */ /*! @name CLRTEN - Clear Timer Enable */ /*! @{ */ #define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) /*! CLR_T_EN_0 - Clear Timer 0 Enable * 0b0..No action * 0b1..Turns TCTRL0[T_EN] = 0 for timer channel 0 */ #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) #define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) /*! CLR_T_EN_1 - Clear Timer 1 Enable * 0b0..No action * 0b1..Turns TCTRL1[T_EN] = 0 for timer channel 1 */ #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) #define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) /*! CLR_T_EN_2 - Clear Timer 2 Enable * 0b0..No action * 0b1..Turns TCTRL2[T_EN] = 0 for timer channel 2 */ #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) #define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) /*! CLR_T_EN_3 - Clear Timer 3 Enable * 0b0..No action * 0b1..Turns TCTRL3[T_EN] = 0 for timer channel 3 */ #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) /*! @} */ /*! @name TVAL - Timer Value */ /*! @{ */ #define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) #define LPIT_TVAL_TMR_VAL_SHIFT (0U) /*! TMR_VAL - Timer Value * 0b00000000000000000000000000000000, 0b00000000000000000000000000000001..Invalid load value in Compare mode * 0b00000000000000000000000000000010-0b11111111111111111111111111111111..In Compare mode: the value to be loaded; in Capture mode, the value of the timer */ #define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) /*! @} */ /* The count of LPIT_TVAL */ #define LPIT_TVAL_COUNT (4U) /*! @name CVAL - Current Timer Value */ /*! @{ */ #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) #define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) /*! TMR_CUR_VAL - Current Timer Value */ #define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) /*! @} */ /* The count of LPIT_CVAL */ #define LPIT_CVAL_COUNT (4U) /*! @name TCTRL - Timer Control */ /*! @{ */ #define LPIT_TCTRL_T_EN_MASK (0x1U) #define LPIT_TCTRL_T_EN_SHIFT (0U) /*! T_EN - Timer Enable * 0b0..Disable * 0b1..Enable */ #define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) #define LPIT_TCTRL_CHAIN_MASK (0x2U) #define LPIT_TCTRL_CHAIN_SHIFT (1U) /*! CHAIN - Chain Channel * 0b0..Disabled * 0b1..Enabled */ #define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) #define LPIT_TCTRL_MODE_MASK (0xCU) #define LPIT_TCTRL_MODE_SHIFT (2U) /*! MODE - Timer Operation Mode * 0b00..32-bit periodic counter * 0b01..Dual 16-bit periodic counter * 0b10..32-bit trigger accumulator * 0b11..32-bit trigger input capture */ #define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) #define LPIT_TCTRL_TSOT_MASK (0x10000U) #define LPIT_TCTRL_TSOT_SHIFT (16U) /*! TSOT - Timer Start on Trigger * 0b0..Immediately * 0b1..When a rising edge is detected */ #define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) #define LPIT_TCTRL_TSOI_MASK (0x20000U) #define LPIT_TCTRL_TSOI_SHIFT (17U) /*! TSOI - Timer Stop on Interrupt * 0b0..Does not stop * 0b1..Stops */ #define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) #define LPIT_TCTRL_TROT_MASK (0x40000U) #define LPIT_TCTRL_TROT_SHIFT (18U) /*! TROT - Timer Reload on Trigger * 0b0..Does not reload * 0b1..Reloads */ #define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) #define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) #define LPIT_TCTRL_TRG_SRC_SHIFT (23U) /*! TRG_SRC - Trigger Source * 0b0..External * 0b1..Internal */ #define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) #define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) #define LPIT_TCTRL_TRG_SEL_SHIFT (24U) /*! TRG_SEL - Trigger Select * 0b0000-0b0011..Timer channel 0-3 trigger source * 0b0100-0b1111..Reserved */ #define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) /*! @} */ /* The count of LPIT_TCTRL */ #define LPIT_TCTRL_COUNT (4U) /*! * @} */ /* end of group LPIT_Register_Masks */ /* LPIT - Peripheral instance base addresses */ /** Peripheral LPIT1 base address */ #define LPIT1_BASE (0x442F0000u) /** Peripheral LPIT1 base pointer */ #define LPIT1 ((LPIT_Type *)LPIT1_BASE) /** Peripheral LPIT2 base address */ #define LPIT2_BASE (0x424C0000u) /** Peripheral LPIT2 base pointer */ #define LPIT2 ((LPIT_Type *)LPIT2_BASE) /** Array initializer of LPIT peripheral base addresses */ #define LPIT_BASE_ADDRS { 0u, LPIT1_BASE, LPIT2_BASE } /** Array initializer of LPIT peripheral base pointers */ #define LPIT_BASE_PTRS { (LPIT_Type *)0u, LPIT1, LPIT2 } /*! * @} */ /* end of group LPIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPSPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer * @{ */ /** LPSPI - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t CR; /**< Control, offset: 0x10 */ __IO uint32_t SR; /**< Status, offset: 0x14 */ __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ uint8_t RESERVED_3[16]; __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ uint8_t RESERVED_4[8]; __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ uint8_t RESERVED_5[896]; __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ } LPSPI_Type; /* ---------------------------------------------------------------------------- -- LPSPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPSPI_Register_Masks LPSPI Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Module Identification Number * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. * *.. */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) #define LPSPI_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) #define LPSPI_PARAM_PCSNUM_SHIFT (16U) /*! PCSNUM - PCS Number */ #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) /*! @} */ /*! @name CR - Control */ /*! @{ */ #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) /*! MEN - Module Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Not reset * 0b1..Reset */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) #define LPSPI_CR_DOZEN_MASK (0x4U) #define LPSPI_CR_DOZEN_SHIFT (2U) /*! DOZEN - Doze Mode Enable * 0b0..Enable * 0b1..Disable */ #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect * 0b1..Reset */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect * 0b1..Reset */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) /*! @} */ /*! @name SR - Status */ /*! @{ */ #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag * 0b0..Transmit data not requested * 0b1..Transmit data requested */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag * 0b0..Receive data not ready * 0b1..Receive data ready */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) /*! WCF - Word Complete Flag * 0b0..Not complete * 0b1..Complete * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) /*! FCF - Frame Complete Flag * 0b0..Not complete * 0b1..Complete * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) /*! TCF - Transfer Complete Flag * 0b0..Not complete * 0b1..Complete * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) /*! TEF - Transmit Error Flag * 0b0..No underrun * 0b1..Underrun * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) /*! REF - Receive Error Flag * 0b0..No overflow * 0b1..Overflow * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) /*! DMF - Data Match Flag * 0b0..No match * 0b1..Match * 0b0..No effect * 0b1..Clear the flag */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) /*! MBF - Module Busy Flag * 0b0..LPSPI is idle * 0b1..LPSPI is busy */ #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) /*! @} */ /*! @name IER - Interrupt Enable */ /*! @{ */ #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) /*! WCIE - Word Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) /*! FCIE - Frame Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) /*! TCIE - Transfer Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) /*! TEIE - Transmit Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) /*! REIE - Receive Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) /*! DMIE - Data Match Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) /*! @} */ /*! @name DER - DMA Enable */ /*! @{ */ #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) #define LPSPI_DER_FCDE_MASK (0x200U) #define LPSPI_DER_FCDE_SHIFT (9U) /*! FCDE - Frame Complete DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) /*! @} */ /*! @name CFGR0 - Configuration 0 */ /*! @{ */ #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) /*! @} */ /*! @name CFGR1 - Configuration 1 */ /*! @{ */ #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) /*! MASTER - Master Mode * 0b0..Slave mode * 0b1..Master mode */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) /*! SAMPLE - Sample Point * 0b0..SCK edge * 0b1..Delayed SCK edge */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) /*! AUTOPCS - Automatic PCS * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) /*! NOSTALL - No Stall * 0b0..Disable * 0b1..Enable */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) #define LPSPI_CFGR1_PARTIAL_MASK (0x10U) #define LPSPI_CFGR1_PARTIAL_SHIFT (4U) /*! PARTIAL - Partial Enable * 0b0..Discard * 0b1..Store */ #define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) #define LPSPI_CFGR1_PCSPOL_MASK (0x700U) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) /*! PCSPOL - Peripheral Chip Select Polarity * 0b000..Active low * 0b001..Active high */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) /* Merged from fields with different position or width, of widths (2, 3), largest definition used */ #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001.. * 0b010..Match first data word with compare word * 0b011..Match any data word with compare word * 0b100..Sequential match, first data word * 0b101..Sequential match, any data word * 0b110..Match first data word (masked) with compare word (masked) * 0b111..Match any data word (masked) with compare word (masked) */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration * 0b00..SIN is used for input data; SOUT is used for output data * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported * 0b11..SOUT is used for input data; SIN is used for output data */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Configuration * 0b0..Retain last value * 0b1..3-stated */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) /*! @} */ /*! @name DMR0 - Data Match 0 */ /*! @{ */ #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) /*! @} */ /*! @name DMR1 - Data Match 1 */ /*! @{ */ #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) /*! MATCH1 - Match 1 Value */ #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) /*! @} */ /*! @name CCR - Clock Configuration */ /*! @{ */ #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) /*! SCKDIV - SCK Divider */ #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) #define LPSPI_CCR_DBT_MASK (0xFF00U) #define LPSPI_CCR_DBT_SHIFT (8U) /*! DBT - Delay Between Transfers */ #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) #define LPSPI_CCR_PCSSCK_SHIFT (16U) /*! PCSSCK - PCS-to-SCK Delay */ #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) /*! SCKPCS - SCK-to-PCS Delay */ #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) /*! @} */ /*! @name CCR1 - Clock Configuration 1 */ /*! @{ */ #define LPSPI_CCR1_SCKSET_MASK (0xFFU) #define LPSPI_CCR1_SCKSET_SHIFT (0U) /*! SCKSET - SCK Setup */ #define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) #define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) #define LPSPI_CCR1_SCKHLD_SHIFT (8U) /*! SCKHLD - SCK Hold */ #define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) #define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) #define LPSPI_CCR1_PCSPCS_SHIFT (16U) /*! PCSPCS - PCS to PCS Delay */ #define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) #define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) #define LPSPI_CCR1_SCKSCK_SHIFT (24U) /*! SCKSCK - SCK Inter-Frame Delay */ #define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) /*! @} */ /*! @name FCR - FIFO Control */ /*! @{ */ #define LPSPI_FCR_TXWATER_MASK (0xFU) #define LPSPI_FCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) #define LPSPI_FCR_RXWATER_MASK (0xF0000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark */ #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) /*! @} */ /*! @name FSR - FIFO Status */ /*! @{ */ #define LPSPI_FSR_TXCOUNT_MASK (0x1FU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count */ #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) /*! @} */ /*! @name TCR - Transmit Command */ /*! @{ */ #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) /*! FRAMESZ - Frame Size */ #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) /*! TXMSK - Transmit Data Mask * 0b0..Normal transfer * 0b1..Mask transmit data */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask * 0b0..Normal transfer * 0b1..Mask receive data */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) /*! CONTC - Continuing Command * 0b0..Command word for start of new transfer * 0b1..Command word for continuing transfer */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer * 0b0..Disable * 0b1..Enable */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap * 0b0..Disable byte swap * 0b1..Enable byte swap */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First * 0b0..MSB first * 0b1..LSB first */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) #define LPSPI_TCR_PCS_MASK (0x3000000U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define LPSPI_TCR_PCS_SHIFT (24U) /*! PCS - Peripheral Chip Select * 0b00..Transfer using PCS[0] * 0b01..Transfer using PCS[1] * 0b10..Transfer using PCS[2] */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) /*! PRESCALE - Prescaler Value * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) /*! CPHA - Clock Phase * 0b0..Captured * 0b1..Changed */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) /*! CPOL - Clock Polarity * 0b0..Inactive low * 0b1..Inactive high */ #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) /*! @} */ /*! @name TDR - Transmit Data */ /*! @{ */ #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) /*! @} */ /*! @name RSR - Receive Status */ /*! @{ */ #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) /*! SOF - Start of Frame * 0b0..Subsequent data word * 0b1..First data word */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) /*! RXEMPTY - RX FIFO Empty * 0b0..Not empty * 0b1..Empty */ #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) /*! @} */ /*! @name RDR - Receive Data */ /*! @{ */ #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) /*! @} */ /*! @name RDROR - Receive Data Read Only */ /*! @{ */ #define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDROR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) /*! @} */ /*! @name TCBR - Transmit Command Burst */ /*! @{ */ #define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TCBR_DATA_SHIFT (0U) /*! DATA - Command Data */ #define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) /*! @} */ /*! @name TDBR - Transmit Data Burst */ /*! @{ */ #define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) /*! @} */ /* The count of LPSPI_TDBR */ #define LPSPI_TDBR_COUNT (128U) /*! @name RDBR - Receive Data Burst */ /*! @{ */ #define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) /*! @} */ /* The count of LPSPI_RDBR */ #define LPSPI_RDBR_COUNT (128U) /*! * @} */ /* end of group LPSPI_Register_Masks */ /* LPSPI - Peripheral instance base addresses */ /** Peripheral LPSPI1 base address */ #define LPSPI1_BASE (0x44360000u) /** Peripheral LPSPI1 base pointer */ #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) /** Peripheral LPSPI2 base address */ #define LPSPI2_BASE (0x44370000u) /** Peripheral LPSPI2 base pointer */ #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) /** Peripheral LPSPI3 base address */ #define LPSPI3_BASE (0x42550000u) /** Peripheral LPSPI3 base pointer */ #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) /** Peripheral LPSPI4 base address */ #define LPSPI4_BASE (0x42560000u) /** Peripheral LPSPI4 base pointer */ #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) /** Peripheral LPSPI5 base address */ #define LPSPI5_BASE (0x426F0000u) /** Peripheral LPSPI5 base pointer */ #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) /** Peripheral LPSPI6 base address */ #define LPSPI6_BASE (0x42700000u) /** Peripheral LPSPI6 base pointer */ #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) /** Peripheral LPSPI7 base address */ #define LPSPI7_BASE (0x42710000u) /** Peripheral LPSPI7 base pointer */ #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) /** Peripheral LPSPI8 base address */ #define LPSPI8_BASE (0x42720000u) /** Peripheral LPSPI8 base pointer */ #define LPSPI8 ((LPSPI_Type *)LPSPI8_BASE) /** Array initializer of LPSPI peripheral base addresses */ #define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE, LPSPI8_BASE } /** Array initializer of LPSPI peripheral base pointers */ #define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8 } /** Interrupt vectors for the LPSPI peripheral type */ #define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn, LPSPI7_IRQn, LPSPI8_IRQn } /*! * @} */ /* end of group LPSPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer * @{ */ /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ __IO uint32_t CMR; /**< Compare, offset: 0x8 */ __IO uint32_t CNR; /**< Counter, offset: 0xC */ } LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /*! @name CSR - Control Status */ /*! @{ */ #define LPTMR_CSR_TEN_MASK (0x1U) #define LPTMR_CSR_TEN_SHIFT (0U) /*! TEN - Timer Enable * 0b0..Disable * 0b1..Enable */ #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) #define LPTMR_CSR_TMS_MASK (0x2U) #define LPTMR_CSR_TMS_SHIFT (1U) /*! TMS - Timer Mode Select * 0b0..Time Counter * 0b1..Pulse Counter */ #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) #define LPTMR_CSR_TFC_MASK (0x4U) #define LPTMR_CSR_TFC_SHIFT (2U) /*! TFC - Timer Free-Running Counter * 0b0..Reset when TCF asserts * 0b1..Reset on overflow */ #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) #define LPTMR_CSR_TPP_MASK (0x8U) #define LPTMR_CSR_TPP_SHIFT (3U) /*! TPP - Timer Pin Polarity * 0b0..Active-high * 0b1..Active-low */ #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) #define LPTMR_CSR_TPS_MASK (0x30U) #define LPTMR_CSR_TPS_SHIFT (4U) /*! TPS - Timer Pin Select * 0b00..Input 0 * 0b01..Input 1 * 0b10..Input 2 * 0b11..Input 3 */ #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) #define LPTMR_CSR_TIE_MASK (0x40U) #define LPTMR_CSR_TIE_SHIFT (6U) /*! TIE - Timer Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) #define LPTMR_CSR_TCF_MASK (0x80U) #define LPTMR_CSR_TCF_SHIFT (7U) /*! TCF - Timer Compare Flag * 0b0..CNR != (CMR + 1) * 0b1..CNR = (CMR + 1) * 0b0..No effect * 0b1..Clear the flag */ #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) #define LPTMR_CSR_TDRE_MASK (0x100U) #define LPTMR_CSR_TDRE_SHIFT (8U) /*! TDRE - Timer DMA Request Enable * 0b0..Disable * 0b1..Enable */ #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) /*! @} */ /*! @name PSR - Prescaler and Glitch Filter */ /*! @{ */ #define LPTMR_PSR_PCS_MASK (0x3U) #define LPTMR_PSR_PCS_SHIFT (0U) /*! PCS - Prescaler and Glitch Filter Clock Select * 0b00..Clock 0 * 0b01..Clock 1 * 0b10..Clock 2 * 0b11..Clock 3 */ #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) #define LPTMR_PSR_PBYP_MASK (0x4U) #define LPTMR_PSR_PBYP_SHIFT (2U) /*! PBYP - Prescaler and Glitch Filter Bypass * 0b0..Prescaler and glitch filter enable * 0b1..Prescaler and glitch filter bypass */ #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) #define LPTMR_PSR_PRESCALE_MASK (0x78U) #define LPTMR_PSR_PRESCALE_SHIFT (3U) /*! PRESCALE - Prescaler and Glitch Filter Value * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges */ #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) /*! @} */ /*! @name CMR - Compare */ /*! @{ */ #define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) #define LPTMR_CMR_COMPARE_SHIFT (0U) /*! COMPARE - Compare Value */ #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) /*! @} */ /*! @name CNR - Counter */ /*! @{ */ #define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) #define LPTMR_CNR_COUNTER_SHIFT (0U) /*! COUNTER - Counter Value */ #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) /*! @} */ /*! * @} */ /* end of group LPTMR_Register_Masks */ /* LPTMR - Peripheral instance base addresses */ /** Peripheral LPTMR1 base address */ #define LPTMR1_BASE (0x44300000u) /** Peripheral LPTMR1 base pointer */ #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) /** Peripheral LPTMR2 base address */ #define LPTMR2_BASE (0x424D0000u) /** Peripheral LPTMR2 base pointer */ #define LPTMR2 ((LPTMR_Type *)LPTMR2_BASE) /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS { 0u, LPTMR1_BASE, LPTMR2_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { (LPTMR_Type *)0u, LPTMR1, LPTMR2 } /*! * @} */ /* end of group LPTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer * @{ */ /** LPUART - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ __IO uint32_t STAT; /**< Status, offset: 0x14 */ __IO uint32_t CTRL; /**< Control, offset: 0x18 */ __IO uint32_t DATA; /**< Data, offset: 0x1C */ __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ uint8_t RESERVED_0[12]; __IO uint32_t MCR; /**< MODEM Control, offset: 0x40 */ __IO uint32_t MSR; /**< MODEM Status, offset: 0x44 */ __IO uint32_t REIR; /**< Receiver Extended Idle, offset: 0x48 */ __IO uint32_t TEIR; /**< Transmitter Extended Idle, offset: 0x4C */ __IO uint32_t HDCR; /**< Half Duplex Control, offset: 0x50 */ uint8_t RESERVED_1[4]; __IO uint32_t TOCR; /**< Timeout Control, offset: 0x58 */ __IO uint32_t TOSR; /**< Timeout Status, offset: 0x5C */ __IO uint32_t TIMEOUT[4]; /**< Timeout N, array offset: 0x60, array step: 0x4 */ uint8_t RESERVED_2[400]; __O uint32_t TCBR[128]; /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */ __O uint32_t TDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ } LPUART_Type; /* ---------------------------------------------------------------------------- -- LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Masks LPUART Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set * 0b0000000000000011..Standard feature set with MODEM and IrDA support * 0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) /*! @} */ /*! @name GLOBAL - Global */ /*! @{ */ #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Not reset * 0b1..Reset */ #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) /*! @} */ /*! @name PINCFG - Pin Configuration */ /*! @{ */ #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) /*! TRGSEL - Trigger Select * 0b00..Input trigger disabled * 0b01..Input trigger used instead of the RXD pin input * 0b10..Input trigger used instead of the CTS_B pin input * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) /*! @} */ /*! @name BAUD - Baud Rate */ /*! @{ */ #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) /*! SBR - Baud Rate Modulo Divisor */ #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) /*! SBNS - Stop Bit Number Select * 0b0..One stop bit * 0b1..Two stop bits */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable * 0b0..Enable * 0b1..Disable */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling * 0b0..Rising edge * 0b1..Both rising and falling edges */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration * 0b00..Address match wake-up * 0b01..Idle match wake-up * 0b10..Match on and match off * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RIDMAE_MASK (0x100000U) #define LPUART_BAUD_RIDMAE_SHIFT (20U) /*! RIDMAE - Receiver Idle DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) /*! OSR - Oversampling Ratio * 0b00000..Results in an OSR of 16 * 0b00001..Reserved * 0b00010..Reserved * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) * 0b00111..Results in an OSR of 8 * 0b01000..Results in an OSR of 9 * 0b01001..Results in an OSR of 10 * 0b01010..Results in an OSR of 11 * 0b01011..Results in an OSR of 12 * 0b01100..Results in an OSR of 13 * 0b01101..Results in an OSR of 14 * 0b01110..Results in an OSR of 15 * 0b01111..Results in an OSR of 16 * 0b10000..Results in an OSR of 17 * 0b10001..Results in an OSR of 18 * 0b10010..Results in an OSR of 19 * 0b10011..Results in an OSR of 20 * 0b10100..Results in an OSR of 21 * 0b10101..Results in an OSR of 22 * 0b10110..Results in an OSR of 23 * 0b10111..Results in an OSR of 24 * 0b11000..Results in an OSR of 25 * 0b11001..Results in an OSR of 26 * 0b11010..Results in an OSR of 27 * 0b11011..Results in an OSR of 28 * 0b11100..Results in an OSR of 29 * 0b11101..Results in an OSR of 30 * 0b11110..Results in an OSR of 31 * 0b11111..Results in an OSR of 32 */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) /*! M10 - 10-Bit Mode Select * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters * 0b1..Receiver and transmitter use 10-bit data characters */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 * 0b0..Disable * 0b1..Enable */ #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) /*! @} */ /*! @name STAT - Status */ /*! @{ */ #define LPUART_STAT_LBKFE_MASK (0x1U) #define LPUART_STAT_LBKFE_SHIFT (0U) /*! LBKFE - LIN Break Flag Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) #define LPUART_STAT_AME_MASK (0x2U) #define LPUART_STAT_AME_SHIFT (1U) /*! AME - Address Mark Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) #define LPUART_STAT_MSF_MASK (0x100U) #define LPUART_STAT_MSF_SHIFT (8U) /*! MSF - MODEM Status Flag * 0b0..Field is 0 * 0b1..Field is 1 */ #define LPUART_STAT_MSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK) #define LPUART_STAT_TSF_MASK (0x200U) #define LPUART_STAT_TSF_SHIFT (9U) /*! TSF - Timeout Status Flag * 0b0..Field is 0 * 0b1..Field is 1 */ #define LPUART_STAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK) #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) /*! MA2F - Match 2 Flag * 0b0..Not equal to MA2 * 0b1..Equal to MA2 * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) /*! MA1F - Match 1 Flag * 0b0..Not equal to MA1 * 0b1..Equal to MA1 * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) /*! PF - Parity Error Flag * 0b0..No parity error detected * 0b1..Parity error detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) /*! FE - Framing Error Flag * 0b0..No framing error detected (this does not guarantee that the framing is correct) * 0b1..Framing error detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) /*! NF - Noise Flag * 0b0..No noise detected * 0b1..Noise detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag * 0b0..No overrun * 0b1..Receive overrun (new LPUART data is lost) * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag * 0b0..Idle line detected * 0b1..Idle line not detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) /*! RDRF - Receive Data Register Full Flag * 0b0..Equal to or less than watermark * 0b1..Greater than watermark */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag * 0b0..Transmitter active * 0b1..Transmitter idle */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) /*! TDRE - Transmit Data Register Empty Flag * 0b0..Greater than watermark * 0b1..Equal to or less than watermark */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) /*! RAF - Receiver Active Flag * 0b0..Idle, waiting for a start bit * 0b1..Receiver active (RXD pin input not idle) */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) /*! BRK13 - Break Character Generation Length * 0b0..9 to 13 bit times * 0b1..12 to 15 bit times */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) /*! RWUID - Receive Wake Up Idle Detect * 0b0..STAT[IDLE] does not become 1 * 0b1..STAT[IDLE] becomes 1 */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) /*! RXINV - Receive Data Inversion * 0b0..Inverted * 0b1..Not inverted */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) /*! MSBF - MSB First * 0b0..LSB * 0b1..MSB */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag * 0b0..Not occurred * 0b1..Occurred * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) /*! LBKDIF - LIN Break Detect Interrupt Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) /*! @} */ /*! @name CTRL - Control */ /*! @{ */ #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) /*! PT - Parity Type * 0b0..Even parity * 0b1..Odd parity */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) /*! ILT - Idle Line Type Select * 0b0..After the start bit * 0b1..After the stop bit */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) /*! WAKE - Receiver Wake-Up Method Select * 0b0..Idle * 0b1..Mark */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit Or 8-Bit Mode Select * 0b0..8-bit * 0b1..9-bit */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) /*! RSRC - Receiver Source Select * 0b0..Internal Loopback mode * 0b1..Single-wire mode */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) /*! DOZEEN - Doze Mode * 0b0..Enable * 0b1..Disable */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) /*! LOOPS - Loop Mode Select * 0b0..Normal operation: RXD and TXD use separate pins * 0b1..Loop mode or Single-Wire mode */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) /*! IDLECFG - Idle Configuration * 0b000..1 * 0b001..2 * 0b010..4 * 0b011..8 * 0b100..16 * 0b101..32 * 0b110..64 * 0b111..128 */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select * 0b0..8-bit to 10-bit * 0b1..7-bit */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 (MA2F) Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 (MA1F) Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) /*! SBK - Send Break * 0b0..Normal transmitter operation * 0b1..Queue break character(s) to be sent */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) /*! RWU - Receiver Wake-Up Control * 0b0..Normal receiver operation * 0b1..LPUART receiver in standby, waiting for a wake-up condition */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) /*! TXINV - Transmit Data Inversion * 0b0..Not inverted * 0b1..Inverted */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TXD Pin Direction in Single-Wire Mode * 0b0..Input * 0b1..Output */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) /*! R9T8 - Receive Bit 9 Transmit Bit 8 */ #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) /*! R8T9 - Receive Bit 8 Transmit Bit 9 */ #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) /*! @} */ /*! @name DATA - Data */ /*! @{ */ #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) /*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) /*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) /*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) /*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) /*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) /*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) /*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) /*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) /*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) /*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) #define LPUART_DATA_LINBRK_MASK (0x400U) #define LPUART_DATA_LINBRK_SHIFT (10U) /*! LINBRK - LIN Break * 0b0..Not detected * 0b1..Detected */ #define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line * 0b0..Not idle * 0b1..Idle */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty * 0b0..Valid data * 0b1..Invalid data and empty */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) /*! FRETSC - Frame Error Transmit Special Character * 0b0..Received without a frame error on reads or transmits a normal character on writes * 0b1..Received with a frame error on reads or transmits an idle or break character on writes */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) /*! PARITYE - Parity Error * 0b0..Received without a parity error * 0b1..Received with a parity error */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) /*! NOISY - Noisy Data Received * 0b0..Received without noise * 0b1..Received with noise */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) /*! @} */ /*! @name MATCH - Match Address */ /*! @{ */ #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) /*! MA1 - Match Address 1 */ #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) /*! MA2 - Match Address 2 */ #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) /*! @} */ /*! @name MODIR - MODEM IrDA */ /*! @{ */ #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter CTS Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter RTS Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter RTS Polarity * 0b0..Active low * 0b1..Active high */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver RTS Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) /*! TXCTSC - Transmit CTS Configuration * 0b0..Sampled at the start of each character * 0b1..Sampled when the transmitter is idle */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) /*! TXCTSSRC - Transmit CTS Source * 0b0..The CTS_B pin * 0b1..An internal connection to the receiver address match result */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) #define LPUART_MODIR_RTSWATER_MASK (0xF00U) #define LPUART_MODIR_RTSWATER_SHIFT (8U) /*! RTSWATER - Receive RTS Configuration */ #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) /*! TNP - Transmitter Narrow Pulse * 0b00..1 / OSR * 0b01..2 / OSR * 0b10..3 / OSR * 0b11..4 / OSR */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - IR Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) /*! @} */ /*! @name FIFO - FIFO */ /*! @{ */ #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO Buffer Depth * 0b000..1 * 0b001..4 * 0b010..8 * 0b011..16 * 0b100..32 * 0b101..64 * 0b110..128 * 0b111..256 */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO Buffer Depth * 0b000..1 * 0b001..4 * 0b010..8 * 0b011..16 * 0b100..32 * 0b101..64 * 0b110..128 * 0b111..256 */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) /*! RXFLUSH - Receive FIFO Flush * 0b0..No effect * 0b1..All data flushed out */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) /*! TXFLUSH - Transmit FIFO Flush * 0b0..No effect * 0b1..All data flushed out */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) /*! RXUF - Receiver FIFO Underflow Flag * 0b0..No underflow * 0b1..Underflow * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) /*! TXOF - Transmitter FIFO Overflow Flag * 0b0..No overflow * 0b1..Overflow * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) /*! RXEMPT - Receive FIFO Or Buffer Empty * 0b0..Not empty * 0b1..Empty */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) /*! TXEMPT - Transmit FIFO Or Buffer Empty * 0b0..Not empty * 0b1..Empty */ #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) /*! @} */ /*! @name WATER - Watermark */ /*! @{ */ #define LPUART_WATER_TXWATER_MASK (0xFU) #define LPUART_WATER_TXWATER_SHIFT (0U) /*! TXWATER - Transmit Watermark */ #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) #define LPUART_WATER_TXCOUNT_MASK (0x1F00U) #define LPUART_WATER_TXCOUNT_SHIFT (8U) /*! TXCOUNT - Transmit Counter */ #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) #define LPUART_WATER_RXWATER_MASK (0xF0000U) #define LPUART_WATER_RXWATER_SHIFT (16U) /*! RXWATER - Receive Watermark */ #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) #define LPUART_WATER_RXCOUNT_MASK (0x1F000000U) #define LPUART_WATER_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Counter */ #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) /*! @} */ /*! @name DATARO - Data Read-Only */ /*! @{ */ #define LPUART_DATARO_DATA_MASK (0xFFFFU) #define LPUART_DATARO_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) /*! @} */ /*! @name MCR - MODEM Control */ /*! @{ */ #define LPUART_MCR_CTS_MASK (0x1U) #define LPUART_MCR_CTS_SHIFT (0U) /*! CTS - Clear To Send * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) #define LPUART_MCR_DSR_MASK (0x2U) #define LPUART_MCR_DSR_SHIFT (1U) /*! DSR - Data Set Ready * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) #define LPUART_MCR_RIN_MASK (0x4U) #define LPUART_MCR_RIN_SHIFT (2U) /*! RIN - Ring Indicator * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) #define LPUART_MCR_DCD_MASK (0x8U) #define LPUART_MCR_DCD_SHIFT (3U) /*! DCD - Data Carrier Detect * 0b0..Disable interrupt * 0b1..Enable interrupt */ #define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) #define LPUART_MCR_DTR_MASK (0x100U) #define LPUART_MCR_DTR_SHIFT (8U) /*! DTR - Data Terminal Ready * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) #define LPUART_MCR_RTS_MASK (0x200U) #define LPUART_MCR_RTS_SHIFT (9U) /*! RTS - Request To Send * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) /*! @} */ /*! @name MSR - MODEM Status */ /*! @{ */ #define LPUART_MSR_DCTS_MASK (0x1U) #define LPUART_MSR_DCTS_SHIFT (0U) /*! DCTS - Delta Clear To Send * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) #define LPUART_MSR_DDSR_MASK (0x2U) #define LPUART_MSR_DDSR_SHIFT (1U) /*! DDSR - Delta Data Set Ready * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) #define LPUART_MSR_DRI_MASK (0x4U) #define LPUART_MSR_DRI_SHIFT (2U) /*! DRI - Delta Ring Indicator * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) #define LPUART_MSR_DDCD_MASK (0x8U) #define LPUART_MSR_DDCD_SHIFT (3U) /*! DDCD - Delta Data Carrier Detect * 0b0..Did not change state * 0b1..Changed state * 0b0..No effect * 0b1..Clear the flag */ #define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) #define LPUART_MSR_CTS_MASK (0x10U) #define LPUART_MSR_CTS_SHIFT (4U) /*! CTS - Clear To Send * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) #define LPUART_MSR_DSR_MASK (0x20U) #define LPUART_MSR_DSR_SHIFT (5U) /*! DSR - Data Set Ready * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) #define LPUART_MSR_RIN_MASK (0x40U) #define LPUART_MSR_RIN_SHIFT (6U) /*! RIN - Ring Indicator * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) #define LPUART_MSR_DCD_MASK (0x80U) #define LPUART_MSR_DCD_SHIFT (7U) /*! DCD - Data Carrier Detect * 0b0..Logic one * 0b1..Logic zero */ #define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) /*! @} */ /*! @name REIR - Receiver Extended Idle */ /*! @{ */ #define LPUART_REIR_IDTIME_MASK (0x3FFFU) #define LPUART_REIR_IDTIME_SHIFT (0U) /*! IDTIME - Idle Time */ #define LPUART_REIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK) /*! @} */ /*! @name TEIR - Transmitter Extended Idle */ /*! @{ */ #define LPUART_TEIR_IDTIME_MASK (0x3FFFU) #define LPUART_TEIR_IDTIME_SHIFT (0U) /*! IDTIME - Idle Time */ #define LPUART_TEIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK) /*! @} */ /*! @name HDCR - Half Duplex Control */ /*! @{ */ #define LPUART_HDCR_TXSTALL_MASK (0x1U) #define LPUART_HDCR_TXSTALL_SHIFT (0U) /*! TXSTALL - Transmit Stall * 0b0..No effect * 0b1..Does not become busy */ #define LPUART_HDCR_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK) #define LPUART_HDCR_RXSEL_MASK (0x2U) #define LPUART_HDCR_RXSEL_SHIFT (1U) /*! RXSEL - Receive Select * 0b0..RXD * 0b1..TXD */ #define LPUART_HDCR_RXSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK) #define LPUART_HDCR_RXWRMSK_MASK (0x4U) #define LPUART_HDCR_RXWRMSK_SHIFT (2U) /*! RXWRMSK - Receive FIFO Write Mask * 0b0..Do not mask * 0b1..Mask */ #define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) #define LPUART_HDCR_RXMSK_MASK (0x8U) #define LPUART_HDCR_RXMSK_SHIFT (3U) /*! RXMSK - Receive Mask * 0b0..Do not mask * 0b1..Mask */ #define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) #define LPUART_HDCR_RTSEXT_MASK (0xFF00U) #define LPUART_HDCR_RTSEXT_SHIFT (8U) /*! RTSEXT - RTS Extended */ #define LPUART_HDCR_RTSEXT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK) /*! @} */ /*! @name TOCR - Timeout Control */ /*! @{ */ #define LPUART_TOCR_TOEN_MASK (0xFU) #define LPUART_TOCR_TOEN_SHIFT (0U) /*! TOEN - Timeout Enable */ #define LPUART_TOCR_TOEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK) #define LPUART_TOCR_TOIE_MASK (0xF00U) #define LPUART_TOCR_TOIE_SHIFT (8U) /*! TOIE - Timeout Interrupt Enable */ #define LPUART_TOCR_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK) /*! @} */ /*! @name TOSR - Timeout Status */ /*! @{ */ #define LPUART_TOSR_TOZ_MASK (0xFU) #define LPUART_TOSR_TOZ_SHIFT (0U) /*! TOZ - Timeout Zero */ #define LPUART_TOSR_TOZ(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK) #define LPUART_TOSR_TOF_MASK (0xF00U) #define LPUART_TOSR_TOF_SHIFT (8U) /*! TOF - Timeout Flag * 0b0000..Not occurred * 0b0001..Occurred * 0b0000..No effect * 0b0001..Clear the flag */ #define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) /*! @} */ /*! @name TIMEOUT - Timeout N */ /*! @{ */ #define LPUART_TIMEOUT_TIMEOUT_MASK (0x3FFFU) #define LPUART_TIMEOUT_TIMEOUT_SHIFT (0U) /*! TIMEOUT - Timeout Value */ #define LPUART_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK) #define LPUART_TIMEOUT_CFG_MASK (0xC0000000U) #define LPUART_TIMEOUT_CFG_SHIFT (30U) /*! CFG - Idle Configuration * 0b00..Becomes 1 after timeout characters are received * 0b01..Becomes 1 when idle for timeout bit clocks * 0b10..Becomes 1 when idle for timeout bit clocks following the next character * 0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached */ #define LPUART_TIMEOUT_CFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK) /*! @} */ /* The count of LPUART_TIMEOUT */ #define LPUART_TIMEOUT_COUNT (4U) /*! @name TCBR - Transmit Command Burst */ /*! @{ */ #define LPUART_TCBR_DATA_MASK (0xFFFFU) #define LPUART_TCBR_DATA_SHIFT (0U) /*! DATA - Data */ #define LPUART_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK) /*! @} */ /* The count of LPUART_TCBR */ #define LPUART_TCBR_COUNT (128U) /*! @name TDBR - Transmit Data Burst */ /*! @{ */ #define LPUART_TDBR_DATA0_MASK (0xFFU) #define LPUART_TDBR_DATA0_SHIFT (0U) /*! DATA0 - Data0 */ #define LPUART_TDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK) #define LPUART_TDBR_DATA1_MASK (0xFF00U) #define LPUART_TDBR_DATA1_SHIFT (8U) /*! DATA1 - Data1 */ #define LPUART_TDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK) #define LPUART_TDBR_DATA2_MASK (0xFF0000U) #define LPUART_TDBR_DATA2_SHIFT (16U) /*! DATA2 - Data2 */ #define LPUART_TDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK) #define LPUART_TDBR_DATA3_MASK (0xFF000000U) #define LPUART_TDBR_DATA3_SHIFT (24U) /*! DATA3 - Data3 */ #define LPUART_TDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK) /*! @} */ /* The count of LPUART_TDBR */ #define LPUART_TDBR_COUNT (256U) /*! * @} */ /* end of group LPUART_Register_Masks */ /* LPUART - Peripheral instance base addresses */ /** Peripheral LPUART1 base address */ #define LPUART1_BASE (0x44380000u) /** Peripheral LPUART1 base pointer */ #define LPUART1 ((LPUART_Type *)LPUART1_BASE) /** Peripheral LPUART2 base address */ #define LPUART2_BASE (0x44390000u) /** Peripheral LPUART2 base pointer */ #define LPUART2 ((LPUART_Type *)LPUART2_BASE) /** Peripheral LPUART3 base address */ #define LPUART3_BASE (0x42570000u) /** Peripheral LPUART3 base pointer */ #define LPUART3 ((LPUART_Type *)LPUART3_BASE) /** Peripheral LPUART4 base address */ #define LPUART4_BASE (0x42580000u) /** Peripheral LPUART4 base pointer */ #define LPUART4 ((LPUART_Type *)LPUART4_BASE) /** Peripheral LPUART5 base address */ #define LPUART5_BASE (0x42590000u) /** Peripheral LPUART5 base pointer */ #define LPUART5 ((LPUART_Type *)LPUART5_BASE) /** Peripheral LPUART6 base address */ #define LPUART6_BASE (0x425A0000u) /** Peripheral LPUART6 base pointer */ #define LPUART6 ((LPUART_Type *)LPUART6_BASE) /** Peripheral LPUART7 base address */ #define LPUART7_BASE (0x42690000u) /** Peripheral LPUART7 base pointer */ #define LPUART7 ((LPUART_Type *)LPUART7_BASE) /** Peripheral LPUART8 base address */ #define LPUART8_BASE (0x426A0000u) /** Peripheral LPUART8 base pointer */ #define LPUART8 ((LPUART_Type *)LPUART8_BASE) /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 } /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- M7_A7_APB_MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_A7_APB_MCM_Peripheral_Access_Layer M7_A7_APB_MCM Peripheral Access Layer * @{ */ /** M7_A7_APB_MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[36]; __IO uint32_t ERR_INFO_EN; /**< Error Info Enable, offset: 0x24 */ uint8_t RESERVED_1[20]; __I uint32_t ITCM_ECC_SINGLE_ERROR_INFO; /**< ITCM single-bit ECC Error Information, offset: 0x3C */ __I uint32_t ITCM_ECC_SINGLE_ERROR_ADDR; /**< ITCM single-bit ECC Error Address Register, offset: 0x40 */ __I uint32_t ITCM_ECC_SINGLE_ERROR_DATA_LSB; /**< ITCM single-bit ECC Error Data Register, offset: 0x44 */ __I uint32_t ITCM_ECC_SINGLE_ERROR_DATA_MSB; /**< ITCM single-bit ECC Error Data Register, offset: 0x48 */ __I uint32_t ITCM_ECC_MULTI_ERROR_INFO; /**< ITCM multi-bit ECC Error Information Register, offset: 0x4C */ __I uint32_t ITCM_ECC_MULTI_ERROR_ADDR; /**< ITCM multi-bit ECC Error Address Register, offset: 0x50 */ __I uint32_t ITCM_ECC_MULTI_ERROR_DATA_LSB; /**< ITCM multi-bit ECC Error Data Register, offset: 0x54 */ __I uint32_t ITCM_ECC_MULTI_ERROR_DATA_MSB; /**< ITCM multi-bit ECC Error Data Register, offset: 0x58 */ __I uint32_t D0TCM_ECC_SINGLE_ERROR_INFO; /**< D0TCM single-bit ECC Error Information Register, offset: 0x5C */ __I uint32_t D0TCM_ECC_SINGLE_ERROR_ADDR; /**< D0TCM single-bit ECC Error Address Register, offset: 0x60 */ __I uint32_t D0TCM_ECC_SINGLE_ERROR_DATA; /**< D0TCM single-bit ECC Error Data Register, offset: 0x64 */ __I uint32_t D0TCM_ECC_MULTI_ERROR_INFO; /**< D0TCM multi-bit ECC Error Information Register, offset: 0x68 */ __I uint32_t D0TCM_ECC_MULTI_ERROR_ADDR; /**< D0TCM multi-bit ECC Error Address Register, offset: 0x6C */ __I uint32_t D0TCM_ECC_MULTI_ERROR_DATA; /**< D0TCM multi-bit ECC Error Data Register, offset: 0x70 */ __I uint32_t D1TCM_ECC_SINGLE_ERROR_INFO; /**< D1TCM single-bit ECC Error Information Register, offset: 0x74 */ __I uint32_t D1TCM_ECC_SINGLE_ERROR_ADDR; /**< D1TCM single-bit ECC Error Address Register, offset: 0x78 */ __I uint32_t D1TCM_ECC_SINGLE_ERROR_DATA; /**< D1TCM single-bit ECC Error Data Register, offset: 0x7C */ __I uint32_t D1TCM_ECC_MULTI_ERROR_INFO; /**< D1TCM multi-bit ECC Error Information Register, offset: 0x80 */ __I uint32_t D1TCM_ECC_MULTI_ERROR_ADDR; /**< D1TCM multi-bit ECC Error Address Register, offset: 0x84 */ __I uint32_t D1TCM_ECC_MULTI_ERROR_DATA; /**< D1TCM multi-bit ECC Error Data Register, offset: 0x88 */ uint8_t RESERVED_2[16]; __IO uint32_t FCCU_SW_FAULTS; /**< FCCU Software Faults, offset: 0x9C */ } M7_A7_APB_MCM_Type; /* ---------------------------------------------------------------------------- -- M7_A7_APB_MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_A7_APB_MCM_Register_Masks M7_A7_APB_MCM Register Masks * @{ */ /*! @name ERR_INFO_EN - Error Info Enable */ /*! @{ */ #define M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRM_INFO_EN_MASK (0x100U) #define M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRM_INFO_EN_SHIFT (8U) /*! ITCM_ERRM_INFO_EN - ITCM Access multi bit ECC Error Info Status Enable * 0b0..Masked * 0b1..Enabled */ #define M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRM_INFO_EN(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRM_INFO_EN_SHIFT)) & M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRM_INFO_EN_MASK) #define M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRS_INFO_EN_MASK (0x200U) #define M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRS_INFO_EN_SHIFT (9U) /*! ITCM_ERRS_INFO_EN - ITCM Access single bit ECC Error Info Status Enable * 0b0..Masked * 0b1..Enabled */ #define M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRS_INFO_EN(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRS_INFO_EN_SHIFT)) & M7_A7_APB_MCM_ERR_INFO_EN_ITCM_ERRS_INFO_EN_MASK) #define M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRM_INFO_EN_MASK (0x400U) #define M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRM_INFO_EN_SHIFT (10U) /*! D0TCM_ERRM_INFO_EN - D0TCM Access multi bit ECC Error Info Status Enable * 0b0..Masked * 0b1..Enabled */ #define M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRM_INFO_EN(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRM_INFO_EN_SHIFT)) & M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRM_INFO_EN_MASK) #define M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRS_INFO_EN_MASK (0x800U) #define M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRS_INFO_EN_SHIFT (11U) /*! D0TCM_ERRS_INFO_EN - D0TCM Access single bit ECC Error Info Status Enable * 0b0..Masked * 0b1..Enabled */ #define M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRS_INFO_EN(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRS_INFO_EN_SHIFT)) & M7_A7_APB_MCM_ERR_INFO_EN_D0TCM_ERRS_INFO_EN_MASK) #define M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRM_INFO_EN_MASK (0x1000U) #define M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRM_INFO_EN_SHIFT (12U) /*! D1TCM_ERRM_INFO_EN - D1TCM Access multi bit ECC Error Info Status Enable * 0b0..Masked * 0b1..Enabled */ #define M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRM_INFO_EN(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRM_INFO_EN_SHIFT)) & M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRM_INFO_EN_MASK) #define M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRS_INFO_EN_MASK (0x2000U) #define M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRS_INFO_EN_SHIFT (13U) /*! D1TCM_ERRS_INFO_EN - D1TCM Access single bit ECC Error Info Status Enable * 0b0..Masked * 0b1..Enabled */ #define M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRS_INFO_EN(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRS_INFO_EN_SHIFT)) & M7_A7_APB_MCM_ERR_INFO_EN_D1TCM_ERRS_INFO_EN_MASK) /*! @} */ /*! @name ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U) /*! ITCM_ECCS_EFW - Read or write of the access * 0b0..Read * 0b1..Write */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U) /*! ITCM_ECCS_EFSIZ - Size of the access * 0b000..8-bit * 0b001..16-bit * 0b010..32-bit * 0b011..64-bit * 0b100-0b111.. */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U) /*! ITCM_ECCS_EFMST - Encodes the requestor of the access * 0b0000..Instruction fetch. * 0b0001..Data access. * 0b0010..Vector fetch on automated exception entry. * 0b0011..AHB slave access. * 0b0100..Debugger access. * 0b0101..MBIST access. * 0b1001..Software data access from store queue. * 0b1011..AHB slave access from store queue. * 0b1100..Debugger access from store queue. * 0b0110.. * 0b0111.. * 0b1000.. * 0b1010.. * 0b1101.. * 0b1110.. * 0b1111.. */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U) /*! ITCM_ECCS_EFPRT - Privilege level of access * 0b0000..User * 0b0010..Privileged * 0b0001.. * 0b0011-0b1111.. */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U) /*! Reserved - Reserved */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK) /*! @} */ /*! @name ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! ITCM_ECCS_ERRED_ADDR - ITCM single-bit ECC error address */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK) /*! @} */ /*! @name ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U) /*! ITCM_ECCS_ERRED_DATA_LSB - ITCM single-bit ECC error data [31:0] */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK) /*! @} */ /*! @name ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U) /*! ITCM_ECCS_ERRED_DATA_MSB - ITCM single-bit ECC error data [63:32] */ #define M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK) /*! @} */ /*! @name ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U) /*! ITCM_ECCM_EFW - ITCM multi-bit ECC error corresponding tcm_wr value */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U) /*! ITCM_ECCM_EFSIZ - ITCM multi-bit ECC error corresponding tcm access size */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U) /*! ITCM_ECCM_EFMST - ITCM multi-bit ECC error corresponding tcm_master */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U) /*! ITCM_ECCM_EFPRT - ITCM multi-bit ECC error corresponding tcm_priv */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U) /*! Reserved - Reserved */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK) /*! @} */ /*! @name ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! ITCM_ECCM_ERRED_ADDR - ITCM multi-bit ECC error address */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK) /*! @} */ /*! @name ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U) /*! ITCM_ECCM_ERRED_DATA_LSB - ITCM multi-bit ECC error data [31:0] */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK) /*! @} */ /*! @name ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U) /*! ITCM_ECCM_ERRED_DATA_MSB - ITCM multi-bit ECC error data [63:32] */ #define M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT)) & M7_A7_APB_MCM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK) /*! @} */ /*! @name D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register */ /*! @{ */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U) /*! D0TCM_ECCS_EFW - D0TCM single-bit ECC error corresponding tcm_wr value */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U) /*! D0TCM_ECCS_EFSIZ - D0TCM single-bit ECC error corresponding tcm access size */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U) /*! D0TCM_ECCS_EFMST - D0TCM single-bit ECC error corresponding tcm_master */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U) /*! D0TCM_ECCS_EFPRT - D0TCM single-bit ECC error corresponding tcm_priv */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK) /*! @} */ /*! @name D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register */ /*! @{ */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! D0TCM_ECCS_ERRED_ADDR - D0TCM single-bit ECC error address */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK) /*! @} */ /*! @name D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U) /*! D0TCM_ECCS_ERRED_DATA - D0TCM single-bit ECC error data */ #define M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK) /*! @} */ /*! @name D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register */ /*! @{ */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U) /*! D0TCM_ECCM_EFW - D0TCM multi-bit ECC error corresponding tcm_wr value */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U) /*! D0TCM_ECCM_EFSIZ - D0TCM multi-bit ECC error corresponding tcm access size */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U) /*! D0TCM_ECCM_EFMST - D0TCM multi-bit ECC error corresponding tcm_master */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U) /*! D0TCM_ECCM_EFPRT - D0TCM multi-bit ECC error corresponding tcm_priv */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK) /*! @} */ /*! @name D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register */ /*! @{ */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! D0TCM_ECCM_ERRED_ADDR - D0TCM multi-bit ECC error address */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK) /*! @} */ /*! @name D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U) /*! D0TCM_ECCM_ERRED_DATA - D0TCM multi-bit ECC error data */ #define M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT)) & M7_A7_APB_MCM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK) /*! @} */ /*! @name D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register */ /*! @{ */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U) /*! D1TCM_ECCS_EFW - D1TCM single-bit ECC error corresponding tcm_wr value */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U) /*! D1TCM_ECCS_EFSIZ - D1TCM single-bit ECC error corresponding tcm access size */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U) /*! D1TCM_ECCS_EFMST - D1TCM single-bit ECC error corresponding tcm_master */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U) /*! D1TCM_ECCS_EFPRT - D1TCM single-bit ECC error corresponding tcm_priv */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK) /*! @} */ /*! @name D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register */ /*! @{ */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! D1TCM_ECCS_ERRED_ADDR - D1TCM single-bit ECC error address */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK) /*! @} */ /*! @name D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U) /*! D1TCM_ECCS_ERRED_DATA - D1TCM single-bit ECC error data */ #define M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK) /*! @} */ /*! @name D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register */ /*! @{ */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U) /*! D1TCM_ECCM_EFW - D1TCM multi-bit ECC error corresponding tcm_wr value */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U) /*! D1TCM_ECCM_EFSIZ - D1TCM multi-bit ECC error corresponding tcm access size */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U) /*! D1TCM_ECCM_EFMST - D1TCM multi-bit ECC error corresponding tcm_master */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U) /*! D1TCM_ECCM_EFPRT - D1TCM multi-bit ECC error corresponding tcm_priv */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK) /*! @} */ /*! @name D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register */ /*! @{ */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! D1TCM_ECCM_ERRED_ADDR - D1TCM multi-bit ECC error address */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK) /*! @} */ /*! @name D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register */ /*! @{ */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU) #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U) /*! D1TCM_ECCM_ERRED_DATA - D1TCM multi-bit ECC error data */ #define M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & M7_A7_APB_MCM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK) /*! @} */ /*! @name FCCU_SW_FAULTS - FCCU Software Faults */ /*! @{ */ #define M7_A7_APB_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_MASK (0x3FU) #define M7_A7_APB_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_SHIFT (0U) /*! FCCU_SW_FAULTS - FCCU Software Faults */ #define M7_A7_APB_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS(x) (((uint32_t)(((uint32_t)(x)) << M7_A7_APB_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_SHIFT)) & M7_A7_APB_MCM_FCCU_SW_FAULTS_FCCU_SW_FAULTS_MASK) /*! @} */ /*! * @} */ /* end of group M7_A7_APB_MCM_Register_Masks */ /* M7_A7_APB_MCM - Peripheral instance base addresses */ /** Peripheral M7__A7_APB_MCM1 base address */ #define M7__A7_APB_MCM1_BASE (0x4A0A0000u) /** Peripheral M7__A7_APB_MCM1 base pointer */ #define M7__A7_APB_MCM1 ((M7_A7_APB_MCM_Type *)M7__A7_APB_MCM1_BASE) /** Array initializer of M7_A7_APB_MCM peripheral base addresses */ #define M7_A7_APB_MCM_BASE_ADDRS { M7__A7_APB_MCM1_BASE } /** Array initializer of M7_A7_APB_MCM peripheral base pointers */ #define M7_A7_APB_MCM_BASE_PTRS { M7__A7_APB_MCM1 } /*! * @} */ /* end of group M7_A7_APB_MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- M7_CMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_CMU_Peripheral_Access_Layer M7_CMU Peripheral Access Layer * @{ */ /** M7_CMU - Register Layout Typedef */ typedef struct { __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ __IO uint32_t SR; /**< Status Register, offset: 0x10 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ } M7_CMU_Type; /* ---------------------------------------------------------------------------- -- M7_CMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_CMU_Register_Masks M7_CMU Register Masks * @{ */ /*! @name GCR - Global Configuration Register */ /*! @{ */ #define M7_CMU_GCR_FCE_MASK (0x1U) #define M7_CMU_GCR_FCE_SHIFT (0U) /*! FCE - Frequency Check Enable * 0b0..Stops frequency checking * 0b1..Starts frequency checking */ #define M7_CMU_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_GCR_FCE_SHIFT)) & M7_CMU_GCR_FCE_MASK) /*! @} */ /*! @name RCCR - Reference Count Configuration Register */ /*! @{ */ #define M7_CMU_RCCR_REF_CNT_MASK (0xFFFFU) #define M7_CMU_RCCR_REF_CNT_SHIFT (0U) /*! REF_CNT - Reference clock count */ #define M7_CMU_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_RCCR_REF_CNT_SHIFT)) & M7_CMU_RCCR_REF_CNT_MASK) /*! @} */ /*! @name HTCR - High Threshold Configuration Register */ /*! @{ */ #define M7_CMU_HTCR_HFREF_MASK (0xFFFFFFU) #define M7_CMU_HTCR_HFREF_SHIFT (0U) /*! HFREF - High frequency reference threshold */ #define M7_CMU_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_HTCR_HFREF_SHIFT)) & M7_CMU_HTCR_HFREF_MASK) /*! @} */ /*! @name LTCR - Low Threshold Configuration Register */ /*! @{ */ #define M7_CMU_LTCR_LFREF_MASK (0xFFFFFFU) #define M7_CMU_LTCR_LFREF_SHIFT (0U) /*! LFREF - Low Frequency Reference Threshold */ #define M7_CMU_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_LTCR_LFREF_SHIFT)) & M7_CMU_LTCR_LFREF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define M7_CMU_SR_FLL_MASK (0x1U) #define M7_CMU_SR_FLL_SHIFT (0U) /*! FLL - Frequency lower than low frequency reference threshold event status * 0b0..No FLL event * 0b1..FLL event occurred */ #define M7_CMU_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_SR_FLL_SHIFT)) & M7_CMU_SR_FLL_MASK) #define M7_CMU_SR_FHH_MASK (0x2U) #define M7_CMU_SR_FHH_SHIFT (1U) /*! FHH - Frequency higher than high frequency reference threshold event status * 0b0..No FHH event * 0b1..FHH event occurred */ #define M7_CMU_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_SR_FHH_SHIFT)) & M7_CMU_SR_FHH_MASK) #define M7_CMU_SR_RS_MASK (0x10U) #define M7_CMU_SR_RS_SHIFT (4U) /*! RS - Run Status * 0b0..Frequency check stopped * 0b1..Frequency check running */ #define M7_CMU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_SR_RS_SHIFT)) & M7_CMU_SR_RS_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define M7_CMU_IER_FLLAIE_MASK (0x4U) #define M7_CMU_IER_FLLAIE_SHIFT (2U) /*! FLLAIE - Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FLL event interrupt disabled * 0b1..Asynchronous FLL event interrupt enabled */ #define M7_CMU_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_IER_FLLAIE_SHIFT)) & M7_CMU_IER_FLLAIE_MASK) #define M7_CMU_IER_FHHAIE_MASK (0x8U) #define M7_CMU_IER_FHHAIE_SHIFT (3U) /*! FHHAIE - Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FHH event interrupt disabled * 0b1..Asynchronous FHH event interrupt enabled */ #define M7_CMU_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << M7_CMU_IER_FHHAIE_SHIFT)) & M7_CMU_IER_FHHAIE_MASK) /*! @} */ /*! * @} */ /* end of group M7_CMU_Register_Masks */ /* M7_CMU - Peripheral instance base addresses */ /** Peripheral M7__CMU_M0 base address */ #define M7__CMU_M0_BASE (0x4A080000u) /** Peripheral M7__CMU_M0 base pointer */ #define M7__CMU_M0 ((M7_CMU_Type *)M7__CMU_M0_BASE) /** Peripheral M7__CMU_M1 base address */ #define M7__CMU_M1_BASE (0x4A090000u) /** Peripheral M7__CMU_M1 base pointer */ #define M7__CMU_M1 ((M7_CMU_Type *)M7__CMU_M1_BASE) /** Array initializer of M7_CMU peripheral base addresses */ #define M7_CMU_BASE_ADDRS { M7__CMU_M0_BASE, M7__CMU_M1_BASE } /** Array initializer of M7_CMU peripheral base pointers */ #define M7_CMU_BASE_PTRS { M7__CMU_M0, M7__CMU_M1 } /*! * @} */ /* end of group M7_CMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- M7_EIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_EIM_Peripheral_Access_Layer M7_EIM Peripheral Access Layer * @{ */ /** M7_EIM - Register Layout Typedef */ typedef struct { __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ uint8_t RESERVED_0[248]; __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ __IO uint32_t EICHD0_WORD2; /**< Error Injection Channel Descriptor 0, Word2, offset: 0x108 */ uint8_t RESERVED_1[52]; __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ __IO uint32_t EICHD1_WORD2; /**< Error Injection Channel Descriptor 1, Word2, offset: 0x148 */ __IO uint32_t EICHD1_WORD3; /**< Error Injection Channel Descriptor 1, Word3, offset: 0x14C */ __IO uint32_t EICHD1_WORD4; /**< Error Injection Channel Descriptor 1, Word4, offset: 0x150 */ uint8_t RESERVED_2[44]; __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ __IO uint32_t EICHD2_WORD2; /**< Error Injection Channel Descriptor 2, Word2, offset: 0x188 */ __IO uint32_t EICHD2_WORD3; /**< Error Injection Channel Descriptor 2, Word3, offset: 0x18C */ __IO uint32_t EICHD2_WORD4; /**< Error Injection Channel Descriptor 2, Word4, offset: 0x190 */ uint8_t RESERVED_3[44]; __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ __IO uint32_t EICHD3_WORD2; /**< Error Injection Channel Descriptor 3, Word2, offset: 0x1C8 */ __IO uint32_t EICHD3_WORD3; /**< Error Injection Channel Descriptor 3, Word3, offset: 0x1CC */ __IO uint32_t EICHD3_WORD4; /**< Error Injection Channel Descriptor 3, Word4, offset: 0x1D0 */ uint8_t RESERVED_4[44]; __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ __IO uint32_t EICHD4_WORD2; /**< Error Injection Channel Descriptor 4, Word2, offset: 0x208 */ __IO uint32_t EICHD4_WORD3; /**< Error Injection Channel Descriptor 4, Word3, offset: 0x20C */ __IO uint32_t EICHD4_WORD4; /**< Error Injection Channel Descriptor 4, Word4, offset: 0x210 */ uint8_t RESERVED_5[44]; __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ uint8_t RESERVED_6[56]; __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ uint8_t RESERVED_7[56]; __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ __IO uint32_t EICHD7_WORD2; /**< Error Injection Channel Descriptor 7, Word2, offset: 0x2C8 */ uint8_t RESERVED_8[52]; __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ } M7_EIM_Type; /* ---------------------------------------------------------------------------- -- M7_EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_EIM_Register_Masks M7_EIM Register Masks * @{ */ /*! @name EIMCR - Error Injection Module Configuration Register */ /*! @{ */ #define M7_EIM_EIMCR_GEIEN_MASK (0x1U) #define M7_EIM_EIMCR_GEIEN_SHIFT (0U) /*! GEIEN - Global Error Injection Enable * 0b0..Disabled * 0b1..Enabled */ #define M7_EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EIMCR_GEIEN_SHIFT)) & M7_EIM_EIMCR_GEIEN_MASK) /*! @} */ /*! @name EICHEN - Error Injection Channel Enable register */ /*! @{ */ #define M7_EIM_EICHEN_EICH8EN_MASK (0x800000U) #define M7_EIM_EICHEN_EICH8EN_SHIFT (23U) /*! EICH8EN - Error Injection Channel 8 Enable * 0b0..Error injection is disabled on Error Injection Channel 8 * 0b1..Error injection is enabled on Error Injection Channel 8 */ #define M7_EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH8EN_SHIFT)) & M7_EIM_EICHEN_EICH8EN_MASK) #define M7_EIM_EICHEN_EICH7EN_MASK (0x1000000U) #define M7_EIM_EICHEN_EICH7EN_SHIFT (24U) /*! EICH7EN - Error Injection Channel 7 Enable * 0b0..Error injection is disabled on Error Injection Channel 7 * 0b1..Error injection is enabled on Error Injection Channel 7 */ #define M7_EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH7EN_SHIFT)) & M7_EIM_EICHEN_EICH7EN_MASK) #define M7_EIM_EICHEN_EICH6EN_MASK (0x2000000U) #define M7_EIM_EICHEN_EICH6EN_SHIFT (25U) /*! EICH6EN - Error Injection Channel 6 Enable * 0b0..Error injection is disabled on Error Injection Channel 6 * 0b1..Error injection is enabled on Error Injection Channel 6 */ #define M7_EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH6EN_SHIFT)) & M7_EIM_EICHEN_EICH6EN_MASK) #define M7_EIM_EICHEN_EICH5EN_MASK (0x4000000U) #define M7_EIM_EICHEN_EICH5EN_SHIFT (26U) /*! EICH5EN - Error Injection Channel 5 Enable * 0b0..Error injection is disabled on Error Injection Channel 5 * 0b1..Error injection is enabled on Error Injection Channel 5 */ #define M7_EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH5EN_SHIFT)) & M7_EIM_EICHEN_EICH5EN_MASK) #define M7_EIM_EICHEN_EICH4EN_MASK (0x8000000U) #define M7_EIM_EICHEN_EICH4EN_SHIFT (27U) /*! EICH4EN - Error Injection Channel 4 Enable * 0b0..Error injection is disabled on Error Injection Channel 4 * 0b1..Error injection is enabled on Error Injection Channel 4 */ #define M7_EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH4EN_SHIFT)) & M7_EIM_EICHEN_EICH4EN_MASK) #define M7_EIM_EICHEN_EICH3EN_MASK (0x10000000U) #define M7_EIM_EICHEN_EICH3EN_SHIFT (28U) /*! EICH3EN - Error Injection Channel 3 Enable * 0b0..Error injection is disabled on Error Injection Channel 3 * 0b1..Error injection is enabled on Error Injection Channel 3 */ #define M7_EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH3EN_SHIFT)) & M7_EIM_EICHEN_EICH3EN_MASK) #define M7_EIM_EICHEN_EICH2EN_MASK (0x20000000U) #define M7_EIM_EICHEN_EICH2EN_SHIFT (29U) /*! EICH2EN - Error Injection Channel 2 Enable * 0b0..Error injection is disabled on Error Injection Channel 2 * 0b1..Error injection is enabled on Error Injection Channel 2 */ #define M7_EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH2EN_SHIFT)) & M7_EIM_EICHEN_EICH2EN_MASK) #define M7_EIM_EICHEN_EICH1EN_MASK (0x40000000U) #define M7_EIM_EICHEN_EICH1EN_SHIFT (30U) /*! EICH1EN - Error Injection Channel 1 Enable * 0b0..Error injection is disabled on Error Injection Channel 1 * 0b1..Error injection is enabled on Error Injection Channel 1 */ #define M7_EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH1EN_SHIFT)) & M7_EIM_EICHEN_EICH1EN_MASK) #define M7_EIM_EICHEN_EICH0EN_MASK (0x80000000U) #define M7_EIM_EICHEN_EICH0EN_SHIFT (31U) /*! EICH0EN - Error Injection Channel 0 Enable * 0b0..Error injection is disabled on Error Injection Channel 0 * 0b1..Error injection is enabled on Error Injection Channel 0 */ #define M7_EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHEN_EICH0EN_SHIFT)) & M7_EIM_EICHEN_EICH0EN_MASK) /*! @} */ /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ /*! @{ */ #define M7_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFFFC0000U) #define M7_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (18U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ /*! @{ */ #define M7_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFU) #define M7_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD2 - Error Injection Channel Descriptor 0, Word2 */ /*! @{ */ #define M7_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define M7_EIM_EICHD0_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT)) & M7_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ /*! @{ */ #define M7_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFFFF0000U) #define M7_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (16U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ /*! @{ */ #define M7_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD2 - Error Injection Channel Descriptor 1, Word2 */ /*! @{ */ #define M7_EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define M7_EIM_EICHD1_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT)) & M7_EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD3 - Error Injection Channel Descriptor 1, Word3 */ /*! @{ */ #define M7_EIM_EICHD1_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD1_WORD3_B8_11DATA_MASK_SHIFT (0U) /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */ #define M7_EIM_EICHD1_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD1_WORD3_B8_11DATA_MASK_SHIFT)) & M7_EIM_EICHD1_WORD3_B8_11DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD4 - Error Injection Channel Descriptor 1, Word4 */ /*! @{ */ #define M7_EIM_EICHD1_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD1_WORD4_B12_15DATA_MASK_SHIFT (0U) /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */ #define M7_EIM_EICHD1_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD1_WORD4_B12_15DATA_MASK_SHIFT)) & M7_EIM_EICHD1_WORD4_B12_15DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ /*! @{ */ #define M7_EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) #define M7_EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (4U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ /*! @{ */ #define M7_EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFU) #define M7_EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD2 - Error Injection Channel Descriptor 2, Word2 */ /*! @{ */ #define M7_EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define M7_EIM_EICHD2_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT)) & M7_EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD3 - Error Injection Channel Descriptor 2, Word3 */ /*! @{ */ #define M7_EIM_EICHD2_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD2_WORD3_B8_11DATA_MASK_SHIFT (0U) /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */ #define M7_EIM_EICHD2_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD2_WORD3_B8_11DATA_MASK_SHIFT)) & M7_EIM_EICHD2_WORD3_B8_11DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD4 - Error Injection Channel Descriptor 2, Word4 */ /*! @{ */ #define M7_EIM_EICHD2_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD2_WORD4_B12_15DATA_MASK_SHIFT (0U) /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */ #define M7_EIM_EICHD2_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD2_WORD4_B12_15DATA_MASK_SHIFT)) & M7_EIM_EICHD2_WORD4_B12_15DATA_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ /*! @{ */ #define M7_EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) #define M7_EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (4U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ /*! @{ */ #define M7_EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD2 - Error Injection Channel Descriptor 3, Word2 */ /*! @{ */ #define M7_EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define M7_EIM_EICHD3_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT)) & M7_EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD3 - Error Injection Channel Descriptor 3, Word3 */ /*! @{ */ #define M7_EIM_EICHD3_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD3_WORD3_B8_11DATA_MASK_SHIFT (0U) /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */ #define M7_EIM_EICHD3_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD3_WORD3_B8_11DATA_MASK_SHIFT)) & M7_EIM_EICHD3_WORD3_B8_11DATA_MASK_MASK) /*! @} */ /*! @name EICHD3_WORD4 - Error Injection Channel Descriptor 3, Word4 */ /*! @{ */ #define M7_EIM_EICHD3_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD3_WORD4_B12_15DATA_MASK_SHIFT (0U) /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */ #define M7_EIM_EICHD3_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD3_WORD4_B12_15DATA_MASK_SHIFT)) & M7_EIM_EICHD3_WORD4_B12_15DATA_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ /*! @{ */ #define M7_EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFFFFFFF0U) #define M7_EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (4U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ /*! @{ */ #define M7_EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD2 - Error Injection Channel Descriptor 4, Word2 */ /*! @{ */ #define M7_EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define M7_EIM_EICHD4_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT)) & M7_EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD3 - Error Injection Channel Descriptor 4, Word3 */ /*! @{ */ #define M7_EIM_EICHD4_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD4_WORD3_B8_11DATA_MASK_SHIFT (0U) /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */ #define M7_EIM_EICHD4_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD4_WORD3_B8_11DATA_MASK_SHIFT)) & M7_EIM_EICHD4_WORD3_B8_11DATA_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD4 - Error Injection Channel Descriptor 4, Word4 */ /*! @{ */ #define M7_EIM_EICHD4_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD4_WORD4_B12_15DATA_MASK_SHIFT (0U) /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */ #define M7_EIM_EICHD4_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD4_WORD4_B12_15DATA_MASK_SHIFT)) & M7_EIM_EICHD4_WORD4_B12_15DATA_MASK_MASK) /*! @} */ /*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ /*! @{ */ #define M7_EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define M7_EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ /*! @{ */ #define M7_EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ /*! @{ */ #define M7_EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFE000000U) #define M7_EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (25U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ /*! @{ */ #define M7_EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ /*! @{ */ #define M7_EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define M7_EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ /*! @{ */ #define M7_EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD7_WORD2 - Error Injection Channel Descriptor 7, Word2 */ /*! @{ */ #define M7_EIM_EICHD7_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define M7_EIM_EICHD7_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define M7_EIM_EICHD7_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD7_WORD2_B4_7DATA_MASK_SHIFT)) & M7_EIM_EICHD7_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ /*! @{ */ #define M7_EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xC0000000U) #define M7_EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (30U) /*! CHKBIT_MASK - Checkbit Mask */ #define M7_EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & M7_EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ /*! @{ */ #define M7_EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0x1U) #define M7_EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define M7_EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << M7_EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & M7_EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! * @} */ /* end of group M7_EIM_Register_Masks */ /* M7_EIM - Peripheral instance base addresses */ /** Peripheral M7__EIM base address */ #define M7__EIM_BASE (0x4A060000u) /** Peripheral M7__EIM base pointer */ #define M7__EIM ((M7_EIM_Type *)M7__EIM_BASE) /** Array initializer of M7_EIM peripheral base addresses */ #define M7_EIM_BASE_ADDRS { M7__EIM_BASE } /** Array initializer of M7_EIM peripheral base pointers */ #define M7_EIM_BASE_PTRS { M7__EIM } /*! * @} */ /* end of group M7_EIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- M7_ERM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_ERM_Peripheral_Access_Layer M7_ERM Peripheral Access Layer * @{ */ /** M7_ERM - Register Layout Typedef */ typedef struct { __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ uint8_t RESERVED_0[12]; __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ uint8_t RESERVED_1[244]; __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ uint8_t RESERVED_2[12]; __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ uint8_t RESERVED_3[12]; __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */ uint8_t RESERVED_4[12]; __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */ uint8_t RESERVED_5[20]; __I uint32_t EAR5; /**< ERM Memory 5 Error Address Register, offset: 0x150 */ __I uint32_t SYN5; /**< ERM Memory 5 Syndrome Register, offset: 0x154 */ __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */ uint8_t RESERVED_6[4]; __I uint32_t EAR6; /**< ERM Memory 6 Error Address Register, offset: 0x160 */ __I uint32_t SYN6; /**< ERM Memory 6 Syndrome Register, offset: 0x164 */ __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */ uint8_t RESERVED_7[4]; __I uint32_t EAR7; /**< ERM Memory 7 Error Address Register, offset: 0x170 */ __I uint32_t SYN7; /**< ERM Memory 7 Syndrome Register, offset: 0x174 */ __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */ } M7_ERM_Type; /* ---------------------------------------------------------------------------- -- M7_ERM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_ERM_Register_Masks M7_ERM Register Masks * @{ */ /*! @name CR0 - ERM Configuration Register 0 */ /*! @{ */ #define M7_ERM_CR0_ENCIE7_MASK (0x4U) #define M7_ERM_CR0_ENCIE7_SHIFT (2U) /*! ENCIE7 - ENCIE7 * 0b0..Interrupt notification of Memory 7 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 7 non-correctable error events is enabled. */ #define M7_ERM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ENCIE7_SHIFT)) & M7_ERM_CR0_ENCIE7_MASK) #define M7_ERM_CR0_ESCIE7_MASK (0x8U) #define M7_ERM_CR0_ESCIE7_SHIFT (3U) /*! ESCIE7 - ESCIE7 * 0b0..Interrupt notification of Memory 7 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 7 single-bit correction events is enabled. */ #define M7_ERM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ESCIE7_SHIFT)) & M7_ERM_CR0_ESCIE7_MASK) #define M7_ERM_CR0_ENCIE6_MASK (0x40U) #define M7_ERM_CR0_ENCIE6_SHIFT (6U) /*! ENCIE6 - ENCIE6 * 0b0..Interrupt notification of Memory 6 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 6 non-correctable error events is enabled. */ #define M7_ERM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ENCIE6_SHIFT)) & M7_ERM_CR0_ENCIE6_MASK) #define M7_ERM_CR0_ESCIE6_MASK (0x80U) #define M7_ERM_CR0_ESCIE6_SHIFT (7U) /*! ESCIE6 - ESCIE6 * 0b0..Interrupt notification of Memory 6 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 6 single-bit correction events is enabled. */ #define M7_ERM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ESCIE6_SHIFT)) & M7_ERM_CR0_ESCIE6_MASK) #define M7_ERM_CR0_ENCIE5_MASK (0x400U) #define M7_ERM_CR0_ENCIE5_SHIFT (10U) /*! ENCIE5 - ENCIE5 * 0b0..Interrupt notification of Memory 5 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 5 non-correctable error events is enabled. */ #define M7_ERM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ENCIE5_SHIFT)) & M7_ERM_CR0_ENCIE5_MASK) #define M7_ERM_CR0_ESCIE5_MASK (0x800U) #define M7_ERM_CR0_ESCIE5_SHIFT (11U) /*! ESCIE5 - ESCIE5 * 0b0..Interrupt notification of Memory 5 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 5 single-bit correction events is enabled. */ #define M7_ERM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ESCIE5_SHIFT)) & M7_ERM_CR0_ESCIE5_MASK) #define M7_ERM_CR0_ENCIE3_MASK (0x40000U) #define M7_ERM_CR0_ENCIE3_SHIFT (18U) /*! ENCIE3 - ENCIE3 * 0b0..Interrupt notification of Memory 3 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 3 non-correctable error events is enabled. */ #define M7_ERM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ENCIE3_SHIFT)) & M7_ERM_CR0_ENCIE3_MASK) #define M7_ERM_CR0_ESCIE3_MASK (0x80000U) #define M7_ERM_CR0_ESCIE3_SHIFT (19U) /*! ESCIE3 - ESCIE3 * 0b0..Interrupt notification of Memory 3 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 3 single-bit correction events is enabled. */ #define M7_ERM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ESCIE3_SHIFT)) & M7_ERM_CR0_ESCIE3_MASK) #define M7_ERM_CR0_ENCIE2_MASK (0x400000U) #define M7_ERM_CR0_ENCIE2_SHIFT (22U) /*! ENCIE2 - ENCIE2 * 0b0..Interrupt notification of Memory 2 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 2 non-correctable error events is enabled. */ #define M7_ERM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ENCIE2_SHIFT)) & M7_ERM_CR0_ENCIE2_MASK) #define M7_ERM_CR0_ESCIE2_MASK (0x800000U) #define M7_ERM_CR0_ESCIE2_SHIFT (23U) /*! ESCIE2 - ESCIE2 * 0b0..Interrupt notification of Memory 2 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 2 single-bit correction events is enabled. */ #define M7_ERM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ESCIE2_SHIFT)) & M7_ERM_CR0_ESCIE2_MASK) #define M7_ERM_CR0_ENCIE1_MASK (0x4000000U) #define M7_ERM_CR0_ENCIE1_SHIFT (26U) /*! ENCIE1 - ENCIE1 * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. */ #define M7_ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ENCIE1_SHIFT)) & M7_ERM_CR0_ENCIE1_MASK) #define M7_ERM_CR0_ESCIE1_MASK (0x8000000U) #define M7_ERM_CR0_ESCIE1_SHIFT (27U) /*! ESCIE1 - ESCIE1 * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. */ #define M7_ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ESCIE1_SHIFT)) & M7_ERM_CR0_ESCIE1_MASK) #define M7_ERM_CR0_ENCIE0_MASK (0x40000000U) #define M7_ERM_CR0_ENCIE0_SHIFT (30U) /*! ENCIE0 - ENCIE0 * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. */ #define M7_ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ENCIE0_SHIFT)) & M7_ERM_CR0_ENCIE0_MASK) #define M7_ERM_CR0_ESCIE0_MASK (0x80000000U) #define M7_ERM_CR0_ESCIE0_SHIFT (31U) /*! ESCIE0 - ESCIE0 * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. */ #define M7_ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CR0_ESCIE0_SHIFT)) & M7_ERM_CR0_ESCIE0_MASK) /*! @} */ /*! @name SR0 - ERM Status Register 0 */ /*! @{ */ #define M7_ERM_SR0_NCE7_MASK (0x4U) #define M7_ERM_SR0_NCE7_SHIFT (2U) /*! NCE7 - NCE7 * 0b0..No non-correctable error event on Memory 7 detected. * 0b1..Non-correctable error event on Memory 7 detected. */ #define M7_ERM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_NCE7_SHIFT)) & M7_ERM_SR0_NCE7_MASK) #define M7_ERM_SR0_SBC7_MASK (0x8U) #define M7_ERM_SR0_SBC7_SHIFT (3U) /*! SBC7 - SBC7 * 0b0..No single-bit correction event on Memory 7 detected. * 0b1..Single-bit correction event on Memory 7 detected. */ #define M7_ERM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_SBC7_SHIFT)) & M7_ERM_SR0_SBC7_MASK) #define M7_ERM_SR0_NCE6_MASK (0x40U) #define M7_ERM_SR0_NCE6_SHIFT (6U) /*! NCE6 - NCE6 * 0b0..No non-correctable error event on Memory 6 detected. * 0b1..Non-correctable error event on Memory 6 detected. */ #define M7_ERM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_NCE6_SHIFT)) & M7_ERM_SR0_NCE6_MASK) #define M7_ERM_SR0_SBC6_MASK (0x80U) #define M7_ERM_SR0_SBC6_SHIFT (7U) /*! SBC6 - SBC6 * 0b0..No single-bit correction event on Memory 6 detected. * 0b1..Single-bit correction event on Memory 6 detected. */ #define M7_ERM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_SBC6_SHIFT)) & M7_ERM_SR0_SBC6_MASK) #define M7_ERM_SR0_NCE5_MASK (0x400U) #define M7_ERM_SR0_NCE5_SHIFT (10U) /*! NCE5 - NCE5 * 0b0..No non-correctable error event on Memory 5 detected. * 0b1..Non-correctable error event on Memory 5 detected. */ #define M7_ERM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_NCE5_SHIFT)) & M7_ERM_SR0_NCE5_MASK) #define M7_ERM_SR0_SBC5_MASK (0x800U) #define M7_ERM_SR0_SBC5_SHIFT (11U) /*! SBC5 - SBC5 * 0b0..No single-bit correction event on Memory 5 detected. * 0b1..Single-bit correction event on Memory 5 detected. */ #define M7_ERM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_SBC5_SHIFT)) & M7_ERM_SR0_SBC5_MASK) #define M7_ERM_SR0_NCE3_MASK (0x40000U) #define M7_ERM_SR0_NCE3_SHIFT (18U) /*! NCE3 - NCE3 * 0b0..No non-correctable error event on Memory 3 detected. * 0b1..Non-correctable error event on Memory 3 detected. */ #define M7_ERM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_NCE3_SHIFT)) & M7_ERM_SR0_NCE3_MASK) #define M7_ERM_SR0_SBC3_MASK (0x80000U) #define M7_ERM_SR0_SBC3_SHIFT (19U) /*! SBC3 - SBC3 * 0b0..No single-bit correction event on Memory 3 detected. * 0b1..Single-bit correction event on Memory 3 detected. */ #define M7_ERM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_SBC3_SHIFT)) & M7_ERM_SR0_SBC3_MASK) #define M7_ERM_SR0_NCE2_MASK (0x400000U) #define M7_ERM_SR0_NCE2_SHIFT (22U) /*! NCE2 - NCE2 * 0b0..No non-correctable error event on Memory 2 detected. * 0b1..Non-correctable error event on Memory 2 detected. */ #define M7_ERM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_NCE2_SHIFT)) & M7_ERM_SR0_NCE2_MASK) #define M7_ERM_SR0_SBC2_MASK (0x800000U) #define M7_ERM_SR0_SBC2_SHIFT (23U) /*! SBC2 - SBC2 * 0b0..No single-bit correction event on Memory 2 detected. * 0b1..Single-bit correction event on Memory 2 detected. */ #define M7_ERM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_SBC2_SHIFT)) & M7_ERM_SR0_SBC2_MASK) #define M7_ERM_SR0_NCE1_MASK (0x4000000U) #define M7_ERM_SR0_NCE1_SHIFT (26U) /*! NCE1 - NCE1 * 0b0..No non-correctable error event on Memory 1 detected. * 0b1..Non-correctable error event on Memory 1 detected. */ #define M7_ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_NCE1_SHIFT)) & M7_ERM_SR0_NCE1_MASK) #define M7_ERM_SR0_SBC1_MASK (0x8000000U) #define M7_ERM_SR0_SBC1_SHIFT (27U) /*! SBC1 - SBC1 * 0b0..No single-bit correction event on Memory 1 detected. * 0b1..Single-bit correction event on Memory 1 detected. */ #define M7_ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_SBC1_SHIFT)) & M7_ERM_SR0_SBC1_MASK) #define M7_ERM_SR0_NCE0_MASK (0x40000000U) #define M7_ERM_SR0_NCE0_SHIFT (30U) /*! NCE0 - NCE0 * 0b0..No non-correctable error event on Memory 0 detected. * 0b1..Non-correctable error event on Memory 0 detected. */ #define M7_ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_NCE0_SHIFT)) & M7_ERM_SR0_NCE0_MASK) #define M7_ERM_SR0_SBC0_MASK (0x80000000U) #define M7_ERM_SR0_SBC0_SHIFT (31U) /*! SBC0 - SBC0 * 0b0..No single-bit correction event on Memory 0 detected. * 0b1..Single-bit correction event on Memory 0 detected. */ #define M7_ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SR0_SBC0_SHIFT)) & M7_ERM_SR0_SBC0_MASK) /*! @} */ /*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ /*! @{ */ #define M7_ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) #define M7_ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define M7_ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & M7_ERM_CORR_ERR_CNT0_COUNT_MASK) /*! @} */ /*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ /*! @{ */ #define M7_ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) #define M7_ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define M7_ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & M7_ERM_CORR_ERR_CNT1_COUNT_MASK) /*! @} */ /*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ /*! @{ */ #define M7_ERM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) #define M7_ERM_CORR_ERR_CNT2_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define M7_ERM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & M7_ERM_CORR_ERR_CNT2_COUNT_MASK) /*! @} */ /*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ /*! @{ */ #define M7_ERM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) #define M7_ERM_CORR_ERR_CNT3_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define M7_ERM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & M7_ERM_CORR_ERR_CNT3_COUNT_MASK) /*! @} */ /*! @name EAR5 - ERM Memory 5 Error Address Register */ /*! @{ */ #define M7_ERM_EAR5_EAR_MASK (0xFFFFFFFFU) #define M7_ERM_EAR5_EAR_SHIFT (0U) /*! EAR - EAR */ #define M7_ERM_EAR5_EAR(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_EAR5_EAR_SHIFT)) & M7_ERM_EAR5_EAR_MASK) /*! @} */ /*! @name SYN5 - ERM Memory 5 Syndrome Register */ /*! @{ */ #define M7_ERM_SYN5_SYNDROME_MASK (0xFF000000U) #define M7_ERM_SYN5_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define M7_ERM_SYN5_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SYN5_SYNDROME_SHIFT)) & M7_ERM_SYN5_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ /*! @{ */ #define M7_ERM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) #define M7_ERM_CORR_ERR_CNT5_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define M7_ERM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & M7_ERM_CORR_ERR_CNT5_COUNT_MASK) /*! @} */ /*! @name EAR6 - ERM Memory 6 Error Address Register */ /*! @{ */ #define M7_ERM_EAR6_EAR_MASK (0xFFFFFFFFU) #define M7_ERM_EAR6_EAR_SHIFT (0U) /*! EAR - EAR */ #define M7_ERM_EAR6_EAR(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_EAR6_EAR_SHIFT)) & M7_ERM_EAR6_EAR_MASK) /*! @} */ /*! @name SYN6 - ERM Memory 6 Syndrome Register */ /*! @{ */ #define M7_ERM_SYN6_SYNDROME_MASK (0xFF000000U) #define M7_ERM_SYN6_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define M7_ERM_SYN6_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SYN6_SYNDROME_SHIFT)) & M7_ERM_SYN6_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ /*! @{ */ #define M7_ERM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) #define M7_ERM_CORR_ERR_CNT6_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define M7_ERM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & M7_ERM_CORR_ERR_CNT6_COUNT_MASK) /*! @} */ /*! @name EAR7 - ERM Memory 7 Error Address Register */ /*! @{ */ #define M7_ERM_EAR7_EAR_MASK (0xFFFFFFFFU) #define M7_ERM_EAR7_EAR_SHIFT (0U) /*! EAR - EAR */ #define M7_ERM_EAR7_EAR(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_EAR7_EAR_SHIFT)) & M7_ERM_EAR7_EAR_MASK) /*! @} */ /*! @name SYN7 - ERM Memory 7 Syndrome Register */ /*! @{ */ #define M7_ERM_SYN7_SYNDROME_MASK (0xFF000000U) #define M7_ERM_SYN7_SYNDROME_SHIFT (24U) /*! SYNDROME - SYNDROME */ #define M7_ERM_SYN7_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_SYN7_SYNDROME_SHIFT)) & M7_ERM_SYN7_SYNDROME_MASK) /*! @} */ /*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ /*! @{ */ #define M7_ERM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) #define M7_ERM_CORR_ERR_CNT7_COUNT_SHIFT (0U) /*! COUNT - Memory n Correctable Error Count */ #define M7_ERM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << M7_ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & M7_ERM_CORR_ERR_CNT7_COUNT_MASK) /*! @} */ /*! * @} */ /* end of group M7_ERM_Register_Masks */ /* M7_ERM - Peripheral instance base addresses */ /** Peripheral M7__ERM base address */ #define M7__ERM_BASE (0x4A070000u) /** Peripheral M7__ERM base pointer */ #define M7__ERM ((M7_ERM_Type *)M7__ERM_BASE) /** Array initializer of M7_ERM peripheral base addresses */ #define M7_ERM_BASE_ADDRS { M7__ERM_BASE } /** Array initializer of M7_ERM peripheral base pointers */ #define M7_ERM_BASE_PTRS { M7__ERM } /*! * @} */ /* end of group M7_ERM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- M7_LSTCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_LSTCU_Peripheral_Access_Layer M7_LSTCU Peripheral Access Layer * @{ */ /** M7_LSTCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x10 */ uint8_t RESERVED_2[76]; __I uint32_t MB_RSTAT0; /**< MBIST Run Status 0, offset: 0x60 */ uint8_t RESERVED_3[284]; __IO uint32_t MBFM0; /**< MBIST Fault Mapping 0, offset: 0x180 */ uint8_t RESERVED_4[220]; __IO uint32_t STAG; /**< Stagger, offset: 0x260 */ uint8_t RESERVED_5[12]; __IO uint32_t PH1_DUR; /**< Phase 1 Duration, offset: 0x270 */ uint8_t RESERVED_6[140]; __IO uint32_t MBPTR[1]; /**< MBIST Scheduler Pointer, array offset: 0x300, array step: 0x4 */ } M7_LSTCU_Type; /* ---------------------------------------------------------------------------- -- M7_LSTCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_LSTCU_Register_Masks M7_LSTCU Register Masks * @{ */ /*! @name ERR_STAT - Error Status */ /*! @{ */ #define M7_LSTCU_ERR_STAT_INVP_MB_MASK (0x2U) #define M7_LSTCU_ERR_STAT_INVP_MB_SHIFT (1U) /*! INVP_MB - Invalid Pointer MBIST * 0b0..No invalid pointer * 0b1..Invalid BIST pointer specified */ #define M7_LSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_ERR_STAT_INVP_MB_SHIFT)) & M7_LSTCU_ERR_STAT_INVP_MB_MASK) #define M7_LSTCU_ERR_STAT_UFSF_MASK (0x10000U) #define M7_LSTCU_ERR_STAT_UFSF_SHIFT (16U) /*! UFSF - Unrecoverable Fault Status * 0b0..No unrecoverable fault * 0b1..Unrecoverable fault */ #define M7_LSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_ERR_STAT_UFSF_SHIFT)) & M7_LSTCU_ERR_STAT_UFSF_MASK) #define M7_LSTCU_ERR_STAT_RFSF_MASK (0x20000U) #define M7_LSTCU_ERR_STAT_RFSF_SHIFT (17U) /*! RFSF - Recoverable Fault Status * 0b0..No recoverable fault * 0b1..Recoverable fault */ #define M7_LSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_ERR_STAT_RFSF_SHIFT)) & M7_LSTCU_ERR_STAT_RFSF_MASK) /*! @} */ /*! @name ERR_FM - Error Fault Mapping */ /*! @{ */ #define M7_LSTCU_ERR_FM_INVPFMMB_MASK (0x2U) #define M7_LSTCU_ERR_FM_INVPFMMB_SHIFT (1U) /*! INVPFMMB - Invalid BIST Pointer Fault Mapping During MBIST Scheduling * 0b0..Recoverable * 0b1..Unrecoverable */ #define M7_LSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_ERR_FM_INVPFMMB_SHIFT)) & M7_LSTCU_ERR_FM_INVPFMMB_MASK) /*! @} */ /*! @name MB_RSTAT0 - MBIST Run Status 0 */ /*! @{ */ #define M7_LSTCU_MB_RSTAT0_MBSTAT0_MASK (0x1U) #define M7_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT (0U) /*! MBSTAT0 - MBIST Run Result Status 0 * 0b0..Pass * 0b1..Fail */ #define M7_LSTCU_MB_RSTAT0_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT)) & M7_LSTCU_MB_RSTAT0_MBSTAT0_MASK) /*! @} */ /*! @name MBFM0 - MBIST Fault Mapping 0 */ /*! @{ */ #define M7_LSTCU_MBFM0_MBSTATFM0_MASK (0x1U) #define M7_LSTCU_MBFM0_MBSTATFM0_SHIFT (0U) /*! MBSTATFM0 - MBIST Fault Mapping n * 0b0..Recoverable * 0b1..Unrecoverable */ #define M7_LSTCU_MBFM0_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_MBFM0_MBSTATFM0_SHIFT)) & M7_LSTCU_MBFM0_MBSTATFM0_MASK) /*! @} */ /*! @name STAG - Stagger */ /*! @{ */ #define M7_LSTCU_STAG_MB_DELAY_MASK (0xFF00U) #define M7_LSTCU_STAG_MB_DELAY_SHIFT (8U) /*! MB_DELAY - MBIST Delay */ #define M7_LSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_STAG_MB_DELAY_SHIFT)) & M7_LSTCU_STAG_MB_DELAY_MASK) /*! @} */ /*! @name PH1_DUR - Phase 1 Duration */ /*! @{ */ #define M7_LSTCU_PH1_DUR_PH1DUR_MASK (0x3FFU) #define M7_LSTCU_PH1_DUR_PH1DUR_SHIFT (0U) /*! PH1DUR - Phase 1 Duration */ #define M7_LSTCU_PH1_DUR_PH1DUR(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_PH1_DUR_PH1DUR_SHIFT)) & M7_LSTCU_PH1_DUR_PH1DUR_MASK) /*! @} */ /*! @name MBPTR - MBIST Scheduler Pointer */ /*! @{ */ #define M7_LSTCU_MBPTR_MBPTR_MASK (0xFFU) #define M7_LSTCU_MBPTR_MBPTR_SHIFT (0U) /*! MBPTR - MBIST Pointer */ #define M7_LSTCU_MBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_MBPTR_MBPTR_SHIFT)) & M7_LSTCU_MBPTR_MBPTR_MASK) #define M7_LSTCU_MBPTR_MBCSM_MASK (0x100U) #define M7_LSTCU_MBPTR_MBCSM_SHIFT (8U) /*! MBCSM - MBIST Mode * 0b0..Sequential * 0b1..Concurrent */ #define M7_LSTCU_MBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_MBPTR_MBCSM_SHIFT)) & M7_LSTCU_MBPTR_MBCSM_MASK) #define M7_LSTCU_MBPTR_MBEOL_MASK (0x80000000U) #define M7_LSTCU_MBPTR_MBEOL_SHIFT (31U) /*! MBEOL - MBIST End of List * 0b0..Not end of list * 0b1..End of list */ #define M7_LSTCU_MBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << M7_LSTCU_MBPTR_MBEOL_SHIFT)) & M7_LSTCU_MBPTR_MBEOL_MASK) /*! @} */ /* The count of M7_LSTCU_MBPTR */ #define M7_LSTCU_MBPTR_COUNT (1U) /*! * @} */ /* end of group M7_LSTCU_Register_Masks */ /* M7_LSTCU - Peripheral instance base addresses */ /** Peripheral M7__LSTCU_M7MIX base address */ #define M7__LSTCU_M7MIX_BASE (0x4A050000u) /** Peripheral M7__LSTCU_M7MIX base pointer */ #define M7__LSTCU_M7MIX ((M7_LSTCU_Type *)M7__LSTCU_M7MIX_BASE) /** Array initializer of M7_LSTCU peripheral base addresses */ #define M7_LSTCU_BASE_ADDRS { M7__LSTCU_M7MIX_BASE } /** Array initializer of M7_LSTCU peripheral base pointers */ #define M7_LSTCU_BASE_PTRS { M7__LSTCU_M7MIX } /*! * @} */ /* end of group M7_LSTCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- M7_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_TCU_Peripheral_Access_Layer M7_TCU Peripheral Access Layer * @{ */ /** M7_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_3[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } M7_TCU_Type; /* ---------------------------------------------------------------------------- -- M7_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup M7_TCU_Register_Masks M7_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define M7_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define M7_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define M7_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & M7_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define M7_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define M7_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define M7_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & M7_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define M7_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define M7_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define M7_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & M7_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define M7_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define M7_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define M7_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & M7_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define M7_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define M7_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define M7_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & M7_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define M7_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define M7_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define M7_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & M7_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define M7_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define M7_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define M7_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & M7_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define M7_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define M7_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define M7_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & M7_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define M7_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define M7_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define M7_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & M7_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define M7_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x2U) #define M7_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define M7_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << M7_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & M7_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group M7_TCU_Register_Masks */ /* M7_TCU - Peripheral instance base addresses */ /** Peripheral M7__TCU base address */ #define M7__TCU_BASE (0x4A000000u) /** Peripheral M7__TCU base pointer */ #define M7__TCU ((M7_TCU_Type *)M7__TCU_BASE) /** Array initializer of M7_TCU peripheral base addresses */ #define M7_TCU_BASE_ADDRS { M7__TCU_BASE } /** Array initializer of M7_TCU peripheral base pointers */ #define M7_TCU_BASE_PTRS { M7__TCU } /*! * @} */ /* end of group M7_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MIPI_DSI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_Peripheral_Access_Layer MIPI_DSI Peripheral Access Layer * @{ */ /** MIPI_DSI - Register Layout Typedef */ typedef struct { __I uint32_t VERSION; /**< Core Version, offset: 0x0 */ __IO uint32_t PWR_UP; /**< Power up, offset: 0x4 */ __IO uint32_t CLKMGR_CFG; /**< Factor for internal dividers, offset: 0x8 */ __IO uint32_t DPI_VCID; /**< DPI Virtual Channel ID, offset: 0xC */ __IO uint32_t DPI_COLOR_CODING; /**< DPI color coding, offset: 0x10 */ __IO uint32_t DPI_CFG_POL; /**< DPI signals polarity, offset: 0x14 */ __IO uint32_t DPI_LP_CMD_TIM; /**< Low Power commands' timing, offset: 0x18 */ uint8_t RESERVED_0[16]; __IO uint32_t PCKHDL_CFG; /**< EoTp, BTA, CRC and ECC Configuration, offset: 0x2C */ __IO uint32_t GEN_VCID; /**< Read responses Virtual Channel ID, offset: 0x30 */ __IO uint32_t MODE_CFG; /**< Operation mode, offset: 0x34 */ __IO uint32_t VID_MODE_CFG; /**< Video mode configuration, offset: 0x38 */ __IO uint32_t VID_PKT_SIZE; /**< Video Packets size, offset: 0x3C */ __IO uint32_t VID_NUM_CHUNKS; /**< Number of Chunks, offset: 0x40 */ __IO uint32_t VID_NULL_SIZE; /**< Null Packets size, offset: 0x44 */ __IO uint32_t VID_HSA_TIME; /**< HSA time, offset: 0x48 */ __IO uint32_t VID_HBP_TIME; /**< HBP time, offset: 0x4C */ __IO uint32_t VID_HLINE_TIME; /**< Overall video line time, offset: 0x50 */ __IO uint32_t VID_VSA_LINES; /**< VSA period, offset: 0x54 */ __IO uint32_t VID_VBP_LINES; /**< VBP period, offset: 0x58 */ __IO uint32_t VID_VFP_LINES; /**< VFP period, offset: 0x5C */ __IO uint32_t VID_VACTIVE_LINES; /**< Video vertical resolution, offset: 0x60 */ __IO uint32_t EDPI_CMD_SIZE; /**< eDPI packets size, offset: 0x64 */ __IO uint32_t CMD_MODE_CFG; /**< Command Mode operation configuration, offset: 0x68 */ __IO uint32_t GEN_HDR; /**< Generic Interface Packet Header, offset: 0x6C */ __IO uint32_t GEN_PLD_DATA; /**< Generic Interface Packets Payload, offset: 0x70 */ __I uint32_t CMD_PKT_STATUS; /**< Generic Interface and DBI FIFO status, offset: 0x74 */ __IO uint32_t TO_CNT_CFG; /**< Timeout Trigger Configuration, offset: 0x78 */ __IO uint32_t HS_RD_TO_CNT; /**< Peripheral timeout after HS read operations, offset: 0x7C */ __IO uint32_t LP_RD_TO_CNT; /**< Peripheral timeout after LP read operations, offset: 0x80 */ __IO uint32_t HS_WR_TO_CNT; /**< Peripheral timeout after HS write operations, offset: 0x84 */ __IO uint32_t LP_WR_TO_CNT; /**< Peripheral timeout after LP write operations, offset: 0x88 */ __IO uint32_t BTA_TO_CNT; /**< Peripheral timeout after BTA completion, offset: 0x8C */ __IO uint32_t SDF_3D; /**< 3D information for VSS packets, offset: 0x90 */ __IO uint32_t LPCLK_CTRL; /**< Non-continuous Clock configuration, offset: 0x94 */ __IO uint32_t PHY_TMR_LPCLK_CFG; /**< Time configuration for (clock lane) transitions between HS and LP, offset: 0x98 */ __IO uint32_t PHY_TMR_CFG; /**< Time configuration for (data lanes) transitions between HS and LP, offset: 0x9C */ __IO uint32_t PHY_RSTZ; /**< D-PHY's PLL and Resets, offset: 0xA0 */ __IO uint32_t PHY_IF_CFG; /**< Active lanes and Stop State minimum time in Stop State, offset: 0xA4 */ __IO uint32_t PHY_ULPS_CTRL; /**< Transitions from and to ULPS, using D-PHY, offset: 0xA8 */ __IO uint32_t PHY_TX_TRIGGERS; /**< Pins related to D-PHY triggers, offset: 0xAC */ __I uint32_t PHY_STATUS; /**< D-PHY Status, offset: 0xB0 */ __IO uint32_t PHY_TST_CTRL0; /**< D-PHY control and clear pins, offset: 0xB4 */ __IO uint32_t PHY_TST_CTRL1; /**< D-PHY data and enable pins, offset: 0xB8 */ __I uint32_t INT_ST0; /**< Interrupts status 0, offset: 0xBC */ __I uint32_t INT_ST1; /**< Interrupts Status 1, offset: 0xC0 */ __IO uint32_t INT_MSK0; /**< INT_ST0 mask, offset: 0xC4 */ __IO uint32_t INT_MSK1; /**< INT_ST1 mask, offset: 0xC8 */ __IO uint32_t PHY_CAL; /**< D-PHY skew calibration, offset: 0xCC */ uint8_t RESERVED_1[8]; __IO uint32_t INT_FORCE0; /**< Force INT_ST0, offset: 0xD8 */ __IO uint32_t INT_FORCE1; /**< Force INT_ST1, offset: 0xDC */ __IO uint32_t AUTO_ULPS_MODE; /**< Automatic ULPS control, offset: 0xE0 */ __IO uint32_t AUTO_ULPS_ENTRY_DELAY; /**< ULPS transition delay, offset: 0xE4 */ __IO uint32_t AUTO_ULPS_WAKEUP_TIME; /**< D-PHY wakeup time, offset: 0xE8 */ uint8_t RESERVED_2[4]; __IO uint32_t DSC_PARAMETER; /**< Display Stream Compression, offset: 0xF0 */ __IO uint32_t PHY_TMR_RD_CFG; /**< PHY timings, offset: 0xF4 */ __IO uint32_t AUTO_ULPS_MIN_TIME; /**< PHY Timings - Transition between ulpsactivenot and ulpsexitreq, offset: 0xF8 */ uint8_t RESERVED_3[4]; __IO uint32_t VID_SHADOW_CTRL; /**< DPI Shadow Feature, offset: 0x100 */ uint8_t RESERVED_4[8]; __I uint32_t DPI_VCID_ACT; /**< Actual DPI Virtual Channel ID, offset: 0x10C */ __I uint32_t DPI_COLOR_CODING_ACT; /**< Actual DPI Color Coding, offset: 0x110 */ uint8_t RESERVED_5[4]; __I uint32_t DPI_LP_CMD_TIM_ACT; /**< Actual DPI Low Power Commands' Timing, offset: 0x118 */ __IO uint32_t EDPI_TE_HW_CFG; /**< TE for Hardware operations, offset: 0x11C */ uint8_t RESERVED_6[24]; __I uint32_t VID_MODE_CFG_ACT; /**< VID_MODE_CFG, offset: 0x138 */ __I uint32_t VID_PKT_SIZE_ACT; /**< Actual VID_PKT_SIZE, offset: 0x13C */ __I uint32_t VID_NUM_CHUNKS_ACT; /**< Actual VID_NUM_CHUNKS, offset: 0x140 */ __I uint32_t VID_NULL_SIZE_ACT; /**< Actual VID_NULL_SIZE, offset: 0x144 */ __I uint32_t VID_HSA_TIME_ACT; /**< Actual VID_HSA_TIME, offset: 0x148 */ __I uint32_t VID_HBP_TIME_ACT; /**< Actual VID_HBP_TIME, offset: 0x14C */ __I uint32_t VID_HLINE_TIME_ACT; /**< Actual VID_HLINE_TIME, offset: 0x150 */ __I uint32_t VID_VSA_LINES_ACT; /**< Actual VID_VSA_LINES, offset: 0x154 */ __I uint32_t VID_VBP_LINES_ACT; /**< VID_VBP_LINES, offset: 0x158 */ __I uint32_t VID_VFP_LINES_ACT; /**< Actual VID_VFP_LINES, offset: 0x15C */ __I uint32_t VID_VACTIVE_LINES_ACT; /**< Actual VID_VACTIVE_LINES, offset: 0x160 */ uint8_t RESERVED_7[4]; __I uint32_t VID_PKT_STATUS; /**< eDPI and DPI FIFOs status, offset: 0x168 */ uint8_t RESERVED_8[36]; __I uint32_t SDF_3D_ACT; /**< SDF_3D, offset: 0x190 */ } MIPI_DSI_Type; /* ---------------------------------------------------------------------------- -- MIPI_DSI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks * @{ */ /*! @name VERSION - Core Version */ /*! @{ */ #define MIPI_DSI_VERSION_version_MASK (0xFFFFFFFFU) #define MIPI_DSI_VERSION_version_SHIFT (0U) /*! version - This field indicates the version of the MIPI DSI host */ #define MIPI_DSI_VERSION_version(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VERSION_version_SHIFT)) & MIPI_DSI_VERSION_version_MASK) /*! @} */ /*! @name PWR_UP - Power up */ /*! @{ */ #define MIPI_DSI_PWR_UP_shutdownz_MASK (0x1U) #define MIPI_DSI_PWR_UP_shutdownz_SHIFT (0U) /*! shutdownz - This bit configures the controller either to power up or to reset * 0b1..Power up the controller * 0b0..Reset the controller */ #define MIPI_DSI_PWR_UP_shutdownz(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PWR_UP_shutdownz_SHIFT)) & MIPI_DSI_PWR_UP_shutdownz_MASK) #define MIPI_DSI_PWR_UP_reserved_31_1_MASK (0xFFFFFFFEU) #define MIPI_DSI_PWR_UP_reserved_31_1_SHIFT (1U) /*! reserved_31_1 - Reserved and read as zero */ #define MIPI_DSI_PWR_UP_reserved_31_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PWR_UP_reserved_31_1_SHIFT)) & MIPI_DSI_PWR_UP_reserved_31_1_MASK) /*! @} */ /*! @name CLKMGR_CFG - Factor for internal dividers */ /*! @{ */ #define MIPI_DSI_CLKMGR_CFG_tx_esc_clk_division_MASK (0xFFU) #define MIPI_DSI_CLKMGR_CFG_tx_esc_clk_division_SHIFT (0U) /*! tx_esc_clk_division - This field indicates the division factor for the TX Escape clock source (lanebyteclk) */ #define MIPI_DSI_CLKMGR_CFG_tx_esc_clk_division(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CLKMGR_CFG_tx_esc_clk_division_SHIFT)) & MIPI_DSI_CLKMGR_CFG_tx_esc_clk_division_MASK) #define MIPI_DSI_CLKMGR_CFG_to_clk_division_MASK (0xFF00U) #define MIPI_DSI_CLKMGR_CFG_to_clk_division_SHIFT (8U) /*! to_clk_division - Time out clock division */ #define MIPI_DSI_CLKMGR_CFG_to_clk_division(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CLKMGR_CFG_to_clk_division_SHIFT)) & MIPI_DSI_CLKMGR_CFG_to_clk_division_MASK) #define MIPI_DSI_CLKMGR_CFG_reserved_31_16_MASK (0xFFFF0000U) #define MIPI_DSI_CLKMGR_CFG_reserved_31_16_SHIFT (16U) /*! reserved_31_16 - Reserved and read as zero */ #define MIPI_DSI_CLKMGR_CFG_reserved_31_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CLKMGR_CFG_reserved_31_16_SHIFT)) & MIPI_DSI_CLKMGR_CFG_reserved_31_16_MASK) /*! @} */ /*! @name DPI_VCID - DPI Virtual Channel ID */ /*! @{ */ #define MIPI_DSI_DPI_VCID_dpi_vcid_MASK (0x3U) #define MIPI_DSI_DPI_VCID_dpi_vcid_SHIFT (0U) /*! dpi_vcid - This field configures the DPI virtual channel id that is indexed to the Video mode packets */ #define MIPI_DSI_DPI_VCID_dpi_vcid(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_VCID_dpi_vcid_SHIFT)) & MIPI_DSI_DPI_VCID_dpi_vcid_MASK) #define MIPI_DSI_DPI_VCID_reserved_31_2_MASK (0xFFFFFFFCU) #define MIPI_DSI_DPI_VCID_reserved_31_2_SHIFT (2U) /*! reserved_31_2 - Reserved and read as zero */ #define MIPI_DSI_DPI_VCID_reserved_31_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_VCID_reserved_31_2_SHIFT)) & MIPI_DSI_DPI_VCID_reserved_31_2_MASK) /*! @} */ /*! @name DPI_COLOR_CODING - DPI color coding */ /*! @{ */ #define MIPI_DSI_DPI_COLOR_CODING_dpi_color_coding_MASK (0xFU) #define MIPI_DSI_DPI_COLOR_CODING_dpi_color_coding_SHIFT (0U) /*! dpi_color_coding - This field configures the DPI color for Video Mode/eDPI Command Mode coding as follows: * 0b0000..16-bit configuration 1 * 0b0001..16-bit configuration 2 * 0b0010..16-bit configuration 3 * 0b0011..18-bit configuration 1 * 0b0100..18-bit configuration 2 * 0b0101..24-bit * 0b0110..20-bit YCbCr 4:2:2 loosely packed / Reserved for eDPI Command Mode * 0b0111..24-bit YCbCr 4:2:2 / Reserved for eDPI Command Mode * 0b1000..16-bit YCbCr 4:2:2 / Reserved for eDPI Command Mode * 0b1001..30-bit - DSC_ENC 10bit / Reserved for eDPI Command Mode * 0b1010..36-bit / Reserved for eDPI Command Mode * 0b1011..12-bit YCbCr 4:2:0 / Reserved for eDPI Command Mode * 0b1100..DSC24 compressed Data * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define MIPI_DSI_DPI_COLOR_CODING_dpi_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_dpi_color_coding_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_dpi_color_coding_MASK) #define MIPI_DSI_DPI_COLOR_CODING_reserved_7_4_MASK (0xF0U) #define MIPI_DSI_DPI_COLOR_CODING_reserved_7_4_SHIFT (4U) /*! reserved_7_4 - Reserved and read as zero */ #define MIPI_DSI_DPI_COLOR_CODING_reserved_7_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_reserved_7_4_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_reserved_7_4_MASK) #define MIPI_DSI_DPI_COLOR_CODING_loosely18_en_MASK (0x100U) #define MIPI_DSI_DPI_COLOR_CODING_loosely18_en_SHIFT (8U) /*! loosely18_en - When set to 1, this bit activates loosely packed variant to 18-bit configurations */ #define MIPI_DSI_DPI_COLOR_CODING_loosely18_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_loosely18_en_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_loosely18_en_MASK) #define MIPI_DSI_DPI_COLOR_CODING_reserved_31_9_MASK (0xFFFFFE00U) #define MIPI_DSI_DPI_COLOR_CODING_reserved_31_9_SHIFT (9U) /*! reserved_31_9 - Reserved and read as zero */ #define MIPI_DSI_DPI_COLOR_CODING_reserved_31_9(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_reserved_31_9_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_reserved_31_9_MASK) /*! @} */ /*! @name DPI_CFG_POL - DPI signals polarity */ /*! @{ */ #define MIPI_DSI_DPI_CFG_POL_dataen_active_low_MASK (0x1U) #define MIPI_DSI_DPI_CFG_POL_dataen_active_low_SHIFT (0U) /*! dataen_active_low - When set to 1, this bit configures the data enable pin (dpidataen) as active low */ #define MIPI_DSI_DPI_CFG_POL_dataen_active_low(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_CFG_POL_dataen_active_low_SHIFT)) & MIPI_DSI_DPI_CFG_POL_dataen_active_low_MASK) #define MIPI_DSI_DPI_CFG_POL_vsync_active_low_MASK (0x2U) #define MIPI_DSI_DPI_CFG_POL_vsync_active_low_SHIFT (1U) /*! vsync_active_low - When set to 1, this bit configures the vertical synchronism pin (dpivsync) as active low */ #define MIPI_DSI_DPI_CFG_POL_vsync_active_low(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_CFG_POL_vsync_active_low_SHIFT)) & MIPI_DSI_DPI_CFG_POL_vsync_active_low_MASK) #define MIPI_DSI_DPI_CFG_POL_hsync_active_low_MASK (0x4U) #define MIPI_DSI_DPI_CFG_POL_hsync_active_low_SHIFT (2U) /*! hsync_active_low - When set to 1, this bit configures the horizontal synchronism pin (dpihsync) as active low */ #define MIPI_DSI_DPI_CFG_POL_hsync_active_low(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_CFG_POL_hsync_active_low_SHIFT)) & MIPI_DSI_DPI_CFG_POL_hsync_active_low_MASK) #define MIPI_DSI_DPI_CFG_POL_shutd_active_low_MASK (0x8U) #define MIPI_DSI_DPI_CFG_POL_shutd_active_low_SHIFT (3U) /*! shutd_active_low - When set to 1, this bit configures the shutdown pin (dpishutdn) as active low */ #define MIPI_DSI_DPI_CFG_POL_shutd_active_low(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_CFG_POL_shutd_active_low_SHIFT)) & MIPI_DSI_DPI_CFG_POL_shutd_active_low_MASK) #define MIPI_DSI_DPI_CFG_POL_colorm_active_low_MASK (0x10U) #define MIPI_DSI_DPI_CFG_POL_colorm_active_low_SHIFT (4U) /*! colorm_active_low - When set to 1, this bit configures the color mode pin (dpicolorm) as active low */ #define MIPI_DSI_DPI_CFG_POL_colorm_active_low(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_CFG_POL_colorm_active_low_SHIFT)) & MIPI_DSI_DPI_CFG_POL_colorm_active_low_MASK) #define MIPI_DSI_DPI_CFG_POL_reserved_31_5_MASK (0xFFFFFFE0U) #define MIPI_DSI_DPI_CFG_POL_reserved_31_5_SHIFT (5U) /*! reserved_31_5 - Reserved and read as zero */ #define MIPI_DSI_DPI_CFG_POL_reserved_31_5(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_CFG_POL_reserved_31_5_SHIFT)) & MIPI_DSI_DPI_CFG_POL_reserved_31_5_MASK) /*! @} */ /*! @name DPI_LP_CMD_TIM - Low Power commands' timing */ /*! @{ */ #define MIPI_DSI_DPI_LP_CMD_TIM_invact_lpcmd_time_MASK (0xFFU) #define MIPI_DSI_DPI_LP_CMD_TIM_invact_lpcmd_time_SHIFT (0U) /*! invact_lpcmd_time - This field is used for the transmission of commands in low-power mode */ #define MIPI_DSI_DPI_LP_CMD_TIM_invact_lpcmd_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_invact_lpcmd_time_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_invact_lpcmd_time_MASK) #define MIPI_DSI_DPI_LP_CMD_TIM_reserved_15_8_MASK (0xFF00U) #define MIPI_DSI_DPI_LP_CMD_TIM_reserved_15_8_SHIFT (8U) /*! reserved_15_8 - Reserved and read as zero */ #define MIPI_DSI_DPI_LP_CMD_TIM_reserved_15_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_reserved_15_8_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_reserved_15_8_MASK) #define MIPI_DSI_DPI_LP_CMD_TIM_outvact_lpcmd_time_MASK (0xFF0000U) #define MIPI_DSI_DPI_LP_CMD_TIM_outvact_lpcmd_time_SHIFT (16U) /*! outvact_lpcmd_time - This field is used for the transmission of commands in low-power mode */ #define MIPI_DSI_DPI_LP_CMD_TIM_outvact_lpcmd_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_outvact_lpcmd_time_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_outvact_lpcmd_time_MASK) #define MIPI_DSI_DPI_LP_CMD_TIM_reserved_31_24_MASK (0xFF000000U) #define MIPI_DSI_DPI_LP_CMD_TIM_reserved_31_24_SHIFT (24U) /*! reserved_31_24 - Reserved and read as zero */ #define MIPI_DSI_DPI_LP_CMD_TIM_reserved_31_24(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_reserved_31_24_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_reserved_31_24_MASK) /*! @} */ /*! @name PCKHDL_CFG - EoTp, BTA, CRC and ECC Configuration */ /*! @{ */ #define MIPI_DSI_PCKHDL_CFG_eotp_tx_en_MASK (0x1U) #define MIPI_DSI_PCKHDL_CFG_eotp_tx_en_SHIFT (0U) /*! eotp_tx_en - When set to 1, this bit enables the EoTp transmission in high-speed */ #define MIPI_DSI_PCKHDL_CFG_eotp_tx_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PCKHDL_CFG_eotp_tx_en_SHIFT)) & MIPI_DSI_PCKHDL_CFG_eotp_tx_en_MASK) #define MIPI_DSI_PCKHDL_CFG_eotp_rx_en_MASK (0x2U) #define MIPI_DSI_PCKHDL_CFG_eotp_rx_en_SHIFT (1U) /*! eotp_rx_en - When set to 1, this bit enables the EoTp reception */ #define MIPI_DSI_PCKHDL_CFG_eotp_rx_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PCKHDL_CFG_eotp_rx_en_SHIFT)) & MIPI_DSI_PCKHDL_CFG_eotp_rx_en_MASK) #define MIPI_DSI_PCKHDL_CFG_bta_en_MASK (0x4U) #define MIPI_DSI_PCKHDL_CFG_bta_en_SHIFT (2U) /*! bta_en - When set to 1, this bit enables the Bus Turn-Around (BTA) request */ #define MIPI_DSI_PCKHDL_CFG_bta_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PCKHDL_CFG_bta_en_SHIFT)) & MIPI_DSI_PCKHDL_CFG_bta_en_MASK) #define MIPI_DSI_PCKHDL_CFG_ecc_rx_en_MASK (0x8U) #define MIPI_DSI_PCKHDL_CFG_ecc_rx_en_SHIFT (3U) /*! ecc_rx_en - When set to 1, this bit enables the ECC reception, error correction, and reporting */ #define MIPI_DSI_PCKHDL_CFG_ecc_rx_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PCKHDL_CFG_ecc_rx_en_SHIFT)) & MIPI_DSI_PCKHDL_CFG_ecc_rx_en_MASK) #define MIPI_DSI_PCKHDL_CFG_crc_rx_en_MASK (0x10U) #define MIPI_DSI_PCKHDL_CFG_crc_rx_en_SHIFT (4U) /*! crc_rx_en - When set to 1, this bit enables the CRC reception and error reporting */ #define MIPI_DSI_PCKHDL_CFG_crc_rx_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PCKHDL_CFG_crc_rx_en_SHIFT)) & MIPI_DSI_PCKHDL_CFG_crc_rx_en_MASK) #define MIPI_DSI_PCKHDL_CFG_eotp_tx_lp_en_MASK (0x20U) #define MIPI_DSI_PCKHDL_CFG_eotp_tx_lp_en_SHIFT (5U) /*! eotp_tx_lp_en - When set to 1, this bit enables the EoTp transmission in low-power */ #define MIPI_DSI_PCKHDL_CFG_eotp_tx_lp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PCKHDL_CFG_eotp_tx_lp_en_SHIFT)) & MIPI_DSI_PCKHDL_CFG_eotp_tx_lp_en_MASK) #define MIPI_DSI_PCKHDL_CFG_reserved_31_6_MASK (0xFFFFFFC0U) #define MIPI_DSI_PCKHDL_CFG_reserved_31_6_SHIFT (6U) /*! reserved_31_6 - Reserved and read as zero */ #define MIPI_DSI_PCKHDL_CFG_reserved_31_6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PCKHDL_CFG_reserved_31_6_SHIFT)) & MIPI_DSI_PCKHDL_CFG_reserved_31_6_MASK) /*! @} */ /*! @name GEN_VCID - Read responses Virtual Channel ID */ /*! @{ */ #define MIPI_DSI_GEN_VCID_gen_vcid_rx_MASK (0x3U) #define MIPI_DSI_GEN_VCID_gen_vcid_rx_SHIFT (0U) /*! gen_vcid_rx - This field indicates the Generic interface read-back virtual channel identification */ #define MIPI_DSI_GEN_VCID_gen_vcid_rx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_VCID_gen_vcid_rx_SHIFT)) & MIPI_DSI_GEN_VCID_gen_vcid_rx_MASK) #define MIPI_DSI_GEN_VCID_reserved_7_2_MASK (0xFCU) #define MIPI_DSI_GEN_VCID_reserved_7_2_SHIFT (2U) /*! reserved_7_2 - Reserved and read as zero */ #define MIPI_DSI_GEN_VCID_reserved_7_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_VCID_reserved_7_2_SHIFT)) & MIPI_DSI_GEN_VCID_reserved_7_2_MASK) #define MIPI_DSI_GEN_VCID_gen_vcid_tear_auto_MASK (0x300U) #define MIPI_DSI_GEN_VCID_gen_vcid_tear_auto_SHIFT (8U) /*! gen_vcid_tear_auto - This field indicates the virtual channel identification for tear effect by hardware */ #define MIPI_DSI_GEN_VCID_gen_vcid_tear_auto(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_VCID_gen_vcid_tear_auto_SHIFT)) & MIPI_DSI_GEN_VCID_gen_vcid_tear_auto_MASK) #define MIPI_DSI_GEN_VCID_reserved_15_10_MASK (0xFC00U) #define MIPI_DSI_GEN_VCID_reserved_15_10_SHIFT (10U) /*! reserved_15_10 - Reserved and read as zero */ #define MIPI_DSI_GEN_VCID_reserved_15_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_VCID_reserved_15_10_SHIFT)) & MIPI_DSI_GEN_VCID_reserved_15_10_MASK) #define MIPI_DSI_GEN_VCID_gen_vcid_tx_auto_MASK (0x30000U) #define MIPI_DSI_GEN_VCID_gen_vcid_tx_auto_SHIFT (16U) /*! gen_vcid_tx_auto - This field indicates the Generic interface virtual channel identification * where generic packet is automatically generated & transmitted */ #define MIPI_DSI_GEN_VCID_gen_vcid_tx_auto(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_VCID_gen_vcid_tx_auto_SHIFT)) & MIPI_DSI_GEN_VCID_gen_vcid_tx_auto_MASK) #define MIPI_DSI_GEN_VCID_reserved_31_18_MASK (0xFFFC0000U) #define MIPI_DSI_GEN_VCID_reserved_31_18_SHIFT (18U) /*! reserved_31_18 - Reserved and read as zero */ #define MIPI_DSI_GEN_VCID_reserved_31_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_VCID_reserved_31_18_SHIFT)) & MIPI_DSI_GEN_VCID_reserved_31_18_MASK) /*! @} */ /*! @name MODE_CFG - Operation mode */ /*! @{ */ #define MIPI_DSI_MODE_CFG_cmd_video_mode_MASK (0x1U) #define MIPI_DSI_MODE_CFG_cmd_video_mode_SHIFT (0U) /*! cmd_video_mode - This bit configures the operation mode: * 0b1..command mode * 0b0..video mode */ #define MIPI_DSI_MODE_CFG_cmd_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_MODE_CFG_cmd_video_mode_SHIFT)) & MIPI_DSI_MODE_CFG_cmd_video_mode_MASK) #define MIPI_DSI_MODE_CFG_reserved_31_1_MASK (0xFFFFFFFEU) #define MIPI_DSI_MODE_CFG_reserved_31_1_SHIFT (1U) /*! reserved_31_1 - Reserved and read as zero */ #define MIPI_DSI_MODE_CFG_reserved_31_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_MODE_CFG_reserved_31_1_SHIFT)) & MIPI_DSI_MODE_CFG_reserved_31_1_MASK) /*! @} */ /*! @name VID_MODE_CFG - Video mode configuration */ /*! @{ */ #define MIPI_DSI_VID_MODE_CFG_vid_mode_type_MASK (0x3U) #define MIPI_DSI_VID_MODE_CFG_vid_mode_type_SHIFT (0U) /*! vid_mode_type - This field indicates the video mode transmission type as follows: * 0b00..Non-burst with sync pulses * 0b01..Non-burst with sync events * 0b10..Burst mode * 0b11..Burst mode */ #define MIPI_DSI_VID_MODE_CFG_vid_mode_type(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_vid_mode_type_SHIFT)) & MIPI_DSI_VID_MODE_CFG_vid_mode_type_MASK) #define MIPI_DSI_VID_MODE_CFG_reserved_7_2_MASK (0xFCU) #define MIPI_DSI_VID_MODE_CFG_reserved_7_2_SHIFT (2U) /*! reserved_7_2 - Reserved and read as zero */ #define MIPI_DSI_VID_MODE_CFG_reserved_7_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_reserved_7_2_SHIFT)) & MIPI_DSI_VID_MODE_CFG_reserved_7_2_MASK) #define MIPI_DSI_VID_MODE_CFG_lp_vsa_en_MASK (0x100U) #define MIPI_DSI_VID_MODE_CFG_lp_vsa_en_SHIFT (8U) /*! lp_vsa_en - When set to 1, this bit enables the return to low-power inside the VSA period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_lp_vsa_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_lp_vsa_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_lp_vsa_en_MASK) #define MIPI_DSI_VID_MODE_CFG_lp_vbp_en_MASK (0x200U) #define MIPI_DSI_VID_MODE_CFG_lp_vbp_en_SHIFT (9U) /*! lp_vbp_en - When set to 1, this bit enables the return to low-power inside the VBP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_lp_vbp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_lp_vbp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_lp_vbp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_lp_vfp_en_MASK (0x400U) #define MIPI_DSI_VID_MODE_CFG_lp_vfp_en_SHIFT (10U) /*! lp_vfp_en - When set to 1, this bit enables the return to low-power inside the VFP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_lp_vfp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_lp_vfp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_lp_vfp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_lp_vact_en_MASK (0x800U) #define MIPI_DSI_VID_MODE_CFG_lp_vact_en_SHIFT (11U) /*! lp_vact_en - When set to 1, this bit enables the return to low-power inside the VACT period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_lp_vact_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_lp_vact_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_lp_vact_en_MASK) #define MIPI_DSI_VID_MODE_CFG_lp_hbp_en_MASK (0x1000U) #define MIPI_DSI_VID_MODE_CFG_lp_hbp_en_SHIFT (12U) /*! lp_hbp_en - When set to 1, this bit enables the return to low-power inside the HBP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_lp_hbp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_lp_hbp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_lp_hbp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_lp_hfp_en_MASK (0x2000U) #define MIPI_DSI_VID_MODE_CFG_lp_hfp_en_SHIFT (13U) /*! lp_hfp_en - When set to 1, this bit enables the return to low-power inside the HFP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_lp_hfp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_lp_hfp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_lp_hfp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_frame_bta_ack_en_MASK (0x4000U) #define MIPI_DSI_VID_MODE_CFG_frame_bta_ack_en_SHIFT (14U) /*! frame_bta_ack_en - When set to 1, this bit enables the request for an acknowledge response at the end of a frame */ #define MIPI_DSI_VID_MODE_CFG_frame_bta_ack_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_frame_bta_ack_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_frame_bta_ack_en_MASK) #define MIPI_DSI_VID_MODE_CFG_lp_cmd_en_MASK (0x8000U) #define MIPI_DSI_VID_MODE_CFG_lp_cmd_en_SHIFT (15U) /*! lp_cmd_en - When set to 1, this bit enables the command transmission only in low-power mode */ #define MIPI_DSI_VID_MODE_CFG_lp_cmd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_lp_cmd_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_lp_cmd_en_MASK) #define MIPI_DSI_VID_MODE_CFG_vpg_en_MASK (0x10000U) #define MIPI_DSI_VID_MODE_CFG_vpg_en_SHIFT (16U) /*! vpg_en - When set to 1, this bit enables the video mode pattern generator */ #define MIPI_DSI_VID_MODE_CFG_vpg_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_vpg_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_vpg_en_MASK) #define MIPI_DSI_VID_MODE_CFG_reserved_19_17_MASK (0xE0000U) #define MIPI_DSI_VID_MODE_CFG_reserved_19_17_SHIFT (17U) /*! reserved_19_17 - Reserved and read as zero */ #define MIPI_DSI_VID_MODE_CFG_reserved_19_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_reserved_19_17_SHIFT)) & MIPI_DSI_VID_MODE_CFG_reserved_19_17_MASK) #define MIPI_DSI_VID_MODE_CFG_vpg_mode_MASK (0x100000U) #define MIPI_DSI_VID_MODE_CFG_vpg_mode_SHIFT (20U) /*! vpg_mode - This field is to select the pattern: * 0b1..vertical only * 0b0..horizontal or vertical */ #define MIPI_DSI_VID_MODE_CFG_vpg_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_vpg_mode_SHIFT)) & MIPI_DSI_VID_MODE_CFG_vpg_mode_MASK) #define MIPI_DSI_VID_MODE_CFG_reserved_23_21_MASK (0xE00000U) #define MIPI_DSI_VID_MODE_CFG_reserved_23_21_SHIFT (21U) /*! reserved_23_21 - Reserved and read as zero */ #define MIPI_DSI_VID_MODE_CFG_reserved_23_21(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_reserved_23_21_SHIFT)) & MIPI_DSI_VID_MODE_CFG_reserved_23_21_MASK) #define MIPI_DSI_VID_MODE_CFG_vpg_orientation_MASK (0x1000000U) #define MIPI_DSI_VID_MODE_CFG_vpg_orientation_SHIFT (24U) /*! vpg_orientation - This field indicates the color bar orientation as follows: * 0b0..Vertical mode * 0b1..Horizontal mode */ #define MIPI_DSI_VID_MODE_CFG_vpg_orientation(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_vpg_orientation_SHIFT)) & MIPI_DSI_VID_MODE_CFG_vpg_orientation_MASK) #define MIPI_DSI_VID_MODE_CFG_reserved_31_25_MASK (0xFE000000U) #define MIPI_DSI_VID_MODE_CFG_reserved_31_25_SHIFT (25U) /*! reserved_31_25 - Reserved and read as zero */ #define MIPI_DSI_VID_MODE_CFG_reserved_31_25(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_reserved_31_25_SHIFT)) & MIPI_DSI_VID_MODE_CFG_reserved_31_25_MASK) /*! @} */ /*! @name VID_PKT_SIZE - Video Packets size */ /*! @{ */ #define MIPI_DSI_VID_PKT_SIZE_vid_pkt_size_MASK (0x3FFFU) #define MIPI_DSI_VID_PKT_SIZE_vid_pkt_size_SHIFT (0U) /*! vid_pkt_size - This field configures the number of pixels in a single video packet */ #define MIPI_DSI_VID_PKT_SIZE_vid_pkt_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_SIZE_vid_pkt_size_SHIFT)) & MIPI_DSI_VID_PKT_SIZE_vid_pkt_size_MASK) #define MIPI_DSI_VID_PKT_SIZE_reserved_31_14_MASK (0xFFFFC000U) #define MIPI_DSI_VID_PKT_SIZE_reserved_31_14_SHIFT (14U) /*! reserved_31_14 - Reserved and read as zero */ #define MIPI_DSI_VID_PKT_SIZE_reserved_31_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_SIZE_reserved_31_14_SHIFT)) & MIPI_DSI_VID_PKT_SIZE_reserved_31_14_MASK) /*! @} */ /*! @name VID_NUM_CHUNKS - Number of Chunks */ /*! @{ */ #define MIPI_DSI_VID_NUM_CHUNKS_vid_num_chunks_MASK (0x1FFFU) #define MIPI_DSI_VID_NUM_CHUNKS_vid_num_chunks_SHIFT (0U) /*! vid_num_chunks - This register configures the number of chunks to be transmitted during a Line * period (a chunk is pair made of a video packet and a null packet) */ #define MIPI_DSI_VID_NUM_CHUNKS_vid_num_chunks(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NUM_CHUNKS_vid_num_chunks_SHIFT)) & MIPI_DSI_VID_NUM_CHUNKS_vid_num_chunks_MASK) #define MIPI_DSI_VID_NUM_CHUNKS_reserved_31_13_MASK (0xFFFFE000U) #define MIPI_DSI_VID_NUM_CHUNKS_reserved_31_13_SHIFT (13U) /*! reserved_31_13 - Reserved and read as zero */ #define MIPI_DSI_VID_NUM_CHUNKS_reserved_31_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NUM_CHUNKS_reserved_31_13_SHIFT)) & MIPI_DSI_VID_NUM_CHUNKS_reserved_31_13_MASK) /*! @} */ /*! @name VID_NULL_SIZE - Null Packets size */ /*! @{ */ #define MIPI_DSI_VID_NULL_SIZE_vid_null_size_MASK (0x1FFFU) #define MIPI_DSI_VID_NULL_SIZE_vid_null_size_SHIFT (0U) /*! vid_null_size - This register configures the number of bytes inside a null packet */ #define MIPI_DSI_VID_NULL_SIZE_vid_null_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NULL_SIZE_vid_null_size_SHIFT)) & MIPI_DSI_VID_NULL_SIZE_vid_null_size_MASK) #define MIPI_DSI_VID_NULL_SIZE_reserved_31_13_MASK (0xFFFFE000U) #define MIPI_DSI_VID_NULL_SIZE_reserved_31_13_SHIFT (13U) /*! reserved_31_13 - Reserved and read as zero */ #define MIPI_DSI_VID_NULL_SIZE_reserved_31_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NULL_SIZE_reserved_31_13_SHIFT)) & MIPI_DSI_VID_NULL_SIZE_reserved_31_13_MASK) /*! @} */ /*! @name VID_HSA_TIME - HSA time */ /*! @{ */ #define MIPI_DSI_VID_HSA_TIME_vid_hsa_time_MASK (0xFFFU) #define MIPI_DSI_VID_HSA_TIME_vid_hsa_time_SHIFT (0U) /*! vid_hsa_time - This field configures the Horizontal Synchronism Active period in lane byte clock cycles */ #define MIPI_DSI_VID_HSA_TIME_vid_hsa_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HSA_TIME_vid_hsa_time_SHIFT)) & MIPI_DSI_VID_HSA_TIME_vid_hsa_time_MASK) #define MIPI_DSI_VID_HSA_TIME_reserved_31_12_MASK (0xFFFFF000U) #define MIPI_DSI_VID_HSA_TIME_reserved_31_12_SHIFT (12U) /*! reserved_31_12 - Reserved and read as zero */ #define MIPI_DSI_VID_HSA_TIME_reserved_31_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HSA_TIME_reserved_31_12_SHIFT)) & MIPI_DSI_VID_HSA_TIME_reserved_31_12_MASK) /*! @} */ /*! @name VID_HBP_TIME - HBP time */ /*! @{ */ #define MIPI_DSI_VID_HBP_TIME_vid_hbp_time_MASK (0xFFFU) #define MIPI_DSI_VID_HBP_TIME_vid_hbp_time_SHIFT (0U) /*! vid_hbp_time - This field configures the Horizontal Back Porch period in lane byte clock cycles */ #define MIPI_DSI_VID_HBP_TIME_vid_hbp_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HBP_TIME_vid_hbp_time_SHIFT)) & MIPI_DSI_VID_HBP_TIME_vid_hbp_time_MASK) #define MIPI_DSI_VID_HBP_TIME_reserved_31_12_MASK (0xFFFFF000U) #define MIPI_DSI_VID_HBP_TIME_reserved_31_12_SHIFT (12U) /*! reserved_31_12 - Reserved and read as zero */ #define MIPI_DSI_VID_HBP_TIME_reserved_31_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HBP_TIME_reserved_31_12_SHIFT)) & MIPI_DSI_VID_HBP_TIME_reserved_31_12_MASK) /*! @} */ /*! @name VID_HLINE_TIME - Overall video line time */ /*! @{ */ #define MIPI_DSI_VID_HLINE_TIME_vid_hline_time_MASK (0x7FFFU) #define MIPI_DSI_VID_HLINE_TIME_vid_hline_time_SHIFT (0U) /*! vid_hline_time - This field configures the size of the total line time (HSA+HBP+HACT+HFP) counted in lane byte clock cycles */ #define MIPI_DSI_VID_HLINE_TIME_vid_hline_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HLINE_TIME_vid_hline_time_SHIFT)) & MIPI_DSI_VID_HLINE_TIME_vid_hline_time_MASK) #define MIPI_DSI_VID_HLINE_TIME_reserved_31_15_MASK (0xFFFF8000U) #define MIPI_DSI_VID_HLINE_TIME_reserved_31_15_SHIFT (15U) /*! reserved_31_15 - Reserved and read as zero */ #define MIPI_DSI_VID_HLINE_TIME_reserved_31_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HLINE_TIME_reserved_31_15_SHIFT)) & MIPI_DSI_VID_HLINE_TIME_reserved_31_15_MASK) /*! @} */ /*! @name VID_VSA_LINES - VSA period */ /*! @{ */ #define MIPI_DSI_VID_VSA_LINES_vsa_lines_MASK (0x3FFU) #define MIPI_DSI_VID_VSA_LINES_vsa_lines_SHIFT (0U) /*! vsa_lines - This field configures the Vertical Synchronism Active period measured in number of horizontal lines */ #define MIPI_DSI_VID_VSA_LINES_vsa_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VSA_LINES_vsa_lines_SHIFT)) & MIPI_DSI_VID_VSA_LINES_vsa_lines_MASK) #define MIPI_DSI_VID_VSA_LINES_reserved_31_10_MASK (0xFFFFFC00U) #define MIPI_DSI_VID_VSA_LINES_reserved_31_10_SHIFT (10U) /*! reserved_31_10 - Reserved and read as zero */ #define MIPI_DSI_VID_VSA_LINES_reserved_31_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VSA_LINES_reserved_31_10_SHIFT)) & MIPI_DSI_VID_VSA_LINES_reserved_31_10_MASK) /*! @} */ /*! @name VID_VBP_LINES - VBP period */ /*! @{ */ #define MIPI_DSI_VID_VBP_LINES_vbp_lines_MASK (0x3FFU) #define MIPI_DSI_VID_VBP_LINES_vbp_lines_SHIFT (0U) /*! vbp_lines - This field configures the Vertical Back Porch period measured in number of horizontal lines */ #define MIPI_DSI_VID_VBP_LINES_vbp_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VBP_LINES_vbp_lines_SHIFT)) & MIPI_DSI_VID_VBP_LINES_vbp_lines_MASK) #define MIPI_DSI_VID_VBP_LINES_reserved_31_10_MASK (0xFFFFFC00U) #define MIPI_DSI_VID_VBP_LINES_reserved_31_10_SHIFT (10U) /*! reserved_31_10 - Reserved and read as zero */ #define MIPI_DSI_VID_VBP_LINES_reserved_31_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VBP_LINES_reserved_31_10_SHIFT)) & MIPI_DSI_VID_VBP_LINES_reserved_31_10_MASK) /*! @} */ /*! @name VID_VFP_LINES - VFP period */ /*! @{ */ #define MIPI_DSI_VID_VFP_LINES_vfp_lines_MASK (0x3FFU) #define MIPI_DSI_VID_VFP_LINES_vfp_lines_SHIFT (0U) /*! vfp_lines - This field configures the Vertical Front Porch period measured in number of horizontal lines */ #define MIPI_DSI_VID_VFP_LINES_vfp_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VFP_LINES_vfp_lines_SHIFT)) & MIPI_DSI_VID_VFP_LINES_vfp_lines_MASK) #define MIPI_DSI_VID_VFP_LINES_reserved_31_10_MASK (0xFFFFFC00U) #define MIPI_DSI_VID_VFP_LINES_reserved_31_10_SHIFT (10U) /*! reserved_31_10 - Reserved and read as zero */ #define MIPI_DSI_VID_VFP_LINES_reserved_31_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VFP_LINES_reserved_31_10_SHIFT)) & MIPI_DSI_VID_VFP_LINES_reserved_31_10_MASK) /*! @} */ /*! @name VID_VACTIVE_LINES - Video vertical resolution */ /*! @{ */ #define MIPI_DSI_VID_VACTIVE_LINES_v_active_lines_MASK (0x3FFFU) #define MIPI_DSI_VID_VACTIVE_LINES_v_active_lines_SHIFT (0U) /*! v_active_lines - This field configures the Vertical Active period measured in number of horizontal lines */ #define MIPI_DSI_VID_VACTIVE_LINES_v_active_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VACTIVE_LINES_v_active_lines_SHIFT)) & MIPI_DSI_VID_VACTIVE_LINES_v_active_lines_MASK) #define MIPI_DSI_VID_VACTIVE_LINES_reserved_31_14_MASK (0xFFFFC000U) #define MIPI_DSI_VID_VACTIVE_LINES_reserved_31_14_SHIFT (14U) /*! reserved_31_14 - Reserved and read as zero */ #define MIPI_DSI_VID_VACTIVE_LINES_reserved_31_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VACTIVE_LINES_reserved_31_14_SHIFT)) & MIPI_DSI_VID_VACTIVE_LINES_reserved_31_14_MASK) /*! @} */ /*! @name EDPI_CMD_SIZE - eDPI packets size */ /*! @{ */ #define MIPI_DSI_EDPI_CMD_SIZE_edpi_allowed_cmd_size_MASK (0xFFFFU) #define MIPI_DSI_EDPI_CMD_SIZE_edpi_allowed_cmd_size_SHIFT (0U) /*! edpi_allowed_cmd_size - This field configures the maximum allowed size for an eDPI write memory command, measured in pixels */ #define MIPI_DSI_EDPI_CMD_SIZE_edpi_allowed_cmd_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_CMD_SIZE_edpi_allowed_cmd_size_SHIFT)) & MIPI_DSI_EDPI_CMD_SIZE_edpi_allowed_cmd_size_MASK) #define MIPI_DSI_EDPI_CMD_SIZE_reserved_31_16_MASK (0xFFFF0000U) #define MIPI_DSI_EDPI_CMD_SIZE_reserved_31_16_SHIFT (16U) /*! reserved_31_16 - Reserved and read as zero */ #define MIPI_DSI_EDPI_CMD_SIZE_reserved_31_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_CMD_SIZE_reserved_31_16_SHIFT)) & MIPI_DSI_EDPI_CMD_SIZE_reserved_31_16_MASK) /*! @} */ /*! @name CMD_MODE_CFG - Command Mode operation configuration */ /*! @{ */ #define MIPI_DSI_CMD_MODE_CFG_tear_fx_en_MASK (0x1U) #define MIPI_DSI_CMD_MODE_CFG_tear_fx_en_SHIFT (0U) /*! tear_fx_en - When set to 1, this bit enables the tearing effect acknowledge request */ #define MIPI_DSI_CMD_MODE_CFG_tear_fx_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_tear_fx_en_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_tear_fx_en_MASK) #define MIPI_DSI_CMD_MODE_CFG_ack_rqst_en_MASK (0x2U) #define MIPI_DSI_CMD_MODE_CFG_ack_rqst_en_SHIFT (1U) /*! ack_rqst_en - When set to 1, this bit enables the acknowledge request after each packet transmission */ #define MIPI_DSI_CMD_MODE_CFG_ack_rqst_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_ack_rqst_en_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_ack_rqst_en_MASK) #define MIPI_DSI_CMD_MODE_CFG_reserved_7_2_MASK (0xFCU) #define MIPI_DSI_CMD_MODE_CFG_reserved_7_2_SHIFT (2U) /*! reserved_7_2 - Reserved and read as zero */ #define MIPI_DSI_CMD_MODE_CFG_reserved_7_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_reserved_7_2_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_reserved_7_2_MASK) #define MIPI_DSI_CMD_MODE_CFG_gen_sw_0p_tx_MASK (0x100U) #define MIPI_DSI_CMD_MODE_CFG_gen_sw_0p_tx_SHIFT (8U) /*! gen_sw_0p_tx - This bit configures the Generic short write packet with zero parameter command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_gen_sw_0p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_gen_sw_0p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_gen_sw_0p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_gen_sw_1p_tx_MASK (0x200U) #define MIPI_DSI_CMD_MODE_CFG_gen_sw_1p_tx_SHIFT (9U) /*! gen_sw_1p_tx - This bit configures the Generic short write packet with one parameter command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_gen_sw_1p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_gen_sw_1p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_gen_sw_1p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_gen_sw_2p_tx_MASK (0x400U) #define MIPI_DSI_CMD_MODE_CFG_gen_sw_2p_tx_SHIFT (10U) /*! gen_sw_2p_tx - This bit configures the Generic short write packet with two parameters command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_gen_sw_2p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_gen_sw_2p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_gen_sw_2p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_gen_sr_0p_tx_MASK (0x800U) #define MIPI_DSI_CMD_MODE_CFG_gen_sr_0p_tx_SHIFT (11U) /*! gen_sr_0p_tx - This bit configures the Generic short read packet with zero parameter command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_gen_sr_0p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_gen_sr_0p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_gen_sr_0p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_gen_sr_1p_tx_MASK (0x1000U) #define MIPI_DSI_CMD_MODE_CFG_gen_sr_1p_tx_SHIFT (12U) /*! gen_sr_1p_tx - This bit configures the Generic short read packet with one parameter command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_gen_sr_1p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_gen_sr_1p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_gen_sr_1p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_gen_sr_2p_tx_MASK (0x2000U) #define MIPI_DSI_CMD_MODE_CFG_gen_sr_2p_tx_SHIFT (13U) /*! gen_sr_2p_tx - This bit configures the Generic short read packet with two parameters command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_gen_sr_2p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_gen_sr_2p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_gen_sr_2p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_gen_lw_tx_MASK (0x4000U) #define MIPI_DSI_CMD_MODE_CFG_gen_lw_tx_SHIFT (14U) /*! gen_lw_tx - This bit configures the Generic long write packet command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_gen_lw_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_gen_lw_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_gen_lw_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_reserved_15_MASK (0x8000U) #define MIPI_DSI_CMD_MODE_CFG_reserved_15_SHIFT (15U) /*! reserved_15 - Reserved and read as zero */ #define MIPI_DSI_CMD_MODE_CFG_reserved_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_reserved_15_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_reserved_15_MASK) #define MIPI_DSI_CMD_MODE_CFG_dcs_sw_0p_tx_MASK (0x10000U) #define MIPI_DSI_CMD_MODE_CFG_dcs_sw_0p_tx_SHIFT (16U) /*! dcs_sw_0p_tx - This bit configures the DCS short write packet with zero parameter command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_dcs_sw_0p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_dcs_sw_0p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_dcs_sw_0p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_dcs_sw_1p_tx_MASK (0x20000U) #define MIPI_DSI_CMD_MODE_CFG_dcs_sw_1p_tx_SHIFT (17U) /*! dcs_sw_1p_tx - This bit configures the DCS short write packet with one parameter command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_dcs_sw_1p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_dcs_sw_1p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_dcs_sw_1p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_dcs_sr_0p_tx_MASK (0x40000U) #define MIPI_DSI_CMD_MODE_CFG_dcs_sr_0p_tx_SHIFT (18U) /*! dcs_sr_0p_tx - This bit configures the DCS short read packet with zero parameter command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_dcs_sr_0p_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_dcs_sr_0p_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_dcs_sr_0p_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_dcs_lw_tx_MASK (0x80000U) #define MIPI_DSI_CMD_MODE_CFG_dcs_lw_tx_SHIFT (19U) /*! dcs_lw_tx - This bit configures the DCS long write packet command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_dcs_lw_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_dcs_lw_tx_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_dcs_lw_tx_MASK) #define MIPI_DSI_CMD_MODE_CFG_reserved_23_20_MASK (0xF00000U) #define MIPI_DSI_CMD_MODE_CFG_reserved_23_20_SHIFT (20U) /*! reserved_23_20 - Reserved and read as zero */ #define MIPI_DSI_CMD_MODE_CFG_reserved_23_20(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_reserved_23_20_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_reserved_23_20_MASK) #define MIPI_DSI_CMD_MODE_CFG_max_rd_pkt_size_MASK (0x1000000U) #define MIPI_DSI_CMD_MODE_CFG_max_rd_pkt_size_SHIFT (24U) /*! max_rd_pkt_size - This bit configures the maximum read packet size command transmission type: * 0b0..Transition type is high-speed * 0b1..Transition type is low-power */ #define MIPI_DSI_CMD_MODE_CFG_max_rd_pkt_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_max_rd_pkt_size_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_max_rd_pkt_size_MASK) #define MIPI_DSI_CMD_MODE_CFG_reserved_31_25_MASK (0xFE000000U) #define MIPI_DSI_CMD_MODE_CFG_reserved_31_25_SHIFT (25U) /*! reserved_31_25 - Reserved and read as zero */ #define MIPI_DSI_CMD_MODE_CFG_reserved_31_25(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_MODE_CFG_reserved_31_25_SHIFT)) & MIPI_DSI_CMD_MODE_CFG_reserved_31_25_MASK) /*! @} */ /*! @name GEN_HDR - Generic Interface Packet Header */ /*! @{ */ #define MIPI_DSI_GEN_HDR_gen_dt_MASK (0x3FU) #define MIPI_DSI_GEN_HDR_gen_dt_SHIFT (0U) /*! gen_dt - This field configures the packet Data Type of the header packet */ #define MIPI_DSI_GEN_HDR_gen_dt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_HDR_gen_dt_SHIFT)) & MIPI_DSI_GEN_HDR_gen_dt_MASK) #define MIPI_DSI_GEN_HDR_gen_vc_MASK (0xC0U) #define MIPI_DSI_GEN_HDR_gen_vc_SHIFT (6U) /*! gen_vc - This field configures the Virtual Channel ID of the header packet */ #define MIPI_DSI_GEN_HDR_gen_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_HDR_gen_vc_SHIFT)) & MIPI_DSI_GEN_HDR_gen_vc_MASK) #define MIPI_DSI_GEN_HDR_gen_wc_lsbyte_MASK (0xFF00U) #define MIPI_DSI_GEN_HDR_gen_wc_lsbyte_SHIFT (8U) /*! gen_wc_lsbyte - This field configures the least significant byte of the header packet's Word * count for long packets or data 0 for short packets */ #define MIPI_DSI_GEN_HDR_gen_wc_lsbyte(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_HDR_gen_wc_lsbyte_SHIFT)) & MIPI_DSI_GEN_HDR_gen_wc_lsbyte_MASK) #define MIPI_DSI_GEN_HDR_gen_wc_msbyte_MASK (0xFF0000U) #define MIPI_DSI_GEN_HDR_gen_wc_msbyte_SHIFT (16U) /*! gen_wc_msbyte - This field configures the most significant byte of the header packet's word * count for long packets or data 1 for short packets */ #define MIPI_DSI_GEN_HDR_gen_wc_msbyte(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_HDR_gen_wc_msbyte_SHIFT)) & MIPI_DSI_GEN_HDR_gen_wc_msbyte_MASK) #define MIPI_DSI_GEN_HDR_reserved_31_24_MASK (0xFF000000U) #define MIPI_DSI_GEN_HDR_reserved_31_24_SHIFT (24U) /*! reserved_31_24 - Reserved and read as zero */ #define MIPI_DSI_GEN_HDR_reserved_31_24(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_HDR_reserved_31_24_SHIFT)) & MIPI_DSI_GEN_HDR_reserved_31_24_MASK) /*! @} */ /*! @name GEN_PLD_DATA - Generic Interface Packets Payload */ /*! @{ */ #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b1_MASK (0xFFU) #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b1_SHIFT (0U) /*! gen_pld_b1 - This field indicates byte 1 of the packet payload */ #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_PLD_DATA_gen_pld_b1_SHIFT)) & MIPI_DSI_GEN_PLD_DATA_gen_pld_b1_MASK) #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b2_MASK (0xFF00U) #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b2_SHIFT (8U) /*! gen_pld_b2 - This field indicates byte 2 of the packet payload */ #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_PLD_DATA_gen_pld_b2_SHIFT)) & MIPI_DSI_GEN_PLD_DATA_gen_pld_b2_MASK) #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b3_MASK (0xFF0000U) #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b3_SHIFT (16U) /*! gen_pld_b3 - This field indicates byte 3 of the packet payload */ #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_PLD_DATA_gen_pld_b3_SHIFT)) & MIPI_DSI_GEN_PLD_DATA_gen_pld_b3_MASK) #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b4_MASK (0xFF000000U) #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b4_SHIFT (24U) /*! gen_pld_b4 - This field indicates byte 4 of the packet payload */ #define MIPI_DSI_GEN_PLD_DATA_gen_pld_b4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_GEN_PLD_DATA_gen_pld_b4_SHIFT)) & MIPI_DSI_GEN_PLD_DATA_gen_pld_b4_MASK) /*! @} */ /*! @name CMD_PKT_STATUS - Generic Interface and DBI FIFO status */ /*! @{ */ #define MIPI_DSI_CMD_PKT_STATUS_gen_cmd_empty_MASK (0x1U) #define MIPI_DSI_CMD_PKT_STATUS_gen_cmd_empty_SHIFT (0U) /*! gen_cmd_empty - This bit indicates the empty status of the generic command FIFO */ #define MIPI_DSI_CMD_PKT_STATUS_gen_cmd_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_cmd_empty_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_cmd_empty_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_cmd_full_MASK (0x2U) #define MIPI_DSI_CMD_PKT_STATUS_gen_cmd_full_SHIFT (1U) /*! gen_cmd_full - This bit indicates the full status of the generic command FIFO */ #define MIPI_DSI_CMD_PKT_STATUS_gen_cmd_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_cmd_full_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_cmd_full_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_empty_MASK (0x4U) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_empty_SHIFT (2U) /*! gen_pld_w_empty - This bit indicates the empty status of the generic write payload FIFO */ #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_empty_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_empty_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_full_MASK (0x8U) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_full_SHIFT (3U) /*! gen_pld_w_full - This bit indicates the full status of the generic write payload FIFO */ #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_full_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_pld_w_full_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_empty_MASK (0x10U) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_empty_SHIFT (4U) /*! gen_pld_r_empty - This bit indicates the empty status of the generic read payload FIFO */ #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_empty_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_empty_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_full_MASK (0x20U) #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_full_SHIFT (5U) /*! gen_pld_r_full - This bit indicates the full status of the generic read payload FIFO */ #define MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_full_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_pld_r_full_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_rd_cmd_busy_MASK (0x40U) #define MIPI_DSI_CMD_PKT_STATUS_gen_rd_cmd_busy_SHIFT (6U) /*! gen_rd_cmd_busy - This bit is set when a read command is issued and cleared when the entire * response is stored in the FIFO for GENERIC interface */ #define MIPI_DSI_CMD_PKT_STATUS_gen_rd_cmd_busy(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_rd_cmd_busy_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_rd_cmd_busy_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_7_MASK (0x80U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_7_SHIFT (7U) /*! reserved_7 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_7_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_7_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_8_MASK (0x100U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_8_SHIFT (8U) /*! reserved_8 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_8_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_8_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_9_MASK (0x200U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_9_SHIFT (9U) /*! reserved_9 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_9(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_9_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_9_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_10_MASK (0x400U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_10_SHIFT (10U) /*! reserved_10 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_10_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_10_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_11_MASK (0x800U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_11_SHIFT (11U) /*! reserved_11 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_11(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_11_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_11_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_12_MASK (0x1000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_12_SHIFT (12U) /*! reserved_12 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_12_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_12_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_13_MASK (0x2000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_13_SHIFT (13U) /*! reserved_13 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_13_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_13_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_14_MASK (0x4000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_14_SHIFT (14U) /*! reserved_14 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_14_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_14_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_15_MASK (0x8000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_15_SHIFT (15U) /*! reserved_15 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_15_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_15_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_empty_MASK (0x10000U) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_empty_SHIFT (16U) /*! gen_buff_cmd_empty - This bit indicates the empty status of the generic command internal buffer */ #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_empty_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_empty_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_full_MASK (0x20000U) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_full_SHIFT (17U) /*! gen_buff_cmd_full - This bit indicates the full status of the generic command internal buffer */ #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_full_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_buff_cmd_full_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_empty_MASK (0x40000U) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_empty_SHIFT (18U) /*! gen_buff_pld_empty - This bit indicates the empty status of the generic payload internal buffer */ #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_empty_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_empty_MASK) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_full_MASK (0x80000U) #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_full_SHIFT (19U) /*! gen_buff_pld_full - This bit indicates the full status of the generic payload internal buffer */ #define MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_full_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_gen_buff_pld_full_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_23_20_MASK (0xF00000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_23_20_SHIFT (20U) /*! reserved_23_20 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_23_20(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_23_20_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_23_20_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_24_MASK (0x1000000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_24_SHIFT (24U) /*! reserved_24 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_24(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_24_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_24_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_25_MASK (0x2000000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_25_SHIFT (25U) /*! reserved_25 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_25(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_25_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_25_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_26_MASK (0x4000000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_26_SHIFT (26U) /*! reserved_26 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_26(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_26_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_26_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_27_MASK (0x8000000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_27_SHIFT (27U) /*! reserved_27 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_27(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_27_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_27_MASK) #define MIPI_DSI_CMD_PKT_STATUS_reserved_31_28_MASK (0xF0000000U) #define MIPI_DSI_CMD_PKT_STATUS_reserved_31_28_SHIFT (28U) /*! reserved_31_28 - Reserved and read as zero */ #define MIPI_DSI_CMD_PKT_STATUS_reserved_31_28(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_CMD_PKT_STATUS_reserved_31_28_SHIFT)) & MIPI_DSI_CMD_PKT_STATUS_reserved_31_28_MASK) /*! @} */ /*! @name TO_CNT_CFG - Timeout Trigger Configuration */ /*! @{ */ #define MIPI_DSI_TO_CNT_CFG_lprx_to_cnt_MASK (0xFFFFU) #define MIPI_DSI_TO_CNT_CFG_lprx_to_cnt_SHIFT (0U) /*! lprx_to_cnt - This field configures the timeout counter that triggers a low-power reception * timeout contention detection (measured in TO_CLK_DIVISION cycles) */ #define MIPI_DSI_TO_CNT_CFG_lprx_to_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_TO_CNT_CFG_lprx_to_cnt_SHIFT)) & MIPI_DSI_TO_CNT_CFG_lprx_to_cnt_MASK) #define MIPI_DSI_TO_CNT_CFG_hstx_to_cnt_MASK (0xFFFF0000U) #define MIPI_DSI_TO_CNT_CFG_hstx_to_cnt_SHIFT (16U) /*! hstx_to_cnt - This field configures the timeout counter that triggers a high-speed transmission * timeout contention detection (measured in TO_CLK_DIVISION cycles) */ #define MIPI_DSI_TO_CNT_CFG_hstx_to_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_TO_CNT_CFG_hstx_to_cnt_SHIFT)) & MIPI_DSI_TO_CNT_CFG_hstx_to_cnt_MASK) /*! @} */ /*! @name HS_RD_TO_CNT - Peripheral timeout after HS read operations */ /*! @{ */ #define MIPI_DSI_HS_RD_TO_CNT_hs_rd_to_cnt_MASK (0xFFFFU) #define MIPI_DSI_HS_RD_TO_CNT_hs_rd_to_cnt_SHIFT (0U) /*! hs_rd_to_cnt - This field sets a period for which MIPI DSI host keeps the link still, after sending a high-speed Read operation */ #define MIPI_DSI_HS_RD_TO_CNT_hs_rd_to_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HS_RD_TO_CNT_hs_rd_to_cnt_SHIFT)) & MIPI_DSI_HS_RD_TO_CNT_hs_rd_to_cnt_MASK) #define MIPI_DSI_HS_RD_TO_CNT_reserved_31_16_MASK (0xFFFF0000U) #define MIPI_DSI_HS_RD_TO_CNT_reserved_31_16_SHIFT (16U) /*! reserved_31_16 - Reserved and read as zero */ #define MIPI_DSI_HS_RD_TO_CNT_reserved_31_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HS_RD_TO_CNT_reserved_31_16_SHIFT)) & MIPI_DSI_HS_RD_TO_CNT_reserved_31_16_MASK) /*! @} */ /*! @name LP_RD_TO_CNT - Peripheral timeout after LP read operations */ /*! @{ */ #define MIPI_DSI_LP_RD_TO_CNT_lp_rd_to_cnt_MASK (0xFFFFU) #define MIPI_DSI_LP_RD_TO_CNT_lp_rd_to_cnt_SHIFT (0U) /*! lp_rd_to_cnt - This field sets a period for which MIPI DSI host keeps the link still, after sending a low-power Read operation */ #define MIPI_DSI_LP_RD_TO_CNT_lp_rd_to_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LP_RD_TO_CNT_lp_rd_to_cnt_SHIFT)) & MIPI_DSI_LP_RD_TO_CNT_lp_rd_to_cnt_MASK) #define MIPI_DSI_LP_RD_TO_CNT_reserved_31_16_MASK (0xFFFF0000U) #define MIPI_DSI_LP_RD_TO_CNT_reserved_31_16_SHIFT (16U) /*! reserved_31_16 - Reserved and read as zero */ #define MIPI_DSI_LP_RD_TO_CNT_reserved_31_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LP_RD_TO_CNT_reserved_31_16_SHIFT)) & MIPI_DSI_LP_RD_TO_CNT_reserved_31_16_MASK) /*! @} */ /*! @name HS_WR_TO_CNT - Peripheral timeout after HS write operations */ /*! @{ */ #define MIPI_DSI_HS_WR_TO_CNT_hs_wr_to_cnt_MASK (0xFFFFU) #define MIPI_DSI_HS_WR_TO_CNT_hs_wr_to_cnt_SHIFT (0U) /*! hs_wr_to_cnt - This field sets a period for which MIPI DSI host keeps the link still, after sending a high-speed Write operation */ #define MIPI_DSI_HS_WR_TO_CNT_hs_wr_to_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HS_WR_TO_CNT_hs_wr_to_cnt_SHIFT)) & MIPI_DSI_HS_WR_TO_CNT_hs_wr_to_cnt_MASK) #define MIPI_DSI_HS_WR_TO_CNT_reserved_23_16_MASK (0xFF0000U) #define MIPI_DSI_HS_WR_TO_CNT_reserved_23_16_SHIFT (16U) /*! reserved_23_16 - Reserved and read as zero */ #define MIPI_DSI_HS_WR_TO_CNT_reserved_23_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HS_WR_TO_CNT_reserved_23_16_SHIFT)) & MIPI_DSI_HS_WR_TO_CNT_reserved_23_16_MASK) #define MIPI_DSI_HS_WR_TO_CNT_presp_to_mode_MASK (0x1000000U) #define MIPI_DSI_HS_WR_TO_CNT_presp_to_mode_SHIFT (24U) /*! presp_to_mode - presp_to_mode */ #define MIPI_DSI_HS_WR_TO_CNT_presp_to_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HS_WR_TO_CNT_presp_to_mode_SHIFT)) & MIPI_DSI_HS_WR_TO_CNT_presp_to_mode_MASK) #define MIPI_DSI_HS_WR_TO_CNT_reserved_31_25_MASK (0xFE000000U) #define MIPI_DSI_HS_WR_TO_CNT_reserved_31_25_SHIFT (25U) /*! reserved_31_25 - Reserved and read as zero */ #define MIPI_DSI_HS_WR_TO_CNT_reserved_31_25(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HS_WR_TO_CNT_reserved_31_25_SHIFT)) & MIPI_DSI_HS_WR_TO_CNT_reserved_31_25_MASK) /*! @} */ /*! @name LP_WR_TO_CNT - Peripheral timeout after LP write operations */ /*! @{ */ #define MIPI_DSI_LP_WR_TO_CNT_lp_wr_to_cnt_MASK (0xFFFFU) #define MIPI_DSI_LP_WR_TO_CNT_lp_wr_to_cnt_SHIFT (0U) /*! lp_wr_to_cnt - This field sets a period for which MIPI DSI host keeps the link still, after sending a low-power Write operation */ #define MIPI_DSI_LP_WR_TO_CNT_lp_wr_to_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LP_WR_TO_CNT_lp_wr_to_cnt_SHIFT)) & MIPI_DSI_LP_WR_TO_CNT_lp_wr_to_cnt_MASK) #define MIPI_DSI_LP_WR_TO_CNT_reserved_31_16_MASK (0xFFFF0000U) #define MIPI_DSI_LP_WR_TO_CNT_reserved_31_16_SHIFT (16U) /*! reserved_31_16 - Reserved and read as zero */ #define MIPI_DSI_LP_WR_TO_CNT_reserved_31_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LP_WR_TO_CNT_reserved_31_16_SHIFT)) & MIPI_DSI_LP_WR_TO_CNT_reserved_31_16_MASK) /*! @} */ /*! @name BTA_TO_CNT - Peripheral timeout after BTA completion */ /*! @{ */ #define MIPI_DSI_BTA_TO_CNT_bta_to_cnt_MASK (0xFFFFU) #define MIPI_DSI_BTA_TO_CNT_bta_to_cnt_SHIFT (0U) /*! bta_to_cnt - This field sets a period for which MIPI DSI host keeps the link still, after completing a Bus Turnaround */ #define MIPI_DSI_BTA_TO_CNT_bta_to_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_BTA_TO_CNT_bta_to_cnt_SHIFT)) & MIPI_DSI_BTA_TO_CNT_bta_to_cnt_MASK) #define MIPI_DSI_BTA_TO_CNT_reserved_31_16_MASK (0xFFFF0000U) #define MIPI_DSI_BTA_TO_CNT_reserved_31_16_SHIFT (16U) /*! reserved_31_16 - Reserved and read as zero */ #define MIPI_DSI_BTA_TO_CNT_reserved_31_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_BTA_TO_CNT_reserved_31_16_SHIFT)) & MIPI_DSI_BTA_TO_CNT_reserved_31_16_MASK) /*! @} */ /*! @name SDF_3D - 3D information for VSS packets */ /*! @{ */ #define MIPI_DSI_SDF_3D_mode_3d_MASK (0x3U) #define MIPI_DSI_SDF_3D_mode_3d_SHIFT (0U) /*! mode_3d - This field defines 3D Mode On/Off and Display Orientation: * 0b00..3D Mode Off , 2D Mode On * 0b01..3D Mode On, Portrait Orientation * 0b10..3D Mode On, Landscape Orientation * 0b11..Reserved, not used */ #define MIPI_DSI_SDF_3D_mode_3d(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_mode_3d_SHIFT)) & MIPI_DSI_SDF_3D_mode_3d_MASK) #define MIPI_DSI_SDF_3D_format_3d_MASK (0xCU) #define MIPI_DSI_SDF_3D_format_3d_SHIFT (2U) /*! format_3d - This field defines 3D Image Format: * 0b01..Alternating frames of left and right data * 0b00..Alternating lines of left and right data * 0b10..Alternating pixels of left and right data * 0b11..Reserved, not used */ #define MIPI_DSI_SDF_3D_format_3d(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_format_3d_SHIFT)) & MIPI_DSI_SDF_3D_format_3d_MASK) #define MIPI_DSI_SDF_3D_second_vsync_MASK (0x10U) #define MIPI_DSI_SDF_3D_second_vsync_SHIFT (4U) /*! second_vsync - This field defines whether there is a second VSYNC pulse between Left and Right * Images, when 3D Image Format is Frame-based: * 0b0..No sync pulses between left and right data * 0b1..Sync pulse HSYNC, VSYNC, blanking between left and right data */ #define MIPI_DSI_SDF_3D_second_vsync(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_second_vsync_SHIFT)) & MIPI_DSI_SDF_3D_second_vsync_MASK) #define MIPI_DSI_SDF_3D_right_first_MASK (0x20U) #define MIPI_DSI_SDF_3D_right_first_SHIFT (5U) /*! right_first - This bit defines the left/right order: * 0b0..left eye is sent first, then right eye * 0b1..right eye data is sent first, then left eye */ #define MIPI_DSI_SDF_3D_right_first(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_right_first_SHIFT)) & MIPI_DSI_SDF_3D_right_first_MASK) #define MIPI_DSI_SDF_3D_reserved_15_6_MASK (0xFFC0U) #define MIPI_DSI_SDF_3D_reserved_15_6_SHIFT (6U) /*! reserved_15_6 - Reserved and read as zero */ #define MIPI_DSI_SDF_3D_reserved_15_6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_reserved_15_6_SHIFT)) & MIPI_DSI_SDF_3D_reserved_15_6_MASK) #define MIPI_DSI_SDF_3D_send_3d_cfg_MASK (0x10000U) #define MIPI_DSI_SDF_3D_send_3d_cfg_SHIFT (16U) /*! send_3d_cfg - When set, causes the next VSS packet to include 3D control payload in every VSS packet */ #define MIPI_DSI_SDF_3D_send_3d_cfg(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_send_3d_cfg_SHIFT)) & MIPI_DSI_SDF_3D_send_3d_cfg_MASK) #define MIPI_DSI_SDF_3D_reserved_31_17_MASK (0xFFFE0000U) #define MIPI_DSI_SDF_3D_reserved_31_17_SHIFT (17U) /*! reserved_31_17 - Reserved and read as zero */ #define MIPI_DSI_SDF_3D_reserved_31_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_reserved_31_17_SHIFT)) & MIPI_DSI_SDF_3D_reserved_31_17_MASK) /*! @} */ /*! @name LPCLK_CTRL - Non-continuous Clock configuration */ /*! @{ */ #define MIPI_DSI_LPCLK_CTRL_phy_txrequestclkhs_MASK (0x1U) #define MIPI_DSI_LPCLK_CTRL_phy_txrequestclkhs_SHIFT (0U) /*! phy_txrequestclkhs - This bit controls the D-PHY PPI txrequestclkhs signal */ #define MIPI_DSI_LPCLK_CTRL_phy_txrequestclkhs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LPCLK_CTRL_phy_txrequestclkhs_SHIFT)) & MIPI_DSI_LPCLK_CTRL_phy_txrequestclkhs_MASK) #define MIPI_DSI_LPCLK_CTRL_auto_clklane_ctrl_MASK (0x2U) #define MIPI_DSI_LPCLK_CTRL_auto_clklane_ctrl_SHIFT (1U) /*! auto_clklane_ctrl - This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows */ #define MIPI_DSI_LPCLK_CTRL_auto_clklane_ctrl(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LPCLK_CTRL_auto_clklane_ctrl_SHIFT)) & MIPI_DSI_LPCLK_CTRL_auto_clklane_ctrl_MASK) #define MIPI_DSI_LPCLK_CTRL_reserved_31_2_MASK (0xFFFFFFFCU) #define MIPI_DSI_LPCLK_CTRL_reserved_31_2_SHIFT (2U) /*! reserved_31_2 - Reserved and read as zero */ #define MIPI_DSI_LPCLK_CTRL_reserved_31_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_LPCLK_CTRL_reserved_31_2_SHIFT)) & MIPI_DSI_LPCLK_CTRL_reserved_31_2_MASK) /*! @} */ /*! @name PHY_TMR_LPCLK_CFG - Time configuration for (clock lane) transitions between HS and LP */ /*! @{ */ #define MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clklp2hs_time_MASK (0x3FFU) #define MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clklp2hs_time_SHIFT (0U) /*! phy_clklp2hs_time - Low-Power to High speed transmission time for D-PHY clock lane */ #define MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clklp2hs_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clklp2hs_time_SHIFT)) & MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clklp2hs_time_MASK) #define MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_15_10_MASK (0xFC00U) #define MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_15_10_SHIFT (10U) /*! reserved_15_10 - Reserved and read as zero */ #define MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_15_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_15_10_SHIFT)) & MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_15_10_MASK) #define MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clkhs2lp_time_MASK (0x3FF0000U) #define MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clkhs2lp_time_SHIFT (16U) /*! phy_clkhs2lp_time - High speed to low-power transmission time for D-PHY clock lane */ #define MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clkhs2lp_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clkhs2lp_time_SHIFT)) & MIPI_DSI_PHY_TMR_LPCLK_CFG_phy_clkhs2lp_time_MASK) #define MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_31_26_MASK (0xFC000000U) #define MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_31_26_SHIFT (26U) /*! reserved_31_26 - Reserved and read as zero */ #define MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_31_26(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_31_26_SHIFT)) & MIPI_DSI_PHY_TMR_LPCLK_CFG_reserved_31_26_MASK) /*! @} */ /*! @name PHY_TMR_CFG - Time configuration for (data lanes) transitions between HS and LP */ /*! @{ */ #define MIPI_DSI_PHY_TMR_CFG_phy_lp2hs_time_MASK (0x3FFU) #define MIPI_DSI_PHY_TMR_CFG_phy_lp2hs_time_SHIFT (0U) /*! phy_lp2hs_time - Low-power to high-speed transmission time for D-PHY data lanes */ #define MIPI_DSI_PHY_TMR_CFG_phy_lp2hs_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_CFG_phy_lp2hs_time_SHIFT)) & MIPI_DSI_PHY_TMR_CFG_phy_lp2hs_time_MASK) #define MIPI_DSI_PHY_TMR_CFG_reserved_15_10_MASK (0xFC00U) #define MIPI_DSI_PHY_TMR_CFG_reserved_15_10_SHIFT (10U) /*! reserved_15_10 - Reserved and read as zero */ #define MIPI_DSI_PHY_TMR_CFG_reserved_15_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_CFG_reserved_15_10_SHIFT)) & MIPI_DSI_PHY_TMR_CFG_reserved_15_10_MASK) #define MIPI_DSI_PHY_TMR_CFG_phy_hs2lp_time_MASK (0x3FF0000U) #define MIPI_DSI_PHY_TMR_CFG_phy_hs2lp_time_SHIFT (16U) /*! phy_hs2lp_time - High-speed to low-power transmission time for D-PHY data lanes */ #define MIPI_DSI_PHY_TMR_CFG_phy_hs2lp_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_CFG_phy_hs2lp_time_SHIFT)) & MIPI_DSI_PHY_TMR_CFG_phy_hs2lp_time_MASK) #define MIPI_DSI_PHY_TMR_CFG_reserved_31_26_MASK (0xFC000000U) #define MIPI_DSI_PHY_TMR_CFG_reserved_31_26_SHIFT (26U) /*! reserved_31_26 - Reserved and read as zero */ #define MIPI_DSI_PHY_TMR_CFG_reserved_31_26(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_CFG_reserved_31_26_SHIFT)) & MIPI_DSI_PHY_TMR_CFG_reserved_31_26_MASK) /*! @} */ /*! @name PHY_RSTZ - D-PHY's PLL and Resets */ /*! @{ */ #define MIPI_DSI_PHY_RSTZ_phy_shutdownz_MASK (0x1U) #define MIPI_DSI_PHY_RSTZ_phy_shutdownz_SHIFT (0U) /*! phy_shutdownz - When set to 0, this bit places the complete D-PHY macro in power-down state */ #define MIPI_DSI_PHY_RSTZ_phy_shutdownz(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_RSTZ_phy_shutdownz_SHIFT)) & MIPI_DSI_PHY_RSTZ_phy_shutdownz_MASK) #define MIPI_DSI_PHY_RSTZ_phy_rstz_MASK (0x2U) #define MIPI_DSI_PHY_RSTZ_phy_rstz_SHIFT (1U) /*! phy_rstz - When set to 0, this bit places the digital section of the D-PHY in the reset state */ #define MIPI_DSI_PHY_RSTZ_phy_rstz(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_RSTZ_phy_rstz_SHIFT)) & MIPI_DSI_PHY_RSTZ_phy_rstz_MASK) #define MIPI_DSI_PHY_RSTZ_phy_enableclk_MASK (0x4U) #define MIPI_DSI_PHY_RSTZ_phy_enableclk_SHIFT (2U) /*! phy_enableclk - When set to 1, this bit enables the D-PHY Clock Lane Module */ #define MIPI_DSI_PHY_RSTZ_phy_enableclk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_RSTZ_phy_enableclk_SHIFT)) & MIPI_DSI_PHY_RSTZ_phy_enableclk_MASK) #define MIPI_DSI_PHY_RSTZ_phy_forcepll_MASK (0x8U) #define MIPI_DSI_PHY_RSTZ_phy_forcepll_SHIFT (3U) /*! phy_forcepll - When the D-PHY is in ULPS, this bit enables the D-PHY PLL */ #define MIPI_DSI_PHY_RSTZ_phy_forcepll(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_RSTZ_phy_forcepll_SHIFT)) & MIPI_DSI_PHY_RSTZ_phy_forcepll_MASK) #define MIPI_DSI_PHY_RSTZ_reserved_31_4_MASK (0xFFFFFFF0U) #define MIPI_DSI_PHY_RSTZ_reserved_31_4_SHIFT (4U) /*! reserved_31_4 - Reserved and read as zero */ #define MIPI_DSI_PHY_RSTZ_reserved_31_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_RSTZ_reserved_31_4_SHIFT)) & MIPI_DSI_PHY_RSTZ_reserved_31_4_MASK) /*! @} */ /*! @name PHY_IF_CFG - Active lanes and Stop State minimum time in Stop State */ /*! @{ */ #define MIPI_DSI_PHY_IF_CFG_n_lanes_MASK (0x3U) #define MIPI_DSI_PHY_IF_CFG_n_lanes_SHIFT (0U) /*! n_lanes - This field configures the number of active data lanes: * 0b11..lanes 0, 1, 2, and 3 * 0b00..lane 0 * 0b10..lanes 0, 1, and 2 * 0b01..lanes 0 and 1 */ #define MIPI_DSI_PHY_IF_CFG_n_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_IF_CFG_n_lanes_SHIFT)) & MIPI_DSI_PHY_IF_CFG_n_lanes_MASK) #define MIPI_DSI_PHY_IF_CFG_reserved_7_2_MASK (0xFCU) #define MIPI_DSI_PHY_IF_CFG_reserved_7_2_SHIFT (2U) /*! reserved_7_2 - Reserved and read as zero */ #define MIPI_DSI_PHY_IF_CFG_reserved_7_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_IF_CFG_reserved_7_2_SHIFT)) & MIPI_DSI_PHY_IF_CFG_reserved_7_2_MASK) #define MIPI_DSI_PHY_IF_CFG_phy_stop_wait_time_MASK (0xFF00U) #define MIPI_DSI_PHY_IF_CFG_phy_stop_wait_time_SHIFT (8U) /*! phy_stop_wait_time - This field configures the minimum time PHY needs to stay in StopState before requesting an high-speed transmission */ #define MIPI_DSI_PHY_IF_CFG_phy_stop_wait_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_IF_CFG_phy_stop_wait_time_SHIFT)) & MIPI_DSI_PHY_IF_CFG_phy_stop_wait_time_MASK) #define MIPI_DSI_PHY_IF_CFG_reserved_31_16_MASK (0xFFFF0000U) #define MIPI_DSI_PHY_IF_CFG_reserved_31_16_SHIFT (16U) /*! reserved_31_16 - Reserved and read as zero */ #define MIPI_DSI_PHY_IF_CFG_reserved_31_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_IF_CFG_reserved_31_16_SHIFT)) & MIPI_DSI_PHY_IF_CFG_reserved_31_16_MASK) /*! @} */ /*! @name PHY_ULPS_CTRL - Transitions from and to ULPS, using D-PHY */ /*! @{ */ #define MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpsclk_MASK (0x1U) #define MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpsclk_SHIFT (0U) /*! phy_txrequlpsclk - ULPS mode Request on clock lane */ #define MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpsclk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpsclk_SHIFT)) & MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpsclk_MASK) #define MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpsclk_MASK (0x2U) #define MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpsclk_SHIFT (1U) /*! phy_txexitulpsclk - ULPS mode Exit on clock lane */ #define MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpsclk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpsclk_SHIFT)) & MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpsclk_MASK) #define MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpslan_MASK (0x4U) #define MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpslan_SHIFT (2U) /*! phy_txrequlpslan - ULPS mode Request on all active data lanes */ #define MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpslan(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpslan_SHIFT)) & MIPI_DSI_PHY_ULPS_CTRL_phy_txrequlpslan_MASK) #define MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpslan_MASK (0x8U) #define MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpslan_SHIFT (3U) /*! phy_txexitulpslan - ULPS mode Exit on all active data lanes */ #define MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpslan(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpslan_SHIFT)) & MIPI_DSI_PHY_ULPS_CTRL_phy_txexitulpslan_MASK) #define MIPI_DSI_PHY_ULPS_CTRL_reserved_31_4_MASK (0xFFFFFFF0U) #define MIPI_DSI_PHY_ULPS_CTRL_reserved_31_4_SHIFT (4U) /*! reserved_31_4 - Reserved and read as zero */ #define MIPI_DSI_PHY_ULPS_CTRL_reserved_31_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_ULPS_CTRL_reserved_31_4_SHIFT)) & MIPI_DSI_PHY_ULPS_CTRL_reserved_31_4_MASK) /*! @} */ /*! @name PHY_TX_TRIGGERS - Pins related to D-PHY triggers */ /*! @{ */ #define MIPI_DSI_PHY_TX_TRIGGERS_phy_tx_triggers_MASK (0xFU) #define MIPI_DSI_PHY_TX_TRIGGERS_phy_tx_triggers_SHIFT (0U) /*! phy_tx_triggers - This field controls the trigger transmissions */ #define MIPI_DSI_PHY_TX_TRIGGERS_phy_tx_triggers(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TX_TRIGGERS_phy_tx_triggers_SHIFT)) & MIPI_DSI_PHY_TX_TRIGGERS_phy_tx_triggers_MASK) #define MIPI_DSI_PHY_TX_TRIGGERS_reserved_31_4_MASK (0xFFFFFFF0U) #define MIPI_DSI_PHY_TX_TRIGGERS_reserved_31_4_SHIFT (4U) /*! reserved_31_4 - Reserved and read as zero */ #define MIPI_DSI_PHY_TX_TRIGGERS_reserved_31_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TX_TRIGGERS_reserved_31_4_SHIFT)) & MIPI_DSI_PHY_TX_TRIGGERS_reserved_31_4_MASK) /*! @} */ /*! @name PHY_STATUS - D-PHY Status */ /*! @{ */ #define MIPI_DSI_PHY_STATUS_phy_lock_MASK (0x1U) #define MIPI_DSI_PHY_STATUS_phy_lock_SHIFT (0U) /*! phy_lock - This bit indicates the status of phylock D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_lock(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_lock_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_lock_MASK) #define MIPI_DSI_PHY_STATUS_phy_direction_MASK (0x2U) #define MIPI_DSI_PHY_STATUS_phy_direction_SHIFT (1U) /*! phy_direction - This bit indicates the status of phydirection D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_direction(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_direction_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_direction_MASK) #define MIPI_DSI_PHY_STATUS_phy_stopstateclklane_MASK (0x4U) #define MIPI_DSI_PHY_STATUS_phy_stopstateclklane_SHIFT (2U) /*! phy_stopstateclklane - This bit indicates the status of phystopstateclklane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_stopstateclklane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_stopstateclklane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_stopstateclklane_MASK) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenotclk_MASK (0x8U) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenotclk_SHIFT (3U) /*! phy_ulpsactivenotclk - This bit indicates the status of phyulpsactivenotclk D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenotclk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_ulpsactivenotclk_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_ulpsactivenotclk_MASK) #define MIPI_DSI_PHY_STATUS_phy_stopstate0lane_MASK (0x10U) #define MIPI_DSI_PHY_STATUS_phy_stopstate0lane_SHIFT (4U) /*! phy_stopstate0lane - This bit indicates the status of phystopstate0lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_stopstate0lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_stopstate0lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_stopstate0lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot0lane_MASK (0x20U) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot0lane_SHIFT (5U) /*! phy_ulpsactivenot0lane - This bit indicates the status of ulpsactivenot0lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot0lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_ulpsactivenot0lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_ulpsactivenot0lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_rxulpsesc0lane_MASK (0x40U) #define MIPI_DSI_PHY_STATUS_phy_rxulpsesc0lane_SHIFT (6U) /*! phy_rxulpsesc0lane - This bit indicates the status of rxulpsesc0lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_rxulpsesc0lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_rxulpsesc0lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_rxulpsesc0lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_stopstate1lane_MASK (0x80U) #define MIPI_DSI_PHY_STATUS_phy_stopstate1lane_SHIFT (7U) /*! phy_stopstate1lane - This bit indicates the status of phystopstate1lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_stopstate1lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_stopstate1lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_stopstate1lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot1lane_MASK (0x100U) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot1lane_SHIFT (8U) /*! phy_ulpsactivenot1lane - This bit indicates the status of ulpsactivenot1lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot1lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_ulpsactivenot1lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_ulpsactivenot1lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_stopstate2lane_MASK (0x200U) #define MIPI_DSI_PHY_STATUS_phy_stopstate2lane_SHIFT (9U) /*! phy_stopstate2lane - This bit indicates the status of phystopstate2lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_stopstate2lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_stopstate2lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_stopstate2lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot2lane_MASK (0x400U) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot2lane_SHIFT (10U) /*! phy_ulpsactivenot2lane - This bit indicates the status of ulpsactivenot2lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot2lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_ulpsactivenot2lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_ulpsactivenot2lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_stopstate3lane_MASK (0x800U) #define MIPI_DSI_PHY_STATUS_phy_stopstate3lane_SHIFT (11U) /*! phy_stopstate3lane - This bit indicates the status of phystopstate3lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_stopstate3lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_stopstate3lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_stopstate3lane_MASK) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot3lane_MASK (0x1000U) #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot3lane_SHIFT (12U) /*! phy_ulpsactivenot3lane - This bit indicates the status of ulpsactivenot3lane D-PHY signal */ #define MIPI_DSI_PHY_STATUS_phy_ulpsactivenot3lane(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_phy_ulpsactivenot3lane_SHIFT)) & MIPI_DSI_PHY_STATUS_phy_ulpsactivenot3lane_MASK) #define MIPI_DSI_PHY_STATUS_reserved_31_13_MASK (0xFFFFE000U) #define MIPI_DSI_PHY_STATUS_reserved_31_13_SHIFT (13U) /*! reserved_31_13 - Reserved and read as zero */ #define MIPI_DSI_PHY_STATUS_reserved_31_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_STATUS_reserved_31_13_SHIFT)) & MIPI_DSI_PHY_STATUS_reserved_31_13_MASK) /*! @} */ /*! @name PHY_TST_CTRL0 - D-PHY control and clear pins */ /*! @{ */ #define MIPI_DSI_PHY_TST_CTRL0_phy_testclr_MASK (0x1U) #define MIPI_DSI_PHY_TST_CTRL0_phy_testclr_SHIFT (0U) /*! phy_testclr - Bi-Dir D-PHY TX test interface clear (active high) */ #define MIPI_DSI_PHY_TST_CTRL0_phy_testclr(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL0_phy_testclr_SHIFT)) & MIPI_DSI_PHY_TST_CTRL0_phy_testclr_MASK) #define MIPI_DSI_PHY_TST_CTRL0_phy_testclk_MASK (0x2U) #define MIPI_DSI_PHY_TST_CTRL0_phy_testclk_SHIFT (1U) /*! phy_testclk - This bit is used to clock the TX TESTDIN bus into the D-PHY */ #define MIPI_DSI_PHY_TST_CTRL0_phy_testclk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL0_phy_testclk_SHIFT)) & MIPI_DSI_PHY_TST_CTRL0_phy_testclk_MASK) #define MIPI_DSI_PHY_TST_CTRL0_reserved_31_2_MASK (0xFFFFFFFCU) #define MIPI_DSI_PHY_TST_CTRL0_reserved_31_2_SHIFT (2U) /*! reserved_31_2 - Reserved and read as zero */ #define MIPI_DSI_PHY_TST_CTRL0_reserved_31_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL0_reserved_31_2_SHIFT)) & MIPI_DSI_PHY_TST_CTRL0_reserved_31_2_MASK) /*! @} */ /*! @name PHY_TST_CTRL1 - D-PHY data and enable pins */ /*! @{ */ #define MIPI_DSI_PHY_TST_CTRL1_phy_testdin_MASK (0xFFU) #define MIPI_DSI_PHY_TST_CTRL1_phy_testdin_SHIFT (0U) /*! phy_testdin - PHY test interface input 8-bit data bus for internal register programming and test functionalities access */ #define MIPI_DSI_PHY_TST_CTRL1_phy_testdin(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL1_phy_testdin_SHIFT)) & MIPI_DSI_PHY_TST_CTRL1_phy_testdin_MASK) #define MIPI_DSI_PHY_TST_CTRL1_pht_testdout_MASK (0xFF00U) #define MIPI_DSI_PHY_TST_CTRL1_pht_testdout_SHIFT (8U) /*! pht_testdout - PHY output 8-bit data bus for read-back and internal probing functionalities */ #define MIPI_DSI_PHY_TST_CTRL1_pht_testdout(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL1_pht_testdout_SHIFT)) & MIPI_DSI_PHY_TST_CTRL1_pht_testdout_MASK) #define MIPI_DSI_PHY_TST_CTRL1_phy_testen_MASK (0x10000U) #define MIPI_DSI_PHY_TST_CTRL1_phy_testen_SHIFT (16U) /*! phy_testen - PHY test interface operation selector: * 0b1..the address write operation is set on the falling edge of the testclk signal * 0b0..the data write operation is set on the rising edge of the testclk signal */ #define MIPI_DSI_PHY_TST_CTRL1_phy_testen(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL1_phy_testen_SHIFT)) & MIPI_DSI_PHY_TST_CTRL1_phy_testen_MASK) #define MIPI_DSI_PHY_TST_CTRL1_reserved_17_MASK (0x20000U) #define MIPI_DSI_PHY_TST_CTRL1_reserved_17_SHIFT (17U) /*! reserved_17 - Reserved and read as zero */ #define MIPI_DSI_PHY_TST_CTRL1_reserved_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL1_reserved_17_SHIFT)) & MIPI_DSI_PHY_TST_CTRL1_reserved_17_MASK) #define MIPI_DSI_PHY_TST_CTRL1_reserved_31_18_MASK (0xFFFC0000U) #define MIPI_DSI_PHY_TST_CTRL1_reserved_31_18_SHIFT (18U) /*! reserved_31_18 - Reserved and read as zero */ #define MIPI_DSI_PHY_TST_CTRL1_reserved_31_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TST_CTRL1_reserved_31_18_SHIFT)) & MIPI_DSI_PHY_TST_CTRL1_reserved_31_18_MASK) /*! @} */ /*! @name INT_ST0 - Interrupts status 0 */ /*! @{ */ #define MIPI_DSI_INT_ST0_ack_with_err_0_MASK (0x1U) #define MIPI_DSI_INT_ST0_ack_with_err_0_SHIFT (0U) /*! ack_with_err_0 - This bit retrieves the SoT error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_0_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_0_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_1_MASK (0x2U) #define MIPI_DSI_INT_ST0_ack_with_err_1_SHIFT (1U) /*! ack_with_err_1 - This bit retrieves the SoT Sync error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_1_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_1_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_2_MASK (0x4U) #define MIPI_DSI_INT_ST0_ack_with_err_2_SHIFT (2U) /*! ack_with_err_2 - This bit retrieves the EoT Sync error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_2_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_2_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_3_MASK (0x8U) #define MIPI_DSI_INT_ST0_ack_with_err_3_SHIFT (3U) /*! ack_with_err_3 - This bit retrieves the Escape Mode Entry Command error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_3_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_3_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_4_MASK (0x10U) #define MIPI_DSI_INT_ST0_ack_with_err_4_SHIFT (4U) /*! ack_with_err_4 - This bit retrieves the low-power Transmit Sync error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_4_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_4_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_5_MASK (0x20U) #define MIPI_DSI_INT_ST0_ack_with_err_5_SHIFT (5U) /*! ack_with_err_5 - This bit retrieves the Peripheral Timeout error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_5(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_5_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_5_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_6_MASK (0x40U) #define MIPI_DSI_INT_ST0_ack_with_err_6_SHIFT (6U) /*! ack_with_err_6 - This bit retrieves the False Control error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_6_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_6_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_7_MASK (0x80U) #define MIPI_DSI_INT_ST0_ack_with_err_7_SHIFT (7U) /*! ack_with_err_7 - This bit retrieves the Contention Detected error from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_7_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_7_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_8_MASK (0x100U) #define MIPI_DSI_INT_ST0_ack_with_err_8_SHIFT (8U) /*! ack_with_err_8 - This bit retrieves the ECC error, single-bit (detected and corrected) from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_8_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_8_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_9_MASK (0x200U) #define MIPI_DSI_INT_ST0_ack_with_err_9_SHIFT (9U) /*! ack_with_err_9 - This bit retrieves the ECC error, multi-bit (detected, not corrected) from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_9(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_9_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_9_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_10_MASK (0x400U) #define MIPI_DSI_INT_ST0_ack_with_err_10_SHIFT (10U) /*! ack_with_err_10 - This bit retrieves the checksum error (long packet only) from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_10_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_10_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_11_MASK (0x800U) #define MIPI_DSI_INT_ST0_ack_with_err_11_SHIFT (11U) /*! ack_with_err_11 - This bit retrieves the not recognized DSI data type from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_11(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_11_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_11_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_12_MASK (0x1000U) #define MIPI_DSI_INT_ST0_ack_with_err_12_SHIFT (12U) /*! ack_with_err_12 - This bit retrieves the DSI VC ID Invalid from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_12_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_12_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_13_MASK (0x2000U) #define MIPI_DSI_INT_ST0_ack_with_err_13_SHIFT (13U) /*! ack_with_err_13 - This bit retrieves the invalid transmission length from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_13_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_13_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_14_MASK (0x4000U) #define MIPI_DSI_INT_ST0_ack_with_err_14_SHIFT (14U) /*! ack_with_err_14 - This bit retrieves the reserved (specific to device) from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_14_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_14_MASK) #define MIPI_DSI_INT_ST0_ack_with_err_15_MASK (0x8000U) #define MIPI_DSI_INT_ST0_ack_with_err_15_SHIFT (15U) /*! ack_with_err_15 - This bit retrieves the DSI protocol violation from the Acknowledge error report */ #define MIPI_DSI_INT_ST0_ack_with_err_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_ack_with_err_15_SHIFT)) & MIPI_DSI_INT_ST0_ack_with_err_15_MASK) #define MIPI_DSI_INT_ST0_dphy_errors_0_MASK (0x10000U) #define MIPI_DSI_INT_ST0_dphy_errors_0_SHIFT (16U) /*! dphy_errors_0 - This bit indicates ErrEsc escape entry error from Lane 0 */ #define MIPI_DSI_INT_ST0_dphy_errors_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_dphy_errors_0_SHIFT)) & MIPI_DSI_INT_ST0_dphy_errors_0_MASK) #define MIPI_DSI_INT_ST0_dphy_errors_1_MASK (0x20000U) #define MIPI_DSI_INT_ST0_dphy_errors_1_SHIFT (17U) /*! dphy_errors_1 - This bit indicates ErrSyncEsc low-power data transmission synchronization error from Lane 0 */ #define MIPI_DSI_INT_ST0_dphy_errors_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_dphy_errors_1_SHIFT)) & MIPI_DSI_INT_ST0_dphy_errors_1_MASK) #define MIPI_DSI_INT_ST0_dphy_errors_2_MASK (0x40000U) #define MIPI_DSI_INT_ST0_dphy_errors_2_SHIFT (18U) /*! dphy_errors_2 - This bit indicates control error ErrControl from Lane 0 */ #define MIPI_DSI_INT_ST0_dphy_errors_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_dphy_errors_2_SHIFT)) & MIPI_DSI_INT_ST0_dphy_errors_2_MASK) #define MIPI_DSI_INT_ST0_dphy_errors_3_MASK (0x80000U) #define MIPI_DSI_INT_ST0_dphy_errors_3_SHIFT (19U) /*! dphy_errors_3 - This bit indicates LP0 contention error ErrContentionLP0 from Lane 0 */ #define MIPI_DSI_INT_ST0_dphy_errors_3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_dphy_errors_3_SHIFT)) & MIPI_DSI_INT_ST0_dphy_errors_3_MASK) #define MIPI_DSI_INT_ST0_dphy_errors_4_MASK (0x100000U) #define MIPI_DSI_INT_ST0_dphy_errors_4_SHIFT (20U) /*! dphy_errors_4 - This bit indicates LP1 contention error ErrContentionLP1 from Lane 0 */ #define MIPI_DSI_INT_ST0_dphy_errors_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_dphy_errors_4_SHIFT)) & MIPI_DSI_INT_ST0_dphy_errors_4_MASK) #define MIPI_DSI_INT_ST0_reserved_31_21_MASK (0xFFE00000U) #define MIPI_DSI_INT_ST0_reserved_31_21_SHIFT (21U) /*! reserved_31_21 - Reserved and read as zero */ #define MIPI_DSI_INT_ST0_reserved_31_21(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST0_reserved_31_21_SHIFT)) & MIPI_DSI_INT_ST0_reserved_31_21_MASK) /*! @} */ /*! @name INT_ST1 - Interrupts Status 1 */ /*! @{ */ #define MIPI_DSI_INT_ST1_to_hs_tx_MASK (0x1U) #define MIPI_DSI_INT_ST1_to_hs_tx_SHIFT (0U) /*! to_hs_tx - This bit indicates that the high-speed transmission timeout counter reached the end and contention has been detected */ #define MIPI_DSI_INT_ST1_to_hs_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_to_hs_tx_SHIFT)) & MIPI_DSI_INT_ST1_to_hs_tx_MASK) #define MIPI_DSI_INT_ST1_to_lp_rx_MASK (0x2U) #define MIPI_DSI_INT_ST1_to_lp_rx_SHIFT (1U) /*! to_lp_rx - This bit indicates that the low-power reception timeout counter reached the end and contention has been detected */ #define MIPI_DSI_INT_ST1_to_lp_rx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_to_lp_rx_SHIFT)) & MIPI_DSI_INT_ST1_to_lp_rx_MASK) #define MIPI_DSI_INT_ST1_ecc_single_err_MASK (0x4U) #define MIPI_DSI_INT_ST1_ecc_single_err_SHIFT (2U) /*! ecc_single_err - This bit indicates that the ECC single error has been detected and corrected in a received packet */ #define MIPI_DSI_INT_ST1_ecc_single_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_ecc_single_err_SHIFT)) & MIPI_DSI_INT_ST1_ecc_single_err_MASK) #define MIPI_DSI_INT_ST1_ecc_multpl_err_MASK (0x8U) #define MIPI_DSI_INT_ST1_ecc_multpl_err_SHIFT (3U) /*! ecc_multpl_err - This bit indicates that the ECC multiple error has been detected in a received packet */ #define MIPI_DSI_INT_ST1_ecc_multpl_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_ecc_multpl_err_SHIFT)) & MIPI_DSI_INT_ST1_ecc_multpl_err_MASK) #define MIPI_DSI_INT_ST1_crc_err_MASK (0x10U) #define MIPI_DSI_INT_ST1_crc_err_SHIFT (4U) /*! crc_err - This bit indicates that the CRC error has been detected in the received packet payload */ #define MIPI_DSI_INT_ST1_crc_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_crc_err_SHIFT)) & MIPI_DSI_INT_ST1_crc_err_MASK) #define MIPI_DSI_INT_ST1_pkt_size_err_MASK (0x20U) #define MIPI_DSI_INT_ST1_pkt_size_err_SHIFT (5U) /*! pkt_size_err - This bit indicates that the packet size error has been detected during the packet reception */ #define MIPI_DSI_INT_ST1_pkt_size_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_pkt_size_err_SHIFT)) & MIPI_DSI_INT_ST1_pkt_size_err_MASK) #define MIPI_DSI_INT_ST1_eopt_err_MASK (0x40U) #define MIPI_DSI_INT_ST1_eopt_err_SHIFT (6U) /*! eopt_err - This bit indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission */ #define MIPI_DSI_INT_ST1_eopt_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_eopt_err_SHIFT)) & MIPI_DSI_INT_ST1_eopt_err_MASK) #define MIPI_DSI_INT_ST1_dpi_pld_wr_err_MASK (0x80U) #define MIPI_DSI_INT_ST1_dpi_pld_wr_err_SHIFT (7U) /*! dpi_pld_wr_err - This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted */ #define MIPI_DSI_INT_ST1_dpi_pld_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_dpi_pld_wr_err_SHIFT)) & MIPI_DSI_INT_ST1_dpi_pld_wr_err_MASK) #define MIPI_DSI_INT_ST1_gen_cmd_wr_err_MASK (0x100U) #define MIPI_DSI_INT_ST1_gen_cmd_wr_err_SHIFT (8U) /*! gen_cmd_wr_err - This bit indicates that the system tried to write a command through the Generic interface and the FIFO is full */ #define MIPI_DSI_INT_ST1_gen_cmd_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_gen_cmd_wr_err_SHIFT)) & MIPI_DSI_INT_ST1_gen_cmd_wr_err_MASK) #define MIPI_DSI_INT_ST1_gen_pld_wr_err_MASK (0x200U) #define MIPI_DSI_INT_ST1_gen_pld_wr_err_SHIFT (9U) /*! gen_pld_wr_err - This bit indicates that the system tried to write a payload data through the Generic interface and the FIFO is full */ #define MIPI_DSI_INT_ST1_gen_pld_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_gen_pld_wr_err_SHIFT)) & MIPI_DSI_INT_ST1_gen_pld_wr_err_MASK) #define MIPI_DSI_INT_ST1_gen_pld_send_err_MASK (0x400U) #define MIPI_DSI_INT_ST1_gen_pld_send_err_SHIFT (10U) /*! gen_pld_send_err - This bit indicates that during a Generic interface packet build, the payload FIFO becomes empty and corrupt data is sent */ #define MIPI_DSI_INT_ST1_gen_pld_send_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_gen_pld_send_err_SHIFT)) & MIPI_DSI_INT_ST1_gen_pld_send_err_MASK) #define MIPI_DSI_INT_ST1_gen_pld_rd_err_MASK (0x800U) #define MIPI_DSI_INT_ST1_gen_pld_rd_err_SHIFT (11U) /*! gen_pld_rd_err - This bit indicates that during a DCS read data, the payload FIFO becomes empty * and the data sent to the interface is corrupted */ #define MIPI_DSI_INT_ST1_gen_pld_rd_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_gen_pld_rd_err_SHIFT)) & MIPI_DSI_INT_ST1_gen_pld_rd_err_MASK) #define MIPI_DSI_INT_ST1_gen_pld_recev_err_MASK (0x1000U) #define MIPI_DSI_INT_ST1_gen_pld_recev_err_SHIFT (12U) /*! gen_pld_recev_err - This bit indicates that during a generic interface packet read back, the * payload FIFO becomes full and the received data is corrupted */ #define MIPI_DSI_INT_ST1_gen_pld_recev_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_gen_pld_recev_err_SHIFT)) & MIPI_DSI_INT_ST1_gen_pld_recev_err_MASK) #define MIPI_DSI_INT_ST1_reserved_13_MASK (0x2000U) #define MIPI_DSI_INT_ST1_reserved_13_SHIFT (13U) /*! reserved_13 - Reserved and read as zero */ #define MIPI_DSI_INT_ST1_reserved_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_reserved_13_SHIFT)) & MIPI_DSI_INT_ST1_reserved_13_MASK) #define MIPI_DSI_INT_ST1_reserved_14_MASK (0x4000U) #define MIPI_DSI_INT_ST1_reserved_14_SHIFT (14U) /*! reserved_14 - Reserved and read as zero */ #define MIPI_DSI_INT_ST1_reserved_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_reserved_14_SHIFT)) & MIPI_DSI_INT_ST1_reserved_14_MASK) #define MIPI_DSI_INT_ST1_reserved_15_MASK (0x8000U) #define MIPI_DSI_INT_ST1_reserved_15_SHIFT (15U) /*! reserved_15 - Reserved and read as zero */ #define MIPI_DSI_INT_ST1_reserved_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_reserved_15_SHIFT)) & MIPI_DSI_INT_ST1_reserved_15_MASK) #define MIPI_DSI_INT_ST1_reserved_16_MASK (0x10000U) #define MIPI_DSI_INT_ST1_reserved_16_SHIFT (16U) /*! reserved_16 - Reserved and read as zero */ #define MIPI_DSI_INT_ST1_reserved_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_reserved_16_SHIFT)) & MIPI_DSI_INT_ST1_reserved_16_MASK) #define MIPI_DSI_INT_ST1_reserved_17_MASK (0x20000U) #define MIPI_DSI_INT_ST1_reserved_17_SHIFT (17U) /*! reserved_17 - Reserved and read as zero */ #define MIPI_DSI_INT_ST1_reserved_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_reserved_17_SHIFT)) & MIPI_DSI_INT_ST1_reserved_17_MASK) #define MIPI_DSI_INT_ST1_reserved_18_MASK (0x40000U) #define MIPI_DSI_INT_ST1_reserved_18_SHIFT (18U) /*! reserved_18 - Reserved and read as zero */ #define MIPI_DSI_INT_ST1_reserved_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_reserved_18_SHIFT)) & MIPI_DSI_INT_ST1_reserved_18_MASK) #define MIPI_DSI_INT_ST1_dpi_buff_pld_under_MASK (0x80000U) #define MIPI_DSI_INT_ST1_dpi_buff_pld_under_SHIFT (19U) /*! dpi_buff_pld_under - This bit indicates that an underflow has occurred when reading payload to build DSI packet for video mode */ #define MIPI_DSI_INT_ST1_dpi_buff_pld_under(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_dpi_buff_pld_under_SHIFT)) & MIPI_DSI_INT_ST1_dpi_buff_pld_under_MASK) #define MIPI_DSI_INT_ST1_tear_request_err_MASK (0x100000U) #define MIPI_DSI_INT_ST1_tear_request_err_SHIFT (20U) /*! tear_request_err - This bit indicates that tear_request has occurred but tear effect is not active in DSI host and device */ #define MIPI_DSI_INT_ST1_tear_request_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_tear_request_err_SHIFT)) & MIPI_DSI_INT_ST1_tear_request_err_MASK) #define MIPI_DSI_INT_ST1_reserved_31_21_MASK (0xFFE00000U) #define MIPI_DSI_INT_ST1_reserved_31_21_SHIFT (21U) /*! reserved_31_21 - Reserved and read as zero */ #define MIPI_DSI_INT_ST1_reserved_31_21(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_ST1_reserved_31_21_SHIFT)) & MIPI_DSI_INT_ST1_reserved_31_21_MASK) /*! @} */ /*! @name INT_MSK0 - INT_ST0 mask */ /*! @{ */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_0_MASK (0x1U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_0_SHIFT (0U) /*! mask_ack_with_err_0 - Mask for ack_with_err_0 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_0_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_0_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_1_MASK (0x2U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_1_SHIFT (1U) /*! mask_ack_with_err_1 - Mask for ack_with_err_1 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_1_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_1_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_2_MASK (0x4U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_2_SHIFT (2U) /*! mask_ack_with_err_2 - Mask for ack_with_err_2 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_2_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_2_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_3_MASK (0x8U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_3_SHIFT (3U) /*! mask_ack_with_err_3 - Mask for ack_with_err_3 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_3_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_3_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_4_MASK (0x10U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_4_SHIFT (4U) /*! mask_ack_with_err_4 - Mask for ack_with_err_4 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_4_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_4_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_5_MASK (0x20U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_5_SHIFT (5U) /*! mask_ack_with_err_5 - Mask for ack_with_err_5 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_5(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_5_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_5_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_6_MASK (0x40U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_6_SHIFT (6U) /*! mask_ack_with_err_6 - Mask for ack_with_err_6 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_6_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_6_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_7_MASK (0x80U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_7_SHIFT (7U) /*! mask_ack_with_err_7 - Mask for ack_with_err_7 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_7_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_7_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_8_MASK (0x100U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_8_SHIFT (8U) /*! mask_ack_with_err_8 - Mask for ack_with_err_8 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_8_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_8_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_9_MASK (0x200U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_9_SHIFT (9U) /*! mask_ack_with_err_9 - Mask for ack_with_err_9 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_9(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_9_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_9_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_10_MASK (0x400U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_10_SHIFT (10U) /*! mask_ack_with_err_10 - Mask for ack_with_err_10 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_10_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_10_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_11_MASK (0x800U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_11_SHIFT (11U) /*! mask_ack_with_err_11 - Mask for ack_with_err_11 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_11(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_11_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_11_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_12_MASK (0x1000U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_12_SHIFT (12U) /*! mask_ack_with_err_12 - Mask for ack_with_err_12 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_12_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_12_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_13_MASK (0x2000U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_13_SHIFT (13U) /*! mask_ack_with_err_13 - Mask for ack_with_err_13 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_13_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_13_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_14_MASK (0x4000U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_14_SHIFT (14U) /*! mask_ack_with_err_14 - Mask for ack_with_err_14 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_14_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_14_MASK) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_15_MASK (0x8000U) #define MIPI_DSI_INT_MSK0_mask_ack_with_err_15_SHIFT (15U) /*! mask_ack_with_err_15 - Mask for ack_with_err_15 */ #define MIPI_DSI_INT_MSK0_mask_ack_with_err_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_ack_with_err_15_SHIFT)) & MIPI_DSI_INT_MSK0_mask_ack_with_err_15_MASK) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_0_MASK (0x10000U) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_0_SHIFT (16U) /*! mask_dphy_errors_0 - Mask for dphy_errors_0 */ #define MIPI_DSI_INT_MSK0_mask_dphy_errors_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_dphy_errors_0_SHIFT)) & MIPI_DSI_INT_MSK0_mask_dphy_errors_0_MASK) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_1_MASK (0x20000U) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_1_SHIFT (17U) /*! mask_dphy_errors_1 - Mask for dphy_errors_1 */ #define MIPI_DSI_INT_MSK0_mask_dphy_errors_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_dphy_errors_1_SHIFT)) & MIPI_DSI_INT_MSK0_mask_dphy_errors_1_MASK) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_2_MASK (0x40000U) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_2_SHIFT (18U) /*! mask_dphy_errors_2 - Mask for dphy_errors_2 */ #define MIPI_DSI_INT_MSK0_mask_dphy_errors_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_dphy_errors_2_SHIFT)) & MIPI_DSI_INT_MSK0_mask_dphy_errors_2_MASK) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_3_MASK (0x80000U) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_3_SHIFT (19U) /*! mask_dphy_errors_3 - Mask for dphy_errors_3 */ #define MIPI_DSI_INT_MSK0_mask_dphy_errors_3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_dphy_errors_3_SHIFT)) & MIPI_DSI_INT_MSK0_mask_dphy_errors_3_MASK) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_4_MASK (0x100000U) #define MIPI_DSI_INT_MSK0_mask_dphy_errors_4_SHIFT (20U) /*! mask_dphy_errors_4 - Mask for dphy_errors_4 */ #define MIPI_DSI_INT_MSK0_mask_dphy_errors_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_mask_dphy_errors_4_SHIFT)) & MIPI_DSI_INT_MSK0_mask_dphy_errors_4_MASK) #define MIPI_DSI_INT_MSK0_reserved_31_21_MASK (0xFFE00000U) #define MIPI_DSI_INT_MSK0_reserved_31_21_SHIFT (21U) /*! reserved_31_21 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK0_reserved_31_21(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK0_reserved_31_21_SHIFT)) & MIPI_DSI_INT_MSK0_reserved_31_21_MASK) /*! @} */ /*! @name INT_MSK1 - INT_ST1 mask */ /*! @{ */ #define MIPI_DSI_INT_MSK1_mask_to_hs_tx_MASK (0x1U) #define MIPI_DSI_INT_MSK1_mask_to_hs_tx_SHIFT (0U) /*! mask_to_hs_tx - Mask for to_hs_tx */ #define MIPI_DSI_INT_MSK1_mask_to_hs_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_to_hs_tx_SHIFT)) & MIPI_DSI_INT_MSK1_mask_to_hs_tx_MASK) #define MIPI_DSI_INT_MSK1_mask_to_lp_rx_MASK (0x2U) #define MIPI_DSI_INT_MSK1_mask_to_lp_rx_SHIFT (1U) /*! mask_to_lp_rx - Mask for to_lp_rx */ #define MIPI_DSI_INT_MSK1_mask_to_lp_rx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_to_lp_rx_SHIFT)) & MIPI_DSI_INT_MSK1_mask_to_lp_rx_MASK) #define MIPI_DSI_INT_MSK1_mask_ecc_single_err_MASK (0x4U) #define MIPI_DSI_INT_MSK1_mask_ecc_single_err_SHIFT (2U) /*! mask_ecc_single_err - Mask for ecc_single_err */ #define MIPI_DSI_INT_MSK1_mask_ecc_single_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_ecc_single_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_ecc_single_err_MASK) #define MIPI_DSI_INT_MSK1_mask_ecc_multpl_err_MASK (0x8U) #define MIPI_DSI_INT_MSK1_mask_ecc_multpl_err_SHIFT (3U) /*! mask_ecc_multpl_err - Mask for ecc_multpl_err */ #define MIPI_DSI_INT_MSK1_mask_ecc_multpl_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_ecc_multpl_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_ecc_multpl_err_MASK) #define MIPI_DSI_INT_MSK1_mask_crc_err_MASK (0x10U) #define MIPI_DSI_INT_MSK1_mask_crc_err_SHIFT (4U) /*! mask_crc_err - Mask for crc_err */ #define MIPI_DSI_INT_MSK1_mask_crc_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_crc_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_crc_err_MASK) #define MIPI_DSI_INT_MSK1_mask_pkt_size_err_MASK (0x20U) #define MIPI_DSI_INT_MSK1_mask_pkt_size_err_SHIFT (5U) /*! mask_pkt_size_err - Mask for pkt_size_err */ #define MIPI_DSI_INT_MSK1_mask_pkt_size_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_pkt_size_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_pkt_size_err_MASK) #define MIPI_DSI_INT_MSK1_mask_eopt_err_MASK (0x40U) #define MIPI_DSI_INT_MSK1_mask_eopt_err_SHIFT (6U) /*! mask_eopt_err - Mask for eopt_err */ #define MIPI_DSI_INT_MSK1_mask_eopt_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_eopt_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_eopt_err_MASK) #define MIPI_DSI_INT_MSK1_mask_dpi_pld_wr_err_MASK (0x80U) #define MIPI_DSI_INT_MSK1_mask_dpi_pld_wr_err_SHIFT (7U) /*! mask_dpi_pld_wr_err - Mask for dpi_pld_wr_err */ #define MIPI_DSI_INT_MSK1_mask_dpi_pld_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_dpi_pld_wr_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_dpi_pld_wr_err_MASK) #define MIPI_DSI_INT_MSK1_mask_gen_cmd_wr_err_MASK (0x100U) #define MIPI_DSI_INT_MSK1_mask_gen_cmd_wr_err_SHIFT (8U) /*! mask_gen_cmd_wr_err - Mask for gen_cmd_wr_err */ #define MIPI_DSI_INT_MSK1_mask_gen_cmd_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_gen_cmd_wr_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_gen_cmd_wr_err_MASK) #define MIPI_DSI_INT_MSK1_mask_gen_pld_wr_err_MASK (0x200U) #define MIPI_DSI_INT_MSK1_mask_gen_pld_wr_err_SHIFT (9U) /*! mask_gen_pld_wr_err - Mask for gen_pld_wr_err */ #define MIPI_DSI_INT_MSK1_mask_gen_pld_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_gen_pld_wr_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_gen_pld_wr_err_MASK) #define MIPI_DSI_INT_MSK1_mask_gen_pld_send_err_MASK (0x400U) #define MIPI_DSI_INT_MSK1_mask_gen_pld_send_err_SHIFT (10U) /*! mask_gen_pld_send_err - Mask for gen_pld_send_err */ #define MIPI_DSI_INT_MSK1_mask_gen_pld_send_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_gen_pld_send_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_gen_pld_send_err_MASK) #define MIPI_DSI_INT_MSK1_mask_gen_pld_rd_err_MASK (0x800U) #define MIPI_DSI_INT_MSK1_mask_gen_pld_rd_err_SHIFT (11U) /*! mask_gen_pld_rd_err - Mask for gen_pld_rd_err */ #define MIPI_DSI_INT_MSK1_mask_gen_pld_rd_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_gen_pld_rd_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_gen_pld_rd_err_MASK) #define MIPI_DSI_INT_MSK1_mask_gen_pld_recev_err_MASK (0x1000U) #define MIPI_DSI_INT_MSK1_mask_gen_pld_recev_err_SHIFT (12U) /*! mask_gen_pld_recev_err - Mask for gen_pld_recev_err */ #define MIPI_DSI_INT_MSK1_mask_gen_pld_recev_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_gen_pld_recev_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_gen_pld_recev_err_MASK) #define MIPI_DSI_INT_MSK1_reserved_13_MASK (0x2000U) #define MIPI_DSI_INT_MSK1_reserved_13_SHIFT (13U) /*! reserved_13 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK1_reserved_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_reserved_13_SHIFT)) & MIPI_DSI_INT_MSK1_reserved_13_MASK) #define MIPI_DSI_INT_MSK1_reserved_14_MASK (0x4000U) #define MIPI_DSI_INT_MSK1_reserved_14_SHIFT (14U) /*! reserved_14 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK1_reserved_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_reserved_14_SHIFT)) & MIPI_DSI_INT_MSK1_reserved_14_MASK) #define MIPI_DSI_INT_MSK1_reserved_15_MASK (0x8000U) #define MIPI_DSI_INT_MSK1_reserved_15_SHIFT (15U) /*! reserved_15 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK1_reserved_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_reserved_15_SHIFT)) & MIPI_DSI_INT_MSK1_reserved_15_MASK) #define MIPI_DSI_INT_MSK1_reserved_16_MASK (0x10000U) #define MIPI_DSI_INT_MSK1_reserved_16_SHIFT (16U) /*! reserved_16 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK1_reserved_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_reserved_16_SHIFT)) & MIPI_DSI_INT_MSK1_reserved_16_MASK) #define MIPI_DSI_INT_MSK1_reserved_17_MASK (0x20000U) #define MIPI_DSI_INT_MSK1_reserved_17_SHIFT (17U) /*! reserved_17 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK1_reserved_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_reserved_17_SHIFT)) & MIPI_DSI_INT_MSK1_reserved_17_MASK) #define MIPI_DSI_INT_MSK1_reserved_18_MASK (0x40000U) #define MIPI_DSI_INT_MSK1_reserved_18_SHIFT (18U) /*! reserved_18 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK1_reserved_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_reserved_18_SHIFT)) & MIPI_DSI_INT_MSK1_reserved_18_MASK) #define MIPI_DSI_INT_MSK1_mask_dpi_buff_pld_under_MASK (0x80000U) #define MIPI_DSI_INT_MSK1_mask_dpi_buff_pld_under_SHIFT (19U) /*! mask_dpi_buff_pld_under - Mask for dpi_buff_pld_under */ #define MIPI_DSI_INT_MSK1_mask_dpi_buff_pld_under(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_dpi_buff_pld_under_SHIFT)) & MIPI_DSI_INT_MSK1_mask_dpi_buff_pld_under_MASK) #define MIPI_DSI_INT_MSK1_mask_tear_request_err_MASK (0x100000U) #define MIPI_DSI_INT_MSK1_mask_tear_request_err_SHIFT (20U) /*! mask_tear_request_err - Mask for tear_request_err */ #define MIPI_DSI_INT_MSK1_mask_tear_request_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_mask_tear_request_err_SHIFT)) & MIPI_DSI_INT_MSK1_mask_tear_request_err_MASK) #define MIPI_DSI_INT_MSK1_reserved_31_21_MASK (0xFFE00000U) #define MIPI_DSI_INT_MSK1_reserved_31_21_SHIFT (21U) /*! reserved_31_21 - Reserved and read as zero */ #define MIPI_DSI_INT_MSK1_reserved_31_21(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_MSK1_reserved_31_21_SHIFT)) & MIPI_DSI_INT_MSK1_reserved_31_21_MASK) /*! @} */ /*! @name PHY_CAL - D-PHY skew calibration */ /*! @{ */ #define MIPI_DSI_PHY_CAL_txskewcalhs_MASK (0x1U) #define MIPI_DSI_PHY_CAL_txskewcalhs_SHIFT (0U) /*! txskewcalhs - High-speed skew calibration is started when txskewcalhs is set high (assuming that PHY is in Stop state) */ #define MIPI_DSI_PHY_CAL_txskewcalhs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_CAL_txskewcalhs_SHIFT)) & MIPI_DSI_PHY_CAL_txskewcalhs_MASK) #define MIPI_DSI_PHY_CAL_reserved_31_1_MASK (0xFFFFFFFEU) #define MIPI_DSI_PHY_CAL_reserved_31_1_SHIFT (1U) /*! reserved_31_1 - Reserved and read as zero */ #define MIPI_DSI_PHY_CAL_reserved_31_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_CAL_reserved_31_1_SHIFT)) & MIPI_DSI_PHY_CAL_reserved_31_1_MASK) /*! @} */ /*! @name INT_FORCE0 - Force INT_ST0 */ /*! @{ */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_0_MASK (0x1U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_0_SHIFT (0U) /*! force_ack_with_err_0 - Force ack_with_err_0 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_0_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_0_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_1_MASK (0x2U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_1_SHIFT (1U) /*! force_ack_with_err_1 - Force ack_with_err_1 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_1_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_1_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_2_MASK (0x4U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_2_SHIFT (2U) /*! force_ack_with_err_2 - Force ack_with_err_2 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_2_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_2_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_3_MASK (0x8U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_3_SHIFT (3U) /*! force_ack_with_err_3 - Force ack_with_err_3 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_3_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_3_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_4_MASK (0x10U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_4_SHIFT (4U) /*! force_ack_with_err_4 - Force ack_with_err_4 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_4_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_4_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_5_MASK (0x20U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_5_SHIFT (5U) /*! force_ack_with_err_5 - Force ack_with_err_5 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_5(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_5_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_5_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_6_MASK (0x40U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_6_SHIFT (6U) /*! force_ack_with_err_6 - Force ack_with_err_6 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_6_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_6_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_7_MASK (0x80U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_7_SHIFT (7U) /*! force_ack_with_err_7 - Force ack_with_err_7 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_7(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_7_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_7_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_8_MASK (0x100U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_8_SHIFT (8U) /*! force_ack_with_err_8 - Force ack_with_err_8 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_8_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_8_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_9_MASK (0x200U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_9_SHIFT (9U) /*! force_ack_with_err_9 - Force ack_with_err_9 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_9(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_9_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_9_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_10_MASK (0x400U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_10_SHIFT (10U) /*! force_ack_with_err_10 - Force ack_with_err_10 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_10_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_10_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_11_MASK (0x800U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_11_SHIFT (11U) /*! force_ack_with_err_11 - Force ack_with_err_11 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_11(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_11_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_11_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_12_MASK (0x1000U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_12_SHIFT (12U) /*! force_ack_with_err_12 - Force ack_with_err_12 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_12_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_12_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_13_MASK (0x2000U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_13_SHIFT (13U) /*! force_ack_with_err_13 - Force ack_with_err_13 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_13_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_13_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_14_MASK (0x4000U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_14_SHIFT (14U) /*! force_ack_with_err_14 - Force ack_with_err_14 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_14_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_14_MASK) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_15_MASK (0x8000U) #define MIPI_DSI_INT_FORCE0_force_ack_with_err_15_SHIFT (15U) /*! force_ack_with_err_15 - Force ack_with_err_15 */ #define MIPI_DSI_INT_FORCE0_force_ack_with_err_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_ack_with_err_15_SHIFT)) & MIPI_DSI_INT_FORCE0_force_ack_with_err_15_MASK) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_0_MASK (0x10000U) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_0_SHIFT (16U) /*! force_dphy_errors_0 - Force dphy_errors_0 */ #define MIPI_DSI_INT_FORCE0_force_dphy_errors_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_dphy_errors_0_SHIFT)) & MIPI_DSI_INT_FORCE0_force_dphy_errors_0_MASK) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_1_MASK (0x20000U) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_1_SHIFT (17U) /*! force_dphy_errors_1 - Force dphy_errors_1 */ #define MIPI_DSI_INT_FORCE0_force_dphy_errors_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_dphy_errors_1_SHIFT)) & MIPI_DSI_INT_FORCE0_force_dphy_errors_1_MASK) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_2_MASK (0x40000U) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_2_SHIFT (18U) /*! force_dphy_errors_2 - Force dphy_errors_2 */ #define MIPI_DSI_INT_FORCE0_force_dphy_errors_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_dphy_errors_2_SHIFT)) & MIPI_DSI_INT_FORCE0_force_dphy_errors_2_MASK) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_3_MASK (0x80000U) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_3_SHIFT (19U) /*! force_dphy_errors_3 - Force dphy_errors_3 */ #define MIPI_DSI_INT_FORCE0_force_dphy_errors_3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_dphy_errors_3_SHIFT)) & MIPI_DSI_INT_FORCE0_force_dphy_errors_3_MASK) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_4_MASK (0x100000U) #define MIPI_DSI_INT_FORCE0_force_dphy_errors_4_SHIFT (20U) /*! force_dphy_errors_4 - Force dphy_errors_4 */ #define MIPI_DSI_INT_FORCE0_force_dphy_errors_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_force_dphy_errors_4_SHIFT)) & MIPI_DSI_INT_FORCE0_force_dphy_errors_4_MASK) #define MIPI_DSI_INT_FORCE0_reserved_31_21_MASK (0xFFE00000U) #define MIPI_DSI_INT_FORCE0_reserved_31_21_SHIFT (21U) /*! reserved_31_21 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE0_reserved_31_21(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE0_reserved_31_21_SHIFT)) & MIPI_DSI_INT_FORCE0_reserved_31_21_MASK) /*! @} */ /*! @name INT_FORCE1 - Force INT_ST1 */ /*! @{ */ #define MIPI_DSI_INT_FORCE1_force_to_hs_tx_MASK (0x1U) #define MIPI_DSI_INT_FORCE1_force_to_hs_tx_SHIFT (0U) /*! force_to_hs_tx - Force to_hs_tx */ #define MIPI_DSI_INT_FORCE1_force_to_hs_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_to_hs_tx_SHIFT)) & MIPI_DSI_INT_FORCE1_force_to_hs_tx_MASK) #define MIPI_DSI_INT_FORCE1_force_to_lp_rx_MASK (0x2U) #define MIPI_DSI_INT_FORCE1_force_to_lp_rx_SHIFT (1U) /*! force_to_lp_rx - Force to_lp_rx */ #define MIPI_DSI_INT_FORCE1_force_to_lp_rx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_to_lp_rx_SHIFT)) & MIPI_DSI_INT_FORCE1_force_to_lp_rx_MASK) #define MIPI_DSI_INT_FORCE1_force_ecc_single_err_MASK (0x4U) #define MIPI_DSI_INT_FORCE1_force_ecc_single_err_SHIFT (2U) /*! force_ecc_single_err - Force ecc_single_err */ #define MIPI_DSI_INT_FORCE1_force_ecc_single_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_ecc_single_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_ecc_single_err_MASK) #define MIPI_DSI_INT_FORCE1_force_ecc_multpl_err_MASK (0x8U) #define MIPI_DSI_INT_FORCE1_force_ecc_multpl_err_SHIFT (3U) /*! force_ecc_multpl_err - Force ecc_multpl_err */ #define MIPI_DSI_INT_FORCE1_force_ecc_multpl_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_ecc_multpl_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_ecc_multpl_err_MASK) #define MIPI_DSI_INT_FORCE1_force_crc_err_MASK (0x10U) #define MIPI_DSI_INT_FORCE1_force_crc_err_SHIFT (4U) /*! force_crc_err - Force crc_err */ #define MIPI_DSI_INT_FORCE1_force_crc_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_crc_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_crc_err_MASK) #define MIPI_DSI_INT_FORCE1_force_pkt_size_err_MASK (0x20U) #define MIPI_DSI_INT_FORCE1_force_pkt_size_err_SHIFT (5U) /*! force_pkt_size_err - Force pkt_size_err */ #define MIPI_DSI_INT_FORCE1_force_pkt_size_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_pkt_size_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_pkt_size_err_MASK) #define MIPI_DSI_INT_FORCE1_force_eopt_err_MASK (0x40U) #define MIPI_DSI_INT_FORCE1_force_eopt_err_SHIFT (6U) /*! force_eopt_err - Force eopt_err */ #define MIPI_DSI_INT_FORCE1_force_eopt_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_eopt_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_eopt_err_MASK) #define MIPI_DSI_INT_FORCE1_force_dpi_pld_wr_err_MASK (0x80U) #define MIPI_DSI_INT_FORCE1_force_dpi_pld_wr_err_SHIFT (7U) /*! force_dpi_pld_wr_err - Force dpi_pld_wr_err */ #define MIPI_DSI_INT_FORCE1_force_dpi_pld_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_dpi_pld_wr_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_dpi_pld_wr_err_MASK) #define MIPI_DSI_INT_FORCE1_force_gen_cmd_wr_err_MASK (0x100U) #define MIPI_DSI_INT_FORCE1_force_gen_cmd_wr_err_SHIFT (8U) /*! force_gen_cmd_wr_err - Force gen_cmd_wr_err */ #define MIPI_DSI_INT_FORCE1_force_gen_cmd_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_gen_cmd_wr_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_gen_cmd_wr_err_MASK) #define MIPI_DSI_INT_FORCE1_force_gen_pld_wr_err_MASK (0x200U) #define MIPI_DSI_INT_FORCE1_force_gen_pld_wr_err_SHIFT (9U) /*! force_gen_pld_wr_err - Force gen_pld_wr_err */ #define MIPI_DSI_INT_FORCE1_force_gen_pld_wr_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_gen_pld_wr_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_gen_pld_wr_err_MASK) #define MIPI_DSI_INT_FORCE1_force_gen_pld_send_err_MASK (0x400U) #define MIPI_DSI_INT_FORCE1_force_gen_pld_send_err_SHIFT (10U) /*! force_gen_pld_send_err - Force gen_pld_send_err */ #define MIPI_DSI_INT_FORCE1_force_gen_pld_send_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_gen_pld_send_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_gen_pld_send_err_MASK) #define MIPI_DSI_INT_FORCE1_force_gen_pld_rd_err_MASK (0x800U) #define MIPI_DSI_INT_FORCE1_force_gen_pld_rd_err_SHIFT (11U) /*! force_gen_pld_rd_err - Force gen_pld_rd_err */ #define MIPI_DSI_INT_FORCE1_force_gen_pld_rd_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_gen_pld_rd_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_gen_pld_rd_err_MASK) #define MIPI_DSI_INT_FORCE1_force_gen_pld_recev_err_MASK (0x1000U) #define MIPI_DSI_INT_FORCE1_force_gen_pld_recev_err_SHIFT (12U) /*! force_gen_pld_recev_err - Force gen_pld_recev_err */ #define MIPI_DSI_INT_FORCE1_force_gen_pld_recev_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_gen_pld_recev_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_gen_pld_recev_err_MASK) #define MIPI_DSI_INT_FORCE1_reserved_13_MASK (0x2000U) #define MIPI_DSI_INT_FORCE1_reserved_13_SHIFT (13U) /*! reserved_13 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE1_reserved_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_reserved_13_SHIFT)) & MIPI_DSI_INT_FORCE1_reserved_13_MASK) #define MIPI_DSI_INT_FORCE1_reserved_14_MASK (0x4000U) #define MIPI_DSI_INT_FORCE1_reserved_14_SHIFT (14U) /*! reserved_14 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE1_reserved_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_reserved_14_SHIFT)) & MIPI_DSI_INT_FORCE1_reserved_14_MASK) #define MIPI_DSI_INT_FORCE1_reserved_15_MASK (0x8000U) #define MIPI_DSI_INT_FORCE1_reserved_15_SHIFT (15U) /*! reserved_15 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE1_reserved_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_reserved_15_SHIFT)) & MIPI_DSI_INT_FORCE1_reserved_15_MASK) #define MIPI_DSI_INT_FORCE1_reserved_16_MASK (0x10000U) #define MIPI_DSI_INT_FORCE1_reserved_16_SHIFT (16U) /*! reserved_16 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE1_reserved_16(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_reserved_16_SHIFT)) & MIPI_DSI_INT_FORCE1_reserved_16_MASK) #define MIPI_DSI_INT_FORCE1_reserved_17_MASK (0x20000U) #define MIPI_DSI_INT_FORCE1_reserved_17_SHIFT (17U) /*! reserved_17 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE1_reserved_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_reserved_17_SHIFT)) & MIPI_DSI_INT_FORCE1_reserved_17_MASK) #define MIPI_DSI_INT_FORCE1_reserved_18_MASK (0x40000U) #define MIPI_DSI_INT_FORCE1_reserved_18_SHIFT (18U) /*! reserved_18 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE1_reserved_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_reserved_18_SHIFT)) & MIPI_DSI_INT_FORCE1_reserved_18_MASK) #define MIPI_DSI_INT_FORCE1_force_dpi_buff_pld_under_MASK (0x80000U) #define MIPI_DSI_INT_FORCE1_force_dpi_buff_pld_under_SHIFT (19U) /*! force_dpi_buff_pld_under - Force for dpi_buff_pld_under */ #define MIPI_DSI_INT_FORCE1_force_dpi_buff_pld_under(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_dpi_buff_pld_under_SHIFT)) & MIPI_DSI_INT_FORCE1_force_dpi_buff_pld_under_MASK) #define MIPI_DSI_INT_FORCE1_force_tear_request_err_MASK (0x100000U) #define MIPI_DSI_INT_FORCE1_force_tear_request_err_SHIFT (20U) /*! force_tear_request_err - Force for tear_request_err */ #define MIPI_DSI_INT_FORCE1_force_tear_request_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_force_tear_request_err_SHIFT)) & MIPI_DSI_INT_FORCE1_force_tear_request_err_MASK) #define MIPI_DSI_INT_FORCE1_reserved_31_21_MASK (0xFFE00000U) #define MIPI_DSI_INT_FORCE1_reserved_31_21_SHIFT (21U) /*! reserved_31_21 - Reserved and read as zero */ #define MIPI_DSI_INT_FORCE1_reserved_31_21(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_INT_FORCE1_reserved_31_21_SHIFT)) & MIPI_DSI_INT_FORCE1_reserved_31_21_MASK) /*! @} */ /*! @name AUTO_ULPS_MODE - Automatic ULPS control */ /*! @{ */ #define MIPI_DSI_AUTO_ULPS_MODE_auto_ulps_MASK (0x1U) #define MIPI_DSI_AUTO_ULPS_MODE_auto_ulps_SHIFT (0U) /*! auto_ulps - This bit enables the automatic mechanism to enter and exit ULPS */ #define MIPI_DSI_AUTO_ULPS_MODE_auto_ulps(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_MODE_auto_ulps_SHIFT)) & MIPI_DSI_AUTO_ULPS_MODE_auto_ulps_MASK) #define MIPI_DSI_AUTO_ULPS_MODE_reserved_15_1_MASK (0xFFFEU) #define MIPI_DSI_AUTO_ULPS_MODE_reserved_15_1_SHIFT (1U) /*! reserved_15_1 - Reserved and read as zero */ #define MIPI_DSI_AUTO_ULPS_MODE_reserved_15_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_MODE_reserved_15_1_SHIFT)) & MIPI_DSI_AUTO_ULPS_MODE_reserved_15_1_MASK) #define MIPI_DSI_AUTO_ULPS_MODE_pll_off_ulps_MASK (0x10000U) #define MIPI_DSI_AUTO_ULPS_MODE_pll_off_ulps_SHIFT (16U) /*! pll_off_ulps - Turn off the D-PHY PLL during ULPS */ #define MIPI_DSI_AUTO_ULPS_MODE_pll_off_ulps(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_MODE_pll_off_ulps_SHIFT)) & MIPI_DSI_AUTO_ULPS_MODE_pll_off_ulps_MASK) #define MIPI_DSI_AUTO_ULPS_MODE_pre_pll_off_req_MASK (0x20000U) #define MIPI_DSI_AUTO_ULPS_MODE_pre_pll_off_req_SHIFT (17U) /*! pre_pll_off_req - When pll_off_ulps is active, allows to turn off PLL before the request to enter in ULPS */ #define MIPI_DSI_AUTO_ULPS_MODE_pre_pll_off_req(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_MODE_pre_pll_off_req_SHIFT)) & MIPI_DSI_AUTO_ULPS_MODE_pre_pll_off_req_MASK) #define MIPI_DSI_AUTO_ULPS_MODE_reserved_31_18_MASK (0xFFFC0000U) #define MIPI_DSI_AUTO_ULPS_MODE_reserved_31_18_SHIFT (18U) /*! reserved_31_18 - Reserved and read as zero */ #define MIPI_DSI_AUTO_ULPS_MODE_reserved_31_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_MODE_reserved_31_18_SHIFT)) & MIPI_DSI_AUTO_ULPS_MODE_reserved_31_18_MASK) /*! @} */ /*! @name AUTO_ULPS_ENTRY_DELAY - ULPS transition delay */ /*! @{ */ #define MIPI_DSI_AUTO_ULPS_ENTRY_DELAY_ulps_entry_delay_MASK (0xFFFFFFFFU) #define MIPI_DSI_AUTO_ULPS_ENTRY_DELAY_ulps_entry_delay_SHIFT (0U) /*! ulps_entry_delay - Configures the delay (in lanebyteclk) to wait before entering ULPS */ #define MIPI_DSI_AUTO_ULPS_ENTRY_DELAY_ulps_entry_delay(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_ENTRY_DELAY_ulps_entry_delay_SHIFT)) & MIPI_DSI_AUTO_ULPS_ENTRY_DELAY_ulps_entry_delay_MASK) /*! @} */ /*! @name AUTO_ULPS_WAKEUP_TIME - D-PHY wakeup time */ /*! @{ */ #define MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_clk_div_MASK (0xFFFFU) #define MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_clk_div_SHIFT (0U) /*! twakeup_clk_div - Twakeup clock divider */ #define MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_clk_div(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_clk_div_SHIFT)) & MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_clk_div_MASK) #define MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_cnt_MASK (0xFFFF0000U) #define MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_cnt_SHIFT (16U) /*! twakeup_cnt - Twakeup counter */ #define MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_cnt(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_cnt_SHIFT)) & MIPI_DSI_AUTO_ULPS_WAKEUP_TIME_twakeup_cnt_MASK) /*! @} */ /*! @name DSC_PARAMETER - Display Stream Compression */ /*! @{ */ #define MIPI_DSI_DSC_PARAMETER_compression_mode_MASK (0x1U) #define MIPI_DSI_DSC_PARAMETER_compression_mode_SHIFT (0U) /*! compression_mode - When set to 1, this bit enables the compression mode */ #define MIPI_DSI_DSC_PARAMETER_compression_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSC_PARAMETER_compression_mode_SHIFT)) & MIPI_DSI_DSC_PARAMETER_compression_mode_MASK) #define MIPI_DSI_DSC_PARAMETER_reserved_7_1_MASK (0xFEU) #define MIPI_DSI_DSC_PARAMETER_reserved_7_1_SHIFT (1U) /*! reserved_7_1 - Reserved and read as zero */ #define MIPI_DSI_DSC_PARAMETER_reserved_7_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSC_PARAMETER_reserved_7_1_SHIFT)) & MIPI_DSI_DSC_PARAMETER_reserved_7_1_MASK) #define MIPI_DSI_DSC_PARAMETER_compress_algo_MASK (0x300U) #define MIPI_DSI_DSC_PARAMETER_compress_algo_SHIFT (8U) /*! compress_algo - This field indicates the algorithm identifier: * 0b00..VESA DSC Standard 1.1 * 0b01..reserved, not used * 0b10..reserved, not used * 0b11..vendor-specific algorithm */ #define MIPI_DSI_DSC_PARAMETER_compress_algo(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSC_PARAMETER_compress_algo_SHIFT)) & MIPI_DSI_DSC_PARAMETER_compress_algo_MASK) #define MIPI_DSI_DSC_PARAMETER_reserved_15_10_MASK (0xFC00U) #define MIPI_DSI_DSC_PARAMETER_reserved_15_10_SHIFT (10U) /*! reserved_15_10 - Reserved and read as zero */ #define MIPI_DSI_DSC_PARAMETER_reserved_15_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSC_PARAMETER_reserved_15_10_SHIFT)) & MIPI_DSI_DSC_PARAMETER_reserved_15_10_MASK) #define MIPI_DSI_DSC_PARAMETER_pps_sel_MASK (0x30000U) #define MIPI_DSI_DSC_PARAMETER_pps_sel_SHIFT (16U) /*! pps_sel - This field indicates the PPS selector: * 0b00..PPS Table 1 * 0b01..PPS Table 2 * 0b10..PPS Table 3 * 0b11..PPS Table 4 */ #define MIPI_DSI_DSC_PARAMETER_pps_sel(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSC_PARAMETER_pps_sel_SHIFT)) & MIPI_DSI_DSC_PARAMETER_pps_sel_MASK) #define MIPI_DSI_DSC_PARAMETER_reserved_31_18_MASK (0xFFFC0000U) #define MIPI_DSI_DSC_PARAMETER_reserved_31_18_SHIFT (18U) /*! reserved_31_18 - Reserved and read as zero */ #define MIPI_DSI_DSC_PARAMETER_reserved_31_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSC_PARAMETER_reserved_31_18_SHIFT)) & MIPI_DSI_DSC_PARAMETER_reserved_31_18_MASK) /*! @} */ /*! @name PHY_TMR_RD_CFG - PHY timings */ /*! @{ */ #define MIPI_DSI_PHY_TMR_RD_CFG_max_rd_time_MASK (0x7FFFU) #define MIPI_DSI_PHY_TMR_RD_CFG_max_rd_time_SHIFT (0U) /*! max_rd_time - This field configures the maximum time required to perform a read command in lane byte clock cycles */ #define MIPI_DSI_PHY_TMR_RD_CFG_max_rd_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_RD_CFG_max_rd_time_SHIFT)) & MIPI_DSI_PHY_TMR_RD_CFG_max_rd_time_MASK) #define MIPI_DSI_PHY_TMR_RD_CFG_reserved_31_15_MASK (0xFFFF8000U) #define MIPI_DSI_PHY_TMR_RD_CFG_reserved_31_15_SHIFT (15U) /*! reserved_31_15 - Reserved and read as zero */ #define MIPI_DSI_PHY_TMR_RD_CFG_reserved_31_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_PHY_TMR_RD_CFG_reserved_31_15_SHIFT)) & MIPI_DSI_PHY_TMR_RD_CFG_reserved_31_15_MASK) /*! @} */ /*! @name AUTO_ULPS_MIN_TIME - PHY Timings - Transition between ulpsactivenot and ulpsexitreq */ /*! @{ */ #define MIPI_DSI_AUTO_ULPS_MIN_TIME_ulps_min_time_MASK (0xFFFU) #define MIPI_DSI_AUTO_ULPS_MIN_TIME_ulps_min_time_SHIFT (0U) /*! ulps_min_time - Configures the minimum time required by PHY between ulpsactivenot and ulpsexitreq for clock and data lane */ #define MIPI_DSI_AUTO_ULPS_MIN_TIME_ulps_min_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_MIN_TIME_ulps_min_time_SHIFT)) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ulps_min_time_MASK) #define MIPI_DSI_AUTO_ULPS_MIN_TIME_reserved_31_12_MASK (0xFFFFF000U) #define MIPI_DSI_AUTO_ULPS_MIN_TIME_reserved_31_12_SHIFT (12U) /*! reserved_31_12 - Reserved and read as zero */ #define MIPI_DSI_AUTO_ULPS_MIN_TIME_reserved_31_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_AUTO_ULPS_MIN_TIME_reserved_31_12_SHIFT)) & MIPI_DSI_AUTO_ULPS_MIN_TIME_reserved_31_12_MASK) /*! @} */ /*! @name VID_SHADOW_CTRL - DPI Shadow Feature */ /*! @{ */ #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_en_MASK (0x1U) #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_en_SHIFT (0U) /*! vid_shadow_en - When set to 1, DPI receives the active configuration from the auxiliary registers */ #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_en_SHIFT)) & MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_en_MASK) #define MIPI_DSI_VID_SHADOW_CTRL_reserved_7_1_MASK (0xFEU) #define MIPI_DSI_VID_SHADOW_CTRL_reserved_7_1_SHIFT (1U) /*! reserved_7_1 - Reserved and read as zero */ #define MIPI_DSI_VID_SHADOW_CTRL_reserved_7_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_SHADOW_CTRL_reserved_7_1_SHIFT)) & MIPI_DSI_VID_SHADOW_CTRL_reserved_7_1_MASK) #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_req_MASK (0x100U) #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_req_SHIFT (8U) /*! vid_shadow_req - When set to 1, this bit request that the dpi registers from regbank are copied to the auxiliary registers */ #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_req(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_req_SHIFT)) & MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_req_MASK) #define MIPI_DSI_VID_SHADOW_CTRL_reserved_15_9_MASK (0xFE00U) #define MIPI_DSI_VID_SHADOW_CTRL_reserved_15_9_SHIFT (9U) /*! reserved_15_9 - Reserved and read as zero */ #define MIPI_DSI_VID_SHADOW_CTRL_reserved_15_9(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_SHADOW_CTRL_reserved_15_9_SHIFT)) & MIPI_DSI_VID_SHADOW_CTRL_reserved_15_9_MASK) #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_pin_req_MASK (0x10000U) #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_pin_req_SHIFT (16U) /*! vid_shadow_pin_req - When set to 1, the video request is done by external pin */ #define MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_pin_req(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_pin_req_SHIFT)) & MIPI_DSI_VID_SHADOW_CTRL_vid_shadow_pin_req_MASK) #define MIPI_DSI_VID_SHADOW_CTRL_reserved_31_17_MASK (0xFFFE0000U) #define MIPI_DSI_VID_SHADOW_CTRL_reserved_31_17_SHIFT (17U) /*! reserved_31_17 - Reserved and read as zero */ #define MIPI_DSI_VID_SHADOW_CTRL_reserved_31_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_SHADOW_CTRL_reserved_31_17_SHIFT)) & MIPI_DSI_VID_SHADOW_CTRL_reserved_31_17_MASK) /*! @} */ /*! @name DPI_VCID_ACT - Actual DPI Virtual Channel ID */ /*! @{ */ #define MIPI_DSI_DPI_VCID_ACT_dpi_vcid_MASK (0x3U) #define MIPI_DSI_DPI_VCID_ACT_dpi_vcid_SHIFT (0U) /*! dpi_vcid - This field specifies the DPI virtual channel id that is indexed to the Video mode packets */ #define MIPI_DSI_DPI_VCID_ACT_dpi_vcid(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_VCID_ACT_dpi_vcid_SHIFT)) & MIPI_DSI_DPI_VCID_ACT_dpi_vcid_MASK) #define MIPI_DSI_DPI_VCID_ACT_reserved_31_2_MASK (0xFFFFFFFCU) #define MIPI_DSI_DPI_VCID_ACT_reserved_31_2_SHIFT (2U) /*! reserved_31_2 - Reserved and read as zero */ #define MIPI_DSI_DPI_VCID_ACT_reserved_31_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_VCID_ACT_reserved_31_2_SHIFT)) & MIPI_DSI_DPI_VCID_ACT_reserved_31_2_MASK) /*! @} */ /*! @name DPI_COLOR_CODING_ACT - Actual DPI Color Coding */ /*! @{ */ #define MIPI_DSI_DPI_COLOR_CODING_ACT_dpi_color_coding_MASK (0xFU) #define MIPI_DSI_DPI_COLOR_CODING_ACT_dpi_color_coding_SHIFT (0U) /*! dpi_color_coding - This field configures the DPI color for Video Mode/eDPI Command Mode coding as follows: * 0b0000..16-bit configuration 1 * 0b0001..16-bit configuration 2 * 0b0010..16-bit configuration 3 * 0b0011..18-bit configuration 1 * 0b0100..18-bit configuration 2 * 0b0101..24-bit * 0b0110..20-bit YCbCr 4:2:2 loosely packed / Reserved for eDPI Command Mode * 0b0111..24-bit YCbCr 4:2:2 / Reserved for eDPI Command Mode * 0b1000..16-bit YCbCr 4:2:2 / Reserved for eDPI Command Mode * 0b1001..30-bit - DSC_ENC 10bit / Reserved for eDPI Command Mode * 0b1010..36-bit / Reserved for eDPI Command Mode * 0b1011..12-bit YCbCr 4:2:0 / Reserved for eDPI Command Mode * 0b1100..DSC24 compressed Data * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define MIPI_DSI_DPI_COLOR_CODING_ACT_dpi_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_ACT_dpi_color_coding_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_ACT_dpi_color_coding_MASK) #define MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_7_4_MASK (0xF0U) #define MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_7_4_SHIFT (4U) /*! reserved_7_4 - Reserved and read as zero */ #define MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_7_4(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_7_4_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_7_4_MASK) #define MIPI_DSI_DPI_COLOR_CODING_ACT_loosely18_en_MASK (0x100U) #define MIPI_DSI_DPI_COLOR_CODING_ACT_loosely18_en_SHIFT (8U) /*! loosely18_en - When 1, this bit activates loosely packed variant to 18-bit configurations */ #define MIPI_DSI_DPI_COLOR_CODING_ACT_loosely18_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_ACT_loosely18_en_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_ACT_loosely18_en_MASK) #define MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_31_9_MASK (0xFFFFFE00U) #define MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_31_9_SHIFT (9U) /*! reserved_31_9 - Reserved and read as zero */ #define MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_31_9(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_31_9_SHIFT)) & MIPI_DSI_DPI_COLOR_CODING_ACT_reserved_31_9_MASK) /*! @} */ /*! @name DPI_LP_CMD_TIM_ACT - Actual DPI Low Power Commands' Timing */ /*! @{ */ #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_invact_lpcmd_time_MASK (0xFFU) #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_invact_lpcmd_time_SHIFT (0U) /*! invact_lpcmd_time - This field is used for the transmission of commands in low-power mode */ #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_invact_lpcmd_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_ACT_invact_lpcmd_time_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_invact_lpcmd_time_MASK) #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_15_8_MASK (0xFF00U) #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_15_8_SHIFT (8U) /*! reserved_15_8 - Reserved and read as zero */ #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_15_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_15_8_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_15_8_MASK) #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_outvact_lpcmd_time_MASK (0xFF0000U) #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_outvact_lpcmd_time_SHIFT (16U) /*! outvact_lpcmd_time - This field is used for the transmission of commands in low-power mode */ #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_outvact_lpcmd_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_ACT_outvact_lpcmd_time_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_outvact_lpcmd_time_MASK) #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_31_24_MASK (0xFF000000U) #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_31_24_SHIFT (24U) /*! reserved_31_24 - Reserved and read as zero */ #define MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_31_24(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_31_24_SHIFT)) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_reserved_31_24_MASK) /*! @} */ /*! @name EDPI_TE_HW_CFG - TE for Hardware operations */ /*! @{ */ #define MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_on_MASK (0x1U) #define MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_on_SHIFT (0U) /*! hw_tear_effect_on - This bit activates Tearing effect by hardware: * 0b0..Tearing effect request is triggered by a set_tear_on or set_tear_scanline * 0b1..Tearing effect request is triggered by the assertion of input pin tear_request. Note that before using * tear_request the tear effect need to be active in DSI host and device. This is accomplished sending * set_tear_on or set_tear_scanline commands according to DSI protocol */ #define MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_on(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_on_SHIFT)) & MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_on_MASK) #define MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_gen_MASK (0x2U) #define MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_gen_SHIFT (1U) /*! hw_tear_effect_gen - When hw_tear_effect = 1 this bit changes tear effect by Hardware priorities: * 0b0..After tearing effect request, tear effect protocol is performed immediately after eDPI data is sent * 0b1..After tearing effect request, tear effect protocol is performed after eDPI data and generic commands are sent */ #define MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_gen(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_gen_SHIFT)) & MIPI_DSI_EDPI_TE_HW_CFG_hw_tear_effect_gen_MASK) #define MIPI_DSI_EDPI_TE_HW_CFG_reserved_3_2_MASK (0xCU) #define MIPI_DSI_EDPI_TE_HW_CFG_reserved_3_2_SHIFT (2U) /*! reserved_3_2 - Reserved and read as zero */ #define MIPI_DSI_EDPI_TE_HW_CFG_reserved_3_2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_TE_HW_CFG_reserved_3_2_SHIFT)) & MIPI_DSI_EDPI_TE_HW_CFG_reserved_3_2_MASK) #define MIPI_DSI_EDPI_TE_HW_CFG_hw_set_scan_line_MASK (0x10U) #define MIPI_DSI_EDPI_TE_HW_CFG_hw_set_scan_line_SHIFT (4U) /*! hw_set_scan_line - When hw_tear_effect_on = 1, this bit configures DCS packet type to be issued by MIPI DSI host to the display module: * 0b0..After tearing effect request, set_tear_on is issued to display module * 0b1..After tearing effect request, set_tear_scan_line issued to display module */ #define MIPI_DSI_EDPI_TE_HW_CFG_hw_set_scan_line(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_TE_HW_CFG_hw_set_scan_line_SHIFT)) & MIPI_DSI_EDPI_TE_HW_CFG_hw_set_scan_line_MASK) #define MIPI_DSI_EDPI_TE_HW_CFG_reserved_15_5_MASK (0xFFE0U) #define MIPI_DSI_EDPI_TE_HW_CFG_reserved_15_5_SHIFT (5U) /*! reserved_15_5 - Reserved and read as zero */ #define MIPI_DSI_EDPI_TE_HW_CFG_reserved_15_5(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_TE_HW_CFG_reserved_15_5_SHIFT)) & MIPI_DSI_EDPI_TE_HW_CFG_reserved_15_5_MASK) #define MIPI_DSI_EDPI_TE_HW_CFG_scan_line_parameter_MASK (0xFFFF0000U) #define MIPI_DSI_EDPI_TE_HW_CFG_scan_line_parameter_SHIFT (16U) /*! scan_line_parameter - When hw_set_scan_line = 1, this bit configures the parameter that describes the Tearing Effect Output Line mode */ #define MIPI_DSI_EDPI_TE_HW_CFG_scan_line_parameter(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_EDPI_TE_HW_CFG_scan_line_parameter_SHIFT)) & MIPI_DSI_EDPI_TE_HW_CFG_scan_line_parameter_MASK) /*! @} */ /*! @name VID_MODE_CFG_ACT - VID_MODE_CFG */ /*! @{ */ #define MIPI_DSI_VID_MODE_CFG_ACT_vid_mode_type_MASK (0x3U) #define MIPI_DSI_VID_MODE_CFG_ACT_vid_mode_type_SHIFT (0U) /*! vid_mode_type - This field specifies the video mode transmission type as follows: * 0b00..Non-burst with sync pulses * 0b01..Non-burst with sync events * 0b10..Burst mode * 0b11..Burst mode */ #define MIPI_DSI_VID_MODE_CFG_ACT_vid_mode_type(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_vid_mode_type_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_vid_mode_type_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vsa_en_MASK (0x4U) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vsa_en_SHIFT (2U) /*! lp_vsa_en - When 1, this bit enables the return to low-power inside the VSA period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vsa_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_lp_vsa_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_lp_vsa_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vbp_en_MASK (0x8U) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vbp_en_SHIFT (3U) /*! lp_vbp_en - When 1, this bit enables the return to low-power inside the VBP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vbp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_lp_vbp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_lp_vbp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vfp_en_MASK (0x10U) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vfp_en_SHIFT (4U) /*! lp_vfp_en - When 1, this bit enables the return to low-power inside the VFP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vfp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_lp_vfp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_lp_vfp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vact_en_MASK (0x20U) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vact_en_SHIFT (5U) /*! lp_vact_en - When 1, this bit enables the return to low-power inside the VACT period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_ACT_lp_vact_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_lp_vact_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_lp_vact_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_hbp_en_MASK (0x40U) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_hbp_en_SHIFT (6U) /*! lp_hbp_en - When 1, this bit enables the return to low-power inside the HBP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_ACT_lp_hbp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_lp_hbp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_lp_hbp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_hfp_en_MASK (0x80U) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_hfp_en_SHIFT (7U) /*! lp_hfp_en - When 1, this bit enables the return to low-power inside the HFP period when timing allows */ #define MIPI_DSI_VID_MODE_CFG_ACT_lp_hfp_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_lp_hfp_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_lp_hfp_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_frame_bta_ack_en_MASK (0x100U) #define MIPI_DSI_VID_MODE_CFG_ACT_frame_bta_ack_en_SHIFT (8U) /*! frame_bta_ack_en - When 1, this bit enables the request for an acknowledge response at the end of a frame */ #define MIPI_DSI_VID_MODE_CFG_ACT_frame_bta_ack_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_frame_bta_ack_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_frame_bta_ack_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_cmd_en_MASK (0x200U) #define MIPI_DSI_VID_MODE_CFG_ACT_lp_cmd_en_SHIFT (9U) /*! lp_cmd_en - When 1, this bit enables the command transmission only in low-power mode */ #define MIPI_DSI_VID_MODE_CFG_ACT_lp_cmd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_lp_cmd_en_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_lp_cmd_en_MASK) #define MIPI_DSI_VID_MODE_CFG_ACT_reserved_31_10_MASK (0xFFFFFC00U) #define MIPI_DSI_VID_MODE_CFG_ACT_reserved_31_10_SHIFT (10U) /*! reserved_31_10 - Reserved and read as zero */ #define MIPI_DSI_VID_MODE_CFG_ACT_reserved_31_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_MODE_CFG_ACT_reserved_31_10_SHIFT)) & MIPI_DSI_VID_MODE_CFG_ACT_reserved_31_10_MASK) /*! @} */ /*! @name VID_PKT_SIZE_ACT - Actual VID_PKT_SIZE */ /*! @{ */ #define MIPI_DSI_VID_PKT_SIZE_ACT_vid_pkt_size_MASK (0x3FFFU) #define MIPI_DSI_VID_PKT_SIZE_ACT_vid_pkt_size_SHIFT (0U) /*! vid_pkt_size - This field specifies the number of pixels in a single video packet */ #define MIPI_DSI_VID_PKT_SIZE_ACT_vid_pkt_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_SIZE_ACT_vid_pkt_size_SHIFT)) & MIPI_DSI_VID_PKT_SIZE_ACT_vid_pkt_size_MASK) #define MIPI_DSI_VID_PKT_SIZE_ACT_reserved_31_14_MASK (0xFFFFC000U) #define MIPI_DSI_VID_PKT_SIZE_ACT_reserved_31_14_SHIFT (14U) /*! reserved_31_14 - Reserved and read as zero */ #define MIPI_DSI_VID_PKT_SIZE_ACT_reserved_31_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_SIZE_ACT_reserved_31_14_SHIFT)) & MIPI_DSI_VID_PKT_SIZE_ACT_reserved_31_14_MASK) /*! @} */ /*! @name VID_NUM_CHUNKS_ACT - Actual VID_NUM_CHUNKS */ /*! @{ */ #define MIPI_DSI_VID_NUM_CHUNKS_ACT_vid_num_chunks_MASK (0x1FFFU) #define MIPI_DSI_VID_NUM_CHUNKS_ACT_vid_num_chunks_SHIFT (0U) /*! vid_num_chunks - This register specifies the number of chunks to be transmitted during a Line * period (a chunk is pair made of a video packet and a null packet) */ #define MIPI_DSI_VID_NUM_CHUNKS_ACT_vid_num_chunks(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NUM_CHUNKS_ACT_vid_num_chunks_SHIFT)) & MIPI_DSI_VID_NUM_CHUNKS_ACT_vid_num_chunks_MASK) #define MIPI_DSI_VID_NUM_CHUNKS_ACT_reserved_31_13_MASK (0xFFFFE000U) #define MIPI_DSI_VID_NUM_CHUNKS_ACT_reserved_31_13_SHIFT (13U) /*! reserved_31_13 - Reserved and read as zero */ #define MIPI_DSI_VID_NUM_CHUNKS_ACT_reserved_31_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NUM_CHUNKS_ACT_reserved_31_13_SHIFT)) & MIPI_DSI_VID_NUM_CHUNKS_ACT_reserved_31_13_MASK) /*! @} */ /*! @name VID_NULL_SIZE_ACT - Actual VID_NULL_SIZE */ /*! @{ */ #define MIPI_DSI_VID_NULL_SIZE_ACT_vid_null_size_MASK (0x1FFFU) #define MIPI_DSI_VID_NULL_SIZE_ACT_vid_null_size_SHIFT (0U) /*! vid_null_size - This register specifies the number of bytes inside a null packet */ #define MIPI_DSI_VID_NULL_SIZE_ACT_vid_null_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NULL_SIZE_ACT_vid_null_size_SHIFT)) & MIPI_DSI_VID_NULL_SIZE_ACT_vid_null_size_MASK) #define MIPI_DSI_VID_NULL_SIZE_ACT_reserved_31_13_MASK (0xFFFFE000U) #define MIPI_DSI_VID_NULL_SIZE_ACT_reserved_31_13_SHIFT (13U) /*! reserved_31_13 - Reserved and read as zero */ #define MIPI_DSI_VID_NULL_SIZE_ACT_reserved_31_13(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_NULL_SIZE_ACT_reserved_31_13_SHIFT)) & MIPI_DSI_VID_NULL_SIZE_ACT_reserved_31_13_MASK) /*! @} */ /*! @name VID_HSA_TIME_ACT - Actual VID_HSA_TIME */ /*! @{ */ #define MIPI_DSI_VID_HSA_TIME_ACT_vid_hsa_time_MASK (0xFFFU) #define MIPI_DSI_VID_HSA_TIME_ACT_vid_hsa_time_SHIFT (0U) /*! vid_hsa_time - This field specifies the Horizontal Synchronism Active period in lane byte clock cycles */ #define MIPI_DSI_VID_HSA_TIME_ACT_vid_hsa_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HSA_TIME_ACT_vid_hsa_time_SHIFT)) & MIPI_DSI_VID_HSA_TIME_ACT_vid_hsa_time_MASK) #define MIPI_DSI_VID_HSA_TIME_ACT_reserved_31_12_MASK (0xFFFFF000U) #define MIPI_DSI_VID_HSA_TIME_ACT_reserved_31_12_SHIFT (12U) /*! reserved_31_12 - Reserved and read as zero */ #define MIPI_DSI_VID_HSA_TIME_ACT_reserved_31_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HSA_TIME_ACT_reserved_31_12_SHIFT)) & MIPI_DSI_VID_HSA_TIME_ACT_reserved_31_12_MASK) /*! @} */ /*! @name VID_HBP_TIME_ACT - Actual VID_HBP_TIME */ /*! @{ */ #define MIPI_DSI_VID_HBP_TIME_ACT_vid_hbp_time_MASK (0xFFFU) #define MIPI_DSI_VID_HBP_TIME_ACT_vid_hbp_time_SHIFT (0U) /*! vid_hbp_time - This field specifies the Horizontal Back Porch period in lane byte clock cycles */ #define MIPI_DSI_VID_HBP_TIME_ACT_vid_hbp_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HBP_TIME_ACT_vid_hbp_time_SHIFT)) & MIPI_DSI_VID_HBP_TIME_ACT_vid_hbp_time_MASK) #define MIPI_DSI_VID_HBP_TIME_ACT_reserved_31_12_MASK (0xFFFFF000U) #define MIPI_DSI_VID_HBP_TIME_ACT_reserved_31_12_SHIFT (12U) /*! reserved_31_12 - Reserved and read as zero */ #define MIPI_DSI_VID_HBP_TIME_ACT_reserved_31_12(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HBP_TIME_ACT_reserved_31_12_SHIFT)) & MIPI_DSI_VID_HBP_TIME_ACT_reserved_31_12_MASK) /*! @} */ /*! @name VID_HLINE_TIME_ACT - Actual VID_HLINE_TIME */ /*! @{ */ #define MIPI_DSI_VID_HLINE_TIME_ACT_vid_hline_time_MASK (0x7FFFU) #define MIPI_DSI_VID_HLINE_TIME_ACT_vid_hline_time_SHIFT (0U) /*! vid_hline_time - This field specifies the size of the total line time (HSA+HBP+HACT+HFP) counted in lane byte clock cycles */ #define MIPI_DSI_VID_HLINE_TIME_ACT_vid_hline_time(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HLINE_TIME_ACT_vid_hline_time_SHIFT)) & MIPI_DSI_VID_HLINE_TIME_ACT_vid_hline_time_MASK) #define MIPI_DSI_VID_HLINE_TIME_ACT_reserved_31_15_MASK (0xFFFF8000U) #define MIPI_DSI_VID_HLINE_TIME_ACT_reserved_31_15_SHIFT (15U) /*! reserved_31_15 - Reserved and read as zero */ #define MIPI_DSI_VID_HLINE_TIME_ACT_reserved_31_15(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_HLINE_TIME_ACT_reserved_31_15_SHIFT)) & MIPI_DSI_VID_HLINE_TIME_ACT_reserved_31_15_MASK) /*! @} */ /*! @name VID_VSA_LINES_ACT - Actual VID_VSA_LINES */ /*! @{ */ #define MIPI_DSI_VID_VSA_LINES_ACT_vsa_lines_MASK (0x3FFU) #define MIPI_DSI_VID_VSA_LINES_ACT_vsa_lines_SHIFT (0U) /*! vsa_lines - This field specifies the Vertical Synchronism Active period measured in number of horizontal lines */ #define MIPI_DSI_VID_VSA_LINES_ACT_vsa_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VSA_LINES_ACT_vsa_lines_SHIFT)) & MIPI_DSI_VID_VSA_LINES_ACT_vsa_lines_MASK) #define MIPI_DSI_VID_VSA_LINES_ACT_reserved_31_10_MASK (0xFFFFFC00U) #define MIPI_DSI_VID_VSA_LINES_ACT_reserved_31_10_SHIFT (10U) /*! reserved_31_10 - Reserved and read as zero */ #define MIPI_DSI_VID_VSA_LINES_ACT_reserved_31_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VSA_LINES_ACT_reserved_31_10_SHIFT)) & MIPI_DSI_VID_VSA_LINES_ACT_reserved_31_10_MASK) /*! @} */ /*! @name VID_VBP_LINES_ACT - VID_VBP_LINES */ /*! @{ */ #define MIPI_DSI_VID_VBP_LINES_ACT_vbp_lines_MASK (0x3FFU) #define MIPI_DSI_VID_VBP_LINES_ACT_vbp_lines_SHIFT (0U) /*! vbp_lines - This field specifies the Vertical Back Porch period measured in number of horizontal lines */ #define MIPI_DSI_VID_VBP_LINES_ACT_vbp_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VBP_LINES_ACT_vbp_lines_SHIFT)) & MIPI_DSI_VID_VBP_LINES_ACT_vbp_lines_MASK) #define MIPI_DSI_VID_VBP_LINES_ACT_reserved_31_10_MASK (0xFFFFFC00U) #define MIPI_DSI_VID_VBP_LINES_ACT_reserved_31_10_SHIFT (10U) /*! reserved_31_10 - Reserved and read as zero */ #define MIPI_DSI_VID_VBP_LINES_ACT_reserved_31_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VBP_LINES_ACT_reserved_31_10_SHIFT)) & MIPI_DSI_VID_VBP_LINES_ACT_reserved_31_10_MASK) /*! @} */ /*! @name VID_VFP_LINES_ACT - Actual VID_VFP_LINES */ /*! @{ */ #define MIPI_DSI_VID_VFP_LINES_ACT_vfp_lines_MASK (0x3FFU) #define MIPI_DSI_VID_VFP_LINES_ACT_vfp_lines_SHIFT (0U) /*! vfp_lines - This field specifies the Vertical Front Porch period measured in number of horizontal lines */ #define MIPI_DSI_VID_VFP_LINES_ACT_vfp_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VFP_LINES_ACT_vfp_lines_SHIFT)) & MIPI_DSI_VID_VFP_LINES_ACT_vfp_lines_MASK) #define MIPI_DSI_VID_VFP_LINES_ACT_reserved_31_10_MASK (0xFFFFFC00U) #define MIPI_DSI_VID_VFP_LINES_ACT_reserved_31_10_SHIFT (10U) /*! reserved_31_10 - Reserved and read as zero */ #define MIPI_DSI_VID_VFP_LINES_ACT_reserved_31_10(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VFP_LINES_ACT_reserved_31_10_SHIFT)) & MIPI_DSI_VID_VFP_LINES_ACT_reserved_31_10_MASK) /*! @} */ /*! @name VID_VACTIVE_LINES_ACT - Actual VID_VACTIVE_LINES */ /*! @{ */ #define MIPI_DSI_VID_VACTIVE_LINES_ACT_v_active_lines_MASK (0x3FFFU) #define MIPI_DSI_VID_VACTIVE_LINES_ACT_v_active_lines_SHIFT (0U) /*! v_active_lines - This field specifies the Vertical Active period measured in number of horizontal lines */ #define MIPI_DSI_VID_VACTIVE_LINES_ACT_v_active_lines(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VACTIVE_LINES_ACT_v_active_lines_SHIFT)) & MIPI_DSI_VID_VACTIVE_LINES_ACT_v_active_lines_MASK) #define MIPI_DSI_VID_VACTIVE_LINES_ACT_reserved_31_14_MASK (0xFFFFC000U) #define MIPI_DSI_VID_VACTIVE_LINES_ACT_reserved_31_14_SHIFT (14U) /*! reserved_31_14 - Reserved and read as zero */ #define MIPI_DSI_VID_VACTIVE_LINES_ACT_reserved_31_14(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_VACTIVE_LINES_ACT_reserved_31_14_SHIFT)) & MIPI_DSI_VID_VACTIVE_LINES_ACT_reserved_31_14_MASK) /*! @} */ /*! @name VID_PKT_STATUS - eDPI and DPI FIFOs status */ /*! @{ */ #define MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_empty_MASK (0x1U) #define MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_empty_SHIFT (0U) /*! dpi_cmd_w_empty - This bit indicates the empty status of write command FIFO for video Mode */ #define MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_empty_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_empty_MASK) #define MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_full_MASK (0x2U) #define MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_full_SHIFT (1U) /*! dpi_cmd_w_full - This bit indicates the full status of write command FIFO for video Mode */ #define MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_full_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_dpi_cmd_w_full_MASK) #define MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_empty_MASK (0x4U) #define MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_empty_SHIFT (2U) /*! dpi_pld_w_empty - This bit indicates the empty status of write payload FIFO for video Mode */ #define MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_empty_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_empty_MASK) #define MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_full_MASK (0x8U) #define MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_full_SHIFT (3U) /*! dpi_pld_w_full - This bit indicates the full status of write payload FIFO for video Mode */ #define MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_full_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_dpi_pld_w_full_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_empty_MASK (0x10U) #define MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_empty_SHIFT (4U) /*! edpi_cmd_w_empty - This bit indicates the empty status of write command FIFO for command Mode */ #define MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_empty_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_empty_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_full_MASK (0x20U) #define MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_full_SHIFT (5U) /*! edpi_cmd_w_full - This bit indicates the full status of write command FIFO for command Mode */ #define MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_full_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_cmd_w_full_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_empty_MASK (0x40U) #define MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_empty_SHIFT (6U) /*! edpi_pld_w_empty - This bit indicates the empty status of write payload FIFO for command Mode */ #define MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_empty_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_empty_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_full_MASK (0x80U) #define MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_full_SHIFT (7U) /*! edpi_pld_w_full - This bit indicates the full status of write payload FIFO for command Mode */ #define MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_full_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_pld_w_full_MASK) #define MIPI_DSI_VID_PKT_STATUS_reserved_15_8_MASK (0xFF00U) #define MIPI_DSI_VID_PKT_STATUS_reserved_15_8_SHIFT (8U) /*! reserved_15_8 - Reserved and read as zero */ #define MIPI_DSI_VID_PKT_STATUS_reserved_15_8(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_reserved_15_8_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_reserved_15_8_MASK) #define MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_empty_MASK (0x10000U) #define MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_empty_SHIFT (16U) /*! dpi_buff_pld_empty - This bit indicates the empty status of the payload internal buffer for video Mode */ #define MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_empty_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_empty_MASK) #define MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_full_MASK (0x20000U) #define MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_full_SHIFT (17U) /*! dpi_buff_pld_full - This bit indicates the full status of the payload internal buffer for video Mode */ #define MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_full_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_dpi_buff_pld_full_MASK) #define MIPI_DSI_VID_PKT_STATUS_reserved_19_18_MASK (0xC0000U) #define MIPI_DSI_VID_PKT_STATUS_reserved_19_18_SHIFT (18U) /*! reserved_19_18 - Reserved and read as zero */ #define MIPI_DSI_VID_PKT_STATUS_reserved_19_18(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_reserved_19_18_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_reserved_19_18_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_empty_MASK (0x100000U) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_empty_SHIFT (20U) /*! edpi_buff_cmd_empty - This bit indicates the empty status of the edpi command internal buffer */ #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_empty_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_empty_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_full_MASK (0x200000U) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_full_SHIFT (21U) /*! edpi_buff_cmd_full - This bit indicates the full status of the edpi command internal buffer */ #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_full_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_buff_cmd_full_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_empty_MASK (0x400000U) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_empty_SHIFT (22U) /*! edpi_buff_pld_empty - This bit indicates the empty status of the edpi payload internal buffer */ #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_empty(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_empty_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_empty_MASK) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_full_MASK (0x800000U) #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_full_SHIFT (23U) /*! edpi_buff_pld_full - This bit indicates the full status of the edpi payload internal buffer */ #define MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_full(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_full_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_edpi_buff_pld_full_MASK) #define MIPI_DSI_VID_PKT_STATUS_reserved_31_24_MASK (0xFF000000U) #define MIPI_DSI_VID_PKT_STATUS_reserved_31_24_SHIFT (24U) /*! reserved_31_24 - Reserved and read as zero */ #define MIPI_DSI_VID_PKT_STATUS_reserved_31_24(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_VID_PKT_STATUS_reserved_31_24_SHIFT)) & MIPI_DSI_VID_PKT_STATUS_reserved_31_24_MASK) /*! @} */ /*! @name SDF_3D_ACT - SDF_3D */ /*! @{ */ #define MIPI_DSI_SDF_3D_ACT_mode_3d_MASK (0x3U) #define MIPI_DSI_SDF_3D_ACT_mode_3d_SHIFT (0U) /*! mode_3d - This field specifies 3D Mode On/Off and Display Orientation: * 0b00..3D Mode Off, 2D Mode On * 0b01..3D Mode On, Portrait Orientation * 0b10..3D Mode On, Landscape Orientation * 0b11..Reserved, not used */ #define MIPI_DSI_SDF_3D_ACT_mode_3d(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_ACT_mode_3d_SHIFT)) & MIPI_DSI_SDF_3D_ACT_mode_3d_MASK) #define MIPI_DSI_SDF_3D_ACT_format_3d_MASK (0xCU) #define MIPI_DSI_SDF_3D_ACT_format_3d_SHIFT (2U) /*! format_3d - This field specifies 3D Image Format: * 0b01..Alternating frames of left and right data * 0b00..Alternating lines of left and right data * 0b10..Alternating pixels of left and right data * 0b11..Reserved, not used */ #define MIPI_DSI_SDF_3D_ACT_format_3d(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_ACT_format_3d_SHIFT)) & MIPI_DSI_SDF_3D_ACT_format_3d_MASK) #define MIPI_DSI_SDF_3D_ACT_second_vsync_MASK (0x10U) #define MIPI_DSI_SDF_3D_ACT_second_vsync_SHIFT (4U) /*! second_vsync - This field specifies whether there is a second VSYNC pulse between Left and Right * Images, when 3D Image Format is Frame-based: * 0b0..No sync pulses between left and right data * 0b1..Sync pulse (HSYNC, VSYNC, blanking) between left and right data */ #define MIPI_DSI_SDF_3D_ACT_second_vsync(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_ACT_second_vsync_SHIFT)) & MIPI_DSI_SDF_3D_ACT_second_vsync_MASK) #define MIPI_DSI_SDF_3D_ACT_right_first_MASK (0x20U) #define MIPI_DSI_SDF_3D_ACT_right_first_SHIFT (5U) /*! right_first - This bit specifies the left/right order: * 0b0..left eye is sent first, then right eye * 0b1..right eye data is sent first, then left eye */ #define MIPI_DSI_SDF_3D_ACT_right_first(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_ACT_right_first_SHIFT)) & MIPI_DSI_SDF_3D_ACT_right_first_MASK) #define MIPI_DSI_SDF_3D_ACT_reserved_15_6_MASK (0xFFC0U) #define MIPI_DSI_SDF_3D_ACT_reserved_15_6_SHIFT (6U) /*! reserved_15_6 - Reserved and read as zero */ #define MIPI_DSI_SDF_3D_ACT_reserved_15_6(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_ACT_reserved_15_6_SHIFT)) & MIPI_DSI_SDF_3D_ACT_reserved_15_6_MASK) #define MIPI_DSI_SDF_3D_ACT_send_3d_cfg_MASK (0x10000U) #define MIPI_DSI_SDF_3D_ACT_send_3d_cfg_SHIFT (16U) /*! send_3d_cfg - When set, causes the next VSS packet to include 3D control payload in every VSS packet */ #define MIPI_DSI_SDF_3D_ACT_send_3d_cfg(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_ACT_send_3d_cfg_SHIFT)) & MIPI_DSI_SDF_3D_ACT_send_3d_cfg_MASK) #define MIPI_DSI_SDF_3D_ACT_reserved_31_17_MASK (0xFFFE0000U) #define MIPI_DSI_SDF_3D_ACT_reserved_31_17_SHIFT (17U) /*! reserved_31_17 - Reserved and read as zero */ #define MIPI_DSI_SDF_3D_ACT_reserved_31_17(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_SDF_3D_ACT_reserved_31_17_SHIFT)) & MIPI_DSI_SDF_3D_ACT_reserved_31_17_MASK) /*! @} */ /*! * @} */ /* end of group MIPI_DSI_Register_Masks */ /* MIPI_DSI - Peripheral instance base addresses */ /** Peripheral MIPI_DSI base address */ #define MIPI_DSI_BASE (0x4ACF0000u) /** Peripheral MIPI_DSI base pointer */ #define MIPI_DSI ((MIPI_DSI_Type *)MIPI_DSI_BASE) /** Array initializer of MIPI_DSI peripheral base addresses */ #define MIPI_DSI_BASE_ADDRS { MIPI_DSI_BASE } /** Array initializer of MIPI_DSI peripheral base pointers */ #define MIPI_DSI_BASE_PTRS { MIPI_DSI } /*! * @} */ /* end of group MIPI_DSI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU0_Peripheral_Access_Layer MMU_TBU0 Peripheral Access Layer * @{ */ /** MMU_TBU0 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU0_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU0_Register_Masks MMU_TBU0 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU0_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU0_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU0_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU0_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU0_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU0_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU0_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU0_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU0_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU0_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU0_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU0_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU0_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU0_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU0_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU0_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU0_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU0_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU0_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU0_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU0_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU0_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU0_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU0_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU0_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU0_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU0_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU0_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU0_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU0_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU0_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU0_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU0_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU0_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU0_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU0_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU0_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU0_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU0_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU0_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU0_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU0_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU0_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU0_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU0_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU0_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU0_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU0_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU0_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU0_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU0_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU0_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU0_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU0_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU0_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU0_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU0_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU0_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU0_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU0_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU0_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU0_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU0_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU0_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU0_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU0_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU0_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU0_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU0_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU0_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU0_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU0_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU0_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU0_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU0_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU0_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU0_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU0_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU0_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU0_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU0_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU0_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU0_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU0_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU0_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU0_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU0_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU0_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU0_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU0_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU0_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU0_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU0_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU0_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU0_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU0_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU0_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU0_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU0_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU0_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU0_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU0_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU0_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU0_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU0_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU0_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU0_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU0_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU0_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU0_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU0_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU0_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU0_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU0_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU0_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU0_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU0_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU0_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU0_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU0_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU0_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU0_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU0_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU0_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU0_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU0_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU0_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU0_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU0_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU0_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU0_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU0_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU0_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU0_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU0_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU0_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU0_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU0_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU0_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU0_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU0_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU0_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU0_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU0_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU0_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU0_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU0_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU0_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU0_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU0_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU0_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU0_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU0_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU0_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU0_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU0_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU0_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU0_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU0_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU0_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU0_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU0_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU0_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU0_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU0_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU0_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU0_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU0_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU0_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU0_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU0_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU0_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU0_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU0_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU0_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU0_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU0_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU0_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU0_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU0_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU0_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU0_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU0_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU0_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU0_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU0_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU0_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU0_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU0_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU0_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU0_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU0_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU0_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU0_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU0_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU0_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU0_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU0_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU0_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU0_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU0_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU0_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU0_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU0_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU0_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU0_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU0_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU0_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU0_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU0_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU0_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU0_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU0_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU0_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU0_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU0_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU0_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU0_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU0_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU0_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU0_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU0_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU0_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU0_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU0_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU0_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU0_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU0_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU0_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU0_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU0_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU0_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU0_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU0_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU0_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU0_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU0_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU0_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU0_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU0_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU0_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU0_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU0_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU0_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU0_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU0_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU0_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU0_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU0_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU0_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU0_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU0_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU0_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU0_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU0_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU0_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU0_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU0_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU0_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU0_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU0_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU0_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU0_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU0_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU0_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX0_MASK) #define MMU_TBU0_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU0_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU0_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX1_MASK) #define MMU_TBU0_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU0_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU0_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX2_MASK) #define MMU_TBU0_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU0_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU0_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX3_MASK) #define MMU_TBU0_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU0_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU0_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX4_MASK) #define MMU_TBU0_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU0_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU0_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX5_MASK) #define MMU_TBU0_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU0_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU0_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX6_MASK) #define MMU_TBU0_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU0_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU0_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX7_MASK) #define MMU_TBU0_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU0_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU0_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX8_MASK) #define MMU_TBU0_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU0_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU0_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX9_MASK) #define MMU_TBU0_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU0_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU0_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX10_MASK) #define MMU_TBU0_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU0_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU0_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX11_MASK) #define MMU_TBU0_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU0_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU0_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU0_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU0_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU0_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU0_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX13_MASK) #define MMU_TBU0_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU0_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU0_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX14_MASK) #define MMU_TBU0_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU0_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU0_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU0_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU0_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU0_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU0_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU0_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU0_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU0_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU0_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU0_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU0_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU0_ITEN_ITEN_MASK (0x1U) #define MMU_TBU0_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU0_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_ITEN_ITEN_SHIFT)) & MMU_TBU0_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU0_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU0_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU0_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU0_ITOP_TBU_ras_cri_MASK) #define MMU_TBU0_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU0_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU0_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU0_ITOP_TBU_ras_eri_MASK) #define MMU_TBU0_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU0_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU0_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU0_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU0_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU0_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU0_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU0_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU0_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU0_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU0_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU0_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU0_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU0_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU0_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU0_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU0_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU0_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU0_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU0_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU0_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU0_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU0_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU0_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU0_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU0_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU0_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU0_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU0_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU0_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU0_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU0_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU0_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU0_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU0_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU0_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU0_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU0_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU0_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU0_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU0_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU0_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU0_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU0_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU0_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU0_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU0_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU0_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU0_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU0_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU0_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU0_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU0_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU0_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU0_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU0_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU0_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU0_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU0_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU0_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU0_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU0_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU0_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU0_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU0_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU0_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU0_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU0_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU0_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU0_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU0_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU0_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU0_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU0_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU0_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU0_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU0_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU0_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU0_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU0_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU0_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU0_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU0_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU0_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU0_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU0_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU0_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU0_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU0_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU0_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU0_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU0_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU0_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU0_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU0_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU0_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU0_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU0_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU0_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU0_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU0_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU0_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU0_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU0_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU0_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU0_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU0_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU0_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU0_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU0_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU0_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU0_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU0_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU0_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU0_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU0_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU0_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU0_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU0_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU0_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU0_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU0_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU0_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU0_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU0_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU0_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU0_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU0_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU0_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU0_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU0_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU0_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU0_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU0_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU0_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU0_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU0_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU0_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU0_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU0_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU0_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU0_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU0_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU0_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU0_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU0_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU0_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU0_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU0_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU0_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU0_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU0_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU0_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU0_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU0_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU0_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU0_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU0_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU0_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU0_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU0_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU0_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU0_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU0_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU0_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU0_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU0_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU0_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU0_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU0_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU0_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU0_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU0_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU0_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU0_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU0_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU0_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU0_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU0_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU0_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU0_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU0_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU0_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU0_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU0_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU0_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU0_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU0_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU0_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU0_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU0_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU0_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU0_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU0_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU0_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU0_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU0_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU0_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU0_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU0_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU0_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU0_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU0_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU0_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU0_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU0_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU0_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU0_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU0_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU0_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU0_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU0_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU0_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU0_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU0_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU0_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU0_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU0_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU0_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU0_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU0_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU0_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU0_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU0_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU0_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU0_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU0_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU0_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU0_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU0_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU0_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU0_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU0_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU0_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU0_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU0_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU0_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU0_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU0_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU0_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU0_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU0_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU0_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU0_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU0_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU0_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU0_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU0_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU0_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU0_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU0_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU0_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU0_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU0_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU0_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU0_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU0_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU0_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU0_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU0_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU0_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU0_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU0_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU0_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU0_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU0_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU0_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU0_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU0_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU0_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU0_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU0_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU0_Register_Masks */ /* MMU_TBU0 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU0 base address */ #define NOC__MMU_TBU_TCU__TBU0_BASE (0x49110000u) /** Peripheral NOC__MMU_TBU_TCU__TBU0 base pointer */ #define NOC__MMU_TBU_TCU__TBU0 ((MMU_TBU0_Type *)NOC__MMU_TBU_TCU__TBU0_BASE) /** Array initializer of MMU_TBU0 peripheral base addresses */ #define MMU_TBU0_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU0_BASE } /** Array initializer of MMU_TBU0 peripheral base pointers */ #define MMU_TBU0_BASE_PTRS { NOC__MMU_TBU_TCU__TBU0 } /*! * @} */ /* end of group MMU_TBU0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU1_Peripheral_Access_Layer MMU_TBU1 Peripheral Access Layer * @{ */ /** MMU_TBU1 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU1_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU1_Register_Masks MMU_TBU1 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU1_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU1_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU1_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU1_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU1_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU1_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU1_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU1_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU1_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU1_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU1_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU1_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU1_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU1_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU1_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU1_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU1_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU1_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU1_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU1_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU1_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU1_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU1_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU1_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU1_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU1_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU1_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU1_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU1_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU1_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU1_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU1_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU1_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU1_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU1_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU1_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU1_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU1_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU1_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU1_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU1_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU1_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU1_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU1_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU1_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU1_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU1_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU1_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU1_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU1_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU1_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU1_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU1_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU1_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU1_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU1_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU1_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU1_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU1_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU1_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU1_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU1_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU1_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU1_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU1_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU1_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU1_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU1_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU1_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU1_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU1_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU1_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU1_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU1_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU1_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU1_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU1_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU1_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU1_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU1_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU1_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU1_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU1_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU1_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU1_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU1_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU1_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU1_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU1_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU1_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU1_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU1_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU1_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU1_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU1_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU1_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU1_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU1_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU1_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU1_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU1_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU1_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU1_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU1_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU1_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU1_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU1_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU1_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU1_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU1_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU1_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU1_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU1_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU1_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU1_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU1_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU1_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU1_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU1_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU1_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU1_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU1_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU1_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU1_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU1_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU1_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU1_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU1_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU1_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU1_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU1_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU1_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU1_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU1_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU1_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU1_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU1_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU1_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU1_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU1_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU1_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU1_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU1_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU1_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU1_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU1_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU1_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU1_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU1_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU1_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU1_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU1_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU1_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU1_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU1_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU1_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU1_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU1_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU1_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU1_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU1_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU1_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU1_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU1_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU1_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU1_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU1_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU1_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU1_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU1_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU1_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU1_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU1_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU1_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU1_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU1_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU1_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU1_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU1_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU1_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU1_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU1_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU1_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU1_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU1_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU1_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU1_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU1_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU1_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU1_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU1_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU1_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU1_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU1_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU1_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU1_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU1_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU1_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU1_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU1_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU1_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU1_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU1_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU1_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU1_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU1_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU1_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU1_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU1_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU1_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU1_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU1_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU1_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU1_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU1_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU1_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU1_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU1_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU1_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU1_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU1_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU1_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU1_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU1_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU1_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU1_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU1_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU1_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU1_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU1_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU1_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU1_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU1_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU1_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU1_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU1_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU1_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU1_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU1_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU1_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU1_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU1_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU1_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU1_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU1_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU1_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU1_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU1_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU1_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU1_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU1_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU1_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU1_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU1_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU1_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU1_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU1_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU1_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU1_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU1_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU1_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU1_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU1_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU1_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU1_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX0_MASK) #define MMU_TBU1_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU1_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU1_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX1_MASK) #define MMU_TBU1_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU1_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU1_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX2_MASK) #define MMU_TBU1_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU1_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU1_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX3_MASK) #define MMU_TBU1_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU1_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU1_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX4_MASK) #define MMU_TBU1_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU1_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU1_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX5_MASK) #define MMU_TBU1_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU1_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU1_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX6_MASK) #define MMU_TBU1_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU1_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU1_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX7_MASK) #define MMU_TBU1_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU1_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU1_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX8_MASK) #define MMU_TBU1_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU1_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU1_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX9_MASK) #define MMU_TBU1_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU1_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU1_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX10_MASK) #define MMU_TBU1_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU1_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU1_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX11_MASK) #define MMU_TBU1_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU1_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU1_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU1_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU1_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU1_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU1_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX13_MASK) #define MMU_TBU1_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU1_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU1_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX14_MASK) #define MMU_TBU1_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU1_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU1_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU1_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU1_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU1_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU1_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU1_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU1_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU1_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU1_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU1_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU1_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU1_ITEN_ITEN_MASK (0x1U) #define MMU_TBU1_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU1_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_ITEN_ITEN_SHIFT)) & MMU_TBU1_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU1_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU1_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU1_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU1_ITOP_TBU_ras_cri_MASK) #define MMU_TBU1_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU1_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU1_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU1_ITOP_TBU_ras_eri_MASK) #define MMU_TBU1_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU1_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU1_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU1_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU1_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU1_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU1_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU1_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU1_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU1_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU1_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU1_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU1_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU1_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU1_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU1_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU1_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU1_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU1_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU1_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU1_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU1_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU1_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU1_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU1_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU1_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU1_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU1_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU1_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU1_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU1_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU1_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU1_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU1_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU1_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU1_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU1_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU1_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU1_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU1_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU1_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU1_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU1_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU1_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU1_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU1_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU1_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU1_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU1_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU1_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU1_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU1_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU1_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU1_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU1_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU1_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU1_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU1_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU1_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU1_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU1_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU1_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU1_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU1_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU1_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU1_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU1_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU1_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU1_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU1_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU1_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU1_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU1_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU1_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU1_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU1_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU1_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU1_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU1_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU1_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU1_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU1_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU1_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU1_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU1_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU1_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU1_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU1_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU1_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU1_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU1_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU1_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU1_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU1_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU1_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU1_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU1_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU1_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU1_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU1_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU1_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU1_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU1_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU1_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU1_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU1_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU1_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU1_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU1_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU1_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU1_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU1_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU1_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU1_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU1_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU1_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU1_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU1_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU1_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU1_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU1_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU1_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU1_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU1_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU1_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU1_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU1_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU1_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU1_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU1_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU1_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU1_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU1_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU1_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU1_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU1_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU1_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU1_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU1_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU1_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU1_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU1_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU1_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU1_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU1_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU1_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU1_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU1_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU1_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU1_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU1_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU1_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU1_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU1_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU1_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU1_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU1_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU1_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU1_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU1_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU1_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU1_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU1_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU1_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU1_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU1_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU1_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU1_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU1_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU1_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU1_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU1_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU1_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU1_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU1_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU1_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU1_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU1_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU1_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU1_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU1_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU1_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU1_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU1_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU1_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU1_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU1_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU1_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU1_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU1_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU1_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU1_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU1_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU1_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU1_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU1_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU1_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU1_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU1_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU1_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU1_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU1_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU1_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU1_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU1_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU1_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU1_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU1_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU1_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU1_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU1_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU1_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU1_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU1_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU1_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU1_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU1_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU1_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU1_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU1_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU1_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU1_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU1_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU1_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU1_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU1_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU1_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU1_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU1_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU1_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU1_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU1_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU1_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU1_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU1_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU1_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU1_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU1_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU1_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU1_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU1_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU1_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU1_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU1_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU1_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU1_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU1_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU1_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU1_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU1_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU1_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU1_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU1_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU1_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU1_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU1_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU1_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU1_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU1_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU1_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU1_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU1_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU1_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU1_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU1_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU1_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU1_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU1_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU1_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU1_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU1_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU1_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU1_Register_Masks */ /* MMU_TBU1 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU1 base address */ #define NOC__MMU_TBU_TCU__TBU1_BASE (0x49130000u) /** Peripheral NOC__MMU_TBU_TCU__TBU1 base pointer */ #define NOC__MMU_TBU_TCU__TBU1 ((MMU_TBU1_Type *)NOC__MMU_TBU_TCU__TBU1_BASE) /** Array initializer of MMU_TBU1 peripheral base addresses */ #define MMU_TBU1_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU1_BASE } /** Array initializer of MMU_TBU1 peripheral base pointers */ #define MMU_TBU1_BASE_PTRS { NOC__MMU_TBU_TCU__TBU1 } /*! * @} */ /* end of group MMU_TBU1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU2_Peripheral_Access_Layer MMU_TBU2 Peripheral Access Layer * @{ */ /** MMU_TBU2 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU2_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU2_Register_Masks MMU_TBU2 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU2_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU2_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU2_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU2_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU2_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU2_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU2_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU2_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU2_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU2_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU2_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU2_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU2_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU2_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU2_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU2_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU2_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU2_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU2_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU2_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU2_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU2_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU2_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU2_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU2_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU2_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU2_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU2_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU2_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU2_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU2_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU2_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU2_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU2_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU2_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU2_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU2_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU2_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU2_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU2_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU2_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU2_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU2_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU2_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU2_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU2_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU2_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU2_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU2_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU2_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU2_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU2_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU2_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU2_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU2_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU2_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU2_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU2_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU2_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU2_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU2_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU2_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU2_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU2_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU2_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU2_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU2_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU2_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU2_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU2_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU2_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU2_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU2_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU2_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU2_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU2_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU2_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU2_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU2_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU2_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU2_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU2_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU2_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU2_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU2_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU2_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU2_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU2_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU2_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU2_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU2_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU2_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU2_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU2_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU2_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU2_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU2_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU2_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU2_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU2_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU2_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU2_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU2_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU2_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU2_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU2_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU2_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU2_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU2_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU2_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU2_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU2_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU2_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU2_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU2_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU2_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU2_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU2_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU2_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU2_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU2_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU2_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU2_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU2_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU2_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU2_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU2_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU2_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU2_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU2_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU2_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU2_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU2_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU2_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU2_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU2_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU2_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU2_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU2_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU2_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU2_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU2_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU2_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU2_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU2_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU2_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU2_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU2_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU2_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU2_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU2_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU2_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU2_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU2_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU2_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU2_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU2_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU2_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU2_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU2_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU2_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU2_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU2_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU2_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU2_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU2_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU2_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU2_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU2_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU2_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU2_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU2_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU2_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU2_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU2_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU2_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU2_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU2_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU2_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU2_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU2_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU2_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU2_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU2_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU2_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU2_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU2_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU2_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU2_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU2_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU2_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU2_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU2_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU2_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU2_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU2_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU2_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU2_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU2_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU2_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU2_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU2_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU2_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU2_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU2_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU2_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU2_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU2_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU2_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU2_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU2_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU2_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU2_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU2_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU2_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU2_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU2_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU2_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU2_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU2_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU2_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU2_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU2_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU2_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU2_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU2_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU2_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU2_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU2_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU2_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU2_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU2_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU2_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU2_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU2_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU2_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU2_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU2_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU2_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU2_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU2_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU2_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU2_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU2_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU2_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU2_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU2_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU2_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU2_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU2_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU2_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU2_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU2_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU2_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU2_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU2_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU2_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU2_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU2_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU2_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU2_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU2_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU2_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU2_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU2_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX0_MASK) #define MMU_TBU2_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU2_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU2_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX1_MASK) #define MMU_TBU2_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU2_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU2_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX2_MASK) #define MMU_TBU2_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU2_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU2_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX3_MASK) #define MMU_TBU2_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU2_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU2_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX4_MASK) #define MMU_TBU2_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU2_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU2_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX5_MASK) #define MMU_TBU2_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU2_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU2_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX6_MASK) #define MMU_TBU2_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU2_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU2_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX7_MASK) #define MMU_TBU2_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU2_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU2_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX8_MASK) #define MMU_TBU2_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU2_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU2_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX9_MASK) #define MMU_TBU2_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU2_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU2_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX10_MASK) #define MMU_TBU2_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU2_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU2_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX11_MASK) #define MMU_TBU2_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU2_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU2_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU2_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU2_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU2_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU2_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX13_MASK) #define MMU_TBU2_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU2_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU2_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX14_MASK) #define MMU_TBU2_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU2_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU2_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU2_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU2_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU2_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU2_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU2_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU2_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU2_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU2_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU2_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU2_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU2_ITEN_ITEN_MASK (0x1U) #define MMU_TBU2_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU2_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_ITEN_ITEN_SHIFT)) & MMU_TBU2_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU2_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU2_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU2_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU2_ITOP_TBU_ras_cri_MASK) #define MMU_TBU2_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU2_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU2_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU2_ITOP_TBU_ras_eri_MASK) #define MMU_TBU2_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU2_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU2_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU2_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU2_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU2_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU2_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU2_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU2_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU2_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU2_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU2_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU2_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU2_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU2_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU2_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU2_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU2_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU2_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU2_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU2_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU2_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU2_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU2_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU2_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU2_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU2_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU2_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU2_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU2_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU2_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU2_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU2_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU2_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU2_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU2_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU2_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU2_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU2_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU2_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU2_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU2_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU2_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU2_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU2_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU2_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU2_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU2_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU2_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU2_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU2_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU2_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU2_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU2_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU2_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU2_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU2_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU2_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU2_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU2_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU2_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU2_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU2_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU2_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU2_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU2_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU2_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU2_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU2_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU2_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU2_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU2_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU2_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU2_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU2_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU2_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU2_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU2_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU2_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU2_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU2_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU2_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU2_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU2_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU2_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU2_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU2_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU2_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU2_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU2_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU2_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU2_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU2_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU2_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU2_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU2_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU2_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU2_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU2_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU2_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU2_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU2_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU2_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU2_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU2_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU2_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU2_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU2_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU2_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU2_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU2_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU2_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU2_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU2_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU2_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU2_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU2_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU2_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU2_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU2_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU2_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU2_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU2_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU2_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU2_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU2_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU2_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU2_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU2_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU2_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU2_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU2_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU2_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU2_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU2_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU2_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU2_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU2_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU2_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU2_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU2_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU2_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU2_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU2_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU2_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU2_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU2_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU2_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU2_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU2_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU2_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU2_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU2_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU2_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU2_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU2_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU2_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU2_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU2_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU2_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU2_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU2_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU2_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU2_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU2_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU2_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU2_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU2_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU2_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU2_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU2_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU2_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU2_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU2_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU2_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU2_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU2_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU2_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU2_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU2_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU2_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU2_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU2_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU2_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU2_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU2_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU2_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU2_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU2_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU2_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU2_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU2_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU2_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU2_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU2_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU2_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU2_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU2_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU2_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU2_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU2_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU2_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU2_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU2_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU2_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU2_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU2_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU2_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU2_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU2_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU2_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU2_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU2_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU2_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU2_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU2_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU2_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU2_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU2_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU2_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU2_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU2_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU2_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU2_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU2_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU2_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU2_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU2_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU2_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU2_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU2_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU2_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU2_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU2_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU2_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU2_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU2_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU2_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU2_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU2_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU2_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU2_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU2_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU2_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU2_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU2_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU2_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU2_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU2_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU2_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU2_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU2_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU2_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU2_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU2_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU2_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU2_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU2_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU2_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU2_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU2_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU2_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU2_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU2_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU2_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU2_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU2_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU2_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU2_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU2_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU2_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU2_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU2_Register_Masks */ /* MMU_TBU2 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU2 base address */ #define NOC__MMU_TBU_TCU__TBU2_BASE (0x49150000u) /** Peripheral NOC__MMU_TBU_TCU__TBU2 base pointer */ #define NOC__MMU_TBU_TCU__TBU2 ((MMU_TBU2_Type *)NOC__MMU_TBU_TCU__TBU2_BASE) /** Array initializer of MMU_TBU2 peripheral base addresses */ #define MMU_TBU2_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU2_BASE } /** Array initializer of MMU_TBU2 peripheral base pointers */ #define MMU_TBU2_BASE_PTRS { NOC__MMU_TBU_TCU__TBU2 } /*! * @} */ /* end of group MMU_TBU2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME10 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME10_Peripheral_Access_Layer MMU_TBU_ME10 Peripheral Access Layer * @{ */ /** MMU_TBU_ME10 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME10_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME10 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME10_Register_Masks MMU_TBU_ME10 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME10_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME10_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME10_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME10_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME10_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME10_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME10_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME10_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME10_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME10_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME10_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME10_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME10_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME10_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME10_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME10_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME10_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME10_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME10_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME10_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME10_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME10_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME10_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME10_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME10_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME10_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME10_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME10_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME10_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME10_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME10_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME10_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME10_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME10_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME10_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME10_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME10_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME10_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME10_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME10_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME10_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME10_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME10_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME10_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME10_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME10_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME10_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME10_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME10_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME10_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME10_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME10_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME10_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME10_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME10_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME10_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME10_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME10_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME10_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME10_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME10_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME10_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME10_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME10_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME10_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME10_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME10_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME10_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME10_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME10_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME10_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME10_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME10_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME10_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME10_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME10_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME10_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME10_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME10_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME10_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME10_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME10_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME10_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME10_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME10_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME10_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME10_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME10_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME10_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME10_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME10_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME10_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME10_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME10_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME10_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME10_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME10_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME10_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME10_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME10_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME10_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME10_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME10_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME10_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME10_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME10_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME10_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME10_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME10_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME10_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME10_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME10_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME10_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME10_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME10_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME10_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME10_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME10_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME10_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME10_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME10_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME10_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME10_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME10_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME10_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME10_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME10_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME10_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME10_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME10_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME10_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME10_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME10_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME10_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_ITEN_ITEN_SHIFT)) & MMU_TBU_ME10_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME10_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME10_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME10_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME10_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME10_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME10_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME10_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME10_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME10_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME10_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME10_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME10_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME10_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME10_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME10_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME10_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME10_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME10_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME10_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME10_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME10_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME10_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME10_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME10_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME10_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME10_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME10_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME10_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME10_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME10_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME10_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME10_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME10_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME10_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME10_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME10_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME10_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME10_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME10_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME10_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME10_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME10_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME10_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME10_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME10_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME10_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME10_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME10_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME10_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME10_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME10_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME10_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME10_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME10_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME10_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME10_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME10_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME10_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME10_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME10_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME10_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME10_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME10_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME10_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME10_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME10_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME10_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME10_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME10_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME10_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME10_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME10_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME10_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME10_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME10_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME10_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME10_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME10_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME10_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME10_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME10_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME10_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME10_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME10_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME10_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME10_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME10_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME10_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME10_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME10_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME10_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME10_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME10_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME10_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME10_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME10_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME10_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME10_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME10_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME10_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME10_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME10_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME10_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME10_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME10_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME10_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME10_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME10_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME10_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME10_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME10_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME10_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME10_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME10_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME10_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME10_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME10_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME10_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME10_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME10_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME10_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME10_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME10_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME10_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME10_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME10_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME10_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME10_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME10_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME10_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME10_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME10_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME10_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME10_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME10_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME10_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME10_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME10_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME10_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME10_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME10_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME10_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME10_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME10_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME10_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME10_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME10_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME10_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME10_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME10_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME10_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME10_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME10_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME10_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME10_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME10_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME10_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME10_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME10_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME10_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME10_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME10_Register_Masks */ /* MMU_TBU_ME10 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU10 base address */ #define NOC__MMU_TBU_TCU__TBU10_BASE (0x49230000u) /** Peripheral NOC__MMU_TBU_TCU__TBU10 base pointer */ #define NOC__MMU_TBU_TCU__TBU10 ((MMU_TBU_ME10_Type *)NOC__MMU_TBU_TCU__TBU10_BASE) /** Array initializer of MMU_TBU_ME10 peripheral base addresses */ #define MMU_TBU_ME10_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU10_BASE } /** Array initializer of MMU_TBU_ME10 peripheral base pointers */ #define MMU_TBU_ME10_BASE_PTRS { NOC__MMU_TBU_TCU__TBU10 } /*! * @} */ /* end of group MMU_TBU_ME10_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME11 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME11_Peripheral_Access_Layer MMU_TBU_ME11 Peripheral Access Layer * @{ */ /** MMU_TBU_ME11 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME11_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME11 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME11_Register_Masks MMU_TBU_ME11 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME11_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME11_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME11_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME11_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME11_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME11_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME11_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME11_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME11_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME11_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME11_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME11_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME11_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME11_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME11_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME11_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME11_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME11_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME11_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME11_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME11_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME11_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME11_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME11_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME11_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME11_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME11_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME11_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME11_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME11_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME11_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME11_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME11_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME11_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME11_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME11_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME11_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME11_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME11_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME11_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME11_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME11_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME11_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME11_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME11_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME11_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME11_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME11_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME11_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME11_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME11_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME11_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME11_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME11_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME11_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME11_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME11_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME11_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME11_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME11_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME11_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME11_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME11_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME11_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME11_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME11_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME11_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME11_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME11_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME11_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME11_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME11_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME11_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME11_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME11_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME11_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME11_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME11_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME11_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME11_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME11_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME11_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME11_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME11_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME11_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME11_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME11_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME11_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME11_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME11_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME11_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME11_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME11_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME11_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME11_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME11_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME11_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME11_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME11_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME11_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME11_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME11_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME11_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME11_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME11_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME11_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME11_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME11_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME11_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME11_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME11_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME11_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME11_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME11_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME11_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME11_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME11_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME11_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME11_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME11_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME11_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME11_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME11_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME11_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME11_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME11_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME11_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME11_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME11_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME11_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME11_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME11_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME11_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME11_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_ITEN_ITEN_SHIFT)) & MMU_TBU_ME11_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME11_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME11_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME11_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME11_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME11_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME11_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME11_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME11_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME11_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME11_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME11_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME11_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME11_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME11_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME11_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME11_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME11_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME11_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME11_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME11_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME11_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME11_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME11_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME11_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME11_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME11_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME11_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME11_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME11_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME11_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME11_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME11_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME11_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME11_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME11_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME11_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME11_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME11_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME11_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME11_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME11_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME11_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME11_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME11_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME11_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME11_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME11_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME11_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME11_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME11_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME11_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME11_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME11_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME11_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME11_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME11_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME11_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME11_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME11_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME11_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME11_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME11_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME11_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME11_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME11_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME11_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME11_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME11_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME11_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME11_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME11_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME11_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME11_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME11_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME11_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME11_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME11_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME11_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME11_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME11_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME11_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME11_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME11_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME11_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME11_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME11_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME11_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME11_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME11_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME11_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME11_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME11_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME11_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME11_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME11_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME11_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME11_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME11_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME11_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME11_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME11_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME11_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME11_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME11_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME11_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME11_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME11_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME11_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME11_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME11_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME11_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME11_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME11_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME11_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME11_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME11_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME11_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME11_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME11_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME11_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME11_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME11_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME11_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME11_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME11_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME11_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME11_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME11_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME11_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME11_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME11_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME11_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME11_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME11_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME11_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME11_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME11_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME11_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME11_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME11_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME11_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME11_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME11_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME11_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME11_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME11_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME11_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME11_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME11_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME11_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME11_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME11_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME11_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME11_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME11_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME11_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME11_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME11_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME11_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME11_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME11_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME11_Register_Masks */ /* MMU_TBU_ME11 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU11 base address */ #define NOC__MMU_TBU_TCU__TBU11_BASE (0x49250000u) /** Peripheral NOC__MMU_TBU_TCU__TBU11 base pointer */ #define NOC__MMU_TBU_TCU__TBU11 ((MMU_TBU_ME11_Type *)NOC__MMU_TBU_TCU__TBU11_BASE) /** Array initializer of MMU_TBU_ME11 peripheral base addresses */ #define MMU_TBU_ME11_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU11_BASE } /** Array initializer of MMU_TBU_ME11 peripheral base pointers */ #define MMU_TBU_ME11_BASE_PTRS { NOC__MMU_TBU_TCU__TBU11 } /*! * @} */ /* end of group MMU_TBU_ME11_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME3_Peripheral_Access_Layer MMU_TBU_ME3 Peripheral Access Layer * @{ */ /** MMU_TBU_ME3 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME3_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME3_Register_Masks MMU_TBU_ME3 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME3_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME3_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME3_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME3_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME3_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME3_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME3_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME3_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME3_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME3_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME3_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME3_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME3_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME3_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME3_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME3_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME3_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME3_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME3_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME3_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME3_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME3_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME3_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME3_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME3_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME3_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME3_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME3_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME3_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME3_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME3_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME3_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME3_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME3_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME3_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME3_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME3_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME3_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME3_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME3_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME3_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME3_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME3_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME3_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME3_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME3_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME3_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME3_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME3_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME3_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME3_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME3_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME3_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME3_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME3_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME3_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME3_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME3_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME3_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME3_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME3_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME3_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME3_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME3_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME3_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME3_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME3_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME3_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME3_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME3_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME3_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME3_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME3_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME3_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME3_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME3_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME3_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME3_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME3_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME3_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME3_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME3_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME3_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME3_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME3_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME3_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME3_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME3_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME3_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME3_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME3_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME3_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME3_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME3_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME3_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME3_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME3_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME3_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME3_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME3_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME3_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME3_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME3_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME3_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME3_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME3_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME3_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME3_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME3_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME3_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME3_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME3_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME3_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME3_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME3_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME3_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME3_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME3_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME3_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME3_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME3_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME3_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME3_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME3_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME3_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME3_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME3_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME3_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME3_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME3_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME3_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME3_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME3_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME3_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_ITEN_ITEN_SHIFT)) & MMU_TBU_ME3_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME3_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME3_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME3_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME3_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME3_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME3_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME3_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME3_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME3_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME3_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME3_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME3_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME3_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME3_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME3_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME3_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME3_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME3_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME3_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME3_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME3_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME3_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME3_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME3_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME3_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME3_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME3_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME3_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME3_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME3_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME3_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME3_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME3_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME3_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME3_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME3_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME3_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME3_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME3_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME3_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME3_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME3_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME3_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME3_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME3_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME3_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME3_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME3_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME3_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME3_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME3_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME3_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME3_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME3_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME3_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME3_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME3_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME3_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME3_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME3_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME3_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME3_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME3_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME3_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME3_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME3_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME3_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME3_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME3_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME3_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME3_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME3_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME3_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME3_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME3_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME3_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME3_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME3_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME3_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME3_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME3_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME3_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME3_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME3_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME3_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME3_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME3_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME3_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME3_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME3_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME3_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME3_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME3_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME3_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME3_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME3_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME3_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME3_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME3_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME3_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME3_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME3_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME3_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME3_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME3_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME3_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME3_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME3_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME3_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME3_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME3_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME3_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME3_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME3_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME3_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME3_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME3_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME3_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME3_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME3_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME3_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME3_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME3_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME3_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME3_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME3_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME3_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME3_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME3_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME3_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME3_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME3_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME3_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME3_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME3_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME3_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME3_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME3_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME3_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME3_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME3_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME3_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME3_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME3_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME3_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME3_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME3_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME3_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME3_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME3_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME3_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME3_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME3_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME3_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME3_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME3_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME3_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME3_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME3_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME3_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME3_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME3_Register_Masks */ /* MMU_TBU_ME3 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU3 base address */ #define NOC__MMU_TBU_TCU__TBU3_BASE (0x49170000u) /** Peripheral NOC__MMU_TBU_TCU__TBU3 base pointer */ #define NOC__MMU_TBU_TCU__TBU3 ((MMU_TBU_ME3_Type *)NOC__MMU_TBU_TCU__TBU3_BASE) /** Array initializer of MMU_TBU_ME3 peripheral base addresses */ #define MMU_TBU_ME3_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU3_BASE } /** Array initializer of MMU_TBU_ME3 peripheral base pointers */ #define MMU_TBU_ME3_BASE_PTRS { NOC__MMU_TBU_TCU__TBU3 } /*! * @} */ /* end of group MMU_TBU_ME3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME4_Peripheral_Access_Layer MMU_TBU_ME4 Peripheral Access Layer * @{ */ /** MMU_TBU_ME4 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME4_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME4_Register_Masks MMU_TBU_ME4 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME4_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME4_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME4_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME4_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME4_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME4_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME4_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME4_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME4_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME4_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME4_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME4_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME4_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME4_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME4_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME4_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME4_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME4_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME4_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME4_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME4_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME4_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME4_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME4_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME4_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME4_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME4_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME4_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME4_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME4_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME4_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME4_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME4_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME4_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME4_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME4_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME4_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME4_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME4_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME4_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME4_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME4_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME4_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME4_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME4_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME4_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME4_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME4_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME4_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME4_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME4_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME4_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME4_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME4_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME4_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME4_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME4_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME4_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME4_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME4_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME4_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME4_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME4_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME4_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME4_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME4_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME4_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME4_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME4_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME4_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME4_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME4_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME4_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME4_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME4_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME4_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME4_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME4_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME4_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME4_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME4_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME4_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME4_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME4_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME4_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME4_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME4_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME4_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME4_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME4_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME4_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME4_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME4_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME4_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME4_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME4_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME4_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME4_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME4_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME4_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME4_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME4_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME4_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME4_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME4_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME4_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME4_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME4_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME4_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME4_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME4_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME4_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME4_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME4_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME4_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME4_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME4_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME4_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME4_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME4_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME4_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME4_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME4_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME4_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME4_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME4_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME4_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME4_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME4_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME4_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME4_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME4_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME4_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME4_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_ITEN_ITEN_SHIFT)) & MMU_TBU_ME4_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME4_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME4_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME4_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME4_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME4_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME4_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME4_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME4_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME4_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME4_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME4_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME4_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME4_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME4_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME4_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME4_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME4_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME4_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME4_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME4_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME4_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME4_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME4_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME4_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME4_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME4_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME4_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME4_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME4_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME4_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME4_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME4_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME4_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME4_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME4_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME4_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME4_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME4_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME4_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME4_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME4_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME4_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME4_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME4_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME4_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME4_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME4_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME4_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME4_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME4_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME4_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME4_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME4_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME4_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME4_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME4_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME4_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME4_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME4_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME4_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME4_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME4_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME4_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME4_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME4_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME4_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME4_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME4_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME4_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME4_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME4_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME4_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME4_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME4_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME4_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME4_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME4_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME4_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME4_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME4_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME4_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME4_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME4_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME4_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME4_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME4_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME4_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME4_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME4_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME4_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME4_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME4_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME4_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME4_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME4_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME4_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME4_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME4_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME4_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME4_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME4_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME4_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME4_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME4_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME4_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME4_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME4_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME4_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME4_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME4_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME4_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME4_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME4_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME4_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME4_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME4_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME4_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME4_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME4_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME4_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME4_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME4_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME4_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME4_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME4_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME4_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME4_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME4_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME4_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME4_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME4_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME4_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME4_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME4_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME4_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME4_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME4_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME4_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME4_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME4_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME4_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME4_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME4_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME4_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME4_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME4_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME4_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME4_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME4_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME4_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME4_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME4_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME4_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME4_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME4_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME4_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME4_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME4_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME4_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME4_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME4_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME4_Register_Masks */ /* MMU_TBU_ME4 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU4 base address */ #define NOC__MMU_TBU_TCU__TBU4_BASE (0x49190000u) /** Peripheral NOC__MMU_TBU_TCU__TBU4 base pointer */ #define NOC__MMU_TBU_TCU__TBU4 ((MMU_TBU_ME4_Type *)NOC__MMU_TBU_TCU__TBU4_BASE) /** Array initializer of MMU_TBU_ME4 peripheral base addresses */ #define MMU_TBU_ME4_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU4_BASE } /** Array initializer of MMU_TBU_ME4 peripheral base pointers */ #define MMU_TBU_ME4_BASE_PTRS { NOC__MMU_TBU_TCU__TBU4 } /*! * @} */ /* end of group MMU_TBU_ME4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME5_Peripheral_Access_Layer MMU_TBU_ME5 Peripheral Access Layer * @{ */ /** MMU_TBU_ME5 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME5_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME5_Register_Masks MMU_TBU_ME5 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME5_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME5_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME5_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME5_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME5_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME5_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME5_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME5_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME5_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME5_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME5_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME5_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME5_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME5_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME5_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME5_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME5_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME5_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME5_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME5_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME5_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME5_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME5_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME5_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME5_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME5_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME5_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME5_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME5_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME5_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME5_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME5_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME5_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME5_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME5_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME5_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME5_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME5_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME5_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME5_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME5_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME5_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME5_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME5_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME5_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME5_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME5_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME5_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME5_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME5_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME5_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME5_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME5_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME5_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME5_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME5_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME5_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME5_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME5_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME5_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME5_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME5_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME5_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME5_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME5_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME5_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME5_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME5_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME5_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME5_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME5_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME5_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME5_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME5_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME5_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME5_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME5_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME5_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME5_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME5_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME5_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME5_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME5_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME5_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME5_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME5_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME5_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME5_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME5_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME5_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME5_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME5_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME5_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME5_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME5_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME5_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME5_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME5_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME5_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME5_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME5_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME5_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME5_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME5_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME5_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME5_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME5_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME5_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME5_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME5_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME5_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME5_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME5_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME5_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME5_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME5_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME5_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME5_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME5_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME5_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME5_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME5_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME5_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME5_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME5_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME5_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME5_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME5_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME5_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME5_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME5_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME5_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME5_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME5_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_ITEN_ITEN_SHIFT)) & MMU_TBU_ME5_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME5_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME5_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME5_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME5_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME5_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME5_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME5_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME5_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME5_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME5_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME5_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME5_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME5_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME5_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME5_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME5_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME5_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME5_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME5_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME5_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME5_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME5_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME5_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME5_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME5_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME5_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME5_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME5_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME5_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME5_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME5_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME5_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME5_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME5_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME5_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME5_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME5_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME5_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME5_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME5_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME5_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME5_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME5_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME5_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME5_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME5_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME5_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME5_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME5_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME5_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME5_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME5_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME5_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME5_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME5_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME5_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME5_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME5_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME5_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME5_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME5_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME5_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME5_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME5_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME5_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME5_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME5_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME5_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME5_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME5_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME5_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME5_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME5_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME5_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME5_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME5_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME5_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME5_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME5_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME5_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME5_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME5_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME5_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME5_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME5_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME5_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME5_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME5_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME5_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME5_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME5_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME5_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME5_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME5_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME5_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME5_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME5_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME5_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME5_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME5_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME5_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME5_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME5_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME5_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME5_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME5_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME5_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME5_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME5_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME5_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME5_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME5_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME5_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME5_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME5_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME5_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME5_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME5_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME5_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME5_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME5_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME5_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME5_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME5_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME5_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME5_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME5_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME5_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME5_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME5_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME5_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME5_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME5_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME5_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME5_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME5_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME5_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME5_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME5_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME5_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME5_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME5_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME5_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME5_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME5_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME5_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME5_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME5_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME5_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME5_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME5_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME5_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME5_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME5_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME5_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME5_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME5_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME5_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME5_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME5_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME5_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME5_Register_Masks */ /* MMU_TBU_ME5 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU5 base address */ #define NOC__MMU_TBU_TCU__TBU5_BASE (0x491B0000u) /** Peripheral NOC__MMU_TBU_TCU__TBU5 base pointer */ #define NOC__MMU_TBU_TCU__TBU5 ((MMU_TBU_ME5_Type *)NOC__MMU_TBU_TCU__TBU5_BASE) /** Array initializer of MMU_TBU_ME5 peripheral base addresses */ #define MMU_TBU_ME5_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU5_BASE } /** Array initializer of MMU_TBU_ME5 peripheral base pointers */ #define MMU_TBU_ME5_BASE_PTRS { NOC__MMU_TBU_TCU__TBU5 } /*! * @} */ /* end of group MMU_TBU_ME5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME6 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME6_Peripheral_Access_Layer MMU_TBU_ME6 Peripheral Access Layer * @{ */ /** MMU_TBU_ME6 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME6_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME6 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME6_Register_Masks MMU_TBU_ME6 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME6_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME6_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME6_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME6_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME6_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME6_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME6_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME6_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME6_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME6_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME6_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME6_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME6_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME6_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME6_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME6_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME6_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME6_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME6_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME6_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME6_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME6_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME6_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME6_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME6_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME6_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME6_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME6_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME6_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME6_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME6_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME6_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME6_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME6_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME6_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME6_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME6_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME6_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME6_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME6_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME6_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME6_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME6_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME6_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME6_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME6_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME6_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME6_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME6_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME6_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME6_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME6_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME6_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME6_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME6_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME6_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME6_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME6_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME6_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME6_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME6_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME6_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME6_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME6_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME6_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME6_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME6_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME6_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME6_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME6_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME6_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME6_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME6_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME6_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME6_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME6_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME6_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME6_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME6_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME6_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME6_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME6_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME6_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME6_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME6_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME6_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME6_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME6_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME6_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME6_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME6_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME6_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME6_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME6_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME6_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME6_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME6_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME6_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME6_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME6_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME6_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME6_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME6_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME6_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME6_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME6_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME6_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME6_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME6_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME6_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME6_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME6_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME6_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME6_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME6_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME6_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME6_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME6_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME6_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME6_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME6_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME6_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME6_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME6_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME6_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME6_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME6_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME6_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME6_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME6_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME6_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME6_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME6_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME6_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_ITEN_ITEN_SHIFT)) & MMU_TBU_ME6_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME6_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME6_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME6_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME6_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME6_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME6_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME6_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME6_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME6_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME6_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME6_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME6_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME6_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME6_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME6_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME6_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME6_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME6_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME6_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME6_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME6_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME6_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME6_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME6_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME6_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME6_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME6_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME6_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME6_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME6_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME6_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME6_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME6_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME6_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME6_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME6_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME6_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME6_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME6_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME6_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME6_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME6_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME6_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME6_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME6_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME6_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME6_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME6_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME6_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME6_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME6_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME6_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME6_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME6_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME6_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME6_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME6_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME6_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME6_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME6_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME6_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME6_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME6_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME6_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME6_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME6_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME6_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME6_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME6_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME6_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME6_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME6_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME6_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME6_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME6_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME6_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME6_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME6_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME6_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME6_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME6_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME6_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME6_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME6_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME6_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME6_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME6_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME6_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME6_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME6_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME6_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME6_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME6_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME6_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME6_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME6_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME6_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME6_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME6_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME6_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME6_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME6_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME6_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME6_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME6_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME6_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME6_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME6_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME6_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME6_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME6_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME6_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME6_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME6_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME6_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME6_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME6_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME6_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME6_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME6_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME6_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME6_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME6_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME6_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME6_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME6_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME6_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME6_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME6_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME6_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME6_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME6_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME6_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME6_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME6_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME6_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME6_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME6_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME6_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME6_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME6_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME6_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME6_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME6_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME6_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME6_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME6_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME6_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME6_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME6_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME6_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME6_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME6_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME6_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME6_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME6_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME6_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME6_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME6_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME6_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME6_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME6_Register_Masks */ /* MMU_TBU_ME6 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU6 base address */ #define NOC__MMU_TBU_TCU__TBU6_BASE (0x491D0000u) /** Peripheral NOC__MMU_TBU_TCU__TBU6 base pointer */ #define NOC__MMU_TBU_TCU__TBU6 ((MMU_TBU_ME6_Type *)NOC__MMU_TBU_TCU__TBU6_BASE) /** Array initializer of MMU_TBU_ME6 peripheral base addresses */ #define MMU_TBU_ME6_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU6_BASE } /** Array initializer of MMU_TBU_ME6 peripheral base pointers */ #define MMU_TBU_ME6_BASE_PTRS { NOC__MMU_TBU_TCU__TBU6 } /*! * @} */ /* end of group MMU_TBU_ME6_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME7 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME7_Peripheral_Access_Layer MMU_TBU_ME7 Peripheral Access Layer * @{ */ /** MMU_TBU_ME7 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME7_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME7 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME7_Register_Masks MMU_TBU_ME7 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME7_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME7_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME7_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME7_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME7_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME7_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME7_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME7_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME7_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME7_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME7_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME7_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME7_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME7_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME7_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME7_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME7_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME7_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME7_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME7_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME7_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME7_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME7_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME7_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME7_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME7_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME7_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME7_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME7_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME7_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME7_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME7_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME7_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME7_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME7_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME7_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME7_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME7_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME7_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME7_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME7_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME7_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME7_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME7_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME7_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME7_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME7_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME7_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME7_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME7_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME7_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME7_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME7_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME7_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME7_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME7_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME7_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME7_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME7_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME7_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME7_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME7_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME7_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME7_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME7_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME7_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME7_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME7_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME7_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME7_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME7_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME7_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME7_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME7_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME7_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME7_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME7_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME7_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME7_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME7_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME7_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME7_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME7_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME7_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME7_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME7_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME7_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME7_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME7_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME7_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME7_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME7_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME7_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME7_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME7_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME7_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME7_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME7_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME7_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME7_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME7_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME7_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME7_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME7_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME7_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME7_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME7_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME7_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME7_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME7_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME7_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME7_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME7_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME7_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME7_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME7_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME7_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME7_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME7_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME7_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME7_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME7_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME7_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME7_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME7_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME7_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME7_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME7_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME7_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME7_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME7_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME7_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME7_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME7_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_ITEN_ITEN_SHIFT)) & MMU_TBU_ME7_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME7_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME7_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME7_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME7_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME7_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME7_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME7_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME7_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME7_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME7_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME7_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME7_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME7_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME7_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME7_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME7_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME7_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME7_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME7_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME7_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME7_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME7_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME7_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME7_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME7_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME7_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME7_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME7_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME7_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME7_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME7_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME7_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME7_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME7_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME7_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME7_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME7_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME7_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME7_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME7_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME7_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME7_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME7_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME7_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME7_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME7_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME7_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME7_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME7_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME7_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME7_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME7_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME7_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME7_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME7_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME7_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME7_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME7_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME7_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME7_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME7_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME7_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME7_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME7_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME7_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME7_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME7_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME7_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME7_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME7_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME7_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME7_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME7_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME7_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME7_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME7_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME7_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME7_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME7_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME7_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME7_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME7_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME7_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME7_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME7_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME7_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME7_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME7_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME7_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME7_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME7_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME7_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME7_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME7_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME7_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME7_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME7_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME7_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME7_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME7_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME7_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME7_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME7_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME7_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME7_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME7_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME7_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME7_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME7_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME7_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME7_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME7_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME7_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME7_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME7_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME7_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME7_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME7_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME7_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME7_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME7_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME7_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME7_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME7_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME7_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME7_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME7_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME7_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME7_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME7_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME7_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME7_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME7_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME7_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME7_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME7_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME7_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME7_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME7_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME7_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME7_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME7_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME7_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME7_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME7_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME7_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME7_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME7_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME7_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME7_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME7_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME7_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME7_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME7_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME7_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME7_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME7_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME7_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME7_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME7_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME7_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME7_Register_Masks */ /* MMU_TBU_ME7 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU7 base address */ #define NOC__MMU_TBU_TCU__TBU7_BASE (0x491F0000u) /** Peripheral NOC__MMU_TBU_TCU__TBU7 base pointer */ #define NOC__MMU_TBU_TCU__TBU7 ((MMU_TBU_ME7_Type *)NOC__MMU_TBU_TCU__TBU7_BASE) /** Array initializer of MMU_TBU_ME7 peripheral base addresses */ #define MMU_TBU_ME7_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU7_BASE } /** Array initializer of MMU_TBU_ME7 peripheral base pointers */ #define MMU_TBU_ME7_BASE_PTRS { NOC__MMU_TBU_TCU__TBU7 } /*! * @} */ /* end of group MMU_TBU_ME7_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TBU_ME9 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME9_Peripheral_Access_Layer MMU_TBU_ME9 Peripheral Access Layer * @{ */ /** MMU_TBU_ME9 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4048]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_1[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_2[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_3[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_4[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_5[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_6[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_7[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_8[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_9[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_10[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_11[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_12[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_13[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_14[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_15[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_16[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_17[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_18[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_19[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_20[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_21[1780]; __IO uint32_t MSMON_CFG_SEL_NS; /**< MSMON_CFG_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_22[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_23[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_24[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_25[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_26[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_27[21940]; __IO uint32_t TBU_CTRL; /**< TBU Control Register, offset: 0x8E00 */ __IO uint32_t TBU_LTI_PORT_RESOURCE_LIMIT; /**< TBU LTI Resource Allocation Register, offset: 0x8E04 */ uint8_t RESERVED_28[16]; __IO uint32_t TBU_SCR; /**< TBU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_29[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_TBU; /**< ITOP_TBU, offset: 0x8E24 */ __I uint32_t ITIN_TBU; /**< ITIN_TBU, offset: 0x8E28 */ uint8_t RESERVED_30[4]; __I uint32_t TBU_SYSDISC0; /**< TBU_SYSDISC0, offset: 0x8E30 */ __I uint32_t TBU_SYSDISC1; /**< TBU_SYSDISC1, offset: 0x8E34 */ __I uint32_t TBU_SYSDISC2; /**< TBU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TBU_SYSDISC3; /**< TBU_SYSDISC3, offset: 0x8E3C */ __I uint32_t TBU_SYSDISC4; /**< TBU_SYSDISC4, offset: 0x8E40 */ __I uint32_t TBU_SYSDISC5; /**< TBU_SYSDISC5, offset: 0x8E44 */ __I uint32_t TBU_SYSDISC6; /**< TBU_SYSDISC6, offset: 0x8E48 */ __I uint32_t TBU_SYSDISC7; /**< TBU_SYSDISC7, offset: 0x8E4C */ __I uint32_t TBU_SYSDISC8; /**< TBU_SYSDISC8, offset: 0x8E50 */ __I uint32_t TBU_SYSDISC9; /**< TBU_SYSDISC9, offset: 0x8E54 */ __I uint32_t TBU_SYSDISC10; /**< TBU_SYSDISC10, offset: 0x8E58 */ __I uint32_t TBU_SYSDISC11; /**< TBU_SYSDISC11, offset: 0x8E5C */ __I uint32_t TBU_SYSDISC12; /**< TBU_SYSDISC12, offset: 0x8E60 */ __I uint32_t TBU_SYSDISC13; /**< TBU_SYSDISC13, offset: 0x8E64 */ __I uint32_t TBU_SYSDISC14; /**< TBU_SYSDISC14, offset: 0x8E68 */ uint8_t RESERVED_31[20]; __I uint32_t TBU_ERRFR_LO; /**< TBU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TBU_ERRFR_HI; /**< TBU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TBU_ERRCTLR_LO; /**< TBU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TBU_ERRCTLR_HI; /**< TBU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TBU_ERRSTATUS_LO; /**< TBU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TBU_ERRSTATUS_HI; /**< TBU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_32[40]; __IO uint32_t TBU_ERRGEN_LO; /**< TBU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TBU_ERRGEN_HI; /**< TBU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_33[8504]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_34[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_35[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_36[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_37[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_38[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_39[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_40[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_41[1780]; __IO uint32_t MSMON_CFG_SEL_S; /**< MSMON_CFG_SEL_s, offset: 0xB800 */ uint8_t RESERVED_42[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_43[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_44[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_45[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_46[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_47[26548]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x12000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x12004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x12008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x1200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x12010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x12014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x12018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x1201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x12020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x12024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x12028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x1202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x12030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x12034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x12038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x1203C */ uint8_t RESERVED_48[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x12600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x12604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x12608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x1260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x12610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x12614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x12618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x1261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x12620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x12624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x12628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x1262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x12630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x12634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x12638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x1263C */ uint8_t RESERVED_49[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x12C80 */ uint8_t RESERVED_50[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x12CC0 */ uint8_t RESERVED_51[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x12D88 */ } MMU_TBU_ME9_Type; /* ---------------------------------------------------------------------------- -- MMU_TBU_ME9 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TBU_ME9_Register_Masks MMU_TBU_ME9 Register Masks * @{ */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME9_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR4_DES_2_MASK) #define MMU_TBU_ME9_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME9_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME9_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME9_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR1_PART_1_MASK) #define MMU_TBU_ME9_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME9_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME9_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME9_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR2_DES_1_MASK) #define MMU_TBU_ME9_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME9_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME9_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR2_JEDEC_MASK) #define MMU_TBU_ME9_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME9_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME9_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR3_CMOD_MASK) #define MMU_TBU_ME9_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME9_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME9_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME9_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME9_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME9_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME9_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TBU_ME9_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME9_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TBU_ME9_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME9_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TBU_ME9_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TBU_ME9_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TBU_ME9_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SCR_SO_MASK) #define MMU_TBU_ME9_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TBU_ME9_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TBU_ME9_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TBU_ME9_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TBU_ME9_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TBU_ME9_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TBU_ME9_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TBU_ME9_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TBU_ME9_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TBU_ME9_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TBU_ME9_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TBU_ME9_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TBU_ME9_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CR_E_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME9_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME9_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME9_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TBU_ME9_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TBU_ME9_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TBU_ME9_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TBU_ME9_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TBU_ME9_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TBU_ME9_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TBU_ME9_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TBU_ME9_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME9_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TBU_ME9_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME9_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TBU_ME9_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TBU_ME9_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME9_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TBU_ME9_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TBU_ME9_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME9_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TBU_ME9_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME9_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME9_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TBU_ME9_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME9_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME9_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TBU_ME9_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME9_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME9_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME9_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TBU_ME9_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME9_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TBU_ME9_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_NS - MSMON_CFG_SEL_ns */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CFG_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME9_MSMON_CFG_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME9_MSMON_CFG_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_SEL_NS_MON_SEL_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_SEL_NS_MON_SEL_MASK) #define MMU_TBU_ME9_MSMON_CFG_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TBU_ME9_MSMON_CFG_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME9_MSMON_CFG_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_SEL_NS_RIS_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TBU_ME9_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME9_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME9_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_NS_VALUE_MASK) #define MMU_TBU_ME9_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME9_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME9_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name TBU_CTRL - TBU Control Register */ /*! @{ */ #define MMU_TBU_ME9_TBU_CTRL_AUX0_MASK (0x1U) #define MMU_TBU_ME9_TBU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TBU_ME9_TBU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX0_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX0_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX1_MASK (0x2U) #define MMU_TBU_ME9_TBU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TBU_ME9_TBU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX1_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX1_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX2_MASK (0x4U) #define MMU_TBU_ME9_TBU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TBU_ME9_TBU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX2_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX2_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX3_MASK (0x8U) #define MMU_TBU_ME9_TBU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TBU_ME9_TBU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX3_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX3_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX4_MASK (0x10U) #define MMU_TBU_ME9_TBU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TBU_ME9_TBU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX4_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX4_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX5_MASK (0x20U) #define MMU_TBU_ME9_TBU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TBU_ME9_TBU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX5_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX5_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX6_MASK (0x40U) #define MMU_TBU_ME9_TBU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TBU_ME9_TBU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX6_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX6_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX7_MASK (0x80U) #define MMU_TBU_ME9_TBU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TBU_ME9_TBU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX7_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX7_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX8_MASK (0x100U) #define MMU_TBU_ME9_TBU_CTRL_AUX8_SHIFT (8U) /*! AUX8 - AUX8 */ #define MMU_TBU_ME9_TBU_CTRL_AUX8(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX8_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX8_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX9_MASK (0x200U) #define MMU_TBU_ME9_TBU_CTRL_AUX9_SHIFT (9U) /*! AUX9 - AUX9 */ #define MMU_TBU_ME9_TBU_CTRL_AUX9(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX9_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX9_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX10_MASK (0x400U) #define MMU_TBU_ME9_TBU_CTRL_AUX10_SHIFT (10U) /*! AUX10 - AUX10 */ #define MMU_TBU_ME9_TBU_CTRL_AUX10(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX10_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX10_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX11_MASK (0x800U) #define MMU_TBU_ME9_TBU_CTRL_AUX11_SHIFT (11U) /*! AUX11 - AUX11 */ #define MMU_TBU_ME9_TBU_CTRL_AUX11(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX11_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX11_MASK) #define MMU_TBU_ME9_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK (0x1000U) #define MMU_TBU_ME9_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT_DISABLE - LTI_PORT_RESOURCE_LIMIT_DISABLE */ #define MMU_TBU_ME9_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_LTI_PORT_RESOURCE_LIMIT_DISABLE_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX13_MASK (0x2000U) #define MMU_TBU_ME9_TBU_CTRL_AUX13_SHIFT (13U) /*! AUX13 - AUX13 */ #define MMU_TBU_ME9_TBU_CTRL_AUX13(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX13_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX13_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX14_MASK (0x4000U) #define MMU_TBU_ME9_TBU_CTRL_AUX14_SHIFT (14U) /*! AUX14 - AUX14 */ #define MMU_TBU_ME9_TBU_CTRL_AUX14(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX14_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX14_MASK) #define MMU_TBU_ME9_TBU_CTRL_AUX15_MASK (0x8000U) #define MMU_TBU_ME9_TBU_CTRL_AUX15_SHIFT (15U) /*! AUX15 - AUX15 */ #define MMU_TBU_ME9_TBU_CTRL_AUX15(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_CTRL_AUX15_SHIFT)) & MMU_TBU_ME9_TBU_CTRL_AUX15_MASK) /*! @} */ /*! @name TBU_LTI_PORT_RESOURCE_LIMIT - TBU LTI Resource Allocation Register */ /*! @{ */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK (0xFU) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT (0U) /*! LTI_PORT_RESOURCE_LIMIT0 - LTI_PORT_RESOURCE_LIMIT0 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT0_MASK) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK (0xF0U) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT (4U) /*! LTI_PORT_RESOURCE_LIMIT1 - LTI_PORT_RESOURCE_LIMIT1 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT1_MASK) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK (0xF00U) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT (8U) /*! LTI_PORT_RESOURCE_LIMIT2 - LTI_PORT_RESOURCE_LIMIT2 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT2_MASK) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK (0xF000U) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT (12U) /*! LTI_PORT_RESOURCE_LIMIT3 - LTI_PORT_RESOURCE_LIMIT3 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT3_MASK) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK (0xF0000U) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT (16U) /*! LTI_PORT_RESOURCE_LIMIT4 - LTI_PORT_RESOURCE_LIMIT4 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT4_MASK) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK (0xF00000U) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT (20U) /*! LTI_PORT_RESOURCE_LIMIT5 - LTI_PORT_RESOURCE_LIMIT5 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT5_MASK) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK (0xF000000U) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT (24U) /*! LTI_PORT_RESOURCE_LIMIT6 - LTI_PORT_RESOURCE_LIMIT6 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT6_MASK) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK (0xF0000000U) #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT (28U) /*! LTI_PORT_RESOURCE_LIMIT7 - LTI_PORT_RESOURCE_LIMIT7 */ #define MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_SHIFT)) & MMU_TBU_ME9_TBU_LTI_PORT_RESOURCE_LIMIT_LTI_PORT_RESOURCE_LIMIT7_MASK) /*! @} */ /*! @name TBU_SCR - TBU Secure Control Register */ /*! @{ */ #define MMU_TBU_ME9_TBU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TBU_ME9_TBU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TBU_ME9_TBU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SCR_NS_UARCH_SHIFT)) & MMU_TBU_ME9_TBU_SCR_NS_UARCH_MASK) #define MMU_TBU_ME9_TBU_SCR_NS_RAS_MASK (0x2U) #define MMU_TBU_ME9_TBU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TBU_ME9_TBU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SCR_NS_RAS_SHIFT)) & MMU_TBU_ME9_TBU_SCR_NS_RAS_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TBU_ME9_ITEN_ITEN_MASK (0x1U) #define MMU_TBU_ME9_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TBU_ME9_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_ITEN_ITEN_SHIFT)) & MMU_TBU_ME9_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_TBU - ITOP_TBU */ /*! @{ */ #define MMU_TBU_ME9_ITOP_TBU_ras_cri_MASK (0x1U) #define MMU_TBU_ME9_ITOP_TBU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TBU_ME9_ITOP_TBU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_ITOP_TBU_ras_cri_SHIFT)) & MMU_TBU_ME9_ITOP_TBU_ras_cri_MASK) #define MMU_TBU_ME9_ITOP_TBU_ras_eri_MASK (0x2U) #define MMU_TBU_ME9_ITOP_TBU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TBU_ME9_ITOP_TBU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_ITOP_TBU_ras_eri_SHIFT)) & MMU_TBU_ME9_ITOP_TBU_ras_eri_MASK) #define MMU_TBU_ME9_ITOP_TBU_ras_fhi_MASK (0x4U) #define MMU_TBU_ME9_ITOP_TBU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TBU_ME9_ITOP_TBU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_ITOP_TBU_ras_fhi_SHIFT)) & MMU_TBU_ME9_ITOP_TBU_ras_fhi_MASK) #define MMU_TBU_ME9_ITOP_TBU_pmu_snapshot_ack_MASK (0x8U) #define MMU_TBU_ME9_ITOP_TBU_pmu_snapshot_ack_SHIFT (3U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TBU_ME9_ITOP_TBU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_ITOP_TBU_pmu_snapshot_ack_SHIFT)) & MMU_TBU_ME9_ITOP_TBU_pmu_snapshot_ack_MASK) #define MMU_TBU_ME9_ITOP_TBU_pmu_irpt_MASK (0x10U) #define MMU_TBU_ME9_ITOP_TBU_pmu_irpt_SHIFT (4U) /*! pmu_irpt - pmu_irpt */ #define MMU_TBU_ME9_ITOP_TBU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_ITOP_TBU_pmu_irpt_SHIFT)) & MMU_TBU_ME9_ITOP_TBU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TBU - ITIN_TBU */ /*! @{ */ #define MMU_TBU_ME9_ITIN_TBU_pmu_snapshot_req_MASK (0x1U) #define MMU_TBU_ME9_ITIN_TBU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TBU_ME9_ITIN_TBU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_ITIN_TBU_pmu_snapshot_req_SHIFT)) & MMU_TBU_ME9_ITIN_TBU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TBU_SYSDISC0 - TBU_SYSDISC0 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK (0x1FFFFU) #define MMU_TBU_ME9_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT (0U) /*! TBUCFG_MTLB_DEPTH - TBUCFG_MTLB_DEPTH */ #define MMU_TBU_ME9_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC0_TBUCFG_MTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC1 - TBU_SYSDISC1 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK (0x7FU) #define MMU_TBU_ME9_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT (0U) /*! TBUCFG_UTLB_DEPTH - TBUCFG_UTLB_DEPTH */ #define MMU_TBU_ME9_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC1_TBUCFG_UTLB_DEPTH_MASK) /*! @} */ /*! @name TBU_SYSDISC2 - TBU_SYSDISC2 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK (0x1FU) #define MMU_TBU_ME9_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT (0U) /*! TBUCFG_MTLB_WAYS - TBUCFG_MTLB_WAYS */ #define MMU_TBU_ME9_TBU_SYSDISC2_TBUCFG_MTLB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC2_TBUCFG_MTLB_WAYS_MASK) /*! @} */ /*! @name TBU_SYSDISC3 - TBU_SYSDISC3 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK (0x7U) #define MMU_TBU_ME9_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT (0U) /*! TBUCFG_MTLB_BANKS - TBUCFG_MTLB_BANKS */ #define MMU_TBU_ME9_TBU_SYSDISC3_TBUCFG_MTLB_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC3_TBUCFG_MTLB_BANKS_MASK) /*! @} */ /*! @name TBU_SYSDISC4 - TBU_SYSDISC4 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TBU_ME9_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT (0U) /*! TBUCFG_XLATE_SLOTS - TBUCFG_XLATE_SLOTS */ #define MMU_TBU_ME9_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC4_TBUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TBU_SYSDISC5 - TBU_SYSDISC5 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TBU_ME9_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT (0U) /*! TBUCFG_PMU_COUNTERS - TBUCFG_PMU_COUNTERS */ #define MMU_TBU_ME9_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC5_TBUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TBU_SYSDISC6 - TBU_SYSDISC6 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME9_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT (0U) /*! TBUCFG_SID_WIDTH - TBUCFG_SID_WIDTH */ #define MMU_TBU_ME9_TBU_SYSDISC6_TBUCFG_SID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC6_TBUCFG_SID_WIDTH_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC6_TBUCFG_SID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC7 - TBU_SYSDISC7 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK (0x1FU) #define MMU_TBU_ME9_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT (0U) /*! TBUCFG_SSID_WIDTH - TBUCFG_SSID_WIDTH */ #define MMU_TBU_ME9_TBU_SYSDISC7_TBUCFG_SSID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC7_TBUCFG_SSID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC8 - TBU_SYSDISC8 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK (0x1U) #define MMU_TBU_ME9_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT (0U) /*! TBUCFG_DIRECT_IDX - TBUCFG_DIRECT_IDX */ #define MMU_TBU_ME9_TBU_SYSDISC8_TBUCFG_DIRECT_IDX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC8_TBUCFG_DIRECT_IDX_MASK) /*! @} */ /*! @name TBU_SYSDISC9 - TBU_SYSDISC9 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK (0x1FU) #define MMU_TBU_ME9_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT (0U) /*! TBUCFG_MTLB_PARTS - TBUCFG_MTLB_PARTS */ #define MMU_TBU_ME9_TBU_SYSDISC9_TBUCFG_MTLB_PARTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC9_TBUCFG_MTLB_PARTS_MASK) /*! @} */ /*! @name TBU_SYSDISC10 - TBU_SYSDISC10 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK (0x3FU) #define MMU_TBU_ME9_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT (0U) /*! TBUCFG_LTI_OG_WIDTH - TBUCFG_LTI_OG_WIDTH */ #define MMU_TBU_ME9_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC10_TBUCFG_LTI_OG_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC11 - TBU_SYSDISC11 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TBU_ME9_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT (0U) /*! TBUCFG_PARTID_WIDTH - TBUCFG_PARTID_WIDTH */ #define MMU_TBU_ME9_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC11_TBUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TBU_SYSDISC12 - TBU_SYSDISC12 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK (0x7FU) #define MMU_TBU_ME9_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT (0U) /*! TBUCFG_HZRD_ENTRIES - TBUCFG_HZRD_ENTRIES */ #define MMU_TBU_ME9_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC12_TBUCFG_HZRD_ENTRIES_MASK) /*! @} */ /*! @name TBU_SYSDISC13 - TBU_SYSDISC13 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TBU_ME9_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TBUCFG_SLOTRAM_TYPE - TBUCFG_SLOTRAM_TYPE */ #define MMU_TBU_ME9_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC13_TBUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TBU_SYSDISC14 - TBU_SYSDISC14 */ /*! @{ */ #define MMU_TBU_ME9_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TBU_ME9_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TBUCFG_CACHERAM_TYPE - TBUCFG_CACHERAM_TYPE */ #define MMU_TBU_ME9_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TBU_ME9_TBU_SYSDISC14_TBUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TBU_ERRFR_LO - TBU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_TBU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TBU_ME9_TBU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TBU_ME9_TBU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_ED_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_ED_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TBU_ME9_TBU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TBU_ME9_TBU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_UI_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_UI_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TBU_ME9_TBU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TBU_ME9_TBU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_FI_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_FI_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TBU_ME9_TBU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TBU_ME9_TBU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_UE_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_UE_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TBU_ME9_TBU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TBU_ME9_TBU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_CFI_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_CFI_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TBU_ME9_TBU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TBU_ME9_TBU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_CEC_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_CEC_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TBU_ME9_TBU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TBU_ME9_TBU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_RP_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_RP_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TBU_ME9_TBU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TBU_ME9_TBU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_DUI_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_DUI_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TBU_ME9_TBU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TBU_ME9_TBU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_CEO_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_CEO_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TBU_ME9_TBU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TBU_ME9_TBU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_INJ_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_INJ_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TBU_ME9_TBU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TBU_ME9_TBU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_CI_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_CI_MASK) #define MMU_TBU_ME9_TBU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TBU_ME9_TBU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TBU_ME9_TBU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRFR_LO_TS_SHIFT)) & MMU_TBU_ME9_TBU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TBU_ERRCTLR_LO - TBU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_TBU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TBU_ME9_TBU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TBU_ME9_TBU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRCTLR_LO_FI_SHIFT)) & MMU_TBU_ME9_TBU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TBU_ERRSTATUS_LO - TBU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_SERR_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010011.. * 0b00010100.. * 0b00010101.. */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_IERR_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_CI_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_UET_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_PN_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_DE_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_CE_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_MV_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_OF_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_ER_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_UE_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_V_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_V_MASK) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TBU_ME9_TBU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TBU_ME9_TBU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TBU_ERRGEN_LO - TBU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TBU_ME9_TBU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_SERR_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_SERR_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_IERR_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_IERR_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_CI_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_CI_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_UET_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_UET_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_PN_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_PN_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_DE_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_DE_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_CE_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_CE_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_OF_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_OF_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_ER_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_ER_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_UE_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_UE_MASK) #define MMU_TBU_ME9_TBU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TBU_ME9_TBU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TBU_ME9_TBU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_TBU_ERRGEN_LO_V_SHIFT)) & MMU_TBU_ME9_TBU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TBU_ME9_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TBU_ME9_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TBU_ME9_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TBU_ME9_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TBU_ME9_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TBU_ME9_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TBU_ME9_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TBU_ME9_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TBU_ME9_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TBU_ME9_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TBU_ME9_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TBU_ME9_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_S_Revision_MASK) #define MMU_TBU_ME9_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TBU_ME9_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TBU_ME9_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_S_Variant_MASK) #define MMU_TBU_ME9_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TBU_ME9_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TBU_ME9_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TBU_ME9_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TBU_ME9_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TBU_ME9_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TBU_ME9_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TBU_ME9_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TBU_ME9_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TBU_ME9_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TBU_ME9_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TBU_ME9_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TBU_ME9_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TBU_ME9_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TBU_ME9_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TBU_ME9_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TBU_ME9_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TBU_ME9_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TBU_ME9_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TBU_ME9_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME9_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TBU_ME9_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TBU_ME9_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TBU_ME9_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TBU_ME9_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TBU_ME9_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_SEL_S - MSMON_CFG_SEL_s */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CFG_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TBU_ME9_MSMON_CFG_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TBU_ME9_MSMON_CFG_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_SEL_S_MON_SEL_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_SEL_S_MON_SEL_MASK) #define MMU_TBU_ME9_MSMON_CFG_SEL_S_RIS_MASK (0xF000000U) #define MMU_TBU_ME9_MSMON_CFG_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TBU_ME9_MSMON_CFG_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_SEL_S_RIS_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TBU_ME9_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TBU_ME9_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TBU_ME9_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TBU_ME9_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TBU_ME9_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TBU_ME9_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TBU_ME9_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TBU_ME9_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME9_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME9_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_S_VALUE_MASK) #define MMU_TBU_ME9_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME9_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME9_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TBU_ME9_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TBU_ME9_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME9_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TBU_ME9_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TBU_ME9_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TBU_ME9_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TBU_ME9_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TBU_ME9_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TBU_ME9_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TBU_ME9_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TBU_ME9_Register_Masks */ /* MMU_TBU_ME9 - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TBU9 base address */ #define NOC__MMU_TBU_TCU__TBU9_BASE (0x49210000u) /** Peripheral NOC__MMU_TBU_TCU__TBU9 base pointer */ #define NOC__MMU_TBU_TCU__TBU9 ((MMU_TBU_ME9_Type *)NOC__MMU_TBU_TCU__TBU9_BASE) /** Array initializer of MMU_TBU_ME9 peripheral base addresses */ #define MMU_TBU_ME9_BASE_ADDRS { NOC__MMU_TBU_TCU__TBU9_BASE } /** Array initializer of MMU_TBU_ME9 peripheral base pointers */ #define MMU_TBU_ME9_BASE_PTRS { NOC__MMU_TBU_TCU__TBU9 } /*! * @} */ /* end of group MMU_TBU_ME9_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MMU_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TCU_Peripheral_Access_Layer MMU_TCU Peripheral Access Layer * @{ */ /** MMU_TCU - Register Layout Typedef */ typedef struct { __I uint32_t SMMU_IDR0; /**< SMMU_IDR0, offset: 0x0 */ __I uint32_t SMMU_IDR1; /**< SMMU_IDR1, offset: 0x4 */ __I uint32_t SMMU_IDR2; /**< SMMU_IDR2, offset: 0x8 */ __I uint32_t SMMU_IDR3; /**< SMMU_IDR3, offset: 0xC */ __I uint32_t SMMU_IDR4; /**< SMMU_IDR4, offset: 0x10 */ __I uint32_t SMMU_IDR5; /**< SMMU_IDR5, offset: 0x14 */ __I uint32_t SMMU_IIDR; /**< SMMU_IIDR, offset: 0x18 */ __I uint32_t SMMU_AIDR; /**< SMMU_AIDR, offset: 0x1C */ __IO uint32_t SMMU_CR0; /**< SMMU_CR0, offset: 0x20 */ __I uint32_t SMMU_CR0ACK; /**< SMMU_CR0ACK, offset: 0x24 */ __IO uint32_t SMMU_CR1; /**< SMMU_CR1, offset: 0x28 */ __IO uint32_t SMMU_CR2; /**< SMMU_CR2, offset: 0x2C */ uint8_t RESERVED_0[20]; __IO uint32_t SMMU_GBPA; /**< SMMU_GBPA, offset: 0x44 */ __IO uint32_t SMMU_AGBPA; /**< SMMU_AGBPA, offset: 0x48 */ uint8_t RESERVED_1[4]; __IO uint32_t SMMU_IRQ_CTRL; /**< SMMU_IRQ_CTRL, offset: 0x50 */ __I uint32_t SMMU_IRQ_CTRLACK; /**< SMMU_IRQ_CTRLACK, offset: 0x54 */ uint8_t RESERVED_2[8]; __I uint32_t SMMU_GERROR; /**< SMMU_GERROR, offset: 0x60 */ __IO uint32_t SMMU_GERRORN; /**< SMMU_GERRORN, offset: 0x64 */ __IO uint32_t SMMU_GERROR_IRQ_CFG0_LO; /**< SMMU_GERROR_IRQ_CFG0 (Least Significant 32-bits), offset: 0x68 */ __IO uint32_t SMMU_GERROR_IRQ_CFG0_HI; /**< SMMU_GERROR_IRQ_CFG0 (Most Significant 32-bits), offset: 0x6C */ __IO uint32_t SMMU_GERROR_IRQ_CFG1; /**< SMMU_GERROR_IRQ_CFG1, offset: 0x70 */ __IO uint32_t SMMU_GERROR_IRQ_CFG2; /**< SMMU_GERROR_IRQ_CFG2, offset: 0x74 */ uint8_t RESERVED_3[8]; __IO uint32_t SMMU_STRTAB_BASE_LO; /**< SMMU_STRTAB_BASE (Least Significant 32-bits), offset: 0x80 */ __IO uint32_t SMMU_STRTAB_BASE_HI; /**< SMMU_STRTAB_BASE (Most Significant 32-bits), offset: 0x84 */ __IO uint32_t SMMU_STRTAB_BASE_CFG; /**< SMMU_STRTAB_BASE_CFG, offset: 0x88 */ uint8_t RESERVED_4[4]; __IO uint32_t SMMU_CMDQ_BASE_LO; /**< SMMU_CMDQ_BASE (Least Significant 32-bits), offset: 0x90 */ __IO uint32_t SMMU_CMDQ_BASE_HI; /**< SMMU_CMDQ_BASE (Most Significant 32-bits), offset: 0x94 */ __IO uint32_t SMMU_CMDQ_PROD; /**< SMMU_CMDQ_PROD, offset: 0x98 */ __IO uint32_t SMMU_CMDQ_CONS; /**< SMMU_CMDQ_CONS, offset: 0x9C */ __IO uint32_t SMMU_EVENTQ_BASE_LO; /**< SMMU_EVENTQ_BASE (Least Significant 32-bits), offset: 0xA0 */ __IO uint32_t SMMU_EVENTQ_BASE_HI; /**< SMMU_EVENTQ_BASE (Most Significant 32-bits), offset: 0xA4 */ uint8_t RESERVED_5[8]; __IO uint32_t SMMU_EVENTQ_IRQ_CFG0_LO; /**< SMMU_EVENTQ_IRQ_CFG0 (Least Significant 32-bits), offset: 0xB0 */ __IO uint32_t SMMU_EVENTQ_IRQ_CFG0_HI; /**< SMMU_EVENTQ_IRQ_CFG0 (Most Significant 32-bits), offset: 0xB4 */ __IO uint32_t SMMU_EVENTQ_IRQ_CFG1; /**< SMMU_EVENTQ_IRQ_CFG1, offset: 0xB8 */ __IO uint32_t SMMU_EVENTQ_IRQ_CFG2; /**< SMMU_EVENTQ_IRQ_CFG2, offset: 0xBC */ __IO uint32_t SMMU_PRIQ_BASE_LO; /**< SMMU_PRIQ_BASE (Least Significant 32-bits), offset: 0xC0 */ __IO uint32_t SMMU_PRIQ_BASE_HI; /**< SMMU_PRIQ_BASE (Most Significant 32-bits), offset: 0xC4 */ uint8_t RESERVED_6[8]; __IO uint32_t SMMU_PRIQ_IRQ_CFG0_LO; /**< SMMU_PRIQ_IRQ_CFG0 (Least Significant 32-bits), offset: 0xD0 */ __IO uint32_t SMMU_PRIQ_IRQ_CFG0_HI; /**< SMMU_PRIQ_IRQ_CFG0 (Most Significant 32-bits), offset: 0xD4 */ __IO uint32_t SMMU_PRIQ_IRQ_CFG1; /**< SMMU_PRIQ_IRQ_CFG1, offset: 0xD8 */ __IO uint32_t SMMU_PRIQ_IRQ_CFG2; /**< SMMU_PRIQ_IRQ_CFG2, offset: 0xDC */ uint8_t RESERVED_7[80]; __I uint32_t SMMU_MPAMIDR; /**< SMMU_MPAMIDR, offset: 0x130 */ uint8_t RESERVED_8[4]; __IO uint32_t SMMU_GMPAM; /**< SMMU_GMPAM, offset: 0x138 */ __IO uint32_t SMMU_GBPMPAM; /**< SMMU_GBPMPAM, offset: 0x13C */ uint8_t RESERVED_9[3728]; __I uint32_t SMMU_PIDR4; /**< Peripheral ID4, offset: 0xFD0 */ uint32_t SMMU_PIDR5; /**< Peripheral ID5, offset: 0xFD4 */ uint32_t SMMU_PIDR6; /**< Peripheral ID6, offset: 0xFD8 */ uint32_t SMMU_PIDR7; /**< Peripheral ID7, offset: 0xFDC */ __I uint32_t SMMU_PIDR0; /**< Peripheral ID0, offset: 0xFE0 */ __I uint32_t SMMU_PIDR1; /**< Peripheral ID1, offset: 0xFE4 */ __I uint32_t SMMU_PIDR2; /**< Peripheral ID2, offset: 0xFE8 */ __I uint32_t SMMU_PIDR3; /**< Peripheral ID3, offset: 0xFEC */ __I uint32_t SMMU_CIDR0; /**< Component ID0, offset: 0xFF0 */ __I uint32_t SMMU_CIDR1; /**< Component ID1, offset: 0xFF4 */ __I uint32_t SMMU_CIDR2; /**< Component ID2, offset: 0xFF8 */ __I uint32_t SMMU_CIDR3; /**< Component ID3, offset: 0xFFC */ uint8_t RESERVED_10[5120]; __IO uint32_t SMMU_PMCG_EVTYPER0; /**< SMMU_PMCG_EVTYPER0, offset: 0x2400 */ __IO uint32_t SMMU_PMCG_EVTYPER1; /**< SMMU_PMCG_EVTYPER1, offset: 0x2404 */ __IO uint32_t SMMU_PMCG_EVTYPER2; /**< SMMU_PMCG_EVTYPER2, offset: 0x2408 */ __IO uint32_t SMMU_PMCG_EVTYPER3; /**< SMMU_PMCG_EVTYPER3, offset: 0x240C */ __IO uint32_t SMMU_PMCG_EVTYPER4; /**< SMMU_PMCG_EVTYPER4, offset: 0x2410 */ __IO uint32_t SMMU_PMCG_EVTYPER5; /**< SMMU_PMCG_EVTYPER5, offset: 0x2414 */ __IO uint32_t SMMU_PMCG_EVTYPER6; /**< SMMU_PMCG_EVTYPER6, offset: 0x2418 */ __IO uint32_t SMMU_PMCG_EVTYPER7; /**< SMMU_PMCG_EVTYPER7, offset: 0x241C */ __IO uint32_t SMMU_PMCG_EVTYPER8; /**< SMMU_PMCG_EVTYPER8, offset: 0x2420 */ __IO uint32_t SMMU_PMCG_EVTYPER9; /**< SMMU_PMCG_EVTYPER9, offset: 0x2424 */ __IO uint32_t SMMU_PMCG_EVTYPER10; /**< SMMU_PMCG_EVTYPER10, offset: 0x2428 */ __IO uint32_t SMMU_PMCG_EVTYPER11; /**< SMMU_PMCG_EVTYPER11, offset: 0x242C */ __IO uint32_t SMMU_PMCG_EVTYPER12; /**< SMMU_PMCG_EVTYPER12, offset: 0x2430 */ __IO uint32_t SMMU_PMCG_EVTYPER13; /**< SMMU_PMCG_EVTYPER13, offset: 0x2434 */ __IO uint32_t SMMU_PMCG_EVTYPER14; /**< SMMU_PMCG_EVTYPER14, offset: 0x2438 */ __IO uint32_t SMMU_PMCG_EVTYPER15; /**< SMMU_PMCG_EVTYPER15, offset: 0x243C */ uint8_t RESERVED_11[1472]; __IO uint32_t SMMU_PMCG_SMR0; /**< SMMU_PMCG_SMR0, offset: 0x2A00 */ uint8_t RESERVED_12[508]; __IO uint32_t SMMU_PMCG_CNTENSET0; /**< SMMU_PMCG_CNTENSET0, offset: 0x2C00 */ uint8_t RESERVED_13[28]; __IO uint32_t SMMU_PMCG_CNTENCLR0; /**< SMMU_PMCG_CNTENCLR0, offset: 0x2C20 */ uint8_t RESERVED_14[28]; __IO uint32_t SMMU_PMCG_INTENSET0; /**< SMMU_PMCG_INTENSET0, offset: 0x2C40 */ uint8_t RESERVED_15[28]; __IO uint32_t SMMU_PMCG_INTENCLR0; /**< SMMU_PMCG_INTENCLR0, offset: 0x2C60 */ uint8_t RESERVED_16[404]; __IO uint32_t SMMU_PMCG_SCR; /**< SMMU_PMCG_SCR, offset: 0x2DF8 */ uint8_t RESERVED_17[4]; __I uint32_t SMMU_PMCG_CFGR; /**< SMMU_PMCG_CFGR, offset: 0x2E00 */ __IO uint32_t SMMU_PMCG_CR; /**< SMMU_PMCG_CR, offset: 0x2E04 */ uint8_t RESERVED_18[24]; __I uint32_t SMMU_PMCG_CEID0_LO; /**< SMMU_PMCG_CEID0 (Least Significant 32-bits), offset: 0x2E20 */ __I uint32_t SMMU_PMCG_CEID0_HI; /**< SMMU_PMCG_CEID0 (Most Significant 32-bits), offset: 0x2E24 */ __I uint32_t SMMU_PMCG_CEID1_LO; /**< SMMU_PMCG_CEID1 (Least Significant 32-bits), offset: 0x2E28 */ __I uint32_t SMMU_PMCG_CEID1_HI; /**< SMMU_PMCG_CEID1 (Most Significant 32-bits), offset: 0x2E2C */ uint8_t RESERVED_19[32]; __IO uint32_t SMMU_PMCG_IRQ_CTRL; /**< SMMU_PMCG_IRQ_CTRL, offset: 0x2E50 */ __I uint32_t SMMU_PMCG_IRQ_CTRLACK; /**< SMMU_PMCG_IRQ_CTRLACK, offset: 0x2E54 */ uint8_t RESERVED_20[24]; __I uint32_t SMMU_PMCG_AIDR; /**< SMMU_PMCG_AIDR, offset: 0x2E70 */ uint8_t RESERVED_21[324]; __I uint32_t SMMU_PMCG_PMAUTHSTATUS; /**< PMU Authentication Status Register, offset: 0x2FB8 */ __I uint32_t SMMU_PMCG_PMDEVARCH; /**< PMU Device Architecture Register, offset: 0x2FBC */ uint8_t RESERVED_22[12]; __I uint32_t SMMU_PMCG_PMDEVTYPE; /**< PMU Device Type Register, offset: 0x2FCC */ __I uint32_t SMMU_PMCG_PIDR4; /**< PMU Peripheral ID4, offset: 0x2FD0 */ uint32_t SMMU_PMCG_PIDR5; /**< PMU Peripheral ID5, offset: 0x2FD4 */ uint32_t SMMU_PMCG_PIDR6; /**< PMU Peripheral ID6, offset: 0x2FD8 */ uint32_t SMMU_PMCG_PIDR7; /**< PMU Peripheral ID7, offset: 0x2FDC */ __I uint32_t SMMU_PMCG_PIDR0; /**< PMU Peripheral ID0, offset: 0x2FE0 */ __I uint32_t SMMU_PMCG_PIDR1; /**< PMU Peripheral ID1, offset: 0x2FE4 */ __I uint32_t SMMU_PMCG_PIDR2; /**< PMU Peripheral ID2, offset: 0x2FE8 */ __I uint32_t SMMU_PMCG_PIDR3; /**< PMU Peripheral ID3, offset: 0x2FEC */ __I uint32_t SMMU_PMCG_CIDR0; /**< PMU Component ID0, offset: 0x2FF0 */ __I uint32_t SMMU_PMCG_CIDR1; /**< PMU Component ID1, offset: 0x2FF4 */ __I uint32_t SMMU_PMCG_CIDR2; /**< PMU Component ID2, offset: 0x2FF8 */ __I uint32_t SMMU_PMCG_CIDR3; /**< PMU Component ID3, offset: 0x2FFC */ __I uint32_t MPAMF_IDR_LO_NS; /**< MPAMF_IDR_ns (Least Significant 32-bits), offset: 0x3000 */ __I uint32_t MPAMF_IDR_HI_NS; /**< MPAMF_IDR_ns (Most Significant 32-bits), offset: 0x3004 */ uint8_t RESERVED_23[16]; __I uint32_t MPAMF_IIDR_NS; /**< MPAMF_IIDR_ns, offset: 0x3018 */ uint8_t RESERVED_24[4]; __I uint32_t MPAMF_AIDR_NS; /**< MPAMF_AIDR_ns, offset: 0x3020 */ uint8_t RESERVED_25[20]; __I uint32_t MPAMF_CCAP_IDR_NS; /**< MPAMF_CCAP_IDR_ns, offset: 0x3038 */ uint8_t RESERVED_26[68]; __I uint32_t MPAMF_MSMON_IDR_NS; /**< MPAMF_MSMON_IDR_ns, offset: 0x3080 */ uint8_t RESERVED_27[4]; __I uint32_t MPAMF_CSUMON_IDR_NS; /**< MPAMF_CSUMON_IDR_ns, offset: 0x3088 */ uint8_t RESERVED_28[116]; __IO uint32_t MPAMCFG_PART_SEL_NS; /**< MPAMCFG_PART_SEL_ns, offset: 0x3100 */ uint8_t RESERVED_29[4]; __IO uint32_t MPAMCFG_CMAX_NS; /**< MPAMCFG_CMAX_ns, offset: 0x3108 */ uint8_t RESERVED_30[1780]; __IO uint32_t MSMON_CFG_MON_SEL_NS; /**< MSMON_CFG_MON_SEL_ns, offset: 0x3800 */ uint8_t RESERVED_31[4]; __IO uint32_t MSMON_CAPT_EVNT_NS; /**< MSMON_CAPT_EVNT_ns, offset: 0x3808 */ uint8_t RESERVED_32[4]; __IO uint32_t MSMON_CFG_CSU_FLT_NS; /**< MSMON_CFG_CSU_FLT_ns, offset: 0x3810 */ uint8_t RESERVED_33[4]; __IO uint32_t MSMON_CFG_CSU_CTL_NS; /**< MSMON_CFG_CSU_CTL_ns, offset: 0x3818 */ uint8_t RESERVED_34[36]; __IO uint32_t MSMON_CSU_NS; /**< MSMON_CSU_ns, offset: 0x3840 */ uint8_t RESERVED_35[4]; __IO uint32_t MSMON_CSU_CAPTURE_NS; /**< MSMON_CSU_CAPTURE_ns, offset: 0x3848 */ uint8_t RESERVED_36[18356]; __I uint32_t SMMU_S_IDR0; /**< SMMU_S_IDR0, offset: 0x8000 */ __I uint32_t SMMU_S_IDR1; /**< SMMU_S_IDR1, offset: 0x8004 */ uint8_t RESERVED_37[4]; __I uint32_t SMMU_S_IDR3; /**< SMMU_S_IDR3, offset: 0x800C */ __I uint32_t SMMU_S_IDR4; /**< SMMU_S_IDR4, offset: 0x8010 */ uint8_t RESERVED_38[12]; __IO uint32_t SMMU_S_CR0; /**< SMMU_S_CR0, offset: 0x8020 */ __IO uint32_t SMMU_S_CR0ACK; /**< SMMU_S_CR0ACK, offset: 0x8024 */ __IO uint32_t SMMU_S_CR1; /**< SMMU_S_CR1, offset: 0x8028 */ __IO uint32_t SMMU_S_CR2; /**< SMMU_S_CR2, offset: 0x802C */ uint8_t RESERVED_39[12]; __IO uint32_t SMMU_S_INIT; /**< SMMU_S_INIT, offset: 0x803C */ uint8_t RESERVED_40[4]; __IO uint32_t SMMU_S_GBPA; /**< SMMU_S_GBPA, offset: 0x8044 */ __IO uint32_t SMMU_S_AGBPA; /**< SMMU_S_AGBPA, offset: 0x8048 */ uint8_t RESERVED_41[4]; __IO uint32_t SMMU_S_IRQ_CTRL; /**< SMMU_S_IRQ_CTRL, offset: 0x8050 */ __I uint32_t SMMU_S_IRQ_CTRLACK; /**< SMMU_S_IRQ_CTRLACK, offset: 0x8054 */ uint8_t RESERVED_42[8]; __I uint32_t SMMU_S_GERROR; /**< SMMU_S_GERROR, offset: 0x8060 */ __IO uint32_t SMMU_S_GERRORN; /**< SMMU_S_GERRORN, offset: 0x8064 */ __IO uint32_t SMMU_S_GERROR_IRQ_CFG0_LO; /**< SMMU_S_GERROR_IRQ_CFG0 (Least Significant 32-bits), offset: 0x8068 */ __IO uint32_t SMMU_S_GERROR_IRQ_CFG0_HI; /**< SMMU_S_GERROR_IRQ_CFG0 (Most Significant 32-bits), offset: 0x806C */ __IO uint32_t SMMU_S_GERROR_IRQ_CFG1; /**< SMMU_S_GERROR_IRQ_CFG1, offset: 0x8070 */ __IO uint32_t SMMU_S_GERROR_IRQ_CFG2; /**< SMMU_S_GERROR_IRQ_CFG2, offset: 0x8074 */ uint8_t RESERVED_43[8]; __IO uint32_t SMMU_S_STRTAB_BASE_LO; /**< SMMU_S_STRTAB_BASE (Least Significant 32-bits), offset: 0x8080 */ __IO uint32_t SMMU_S_STRTAB_BASE_HI; /**< SMMU_S_STRTAB_BASE (Most Significant 32-bits), offset: 0x8084 */ __IO uint32_t SMMU_S_STRTAB_BASE_CFG; /**< SMMU_S_STRTAB_BASE_CFG, offset: 0x8088 */ uint8_t RESERVED_44[4]; __IO uint32_t SMMU_S_CMDQ_BASE_LO; /**< SMMU_S_CMDQ_BASE (Least Significant 32-bits), offset: 0x8090 */ __IO uint32_t SMMU_S_CMDQ_BASE_HI; /**< SMMU_S_CMDQ_BASE (Most Significant 32-bits), offset: 0x8094 */ __IO uint32_t SMMU_S_CMDQ_PROD; /**< SMMU_S_CMDQ_PROD, offset: 0x8098 */ __IO uint32_t SMMU_S_CMDQ_CONS; /**< SMMU_S_CMDQ_CONS, offset: 0x809C */ __IO uint32_t SMMU_S_EVENTQ_BASE_LO; /**< SMMU_S_EVENTQ_BASE (Least Significant 32-bits), offset: 0x80A0 */ __IO uint32_t SMMU_S_EVENTQ_BASE_HI; /**< SMMU_S_EVENTQ_BASE (Most Significant 32-bits), offset: 0x80A4 */ __IO uint32_t SMMU_S_EVENTQ_PROD; /**< SMMU_S_EVENTQ_PROD, offset: 0x80A8 */ __IO uint32_t SMMU_S_EVENTQ_CONS; /**< SMMU_S_EVENTQ_CONS, offset: 0x80AC */ __IO uint32_t SMMU_S_EVENTQ_IRQ_CFG0_LO; /**< SMMU_S_EVENTQ_IRQ_CFG0 (Least Significant 32-bits), offset: 0x80B0 */ __IO uint32_t SMMU_S_EVENTQ_IRQ_CFG0_HI; /**< SMMU_S_EVENTQ_IRQ_CFG0 (Most Significant 32-bits), offset: 0x80B4 */ __IO uint32_t SMMU_S_EVENTQ_IRQ_CFG1; /**< SMMU_S_EVENTQ_IRQ_CFG1, offset: 0x80B8 */ __IO uint32_t SMMU_S_EVENTQ_IRQ_CFG2; /**< SMMU_S_EVENTQ_IRQ_CFG2, offset: 0x80BC */ uint8_t RESERVED_45[3392]; __IO uint32_t TCU_CTRL; /**< TCU Control Register, offset: 0x8E00 */ __IO uint32_t TCU_QOS; /**< TCU Quality of Service Register, offset: 0x8E04 */ __I uint32_t TCU_CFG; /**< TCU Configuration Information Register, offset: 0x8E08 */ uint8_t RESERVED_46[4]; __I uint32_t TCU_STATUS; /**< TCU Status Information Register, offset: 0x8E10 */ uint8_t RESERVED_47[4]; __IO uint32_t TCU_SCR; /**< TCU Secure Control Register, offset: 0x8E18 */ uint8_t RESERVED_48[4]; __IO uint32_t ITEN; /**< ITEN, offset: 0x8E20 */ __IO uint32_t ITOP_PIU; /**< ITOP_PIU, offset: 0x8E24 */ __IO uint32_t ITOP_TMU; /**< ITOP_TMU, offset: 0x8E28 */ uint8_t RESERVED_49[4]; __I uint32_t ITIN_TMU; /**< ITIN_TMU, offset: 0x8E30 */ __I uint32_t TCU_SYSDISC0; /**< TCU_SYSDISC0, offset: 0x8E34 */ __I uint32_t TCU_SYSDISC1; /**< TCU_SYSDISC2, offset: 0x8E38 */ __I uint32_t TCU_SYSDISC2; /**< TCU_SYSDISC2, offset: 0x8E3C */ __I uint32_t TCU_SYSDISC3; /**< TCU_SYSDISC3, offset: 0x8E40 */ __I uint32_t TCU_SYSDISC4; /**< TCU_SYSDISC4, offset: 0x8E44 */ __I uint32_t TCU_SYSDISC5; /**< TCU_SYSDISC5, offset: 0x8E48 */ __I uint32_t TCU_SYSDISC6; /**< TCU_SYSDISC6, offset: 0x8E4C */ __I uint32_t TCU_SYSDISC7; /**< TCU_SYSDISC7, offset: 0x8E50 */ __I uint32_t TCU_SYSDISC8; /**< TCU_SYSDISC8, offset: 0x8E54 */ __I uint32_t TCU_SYSDISC9; /**< TCU_SYSDISC9, offset: 0x8E58 */ __I uint32_t TCU_SYSDISC10; /**< TCU_SYSDISC10, offset: 0x8E5C */ __I uint32_t TCU_SYSDISC11; /**< TCU_SYSDISC11, offset: 0x8E60 */ __I uint32_t TCU_SYSDISC12; /**< TCU_SYSDISC12, offset: 0x8E64 */ __I uint32_t TCU_SYSDISC13; /**< TCU_SYSDISC13, offset: 0x8E68 */ __I uint32_t TCU_SYSDISC14; /**< TCU_SYSDISC14, offset: 0x8E6C */ __I uint32_t TCU_SYSDISC15; /**< TCU_SYSDISC15, offset: 0x8E70 */ __I uint32_t TCU_SYSDISC16; /**< TCU_SYSDISC16, offset: 0x8E74 */ __I uint32_t TCU_SYSDISC17; /**< TCU_SYSDISC17, offset: 0x8E78 */ uint8_t RESERVED_50[4]; __I uint32_t TCU_ERRFR_LO; /**< TCU Error Feature Register (Least Significant 32-bits), offset: 0x8E80 */ uint32_t TCU_ERRFR_HI; /**< TCU Error Feature Register (Most Significant 32-bits), offset: 0x8E84 */ __IO uint32_t TCU_ERRCTLR_LO; /**< TCU Error Control Register (Least Significant 32-bits), offset: 0x8E88 */ uint32_t TCU_ERRCTLR_HI; /**< TCU Error Control Register (Most Significant 32-bits), offset: 0x8E8C */ __IO uint32_t TCU_ERRSTATUS_LO; /**< TCU Error Record Primary Syndrome Register (Least Significant 32-bits), offset: 0x8E90 */ uint32_t TCU_ERRSTATUS_HI; /**< TCU Error Record Primary Syndrome Register (Most Significant 32-bits), offset: 0x8E94 */ uint8_t RESERVED_51[40]; __IO uint32_t TCU_ERRGEN_LO; /**< TCU Error Generation Register (Least Significant 32-bits), offset: 0x8EC0 */ uint32_t TCU_ERRGEN_HI; /**< TCU Error Generation Register (Most Significant 32-bits), offset: 0x8EC4 */ uint8_t RESERVED_52[312]; __IO uint32_t TCU_NODE_CTRL0; /**< TCU Node Control Register 0, offset: 0x9000 */ __IO uint32_t TCU_NODE_CTRL1; /**< TCU Node Control Register 1, offset: 0x9004 */ __IO uint32_t TCU_NODE_CTRL2; /**< TCU Node Control Register 2, offset: 0x9008 */ __IO uint32_t TCU_NODE_CTRL3; /**< TCU Node Control Register 3, offset: 0x900C */ __IO uint32_t TCU_NODE_CTRL4; /**< TCU Node Control Register 4, offset: 0x9010 */ __IO uint32_t TCU_NODE_CTRL5; /**< TCU Node Control Register 5, offset: 0x9014 */ __IO uint32_t TCU_NODE_CTRL6; /**< TCU Node Control Register 6, offset: 0x9018 */ __IO uint32_t TCU_NODE_CTRL7; /**< TCU Node Control Register 7, offset: 0x901C */ __IO uint32_t TCU_NODE_CTRL8; /**< TCU Node Control Register 8, offset: 0x9020 */ __IO uint32_t TCU_NODE_CTRL9; /**< TCU Node Control Register 9, offset: 0x9024 */ __IO uint32_t TCU_NODE_CTRL10; /**< TCU Node Control Register 10, offset: 0x9028 */ __IO uint32_t TCU_NODE_CTRL11; /**< TCU Node Control Register 11, offset: 0x902C */ __IO uint32_t TCU_NODE_CTRL12; /**< TCU Node Control Register 12, offset: 0x9030 */ __IO uint32_t TCU_NODE_CTRL13; /**< TCU Node Control Register 13, offset: 0x9034 */ uint8_t RESERVED_53[968]; __I uint32_t TCU_NODE_STATUS0; /**< TCU Node Status Register 0, offset: 0x9400 */ __I uint32_t TCU_NODE_STATUS1; /**< TCU Node Status Register 1, offset: 0x9404 */ __I uint32_t TCU_NODE_STATUS2; /**< TCU Node Status Register 2, offset: 0x9408 */ __I uint32_t TCU_NODE_STATUS3; /**< TCU Node Status Register 3, offset: 0x940C */ __I uint32_t TCU_NODE_STATUS4; /**< TCU Node Status Register 4, offset: 0x9410 */ __I uint32_t TCU_NODE_STATUS5; /**< TCU Node Status Register 5, offset: 0x9414 */ __I uint32_t TCU_NODE_STATUS6; /**< TCU Node Status Register 6, offset: 0x9418 */ __I uint32_t TCU_NODE_STATUS7; /**< TCU Node Status Register 7, offset: 0x941C */ __I uint32_t TCU_NODE_STATUS8; /**< TCU Node Status Register 8, offset: 0x9420 */ __I uint32_t TCU_NODE_STATUS9; /**< TCU Node Status Register 9, offset: 0x9424 */ __I uint32_t TCU_NODE_STATUS10; /**< TCU Node Status Register 10, offset: 0x9428 */ __I uint32_t TCU_NODE_STATUS11; /**< TCU Node Status Register 11, offset: 0x942C */ __I uint32_t TCU_NODE_STATUS12; /**< TCU Node Status Register 12, offset: 0x9430 */ __I uint32_t TCU_NODE_STATUS13; /**< TCU Node Status Register 13, offset: 0x9434 */ uint8_t RESERVED_54[968]; __IO uint32_t TCU_WC_S1L0_CMAX; /**< TCU Walk Cache S1L0 Max Capacity Register, offset: 0x9800 */ __IO uint32_t TCU_WC_S1L1_CMAX; /**< TCU Walk Cache S1L1 Max Capacity Register, offset: 0x9804 */ __IO uint32_t TCU_WC_S1L2_CMAX; /**< TCU Walk Cache S1L2 Max Capacity Register, offset: 0x9808 */ __IO uint32_t TCU_WC_S1L3_CMAX; /**< TCU Walk Cache S1L3 Max Capacity Register, offset: 0x980C */ __IO uint32_t TCU_WC_S2L0_CMAX; /**< TCU Walk Cache S2L0 Max Capacity Register, offset: 0x9810 */ __IO uint32_t TCU_WC_S2L1_CMAX; /**< TCU Walk Cache S2L1 Max Capacity Register, offset: 0x9814 */ __IO uint32_t TCU_WC_S2L2_CMAX; /**< TCU Walk Cache S2L2 Max Capacity Register, offset: 0x9818 */ __IO uint32_t TCU_WC_S2L3_CMAX; /**< TCU Walk Cache S2L3 Max Capacity Register, offset: 0x981C */ uint8_t RESERVED_55[6112]; __I uint32_t MPAMF_IDR_LO_S; /**< MPAMF_IDR_s (Least Significant 32-bits), offset: 0xB000 */ __I uint32_t MPAMF_IDR_HI_S; /**< MPAMF_IDR_s (Most Significant 32-bits), offset: 0xB004 */ __I uint32_t MPAMF_SIDR_S; /**< MPAMF_SIDR_s, offset: 0xB008 */ uint8_t RESERVED_56[12]; __I uint32_t MPAMF_IIDR_S; /**< MPAMF_IIDR_s, offset: 0xB018 */ uint8_t RESERVED_57[4]; __I uint32_t MPAMF_AIDR_S; /**< MPAMF_AIDR_s, offset: 0xB020 */ uint8_t RESERVED_58[20]; __I uint32_t MPAMF_CCAP_IDR_S; /**< MPAMF_CCAP_IDR_s, offset: 0xB038 */ uint8_t RESERVED_59[68]; __I uint32_t MPAMF_MSMON_IDR_S; /**< MPAMF_MSMON_IDR_s, offset: 0xB080 */ uint8_t RESERVED_60[4]; __I uint32_t MPAMF_CSUMON_IDR_S; /**< MPAMF_CSUMON_IDR_s, offset: 0xB088 */ uint8_t RESERVED_61[116]; __IO uint32_t MPAMCFG_PART_SEL_S; /**< MPAMCFG_PART_SEL_s, offset: 0xB100 */ uint8_t RESERVED_62[4]; __IO uint32_t MPAMCFG_CMAX_S; /**< MPAMCFG_CMAX_s, offset: 0xB108 */ uint8_t RESERVED_63[1780]; __IO uint32_t MSMON_CFG_MON_SEL_S; /**< MSMON_CFG_MON_SEL_s, offset: 0xB800 */ uint8_t RESERVED_64[4]; __IO uint32_t MSMON_CAPT_EVNT_S; /**< MSMON_CAPT_EVNT_s, offset: 0xB808 */ uint8_t RESERVED_65[4]; __IO uint32_t MSMON_CFG_CSU_FLT_S; /**< MSMON_CFG_CSU_FLT_s, offset: 0xB810 */ uint8_t RESERVED_66[4]; __IO uint32_t MSMON_CFG_CSU_CTL_S; /**< MSMON_CFG_CSU_CTL_s, offset: 0xB818 */ uint8_t RESERVED_67[36]; __IO uint32_t MSMON_CSU_S; /**< MSMON_CSU_s, offset: 0xB840 */ uint8_t RESERVED_68[4]; __IO uint32_t MSMON_CSU_CAPTURE_S; /**< MSMON_CSU_CAPTURE_s, offset: 0xB848 */ uint8_t RESERVED_69[18524]; __IO uint32_t SMMU_EVENTQ_PROD; /**< SMMU_EVENTQ_PROD, offset: 0x100A8 */ __IO uint32_t SMMU_EVENTQ_CONS; /**< SMMU_EVENTQ_CONS, offset: 0x100AC */ uint8_t RESERVED_70[24]; __IO uint32_t SMMU_PRIQ_PROD; /**< SMMU_PRIQ_PROD, offset: 0x100C8 */ __IO uint32_t SMMU_PRIQ_CONS; /**< SMMU_PRIQ_CONS, offset: 0x100CC */ uint8_t RESERVED_71[73520]; __IO uint32_t SMMU_PMCG_EVCNTR0; /**< SMMU_PMCG_EVCNTR0, offset: 0x22000 */ __IO uint32_t SMMU_PMCG_EVCNTR1; /**< SMMU_PMCG_EVCNTR1, offset: 0x22004 */ __IO uint32_t SMMU_PMCG_EVCNTR2; /**< SMMU_PMCG_EVCNTR2, offset: 0x22008 */ __IO uint32_t SMMU_PMCG_EVCNTR3; /**< SMMU_PMCG_EVCNTR3, offset: 0x2200C */ __IO uint32_t SMMU_PMCG_EVCNTR4; /**< SMMU_PMCG_EVCNTR4, offset: 0x22010 */ __IO uint32_t SMMU_PMCG_EVCNTR5; /**< SMMU_PMCG_EVCNTR5, offset: 0x22014 */ __IO uint32_t SMMU_PMCG_EVCNTR6; /**< SMMU_PMCG_EVCNTR6, offset: 0x22018 */ __IO uint32_t SMMU_PMCG_EVCNTR7; /**< SMMU_PMCG_EVCNTR7, offset: 0x2201C */ __IO uint32_t SMMU_PMCG_EVCNTR8; /**< SMMU_PMCG_EVCNTR8, offset: 0x22020 */ __IO uint32_t SMMU_PMCG_EVCNTR9; /**< SMMU_PMCG_EVCNTR9, offset: 0x22024 */ __IO uint32_t SMMU_PMCG_EVCNTR10; /**< SMMU_PMCG_EVCNTR10, offset: 0x22028 */ __IO uint32_t SMMU_PMCG_EVCNTR11; /**< SMMU_PMCG_EVCNTR11, offset: 0x2202C */ __IO uint32_t SMMU_PMCG_EVCNTR12; /**< SMMU_PMCG_EVCNTR12, offset: 0x22030 */ __IO uint32_t SMMU_PMCG_EVCNTR13; /**< SMMU_PMCG_EVCNTR13, offset: 0x22034 */ __IO uint32_t SMMU_PMCG_EVCNTR14; /**< SMMU_PMCG_EVCNTR14, offset: 0x22038 */ __IO uint32_t SMMU_PMCG_EVCNTR15; /**< SMMU_PMCG_EVCNTR15, offset: 0x2203C */ uint8_t RESERVED_72[1472]; __IO uint32_t SMMU_PMCG_SVR0; /**< SMMU_PMCG_SVR0, offset: 0x22600 */ __IO uint32_t SMMU_PMCG_SVR1; /**< SMMU_PMCG_SVR1, offset: 0x22604 */ __IO uint32_t SMMU_PMCG_SVR2; /**< SMMU_PMCG_SVR2, offset: 0x22608 */ __IO uint32_t SMMU_PMCG_SVR3; /**< SMMU_PMCG_SVR3, offset: 0x2260C */ __IO uint32_t SMMU_PMCG_SVR4; /**< SMMU_PMCG_SVR4, offset: 0x22610 */ __IO uint32_t SMMU_PMCG_SVR5; /**< SMMU_PMCG_SVR5, offset: 0x22614 */ __IO uint32_t SMMU_PMCG_SVR6; /**< SMMU_PMCG_SVR6, offset: 0x22618 */ __IO uint32_t SMMU_PMCG_SVR7; /**< SMMU_PMCG_SVR7, offset: 0x2261C */ __IO uint32_t SMMU_PMCG_SVR8; /**< SMMU_PMCG_SVR8, offset: 0x22620 */ __IO uint32_t SMMU_PMCG_SVR9; /**< SMMU_PMCG_SVR9, offset: 0x22624 */ __IO uint32_t SMMU_PMCG_SVR10; /**< SMMU_PMCG_SVR10, offset: 0x22628 */ __IO uint32_t SMMU_PMCG_SVR11; /**< SMMU_PMCG_SVR11, offset: 0x2262C */ __IO uint32_t SMMU_PMCG_SVR12; /**< SMMU_PMCG_SVR12, offset: 0x22630 */ __IO uint32_t SMMU_PMCG_SVR13; /**< SMMU_PMCG_SVR13, offset: 0x22634 */ __IO uint32_t SMMU_PMCG_SVR14; /**< SMMU_PMCG_SVR14, offset: 0x22638 */ __IO uint32_t SMMU_PMCG_SVR15; /**< SMMU_PMCG_SVR15, offset: 0x2263C */ uint8_t RESERVED_73[1600]; __IO uint32_t SMMU_PMCG_OVSCLR0; /**< SMMU_PMCG_OVSCLR0, offset: 0x22C80 */ uint8_t RESERVED_74[60]; __IO uint32_t SMMU_PMCG_OVSSET0; /**< SMMU_PMCG_OVSSET0, offset: 0x22CC0 */ uint8_t RESERVED_75[196]; __O uint32_t SMMU_PMCG_CAPR; /**< SMMU_PMCG_CAPR, offset: 0x22D88 */ } MMU_TCU_Type; /* ---------------------------------------------------------------------------- -- MMU_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MMU_TCU_Register_Masks MMU_TCU Register Masks * @{ */ /*! @name SMMU_IDR0 - SMMU_IDR0 */ /*! @{ */ #define MMU_TCU_SMMU_IDR0_S2P_MASK (0x1U) #define MMU_TCU_SMMU_IDR0_S2P_SHIFT (0U) /*! S2P - S2P */ #define MMU_TCU_SMMU_IDR0_S2P(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_S2P_SHIFT)) & MMU_TCU_SMMU_IDR0_S2P_MASK) #define MMU_TCU_SMMU_IDR0_S1P_MASK (0x2U) #define MMU_TCU_SMMU_IDR0_S1P_SHIFT (1U) /*! S1P - S1P */ #define MMU_TCU_SMMU_IDR0_S1P(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_S1P_SHIFT)) & MMU_TCU_SMMU_IDR0_S1P_MASK) #define MMU_TCU_SMMU_IDR0_TTF_MASK (0xCU) #define MMU_TCU_SMMU_IDR0_TTF_SHIFT (2U) /*! TTF - TTF */ #define MMU_TCU_SMMU_IDR0_TTF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_TTF_SHIFT)) & MMU_TCU_SMMU_IDR0_TTF_MASK) #define MMU_TCU_SMMU_IDR0_COHACC_MASK (0x10U) #define MMU_TCU_SMMU_IDR0_COHACC_SHIFT (4U) /*! COHACC - COHACC */ #define MMU_TCU_SMMU_IDR0_COHACC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_COHACC_SHIFT)) & MMU_TCU_SMMU_IDR0_COHACC_MASK) #define MMU_TCU_SMMU_IDR0_BTM_MASK (0x20U) #define MMU_TCU_SMMU_IDR0_BTM_SHIFT (5U) /*! BTM - BTM */ #define MMU_TCU_SMMU_IDR0_BTM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_BTM_SHIFT)) & MMU_TCU_SMMU_IDR0_BTM_MASK) #define MMU_TCU_SMMU_IDR0_HTTU_MASK (0xC0U) #define MMU_TCU_SMMU_IDR0_HTTU_SHIFT (6U) /*! HTTU - HTTU */ #define MMU_TCU_SMMU_IDR0_HTTU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_HTTU_SHIFT)) & MMU_TCU_SMMU_IDR0_HTTU_MASK) #define MMU_TCU_SMMU_IDR0_DORMHINT_MASK (0x100U) #define MMU_TCU_SMMU_IDR0_DORMHINT_SHIFT (8U) /*! DORMHINT - DORMHINT */ #define MMU_TCU_SMMU_IDR0_DORMHINT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_DORMHINT_SHIFT)) & MMU_TCU_SMMU_IDR0_DORMHINT_MASK) #define MMU_TCU_SMMU_IDR0_HYP_MASK (0x200U) #define MMU_TCU_SMMU_IDR0_HYP_SHIFT (9U) /*! HYP - HYP */ #define MMU_TCU_SMMU_IDR0_HYP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_HYP_SHIFT)) & MMU_TCU_SMMU_IDR0_HYP_MASK) #define MMU_TCU_SMMU_IDR0_ATS_MASK (0x400U) #define MMU_TCU_SMMU_IDR0_ATS_SHIFT (10U) /*! ATS - ATS */ #define MMU_TCU_SMMU_IDR0_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_ATS_SHIFT)) & MMU_TCU_SMMU_IDR0_ATS_MASK) #define MMU_TCU_SMMU_IDR0_NS1ATS_MASK (0x800U) #define MMU_TCU_SMMU_IDR0_NS1ATS_SHIFT (11U) /*! NS1ATS - NS1ATS */ #define MMU_TCU_SMMU_IDR0_NS1ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_NS1ATS_SHIFT)) & MMU_TCU_SMMU_IDR0_NS1ATS_MASK) #define MMU_TCU_SMMU_IDR0_ASID16_MASK (0x1000U) #define MMU_TCU_SMMU_IDR0_ASID16_SHIFT (12U) /*! ASID16 - ASID16 */ #define MMU_TCU_SMMU_IDR0_ASID16(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_ASID16_SHIFT)) & MMU_TCU_SMMU_IDR0_ASID16_MASK) #define MMU_TCU_SMMU_IDR0_MSI_MASK (0x2000U) #define MMU_TCU_SMMU_IDR0_MSI_SHIFT (13U) /*! MSI - MSI */ #define MMU_TCU_SMMU_IDR0_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_MSI_SHIFT)) & MMU_TCU_SMMU_IDR0_MSI_MASK) #define MMU_TCU_SMMU_IDR0_SEV_MASK (0x4000U) #define MMU_TCU_SMMU_IDR0_SEV_SHIFT (14U) /*! SEV - SEV */ #define MMU_TCU_SMMU_IDR0_SEV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_SEV_SHIFT)) & MMU_TCU_SMMU_IDR0_SEV_MASK) #define MMU_TCU_SMMU_IDR0_ATOS_MASK (0x8000U) #define MMU_TCU_SMMU_IDR0_ATOS_SHIFT (15U) /*! ATOS - ATOS */ #define MMU_TCU_SMMU_IDR0_ATOS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_ATOS_SHIFT)) & MMU_TCU_SMMU_IDR0_ATOS_MASK) #define MMU_TCU_SMMU_IDR0_PRI_MASK (0x10000U) #define MMU_TCU_SMMU_IDR0_PRI_SHIFT (16U) /*! PRI - PRI */ #define MMU_TCU_SMMU_IDR0_PRI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_PRI_SHIFT)) & MMU_TCU_SMMU_IDR0_PRI_MASK) #define MMU_TCU_SMMU_IDR0_VMW_MASK (0x20000U) #define MMU_TCU_SMMU_IDR0_VMW_SHIFT (17U) /*! VMW - VMW */ #define MMU_TCU_SMMU_IDR0_VMW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_VMW_SHIFT)) & MMU_TCU_SMMU_IDR0_VMW_MASK) #define MMU_TCU_SMMU_IDR0_VMID16_MASK (0x40000U) #define MMU_TCU_SMMU_IDR0_VMID16_SHIFT (18U) /*! VMID16 - VMID16 */ #define MMU_TCU_SMMU_IDR0_VMID16(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_VMID16_SHIFT)) & MMU_TCU_SMMU_IDR0_VMID16_MASK) #define MMU_TCU_SMMU_IDR0_CD2L_MASK (0x80000U) #define MMU_TCU_SMMU_IDR0_CD2L_SHIFT (19U) /*! CD2L - CD2L */ #define MMU_TCU_SMMU_IDR0_CD2L(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_CD2L_SHIFT)) & MMU_TCU_SMMU_IDR0_CD2L_MASK) #define MMU_TCU_SMMU_IDR0_VATOS_MASK (0x100000U) #define MMU_TCU_SMMU_IDR0_VATOS_SHIFT (20U) /*! VATOS - VATOS */ #define MMU_TCU_SMMU_IDR0_VATOS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_VATOS_SHIFT)) & MMU_TCU_SMMU_IDR0_VATOS_MASK) #define MMU_TCU_SMMU_IDR0_TTENDIAN_MASK (0x600000U) #define MMU_TCU_SMMU_IDR0_TTENDIAN_SHIFT (21U) /*! TTENDIAN - TTENDIAN */ #define MMU_TCU_SMMU_IDR0_TTENDIAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_TTENDIAN_SHIFT)) & MMU_TCU_SMMU_IDR0_TTENDIAN_MASK) #define MMU_TCU_SMMU_IDR0_STALL_MODEL_MASK (0x3000000U) #define MMU_TCU_SMMU_IDR0_STALL_MODEL_SHIFT (24U) /*! STALL_MODEL - STALL_MODEL */ #define MMU_TCU_SMMU_IDR0_STALL_MODEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_STALL_MODEL_SHIFT)) & MMU_TCU_SMMU_IDR0_STALL_MODEL_MASK) #define MMU_TCU_SMMU_IDR0_TERM_MODEL_MASK (0x4000000U) #define MMU_TCU_SMMU_IDR0_TERM_MODEL_SHIFT (26U) /*! TERM_MODEL - TERM_MODEL */ #define MMU_TCU_SMMU_IDR0_TERM_MODEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_TERM_MODEL_SHIFT)) & MMU_TCU_SMMU_IDR0_TERM_MODEL_MASK) #define MMU_TCU_SMMU_IDR0_ST_LEVEL_MASK (0x18000000U) #define MMU_TCU_SMMU_IDR0_ST_LEVEL_SHIFT (27U) /*! ST_LEVEL - ST_LEVEL */ #define MMU_TCU_SMMU_IDR0_ST_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR0_ST_LEVEL_SHIFT)) & MMU_TCU_SMMU_IDR0_ST_LEVEL_MASK) /*! @} */ /*! @name SMMU_IDR1 - SMMU_IDR1 */ /*! @{ */ #define MMU_TCU_SMMU_IDR1_SIDSIZE_MASK (0x3FU) #define MMU_TCU_SMMU_IDR1_SIDSIZE_SHIFT (0U) /*! SIDSIZE - SIDSIZE */ #define MMU_TCU_SMMU_IDR1_SIDSIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_SIDSIZE_SHIFT)) & MMU_TCU_SMMU_IDR1_SIDSIZE_MASK) #define MMU_TCU_SMMU_IDR1_SSIDSIZE_MASK (0x7C0U) #define MMU_TCU_SMMU_IDR1_SSIDSIZE_SHIFT (6U) /*! SSIDSIZE - SSIDSIZE */ #define MMU_TCU_SMMU_IDR1_SSIDSIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_SSIDSIZE_SHIFT)) & MMU_TCU_SMMU_IDR1_SSIDSIZE_MASK) #define MMU_TCU_SMMU_IDR1_PRIQS_MASK (0xF800U) #define MMU_TCU_SMMU_IDR1_PRIQS_SHIFT (11U) /*! PRIQS - PRIQS */ #define MMU_TCU_SMMU_IDR1_PRIQS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_PRIQS_SHIFT)) & MMU_TCU_SMMU_IDR1_PRIQS_MASK) #define MMU_TCU_SMMU_IDR1_EVENTQS_MASK (0x1F0000U) #define MMU_TCU_SMMU_IDR1_EVENTQS_SHIFT (16U) /*! EVENTQS - EVENTQS */ #define MMU_TCU_SMMU_IDR1_EVENTQS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_EVENTQS_SHIFT)) & MMU_TCU_SMMU_IDR1_EVENTQS_MASK) #define MMU_TCU_SMMU_IDR1_CMDQS_MASK (0x3E00000U) #define MMU_TCU_SMMU_IDR1_CMDQS_SHIFT (21U) /*! CMDQS - CMDQS */ #define MMU_TCU_SMMU_IDR1_CMDQS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_CMDQS_SHIFT)) & MMU_TCU_SMMU_IDR1_CMDQS_MASK) #define MMU_TCU_SMMU_IDR1_ATTR_PERMS_OVR_MASK (0x4000000U) #define MMU_TCU_SMMU_IDR1_ATTR_PERMS_OVR_SHIFT (26U) /*! ATTR_PERMS_OVR - ATTR_PERMS_OVR */ #define MMU_TCU_SMMU_IDR1_ATTR_PERMS_OVR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_ATTR_PERMS_OVR_SHIFT)) & MMU_TCU_SMMU_IDR1_ATTR_PERMS_OVR_MASK) #define MMU_TCU_SMMU_IDR1_ATTR_TYPES_OVR_MASK (0x8000000U) #define MMU_TCU_SMMU_IDR1_ATTR_TYPES_OVR_SHIFT (27U) /*! ATTR_TYPES_OVR - ATTR_TYPES_OVR */ #define MMU_TCU_SMMU_IDR1_ATTR_TYPES_OVR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_ATTR_TYPES_OVR_SHIFT)) & MMU_TCU_SMMU_IDR1_ATTR_TYPES_OVR_MASK) #define MMU_TCU_SMMU_IDR1_REL_MASK (0x10000000U) #define MMU_TCU_SMMU_IDR1_REL_SHIFT (28U) /*! REL - REL */ #define MMU_TCU_SMMU_IDR1_REL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_REL_SHIFT)) & MMU_TCU_SMMU_IDR1_REL_MASK) #define MMU_TCU_SMMU_IDR1_QUEUES_PRESET_MASK (0x20000000U) #define MMU_TCU_SMMU_IDR1_QUEUES_PRESET_SHIFT (29U) /*! QUEUES_PRESET - QUEUES_PRESET */ #define MMU_TCU_SMMU_IDR1_QUEUES_PRESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_QUEUES_PRESET_SHIFT)) & MMU_TCU_SMMU_IDR1_QUEUES_PRESET_MASK) #define MMU_TCU_SMMU_IDR1_TABLES_PRESET_MASK (0x40000000U) #define MMU_TCU_SMMU_IDR1_TABLES_PRESET_SHIFT (30U) /*! TABLES_PRESET - TABLES_PRESET */ #define MMU_TCU_SMMU_IDR1_TABLES_PRESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR1_TABLES_PRESET_SHIFT)) & MMU_TCU_SMMU_IDR1_TABLES_PRESET_MASK) /*! @} */ /*! @name SMMU_IDR2 - SMMU_IDR2 */ /*! @{ */ #define MMU_TCU_SMMU_IDR2_BA_VATOS_MASK (0x3FFU) #define MMU_TCU_SMMU_IDR2_BA_VATOS_SHIFT (0U) /*! BA_VATOS - BA_VATOS */ #define MMU_TCU_SMMU_IDR2_BA_VATOS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR2_BA_VATOS_SHIFT)) & MMU_TCU_SMMU_IDR2_BA_VATOS_MASK) /*! @} */ /*! @name SMMU_IDR3 - SMMU_IDR3 */ /*! @{ */ #define MMU_TCU_SMMU_IDR3_HAD_MASK (0x4U) #define MMU_TCU_SMMU_IDR3_HAD_SHIFT (2U) /*! HAD - HAD */ #define MMU_TCU_SMMU_IDR3_HAD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_HAD_SHIFT)) & MMU_TCU_SMMU_IDR3_HAD_MASK) #define MMU_TCU_SMMU_IDR3_PBHA_MASK (0x8U) #define MMU_TCU_SMMU_IDR3_PBHA_SHIFT (3U) /*! PBHA - PBHA */ #define MMU_TCU_SMMU_IDR3_PBHA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_PBHA_SHIFT)) & MMU_TCU_SMMU_IDR3_PBHA_MASK) #define MMU_TCU_SMMU_IDR3_XNX_MASK (0x10U) #define MMU_TCU_SMMU_IDR3_XNX_SHIFT (4U) /*! XNX - XNX */ #define MMU_TCU_SMMU_IDR3_XNX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_XNX_SHIFT)) & MMU_TCU_SMMU_IDR3_XNX_MASK) #define MMU_TCU_SMMU_IDR3_PPS_MASK (0x20U) #define MMU_TCU_SMMU_IDR3_PPS_SHIFT (5U) /*! PPS - PPS */ #define MMU_TCU_SMMU_IDR3_PPS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_PPS_SHIFT)) & MMU_TCU_SMMU_IDR3_PPS_MASK) #define MMU_TCU_SMMU_IDR3_MPAM_MASK (0x80U) #define MMU_TCU_SMMU_IDR3_MPAM_SHIFT (7U) /*! MPAM - MPAM */ #define MMU_TCU_SMMU_IDR3_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_MPAM_SHIFT)) & MMU_TCU_SMMU_IDR3_MPAM_MASK) #define MMU_TCU_SMMU_IDR3_FWB_MASK (0x100U) #define MMU_TCU_SMMU_IDR3_FWB_SHIFT (8U) /*! FWB - FWB */ #define MMU_TCU_SMMU_IDR3_FWB(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_FWB_SHIFT)) & MMU_TCU_SMMU_IDR3_FWB_MASK) #define MMU_TCU_SMMU_IDR3_STT_MASK (0x200U) #define MMU_TCU_SMMU_IDR3_STT_SHIFT (9U) /*! STT - STT */ #define MMU_TCU_SMMU_IDR3_STT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_STT_SHIFT)) & MMU_TCU_SMMU_IDR3_STT_MASK) #define MMU_TCU_SMMU_IDR3_RIL_MASK (0x400U) #define MMU_TCU_SMMU_IDR3_RIL_SHIFT (10U) /*! RIL - RIL */ #define MMU_TCU_SMMU_IDR3_RIL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_RIL_SHIFT)) & MMU_TCU_SMMU_IDR3_RIL_MASK) #define MMU_TCU_SMMU_IDR3_BBML_MASK (0x1800U) #define MMU_TCU_SMMU_IDR3_BBML_SHIFT (11U) /*! BBML - BBML */ #define MMU_TCU_SMMU_IDR3_BBML(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR3_BBML_SHIFT)) & MMU_TCU_SMMU_IDR3_BBML_MASK) /*! @} */ /*! @name SMMU_IDR4 - SMMU_IDR4 */ /*! @{ */ #define MMU_TCU_SMMU_IDR4_IMPDEF_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_IDR4_IMPDEF_SHIFT (0U) /*! IMPDEF - IMPDEF */ #define MMU_TCU_SMMU_IDR4_IMPDEF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR4_IMPDEF_SHIFT)) & MMU_TCU_SMMU_IDR4_IMPDEF_MASK) /*! @} */ /*! @name SMMU_IDR5 - SMMU_IDR5 */ /*! @{ */ #define MMU_TCU_SMMU_IDR5_OAS_MASK (0x7U) #define MMU_TCU_SMMU_IDR5_OAS_SHIFT (0U) /*! OAS - OAS */ #define MMU_TCU_SMMU_IDR5_OAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR5_OAS_SHIFT)) & MMU_TCU_SMMU_IDR5_OAS_MASK) #define MMU_TCU_SMMU_IDR5_GRAN4K_MASK (0x10U) #define MMU_TCU_SMMU_IDR5_GRAN4K_SHIFT (4U) /*! GRAN4K - GRAN4K */ #define MMU_TCU_SMMU_IDR5_GRAN4K(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR5_GRAN4K_SHIFT)) & MMU_TCU_SMMU_IDR5_GRAN4K_MASK) #define MMU_TCU_SMMU_IDR5_GRAN16K_MASK (0x20U) #define MMU_TCU_SMMU_IDR5_GRAN16K_SHIFT (5U) /*! GRAN16K - GRAN16K */ #define MMU_TCU_SMMU_IDR5_GRAN16K(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR5_GRAN16K_SHIFT)) & MMU_TCU_SMMU_IDR5_GRAN16K_MASK) #define MMU_TCU_SMMU_IDR5_GRAN64K_MASK (0x40U) #define MMU_TCU_SMMU_IDR5_GRAN64K_SHIFT (6U) /*! GRAN64K - GRAN64K */ #define MMU_TCU_SMMU_IDR5_GRAN64K(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR5_GRAN64K_SHIFT)) & MMU_TCU_SMMU_IDR5_GRAN64K_MASK) #define MMU_TCU_SMMU_IDR5_VAX_MASK (0xC00U) #define MMU_TCU_SMMU_IDR5_VAX_SHIFT (10U) /*! VAX - VAX */ #define MMU_TCU_SMMU_IDR5_VAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR5_VAX_SHIFT)) & MMU_TCU_SMMU_IDR5_VAX_MASK) #define MMU_TCU_SMMU_IDR5_STALL_MAX_MASK (0xFFFF0000U) #define MMU_TCU_SMMU_IDR5_STALL_MAX_SHIFT (16U) /*! STALL_MAX - STALL_MAX */ #define MMU_TCU_SMMU_IDR5_STALL_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IDR5_STALL_MAX_SHIFT)) & MMU_TCU_SMMU_IDR5_STALL_MAX_MASK) /*! @} */ /*! @name SMMU_IIDR - SMMU_IIDR */ /*! @{ */ #define MMU_TCU_SMMU_IIDR_Implementer_MASK (0xFFFU) #define MMU_TCU_SMMU_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TCU_SMMU_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IIDR_Implementer_SHIFT)) & MMU_TCU_SMMU_IIDR_Implementer_MASK) #define MMU_TCU_SMMU_IIDR_Revision_MASK (0xF000U) #define MMU_TCU_SMMU_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TCU_SMMU_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IIDR_Revision_SHIFT)) & MMU_TCU_SMMU_IIDR_Revision_MASK) #define MMU_TCU_SMMU_IIDR_Variant_MASK (0xF0000U) #define MMU_TCU_SMMU_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TCU_SMMU_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IIDR_Variant_SHIFT)) & MMU_TCU_SMMU_IIDR_Variant_MASK) #define MMU_TCU_SMMU_IIDR_ProductID_MASK (0xFFF00000U) #define MMU_TCU_SMMU_IIDR_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TCU_SMMU_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IIDR_ProductID_SHIFT)) & MMU_TCU_SMMU_IIDR_ProductID_MASK) /*! @} */ /*! @name SMMU_AIDR - SMMU_AIDR */ /*! @{ */ #define MMU_TCU_SMMU_AIDR_ArchMinorRev_MASK (0xFU) #define MMU_TCU_SMMU_AIDR_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TCU_SMMU_AIDR_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_AIDR_ArchMinorRev_SHIFT)) & MMU_TCU_SMMU_AIDR_ArchMinorRev_MASK) #define MMU_TCU_SMMU_AIDR_ArchMajorRev_MASK (0xF0U) #define MMU_TCU_SMMU_AIDR_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TCU_SMMU_AIDR_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_AIDR_ArchMajorRev_SHIFT)) & MMU_TCU_SMMU_AIDR_ArchMajorRev_MASK) /*! @} */ /*! @name SMMU_CR0 - SMMU_CR0 */ /*! @{ */ #define MMU_TCU_SMMU_CR0_SMMUEN_MASK (0x1U) #define MMU_TCU_SMMU_CR0_SMMUEN_SHIFT (0U) /*! SMMUEN - SMMUEN */ #define MMU_TCU_SMMU_CR0_SMMUEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0_SMMUEN_SHIFT)) & MMU_TCU_SMMU_CR0_SMMUEN_MASK) #define MMU_TCU_SMMU_CR0_PRIQEN_MASK (0x2U) #define MMU_TCU_SMMU_CR0_PRIQEN_SHIFT (1U) /*! PRIQEN - PRIQEN */ #define MMU_TCU_SMMU_CR0_PRIQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0_PRIQEN_SHIFT)) & MMU_TCU_SMMU_CR0_PRIQEN_MASK) #define MMU_TCU_SMMU_CR0_EVENTQEN_MASK (0x4U) #define MMU_TCU_SMMU_CR0_EVENTQEN_SHIFT (2U) /*! EVENTQEN - EVENTQEN */ #define MMU_TCU_SMMU_CR0_EVENTQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0_EVENTQEN_SHIFT)) & MMU_TCU_SMMU_CR0_EVENTQEN_MASK) #define MMU_TCU_SMMU_CR0_CMDQEN_MASK (0x8U) #define MMU_TCU_SMMU_CR0_CMDQEN_SHIFT (3U) /*! CMDQEN - CMDQEN */ #define MMU_TCU_SMMU_CR0_CMDQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0_CMDQEN_SHIFT)) & MMU_TCU_SMMU_CR0_CMDQEN_MASK) #define MMU_TCU_SMMU_CR0_ATSCHK_MASK (0x10U) #define MMU_TCU_SMMU_CR0_ATSCHK_SHIFT (4U) /*! ATSCHK - ATSCHK */ #define MMU_TCU_SMMU_CR0_ATSCHK(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0_ATSCHK_SHIFT)) & MMU_TCU_SMMU_CR0_ATSCHK_MASK) #define MMU_TCU_SMMU_CR0_VMW_MASK (0x1C0U) #define MMU_TCU_SMMU_CR0_VMW_SHIFT (6U) /*! VMW - VMW */ #define MMU_TCU_SMMU_CR0_VMW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0_VMW_SHIFT)) & MMU_TCU_SMMU_CR0_VMW_MASK) /*! @} */ /*! @name SMMU_CR0ACK - SMMU_CR0ACK */ /*! @{ */ #define MMU_TCU_SMMU_CR0ACK_SMMUEN_MASK (0x1U) #define MMU_TCU_SMMU_CR0ACK_SMMUEN_SHIFT (0U) /*! SMMUEN - SMMUEN */ #define MMU_TCU_SMMU_CR0ACK_SMMUEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0ACK_SMMUEN_SHIFT)) & MMU_TCU_SMMU_CR0ACK_SMMUEN_MASK) #define MMU_TCU_SMMU_CR0ACK_PRIQEN_MASK (0x2U) #define MMU_TCU_SMMU_CR0ACK_PRIQEN_SHIFT (1U) /*! PRIQEN - PRIQEN */ #define MMU_TCU_SMMU_CR0ACK_PRIQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0ACK_PRIQEN_SHIFT)) & MMU_TCU_SMMU_CR0ACK_PRIQEN_MASK) #define MMU_TCU_SMMU_CR0ACK_EVENTQEN_MASK (0x4U) #define MMU_TCU_SMMU_CR0ACK_EVENTQEN_SHIFT (2U) /*! EVENTQEN - EVENTQEN */ #define MMU_TCU_SMMU_CR0ACK_EVENTQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0ACK_EVENTQEN_SHIFT)) & MMU_TCU_SMMU_CR0ACK_EVENTQEN_MASK) #define MMU_TCU_SMMU_CR0ACK_CMDQEN_MASK (0x8U) #define MMU_TCU_SMMU_CR0ACK_CMDQEN_SHIFT (3U) /*! CMDQEN - CMDQEN */ #define MMU_TCU_SMMU_CR0ACK_CMDQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0ACK_CMDQEN_SHIFT)) & MMU_TCU_SMMU_CR0ACK_CMDQEN_MASK) #define MMU_TCU_SMMU_CR0ACK_ATSCHK_MASK (0x10U) #define MMU_TCU_SMMU_CR0ACK_ATSCHK_SHIFT (4U) /*! ATSCHK - ATSCHK */ #define MMU_TCU_SMMU_CR0ACK_ATSCHK(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0ACK_ATSCHK_SHIFT)) & MMU_TCU_SMMU_CR0ACK_ATSCHK_MASK) #define MMU_TCU_SMMU_CR0ACK_VMW_MASK (0x1C0U) #define MMU_TCU_SMMU_CR0ACK_VMW_SHIFT (6U) /*! VMW - VMW */ #define MMU_TCU_SMMU_CR0ACK_VMW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR0ACK_VMW_SHIFT)) & MMU_TCU_SMMU_CR0ACK_VMW_MASK) /*! @} */ /*! @name SMMU_CR1 - SMMU_CR1 */ /*! @{ */ #define MMU_TCU_SMMU_CR1_QUEUE_IC_MASK (0x3U) #define MMU_TCU_SMMU_CR1_QUEUE_IC_SHIFT (0U) /*! QUEUE_IC - QUEUE_IC */ #define MMU_TCU_SMMU_CR1_QUEUE_IC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR1_QUEUE_IC_SHIFT)) & MMU_TCU_SMMU_CR1_QUEUE_IC_MASK) #define MMU_TCU_SMMU_CR1_QUEUE_OC_MASK (0xCU) #define MMU_TCU_SMMU_CR1_QUEUE_OC_SHIFT (2U) /*! QUEUE_OC - QUEUE_OC */ #define MMU_TCU_SMMU_CR1_QUEUE_OC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR1_QUEUE_OC_SHIFT)) & MMU_TCU_SMMU_CR1_QUEUE_OC_MASK) #define MMU_TCU_SMMU_CR1_QUEUE_SH_MASK (0x30U) #define MMU_TCU_SMMU_CR1_QUEUE_SH_SHIFT (4U) /*! QUEUE_SH - QUEUE_SH */ #define MMU_TCU_SMMU_CR1_QUEUE_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR1_QUEUE_SH_SHIFT)) & MMU_TCU_SMMU_CR1_QUEUE_SH_MASK) #define MMU_TCU_SMMU_CR1_TABLE_IC_MASK (0xC0U) #define MMU_TCU_SMMU_CR1_TABLE_IC_SHIFT (6U) /*! TABLE_IC - TABLE_IC */ #define MMU_TCU_SMMU_CR1_TABLE_IC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR1_TABLE_IC_SHIFT)) & MMU_TCU_SMMU_CR1_TABLE_IC_MASK) #define MMU_TCU_SMMU_CR1_TABLE_OC_MASK (0x300U) #define MMU_TCU_SMMU_CR1_TABLE_OC_SHIFT (8U) /*! TABLE_OC - TABLE_OC */ #define MMU_TCU_SMMU_CR1_TABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR1_TABLE_OC_SHIFT)) & MMU_TCU_SMMU_CR1_TABLE_OC_MASK) #define MMU_TCU_SMMU_CR1_TABLE_SH_MASK (0xC00U) #define MMU_TCU_SMMU_CR1_TABLE_SH_SHIFT (10U) /*! TABLE_SH - TABLE_SH */ #define MMU_TCU_SMMU_CR1_TABLE_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR1_TABLE_SH_SHIFT)) & MMU_TCU_SMMU_CR1_TABLE_SH_MASK) /*! @} */ /*! @name SMMU_CR2 - SMMU_CR2 */ /*! @{ */ #define MMU_TCU_SMMU_CR2_E2H_MASK (0x1U) #define MMU_TCU_SMMU_CR2_E2H_SHIFT (0U) /*! E2H - E2H */ #define MMU_TCU_SMMU_CR2_E2H(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR2_E2H_SHIFT)) & MMU_TCU_SMMU_CR2_E2H_MASK) #define MMU_TCU_SMMU_CR2_RECINVSID_MASK (0x2U) #define MMU_TCU_SMMU_CR2_RECINVSID_SHIFT (1U) /*! RECINVSID - RECINVSID */ #define MMU_TCU_SMMU_CR2_RECINVSID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR2_RECINVSID_SHIFT)) & MMU_TCU_SMMU_CR2_RECINVSID_MASK) #define MMU_TCU_SMMU_CR2_PTM_MASK (0x4U) #define MMU_TCU_SMMU_CR2_PTM_SHIFT (2U) /*! PTM - PTM */ #define MMU_TCU_SMMU_CR2_PTM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CR2_PTM_SHIFT)) & MMU_TCU_SMMU_CR2_PTM_MASK) /*! @} */ /*! @name SMMU_GBPA - SMMU_GBPA */ /*! @{ */ #define MMU_TCU_SMMU_GBPA_MemAttr_MASK (0xFU) #define MMU_TCU_SMMU_GBPA_MemAttr_SHIFT (0U) /*! MemAttr - MemAttr */ #define MMU_TCU_SMMU_GBPA_MemAttr(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_MemAttr_SHIFT)) & MMU_TCU_SMMU_GBPA_MemAttr_MASK) #define MMU_TCU_SMMU_GBPA_MTCFG_MASK (0x10U) #define MMU_TCU_SMMU_GBPA_MTCFG_SHIFT (4U) /*! MTCFG - MTCFG */ #define MMU_TCU_SMMU_GBPA_MTCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_MTCFG_SHIFT)) & MMU_TCU_SMMU_GBPA_MTCFG_MASK) #define MMU_TCU_SMMU_GBPA_ALLOCCFG_MASK (0xF00U) #define MMU_TCU_SMMU_GBPA_ALLOCCFG_SHIFT (8U) /*! ALLOCCFG - ALLOCCFG */ #define MMU_TCU_SMMU_GBPA_ALLOCCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_ALLOCCFG_SHIFT)) & MMU_TCU_SMMU_GBPA_ALLOCCFG_MASK) #define MMU_TCU_SMMU_GBPA_SHCFG_MASK (0x3000U) #define MMU_TCU_SMMU_GBPA_SHCFG_SHIFT (12U) /*! SHCFG - SHCFG */ #define MMU_TCU_SMMU_GBPA_SHCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_SHCFG_SHIFT)) & MMU_TCU_SMMU_GBPA_SHCFG_MASK) #define MMU_TCU_SMMU_GBPA_PRIVCFG_MASK (0x30000U) #define MMU_TCU_SMMU_GBPA_PRIVCFG_SHIFT (16U) /*! PRIVCFG - PRIVCFG */ #define MMU_TCU_SMMU_GBPA_PRIVCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_PRIVCFG_SHIFT)) & MMU_TCU_SMMU_GBPA_PRIVCFG_MASK) #define MMU_TCU_SMMU_GBPA_INSTCFG_MASK (0xC0000U) #define MMU_TCU_SMMU_GBPA_INSTCFG_SHIFT (18U) /*! INSTCFG - INSTCFG */ #define MMU_TCU_SMMU_GBPA_INSTCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_INSTCFG_SHIFT)) & MMU_TCU_SMMU_GBPA_INSTCFG_MASK) #define MMU_TCU_SMMU_GBPA_ABORT_MASK (0x100000U) #define MMU_TCU_SMMU_GBPA_ABORT_SHIFT (20U) /*! ABORT - ABORT */ #define MMU_TCU_SMMU_GBPA_ABORT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_ABORT_SHIFT)) & MMU_TCU_SMMU_GBPA_ABORT_MASK) #define MMU_TCU_SMMU_GBPA_Update_MASK (0x80000000U) #define MMU_TCU_SMMU_GBPA_Update_SHIFT (31U) /*! Update - Update */ #define MMU_TCU_SMMU_GBPA_Update(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPA_Update_SHIFT)) & MMU_TCU_SMMU_GBPA_Update_MASK) /*! @} */ /*! @name SMMU_AGBPA - SMMU_AGBPA */ /*! @{ */ #define MMU_TCU_SMMU_AGBPA_PBHA_MASK (0xFU) #define MMU_TCU_SMMU_AGBPA_PBHA_SHIFT (0U) /*! PBHA - PBHA */ #define MMU_TCU_SMMU_AGBPA_PBHA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_AGBPA_PBHA_SHIFT)) & MMU_TCU_SMMU_AGBPA_PBHA_MASK) #define MMU_TCU_SMMU_AGBPA_Update_MASK (0x80000000U) #define MMU_TCU_SMMU_AGBPA_Update_SHIFT (31U) /*! Update - Update */ #define MMU_TCU_SMMU_AGBPA_Update(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_AGBPA_Update_SHIFT)) & MMU_TCU_SMMU_AGBPA_Update_MASK) /*! @} */ /*! @name SMMU_IRQ_CTRL - SMMU_IRQ_CTRL */ /*! @{ */ #define MMU_TCU_SMMU_IRQ_CTRL_GERROR_IRQEN_MASK (0x1U) #define MMU_TCU_SMMU_IRQ_CTRL_GERROR_IRQEN_SHIFT (0U) /*! GERROR_IRQEN - GERROR_IRQEN */ #define MMU_TCU_SMMU_IRQ_CTRL_GERROR_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IRQ_CTRL_GERROR_IRQEN_SHIFT)) & MMU_TCU_SMMU_IRQ_CTRL_GERROR_IRQEN_MASK) #define MMU_TCU_SMMU_IRQ_CTRL_PRIQ_IRQEN_MASK (0x2U) #define MMU_TCU_SMMU_IRQ_CTRL_PRIQ_IRQEN_SHIFT (1U) /*! PRIQ_IRQEN - PRIQ_IRQEN */ #define MMU_TCU_SMMU_IRQ_CTRL_PRIQ_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IRQ_CTRL_PRIQ_IRQEN_SHIFT)) & MMU_TCU_SMMU_IRQ_CTRL_PRIQ_IRQEN_MASK) #define MMU_TCU_SMMU_IRQ_CTRL_EVENTQ_IRQEN_MASK (0x4U) #define MMU_TCU_SMMU_IRQ_CTRL_EVENTQ_IRQEN_SHIFT (2U) /*! EVENTQ_IRQEN - EVENTQ_IRQEN */ #define MMU_TCU_SMMU_IRQ_CTRL_EVENTQ_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IRQ_CTRL_EVENTQ_IRQEN_SHIFT)) & MMU_TCU_SMMU_IRQ_CTRL_EVENTQ_IRQEN_MASK) /*! @} */ /*! @name SMMU_IRQ_CTRLACK - SMMU_IRQ_CTRLACK */ /*! @{ */ #define MMU_TCU_SMMU_IRQ_CTRLACK_GERROR_IRQEN_MASK (0x1U) #define MMU_TCU_SMMU_IRQ_CTRLACK_GERROR_IRQEN_SHIFT (0U) /*! GERROR_IRQEN - GERROR_IRQEN */ #define MMU_TCU_SMMU_IRQ_CTRLACK_GERROR_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IRQ_CTRLACK_GERROR_IRQEN_SHIFT)) & MMU_TCU_SMMU_IRQ_CTRLACK_GERROR_IRQEN_MASK) #define MMU_TCU_SMMU_IRQ_CTRLACK_PRIQ_IRQEN_MASK (0x2U) #define MMU_TCU_SMMU_IRQ_CTRLACK_PRIQ_IRQEN_SHIFT (1U) /*! PRIQ_IRQEN - PRIQ_IRQEN */ #define MMU_TCU_SMMU_IRQ_CTRLACK_PRIQ_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IRQ_CTRLACK_PRIQ_IRQEN_SHIFT)) & MMU_TCU_SMMU_IRQ_CTRLACK_PRIQ_IRQEN_MASK) #define MMU_TCU_SMMU_IRQ_CTRLACK_EVENTQ_IRQEN_MASK (0x4U) #define MMU_TCU_SMMU_IRQ_CTRLACK_EVENTQ_IRQEN_SHIFT (2U) /*! EVENTQ_IRQEN - EVENTQ_IRQEN */ #define MMU_TCU_SMMU_IRQ_CTRLACK_EVENTQ_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_IRQ_CTRLACK_EVENTQ_IRQEN_SHIFT)) & MMU_TCU_SMMU_IRQ_CTRLACK_EVENTQ_IRQEN_MASK) /*! @} */ /*! @name SMMU_GERROR - SMMU_GERROR */ /*! @{ */ #define MMU_TCU_SMMU_GERROR_CMDQ_ERR_MASK (0x1U) #define MMU_TCU_SMMU_GERROR_CMDQ_ERR_SHIFT (0U) /*! CMDQ_ERR - CMDQ_ERR */ #define MMU_TCU_SMMU_GERROR_CMDQ_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_CMDQ_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_CMDQ_ERR_MASK) #define MMU_TCU_SMMU_GERROR_EVENTQ_ABT_ERR_MASK (0x4U) #define MMU_TCU_SMMU_GERROR_EVENTQ_ABT_ERR_SHIFT (2U) /*! EVENTQ_ABT_ERR - EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_GERROR_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERROR_PRIQ_ABT_ERR_MASK (0x8U) #define MMU_TCU_SMMU_GERROR_PRIQ_ABT_ERR_SHIFT (3U) /*! PRIQ_ABT_ERR - PRIQ_ABT_ERR */ #define MMU_TCU_SMMU_GERROR_PRIQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_PRIQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_PRIQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERROR_MSI_CMDQ_ABT_ERR_MASK (0x10U) #define MMU_TCU_SMMU_GERROR_MSI_CMDQ_ABT_ERR_SHIFT (4U) /*! MSI_CMDQ_ABT_ERR - MSI_CMDQ_ABT_ERR */ #define MMU_TCU_SMMU_GERROR_MSI_CMDQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_MSI_CMDQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_MSI_CMDQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERROR_MSI_EVENTQ_ABT_ERR_MASK (0x20U) #define MMU_TCU_SMMU_GERROR_MSI_EVENTQ_ABT_ERR_SHIFT (5U) /*! MSI_EVENTQ_ABT_ERR - MSI_EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_GERROR_MSI_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_MSI_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_MSI_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERROR_MSI_PRIQ_ABT_ERR_MASK (0x40U) #define MMU_TCU_SMMU_GERROR_MSI_PRIQ_ABT_ERR_SHIFT (6U) /*! MSI_PRIQ_ABT_ERR - MSI_PRIQ_ABT_ERR */ #define MMU_TCU_SMMU_GERROR_MSI_PRIQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_MSI_PRIQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_MSI_PRIQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERROR_MSI_GERROR_ABT_ERR_MASK (0x80U) #define MMU_TCU_SMMU_GERROR_MSI_GERROR_ABT_ERR_SHIFT (7U) /*! MSI_GERROR_ABT_ERR - MSI_GERROR_ABT_ERR */ #define MMU_TCU_SMMU_GERROR_MSI_GERROR_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_MSI_GERROR_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_MSI_GERROR_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERROR_SFM_ERR_MASK (0x100U) #define MMU_TCU_SMMU_GERROR_SFM_ERR_SHIFT (8U) /*! SFM_ERR - SFM_ERR */ #define MMU_TCU_SMMU_GERROR_SFM_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_SFM_ERR_SHIFT)) & MMU_TCU_SMMU_GERROR_SFM_ERR_MASK) /*! @} */ /*! @name SMMU_GERRORN - SMMU_GERRORN */ /*! @{ */ #define MMU_TCU_SMMU_GERRORN_CMDQ_ERR_MASK (0x1U) #define MMU_TCU_SMMU_GERRORN_CMDQ_ERR_SHIFT (0U) /*! CMDQ_ERR - CMDQ_ERR */ #define MMU_TCU_SMMU_GERRORN_CMDQ_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_CMDQ_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_CMDQ_ERR_MASK) #define MMU_TCU_SMMU_GERRORN_EVENTQ_ABT_ERR_MASK (0x4U) #define MMU_TCU_SMMU_GERRORN_EVENTQ_ABT_ERR_SHIFT (2U) /*! EVENTQ_ABT_ERR - EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_GERRORN_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERRORN_PRIQ_ABT_ERR_MASK (0x8U) #define MMU_TCU_SMMU_GERRORN_PRIQ_ABT_ERR_SHIFT (3U) /*! PRIQ_ABT_ERR - PRIQ_ABT_ERR */ #define MMU_TCU_SMMU_GERRORN_PRIQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_PRIQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_PRIQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERRORN_MSI_CMDQ_ABT_ERR_MASK (0x10U) #define MMU_TCU_SMMU_GERRORN_MSI_CMDQ_ABT_ERR_SHIFT (4U) /*! MSI_CMDQ_ABT_ERR - MSI_CMDQ_ABT_ERR */ #define MMU_TCU_SMMU_GERRORN_MSI_CMDQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_MSI_CMDQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_MSI_CMDQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERRORN_MSI_EVENTQ_ABT_ERR_MASK (0x20U) #define MMU_TCU_SMMU_GERRORN_MSI_EVENTQ_ABT_ERR_SHIFT (5U) /*! MSI_EVENTQ_ABT_ERR - MSI_EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_GERRORN_MSI_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_MSI_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_MSI_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERRORN_MSI_PRIQ_ABT_ERR_MASK (0x40U) #define MMU_TCU_SMMU_GERRORN_MSI_PRIQ_ABT_ERR_SHIFT (6U) /*! MSI_PRIQ_ABT_ERR - MSI_PRIQ_ABT_ERR */ #define MMU_TCU_SMMU_GERRORN_MSI_PRIQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_MSI_PRIQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_MSI_PRIQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERRORN_MSI_GERROR_ABT_ERR_MASK (0x80U) #define MMU_TCU_SMMU_GERRORN_MSI_GERROR_ABT_ERR_SHIFT (7U) /*! MSI_GERROR_ABT_ERR - MSI_GERROR_ABT_ERR */ #define MMU_TCU_SMMU_GERRORN_MSI_GERROR_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_MSI_GERROR_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_MSI_GERROR_ABT_ERR_MASK) #define MMU_TCU_SMMU_GERRORN_SFM_ERR_MASK (0x100U) #define MMU_TCU_SMMU_GERRORN_SFM_ERR_SHIFT (8U) /*! SFM_ERR - SFM_ERR */ #define MMU_TCU_SMMU_GERRORN_SFM_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERRORN_SFM_ERR_SHIFT)) & MMU_TCU_SMMU_GERRORN_SFM_ERR_MASK) /*! @} */ /*! @name SMMU_GERROR_IRQ_CFG0_LO - SMMU_GERROR_IRQ_CFG0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG0_LO_ADDR_MASK (0xFFFFFFFCU) #define MMU_TCU_SMMU_GERROR_IRQ_CFG0_LO_ADDR_SHIFT (2U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG0_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_IRQ_CFG0_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_GERROR_IRQ_CFG0_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_GERROR_IRQ_CFG0_HI - SMMU_GERROR_IRQ_CFG0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG0_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_GERROR_IRQ_CFG0_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG0_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_IRQ_CFG0_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_GERROR_IRQ_CFG0_HI_ADDR_MASK) /*! @} */ /*! @name SMMU_GERROR_IRQ_CFG1 - SMMU_GERROR_IRQ_CFG1 */ /*! @{ */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG1_DATA_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_GERROR_IRQ_CFG1_DATA_SHIFT (0U) /*! DATA - DATA */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG1_DATA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_IRQ_CFG1_DATA_SHIFT)) & MMU_TCU_SMMU_GERROR_IRQ_CFG1_DATA_MASK) /*! @} */ /*! @name SMMU_GERROR_IRQ_CFG2 - SMMU_GERROR_IRQ_CFG2 */ /*! @{ */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG2_MemAttr_MASK (0xFU) #define MMU_TCU_SMMU_GERROR_IRQ_CFG2_MemAttr_SHIFT (0U) /*! MemAttr - MemAttr */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG2_MemAttr(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_IRQ_CFG2_MemAttr_SHIFT)) & MMU_TCU_SMMU_GERROR_IRQ_CFG2_MemAttr_MASK) #define MMU_TCU_SMMU_GERROR_IRQ_CFG2_SH_MASK (0x30U) #define MMU_TCU_SMMU_GERROR_IRQ_CFG2_SH_SHIFT (4U) /*! SH - SH */ #define MMU_TCU_SMMU_GERROR_IRQ_CFG2_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GERROR_IRQ_CFG2_SH_SHIFT)) & MMU_TCU_SMMU_GERROR_IRQ_CFG2_SH_MASK) /*! @} */ /*! @name SMMU_STRTAB_BASE_LO - SMMU_STRTAB_BASE (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_STRTAB_BASE_LO_ADDR_MASK (0xFFFFFFC0U) #define MMU_TCU_SMMU_STRTAB_BASE_LO_ADDR_SHIFT (6U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_STRTAB_BASE_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_STRTAB_BASE_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_STRTAB_BASE_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_STRTAB_BASE_HI - SMMU_STRTAB_BASE (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_STRTAB_BASE_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_STRTAB_BASE_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_STRTAB_BASE_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_STRTAB_BASE_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_STRTAB_BASE_HI_ADDR_MASK) #define MMU_TCU_SMMU_STRTAB_BASE_HI_RA_MASK (0x40000000U) #define MMU_TCU_SMMU_STRTAB_BASE_HI_RA_SHIFT (30U) /*! RA - RA */ #define MMU_TCU_SMMU_STRTAB_BASE_HI_RA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_STRTAB_BASE_HI_RA_SHIFT)) & MMU_TCU_SMMU_STRTAB_BASE_HI_RA_MASK) /*! @} */ /*! @name SMMU_STRTAB_BASE_CFG - SMMU_STRTAB_BASE_CFG */ /*! @{ */ #define MMU_TCU_SMMU_STRTAB_BASE_CFG_LOG2SIZE_MASK (0x3FU) #define MMU_TCU_SMMU_STRTAB_BASE_CFG_LOG2SIZE_SHIFT (0U) /*! LOG2SIZE - LOG2SIZE */ #define MMU_TCU_SMMU_STRTAB_BASE_CFG_LOG2SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_STRTAB_BASE_CFG_LOG2SIZE_SHIFT)) & MMU_TCU_SMMU_STRTAB_BASE_CFG_LOG2SIZE_MASK) #define MMU_TCU_SMMU_STRTAB_BASE_CFG_SPLIT_MASK (0x7C0U) #define MMU_TCU_SMMU_STRTAB_BASE_CFG_SPLIT_SHIFT (6U) /*! SPLIT - SPLIT */ #define MMU_TCU_SMMU_STRTAB_BASE_CFG_SPLIT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_STRTAB_BASE_CFG_SPLIT_SHIFT)) & MMU_TCU_SMMU_STRTAB_BASE_CFG_SPLIT_MASK) #define MMU_TCU_SMMU_STRTAB_BASE_CFG_FMT_MASK (0x30000U) #define MMU_TCU_SMMU_STRTAB_BASE_CFG_FMT_SHIFT (16U) /*! FMT - FMT */ #define MMU_TCU_SMMU_STRTAB_BASE_CFG_FMT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_STRTAB_BASE_CFG_FMT_SHIFT)) & MMU_TCU_SMMU_STRTAB_BASE_CFG_FMT_MASK) /*! @} */ /*! @name SMMU_CMDQ_BASE_LO - SMMU_CMDQ_BASE (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_CMDQ_BASE_LO_LOG2SIZE_MASK (0x1FU) #define MMU_TCU_SMMU_CMDQ_BASE_LO_LOG2SIZE_SHIFT (0U) /*! LOG2SIZE - LOG2SIZE */ #define MMU_TCU_SMMU_CMDQ_BASE_LO_LOG2SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CMDQ_BASE_LO_LOG2SIZE_SHIFT)) & MMU_TCU_SMMU_CMDQ_BASE_LO_LOG2SIZE_MASK) #define MMU_TCU_SMMU_CMDQ_BASE_LO_ADDR_MASK (0xFFFFFFE0U) #define MMU_TCU_SMMU_CMDQ_BASE_LO_ADDR_SHIFT (5U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_CMDQ_BASE_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CMDQ_BASE_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_CMDQ_BASE_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_CMDQ_BASE_HI - SMMU_CMDQ_BASE (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_CMDQ_BASE_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_CMDQ_BASE_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_CMDQ_BASE_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CMDQ_BASE_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_CMDQ_BASE_HI_ADDR_MASK) #define MMU_TCU_SMMU_CMDQ_BASE_HI_RA_MASK (0x40000000U) #define MMU_TCU_SMMU_CMDQ_BASE_HI_RA_SHIFT (30U) /*! RA - RA */ #define MMU_TCU_SMMU_CMDQ_BASE_HI_RA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CMDQ_BASE_HI_RA_SHIFT)) & MMU_TCU_SMMU_CMDQ_BASE_HI_RA_MASK) /*! @} */ /*! @name SMMU_CMDQ_PROD - SMMU_CMDQ_PROD */ /*! @{ */ #define MMU_TCU_SMMU_CMDQ_PROD_WR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_CMDQ_PROD_WR_SHIFT (0U) /*! WR - WR */ #define MMU_TCU_SMMU_CMDQ_PROD_WR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CMDQ_PROD_WR_SHIFT)) & MMU_TCU_SMMU_CMDQ_PROD_WR_MASK) /*! @} */ /*! @name SMMU_CMDQ_CONS - SMMU_CMDQ_CONS */ /*! @{ */ #define MMU_TCU_SMMU_CMDQ_CONS_RD_MASK (0xFFFFFU) #define MMU_TCU_SMMU_CMDQ_CONS_RD_SHIFT (0U) /*! RD - RD */ #define MMU_TCU_SMMU_CMDQ_CONS_RD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CMDQ_CONS_RD_SHIFT)) & MMU_TCU_SMMU_CMDQ_CONS_RD_MASK) #define MMU_TCU_SMMU_CMDQ_CONS_ERR_MASK (0x7F000000U) #define MMU_TCU_SMMU_CMDQ_CONS_ERR_SHIFT (24U) /*! ERR - ERR */ #define MMU_TCU_SMMU_CMDQ_CONS_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CMDQ_CONS_ERR_SHIFT)) & MMU_TCU_SMMU_CMDQ_CONS_ERR_MASK) /*! @} */ /*! @name SMMU_EVENTQ_BASE_LO - SMMU_EVENTQ_BASE (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_BASE_LO_LOG2SIZE_MASK (0x1FU) #define MMU_TCU_SMMU_EVENTQ_BASE_LO_LOG2SIZE_SHIFT (0U) /*! LOG2SIZE - LOG2SIZE */ #define MMU_TCU_SMMU_EVENTQ_BASE_LO_LOG2SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_BASE_LO_LOG2SIZE_SHIFT)) & MMU_TCU_SMMU_EVENTQ_BASE_LO_LOG2SIZE_MASK) #define MMU_TCU_SMMU_EVENTQ_BASE_LO_ADDR_MASK (0xFFFFFFE0U) #define MMU_TCU_SMMU_EVENTQ_BASE_LO_ADDR_SHIFT (5U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_EVENTQ_BASE_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_BASE_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_EVENTQ_BASE_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_EVENTQ_BASE_HI - SMMU_EVENTQ_BASE (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_BASE_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_EVENTQ_BASE_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_EVENTQ_BASE_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_BASE_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_EVENTQ_BASE_HI_ADDR_MASK) #define MMU_TCU_SMMU_EVENTQ_BASE_HI_WA_MASK (0x40000000U) #define MMU_TCU_SMMU_EVENTQ_BASE_HI_WA_SHIFT (30U) /*! WA - WA */ #define MMU_TCU_SMMU_EVENTQ_BASE_HI_WA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_BASE_HI_WA_SHIFT)) & MMU_TCU_SMMU_EVENTQ_BASE_HI_WA_MASK) /*! @} */ /*! @name SMMU_EVENTQ_IRQ_CFG0_LO - SMMU_EVENTQ_IRQ_CFG0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_LO_ADDR_MASK (0xFFFFFFFCU) #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_LO_ADDR_SHIFT (2U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_EVENTQ_IRQ_CFG0_HI - SMMU_EVENTQ_IRQ_CFG0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_EVENTQ_IRQ_CFG0_HI_ADDR_MASK) /*! @} */ /*! @name SMMU_EVENTQ_IRQ_CFG1 - SMMU_EVENTQ_IRQ_CFG1 */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG1_DATA_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG1_DATA_SHIFT (0U) /*! DATA - DATA */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG1_DATA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_IRQ_CFG1_DATA_SHIFT)) & MMU_TCU_SMMU_EVENTQ_IRQ_CFG1_DATA_MASK) /*! @} */ /*! @name SMMU_EVENTQ_IRQ_CFG2 - SMMU_EVENTQ_IRQ_CFG2 */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_MemAttr_MASK (0xFU) #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_MemAttr_SHIFT (0U) /*! MemAttr - MemAttr */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_MemAttr(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_MemAttr_SHIFT)) & MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_MemAttr_MASK) #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_SH_MASK (0x30U) #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_SH_SHIFT (4U) /*! SH - SH */ #define MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_SH_SHIFT)) & MMU_TCU_SMMU_EVENTQ_IRQ_CFG2_SH_MASK) /*! @} */ /*! @name SMMU_PRIQ_BASE_LO - SMMU_PRIQ_BASE (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_BASE_LO_LOG2SIZE_MASK (0x1FU) #define MMU_TCU_SMMU_PRIQ_BASE_LO_LOG2SIZE_SHIFT (0U) /*! LOG2SIZE - LOG2SIZE */ #define MMU_TCU_SMMU_PRIQ_BASE_LO_LOG2SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_BASE_LO_LOG2SIZE_SHIFT)) & MMU_TCU_SMMU_PRIQ_BASE_LO_LOG2SIZE_MASK) #define MMU_TCU_SMMU_PRIQ_BASE_LO_ADDR_MASK (0xFFFFFFE0U) #define MMU_TCU_SMMU_PRIQ_BASE_LO_ADDR_SHIFT (5U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_PRIQ_BASE_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_BASE_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_PRIQ_BASE_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_PRIQ_BASE_HI - SMMU_PRIQ_BASE (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_BASE_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_PRIQ_BASE_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_PRIQ_BASE_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_BASE_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_PRIQ_BASE_HI_ADDR_MASK) #define MMU_TCU_SMMU_PRIQ_BASE_HI_WA_MASK (0x40000000U) #define MMU_TCU_SMMU_PRIQ_BASE_HI_WA_SHIFT (30U) /*! WA - WA */ #define MMU_TCU_SMMU_PRIQ_BASE_HI_WA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_BASE_HI_WA_SHIFT)) & MMU_TCU_SMMU_PRIQ_BASE_HI_WA_MASK) /*! @} */ /*! @name SMMU_PRIQ_IRQ_CFG0_LO - SMMU_PRIQ_IRQ_CFG0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG0_LO_ADDR_MASK (0xFFFFFFFCU) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG0_LO_ADDR_SHIFT (2U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG0_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_IRQ_CFG0_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_PRIQ_IRQ_CFG0_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_PRIQ_IRQ_CFG0_HI - SMMU_PRIQ_IRQ_CFG0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG0_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG0_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG0_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_IRQ_CFG0_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_PRIQ_IRQ_CFG0_HI_ADDR_MASK) /*! @} */ /*! @name SMMU_PRIQ_IRQ_CFG1 - SMMU_PRIQ_IRQ_CFG1 */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG1_DATA_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG1_DATA_SHIFT (0U) /*! DATA - DATA */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG1_DATA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_IRQ_CFG1_DATA_SHIFT)) & MMU_TCU_SMMU_PRIQ_IRQ_CFG1_DATA_MASK) /*! @} */ /*! @name SMMU_PRIQ_IRQ_CFG2 - SMMU_PRIQ_IRQ_CFG2 */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_MemAttr_MASK (0xFU) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_MemAttr_SHIFT (0U) /*! MemAttr - MemAttr */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_MemAttr(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_IRQ_CFG2_MemAttr_SHIFT)) & MMU_TCU_SMMU_PRIQ_IRQ_CFG2_MemAttr_MASK) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_SH_MASK (0x30U) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_SH_SHIFT (4U) /*! SH - SH */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_IRQ_CFG2_SH_SHIFT)) & MMU_TCU_SMMU_PRIQ_IRQ_CFG2_SH_MASK) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_LO_MASK (0x80000000U) #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_LO_SHIFT (31U) /*! LO - LO */ #define MMU_TCU_SMMU_PRIQ_IRQ_CFG2_LO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_IRQ_CFG2_LO_SHIFT)) & MMU_TCU_SMMU_PRIQ_IRQ_CFG2_LO_MASK) /*! @} */ /*! @name SMMU_MPAMIDR - SMMU_MPAMIDR */ /*! @{ */ #define MMU_TCU_SMMU_MPAMIDR_PARTID_MAX_MASK (0xFFFFU) #define MMU_TCU_SMMU_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TCU_SMMU_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_MPAMIDR_PARTID_MAX_SHIFT)) & MMU_TCU_SMMU_MPAMIDR_PARTID_MAX_MASK) #define MMU_TCU_SMMU_MPAMIDR_PMG_MAX_MASK (0xFF0000U) #define MMU_TCU_SMMU_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TCU_SMMU_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_MPAMIDR_PMG_MAX_SHIFT)) & MMU_TCU_SMMU_MPAMIDR_PMG_MAX_MASK) /*! @} */ /*! @name SMMU_GMPAM - SMMU_GMPAM */ /*! @{ */ #define MMU_TCU_SMMU_GMPAM_SO_PARTID_MASK (0xFFFFU) #define MMU_TCU_SMMU_GMPAM_SO_PARTID_SHIFT (0U) /*! SO_PARTID - SO_PARTID */ #define MMU_TCU_SMMU_GMPAM_SO_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GMPAM_SO_PARTID_SHIFT)) & MMU_TCU_SMMU_GMPAM_SO_PARTID_MASK) #define MMU_TCU_SMMU_GMPAM_SO_PMG_MASK (0xFF0000U) #define MMU_TCU_SMMU_GMPAM_SO_PMG_SHIFT (16U) /*! SO_PMG - SO_PMG */ #define MMU_TCU_SMMU_GMPAM_SO_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GMPAM_SO_PMG_SHIFT)) & MMU_TCU_SMMU_GMPAM_SO_PMG_MASK) #define MMU_TCU_SMMU_GMPAM_Update_MASK (0x80000000U) #define MMU_TCU_SMMU_GMPAM_Update_SHIFT (31U) /*! Update - Update */ #define MMU_TCU_SMMU_GMPAM_Update(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GMPAM_Update_SHIFT)) & MMU_TCU_SMMU_GMPAM_Update_MASK) /*! @} */ /*! @name SMMU_GBPMPAM - SMMU_GBPMPAM */ /*! @{ */ #define MMU_TCU_SMMU_GBPMPAM_GBP_PARTID_MASK (0xFFFFU) #define MMU_TCU_SMMU_GBPMPAM_GBP_PARTID_SHIFT (0U) /*! GBP_PARTID - GBP_PARTID */ #define MMU_TCU_SMMU_GBPMPAM_GBP_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPMPAM_GBP_PARTID_SHIFT)) & MMU_TCU_SMMU_GBPMPAM_GBP_PARTID_MASK) #define MMU_TCU_SMMU_GBPMPAM_GBP_PMG_MASK (0xFF0000U) #define MMU_TCU_SMMU_GBPMPAM_GBP_PMG_SHIFT (16U) /*! GBP_PMG - GBP_PMG */ #define MMU_TCU_SMMU_GBPMPAM_GBP_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPMPAM_GBP_PMG_SHIFT)) & MMU_TCU_SMMU_GBPMPAM_GBP_PMG_MASK) #define MMU_TCU_SMMU_GBPMPAM_Update_MASK (0x80000000U) #define MMU_TCU_SMMU_GBPMPAM_Update_SHIFT (31U) /*! Update - Update */ #define MMU_TCU_SMMU_GBPMPAM_Update(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_GBPMPAM_Update_SHIFT)) & MMU_TCU_SMMU_GBPMPAM_Update_MASK) /*! @} */ /*! @name SMMU_PIDR4 - Peripheral ID4 */ /*! @{ */ #define MMU_TCU_SMMU_PIDR4_DES_2_MASK (0xFU) #define MMU_TCU_SMMU_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TCU_SMMU_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR4_DES_2_SHIFT)) & MMU_TCU_SMMU_PIDR4_DES_2_MASK) #define MMU_TCU_SMMU_PIDR4_SIZE_MASK (0xF0U) #define MMU_TCU_SMMU_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TCU_SMMU_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR4_SIZE_SHIFT)) & MMU_TCU_SMMU_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PIDR0 - Peripheral ID0 */ /*! @{ */ #define MMU_TCU_SMMU_PIDR0_PART_0_MASK (0xFFU) #define MMU_TCU_SMMU_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TCU_SMMU_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR0_PART_0_SHIFT)) & MMU_TCU_SMMU_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PIDR1 - Peripheral ID1 */ /*! @{ */ #define MMU_TCU_SMMU_PIDR1_PART_1_MASK (0xFU) #define MMU_TCU_SMMU_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TCU_SMMU_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR1_PART_1_SHIFT)) & MMU_TCU_SMMU_PIDR1_PART_1_MASK) #define MMU_TCU_SMMU_PIDR1_DES_0_MASK (0xF0U) #define MMU_TCU_SMMU_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TCU_SMMU_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR1_DES_0_SHIFT)) & MMU_TCU_SMMU_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PIDR2 - Peripheral ID2 */ /*! @{ */ #define MMU_TCU_SMMU_PIDR2_DES_1_MASK (0x7U) #define MMU_TCU_SMMU_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TCU_SMMU_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR2_DES_1_SHIFT)) & MMU_TCU_SMMU_PIDR2_DES_1_MASK) #define MMU_TCU_SMMU_PIDR2_JEDEC_MASK (0x8U) #define MMU_TCU_SMMU_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TCU_SMMU_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR2_JEDEC_SHIFT)) & MMU_TCU_SMMU_PIDR2_JEDEC_MASK) #define MMU_TCU_SMMU_PIDR2_REVISION_MASK (0xF0U) #define MMU_TCU_SMMU_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TCU_SMMU_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR2_REVISION_SHIFT)) & MMU_TCU_SMMU_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PIDR3 - Peripheral ID3 */ /*! @{ */ #define MMU_TCU_SMMU_PIDR3_CMOD_MASK (0xFU) #define MMU_TCU_SMMU_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TCU_SMMU_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR3_CMOD_SHIFT)) & MMU_TCU_SMMU_PIDR3_CMOD_MASK) #define MMU_TCU_SMMU_PIDR3_REVAND_MASK (0xF0U) #define MMU_TCU_SMMU_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TCU_SMMU_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PIDR3_REVAND_SHIFT)) & MMU_TCU_SMMU_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_CIDR0 - Component ID0 */ /*! @{ */ #define MMU_TCU_SMMU_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TCU_SMMU_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CIDR0_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR1 - Component ID1 */ /*! @{ */ #define MMU_TCU_SMMU_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TCU_SMMU_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CIDR1_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_CIDR1_PREAMBLE_MASK) #define MMU_TCU_SMMU_CIDR1_CLASS_MASK (0xF0U) #define MMU_TCU_SMMU_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TCU_SMMU_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CIDR1_CLASS_SHIFT)) & MMU_TCU_SMMU_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_CIDR2 - Component ID2 */ /*! @{ */ #define MMU_TCU_SMMU_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TCU_SMMU_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CIDR2_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_CIDR3 - Component ID3 */ /*! @{ */ #define MMU_TCU_SMMU_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TCU_SMMU_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_CIDR3_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER0 - SMMU_PMCG_EVTYPER0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER0_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER0_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER0_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER0_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER0_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK (0x20000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT (29U) /*! FILTER_SID_SPAN - FILTER_SID_SPAN */ #define MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SID_SPAN_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK (0x40000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT (30U) /*! FILTER_SEC_SID - FILTER_SEC_SID */ #define MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER0_FILTER_SEC_SID_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER0_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER0_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER0_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER0_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER1 - SMMU_PMCG_EVTYPER1 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER1_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER1_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER1_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER1_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER1_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER1_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER1_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER1_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER1_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER2 - SMMU_PMCG_EVTYPER2 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER2_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER2_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER2_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER2_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER2_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER2_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER2_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER2_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER2_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER3 - SMMU_PMCG_EVTYPER3 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER3_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER3_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER3_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER3_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER3_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER3_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER3_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER3_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER3_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER4 - SMMU_PMCG_EVTYPER4 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER4_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER4_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER4_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER4_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER4_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER4_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER4_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER4_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER4_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER5 - SMMU_PMCG_EVTYPER5 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER5_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER5_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER5_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER5_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER5_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER5_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER5_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER5_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER5_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER6 - SMMU_PMCG_EVTYPER6 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER6_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER6_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER6_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER6_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER6_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER6_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER6_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER6_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER6_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER7 - SMMU_PMCG_EVTYPER7 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER7_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER7_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER7_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER7_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER7_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER7_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER7_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER7_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER7_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER8 - SMMU_PMCG_EVTYPER8 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER8_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER8_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER8_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER8_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER8_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER8_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER8_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER8_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER8_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER9 - SMMU_PMCG_EVTYPER9 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER9_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER9_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER9_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER9_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER9_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER9_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER9_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER9_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER9_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER10 - SMMU_PMCG_EVTYPER10 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER10_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER10_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER10_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER10_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER10_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER10_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER10_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER10_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER10_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER11 - SMMU_PMCG_EVTYPER11 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER11_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER11_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER11_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER11_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER11_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER11_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER11_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER11_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER11_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER12 - SMMU_PMCG_EVTYPER12 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER12_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER12_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER12_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER12_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER12_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER12_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER12_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER12_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER12_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER13 - SMMU_PMCG_EVTYPER13 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER13_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER13_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER13_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER13_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER13_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER13_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER13_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER13_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER13_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER14 - SMMU_PMCG_EVTYPER14 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER14_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER14_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER14_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER14_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER14_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER14_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER14_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER14_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER14_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_EVTYPER15 - SMMU_PMCG_EVTYPER15 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVTYPER15_EVNT_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_EVTYPER15_EVNT_SHIFT (0U) /*! EVNT - EVNT */ #define MMU_TCU_SMMU_PMCG_EVTYPER15_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER15_EVNT_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER15_EVNT_MASK) #define MMU_TCU_SMMU_PMCG_EVTYPER15_OVFCAP_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT (31U) /*! OVFCAP - OVFCAP */ #define MMU_TCU_SMMU_PMCG_EVTYPER15_OVFCAP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVTYPER15_OVFCAP_SHIFT)) & MMU_TCU_SMMU_PMCG_EVTYPER15_OVFCAP_MASK) /*! @} */ /*! @name SMMU_PMCG_SMR0 - SMMU_PMCG_SMR0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SMR0_STREAMID_MASK (0xFFFFFFU) #define MMU_TCU_SMMU_PMCG_SMR0_STREAMID_SHIFT (0U) /*! STREAMID - STREAMID */ #define MMU_TCU_SMMU_PMCG_SMR0_STREAMID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SMR0_STREAMID_SHIFT)) & MMU_TCU_SMMU_PMCG_SMR0_STREAMID_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENSET0 - SMMU_PMCG_CNTENSET0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CNTENSET0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TCU_SMMU_PMCG_CNTENSET0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CNTENSET0_CNTEN_SHIFT)) & MMU_TCU_SMMU_PMCG_CNTENSET0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_CNTENCLR0 - SMMU_PMCG_CNTENCLR0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CNTENCLR0_CNTEN_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT (0U) /*! CNTEN - CNTEN */ #define MMU_TCU_SMMU_PMCG_CNTENCLR0_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CNTENCLR0_CNTEN_SHIFT)) & MMU_TCU_SMMU_PMCG_CNTENCLR0_CNTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENSET0 - SMMU_PMCG_INTENSET0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_INTENSET0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TCU_SMMU_PMCG_INTENSET0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_INTENSET0_INTEN_SHIFT)) & MMU_TCU_SMMU_PMCG_INTENSET0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_INTENCLR0 - SMMU_PMCG_INTENCLR0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_INTENCLR0_INTEN_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define MMU_TCU_SMMU_PMCG_INTENCLR0_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_INTENCLR0_INTEN_SHIFT)) & MMU_TCU_SMMU_PMCG_INTENCLR0_INTEN_MASK) /*! @} */ /*! @name SMMU_PMCG_SCR - SMMU_PMCG_SCR */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SCR_SO_MASK (0x1U) #define MMU_TCU_SMMU_PMCG_SCR_SO_SHIFT (0U) /*! SO - SO */ #define MMU_TCU_SMMU_PMCG_SCR_SO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SCR_SO_SHIFT)) & MMU_TCU_SMMU_PMCG_SCR_SO_MASK) #define MMU_TCU_SMMU_PMCG_SCR_NSRA_MASK (0x2U) #define MMU_TCU_SMMU_PMCG_SCR_NSRA_SHIFT (1U) /*! NSRA - NSRA */ #define MMU_TCU_SMMU_PMCG_SCR_NSRA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SCR_NSRA_SHIFT)) & MMU_TCU_SMMU_PMCG_SCR_NSRA_MASK) #define MMU_TCU_SMMU_PMCG_SCR_NSMSI_MASK (0x4U) #define MMU_TCU_SMMU_PMCG_SCR_NSMSI_SHIFT (2U) /*! NSMSI - NSMSI */ #define MMU_TCU_SMMU_PMCG_SCR_NSMSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SCR_NSMSI_SHIFT)) & MMU_TCU_SMMU_PMCG_SCR_NSMSI_MASK) #define MMU_TCU_SMMU_PMCG_SCR_READS_AS_ONE_MASK (0x80000000U) #define MMU_TCU_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT (31U) /*! READS_AS_ONE - READS_AS_ONE */ #define MMU_TCU_SMMU_PMCG_SCR_READS_AS_ONE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SCR_READS_AS_ONE_SHIFT)) & MMU_TCU_SMMU_PMCG_SCR_READS_AS_ONE_MASK) /*! @} */ /*! @name SMMU_PMCG_CFGR - SMMU_PMCG_CFGR */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CFGR_NCTR_MASK (0x3FU) #define MMU_TCU_SMMU_PMCG_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define MMU_TCU_SMMU_PMCG_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CFGR_NCTR_SHIFT)) & MMU_TCU_SMMU_PMCG_CFGR_NCTR_MASK) #define MMU_TCU_SMMU_PMCG_CFGR_SIZE_MASK (0x3F00U) #define MMU_TCU_SMMU_PMCG_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define MMU_TCU_SMMU_PMCG_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CFGR_SIZE_SHIFT)) & MMU_TCU_SMMU_PMCG_CFGR_SIZE_MASK) #define MMU_TCU_SMMU_PMCG_CFGR_RELOC_CTRS_MASK (0x100000U) #define MMU_TCU_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT (20U) /*! RELOC_CTRS - RELOC_CTRS */ #define MMU_TCU_SMMU_PMCG_CFGR_RELOC_CTRS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CFGR_RELOC_CTRS_SHIFT)) & MMU_TCU_SMMU_PMCG_CFGR_RELOC_CTRS_MASK) #define MMU_TCU_SMMU_PMCG_CFGR_MSI_MASK (0x200000U) #define MMU_TCU_SMMU_PMCG_CFGR_MSI_SHIFT (21U) /*! MSI - MSI */ #define MMU_TCU_SMMU_PMCG_CFGR_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CFGR_MSI_SHIFT)) & MMU_TCU_SMMU_PMCG_CFGR_MSI_MASK) #define MMU_TCU_SMMU_PMCG_CFGR_CAPTURE_MASK (0x400000U) #define MMU_TCU_SMMU_PMCG_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define MMU_TCU_SMMU_PMCG_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CFGR_CAPTURE_SHIFT)) & MMU_TCU_SMMU_PMCG_CFGR_CAPTURE_MASK) #define MMU_TCU_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK (0x800000U) #define MMU_TCU_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT (23U) /*! SID_FILTER_TYPE - SID_FILTER_TYPE */ #define MMU_TCU_SMMU_PMCG_CFGR_SID_FILTER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CFGR_SID_FILTER_TYPE_SHIFT)) & MMU_TCU_SMMU_PMCG_CFGR_SID_FILTER_TYPE_MASK) #define MMU_TCU_SMMU_PMCG_CFGR_MPAM_MASK (0x1000000U) #define MMU_TCU_SMMU_PMCG_CFGR_MPAM_SHIFT (24U) /*! MPAM - MPAM */ #define MMU_TCU_SMMU_PMCG_CFGR_MPAM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CFGR_MPAM_SHIFT)) & MMU_TCU_SMMU_PMCG_CFGR_MPAM_MASK) /*! @} */ /*! @name SMMU_PMCG_CR - SMMU_PMCG_CR */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CR_E_MASK (0x1U) #define MMU_TCU_SMMU_PMCG_CR_E_SHIFT (0U) /*! E - E */ #define MMU_TCU_SMMU_PMCG_CR_E(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CR_E_SHIFT)) & MMU_TCU_SMMU_PMCG_CR_E_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_LO - SMMU_PMCG_CEID0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CEID0_LO_N_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_CEID0_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TCU_SMMU_PMCG_CEID0_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CEID0_LO_N_SHIFT)) & MMU_TCU_SMMU_PMCG_CEID0_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID0_HI - SMMU_PMCG_CEID0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CEID0_HI_N_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_CEID0_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TCU_SMMU_PMCG_CEID0_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CEID0_HI_N_SHIFT)) & MMU_TCU_SMMU_PMCG_CEID0_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_LO - SMMU_PMCG_CEID1 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CEID1_LO_N_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_CEID1_LO_N_SHIFT (0U) /*! N - N */ #define MMU_TCU_SMMU_PMCG_CEID1_LO_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CEID1_LO_N_SHIFT)) & MMU_TCU_SMMU_PMCG_CEID1_LO_N_MASK) /*! @} */ /*! @name SMMU_PMCG_CEID1_HI - SMMU_PMCG_CEID1 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CEID1_HI_N_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_CEID1_HI_N_SHIFT (0U) /*! N - N */ #define MMU_TCU_SMMU_PMCG_CEID1_HI_N(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CEID1_HI_N_SHIFT)) & MMU_TCU_SMMU_PMCG_CEID1_HI_N_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRL - SMMU_PMCG_IRQ_CTRL */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK (0x1U) #define MMU_TCU_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TCU_SMMU_PMCG_IRQ_CTRL_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_IRQ_CTRL_IRQEN_SHIFT)) & MMU_TCU_SMMU_PMCG_IRQ_CTRL_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_IRQ_CTRLACK - SMMU_PMCG_IRQ_CTRLACK */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK (0x1U) #define MMU_TCU_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT (0U) /*! IRQEN - IRQEN */ #define MMU_TCU_SMMU_PMCG_IRQ_CTRLACK_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_IRQ_CTRLACK_IRQEN_SHIFT)) & MMU_TCU_SMMU_PMCG_IRQ_CTRLACK_IRQEN_MASK) /*! @} */ /*! @name SMMU_PMCG_AIDR - SMMU_PMCG_AIDR */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_AIDR_ARCHMINORREV_MASK (0xFU) #define MMU_TCU_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT (0U) /*! ARCHMINORREV - ARCHMINORREV */ #define MMU_TCU_SMMU_PMCG_AIDR_ARCHMINORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_AIDR_ARCHMINORREV_SHIFT)) & MMU_TCU_SMMU_PMCG_AIDR_ARCHMINORREV_MASK) #define MMU_TCU_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK (0xF0U) #define MMU_TCU_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT (4U) /*! ARCHMAJORREV - ARCHMAJORREV */ #define MMU_TCU_SMMU_PMCG_AIDR_ARCHMAJORREV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_AIDR_ARCHMAJORREV_SHIFT)) & MMU_TCU_SMMU_PMCG_AIDR_ARCHMAJORREV_MASK) /*! @} */ /*! @name SMMU_PMCG_PMAUTHSTATUS - PMU Authentication Status Register */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK (0x1U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSE_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSE_MASK) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK (0x2U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSI_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSI_MASK) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK (0x4U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNE_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNE_MASK) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK (0x8U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNI_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_NSNI_MASK) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SE_MASK (0x10U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SE_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SE_MASK) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SI_MASK (0x20U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SI_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SI_MASK) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK (0x40U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNE_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNE_MASK) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK (0x80U) #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNI_SHIFT)) & MMU_TCU_SMMU_PMCG_PMAUTHSTATUS_SNI_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVARCH - PMU Device Architecture Register */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHID_SHIFT)) & MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHID_MASK) #define MMU_TCU_SMMU_PMCG_PMDEVARCH_REVISION_MASK (0xF0000U) #define MMU_TCU_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define MMU_TCU_SMMU_PMCG_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMDEVARCH_REVISION_SHIFT)) & MMU_TCU_SMMU_PMCG_PMDEVARCH_REVISION_MASK) #define MMU_TCU_SMMU_PMCG_PMDEVARCH_PRESENT_MASK (0x100000U) #define MMU_TCU_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define MMU_TCU_SMMU_PMCG_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMDEVARCH_PRESENT_SHIFT)) & MMU_TCU_SMMU_PMCG_PMDEVARCH_PRESENT_MASK) #define MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHITECT_SHIFT)) & MMU_TCU_SMMU_PMCG_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name SMMU_PMCG_PMDEVTYPE - PMU Device Type Register */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PMDEVTYPE_CLS_MASK (0xFU) #define MMU_TCU_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT (0U) /*! CLS - CLS */ #define MMU_TCU_SMMU_PMCG_PMDEVTYPE_CLS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMDEVTYPE_CLS_SHIFT)) & MMU_TCU_SMMU_PMCG_PMDEVTYPE_CLS_MASK) #define MMU_TCU_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK (0xF0U) #define MMU_TCU_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT (4U) /*! SUB_TYPE - SUB_TYPE */ #define MMU_TCU_SMMU_PMCG_PMDEVTYPE_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_SHIFT)) & MMU_TCU_SMMU_PMCG_PMDEVTYPE_SUB_TYPE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR4 - PMU Peripheral ID4 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PIDR4_DES_2_MASK (0xFU) #define MMU_TCU_SMMU_PMCG_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define MMU_TCU_SMMU_PMCG_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR4_DES_2_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR4_DES_2_MASK) #define MMU_TCU_SMMU_PMCG_PIDR4_SIZE_MASK (0xF0U) #define MMU_TCU_SMMU_PMCG_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define MMU_TCU_SMMU_PMCG_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR4_SIZE_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR4_SIZE_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR0 - PMU Peripheral ID0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PIDR0_PART_0_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define MMU_TCU_SMMU_PMCG_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR0_PART_0_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR0_PART_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR1 - PMU Peripheral ID1 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PIDR1_PART_1_MASK (0xFU) #define MMU_TCU_SMMU_PMCG_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define MMU_TCU_SMMU_PMCG_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR1_PART_1_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR1_PART_1_MASK) #define MMU_TCU_SMMU_PMCG_PIDR1_DES_0_MASK (0xF0U) #define MMU_TCU_SMMU_PMCG_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define MMU_TCU_SMMU_PMCG_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR1_DES_0_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR1_DES_0_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR2 - PMU Peripheral ID2 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PIDR2_DES_1_MASK (0x7U) #define MMU_TCU_SMMU_PMCG_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define MMU_TCU_SMMU_PMCG_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR2_DES_1_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR2_DES_1_MASK) #define MMU_TCU_SMMU_PMCG_PIDR2_JEDEC_MASK (0x8U) #define MMU_TCU_SMMU_PMCG_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define MMU_TCU_SMMU_PMCG_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR2_JEDEC_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR2_JEDEC_MASK) #define MMU_TCU_SMMU_PMCG_PIDR2_REVISION_MASK (0xF0U) #define MMU_TCU_SMMU_PMCG_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define MMU_TCU_SMMU_PMCG_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR2_REVISION_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR2_REVISION_MASK) /*! @} */ /*! @name SMMU_PMCG_PIDR3 - PMU Peripheral ID3 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_PIDR3_CMOD_MASK (0xFU) #define MMU_TCU_SMMU_PMCG_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define MMU_TCU_SMMU_PMCG_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR3_CMOD_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR3_CMOD_MASK) #define MMU_TCU_SMMU_PMCG_PIDR3_REVAND_MASK (0xF0U) #define MMU_TCU_SMMU_PMCG_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define MMU_TCU_SMMU_PMCG_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_PIDR3_REVAND_SHIFT)) & MMU_TCU_SMMU_PMCG_PIDR3_REVAND_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR0 - PMU Component ID0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CIDR0_PREAMBLE_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_PMCG_CIDR0_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CIDR0_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_PMCG_CIDR0_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR1 - PMU Component ID1 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CIDR1_PREAMBLE_MASK (0xFU) #define MMU_TCU_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_PMCG_CIDR1_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CIDR1_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_PMCG_CIDR1_PREAMBLE_MASK) #define MMU_TCU_SMMU_PMCG_CIDR1_CLASS_MASK (0xF0U) #define MMU_TCU_SMMU_PMCG_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define MMU_TCU_SMMU_PMCG_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CIDR1_CLASS_SHIFT)) & MMU_TCU_SMMU_PMCG_CIDR1_CLASS_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR2 - PMU Component ID2 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CIDR2_PREAMBLE_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_PMCG_CIDR2_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CIDR2_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_PMCG_CIDR2_PREAMBLE_MASK) /*! @} */ /*! @name SMMU_PMCG_CIDR3 - PMU Component ID3 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CIDR3_PREAMBLE_MASK (0xFFU) #define MMU_TCU_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT (0U) /*! PREAMBLE - PREAMBLE */ #define MMU_TCU_SMMU_PMCG_CIDR3_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CIDR3_PREAMBLE_SHIFT)) & MMU_TCU_SMMU_PMCG_CIDR3_PREAMBLE_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_NS - MPAMF_IDR_ns (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_MPAMF_IDR_LO_NS_PARTID_MAX_MASK (0xFFFFU) #define MMU_TCU_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TCU_MPAMF_IDR_LO_NS_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_PARTID_MAX_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_PARTID_MAX_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_PMG_MAX_MASK (0xFF0000U) #define MMU_TCU_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TCU_MPAMF_IDR_LO_NS_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_PMG_MAX_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_PMG_MAX_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_HAS_CCAP_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_HAS_CCAP_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_HAS_CPOR_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_HAS_CPOR_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_HAS_MBW_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_HAS_MBW_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_HAS_PRI_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_HAS_PRI_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_EXT_MASK (0x10000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TCU_MPAMF_IDR_LO_NS_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_EXT_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_EXT_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_HAS_IMPL_IDR_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_MSMON_MASK (0x40000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_HAS_MSMON_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_HAS_MSMON_MASK) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TCU_MPAMF_IDR_LO_NS_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_NS_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_NS - MPAMF_IDR_ns (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_RIS_MASK (0x1U) #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_NS_HAS_RIS_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_NS_HAS_RIS_MASK) #define MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK (0x10U) #define MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_PART_MASK) #define MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_NS_NO_IMPL_MSMON_MASK) #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_NS_HAS_EXTD_ESR_MASK) #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_ESR_MASK (0x80U) #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TCU_MPAMF_IDR_HI_NS_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_NS_HAS_ESR_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_NS_HAS_ESR_MASK) #define MMU_TCU_MPAMF_IDR_HI_NS_RIS_MAX_MASK (0xF000000U) #define MMU_TCU_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TCU_MPAMF_IDR_HI_NS_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_NS_RIS_MAX_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_NS_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_NS - MPAMF_IIDR_ns */ /*! @{ */ #define MMU_TCU_MPAMF_IIDR_NS_Implementer_MASK (0xFFFU) #define MMU_TCU_MPAMF_IIDR_NS_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TCU_MPAMF_IIDR_NS_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_NS_Implementer_SHIFT)) & MMU_TCU_MPAMF_IIDR_NS_Implementer_MASK) #define MMU_TCU_MPAMF_IIDR_NS_Revision_MASK (0xF000U) #define MMU_TCU_MPAMF_IIDR_NS_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TCU_MPAMF_IIDR_NS_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_NS_Revision_SHIFT)) & MMU_TCU_MPAMF_IIDR_NS_Revision_MASK) #define MMU_TCU_MPAMF_IIDR_NS_Variant_MASK (0xF0000U) #define MMU_TCU_MPAMF_IIDR_NS_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TCU_MPAMF_IIDR_NS_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_NS_Variant_SHIFT)) & MMU_TCU_MPAMF_IIDR_NS_Variant_MASK) #define MMU_TCU_MPAMF_IIDR_NS_ProductID_MASK (0xFFF00000U) #define MMU_TCU_MPAMF_IIDR_NS_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TCU_MPAMF_IIDR_NS_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_NS_ProductID_SHIFT)) & MMU_TCU_MPAMF_IIDR_NS_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_NS - MPAMF_AIDR_ns */ /*! @{ */ #define MMU_TCU_MPAMF_AIDR_NS_ArchMinorRev_MASK (0xFU) #define MMU_TCU_MPAMF_AIDR_NS_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TCU_MPAMF_AIDR_NS_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_AIDR_NS_ArchMinorRev_SHIFT)) & MMU_TCU_MPAMF_AIDR_NS_ArchMinorRev_MASK) #define MMU_TCU_MPAMF_AIDR_NS_ArchMajorRev_MASK (0xF0U) #define MMU_TCU_MPAMF_AIDR_NS_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TCU_MPAMF_AIDR_NS_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_AIDR_NS_ArchMajorRev_SHIFT)) & MMU_TCU_MPAMF_AIDR_NS_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_NS - MPAMF_CCAP_IDR_ns */ /*! @{ */ #define MMU_TCU_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK (0x3FU) #define MMU_TCU_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TCU_MPAMF_CCAP_IDR_NS_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_CCAP_IDR_NS_CMAX_WD_SHIFT)) & MMU_TCU_MPAMF_CCAP_IDR_NS_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_NS - MPAMF_MSMON_IDR_ns */ /*! @{ */ #define MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK (0x10000U) #define MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_CSU_SHIFT)) & MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_CSU_MASK) #define MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK (0x20000U) #define MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_MBWU_SHIFT)) & MMU_TCU_MPAMF_MSMON_IDR_NS_MSMON_MBWU_MASK) #define MMU_TCU_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TCU_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TCU_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TCU_MPAMF_MSMON_IDR_NS_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_NS - MPAMF_CSUMON_IDR_ns */ /*! @{ */ #define MMU_TCU_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK (0xFFFFU) #define MMU_TCU_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TCU_MPAMF_CSUMON_IDR_NS_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_CSUMON_IDR_NS_NUM_MON_SHIFT)) & MMU_TCU_MPAMF_CSUMON_IDR_NS_NUM_MON_MASK) #define MMU_TCU_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TCU_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TCU_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_SHIFT)) & MMU_TCU_MPAMF_CSUMON_IDR_NS_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_NS - MPAMCFG_PART_SEL_ns */ /*! @{ */ #define MMU_TCU_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK (0xFFFFU) #define MMU_TCU_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TCU_MPAMCFG_PART_SEL_NS_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_PART_SEL_NS_PARTID_SEL_SHIFT)) & MMU_TCU_MPAMCFG_PART_SEL_NS_PARTID_SEL_MASK) #define MMU_TCU_MPAMCFG_PART_SEL_NS_INTERNAL_MASK (0x10000U) #define MMU_TCU_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TCU_MPAMCFG_PART_SEL_NS_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_PART_SEL_NS_INTERNAL_SHIFT)) & MMU_TCU_MPAMCFG_PART_SEL_NS_INTERNAL_MASK) #define MMU_TCU_MPAMCFG_PART_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TCU_MPAMCFG_PART_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TCU_MPAMCFG_PART_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_PART_SEL_NS_RIS_SHIFT)) & MMU_TCU_MPAMCFG_PART_SEL_NS_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_NS - MPAMCFG_CMAX_ns */ /*! @{ */ #define MMU_TCU_MPAMCFG_CMAX_NS_CMAX_MASK (0xFFFFU) #define MMU_TCU_MPAMCFG_CMAX_NS_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_MPAMCFG_CMAX_NS_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_CMAX_NS_CMAX_SHIFT)) & MMU_TCU_MPAMCFG_CMAX_NS_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_MON_SEL_NS - MSMON_CFG_MON_SEL_ns */ /*! @{ */ #define MMU_TCU_MSMON_CFG_MON_SEL_NS_MON_SEL_MASK (0xFFFFU) #define MMU_TCU_MSMON_CFG_MON_SEL_NS_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TCU_MSMON_CFG_MON_SEL_NS_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_MON_SEL_NS_MON_SEL_SHIFT)) & MMU_TCU_MSMON_CFG_MON_SEL_NS_MON_SEL_MASK) #define MMU_TCU_MSMON_CFG_MON_SEL_NS_RIS_MASK (0xF000000U) #define MMU_TCU_MSMON_CFG_MON_SEL_NS_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TCU_MSMON_CFG_MON_SEL_NS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_MON_SEL_NS_RIS_SHIFT)) & MMU_TCU_MSMON_CFG_MON_SEL_NS_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_NS - MSMON_CAPT_EVNT_ns */ /*! @{ */ #define MMU_TCU_MSMON_CAPT_EVNT_NS_NOW_MASK (0x1U) #define MMU_TCU_MSMON_CAPT_EVNT_NS_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TCU_MSMON_CAPT_EVNT_NS_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CAPT_EVNT_NS_NOW_SHIFT)) & MMU_TCU_MSMON_CAPT_EVNT_NS_NOW_MASK) #define MMU_TCU_MSMON_CAPT_EVNT_NS_ALL_MASK (0x2U) #define MMU_TCU_MSMON_CAPT_EVNT_NS_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TCU_MSMON_CAPT_EVNT_NS_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CAPT_EVNT_NS_ALL_SHIFT)) & MMU_TCU_MSMON_CAPT_EVNT_NS_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_NS - MSMON_CFG_CSU_FLT_ns */ /*! @{ */ #define MMU_TCU_MSMON_CFG_CSU_FLT_NS_PARTID_MASK (0xFFFFU) #define MMU_TCU_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TCU_MSMON_CFG_CSU_FLT_NS_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_FLT_NS_PARTID_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_FLT_NS_PARTID_MASK) #define MMU_TCU_MSMON_CFG_CSU_FLT_NS_PMG_MASK (0xFF0000U) #define MMU_TCU_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TCU_MSMON_CFG_CSU_FLT_NS_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_FLT_NS_PMG_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_FLT_NS_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_NS - MSMON_CFG_CSU_CTL_ns */ /*! @{ */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_TYPE_MASK (0xFFU) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_TYPE_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_TYPE_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK (0x10000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PARTID_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK (0x20000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_MATCH_PMG_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK (0xF00000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_SUBTYPE_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_SUBTYPE_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_FRZ_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK (0x2000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_INTR_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_OFLOW_STATUS_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK (0x8000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_RESET_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK (0x70000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_CAPT_EVNT_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_EN_MASK (0x80000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TCU_MSMON_CFG_CSU_CTL_NS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_NS_EN_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_NS_EN_MASK) /*! @} */ /*! @name MSMON_CSU_NS - MSMON_CSU_ns */ /*! @{ */ #define MMU_TCU_MSMON_CSU_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TCU_MSMON_CSU_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TCU_MSMON_CSU_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_NS_VALUE_SHIFT)) & MMU_TCU_MSMON_CSU_NS_VALUE_MASK) #define MMU_TCU_MSMON_CSU_NS_NRDY_MASK (0x80000000U) #define MMU_TCU_MSMON_CSU_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TCU_MSMON_CSU_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_NS_NRDY_SHIFT)) & MMU_TCU_MSMON_CSU_NS_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_NS - MSMON_CSU_CAPTURE_ns */ /*! @{ */ #define MMU_TCU_MSMON_CSU_CAPTURE_NS_VALUE_MASK (0x7FFFFFFFU) #define MMU_TCU_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TCU_MSMON_CSU_CAPTURE_NS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_CAPTURE_NS_VALUE_SHIFT)) & MMU_TCU_MSMON_CSU_CAPTURE_NS_VALUE_MASK) #define MMU_TCU_MSMON_CSU_CAPTURE_NS_NRDY_MASK (0x80000000U) #define MMU_TCU_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TCU_MSMON_CSU_CAPTURE_NS_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_CAPTURE_NS_NRDY_SHIFT)) & MMU_TCU_MSMON_CSU_CAPTURE_NS_NRDY_MASK) /*! @} */ /*! @name SMMU_S_IDR0 - SMMU_S_IDR0 */ /*! @{ */ #define MMU_TCU_SMMU_S_IDR0_MSI_MASK (0x2000U) #define MMU_TCU_SMMU_S_IDR0_MSI_SHIFT (13U) /*! MSI - MSI */ #define MMU_TCU_SMMU_S_IDR0_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IDR0_MSI_SHIFT)) & MMU_TCU_SMMU_S_IDR0_MSI_MASK) #define MMU_TCU_SMMU_S_IDR0_STALL_MODEL_MASK (0x3000000U) #define MMU_TCU_SMMU_S_IDR0_STALL_MODEL_SHIFT (24U) /*! STALL_MODEL - STALL_MODEL */ #define MMU_TCU_SMMU_S_IDR0_STALL_MODEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IDR0_STALL_MODEL_SHIFT)) & MMU_TCU_SMMU_S_IDR0_STALL_MODEL_MASK) /*! @} */ /*! @name SMMU_S_IDR1 - SMMU_S_IDR1 */ /*! @{ */ #define MMU_TCU_SMMU_S_IDR1_S_SIDSIZE_MASK (0x3FU) #define MMU_TCU_SMMU_S_IDR1_S_SIDSIZE_SHIFT (0U) /*! S_SIDSIZE - S_SIDSIZE */ #define MMU_TCU_SMMU_S_IDR1_S_SIDSIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IDR1_S_SIDSIZE_SHIFT)) & MMU_TCU_SMMU_S_IDR1_S_SIDSIZE_MASK) #define MMU_TCU_SMMU_S_IDR1_SEL2_MASK (0x20000000U) #define MMU_TCU_SMMU_S_IDR1_SEL2_SHIFT (29U) /*! SEL2 - SEL2 */ #define MMU_TCU_SMMU_S_IDR1_SEL2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IDR1_SEL2_SHIFT)) & MMU_TCU_SMMU_S_IDR1_SEL2_MASK) #define MMU_TCU_SMMU_S_IDR1_SECURE_IMPL_MASK (0x80000000U) #define MMU_TCU_SMMU_S_IDR1_SECURE_IMPL_SHIFT (31U) /*! SECURE_IMPL - SECURE_IMPL */ #define MMU_TCU_SMMU_S_IDR1_SECURE_IMPL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IDR1_SECURE_IMPL_SHIFT)) & MMU_TCU_SMMU_S_IDR1_SECURE_IMPL_MASK) /*! @} */ /*! @name SMMU_S_IDR3 - SMMU_S_IDR3 */ /*! @{ */ #define MMU_TCU_SMMU_S_IDR3_SAMS_MASK (0x40U) #define MMU_TCU_SMMU_S_IDR3_SAMS_SHIFT (6U) /*! SAMS - SAMS */ #define MMU_TCU_SMMU_S_IDR3_SAMS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IDR3_SAMS_SHIFT)) & MMU_TCU_SMMU_S_IDR3_SAMS_MASK) /*! @} */ /*! @name SMMU_S_IDR4 - SMMU_S_IDR4 */ /*! @{ */ #define MMU_TCU_SMMU_S_IDR4_IMPDEF_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_S_IDR4_IMPDEF_SHIFT (0U) /*! IMPDEF - IMPDEF */ #define MMU_TCU_SMMU_S_IDR4_IMPDEF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IDR4_IMPDEF_SHIFT)) & MMU_TCU_SMMU_S_IDR4_IMPDEF_MASK) /*! @} */ /*! @name SMMU_S_CR0 - SMMU_S_CR0 */ /*! @{ */ #define MMU_TCU_SMMU_S_CR0_SMMUEN_MASK (0x1U) #define MMU_TCU_SMMU_S_CR0_SMMUEN_SHIFT (0U) /*! SMMUEN - SMMUEN */ #define MMU_TCU_SMMU_S_CR0_SMMUEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0_SMMUEN_SHIFT)) & MMU_TCU_SMMU_S_CR0_SMMUEN_MASK) #define MMU_TCU_SMMU_S_CR0_EVENTQEN_MASK (0x4U) #define MMU_TCU_SMMU_S_CR0_EVENTQEN_SHIFT (2U) /*! EVENTQEN - EVENTQEN */ #define MMU_TCU_SMMU_S_CR0_EVENTQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0_EVENTQEN_SHIFT)) & MMU_TCU_SMMU_S_CR0_EVENTQEN_MASK) #define MMU_TCU_SMMU_S_CR0_CMDQEN_MASK (0x8U) #define MMU_TCU_SMMU_S_CR0_CMDQEN_SHIFT (3U) /*! CMDQEN - CMDQEN */ #define MMU_TCU_SMMU_S_CR0_CMDQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0_CMDQEN_SHIFT)) & MMU_TCU_SMMU_S_CR0_CMDQEN_MASK) #define MMU_TCU_SMMU_S_CR0_SIF_MASK (0x20U) #define MMU_TCU_SMMU_S_CR0_SIF_SHIFT (5U) /*! SIF - SIF */ #define MMU_TCU_SMMU_S_CR0_SIF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0_SIF_SHIFT)) & MMU_TCU_SMMU_S_CR0_SIF_MASK) #define MMU_TCU_SMMU_S_CR0_NSSTALLD_MASK (0x200U) #define MMU_TCU_SMMU_S_CR0_NSSTALLD_SHIFT (9U) /*! NSSTALLD - NSSTALLD */ #define MMU_TCU_SMMU_S_CR0_NSSTALLD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0_NSSTALLD_SHIFT)) & MMU_TCU_SMMU_S_CR0_NSSTALLD_MASK) /*! @} */ /*! @name SMMU_S_CR0ACK - SMMU_S_CR0ACK */ /*! @{ */ #define MMU_TCU_SMMU_S_CR0ACK_SMMUEN_MASK (0x1U) #define MMU_TCU_SMMU_S_CR0ACK_SMMUEN_SHIFT (0U) /*! SMMUEN - SMMUEN */ #define MMU_TCU_SMMU_S_CR0ACK_SMMUEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0ACK_SMMUEN_SHIFT)) & MMU_TCU_SMMU_S_CR0ACK_SMMUEN_MASK) #define MMU_TCU_SMMU_S_CR0ACK_EVENTQEN_MASK (0x4U) #define MMU_TCU_SMMU_S_CR0ACK_EVENTQEN_SHIFT (2U) /*! EVENTQEN - EVENTQEN */ #define MMU_TCU_SMMU_S_CR0ACK_EVENTQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0ACK_EVENTQEN_SHIFT)) & MMU_TCU_SMMU_S_CR0ACK_EVENTQEN_MASK) #define MMU_TCU_SMMU_S_CR0ACK_CMDQEN_MASK (0x8U) #define MMU_TCU_SMMU_S_CR0ACK_CMDQEN_SHIFT (3U) /*! CMDQEN - CMDQEN */ #define MMU_TCU_SMMU_S_CR0ACK_CMDQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0ACK_CMDQEN_SHIFT)) & MMU_TCU_SMMU_S_CR0ACK_CMDQEN_MASK) #define MMU_TCU_SMMU_S_CR0ACK_SIF_MASK (0x20U) #define MMU_TCU_SMMU_S_CR0ACK_SIF_SHIFT (5U) /*! SIF - SIF */ #define MMU_TCU_SMMU_S_CR0ACK_SIF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0ACK_SIF_SHIFT)) & MMU_TCU_SMMU_S_CR0ACK_SIF_MASK) #define MMU_TCU_SMMU_S_CR0ACK_NSSTALLD_MASK (0x200U) #define MMU_TCU_SMMU_S_CR0ACK_NSSTALLD_SHIFT (9U) /*! NSSTALLD - NSSTALLD */ #define MMU_TCU_SMMU_S_CR0ACK_NSSTALLD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR0ACK_NSSTALLD_SHIFT)) & MMU_TCU_SMMU_S_CR0ACK_NSSTALLD_MASK) /*! @} */ /*! @name SMMU_S_CR1 - SMMU_S_CR1 */ /*! @{ */ #define MMU_TCU_SMMU_S_CR1_QUEUE_IC_MASK (0x3U) #define MMU_TCU_SMMU_S_CR1_QUEUE_IC_SHIFT (0U) /*! QUEUE_IC - QUEUE_IC */ #define MMU_TCU_SMMU_S_CR1_QUEUE_IC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR1_QUEUE_IC_SHIFT)) & MMU_TCU_SMMU_S_CR1_QUEUE_IC_MASK) #define MMU_TCU_SMMU_S_CR1_QUEUE_OC_MASK (0xCU) #define MMU_TCU_SMMU_S_CR1_QUEUE_OC_SHIFT (2U) /*! QUEUE_OC - QUEUE_OC */ #define MMU_TCU_SMMU_S_CR1_QUEUE_OC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR1_QUEUE_OC_SHIFT)) & MMU_TCU_SMMU_S_CR1_QUEUE_OC_MASK) #define MMU_TCU_SMMU_S_CR1_QUEUE_SH_MASK (0x30U) #define MMU_TCU_SMMU_S_CR1_QUEUE_SH_SHIFT (4U) /*! QUEUE_SH - QUEUE_SH */ #define MMU_TCU_SMMU_S_CR1_QUEUE_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR1_QUEUE_SH_SHIFT)) & MMU_TCU_SMMU_S_CR1_QUEUE_SH_MASK) #define MMU_TCU_SMMU_S_CR1_TABLE_IC_MASK (0xC0U) #define MMU_TCU_SMMU_S_CR1_TABLE_IC_SHIFT (6U) /*! TABLE_IC - TABLE_IC */ #define MMU_TCU_SMMU_S_CR1_TABLE_IC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR1_TABLE_IC_SHIFT)) & MMU_TCU_SMMU_S_CR1_TABLE_IC_MASK) #define MMU_TCU_SMMU_S_CR1_TABLE_OC_MASK (0x300U) #define MMU_TCU_SMMU_S_CR1_TABLE_OC_SHIFT (8U) /*! TABLE_OC - TABLE_OC */ #define MMU_TCU_SMMU_S_CR1_TABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR1_TABLE_OC_SHIFT)) & MMU_TCU_SMMU_S_CR1_TABLE_OC_MASK) #define MMU_TCU_SMMU_S_CR1_TABLE_SH_MASK (0xC00U) #define MMU_TCU_SMMU_S_CR1_TABLE_SH_SHIFT (10U) /*! TABLE_SH - TABLE_SH */ #define MMU_TCU_SMMU_S_CR1_TABLE_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR1_TABLE_SH_SHIFT)) & MMU_TCU_SMMU_S_CR1_TABLE_SH_MASK) /*! @} */ /*! @name SMMU_S_CR2 - SMMU_S_CR2 */ /*! @{ */ #define MMU_TCU_SMMU_S_CR2_E2H_MASK (0x1U) #define MMU_TCU_SMMU_S_CR2_E2H_SHIFT (0U) /*! E2H - E2H */ #define MMU_TCU_SMMU_S_CR2_E2H(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR2_E2H_SHIFT)) & MMU_TCU_SMMU_S_CR2_E2H_MASK) #define MMU_TCU_SMMU_S_CR2_RECINVSID_MASK (0x2U) #define MMU_TCU_SMMU_S_CR2_RECINVSID_SHIFT (1U) /*! RECINVSID - RECINVSID */ #define MMU_TCU_SMMU_S_CR2_RECINVSID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR2_RECINVSID_SHIFT)) & MMU_TCU_SMMU_S_CR2_RECINVSID_MASK) #define MMU_TCU_SMMU_S_CR2_PTM_MASK (0x4U) #define MMU_TCU_SMMU_S_CR2_PTM_SHIFT (2U) /*! PTM - PTM */ #define MMU_TCU_SMMU_S_CR2_PTM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CR2_PTM_SHIFT)) & MMU_TCU_SMMU_S_CR2_PTM_MASK) /*! @} */ /*! @name SMMU_S_INIT - SMMU_S_INIT */ /*! @{ */ #define MMU_TCU_SMMU_S_INIT_INV_ALL_MASK (0x1U) #define MMU_TCU_SMMU_S_INIT_INV_ALL_SHIFT (0U) /*! INV_ALL - INV_ALL */ #define MMU_TCU_SMMU_S_INIT_INV_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_INIT_INV_ALL_SHIFT)) & MMU_TCU_SMMU_S_INIT_INV_ALL_MASK) /*! @} */ /*! @name SMMU_S_GBPA - SMMU_S_GBPA */ /*! @{ */ #define MMU_TCU_SMMU_S_GBPA_MemAttr_MASK (0xFU) #define MMU_TCU_SMMU_S_GBPA_MemAttr_SHIFT (0U) /*! MemAttr - MemAttr */ #define MMU_TCU_SMMU_S_GBPA_MemAttr(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_MemAttr_SHIFT)) & MMU_TCU_SMMU_S_GBPA_MemAttr_MASK) #define MMU_TCU_SMMU_S_GBPA_MTCFG_MASK (0x10U) #define MMU_TCU_SMMU_S_GBPA_MTCFG_SHIFT (4U) /*! MTCFG - MTCFG */ #define MMU_TCU_SMMU_S_GBPA_MTCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_MTCFG_SHIFT)) & MMU_TCU_SMMU_S_GBPA_MTCFG_MASK) #define MMU_TCU_SMMU_S_GBPA_ALLOCCFG_MASK (0xF00U) #define MMU_TCU_SMMU_S_GBPA_ALLOCCFG_SHIFT (8U) /*! ALLOCCFG - ALLOCCFG */ #define MMU_TCU_SMMU_S_GBPA_ALLOCCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_ALLOCCFG_SHIFT)) & MMU_TCU_SMMU_S_GBPA_ALLOCCFG_MASK) #define MMU_TCU_SMMU_S_GBPA_SHCFG_MASK (0x3000U) #define MMU_TCU_SMMU_S_GBPA_SHCFG_SHIFT (12U) /*! SHCFG - SHCFG */ #define MMU_TCU_SMMU_S_GBPA_SHCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_SHCFG_SHIFT)) & MMU_TCU_SMMU_S_GBPA_SHCFG_MASK) #define MMU_TCU_SMMU_S_GBPA_NSCFG_MASK (0xC000U) #define MMU_TCU_SMMU_S_GBPA_NSCFG_SHIFT (14U) /*! NSCFG - NSCFG */ #define MMU_TCU_SMMU_S_GBPA_NSCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_NSCFG_SHIFT)) & MMU_TCU_SMMU_S_GBPA_NSCFG_MASK) #define MMU_TCU_SMMU_S_GBPA_PRIVCFG_MASK (0x30000U) #define MMU_TCU_SMMU_S_GBPA_PRIVCFG_SHIFT (16U) /*! PRIVCFG - PRIVCFG */ #define MMU_TCU_SMMU_S_GBPA_PRIVCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_PRIVCFG_SHIFT)) & MMU_TCU_SMMU_S_GBPA_PRIVCFG_MASK) #define MMU_TCU_SMMU_S_GBPA_INSTCFG_MASK (0xC0000U) #define MMU_TCU_SMMU_S_GBPA_INSTCFG_SHIFT (18U) /*! INSTCFG - INSTCFG */ #define MMU_TCU_SMMU_S_GBPA_INSTCFG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_INSTCFG_SHIFT)) & MMU_TCU_SMMU_S_GBPA_INSTCFG_MASK) #define MMU_TCU_SMMU_S_GBPA_ABORT_MASK (0x100000U) #define MMU_TCU_SMMU_S_GBPA_ABORT_SHIFT (20U) /*! ABORT - ABORT */ #define MMU_TCU_SMMU_S_GBPA_ABORT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_ABORT_SHIFT)) & MMU_TCU_SMMU_S_GBPA_ABORT_MASK) #define MMU_TCU_SMMU_S_GBPA_Update_MASK (0x80000000U) #define MMU_TCU_SMMU_S_GBPA_Update_SHIFT (31U) /*! Update - Update */ #define MMU_TCU_SMMU_S_GBPA_Update(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GBPA_Update_SHIFT)) & MMU_TCU_SMMU_S_GBPA_Update_MASK) /*! @} */ /*! @name SMMU_S_AGBPA - SMMU_S_AGBPA */ /*! @{ */ #define MMU_TCU_SMMU_S_AGBPA_PBHA_MASK (0xFU) #define MMU_TCU_SMMU_S_AGBPA_PBHA_SHIFT (0U) /*! PBHA - PBHA */ #define MMU_TCU_SMMU_S_AGBPA_PBHA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_AGBPA_PBHA_SHIFT)) & MMU_TCU_SMMU_S_AGBPA_PBHA_MASK) #define MMU_TCU_SMMU_S_AGBPA_Update_MASK (0x80000000U) #define MMU_TCU_SMMU_S_AGBPA_Update_SHIFT (31U) /*! Update - Update */ #define MMU_TCU_SMMU_S_AGBPA_Update(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_AGBPA_Update_SHIFT)) & MMU_TCU_SMMU_S_AGBPA_Update_MASK) /*! @} */ /*! @name SMMU_S_IRQ_CTRL - SMMU_S_IRQ_CTRL */ /*! @{ */ #define MMU_TCU_SMMU_S_IRQ_CTRL_GERROR_IRQEN_MASK (0x1U) #define MMU_TCU_SMMU_S_IRQ_CTRL_GERROR_IRQEN_SHIFT (0U) /*! GERROR_IRQEN - GERROR_IRQEN */ #define MMU_TCU_SMMU_S_IRQ_CTRL_GERROR_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IRQ_CTRL_GERROR_IRQEN_SHIFT)) & MMU_TCU_SMMU_S_IRQ_CTRL_GERROR_IRQEN_MASK) #define MMU_TCU_SMMU_S_IRQ_CTRL_EVENTQ_IRQEN_MASK (0x4U) #define MMU_TCU_SMMU_S_IRQ_CTRL_EVENTQ_IRQEN_SHIFT (2U) /*! EVENTQ_IRQEN - EVENTQ_IRQEN */ #define MMU_TCU_SMMU_S_IRQ_CTRL_EVENTQ_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IRQ_CTRL_EVENTQ_IRQEN_SHIFT)) & MMU_TCU_SMMU_S_IRQ_CTRL_EVENTQ_IRQEN_MASK) /*! @} */ /*! @name SMMU_S_IRQ_CTRLACK - SMMU_S_IRQ_CTRLACK */ /*! @{ */ #define MMU_TCU_SMMU_S_IRQ_CTRLACK_GERROR_IRQEN_MASK (0x1U) #define MMU_TCU_SMMU_S_IRQ_CTRLACK_GERROR_IRQEN_SHIFT (0U) /*! GERROR_IRQEN - GERROR_IRQEN */ #define MMU_TCU_SMMU_S_IRQ_CTRLACK_GERROR_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IRQ_CTRLACK_GERROR_IRQEN_SHIFT)) & MMU_TCU_SMMU_S_IRQ_CTRLACK_GERROR_IRQEN_MASK) #define MMU_TCU_SMMU_S_IRQ_CTRLACK_EVENTQ_IRQEN_MASK (0x4U) #define MMU_TCU_SMMU_S_IRQ_CTRLACK_EVENTQ_IRQEN_SHIFT (2U) /*! EVENTQ_IRQEN - EVENTQ_IRQEN */ #define MMU_TCU_SMMU_S_IRQ_CTRLACK_EVENTQ_IRQEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_IRQ_CTRLACK_EVENTQ_IRQEN_SHIFT)) & MMU_TCU_SMMU_S_IRQ_CTRLACK_EVENTQ_IRQEN_MASK) /*! @} */ /*! @name SMMU_S_GERROR - SMMU_S_GERROR */ /*! @{ */ #define MMU_TCU_SMMU_S_GERROR_CMDQ_ERR_MASK (0x1U) #define MMU_TCU_SMMU_S_GERROR_CMDQ_ERR_SHIFT (0U) /*! CMDQ_ERR - CMDQ_ERR */ #define MMU_TCU_SMMU_S_GERROR_CMDQ_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_CMDQ_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_CMDQ_ERR_MASK) #define MMU_TCU_SMMU_S_GERROR_EVENTQ_ABT_ERR_MASK (0x4U) #define MMU_TCU_SMMU_S_GERROR_EVENTQ_ABT_ERR_SHIFT (2U) /*! EVENTQ_ABT_ERR - EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_S_GERROR_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERROR_MSI_CMDQ_ABT_ERR_MASK (0x10U) #define MMU_TCU_SMMU_S_GERROR_MSI_CMDQ_ABT_ERR_SHIFT (4U) /*! MSI_CMDQ_ABT_ERR - MSI_CMDQ_ABT_ERR */ #define MMU_TCU_SMMU_S_GERROR_MSI_CMDQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_MSI_CMDQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_MSI_CMDQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERROR_MSI_EVENTQ_ABT_ERR_MASK (0x20U) #define MMU_TCU_SMMU_S_GERROR_MSI_EVENTQ_ABT_ERR_SHIFT (5U) /*! MSI_EVENTQ_ABT_ERR - MSI_EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_S_GERROR_MSI_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_MSI_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_MSI_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERROR_MSI_GERROR_ABT_ERR_MASK (0x80U) #define MMU_TCU_SMMU_S_GERROR_MSI_GERROR_ABT_ERR_SHIFT (7U) /*! MSI_GERROR_ABT_ERR - MSI_GERROR_ABT_ERR */ #define MMU_TCU_SMMU_S_GERROR_MSI_GERROR_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_MSI_GERROR_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_MSI_GERROR_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERROR_SFM_ERR_MASK (0x100U) #define MMU_TCU_SMMU_S_GERROR_SFM_ERR_SHIFT (8U) /*! SFM_ERR - SFM_ERR */ #define MMU_TCU_SMMU_S_GERROR_SFM_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_SFM_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_SFM_ERR_MASK) /*! @} */ /*! @name SMMU_S_GERRORN - SMMU_S_GERRORN */ /*! @{ */ #define MMU_TCU_SMMU_S_GERRORN_CMDQ_ERR_MASK (0x1U) #define MMU_TCU_SMMU_S_GERRORN_CMDQ_ERR_SHIFT (0U) /*! CMDQ_ERR - CMDQ_ERR */ #define MMU_TCU_SMMU_S_GERRORN_CMDQ_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERRORN_CMDQ_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERRORN_CMDQ_ERR_MASK) #define MMU_TCU_SMMU_S_GERRORN_EVENTQ_ABT_ERR_MASK (0x4U) #define MMU_TCU_SMMU_S_GERRORN_EVENTQ_ABT_ERR_SHIFT (2U) /*! EVENTQ_ABT_ERR - EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_S_GERRORN_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERRORN_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERRORN_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERRORN_MSI_CMDQ_ABT_ERR_MASK (0x10U) #define MMU_TCU_SMMU_S_GERRORN_MSI_CMDQ_ABT_ERR_SHIFT (4U) /*! MSI_CMDQ_ABT_ERR - MSI_CMDQ_ABT_ERR */ #define MMU_TCU_SMMU_S_GERRORN_MSI_CMDQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERRORN_MSI_CMDQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERRORN_MSI_CMDQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERRORN_MSI_EVENTQ_ABT_ERR_MASK (0x20U) #define MMU_TCU_SMMU_S_GERRORN_MSI_EVENTQ_ABT_ERR_SHIFT (5U) /*! MSI_EVENTQ_ABT_ERR - MSI_EVENTQ_ABT_ERR */ #define MMU_TCU_SMMU_S_GERRORN_MSI_EVENTQ_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERRORN_MSI_EVENTQ_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERRORN_MSI_EVENTQ_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERRORN_MSI_GERROR_ABT_ERR_MASK (0x80U) #define MMU_TCU_SMMU_S_GERRORN_MSI_GERROR_ABT_ERR_SHIFT (7U) /*! MSI_GERROR_ABT_ERR - MSI_GERROR_ABT_ERR */ #define MMU_TCU_SMMU_S_GERRORN_MSI_GERROR_ABT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERRORN_MSI_GERROR_ABT_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERRORN_MSI_GERROR_ABT_ERR_MASK) #define MMU_TCU_SMMU_S_GERRORN_SFM_ERR_MASK (0x100U) #define MMU_TCU_SMMU_S_GERRORN_SFM_ERR_SHIFT (8U) /*! SFM_ERR - SFM_ERR */ #define MMU_TCU_SMMU_S_GERRORN_SFM_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERRORN_SFM_ERR_SHIFT)) & MMU_TCU_SMMU_S_GERRORN_SFM_ERR_MASK) /*! @} */ /*! @name SMMU_S_GERROR_IRQ_CFG0_LO - SMMU_S_GERROR_IRQ_CFG0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_LO_ADDR_MASK (0xFFFFFFFCU) #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_LO_ADDR_SHIFT (2U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_S_GERROR_IRQ_CFG0_HI - SMMU_S_GERROR_IRQ_CFG0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_S_GERROR_IRQ_CFG0_HI_ADDR_MASK) /*! @} */ /*! @name SMMU_S_GERROR_IRQ_CFG1 - SMMU_S_GERROR_IRQ_CFG1 */ /*! @{ */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG1_DATA_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG1_DATA_SHIFT (0U) /*! DATA - DATA */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG1_DATA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_IRQ_CFG1_DATA_SHIFT)) & MMU_TCU_SMMU_S_GERROR_IRQ_CFG1_DATA_MASK) /*! @} */ /*! @name SMMU_S_GERROR_IRQ_CFG2 - SMMU_S_GERROR_IRQ_CFG2 */ /*! @{ */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_MemAttr_MASK (0xFU) #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_MemAttr_SHIFT (0U) /*! MemAttr - MemAttr */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_MemAttr(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_MemAttr_SHIFT)) & MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_MemAttr_MASK) #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_SH_MASK (0x30U) #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_SH_SHIFT (4U) /*! SH - SH */ #define MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_SH_SHIFT)) & MMU_TCU_SMMU_S_GERROR_IRQ_CFG2_SH_MASK) /*! @} */ /*! @name SMMU_S_STRTAB_BASE_LO - SMMU_S_STRTAB_BASE (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_STRTAB_BASE_LO_ADDR_MASK (0xFFFFFFC0U) #define MMU_TCU_SMMU_S_STRTAB_BASE_LO_ADDR_SHIFT (6U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_STRTAB_BASE_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_STRTAB_BASE_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_S_STRTAB_BASE_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_S_STRTAB_BASE_HI - SMMU_S_STRTAB_BASE (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_STRTAB_BASE_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_STRTAB_BASE_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_STRTAB_BASE_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_STRTAB_BASE_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_S_STRTAB_BASE_HI_ADDR_MASK) #define MMU_TCU_SMMU_S_STRTAB_BASE_HI_RA_MASK (0x40000000U) #define MMU_TCU_SMMU_S_STRTAB_BASE_HI_RA_SHIFT (30U) /*! RA - RA */ #define MMU_TCU_SMMU_S_STRTAB_BASE_HI_RA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_STRTAB_BASE_HI_RA_SHIFT)) & MMU_TCU_SMMU_S_STRTAB_BASE_HI_RA_MASK) /*! @} */ /*! @name SMMU_S_STRTAB_BASE_CFG - SMMU_S_STRTAB_BASE_CFG */ /*! @{ */ #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_LOG2SIZE_MASK (0x3FU) #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_LOG2SIZE_SHIFT (0U) /*! LOG2SIZE - LOG2SIZE */ #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_LOG2SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_STRTAB_BASE_CFG_LOG2SIZE_SHIFT)) & MMU_TCU_SMMU_S_STRTAB_BASE_CFG_LOG2SIZE_MASK) #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_SPLIT_MASK (0x7C0U) #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_SPLIT_SHIFT (6U) /*! SPLIT - SPLIT */ #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_SPLIT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_STRTAB_BASE_CFG_SPLIT_SHIFT)) & MMU_TCU_SMMU_S_STRTAB_BASE_CFG_SPLIT_MASK) #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_FMT_MASK (0x30000U) #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_FMT_SHIFT (16U) /*! FMT - FMT */ #define MMU_TCU_SMMU_S_STRTAB_BASE_CFG_FMT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_STRTAB_BASE_CFG_FMT_SHIFT)) & MMU_TCU_SMMU_S_STRTAB_BASE_CFG_FMT_MASK) /*! @} */ /*! @name SMMU_S_CMDQ_BASE_LO - SMMU_S_CMDQ_BASE (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_CMDQ_BASE_LO_LOG2SIZE_MASK (0x1FU) #define MMU_TCU_SMMU_S_CMDQ_BASE_LO_LOG2SIZE_SHIFT (0U) /*! LOG2SIZE - LOG2SIZE */ #define MMU_TCU_SMMU_S_CMDQ_BASE_LO_LOG2SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CMDQ_BASE_LO_LOG2SIZE_SHIFT)) & MMU_TCU_SMMU_S_CMDQ_BASE_LO_LOG2SIZE_MASK) #define MMU_TCU_SMMU_S_CMDQ_BASE_LO_ADDR_MASK (0xFFFFFFE0U) #define MMU_TCU_SMMU_S_CMDQ_BASE_LO_ADDR_SHIFT (5U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_CMDQ_BASE_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CMDQ_BASE_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_S_CMDQ_BASE_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_S_CMDQ_BASE_HI - SMMU_S_CMDQ_BASE (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_CMDQ_BASE_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_CMDQ_BASE_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_CMDQ_BASE_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CMDQ_BASE_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_S_CMDQ_BASE_HI_ADDR_MASK) #define MMU_TCU_SMMU_S_CMDQ_BASE_HI_RA_MASK (0x40000000U) #define MMU_TCU_SMMU_S_CMDQ_BASE_HI_RA_SHIFT (30U) /*! RA - RA */ #define MMU_TCU_SMMU_S_CMDQ_BASE_HI_RA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CMDQ_BASE_HI_RA_SHIFT)) & MMU_TCU_SMMU_S_CMDQ_BASE_HI_RA_MASK) /*! @} */ /*! @name SMMU_S_CMDQ_PROD - SMMU_S_CMDQ_PROD */ /*! @{ */ #define MMU_TCU_SMMU_S_CMDQ_PROD_WR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_CMDQ_PROD_WR_SHIFT (0U) /*! WR - WR */ #define MMU_TCU_SMMU_S_CMDQ_PROD_WR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CMDQ_PROD_WR_SHIFT)) & MMU_TCU_SMMU_S_CMDQ_PROD_WR_MASK) /*! @} */ /*! @name SMMU_S_CMDQ_CONS - SMMU_S_CMDQ_CONS */ /*! @{ */ #define MMU_TCU_SMMU_S_CMDQ_CONS_RD_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_CMDQ_CONS_RD_SHIFT (0U) /*! RD - RD */ #define MMU_TCU_SMMU_S_CMDQ_CONS_RD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CMDQ_CONS_RD_SHIFT)) & MMU_TCU_SMMU_S_CMDQ_CONS_RD_MASK) #define MMU_TCU_SMMU_S_CMDQ_CONS_ERR_MASK (0x7F000000U) #define MMU_TCU_SMMU_S_CMDQ_CONS_ERR_SHIFT (24U) /*! ERR - ERR */ #define MMU_TCU_SMMU_S_CMDQ_CONS_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_CMDQ_CONS_ERR_SHIFT)) & MMU_TCU_SMMU_S_CMDQ_CONS_ERR_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_BASE_LO - SMMU_S_EVENTQ_BASE (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_BASE_LO_LOG2SIZE_MASK (0x1FU) #define MMU_TCU_SMMU_S_EVENTQ_BASE_LO_LOG2SIZE_SHIFT (0U) /*! LOG2SIZE - LOG2SIZE */ #define MMU_TCU_SMMU_S_EVENTQ_BASE_LO_LOG2SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_BASE_LO_LOG2SIZE_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_BASE_LO_LOG2SIZE_MASK) #define MMU_TCU_SMMU_S_EVENTQ_BASE_LO_ADDR_MASK (0xFFFFFFE0U) #define MMU_TCU_SMMU_S_EVENTQ_BASE_LO_ADDR_SHIFT (5U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_EVENTQ_BASE_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_BASE_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_BASE_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_BASE_HI - SMMU_S_EVENTQ_BASE (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_BASE_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_EVENTQ_BASE_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_EVENTQ_BASE_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_BASE_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_BASE_HI_ADDR_MASK) #define MMU_TCU_SMMU_S_EVENTQ_BASE_HI_WA_MASK (0x40000000U) #define MMU_TCU_SMMU_S_EVENTQ_BASE_HI_WA_SHIFT (30U) /*! WA - WA */ #define MMU_TCU_SMMU_S_EVENTQ_BASE_HI_WA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_BASE_HI_WA_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_BASE_HI_WA_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_PROD - SMMU_S_EVENTQ_PROD */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_PROD_WR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_EVENTQ_PROD_WR_SHIFT (0U) /*! WR - WR */ #define MMU_TCU_SMMU_S_EVENTQ_PROD_WR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_PROD_WR_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_PROD_WR_MASK) #define MMU_TCU_SMMU_S_EVENTQ_PROD_OVFLG_MASK (0x80000000U) #define MMU_TCU_SMMU_S_EVENTQ_PROD_OVFLG_SHIFT (31U) /*! OVFLG - OVFLG */ #define MMU_TCU_SMMU_S_EVENTQ_PROD_OVFLG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_PROD_OVFLG_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_PROD_OVFLG_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_CONS - SMMU_S_EVENTQ_CONS */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_CONS_RD_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_EVENTQ_CONS_RD_SHIFT (0U) /*! RD - RD */ #define MMU_TCU_SMMU_S_EVENTQ_CONS_RD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_CONS_RD_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_CONS_RD_MASK) #define MMU_TCU_SMMU_S_EVENTQ_CONS_OVACKFLG_MASK (0x80000000U) #define MMU_TCU_SMMU_S_EVENTQ_CONS_OVACKFLG_SHIFT (31U) /*! OVACKFLG - OVACKFLG */ #define MMU_TCU_SMMU_S_EVENTQ_CONS_OVACKFLG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_CONS_OVACKFLG_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_CONS_OVACKFLG_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_IRQ_CFG0_LO - SMMU_S_EVENTQ_IRQ_CFG0 (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_LO_ADDR_MASK (0xFFFFFFFCU) #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_LO_ADDR_SHIFT (2U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_LO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_LO_ADDR_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_LO_ADDR_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_IRQ_CFG0_HI - SMMU_S_EVENTQ_IRQ_CFG0 (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_HI_ADDR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_HI_ADDR_SHIFT (0U) /*! ADDR - ADDR */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_HI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_HI_ADDR_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG0_HI_ADDR_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_IRQ_CFG1 - SMMU_S_EVENTQ_IRQ_CFG1 */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG1_DATA_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG1_DATA_SHIFT (0U) /*! DATA - DATA */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG1_DATA(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG1_DATA_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG1_DATA_MASK) /*! @} */ /*! @name SMMU_S_EVENTQ_IRQ_CFG2 - SMMU_S_EVENTQ_IRQ_CFG2 */ /*! @{ */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_MemAttr_MASK (0xFU) #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_MemAttr_SHIFT (0U) /*! MemAttr - MemAttr */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_MemAttr(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_MemAttr_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_MemAttr_MASK) #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_SH_MASK (0x30U) #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_SH_SHIFT (4U) /*! SH - SH */ #define MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_SH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_SH_SHIFT)) & MMU_TCU_SMMU_S_EVENTQ_IRQ_CFG2_SH_MASK) /*! @} */ /*! @name TCU_CTRL - TCU Control Register */ /*! @{ */ #define MMU_TCU_TCU_CTRL_AUX0_MASK (0x1U) #define MMU_TCU_TCU_CTRL_AUX0_SHIFT (0U) /*! AUX0 - AUX0 */ #define MMU_TCU_TCU_CTRL_AUX0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX0_SHIFT)) & MMU_TCU_TCU_CTRL_AUX0_MASK) #define MMU_TCU_TCU_CTRL_AUX1_MASK (0x2U) #define MMU_TCU_TCU_CTRL_AUX1_SHIFT (1U) /*! AUX1 - AUX1 */ #define MMU_TCU_TCU_CTRL_AUX1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX1_SHIFT)) & MMU_TCU_TCU_CTRL_AUX1_MASK) #define MMU_TCU_TCU_CTRL_AUX2_MASK (0x4U) #define MMU_TCU_TCU_CTRL_AUX2_SHIFT (2U) /*! AUX2 - AUX2 */ #define MMU_TCU_TCU_CTRL_AUX2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX2_SHIFT)) & MMU_TCU_TCU_CTRL_AUX2_MASK) #define MMU_TCU_TCU_CTRL_AUX3_MASK (0x8U) #define MMU_TCU_TCU_CTRL_AUX3_SHIFT (3U) /*! AUX3 - AUX3 */ #define MMU_TCU_TCU_CTRL_AUX3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX3_SHIFT)) & MMU_TCU_TCU_CTRL_AUX3_MASK) #define MMU_TCU_TCU_CTRL_AUX4_MASK (0x10U) #define MMU_TCU_TCU_CTRL_AUX4_SHIFT (4U) /*! AUX4 - AUX4 */ #define MMU_TCU_TCU_CTRL_AUX4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX4_SHIFT)) & MMU_TCU_TCU_CTRL_AUX4_MASK) #define MMU_TCU_TCU_CTRL_AUX5_MASK (0x20U) #define MMU_TCU_TCU_CTRL_AUX5_SHIFT (5U) /*! AUX5 - AUX5 */ #define MMU_TCU_TCU_CTRL_AUX5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX5_SHIFT)) & MMU_TCU_TCU_CTRL_AUX5_MASK) #define MMU_TCU_TCU_CTRL_AUX6_MASK (0x40U) #define MMU_TCU_TCU_CTRL_AUX6_SHIFT (6U) /*! AUX6 - AUX6 */ #define MMU_TCU_TCU_CTRL_AUX6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX6_SHIFT)) & MMU_TCU_TCU_CTRL_AUX6_MASK) #define MMU_TCU_TCU_CTRL_AUX7_MASK (0x80U) #define MMU_TCU_TCU_CTRL_AUX7_SHIFT (7U) /*! AUX7 - AUX7 */ #define MMU_TCU_TCU_CTRL_AUX7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX7_SHIFT)) & MMU_TCU_TCU_CTRL_AUX7_MASK) #define MMU_TCU_TCU_CTRL_WCS1L0_DIS_MASK (0x100U) #define MMU_TCU_TCU_CTRL_WCS1L0_DIS_SHIFT (8U) /*! WCS1L0_DIS - WCS1L0_DIS */ #define MMU_TCU_TCU_CTRL_WCS1L0_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS1L0_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS1L0_DIS_MASK) #define MMU_TCU_TCU_CTRL_WCS1L1_DIS_MASK (0x200U) #define MMU_TCU_TCU_CTRL_WCS1L1_DIS_SHIFT (9U) /*! WCS1L1_DIS - WCS1L1_DIS */ #define MMU_TCU_TCU_CTRL_WCS1L1_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS1L1_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS1L1_DIS_MASK) #define MMU_TCU_TCU_CTRL_WCS1L2_DIS_MASK (0x400U) #define MMU_TCU_TCU_CTRL_WCS1L2_DIS_SHIFT (10U) /*! WCS1L2_DIS - WCS1L2_DIS */ #define MMU_TCU_TCU_CTRL_WCS1L2_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS1L2_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS1L2_DIS_MASK) #define MMU_TCU_TCU_CTRL_WCS1L3_DIS_MASK (0x800U) #define MMU_TCU_TCU_CTRL_WCS1L3_DIS_SHIFT (11U) /*! WCS1L3_DIS - WCS1L3_DIS */ #define MMU_TCU_TCU_CTRL_WCS1L3_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS1L3_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS1L3_DIS_MASK) #define MMU_TCU_TCU_CTRL_WCS2L0_DIS_MASK (0x1000U) #define MMU_TCU_TCU_CTRL_WCS2L0_DIS_SHIFT (12U) /*! WCS2L0_DIS - WCS2L0_DIS */ #define MMU_TCU_TCU_CTRL_WCS2L0_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS2L0_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS2L0_DIS_MASK) #define MMU_TCU_TCU_CTRL_WCS2L1_DIS_MASK (0x2000U) #define MMU_TCU_TCU_CTRL_WCS2L1_DIS_SHIFT (13U) /*! WCS2L1_DIS - WCS2L1_DIS */ #define MMU_TCU_TCU_CTRL_WCS2L1_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS2L1_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS2L1_DIS_MASK) #define MMU_TCU_TCU_CTRL_WCS2L2_DIS_MASK (0x4000U) #define MMU_TCU_TCU_CTRL_WCS2L2_DIS_SHIFT (14U) /*! WCS2L2_DIS - WCS2L2_DIS */ #define MMU_TCU_TCU_CTRL_WCS2L2_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS2L2_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS2L2_DIS_MASK) #define MMU_TCU_TCU_CTRL_WCS2L3_DIS_MASK (0x8000U) #define MMU_TCU_TCU_CTRL_WCS2L3_DIS_SHIFT (15U) /*! WCS2L3_DIS - WCS2L3_DIS */ #define MMU_TCU_TCU_CTRL_WCS2L3_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_WCS2L3_DIS_SHIFT)) & MMU_TCU_TCU_CTRL_WCS2L3_DIS_MASK) #define MMU_TCU_TCU_CTRL_AUX16_MASK (0x10000U) #define MMU_TCU_TCU_CTRL_AUX16_SHIFT (16U) /*! AUX16 - AUX16 */ #define MMU_TCU_TCU_CTRL_AUX16(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX16_SHIFT)) & MMU_TCU_TCU_CTRL_AUX16_MASK) #define MMU_TCU_TCU_CTRL_AUX17_MASK (0x20000U) #define MMU_TCU_TCU_CTRL_AUX17_SHIFT (17U) /*! AUX17 - AUX17 */ #define MMU_TCU_TCU_CTRL_AUX17(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX17_SHIFT)) & MMU_TCU_TCU_CTRL_AUX17_MASK) #define MMU_TCU_TCU_CTRL_AUX18_MASK (0x40000U) #define MMU_TCU_TCU_CTRL_AUX18_SHIFT (18U) /*! AUX18 - AUX18 */ #define MMU_TCU_TCU_CTRL_AUX18(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX18_SHIFT)) & MMU_TCU_TCU_CTRL_AUX18_MASK) #define MMU_TCU_TCU_CTRL_AUX19_MASK (0x80000U) #define MMU_TCU_TCU_CTRL_AUX19_SHIFT (19U) /*! AUX19 - AUX19 */ #define MMU_TCU_TCU_CTRL_AUX19(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX19_SHIFT)) & MMU_TCU_TCU_CTRL_AUX19_MASK) #define MMU_TCU_TCU_CTRL_AUX20_MASK (0x100000U) #define MMU_TCU_TCU_CTRL_AUX20_SHIFT (20U) /*! AUX20 - AUX20 */ #define MMU_TCU_TCU_CTRL_AUX20(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX20_SHIFT)) & MMU_TCU_TCU_CTRL_AUX20_MASK) #define MMU_TCU_TCU_CTRL_AUX21_MASK (0x200000U) #define MMU_TCU_TCU_CTRL_AUX21_SHIFT (21U) /*! AUX21 - AUX21 */ #define MMU_TCU_TCU_CTRL_AUX21(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX21_SHIFT)) & MMU_TCU_TCU_CTRL_AUX21_MASK) #define MMU_TCU_TCU_CTRL_AUX22_MASK (0x400000U) #define MMU_TCU_TCU_CTRL_AUX22_SHIFT (22U) /*! AUX22 - AUX22 */ #define MMU_TCU_TCU_CTRL_AUX22(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX22_SHIFT)) & MMU_TCU_TCU_CTRL_AUX22_MASK) #define MMU_TCU_TCU_CTRL_AUX23_MASK (0x800000U) #define MMU_TCU_TCU_CTRL_AUX23_SHIFT (23U) /*! AUX23 - AUX23 */ #define MMU_TCU_TCU_CTRL_AUX23(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX23_SHIFT)) & MMU_TCU_TCU_CTRL_AUX23_MASK) #define MMU_TCU_TCU_CTRL_AUX24_MASK (0x1000000U) #define MMU_TCU_TCU_CTRL_AUX24_SHIFT (24U) /*! AUX24 - AUX24 */ #define MMU_TCU_TCU_CTRL_AUX24(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX24_SHIFT)) & MMU_TCU_TCU_CTRL_AUX24_MASK) #define MMU_TCU_TCU_CTRL_AUX25_MASK (0x2000000U) #define MMU_TCU_TCU_CTRL_AUX25_SHIFT (25U) /*! AUX25 - AUX25 */ #define MMU_TCU_TCU_CTRL_AUX25(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX25_SHIFT)) & MMU_TCU_TCU_CTRL_AUX25_MASK) #define MMU_TCU_TCU_CTRL_AUX26_MASK (0x4000000U) #define MMU_TCU_TCU_CTRL_AUX26_SHIFT (26U) /*! AUX26 - AUX26 */ #define MMU_TCU_TCU_CTRL_AUX26(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX26_SHIFT)) & MMU_TCU_TCU_CTRL_AUX26_MASK) #define MMU_TCU_TCU_CTRL_AUX27_MASK (0x8000000U) #define MMU_TCU_TCU_CTRL_AUX27_SHIFT (27U) /*! AUX27 - AUX27 */ #define MMU_TCU_TCU_CTRL_AUX27(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX27_SHIFT)) & MMU_TCU_TCU_CTRL_AUX27_MASK) #define MMU_TCU_TCU_CTRL_AUX28_MASK (0x10000000U) #define MMU_TCU_TCU_CTRL_AUX28_SHIFT (28U) /*! AUX28 - AUX28 */ #define MMU_TCU_TCU_CTRL_AUX28(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX28_SHIFT)) & MMU_TCU_TCU_CTRL_AUX28_MASK) #define MMU_TCU_TCU_CTRL_AUX29_MASK (0x20000000U) #define MMU_TCU_TCU_CTRL_AUX29_SHIFT (29U) /*! AUX29 - AUX29 */ #define MMU_TCU_TCU_CTRL_AUX29(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX29_SHIFT)) & MMU_TCU_TCU_CTRL_AUX29_MASK) #define MMU_TCU_TCU_CTRL_AUX30_MASK (0x40000000U) #define MMU_TCU_TCU_CTRL_AUX30_SHIFT (30U) /*! AUX30 - AUX30 */ #define MMU_TCU_TCU_CTRL_AUX30(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX30_SHIFT)) & MMU_TCU_TCU_CTRL_AUX30_MASK) #define MMU_TCU_TCU_CTRL_AUX31_MASK (0x80000000U) #define MMU_TCU_TCU_CTRL_AUX31_SHIFT (31U) /*! AUX31 - AUX31 */ #define MMU_TCU_TCU_CTRL_AUX31(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CTRL_AUX31_SHIFT)) & MMU_TCU_TCU_CTRL_AUX31_MASK) /*! @} */ /*! @name TCU_QOS - TCU Quality of Service Register */ /*! @{ */ #define MMU_TCU_TCU_QOS_QOS_PTW0_MASK (0xFU) #define MMU_TCU_TCU_QOS_QOS_PTW0_SHIFT (0U) /*! QOS_PTW0 - QOS_PTW0 */ #define MMU_TCU_TCU_QOS_QOS_PTW0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_QOS_QOS_PTW0_SHIFT)) & MMU_TCU_TCU_QOS_QOS_PTW0_MASK) #define MMU_TCU_TCU_QOS_QOS_PTW1_MASK (0xF0U) #define MMU_TCU_TCU_QOS_QOS_PTW1_SHIFT (4U) /*! QOS_PTW1 - QOS_PTW1 */ #define MMU_TCU_TCU_QOS_QOS_PTW1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_QOS_QOS_PTW1_SHIFT)) & MMU_TCU_TCU_QOS_QOS_PTW1_MASK) #define MMU_TCU_TCU_QOS_QOS_PTW2_MASK (0xF00U) #define MMU_TCU_TCU_QOS_QOS_PTW2_SHIFT (8U) /*! QOS_PTW2 - QOS_PTW2 */ #define MMU_TCU_TCU_QOS_QOS_PTW2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_QOS_QOS_PTW2_SHIFT)) & MMU_TCU_TCU_QOS_QOS_PTW2_MASK) #define MMU_TCU_TCU_QOS_QOS_PTW3_MASK (0xF000U) #define MMU_TCU_TCU_QOS_QOS_PTW3_SHIFT (12U) /*! QOS_PTW3 - QOS_PTW3 */ #define MMU_TCU_TCU_QOS_QOS_PTW3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_QOS_QOS_PTW3_SHIFT)) & MMU_TCU_TCU_QOS_QOS_PTW3_MASK) #define MMU_TCU_TCU_QOS_QOS_QUEUE_MASK (0xF0000U) #define MMU_TCU_TCU_QOS_QOS_QUEUE_SHIFT (16U) /*! QOS_QUEUE - QOS_QUEUE */ #define MMU_TCU_TCU_QOS_QOS_QUEUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_QOS_QOS_QUEUE_SHIFT)) & MMU_TCU_TCU_QOS_QOS_QUEUE_MASK) #define MMU_TCU_TCU_QOS_QOS_MSI_MASK (0xF00000U) #define MMU_TCU_TCU_QOS_QOS_MSI_SHIFT (20U) /*! QOS_MSI - QOS_MSI */ #define MMU_TCU_TCU_QOS_QOS_MSI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_QOS_QOS_MSI_SHIFT)) & MMU_TCU_TCU_QOS_QOS_MSI_MASK) #define MMU_TCU_TCU_QOS_QOS_DVMSYNC_MASK (0xF000000U) #define MMU_TCU_TCU_QOS_QOS_DVMSYNC_SHIFT (24U) /*! QOS_DVMSYNC - QOS_DVMSYNC */ #define MMU_TCU_TCU_QOS_QOS_DVMSYNC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_QOS_QOS_DVMSYNC_SHIFT)) & MMU_TCU_TCU_QOS_QOS_DVMSYNC_MASK) /*! @} */ /*! @name TCU_CFG - TCU Configuration Information Register */ /*! @{ */ #define MMU_TCU_TCU_CFG_XLATE_SLOTS_MASK (0xFFF0U) #define MMU_TCU_TCU_CFG_XLATE_SLOTS_SHIFT (4U) /*! XLATE_SLOTS - XLATE_SLOTS */ #define MMU_TCU_TCU_CFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_CFG_XLATE_SLOTS_SHIFT)) & MMU_TCU_TCU_CFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TCU_STATUS - TCU Status Information Register */ /*! @{ */ #define MMU_TCU_TCU_STATUS_GNT_XLATE_SLOTS_MASK (0xFFF0U) #define MMU_TCU_TCU_STATUS_GNT_XLATE_SLOTS_SHIFT (4U) /*! GNT_XLATE_SLOTS - GNT_XLATE_SLOTS */ #define MMU_TCU_TCU_STATUS_GNT_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_STATUS_GNT_XLATE_SLOTS_SHIFT)) & MMU_TCU_TCU_STATUS_GNT_XLATE_SLOTS_MASK) /*! @} */ /*! @name TCU_SCR - TCU Secure Control Register */ /*! @{ */ #define MMU_TCU_TCU_SCR_NS_UARCH_MASK (0x1U) #define MMU_TCU_TCU_SCR_NS_UARCH_SHIFT (0U) /*! NS_UARCH - NS_UARCH */ #define MMU_TCU_TCU_SCR_NS_UARCH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SCR_NS_UARCH_SHIFT)) & MMU_TCU_TCU_SCR_NS_UARCH_MASK) #define MMU_TCU_TCU_SCR_NS_RAS_MASK (0x2U) #define MMU_TCU_TCU_SCR_NS_RAS_SHIFT (1U) /*! NS_RAS - NS_RAS */ #define MMU_TCU_TCU_SCR_NS_RAS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SCR_NS_RAS_SHIFT)) & MMU_TCU_TCU_SCR_NS_RAS_MASK) #define MMU_TCU_TCU_SCR_NS_INIT_MASK (0x8U) #define MMU_TCU_TCU_SCR_NS_INIT_SHIFT (3U) /*! NS_INIT - NS_INIT */ #define MMU_TCU_TCU_SCR_NS_INIT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SCR_NS_INIT_SHIFT)) & MMU_TCU_TCU_SCR_NS_INIT_MASK) /*! @} */ /*! @name ITEN - ITEN */ /*! @{ */ #define MMU_TCU_ITEN_ITEN_MASK (0x1U) #define MMU_TCU_ITEN_ITEN_SHIFT (0U) /*! ITEN - ITEN */ #define MMU_TCU_ITEN_ITEN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITEN_ITEN_SHIFT)) & MMU_TCU_ITEN_ITEN_MASK) /*! @} */ /*! @name ITOP_PIU - ITOP_PIU */ /*! @{ */ #define MMU_TCU_ITOP_PIU_ras_cri_MASK (0x1U) #define MMU_TCU_ITOP_PIU_ras_cri_SHIFT (0U) /*! ras_cri - ras_cri */ #define MMU_TCU_ITOP_PIU_ras_cri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_ras_cri_SHIFT)) & MMU_TCU_ITOP_PIU_ras_cri_MASK) #define MMU_TCU_ITOP_PIU_ras_eri_MASK (0x2U) #define MMU_TCU_ITOP_PIU_ras_eri_SHIFT (1U) /*! ras_eri - ras_eri */ #define MMU_TCU_ITOP_PIU_ras_eri(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_ras_eri_SHIFT)) & MMU_TCU_ITOP_PIU_ras_eri_MASK) #define MMU_TCU_ITOP_PIU_ras_fhi_MASK (0x4U) #define MMU_TCU_ITOP_PIU_ras_fhi_SHIFT (2U) /*! ras_fhi - ras_fhi */ #define MMU_TCU_ITOP_PIU_ras_fhi(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_ras_fhi_SHIFT)) & MMU_TCU_ITOP_PIU_ras_fhi_MASK) #define MMU_TCU_ITOP_PIU_evento_MASK (0x8U) #define MMU_TCU_ITOP_PIU_evento_SHIFT (3U) /*! evento - evento */ #define MMU_TCU_ITOP_PIU_evento(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_evento_SHIFT)) & MMU_TCU_ITOP_PIU_evento_MASK) #define MMU_TCU_ITOP_PIU_global_irpt_s_MASK (0x10U) #define MMU_TCU_ITOP_PIU_global_irpt_s_SHIFT (4U) /*! global_irpt_s - global_irpt_s */ #define MMU_TCU_ITOP_PIU_global_irpt_s(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_global_irpt_s_SHIFT)) & MMU_TCU_ITOP_PIU_global_irpt_s_MASK) #define MMU_TCU_ITOP_PIU_global_irpt_ns_MASK (0x20U) #define MMU_TCU_ITOP_PIU_global_irpt_ns_SHIFT (5U) /*! global_irpt_ns - global_irpt_ns */ #define MMU_TCU_ITOP_PIU_global_irpt_ns(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_global_irpt_ns_SHIFT)) & MMU_TCU_ITOP_PIU_global_irpt_ns_MASK) #define MMU_TCU_ITOP_PIU_cmd_sync_irpt_s_MASK (0x40U) #define MMU_TCU_ITOP_PIU_cmd_sync_irpt_s_SHIFT (6U) /*! cmd_sync_irpt_s - cmd_sync_irpt_s */ #define MMU_TCU_ITOP_PIU_cmd_sync_irpt_s(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_cmd_sync_irpt_s_SHIFT)) & MMU_TCU_ITOP_PIU_cmd_sync_irpt_s_MASK) #define MMU_TCU_ITOP_PIU_cmd_sync_irpt_ns_MASK (0x80U) #define MMU_TCU_ITOP_PIU_cmd_sync_irpt_ns_SHIFT (7U) /*! cmd_sync_irpt_ns - cmd_sync_irpt_ns */ #define MMU_TCU_ITOP_PIU_cmd_sync_irpt_ns(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_cmd_sync_irpt_ns_SHIFT)) & MMU_TCU_ITOP_PIU_cmd_sync_irpt_ns_MASK) #define MMU_TCU_ITOP_PIU_pri_q_irpt_MASK (0x100U) #define MMU_TCU_ITOP_PIU_pri_q_irpt_SHIFT (8U) /*! pri_q_irpt - pri_q_irpt */ #define MMU_TCU_ITOP_PIU_pri_q_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_pri_q_irpt_SHIFT)) & MMU_TCU_ITOP_PIU_pri_q_irpt_MASK) #define MMU_TCU_ITOP_PIU_event_q_irpt_s_MASK (0x200U) #define MMU_TCU_ITOP_PIU_event_q_irpt_s_SHIFT (9U) /*! event_q_irpt_s - event_q_irpt_s */ #define MMU_TCU_ITOP_PIU_event_q_irpt_s(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_event_q_irpt_s_SHIFT)) & MMU_TCU_ITOP_PIU_event_q_irpt_s_MASK) #define MMU_TCU_ITOP_PIU_event_q_irpt_ns_MASK (0x400U) #define MMU_TCU_ITOP_PIU_event_q_irpt_ns_SHIFT (10U) /*! event_q_irpt_ns - event_q_irpt_ns */ #define MMU_TCU_ITOP_PIU_event_q_irpt_ns(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_PIU_event_q_irpt_ns_SHIFT)) & MMU_TCU_ITOP_PIU_event_q_irpt_ns_MASK) /*! @} */ /*! @name ITOP_TMU - ITOP_TMU */ /*! @{ */ #define MMU_TCU_ITOP_TMU_pmu_snapshot_ack_MASK (0x1U) #define MMU_TCU_ITOP_TMU_pmu_snapshot_ack_SHIFT (0U) /*! pmu_snapshot_ack - pmu_snapshot_ack */ #define MMU_TCU_ITOP_TMU_pmu_snapshot_ack(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_TMU_pmu_snapshot_ack_SHIFT)) & MMU_TCU_ITOP_TMU_pmu_snapshot_ack_MASK) #define MMU_TCU_ITOP_TMU_pmu_irpt_MASK (0x2U) #define MMU_TCU_ITOP_TMU_pmu_irpt_SHIFT (1U) /*! pmu_irpt - pmu_irpt */ #define MMU_TCU_ITOP_TMU_pmu_irpt(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITOP_TMU_pmu_irpt_SHIFT)) & MMU_TCU_ITOP_TMU_pmu_irpt_MASK) /*! @} */ /*! @name ITIN_TMU - ITIN_TMU */ /*! @{ */ #define MMU_TCU_ITIN_TMU_pmu_snapshot_req_MASK (0x1U) #define MMU_TCU_ITIN_TMU_pmu_snapshot_req_SHIFT (0U) /*! pmu_snapshot_req - pmu_snapshot_req */ #define MMU_TCU_ITIN_TMU_pmu_snapshot_req(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_ITIN_TMU_pmu_snapshot_req_SHIFT)) & MMU_TCU_ITIN_TMU_pmu_snapshot_req_MASK) /*! @} */ /*! @name TCU_SYSDISC0 - TCU_SYSDISC0 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC0_TCUCFG_WC_DEPTH_MASK (0x1FFFFU) #define MMU_TCU_TCU_SYSDISC0_TCUCFG_WC_DEPTH_SHIFT (0U) /*! TCUCFG_WC_DEPTH - TCUCFG_WC_DEPTH */ #define MMU_TCU_TCU_SYSDISC0_TCUCFG_WC_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC0_TCUCFG_WC_DEPTH_SHIFT)) & MMU_TCU_TCU_SYSDISC0_TCUCFG_WC_DEPTH_MASK) /*! @} */ /*! @name TCU_SYSDISC1 - TCU_SYSDISC2 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC1_TCUCFG_CC_DEPTH_MASK (0x1FFFU) #define MMU_TCU_TCU_SYSDISC1_TCUCFG_CC_DEPTH_SHIFT (0U) /*! TCUCFG_CC_DEPTH - TCUCFG_CC_DEPTH */ #define MMU_TCU_TCU_SYSDISC1_TCUCFG_CC_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC1_TCUCFG_CC_DEPTH_SHIFT)) & MMU_TCU_TCU_SYSDISC1_TCUCFG_CC_DEPTH_MASK) /*! @} */ /*! @name TCU_SYSDISC2 - TCU_SYSDISC2 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC2_TCUCFG_WC_WAYS_MASK (0x1FU) #define MMU_TCU_TCU_SYSDISC2_TCUCFG_WC_WAYS_SHIFT (0U) /*! TCUCFG_WC_WAYS - TCUCFG_WC_WAYS */ #define MMU_TCU_TCU_SYSDISC2_TCUCFG_WC_WAYS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC2_TCUCFG_WC_WAYS_SHIFT)) & MMU_TCU_TCU_SYSDISC2_TCUCFG_WC_WAYS_MASK) /*! @} */ /*! @name TCU_SYSDISC3 - TCU_SYSDISC3 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC3_TCUCFG_WC_BANKS_MASK (0x7U) #define MMU_TCU_TCU_SYSDISC3_TCUCFG_WC_BANKS_SHIFT (0U) /*! TCUCFG_WC_BANKS - TCUCFG_WC_BANKS */ #define MMU_TCU_TCU_SYSDISC3_TCUCFG_WC_BANKS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC3_TCUCFG_WC_BANKS_SHIFT)) & MMU_TCU_TCU_SYSDISC3_TCUCFG_WC_BANKS_MASK) /*! @} */ /*! @name TCU_SYSDISC4 - TCU_SYSDISC4 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC4_TCUCFG_XLATE_SLOTS_MASK (0x1FFFU) #define MMU_TCU_TCU_SYSDISC4_TCUCFG_XLATE_SLOTS_SHIFT (0U) /*! TCUCFG_XLATE_SLOTS - TCUCFG_XLATE_SLOTS */ #define MMU_TCU_TCU_SYSDISC4_TCUCFG_XLATE_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC4_TCUCFG_XLATE_SLOTS_SHIFT)) & MMU_TCU_TCU_SYSDISC4_TCUCFG_XLATE_SLOTS_MASK) /*! @} */ /*! @name TCU_SYSDISC5 - TCU_SYSDISC5 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC5_TCUCFG_PTW_SLOTS_MASK (0x3FFU) #define MMU_TCU_TCU_SYSDISC5_TCUCFG_PTW_SLOTS_SHIFT (0U) /*! TCUCFG_PTW_SLOTS - TCUCFG_PTW_SLOTS */ #define MMU_TCU_TCU_SYSDISC5_TCUCFG_PTW_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC5_TCUCFG_PTW_SLOTS_SHIFT)) & MMU_TCU_TCU_SYSDISC5_TCUCFG_PTW_SLOTS_MASK) /*! @} */ /*! @name TCU_SYSDISC6 - TCU_SYSDISC6 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC6_TCUCFG_CTW_SLOTS_MASK (0x7U) #define MMU_TCU_TCU_SYSDISC6_TCUCFG_CTW_SLOTS_SHIFT (0U) /*! TCUCFG_CTW_SLOTS - TCUCFG_CTW_SLOTS */ #define MMU_TCU_TCU_SYSDISC6_TCUCFG_CTW_SLOTS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC6_TCUCFG_CTW_SLOTS_SHIFT)) & MMU_TCU_TCU_SYSDISC6_TCUCFG_CTW_SLOTS_MASK) /*! @} */ /*! @name TCU_SYSDISC7 - TCU_SYSDISC7 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC7_TCUCFG_CC_IDXGEN_MODE_MASK (0x1U) #define MMU_TCU_TCU_SYSDISC7_TCUCFG_CC_IDXGEN_MODE_SHIFT (0U) /*! TCUCFG_CC_IDXGEN_MODE - TCUCFG_CC_IDXGEN_MODE */ #define MMU_TCU_TCU_SYSDISC7_TCUCFG_CC_IDXGEN_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC7_TCUCFG_CC_IDXGEN_MODE_SHIFT)) & MMU_TCU_TCU_SYSDISC7_TCUCFG_CC_IDXGEN_MODE_MASK) /*! @} */ /*! @name TCU_SYSDISC8 - TCU_SYSDISC8 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC8_TCUCFG_DTI_ATS_MASK (0xFU) #define MMU_TCU_TCU_SYSDISC8_TCUCFG_DTI_ATS_SHIFT (0U) /*! TCUCFG_DTI_ATS - TCUCFG_DTI_ATS */ #define MMU_TCU_TCU_SYSDISC8_TCUCFG_DTI_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC8_TCUCFG_DTI_ATS_SHIFT)) & MMU_TCU_TCU_SYSDISC8_TCUCFG_DTI_ATS_MASK) /*! @} */ /*! @name TCU_SYSDISC9 - TCU_SYSDISC9 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC9_TCUCFG_NUM_TBU_MASK (0x3FU) #define MMU_TCU_TCU_SYSDISC9_TCUCFG_NUM_TBU_SHIFT (0U) /*! TCUCFG_NUM_TBU - TCUCFG_NUM_TBU */ #define MMU_TCU_TCU_SYSDISC9_TCUCFG_NUM_TBU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC9_TCUCFG_NUM_TBU_SHIFT)) & MMU_TCU_TCU_SYSDISC9_TCUCFG_NUM_TBU_MASK) /*! @} */ /*! @name TCU_SYSDISC10 - TCU_SYSDISC10 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC10_TCUCFG_PMU_COUNTERS_MASK (0x3FU) #define MMU_TCU_TCU_SYSDISC10_TCUCFG_PMU_COUNTERS_SHIFT (0U) /*! TCUCFG_PMU_COUNTERS - TCUCFG_PMU_COUNTERS */ #define MMU_TCU_TCU_SYSDISC10_TCUCFG_PMU_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC10_TCUCFG_PMU_COUNTERS_SHIFT)) & MMU_TCU_TCU_SYSDISC10_TCUCFG_PMU_COUNTERS_MASK) /*! @} */ /*! @name TCU_SYSDISC11 - TCU_SYSDISC11 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC11_TCUCFG_PARTID_WIDTH_MASK (0xFU) #define MMU_TCU_TCU_SYSDISC11_TCUCFG_PARTID_WIDTH_SHIFT (0U) /*! TCUCFG_PARTID_WIDTH - TCUCFG_PARTID_WIDTH */ #define MMU_TCU_TCU_SYSDISC11_TCUCFG_PARTID_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC11_TCUCFG_PARTID_WIDTH_SHIFT)) & MMU_TCU_TCU_SYSDISC11_TCUCFG_PARTID_WIDTH_MASK) /*! @} */ /*! @name TCU_SYSDISC12 - TCU_SYSDISC12 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC12_TCUCFG_HZU_DEPTH_MASK (0xFU) #define MMU_TCU_TCU_SYSDISC12_TCUCFG_HZU_DEPTH_SHIFT (0U) /*! TCUCFG_HZU_DEPTH - TCUCFG_HZU_DEPTH */ #define MMU_TCU_TCU_SYSDISC12_TCUCFG_HZU_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC12_TCUCFG_HZU_DEPTH_SHIFT)) & MMU_TCU_TCU_SYSDISC12_TCUCFG_HZU_DEPTH_MASK) /*! @} */ /*! @name TCU_SYSDISC13 - TCU_SYSDISC13 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC13_TCUCFG_PREFETCH_SUPPORTED_MASK (0x1U) #define MMU_TCU_TCU_SYSDISC13_TCUCFG_PREFETCH_SUPPORTED_SHIFT (0U) /*! TCUCFG_PREFETCH_SUPPORTED - TCUCFG_PREFETCH_SUPPORTED */ #define MMU_TCU_TCU_SYSDISC13_TCUCFG_PREFETCH_SUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC13_TCUCFG_PREFETCH_SUPPORTED_SHIFT)) & MMU_TCU_TCU_SYSDISC13_TCUCFG_PREFETCH_SUPPORTED_MASK) /*! @} */ /*! @name TCU_SYSDISC14 - TCU_SYSDISC14 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC14_TCUCFG_DATARAM_TYPE_MASK (0x3U) #define MMU_TCU_TCU_SYSDISC14_TCUCFG_DATARAM_TYPE_SHIFT (0U) /*! TCUCFG_DATARAM_TYPE - TCUCFG_DATARAM_TYPE */ #define MMU_TCU_TCU_SYSDISC14_TCUCFG_DATARAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC14_TCUCFG_DATARAM_TYPE_SHIFT)) & MMU_TCU_TCU_SYSDISC14_TCUCFG_DATARAM_TYPE_MASK) /*! @} */ /*! @name TCU_SYSDISC15 - TCU_SYSDISC15 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC15_TCUCFG_SLOTRAM_TYPE_MASK (0x3U) #define MMU_TCU_TCU_SYSDISC15_TCUCFG_SLOTRAM_TYPE_SHIFT (0U) /*! TCUCFG_SLOTRAM_TYPE - TCUCFG_SLOTRAM_TYPE */ #define MMU_TCU_TCU_SYSDISC15_TCUCFG_SLOTRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC15_TCUCFG_SLOTRAM_TYPE_SHIFT)) & MMU_TCU_TCU_SYSDISC15_TCUCFG_SLOTRAM_TYPE_MASK) /*! @} */ /*! @name TCU_SYSDISC16 - TCU_SYSDISC16 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC16_TCUCFG_CACHERAM_TYPE_MASK (0x3U) #define MMU_TCU_TCU_SYSDISC16_TCUCFG_CACHERAM_TYPE_SHIFT (0U) /*! TCUCFG_CACHERAM_TYPE - TCUCFG_CACHERAM_TYPE */ #define MMU_TCU_TCU_SYSDISC16_TCUCFG_CACHERAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC16_TCUCFG_CACHERAM_TYPE_SHIFT)) & MMU_TCU_TCU_SYSDISC16_TCUCFG_CACHERAM_TYPE_MASK) /*! @} */ /*! @name TCU_SYSDISC17 - TCU_SYSDISC17 */ /*! @{ */ #define MMU_TCU_TCU_SYSDISC17_TCUCFG_QTW_DATA_WIDTH_MASK (0x3FFU) #define MMU_TCU_TCU_SYSDISC17_TCUCFG_QTW_DATA_WIDTH_SHIFT (0U) /*! TCUCFG_QTW_DATA_WIDTH - TCUCFG_QTW_DATA_WIDTH */ #define MMU_TCU_TCU_SYSDISC17_TCUCFG_QTW_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_SYSDISC17_TCUCFG_QTW_DATA_WIDTH_SHIFT)) & MMU_TCU_TCU_SYSDISC17_TCUCFG_QTW_DATA_WIDTH_MASK) /*! @} */ /*! @name TCU_ERRFR_LO - TCU Error Feature Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_TCU_ERRFR_LO_ED_MASK (0x3U) #define MMU_TCU_TCU_ERRFR_LO_ED_SHIFT (0U) /*! ED - ED */ #define MMU_TCU_TCU_ERRFR_LO_ED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_ED_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_ED_MASK) #define MMU_TCU_TCU_ERRFR_LO_UI_MASK (0x30U) #define MMU_TCU_TCU_ERRFR_LO_UI_SHIFT (4U) /*! UI - UI */ #define MMU_TCU_TCU_ERRFR_LO_UI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_UI_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_UI_MASK) #define MMU_TCU_TCU_ERRFR_LO_FI_MASK (0xC0U) #define MMU_TCU_TCU_ERRFR_LO_FI_SHIFT (6U) /*! FI - FI */ #define MMU_TCU_TCU_ERRFR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_FI_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_FI_MASK) #define MMU_TCU_TCU_ERRFR_LO_UE_MASK (0x300U) #define MMU_TCU_TCU_ERRFR_LO_UE_SHIFT (8U) /*! UE - UE */ #define MMU_TCU_TCU_ERRFR_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_UE_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_UE_MASK) #define MMU_TCU_TCU_ERRFR_LO_CFI_MASK (0xC00U) #define MMU_TCU_TCU_ERRFR_LO_CFI_SHIFT (10U) /*! CFI - CFI */ #define MMU_TCU_TCU_ERRFR_LO_CFI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_CFI_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_CFI_MASK) #define MMU_TCU_TCU_ERRFR_LO_CEC_MASK (0x7000U) #define MMU_TCU_TCU_ERRFR_LO_CEC_SHIFT (12U) /*! CEC - CEC */ #define MMU_TCU_TCU_ERRFR_LO_CEC(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_CEC_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_CEC_MASK) #define MMU_TCU_TCU_ERRFR_LO_RP_MASK (0x8000U) #define MMU_TCU_TCU_ERRFR_LO_RP_SHIFT (15U) /*! RP - RP */ #define MMU_TCU_TCU_ERRFR_LO_RP(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_RP_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_RP_MASK) #define MMU_TCU_TCU_ERRFR_LO_DUI_MASK (0x30000U) #define MMU_TCU_TCU_ERRFR_LO_DUI_SHIFT (16U) /*! DUI - DUI */ #define MMU_TCU_TCU_ERRFR_LO_DUI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_DUI_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_DUI_MASK) #define MMU_TCU_TCU_ERRFR_LO_CEO_MASK (0xC0000U) #define MMU_TCU_TCU_ERRFR_LO_CEO_SHIFT (18U) /*! CEO - CEO */ #define MMU_TCU_TCU_ERRFR_LO_CEO(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_CEO_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_CEO_MASK) #define MMU_TCU_TCU_ERRFR_LO_INJ_MASK (0x300000U) #define MMU_TCU_TCU_ERRFR_LO_INJ_SHIFT (20U) /*! INJ - INJ */ #define MMU_TCU_TCU_ERRFR_LO_INJ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_INJ_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_INJ_MASK) #define MMU_TCU_TCU_ERRFR_LO_CI_MASK (0xC00000U) #define MMU_TCU_TCU_ERRFR_LO_CI_SHIFT (22U) /*! CI - CI */ #define MMU_TCU_TCU_ERRFR_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_CI_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_CI_MASK) #define MMU_TCU_TCU_ERRFR_LO_TS_MASK (0x3000000U) #define MMU_TCU_TCU_ERRFR_LO_TS_SHIFT (24U) /*! TS - TS */ #define MMU_TCU_TCU_ERRFR_LO_TS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRFR_LO_TS_SHIFT)) & MMU_TCU_TCU_ERRFR_LO_TS_MASK) /*! @} */ /*! @name TCU_ERRCTLR_LO - TCU Error Control Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_TCU_ERRCTLR_LO_FI_MASK (0x8U) #define MMU_TCU_TCU_ERRCTLR_LO_FI_SHIFT (3U) /*! FI - FI */ #define MMU_TCU_TCU_ERRCTLR_LO_FI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRCTLR_LO_FI_SHIFT)) & MMU_TCU_TCU_ERRCTLR_LO_FI_MASK) /*! @} */ /*! @name TCU_ERRSTATUS_LO - TCU Error Record Primary Syndrome Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_TCU_ERRSTATUS_LO_SERR_MASK (0xFFU) #define MMU_TCU_TCU_ERRSTATUS_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TCU_TCU_ERRSTATUS_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_SERR_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_SERR_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_IERR_MASK (0xFF00U) #define MMU_TCU_TCU_ERRSTATUS_LO_IERR_SHIFT (8U) /*! IERR - IERR * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00001000.. * 0b00001001.. * 0b00001010.. * 0b00001011.. * 0b00001100.. * 0b00001101.. * 0b00001110.. * 0b00001111.. * 0b00010000.. * 0b00010001.. * 0b00010010.. */ #define MMU_TCU_TCU_ERRSTATUS_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_IERR_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_IERR_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_CI_MASK (0x80000U) #define MMU_TCU_TCU_ERRSTATUS_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TCU_TCU_ERRSTATUS_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_CI_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_CI_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_UET_MASK (0x300000U) #define MMU_TCU_TCU_ERRSTATUS_LO_UET_SHIFT (20U) /*! UET - UET * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TCU_TCU_ERRSTATUS_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_UET_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_UET_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_PN_MASK (0x400000U) #define MMU_TCU_TCU_ERRSTATUS_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TCU_TCU_ERRSTATUS_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_PN_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_PN_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_DE_MASK (0x800000U) #define MMU_TCU_TCU_ERRSTATUS_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TCU_TCU_ERRSTATUS_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_DE_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_DE_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_CE_MASK (0x3000000U) #define MMU_TCU_TCU_ERRSTATUS_LO_CE_SHIFT (24U) /*! CE - CE * 0b00..2'b00 * 0b11..2'b11 */ #define MMU_TCU_TCU_ERRSTATUS_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_CE_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_CE_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_MV_MASK (0x4000000U) #define MMU_TCU_TCU_ERRSTATUS_LO_MV_SHIFT (26U) /*! MV - MV */ #define MMU_TCU_TCU_ERRSTATUS_LO_MV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_MV_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_MV_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_OF_MASK (0x8000000U) #define MMU_TCU_TCU_ERRSTATUS_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TCU_TCU_ERRSTATUS_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_OF_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_OF_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_ER_MASK (0x10000000U) #define MMU_TCU_TCU_ERRSTATUS_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TCU_TCU_ERRSTATUS_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_ER_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_ER_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_UE_MASK (0x20000000U) #define MMU_TCU_TCU_ERRSTATUS_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TCU_TCU_ERRSTATUS_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_UE_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_UE_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_V_MASK (0x40000000U) #define MMU_TCU_TCU_ERRSTATUS_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TCU_TCU_ERRSTATUS_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_V_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_V_MASK) #define MMU_TCU_TCU_ERRSTATUS_LO_AV_MASK (0x80000000U) #define MMU_TCU_TCU_ERRSTATUS_LO_AV_SHIFT (31U) /*! AV - AV */ #define MMU_TCU_TCU_ERRSTATUS_LO_AV(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRSTATUS_LO_AV_SHIFT)) & MMU_TCU_TCU_ERRSTATUS_LO_AV_MASK) /*! @} */ /*! @name TCU_ERRGEN_LO - TCU Error Generation Register (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_TCU_ERRGEN_LO_SERR_MASK (0xFFU) #define MMU_TCU_TCU_ERRGEN_LO_SERR_SHIFT (0U) /*! SERR - SERR */ #define MMU_TCU_TCU_ERRGEN_LO_SERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_SERR_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_SERR_MASK) #define MMU_TCU_TCU_ERRGEN_LO_IERR_MASK (0xFF00U) #define MMU_TCU_TCU_ERRGEN_LO_IERR_SHIFT (8U) /*! IERR - IERR */ #define MMU_TCU_TCU_ERRGEN_LO_IERR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_IERR_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_IERR_MASK) #define MMU_TCU_TCU_ERRGEN_LO_CI_MASK (0x80000U) #define MMU_TCU_TCU_ERRGEN_LO_CI_SHIFT (19U) /*! CI - CI */ #define MMU_TCU_TCU_ERRGEN_LO_CI(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_CI_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_CI_MASK) #define MMU_TCU_TCU_ERRGEN_LO_UET_MASK (0x300000U) #define MMU_TCU_TCU_ERRGEN_LO_UET_SHIFT (20U) /*! UET - UET */ #define MMU_TCU_TCU_ERRGEN_LO_UET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_UET_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_UET_MASK) #define MMU_TCU_TCU_ERRGEN_LO_PN_MASK (0x400000U) #define MMU_TCU_TCU_ERRGEN_LO_PN_SHIFT (22U) /*! PN - PN */ #define MMU_TCU_TCU_ERRGEN_LO_PN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_PN_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_PN_MASK) #define MMU_TCU_TCU_ERRGEN_LO_DE_MASK (0x800000U) #define MMU_TCU_TCU_ERRGEN_LO_DE_SHIFT (23U) /*! DE - DE */ #define MMU_TCU_TCU_ERRGEN_LO_DE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_DE_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_DE_MASK) #define MMU_TCU_TCU_ERRGEN_LO_CE_MASK (0x3000000U) #define MMU_TCU_TCU_ERRGEN_LO_CE_SHIFT (24U) /*! CE - CE */ #define MMU_TCU_TCU_ERRGEN_LO_CE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_CE_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_CE_MASK) #define MMU_TCU_TCU_ERRGEN_LO_OF_MASK (0x8000000U) #define MMU_TCU_TCU_ERRGEN_LO_OF_SHIFT (27U) /*! OF - OF */ #define MMU_TCU_TCU_ERRGEN_LO_OF(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_OF_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_OF_MASK) #define MMU_TCU_TCU_ERRGEN_LO_ER_MASK (0x10000000U) #define MMU_TCU_TCU_ERRGEN_LO_ER_SHIFT (28U) /*! ER - ER */ #define MMU_TCU_TCU_ERRGEN_LO_ER(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_ER_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_ER_MASK) #define MMU_TCU_TCU_ERRGEN_LO_UE_MASK (0x20000000U) #define MMU_TCU_TCU_ERRGEN_LO_UE_SHIFT (29U) /*! UE - UE */ #define MMU_TCU_TCU_ERRGEN_LO_UE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_UE_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_UE_MASK) #define MMU_TCU_TCU_ERRGEN_LO_V_MASK (0x40000000U) #define MMU_TCU_TCU_ERRGEN_LO_V_SHIFT (30U) /*! V - V */ #define MMU_TCU_TCU_ERRGEN_LO_V(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_ERRGEN_LO_V_SHIFT)) & MMU_TCU_TCU_ERRGEN_LO_V_MASK) /*! @} */ /*! @name TCU_NODE_CTRL0 - TCU Node Control Register 0 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL0_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL0_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL0_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL0_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL0_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL0_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL0_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL0_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL0_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL0_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL1 - TCU Node Control Register 1 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL1_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL1_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL1_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL1_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL1_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL1_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL1_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL1_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL1_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL1_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL2 - TCU Node Control Register 2 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL2_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL2_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL2_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL2_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL2_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL2_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL2_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL2_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL2_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL2_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL3 - TCU Node Control Register 3 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL3_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL3_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL3_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL3_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL3_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL3_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL3_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL3_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL3_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL3_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL4 - TCU Node Control Register 4 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL4_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL4_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL4_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL4_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL4_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL4_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL4_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL4_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL4_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL4_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL5 - TCU Node Control Register 5 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL5_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL5_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL5_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL5_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL5_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL5_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL5_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL5_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL5_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL5_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL6 - TCU Node Control Register 6 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL6_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL6_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL6_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL6_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL6_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL6_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL6_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL6_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL6_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL6_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL7 - TCU Node Control Register 7 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL7_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL7_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL7_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL7_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL7_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL7_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL7_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL7_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL7_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL7_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL8 - TCU Node Control Register 8 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL8_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL8_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL8_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL8_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL8_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL8_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL8_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL8_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL8_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL8_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL9 - TCU Node Control Register 9 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL9_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL9_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL9_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL9_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL9_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL9_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL9_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL9_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL9_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL9_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL10 - TCU Node Control Register 10 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL10_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL10_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL10_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL10_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL10_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL10_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL10_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL10_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL10_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL10_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL11 - TCU Node Control Register 11 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL11_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL11_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL11_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL11_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL11_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL11_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL11_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL11_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL11_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL11_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL12 - TCU Node Control Register 12 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL12_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL12_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL12_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL12_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL12_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL12_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL12_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL12_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL12_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL12_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_CTRL13 - TCU Node Control Register 13 */ /*! @{ */ #define MMU_TCU_TCU_NODE_CTRL13_PRI_LEVEL_MASK (0x3U) #define MMU_TCU_TCU_NODE_CTRL13_PRI_LEVEL_SHIFT (0U) /*! PRI_LEVEL - PRI_LEVEL */ #define MMU_TCU_TCU_NODE_CTRL13_PRI_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_PRI_LEVEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_PRI_LEVEL_MASK) #define MMU_TCU_TCU_NODE_CTRL13_PRIORITY_SEL_MASK (0x4U) #define MMU_TCU_TCU_NODE_CTRL13_PRIORITY_SEL_SHIFT (2U) /*! PRIORITY_SEL - PRIORITY_SEL */ #define MMU_TCU_TCU_NODE_CTRL13_PRIORITY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_PRIORITY_SEL_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_PRIORITY_SEL_MASK) #define MMU_TCU_TCU_NODE_CTRL13_DIS_DVM_MASK (0x10U) #define MMU_TCU_TCU_NODE_CTRL13_DIS_DVM_SHIFT (4U) /*! DIS_DVM - DIS_DVM */ #define MMU_TCU_TCU_NODE_CTRL13_DIS_DVM(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_DIS_DVM_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_DIS_DVM_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY0_MASK (0x30000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY0_SHIFT (16U) /*! LTI_PORT_PRIORITY0 - LTI_PORT_PRIORITY0 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY0(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY0_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY0_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY1_MASK (0xC0000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY1_SHIFT (18U) /*! LTI_PORT_PRIORITY1 - LTI_PORT_PRIORITY1 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY1(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY1_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY1_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY2_MASK (0x300000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY2_SHIFT (20U) /*! LTI_PORT_PRIORITY2 - LTI_PORT_PRIORITY2 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY2(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY2_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY2_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY3_MASK (0xC00000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY3_SHIFT (22U) /*! LTI_PORT_PRIORITY3 - LTI_PORT_PRIORITY3 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY3(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY3_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY3_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY4_MASK (0x3000000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY4_SHIFT (24U) /*! LTI_PORT_PRIORITY4 - LTI_PORT_PRIORITY4 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY4(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY4_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY4_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY5_MASK (0xC000000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY5_SHIFT (26U) /*! LTI_PORT_PRIORITY5 - LTI_PORT_PRIORITY5 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY5(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY5_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY5_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY6_MASK (0x30000000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY6_SHIFT (28U) /*! LTI_PORT_PRIORITY6 - LTI_PORT_PRIORITY6 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY6(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY6_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY6_MASK) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY7_MASK (0xC0000000U) #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY7_SHIFT (30U) /*! LTI_PORT_PRIORITY7 - LTI_PORT_PRIORITY7 */ #define MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY7(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY7_SHIFT)) & MMU_TCU_TCU_NODE_CTRL13_LTI_PORT_PRIORITY7_MASK) /*! @} */ /*! @name TCU_NODE_STATUS0 - TCU Node Status Register 0 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS0_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS0_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS0_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS0_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS0_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS0_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS0_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS0_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS0_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS0_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS1 - TCU Node Status Register 1 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS1_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS1_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS1_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS1_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS1_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS1_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS1_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS1_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS1_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS1_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS2 - TCU Node Status Register 2 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS2_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS2_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS2_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS2_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS2_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS2_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS2_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS2_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS2_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS2_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS3 - TCU Node Status Register 3 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS3_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS3_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS3_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS3_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS3_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS3_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS3_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS3_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS3_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS3_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS4 - TCU Node Status Register 4 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS4_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS4_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS4_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS4_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS4_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS4_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS4_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS4_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS4_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS4_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS5 - TCU Node Status Register 5 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS5_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS5_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS5_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS5_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS5_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS5_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS5_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS5_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS5_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS5_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS6 - TCU Node Status Register 6 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS6_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS6_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS6_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS6_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS6_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS6_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS6_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS6_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS6_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS6_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS7 - TCU Node Status Register 7 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS7_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS7_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS7_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS7_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS7_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS7_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS7_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS7_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS7_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS7_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS8 - TCU Node Status Register 8 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS8_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS8_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS8_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS8_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS8_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS8_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS8_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS8_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS8_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS8_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS9 - TCU Node Status Register 9 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS9_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS9_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS9_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS9_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS9_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS9_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS9_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS9_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS9_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS9_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS10 - TCU Node Status Register 10 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS10_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS10_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS10_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS10_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS10_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS10_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS10_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS10_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS10_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS10_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS11 - TCU Node Status Register 11 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS11_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS11_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS11_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS11_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS11_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS11_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS11_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS11_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS11_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS11_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS12 - TCU Node Status Register 12 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS12_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS12_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS12_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS12_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS12_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS12_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS12_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS12_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS12_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS12_ATS_MASK) /*! @} */ /*! @name TCU_NODE_STATUS13 - TCU Node Status Register 13 */ /*! @{ */ #define MMU_TCU_TCU_NODE_STATUS13_CONNECTED_MASK (0x1U) #define MMU_TCU_TCU_NODE_STATUS13_CONNECTED_SHIFT (0U) /*! CONNECTED - CONNECTED */ #define MMU_TCU_TCU_NODE_STATUS13_CONNECTED(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS13_CONNECTED_SHIFT)) & MMU_TCU_TCU_NODE_STATUS13_CONNECTED_MASK) #define MMU_TCU_TCU_NODE_STATUS13_ATS_MASK (0x2U) #define MMU_TCU_TCU_NODE_STATUS13_ATS_SHIFT (1U) /*! ATS - ATS */ #define MMU_TCU_TCU_NODE_STATUS13_ATS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_NODE_STATUS13_ATS_SHIFT)) & MMU_TCU_TCU_NODE_STATUS13_ATS_MASK) /*! @} */ /*! @name TCU_WC_S1L0_CMAX - TCU Walk Cache S1L0 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S1L0_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S1L0_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S1L0_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S1L0_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S1L0_CMAX_CMAX_MASK) /*! @} */ /*! @name TCU_WC_S1L1_CMAX - TCU Walk Cache S1L1 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S1L1_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S1L1_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S1L1_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S1L1_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S1L1_CMAX_CMAX_MASK) /*! @} */ /*! @name TCU_WC_S1L2_CMAX - TCU Walk Cache S1L2 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S1L2_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S1L2_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S1L2_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S1L2_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S1L2_CMAX_CMAX_MASK) /*! @} */ /*! @name TCU_WC_S1L3_CMAX - TCU Walk Cache S1L3 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S1L3_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S1L3_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S1L3_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S1L3_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S1L3_CMAX_CMAX_MASK) /*! @} */ /*! @name TCU_WC_S2L0_CMAX - TCU Walk Cache S2L0 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S2L0_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S2L0_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S2L0_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S2L0_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S2L0_CMAX_CMAX_MASK) /*! @} */ /*! @name TCU_WC_S2L1_CMAX - TCU Walk Cache S2L1 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S2L1_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S2L1_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S2L1_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S2L1_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S2L1_CMAX_CMAX_MASK) /*! @} */ /*! @name TCU_WC_S2L2_CMAX - TCU Walk Cache S2L2 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S2L2_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S2L2_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S2L2_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S2L2_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S2L2_CMAX_CMAX_MASK) /*! @} */ /*! @name TCU_WC_S2L3_CMAX - TCU Walk Cache S2L3 Max Capacity Register */ /*! @{ */ #define MMU_TCU_TCU_WC_S2L3_CMAX_CMAX_MASK (0xFFFFU) #define MMU_TCU_TCU_WC_S2L3_CMAX_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_TCU_WC_S2L3_CMAX_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_TCU_WC_S2L3_CMAX_CMAX_SHIFT)) & MMU_TCU_TCU_WC_S2L3_CMAX_CMAX_MASK) /*! @} */ /*! @name MPAMF_IDR_LO_S - MPAMF_IDR_s (Least Significant 32-bits) */ /*! @{ */ #define MMU_TCU_MPAMF_IDR_LO_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TCU_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TCU_MPAMF_IDR_LO_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_PARTID_MAX_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_PARTID_MAX_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TCU_MPAMF_IDR_LO_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TCU_MPAMF_IDR_LO_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_PMG_MAX_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_PMG_MAX_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK (0x1000000U) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT (24U) /*! HAS_CCAP_PART - HAS_CCAP_PART */ #define MMU_TCU_MPAMF_IDR_LO_S_HAS_CCAP_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_HAS_CCAP_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_HAS_CCAP_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK (0x2000000U) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT (25U) /*! HAS_CPOR_PART - HAS_CPOR_PART */ #define MMU_TCU_MPAMF_IDR_LO_S_HAS_CPOR_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_HAS_CPOR_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_HAS_CPOR_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK (0x4000000U) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT (26U) /*! HAS_MBW_PART - HAS_MBW_PART */ #define MMU_TCU_MPAMF_IDR_LO_S_HAS_MBW_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_HAS_MBW_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_HAS_MBW_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK (0x8000000U) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT (27U) /*! HAS_PRI_PART - HAS_PRI_PART */ #define MMU_TCU_MPAMF_IDR_LO_S_HAS_PRI_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_HAS_PRI_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_HAS_PRI_PART_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_EXT_MASK (0x10000000U) #define MMU_TCU_MPAMF_IDR_LO_S_EXT_SHIFT (28U) /*! EXT - EXT */ #define MMU_TCU_MPAMF_IDR_LO_S_EXT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_EXT_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_EXT_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK (0x20000000U) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT (29U) /*! HAS_IMPL_IDR - HAS_IMPL_IDR */ #define MMU_TCU_MPAMF_IDR_LO_S_HAS_IMPL_IDR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_HAS_IMPL_IDR_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_HAS_IMPL_IDR_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_MSMON_MASK (0x40000000U) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT (30U) /*! HAS_MSMON - HAS_MSMON */ #define MMU_TCU_MPAMF_IDR_LO_S_HAS_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_HAS_MSMON_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_HAS_MSMON_MASK) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK (0x80000000U) #define MMU_TCU_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT (31U) /*! HAS_PARTID_NRW - HAS_PARTID_NRW */ #define MMU_TCU_MPAMF_IDR_LO_S_HAS_PARTID_NRW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_LO_S_HAS_PARTID_NRW_SHIFT)) & MMU_TCU_MPAMF_IDR_LO_S_HAS_PARTID_NRW_MASK) /*! @} */ /*! @name MPAMF_IDR_HI_S - MPAMF_IDR_s (Most Significant 32-bits) */ /*! @{ */ #define MMU_TCU_MPAMF_IDR_HI_S_HAS_RIS_MASK (0x1U) #define MMU_TCU_MPAMF_IDR_HI_S_HAS_RIS_SHIFT (0U) /*! HAS_RIS - HAS_RIS */ #define MMU_TCU_MPAMF_IDR_HI_S_HAS_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_S_HAS_RIS_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_S_HAS_RIS_MASK) #define MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK (0x10U) #define MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT (4U) /*! NO_IMPL_PART - NO_IMPL_PART */ #define MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_PART(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_PART_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_PART_MASK) #define MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK (0x20U) #define MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT (5U) /*! NO_IMPL_MSMON - NO_IMPL_MSMON */ #define MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_MSMON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_MSMON_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_S_NO_IMPL_MSMON_MASK) #define MMU_TCU_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK (0x40U) #define MMU_TCU_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT (6U) /*! HAS_EXTD_ESR - HAS_EXTD_ESR */ #define MMU_TCU_MPAMF_IDR_HI_S_HAS_EXTD_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_S_HAS_EXTD_ESR_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_S_HAS_EXTD_ESR_MASK) #define MMU_TCU_MPAMF_IDR_HI_S_HAS_ESR_MASK (0x80U) #define MMU_TCU_MPAMF_IDR_HI_S_HAS_ESR_SHIFT (7U) /*! HAS_ESR - HAS_ESR */ #define MMU_TCU_MPAMF_IDR_HI_S_HAS_ESR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_S_HAS_ESR_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_S_HAS_ESR_MASK) #define MMU_TCU_MPAMF_IDR_HI_S_RIS_MAX_MASK (0xF000000U) #define MMU_TCU_MPAMF_IDR_HI_S_RIS_MAX_SHIFT (24U) /*! RIS_MAX - RIS_MAX */ #define MMU_TCU_MPAMF_IDR_HI_S_RIS_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IDR_HI_S_RIS_MAX_SHIFT)) & MMU_TCU_MPAMF_IDR_HI_S_RIS_MAX_MASK) /*! @} */ /*! @name MPAMF_SIDR_S - MPAMF_SIDR_s */ /*! @{ */ #define MMU_TCU_MPAMF_SIDR_S_PARTID_MAX_MASK (0xFFFFU) #define MMU_TCU_MPAMF_SIDR_S_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define MMU_TCU_MPAMF_SIDR_S_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_SIDR_S_PARTID_MAX_SHIFT)) & MMU_TCU_MPAMF_SIDR_S_PARTID_MAX_MASK) #define MMU_TCU_MPAMF_SIDR_S_PMG_MAX_MASK (0xFF0000U) #define MMU_TCU_MPAMF_SIDR_S_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define MMU_TCU_MPAMF_SIDR_S_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_SIDR_S_PMG_MAX_SHIFT)) & MMU_TCU_MPAMF_SIDR_S_PMG_MAX_MASK) /*! @} */ /*! @name MPAMF_IIDR_S - MPAMF_IIDR_s */ /*! @{ */ #define MMU_TCU_MPAMF_IIDR_S_Implementer_MASK (0xFFFU) #define MMU_TCU_MPAMF_IIDR_S_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define MMU_TCU_MPAMF_IIDR_S_Implementer(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_S_Implementer_SHIFT)) & MMU_TCU_MPAMF_IIDR_S_Implementer_MASK) #define MMU_TCU_MPAMF_IIDR_S_Revision_MASK (0xF000U) #define MMU_TCU_MPAMF_IIDR_S_Revision_SHIFT (12U) /*! Revision - Revision */ #define MMU_TCU_MPAMF_IIDR_S_Revision(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_S_Revision_SHIFT)) & MMU_TCU_MPAMF_IIDR_S_Revision_MASK) #define MMU_TCU_MPAMF_IIDR_S_Variant_MASK (0xF0000U) #define MMU_TCU_MPAMF_IIDR_S_Variant_SHIFT (16U) /*! Variant - Variant */ #define MMU_TCU_MPAMF_IIDR_S_Variant(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_S_Variant_SHIFT)) & MMU_TCU_MPAMF_IIDR_S_Variant_MASK) #define MMU_TCU_MPAMF_IIDR_S_ProductID_MASK (0xFFF00000U) #define MMU_TCU_MPAMF_IIDR_S_ProductID_SHIFT (20U) /*! ProductID - ProductID */ #define MMU_TCU_MPAMF_IIDR_S_ProductID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_IIDR_S_ProductID_SHIFT)) & MMU_TCU_MPAMF_IIDR_S_ProductID_MASK) /*! @} */ /*! @name MPAMF_AIDR_S - MPAMF_AIDR_s */ /*! @{ */ #define MMU_TCU_MPAMF_AIDR_S_ArchMinorRev_MASK (0xFU) #define MMU_TCU_MPAMF_AIDR_S_ArchMinorRev_SHIFT (0U) /*! ArchMinorRev - ArchMinorRev */ #define MMU_TCU_MPAMF_AIDR_S_ArchMinorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_AIDR_S_ArchMinorRev_SHIFT)) & MMU_TCU_MPAMF_AIDR_S_ArchMinorRev_MASK) #define MMU_TCU_MPAMF_AIDR_S_ArchMajorRev_MASK (0xF0U) #define MMU_TCU_MPAMF_AIDR_S_ArchMajorRev_SHIFT (4U) /*! ArchMajorRev - ArchMajorRev */ #define MMU_TCU_MPAMF_AIDR_S_ArchMajorRev(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_AIDR_S_ArchMajorRev_SHIFT)) & MMU_TCU_MPAMF_AIDR_S_ArchMajorRev_MASK) /*! @} */ /*! @name MPAMF_CCAP_IDR_S - MPAMF_CCAP_IDR_s */ /*! @{ */ #define MMU_TCU_MPAMF_CCAP_IDR_S_CMAX_WD_MASK (0x3FU) #define MMU_TCU_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT (0U) /*! CMAX_WD - CMAX_WD */ #define MMU_TCU_MPAMF_CCAP_IDR_S_CMAX_WD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_CCAP_IDR_S_CMAX_WD_SHIFT)) & MMU_TCU_MPAMF_CCAP_IDR_S_CMAX_WD_MASK) /*! @} */ /*! @name MPAMF_MSMON_IDR_S - MPAMF_MSMON_IDR_s */ /*! @{ */ #define MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK (0x10000U) #define MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT (16U) /*! MSMON_CSU - MSMON_CSU */ #define MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_CSU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_CSU_SHIFT)) & MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_CSU_MASK) #define MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK (0x20000U) #define MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT (17U) /*! MSMON_MBWU - MSMON_MBWU */ #define MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_MBWU(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_MBWU_SHIFT)) & MMU_TCU_MPAMF_MSMON_IDR_S_MSMON_MBWU_MASK) #define MMU_TCU_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK (0x80000000U) #define MMU_TCU_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT (31U) /*! HAS_LOCAL_CAPT_EVNT - HAS_LOCAL_CAPT_EVNT */ #define MMU_TCU_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_SHIFT)) & MMU_TCU_MPAMF_MSMON_IDR_S_HAS_LOCAL_CAPT_EVNT_MASK) /*! @} */ /*! @name MPAMF_CSUMON_IDR_S - MPAMF_CSUMON_IDR_s */ /*! @{ */ #define MMU_TCU_MPAMF_CSUMON_IDR_S_NUM_MON_MASK (0xFFFFU) #define MMU_TCU_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT (0U) /*! NUM_MON - NUM_MON */ #define MMU_TCU_MPAMF_CSUMON_IDR_S_NUM_MON(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_CSUMON_IDR_S_NUM_MON_SHIFT)) & MMU_TCU_MPAMF_CSUMON_IDR_S_NUM_MON_MASK) #define MMU_TCU_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK (0x80000000U) #define MMU_TCU_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT (31U) /*! HAS_CAPTURE - HAS_CAPTURE */ #define MMU_TCU_MPAMF_CSUMON_IDR_S_HAS_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_SHIFT)) & MMU_TCU_MPAMF_CSUMON_IDR_S_HAS_CAPTURE_MASK) /*! @} */ /*! @name MPAMCFG_PART_SEL_S - MPAMCFG_PART_SEL_s */ /*! @{ */ #define MMU_TCU_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK (0xFFFFU) #define MMU_TCU_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT (0U) /*! PARTID_SEL - PARTID_SEL */ #define MMU_TCU_MPAMCFG_PART_SEL_S_PARTID_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_PART_SEL_S_PARTID_SEL_SHIFT)) & MMU_TCU_MPAMCFG_PART_SEL_S_PARTID_SEL_MASK) #define MMU_TCU_MPAMCFG_PART_SEL_S_INTERNAL_MASK (0x10000U) #define MMU_TCU_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT (16U) /*! INTERNAL - INTERNAL */ #define MMU_TCU_MPAMCFG_PART_SEL_S_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_PART_SEL_S_INTERNAL_SHIFT)) & MMU_TCU_MPAMCFG_PART_SEL_S_INTERNAL_MASK) #define MMU_TCU_MPAMCFG_PART_SEL_S_RIS_MASK (0xF000000U) #define MMU_TCU_MPAMCFG_PART_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TCU_MPAMCFG_PART_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_PART_SEL_S_RIS_SHIFT)) & MMU_TCU_MPAMCFG_PART_SEL_S_RIS_MASK) /*! @} */ /*! @name MPAMCFG_CMAX_S - MPAMCFG_CMAX_s */ /*! @{ */ #define MMU_TCU_MPAMCFG_CMAX_S_CMAX_MASK (0xFFFFU) #define MMU_TCU_MPAMCFG_CMAX_S_CMAX_SHIFT (0U) /*! CMAX - CMAX */ #define MMU_TCU_MPAMCFG_CMAX_S_CMAX(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MPAMCFG_CMAX_S_CMAX_SHIFT)) & MMU_TCU_MPAMCFG_CMAX_S_CMAX_MASK) /*! @} */ /*! @name MSMON_CFG_MON_SEL_S - MSMON_CFG_MON_SEL_s */ /*! @{ */ #define MMU_TCU_MSMON_CFG_MON_SEL_S_MON_SEL_MASK (0xFFFFU) #define MMU_TCU_MSMON_CFG_MON_SEL_S_MON_SEL_SHIFT (0U) /*! MON_SEL - MON_SEL */ #define MMU_TCU_MSMON_CFG_MON_SEL_S_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_MON_SEL_S_MON_SEL_SHIFT)) & MMU_TCU_MSMON_CFG_MON_SEL_S_MON_SEL_MASK) #define MMU_TCU_MSMON_CFG_MON_SEL_S_RIS_MASK (0xF000000U) #define MMU_TCU_MSMON_CFG_MON_SEL_S_RIS_SHIFT (24U) /*! RIS - RIS */ #define MMU_TCU_MSMON_CFG_MON_SEL_S_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_MON_SEL_S_RIS_SHIFT)) & MMU_TCU_MSMON_CFG_MON_SEL_S_RIS_MASK) /*! @} */ /*! @name MSMON_CAPT_EVNT_S - MSMON_CAPT_EVNT_s */ /*! @{ */ #define MMU_TCU_MSMON_CAPT_EVNT_S_NOW_MASK (0x1U) #define MMU_TCU_MSMON_CAPT_EVNT_S_NOW_SHIFT (0U) /*! NOW - NOW */ #define MMU_TCU_MSMON_CAPT_EVNT_S_NOW(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CAPT_EVNT_S_NOW_SHIFT)) & MMU_TCU_MSMON_CAPT_EVNT_S_NOW_MASK) #define MMU_TCU_MSMON_CAPT_EVNT_S_ALL_MASK (0x2U) #define MMU_TCU_MSMON_CAPT_EVNT_S_ALL_SHIFT (1U) /*! ALL - ALL */ #define MMU_TCU_MSMON_CAPT_EVNT_S_ALL(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CAPT_EVNT_S_ALL_SHIFT)) & MMU_TCU_MSMON_CAPT_EVNT_S_ALL_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_FLT_S - MSMON_CFG_CSU_FLT_s */ /*! @{ */ #define MMU_TCU_MSMON_CFG_CSU_FLT_S_PARTID_MASK (0xFFFFU) #define MMU_TCU_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define MMU_TCU_MSMON_CFG_CSU_FLT_S_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_FLT_S_PARTID_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_FLT_S_PARTID_MASK) #define MMU_TCU_MSMON_CFG_CSU_FLT_S_PMG_MASK (0xFF0000U) #define MMU_TCU_MSMON_CFG_CSU_FLT_S_PMG_SHIFT (16U) /*! PMG - PMG */ #define MMU_TCU_MSMON_CFG_CSU_FLT_S_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_FLT_S_PMG_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_FLT_S_PMG_MASK) /*! @} */ /*! @name MSMON_CFG_CSU_CTL_S - MSMON_CFG_CSU_CTL_s */ /*! @{ */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_TYPE_MASK (0xFFU) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_TYPE_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_TYPE_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK (0x10000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT (16U) /*! MATCH_PARTID - MATCH_PARTID */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PARTID(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PARTID_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK (0x20000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT (17U) /*! MATCH_PMG - MATCH_PMG */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PMG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PMG_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_MATCH_PMG_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK (0xF00000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT (20U) /*! SUBTYPE - SUBTYPE */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_SUBTYPE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_SUBTYPE_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_SUBTYPE_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK (0x1000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT (24U) /*! OFLOW_FRZ - OFLOW_FRZ */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_FRZ_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK (0x2000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT (25U) /*! OFLOW_INTR - OFLOW_INTR */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_INTR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_INTR_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK (0x4000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT (26U) /*! OFLOW_STATUS - OFLOW_STATUS */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_OFLOW_STATUS_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK (0x8000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT (27U) /*! CAPT_RESET - CAPT_RESET */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_RESET(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_RESET_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_RESET_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK (0x70000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT (28U) /*! CAPT_EVNT - CAPT_EVNT */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_EVNT(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_CAPT_EVNT_MASK) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_EN_MASK (0x80000000U) #define MMU_TCU_MSMON_CFG_CSU_CTL_S_EN_SHIFT (31U) /*! EN - EN */ #define MMU_TCU_MSMON_CFG_CSU_CTL_S_EN(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CFG_CSU_CTL_S_EN_SHIFT)) & MMU_TCU_MSMON_CFG_CSU_CTL_S_EN_MASK) /*! @} */ /*! @name MSMON_CSU_S - MSMON_CSU_s */ /*! @{ */ #define MMU_TCU_MSMON_CSU_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TCU_MSMON_CSU_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TCU_MSMON_CSU_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_S_VALUE_SHIFT)) & MMU_TCU_MSMON_CSU_S_VALUE_MASK) #define MMU_TCU_MSMON_CSU_S_NRDY_MASK (0x80000000U) #define MMU_TCU_MSMON_CSU_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TCU_MSMON_CSU_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_S_NRDY_SHIFT)) & MMU_TCU_MSMON_CSU_S_NRDY_MASK) /*! @} */ /*! @name MSMON_CSU_CAPTURE_S - MSMON_CSU_CAPTURE_s */ /*! @{ */ #define MMU_TCU_MSMON_CSU_CAPTURE_S_VALUE_MASK (0x7FFFFFFFU) #define MMU_TCU_MSMON_CSU_CAPTURE_S_VALUE_SHIFT (0U) /*! VALUE - VALUE */ #define MMU_TCU_MSMON_CSU_CAPTURE_S_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_CAPTURE_S_VALUE_SHIFT)) & MMU_TCU_MSMON_CSU_CAPTURE_S_VALUE_MASK) #define MMU_TCU_MSMON_CSU_CAPTURE_S_NRDY_MASK (0x80000000U) #define MMU_TCU_MSMON_CSU_CAPTURE_S_NRDY_SHIFT (31U) /*! NRDY - NRDY */ #define MMU_TCU_MSMON_CSU_CAPTURE_S_NRDY(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_MSMON_CSU_CAPTURE_S_NRDY_SHIFT)) & MMU_TCU_MSMON_CSU_CAPTURE_S_NRDY_MASK) /*! @} */ /*! @name SMMU_EVENTQ_PROD - SMMU_EVENTQ_PROD */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_PROD_WR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_EVENTQ_PROD_WR_SHIFT (0U) /*! WR - WR */ #define MMU_TCU_SMMU_EVENTQ_PROD_WR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_PROD_WR_SHIFT)) & MMU_TCU_SMMU_EVENTQ_PROD_WR_MASK) #define MMU_TCU_SMMU_EVENTQ_PROD_OVFLG_MASK (0x80000000U) #define MMU_TCU_SMMU_EVENTQ_PROD_OVFLG_SHIFT (31U) /*! OVFLG - OVFLG */ #define MMU_TCU_SMMU_EVENTQ_PROD_OVFLG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_PROD_OVFLG_SHIFT)) & MMU_TCU_SMMU_EVENTQ_PROD_OVFLG_MASK) /*! @} */ /*! @name SMMU_EVENTQ_CONS - SMMU_EVENTQ_CONS */ /*! @{ */ #define MMU_TCU_SMMU_EVENTQ_CONS_RD_MASK (0xFFFFFU) #define MMU_TCU_SMMU_EVENTQ_CONS_RD_SHIFT (0U) /*! RD - RD */ #define MMU_TCU_SMMU_EVENTQ_CONS_RD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_CONS_RD_SHIFT)) & MMU_TCU_SMMU_EVENTQ_CONS_RD_MASK) #define MMU_TCU_SMMU_EVENTQ_CONS_OVACKFLG_MASK (0x80000000U) #define MMU_TCU_SMMU_EVENTQ_CONS_OVACKFLG_SHIFT (31U) /*! OVACKFLG - OVACKFLG */ #define MMU_TCU_SMMU_EVENTQ_CONS_OVACKFLG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_EVENTQ_CONS_OVACKFLG_SHIFT)) & MMU_TCU_SMMU_EVENTQ_CONS_OVACKFLG_MASK) /*! @} */ /*! @name SMMU_PRIQ_PROD - SMMU_PRIQ_PROD */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_PROD_WR_MASK (0xFFFFFU) #define MMU_TCU_SMMU_PRIQ_PROD_WR_SHIFT (0U) /*! WR - WR */ #define MMU_TCU_SMMU_PRIQ_PROD_WR(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_PROD_WR_SHIFT)) & MMU_TCU_SMMU_PRIQ_PROD_WR_MASK) #define MMU_TCU_SMMU_PRIQ_PROD_OVFLG_MASK (0x80000000U) #define MMU_TCU_SMMU_PRIQ_PROD_OVFLG_SHIFT (31U) /*! OVFLG - OVFLG */ #define MMU_TCU_SMMU_PRIQ_PROD_OVFLG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_PROD_OVFLG_SHIFT)) & MMU_TCU_SMMU_PRIQ_PROD_OVFLG_MASK) /*! @} */ /*! @name SMMU_PRIQ_CONS - SMMU_PRIQ_CONS */ /*! @{ */ #define MMU_TCU_SMMU_PRIQ_CONS_RD_MASK (0xFFFFFU) #define MMU_TCU_SMMU_PRIQ_CONS_RD_SHIFT (0U) /*! RD - RD */ #define MMU_TCU_SMMU_PRIQ_CONS_RD(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_CONS_RD_SHIFT)) & MMU_TCU_SMMU_PRIQ_CONS_RD_MASK) #define MMU_TCU_SMMU_PRIQ_CONS_OVACKFLG_MASK (0x80000000U) #define MMU_TCU_SMMU_PRIQ_CONS_OVACKFLG_SHIFT (31U) /*! OVACKFLG - OVACKFLG */ #define MMU_TCU_SMMU_PRIQ_CONS_OVACKFLG(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PRIQ_CONS_OVACKFLG_SHIFT)) & MMU_TCU_SMMU_PRIQ_CONS_OVACKFLG_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR0 - SMMU_PMCG_EVCNTR0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR0_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR0_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR1 - SMMU_PMCG_EVCNTR1 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR1_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR1_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR2 - SMMU_PMCG_EVCNTR2 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR2_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR2_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR3 - SMMU_PMCG_EVCNTR3 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR3_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR3_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR4 - SMMU_PMCG_EVCNTR4 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR4_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR4_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR5 - SMMU_PMCG_EVCNTR5 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR5_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR5_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR6 - SMMU_PMCG_EVCNTR6 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR6_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR6_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR7 - SMMU_PMCG_EVCNTR7 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR7_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR7_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR8 - SMMU_PMCG_EVCNTR8 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR8_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR8_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR9 - SMMU_PMCG_EVCNTR9 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR9_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR9_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR10 - SMMU_PMCG_EVCNTR10 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR10_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR10_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR11 - SMMU_PMCG_EVCNTR11 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR11_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR11_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR12 - SMMU_PMCG_EVCNTR12 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR12_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR12_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR13 - SMMU_PMCG_EVCNTR13 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR13_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR13_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR14 - SMMU_PMCG_EVCNTR14 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR14_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR14_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_EVCNTR15 - SMMU_PMCG_EVCNTR15 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT (0U) /*! COUNTER_VALUE - COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_EVCNTR15_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_EVCNTR15_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR0 - SMMU_PMCG_SVR0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR0_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR1 - SMMU_PMCG_SVR1 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR1_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR2 - SMMU_PMCG_SVR2 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR2_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR3 - SMMU_PMCG_SVR3 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR3_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR4 - SMMU_PMCG_SVR4 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR4_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR5 - SMMU_PMCG_SVR5 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR5_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR6 - SMMU_PMCG_SVR6 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR6_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR7 - SMMU_PMCG_SVR7 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR7_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR8 - SMMU_PMCG_SVR8 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR8_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR9 - SMMU_PMCG_SVR9 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR9_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR10 - SMMU_PMCG_SVR10 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR10_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR11 - SMMU_PMCG_SVR11 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR11_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR12 - SMMU_PMCG_SVR12 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR12_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR13 - SMMU_PMCG_SVR13 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR13_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR14 - SMMU_PMCG_SVR14 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR14_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_SVR15 - SMMU_PMCG_SVR15 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT (0U) /*! SHADOW_COUNTER_VALUE - SHADOW_COUNTER_VALUE */ #define MMU_TCU_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_SHIFT)) & MMU_TCU_SMMU_PMCG_SVR15_SHADOW_COUNTER_VALUE_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSCLR0 - SMMU_PMCG_OVSCLR0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_OVSCLR0_OVS_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TCU_SMMU_PMCG_OVSCLR0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_OVSCLR0_OVS_SHIFT)) & MMU_TCU_SMMU_PMCG_OVSCLR0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_OVSSET0 - SMMU_PMCG_OVSSET0 */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_OVSSET0_OVS_MASK (0xFFFFFFFFU) #define MMU_TCU_SMMU_PMCG_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define MMU_TCU_SMMU_PMCG_OVSSET0_OVS(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_OVSSET0_OVS_SHIFT)) & MMU_TCU_SMMU_PMCG_OVSSET0_OVS_MASK) /*! @} */ /*! @name SMMU_PMCG_CAPR - SMMU_PMCG_CAPR */ /*! @{ */ #define MMU_TCU_SMMU_PMCG_CAPR_CAPTURE_MASK (0x1U) #define MMU_TCU_SMMU_PMCG_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define MMU_TCU_SMMU_PMCG_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << MMU_TCU_SMMU_PMCG_CAPR_CAPTURE_SHIFT)) & MMU_TCU_SMMU_PMCG_CAPR_CAPTURE_MASK) /*! @} */ /*! * @} */ /* end of group MMU_TCU_Register_Masks */ /* MMU_TCU - Peripheral instance base addresses */ /** Peripheral NOC__MMU_TBU_TCU__TCU base address */ #define NOC__MMU_TBU_TCU__TCU_BASE (0x490D0000u) /** Peripheral NOC__MMU_TBU_TCU__TCU base pointer */ #define NOC__MMU_TBU_TCU__TCU ((MMU_TCU_Type *)NOC__MMU_TBU_TCU__TCU_BASE) /** Array initializer of MMU_TCU peripheral base addresses */ #define MMU_TCU_BASE_ADDRS { NOC__MMU_TBU_TCU__TCU_BASE } /** Array initializer of MMU_TCU peripheral base pointers */ #define MMU_TCU_BASE_PTRS { NOC__MMU_TBU_TCU__TCU } /*! * @} */ /* end of group MMU_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MSGINTR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MSGINTR_Peripheral_Access_Layer MSGINTR Peripheral Access Layer * @{ */ /** MSGINTR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x8 */ __O uint32_t MSIIR; /**< Message Signaled Interrupt Index Register 0..Message Signaled Interrupt Index Register 2, array offset: 0x0, array step: 0x8 */ __I uint32_t MSIR; /**< Message Signaled Interrupt Register 0..Message Signaled Interrupt Register 2, array offset: 0x4, array step: 0x8 */ } MSI[3]; } MSGINTR_Type; /* ---------------------------------------------------------------------------- -- MSGINTR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MSGINTR_Register_Masks MSGINTR Register Masks * @{ */ /*! @name MSIIR - Message Signaled Interrupt Index Register 0..Message Signaled Interrupt Index Register 2 */ /*! @{ */ #define MSGINTR_MSIIR_IBS_MASK (0x1FU) #define MSGINTR_MSIIR_IBS_SHIFT (0U) #define MSGINTR_MSIIR_IBS(x) (((uint32_t)(((uint32_t)(x)) << MSGINTR_MSIIR_IBS_SHIFT)) & MSGINTR_MSIIR_IBS_MASK) /*! @} */ /* The count of MSGINTR_MSIIR */ #define MSGINTR_MSIIR_COUNT (3U) /*! @name MSIR - Message Signaled Interrupt Register 0..Message Signaled Interrupt Register 2 */ /*! @{ */ #define MSGINTR_MSIR_SHn_MASK (0xFFFFFFFFU) #define MSGINTR_MSIR_SHn_SHIFT (0U) #define MSGINTR_MSIR_SHn(x) (((uint32_t)(((uint32_t)(x)) << MSGINTR_MSIR_SHn_SHIFT)) & MSGINTR_MSIR_SHn_MASK) /*! @} */ /* The count of MSGINTR_MSIR */ #define MSGINTR_MSIR_COUNT (3U) /*! * @} */ /* end of group MSGINTR_Register_Masks */ /* MSGINTR - Peripheral instance base addresses */ /** Peripheral MSGINTR1 base address */ #define MSGINTR1_BASE (0x44690000u) /** Peripheral MSGINTR1 base pointer */ #define MSGINTR1 ((MSGINTR_Type *)MSGINTR1_BASE) /** Peripheral MSGINTR2 base address */ #define MSGINTR2_BASE (0x446A0000u) /** Peripheral MSGINTR2 base pointer */ #define MSGINTR2 ((MSGINTR_Type *)MSGINTR2_BASE) /** Array initializer of MSGINTR peripheral base addresses */ #define MSGINTR_BASE_ADDRS { 0u, MSGINTR1_BASE, MSGINTR2_BASE } /** Array initializer of MSGINTR peripheral base pointers */ #define MSGINTR_BASE_PTRS { (MSGINTR_Type *)0u, MSGINTR1, MSGINTR2 } /** Interrupt vectors for the MSGINTR peripheral type */ #define MSGINTR_IRQS { NotAvail_IRQn, MSGINTR1_IRQn, MSGINTR2_IRQn } /*! * @} */ /* end of group MSGINTR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer * @{ */ /** MU - Register Layout Typedef */ typedef struct { __I uint32_t VER; /**< Version ID, offset: 0x0 */ __I uint32_t PAR; /**< Parameter, offset: 0x4 */ __IO uint32_t CR; /**< Control, offset: 0x8 */ __IO uint32_t SR; /**< Status, offset: 0xC */ __IO uint32_t CCR0; /**< Core Control 0, offset: 0x10, not available in all instances (available on 54 out of 150) */ uint32_t CIER0; /**< Core Interrupt Enable 0, offset: 0x14, not available in all instances (available on 54 out of 150) */ __IO uint32_t CSSR0; /**< Core Sticky Status 0, offset: 0x18, not available in all instances (available on 54 out of 150) */ uint8_t RESERVED_0[228]; __IO uint32_t FCR; /**< Flag Control, offset: 0x100 */ __I uint32_t FSR; /**< Flag Status, offset: 0x104 */ uint8_t RESERVED_1[8]; __IO uint32_t GIER; /**< General-Purpose Interrupt Enable, offset: 0x110 */ __IO uint32_t GCR; /**< General-Purpose Control, offset: 0x114 */ __IO uint32_t GSR; /**< General-purpose Status, offset: 0x118 */ uint8_t RESERVED_2[4]; __IO uint32_t TCR; /**< Transmit Control, offset: 0x120 */ __I uint32_t TSR; /**< Transmit Status, offset: 0x124 */ __IO uint32_t RCR; /**< Receive Control, offset: 0x128 */ __I uint32_t RSR; /**< Receive Status, offset: 0x12C */ uint8_t RESERVED_3[208]; __O uint32_t TR[4]; /**< Transmit, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_4[112]; __I uint32_t RR[4]; /**< Receive, array offset: 0x280, array step: 0x4 */ } MU_Type; /* ---------------------------------------------------------------------------- -- MU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MU_Register_Masks MU Register Masks * @{ */ /*! @name VER - Version ID */ /*! @{ */ #define MU_VER_FEATURE_MASK (0xFFFFU) #define MU_VER_FEATURE_SHIFT (0U) /*! FEATURE - Feature Set Number */ #define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) #define MU_VER_MINOR_MASK (0xFF0000U) #define MU_VER_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) #define MU_VER_MAJOR_MASK (0xFF000000U) #define MU_VER_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) /*! @} */ /*! @name PAR - Parameter */ /*! @{ */ #define MU_PAR_TR_NUM_MASK (0xFFU) #define MU_PAR_TR_NUM_SHIFT (0U) /*! TR_NUM - Transmit Register Number */ #define MU_PAR_TR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK) #define MU_PAR_RR_NUM_MASK (0xFF00U) #define MU_PAR_RR_NUM_SHIFT (8U) /*! RR_NUM - Receive Register Number */ #define MU_PAR_RR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK) #define MU_PAR_GIR_NUM_MASK (0xFF0000U) #define MU_PAR_GIR_NUM_SHIFT (16U) /*! GIR_NUM - General-Purpose Interrupt Request Number */ #define MU_PAR_GIR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK) #define MU_PAR_FLAG_WIDTH_MASK (0xFF000000U) #define MU_PAR_FLAG_WIDTH_SHIFT (24U) /*! FLAG_WIDTH - Flag Width */ #define MU_PAR_FLAG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK) /*! @} */ /*! @name CR - Control */ /*! @{ */ #define MU_CR_MUR_MASK (0x1U) #define MU_CR_MUR_SHIFT (0U) /*! MUR - MU Reset * 0b0..Idle * 0b1..Reset */ #define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) #define MU_CR_MURIE_MASK (0x2U) #define MU_CR_MURIE_SHIFT (1U) /*! MURIE - MUB Reset Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_CR_MURIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK) /*! @} */ /*! @name SR - Status */ /*! @{ */ #define MU_SR_MURS_MASK (0x1U) #define MU_SR_MURS_SHIFT (0U) /*! MURS - MUA and MUB Reset State * 0b0..Out of reset * 0b1..In reset */ #define MU_SR_MURS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK) #define MU_SR_MURIP_MASK (0x2U) #define MU_SR_MURIP_SHIFT (1U) /*! MURIP - MU Reset Interrupt Pending Flag * 0b0..Reset not issued * 0b1..Reset issued * 0b0..No effect * 0b1..Clear the flag */ #define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) #define MU_SR_EP_MASK (0x4U) #define MU_SR_EP_SHIFT (2U) /*! EP - MUB Side Event Pending * 0b0..Not pending * 0b1..Pending */ #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) #define MU_SR_FUP_MASK (0x8U) #define MU_SR_FUP_SHIFT (3U) /*! FUP - MUB Flag Update Pending * 0b0..No pending update flags (initiated by MUA) * 0b1..Pending update flags (initiated by MUA) */ #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) #define MU_SR_GIRP_MASK (0x10U) #define MU_SR_GIRP_SHIFT (4U) /*! GIRP - MUB General-Purpose Interrupt Pending * 0b0..No request sent * 0b1..Request sent */ #define MU_SR_GIRP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK) #define MU_SR_TEP_MASK (0x20U) #define MU_SR_TEP_SHIFT (5U) /*! TEP - MUB Transmit Empty Pending * 0b0..Not pending; MUA is reading no Receive (RRn) register * 0b1..Pending; MUA is reading a Receive (RRn) register */ #define MU_SR_TEP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK) #define MU_SR_RFP_MASK (0x40U) #define MU_SR_RFP_SHIFT (6U) /*! RFP - MUB Receive Full Pending * 0b0..Not pending; MUA is not writing to a Transmit register * 0b1..Pending; MUA is writing to a Transmit register */ #define MU_SR_RFP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK) /*! @} */ /*! @name CCR0 - Core Control 0 */ /*! @{ */ #define MU_CCR0_NMI_MASK (0x1U) #define MU_CCR0_NMI_SHIFT (0U) /*! NMI - MUB Nonmaskable Interrupt Request * 0b0..Nonmaskable interrupt not issued * 0b1..Nonmaskable interrupt issued */ #define MU_CCR0_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR0_NMI_SHIFT)) & MU_CCR0_NMI_MASK) /*! @} */ /*! @name CSSR0 - Core Sticky Status 0 */ /*! @{ */ #define MU_CSSR0_NMIC_MASK (0x1U) #define MU_CSSR0_NMIC_SHIFT (0U) /*! NMIC - Processor A Nonmaskable Interrupt Clear * 0b0..Default * 0b1..Clear MUB_CCR0[NMI] */ #define MU_CSSR0_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_NMIC_SHIFT)) & MU_CSSR0_NMIC_MASK) /*! @} */ /*! @name FCR - Flag Control */ /*! @{ */ #define MU_FCR_F0_MASK (0x1U) #define MU_FCR_F0_SHIFT (0U) /*! F0 - MUB to MUA Flag * 0b0..Clear MUA_FSR[Fn] * 0b1..Set MUA_FSR[Fn] */ #define MU_FCR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK) #define MU_FCR_F1_MASK (0x2U) #define MU_FCR_F1_SHIFT (1U) /*! F1 - MUB to MUA Flag * 0b0..Clear MUA_FSR[Fn] * 0b1..Set MUA_FSR[Fn] */ #define MU_FCR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK) #define MU_FCR_F2_MASK (0x4U) #define MU_FCR_F2_SHIFT (2U) /*! F2 - MUB to MUA Flag * 0b0..Clear MUA_FSR[Fn] * 0b1..Set MUA_FSR[Fn] */ #define MU_FCR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK) /*! @} */ /*! @name FSR - Flag Status */ /*! @{ */ #define MU_FSR_F0_MASK (0x1U) #define MU_FSR_F0_SHIFT (0U) /*! F0 - MUB to MUA-Side Flag * 0b0..MUA_FCR[Fn] = 0 * 0b1..MUA_FCR[Fn] = 1 */ #define MU_FSR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK) #define MU_FSR_F1_MASK (0x2U) #define MU_FSR_F1_SHIFT (1U) /*! F1 - MUB to MUA-Side Flag * 0b0..MUA_FCR[Fn] = 0 * 0b1..MUA_FCR[Fn] = 1 */ #define MU_FSR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK) #define MU_FSR_F2_MASK (0x4U) #define MU_FSR_F2_SHIFT (2U) /*! F2 - MUB to MUA-Side Flag * 0b0..MUA_FCR[Fn] = 0 * 0b1..MUA_FCR[Fn] = 1 */ #define MU_FSR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK) /*! @} */ /*! @name GIER - General-Purpose Interrupt Enable */ /*! @{ */ #define MU_GIER_GIE0_MASK (0x1U) #define MU_GIER_GIE0_SHIFT (0U) /*! GIE0 - MUB General-purpose Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_GIER_GIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK) #define MU_GIER_GIE1_MASK (0x2U) #define MU_GIER_GIE1_SHIFT (1U) /*! GIE1 - MUB General-purpose Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_GIER_GIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK) #define MU_GIER_GIE2_MASK (0x4U) #define MU_GIER_GIE2_SHIFT (2U) /*! GIE2 - MUB General-purpose Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_GIER_GIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK) #define MU_GIER_GIE3_MASK (0x8U) #define MU_GIER_GIE3_SHIFT (3U) /*! GIE3 - MUB General-purpose Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_GIER_GIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK) /*! @} */ /*! @name GCR - General-Purpose Control */ /*! @{ */ #define MU_GCR_GIR0_MASK (0x1U) #define MU_GCR_GIR0_SHIFT (0U) /*! GIR0 - MUB General-Purpose Interrupt Request * 0b0..Not requested * 0b1..Requested */ #define MU_GCR_GIR0(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK) #define MU_GCR_GIR1_MASK (0x2U) #define MU_GCR_GIR1_SHIFT (1U) /*! GIR1 - MUB General-Purpose Interrupt Request * 0b0..Not requested * 0b1..Requested */ #define MU_GCR_GIR1(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK) #define MU_GCR_GIR2_MASK (0x4U) #define MU_GCR_GIR2_SHIFT (2U) /*! GIR2 - MUB General-Purpose Interrupt Request * 0b0..Not requested * 0b1..Requested */ #define MU_GCR_GIR2(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK) #define MU_GCR_GIR3_MASK (0x8U) #define MU_GCR_GIR3_SHIFT (3U) /*! GIR3 - MUB General-Purpose Interrupt Request * 0b0..Not requested * 0b1..Requested */ #define MU_GCR_GIR3(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK) /*! @} */ /*! @name GSR - General-purpose Status */ /*! @{ */ #define MU_GSR_GIP0_MASK (0x1U) #define MU_GSR_GIP0_SHIFT (0U) /*! GIP0 - MUB General-Purpose Interrupt Request Pending * 0b0..Not pending * 0b1..Pending * 0b0..No effect * 0b1..Clear the flag */ #define MU_GSR_GIP0(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK) #define MU_GSR_GIP1_MASK (0x2U) #define MU_GSR_GIP1_SHIFT (1U) /*! GIP1 - MUB General-Purpose Interrupt Request Pending * 0b0..Not pending * 0b1..Pending * 0b0..No effect * 0b1..Clear the flag */ #define MU_GSR_GIP1(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK) #define MU_GSR_GIP2_MASK (0x4U) #define MU_GSR_GIP2_SHIFT (2U) /*! GIP2 - MUB General-Purpose Interrupt Request Pending * 0b0..Not pending * 0b1..Pending * 0b0..No effect * 0b1..Clear the flag */ #define MU_GSR_GIP2(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK) #define MU_GSR_GIP3_MASK (0x8U) #define MU_GSR_GIP3_SHIFT (3U) /*! GIP3 - MUB General-Purpose Interrupt Request Pending * 0b0..Not pending * 0b1..Pending * 0b0..No effect * 0b1..Clear the flag */ #define MU_GSR_GIP3(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK) /*! @} */ /*! @name TCR - Transmit Control */ /*! @{ */ #define MU_TCR_TIE0_MASK (0x1U) #define MU_TCR_TIE0_SHIFT (0U) /*! TIE0 - MUB Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_TCR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK) #define MU_TCR_TIE1_MASK (0x2U) #define MU_TCR_TIE1_SHIFT (1U) /*! TIE1 - MUB Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_TCR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK) #define MU_TCR_TIE2_MASK (0x4U) #define MU_TCR_TIE2_SHIFT (2U) /*! TIE2 - MUB Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_TCR_TIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK) #define MU_TCR_TIE3_MASK (0x8U) #define MU_TCR_TIE3_SHIFT (3U) /*! TIE3 - MUB Transmit Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_TCR_TIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK) /*! @} */ /*! @name TSR - Transmit Status */ /*! @{ */ #define MU_TSR_TE0_MASK (0x1U) #define MU_TSR_TE0_SHIFT (0U) /*! TE0 - MUB Transmit Empty * 0b0..Not empty * 0b1..Empty */ #define MU_TSR_TE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK) #define MU_TSR_TE1_MASK (0x2U) #define MU_TSR_TE1_SHIFT (1U) /*! TE1 - MUB Transmit Empty * 0b0..Not empty * 0b1..Empty */ #define MU_TSR_TE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK) #define MU_TSR_TE2_MASK (0x4U) #define MU_TSR_TE2_SHIFT (2U) /*! TE2 - MUB Transmit Empty * 0b0..Not empty * 0b1..Empty */ #define MU_TSR_TE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK) #define MU_TSR_TE3_MASK (0x8U) #define MU_TSR_TE3_SHIFT (3U) /*! TE3 - MUB Transmit Empty * 0b0..Not empty * 0b1..Empty */ #define MU_TSR_TE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK) /*! @} */ /*! @name RCR - Receive Control */ /*! @{ */ #define MU_RCR_RIE0_MASK (0x1U) #define MU_RCR_RIE0_SHIFT (0U) /*! RIE0 - MUB Receive Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_RCR_RIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK) #define MU_RCR_RIE1_MASK (0x2U) #define MU_RCR_RIE1_SHIFT (1U) /*! RIE1 - MUB Receive Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_RCR_RIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK) #define MU_RCR_RIE2_MASK (0x4U) #define MU_RCR_RIE2_SHIFT (2U) /*! RIE2 - MUB Receive Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_RCR_RIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK) #define MU_RCR_RIE3_MASK (0x8U) #define MU_RCR_RIE3_SHIFT (3U) /*! RIE3 - MUB Receive Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define MU_RCR_RIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK) /*! @} */ /*! @name RSR - Receive Status */ /*! @{ */ #define MU_RSR_RF0_MASK (0x1U) #define MU_RSR_RF0_SHIFT (0U) /*! RF0 - MUB Receive Register Full * 0b0..Not full * 0b1..Full */ #define MU_RSR_RF0(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK) #define MU_RSR_RF1_MASK (0x2U) #define MU_RSR_RF1_SHIFT (1U) /*! RF1 - MUB Receive Register Full * 0b0..Not full * 0b1..Full */ #define MU_RSR_RF1(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK) #define MU_RSR_RF2_MASK (0x4U) #define MU_RSR_RF2_SHIFT (2U) /*! RF2 - MUB Receive Register Full * 0b0..Not full * 0b1..Full */ #define MU_RSR_RF2(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK) #define MU_RSR_RF3_MASK (0x8U) #define MU_RSR_RF3_SHIFT (3U) /*! RF3 - MUB Receive Register Full * 0b0..Not full * 0b1..Full */ #define MU_RSR_RF3(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK) /*! @} */ /*! @name TR - Transmit */ /*! @{ */ #define MU_TR_TR_DATA_MASK (0xFFFFFFFFU) #define MU_TR_TR_DATA_SHIFT (0U) /*! TR_DATA - MUB Transmit Data */ #define MU_TR_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK) /*! @} */ /* The count of MU_TR */ #define MU_TR_COUNT (4U) /*! @name RR - Receive */ /*! @{ */ #define MU_RR_RR_DATA_MASK (0xFFFFFFFFU) #define MU_RR_RR_DATA_SHIFT (0U) /*! RR_DATA - MUB Receive Data */ #define MU_RR_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK) /*! @} */ /* The count of MU_RR */ #define MU_RR_COUNT (4U) /*! * @} */ /* end of group MU_Register_Masks */ /* MU - Peripheral instance base addresses */ /** Peripheral MU5_MUA base address */ #define MU5_MUA_BASE (0x44610000u) /** Peripheral MU5_MUA base pointer */ #define MU5_MUA ((MU_Type *)MU5_MUA_BASE) /** Peripheral MU7_MUB base address */ #define MU7_MUB_BASE (0x42440000u) /** Peripheral MU7_MUB base pointer */ #define MU7_MUB ((MU_Type *)MU7_MUB_BASE) /** Peripheral MU8_MUB base address */ #define MU8_MUB_BASE (0x42740000u) /** Peripheral MU8_MUB base pointer */ #define MU8_MUB ((MU_Type *)MU8_MUB_BASE) /** Peripheral AON__MUI_A1__MUA base address */ #define AON__MUI_A1__MUA_BASE (0x44220000u) /** Peripheral AON__MUI_A1__MUA base pointer */ #define AON__MUI_A1__MUA ((MU_Type *)AON__MUI_A1__MUA_BASE) /** Peripheral AON__MUI_A1__MUB base address */ #define AON__MUI_A1__MUB_BASE (0x44230000u) /** Peripheral AON__MUI_A1__MUB base pointer */ #define AON__MUI_A1__MUB ((MU_Type *)AON__MUI_A1__MUB_BASE) /** Peripheral AON__MUI_A2__MUA base address */ #define AON__MUI_A2__MUA_BASE (0x445B0000u) /** Peripheral AON__MUI_A2__MUA base pointer */ #define AON__MUI_A2__MUA ((MU_Type *)AON__MUI_A2__MUA_BASE) /** Peripheral AON__MUI_A2__MUB base address */ #define AON__MUI_A2__MUB_BASE (0x445C0000u) /** Peripheral AON__MUI_A2__MUB base pointer */ #define AON__MUI_A2__MUB ((MU_Type *)AON__MUI_A2__MUB_BASE) /** Peripheral AON__MUI_A3__MUA base address */ #define AON__MUI_A3__MUA_BASE (0x445D0000u) /** Peripheral AON__MUI_A3__MUA base pointer */ #define AON__MUI_A3__MUA ((MU_Type *)AON__MUI_A3__MUA_BASE) /** Peripheral AON__MUI_A3__MUB base address */ #define AON__MUI_A3__MUB_BASE (0x445E0000u) /** Peripheral AON__MUI_A3__MUB base pointer */ #define AON__MUI_A3__MUB ((MU_Type *)AON__MUI_A3__MUB_BASE) /** Peripheral AON__MUI_A4__MUA base address */ #define AON__MUI_A4__MUA_BASE (0x445F0000u) /** Peripheral AON__MUI_A4__MUA base pointer */ #define AON__MUI_A4__MUA ((MU_Type *)AON__MUI_A4__MUA_BASE) /** Peripheral AON__MUI_A4__MUB base address */ #define AON__MUI_A4__MUB_BASE (0x44600000u) /** Peripheral AON__MUI_A4__MUB base pointer */ #define AON__MUI_A4__MUB ((MU_Type *)AON__MUI_A4__MUB_BASE) /** Peripheral AON__MUI_A5__MUB base address */ #define AON__MUI_A5__MUB_BASE (0x44620000u) /** Peripheral AON__MUI_A5__MUB base pointer */ #define AON__MUI_A5__MUB ((MU_Type *)AON__MUI_A5__MUB_BASE) /** Peripheral AON__MUI_A6__MUA base address */ #define AON__MUI_A6__MUA_BASE (0x44630000u) /** Peripheral AON__MUI_A6__MUA base pointer */ #define AON__MUI_A6__MUA ((MU_Type *)AON__MUI_A6__MUA_BASE) /** Peripheral AON__MUI_A6__MUB base address */ #define AON__MUI_A6__MUB_BASE (0x44640000u) /** Peripheral AON__MUI_A6__MUB base pointer */ #define AON__MUI_A6__MUB ((MU_Type *)AON__MUI_A6__MUB_BASE) /** Peripheral CAMERA__MUI_A1__MUA base address */ #define CAMERA__MUI_A1__MUA_BASE (0x4AC60000u) /** Peripheral CAMERA__MUI_A1__MUA base pointer */ #define CAMERA__MUI_A1__MUA ((MU_Type *)CAMERA__MUI_A1__MUA_BASE) /** Peripheral CAMERA__MUI_A2__MUA base address */ #define CAMERA__MUI_A2__MUA_BASE (0x4AC70000u) /** Peripheral CAMERA__MUI_A2__MUA base pointer */ #define CAMERA__MUI_A2__MUA ((MU_Type *)CAMERA__MUI_A2__MUA_BASE) /** Peripheral CAMERA__MUI_A3__MUA base address */ #define CAMERA__MUI_A3__MUA_BASE (0x4AC80000u) /** Peripheral CAMERA__MUI_A3__MUA base pointer */ #define CAMERA__MUI_A3__MUA ((MU_Type *)CAMERA__MUI_A3__MUA_BASE) /** Peripheral CAMERA__MUI_A4__MUA base address */ #define CAMERA__MUI_A4__MUA_BASE (0x4AC90000u) /** Peripheral CAMERA__MUI_A4__MUA base pointer */ #define CAMERA__MUI_A4__MUA ((MU_Type *)CAMERA__MUI_A4__MUA_BASE) /** Peripheral CAMERA__MUI_A5__MUA base address */ #define CAMERA__MUI_A5__MUA_BASE (0x4ACA0000u) /** Peripheral CAMERA__MUI_A5__MUA base pointer */ #define CAMERA__MUI_A5__MUA ((MU_Type *)CAMERA__MUI_A5__MUA_BASE) /** Peripheral CAMERA__MUI_A6__MUA base address */ #define CAMERA__MUI_A6__MUA_BASE (0x4ACB0000u) /** Peripheral CAMERA__MUI_A6__MUA base pointer */ #define CAMERA__MUI_A6__MUA ((MU_Type *)CAMERA__MUI_A6__MUA_BASE) /** Peripheral CAMERA__MUI_A7__MUA base address */ #define CAMERA__MUI_A7__MUA_BASE (0x4ACC0000u) /** Peripheral CAMERA__MUI_A7__MUA base pointer */ #define CAMERA__MUI_A7__MUA ((MU_Type *)CAMERA__MUI_A7__MUA_BASE) /** Peripheral CAMERA__MUI_A8__MUA base address */ #define CAMERA__MUI_A8__MUA_BASE (0x4ACD0000u) /** Peripheral CAMERA__MUI_A8__MUA base pointer */ #define CAMERA__MUI_A8__MUA ((MU_Type *)CAMERA__MUI_A8__MUA_BASE) /** Peripheral CAMERA__MUI_A9__MUA base address */ #define CAMERA__MUI_A9__MUA_BASE (0x4ACE0000u) /** Peripheral CAMERA__MUI_A9__MUA base pointer */ #define CAMERA__MUI_A9__MUA ((MU_Type *)CAMERA__MUI_A9__MUA_BASE) /** Peripheral WAKEUP__MUI_A7__MUA base address */ #define WAKEUP__MUI_A7__MUA_BASE (0x42430000u) /** Peripheral WAKEUP__MUI_A7__MUA base pointer */ #define WAKEUP__MUI_A7__MUA ((MU_Type *)WAKEUP__MUI_A7__MUA_BASE) /** Peripheral WAKEUP__MUI_A8__MUA base address */ #define WAKEUP__MUI_A8__MUA_BASE (0x42730000u) /** Peripheral WAKEUP__MUI_A8__MUA base pointer */ #define WAKEUP__MUI_A8__MUA ((MU_Type *)WAKEUP__MUI_A8__MUA_BASE) /** Array initializer of MU peripheral base addresses */ #define MU_BASE_ADDRS { MU5_MUA_BASE, MU7_MUB_BASE, MU8_MUB_BASE, AON__MUI_A1__MUA_BASE, AON__MUI_A1__MUB_BASE, AON__MUI_A2__MUA_BASE, AON__MUI_A2__MUB_BASE, AON__MUI_A3__MUA_BASE, AON__MUI_A3__MUB_BASE, AON__MUI_A4__MUA_BASE, AON__MUI_A4__MUB_BASE, AON__MUI_A5__MUB_BASE, AON__MUI_A6__MUA_BASE, AON__MUI_A6__MUB_BASE, CAMERA__MUI_A1__MUA_BASE, CAMERA__MUI_A2__MUA_BASE, CAMERA__MUI_A3__MUA_BASE, CAMERA__MUI_A4__MUA_BASE, CAMERA__MUI_A5__MUA_BASE, CAMERA__MUI_A6__MUA_BASE, CAMERA__MUI_A7__MUA_BASE, CAMERA__MUI_A8__MUA_BASE, CAMERA__MUI_A9__MUA_BASE, WAKEUP__MUI_A7__MUA_BASE, WAKEUP__MUI_A8__MUA_BASE } /** Array initializer of MU peripheral base pointers */ #define MU_BASE_PTRS { MU5_MUA, MU7_MUB, MU8_MUB, AON__MUI_A1__MUA, AON__MUI_A1__MUB, AON__MUI_A2__MUA, AON__MUI_A2__MUB, AON__MUI_A3__MUA, AON__MUI_A3__MUB, AON__MUI_A4__MUA, AON__MUI_A4__MUB, AON__MUI_A5__MUB, AON__MUI_A6__MUA, AON__MUI_A6__MUB, CAMERA__MUI_A1__MUA, CAMERA__MUI_A2__MUA, CAMERA__MUI_A3__MUA, CAMERA__MUI_A4__MUA, CAMERA__MUI_A5__MUA, CAMERA__MUI_A6__MUA, CAMERA__MUI_A7__MUA, CAMERA__MUI_A8__MUA, CAMERA__MUI_A9__MUA, WAKEUP__MUI_A7__MUA, WAKEUP__MUI_A8__MUA } /** Interrupt vectors for the MU peripheral type */ #define MU_IRQS { MU5_A_IRQn, MU7_B_IRQn, MU8_B_IRQn, MU1_A_IRQn, MU1_B_IRQn, MU2_A_IRQn, MU2_B_IRQn, MU3_A_IRQn, MU3_B_IRQn, MU4_A_IRQn, MU4_B_IRQn, MU5_B_IRQn, MU6_A_IRQn, MU6_B_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } /*! * @} */ /* end of group MU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NETC_ENETC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_ENETC_Peripheral_Access_Layer NETC_ENETC Peripheral Access Layer * @{ */ /** NETC_ENETC - Register Layout Typedef */ typedef struct { __I uint32_t ECAPR0; /**< ENETC capability register 0, offset: 0x0 */ __I uint32_t ECAPR1; /**< ENETC capability register 1, offset: 0x4 */ __I uint32_t ECAPR2; /**< ENETC capability register 2, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t PMR; /**< Port mode register, offset: 0x10 */ uint8_t RESERVED_1[108]; __IO uint32_t PONVLANR; /**< Port outer native VLAN register, offset: 0x80 */ __IO uint32_t PINVLANR; /**< Port inner native VLAN register, offset: 0x84 */ __IO uint32_t PVCLCTR; /**< Port VLAN classification control register, offset: 0x88 */ uint8_t RESERVED_2[16]; __IO uint32_t PARCSCR; /**< Parser checksum configuration register, offset: 0x9C */ __IO uint32_t PARCECR[4]; /**< Parser custom EtherType 0 configuration register..Parser custom EtherType 3 configuration register, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_3[88]; __IO uint32_t PPAUONTR; /**< Port pause ON threshold register, offset: 0x108 */ __IO uint32_t PPAUOFFTR; /**< Port pause OFF threshold register, offset: 0x10C */ uint8_t RESERVED_4[16]; __I uint32_t PRXMBER; /**< Port receive memory buffer entitlement register, offset: 0x120 */ __I uint32_t PRXMBLR; /**< Port receive memory buffer limit register, offset: 0x124 */ __I uint32_t PRXBCR; /**< Port receive buffer count register, offset: 0x128 */ __I uint32_t PRXBCHWMR; /**< Port receive buffer count high watermark register, offset: 0x12C */ uint8_t RESERVED_5[16]; struct { /* offset: 0x140, array step: 0x10 */ __I uint32_t PICDRDCR; /**< Port ingress congestion DR0 discard count register..Port ingress congestion DR3 discard count register, array offset: 0x140, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t PICDRDCRRR; /**< Port ingress congestion DR0 discard count read-reset register..Port ingress congestion DR3 discard count read-reset register, array offset: 0x148, array step: 0x10 */ uint8_t RESERVED_1[4]; } PICDRADCR[4]; __IO uint32_t PICPDSR; /**< Port ingress congestion priority discard status register, offset: 0x180 */ uint8_t RESERVED_6[124]; __IO uint32_t PSIPMMR; /**< Port station interface promiscuous MAC mode register, offset: 0x200 */ __IO uint32_t PSIPVMR; /**< Port station interface promiscuous VLAN mode register, offset: 0x204 */ __I uint32_t PBFDSIR; /**< Port broadcast frames dropped due to MAC filtering register, offset: 0x208 */ __I uint32_t PFDMSAPR; /**< Port frame drop MAC source address pruning register, offset: 0x20C */ uint8_t RESERVED_7[48]; __I uint32_t PRSSCAPR; /**< Port RSS capability register, offset: 0x240 */ __IO uint32_t PRSSCR; /**< Port RSS Control Register, offset: 0x244 */ uint8_t RESERVED_8[8]; __IO uint32_t PRSSKR0; /**< Port RSS key register 0, offset: 0x250 */ __IO uint32_t PRSSKR1; /**< Port RSS key register 1, offset: 0x254 */ __IO uint32_t PRSSKR2; /**< Port RSS key register 2, offset: 0x258 */ __IO uint32_t PRSSKR3; /**< Port RSS key register 3, offset: 0x25C */ __IO uint32_t PRSSKR4; /**< Port RSS key register 4, offset: 0x260 */ __IO uint32_t PRSSKR5; /**< Port RSS key register 5, offset: 0x264 */ __IO uint32_t PRSSKR6; /**< Port RSS key register 6, offset: 0x268 */ __IO uint32_t PRSSKR7; /**< Port RSS key register 7, offset: 0x26C */ __IO uint32_t PRSSKR8; /**< Port RSS key register 8, offset: 0x270 */ __IO uint32_t PRSSKR9; /**< Port RSS key register 9, offset: 0x274 */ uint8_t RESERVED_9[8]; __I uint32_t PSIMAFCAPR; /**< Port station interface MAC address filtering capability register, offset: 0x280 */ __I uint32_t PUFDMFR; /**< Port unicast frames dropped due to MAC filtering register, offset: 0x284 */ __I uint32_t PMFDMFR; /**< Port multicast frames dropped due to MAC filtering register, offset: 0x288 */ uint8_t RESERVED_10[52]; __I uint32_t PSIVLANFCAPR; /**< Port station interface VLAN filtering capability register, offset: 0x2C0 */ __IO uint32_t PSIVLANFMR; /**< Port station interface VLAN filtering mode register, offset: 0x2C4 */ uint8_t RESERVED_11[8]; __I uint32_t PUFDVFR; /**< Port unicast frames dropped VLAN filtering register, offset: 0x2D0 */ __I uint32_t PMFDVFR; /**< Port multicast frames dropped VLAN filtering register, offset: 0x2D4 */ __I uint32_t PBFDVFR; /**< Port broadcast frames dropped VLAN filtering register, offset: 0x2D8 */ uint8_t RESERVED_12[100]; __IO uint32_t PLPMR; /**< Port low power mode register, offset: 0x340 */ __I uint32_t PWOSR; /**< Port wake-on status register, offset: 0x344 */ uint8_t RESERVED_13[40]; __IO uint32_t IPV2ICMPMR0; /**< Receive IPV to ICM priority mapping register 0, offset: 0x370 */ uint8_t RESERVED_14[12]; __IO uint32_t PRIO2TCMR0; /**< Transmit priority to traffic class mapping register 0, offset: 0x380 */ uint8_t RESERVED_15[12]; __IO uint32_t PTCTSDR[8]; /**< Port traffic class 0 time specific departure register..Port traffic class 7 time specific departure register, array offset: 0x390, array step: 0x4 */ uint8_t RESERVED_16[1104]; __I uint32_t SMCAPR; /**< Switch management capability register, offset: 0x800 */ uint8_t RESERVED_17[6140]; struct { /* offset: 0x2000, array step: 0x80 */ __IO uint32_t PSIPMAR0; /**< Port station interface 0 primary MAC address register 0..Port station interface 2 primary MAC address register 0, array offset: 0x2000, array step: 0x80 */ __IO uint32_t PSIPMAR1; /**< Port station interface 0 primary MAC address register 1..Port station interface 2 primary MAC address register 1, array offset: 0x2004, array step: 0x80 */ __IO uint32_t PSIVLANR; /**< Port station interface 0 VLAN register..Port station interface 2 VLAN register, array offset: 0x2008, array step: 0x80 */ uint8_t RESERVED_0[4]; __IO uint32_t PSICFGR0; /**< Port station interface 0 configuration register 0..Port station interface 2 configuration register 0, array offset: 0x2010, array step: 0x80 */ __IO uint32_t PSICFGR1; /**< Port station interface 1 configuration register 1..Port station interface 2 configuration register 1, array offset: 0x2014, array step: 0x80, valid indices: [1-2] */ __IO uint32_t PSICFGR2; /**< Port station interface 0 configuration register 2..Port station interface 2 configuration register 2, array offset: 0x2018, array step: 0x80 */ uint8_t RESERVED_1[20]; __IO uint32_t PSIVMAFCFGR; /**< Port station interface 0 VSI MAC address filtering configuration register..Port station interface 2 VSI MAC address filtering configuration register, array offset: 0x2030, array step: 0x80 */ __IO uint32_t PSIVLANFCFGR; /**< Port station interface 0 VLAN filtering configuration register..Port station interface 2 VLAN filtering configuration register, array offset: 0x2034, array step: 0x80 */ uint8_t RESERVED_2[24]; __IO uint32_t PSIUMHFR0; /**< Port station interface 0 unicast MAC hash filter register 0..Port station interface 2 unicast MAC hash filter register 0, array offset: 0x2050, array step: 0x80 */ __IO uint32_t PSIUMHFR1; /**< Port station interface 0 unicast MAC hash filter register 1..Port station interface 2 unicast MAC hash filter register 1, array offset: 0x2054, array step: 0x80 */ __IO uint32_t PSIMMHFR0; /**< Port station interface 0 multicast MAC hash filter register 0..Port station interface 2 multicast MAC hash filter register 0, array offset: 0x2058, array step: 0x80 */ __IO uint32_t PSIMMHFR1; /**< Port station interface 0 multicast MAC hash filter register 1..Port station interface 2 multicast MAC hash filter register 1, array offset: 0x205C, array step: 0x80 */ __IO uint32_t PSIVHFR0; /**< Port station interface 0 VLAN hash filter register 0..Port station interface 2 VLAN hash filter register 0, array offset: 0x2060, array step: 0x80 */ __IO uint32_t PSIVHFR1; /**< Port station interface 0 VLAN hash filter register 1..Port station interface 2 VLAN hash filter register 1, array offset: 0x2064, array step: 0x80 */ uint8_t RESERVED_3[24]; } NUM_SI[3]; } NETC_ENETC_Type; /* ---------------------------------------------------------------------------- -- NETC_ENETC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_ENETC_Register_Masks NETC_ENETC Register Masks * @{ */ /*! @name ECAPR0 - ENETC capability register 0 */ /*! @{ */ #define NETC_ENETC_ECAPR0_RFS_MASK (0x4U) #define NETC_ENETC_ECAPR0_RFS_SHIFT (2U) #define NETC_ENETC_ECAPR0_RFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_RFS_SHIFT)) & NETC_ENETC_ECAPR0_RFS_MASK) #define NETC_ENETC_ECAPR0_TSD_MASK (0x20U) #define NETC_ENETC_ECAPR0_TSD_SHIFT (5U) #define NETC_ENETC_ECAPR0_TSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_TSD_SHIFT)) & NETC_ENETC_ECAPR0_TSD_MASK) #define NETC_ENETC_ECAPR0_RSS_MASK (0x100U) #define NETC_ENETC_ECAPR0_RSS_SHIFT (8U) #define NETC_ENETC_ECAPR0_RSS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_RSS_SHIFT)) & NETC_ENETC_ECAPR0_RSS_MASK) #define NETC_ENETC_ECAPR0_RSC_MASK (0x200U) #define NETC_ENETC_ECAPR0_RSC_SHIFT (9U) #define NETC_ENETC_ECAPR0_RSC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_RSC_SHIFT)) & NETC_ENETC_ECAPR0_RSC_MASK) #define NETC_ENETC_ECAPR0_LSO_MASK (0x400U) #define NETC_ENETC_ECAPR0_LSO_SHIFT (10U) #define NETC_ENETC_ECAPR0_LSO(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_LSO_SHIFT)) & NETC_ENETC_ECAPR0_LSO_MASK) #define NETC_ENETC_ECAPR0_WO_MASK (0x2000U) #define NETC_ENETC_ECAPR0_WO_SHIFT (13U) #define NETC_ENETC_ECAPR0_WO(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_WO_SHIFT)) & NETC_ENETC_ECAPR0_WO_MASK) #define NETC_ENETC_ECAPR0_FS_MASK (0x10000U) #define NETC_ENETC_ECAPR0_FS_SHIFT (16U) /*! FS - Functional safety capability supported. */ #define NETC_ENETC_ECAPR0_FS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR0_FS_SHIFT)) & NETC_ENETC_ECAPR0_FS_MASK) /*! @} */ /*! @name ECAPR1 - ENETC capability register 1 */ /*! @{ */ #define NETC_ENETC_ECAPR1_NUM_TCS_MASK (0x70U) #define NETC_ENETC_ECAPR1_NUM_TCS_SHIFT (4U) #define NETC_ENETC_ECAPR1_NUM_TCS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_TCS_SHIFT)) & NETC_ENETC_ECAPR1_NUM_TCS_MASK) #define NETC_ENETC_ECAPR1_NUM_MCH_MASK (0x300U) #define NETC_ENETC_ECAPR1_NUM_MCH_SHIFT (8U) #define NETC_ENETC_ECAPR1_NUM_MCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_MCH_SHIFT)) & NETC_ENETC_ECAPR1_NUM_MCH_MASK) #define NETC_ENETC_ECAPR1_NUM_UCH_MASK (0xC00U) #define NETC_ENETC_ECAPR1_NUM_UCH_SHIFT (10U) #define NETC_ENETC_ECAPR1_NUM_UCH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_UCH_SHIFT)) & NETC_ENETC_ECAPR1_NUM_UCH_MASK) #define NETC_ENETC_ECAPR1_NUM_MSIX_MASK (0x7FF000U) #define NETC_ENETC_ECAPR1_NUM_MSIX_SHIFT (12U) /*! NUM_MSIX - Number of MSI-X */ #define NETC_ENETC_ECAPR1_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_MSIX_SHIFT)) & NETC_ENETC_ECAPR1_NUM_MSIX_MASK) #define NETC_ENETC_ECAPR1_NUM_VSI_MASK (0xF000000U) #define NETC_ENETC_ECAPR1_NUM_VSI_SHIFT (24U) #define NETC_ENETC_ECAPR1_NUM_VSI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_VSI_SHIFT)) & NETC_ENETC_ECAPR1_NUM_VSI_MASK) #define NETC_ENETC_ECAPR1_NUM_IPV_MASK (0x80000000U) #define NETC_ENETC_ECAPR1_NUM_IPV_SHIFT (31U) #define NETC_ENETC_ECAPR1_NUM_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR1_NUM_IPV_SHIFT)) & NETC_ENETC_ECAPR1_NUM_IPV_MASK) /*! @} */ /*! @name ECAPR2 - ENETC capability register 2 */ /*! @{ */ #define NETC_ENETC_ECAPR2_NUM_TX_BDR_MASK (0x3FFU) #define NETC_ENETC_ECAPR2_NUM_TX_BDR_SHIFT (0U) #define NETC_ENETC_ECAPR2_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR2_NUM_TX_BDR_SHIFT)) & NETC_ENETC_ECAPR2_NUM_TX_BDR_MASK) #define NETC_ENETC_ECAPR2_NUM_RX_BDR_MASK (0x3FF0000U) #define NETC_ENETC_ECAPR2_NUM_RX_BDR_SHIFT (16U) #define NETC_ENETC_ECAPR2_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_ECAPR2_NUM_RX_BDR_SHIFT)) & NETC_ENETC_ECAPR2_NUM_RX_BDR_MASK) /*! @} */ /*! @name PMR - Port mode register */ /*! @{ */ #define NETC_ENETC_PMR_SI0EN_MASK (0x10000U) #define NETC_ENETC_PMR_SI0EN_SHIFT (16U) #define NETC_ENETC_PMR_SI0EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMR_SI0EN_SHIFT)) & NETC_ENETC_PMR_SI0EN_MASK) #define NETC_ENETC_PMR_SI1EN_MASK (0x20000U) #define NETC_ENETC_PMR_SI1EN_SHIFT (17U) #define NETC_ENETC_PMR_SI1EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMR_SI1EN_SHIFT)) & NETC_ENETC_PMR_SI1EN_MASK) #define NETC_ENETC_PMR_SI2EN_MASK (0x40000U) #define NETC_ENETC_PMR_SI2EN_SHIFT (18U) #define NETC_ENETC_PMR_SI2EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMR_SI2EN_SHIFT)) & NETC_ENETC_PMR_SI2EN_MASK) /*! @} */ /*! @name PONVLANR - Port outer native VLAN register */ /*! @{ */ #define NETC_ENETC_PONVLANR_VID_MASK (0xFFFU) #define NETC_ENETC_PONVLANR_VID_SHIFT (0U) #define NETC_ENETC_PONVLANR_VID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_VID_SHIFT)) & NETC_ENETC_PONVLANR_VID_MASK) #define NETC_ENETC_PONVLANR_DEI_MASK (0x1000U) #define NETC_ENETC_PONVLANR_DEI_SHIFT (12U) #define NETC_ENETC_PONVLANR_DEI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_DEI_SHIFT)) & NETC_ENETC_PONVLANR_DEI_MASK) #define NETC_ENETC_PONVLANR_PCP_MASK (0xE000U) #define NETC_ENETC_PONVLANR_PCP_SHIFT (13U) #define NETC_ENETC_PONVLANR_PCP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_PCP_SHIFT)) & NETC_ENETC_PONVLANR_PCP_MASK) #define NETC_ENETC_PONVLANR_TPID_MASK (0x30000U) #define NETC_ENETC_PONVLANR_TPID_SHIFT (16U) /*! TPID * 0b00..Standard C-VLAN 0x8100 * 0b01..Standard S-VLAN 0x88A8 * 0b10..Custom VLAN as defined by CVLANR1[ETYPE] * 0b11..Custom VLAN as defined by CVLANR2[ETYPE] */ #define NETC_ENETC_PONVLANR_TPID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_TPID_SHIFT)) & NETC_ENETC_PONVLANR_TPID_MASK) #define NETC_ENETC_PONVLANR_PNE_MASK (0x40000U) #define NETC_ENETC_PONVLANR_PNE_SHIFT (18U) #define NETC_ENETC_PONVLANR_PNE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_PNE_SHIFT)) & NETC_ENETC_PONVLANR_PNE_MASK) #define NETC_ENETC_PONVLANR_VZE_MASK (0x80000U) #define NETC_ENETC_PONVLANR_VZE_SHIFT (19U) #define NETC_ENETC_PONVLANR_VZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PONVLANR_VZE_SHIFT)) & NETC_ENETC_PONVLANR_VZE_MASK) /*! @} */ /*! @name PINVLANR - Port inner native VLAN register */ /*! @{ */ #define NETC_ENETC_PINVLANR_VID_MASK (0xFFFU) #define NETC_ENETC_PINVLANR_VID_SHIFT (0U) #define NETC_ENETC_PINVLANR_VID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_VID_SHIFT)) & NETC_ENETC_PINVLANR_VID_MASK) #define NETC_ENETC_PINVLANR_DEI_MASK (0x1000U) #define NETC_ENETC_PINVLANR_DEI_SHIFT (12U) #define NETC_ENETC_PINVLANR_DEI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_DEI_SHIFT)) & NETC_ENETC_PINVLANR_DEI_MASK) #define NETC_ENETC_PINVLANR_PCP_MASK (0xE000U) #define NETC_ENETC_PINVLANR_PCP_SHIFT (13U) #define NETC_ENETC_PINVLANR_PCP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_PCP_SHIFT)) & NETC_ENETC_PINVLANR_PCP_MASK) #define NETC_ENETC_PINVLANR_TPID_MASK (0x30000U) #define NETC_ENETC_PINVLANR_TPID_SHIFT (16U) /*! TPID * 0b00..Standard C-VLAN 0x8100 * 0b01..Standard S-VLAN 0x88A8 * 0b10..Custom VLAN as defined by CVLANR1[ETYPE] * 0b11..Custom VLAN as defined by CVLANR2[ETYPE] */ #define NETC_ENETC_PINVLANR_TPID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_TPID_SHIFT)) & NETC_ENETC_PINVLANR_TPID_MASK) #define NETC_ENETC_PINVLANR_PNE_MASK (0x40000U) #define NETC_ENETC_PINVLANR_PNE_SHIFT (18U) #define NETC_ENETC_PINVLANR_PNE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_PNE_SHIFT)) & NETC_ENETC_PINVLANR_PNE_MASK) #define NETC_ENETC_PINVLANR_VZE_MASK (0x80000U) #define NETC_ENETC_PINVLANR_VZE_SHIFT (19U) #define NETC_ENETC_PINVLANR_VZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PINVLANR_VZE_SHIFT)) & NETC_ENETC_PINVLANR_VZE_MASK) /*! @} */ /*! @name PVCLCTR - Port VLAN classification control register */ /*! @{ */ #define NETC_ENETC_PVCLCTR_OAI_MASK (0x200U) #define NETC_ENETC_PVCLCTR_OAI_SHIFT (9U) #define NETC_ENETC_PVCLCTR_OAI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PVCLCTR_OAI_SHIFT)) & NETC_ENETC_PVCLCTR_OAI_MASK) /*! @} */ /*! @name PARCSCR - Parser checksum configuration register */ /*! @{ */ #define NETC_ENETC_PARCSCR_L4CD_MASK (0x1U) #define NETC_ENETC_PARCSCR_L4CD_SHIFT (0U) /*! L4CD - Layer 4 TCP and UDP checksum validation Disable. * 0b0..Enabled * 0b1..Disabled */ #define NETC_ENETC_PARCSCR_L4CD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCSCR_L4CD_SHIFT)) & NETC_ENETC_PARCSCR_L4CD_MASK) #define NETC_ENETC_PARCSCR_L3CD_MASK (0x2U) #define NETC_ENETC_PARCSCR_L3CD_SHIFT (1U) /*! L3CD - Layer 3 IPv4 Header checksum validation Disable. * 0b0..Enabled * 0b1..Disabled */ #define NETC_ENETC_PARCSCR_L3CD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCSCR_L3CD_SHIFT)) & NETC_ENETC_PARCSCR_L3CD_MASK) /*! @} */ /*! @name PARCECR - Parser custom EtherType 0 configuration register..Parser custom EtherType 3 configuration register */ /*! @{ */ #define NETC_ENETC_PARCECR_CP_MASK (0xFU) #define NETC_ENETC_PARCECR_CP_SHIFT (0U) /*! CP - CP */ #define NETC_ENETC_PARCECR_CP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCECR_CP_SHIFT)) & NETC_ENETC_PARCECR_CP_MASK) #define NETC_ENETC_PARCECR_EN_MASK (0x20U) #define NETC_ENETC_PARCECR_EN_SHIFT (5U) /*! EN - EN */ #define NETC_ENETC_PARCECR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCECR_EN_SHIFT)) & NETC_ENETC_PARCECR_EN_MASK) #define NETC_ENETC_PARCECR_ETYPE_MASK (0xFFFF0000U) #define NETC_ENETC_PARCECR_ETYPE_SHIFT (16U) /*! ETYPE - EtherType */ #define NETC_ENETC_PARCECR_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PARCECR_ETYPE_SHIFT)) & NETC_ENETC_PARCECR_ETYPE_MASK) /*! @} */ /* The count of NETC_ENETC_PARCECR */ #define NETC_ENETC_PARCECR_COUNT (4U) /*! @name PPAUONTR - Port pause ON threshold register */ /*! @{ */ #define NETC_ENETC_PPAUONTR_THRESH_MASK (0xFFFFFFU) #define NETC_ENETC_PPAUONTR_THRESH_SHIFT (0U) #define NETC_ENETC_PPAUONTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PPAUONTR_THRESH_SHIFT)) & NETC_ENETC_PPAUONTR_THRESH_MASK) /*! @} */ /*! @name PPAUOFFTR - Port pause OFF threshold register */ /*! @{ */ #define NETC_ENETC_PPAUOFFTR_THRESH_MASK (0xFFFFFFU) #define NETC_ENETC_PPAUOFFTR_THRESH_SHIFT (0U) #define NETC_ENETC_PPAUOFFTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PPAUOFFTR_THRESH_SHIFT)) & NETC_ENETC_PPAUOFFTR_THRESH_MASK) /*! @} */ /*! @name PRXMBER - Port receive memory buffer entitlement register */ /*! @{ */ #define NETC_ENETC_PRXMBER_AMOUNT_MASK (0xFFFFFFU) #define NETC_ENETC_PRXMBER_AMOUNT_SHIFT (0U) #define NETC_ENETC_PRXMBER_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXMBER_AMOUNT_SHIFT)) & NETC_ENETC_PRXMBER_AMOUNT_MASK) /*! @} */ /*! @name PRXMBLR - Port receive memory buffer limit register */ /*! @{ */ #define NETC_ENETC_PRXMBLR_LIMIT_MASK (0xFFFFFFU) #define NETC_ENETC_PRXMBLR_LIMIT_SHIFT (0U) #define NETC_ENETC_PRXMBLR_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXMBLR_LIMIT_SHIFT)) & NETC_ENETC_PRXMBLR_LIMIT_MASK) /*! @} */ /*! @name PRXBCR - Port receive buffer count register */ /*! @{ */ #define NETC_ENETC_PRXBCR_COUNT_MASK (0xFFFFFFU) #define NETC_ENETC_PRXBCR_COUNT_SHIFT (0U) #define NETC_ENETC_PRXBCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXBCR_COUNT_SHIFT)) & NETC_ENETC_PRXBCR_COUNT_MASK) /*! @} */ /*! @name PRXBCHWMR - Port receive buffer count high watermark register */ /*! @{ */ #define NETC_ENETC_PRXBCHWMR_WATERMARK_MASK (0xFFFFFFU) #define NETC_ENETC_PRXBCHWMR_WATERMARK_SHIFT (0U) #define NETC_ENETC_PRXBCHWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRXBCHWMR_WATERMARK_SHIFT)) & NETC_ENETC_PRXBCHWMR_WATERMARK_MASK) /*! @} */ /*! @name PICDRDCR - Port ingress congestion DR0 discard count register..Port ingress congestion DR3 discard count register */ /*! @{ */ #define NETC_ENETC_PICDRDCR_COUNT_MASK (0xFFFFFFFFU) #define NETC_ENETC_PICDRDCR_COUNT_SHIFT (0U) #define NETC_ENETC_PICDRDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICDRDCR_COUNT_SHIFT)) & NETC_ENETC_PICDRDCR_COUNT_MASK) /*! @} */ /* The count of NETC_ENETC_PICDRDCR */ #define NETC_ENETC_PICDRADCR_PICDRDCR_COUNT (4U) /*! @name PICDRDCRRR - Port ingress congestion DR0 discard count read-reset register..Port ingress congestion DR3 discard count read-reset register */ /*! @{ */ #define NETC_ENETC_PICDRDCRRR_COUNT_MASK (0xFFFFFFFFU) #define NETC_ENETC_PICDRDCRRR_COUNT_SHIFT (0U) #define NETC_ENETC_PICDRDCRRR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICDRDCRRR_COUNT_SHIFT)) & NETC_ENETC_PICDRDCRRR_COUNT_MASK) /*! @} */ /* The count of NETC_ENETC_PICDRDCRRR */ #define NETC_ENETC_PICDRADCR_PICDRDCRRR_COUNT (4U) /*! @name PICPDSR - Port ingress congestion priority discard status register */ /*! @{ */ #define NETC_ENETC_PICPDSR_DR0_P0DS_MASK (0x1U) #define NETC_ENETC_PICPDSR_DR0_P0DS_SHIFT (0U) #define NETC_ENETC_PICPDSR_DR0_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR0_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR0_P0DS_MASK) #define NETC_ENETC_PICPDSR_DR0_P1DS_MASK (0x10U) #define NETC_ENETC_PICPDSR_DR0_P1DS_SHIFT (4U) #define NETC_ENETC_PICPDSR_DR0_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR0_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR0_P1DS_MASK) #define NETC_ENETC_PICPDSR_DR1_P0DS_MASK (0x100U) #define NETC_ENETC_PICPDSR_DR1_P0DS_SHIFT (8U) #define NETC_ENETC_PICPDSR_DR1_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR1_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR1_P0DS_MASK) #define NETC_ENETC_PICPDSR_DR1_P1DS_MASK (0x1000U) #define NETC_ENETC_PICPDSR_DR1_P1DS_SHIFT (12U) #define NETC_ENETC_PICPDSR_DR1_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR1_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR1_P1DS_MASK) #define NETC_ENETC_PICPDSR_DR2_P0DS_MASK (0x10000U) #define NETC_ENETC_PICPDSR_DR2_P0DS_SHIFT (16U) #define NETC_ENETC_PICPDSR_DR2_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR2_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR2_P0DS_MASK) #define NETC_ENETC_PICPDSR_DR2_P1DS_MASK (0x100000U) #define NETC_ENETC_PICPDSR_DR2_P1DS_SHIFT (20U) #define NETC_ENETC_PICPDSR_DR2_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR2_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR2_P1DS_MASK) #define NETC_ENETC_PICPDSR_DR3_P0DS_MASK (0x1000000U) #define NETC_ENETC_PICPDSR_DR3_P0DS_SHIFT (24U) #define NETC_ENETC_PICPDSR_DR3_P0DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR3_P0DS_SHIFT)) & NETC_ENETC_PICPDSR_DR3_P0DS_MASK) #define NETC_ENETC_PICPDSR_DR3_P1DS_MASK (0x10000000U) #define NETC_ENETC_PICPDSR_DR3_P1DS_SHIFT (28U) #define NETC_ENETC_PICPDSR_DR3_P1DS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PICPDSR_DR3_P1DS_SHIFT)) & NETC_ENETC_PICPDSR_DR3_P1DS_MASK) /*! @} */ /*! @name PSIPMMR - Port station interface promiscuous MAC mode register */ /*! @{ */ #define NETC_ENETC_PSIPMMR_SI0_MAC_UP_MASK (0x1U) #define NETC_ENETC_PSIPMMR_SI0_MAC_UP_SHIFT (0U) #define NETC_ENETC_PSIPMMR_SI0_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI0_MAC_UP_SHIFT)) & NETC_ENETC_PSIPMMR_SI0_MAC_UP_MASK) #define NETC_ENETC_PSIPMMR_SI1_MAC_UP_MASK (0x2U) #define NETC_ENETC_PSIPMMR_SI1_MAC_UP_SHIFT (1U) #define NETC_ENETC_PSIPMMR_SI1_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI1_MAC_UP_SHIFT)) & NETC_ENETC_PSIPMMR_SI1_MAC_UP_MASK) #define NETC_ENETC_PSIPMMR_SI2_MAC_UP_MASK (0x4U) #define NETC_ENETC_PSIPMMR_SI2_MAC_UP_SHIFT (2U) #define NETC_ENETC_PSIPMMR_SI2_MAC_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI2_MAC_UP_SHIFT)) & NETC_ENETC_PSIPMMR_SI2_MAC_UP_MASK) #define NETC_ENETC_PSIPMMR_SI0_MAC_MP_MASK (0x10000U) #define NETC_ENETC_PSIPMMR_SI0_MAC_MP_SHIFT (16U) #define NETC_ENETC_PSIPMMR_SI0_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI0_MAC_MP_SHIFT)) & NETC_ENETC_PSIPMMR_SI0_MAC_MP_MASK) #define NETC_ENETC_PSIPMMR_SI1_MAC_MP_MASK (0x20000U) #define NETC_ENETC_PSIPMMR_SI1_MAC_MP_SHIFT (17U) #define NETC_ENETC_PSIPMMR_SI1_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI1_MAC_MP_SHIFT)) & NETC_ENETC_PSIPMMR_SI1_MAC_MP_MASK) #define NETC_ENETC_PSIPMMR_SI2_MAC_MP_MASK (0x40000U) #define NETC_ENETC_PSIPMMR_SI2_MAC_MP_SHIFT (18U) #define NETC_ENETC_PSIPMMR_SI2_MAC_MP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMMR_SI2_MAC_MP_SHIFT)) & NETC_ENETC_PSIPMMR_SI2_MAC_MP_MASK) /*! @} */ /*! @name PSIPVMR - Port station interface promiscuous VLAN mode register */ /*! @{ */ #define NETC_ENETC_PSIPVMR_SI0_VLAN_P_MASK (0x1U) #define NETC_ENETC_PSIPVMR_SI0_VLAN_P_SHIFT (0U) #define NETC_ENETC_PSIPVMR_SI0_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI0_VLAN_P_SHIFT)) & NETC_ENETC_PSIPVMR_SI0_VLAN_P_MASK) #define NETC_ENETC_PSIPVMR_SI1_VLAN_P_MASK (0x2U) #define NETC_ENETC_PSIPVMR_SI1_VLAN_P_SHIFT (1U) #define NETC_ENETC_PSIPVMR_SI1_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI1_VLAN_P_SHIFT)) & NETC_ENETC_PSIPVMR_SI1_VLAN_P_MASK) #define NETC_ENETC_PSIPVMR_SI2_VLAN_P_MASK (0x4U) #define NETC_ENETC_PSIPVMR_SI2_VLAN_P_SHIFT (2U) #define NETC_ENETC_PSIPVMR_SI2_VLAN_P(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI2_VLAN_P_SHIFT)) & NETC_ENETC_PSIPVMR_SI2_VLAN_P_MASK) #define NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_MASK (0x10000U) #define NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_SHIFT (16U) #define NETC_ENETC_PSIPVMR_SI0_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_SHIFT)) & NETC_ENETC_PSIPVMR_SI0_VLAN_UTA_MASK) #define NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_MASK (0x20000U) #define NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_SHIFT (17U) #define NETC_ENETC_PSIPVMR_SI1_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_SHIFT)) & NETC_ENETC_PSIPVMR_SI1_VLAN_UTA_MASK) #define NETC_ENETC_PSIPVMR_SI2_VLAN_UTA_MASK (0x40000U) #define NETC_ENETC_PSIPVMR_SI2_VLAN_UTA_SHIFT (18U) #define NETC_ENETC_PSIPVMR_SI2_VLAN_UTA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPVMR_SI2_VLAN_UTA_SHIFT)) & NETC_ENETC_PSIPVMR_SI2_VLAN_UTA_MASK) /*! @} */ /*! @name PBFDSIR - Port broadcast frames dropped due to MAC filtering register */ /*! @{ */ #define NETC_ENETC_PBFDSIR_FRAME_DROP_MASK (0xFFFFFFFFU) #define NETC_ENETC_PBFDSIR_FRAME_DROP_SHIFT (0U) #define NETC_ENETC_PBFDSIR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PBFDSIR_FRAME_DROP_SHIFT)) & NETC_ENETC_PBFDSIR_FRAME_DROP_MASK) /*! @} */ /*! @name PFDMSAPR - Port frame drop MAC source address pruning register */ /*! @{ */ #define NETC_ENETC_PFDMSAPR_FRAME_DROP_MASK (0xFFFFFFFFU) #define NETC_ENETC_PFDMSAPR_FRAME_DROP_SHIFT (0U) #define NETC_ENETC_PFDMSAPR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PFDMSAPR_FRAME_DROP_SHIFT)) & NETC_ENETC_PFDMSAPR_FRAME_DROP_MASK) /*! @} */ /*! @name PRSSCAPR - Port RSS capability register */ /*! @{ */ #define NETC_ENETC_PRSSCAPR_NUM_RSS_MASK (0xFU) #define NETC_ENETC_PRSSCAPR_NUM_RSS_SHIFT (0U) #define NETC_ENETC_PRSSCAPR_NUM_RSS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSCAPR_NUM_RSS_SHIFT)) & NETC_ENETC_PRSSCAPR_NUM_RSS_MASK) /*! @} */ /*! @name PRSSCR - Port RSS Control Register */ /*! @{ */ #define NETC_ENETC_PRSSCR_IP4TCP_DIS_MASK (0x1U) #define NETC_ENETC_PRSSCR_IP4TCP_DIS_SHIFT (0U) /*! IP4TCP_DIS - IPv4 with TCP packet disable. */ #define NETC_ENETC_PRSSCR_IP4TCP_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSCR_IP4TCP_DIS_SHIFT)) & NETC_ENETC_PRSSCR_IP4TCP_DIS_MASK) #define NETC_ENETC_PRSSCR_IP4_DIS_MASK (0x2U) #define NETC_ENETC_PRSSCR_IP4_DIS_SHIFT (1U) /*! IP4_DIS - IPv4 packet disable. */ #define NETC_ENETC_PRSSCR_IP4_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSCR_IP4_DIS_SHIFT)) & NETC_ENETC_PRSSCR_IP4_DIS_MASK) #define NETC_ENETC_PRSSCR_IP6TCP_DIS_MASK (0x4U) #define NETC_ENETC_PRSSCR_IP6TCP_DIS_SHIFT (2U) /*! IP6TCP_DIS - IPv6 with TCP packet disable. */ #define NETC_ENETC_PRSSCR_IP6TCP_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSCR_IP6TCP_DIS_SHIFT)) & NETC_ENETC_PRSSCR_IP6TCP_DIS_MASK) #define NETC_ENETC_PRSSCR_IP4UDP_DIS_MASK (0x8U) #define NETC_ENETC_PRSSCR_IP4UDP_DIS_SHIFT (3U) /*! IP4UDP_DIS - IPv4 with UDP disable. */ #define NETC_ENETC_PRSSCR_IP4UDP_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSCR_IP4UDP_DIS_SHIFT)) & NETC_ENETC_PRSSCR_IP4UDP_DIS_MASK) #define NETC_ENETC_PRSSCR_IP6UDP_DIS_MASK (0x10U) #define NETC_ENETC_PRSSCR_IP6UDP_DIS_SHIFT (4U) /*! IP6UDP_DIS - IPv6 with UDP disable. */ #define NETC_ENETC_PRSSCR_IP6UDP_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSCR_IP6UDP_DIS_SHIFT)) & NETC_ENETC_PRSSCR_IP6UDP_DIS_MASK) #define NETC_ENETC_PRSSCR_IP6_DIS_MASK (0x20U) #define NETC_ENETC_PRSSCR_IP6_DIS_SHIFT (5U) /*! IP6_DIS - IPv6 packet disable. */ #define NETC_ENETC_PRSSCR_IP6_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSCR_IP6_DIS_SHIFT)) & NETC_ENETC_PRSSCR_IP6_DIS_MASK) /*! @} */ /*! @name PRSSKR0 - Port RSS key register 0 */ /*! @{ */ #define NETC_ENETC_PRSSKR0_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR0_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR0_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR0_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR0_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR1 - Port RSS key register 1 */ /*! @{ */ #define NETC_ENETC_PRSSKR1_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR1_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR1_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR1_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR1_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR2 - Port RSS key register 2 */ /*! @{ */ #define NETC_ENETC_PRSSKR2_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR2_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR2_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR2_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR2_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR3 - Port RSS key register 3 */ /*! @{ */ #define NETC_ENETC_PRSSKR3_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR3_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR3_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR3_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR3_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR4 - Port RSS key register 4 */ /*! @{ */ #define NETC_ENETC_PRSSKR4_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR4_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR4_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR4_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR4_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR5 - Port RSS key register 5 */ /*! @{ */ #define NETC_ENETC_PRSSKR5_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR5_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR5_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR5_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR5_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR6 - Port RSS key register 6 */ /*! @{ */ #define NETC_ENETC_PRSSKR6_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR6_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR6_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR6_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR6_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR7 - Port RSS key register 7 */ /*! @{ */ #define NETC_ENETC_PRSSKR7_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR7_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR7_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR7_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR7_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR8 - Port RSS key register 8 */ /*! @{ */ #define NETC_ENETC_PRSSKR8_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR8_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR8_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR8_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR8_RSS_KEY_MASK) /*! @} */ /*! @name PRSSKR9 - Port RSS key register 9 */ /*! @{ */ #define NETC_ENETC_PRSSKR9_RSS_KEY_MASK (0xFFFFFFFFU) #define NETC_ENETC_PRSSKR9_RSS_KEY_SHIFT (0U) #define NETC_ENETC_PRSSKR9_RSS_KEY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRSSKR9_RSS_KEY_SHIFT)) & NETC_ENETC_PRSSKR9_RSS_KEY_MASK) /*! @} */ /*! @name PSIMAFCAPR - Port station interface MAC address filtering capability register */ /*! @{ */ #define NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_MASK (0xFFFU) #define NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_SHIFT (0U) #define NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_SHIFT)) & NETC_ENETC_PSIMAFCAPR_NUM_MAC_AFTE_MASK) /*! @} */ /*! @name PUFDMFR - Port unicast frames dropped due to MAC filtering register */ /*! @{ */ #define NETC_ENETC_PUFDMFR_FRAME_DROP_MASK (0xFFFFFFFFU) #define NETC_ENETC_PUFDMFR_FRAME_DROP_SHIFT (0U) #define NETC_ENETC_PUFDMFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PUFDMFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PUFDMFR_FRAME_DROP_MASK) /*! @} */ /*! @name PMFDMFR - Port multicast frames dropped due to MAC filtering register */ /*! @{ */ #define NETC_ENETC_PMFDMFR_FRAME_DROP_MASK (0xFFFFFFFFU) #define NETC_ENETC_PMFDMFR_FRAME_DROP_SHIFT (0U) #define NETC_ENETC_PMFDMFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMFDMFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PMFDMFR_FRAME_DROP_MASK) /*! @} */ /*! @name PSIVLANFCAPR - Port station interface VLAN filtering capability register */ /*! @{ */ #define NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_MASK (0xFFFU) #define NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_SHIFT (0U) #define NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_SHIFT)) & NETC_ENETC_PSIVLANFCAPR_NUM_VLAN_FTE_MASK) /*! @} */ /*! @name PSIVLANFMR - Port station interface VLAN filtering mode register */ /*! @{ */ #define NETC_ENETC_PSIVLANFMR_VS_MASK (0x1U) #define NETC_ENETC_PSIVLANFMR_VS_SHIFT (0U) #define NETC_ENETC_PSIVLANFMR_VS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANFMR_VS_SHIFT)) & NETC_ENETC_PSIVLANFMR_VS_MASK) /*! @} */ /*! @name PUFDVFR - Port unicast frames dropped VLAN filtering register */ /*! @{ */ #define NETC_ENETC_PUFDVFR_FRAME_DROP_MASK (0xFFFFFFFFU) #define NETC_ENETC_PUFDVFR_FRAME_DROP_SHIFT (0U) #define NETC_ENETC_PUFDVFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PUFDVFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PUFDVFR_FRAME_DROP_MASK) /*! @} */ /*! @name PMFDVFR - Port multicast frames dropped VLAN filtering register */ /*! @{ */ #define NETC_ENETC_PMFDVFR_FRAME_DROP_MASK (0xFFFFFFFFU) #define NETC_ENETC_PMFDVFR_FRAME_DROP_SHIFT (0U) #define NETC_ENETC_PMFDVFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PMFDVFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PMFDVFR_FRAME_DROP_MASK) /*! @} */ /*! @name PBFDVFR - Port broadcast frames dropped VLAN filtering register */ /*! @{ */ #define NETC_ENETC_PBFDVFR_FRAME_DROP_MASK (0xFFFFFFFFU) #define NETC_ENETC_PBFDVFR_FRAME_DROP_SHIFT (0U) #define NETC_ENETC_PBFDVFR_FRAME_DROP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PBFDVFR_FRAME_DROP_SHIFT)) & NETC_ENETC_PBFDVFR_FRAME_DROP_MASK) /*! @} */ /*! @name PLPMR - Port low power mode register */ /*! @{ */ #define NETC_ENETC_PLPMR_WME_MASK (0x1U) #define NETC_ENETC_PLPMR_WME_SHIFT (0U) #define NETC_ENETC_PLPMR_WME(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PLPMR_WME_SHIFT)) & NETC_ENETC_PLPMR_WME_MASK) /*! @} */ /*! @name PWOSR - Port wake-on status register */ /*! @{ */ #define NETC_ENETC_PWOSR_WOLA_MASK (0x1U) #define NETC_ENETC_PWOSR_WOLA_SHIFT (0U) #define NETC_ENETC_PWOSR_WOLA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PWOSR_WOLA_SHIFT)) & NETC_ENETC_PWOSR_WOLA_MASK) #define NETC_ENETC_PWOSR_ICMB_MASK (0x2U) #define NETC_ENETC_PWOSR_ICMB_SHIFT (1U) #define NETC_ENETC_PWOSR_ICMB(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PWOSR_ICMB_SHIFT)) & NETC_ENETC_PWOSR_ICMB_MASK) /*! @} */ /*! @name IPV2ICMPMR0 - Receive IPV to ICM priority mapping register 0 */ /*! @{ */ #define NETC_ENETC_IPV2ICMPMR0_IPV0ICM_MASK (0x1U) #define NETC_ENETC_IPV2ICMPMR0_IPV0ICM_SHIFT (0U) #define NETC_ENETC_IPV2ICMPMR0_IPV0ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV0ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV0ICM_MASK) #define NETC_ENETC_IPV2ICMPMR0_IPV1ICM_MASK (0x10U) #define NETC_ENETC_IPV2ICMPMR0_IPV1ICM_SHIFT (4U) #define NETC_ENETC_IPV2ICMPMR0_IPV1ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV1ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV1ICM_MASK) #define NETC_ENETC_IPV2ICMPMR0_IPV2ICM_MASK (0x100U) #define NETC_ENETC_IPV2ICMPMR0_IPV2ICM_SHIFT (8U) #define NETC_ENETC_IPV2ICMPMR0_IPV2ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV2ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV2ICM_MASK) #define NETC_ENETC_IPV2ICMPMR0_IPV3ICM_MASK (0x1000U) #define NETC_ENETC_IPV2ICMPMR0_IPV3ICM_SHIFT (12U) #define NETC_ENETC_IPV2ICMPMR0_IPV3ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV3ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV3ICM_MASK) #define NETC_ENETC_IPV2ICMPMR0_IPV4ICM_MASK (0x10000U) #define NETC_ENETC_IPV2ICMPMR0_IPV4ICM_SHIFT (16U) #define NETC_ENETC_IPV2ICMPMR0_IPV4ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV4ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV4ICM_MASK) #define NETC_ENETC_IPV2ICMPMR0_IPV5ICM_MASK (0x100000U) #define NETC_ENETC_IPV2ICMPMR0_IPV5ICM_SHIFT (20U) #define NETC_ENETC_IPV2ICMPMR0_IPV5ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV5ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV5ICM_MASK) #define NETC_ENETC_IPV2ICMPMR0_IPV6ICM_MASK (0x1000000U) #define NETC_ENETC_IPV2ICMPMR0_IPV6ICM_SHIFT (24U) #define NETC_ENETC_IPV2ICMPMR0_IPV6ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV6ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV6ICM_MASK) #define NETC_ENETC_IPV2ICMPMR0_IPV7ICM_MASK (0x10000000U) #define NETC_ENETC_IPV2ICMPMR0_IPV7ICM_SHIFT (28U) #define NETC_ENETC_IPV2ICMPMR0_IPV7ICM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_IPV2ICMPMR0_IPV7ICM_SHIFT)) & NETC_ENETC_IPV2ICMPMR0_IPV7ICM_MASK) /*! @} */ /*! @name PRIO2TCMR0 - Transmit priority to traffic class mapping register 0 */ /*! @{ */ #define NETC_ENETC_PRIO2TCMR0_PRIO0TC_MASK (0x7U) #define NETC_ENETC_PRIO2TCMR0_PRIO0TC_SHIFT (0U) #define NETC_ENETC_PRIO2TCMR0_PRIO0TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO0TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO0TC_MASK) #define NETC_ENETC_PRIO2TCMR0_PRIO1TC_MASK (0x70U) #define NETC_ENETC_PRIO2TCMR0_PRIO1TC_SHIFT (4U) #define NETC_ENETC_PRIO2TCMR0_PRIO1TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO1TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO1TC_MASK) #define NETC_ENETC_PRIO2TCMR0_PRIO2TC_MASK (0x700U) #define NETC_ENETC_PRIO2TCMR0_PRIO2TC_SHIFT (8U) #define NETC_ENETC_PRIO2TCMR0_PRIO2TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO2TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO2TC_MASK) #define NETC_ENETC_PRIO2TCMR0_PRIO3TC_MASK (0x7000U) #define NETC_ENETC_PRIO2TCMR0_PRIO3TC_SHIFT (12U) #define NETC_ENETC_PRIO2TCMR0_PRIO3TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO3TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO3TC_MASK) #define NETC_ENETC_PRIO2TCMR0_PRIO4TC_MASK (0x70000U) #define NETC_ENETC_PRIO2TCMR0_PRIO4TC_SHIFT (16U) #define NETC_ENETC_PRIO2TCMR0_PRIO4TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO4TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO4TC_MASK) #define NETC_ENETC_PRIO2TCMR0_PRIO5TC_MASK (0x700000U) #define NETC_ENETC_PRIO2TCMR0_PRIO5TC_SHIFT (20U) #define NETC_ENETC_PRIO2TCMR0_PRIO5TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO5TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO5TC_MASK) #define NETC_ENETC_PRIO2TCMR0_PRIO6TC_MASK (0x7000000U) #define NETC_ENETC_PRIO2TCMR0_PRIO6TC_SHIFT (24U) #define NETC_ENETC_PRIO2TCMR0_PRIO6TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO6TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO6TC_MASK) #define NETC_ENETC_PRIO2TCMR0_PRIO7TC_MASK (0x70000000U) #define NETC_ENETC_PRIO2TCMR0_PRIO7TC_SHIFT (28U) #define NETC_ENETC_PRIO2TCMR0_PRIO7TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PRIO2TCMR0_PRIO7TC_SHIFT)) & NETC_ENETC_PRIO2TCMR0_PRIO7TC_MASK) /*! @} */ /*! @name PTCTSDR - Port traffic class 0 time specific departure register..Port traffic class 7 time specific departure register */ /*! @{ */ #define NETC_ENETC_PTCTSDR_TSDE_MASK (0x80000000U) #define NETC_ENETC_PTCTSDR_TSDE_SHIFT (31U) /*! TSDE - Time Specific Departure Enable * 0b0..Disabled * 0b1..Enabled */ #define NETC_ENETC_PTCTSDR_TSDE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PTCTSDR_TSDE_SHIFT)) & NETC_ENETC_PTCTSDR_TSDE_MASK) /*! @} */ /* The count of NETC_ENETC_PTCTSDR */ #define NETC_ENETC_PTCTSDR_COUNT (8U) /*! @name SMCAPR - Switch management capability register */ /*! @{ */ #define NETC_ENETC_SMCAPR_SM_MASK (0x1U) #define NETC_ENETC_SMCAPR_SM_SHIFT (0U) #define NETC_ENETC_SMCAPR_SM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_SMCAPR_SM_SHIFT)) & NETC_ENETC_SMCAPR_SM_MASK) /*! @} */ /*! @name PSIPMAR0 - Port station interface 0 primary MAC address register 0..Port station interface 2 primary MAC address register 0 */ /*! @{ */ #define NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) #define NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_SHIFT (0U) #define NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_SHIFT)) & NETC_ENETC_PSIPMAR0_PRIM_MAC_ADDR_MASK) /*! @} */ /* The count of NETC_ENETC_PSIPMAR0 */ #define NETC_ENETC_PSIPMAR0_COUNT (3U) /*! @name PSIPMAR1 - Port station interface 0 primary MAC address register 1..Port station interface 2 primary MAC address register 1 */ /*! @{ */ #define NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) #define NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_SHIFT (0U) #define NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_SHIFT)) & NETC_ENETC_PSIPMAR1_PRIM_MAC_ADDR_MASK) /*! @} */ /* The count of NETC_ENETC_PSIPMAR1 */ #define NETC_ENETC_PSIPMAR1_COUNT (3U) /*! @name PSIVLANR - Port station interface 0 VLAN register..Port station interface 2 VLAN register */ /*! @{ */ #define NETC_ENETC_PSIVLANR_VID_MASK (0xFFFU) #define NETC_ENETC_PSIVLANR_VID_SHIFT (0U) #define NETC_ENETC_PSIVLANR_VID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_VID_SHIFT)) & NETC_ENETC_PSIVLANR_VID_MASK) #define NETC_ENETC_PSIVLANR_DEI_MASK (0x1000U) #define NETC_ENETC_PSIVLANR_DEI_SHIFT (12U) #define NETC_ENETC_PSIVLANR_DEI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_DEI_SHIFT)) & NETC_ENETC_PSIVLANR_DEI_MASK) #define NETC_ENETC_PSIVLANR_PCP_MASK (0xE000U) #define NETC_ENETC_PSIVLANR_PCP_SHIFT (13U) #define NETC_ENETC_PSIVLANR_PCP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_PCP_SHIFT)) & NETC_ENETC_PSIVLANR_PCP_MASK) #define NETC_ENETC_PSIVLANR_TPID_MASK (0x30000U) #define NETC_ENETC_PSIVLANR_TPID_SHIFT (16U) #define NETC_ENETC_PSIVLANR_TPID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_TPID_SHIFT)) & NETC_ENETC_PSIVLANR_TPID_MASK) #define NETC_ENETC_PSIVLANR_TXTAGR_MASK (0xF00000U) #define NETC_ENETC_PSIVLANR_TXTAGR_SHIFT (20U) #define NETC_ENETC_PSIVLANR_TXTAGR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_TXTAGR_SHIFT)) & NETC_ENETC_PSIVLANR_TXTAGR_MASK) #define NETC_ENETC_PSIVLANR_VTEA_MASK (0x40000000U) #define NETC_ENETC_PSIVLANR_VTEA_SHIFT (30U) /*! VTEA - VLAN tag extract action * 0b0..SI-based VLAN header is removed from received frames. * 0b1..The VID in the SI-based VLAN header is zeroed. The SI-based VLAN header becomes a priority tag. */ #define NETC_ENETC_PSIVLANR_VTEA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_VTEA_SHIFT)) & NETC_ENETC_PSIVLANR_VTEA_MASK) #define NETC_ENETC_PSIVLANR_E_MASK (0x80000000U) #define NETC_ENETC_PSIVLANR_E_SHIFT (31U) /*! E - Enable * 0b0..Disabled * 0b1..Enabled */ #define NETC_ENETC_PSIVLANR_E(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANR_E_SHIFT)) & NETC_ENETC_PSIVLANR_E_MASK) /*! @} */ /* The count of NETC_ENETC_PSIVLANR */ #define NETC_ENETC_PSIVLANR_COUNT (3U) /*! @name PSICFGR0 - Port station interface 0 configuration register 0..Port station interface 2 configuration register 0 */ /*! @{ */ #define NETC_ENETC_PSICFGR0_NUM_TX_BDR_MASK (0x7FU) #define NETC_ENETC_PSICFGR0_NUM_TX_BDR_SHIFT (0U) #define NETC_ENETC_PSICFGR0_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_NUM_TX_BDR_SHIFT)) & NETC_ENETC_PSICFGR0_NUM_TX_BDR_MASK) #define NETC_ENETC_PSICFGR0_VTIA_MASK (0x400U) #define NETC_ENETC_PSICFGR0_VTIA_SHIFT (10U) #define NETC_ENETC_PSICFGR0_VTIA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_VTIA_SHIFT)) & NETC_ENETC_PSICFGR0_VTIA_MASK) #define NETC_ENETC_PSICFGR0_SPE_MASK (0x800U) #define NETC_ENETC_PSICFGR0_SPE_SHIFT (11U) #define NETC_ENETC_PSICFGR0_SPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SPE_SHIFT)) & NETC_ENETC_PSICFGR0_SPE_MASK) #define NETC_ENETC_PSICFGR0_VTE_MASK (0x1000U) #define NETC_ENETC_PSICFGR0_VTE_SHIFT (12U) #define NETC_ENETC_PSICFGR0_VTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_VTE_SHIFT)) & NETC_ENETC_PSICFGR0_VTE_MASK) #define NETC_ENETC_PSICFGR0_VASE_MASK (0x2000U) #define NETC_ENETC_PSICFGR0_VASE_SHIFT (13U) #define NETC_ENETC_PSICFGR0_VASE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_VASE_SHIFT)) & NETC_ENETC_PSICFGR0_VASE_MASK) #define NETC_ENETC_PSICFGR0_SIVIE_MASK (0x4000U) #define NETC_ENETC_PSICFGR0_SIVIE_SHIFT (14U) #define NETC_ENETC_PSICFGR0_SIVIE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SIVIE_SHIFT)) & NETC_ENETC_PSICFGR0_SIVIE_MASK) #define NETC_ENETC_PSICFGR0_ASE_MASK (0x8000U) #define NETC_ENETC_PSICFGR0_ASE_SHIFT (15U) #define NETC_ENETC_PSICFGR0_ASE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_ASE_SHIFT)) & NETC_ENETC_PSICFGR0_ASE_MASK) #define NETC_ENETC_PSICFGR0_NUM_RX_BDR_MASK (0x7F0000U) #define NETC_ENETC_PSICFGR0_NUM_RX_BDR_SHIFT (16U) #define NETC_ENETC_PSICFGR0_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_NUM_RX_BDR_SHIFT)) & NETC_ENETC_PSICFGR0_NUM_RX_BDR_MASK) #define NETC_ENETC_PSICFGR0_SIVC_MASK (0xF000000U) #define NETC_ENETC_PSICFGR0_SIVC_SHIFT (24U) #define NETC_ENETC_PSICFGR0_SIVC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SIVC_SHIFT)) & NETC_ENETC_PSICFGR0_SIVC_MASK) #define NETC_ENETC_PSICFGR0_SIBW_MASK (0xF0000000U) #define NETC_ENETC_PSICFGR0_SIBW_SHIFT (28U) #define NETC_ENETC_PSICFGR0_SIBW(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR0_SIBW_SHIFT)) & NETC_ENETC_PSICFGR0_SIBW_MASK) /*! @} */ /* The count of NETC_ENETC_PSICFGR0 */ #define NETC_ENETC_PSICFGR0_COUNT (3U) /*! @name PSICFGR1 - Port station interface 1 configuration register 1..Port station interface 2 configuration register 1 */ /*! @{ */ #define NETC_ENETC_PSICFGR1_TC0_MAP_MASK (0x7U) #define NETC_ENETC_PSICFGR1_TC0_MAP_SHIFT (0U) #define NETC_ENETC_PSICFGR1_TC0_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC0_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC0_MAP_MASK) #define NETC_ENETC_PSICFGR1_TC1_MAP_MASK (0x70U) #define NETC_ENETC_PSICFGR1_TC1_MAP_SHIFT (4U) #define NETC_ENETC_PSICFGR1_TC1_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC1_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC1_MAP_MASK) #define NETC_ENETC_PSICFGR1_TC2_MAP_MASK (0x700U) #define NETC_ENETC_PSICFGR1_TC2_MAP_SHIFT (8U) #define NETC_ENETC_PSICFGR1_TC2_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC2_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC2_MAP_MASK) #define NETC_ENETC_PSICFGR1_TC3_MAP_MASK (0x7000U) #define NETC_ENETC_PSICFGR1_TC3_MAP_SHIFT (12U) #define NETC_ENETC_PSICFGR1_TC3_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC3_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC3_MAP_MASK) #define NETC_ENETC_PSICFGR1_TC4_MAP_MASK (0x70000U) #define NETC_ENETC_PSICFGR1_TC4_MAP_SHIFT (16U) #define NETC_ENETC_PSICFGR1_TC4_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC4_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC4_MAP_MASK) #define NETC_ENETC_PSICFGR1_TC5_MAP_MASK (0x700000U) #define NETC_ENETC_PSICFGR1_TC5_MAP_SHIFT (20U) #define NETC_ENETC_PSICFGR1_TC5_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC5_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC5_MAP_MASK) #define NETC_ENETC_PSICFGR1_TC6_MAP_MASK (0x7000000U) #define NETC_ENETC_PSICFGR1_TC6_MAP_SHIFT (24U) #define NETC_ENETC_PSICFGR1_TC6_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC6_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC6_MAP_MASK) #define NETC_ENETC_PSICFGR1_TC7_MAP_MASK (0x70000000U) #define NETC_ENETC_PSICFGR1_TC7_MAP_SHIFT (28U) #define NETC_ENETC_PSICFGR1_TC7_MAP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR1_TC7_MAP_SHIFT)) & NETC_ENETC_PSICFGR1_TC7_MAP_MASK) /*! @} */ /* The count of NETC_ENETC_PSICFGR1 */ #define NETC_ENETC_PSICFGR1_COUNT (3U) /*! @name PSICFGR2 - Port station interface 0 configuration register 2..Port station interface 2 configuration register 2 */ /*! @{ */ #define NETC_ENETC_PSICFGR2_NUM_MSIX_MASK (0x3FU) #define NETC_ENETC_PSICFGR2_NUM_MSIX_SHIFT (0U) /*! NUM_MSIX - Number of MSI-X */ #define NETC_ENETC_PSICFGR2_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSICFGR2_NUM_MSIX_SHIFT)) & NETC_ENETC_PSICFGR2_NUM_MSIX_MASK) /*! @} */ /* The count of NETC_ENETC_PSICFGR2 */ #define NETC_ENETC_PSICFGR2_COUNT (3U) /*! @name PSIVMAFCFGR - Port station interface 0 VSI MAC address filtering configuration register..Port station interface 2 VSI MAC address filtering configuration register */ /*! @{ */ #define NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_MASK (0xFFU) #define NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_SHIFT (0U) #define NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_SHIFT)) & NETC_ENETC_PSIVMAFCFGR_NUM_MAC_AFTE_MASK) /*! @} */ /* The count of NETC_ENETC_PSIVMAFCFGR */ #define NETC_ENETC_PSIVMAFCFGR_COUNT (3U) /*! @name PSIVLANFCFGR - Port station interface 0 VLAN filtering configuration register..Port station interface 2 VLAN filtering configuration register */ /*! @{ */ #define NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_MASK (0xFFU) #define NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_SHIFT (0U) #define NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_SHIFT)) & NETC_ENETC_PSIVLANFCFGR_NUM_VLAN_FTE_MASK) /*! @} */ /* The count of NETC_ENETC_PSIVLANFCFGR */ #define NETC_ENETC_PSIVLANFCFGR_COUNT (3U) /*! @name PSIUMHFR0 - Port station interface 0 unicast MAC hash filter register 0..Port station interface 2 unicast MAC hash filter register 0 */ /*! @{ */ #define NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_MASK (0xFFFFFFFFU) #define NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_SHIFT (0U) #define NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_SHIFT)) & NETC_ENETC_PSIUMHFR0_MAC_HASH_FLT_LOW_MASK) /*! @} */ /* The count of NETC_ENETC_PSIUMHFR0 */ #define NETC_ENETC_PSIUMHFR0_COUNT (3U) /*! @name PSIUMHFR1 - Port station interface 0 unicast MAC hash filter register 1..Port station interface 2 unicast MAC hash filter register 1 */ /*! @{ */ #define NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_MASK (0xFFFFFFFFU) #define NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_SHIFT (0U) #define NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_SHIFT)) & NETC_ENETC_PSIUMHFR1_MAC_HASH_FLT_HIGH_MASK) /*! @} */ /* The count of NETC_ENETC_PSIUMHFR1 */ #define NETC_ENETC_PSIUMHFR1_COUNT (3U) /*! @name PSIMMHFR0 - Port station interface 0 multicast MAC hash filter register 0..Port station interface 2 multicast MAC hash filter register 0 */ /*! @{ */ #define NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_MASK (0xFFFFFFFFU) #define NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_SHIFT (0U) #define NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_SHIFT)) & NETC_ENETC_PSIMMHFR0_MAC_HASH_FLT_LOW_MASK) /*! @} */ /* The count of NETC_ENETC_PSIMMHFR0 */ #define NETC_ENETC_PSIMMHFR0_COUNT (3U) /*! @name PSIMMHFR1 - Port station interface 0 multicast MAC hash filter register 1..Port station interface 2 multicast MAC hash filter register 1 */ /*! @{ */ #define NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_MASK (0xFFFFFFFFU) #define NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_SHIFT (0U) #define NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_SHIFT)) & NETC_ENETC_PSIMMHFR1_MAC_HASH_FLT_HIGH_MASK) /*! @} */ /* The count of NETC_ENETC_PSIMMHFR1 */ #define NETC_ENETC_PSIMMHFR1_COUNT (3U) /*! @name PSIVHFR0 - Port station interface 0 VLAN hash filter register 0..Port station interface 2 VLAN hash filter register 0 */ /*! @{ */ #define NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_MASK (0xFFFFFFFFU) #define NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_SHIFT (0U) #define NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_SHIFT)) & NETC_ENETC_PSIVHFR0_VLAN_HASH_FLT_LOW_MASK) /*! @} */ /* The count of NETC_ENETC_PSIVHFR0 */ #define NETC_ENETC_PSIVHFR0_COUNT (3U) /*! @name PSIVHFR1 - Port station interface 0 VLAN hash filter register 1..Port station interface 2 VLAN hash filter register 1 */ /*! @{ */ #define NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_MASK (0xFFFFFFFFU) #define NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_SHIFT (0U) #define NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_SHIFT)) & NETC_ENETC_PSIVHFR1_VLAN_HASH_FLT_HIGH_MASK) /*! @} */ /* The count of NETC_ENETC_PSIVHFR1 */ #define NETC_ENETC_PSIVHFR1_COUNT (3U) /*! * @} */ /* end of group NETC_ENETC_Register_Masks */ /* NETC_ENETC - Peripheral instance base addresses */ /** Peripheral ENETC0_BASE base address */ #define ENETC0_BASE_BASE (0x4CC10000u) /** Peripheral ENETC0_BASE base pointer */ #define ENETC0_BASE ((NETC_ENETC_Type *)ENETC0_BASE_BASE) /** Peripheral ENETC1_BASE base address */ #define ENETC1_BASE_BASE (0x4CC50000u) /** Peripheral ENETC1_BASE base pointer */ #define ENETC1_BASE ((NETC_ENETC_Type *)ENETC1_BASE_BASE) /** Peripheral ENETC2_BASE base address */ #define ENETC2_BASE_BASE (0x4CC90000u) /** Peripheral ENETC2_BASE base pointer */ #define ENETC2_BASE ((NETC_ENETC_Type *)ENETC2_BASE_BASE) /** Array initializer of NETC_ENETC peripheral base addresses */ #define NETC_ENETC_BASE_ADDRS { ENETC0_BASE_BASE, ENETC1_BASE_BASE, ENETC2_BASE_BASE } /** Array initializer of NETC_ENETC peripheral base pointers */ #define NETC_ENETC_BASE_PTRS { ENETC0_BASE, ENETC1_BASE, ENETC2_BASE } /*! * @} */ /* end of group NETC_ENETC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NETC_ETH_LINK Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_ETH_LINK_Peripheral_Access_Layer NETC_ETH_LINK Peripheral Access Layer * @{ */ /** NETC_ETH_LINK - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __IO uint32_t PM0_COMMAND_CONFIG; /**< Port MAC 0 Command and Configuration Register, offset: 0x8 */ __I uint32_t PM0_MAC_ADDR_0; /**< Port MAC 0 MAC Address Register 0, offset: 0xC */ __I uint32_t PM0_MAC_ADDR_1; /**< Port MAC 0 MAC Address Register 1, offset: 0x10 */ __IO uint32_t PM0_MAXFRM; /**< Port MAC 0 Maximum Frame Length Register, offset: 0x14 */ uint8_t RESERVED_1[24]; __IO uint32_t PM0_MDIO_CFG; /**< Port MAC 0 Internal MDIO Configuration Register, offset: 0x30, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM0_MDIO_CTL; /**< Port MAC 0 Internal MDIO Interface Control Register, offset: 0x34, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM0_MDIO_DATA; /**< Port MAC 0 Internal MDIO Interface Data Register, offset: 0x38, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM0_MDIO_ADDR; /**< Port MAC 0 Internal MDIO Register Address Register, offset: 0x3C, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM0_IEVENT; /**< Port MAC 0 Interrupt Event Register, offset: 0x40 */ uint8_t RESERVED_2[8]; __IO uint32_t PM0_IMASK; /**< Port MAC 0 Interrupt Mask Register(INT_MASK), offset: 0x4C */ uint8_t RESERVED_3[4]; __IO uint32_t PM0_PAUSE_QUANTA; /**< Port MAC 0 Pause Quanta Register, offset: 0x54 */ uint8_t RESERVED_4[12]; __IO uint32_t PM0_PAUSE_THRESH; /**< Port MAC 0 Pause Quanta Threshold Register, offset: 0x64 */ uint8_t RESERVED_5[12]; __I uint32_t PM0_RX_PAUSE_STATUS; /**< Port MAC 0 Receive Pause Status Register, offset: 0x74 */ uint8_t RESERVED_6[64]; __IO uint32_t PM0_LPWAKE_TIMER; /**< Port MAC 0 EEE Low Power Wakeup Timer Register, offset: 0xB8 */ __IO uint32_t PM0_SLEEP_TIMER; /**< Port MAC 0 Transmit EEE Low Power Timer Register, offset: 0xBC */ __IO uint32_t PM0_SINGLE_STEP; /**< Port MAC 0 IEEE1588 Single-Step Control Register, offset: 0xC0 */ uint8_t RESERVED_7[12]; __IO uint32_t PM0_HD_BACKOFF_ENTROPY; /**< Port MAC 0 half-duplex backoff entropy register, offset: 0xD0 */ __IO uint32_t PM0_HD_FLOW_CTRL; /**< Port MAC 0 Half-Duplex Flow Control Register, offset: 0xD4 */ uint8_t RESERVED_8[8]; __IO uint32_t PM0_STATN_CONFIG; /**< Port MAC 0 Statistics Configuration Register, offset: 0xE0 */ uint8_t RESERVED_9[28]; __I uint64_t PM0_REOCTN; /**< Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x100 */ __I uint64_t PM0_ROCTN; /**< Port MAC 0 Receive Octets Counter(iflnOctetsn), offset: 0x108 */ uint8_t RESERVED_10[8]; __I uint64_t PM0_RXPFN; /**< Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x118 */ __I uint64_t PM0_RFRMN; /**< Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x120 */ __I uint64_t PM0_RFCSN; /**< Port MAC 0 Receive Frame Check Sequence Error Counter Register(), offset: 0x128 */ __I uint64_t PM0_RVLANN; /**< Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x130 */ __I uint64_t PM0_RERRN; /**< Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x138 */ __I uint64_t PM0_RUCAN; /**< Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x140 */ __I uint64_t PM0_RMCAN; /**< Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x148 */ __I uint64_t PM0_RBCAN; /**< Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x150 */ __I uint64_t PM0_RDRPN; /**< Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x158 */ __I uint64_t PM0_RPKTN; /**< Port MAC 0 Receive Packets Counter Register(etherStatsPktsn), offset: 0x160 */ __I uint64_t PM0_RUNDN; /**< Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x168 */ __I uint64_t PM0_R64N; /**< Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x170 */ __I uint64_t PM0_R127N; /**< Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x178 */ __I uint64_t PM0_R255N; /**< Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x180 */ __I uint64_t PM0_R511N; /**< Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x188 */ __I uint64_t PM0_R1023N; /**< Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x190 */ __I uint64_t PM0_R1522N; /**< Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x198 */ __I uint64_t PM0_R1523XN; /**< Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x1A0 */ __I uint64_t PM0_ROVRN; /**< Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x1A8 */ __I uint64_t PM0_RJBRN; /**< Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x1B0 */ __I uint64_t PM0_RFRGN; /**< Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x1B8 */ __I uint64_t PM0_RCNPN; /**< Port MAC 0 Receive Control Packet Counter Register, offset: 0x1C0 */ __I uint64_t PM0_RDRNTPN; /**< Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x1C8 */ uint8_t RESERVED_11[48]; __I uint64_t PM0_TEOCTN; /**< Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x200 */ __I uint64_t PM0_TOCTN; /**< Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x208 */ uint8_t RESERVED_12[8]; __I uint64_t PM0_TXPFN; /**< Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x218 */ __I uint64_t PM0_TFRMN; /**< Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x220 */ __I uint64_t PM0_TFCSN; /**< Port MAC 0 Transmit Frame Check Sequence Error Counter Register(), offset: 0x228 */ __I uint64_t PM0_TVLANN; /**< Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x230 */ __I uint64_t PM0_TERRN; /**< Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x238 */ __I uint64_t PM0_TUCAN; /**< Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x240 */ __I uint64_t PM0_TMCAN; /**< Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x248 */ __I uint64_t PM0_TBCAN; /**< Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x250 */ uint8_t RESERVED_13[8]; __I uint64_t PM0_TPKTN; /**< Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x260 */ __I uint64_t PM0_TUNDN; /**< Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x268 */ __I uint64_t PM0_T64N; /**< Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x270 */ __I uint64_t PM0_T127N; /**< Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x278 */ __I uint64_t PM0_T255N; /**< Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x280 */ __I uint64_t PM0_T511N; /**< Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x288 */ __I uint64_t PM0_T1023N; /**< Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x290 */ __I uint64_t PM0_T1522N; /**< Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x298 */ __I uint64_t PM0_T1523XN; /**< Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x2A0 */ uint8_t RESERVED_14[24]; __I uint64_t PM0_TCNPN; /**< Port MAC 0 Transmit Control Packet Counter Register, offset: 0x2C0 */ uint8_t RESERVED_15[8]; __I uint64_t PM0_TDFRN; /**< Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x2D0, not available in all instances (available on 12 out of 18) */ __I uint64_t PM0_TMCOLN; /**< Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x2D8, not available in all instances (available on 12 out of 18) */ __I uint64_t PM0_TSCOLN; /**< Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x2E0, not available in all instances (available on 12 out of 18) */ __I uint64_t PM0_TLCOLN; /**< Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x2E8, not available in all instances (available on 12 out of 18) */ __I uint64_t PM0_TECOLN; /**< Port MAC 0 Transmit Excessive Collisions Counter Register, offset: 0x2F0, not available in all instances (available on 12 out of 18) */ uint8_t RESERVED_16[8]; __IO uint32_t PM0_IF_MODE; /**< Port MAC 0 Interface Mode Control Register, offset: 0x300 */ __I uint32_t PM0_IF_STATUS; /**< Port MAC 0 Interface Status Register, offset: 0x304 */ uint8_t RESERVED_17[256]; __IO uint32_t PM1_COMMAND_CONFIG; /**< Port MAC 1 Command and Configuration Register, offset: 0x408, not available in all instances (available on 6 out of 18) */ __I uint32_t PM1_MAC_ADDR_0; /**< Port MAC 1 MAC Address Register 0, offset: 0x40C, not available in all instances (available on 6 out of 18) */ __I uint32_t PM1_MAC_ADDR_1; /**< Port MAC 1 MAC Address Register 1, offset: 0x410, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM1_MAXFRM; /**< Port MAC 1 Maximum Frame Length Register, offset: 0x414, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_18[40]; __IO uint32_t PM1_IEVENT; /**< Port MAC 1 Interrupt Event Register, offset: 0x440, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_19[8]; __IO uint32_t PM1_IMASK; /**< Port MAC 1 Interrupt Mask Register(INT_MASK), offset: 0x44C, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_20[4]; __IO uint32_t PM1_PAUSE_QUANTA; /**< Port MAC 1 Pause Quanta Register, offset: 0x454, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_21[12]; __IO uint32_t PM1_PAUSE_THRESH; /**< Port MAC 1 Pause Quanta Threshold Register, offset: 0x464, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_22[12]; __I uint32_t PM1_RX_PAUSE_STATUS; /**< Port MAC 1 Receive Pause Status Register, offset: 0x474, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_23[64]; __IO uint32_t PM1_LPWAKE_TIMER; /**< Port MAC 1 EEE Low Power Wakeup Timer Register, offset: 0x4B8, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM1_SLEEP_TIMER; /**< Port MAC 1 Transmit EEE Low Power Timer Register, offset: 0x4BC, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM1_SINGLE_STEP; /**< Port MAC 1 IEEE1588 Single-Step Control Register, offset: 0x4C0, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_24[12]; __IO uint32_t PM1_HD_BACKOFF_ENTROPY; /**< Port MAC 1 half-duplex backoff entropy register, offset: 0x4D0, not available in all instances (available on 6 out of 18) */ __IO uint32_t PM1_HD_FLOW_CTRL; /**< Port MAC 1 Half-Duplex Flow Control Register, offset: 0x4D4, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_25[8]; __IO uint32_t PM1_STATN_CONFIG; /**< Port MAC 1 Statistics Configuration Register, offset: 0x4E0, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_26[28]; __I uint64_t PM1_REOCTN; /**< Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn), offset: 0x500, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_ROCTN; /**< Port MAC 1 Receive Octets Counter(iflnOctetsn), offset: 0x508, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_27[8]; __I uint64_t PM1_RXPFN; /**< Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x518, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RFRMN; /**< Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn), offset: 0x520, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RFCSN; /**< Port MAC 1 Receive Frame Check Sequence Error Counter Register(), offset: 0x528, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RVLANN; /**< Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn), offset: 0x530, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RERRN; /**< Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn), offset: 0x538, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RUCAN; /**< Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn), offset: 0x540, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RMCAN; /**< Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn), offset: 0x548, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RBCAN; /**< Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn), offset: 0x550, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RDRPN; /**< Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn), offset: 0x558, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RPKTN; /**< Port MAC 1 Receive Packets Counter Register(etherStatsPktsn), offset: 0x560, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RUNDN; /**< Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x568, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_R64N; /**< Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN), offset: 0x570, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_R127N; /**< Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN), offset: 0x578, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_R255N; /**< Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN), offset: 0x580, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_R511N; /**< Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN), offset: 0x588, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_R1023N; /**< Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN), offset: 0x590, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_R1522N; /**< Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN), offset: 0x598, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_R1523XN; /**< Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN), offset: 0x5A0, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_ROVRN; /**< Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn), offset: 0x5A8, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RJBRN; /**< Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn), offset: 0x5B0, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RFRGN; /**< Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn, offset: 0x5B8, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RCNPN; /**< Port MAC 1 Receive Control Packet Counter Register, offset: 0x5C0, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_RDRNTPN; /**< Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn), offset: 0x5C8, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_28[48]; __I uint64_t PM1_TEOCTN; /**< Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn), offset: 0x600, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TOCTN; /**< Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn), offset: 0x608, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_29[8]; __I uint64_t PM1_TXPFN; /**< Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn), offset: 0x618, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TFRMN; /**< Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn), offset: 0x620, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TFCSN; /**< Port MAC 1 Transmit Frame Check Sequence Error Counter Register(), offset: 0x628, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TVLANN; /**< Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn), offset: 0x630, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TERRN; /**< Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn), offset: 0x638, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TUCAN; /**< Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn), offset: 0x640, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TMCAN; /**< Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn), offset: 0x648, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TBCAN; /**< Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn), offset: 0x650, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_30[8]; __I uint64_t PM1_TPKTN; /**< Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn), offset: 0x660, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TUNDN; /**< Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn), offset: 0x668, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_T64N; /**< Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN), offset: 0x670, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_T127N; /**< Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN), offset: 0x678, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_T255N; /**< Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN), offset: 0x680, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_T511N; /**< Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN), offset: 0x688, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_T1023N; /**< Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN), offset: 0x690, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_T1522N; /**< Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN), offset: 0x698, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_T1523XN; /**< Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN), offset: 0x6A0, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_31[24]; __I uint64_t PM1_TCNPN; /**< Port MAC 1 Transmit Control Packet Counter Register, offset: 0x6C0, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_32[8]; __I uint64_t PM1_TDFRN; /**< Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions), offset: 0x6D0, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TMCOLN; /**< Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames), offset: 0x6D8, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TSCOLN; /**< Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register, offset: 0x6E0, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TLCOLN; /**< Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register, offset: 0x6E8, not available in all instances (available on 6 out of 18) */ __I uint64_t PM1_TECOLN; /**< Port MAC 1 Transmit Excessive Collisions Counter Register, offset: 0x6F0, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_33[8]; __IO uint32_t PM1_IF_MODE; /**< Port MAC 1 Interface Mode Control Register, offset: 0x700, not available in all instances (available on 6 out of 18) */ __I uint32_t PM1_IF_STATUS; /**< Port MAC 1 Interface Status Register, offset: 0x704, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_34[248]; __IO uint32_t MAC_MERGE_MMCSR; /**< Port MAC Merge Control and Status Register, offset: 0x800, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_35[4]; __IO uint32_t MAC_MERGE_MMFAECR; /**< Port MAC Merge Frame Assembly Error Count Register, offset: 0x808, not available in all instances (available on 6 out of 18) */ __IO uint32_t MAC_MERGE_MMFSECR; /**< Port MAC Merge Frame SMD Error Count Register, offset: 0x80C, not available in all instances (available on 6 out of 18) */ __IO uint32_t MAC_MERGE_MMFAOCR; /**< Port MAC Merge Frame Assembly OK Count Register, offset: 0x810, not available in all instances (available on 6 out of 18) */ __IO uint32_t MAC_MERGE_MMFCRXR; /**< Port MAC Merge Fragment Count RX Register, offset: 0x814, not available in all instances (available on 6 out of 18) */ __IO uint32_t MAC_MERGE_MMFCTXR; /**< Port MAC Merge Fragment Count TX Register, offset: 0x818, not available in all instances (available on 6 out of 18) */ __IO uint32_t MAC_MERGE_MMHCR; /**< Port MAC Merge Hold Count Register, offset: 0x81C, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_36[992]; __IO uint32_t PEMDIOCR; /**< Port external MDIO configuration register, offset: 0xC00 */ __IO uint32_t PEMDIOICR; /**< Port external MDIO interface control register, offset: 0xC04 */ __IO uint32_t PEMDIOIDR; /**< Port external MDIO interface data register, offset: 0xC08 */ __IO uint32_t PEMDIORAR; /**< Port external MDIO register address register, offset: 0xC0C */ __I uint32_t PEMDIOSR; /**< Port external MDIO status register, offset: 0xC10 */ uint8_t RESERVED_37[12]; __IO uint32_t PPSCR; /**< PHY status configuration register, offset: 0xC20 */ __IO uint32_t PPSCTRLR; /**< Port PHY status control register, offset: 0xC24 */ __I uint32_t PPSDR; /**< Port PHY status data register, offset: 0xC28 */ __IO uint32_t PPSRAR; /**< Port PHY status register address register, offset: 0xC2C */ __IO uint32_t PPSER; /**< Port PHY status event register, offset: 0xC30 */ __IO uint32_t PPSMR; /**< Port PHY status mask register, offset: 0xC34 */ } NETC_ETH_LINK_Type; /* ---------------------------------------------------------------------------- -- NETC_ETH_LINK Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_ETH_LINK_Register_Masks NETC_ETH_LINK Register Masks * @{ */ /*! @name PM0_COMMAND_CONFIG - Port MAC 0 Command and Configuration Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_MASK (0x1U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_SHIFT (0U) /*! TX_EN - MAC transmit path enable */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_EN_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_MASK (0x2U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_SHIFT (1U) /*! RX_EN - MAC receive path enable */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_EN_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U) /*! PAUSE_FWD - Terminate/forward received PAUSE frames */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_FWD_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U) /*! PAUSE_IGN - Ignore PAUSE frame quanta */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_PAUSE_IGN_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U) /*! LOOP_ENA - Loopback enable */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_LOOP_ENA_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_MASK (0x1800U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_SHIFT (11U) /*! LPBK_MODE - Loopback mode */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_LPBK_MODE_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U) /*! CNT_FRM_EN - Control frame reception enable */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_CNT_FRM_EN_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_MASK (0x4000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_SHIFT (14U) /*! TS_PNT - Timestamp Point */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_PNT_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_MASK (0x8000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_SHIFT (15U) /*! TXP - Enable padding of frames in transmit direction (1, default). */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TXP_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SEND_IDLE_MASK (0x10000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SEND_IDLE_SHIFT (16U) /*! SEND_IDLE - Force send idle */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SEND_IDLE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_SEND_IDLE_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_SEND_IDLE_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SFD_MASK (0x200000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SFD_SHIFT (21U) /*! SFD - Disable check of SFD (0xd5) character at frame start. */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SFD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_SFD_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_SFD_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U) /*! TX_FLUSH - Tx flush */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_FLUSH_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U) /*! TX_LOWP_ENA - Transmit Low Power Idle Enable. * 0b0..(default), the MAC operates in normal mode. * 0b1..The MAC completes the transmission of the current Frame and generates Low Power Idle Sequences to the * line. It is advised to inspect IEVENT[TX_EMPTY] is set before enabling the LPI. */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TX_LOWP_ENA_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_REG_LOWP_RXETY_MASK (0x1000000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_REG_LOWP_RXETY_SHIFT (24U) /*! REG_LOWP_RXETY - Rx low power empty indicator */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_REG_LOWP_RXETY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_REG_LOWP_RXETY_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_REG_LOWP_RXETY_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_MASK (0x4000000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_SHIFT (26U) /*! SWR - Software Reset. Self clearing bit. */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_SWR_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_MASK (0x10000000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_SHIFT (28U) /*! RX_FLUSH - Ingress flush enable */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_RX_FLUSH_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_SHIFT (30U) /*! TS_MODE - Transmit timestamp mode */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_TS_MODE_MASK) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_MASK (0x80000000U) #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_SHIFT (31U) /*! MG - Magic Packet detection enable. */ #define NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_SHIFT)) & NETC_ETH_LINK_PM0_COMMAND_CONFIG_MG_MASK) /*! @} */ /*! @name PM0_MAC_ADDR_0 - Port MAC 0 MAC Address Register 0 */ /*! @{ */ #define NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U) /*! MAC_ADDR_0 - MAC address 0 */ #define NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & NETC_ETH_LINK_PM0_MAC_ADDR_0_MAC_ADDR_0_MASK) /*! @} */ /*! @name PM0_MAC_ADDR_1 - Port MAC 0 MAC Address Register 1 */ /*! @{ */ #define NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU) #define NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U) /*! MAC_ADDR_1 - MAC address 1 */ #define NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & NETC_ETH_LINK_PM0_MAC_ADDR_1_MAC_ADDR_1_MASK) /*! @} */ /*! @name PM0_MAXFRM - Port MAC 0 Maximum Frame Length Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_MASK (0xFFFFU) #define NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_SHIFT (0U) /*! MAXFRM - Maximum supported received frame length. */ #define NETC_ETH_LINK_PM0_MAXFRM_MAXFRM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_SHIFT)) & NETC_ETH_LINK_PM0_MAXFRM_MAXFRM_MASK) #define NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_MASK (0xFFFF0000U) #define NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_SHIFT (16U) /*! TX_MTU - Maximum transmit frame length */ #define NETC_ETH_LINK_PM0_MAXFRM_TX_MTU(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_SHIFT)) & NETC_ETH_LINK_PM0_MAXFRM_TX_MTU_MASK) /*! @} */ /*! @name PM0_MDIO_CFG - Port MAC 0 Internal MDIO Configuration Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_MASK (0x1U) #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_SHIFT (0U) /*! BSY2 - MDIO busy (same as bit 31) */ #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY2(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_BSY2_MASK) #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_MASK (0x1CU) #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_SHIFT (2U) /*! MDIO_HOLD - MDIO hold time */ #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_HOLD_MASK) #define NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_MASK (0x20U) #define NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_SHIFT (5U) /*! PRE_DIS - MDIO preamble disable. */ #define NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_PRE_DIS_MASK) #define NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_MASK (0x40U) #define NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_SHIFT (6U) /*! ENC45 - Enable Clause 45 support. */ #define NETC_ETH_LINK_PM0_MDIO_CFG_ENC45(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_MASK) #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_MASK (0xFF80U) #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_SHIFT (7U) /*! MDIO_CLK_DIV - MDIO clock divisor. */ #define NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_MDIO_CLK_DIV_MASK) #define NETC_ETH_LINK_PM0_MDIO_CFG_CIM_MASK (0x20000000U) #define NETC_ETH_LINK_PM0_MDIO_CFG_CIM_SHIFT (29U) /*! CIM - MDIO command completion interrupt mask. */ #define NETC_ETH_LINK_PM0_MDIO_CFG_CIM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_CIM_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_CIM_MASK) #define NETC_ETH_LINK_PM0_MDIO_CFG_CMP_MASK (0x40000000U) #define NETC_ETH_LINK_PM0_MDIO_CFG_CMP_SHIFT (30U) /*! CMP - MDIO command completion event. Bit is cleared by writing `1'. */ #define NETC_ETH_LINK_PM0_MDIO_CFG_CMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_CMP_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_CMP_MASK) #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_MASK (0x80000000U) #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_SHIFT (31U) /*! BSY1 - MDIO busy */ #define NETC_ETH_LINK_PM0_MDIO_CFG_BSY1(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CFG_BSY1_MASK) /*! @} */ /*! @name PM0_MDIO_CTL - Port MAC 0 Internal MDIO Interface Control Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_MASK (0x1FU) #define NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_SHIFT (0U) /*! DEV_ADDR - MDIO device address (Clause 45) / register address (Clause 22) */ #define NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR_MASK) #define NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_MASK (0x3E0U) #define NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_SHIFT (5U) /*! PORT_ADDR - MDIO port address (Clause 45) / PHY address (Clause 22) */ #define NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR_MASK) #define NETC_ETH_LINK_PM0_MDIO_CTL_READ_MASK (0x8000U) #define NETC_ETH_LINK_PM0_MDIO_CTL_READ_SHIFT (15U) /*! READ - MDIO read initiation. */ #define NETC_ETH_LINK_PM0_MDIO_CTL_READ(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_READ_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_READ_MASK) #define NETC_ETH_LINK_PM0_MDIO_CTL_BSY_MASK (0x80000000U) #define NETC_ETH_LINK_PM0_MDIO_CTL_BSY_SHIFT (31U) /*! BSY - MDIO busy */ #define NETC_ETH_LINK_PM0_MDIO_CTL_BSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_CTL_BSY_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_CTL_BSY_MASK) /*! @} */ /*! @name PM0_MDIO_DATA - Port MAC 0 Internal MDIO Interface Data Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_MASK (0xFFFFU) #define NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_SHIFT (0U) /*! MDIO_DATA - 16-bit MDIO data. */ #define NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_DATA_MDIO_DATA_MASK) #define NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_MASK (0x80000000U) #define NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_SHIFT (31U) /*! BUSY - MDIO busy bit. The state of this bit is also reflected in MDIO_CFG[BSY]. */ #define NETC_ETH_LINK_PM0_MDIO_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_DATA_BUSY_MASK) /*! @} */ /*! @name PM0_MDIO_ADDR - Port MAC 0 Internal MDIO Register Address Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_MDIO_ADDR_REGADDR_MASK (0xFFFFU) #define NETC_ETH_LINK_PM0_MDIO_ADDR_REGADDR_SHIFT (0U) /*! REGADDR - MDIO PHY register address. */ #define NETC_ETH_LINK_PM0_MDIO_ADDR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_MDIO_ADDR_REGADDR_SHIFT)) & NETC_ETH_LINK_PM0_MDIO_ADDR_REGADDR_MASK) /*! @} */ /*! @name PM0_IEVENT - Port MAC 0 Interrupt Event Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_IEVENT_LOC_FAULT_MASK (0x1U) #define NETC_ETH_LINK_PM0_IEVENT_LOC_FAULT_SHIFT (0U) /*! LOC_FAULT - Local fault event (XGMII) */ #define NETC_ETH_LINK_PM0_IEVENT_LOC_FAULT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_LOC_FAULT_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_LOC_FAULT_MASK) #define NETC_ETH_LINK_PM0_IEVENT_REM_FAULT_MASK (0x2U) #define NETC_ETH_LINK_PM0_IEVENT_REM_FAULT_SHIFT (1U) /*! REM_FAULT - Remote fault event (XGMII) */ #define NETC_ETH_LINK_PM0_IEVENT_REM_FAULT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_REM_FAULT_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_REM_FAULT_MASK) #define NETC_ETH_LINK_PM0_IEVENT_RX_LOWP_MASK (0x10U) #define NETC_ETH_LINK_PM0_IEVENT_RX_LOWP_SHIFT (4U) /*! RX_LOWP - Low Power Idle event */ #define NETC_ETH_LINK_PM0_IEVENT_RX_LOWP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_RX_LOWP_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_RX_LOWP_MASK) #define NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_MASK (0x20U) #define NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_SHIFT (5U) /*! TX_EMPTY - Transmit FIFO empty event */ #define NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_MASK) #define NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_MASK (0x40U) #define NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_SHIFT (6U) /*! RX_EMPTY - Receive idle event */ #define NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_MASK) #define NETC_ETH_LINK_PM0_IEVENT_LI_FAULT_MASK (0x80U) #define NETC_ETH_LINK_PM0_IEVENT_LI_FAULT_SHIFT (7U) /*! LI_FAULT - Link Interruption fault event (XGMII) */ #define NETC_ETH_LINK_PM0_IEVENT_LI_FAULT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_LI_FAULT_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_LI_FAULT_MASK) #define NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_MASK (0x400U) #define NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_SHIFT (10U) /*! TX_OVFL - Transmit FIFO overflow event. */ #define NETC_ETH_LINK_PM0_IEVENT_TX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_MASK) #define NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_MASK (0x800U) #define NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_SHIFT (11U) /*! TX_UNFL - Transmit FIFO underflow event. */ #define NETC_ETH_LINK_PM0_IEVENT_TX_UNFL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_MASK) #define NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_MASK (0x1000U) #define NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_SHIFT (12U) /*! RX_OVFL - Receive FIFO overflow event. */ #define NETC_ETH_LINK_PM0_IEVENT_RX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_MASK) #define NETC_ETH_LINK_PM0_IEVENT_MGI_MASK (0x4000U) #define NETC_ETH_LINK_PM0_IEVENT_MGI_SHIFT (14U) /*! MGI - Magic packet detection indication event */ #define NETC_ETH_LINK_PM0_IEVENT_MGI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_MGI_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_MGI_MASK) #define NETC_ETH_LINK_PM0_IEVENT_TX_CSD_MASK (0x200000U) #define NETC_ETH_LINK_PM0_IEVENT_TX_CSD_SHIFT (21U) /*! TX_CSD - Tx Clock Stop Detection */ #define NETC_ETH_LINK_PM0_IEVENT_TX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_TX_CSD_MASK) #define NETC_ETH_LINK_PM0_IEVENT_RX_CSD_MASK (0x400000U) #define NETC_ETH_LINK_PM0_IEVENT_RX_CSD_SHIFT (22U) /*! RX_CSD - Rx Clock Stop Detection */ #define NETC_ETH_LINK_PM0_IEVENT_RX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_RX_CSD_MASK) #define NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_MASK (0x800000U) #define NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_SHIFT (23U) /*! SPD_DUP - Speed/Duplex Change */ #define NETC_ETH_LINK_PM0_IEVENT_SPD_DUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_MASK) #define NETC_ETH_LINK_PM0_IEVENT_LINK_UP_MASK (0x1000000U) #define NETC_ETH_LINK_PM0_IEVENT_LINK_UP_SHIFT (24U) /*! LINK_UP - Link Up */ #define NETC_ETH_LINK_PM0_IEVENT_LINK_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_LINK_UP_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_LINK_UP_MASK) #define NETC_ETH_LINK_PM0_IEVENT_LINK_DOWN_MASK (0x2000000U) #define NETC_ETH_LINK_PM0_IEVENT_LINK_DOWN_SHIFT (25U) /*! LINK_DOWN - Link Down */ #define NETC_ETH_LINK_PM0_IEVENT_LINK_DOWN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_LINK_DOWN_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_LINK_DOWN_MASK) #define NETC_ETH_LINK_PM0_IEVENT_AN_DONE_MASK (0x4000000U) #define NETC_ETH_LINK_PM0_IEVENT_AN_DONE_SHIFT (26U) /*! AN_DONE - Auto-Negotiation Done */ #define NETC_ETH_LINK_PM0_IEVENT_AN_DONE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_AN_DONE_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_AN_DONE_MASK) #define NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_MASK (0x8000000U) #define NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_SHIFT (27U) /*! MRG_SERR - MAC merge frame SMD error received event */ #define NETC_ETH_LINK_PM0_IEVENT_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_MASK) #define NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_MASK (0x10000000U) #define NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_SHIFT (28U) /*! MRG_AERR - MAC merge frame assembly error event */ #define NETC_ETH_LINK_PM0_IEVENT_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_MASK) /*! @} */ /*! @name PM0_IMASK - Port MAC 0 Interrupt Mask Register(INT_MASK) */ /*! @{ */ #define NETC_ETH_LINK_PM0_IMASK_LOC_FAULT_MASK (0x1U) #define NETC_ETH_LINK_PM0_IMASK_LOC_FAULT_SHIFT (0U) /*! LOC_FAULT - Local fault event (XGMII) mask */ #define NETC_ETH_LINK_PM0_IMASK_LOC_FAULT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_LOC_FAULT_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_LOC_FAULT_MASK) #define NETC_ETH_LINK_PM0_IMASK_REM_FAULT_MASK (0x2U) #define NETC_ETH_LINK_PM0_IMASK_REM_FAULT_SHIFT (1U) /*! REM_FAULT - Remote fault event (XGMII) mask */ #define NETC_ETH_LINK_PM0_IMASK_REM_FAULT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_REM_FAULT_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_REM_FAULT_MASK) #define NETC_ETH_LINK_PM0_IMASK_LI_FAULT_MASK (0x80U) #define NETC_ETH_LINK_PM0_IMASK_LI_FAULT_SHIFT (7U) /*! LI_FAULT - Link Interruption fault (XGMII) event mask */ #define NETC_ETH_LINK_PM0_IMASK_LI_FAULT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_LI_FAULT_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_LI_FAULT_MASK) #define NETC_ETH_LINK_PM0_IMASK_MGI_MASK (0x4000U) #define NETC_ETH_LINK_PM0_IMASK_MGI_SHIFT (14U) /*! MGI - Magic packet detection indication event mask. */ #define NETC_ETH_LINK_PM0_IMASK_MGI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_MGI_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_MGI_MASK) #define NETC_ETH_LINK_PM0_IMASK_TX_CSD_MASK (0x200000U) #define NETC_ETH_LINK_PM0_IMASK_TX_CSD_SHIFT (21U) /*! TX_CSD - Tx Clock Stop Detection */ #define NETC_ETH_LINK_PM0_IMASK_TX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_TX_CSD_MASK) #define NETC_ETH_LINK_PM0_IMASK_RX_CSD_MASK (0x400000U) #define NETC_ETH_LINK_PM0_IMASK_RX_CSD_SHIFT (22U) /*! RX_CSD - Rx Clock Stop Detection */ #define NETC_ETH_LINK_PM0_IMASK_RX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_RX_CSD_MASK) #define NETC_ETH_LINK_PM0_IMASK_SPD_DUP_MASK (0x800000U) #define NETC_ETH_LINK_PM0_IMASK_SPD_DUP_SHIFT (23U) /*! SPD_DUP - Speed/Duplex change event mask. */ #define NETC_ETH_LINK_PM0_IMASK_SPD_DUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_SPD_DUP_MASK) #define NETC_ETH_LINK_PM0_IMASK_LINK_UP_MASK (0x1000000U) #define NETC_ETH_LINK_PM0_IMASK_LINK_UP_SHIFT (24U) /*! LINK_UP - Link Up */ #define NETC_ETH_LINK_PM0_IMASK_LINK_UP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_LINK_UP_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_LINK_UP_MASK) #define NETC_ETH_LINK_PM0_IMASK_LINK_DOWN_MASK (0x2000000U) #define NETC_ETH_LINK_PM0_IMASK_LINK_DOWN_SHIFT (25U) /*! LINK_DOWN - Link Down */ #define NETC_ETH_LINK_PM0_IMASK_LINK_DOWN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_LINK_DOWN_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_LINK_DOWN_MASK) #define NETC_ETH_LINK_PM0_IMASK_AN_DONE_MASK (0x4000000U) #define NETC_ETH_LINK_PM0_IMASK_AN_DONE_SHIFT (26U) /*! AN_DONE - Auto-Negotiation Done */ #define NETC_ETH_LINK_PM0_IMASK_AN_DONE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_AN_DONE_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_AN_DONE_MASK) #define NETC_ETH_LINK_PM0_IMASK_MRG_SERR_MASK (0x8000000U) #define NETC_ETH_LINK_PM0_IMASK_MRG_SERR_SHIFT (27U) /*! MRG_SERR - MAC merge frame SMD error received event interrupt mask */ #define NETC_ETH_LINK_PM0_IMASK_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_MRG_SERR_MASK) #define NETC_ETH_LINK_PM0_IMASK_MRG_AERR_MASK (0x10000000U) #define NETC_ETH_LINK_PM0_IMASK_MRG_AERR_SHIFT (28U) /*! MRG_AERR - MAC merge frame assembly error event interrupt mask */ #define NETC_ETH_LINK_PM0_IMASK_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IMASK_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM0_IMASK_MRG_AERR_MASK) /*! @} */ /*! @name PM0_PAUSE_QUANTA - Port MAC 0 Pause Quanta Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_MASK (0xFFFFU) #define NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_SHIFT (0U) /*! PQNT - Value to be used for the quanta value when XOFF is triggered. */ #define NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_SHIFT)) & NETC_ETH_LINK_PM0_PAUSE_QUANTA_PQNT_MASK) /*! @} */ /*! @name PM0_PAUSE_THRESH - Port MAC 0 Pause Quanta Threshold Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_MASK (0xFFFFU) #define NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_SHIFT (0U) /*! QTH - Quanta threshold. */ #define NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_SHIFT)) & NETC_ETH_LINK_PM0_PAUSE_THRESH_QTH_MASK) /*! @} */ /*! @name PM0_RX_PAUSE_STATUS - Port MAC 0 Receive Pause Status Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_MASK (0x1U) #define NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT (0U) /*! PSTAT - Pause status. */ #define NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_SHIFT)) & NETC_ETH_LINK_PM0_RX_PAUSE_STATUS_PSTAT_MASK) /*! @} */ /*! @name PM0_LPWAKE_TIMER - Port MAC 0 EEE Low Power Wakeup Timer Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU) #define NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U) /*! TW_SYS_TX - EEE System transmit wait time */ #define NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & NETC_ETH_LINK_PM0_LPWAKE_TIMER_TW_SYS_TX_MASK) /*! @} */ /*! @name PM0_SLEEP_TIMER - Port MAC 0 Transmit EEE Low Power Timer Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU) #define NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_SHIFT (0U) #define NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_SHIFT)) & NETC_ETH_LINK_PM0_SLEEP_TIMER_SLEEPT_MASK) /*! @} */ /*! @name PM0_SINGLE_STEP - Port MAC 0 IEEE1588 Single-Step Control Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_SINGLE_STEP_CH_MASK (0x40U) #define NETC_ETH_LINK_PM0_SINGLE_STEP_CH_SHIFT (6U) /*! CH - Checksum update */ #define NETC_ETH_LINK_PM0_SINGLE_STEP_CH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SINGLE_STEP_CH_SHIFT)) & NETC_ETH_LINK_PM0_SINGLE_STEP_CH_MASK) #define NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_MASK (0x7F80U) #define NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_SHIFT (7U) #define NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_SHIFT)) & NETC_ETH_LINK_PM0_SINGLE_STEP_OFFSET_MASK) #define NETC_ETH_LINK_PM0_SINGLE_STEP_EN_MASK (0x80000000U) #define NETC_ETH_LINK_PM0_SINGLE_STEP_EN_SHIFT (31U) /*! EN - IEEE-1588 Single-Step enable. */ #define NETC_ETH_LINK_PM0_SINGLE_STEP_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_SINGLE_STEP_EN_SHIFT)) & NETC_ETH_LINK_PM0_SINGLE_STEP_EN_MASK) /*! @} */ /*! @name PM0_HD_BACKOFF_ENTROPY - Port MAC 0 half-duplex backoff entropy register */ /*! @{ */ #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU) #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U) /*! HD_BACKOFF_ENTROPY - Half duplex backoff entropy */ #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK) #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) /*! SW_ENTROPY_VALID - SW programmable entropy valid * 0b0..Not valid * 0b1..Valid */ #define NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & NETC_ETH_LINK_PM0_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) /*! @} */ /*! @name PM0_HD_FLOW_CTRL - Port MAC 0 Half-Duplex Flow Control Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK (0xFFFU) #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT (0U) /*! HD_BP_OFF_MIN - Half-Duplex Back-Pressure Off Minimum */ #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT)) & NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK) #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK (0xFFF0000U) #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT (16U) /*! HD_BP_ON_MAX - Half-Duplex Back-Pressure On Maximum */ #define NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT)) & NETC_ETH_LINK_PM0_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK) /*! @} */ /*! @name PM0_STATN_CONFIG - Port MAC 0 Statistics Configuration Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_MASK (0x1U) #define NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_SHIFT (0U) #define NETC_ETH_LINK_PM0_STATN_CONFIG_SAT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_SAT_MASK) #define NETC_ETH_LINK_PM0_STATN_CONFIG_COD_MASK (0x2U) #define NETC_ETH_LINK_PM0_STATN_CONFIG_COD_SHIFT (1U) #define NETC_ETH_LINK_PM0_STATN_CONFIG_COD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_COD_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_COD_MASK) #define NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_MASK (0x4U) #define NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_SHIFT (2U) #define NETC_ETH_LINK_PM0_STATN_CONFIG_CLR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_CLR_MASK) #define NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_MASK (0x8U) #define NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_SHIFT (3U) /*! WEN - Write enable for Tx/Rx stats registers */ #define NETC_ETH_LINK_PM0_STATN_CONFIG_WEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_SHIFT)) & NETC_ETH_LINK_PM0_STATN_CONFIG_WEN_MASK) /*! @} */ /*! @name PM0_REOCTN - Port MAC 0 Receive Ethernet Octets Counter(etherStatsOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_REOCTN_REOCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_REOCTN_REOCTn_SHIFT (0U) /*! REOCTn - Incremented for each octet received in both good and bad packets. */ #define NETC_ETH_LINK_PM0_REOCTN_REOCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_REOCTN_REOCTn_SHIFT)) & NETC_ETH_LINK_PM0_REOCTN_REOCTn_MASK) /*! @} */ /*! @name PM0_ROCTN - Port MAC 0 Receive Octets Counter(iflnOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_ROCTN_ROCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_ROCTN_ROCTn_SHIFT (0U) /*! ROCTn - Incremented for each octet received except preamble (that is, Header, Payload, Pad and * FCS) for all valid frames and valid PAUSE frames received. */ #define NETC_ETH_LINK_PM0_ROCTN_ROCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_ROCTN_ROCTn_SHIFT)) & NETC_ETH_LINK_PM0_ROCTN_ROCTn_MASK) /*! @} */ /*! @name PM0_RXPFN - Port MAC 0 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RXPFN_RXPFn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RXPFN_RXPFn_SHIFT (0U) /*! RXPFn - Incremented for each valid PAUSE frame received . */ #define NETC_ETH_LINK_PM0_RXPFN_RXPFn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RXPFN_RXPFn_SHIFT)) & NETC_ETH_LINK_PM0_RXPFN_RXPFn_MASK) /*! @} */ /*! @name PM0_RFRMN - Port MAC 0 Receive Frame Counter Register(aFramesReceivedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RFRMN_RFRMn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RFRMN_RFRMn_SHIFT (0U) /*! RFRMn - Incremented for each frame received without error, including PAUSE frames. */ #define NETC_ETH_LINK_PM0_RFRMN_RFRMn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RFRMN_RFRMn_SHIFT)) & NETC_ETH_LINK_PM0_RFRMN_RFRMn_MASK) /*! @} */ /*! @name PM0_RFCSN - Port MAC 0 Receive Frame Check Sequence Error Counter Register() */ /*! @{ */ #define NETC_ETH_LINK_PM0_RFCSN_RFCSn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RFCSN_RFCSn_SHIFT (0U) /*! RFCSn - Incremented for each frame received with a CRC-32 error but the frame is otherwise of correct length. */ #define NETC_ETH_LINK_PM0_RFCSN_RFCSn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RFCSN_RFCSn_SHIFT)) & NETC_ETH_LINK_PM0_RFCSN_RFCSn_MASK) /*! @} */ /*! @name PM0_RVLANN - Port MAC 0 Receive VLAN Frame Counter Register(VLANReceivedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RVLANN_RVLANn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RVLANN_RVLANn_SHIFT (0U) /*! RVLANn - Incremented for each valid VLAN tagged frame received with EtherType 0x8100 */ #define NETC_ETH_LINK_PM0_RVLANN_RVLANn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RVLANN_RVLANn_SHIFT)) & NETC_ETH_LINK_PM0_RVLANN_RVLANn_MASK) /*! @} */ /*! @name PM0_RERRN - Port MAC 0 Receive Frame Error Counter Register(ifInErrorsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RERRN_RERRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RERRN_RERRn_SHIFT (0U) /*! RERRn - Incremented for each frame received with an error (except for undersized/fragment frame): */ #define NETC_ETH_LINK_PM0_RERRN_RERRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RERRN_RERRn_SHIFT)) & NETC_ETH_LINK_PM0_RERRN_RERRn_MASK) /*! @} */ /*! @name PM0_RUCAN - Port MAC 0 Receive Unicast Frame Counter Register(ifInUcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RUCAN_RUCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RUCAN_RUCAn_SHIFT (0U) /*! RUCAn - Incremented for each valid frame received(on the receive FIFO interface) in which bit 0 * of the destination address was 0 . */ #define NETC_ETH_LINK_PM0_RUCAN_RUCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RUCAN_RUCAn_SHIFT)) & NETC_ETH_LINK_PM0_RUCAN_RUCAn_MASK) /*! @} */ /*! @name PM0_RMCAN - Port MAC 0 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RMCAN_RMCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RMCAN_RMCAn_SHIFT (0U) #define NETC_ETH_LINK_PM0_RMCAN_RMCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RMCAN_RMCAn_SHIFT)) & NETC_ETH_LINK_PM0_RMCAN_RMCAn_MASK) /*! @} */ /*! @name PM0_RBCAN - Port MAC 0 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RBCAN_RBCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RBCAN_RBCAn_SHIFT (0U) /*! RBCAn - Incremented for each valid frame received(on the receive FIFO interface) in which all * bits of the destination address were 1 . */ #define NETC_ETH_LINK_PM0_RBCAN_RBCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RBCAN_RBCAn_SHIFT)) & NETC_ETH_LINK_PM0_RBCAN_RBCAn_MASK) /*! @} */ /*! @name PM0_RDRPN - Port MAC 0 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RDRPN_RDRPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RDRPN_RDRPn_SHIFT (0U) #define NETC_ETH_LINK_PM0_RDRPN_RDRPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RDRPN_RDRPn_SHIFT)) & NETC_ETH_LINK_PM0_RDRPN_RDRPn_MASK) /*! @} */ /*! @name PM0_RPKTN - Port MAC 0 Receive Packets Counter Register(etherStatsPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RPKTN_RPKTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RPKTN_RPKTn_SHIFT (0U) /*! RPKTn - Incremented for each good or bad packet received. */ #define NETC_ETH_LINK_PM0_RPKTN_RPKTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RPKTN_RPKTn_SHIFT)) & NETC_ETH_LINK_PM0_RPKTN_RPKTn_MASK) /*! @} */ /*! @name PM0_RUNDN - Port MAC 0 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RUNDN_RUNDn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RUNDN_RUNDn_SHIFT (0U) #define NETC_ETH_LINK_PM0_RUNDN_RUNDn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RUNDN_RUNDn_SHIFT)) & NETC_ETH_LINK_PM0_RUNDN_RUNDn_MASK) /*! @} */ /*! @name PM0_R64N - Port MAC 0 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_R64N_R64n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_R64N_R64n_SHIFT (0U) /*! R64n - Incremented for each 64-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM0_R64N_R64n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R64N_R64n_SHIFT)) & NETC_ETH_LINK_PM0_R64N_R64n_MASK) /*! @} */ /*! @name PM0_R127N - Port MAC 0 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_R127N_R127n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_R127N_R127n_SHIFT (0U) /*! R127n - Incremented for each 65- to 127-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM0_R127N_R127n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R127N_R127n_SHIFT)) & NETC_ETH_LINK_PM0_R127N_R127n_MASK) /*! @} */ /*! @name PM0_R255N - Port MAC 0 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_R255N_R255n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_R255N_R255n_SHIFT (0U) /*! R255n - Incremented for each 128- to 255-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM0_R255N_R255n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R255N_R255n_SHIFT)) & NETC_ETH_LINK_PM0_R255N_R255n_MASK) /*! @} */ /*! @name PM0_R511N - Port MAC 0 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_R511N_R511n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_R511N_R511n_SHIFT (0U) /*! R511n - Incremented for each 256- to 511-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM0_R511N_R511n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R511N_R511n_SHIFT)) & NETC_ETH_LINK_PM0_R511N_R511n_MASK) /*! @} */ /*! @name PM0_R1023N - Port MAC 0 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_R1023N_R1023n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_R1023N_R1023n_SHIFT (0U) /*! R1023n - Incremented for each 512- to 1023-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM0_R1023N_R1023n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R1023N_R1023n_SHIFT)) & NETC_ETH_LINK_PM0_R1023N_R1023n_MASK) /*! @} */ /*! @name PM0_R1522N - Port MAC 0 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_R1522N_R1522n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_R1522N_R1522n_SHIFT (0U) /*! R1522n - Incremented for each 1024- to 1522-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM0_R1522N_R1522n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R1522N_R1522n_SHIFT)) & NETC_ETH_LINK_PM0_R1522N_R1522n_MASK) /*! @} */ /*! @name PM0_R1523XN - Port MAC 0 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_R1523XN_R1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_R1523XN_R1523Xn_SHIFT (0U) #define NETC_ETH_LINK_PM0_R1523XN_R1523Xn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_R1523XN_R1523Xn_SHIFT)) & NETC_ETH_LINK_PM0_R1523XN_R1523Xn_MASK) /*! @} */ /*! @name PM0_ROVRN - Port MAC 0 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_ROVRN_ROVRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_ROVRN_ROVRn_SHIFT (0U) #define NETC_ETH_LINK_PM0_ROVRN_ROVRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_ROVRN_ROVRn_SHIFT)) & NETC_ETH_LINK_PM0_ROVRN_ROVRn_MASK) /*! @} */ /*! @name PM0_RJBRN - Port MAC 0 Receive Jabber Packet Counter Register(etherStatsJabbersn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RJBRN_RJBRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RJBRN_RJBRn_SHIFT (0U) #define NETC_ETH_LINK_PM0_RJBRN_RJBRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RJBRN_RJBRn_SHIFT)) & NETC_ETH_LINK_PM0_RJBRN_RJBRn_MASK) /*! @} */ /*! @name PM0_RFRGN - Port MAC 0 Receive Fragment Packet Counter Register(etherStatsFragmentsn */ /*! @{ */ #define NETC_ETH_LINK_PM0_RFRGN_RFRGn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RFRGN_RFRGn_SHIFT (0U) #define NETC_ETH_LINK_PM0_RFRGN_RFRGn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RFRGN_RFRGn_SHIFT)) & NETC_ETH_LINK_PM0_RFRGN_RFRGn_MASK) /*! @} */ /*! @name PM0_RCNPN - Port MAC 0 Receive Control Packet Counter Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_RCNPN_RCNPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RCNPN_RCNPn_SHIFT (0U) /*! RCNPn - Incremented for each valid control packet (type 0x8808) but not for PAUSE packets */ #define NETC_ETH_LINK_PM0_RCNPN_RCNPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RCNPN_RCNPn_SHIFT)) & NETC_ETH_LINK_PM0_RCNPN_RCNPn_MASK) /*! @} */ /*! @name PM0_RDRNTPN - Port MAC 0 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_SHIFT (0U) /*! RDRNTPn - Incremented for each fully dropped packet (not truncated) due to internal errors of * the MAC client. Occurs when a receive FIFO overflows. */ #define NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_SHIFT)) & NETC_ETH_LINK_PM0_RDRNTPN_RDRNTPn_MASK) /*! @} */ /*! @name PM0_TEOCTN - Port MAC 0 Transmit Ethernet Octets Counter(etherStatsOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_SHIFT (0U) /*! TEOCTn - Incremented for each octet transmitted in both good and bad packets. */ #define NETC_ETH_LINK_PM0_TEOCTN_TEOCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_SHIFT)) & NETC_ETH_LINK_PM0_TEOCTN_TEOCTn_MASK) /*! @} */ /*! @name PM0_TOCTN - Port MAC 0 Transmit Octets Counter Register(ifOutOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TOCTN_TOCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TOCTN_TOCTn_SHIFT (0U) #define NETC_ETH_LINK_PM0_TOCTN_TOCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TOCTN_TOCTn_SHIFT)) & NETC_ETH_LINK_PM0_TOCTN_TOCTn_MASK) /*! @} */ /*! @name PM0_TXPFN - Port MAC 0 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TXPFN_TXPFn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TXPFN_TXPFn_SHIFT (0U) /*! TXPFn - Incremented for each valid PAUSE frame transmitted . Note: Pause frames forwarded to the * MAC from MAC Client are not counted by TXPFn. */ #define NETC_ETH_LINK_PM0_TXPFN_TXPFn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TXPFN_TXPFn_SHIFT)) & NETC_ETH_LINK_PM0_TXPFN_TXPFn_MASK) /*! @} */ /*! @name PM0_TFRMN - Port MAC 0 Transmit Frame Counter Register(aFramesTransmittedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TFRMN_TFRMn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TFRMN_TFRMn_SHIFT (0U) /*! TFRMn - Incremented for each frame transmitted without error, including PAUSE frames. */ #define NETC_ETH_LINK_PM0_TFRMN_TFRMn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TFRMN_TFRMn_SHIFT)) & NETC_ETH_LINK_PM0_TFRMN_TFRMn_MASK) /*! @} */ /*! @name PM0_TFCSN - Port MAC 0 Transmit Frame Check Sequence Error Counter Register() */ /*! @{ */ #define NETC_ETH_LINK_PM0_TFCSN_TFCSn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TFCSN_TFCSn_SHIFT (0U) /*! TFCSn - Incremented for each frame transmitted with a CRC-32 error except for underflows. */ #define NETC_ETH_LINK_PM0_TFCSN_TFCSn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TFCSN_TFCSn_SHIFT)) & NETC_ETH_LINK_PM0_TFCSN_TFCSn_MASK) /*! @} */ /*! @name PM0_TVLANN - Port MAC 0 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TVLANN_TVLANn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TVLANN_TVLANn_SHIFT (0U) /*! TVLANn - Incremented for each valid VLAN tagged frame transmitted with EtherType 0x8100. */ #define NETC_ETH_LINK_PM0_TVLANN_TVLANn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TVLANN_TVLANn_SHIFT)) & NETC_ETH_LINK_PM0_TVLANN_TVLANn_MASK) /*! @} */ /*! @name PM0_TERRN - Port MAC 0 Transmit Frame Error Counter Register(ifOutErrorsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TERRN_TERRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TERRN_TERRn_SHIFT (0U) /*! TERRn - Transmit frame error count */ #define NETC_ETH_LINK_PM0_TERRN_TERRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TERRN_TERRn_SHIFT)) & NETC_ETH_LINK_PM0_TERRN_TERRn_MASK) /*! @} */ /*! @name PM0_TUCAN - Port MAC 0 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TUCAN_TUCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TUCAN_TUCAn_SHIFT (0U) /*! TUCAn - Incremented for each valid frame transmitted(to the FIFO interface) in which bit 0 of the destination address was 0. */ #define NETC_ETH_LINK_PM0_TUCAN_TUCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TUCAN_TUCAn_SHIFT)) & NETC_ETH_LINK_PM0_TUCAN_TUCAn_MASK) /*! @} */ /*! @name PM0_TMCAN - Port MAC 0 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TMCAN_TMCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TMCAN_TMCAn_SHIFT (0U) #define NETC_ETH_LINK_PM0_TMCAN_TMCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TMCAN_TMCAn_SHIFT)) & NETC_ETH_LINK_PM0_TMCAN_TMCAn_MASK) /*! @} */ /*! @name PM0_TBCAN - Port MAC 0 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TBCAN_TBCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TBCAN_TBCAn_SHIFT (0U) /*! TBCAn - Incremented for each valid frame transmitted(to the FIFO interface) in which all bits of * the destination address were 1 . */ #define NETC_ETH_LINK_PM0_TBCAN_TBCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TBCAN_TBCAn_SHIFT)) & NETC_ETH_LINK_PM0_TBCAN_TBCAn_MASK) /*! @} */ /*! @name PM0_TPKTN - Port MAC 0 Transmit Packets Counter Register(etherStatsPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TPKTN_TPKTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TPKTN_TPKTn_SHIFT (0U) /*! TPKTn - Incremented for each good or bad packet transmitted. */ #define NETC_ETH_LINK_PM0_TPKTN_TPKTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TPKTN_TPKTn_SHIFT)) & NETC_ETH_LINK_PM0_TPKTN_TPKTn_MASK) /*! @} */ /*! @name PM0_TUNDN - Port MAC 0 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TUNDN_TUNDn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TUNDN_TUNDn_SHIFT (0U) /*! TUNDn - Incremented for each packet transmitted that was less than 64 octets long with a good CRC. */ #define NETC_ETH_LINK_PM0_TUNDN_TUNDn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TUNDN_TUNDn_SHIFT)) & NETC_ETH_LINK_PM0_TUNDN_TUNDn_MASK) /*! @} */ /*! @name PM0_T64N - Port MAC 0 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_T64N_T64n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_T64N_T64n_SHIFT (0U) /*! T64n - Incremented for each 64-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM0_T64N_T64n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T64N_T64n_SHIFT)) & NETC_ETH_LINK_PM0_T64N_T64n_MASK) /*! @} */ /*! @name PM0_T127N - Port MAC 0 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_T127N_T127n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_T127N_T127n_SHIFT (0U) /*! T127n - Incremented for each 65 to 127-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM0_T127N_T127n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T127N_T127n_SHIFT)) & NETC_ETH_LINK_PM0_T127N_T127n_MASK) /*! @} */ /*! @name PM0_T255N - Port MAC 0 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_T255N_T255n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_T255N_T255n_SHIFT (0U) /*! T255n - Incremented for each 128 to 255-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM0_T255N_T255n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T255N_T255n_SHIFT)) & NETC_ETH_LINK_PM0_T255N_T255n_MASK) /*! @} */ /*! @name PM0_T511N - Port MAC 0 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_T511N_T511n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_T511N_T511n_SHIFT (0U) /*! T511n - Incremented for each 256 to 511-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM0_T511N_T511n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T511N_T511n_SHIFT)) & NETC_ETH_LINK_PM0_T511N_T511n_MASK) /*! @} */ /*! @name PM0_T1023N - Port MAC 0 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_T1023N_T1023n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_T1023N_T1023n_SHIFT (0U) /*! T1023n - Incremented for each 512 to 1023-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM0_T1023N_T1023n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T1023N_T1023n_SHIFT)) & NETC_ETH_LINK_PM0_T1023N_T1023n_MASK) /*! @} */ /*! @name PM0_T1522N - Port MAC 0 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_T1522N_T1522n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_T1522N_T1522n_SHIFT (0U) /*! T1522n - Incremented for each 1024- to 1522-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM0_T1522N_T1522n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T1522N_T1522n_SHIFT)) & NETC_ETH_LINK_PM0_T1522N_T1522n_MASK) /*! @} */ /*! @name PM0_T1523XN - Port MAC 0 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM0_T1523XN_T1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_T1523XN_T1523Xn_SHIFT (0U) #define NETC_ETH_LINK_PM0_T1523XN_T1523Xn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_T1523XN_T1523Xn_SHIFT)) & NETC_ETH_LINK_PM0_T1523XN_T1523Xn_MASK) /*! @} */ /*! @name PM0_TCNPN - Port MAC 0 Transmit Control Packet Counter Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_TCNPN_TCNPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TCNPN_TCNPn_SHIFT (0U) /*! TCNPn - Incremented for each valid control packet transmitted (type 0x8808) but not for PAUSE packets */ #define NETC_ETH_LINK_PM0_TCNPN_TCNPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TCNPN_TCNPn_SHIFT)) & NETC_ETH_LINK_PM0_TCNPN_TCNPn_MASK) /*! @} */ /*! @name PM0_TDFRN - Port MAC 0 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TDFRN_TDFRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TDFRN_TDFRn_SHIFT (0U) /*! TDFRn - Increments for successful transmissions, without retransmits, that were deferred (half-duplex only). */ #define NETC_ETH_LINK_PM0_TDFRN_TDFRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TDFRN_TDFRn_SHIFT)) & NETC_ETH_LINK_PM0_TDFRN_TDFRn_MASK) /*! @} */ /*! @name PM0_TMCOLN - Port MAC 0 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */ /*! @{ */ #define NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_SHIFT (0U) /*! TMCOLn - Increments for successful transmission after more than one retransmission (half-duplex only). */ #define NETC_ETH_LINK_PM0_TMCOLN_TMCOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_SHIFT)) & NETC_ETH_LINK_PM0_TMCOLN_TMCOLn_MASK) /*! @} */ /*! @name PM0_TSCOLN - Port MAC 0 Transmit Single Collision Counter(aSingleCollisionFrames) Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_SHIFT (0U) /*! TSCOLn - Increments for successful transmission after one retransmission (half-duplex only). */ #define NETC_ETH_LINK_PM0_TSCOLN_TSCOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_SHIFT)) & NETC_ETH_LINK_PM0_TSCOLN_TSCOLn_MASK) /*! @} */ /*! @name PM0_TLCOLN - Port MAC 0 Transmit Late Collision Counter(aLateCollisions) Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_SHIFT (0U) /*! TLCOLn - Late collision occurred. Frame corrupted / discarded (half-duplex only) */ #define NETC_ETH_LINK_PM0_TLCOLN_TLCOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_SHIFT)) & NETC_ETH_LINK_PM0_TLCOLN_TLCOLn_MASK) /*! @} */ /*! @name PM0_TECOLN - Port MAC 0 Transmit Excessive Collisions Counter Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_TECOLN_TECOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM0_TECOLN_TECOLn_SHIFT (0U) /*! TECOLn - Excessive collisions occurred. Frame was discarded (half-duplex only) */ #define NETC_ETH_LINK_PM0_TECOLN_TECOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM0_TECOLN_TECOLn_SHIFT)) & NETC_ETH_LINK_PM0_TECOLN_TECOLn_MASK) /*! @} */ /*! @name PM0_IF_MODE - Port MAC 0 Interface Mode Control Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_IF_MODE_IFMODE_MASK (0x7U) #define NETC_ETH_LINK_PM0_IF_MODE_IFMODE_SHIFT (0U) /*! IFMODE - Interface mode */ #define NETC_ETH_LINK_PM0_IF_MODE_IFMODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_IFMODE_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_IFMODE_MASK) #define NETC_ETH_LINK_PM0_IF_MODE_REVMII_MASK (0x8U) #define NETC_ETH_LINK_PM0_IF_MODE_REVMII_SHIFT (3U) /*! REVMII - Reverse Mode * 0b0..Reverse mode disabled - port is in MAC mode * 0b1..Reverse mode enabled - port is in PHY mode */ #define NETC_ETH_LINK_PM0_IF_MODE_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_REVMII_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_REVMII_MASK) #define NETC_ETH_LINK_PM0_IF_MODE_M10_MASK (0x10U) #define NETC_ETH_LINK_PM0_IF_MODE_M10_SHIFT (4U) /*! M10 * 0b0..100 Mbps * 0b1..10 Mbps */ #define NETC_ETH_LINK_PM0_IF_MODE_M10(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_M10_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_M10_MASK) #define NETC_ETH_LINK_PM0_IF_MODE_HD_MASK (0x40U) #define NETC_ETH_LINK_PM0_IF_MODE_HD_SHIFT (6U) /*! HD - Half-duplex * 0b0..full duplex * 0b1..half duplex */ #define NETC_ETH_LINK_PM0_IF_MODE_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_HD_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_HD_MASK) #define NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_MASK (0x1000U) #define NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_SHIFT (12U) /*! CLK_STOP - Clock Stop * 0b0..Not stoppable * 0b1..Stoppable */ #define NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_CLK_STOP_MASK) #define NETC_ETH_LINK_PM0_IF_MODE_SSP_MASK (0x6000U) #define NETC_ETH_LINK_PM0_IF_MODE_SSP_SHIFT (13U) /*! SSP - Set Speed * 0b00..100 Mbps * 0b01..10 Mbps * 0b10..1 Gbps * 0b11..reserved */ #define NETC_ETH_LINK_PM0_IF_MODE_SSP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_SSP_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_SSP_MASK) #define NETC_ETH_LINK_PM0_IF_MODE_ENA_MASK (0x8000U) #define NETC_ETH_LINK_PM0_IF_MODE_ENA_SHIFT (15U) /*! ENA - AN Enable * 0b0..SSP and HD fields determine the RGMII link speed and duplex mode * 0b1..RGMII Auto-Negotiation Enabled - PHY in-band status information is used to select the speed of operation and duplex mode. */ #define NETC_ETH_LINK_PM0_IF_MODE_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_MODE_ENA_SHIFT)) & NETC_ETH_LINK_PM0_IF_MODE_ENA_MASK) /*! @} */ /*! @name PM0_IF_STATUS - Port MAC 0 Interface Status Register */ /*! @{ */ #define NETC_ETH_LINK_PM0_IF_STATUS_RGFD_MASK (0x1000U) #define NETC_ETH_LINK_PM0_IF_STATUS_RGFD_SHIFT (12U) /*! RGFD - RGMII full duplex */ #define NETC_ETH_LINK_PM0_IF_STATUS_RGFD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_STATUS_RGFD_SHIFT)) & NETC_ETH_LINK_PM0_IF_STATUS_RGFD_MASK) #define NETC_ETH_LINK_PM0_IF_STATUS_RGSP_MASK (0x6000U) #define NETC_ETH_LINK_PM0_IF_STATUS_RGSP_SHIFT (13U) /*! RGSP - RGMII speed setting */ #define NETC_ETH_LINK_PM0_IF_STATUS_RGSP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_STATUS_RGSP_SHIFT)) & NETC_ETH_LINK_PM0_IF_STATUS_RGSP_MASK) #define NETC_ETH_LINK_PM0_IF_STATUS_RGLNK_MASK (0x8000U) #define NETC_ETH_LINK_PM0_IF_STATUS_RGLNK_SHIFT (15U) /*! RGLNK - RGMII link */ #define NETC_ETH_LINK_PM0_IF_STATUS_RGLNK(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM0_IF_STATUS_RGLNK_SHIFT)) & NETC_ETH_LINK_PM0_IF_STATUS_RGLNK_MASK) /*! @} */ /*! @name PM1_COMMAND_CONFIG - Port MAC 1 Command and Configuration Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_MASK (0x1U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_SHIFT (0U) /*! TX_EN - MAC transmit path enable */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_EN_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_MASK (0x2U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_SHIFT (1U) /*! RX_EN - MAC receive path enable */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_EN_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK (0x80U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT (7U) /*! PAUSE_FWD - Terminate/forward received PAUSE frames */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_FWD_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK (0x100U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT (8U) /*! PAUSE_IGN - Ignore PAUSE frame quanta */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_PAUSE_IGN_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_MASK (0x400U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT (10U) /*! LOOP_ENA - Loopback enable */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_LOOP_ENA_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_MASK (0x1800U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_SHIFT (11U) /*! LPBK_MODE - Loopback mode */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_LPBK_MODE_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK (0x2000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT (13U) /*! CNT_FRM_EN - Control frame reception enable */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_CNT_FRM_EN_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_MASK (0x4000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_SHIFT (14U) /*! TS_PNT - Timestamp Point */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_PNT_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_MASK (0x8000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_SHIFT (15U) /*! TXP - Enable padding of frames in transmit direction (1, default). */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TXP_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_MASK (0x400000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT (22U) /*! TX_FLUSH - Tx flush */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_FLUSH_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK (0x800000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT (23U) /*! TX_LOWP_ENA - Transmit Low Power Idle Enable. * 0b0..(default), the MAC operates in normal mode. * 0b1..The MAC completes the transmission of the current Frame and generates Low Power Idle Sequences to the * line. It is advised to inspect IEVENT[TX_EMPTY] is set before enabling the LPI. */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TX_LOWP_ENA_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_MASK (0x4000000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_SHIFT (26U) /*! SWR - Software Reset. Self clearing bit. */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_SWR_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_MASK (0x10000000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_SHIFT (28U) /*! RX_FLUSH - Ingress flush enable */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_RX_FLUSH_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_MASK (0x40000000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_SHIFT (30U) /*! TS_MODE - Transmit timestamp mode */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_TS_MODE_MASK) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_MASK (0x80000000U) #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_SHIFT (31U) /*! MG - Magic Packet detection enable. */ #define NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_SHIFT)) & NETC_ETH_LINK_PM1_COMMAND_CONFIG_MG_MASK) /*! @} */ /*! @name PM1_MAC_ADDR_0 - Port MAC 1 MAC Address Register 0 */ /*! @{ */ #define NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT (0U) /*! MAC_ADDR_0 - MAC address 0 */ #define NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_SHIFT)) & NETC_ETH_LINK_PM1_MAC_ADDR_0_MAC_ADDR_0_MASK) /*! @} */ /*! @name PM1_MAC_ADDR_1 - Port MAC 1 MAC Address Register 1 */ /*! @{ */ #define NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK (0xFFFFU) #define NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT (0U) /*! MAC_ADDR_1 - MAC address 1 */ #define NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_SHIFT)) & NETC_ETH_LINK_PM1_MAC_ADDR_1_MAC_ADDR_1_MASK) /*! @} */ /*! @name PM1_MAXFRM - Port MAC 1 Maximum Frame Length Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_MASK (0xFFFFU) #define NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_SHIFT (0U) /*! MAXFRM - Maximum supported received frame length. */ #define NETC_ETH_LINK_PM1_MAXFRM_MAXFRM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_SHIFT)) & NETC_ETH_LINK_PM1_MAXFRM_MAXFRM_MASK) #define NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_MASK (0xFFFF0000U) #define NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_SHIFT (16U) /*! TX_MTU - Maximum transmit frame length */ #define NETC_ETH_LINK_PM1_MAXFRM_TX_MTU(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_SHIFT)) & NETC_ETH_LINK_PM1_MAXFRM_TX_MTU_MASK) /*! @} */ /*! @name PM1_IEVENT - Port MAC 1 Interrupt Event Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_MASK (0x20U) #define NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_SHIFT (5U) /*! TX_EMPTY - Transmit FIFO empty event */ #define NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_EMPTY_MASK) #define NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_MASK (0x40U) #define NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_SHIFT (6U) /*! RX_EMPTY - Receive idle event */ #define NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_RX_EMPTY_MASK) #define NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_MASK (0x400U) #define NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_SHIFT (10U) /*! TX_OVFL - Transmit FIFO overflow event. */ #define NETC_ETH_LINK_PM1_IEVENT_TX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_OVFL_MASK) #define NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_MASK (0x800U) #define NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_SHIFT (11U) /*! TX_UNFL - Transmit FIFO underflow event. */ #define NETC_ETH_LINK_PM1_IEVENT_TX_UNFL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_UNFL_MASK) #define NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_MASK (0x1000U) #define NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_SHIFT (12U) /*! RX_OVFL - Receive FIFO overflow event. */ #define NETC_ETH_LINK_PM1_IEVENT_RX_OVFL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_RX_OVFL_MASK) #define NETC_ETH_LINK_PM1_IEVENT_MGI_MASK (0x4000U) #define NETC_ETH_LINK_PM1_IEVENT_MGI_SHIFT (14U) /*! MGI - Magic packet detection indication event */ #define NETC_ETH_LINK_PM1_IEVENT_MGI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_MGI_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_MGI_MASK) #define NETC_ETH_LINK_PM1_IEVENT_TX_CSD_MASK (0x200000U) #define NETC_ETH_LINK_PM1_IEVENT_TX_CSD_SHIFT (21U) /*! TX_CSD - Tx Clock Stop Detection */ #define NETC_ETH_LINK_PM1_IEVENT_TX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_TX_CSD_MASK) #define NETC_ETH_LINK_PM1_IEVENT_RX_CSD_MASK (0x400000U) #define NETC_ETH_LINK_PM1_IEVENT_RX_CSD_SHIFT (22U) /*! RX_CSD - Rx Clock Stop Detection */ #define NETC_ETH_LINK_PM1_IEVENT_RX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_RX_CSD_MASK) #define NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_MASK (0x800000U) #define NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_SHIFT (23U) /*! SPD_DUP - Speed/Duplex Change */ #define NETC_ETH_LINK_PM1_IEVENT_SPD_DUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_SPD_DUP_MASK) #define NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_MASK (0x8000000U) #define NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_SHIFT (27U) /*! MRG_SERR - MAC merge frame SMD error received event */ #define NETC_ETH_LINK_PM1_IEVENT_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_MRG_SERR_MASK) #define NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_MASK (0x10000000U) #define NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_SHIFT (28U) /*! MRG_AERR - MAC merge frame assembly error event */ #define NETC_ETH_LINK_PM1_IEVENT_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM1_IEVENT_MRG_AERR_MASK) /*! @} */ /*! @name PM1_IMASK - Port MAC 1 Interrupt Mask Register(INT_MASK) */ /*! @{ */ #define NETC_ETH_LINK_PM1_IMASK_MGI_MASK (0x4000U) #define NETC_ETH_LINK_PM1_IMASK_MGI_SHIFT (14U) /*! MGI - Magic packet detection indication event mask. */ #define NETC_ETH_LINK_PM1_IMASK_MGI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_MGI_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_MGI_MASK) #define NETC_ETH_LINK_PM1_IMASK_TX_CSD_MASK (0x200000U) #define NETC_ETH_LINK_PM1_IMASK_TX_CSD_SHIFT (21U) /*! TX_CSD - Tx Clock Stop Detection */ #define NETC_ETH_LINK_PM1_IMASK_TX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_TX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_TX_CSD_MASK) #define NETC_ETH_LINK_PM1_IMASK_RX_CSD_MASK (0x400000U) #define NETC_ETH_LINK_PM1_IMASK_RX_CSD_SHIFT (22U) /*! RX_CSD - Rx Clock Stop Detection */ #define NETC_ETH_LINK_PM1_IMASK_RX_CSD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_RX_CSD_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_RX_CSD_MASK) #define NETC_ETH_LINK_PM1_IMASK_SPD_DUP_MASK (0x800000U) #define NETC_ETH_LINK_PM1_IMASK_SPD_DUP_SHIFT (23U) /*! SPD_DUP - Speed/Duplex change event mask. */ #define NETC_ETH_LINK_PM1_IMASK_SPD_DUP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_SPD_DUP_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_SPD_DUP_MASK) #define NETC_ETH_LINK_PM1_IMASK_MRG_SERR_MASK (0x8000000U) #define NETC_ETH_LINK_PM1_IMASK_MRG_SERR_SHIFT (27U) /*! MRG_SERR - MAC merge frame SMD error received event interrupt mask */ #define NETC_ETH_LINK_PM1_IMASK_MRG_SERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_MRG_SERR_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_MRG_SERR_MASK) #define NETC_ETH_LINK_PM1_IMASK_MRG_AERR_MASK (0x10000000U) #define NETC_ETH_LINK_PM1_IMASK_MRG_AERR_SHIFT (28U) /*! MRG_AERR - MAC merge frame assembly error event interrupt mask */ #define NETC_ETH_LINK_PM1_IMASK_MRG_AERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IMASK_MRG_AERR_SHIFT)) & NETC_ETH_LINK_PM1_IMASK_MRG_AERR_MASK) /*! @} */ /*! @name PM1_PAUSE_QUANTA - Port MAC 1 Pause Quanta Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_MASK (0xFFFFU) #define NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_SHIFT (0U) /*! PQNT - Value to be used for the quanta value when XOFF is triggered. */ #define NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_SHIFT)) & NETC_ETH_LINK_PM1_PAUSE_QUANTA_PQNT_MASK) /*! @} */ /*! @name PM1_PAUSE_THRESH - Port MAC 1 Pause Quanta Threshold Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_MASK (0xFFFFU) #define NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_SHIFT (0U) /*! QTH - Quanta threshold. */ #define NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_SHIFT)) & NETC_ETH_LINK_PM1_PAUSE_THRESH_QTH_MASK) /*! @} */ /*! @name PM1_RX_PAUSE_STATUS - Port MAC 1 Receive Pause Status Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_MASK (0x1U) #define NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT (0U) /*! PSTAT - Pause status. */ #define NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_SHIFT)) & NETC_ETH_LINK_PM1_RX_PAUSE_STATUS_PSTAT_MASK) /*! @} */ /*! @name PM1_LPWAKE_TIMER - Port MAC 1 EEE Low Power Wakeup Timer Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK (0xFFFFFFU) #define NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT (0U) /*! TW_SYS_TX - EEE System transmit wait time */ #define NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_SHIFT)) & NETC_ETH_LINK_PM1_LPWAKE_TIMER_TW_SYS_TX_MASK) /*! @} */ /*! @name PM1_SLEEP_TIMER - Port MAC 1 Transmit EEE Low Power Timer Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_MASK (0xFFFFFFU) #define NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_SHIFT (0U) #define NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_SHIFT)) & NETC_ETH_LINK_PM1_SLEEP_TIMER_SLEEPT_MASK) /*! @} */ /*! @name PM1_SINGLE_STEP - Port MAC 1 IEEE1588 Single-Step Control Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_SINGLE_STEP_CH_MASK (0x40U) #define NETC_ETH_LINK_PM1_SINGLE_STEP_CH_SHIFT (6U) /*! CH - Checksum update */ #define NETC_ETH_LINK_PM1_SINGLE_STEP_CH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SINGLE_STEP_CH_SHIFT)) & NETC_ETH_LINK_PM1_SINGLE_STEP_CH_MASK) #define NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_MASK (0x7F80U) #define NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_SHIFT (7U) #define NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_SHIFT)) & NETC_ETH_LINK_PM1_SINGLE_STEP_OFFSET_MASK) #define NETC_ETH_LINK_PM1_SINGLE_STEP_EN_MASK (0x80000000U) #define NETC_ETH_LINK_PM1_SINGLE_STEP_EN_SHIFT (31U) /*! EN - IEEE-1588 Single-Step enable. */ #define NETC_ETH_LINK_PM1_SINGLE_STEP_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_SINGLE_STEP_EN_SHIFT)) & NETC_ETH_LINK_PM1_SINGLE_STEP_EN_MASK) /*! @} */ /*! @name PM1_HD_BACKOFF_ENTROPY - Port MAC 1 half-duplex backoff entropy register */ /*! @{ */ #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK (0x3FFU) #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT (0U) /*! HD_BACKOFF_ENTROPY - Half duplex backoff entropy */ #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_SHIFT)) & NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_HD_BACKOFF_ENTROPY_MASK) #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK (0x80000000U) #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT (31U) /*! SW_ENTROPY_VALID - SW programmable entropy valid * 0b0..Not valid * 0b1..Valid */ #define NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_SHIFT)) & NETC_ETH_LINK_PM1_HD_BACKOFF_ENTROPY_SW_ENTROPY_VALID_MASK) /*! @} */ /*! @name PM1_HD_FLOW_CTRL - Port MAC 1 Half-Duplex Flow Control Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK (0xFFFU) #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT (0U) /*! HD_BP_OFF_MIN - Half-Duplex Back-Pressure Off Minimum */ #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_SHIFT)) & NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_OFF_MIN_MASK) #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK (0xFFF0000U) #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT (16U) /*! HD_BP_ON_MAX - Half-Duplex Back-Pressure On Maximum */ #define NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_SHIFT)) & NETC_ETH_LINK_PM1_HD_FLOW_CTRL_HD_BP_ON_MAX_MASK) /*! @} */ /*! @name PM1_STATN_CONFIG - Port MAC 1 Statistics Configuration Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_MASK (0x1U) #define NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_SHIFT (0U) #define NETC_ETH_LINK_PM1_STATN_CONFIG_SAT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_SAT_MASK) #define NETC_ETH_LINK_PM1_STATN_CONFIG_COD_MASK (0x2U) #define NETC_ETH_LINK_PM1_STATN_CONFIG_COD_SHIFT (1U) #define NETC_ETH_LINK_PM1_STATN_CONFIG_COD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_COD_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_COD_MASK) #define NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_MASK (0x4U) #define NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_SHIFT (2U) #define NETC_ETH_LINK_PM1_STATN_CONFIG_CLR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_CLR_MASK) #define NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_MASK (0x8U) #define NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_SHIFT (3U) /*! WEN - Write enable for Tx/Rx stats registers */ #define NETC_ETH_LINK_PM1_STATN_CONFIG_WEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_SHIFT)) & NETC_ETH_LINK_PM1_STATN_CONFIG_WEN_MASK) /*! @} */ /*! @name PM1_REOCTN - Port MAC 1 Receive Ethernet Octets Counter(etherStatsOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_REOCTN_REOCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_REOCTN_REOCTn_SHIFT (0U) /*! REOCTn - Incremented for each octet received in both good and bad packets. */ #define NETC_ETH_LINK_PM1_REOCTN_REOCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_REOCTN_REOCTn_SHIFT)) & NETC_ETH_LINK_PM1_REOCTN_REOCTn_MASK) /*! @} */ /*! @name PM1_ROCTN - Port MAC 1 Receive Octets Counter(iflnOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_ROCTN_ROCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_ROCTN_ROCTn_SHIFT (0U) /*! ROCTn - Incremented for each octet received except preamble (that is, Header, Payload, Pad and * FCS) for all valid frames and valid PAUSE frames received. */ #define NETC_ETH_LINK_PM1_ROCTN_ROCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_ROCTN_ROCTn_SHIFT)) & NETC_ETH_LINK_PM1_ROCTN_ROCTn_MASK) /*! @} */ /*! @name PM1_RXPFN - Port MAC 1 Receive Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RXPFN_RXPFn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RXPFN_RXPFn_SHIFT (0U) /*! RXPFn - Incremented for each valid PAUSE frame received . */ #define NETC_ETH_LINK_PM1_RXPFN_RXPFn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RXPFN_RXPFn_SHIFT)) & NETC_ETH_LINK_PM1_RXPFN_RXPFn_MASK) /*! @} */ /*! @name PM1_RFRMN - Port MAC 1 Receive Frame Counter Register(aFramesReceivedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RFRMN_RFRMn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RFRMN_RFRMn_SHIFT (0U) /*! RFRMn - Incremented for each frame received without error, including PAUSE frames. */ #define NETC_ETH_LINK_PM1_RFRMN_RFRMn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RFRMN_RFRMn_SHIFT)) & NETC_ETH_LINK_PM1_RFRMN_RFRMn_MASK) /*! @} */ /*! @name PM1_RFCSN - Port MAC 1 Receive Frame Check Sequence Error Counter Register() */ /*! @{ */ #define NETC_ETH_LINK_PM1_RFCSN_RFCSn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RFCSN_RFCSn_SHIFT (0U) /*! RFCSn - Incremented for each frame received with a CRC-32 error but the frame is otherwise of correct length. */ #define NETC_ETH_LINK_PM1_RFCSN_RFCSn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RFCSN_RFCSn_SHIFT)) & NETC_ETH_LINK_PM1_RFCSN_RFCSn_MASK) /*! @} */ /*! @name PM1_RVLANN - Port MAC 1 Receive VLAN Frame Counter Register(VLANReceivedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RVLANN_RVLANn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RVLANN_RVLANn_SHIFT (0U) /*! RVLANn - Incremented for each valid VLAN tagged frame received with EtherType 0x8100 */ #define NETC_ETH_LINK_PM1_RVLANN_RVLANn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RVLANN_RVLANn_SHIFT)) & NETC_ETH_LINK_PM1_RVLANN_RVLANn_MASK) /*! @} */ /*! @name PM1_RERRN - Port MAC 1 Receive Frame Error Counter Register(ifInErrorsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RERRN_RERRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RERRN_RERRn_SHIFT (0U) /*! RERRn - Incremented for each frame received with an error (except for undersized/fragment frame): */ #define NETC_ETH_LINK_PM1_RERRN_RERRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RERRN_RERRn_SHIFT)) & NETC_ETH_LINK_PM1_RERRN_RERRn_MASK) /*! @} */ /*! @name PM1_RUCAN - Port MAC 1 Receive Unicast Frame Counter Register(ifInUcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RUCAN_RUCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RUCAN_RUCAn_SHIFT (0U) /*! RUCAn - Incremented for each valid frame received(on the receive FIFO interface) in which bit 0 * of the destination address was 0 . */ #define NETC_ETH_LINK_PM1_RUCAN_RUCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RUCAN_RUCAn_SHIFT)) & NETC_ETH_LINK_PM1_RUCAN_RUCAn_MASK) /*! @} */ /*! @name PM1_RMCAN - Port MAC 1 Receive Multicast Frame Counter Register(ifInMulticastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RMCAN_RMCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RMCAN_RMCAn_SHIFT (0U) #define NETC_ETH_LINK_PM1_RMCAN_RMCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RMCAN_RMCAn_SHIFT)) & NETC_ETH_LINK_PM1_RMCAN_RMCAn_MASK) /*! @} */ /*! @name PM1_RBCAN - Port MAC 1 Receive Broadcast Frame Counter Register(ifInBroadcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RBCAN_RBCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RBCAN_RBCAn_SHIFT (0U) /*! RBCAn - Incremented for each valid frame received(on the receive FIFO interface) in which all * bits of the destination address were 1 . */ #define NETC_ETH_LINK_PM1_RBCAN_RBCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RBCAN_RBCAn_SHIFT)) & NETC_ETH_LINK_PM1_RBCAN_RBCAn_MASK) /*! @} */ /*! @name PM1_RDRPN - Port MAC 1 Receive Dropped Packets Counter Register(etherStatsDropEventsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RDRPN_RDRPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RDRPN_RDRPn_SHIFT (0U) #define NETC_ETH_LINK_PM1_RDRPN_RDRPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RDRPN_RDRPn_SHIFT)) & NETC_ETH_LINK_PM1_RDRPN_RDRPn_MASK) /*! @} */ /*! @name PM1_RPKTN - Port MAC 1 Receive Packets Counter Register(etherStatsPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RPKTN_RPKTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RPKTN_RPKTn_SHIFT (0U) /*! RPKTn - Incremented for each good or bad packet received. */ #define NETC_ETH_LINK_PM1_RPKTN_RPKTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RPKTN_RPKTn_SHIFT)) & NETC_ETH_LINK_PM1_RPKTN_RPKTn_MASK) /*! @} */ /*! @name PM1_RUNDN - Port MAC 1 Receive Undersized Packet Counter Register(etherStatsUndersizePktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RUNDN_RUNDn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RUNDN_RUNDn_SHIFT (0U) #define NETC_ETH_LINK_PM1_RUNDN_RUNDn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RUNDN_RUNDn_SHIFT)) & NETC_ETH_LINK_PM1_RUNDN_RUNDn_MASK) /*! @} */ /*! @name PM1_R64N - Port MAC 1 Receive 64-Octet Packet Counter Register(etherStatsPkts64OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_R64N_R64n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_R64N_R64n_SHIFT (0U) /*! R64n - Incremented for each 64-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM1_R64N_R64n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R64N_R64n_SHIFT)) & NETC_ETH_LINK_PM1_R64N_R64n_MASK) /*! @} */ /*! @name PM1_R127N - Port MAC 1 Receive 65 to 127-Octet Packet Counter Register(etherStatsPkts65to127OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_R127N_R127n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_R127N_R127n_SHIFT (0U) /*! R127n - Incremented for each 65- to 127-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM1_R127N_R127n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R127N_R127n_SHIFT)) & NETC_ETH_LINK_PM1_R127N_R127n_MASK) /*! @} */ /*! @name PM1_R255N - Port MAC 1 Receive 128 to 255-Octet Packet Counter Register(etherStatsPkts128to255OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_R255N_R255n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_R255N_R255n_SHIFT (0U) /*! R255n - Incremented for each 128- to 255-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM1_R255N_R255n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R255N_R255n_SHIFT)) & NETC_ETH_LINK_PM1_R255N_R255n_MASK) /*! @} */ /*! @name PM1_R511N - Port MAC 1 Receive 256 to 511-Octet Packet Counter Register(etherStatsPkts256to511OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_R511N_R511n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_R511N_R511n_SHIFT (0U) /*! R511n - Incremented for each 256- to 511-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM1_R511N_R511n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R511N_R511n_SHIFT)) & NETC_ETH_LINK_PM1_R511N_R511n_MASK) /*! @} */ /*! @name PM1_R1023N - Port MAC 1 Receive 512 to 1023-Octet Packet Counter Register(etherStatsPkts512to1023OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_R1023N_R1023n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_R1023N_R1023n_SHIFT (0U) /*! R1023n - Incremented for each 512- to 1023-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM1_R1023N_R1023n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R1023N_R1023n_SHIFT)) & NETC_ETH_LINK_PM1_R1023N_R1023n_MASK) /*! @} */ /*! @name PM1_R1522N - Port MAC 1 Receive 1024 to 1522-Octet Packet Counter Register(etherStatsPkts1024to1522OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_R1522N_R1522n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_R1522N_R1522n_SHIFT (0U) /*! R1522n - Incremented for each 1024- to 1522-octet frame received, good or bad. */ #define NETC_ETH_LINK_PM1_R1522N_R1522n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R1522N_R1522n_SHIFT)) & NETC_ETH_LINK_PM1_R1522N_R1522n_MASK) /*! @} */ /*! @name PM1_R1523XN - Port MAC 1 Receive 1523 to Max-Octet Packet Counter Register(etherStatsPkts1523toMaxOctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_R1523XN_R1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_R1523XN_R1523Xn_SHIFT (0U) #define NETC_ETH_LINK_PM1_R1523XN_R1523Xn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_R1523XN_R1523Xn_SHIFT)) & NETC_ETH_LINK_PM1_R1523XN_R1523Xn_MASK) /*! @} */ /*! @name PM1_ROVRN - Port MAC 1 Receive Oversized Packet Counter Register(etherStatsOversizePktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_ROVRN_ROVRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_ROVRN_ROVRn_SHIFT (0U) #define NETC_ETH_LINK_PM1_ROVRN_ROVRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_ROVRN_ROVRn_SHIFT)) & NETC_ETH_LINK_PM1_ROVRN_ROVRn_MASK) /*! @} */ /*! @name PM1_RJBRN - Port MAC 1 Receive Jabber Packet Counter Register(etherStatsJabbersn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RJBRN_RJBRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RJBRN_RJBRn_SHIFT (0U) #define NETC_ETH_LINK_PM1_RJBRN_RJBRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RJBRN_RJBRn_SHIFT)) & NETC_ETH_LINK_PM1_RJBRN_RJBRn_MASK) /*! @} */ /*! @name PM1_RFRGN - Port MAC 1 Receive Fragment Packet Counter Register(etherStatsFragmentsn */ /*! @{ */ #define NETC_ETH_LINK_PM1_RFRGN_RFRGn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RFRGN_RFRGn_SHIFT (0U) #define NETC_ETH_LINK_PM1_RFRGN_RFRGn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RFRGN_RFRGn_SHIFT)) & NETC_ETH_LINK_PM1_RFRGN_RFRGn_MASK) /*! @} */ /*! @name PM1_RCNPN - Port MAC 1 Receive Control Packet Counter Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_RCNPN_RCNPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RCNPN_RCNPn_SHIFT (0U) /*! RCNPn - Incremented for each valid control packet (type 0x8808) but not for PAUSE packets */ #define NETC_ETH_LINK_PM1_RCNPN_RCNPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RCNPN_RCNPn_SHIFT)) & NETC_ETH_LINK_PM1_RCNPN_RCNPn_MASK) /*! @} */ /*! @name PM1_RDRNTPN - Port MAC 1 Receive Dropped Not Truncated Packets Counter Register(etherStatsDropEventsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_SHIFT (0U) /*! RDRNTPn - Incremented for each fully dropped packet (not truncated) due to internal errors of * the MAC client. Occurs when a receive FIFO overflows. */ #define NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_SHIFT)) & NETC_ETH_LINK_PM1_RDRNTPN_RDRNTPn_MASK) /*! @} */ /*! @name PM1_TEOCTN - Port MAC 1 Transmit Ethernet Octets Counter(etherStatsOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_SHIFT (0U) /*! TEOCTn - Incremented for each octet transmitted in both good and bad packets. */ #define NETC_ETH_LINK_PM1_TEOCTN_TEOCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_SHIFT)) & NETC_ETH_LINK_PM1_TEOCTN_TEOCTn_MASK) /*! @} */ /*! @name PM1_TOCTN - Port MAC 1 Transmit Octets Counter Register(ifOutOctetsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TOCTN_TOCTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TOCTN_TOCTn_SHIFT (0U) #define NETC_ETH_LINK_PM1_TOCTN_TOCTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TOCTN_TOCTn_SHIFT)) & NETC_ETH_LINK_PM1_TOCTN_TOCTn_MASK) /*! @} */ /*! @name PM1_TXPFN - Port MAC 1 Transmit Valid Pause Frame Counter Register(aPAUSEMACCtrlFramesReceivedn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TXPFN_TXPFn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TXPFN_TXPFn_SHIFT (0U) /*! TXPFn - Incremented for each valid PAUSE frame transmitted . Note: Pause frames forwarded to the * MAC from MAC Client are not counted by TXPFn. */ #define NETC_ETH_LINK_PM1_TXPFN_TXPFn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TXPFN_TXPFn_SHIFT)) & NETC_ETH_LINK_PM1_TXPFN_TXPFn_MASK) /*! @} */ /*! @name PM1_TFRMN - Port MAC 1 Transmit Frame Counter Register(aFramesTransmittedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TFRMN_TFRMn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TFRMN_TFRMn_SHIFT (0U) /*! TFRMn - Incremented for each frame transmitted without error, including PAUSE frames. */ #define NETC_ETH_LINK_PM1_TFRMN_TFRMn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TFRMN_TFRMn_SHIFT)) & NETC_ETH_LINK_PM1_TFRMN_TFRMn_MASK) /*! @} */ /*! @name PM1_TFCSN - Port MAC 1 Transmit Frame Check Sequence Error Counter Register() */ /*! @{ */ #define NETC_ETH_LINK_PM1_TFCSN_TFCSn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TFCSN_TFCSn_SHIFT (0U) /*! TFCSn - Incremented for each frame transmitted with a CRC-32 error except for underflows. */ #define NETC_ETH_LINK_PM1_TFCSN_TFCSn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TFCSN_TFCSn_SHIFT)) & NETC_ETH_LINK_PM1_TFCSN_TFCSn_MASK) /*! @} */ /*! @name PM1_TVLANN - Port MAC 1 Transmit VLAN Frame Counter Register(VLANTransmittedOKn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TVLANN_TVLANn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TVLANN_TVLANn_SHIFT (0U) /*! TVLANn - Incremented for each valid VLAN tagged frame transmitted with EtherType 0x8100. */ #define NETC_ETH_LINK_PM1_TVLANN_TVLANn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TVLANN_TVLANn_SHIFT)) & NETC_ETH_LINK_PM1_TVLANN_TVLANn_MASK) /*! @} */ /*! @name PM1_TERRN - Port MAC 1 Transmit Frame Error Counter Register(ifOutErrorsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TERRN_TERRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TERRN_TERRn_SHIFT (0U) /*! TERRn - Transmit frame error count */ #define NETC_ETH_LINK_PM1_TERRN_TERRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TERRN_TERRn_SHIFT)) & NETC_ETH_LINK_PM1_TERRN_TERRn_MASK) /*! @} */ /*! @name PM1_TUCAN - Port MAC 1 Transmit Unicast Frame Counter Register(ifOutUcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TUCAN_TUCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TUCAN_TUCAn_SHIFT (0U) /*! TUCAn - Incremented for each valid frame transmitted(to the FIFO interface) in which bit 0 of the destination address was 0. */ #define NETC_ETH_LINK_PM1_TUCAN_TUCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TUCAN_TUCAn_SHIFT)) & NETC_ETH_LINK_PM1_TUCAN_TUCAn_MASK) /*! @} */ /*! @name PM1_TMCAN - Port MAC 1 Transmit Multicast Frame Counter Register(ifOutMulticastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TMCAN_TMCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TMCAN_TMCAn_SHIFT (0U) #define NETC_ETH_LINK_PM1_TMCAN_TMCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TMCAN_TMCAn_SHIFT)) & NETC_ETH_LINK_PM1_TMCAN_TMCAn_MASK) /*! @} */ /*! @name PM1_TBCAN - Port MAC 1 Transmit Broadcast Frame Counter Register(ifOutBroadcastPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TBCAN_TBCAn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TBCAN_TBCAn_SHIFT (0U) /*! TBCAn - Incremented for each valid frame transmitted(to the FIFO interface) in which all bits of * the destination address were 1 . */ #define NETC_ETH_LINK_PM1_TBCAN_TBCAn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TBCAN_TBCAn_SHIFT)) & NETC_ETH_LINK_PM1_TBCAN_TBCAn_MASK) /*! @} */ /*! @name PM1_TPKTN - Port MAC 1 Transmit Packets Counter Register(etherStatsPktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TPKTN_TPKTn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TPKTN_TPKTn_SHIFT (0U) /*! TPKTn - Incremented for each good or bad packet transmitted. */ #define NETC_ETH_LINK_PM1_TPKTN_TPKTn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TPKTN_TPKTn_SHIFT)) & NETC_ETH_LINK_PM1_TPKTN_TPKTn_MASK) /*! @} */ /*! @name PM1_TUNDN - Port MAC 1 Transmit Undersized Packet Counter Register(etherStatsUndersizePktsn) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TUNDN_TUNDn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TUNDN_TUNDn_SHIFT (0U) /*! TUNDn - Incremented for each packet transmitted that was less than 64 octets long with a good CRC. */ #define NETC_ETH_LINK_PM1_TUNDN_TUNDn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TUNDN_TUNDn_SHIFT)) & NETC_ETH_LINK_PM1_TUNDN_TUNDn_MASK) /*! @} */ /*! @name PM1_T64N - Port MAC 1 Transmit 64-Octet Packet Counter Register (etherStatsPkts64OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_T64N_T64n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_T64N_T64n_SHIFT (0U) /*! T64n - Incremented for each 64-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM1_T64N_T64n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T64N_T64n_SHIFT)) & NETC_ETH_LINK_PM1_T64N_T64n_MASK) /*! @} */ /*! @name PM1_T127N - Port MAC 1 Transmit 65 to 127-Octet Packet Counter Register (etherStatsPkts65to127OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_T127N_T127n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_T127N_T127n_SHIFT (0U) /*! T127n - Incremented for each 65 to 127-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM1_T127N_T127n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T127N_T127n_SHIFT)) & NETC_ETH_LINK_PM1_T127N_T127n_MASK) /*! @} */ /*! @name PM1_T255N - Port MAC 1 Transmit 128 to 255-Octet Packet Counter Register (etherStatsPkts128to255OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_T255N_T255n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_T255N_T255n_SHIFT (0U) /*! T255n - Incremented for each 128 to 255-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM1_T255N_T255n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T255N_T255n_SHIFT)) & NETC_ETH_LINK_PM1_T255N_T255n_MASK) /*! @} */ /*! @name PM1_T511N - Port MAC 1 Transmit 256 to 511-Octet Packet Counter Register (etherStatsPkts256to511OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_T511N_T511n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_T511N_T511n_SHIFT (0U) /*! T511n - Incremented for each 256 to 511-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM1_T511N_T511n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T511N_T511n_SHIFT)) & NETC_ETH_LINK_PM1_T511N_T511n_MASK) /*! @} */ /*! @name PM1_T1023N - Port MAC 1 Transmit 512 to 1023-Octet Packet Counter Register (etherStatsPkts512to1023OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_T1023N_T1023n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_T1023N_T1023n_SHIFT (0U) /*! T1023n - Incremented for each 512 to 1023-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM1_T1023N_T1023n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T1023N_T1023n_SHIFT)) & NETC_ETH_LINK_PM1_T1023N_T1023n_MASK) /*! @} */ /*! @name PM1_T1522N - Port MAC 1 Transmit 1024 to 1522-Octet Packet Counter Register (etherStatsPkts1024to1522OctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_T1522N_T1522n_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_T1522N_T1522n_SHIFT (0U) /*! T1522n - Incremented for each 1024- to 1522-octet frame transmitted, good or bad. */ #define NETC_ETH_LINK_PM1_T1522N_T1522n(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T1522N_T1522n_SHIFT)) & NETC_ETH_LINK_PM1_T1522N_T1522n_MASK) /*! @} */ /*! @name PM1_T1523XN - Port MAC 1 Transmit 1523 to TX_MTU-Octet Packet Counter Register (etherStatsPkts1523toMaxOctetsN) */ /*! @{ */ #define NETC_ETH_LINK_PM1_T1523XN_T1523Xn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_T1523XN_T1523Xn_SHIFT (0U) #define NETC_ETH_LINK_PM1_T1523XN_T1523Xn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_T1523XN_T1523Xn_SHIFT)) & NETC_ETH_LINK_PM1_T1523XN_T1523Xn_MASK) /*! @} */ /*! @name PM1_TCNPN - Port MAC 1 Transmit Control Packet Counter Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_TCNPN_TCNPn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TCNPN_TCNPn_SHIFT (0U) /*! TCNPn - Incremented for each valid control packet transmitted (type 0x8808) but not for PAUSE packets */ #define NETC_ETH_LINK_PM1_TCNPN_TCNPn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TCNPN_TCNPn_SHIFT)) & NETC_ETH_LINK_PM1_TCNPN_TCNPn_MASK) /*! @} */ /*! @name PM1_TDFRN - Port MAC 1 Transmit Deferred Packet Counter Register(aFramesWithDeferredXmissions) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TDFRN_TDFRn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TDFRN_TDFRn_SHIFT (0U) /*! TDFRn - Increments for successful transmissions, without retransmits, that were deferred (half-duplex only). */ #define NETC_ETH_LINK_PM1_TDFRN_TDFRn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TDFRN_TDFRn_SHIFT)) & NETC_ETH_LINK_PM1_TDFRN_TDFRn_MASK) /*! @} */ /*! @name PM1_TMCOLN - Port MAC 1 Transmit Multiple Collisions Counter Register(aMultipleCollisionFrames) */ /*! @{ */ #define NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_SHIFT (0U) /*! TMCOLn - Increments for successful transmission after more than one retransmission (half-duplex only). */ #define NETC_ETH_LINK_PM1_TMCOLN_TMCOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_SHIFT)) & NETC_ETH_LINK_PM1_TMCOLN_TMCOLn_MASK) /*! @} */ /*! @name PM1_TSCOLN - Port MAC 1 Transmit Single Collision Counter(aSingleCollisionFrames) Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_SHIFT (0U) /*! TSCOLn - Increments for successful transmission after one retransmission (half-duplex only). */ #define NETC_ETH_LINK_PM1_TSCOLN_TSCOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_SHIFT)) & NETC_ETH_LINK_PM1_TSCOLN_TSCOLn_MASK) /*! @} */ /*! @name PM1_TLCOLN - Port MAC 1 Transmit Late Collision Counter(aLateCollisions) Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_SHIFT (0U) /*! TLCOLn - Late collision occurred. Frame corrupted / discarded (half-duplex only) */ #define NETC_ETH_LINK_PM1_TLCOLN_TLCOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_SHIFT)) & NETC_ETH_LINK_PM1_TLCOLN_TLCOLn_MASK) /*! @} */ /*! @name PM1_TECOLN - Port MAC 1 Transmit Excessive Collisions Counter Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_TECOLN_TECOLn_MASK (0xFFFFFFFFFFFFFFFFU) #define NETC_ETH_LINK_PM1_TECOLN_TECOLn_SHIFT (0U) /*! TECOLn - Excessive collisions occurred. Frame was discarded (half-duplex only) */ #define NETC_ETH_LINK_PM1_TECOLN_TECOLn(x) (((uint64_t)(((uint64_t)(x)) << NETC_ETH_LINK_PM1_TECOLN_TECOLn_SHIFT)) & NETC_ETH_LINK_PM1_TECOLN_TECOLn_MASK) /*! @} */ /*! @name PM1_IF_MODE - Port MAC 1 Interface Mode Control Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_IF_MODE_IFMODE_MASK (0x7U) #define NETC_ETH_LINK_PM1_IF_MODE_IFMODE_SHIFT (0U) /*! IFMODE - Interface mode */ #define NETC_ETH_LINK_PM1_IF_MODE_IFMODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_IFMODE_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_IFMODE_MASK) #define NETC_ETH_LINK_PM1_IF_MODE_REVMII_MASK (0x8U) #define NETC_ETH_LINK_PM1_IF_MODE_REVMII_SHIFT (3U) /*! REVMII - Reverse Mode * 0b0..Reverse mode disabled - port is in MAC mode * 0b1..Reverse mode enabled - port is in PHY mode */ #define NETC_ETH_LINK_PM1_IF_MODE_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_REVMII_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_REVMII_MASK) #define NETC_ETH_LINK_PM1_IF_MODE_M10_MASK (0x10U) #define NETC_ETH_LINK_PM1_IF_MODE_M10_SHIFT (4U) /*! M10 * 0b0..100 Mbps * 0b1..10 Mbps */ #define NETC_ETH_LINK_PM1_IF_MODE_M10(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_M10_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_M10_MASK) #define NETC_ETH_LINK_PM1_IF_MODE_HD_MASK (0x40U) #define NETC_ETH_LINK_PM1_IF_MODE_HD_SHIFT (6U) /*! HD - Half-duplex * 0b0..full duplex * 0b1..half duplex */ #define NETC_ETH_LINK_PM1_IF_MODE_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_HD_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_HD_MASK) #define NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_MASK (0x1000U) #define NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_SHIFT (12U) /*! CLK_STOP - Clock Stop * 0b0..Not stoppable * 0b1..Stoppable */ #define NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_CLK_STOP_MASK) #define NETC_ETH_LINK_PM1_IF_MODE_SSP_MASK (0x6000U) #define NETC_ETH_LINK_PM1_IF_MODE_SSP_SHIFT (13U) /*! SSP - Set Speed * 0b00..100 Mbps * 0b01..10 Mbps * 0b10..1 Gbps * 0b11..reserved */ #define NETC_ETH_LINK_PM1_IF_MODE_SSP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_SSP_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_SSP_MASK) #define NETC_ETH_LINK_PM1_IF_MODE_ENA_MASK (0x8000U) #define NETC_ETH_LINK_PM1_IF_MODE_ENA_SHIFT (15U) /*! ENA - AN Enable * 0b0..SSP and HD fields determine the RGMII link speed and duplex mode * 0b1..RGMII Auto-Negotiation Enabled - PHY in-band status information is used to select the speed of operation and duplex mode. */ #define NETC_ETH_LINK_PM1_IF_MODE_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_MODE_ENA_SHIFT)) & NETC_ETH_LINK_PM1_IF_MODE_ENA_MASK) /*! @} */ /*! @name PM1_IF_STATUS - Port MAC 1 Interface Status Register */ /*! @{ */ #define NETC_ETH_LINK_PM1_IF_STATUS_RGFD_MASK (0x1000U) #define NETC_ETH_LINK_PM1_IF_STATUS_RGFD_SHIFT (12U) /*! RGFD - RGMII full duplex */ #define NETC_ETH_LINK_PM1_IF_STATUS_RGFD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_STATUS_RGFD_SHIFT)) & NETC_ETH_LINK_PM1_IF_STATUS_RGFD_MASK) #define NETC_ETH_LINK_PM1_IF_STATUS_RGSP_MASK (0x6000U) #define NETC_ETH_LINK_PM1_IF_STATUS_RGSP_SHIFT (13U) /*! RGSP - RGMII speed setting */ #define NETC_ETH_LINK_PM1_IF_STATUS_RGSP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_STATUS_RGSP_SHIFT)) & NETC_ETH_LINK_PM1_IF_STATUS_RGSP_MASK) #define NETC_ETH_LINK_PM1_IF_STATUS_RGLNK_MASK (0x8000U) #define NETC_ETH_LINK_PM1_IF_STATUS_RGLNK_SHIFT (15U) /*! RGLNK - RGMII link */ #define NETC_ETH_LINK_PM1_IF_STATUS_RGLNK(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PM1_IF_STATUS_RGLNK_SHIFT)) & NETC_ETH_LINK_PM1_IF_STATUS_RGLNK_MASK) /*! @} */ /*! @name MAC_MERGE_MMCSR - Port MAC Merge Control and Status Register */ /*! @{ */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_MASK (0x1U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_SHIFT (0U) /*! LPS - Local preemption supported */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LPS_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_MASK (0x2U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_SHIFT (1U) /*! LPE - Local preemption enabled */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LPE_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_MASK (0x4U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_SHIFT (2U) /*! LPA - Local preemption active */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_MASK (0x18U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_SHIFT (3U) /*! LAFS - Local additional fragment size */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LAFS_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_MASK (0x20U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_SHIFT (5U) /*! RPS - Remote preemption supported */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RPS_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_MASK (0x40U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_SHIFT (6U) /*! RPE - Remote preemption enabled */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RPE_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_MASK (0x80U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_SHIFT (7U) /*! RPA - Remote preemption active */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RPA_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_MASK (0x300U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_SHIFT (8U) /*! RAFS - Remote additional fragment size */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_MASK (0x18000U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_SHIFT (15U) /*! ME - Merge enabled */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_ME(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_MASK (0x20000U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_SHIFT (17U) /*! VDIS - Verify disabled */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_MASK (0x1C0000U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_SHIFT (18U) /*! VSTS - Verify status */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_MASK (0x600000U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_SHIFT (21U) /*! TXSTS - Merge status */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_MASK (0x3F800000U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_SHIFT (23U) /*! VT - Verify Time */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_VT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_MASK) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_MASK (0x80000000U) #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT (31U) /*! LINK_FAIL - Link Fail */ #define NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL_MASK) /*! @} */ /*! @name MAC_MERGE_MMFAECR - Port MAC Merge Frame Assembly Error Count Register */ /*! @{ */ #define NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_SHIFT (0U) #define NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFAECR_MMFAEC_MASK) /*! @} */ /*! @name MAC_MERGE_MMFSECR - Port MAC Merge Frame SMD Error Count Register */ /*! @{ */ #define NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_SHIFT (0U) #define NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFSECR_MMFSEC_MASK) /*! @} */ /*! @name MAC_MERGE_MMFAOCR - Port MAC Merge Frame Assembly OK Count Register */ /*! @{ */ #define NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT (0U) #define NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFAOCR_MMFAOC_MASK) /*! @} */ /*! @name MAC_MERGE_MMFCRXR - Port MAC Merge Fragment Count RX Register */ /*! @{ */ #define NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT (0U) #define NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFCRXR_MMFCRX_MASK) /*! @} */ /*! @name MAC_MERGE_MMFCTXR - Port MAC Merge Fragment Count TX Register */ /*! @{ */ #define NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT (0U) #define NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMFCTXR_MMFCTX_MASK) /*! @} */ /*! @name MAC_MERGE_MMHCR - Port MAC Merge Hold Count Register */ /*! @{ */ #define NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_MASK (0xFFFFFFFFU) #define NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_SHIFT (0U) #define NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_SHIFT)) & NETC_ETH_LINK_MAC_MERGE_MMHCR_MMHC_MASK) /*! @} */ /*! @name PEMDIOCR - Port external MDIO configuration register */ /*! @{ */ #define NETC_ETH_LINK_PEMDIOCR_BSY2_MASK (0x1U) #define NETC_ETH_LINK_PEMDIOCR_BSY2_SHIFT (0U) /*! BSY2 * 0b0..An MDIO transaction is not occurring; software may access other MDIO registers * 0b1..An MDIO transaction is occurring. */ #define NETC_ETH_LINK_PEMDIOCR_BSY2(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_BSY2_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_BSY2_MASK) #define NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_MASK (0x2U) #define NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_SHIFT (1U) /*! MDIO_RD_ER * 0b0..No error on last MDIO transaction (read or write). * 0b1..An error was detected on the last MDIO transaction (read or write). Errors on internal MDIO accesses can * be triggered by an access to an invalid device, or by a write to a shared on-die PHY device that has not * been locked. */ #define NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_MDIO_RD_ER_MASK) #define NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_MASK (0x1CU) #define NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_SHIFT (2U) /*! MDIO_HOLD * 0b000..1 NETC cycle * 0b001..3 NETC cycles * 0b010..5 NETC cycles (default - recommended value) * 0b011..7 NETC cycles * 0b100..9 NETC cycles * 0b101..11 NETC cycles * 0b110..13 NETC cycles * 0b111..15 NETC cycles */ #define NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_MDIO_HOLD_MASK) #define NETC_ETH_LINK_PEMDIOCR_PRE_DIS_MASK (0x20U) #define NETC_ETH_LINK_PEMDIOCR_PRE_DIS_SHIFT (5U) /*! PRE_DIS * 0b0..Generation of MDIO preamble is enabled (default operation) * 0b1..Generation of MDIO preamble is disabled. */ #define NETC_ETH_LINK_PEMDIOCR_PRE_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_PRE_DIS_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_PRE_DIS_MASK) #define NETC_ETH_LINK_PEMDIOCR_ENC45_MASK (0x40U) #define NETC_ETH_LINK_PEMDIOCR_ENC45_SHIFT (6U) /*! ENC45 * 0b0..Clause 22 transactions are used. * 0b1..Clause 45 transactions are used. */ #define NETC_ETH_LINK_PEMDIOCR_ENC45(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_ENC45_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_ENC45_MASK) #define NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_MASK (0xFF80U) #define NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_SHIFT (7U) /*! MDIO_CLK_DIV - MDIO Clock Divisor. */ #define NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_MDIO_CLK_DIV_MASK) #define NETC_ETH_LINK_PEMDIOCR_WHOAMI_MASK (0x70000U) #define NETC_ETH_LINK_PEMDIOCR_WHOAMI_SHIFT (16U) /*! WHOAMI - Returns the Link ID. */ #define NETC_ETH_LINK_PEMDIOCR_WHOAMI(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_WHOAMI_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_WHOAMI_MASK) #define NETC_ETH_LINK_PEMDIOCR_EHOLD_MASK (0x400000U) #define NETC_ETH_LINK_PEMDIOCR_EHOLD_SHIFT (22U) /*! EHOLD - Extended HOLD Select * 0b0..Normal Operation * 0b1..Extended operation. */ #define NETC_ETH_LINK_PEMDIOCR_EHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_EHOLD_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_EHOLD_MASK) #define NETC_ETH_LINK_PEMDIOCR_NEG_MASK (0x800000U) #define NETC_ETH_LINK_PEMDIOCR_NEG_SHIFT (23U) /*! NEG * 0b0..normal operation - positive edge. * 0b1..MDIO is driven by master on MDC negative edge (default for external MDIOs). */ #define NETC_ETH_LINK_PEMDIOCR_NEG(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_NEG_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_NEG_MASK) #define NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_MASK (0x10000000U) #define NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_SHIFT (28U) /*! ADDR_ERR * 0b0..Normal * 0b1..Error. An access control violation has occurred. The request address used does not match the MDIO PHY's * address (clause 22) or MDIO port address (clause 45) assigned. */ #define NETC_ETH_LINK_PEMDIOCR_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_ADDR_ERR_MASK) #define NETC_ETH_LINK_PEMDIOCR_CIM_MASK (0x20000000U) #define NETC_ETH_LINK_PEMDIOCR_CIM_SHIFT (29U) /*! CIM * 0b0..Masked * 0b1..Enabled */ #define NETC_ETH_LINK_PEMDIOCR_CIM(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_CIM_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_CIM_MASK) #define NETC_ETH_LINK_PEMDIOCR_CMP_MASK (0x40000000U) #define NETC_ETH_LINK_PEMDIOCR_CMP_SHIFT (30U) /*! CMP * 0b0..An MDIO command completion did not occur. * 0b1..An MDIO command completion occurred. */ #define NETC_ETH_LINK_PEMDIOCR_CMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_CMP_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_CMP_MASK) #define NETC_ETH_LINK_PEMDIOCR_BSY1_MASK (0x80000000U) #define NETC_ETH_LINK_PEMDIOCR_BSY1_SHIFT (31U) /*! BSY1 * 0b0..An MDIO transaction is not occurring; software may access other MDIO registers. * 0b1..An MDIO transaction is occurring. */ #define NETC_ETH_LINK_PEMDIOCR_BSY1(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOCR_BSY1_SHIFT)) & NETC_ETH_LINK_PEMDIOCR_BSY1_MASK) /*! @} */ /*! @name PEMDIOICR - Port external MDIO interface control register */ /*! @{ */ #define NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_MASK (0x1FU) #define NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_SHIFT (0U) /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */ #define NETC_ETH_LINK_PEMDIOICR_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_DEV_ADDR_MASK) #define NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_MASK (0x3E0U) #define NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_SHIFT (5U) /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */ #define NETC_ETH_LINK_PEMDIOICR_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_PORT_ADDR_MASK) #define NETC_ETH_LINK_PEMDIOICR_POST_INC_MASK (0x4000U) #define NETC_ETH_LINK_PEMDIOICR_POST_INC_SHIFT (14U) /*! POST_INC - MDIO read with address post-increment initiation. Self-clearing once transaction is complete. */ #define NETC_ETH_LINK_PEMDIOICR_POST_INC(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_POST_INC_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_POST_INC_MASK) #define NETC_ETH_LINK_PEMDIOICR_READ_MASK (0x8000U) #define NETC_ETH_LINK_PEMDIOICR_READ_SHIFT (15U) /*! READ - MDIO read initiation. */ #define NETC_ETH_LINK_PEMDIOICR_READ(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_READ_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_READ_MASK) #define NETC_ETH_LINK_PEMDIOICR_BSY_MASK (0x80000000U) #define NETC_ETH_LINK_PEMDIOICR_BSY_SHIFT (31U) /*! BSY - MDIO busy */ #define NETC_ETH_LINK_PEMDIOICR_BSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOICR_BSY_SHIFT)) & NETC_ETH_LINK_PEMDIOICR_BSY_MASK) /*! @} */ /*! @name PEMDIOIDR - Port external MDIO interface data register */ /*! @{ */ #define NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_MASK (0xFFFFU) #define NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_SHIFT (0U) /*! MDIO_DATA - 16-bit MDIO data. */ #define NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_SHIFT)) & NETC_ETH_LINK_PEMDIOIDR_MDIO_DATA_MASK) /*! @} */ /*! @name PEMDIORAR - Port external MDIO register address register */ /*! @{ */ #define NETC_ETH_LINK_PEMDIORAR_REGADDR_MASK (0xFFFFU) #define NETC_ETH_LINK_PEMDIORAR_REGADDR_SHIFT (0U) /*! REGADDR - MDIO PHY register address. */ #define NETC_ETH_LINK_PEMDIORAR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIORAR_REGADDR_SHIFT)) & NETC_ETH_LINK_PEMDIORAR_REGADDR_MASK) /*! @} */ /*! @name PEMDIOSR - Port external MDIO status register */ /*! @{ */ #define NETC_ETH_LINK_PEMDIOSR_BSY_MASK (0x1U) #define NETC_ETH_LINK_PEMDIOSR_BSY_SHIFT (0U) /*! BSY - Global MDIO busy */ #define NETC_ETH_LINK_PEMDIOSR_BSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_BSY_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_BSY_MASK) #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_MASK (0x1F00U) #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_SHIFT (8U) /*! WHT_LIST - PHY white list */ #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_WHT_LIST_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_WHT_LIST_MASK) #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_MASK (0x8000U) #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_SHIFT (15U) /*! WHT_LIST_ENA - PHY white list enable */ #define NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_WHT_LIST_ENA_MASK) #define NETC_ETH_LINK_PEMDIOSR_PORT_ID_MASK (0x70000U) #define NETC_ETH_LINK_PEMDIOSR_PORT_ID_SHIFT (16U) /*! PORT_ID - Port ID */ #define NETC_ETH_LINK_PEMDIOSR_PORT_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_PORT_ID_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_PORT_ID_MASK) #define NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_MASK (0x80000U) #define NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_SHIFT (19U) /*! REQ_TYPE - Port ID */ #define NETC_ETH_LINK_PEMDIOSR_REQ_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_SHIFT)) & NETC_ETH_LINK_PEMDIOSR_REQ_TYPE_MASK) /*! @} */ /*! @name PPSCR - PHY status configuration register */ /*! @{ */ #define NETC_ETH_LINK_PPSCR_BSY_MASK (0x1U) #define NETC_ETH_LINK_PPSCR_BSY_SHIFT (0U) /*! BSY - MDIO busy */ #define NETC_ETH_LINK_PPSCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCR_BSY_SHIFT)) & NETC_ETH_LINK_PPSCR_BSY_MASK) #define NETC_ETH_LINK_PPSCR_MDIO_RD_ER_MASK (0x2U) #define NETC_ETH_LINK_PPSCR_MDIO_RD_ER_SHIFT (1U) /*! MDIO_RD_ER - MDIO read error */ #define NETC_ETH_LINK_PPSCR_MDIO_RD_ER(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCR_MDIO_RD_ER_SHIFT)) & NETC_ETH_LINK_PPSCR_MDIO_RD_ER_MASK) #define NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_MASK (0xFFFF0000U) #define NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_SHIFT (16U) /*! STATUS_INTERVAL - PHY status read interval */ #define NETC_ETH_LINK_PPSCR_STATUS_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_SHIFT)) & NETC_ETH_LINK_PPSCR_STATUS_INTERVAL_MASK) /*! @} */ /*! @name PPSCTRLR - Port PHY status control register */ /*! @{ */ #define NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_MASK (0x1FU) #define NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_SHIFT (0U) /*! DEV_ADDR - 5-bit MDIO device address (Clause 45) / register address (Clause 22) */ #define NETC_ETH_LINK_PPSCTRLR_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_SHIFT)) & NETC_ETH_LINK_PPSCTRLR_DEV_ADDR_MASK) #define NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_MASK (0x3E0U) #define NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_SHIFT (5U) /*! PORT_ADDR - 5-bit MDIO port address (Clause 45) / PHY address (Clause 22) */ #define NETC_ETH_LINK_PPSCTRLR_PORT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_SHIFT)) & NETC_ETH_LINK_PPSCTRLR_PORT_ADDR_MASK) /*! @} */ /*! @name PPSDR - Port PHY status data register */ /*! @{ */ #define NETC_ETH_LINK_PPSDR_MDIO_DATA_MASK (0xFFFFU) #define NETC_ETH_LINK_PPSDR_MDIO_DATA_SHIFT (0U) /*! MDIO_DATA - 16-bit MDIO data */ #define NETC_ETH_LINK_PPSDR_MDIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSDR_MDIO_DATA_SHIFT)) & NETC_ETH_LINK_PPSDR_MDIO_DATA_MASK) #define NETC_ETH_LINK_PPSDR_CURR_CNT_MASK (0xFFFF0000U) #define NETC_ETH_LINK_PPSDR_CURR_CNT_SHIFT (16U) /*! CURR_CNT - Current count */ #define NETC_ETH_LINK_PPSDR_CURR_CNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSDR_CURR_CNT_SHIFT)) & NETC_ETH_LINK_PPSDR_CURR_CNT_MASK) /*! @} */ /*! @name PPSRAR - Port PHY status register address register */ /*! @{ */ #define NETC_ETH_LINK_PPSRAR_REGADDR_MASK (0xFFFFU) #define NETC_ETH_LINK_PPSRAR_REGADDR_SHIFT (0U) /*! REGADDR - MDIO PHY register address. Address of the register within the Clause 45 PHY device from which data is to be read. */ #define NETC_ETH_LINK_PPSRAR_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSRAR_REGADDR_SHIFT)) & NETC_ETH_LINK_PPSRAR_REGADDR_MASK) /*! @} */ /*! @name PPSER - Port PHY status event register */ /*! @{ */ #define NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_MASK (0xFFFFU) #define NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_SHIFT (0U) /*! STATUS_EVENT_HL - Status event high-to-low. Set to 1 if a 1->0 transition on a corresponding data bit has occurred. Write 1 to clear. */ #define NETC_ETH_LINK_PPSER_STATUS_EVENT_HL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_SHIFT)) & NETC_ETH_LINK_PPSER_STATUS_EVENT_HL_MASK) #define NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_MASK (0xFFFF0000U) #define NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_SHIFT (16U) /*! STATUS_EVENT_LH - Status event low-to-high. Set to 1 if a 0->1 transition on a corresponding data bit has occurred. Write 1 to clear. */ #define NETC_ETH_LINK_PPSER_STATUS_EVENT_LH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_SHIFT)) & NETC_ETH_LINK_PPSER_STATUS_EVENT_LH_MASK) /*! @} */ /*! @name PPSMR - Port PHY status mask register */ /*! @{ */ #define NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_MASK (0xFFFFU) #define NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_SHIFT (0U) /*! STATUS_MASK_HL - Status high-to-low mask. If set to 1, assert an interrupt if the corresponding event bit is set. */ #define NETC_ETH_LINK_PPSMR_STATUS_MASK_HL(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_SHIFT)) & NETC_ETH_LINK_PPSMR_STATUS_MASK_HL_MASK) #define NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_MASK (0xFFFF0000U) #define NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_SHIFT (16U) /*! STATUS_MASK_LH - Status mask low-to-high. If set to 1, assert an interrupt if the corresponding event bit is set. */ #define NETC_ETH_LINK_PPSMR_STATUS_MASK_LH(x) (((uint32_t)(((uint32_t)(x)) << NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_SHIFT)) & NETC_ETH_LINK_PPSMR_STATUS_MASK_LH_MASK) /*! @} */ /*! * @} */ /* end of group NETC_ETH_LINK_Register_Masks */ /* NETC_ETH_LINK - Peripheral instance base addresses */ /** Peripheral ENETC0_ETH_MAC_PORT base address */ #define ENETC0_ETH_MAC_PORT_BASE (0x4CC15000u) /** Peripheral ENETC0_ETH_MAC_PORT base pointer */ #define ENETC0_ETH_MAC_PORT ((NETC_ETH_LINK_Type *)ENETC0_ETH_MAC_PORT_BASE) /** Peripheral ENETC1_ETH_MAC_PORT base address */ #define ENETC1_ETH_MAC_PORT_BASE (0x4CC55000u) /** Peripheral ENETC1_ETH_MAC_PORT base pointer */ #define ENETC1_ETH_MAC_PORT ((NETC_ETH_LINK_Type *)ENETC1_ETH_MAC_PORT_BASE) /** Peripheral ENETC2_ETH_MAC_PORT base address */ #define ENETC2_ETH_MAC_PORT_BASE (0x4CC95000u) /** Peripheral ENETC2_ETH_MAC_PORT base pointer */ #define ENETC2_ETH_MAC_PORT ((NETC_ETH_LINK_Type *)ENETC2_ETH_MAC_PORT_BASE) /** Array initializer of NETC_ETH_LINK peripheral base addresses */ #define NETC_ETH_LINK_BASE_ADDRS { ENETC0_ETH_MAC_PORT_BASE, ENETC1_ETH_MAC_PORT_BASE, ENETC2_ETH_MAC_PORT_BASE } /** Array initializer of NETC_ETH_LINK peripheral base pointers */ #define NETC_ETH_LINK_BASE_PTRS { ENETC0_ETH_MAC_PORT, ENETC1_ETH_MAC_PORT, ENETC2_ETH_MAC_PORT } /*! * @} */ /* end of group NETC_ETH_LINK_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NETC_IERB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_IERB_Peripheral_Access_Layer NETC_IERB Peripheral Access Layer * @{ */ /** NETC_IERB - Register Layout Typedef */ typedef struct { __I uint32_t CAPR0; /**< Capability Register 0, offset: 0x0 */ __I uint32_t CAPR1; /**< Capability Register 1, offset: 0x4 */ __I uint32_t CAPR2; /**< Capability Register 2, offset: 0x8 */ __I uint32_t CAPR3; /**< Capability Register 3, offset: 0xC */ uint8_t RESERVED_0[16]; __I uint32_t CMCAPR; /**< Common Memory Capability Register, offset: 0x20 */ uint8_t RESERVED_1[12]; __I uint32_t ITTMCAPR; /**< Ingress Ternary Table Memory Capability Register, offset: 0x30 */ uint8_t RESERVED_2[76]; __IO uint32_t SMDTR; /**< Shared memory depletion threshold register, offset: 0x80 */ __IO uint32_t ERSMBAR; /**< ENETC receive shared memory buffer allotment register, offset: 0x84 */ uint8_t RESERVED_3[56]; struct { /* offset: 0xC0, array step: 0x8 */ __IO uint32_t HTAHPCR; /**< HTA 0 HP configuration register, array offset: 0xC0, array step: 0x8 */ __IO uint32_t HTALPCR; /**< HTA 0 LP configuration register, array offset: 0xC4, array step: 0x8 */ } HTA_NUM[1]; uint8_t RESERVED_4[56]; __IO uint32_t HBTMAR; /**< Hash bucket table memory allocation register, offset: 0x100 */ __IO uint32_t HBTCR; /**< Hash Bucket Table Configuration Register, offset: 0x104 */ uint8_t RESERVED_5[40]; __IO uint32_t ITTCR; /**< Ingress ternary table configuration register, offset: 0x130 */ uint8_t RESERVED_6[60]; __IO uint32_t NETCFLRCR; /**< NETC FLR configuration register, offset: 0x170 */ uint8_t RESERVED_7[4]; __IO uint32_t NETCCLKFR; /**< NETC clock period fractional register, offset: 0x178 */ __IO uint32_t NETCCLKCR; /**< NETC clock configuration register, offset: 0x17C */ __IO uint32_t SBCR; /**< System bus configuration register, offset: 0x180 */ __IO uint32_t SBOTCR; /**< System bus outstanding transaction control register, offset: 0x184 */ uint8_t RESERVED_8[8]; __IO uint32_t SGLTTR; /**< Stream gating lag time for timestamp refresh register, offset: 0x190 */ uint8_t RESERVED_9[108]; struct { /* offset: 0x200, array step: 0x10 */ uint8_t RESERVED_0[8]; __IO uint32_t RCMSICAR; /**< Root complex 0 MSI-X cache attribute register, array offset: 0x208, array step: 0x10 */ __IO uint32_t RCMSIAMQR; /**< Root complex 0 MSI access management qualifier register, array offset: 0x20C, array step: 0x10 */ } ARRAY_NUM_RC[1]; uint8_t RESERVED_10[260]; __I uint32_t EMDIOMCR; /**< EMDIO MSI-X configuration register, offset: 0x314 */ uint8_t RESERVED_11[8]; __IO uint32_t EMDIO_CFH_DIDVID; /**< EMDIO config header device ID and vendor ID register, offset: 0x320 */ __IO uint32_t EMDIO_CFH_SIDSVID; /**< EMDIO config header subsystem ID and subsystem vendor ID register, offset: 0x324 */ uint8_t RESERVED_12[28]; __IO uint32_t EMDIOFAUXR; /**< EMDIO function auxiliary register, offset: 0x344 */ __IO uint32_t EMDIOBLPR[2]; /**< EMDIO boot loader parameter register 0..EMDIO boot loader parameter register 1, array offset: 0x348, array step: 0x4 */ __IO uint32_t EMDIO_CFG; /**< EMDIO configuration register, offset: 0x350 */ uint8_t RESERVED_13[12]; __IO uint32_t EMDIORIDAR; /**< EMDIO RID assignment register, offset: 0x360 */ uint8_t RESERVED_14[156]; struct { /* offset: 0x400, array step: 0x64 */ uint8_t RESERVED_0[20]; __IO uint32_t TMCR; /**< Timer 0 MSI-X configuration register, array offset: 0x414, array step: 0x64 */ uint8_t RESERVED_1[8]; __IO uint32_t T_CFH_DIDVID; /**< Timer 0 config header device ID and vendor ID register, array offset: 0x420, array step: 0x64 */ __IO uint32_t T_CFH_SIDSVID; /**< Timer 0 config header subsystem ID and subsystem vendor ID register, array offset: 0x424, array step: 0x64 */ uint8_t RESERVED_2[28]; __IO uint32_t TFAUXR; /**< Timer 0 function auxiliary register, array offset: 0x444, array step: 0x64 */ __IO uint32_t TBLPR[2]; /**< Timer 0 boot loader parameter register 0..Timer 0 boot loader parameter register 1, array offset: 0x448, array step: index*0x64, index2*0x4 */ uint8_t RESERVED_3[16]; __IO uint32_t TRIDAR; /**< Timer 0 RID assignment register, array offset: 0x460, array step: 0x64 */ } NUM_TMR_ARRAY[1]; uint8_t RESERVED_15[924]; __I uint32_t TGSMCAPR; /**< Time gate scheduling memory capability register, offset: 0x800 */ __I uint32_t TGSM0MAPR; /**< Time gate scheduling memory 0 mapping register, offset: 0x804 */ __I uint32_t TGSM0CAPR; /**< Time gate scheduling memory 0 capability register, offset: 0x808 */ uint8_t RESERVED_16[2036]; __I uint32_t L0CAPR; /**< Link 0 capability register, offset: 0x1000 */ __I uint32_t L0MCAPR; /**< Link 0 MAC capability register, offset: 0x1004 */ __I uint32_t L0IOCAPR; /**< Link 0 I/O capability register, offset: 0x1008 */ uint8_t RESERVED_17[4]; __IO uint32_t L0BCR; /**< Link 0 binding configuration register, offset: 0x1010 */ uint8_t RESERVED_18[12]; __IO uint32_t L0E0MAR0; /**< Link 0 end 0 MAC address register 0, offset: 0x1020 */ __IO uint32_t L0E0MAR1; /**< Link 0 end 0 MAC address register 1, offset: 0x1024 */ uint8_t RESERVED_19[24]; __I uint32_t L1CAPR; /**< Link 1 capability register, offset: 0x1040 */ __I uint32_t L1MCAPR; /**< Link 1 MAC capability register, offset: 0x1044 */ __I uint32_t L1IOCAPR; /**< Link 1 I/O capability register, offset: 0x1048 */ uint8_t RESERVED_20[4]; __IO uint32_t L1BCR; /**< Link 1 binding configuration register, offset: 0x1050 */ uint8_t RESERVED_21[12]; __IO uint32_t L1E0MAR0; /**< Link 1 end 0 MAC address register 0, offset: 0x1060 */ __IO uint32_t L1E0MAR1; /**< Link 1 end 0 MAC address register 1, offset: 0x1064 */ uint8_t RESERVED_22[24]; __I uint32_t L2CAPR; /**< Link 2 capability register, offset: 0x1080 */ __I uint32_t L2MCAPR; /**< Link 2 MAC capability register, offset: 0x1084 */ __I uint32_t L2IOCAPR; /**< Link 2 I/O capability register, offset: 0x1088 */ uint8_t RESERVED_23[4]; __IO uint32_t L2BCR; /**< Link 2 binding configuration register, offset: 0x1090 */ uint8_t RESERVED_24[12]; __IO uint32_t L2E0MAR0; /**< Link 2 end 0 MAC address register 0, offset: 0x10A0 */ __IO uint32_t L2E0MAR1; /**< Link 2 end 0 MAC address register 1, offset: 0x10A4 */ uint8_t RESERVED_25[8024]; struct { /* offset: 0x3000, array step: 0x100 */ uint8_t RESERVED_0[4]; __I uint32_t EBCR1; /**< ENETC 0 binding configuration register 1..ENETC 2 binding configuration register 1, array offset: 0x3004, array step: 0x100 */ __I uint32_t EBCR2; /**< ENETC 0 binding configuration register 2..ENETC 2 binding configuration register 2, array offset: 0x3008, array step: 0x100 */ uint8_t RESERVED_1[4]; __IO uint32_t EVFRIDAR; /**< ENETC 0 VF RID assignment register..ENETC 2 VF RID assignment register, array offset: 0x3010, array step: 0x100 */ __IO uint32_t EMCR; /**< ENETC 0 MSI-X configuration register..ENETC 2 MSI-X configuration register, array offset: 0x3014, array step: 0x100 */ uint8_t RESERVED_2[8]; __IO uint32_t E_CFH_DIDVID; /**< ENETC 0 config header device ID and vendor ID register..ENETC 2 config header device ID and vendor ID register, array offset: 0x3020, array step: 0x100 */ __IO uint32_t E_CFH_SIDSVID; /**< ENETC 0 config header subsystem ID and subsystem vendor ID register..ENETC 2 config header subsystem ID and subsystem vendor ID register, array offset: 0x3024, array step: 0x100 */ __IO uint32_t E_CFC_VFDID; /**< ENETC 0 config capability VF device ID register..ENETC 2 config capability VF device ID register, array offset: 0x3028, array step: 0x100 */ uint8_t RESERVED_3[4]; __IO uint32_t EBCAR; /**< ENETC 0 buffer cache attribute register 0..ENETC 2 buffer cache attribute register 0, array offset: 0x3030, array step: 0x100 */ __IO uint32_t EMCAR; /**< ENETC 0 message cache attribute register..ENETC 2 message cache attribute register, array offset: 0x3034, array step: 0x100 */ __IO uint32_t ECAR; /**< ENETC 0 command cache attribute register..ENETC 2 command cache attribute register, array offset: 0x3038, array step: 0x100 */ uint8_t RESERVED_4[4]; __IO uint32_t EAMQR; /**< ENETC 0 access management qualifier register..ENETC 2 access management qualifier register, array offset: 0x3040, array step: 0x100 */ __IO uint32_t EFAUXR; /**< ENETC 0 function auxiliary register..ENETC 2 function auxiliary register, array offset: 0x3044, array step: 0x100 */ __IO uint32_t EBLPR[2]; /**< ENETC 0 boot loader parameter register 0..ENETC 2 boot loader parameter register 1, array offset: 0x3048, array step: index*0x100, index2*0x4 */ __IO uint32_t ERXMBER; /**< ENETC 0 receive memory buffer entitlement register..ENETC 2 receive memory buffer entitlement register, array offset: 0x3050, array step: 0x100 */ __IO uint32_t ERXMBLR; /**< ENETC 0 receive memory buffer limit register..ENETC 2 receive memory buffer limit register, array offset: 0x3054, array step: 0x100 */ uint8_t RESERVED_5[8]; __IO uint32_t ERIDAR; /**< ENETC 0 RID assignment register..ENETC 2 RID assignment register, array offset: 0x3060, array step: 0x100 */ uint8_t RESERVED_6[12]; __IO uint32_t ETXHPTBCR; /**< ENETC 0 transmit high priority tier byte credit register..ENETC 2 transmit high priority tier byte credit register, array offset: 0x3070, array step: 0x100 */ __IO uint32_t ETXLPTBCR; /**< ENETC 0 transmit low priority tier byte credit register..ENETC 2 transmit low priority tier byte credit register, array offset: 0x3074, array step: 0x100 */ uint8_t RESERVED_7[8]; __IO uint32_t EHTMAR; /**< ENETC 0 hash table memory allotment register..ENETC 2 hash table memory allotment register, array offset: 0x3080, array step: 0x100 */ __IO uint32_t EITMAR; /**< ENETC 0 index table memory allocation register..ENETC 2 index table memory allocation register, array offset: 0x3084, array step: 0x100 */ __IO uint32_t EIPFTMAR; /**< ENETC 0 ingress port filter table memory allocation register..ENETC 2 ingress port filter table memory allocation register, array offset: 0x3088, array step: 0x100 */ uint8_t RESERVED_8[20]; __IO uint32_t ERPITMAR; /**< ENETC 0 rate policer index table memory allocation register..ENETC 2 rate policer index table memory allocation register, array offset: 0x30A0, array step: 0x100 */ __IO uint32_t EISCITMAR; /**< ENETC 0 ingress stream counter index table memory allocation register..ENETC 2 ingress stream counter index table memory allocation register, array offset: 0x30A4, array step: 0x100 */ __IO uint32_t EISITMAR; /**< ENETC 0 ingress stream index table memory allocation register..ENETC 2 ingress stream index table memory allocation register, array offset: 0x30A8, array step: 0x100 */ uint8_t RESERVED_9[8]; __IO uint32_t ESGIITMAR; /**< ENETC 0 stream gate instance index table memory allocation register..ENETC 2 stream gate instance index table memory allocation register, array offset: 0x30B4, array step: 0x100 */ __IO uint32_t ESGCLITMAR; /**< ENETC 0 stream gate control list index table memory allocation register..ENETC 2 stream gate control list index table memory allocation register, array offset: 0x30B8, array step: 0x100 */ uint8_t RESERVED_10[52]; __IO uint32_t ETGSTAR; /**< ENETC 0 time gate scheduling table allocation register..ENETC 2 time gate scheduling table allocation register, array offset: 0x30F0, array step: 0x100 */ __IO uint32_t ETGSLR; /**< ENETC 0 time gate scheduling lookahead register..ENETC 2 time gate scheduling lookahead register, array offset: 0x30F4, array step: 0x100 */ uint8_t RESERVED_11[8]; } CFG_ENETC_INST[3]; uint8_t RESERVED_26[3328]; struct { /* offset: 0x4000, array step: 0x40 */ __IO uint32_t VAMQR; /**< VSI 0 access management qualifier register..VSI 5 access management qualifier register, array offset: 0x4000, array step: 0x40 */ __IO uint32_t VFAUXR; /**< VSI 0 function auxiliary register..VSI 5 function auxiliary register, array offset: 0x4004, array step: 0x40 */ __IO uint32_t VBLPR[2]; /**< VSI 0 boot loader parameter register 0..VSI 5 boot loader parameter register 1, array offset: 0x4008, array step: index*0x40, index2*0x4 */ __IO uint32_t VPMAR0; /**< VSI 0 primary MAC address register 0..VSI 5 primary MAC address register 0, array offset: 0x4010, array step: 0x40 */ __IO uint32_t VPMAR1; /**< VSI 0 primary MAC address register 1..VSI 5 primary MAC address register 1, array offset: 0x4014, array step: 0x40 */ uint8_t RESERVED_0[40]; } CFG_VSI_INST[6]; } NETC_IERB_Type; /* ---------------------------------------------------------------------------- -- NETC_IERB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_IERB_Register_Masks NETC_IERB Register Masks * @{ */ /*! @name CAPR0 - Capability Register 0 */ /*! @{ */ #define NETC_IERB_CAPR0_NUM_EMDIO_MASK (0x10U) #define NETC_IERB_CAPR0_NUM_EMDIO_SHIFT (4U) #define NETC_IERB_CAPR0_NUM_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_EMDIO_SHIFT)) & NETC_IERB_CAPR0_NUM_EMDIO_MASK) #define NETC_IERB_CAPR0_NUM_TMR_MASK (0xC0U) #define NETC_IERB_CAPR0_NUM_TMR_SHIFT (6U) #define NETC_IERB_CAPR0_NUM_TMR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_TMR_SHIFT)) & NETC_IERB_CAPR0_NUM_TMR_MASK) #define NETC_IERB_CAPR0_NUM_LINKS_MASK (0x1F00U) #define NETC_IERB_CAPR0_NUM_LINKS_SHIFT (8U) #define NETC_IERB_CAPR0_NUM_LINKS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_LINKS_SHIFT)) & NETC_IERB_CAPR0_NUM_LINKS_MASK) #define NETC_IERB_CAPR0_NUM_SW_MASK (0x30000U) #define NETC_IERB_CAPR0_NUM_SW_SHIFT (16U) #define NETC_IERB_CAPR0_NUM_SW(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_SW_SHIFT)) & NETC_IERB_CAPR0_NUM_SW_MASK) #define NETC_IERB_CAPR0_NUM_ENETC_MASK (0xF80000U) #define NETC_IERB_CAPR0_NUM_ENETC_SHIFT (19U) #define NETC_IERB_CAPR0_NUM_ENETC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_ENETC_SHIFT)) & NETC_IERB_CAPR0_NUM_ENETC_MASK) #define NETC_IERB_CAPR0_NUM_VSI_MASK (0x7F000000U) #define NETC_IERB_CAPR0_NUM_VSI_SHIFT (24U) #define NETC_IERB_CAPR0_NUM_VSI(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_VSI_SHIFT)) & NETC_IERB_CAPR0_NUM_VSI_MASK) /*! @} */ /*! @name CAPR1 - Capability Register 1 */ /*! @{ */ #define NETC_IERB_CAPR1_NUM_RX_BDR_MASK (0x3FFU) #define NETC_IERB_CAPR1_NUM_RX_BDR_SHIFT (0U) #define NETC_IERB_CAPR1_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR1_NUM_RX_BDR_SHIFT)) & NETC_IERB_CAPR1_NUM_RX_BDR_MASK) #define NETC_IERB_CAPR1_NUM_TX_BDR_MASK (0x3FF0000U) #define NETC_IERB_CAPR1_NUM_TX_BDR_SHIFT (16U) #define NETC_IERB_CAPR1_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR1_NUM_TX_BDR_SHIFT)) & NETC_IERB_CAPR1_NUM_TX_BDR_MASK) /*! @} */ /*! @name CAPR2 - Capability Register 2 */ /*! @{ */ #define NETC_IERB_CAPR2_NUM_MSIX_MASK (0x7FFU) #define NETC_IERB_CAPR2_NUM_MSIX_SHIFT (0U) #define NETC_IERB_CAPR2_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR2_NUM_MSIX_SHIFT)) & NETC_IERB_CAPR2_NUM_MSIX_MASK) /*! @} */ /*! @name CAPR3 - Capability Register 3 */ /*! @{ */ #define NETC_IERB_CAPR3_NUM_MAC_AFTE_MASK (0xFFFU) #define NETC_IERB_CAPR3_NUM_MAC_AFTE_SHIFT (0U) #define NETC_IERB_CAPR3_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR3_NUM_MAC_AFTE_SHIFT)) & NETC_IERB_CAPR3_NUM_MAC_AFTE_MASK) #define NETC_IERB_CAPR3_NUM_VLAN_FTE_MASK (0xFFF0000U) #define NETC_IERB_CAPR3_NUM_VLAN_FTE_SHIFT (16U) #define NETC_IERB_CAPR3_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR3_NUM_VLAN_FTE_SHIFT)) & NETC_IERB_CAPR3_NUM_VLAN_FTE_MASK) /*! @} */ /*! @name CMCAPR - Common Memory Capability Register */ /*! @{ */ #define NETC_IERB_CMCAPR_NUM_WORDS_MASK (0xFFFFFFU) #define NETC_IERB_CMCAPR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_CMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_CMCAPR_NUM_WORDS_MASK) #define NETC_IERB_CMCAPR_WORD_SIZE_MASK (0x30000000U) #define NETC_IERB_CMCAPR_WORD_SIZE_SHIFT (28U) #define NETC_IERB_CMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CMCAPR_WORD_SIZE_SHIFT)) & NETC_IERB_CMCAPR_WORD_SIZE_MASK) /*! @} */ /*! @name ITTMCAPR - Ingress Ternary Table Memory Capability Register */ /*! @{ */ #define NETC_IERB_ITTMCAPR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_ITTMCAPR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_ITTMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ITTMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_ITTMCAPR_NUM_WORDS_MASK) #define NETC_IERB_ITTMCAPR_WORD_SIZE_MASK (0x30000000U) #define NETC_IERB_ITTMCAPR_WORD_SIZE_SHIFT (28U) #define NETC_IERB_ITTMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ITTMCAPR_WORD_SIZE_SHIFT)) & NETC_IERB_ITTMCAPR_WORD_SIZE_MASK) /*! @} */ /*! @name SMDTR - Shared memory depletion threshold register */ /*! @{ */ #define NETC_IERB_SMDTR_THRESH_MASK (0xFFFFFFU) #define NETC_IERB_SMDTR_THRESH_SHIFT (0U) #define NETC_IERB_SMDTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SMDTR_THRESH_SHIFT)) & NETC_IERB_SMDTR_THRESH_MASK) /*! @} */ /*! @name ERSMBAR - ENETC receive shared memory buffer allotment register */ /*! @{ */ #define NETC_IERB_ERSMBAR_THRESH_MASK (0xFFFFFFU) #define NETC_IERB_ERSMBAR_THRESH_SHIFT (0U) #define NETC_IERB_ERSMBAR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERSMBAR_THRESH_SHIFT)) & NETC_IERB_ERSMBAR_THRESH_MASK) /*! @} */ /*! @name HTAHPCR - HTA 0 HP configuration register */ /*! @{ */ #define NETC_IERB_HTAHPCR_BLIMIT_MASK (0xFFFFU) #define NETC_IERB_HTAHPCR_BLIMIT_SHIFT (0U) #define NETC_IERB_HTAHPCR_BLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTAHPCR_BLIMIT_SHIFT)) & NETC_IERB_HTAHPCR_BLIMIT_MASK) #define NETC_IERB_HTAHPCR_FLIMIT_MASK (0xFF000000U) #define NETC_IERB_HTAHPCR_FLIMIT_SHIFT (24U) #define NETC_IERB_HTAHPCR_FLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTAHPCR_FLIMIT_SHIFT)) & NETC_IERB_HTAHPCR_FLIMIT_MASK) /*! @} */ /* The count of NETC_IERB_HTAHPCR */ #define NETC_IERB_HTAHPCR_COUNT (1U) /*! @name HTALPCR - HTA 0 LP configuration register */ /*! @{ */ #define NETC_IERB_HTALPCR_BLIMIT_MASK (0xFFFFU) #define NETC_IERB_HTALPCR_BLIMIT_SHIFT (0U) #define NETC_IERB_HTALPCR_BLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTALPCR_BLIMIT_SHIFT)) & NETC_IERB_HTALPCR_BLIMIT_MASK) #define NETC_IERB_HTALPCR_FLIMIT_MASK (0xFF000000U) #define NETC_IERB_HTALPCR_FLIMIT_SHIFT (24U) #define NETC_IERB_HTALPCR_FLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTALPCR_FLIMIT_SHIFT)) & NETC_IERB_HTALPCR_FLIMIT_MASK) /*! @} */ /* The count of NETC_IERB_HTALPCR */ #define NETC_IERB_HTALPCR_COUNT (1U) /*! @name HBTMAR - Hash bucket table memory allocation register */ /*! @{ */ #define NETC_IERB_HBTMAR_NUM_WORDS_MASK (0x3FFFU) #define NETC_IERB_HBTMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_HBTMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_HBTMAR_NUM_WORDS_MASK) #define NETC_IERB_HBTMAR_MIN_WORDS_MASK (0xFF0000U) #define NETC_IERB_HBTMAR_MIN_WORDS_SHIFT (16U) #define NETC_IERB_HBTMAR_MIN_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_MIN_WORDS_SHIFT)) & NETC_IERB_HBTMAR_MIN_WORDS_MASK) #define NETC_IERB_HBTMAR_NEPW_MASK (0x7000000U) #define NETC_IERB_HBTMAR_NEPW_SHIFT (24U) #define NETC_IERB_HBTMAR_NEPW(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_NEPW_SHIFT)) & NETC_IERB_HBTMAR_NEPW_MASK) #define NETC_IERB_HBTMAR_MLOC_MASK (0xC0000000U) #define NETC_IERB_HBTMAR_MLOC_SHIFT (30U) #define NETC_IERB_HBTMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_MLOC_SHIFT)) & NETC_IERB_HBTMAR_MLOC_MASK) /*! @} */ /*! @name HBTCR - Hash Bucket Table Configuration Register */ /*! @{ */ #define NETC_IERB_HBTCR_MAX_COL_MASK (0x7U) #define NETC_IERB_HBTCR_MAX_COL_SHIFT (0U) /*! MAX_COL - Maximum hash table collision chain length */ #define NETC_IERB_HBTCR_MAX_COL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTCR_MAX_COL_SHIFT)) & NETC_IERB_HBTCR_MAX_COL_MASK) #define NETC_IERB_HBTCR_MAX_VISITS_MASK (0xF0U) #define NETC_IERB_HBTCR_MAX_VISITS_SHIFT (4U) /*! MAX_VISITS - Maximum number of table entry visits */ #define NETC_IERB_HBTCR_MAX_VISITS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTCR_MAX_VISITS_SHIFT)) & NETC_IERB_HBTCR_MAX_VISITS_MASK) /*! @} */ /*! @name ITTCR - Ingress ternary table configuration register */ /*! @{ */ #define NETC_IERB_ITTCR_MAX_VISITS_MASK (0xFU) #define NETC_IERB_ITTCR_MAX_VISITS_SHIFT (0U) /*! MAX_VISITS - Maximum number of table entry visits */ #define NETC_IERB_ITTCR_MAX_VISITS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ITTCR_MAX_VISITS_SHIFT)) & NETC_IERB_ITTCR_MAX_VISITS_MASK) /*! @} */ /*! @name NETCFLRCR - NETC FLR configuration register */ /*! @{ */ #define NETC_IERB_NETCFLRCR_VALUE_MASK (0x1FFU) #define NETC_IERB_NETCFLRCR_VALUE_SHIFT (0U) #define NETC_IERB_NETCFLRCR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCFLRCR_VALUE_SHIFT)) & NETC_IERB_NETCFLRCR_VALUE_MASK) #define NETC_IERB_NETCFLRCR_SCALE_MASK (0xE00U) #define NETC_IERB_NETCFLRCR_SCALE_SHIFT (9U) /*! SCALE - Scale */ #define NETC_IERB_NETCFLRCR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCFLRCR_SCALE_SHIFT)) & NETC_IERB_NETCFLRCR_SCALE_MASK) /*! @} */ /*! @name NETCCLKFR - NETC clock period fractional register */ /*! @{ */ #define NETC_IERB_NETCCLKFR_FRAC_MASK (0xFFFFFFFFU) #define NETC_IERB_NETCCLKFR_FRAC_SHIFT (0U) #define NETC_IERB_NETCCLKFR_FRAC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKFR_FRAC_SHIFT)) & NETC_IERB_NETCCLKFR_FRAC_MASK) /*! @} */ /*! @name NETCCLKCR - NETC clock configuration register */ /*! @{ */ #define NETC_IERB_NETCCLKCR_FREQ_MASK (0x7FFU) #define NETC_IERB_NETCCLKCR_FREQ_SHIFT (0U) /*! FREQ - Frequency */ #define NETC_IERB_NETCCLKCR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKCR_FREQ_SHIFT)) & NETC_IERB_NETCCLKCR_FREQ_MASK) #define NETC_IERB_NETCCLKCR_PERIOD_MASK (0x3FF0000U) #define NETC_IERB_NETCCLKCR_PERIOD_SHIFT (16U) /*! PERIOD - Period */ #define NETC_IERB_NETCCLKCR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKCR_PERIOD_SHIFT)) & NETC_IERB_NETCCLKCR_PERIOD_MASK) /*! @} */ /*! @name SBCR - System bus configuration register */ /*! @{ */ #define NETC_IERB_SBCR_WBS_MASK (0x3U) #define NETC_IERB_SBCR_WBS_SHIFT (0U) /*! WBS - System Bus Maximum Write Burst Size. * 0b00..16B; AWLEN = 1 (2 data transfers) * 0b01..32B; AWLEN = 3 (4 data transfers) * 0b10..64B; AWLEN = 7 (8 data transfers) * 0b11..128B; AWLEN = 15 (16 data transfers) */ #define NETC_IERB_SBCR_WBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_WBS_SHIFT)) & NETC_IERB_SBCR_WBS_MASK) #define NETC_IERB_SBCR_RBS_MASK (0xCU) #define NETC_IERB_SBCR_RBS_SHIFT (2U) /*! RBS - System Bus Maximum Read Burst Size. * 0b00..16B; ARLEN = 1 (2 data transfers) * 0b01..32B; ARLEN = 3 (4 data transfers) * 0b10..64B; ARLEN = 7 (8 data transfers) * 0b11..128B; ARLEN = 15 (16 data transfers) */ #define NETC_IERB_SBCR_RBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_RBS_SHIFT)) & NETC_IERB_SBCR_RBS_MASK) /*! @} */ /*! @name SBOTCR - System bus outstanding transaction control register */ /*! @{ */ #define NETC_IERB_SBOTCR_OT_LIMIT_MASK (0xFFFFFFFFU) #define NETC_IERB_SBOTCR_OT_LIMIT_SHIFT (0U) #define NETC_IERB_SBOTCR_OT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBOTCR_OT_LIMIT_SHIFT)) & NETC_IERB_SBOTCR_OT_LIMIT_MASK) /*! @} */ /*! @name SGLTTR - Stream gating lag time for timestamp refresh register */ /*! @{ */ #define NETC_IERB_SGLTTR_LAG_TIME_MASK (0x1FU) #define NETC_IERB_SGLTTR_LAG_TIME_SHIFT (0U) #define NETC_IERB_SGLTTR_LAG_TIME(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SGLTTR_LAG_TIME_SHIFT)) & NETC_IERB_SGLTTR_LAG_TIME_MASK) /*! @} */ /*! @name RCMSICAR - Root complex 0 MSI-X cache attribute register */ /*! @{ */ #define NETC_IERB_RCMSICAR_MSI_WRCACHE_MASK (0xFU) #define NETC_IERB_RCMSICAR_MSI_WRCACHE_SHIFT (0U) #define NETC_IERB_RCMSICAR_MSI_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRCACHE_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRCACHE_MASK) #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN_MASK (0x30U) #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN_SHIFT (4U) #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRDOMAIN_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRDOMAIN_MASK) #define NETC_IERB_RCMSICAR_MSI_WRSNP_MASK (0xC0U) #define NETC_IERB_RCMSICAR_MSI_WRSNP_SHIFT (6U) #define NETC_IERB_RCMSICAR_MSI_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRSNP_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRSNP_MASK) /*! @} */ /* The count of NETC_IERB_RCMSICAR */ #define NETC_IERB_RCMSICAR_COUNT (1U) /*! @name RCMSIAMQR - Root complex 0 MSI access management qualifier register */ /*! @{ */ #define NETC_IERB_RCMSIAMQR_AWQOS_MASK (0xF00000U) #define NETC_IERB_RCMSIAMQR_AWQOS_SHIFT (20U) #define NETC_IERB_RCMSIAMQR_AWQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSIAMQR_AWQOS_SHIFT)) & NETC_IERB_RCMSIAMQR_AWQOS_MASK) /*! @} */ /* The count of NETC_IERB_RCMSIAMQR */ #define NETC_IERB_RCMSIAMQR_COUNT (1U) /*! @name EMDIOMCR - EMDIO MSI-X configuration register */ /*! @{ */ #define NETC_IERB_EMDIOMCR_NUM_MSIX_MASK (0x1U) #define NETC_IERB_EMDIOMCR_NUM_MSIX_SHIFT (0U) #define NETC_IERB_EMDIOMCR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOMCR_NUM_MSIX_SHIFT)) & NETC_IERB_EMDIOMCR_NUM_MSIX_MASK) /*! @} */ /*! @name EMDIO_CFH_DIDVID - EMDIO config header device ID and vendor ID register */ /*! @{ */ #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_SHIFT (0U) #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_MASK) #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_SHIFT (16U) #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_MASK) /*! @} */ /*! @name EMDIO_CFH_SIDSVID - EMDIO config header subsystem ID and subsystem vendor ID register */ /*! @{ */ #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) /*! @} */ /*! @name EMDIOFAUXR - EMDIO function auxiliary register */ /*! @{ */ #define NETC_IERB_EMDIOFAUXR_FAUX_MASK (0xFU) #define NETC_IERB_EMDIOFAUXR_FAUX_SHIFT (0U) /*! FAUX - Function Auxiliary Information */ #define NETC_IERB_EMDIOFAUXR_FAUX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOFAUXR_FAUX_SHIFT)) & NETC_IERB_EMDIOFAUXR_FAUX_MASK) /*! @} */ /*! @name EMDIOBLPR - EMDIO boot loader parameter register 0..EMDIO boot loader parameter register 1 */ /*! @{ */ #define NETC_IERB_EMDIOBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) #define NETC_IERB_EMDIOBLPR_PARAM_VAL_SHIFT (0U) #define NETC_IERB_EMDIOBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_EMDIOBLPR_PARAM_VAL_MASK) /*! @} */ /* The count of NETC_IERB_EMDIOBLPR */ #define NETC_IERB_EMDIOBLPR_COUNT (2U) /*! @name EMDIO_CFG - EMDIO configuration register */ /*! @{ */ #define NETC_IERB_EMDIO_CFG_MDIO_MODE_MASK (0x10U) #define NETC_IERB_EMDIO_CFG_MDIO_MODE_SHIFT (4U) #define NETC_IERB_EMDIO_CFG_MDIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFG_MDIO_MODE_SHIFT)) & NETC_IERB_EMDIO_CFG_MDIO_MODE_MASK) #define NETC_IERB_EMDIO_CFG_MDC_MODE_MASK (0x20U) #define NETC_IERB_EMDIO_CFG_MDC_MODE_SHIFT (5U) #define NETC_IERB_EMDIO_CFG_MDC_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFG_MDC_MODE_SHIFT)) & NETC_IERB_EMDIO_CFG_MDC_MODE_MASK) /*! @} */ /*! @name EMDIORIDAR - EMDIO RID assignment register */ /*! @{ */ #define NETC_IERB_EMDIORIDAR_RID_MASK (0xFFFFU) #define NETC_IERB_EMDIORIDAR_RID_SHIFT (0U) #define NETC_IERB_EMDIORIDAR_RID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIORIDAR_RID_SHIFT)) & NETC_IERB_EMDIORIDAR_RID_MASK) #define NETC_IERB_EMDIORIDAR_PBUS_MASK (0xFF0000U) #define NETC_IERB_EMDIORIDAR_PBUS_SHIFT (16U) #define NETC_IERB_EMDIORIDAR_PBUS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIORIDAR_PBUS_SHIFT)) & NETC_IERB_EMDIORIDAR_PBUS_MASK) /*! @} */ /*! @name TMCR - Timer 0 MSI-X configuration register */ /*! @{ */ #define NETC_IERB_TMCR_NUM_MSIX_MASK (0x1U) #define NETC_IERB_TMCR_NUM_MSIX_SHIFT (0U) #define NETC_IERB_TMCR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TMCR_NUM_MSIX_SHIFT)) & NETC_IERB_TMCR_NUM_MSIX_MASK) /*! @} */ /* The count of NETC_IERB_TMCR */ #define NETC_IERB_TMCR_COUNT (1U) /*! @name T_CFH_DIDVID - Timer 0 config header device ID and vendor ID register */ /*! @{ */ #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID_SHIFT (0U) #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_T_CFH_DIDVID_VENDOR_ID_MASK) #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID_SHIFT (16U) #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_T_CFH_DIDVID_DEVICE_ID_MASK) /*! @} */ /* The count of NETC_IERB_T_CFH_DIDVID */ #define NETC_IERB_T_CFH_DIDVID_COUNT (1U) /*! @name T_CFH_SIDSVID - Timer 0 config header subsystem ID and subsystem vendor ID register */ /*! @{ */ #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) /*! @} */ /* The count of NETC_IERB_T_CFH_SIDSVID */ #define NETC_IERB_T_CFH_SIDSVID_COUNT (1U) /*! @name TFAUXR - Timer 0 function auxiliary register */ /*! @{ */ #define NETC_IERB_TFAUXR_FAUX_MASK (0xFU) #define NETC_IERB_TFAUXR_FAUX_SHIFT (0U) /*! FAUX - Function Auxiliary Information */ #define NETC_IERB_TFAUXR_FAUX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TFAUXR_FAUX_SHIFT)) & NETC_IERB_TFAUXR_FAUX_MASK) /*! @} */ /* The count of NETC_IERB_TFAUXR */ #define NETC_IERB_TFAUXR_COUNT (1U) /*! @name TBLPR - Timer 0 boot loader parameter register 0..Timer 0 boot loader parameter register 1 */ /*! @{ */ #define NETC_IERB_TBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) #define NETC_IERB_TBLPR_PARAM_VAL_SHIFT (0U) #define NETC_IERB_TBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_TBLPR_PARAM_VAL_MASK) /*! @} */ /* The count of NETC_IERB_TBLPR */ #define NETC_IERB_TBLPR_COUNT (1U) /* The count of NETC_IERB_TBLPR */ #define NETC_IERB_TBLPR_COUNT2 (2U) /*! @name TRIDAR - Timer 0 RID assignment register */ /*! @{ */ #define NETC_IERB_TRIDAR_RID_MASK (0xFFFFU) #define NETC_IERB_TRIDAR_RID_SHIFT (0U) #define NETC_IERB_TRIDAR_RID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TRIDAR_RID_SHIFT)) & NETC_IERB_TRIDAR_RID_MASK) #define NETC_IERB_TRIDAR_PBUS_MASK (0xFF0000U) #define NETC_IERB_TRIDAR_PBUS_SHIFT (16U) #define NETC_IERB_TRIDAR_PBUS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TRIDAR_PBUS_SHIFT)) & NETC_IERB_TRIDAR_PBUS_MASK) /*! @} */ /* The count of NETC_IERB_TRIDAR */ #define NETC_IERB_TRIDAR_COUNT (1U) /*! @name TGSMCAPR - Time gate scheduling memory capability register */ /*! @{ */ #define NETC_IERB_TGSMCAPR_NUM_MEM_MASK (0xFU) #define NETC_IERB_TGSMCAPR_NUM_MEM_SHIFT (0U) #define NETC_IERB_TGSMCAPR_NUM_MEM(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TGSMCAPR_NUM_MEM_SHIFT)) & NETC_IERB_TGSMCAPR_NUM_MEM_MASK) /*! @} */ /*! @name TGSM0MAPR - Time gate scheduling memory 0 mapping register */ /*! @{ */ #define NETC_IERB_TGSM0MAPR_ENETCn_MASK (0xFFFF0000U) #define NETC_IERB_TGSM0MAPR_ENETCn_SHIFT (16U) /*! ENETCn * 0b0000000000000000..ENETC instance "n" is not a user of this time gate scheduling of memory. * 0b0000000000000001..ENETC instance "n" is a user of this time gate scheduling of memory. */ #define NETC_IERB_TGSM0MAPR_ENETCn(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TGSM0MAPR_ENETCn_SHIFT)) & NETC_IERB_TGSM0MAPR_ENETCn_MASK) /*! @} */ /*! @name TGSM0CAPR - Time gate scheduling memory 0 capability register */ /*! @{ */ #define NETC_IERB_TGSM0CAPR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_TGSM0CAPR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_TGSM0CAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TGSM0CAPR_NUM_WORDS_SHIFT)) & NETC_IERB_TGSM0CAPR_NUM_WORDS_MASK) /*! @} */ /*! @name L0CAPR - Link 0 capability register */ /*! @{ */ #define NETC_IERB_L0CAPR_LINK_TYPE_MASK (0x10U) #define NETC_IERB_L0CAPR_LINK_TYPE_SHIFT (4U) #define NETC_IERB_L0CAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L0CAPR_LINK_TYPE_MASK) #define NETC_IERB_L0CAPR_NUM_TC_MASK (0xF000U) #define NETC_IERB_L0CAPR_NUM_TC_SHIFT (12U) #define NETC_IERB_L0CAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_NUM_TC_SHIFT)) & NETC_IERB_L0CAPR_NUM_TC_MASK) #define NETC_IERB_L0CAPR_TGS_MASK (0x10000000U) #define NETC_IERB_L0CAPR_TGS_SHIFT (28U) /*! TGS - Time Gate Scheduling */ #define NETC_IERB_L0CAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_TGS_SHIFT)) & NETC_IERB_L0CAPR_TGS_MASK) #define NETC_IERB_L0CAPR_CBS_MASK (0x20000000U) #define NETC_IERB_L0CAPR_CBS_SHIFT (29U) /*! CBS - Credit Based Shaping */ #define NETC_IERB_L0CAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_CBS_SHIFT)) & NETC_IERB_L0CAPR_CBS_MASK) /*! @} */ /*! @name L0MCAPR - Link 0 MAC capability register */ /*! @{ */ #define NETC_IERB_L0MCAPR_MAC_VAR_MASK (0x7U) #define NETC_IERB_L0MCAPR_MAC_VAR_SHIFT (0U) /*! MAC_VAR - MAC Variant */ #define NETC_IERB_L0MCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L0MCAPR_MAC_VAR_MASK) #define NETC_IERB_L0MCAPR_EFPAD_MASK (0x30U) #define NETC_IERB_L0MCAPR_EFPAD_SHIFT (4U) /*! EFPAD - Egress frame padding capability */ #define NETC_IERB_L0MCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_EFPAD_SHIFT)) & NETC_IERB_L0MCAPR_EFPAD_MASK) #define NETC_IERB_L0MCAPR_HD_MASK (0x100U) #define NETC_IERB_L0MCAPR_HD_SHIFT (8U) /*! HD - Half Duplex capability */ #define NETC_IERB_L0MCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_HD_SHIFT)) & NETC_IERB_L0MCAPR_HD_MASK) #define NETC_IERB_L0MCAPR_FP_MASK (0x600U) #define NETC_IERB_L0MCAPR_FP_SHIFT (9U) /*! FP - Indicates if frame preemption is supported */ #define NETC_IERB_L0MCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_FP_SHIFT)) & NETC_IERB_L0MCAPR_FP_MASK) #define NETC_IERB_L0MCAPR_MII_PROT_MASK (0xF000000U) #define NETC_IERB_L0MCAPR_MII_PROT_SHIFT (24U) /*! MII_PROT - Indicates the MII protocol supported */ #define NETC_IERB_L0MCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L0MCAPR_MII_PROT_MASK) /*! @} */ /*! @name L0IOCAPR - Link 0 I/O capability register */ /*! @{ */ #define NETC_IERB_L0IOCAPR_PCS_PROT_MASK (0xFFFFU) #define NETC_IERB_L0IOCAPR_PCS_PROT_SHIFT (0U) /*! PCS_PROT - PCS protocols supported */ #define NETC_IERB_L0IOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L0IOCAPR_PCS_PROT_MASK) #define NETC_IERB_L0IOCAPR_IO_VAR_MASK (0xF000000U) #define NETC_IERB_L0IOCAPR_IO_VAR_SHIFT (24U) /*! IO_VAR - IO Variants supported */ #define NETC_IERB_L0IOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L0IOCAPR_IO_VAR_MASK) #define NETC_IERB_L0IOCAPR_REVMII_RATE_MASK (0x40000000U) #define NETC_IERB_L0IOCAPR_REVMII_RATE_SHIFT (30U) /*! REVMII_RATE - RevMII MII rate */ #define NETC_IERB_L0IOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L0IOCAPR_REVMII_RATE_MASK) #define NETC_IERB_L0IOCAPR_REVMII_MASK (0x80000000U) #define NETC_IERB_L0IOCAPR_REVMII_SHIFT (31U) /*! REVMII - Reverse Mode Device Configuration */ #define NETC_IERB_L0IOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_REVMII_SHIFT)) & NETC_IERB_L0IOCAPR_REVMII_MASK) /*! @} */ /*! @name L0BCR - Link 0 binding configuration register */ /*! @{ */ #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST_MASK (0x1FU) #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST_SHIFT (0U) #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L0BCR_SW_PORT_ENETC_INST_MASK) #define NETC_IERB_L0BCR_NETC_FUNC_MASK (0x40U) #define NETC_IERB_L0BCR_NETC_FUNC_SHIFT (6U) #define NETC_IERB_L0BCR_NETC_FUNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L0BCR_NETC_FUNC_MASK) #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_MASK (0x1F00U) #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_SHIFT (8U) #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_MASK) /*! @} */ /*! @name L0E0MAR0 - Link 0 end 0 MAC address register 0 */ /*! @{ */ #define NETC_IERB_L0E0MAR0_MAC_ADDR_MASK (0xFFFFFFFFU) #define NETC_IERB_L0E0MAR0_MAC_ADDR_SHIFT (0U) #define NETC_IERB_L0E0MAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L0E0MAR0_MAC_ADDR_MASK) /*! @} */ /*! @name L0E0MAR1 - Link 0 end 0 MAC address register 1 */ /*! @{ */ #define NETC_IERB_L0E0MAR1_MAC_ADDR_MASK (0xFFFFU) #define NETC_IERB_L0E0MAR1_MAC_ADDR_SHIFT (0U) #define NETC_IERB_L0E0MAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L0E0MAR1_MAC_ADDR_MASK) /*! @} */ /*! @name L1CAPR - Link 1 capability register */ /*! @{ */ #define NETC_IERB_L1CAPR_LINK_TYPE_MASK (0x10U) #define NETC_IERB_L1CAPR_LINK_TYPE_SHIFT (4U) #define NETC_IERB_L1CAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L1CAPR_LINK_TYPE_MASK) #define NETC_IERB_L1CAPR_NUM_TC_MASK (0xF000U) #define NETC_IERB_L1CAPR_NUM_TC_SHIFT (12U) #define NETC_IERB_L1CAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_NUM_TC_SHIFT)) & NETC_IERB_L1CAPR_NUM_TC_MASK) #define NETC_IERB_L1CAPR_TGS_MASK (0x10000000U) #define NETC_IERB_L1CAPR_TGS_SHIFT (28U) /*! TGS - Time Gate Scheduling */ #define NETC_IERB_L1CAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_TGS_SHIFT)) & NETC_IERB_L1CAPR_TGS_MASK) #define NETC_IERB_L1CAPR_CBS_MASK (0x20000000U) #define NETC_IERB_L1CAPR_CBS_SHIFT (29U) /*! CBS - Credit Based Shaping */ #define NETC_IERB_L1CAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_CBS_SHIFT)) & NETC_IERB_L1CAPR_CBS_MASK) /*! @} */ /*! @name L1MCAPR - Link 1 MAC capability register */ /*! @{ */ #define NETC_IERB_L1MCAPR_MAC_VAR_MASK (0x7U) #define NETC_IERB_L1MCAPR_MAC_VAR_SHIFT (0U) /*! MAC_VAR - MAC Variant */ #define NETC_IERB_L1MCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L1MCAPR_MAC_VAR_MASK) #define NETC_IERB_L1MCAPR_EFPAD_MASK (0x30U) #define NETC_IERB_L1MCAPR_EFPAD_SHIFT (4U) /*! EFPAD - Egress frame padding capability */ #define NETC_IERB_L1MCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_EFPAD_SHIFT)) & NETC_IERB_L1MCAPR_EFPAD_MASK) #define NETC_IERB_L1MCAPR_HD_MASK (0x100U) #define NETC_IERB_L1MCAPR_HD_SHIFT (8U) /*! HD - Half Duplex capability */ #define NETC_IERB_L1MCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_HD_SHIFT)) & NETC_IERB_L1MCAPR_HD_MASK) #define NETC_IERB_L1MCAPR_FP_MASK (0x600U) #define NETC_IERB_L1MCAPR_FP_SHIFT (9U) /*! FP - Indicates if frame preemption is supported */ #define NETC_IERB_L1MCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_FP_SHIFT)) & NETC_IERB_L1MCAPR_FP_MASK) #define NETC_IERB_L1MCAPR_MII_PROT_MASK (0xF000000U) #define NETC_IERB_L1MCAPR_MII_PROT_SHIFT (24U) /*! MII_PROT - Indicates the MII protocol supported */ #define NETC_IERB_L1MCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L1MCAPR_MII_PROT_MASK) /*! @} */ /*! @name L1IOCAPR - Link 1 I/O capability register */ /*! @{ */ #define NETC_IERB_L1IOCAPR_PCS_PROT_MASK (0xFFFFU) #define NETC_IERB_L1IOCAPR_PCS_PROT_SHIFT (0U) /*! PCS_PROT - PCS protocols supported */ #define NETC_IERB_L1IOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L1IOCAPR_PCS_PROT_MASK) #define NETC_IERB_L1IOCAPR_IO_VAR_MASK (0xF000000U) #define NETC_IERB_L1IOCAPR_IO_VAR_SHIFT (24U) /*! IO_VAR - IO Variants supported */ #define NETC_IERB_L1IOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L1IOCAPR_IO_VAR_MASK) #define NETC_IERB_L1IOCAPR_REVMII_RATE_MASK (0x40000000U) #define NETC_IERB_L1IOCAPR_REVMII_RATE_SHIFT (30U) /*! REVMII_RATE - RevMII MII rate */ #define NETC_IERB_L1IOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L1IOCAPR_REVMII_RATE_MASK) #define NETC_IERB_L1IOCAPR_REVMII_MASK (0x80000000U) #define NETC_IERB_L1IOCAPR_REVMII_SHIFT (31U) /*! REVMII - Reverse Mode Device Configuration */ #define NETC_IERB_L1IOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_REVMII_SHIFT)) & NETC_IERB_L1IOCAPR_REVMII_MASK) /*! @} */ /*! @name L1BCR - Link 1 binding configuration register */ /*! @{ */ #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST_MASK (0x1FU) #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST_SHIFT (0U) #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L1BCR_SW_PORT_ENETC_INST_MASK) #define NETC_IERB_L1BCR_NETC_FUNC_MASK (0x40U) #define NETC_IERB_L1BCR_NETC_FUNC_SHIFT (6U) #define NETC_IERB_L1BCR_NETC_FUNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L1BCR_NETC_FUNC_MASK) #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_MASK (0x1F00U) #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_SHIFT (8U) #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_MASK) /*! @} */ /*! @name L1E0MAR0 - Link 1 end 0 MAC address register 0 */ /*! @{ */ #define NETC_IERB_L1E0MAR0_MAC_ADDR_MASK (0xFFFFFFFFU) #define NETC_IERB_L1E0MAR0_MAC_ADDR_SHIFT (0U) #define NETC_IERB_L1E0MAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L1E0MAR0_MAC_ADDR_MASK) /*! @} */ /*! @name L1E0MAR1 - Link 1 end 0 MAC address register 1 */ /*! @{ */ #define NETC_IERB_L1E0MAR1_MAC_ADDR_MASK (0xFFFFU) #define NETC_IERB_L1E0MAR1_MAC_ADDR_SHIFT (0U) #define NETC_IERB_L1E0MAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L1E0MAR1_MAC_ADDR_MASK) /*! @} */ /*! @name L2CAPR - Link 2 capability register */ /*! @{ */ #define NETC_IERB_L2CAPR_LINK_TYPE_MASK (0x10U) #define NETC_IERB_L2CAPR_LINK_TYPE_SHIFT (4U) #define NETC_IERB_L2CAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L2CAPR_LINK_TYPE_MASK) #define NETC_IERB_L2CAPR_NUM_TC_MASK (0xF000U) #define NETC_IERB_L2CAPR_NUM_TC_SHIFT (12U) #define NETC_IERB_L2CAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_NUM_TC_SHIFT)) & NETC_IERB_L2CAPR_NUM_TC_MASK) #define NETC_IERB_L2CAPR_TGS_MASK (0x10000000U) #define NETC_IERB_L2CAPR_TGS_SHIFT (28U) /*! TGS - Time Gate Scheduling */ #define NETC_IERB_L2CAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_TGS_SHIFT)) & NETC_IERB_L2CAPR_TGS_MASK) #define NETC_IERB_L2CAPR_CBS_MASK (0x20000000U) #define NETC_IERB_L2CAPR_CBS_SHIFT (29U) /*! CBS - Credit Based Shaping */ #define NETC_IERB_L2CAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_CBS_SHIFT)) & NETC_IERB_L2CAPR_CBS_MASK) /*! @} */ /*! @name L2MCAPR - Link 2 MAC capability register */ /*! @{ */ #define NETC_IERB_L2MCAPR_MAC_VAR_MASK (0x7U) #define NETC_IERB_L2MCAPR_MAC_VAR_SHIFT (0U) /*! MAC_VAR - MAC Variant */ #define NETC_IERB_L2MCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L2MCAPR_MAC_VAR_MASK) #define NETC_IERB_L2MCAPR_EFPAD_MASK (0x30U) #define NETC_IERB_L2MCAPR_EFPAD_SHIFT (4U) /*! EFPAD - Egress frame padding capability */ #define NETC_IERB_L2MCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_EFPAD_SHIFT)) & NETC_IERB_L2MCAPR_EFPAD_MASK) #define NETC_IERB_L2MCAPR_HD_MASK (0x100U) #define NETC_IERB_L2MCAPR_HD_SHIFT (8U) /*! HD - Half Duplex capability */ #define NETC_IERB_L2MCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_HD_SHIFT)) & NETC_IERB_L2MCAPR_HD_MASK) #define NETC_IERB_L2MCAPR_FP_MASK (0x600U) #define NETC_IERB_L2MCAPR_FP_SHIFT (9U) /*! FP - Indicates if frame preemption is supported */ #define NETC_IERB_L2MCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_FP_SHIFT)) & NETC_IERB_L2MCAPR_FP_MASK) #define NETC_IERB_L2MCAPR_MII_PROT_MASK (0xF000000U) #define NETC_IERB_L2MCAPR_MII_PROT_SHIFT (24U) /*! MII_PROT - Indicates the MII protocol supported */ #define NETC_IERB_L2MCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L2MCAPR_MII_PROT_MASK) /*! @} */ /*! @name L2IOCAPR - Link 2 I/O capability register */ /*! @{ */ #define NETC_IERB_L2IOCAPR_PCS_PROT_MASK (0xFFFFU) #define NETC_IERB_L2IOCAPR_PCS_PROT_SHIFT (0U) /*! PCS_PROT - PCS protocols supported */ #define NETC_IERB_L2IOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L2IOCAPR_PCS_PROT_MASK) #define NETC_IERB_L2IOCAPR_IO_VAR_MASK (0xF000000U) #define NETC_IERB_L2IOCAPR_IO_VAR_SHIFT (24U) /*! IO_VAR - IO Variants supported */ #define NETC_IERB_L2IOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L2IOCAPR_IO_VAR_MASK) #define NETC_IERB_L2IOCAPR_REVMII_RATE_MASK (0x40000000U) #define NETC_IERB_L2IOCAPR_REVMII_RATE_SHIFT (30U) /*! REVMII_RATE - RevMII MII rate */ #define NETC_IERB_L2IOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L2IOCAPR_REVMII_RATE_MASK) #define NETC_IERB_L2IOCAPR_REVMII_MASK (0x80000000U) #define NETC_IERB_L2IOCAPR_REVMII_SHIFT (31U) /*! REVMII - Reverse Mode Device Configuration */ #define NETC_IERB_L2IOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2IOCAPR_REVMII_SHIFT)) & NETC_IERB_L2IOCAPR_REVMII_MASK) /*! @} */ /*! @name L2BCR - Link 2 binding configuration register */ /*! @{ */ #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST_MASK (0x1FU) #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST_SHIFT (0U) #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L2BCR_SW_PORT_ENETC_INST_MASK) #define NETC_IERB_L2BCR_NETC_FUNC_MASK (0x40U) #define NETC_IERB_L2BCR_NETC_FUNC_SHIFT (6U) #define NETC_IERB_L2BCR_NETC_FUNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L2BCR_NETC_FUNC_MASK) #define NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_MASK (0x1F00U) #define NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_SHIFT (8U) #define NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L2BCR_MDIO_PHYAD_PRTAD_MASK) /*! @} */ /*! @name L2E0MAR0 - Link 2 end 0 MAC address register 0 */ /*! @{ */ #define NETC_IERB_L2E0MAR0_MAC_ADDR_MASK (0xFFFFFFFFU) #define NETC_IERB_L2E0MAR0_MAC_ADDR_SHIFT (0U) #define NETC_IERB_L2E0MAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L2E0MAR0_MAC_ADDR_MASK) /*! @} */ /*! @name L2E0MAR1 - Link 2 end 0 MAC address register 1 */ /*! @{ */ #define NETC_IERB_L2E0MAR1_MAC_ADDR_MASK (0xFFFFU) #define NETC_IERB_L2E0MAR1_MAC_ADDR_SHIFT (0U) #define NETC_IERB_L2E0MAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L2E0MAR1_MAC_ADDR_MASK) /*! @} */ /*! @name EBCR1 - ENETC 0 binding configuration register 1..ENETC 2 binding configuration register 1 */ /*! @{ */ #define NETC_IERB_EBCR1_NUM_RX_BDR_MASK (0x3FFU) #define NETC_IERB_EBCR1_NUM_RX_BDR_SHIFT (0U) #define NETC_IERB_EBCR1_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR1_NUM_RX_BDR_SHIFT)) & NETC_IERB_EBCR1_NUM_RX_BDR_MASK) #define NETC_IERB_EBCR1_NUM_TX_BDR_MASK (0x3FF0000U) #define NETC_IERB_EBCR1_NUM_TX_BDR_SHIFT (16U) #define NETC_IERB_EBCR1_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR1_NUM_TX_BDR_SHIFT)) & NETC_IERB_EBCR1_NUM_TX_BDR_MASK) /*! @} */ /* The count of NETC_IERB_EBCR1 */ #define NETC_IERB_EBCR1_COUNT (3U) /*! @name EBCR2 - ENETC 0 binding configuration register 2..ENETC 2 binding configuration register 2 */ /*! @{ */ #define NETC_IERB_EBCR2_NUM_MAC_AFTE_MASK (0xFFFU) #define NETC_IERB_EBCR2_NUM_MAC_AFTE_SHIFT (0U) #define NETC_IERB_EBCR2_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR2_NUM_MAC_AFTE_SHIFT)) & NETC_IERB_EBCR2_NUM_MAC_AFTE_MASK) #define NETC_IERB_EBCR2_NUM_VLAN_FTE_MASK (0xFFF0000U) #define NETC_IERB_EBCR2_NUM_VLAN_FTE_SHIFT (16U) #define NETC_IERB_EBCR2_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR2_NUM_VLAN_FTE_SHIFT)) & NETC_IERB_EBCR2_NUM_VLAN_FTE_MASK) /*! @} */ /* The count of NETC_IERB_EBCR2 */ #define NETC_IERB_EBCR2_COUNT (3U) /*! @name EVFRIDAR - ENETC 0 VF RID assignment register..ENETC 2 VF RID assignment register */ /*! @{ */ #define NETC_IERB_EVFRIDAR_NUM_VF_MASK (0xFU) #define NETC_IERB_EVFRIDAR_NUM_VF_SHIFT (0U) #define NETC_IERB_EVFRIDAR_NUM_VF(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EVFRIDAR_NUM_VF_SHIFT)) & NETC_IERB_EVFRIDAR_NUM_VF_MASK) #define NETC_IERB_EVFRIDAR_STRIDE_MASK (0x300U) #define NETC_IERB_EVFRIDAR_STRIDE_SHIFT (8U) #define NETC_IERB_EVFRIDAR_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EVFRIDAR_STRIDE_SHIFT)) & NETC_IERB_EVFRIDAR_STRIDE_MASK) #define NETC_IERB_EVFRIDAR_OFFSET_MASK (0xFFFF0000U) #define NETC_IERB_EVFRIDAR_OFFSET_SHIFT (16U) #define NETC_IERB_EVFRIDAR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EVFRIDAR_OFFSET_SHIFT)) & NETC_IERB_EVFRIDAR_OFFSET_MASK) /*! @} */ /* The count of NETC_IERB_EVFRIDAR */ #define NETC_IERB_EVFRIDAR_COUNT (3U) /*! @name EMCR - ENETC 0 MSI-X configuration register..ENETC 2 MSI-X configuration register */ /*! @{ */ #define NETC_IERB_EMCR_NUM_MSIX_MASK (0x7FFU) #define NETC_IERB_EMCR_NUM_MSIX_SHIFT (0U) #define NETC_IERB_EMCR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCR_NUM_MSIX_SHIFT)) & NETC_IERB_EMCR_NUM_MSIX_MASK) /*! @} */ /* The count of NETC_IERB_EMCR */ #define NETC_IERB_EMCR_COUNT (3U) /*! @name E_CFH_DIDVID - ENETC 0 config header device ID and vendor ID register..ENETC 2 config header device ID and vendor ID register */ /*! @{ */ #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID_SHIFT (0U) #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_E_CFH_DIDVID_VENDOR_ID_MASK) #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID_SHIFT (16U) #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFH_DIDVID_DEVICE_ID_MASK) /*! @} */ /* The count of NETC_IERB_E_CFH_DIDVID */ #define NETC_IERB_E_CFH_DIDVID_COUNT (3U) /*! @name E_CFH_SIDSVID - ENETC 0 config header subsystem ID and subsystem vendor ID register..ENETC 2 config header subsystem ID and subsystem vendor ID register */ /*! @{ */ #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) /*! @} */ /* The count of NETC_IERB_E_CFH_SIDSVID */ #define NETC_IERB_E_CFH_SIDSVID_COUNT (3U) /*! @name E_CFC_VFDID - ENETC 0 config capability VF device ID register..ENETC 2 config capability VF device ID register */ /*! @{ */ #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_MASK (0xFFFF0000U) #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_SHIFT (16U) #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_MASK) /*! @} */ /* The count of NETC_IERB_E_CFC_VFDID */ #define NETC_IERB_E_CFC_VFDID_COUNT (3U) /*! @name EBCAR - ENETC 0 buffer cache attribute register 0..ENETC 2 buffer cache attribute register 0 */ /*! @{ */ #define NETC_IERB_EBCAR_BD_WRCACHE_MASK (0xFU) #define NETC_IERB_EBCAR_BD_WRCACHE_SHIFT (0U) #define NETC_IERB_EBCAR_BD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRCACHE_SHIFT)) & NETC_IERB_EBCAR_BD_WRCACHE_MASK) #define NETC_IERB_EBCAR_BD_WRDOMAIN_MASK (0x30U) #define NETC_IERB_EBCAR_BD_WRDOMAIN_SHIFT (4U) #define NETC_IERB_EBCAR_BD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRDOMAIN_SHIFT)) & NETC_IERB_EBCAR_BD_WRDOMAIN_MASK) #define NETC_IERB_EBCAR_BD_WRSNP_MASK (0xC0U) #define NETC_IERB_EBCAR_BD_WRSNP_SHIFT (6U) #define NETC_IERB_EBCAR_BD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRSNP_SHIFT)) & NETC_IERB_EBCAR_BD_WRSNP_MASK) #define NETC_IERB_EBCAR_WRCACHE_MASK (0xF00U) #define NETC_IERB_EBCAR_WRCACHE_SHIFT (8U) #define NETC_IERB_EBCAR_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRCACHE_SHIFT)) & NETC_IERB_EBCAR_WRCACHE_MASK) #define NETC_IERB_EBCAR_WRDOMAIN_MASK (0x3000U) #define NETC_IERB_EBCAR_WRDOMAIN_SHIFT (12U) #define NETC_IERB_EBCAR_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRDOMAIN_SHIFT)) & NETC_IERB_EBCAR_WRDOMAIN_MASK) #define NETC_IERB_EBCAR_WRSNP_MASK (0xC000U) #define NETC_IERB_EBCAR_WRSNP_SHIFT (14U) #define NETC_IERB_EBCAR_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRSNP_SHIFT)) & NETC_IERB_EBCAR_WRSNP_MASK) #define NETC_IERB_EBCAR_BD_RDCACHE_MASK (0xF0000U) #define NETC_IERB_EBCAR_BD_RDCACHE_SHIFT (16U) #define NETC_IERB_EBCAR_BD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDCACHE_SHIFT)) & NETC_IERB_EBCAR_BD_RDCACHE_MASK) #define NETC_IERB_EBCAR_BD_RDDOMAIN_MASK (0x300000U) #define NETC_IERB_EBCAR_BD_RDDOMAIN_SHIFT (20U) #define NETC_IERB_EBCAR_BD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDDOMAIN_SHIFT)) & NETC_IERB_EBCAR_BD_RDDOMAIN_MASK) #define NETC_IERB_EBCAR_BD_RDSNP_MASK (0xC00000U) #define NETC_IERB_EBCAR_BD_RDSNP_SHIFT (22U) #define NETC_IERB_EBCAR_BD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDSNP_SHIFT)) & NETC_IERB_EBCAR_BD_RDSNP_MASK) #define NETC_IERB_EBCAR_RDCACHE_MASK (0xF000000U) #define NETC_IERB_EBCAR_RDCACHE_SHIFT (24U) #define NETC_IERB_EBCAR_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDCACHE_SHIFT)) & NETC_IERB_EBCAR_RDCACHE_MASK) #define NETC_IERB_EBCAR_RDDOMAIN_MASK (0x30000000U) #define NETC_IERB_EBCAR_RDDOMAIN_SHIFT (28U) #define NETC_IERB_EBCAR_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDDOMAIN_SHIFT)) & NETC_IERB_EBCAR_RDDOMAIN_MASK) #define NETC_IERB_EBCAR_RDSNP_MASK (0xC0000000U) #define NETC_IERB_EBCAR_RDSNP_SHIFT (30U) #define NETC_IERB_EBCAR_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDSNP_SHIFT)) & NETC_IERB_EBCAR_RDSNP_MASK) /*! @} */ /* The count of NETC_IERB_EBCAR */ #define NETC_IERB_EBCAR_COUNT (3U) /*! @name EMCAR - ENETC 0 message cache attribute register..ENETC 2 message cache attribute register */ /*! @{ */ #define NETC_IERB_EMCAR_MSG_WRCACHE_MASK (0xFU) #define NETC_IERB_EMCAR_MSG_WRCACHE_SHIFT (0U) #define NETC_IERB_EMCAR_MSG_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRCACHE_SHIFT)) & NETC_IERB_EMCAR_MSG_WRCACHE_MASK) #define NETC_IERB_EMCAR_MSG_WRDOMAIN_MASK (0x30U) #define NETC_IERB_EMCAR_MSG_WRDOMAIN_SHIFT (4U) #define NETC_IERB_EMCAR_MSG_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRDOMAIN_SHIFT)) & NETC_IERB_EMCAR_MSG_WRDOMAIN_MASK) #define NETC_IERB_EMCAR_MSG_WRSNP_MASK (0xC0U) #define NETC_IERB_EMCAR_MSG_WRSNP_SHIFT (6U) #define NETC_IERB_EMCAR_MSG_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRSNP_SHIFT)) & NETC_IERB_EMCAR_MSG_WRSNP_MASK) #define NETC_IERB_EMCAR_MSG_RDCACHE_MASK (0xF0000U) #define NETC_IERB_EMCAR_MSG_RDCACHE_SHIFT (16U) #define NETC_IERB_EMCAR_MSG_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDCACHE_SHIFT)) & NETC_IERB_EMCAR_MSG_RDCACHE_MASK) #define NETC_IERB_EMCAR_MSG_RDDOMAIN_MASK (0x300000U) #define NETC_IERB_EMCAR_MSG_RDDOMAIN_SHIFT (20U) #define NETC_IERB_EMCAR_MSG_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDDOMAIN_SHIFT)) & NETC_IERB_EMCAR_MSG_RDDOMAIN_MASK) #define NETC_IERB_EMCAR_MSG_RDSNP_MASK (0xC00000U) #define NETC_IERB_EMCAR_MSG_RDSNP_SHIFT (22U) #define NETC_IERB_EMCAR_MSG_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDSNP_SHIFT)) & NETC_IERB_EMCAR_MSG_RDSNP_MASK) /*! @} */ /* The count of NETC_IERB_EMCAR */ #define NETC_IERB_EMCAR_COUNT (3U) /*! @name ECAR - ENETC 0 command cache attribute register..ENETC 2 command cache attribute register */ /*! @{ */ #define NETC_IERB_ECAR_CBD_WRCACHE_MASK (0xFU) #define NETC_IERB_ECAR_CBD_WRCACHE_SHIFT (0U) #define NETC_IERB_ECAR_CBD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRCACHE_SHIFT)) & NETC_IERB_ECAR_CBD_WRCACHE_MASK) #define NETC_IERB_ECAR_CBD_WRDOMAIN_MASK (0x30U) #define NETC_IERB_ECAR_CBD_WRDOMAIN_SHIFT (4U) #define NETC_IERB_ECAR_CBD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRDOMAIN_SHIFT)) & NETC_IERB_ECAR_CBD_WRDOMAIN_MASK) #define NETC_IERB_ECAR_CBD_WRSNP_MASK (0xC0U) #define NETC_IERB_ECAR_CBD_WRSNP_SHIFT (6U) #define NETC_IERB_ECAR_CBD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRSNP_SHIFT)) & NETC_IERB_ECAR_CBD_WRSNP_MASK) #define NETC_IERB_ECAR_CWRCACHE_MASK (0xF00U) #define NETC_IERB_ECAR_CWRCACHE_SHIFT (8U) #define NETC_IERB_ECAR_CWRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRCACHE_SHIFT)) & NETC_IERB_ECAR_CWRCACHE_MASK) #define NETC_IERB_ECAR_CWRDOMAIN_MASK (0x3000U) #define NETC_IERB_ECAR_CWRDOMAIN_SHIFT (12U) #define NETC_IERB_ECAR_CWRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRDOMAIN_SHIFT)) & NETC_IERB_ECAR_CWRDOMAIN_MASK) #define NETC_IERB_ECAR_CWRSNP_MASK (0xC000U) #define NETC_IERB_ECAR_CWRSNP_SHIFT (14U) #define NETC_IERB_ECAR_CWRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRSNP_SHIFT)) & NETC_IERB_ECAR_CWRSNP_MASK) #define NETC_IERB_ECAR_CBD_RDCACHE_MASK (0xF0000U) #define NETC_IERB_ECAR_CBD_RDCACHE_SHIFT (16U) #define NETC_IERB_ECAR_CBD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDCACHE_SHIFT)) & NETC_IERB_ECAR_CBD_RDCACHE_MASK) #define NETC_IERB_ECAR_CBD_RDDOMAIN_MASK (0x300000U) #define NETC_IERB_ECAR_CBD_RDDOMAIN_SHIFT (20U) #define NETC_IERB_ECAR_CBD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDDOMAIN_SHIFT)) & NETC_IERB_ECAR_CBD_RDDOMAIN_MASK) #define NETC_IERB_ECAR_CBD_RDSNP_MASK (0xC00000U) #define NETC_IERB_ECAR_CBD_RDSNP_SHIFT (22U) #define NETC_IERB_ECAR_CBD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDSNP_SHIFT)) & NETC_IERB_ECAR_CBD_RDSNP_MASK) #define NETC_IERB_ECAR_CRDCACHE_MASK (0xF000000U) #define NETC_IERB_ECAR_CRDCACHE_SHIFT (24U) #define NETC_IERB_ECAR_CRDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDCACHE_SHIFT)) & NETC_IERB_ECAR_CRDCACHE_MASK) #define NETC_IERB_ECAR_CRDDOMAIN_MASK (0x30000000U) #define NETC_IERB_ECAR_CRDDOMAIN_SHIFT (28U) #define NETC_IERB_ECAR_CRDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDDOMAIN_SHIFT)) & NETC_IERB_ECAR_CRDDOMAIN_MASK) #define NETC_IERB_ECAR_CRDSNP_MASK (0xC0000000U) #define NETC_IERB_ECAR_CRDSNP_SHIFT (30U) #define NETC_IERB_ECAR_CRDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDSNP_SHIFT)) & NETC_IERB_ECAR_CRDSNP_MASK) /*! @} */ /* The count of NETC_IERB_ECAR */ #define NETC_IERB_ECAR_COUNT (3U) /*! @name EAMQR - ENETC 0 access management qualifier register..ENETC 2 access management qualifier register */ /*! @{ */ #define NETC_IERB_EAMQR_ARQOS_MASK (0xF0000U) #define NETC_IERB_EAMQR_ARQOS_SHIFT (16U) #define NETC_IERB_EAMQR_ARQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_ARQOS_SHIFT)) & NETC_IERB_EAMQR_ARQOS_MASK) #define NETC_IERB_EAMQR_AWQOS_MASK (0xF00000U) #define NETC_IERB_EAMQR_AWQOS_SHIFT (20U) #define NETC_IERB_EAMQR_AWQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_AWQOS_SHIFT)) & NETC_IERB_EAMQR_AWQOS_MASK) /*! @} */ /* The count of NETC_IERB_EAMQR */ #define NETC_IERB_EAMQR_COUNT (3U) /*! @name EFAUXR - ENETC 0 function auxiliary register..ENETC 2 function auxiliary register */ /*! @{ */ #define NETC_IERB_EFAUXR_FAUX_MASK (0xFU) #define NETC_IERB_EFAUXR_FAUX_SHIFT (0U) /*! FAUX - Function Auxiliary Information */ #define NETC_IERB_EFAUXR_FAUX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EFAUXR_FAUX_SHIFT)) & NETC_IERB_EFAUXR_FAUX_MASK) /*! @} */ /* The count of NETC_IERB_EFAUXR */ #define NETC_IERB_EFAUXR_COUNT (3U) /*! @name EBLPR - ENETC 0 boot loader parameter register 0..ENETC 2 boot loader parameter register 1 */ /*! @{ */ #define NETC_IERB_EBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) #define NETC_IERB_EBLPR_PARAM_VAL_SHIFT (0U) #define NETC_IERB_EBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_EBLPR_PARAM_VAL_MASK) /*! @} */ /* The count of NETC_IERB_EBLPR */ #define NETC_IERB_EBLPR_COUNT (3U) /* The count of NETC_IERB_EBLPR */ #define NETC_IERB_EBLPR_COUNT2 (2U) /*! @name ERXMBER - ENETC 0 receive memory buffer entitlement register..ENETC 2 receive memory buffer entitlement register */ /*! @{ */ #define NETC_IERB_ERXMBER_AMOUNT_MASK (0xFFFFFFU) #define NETC_IERB_ERXMBER_AMOUNT_SHIFT (0U) #define NETC_IERB_ERXMBER_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERXMBER_AMOUNT_SHIFT)) & NETC_IERB_ERXMBER_AMOUNT_MASK) /*! @} */ /* The count of NETC_IERB_ERXMBER */ #define NETC_IERB_ERXMBER_COUNT (3U) /*! @name ERXMBLR - ENETC 0 receive memory buffer limit register..ENETC 2 receive memory buffer limit register */ /*! @{ */ #define NETC_IERB_ERXMBLR_LIMIT_MASK (0xFFFFFFU) #define NETC_IERB_ERXMBLR_LIMIT_SHIFT (0U) #define NETC_IERB_ERXMBLR_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERXMBLR_LIMIT_SHIFT)) & NETC_IERB_ERXMBLR_LIMIT_MASK) /*! @} */ /* The count of NETC_IERB_ERXMBLR */ #define NETC_IERB_ERXMBLR_COUNT (3U) /*! @name ERIDAR - ENETC 0 RID assignment register..ENETC 2 RID assignment register */ /*! @{ */ #define NETC_IERB_ERIDAR_RID_MASK (0xFFFFU) #define NETC_IERB_ERIDAR_RID_SHIFT (0U) #define NETC_IERB_ERIDAR_RID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERIDAR_RID_SHIFT)) & NETC_IERB_ERIDAR_RID_MASK) #define NETC_IERB_ERIDAR_PBUS_MASK (0xFF0000U) #define NETC_IERB_ERIDAR_PBUS_SHIFT (16U) #define NETC_IERB_ERIDAR_PBUS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERIDAR_PBUS_SHIFT)) & NETC_IERB_ERIDAR_PBUS_MASK) /*! @} */ /* The count of NETC_IERB_ERIDAR */ #define NETC_IERB_ERIDAR_COUNT (3U) /*! @name ETXHPTBCR - ENETC 0 transmit high priority tier byte credit register..ENETC 2 transmit high priority tier byte credit register */ /*! @{ */ #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT_MASK (0xFFFFU) #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT_SHIFT (0U) #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETXHPTBCR_BYTE_CREDIT_SHIFT)) & NETC_IERB_ETXHPTBCR_BYTE_CREDIT_MASK) /*! @} */ /* The count of NETC_IERB_ETXHPTBCR */ #define NETC_IERB_ETXHPTBCR_COUNT (3U) /*! @name ETXLPTBCR - ENETC 0 transmit low priority tier byte credit register..ENETC 2 transmit low priority tier byte credit register */ /*! @{ */ #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT_MASK (0xFFFFU) #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT_SHIFT (0U) #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETXLPTBCR_BYTE_CREDIT_SHIFT)) & NETC_IERB_ETXLPTBCR_BYTE_CREDIT_MASK) /*! @} */ /* The count of NETC_IERB_ETXLPTBCR */ #define NETC_IERB_ETXLPTBCR_COUNT (3U) /*! @name EHTMAR - ENETC 0 hash table memory allotment register..ENETC 2 hash table memory allotment register */ /*! @{ */ #define NETC_IERB_EHTMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_EHTMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_EHTMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EHTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EHTMAR_NUM_WORDS_MASK) #define NETC_IERB_EHTMAR_MLOC_MASK (0xC0000000U) #define NETC_IERB_EHTMAR_MLOC_SHIFT (30U) /*! MLOC * 0b00..Common memory * 0b01-0b11.. */ #define NETC_IERB_EHTMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EHTMAR_MLOC_SHIFT)) & NETC_IERB_EHTMAR_MLOC_MASK) /*! @} */ /* The count of NETC_IERB_EHTMAR */ #define NETC_IERB_EHTMAR_COUNT (3U) /*! @name EITMAR - ENETC 0 index table memory allocation register..ENETC 2 index table memory allocation register */ /*! @{ */ #define NETC_IERB_EITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_EITMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_EITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EITMAR_NUM_WORDS_MASK) #define NETC_IERB_EITMAR_MLOC_MASK (0xC0000000U) #define NETC_IERB_EITMAR_MLOC_SHIFT (30U) #define NETC_IERB_EITMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EITMAR_MLOC_SHIFT)) & NETC_IERB_EITMAR_MLOC_MASK) /*! @} */ /* The count of NETC_IERB_EITMAR */ #define NETC_IERB_EITMAR_COUNT (3U) /*! @name EIPFTMAR - ENETC 0 ingress port filter table memory allocation register..ENETC 2 ingress port filter table memory allocation register */ /*! @{ */ #define NETC_IERB_EIPFTMAR_ALLOC_MASK (0xFFFFU) #define NETC_IERB_EIPFTMAR_ALLOC_SHIFT (0U) #define NETC_IERB_EIPFTMAR_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EIPFTMAR_ALLOC_SHIFT)) & NETC_IERB_EIPFTMAR_ALLOC_MASK) /*! @} */ /* The count of NETC_IERB_EIPFTMAR */ #define NETC_IERB_EIPFTMAR_COUNT (3U) /*! @name ERPITMAR - ENETC 0 rate policer index table memory allocation register..ENETC 2 rate policer index table memory allocation register */ /*! @{ */ #define NETC_IERB_ERPITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_ERPITMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_ERPITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERPITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ERPITMAR_NUM_WORDS_MASK) /*! @} */ /* The count of NETC_IERB_ERPITMAR */ #define NETC_IERB_ERPITMAR_COUNT (3U) /*! @name EISCITMAR - ENETC 0 ingress stream counter index table memory allocation register..ENETC 2 ingress stream counter index table memory allocation register */ /*! @{ */ #define NETC_IERB_EISCITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_EISCITMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_EISCITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EISCITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EISCITMAR_NUM_WORDS_MASK) /*! @} */ /* The count of NETC_IERB_EISCITMAR */ #define NETC_IERB_EISCITMAR_COUNT (3U) /*! @name EISITMAR - ENETC 0 ingress stream index table memory allocation register..ENETC 2 ingress stream index table memory allocation register */ /*! @{ */ #define NETC_IERB_EISITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_EISITMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_EISITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EISITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EISITMAR_NUM_WORDS_MASK) /*! @} */ /* The count of NETC_IERB_EISITMAR */ #define NETC_IERB_EISITMAR_COUNT (3U) /*! @name ESGIITMAR - ENETC 0 stream gate instance index table memory allocation register..ENETC 2 stream gate instance index table memory allocation register */ /*! @{ */ #define NETC_IERB_ESGIITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_ESGIITMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_ESGIITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ESGIITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ESGIITMAR_NUM_WORDS_MASK) /*! @} */ /* The count of NETC_IERB_ESGIITMAR */ #define NETC_IERB_ESGIITMAR_COUNT (3U) /*! @name ESGCLITMAR - ENETC 0 stream gate control list index table memory allocation register..ENETC 2 stream gate control list index table memory allocation register */ /*! @{ */ #define NETC_IERB_ESGCLITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_IERB_ESGCLITMAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_ESGCLITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ESGCLITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ESGCLITMAR_NUM_WORDS_MASK) /*! @} */ /* The count of NETC_IERB_ESGCLITMAR */ #define NETC_IERB_ESGCLITMAR_COUNT (3U) /*! @name ETGSTAR - ENETC 0 time gate scheduling table allocation register..ENETC 2 time gate scheduling table allocation register */ /*! @{ */ #define NETC_IERB_ETGSTAR_NUM_WORDS_MASK (0xFFFU) #define NETC_IERB_ETGSTAR_NUM_WORDS_SHIFT (0U) #define NETC_IERB_ETGSTAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSTAR_NUM_WORDS_SHIFT)) & NETC_IERB_ETGSTAR_NUM_WORDS_MASK) /*! @} */ /* The count of NETC_IERB_ETGSTAR */ #define NETC_IERB_ETGSTAR_COUNT (3U) /*! @name ETGSLR - ENETC 0 time gate scheduling lookahead register..ENETC 2 time gate scheduling lookahead register */ /*! @{ */ #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD_MASK (0xFFFFFU) #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD_SHIFT (0U) #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSLR_MIN_LOOKAHEAD_SHIFT)) & NETC_IERB_ETGSLR_MIN_LOOKAHEAD_MASK) #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_MASK (0x80000000U) #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_SHIFT (31U) /*! ZERO_LOOKAHEAD - Zero Lookahead * 0b0..Use MIN_LOOKAHEAD value. * 0b1..If a gate control list is configured, use MIN_LOOKAHEAD value, otherwise use value of zero. */ #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_SHIFT)) & NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_MASK) /*! @} */ /* The count of NETC_IERB_ETGSLR */ #define NETC_IERB_ETGSLR_COUNT (3U) /*! @name VAMQR - VSI 0 access management qualifier register..VSI 5 access management qualifier register */ /*! @{ */ #define NETC_IERB_VAMQR_ARQOS_MASK (0xF0000U) #define NETC_IERB_VAMQR_ARQOS_SHIFT (16U) #define NETC_IERB_VAMQR_ARQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_ARQOS_SHIFT)) & NETC_IERB_VAMQR_ARQOS_MASK) #define NETC_IERB_VAMQR_AWQOS_MASK (0xF00000U) #define NETC_IERB_VAMQR_AWQOS_SHIFT (20U) #define NETC_IERB_VAMQR_AWQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_AWQOS_SHIFT)) & NETC_IERB_VAMQR_AWQOS_MASK) /*! @} */ /* The count of NETC_IERB_VAMQR */ #define NETC_IERB_VAMQR_COUNT (6U) /*! @name VFAUXR - VSI 0 function auxiliary register..VSI 5 function auxiliary register */ /*! @{ */ #define NETC_IERB_VFAUXR_FAUX_MASK (0xFU) #define NETC_IERB_VFAUXR_FAUX_SHIFT (0U) /*! FAUX - Function Auxiliary Information */ #define NETC_IERB_VFAUXR_FAUX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VFAUXR_FAUX_SHIFT)) & NETC_IERB_VFAUXR_FAUX_MASK) /*! @} */ /* The count of NETC_IERB_VFAUXR */ #define NETC_IERB_VFAUXR_COUNT (6U) /*! @name VBLPR - VSI 0 boot loader parameter register 0..VSI 5 boot loader parameter register 1 */ /*! @{ */ #define NETC_IERB_VBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) #define NETC_IERB_VBLPR_PARAM_VAL_SHIFT (0U) #define NETC_IERB_VBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_VBLPR_PARAM_VAL_MASK) /*! @} */ /* The count of NETC_IERB_VBLPR */ #define NETC_IERB_VBLPR_COUNT (6U) /* The count of NETC_IERB_VBLPR */ #define NETC_IERB_VBLPR_COUNT2 (2U) /*! @name VPMAR0 - VSI 0 primary MAC address register 0..VSI 5 primary MAC address register 0 */ /*! @{ */ #define NETC_IERB_VPMAR0_MAC_ADDR_MASK (0xFFFFFFFFU) #define NETC_IERB_VPMAR0_MAC_ADDR_SHIFT (0U) #define NETC_IERB_VPMAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VPMAR0_MAC_ADDR_SHIFT)) & NETC_IERB_VPMAR0_MAC_ADDR_MASK) /*! @} */ /* The count of NETC_IERB_VPMAR0 */ #define NETC_IERB_VPMAR0_COUNT (6U) /*! @name VPMAR1 - VSI 0 primary MAC address register 1..VSI 5 primary MAC address register 1 */ /*! @{ */ #define NETC_IERB_VPMAR1_MAC_ADDR_MASK (0xFFFFU) #define NETC_IERB_VPMAR1_MAC_ADDR_SHIFT (0U) #define NETC_IERB_VPMAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VPMAR1_MAC_ADDR_SHIFT)) & NETC_IERB_VPMAR1_MAC_ADDR_MASK) /*! @} */ /* The count of NETC_IERB_VPMAR1 */ #define NETC_IERB_VPMAR1_COUNT (6U) /*! * @} */ /* end of group NETC_IERB_Register_Masks */ /* NETC_IERB - Peripheral instance base addresses */ /** Peripheral NETC_IERB base address */ #define NETC_IERB_BASE (0x4CDE0000u) /** Peripheral NETC_IERB base pointer */ #define NETC_IERB ((NETC_IERB_Type *)NETC_IERB_BASE) /** Array initializer of NETC_IERB peripheral base addresses */ #define NETC_IERB_BASE_ADDRS { NETC_IERB_BASE } /** Array initializer of NETC_IERB peripheral base pointers */ #define NETC_IERB_BASE_PTRS { NETC_IERB } /*! * @} */ /* end of group NETC_IERB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NETC_PORT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_PORT_Peripheral_Access_Layer NETC_PORT Peripheral Access Layer * @{ */ /** NETC_PORT - Register Layout Typedef */ typedef struct { __I uint32_t PCAPR; /**< Port capability register, offset: 0x0 */ __I uint32_t PMCAPR; /**< Port MAC capability register, offset: 0x4 */ __I uint32_t PIOCAPR; /**< Port I/O capability register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ uint8_t RESERVED_1[12]; __IO uint32_t PMAR0; /**< Port MAC address register 0, offset: 0x20 */ __IO uint32_t PMAR1; /**< Port MAC address register 1, offset: 0x24 */ uint8_t RESERVED_2[40]; __IO uint32_t PTAR; /**< Port TPID acceptance register, offset: 0x50 */ __IO uint32_t PQOSMR; /**< Port QoS mode register, offset: 0x54 */ uint8_t RESERVED_3[40]; __IO uint32_t PPCR; /**< Port parser configuration register, offset: 0x80 */ __IO uint32_t PIPFCR; /**< Port ingress port filter configuration register, offset: 0x84 */ uint8_t RESERVED_4[24]; __IO uint32_t PSGCR; /**< Port stream gate configuration register, offset: 0xA0 */ uint8_t RESERVED_5[92]; __IO uint32_t POR; /**< Port operational register, offset: 0x100 */ __I uint32_t PSR; /**< Port status register, offset: 0x104 */ __IO uint32_t PRXSDUOR; /**< Port receive SDU overhead register, offset: 0x108 */ __IO uint32_t PTXSDUOR; /**< Port transmit SDU overhead register, offset: 0x10C */ __IO uint32_t PTGSCR; /**< Port time gate scheduling control register, offset: 0x110 */ __I uint32_t PTGAGLSR; /**< Port time gate scheduling admin gate list status register, offset: 0x114 */ __I uint32_t PTGAGLLR; /**< Port time gate scheduling admin gate list length register, offset: 0x118 */ __I uint32_t PTGOGLLR; /**< Port time gating operational gate list length register, offset: 0x11C */ __IO uint32_t PTGSATOR; /**< Port time gate scheduling advance time offset register, offset: 0x120 */ __I uint32_t PTGSHAR; /**< Port time gate scheduling hold advance register, offset: 0x124, not available in all instances (available on 6 out of 18) */ __I uint32_t PTGSRAR; /**< Port time gate scheduling release advance register, offset: 0x128, not available in all instances (available on 6 out of 18) */ __IO uint32_t PTGSHCR; /**< Port time gate scheduling hold configuration register, offset: 0x12C, not available in all instances (available on 6 out of 18) */ uint8_t RESERVED_6[4]; __IO uint32_t PFPCR; /**< Port frame preemption configuration register, offset: 0x134, not available in all instances (available on 6 out of 18) */ __IO uint32_t PDGSR; /**< Port default gate state register, offset: 0x138 */ uint8_t RESERVED_7[132]; __I uint32_t PRXDCR; /**< Port Rx discard count register, offset: 0x1C0 */ uint8_t RESERVED_8[4]; __IO uint32_t PRXDCRR0; /**< Port Rx discard count reason register 0, offset: 0x1C8 */ __IO uint32_t PRXDCRR1; /**< Port Rx discard count reason register 1, offset: 0x1CC */ uint8_t RESERVED_9[48]; struct { /* offset: 0x200, array step: 0x20 */ __I uint32_t PTGSTCSR; /**< Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register, array offset: 0x200, array step: 0x20 */ uint8_t RESERVED_0[4]; __IO uint32_t PTCTMSDUR; /**< Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register, array offset: 0x208, array step: 0x20 */ uint8_t RESERVED_1[4]; __IO uint32_t PTCCBSR0; /**< Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0, array offset: 0x210, array step: 0x20 */ __IO uint32_t PTCCBSR1; /**< Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1, array offset: 0x214, array step: 0x20 */ uint8_t RESERVED_2[8]; } TCT_NUM[8]; uint8_t RESERVED_10[352]; __IO uint32_t PISIDCR; /**< Port ingress stream identification configuration register, offset: 0x460 */ } NETC_PORT_Type; /* ---------------------------------------------------------------------------- -- NETC_PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_PORT_Register_Masks NETC_PORT Register Masks * @{ */ /*! @name PCAPR - Port capability register */ /*! @{ */ #define NETC_PORT_PCAPR_LINK_TYPE_MASK (0x10U) #define NETC_PORT_PCAPR_LINK_TYPE_SHIFT (4U) #define NETC_PORT_PCAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_LINK_TYPE_SHIFT)) & NETC_PORT_PCAPR_LINK_TYPE_MASK) #define NETC_PORT_PCAPR_NUM_TC_MASK (0xF000U) #define NETC_PORT_PCAPR_NUM_TC_SHIFT (12U) #define NETC_PORT_PCAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_NUM_TC_SHIFT)) & NETC_PORT_PCAPR_NUM_TC_MASK) #define NETC_PORT_PCAPR_TGS_MASK (0x10000000U) #define NETC_PORT_PCAPR_TGS_SHIFT (28U) /*! TGS - Time Gate Scheduling */ #define NETC_PORT_PCAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_TGS_SHIFT)) & NETC_PORT_PCAPR_TGS_MASK) #define NETC_PORT_PCAPR_CBS_MASK (0x20000000U) #define NETC_PORT_PCAPR_CBS_SHIFT (29U) /*! CBS - Credit Based Shaping */ #define NETC_PORT_PCAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCAPR_CBS_SHIFT)) & NETC_PORT_PCAPR_CBS_MASK) /*! @} */ /*! @name PMCAPR - Port MAC capability register */ /*! @{ */ #define NETC_PORT_PMCAPR_MAC_VAR_MASK (0x7U) #define NETC_PORT_PMCAPR_MAC_VAR_SHIFT (0U) /*! MAC_VAR - MAC Variant */ #define NETC_PORT_PMCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_MAC_VAR_SHIFT)) & NETC_PORT_PMCAPR_MAC_VAR_MASK) #define NETC_PORT_PMCAPR_EFPAD_MASK (0x30U) #define NETC_PORT_PMCAPR_EFPAD_SHIFT (4U) #define NETC_PORT_PMCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_EFPAD_SHIFT)) & NETC_PORT_PMCAPR_EFPAD_MASK) #define NETC_PORT_PMCAPR_HD_MASK (0x100U) #define NETC_PORT_PMCAPR_HD_SHIFT (8U) #define NETC_PORT_PMCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_HD_SHIFT)) & NETC_PORT_PMCAPR_HD_MASK) #define NETC_PORT_PMCAPR_FP_MASK (0x600U) #define NETC_PORT_PMCAPR_FP_SHIFT (9U) /*! FP - Indicates if frame preemption is supported */ #define NETC_PORT_PMCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_FP_SHIFT)) & NETC_PORT_PMCAPR_FP_MASK) #define NETC_PORT_PMCAPR_MII_PROT_MASK (0xF000000U) #define NETC_PORT_PMCAPR_MII_PROT_SHIFT (24U) /*! MII_PROT - Indicates the MII protocol supported */ #define NETC_PORT_PMCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMCAPR_MII_PROT_SHIFT)) & NETC_PORT_PMCAPR_MII_PROT_MASK) /*! @} */ /*! @name PIOCAPR - Port I/O capability register */ /*! @{ */ #define NETC_PORT_PIOCAPR_PCS_PROT_MASK (0xFFFFU) #define NETC_PORT_PIOCAPR_PCS_PROT_SHIFT (0U) /*! PCS_PROT - PCS protocols supported */ #define NETC_PORT_PIOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_PCS_PROT_SHIFT)) & NETC_PORT_PIOCAPR_PCS_PROT_MASK) #define NETC_PORT_PIOCAPR_IO_VAR_MASK (0xF000000U) #define NETC_PORT_PIOCAPR_IO_VAR_SHIFT (24U) /*! IO_VAR - IO Variants supported */ #define NETC_PORT_PIOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_IO_VAR_SHIFT)) & NETC_PORT_PIOCAPR_IO_VAR_MASK) #define NETC_PORT_PIOCAPR_EMDIO_MASK (0x10000000U) #define NETC_PORT_PIOCAPR_EMDIO_SHIFT (28U) #define NETC_PORT_PIOCAPR_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_EMDIO_SHIFT)) & NETC_PORT_PIOCAPR_EMDIO_MASK) #define NETC_PORT_PIOCAPR_REVMII_RATE_MASK (0x40000000U) #define NETC_PORT_PIOCAPR_REVMII_RATE_SHIFT (30U) /*! REVMII_RATE - RevMII MII rate */ #define NETC_PORT_PIOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_REVMII_RATE_SHIFT)) & NETC_PORT_PIOCAPR_REVMII_RATE_MASK) #define NETC_PORT_PIOCAPR_REVMII_MASK (0x80000000U) #define NETC_PORT_PIOCAPR_REVMII_SHIFT (31U) /*! REVMII - Reverse Mode Device Configuration */ #define NETC_PORT_PIOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIOCAPR_REVMII_SHIFT)) & NETC_PORT_PIOCAPR_REVMII_MASK) /*! @} */ /*! @name PCR - Port configuration register */ /*! @{ */ #define NETC_PORT_PCR_HDR_FMT_MASK (0x1U) #define NETC_PORT_PCR_HDR_FMT_SHIFT (0U) /*! HDR_FMT - Header Format * 0b0..Ethernet frame format * 0b1..Reserved */ #define NETC_PORT_PCR_HDR_FMT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_HDR_FMT_SHIFT)) & NETC_PORT_PCR_HDR_FMT_MASK) #define NETC_PORT_PCR_L2DOSE_MASK (0x10U) #define NETC_PORT_PCR_L2DOSE_SHIFT (4U) /*! L2DOSE * 0b0..Disabled * 0b1..Enabled */ #define NETC_PORT_PCR_L2DOSE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_L2DOSE_SHIFT)) & NETC_PORT_PCR_L2DOSE_MASK) #define NETC_PORT_PCR_L3DOSE_MASK (0x20U) #define NETC_PORT_PCR_L3DOSE_SHIFT (5U) /*! L3DOSE - L3 IP Denial of Service (DoS) Protection Enable * 0b0..Disabled * 0b1..Enabled */ #define NETC_PORT_PCR_L3DOSE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_L3DOSE_SHIFT)) & NETC_PORT_PCR_L3DOSE_MASK) #define NETC_PORT_PCR_TIMER_CS_MASK (0x100U) #define NETC_PORT_PCR_TIMER_CS_SHIFT (8U) /*! TIMER_CS - Timer Clock Selection * 0b0..Synchronized timestamp with unit of nanoseconds * 0b1..Free running timestamp with unit of NETC clock ticks */ #define NETC_PORT_PCR_TIMER_CS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_TIMER_CS_SHIFT)) & NETC_PORT_PCR_TIMER_CS_MASK) #define NETC_PORT_PCR_PSPEED_MASK (0x3FFF0000U) #define NETC_PORT_PCR_PSPEED_SHIFT (16U) /*! PSPEED - Port Speed */ #define NETC_PORT_PCR_PSPEED(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PCR_PSPEED_SHIFT)) & NETC_PORT_PCR_PSPEED_MASK) /*! @} */ /*! @name PMAR0 - Port MAC address register 0 */ /*! @{ */ #define NETC_PORT_PMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) #define NETC_PORT_PMAR0_PRIM_MAC_ADDR_SHIFT (0U) #define NETC_PORT_PMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMAR0_PRIM_MAC_ADDR_SHIFT)) & NETC_PORT_PMAR0_PRIM_MAC_ADDR_MASK) /*! @} */ /*! @name PMAR1 - Port MAC address register 1 */ /*! @{ */ #define NETC_PORT_PMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) #define NETC_PORT_PMAR1_PRIM_MAC_ADDR_SHIFT (0U) #define NETC_PORT_PMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PMAR1_PRIM_MAC_ADDR_SHIFT)) & NETC_PORT_PMAR1_PRIM_MAC_ADDR_MASK) /*! @} */ /*! @name PTAR - Port TPID acceptance register */ /*! @{ */ #define NETC_PORT_PTAR_OVTPIDL_MASK (0xFU) #define NETC_PORT_PTAR_OVTPIDL_SHIFT (0U) #define NETC_PORT_PTAR_OVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTAR_OVTPIDL_SHIFT)) & NETC_PORT_PTAR_OVTPIDL_MASK) #define NETC_PORT_PTAR_IVTPIDL_MASK (0xF0U) #define NETC_PORT_PTAR_IVTPIDL_SHIFT (4U) #define NETC_PORT_PTAR_IVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTAR_IVTPIDL_SHIFT)) & NETC_PORT_PTAR_IVTPIDL_MASK) /*! @} */ /*! @name PQOSMR - Port QoS mode register */ /*! @{ */ #define NETC_PORT_PQOSMR_VS_MASK (0x1U) #define NETC_PORT_PQOSMR_VS_SHIFT (0U) #define NETC_PORT_PQOSMR_VS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_VS_SHIFT)) & NETC_PORT_PQOSMR_VS_MASK) #define NETC_PORT_PQOSMR_VE_MASK (0x2U) #define NETC_PORT_PQOSMR_VE_SHIFT (1U) #define NETC_PORT_PQOSMR_VE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_VE_SHIFT)) & NETC_PORT_PQOSMR_VE_MASK) #define NETC_PORT_PQOSMR_DDR_MASK (0xCU) #define NETC_PORT_PQOSMR_DDR_SHIFT (2U) #define NETC_PORT_PQOSMR_DDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_DDR_SHIFT)) & NETC_PORT_PQOSMR_DDR_MASK) #define NETC_PORT_PQOSMR_DIPV_MASK (0x70U) #define NETC_PORT_PQOSMR_DIPV_SHIFT (4U) #define NETC_PORT_PQOSMR_DIPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_DIPV_SHIFT)) & NETC_PORT_PQOSMR_DIPV_MASK) #define NETC_PORT_PQOSMR_VQMP_MASK (0xF0000U) #define NETC_PORT_PQOSMR_VQMP_SHIFT (16U) /*! VQMP - Mapping profile index */ #define NETC_PORT_PQOSMR_VQMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PQOSMR_VQMP_SHIFT)) & NETC_PORT_PQOSMR_VQMP_MASK) /*! @} */ /*! @name PPCR - Port parser configuration register */ /*! @{ */ #define NETC_PORT_PPCR_L1PFS_MASK (0x3EU) #define NETC_PORT_PPCR_L1PFS_SHIFT (1U) #define NETC_PORT_PPCR_L1PFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L1PFS_SHIFT)) & NETC_PORT_PPCR_L1PFS_MASK) #define NETC_PORT_PPCR_L2PFS_MASK (0x3E00U) #define NETC_PORT_PPCR_L2PFS_SHIFT (9U) #define NETC_PORT_PPCR_L2PFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L2PFS_SHIFT)) & NETC_PORT_PPCR_L2PFS_MASK) #define NETC_PORT_PPCR_L3HFP_MASK (0x10000U) #define NETC_PORT_PPCR_L3HFP_SHIFT (16U) #define NETC_PORT_PPCR_L3HFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L3HFP_SHIFT)) & NETC_PORT_PPCR_L3HFP_MASK) #define NETC_PORT_PPCR_L3PFS_MASK (0x3E0000U) #define NETC_PORT_PPCR_L3PFS_SHIFT (17U) #define NETC_PORT_PPCR_L3PFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L3PFS_SHIFT)) & NETC_PORT_PPCR_L3PFS_MASK) #define NETC_PORT_PPCR_L4HFP_MASK (0x1000000U) #define NETC_PORT_PPCR_L4HFP_SHIFT (24U) #define NETC_PORT_PPCR_L4HFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L4HFP_SHIFT)) & NETC_PORT_PPCR_L4HFP_MASK) #define NETC_PORT_PPCR_L4PFS_MASK (0x3E000000U) #define NETC_PORT_PPCR_L4PFS_SHIFT (25U) #define NETC_PORT_PPCR_L4PFS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PPCR_L4PFS_SHIFT)) & NETC_PORT_PPCR_L4PFS_MASK) /*! @} */ /*! @name PIPFCR - Port ingress port filter configuration register */ /*! @{ */ #define NETC_PORT_PIPFCR_EN_MASK (0x1U) #define NETC_PORT_PIPFCR_EN_SHIFT (0U) #define NETC_PORT_PIPFCR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PIPFCR_EN_SHIFT)) & NETC_PORT_PIPFCR_EN_MASK) /*! @} */ /*! @name PSGCR - Port stream gate configuration register */ /*! @{ */ #define NETC_PORT_PSGCR_PDELAY_MASK (0xFFFFFFU) #define NETC_PORT_PSGCR_PDELAY_SHIFT (0U) #define NETC_PORT_PSGCR_PDELAY(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSGCR_PDELAY_SHIFT)) & NETC_PORT_PSGCR_PDELAY_MASK) #define NETC_PORT_PSGCR_OGC_MASK (0x80000000U) #define NETC_PORT_PSGCR_OGC_SHIFT (31U) #define NETC_PORT_PSGCR_OGC(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSGCR_OGC_SHIFT)) & NETC_PORT_PSGCR_OGC_MASK) /*! @} */ /*! @name POR - Port operational register */ /*! @{ */ #define NETC_PORT_POR_TXDIS_MASK (0x1U) #define NETC_PORT_POR_TXDIS_SHIFT (0U) /*! TXDIS - Tx Disable */ #define NETC_PORT_POR_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_POR_TXDIS_SHIFT)) & NETC_PORT_POR_TXDIS_MASK) #define NETC_PORT_POR_RXDIS_MASK (0x2U) #define NETC_PORT_POR_RXDIS_SHIFT (1U) #define NETC_PORT_POR_RXDIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_POR_RXDIS_SHIFT)) & NETC_PORT_POR_RXDIS_MASK) /*! @} */ /*! @name PSR - Port status register */ /*! @{ */ #define NETC_PORT_PSR_TX_BUSY_MASK (0x1U) #define NETC_PORT_PSR_TX_BUSY_SHIFT (0U) /*! TX_BUSY * 0b0..Idle * 0b1..Busy */ #define NETC_PORT_PSR_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSR_TX_BUSY_SHIFT)) & NETC_PORT_PSR_TX_BUSY_MASK) #define NETC_PORT_PSR_RX_BUSY_MASK (0x2U) #define NETC_PORT_PSR_RX_BUSY_SHIFT (1U) /*! RX_BUSY * 0b0..Idle * 0b1..Busy */ #define NETC_PORT_PSR_RX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PSR_RX_BUSY_SHIFT)) & NETC_PORT_PSR_RX_BUSY_MASK) /*! @} */ /*! @name PRXSDUOR - Port receive SDU overhead register */ /*! @{ */ #define NETC_PORT_PRXSDUOR_PPDU_BCO_MASK (0x1FU) #define NETC_PORT_PRXSDUOR_PPDU_BCO_SHIFT (0U) /*! PPDU_BCO - PPDU Byte count overhead */ #define NETC_PORT_PRXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXSDUOR_PPDU_BCO_SHIFT)) & NETC_PORT_PRXSDUOR_PPDU_BCO_MASK) #define NETC_PORT_PRXSDUOR_MACSEC_BCO_MASK (0x1F00U) #define NETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT (8U) /*! MACSEC_BCO - MACsec byte count overhead */ #define NETC_PORT_PRXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT)) & NETC_PORT_PRXSDUOR_MACSEC_BCO_MASK) /*! @} */ /*! @name PTXSDUOR - Port transmit SDU overhead register */ /*! @{ */ #define NETC_PORT_PTXSDUOR_PPDU_BCO_MASK (0x1FU) #define NETC_PORT_PTXSDUOR_PPDU_BCO_SHIFT (0U) /*! PPDU_BCO - PPDU Byte count overhead */ #define NETC_PORT_PTXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXSDUOR_PPDU_BCO_SHIFT)) & NETC_PORT_PTXSDUOR_PPDU_BCO_MASK) #define NETC_PORT_PTXSDUOR_MACSEC_BCO_MASK (0x1F00U) #define NETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT (8U) /*! MACSEC_BCO - MACsec byte count overhead */ #define NETC_PORT_PTXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT)) & NETC_PORT_PTXSDUOR_MACSEC_BCO_MASK) /*! @} */ /*! @name PTGSCR - Port time gate scheduling control register */ /*! @{ */ #define NETC_PORT_PTGSCR_TGE_MASK (0x80000000U) #define NETC_PORT_PTGSCR_TGE_SHIFT (31U) /*! TGE - Time Gating Enable * 0b0..Disabled * 0b1..The initial state of each gate is open. This field must be set to 1 (enabling time gate scheduling) * before any administrative gate control list can be configured. */ #define NETC_PORT_PTGSCR_TGE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSCR_TGE_SHIFT)) & NETC_PORT_PTGSCR_TGE_MASK) /*! @} */ /*! @name PTGAGLSR - Port time gate scheduling admin gate list status register */ /*! @{ */ #define NETC_PORT_PTGAGLSR_TG_MASK (0x1U) #define NETC_PORT_PTGAGLSR_TG_SHIFT (0U) #define NETC_PORT_PTGAGLSR_TG(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGAGLSR_TG_SHIFT)) & NETC_PORT_PTGAGLSR_TG_MASK) #define NETC_PORT_PTGAGLSR_CFG_PEND_MASK (0x2U) #define NETC_PORT_PTGAGLSR_CFG_PEND_SHIFT (1U) #define NETC_PORT_PTGAGLSR_CFG_PEND(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGAGLSR_CFG_PEND_SHIFT)) & NETC_PORT_PTGAGLSR_CFG_PEND_MASK) /*! @} */ /*! @name PTGAGLLR - Port time gate scheduling admin gate list length register */ /*! @{ */ #define NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK (0xFFFFU) #define NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT (0U) #define NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT)) & NETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK) /*! @} */ /*! @name PTGOGLLR - Port time gating operational gate list length register */ /*! @{ */ #define NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK (0xFFFFU) #define NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT (0U) #define NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT)) & NETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK) /*! @} */ /*! @name PTGSATOR - Port time gate scheduling advance time offset register */ /*! @{ */ #define NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_MASK (0xFFFFU) #define NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_SHIFT (0U) #define NETC_PORT_PTGSATOR_ADV_TIME_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_SHIFT)) & NETC_PORT_PTGSATOR_ADV_TIME_OFFSET_MASK) /*! @} */ /*! @name PTGSHAR - Port time gate scheduling hold advance register */ /*! @{ */ #define NETC_PORT_PTGSHAR_HOLDADVANCE_MASK (0xFFFFU) #define NETC_PORT_PTGSHAR_HOLDADVANCE_SHIFT (0U) #define NETC_PORT_PTGSHAR_HOLDADVANCE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSHAR_HOLDADVANCE_SHIFT)) & NETC_PORT_PTGSHAR_HOLDADVANCE_MASK) /*! @} */ /*! @name PTGSRAR - Port time gate scheduling release advance register */ /*! @{ */ #define NETC_PORT_PTGSRAR_RELEASEADVANCE_MASK (0xFFFFU) #define NETC_PORT_PTGSRAR_RELEASEADVANCE_SHIFT (0U) #define NETC_PORT_PTGSRAR_RELEASEADVANCE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSRAR_RELEASEADVANCE_SHIFT)) & NETC_PORT_PTGSRAR_RELEASEADVANCE_MASK) /*! @} */ /*! @name PTGSHCR - Port time gate scheduling hold configuration register */ /*! @{ */ #define NETC_PORT_PTGSHCR_HOLD_SKEW_MASK (0xFFFFFU) #define NETC_PORT_PTGSHCR_HOLD_SKEW_SHIFT (0U) #define NETC_PORT_PTGSHCR_HOLD_SKEW(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSHCR_HOLD_SKEW_SHIFT)) & NETC_PORT_PTGSHCR_HOLD_SKEW_MASK) /*! @} */ /*! @name PFPCR - Port frame preemption configuration register */ /*! @{ */ #define NETC_PORT_PFPCR_FPE_TC0_MASK (0x1U) #define NETC_PORT_PFPCR_FPE_TC0_SHIFT (0U) #define NETC_PORT_PFPCR_FPE_TC0(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC0_SHIFT)) & NETC_PORT_PFPCR_FPE_TC0_MASK) #define NETC_PORT_PFPCR_FPE_TC1_MASK (0x2U) #define NETC_PORT_PFPCR_FPE_TC1_SHIFT (1U) #define NETC_PORT_PFPCR_FPE_TC1(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC1_SHIFT)) & NETC_PORT_PFPCR_FPE_TC1_MASK) #define NETC_PORT_PFPCR_FPE_TC2_MASK (0x4U) #define NETC_PORT_PFPCR_FPE_TC2_SHIFT (2U) #define NETC_PORT_PFPCR_FPE_TC2(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC2_SHIFT)) & NETC_PORT_PFPCR_FPE_TC2_MASK) #define NETC_PORT_PFPCR_FPE_TC3_MASK (0x8U) #define NETC_PORT_PFPCR_FPE_TC3_SHIFT (3U) #define NETC_PORT_PFPCR_FPE_TC3(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC3_SHIFT)) & NETC_PORT_PFPCR_FPE_TC3_MASK) #define NETC_PORT_PFPCR_FPE_TC4_MASK (0x10U) #define NETC_PORT_PFPCR_FPE_TC4_SHIFT (4U) #define NETC_PORT_PFPCR_FPE_TC4(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC4_SHIFT)) & NETC_PORT_PFPCR_FPE_TC4_MASK) #define NETC_PORT_PFPCR_FPE_TC5_MASK (0x20U) #define NETC_PORT_PFPCR_FPE_TC5_SHIFT (5U) #define NETC_PORT_PFPCR_FPE_TC5(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC5_SHIFT)) & NETC_PORT_PFPCR_FPE_TC5_MASK) #define NETC_PORT_PFPCR_FPE_TC6_MASK (0x40U) #define NETC_PORT_PFPCR_FPE_TC6_SHIFT (6U) #define NETC_PORT_PFPCR_FPE_TC6(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC6_SHIFT)) & NETC_PORT_PFPCR_FPE_TC6_MASK) #define NETC_PORT_PFPCR_FPE_TC7_MASK (0x80U) #define NETC_PORT_PFPCR_FPE_TC7_SHIFT (7U) #define NETC_PORT_PFPCR_FPE_TC7(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PFPCR_FPE_TC7_SHIFT)) & NETC_PORT_PFPCR_FPE_TC7_MASK) /*! @} */ /*! @name PDGSR - Port default gate state register */ /*! @{ */ #define NETC_PORT_PDGSR_DGS_TC0_MASK (0x1U) #define NETC_PORT_PDGSR_DGS_TC0_SHIFT (0U) #define NETC_PORT_PDGSR_DGS_TC0(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC0_SHIFT)) & NETC_PORT_PDGSR_DGS_TC0_MASK) #define NETC_PORT_PDGSR_DGS_TC1_MASK (0x2U) #define NETC_PORT_PDGSR_DGS_TC1_SHIFT (1U) #define NETC_PORT_PDGSR_DGS_TC1(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC1_SHIFT)) & NETC_PORT_PDGSR_DGS_TC1_MASK) #define NETC_PORT_PDGSR_DGS_TC2_MASK (0x4U) #define NETC_PORT_PDGSR_DGS_TC2_SHIFT (2U) #define NETC_PORT_PDGSR_DGS_TC2(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC2_SHIFT)) & NETC_PORT_PDGSR_DGS_TC2_MASK) #define NETC_PORT_PDGSR_DGS_TC3_MASK (0x8U) #define NETC_PORT_PDGSR_DGS_TC3_SHIFT (3U) #define NETC_PORT_PDGSR_DGS_TC3(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC3_SHIFT)) & NETC_PORT_PDGSR_DGS_TC3_MASK) #define NETC_PORT_PDGSR_DGS_TC4_MASK (0x10U) #define NETC_PORT_PDGSR_DGS_TC4_SHIFT (4U) #define NETC_PORT_PDGSR_DGS_TC4(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC4_SHIFT)) & NETC_PORT_PDGSR_DGS_TC4_MASK) #define NETC_PORT_PDGSR_DGS_TC5_MASK (0x20U) #define NETC_PORT_PDGSR_DGS_TC5_SHIFT (5U) #define NETC_PORT_PDGSR_DGS_TC5(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC5_SHIFT)) & NETC_PORT_PDGSR_DGS_TC5_MASK) #define NETC_PORT_PDGSR_DGS_TC6_MASK (0x40U) #define NETC_PORT_PDGSR_DGS_TC6_SHIFT (6U) #define NETC_PORT_PDGSR_DGS_TC6(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC6_SHIFT)) & NETC_PORT_PDGSR_DGS_TC6_MASK) #define NETC_PORT_PDGSR_DGS_TC7_MASK (0x80U) #define NETC_PORT_PDGSR_DGS_TC7_SHIFT (7U) #define NETC_PORT_PDGSR_DGS_TC7(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PDGSR_DGS_TC7_SHIFT)) & NETC_PORT_PDGSR_DGS_TC7_MASK) /*! @} */ /*! @name PRXDCR - Port Rx discard count register */ /*! @{ */ #define NETC_PORT_PRXDCR_COUNT_MASK (0xFFFFFFFFU) #define NETC_PORT_PRXDCR_COUNT_SHIFT (0U) #define NETC_PORT_PRXDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCR_COUNT_SHIFT)) & NETC_PORT_PRXDCR_COUNT_MASK) /*! @} */ /*! @name PRXDCRR0 - Port Rx discard count reason register 0 */ /*! @{ */ #define NETC_PORT_PRXDCRR0_PCDR_MASK (0x1U) #define NETC_PORT_PRXDCRR0_PCDR_SHIFT (0U) #define NETC_PORT_PRXDCRR0_PCDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_PCDR_SHIFT)) & NETC_PORT_PRXDCRR0_PCDR_MASK) #define NETC_PORT_PRXDCRR0_SMREDR_MASK (0x2U) #define NETC_PORT_PRXDCRR0_SMREDR_SHIFT (1U) #define NETC_PORT_PRXDCRR0_SMREDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SMREDR_SHIFT)) & NETC_PORT_PRXDCRR0_SMREDR_MASK) #define NETC_PORT_PRXDCRR0_RXDISDR_MASK (0x4U) #define NETC_PORT_PRXDCRR0_RXDISDR_SHIFT (2U) #define NETC_PORT_PRXDCRR0_RXDISDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_RXDISDR_SHIFT)) & NETC_PORT_PRXDCRR0_RXDISDR_MASK) #define NETC_PORT_PRXDCRR0_IPFDR_MASK (0x8U) #define NETC_PORT_PRXDCRR0_IPFDR_SHIFT (3U) #define NETC_PORT_PRXDCRR0_IPFDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_IPFDR_SHIFT)) & NETC_PORT_PRXDCRR0_IPFDR_MASK) #define NETC_PORT_PRXDCRR0_RPDR_MASK (0x10U) #define NETC_PORT_PRXDCRR0_RPDR_SHIFT (4U) #define NETC_PORT_PRXDCRR0_RPDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_RPDR_SHIFT)) & NETC_PORT_PRXDCRR0_RPDR_MASK) #define NETC_PORT_PRXDCRR0_ISFDR_MASK (0x20U) #define NETC_PORT_PRXDCRR0_ISFDR_SHIFT (5U) #define NETC_PORT_PRXDCRR0_ISFDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_ISFDR_SHIFT)) & NETC_PORT_PRXDCRR0_ISFDR_MASK) #define NETC_PORT_PRXDCRR0_SGCDR_MASK (0x40U) #define NETC_PORT_PRXDCRR0_SGCDR_SHIFT (6U) #define NETC_PORT_PRXDCRR0_SGCDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SGCDR_SHIFT)) & NETC_PORT_PRXDCRR0_SGCDR_MASK) #define NETC_PORT_PRXDCRR0_SGOEDR_MASK (0x80U) #define NETC_PORT_PRXDCRR0_SGOEDR_SHIFT (7U) #define NETC_PORT_PRXDCRR0_SGOEDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SGOEDR_SHIFT)) & NETC_PORT_PRXDCRR0_SGOEDR_MASK) #define NETC_PORT_PRXDCRR0_MSDUEDR_MASK (0x100U) #define NETC_PORT_PRXDCRR0_MSDUEDR_SHIFT (8U) #define NETC_PORT_PRXDCRR0_MSDUEDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_MSDUEDR_SHIFT)) & NETC_PORT_PRXDCRR0_MSDUEDR_MASK) #define NETC_PORT_PRXDCRR0_ITEDR_MASK (0x800U) #define NETC_PORT_PRXDCRR0_ITEDR_SHIFT (11U) #define NETC_PORT_PRXDCRR0_ITEDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_ITEDR_SHIFT)) & NETC_PORT_PRXDCRR0_ITEDR_MASK) #define NETC_PORT_PRXDCRR0_ECCEDR_MASK (0x1000U) #define NETC_PORT_PRXDCRR0_ECCEDR_SHIFT (12U) #define NETC_PORT_PRXDCRR0_ECCEDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_ECCEDR_SHIFT)) & NETC_PORT_PRXDCRR0_ECCEDR_MASK) #define NETC_PORT_PRXDCRR0_SIFDR_MASK (0x2000U) #define NETC_PORT_PRXDCRR0_SIFDR_SHIFT (13U) #define NETC_PORT_PRXDCRR0_SIFDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_SIFDR_SHIFT)) & NETC_PORT_PRXDCRR0_SIFDR_MASK) #define NETC_PORT_PRXDCRR0_L2DOSDR_MASK (0x4000U) #define NETC_PORT_PRXDCRR0_L2DOSDR_SHIFT (14U) /*! L2DOSDR - Layer 2 Denial of Service Discard Reason */ #define NETC_PORT_PRXDCRR0_L2DOSDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_L2DOSDR_SHIFT)) & NETC_PORT_PRXDCRR0_L2DOSDR_MASK) #define NETC_PORT_PRXDCRR0_L3DOSDR_MASK (0x8000U) #define NETC_PORT_PRXDCRR0_L3DOSDR_SHIFT (15U) /*! L3DOSDR - Layer 3 Denial of Service Discard Reason */ #define NETC_PORT_PRXDCRR0_L3DOSDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR0_L3DOSDR_SHIFT)) & NETC_PORT_PRXDCRR0_L3DOSDR_MASK) /*! @} */ /*! @name PRXDCRR1 - Port Rx discard count reason register 1 */ /*! @{ */ #define NETC_PORT_PRXDCRR1_ENTRYID_MASK (0xFFFFU) #define NETC_PORT_PRXDCRR1_ENTRYID_SHIFT (0U) #define NETC_PORT_PRXDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR1_ENTRYID_SHIFT)) & NETC_PORT_PRXDCRR1_ENTRYID_MASK) #define NETC_PORT_PRXDCRR1_TT_MASK (0xF0000000U) #define NETC_PORT_PRXDCRR1_TT_SHIFT (28U) #define NETC_PORT_PRXDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PRXDCRR1_TT_SHIFT)) & NETC_PORT_PRXDCRR1_TT_MASK) /*! @} */ /*! @name PTGSTCSR - Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register */ /*! @{ */ #define NETC_PORT_PTGSTCSR_LH_STATE_MASK (0x10000U) #define NETC_PORT_PTGSTCSR_LH_STATE_SHIFT (16U) #define NETC_PORT_PTGSTCSR_LH_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTGSTCSR_LH_STATE_SHIFT)) & NETC_PORT_PTGSTCSR_LH_STATE_MASK) /*! @} */ /* The count of NETC_PORT_PTGSTCSR */ #define NETC_PORT_PTGSTCSR_COUNT (8U) /*! @name PTCTMSDUR - Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register */ /*! @{ */ #define NETC_PORT_PTCTMSDUR_MAXSDU_MASK (0xFFFFU) #define NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT (0U) /*! MAXSDU - Transmit Maximum Service Data Unit Size */ #define NETC_PORT_PTCTMSDUR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT)) & NETC_PORT_PTCTMSDUR_MAXSDU_MASK) #define NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK (0x30000U) #define NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT (16U) /*! SDU_TYPE * 0b00..PPDU (Physical Layer PDU). * 0b01..MPDU (MAC PDU). * 0b10..MSDU (MAC SDU); MPDU minus 12B MAC Header and 4B FCS. The frame length is adjusted by subtracting 16 bytes from it. * *.. */ #define NETC_PORT_PTCTMSDUR_SDU_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT)) & NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK) #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK (0x1000000U) #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT (24U) /*! SF_MAXSDU_DIS - Store-and-Forward Transmit Maximum Service Data Unit (SDU) Check Disable * 0b0..Enabled * 0b1..Disabled */ #define NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT)) & NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK) /*! @} */ /* The count of NETC_PORT_PTCTMSDUR */ #define NETC_PORT_PTCTMSDUR_COUNT (8U) /*! @name PTCCBSR0 - Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0 */ /*! @{ */ #define NETC_PORT_PTCCBSR0_BW_MASK (0x7FU) #define NETC_PORT_PTCCBSR0_BW_SHIFT (0U) #define NETC_PORT_PTCCBSR0_BW(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCCBSR0_BW_SHIFT)) & NETC_PORT_PTCCBSR0_BW_MASK) #define NETC_PORT_PTCCBSR0_FRACT_MASK (0xF0000U) #define NETC_PORT_PTCCBSR0_FRACT_SHIFT (16U) #define NETC_PORT_PTCCBSR0_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCCBSR0_FRACT_SHIFT)) & NETC_PORT_PTCCBSR0_FRACT_MASK) #define NETC_PORT_PTCCBSR0_CBSE_MASK (0x80000000U) #define NETC_PORT_PTCCBSR0_CBSE_SHIFT (31U) /*! CBSE * 0b0..Disabled * 0b1..Enabled */ #define NETC_PORT_PTCCBSR0_CBSE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCCBSR0_CBSE_SHIFT)) & NETC_PORT_PTCCBSR0_CBSE_MASK) /*! @} */ /* The count of NETC_PORT_PTCCBSR0 */ #define NETC_PORT_PTCCBSR0_COUNT (8U) /*! @name PTCCBSR1 - Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1 */ /*! @{ */ #define NETC_PORT_PTCCBSR1_HI_CREDIT_MASK (0xFFFFFFFFU) #define NETC_PORT_PTCCBSR1_HI_CREDIT_SHIFT (0U) #define NETC_PORT_PTCCBSR1_HI_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PTCCBSR1_HI_CREDIT_SHIFT)) & NETC_PORT_PTCCBSR1_HI_CREDIT_MASK) /*! @} */ /* The count of NETC_PORT_PTCCBSR1 */ #define NETC_PORT_PTCCBSR1_COUNT (8U) /*! @name PISIDCR - Port ingress stream identification configuration register */ /*! @{ */ #define NETC_PORT_PISIDCR_KCPAIR_MASK (0x1U) #define NETC_PORT_PISIDCR_KCPAIR_SHIFT (0U) /*! KCPAIR * 0b0..Utilizes ISIDKC0CR0 and ISIDKC1CR0 * 0b1..Utilizes ISIDKC2CR0 and ISIDKC3CR0 (setting not applicable for ENETC) */ #define NETC_PORT_PISIDCR_KCPAIR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_KCPAIR_SHIFT)) & NETC_PORT_PISIDCR_KCPAIR_MASK) #define NETC_PORT_PISIDCR_KC0EN_MASK (0x2U) #define NETC_PORT_PISIDCR_KC0EN_SHIFT (1U) /*! KC0EN - Key Construction 0 Enable * 0b0..There is no exact match lookup performed for the first stream identification lookup. * 0b1..An exact match lookup is performed for the first stream identification regardless of whether there are * entries in the table for the first stream identification. */ #define NETC_PORT_PISIDCR_KC0EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_KC0EN_SHIFT)) & NETC_PORT_PISIDCR_KC0EN_MASK) #define NETC_PORT_PISIDCR_KC1EN_MASK (0x4U) #define NETC_PORT_PISIDCR_KC1EN_SHIFT (2U) /*! KC1EN - Key Construction 1 Enable * 0b0..There is no exact match lookup performed for the second stream identification lookup. * 0b1..An exact match lookup is performed for second stream identification regardless of whether or not there * are entries in the table for second stream identification. */ #define NETC_PORT_PISIDCR_KC1EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_KC1EN_SHIFT)) & NETC_PORT_PISIDCR_KC1EN_MASK) #define NETC_PORT_PISIDCR_ISEID_MASK (0xFFFF0000U) #define NETC_PORT_PISIDCR_ISEID_SHIFT (16U) #define NETC_PORT_PISIDCR_ISEID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PORT_PISIDCR_ISEID_SHIFT)) & NETC_PORT_PISIDCR_ISEID_MASK) /*! @} */ /*! * @} */ /* end of group NETC_PORT_Register_Masks */ /* NETC_PORT - Peripheral instance base addresses */ /** Peripheral ENETC0_PORT base address */ #define ENETC0_PORT_BASE (0x4CC14000u) /** Peripheral ENETC0_PORT base pointer */ #define ENETC0_PORT ((NETC_PORT_Type *)ENETC0_PORT_BASE) /** Peripheral ENETC1_PORT base address */ #define ENETC1_PORT_BASE (0x4CC54000u) /** Peripheral ENETC1_PORT base pointer */ #define ENETC1_PORT ((NETC_PORT_Type *)ENETC1_PORT_BASE) /** Peripheral ENETC2_PORT base address */ #define ENETC2_PORT_BASE (0x4CC94000u) /** Peripheral ENETC2_PORT base pointer */ #define ENETC2_PORT ((NETC_PORT_Type *)ENETC2_PORT_BASE) /** Array initializer of NETC_PORT peripheral base addresses */ #define NETC_PORT_BASE_ADDRS { ENETC0_PORT_BASE, ENETC1_PORT_BASE, ENETC2_PORT_BASE } /** Array initializer of NETC_PORT peripheral base pointers */ #define NETC_PORT_BASE_PTRS { ENETC0_PORT, ENETC1_PORT, ENETC2_PORT } /*! * @} */ /* end of group NETC_PORT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NETC_PRIV Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_PRIV_Peripheral_Access_Layer NETC_PRIV Peripheral Access Layer * @{ */ /** NETC_PRIV - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[256]; __IO uint32_t NETCRR; /**< NETC reset register, offset: 0x100 */ __I uint32_t NETCSR; /**< NETC status register, offset: 0x104 */ uint8_t RESERVED_1[256]; __IO uint32_t MEICR; /**< Memory Error Injection Config Register, offset: 0x208 */ __IO uint32_t EICR; /**< Error Injection Code Register, offset: 0x20C */ uint8_t RESERVED_2[3056]; __IO uint32_t CMECR; /**< Correctable memory error configuration register, offset: 0xE00 */ __IO uint32_t CMESR; /**< Correctable memory error status register, offset: 0xE04 */ uint8_t RESERVED_3[4]; __I uint32_t CMECTR; /**< Correctable memory error count register, offset: 0xE0C */ uint8_t RESERVED_4[32]; __IO uint32_t UNMECR; /**< Uncorrectable non-fatal memory error configuration register, offset: 0xE30 */ __IO uint32_t UNMESR0; /**< Uncorrectable non-fatal memory error status register 0, offset: 0xE34 */ __I uint32_t UNMESR1; /**< Uncorrectable non-fatal memory error status register 1, offset: 0xE38 */ __I uint32_t UNMECTR; /**< Uncorrectable non-fatal memory error count register, offset: 0xE3C */ __IO uint32_t UFMECR; /**< Uncorrectable fatal memory error configuration register, offset: 0xE40 */ __IO uint32_t UFMESR0; /**< Uncorrectable fatal memory error status register 0, offset: 0xE44 */ __I uint32_t UFMESR1; /**< Uncorrectable fatal memory error status register 1, offset: 0xE48 */ } NETC_PRIV_Type; /* ---------------------------------------------------------------------------- -- NETC_PRIV Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_PRIV_Register_Masks NETC_PRIV Register Masks * @{ */ /*! @name NETCRR - NETC reset register */ /*! @{ */ #define NETC_PRIV_NETCRR_SR_MASK (0x1U) #define NETC_PRIV_NETCRR_SR_SHIFT (0U) /*! SR - Soft reset */ #define NETC_PRIV_NETCRR_SR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCRR_SR_SHIFT)) & NETC_PRIV_NETCRR_SR_MASK) #define NETC_PRIV_NETCRR_LOCK_MASK (0x2U) #define NETC_PRIV_NETCRR_LOCK_SHIFT (1U) /*! LOCK - Lock */ #define NETC_PRIV_NETCRR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCRR_LOCK_SHIFT)) & NETC_PRIV_NETCRR_LOCK_MASK) /*! @} */ /*! @name NETCSR - NETC status register */ /*! @{ */ #define NETC_PRIV_NETCSR_ERROR_MASK (0x1U) #define NETC_PRIV_NETCSR_ERROR_SHIFT (0U) /*! ERROR - Error * 0b0..Configuration is valid. * 0b1..The current IERB configuration setting is invalid due to error in binding or resource allocation. * Operating NETC in current condition could lead to undefined behavior. */ #define NETC_PRIV_NETCSR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCSR_ERROR_SHIFT)) & NETC_PRIV_NETCSR_ERROR_MASK) #define NETC_PRIV_NETCSR_STATE_MASK (0x2U) #define NETC_PRIV_NETCSR_STATE_SHIFT (1U) /*! STATE - Indicates NETC's operational state * 0b0..All NETC functions are ready for operation. * 0b1..NETC has inhibited write access to IERB registers and is in the process of initializing NETC. */ #define NETC_PRIV_NETCSR_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCSR_STATE_SHIFT)) & NETC_PRIV_NETCSR_STATE_MASK) /*! @} */ /*! @name MEICR - Memory Error Injection Config Register */ /*! @{ */ #define NETC_PRIV_MEICR_LINK_ID_MASK (0x1FU) #define NETC_PRIV_MEICR_LINK_ID_SHIFT (0U) /*! LINK_ID - Link ID */ #define NETC_PRIV_MEICR_LINK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_LINK_ID_SHIFT)) & NETC_PRIV_MEICR_LINK_ID_MASK) #define NETC_PRIV_MEICR_MEM_ID_MASK (0x1F00U) #define NETC_PRIV_MEICR_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define NETC_PRIV_MEICR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_MEM_ID_SHIFT)) & NETC_PRIV_MEICR_MEM_ID_MASK) #define NETC_PRIV_MEICR_ARM_MASK (0xC0000000U) #define NETC_PRIV_MEICR_ARM_SHIFT (30U) /*! ARM - Armed * 0b00..Disabled * 0b01..Single Bit ECC Error * 0b10..Multi Bit ECC Error * 0b11..Reserved (disabled) */ #define NETC_PRIV_MEICR_ARM(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_ARM_SHIFT)) & NETC_PRIV_MEICR_ARM_MASK) /*! @} */ /*! @name EICR - Error Injection Code Register */ /*! @{ */ #define NETC_PRIV_EICR_EN_MASK (0xFFU) #define NETC_PRIV_EICR_EN_SHIFT (0U) /*! EN - Enable * 0b10000110..Enables error injection function * *..Disables error injection function */ #define NETC_PRIV_EICR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_EICR_EN_SHIFT)) & NETC_PRIV_EICR_EN_MASK) /*! @} */ /*! @name CMECR - Correctable memory error configuration register */ /*! @{ */ #define NETC_PRIV_CMECR_THRESHOLD_MASK (0xFFU) #define NETC_PRIV_CMECR_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define NETC_PRIV_CMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMECR_THRESHOLD_SHIFT)) & NETC_PRIV_CMECR_THRESHOLD_MASK) /*! @} */ /*! @name CMESR - Correctable memory error status register */ /*! @{ */ #define NETC_PRIV_CMESR_LINK_SLICE_ID_MASK (0x1FU) #define NETC_PRIV_CMESR_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define NETC_PRIV_CMESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_LINK_SLICE_ID_SHIFT)) & NETC_PRIV_CMESR_LINK_SLICE_ID_MASK) #define NETC_PRIV_CMESR_MEM_ID_MASK (0x1F00U) #define NETC_PRIV_CMESR_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define NETC_PRIV_CMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_MEM_ID_SHIFT)) & NETC_PRIV_CMESR_MEM_ID_MASK) #define NETC_PRIV_CMESR_LE_MASK (0x20000000U) #define NETC_PRIV_CMESR_LE_SHIFT (29U) /*! LE - Locality Elevated */ #define NETC_PRIV_CMESR_LE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_LE_SHIFT)) & NETC_PRIV_CMESR_LE_MASK) #define NETC_PRIV_CMESR_SBEE_MASK (0x80000000U) #define NETC_PRIV_CMESR_SBEE_SHIFT (31U) /*! SBEE - Single-bit ECC error */ #define NETC_PRIV_CMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_SBEE_SHIFT)) & NETC_PRIV_CMESR_SBEE_MASK) /*! @} */ /*! @name CMECTR - Correctable memory error count register */ /*! @{ */ #define NETC_PRIV_CMECTR_COUNT_MASK (0xFFU) #define NETC_PRIV_CMECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define NETC_PRIV_CMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMECTR_COUNT_SHIFT)) & NETC_PRIV_CMECTR_COUNT_MASK) /*! @} */ /*! @name UNMECR - Uncorrectable non-fatal memory error configuration register */ /*! @{ */ #define NETC_PRIV_UNMECR_THRESHOLD_MASK (0xFFU) #define NETC_PRIV_UNMECR_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold * 0b00000000..Disables reporting of non-fatal memory errors. * *..Determines the threshold value (1-255) of non-fatal memory errors to be reported. */ #define NETC_PRIV_UNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECR_THRESHOLD_SHIFT)) & NETC_PRIV_UNMECR_THRESHOLD_MASK) #define NETC_PRIV_UNMECR_RD_MASK (0x80000000U) #define NETC_PRIV_UNMECR_RD_SHIFT (31U) /*! RD - Report disable * 0b0..Enabled * 0b1..Disabled */ #define NETC_PRIV_UNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECR_RD_SHIFT)) & NETC_PRIV_UNMECR_RD_MASK) /*! @} */ /*! @name UNMESR0 - Uncorrectable non-fatal memory error status register 0 */ /*! @{ */ #define NETC_PRIV_UNMESR0_LINK_SLICE_ID_MASK (0x1FU) #define NETC_PRIV_UNMESR0_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define NETC_PRIV_UNMESR0_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_LINK_SLICE_ID_SHIFT)) & NETC_PRIV_UNMESR0_LINK_SLICE_ID_MASK) #define NETC_PRIV_UNMESR0_MEM_ID_MASK (0x1F00U) #define NETC_PRIV_UNMESR0_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define NETC_PRIV_UNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_MEM_ID_SHIFT)) & NETC_PRIV_UNMESR0_MEM_ID_MASK) #define NETC_PRIV_UNMESR0_SYNDROME_MASK (0x7FF0000U) #define NETC_PRIV_UNMESR0_SYNDROME_SHIFT (16U) /*! SYNDROME - Syndrome */ #define NETC_PRIV_UNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_SYNDROME_SHIFT)) & NETC_PRIV_UNMESR0_SYNDROME_MASK) #define NETC_PRIV_UNMESR0_LE_MASK (0x20000000U) #define NETC_PRIV_UNMESR0_LE_SHIFT (29U) /*! LE - Locality Elevated */ #define NETC_PRIV_UNMESR0_LE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_LE_SHIFT)) & NETC_PRIV_UNMESR0_LE_MASK) #define NETC_PRIV_UNMESR0_MBEE_MASK (0x80000000U) #define NETC_PRIV_UNMESR0_MBEE_SHIFT (31U) /*! MBEE - Multi-bit ECC error */ #define NETC_PRIV_UNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_MBEE_SHIFT)) & NETC_PRIV_UNMESR0_MBEE_MASK) /*! @} */ /*! @name UNMESR1 - Uncorrectable non-fatal memory error status register 1 */ /*! @{ */ #define NETC_PRIV_UNMESR1_ADDR_MASK (0xFFFFFFFFU) #define NETC_PRIV_UNMESR1_ADDR_SHIFT (0U) /*! ADDR - Address */ #define NETC_PRIV_UNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR1_ADDR_SHIFT)) & NETC_PRIV_UNMESR1_ADDR_MASK) /*! @} */ /*! @name UNMECTR - Uncorrectable non-fatal memory error count register */ /*! @{ */ #define NETC_PRIV_UNMECTR_COUNT_MASK (0xFFU) #define NETC_PRIV_UNMECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define NETC_PRIV_UNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECTR_COUNT_SHIFT)) & NETC_PRIV_UNMECTR_COUNT_MASK) /*! @} */ /*! @name UFMECR - Uncorrectable fatal memory error configuration register */ /*! @{ */ #define NETC_PRIV_UFMECR_RD_MASK (0x80000000U) #define NETC_PRIV_UFMECR_RD_SHIFT (31U) /*! RD - Report disable * 0b0..Enabled * 0b1..Disabled */ #define NETC_PRIV_UFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMECR_RD_SHIFT)) & NETC_PRIV_UFMECR_RD_MASK) /*! @} */ /*! @name UFMESR0 - Uncorrectable fatal memory error status register 0 */ /*! @{ */ #define NETC_PRIV_UFMESR0_LINK_SLICE_ID_MASK (0x1FU) #define NETC_PRIV_UFMESR0_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define NETC_PRIV_UFMESR0_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_LINK_SLICE_ID_SHIFT)) & NETC_PRIV_UFMESR0_LINK_SLICE_ID_MASK) #define NETC_PRIV_UFMESR0_MEM_ID_MASK (0x1F00U) #define NETC_PRIV_UFMESR0_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define NETC_PRIV_UFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_MEM_ID_SHIFT)) & NETC_PRIV_UFMESR0_MEM_ID_MASK) #define NETC_PRIV_UFMESR0_SYNDROME_MASK (0x7FF0000U) #define NETC_PRIV_UFMESR0_SYNDROME_SHIFT (16U) /*! SYNDROME - Syndrome */ #define NETC_PRIV_UFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_SYNDROME_SHIFT)) & NETC_PRIV_UFMESR0_SYNDROME_MASK) #define NETC_PRIV_UFMESR0_LE_MASK (0x20000000U) #define NETC_PRIV_UFMESR0_LE_SHIFT (29U) /*! LE - Locality Elevated */ #define NETC_PRIV_UFMESR0_LE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_LE_SHIFT)) & NETC_PRIV_UFMESR0_LE_MASK) #define NETC_PRIV_UFMESR0_M_MASK (0x40000000U) #define NETC_PRIV_UFMESR0_M_SHIFT (30U) /*! M - Multiple */ #define NETC_PRIV_UFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_M_SHIFT)) & NETC_PRIV_UFMESR0_M_MASK) #define NETC_PRIV_UFMESR0_MBEE_MASK (0x80000000U) #define NETC_PRIV_UFMESR0_MBEE_SHIFT (31U) /*! MBEE - Multi-bit ECC error */ #define NETC_PRIV_UFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_MBEE_SHIFT)) & NETC_PRIV_UFMESR0_MBEE_MASK) /*! @} */ /*! @name UFMESR1 - Uncorrectable fatal memory error status register 1 */ /*! @{ */ #define NETC_PRIV_UFMESR1_ADDR_MASK (0xFFFFFFFFU) #define NETC_PRIV_UFMESR1_ADDR_SHIFT (0U) /*! ADDR - Address */ #define NETC_PRIV_UFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR1_ADDR_SHIFT)) & NETC_PRIV_UFMESR1_ADDR_MASK) /*! @} */ /*! * @} */ /* end of group NETC_PRIV_Register_Masks */ /* NETC_PRIV - Peripheral instance base addresses */ /** Peripheral NETC_PRIV base address */ #define NETC_PRIV_BASE (0x4CDF0000u) /** Peripheral NETC_PRIV base pointer */ #define NETC_PRIV ((NETC_PRIV_Type *)NETC_PRIV_BASE) /** Array initializer of NETC_PRIV peripheral base addresses */ #define NETC_PRIV_BASE_ADDRS { NETC_PRIV_BASE } /** Array initializer of NETC_PRIV peripheral base pointers */ #define NETC_PRIV_BASE_PTRS { NETC_PRIV } /*! * @} */ /* end of group NETC_PRIV_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NETC_SW_ENETC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_SW_ENETC_Peripheral_Access_Layer NETC_SW_ENETC Peripheral Access Layer * @{ */ /** NETC_SW_ENETC - Register Layout Typedef */ typedef struct { __I uint32_t IPCAPR; /**< Ingress port capability register, offset: 0x0 */ __I uint32_t EPCAPR; /**< Egress port capability register, offset: 0x4 */ uint8_t RESERVED_0[8]; __I uint32_t OSR; /**< Operational state register, offset: 0x10 */ uint8_t RESERVED_1[44]; __IO uint32_t CMECR; /**< Correctable memory error configuration register, offset: 0x40 */ __IO uint32_t CMESR; /**< Correctable memory error status register, offset: 0x44 */ uint8_t RESERVED_2[4]; __I uint32_t CMECTR; /**< Correctable memory error count register, offset: 0x4C */ uint8_t RESERVED_3[16]; __IO uint32_t UNMACECR; /**< Uncorrectable non-fatal MAC error configuration register, offset: 0x60 */ __I uint32_t UNMACESR; /**< Uncorrectable non-fatal MAC error status register, offset: 0x64 */ uint8_t RESERVED_4[40]; __IO uint32_t UNMECR; /**< Uncorrectable non-fatal memory error configuration register, offset: 0x90 */ __IO uint32_t UNMESR0; /**< Uncorrectable non-fatal memory error status register 0, offset: 0x94 */ __I uint32_t UNMESR1; /**< Uncorrectable non-fatal memory error status register 1, offset: 0x98 */ __I uint32_t UNMECTR; /**< Uncorrectable non-fatal memory error count register, offset: 0x9C */ __IO uint32_t UFMECR; /**< Uncorrectable fatal memory error configuration register, offset: 0xA0 */ __IO uint32_t UFMESR0; /**< Uncorrectable fatal memory error status register 0, offset: 0xA4 */ __I uint32_t UFMESR1; /**< Uncorrectable fatal memory error status register 1, offset: 0xA8 */ uint8_t RESERVED_5[36]; __I uint32_t MIRR; /**< MAC interrupt reason register, offset: 0xD0 */ __IO uint32_t MMSIVR; /**< MAC MSI-X vector register, offset: 0xD4 */ uint8_t RESERVED_6[16]; __I uint32_t EMDIOIRR; /**< External MDIO interrupt reason register, offset: 0xE8 */ __IO uint32_t EMDIOMSIVR; /**< External MDIO MSI-X vector register, offset: 0xEC */ uint8_t RESERVED_7[272]; __IO uint32_t CVLANR1; /**< Custom VLAN EtherType register 1, offset: 0x200 */ __IO uint32_t CVLANR2; /**< Custom VLAN EtherType register 2, offset: 0x204 */ uint8_t RESERVED_8[24]; __IO uint32_t DOSL2CR; /**< DoS L2 configuration register, offset: 0x220 */ __IO uint32_t DOSL3CR; /**< DoS L3 configuration register, offset: 0x224 */ uint8_t RESERVED_9[216]; struct { /* offset: 0x300, array step: 0xC */ __IO uint32_t VLANIPVMPR0; /**< VLAN to IPV mapping profile 0 register 0, array offset: 0x300, array step: 0xC */ __IO uint32_t VLANIPVMPR1; /**< VLAN to IPV mapping profile 0 register 1, array offset: 0x304, array step: 0xC */ __IO uint32_t VLANDRMPR; /**< VLAN to DR mapping profile 0 register, array offset: 0x308, array step: 0xC */ } NUM_PROFILE[1]; uint8_t RESERVED_10[820]; __I uint32_t IPFCAPR; /**< Ingress port filter capability register, offset: 0x640 */ __I uint32_t IPFTCAPR; /**< Ingress port filter table capability register, offset: 0x644 */ __I uint32_t IPFTMOR; /**< Ingress port filter table memory operational register, offset: 0x648 */ uint8_t RESERVED_11[436]; __I uint32_t ITMCAPR; /**< Index table memory capability register, offset: 0x800 */ uint8_t RESERVED_12[12]; __I uint32_t RPCAPR; /**< Rate policer capability register, offset: 0x810 */ __I uint32_t RPITCAPR; /**< Rate policer index table capability register, offset: 0x814 */ __IO uint32_t RPITMAR; /**< Rate policer index table memory allocation register, offset: 0x818 */ __I uint32_t RPITOR; /**< Rate policer index table operational register, offset: 0x81C */ uint8_t RESERVED_13[4]; __I uint32_t ISCITCAPR; /**< Ingress stream counter index table capability register, offset: 0x824 */ __IO uint32_t ISCITMAR; /**< Ingress stream counter index table memory allocation register, offset: 0x828 */ __I uint32_t ISCITOR; /**< Ingress stream counter index table operational register, offset: 0x82C */ __I uint32_t ISCAPR; /**< Ingress stream capability register, offset: 0x830 */ __I uint32_t ISITCAPR; /**< Ingress stream index table capability register, offset: 0x834 */ __IO uint32_t ISITMAR; /**< Ingress stream index table memory allocation register, offset: 0x838 */ __I uint32_t ISITOR; /**< Ingress stream index table operational register, offset: 0x83C */ uint8_t RESERVED_14[32]; __I uint32_t SGCAPR; /**< Stream gate capability register, offset: 0x860 */ __I uint32_t SGIITCAPR; /**< Stream gate instance index table capability register, offset: 0x864 */ __IO uint32_t SGIITMAR; /**< Stream gate instance index table memory allocation register, offset: 0x868 */ __I uint32_t SGIITOR; /**< Stream gate instance index table operational register, offset: 0x86C */ uint8_t RESERVED_15[4]; __I uint32_t SGCLITCAPR; /**< Stream gate control list index table capability register, offset: 0x874 */ __IO uint32_t SGCLITMAR; /**< Stream gate control list index table memory allocation register, offset: 0x878 */ __I uint32_t SGCLTMOR; /**< Stream gate control list table memory operational register, offset: 0x87C */ uint8_t RESERVED_16[84]; __I uint32_t TGSTCAPR; /**< Time gate scheduling table capability register, offset: 0x8D4 */ uint8_t RESERVED_17[4]; __I uint32_t TGSTMOR; /**< Time gate scheduling table memory operation register, offset: 0x8DC */ uint8_t RESERVED_18[32]; __I uint32_t HTMCAPR; /**< Hash table memory capability register, offset: 0x900 */ __I uint32_t HTMOR; /**< Hash table memory operational register, offset: 0x904 */ uint8_t RESERVED_19[8]; __I uint32_t ISIDCAPR; /**< Ingress stream identification capability register, offset: 0x910 */ uint8_t RESERVED_20[12]; __I uint32_t ISIDKC0OR; /**< Ingress stream identification key construction 0 operational register, offset: 0x920 */ __IO uint32_t ISIDKC0CR0; /**< Ingress stream identification key construction 0 configuration register 0, offset: 0x924 */ uint8_t RESERVED_21[8]; __IO uint32_t ISIDKC0PF0CR; /**< Ingress stream identification key construction 0 payload field 0 configuration register, offset: 0x930 */ __IO uint32_t ISIDKC0PF1CR; /**< Ingress stream identification key construction 0 payload field 1 configuration register, offset: 0x934 */ __IO uint32_t ISIDKC0PF2CR; /**< Ingress stream identification key construction 0 payload field 2 configuration register, offset: 0x938 */ __IO uint32_t ISIDKC0PF3CR; /**< Ingress stream identification key construction 0 payload field 3 configuration register, offset: 0x93C */ __I uint32_t ISIDKC1OR; /**< Ingress stream identification key construction 1 operational register, offset: 0x940 */ __IO uint32_t ISIDKC1CR0; /**< Ingress stream identification key construction 1 configuration register 0, offset: 0x944 */ uint8_t RESERVED_22[8]; __IO uint32_t ISIDKC1PF0CR; /**< Ingress stream identification key construction 1 payload field 0 configuration register, offset: 0x950 */ __IO uint32_t ISIDKC1PF1CR; /**< Ingress stream identification key construction 1 payload field 1 configuration register, offset: 0x954 */ __IO uint32_t ISIDKC1PF2CR; /**< Ingress stream identification key construction 1 payload field 2 configuration register, offset: 0x958 */ __IO uint32_t ISIDKC1PF3CR; /**< Ingress stream identification key construction 1 payload field 3 configuration register, offset: 0x95C */ uint8_t RESERVED_23[164]; __I uint32_t ISFHTOR; /**< Ingress stream filter hash table operational register, offset: 0xA04 */ } NETC_SW_ENETC_Type; /* ---------------------------------------------------------------------------- -- NETC_SW_ENETC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_SW_ENETC_Register_Masks NETC_SW_ENETC Register Masks * @{ */ /*! @name IPCAPR - Ingress port capability register */ /*! @{ */ #define NETC_SW_ENETC_IPCAPR_RP_MASK (0x1U) #define NETC_SW_ENETC_IPCAPR_RP_SHIFT (0U) #define NETC_SW_ENETC_IPCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_RP_SHIFT)) & NETC_SW_ENETC_IPCAPR_RP_MASK) #define NETC_SW_ENETC_IPCAPR_IPFLT_MASK (0x2U) #define NETC_SW_ENETC_IPCAPR_IPFLT_SHIFT (1U) #define NETC_SW_ENETC_IPCAPR_IPFLT(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_IPFLT_SHIFT)) & NETC_SW_ENETC_IPCAPR_IPFLT_MASK) #define NETC_SW_ENETC_IPCAPR_ISID_MASK (0x4U) #define NETC_SW_ENETC_IPCAPR_ISID_SHIFT (2U) #define NETC_SW_ENETC_IPCAPR_ISID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_ISID_SHIFT)) & NETC_SW_ENETC_IPCAPR_ISID_MASK) #define NETC_SW_ENETC_IPCAPR_SDU_MASK (0x1F00U) #define NETC_SW_ENETC_IPCAPR_SDU_SHIFT (8U) /*! SDU - Indicates support for various PDU/SDUs (Protocol/Service Data Unit) definitions. */ #define NETC_SW_ENETC_IPCAPR_SDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_SDU_SHIFT)) & NETC_SW_ENETC_IPCAPR_SDU_MASK) #define NETC_SW_ENETC_IPCAPR_NUM_VQMP_MASK (0xF0000U) #define NETC_SW_ENETC_IPCAPR_NUM_VQMP_SHIFT (16U) #define NETC_SW_ENETC_IPCAPR_NUM_VQMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPCAPR_NUM_VQMP_SHIFT)) & NETC_SW_ENETC_IPCAPR_NUM_VQMP_MASK) /*! @} */ /*! @name EPCAPR - Egress port capability register */ /*! @{ */ #define NETC_SW_ENETC_EPCAPR_SDU_MASK (0x1F00U) #define NETC_SW_ENETC_EPCAPR_SDU_SHIFT (8U) /*! SDU - Indicates support for various PDU/SDUs (Protocol/Service Data Unit) definitions. */ #define NETC_SW_ENETC_EPCAPR_SDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EPCAPR_SDU_SHIFT)) & NETC_SW_ENETC_EPCAPR_SDU_MASK) /*! @} */ /*! @name OSR - Operational state register */ /*! @{ */ #define NETC_SW_ENETC_OSR_STATE_MASK (0x1U) #define NETC_SW_ENETC_OSR_STATE_SHIFT (0U) #define NETC_SW_ENETC_OSR_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_OSR_STATE_SHIFT)) & NETC_SW_ENETC_OSR_STATE_MASK) #define NETC_SW_ENETC_OSR_ITM_STATE_MASK (0x2U) #define NETC_SW_ENETC_OSR_ITM_STATE_SHIFT (1U) #define NETC_SW_ENETC_OSR_ITM_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_OSR_ITM_STATE_SHIFT)) & NETC_SW_ENETC_OSR_ITM_STATE_MASK) /*! @} */ /*! @name CMECR - Correctable memory error configuration register */ /*! @{ */ #define NETC_SW_ENETC_CMECR_THRESHOLD_MASK (0xFFU) #define NETC_SW_ENETC_CMECR_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define NETC_SW_ENETC_CMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMECR_THRESHOLD_SHIFT)) & NETC_SW_ENETC_CMECR_THRESHOLD_MASK) /*! @} */ /*! @name CMESR - Correctable memory error status register */ /*! @{ */ #define NETC_SW_ENETC_CMESR_LINK_SLICE_ID_MASK (0x1FU) #define NETC_SW_ENETC_CMESR_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define NETC_SW_ENETC_CMESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMESR_LINK_SLICE_ID_SHIFT)) & NETC_SW_ENETC_CMESR_LINK_SLICE_ID_MASK) #define NETC_SW_ENETC_CMESR_MEM_ID_MASK (0x1F00U) #define NETC_SW_ENETC_CMESR_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define NETC_SW_ENETC_CMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMESR_MEM_ID_SHIFT)) & NETC_SW_ENETC_CMESR_MEM_ID_MASK) #define NETC_SW_ENETC_CMESR_SBEE_MASK (0x80000000U) #define NETC_SW_ENETC_CMESR_SBEE_SHIFT (31U) /*! SBEE - Single-bit ECC error */ #define NETC_SW_ENETC_CMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMESR_SBEE_SHIFT)) & NETC_SW_ENETC_CMESR_SBEE_MASK) /*! @} */ /*! @name CMECTR - Correctable memory error count register */ /*! @{ */ #define NETC_SW_ENETC_CMECTR_COUNT_MASK (0xFFU) #define NETC_SW_ENETC_CMECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define NETC_SW_ENETC_CMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CMECTR_COUNT_SHIFT)) & NETC_SW_ENETC_CMECTR_COUNT_MASK) /*! @} */ /*! @name UNMACECR - Uncorrectable non-fatal MAC error configuration register */ /*! @{ */ #define NETC_SW_ENETC_UNMACECR_PORT0_MASK (0x1U) #define NETC_SW_ENETC_UNMACECR_PORT0_SHIFT (0U) /*! PORT0 - Report disable port */ #define NETC_SW_ENETC_UNMACECR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACECR_PORT0_SHIFT)) & NETC_SW_ENETC_UNMACECR_PORT0_MASK) /*! @} */ /*! @name UNMACESR - Uncorrectable non-fatal MAC error status register */ /*! @{ */ #define NETC_SW_ENETC_UNMACESR_PORT0_MASK (0x1U) #define NETC_SW_ENETC_UNMACESR_PORT0_SHIFT (0U) /*! PORT0 - Port MAC error */ #define NETC_SW_ENETC_UNMACESR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMACESR_PORT0_SHIFT)) & NETC_SW_ENETC_UNMACESR_PORT0_MASK) /*! @} */ /*! @name UNMECR - Uncorrectable non-fatal memory error configuration register */ /*! @{ */ #define NETC_SW_ENETC_UNMECR_THRESHOLD_MASK (0xFFU) #define NETC_SW_ENETC_UNMECR_THRESHOLD_SHIFT (0U) /*! THRESHOLD - Threshold */ #define NETC_SW_ENETC_UNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMECR_THRESHOLD_SHIFT)) & NETC_SW_ENETC_UNMECR_THRESHOLD_MASK) #define NETC_SW_ENETC_UNMECR_RD_MASK (0x80000000U) #define NETC_SW_ENETC_UNMECR_RD_SHIFT (31U) /*! RD - Report disable */ #define NETC_SW_ENETC_UNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMECR_RD_SHIFT)) & NETC_SW_ENETC_UNMECR_RD_MASK) /*! @} */ /*! @name UNMESR0 - Uncorrectable non-fatal memory error status register 0 */ /*! @{ */ #define NETC_SW_ENETC_UNMESR0_LINK_SLICE_ID_MASK (0x1FU) #define NETC_SW_ENETC_UNMESR0_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define NETC_SW_ENETC_UNMESR0_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR0_LINK_SLICE_ID_SHIFT)) & NETC_SW_ENETC_UNMESR0_LINK_SLICE_ID_MASK) #define NETC_SW_ENETC_UNMESR0_MEM_ID_MASK (0x1F00U) #define NETC_SW_ENETC_UNMESR0_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define NETC_SW_ENETC_UNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR0_MEM_ID_SHIFT)) & NETC_SW_ENETC_UNMESR0_MEM_ID_MASK) #define NETC_SW_ENETC_UNMESR0_SYNDROME_MASK (0x7FF0000U) #define NETC_SW_ENETC_UNMESR0_SYNDROME_SHIFT (16U) /*! SYNDROME - Syndrome */ #define NETC_SW_ENETC_UNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR0_SYNDROME_SHIFT)) & NETC_SW_ENETC_UNMESR0_SYNDROME_MASK) #define NETC_SW_ENETC_UNMESR0_MBEE_MASK (0x80000000U) #define NETC_SW_ENETC_UNMESR0_MBEE_SHIFT (31U) /*! MBEE - Multi-bit ECC error */ #define NETC_SW_ENETC_UNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR0_MBEE_SHIFT)) & NETC_SW_ENETC_UNMESR0_MBEE_MASK) /*! @} */ /*! @name UNMESR1 - Uncorrectable non-fatal memory error status register 1 */ /*! @{ */ #define NETC_SW_ENETC_UNMESR1_ADDR_MASK (0xFFFFFFFFU) #define NETC_SW_ENETC_UNMESR1_ADDR_SHIFT (0U) /*! ADDR - Address */ #define NETC_SW_ENETC_UNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMESR1_ADDR_SHIFT)) & NETC_SW_ENETC_UNMESR1_ADDR_MASK) /*! @} */ /*! @name UNMECTR - Uncorrectable non-fatal memory error count register */ /*! @{ */ #define NETC_SW_ENETC_UNMECTR_COUNT_MASK (0xFFU) #define NETC_SW_ENETC_UNMECTR_COUNT_SHIFT (0U) /*! COUNT - Count */ #define NETC_SW_ENETC_UNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UNMECTR_COUNT_SHIFT)) & NETC_SW_ENETC_UNMECTR_COUNT_MASK) /*! @} */ /*! @name UFMECR - Uncorrectable fatal memory error configuration register */ /*! @{ */ #define NETC_SW_ENETC_UFMECR_RD_MASK (0x80000000U) #define NETC_SW_ENETC_UFMECR_RD_SHIFT (31U) /*! RD - Report disable */ #define NETC_SW_ENETC_UFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMECR_RD_SHIFT)) & NETC_SW_ENETC_UFMECR_RD_MASK) /*! @} */ /*! @name UFMESR0 - Uncorrectable fatal memory error status register 0 */ /*! @{ */ #define NETC_SW_ENETC_UFMESR0_LINK_SLICE_ID_MASK (0x1FU) #define NETC_SW_ENETC_UFMESR0_LINK_SLICE_ID_SHIFT (0U) /*! LINK_SLICE_ID - Link or Slice ID */ #define NETC_SW_ENETC_UFMESR0_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_LINK_SLICE_ID_SHIFT)) & NETC_SW_ENETC_UFMESR0_LINK_SLICE_ID_MASK) #define NETC_SW_ENETC_UFMESR0_MEM_ID_MASK (0x1F00U) #define NETC_SW_ENETC_UFMESR0_MEM_ID_SHIFT (8U) /*! MEM_ID - Memory ID */ #define NETC_SW_ENETC_UFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_MEM_ID_SHIFT)) & NETC_SW_ENETC_UFMESR0_MEM_ID_MASK) #define NETC_SW_ENETC_UFMESR0_SYNDROME_MASK (0x7FF0000U) #define NETC_SW_ENETC_UFMESR0_SYNDROME_SHIFT (16U) /*! SYNDROME - Syndrome */ #define NETC_SW_ENETC_UFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_SYNDROME_SHIFT)) & NETC_SW_ENETC_UFMESR0_SYNDROME_MASK) #define NETC_SW_ENETC_UFMESR0_M_MASK (0x40000000U) #define NETC_SW_ENETC_UFMESR0_M_SHIFT (30U) /*! M - Multiple */ #define NETC_SW_ENETC_UFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_M_SHIFT)) & NETC_SW_ENETC_UFMESR0_M_MASK) #define NETC_SW_ENETC_UFMESR0_MBEE_MASK (0x80000000U) #define NETC_SW_ENETC_UFMESR0_MBEE_SHIFT (31U) /*! MBEE - Multi-bit ECC error */ #define NETC_SW_ENETC_UFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR0_MBEE_SHIFT)) & NETC_SW_ENETC_UFMESR0_MBEE_MASK) /*! @} */ /*! @name UFMESR1 - Uncorrectable fatal memory error status register 1 */ /*! @{ */ #define NETC_SW_ENETC_UFMESR1_ADDR_MASK (0xFFFFFFFFU) #define NETC_SW_ENETC_UFMESR1_ADDR_SHIFT (0U) /*! ADDR - Address */ #define NETC_SW_ENETC_UFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_UFMESR1_ADDR_SHIFT)) & NETC_SW_ENETC_UFMESR1_ADDR_MASK) /*! @} */ /*! @name MIRR - MAC interrupt reason register */ /*! @{ */ #define NETC_SW_ENETC_MIRR_PORT0_MASK (0x1U) #define NETC_SW_ENETC_MIRR_PORT0_SHIFT (0U) #define NETC_SW_ENETC_MIRR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_MIRR_PORT0_SHIFT)) & NETC_SW_ENETC_MIRR_PORT0_MASK) /*! @} */ /*! @name MMSIVR - MAC MSI-X vector register */ /*! @{ */ #define NETC_SW_ENETC_MMSIVR_VECTOR_MASK (0x3FU) #define NETC_SW_ENETC_MMSIVR_VECTOR_SHIFT (0U) #define NETC_SW_ENETC_MMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_MMSIVR_VECTOR_SHIFT)) & NETC_SW_ENETC_MMSIVR_VECTOR_MASK) /*! @} */ /*! @name EMDIOIRR - External MDIO interrupt reason register */ /*! @{ */ #define NETC_SW_ENETC_EMDIOIRR_PORT0_MASK (0x1U) #define NETC_SW_ENETC_EMDIOIRR_PORT0_SHIFT (0U) #define NETC_SW_ENETC_EMDIOIRR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOIRR_PORT0_SHIFT)) & NETC_SW_ENETC_EMDIOIRR_PORT0_MASK) /*! @} */ /*! @name EMDIOMSIVR - External MDIO MSI-X vector register */ /*! @{ */ #define NETC_SW_ENETC_EMDIOMSIVR_VECTOR_MASK (0x3FU) #define NETC_SW_ENETC_EMDIOMSIVR_VECTOR_SHIFT (0U) #define NETC_SW_ENETC_EMDIOMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_EMDIOMSIVR_VECTOR_SHIFT)) & NETC_SW_ENETC_EMDIOMSIVR_VECTOR_MASK) /*! @} */ /*! @name CVLANR1 - Custom VLAN EtherType register 1 */ /*! @{ */ #define NETC_SW_ENETC_CVLANR1_ETYPE_MASK (0xFFFFU) #define NETC_SW_ENETC_CVLANR1_ETYPE_SHIFT (0U) #define NETC_SW_ENETC_CVLANR1_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR1_ETYPE_SHIFT)) & NETC_SW_ENETC_CVLANR1_ETYPE_MASK) #define NETC_SW_ENETC_CVLANR1_V_MASK (0x80000000U) #define NETC_SW_ENETC_CVLANR1_V_SHIFT (31U) #define NETC_SW_ENETC_CVLANR1_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR1_V_SHIFT)) & NETC_SW_ENETC_CVLANR1_V_MASK) /*! @} */ /*! @name CVLANR2 - Custom VLAN EtherType register 2 */ /*! @{ */ #define NETC_SW_ENETC_CVLANR2_ETYPE_MASK (0xFFFFU) #define NETC_SW_ENETC_CVLANR2_ETYPE_SHIFT (0U) #define NETC_SW_ENETC_CVLANR2_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR2_ETYPE_SHIFT)) & NETC_SW_ENETC_CVLANR2_ETYPE_MASK) #define NETC_SW_ENETC_CVLANR2_V_MASK (0x80000000U) #define NETC_SW_ENETC_CVLANR2_V_SHIFT (31U) #define NETC_SW_ENETC_CVLANR2_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_CVLANR2_V_SHIFT)) & NETC_SW_ENETC_CVLANR2_V_MASK) /*! @} */ /*! @name DOSL2CR - DoS L2 configuration register */ /*! @{ */ #define NETC_SW_ENETC_DOSL2CR_SAMEADDR_MASK (0x1U) #define NETC_SW_ENETC_DOSL2CR_SAMEADDR_SHIFT (0U) #define NETC_SW_ENETC_DOSL2CR_SAMEADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_DOSL2CR_SAMEADDR_SHIFT)) & NETC_SW_ENETC_DOSL2CR_SAMEADDR_MASK) #define NETC_SW_ENETC_DOSL2CR_MSAMCC_MASK (0x2U) #define NETC_SW_ENETC_DOSL2CR_MSAMCC_SHIFT (1U) #define NETC_SW_ENETC_DOSL2CR_MSAMCC(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_DOSL2CR_MSAMCC_SHIFT)) & NETC_SW_ENETC_DOSL2CR_MSAMCC_MASK) /*! @} */ /*! @name DOSL3CR - DoS L3 configuration register */ /*! @{ */ #define NETC_SW_ENETC_DOSL3CR_SAMEADDR_MASK (0x1U) #define NETC_SW_ENETC_DOSL3CR_SAMEADDR_SHIFT (0U) #define NETC_SW_ENETC_DOSL3CR_SAMEADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_DOSL3CR_SAMEADDR_SHIFT)) & NETC_SW_ENETC_DOSL3CR_SAMEADDR_MASK) /*! @} */ /*! @name VLANIPVMPR0 - VLAN to IPV mapping profile 0 register 0 */ /*! @{ */ #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_MASK (0x7U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_SHIFT (0U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_0_MASK) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_MASK (0x70U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_SHIFT (4U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_1_MASK) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_MASK (0x700U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_SHIFT (8U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_2_MASK) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_MASK (0x7000U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_SHIFT (12U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_3_MASK) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_MASK (0x70000U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_SHIFT (16U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_4_MASK) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_MASK (0x700000U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_SHIFT (20U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_5_MASK) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_MASK (0x7000000U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_SHIFT (24U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_6_MASK) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_MASK (0x70000000U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_SHIFT (28U) #define NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR0_PCP_DEI_7_MASK) /*! @} */ /* The count of NETC_SW_ENETC_VLANIPVMPR0 */ #define NETC_SW_ENETC_VLANIPVMPR0_COUNT (1U) /*! @name VLANIPVMPR1 - VLAN to IPV mapping profile 0 register 1 */ /*! @{ */ #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_MASK (0x7U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_SHIFT (0U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_8_MASK) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_MASK (0x70U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_SHIFT (4U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_9_MASK) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_MASK (0x700U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_SHIFT (8U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_10_MASK) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_MASK (0x7000U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_SHIFT (12U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_11_MASK) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_MASK (0x70000U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_SHIFT (16U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_12_MASK) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_MASK (0x700000U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_SHIFT (20U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_13_MASK) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_MASK (0x7000000U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_SHIFT (24U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_14_MASK) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_MASK (0x70000000U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_SHIFT (28U) #define NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_SHIFT)) & NETC_SW_ENETC_VLANIPVMPR1_PCP_DEI_15_MASK) /*! @} */ /* The count of NETC_SW_ENETC_VLANIPVMPR1 */ #define NETC_SW_ENETC_VLANIPVMPR1_COUNT (1U) /*! @name VLANDRMPR - VLAN to DR mapping profile 0 register */ /*! @{ */ #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_MASK (0x3U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_SHIFT (0U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_0_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_MASK (0xCU) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_SHIFT (2U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_1_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_MASK (0x30U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_SHIFT (4U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_2_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_MASK (0xC0U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_SHIFT (6U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_3_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_MASK (0x300U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_SHIFT (8U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_4_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_MASK (0xC00U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_SHIFT (10U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_5_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_MASK (0x3000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_SHIFT (12U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_6_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_MASK (0xC000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_SHIFT (14U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_7_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_MASK (0x30000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_SHIFT (16U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_8_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_MASK (0xC0000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_SHIFT (18U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_9_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_MASK (0x300000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_SHIFT (20U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_10_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_MASK (0xC00000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_SHIFT (22U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_11_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_MASK (0x3000000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_SHIFT (24U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_12_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_MASK (0xC000000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_SHIFT (26U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_13_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_MASK (0x30000000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_SHIFT (28U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_14_MASK) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_MASK (0xC0000000U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_SHIFT (30U) #define NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_SHIFT)) & NETC_SW_ENETC_VLANDRMPR_PCP_DEI_15_MASK) /*! @} */ /* The count of NETC_SW_ENETC_VLANDRMPR */ #define NETC_SW_ENETC_VLANDRMPR_COUNT (1U) /*! @name IPFCAPR - Ingress port filter capability register */ /*! @{ */ #define NETC_SW_ENETC_IPFCAPR_RP_MASK (0x1U) #define NETC_SW_ENETC_IPFCAPR_RP_SHIFT (0U) #define NETC_SW_ENETC_IPFCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_RP_SHIFT)) & NETC_SW_ENETC_IPFCAPR_RP_MASK) #define NETC_SW_ENETC_IPFCAPR_ISID_MASK (0x2U) #define NETC_SW_ENETC_IPFCAPR_ISID_SHIFT (1U) #define NETC_SW_ENETC_IPFCAPR_ISID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_ISID_SHIFT)) & NETC_SW_ENETC_IPFCAPR_ISID_MASK) #define NETC_SW_ENETC_IPFCAPR_FWD_SI_MASK (0x4U) #define NETC_SW_ENETC_IPFCAPR_FWD_SI_SHIFT (2U) #define NETC_SW_ENETC_IPFCAPR_FWD_SI(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_FWD_SI_SHIFT)) & NETC_SW_ENETC_IPFCAPR_FWD_SI_MASK) #define NETC_SW_ENETC_IPFCAPR_WOL_MASK (0x8U) #define NETC_SW_ENETC_IPFCAPR_WOL_SHIFT (3U) #define NETC_SW_ENETC_IPFCAPR_WOL(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFCAPR_WOL_SHIFT)) & NETC_SW_ENETC_IPFCAPR_WOL_MASK) /*! @} */ /*! @name IPFTCAPR - Ingress port filter table capability register */ /*! @{ */ #define NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_IPFTCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_IPFTCAPR_NUM_WORDS_MASK) /*! @} */ /*! @name IPFTMOR - Ingress port filter table memory operational register */ /*! @{ */ #define NETC_SW_ENETC_IPFTMOR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_IPFTMOR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_IPFTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_IPFTMOR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_IPFTMOR_NUM_WORDS_MASK) /*! @} */ /*! @name ITMCAPR - Index table memory capability register */ /*! @{ */ #define NETC_SW_ENETC_ITMCAPR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_ITMCAPR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_ITMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ITMCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_ITMCAPR_NUM_WORDS_MASK) #define NETC_SW_ENETC_ITMCAPR_WORD_SIZE_MASK (0x30000000U) #define NETC_SW_ENETC_ITMCAPR_WORD_SIZE_SHIFT (28U) #define NETC_SW_ENETC_ITMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ITMCAPR_WORD_SIZE_SHIFT)) & NETC_SW_ENETC_ITMCAPR_WORD_SIZE_MASK) #define NETC_SW_ENETC_ITMCAPR_MLOC_MASK (0xC0000000U) #define NETC_SW_ENETC_ITMCAPR_MLOC_SHIFT (30U) #define NETC_SW_ENETC_ITMCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ITMCAPR_MLOC_SHIFT)) & NETC_SW_ENETC_ITMCAPR_MLOC_MASK) /*! @} */ /*! @name RPCAPR - Rate policer capability register */ /*! @{ */ #define NETC_SW_ENETC_RPCAPR_TRTCM_MASK (0x1U) #define NETC_SW_ENETC_RPCAPR_TRTCM_SHIFT (0U) #define NETC_SW_ENETC_RPCAPR_TRTCM(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPCAPR_TRTCM_SHIFT)) & NETC_SW_ENETC_RPCAPR_TRTCM_MASK) #define NETC_SW_ENETC_RPCAPR_CM_MASK (0x2U) #define NETC_SW_ENETC_RPCAPR_CM_SHIFT (1U) #define NETC_SW_ENETC_RPCAPR_CM(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPCAPR_CM_SHIFT)) & NETC_SW_ENETC_RPCAPR_CM_MASK) /*! @} */ /*! @name RPITCAPR - Rate policer index table capability register */ /*! @{ */ #define NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_MASK (0x3FFFU) #define NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_RPITCAPR_NUM_ENTRIES_MASK) /*! @} */ /*! @name RPITMAR - Rate policer index table memory allocation register */ /*! @{ */ #define NETC_SW_ENETC_RPITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_RPITMAR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_RPITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_RPITMAR_NUM_WORDS_MASK) /*! @} */ /*! @name RPITOR - Rate policer index table operational register */ /*! @{ */ #define NETC_SW_ENETC_RPITOR_NUM_ENTRIES_MASK (0x3FFFU) #define NETC_SW_ENETC_RPITOR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_RPITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_RPITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_RPITOR_NUM_ENTRIES_MASK) /*! @} */ /*! @name ISCITCAPR - Ingress stream counter index table capability register */ /*! @{ */ #define NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISCITCAPR_NUM_ENTRIES_MASK) /*! @} */ /*! @name ISCITMAR - Ingress stream counter index table memory allocation register */ /*! @{ */ #define NETC_SW_ENETC_ISCITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_ISCITMAR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_ISCITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_ISCITMAR_NUM_WORDS_MASK) /*! @} */ /*! @name ISCITOR - Ingress stream counter index table operational register */ /*! @{ */ #define NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_ISCITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISCITOR_NUM_ENTRIES_MASK) /*! @} */ /*! @name ISCAPR - Ingress stream capability register */ /*! @{ */ #define NETC_SW_ENETC_ISCAPR_SG_MASK (0x8U) #define NETC_SW_ENETC_ISCAPR_SG_SHIFT (3U) #define NETC_SW_ENETC_ISCAPR_SG(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_SG_SHIFT)) & NETC_SW_ENETC_ISCAPR_SG_MASK) #define NETC_SW_ENETC_ISCAPR_RP_MASK (0x10U) #define NETC_SW_ENETC_ISCAPR_RP_SHIFT (4U) #define NETC_SW_ENETC_ISCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_RP_SHIFT)) & NETC_SW_ENETC_ISCAPR_RP_MASK) #define NETC_SW_ENETC_ISCAPR_MAXSDU_MASK (0x20U) #define NETC_SW_ENETC_ISCAPR_MAXSDU_SHIFT (5U) #define NETC_SW_ENETC_ISCAPR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_MAXSDU_SHIFT)) & NETC_SW_ENETC_ISCAPR_MAXSDU_MASK) #define NETC_SW_ENETC_ISCAPR_FWD_MASK (0x200U) #define NETC_SW_ENETC_ISCAPR_FWD_SHIFT (9U) #define NETC_SW_ENETC_ISCAPR_FWD(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISCAPR_FWD_SHIFT)) & NETC_SW_ENETC_ISCAPR_FWD_MASK) /*! @} */ /*! @name ISITCAPR - Ingress stream index table capability register */ /*! @{ */ #define NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISITCAPR_NUM_ENTRIES_MASK) /*! @} */ /*! @name ISITMAR - Ingress stream index table memory allocation register */ /*! @{ */ #define NETC_SW_ENETC_ISITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_ISITMAR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_ISITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_ISITMAR_NUM_WORDS_MASK) /*! @} */ /*! @name ISITOR - Ingress stream index table operational register */ /*! @{ */ #define NETC_SW_ENETC_ISITOR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_ISITOR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_ISITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISITOR_NUM_ENTRIES_MASK) /*! @} */ /*! @name SGCAPR - Stream gate capability register */ /*! @{ */ #define NETC_SW_ENETC_SGCAPR_GLC_AO_MASK (0x1U) #define NETC_SW_ENETC_SGCAPR_GLC_AO_SHIFT (0U) #define NETC_SW_ENETC_SGCAPR_GLC_AO(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_AO_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_AO_MASK) #define NETC_SW_ENETC_SGCAPR_GLC_GC_MASK (0x2U) #define NETC_SW_ENETC_SGCAPR_GLC_GC_SHIFT (1U) #define NETC_SW_ENETC_SGCAPR_GLC_GC(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_GC_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_GC_MASK) #define NETC_SW_ENETC_SGCAPR_GLC_IO_MASK (0x4U) #define NETC_SW_ENETC_SGCAPR_GLC_IO_SHIFT (2U) #define NETC_SW_ENETC_SGCAPR_GLC_IO(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_IO_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_IO_MASK) #define NETC_SW_ENETC_SGCAPR_GLC_IPV_MASK (0x8U) #define NETC_SW_ENETC_SGCAPR_GLC_IPV_SHIFT (3U) #define NETC_SW_ENETC_SGCAPR_GLC_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_IPV_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_IPV_MASK) #define NETC_SW_ENETC_SGCAPR_GLC_CTD_MASK (0x10U) #define NETC_SW_ENETC_SGCAPR_GLC_CTD_SHIFT (4U) #define NETC_SW_ENETC_SGCAPR_GLC_CTD(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCAPR_GLC_CTD_SHIFT)) & NETC_SW_ENETC_SGCAPR_GLC_CTD_MASK) /*! @} */ /*! @name SGIITCAPR - Stream gate instance index table capability register */ /*! @{ */ #define NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_SGIITCAPR_NUM_ENTRIES_MASK) /*! @} */ /*! @name SGIITMAR - Stream gate instance index table memory allocation register */ /*! @{ */ #define NETC_SW_ENETC_SGIITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_SGIITMAR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_SGIITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGIITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGIITMAR_NUM_WORDS_MASK) /*! @} */ /*! @name SGIITOR - Stream gate instance index table operational register */ /*! @{ */ #define NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_SGIITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_SGIITOR_NUM_ENTRIES_MASK) /*! @} */ /*! @name SGCLITCAPR - Stream gate control list index table capability register */ /*! @{ */ #define NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGCLITCAPR_NUM_WORDS_MASK) /*! @} */ /*! @name SGCLITMAR - Stream gate control list index table memory allocation register */ /*! @{ */ #define NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_SGCLITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGCLITMAR_NUM_WORDS_MASK) /*! @} */ /*! @name SGCLTMOR - Stream gate control list table memory operational register */ /*! @{ */ #define NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_SGCLTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_SGCLTMOR_NUM_WORDS_MASK) /*! @} */ /*! @name TGSTCAPR - Time gate scheduling table capability register */ /*! @{ */ #define NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_TGSTCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_TGSTCAPR_NUM_WORDS_MASK) /*! @} */ /*! @name TGSTMOR - Time gate scheduling table memory operation register */ /*! @{ */ #define NETC_SW_ENETC_TGSTMOR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_TGSTMOR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_TGSTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_TGSTMOR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_TGSTMOR_NUM_WORDS_MASK) /*! @} */ /*! @name HTMCAPR - Hash table memory capability register */ /*! @{ */ #define NETC_SW_ENETC_HTMCAPR_NUM_WORDS_MASK (0xFFFFU) #define NETC_SW_ENETC_HTMCAPR_NUM_WORDS_SHIFT (0U) #define NETC_SW_ENETC_HTMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMCAPR_NUM_WORDS_SHIFT)) & NETC_SW_ENETC_HTMCAPR_NUM_WORDS_MASK) #define NETC_SW_ENETC_HTMCAPR_WORD_SIZE_MASK (0x30000000U) #define NETC_SW_ENETC_HTMCAPR_WORD_SIZE_SHIFT (28U) #define NETC_SW_ENETC_HTMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMCAPR_WORD_SIZE_SHIFT)) & NETC_SW_ENETC_HTMCAPR_WORD_SIZE_MASK) #define NETC_SW_ENETC_HTMCAPR_MLOC_MASK (0xC0000000U) #define NETC_SW_ENETC_HTMCAPR_MLOC_SHIFT (30U) #define NETC_SW_ENETC_HTMCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMCAPR_MLOC_SHIFT)) & NETC_SW_ENETC_HTMCAPR_MLOC_MASK) /*! @} */ /*! @name HTMOR - Hash table memory operational register */ /*! @{ */ #define NETC_SW_ENETC_HTMOR_AMOUNT_MASK (0xFFFFU) #define NETC_SW_ENETC_HTMOR_AMOUNT_SHIFT (0U) #define NETC_SW_ENETC_HTMOR_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMOR_AMOUNT_SHIFT)) & NETC_SW_ENETC_HTMOR_AMOUNT_MASK) #define NETC_SW_ENETC_HTMOR_WATERMARK_MASK (0xFFFF0000U) #define NETC_SW_ENETC_HTMOR_WATERMARK_SHIFT (16U) #define NETC_SW_ENETC_HTMOR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_HTMOR_WATERMARK_SHIFT)) & NETC_SW_ENETC_HTMOR_WATERMARK_MASK) /*! @} */ /*! @name ISIDCAPR - Ingress stream identification capability register */ /*! @{ */ #define NETC_SW_ENETC_ISIDCAPR_NUM_KC_MASK (0x3U) #define NETC_SW_ENETC_ISIDCAPR_NUM_KC_SHIFT (0U) #define NETC_SW_ENETC_ISIDCAPR_NUM_KC(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_NUM_KC_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_NUM_KC_MASK) #define NETC_SW_ENETC_ISIDCAPR_NUM_PF_MASK (0x1CU) #define NETC_SW_ENETC_ISIDCAPR_NUM_PF_SHIFT (2U) #define NETC_SW_ENETC_ISIDCAPR_NUM_PF(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_NUM_PF_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_NUM_PF_MASK) #define NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_MASK (0x1F00U) #define NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_SHIFT (8U) #define NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_MAX_KSIZE_MASK) #define NETC_SW_ENETC_ISIDCAPR_UFT_MASK (0x10000U) #define NETC_SW_ENETC_ISIDCAPR_UFT_SHIFT (16U) #define NETC_SW_ENETC_ISIDCAPR_UFT(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_UFT_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_UFT_MASK) #define NETC_SW_ENETC_ISIDCAPR_ETHFT_MASK (0x20000U) #define NETC_SW_ENETC_ISIDCAPR_ETHFT_SHIFT (17U) #define NETC_SW_ENETC_ISIDCAPR_ETHFT(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDCAPR_ETHFT_SHIFT)) & NETC_SW_ENETC_ISIDCAPR_ETHFT_MASK) /*! @} */ /*! @name ISIDKC0OR - Ingress stream identification key construction 0 operational register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISIDKC0OR_NUM_ENTRIES_MASK) #define NETC_SW_ENETC_ISIDKC0OR_EN_MASK (0x80000000U) #define NETC_SW_ENETC_ISIDKC0OR_EN_SHIFT (31U) #define NETC_SW_ENETC_ISIDKC0OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0OR_EN_SHIFT)) & NETC_SW_ENETC_ISIDKC0OR_EN_MASK) /*! @} */ /*! @name ISIDKC0CR0 - Ingress stream identification key construction 0 configuration register 0 */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC0CR0_VALID_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC0CR0_VALID_SHIFT (0U) /*! VALID - Valid * 0b0..The entire key construction rule is not valid including any configuration payload key fields defined. * 0b1..The key construction rule is valid. */ #define NETC_SW_ENETC_ISIDKC0CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_VALID_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_VALID_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_PORTP_MASK (0x2U) #define NETC_SW_ENETC_ISIDKC0CR0_PORTP_SHIFT (1U) /*! PORTP - Source Port Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC0CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_PORTP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_PORTP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_DMACP_MASK (0x8U) #define NETC_SW_ENETC_ISIDKC0CR0_DMACP_SHIFT (3U) /*! DMACP - Destination MAC (address) Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC0CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_DMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_DMACP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_SMACP_MASK (0x10U) #define NETC_SW_ENETC_ISIDKC0CR0_SMACP_SHIFT (4U) /*! SMACP - Source MAC (address) Present. * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC0CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_SMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_SMACP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP_MASK (0x20U) #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP_SHIFT (5U) /*! OVIDP - Outer VID Present * 0b0..Outer VLAN ID is not present in the key * 0b1..Outer VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC0CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_OVIDP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_OPCPP_MASK (0x40U) #define NETC_SW_ENETC_ISIDKC0CR0_OPCPP_SHIFT (6U) /*! OPCPP - Outer PCP Present * 0b0..Outer PCP is not present in the key * 0b1..Outer PCP is present in the key */ #define NETC_SW_ENETC_ISIDKC0CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_OPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_OPCPP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP_MASK (0x80U) #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP_SHIFT (7U) /*! IVIDP - Inner VID Present * 0b0..Inner VLAN ID is not present in the key * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC0CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_IVIDP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP_MASK (0x100U) #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP_SHIFT (8U) /*! IPCPP - Inner PCP Present * 0b0..Inner VLAN ID is not present in the key * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC0CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_IPCPP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_SQTP_MASK (0x200U) #define NETC_SW_ENETC_ISIDKC0CR0_SQTP_SHIFT (9U) /*! SQTP - Sequence Tag (code point) Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC0CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_SQTP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_SQTP_MASK) #define NETC_SW_ENETC_ISIDKC0CR0_ETP_MASK (0x400U) #define NETC_SW_ENETC_ISIDKC0CR0_ETP_SHIFT (10U) /*! ETP - EtherType Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC0CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0CR0_ETP_SHIFT)) & NETC_SW_ENETC_ISIDKC0CR0_ETP_MASK) /*! @} */ /*! @name ISIDKC0PF0CR - Ingress stream identification key construction 0 payload field 0 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC0PF0CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC0PF0CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC0PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF0CR_LBMASK_MASK) /*! @} */ /*! @name ISIDKC0PF1CR - Ingress stream identification key construction 0 payload field 1 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC0PF1CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC0PF1CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC0PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF1CR_LBMASK_MASK) /*! @} */ /*! @name ISIDKC0PF2CR - Ingress stream identification key construction 0 payload field 2 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC0PF2CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC0PF2CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC0PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF2CR_LBMASK_MASK) /*! @} */ /*! @name ISIDKC0PF3CR - Ingress stream identification key construction 0 payload field 3 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC0PF3CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC0PF3CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC0PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC0PF3CR_LBMASK_MASK) /*! @} */ /*! @name ISIDKC1OR - Ingress stream identification key construction 1 operational register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISIDKC1OR_NUM_ENTRIES_MASK) #define NETC_SW_ENETC_ISIDKC1OR_EN_MASK (0x80000000U) #define NETC_SW_ENETC_ISIDKC1OR_EN_SHIFT (31U) #define NETC_SW_ENETC_ISIDKC1OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1OR_EN_SHIFT)) & NETC_SW_ENETC_ISIDKC1OR_EN_MASK) /*! @} */ /*! @name ISIDKC1CR0 - Ingress stream identification key construction 1 configuration register 0 */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC1CR0_VALID_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC1CR0_VALID_SHIFT (0U) /*! VALID - Valid * 0b0..The entire key construction rule is not valid including any configuration payload key fields defined. * 0b1..The key construction rule is valid. */ #define NETC_SW_ENETC_ISIDKC1CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_VALID_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_VALID_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_PORTP_MASK (0x2U) #define NETC_SW_ENETC_ISIDKC1CR0_PORTP_SHIFT (1U) /*! PORTP - Source Port Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC1CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_PORTP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_PORTP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_DMACP_MASK (0x8U) #define NETC_SW_ENETC_ISIDKC1CR0_DMACP_SHIFT (3U) /*! DMACP - Destination MAC (address) Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC1CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_DMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_DMACP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_SMACP_MASK (0x10U) #define NETC_SW_ENETC_ISIDKC1CR0_SMACP_SHIFT (4U) /*! SMACP - Source MAC (address) Present. * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC1CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_SMACP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_SMACP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP_MASK (0x20U) #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP_SHIFT (5U) /*! OVIDP - Outer VID Present * 0b0..Outer VLAN ID is not present in the key * 0b1..Outer VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC1CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_OVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_OVIDP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_OPCPP_MASK (0x40U) #define NETC_SW_ENETC_ISIDKC1CR0_OPCPP_SHIFT (6U) /*! OPCPP - Outer PCP Present * 0b0..Outer PCP is not present in the key * 0b1..Outer PCP is present in the key */ #define NETC_SW_ENETC_ISIDKC1CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_OPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_OPCPP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP_MASK (0x80U) #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP_SHIFT (7U) /*! IVIDP - Inner VID Present * 0b0..Inner VLAN ID is not present in the key * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC1CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_IVIDP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_IVIDP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP_MASK (0x100U) #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP_SHIFT (8U) /*! IPCPP - Inner PCP Present * 0b0..Inner VLAN ID is not present in the key * 0b1..Inner VLAN ID is present in the key */ #define NETC_SW_ENETC_ISIDKC1CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_IPCPP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_IPCPP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_SQTP_MASK (0x200U) #define NETC_SW_ENETC_ISIDKC1CR0_SQTP_SHIFT (9U) /*! SQTP - Sequence Tag (code point) Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC1CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_SQTP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_SQTP_MASK) #define NETC_SW_ENETC_ISIDKC1CR0_ETP_MASK (0x400U) #define NETC_SW_ENETC_ISIDKC1CR0_ETP_SHIFT (10U) /*! ETP - EtherType Present * 0b0..Not present * 0b1..Present */ #define NETC_SW_ENETC_ISIDKC1CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1CR0_ETP_SHIFT)) & NETC_SW_ENETC_ISIDKC1CR0_ETP_MASK) /*! @} */ /*! @name ISIDKC1PF0CR - Ingress stream identification key construction 1 payload field 0 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC1PF0CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC1PF0CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC1PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF0CR_LBMASK_MASK) /*! @} */ /*! @name ISIDKC1PF1CR - Ingress stream identification key construction 1 payload field 1 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC1PF1CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC1PF1CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC1PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF1CR_LBMASK_MASK) /*! @} */ /*! @name ISIDKC1PF2CR - Ingress stream identification key construction 1 payload field 2 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC1PF2CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC1PF2CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC1PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF2CR_LBMASK_MASK) /*! @} */ /*! @name ISIDKC1PF3CR - Ingress stream identification key construction 1 payload field 3 configuration register */ /*! @{ */ #define NETC_SW_ENETC_ISIDKC1PF3CR_PFP_MASK (0x1U) #define NETC_SW_ENETC_ISIDKC1PF3CR_PFP_SHIFT (0U) #define NETC_SW_ENETC_ISIDKC1PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_PFP_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_PFP_MASK) #define NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_MASK (0x1EU) #define NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_SHIFT (1U) #define NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_NUM_BYTES_MASK) #define NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_MASK (0x7F00U) #define NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT (8U) #define NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_BYTE_OFFSET_MASK) #define NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_MASK (0x70000U) #define NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_SHIFT (16U) #define NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_FBMASK_MASK) #define NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_MASK (0x700000U) #define NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_SHIFT (20U) #define NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_SHIFT)) & NETC_SW_ENETC_ISIDKC1PF3CR_LBMASK_MASK) /*! @} */ /*! @name ISFHTOR - Ingress stream filter hash table operational register */ /*! @{ */ #define NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_MASK (0xFFFFU) #define NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_SHIFT (0U) #define NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_SHIFT)) & NETC_SW_ENETC_ISFHTOR_NUM_ENTRIES_MASK) /*! @} */ /*! * @} */ /* end of group NETC_SW_ENETC_Register_Masks */ /* NETC_SW_ENETC - Peripheral instance base addresses */ /** Peripheral ENETC0_COMMON base address */ #define ENETC0_COMMON_BASE (0x4CC11000u) /** Peripheral ENETC0_COMMON base pointer */ #define ENETC0_COMMON ((NETC_SW_ENETC_Type *)ENETC0_COMMON_BASE) /** Peripheral ENETC1_COMMON base address */ #define ENETC1_COMMON_BASE (0x4CC51000u) /** Peripheral ENETC1_COMMON base pointer */ #define ENETC1_COMMON ((NETC_SW_ENETC_Type *)ENETC1_COMMON_BASE) /** Peripheral ENETC2_COMMON base address */ #define ENETC2_COMMON_BASE (0x4CC91000u) /** Peripheral ENETC2_COMMON base pointer */ #define ENETC2_COMMON ((NETC_SW_ENETC_Type *)ENETC2_COMMON_BASE) /** Array initializer of NETC_SW_ENETC peripheral base addresses */ #define NETC_SW_ENETC_BASE_ADDRS { ENETC0_COMMON_BASE, ENETC1_COMMON_BASE, ENETC2_COMMON_BASE } /** Array initializer of NETC_SW_ENETC peripheral base pointers */ #define NETC_SW_ENETC_BASE_PTRS { ENETC0_COMMON, ENETC1_COMMON, ENETC2_COMMON } /*! * @} */ /* end of group NETC_SW_ENETC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NETC_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_TCU_Peripheral_Access_Layer NETC_TCU Peripheral Access Layer * @{ */ /** NETC_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[252]; __IO uint32_t TCU_SCM; /**< SCM test mode, offset: 0x510 */ uint8_t RESERVED_3[12]; __IO uint32_t TCU_SCM_SEL; /**< SCM test sel, offset: 0x520 */ uint8_t RESERVED_4[12]; __IO uint32_t TCU_ENET_BS; /**< enet_bs test mode, offset: 0x530 */ uint8_t RESERVED_5[44]; __IO uint32_t TCU_DFT_DIVIDER; /**< observe MIX divider state and override it, offset: 0x560 */ uint8_t RESERVED_6[764]; __IO uint32_t TCU_ENET_REF_CLK_SEL; /**< clock select, offset: 0x860 */ uint8_t RESERVED_7[924]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_8[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } NETC_TCU_Type; /* ---------------------------------------------------------------------------- -- NETC_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NETC_TCU_Register_Masks NETC_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define NETC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define NETC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define NETC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & NETC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define NETC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define NETC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define NETC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & NETC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_SCM - SCM test mode */ /*! @{ */ #define NETC_TCU_TCU_SCM_scm_test_mode_MASK (0x1U) #define NETC_TCU_TCU_SCM_scm_test_mode_SHIFT (0U) /*! scm_test_mode - SCM test mode */ #define NETC_TCU_TCU_SCM_scm_test_mode(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_SCM_scm_test_mode_SHIFT)) & NETC_TCU_TCU_SCM_scm_test_mode_MASK) #define NETC_TCU_TCU_SCM_scm_obst_rst_b_MASK (0x2U) #define NETC_TCU_TCU_SCM_scm_obst_rst_b_SHIFT (1U) /*! scm_obst_rst_b - SCM obst rst b */ #define NETC_TCU_TCU_SCM_scm_obst_rst_b(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_SCM_scm_obst_rst_b_SHIFT)) & NETC_TCU_TCU_SCM_scm_obst_rst_b_MASK) #define NETC_TCU_TCU_SCM_scm_result_MASK (0x3FFFCU) #define NETC_TCU_TCU_SCM_scm_result_SHIFT (2U) /*! scm_result - SCM results */ #define NETC_TCU_TCU_SCM_scm_result(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_SCM_scm_result_SHIFT)) & NETC_TCU_TCU_SCM_scm_result_MASK) /*! @} */ /*! @name TCU_SCM_SEL - SCM test sel */ /*! @{ */ #define NETC_TCU_TCU_SCM_SEL_scm_sel_MASK (0xFFFFFFFFU) #define NETC_TCU_TCU_SCM_SEL_scm_sel_SHIFT (0U) /*! scm_sel - SCM clock sel */ #define NETC_TCU_TCU_SCM_SEL_scm_sel(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_SCM_SEL_scm_sel_SHIFT)) & NETC_TCU_TCU_SCM_SEL_scm_sel_MASK) /*! @} */ /*! @name TCU_ENET_BS - enet_bs test mode */ /*! @{ */ #define NETC_TCU_TCU_ENET_BS_enet_bs_tdi_MASK (0x1U) #define NETC_TCU_TCU_ENET_BS_enet_bs_tdi_SHIFT (0U) /*! enet_bs_tdi - enet_bs tdi */ #define NETC_TCU_TCU_ENET_BS_enet_bs_tdi(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_tdi_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_tdi_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_acmode_MASK (0x2U) #define NETC_TCU_TCU_ENET_BS_enet_bs_acmode_SHIFT (1U) /*! enet_bs_acmode - enet_bs_acmode */ #define NETC_TCU_TCU_ENET_BS_enet_bs_acmode(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_acmode_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_acmode_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_actest_MASK (0x4U) #define NETC_TCU_TCU_ENET_BS_enet_bs_actest_SHIFT (2U) /*! enet_bs_actest - enet_bs_actest */ #define NETC_TCU_TCU_ENET_BS_enet_bs_actest(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_actest_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_actest_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_cdr_MASK (0x8U) #define NETC_TCU_TCU_ENET_BS_enet_bs_cdr_SHIFT (3U) /*! enet_bs_cdr - enet_bs_cdr */ #define NETC_TCU_TCU_ENET_BS_enet_bs_cdr(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_cdr_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_cdr_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_udr_MASK (0x10U) #define NETC_TCU_TCU_ENET_BS_enet_bs_udr_SHIFT (4U) /*! enet_bs_udr - enet_bs_udr */ #define NETC_TCU_TCU_ENET_BS_enet_bs_udr(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_udr_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_udr_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_ce_MASK (0x20U) #define NETC_TCU_TCU_ENET_BS_enet_bs_ce_SHIFT (5U) /*! enet_bs_ce - enet_bs_ce */ #define NETC_TCU_TCU_ENET_BS_enet_bs_ce(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_ce_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_ce_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_init_MASK (0x40U) #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_init_SHIFT (6U) /*! enet_bs_rx_init - enet_bs_rx_init */ #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_init(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_rx_init_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_rx_init_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_sdr_MASK (0x80U) #define NETC_TCU_TCU_ENET_BS_enet_bs_sdr_SHIFT (7U) /*! enet_bs_sdr - enet_bs_sdr */ #define NETC_TCU_TCU_ENET_BS_enet_bs_sdr(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_sdr_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_sdr_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_tx_lowswing_MASK (0x100U) #define NETC_TCU_TCU_ENET_BS_enet_bs_tx_lowswing_SHIFT (8U) /*! enet_bs_tx_lowswing - enet_bs_tx_lowswing */ #define NETC_TCU_TCU_ENET_BS_enet_bs_tx_lowswing(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_tx_lowswing_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_tx_lowswing_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_bigswing_MASK (0x200U) #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_bigswing_SHIFT (9U) /*! enet_bs_rx_bigswing - enet_bs_rx_bigswing */ #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_bigswing(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_rx_bigswing_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_rx_bigswing_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_level_MASK (0x7C00U) #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_level_SHIFT (10U) /*! enet_bs_rx_level - enet_bs_rx_level */ #define NETC_TCU_TCU_ENET_BS_enet_bs_rx_level(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_rx_level_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_rx_level_MASK) #define NETC_TCU_TCU_ENET_BS_enet_bs_tdo_MASK (0x80000000U) #define NETC_TCU_TCU_ENET_BS_enet_bs_tdo_SHIFT (31U) /*! enet_bs_tdo - enet_bs_tdo */ #define NETC_TCU_TCU_ENET_BS_enet_bs_tdo(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_BS_enet_bs_tdo_SHIFT)) & NETC_TCU_TCU_ENET_BS_enet_bs_tdo_MASK) /*! @} */ /*! @name TCU_DFT_DIVIDER - observe MIX divider state and override it */ /*! @{ */ #define NETC_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_MASK (0x1U) #define NETC_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_SHIFT (0U) /*! tcu_dft_divider_disable - dft divider disable */ #define NETC_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_SHIFT)) & NETC_TCU_TCU_DFT_DIVIDER_tcu_dft_divider_disable_MASK) /*! @} */ /*! @name TCU_ENET_REF_CLK_SEL - clock select */ /*! @{ */ #define NETC_TCU_TCU_ENET_REF_CLK_SEL_enet_ref_clk_sel_MASK (0x1U) #define NETC_TCU_TCU_ENET_REF_CLK_SEL_enet_ref_clk_sel_SHIFT (0U) /*! enet_ref_clk_sel - clock select */ #define NETC_TCU_TCU_ENET_REF_CLK_SEL_enet_ref_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_ENET_REF_CLK_SEL_enet_ref_clk_sel_SHIFT)) & NETC_TCU_TCU_ENET_REF_CLK_SEL_enet_ref_clk_sel_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define NETC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define NETC_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & NETC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define NETC_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & NETC_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define NETC_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & NETC_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define NETC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & NETC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define NETC_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & NETC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define NETC_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define NETC_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & NETC_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define NETC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define NETC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define NETC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & NETC_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define NETC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_MASK (0x2U) #define NETC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_SHIFT (1U) /*! tcu_fuse_obs_1 - fuse observation */ #define NETC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_SHIFT)) & NETC_TCU_TCU_DFT_FUSE_tcu_fuse_obs_1_MASK) /*! @} */ /*! * @} */ /* end of group NETC_TCU_Register_Masks */ /* NETC_TCU - Peripheral instance base addresses */ /** Peripheral NETC__TCU base address */ #define NETC__TCU_BASE (0x4C800000u) /** Peripheral NETC__TCU base pointer */ #define NETC__TCU ((NETC_TCU_Type *)NETC__TCU_BASE) /** Array initializer of NETC_TCU peripheral base addresses */ #define NETC_TCU_BASE_ADDRS { NETC__TCU_BASE } /** Array initializer of NETC_TCU peripheral base pointers */ #define NETC_TCU_BASE_PTRS { NETC__TCU } /*! * @} */ /* end of group NETC_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NEUTRON Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NEUTRON_Peripheral_Access_Layer NEUTRON Peripheral Access Layer * @{ */ /** NEUTRON - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL; /**< Control, offset: 0x0 */ __IO uint32_t FORMAT; /**< Format, offset: 0x4 */ __IO uint32_t LENGTH; /**< Length, offset: 0x8 */ __IO uint32_t WEIGHTBASE; /**< Weight Base, offset: 0xC */ __IO uint32_t BIASBASE; /**< Bias Base Address, offset: 0x10 */ __IO uint32_t ARGMAXBASE; /**< Base address for ARGMAX indices, offset: 0x14 */ __IO uint32_t SCALEBASE; /**< Scale Base, offset: 0x18 */ __IO uint32_t ACTCTRL; /**< Activation Control, offset: 0x1C */ __IO uint32_t DEQUANT; /**< Dequant, offset: 0x20 */ __IO uint32_t BATCH; /**< Batch Count, offset: 0x24 */ __IO uint32_t RESCTRL; /**< Result Control, offset: 0x28 */ __IO uint32_t RES_Y; /**< Result Writer Configuration Y, offset: 0x2C */ __IO uint32_t RES_X; /**< Result Writer Configuration X, offset: 0x30 */ uint8_t RESERVED_0[4]; __IO uint32_t ASYMCTRL; /**< Asymmetric Control Register, offset: 0x38 */ __IO uint32_t FLUSH; /**< Flush, offset: 0x3C */ __IO uint32_t INTR; /**< Interrupt, offset: 0x40 */ __IO uint32_t WEIGHTCTRL; /**< Weight Control, offset: 0x44 */ __IO uint32_t CIRCADDR; /**< Circular Address, offset: 0x48 */ __IO uint32_t PROGSEQ; /**< PROGSEQ, offset: 0x4C */ __IO uint32_t SCRATCH0_2[3]; /**< Scratch Register 0..Scratch Register 2, array offset: 0x50, array step: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t CODEBOOK[16]; /**< Codebook Register 0..Codebook Register 15, array offset: 0x60, array step: 0x4 */ __IO uint32_t CANVAS_SIZE; /**< Canvas Size, offset: 0xA0 */ __IO uint32_t CANVAS_READ_CONV; /**< Canvas Conv, offset: 0xA4 */ __IO uint32_t CANVAS_LOAD_PAD; /**< Canvas Load Pad, offset: 0xA8 */ __IO uint32_t CANVAS_LOAD_Y; /**< Y Dimension Stride, offset: 0xAC */ __IO uint32_t CANVAS_LOAD_X; /**< X Dimension Stride, offset: 0xB0 */ __IO uint32_t CANVAS_LOAD_BATCH; /**< Canvas Load Batch, offset: 0xB4 */ __IO uint32_t CANVAS_LOAD_OUTER_BATCH; /**< Canvas Load Outer Batch, offset: 0xB8 */ __IO uint32_t CANVAS_SECONDARY_READ; /**< Canvas Secondary Read, offset: 0xBC */ __IO uint32_t CANVAS_SECOND_Y_ADJ; /**< CANVAS_SECOND_Y_ADJ, offset: 0xC0 */ __IO uint32_t CANVAS_PDS_POS; /**< CANVAS Pad Data Supervisor Position, offset: 0xC4 */ __IO uint32_t CANVAS_PDS_PAD; /**< CANVAS Pad Data Supervisor Padding, offset: 0xC8 */ __IO uint32_t CANVAS_PDS_STRIDES; /**< CANVAS Pad Data Supervisor Strides, offset: 0xCC */ __IO uint32_t SCRATCH3_5[3]; /**< Scratch Register 0..Scratch Register 2, array offset: 0xD0, array step: 0x4 */ uint8_t RESERVED_2[4]; __IO uint32_t ACTCTRL2; /**< Activation Control, offset: 0xE0 */ __IO uint32_t INTERPOLBASE; /**< Interpolator Base Address, offset: 0xE4 */ __IO uint32_t CANVAS_PDS_INP; /**< CANVAS Pad Data Supervisor Input, offset: 0xE8 */ __IO uint32_t CANVAS_SECOND_X_ADJ; /**< CANVAS_SECOND_X_ADJ, offset: 0xEC */ __IO uint32_t INTERPOLOFF; /**< Interpolator Offset, offset: 0xF0 */ __IO uint32_t ACTCTRL3; /**< Activation scale, offset: 0xF4 */ uint8_t RESERVED_3[8]; __IO uint32_t DATABASE; /**< Base address for Data Canvas loading, offset: 0x100 */ uint8_t RESERVED_4[124]; __IO uint32_t RESBASE; /**< Result base address for pipeline, offset: 0x180 */ uint8_t RESERVED_5[632]; __I uint32_t ID; /**< Neutron ID, offset: 0x3FC */ } NEUTRON_Type; /* ---------------------------------------------------------------------------- -- NEUTRON Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NEUTRON_Register_Masks NEUTRON Register Masks * @{ */ /*! @name CTRL - Control */ /*! @{ */ #define NEUTRON_CTRL_PIPELINE_ENABLE_MASK (0xFFFFU) #define NEUTRON_CTRL_PIPELINE_ENABLE_SHIFT (0U) /*! PIPELINE_ENABLE - Pipeline Enable */ #define NEUTRON_CTRL_PIPELINE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CTRL_PIPELINE_ENABLE_SHIFT)) & NEUTRON_CTRL_PIPELINE_ENABLE_MASK) #define NEUTRON_CTRL_CTRL_SHADOW_BUSY_MASK (0x80000000U) #define NEUTRON_CTRL_CTRL_SHADOW_BUSY_SHIFT (31U) /*! CTRL_SHADOW_BUSY - Control Shadow Busy */ #define NEUTRON_CTRL_CTRL_SHADOW_BUSY(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CTRL_CTRL_SHADOW_BUSY_SHIFT)) & NEUTRON_CTRL_CTRL_SHADOW_BUSY_MASK) /*! @} */ /*! @name FORMAT - Format */ /*! @{ */ #define NEUTRON_FORMAT_WSIZE_MASK (0x3U) #define NEUTRON_FORMAT_WSIZE_SHIFT (0U) /*! WSIZE - Size Weights */ #define NEUTRON_FORMAT_WSIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_WSIZE_SHIFT)) & NEUTRON_FORMAT_WSIZE_MASK) #define NEUTRON_FORMAT_DSIZE_MASK (0xCU) #define NEUTRON_FORMAT_DSIZE_SHIFT (2U) /*! DSIZE - Size Data */ #define NEUTRON_FORMAT_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_DSIZE_SHIFT)) & NEUTRON_FORMAT_DSIZE_MASK) #define NEUTRON_FORMAT_BSIZE_MASK (0x30U) #define NEUTRON_FORMAT_BSIZE_SHIFT (4U) /*! BSIZE - Size Bias */ #define NEUTRON_FORMAT_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_BSIZE_SHIFT)) & NEUTRON_FORMAT_BSIZE_MASK) #define NEUTRON_FORMAT_RSIZE_MASK (0xC0U) #define NEUTRON_FORMAT_RSIZE_SHIFT (6U) /*! RSIZE - Size of Post-Scaler */ #define NEUTRON_FORMAT_RSIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_RSIZE_SHIFT)) & NEUTRON_FORMAT_RSIZE_MASK) #define NEUTRON_FORMAT_SCALER_SIZE_MASK (0x100U) #define NEUTRON_FORMAT_SCALER_SIZE_SHIFT (8U) /*! SCALER_SIZE - Scaler size * 0b0..Represents 32-bit dequant factor * 0b1..Represents 16-bit scaler or FP16 scaler format. */ #define NEUTRON_FORMAT_SCALER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_SCALER_SIZE_SHIFT)) & NEUTRON_FORMAT_SCALER_SIZE_MASK) #define NEUTRON_FORMAT_INTRLVRES_MASK (0x200U) #define NEUTRON_FORMAT_INTRLVRES_SHIFT (9U) /*! INTRLVRES - Interleave Results */ #define NEUTRON_FORMAT_INTRLVRES(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_INTRLVRES_SHIFT)) & NEUTRON_FORMAT_INTRLVRES_MASK) #define NEUTRON_FORMAT_SLOW16BIT_MASK (0x400U) #define NEUTRON_FORMAT_SLOW16BIT_SHIFT (10U) /*! SLOW16BIT - Slow 16-bit mode */ #define NEUTRON_FORMAT_SLOW16BIT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_SLOW16BIT_SHIFT)) & NEUTRON_FORMAT_SLOW16BIT_MASK) #define NEUTRON_FORMAT_FLOAT_ACC_EN_MASK (0x800U) #define NEUTRON_FORMAT_FLOAT_ACC_EN_SHIFT (11U) /*! FLOAT_ACC_EN - Enable Floating Point Acculmulator * 0b0..Disable * 0b1..Enable 4 */ #define NEUTRON_FORMAT_FLOAT_ACC_EN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_FLOAT_ACC_EN_SHIFT)) & NEUTRON_FORMAT_FLOAT_ACC_EN_MASK) #define NEUTRON_FORMAT_ACCDNSHIFT_MASK (0x3000U) #define NEUTRON_FORMAT_ACCDNSHIFT_SHIFT (12U) /*! ACCDNSHIFT - Accumulation Downshift * 0b00..no pre-shift accumulator * 0b01..downshift 4 * 0b10..downshift 8 * 0b11..downshift 12 */ #define NEUTRON_FORMAT_ACCDNSHIFT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_ACCDNSHIFT_SHIFT)) & NEUTRON_FORMAT_ACCDNSHIFT_MASK) #define NEUTRON_FORMAT_DONT_REARRANGEW_MASK (0x8000U) #define NEUTRON_FORMAT_DONT_REARRANGEW_SHIFT (15U) /*! DONT_REARRANGEW - Use Weights */ #define NEUTRON_FORMAT_DONT_REARRANGEW(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_DONT_REARRANGEW_SHIFT)) & NEUTRON_FORMAT_DONT_REARRANGEW_MASK) #define NEUTRON_FORMAT_SIGN_W_MASK (0x10000U) #define NEUTRON_FORMAT_SIGN_W_SHIFT (16U) /*! SIGN_W - Signed Weights */ #define NEUTRON_FORMAT_SIGN_W(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_SIGN_W_SHIFT)) & NEUTRON_FORMAT_SIGN_W_MASK) #define NEUTRON_FORMAT_SIGN_D_MASK (0x20000U) #define NEUTRON_FORMAT_SIGN_D_SHIFT (17U) /*! SIGN_D - Signed Data */ #define NEUTRON_FORMAT_SIGN_D(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_SIGN_D_SHIFT)) & NEUTRON_FORMAT_SIGN_D_MASK) #define NEUTRON_FORMAT_SIGN_B_MASK (0x40000U) #define NEUTRON_FORMAT_SIGN_B_SHIFT (18U) /*! SIGN_B - Signed bias */ #define NEUTRON_FORMAT_SIGN_B(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_SIGN_B_SHIFT)) & NEUTRON_FORMAT_SIGN_B_MASK) #define NEUTRON_FORMAT_SIGN_R_MASK (0x80000U) #define NEUTRON_FORMAT_SIGN_R_SHIFT (19U) /*! SIGN_R - Signed Result */ #define NEUTRON_FORMAT_SIGN_R(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_SIGN_R_SHIFT)) & NEUTRON_FORMAT_SIGN_R_MASK) #define NEUTRON_FORMAT_STICKY_MODEL_MASK (0x800000U) #define NEUTRON_FORMAT_STICKY_MODEL_SHIFT (23U) /*! STICKY_MODEL - Sticky model restart */ #define NEUTRON_FORMAT_STICKY_MODEL(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_STICKY_MODEL_SHIFT)) & NEUTRON_FORMAT_STICKY_MODEL_MASK) #define NEUTRON_FORMAT_USE_B_MASK (0x1000000U) #define NEUTRON_FORMAT_USE_B_SHIFT (24U) /*! USE_B - Use Bias */ #define NEUTRON_FORMAT_USE_B(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_USE_B_SHIFT)) & NEUTRON_FORMAT_USE_B_MASK) #define NEUTRON_FORMAT_USE_SCALER_MASK (0x4000000U) #define NEUTRON_FORMAT_USE_SCALER_SHIFT (26U) /*! USE_SCALER - Use scaler */ #define NEUTRON_FORMAT_USE_SCALER(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_USE_SCALER_SHIFT)) & NEUTRON_FORMAT_USE_SCALER_MASK) #define NEUTRON_FORMAT_ACTIVATION_MODE_MASK (0x38000000U) #define NEUTRON_FORMAT_ACTIVATION_MODE_SHIFT (27U) /*! ACTIVATION_MODE - Activation Mode * 0b000..None * 0b001..reLU * 0b010..Sigmoid * 0b011..HSWISH * 0b100..tanh * 0b101..eLU * 0b110..exp (for negative input range up to 0) * 0b111..leakyRELU */ #define NEUTRON_FORMAT_ACTIVATION_MODE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_ACTIVATION_MODE_SHIFT)) & NEUTRON_FORMAT_ACTIVATION_MODE_MASK) #define NEUTRON_FORMAT_VECTMULT_MASK (0x40000000U) #define NEUTRON_FORMAT_VECTMULT_SHIFT (30U) /*! VECTMULT - Vector Multiplication */ #define NEUTRON_FORMAT_VECTMULT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_VECTMULT_SHIFT)) & NEUTRON_FORMAT_VECTMULT_MASK) #define NEUTRON_FORMAT_COMPMULT_MASK (0x80000000U) #define NEUTRON_FORMAT_COMPMULT_SHIFT (31U) /*! COMPMULT - 1s Complement Weights */ #define NEUTRON_FORMAT_COMPMULT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FORMAT_COMPMULT_SHIFT)) & NEUTRON_FORMAT_COMPMULT_MASK) /*! @} */ /*! @name LENGTH - Length */ /*! @{ */ #define NEUTRON_LENGTH_ROWS_MASK (0xFFFFU) #define NEUTRON_LENGTH_ROWS_SHIFT (0U) /*! ROWS - Rows */ #define NEUTRON_LENGTH_ROWS(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_LENGTH_ROWS_SHIFT)) & NEUTRON_LENGTH_ROWS_MASK) #define NEUTRON_LENGTH_DATA_MASK (0xFFFF0000U) #define NEUTRON_LENGTH_DATA_SHIFT (16U) /*! DATA - Data */ #define NEUTRON_LENGTH_DATA(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_LENGTH_DATA_SHIFT)) & NEUTRON_LENGTH_DATA_MASK) /*! @} */ /*! @name WEIGHTBASE - Weight Base */ /*! @{ */ #define NEUTRON_WEIGHTBASE_BASE_MASK (0xFFFFFFFFU) #define NEUTRON_WEIGHTBASE_BASE_SHIFT (0U) /*! BASE - Base */ #define NEUTRON_WEIGHTBASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTBASE_BASE_SHIFT)) & NEUTRON_WEIGHTBASE_BASE_MASK) /*! @} */ /*! @name BIASBASE - Bias Base Address */ /*! @{ */ #define NEUTRON_BIASBASE_BASE_MASK (0xFFFFFFFFU) #define NEUTRON_BIASBASE_BASE_SHIFT (0U) /*! BASE - Base address for Bases */ #define NEUTRON_BIASBASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_BIASBASE_BASE_SHIFT)) & NEUTRON_BIASBASE_BASE_MASK) /*! @} */ /*! @name ARGMAXBASE - Base address for ARGMAX indices */ /*! @{ */ #define NEUTRON_ARGMAXBASE_BASE_MASK (0xFFFFFFFFU) #define NEUTRON_ARGMAXBASE_BASE_SHIFT (0U) /*! BASE - Specifies base address for ARGMAX results. */ #define NEUTRON_ARGMAXBASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ARGMAXBASE_BASE_SHIFT)) & NEUTRON_ARGMAXBASE_BASE_MASK) /*! @} */ /*! @name SCALEBASE - Scale Base */ /*! @{ */ #define NEUTRON_SCALEBASE_BASE_MASK (0xFFFFFFFFU) #define NEUTRON_SCALEBASE_BASE_SHIFT (0U) /*! BASE - Base address for Scalers */ #define NEUTRON_SCALEBASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_SCALEBASE_BASE_SHIFT)) & NEUTRON_SCALEBASE_BASE_MASK) /*! @} */ /*! @name ACTCTRL - Activation Control */ /*! @{ */ #define NEUTRON_ACTCTRL_CLIPMAX_MASK (0xFFFFU) #define NEUTRON_ACTCTRL_CLIPMAX_SHIFT (0U) /*! CLIPMAX - Clip max value */ #define NEUTRON_ACTCTRL_CLIPMAX(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL_CLIPMAX_SHIFT)) & NEUTRON_ACTCTRL_CLIPMAX_MASK) #define NEUTRON_ACTCTRL_CLIPMIN_MASK (0xFFFF0000U) #define NEUTRON_ACTCTRL_CLIPMIN_SHIFT (16U) /*! CLIPMIN - Clip min value */ #define NEUTRON_ACTCTRL_CLIPMIN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL_CLIPMIN_SHIFT)) & NEUTRON_ACTCTRL_CLIPMIN_MASK) /*! @} */ /*! @name DEQUANT - Dequant */ /*! @{ */ #define NEUTRON_DEQUANT_CMN_SHIFT_MASK (0x3FU) #define NEUTRON_DEQUANT_CMN_SHIFT_SHIFT (0U) /*! CMN_SHIFT - Common Shift factor */ #define NEUTRON_DEQUANT_CMN_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_DEQUANT_CMN_SHIFT_SHIFT)) & NEUTRON_DEQUANT_CMN_SHIFT_MASK) #define NEUTRON_DEQUANT_USE_FP16_BIAS_MASK (0x40U) #define NEUTRON_DEQUANT_USE_FP16_BIAS_SHIFT (6U) /*! USE_FP16_BIAS - Dequantization using FP16 Bias */ #define NEUTRON_DEQUANT_USE_FP16_BIAS(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_DEQUANT_USE_FP16_BIAS_SHIFT)) & NEUTRON_DEQUANT_USE_FP16_BIAS_MASK) #define NEUTRON_DEQUANT_USE_COMMON_DEQUANT_MASK (0x80U) #define NEUTRON_DEQUANT_USE_COMMON_DEQUANT_SHIFT (7U) /*! USE_COMMON_DEQUANT - Use common dequant factor */ #define NEUTRON_DEQUANT_USE_COMMON_DEQUANT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_DEQUANT_USE_COMMON_DEQUANT_SHIFT)) & NEUTRON_DEQUANT_USE_COMMON_DEQUANT_MASK) #define NEUTRON_DEQUANT_ACT_OFF_MASK (0xFF00U) #define NEUTRON_DEQUANT_ACT_OFF_SHIFT (8U) /*! ACT_OFF - Activation Offset */ #define NEUTRON_DEQUANT_ACT_OFF(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_DEQUANT_ACT_OFF_SHIFT)) & NEUTRON_DEQUANT_ACT_OFF_MASK) #define NEUTRON_DEQUANT_CMN_SCALER_VAL_MASK (0xFFFF0000U) #define NEUTRON_DEQUANT_CMN_SCALER_VAL_SHIFT (16U) /*! CMN_SCALER_VAL - Common Scale Value */ #define NEUTRON_DEQUANT_CMN_SCALER_VAL(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_DEQUANT_CMN_SCALER_VAL_SHIFT)) & NEUTRON_DEQUANT_CMN_SCALER_VAL_MASK) /*! @} */ /*! @name BATCH - Batch Count */ /*! @{ */ #define NEUTRON_BATCH_COUNT_MASK (0xFFFFU) #define NEUTRON_BATCH_COUNT_SHIFT (0U) /*! COUNT - Matrix by Column */ #define NEUTRON_BATCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_BATCH_COUNT_SHIFT)) & NEUTRON_BATCH_COUNT_MASK) /*! @} */ /*! @name RESCTRL - Result Control */ /*! @{ */ #define NEUTRON_RESCTRL_PIPE_STRIDE_MASK (0xFU) #define NEUTRON_RESCTRL_PIPE_STRIDE_SHIFT (0U) /*! PIPE_STRIDE - Skip unused pipelines */ #define NEUTRON_RESCTRL_PIPE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_PIPE_STRIDE_SHIFT)) & NEUTRON_RESCTRL_PIPE_STRIDE_MASK) #define NEUTRON_RESCTRL_POOLX_SIZE_MASK (0xFFF0U) #define NEUTRON_RESCTRL_POOLX_SIZE_SHIFT (4U) /*! POOLX_SIZE - Output max Pool X */ #define NEUTRON_RESCTRL_POOLX_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_POOLX_SIZE_SHIFT)) & NEUTRON_RESCTRL_POOLX_SIZE_MASK) #define NEUTRON_RESCTRL_POOLY_SIZE_MASK (0x70000U) #define NEUTRON_RESCTRL_POOLY_SIZE_SHIFT (16U) /*! POOLY_SIZE - Output max Pool Y */ #define NEUTRON_RESCTRL_POOLY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_POOLY_SIZE_SHIFT)) & NEUTRON_RESCTRL_POOLY_SIZE_MASK) #define NEUTRON_RESCTRL_POOL_DEPTH_MASK (0x180000U) #define NEUTRON_RESCTRL_POOL_DEPTH_SHIFT (19U) /*! POOL_DEPTH - Pooling Depth */ #define NEUTRON_RESCTRL_POOL_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_POOL_DEPTH_SHIFT)) & NEUTRON_RESCTRL_POOL_DEPTH_MASK) #define NEUTRON_RESCTRL_ARGMAX_EN_MASK (0x800000U) #define NEUTRON_RESCTRL_ARGMAX_EN_SHIFT (23U) /*! ARGMAX_EN - Use this bit to enable ARGMAX function. ARGMAX results will be written out to the * memory address specified by ARGMAXBASE register. */ #define NEUTRON_RESCTRL_ARGMAX_EN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_ARGMAX_EN_SHIFT)) & NEUTRON_RESCTRL_ARGMAX_EN_MASK) #define NEUTRON_RESCTRL_ARGMAX_BYTE_MASK (0x1000000U) #define NEUTRON_RESCTRL_ARGMAX_BYTE_SHIFT (24U) /*! ARGMAX_BYTE - ARGMAX Byte */ #define NEUTRON_RESCTRL_ARGMAX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_ARGMAX_BYTE_SHIFT)) & NEUTRON_RESCTRL_ARGMAX_BYTE_MASK) #define NEUTRON_RESCTRL_IGNORE_POOL_MASK (0x2000000U) #define NEUTRON_RESCTRL_IGNORE_POOL_SHIFT (25U) /*! IGNORE_POOL - IGNORE POOL */ #define NEUTRON_RESCTRL_IGNORE_POOL(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_IGNORE_POOL_SHIFT)) & NEUTRON_RESCTRL_IGNORE_POOL_MASK) #define NEUTRON_RESCTRL_IGNORE_RESULTS_MASK (0x4000000U) #define NEUTRON_RESCTRL_IGNORE_RESULTS_SHIFT (26U) /*! IGNORE_RESULTS - IGNORE RESULTS */ #define NEUTRON_RESCTRL_IGNORE_RESULTS(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_IGNORE_RESULTS_SHIFT)) & NEUTRON_RESCTRL_IGNORE_RESULTS_MASK) #define NEUTRON_RESCTRL_PARTIAL_REUSE_MASK (0x8000000U) #define NEUTRON_RESCTRL_PARTIAL_REUSE_SHIFT (27U) /*! PARTIAL_REUSE - Partial Reuse */ #define NEUTRON_RESCTRL_PARTIAL_REUSE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_PARTIAL_REUSE_SHIFT)) & NEUTRON_RESCTRL_PARTIAL_REUSE_MASK) #define NEUTRON_RESCTRL_PARTIAL_RESTORE_MASK (0x10000000U) #define NEUTRON_RESCTRL_PARTIAL_RESTORE_SHIFT (28U) /*! PARTIAL_RESTORE - Partial Restore */ #define NEUTRON_RESCTRL_PARTIAL_RESTORE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_PARTIAL_RESTORE_SHIFT)) & NEUTRON_RESCTRL_PARTIAL_RESTORE_MASK) #define NEUTRON_RESCTRL_POOL_DEF0_MASK (0x20000000U) #define NEUTRON_RESCTRL_POOL_DEF0_SHIFT (29U) /*! POOL_DEF0 - Force Max Pool to Zero */ #define NEUTRON_RESCTRL_POOL_DEF0(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_POOL_DEF0_SHIFT)) & NEUTRON_RESCTRL_POOL_DEF0_MASK) #define NEUTRON_RESCTRL_POOL_ADDER_MASK (0x40000000U) #define NEUTRON_RESCTRL_POOL_ADDER_SHIFT (30U) /*! POOL_ADDER - Vector Addition */ #define NEUTRON_RESCTRL_POOL_ADDER(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_POOL_ADDER_SHIFT)) & NEUTRON_RESCTRL_POOL_ADDER_MASK) #define NEUTRON_RESCTRL_POOL_RESTART_MASK (0x80000000U) #define NEUTRON_RESCTRL_POOL_RESTART_SHIFT (31U) /*! POOL_RESTART - Reset Pool */ #define NEUTRON_RESCTRL_POOL_RESTART(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESCTRL_POOL_RESTART_SHIFT)) & NEUTRON_RESCTRL_POOL_RESTART_MASK) /*! @} */ /*! @name RES_Y - Result Writer Configuration Y */ /*! @{ */ #define NEUTRON_RES_Y_STRIDE_MASK (0xFFFFFFFU) #define NEUTRON_RES_Y_STRIDE_SHIFT (0U) /*! STRIDE - Y-Stride */ #define NEUTRON_RES_Y_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RES_Y_STRIDE_SHIFT)) & NEUTRON_RES_Y_STRIDE_MASK) #define NEUTRON_RES_Y_COUNT_MASK (0xF0000000U) #define NEUTRON_RES_Y_COUNT_SHIFT (28U) /*! COUNT - Y-count */ #define NEUTRON_RES_Y_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RES_Y_COUNT_SHIFT)) & NEUTRON_RES_Y_COUNT_MASK) /*! @} */ /*! @name RES_X - Result Writer Configuration X */ /*! @{ */ #define NEUTRON_RES_X_STRIDE_MASK (0xFFFFU) #define NEUTRON_RES_X_STRIDE_SHIFT (0U) /*! STRIDE - X-Stride */ #define NEUTRON_RES_X_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RES_X_STRIDE_SHIFT)) & NEUTRON_RES_X_STRIDE_MASK) #define NEUTRON_RES_X_COUNT_MASK (0xFFFF0000U) #define NEUTRON_RES_X_COUNT_SHIFT (16U) /*! COUNT - X-count */ #define NEUTRON_RES_X_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RES_X_COUNT_SHIFT)) & NEUTRON_RES_X_COUNT_MASK) /*! @} */ /*! @name ASYMCTRL - Asymmetric Control Register */ /*! @{ */ #define NEUTRON_ASYMCTRL_ZPD_MASK (0xFFU) #define NEUTRON_ASYMCTRL_ZPD_SHIFT (0U) /*! ZPD - Zero point for data */ #define NEUTRON_ASYMCTRL_ZPD(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ASYMCTRL_ZPD_SHIFT)) & NEUTRON_ASYMCTRL_ZPD_MASK) #define NEUTRON_ASYMCTRL_ZPW_MASK (0xFF00U) #define NEUTRON_ASYMCTRL_ZPW_SHIFT (8U) /*! ZPW - Zero point for weight */ #define NEUTRON_ASYMCTRL_ZPW(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ASYMCTRL_ZPW_SHIFT)) & NEUTRON_ASYMCTRL_ZPW_MASK) /*! @} */ /*! @name FLUSH - Flush */ /*! @{ */ #define NEUTRON_FLUSH_JOB_MASK (0x1U) #define NEUTRON_FLUSH_JOB_SHIFT (0U) /*! JOB - All Batches FLUSH execute */ #define NEUTRON_FLUSH_JOB(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FLUSH_JOB_SHIFT)) & NEUTRON_FLUSH_JOB_MASK) #define NEUTRON_FLUSH_BATCH_MASK (0x2U) #define NEUTRON_FLUSH_BATCH_SHIFT (1U) /*! BATCH - Each Batches FLUSH execute */ #define NEUTRON_FLUSH_BATCH(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_FLUSH_BATCH_SHIFT)) & NEUTRON_FLUSH_BATCH_MASK) /*! @} */ /*! @name INTR - Interrupt */ /*! @{ */ #define NEUTRON_INTR_INTREN_MASK (0x1U) #define NEUTRON_INTR_INTREN_SHIFT (0U) /*! INTREN - Interrupt Enable */ #define NEUTRON_INTR_INTREN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTR_INTREN_SHIFT)) & NEUTRON_INTR_INTREN_MASK) #define NEUTRON_INTR_EVENTEN_MASK (0x2U) #define NEUTRON_INTR_EVENTEN_SHIFT (1U) /*! EVENTEN - Event Enable */ #define NEUTRON_INTR_EVENTEN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTR_EVENTEN_SHIFT)) & NEUTRON_INTR_EVENTEN_MASK) #define NEUTRON_INTR_ERRORTRAP_M_MASK (0x4U) #define NEUTRON_INTR_ERRORTRAP_M_SHIFT (2U) /*! ERRORTRAP_M - Error Trap */ #define NEUTRON_INTR_ERRORTRAP_M(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTR_ERRORTRAP_M_SHIFT)) & NEUTRON_INTR_ERRORTRAP_M_MASK) #define NEUTRON_INTR_ERRORTRAP_R_MASK (0x8U) #define NEUTRON_INTR_ERRORTRAP_R_SHIFT (3U) /*! ERRORTRAP_R - Error Trap for RES Bus */ #define NEUTRON_INTR_ERRORTRAP_R(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTR_ERRORTRAP_R_SHIFT)) & NEUTRON_INTR_ERRORTRAP_R_MASK) #define NEUTRON_INTR_MODE_MASK (0x30U) #define NEUTRON_INTR_MODE_SHIFT (4U) /*! MODE - Interrupt mode * 0b00..Interrupt on completion * 0b01..Interrupt on job loaded * 0b10..Interrupt when Neutron IDLE * 0b11..Interrupt on ERROR */ #define NEUTRON_INTR_MODE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTR_MODE_SHIFT)) & NEUTRON_INTR_MODE_MASK) #define NEUTRON_INTR_EVENT_MODE_MASK (0xC0U) #define NEUTRON_INTR_EVENT_MODE_SHIFT (6U) /*! EVENT_MODE - Event mode */ #define NEUTRON_INTR_EVENT_MODE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTR_EVENT_MODE_SHIFT)) & NEUTRON_INTR_EVENT_MODE_MASK) /*! @} */ /*! @name WEIGHTCTRL - Weight Control */ /*! @{ */ #define NEUTRON_WEIGHTCTRL_WCTRL_USE_MINI_W_MASK (0x1U) #define NEUTRON_WEIGHTCTRL_WCTRL_USE_MINI_W_SHIFT (0U) /*! WCTRL_USE_MINI_W - Mini Weights Enable */ #define NEUTRON_WEIGHTCTRL_WCTRL_USE_MINI_W(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_WCTRL_USE_MINI_W_SHIFT)) & NEUTRON_WEIGHTCTRL_WCTRL_USE_MINI_W_MASK) #define NEUTRON_WEIGHTCTRL_WCTRL_MINI_W_SIZE_MASK (0xEU) #define NEUTRON_WEIGHTCTRL_WCTRL_MINI_W_SIZE_SHIFT (1U) /*! WCTRL_MINI_W_SIZE - Mini Weight Size */ #define NEUTRON_WEIGHTCTRL_WCTRL_MINI_W_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_WCTRL_MINI_W_SIZE_SHIFT)) & NEUTRON_WEIGHTCTRL_WCTRL_MINI_W_SIZE_MASK) #define NEUTRON_WEIGHTCTRL_WCTRL_USE_CODEBOOK_MASK (0x10U) #define NEUTRON_WEIGHTCTRL_WCTRL_USE_CODEBOOK_SHIFT (4U) /*! WCTRL_USE_CODEBOOK - Codebook */ #define NEUTRON_WEIGHTCTRL_WCTRL_USE_CODEBOOK(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_WCTRL_USE_CODEBOOK_SHIFT)) & NEUTRON_WEIGHTCTRL_WCTRL_USE_CODEBOOK_MASK) #define NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_MASK (0x20U) #define NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_SHIFT (5U) /*! WCTRL_MUL_BY_1 - No Weights */ #define NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_SHIFT)) & NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_MASK) #define NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_SELECTIVE_MASK (0x40U) #define NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_SELECTIVE_SHIFT (6U) /*! WCTRL_MUL_BY_1_SELECTIVE - Selective multiply by 1 mode */ #define NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_SELECTIVE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_SELECTIVE_SHIFT)) & NEUTRON_WEIGHTCTRL_WCTRL_MUL_BY_1_SELECTIVE_MASK) #define NEUTRON_WEIGHTCTRL_SQUARE_DATA_MASK (0x100U) #define NEUTRON_WEIGHTCTRL_SQUARE_DATA_SHIFT (8U) /*! SQUARE_DATA - Square data */ #define NEUTRON_WEIGHTCTRL_SQUARE_DATA(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_SQUARE_DATA_SHIFT)) & NEUTRON_WEIGHTCTRL_SQUARE_DATA_MASK) #define NEUTRON_WEIGHTCTRL_MULT_WT_DATA_NEG_MASK (0x200U) #define NEUTRON_WEIGHTCTRL_MULT_WT_DATA_NEG_SHIFT (9U) /*! MULT_WT_DATA_NEG - Multiply data by weight if data is negative */ #define NEUTRON_WEIGHTCTRL_MULT_WT_DATA_NEG(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_MULT_WT_DATA_NEG_SHIFT)) & NEUTRON_WEIGHTCTRL_MULT_WT_DATA_NEG_MASK) #define NEUTRON_WEIGHTCTRL_USE_WEIGHT_COLUMN_MASK (0x400U) #define NEUTRON_WEIGHTCTRL_USE_WEIGHT_COLUMN_SHIFT (10U) /*! USE_WEIGHT_COLUMN - Use Weight Column */ #define NEUTRON_WEIGHTCTRL_USE_WEIGHT_COLUMN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_WEIGHTCTRL_USE_WEIGHT_COLUMN_SHIFT)) & NEUTRON_WEIGHTCTRL_USE_WEIGHT_COLUMN_MASK) /*! @} */ /*! @name CIRCADDR - Circular Address */ /*! @{ */ #define NEUTRON_CIRCADDR_DATMASK_MASK (0xFFFFU) #define NEUTRON_CIRCADDR_DATMASK_SHIFT (0U) /*! DATMASK - Data circular address mask */ #define NEUTRON_CIRCADDR_DATMASK(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CIRCADDR_DATMASK_SHIFT)) & NEUTRON_CIRCADDR_DATMASK_MASK) #define NEUTRON_CIRCADDR_RESMASK_MASK (0xFFFF0000U) #define NEUTRON_CIRCADDR_RESMASK_SHIFT (16U) /*! RESMASK - Res circular address mask */ #define NEUTRON_CIRCADDR_RESMASK(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CIRCADDR_RESMASK_SHIFT)) & NEUTRON_CIRCADDR_RESMASK_MASK) /*! @} */ /*! @name PROGSEQ - PROGSEQ */ /*! @{ */ #define NEUTRON_PROGSEQ_ENABLE_MASK (0x1U) #define NEUTRON_PROGSEQ_ENABLE_SHIFT (0U) /*! ENABLE - Enable Register loading Sequencer */ #define NEUTRON_PROGSEQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_PROGSEQ_ENABLE_SHIFT)) & NEUTRON_PROGSEQ_ENABLE_MASK) #define NEUTRON_PROGSEQ_BASE_MASK (0xFFFFFFFCU) #define NEUTRON_PROGSEQ_BASE_SHIFT (2U) /*! BASE - Location of Sequencer code */ #define NEUTRON_PROGSEQ_BASE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_PROGSEQ_BASE_SHIFT)) & NEUTRON_PROGSEQ_BASE_MASK) /*! @} */ /*! @name SCRATCH0_2 - Scratch Register 0..Scratch Register 2 */ /*! @{ */ #define NEUTRON_SCRATCH0_2_SCR_MASK (0xFFFFFFFFU) #define NEUTRON_SCRATCH0_2_SCR_SHIFT (0U) /*! SCR - Scratch */ #define NEUTRON_SCRATCH0_2_SCR(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_SCRATCH0_2_SCR_SHIFT)) & NEUTRON_SCRATCH0_2_SCR_MASK) /*! @} */ /* The count of NEUTRON_SCRATCH0_2 */ #define NEUTRON_SCRATCH0_2_COUNT (3U) /*! @name CODEBOOK - Codebook Register 0..Codebook Register 15 */ /*! @{ */ #define NEUTRON_CODEBOOK_CODE_MASK (0xFFFFFFFFU) #define NEUTRON_CODEBOOK_CODE_SHIFT (0U) /*! CODE - Codebook code */ #define NEUTRON_CODEBOOK_CODE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CODEBOOK_CODE_SHIFT)) & NEUTRON_CODEBOOK_CODE_MASK) /*! @} */ /* The count of NEUTRON_CODEBOOK */ #define NEUTRON_CODEBOOK_COUNT (16U) /*! @name CANVAS_SIZE - Canvas Size */ /*! @{ */ #define NEUTRON_CANVAS_SIZE_XTOTAL_MASK (0xFFFFU) #define NEUTRON_CANVAS_SIZE_XTOTAL_SHIFT (0U) /*! XTOTAL - Canvas XTOTAL */ #define NEUTRON_CANVAS_SIZE_XTOTAL(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SIZE_XTOTAL_SHIFT)) & NEUTRON_CANVAS_SIZE_XTOTAL_MASK) #define NEUTRON_CANVAS_SIZE_PIPE_Y_CNT_MASK (0xFF0000U) #define NEUTRON_CANVAS_SIZE_PIPE_Y_CNT_SHIFT (16U) /*! PIPE_Y_CNT - Pipeline Y Count Configuration */ #define NEUTRON_CANVAS_SIZE_PIPE_Y_CNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SIZE_PIPE_Y_CNT_SHIFT)) & NEUTRON_CANVAS_SIZE_PIPE_Y_CNT_MASK) #define NEUTRON_CANVAS_SIZE_LOAD_HEIGHT_MASK (0x7000000U) #define NEUTRON_CANVAS_SIZE_LOAD_HEIGHT_SHIFT (24U) /*! LOAD_HEIGHT - Load Height */ #define NEUTRON_CANVAS_SIZE_LOAD_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SIZE_LOAD_HEIGHT_SHIFT)) & NEUTRON_CANVAS_SIZE_LOAD_HEIGHT_MASK) #define NEUTRON_CANVAS_SIZE_READ_HEIGHT_MASK (0x38000000U) #define NEUTRON_CANVAS_SIZE_READ_HEIGHT_SHIFT (27U) /*! READ_HEIGHT - Read Height */ #define NEUTRON_CANVAS_SIZE_READ_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SIZE_READ_HEIGHT_SHIFT)) & NEUTRON_CANVAS_SIZE_READ_HEIGHT_MASK) /*! @} */ /*! @name CANVAS_READ_CONV - Canvas Conv */ /*! @{ */ #define NEUTRON_CANVAS_READ_CONV_X_SIZE_MASK (0xFFFFU) #define NEUTRON_CANVAS_READ_CONV_X_SIZE_SHIFT (0U) /*! X_SIZE - Convolution X Size */ #define NEUTRON_CANVAS_READ_CONV_X_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_READ_CONV_X_SIZE_SHIFT)) & NEUTRON_CANVAS_READ_CONV_X_SIZE_MASK) #define NEUTRON_CANVAS_READ_CONV_STRIDE_MASK (0x7FFF0000U) #define NEUTRON_CANVAS_READ_CONV_STRIDE_SHIFT (16U) /*! STRIDE - Conv Stride */ #define NEUTRON_CANVAS_READ_CONV_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_READ_CONV_STRIDE_SHIFT)) & NEUTRON_CANVAS_READ_CONV_STRIDE_MASK) #define NEUTRON_CANVAS_READ_CONV_STRIDE2EN_MASK (0x80000000U) #define NEUTRON_CANVAS_READ_CONV_STRIDE2EN_SHIFT (31U) /*! STRIDE2EN - Stride 2 Enable */ #define NEUTRON_CANVAS_READ_CONV_STRIDE2EN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_READ_CONV_STRIDE2EN_SHIFT)) & NEUTRON_CANVAS_READ_CONV_STRIDE2EN_MASK) /*! @} */ /*! @name CANVAS_LOAD_PAD - Canvas Load Pad */ /*! @{ */ #define NEUTRON_CANVAS_LOAD_PAD_TOP_MASK (0x3FU) #define NEUTRON_CANVAS_LOAD_PAD_TOP_SHIFT (0U) /*! TOP - Top Padding */ #define NEUTRON_CANVAS_LOAD_PAD_TOP(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_PAD_TOP_SHIFT)) & NEUTRON_CANVAS_LOAD_PAD_TOP_MASK) #define NEUTRON_CANVAS_LOAD_PAD_LEFT_MASK (0xFFFF00U) #define NEUTRON_CANVAS_LOAD_PAD_LEFT_SHIFT (8U) /*! LEFT - Horizontal Padding */ #define NEUTRON_CANVAS_LOAD_PAD_LEFT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_PAD_LEFT_SHIFT)) & NEUTRON_CANVAS_LOAD_PAD_LEFT_MASK) #define NEUTRON_CANVAS_LOAD_PAD_VAL_MASK (0xFF000000U) #define NEUTRON_CANVAS_LOAD_PAD_VAL_SHIFT (24U) /*! VAL - Pad Value */ #define NEUTRON_CANVAS_LOAD_PAD_VAL(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_PAD_VAL_SHIFT)) & NEUTRON_CANVAS_LOAD_PAD_VAL_MASK) /*! @} */ /*! @name CANVAS_LOAD_Y - Y Dimension Stride */ /*! @{ */ #define NEUTRON_CANVAS_LOAD_Y_INC_MASK (0x3FFFFFU) #define NEUTRON_CANVAS_LOAD_Y_INC_SHIFT (0U) /*! INC - Y Stride */ #define NEUTRON_CANVAS_LOAD_Y_INC(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_Y_INC_SHIFT)) & NEUTRON_CANVAS_LOAD_Y_INC_MASK) #define NEUTRON_CANVAS_LOAD_Y_COUNT_MASK (0xFFC00000U) #define NEUTRON_CANVAS_LOAD_Y_COUNT_SHIFT (22U) /*! COUNT - Word Reads */ #define NEUTRON_CANVAS_LOAD_Y_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_Y_COUNT_SHIFT)) & NEUTRON_CANVAS_LOAD_Y_COUNT_MASK) /*! @} */ /*! @name CANVAS_LOAD_X - X Dimension Stride */ /*! @{ */ #define NEUTRON_CANVAS_LOAD_X_STRIDE_MASK (0xFFFFFU) #define NEUTRON_CANVAS_LOAD_X_STRIDE_SHIFT (0U) /*! STRIDE - Offset */ #define NEUTRON_CANVAS_LOAD_X_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_X_STRIDE_SHIFT)) & NEUTRON_CANVAS_LOAD_X_STRIDE_MASK) #define NEUTRON_CANVAS_LOAD_X_COUNT_MASK (0xFF00000U) #define NEUTRON_CANVAS_LOAD_X_COUNT_SHIFT (20U) /*! COUNT - Count */ #define NEUTRON_CANVAS_LOAD_X_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_X_COUNT_SHIFT)) & NEUTRON_CANVAS_LOAD_X_COUNT_MASK) /*! @} */ /*! @name CANVAS_LOAD_BATCH - Canvas Load Batch */ /*! @{ */ #define NEUTRON_CANVAS_LOAD_BATCH_COUNT_MASK (0xFFFU) #define NEUTRON_CANVAS_LOAD_BATCH_COUNT_SHIFT (0U) /*! COUNT - Canvas Batch Count */ #define NEUTRON_CANVAS_LOAD_BATCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_BATCH_COUNT_SHIFT)) & NEUTRON_CANVAS_LOAD_BATCH_COUNT_MASK) #define NEUTRON_CANVAS_LOAD_BATCH_INC_MASK (0xFFFFF000U) #define NEUTRON_CANVAS_LOAD_BATCH_INC_SHIFT (12U) /*! INC - Canvas Batch Inc */ #define NEUTRON_CANVAS_LOAD_BATCH_INC(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_BATCH_INC_SHIFT)) & NEUTRON_CANVAS_LOAD_BATCH_INC_MASK) /*! @} */ /*! @name CANVAS_LOAD_OUTER_BATCH - Canvas Load Outer Batch */ /*! @{ */ #define NEUTRON_CANVAS_LOAD_OUTER_BATCH_COUNT_MASK (0xFFFU) #define NEUTRON_CANVAS_LOAD_OUTER_BATCH_COUNT_SHIFT (0U) /*! COUNT - Canvas Outer Batch Count */ #define NEUTRON_CANVAS_LOAD_OUTER_BATCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_OUTER_BATCH_COUNT_SHIFT)) & NEUTRON_CANVAS_LOAD_OUTER_BATCH_COUNT_MASK) #define NEUTRON_CANVAS_LOAD_OUTER_BATCH_INC_MASK (0xFFFFF000U) #define NEUTRON_CANVAS_LOAD_OUTER_BATCH_INC_SHIFT (12U) /*! INC - Canvas Outer Batch Inc */ #define NEUTRON_CANVAS_LOAD_OUTER_BATCH_INC(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_LOAD_OUTER_BATCH_INC_SHIFT)) & NEUTRON_CANVAS_LOAD_OUTER_BATCH_INC_MASK) /*! @} */ /*! @name CANVAS_SECONDARY_READ - Canvas Secondary Read */ /*! @{ */ #define NEUTRON_CANVAS_SECONDARY_READ_SEC_DATA_MASK (0xFFU) #define NEUTRON_CANVAS_SECONDARY_READ_SEC_DATA_SHIFT (0U) /*! SEC_DATA - Data Consumed Value */ #define NEUTRON_CANVAS_SECONDARY_READ_SEC_DATA(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECONDARY_READ_SEC_DATA_SHIFT)) & NEUTRON_CANVAS_SECONDARY_READ_SEC_DATA_MASK) #define NEUTRON_CANVAS_SECONDARY_READ_SEC_HEIGHT_MASK (0xF00U) #define NEUTRON_CANVAS_SECONDARY_READ_SEC_HEIGHT_SHIFT (8U) /*! SEC_HEIGHT - Secondary Read Height */ #define NEUTRON_CANVAS_SECONDARY_READ_SEC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECONDARY_READ_SEC_HEIGHT_SHIFT)) & NEUTRON_CANVAS_SECONDARY_READ_SEC_HEIGHT_MASK) #define NEUTRON_CANVAS_SECONDARY_READ_SEC_Y_CFG_MASK (0x7F000U) #define NEUTRON_CANVAS_SECONDARY_READ_SEC_Y_CFG_SHIFT (12U) /*! SEC_Y_CFG - Secondary Pipeline Y Configuration */ #define NEUTRON_CANVAS_SECONDARY_READ_SEC_Y_CFG(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECONDARY_READ_SEC_Y_CFG_SHIFT)) & NEUTRON_CANVAS_SECONDARY_READ_SEC_Y_CFG_MASK) #define NEUTRON_CANVAS_SECONDARY_READ_SEC_EN_MASK (0x80000U) #define NEUTRON_CANVAS_SECONDARY_READ_SEC_EN_SHIFT (19U) /*! SEC_EN - Enable Secondary Setting */ #define NEUTRON_CANVAS_SECONDARY_READ_SEC_EN(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECONDARY_READ_SEC_EN_SHIFT)) & NEUTRON_CANVAS_SECONDARY_READ_SEC_EN_MASK) /*! @} */ /*! @name CANVAS_SECOND_Y_ADJ - CANVAS_SECOND_Y_ADJ */ /*! @{ */ #define NEUTRON_CANVAS_SECOND_Y_ADJ_COUNT_MASK (0xFU) #define NEUTRON_CANVAS_SECOND_Y_ADJ_COUNT_SHIFT (0U) /*! COUNT - Count between adjustments */ #define NEUTRON_CANVAS_SECOND_Y_ADJ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECOND_Y_ADJ_COUNT_SHIFT)) & NEUTRON_CANVAS_SECOND_Y_ADJ_COUNT_MASK) #define NEUTRON_CANVAS_SECOND_Y_ADJ_START_MASK (0xF0U) #define NEUTRON_CANVAS_SECOND_Y_ADJ_START_SHIFT (4U) /*! START - Start */ #define NEUTRON_CANVAS_SECOND_Y_ADJ_START(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECOND_Y_ADJ_START_SHIFT)) & NEUTRON_CANVAS_SECOND_Y_ADJ_START_MASK) #define NEUTRON_CANVAS_SECOND_Y_ADJ_UNSIGNED_STRIDE_MASK (0xFFFFFC00U) #define NEUTRON_CANVAS_SECOND_Y_ADJ_UNSIGNED_STRIDE_SHIFT (10U) /*! UNSIGNED_STRIDE - Stride */ #define NEUTRON_CANVAS_SECOND_Y_ADJ_UNSIGNED_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECOND_Y_ADJ_UNSIGNED_STRIDE_SHIFT)) & NEUTRON_CANVAS_SECOND_Y_ADJ_UNSIGNED_STRIDE_MASK) /*! @} */ /*! @name CANVAS_PDS_POS - CANVAS Pad Data Supervisor Position */ /*! @{ */ #define NEUTRON_CANVAS_PDS_POS_POS_Y_MASK (0xFFFU) #define NEUTRON_CANVAS_PDS_POS_POS_Y_SHIFT (0U) /*! POS_Y - POS_Y */ #define NEUTRON_CANVAS_PDS_POS_POS_Y(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_POS_POS_Y_SHIFT)) & NEUTRON_CANVAS_PDS_POS_POS_Y_MASK) #define NEUTRON_CANVAS_PDS_POS_POS_X_MASK (0xFFF000U) #define NEUTRON_CANVAS_PDS_POS_POS_X_SHIFT (12U) /*! POS_X - POS_X */ #define NEUTRON_CANVAS_PDS_POS_POS_X(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_POS_POS_X_SHIFT)) & NEUTRON_CANVAS_PDS_POS_POS_X_MASK) /*! @} */ /*! @name CANVAS_PDS_PAD - CANVAS Pad Data Supervisor Padding */ /*! @{ */ #define NEUTRON_CANVAS_PDS_PAD_PADT_MASK (0x1FU) #define NEUTRON_CANVAS_PDS_PAD_PADT_SHIFT (0U) /*! PADT - PADT */ #define NEUTRON_CANVAS_PDS_PAD_PADT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_PAD_PADT_SHIFT)) & NEUTRON_CANVAS_PDS_PAD_PADT_MASK) #define NEUTRON_CANVAS_PDS_PAD_PADL_MASK (0x3E0U) #define NEUTRON_CANVAS_PDS_PAD_PADL_SHIFT (5U) /*! PADL - PADL */ #define NEUTRON_CANVAS_PDS_PAD_PADL(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_PAD_PADL_SHIFT)) & NEUTRON_CANVAS_PDS_PAD_PADL_MASK) #define NEUTRON_CANVAS_PDS_PAD_PADB_MASK (0x7C00U) #define NEUTRON_CANVAS_PDS_PAD_PADB_SHIFT (10U) /*! PADB - PADB */ #define NEUTRON_CANVAS_PDS_PAD_PADB(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_PAD_PADB_SHIFT)) & NEUTRON_CANVAS_PDS_PAD_PADB_MASK) #define NEUTRON_CANVAS_PDS_PAD_PADR_MASK (0xF8000U) #define NEUTRON_CANVAS_PDS_PAD_PADR_SHIFT (15U) /*! PADR - PADR */ #define NEUTRON_CANVAS_PDS_PAD_PADR(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_PAD_PADR_SHIFT)) & NEUTRON_CANVAS_PDS_PAD_PADR_MASK) #define NEUTRON_CANVAS_PDS_PAD_ENP0PAD_MASK (0x80000000U) #define NEUTRON_CANVAS_PDS_PAD_ENP0PAD_SHIFT (31U) /*! ENP0PAD - Enable Pipeline 0 Padding */ #define NEUTRON_CANVAS_PDS_PAD_ENP0PAD(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_PAD_ENP0PAD_SHIFT)) & NEUTRON_CANVAS_PDS_PAD_ENP0PAD_MASK) /*! @} */ /*! @name CANVAS_PDS_STRIDES - CANVAS Pad Data Supervisor Strides */ /*! @{ */ #define NEUTRON_CANVAS_PDS_STRIDES_DilationH_MASK (0x1FU) #define NEUTRON_CANVAS_PDS_STRIDES_DilationH_SHIFT (0U) /*! DilationH - DilationH */ #define NEUTRON_CANVAS_PDS_STRIDES_DilationH(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_STRIDES_DilationH_SHIFT)) & NEUTRON_CANVAS_PDS_STRIDES_DilationH_MASK) #define NEUTRON_CANVAS_PDS_STRIDES_DilationW_MASK (0x3E0U) #define NEUTRON_CANVAS_PDS_STRIDES_DilationW_SHIFT (5U) /*! DilationW - DilationW */ #define NEUTRON_CANVAS_PDS_STRIDES_DilationW(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_STRIDES_DilationW_SHIFT)) & NEUTRON_CANVAS_PDS_STRIDES_DilationW_MASK) #define NEUTRON_CANVAS_PDS_STRIDES_StrideH_MASK (0x7C00U) #define NEUTRON_CANVAS_PDS_STRIDES_StrideH_SHIFT (10U) /*! StrideH - StrideH */ #define NEUTRON_CANVAS_PDS_STRIDES_StrideH(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_STRIDES_StrideH_SHIFT)) & NEUTRON_CANVAS_PDS_STRIDES_StrideH_MASK) #define NEUTRON_CANVAS_PDS_STRIDES_StrideW_MASK (0xF8000U) #define NEUTRON_CANVAS_PDS_STRIDES_StrideW_SHIFT (15U) /*! StrideW - StrideW */ #define NEUTRON_CANVAS_PDS_STRIDES_StrideW(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_STRIDES_StrideW_SHIFT)) & NEUTRON_CANVAS_PDS_STRIDES_StrideW_MASK) #define NEUTRON_CANVAS_PDS_STRIDES_KernelH_MASK (0x3F00000U) #define NEUTRON_CANVAS_PDS_STRIDES_KernelH_SHIFT (20U) /*! KernelH - KernelH */ #define NEUTRON_CANVAS_PDS_STRIDES_KernelH(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_STRIDES_KernelH_SHIFT)) & NEUTRON_CANVAS_PDS_STRIDES_KernelH_MASK) #define NEUTRON_CANVAS_PDS_STRIDES_KernelW_MASK (0xFC000000U) #define NEUTRON_CANVAS_PDS_STRIDES_KernelW_SHIFT (26U) /*! KernelW - KernelW */ #define NEUTRON_CANVAS_PDS_STRIDES_KernelW(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_STRIDES_KernelW_SHIFT)) & NEUTRON_CANVAS_PDS_STRIDES_KernelW_MASK) /*! @} */ /*! @name SCRATCH3_5 - Scratch Register 0..Scratch Register 2 */ /*! @{ */ #define NEUTRON_SCRATCH3_5_SCR_MASK (0xFFFFFFFFU) #define NEUTRON_SCRATCH3_5_SCR_SHIFT (0U) /*! SCR - Scratch */ #define NEUTRON_SCRATCH3_5_SCR(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_SCRATCH3_5_SCR_SHIFT)) & NEUTRON_SCRATCH3_5_SCR_MASK) /*! @} */ /* The count of NEUTRON_SCRATCH3_5 */ #define NEUTRON_SCRATCH3_5_COUNT (3U) /*! @name ACTCTRL2 - Activation Control */ /*! @{ */ #define NEUTRON_ACTCTRL2_UPPER_ACT_SCALE_MASK (0x3FFU) #define NEUTRON_ACTCTRL2_UPPER_ACT_SCALE_SHIFT (0U) /*! UPPER_ACT_SCALE - Upper Activation scale */ #define NEUTRON_ACTCTRL2_UPPER_ACT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_UPPER_ACT_SCALE_SHIFT)) & NEUTRON_ACTCTRL2_UPPER_ACT_SCALE_MASK) #define NEUTRON_ACTCTRL2_HW_INTERPOLATE_MASK (0x400U) #define NEUTRON_ACTCTRL2_HW_INTERPOLATE_SHIFT (10U) /*! HW_INTERPOLATE - Hardware Interpolator */ #define NEUTRON_ACTCTRL2_HW_INTERPOLATE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_HW_INTERPOLATE_SHIFT)) & NEUTRON_ACTCTRL2_HW_INTERPOLATE_MASK) #define NEUTRON_ACTCTRL2_INTERPOLATE_ORDER_MASK (0x1800U) #define NEUTRON_ACTCTRL2_INTERPOLATE_ORDER_SHIFT (11U) /*! INTERPOLATE_ORDER - Interpolation Order */ #define NEUTRON_ACTCTRL2_INTERPOLATE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_INTERPOLATE_ORDER_SHIFT)) & NEUTRON_ACTCTRL2_INTERPOLATE_ORDER_MASK) #define NEUTRON_ACTCTRL2_INTERPOLATOR_BITS_MASK (0x1E000U) #define NEUTRON_ACTCTRL2_INTERPOLATOR_BITS_SHIFT (13U) /*! INTERPOLATOR_BITS - Interpolator Bits for lookup in a table */ #define NEUTRON_ACTCTRL2_INTERPOLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_INTERPOLATOR_BITS_SHIFT)) & NEUTRON_ACTCTRL2_INTERPOLATOR_BITS_MASK) #define NEUTRON_ACTCTRL2_INTERPOLATOR_BYTES_MASK (0x20000U) #define NEUTRON_ACTCTRL2_INTERPOLATOR_BYTES_SHIFT (17U) /*! INTERPOLATOR_BYTES - Interpolator Byte mode (default is 16 bits) */ #define NEUTRON_ACTCTRL2_INTERPOLATOR_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_INTERPOLATOR_BYTES_SHIFT)) & NEUTRON_ACTCTRL2_INTERPOLATOR_BYTES_MASK) #define NEUTRON_ACTCTRL2_INTERPOLATOR_POST_PROC_MASK (0x40000U) #define NEUTRON_ACTCTRL2_INTERPOLATOR_POST_PROC_SHIFT (18U) /*! INTERPOLATOR_POST_PROC - Interpolator use post processing */ #define NEUTRON_ACTCTRL2_INTERPOLATOR_POST_PROC(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_INTERPOLATOR_POST_PROC_SHIFT)) & NEUTRON_ACTCTRL2_INTERPOLATOR_POST_PROC_MASK) #define NEUTRON_ACTCTRL2_INTERPOLATOR_UNSIGNED_SAT_MASK (0x80000U) #define NEUTRON_ACTCTRL2_INTERPOLATOR_UNSIGNED_SAT_SHIFT (19U) /*! INTERPOLATOR_UNSIGNED_SAT - Interpolator Allow Unsigned Saturation (default is signed) */ #define NEUTRON_ACTCTRL2_INTERPOLATOR_UNSIGNED_SAT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_INTERPOLATOR_UNSIGNED_SAT_SHIFT)) & NEUTRON_ACTCTRL2_INTERPOLATOR_UNSIGNED_SAT_MASK) #define NEUTRON_ACTCTRL2_INTERPOLATOR_POST_SCALE_MASK (0xFFF00000U) #define NEUTRON_ACTCTRL2_INTERPOLATOR_POST_SCALE_SHIFT (20U) /*! INTERPOLATOR_POST_SCALE - Interpolator Post Scale */ #define NEUTRON_ACTCTRL2_INTERPOLATOR_POST_SCALE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL2_INTERPOLATOR_POST_SCALE_SHIFT)) & NEUTRON_ACTCTRL2_INTERPOLATOR_POST_SCALE_MASK) /*! @} */ /*! @name INTERPOLBASE - Interpolator Base Address */ /*! @{ */ #define NEUTRON_INTERPOLBASE_ADDR_MASK (0xFFFFFFFCU) #define NEUTRON_INTERPOLBASE_ADDR_SHIFT (2U) /*! ADDR - Interpolator base address value */ #define NEUTRON_INTERPOLBASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTERPOLBASE_ADDR_SHIFT)) & NEUTRON_INTERPOLBASE_ADDR_MASK) /*! @} */ /*! @name CANVAS_PDS_INP - CANVAS Pad Data Supervisor Input */ /*! @{ */ #define NEUTRON_CANVAS_PDS_INP_INP_H_MASK (0xFFFU) #define NEUTRON_CANVAS_PDS_INP_INP_H_SHIFT (0U) /*! INP_H - INP_H */ #define NEUTRON_CANVAS_PDS_INP_INP_H(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_INP_INP_H_SHIFT)) & NEUTRON_CANVAS_PDS_INP_INP_H_MASK) #define NEUTRON_CANVAS_PDS_INP_INP_W_MASK (0xFFF000U) #define NEUTRON_CANVAS_PDS_INP_INP_W_SHIFT (12U) /*! INP_W - INP_W */ #define NEUTRON_CANVAS_PDS_INP_INP_W(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_INP_INP_W_SHIFT)) & NEUTRON_CANVAS_PDS_INP_INP_W_MASK) #define NEUTRON_CANVAS_PDS_INP_CinReads_MASK (0xFF000000U) #define NEUTRON_CANVAS_PDS_INP_CinReads_SHIFT (24U) /*! CinReads - CinReads */ #define NEUTRON_CANVAS_PDS_INP_CinReads(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_PDS_INP_CinReads_SHIFT)) & NEUTRON_CANVAS_PDS_INP_CinReads_MASK) /*! @} */ /*! @name CANVAS_SECOND_X_ADJ - CANVAS_SECOND_X_ADJ */ /*! @{ */ #define NEUTRON_CANVAS_SECOND_X_ADJ_COUNT_MASK (0xFU) #define NEUTRON_CANVAS_SECOND_X_ADJ_COUNT_SHIFT (0U) /*! COUNT - Count between adjustments */ #define NEUTRON_CANVAS_SECOND_X_ADJ_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECOND_X_ADJ_COUNT_SHIFT)) & NEUTRON_CANVAS_SECOND_X_ADJ_COUNT_MASK) #define NEUTRON_CANVAS_SECOND_X_ADJ_START_MASK (0xF0U) #define NEUTRON_CANVAS_SECOND_X_ADJ_START_SHIFT (4U) /*! START - Start */ #define NEUTRON_CANVAS_SECOND_X_ADJ_START(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECOND_X_ADJ_START_SHIFT)) & NEUTRON_CANVAS_SECOND_X_ADJ_START_MASK) #define NEUTRON_CANVAS_SECOND_X_ADJ_SIGNED_STRIDE_MASK (0xFFFFFC00U) #define NEUTRON_CANVAS_SECOND_X_ADJ_SIGNED_STRIDE_SHIFT (10U) /*! SIGNED_STRIDE - Stride */ #define NEUTRON_CANVAS_SECOND_X_ADJ_SIGNED_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_CANVAS_SECOND_X_ADJ_SIGNED_STRIDE_SHIFT)) & NEUTRON_CANVAS_SECOND_X_ADJ_SIGNED_STRIDE_MASK) /*! @} */ /*! @name INTERPOLOFF - Interpolator Offset */ /*! @{ */ #define NEUTRON_INTERPOLOFF_OFFSET_MASK (0xFFFFU) #define NEUTRON_INTERPOLOFF_OFFSET_SHIFT (0U) /*! OFFSET - Interpolator Offset */ #define NEUTRON_INTERPOLOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_INTERPOLOFF_OFFSET_SHIFT)) & NEUTRON_INTERPOLOFF_OFFSET_MASK) /*! @} */ /*! @name ACTCTRL3 - Activation scale */ /*! @{ */ #define NEUTRON_ACTCTRL3_ACTCTRL3_MASK (0x3FFU) #define NEUTRON_ACTCTRL3_ACTCTRL3_SHIFT (0U) /*! ACTCTRL3 - Activation scale */ #define NEUTRON_ACTCTRL3_ACTCTRL3(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL3_ACTCTRL3_SHIFT)) & NEUTRON_ACTCTRL3_ACTCTRL3_MASK) #define NEUTRON_ACTCTRL3_EN_ALT_SCALE_MASK (0x10000U) #define NEUTRON_ACTCTRL3_EN_ALT_SCALE_SHIFT (16U) /*! EN_ALT_SCALE - Enable Alternate Scaling * 0b0..Disabled * 0b1..If scaling factor is 16-bit then accurate FP16 is enabled else scaling factor is 32-bit with single-precision floating-point */ #define NEUTRON_ACTCTRL3_EN_ALT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ACTCTRL3_EN_ALT_SCALE_SHIFT)) & NEUTRON_ACTCTRL3_EN_ALT_SCALE_MASK) /*! @} */ /*! @name DATABASE - Base address for Data Canvas loading */ /*! @{ */ #define NEUTRON_DATABASE_BASE_MASK (0xFFFFFFFFU) #define NEUTRON_DATABASE_BASE_SHIFT (0U) /*! BASE - Base Address for Data Canvas loading */ #define NEUTRON_DATABASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_DATABASE_BASE_SHIFT)) & NEUTRON_DATABASE_BASE_MASK) /*! @} */ /*! @name RESBASE - Result base address for pipeline */ /*! @{ */ #define NEUTRON_RESBASE_BASE_MASK (0xFFFFFFFFU) #define NEUTRON_RESBASE_BASE_SHIFT (0U) /*! BASE - Result Base Address for pipeline 0 */ #define NEUTRON_RESBASE_BASE(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_RESBASE_BASE_SHIFT)) & NEUTRON_RESBASE_BASE_MASK) /*! @} */ /*! @name ID - Neutron ID */ /*! @{ */ #define NEUTRON_ID_MACS_MASK (0xFU) #define NEUTRON_ID_MACS_SHIFT (0U) /*! MACS - MACS Number */ #define NEUTRON_ID_MACS(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ID_MACS_SHIFT)) & NEUTRON_ID_MACS_MASK) #define NEUTRON_ID_PIPELINES_MASK (0xF0U) #define NEUTRON_ID_PIPELINES_SHIFT (4U) /*! PIPELINES - PIPELINES Number */ #define NEUTRON_ID_PIPELINES(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ID_PIPELINES_SHIFT)) & NEUTRON_ID_PIPELINES_MASK) #define NEUTRON_ID_CANVAS_MASK (0x100U) #define NEUTRON_ID_CANVAS_SHIFT (8U) /*! CANVAS - Canvas Presence */ #define NEUTRON_ID_CANVAS(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ID_CANVAS_SHIFT)) & NEUTRON_ID_CANVAS_MASK) #define NEUTRON_ID_POOLING_MASK (0x200U) #define NEUTRON_ID_POOLING_SHIFT (9U) /*! POOLING - Pooling Presence */ #define NEUTRON_ID_POOLING(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ID_POOLING_SHIFT)) & NEUTRON_ID_POOLING_MASK) #define NEUTRON_ID_RESBUS_MASK (0x400U) #define NEUTRON_ID_RESBUS_SHIFT (10U) /*! RESBUS - Separate Results Number */ #define NEUTRON_ID_RESBUS(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ID_RESBUS_SHIFT)) & NEUTRON_ID_RESBUS_MASK) #define NEUTRON_ID_VERSION_MASK (0xFFF0000U) #define NEUTRON_ID_VERSION_SHIFT (16U) /*! VERSION - Version ID */ #define NEUTRON_ID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ID_VERSION_SHIFT)) & NEUTRON_ID_VERSION_MASK) #define NEUTRON_ID_ARCH_MASK (0xF0000000U) #define NEUTRON_ID_ARCH_SHIFT (28U) /*! ARCH - Arch Type */ #define NEUTRON_ID_ARCH(x) (((uint32_t)(((uint32_t)(x)) << NEUTRON_ID_ARCH_SHIFT)) & NEUTRON_ID_ARCH_MASK) /*! @} */ /*! * @} */ /* end of group NEUTRON_Register_Masks */ /* NEUTRON - Peripheral instance base addresses */ /** Peripheral NPU__NEUTRON_NPU__NEUTRON0__NEUTRON base address */ #define NPU__NEUTRON_NPU__NEUTRON0__NEUTRON_BASE (0x4ABC0000u) /** Peripheral NPU__NEUTRON_NPU__NEUTRON0__NEUTRON base pointer */ #define NPU__NEUTRON_NPU__NEUTRON0__NEUTRON ((NEUTRON_Type *)NPU__NEUTRON_NPU__NEUTRON0__NEUTRON_BASE) /** Peripheral NPU__NEUTRON_NPU__NEUTRON1__NEUTRON base address */ #define NPU__NEUTRON_NPU__NEUTRON1__NEUTRON_BASE (0x4ABC1000u) /** Peripheral NPU__NEUTRON_NPU__NEUTRON1__NEUTRON base pointer */ #define NPU__NEUTRON_NPU__NEUTRON1__NEUTRON ((NEUTRON_Type *)NPU__NEUTRON_NPU__NEUTRON1__NEUTRON_BASE) /** Peripheral NPU__NEUTRON_NPU__NEUTRON2__NEUTRON base address */ #define NPU__NEUTRON_NPU__NEUTRON2__NEUTRON_BASE (0x4ABC2000u) /** Peripheral NPU__NEUTRON_NPU__NEUTRON2__NEUTRON base pointer */ #define NPU__NEUTRON_NPU__NEUTRON2__NEUTRON ((NEUTRON_Type *)NPU__NEUTRON_NPU__NEUTRON2__NEUTRON_BASE) /** Peripheral NPU__NEUTRON_NPU__NEUTRON3__NEUTRON base address */ #define NPU__NEUTRON_NPU__NEUTRON3__NEUTRON_BASE (0x4ABC3000u) /** Peripheral NPU__NEUTRON_NPU__NEUTRON3__NEUTRON base pointer */ #define NPU__NEUTRON_NPU__NEUTRON3__NEUTRON ((NEUTRON_Type *)NPU__NEUTRON_NPU__NEUTRON3__NEUTRON_BASE) /** Peripheral NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON base address */ #define NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON_BASE (0x4ABC4000u) /** Peripheral NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON base pointer */ #define NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON ((NEUTRON_Type *)NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON_BASE) /** Array initializer of NEUTRON peripheral base addresses */ #define NEUTRON_BASE_ADDRS { NPU__NEUTRON_NPU__NEUTRON0__NEUTRON_BASE, NPU__NEUTRON_NPU__NEUTRON1__NEUTRON_BASE, NPU__NEUTRON_NPU__NEUTRON2__NEUTRON_BASE, NPU__NEUTRON_NPU__NEUTRON3__NEUTRON_BASE, NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON_BASE } /** Array initializer of NEUTRON peripheral base pointers */ #define NEUTRON_BASE_PTRS { NPU__NEUTRON_NPU__NEUTRON0__NEUTRON, NPU__NEUTRON_NPU__NEUTRON1__NEUTRON, NPU__NEUTRON_NPU__NEUTRON2__NEUTRON, NPU__NEUTRON_NPU__NEUTRON3__NEUTRON, NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON } /*! * @} */ /* end of group NEUTRON_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ALWAYS_ON_MAIN_RESFAULTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ALWAYS_ON_MAIN_RESFAULTC_Peripheral_Access_Layer NOC_ALWAYS_ON_MAIN_RESFAULTC Peripheral Access Layer * @{ */ /** NOC_ALWAYS_ON_MAIN_RESFAULTC - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __I uint32_t MISSIONFAULT[4]; /**< Mission Fault n, array offset: 0x8, array step: 0x4 */ __I uint32_t LATENTFAULT[4]; /**< Latent Fault n, array offset: 0x18, array step: 0x4 */ __I uint32_t FAULTS; /**< Interrupt Enable, offset: 0x28 */ __IO uint32_t INTEN; /**< Interrupt Enable, offset: 0x2C */ __O uint32_t INTCLR; /**< InterruptClear, offset: 0x30 */ __O uint32_t BISTCTL; /**< BistControl, offset: 0x34 */ __I uint32_t BISTDONE; /**< BistDone, offset: 0x38 */ __IO uint32_t BISTTO1; /**< Bist T01, offset: 0x3C */ __IO uint32_t BISTTO2; /**< Bist T02, offset: 0x40 */ } NOC_ALWAYS_ON_MAIN_RESFAULTC_Type; /* ---------------------------------------------------------------------------- -- NOC_ALWAYS_ON_MAIN_RESFAULTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ALWAYS_ON_MAIN_RESFAULTC_Register_Masks NOC_ALWAYS_ON_MAIN_RESFAULTC Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORETYPEID_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORETYPEID_MASK) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_USERID_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_USERID_MASK) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_NOCID_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MISSIONFAULT - Mission Fault n */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_MISSIONFAULT_MISSIONFAULT_MASK (0xFFFFFFFFU) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_MISSIONFAULT_MISSIONFAULT_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_MISSIONFAULT_MISSIONFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_MISSIONFAULT_MISSIONFAULT_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_MISSIONFAULT_MISSIONFAULT_MASK) /*! @} */ /* The count of NOC_ALWAYS_ON_MAIN_RESFAULTC_MISSIONFAULT */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_MISSIONFAULT_COUNT (4U) /*! @name LATENTFAULT - Latent Fault n */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_LATENTFAULT_LATENTFAULT_MASK (0xFFFFFFFFU) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_LATENTFAULT_LATENTFAULT_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_LATENTFAULT_LATENTFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_LATENTFAULT_LATENTFAULT_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_LATENTFAULT_LATENTFAULT_MASK) /*! @} */ /* The count of NOC_ALWAYS_ON_MAIN_RESFAULTC_LATENTFAULT */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_LATENTFAULT_COUNT (4U) /*! @name FAULTS - Interrupt Enable */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_LATENTFAULT_MASK (0x1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_LATENTFAULT_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_LATENTFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_LATENTFAULT_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_LATENTFAULT_MASK) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_MISSIONFAULT_MASK (0x2U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_MISSIONFAULT_SHIFT (1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_MISSIONFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_MISSIONFAULT_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_FAULTS_MISSIONFAULT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_BISTDONEEN_MASK (0x1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_BISTDONEEN_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_BISTDONEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_BISTDONEEN_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_BISTDONEEN_MASK) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_MISSIONFAULTEN_MASK (0x2U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_MISSIONFAULTEN_SHIFT (1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_MISSIONFAULTEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_MISSIONFAULTEN_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_INTEN_MISSIONFAULTEN_MASK) /*! @} */ /*! @name INTCLR - InterruptClear */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_LATENTFAULTCLR_MASK (0x1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_LATENTFAULTCLR_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_LATENTFAULTCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_LATENTFAULTCLR_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_LATENTFAULTCLR_MASK) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_MISSIONFAULTCLR_MASK (0x2U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_MISSIONFAULTCLR_SHIFT (1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_MISSIONFAULTCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_MISSIONFAULTCLR_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_INTCLR_MISSIONFAULTCLR_MASK) /*! @} */ /*! @name BISTCTL - BistControl */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTSTART_MASK (0x1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTSTART_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTSTART(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTSTART_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTSTART_MASK) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTDONECLR_MASK (0x2U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTDONECLR_SHIFT (1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTDONECLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTDONECLR_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTCTL_BISTDONECLR_MASK) /*! @} */ /*! @name BISTDONE - BistDone */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_BISTDONE_MASK (0x1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_BISTDONE_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_BISTDONE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_BISTDONE_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_BISTDONE_MASK) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_MISSIONMODE_MASK (0x2U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_MISSIONMODE_SHIFT (1U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_MISSIONMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_MISSIONMODE_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTDONE_MISSIONMODE_MASK) /*! @} */ /*! @name BISTTO1 - Bist T01 */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO1_BISTTO1_MASK (0xFFFFU) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO1_BISTTO1_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO1_BISTTO1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO1_BISTTO1_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO1_BISTTO1_MASK) /*! @} */ /*! @name BISTTO2 - Bist T02 */ /*! @{ */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO2_BISTTO2_MASK (0xFFU) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO2_BISTTO2_SHIFT (0U) #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO2_BISTTO2(x) (((uint32_t)(((uint32_t)(x)) << NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO2_BISTTO2_SHIFT)) & NOC_ALWAYS_ON_MAIN_RESFAULTC_BISTTO2_BISTTO2_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ALWAYS_ON_MAIN_RESFAULTC_Register_Masks */ /* NOC_ALWAYS_ON_MAIN_RESFAULTC - Peripheral instance base addresses */ /** Peripheral NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER base address */ #define NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER_BASE (0x49063080u) /** Peripheral NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER base pointer */ #define NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER ((NOC_ALWAYS_ON_MAIN_RESFAULTC_Type *)NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER_BASE) /** Array initializer of NOC_ALWAYS_ON_MAIN_RESFAULTC peripheral base addresses * */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BASE_ADDRS { NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER_BASE } /** Array initializer of NOC_ALWAYS_ON_MAIN_RESFAULTC peripheral base pointers */ #define NOC_ALWAYS_ON_MAIN_RESFAULTC_BASE_PTRS { NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER } /*! * @} */ /* end of group NOC_ALWAYS_ON_MAIN_RESFAULTC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_BLK_CTRL_NOCMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_BLK_CTRL_NOCMIX_Peripheral_Access_Layer NOC_BLK_CTRL_NOCMIX Peripheral Access Layer * @{ */ /** NOC_BLK_CTRL_NOCMIX - Register Layout Typedef */ typedef struct { __IO uint32_t DEXSC_ERR; /**< DEXSC error response configuration, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t AXI_LIMIT_WAKEUPMIX; /**< AXI limit wakeupmix configuration, offset: 0x8 */ __IO uint32_t CACHE_ATTR; /**< AxCACHE[1] override configuration register, offset: 0xC */ uint8_t RESERVED_1[20]; __IO uint32_t TIE_VALUE; /**< GPR for uncertain tie0 or tie1, offset: 0x24 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_0; /**< AXI beat limiter 0 configuration, offset: 0x28 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_1; /**< AXI beat limiter 1 configuration, offset: 0x2C */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_2; /**< AXI beat limiter 2 configuration, offset: 0x30 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_3; /**< AXI beat limiter 3 configuration, offset: 0x34 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_4; /**< AXI beat limiter 4 configuration, offset: 0x38 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_5; /**< AXI beat limiter 5 configuration, offset: 0x3C */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_6; /**< AXI beat limiter 6 configuration, offset: 0x40 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_7; /**< AXI beat limiter 7 configuration, offset: 0x44 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_8; /**< AXI beat limiter 8 configuration, offset: 0x48 */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_9; /**< AXI beat limiter 9 configuration, offset: 0x4C */ __IO uint32_t AXI_LIMIT_BEAT_LIMITER_10; /**< AXI beat limiter 10 configuration, offset: 0x50 */ __IO uint32_t WAKEUPMIX_PRESSURE_HURRY; /**< WAKEUPMIX pressure/hurry value configuration, offset: 0x54 */ __IO uint32_t VPUMIX_PRESSURE_HURRY; /**< VPUMIX pressure/hurry value configuration, offset: 0x58 */ __IO uint32_t HSIOMIX_PRESSURE_HURRY; /**< HSIOMUX pressure/hurry value configuration, offset: 0x5C */ __IO uint32_t MMU700_PRESSURE_HURRY; /**< MMU700 pressure/hurry value configuration, offset: 0x60 */ __IO uint32_t NETCMIX_PRESSURE_HURRY; /**< NETCMIX pressure/hurry value configuration, offset: 0x64 */ __IO uint32_t DISPLAYMIX_RT_PRESSURE_HURRY; /**< DISPLAYMIX_RT pressure/hurry value configuration, offset: 0x68 */ __IO uint32_t GPUMIX_PRESSURE_HURRY; /**< GPUMIX pressure/hurry value configuration, offset: 0x6C */ __IO uint32_t NPUMIX_PRESSURE_HURRY; /**< NPUMIX pressure/hurry value configuration, offset: 0x70 */ __IO uint32_t GIC700_PRESSURE_HURRY; /**< GIC700 pressure/hurry value configuration, offset: 0x74 */ __IO uint32_t CORTEXAMIX_B_PRESSURE_HURRY; /**< CORTEXAMIX B pressure/hurry value configuration, offset: 0x78 */ __IO uint32_t CORTEXAMIX_A_PRESSURE_HURRY; /**< CORTEXAMIX A pressure/hurry value configuration, offset: 0x7C */ __IO uint32_t OCRAM_SGLECC_ERR_INT; /**< OCRAM single ECC error interrupt flag, offset: 0x80 */ uint8_t RESERVED_2[60]; __IO uint32_t NIU_TO_CTRL_WAKEUP; /**< WAKEUPMIX NIU Timeout Control Register, offset: 0xC0 */ __IO uint32_t NIU_TO_CTRL_CORTEXA; /**< CORTEXAMIX NIU Timeout Control Register, offset: 0xC4 */ __IO uint32_t NIU_TO_CTRL_GIC700; /**< GIC700 NIU Timeout Control Register, offset: 0xC8 */ __IO uint32_t NIU_TO_CTRL_NPU; /**< NPUMIX NIU Timeout Control Register, offset: 0xCC */ __IO uint32_t NIU_TO_CTRL_GPU; /**< GPUMIX NIU Timeout Control Register, offset: 0xD0 */ __IO uint32_t NIU_TO_CTRL_CAMERA; /**< CAMERAMIX NIU Timeout Control Register, offset: 0xD4 */ __IO uint32_t NIU_TO_CTRL_DISPLAY_RT; /**< DISPLAYMIX (real time) NIU Timeout Control Register, offset: 0xD8 */ __IO uint32_t NIU_TO_CTRL_NETC; /**< NETCMIX NIU Timeout Control Register, offset: 0xDC */ __IO uint32_t NIU_TO_CTRL_MMU700; /**< MMU700 NIU Timeout Control Register, offset: 0xE0 */ __IO uint32_t NIU_TO_CTRL_HSIO; /**< HSIOMIX NIU Timeout Control Register, offset: 0xE4 */ __IO uint32_t NIU_TO_CTRL_DISPLAY_BE; /**< DISPLAYMIX (best effort) NIU Timeout Control Register, offset: 0xE8 */ __IO uint32_t NIU_TO_CTRL_VPU; /**< VPUMIX NIU Timeout Control Register, offset: 0xEC */ __IO uint32_t INITIATOR_TIMEOUT; /**< Register for initiator timeout, offset: 0xF0 */ } NOC_BLK_CTRL_NOCMIX_Type; /* ---------------------------------------------------------------------------- -- NOC_BLK_CTRL_NOCMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_BLK_CTRL_NOCMIX_Register_Masks NOC_BLK_CTRL_NOCMIX Register Masks * @{ */ /*! @name DEXSC_ERR - DEXSC error response configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_ERR_RESP_EN_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_ERR_RESP_EN_SHIFT (0U) /*! NPU_ERR_RESP_EN - NPU RAM error response enable */ #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_ERR_RESP_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_ERR_RESP_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_EXC_ERR_RESP_EN_MASK (0x2U) #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_EXC_ERR_RESP_EN_SHIFT (1U) /*! NPU_EXC_ERR_RESP_EN - NPU RAM exclusive access error response enable */ #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_EXC_ERR_RESP_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_EXC_ERR_RESP_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_LOCK_ERR_RESP_EN_MASK (0x4U) #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_LOCK_ERR_RESP_EN_SHIFT (2U) /*! NPU_LOCK_ERR_RESP_EN - NPU RAM lock error response enable */ #define NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_LOCK_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_LOCK_ERR_RESP_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_DEXSC_ERR_NPU_LOCK_ERR_RESP_EN_MASK) /*! @} */ /*! @name AXI_LIMIT_WAKEUPMIX - AXI limit wakeupmix configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_ENABLE_SHIFT (0U) /*! ENABLE - Enable beat limiter */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_WAKEUPMIX_BEAT_LIMIT_MASK) /*! @} */ /*! @name CACHE_ATTR - AxCACHE[1] override configuration register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_SHIFT (0U) /*! WAKEUPMIX_ARCACHE_EN - WAKEUPMIX ARCACHE[1] override enable */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_MASK (0x2U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_SHIFT (1U) /*! WAKEUPMIX_AWCACHE_EN - WAKEUPMIX AWCACHE[1] override enable */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_EN_MASK (0x4U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_EN_SHIFT (2U) /*! CACHE_ARCACHE_EN - CACHE ARCACHE[1] override enable */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_EN_MASK (0x8U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_EN_SHIFT (3U) /*! CACHE_AWCACHE_EN - CACHE AWCACHE[1] override enable */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_EN_MASK (0x10U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_EN_SHIFT (4U) /*! HSIOMIX_ARCACHE_EN - HSIOMIX ARCACHE[1] override enable */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_EN_MASK (0x20U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_EN_SHIFT (5U) /*! HSIOMIX_AWCACHE_EN - HSIOMIX AWCACHE[1] override enable */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_EN_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_EN_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_MASK (0x10000U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_SHIFT (16U) /*! WAKEUPMIX_ARCACHE - WAKEUPMIX ARCACHE[1] override value */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_ARCACHE_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_MASK (0x20000U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_SHIFT (17U) /*! WAKEUPMIX_AWCACHE - WAKEUPMIX AWCACHE[1] override value */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_WAKEUPMIX_AWCACHE_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_MASK (0x40000U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_SHIFT (18U) /*! CACHE_ARCACHE - CACHE ARCACHE[1] override value */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_ARCACHE_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_MASK (0x80000U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_SHIFT (19U) /*! CACHE_AWCACHE - CACHE AWCACHE[1] override value */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_CACHE_AWCACHE_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_MASK (0x100000U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_SHIFT (20U) /*! HSIOMIX_ARCACHE - HSIOMIX ARCACHE[1] override value */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_ARCACHE_MASK) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_MASK (0x200000U) #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_SHIFT (21U) /*! HSIOMIX_AWCACHE - HSIOMIX AWCACHE[1] override value */ #define NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CACHE_ATTR_HSIOMIX_AWCACHE_MASK) /*! @} */ /*! @name TIE_VALUE - GPR for uncertain tie0 or tie1 */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AIPS4_HBSTRB_MASK (0xFU) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AIPS4_HBSTRB_SHIFT (0U) /*! AIPS4_HBSTRB - AIPS4_HBSTRB tie */ #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AIPS4_HBSTRB(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AIPS4_HBSTRB_SHIFT)) & NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AIPS4_HBSTRB_MASK) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICT_ALLOW_NS_MASK (0x40U) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICT_ALLOW_NS_SHIFT (6U) /*! GICT_ALLOW_NS - GICT_ALLOW_NS */ #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICT_ALLOW_NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICT_ALLOW_NS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICT_ALLOW_NS_MASK) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICP_ALLOW_NS_MASK (0x80U) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICP_ALLOW_NS_SHIFT (7U) /*! GICP_ALLOW_NS - GICP_ALLOW_NS tie */ #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICP_ALLOW_NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICP_ALLOW_NS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_TIE_VALUE_GICP_ALLOW_NS_MASK) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_ARSNOOP_S_MASK (0x3C0000U) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_ARSNOOP_S_SHIFT (18U) /*! ARSNOOP_S - ARSNOOP_S tie */ #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_ARSNOOP_S(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_TIE_VALUE_ARSNOOP_S_SHIFT)) & NOC_BLK_CTRL_NOCMIX_TIE_VALUE_ARSNOOP_S_MASK) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AWSNOOP_S_MASK (0x3C00000U) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AWSNOOP_S_SHIFT (22U) /*! AWSNOOP_S - AWNSOOP_S tie */ #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AWSNOOP_S(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AWSNOOP_S_SHIFT)) & NOC_BLK_CTRL_NOCMIX_TIE_VALUE_AWSNOOP_S_MASK) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_DFTRAMHOLD_MASK (0x20000000U) #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_DFTRAMHOLD_SHIFT (29U) /*! DFTRAMHOLD - DFTRAMHOLD tie */ #define NOC_BLK_CTRL_NOCMIX_TIE_VALUE_DFTRAMHOLD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_TIE_VALUE_DFTRAMHOLD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_TIE_VALUE_DFTRAMHOLD_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_0 - AXI beat limiter 0 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 0 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_0_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_1 - AXI beat limiter 1 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 1 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_1_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_2 - AXI beat limiter 2 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 2 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_2_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_3 - AXI beat limiter 3 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 3 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_3_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_4 - AXI beat limiter 4 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 4 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_4_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_5 - AXI beat limiter 5 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 5 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_5_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_6 - AXI beat limiter 6 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 6 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_6_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_7 - AXI beat limiter 7 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 7 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_7_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_8 - AXI beat limiter 8 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 8 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_8_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_9 - AXI beat limiter 9 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 9 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_9_BEAT_LIMIT_MASK) /*! @} */ /*! @name AXI_LIMIT_BEAT_LIMITER_10 - AXI beat limiter 10 configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_ENABLE_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_ENABLE_SHIFT (0U) /*! ENABLE - Beat limiter 10 enable */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_ENABLE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_ENABLE_MASK) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_BEAT_LIMIT_MASK (0xFFFF0000U) #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_BEAT_LIMIT_SHIFT (16U) /*! BEAT_LIMIT - Burst beat limit */ #define NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_BEAT_LIMIT_SHIFT)) & NOC_BLK_CTRL_NOCMIX_AXI_LIMIT_BEAT_LIMITER_10_BEAT_LIMIT_MASK) /*! @} */ /*! @name WAKEUPMIX_PRESSURE_HURRY - WAKEUPMIX pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - WAKEUPMIX hurry value */ #define NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - WAKUPMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_WAKEUPMIX_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name VPUMIX_PRESSURE_HURRY - VPUMIX pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - VPUMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - VPUMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_VPUMIX_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name HSIOMIX_PRESSURE_HURRY - HSIOMUX pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - HSIOMIX hurry value */ #define NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - HSIOMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_HSIOMIX_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name MMU700_PRESSURE_HURRY - MMU700 pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - MMU700 hurry value */ #define NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - MMU700 pressure value */ #define NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_MMU700_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name NETCMIX_PRESSURE_HURRY - NETCMIX pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - NETCMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - NETCMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NETCMIX_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name DISPLAYMIX_RT_PRESSURE_HURRY - DISPLAYMIX_RT pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - DISPLAYMIX_RT hurry value */ #define NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - DISPLAYMIX_RT pressure value */ #define NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_DISPLAYMIX_RT_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name GPUMIX_PRESSURE_HURRY - GPUMIX pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - GPUMIX hurry value */ #define NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - GPUMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_GPUMIX_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name NPUMIX_PRESSURE_HURRY - NPUMIX pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - NPUMIX hurry value */ #define NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - NPUMIX pressure value */ #define NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NPUMIX_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name GIC700_PRESSURE_HURRY - GIC700 pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - GIC700 hurry value */ #define NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - GIC700 pressure value */ #define NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_GIC700_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name CORTEXAMIX_B_PRESSURE_HURRY - CORTEXAMIX B pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - CORTEXAMIX B hurry value */ #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - CORTEXAMIX B pressure value */ #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_B_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name CORTEXAMIX_A_PRESSURE_HURRY - CORTEXAMIX A pressure/hurry value configuration */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_HURRY_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_HURRY_SHIFT (0U) /*! HURRY - CORTEXAMIX A hurry value */ #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_HURRY(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_HURRY_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_HURRY_MASK) #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_PRESSURE_MASK (0x38U) #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_PRESSURE_SHIFT (3U) /*! PRESSURE - CORTEXAMIX A pressure value */ #define NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_PRESSURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_PRESSURE_SHIFT)) & NOC_BLK_CTRL_NOCMIX_CORTEXAMIX_A_PRESSURE_HURRY_PRESSURE_MASK) /*! @} */ /*! @name OCRAM_SGLECC_ERR_INT - OCRAM single ECC error interrupt flag */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_SHIFT (0U) /*! SGL_ECC_ERR_IF - OCRAM single ECC error interrupt flag */ #define NOC_BLK_CTRL_NOCMIX_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_SHIFT)) & NOC_BLK_CTRL_NOCMIX_OCRAM_SGLECC_ERR_INT_SGL_ECC_ERR_IF_MASK) /*! @} */ /*! @name NIU_TO_CTRL_WAKEUP - WAKEUPMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_WAKEUP_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_CORTEXA - CORTEXAMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CORTEXA_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_GIC700 - GIC700 NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GIC700_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_NPU - NPUMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NPU_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_GPU - GPUMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_GPU_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_CAMERA - CAMERAMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_CAMERA_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_DISPLAY_RT - DISPLAYMIX (real time) NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_RT_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_NETC - NETCMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_NETC_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_MMU700 - MMU700 NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_MMU700_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_HSIO - HSIOMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_HSIO_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_DISPLAY_BE - DISPLAYMIX (best effort) NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_DISPLAY_BE_DIS_MASK) /*! @} */ /*! @name NIU_TO_CTRL_VPU - VPUMIX NIU Timeout Control Register */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_CLK_DIV_RATIO_MASK (0x7U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_CLK_DIV_RATIO_SHIFT (0U) /*! CLK_DIV_RATIO - Division ratio for external reference clock * 0b000..Divide by 4 * 0b001..Divide by 8 * 0b010..Divide by 16 * 0b011..Divide by 32 * 0b100..Divide by 64 * 0b101..Divide by 128 * 0b110..Divide by 256 * 0b111..Divide by 512 */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_CLK_DIV_RATIO_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_CLK_DIV_RATIO_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_UPD_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_UPD_SHIFT (15U) /*! UPD - Update clock division ratio */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_UPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_UPD_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_UPD_MASK) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_DIS_MASK (0x80000000U) #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_DIS_SHIFT (31U) /*! DIS - Disable timeout * 0b0..Timeout feature is enabled * 0b1..Timeout feature is disabled */ #define NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_DIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_DIS_SHIFT)) & NOC_BLK_CTRL_NOCMIX_NIU_TO_CTRL_VPU_DIS_MASK) /*! @} */ /*! @name INITIATOR_TIMEOUT - Register for initiator timeout */ /*! @{ */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_creg_timeout_MASK (0x1U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_creg_timeout_SHIFT (0U) /*! m_creg_timeout - Initiator timeout for m_creg */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_creg_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_creg_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_creg_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_rd_timeout_MASK (0x2U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_rd_timeout_SHIFT (1U) /*! m_e_0_rd_timeout - WAKEUPMIX (m_e_0) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_wr_timeout_MASK (0x4U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_wr_timeout_SHIFT (2U) /*! m_e_0_wr_timeout - WAKEUPMIX (m_e_0) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_0_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_rd_timeout_MASK (0x8U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_rd_timeout_SHIFT (3U) /*! m_e_1a_rd_timeout - CORTEXAMIX (m_e_1a) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_wr_timeout_MASK (0x10U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_wr_timeout_SHIFT (4U) /*! m_e_1a_wr_timeout - CORTEXAMIX (m_e_1a) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1a_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_rd_timeout_MASK (0x20U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_rd_timeout_SHIFT (5U) /*! m_e_1b_rd_timeout - CORTEXAMIX (m_e_1b) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_wr_timeout_MASK (0x40U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_wr_timeout_SHIFT (6U) /*! m_e_1b_wr_timeout - CORTEXAMIX (m_e_1b) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_1b_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_rd_timeout_MASK (0x80U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_rd_timeout_SHIFT (7U) /*! m_e_2_rd_timeout - GIC-700 (m_e_2) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_wr_timeout_MASK (0x100U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_wr_timeout_SHIFT (8U) /*! m_e_2_wr_timeout - GIC-700 (m_e_2) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_2_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_rd_timeout_MASK (0x200U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_rd_timeout_SHIFT (9U) /*! m_e_3_rd_timeout - NPUMIX (m_e_3) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_wr_timeout_MASK (0x400U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_wr_timeout_SHIFT (10U) /*! m_e_3_wr_timeout - NPUMIX (m_e_3) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_3_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_rd_timeout_MASK (0x800U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_rd_timeout_SHIFT (11U) /*! m_e_4_rd_timeout - GPUMIX (m_e_4) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_wr_timeout_MASK (0x1000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_wr_timeout_SHIFT (12U) /*! m_e_4_wr_timeout - GPUMIX (m_e_4) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_4_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_rd_timeout_MASK (0x2000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_rd_timeout_SHIFT (13U) /*! m_e_5_rd_timeout - CAMERAMIX (m_e_5) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_wr_timeout_MASK (0x4000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_wr_timeout_SHIFT (14U) /*! m_e_5_wr_timeout - CAMERAMIX (m_e_5) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_5_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_6_rd_timeout_MASK (0x8000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_6_rd_timeout_SHIFT (15U) /*! m_e_6_rd_timeout - DISPLAYMIX (m_e_6) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_6_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_6_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_6_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_rd_timeout_MASK (0x20000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_rd_timeout_SHIFT (17U) /*! m_e_7_rd_timeout - NETCMIX (m_e_7) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_wr_timeout_MASK (0x40000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_wr_timeout_SHIFT (18U) /*! m_e_7_wr_timeout - NETCMIX (m_e_7) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_7_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_rd_timeout_MASK (0x80000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_rd_timeout_SHIFT (19U) /*! m_e_8_rd_timeout - MMU-700 (m_e_8) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_wr_timeout_MASK (0x100000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_wr_timeout_SHIFT (20U) /*! m_e_8_wr_timeout - MMU-700 (m_e_8) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_8_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_rd_timeout_MASK (0x200000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_rd_timeout_SHIFT (21U) /*! m_e_9_rd_timeout - HSIOMIX (m_e_9) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_wr_timeout_MASK (0x400000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_wr_timeout_SHIFT (22U) /*! m_e_9_wr_timeout - HSIOMIX (m_e_9) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_9_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_rd_timeout_MASK (0x800000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_rd_timeout_SHIFT (23U) /*! m_e_10_rd_timeout - DISPLAYMIX (m_e_10) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_wr_timeout_MASK (0x1000000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_wr_timeout_SHIFT (24U) /*! m_e_10_wr_timeout - DISPLAYMIX (m_e_10) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_10_wr_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_rd_timeout_MASK (0x2000000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_rd_timeout_SHIFT (25U) /*! m_e_11_rd_timeout - GPUMIX (m_e_11) read timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_rd_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_rd_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_rd_timeout_MASK) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_wr_timeout_MASK (0x4000000U) #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_wr_timeout_SHIFT (26U) /*! m_e_11_wr_timeout - GPUMIX (m_e_11) write timeout */ #define NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_wr_timeout(x) (((uint32_t)(((uint32_t)(x)) << NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_wr_timeout_SHIFT)) & NOC_BLK_CTRL_NOCMIX_INITIATOR_TIMEOUT_m_e_11_wr_timeout_MASK) /*! @} */ /*! * @} */ /* end of group NOC_BLK_CTRL_NOCMIX_Register_Masks */ /* NOC_BLK_CTRL_NOCMIX - Peripheral instance base addresses */ /** Peripheral NOC__BLK_CTRL_NOCMIX base address */ #define NOC__BLK_CTRL_NOCMIX_BASE (0x49000000u) /** Peripheral NOC__BLK_CTRL_NOCMIX base pointer */ #define NOC__BLK_CTRL_NOCMIX ((NOC_BLK_CTRL_NOCMIX_Type *)NOC__BLK_CTRL_NOCMIX_BASE) /** Array initializer of NOC_BLK_CTRL_NOCMIX peripheral base addresses */ #define NOC_BLK_CTRL_NOCMIX_BASE_ADDRS { NOC__BLK_CTRL_NOCMIX_BASE } /** Array initializer of NOC_BLK_CTRL_NOCMIX peripheral base pointers */ #define NOC_BLK_CTRL_NOCMIX_BASE_PTRS { NOC__BLK_CTRL_NOCMIX } /*! * @} */ /* end of group NOC_BLK_CTRL_NOCMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_CMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_CMU_Peripheral_Access_Layer NOC_CMU Peripheral Access Layer * @{ */ /** NOC_CMU - Register Layout Typedef */ typedef struct { __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ __IO uint32_t SR; /**< Status Register, offset: 0x10 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ } NOC_CMU_Type; /* ---------------------------------------------------------------------------- -- NOC_CMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_CMU_Register_Masks NOC_CMU Register Masks * @{ */ /*! @name GCR - Global Configuration Register */ /*! @{ */ #define NOC_CMU_GCR_FCE_MASK (0x1U) #define NOC_CMU_GCR_FCE_SHIFT (0U) /*! FCE - Frequency Check Enable * 0b0..Stops frequency checking * 0b1..Starts frequency checking */ #define NOC_CMU_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_GCR_FCE_SHIFT)) & NOC_CMU_GCR_FCE_MASK) /*! @} */ /*! @name RCCR - Reference Count Configuration Register */ /*! @{ */ #define NOC_CMU_RCCR_REF_CNT_MASK (0xFFFFU) #define NOC_CMU_RCCR_REF_CNT_SHIFT (0U) /*! REF_CNT - Reference clock count */ #define NOC_CMU_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_RCCR_REF_CNT_SHIFT)) & NOC_CMU_RCCR_REF_CNT_MASK) /*! @} */ /*! @name HTCR - High Threshold Configuration Register */ /*! @{ */ #define NOC_CMU_HTCR_HFREF_MASK (0xFFFFFFU) #define NOC_CMU_HTCR_HFREF_SHIFT (0U) /*! HFREF - High frequency reference threshold */ #define NOC_CMU_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_HTCR_HFREF_SHIFT)) & NOC_CMU_HTCR_HFREF_MASK) /*! @} */ /*! @name LTCR - Low Threshold Configuration Register */ /*! @{ */ #define NOC_CMU_LTCR_LFREF_MASK (0xFFFFFFU) #define NOC_CMU_LTCR_LFREF_SHIFT (0U) /*! LFREF - Low Frequency Reference Threshold */ #define NOC_CMU_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_LTCR_LFREF_SHIFT)) & NOC_CMU_LTCR_LFREF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define NOC_CMU_SR_FLL_MASK (0x1U) #define NOC_CMU_SR_FLL_SHIFT (0U) /*! FLL - Frequency lower than low frequency reference threshold event status * 0b0..No FLL event * 0b1..FLL event occurred */ #define NOC_CMU_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_SR_FLL_SHIFT)) & NOC_CMU_SR_FLL_MASK) #define NOC_CMU_SR_FHH_MASK (0x2U) #define NOC_CMU_SR_FHH_SHIFT (1U) /*! FHH - Frequency higher than high frequency reference threshold event status * 0b0..No FHH event * 0b1..FHH event occurred */ #define NOC_CMU_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_SR_FHH_SHIFT)) & NOC_CMU_SR_FHH_MASK) #define NOC_CMU_SR_RS_MASK (0x10U) #define NOC_CMU_SR_RS_SHIFT (4U) /*! RS - Run Status * 0b0..Frequency check stopped * 0b1..Frequency check running */ #define NOC_CMU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_SR_RS_SHIFT)) & NOC_CMU_SR_RS_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define NOC_CMU_IER_FLLAIE_MASK (0x4U) #define NOC_CMU_IER_FLLAIE_SHIFT (2U) /*! FLLAIE - Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FLL event interrupt disabled * 0b1..Asynchronous FLL event interrupt enabled */ #define NOC_CMU_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_IER_FLLAIE_SHIFT)) & NOC_CMU_IER_FLLAIE_MASK) #define NOC_CMU_IER_FHHAIE_MASK (0x8U) #define NOC_CMU_IER_FHHAIE_SHIFT (3U) /*! FHHAIE - Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FHH event interrupt disabled * 0b1..Asynchronous FHH event interrupt enabled */ #define NOC_CMU_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << NOC_CMU_IER_FHHAIE_SHIFT)) & NOC_CMU_IER_FHHAIE_MASK) /*! @} */ /*! * @} */ /* end of group NOC_CMU_Register_Masks */ /* NOC_CMU - Peripheral instance base addresses */ /** Peripheral NOC__CMU_N0 base address */ #define NOC__CMU_N0_BASE (0x49070000u) /** Peripheral NOC__CMU_N0 base pointer */ #define NOC__CMU_N0 ((NOC_CMU_Type *)NOC__CMU_N0_BASE) /** Peripheral NOC__CMU_N1 base address */ #define NOC__CMU_N1_BASE (0x49080000u) /** Peripheral NOC__CMU_N1 base pointer */ #define NOC__CMU_N1 ((NOC_CMU_Type *)NOC__CMU_N1_BASE) /** Array initializer of NOC_CMU peripheral base addresses */ #define NOC_CMU_BASE_ADDRS { NOC__CMU_N0_BASE, NOC__CMU_N1_BASE } /** Array initializer of NOC_CMU peripheral base pointers */ #define NOC_CMU_BASE_PTRS { NOC__CMU_N0, NOC__CMU_N1 } /*! * @} */ /* end of group NOC_CMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_EIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_EIM_Peripheral_Access_Layer NOC_EIM Peripheral Access Layer * @{ */ /** NOC_EIM - Register Layout Typedef */ typedef struct { __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ uint8_t RESERVED_0[252]; __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ } NOC_EIM_Type; /* ---------------------------------------------------------------------------- -- NOC_EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_EIM_Register_Masks NOC_EIM Register Masks * @{ */ /*! @name EIMCR - Error Injection Module Configuration Register */ /*! @{ */ #define NOC_EIM_EIMCR_GEIEN_MASK (0x1U) #define NOC_EIM_EIMCR_GEIEN_SHIFT (0U) /*! GEIEN - Global Error Injection Enable * 0b0..Disabled * 0b1..Enabled */ #define NOC_EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_EIM_EIMCR_GEIEN_SHIFT)) & NOC_EIM_EIMCR_GEIEN_MASK) /*! @} */ /*! @name EICHEN - Error Injection Channel Enable register */ /*! @{ */ #define NOC_EIM_EICHEN_EICH0EN_MASK (0x80000000U) #define NOC_EIM_EICHEN_EICH0EN_SHIFT (31U) /*! EICH0EN - Error Injection Channel 0 Enable * 0b0..Error injection is disabled on Error Injection Channel 0 * 0b1..Error injection is enabled on Error Injection Channel 0 */ #define NOC_EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_EIM_EICHEN_EICH0EN_SHIFT)) & NOC_EIM_EICHEN_EICH0EN_MASK) /*! @} */ /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ /*! @{ */ #define NOC_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0x1FU) #define NOC_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define NOC_EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & NOC_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_EIM_Register_Masks */ /* NOC_EIM - Peripheral instance base addresses */ /** Peripheral NOC__EIMN base address */ #define NOC__EIMN_BASE (0x49270000u) /** Peripheral NOC__EIMN base pointer */ #define NOC__EIMN ((NOC_EIM_Type *)NOC__EIMN_BASE) /** Array initializer of NOC_EIM peripheral base addresses */ #define NOC_EIM_BASE_ADDRS { NOC__EIMN_BASE } /** Array initializer of NOC_EIM peripheral base pointers */ #define NOC_EIM_BASE_PTRS { NOC__EIMN } /*! * @} */ /* end of group NOC_EIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICA_Peripheral_Access_Layer NOC_GICA Peripheral Access Layer * @{ */ /** NOC_GICA - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __I uint64_t GICA_TYPER; /**< GICA_TYPER, offset: 0x8 */ uint8_t RESERVED_1[48]; __O uint32_t GICA_SETSPI_NSR; /**< GICA_SETSPI_NSR, offset: 0x40 */ uint8_t RESERVED_2[4]; __O uint32_t GICA_CLRSPI_NSR; /**< GICA_CLRSPI_NSR, offset: 0x48 */ uint8_t RESERVED_3[4]; __O uint32_t GICA_SETSPI_SR; /**< GICA_SETSPI_SR, offset: 0x50 */ uint8_t RESERVED_4[4]; __O uint32_t GICA_CLRSPI_SR; /**< GICA_CLRSPI_SR, offset: 0x58 */ uint8_t RESERVED_5[3952]; __I uint32_t GICA_IIDR; /**< GICA_IIDR, offset: 0xFCC */ uint8_t RESERVED_6[61440]; __I uint32_t GICA_PIDR4; /**< GICA_PIDR4, offset: 0xFFD0 */ __I uint32_t GICA_PIDR5; /**< GICA_PIDR5, offset: 0xFFD4 */ __I uint32_t GICA_PIDR6; /**< GICA_PIDR6, offset: 0xFFD8 */ __I uint32_t GICA_PIDR7; /**< GICA_PIDR7, offset: 0xFFDC */ __I uint32_t GICA_PIDR0; /**< GICA_PIDR0, offset: 0xFFE0 */ __I uint32_t GICA_PIDR1; /**< GICA_PIDR1, offset: 0xFFE4 */ __I uint32_t GICA_PIDR2; /**< GICA_PIDR2, offset: 0xFFE8 */ __I uint32_t GICA_PIDR3; /**< GICA_PIDR3, offset: 0xFFEC */ __I uint32_t GICA_CIDR0; /**< GICA_CIDR0, offset: 0xFFF0 */ __I uint32_t GICA_CIDR1; /**< GICA_CIDR1, offset: 0xFFF4 */ __I uint32_t GICA_CIDR2; /**< GICA_CIDR2, offset: 0xFFF8 */ __I uint32_t GICA_CIDR3; /**< GICA_CIDR3, offset: 0xFFFC */ } NOC_GICA_Type; /* ---------------------------------------------------------------------------- -- NOC_GICA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICA_Register_Masks NOC_GICA Register Masks * @{ */ /*! @name GICA_TYPER - GICA_TYPER */ /*! @{ */ #define NOC_GICA_GICA_TYPER_NumSPIs_MASK (0x7FFU) #define NOC_GICA_GICA_TYPER_NumSPIs_SHIFT (0U) /*! NumSPIs - NumSPIs */ #define NOC_GICA_GICA_TYPER_NumSPIs(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICA_GICA_TYPER_NumSPIs_SHIFT)) & NOC_GICA_GICA_TYPER_NumSPIs_MASK) #define NOC_GICA_GICA_TYPER_RESERVED0_MASK (0xF800U) #define NOC_GICA_GICA_TYPER_RESERVED0_SHIFT (11U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_TYPER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICA_GICA_TYPER_RESERVED0_SHIFT)) & NOC_GICA_GICA_TYPER_RESERVED0_MASK) #define NOC_GICA_GICA_TYPER_INTID_MASK (0x1FFF0000U) #define NOC_GICA_GICA_TYPER_INTID_SHIFT (16U) /*! INTID - INTID */ #define NOC_GICA_GICA_TYPER_INTID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICA_GICA_TYPER_INTID_SHIFT)) & NOC_GICA_GICA_TYPER_INTID_MASK) #define NOC_GICA_GICA_TYPER_SR_MASK (0x20000000U) #define NOC_GICA_GICA_TYPER_SR_SHIFT (29U) /*! SR - SR */ #define NOC_GICA_GICA_TYPER_SR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICA_GICA_TYPER_SR_SHIFT)) & NOC_GICA_GICA_TYPER_SR_MASK) #define NOC_GICA_GICA_TYPER_CLR_MASK (0x40000000U) #define NOC_GICA_GICA_TYPER_CLR_SHIFT (30U) /*! CLR - CLR */ #define NOC_GICA_GICA_TYPER_CLR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICA_GICA_TYPER_CLR_SHIFT)) & NOC_GICA_GICA_TYPER_CLR_MASK) #define NOC_GICA_GICA_TYPER_Valid_MASK (0x80000000U) #define NOC_GICA_GICA_TYPER_Valid_SHIFT (31U) /*! Valid - Valid */ #define NOC_GICA_GICA_TYPER_Valid(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICA_GICA_TYPER_Valid_SHIFT)) & NOC_GICA_GICA_TYPER_Valid_MASK) #define NOC_GICA_GICA_TYPER_RESERVED1_MASK (0xFFFFFFFF00000000U) #define NOC_GICA_GICA_TYPER_RESERVED1_SHIFT (32U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICA_GICA_TYPER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICA_GICA_TYPER_RESERVED1_SHIFT)) & NOC_GICA_GICA_TYPER_RESERVED1_MASK) /*! @} */ /*! @name GICA_SETSPI_NSR - GICA_SETSPI_NSR */ /*! @{ */ #define NOC_GICA_GICA_SETSPI_NSR_ID_MASK (0xFFFFU) #define NOC_GICA_GICA_SETSPI_NSR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICA_GICA_SETSPI_NSR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_SETSPI_NSR_ID_SHIFT)) & NOC_GICA_GICA_SETSPI_NSR_ID_MASK) #define NOC_GICA_GICA_SETSPI_NSR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICA_GICA_SETSPI_NSR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_SETSPI_NSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_SETSPI_NSR_RESERVED0_SHIFT)) & NOC_GICA_GICA_SETSPI_NSR_RESERVED0_MASK) /*! @} */ /*! @name GICA_CLRSPI_NSR - GICA_CLRSPI_NSR */ /*! @{ */ #define NOC_GICA_GICA_CLRSPI_NSR_ID_MASK (0xFFFFU) #define NOC_GICA_GICA_CLRSPI_NSR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICA_GICA_CLRSPI_NSR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CLRSPI_NSR_ID_SHIFT)) & NOC_GICA_GICA_CLRSPI_NSR_ID_MASK) #define NOC_GICA_GICA_CLRSPI_NSR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICA_GICA_CLRSPI_NSR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_CLRSPI_NSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CLRSPI_NSR_RESERVED0_SHIFT)) & NOC_GICA_GICA_CLRSPI_NSR_RESERVED0_MASK) /*! @} */ /*! @name GICA_SETSPI_SR - GICA_SETSPI_SR */ /*! @{ */ #define NOC_GICA_GICA_SETSPI_SR_ID_MASK (0xFFFFU) #define NOC_GICA_GICA_SETSPI_SR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICA_GICA_SETSPI_SR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_SETSPI_SR_ID_SHIFT)) & NOC_GICA_GICA_SETSPI_SR_ID_MASK) #define NOC_GICA_GICA_SETSPI_SR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICA_GICA_SETSPI_SR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_SETSPI_SR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_SETSPI_SR_RESERVED0_SHIFT)) & NOC_GICA_GICA_SETSPI_SR_RESERVED0_MASK) /*! @} */ /*! @name GICA_CLRSPI_SR - GICA_CLRSPI_SR */ /*! @{ */ #define NOC_GICA_GICA_CLRSPI_SR_ID_MASK (0xFFFFU) #define NOC_GICA_GICA_CLRSPI_SR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICA_GICA_CLRSPI_SR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CLRSPI_SR_ID_SHIFT)) & NOC_GICA_GICA_CLRSPI_SR_ID_MASK) #define NOC_GICA_GICA_CLRSPI_SR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICA_GICA_CLRSPI_SR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_CLRSPI_SR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CLRSPI_SR_RESERVED0_SHIFT)) & NOC_GICA_GICA_CLRSPI_SR_RESERVED0_MASK) /*! @} */ /*! @name GICA_IIDR - GICA_IIDR */ /*! @{ */ #define NOC_GICA_GICA_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICA_GICA_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICA_GICA_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_IIDR_Implementer_SHIFT)) & NOC_GICA_GICA_IIDR_Implementer_MASK) #define NOC_GICA_GICA_IIDR_Revision_MASK (0xF000U) #define NOC_GICA_GICA_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICA_GICA_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_IIDR_Revision_SHIFT)) & NOC_GICA_GICA_IIDR_Revision_MASK) #define NOC_GICA_GICA_IIDR_Variant_MASK (0xF0000U) #define NOC_GICA_GICA_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICA_GICA_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_IIDR_Variant_SHIFT)) & NOC_GICA_GICA_IIDR_Variant_MASK) #define NOC_GICA_GICA_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICA_GICA_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_IIDR_RESERVED0_SHIFT)) & NOC_GICA_GICA_IIDR_RESERVED0_MASK) #define NOC_GICA_GICA_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICA_GICA_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICA_GICA_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_IIDR_ProductID_SHIFT)) & NOC_GICA_GICA_IIDR_ProductID_MASK) /*! @} */ /*! @name GICA_PIDR4 - GICA_PIDR4 */ /*! @{ */ #define NOC_GICA_GICA_PIDR4_DES_2_MASK (0xFU) #define NOC_GICA_GICA_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICA_GICA_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR4_DES_2_SHIFT)) & NOC_GICA_GICA_PIDR4_DES_2_MASK) #define NOC_GICA_GICA_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICA_GICA_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICA_GICA_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR4_SIZE_SHIFT)) & NOC_GICA_GICA_PIDR4_SIZE_MASK) #define NOC_GICA_GICA_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR4_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICA_PIDR5 - GICA_PIDR5 */ /*! @{ */ #define NOC_GICA_GICA_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICA_GICA_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICA_GICA_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR5_RESERVED_SHIFT)) & NOC_GICA_GICA_PIDR5_RESERVED_MASK) #define NOC_GICA_GICA_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR5_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICA_PIDR6 - GICA_PIDR6 */ /*! @{ */ #define NOC_GICA_GICA_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICA_GICA_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICA_GICA_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR6_RESERVED_SHIFT)) & NOC_GICA_GICA_PIDR6_RESERVED_MASK) #define NOC_GICA_GICA_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR6_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICA_PIDR7 - GICA_PIDR7 */ /*! @{ */ #define NOC_GICA_GICA_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICA_GICA_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICA_GICA_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR7_RESERVED_SHIFT)) & NOC_GICA_GICA_PIDR7_RESERVED_MASK) #define NOC_GICA_GICA_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR7_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICA_PIDR0 - GICA_PIDR0 */ /*! @{ */ #define NOC_GICA_GICA_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICA_GICA_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICA_GICA_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR0_PART_0_SHIFT)) & NOC_GICA_GICA_PIDR0_PART_0_MASK) #define NOC_GICA_GICA_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR0_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICA_PIDR1 - GICA_PIDR1 */ /*! @{ */ #define NOC_GICA_GICA_PIDR1_PART_1_MASK (0xFU) #define NOC_GICA_GICA_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICA_GICA_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR1_PART_1_SHIFT)) & NOC_GICA_GICA_PIDR1_PART_1_MASK) #define NOC_GICA_GICA_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICA_GICA_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICA_GICA_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR1_DES_0_SHIFT)) & NOC_GICA_GICA_PIDR1_DES_0_MASK) #define NOC_GICA_GICA_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR1_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICA_PIDR2 - GICA_PIDR2 */ /*! @{ */ #define NOC_GICA_GICA_PIDR2_DES_1_MASK (0x7U) #define NOC_GICA_GICA_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICA_GICA_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR2_DES_1_SHIFT)) & NOC_GICA_GICA_PIDR2_DES_1_MASK) #define NOC_GICA_GICA_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICA_GICA_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICA_GICA_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR2_JEDEC_SHIFT)) & NOC_GICA_GICA_PIDR2_JEDEC_MASK) #define NOC_GICA_GICA_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICA_GICA_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICA_GICA_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR2_REVISION_SHIFT)) & NOC_GICA_GICA_PIDR2_REVISION_MASK) #define NOC_GICA_GICA_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR2_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICA_PIDR3 - GICA_PIDR3 */ /*! @{ */ #define NOC_GICA_GICA_PIDR3_CMOD_MASK (0x7U) #define NOC_GICA_GICA_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICA_GICA_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR3_CMOD_SHIFT)) & NOC_GICA_GICA_PIDR3_CMOD_MASK) #define NOC_GICA_GICA_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICA_GICA_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR3_RESERVED0_SHIFT)) & NOC_GICA_GICA_PIDR3_RESERVED0_MASK) #define NOC_GICA_GICA_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICA_GICA_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICA_GICA_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR3_REVAND_SHIFT)) & NOC_GICA_GICA_PIDR3_REVAND_MASK) #define NOC_GICA_GICA_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICA_GICA_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_PIDR3_RESERVED1_SHIFT)) & NOC_GICA_GICA_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICA_CIDR0 - GICA_CIDR0 */ /*! @{ */ #define NOC_GICA_GICA_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICA_GICA_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICA_GICA_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR0_PRMBL_0_SHIFT)) & NOC_GICA_GICA_CIDR0_PRMBL_0_MASK) #define NOC_GICA_GICA_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR0_RESERVED0_SHIFT)) & NOC_GICA_GICA_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICA_CIDR1 - GICA_CIDR1 */ /*! @{ */ #define NOC_GICA_GICA_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICA_GICA_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICA_GICA_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR1_PRMBL_1_SHIFT)) & NOC_GICA_GICA_CIDR1_PRMBL_1_MASK) #define NOC_GICA_GICA_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICA_GICA_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICA_GICA_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR1_CLASS_SHIFT)) & NOC_GICA_GICA_CIDR1_CLASS_MASK) #define NOC_GICA_GICA_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR1_RESERVED0_SHIFT)) & NOC_GICA_GICA_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICA_CIDR2 - GICA_CIDR2 */ /*! @{ */ #define NOC_GICA_GICA_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICA_GICA_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICA_GICA_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR2_PRMBL_2_SHIFT)) & NOC_GICA_GICA_CIDR2_PRMBL_2_MASK) #define NOC_GICA_GICA_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR2_RESERVED0_SHIFT)) & NOC_GICA_GICA_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICA_CIDR3 - GICA_CIDR3 */ /*! @{ */ #define NOC_GICA_GICA_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICA_GICA_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICA_GICA_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR3_PRMBL_3_SHIFT)) & NOC_GICA_GICA_CIDR3_PRMBL_3_MASK) #define NOC_GICA_GICA_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICA_GICA_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICA_GICA_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICA_GICA_CIDR3_RESERVED0_SHIFT)) & NOC_GICA_GICA_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICA_Register_Masks */ /* NOC_GICA - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICA base address */ #define NOC__GIC__GICA_BASE (0x48010000u) /** Peripheral NOC__GIC__GICA base pointer */ #define NOC__GIC__GICA ((NOC_GICA_Type *)NOC__GIC__GICA_BASE) /** Array initializer of NOC_GICA peripheral base addresses */ #define NOC_GICA_BASE_ADDRS { NOC__GIC__GICA_BASE } /** Array initializer of NOC_GICA peripheral base pointers */ #define NOC_GICA_BASE_PTRS { NOC__GIC__GICA } /*! * @} */ /* end of group NOC_GICA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICD_Peripheral_Access_Layer NOC_GICD Peripheral Access Layer * @{ */ /** NOC_GICD - Register Layout Typedef */ typedef struct { __IO uint32_t GICD_CTLR; /**< GICD_CTLR, offset: 0x0 */ __I uint32_t GICD_TYPER; /**< GICD_TYPER, offset: 0x4 */ __I uint32_t GICD_IIDR; /**< GICD_IIDR, offset: 0x8 */ __I uint32_t GICD_TYPER2; /**< GICD_TYPER2, offset: 0xC */ __I uint32_t GICD_STATUSR; /**< GICD_STATUSR, offset: 0x10 */ uint8_t RESERVED_0[12]; __IO uint32_t GICD_FCTLR; /**< GICD_FCTLR, offset: 0x20 */ __IO uint32_t GICD_SAC; /**< GICD_SAC, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t GICD_FCTLR2; /**< GICD_FCTLR2, offset: 0x30 */ __IO uint32_t GICD_UTILR; /**< GICD_UTILR, offset: 0x34 */ __IO uint32_t GICD_FCTLR3; /**< GICD_FCTLR3, offset: 0x38 */ uint8_t RESERVED_2[4]; __O uint32_t GICD_SETSPI_NSR; /**< GICD_SETSPI_NSR, offset: 0x40 */ uint8_t RESERVED_3[4]; __O uint32_t GICD_CLRSPI_NSR; /**< GICD_CLRSPI_NSR, offset: 0x48 */ uint8_t RESERVED_4[4]; __O uint32_t GICD_SETSPI_SR; /**< GICD_SETSPI_SR, offset: 0x50 */ uint8_t RESERVED_5[4]; __O uint32_t GICD_CLRSPI_SR; /**< GICD_CLRSPI_SR, offset: 0x58 */ uint8_t RESERVED_6[40]; __IO uint32_t GICD_IGROUPR1; /**< GICD_IGROUPR1, offset: 0x84 */ __IO uint32_t GICD_IGROUPR2; /**< GICD_IGROUPR2, offset: 0x88 */ __IO uint32_t GICD_IGROUPR3; /**< GICD_IGROUPR3, offset: 0x8C */ __IO uint32_t GICD_IGROUPR4; /**< GICD_IGROUPR4, offset: 0x90 */ __IO uint32_t GICD_IGROUPR5; /**< GICD_IGROUPR5, offset: 0x94 */ __IO uint32_t GICD_IGROUPR6; /**< GICD_IGROUPR6, offset: 0x98 */ __IO uint32_t GICD_IGROUPR7; /**< GICD_IGROUPR7, offset: 0x9C */ __IO uint32_t GICD_IGROUPR8; /**< GICD_IGROUPR8, offset: 0xA0 */ __IO uint32_t GICD_IGROUPR9; /**< GICD_IGROUPR9, offset: 0xA4 */ __IO uint32_t GICD_IGROUPR10; /**< GICD_IGROUPR10, offset: 0xA8 */ __IO uint32_t GICD_IGROUPR11; /**< GICD_IGROUPR11, offset: 0xAC */ __IO uint32_t GICD_IGROUPR12; /**< GICD_IGROUPR12, offset: 0xB0 */ uint8_t RESERVED_7[80]; __IO uint32_t GICD_ISENABLER1; /**< GICD_ISENABLER1, offset: 0x104 */ __IO uint32_t GICD_ISENABLER2; /**< GICD_ISENABLER2, offset: 0x108 */ __IO uint32_t GICD_ISENABLER3; /**< GICD_ISENABLER3, offset: 0x10C */ __IO uint32_t GICD_ISENABLER4; /**< GICD_ISENABLER4, offset: 0x110 */ __IO uint32_t GICD_ISENABLER5; /**< GICD_ISENABLER5, offset: 0x114 */ __IO uint32_t GICD_ISENABLER6; /**< GICD_ISENABLER6, offset: 0x118 */ __IO uint32_t GICD_ISENABLER7; /**< GICD_ISENABLER7, offset: 0x11C */ __IO uint32_t GICD_ISENABLER8; /**< GICD_ISENABLER8, offset: 0x120 */ __IO uint32_t GICD_ISENABLER9; /**< GICD_ISENABLER9, offset: 0x124 */ __IO uint32_t GICD_ISENABLER10; /**< GICD_ISENABLER10, offset: 0x128 */ __IO uint32_t GICD_ISENABLER11; /**< GICD_ISENABLER11, offset: 0x12C */ __IO uint32_t GICD_ISENABLER12; /**< GICD_ISENABLER12, offset: 0x130 */ uint8_t RESERVED_8[80]; __IO uint32_t GICD_ICENABLER1; /**< GICD_ICENABLER1, offset: 0x184 */ __IO uint32_t GICD_ICENABLER2; /**< GICD_ICENABLER2, offset: 0x188 */ __IO uint32_t GICD_ICENABLER3; /**< GICD_ICENABLER3, offset: 0x18C */ __IO uint32_t GICD_ICENABLER4; /**< GICD_ICENABLER4, offset: 0x190 */ __IO uint32_t GICD_ICENABLER5; /**< GICD_ICENABLER5, offset: 0x194 */ __IO uint32_t GICD_ICENABLER6; /**< GICD_ICENABLER6, offset: 0x198 */ __IO uint32_t GICD_ICENABLER7; /**< GICD_ICENABLER7, offset: 0x19C */ __IO uint32_t GICD_ICENABLER8; /**< GICD_ICENABLER8, offset: 0x1A0 */ __IO uint32_t GICD_ICENABLER9; /**< GICD_ICENABLER9, offset: 0x1A4 */ __IO uint32_t GICD_ICENABLER10; /**< GICD_ICENABLER10, offset: 0x1A8 */ __IO uint32_t GICD_ICENABLER11; /**< GICD_ICENABLER11, offset: 0x1AC */ __IO uint32_t GICD_ICENABLER12; /**< GICD_ICENABLER12, offset: 0x1B0 */ uint8_t RESERVED_9[80]; __IO uint32_t GICD_ISPENDR1; /**< GICD_ISPENDR1, offset: 0x204 */ __IO uint32_t GICD_ISPENDR2; /**< GICD_ISPENDR2, offset: 0x208 */ __IO uint32_t GICD_ISPENDR3; /**< GICD_ISPENDR3, offset: 0x20C */ __IO uint32_t GICD_ISPENDR4; /**< GICD_ISPENDR4, offset: 0x210 */ __IO uint32_t GICD_ISPENDR5; /**< GICD_ISPENDR5, offset: 0x214 */ __IO uint32_t GICD_ISPENDR6; /**< GICD_ISPENDR6, offset: 0x218 */ __IO uint32_t GICD_ISPENDR7; /**< GICD_ISPENDR7, offset: 0x21C */ __IO uint32_t GICD_ISPENDR8; /**< GICD_ISPENDR8, offset: 0x220 */ __IO uint32_t GICD_ISPENDR9; /**< GICD_ISPENDR9, offset: 0x224 */ __IO uint32_t GICD_ISPENDR10; /**< GICD_ISPENDR10, offset: 0x228 */ __IO uint32_t GICD_ISPENDR11; /**< GICD_ISPENDR11, offset: 0x22C */ __IO uint32_t GICD_ISPENDR12; /**< GICD_ISPENDR12, offset: 0x230 */ uint8_t RESERVED_10[80]; __IO uint32_t GICD_ICPENDR1; /**< GICD_ICPENDR1, offset: 0x284 */ __IO uint32_t GICD_ICPENDR2; /**< GICD_ICPENDR2, offset: 0x288 */ __IO uint32_t GICD_ICPENDR3; /**< GICD_ICPENDR3, offset: 0x28C */ __IO uint32_t GICD_ICPENDR4; /**< GICD_ICPENDR4, offset: 0x290 */ __IO uint32_t GICD_ICPENDR5; /**< GICD_ICPENDR5, offset: 0x294 */ __IO uint32_t GICD_ICPENDR6; /**< GICD_ICPENDR6, offset: 0x298 */ __IO uint32_t GICD_ICPENDR7; /**< GICD_ICPENDR7, offset: 0x29C */ __IO uint32_t GICD_ICPENDR8; /**< GICD_ICPENDR8, offset: 0x2A0 */ __IO uint32_t GICD_ICPENDR9; /**< GICD_ICPENDR9, offset: 0x2A4 */ __IO uint32_t GICD_ICPENDR10; /**< GICD_ICPENDR10, offset: 0x2A8 */ __IO uint32_t GICD_ICPENDR11; /**< GICD_ICPENDR11, offset: 0x2AC */ __IO uint32_t GICD_ICPENDR12; /**< GICD_ICPENDR12, offset: 0x2B0 */ uint8_t RESERVED_11[80]; __IO uint32_t GICD_ISACTIVER1; /**< GICD_ISACTIVER1, offset: 0x304 */ __IO uint32_t GICD_ISACTIVER2; /**< GICD_ISACTIVER2, offset: 0x308 */ __IO uint32_t GICD_ISACTIVER3; /**< GICD_ISACTIVER3, offset: 0x30C */ __IO uint32_t GICD_ISACTIVER4; /**< GICD_ISACTIVER4, offset: 0x310 */ __IO uint32_t GICD_ISACTIVER5; /**< GICD_ISACTIVER5, offset: 0x314 */ __IO uint32_t GICD_ISACTIVER6; /**< GICD_ISACTIVER6, offset: 0x318 */ __IO uint32_t GICD_ISACTIVER7; /**< GICD_ISACTIVER7, offset: 0x31C */ __IO uint32_t GICD_ISACTIVER8; /**< GICD_ISACTIVER8, offset: 0x320 */ __IO uint32_t GICD_ISACTIVER9; /**< GICD_ISACTIVER9, offset: 0x324 */ __IO uint32_t GICD_ISACTIVER10; /**< GICD_ISACTIVER10, offset: 0x328 */ __IO uint32_t GICD_ISACTIVER11; /**< GICD_ISACTIVER11, offset: 0x32C */ __IO uint32_t GICD_ISACTIVER12; /**< GICD_ISACTIVER12, offset: 0x330 */ uint8_t RESERVED_12[80]; __IO uint32_t GICD_ICACTIVER1; /**< GICD_ICACTIVER1, offset: 0x384 */ __IO uint32_t GICD_ICACTIVER2; /**< GICD_ICACTIVER2, offset: 0x388 */ __IO uint32_t GICD_ICACTIVER3; /**< GICD_ICACTIVER3, offset: 0x38C */ __IO uint32_t GICD_ICACTIVER4; /**< GICD_ICACTIVER4, offset: 0x390 */ __IO uint32_t GICD_ICACTIVER5; /**< GICD_ICACTIVER5, offset: 0x394 */ __IO uint32_t GICD_ICACTIVER6; /**< GICD_ICACTIVER6, offset: 0x398 */ __IO uint32_t GICD_ICACTIVER7; /**< GICD_ICACTIVER7, offset: 0x39C */ __IO uint32_t GICD_ICACTIVER8; /**< GICD_ICACTIVER8, offset: 0x3A0 */ __IO uint32_t GICD_ICACTIVER9; /**< GICD_ICACTIVER9, offset: 0x3A4 */ __IO uint32_t GICD_ICACTIVER10; /**< GICD_ICACTIVER10, offset: 0x3A8 */ __IO uint32_t GICD_ICACTIVER11; /**< GICD_ICACTIVER11, offset: 0x3AC */ __IO uint32_t GICD_ICACTIVER12; /**< GICD_ICACTIVER12, offset: 0x3B0 */ uint8_t RESERVED_13[108]; __IO uint32_t GICD_IPRIORITYR8; /**< GICD_IPRIORITYR8, offset: 0x420 */ __IO uint32_t GICD_IPRIORITYR9; /**< GICD_IPRIORITYR9, offset: 0x424 */ __IO uint32_t GICD_IPRIORITYR10; /**< GICD_IPRIORITYR10, offset: 0x428 */ __IO uint32_t GICD_IPRIORITYR11; /**< GICD_IPRIORITYR11, offset: 0x42C */ __IO uint32_t GICD_IPRIORITYR12; /**< GICD_IPRIORITYR12, offset: 0x430 */ __IO uint32_t GICD_IPRIORITYR13; /**< GICD_IPRIORITYR13, offset: 0x434 */ __IO uint32_t GICD_IPRIORITYR14; /**< GICD_IPRIORITYR14, offset: 0x438 */ __IO uint32_t GICD_IPRIORITYR15; /**< GICD_IPRIORITYR15, offset: 0x43C */ __IO uint32_t GICD_IPRIORITYR16; /**< GICD_IPRIORITYR16, offset: 0x440 */ __IO uint32_t GICD_IPRIORITYR17; /**< GICD_IPRIORITYR17, offset: 0x444 */ __IO uint32_t GICD_IPRIORITYR18; /**< GICD_IPRIORITYR18, offset: 0x448 */ __IO uint32_t GICD_IPRIORITYR19; /**< GICD_IPRIORITYR19, offset: 0x44C */ __IO uint32_t GICD_IPRIORITYR20; /**< GICD_IPRIORITYR20, offset: 0x450 */ __IO uint32_t GICD_IPRIORITYR21; /**< GICD_IPRIORITYR21, offset: 0x454 */ __IO uint32_t GICD_IPRIORITYR22; /**< GICD_IPRIORITYR22, offset: 0x458 */ __IO uint32_t GICD_IPRIORITYR23; /**< GICD_IPRIORITYR23, offset: 0x45C */ __IO uint32_t GICD_IPRIORITYR24; /**< GICD_IPRIORITYR24, offset: 0x460 */ __IO uint32_t GICD_IPRIORITYR25; /**< GICD_IPRIORITYR25, offset: 0x464 */ __IO uint32_t GICD_IPRIORITYR26; /**< GICD_IPRIORITYR26, offset: 0x468 */ __IO uint32_t GICD_IPRIORITYR27; /**< GICD_IPRIORITYR27, offset: 0x46C */ __IO uint32_t GICD_IPRIORITYR28; /**< GICD_IPRIORITYR28, offset: 0x470 */ __IO uint32_t GICD_IPRIORITYR29; /**< GICD_IPRIORITYR29, offset: 0x474 */ __IO uint32_t GICD_IPRIORITYR30; /**< GICD_IPRIORITYR30, offset: 0x478 */ __IO uint32_t GICD_IPRIORITYR31; /**< GICD_IPRIORITYR31, offset: 0x47C */ __IO uint32_t GICD_IPRIORITYR32; /**< GICD_IPRIORITYR32, offset: 0x480 */ __IO uint32_t GICD_IPRIORITYR33; /**< GICD_IPRIORITYR33, offset: 0x484 */ __IO uint32_t GICD_IPRIORITYR34; /**< GICD_IPRIORITYR34, offset: 0x488 */ __IO uint32_t GICD_IPRIORITYR35; /**< GICD_IPRIORITYR35, offset: 0x48C */ __IO uint32_t GICD_IPRIORITYR36; /**< GICD_IPRIORITYR36, offset: 0x490 */ __IO uint32_t GICD_IPRIORITYR37; /**< GICD_IPRIORITYR37, offset: 0x494 */ __IO uint32_t GICD_IPRIORITYR38; /**< GICD_IPRIORITYR38, offset: 0x498 */ __IO uint32_t GICD_IPRIORITYR39; /**< GICD_IPRIORITYR39, offset: 0x49C */ __IO uint32_t GICD_IPRIORITYR40; /**< GICD_IPRIORITYR40, offset: 0x4A0 */ __IO uint32_t GICD_IPRIORITYR41; /**< GICD_IPRIORITYR41, offset: 0x4A4 */ __IO uint32_t GICD_IPRIORITYR42; /**< GICD_IPRIORITYR42, offset: 0x4A8 */ __IO uint32_t GICD_IPRIORITYR43; /**< GICD_IPRIORITYR43, offset: 0x4AC */ __IO uint32_t GICD_IPRIORITYR44; /**< GICD_IPRIORITYR44, offset: 0x4B0 */ __IO uint32_t GICD_IPRIORITYR45; /**< GICD_IPRIORITYR45, offset: 0x4B4 */ __IO uint32_t GICD_IPRIORITYR46; /**< GICD_IPRIORITYR46, offset: 0x4B8 */ __IO uint32_t GICD_IPRIORITYR47; /**< GICD_IPRIORITYR47, offset: 0x4BC */ __IO uint32_t GICD_IPRIORITYR48; /**< GICD_IPRIORITYR48, offset: 0x4C0 */ __IO uint32_t GICD_IPRIORITYR49; /**< GICD_IPRIORITYR49, offset: 0x4C4 */ __IO uint32_t GICD_IPRIORITYR50; /**< GICD_IPRIORITYR50, offset: 0x4C8 */ __IO uint32_t GICD_IPRIORITYR51; /**< GICD_IPRIORITYR51, offset: 0x4CC */ __IO uint32_t GICD_IPRIORITYR52; /**< GICD_IPRIORITYR52, offset: 0x4D0 */ __IO uint32_t GICD_IPRIORITYR53; /**< GICD_IPRIORITYR53, offset: 0x4D4 */ __IO uint32_t GICD_IPRIORITYR54; /**< GICD_IPRIORITYR54, offset: 0x4D8 */ __IO uint32_t GICD_IPRIORITYR55; /**< GICD_IPRIORITYR55, offset: 0x4DC */ __IO uint32_t GICD_IPRIORITYR56; /**< GICD_IPRIORITYR56, offset: 0x4E0 */ __IO uint32_t GICD_IPRIORITYR57; /**< GICD_IPRIORITYR57, offset: 0x4E4 */ __IO uint32_t GICD_IPRIORITYR58; /**< GICD_IPRIORITYR58, offset: 0x4E8 */ __IO uint32_t GICD_IPRIORITYR59; /**< GICD_IPRIORITYR59, offset: 0x4EC */ __IO uint32_t GICD_IPRIORITYR60; /**< GICD_IPRIORITYR60, offset: 0x4F0 */ __IO uint32_t GICD_IPRIORITYR61; /**< GICD_IPRIORITYR61, offset: 0x4F4 */ __IO uint32_t GICD_IPRIORITYR62; /**< GICD_IPRIORITYR62, offset: 0x4F8 */ __IO uint32_t GICD_IPRIORITYR63; /**< GICD_IPRIORITYR63, offset: 0x4FC */ __IO uint32_t GICD_IPRIORITYR64; /**< GICD_IPRIORITYR64, offset: 0x500 */ __IO uint32_t GICD_IPRIORITYR65; /**< GICD_IPRIORITYR65, offset: 0x504 */ __IO uint32_t GICD_IPRIORITYR66; /**< GICD_IPRIORITYR66, offset: 0x508 */ __IO uint32_t GICD_IPRIORITYR67; /**< GICD_IPRIORITYR67, offset: 0x50C */ __IO uint32_t GICD_IPRIORITYR68; /**< GICD_IPRIORITYR68, offset: 0x510 */ __IO uint32_t GICD_IPRIORITYR69; /**< GICD_IPRIORITYR69, offset: 0x514 */ __IO uint32_t GICD_IPRIORITYR70; /**< GICD_IPRIORITYR70, offset: 0x518 */ __IO uint32_t GICD_IPRIORITYR71; /**< GICD_IPRIORITYR71, offset: 0x51C */ __IO uint32_t GICD_IPRIORITYR72; /**< GICD_IPRIORITYR72, offset: 0x520 */ __IO uint32_t GICD_IPRIORITYR73; /**< GICD_IPRIORITYR73, offset: 0x524 */ __IO uint32_t GICD_IPRIORITYR74; /**< GICD_IPRIORITYR74, offset: 0x528 */ __IO uint32_t GICD_IPRIORITYR75; /**< GICD_IPRIORITYR75, offset: 0x52C */ __IO uint32_t GICD_IPRIORITYR76; /**< GICD_IPRIORITYR76, offset: 0x530 */ __IO uint32_t GICD_IPRIORITYR77; /**< GICD_IPRIORITYR77, offset: 0x534 */ __IO uint32_t GICD_IPRIORITYR78; /**< GICD_IPRIORITYR78, offset: 0x538 */ __IO uint32_t GICD_IPRIORITYR79; /**< GICD_IPRIORITYR79, offset: 0x53C */ __IO uint32_t GICD_IPRIORITYR80; /**< GICD_IPRIORITYR80, offset: 0x540 */ __IO uint32_t GICD_IPRIORITYR81; /**< GICD_IPRIORITYR81, offset: 0x544 */ __IO uint32_t GICD_IPRIORITYR82; /**< GICD_IPRIORITYR82, offset: 0x548 */ __IO uint32_t GICD_IPRIORITYR83; /**< GICD_IPRIORITYR83, offset: 0x54C */ __IO uint32_t GICD_IPRIORITYR84; /**< GICD_IPRIORITYR84, offset: 0x550 */ __IO uint32_t GICD_IPRIORITYR85; /**< GICD_IPRIORITYR85, offset: 0x554 */ __IO uint32_t GICD_IPRIORITYR86; /**< GICD_IPRIORITYR86, offset: 0x558 */ __IO uint32_t GICD_IPRIORITYR87; /**< GICD_IPRIORITYR87, offset: 0x55C */ __IO uint32_t GICD_IPRIORITYR88; /**< GICD_IPRIORITYR88, offset: 0x560 */ __IO uint32_t GICD_IPRIORITYR89; /**< GICD_IPRIORITYR89, offset: 0x564 */ __IO uint32_t GICD_IPRIORITYR90; /**< GICD_IPRIORITYR90, offset: 0x568 */ __IO uint32_t GICD_IPRIORITYR91; /**< GICD_IPRIORITYR91, offset: 0x56C */ __IO uint32_t GICD_IPRIORITYR92; /**< GICD_IPRIORITYR92, offset: 0x570 */ __IO uint32_t GICD_IPRIORITYR93; /**< GICD_IPRIORITYR93, offset: 0x574 */ __IO uint32_t GICD_IPRIORITYR94; /**< GICD_IPRIORITYR94, offset: 0x578 */ __IO uint32_t GICD_IPRIORITYR95; /**< GICD_IPRIORITYR95, offset: 0x57C */ __IO uint32_t GICD_IPRIORITYR96; /**< GICD_IPRIORITYR96, offset: 0x580 */ __IO uint32_t GICD_IPRIORITYR97; /**< GICD_IPRIORITYR97, offset: 0x584 */ __IO uint32_t GICD_IPRIORITYR98; /**< GICD_IPRIORITYR98, offset: 0x588 */ __IO uint32_t GICD_IPRIORITYR99; /**< GICD_IPRIORITYR99, offset: 0x58C */ __IO uint32_t GICD_IPRIORITYR100; /**< GICD_IPRIORITYR100, offset: 0x590 */ __IO uint32_t GICD_IPRIORITYR101; /**< GICD_IPRIORITYR101, offset: 0x594 */ __IO uint32_t GICD_IPRIORITYR102; /**< GICD_IPRIORITYR102, offset: 0x598 */ __IO uint32_t GICD_IPRIORITYR103; /**< GICD_IPRIORITYR103, offset: 0x59C */ uint8_t RESERVED_14[1640]; __IO uint32_t GICD_ICFGR2; /**< GICD_ICFGR2, offset: 0xC08 */ __IO uint32_t GICD_ICFGR3; /**< GICD_ICFGR3, offset: 0xC0C */ __IO uint32_t GICD_ICFGR4; /**< GICD_ICFGR4, offset: 0xC10 */ __IO uint32_t GICD_ICFGR5; /**< GICD_ICFGR5, offset: 0xC14 */ __IO uint32_t GICD_ICFGR6; /**< GICD_ICFGR6, offset: 0xC18 */ __IO uint32_t GICD_ICFGR7; /**< GICD_ICFGR7, offset: 0xC1C */ __IO uint32_t GICD_ICFGR8; /**< GICD_ICFGR8, offset: 0xC20 */ __IO uint32_t GICD_ICFGR9; /**< GICD_ICFGR9, offset: 0xC24 */ __IO uint32_t GICD_ICFGR10; /**< GICD_ICFGR10, offset: 0xC28 */ __IO uint32_t GICD_ICFGR11; /**< GICD_ICFGR11, offset: 0xC2C */ __IO uint32_t GICD_ICFGR12; /**< GICD_ICFGR12, offset: 0xC30 */ __IO uint32_t GICD_ICFGR13; /**< GICD_ICFGR13, offset: 0xC34 */ __IO uint32_t GICD_ICFGR14; /**< GICD_ICFGR14, offset: 0xC38 */ __IO uint32_t GICD_ICFGR15; /**< GICD_ICFGR15, offset: 0xC3C */ __IO uint32_t GICD_ICFGR16; /**< GICD_ICFGR16, offset: 0xC40 */ __IO uint32_t GICD_ICFGR17; /**< GICD_ICFGR17, offset: 0xC44 */ __IO uint32_t GICD_ICFGR18; /**< GICD_ICFGR18, offset: 0xC48 */ __IO uint32_t GICD_ICFGR19; /**< GICD_ICFGR19, offset: 0xC4C */ __IO uint32_t GICD_ICFGR20; /**< GICD_ICFGR20, offset: 0xC50 */ __IO uint32_t GICD_ICFGR21; /**< GICD_ICFGR21, offset: 0xC54 */ __IO uint32_t GICD_ICFGR22; /**< GICD_ICFGR22, offset: 0xC58 */ __IO uint32_t GICD_ICFGR23; /**< GICD_ICFGR23, offset: 0xC5C */ __IO uint32_t GICD_ICFGR24; /**< GICD_ICFGR24, offset: 0xC60 */ __IO uint32_t GICD_ICFGR25; /**< GICD_ICFGR25, offset: 0xC64 */ uint8_t RESERVED_15[156]; __IO uint32_t GICD_IGRPMODR1; /**< GICD_IGRPMODR1, offset: 0xD04 */ __IO uint32_t GICD_IGRPMODR2; /**< GICD_IGRPMODR2, offset: 0xD08 */ __IO uint32_t GICD_IGRPMODR3; /**< GICD_IGRPMODR3, offset: 0xD0C */ __IO uint32_t GICD_IGRPMODR4; /**< GICD_IGRPMODR4, offset: 0xD10 */ __IO uint32_t GICD_IGRPMODR5; /**< GICD_IGRPMODR5, offset: 0xD14 */ __IO uint32_t GICD_IGRPMODR6; /**< GICD_IGRPMODR6, offset: 0xD18 */ __IO uint32_t GICD_IGRPMODR7; /**< GICD_IGRPMODR7, offset: 0xD1C */ __IO uint32_t GICD_IGRPMODR8; /**< GICD_IGRPMODR8, offset: 0xD20 */ __IO uint32_t GICD_IGRPMODR9; /**< GICD_IGRPMODR9, offset: 0xD24 */ __IO uint32_t GICD_IGRPMODR10; /**< GICD_IGRPMODR10, offset: 0xD28 */ __IO uint32_t GICD_IGRPMODR11; /**< GICD_IGRPMODR11, offset: 0xD2C */ __IO uint32_t GICD_IGRPMODR12; /**< GICD_IGRPMODR12, offset: 0xD30 */ uint8_t RESERVED_16[212]; __IO uint32_t GICD_NSACR2; /**< GICD_NSACR2, offset: 0xE08 */ __IO uint32_t GICD_NSACR3; /**< GICD_NSACR3, offset: 0xE0C */ __IO uint32_t GICD_NSACR4; /**< GICD_NSACR4, offset: 0xE10 */ __IO uint32_t GICD_NSACR5; /**< GICD_NSACR5, offset: 0xE14 */ __IO uint32_t GICD_NSACR6; /**< GICD_NSACR6, offset: 0xE18 */ __IO uint32_t GICD_NSACR7; /**< GICD_NSACR7, offset: 0xE1C */ __IO uint32_t GICD_NSACR8; /**< GICD_NSACR8, offset: 0xE20 */ __IO uint32_t GICD_NSACR9; /**< GICD_NSACR9, offset: 0xE24 */ __IO uint32_t GICD_NSACR10; /**< GICD_NSACR10, offset: 0xE28 */ __IO uint32_t GICD_NSACR11; /**< GICD_NSACR11, offset: 0xE2C */ __IO uint32_t GICD_NSACR12; /**< GICD_NSACR12, offset: 0xE30 */ __IO uint32_t GICD_NSACR13; /**< GICD_NSACR13, offset: 0xE34 */ __IO uint32_t GICD_NSACR14; /**< GICD_NSACR14, offset: 0xE38 */ __IO uint32_t GICD_NSACR15; /**< GICD_NSACR15, offset: 0xE3C */ __IO uint32_t GICD_NSACR16; /**< GICD_NSACR16, offset: 0xE40 */ __IO uint32_t GICD_NSACR17; /**< GICD_NSACR17, offset: 0xE44 */ __IO uint32_t GICD_NSACR18; /**< GICD_NSACR18, offset: 0xE48 */ __IO uint32_t GICD_NSACR19; /**< GICD_NSACR19, offset: 0xE4C */ __IO uint32_t GICD_NSACR20; /**< GICD_NSACR20, offset: 0xE50 */ __IO uint32_t GICD_NSACR21; /**< GICD_NSACR21, offset: 0xE54 */ __IO uint32_t GICD_NSACR22; /**< GICD_NSACR22, offset: 0xE58 */ __IO uint32_t GICD_NSACR23; /**< GICD_NSACR23, offset: 0xE5C */ __IO uint32_t GICD_NSACR24; /**< GICD_NSACR24, offset: 0xE60 */ __IO uint32_t GICD_NSACR25; /**< GICD_NSACR25, offset: 0xE64 */ uint8_t RESERVED_17[21144]; __IO uint64_t GICD_IROUTER32; /**< GICD_IROUTER32, offset: 0x6100 */ __IO uint64_t GICD_IROUTER33; /**< GICD_IROUTER33, offset: 0x6108 */ __IO uint64_t GICD_IROUTER34; /**< GICD_IROUTER34, offset: 0x6110 */ __IO uint64_t GICD_IROUTER35; /**< GICD_IROUTER35, offset: 0x6118 */ __IO uint64_t GICD_IROUTER36; /**< GICD_IROUTER36, offset: 0x6120 */ __IO uint64_t GICD_IROUTER37; /**< GICD_IROUTER37, offset: 0x6128 */ __IO uint64_t GICD_IROUTER38; /**< GICD_IROUTER38, offset: 0x6130 */ __IO uint64_t GICD_IROUTER39; /**< GICD_IROUTER39, offset: 0x6138 */ __IO uint64_t GICD_IROUTER40; /**< GICD_IROUTER40, offset: 0x6140 */ __IO uint64_t GICD_IROUTER41; /**< GICD_IROUTER41, offset: 0x6148 */ __IO uint64_t GICD_IROUTER42; /**< GICD_IROUTER42, offset: 0x6150 */ __IO uint64_t GICD_IROUTER43; /**< GICD_IROUTER43, offset: 0x6158 */ __IO uint64_t GICD_IROUTER44; /**< GICD_IROUTER44, offset: 0x6160 */ __IO uint64_t GICD_IROUTER45; /**< GICD_IROUTER45, offset: 0x6168 */ __IO uint64_t GICD_IROUTER46; /**< GICD_IROUTER46, offset: 0x6170 */ __IO uint64_t GICD_IROUTER47; /**< GICD_IROUTER47, offset: 0x6178 */ __IO uint64_t GICD_IROUTER48; /**< GICD_IROUTER48, offset: 0x6180 */ __IO uint64_t GICD_IROUTER49; /**< GICD_IROUTER49, offset: 0x6188 */ __IO uint64_t GICD_IROUTER50; /**< GICD_IROUTER50, offset: 0x6190 */ __IO uint64_t GICD_IROUTER51; /**< GICD_IROUTER51, offset: 0x6198 */ __IO uint64_t GICD_IROUTER52; /**< GICD_IROUTER52, offset: 0x61A0 */ __IO uint64_t GICD_IROUTER53; /**< GICD_IROUTER53, offset: 0x61A8 */ __IO uint64_t GICD_IROUTER54; /**< GICD_IROUTER54, offset: 0x61B0 */ __IO uint64_t GICD_IROUTER55; /**< GICD_IROUTER55, offset: 0x61B8 */ __IO uint64_t GICD_IROUTER56; /**< GICD_IROUTER56, offset: 0x61C0 */ __IO uint64_t GICD_IROUTER57; /**< GICD_IROUTER57, offset: 0x61C8 */ __IO uint64_t GICD_IROUTER58; /**< GICD_IROUTER58, offset: 0x61D0 */ __IO uint64_t GICD_IROUTER59; /**< GICD_IROUTER59, offset: 0x61D8 */ __IO uint64_t GICD_IROUTER60; /**< GICD_IROUTER60, offset: 0x61E0 */ __IO uint64_t GICD_IROUTER61; /**< GICD_IROUTER61, offset: 0x61E8 */ __IO uint64_t GICD_IROUTER62; /**< GICD_IROUTER62, offset: 0x61F0 */ __IO uint64_t GICD_IROUTER63; /**< GICD_IROUTER63, offset: 0x61F8 */ __IO uint64_t GICD_IROUTER64; /**< GICD_IROUTER64, offset: 0x6200 */ __IO uint64_t GICD_IROUTER65; /**< GICD_IROUTER65, offset: 0x6208 */ __IO uint64_t GICD_IROUTER66; /**< GICD_IROUTER66, offset: 0x6210 */ __IO uint64_t GICD_IROUTER67; /**< GICD_IROUTER67, offset: 0x6218 */ __IO uint64_t GICD_IROUTER68; /**< GICD_IROUTER68, offset: 0x6220 */ __IO uint64_t GICD_IROUTER69; /**< GICD_IROUTER69, offset: 0x6228 */ __IO uint64_t GICD_IROUTER70; /**< GICD_IROUTER70, offset: 0x6230 */ __IO uint64_t GICD_IROUTER71; /**< GICD_IROUTER71, offset: 0x6238 */ __IO uint64_t GICD_IROUTER72; /**< GICD_IROUTER72, offset: 0x6240 */ __IO uint64_t GICD_IROUTER73; /**< GICD_IROUTER73, offset: 0x6248 */ __IO uint64_t GICD_IROUTER74; /**< GICD_IROUTER74, offset: 0x6250 */ __IO uint64_t GICD_IROUTER75; /**< GICD_IROUTER75, offset: 0x6258 */ __IO uint64_t GICD_IROUTER76; /**< GICD_IROUTER76, offset: 0x6260 */ __IO uint64_t GICD_IROUTER77; /**< GICD_IROUTER77, offset: 0x6268 */ __IO uint64_t GICD_IROUTER78; /**< GICD_IROUTER78, offset: 0x6270 */ __IO uint64_t GICD_IROUTER79; /**< GICD_IROUTER79, offset: 0x6278 */ __IO uint64_t GICD_IROUTER80; /**< GICD_IROUTER80, offset: 0x6280 */ __IO uint64_t GICD_IROUTER81; /**< GICD_IROUTER81, offset: 0x6288 */ __IO uint64_t GICD_IROUTER82; /**< GICD_IROUTER82, offset: 0x6290 */ __IO uint64_t GICD_IROUTER83; /**< GICD_IROUTER83, offset: 0x6298 */ __IO uint64_t GICD_IROUTER84; /**< GICD_IROUTER84, offset: 0x62A0 */ __IO uint64_t GICD_IROUTER85; /**< GICD_IROUTER85, offset: 0x62A8 */ __IO uint64_t GICD_IROUTER86; /**< GICD_IROUTER86, offset: 0x62B0 */ __IO uint64_t GICD_IROUTER87; /**< GICD_IROUTER87, offset: 0x62B8 */ __IO uint64_t GICD_IROUTER88; /**< GICD_IROUTER88, offset: 0x62C0 */ __IO uint64_t GICD_IROUTER89; /**< GICD_IROUTER89, offset: 0x62C8 */ __IO uint64_t GICD_IROUTER90; /**< GICD_IROUTER90, offset: 0x62D0 */ __IO uint64_t GICD_IROUTER91; /**< GICD_IROUTER91, offset: 0x62D8 */ __IO uint64_t GICD_IROUTER92; /**< GICD_IROUTER92, offset: 0x62E0 */ __IO uint64_t GICD_IROUTER93; /**< GICD_IROUTER93, offset: 0x62E8 */ __IO uint64_t GICD_IROUTER94; /**< GICD_IROUTER94, offset: 0x62F0 */ __IO uint64_t GICD_IROUTER95; /**< GICD_IROUTER95, offset: 0x62F8 */ __IO uint64_t GICD_IROUTER96; /**< GICD_IROUTER96, offset: 0x6300 */ __IO uint64_t GICD_IROUTER97; /**< GICD_IROUTER97, offset: 0x6308 */ __IO uint64_t GICD_IROUTER98; /**< GICD_IROUTER98, offset: 0x6310 */ __IO uint64_t GICD_IROUTER99; /**< GICD_IROUTER99, offset: 0x6318 */ __IO uint64_t GICD_IROUTER100; /**< GICD_IROUTER100, offset: 0x6320 */ __IO uint64_t GICD_IROUTER101; /**< GICD_IROUTER101, offset: 0x6328 */ __IO uint64_t GICD_IROUTER102; /**< GICD_IROUTER102, offset: 0x6330 */ __IO uint64_t GICD_IROUTER103; /**< GICD_IROUTER103, offset: 0x6338 */ __IO uint64_t GICD_IROUTER104; /**< GICD_IROUTER104, offset: 0x6340 */ __IO uint64_t GICD_IROUTER105; /**< GICD_IROUTER105, offset: 0x6348 */ __IO uint64_t GICD_IROUTER106; /**< GICD_IROUTER106, offset: 0x6350 */ __IO uint64_t GICD_IROUTER107; /**< GICD_IROUTER107, offset: 0x6358 */ __IO uint64_t GICD_IROUTER108; /**< GICD_IROUTER108, offset: 0x6360 */ __IO uint64_t GICD_IROUTER109; /**< GICD_IROUTER109, offset: 0x6368 */ __IO uint64_t GICD_IROUTER110; /**< GICD_IROUTER110, offset: 0x6370 */ __IO uint64_t GICD_IROUTER111; /**< GICD_IROUTER111, offset: 0x6378 */ __IO uint64_t GICD_IROUTER112; /**< GICD_IROUTER112, offset: 0x6380 */ __IO uint64_t GICD_IROUTER113; /**< GICD_IROUTER113, offset: 0x6388 */ __IO uint64_t GICD_IROUTER114; /**< GICD_IROUTER114, offset: 0x6390 */ __IO uint64_t GICD_IROUTER115; /**< GICD_IROUTER115, offset: 0x6398 */ __IO uint64_t GICD_IROUTER116; /**< GICD_IROUTER116, offset: 0x63A0 */ __IO uint64_t GICD_IROUTER117; /**< GICD_IROUTER117, offset: 0x63A8 */ __IO uint64_t GICD_IROUTER118; /**< GICD_IROUTER118, offset: 0x63B0 */ __IO uint64_t GICD_IROUTER119; /**< GICD_IROUTER119, offset: 0x63B8 */ __IO uint64_t GICD_IROUTER120; /**< GICD_IROUTER120, offset: 0x63C0 */ __IO uint64_t GICD_IROUTER121; /**< GICD_IROUTER121, offset: 0x63C8 */ __IO uint64_t GICD_IROUTER122; /**< GICD_IROUTER122, offset: 0x63D0 */ __IO uint64_t GICD_IROUTER123; /**< GICD_IROUTER123, offset: 0x63D8 */ __IO uint64_t GICD_IROUTER124; /**< GICD_IROUTER124, offset: 0x63E0 */ __IO uint64_t GICD_IROUTER125; /**< GICD_IROUTER125, offset: 0x63E8 */ __IO uint64_t GICD_IROUTER126; /**< GICD_IROUTER126, offset: 0x63F0 */ __IO uint64_t GICD_IROUTER127; /**< GICD_IROUTER127, offset: 0x63F8 */ __IO uint64_t GICD_IROUTER128; /**< GICD_IROUTER128, offset: 0x6400 */ __IO uint64_t GICD_IROUTER129; /**< GICD_IROUTER129, offset: 0x6408 */ __IO uint64_t GICD_IROUTER130; /**< GICD_IROUTER130, offset: 0x6410 */ __IO uint64_t GICD_IROUTER131; /**< GICD_IROUTER131, offset: 0x6418 */ __IO uint64_t GICD_IROUTER132; /**< GICD_IROUTER132, offset: 0x6420 */ __IO uint64_t GICD_IROUTER133; /**< GICD_IROUTER133, offset: 0x6428 */ __IO uint64_t GICD_IROUTER134; /**< GICD_IROUTER134, offset: 0x6430 */ __IO uint64_t GICD_IROUTER135; /**< GICD_IROUTER135, offset: 0x6438 */ __IO uint64_t GICD_IROUTER136; /**< GICD_IROUTER136, offset: 0x6440 */ __IO uint64_t GICD_IROUTER137; /**< GICD_IROUTER137, offset: 0x6448 */ __IO uint64_t GICD_IROUTER138; /**< GICD_IROUTER138, offset: 0x6450 */ __IO uint64_t GICD_IROUTER139; /**< GICD_IROUTER139, offset: 0x6458 */ __IO uint64_t GICD_IROUTER140; /**< GICD_IROUTER140, offset: 0x6460 */ __IO uint64_t GICD_IROUTER141; /**< GICD_IROUTER141, offset: 0x6468 */ __IO uint64_t GICD_IROUTER142; /**< GICD_IROUTER142, offset: 0x6470 */ __IO uint64_t GICD_IROUTER143; /**< GICD_IROUTER143, offset: 0x6478 */ __IO uint64_t GICD_IROUTER144; /**< GICD_IROUTER144, offset: 0x6480 */ __IO uint64_t GICD_IROUTER145; /**< GICD_IROUTER145, offset: 0x6488 */ __IO uint64_t GICD_IROUTER146; /**< GICD_IROUTER146, offset: 0x6490 */ __IO uint64_t GICD_IROUTER147; /**< GICD_IROUTER147, offset: 0x6498 */ __IO uint64_t GICD_IROUTER148; /**< GICD_IROUTER148, offset: 0x64A0 */ __IO uint64_t GICD_IROUTER149; /**< GICD_IROUTER149, offset: 0x64A8 */ __IO uint64_t GICD_IROUTER150; /**< GICD_IROUTER150, offset: 0x64B0 */ __IO uint64_t GICD_IROUTER151; /**< GICD_IROUTER151, offset: 0x64B8 */ __IO uint64_t GICD_IROUTER152; /**< GICD_IROUTER152, offset: 0x64C0 */ __IO uint64_t GICD_IROUTER153; /**< GICD_IROUTER153, offset: 0x64C8 */ __IO uint64_t GICD_IROUTER154; /**< GICD_IROUTER154, offset: 0x64D0 */ __IO uint64_t GICD_IROUTER155; /**< GICD_IROUTER155, offset: 0x64D8 */ __IO uint64_t GICD_IROUTER156; /**< GICD_IROUTER156, offset: 0x64E0 */ __IO uint64_t GICD_IROUTER157; /**< GICD_IROUTER157, offset: 0x64E8 */ __IO uint64_t GICD_IROUTER158; /**< GICD_IROUTER158, offset: 0x64F0 */ __IO uint64_t GICD_IROUTER159; /**< GICD_IROUTER159, offset: 0x64F8 */ __IO uint64_t GICD_IROUTER160; /**< GICD_IROUTER160, offset: 0x6500 */ __IO uint64_t GICD_IROUTER161; /**< GICD_IROUTER161, offset: 0x6508 */ __IO uint64_t GICD_IROUTER162; /**< GICD_IROUTER162, offset: 0x6510 */ __IO uint64_t GICD_IROUTER163; /**< GICD_IROUTER163, offset: 0x6518 */ __IO uint64_t GICD_IROUTER164; /**< GICD_IROUTER164, offset: 0x6520 */ __IO uint64_t GICD_IROUTER165; /**< GICD_IROUTER165, offset: 0x6528 */ __IO uint64_t GICD_IROUTER166; /**< GICD_IROUTER166, offset: 0x6530 */ __IO uint64_t GICD_IROUTER167; /**< GICD_IROUTER167, offset: 0x6538 */ __IO uint64_t GICD_IROUTER168; /**< GICD_IROUTER168, offset: 0x6540 */ __IO uint64_t GICD_IROUTER169; /**< GICD_IROUTER169, offset: 0x6548 */ __IO uint64_t GICD_IROUTER170; /**< GICD_IROUTER170, offset: 0x6550 */ __IO uint64_t GICD_IROUTER171; /**< GICD_IROUTER171, offset: 0x6558 */ __IO uint64_t GICD_IROUTER172; /**< GICD_IROUTER172, offset: 0x6560 */ __IO uint64_t GICD_IROUTER173; /**< GICD_IROUTER173, offset: 0x6568 */ __IO uint64_t GICD_IROUTER174; /**< GICD_IROUTER174, offset: 0x6570 */ __IO uint64_t GICD_IROUTER175; /**< GICD_IROUTER175, offset: 0x6578 */ __IO uint64_t GICD_IROUTER176; /**< GICD_IROUTER176, offset: 0x6580 */ __IO uint64_t GICD_IROUTER177; /**< GICD_IROUTER177, offset: 0x6588 */ __IO uint64_t GICD_IROUTER178; /**< GICD_IROUTER178, offset: 0x6590 */ __IO uint64_t GICD_IROUTER179; /**< GICD_IROUTER179, offset: 0x6598 */ __IO uint64_t GICD_IROUTER180; /**< GICD_IROUTER180, offset: 0x65A0 */ __IO uint64_t GICD_IROUTER181; /**< GICD_IROUTER181, offset: 0x65A8 */ __IO uint64_t GICD_IROUTER182; /**< GICD_IROUTER182, offset: 0x65B0 */ __IO uint64_t GICD_IROUTER183; /**< GICD_IROUTER183, offset: 0x65B8 */ __IO uint64_t GICD_IROUTER184; /**< GICD_IROUTER184, offset: 0x65C0 */ __IO uint64_t GICD_IROUTER185; /**< GICD_IROUTER185, offset: 0x65C8 */ __IO uint64_t GICD_IROUTER186; /**< GICD_IROUTER186, offset: 0x65D0 */ __IO uint64_t GICD_IROUTER187; /**< GICD_IROUTER187, offset: 0x65D8 */ __IO uint64_t GICD_IROUTER188; /**< GICD_IROUTER188, offset: 0x65E0 */ __IO uint64_t GICD_IROUTER189; /**< GICD_IROUTER189, offset: 0x65E8 */ __IO uint64_t GICD_IROUTER190; /**< GICD_IROUTER190, offset: 0x65F0 */ __IO uint64_t GICD_IROUTER191; /**< GICD_IROUTER191, offset: 0x65F8 */ __IO uint64_t GICD_IROUTER192; /**< GICD_IROUTER192, offset: 0x6600 */ __IO uint64_t GICD_IROUTER193; /**< GICD_IROUTER193, offset: 0x6608 */ __IO uint64_t GICD_IROUTER194; /**< GICD_IROUTER194, offset: 0x6610 */ __IO uint64_t GICD_IROUTER195; /**< GICD_IROUTER195, offset: 0x6618 */ __IO uint64_t GICD_IROUTER196; /**< GICD_IROUTER196, offset: 0x6620 */ __IO uint64_t GICD_IROUTER197; /**< GICD_IROUTER197, offset: 0x6628 */ __IO uint64_t GICD_IROUTER198; /**< GICD_IROUTER198, offset: 0x6630 */ __IO uint64_t GICD_IROUTER199; /**< GICD_IROUTER199, offset: 0x6638 */ __IO uint64_t GICD_IROUTER200; /**< GICD_IROUTER200, offset: 0x6640 */ __IO uint64_t GICD_IROUTER201; /**< GICD_IROUTER201, offset: 0x6648 */ __IO uint64_t GICD_IROUTER202; /**< GICD_IROUTER202, offset: 0x6650 */ __IO uint64_t GICD_IROUTER203; /**< GICD_IROUTER203, offset: 0x6658 */ __IO uint64_t GICD_IROUTER204; /**< GICD_IROUTER204, offset: 0x6660 */ __IO uint64_t GICD_IROUTER205; /**< GICD_IROUTER205, offset: 0x6668 */ __IO uint64_t GICD_IROUTER206; /**< GICD_IROUTER206, offset: 0x6670 */ __IO uint64_t GICD_IROUTER207; /**< GICD_IROUTER207, offset: 0x6678 */ __IO uint64_t GICD_IROUTER208; /**< GICD_IROUTER208, offset: 0x6680 */ __IO uint64_t GICD_IROUTER209; /**< GICD_IROUTER209, offset: 0x6688 */ __IO uint64_t GICD_IROUTER210; /**< GICD_IROUTER210, offset: 0x6690 */ __IO uint64_t GICD_IROUTER211; /**< GICD_IROUTER211, offset: 0x6698 */ __IO uint64_t GICD_IROUTER212; /**< GICD_IROUTER212, offset: 0x66A0 */ __IO uint64_t GICD_IROUTER213; /**< GICD_IROUTER213, offset: 0x66A8 */ __IO uint64_t GICD_IROUTER214; /**< GICD_IROUTER214, offset: 0x66B0 */ __IO uint64_t GICD_IROUTER215; /**< GICD_IROUTER215, offset: 0x66B8 */ __IO uint64_t GICD_IROUTER216; /**< GICD_IROUTER216, offset: 0x66C0 */ __IO uint64_t GICD_IROUTER217; /**< GICD_IROUTER217, offset: 0x66C8 */ __IO uint64_t GICD_IROUTER218; /**< GICD_IROUTER218, offset: 0x66D0 */ __IO uint64_t GICD_IROUTER219; /**< GICD_IROUTER219, offset: 0x66D8 */ __IO uint64_t GICD_IROUTER220; /**< GICD_IROUTER220, offset: 0x66E0 */ __IO uint64_t GICD_IROUTER221; /**< GICD_IROUTER221, offset: 0x66E8 */ __IO uint64_t GICD_IROUTER222; /**< GICD_IROUTER222, offset: 0x66F0 */ __IO uint64_t GICD_IROUTER223; /**< GICD_IROUTER223, offset: 0x66F8 */ __IO uint64_t GICD_IROUTER224; /**< GICD_IROUTER224, offset: 0x6700 */ __IO uint64_t GICD_IROUTER225; /**< GICD_IROUTER225, offset: 0x6708 */ __IO uint64_t GICD_IROUTER226; /**< GICD_IROUTER226, offset: 0x6710 */ __IO uint64_t GICD_IROUTER227; /**< GICD_IROUTER227, offset: 0x6718 */ __IO uint64_t GICD_IROUTER228; /**< GICD_IROUTER228, offset: 0x6720 */ __IO uint64_t GICD_IROUTER229; /**< GICD_IROUTER229, offset: 0x6728 */ __IO uint64_t GICD_IROUTER230; /**< GICD_IROUTER230, offset: 0x6730 */ __IO uint64_t GICD_IROUTER231; /**< GICD_IROUTER231, offset: 0x6738 */ __IO uint64_t GICD_IROUTER232; /**< GICD_IROUTER232, offset: 0x6740 */ __IO uint64_t GICD_IROUTER233; /**< GICD_IROUTER233, offset: 0x6748 */ __IO uint64_t GICD_IROUTER234; /**< GICD_IROUTER234, offset: 0x6750 */ __IO uint64_t GICD_IROUTER235; /**< GICD_IROUTER235, offset: 0x6758 */ __IO uint64_t GICD_IROUTER236; /**< GICD_IROUTER236, offset: 0x6760 */ __IO uint64_t GICD_IROUTER237; /**< GICD_IROUTER237, offset: 0x6768 */ __IO uint64_t GICD_IROUTER238; /**< GICD_IROUTER238, offset: 0x6770 */ __IO uint64_t GICD_IROUTER239; /**< GICD_IROUTER239, offset: 0x6778 */ __IO uint64_t GICD_IROUTER240; /**< GICD_IROUTER240, offset: 0x6780 */ __IO uint64_t GICD_IROUTER241; /**< GICD_IROUTER241, offset: 0x6788 */ __IO uint64_t GICD_IROUTER242; /**< GICD_IROUTER242, offset: 0x6790 */ __IO uint64_t GICD_IROUTER243; /**< GICD_IROUTER243, offset: 0x6798 */ __IO uint64_t GICD_IROUTER244; /**< GICD_IROUTER244, offset: 0x67A0 */ __IO uint64_t GICD_IROUTER245; /**< GICD_IROUTER245, offset: 0x67A8 */ __IO uint64_t GICD_IROUTER246; /**< GICD_IROUTER246, offset: 0x67B0 */ __IO uint64_t GICD_IROUTER247; /**< GICD_IROUTER247, offset: 0x67B8 */ __IO uint64_t GICD_IROUTER248; /**< GICD_IROUTER248, offset: 0x67C0 */ __IO uint64_t GICD_IROUTER249; /**< GICD_IROUTER249, offset: 0x67C8 */ __IO uint64_t GICD_IROUTER250; /**< GICD_IROUTER250, offset: 0x67D0 */ __IO uint64_t GICD_IROUTER251; /**< GICD_IROUTER251, offset: 0x67D8 */ __IO uint64_t GICD_IROUTER252; /**< GICD_IROUTER252, offset: 0x67E0 */ __IO uint64_t GICD_IROUTER253; /**< GICD_IROUTER253, offset: 0x67E8 */ __IO uint64_t GICD_IROUTER254; /**< GICD_IROUTER254, offset: 0x67F0 */ __IO uint64_t GICD_IROUTER255; /**< GICD_IROUTER255, offset: 0x67F8 */ __IO uint64_t GICD_IROUTER256; /**< GICD_IROUTER256, offset: 0x6800 */ __IO uint64_t GICD_IROUTER257; /**< GICD_IROUTER257, offset: 0x6808 */ __IO uint64_t GICD_IROUTER258; /**< GICD_IROUTER258, offset: 0x6810 */ __IO uint64_t GICD_IROUTER259; /**< GICD_IROUTER259, offset: 0x6818 */ __IO uint64_t GICD_IROUTER260; /**< GICD_IROUTER260, offset: 0x6820 */ __IO uint64_t GICD_IROUTER261; /**< GICD_IROUTER261, offset: 0x6828 */ __IO uint64_t GICD_IROUTER262; /**< GICD_IROUTER262, offset: 0x6830 */ __IO uint64_t GICD_IROUTER263; /**< GICD_IROUTER263, offset: 0x6838 */ __IO uint64_t GICD_IROUTER264; /**< GICD_IROUTER264, offset: 0x6840 */ __IO uint64_t GICD_IROUTER265; /**< GICD_IROUTER265, offset: 0x6848 */ __IO uint64_t GICD_IROUTER266; /**< GICD_IROUTER266, offset: 0x6850 */ __IO uint64_t GICD_IROUTER267; /**< GICD_IROUTER267, offset: 0x6858 */ __IO uint64_t GICD_IROUTER268; /**< GICD_IROUTER268, offset: 0x6860 */ __IO uint64_t GICD_IROUTER269; /**< GICD_IROUTER269, offset: 0x6868 */ __IO uint64_t GICD_IROUTER270; /**< GICD_IROUTER270, offset: 0x6870 */ __IO uint64_t GICD_IROUTER271; /**< GICD_IROUTER271, offset: 0x6878 */ __IO uint64_t GICD_IROUTER272; /**< GICD_IROUTER272, offset: 0x6880 */ __IO uint64_t GICD_IROUTER273; /**< GICD_IROUTER273, offset: 0x6888 */ __IO uint64_t GICD_IROUTER274; /**< GICD_IROUTER274, offset: 0x6890 */ __IO uint64_t GICD_IROUTER275; /**< GICD_IROUTER275, offset: 0x6898 */ __IO uint64_t GICD_IROUTER276; /**< GICD_IROUTER276, offset: 0x68A0 */ __IO uint64_t GICD_IROUTER277; /**< GICD_IROUTER277, offset: 0x68A8 */ __IO uint64_t GICD_IROUTER278; /**< GICD_IROUTER278, offset: 0x68B0 */ __IO uint64_t GICD_IROUTER279; /**< GICD_IROUTER279, offset: 0x68B8 */ __IO uint64_t GICD_IROUTER280; /**< GICD_IROUTER280, offset: 0x68C0 */ __IO uint64_t GICD_IROUTER281; /**< GICD_IROUTER281, offset: 0x68C8 */ __IO uint64_t GICD_IROUTER282; /**< GICD_IROUTER282, offset: 0x68D0 */ __IO uint64_t GICD_IROUTER283; /**< GICD_IROUTER283, offset: 0x68D8 */ __IO uint64_t GICD_IROUTER284; /**< GICD_IROUTER284, offset: 0x68E0 */ __IO uint64_t GICD_IROUTER285; /**< GICD_IROUTER285, offset: 0x68E8 */ __IO uint64_t GICD_IROUTER286; /**< GICD_IROUTER286, offset: 0x68F0 */ __IO uint64_t GICD_IROUTER287; /**< GICD_IROUTER287, offset: 0x68F8 */ __IO uint64_t GICD_IROUTER288; /**< GICD_IROUTER288, offset: 0x6900 */ __IO uint64_t GICD_IROUTER289; /**< GICD_IROUTER289, offset: 0x6908 */ __IO uint64_t GICD_IROUTER290; /**< GICD_IROUTER290, offset: 0x6910 */ __IO uint64_t GICD_IROUTER291; /**< GICD_IROUTER291, offset: 0x6918 */ __IO uint64_t GICD_IROUTER292; /**< GICD_IROUTER292, offset: 0x6920 */ __IO uint64_t GICD_IROUTER293; /**< GICD_IROUTER293, offset: 0x6928 */ __IO uint64_t GICD_IROUTER294; /**< GICD_IROUTER294, offset: 0x6930 */ __IO uint64_t GICD_IROUTER295; /**< GICD_IROUTER295, offset: 0x6938 */ __IO uint64_t GICD_IROUTER296; /**< GICD_IROUTER296, offset: 0x6940 */ __IO uint64_t GICD_IROUTER297; /**< GICD_IROUTER297, offset: 0x6948 */ __IO uint64_t GICD_IROUTER298; /**< GICD_IROUTER298, offset: 0x6950 */ __IO uint64_t GICD_IROUTER299; /**< GICD_IROUTER299, offset: 0x6958 */ __IO uint64_t GICD_IROUTER300; /**< GICD_IROUTER300, offset: 0x6960 */ __IO uint64_t GICD_IROUTER301; /**< GICD_IROUTER301, offset: 0x6968 */ __IO uint64_t GICD_IROUTER302; /**< GICD_IROUTER302, offset: 0x6970 */ __IO uint64_t GICD_IROUTER303; /**< GICD_IROUTER303, offset: 0x6978 */ __IO uint64_t GICD_IROUTER304; /**< GICD_IROUTER304, offset: 0x6980 */ __IO uint64_t GICD_IROUTER305; /**< GICD_IROUTER305, offset: 0x6988 */ __IO uint64_t GICD_IROUTER306; /**< GICD_IROUTER306, offset: 0x6990 */ __IO uint64_t GICD_IROUTER307; /**< GICD_IROUTER307, offset: 0x6998 */ __IO uint64_t GICD_IROUTER308; /**< GICD_IROUTER308, offset: 0x69A0 */ __IO uint64_t GICD_IROUTER309; /**< GICD_IROUTER309, offset: 0x69A8 */ __IO uint64_t GICD_IROUTER310; /**< GICD_IROUTER310, offset: 0x69B0 */ __IO uint64_t GICD_IROUTER311; /**< GICD_IROUTER311, offset: 0x69B8 */ __IO uint64_t GICD_IROUTER312; /**< GICD_IROUTER312, offset: 0x69C0 */ __IO uint64_t GICD_IROUTER313; /**< GICD_IROUTER313, offset: 0x69C8 */ __IO uint64_t GICD_IROUTER314; /**< GICD_IROUTER314, offset: 0x69D0 */ __IO uint64_t GICD_IROUTER315; /**< GICD_IROUTER315, offset: 0x69D8 */ __IO uint64_t GICD_IROUTER316; /**< GICD_IROUTER316, offset: 0x69E0 */ __IO uint64_t GICD_IROUTER317; /**< GICD_IROUTER317, offset: 0x69E8 */ __IO uint64_t GICD_IROUTER318; /**< GICD_IROUTER318, offset: 0x69F0 */ __IO uint64_t GICD_IROUTER319; /**< GICD_IROUTER319, offset: 0x69F8 */ __IO uint64_t GICD_IROUTER320; /**< GICD_IROUTER320, offset: 0x6A00 */ __IO uint64_t GICD_IROUTER321; /**< GICD_IROUTER321, offset: 0x6A08 */ __IO uint64_t GICD_IROUTER322; /**< GICD_IROUTER322, offset: 0x6A10 */ __IO uint64_t GICD_IROUTER323; /**< GICD_IROUTER323, offset: 0x6A18 */ __IO uint64_t GICD_IROUTER324; /**< GICD_IROUTER324, offset: 0x6A20 */ __IO uint64_t GICD_IROUTER325; /**< GICD_IROUTER325, offset: 0x6A28 */ __IO uint64_t GICD_IROUTER326; /**< GICD_IROUTER326, offset: 0x6A30 */ __IO uint64_t GICD_IROUTER327; /**< GICD_IROUTER327, offset: 0x6A38 */ __IO uint64_t GICD_IROUTER328; /**< GICD_IROUTER328, offset: 0x6A40 */ __IO uint64_t GICD_IROUTER329; /**< GICD_IROUTER329, offset: 0x6A48 */ __IO uint64_t GICD_IROUTER330; /**< GICD_IROUTER330, offset: 0x6A50 */ __IO uint64_t GICD_IROUTER331; /**< GICD_IROUTER331, offset: 0x6A58 */ __IO uint64_t GICD_IROUTER332; /**< GICD_IROUTER332, offset: 0x6A60 */ __IO uint64_t GICD_IROUTER333; /**< GICD_IROUTER333, offset: 0x6A68 */ __IO uint64_t GICD_IROUTER334; /**< GICD_IROUTER334, offset: 0x6A70 */ __IO uint64_t GICD_IROUTER335; /**< GICD_IROUTER335, offset: 0x6A78 */ __IO uint64_t GICD_IROUTER336; /**< GICD_IROUTER336, offset: 0x6A80 */ __IO uint64_t GICD_IROUTER337; /**< GICD_IROUTER337, offset: 0x6A88 */ __IO uint64_t GICD_IROUTER338; /**< GICD_IROUTER338, offset: 0x6A90 */ __IO uint64_t GICD_IROUTER339; /**< GICD_IROUTER339, offset: 0x6A98 */ __IO uint64_t GICD_IROUTER340; /**< GICD_IROUTER340, offset: 0x6AA0 */ __IO uint64_t GICD_IROUTER341; /**< GICD_IROUTER341, offset: 0x6AA8 */ __IO uint64_t GICD_IROUTER342; /**< GICD_IROUTER342, offset: 0x6AB0 */ __IO uint64_t GICD_IROUTER343; /**< GICD_IROUTER343, offset: 0x6AB8 */ __IO uint64_t GICD_IROUTER344; /**< GICD_IROUTER344, offset: 0x6AC0 */ __IO uint64_t GICD_IROUTER345; /**< GICD_IROUTER345, offset: 0x6AC8 */ __IO uint64_t GICD_IROUTER346; /**< GICD_IROUTER346, offset: 0x6AD0 */ __IO uint64_t GICD_IROUTER347; /**< GICD_IROUTER347, offset: 0x6AD8 */ __IO uint64_t GICD_IROUTER348; /**< GICD_IROUTER348, offset: 0x6AE0 */ __IO uint64_t GICD_IROUTER349; /**< GICD_IROUTER349, offset: 0x6AE8 */ __IO uint64_t GICD_IROUTER350; /**< GICD_IROUTER350, offset: 0x6AF0 */ __IO uint64_t GICD_IROUTER351; /**< GICD_IROUTER351, offset: 0x6AF8 */ __IO uint64_t GICD_IROUTER352; /**< GICD_IROUTER352, offset: 0x6B00 */ __IO uint64_t GICD_IROUTER353; /**< GICD_IROUTER353, offset: 0x6B08 */ __IO uint64_t GICD_IROUTER354; /**< GICD_IROUTER354, offset: 0x6B10 */ __IO uint64_t GICD_IROUTER355; /**< GICD_IROUTER355, offset: 0x6B18 */ __IO uint64_t GICD_IROUTER356; /**< GICD_IROUTER356, offset: 0x6B20 */ __IO uint64_t GICD_IROUTER357; /**< GICD_IROUTER357, offset: 0x6B28 */ __IO uint64_t GICD_IROUTER358; /**< GICD_IROUTER358, offset: 0x6B30 */ __IO uint64_t GICD_IROUTER359; /**< GICD_IROUTER359, offset: 0x6B38 */ __IO uint64_t GICD_IROUTER360; /**< GICD_IROUTER360, offset: 0x6B40 */ __IO uint64_t GICD_IROUTER361; /**< GICD_IROUTER361, offset: 0x6B48 */ __IO uint64_t GICD_IROUTER362; /**< GICD_IROUTER362, offset: 0x6B50 */ __IO uint64_t GICD_IROUTER363; /**< GICD_IROUTER363, offset: 0x6B58 */ __IO uint64_t GICD_IROUTER364; /**< GICD_IROUTER364, offset: 0x6B60 */ __IO uint64_t GICD_IROUTER365; /**< GICD_IROUTER365, offset: 0x6B68 */ __IO uint64_t GICD_IROUTER366; /**< GICD_IROUTER366, offset: 0x6B70 */ __IO uint64_t GICD_IROUTER367; /**< GICD_IROUTER367, offset: 0x6B78 */ __IO uint64_t GICD_IROUTER368; /**< GICD_IROUTER368, offset: 0x6B80 */ __IO uint64_t GICD_IROUTER369; /**< GICD_IROUTER369, offset: 0x6B88 */ __IO uint64_t GICD_IROUTER370; /**< GICD_IROUTER370, offset: 0x6B90 */ __IO uint64_t GICD_IROUTER371; /**< GICD_IROUTER371, offset: 0x6B98 */ __IO uint64_t GICD_IROUTER372; /**< GICD_IROUTER372, offset: 0x6BA0 */ __IO uint64_t GICD_IROUTER373; /**< GICD_IROUTER373, offset: 0x6BA8 */ __IO uint64_t GICD_IROUTER374; /**< GICD_IROUTER374, offset: 0x6BB0 */ __IO uint64_t GICD_IROUTER375; /**< GICD_IROUTER375, offset: 0x6BB8 */ __IO uint64_t GICD_IROUTER376; /**< GICD_IROUTER376, offset: 0x6BC0 */ __IO uint64_t GICD_IROUTER377; /**< GICD_IROUTER377, offset: 0x6BC8 */ __IO uint64_t GICD_IROUTER378; /**< GICD_IROUTER378, offset: 0x6BD0 */ __IO uint64_t GICD_IROUTER379; /**< GICD_IROUTER379, offset: 0x6BD8 */ __IO uint64_t GICD_IROUTER380; /**< GICD_IROUTER380, offset: 0x6BE0 */ __IO uint64_t GICD_IROUTER381; /**< GICD_IROUTER381, offset: 0x6BE8 */ __IO uint64_t GICD_IROUTER382; /**< GICD_IROUTER382, offset: 0x6BF0 */ __IO uint64_t GICD_IROUTER383; /**< GICD_IROUTER383, offset: 0x6BF8 */ __IO uint64_t GICD_IROUTER384; /**< GICD_IROUTER384, offset: 0x6C00 */ __IO uint64_t GICD_IROUTER385; /**< GICD_IROUTER385, offset: 0x6C08 */ __IO uint64_t GICD_IROUTER386; /**< GICD_IROUTER386, offset: 0x6C10 */ __IO uint64_t GICD_IROUTER387; /**< GICD_IROUTER387, offset: 0x6C18 */ __IO uint64_t GICD_IROUTER388; /**< GICD_IROUTER388, offset: 0x6C20 */ __IO uint64_t GICD_IROUTER389; /**< GICD_IROUTER389, offset: 0x6C28 */ __IO uint64_t GICD_IROUTER390; /**< GICD_IROUTER390, offset: 0x6C30 */ __IO uint64_t GICD_IROUTER391; /**< GICD_IROUTER391, offset: 0x6C38 */ __IO uint64_t GICD_IROUTER392; /**< GICD_IROUTER392, offset: 0x6C40 */ __IO uint64_t GICD_IROUTER393; /**< GICD_IROUTER393, offset: 0x6C48 */ __IO uint64_t GICD_IROUTER394; /**< GICD_IROUTER394, offset: 0x6C50 */ __IO uint64_t GICD_IROUTER395; /**< GICD_IROUTER395, offset: 0x6C58 */ __IO uint64_t GICD_IROUTER396; /**< GICD_IROUTER396, offset: 0x6C60 */ __IO uint64_t GICD_IROUTER397; /**< GICD_IROUTER397, offset: 0x6C68 */ __IO uint64_t GICD_IROUTER398; /**< GICD_IROUTER398, offset: 0x6C70 */ __IO uint64_t GICD_IROUTER399; /**< GICD_IROUTER399, offset: 0x6C78 */ __IO uint64_t GICD_IROUTER400; /**< GICD_IROUTER400, offset: 0x6C80 */ __IO uint64_t GICD_IROUTER401; /**< GICD_IROUTER401, offset: 0x6C88 */ __IO uint64_t GICD_IROUTER402; /**< GICD_IROUTER402, offset: 0x6C90 */ __IO uint64_t GICD_IROUTER403; /**< GICD_IROUTER403, offset: 0x6C98 */ __IO uint64_t GICD_IROUTER404; /**< GICD_IROUTER404, offset: 0x6CA0 */ __IO uint64_t GICD_IROUTER405; /**< GICD_IROUTER405, offset: 0x6CA8 */ __IO uint64_t GICD_IROUTER406; /**< GICD_IROUTER406, offset: 0x6CB0 */ __IO uint64_t GICD_IROUTER407; /**< GICD_IROUTER407, offset: 0x6CB8 */ __IO uint64_t GICD_IROUTER408; /**< GICD_IROUTER408, offset: 0x6CC0 */ __IO uint64_t GICD_IROUTER409; /**< GICD_IROUTER409, offset: 0x6CC8 */ __IO uint64_t GICD_IROUTER410; /**< GICD_IROUTER410, offset: 0x6CD0 */ __IO uint64_t GICD_IROUTER411; /**< GICD_IROUTER411, offset: 0x6CD8 */ __IO uint64_t GICD_IROUTER412; /**< GICD_IROUTER412, offset: 0x6CE0 */ __IO uint64_t GICD_IROUTER413; /**< GICD_IROUTER413, offset: 0x6CE8 */ __IO uint64_t GICD_IROUTER414; /**< GICD_IROUTER414, offset: 0x6CF0 */ __IO uint64_t GICD_IROUTER415; /**< GICD_IROUTER415, offset: 0x6CF8 */ uint8_t RESERVED_18[23296]; __O uint64_t GICD_RDOFFR0; /**< GICD_RDOFFR0, offset: 0xC800 */ uint8_t RESERVED_19[6144]; __IO uint32_t GICD_ICLAR2; /**< GICD_ICLAR2, offset: 0xE008 */ __IO uint32_t GICD_ICLAR3; /**< GICD_ICLAR3, offset: 0xE00C */ __IO uint32_t GICD_ICLAR4; /**< GICD_ICLAR4, offset: 0xE010 */ __IO uint32_t GICD_ICLAR5; /**< GICD_ICLAR5, offset: 0xE014 */ __IO uint32_t GICD_ICLAR6; /**< GICD_ICLAR6, offset: 0xE018 */ __IO uint32_t GICD_ICLAR7; /**< GICD_ICLAR7, offset: 0xE01C */ __IO uint32_t GICD_ICLAR8; /**< GICD_ICLAR8, offset: 0xE020 */ __IO uint32_t GICD_ICLAR9; /**< GICD_ICLAR9, offset: 0xE024 */ __IO uint32_t GICD_ICLAR10; /**< GICD_ICLAR10, offset: 0xE028 */ __IO uint32_t GICD_ICLAR11; /**< GICD_ICLAR11, offset: 0xE02C */ __IO uint32_t GICD_ICLAR12; /**< GICD_ICLAR12, offset: 0xE030 */ __IO uint32_t GICD_ICLAR13; /**< GICD_ICLAR13, offset: 0xE034 */ __IO uint32_t GICD_ICLAR14; /**< GICD_ICLAR14, offset: 0xE038 */ __IO uint32_t GICD_ICLAR15; /**< GICD_ICLAR15, offset: 0xE03C */ __IO uint32_t GICD_ICLAR16; /**< GICD_ICLAR16, offset: 0xE040 */ __IO uint32_t GICD_ICLAR17; /**< GICD_ICLAR17, offset: 0xE044 */ __IO uint32_t GICD_ICLAR18; /**< GICD_ICLAR18, offset: 0xE048 */ __IO uint32_t GICD_ICLAR19; /**< GICD_ICLAR19, offset: 0xE04C */ __IO uint32_t GICD_ICLAR20; /**< GICD_ICLAR20, offset: 0xE050 */ __IO uint32_t GICD_ICLAR21; /**< GICD_ICLAR21, offset: 0xE054 */ __IO uint32_t GICD_ICLAR22; /**< GICD_ICLAR22, offset: 0xE058 */ __IO uint32_t GICD_ICLAR23; /**< GICD_ICLAR23, offset: 0xE05C */ __IO uint32_t GICD_ICLAR24; /**< GICD_ICLAR24, offset: 0xE060 */ __IO uint32_t GICD_ICLAR25; /**< GICD_ICLAR25, offset: 0xE064 */ uint8_t RESERVED_20[156]; __IO uint32_t GICD_ICERRR1; /**< GICD_ICERRR1, offset: 0xE104 */ __IO uint32_t GICD_ICERRR2; /**< GICD_ICERRR2, offset: 0xE108 */ __IO uint32_t GICD_ICERRR3; /**< GICD_ICERRR3, offset: 0xE10C */ __IO uint32_t GICD_ICERRR4; /**< GICD_ICERRR4, offset: 0xE110 */ __IO uint32_t GICD_ICERRR5; /**< GICD_ICERRR5, offset: 0xE114 */ __IO uint32_t GICD_ICERRR6; /**< GICD_ICERRR6, offset: 0xE118 */ __IO uint32_t GICD_ICERRR7; /**< GICD_ICERRR7, offset: 0xE11C */ __IO uint32_t GICD_ICERRR8; /**< GICD_ICERRR8, offset: 0xE120 */ __IO uint32_t GICD_ICERRR9; /**< GICD_ICERRR9, offset: 0xE124 */ __IO uint32_t GICD_ICERRR10; /**< GICD_ICERRR10, offset: 0xE128 */ __IO uint32_t GICD_ICERRR11; /**< GICD_ICERRR11, offset: 0xE12C */ __IO uint32_t GICD_ICERRR12; /**< GICD_ICERRR12, offset: 0xE130 */ uint8_t RESERVED_21[80]; __IO uint32_t GICD_ICGERRR1; /**< GICD_ICGERRR1, offset: 0xE184 */ __IO uint32_t GICD_ICGERRR2; /**< GICD_ICGERRR2, offset: 0xE188 */ __IO uint32_t GICD_ICGERRR3; /**< GICD_ICGERRR3, offset: 0xE18C */ __IO uint32_t GICD_ICGERRR4; /**< GICD_ICGERRR4, offset: 0xE190 */ __IO uint32_t GICD_ICGERRR5; /**< GICD_ICGERRR5, offset: 0xE194 */ __IO uint32_t GICD_ICGERRR6; /**< GICD_ICGERRR6, offset: 0xE198 */ __IO uint32_t GICD_ICGERRR7; /**< GICD_ICGERRR7, offset: 0xE19C */ __IO uint32_t GICD_ICGERRR8; /**< GICD_ICGERRR8, offset: 0xE1A0 */ __IO uint32_t GICD_ICGERRR9; /**< GICD_ICGERRR9, offset: 0xE1A4 */ __IO uint32_t GICD_ICGERRR10; /**< GICD_ICGERRR10, offset: 0xE1A8 */ __IO uint32_t GICD_ICGERRR11; /**< GICD_ICGERRR11, offset: 0xE1AC */ __IO uint32_t GICD_ICGERRR12; /**< GICD_ICGERRR12, offset: 0xE1B0 */ uint8_t RESERVED_22[80]; __IO uint32_t GICD_ISERRR1; /**< GICD_ISERRR1, offset: 0xE204 */ __IO uint32_t GICD_ISERRR2; /**< GICD_ISERRR2, offset: 0xE208 */ __IO uint32_t GICD_ISERRR3; /**< GICD_ISERRR3, offset: 0xE20C */ __IO uint32_t GICD_ISERRR4; /**< GICD_ISERRR4, offset: 0xE210 */ __IO uint32_t GICD_ISERRR5; /**< GICD_ISERRR5, offset: 0xE214 */ __IO uint32_t GICD_ISERRR6; /**< GICD_ISERRR6, offset: 0xE218 */ __IO uint32_t GICD_ISERRR7; /**< GICD_ISERRR7, offset: 0xE21C */ __IO uint32_t GICD_ISERRR8; /**< GICD_ISERRR8, offset: 0xE220 */ __IO uint32_t GICD_ISERRR9; /**< GICD_ISERRR9, offset: 0xE224 */ __IO uint32_t GICD_ISERRR10; /**< GICD_ISERRR10, offset: 0xE228 */ __IO uint32_t GICD_ISERRR11; /**< GICD_ISERRR11, offset: 0xE22C */ __IO uint32_t GICD_ISERRR12; /**< GICD_ISERRR12, offset: 0xE230 */ uint8_t RESERVED_23[3532]; __I uint64_t GICD_CFGID; /**< GICD_CFGID, offset: 0xF000 */ uint8_t RESERVED_24[4040]; __I uint32_t GICD_PIDR4; /**< GICD_PIDR4, offset: 0xFFD0 */ __I uint32_t GICD_PIDR5; /**< GICD_PIDR5, offset: 0xFFD4 */ __I uint32_t GICD_PIDR6; /**< GICD_PIDR6, offset: 0xFFD8 */ __I uint32_t GICD_PIDR7; /**< GICD_PIDR7, offset: 0xFFDC */ __I uint32_t GICD_PIDR0; /**< GICD_PIDR0, offset: 0xFFE0 */ __I uint32_t GICD_PIDR1; /**< GICD_PIDR1, offset: 0xFFE4 */ __I uint32_t GICD_PIDR2; /**< GICD_PIDR2, offset: 0xFFE8 */ __I uint32_t GICD_PIDR3; /**< GICD_PIDR3, offset: 0xFFEC */ __I uint32_t GICD_CIDR0; /**< GICD_CIDR0, offset: 0xFFF0 */ __I uint32_t GICD_CIDR1; /**< GICD_CIDR1, offset: 0xFFF4 */ __I uint32_t GICD_CIDR2; /**< GICD_CIDR2, offset: 0xFFF8 */ __I uint32_t GICD_CIDR3; /**< GICD_CIDR3, offset: 0xFFFC */ } NOC_GICD_Type; /* ---------------------------------------------------------------------------- -- NOC_GICD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICD_Register_Masks NOC_GICD Register Masks * @{ */ /*! @name GICD_CTLR - GICD_CTLR */ /*! @{ */ #define NOC_GICD_GICD_CTLR_EnableGrp0_MASK (0x1U) #define NOC_GICD_GICD_CTLR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICD_GICD_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_EnableGrp0_SHIFT)) & NOC_GICD_GICD_CTLR_EnableGrp0_MASK) #define NOC_GICD_GICD_CTLR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICD_GICD_CTLR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICD_GICD_CTLR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_EnableGrp1_ns_SHIFT)) & NOC_GICD_GICD_CTLR_EnableGrp1_ns_MASK) #define NOC_GICD_GICD_CTLR_EnableGrp1_s_MASK (0x4U) #define NOC_GICD_GICD_CTLR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICD_GICD_CTLR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_EnableGrp1_s_SHIFT)) & NOC_GICD_GICD_CTLR_EnableGrp1_s_MASK) #define NOC_GICD_GICD_CTLR_RESERVED0_MASK (0x8U) #define NOC_GICD_GICD_CTLR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_RESERVED0_SHIFT)) & NOC_GICD_GICD_CTLR_RESERVED0_MASK) #define NOC_GICD_GICD_CTLR_ARE_S_MASK (0x10U) #define NOC_GICD_GICD_CTLR_ARE_S_SHIFT (4U) /*! ARE_S - ARE_S */ #define NOC_GICD_GICD_CTLR_ARE_S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_ARE_S_SHIFT)) & NOC_GICD_GICD_CTLR_ARE_S_MASK) #define NOC_GICD_GICD_CTLR_ARE_NS_MASK (0x20U) #define NOC_GICD_GICD_CTLR_ARE_NS_SHIFT (5U) /*! ARE_NS - ARE_NS */ #define NOC_GICD_GICD_CTLR_ARE_NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_ARE_NS_SHIFT)) & NOC_GICD_GICD_CTLR_ARE_NS_MASK) #define NOC_GICD_GICD_CTLR_DS_MASK (0x40U) #define NOC_GICD_GICD_CTLR_DS_SHIFT (6U) /*! DS - DS */ #define NOC_GICD_GICD_CTLR_DS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_DS_SHIFT)) & NOC_GICD_GICD_CTLR_DS_MASK) #define NOC_GICD_GICD_CTLR_E1NWF_MASK (0x80U) #define NOC_GICD_GICD_CTLR_E1NWF_SHIFT (7U) /*! E1NWF - E1NWF */ #define NOC_GICD_GICD_CTLR_E1NWF(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_E1NWF_SHIFT)) & NOC_GICD_GICD_CTLR_E1NWF_MASK) #define NOC_GICD_GICD_CTLR_RESERVED1_MASK (0x7FFFFF00U) #define NOC_GICD_GICD_CTLR_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_RESERVED1_SHIFT)) & NOC_GICD_GICD_CTLR_RESERVED1_MASK) #define NOC_GICD_GICD_CTLR_RWP_MASK (0x80000000U) #define NOC_GICD_GICD_CTLR_RWP_SHIFT (31U) /*! RWP - RWP */ #define NOC_GICD_GICD_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CTLR_RWP_SHIFT)) & NOC_GICD_GICD_CTLR_RWP_MASK) /*! @} */ /*! @name GICD_TYPER - GICD_TYPER */ /*! @{ */ #define NOC_GICD_GICD_TYPER_ITLinesNumber_MASK (0x1FU) #define NOC_GICD_GICD_TYPER_ITLinesNumber_SHIFT (0U) /*! ITLinesNumber - ITLinesNumber */ #define NOC_GICD_GICD_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_ITLinesNumber_SHIFT)) & NOC_GICD_GICD_TYPER_ITLinesNumber_MASK) #define NOC_GICD_GICD_TYPER_CPUNumber_MASK (0xE0U) #define NOC_GICD_GICD_TYPER_CPUNumber_SHIFT (5U) /*! CPUNumber - CPUNumber */ #define NOC_GICD_GICD_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_CPUNumber_SHIFT)) & NOC_GICD_GICD_TYPER_CPUNumber_MASK) #define NOC_GICD_GICD_TYPER_Espi_MASK (0x100U) #define NOC_GICD_GICD_TYPER_Espi_SHIFT (8U) /*! Espi - Espi */ #define NOC_GICD_GICD_TYPER_Espi(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_Espi_SHIFT)) & NOC_GICD_GICD_TYPER_Espi_MASK) #define NOC_GICD_GICD_TYPER_RESERVED0_MASK (0x200U) #define NOC_GICD_GICD_TYPER_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_TYPER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_RESERVED0_SHIFT)) & NOC_GICD_GICD_TYPER_RESERVED0_MASK) #define NOC_GICD_GICD_TYPER_SecurityExtn_MASK (0x400U) #define NOC_GICD_GICD_TYPER_SecurityExtn_SHIFT (10U) /*! SecurityExtn - SecurityExtn */ #define NOC_GICD_GICD_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_SecurityExtn_SHIFT)) & NOC_GICD_GICD_TYPER_SecurityExtn_MASK) #define NOC_GICD_GICD_TYPER_LSPI_MASK (0xF800U) #define NOC_GICD_GICD_TYPER_LSPI_SHIFT (11U) /*! LSPI - LSPI */ #define NOC_GICD_GICD_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_LSPI_SHIFT)) & NOC_GICD_GICD_TYPER_LSPI_MASK) #define NOC_GICD_GICD_TYPER_MBIS_MASK (0x10000U) #define NOC_GICD_GICD_TYPER_MBIS_SHIFT (16U) /*! MBIS - MBIS */ #define NOC_GICD_GICD_TYPER_MBIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_MBIS_SHIFT)) & NOC_GICD_GICD_TYPER_MBIS_MASK) #define NOC_GICD_GICD_TYPER_LPIS_MASK (0x20000U) #define NOC_GICD_GICD_TYPER_LPIS_SHIFT (17U) /*! LPIS - LPIS */ #define NOC_GICD_GICD_TYPER_LPIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_LPIS_SHIFT)) & NOC_GICD_GICD_TYPER_LPIS_MASK) #define NOC_GICD_GICD_TYPER_DVIS_MASK (0x40000U) #define NOC_GICD_GICD_TYPER_DVIS_SHIFT (18U) /*! DVIS - DVIS */ #define NOC_GICD_GICD_TYPER_DVIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_DVIS_SHIFT)) & NOC_GICD_GICD_TYPER_DVIS_MASK) #define NOC_GICD_GICD_TYPER_IDbits_MASK (0xF80000U) #define NOC_GICD_GICD_TYPER_IDbits_SHIFT (19U) /*! IDbits - IDbits */ #define NOC_GICD_GICD_TYPER_IDbits(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_IDbits_SHIFT)) & NOC_GICD_GICD_TYPER_IDbits_MASK) #define NOC_GICD_GICD_TYPER_A3V_MASK (0x1000000U) #define NOC_GICD_GICD_TYPER_A3V_SHIFT (24U) /*! A3V - A3V */ #define NOC_GICD_GICD_TYPER_A3V(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_A3V_SHIFT)) & NOC_GICD_GICD_TYPER_A3V_MASK) #define NOC_GICD_GICD_TYPER_No1N_MASK (0x2000000U) #define NOC_GICD_GICD_TYPER_No1N_SHIFT (25U) /*! No1N - No1N */ #define NOC_GICD_GICD_TYPER_No1N(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_No1N_SHIFT)) & NOC_GICD_GICD_TYPER_No1N_MASK) #define NOC_GICD_GICD_TYPER_RSS_MASK (0x4000000U) #define NOC_GICD_GICD_TYPER_RSS_SHIFT (26U) /*! RSS - RSS */ #define NOC_GICD_GICD_TYPER_RSS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_RSS_SHIFT)) & NOC_GICD_GICD_TYPER_RSS_MASK) #define NOC_GICD_GICD_TYPER_ESPI_range_MASK (0xF8000000U) #define NOC_GICD_GICD_TYPER_ESPI_range_SHIFT (27U) /*! ESPI_range - ESPI_range */ #define NOC_GICD_GICD_TYPER_ESPI_range(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER_ESPI_range_SHIFT)) & NOC_GICD_GICD_TYPER_ESPI_range_MASK) /*! @} */ /*! @name GICD_IIDR - GICD_IIDR */ /*! @{ */ #define NOC_GICD_GICD_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICD_GICD_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICD_GICD_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IIDR_Implementer_SHIFT)) & NOC_GICD_GICD_IIDR_Implementer_MASK) #define NOC_GICD_GICD_IIDR_Revision_MASK (0xF000U) #define NOC_GICD_GICD_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICD_GICD_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IIDR_Revision_SHIFT)) & NOC_GICD_GICD_IIDR_Revision_MASK) #define NOC_GICD_GICD_IIDR_Variant_MASK (0xF0000U) #define NOC_GICD_GICD_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICD_GICD_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IIDR_Variant_SHIFT)) & NOC_GICD_GICD_IIDR_Variant_MASK) #define NOC_GICD_GICD_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICD_GICD_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IIDR_RESERVED0_SHIFT)) & NOC_GICD_GICD_IIDR_RESERVED0_MASK) #define NOC_GICD_GICD_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICD_GICD_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICD_GICD_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IIDR_ProductID_SHIFT)) & NOC_GICD_GICD_IIDR_ProductID_MASK) /*! @} */ /*! @name GICD_TYPER2 - GICD_TYPER2 */ /*! @{ */ #define NOC_GICD_GICD_TYPER2_VID_MASK (0x1FU) #define NOC_GICD_GICD_TYPER2_VID_SHIFT (0U) /*! VID - VID */ #define NOC_GICD_GICD_TYPER2_VID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER2_VID_SHIFT)) & NOC_GICD_GICD_TYPER2_VID_MASK) #define NOC_GICD_GICD_TYPER2_RESERVED0_MASK (0x60U) #define NOC_GICD_GICD_TYPER2_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_TYPER2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER2_RESERVED0_SHIFT)) & NOC_GICD_GICD_TYPER2_RESERVED0_MASK) #define NOC_GICD_GICD_TYPER2_VIL_MASK (0x80U) #define NOC_GICD_GICD_TYPER2_VIL_SHIFT (7U) /*! VIL - VIL */ #define NOC_GICD_GICD_TYPER2_VIL(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER2_VIL_SHIFT)) & NOC_GICD_GICD_TYPER2_VIL_MASK) #define NOC_GICD_GICD_TYPER2_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_TYPER2_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_TYPER2_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_TYPER2_RESERVED1_SHIFT)) & NOC_GICD_GICD_TYPER2_RESERVED1_MASK) /*! @} */ /*! @name GICD_STATUSR - GICD_STATUSR */ /*! @{ */ #define NOC_GICD_GICD_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICD_GICD_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICD_GICD_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_STATUSR_RESERVED_SHIFT)) & NOC_GICD_GICD_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICD_FCTLR - GICD_FCTLR */ /*! @{ */ #define NOC_GICD_GICD_FCTLR_SIP_MASK (0x1U) #define NOC_GICD_GICD_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICD_GICD_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_SIP_SHIFT)) & NOC_GICD_GICD_FCTLR_SIP_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED0_MASK (0x2U) #define NOC_GICD_GICD_FCTLR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED0_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED0_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED1_MASK (0x4U) #define NOC_GICD_GICD_FCTLR_RESERVED1_SHIFT (2U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED1_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED1_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED2_MASK (0x8U) #define NOC_GICD_GICD_FCTLR_RESERVED2_SHIFT (3U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICD_GICD_FCTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED2_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED2_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED3_MASK (0xFFF0U) #define NOC_GICD_GICD_FCTLR_RESERVED3_SHIFT (4U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICD_GICD_FCTLR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED3_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED3_MASK) #define NOC_GICD_GICD_FCTLR_NSACR_MASK (0x30000U) #define NOC_GICD_GICD_FCTLR_NSACR_SHIFT (16U) /*! NSACR - NSACR */ #define NOC_GICD_GICD_FCTLR_NSACR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_NSACR_SHIFT)) & NOC_GICD_GICD_FCTLR_NSACR_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED4_MASK (0x40000U) #define NOC_GICD_GICD_FCTLR_RESERVED4_SHIFT (18U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICD_GICD_FCTLR_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED4_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED4_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED5_MASK (0x80000U) #define NOC_GICD_GICD_FCTLR_RESERVED5_SHIFT (19U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICD_GICD_FCTLR_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED5_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED5_MASK) #define NOC_GICD_GICD_FCTLR_CLPL_MASK (0xF00000U) #define NOC_GICD_GICD_FCTLR_CLPL_SHIFT (20U) /*! CLPL - CLPL */ #define NOC_GICD_GICD_FCTLR_CLPL(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_CLPL_SHIFT)) & NOC_GICD_GICD_FCTLR_CLPL_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED6_MASK (0x3000000U) #define NOC_GICD_GICD_FCTLR_RESERVED6_SHIFT (24U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICD_GICD_FCTLR_RESERVED6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED6_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED6_MASK) #define NOC_GICD_GICD_FCTLR_POS_MASK (0x4000000U) #define NOC_GICD_GICD_FCTLR_POS_SHIFT (26U) /*! POS - POS */ #define NOC_GICD_GICD_FCTLR_POS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_POS_SHIFT)) & NOC_GICD_GICD_FCTLR_POS_MASK) #define NOC_GICD_GICD_FCTLR_RESERVED7_MASK (0xF8000000U) #define NOC_GICD_GICD_FCTLR_RESERVED7_SHIFT (27U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICD_GICD_FCTLR_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR_RESERVED7_SHIFT)) & NOC_GICD_GICD_FCTLR_RESERVED7_MASK) /*! @} */ /*! @name GICD_SAC - GICD_SAC */ /*! @{ */ #define NOC_GICD_GICD_SAC_RESERVED0_MASK (0x1U) #define NOC_GICD_GICD_SAC_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_SAC_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SAC_RESERVED0_SHIFT)) & NOC_GICD_GICD_SAC_RESERVED0_MASK) #define NOC_GICD_GICD_SAC_GICTNS_MASK (0x2U) #define NOC_GICD_GICD_SAC_GICTNS_SHIFT (1U) /*! GICTNS - GICTNS */ #define NOC_GICD_GICD_SAC_GICTNS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SAC_GICTNS_SHIFT)) & NOC_GICD_GICD_SAC_GICTNS_MASK) #define NOC_GICD_GICD_SAC_GICPNS_MASK (0x4U) #define NOC_GICD_GICD_SAC_GICPNS_SHIFT (2U) /*! GICPNS - GICPNS */ #define NOC_GICD_GICD_SAC_GICPNS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SAC_GICPNS_SHIFT)) & NOC_GICD_GICD_SAC_GICPNS_MASK) #define NOC_GICD_GICD_SAC_RESERVED1_MASK (0xFFFFFFF8U) #define NOC_GICD_GICD_SAC_RESERVED1_SHIFT (3U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_SAC_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SAC_RESERVED1_SHIFT)) & NOC_GICD_GICD_SAC_RESERVED1_MASK) /*! @} */ /*! @name GICD_FCTLR2 - GICD_FCTLR2 */ /*! @{ */ #define NOC_GICD_GICD_FCTLR2_CGO_MASK (0xFFFU) #define NOC_GICD_GICD_FCTLR2_CGO_SHIFT (0U) /*! CGO - CGO */ #define NOC_GICD_GICD_FCTLR2_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_CGO_SHIFT)) & NOC_GICD_GICD_FCTLR2_CGO_MASK) #define NOC_GICD_GICD_FCTLR2_RESERVED0_MASK (0x7000U) #define NOC_GICD_GICD_FCTLR2_RESERVED0_SHIFT (12U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_FCTLR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_RESERVED0_SHIFT)) & NOC_GICD_GICD_FCTLR2_RESERVED0_MASK) #define NOC_GICD_GICD_FCTLR2_RESERVED1_MASK (0x8000U) #define NOC_GICD_GICD_FCTLR2_RESERVED1_SHIFT (15U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_FCTLR2_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_RESERVED1_SHIFT)) & NOC_GICD_GICD_FCTLR2_RESERVED1_MASK) #define NOC_GICD_GICD_FCTLR2_RWS_MASK (0x10000U) #define NOC_GICD_GICD_FCTLR2_RWS_SHIFT (16U) /*! RWS - RWS */ #define NOC_GICD_GICD_FCTLR2_RWS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_RWS_SHIFT)) & NOC_GICD_GICD_FCTLR2_RWS_MASK) #define NOC_GICD_GICD_FCTLR2_DCC_MASK (0x20000U) #define NOC_GICD_GICD_FCTLR2_DCC_SHIFT (17U) /*! DCC - DCC */ #define NOC_GICD_GICD_FCTLR2_DCC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_DCC_SHIFT)) & NOC_GICD_GICD_FCTLR2_DCC_MASK) #define NOC_GICD_GICD_FCTLR2_QDENY_MASK (0x40000U) #define NOC_GICD_GICD_FCTLR2_QDENY_SHIFT (18U) /*! QDENY - QDENY */ #define NOC_GICD_GICD_FCTLR2_QDENY(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_QDENY_SHIFT)) & NOC_GICD_GICD_FCTLR2_QDENY_MASK) #define NOC_GICD_GICD_FCTLR2_RWC_MASK (0x80000U) #define NOC_GICD_GICD_FCTLR2_RWC_SHIFT (19U) /*! RWC - RWC */ #define NOC_GICD_GICD_FCTLR2_RWC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_RWC_SHIFT)) & NOC_GICD_GICD_FCTLR2_RWC_MASK) #define NOC_GICD_GICD_FCTLR2_RESERVED2_MASK (0x1F00000U) #define NOC_GICD_GICD_FCTLR2_RESERVED2_SHIFT (20U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICD_GICD_FCTLR2_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_RESERVED2_SHIFT)) & NOC_GICD_GICD_FCTLR2_RESERVED2_MASK) #define NOC_GICD_GICD_FCTLR2_SLC_MASK (0x2000000U) #define NOC_GICD_GICD_FCTLR2_SLC_SHIFT (25U) /*! SLC - SLC */ #define NOC_GICD_GICD_FCTLR2_SLC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_SLC_SHIFT)) & NOC_GICD_GICD_FCTLR2_SLC_MASK) #define NOC_GICD_GICD_FCTLR2_RESERVED3_MASK (0xC000000U) #define NOC_GICD_GICD_FCTLR2_RESERVED3_SHIFT (26U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICD_GICD_FCTLR2_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_RESERVED3_SHIFT)) & NOC_GICD_GICD_FCTLR2_RESERVED3_MASK) #define NOC_GICD_GICD_FCTLR2_RCD_MASK (0x10000000U) #define NOC_GICD_GICD_FCTLR2_RCD_SHIFT (28U) /*! RCD - RCD */ #define NOC_GICD_GICD_FCTLR2_RCD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_RCD_SHIFT)) & NOC_GICD_GICD_FCTLR2_RCD_MASK) #define NOC_GICD_GICD_FCTLR2_IRP_MASK (0x20000000U) #define NOC_GICD_GICD_FCTLR2_IRP_SHIFT (29U) /*! IRP - IRP */ #define NOC_GICD_GICD_FCTLR2_IRP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_IRP_SHIFT)) & NOC_GICD_GICD_FCTLR2_IRP_MASK) #define NOC_GICD_GICD_FCTLR2_AWP_MASK (0x40000000U) #define NOC_GICD_GICD_FCTLR2_AWP_SHIFT (30U) /*! AWP - AWP */ #define NOC_GICD_GICD_FCTLR2_AWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_AWP_SHIFT)) & NOC_GICD_GICD_FCTLR2_AWP_MASK) #define NOC_GICD_GICD_FCTLR2_ARP_MASK (0x80000000U) #define NOC_GICD_GICD_FCTLR2_ARP_SHIFT (31U) /*! ARP - ARP */ #define NOC_GICD_GICD_FCTLR2_ARP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR2_ARP_SHIFT)) & NOC_GICD_GICD_FCTLR2_ARP_MASK) /*! @} */ /*! @name GICD_UTILR - GICD_UTILR */ /*! @{ */ #define NOC_GICD_GICD_UTILR_UEDU_MASK (0xFU) #define NOC_GICD_GICD_UTILR_UEDU_SHIFT (0U) /*! UEDU - UEDU */ #define NOC_GICD_GICD_UTILR_UEDU(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEDU_SHIFT)) & NOC_GICD_GICD_UTILR_UEDU_MASK) #define NOC_GICD_GICD_UTILR_RESERVED0_MASK (0x1FF0U) #define NOC_GICD_GICD_UTILR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_UTILR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_RESERVED0_SHIFT)) & NOC_GICD_GICD_UTILR_RESERVED0_MASK) #define NOC_GICD_GICD_UTILR_UEDA_MASK (0x2000U) #define NOC_GICD_GICD_UTILR_UEDA_SHIFT (13U) /*! UEDA - UEDA */ #define NOC_GICD_GICD_UTILR_UEDA(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEDA_SHIFT)) & NOC_GICD_GICD_UTILR_UEDA_MASK) #define NOC_GICD_GICD_UTILR_UEDE_MASK (0x4000U) #define NOC_GICD_GICD_UTILR_UEDE_SHIFT (14U) /*! UEDE - UEDE */ #define NOC_GICD_GICD_UTILR_UEDE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEDE_SHIFT)) & NOC_GICD_GICD_UTILR_UEDE_MASK) #define NOC_GICD_GICD_UTILR_UEDT_MASK (0x8000U) #define NOC_GICD_GICD_UTILR_UEDT_SHIFT (15U) /*! UEDT - UEDT */ #define NOC_GICD_GICD_UTILR_UEDT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEDT_SHIFT)) & NOC_GICD_GICD_UTILR_UEDT_MASK) #define NOC_GICD_GICD_UTILR_UEOU_MASK (0xF0000U) #define NOC_GICD_GICD_UTILR_UEOU_SHIFT (16U) /*! UEOU - UEOU */ #define NOC_GICD_GICD_UTILR_UEOU(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEOU_SHIFT)) & NOC_GICD_GICD_UTILR_UEOU_MASK) #define NOC_GICD_GICD_UTILR_RESERVED1_MASK (0x1FF00000U) #define NOC_GICD_GICD_UTILR_RESERVED1_SHIFT (20U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_UTILR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_RESERVED1_SHIFT)) & NOC_GICD_GICD_UTILR_RESERVED1_MASK) #define NOC_GICD_GICD_UTILR_UEOA_MASK (0x20000000U) #define NOC_GICD_GICD_UTILR_UEOA_SHIFT (29U) /*! UEOA - UEOA */ #define NOC_GICD_GICD_UTILR_UEOA(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEOA_SHIFT)) & NOC_GICD_GICD_UTILR_UEOA_MASK) #define NOC_GICD_GICD_UTILR_UEOE_MASK (0x40000000U) #define NOC_GICD_GICD_UTILR_UEOE_SHIFT (30U) /*! UEOE - UEOE */ #define NOC_GICD_GICD_UTILR_UEOE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEOE_SHIFT)) & NOC_GICD_GICD_UTILR_UEOE_MASK) #define NOC_GICD_GICD_UTILR_UEOT_MASK (0x80000000U) #define NOC_GICD_GICD_UTILR_UEOT_SHIFT (31U) /*! UEOT - UEOT */ #define NOC_GICD_GICD_UTILR_UEOT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_UTILR_UEOT_SHIFT)) & NOC_GICD_GICD_UTILR_UEOT_MASK) /*! @} */ /*! @name GICD_FCTLR3 - GICD_FCTLR3 */ /*! @{ */ #define NOC_GICD_GICD_FCTLR3_NCP0_MASK (0x1FU) #define NOC_GICD_GICD_FCTLR3_NCP0_SHIFT (0U) /*! NCP0 - NCP0 */ #define NOC_GICD_GICD_FCTLR3_NCP0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR3_NCP0_SHIFT)) & NOC_GICD_GICD_FCTLR3_NCP0_MASK) #define NOC_GICD_GICD_FCTLR3_RESERVED0_MASK (0x60U) #define NOC_GICD_GICD_FCTLR3_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_FCTLR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR3_RESERVED0_SHIFT)) & NOC_GICD_GICD_FCTLR3_RESERVED0_MASK) #define NOC_GICD_GICD_FCTLR3_SCP1_MASK (0x80U) #define NOC_GICD_GICD_FCTLR3_SCP1_SHIFT (7U) /*! SCP1 - SCP1 */ #define NOC_GICD_GICD_FCTLR3_SCP1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR3_SCP1_SHIFT)) & NOC_GICD_GICD_FCTLR3_SCP1_MASK) #define NOC_GICD_GICD_FCTLR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_FCTLR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_FCTLR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_FCTLR3_RESERVED1_SHIFT)) & NOC_GICD_GICD_FCTLR3_RESERVED1_MASK) /*! @} */ /*! @name GICD_SETSPI_NSR - GICD_SETSPI_NSR */ /*! @{ */ #define NOC_GICD_GICD_SETSPI_NSR_ID_MASK (0xFFFFU) #define NOC_GICD_GICD_SETSPI_NSR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICD_GICD_SETSPI_NSR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SETSPI_NSR_ID_SHIFT)) & NOC_GICD_GICD_SETSPI_NSR_ID_MASK) #define NOC_GICD_GICD_SETSPI_NSR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICD_GICD_SETSPI_NSR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_SETSPI_NSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SETSPI_NSR_RESERVED0_SHIFT)) & NOC_GICD_GICD_SETSPI_NSR_RESERVED0_MASK) /*! @} */ /*! @name GICD_CLRSPI_NSR - GICD_CLRSPI_NSR */ /*! @{ */ #define NOC_GICD_GICD_CLRSPI_NSR_ID_MASK (0xFFFFU) #define NOC_GICD_GICD_CLRSPI_NSR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICD_GICD_CLRSPI_NSR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CLRSPI_NSR_ID_SHIFT)) & NOC_GICD_GICD_CLRSPI_NSR_ID_MASK) #define NOC_GICD_GICD_CLRSPI_NSR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICD_GICD_CLRSPI_NSR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CLRSPI_NSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CLRSPI_NSR_RESERVED0_SHIFT)) & NOC_GICD_GICD_CLRSPI_NSR_RESERVED0_MASK) /*! @} */ /*! @name GICD_SETSPI_SR - GICD_SETSPI_SR */ /*! @{ */ #define NOC_GICD_GICD_SETSPI_SR_ID_MASK (0xFFFFU) #define NOC_GICD_GICD_SETSPI_SR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICD_GICD_SETSPI_SR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SETSPI_SR_ID_SHIFT)) & NOC_GICD_GICD_SETSPI_SR_ID_MASK) #define NOC_GICD_GICD_SETSPI_SR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICD_GICD_SETSPI_SR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_SETSPI_SR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_SETSPI_SR_RESERVED0_SHIFT)) & NOC_GICD_GICD_SETSPI_SR_RESERVED0_MASK) /*! @} */ /*! @name GICD_CLRSPI_SR - GICD_CLRSPI_SR */ /*! @{ */ #define NOC_GICD_GICD_CLRSPI_SR_ID_MASK (0xFFFFU) #define NOC_GICD_GICD_CLRSPI_SR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICD_GICD_CLRSPI_SR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CLRSPI_SR_ID_SHIFT)) & NOC_GICD_GICD_CLRSPI_SR_ID_MASK) #define NOC_GICD_GICD_CLRSPI_SR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICD_GICD_CLRSPI_SR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CLRSPI_SR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CLRSPI_SR_RESERVED0_SHIFT)) & NOC_GICD_GICD_CLRSPI_SR_RESERVED0_MASK) /*! @} */ /*! @name GICD_IGROUPR1 - GICD_IGROUPR1 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR1_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR1_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR1_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR1_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR1_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR2 - GICD_IGROUPR2 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR2_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR2_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR2_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR2_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR2_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR3 - GICD_IGROUPR3 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR3_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR3_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR3_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR3_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR3_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR4 - GICD_IGROUPR4 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR4_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR4_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR4_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR4_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR4_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR5 - GICD_IGROUPR5 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR5_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR5_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR5_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR5_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR5_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR6 - GICD_IGROUPR6 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR6_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR6_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR6_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR6_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR6_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR7 - GICD_IGROUPR7 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR7_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR7_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR7_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR7_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR7_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR8 - GICD_IGROUPR8 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR8_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR8_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR8_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR8_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR8_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR9 - GICD_IGROUPR9 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR9_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR9_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR9_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR9_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR9_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR10 - GICD_IGROUPR10 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR10_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR10_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR10_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR10_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR10_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR11 - GICD_IGROUPR11 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR11_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR11_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR11_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR11_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR11_group_status_bit31_MASK) /*! @} */ /*! @name GICD_IGROUPR12 - GICD_IGROUPR12 */ /*! @{ */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit0_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit0_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit1_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit1_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit2_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit2_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit3_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit3_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit4_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit4_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit5_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit5_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit6_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit6_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit7_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit7_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit8_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit8_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit9_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit9_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit10_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit10_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit11_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit11_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit12_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit12_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit13_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit13_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit14_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit14_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit15_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit15_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit16_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit16_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit17_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit17_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit18_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit18_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit19_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit19_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit20_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit20_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit21_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit21_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit22_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit22_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit23_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit23_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit24_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit24_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit25_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit25_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit26_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit26_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit27_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit27_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit28_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit28_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit29_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit29_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit30_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit30_MASK) #define NOC_GICD_GICD_IGROUPR12_group_status_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGROUPR12_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICD_GICD_IGROUPR12_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGROUPR12_group_status_bit31_SHIFT)) & NOC_GICD_GICD_IGROUPR12_group_status_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER1 - GICD_ISENABLER1 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER1_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER1_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER1_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER1_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER2 - GICD_ISENABLER2 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER2_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER2_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER2_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER2_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER3 - GICD_ISENABLER3 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER3_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER3_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER3_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER3_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER4 - GICD_ISENABLER4 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER4_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER4_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER4_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER4_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER5 - GICD_ISENABLER5 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER5_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER5_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER5_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER5_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER6 - GICD_ISENABLER6 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER6_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER6_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER6_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER6_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER7 - GICD_ISENABLER7 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER7_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER7_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER7_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER7_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER8 - GICD_ISENABLER8 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER8_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER8_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER8_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER8_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER9 - GICD_ISENABLER9 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER9_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER9_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER9_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER9_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER10 - GICD_ISENABLER10 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER10_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER10_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER10_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER10_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER11 - GICD_ISENABLER11 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER11_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER11_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER11_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER11_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISENABLER12 - GICD_ISENABLER12 */ /*! @{ */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit0_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit0_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit1_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit1_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit2_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit2_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit3_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit3_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit4_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit4_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit5_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit5_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit6_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit6_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit7_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit7_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit8_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit8_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit9_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit9_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit10_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit10_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit11_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit11_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit12_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit12_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit13_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit13_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit14_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit14_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit15_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit15_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit16_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit16_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit17_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit17_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit18_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit18_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit19_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit19_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit20_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit20_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit21_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit21_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit22_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit22_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit23_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit23_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit24_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit24_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit25_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit25_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit26_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit26_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit27_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit27_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit28_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit28_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit29_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit29_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit30_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit30_MASK) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISENABLER12_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICD_GICD_ISENABLER12_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISENABLER12_set_enable_bit31_SHIFT)) & NOC_GICD_GICD_ISENABLER12_set_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER1 - GICD_ICENABLER1 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER1_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER1_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER1_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER2 - GICD_ICENABLER2 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER2_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER2_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER2_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER3 - GICD_ICENABLER3 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER3_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER3_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER3_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER4 - GICD_ICENABLER4 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER4_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER4_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER4_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER5 - GICD_ICENABLER5 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER5_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER5_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER5_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER6 - GICD_ICENABLER6 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER6_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER6_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER6_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER7 - GICD_ICENABLER7 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER7_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER7_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER7_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER8 - GICD_ICENABLER8 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER8_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER8_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER8_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER9 - GICD_ICENABLER9 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER9_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER9_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER9_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER10 - GICD_ICENABLER10 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER10_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER10_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER10_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER11 - GICD_ICENABLER11 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER11_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER11_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER11_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ICENABLER12 - GICD_ICENABLER12 */ /*! @{ */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit0_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit0_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit1_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit1_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit2_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit2_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit3_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit3_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit4_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit4_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit5_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit5_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit6_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit6_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit7_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit7_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit8_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit8_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit9_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit9_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit10_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit10_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit11_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit11_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit12_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit12_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit13_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit13_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit14_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit14_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit15_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit15_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit16_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit16_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit17_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit17_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit18_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit18_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit19_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit19_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit20_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit20_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit21_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit21_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit22_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit22_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit23_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit23_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit24_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit24_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit25_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit25_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit26_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit26_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit27_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit27_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit28_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit28_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit29_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit29_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit30_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit30_MASK) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICD_GICD_ICENABLER12_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICENABLER12_clear_enable_bit31_SHIFT)) & NOC_GICD_GICD_ICENABLER12_clear_enable_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR1 - GICD_ISPENDR1 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR1_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR1_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR1_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR1_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR2 - GICD_ISPENDR2 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR2_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR2_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR2_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR2_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR3 - GICD_ISPENDR3 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR3_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR3_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR3_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR3_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR4 - GICD_ISPENDR4 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR4_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR4_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR4_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR4_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR5 - GICD_ISPENDR5 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR5_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR5_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR5_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR5_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR6 - GICD_ISPENDR6 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR6_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR6_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR6_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR6_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR7 - GICD_ISPENDR7 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR7_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR7_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR7_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR7_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR8 - GICD_ISPENDR8 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR8_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR8_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR8_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR8_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR9 - GICD_ISPENDR9 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR9_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR9_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR9_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR9_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR10 - GICD_ISPENDR10 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR10_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR10_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR10_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR10_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR11 - GICD_ISPENDR11 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR11_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR11_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR11_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR11_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISPENDR12 - GICD_ISPENDR12 */ /*! @{ */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit0_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit0_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit1_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit1_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit2_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit2_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit3_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit3_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit4_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit4_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit5_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit5_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit6_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit6_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit7_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit7_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit8_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit8_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit9_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit9_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit10_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit10_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit11_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit11_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit12_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit12_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit13_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit13_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit14_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit14_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit15_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit15_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit16_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit16_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit17_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit17_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit18_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit18_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit19_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit19_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit20_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit20_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit21_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit21_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit22_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit22_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit23_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit23_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit24_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit24_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit25_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit25_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit26_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit26_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit27_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit27_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit28_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit28_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit29_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit29_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit30_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit30_MASK) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISPENDR12_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICD_GICD_ISPENDR12_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISPENDR12_set_pending_bit31_SHIFT)) & NOC_GICD_GICD_ISPENDR12_set_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR1 - GICD_ICPENDR1 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR1_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR1_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR1_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR2 - GICD_ICPENDR2 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR2_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR2_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR2_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR3 - GICD_ICPENDR3 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR3_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR3_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR3_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR4 - GICD_ICPENDR4 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR4_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR4_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR4_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR5 - GICD_ICPENDR5 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR5_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR5_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR5_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR6 - GICD_ICPENDR6 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR6_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR6_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR6_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR7 - GICD_ICPENDR7 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR7_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR7_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR7_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR8 - GICD_ICPENDR8 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR8_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR8_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR8_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR9 - GICD_ICPENDR9 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR9_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR9_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR9_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR10 - GICD_ICPENDR10 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR10_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR10_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR10_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR11 - GICD_ICPENDR11 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR11_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR11_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR11_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ICPENDR12 - GICD_ICPENDR12 */ /*! @{ */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit0_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit0_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit1_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit1_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit2_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit2_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit3_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit3_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit4_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit4_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit5_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit5_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit6_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit6_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit7_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit7_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit8_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit8_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit9_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit9_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit10_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit10_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit11_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit11_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit12_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit12_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit13_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit13_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit14_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit14_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit15_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit15_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit16_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit16_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit17_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit17_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit18_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit18_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit19_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit19_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit20_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit20_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit21_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit21_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit22_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit22_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit23_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit23_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit24_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit24_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit25_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit25_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit26_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit26_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit27_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit27_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit28_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit28_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit29_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit29_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit30_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit30_MASK) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICD_GICD_ICPENDR12_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICPENDR12_clear_pending_bit31_SHIFT)) & NOC_GICD_GICD_ICPENDR12_clear_pending_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER1 - GICD_ISACTIVER1 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER1_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER1_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER1_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER1_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER2 - GICD_ISACTIVER2 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER2_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER2_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER2_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER2_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER3 - GICD_ISACTIVER3 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER3_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER3_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER3_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER3_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER4 - GICD_ISACTIVER4 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER4_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER4_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER4_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER4_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER5 - GICD_ISACTIVER5 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER5_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER5_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER5_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER5_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER6 - GICD_ISACTIVER6 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER6_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER6_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER6_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER6_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER7 - GICD_ISACTIVER7 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER7_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER7_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER7_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER7_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER8 - GICD_ISACTIVER8 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER8_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER8_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER8_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER8_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER9 - GICD_ISACTIVER9 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER9_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER9_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER9_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER9_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER10 - GICD_ISACTIVER10 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER10_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER10_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER10_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER10_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER11 - GICD_ISACTIVER11 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER11_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER11_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER11_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER11_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ISACTIVER12 - GICD_ISACTIVER12 */ /*! @{ */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit0_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit0_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit1_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit1_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit2_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit2_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit3_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit3_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit4_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit4_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit5_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit5_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit6_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit6_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit7_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit7_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit8_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit8_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit9_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit9_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit10_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit10_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit11_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit11_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit12_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit12_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit13_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit13_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit14_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit14_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit15_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit15_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit16_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit16_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit17_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit17_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit18_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit18_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit19_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit19_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit20_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit20_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit21_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit21_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit22_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit22_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit23_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit23_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit24_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit24_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit25_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit25_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit26_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit26_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit27_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit27_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit28_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit28_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit29_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit29_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit30_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit30_MASK) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ISACTIVER12_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICD_GICD_ISACTIVER12_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISACTIVER12_set_active_bit31_SHIFT)) & NOC_GICD_GICD_ISACTIVER12_set_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER1 - GICD_ICACTIVER1 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER1_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER1_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER1_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER2 - GICD_ICACTIVER2 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER2_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER2_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER2_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER3 - GICD_ICACTIVER3 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER3_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER3_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER3_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER4 - GICD_ICACTIVER4 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER4_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER4_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER4_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER5 - GICD_ICACTIVER5 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER5_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER5_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER5_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER6 - GICD_ICACTIVER6 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER6_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER6_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER6_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER7 - GICD_ICACTIVER7 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER7_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER7_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER7_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER8 - GICD_ICACTIVER8 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER8_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER8_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER8_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER9 - GICD_ICACTIVER9 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER9_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER9_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER9_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER10 - GICD_ICACTIVER10 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER10_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER10_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER10_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER11 - GICD_ICACTIVER11 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER11_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER11_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER11_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_ICACTIVER12 - GICD_ICACTIVER12 */ /*! @{ */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit0_MASK (0x1U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit0_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit0_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit1_MASK (0x2U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit1_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit1_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit2_MASK (0x4U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit2_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit2_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit3_MASK (0x8U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit3_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit3_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit4_MASK (0x10U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit4_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit4_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit5_MASK (0x20U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit5_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit5_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit6_MASK (0x40U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit6_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit6_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit7_MASK (0x80U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit7_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit7_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit8_MASK (0x100U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit8_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit8_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit9_MASK (0x200U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit9_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit9_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit10_MASK (0x400U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit10_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit10_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit11_MASK (0x800U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit11_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit11_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit12_MASK (0x1000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit12_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit12_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit13_MASK (0x2000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit13_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit13_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit14_MASK (0x4000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit14_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit14_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit15_MASK (0x8000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit15_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit15_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit16_MASK (0x10000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit16_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit16_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit17_MASK (0x20000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit17_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit17_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit18_MASK (0x40000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit18_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit18_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit19_MASK (0x80000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit19_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit19_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit20_MASK (0x100000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit20_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit20_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit21_MASK (0x200000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit21_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit21_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit22_MASK (0x400000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit22_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit22_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit23_MASK (0x800000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit23_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit23_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit24_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit24_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit25_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit25_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit26_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit26_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit27_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit27_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit28_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit28_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit29_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit29_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit30_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit30_MASK) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICD_GICD_ICACTIVER12_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICACTIVER12_clear_active_bit31_SHIFT)) & NOC_GICD_GICD_ICACTIVER12_clear_active_bit31_MASK) /*! @} */ /*! @name GICD_IPRIORITYR8 - GICD_IPRIORITYR8 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR8_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR8_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR8_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR8_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR8_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR8_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR8_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR8_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR8_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR8_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR8_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR8_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR8_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR8_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR8_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR8_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR8_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR8_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR8_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR8_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR9 - GICD_IPRIORITYR9 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR9_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR9_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR9_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR9_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR9_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR9_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR9_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR9_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR9_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR9_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR9_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR9_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR9_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR9_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR9_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR9_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR9_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR9_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR9_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR9_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR10 - GICD_IPRIORITYR10 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR10_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR10_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR10_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR10_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR10_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR10_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR10_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR10_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR10_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR10_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR10_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR10_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR10_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR10_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR10_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR10_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR10_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR10_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR10_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR10_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR11 - GICD_IPRIORITYR11 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR11_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR11_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR11_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR11_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR11_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR11_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR11_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR11_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR11_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR11_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR11_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR11_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR11_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR11_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR11_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR11_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR11_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR11_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR11_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR11_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR12 - GICD_IPRIORITYR12 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR12_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR12_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR12_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR12_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR12_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR12_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR12_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR12_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR12_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR12_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR12_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR12_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR12_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR12_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR12_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR12_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR12_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR12_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR12_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR12_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR13 - GICD_IPRIORITYR13 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR13_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR13_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR13_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR13_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR13_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR13_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR13_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR13_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR13_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR13_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR13_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR13_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR13_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR13_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR13_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR13_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR13_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR13_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR13_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR13_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR14 - GICD_IPRIORITYR14 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR14_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR14_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR14_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR14_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR14_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR14_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR14_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR14_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR14_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR14_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR14_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR14_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR14_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR14_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR14_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR14_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR14_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR14_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR14_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR14_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR15 - GICD_IPRIORITYR15 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR15_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR15_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR15_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR15_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR15_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR15_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR15_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR15_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR15_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR15_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR15_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR15_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR15_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR15_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR15_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR15_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR15_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR15_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR15_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR15_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR16 - GICD_IPRIORITYR16 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR16_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR16_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR16_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR16_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR16_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR16_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR16_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR16_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR16_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR16_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR16_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR16_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR16_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR16_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR16_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR16_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR16_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR16_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR16_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR16_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR17 - GICD_IPRIORITYR17 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR17_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR17_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR17_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR17_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR17_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR17_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR17_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR17_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR17_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR17_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR17_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR17_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR17_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR17_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR17_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR17_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR17_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR17_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR17_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR17_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR18 - GICD_IPRIORITYR18 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR18_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR18_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR18_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR18_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR18_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR18_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR18_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR18_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR18_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR18_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR18_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR18_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR18_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR18_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR18_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR18_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR18_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR18_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR18_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR18_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR19 - GICD_IPRIORITYR19 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR19_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR19_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR19_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR19_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR19_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR19_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR19_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR19_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR19_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR19_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR19_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR19_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR19_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR19_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR19_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR19_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR19_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR19_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR19_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR19_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR20 - GICD_IPRIORITYR20 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR20_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR20_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR20_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR20_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR20_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR20_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR20_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR20_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR20_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR20_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR20_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR20_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR20_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR20_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR20_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR20_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR20_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR20_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR20_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR20_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR21 - GICD_IPRIORITYR21 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR21_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR21_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR21_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR21_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR21_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR21_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR21_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR21_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR21_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR21_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR21_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR21_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR21_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR21_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR21_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR21_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR21_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR21_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR21_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR21_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR22 - GICD_IPRIORITYR22 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR22_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR22_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR22_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR22_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR22_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR22_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR22_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR22_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR22_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR22_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR22_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR22_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR22_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR22_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR22_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR22_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR22_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR22_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR22_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR22_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR23 - GICD_IPRIORITYR23 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR23_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR23_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR23_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR23_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR23_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR23_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR23_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR23_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR23_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR23_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR23_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR23_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR23_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR23_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR23_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR23_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR23_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR23_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR23_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR23_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR24 - GICD_IPRIORITYR24 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR24_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR24_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR24_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR24_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR24_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR24_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR24_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR24_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR24_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR24_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR24_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR24_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR24_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR24_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR24_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR24_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR24_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR24_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR24_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR24_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR25 - GICD_IPRIORITYR25 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR25_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR25_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR25_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR25_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR25_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR25_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR25_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR25_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR25_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR25_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR25_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR25_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR25_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR25_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR25_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR25_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR25_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR25_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR25_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR25_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR26 - GICD_IPRIORITYR26 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR26_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR26_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR26_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR26_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR26_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR26_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR26_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR26_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR26_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR26_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR26_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR26_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR26_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR26_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR26_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR26_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR26_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR26_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR26_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR26_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR27 - GICD_IPRIORITYR27 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR27_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR27_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR27_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR27_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR27_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR27_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR27_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR27_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR27_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR27_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR27_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR27_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR27_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR27_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR27_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR27_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR27_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR27_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR27_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR27_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR28 - GICD_IPRIORITYR28 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR28_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR28_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR28_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR28_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR28_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR28_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR28_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR28_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR28_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR28_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR28_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR28_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR28_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR28_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR28_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR28_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR28_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR28_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR28_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR28_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR29 - GICD_IPRIORITYR29 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR29_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR29_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR29_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR29_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR29_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR29_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR29_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR29_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR29_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR29_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR29_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR29_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR29_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR29_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR29_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR29_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR29_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR29_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR29_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR29_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR30 - GICD_IPRIORITYR30 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR30_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR30_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR30_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR30_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR30_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR30_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR30_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR30_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR30_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR30_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR30_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR30_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR30_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR30_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR30_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR30_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR30_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR30_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR30_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR30_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR31 - GICD_IPRIORITYR31 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR31_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR31_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR31_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR31_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR31_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR31_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR31_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR31_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR31_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR31_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR31_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR31_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR31_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR31_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR31_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR31_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR31_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR31_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR31_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR31_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR32 - GICD_IPRIORITYR32 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR32_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR32_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR32_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR32_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR32_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR32_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR32_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR32_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR32_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR32_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR32_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR32_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR32_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR32_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR32_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR32_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR32_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR32_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR32_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR32_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR33 - GICD_IPRIORITYR33 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR33_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR33_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR33_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR33_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR33_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR33_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR33_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR33_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR33_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR33_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR33_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR33_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR33_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR33_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR33_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR33_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR33_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR33_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR33_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR33_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR34 - GICD_IPRIORITYR34 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR34_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR34_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR34_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR34_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR34_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR34_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR34_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR34_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR34_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR34_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR34_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR34_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR34_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR34_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR34_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR34_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR34_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR34_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR34_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR34_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR35 - GICD_IPRIORITYR35 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR35_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR35_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR35_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR35_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR35_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR35_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR35_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR35_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR35_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR35_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR35_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR35_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR35_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR35_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR35_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR35_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR35_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR35_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR35_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR35_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR36 - GICD_IPRIORITYR36 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR36_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR36_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR36_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR36_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR36_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR36_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR36_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR36_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR36_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR36_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR36_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR36_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR36_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR36_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR36_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR36_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR36_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR36_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR36_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR36_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR37 - GICD_IPRIORITYR37 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR37_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR37_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR37_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR37_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR37_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR37_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR37_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR37_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR37_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR37_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR37_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR37_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR37_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR37_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR37_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR37_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR37_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR37_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR37_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR37_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR38 - GICD_IPRIORITYR38 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR38_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR38_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR38_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR38_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR38_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR38_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR38_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR38_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR38_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR38_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR38_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR38_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR38_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR38_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR38_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR38_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR38_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR38_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR38_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR38_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR39 - GICD_IPRIORITYR39 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR39_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR39_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR39_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR39_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR39_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR39_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR39_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR39_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR39_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR39_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR39_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR39_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR39_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR39_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR39_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR39_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR39_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR39_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR39_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR39_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR40 - GICD_IPRIORITYR40 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR40_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR40_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR40_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR40_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR40_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR40_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR40_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR40_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR40_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR40_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR40_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR40_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR40_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR40_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR40_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR40_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR40_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR40_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR40_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR40_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR41 - GICD_IPRIORITYR41 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR41_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR41_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR41_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR41_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR41_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR41_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR41_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR41_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR41_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR41_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR41_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR41_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR41_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR41_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR41_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR41_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR41_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR41_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR41_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR41_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR42 - GICD_IPRIORITYR42 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR42_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR42_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR42_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR42_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR42_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR42_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR42_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR42_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR42_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR42_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR42_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR42_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR42_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR42_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR42_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR42_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR42_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR42_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR42_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR42_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR43 - GICD_IPRIORITYR43 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR43_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR43_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR43_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR43_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR43_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR43_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR43_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR43_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR43_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR43_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR43_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR43_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR43_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR43_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR43_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR43_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR43_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR43_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR43_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR43_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR44 - GICD_IPRIORITYR44 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR44_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR44_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR44_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR44_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR44_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR44_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR44_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR44_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR44_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR44_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR44_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR44_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR44_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR44_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR44_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR44_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR44_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR44_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR44_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR44_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR45 - GICD_IPRIORITYR45 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR45_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR45_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR45_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR45_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR45_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR45_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR45_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR45_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR45_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR45_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR45_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR45_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR45_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR45_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR45_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR45_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR45_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR45_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR45_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR45_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR46 - GICD_IPRIORITYR46 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR46_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR46_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR46_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR46_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR46_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR46_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR46_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR46_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR46_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR46_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR46_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR46_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR46_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR46_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR46_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR46_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR46_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR46_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR46_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR46_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR47 - GICD_IPRIORITYR47 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR47_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR47_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR47_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR47_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR47_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR47_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR47_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR47_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR47_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR47_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR47_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR47_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR47_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR47_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR47_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR47_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR47_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR47_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR47_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR47_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR48 - GICD_IPRIORITYR48 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR48_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR48_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR48_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR48_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR48_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR48_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR48_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR48_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR48_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR48_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR48_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR48_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR48_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR48_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR48_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR48_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR48_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR48_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR48_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR48_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR49 - GICD_IPRIORITYR49 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR49_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR49_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR49_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR49_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR49_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR49_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR49_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR49_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR49_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR49_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR49_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR49_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR49_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR49_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR49_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR49_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR49_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR49_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR49_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR49_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR50 - GICD_IPRIORITYR50 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR50_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR50_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR50_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR50_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR50_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR50_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR50_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR50_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR50_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR50_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR50_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR50_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR50_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR50_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR50_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR50_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR50_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR50_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR50_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR50_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR51 - GICD_IPRIORITYR51 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR51_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR51_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR51_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR51_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR51_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR51_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR51_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR51_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR51_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR51_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR51_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR51_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR51_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR51_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR51_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR51_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR51_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR51_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR51_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR51_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR52 - GICD_IPRIORITYR52 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR52_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR52_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR52_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR52_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR52_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR52_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR52_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR52_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR52_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR52_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR52_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR52_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR52_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR52_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR52_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR52_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR52_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR52_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR52_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR52_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR53 - GICD_IPRIORITYR53 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR53_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR53_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR53_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR53_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR53_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR53_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR53_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR53_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR53_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR53_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR53_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR53_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR53_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR53_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR53_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR53_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR53_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR53_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR53_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR53_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR54 - GICD_IPRIORITYR54 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR54_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR54_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR54_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR54_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR54_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR54_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR54_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR54_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR54_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR54_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR54_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR54_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR54_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR54_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR54_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR54_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR54_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR54_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR54_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR54_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR55 - GICD_IPRIORITYR55 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR55_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR55_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR55_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR55_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR55_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR55_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR55_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR55_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR55_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR55_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR55_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR55_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR55_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR55_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR55_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR55_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR55_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR55_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR55_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR55_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR56 - GICD_IPRIORITYR56 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR56_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR56_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR56_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR56_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR56_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR56_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR56_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR56_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR56_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR56_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR56_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR56_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR56_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR56_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR56_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR56_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR56_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR56_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR56_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR56_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR57 - GICD_IPRIORITYR57 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR57_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR57_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR57_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR57_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR57_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR57_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR57_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR57_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR57_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR57_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR57_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR57_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR57_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR57_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR57_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR57_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR57_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR57_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR57_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR57_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR58 - GICD_IPRIORITYR58 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR58_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR58_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR58_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR58_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR58_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR58_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR58_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR58_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR58_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR58_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR58_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR58_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR58_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR58_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR58_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR58_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR58_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR58_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR58_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR58_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR59 - GICD_IPRIORITYR59 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR59_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR59_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR59_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR59_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR59_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR59_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR59_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR59_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR59_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR59_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR59_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR59_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR59_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR59_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR59_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR59_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR59_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR59_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR59_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR59_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR60 - GICD_IPRIORITYR60 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR60_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR60_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR60_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR60_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR60_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR60_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR60_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR60_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR60_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR60_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR60_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR60_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR60_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR60_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR60_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR60_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR60_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR60_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR60_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR60_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR61 - GICD_IPRIORITYR61 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR61_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR61_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR61_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR61_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR61_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR61_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR61_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR61_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR61_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR61_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR61_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR61_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR61_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR61_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR61_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR61_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR61_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR61_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR61_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR61_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR62 - GICD_IPRIORITYR62 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR62_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR62_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR62_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR62_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR62_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR62_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR62_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR62_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR62_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR62_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR62_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR62_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR62_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR62_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR62_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR62_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR62_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR62_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR62_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR62_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR63 - GICD_IPRIORITYR63 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR63_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR63_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR63_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR63_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR63_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR63_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR63_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR63_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR63_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR63_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR63_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR63_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR63_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR63_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR63_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR63_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR63_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR63_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR63_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR63_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR64 - GICD_IPRIORITYR64 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR64_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR64_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR64_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR64_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR64_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR64_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR64_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR64_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR64_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR64_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR64_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR64_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR64_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR64_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR64_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR64_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR64_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR64_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR64_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR64_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR65 - GICD_IPRIORITYR65 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR65_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR65_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR65_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR65_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR65_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR65_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR65_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR65_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR65_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR65_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR65_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR65_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR65_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR65_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR65_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR65_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR65_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR65_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR65_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR65_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR66 - GICD_IPRIORITYR66 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR66_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR66_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR66_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR66_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR66_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR66_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR66_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR66_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR66_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR66_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR66_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR66_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR66_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR66_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR66_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR66_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR66_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR66_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR66_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR66_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR67 - GICD_IPRIORITYR67 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR67_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR67_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR67_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR67_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR67_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR67_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR67_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR67_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR67_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR67_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR67_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR67_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR67_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR67_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR67_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR67_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR67_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR67_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR67_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR67_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR68 - GICD_IPRIORITYR68 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR68_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR68_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR68_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR68_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR68_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR68_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR68_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR68_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR68_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR68_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR68_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR68_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR68_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR68_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR68_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR68_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR68_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR68_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR68_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR68_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR69 - GICD_IPRIORITYR69 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR69_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR69_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR69_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR69_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR69_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR69_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR69_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR69_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR69_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR69_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR69_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR69_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR69_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR69_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR69_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR69_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR69_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR69_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR69_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR69_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR70 - GICD_IPRIORITYR70 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR70_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR70_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR70_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR70_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR70_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR70_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR70_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR70_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR70_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR70_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR70_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR70_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR70_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR70_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR70_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR70_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR70_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR70_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR70_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR70_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR71 - GICD_IPRIORITYR71 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR71_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR71_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR71_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR71_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR71_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR71_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR71_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR71_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR71_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR71_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR71_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR71_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR71_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR71_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR71_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR71_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR71_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR71_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR71_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR71_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR72 - GICD_IPRIORITYR72 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR72_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR72_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR72_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR72_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR72_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR72_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR72_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR72_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR72_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR72_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR72_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR72_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR72_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR72_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR72_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR72_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR72_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR72_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR72_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR72_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR73 - GICD_IPRIORITYR73 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR73_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR73_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR73_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR73_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR73_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR73_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR73_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR73_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR73_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR73_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR73_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR73_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR73_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR73_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR73_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR73_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR73_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR73_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR73_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR73_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR74 - GICD_IPRIORITYR74 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR74_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR74_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR74_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR74_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR74_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR74_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR74_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR74_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR74_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR74_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR74_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR74_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR74_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR74_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR74_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR74_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR74_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR74_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR74_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR74_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR75 - GICD_IPRIORITYR75 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR75_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR75_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR75_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR75_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR75_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR75_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR75_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR75_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR75_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR75_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR75_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR75_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR75_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR75_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR75_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR75_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR75_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR75_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR75_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR75_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR76 - GICD_IPRIORITYR76 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR76_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR76_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR76_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR76_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR76_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR76_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR76_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR76_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR76_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR76_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR76_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR76_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR76_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR76_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR76_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR76_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR76_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR76_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR76_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR76_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR77 - GICD_IPRIORITYR77 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR77_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR77_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR77_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR77_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR77_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR77_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR77_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR77_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR77_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR77_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR77_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR77_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR77_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR77_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR77_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR77_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR77_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR77_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR77_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR77_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR78 - GICD_IPRIORITYR78 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR78_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR78_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR78_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR78_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR78_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR78_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR78_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR78_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR78_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR78_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR78_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR78_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR78_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR78_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR78_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR78_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR78_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR78_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR78_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR78_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR79 - GICD_IPRIORITYR79 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR79_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR79_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR79_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR79_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR79_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR79_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR79_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR79_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR79_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR79_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR79_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR79_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR79_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR79_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR79_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR79_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR79_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR79_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR79_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR79_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR80 - GICD_IPRIORITYR80 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR80_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR80_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR80_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR80_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR80_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR80_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR80_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR80_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR80_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR80_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR80_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR80_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR80_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR80_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR80_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR80_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR80_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR80_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR80_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR80_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR81 - GICD_IPRIORITYR81 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR81_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR81_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR81_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR81_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR81_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR81_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR81_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR81_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR81_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR81_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR81_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR81_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR81_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR81_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR81_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR81_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR81_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR81_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR81_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR81_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR82 - GICD_IPRIORITYR82 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR82_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR82_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR82_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR82_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR82_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR82_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR82_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR82_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR82_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR82_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR82_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR82_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR82_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR82_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR82_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR82_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR82_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR82_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR82_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR82_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR83 - GICD_IPRIORITYR83 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR83_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR83_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR83_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR83_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR83_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR83_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR83_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR83_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR83_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR83_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR83_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR83_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR83_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR83_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR83_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR83_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR83_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR83_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR83_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR83_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR84 - GICD_IPRIORITYR84 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR84_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR84_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR84_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR84_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR84_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR84_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR84_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR84_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR84_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR84_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR84_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR84_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR84_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR84_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR84_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR84_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR84_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR84_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR84_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR84_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR85 - GICD_IPRIORITYR85 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR85_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR85_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR85_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR85_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR85_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR85_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR85_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR85_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR85_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR85_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR85_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR85_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR85_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR85_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR85_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR85_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR85_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR85_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR85_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR85_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR86 - GICD_IPRIORITYR86 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR86_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR86_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR86_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR86_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR86_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR86_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR86_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR86_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR86_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR86_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR86_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR86_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR86_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR86_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR86_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR86_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR86_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR86_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR86_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR86_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR87 - GICD_IPRIORITYR87 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR87_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR87_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR87_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR87_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR87_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR87_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR87_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR87_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR87_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR87_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR87_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR87_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR87_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR87_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR87_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR87_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR87_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR87_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR87_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR87_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR88 - GICD_IPRIORITYR88 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR88_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR88_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR88_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR88_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR88_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR88_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR88_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR88_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR88_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR88_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR88_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR88_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR88_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR88_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR88_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR88_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR88_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR88_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR88_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR88_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR89 - GICD_IPRIORITYR89 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR89_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR89_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR89_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR89_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR89_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR89_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR89_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR89_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR89_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR89_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR89_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR89_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR89_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR89_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR89_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR89_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR89_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR89_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR89_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR89_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR90 - GICD_IPRIORITYR90 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR90_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR90_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR90_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR90_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR90_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR90_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR90_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR90_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR90_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR90_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR90_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR90_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR90_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR90_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR90_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR90_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR90_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR90_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR90_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR90_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR91 - GICD_IPRIORITYR91 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR91_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR91_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR91_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR91_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR91_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR91_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR91_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR91_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR91_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR91_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR91_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR91_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR91_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR91_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR91_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR91_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR91_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR91_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR91_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR91_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR92 - GICD_IPRIORITYR92 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR92_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR92_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR92_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR92_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR92_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR92_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR92_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR92_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR92_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR92_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR92_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR92_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR92_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR92_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR92_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR92_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR92_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR92_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR92_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR92_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR93 - GICD_IPRIORITYR93 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR93_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR93_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR93_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR93_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR93_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR93_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR93_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR93_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR93_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR93_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR93_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR93_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR93_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR93_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR93_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR93_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR93_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR93_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR93_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR93_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR94 - GICD_IPRIORITYR94 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR94_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR94_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR94_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR94_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR94_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR94_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR94_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR94_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR94_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR94_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR94_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR94_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR94_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR94_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR94_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR94_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR94_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR94_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR94_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR94_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR95 - GICD_IPRIORITYR95 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR95_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR95_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR95_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR95_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR95_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR95_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR95_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR95_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR95_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR95_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR95_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR95_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR95_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR95_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR95_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR95_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR95_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR95_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR95_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR95_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR96 - GICD_IPRIORITYR96 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR96_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR96_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR96_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR96_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR96_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR96_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR96_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR96_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR96_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR96_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR96_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR96_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR96_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR96_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR96_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR96_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR96_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR96_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR96_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR96_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR97 - GICD_IPRIORITYR97 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR97_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR97_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR97_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR97_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR97_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR97_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR97_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR97_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR97_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR97_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR97_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR97_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR97_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR97_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR97_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR97_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR97_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR97_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR97_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR97_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR98 - GICD_IPRIORITYR98 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR98_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR98_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR98_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR98_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR98_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR98_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR98_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR98_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR98_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR98_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR98_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR98_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR98_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR98_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR98_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR98_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR98_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR98_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR98_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR98_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR99 - GICD_IPRIORITYR99 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR99_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR99_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR99_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR99_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR99_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR99_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR99_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR99_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR99_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR99_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR99_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR99_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR99_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR99_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR99_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR99_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR99_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR99_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR99_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR99_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR100 - GICD_IPRIORITYR100 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR100_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR100_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR100_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR100_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR100_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR100_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR100_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR100_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR100_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR100_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR100_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR100_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR100_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR100_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR100_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR100_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR100_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR100_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR100_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR100_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR101 - GICD_IPRIORITYR101 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR101_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR101_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR101_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR101_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR101_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR101_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR101_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR101_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR101_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR101_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR101_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR101_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR101_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR101_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR101_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR101_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR101_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR101_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR101_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR101_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR102 - GICD_IPRIORITYR102 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR102_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR102_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR102_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR102_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR102_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR102_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR102_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR102_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR102_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR102_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR102_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR102_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR102_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR102_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR102_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR102_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR102_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR102_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR102_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR102_offset3_MASK) /*! @} */ /*! @name GICD_IPRIORITYR103 - GICD_IPRIORITYR103 */ /*! @{ */ #define NOC_GICD_GICD_IPRIORITYR103_offset0_MASK (0xFFU) #define NOC_GICD_GICD_IPRIORITYR103_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR103_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR103_offset0_SHIFT)) & NOC_GICD_GICD_IPRIORITYR103_offset0_MASK) #define NOC_GICD_GICD_IPRIORITYR103_offset1_MASK (0xFF00U) #define NOC_GICD_GICD_IPRIORITYR103_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR103_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR103_offset1_SHIFT)) & NOC_GICD_GICD_IPRIORITYR103_offset1_MASK) #define NOC_GICD_GICD_IPRIORITYR103_offset2_MASK (0xFF0000U) #define NOC_GICD_GICD_IPRIORITYR103_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR103_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR103_offset2_SHIFT)) & NOC_GICD_GICD_IPRIORITYR103_offset2_MASK) #define NOC_GICD_GICD_IPRIORITYR103_offset3_MASK (0xFF000000U) #define NOC_GICD_GICD_IPRIORITYR103_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICD_GICD_IPRIORITYR103_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IPRIORITYR103_offset3_SHIFT)) & NOC_GICD_GICD_IPRIORITYR103_offset3_MASK) /*! @} */ /*! @name GICD_ICFGR2 - GICD_ICFGR2 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR2_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR2_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config0_MASK) #define NOC_GICD_GICD_ICFGR2_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR2_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config1_MASK) #define NOC_GICD_GICD_ICFGR2_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR2_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config2_MASK) #define NOC_GICD_GICD_ICFGR2_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR2_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config3_MASK) #define NOC_GICD_GICD_ICFGR2_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR2_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config4_MASK) #define NOC_GICD_GICD_ICFGR2_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR2_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config5_MASK) #define NOC_GICD_GICD_ICFGR2_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR2_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config6_MASK) #define NOC_GICD_GICD_ICFGR2_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR2_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config7_MASK) #define NOC_GICD_GICD_ICFGR2_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR2_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config8_MASK) #define NOC_GICD_GICD_ICFGR2_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR2_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config9_MASK) #define NOC_GICD_GICD_ICFGR2_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR2_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config10_MASK) #define NOC_GICD_GICD_ICFGR2_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR2_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config11_MASK) #define NOC_GICD_GICD_ICFGR2_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR2_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config12_MASK) #define NOC_GICD_GICD_ICFGR2_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR2_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config13_MASK) #define NOC_GICD_GICD_ICFGR2_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR2_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config14_MASK) #define NOC_GICD_GICD_ICFGR2_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR2_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR2_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR2_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR2_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR3 - GICD_ICFGR3 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR3_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR3_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config0_MASK) #define NOC_GICD_GICD_ICFGR3_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR3_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config1_MASK) #define NOC_GICD_GICD_ICFGR3_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR3_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config2_MASK) #define NOC_GICD_GICD_ICFGR3_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR3_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config3_MASK) #define NOC_GICD_GICD_ICFGR3_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR3_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config4_MASK) #define NOC_GICD_GICD_ICFGR3_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR3_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config5_MASK) #define NOC_GICD_GICD_ICFGR3_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR3_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config6_MASK) #define NOC_GICD_GICD_ICFGR3_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR3_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config7_MASK) #define NOC_GICD_GICD_ICFGR3_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR3_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config8_MASK) #define NOC_GICD_GICD_ICFGR3_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR3_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config9_MASK) #define NOC_GICD_GICD_ICFGR3_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR3_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config10_MASK) #define NOC_GICD_GICD_ICFGR3_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR3_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config11_MASK) #define NOC_GICD_GICD_ICFGR3_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR3_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config12_MASK) #define NOC_GICD_GICD_ICFGR3_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR3_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config13_MASK) #define NOC_GICD_GICD_ICFGR3_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR3_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config14_MASK) #define NOC_GICD_GICD_ICFGR3_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR3_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR3_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR3_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR3_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR4 - GICD_ICFGR4 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR4_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR4_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config0_MASK) #define NOC_GICD_GICD_ICFGR4_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR4_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config1_MASK) #define NOC_GICD_GICD_ICFGR4_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR4_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config2_MASK) #define NOC_GICD_GICD_ICFGR4_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR4_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config3_MASK) #define NOC_GICD_GICD_ICFGR4_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR4_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config4_MASK) #define NOC_GICD_GICD_ICFGR4_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR4_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config5_MASK) #define NOC_GICD_GICD_ICFGR4_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR4_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config6_MASK) #define NOC_GICD_GICD_ICFGR4_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR4_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config7_MASK) #define NOC_GICD_GICD_ICFGR4_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR4_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config8_MASK) #define NOC_GICD_GICD_ICFGR4_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR4_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config9_MASK) #define NOC_GICD_GICD_ICFGR4_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR4_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config10_MASK) #define NOC_GICD_GICD_ICFGR4_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR4_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config11_MASK) #define NOC_GICD_GICD_ICFGR4_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR4_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config12_MASK) #define NOC_GICD_GICD_ICFGR4_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR4_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config13_MASK) #define NOC_GICD_GICD_ICFGR4_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR4_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config14_MASK) #define NOC_GICD_GICD_ICFGR4_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR4_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR4_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR4_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR4_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR5 - GICD_ICFGR5 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR5_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR5_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config0_MASK) #define NOC_GICD_GICD_ICFGR5_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR5_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config1_MASK) #define NOC_GICD_GICD_ICFGR5_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR5_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config2_MASK) #define NOC_GICD_GICD_ICFGR5_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR5_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config3_MASK) #define NOC_GICD_GICD_ICFGR5_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR5_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config4_MASK) #define NOC_GICD_GICD_ICFGR5_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR5_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config5_MASK) #define NOC_GICD_GICD_ICFGR5_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR5_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config6_MASK) #define NOC_GICD_GICD_ICFGR5_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR5_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config7_MASK) #define NOC_GICD_GICD_ICFGR5_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR5_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config8_MASK) #define NOC_GICD_GICD_ICFGR5_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR5_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config9_MASK) #define NOC_GICD_GICD_ICFGR5_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR5_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config10_MASK) #define NOC_GICD_GICD_ICFGR5_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR5_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config11_MASK) #define NOC_GICD_GICD_ICFGR5_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR5_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config12_MASK) #define NOC_GICD_GICD_ICFGR5_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR5_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config13_MASK) #define NOC_GICD_GICD_ICFGR5_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR5_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config14_MASK) #define NOC_GICD_GICD_ICFGR5_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR5_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR5_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR5_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR5_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR6 - GICD_ICFGR6 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR6_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR6_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config0_MASK) #define NOC_GICD_GICD_ICFGR6_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR6_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config1_MASK) #define NOC_GICD_GICD_ICFGR6_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR6_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config2_MASK) #define NOC_GICD_GICD_ICFGR6_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR6_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config3_MASK) #define NOC_GICD_GICD_ICFGR6_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR6_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config4_MASK) #define NOC_GICD_GICD_ICFGR6_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR6_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config5_MASK) #define NOC_GICD_GICD_ICFGR6_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR6_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config6_MASK) #define NOC_GICD_GICD_ICFGR6_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR6_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config7_MASK) #define NOC_GICD_GICD_ICFGR6_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR6_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config8_MASK) #define NOC_GICD_GICD_ICFGR6_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR6_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config9_MASK) #define NOC_GICD_GICD_ICFGR6_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR6_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config10_MASK) #define NOC_GICD_GICD_ICFGR6_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR6_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config11_MASK) #define NOC_GICD_GICD_ICFGR6_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR6_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config12_MASK) #define NOC_GICD_GICD_ICFGR6_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR6_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config13_MASK) #define NOC_GICD_GICD_ICFGR6_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR6_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config14_MASK) #define NOC_GICD_GICD_ICFGR6_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR6_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR6_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR6_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR6_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR7 - GICD_ICFGR7 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR7_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR7_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config0_MASK) #define NOC_GICD_GICD_ICFGR7_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR7_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config1_MASK) #define NOC_GICD_GICD_ICFGR7_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR7_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config2_MASK) #define NOC_GICD_GICD_ICFGR7_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR7_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config3_MASK) #define NOC_GICD_GICD_ICFGR7_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR7_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config4_MASK) #define NOC_GICD_GICD_ICFGR7_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR7_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config5_MASK) #define NOC_GICD_GICD_ICFGR7_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR7_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config6_MASK) #define NOC_GICD_GICD_ICFGR7_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR7_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config7_MASK) #define NOC_GICD_GICD_ICFGR7_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR7_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config8_MASK) #define NOC_GICD_GICD_ICFGR7_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR7_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config9_MASK) #define NOC_GICD_GICD_ICFGR7_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR7_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config10_MASK) #define NOC_GICD_GICD_ICFGR7_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR7_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config11_MASK) #define NOC_GICD_GICD_ICFGR7_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR7_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config12_MASK) #define NOC_GICD_GICD_ICFGR7_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR7_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config13_MASK) #define NOC_GICD_GICD_ICFGR7_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR7_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config14_MASK) #define NOC_GICD_GICD_ICFGR7_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR7_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR7_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR7_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR7_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR8 - GICD_ICFGR8 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR8_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR8_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config0_MASK) #define NOC_GICD_GICD_ICFGR8_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR8_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config1_MASK) #define NOC_GICD_GICD_ICFGR8_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR8_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config2_MASK) #define NOC_GICD_GICD_ICFGR8_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR8_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config3_MASK) #define NOC_GICD_GICD_ICFGR8_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR8_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config4_MASK) #define NOC_GICD_GICD_ICFGR8_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR8_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config5_MASK) #define NOC_GICD_GICD_ICFGR8_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR8_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config6_MASK) #define NOC_GICD_GICD_ICFGR8_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR8_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config7_MASK) #define NOC_GICD_GICD_ICFGR8_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR8_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config8_MASK) #define NOC_GICD_GICD_ICFGR8_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR8_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config9_MASK) #define NOC_GICD_GICD_ICFGR8_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR8_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config10_MASK) #define NOC_GICD_GICD_ICFGR8_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR8_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config11_MASK) #define NOC_GICD_GICD_ICFGR8_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR8_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config12_MASK) #define NOC_GICD_GICD_ICFGR8_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR8_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config13_MASK) #define NOC_GICD_GICD_ICFGR8_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR8_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config14_MASK) #define NOC_GICD_GICD_ICFGR8_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR8_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR8_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR8_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR8_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR9 - GICD_ICFGR9 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR9_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR9_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config0_MASK) #define NOC_GICD_GICD_ICFGR9_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR9_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config1_MASK) #define NOC_GICD_GICD_ICFGR9_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR9_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config2_MASK) #define NOC_GICD_GICD_ICFGR9_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR9_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config3_MASK) #define NOC_GICD_GICD_ICFGR9_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR9_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config4_MASK) #define NOC_GICD_GICD_ICFGR9_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR9_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config5_MASK) #define NOC_GICD_GICD_ICFGR9_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR9_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config6_MASK) #define NOC_GICD_GICD_ICFGR9_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR9_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config7_MASK) #define NOC_GICD_GICD_ICFGR9_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR9_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config8_MASK) #define NOC_GICD_GICD_ICFGR9_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR9_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config9_MASK) #define NOC_GICD_GICD_ICFGR9_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR9_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config10_MASK) #define NOC_GICD_GICD_ICFGR9_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR9_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config11_MASK) #define NOC_GICD_GICD_ICFGR9_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR9_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config12_MASK) #define NOC_GICD_GICD_ICFGR9_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR9_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config13_MASK) #define NOC_GICD_GICD_ICFGR9_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR9_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config14_MASK) #define NOC_GICD_GICD_ICFGR9_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR9_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR9_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR9_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR9_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR10 - GICD_ICFGR10 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR10_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR10_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config0_MASK) #define NOC_GICD_GICD_ICFGR10_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR10_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config1_MASK) #define NOC_GICD_GICD_ICFGR10_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR10_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config2_MASK) #define NOC_GICD_GICD_ICFGR10_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR10_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config3_MASK) #define NOC_GICD_GICD_ICFGR10_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR10_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config4_MASK) #define NOC_GICD_GICD_ICFGR10_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR10_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config5_MASK) #define NOC_GICD_GICD_ICFGR10_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR10_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config6_MASK) #define NOC_GICD_GICD_ICFGR10_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR10_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config7_MASK) #define NOC_GICD_GICD_ICFGR10_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR10_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config8_MASK) #define NOC_GICD_GICD_ICFGR10_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR10_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config9_MASK) #define NOC_GICD_GICD_ICFGR10_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR10_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config10_MASK) #define NOC_GICD_GICD_ICFGR10_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR10_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config11_MASK) #define NOC_GICD_GICD_ICFGR10_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR10_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config12_MASK) #define NOC_GICD_GICD_ICFGR10_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR10_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config13_MASK) #define NOC_GICD_GICD_ICFGR10_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR10_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config14_MASK) #define NOC_GICD_GICD_ICFGR10_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR10_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR10_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR10_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR10_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR11 - GICD_ICFGR11 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR11_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR11_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config0_MASK) #define NOC_GICD_GICD_ICFGR11_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR11_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config1_MASK) #define NOC_GICD_GICD_ICFGR11_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR11_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config2_MASK) #define NOC_GICD_GICD_ICFGR11_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR11_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config3_MASK) #define NOC_GICD_GICD_ICFGR11_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR11_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config4_MASK) #define NOC_GICD_GICD_ICFGR11_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR11_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config5_MASK) #define NOC_GICD_GICD_ICFGR11_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR11_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config6_MASK) #define NOC_GICD_GICD_ICFGR11_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR11_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config7_MASK) #define NOC_GICD_GICD_ICFGR11_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR11_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config8_MASK) #define NOC_GICD_GICD_ICFGR11_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR11_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config9_MASK) #define NOC_GICD_GICD_ICFGR11_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR11_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config10_MASK) #define NOC_GICD_GICD_ICFGR11_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR11_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config11_MASK) #define NOC_GICD_GICD_ICFGR11_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR11_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config12_MASK) #define NOC_GICD_GICD_ICFGR11_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR11_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config13_MASK) #define NOC_GICD_GICD_ICFGR11_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR11_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config14_MASK) #define NOC_GICD_GICD_ICFGR11_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR11_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR11_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR11_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR11_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR12 - GICD_ICFGR12 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR12_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR12_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config0_MASK) #define NOC_GICD_GICD_ICFGR12_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR12_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config1_MASK) #define NOC_GICD_GICD_ICFGR12_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR12_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config2_MASK) #define NOC_GICD_GICD_ICFGR12_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR12_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config3_MASK) #define NOC_GICD_GICD_ICFGR12_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR12_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config4_MASK) #define NOC_GICD_GICD_ICFGR12_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR12_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config5_MASK) #define NOC_GICD_GICD_ICFGR12_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR12_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config6_MASK) #define NOC_GICD_GICD_ICFGR12_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR12_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config7_MASK) #define NOC_GICD_GICD_ICFGR12_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR12_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config8_MASK) #define NOC_GICD_GICD_ICFGR12_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR12_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config9_MASK) #define NOC_GICD_GICD_ICFGR12_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR12_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config10_MASK) #define NOC_GICD_GICD_ICFGR12_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR12_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config11_MASK) #define NOC_GICD_GICD_ICFGR12_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR12_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config12_MASK) #define NOC_GICD_GICD_ICFGR12_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR12_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config13_MASK) #define NOC_GICD_GICD_ICFGR12_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR12_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config14_MASK) #define NOC_GICD_GICD_ICFGR12_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR12_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR12_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR12_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR12_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR13 - GICD_ICFGR13 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR13_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR13_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config0_MASK) #define NOC_GICD_GICD_ICFGR13_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR13_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config1_MASK) #define NOC_GICD_GICD_ICFGR13_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR13_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config2_MASK) #define NOC_GICD_GICD_ICFGR13_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR13_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config3_MASK) #define NOC_GICD_GICD_ICFGR13_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR13_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config4_MASK) #define NOC_GICD_GICD_ICFGR13_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR13_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config5_MASK) #define NOC_GICD_GICD_ICFGR13_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR13_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config6_MASK) #define NOC_GICD_GICD_ICFGR13_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR13_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config7_MASK) #define NOC_GICD_GICD_ICFGR13_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR13_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config8_MASK) #define NOC_GICD_GICD_ICFGR13_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR13_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config9_MASK) #define NOC_GICD_GICD_ICFGR13_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR13_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config10_MASK) #define NOC_GICD_GICD_ICFGR13_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR13_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config11_MASK) #define NOC_GICD_GICD_ICFGR13_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR13_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config12_MASK) #define NOC_GICD_GICD_ICFGR13_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR13_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config13_MASK) #define NOC_GICD_GICD_ICFGR13_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR13_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config14_MASK) #define NOC_GICD_GICD_ICFGR13_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR13_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR13_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR13_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR13_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR14 - GICD_ICFGR14 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR14_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR14_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config0_MASK) #define NOC_GICD_GICD_ICFGR14_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR14_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config1_MASK) #define NOC_GICD_GICD_ICFGR14_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR14_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config2_MASK) #define NOC_GICD_GICD_ICFGR14_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR14_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config3_MASK) #define NOC_GICD_GICD_ICFGR14_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR14_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config4_MASK) #define NOC_GICD_GICD_ICFGR14_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR14_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config5_MASK) #define NOC_GICD_GICD_ICFGR14_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR14_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config6_MASK) #define NOC_GICD_GICD_ICFGR14_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR14_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config7_MASK) #define NOC_GICD_GICD_ICFGR14_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR14_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config8_MASK) #define NOC_GICD_GICD_ICFGR14_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR14_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config9_MASK) #define NOC_GICD_GICD_ICFGR14_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR14_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config10_MASK) #define NOC_GICD_GICD_ICFGR14_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR14_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config11_MASK) #define NOC_GICD_GICD_ICFGR14_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR14_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config12_MASK) #define NOC_GICD_GICD_ICFGR14_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR14_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config13_MASK) #define NOC_GICD_GICD_ICFGR14_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR14_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config14_MASK) #define NOC_GICD_GICD_ICFGR14_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR14_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR14_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR14_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR14_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR15 - GICD_ICFGR15 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR15_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR15_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config0_MASK) #define NOC_GICD_GICD_ICFGR15_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR15_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config1_MASK) #define NOC_GICD_GICD_ICFGR15_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR15_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config2_MASK) #define NOC_GICD_GICD_ICFGR15_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR15_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config3_MASK) #define NOC_GICD_GICD_ICFGR15_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR15_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config4_MASK) #define NOC_GICD_GICD_ICFGR15_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR15_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config5_MASK) #define NOC_GICD_GICD_ICFGR15_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR15_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config6_MASK) #define NOC_GICD_GICD_ICFGR15_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR15_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config7_MASK) #define NOC_GICD_GICD_ICFGR15_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR15_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config8_MASK) #define NOC_GICD_GICD_ICFGR15_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR15_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config9_MASK) #define NOC_GICD_GICD_ICFGR15_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR15_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config10_MASK) #define NOC_GICD_GICD_ICFGR15_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR15_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config11_MASK) #define NOC_GICD_GICD_ICFGR15_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR15_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config12_MASK) #define NOC_GICD_GICD_ICFGR15_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR15_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config13_MASK) #define NOC_GICD_GICD_ICFGR15_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR15_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config14_MASK) #define NOC_GICD_GICD_ICFGR15_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR15_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR15_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR15_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR15_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR16 - GICD_ICFGR16 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR16_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR16_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config0_MASK) #define NOC_GICD_GICD_ICFGR16_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR16_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config1_MASK) #define NOC_GICD_GICD_ICFGR16_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR16_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config2_MASK) #define NOC_GICD_GICD_ICFGR16_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR16_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config3_MASK) #define NOC_GICD_GICD_ICFGR16_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR16_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config4_MASK) #define NOC_GICD_GICD_ICFGR16_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR16_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config5_MASK) #define NOC_GICD_GICD_ICFGR16_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR16_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config6_MASK) #define NOC_GICD_GICD_ICFGR16_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR16_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config7_MASK) #define NOC_GICD_GICD_ICFGR16_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR16_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config8_MASK) #define NOC_GICD_GICD_ICFGR16_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR16_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config9_MASK) #define NOC_GICD_GICD_ICFGR16_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR16_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config10_MASK) #define NOC_GICD_GICD_ICFGR16_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR16_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config11_MASK) #define NOC_GICD_GICD_ICFGR16_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR16_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config12_MASK) #define NOC_GICD_GICD_ICFGR16_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR16_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config13_MASK) #define NOC_GICD_GICD_ICFGR16_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR16_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config14_MASK) #define NOC_GICD_GICD_ICFGR16_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR16_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR16_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR16_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR16_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR17 - GICD_ICFGR17 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR17_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR17_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config0_MASK) #define NOC_GICD_GICD_ICFGR17_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR17_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config1_MASK) #define NOC_GICD_GICD_ICFGR17_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR17_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config2_MASK) #define NOC_GICD_GICD_ICFGR17_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR17_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config3_MASK) #define NOC_GICD_GICD_ICFGR17_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR17_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config4_MASK) #define NOC_GICD_GICD_ICFGR17_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR17_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config5_MASK) #define NOC_GICD_GICD_ICFGR17_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR17_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config6_MASK) #define NOC_GICD_GICD_ICFGR17_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR17_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config7_MASK) #define NOC_GICD_GICD_ICFGR17_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR17_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config8_MASK) #define NOC_GICD_GICD_ICFGR17_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR17_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config9_MASK) #define NOC_GICD_GICD_ICFGR17_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR17_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config10_MASK) #define NOC_GICD_GICD_ICFGR17_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR17_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config11_MASK) #define NOC_GICD_GICD_ICFGR17_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR17_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config12_MASK) #define NOC_GICD_GICD_ICFGR17_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR17_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config13_MASK) #define NOC_GICD_GICD_ICFGR17_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR17_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config14_MASK) #define NOC_GICD_GICD_ICFGR17_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR17_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR17_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR17_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR17_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR18 - GICD_ICFGR18 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR18_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR18_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config0_MASK) #define NOC_GICD_GICD_ICFGR18_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR18_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config1_MASK) #define NOC_GICD_GICD_ICFGR18_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR18_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config2_MASK) #define NOC_GICD_GICD_ICFGR18_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR18_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config3_MASK) #define NOC_GICD_GICD_ICFGR18_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR18_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config4_MASK) #define NOC_GICD_GICD_ICFGR18_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR18_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config5_MASK) #define NOC_GICD_GICD_ICFGR18_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR18_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config6_MASK) #define NOC_GICD_GICD_ICFGR18_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR18_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config7_MASK) #define NOC_GICD_GICD_ICFGR18_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR18_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config8_MASK) #define NOC_GICD_GICD_ICFGR18_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR18_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config9_MASK) #define NOC_GICD_GICD_ICFGR18_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR18_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config10_MASK) #define NOC_GICD_GICD_ICFGR18_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR18_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config11_MASK) #define NOC_GICD_GICD_ICFGR18_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR18_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config12_MASK) #define NOC_GICD_GICD_ICFGR18_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR18_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config13_MASK) #define NOC_GICD_GICD_ICFGR18_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR18_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config14_MASK) #define NOC_GICD_GICD_ICFGR18_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR18_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR18_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR18_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR18_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR19 - GICD_ICFGR19 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR19_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR19_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config0_MASK) #define NOC_GICD_GICD_ICFGR19_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR19_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config1_MASK) #define NOC_GICD_GICD_ICFGR19_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR19_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config2_MASK) #define NOC_GICD_GICD_ICFGR19_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR19_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config3_MASK) #define NOC_GICD_GICD_ICFGR19_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR19_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config4_MASK) #define NOC_GICD_GICD_ICFGR19_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR19_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config5_MASK) #define NOC_GICD_GICD_ICFGR19_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR19_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config6_MASK) #define NOC_GICD_GICD_ICFGR19_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR19_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config7_MASK) #define NOC_GICD_GICD_ICFGR19_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR19_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config8_MASK) #define NOC_GICD_GICD_ICFGR19_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR19_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config9_MASK) #define NOC_GICD_GICD_ICFGR19_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR19_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config10_MASK) #define NOC_GICD_GICD_ICFGR19_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR19_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config11_MASK) #define NOC_GICD_GICD_ICFGR19_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR19_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config12_MASK) #define NOC_GICD_GICD_ICFGR19_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR19_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config13_MASK) #define NOC_GICD_GICD_ICFGR19_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR19_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config14_MASK) #define NOC_GICD_GICD_ICFGR19_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR19_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR19_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR19_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR19_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR20 - GICD_ICFGR20 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR20_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR20_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config0_MASK) #define NOC_GICD_GICD_ICFGR20_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR20_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config1_MASK) #define NOC_GICD_GICD_ICFGR20_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR20_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config2_MASK) #define NOC_GICD_GICD_ICFGR20_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR20_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config3_MASK) #define NOC_GICD_GICD_ICFGR20_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR20_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config4_MASK) #define NOC_GICD_GICD_ICFGR20_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR20_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config5_MASK) #define NOC_GICD_GICD_ICFGR20_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR20_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config6_MASK) #define NOC_GICD_GICD_ICFGR20_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR20_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config7_MASK) #define NOC_GICD_GICD_ICFGR20_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR20_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config8_MASK) #define NOC_GICD_GICD_ICFGR20_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR20_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config9_MASK) #define NOC_GICD_GICD_ICFGR20_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR20_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config10_MASK) #define NOC_GICD_GICD_ICFGR20_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR20_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config11_MASK) #define NOC_GICD_GICD_ICFGR20_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR20_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config12_MASK) #define NOC_GICD_GICD_ICFGR20_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR20_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config13_MASK) #define NOC_GICD_GICD_ICFGR20_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR20_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config14_MASK) #define NOC_GICD_GICD_ICFGR20_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR20_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR20_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR20_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR20_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR21 - GICD_ICFGR21 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR21_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR21_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config0_MASK) #define NOC_GICD_GICD_ICFGR21_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR21_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config1_MASK) #define NOC_GICD_GICD_ICFGR21_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR21_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config2_MASK) #define NOC_GICD_GICD_ICFGR21_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR21_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config3_MASK) #define NOC_GICD_GICD_ICFGR21_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR21_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config4_MASK) #define NOC_GICD_GICD_ICFGR21_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR21_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config5_MASK) #define NOC_GICD_GICD_ICFGR21_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR21_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config6_MASK) #define NOC_GICD_GICD_ICFGR21_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR21_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config7_MASK) #define NOC_GICD_GICD_ICFGR21_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR21_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config8_MASK) #define NOC_GICD_GICD_ICFGR21_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR21_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config9_MASK) #define NOC_GICD_GICD_ICFGR21_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR21_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config10_MASK) #define NOC_GICD_GICD_ICFGR21_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR21_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config11_MASK) #define NOC_GICD_GICD_ICFGR21_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR21_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config12_MASK) #define NOC_GICD_GICD_ICFGR21_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR21_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config13_MASK) #define NOC_GICD_GICD_ICFGR21_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR21_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config14_MASK) #define NOC_GICD_GICD_ICFGR21_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR21_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR21_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR21_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR21_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR22 - GICD_ICFGR22 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR22_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR22_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config0_MASK) #define NOC_GICD_GICD_ICFGR22_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR22_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config1_MASK) #define NOC_GICD_GICD_ICFGR22_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR22_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config2_MASK) #define NOC_GICD_GICD_ICFGR22_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR22_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config3_MASK) #define NOC_GICD_GICD_ICFGR22_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR22_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config4_MASK) #define NOC_GICD_GICD_ICFGR22_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR22_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config5_MASK) #define NOC_GICD_GICD_ICFGR22_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR22_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config6_MASK) #define NOC_GICD_GICD_ICFGR22_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR22_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config7_MASK) #define NOC_GICD_GICD_ICFGR22_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR22_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config8_MASK) #define NOC_GICD_GICD_ICFGR22_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR22_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config9_MASK) #define NOC_GICD_GICD_ICFGR22_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR22_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config10_MASK) #define NOC_GICD_GICD_ICFGR22_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR22_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config11_MASK) #define NOC_GICD_GICD_ICFGR22_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR22_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config12_MASK) #define NOC_GICD_GICD_ICFGR22_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR22_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config13_MASK) #define NOC_GICD_GICD_ICFGR22_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR22_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config14_MASK) #define NOC_GICD_GICD_ICFGR22_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR22_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR22_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR22_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR22_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR23 - GICD_ICFGR23 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR23_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR23_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config0_MASK) #define NOC_GICD_GICD_ICFGR23_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR23_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config1_MASK) #define NOC_GICD_GICD_ICFGR23_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR23_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config2_MASK) #define NOC_GICD_GICD_ICFGR23_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR23_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config3_MASK) #define NOC_GICD_GICD_ICFGR23_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR23_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config4_MASK) #define NOC_GICD_GICD_ICFGR23_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR23_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config5_MASK) #define NOC_GICD_GICD_ICFGR23_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR23_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config6_MASK) #define NOC_GICD_GICD_ICFGR23_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR23_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config7_MASK) #define NOC_GICD_GICD_ICFGR23_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR23_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config8_MASK) #define NOC_GICD_GICD_ICFGR23_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR23_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config9_MASK) #define NOC_GICD_GICD_ICFGR23_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR23_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config10_MASK) #define NOC_GICD_GICD_ICFGR23_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR23_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config11_MASK) #define NOC_GICD_GICD_ICFGR23_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR23_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config12_MASK) #define NOC_GICD_GICD_ICFGR23_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR23_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config13_MASK) #define NOC_GICD_GICD_ICFGR23_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR23_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config14_MASK) #define NOC_GICD_GICD_ICFGR23_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR23_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR23_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR23_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR23_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR24 - GICD_ICFGR24 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR24_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR24_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config0_MASK) #define NOC_GICD_GICD_ICFGR24_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR24_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config1_MASK) #define NOC_GICD_GICD_ICFGR24_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR24_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config2_MASK) #define NOC_GICD_GICD_ICFGR24_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR24_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config3_MASK) #define NOC_GICD_GICD_ICFGR24_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR24_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config4_MASK) #define NOC_GICD_GICD_ICFGR24_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR24_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config5_MASK) #define NOC_GICD_GICD_ICFGR24_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR24_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config6_MASK) #define NOC_GICD_GICD_ICFGR24_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR24_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config7_MASK) #define NOC_GICD_GICD_ICFGR24_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR24_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config8_MASK) #define NOC_GICD_GICD_ICFGR24_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR24_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config9_MASK) #define NOC_GICD_GICD_ICFGR24_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR24_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config10_MASK) #define NOC_GICD_GICD_ICFGR24_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR24_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config11_MASK) #define NOC_GICD_GICD_ICFGR24_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR24_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config12_MASK) #define NOC_GICD_GICD_ICFGR24_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR24_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config13_MASK) #define NOC_GICD_GICD_ICFGR24_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR24_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config14_MASK) #define NOC_GICD_GICD_ICFGR24_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR24_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR24_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR24_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR24_int_config15_MASK) /*! @} */ /*! @name GICD_ICFGR25 - GICD_ICFGR25 */ /*! @{ */ #define NOC_GICD_GICD_ICFGR25_int_config0_MASK (0x3U) #define NOC_GICD_GICD_ICFGR25_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config0_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config0_MASK) #define NOC_GICD_GICD_ICFGR25_int_config1_MASK (0xCU) #define NOC_GICD_GICD_ICFGR25_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config1_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config1_MASK) #define NOC_GICD_GICD_ICFGR25_int_config2_MASK (0x30U) #define NOC_GICD_GICD_ICFGR25_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config2_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config2_MASK) #define NOC_GICD_GICD_ICFGR25_int_config3_MASK (0xC0U) #define NOC_GICD_GICD_ICFGR25_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config3_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config3_MASK) #define NOC_GICD_GICD_ICFGR25_int_config4_MASK (0x300U) #define NOC_GICD_GICD_ICFGR25_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config4_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config4_MASK) #define NOC_GICD_GICD_ICFGR25_int_config5_MASK (0xC00U) #define NOC_GICD_GICD_ICFGR25_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config5_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config5_MASK) #define NOC_GICD_GICD_ICFGR25_int_config6_MASK (0x3000U) #define NOC_GICD_GICD_ICFGR25_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config6_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config6_MASK) #define NOC_GICD_GICD_ICFGR25_int_config7_MASK (0xC000U) #define NOC_GICD_GICD_ICFGR25_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config7_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config7_MASK) #define NOC_GICD_GICD_ICFGR25_int_config8_MASK (0x30000U) #define NOC_GICD_GICD_ICFGR25_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config8_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config8_MASK) #define NOC_GICD_GICD_ICFGR25_int_config9_MASK (0xC0000U) #define NOC_GICD_GICD_ICFGR25_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config9_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config9_MASK) #define NOC_GICD_GICD_ICFGR25_int_config10_MASK (0x300000U) #define NOC_GICD_GICD_ICFGR25_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config10_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config10_MASK) #define NOC_GICD_GICD_ICFGR25_int_config11_MASK (0xC00000U) #define NOC_GICD_GICD_ICFGR25_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config11_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config11_MASK) #define NOC_GICD_GICD_ICFGR25_int_config12_MASK (0x3000000U) #define NOC_GICD_GICD_ICFGR25_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config12_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config12_MASK) #define NOC_GICD_GICD_ICFGR25_int_config13_MASK (0xC000000U) #define NOC_GICD_GICD_ICFGR25_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config13_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config13_MASK) #define NOC_GICD_GICD_ICFGR25_int_config14_MASK (0x30000000U) #define NOC_GICD_GICD_ICFGR25_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config14_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config14_MASK) #define NOC_GICD_GICD_ICFGR25_int_config15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICFGR25_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICD_GICD_ICFGR25_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICFGR25_int_config15_SHIFT)) & NOC_GICD_GICD_ICFGR25_int_config15_MASK) /*! @} */ /*! @name GICD_IGRPMODR1 - GICD_IGRPMODR1 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR1_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR1_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR1_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR2 - GICD_IGRPMODR2 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR2_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR2_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR2_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR3 - GICD_IGRPMODR3 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR3_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR3_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR3_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR4 - GICD_IGRPMODR4 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR4_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR4_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR4_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR5 - GICD_IGRPMODR5 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR5_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR5_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR5_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR6 - GICD_IGRPMODR6 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR6_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR6_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR6_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR7 - GICD_IGRPMODR7 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR7_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR7_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR7_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR8 - GICD_IGRPMODR8 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR8_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR8_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR8_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR9 - GICD_IGRPMODR9 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR9_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR9_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR9_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR10 - GICD_IGRPMODR10 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR10_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR10_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR10_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR11 - GICD_IGRPMODR11 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR11_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR11_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR11_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_IGRPMODR12 - GICD_IGRPMODR12 */ /*! @{ */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit0_MASK (0x1U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit0_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit0_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit1_MASK (0x2U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit1_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit1_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit2_MASK (0x4U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit2_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit2_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit3_MASK (0x8U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit3_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit3_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit4_MASK (0x10U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit4_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit4_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit5_MASK (0x20U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit5_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit5_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit6_MASK (0x40U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit6_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit6_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit7_MASK (0x80U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit7_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit7_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit8_MASK (0x100U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit8_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit8_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit9_MASK (0x200U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit9_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit9_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit10_MASK (0x400U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit10_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit10_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit11_MASK (0x800U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit11_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit11_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit12_MASK (0x1000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit12_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit12_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit13_MASK (0x2000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit13_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit13_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit14_MASK (0x4000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit14_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit14_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit15_MASK (0x8000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit15_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit15_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit16_MASK (0x10000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit16_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit16_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit17_MASK (0x20000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit17_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit17_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit18_MASK (0x40000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit18_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit18_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit19_MASK (0x80000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit19_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit19_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit20_MASK (0x100000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit20_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit20_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit21_MASK (0x200000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit21_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit21_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit22_MASK (0x400000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit22_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit22_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit23_MASK (0x800000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit23_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit23_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit24_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit24_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit25_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit25_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit26_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit26_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit27_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit27_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit28_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit28_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit29_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit29_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit30_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit30_MASK) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICD_GICD_IGRPMODR12_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_IGRPMODR12_group_modifier_bit31_SHIFT)) & NOC_GICD_GICD_IGRPMODR12_group_modifier_bit31_MASK) /*! @} */ /*! @name GICD_NSACR2 - GICD_NSACR2 */ /*! @{ */ #define NOC_GICD_GICD_NSACR2_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR2_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR2_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access0_MASK) #define NOC_GICD_GICD_NSACR2_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR2_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR2_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access1_MASK) #define NOC_GICD_GICD_NSACR2_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR2_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR2_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access2_MASK) #define NOC_GICD_GICD_NSACR2_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR2_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR2_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access3_MASK) #define NOC_GICD_GICD_NSACR2_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR2_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR2_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access4_MASK) #define NOC_GICD_GICD_NSACR2_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR2_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR2_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access5_MASK) #define NOC_GICD_GICD_NSACR2_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR2_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR2_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access6_MASK) #define NOC_GICD_GICD_NSACR2_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR2_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR2_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access7_MASK) #define NOC_GICD_GICD_NSACR2_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR2_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR2_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access8_MASK) #define NOC_GICD_GICD_NSACR2_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR2_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR2_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access9_MASK) #define NOC_GICD_GICD_NSACR2_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR2_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR2_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access10_MASK) #define NOC_GICD_GICD_NSACR2_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR2_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR2_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access11_MASK) #define NOC_GICD_GICD_NSACR2_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR2_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR2_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access12_MASK) #define NOC_GICD_GICD_NSACR2_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR2_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR2_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access13_MASK) #define NOC_GICD_GICD_NSACR2_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR2_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR2_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access14_MASK) #define NOC_GICD_GICD_NSACR2_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR2_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR2_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR2_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR2_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR3 - GICD_NSACR3 */ /*! @{ */ #define NOC_GICD_GICD_NSACR3_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR3_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR3_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access0_MASK) #define NOC_GICD_GICD_NSACR3_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR3_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR3_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access1_MASK) #define NOC_GICD_GICD_NSACR3_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR3_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR3_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access2_MASK) #define NOC_GICD_GICD_NSACR3_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR3_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR3_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access3_MASK) #define NOC_GICD_GICD_NSACR3_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR3_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR3_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access4_MASK) #define NOC_GICD_GICD_NSACR3_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR3_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR3_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access5_MASK) #define NOC_GICD_GICD_NSACR3_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR3_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR3_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access6_MASK) #define NOC_GICD_GICD_NSACR3_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR3_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR3_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access7_MASK) #define NOC_GICD_GICD_NSACR3_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR3_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR3_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access8_MASK) #define NOC_GICD_GICD_NSACR3_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR3_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR3_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access9_MASK) #define NOC_GICD_GICD_NSACR3_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR3_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR3_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access10_MASK) #define NOC_GICD_GICD_NSACR3_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR3_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR3_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access11_MASK) #define NOC_GICD_GICD_NSACR3_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR3_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR3_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access12_MASK) #define NOC_GICD_GICD_NSACR3_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR3_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR3_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access13_MASK) #define NOC_GICD_GICD_NSACR3_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR3_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR3_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access14_MASK) #define NOC_GICD_GICD_NSACR3_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR3_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR3_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR3_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR3_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR4 - GICD_NSACR4 */ /*! @{ */ #define NOC_GICD_GICD_NSACR4_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR4_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR4_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access0_MASK) #define NOC_GICD_GICD_NSACR4_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR4_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR4_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access1_MASK) #define NOC_GICD_GICD_NSACR4_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR4_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR4_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access2_MASK) #define NOC_GICD_GICD_NSACR4_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR4_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR4_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access3_MASK) #define NOC_GICD_GICD_NSACR4_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR4_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR4_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access4_MASK) #define NOC_GICD_GICD_NSACR4_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR4_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR4_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access5_MASK) #define NOC_GICD_GICD_NSACR4_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR4_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR4_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access6_MASK) #define NOC_GICD_GICD_NSACR4_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR4_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR4_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access7_MASK) #define NOC_GICD_GICD_NSACR4_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR4_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR4_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access8_MASK) #define NOC_GICD_GICD_NSACR4_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR4_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR4_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access9_MASK) #define NOC_GICD_GICD_NSACR4_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR4_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR4_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access10_MASK) #define NOC_GICD_GICD_NSACR4_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR4_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR4_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access11_MASK) #define NOC_GICD_GICD_NSACR4_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR4_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR4_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access12_MASK) #define NOC_GICD_GICD_NSACR4_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR4_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR4_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access13_MASK) #define NOC_GICD_GICD_NSACR4_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR4_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR4_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access14_MASK) #define NOC_GICD_GICD_NSACR4_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR4_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR4_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR4_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR4_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR5 - GICD_NSACR5 */ /*! @{ */ #define NOC_GICD_GICD_NSACR5_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR5_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR5_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access0_MASK) #define NOC_GICD_GICD_NSACR5_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR5_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR5_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access1_MASK) #define NOC_GICD_GICD_NSACR5_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR5_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR5_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access2_MASK) #define NOC_GICD_GICD_NSACR5_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR5_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR5_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access3_MASK) #define NOC_GICD_GICD_NSACR5_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR5_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR5_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access4_MASK) #define NOC_GICD_GICD_NSACR5_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR5_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR5_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access5_MASK) #define NOC_GICD_GICD_NSACR5_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR5_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR5_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access6_MASK) #define NOC_GICD_GICD_NSACR5_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR5_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR5_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access7_MASK) #define NOC_GICD_GICD_NSACR5_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR5_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR5_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access8_MASK) #define NOC_GICD_GICD_NSACR5_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR5_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR5_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access9_MASK) #define NOC_GICD_GICD_NSACR5_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR5_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR5_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access10_MASK) #define NOC_GICD_GICD_NSACR5_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR5_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR5_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access11_MASK) #define NOC_GICD_GICD_NSACR5_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR5_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR5_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access12_MASK) #define NOC_GICD_GICD_NSACR5_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR5_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR5_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access13_MASK) #define NOC_GICD_GICD_NSACR5_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR5_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR5_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access14_MASK) #define NOC_GICD_GICD_NSACR5_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR5_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR5_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR5_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR5_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR6 - GICD_NSACR6 */ /*! @{ */ #define NOC_GICD_GICD_NSACR6_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR6_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR6_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access0_MASK) #define NOC_GICD_GICD_NSACR6_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR6_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR6_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access1_MASK) #define NOC_GICD_GICD_NSACR6_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR6_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR6_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access2_MASK) #define NOC_GICD_GICD_NSACR6_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR6_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR6_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access3_MASK) #define NOC_GICD_GICD_NSACR6_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR6_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR6_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access4_MASK) #define NOC_GICD_GICD_NSACR6_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR6_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR6_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access5_MASK) #define NOC_GICD_GICD_NSACR6_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR6_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR6_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access6_MASK) #define NOC_GICD_GICD_NSACR6_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR6_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR6_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access7_MASK) #define NOC_GICD_GICD_NSACR6_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR6_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR6_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access8_MASK) #define NOC_GICD_GICD_NSACR6_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR6_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR6_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access9_MASK) #define NOC_GICD_GICD_NSACR6_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR6_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR6_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access10_MASK) #define NOC_GICD_GICD_NSACR6_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR6_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR6_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access11_MASK) #define NOC_GICD_GICD_NSACR6_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR6_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR6_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access12_MASK) #define NOC_GICD_GICD_NSACR6_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR6_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR6_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access13_MASK) #define NOC_GICD_GICD_NSACR6_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR6_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR6_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access14_MASK) #define NOC_GICD_GICD_NSACR6_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR6_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR6_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR6_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR6_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR7 - GICD_NSACR7 */ /*! @{ */ #define NOC_GICD_GICD_NSACR7_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR7_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR7_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access0_MASK) #define NOC_GICD_GICD_NSACR7_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR7_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR7_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access1_MASK) #define NOC_GICD_GICD_NSACR7_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR7_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR7_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access2_MASK) #define NOC_GICD_GICD_NSACR7_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR7_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR7_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access3_MASK) #define NOC_GICD_GICD_NSACR7_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR7_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR7_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access4_MASK) #define NOC_GICD_GICD_NSACR7_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR7_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR7_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access5_MASK) #define NOC_GICD_GICD_NSACR7_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR7_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR7_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access6_MASK) #define NOC_GICD_GICD_NSACR7_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR7_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR7_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access7_MASK) #define NOC_GICD_GICD_NSACR7_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR7_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR7_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access8_MASK) #define NOC_GICD_GICD_NSACR7_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR7_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR7_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access9_MASK) #define NOC_GICD_GICD_NSACR7_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR7_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR7_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access10_MASK) #define NOC_GICD_GICD_NSACR7_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR7_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR7_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access11_MASK) #define NOC_GICD_GICD_NSACR7_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR7_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR7_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access12_MASK) #define NOC_GICD_GICD_NSACR7_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR7_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR7_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access13_MASK) #define NOC_GICD_GICD_NSACR7_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR7_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR7_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access14_MASK) #define NOC_GICD_GICD_NSACR7_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR7_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR7_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR7_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR7_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR8 - GICD_NSACR8 */ /*! @{ */ #define NOC_GICD_GICD_NSACR8_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR8_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR8_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access0_MASK) #define NOC_GICD_GICD_NSACR8_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR8_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR8_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access1_MASK) #define NOC_GICD_GICD_NSACR8_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR8_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR8_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access2_MASK) #define NOC_GICD_GICD_NSACR8_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR8_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR8_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access3_MASK) #define NOC_GICD_GICD_NSACR8_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR8_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR8_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access4_MASK) #define NOC_GICD_GICD_NSACR8_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR8_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR8_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access5_MASK) #define NOC_GICD_GICD_NSACR8_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR8_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR8_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access6_MASK) #define NOC_GICD_GICD_NSACR8_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR8_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR8_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access7_MASK) #define NOC_GICD_GICD_NSACR8_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR8_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR8_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access8_MASK) #define NOC_GICD_GICD_NSACR8_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR8_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR8_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access9_MASK) #define NOC_GICD_GICD_NSACR8_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR8_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR8_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access10_MASK) #define NOC_GICD_GICD_NSACR8_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR8_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR8_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access11_MASK) #define NOC_GICD_GICD_NSACR8_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR8_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR8_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access12_MASK) #define NOC_GICD_GICD_NSACR8_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR8_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR8_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access13_MASK) #define NOC_GICD_GICD_NSACR8_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR8_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR8_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access14_MASK) #define NOC_GICD_GICD_NSACR8_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR8_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR8_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR8_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR8_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR9 - GICD_NSACR9 */ /*! @{ */ #define NOC_GICD_GICD_NSACR9_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR9_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR9_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access0_MASK) #define NOC_GICD_GICD_NSACR9_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR9_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR9_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access1_MASK) #define NOC_GICD_GICD_NSACR9_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR9_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR9_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access2_MASK) #define NOC_GICD_GICD_NSACR9_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR9_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR9_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access3_MASK) #define NOC_GICD_GICD_NSACR9_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR9_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR9_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access4_MASK) #define NOC_GICD_GICD_NSACR9_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR9_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR9_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access5_MASK) #define NOC_GICD_GICD_NSACR9_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR9_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR9_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access6_MASK) #define NOC_GICD_GICD_NSACR9_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR9_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR9_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access7_MASK) #define NOC_GICD_GICD_NSACR9_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR9_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR9_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access8_MASK) #define NOC_GICD_GICD_NSACR9_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR9_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR9_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access9_MASK) #define NOC_GICD_GICD_NSACR9_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR9_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR9_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access10_MASK) #define NOC_GICD_GICD_NSACR9_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR9_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR9_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access11_MASK) #define NOC_GICD_GICD_NSACR9_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR9_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR9_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access12_MASK) #define NOC_GICD_GICD_NSACR9_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR9_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR9_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access13_MASK) #define NOC_GICD_GICD_NSACR9_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR9_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR9_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access14_MASK) #define NOC_GICD_GICD_NSACR9_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR9_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR9_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR9_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR9_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR10 - GICD_NSACR10 */ /*! @{ */ #define NOC_GICD_GICD_NSACR10_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR10_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR10_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access0_MASK) #define NOC_GICD_GICD_NSACR10_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR10_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR10_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access1_MASK) #define NOC_GICD_GICD_NSACR10_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR10_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR10_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access2_MASK) #define NOC_GICD_GICD_NSACR10_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR10_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR10_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access3_MASK) #define NOC_GICD_GICD_NSACR10_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR10_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR10_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access4_MASK) #define NOC_GICD_GICD_NSACR10_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR10_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR10_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access5_MASK) #define NOC_GICD_GICD_NSACR10_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR10_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR10_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access6_MASK) #define NOC_GICD_GICD_NSACR10_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR10_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR10_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access7_MASK) #define NOC_GICD_GICD_NSACR10_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR10_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR10_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access8_MASK) #define NOC_GICD_GICD_NSACR10_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR10_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR10_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access9_MASK) #define NOC_GICD_GICD_NSACR10_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR10_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR10_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access10_MASK) #define NOC_GICD_GICD_NSACR10_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR10_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR10_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access11_MASK) #define NOC_GICD_GICD_NSACR10_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR10_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR10_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access12_MASK) #define NOC_GICD_GICD_NSACR10_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR10_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR10_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access13_MASK) #define NOC_GICD_GICD_NSACR10_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR10_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR10_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access14_MASK) #define NOC_GICD_GICD_NSACR10_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR10_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR10_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR10_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR10_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR11 - GICD_NSACR11 */ /*! @{ */ #define NOC_GICD_GICD_NSACR11_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR11_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR11_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access0_MASK) #define NOC_GICD_GICD_NSACR11_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR11_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR11_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access1_MASK) #define NOC_GICD_GICD_NSACR11_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR11_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR11_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access2_MASK) #define NOC_GICD_GICD_NSACR11_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR11_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR11_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access3_MASK) #define NOC_GICD_GICD_NSACR11_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR11_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR11_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access4_MASK) #define NOC_GICD_GICD_NSACR11_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR11_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR11_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access5_MASK) #define NOC_GICD_GICD_NSACR11_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR11_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR11_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access6_MASK) #define NOC_GICD_GICD_NSACR11_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR11_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR11_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access7_MASK) #define NOC_GICD_GICD_NSACR11_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR11_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR11_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access8_MASK) #define NOC_GICD_GICD_NSACR11_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR11_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR11_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access9_MASK) #define NOC_GICD_GICD_NSACR11_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR11_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR11_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access10_MASK) #define NOC_GICD_GICD_NSACR11_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR11_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR11_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access11_MASK) #define NOC_GICD_GICD_NSACR11_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR11_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR11_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access12_MASK) #define NOC_GICD_GICD_NSACR11_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR11_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR11_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access13_MASK) #define NOC_GICD_GICD_NSACR11_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR11_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR11_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access14_MASK) #define NOC_GICD_GICD_NSACR11_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR11_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR11_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR11_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR11_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR12 - GICD_NSACR12 */ /*! @{ */ #define NOC_GICD_GICD_NSACR12_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR12_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR12_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access0_MASK) #define NOC_GICD_GICD_NSACR12_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR12_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR12_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access1_MASK) #define NOC_GICD_GICD_NSACR12_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR12_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR12_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access2_MASK) #define NOC_GICD_GICD_NSACR12_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR12_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR12_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access3_MASK) #define NOC_GICD_GICD_NSACR12_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR12_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR12_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access4_MASK) #define NOC_GICD_GICD_NSACR12_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR12_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR12_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access5_MASK) #define NOC_GICD_GICD_NSACR12_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR12_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR12_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access6_MASK) #define NOC_GICD_GICD_NSACR12_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR12_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR12_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access7_MASK) #define NOC_GICD_GICD_NSACR12_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR12_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR12_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access8_MASK) #define NOC_GICD_GICD_NSACR12_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR12_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR12_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access9_MASK) #define NOC_GICD_GICD_NSACR12_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR12_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR12_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access10_MASK) #define NOC_GICD_GICD_NSACR12_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR12_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR12_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access11_MASK) #define NOC_GICD_GICD_NSACR12_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR12_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR12_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access12_MASK) #define NOC_GICD_GICD_NSACR12_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR12_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR12_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access13_MASK) #define NOC_GICD_GICD_NSACR12_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR12_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR12_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access14_MASK) #define NOC_GICD_GICD_NSACR12_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR12_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR12_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR12_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR12_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR13 - GICD_NSACR13 */ /*! @{ */ #define NOC_GICD_GICD_NSACR13_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR13_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR13_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access0_MASK) #define NOC_GICD_GICD_NSACR13_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR13_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR13_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access1_MASK) #define NOC_GICD_GICD_NSACR13_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR13_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR13_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access2_MASK) #define NOC_GICD_GICD_NSACR13_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR13_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR13_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access3_MASK) #define NOC_GICD_GICD_NSACR13_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR13_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR13_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access4_MASK) #define NOC_GICD_GICD_NSACR13_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR13_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR13_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access5_MASK) #define NOC_GICD_GICD_NSACR13_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR13_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR13_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access6_MASK) #define NOC_GICD_GICD_NSACR13_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR13_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR13_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access7_MASK) #define NOC_GICD_GICD_NSACR13_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR13_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR13_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access8_MASK) #define NOC_GICD_GICD_NSACR13_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR13_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR13_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access9_MASK) #define NOC_GICD_GICD_NSACR13_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR13_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR13_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access10_MASK) #define NOC_GICD_GICD_NSACR13_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR13_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR13_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access11_MASK) #define NOC_GICD_GICD_NSACR13_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR13_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR13_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access12_MASK) #define NOC_GICD_GICD_NSACR13_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR13_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR13_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access13_MASK) #define NOC_GICD_GICD_NSACR13_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR13_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR13_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access14_MASK) #define NOC_GICD_GICD_NSACR13_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR13_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR13_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR13_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR13_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR14 - GICD_NSACR14 */ /*! @{ */ #define NOC_GICD_GICD_NSACR14_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR14_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR14_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access0_MASK) #define NOC_GICD_GICD_NSACR14_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR14_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR14_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access1_MASK) #define NOC_GICD_GICD_NSACR14_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR14_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR14_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access2_MASK) #define NOC_GICD_GICD_NSACR14_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR14_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR14_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access3_MASK) #define NOC_GICD_GICD_NSACR14_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR14_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR14_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access4_MASK) #define NOC_GICD_GICD_NSACR14_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR14_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR14_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access5_MASK) #define NOC_GICD_GICD_NSACR14_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR14_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR14_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access6_MASK) #define NOC_GICD_GICD_NSACR14_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR14_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR14_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access7_MASK) #define NOC_GICD_GICD_NSACR14_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR14_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR14_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access8_MASK) #define NOC_GICD_GICD_NSACR14_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR14_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR14_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access9_MASK) #define NOC_GICD_GICD_NSACR14_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR14_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR14_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access10_MASK) #define NOC_GICD_GICD_NSACR14_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR14_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR14_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access11_MASK) #define NOC_GICD_GICD_NSACR14_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR14_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR14_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access12_MASK) #define NOC_GICD_GICD_NSACR14_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR14_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR14_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access13_MASK) #define NOC_GICD_GICD_NSACR14_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR14_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR14_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access14_MASK) #define NOC_GICD_GICD_NSACR14_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR14_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR14_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR14_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR14_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR15 - GICD_NSACR15 */ /*! @{ */ #define NOC_GICD_GICD_NSACR15_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR15_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR15_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access0_MASK) #define NOC_GICD_GICD_NSACR15_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR15_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR15_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access1_MASK) #define NOC_GICD_GICD_NSACR15_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR15_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR15_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access2_MASK) #define NOC_GICD_GICD_NSACR15_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR15_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR15_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access3_MASK) #define NOC_GICD_GICD_NSACR15_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR15_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR15_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access4_MASK) #define NOC_GICD_GICD_NSACR15_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR15_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR15_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access5_MASK) #define NOC_GICD_GICD_NSACR15_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR15_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR15_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access6_MASK) #define NOC_GICD_GICD_NSACR15_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR15_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR15_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access7_MASK) #define NOC_GICD_GICD_NSACR15_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR15_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR15_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access8_MASK) #define NOC_GICD_GICD_NSACR15_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR15_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR15_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access9_MASK) #define NOC_GICD_GICD_NSACR15_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR15_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR15_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access10_MASK) #define NOC_GICD_GICD_NSACR15_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR15_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR15_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access11_MASK) #define NOC_GICD_GICD_NSACR15_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR15_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR15_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access12_MASK) #define NOC_GICD_GICD_NSACR15_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR15_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR15_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access13_MASK) #define NOC_GICD_GICD_NSACR15_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR15_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR15_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access14_MASK) #define NOC_GICD_GICD_NSACR15_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR15_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR15_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR15_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR15_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR16 - GICD_NSACR16 */ /*! @{ */ #define NOC_GICD_GICD_NSACR16_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR16_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR16_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access0_MASK) #define NOC_GICD_GICD_NSACR16_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR16_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR16_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access1_MASK) #define NOC_GICD_GICD_NSACR16_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR16_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR16_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access2_MASK) #define NOC_GICD_GICD_NSACR16_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR16_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR16_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access3_MASK) #define NOC_GICD_GICD_NSACR16_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR16_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR16_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access4_MASK) #define NOC_GICD_GICD_NSACR16_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR16_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR16_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access5_MASK) #define NOC_GICD_GICD_NSACR16_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR16_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR16_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access6_MASK) #define NOC_GICD_GICD_NSACR16_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR16_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR16_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access7_MASK) #define NOC_GICD_GICD_NSACR16_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR16_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR16_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access8_MASK) #define NOC_GICD_GICD_NSACR16_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR16_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR16_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access9_MASK) #define NOC_GICD_GICD_NSACR16_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR16_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR16_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access10_MASK) #define NOC_GICD_GICD_NSACR16_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR16_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR16_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access11_MASK) #define NOC_GICD_GICD_NSACR16_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR16_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR16_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access12_MASK) #define NOC_GICD_GICD_NSACR16_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR16_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR16_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access13_MASK) #define NOC_GICD_GICD_NSACR16_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR16_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR16_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access14_MASK) #define NOC_GICD_GICD_NSACR16_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR16_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR16_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR16_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR16_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR17 - GICD_NSACR17 */ /*! @{ */ #define NOC_GICD_GICD_NSACR17_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR17_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR17_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access0_MASK) #define NOC_GICD_GICD_NSACR17_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR17_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR17_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access1_MASK) #define NOC_GICD_GICD_NSACR17_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR17_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR17_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access2_MASK) #define NOC_GICD_GICD_NSACR17_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR17_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR17_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access3_MASK) #define NOC_GICD_GICD_NSACR17_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR17_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR17_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access4_MASK) #define NOC_GICD_GICD_NSACR17_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR17_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR17_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access5_MASK) #define NOC_GICD_GICD_NSACR17_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR17_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR17_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access6_MASK) #define NOC_GICD_GICD_NSACR17_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR17_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR17_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access7_MASK) #define NOC_GICD_GICD_NSACR17_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR17_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR17_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access8_MASK) #define NOC_GICD_GICD_NSACR17_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR17_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR17_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access9_MASK) #define NOC_GICD_GICD_NSACR17_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR17_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR17_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access10_MASK) #define NOC_GICD_GICD_NSACR17_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR17_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR17_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access11_MASK) #define NOC_GICD_GICD_NSACR17_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR17_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR17_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access12_MASK) #define NOC_GICD_GICD_NSACR17_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR17_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR17_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access13_MASK) #define NOC_GICD_GICD_NSACR17_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR17_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR17_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access14_MASK) #define NOC_GICD_GICD_NSACR17_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR17_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR17_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR17_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR17_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR18 - GICD_NSACR18 */ /*! @{ */ #define NOC_GICD_GICD_NSACR18_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR18_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR18_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access0_MASK) #define NOC_GICD_GICD_NSACR18_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR18_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR18_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access1_MASK) #define NOC_GICD_GICD_NSACR18_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR18_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR18_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access2_MASK) #define NOC_GICD_GICD_NSACR18_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR18_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR18_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access3_MASK) #define NOC_GICD_GICD_NSACR18_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR18_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR18_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access4_MASK) #define NOC_GICD_GICD_NSACR18_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR18_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR18_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access5_MASK) #define NOC_GICD_GICD_NSACR18_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR18_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR18_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access6_MASK) #define NOC_GICD_GICD_NSACR18_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR18_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR18_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access7_MASK) #define NOC_GICD_GICD_NSACR18_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR18_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR18_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access8_MASK) #define NOC_GICD_GICD_NSACR18_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR18_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR18_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access9_MASK) #define NOC_GICD_GICD_NSACR18_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR18_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR18_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access10_MASK) #define NOC_GICD_GICD_NSACR18_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR18_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR18_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access11_MASK) #define NOC_GICD_GICD_NSACR18_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR18_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR18_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access12_MASK) #define NOC_GICD_GICD_NSACR18_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR18_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR18_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access13_MASK) #define NOC_GICD_GICD_NSACR18_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR18_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR18_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access14_MASK) #define NOC_GICD_GICD_NSACR18_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR18_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR18_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR18_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR18_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR19 - GICD_NSACR19 */ /*! @{ */ #define NOC_GICD_GICD_NSACR19_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR19_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR19_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access0_MASK) #define NOC_GICD_GICD_NSACR19_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR19_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR19_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access1_MASK) #define NOC_GICD_GICD_NSACR19_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR19_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR19_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access2_MASK) #define NOC_GICD_GICD_NSACR19_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR19_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR19_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access3_MASK) #define NOC_GICD_GICD_NSACR19_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR19_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR19_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access4_MASK) #define NOC_GICD_GICD_NSACR19_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR19_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR19_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access5_MASK) #define NOC_GICD_GICD_NSACR19_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR19_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR19_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access6_MASK) #define NOC_GICD_GICD_NSACR19_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR19_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR19_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access7_MASK) #define NOC_GICD_GICD_NSACR19_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR19_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR19_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access8_MASK) #define NOC_GICD_GICD_NSACR19_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR19_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR19_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access9_MASK) #define NOC_GICD_GICD_NSACR19_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR19_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR19_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access10_MASK) #define NOC_GICD_GICD_NSACR19_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR19_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR19_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access11_MASK) #define NOC_GICD_GICD_NSACR19_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR19_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR19_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access12_MASK) #define NOC_GICD_GICD_NSACR19_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR19_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR19_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access13_MASK) #define NOC_GICD_GICD_NSACR19_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR19_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR19_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access14_MASK) #define NOC_GICD_GICD_NSACR19_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR19_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR19_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR19_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR19_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR20 - GICD_NSACR20 */ /*! @{ */ #define NOC_GICD_GICD_NSACR20_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR20_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR20_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access0_MASK) #define NOC_GICD_GICD_NSACR20_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR20_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR20_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access1_MASK) #define NOC_GICD_GICD_NSACR20_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR20_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR20_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access2_MASK) #define NOC_GICD_GICD_NSACR20_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR20_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR20_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access3_MASK) #define NOC_GICD_GICD_NSACR20_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR20_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR20_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access4_MASK) #define NOC_GICD_GICD_NSACR20_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR20_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR20_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access5_MASK) #define NOC_GICD_GICD_NSACR20_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR20_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR20_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access6_MASK) #define NOC_GICD_GICD_NSACR20_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR20_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR20_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access7_MASK) #define NOC_GICD_GICD_NSACR20_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR20_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR20_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access8_MASK) #define NOC_GICD_GICD_NSACR20_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR20_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR20_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access9_MASK) #define NOC_GICD_GICD_NSACR20_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR20_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR20_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access10_MASK) #define NOC_GICD_GICD_NSACR20_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR20_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR20_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access11_MASK) #define NOC_GICD_GICD_NSACR20_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR20_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR20_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access12_MASK) #define NOC_GICD_GICD_NSACR20_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR20_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR20_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access13_MASK) #define NOC_GICD_GICD_NSACR20_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR20_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR20_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access14_MASK) #define NOC_GICD_GICD_NSACR20_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR20_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR20_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR20_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR20_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR21 - GICD_NSACR21 */ /*! @{ */ #define NOC_GICD_GICD_NSACR21_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR21_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR21_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access0_MASK) #define NOC_GICD_GICD_NSACR21_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR21_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR21_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access1_MASK) #define NOC_GICD_GICD_NSACR21_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR21_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR21_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access2_MASK) #define NOC_GICD_GICD_NSACR21_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR21_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR21_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access3_MASK) #define NOC_GICD_GICD_NSACR21_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR21_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR21_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access4_MASK) #define NOC_GICD_GICD_NSACR21_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR21_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR21_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access5_MASK) #define NOC_GICD_GICD_NSACR21_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR21_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR21_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access6_MASK) #define NOC_GICD_GICD_NSACR21_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR21_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR21_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access7_MASK) #define NOC_GICD_GICD_NSACR21_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR21_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR21_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access8_MASK) #define NOC_GICD_GICD_NSACR21_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR21_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR21_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access9_MASK) #define NOC_GICD_GICD_NSACR21_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR21_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR21_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access10_MASK) #define NOC_GICD_GICD_NSACR21_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR21_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR21_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access11_MASK) #define NOC_GICD_GICD_NSACR21_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR21_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR21_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access12_MASK) #define NOC_GICD_GICD_NSACR21_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR21_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR21_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access13_MASK) #define NOC_GICD_GICD_NSACR21_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR21_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR21_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access14_MASK) #define NOC_GICD_GICD_NSACR21_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR21_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR21_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR21_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR21_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR22 - GICD_NSACR22 */ /*! @{ */ #define NOC_GICD_GICD_NSACR22_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR22_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR22_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access0_MASK) #define NOC_GICD_GICD_NSACR22_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR22_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR22_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access1_MASK) #define NOC_GICD_GICD_NSACR22_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR22_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR22_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access2_MASK) #define NOC_GICD_GICD_NSACR22_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR22_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR22_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access3_MASK) #define NOC_GICD_GICD_NSACR22_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR22_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR22_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access4_MASK) #define NOC_GICD_GICD_NSACR22_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR22_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR22_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access5_MASK) #define NOC_GICD_GICD_NSACR22_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR22_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR22_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access6_MASK) #define NOC_GICD_GICD_NSACR22_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR22_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR22_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access7_MASK) #define NOC_GICD_GICD_NSACR22_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR22_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR22_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access8_MASK) #define NOC_GICD_GICD_NSACR22_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR22_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR22_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access9_MASK) #define NOC_GICD_GICD_NSACR22_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR22_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR22_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access10_MASK) #define NOC_GICD_GICD_NSACR22_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR22_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR22_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access11_MASK) #define NOC_GICD_GICD_NSACR22_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR22_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR22_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access12_MASK) #define NOC_GICD_GICD_NSACR22_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR22_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR22_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access13_MASK) #define NOC_GICD_GICD_NSACR22_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR22_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR22_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access14_MASK) #define NOC_GICD_GICD_NSACR22_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR22_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR22_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR22_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR22_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR23 - GICD_NSACR23 */ /*! @{ */ #define NOC_GICD_GICD_NSACR23_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR23_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR23_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access0_MASK) #define NOC_GICD_GICD_NSACR23_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR23_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR23_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access1_MASK) #define NOC_GICD_GICD_NSACR23_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR23_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR23_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access2_MASK) #define NOC_GICD_GICD_NSACR23_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR23_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR23_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access3_MASK) #define NOC_GICD_GICD_NSACR23_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR23_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR23_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access4_MASK) #define NOC_GICD_GICD_NSACR23_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR23_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR23_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access5_MASK) #define NOC_GICD_GICD_NSACR23_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR23_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR23_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access6_MASK) #define NOC_GICD_GICD_NSACR23_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR23_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR23_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access7_MASK) #define NOC_GICD_GICD_NSACR23_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR23_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR23_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access8_MASK) #define NOC_GICD_GICD_NSACR23_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR23_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR23_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access9_MASK) #define NOC_GICD_GICD_NSACR23_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR23_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR23_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access10_MASK) #define NOC_GICD_GICD_NSACR23_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR23_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR23_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access11_MASK) #define NOC_GICD_GICD_NSACR23_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR23_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR23_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access12_MASK) #define NOC_GICD_GICD_NSACR23_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR23_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR23_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access13_MASK) #define NOC_GICD_GICD_NSACR23_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR23_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR23_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access14_MASK) #define NOC_GICD_GICD_NSACR23_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR23_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR23_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR23_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR23_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR24 - GICD_NSACR24 */ /*! @{ */ #define NOC_GICD_GICD_NSACR24_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR24_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR24_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access0_MASK) #define NOC_GICD_GICD_NSACR24_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR24_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR24_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access1_MASK) #define NOC_GICD_GICD_NSACR24_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR24_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR24_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access2_MASK) #define NOC_GICD_GICD_NSACR24_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR24_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR24_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access3_MASK) #define NOC_GICD_GICD_NSACR24_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR24_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR24_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access4_MASK) #define NOC_GICD_GICD_NSACR24_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR24_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR24_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access5_MASK) #define NOC_GICD_GICD_NSACR24_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR24_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR24_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access6_MASK) #define NOC_GICD_GICD_NSACR24_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR24_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR24_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access7_MASK) #define NOC_GICD_GICD_NSACR24_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR24_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR24_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access8_MASK) #define NOC_GICD_GICD_NSACR24_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR24_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR24_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access9_MASK) #define NOC_GICD_GICD_NSACR24_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR24_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR24_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access10_MASK) #define NOC_GICD_GICD_NSACR24_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR24_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR24_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access11_MASK) #define NOC_GICD_GICD_NSACR24_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR24_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR24_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access12_MASK) #define NOC_GICD_GICD_NSACR24_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR24_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR24_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access13_MASK) #define NOC_GICD_GICD_NSACR24_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR24_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR24_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access14_MASK) #define NOC_GICD_GICD_NSACR24_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR24_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR24_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR24_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR24_ns_access15_MASK) /*! @} */ /*! @name GICD_NSACR25 - GICD_NSACR25 */ /*! @{ */ #define NOC_GICD_GICD_NSACR25_ns_access0_MASK (0x3U) #define NOC_GICD_GICD_NSACR25_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICD_GICD_NSACR25_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access0_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access0_MASK) #define NOC_GICD_GICD_NSACR25_ns_access1_MASK (0xCU) #define NOC_GICD_GICD_NSACR25_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICD_GICD_NSACR25_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access1_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access1_MASK) #define NOC_GICD_GICD_NSACR25_ns_access2_MASK (0x30U) #define NOC_GICD_GICD_NSACR25_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICD_GICD_NSACR25_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access2_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access2_MASK) #define NOC_GICD_GICD_NSACR25_ns_access3_MASK (0xC0U) #define NOC_GICD_GICD_NSACR25_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICD_GICD_NSACR25_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access3_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access3_MASK) #define NOC_GICD_GICD_NSACR25_ns_access4_MASK (0x300U) #define NOC_GICD_GICD_NSACR25_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICD_GICD_NSACR25_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access4_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access4_MASK) #define NOC_GICD_GICD_NSACR25_ns_access5_MASK (0xC00U) #define NOC_GICD_GICD_NSACR25_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICD_GICD_NSACR25_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access5_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access5_MASK) #define NOC_GICD_GICD_NSACR25_ns_access6_MASK (0x3000U) #define NOC_GICD_GICD_NSACR25_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICD_GICD_NSACR25_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access6_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access6_MASK) #define NOC_GICD_GICD_NSACR25_ns_access7_MASK (0xC000U) #define NOC_GICD_GICD_NSACR25_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICD_GICD_NSACR25_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access7_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access7_MASK) #define NOC_GICD_GICD_NSACR25_ns_access8_MASK (0x30000U) #define NOC_GICD_GICD_NSACR25_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICD_GICD_NSACR25_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access8_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access8_MASK) #define NOC_GICD_GICD_NSACR25_ns_access9_MASK (0xC0000U) #define NOC_GICD_GICD_NSACR25_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICD_GICD_NSACR25_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access9_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access9_MASK) #define NOC_GICD_GICD_NSACR25_ns_access10_MASK (0x300000U) #define NOC_GICD_GICD_NSACR25_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICD_GICD_NSACR25_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access10_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access10_MASK) #define NOC_GICD_GICD_NSACR25_ns_access11_MASK (0xC00000U) #define NOC_GICD_GICD_NSACR25_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICD_GICD_NSACR25_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access11_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access11_MASK) #define NOC_GICD_GICD_NSACR25_ns_access12_MASK (0x3000000U) #define NOC_GICD_GICD_NSACR25_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICD_GICD_NSACR25_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access12_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access12_MASK) #define NOC_GICD_GICD_NSACR25_ns_access13_MASK (0xC000000U) #define NOC_GICD_GICD_NSACR25_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICD_GICD_NSACR25_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access13_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access13_MASK) #define NOC_GICD_GICD_NSACR25_ns_access14_MASK (0x30000000U) #define NOC_GICD_GICD_NSACR25_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICD_GICD_NSACR25_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access14_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access14_MASK) #define NOC_GICD_GICD_NSACR25_ns_access15_MASK (0xC0000000U) #define NOC_GICD_GICD_NSACR25_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICD_GICD_NSACR25_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_NSACR25_ns_access15_SHIFT)) & NOC_GICD_GICD_NSACR25_ns_access15_MASK) /*! @} */ /*! @name GICD_IROUTER32 - GICD_IROUTER32 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER32_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER32_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER32_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER32_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER32_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER32_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER32_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER32_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER32_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER32_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER32_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER32_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER32_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER32_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER32_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER32_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER32_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER32_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER32_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER32_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER32_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER32_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER32_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER32_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER32_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER32_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER32_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER32_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER32_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER32_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER32_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER32_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER32_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER32_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER32_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER33 - GICD_IROUTER33 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER33_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER33_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER33_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER33_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER33_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER33_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER33_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER33_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER33_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER33_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER33_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER33_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER33_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER33_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER33_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER33_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER33_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER33_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER33_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER33_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER33_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER33_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER33_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER33_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER33_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER33_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER33_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER33_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER33_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER33_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER33_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER33_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER33_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER33_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER33_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER34 - GICD_IROUTER34 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER34_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER34_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER34_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER34_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER34_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER34_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER34_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER34_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER34_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER34_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER34_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER34_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER34_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER34_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER34_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER34_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER34_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER34_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER34_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER34_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER34_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER34_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER34_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER34_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER34_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER34_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER34_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER34_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER34_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER34_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER34_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER34_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER34_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER34_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER34_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER35 - GICD_IROUTER35 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER35_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER35_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER35_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER35_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER35_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER35_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER35_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER35_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER35_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER35_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER35_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER35_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER35_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER35_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER35_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER35_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER35_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER35_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER35_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER35_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER35_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER35_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER35_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER35_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER35_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER35_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER35_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER35_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER35_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER35_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER35_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER35_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER35_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER35_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER35_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER36 - GICD_IROUTER36 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER36_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER36_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER36_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER36_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER36_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER36_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER36_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER36_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER36_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER36_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER36_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER36_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER36_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER36_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER36_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER36_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER36_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER36_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER36_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER36_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER36_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER36_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER36_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER36_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER36_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER36_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER36_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER36_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER36_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER36_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER36_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER36_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER36_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER36_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER36_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER37 - GICD_IROUTER37 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER37_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER37_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER37_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER37_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER37_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER37_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER37_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER37_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER37_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER37_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER37_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER37_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER37_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER37_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER37_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER37_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER37_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER37_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER37_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER37_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER37_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER37_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER37_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER37_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER37_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER37_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER37_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER37_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER37_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER37_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER37_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER37_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER37_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER37_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER37_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER38 - GICD_IROUTER38 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER38_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER38_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER38_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER38_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER38_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER38_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER38_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER38_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER38_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER38_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER38_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER38_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER38_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER38_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER38_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER38_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER38_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER38_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER38_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER38_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER38_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER38_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER38_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER38_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER38_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER38_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER38_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER38_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER38_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER38_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER38_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER38_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER38_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER38_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER38_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER39 - GICD_IROUTER39 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER39_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER39_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER39_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER39_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER39_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER39_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER39_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER39_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER39_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER39_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER39_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER39_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER39_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER39_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER39_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER39_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER39_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER39_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER39_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER39_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER39_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER39_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER39_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER39_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER39_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER39_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER39_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER39_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER39_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER39_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER39_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER39_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER39_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER39_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER39_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER40 - GICD_IROUTER40 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER40_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER40_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER40_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER40_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER40_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER40_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER40_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER40_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER40_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER40_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER40_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER40_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER40_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER40_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER40_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER40_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER40_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER40_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER40_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER40_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER40_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER40_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER40_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER40_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER40_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER40_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER40_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER40_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER40_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER40_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER40_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER40_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER40_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER40_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER40_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER41 - GICD_IROUTER41 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER41_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER41_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER41_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER41_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER41_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER41_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER41_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER41_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER41_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER41_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER41_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER41_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER41_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER41_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER41_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER41_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER41_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER41_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER41_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER41_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER41_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER41_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER41_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER41_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER41_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER41_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER41_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER41_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER41_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER41_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER41_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER41_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER41_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER41_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER41_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER42 - GICD_IROUTER42 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER42_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER42_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER42_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER42_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER42_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER42_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER42_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER42_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER42_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER42_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER42_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER42_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER42_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER42_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER42_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER42_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER42_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER42_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER42_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER42_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER42_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER42_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER42_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER42_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER42_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER42_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER42_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER42_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER42_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER42_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER42_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER42_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER42_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER42_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER42_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER43 - GICD_IROUTER43 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER43_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER43_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER43_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER43_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER43_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER43_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER43_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER43_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER43_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER43_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER43_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER43_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER43_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER43_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER43_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER43_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER43_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER43_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER43_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER43_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER43_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER43_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER43_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER43_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER43_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER43_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER43_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER43_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER43_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER43_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER43_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER43_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER43_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER43_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER43_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER44 - GICD_IROUTER44 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER44_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER44_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER44_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER44_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER44_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER44_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER44_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER44_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER44_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER44_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER44_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER44_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER44_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER44_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER44_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER44_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER44_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER44_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER44_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER44_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER44_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER44_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER44_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER44_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER44_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER44_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER44_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER44_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER44_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER44_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER44_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER44_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER44_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER44_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER44_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER45 - GICD_IROUTER45 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER45_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER45_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER45_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER45_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER45_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER45_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER45_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER45_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER45_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER45_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER45_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER45_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER45_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER45_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER45_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER45_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER45_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER45_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER45_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER45_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER45_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER45_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER45_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER45_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER45_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER45_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER45_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER45_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER45_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER45_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER45_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER45_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER45_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER45_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER45_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER46 - GICD_IROUTER46 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER46_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER46_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER46_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER46_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER46_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER46_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER46_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER46_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER46_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER46_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER46_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER46_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER46_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER46_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER46_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER46_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER46_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER46_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER46_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER46_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER46_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER46_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER46_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER46_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER46_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER46_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER46_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER46_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER46_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER46_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER46_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER46_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER46_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER46_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER46_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER47 - GICD_IROUTER47 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER47_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER47_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER47_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER47_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER47_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER47_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER47_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER47_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER47_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER47_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER47_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER47_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER47_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER47_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER47_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER47_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER47_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER47_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER47_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER47_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER47_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER47_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER47_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER47_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER47_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER47_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER47_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER47_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER47_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER47_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER47_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER47_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER47_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER47_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER47_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER48 - GICD_IROUTER48 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER48_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER48_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER48_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER48_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER48_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER48_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER48_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER48_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER48_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER48_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER48_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER48_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER48_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER48_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER48_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER48_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER48_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER48_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER48_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER48_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER48_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER48_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER48_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER48_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER48_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER48_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER48_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER48_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER48_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER48_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER48_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER48_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER48_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER48_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER48_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER49 - GICD_IROUTER49 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER49_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER49_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER49_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER49_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER49_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER49_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER49_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER49_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER49_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER49_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER49_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER49_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER49_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER49_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER49_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER49_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER49_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER49_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER49_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER49_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER49_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER49_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER49_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER49_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER49_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER49_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER49_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER49_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER49_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER49_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER49_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER49_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER49_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER49_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER49_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER50 - GICD_IROUTER50 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER50_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER50_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER50_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER50_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER50_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER50_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER50_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER50_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER50_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER50_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER50_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER50_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER50_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER50_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER50_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER50_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER50_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER50_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER50_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER50_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER50_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER50_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER50_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER50_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER50_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER50_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER50_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER50_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER50_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER50_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER50_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER50_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER50_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER50_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER50_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER51 - GICD_IROUTER51 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER51_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER51_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER51_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER51_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER51_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER51_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER51_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER51_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER51_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER51_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER51_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER51_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER51_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER51_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER51_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER51_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER51_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER51_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER51_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER51_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER51_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER51_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER51_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER51_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER51_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER51_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER51_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER51_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER51_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER51_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER51_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER51_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER51_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER51_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER51_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER52 - GICD_IROUTER52 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER52_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER52_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER52_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER52_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER52_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER52_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER52_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER52_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER52_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER52_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER52_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER52_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER52_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER52_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER52_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER52_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER52_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER52_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER52_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER52_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER52_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER52_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER52_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER52_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER52_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER52_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER52_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER52_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER52_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER52_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER52_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER52_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER52_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER52_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER52_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER53 - GICD_IROUTER53 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER53_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER53_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER53_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER53_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER53_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER53_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER53_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER53_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER53_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER53_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER53_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER53_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER53_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER53_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER53_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER53_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER53_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER53_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER53_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER53_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER53_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER53_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER53_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER53_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER53_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER53_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER53_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER53_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER53_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER53_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER53_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER53_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER53_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER53_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER53_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER54 - GICD_IROUTER54 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER54_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER54_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER54_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER54_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER54_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER54_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER54_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER54_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER54_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER54_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER54_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER54_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER54_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER54_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER54_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER54_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER54_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER54_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER54_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER54_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER54_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER54_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER54_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER54_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER54_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER54_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER54_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER54_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER54_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER54_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER54_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER54_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER54_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER54_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER54_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER55 - GICD_IROUTER55 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER55_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER55_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER55_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER55_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER55_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER55_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER55_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER55_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER55_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER55_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER55_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER55_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER55_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER55_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER55_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER55_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER55_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER55_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER55_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER55_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER55_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER55_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER55_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER55_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER55_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER55_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER55_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER55_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER55_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER55_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER55_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER55_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER55_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER55_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER55_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER56 - GICD_IROUTER56 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER56_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER56_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER56_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER56_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER56_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER56_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER56_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER56_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER56_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER56_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER56_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER56_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER56_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER56_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER56_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER56_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER56_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER56_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER56_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER56_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER56_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER56_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER56_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER56_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER56_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER56_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER56_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER56_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER56_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER56_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER56_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER56_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER56_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER56_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER56_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER57 - GICD_IROUTER57 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER57_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER57_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER57_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER57_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER57_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER57_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER57_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER57_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER57_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER57_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER57_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER57_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER57_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER57_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER57_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER57_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER57_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER57_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER57_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER57_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER57_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER57_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER57_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER57_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER57_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER57_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER57_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER57_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER57_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER57_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER57_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER57_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER57_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER57_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER57_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER58 - GICD_IROUTER58 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER58_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER58_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER58_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER58_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER58_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER58_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER58_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER58_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER58_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER58_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER58_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER58_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER58_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER58_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER58_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER58_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER58_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER58_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER58_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER58_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER58_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER58_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER58_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER58_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER58_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER58_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER58_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER58_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER58_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER58_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER58_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER58_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER58_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER58_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER58_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER59 - GICD_IROUTER59 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER59_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER59_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER59_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER59_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER59_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER59_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER59_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER59_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER59_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER59_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER59_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER59_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER59_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER59_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER59_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER59_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER59_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER59_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER59_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER59_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER59_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER59_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER59_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER59_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER59_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER59_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER59_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER59_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER59_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER59_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER59_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER59_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER59_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER59_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER59_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER60 - GICD_IROUTER60 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER60_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER60_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER60_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER60_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER60_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER60_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER60_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER60_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER60_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER60_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER60_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER60_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER60_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER60_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER60_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER60_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER60_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER60_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER60_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER60_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER60_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER60_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER60_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER60_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER60_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER60_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER60_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER60_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER60_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER60_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER60_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER60_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER60_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER60_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER60_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER61 - GICD_IROUTER61 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER61_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER61_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER61_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER61_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER61_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER61_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER61_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER61_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER61_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER61_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER61_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER61_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER61_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER61_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER61_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER61_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER61_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER61_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER61_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER61_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER61_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER61_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER61_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER61_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER61_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER61_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER61_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER61_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER61_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER61_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER61_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER61_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER61_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER61_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER61_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER62 - GICD_IROUTER62 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER62_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER62_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER62_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER62_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER62_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER62_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER62_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER62_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER62_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER62_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER62_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER62_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER62_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER62_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER62_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER62_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER62_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER62_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER62_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER62_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER62_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER62_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER62_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER62_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER62_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER62_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER62_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER62_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER62_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER62_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER62_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER62_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER62_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER62_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER62_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER63 - GICD_IROUTER63 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER63_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER63_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER63_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER63_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER63_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER63_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER63_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER63_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER63_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER63_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER63_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER63_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER63_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER63_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER63_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER63_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER63_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER63_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER63_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER63_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER63_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER63_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER63_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER63_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER63_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER63_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER63_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER63_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER63_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER63_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER63_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER63_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER63_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER63_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER63_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER64 - GICD_IROUTER64 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER64_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER64_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER64_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER64_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER64_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER64_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER64_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER64_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER64_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER64_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER64_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER64_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER64_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER64_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER64_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER64_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER64_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER64_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER64_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER64_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER64_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER64_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER64_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER64_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER64_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER64_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER64_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER64_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER64_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER64_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER64_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER64_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER64_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER64_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER64_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER65 - GICD_IROUTER65 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER65_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER65_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER65_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER65_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER65_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER65_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER65_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER65_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER65_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER65_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER65_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER65_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER65_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER65_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER65_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER65_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER65_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER65_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER65_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER65_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER65_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER65_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER65_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER65_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER65_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER65_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER65_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER65_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER65_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER65_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER65_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER65_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER65_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER65_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER65_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER66 - GICD_IROUTER66 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER66_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER66_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER66_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER66_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER66_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER66_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER66_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER66_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER66_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER66_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER66_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER66_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER66_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER66_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER66_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER66_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER66_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER66_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER66_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER66_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER66_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER66_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER66_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER66_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER66_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER66_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER66_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER66_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER66_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER66_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER66_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER66_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER66_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER66_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER66_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER67 - GICD_IROUTER67 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER67_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER67_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER67_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER67_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER67_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER67_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER67_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER67_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER67_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER67_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER67_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER67_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER67_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER67_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER67_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER67_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER67_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER67_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER67_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER67_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER67_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER67_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER67_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER67_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER67_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER67_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER67_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER67_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER67_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER67_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER67_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER67_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER67_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER67_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER67_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER68 - GICD_IROUTER68 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER68_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER68_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER68_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER68_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER68_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER68_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER68_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER68_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER68_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER68_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER68_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER68_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER68_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER68_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER68_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER68_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER68_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER68_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER68_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER68_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER68_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER68_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER68_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER68_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER68_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER68_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER68_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER68_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER68_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER68_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER68_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER68_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER68_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER68_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER68_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER69 - GICD_IROUTER69 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER69_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER69_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER69_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER69_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER69_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER69_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER69_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER69_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER69_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER69_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER69_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER69_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER69_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER69_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER69_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER69_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER69_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER69_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER69_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER69_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER69_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER69_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER69_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER69_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER69_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER69_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER69_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER69_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER69_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER69_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER69_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER69_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER69_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER69_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER69_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER70 - GICD_IROUTER70 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER70_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER70_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER70_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER70_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER70_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER70_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER70_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER70_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER70_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER70_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER70_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER70_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER70_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER70_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER70_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER70_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER70_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER70_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER70_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER70_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER70_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER70_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER70_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER70_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER70_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER70_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER70_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER70_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER70_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER70_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER70_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER70_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER70_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER70_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER70_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER71 - GICD_IROUTER71 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER71_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER71_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER71_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER71_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER71_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER71_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER71_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER71_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER71_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER71_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER71_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER71_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER71_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER71_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER71_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER71_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER71_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER71_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER71_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER71_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER71_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER71_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER71_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER71_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER71_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER71_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER71_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER71_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER71_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER71_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER71_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER71_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER71_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER71_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER71_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER72 - GICD_IROUTER72 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER72_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER72_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER72_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER72_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER72_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER72_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER72_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER72_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER72_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER72_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER72_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER72_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER72_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER72_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER72_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER72_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER72_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER72_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER72_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER72_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER72_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER72_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER72_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER72_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER72_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER72_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER72_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER72_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER72_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER72_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER72_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER72_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER72_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER72_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER72_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER73 - GICD_IROUTER73 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER73_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER73_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER73_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER73_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER73_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER73_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER73_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER73_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER73_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER73_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER73_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER73_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER73_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER73_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER73_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER73_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER73_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER73_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER73_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER73_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER73_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER73_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER73_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER73_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER73_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER73_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER73_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER73_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER73_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER73_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER73_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER73_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER73_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER73_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER73_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER74 - GICD_IROUTER74 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER74_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER74_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER74_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER74_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER74_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER74_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER74_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER74_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER74_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER74_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER74_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER74_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER74_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER74_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER74_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER74_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER74_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER74_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER74_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER74_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER74_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER74_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER74_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER74_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER74_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER74_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER74_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER74_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER74_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER74_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER74_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER74_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER74_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER74_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER74_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER75 - GICD_IROUTER75 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER75_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER75_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER75_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER75_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER75_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER75_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER75_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER75_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER75_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER75_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER75_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER75_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER75_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER75_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER75_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER75_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER75_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER75_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER75_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER75_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER75_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER75_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER75_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER75_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER75_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER75_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER75_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER75_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER75_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER75_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER75_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER75_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER75_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER75_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER75_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER76 - GICD_IROUTER76 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER76_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER76_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER76_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER76_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER76_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER76_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER76_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER76_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER76_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER76_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER76_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER76_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER76_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER76_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER76_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER76_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER76_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER76_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER76_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER76_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER76_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER76_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER76_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER76_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER76_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER76_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER76_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER76_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER76_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER76_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER76_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER76_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER76_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER76_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER76_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER77 - GICD_IROUTER77 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER77_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER77_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER77_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER77_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER77_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER77_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER77_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER77_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER77_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER77_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER77_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER77_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER77_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER77_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER77_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER77_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER77_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER77_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER77_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER77_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER77_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER77_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER77_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER77_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER77_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER77_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER77_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER77_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER77_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER77_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER77_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER77_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER77_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER77_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER77_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER78 - GICD_IROUTER78 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER78_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER78_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER78_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER78_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER78_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER78_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER78_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER78_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER78_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER78_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER78_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER78_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER78_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER78_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER78_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER78_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER78_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER78_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER78_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER78_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER78_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER78_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER78_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER78_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER78_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER78_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER78_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER78_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER78_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER78_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER78_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER78_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER78_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER78_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER78_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER79 - GICD_IROUTER79 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER79_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER79_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER79_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER79_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER79_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER79_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER79_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER79_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER79_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER79_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER79_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER79_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER79_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER79_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER79_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER79_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER79_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER79_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER79_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER79_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER79_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER79_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER79_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER79_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER79_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER79_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER79_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER79_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER79_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER79_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER79_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER79_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER79_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER79_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER79_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER80 - GICD_IROUTER80 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER80_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER80_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER80_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER80_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER80_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER80_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER80_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER80_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER80_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER80_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER80_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER80_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER80_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER80_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER80_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER80_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER80_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER80_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER80_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER80_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER80_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER80_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER80_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER80_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER80_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER80_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER80_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER80_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER80_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER80_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER80_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER80_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER80_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER80_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER80_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER81 - GICD_IROUTER81 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER81_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER81_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER81_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER81_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER81_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER81_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER81_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER81_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER81_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER81_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER81_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER81_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER81_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER81_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER81_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER81_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER81_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER81_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER81_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER81_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER81_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER81_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER81_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER81_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER81_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER81_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER81_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER81_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER81_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER81_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER81_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER81_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER81_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER81_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER81_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER82 - GICD_IROUTER82 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER82_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER82_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER82_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER82_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER82_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER82_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER82_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER82_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER82_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER82_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER82_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER82_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER82_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER82_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER82_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER82_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER82_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER82_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER82_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER82_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER82_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER82_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER82_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER82_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER82_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER82_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER82_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER82_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER82_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER82_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER82_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER82_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER82_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER82_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER82_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER83 - GICD_IROUTER83 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER83_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER83_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER83_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER83_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER83_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER83_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER83_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER83_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER83_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER83_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER83_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER83_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER83_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER83_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER83_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER83_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER83_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER83_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER83_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER83_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER83_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER83_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER83_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER83_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER83_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER83_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER83_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER83_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER83_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER83_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER83_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER83_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER83_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER83_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER83_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER84 - GICD_IROUTER84 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER84_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER84_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER84_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER84_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER84_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER84_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER84_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER84_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER84_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER84_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER84_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER84_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER84_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER84_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER84_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER84_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER84_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER84_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER84_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER84_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER84_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER84_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER84_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER84_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER84_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER84_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER84_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER84_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER84_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER84_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER84_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER84_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER84_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER84_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER84_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER85 - GICD_IROUTER85 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER85_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER85_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER85_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER85_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER85_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER85_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER85_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER85_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER85_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER85_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER85_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER85_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER85_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER85_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER85_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER85_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER85_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER85_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER85_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER85_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER85_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER85_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER85_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER85_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER85_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER85_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER85_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER85_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER85_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER85_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER85_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER85_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER85_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER85_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER85_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER86 - GICD_IROUTER86 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER86_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER86_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER86_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER86_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER86_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER86_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER86_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER86_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER86_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER86_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER86_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER86_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER86_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER86_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER86_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER86_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER86_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER86_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER86_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER86_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER86_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER86_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER86_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER86_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER86_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER86_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER86_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER86_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER86_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER86_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER86_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER86_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER86_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER86_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER86_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER87 - GICD_IROUTER87 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER87_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER87_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER87_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER87_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER87_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER87_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER87_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER87_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER87_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER87_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER87_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER87_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER87_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER87_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER87_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER87_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER87_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER87_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER87_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER87_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER87_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER87_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER87_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER87_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER87_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER87_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER87_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER87_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER87_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER87_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER87_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER87_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER87_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER87_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER87_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER88 - GICD_IROUTER88 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER88_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER88_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER88_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER88_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER88_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER88_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER88_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER88_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER88_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER88_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER88_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER88_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER88_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER88_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER88_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER88_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER88_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER88_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER88_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER88_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER88_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER88_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER88_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER88_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER88_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER88_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER88_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER88_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER88_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER88_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER88_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER88_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER88_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER88_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER88_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER89 - GICD_IROUTER89 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER89_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER89_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER89_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER89_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER89_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER89_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER89_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER89_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER89_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER89_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER89_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER89_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER89_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER89_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER89_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER89_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER89_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER89_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER89_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER89_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER89_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER89_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER89_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER89_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER89_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER89_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER89_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER89_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER89_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER89_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER89_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER89_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER89_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER89_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER89_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER90 - GICD_IROUTER90 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER90_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER90_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER90_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER90_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER90_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER90_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER90_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER90_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER90_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER90_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER90_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER90_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER90_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER90_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER90_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER90_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER90_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER90_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER90_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER90_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER90_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER90_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER90_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER90_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER90_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER90_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER90_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER90_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER90_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER90_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER90_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER90_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER90_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER90_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER90_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER91 - GICD_IROUTER91 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER91_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER91_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER91_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER91_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER91_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER91_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER91_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER91_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER91_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER91_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER91_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER91_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER91_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER91_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER91_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER91_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER91_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER91_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER91_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER91_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER91_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER91_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER91_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER91_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER91_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER91_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER91_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER91_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER91_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER91_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER91_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER91_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER91_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER91_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER91_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER92 - GICD_IROUTER92 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER92_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER92_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER92_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER92_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER92_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER92_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER92_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER92_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER92_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER92_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER92_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER92_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER92_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER92_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER92_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER92_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER92_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER92_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER92_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER92_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER92_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER92_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER92_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER92_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER92_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER92_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER92_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER92_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER92_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER92_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER92_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER92_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER92_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER92_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER92_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER93 - GICD_IROUTER93 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER93_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER93_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER93_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER93_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER93_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER93_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER93_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER93_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER93_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER93_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER93_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER93_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER93_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER93_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER93_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER93_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER93_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER93_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER93_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER93_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER93_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER93_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER93_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER93_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER93_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER93_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER93_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER93_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER93_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER93_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER93_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER93_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER93_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER93_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER93_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER94 - GICD_IROUTER94 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER94_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER94_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER94_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER94_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER94_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER94_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER94_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER94_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER94_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER94_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER94_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER94_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER94_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER94_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER94_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER94_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER94_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER94_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER94_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER94_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER94_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER94_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER94_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER94_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER94_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER94_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER94_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER94_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER94_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER94_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER94_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER94_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER94_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER94_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER94_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER95 - GICD_IROUTER95 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER95_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER95_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER95_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER95_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER95_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER95_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER95_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER95_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER95_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER95_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER95_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER95_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER95_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER95_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER95_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER95_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER95_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER95_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER95_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER95_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER95_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER95_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER95_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER95_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER95_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER95_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER95_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER95_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER95_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER95_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER95_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER95_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER95_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER95_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER95_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER96 - GICD_IROUTER96 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER96_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER96_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER96_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER96_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER96_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER96_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER96_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER96_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER96_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER96_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER96_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER96_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER96_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER96_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER96_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER96_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER96_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER96_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER96_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER96_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER96_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER96_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER96_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER96_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER96_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER96_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER96_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER96_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER96_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER96_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER96_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER96_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER96_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER96_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER96_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER97 - GICD_IROUTER97 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER97_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER97_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER97_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER97_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER97_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER97_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER97_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER97_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER97_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER97_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER97_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER97_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER97_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER97_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER97_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER97_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER97_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER97_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER97_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER97_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER97_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER97_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER97_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER97_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER97_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER97_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER97_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER97_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER97_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER97_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER97_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER97_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER97_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER97_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER97_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER98 - GICD_IROUTER98 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER98_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER98_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER98_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER98_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER98_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER98_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER98_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER98_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER98_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER98_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER98_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER98_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER98_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER98_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER98_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER98_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER98_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER98_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER98_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER98_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER98_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER98_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER98_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER98_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER98_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER98_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER98_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER98_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER98_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER98_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER98_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER98_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER98_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER98_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER98_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER99 - GICD_IROUTER99 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER99_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER99_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER99_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER99_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER99_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER99_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER99_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER99_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER99_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER99_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER99_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER99_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER99_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER99_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER99_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER99_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER99_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER99_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER99_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER99_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER99_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER99_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER99_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER99_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER99_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER99_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER99_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER99_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER99_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER99_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER99_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER99_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER99_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER99_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER99_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER100 - GICD_IROUTER100 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER100_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER100_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER100_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER100_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER100_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER100_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER100_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER100_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER100_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER100_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER100_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER100_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER100_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER100_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER100_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER100_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER100_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER100_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER100_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER100_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER100_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER100_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER100_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER100_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER100_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER100_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER100_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER100_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER100_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER100_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER100_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER100_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER100_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER100_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER100_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER101 - GICD_IROUTER101 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER101_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER101_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER101_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER101_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER101_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER101_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER101_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER101_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER101_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER101_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER101_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER101_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER101_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER101_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER101_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER101_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER101_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER101_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER101_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER101_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER101_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER101_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER101_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER101_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER101_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER101_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER101_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER101_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER101_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER101_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER101_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER101_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER101_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER101_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER101_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER102 - GICD_IROUTER102 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER102_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER102_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER102_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER102_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER102_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER102_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER102_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER102_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER102_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER102_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER102_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER102_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER102_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER102_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER102_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER102_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER102_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER102_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER102_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER102_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER102_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER102_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER102_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER102_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER102_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER102_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER102_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER102_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER102_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER102_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER102_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER102_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER102_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER102_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER102_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER103 - GICD_IROUTER103 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER103_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER103_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER103_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER103_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER103_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER103_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER103_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER103_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER103_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER103_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER103_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER103_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER103_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER103_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER103_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER103_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER103_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER103_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER103_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER103_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER103_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER103_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER103_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER103_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER103_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER103_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER103_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER103_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER103_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER103_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER103_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER103_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER103_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER103_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER103_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER104 - GICD_IROUTER104 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER104_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER104_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER104_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER104_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER104_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER104_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER104_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER104_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER104_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER104_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER104_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER104_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER104_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER104_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER104_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER104_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER104_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER104_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER104_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER104_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER104_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER104_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER104_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER104_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER104_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER104_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER104_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER104_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER104_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER104_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER104_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER104_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER104_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER104_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER104_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER105 - GICD_IROUTER105 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER105_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER105_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER105_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER105_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER105_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER105_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER105_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER105_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER105_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER105_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER105_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER105_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER105_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER105_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER105_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER105_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER105_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER105_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER105_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER105_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER105_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER105_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER105_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER105_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER105_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER105_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER105_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER105_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER105_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER105_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER105_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER105_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER105_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER105_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER105_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER106 - GICD_IROUTER106 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER106_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER106_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER106_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER106_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER106_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER106_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER106_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER106_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER106_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER106_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER106_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER106_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER106_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER106_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER106_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER106_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER106_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER106_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER106_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER106_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER106_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER106_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER106_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER106_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER106_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER106_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER106_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER106_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER106_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER106_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER106_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER106_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER106_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER106_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER106_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER107 - GICD_IROUTER107 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER107_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER107_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER107_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER107_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER107_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER107_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER107_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER107_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER107_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER107_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER107_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER107_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER107_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER107_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER107_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER107_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER107_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER107_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER107_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER107_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER107_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER107_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER107_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER107_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER107_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER107_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER107_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER107_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER107_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER107_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER107_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER107_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER107_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER107_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER107_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER108 - GICD_IROUTER108 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER108_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER108_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER108_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER108_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER108_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER108_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER108_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER108_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER108_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER108_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER108_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER108_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER108_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER108_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER108_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER108_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER108_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER108_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER108_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER108_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER108_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER108_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER108_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER108_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER108_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER108_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER108_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER108_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER108_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER108_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER108_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER108_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER108_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER108_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER108_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER109 - GICD_IROUTER109 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER109_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER109_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER109_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER109_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER109_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER109_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER109_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER109_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER109_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER109_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER109_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER109_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER109_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER109_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER109_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER109_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER109_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER109_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER109_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER109_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER109_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER109_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER109_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER109_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER109_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER109_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER109_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER109_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER109_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER109_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER109_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER109_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER109_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER109_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER109_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER110 - GICD_IROUTER110 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER110_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER110_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER110_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER110_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER110_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER110_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER110_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER110_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER110_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER110_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER110_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER110_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER110_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER110_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER110_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER110_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER110_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER110_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER110_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER110_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER110_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER110_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER110_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER110_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER110_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER110_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER110_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER110_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER110_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER110_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER110_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER110_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER110_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER110_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER110_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER111 - GICD_IROUTER111 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER111_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER111_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER111_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER111_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER111_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER111_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER111_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER111_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER111_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER111_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER111_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER111_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER111_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER111_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER111_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER111_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER111_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER111_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER111_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER111_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER111_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER111_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER111_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER111_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER111_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER111_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER111_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER111_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER111_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER111_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER111_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER111_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER111_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER111_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER111_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER112 - GICD_IROUTER112 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER112_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER112_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER112_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER112_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER112_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER112_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER112_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER112_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER112_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER112_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER112_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER112_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER112_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER112_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER112_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER112_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER112_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER112_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER112_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER112_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER112_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER112_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER112_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER112_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER112_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER112_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER112_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER112_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER112_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER112_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER112_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER112_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER112_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER112_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER112_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER113 - GICD_IROUTER113 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER113_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER113_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER113_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER113_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER113_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER113_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER113_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER113_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER113_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER113_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER113_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER113_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER113_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER113_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER113_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER113_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER113_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER113_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER113_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER113_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER113_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER113_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER113_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER113_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER113_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER113_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER113_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER113_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER113_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER113_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER113_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER113_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER113_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER113_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER113_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER114 - GICD_IROUTER114 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER114_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER114_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER114_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER114_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER114_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER114_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER114_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER114_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER114_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER114_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER114_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER114_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER114_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER114_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER114_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER114_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER114_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER114_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER114_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER114_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER114_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER114_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER114_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER114_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER114_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER114_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER114_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER114_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER114_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER114_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER114_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER114_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER114_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER114_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER114_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER115 - GICD_IROUTER115 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER115_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER115_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER115_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER115_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER115_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER115_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER115_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER115_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER115_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER115_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER115_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER115_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER115_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER115_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER115_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER115_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER115_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER115_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER115_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER115_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER115_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER115_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER115_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER115_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER115_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER115_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER115_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER115_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER115_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER115_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER115_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER115_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER115_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER115_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER115_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER116 - GICD_IROUTER116 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER116_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER116_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER116_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER116_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER116_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER116_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER116_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER116_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER116_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER116_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER116_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER116_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER116_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER116_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER116_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER116_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER116_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER116_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER116_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER116_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER116_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER116_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER116_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER116_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER116_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER116_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER116_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER116_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER116_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER116_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER116_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER116_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER116_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER116_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER116_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER117 - GICD_IROUTER117 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER117_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER117_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER117_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER117_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER117_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER117_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER117_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER117_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER117_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER117_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER117_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER117_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER117_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER117_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER117_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER117_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER117_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER117_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER117_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER117_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER117_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER117_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER117_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER117_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER117_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER117_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER117_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER117_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER117_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER117_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER117_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER117_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER117_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER117_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER117_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER118 - GICD_IROUTER118 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER118_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER118_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER118_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER118_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER118_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER118_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER118_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER118_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER118_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER118_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER118_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER118_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER118_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER118_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER118_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER118_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER118_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER118_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER118_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER118_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER118_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER118_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER118_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER118_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER118_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER118_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER118_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER118_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER118_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER118_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER118_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER118_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER118_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER118_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER118_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER119 - GICD_IROUTER119 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER119_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER119_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER119_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER119_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER119_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER119_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER119_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER119_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER119_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER119_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER119_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER119_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER119_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER119_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER119_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER119_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER119_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER119_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER119_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER119_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER119_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER119_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER119_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER119_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER119_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER119_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER119_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER119_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER119_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER119_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER119_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER119_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER119_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER119_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER119_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER120 - GICD_IROUTER120 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER120_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER120_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER120_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER120_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER120_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER120_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER120_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER120_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER120_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER120_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER120_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER120_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER120_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER120_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER120_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER120_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER120_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER120_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER120_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER120_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER120_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER120_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER120_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER120_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER120_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER120_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER120_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER120_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER120_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER120_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER120_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER120_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER120_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER120_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER120_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER121 - GICD_IROUTER121 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER121_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER121_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER121_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER121_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER121_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER121_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER121_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER121_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER121_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER121_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER121_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER121_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER121_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER121_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER121_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER121_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER121_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER121_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER121_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER121_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER121_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER121_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER121_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER121_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER121_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER121_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER121_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER121_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER121_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER121_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER121_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER121_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER121_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER121_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER121_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER122 - GICD_IROUTER122 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER122_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER122_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER122_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER122_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER122_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER122_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER122_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER122_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER122_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER122_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER122_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER122_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER122_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER122_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER122_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER122_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER122_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER122_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER122_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER122_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER122_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER122_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER122_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER122_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER122_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER122_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER122_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER122_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER122_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER122_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER122_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER122_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER122_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER122_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER122_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER123 - GICD_IROUTER123 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER123_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER123_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER123_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER123_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER123_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER123_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER123_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER123_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER123_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER123_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER123_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER123_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER123_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER123_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER123_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER123_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER123_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER123_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER123_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER123_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER123_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER123_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER123_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER123_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER123_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER123_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER123_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER123_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER123_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER123_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER123_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER123_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER123_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER123_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER123_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER124 - GICD_IROUTER124 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER124_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER124_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER124_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER124_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER124_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER124_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER124_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER124_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER124_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER124_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER124_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER124_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER124_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER124_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER124_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER124_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER124_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER124_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER124_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER124_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER124_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER124_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER124_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER124_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER124_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER124_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER124_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER124_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER124_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER124_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER124_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER124_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER124_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER124_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER124_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER125 - GICD_IROUTER125 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER125_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER125_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER125_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER125_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER125_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER125_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER125_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER125_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER125_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER125_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER125_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER125_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER125_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER125_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER125_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER125_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER125_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER125_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER125_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER125_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER125_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER125_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER125_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER125_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER125_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER125_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER125_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER125_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER125_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER125_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER125_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER125_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER125_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER125_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER125_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER126 - GICD_IROUTER126 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER126_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER126_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER126_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER126_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER126_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER126_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER126_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER126_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER126_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER126_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER126_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER126_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER126_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER126_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER126_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER126_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER126_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER126_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER126_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER126_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER126_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER126_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER126_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER126_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER126_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER126_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER126_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER126_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER126_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER126_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER126_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER126_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER126_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER126_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER126_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER127 - GICD_IROUTER127 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER127_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER127_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER127_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER127_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER127_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER127_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER127_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER127_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER127_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER127_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER127_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER127_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER127_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER127_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER127_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER127_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER127_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER127_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER127_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER127_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER127_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER127_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER127_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER127_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER127_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER127_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER127_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER127_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER127_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER127_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER127_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER127_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER127_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER127_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER127_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER128 - GICD_IROUTER128 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER128_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER128_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER128_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER128_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER128_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER128_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER128_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER128_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER128_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER128_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER128_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER128_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER128_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER128_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER128_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER128_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER128_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER128_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER128_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER128_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER128_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER128_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER128_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER128_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER128_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER128_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER128_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER128_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER128_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER128_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER128_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER128_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER128_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER128_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER128_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER129 - GICD_IROUTER129 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER129_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER129_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER129_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER129_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER129_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER129_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER129_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER129_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER129_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER129_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER129_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER129_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER129_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER129_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER129_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER129_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER129_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER129_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER129_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER129_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER129_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER129_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER129_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER129_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER129_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER129_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER129_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER129_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER129_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER129_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER129_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER129_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER129_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER129_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER129_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER130 - GICD_IROUTER130 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER130_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER130_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER130_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER130_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER130_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER130_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER130_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER130_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER130_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER130_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER130_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER130_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER130_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER130_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER130_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER130_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER130_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER130_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER130_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER130_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER130_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER130_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER130_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER130_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER130_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER130_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER130_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER130_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER130_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER130_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER130_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER130_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER130_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER130_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER130_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER131 - GICD_IROUTER131 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER131_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER131_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER131_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER131_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER131_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER131_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER131_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER131_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER131_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER131_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER131_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER131_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER131_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER131_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER131_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER131_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER131_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER131_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER131_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER131_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER131_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER131_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER131_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER131_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER131_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER131_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER131_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER131_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER131_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER131_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER131_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER131_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER131_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER131_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER131_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER132 - GICD_IROUTER132 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER132_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER132_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER132_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER132_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER132_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER132_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER132_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER132_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER132_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER132_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER132_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER132_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER132_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER132_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER132_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER132_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER132_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER132_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER132_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER132_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER132_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER132_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER132_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER132_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER132_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER132_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER132_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER132_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER132_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER132_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER132_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER132_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER132_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER132_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER132_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER133 - GICD_IROUTER133 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER133_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER133_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER133_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER133_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER133_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER133_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER133_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER133_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER133_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER133_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER133_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER133_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER133_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER133_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER133_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER133_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER133_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER133_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER133_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER133_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER133_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER133_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER133_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER133_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER133_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER133_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER133_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER133_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER133_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER133_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER133_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER133_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER133_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER133_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER133_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER134 - GICD_IROUTER134 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER134_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER134_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER134_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER134_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER134_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER134_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER134_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER134_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER134_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER134_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER134_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER134_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER134_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER134_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER134_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER134_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER134_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER134_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER134_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER134_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER134_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER134_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER134_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER134_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER134_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER134_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER134_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER134_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER134_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER134_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER134_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER134_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER134_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER134_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER134_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER135 - GICD_IROUTER135 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER135_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER135_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER135_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER135_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER135_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER135_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER135_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER135_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER135_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER135_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER135_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER135_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER135_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER135_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER135_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER135_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER135_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER135_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER135_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER135_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER135_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER135_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER135_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER135_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER135_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER135_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER135_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER135_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER135_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER135_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER135_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER135_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER135_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER135_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER135_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER136 - GICD_IROUTER136 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER136_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER136_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER136_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER136_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER136_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER136_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER136_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER136_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER136_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER136_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER136_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER136_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER136_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER136_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER136_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER136_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER136_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER136_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER136_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER136_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER136_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER136_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER136_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER136_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER136_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER136_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER136_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER136_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER136_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER136_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER136_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER136_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER136_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER136_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER136_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER137 - GICD_IROUTER137 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER137_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER137_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER137_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER137_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER137_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER137_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER137_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER137_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER137_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER137_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER137_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER137_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER137_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER137_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER137_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER137_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER137_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER137_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER137_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER137_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER137_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER137_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER137_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER137_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER137_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER137_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER137_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER137_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER137_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER137_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER137_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER137_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER137_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER137_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER137_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER138 - GICD_IROUTER138 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER138_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER138_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER138_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER138_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER138_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER138_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER138_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER138_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER138_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER138_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER138_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER138_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER138_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER138_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER138_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER138_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER138_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER138_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER138_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER138_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER138_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER138_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER138_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER138_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER138_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER138_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER138_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER138_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER138_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER138_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER138_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER138_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER138_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER138_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER138_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER139 - GICD_IROUTER139 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER139_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER139_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER139_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER139_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER139_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER139_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER139_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER139_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER139_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER139_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER139_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER139_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER139_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER139_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER139_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER139_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER139_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER139_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER139_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER139_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER139_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER139_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER139_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER139_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER139_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER139_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER139_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER139_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER139_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER139_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER139_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER139_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER139_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER139_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER139_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER140 - GICD_IROUTER140 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER140_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER140_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER140_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER140_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER140_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER140_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER140_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER140_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER140_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER140_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER140_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER140_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER140_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER140_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER140_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER140_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER140_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER140_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER140_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER140_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER140_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER140_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER140_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER140_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER140_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER140_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER140_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER140_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER140_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER140_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER140_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER140_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER140_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER140_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER140_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER141 - GICD_IROUTER141 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER141_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER141_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER141_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER141_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER141_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER141_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER141_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER141_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER141_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER141_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER141_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER141_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER141_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER141_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER141_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER141_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER141_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER141_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER141_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER141_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER141_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER141_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER141_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER141_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER141_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER141_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER141_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER141_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER141_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER141_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER141_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER141_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER141_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER141_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER141_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER142 - GICD_IROUTER142 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER142_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER142_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER142_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER142_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER142_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER142_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER142_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER142_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER142_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER142_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER142_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER142_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER142_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER142_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER142_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER142_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER142_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER142_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER142_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER142_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER142_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER142_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER142_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER142_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER142_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER142_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER142_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER142_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER142_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER142_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER142_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER142_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER142_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER142_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER142_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER143 - GICD_IROUTER143 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER143_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER143_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER143_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER143_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER143_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER143_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER143_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER143_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER143_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER143_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER143_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER143_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER143_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER143_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER143_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER143_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER143_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER143_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER143_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER143_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER143_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER143_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER143_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER143_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER143_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER143_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER143_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER143_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER143_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER143_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER143_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER143_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER143_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER143_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER143_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER144 - GICD_IROUTER144 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER144_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER144_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER144_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER144_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER144_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER144_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER144_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER144_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER144_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER144_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER144_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER144_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER144_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER144_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER144_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER144_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER144_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER144_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER144_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER144_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER144_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER144_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER144_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER144_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER144_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER144_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER144_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER144_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER144_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER144_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER144_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER144_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER144_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER144_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER144_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER145 - GICD_IROUTER145 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER145_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER145_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER145_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER145_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER145_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER145_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER145_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER145_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER145_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER145_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER145_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER145_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER145_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER145_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER145_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER145_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER145_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER145_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER145_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER145_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER145_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER145_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER145_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER145_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER145_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER145_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER145_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER145_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER145_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER145_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER145_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER145_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER145_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER145_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER145_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER146 - GICD_IROUTER146 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER146_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER146_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER146_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER146_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER146_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER146_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER146_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER146_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER146_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER146_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER146_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER146_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER146_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER146_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER146_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER146_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER146_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER146_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER146_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER146_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER146_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER146_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER146_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER146_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER146_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER146_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER146_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER146_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER146_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER146_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER146_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER146_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER146_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER146_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER146_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER147 - GICD_IROUTER147 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER147_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER147_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER147_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER147_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER147_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER147_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER147_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER147_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER147_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER147_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER147_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER147_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER147_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER147_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER147_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER147_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER147_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER147_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER147_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER147_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER147_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER147_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER147_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER147_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER147_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER147_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER147_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER147_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER147_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER147_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER147_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER147_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER147_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER147_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER147_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER148 - GICD_IROUTER148 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER148_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER148_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER148_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER148_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER148_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER148_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER148_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER148_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER148_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER148_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER148_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER148_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER148_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER148_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER148_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER148_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER148_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER148_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER148_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER148_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER148_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER148_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER148_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER148_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER148_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER148_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER148_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER148_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER148_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER148_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER148_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER148_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER148_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER148_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER148_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER149 - GICD_IROUTER149 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER149_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER149_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER149_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER149_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER149_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER149_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER149_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER149_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER149_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER149_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER149_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER149_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER149_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER149_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER149_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER149_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER149_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER149_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER149_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER149_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER149_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER149_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER149_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER149_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER149_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER149_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER149_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER149_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER149_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER149_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER149_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER149_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER149_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER149_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER149_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER150 - GICD_IROUTER150 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER150_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER150_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER150_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER150_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER150_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER150_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER150_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER150_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER150_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER150_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER150_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER150_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER150_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER150_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER150_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER150_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER150_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER150_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER150_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER150_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER150_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER150_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER150_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER150_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER150_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER150_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER150_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER150_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER150_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER150_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER150_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER150_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER150_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER150_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER150_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER151 - GICD_IROUTER151 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER151_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER151_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER151_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER151_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER151_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER151_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER151_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER151_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER151_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER151_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER151_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER151_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER151_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER151_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER151_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER151_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER151_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER151_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER151_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER151_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER151_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER151_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER151_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER151_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER151_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER151_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER151_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER151_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER151_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER151_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER151_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER151_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER151_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER151_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER151_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER152 - GICD_IROUTER152 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER152_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER152_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER152_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER152_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER152_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER152_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER152_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER152_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER152_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER152_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER152_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER152_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER152_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER152_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER152_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER152_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER152_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER152_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER152_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER152_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER152_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER152_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER152_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER152_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER152_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER152_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER152_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER152_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER152_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER152_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER152_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER152_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER152_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER152_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER152_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER153 - GICD_IROUTER153 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER153_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER153_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER153_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER153_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER153_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER153_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER153_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER153_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER153_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER153_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER153_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER153_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER153_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER153_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER153_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER153_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER153_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER153_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER153_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER153_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER153_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER153_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER153_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER153_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER153_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER153_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER153_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER153_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER153_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER153_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER153_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER153_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER153_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER153_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER153_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER154 - GICD_IROUTER154 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER154_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER154_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER154_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER154_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER154_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER154_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER154_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER154_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER154_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER154_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER154_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER154_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER154_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER154_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER154_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER154_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER154_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER154_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER154_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER154_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER154_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER154_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER154_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER154_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER154_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER154_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER154_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER154_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER154_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER154_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER154_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER154_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER154_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER154_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER154_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER155 - GICD_IROUTER155 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER155_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER155_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER155_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER155_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER155_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER155_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER155_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER155_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER155_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER155_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER155_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER155_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER155_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER155_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER155_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER155_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER155_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER155_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER155_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER155_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER155_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER155_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER155_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER155_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER155_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER155_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER155_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER155_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER155_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER155_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER155_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER155_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER155_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER155_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER155_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER156 - GICD_IROUTER156 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER156_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER156_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER156_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER156_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER156_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER156_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER156_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER156_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER156_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER156_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER156_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER156_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER156_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER156_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER156_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER156_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER156_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER156_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER156_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER156_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER156_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER156_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER156_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER156_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER156_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER156_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER156_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER156_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER156_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER156_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER156_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER156_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER156_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER156_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER156_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER157 - GICD_IROUTER157 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER157_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER157_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER157_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER157_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER157_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER157_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER157_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER157_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER157_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER157_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER157_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER157_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER157_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER157_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER157_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER157_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER157_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER157_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER157_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER157_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER157_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER157_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER157_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER157_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER157_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER157_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER157_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER157_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER157_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER157_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER157_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER157_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER157_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER157_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER157_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER158 - GICD_IROUTER158 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER158_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER158_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER158_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER158_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER158_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER158_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER158_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER158_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER158_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER158_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER158_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER158_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER158_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER158_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER158_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER158_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER158_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER158_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER158_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER158_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER158_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER158_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER158_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER158_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER158_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER158_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER158_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER158_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER158_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER158_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER158_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER158_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER158_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER158_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER158_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER159 - GICD_IROUTER159 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER159_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER159_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER159_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER159_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER159_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER159_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER159_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER159_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER159_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER159_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER159_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER159_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER159_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER159_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER159_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER159_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER159_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER159_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER159_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER159_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER159_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER159_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER159_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER159_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER159_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER159_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER159_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER159_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER159_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER159_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER159_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER159_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER159_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER159_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER159_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER160 - GICD_IROUTER160 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER160_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER160_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER160_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER160_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER160_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER160_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER160_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER160_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER160_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER160_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER160_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER160_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER160_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER160_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER160_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER160_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER160_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER160_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER160_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER160_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER160_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER160_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER160_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER160_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER160_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER160_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER160_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER160_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER160_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER160_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER160_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER160_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER160_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER160_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER160_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER161 - GICD_IROUTER161 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER161_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER161_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER161_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER161_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER161_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER161_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER161_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER161_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER161_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER161_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER161_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER161_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER161_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER161_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER161_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER161_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER161_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER161_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER161_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER161_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER161_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER161_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER161_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER161_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER161_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER161_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER161_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER161_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER161_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER161_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER161_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER161_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER161_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER161_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER161_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER162 - GICD_IROUTER162 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER162_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER162_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER162_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER162_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER162_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER162_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER162_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER162_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER162_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER162_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER162_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER162_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER162_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER162_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER162_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER162_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER162_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER162_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER162_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER162_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER162_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER162_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER162_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER162_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER162_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER162_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER162_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER162_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER162_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER162_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER162_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER162_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER162_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER162_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER162_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER163 - GICD_IROUTER163 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER163_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER163_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER163_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER163_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER163_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER163_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER163_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER163_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER163_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER163_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER163_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER163_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER163_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER163_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER163_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER163_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER163_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER163_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER163_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER163_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER163_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER163_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER163_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER163_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER163_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER163_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER163_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER163_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER163_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER163_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER163_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER163_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER163_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER163_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER163_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER164 - GICD_IROUTER164 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER164_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER164_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER164_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER164_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER164_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER164_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER164_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER164_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER164_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER164_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER164_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER164_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER164_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER164_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER164_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER164_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER164_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER164_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER164_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER164_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER164_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER164_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER164_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER164_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER164_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER164_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER164_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER164_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER164_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER164_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER164_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER164_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER164_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER164_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER164_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER165 - GICD_IROUTER165 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER165_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER165_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER165_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER165_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER165_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER165_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER165_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER165_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER165_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER165_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER165_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER165_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER165_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER165_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER165_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER165_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER165_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER165_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER165_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER165_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER165_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER165_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER165_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER165_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER165_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER165_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER165_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER165_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER165_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER165_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER165_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER165_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER165_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER165_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER165_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER166 - GICD_IROUTER166 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER166_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER166_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER166_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER166_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER166_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER166_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER166_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER166_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER166_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER166_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER166_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER166_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER166_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER166_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER166_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER166_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER166_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER166_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER166_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER166_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER166_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER166_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER166_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER166_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER166_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER166_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER166_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER166_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER166_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER166_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER166_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER166_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER166_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER166_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER166_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER167 - GICD_IROUTER167 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER167_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER167_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER167_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER167_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER167_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER167_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER167_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER167_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER167_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER167_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER167_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER167_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER167_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER167_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER167_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER167_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER167_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER167_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER167_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER167_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER167_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER167_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER167_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER167_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER167_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER167_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER167_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER167_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER167_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER167_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER167_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER167_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER167_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER167_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER167_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER168 - GICD_IROUTER168 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER168_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER168_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER168_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER168_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER168_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER168_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER168_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER168_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER168_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER168_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER168_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER168_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER168_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER168_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER168_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER168_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER168_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER168_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER168_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER168_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER168_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER168_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER168_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER168_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER168_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER168_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER168_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER168_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER168_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER168_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER168_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER168_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER168_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER168_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER168_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER169 - GICD_IROUTER169 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER169_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER169_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER169_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER169_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER169_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER169_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER169_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER169_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER169_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER169_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER169_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER169_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER169_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER169_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER169_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER169_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER169_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER169_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER169_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER169_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER169_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER169_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER169_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER169_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER169_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER169_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER169_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER169_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER169_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER169_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER169_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER169_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER169_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER169_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER169_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER170 - GICD_IROUTER170 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER170_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER170_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER170_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER170_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER170_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER170_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER170_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER170_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER170_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER170_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER170_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER170_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER170_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER170_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER170_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER170_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER170_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER170_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER170_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER170_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER170_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER170_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER170_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER170_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER170_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER170_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER170_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER170_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER170_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER170_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER170_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER170_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER170_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER170_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER170_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER171 - GICD_IROUTER171 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER171_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER171_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER171_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER171_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER171_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER171_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER171_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER171_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER171_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER171_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER171_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER171_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER171_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER171_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER171_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER171_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER171_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER171_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER171_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER171_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER171_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER171_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER171_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER171_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER171_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER171_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER171_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER171_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER171_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER171_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER171_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER171_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER171_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER171_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER171_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER172 - GICD_IROUTER172 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER172_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER172_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER172_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER172_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER172_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER172_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER172_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER172_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER172_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER172_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER172_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER172_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER172_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER172_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER172_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER172_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER172_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER172_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER172_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER172_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER172_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER172_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER172_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER172_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER172_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER172_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER172_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER172_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER172_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER172_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER172_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER172_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER172_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER172_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER172_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER173 - GICD_IROUTER173 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER173_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER173_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER173_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER173_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER173_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER173_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER173_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER173_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER173_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER173_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER173_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER173_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER173_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER173_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER173_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER173_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER173_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER173_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER173_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER173_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER173_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER173_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER173_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER173_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER173_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER173_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER173_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER173_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER173_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER173_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER173_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER173_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER173_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER173_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER173_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER174 - GICD_IROUTER174 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER174_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER174_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER174_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER174_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER174_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER174_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER174_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER174_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER174_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER174_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER174_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER174_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER174_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER174_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER174_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER174_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER174_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER174_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER174_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER174_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER174_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER174_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER174_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER174_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER174_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER174_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER174_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER174_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER174_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER174_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER174_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER174_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER174_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER174_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER174_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER175 - GICD_IROUTER175 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER175_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER175_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER175_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER175_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER175_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER175_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER175_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER175_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER175_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER175_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER175_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER175_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER175_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER175_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER175_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER175_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER175_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER175_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER175_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER175_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER175_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER175_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER175_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER175_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER175_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER175_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER175_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER175_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER175_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER175_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER175_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER175_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER175_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER175_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER175_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER176 - GICD_IROUTER176 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER176_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER176_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER176_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER176_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER176_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER176_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER176_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER176_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER176_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER176_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER176_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER176_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER176_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER176_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER176_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER176_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER176_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER176_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER176_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER176_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER176_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER176_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER176_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER176_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER176_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER176_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER176_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER176_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER176_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER176_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER176_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER176_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER176_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER176_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER176_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER177 - GICD_IROUTER177 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER177_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER177_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER177_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER177_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER177_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER177_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER177_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER177_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER177_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER177_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER177_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER177_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER177_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER177_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER177_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER177_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER177_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER177_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER177_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER177_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER177_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER177_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER177_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER177_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER177_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER177_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER177_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER177_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER177_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER177_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER177_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER177_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER177_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER177_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER177_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER178 - GICD_IROUTER178 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER178_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER178_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER178_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER178_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER178_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER178_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER178_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER178_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER178_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER178_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER178_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER178_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER178_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER178_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER178_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER178_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER178_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER178_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER178_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER178_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER178_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER178_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER178_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER178_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER178_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER178_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER178_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER178_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER178_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER178_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER178_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER178_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER178_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER178_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER178_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER179 - GICD_IROUTER179 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER179_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER179_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER179_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER179_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER179_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER179_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER179_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER179_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER179_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER179_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER179_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER179_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER179_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER179_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER179_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER179_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER179_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER179_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER179_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER179_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER179_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER179_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER179_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER179_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER179_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER179_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER179_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER179_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER179_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER179_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER179_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER179_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER179_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER179_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER179_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER180 - GICD_IROUTER180 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER180_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER180_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER180_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER180_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER180_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER180_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER180_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER180_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER180_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER180_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER180_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER180_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER180_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER180_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER180_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER180_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER180_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER180_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER180_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER180_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER180_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER180_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER180_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER180_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER180_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER180_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER180_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER180_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER180_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER180_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER180_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER180_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER180_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER180_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER180_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER181 - GICD_IROUTER181 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER181_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER181_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER181_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER181_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER181_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER181_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER181_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER181_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER181_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER181_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER181_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER181_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER181_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER181_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER181_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER181_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER181_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER181_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER181_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER181_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER181_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER181_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER181_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER181_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER181_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER181_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER181_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER181_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER181_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER181_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER181_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER181_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER181_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER181_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER181_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER182 - GICD_IROUTER182 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER182_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER182_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER182_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER182_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER182_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER182_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER182_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER182_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER182_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER182_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER182_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER182_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER182_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER182_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER182_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER182_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER182_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER182_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER182_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER182_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER182_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER182_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER182_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER182_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER182_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER182_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER182_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER182_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER182_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER182_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER182_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER182_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER182_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER182_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER182_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER183 - GICD_IROUTER183 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER183_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER183_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER183_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER183_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER183_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER183_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER183_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER183_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER183_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER183_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER183_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER183_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER183_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER183_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER183_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER183_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER183_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER183_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER183_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER183_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER183_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER183_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER183_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER183_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER183_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER183_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER183_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER183_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER183_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER183_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER183_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER183_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER183_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER183_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER183_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER184 - GICD_IROUTER184 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER184_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER184_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER184_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER184_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER184_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER184_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER184_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER184_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER184_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER184_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER184_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER184_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER184_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER184_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER184_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER184_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER184_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER184_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER184_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER184_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER184_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER184_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER184_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER184_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER184_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER184_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER184_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER184_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER184_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER184_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER184_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER184_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER184_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER184_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER184_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER185 - GICD_IROUTER185 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER185_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER185_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER185_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER185_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER185_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER185_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER185_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER185_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER185_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER185_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER185_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER185_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER185_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER185_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER185_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER185_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER185_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER185_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER185_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER185_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER185_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER185_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER185_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER185_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER185_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER185_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER185_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER185_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER185_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER185_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER185_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER185_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER185_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER185_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER185_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER186 - GICD_IROUTER186 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER186_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER186_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER186_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER186_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER186_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER186_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER186_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER186_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER186_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER186_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER186_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER186_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER186_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER186_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER186_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER186_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER186_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER186_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER186_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER186_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER186_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER186_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER186_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER186_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER186_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER186_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER186_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER186_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER186_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER186_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER186_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER186_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER186_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER186_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER186_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER187 - GICD_IROUTER187 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER187_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER187_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER187_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER187_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER187_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER187_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER187_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER187_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER187_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER187_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER187_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER187_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER187_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER187_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER187_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER187_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER187_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER187_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER187_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER187_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER187_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER187_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER187_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER187_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER187_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER187_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER187_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER187_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER187_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER187_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER187_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER187_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER187_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER187_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER187_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER188 - GICD_IROUTER188 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER188_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER188_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER188_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER188_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER188_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER188_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER188_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER188_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER188_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER188_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER188_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER188_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER188_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER188_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER188_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER188_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER188_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER188_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER188_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER188_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER188_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER188_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER188_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER188_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER188_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER188_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER188_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER188_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER188_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER188_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER188_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER188_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER188_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER188_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER188_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER189 - GICD_IROUTER189 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER189_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER189_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER189_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER189_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER189_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER189_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER189_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER189_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER189_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER189_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER189_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER189_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER189_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER189_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER189_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER189_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER189_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER189_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER189_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER189_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER189_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER189_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER189_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER189_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER189_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER189_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER189_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER189_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER189_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER189_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER189_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER189_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER189_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER189_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER189_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER190 - GICD_IROUTER190 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER190_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER190_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER190_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER190_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER190_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER190_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER190_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER190_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER190_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER190_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER190_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER190_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER190_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER190_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER190_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER190_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER190_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER190_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER190_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER190_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER190_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER190_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER190_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER190_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER190_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER190_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER190_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER190_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER190_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER190_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER190_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER190_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER190_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER190_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER190_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER191 - GICD_IROUTER191 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER191_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER191_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER191_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER191_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER191_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER191_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER191_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER191_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER191_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER191_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER191_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER191_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER191_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER191_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER191_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER191_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER191_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER191_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER191_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER191_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER191_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER191_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER191_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER191_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER191_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER191_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER191_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER191_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER191_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER191_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER191_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER191_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER191_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER191_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER191_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER192 - GICD_IROUTER192 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER192_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER192_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER192_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER192_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER192_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER192_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER192_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER192_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER192_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER192_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER192_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER192_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER192_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER192_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER192_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER192_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER192_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER192_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER192_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER192_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER192_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER192_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER192_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER192_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER192_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER192_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER192_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER192_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER192_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER192_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER192_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER192_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER192_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER192_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER192_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER193 - GICD_IROUTER193 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER193_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER193_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER193_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER193_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER193_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER193_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER193_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER193_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER193_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER193_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER193_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER193_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER193_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER193_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER193_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER193_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER193_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER193_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER193_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER193_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER193_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER193_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER193_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER193_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER193_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER193_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER193_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER193_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER193_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER193_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER193_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER193_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER193_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER193_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER193_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER194 - GICD_IROUTER194 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER194_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER194_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER194_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER194_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER194_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER194_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER194_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER194_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER194_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER194_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER194_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER194_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER194_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER194_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER194_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER194_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER194_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER194_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER194_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER194_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER194_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER194_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER194_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER194_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER194_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER194_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER194_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER194_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER194_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER194_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER194_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER194_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER194_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER194_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER194_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER195 - GICD_IROUTER195 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER195_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER195_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER195_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER195_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER195_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER195_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER195_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER195_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER195_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER195_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER195_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER195_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER195_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER195_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER195_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER195_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER195_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER195_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER195_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER195_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER195_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER195_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER195_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER195_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER195_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER195_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER195_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER195_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER195_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER195_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER195_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER195_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER195_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER195_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER195_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER196 - GICD_IROUTER196 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER196_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER196_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER196_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER196_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER196_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER196_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER196_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER196_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER196_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER196_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER196_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER196_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER196_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER196_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER196_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER196_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER196_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER196_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER196_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER196_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER196_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER196_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER196_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER196_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER196_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER196_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER196_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER196_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER196_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER196_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER196_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER196_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER196_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER196_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER196_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER197 - GICD_IROUTER197 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER197_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER197_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER197_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER197_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER197_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER197_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER197_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER197_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER197_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER197_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER197_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER197_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER197_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER197_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER197_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER197_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER197_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER197_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER197_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER197_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER197_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER197_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER197_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER197_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER197_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER197_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER197_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER197_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER197_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER197_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER197_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER197_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER197_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER197_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER197_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER198 - GICD_IROUTER198 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER198_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER198_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER198_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER198_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER198_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER198_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER198_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER198_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER198_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER198_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER198_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER198_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER198_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER198_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER198_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER198_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER198_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER198_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER198_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER198_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER198_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER198_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER198_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER198_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER198_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER198_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER198_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER198_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER198_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER198_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER198_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER198_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER198_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER198_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER198_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER199 - GICD_IROUTER199 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER199_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER199_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER199_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER199_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER199_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER199_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER199_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER199_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER199_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER199_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER199_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER199_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER199_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER199_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER199_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER199_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER199_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER199_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER199_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER199_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER199_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER199_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER199_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER199_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER199_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER199_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER199_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER199_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER199_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER199_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER199_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER199_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER199_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER199_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER199_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER200 - GICD_IROUTER200 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER200_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER200_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER200_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER200_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER200_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER200_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER200_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER200_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER200_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER200_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER200_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER200_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER200_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER200_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER200_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER200_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER200_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER200_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER200_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER200_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER200_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER200_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER200_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER200_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER200_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER200_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER200_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER200_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER200_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER200_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER200_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER200_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER200_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER200_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER200_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER201 - GICD_IROUTER201 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER201_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER201_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER201_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER201_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER201_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER201_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER201_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER201_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER201_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER201_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER201_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER201_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER201_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER201_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER201_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER201_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER201_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER201_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER201_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER201_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER201_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER201_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER201_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER201_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER201_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER201_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER201_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER201_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER201_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER201_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER201_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER201_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER201_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER201_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER201_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER202 - GICD_IROUTER202 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER202_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER202_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER202_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER202_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER202_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER202_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER202_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER202_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER202_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER202_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER202_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER202_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER202_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER202_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER202_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER202_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER202_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER202_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER202_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER202_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER202_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER202_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER202_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER202_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER202_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER202_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER202_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER202_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER202_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER202_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER202_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER202_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER202_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER202_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER202_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER203 - GICD_IROUTER203 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER203_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER203_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER203_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER203_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER203_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER203_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER203_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER203_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER203_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER203_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER203_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER203_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER203_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER203_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER203_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER203_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER203_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER203_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER203_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER203_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER203_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER203_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER203_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER203_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER203_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER203_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER203_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER203_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER203_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER203_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER203_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER203_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER203_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER203_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER203_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER204 - GICD_IROUTER204 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER204_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER204_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER204_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER204_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER204_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER204_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER204_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER204_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER204_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER204_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER204_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER204_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER204_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER204_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER204_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER204_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER204_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER204_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER204_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER204_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER204_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER204_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER204_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER204_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER204_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER204_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER204_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER204_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER204_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER204_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER204_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER204_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER204_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER204_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER204_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER205 - GICD_IROUTER205 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER205_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER205_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER205_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER205_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER205_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER205_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER205_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER205_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER205_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER205_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER205_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER205_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER205_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER205_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER205_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER205_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER205_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER205_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER205_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER205_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER205_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER205_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER205_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER205_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER205_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER205_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER205_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER205_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER205_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER205_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER205_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER205_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER205_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER205_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER205_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER206 - GICD_IROUTER206 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER206_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER206_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER206_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER206_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER206_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER206_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER206_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER206_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER206_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER206_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER206_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER206_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER206_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER206_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER206_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER206_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER206_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER206_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER206_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER206_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER206_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER206_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER206_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER206_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER206_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER206_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER206_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER206_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER206_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER206_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER206_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER206_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER206_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER206_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER206_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER207 - GICD_IROUTER207 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER207_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER207_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER207_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER207_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER207_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER207_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER207_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER207_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER207_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER207_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER207_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER207_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER207_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER207_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER207_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER207_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER207_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER207_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER207_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER207_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER207_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER207_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER207_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER207_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER207_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER207_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER207_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER207_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER207_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER207_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER207_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER207_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER207_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER207_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER207_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER208 - GICD_IROUTER208 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER208_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER208_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER208_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER208_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER208_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER208_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER208_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER208_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER208_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER208_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER208_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER208_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER208_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER208_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER208_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER208_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER208_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER208_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER208_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER208_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER208_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER208_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER208_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER208_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER208_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER208_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER208_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER208_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER208_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER208_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER208_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER208_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER208_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER208_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER208_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER209 - GICD_IROUTER209 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER209_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER209_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER209_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER209_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER209_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER209_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER209_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER209_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER209_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER209_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER209_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER209_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER209_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER209_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER209_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER209_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER209_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER209_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER209_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER209_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER209_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER209_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER209_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER209_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER209_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER209_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER209_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER209_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER209_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER209_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER209_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER209_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER209_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER209_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER209_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER210 - GICD_IROUTER210 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER210_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER210_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER210_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER210_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER210_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER210_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER210_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER210_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER210_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER210_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER210_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER210_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER210_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER210_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER210_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER210_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER210_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER210_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER210_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER210_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER210_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER210_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER210_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER210_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER210_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER210_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER210_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER210_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER210_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER210_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER210_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER210_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER210_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER210_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER210_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER211 - GICD_IROUTER211 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER211_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER211_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER211_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER211_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER211_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER211_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER211_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER211_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER211_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER211_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER211_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER211_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER211_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER211_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER211_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER211_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER211_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER211_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER211_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER211_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER211_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER211_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER211_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER211_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER211_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER211_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER211_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER211_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER211_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER211_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER211_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER211_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER211_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER211_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER211_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER212 - GICD_IROUTER212 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER212_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER212_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER212_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER212_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER212_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER212_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER212_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER212_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER212_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER212_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER212_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER212_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER212_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER212_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER212_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER212_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER212_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER212_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER212_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER212_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER212_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER212_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER212_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER212_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER212_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER212_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER212_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER212_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER212_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER212_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER212_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER212_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER212_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER212_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER212_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER213 - GICD_IROUTER213 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER213_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER213_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER213_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER213_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER213_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER213_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER213_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER213_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER213_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER213_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER213_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER213_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER213_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER213_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER213_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER213_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER213_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER213_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER213_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER213_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER213_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER213_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER213_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER213_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER213_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER213_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER213_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER213_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER213_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER213_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER213_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER213_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER213_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER213_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER213_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER214 - GICD_IROUTER214 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER214_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER214_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER214_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER214_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER214_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER214_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER214_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER214_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER214_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER214_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER214_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER214_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER214_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER214_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER214_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER214_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER214_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER214_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER214_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER214_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER214_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER214_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER214_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER214_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER214_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER214_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER214_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER214_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER214_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER214_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER214_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER214_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER214_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER214_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER214_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER215 - GICD_IROUTER215 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER215_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER215_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER215_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER215_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER215_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER215_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER215_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER215_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER215_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER215_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER215_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER215_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER215_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER215_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER215_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER215_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER215_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER215_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER215_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER215_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER215_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER215_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER215_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER215_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER215_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER215_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER215_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER215_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER215_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER215_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER215_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER215_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER215_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER215_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER215_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER216 - GICD_IROUTER216 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER216_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER216_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER216_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER216_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER216_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER216_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER216_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER216_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER216_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER216_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER216_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER216_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER216_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER216_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER216_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER216_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER216_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER216_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER216_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER216_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER216_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER216_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER216_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER216_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER216_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER216_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER216_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER216_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER216_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER216_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER216_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER216_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER216_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER216_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER216_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER217 - GICD_IROUTER217 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER217_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER217_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER217_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER217_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER217_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER217_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER217_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER217_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER217_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER217_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER217_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER217_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER217_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER217_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER217_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER217_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER217_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER217_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER217_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER217_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER217_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER217_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER217_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER217_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER217_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER217_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER217_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER217_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER217_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER217_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER217_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER217_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER217_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER217_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER217_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER218 - GICD_IROUTER218 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER218_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER218_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER218_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER218_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER218_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER218_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER218_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER218_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER218_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER218_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER218_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER218_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER218_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER218_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER218_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER218_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER218_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER218_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER218_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER218_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER218_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER218_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER218_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER218_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER218_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER218_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER218_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER218_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER218_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER218_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER218_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER218_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER218_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER218_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER218_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER219 - GICD_IROUTER219 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER219_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER219_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER219_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER219_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER219_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER219_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER219_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER219_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER219_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER219_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER219_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER219_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER219_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER219_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER219_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER219_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER219_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER219_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER219_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER219_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER219_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER219_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER219_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER219_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER219_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER219_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER219_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER219_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER219_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER219_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER219_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER219_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER219_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER219_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER219_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER220 - GICD_IROUTER220 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER220_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER220_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER220_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER220_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER220_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER220_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER220_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER220_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER220_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER220_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER220_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER220_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER220_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER220_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER220_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER220_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER220_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER220_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER220_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER220_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER220_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER220_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER220_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER220_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER220_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER220_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER220_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER220_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER220_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER220_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER220_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER220_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER220_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER220_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER220_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER221 - GICD_IROUTER221 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER221_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER221_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER221_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER221_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER221_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER221_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER221_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER221_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER221_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER221_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER221_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER221_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER221_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER221_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER221_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER221_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER221_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER221_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER221_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER221_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER221_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER221_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER221_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER221_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER221_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER221_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER221_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER221_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER221_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER221_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER221_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER221_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER221_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER221_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER221_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER222 - GICD_IROUTER222 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER222_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER222_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER222_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER222_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER222_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER222_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER222_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER222_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER222_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER222_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER222_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER222_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER222_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER222_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER222_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER222_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER222_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER222_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER222_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER222_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER222_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER222_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER222_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER222_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER222_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER222_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER222_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER222_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER222_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER222_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER222_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER222_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER222_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER222_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER222_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER223 - GICD_IROUTER223 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER223_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER223_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER223_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER223_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER223_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER223_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER223_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER223_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER223_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER223_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER223_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER223_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER223_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER223_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER223_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER223_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER223_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER223_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER223_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER223_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER223_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER223_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER223_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER223_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER223_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER223_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER223_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER223_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER223_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER223_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER223_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER223_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER223_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER223_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER223_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER224 - GICD_IROUTER224 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER224_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER224_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER224_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER224_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER224_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER224_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER224_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER224_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER224_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER224_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER224_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER224_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER224_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER224_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER224_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER224_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER224_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER224_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER224_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER224_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER224_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER224_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER224_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER224_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER224_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER224_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER224_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER224_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER224_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER224_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER224_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER224_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER224_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER224_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER224_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER225 - GICD_IROUTER225 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER225_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER225_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER225_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER225_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER225_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER225_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER225_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER225_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER225_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER225_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER225_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER225_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER225_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER225_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER225_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER225_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER225_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER225_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER225_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER225_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER225_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER225_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER225_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER225_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER225_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER225_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER225_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER225_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER225_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER225_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER225_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER225_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER225_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER225_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER225_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER226 - GICD_IROUTER226 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER226_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER226_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER226_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER226_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER226_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER226_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER226_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER226_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER226_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER226_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER226_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER226_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER226_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER226_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER226_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER226_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER226_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER226_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER226_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER226_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER226_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER226_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER226_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER226_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER226_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER226_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER226_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER226_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER226_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER226_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER226_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER226_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER226_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER226_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER226_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER227 - GICD_IROUTER227 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER227_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER227_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER227_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER227_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER227_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER227_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER227_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER227_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER227_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER227_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER227_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER227_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER227_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER227_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER227_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER227_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER227_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER227_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER227_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER227_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER227_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER227_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER227_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER227_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER227_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER227_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER227_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER227_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER227_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER227_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER227_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER227_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER227_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER227_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER227_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER228 - GICD_IROUTER228 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER228_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER228_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER228_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER228_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER228_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER228_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER228_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER228_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER228_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER228_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER228_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER228_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER228_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER228_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER228_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER228_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER228_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER228_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER228_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER228_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER228_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER228_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER228_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER228_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER228_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER228_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER228_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER228_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER228_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER228_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER228_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER228_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER228_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER228_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER228_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER229 - GICD_IROUTER229 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER229_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER229_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER229_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER229_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER229_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER229_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER229_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER229_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER229_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER229_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER229_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER229_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER229_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER229_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER229_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER229_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER229_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER229_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER229_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER229_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER229_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER229_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER229_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER229_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER229_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER229_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER229_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER229_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER229_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER229_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER229_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER229_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER229_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER229_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER229_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER230 - GICD_IROUTER230 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER230_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER230_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER230_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER230_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER230_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER230_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER230_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER230_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER230_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER230_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER230_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER230_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER230_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER230_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER230_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER230_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER230_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER230_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER230_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER230_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER230_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER230_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER230_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER230_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER230_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER230_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER230_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER230_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER230_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER230_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER230_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER230_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER230_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER230_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER230_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER231 - GICD_IROUTER231 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER231_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER231_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER231_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER231_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER231_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER231_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER231_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER231_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER231_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER231_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER231_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER231_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER231_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER231_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER231_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER231_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER231_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER231_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER231_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER231_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER231_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER231_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER231_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER231_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER231_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER231_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER231_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER231_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER231_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER231_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER231_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER231_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER231_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER231_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER231_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER232 - GICD_IROUTER232 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER232_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER232_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER232_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER232_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER232_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER232_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER232_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER232_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER232_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER232_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER232_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER232_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER232_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER232_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER232_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER232_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER232_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER232_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER232_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER232_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER232_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER232_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER232_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER232_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER232_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER232_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER232_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER232_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER232_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER232_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER232_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER232_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER232_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER232_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER232_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER233 - GICD_IROUTER233 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER233_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER233_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER233_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER233_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER233_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER233_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER233_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER233_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER233_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER233_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER233_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER233_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER233_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER233_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER233_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER233_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER233_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER233_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER233_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER233_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER233_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER233_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER233_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER233_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER233_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER233_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER233_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER233_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER233_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER233_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER233_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER233_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER233_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER233_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER233_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER234 - GICD_IROUTER234 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER234_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER234_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER234_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER234_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER234_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER234_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER234_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER234_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER234_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER234_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER234_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER234_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER234_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER234_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER234_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER234_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER234_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER234_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER234_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER234_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER234_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER234_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER234_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER234_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER234_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER234_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER234_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER234_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER234_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER234_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER234_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER234_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER234_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER234_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER234_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER235 - GICD_IROUTER235 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER235_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER235_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER235_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER235_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER235_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER235_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER235_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER235_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER235_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER235_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER235_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER235_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER235_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER235_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER235_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER235_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER235_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER235_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER235_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER235_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER235_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER235_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER235_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER235_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER235_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER235_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER235_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER235_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER235_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER235_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER235_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER235_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER235_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER235_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER235_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER236 - GICD_IROUTER236 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER236_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER236_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER236_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER236_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER236_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER236_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER236_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER236_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER236_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER236_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER236_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER236_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER236_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER236_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER236_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER236_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER236_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER236_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER236_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER236_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER236_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER236_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER236_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER236_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER236_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER236_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER236_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER236_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER236_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER236_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER236_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER236_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER236_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER236_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER236_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER237 - GICD_IROUTER237 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER237_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER237_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER237_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER237_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER237_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER237_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER237_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER237_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER237_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER237_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER237_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER237_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER237_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER237_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER237_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER237_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER237_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER237_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER237_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER237_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER237_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER237_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER237_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER237_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER237_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER237_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER237_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER237_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER237_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER237_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER237_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER237_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER237_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER237_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER237_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER238 - GICD_IROUTER238 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER238_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER238_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER238_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER238_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER238_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER238_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER238_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER238_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER238_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER238_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER238_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER238_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER238_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER238_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER238_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER238_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER238_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER238_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER238_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER238_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER238_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER238_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER238_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER238_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER238_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER238_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER238_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER238_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER238_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER238_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER238_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER238_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER238_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER238_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER238_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER239 - GICD_IROUTER239 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER239_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER239_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER239_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER239_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER239_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER239_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER239_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER239_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER239_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER239_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER239_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER239_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER239_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER239_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER239_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER239_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER239_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER239_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER239_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER239_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER239_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER239_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER239_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER239_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER239_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER239_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER239_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER239_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER239_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER239_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER239_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER239_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER239_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER239_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER239_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER240 - GICD_IROUTER240 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER240_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER240_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER240_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER240_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER240_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER240_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER240_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER240_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER240_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER240_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER240_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER240_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER240_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER240_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER240_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER240_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER240_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER240_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER240_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER240_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER240_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER240_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER240_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER240_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER240_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER240_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER240_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER240_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER240_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER240_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER240_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER240_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER240_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER240_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER240_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER241 - GICD_IROUTER241 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER241_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER241_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER241_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER241_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER241_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER241_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER241_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER241_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER241_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER241_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER241_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER241_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER241_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER241_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER241_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER241_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER241_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER241_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER241_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER241_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER241_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER241_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER241_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER241_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER241_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER241_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER241_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER241_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER241_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER241_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER241_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER241_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER241_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER241_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER241_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER242 - GICD_IROUTER242 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER242_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER242_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER242_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER242_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER242_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER242_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER242_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER242_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER242_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER242_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER242_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER242_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER242_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER242_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER242_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER242_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER242_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER242_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER242_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER242_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER242_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER242_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER242_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER242_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER242_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER242_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER242_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER242_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER242_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER242_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER242_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER242_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER242_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER242_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER242_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER243 - GICD_IROUTER243 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER243_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER243_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER243_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER243_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER243_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER243_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER243_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER243_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER243_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER243_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER243_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER243_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER243_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER243_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER243_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER243_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER243_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER243_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER243_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER243_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER243_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER243_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER243_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER243_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER243_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER243_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER243_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER243_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER243_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER243_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER243_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER243_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER243_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER243_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER243_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER244 - GICD_IROUTER244 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER244_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER244_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER244_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER244_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER244_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER244_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER244_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER244_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER244_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER244_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER244_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER244_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER244_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER244_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER244_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER244_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER244_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER244_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER244_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER244_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER244_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER244_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER244_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER244_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER244_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER244_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER244_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER244_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER244_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER244_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER244_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER244_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER244_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER244_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER244_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER245 - GICD_IROUTER245 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER245_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER245_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER245_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER245_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER245_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER245_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER245_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER245_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER245_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER245_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER245_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER245_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER245_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER245_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER245_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER245_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER245_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER245_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER245_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER245_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER245_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER245_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER245_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER245_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER245_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER245_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER245_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER245_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER245_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER245_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER245_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER245_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER245_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER245_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER245_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER246 - GICD_IROUTER246 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER246_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER246_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER246_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER246_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER246_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER246_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER246_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER246_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER246_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER246_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER246_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER246_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER246_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER246_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER246_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER246_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER246_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER246_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER246_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER246_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER246_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER246_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER246_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER246_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER246_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER246_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER246_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER246_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER246_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER246_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER246_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER246_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER246_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER246_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER246_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER247 - GICD_IROUTER247 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER247_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER247_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER247_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER247_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER247_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER247_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER247_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER247_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER247_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER247_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER247_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER247_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER247_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER247_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER247_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER247_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER247_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER247_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER247_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER247_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER247_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER247_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER247_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER247_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER247_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER247_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER247_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER247_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER247_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER247_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER247_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER247_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER247_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER247_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER247_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER248 - GICD_IROUTER248 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER248_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER248_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER248_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER248_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER248_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER248_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER248_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER248_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER248_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER248_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER248_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER248_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER248_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER248_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER248_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER248_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER248_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER248_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER248_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER248_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER248_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER248_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER248_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER248_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER248_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER248_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER248_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER248_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER248_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER248_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER248_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER248_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER248_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER248_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER248_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER249 - GICD_IROUTER249 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER249_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER249_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER249_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER249_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER249_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER249_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER249_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER249_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER249_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER249_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER249_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER249_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER249_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER249_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER249_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER249_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER249_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER249_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER249_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER249_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER249_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER249_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER249_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER249_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER249_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER249_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER249_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER249_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER249_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER249_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER249_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER249_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER249_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER249_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER249_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER250 - GICD_IROUTER250 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER250_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER250_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER250_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER250_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER250_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER250_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER250_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER250_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER250_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER250_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER250_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER250_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER250_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER250_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER250_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER250_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER250_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER250_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER250_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER250_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER250_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER250_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER250_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER250_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER250_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER250_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER250_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER250_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER250_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER250_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER250_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER250_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER250_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER250_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER250_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER251 - GICD_IROUTER251 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER251_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER251_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER251_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER251_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER251_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER251_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER251_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER251_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER251_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER251_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER251_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER251_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER251_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER251_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER251_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER251_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER251_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER251_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER251_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER251_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER251_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER251_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER251_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER251_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER251_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER251_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER251_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER251_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER251_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER251_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER251_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER251_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER251_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER251_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER251_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER252 - GICD_IROUTER252 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER252_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER252_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER252_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER252_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER252_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER252_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER252_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER252_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER252_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER252_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER252_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER252_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER252_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER252_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER252_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER252_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER252_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER252_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER252_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER252_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER252_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER252_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER252_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER252_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER252_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER252_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER252_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER252_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER252_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER252_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER252_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER252_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER252_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER252_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER252_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER253 - GICD_IROUTER253 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER253_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER253_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER253_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER253_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER253_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER253_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER253_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER253_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER253_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER253_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER253_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER253_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER253_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER253_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER253_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER253_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER253_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER253_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER253_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER253_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER253_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER253_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER253_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER253_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER253_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER253_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER253_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER253_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER253_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER253_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER253_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER253_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER253_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER253_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER253_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER254 - GICD_IROUTER254 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER254_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER254_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER254_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER254_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER254_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER254_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER254_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER254_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER254_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER254_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER254_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER254_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER254_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER254_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER254_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER254_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER254_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER254_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER254_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER254_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER254_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER254_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER254_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER254_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER254_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER254_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER254_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER254_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER254_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER254_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER254_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER254_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER254_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER254_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER254_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER255 - GICD_IROUTER255 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER255_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER255_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER255_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER255_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER255_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER255_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER255_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER255_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER255_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER255_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER255_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER255_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER255_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER255_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER255_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER255_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER255_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER255_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER255_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER255_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER255_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER255_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER255_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER255_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER255_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER255_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER255_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER255_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER255_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER255_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER255_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER255_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER255_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER255_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER255_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER256 - GICD_IROUTER256 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER256_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER256_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER256_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER256_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER256_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER256_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER256_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER256_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER256_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER256_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER256_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER256_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER256_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER256_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER256_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER256_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER256_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER256_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER256_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER256_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER256_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER256_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER256_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER256_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER256_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER256_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER256_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER256_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER256_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER256_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER256_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER256_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER256_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER256_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER256_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER257 - GICD_IROUTER257 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER257_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER257_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER257_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER257_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER257_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER257_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER257_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER257_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER257_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER257_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER257_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER257_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER257_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER257_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER257_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER257_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER257_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER257_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER257_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER257_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER257_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER257_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER257_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER257_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER257_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER257_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER257_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER257_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER257_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER257_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER257_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER257_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER257_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER257_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER257_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER258 - GICD_IROUTER258 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER258_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER258_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER258_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER258_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER258_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER258_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER258_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER258_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER258_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER258_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER258_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER258_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER258_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER258_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER258_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER258_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER258_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER258_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER258_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER258_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER258_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER258_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER258_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER258_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER258_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER258_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER258_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER258_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER258_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER258_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER258_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER258_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER258_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER258_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER258_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER259 - GICD_IROUTER259 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER259_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER259_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER259_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER259_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER259_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER259_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER259_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER259_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER259_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER259_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER259_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER259_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER259_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER259_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER259_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER259_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER259_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER259_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER259_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER259_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER259_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER259_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER259_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER259_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER259_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER259_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER259_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER259_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER259_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER259_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER259_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER259_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER259_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER259_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER259_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER260 - GICD_IROUTER260 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER260_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER260_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER260_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER260_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER260_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER260_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER260_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER260_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER260_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER260_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER260_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER260_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER260_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER260_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER260_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER260_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER260_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER260_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER260_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER260_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER260_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER260_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER260_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER260_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER260_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER260_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER260_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER260_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER260_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER260_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER260_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER260_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER260_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER260_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER260_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER261 - GICD_IROUTER261 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER261_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER261_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER261_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER261_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER261_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER261_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER261_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER261_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER261_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER261_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER261_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER261_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER261_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER261_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER261_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER261_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER261_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER261_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER261_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER261_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER261_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER261_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER261_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER261_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER261_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER261_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER261_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER261_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER261_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER261_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER261_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER261_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER261_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER261_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER261_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER262 - GICD_IROUTER262 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER262_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER262_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER262_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER262_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER262_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER262_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER262_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER262_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER262_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER262_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER262_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER262_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER262_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER262_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER262_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER262_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER262_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER262_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER262_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER262_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER262_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER262_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER262_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER262_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER262_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER262_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER262_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER262_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER262_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER262_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER262_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER262_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER262_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER262_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER262_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER263 - GICD_IROUTER263 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER263_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER263_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER263_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER263_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER263_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER263_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER263_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER263_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER263_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER263_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER263_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER263_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER263_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER263_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER263_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER263_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER263_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER263_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER263_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER263_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER263_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER263_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER263_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER263_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER263_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER263_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER263_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER263_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER263_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER263_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER263_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER263_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER263_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER263_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER263_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER264 - GICD_IROUTER264 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER264_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER264_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER264_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER264_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER264_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER264_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER264_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER264_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER264_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER264_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER264_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER264_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER264_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER264_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER264_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER264_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER264_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER264_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER264_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER264_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER264_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER264_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER264_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER264_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER264_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER264_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER264_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER264_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER264_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER264_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER264_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER264_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER264_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER264_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER264_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER265 - GICD_IROUTER265 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER265_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER265_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER265_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER265_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER265_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER265_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER265_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER265_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER265_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER265_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER265_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER265_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER265_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER265_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER265_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER265_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER265_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER265_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER265_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER265_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER265_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER265_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER265_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER265_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER265_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER265_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER265_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER265_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER265_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER265_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER265_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER265_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER265_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER265_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER265_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER266 - GICD_IROUTER266 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER266_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER266_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER266_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER266_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER266_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER266_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER266_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER266_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER266_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER266_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER266_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER266_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER266_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER266_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER266_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER266_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER266_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER266_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER266_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER266_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER266_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER266_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER266_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER266_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER266_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER266_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER266_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER266_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER266_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER266_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER266_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER266_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER266_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER266_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER266_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER267 - GICD_IROUTER267 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER267_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER267_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER267_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER267_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER267_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER267_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER267_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER267_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER267_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER267_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER267_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER267_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER267_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER267_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER267_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER267_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER267_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER267_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER267_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER267_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER267_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER267_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER267_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER267_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER267_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER267_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER267_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER267_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER267_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER267_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER267_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER267_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER267_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER267_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER267_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER268 - GICD_IROUTER268 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER268_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER268_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER268_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER268_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER268_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER268_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER268_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER268_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER268_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER268_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER268_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER268_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER268_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER268_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER268_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER268_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER268_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER268_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER268_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER268_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER268_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER268_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER268_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER268_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER268_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER268_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER268_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER268_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER268_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER268_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER268_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER268_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER268_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER268_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER268_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER269 - GICD_IROUTER269 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER269_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER269_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER269_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER269_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER269_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER269_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER269_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER269_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER269_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER269_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER269_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER269_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER269_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER269_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER269_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER269_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER269_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER269_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER269_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER269_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER269_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER269_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER269_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER269_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER269_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER269_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER269_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER269_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER269_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER269_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER269_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER269_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER269_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER269_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER269_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER270 - GICD_IROUTER270 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER270_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER270_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER270_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER270_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER270_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER270_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER270_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER270_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER270_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER270_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER270_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER270_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER270_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER270_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER270_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER270_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER270_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER270_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER270_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER270_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER270_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER270_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER270_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER270_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER270_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER270_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER270_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER270_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER270_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER270_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER270_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER270_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER270_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER270_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER270_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER271 - GICD_IROUTER271 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER271_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER271_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER271_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER271_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER271_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER271_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER271_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER271_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER271_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER271_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER271_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER271_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER271_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER271_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER271_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER271_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER271_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER271_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER271_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER271_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER271_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER271_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER271_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER271_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER271_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER271_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER271_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER271_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER271_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER271_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER271_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER271_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER271_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER271_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER271_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER272 - GICD_IROUTER272 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER272_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER272_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER272_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER272_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER272_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER272_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER272_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER272_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER272_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER272_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER272_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER272_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER272_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER272_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER272_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER272_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER272_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER272_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER272_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER272_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER272_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER272_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER272_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER272_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER272_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER272_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER272_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER272_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER272_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER272_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER272_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER272_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER272_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER272_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER272_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER273 - GICD_IROUTER273 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER273_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER273_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER273_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER273_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER273_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER273_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER273_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER273_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER273_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER273_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER273_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER273_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER273_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER273_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER273_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER273_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER273_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER273_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER273_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER273_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER273_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER273_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER273_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER273_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER273_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER273_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER273_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER273_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER273_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER273_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER273_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER273_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER273_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER273_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER273_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER274 - GICD_IROUTER274 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER274_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER274_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER274_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER274_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER274_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER274_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER274_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER274_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER274_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER274_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER274_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER274_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER274_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER274_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER274_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER274_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER274_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER274_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER274_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER274_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER274_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER274_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER274_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER274_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER274_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER274_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER274_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER274_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER274_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER274_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER274_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER274_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER274_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER274_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER274_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER275 - GICD_IROUTER275 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER275_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER275_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER275_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER275_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER275_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER275_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER275_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER275_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER275_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER275_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER275_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER275_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER275_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER275_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER275_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER275_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER275_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER275_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER275_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER275_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER275_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER275_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER275_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER275_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER275_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER275_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER275_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER275_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER275_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER275_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER275_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER275_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER275_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER275_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER275_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER276 - GICD_IROUTER276 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER276_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER276_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER276_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER276_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER276_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER276_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER276_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER276_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER276_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER276_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER276_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER276_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER276_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER276_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER276_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER276_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER276_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER276_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER276_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER276_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER276_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER276_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER276_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER276_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER276_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER276_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER276_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER276_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER276_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER276_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER276_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER276_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER276_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER276_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER276_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER277 - GICD_IROUTER277 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER277_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER277_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER277_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER277_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER277_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER277_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER277_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER277_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER277_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER277_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER277_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER277_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER277_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER277_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER277_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER277_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER277_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER277_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER277_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER277_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER277_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER277_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER277_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER277_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER277_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER277_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER277_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER277_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER277_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER277_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER277_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER277_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER277_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER277_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER277_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER278 - GICD_IROUTER278 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER278_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER278_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER278_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER278_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER278_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER278_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER278_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER278_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER278_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER278_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER278_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER278_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER278_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER278_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER278_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER278_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER278_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER278_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER278_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER278_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER278_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER278_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER278_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER278_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER278_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER278_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER278_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER278_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER278_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER278_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER278_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER278_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER278_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER278_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER278_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER279 - GICD_IROUTER279 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER279_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER279_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER279_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER279_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER279_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER279_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER279_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER279_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER279_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER279_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER279_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER279_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER279_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER279_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER279_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER279_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER279_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER279_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER279_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER279_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER279_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER279_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER279_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER279_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER279_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER279_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER279_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER279_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER279_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER279_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER279_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER279_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER279_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER279_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER279_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER280 - GICD_IROUTER280 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER280_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER280_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER280_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER280_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER280_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER280_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER280_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER280_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER280_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER280_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER280_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER280_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER280_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER280_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER280_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER280_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER280_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER280_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER280_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER280_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER280_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER280_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER280_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER280_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER280_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER280_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER280_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER280_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER280_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER280_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER280_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER280_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER280_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER280_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER280_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER281 - GICD_IROUTER281 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER281_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER281_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER281_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER281_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER281_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER281_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER281_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER281_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER281_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER281_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER281_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER281_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER281_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER281_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER281_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER281_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER281_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER281_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER281_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER281_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER281_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER281_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER281_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER281_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER281_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER281_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER281_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER281_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER281_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER281_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER281_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER281_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER281_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER281_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER281_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER282 - GICD_IROUTER282 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER282_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER282_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER282_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER282_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER282_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER282_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER282_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER282_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER282_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER282_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER282_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER282_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER282_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER282_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER282_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER282_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER282_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER282_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER282_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER282_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER282_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER282_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER282_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER282_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER282_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER282_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER282_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER282_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER282_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER282_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER282_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER282_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER282_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER282_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER282_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER283 - GICD_IROUTER283 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER283_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER283_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER283_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER283_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER283_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER283_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER283_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER283_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER283_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER283_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER283_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER283_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER283_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER283_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER283_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER283_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER283_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER283_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER283_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER283_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER283_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER283_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER283_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER283_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER283_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER283_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER283_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER283_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER283_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER283_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER283_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER283_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER283_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER283_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER283_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER284 - GICD_IROUTER284 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER284_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER284_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER284_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER284_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER284_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER284_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER284_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER284_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER284_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER284_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER284_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER284_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER284_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER284_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER284_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER284_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER284_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER284_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER284_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER284_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER284_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER284_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER284_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER284_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER284_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER284_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER284_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER284_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER284_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER284_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER284_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER284_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER284_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER284_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER284_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER285 - GICD_IROUTER285 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER285_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER285_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER285_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER285_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER285_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER285_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER285_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER285_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER285_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER285_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER285_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER285_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER285_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER285_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER285_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER285_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER285_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER285_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER285_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER285_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER285_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER285_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER285_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER285_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER285_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER285_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER285_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER285_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER285_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER285_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER285_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER285_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER285_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER285_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER285_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER286 - GICD_IROUTER286 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER286_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER286_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER286_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER286_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER286_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER286_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER286_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER286_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER286_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER286_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER286_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER286_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER286_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER286_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER286_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER286_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER286_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER286_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER286_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER286_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER286_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER286_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER286_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER286_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER286_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER286_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER286_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER286_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER286_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER286_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER286_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER286_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER286_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER286_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER286_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER287 - GICD_IROUTER287 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER287_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER287_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER287_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER287_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER287_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER287_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER287_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER287_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER287_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER287_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER287_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER287_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER287_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER287_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER287_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER287_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER287_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER287_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER287_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER287_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER287_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER287_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER287_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER287_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER287_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER287_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER287_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER287_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER287_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER287_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER287_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER287_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER287_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER287_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER287_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER288 - GICD_IROUTER288 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER288_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER288_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER288_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER288_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER288_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER288_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER288_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER288_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER288_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER288_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER288_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER288_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER288_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER288_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER288_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER288_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER288_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER288_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER288_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER288_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER288_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER288_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER288_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER288_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER288_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER288_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER288_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER288_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER288_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER288_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER288_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER288_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER288_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER288_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER288_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER289 - GICD_IROUTER289 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER289_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER289_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER289_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER289_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER289_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER289_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER289_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER289_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER289_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER289_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER289_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER289_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER289_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER289_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER289_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER289_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER289_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER289_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER289_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER289_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER289_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER289_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER289_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER289_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER289_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER289_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER289_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER289_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER289_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER289_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER289_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER289_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER289_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER289_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER289_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER290 - GICD_IROUTER290 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER290_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER290_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER290_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER290_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER290_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER290_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER290_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER290_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER290_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER290_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER290_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER290_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER290_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER290_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER290_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER290_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER290_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER290_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER290_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER290_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER290_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER290_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER290_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER290_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER290_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER290_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER290_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER290_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER290_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER290_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER290_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER290_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER290_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER290_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER290_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER291 - GICD_IROUTER291 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER291_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER291_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER291_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER291_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER291_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER291_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER291_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER291_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER291_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER291_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER291_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER291_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER291_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER291_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER291_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER291_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER291_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER291_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER291_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER291_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER291_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER291_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER291_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER291_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER291_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER291_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER291_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER291_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER291_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER291_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER291_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER291_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER291_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER291_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER291_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER292 - GICD_IROUTER292 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER292_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER292_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER292_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER292_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER292_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER292_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER292_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER292_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER292_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER292_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER292_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER292_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER292_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER292_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER292_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER292_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER292_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER292_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER292_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER292_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER292_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER292_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER292_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER292_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER292_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER292_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER292_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER292_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER292_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER292_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER292_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER292_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER292_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER292_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER292_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER293 - GICD_IROUTER293 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER293_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER293_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER293_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER293_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER293_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER293_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER293_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER293_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER293_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER293_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER293_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER293_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER293_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER293_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER293_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER293_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER293_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER293_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER293_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER293_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER293_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER293_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER293_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER293_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER293_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER293_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER293_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER293_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER293_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER293_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER293_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER293_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER293_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER293_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER293_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER294 - GICD_IROUTER294 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER294_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER294_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER294_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER294_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER294_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER294_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER294_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER294_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER294_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER294_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER294_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER294_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER294_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER294_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER294_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER294_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER294_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER294_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER294_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER294_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER294_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER294_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER294_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER294_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER294_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER294_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER294_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER294_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER294_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER294_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER294_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER294_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER294_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER294_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER294_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER295 - GICD_IROUTER295 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER295_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER295_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER295_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER295_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER295_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER295_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER295_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER295_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER295_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER295_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER295_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER295_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER295_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER295_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER295_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER295_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER295_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER295_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER295_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER295_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER295_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER295_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER295_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER295_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER295_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER295_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER295_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER295_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER295_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER295_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER295_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER295_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER295_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER295_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER295_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER296 - GICD_IROUTER296 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER296_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER296_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER296_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER296_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER296_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER296_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER296_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER296_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER296_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER296_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER296_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER296_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER296_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER296_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER296_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER296_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER296_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER296_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER296_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER296_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER296_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER296_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER296_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER296_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER296_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER296_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER296_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER296_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER296_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER296_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER296_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER296_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER296_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER296_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER296_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER297 - GICD_IROUTER297 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER297_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER297_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER297_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER297_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER297_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER297_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER297_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER297_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER297_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER297_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER297_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER297_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER297_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER297_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER297_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER297_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER297_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER297_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER297_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER297_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER297_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER297_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER297_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER297_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER297_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER297_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER297_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER297_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER297_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER297_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER297_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER297_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER297_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER297_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER297_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER298 - GICD_IROUTER298 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER298_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER298_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER298_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER298_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER298_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER298_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER298_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER298_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER298_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER298_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER298_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER298_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER298_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER298_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER298_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER298_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER298_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER298_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER298_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER298_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER298_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER298_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER298_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER298_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER298_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER298_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER298_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER298_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER298_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER298_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER298_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER298_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER298_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER298_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER298_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER299 - GICD_IROUTER299 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER299_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER299_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER299_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER299_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER299_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER299_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER299_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER299_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER299_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER299_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER299_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER299_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER299_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER299_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER299_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER299_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER299_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER299_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER299_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER299_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER299_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER299_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER299_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER299_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER299_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER299_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER299_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER299_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER299_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER299_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER299_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER299_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER299_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER299_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER299_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER300 - GICD_IROUTER300 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER300_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER300_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER300_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER300_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER300_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER300_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER300_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER300_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER300_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER300_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER300_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER300_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER300_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER300_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER300_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER300_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER300_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER300_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER300_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER300_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER300_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER300_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER300_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER300_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER300_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER300_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER300_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER300_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER300_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER300_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER300_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER300_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER300_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER300_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER300_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER301 - GICD_IROUTER301 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER301_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER301_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER301_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER301_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER301_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER301_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER301_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER301_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER301_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER301_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER301_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER301_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER301_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER301_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER301_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER301_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER301_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER301_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER301_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER301_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER301_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER301_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER301_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER301_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER301_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER301_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER301_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER301_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER301_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER301_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER301_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER301_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER301_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER301_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER301_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER302 - GICD_IROUTER302 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER302_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER302_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER302_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER302_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER302_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER302_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER302_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER302_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER302_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER302_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER302_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER302_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER302_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER302_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER302_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER302_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER302_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER302_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER302_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER302_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER302_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER302_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER302_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER302_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER302_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER302_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER302_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER302_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER302_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER302_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER302_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER302_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER302_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER302_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER302_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER303 - GICD_IROUTER303 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER303_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER303_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER303_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER303_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER303_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER303_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER303_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER303_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER303_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER303_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER303_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER303_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER303_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER303_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER303_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER303_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER303_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER303_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER303_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER303_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER303_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER303_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER303_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER303_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER303_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER303_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER303_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER303_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER303_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER303_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER303_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER303_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER303_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER303_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER303_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER304 - GICD_IROUTER304 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER304_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER304_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER304_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER304_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER304_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER304_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER304_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER304_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER304_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER304_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER304_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER304_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER304_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER304_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER304_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER304_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER304_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER304_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER304_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER304_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER304_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER304_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER304_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER304_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER304_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER304_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER304_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER304_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER304_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER304_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER304_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER304_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER304_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER304_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER304_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER305 - GICD_IROUTER305 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER305_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER305_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER305_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER305_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER305_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER305_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER305_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER305_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER305_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER305_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER305_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER305_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER305_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER305_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER305_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER305_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER305_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER305_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER305_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER305_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER305_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER305_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER305_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER305_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER305_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER305_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER305_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER305_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER305_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER305_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER305_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER305_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER305_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER305_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER305_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER306 - GICD_IROUTER306 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER306_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER306_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER306_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER306_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER306_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER306_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER306_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER306_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER306_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER306_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER306_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER306_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER306_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER306_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER306_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER306_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER306_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER306_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER306_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER306_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER306_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER306_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER306_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER306_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER306_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER306_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER306_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER306_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER306_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER306_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER306_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER306_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER306_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER306_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER306_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER307 - GICD_IROUTER307 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER307_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER307_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER307_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER307_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER307_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER307_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER307_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER307_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER307_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER307_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER307_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER307_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER307_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER307_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER307_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER307_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER307_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER307_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER307_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER307_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER307_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER307_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER307_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER307_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER307_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER307_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER307_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER307_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER307_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER307_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER307_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER307_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER307_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER307_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER307_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER308 - GICD_IROUTER308 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER308_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER308_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER308_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER308_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER308_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER308_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER308_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER308_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER308_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER308_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER308_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER308_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER308_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER308_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER308_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER308_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER308_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER308_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER308_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER308_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER308_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER308_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER308_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER308_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER308_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER308_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER308_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER308_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER308_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER308_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER308_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER308_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER308_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER308_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER308_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER309 - GICD_IROUTER309 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER309_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER309_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER309_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER309_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER309_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER309_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER309_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER309_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER309_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER309_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER309_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER309_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER309_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER309_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER309_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER309_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER309_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER309_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER309_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER309_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER309_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER309_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER309_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER309_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER309_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER309_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER309_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER309_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER309_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER309_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER309_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER309_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER309_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER309_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER309_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER310 - GICD_IROUTER310 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER310_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER310_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER310_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER310_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER310_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER310_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER310_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER310_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER310_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER310_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER310_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER310_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER310_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER310_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER310_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER310_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER310_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER310_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER310_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER310_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER310_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER310_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER310_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER310_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER310_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER310_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER310_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER310_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER310_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER310_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER310_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER310_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER310_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER310_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER310_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER311 - GICD_IROUTER311 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER311_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER311_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER311_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER311_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER311_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER311_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER311_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER311_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER311_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER311_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER311_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER311_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER311_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER311_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER311_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER311_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER311_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER311_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER311_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER311_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER311_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER311_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER311_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER311_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER311_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER311_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER311_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER311_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER311_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER311_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER311_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER311_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER311_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER311_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER311_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER312 - GICD_IROUTER312 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER312_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER312_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER312_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER312_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER312_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER312_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER312_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER312_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER312_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER312_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER312_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER312_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER312_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER312_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER312_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER312_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER312_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER312_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER312_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER312_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER312_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER312_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER312_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER312_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER312_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER312_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER312_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER312_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER312_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER312_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER312_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER312_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER312_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER312_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER312_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER313 - GICD_IROUTER313 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER313_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER313_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER313_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER313_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER313_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER313_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER313_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER313_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER313_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER313_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER313_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER313_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER313_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER313_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER313_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER313_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER313_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER313_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER313_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER313_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER313_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER313_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER313_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER313_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER313_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER313_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER313_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER313_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER313_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER313_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER313_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER313_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER313_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER313_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER313_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER314 - GICD_IROUTER314 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER314_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER314_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER314_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER314_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER314_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER314_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER314_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER314_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER314_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER314_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER314_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER314_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER314_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER314_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER314_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER314_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER314_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER314_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER314_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER314_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER314_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER314_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER314_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER314_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER314_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER314_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER314_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER314_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER314_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER314_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER314_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER314_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER314_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER314_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER314_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER315 - GICD_IROUTER315 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER315_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER315_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER315_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER315_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER315_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER315_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER315_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER315_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER315_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER315_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER315_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER315_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER315_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER315_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER315_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER315_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER315_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER315_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER315_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER315_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER315_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER315_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER315_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER315_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER315_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER315_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER315_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER315_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER315_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER315_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER315_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER315_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER315_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER315_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER315_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER316 - GICD_IROUTER316 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER316_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER316_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER316_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER316_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER316_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER316_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER316_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER316_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER316_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER316_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER316_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER316_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER316_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER316_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER316_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER316_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER316_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER316_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER316_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER316_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER316_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER316_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER316_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER316_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER316_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER316_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER316_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER316_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER316_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER316_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER316_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER316_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER316_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER316_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER316_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER317 - GICD_IROUTER317 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER317_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER317_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER317_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER317_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER317_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER317_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER317_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER317_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER317_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER317_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER317_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER317_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER317_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER317_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER317_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER317_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER317_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER317_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER317_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER317_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER317_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER317_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER317_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER317_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER317_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER317_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER317_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER317_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER317_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER317_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER317_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER317_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER317_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER317_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER317_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER318 - GICD_IROUTER318 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER318_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER318_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER318_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER318_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER318_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER318_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER318_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER318_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER318_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER318_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER318_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER318_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER318_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER318_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER318_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER318_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER318_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER318_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER318_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER318_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER318_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER318_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER318_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER318_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER318_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER318_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER318_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER318_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER318_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER318_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER318_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER318_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER318_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER318_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER318_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER319 - GICD_IROUTER319 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER319_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER319_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER319_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER319_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER319_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER319_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER319_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER319_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER319_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER319_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER319_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER319_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER319_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER319_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER319_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER319_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER319_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER319_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER319_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER319_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER319_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER319_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER319_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER319_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER319_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER319_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER319_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER319_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER319_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER319_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER319_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER319_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER319_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER319_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER319_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER320 - GICD_IROUTER320 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER320_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER320_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER320_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER320_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER320_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER320_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER320_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER320_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER320_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER320_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER320_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER320_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER320_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER320_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER320_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER320_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER320_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER320_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER320_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER320_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER320_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER320_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER320_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER320_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER320_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER320_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER320_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER320_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER320_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER320_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER320_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER320_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER320_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER320_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER320_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER321 - GICD_IROUTER321 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER321_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER321_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER321_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER321_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER321_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER321_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER321_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER321_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER321_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER321_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER321_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER321_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER321_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER321_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER321_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER321_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER321_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER321_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER321_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER321_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER321_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER321_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER321_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER321_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER321_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER321_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER321_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER321_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER321_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER321_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER321_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER321_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER321_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER321_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER321_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER322 - GICD_IROUTER322 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER322_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER322_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER322_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER322_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER322_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER322_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER322_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER322_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER322_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER322_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER322_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER322_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER322_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER322_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER322_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER322_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER322_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER322_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER322_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER322_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER322_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER322_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER322_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER322_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER322_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER322_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER322_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER322_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER322_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER322_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER322_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER322_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER322_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER322_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER322_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER323 - GICD_IROUTER323 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER323_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER323_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER323_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER323_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER323_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER323_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER323_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER323_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER323_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER323_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER323_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER323_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER323_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER323_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER323_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER323_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER323_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER323_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER323_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER323_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER323_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER323_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER323_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER323_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER323_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER323_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER323_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER323_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER323_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER323_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER323_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER323_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER323_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER323_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER323_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER324 - GICD_IROUTER324 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER324_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER324_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER324_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER324_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER324_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER324_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER324_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER324_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER324_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER324_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER324_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER324_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER324_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER324_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER324_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER324_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER324_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER324_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER324_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER324_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER324_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER324_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER324_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER324_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER324_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER324_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER324_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER324_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER324_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER324_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER324_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER324_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER324_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER324_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER324_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER325 - GICD_IROUTER325 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER325_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER325_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER325_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER325_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER325_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER325_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER325_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER325_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER325_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER325_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER325_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER325_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER325_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER325_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER325_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER325_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER325_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER325_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER325_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER325_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER325_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER325_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER325_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER325_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER325_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER325_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER325_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER325_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER325_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER325_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER325_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER325_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER325_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER325_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER325_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER326 - GICD_IROUTER326 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER326_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER326_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER326_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER326_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER326_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER326_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER326_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER326_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER326_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER326_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER326_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER326_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER326_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER326_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER326_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER326_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER326_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER326_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER326_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER326_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER326_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER326_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER326_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER326_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER326_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER326_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER326_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER326_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER326_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER326_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER326_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER326_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER326_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER326_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER326_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER327 - GICD_IROUTER327 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER327_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER327_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER327_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER327_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER327_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER327_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER327_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER327_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER327_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER327_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER327_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER327_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER327_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER327_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER327_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER327_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER327_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER327_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER327_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER327_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER327_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER327_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER327_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER327_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER327_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER327_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER327_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER327_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER327_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER327_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER327_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER327_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER327_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER327_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER327_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER328 - GICD_IROUTER328 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER328_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER328_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER328_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER328_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER328_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER328_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER328_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER328_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER328_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER328_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER328_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER328_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER328_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER328_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER328_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER328_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER328_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER328_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER328_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER328_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER328_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER328_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER328_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER328_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER328_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER328_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER328_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER328_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER328_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER328_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER328_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER328_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER328_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER328_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER328_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER329 - GICD_IROUTER329 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER329_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER329_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER329_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER329_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER329_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER329_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER329_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER329_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER329_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER329_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER329_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER329_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER329_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER329_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER329_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER329_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER329_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER329_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER329_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER329_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER329_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER329_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER329_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER329_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER329_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER329_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER329_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER329_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER329_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER329_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER329_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER329_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER329_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER329_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER329_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER330 - GICD_IROUTER330 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER330_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER330_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER330_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER330_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER330_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER330_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER330_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER330_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER330_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER330_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER330_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER330_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER330_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER330_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER330_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER330_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER330_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER330_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER330_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER330_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER330_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER330_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER330_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER330_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER330_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER330_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER330_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER330_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER330_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER330_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER330_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER330_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER330_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER330_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER330_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER331 - GICD_IROUTER331 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER331_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER331_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER331_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER331_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER331_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER331_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER331_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER331_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER331_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER331_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER331_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER331_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER331_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER331_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER331_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER331_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER331_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER331_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER331_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER331_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER331_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER331_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER331_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER331_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER331_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER331_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER331_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER331_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER331_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER331_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER331_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER331_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER331_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER331_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER331_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER332 - GICD_IROUTER332 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER332_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER332_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER332_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER332_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER332_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER332_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER332_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER332_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER332_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER332_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER332_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER332_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER332_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER332_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER332_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER332_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER332_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER332_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER332_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER332_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER332_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER332_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER332_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER332_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER332_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER332_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER332_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER332_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER332_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER332_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER332_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER332_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER332_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER332_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER332_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER333 - GICD_IROUTER333 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER333_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER333_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER333_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER333_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER333_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER333_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER333_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER333_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER333_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER333_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER333_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER333_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER333_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER333_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER333_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER333_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER333_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER333_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER333_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER333_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER333_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER333_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER333_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER333_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER333_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER333_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER333_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER333_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER333_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER333_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER333_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER333_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER333_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER333_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER333_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER334 - GICD_IROUTER334 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER334_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER334_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER334_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER334_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER334_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER334_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER334_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER334_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER334_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER334_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER334_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER334_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER334_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER334_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER334_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER334_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER334_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER334_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER334_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER334_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER334_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER334_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER334_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER334_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER334_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER334_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER334_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER334_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER334_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER334_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER334_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER334_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER334_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER334_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER334_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER335 - GICD_IROUTER335 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER335_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER335_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER335_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER335_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER335_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER335_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER335_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER335_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER335_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER335_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER335_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER335_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER335_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER335_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER335_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER335_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER335_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER335_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER335_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER335_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER335_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER335_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER335_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER335_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER335_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER335_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER335_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER335_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER335_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER335_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER335_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER335_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER335_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER335_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER335_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER336 - GICD_IROUTER336 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER336_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER336_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER336_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER336_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER336_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER336_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER336_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER336_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER336_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER336_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER336_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER336_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER336_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER336_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER336_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER336_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER336_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER336_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER336_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER336_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER336_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER336_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER336_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER336_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER336_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER336_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER336_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER336_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER336_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER336_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER336_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER336_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER336_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER336_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER336_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER337 - GICD_IROUTER337 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER337_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER337_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER337_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER337_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER337_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER337_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER337_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER337_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER337_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER337_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER337_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER337_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER337_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER337_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER337_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER337_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER337_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER337_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER337_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER337_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER337_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER337_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER337_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER337_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER337_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER337_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER337_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER337_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER337_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER337_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER337_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER337_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER337_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER337_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER337_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER338 - GICD_IROUTER338 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER338_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER338_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER338_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER338_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER338_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER338_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER338_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER338_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER338_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER338_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER338_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER338_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER338_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER338_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER338_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER338_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER338_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER338_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER338_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER338_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER338_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER338_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER338_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER338_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER338_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER338_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER338_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER338_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER338_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER338_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER338_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER338_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER338_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER338_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER338_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER339 - GICD_IROUTER339 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER339_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER339_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER339_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER339_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER339_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER339_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER339_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER339_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER339_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER339_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER339_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER339_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER339_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER339_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER339_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER339_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER339_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER339_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER339_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER339_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER339_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER339_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER339_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER339_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER339_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER339_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER339_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER339_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER339_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER339_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER339_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER339_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER339_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER339_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER339_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER340 - GICD_IROUTER340 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER340_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER340_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER340_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER340_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER340_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER340_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER340_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER340_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER340_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER340_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER340_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER340_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER340_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER340_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER340_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER340_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER340_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER340_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER340_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER340_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER340_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER340_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER340_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER340_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER340_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER340_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER340_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER340_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER340_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER340_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER340_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER340_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER340_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER340_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER340_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER341 - GICD_IROUTER341 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER341_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER341_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER341_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER341_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER341_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER341_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER341_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER341_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER341_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER341_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER341_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER341_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER341_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER341_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER341_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER341_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER341_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER341_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER341_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER341_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER341_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER341_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER341_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER341_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER341_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER341_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER341_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER341_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER341_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER341_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER341_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER341_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER341_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER341_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER341_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER342 - GICD_IROUTER342 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER342_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER342_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER342_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER342_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER342_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER342_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER342_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER342_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER342_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER342_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER342_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER342_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER342_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER342_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER342_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER342_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER342_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER342_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER342_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER342_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER342_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER342_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER342_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER342_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER342_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER342_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER342_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER342_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER342_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER342_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER342_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER342_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER342_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER342_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER342_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER343 - GICD_IROUTER343 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER343_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER343_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER343_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER343_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER343_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER343_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER343_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER343_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER343_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER343_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER343_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER343_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER343_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER343_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER343_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER343_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER343_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER343_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER343_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER343_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER343_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER343_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER343_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER343_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER343_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER343_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER343_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER343_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER343_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER343_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER343_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER343_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER343_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER343_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER343_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER344 - GICD_IROUTER344 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER344_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER344_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER344_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER344_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER344_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER344_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER344_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER344_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER344_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER344_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER344_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER344_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER344_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER344_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER344_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER344_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER344_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER344_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER344_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER344_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER344_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER344_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER344_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER344_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER344_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER344_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER344_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER344_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER344_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER344_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER344_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER344_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER344_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER344_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER344_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER345 - GICD_IROUTER345 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER345_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER345_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER345_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER345_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER345_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER345_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER345_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER345_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER345_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER345_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER345_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER345_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER345_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER345_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER345_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER345_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER345_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER345_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER345_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER345_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER345_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER345_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER345_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER345_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER345_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER345_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER345_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER345_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER345_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER345_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER345_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER345_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER345_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER345_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER345_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER346 - GICD_IROUTER346 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER346_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER346_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER346_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER346_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER346_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER346_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER346_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER346_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER346_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER346_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER346_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER346_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER346_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER346_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER346_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER346_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER346_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER346_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER346_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER346_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER346_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER346_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER346_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER346_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER346_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER346_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER346_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER346_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER346_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER346_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER346_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER346_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER346_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER346_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER346_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER347 - GICD_IROUTER347 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER347_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER347_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER347_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER347_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER347_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER347_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER347_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER347_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER347_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER347_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER347_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER347_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER347_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER347_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER347_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER347_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER347_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER347_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER347_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER347_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER347_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER347_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER347_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER347_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER347_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER347_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER347_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER347_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER347_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER347_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER347_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER347_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER347_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER347_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER347_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER348 - GICD_IROUTER348 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER348_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER348_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER348_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER348_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER348_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER348_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER348_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER348_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER348_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER348_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER348_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER348_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER348_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER348_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER348_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER348_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER348_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER348_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER348_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER348_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER348_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER348_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER348_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER348_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER348_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER348_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER348_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER348_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER348_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER348_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER348_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER348_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER348_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER348_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER348_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER349 - GICD_IROUTER349 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER349_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER349_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER349_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER349_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER349_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER349_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER349_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER349_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER349_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER349_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER349_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER349_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER349_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER349_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER349_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER349_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER349_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER349_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER349_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER349_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER349_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER349_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER349_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER349_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER349_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER349_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER349_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER349_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER349_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER349_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER349_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER349_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER349_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER349_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER349_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER350 - GICD_IROUTER350 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER350_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER350_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER350_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER350_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER350_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER350_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER350_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER350_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER350_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER350_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER350_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER350_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER350_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER350_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER350_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER350_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER350_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER350_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER350_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER350_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER350_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER350_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER350_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER350_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER350_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER350_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER350_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER350_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER350_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER350_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER350_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER350_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER350_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER350_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER350_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER351 - GICD_IROUTER351 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER351_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER351_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER351_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER351_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER351_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER351_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER351_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER351_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER351_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER351_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER351_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER351_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER351_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER351_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER351_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER351_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER351_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER351_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER351_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER351_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER351_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER351_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER351_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER351_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER351_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER351_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER351_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER351_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER351_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER351_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER351_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER351_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER351_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER351_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER351_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER352 - GICD_IROUTER352 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER352_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER352_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER352_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER352_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER352_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER352_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER352_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER352_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER352_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER352_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER352_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER352_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER352_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER352_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER352_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER352_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER352_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER352_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER352_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER352_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER352_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER352_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER352_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER352_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER352_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER352_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER352_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER352_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER352_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER352_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER352_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER352_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER352_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER352_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER352_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER353 - GICD_IROUTER353 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER353_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER353_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER353_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER353_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER353_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER353_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER353_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER353_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER353_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER353_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER353_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER353_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER353_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER353_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER353_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER353_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER353_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER353_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER353_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER353_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER353_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER353_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER353_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER353_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER353_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER353_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER353_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER353_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER353_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER353_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER353_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER353_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER353_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER353_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER353_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER354 - GICD_IROUTER354 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER354_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER354_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER354_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER354_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER354_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER354_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER354_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER354_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER354_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER354_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER354_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER354_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER354_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER354_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER354_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER354_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER354_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER354_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER354_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER354_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER354_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER354_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER354_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER354_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER354_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER354_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER354_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER354_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER354_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER354_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER354_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER354_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER354_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER354_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER354_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER355 - GICD_IROUTER355 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER355_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER355_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER355_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER355_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER355_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER355_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER355_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER355_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER355_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER355_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER355_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER355_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER355_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER355_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER355_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER355_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER355_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER355_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER355_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER355_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER355_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER355_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER355_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER355_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER355_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER355_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER355_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER355_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER355_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER355_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER355_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER355_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER355_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER355_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER355_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER356 - GICD_IROUTER356 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER356_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER356_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER356_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER356_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER356_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER356_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER356_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER356_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER356_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER356_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER356_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER356_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER356_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER356_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER356_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER356_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER356_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER356_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER356_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER356_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER356_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER356_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER356_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER356_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER356_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER356_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER356_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER356_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER356_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER356_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER356_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER356_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER356_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER356_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER356_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER357 - GICD_IROUTER357 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER357_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER357_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER357_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER357_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER357_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER357_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER357_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER357_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER357_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER357_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER357_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER357_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER357_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER357_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER357_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER357_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER357_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER357_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER357_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER357_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER357_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER357_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER357_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER357_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER357_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER357_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER357_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER357_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER357_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER357_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER357_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER357_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER357_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER357_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER357_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER358 - GICD_IROUTER358 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER358_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER358_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER358_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER358_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER358_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER358_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER358_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER358_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER358_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER358_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER358_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER358_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER358_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER358_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER358_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER358_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER358_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER358_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER358_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER358_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER358_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER358_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER358_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER358_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER358_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER358_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER358_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER358_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER358_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER358_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER358_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER358_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER358_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER358_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER358_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER359 - GICD_IROUTER359 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER359_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER359_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER359_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER359_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER359_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER359_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER359_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER359_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER359_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER359_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER359_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER359_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER359_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER359_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER359_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER359_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER359_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER359_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER359_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER359_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER359_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER359_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER359_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER359_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER359_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER359_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER359_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER359_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER359_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER359_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER359_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER359_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER359_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER359_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER359_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER360 - GICD_IROUTER360 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER360_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER360_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER360_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER360_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER360_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER360_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER360_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER360_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER360_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER360_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER360_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER360_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER360_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER360_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER360_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER360_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER360_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER360_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER360_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER360_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER360_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER360_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER360_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER360_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER360_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER360_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER360_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER360_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER360_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER360_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER360_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER360_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER360_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER360_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER360_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER361 - GICD_IROUTER361 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER361_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER361_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER361_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER361_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER361_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER361_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER361_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER361_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER361_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER361_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER361_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER361_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER361_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER361_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER361_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER361_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER361_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER361_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER361_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER361_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER361_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER361_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER361_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER361_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER361_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER361_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER361_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER361_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER361_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER361_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER361_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER361_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER361_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER361_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER361_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER362 - GICD_IROUTER362 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER362_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER362_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER362_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER362_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER362_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER362_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER362_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER362_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER362_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER362_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER362_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER362_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER362_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER362_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER362_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER362_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER362_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER362_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER362_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER362_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER362_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER362_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER362_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER362_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER362_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER362_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER362_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER362_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER362_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER362_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER362_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER362_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER362_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER362_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER362_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER363 - GICD_IROUTER363 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER363_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER363_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER363_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER363_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER363_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER363_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER363_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER363_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER363_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER363_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER363_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER363_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER363_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER363_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER363_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER363_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER363_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER363_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER363_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER363_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER363_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER363_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER363_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER363_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER363_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER363_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER363_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER363_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER363_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER363_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER363_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER363_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER363_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER363_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER363_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER364 - GICD_IROUTER364 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER364_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER364_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER364_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER364_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER364_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER364_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER364_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER364_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER364_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER364_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER364_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER364_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER364_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER364_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER364_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER364_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER364_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER364_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER364_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER364_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER364_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER364_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER364_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER364_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER364_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER364_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER364_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER364_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER364_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER364_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER364_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER364_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER364_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER364_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER364_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER365 - GICD_IROUTER365 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER365_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER365_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER365_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER365_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER365_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER365_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER365_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER365_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER365_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER365_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER365_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER365_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER365_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER365_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER365_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER365_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER365_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER365_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER365_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER365_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER365_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER365_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER365_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER365_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER365_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER365_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER365_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER365_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER365_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER365_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER365_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER365_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER365_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER365_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER365_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER366 - GICD_IROUTER366 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER366_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER366_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER366_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER366_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER366_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER366_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER366_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER366_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER366_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER366_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER366_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER366_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER366_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER366_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER366_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER366_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER366_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER366_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER366_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER366_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER366_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER366_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER366_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER366_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER366_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER366_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER366_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER366_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER366_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER366_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER366_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER366_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER366_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER366_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER366_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER367 - GICD_IROUTER367 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER367_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER367_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER367_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER367_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER367_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER367_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER367_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER367_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER367_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER367_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER367_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER367_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER367_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER367_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER367_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER367_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER367_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER367_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER367_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER367_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER367_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER367_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER367_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER367_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER367_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER367_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER367_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER367_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER367_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER367_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER367_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER367_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER367_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER367_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER367_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER368 - GICD_IROUTER368 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER368_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER368_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER368_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER368_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER368_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER368_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER368_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER368_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER368_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER368_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER368_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER368_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER368_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER368_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER368_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER368_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER368_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER368_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER368_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER368_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER368_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER368_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER368_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER368_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER368_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER368_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER368_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER368_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER368_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER368_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER368_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER368_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER368_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER368_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER368_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER369 - GICD_IROUTER369 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER369_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER369_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER369_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER369_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER369_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER369_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER369_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER369_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER369_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER369_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER369_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER369_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER369_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER369_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER369_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER369_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER369_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER369_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER369_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER369_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER369_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER369_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER369_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER369_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER369_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER369_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER369_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER369_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER369_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER369_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER369_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER369_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER369_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER369_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER369_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER370 - GICD_IROUTER370 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER370_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER370_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER370_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER370_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER370_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER370_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER370_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER370_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER370_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER370_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER370_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER370_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER370_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER370_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER370_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER370_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER370_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER370_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER370_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER370_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER370_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER370_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER370_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER370_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER370_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER370_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER370_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER370_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER370_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER370_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER370_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER370_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER370_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER370_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER370_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER371 - GICD_IROUTER371 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER371_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER371_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER371_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER371_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER371_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER371_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER371_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER371_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER371_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER371_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER371_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER371_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER371_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER371_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER371_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER371_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER371_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER371_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER371_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER371_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER371_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER371_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER371_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER371_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER371_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER371_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER371_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER371_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER371_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER371_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER371_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER371_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER371_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER371_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER371_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER372 - GICD_IROUTER372 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER372_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER372_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER372_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER372_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER372_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER372_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER372_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER372_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER372_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER372_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER372_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER372_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER372_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER372_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER372_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER372_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER372_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER372_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER372_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER372_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER372_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER372_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER372_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER372_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER372_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER372_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER372_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER372_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER372_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER372_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER372_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER372_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER372_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER372_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER372_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER373 - GICD_IROUTER373 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER373_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER373_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER373_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER373_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER373_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER373_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER373_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER373_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER373_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER373_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER373_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER373_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER373_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER373_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER373_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER373_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER373_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER373_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER373_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER373_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER373_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER373_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER373_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER373_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER373_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER373_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER373_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER373_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER373_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER373_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER373_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER373_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER373_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER373_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER373_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER374 - GICD_IROUTER374 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER374_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER374_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER374_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER374_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER374_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER374_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER374_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER374_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER374_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER374_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER374_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER374_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER374_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER374_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER374_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER374_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER374_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER374_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER374_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER374_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER374_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER374_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER374_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER374_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER374_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER374_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER374_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER374_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER374_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER374_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER374_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER374_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER374_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER374_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER374_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER375 - GICD_IROUTER375 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER375_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER375_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER375_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER375_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER375_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER375_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER375_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER375_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER375_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER375_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER375_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER375_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER375_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER375_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER375_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER375_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER375_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER375_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER375_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER375_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER375_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER375_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER375_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER375_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER375_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER375_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER375_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER375_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER375_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER375_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER375_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER375_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER375_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER375_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER375_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER376 - GICD_IROUTER376 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER376_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER376_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER376_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER376_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER376_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER376_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER376_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER376_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER376_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER376_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER376_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER376_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER376_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER376_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER376_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER376_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER376_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER376_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER376_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER376_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER376_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER376_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER376_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER376_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER376_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER376_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER376_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER376_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER376_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER376_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER376_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER376_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER376_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER376_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER376_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER377 - GICD_IROUTER377 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER377_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER377_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER377_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER377_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER377_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER377_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER377_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER377_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER377_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER377_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER377_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER377_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER377_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER377_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER377_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER377_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER377_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER377_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER377_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER377_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER377_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER377_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER377_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER377_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER377_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER377_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER377_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER377_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER377_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER377_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER377_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER377_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER377_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER377_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER377_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER378 - GICD_IROUTER378 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER378_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER378_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER378_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER378_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER378_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER378_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER378_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER378_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER378_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER378_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER378_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER378_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER378_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER378_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER378_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER378_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER378_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER378_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER378_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER378_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER378_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER378_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER378_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER378_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER378_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER378_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER378_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER378_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER378_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER378_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER378_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER378_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER378_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER378_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER378_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER379 - GICD_IROUTER379 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER379_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER379_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER379_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER379_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER379_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER379_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER379_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER379_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER379_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER379_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER379_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER379_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER379_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER379_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER379_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER379_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER379_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER379_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER379_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER379_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER379_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER379_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER379_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER379_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER379_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER379_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER379_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER379_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER379_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER379_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER379_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER379_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER379_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER379_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER379_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER380 - GICD_IROUTER380 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER380_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER380_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER380_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER380_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER380_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER380_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER380_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER380_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER380_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER380_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER380_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER380_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER380_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER380_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER380_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER380_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER380_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER380_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER380_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER380_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER380_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER380_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER380_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER380_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER380_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER380_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER380_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER380_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER380_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER380_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER380_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER380_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER380_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER380_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER380_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER381 - GICD_IROUTER381 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER381_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER381_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER381_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER381_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER381_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER381_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER381_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER381_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER381_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER381_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER381_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER381_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER381_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER381_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER381_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER381_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER381_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER381_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER381_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER381_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER381_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER381_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER381_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER381_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER381_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER381_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER381_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER381_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER381_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER381_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER381_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER381_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER381_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER381_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER381_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER382 - GICD_IROUTER382 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER382_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER382_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER382_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER382_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER382_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER382_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER382_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER382_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER382_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER382_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER382_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER382_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER382_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER382_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER382_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER382_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER382_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER382_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER382_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER382_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER382_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER382_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER382_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER382_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER382_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER382_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER382_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER382_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER382_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER382_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER382_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER382_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER382_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER382_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER382_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER383 - GICD_IROUTER383 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER383_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER383_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER383_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER383_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER383_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER383_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER383_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER383_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER383_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER383_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER383_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER383_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER383_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER383_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER383_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER383_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER383_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER383_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER383_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER383_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER383_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER383_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER383_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER383_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER383_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER383_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER383_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER383_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER383_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER383_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER383_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER383_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER383_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER383_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER383_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER384 - GICD_IROUTER384 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER384_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER384_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER384_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER384_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER384_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER384_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER384_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER384_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER384_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER384_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER384_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER384_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER384_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER384_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER384_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER384_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER384_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER384_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER384_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER384_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER384_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER384_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER384_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER384_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER384_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER384_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER384_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER384_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER384_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER384_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER384_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER384_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER384_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER384_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER384_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER385 - GICD_IROUTER385 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER385_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER385_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER385_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER385_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER385_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER385_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER385_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER385_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER385_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER385_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER385_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER385_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER385_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER385_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER385_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER385_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER385_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER385_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER385_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER385_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER385_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER385_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER385_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER385_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER385_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER385_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER385_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER385_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER385_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER385_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER385_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER385_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER385_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER385_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER385_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER386 - GICD_IROUTER386 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER386_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER386_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER386_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER386_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER386_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER386_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER386_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER386_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER386_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER386_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER386_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER386_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER386_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER386_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER386_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER386_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER386_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER386_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER386_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER386_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER386_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER386_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER386_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER386_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER386_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER386_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER386_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER386_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER386_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER386_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER386_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER386_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER386_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER386_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER386_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER387 - GICD_IROUTER387 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER387_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER387_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER387_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER387_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER387_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER387_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER387_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER387_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER387_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER387_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER387_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER387_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER387_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER387_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER387_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER387_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER387_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER387_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER387_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER387_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER387_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER387_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER387_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER387_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER387_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER387_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER387_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER387_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER387_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER387_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER387_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER387_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER387_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER387_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER387_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER388 - GICD_IROUTER388 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER388_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER388_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER388_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER388_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER388_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER388_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER388_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER388_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER388_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER388_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER388_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER388_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER388_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER388_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER388_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER388_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER388_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER388_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER388_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER388_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER388_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER388_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER388_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER388_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER388_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER388_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER388_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER388_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER388_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER388_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER388_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER388_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER388_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER388_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER388_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER389 - GICD_IROUTER389 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER389_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER389_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER389_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER389_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER389_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER389_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER389_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER389_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER389_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER389_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER389_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER389_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER389_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER389_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER389_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER389_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER389_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER389_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER389_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER389_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER389_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER389_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER389_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER389_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER389_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER389_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER389_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER389_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER389_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER389_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER389_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER389_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER389_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER389_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER389_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER390 - GICD_IROUTER390 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER390_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER390_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER390_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER390_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER390_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER390_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER390_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER390_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER390_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER390_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER390_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER390_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER390_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER390_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER390_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER390_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER390_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER390_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER390_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER390_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER390_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER390_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER390_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER390_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER390_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER390_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER390_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER390_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER390_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER390_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER390_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER390_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER390_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER390_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER390_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER391 - GICD_IROUTER391 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER391_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER391_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER391_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER391_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER391_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER391_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER391_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER391_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER391_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER391_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER391_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER391_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER391_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER391_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER391_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER391_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER391_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER391_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER391_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER391_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER391_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER391_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER391_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER391_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER391_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER391_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER391_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER391_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER391_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER391_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER391_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER391_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER391_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER391_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER391_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER392 - GICD_IROUTER392 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER392_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER392_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER392_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER392_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER392_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER392_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER392_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER392_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER392_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER392_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER392_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER392_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER392_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER392_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER392_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER392_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER392_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER392_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER392_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER392_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER392_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER392_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER392_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER392_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER392_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER392_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER392_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER392_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER392_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER392_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER392_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER392_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER392_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER392_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER392_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER393 - GICD_IROUTER393 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER393_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER393_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER393_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER393_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER393_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER393_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER393_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER393_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER393_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER393_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER393_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER393_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER393_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER393_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER393_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER393_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER393_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER393_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER393_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER393_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER393_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER393_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER393_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER393_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER393_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER393_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER393_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER393_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER393_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER393_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER393_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER393_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER393_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER393_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER393_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER394 - GICD_IROUTER394 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER394_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER394_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER394_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER394_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER394_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER394_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER394_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER394_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER394_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER394_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER394_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER394_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER394_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER394_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER394_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER394_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER394_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER394_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER394_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER394_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER394_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER394_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER394_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER394_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER394_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER394_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER394_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER394_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER394_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER394_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER394_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER394_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER394_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER394_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER394_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER395 - GICD_IROUTER395 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER395_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER395_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER395_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER395_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER395_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER395_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER395_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER395_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER395_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER395_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER395_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER395_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER395_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER395_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER395_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER395_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER395_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER395_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER395_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER395_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER395_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER395_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER395_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER395_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER395_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER395_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER395_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER395_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER395_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER395_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER395_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER395_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER395_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER395_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER395_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER396 - GICD_IROUTER396 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER396_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER396_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER396_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER396_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER396_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER396_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER396_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER396_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER396_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER396_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER396_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER396_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER396_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER396_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER396_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER396_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER396_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER396_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER396_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER396_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER396_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER396_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER396_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER396_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER396_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER396_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER396_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER396_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER396_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER396_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER396_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER396_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER396_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER396_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER396_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER397 - GICD_IROUTER397 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER397_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER397_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER397_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER397_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER397_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER397_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER397_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER397_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER397_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER397_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER397_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER397_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER397_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER397_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER397_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER397_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER397_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER397_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER397_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER397_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER397_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER397_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER397_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER397_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER397_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER397_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER397_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER397_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER397_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER397_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER397_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER397_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER397_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER397_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER397_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER398 - GICD_IROUTER398 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER398_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER398_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER398_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER398_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER398_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER398_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER398_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER398_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER398_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER398_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER398_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER398_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER398_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER398_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER398_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER398_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER398_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER398_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER398_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER398_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER398_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER398_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER398_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER398_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER398_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER398_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER398_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER398_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER398_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER398_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER398_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER398_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER398_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER398_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER398_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER399 - GICD_IROUTER399 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER399_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER399_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER399_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER399_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER399_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER399_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER399_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER399_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER399_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER399_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER399_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER399_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER399_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER399_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER399_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER399_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER399_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER399_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER399_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER399_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER399_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER399_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER399_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER399_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER399_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER399_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER399_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER399_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER399_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER399_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER399_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER399_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER399_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER399_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER399_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER400 - GICD_IROUTER400 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER400_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER400_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER400_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER400_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER400_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER400_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER400_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER400_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER400_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER400_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER400_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER400_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER400_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER400_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER400_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER400_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER400_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER400_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER400_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER400_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER400_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER400_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER400_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER400_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER400_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER400_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER400_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER400_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER400_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER400_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER400_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER400_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER400_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER400_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER400_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER401 - GICD_IROUTER401 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER401_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER401_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER401_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER401_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER401_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER401_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER401_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER401_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER401_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER401_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER401_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER401_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER401_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER401_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER401_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER401_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER401_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER401_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER401_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER401_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER401_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER401_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER401_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER401_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER401_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER401_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER401_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER401_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER401_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER401_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER401_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER401_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER401_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER401_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER401_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER402 - GICD_IROUTER402 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER402_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER402_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER402_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER402_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER402_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER402_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER402_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER402_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER402_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER402_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER402_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER402_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER402_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER402_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER402_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER402_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER402_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER402_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER402_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER402_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER402_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER402_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER402_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER402_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER402_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER402_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER402_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER402_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER402_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER402_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER402_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER402_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER402_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER402_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER402_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER403 - GICD_IROUTER403 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER403_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER403_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER403_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER403_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER403_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER403_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER403_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER403_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER403_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER403_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER403_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER403_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER403_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER403_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER403_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER403_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER403_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER403_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER403_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER403_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER403_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER403_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER403_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER403_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER403_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER403_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER403_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER403_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER403_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER403_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER403_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER403_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER403_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER403_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER403_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER404 - GICD_IROUTER404 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER404_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER404_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER404_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER404_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER404_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER404_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER404_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER404_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER404_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER404_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER404_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER404_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER404_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER404_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER404_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER404_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER404_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER404_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER404_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER404_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER404_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER404_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER404_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER404_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER404_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER404_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER404_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER404_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER404_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER404_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER404_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER404_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER404_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER404_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER404_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER405 - GICD_IROUTER405 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER405_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER405_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER405_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER405_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER405_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER405_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER405_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER405_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER405_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER405_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER405_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER405_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER405_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER405_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER405_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER405_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER405_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER405_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER405_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER405_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER405_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER405_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER405_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER405_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER405_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER405_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER405_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER405_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER405_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER405_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER405_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER405_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER405_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER405_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER405_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER406 - GICD_IROUTER406 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER406_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER406_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER406_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER406_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER406_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER406_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER406_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER406_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER406_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER406_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER406_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER406_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER406_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER406_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER406_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER406_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER406_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER406_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER406_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER406_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER406_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER406_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER406_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER406_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER406_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER406_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER406_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER406_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER406_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER406_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER406_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER406_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER406_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER406_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER406_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER407 - GICD_IROUTER407 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER407_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER407_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER407_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER407_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER407_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER407_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER407_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER407_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER407_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER407_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER407_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER407_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER407_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER407_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER407_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER407_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER407_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER407_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER407_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER407_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER407_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER407_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER407_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER407_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER407_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER407_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER407_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER407_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER407_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER407_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER407_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER407_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER407_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER407_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER407_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER408 - GICD_IROUTER408 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER408_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER408_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER408_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER408_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER408_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER408_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER408_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER408_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER408_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER408_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER408_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER408_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER408_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER408_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER408_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER408_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER408_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER408_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER408_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER408_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER408_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER408_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER408_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER408_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER408_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER408_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER408_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER408_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER408_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER408_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER408_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER408_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER408_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER408_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER408_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER409 - GICD_IROUTER409 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER409_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER409_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER409_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER409_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER409_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER409_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER409_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER409_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER409_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER409_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER409_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER409_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER409_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER409_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER409_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER409_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER409_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER409_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER409_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER409_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER409_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER409_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER409_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER409_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER409_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER409_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER409_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER409_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER409_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER409_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER409_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER409_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER409_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER409_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER409_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER410 - GICD_IROUTER410 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER410_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER410_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER410_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER410_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER410_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER410_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER410_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER410_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER410_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER410_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER410_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER410_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER410_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER410_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER410_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER410_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER410_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER410_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER410_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER410_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER410_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER410_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER410_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER410_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER410_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER410_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER410_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER410_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER410_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER410_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER410_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER410_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER410_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER410_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER410_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER411 - GICD_IROUTER411 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER411_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER411_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER411_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER411_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER411_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER411_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER411_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER411_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER411_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER411_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER411_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER411_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER411_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER411_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER411_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER411_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER411_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER411_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER411_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER411_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER411_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER411_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER411_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER411_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER411_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER411_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER411_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER411_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER411_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER411_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER411_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER411_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER411_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER411_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER411_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER412 - GICD_IROUTER412 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER412_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER412_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER412_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER412_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER412_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER412_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER412_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER412_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER412_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER412_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER412_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER412_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER412_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER412_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER412_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER412_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER412_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER412_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER412_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER412_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER412_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER412_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER412_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER412_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER412_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER412_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER412_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER412_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER412_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER412_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER412_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER412_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER412_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER412_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER412_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER413 - GICD_IROUTER413 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER413_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER413_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER413_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER413_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER413_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER413_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER413_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER413_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER413_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER413_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER413_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER413_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER413_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER413_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER413_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER413_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER413_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER413_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER413_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER413_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER413_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER413_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER413_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER413_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER413_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER413_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER413_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER413_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER413_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER413_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER413_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER413_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER413_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER413_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER413_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER414 - GICD_IROUTER414 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER414_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER414_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER414_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER414_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER414_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER414_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER414_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER414_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER414_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER414_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER414_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER414_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER414_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER414_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER414_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER414_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER414_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER414_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER414_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER414_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER414_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER414_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER414_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER414_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER414_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER414_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER414_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER414_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER414_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER414_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER414_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER414_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER414_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER414_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER414_RESERVED1_MASK) /*! @} */ /*! @name GICD_IROUTER415 - GICD_IROUTER415 */ /*! @{ */ #define NOC_GICD_GICD_IROUTER415_Affinity0_MASK (0xFFU) #define NOC_GICD_GICD_IROUTER415_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICD_GICD_IROUTER415_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER415_Affinity0_SHIFT)) & NOC_GICD_GICD_IROUTER415_Affinity0_MASK) #define NOC_GICD_GICD_IROUTER415_Affinity1_MASK (0xFF00U) #define NOC_GICD_GICD_IROUTER415_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICD_GICD_IROUTER415_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER415_Affinity1_SHIFT)) & NOC_GICD_GICD_IROUTER415_Affinity1_MASK) #define NOC_GICD_GICD_IROUTER415_Affinity2_MASK (0xFF0000U) #define NOC_GICD_GICD_IROUTER415_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICD_GICD_IROUTER415_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER415_Affinity2_SHIFT)) & NOC_GICD_GICD_IROUTER415_Affinity2_MASK) #define NOC_GICD_GICD_IROUTER415_RESERVED0_MASK (0x7F000000U) #define NOC_GICD_GICD_IROUTER415_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_IROUTER415_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER415_RESERVED0_SHIFT)) & NOC_GICD_GICD_IROUTER415_RESERVED0_MASK) #define NOC_GICD_GICD_IROUTER415_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICD_GICD_IROUTER415_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICD_GICD_IROUTER415_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER415_InterruptRoutingMode_SHIFT)) & NOC_GICD_GICD_IROUTER415_InterruptRoutingMode_MASK) #define NOC_GICD_GICD_IROUTER415_Affinity3_MASK (0xFF00000000U) #define NOC_GICD_GICD_IROUTER415_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICD_GICD_IROUTER415_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER415_Affinity3_SHIFT)) & NOC_GICD_GICD_IROUTER415_Affinity3_MASK) #define NOC_GICD_GICD_IROUTER415_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICD_GICD_IROUTER415_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_IROUTER415_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_IROUTER415_RESERVED1_SHIFT)) & NOC_GICD_GICD_IROUTER415_RESERVED1_MASK) /*! @} */ /*! @name GICD_RDOFFR0 - GICD_RDOFFR0 */ /*! @{ */ #define NOC_GICD_GICD_RDOFFR0_RD_OFF_MASK (0x3FU) #define NOC_GICD_GICD_RDOFFR0_RD_OFF_SHIFT (0U) /*! RD_OFF - RD_OFF */ #define NOC_GICD_GICD_RDOFFR0_RD_OFF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_RDOFFR0_RD_OFF_SHIFT)) & NOC_GICD_GICD_RDOFFR0_RD_OFF_MASK) #define NOC_GICD_GICD_RDOFFR0_RESERVED0_MASK (0xFFFFFFFFFFFFFFC0U) #define NOC_GICD_GICD_RDOFFR0_RESERVED0_SHIFT (6U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_RDOFFR0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_RDOFFR0_RESERVED0_SHIFT)) & NOC_GICD_GICD_RDOFFR0_RESERVED0_MASK) /*! @} */ /*! @name GICD_ICLAR2 - GICD_ICLAR2 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR2_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR2_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR2_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes0_MASK) #define NOC_GICD_GICD_ICLAR2_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR2_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR2_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes1_MASK) #define NOC_GICD_GICD_ICLAR2_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR2_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR2_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes2_MASK) #define NOC_GICD_GICD_ICLAR2_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR2_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR2_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes3_MASK) #define NOC_GICD_GICD_ICLAR2_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR2_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR2_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes4_MASK) #define NOC_GICD_GICD_ICLAR2_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR2_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR2_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes5_MASK) #define NOC_GICD_GICD_ICLAR2_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR2_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR2_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes6_MASK) #define NOC_GICD_GICD_ICLAR2_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR2_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR2_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes7_MASK) #define NOC_GICD_GICD_ICLAR2_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR2_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR2_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes8_MASK) #define NOC_GICD_GICD_ICLAR2_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR2_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR2_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes9_MASK) #define NOC_GICD_GICD_ICLAR2_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR2_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR2_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes10_MASK) #define NOC_GICD_GICD_ICLAR2_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR2_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR2_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes11_MASK) #define NOC_GICD_GICD_ICLAR2_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR2_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR2_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes12_MASK) #define NOC_GICD_GICD_ICLAR2_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR2_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR2_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes13_MASK) #define NOC_GICD_GICD_ICLAR2_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR2_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR2_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes14_MASK) #define NOC_GICD_GICD_ICLAR2_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR2_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR2_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR2_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR2_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR3 - GICD_ICLAR3 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR3_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR3_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR3_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes0_MASK) #define NOC_GICD_GICD_ICLAR3_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR3_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR3_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes1_MASK) #define NOC_GICD_GICD_ICLAR3_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR3_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR3_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes2_MASK) #define NOC_GICD_GICD_ICLAR3_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR3_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR3_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes3_MASK) #define NOC_GICD_GICD_ICLAR3_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR3_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR3_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes4_MASK) #define NOC_GICD_GICD_ICLAR3_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR3_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR3_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes5_MASK) #define NOC_GICD_GICD_ICLAR3_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR3_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR3_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes6_MASK) #define NOC_GICD_GICD_ICLAR3_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR3_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR3_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes7_MASK) #define NOC_GICD_GICD_ICLAR3_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR3_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR3_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes8_MASK) #define NOC_GICD_GICD_ICLAR3_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR3_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR3_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes9_MASK) #define NOC_GICD_GICD_ICLAR3_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR3_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR3_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes10_MASK) #define NOC_GICD_GICD_ICLAR3_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR3_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR3_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes11_MASK) #define NOC_GICD_GICD_ICLAR3_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR3_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR3_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes12_MASK) #define NOC_GICD_GICD_ICLAR3_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR3_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR3_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes13_MASK) #define NOC_GICD_GICD_ICLAR3_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR3_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR3_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes14_MASK) #define NOC_GICD_GICD_ICLAR3_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR3_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR3_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR3_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR3_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR4 - GICD_ICLAR4 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR4_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR4_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR4_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes0_MASK) #define NOC_GICD_GICD_ICLAR4_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR4_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR4_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes1_MASK) #define NOC_GICD_GICD_ICLAR4_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR4_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR4_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes2_MASK) #define NOC_GICD_GICD_ICLAR4_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR4_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR4_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes3_MASK) #define NOC_GICD_GICD_ICLAR4_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR4_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR4_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes4_MASK) #define NOC_GICD_GICD_ICLAR4_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR4_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR4_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes5_MASK) #define NOC_GICD_GICD_ICLAR4_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR4_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR4_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes6_MASK) #define NOC_GICD_GICD_ICLAR4_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR4_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR4_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes7_MASK) #define NOC_GICD_GICD_ICLAR4_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR4_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR4_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes8_MASK) #define NOC_GICD_GICD_ICLAR4_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR4_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR4_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes9_MASK) #define NOC_GICD_GICD_ICLAR4_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR4_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR4_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes10_MASK) #define NOC_GICD_GICD_ICLAR4_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR4_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR4_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes11_MASK) #define NOC_GICD_GICD_ICLAR4_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR4_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR4_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes12_MASK) #define NOC_GICD_GICD_ICLAR4_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR4_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR4_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes13_MASK) #define NOC_GICD_GICD_ICLAR4_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR4_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR4_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes14_MASK) #define NOC_GICD_GICD_ICLAR4_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR4_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR4_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR4_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR4_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR5 - GICD_ICLAR5 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR5_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR5_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR5_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes0_MASK) #define NOC_GICD_GICD_ICLAR5_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR5_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR5_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes1_MASK) #define NOC_GICD_GICD_ICLAR5_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR5_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR5_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes2_MASK) #define NOC_GICD_GICD_ICLAR5_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR5_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR5_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes3_MASK) #define NOC_GICD_GICD_ICLAR5_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR5_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR5_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes4_MASK) #define NOC_GICD_GICD_ICLAR5_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR5_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR5_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes5_MASK) #define NOC_GICD_GICD_ICLAR5_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR5_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR5_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes6_MASK) #define NOC_GICD_GICD_ICLAR5_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR5_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR5_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes7_MASK) #define NOC_GICD_GICD_ICLAR5_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR5_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR5_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes8_MASK) #define NOC_GICD_GICD_ICLAR5_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR5_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR5_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes9_MASK) #define NOC_GICD_GICD_ICLAR5_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR5_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR5_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes10_MASK) #define NOC_GICD_GICD_ICLAR5_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR5_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR5_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes11_MASK) #define NOC_GICD_GICD_ICLAR5_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR5_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR5_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes12_MASK) #define NOC_GICD_GICD_ICLAR5_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR5_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR5_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes13_MASK) #define NOC_GICD_GICD_ICLAR5_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR5_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR5_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes14_MASK) #define NOC_GICD_GICD_ICLAR5_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR5_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR5_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR5_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR5_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR6 - GICD_ICLAR6 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR6_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR6_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR6_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes0_MASK) #define NOC_GICD_GICD_ICLAR6_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR6_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR6_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes1_MASK) #define NOC_GICD_GICD_ICLAR6_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR6_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR6_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes2_MASK) #define NOC_GICD_GICD_ICLAR6_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR6_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR6_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes3_MASK) #define NOC_GICD_GICD_ICLAR6_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR6_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR6_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes4_MASK) #define NOC_GICD_GICD_ICLAR6_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR6_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR6_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes5_MASK) #define NOC_GICD_GICD_ICLAR6_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR6_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR6_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes6_MASK) #define NOC_GICD_GICD_ICLAR6_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR6_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR6_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes7_MASK) #define NOC_GICD_GICD_ICLAR6_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR6_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR6_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes8_MASK) #define NOC_GICD_GICD_ICLAR6_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR6_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR6_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes9_MASK) #define NOC_GICD_GICD_ICLAR6_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR6_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR6_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes10_MASK) #define NOC_GICD_GICD_ICLAR6_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR6_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR6_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes11_MASK) #define NOC_GICD_GICD_ICLAR6_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR6_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR6_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes12_MASK) #define NOC_GICD_GICD_ICLAR6_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR6_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR6_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes13_MASK) #define NOC_GICD_GICD_ICLAR6_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR6_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR6_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes14_MASK) #define NOC_GICD_GICD_ICLAR6_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR6_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR6_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR6_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR6_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR7 - GICD_ICLAR7 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR7_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR7_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR7_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes0_MASK) #define NOC_GICD_GICD_ICLAR7_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR7_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR7_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes1_MASK) #define NOC_GICD_GICD_ICLAR7_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR7_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR7_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes2_MASK) #define NOC_GICD_GICD_ICLAR7_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR7_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR7_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes3_MASK) #define NOC_GICD_GICD_ICLAR7_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR7_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR7_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes4_MASK) #define NOC_GICD_GICD_ICLAR7_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR7_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR7_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes5_MASK) #define NOC_GICD_GICD_ICLAR7_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR7_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR7_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes6_MASK) #define NOC_GICD_GICD_ICLAR7_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR7_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR7_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes7_MASK) #define NOC_GICD_GICD_ICLAR7_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR7_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR7_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes8_MASK) #define NOC_GICD_GICD_ICLAR7_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR7_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR7_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes9_MASK) #define NOC_GICD_GICD_ICLAR7_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR7_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR7_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes10_MASK) #define NOC_GICD_GICD_ICLAR7_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR7_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR7_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes11_MASK) #define NOC_GICD_GICD_ICLAR7_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR7_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR7_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes12_MASK) #define NOC_GICD_GICD_ICLAR7_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR7_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR7_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes13_MASK) #define NOC_GICD_GICD_ICLAR7_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR7_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR7_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes14_MASK) #define NOC_GICD_GICD_ICLAR7_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR7_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR7_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR7_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR7_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR8 - GICD_ICLAR8 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR8_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR8_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR8_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes0_MASK) #define NOC_GICD_GICD_ICLAR8_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR8_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR8_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes1_MASK) #define NOC_GICD_GICD_ICLAR8_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR8_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR8_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes2_MASK) #define NOC_GICD_GICD_ICLAR8_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR8_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR8_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes3_MASK) #define NOC_GICD_GICD_ICLAR8_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR8_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR8_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes4_MASK) #define NOC_GICD_GICD_ICLAR8_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR8_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR8_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes5_MASK) #define NOC_GICD_GICD_ICLAR8_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR8_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR8_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes6_MASK) #define NOC_GICD_GICD_ICLAR8_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR8_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR8_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes7_MASK) #define NOC_GICD_GICD_ICLAR8_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR8_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR8_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes8_MASK) #define NOC_GICD_GICD_ICLAR8_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR8_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR8_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes9_MASK) #define NOC_GICD_GICD_ICLAR8_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR8_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR8_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes10_MASK) #define NOC_GICD_GICD_ICLAR8_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR8_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR8_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes11_MASK) #define NOC_GICD_GICD_ICLAR8_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR8_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR8_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes12_MASK) #define NOC_GICD_GICD_ICLAR8_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR8_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR8_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes13_MASK) #define NOC_GICD_GICD_ICLAR8_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR8_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR8_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes14_MASK) #define NOC_GICD_GICD_ICLAR8_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR8_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR8_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR8_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR8_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR9 - GICD_ICLAR9 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR9_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR9_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR9_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes0_MASK) #define NOC_GICD_GICD_ICLAR9_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR9_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR9_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes1_MASK) #define NOC_GICD_GICD_ICLAR9_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR9_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR9_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes2_MASK) #define NOC_GICD_GICD_ICLAR9_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR9_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR9_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes3_MASK) #define NOC_GICD_GICD_ICLAR9_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR9_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR9_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes4_MASK) #define NOC_GICD_GICD_ICLAR9_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR9_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR9_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes5_MASK) #define NOC_GICD_GICD_ICLAR9_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR9_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR9_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes6_MASK) #define NOC_GICD_GICD_ICLAR9_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR9_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR9_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes7_MASK) #define NOC_GICD_GICD_ICLAR9_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR9_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR9_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes8_MASK) #define NOC_GICD_GICD_ICLAR9_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR9_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR9_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes9_MASK) #define NOC_GICD_GICD_ICLAR9_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR9_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR9_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes10_MASK) #define NOC_GICD_GICD_ICLAR9_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR9_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR9_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes11_MASK) #define NOC_GICD_GICD_ICLAR9_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR9_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR9_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes12_MASK) #define NOC_GICD_GICD_ICLAR9_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR9_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR9_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes13_MASK) #define NOC_GICD_GICD_ICLAR9_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR9_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR9_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes14_MASK) #define NOC_GICD_GICD_ICLAR9_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR9_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR9_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR9_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR9_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR10 - GICD_ICLAR10 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR10_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR10_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR10_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes0_MASK) #define NOC_GICD_GICD_ICLAR10_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR10_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR10_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes1_MASK) #define NOC_GICD_GICD_ICLAR10_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR10_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR10_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes2_MASK) #define NOC_GICD_GICD_ICLAR10_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR10_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR10_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes3_MASK) #define NOC_GICD_GICD_ICLAR10_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR10_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR10_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes4_MASK) #define NOC_GICD_GICD_ICLAR10_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR10_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR10_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes5_MASK) #define NOC_GICD_GICD_ICLAR10_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR10_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR10_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes6_MASK) #define NOC_GICD_GICD_ICLAR10_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR10_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR10_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes7_MASK) #define NOC_GICD_GICD_ICLAR10_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR10_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR10_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes8_MASK) #define NOC_GICD_GICD_ICLAR10_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR10_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR10_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes9_MASK) #define NOC_GICD_GICD_ICLAR10_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR10_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR10_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes10_MASK) #define NOC_GICD_GICD_ICLAR10_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR10_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR10_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes11_MASK) #define NOC_GICD_GICD_ICLAR10_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR10_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR10_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes12_MASK) #define NOC_GICD_GICD_ICLAR10_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR10_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR10_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes13_MASK) #define NOC_GICD_GICD_ICLAR10_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR10_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR10_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes14_MASK) #define NOC_GICD_GICD_ICLAR10_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR10_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR10_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR10_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR10_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR11 - GICD_ICLAR11 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR11_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR11_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR11_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes0_MASK) #define NOC_GICD_GICD_ICLAR11_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR11_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR11_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes1_MASK) #define NOC_GICD_GICD_ICLAR11_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR11_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR11_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes2_MASK) #define NOC_GICD_GICD_ICLAR11_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR11_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR11_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes3_MASK) #define NOC_GICD_GICD_ICLAR11_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR11_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR11_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes4_MASK) #define NOC_GICD_GICD_ICLAR11_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR11_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR11_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes5_MASK) #define NOC_GICD_GICD_ICLAR11_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR11_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR11_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes6_MASK) #define NOC_GICD_GICD_ICLAR11_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR11_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR11_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes7_MASK) #define NOC_GICD_GICD_ICLAR11_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR11_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR11_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes8_MASK) #define NOC_GICD_GICD_ICLAR11_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR11_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR11_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes9_MASK) #define NOC_GICD_GICD_ICLAR11_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR11_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR11_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes10_MASK) #define NOC_GICD_GICD_ICLAR11_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR11_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR11_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes11_MASK) #define NOC_GICD_GICD_ICLAR11_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR11_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR11_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes12_MASK) #define NOC_GICD_GICD_ICLAR11_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR11_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR11_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes13_MASK) #define NOC_GICD_GICD_ICLAR11_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR11_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR11_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes14_MASK) #define NOC_GICD_GICD_ICLAR11_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR11_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR11_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR11_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR11_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR12 - GICD_ICLAR12 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR12_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR12_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR12_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes0_MASK) #define NOC_GICD_GICD_ICLAR12_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR12_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR12_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes1_MASK) #define NOC_GICD_GICD_ICLAR12_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR12_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR12_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes2_MASK) #define NOC_GICD_GICD_ICLAR12_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR12_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR12_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes3_MASK) #define NOC_GICD_GICD_ICLAR12_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR12_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR12_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes4_MASK) #define NOC_GICD_GICD_ICLAR12_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR12_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR12_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes5_MASK) #define NOC_GICD_GICD_ICLAR12_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR12_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR12_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes6_MASK) #define NOC_GICD_GICD_ICLAR12_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR12_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR12_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes7_MASK) #define NOC_GICD_GICD_ICLAR12_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR12_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR12_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes8_MASK) #define NOC_GICD_GICD_ICLAR12_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR12_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR12_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes9_MASK) #define NOC_GICD_GICD_ICLAR12_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR12_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR12_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes10_MASK) #define NOC_GICD_GICD_ICLAR12_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR12_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR12_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes11_MASK) #define NOC_GICD_GICD_ICLAR12_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR12_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR12_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes12_MASK) #define NOC_GICD_GICD_ICLAR12_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR12_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR12_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes13_MASK) #define NOC_GICD_GICD_ICLAR12_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR12_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR12_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes14_MASK) #define NOC_GICD_GICD_ICLAR12_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR12_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR12_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR12_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR12_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR13 - GICD_ICLAR13 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR13_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR13_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR13_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes0_MASK) #define NOC_GICD_GICD_ICLAR13_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR13_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR13_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes1_MASK) #define NOC_GICD_GICD_ICLAR13_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR13_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR13_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes2_MASK) #define NOC_GICD_GICD_ICLAR13_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR13_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR13_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes3_MASK) #define NOC_GICD_GICD_ICLAR13_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR13_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR13_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes4_MASK) #define NOC_GICD_GICD_ICLAR13_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR13_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR13_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes5_MASK) #define NOC_GICD_GICD_ICLAR13_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR13_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR13_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes6_MASK) #define NOC_GICD_GICD_ICLAR13_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR13_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR13_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes7_MASK) #define NOC_GICD_GICD_ICLAR13_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR13_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR13_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes8_MASK) #define NOC_GICD_GICD_ICLAR13_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR13_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR13_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes9_MASK) #define NOC_GICD_GICD_ICLAR13_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR13_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR13_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes10_MASK) #define NOC_GICD_GICD_ICLAR13_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR13_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR13_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes11_MASK) #define NOC_GICD_GICD_ICLAR13_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR13_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR13_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes12_MASK) #define NOC_GICD_GICD_ICLAR13_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR13_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR13_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes13_MASK) #define NOC_GICD_GICD_ICLAR13_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR13_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR13_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes14_MASK) #define NOC_GICD_GICD_ICLAR13_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR13_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR13_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR13_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR13_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR14 - GICD_ICLAR14 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR14_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR14_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR14_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes0_MASK) #define NOC_GICD_GICD_ICLAR14_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR14_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR14_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes1_MASK) #define NOC_GICD_GICD_ICLAR14_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR14_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR14_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes2_MASK) #define NOC_GICD_GICD_ICLAR14_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR14_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR14_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes3_MASK) #define NOC_GICD_GICD_ICLAR14_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR14_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR14_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes4_MASK) #define NOC_GICD_GICD_ICLAR14_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR14_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR14_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes5_MASK) #define NOC_GICD_GICD_ICLAR14_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR14_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR14_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes6_MASK) #define NOC_GICD_GICD_ICLAR14_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR14_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR14_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes7_MASK) #define NOC_GICD_GICD_ICLAR14_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR14_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR14_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes8_MASK) #define NOC_GICD_GICD_ICLAR14_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR14_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR14_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes9_MASK) #define NOC_GICD_GICD_ICLAR14_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR14_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR14_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes10_MASK) #define NOC_GICD_GICD_ICLAR14_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR14_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR14_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes11_MASK) #define NOC_GICD_GICD_ICLAR14_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR14_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR14_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes12_MASK) #define NOC_GICD_GICD_ICLAR14_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR14_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR14_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes13_MASK) #define NOC_GICD_GICD_ICLAR14_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR14_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR14_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes14_MASK) #define NOC_GICD_GICD_ICLAR14_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR14_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR14_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR14_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR14_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR15 - GICD_ICLAR15 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR15_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR15_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR15_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes0_MASK) #define NOC_GICD_GICD_ICLAR15_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR15_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR15_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes1_MASK) #define NOC_GICD_GICD_ICLAR15_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR15_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR15_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes2_MASK) #define NOC_GICD_GICD_ICLAR15_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR15_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR15_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes3_MASK) #define NOC_GICD_GICD_ICLAR15_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR15_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR15_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes4_MASK) #define NOC_GICD_GICD_ICLAR15_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR15_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR15_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes5_MASK) #define NOC_GICD_GICD_ICLAR15_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR15_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR15_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes6_MASK) #define NOC_GICD_GICD_ICLAR15_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR15_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR15_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes7_MASK) #define NOC_GICD_GICD_ICLAR15_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR15_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR15_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes8_MASK) #define NOC_GICD_GICD_ICLAR15_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR15_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR15_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes9_MASK) #define NOC_GICD_GICD_ICLAR15_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR15_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR15_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes10_MASK) #define NOC_GICD_GICD_ICLAR15_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR15_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR15_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes11_MASK) #define NOC_GICD_GICD_ICLAR15_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR15_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR15_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes12_MASK) #define NOC_GICD_GICD_ICLAR15_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR15_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR15_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes13_MASK) #define NOC_GICD_GICD_ICLAR15_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR15_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR15_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes14_MASK) #define NOC_GICD_GICD_ICLAR15_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR15_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR15_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR15_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR15_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR16 - GICD_ICLAR16 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR16_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR16_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR16_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes0_MASK) #define NOC_GICD_GICD_ICLAR16_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR16_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR16_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes1_MASK) #define NOC_GICD_GICD_ICLAR16_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR16_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR16_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes2_MASK) #define NOC_GICD_GICD_ICLAR16_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR16_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR16_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes3_MASK) #define NOC_GICD_GICD_ICLAR16_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR16_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR16_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes4_MASK) #define NOC_GICD_GICD_ICLAR16_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR16_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR16_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes5_MASK) #define NOC_GICD_GICD_ICLAR16_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR16_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR16_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes6_MASK) #define NOC_GICD_GICD_ICLAR16_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR16_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR16_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes7_MASK) #define NOC_GICD_GICD_ICLAR16_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR16_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR16_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes8_MASK) #define NOC_GICD_GICD_ICLAR16_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR16_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR16_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes9_MASK) #define NOC_GICD_GICD_ICLAR16_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR16_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR16_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes10_MASK) #define NOC_GICD_GICD_ICLAR16_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR16_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR16_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes11_MASK) #define NOC_GICD_GICD_ICLAR16_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR16_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR16_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes12_MASK) #define NOC_GICD_GICD_ICLAR16_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR16_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR16_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes13_MASK) #define NOC_GICD_GICD_ICLAR16_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR16_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR16_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes14_MASK) #define NOC_GICD_GICD_ICLAR16_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR16_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR16_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR16_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR16_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR17 - GICD_ICLAR17 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR17_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR17_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR17_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes0_MASK) #define NOC_GICD_GICD_ICLAR17_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR17_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR17_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes1_MASK) #define NOC_GICD_GICD_ICLAR17_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR17_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR17_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes2_MASK) #define NOC_GICD_GICD_ICLAR17_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR17_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR17_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes3_MASK) #define NOC_GICD_GICD_ICLAR17_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR17_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR17_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes4_MASK) #define NOC_GICD_GICD_ICLAR17_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR17_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR17_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes5_MASK) #define NOC_GICD_GICD_ICLAR17_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR17_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR17_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes6_MASK) #define NOC_GICD_GICD_ICLAR17_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR17_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR17_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes7_MASK) #define NOC_GICD_GICD_ICLAR17_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR17_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR17_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes8_MASK) #define NOC_GICD_GICD_ICLAR17_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR17_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR17_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes9_MASK) #define NOC_GICD_GICD_ICLAR17_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR17_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR17_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes10_MASK) #define NOC_GICD_GICD_ICLAR17_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR17_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR17_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes11_MASK) #define NOC_GICD_GICD_ICLAR17_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR17_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR17_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes12_MASK) #define NOC_GICD_GICD_ICLAR17_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR17_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR17_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes13_MASK) #define NOC_GICD_GICD_ICLAR17_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR17_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR17_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes14_MASK) #define NOC_GICD_GICD_ICLAR17_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR17_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR17_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR17_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR17_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR18 - GICD_ICLAR18 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR18_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR18_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR18_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes0_MASK) #define NOC_GICD_GICD_ICLAR18_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR18_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR18_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes1_MASK) #define NOC_GICD_GICD_ICLAR18_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR18_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR18_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes2_MASK) #define NOC_GICD_GICD_ICLAR18_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR18_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR18_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes3_MASK) #define NOC_GICD_GICD_ICLAR18_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR18_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR18_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes4_MASK) #define NOC_GICD_GICD_ICLAR18_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR18_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR18_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes5_MASK) #define NOC_GICD_GICD_ICLAR18_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR18_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR18_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes6_MASK) #define NOC_GICD_GICD_ICLAR18_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR18_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR18_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes7_MASK) #define NOC_GICD_GICD_ICLAR18_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR18_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR18_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes8_MASK) #define NOC_GICD_GICD_ICLAR18_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR18_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR18_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes9_MASK) #define NOC_GICD_GICD_ICLAR18_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR18_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR18_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes10_MASK) #define NOC_GICD_GICD_ICLAR18_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR18_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR18_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes11_MASK) #define NOC_GICD_GICD_ICLAR18_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR18_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR18_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes12_MASK) #define NOC_GICD_GICD_ICLAR18_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR18_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR18_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes13_MASK) #define NOC_GICD_GICD_ICLAR18_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR18_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR18_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes14_MASK) #define NOC_GICD_GICD_ICLAR18_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR18_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR18_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR18_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR18_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR19 - GICD_ICLAR19 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR19_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR19_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR19_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes0_MASK) #define NOC_GICD_GICD_ICLAR19_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR19_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR19_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes1_MASK) #define NOC_GICD_GICD_ICLAR19_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR19_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR19_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes2_MASK) #define NOC_GICD_GICD_ICLAR19_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR19_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR19_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes3_MASK) #define NOC_GICD_GICD_ICLAR19_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR19_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR19_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes4_MASK) #define NOC_GICD_GICD_ICLAR19_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR19_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR19_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes5_MASK) #define NOC_GICD_GICD_ICLAR19_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR19_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR19_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes6_MASK) #define NOC_GICD_GICD_ICLAR19_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR19_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR19_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes7_MASK) #define NOC_GICD_GICD_ICLAR19_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR19_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR19_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes8_MASK) #define NOC_GICD_GICD_ICLAR19_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR19_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR19_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes9_MASK) #define NOC_GICD_GICD_ICLAR19_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR19_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR19_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes10_MASK) #define NOC_GICD_GICD_ICLAR19_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR19_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR19_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes11_MASK) #define NOC_GICD_GICD_ICLAR19_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR19_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR19_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes12_MASK) #define NOC_GICD_GICD_ICLAR19_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR19_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR19_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes13_MASK) #define NOC_GICD_GICD_ICLAR19_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR19_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR19_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes14_MASK) #define NOC_GICD_GICD_ICLAR19_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR19_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR19_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR19_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR19_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR20 - GICD_ICLAR20 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR20_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR20_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR20_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes0_MASK) #define NOC_GICD_GICD_ICLAR20_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR20_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR20_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes1_MASK) #define NOC_GICD_GICD_ICLAR20_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR20_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR20_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes2_MASK) #define NOC_GICD_GICD_ICLAR20_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR20_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR20_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes3_MASK) #define NOC_GICD_GICD_ICLAR20_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR20_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR20_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes4_MASK) #define NOC_GICD_GICD_ICLAR20_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR20_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR20_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes5_MASK) #define NOC_GICD_GICD_ICLAR20_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR20_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR20_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes6_MASK) #define NOC_GICD_GICD_ICLAR20_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR20_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR20_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes7_MASK) #define NOC_GICD_GICD_ICLAR20_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR20_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR20_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes8_MASK) #define NOC_GICD_GICD_ICLAR20_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR20_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR20_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes9_MASK) #define NOC_GICD_GICD_ICLAR20_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR20_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR20_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes10_MASK) #define NOC_GICD_GICD_ICLAR20_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR20_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR20_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes11_MASK) #define NOC_GICD_GICD_ICLAR20_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR20_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR20_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes12_MASK) #define NOC_GICD_GICD_ICLAR20_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR20_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR20_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes13_MASK) #define NOC_GICD_GICD_ICLAR20_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR20_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR20_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes14_MASK) #define NOC_GICD_GICD_ICLAR20_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR20_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR20_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR20_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR20_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR21 - GICD_ICLAR21 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR21_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR21_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR21_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes0_MASK) #define NOC_GICD_GICD_ICLAR21_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR21_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR21_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes1_MASK) #define NOC_GICD_GICD_ICLAR21_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR21_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR21_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes2_MASK) #define NOC_GICD_GICD_ICLAR21_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR21_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR21_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes3_MASK) #define NOC_GICD_GICD_ICLAR21_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR21_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR21_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes4_MASK) #define NOC_GICD_GICD_ICLAR21_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR21_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR21_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes5_MASK) #define NOC_GICD_GICD_ICLAR21_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR21_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR21_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes6_MASK) #define NOC_GICD_GICD_ICLAR21_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR21_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR21_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes7_MASK) #define NOC_GICD_GICD_ICLAR21_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR21_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR21_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes8_MASK) #define NOC_GICD_GICD_ICLAR21_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR21_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR21_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes9_MASK) #define NOC_GICD_GICD_ICLAR21_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR21_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR21_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes10_MASK) #define NOC_GICD_GICD_ICLAR21_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR21_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR21_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes11_MASK) #define NOC_GICD_GICD_ICLAR21_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR21_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR21_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes12_MASK) #define NOC_GICD_GICD_ICLAR21_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR21_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR21_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes13_MASK) #define NOC_GICD_GICD_ICLAR21_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR21_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR21_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes14_MASK) #define NOC_GICD_GICD_ICLAR21_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR21_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR21_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR21_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR21_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR22 - GICD_ICLAR22 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR22_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR22_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR22_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes0_MASK) #define NOC_GICD_GICD_ICLAR22_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR22_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR22_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes1_MASK) #define NOC_GICD_GICD_ICLAR22_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR22_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR22_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes2_MASK) #define NOC_GICD_GICD_ICLAR22_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR22_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR22_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes3_MASK) #define NOC_GICD_GICD_ICLAR22_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR22_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR22_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes4_MASK) #define NOC_GICD_GICD_ICLAR22_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR22_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR22_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes5_MASK) #define NOC_GICD_GICD_ICLAR22_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR22_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR22_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes6_MASK) #define NOC_GICD_GICD_ICLAR22_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR22_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR22_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes7_MASK) #define NOC_GICD_GICD_ICLAR22_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR22_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR22_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes8_MASK) #define NOC_GICD_GICD_ICLAR22_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR22_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR22_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes9_MASK) #define NOC_GICD_GICD_ICLAR22_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR22_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR22_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes10_MASK) #define NOC_GICD_GICD_ICLAR22_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR22_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR22_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes11_MASK) #define NOC_GICD_GICD_ICLAR22_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR22_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR22_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes12_MASK) #define NOC_GICD_GICD_ICLAR22_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR22_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR22_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes13_MASK) #define NOC_GICD_GICD_ICLAR22_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR22_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR22_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes14_MASK) #define NOC_GICD_GICD_ICLAR22_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR22_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR22_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR22_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR22_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR23 - GICD_ICLAR23 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR23_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR23_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR23_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes0_MASK) #define NOC_GICD_GICD_ICLAR23_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR23_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR23_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes1_MASK) #define NOC_GICD_GICD_ICLAR23_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR23_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR23_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes2_MASK) #define NOC_GICD_GICD_ICLAR23_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR23_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR23_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes3_MASK) #define NOC_GICD_GICD_ICLAR23_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR23_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR23_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes4_MASK) #define NOC_GICD_GICD_ICLAR23_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR23_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR23_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes5_MASK) #define NOC_GICD_GICD_ICLAR23_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR23_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR23_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes6_MASK) #define NOC_GICD_GICD_ICLAR23_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR23_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR23_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes7_MASK) #define NOC_GICD_GICD_ICLAR23_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR23_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR23_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes8_MASK) #define NOC_GICD_GICD_ICLAR23_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR23_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR23_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes9_MASK) #define NOC_GICD_GICD_ICLAR23_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR23_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR23_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes10_MASK) #define NOC_GICD_GICD_ICLAR23_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR23_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR23_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes11_MASK) #define NOC_GICD_GICD_ICLAR23_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR23_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR23_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes12_MASK) #define NOC_GICD_GICD_ICLAR23_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR23_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR23_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes13_MASK) #define NOC_GICD_GICD_ICLAR23_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR23_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR23_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes14_MASK) #define NOC_GICD_GICD_ICLAR23_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR23_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR23_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR23_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR23_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR24 - GICD_ICLAR24 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR24_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR24_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR24_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes0_MASK) #define NOC_GICD_GICD_ICLAR24_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR24_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR24_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes1_MASK) #define NOC_GICD_GICD_ICLAR24_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR24_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR24_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes2_MASK) #define NOC_GICD_GICD_ICLAR24_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR24_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR24_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes3_MASK) #define NOC_GICD_GICD_ICLAR24_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR24_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR24_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes4_MASK) #define NOC_GICD_GICD_ICLAR24_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR24_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR24_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes5_MASK) #define NOC_GICD_GICD_ICLAR24_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR24_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR24_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes6_MASK) #define NOC_GICD_GICD_ICLAR24_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR24_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR24_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes7_MASK) #define NOC_GICD_GICD_ICLAR24_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR24_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR24_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes8_MASK) #define NOC_GICD_GICD_ICLAR24_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR24_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR24_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes9_MASK) #define NOC_GICD_GICD_ICLAR24_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR24_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR24_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes10_MASK) #define NOC_GICD_GICD_ICLAR24_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR24_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR24_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes11_MASK) #define NOC_GICD_GICD_ICLAR24_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR24_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR24_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes12_MASK) #define NOC_GICD_GICD_ICLAR24_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR24_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR24_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes13_MASK) #define NOC_GICD_GICD_ICLAR24_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR24_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR24_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes14_MASK) #define NOC_GICD_GICD_ICLAR24_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR24_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR24_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR24_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR24_classes15_MASK) /*! @} */ /*! @name GICD_ICLAR25 - GICD_ICLAR25 */ /*! @{ */ #define NOC_GICD_GICD_ICLAR25_classes0_MASK (0x3U) #define NOC_GICD_GICD_ICLAR25_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICD_GICD_ICLAR25_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes0_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes0_MASK) #define NOC_GICD_GICD_ICLAR25_classes1_MASK (0xCU) #define NOC_GICD_GICD_ICLAR25_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICD_GICD_ICLAR25_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes1_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes1_MASK) #define NOC_GICD_GICD_ICLAR25_classes2_MASK (0x30U) #define NOC_GICD_GICD_ICLAR25_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICD_GICD_ICLAR25_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes2_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes2_MASK) #define NOC_GICD_GICD_ICLAR25_classes3_MASK (0xC0U) #define NOC_GICD_GICD_ICLAR25_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICD_GICD_ICLAR25_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes3_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes3_MASK) #define NOC_GICD_GICD_ICLAR25_classes4_MASK (0x300U) #define NOC_GICD_GICD_ICLAR25_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICD_GICD_ICLAR25_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes4_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes4_MASK) #define NOC_GICD_GICD_ICLAR25_classes5_MASK (0xC00U) #define NOC_GICD_GICD_ICLAR25_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICD_GICD_ICLAR25_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes5_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes5_MASK) #define NOC_GICD_GICD_ICLAR25_classes6_MASK (0x3000U) #define NOC_GICD_GICD_ICLAR25_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICD_GICD_ICLAR25_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes6_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes6_MASK) #define NOC_GICD_GICD_ICLAR25_classes7_MASK (0xC000U) #define NOC_GICD_GICD_ICLAR25_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICD_GICD_ICLAR25_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes7_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes7_MASK) #define NOC_GICD_GICD_ICLAR25_classes8_MASK (0x30000U) #define NOC_GICD_GICD_ICLAR25_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICD_GICD_ICLAR25_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes8_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes8_MASK) #define NOC_GICD_GICD_ICLAR25_classes9_MASK (0xC0000U) #define NOC_GICD_GICD_ICLAR25_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICD_GICD_ICLAR25_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes9_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes9_MASK) #define NOC_GICD_GICD_ICLAR25_classes10_MASK (0x300000U) #define NOC_GICD_GICD_ICLAR25_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICD_GICD_ICLAR25_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes10_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes10_MASK) #define NOC_GICD_GICD_ICLAR25_classes11_MASK (0xC00000U) #define NOC_GICD_GICD_ICLAR25_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICD_GICD_ICLAR25_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes11_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes11_MASK) #define NOC_GICD_GICD_ICLAR25_classes12_MASK (0x3000000U) #define NOC_GICD_GICD_ICLAR25_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICD_GICD_ICLAR25_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes12_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes12_MASK) #define NOC_GICD_GICD_ICLAR25_classes13_MASK (0xC000000U) #define NOC_GICD_GICD_ICLAR25_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICD_GICD_ICLAR25_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes13_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes13_MASK) #define NOC_GICD_GICD_ICLAR25_classes14_MASK (0x30000000U) #define NOC_GICD_GICD_ICLAR25_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICD_GICD_ICLAR25_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes14_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes14_MASK) #define NOC_GICD_GICD_ICLAR25_classes15_MASK (0xC0000000U) #define NOC_GICD_GICD_ICLAR25_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICD_GICD_ICLAR25_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICLAR25_classes15_SHIFT)) & NOC_GICD_GICD_ICLAR25_classes15_MASK) /*! @} */ /*! @name GICD_ICERRR1 - GICD_ICERRR1 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR1_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR1_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR1_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status0_SHIFT)) & NOC_GICD_GICD_ICERRR1_status0_MASK) #define NOC_GICD_GICD_ICERRR1_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR1_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR1_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status1_SHIFT)) & NOC_GICD_GICD_ICERRR1_status1_MASK) #define NOC_GICD_GICD_ICERRR1_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR1_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR1_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status2_SHIFT)) & NOC_GICD_GICD_ICERRR1_status2_MASK) #define NOC_GICD_GICD_ICERRR1_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR1_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR1_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status3_SHIFT)) & NOC_GICD_GICD_ICERRR1_status3_MASK) #define NOC_GICD_GICD_ICERRR1_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR1_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR1_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status4_SHIFT)) & NOC_GICD_GICD_ICERRR1_status4_MASK) #define NOC_GICD_GICD_ICERRR1_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR1_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR1_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status5_SHIFT)) & NOC_GICD_GICD_ICERRR1_status5_MASK) #define NOC_GICD_GICD_ICERRR1_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR1_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR1_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status6_SHIFT)) & NOC_GICD_GICD_ICERRR1_status6_MASK) #define NOC_GICD_GICD_ICERRR1_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR1_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR1_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status7_SHIFT)) & NOC_GICD_GICD_ICERRR1_status7_MASK) #define NOC_GICD_GICD_ICERRR1_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR1_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR1_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status8_SHIFT)) & NOC_GICD_GICD_ICERRR1_status8_MASK) #define NOC_GICD_GICD_ICERRR1_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR1_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR1_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status9_SHIFT)) & NOC_GICD_GICD_ICERRR1_status9_MASK) #define NOC_GICD_GICD_ICERRR1_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR1_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR1_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status10_SHIFT)) & NOC_GICD_GICD_ICERRR1_status10_MASK) #define NOC_GICD_GICD_ICERRR1_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR1_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR1_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status11_SHIFT)) & NOC_GICD_GICD_ICERRR1_status11_MASK) #define NOC_GICD_GICD_ICERRR1_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR1_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR1_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status12_SHIFT)) & NOC_GICD_GICD_ICERRR1_status12_MASK) #define NOC_GICD_GICD_ICERRR1_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR1_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR1_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status13_SHIFT)) & NOC_GICD_GICD_ICERRR1_status13_MASK) #define NOC_GICD_GICD_ICERRR1_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR1_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR1_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status14_SHIFT)) & NOC_GICD_GICD_ICERRR1_status14_MASK) #define NOC_GICD_GICD_ICERRR1_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR1_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR1_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status15_SHIFT)) & NOC_GICD_GICD_ICERRR1_status15_MASK) #define NOC_GICD_GICD_ICERRR1_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR1_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR1_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status16_SHIFT)) & NOC_GICD_GICD_ICERRR1_status16_MASK) #define NOC_GICD_GICD_ICERRR1_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR1_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR1_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status17_SHIFT)) & NOC_GICD_GICD_ICERRR1_status17_MASK) #define NOC_GICD_GICD_ICERRR1_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR1_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR1_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status18_SHIFT)) & NOC_GICD_GICD_ICERRR1_status18_MASK) #define NOC_GICD_GICD_ICERRR1_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR1_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR1_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status19_SHIFT)) & NOC_GICD_GICD_ICERRR1_status19_MASK) #define NOC_GICD_GICD_ICERRR1_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR1_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR1_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status20_SHIFT)) & NOC_GICD_GICD_ICERRR1_status20_MASK) #define NOC_GICD_GICD_ICERRR1_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR1_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR1_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status21_SHIFT)) & NOC_GICD_GICD_ICERRR1_status21_MASK) #define NOC_GICD_GICD_ICERRR1_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR1_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR1_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status22_SHIFT)) & NOC_GICD_GICD_ICERRR1_status22_MASK) #define NOC_GICD_GICD_ICERRR1_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR1_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR1_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status23_SHIFT)) & NOC_GICD_GICD_ICERRR1_status23_MASK) #define NOC_GICD_GICD_ICERRR1_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR1_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR1_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status24_SHIFT)) & NOC_GICD_GICD_ICERRR1_status24_MASK) #define NOC_GICD_GICD_ICERRR1_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR1_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR1_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status25_SHIFT)) & NOC_GICD_GICD_ICERRR1_status25_MASK) #define NOC_GICD_GICD_ICERRR1_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR1_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR1_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status26_SHIFT)) & NOC_GICD_GICD_ICERRR1_status26_MASK) #define NOC_GICD_GICD_ICERRR1_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR1_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR1_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status27_SHIFT)) & NOC_GICD_GICD_ICERRR1_status27_MASK) #define NOC_GICD_GICD_ICERRR1_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR1_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR1_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status28_SHIFT)) & NOC_GICD_GICD_ICERRR1_status28_MASK) #define NOC_GICD_GICD_ICERRR1_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR1_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR1_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status29_SHIFT)) & NOC_GICD_GICD_ICERRR1_status29_MASK) #define NOC_GICD_GICD_ICERRR1_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR1_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR1_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status30_SHIFT)) & NOC_GICD_GICD_ICERRR1_status30_MASK) #define NOC_GICD_GICD_ICERRR1_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR1_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR1_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR1_status31_SHIFT)) & NOC_GICD_GICD_ICERRR1_status31_MASK) /*! @} */ /*! @name GICD_ICERRR2 - GICD_ICERRR2 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR2_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR2_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR2_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status0_SHIFT)) & NOC_GICD_GICD_ICERRR2_status0_MASK) #define NOC_GICD_GICD_ICERRR2_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR2_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR2_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status1_SHIFT)) & NOC_GICD_GICD_ICERRR2_status1_MASK) #define NOC_GICD_GICD_ICERRR2_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR2_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR2_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status2_SHIFT)) & NOC_GICD_GICD_ICERRR2_status2_MASK) #define NOC_GICD_GICD_ICERRR2_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR2_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR2_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status3_SHIFT)) & NOC_GICD_GICD_ICERRR2_status3_MASK) #define NOC_GICD_GICD_ICERRR2_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR2_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR2_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status4_SHIFT)) & NOC_GICD_GICD_ICERRR2_status4_MASK) #define NOC_GICD_GICD_ICERRR2_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR2_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR2_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status5_SHIFT)) & NOC_GICD_GICD_ICERRR2_status5_MASK) #define NOC_GICD_GICD_ICERRR2_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR2_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR2_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status6_SHIFT)) & NOC_GICD_GICD_ICERRR2_status6_MASK) #define NOC_GICD_GICD_ICERRR2_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR2_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR2_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status7_SHIFT)) & NOC_GICD_GICD_ICERRR2_status7_MASK) #define NOC_GICD_GICD_ICERRR2_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR2_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR2_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status8_SHIFT)) & NOC_GICD_GICD_ICERRR2_status8_MASK) #define NOC_GICD_GICD_ICERRR2_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR2_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR2_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status9_SHIFT)) & NOC_GICD_GICD_ICERRR2_status9_MASK) #define NOC_GICD_GICD_ICERRR2_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR2_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR2_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status10_SHIFT)) & NOC_GICD_GICD_ICERRR2_status10_MASK) #define NOC_GICD_GICD_ICERRR2_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR2_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR2_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status11_SHIFT)) & NOC_GICD_GICD_ICERRR2_status11_MASK) #define NOC_GICD_GICD_ICERRR2_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR2_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR2_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status12_SHIFT)) & NOC_GICD_GICD_ICERRR2_status12_MASK) #define NOC_GICD_GICD_ICERRR2_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR2_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR2_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status13_SHIFT)) & NOC_GICD_GICD_ICERRR2_status13_MASK) #define NOC_GICD_GICD_ICERRR2_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR2_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR2_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status14_SHIFT)) & NOC_GICD_GICD_ICERRR2_status14_MASK) #define NOC_GICD_GICD_ICERRR2_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR2_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR2_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status15_SHIFT)) & NOC_GICD_GICD_ICERRR2_status15_MASK) #define NOC_GICD_GICD_ICERRR2_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR2_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR2_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status16_SHIFT)) & NOC_GICD_GICD_ICERRR2_status16_MASK) #define NOC_GICD_GICD_ICERRR2_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR2_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR2_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status17_SHIFT)) & NOC_GICD_GICD_ICERRR2_status17_MASK) #define NOC_GICD_GICD_ICERRR2_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR2_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR2_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status18_SHIFT)) & NOC_GICD_GICD_ICERRR2_status18_MASK) #define NOC_GICD_GICD_ICERRR2_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR2_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR2_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status19_SHIFT)) & NOC_GICD_GICD_ICERRR2_status19_MASK) #define NOC_GICD_GICD_ICERRR2_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR2_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR2_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status20_SHIFT)) & NOC_GICD_GICD_ICERRR2_status20_MASK) #define NOC_GICD_GICD_ICERRR2_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR2_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR2_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status21_SHIFT)) & NOC_GICD_GICD_ICERRR2_status21_MASK) #define NOC_GICD_GICD_ICERRR2_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR2_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR2_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status22_SHIFT)) & NOC_GICD_GICD_ICERRR2_status22_MASK) #define NOC_GICD_GICD_ICERRR2_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR2_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR2_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status23_SHIFT)) & NOC_GICD_GICD_ICERRR2_status23_MASK) #define NOC_GICD_GICD_ICERRR2_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR2_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR2_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status24_SHIFT)) & NOC_GICD_GICD_ICERRR2_status24_MASK) #define NOC_GICD_GICD_ICERRR2_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR2_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR2_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status25_SHIFT)) & NOC_GICD_GICD_ICERRR2_status25_MASK) #define NOC_GICD_GICD_ICERRR2_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR2_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR2_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status26_SHIFT)) & NOC_GICD_GICD_ICERRR2_status26_MASK) #define NOC_GICD_GICD_ICERRR2_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR2_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR2_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status27_SHIFT)) & NOC_GICD_GICD_ICERRR2_status27_MASK) #define NOC_GICD_GICD_ICERRR2_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR2_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR2_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status28_SHIFT)) & NOC_GICD_GICD_ICERRR2_status28_MASK) #define NOC_GICD_GICD_ICERRR2_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR2_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR2_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status29_SHIFT)) & NOC_GICD_GICD_ICERRR2_status29_MASK) #define NOC_GICD_GICD_ICERRR2_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR2_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR2_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status30_SHIFT)) & NOC_GICD_GICD_ICERRR2_status30_MASK) #define NOC_GICD_GICD_ICERRR2_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR2_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR2_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR2_status31_SHIFT)) & NOC_GICD_GICD_ICERRR2_status31_MASK) /*! @} */ /*! @name GICD_ICERRR3 - GICD_ICERRR3 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR3_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR3_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR3_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status0_SHIFT)) & NOC_GICD_GICD_ICERRR3_status0_MASK) #define NOC_GICD_GICD_ICERRR3_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR3_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR3_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status1_SHIFT)) & NOC_GICD_GICD_ICERRR3_status1_MASK) #define NOC_GICD_GICD_ICERRR3_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR3_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR3_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status2_SHIFT)) & NOC_GICD_GICD_ICERRR3_status2_MASK) #define NOC_GICD_GICD_ICERRR3_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR3_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR3_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status3_SHIFT)) & NOC_GICD_GICD_ICERRR3_status3_MASK) #define NOC_GICD_GICD_ICERRR3_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR3_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR3_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status4_SHIFT)) & NOC_GICD_GICD_ICERRR3_status4_MASK) #define NOC_GICD_GICD_ICERRR3_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR3_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR3_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status5_SHIFT)) & NOC_GICD_GICD_ICERRR3_status5_MASK) #define NOC_GICD_GICD_ICERRR3_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR3_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR3_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status6_SHIFT)) & NOC_GICD_GICD_ICERRR3_status6_MASK) #define NOC_GICD_GICD_ICERRR3_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR3_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR3_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status7_SHIFT)) & NOC_GICD_GICD_ICERRR3_status7_MASK) #define NOC_GICD_GICD_ICERRR3_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR3_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR3_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status8_SHIFT)) & NOC_GICD_GICD_ICERRR3_status8_MASK) #define NOC_GICD_GICD_ICERRR3_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR3_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR3_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status9_SHIFT)) & NOC_GICD_GICD_ICERRR3_status9_MASK) #define NOC_GICD_GICD_ICERRR3_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR3_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR3_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status10_SHIFT)) & NOC_GICD_GICD_ICERRR3_status10_MASK) #define NOC_GICD_GICD_ICERRR3_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR3_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR3_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status11_SHIFT)) & NOC_GICD_GICD_ICERRR3_status11_MASK) #define NOC_GICD_GICD_ICERRR3_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR3_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR3_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status12_SHIFT)) & NOC_GICD_GICD_ICERRR3_status12_MASK) #define NOC_GICD_GICD_ICERRR3_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR3_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR3_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status13_SHIFT)) & NOC_GICD_GICD_ICERRR3_status13_MASK) #define NOC_GICD_GICD_ICERRR3_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR3_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR3_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status14_SHIFT)) & NOC_GICD_GICD_ICERRR3_status14_MASK) #define NOC_GICD_GICD_ICERRR3_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR3_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR3_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status15_SHIFT)) & NOC_GICD_GICD_ICERRR3_status15_MASK) #define NOC_GICD_GICD_ICERRR3_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR3_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR3_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status16_SHIFT)) & NOC_GICD_GICD_ICERRR3_status16_MASK) #define NOC_GICD_GICD_ICERRR3_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR3_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR3_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status17_SHIFT)) & NOC_GICD_GICD_ICERRR3_status17_MASK) #define NOC_GICD_GICD_ICERRR3_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR3_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR3_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status18_SHIFT)) & NOC_GICD_GICD_ICERRR3_status18_MASK) #define NOC_GICD_GICD_ICERRR3_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR3_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR3_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status19_SHIFT)) & NOC_GICD_GICD_ICERRR3_status19_MASK) #define NOC_GICD_GICD_ICERRR3_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR3_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR3_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status20_SHIFT)) & NOC_GICD_GICD_ICERRR3_status20_MASK) #define NOC_GICD_GICD_ICERRR3_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR3_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR3_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status21_SHIFT)) & NOC_GICD_GICD_ICERRR3_status21_MASK) #define NOC_GICD_GICD_ICERRR3_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR3_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR3_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status22_SHIFT)) & NOC_GICD_GICD_ICERRR3_status22_MASK) #define NOC_GICD_GICD_ICERRR3_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR3_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR3_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status23_SHIFT)) & NOC_GICD_GICD_ICERRR3_status23_MASK) #define NOC_GICD_GICD_ICERRR3_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR3_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR3_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status24_SHIFT)) & NOC_GICD_GICD_ICERRR3_status24_MASK) #define NOC_GICD_GICD_ICERRR3_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR3_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR3_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status25_SHIFT)) & NOC_GICD_GICD_ICERRR3_status25_MASK) #define NOC_GICD_GICD_ICERRR3_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR3_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR3_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status26_SHIFT)) & NOC_GICD_GICD_ICERRR3_status26_MASK) #define NOC_GICD_GICD_ICERRR3_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR3_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR3_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status27_SHIFT)) & NOC_GICD_GICD_ICERRR3_status27_MASK) #define NOC_GICD_GICD_ICERRR3_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR3_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR3_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status28_SHIFT)) & NOC_GICD_GICD_ICERRR3_status28_MASK) #define NOC_GICD_GICD_ICERRR3_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR3_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR3_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status29_SHIFT)) & NOC_GICD_GICD_ICERRR3_status29_MASK) #define NOC_GICD_GICD_ICERRR3_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR3_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR3_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status30_SHIFT)) & NOC_GICD_GICD_ICERRR3_status30_MASK) #define NOC_GICD_GICD_ICERRR3_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR3_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR3_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR3_status31_SHIFT)) & NOC_GICD_GICD_ICERRR3_status31_MASK) /*! @} */ /*! @name GICD_ICERRR4 - GICD_ICERRR4 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR4_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR4_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR4_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status0_SHIFT)) & NOC_GICD_GICD_ICERRR4_status0_MASK) #define NOC_GICD_GICD_ICERRR4_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR4_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR4_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status1_SHIFT)) & NOC_GICD_GICD_ICERRR4_status1_MASK) #define NOC_GICD_GICD_ICERRR4_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR4_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR4_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status2_SHIFT)) & NOC_GICD_GICD_ICERRR4_status2_MASK) #define NOC_GICD_GICD_ICERRR4_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR4_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR4_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status3_SHIFT)) & NOC_GICD_GICD_ICERRR4_status3_MASK) #define NOC_GICD_GICD_ICERRR4_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR4_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR4_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status4_SHIFT)) & NOC_GICD_GICD_ICERRR4_status4_MASK) #define NOC_GICD_GICD_ICERRR4_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR4_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR4_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status5_SHIFT)) & NOC_GICD_GICD_ICERRR4_status5_MASK) #define NOC_GICD_GICD_ICERRR4_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR4_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR4_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status6_SHIFT)) & NOC_GICD_GICD_ICERRR4_status6_MASK) #define NOC_GICD_GICD_ICERRR4_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR4_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR4_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status7_SHIFT)) & NOC_GICD_GICD_ICERRR4_status7_MASK) #define NOC_GICD_GICD_ICERRR4_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR4_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR4_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status8_SHIFT)) & NOC_GICD_GICD_ICERRR4_status8_MASK) #define NOC_GICD_GICD_ICERRR4_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR4_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR4_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status9_SHIFT)) & NOC_GICD_GICD_ICERRR4_status9_MASK) #define NOC_GICD_GICD_ICERRR4_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR4_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR4_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status10_SHIFT)) & NOC_GICD_GICD_ICERRR4_status10_MASK) #define NOC_GICD_GICD_ICERRR4_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR4_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR4_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status11_SHIFT)) & NOC_GICD_GICD_ICERRR4_status11_MASK) #define NOC_GICD_GICD_ICERRR4_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR4_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR4_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status12_SHIFT)) & NOC_GICD_GICD_ICERRR4_status12_MASK) #define NOC_GICD_GICD_ICERRR4_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR4_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR4_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status13_SHIFT)) & NOC_GICD_GICD_ICERRR4_status13_MASK) #define NOC_GICD_GICD_ICERRR4_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR4_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR4_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status14_SHIFT)) & NOC_GICD_GICD_ICERRR4_status14_MASK) #define NOC_GICD_GICD_ICERRR4_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR4_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR4_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status15_SHIFT)) & NOC_GICD_GICD_ICERRR4_status15_MASK) #define NOC_GICD_GICD_ICERRR4_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR4_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR4_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status16_SHIFT)) & NOC_GICD_GICD_ICERRR4_status16_MASK) #define NOC_GICD_GICD_ICERRR4_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR4_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR4_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status17_SHIFT)) & NOC_GICD_GICD_ICERRR4_status17_MASK) #define NOC_GICD_GICD_ICERRR4_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR4_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR4_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status18_SHIFT)) & NOC_GICD_GICD_ICERRR4_status18_MASK) #define NOC_GICD_GICD_ICERRR4_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR4_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR4_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status19_SHIFT)) & NOC_GICD_GICD_ICERRR4_status19_MASK) #define NOC_GICD_GICD_ICERRR4_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR4_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR4_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status20_SHIFT)) & NOC_GICD_GICD_ICERRR4_status20_MASK) #define NOC_GICD_GICD_ICERRR4_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR4_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR4_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status21_SHIFT)) & NOC_GICD_GICD_ICERRR4_status21_MASK) #define NOC_GICD_GICD_ICERRR4_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR4_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR4_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status22_SHIFT)) & NOC_GICD_GICD_ICERRR4_status22_MASK) #define NOC_GICD_GICD_ICERRR4_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR4_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR4_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status23_SHIFT)) & NOC_GICD_GICD_ICERRR4_status23_MASK) #define NOC_GICD_GICD_ICERRR4_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR4_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR4_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status24_SHIFT)) & NOC_GICD_GICD_ICERRR4_status24_MASK) #define NOC_GICD_GICD_ICERRR4_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR4_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR4_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status25_SHIFT)) & NOC_GICD_GICD_ICERRR4_status25_MASK) #define NOC_GICD_GICD_ICERRR4_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR4_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR4_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status26_SHIFT)) & NOC_GICD_GICD_ICERRR4_status26_MASK) #define NOC_GICD_GICD_ICERRR4_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR4_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR4_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status27_SHIFT)) & NOC_GICD_GICD_ICERRR4_status27_MASK) #define NOC_GICD_GICD_ICERRR4_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR4_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR4_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status28_SHIFT)) & NOC_GICD_GICD_ICERRR4_status28_MASK) #define NOC_GICD_GICD_ICERRR4_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR4_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR4_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status29_SHIFT)) & NOC_GICD_GICD_ICERRR4_status29_MASK) #define NOC_GICD_GICD_ICERRR4_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR4_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR4_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status30_SHIFT)) & NOC_GICD_GICD_ICERRR4_status30_MASK) #define NOC_GICD_GICD_ICERRR4_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR4_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR4_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR4_status31_SHIFT)) & NOC_GICD_GICD_ICERRR4_status31_MASK) /*! @} */ /*! @name GICD_ICERRR5 - GICD_ICERRR5 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR5_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR5_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR5_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status0_SHIFT)) & NOC_GICD_GICD_ICERRR5_status0_MASK) #define NOC_GICD_GICD_ICERRR5_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR5_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR5_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status1_SHIFT)) & NOC_GICD_GICD_ICERRR5_status1_MASK) #define NOC_GICD_GICD_ICERRR5_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR5_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR5_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status2_SHIFT)) & NOC_GICD_GICD_ICERRR5_status2_MASK) #define NOC_GICD_GICD_ICERRR5_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR5_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR5_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status3_SHIFT)) & NOC_GICD_GICD_ICERRR5_status3_MASK) #define NOC_GICD_GICD_ICERRR5_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR5_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR5_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status4_SHIFT)) & NOC_GICD_GICD_ICERRR5_status4_MASK) #define NOC_GICD_GICD_ICERRR5_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR5_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR5_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status5_SHIFT)) & NOC_GICD_GICD_ICERRR5_status5_MASK) #define NOC_GICD_GICD_ICERRR5_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR5_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR5_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status6_SHIFT)) & NOC_GICD_GICD_ICERRR5_status6_MASK) #define NOC_GICD_GICD_ICERRR5_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR5_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR5_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status7_SHIFT)) & NOC_GICD_GICD_ICERRR5_status7_MASK) #define NOC_GICD_GICD_ICERRR5_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR5_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR5_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status8_SHIFT)) & NOC_GICD_GICD_ICERRR5_status8_MASK) #define NOC_GICD_GICD_ICERRR5_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR5_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR5_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status9_SHIFT)) & NOC_GICD_GICD_ICERRR5_status9_MASK) #define NOC_GICD_GICD_ICERRR5_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR5_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR5_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status10_SHIFT)) & NOC_GICD_GICD_ICERRR5_status10_MASK) #define NOC_GICD_GICD_ICERRR5_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR5_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR5_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status11_SHIFT)) & NOC_GICD_GICD_ICERRR5_status11_MASK) #define NOC_GICD_GICD_ICERRR5_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR5_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR5_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status12_SHIFT)) & NOC_GICD_GICD_ICERRR5_status12_MASK) #define NOC_GICD_GICD_ICERRR5_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR5_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR5_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status13_SHIFT)) & NOC_GICD_GICD_ICERRR5_status13_MASK) #define NOC_GICD_GICD_ICERRR5_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR5_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR5_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status14_SHIFT)) & NOC_GICD_GICD_ICERRR5_status14_MASK) #define NOC_GICD_GICD_ICERRR5_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR5_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR5_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status15_SHIFT)) & NOC_GICD_GICD_ICERRR5_status15_MASK) #define NOC_GICD_GICD_ICERRR5_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR5_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR5_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status16_SHIFT)) & NOC_GICD_GICD_ICERRR5_status16_MASK) #define NOC_GICD_GICD_ICERRR5_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR5_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR5_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status17_SHIFT)) & NOC_GICD_GICD_ICERRR5_status17_MASK) #define NOC_GICD_GICD_ICERRR5_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR5_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR5_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status18_SHIFT)) & NOC_GICD_GICD_ICERRR5_status18_MASK) #define NOC_GICD_GICD_ICERRR5_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR5_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR5_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status19_SHIFT)) & NOC_GICD_GICD_ICERRR5_status19_MASK) #define NOC_GICD_GICD_ICERRR5_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR5_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR5_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status20_SHIFT)) & NOC_GICD_GICD_ICERRR5_status20_MASK) #define NOC_GICD_GICD_ICERRR5_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR5_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR5_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status21_SHIFT)) & NOC_GICD_GICD_ICERRR5_status21_MASK) #define NOC_GICD_GICD_ICERRR5_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR5_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR5_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status22_SHIFT)) & NOC_GICD_GICD_ICERRR5_status22_MASK) #define NOC_GICD_GICD_ICERRR5_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR5_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR5_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status23_SHIFT)) & NOC_GICD_GICD_ICERRR5_status23_MASK) #define NOC_GICD_GICD_ICERRR5_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR5_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR5_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status24_SHIFT)) & NOC_GICD_GICD_ICERRR5_status24_MASK) #define NOC_GICD_GICD_ICERRR5_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR5_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR5_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status25_SHIFT)) & NOC_GICD_GICD_ICERRR5_status25_MASK) #define NOC_GICD_GICD_ICERRR5_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR5_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR5_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status26_SHIFT)) & NOC_GICD_GICD_ICERRR5_status26_MASK) #define NOC_GICD_GICD_ICERRR5_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR5_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR5_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status27_SHIFT)) & NOC_GICD_GICD_ICERRR5_status27_MASK) #define NOC_GICD_GICD_ICERRR5_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR5_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR5_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status28_SHIFT)) & NOC_GICD_GICD_ICERRR5_status28_MASK) #define NOC_GICD_GICD_ICERRR5_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR5_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR5_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status29_SHIFT)) & NOC_GICD_GICD_ICERRR5_status29_MASK) #define NOC_GICD_GICD_ICERRR5_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR5_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR5_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status30_SHIFT)) & NOC_GICD_GICD_ICERRR5_status30_MASK) #define NOC_GICD_GICD_ICERRR5_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR5_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR5_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR5_status31_SHIFT)) & NOC_GICD_GICD_ICERRR5_status31_MASK) /*! @} */ /*! @name GICD_ICERRR6 - GICD_ICERRR6 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR6_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR6_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR6_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status0_SHIFT)) & NOC_GICD_GICD_ICERRR6_status0_MASK) #define NOC_GICD_GICD_ICERRR6_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR6_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR6_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status1_SHIFT)) & NOC_GICD_GICD_ICERRR6_status1_MASK) #define NOC_GICD_GICD_ICERRR6_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR6_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR6_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status2_SHIFT)) & NOC_GICD_GICD_ICERRR6_status2_MASK) #define NOC_GICD_GICD_ICERRR6_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR6_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR6_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status3_SHIFT)) & NOC_GICD_GICD_ICERRR6_status3_MASK) #define NOC_GICD_GICD_ICERRR6_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR6_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR6_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status4_SHIFT)) & NOC_GICD_GICD_ICERRR6_status4_MASK) #define NOC_GICD_GICD_ICERRR6_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR6_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR6_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status5_SHIFT)) & NOC_GICD_GICD_ICERRR6_status5_MASK) #define NOC_GICD_GICD_ICERRR6_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR6_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR6_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status6_SHIFT)) & NOC_GICD_GICD_ICERRR6_status6_MASK) #define NOC_GICD_GICD_ICERRR6_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR6_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR6_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status7_SHIFT)) & NOC_GICD_GICD_ICERRR6_status7_MASK) #define NOC_GICD_GICD_ICERRR6_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR6_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR6_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status8_SHIFT)) & NOC_GICD_GICD_ICERRR6_status8_MASK) #define NOC_GICD_GICD_ICERRR6_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR6_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR6_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status9_SHIFT)) & NOC_GICD_GICD_ICERRR6_status9_MASK) #define NOC_GICD_GICD_ICERRR6_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR6_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR6_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status10_SHIFT)) & NOC_GICD_GICD_ICERRR6_status10_MASK) #define NOC_GICD_GICD_ICERRR6_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR6_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR6_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status11_SHIFT)) & NOC_GICD_GICD_ICERRR6_status11_MASK) #define NOC_GICD_GICD_ICERRR6_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR6_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR6_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status12_SHIFT)) & NOC_GICD_GICD_ICERRR6_status12_MASK) #define NOC_GICD_GICD_ICERRR6_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR6_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR6_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status13_SHIFT)) & NOC_GICD_GICD_ICERRR6_status13_MASK) #define NOC_GICD_GICD_ICERRR6_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR6_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR6_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status14_SHIFT)) & NOC_GICD_GICD_ICERRR6_status14_MASK) #define NOC_GICD_GICD_ICERRR6_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR6_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR6_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status15_SHIFT)) & NOC_GICD_GICD_ICERRR6_status15_MASK) #define NOC_GICD_GICD_ICERRR6_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR6_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR6_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status16_SHIFT)) & NOC_GICD_GICD_ICERRR6_status16_MASK) #define NOC_GICD_GICD_ICERRR6_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR6_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR6_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status17_SHIFT)) & NOC_GICD_GICD_ICERRR6_status17_MASK) #define NOC_GICD_GICD_ICERRR6_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR6_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR6_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status18_SHIFT)) & NOC_GICD_GICD_ICERRR6_status18_MASK) #define NOC_GICD_GICD_ICERRR6_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR6_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR6_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status19_SHIFT)) & NOC_GICD_GICD_ICERRR6_status19_MASK) #define NOC_GICD_GICD_ICERRR6_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR6_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR6_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status20_SHIFT)) & NOC_GICD_GICD_ICERRR6_status20_MASK) #define NOC_GICD_GICD_ICERRR6_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR6_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR6_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status21_SHIFT)) & NOC_GICD_GICD_ICERRR6_status21_MASK) #define NOC_GICD_GICD_ICERRR6_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR6_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR6_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status22_SHIFT)) & NOC_GICD_GICD_ICERRR6_status22_MASK) #define NOC_GICD_GICD_ICERRR6_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR6_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR6_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status23_SHIFT)) & NOC_GICD_GICD_ICERRR6_status23_MASK) #define NOC_GICD_GICD_ICERRR6_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR6_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR6_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status24_SHIFT)) & NOC_GICD_GICD_ICERRR6_status24_MASK) #define NOC_GICD_GICD_ICERRR6_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR6_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR6_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status25_SHIFT)) & NOC_GICD_GICD_ICERRR6_status25_MASK) #define NOC_GICD_GICD_ICERRR6_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR6_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR6_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status26_SHIFT)) & NOC_GICD_GICD_ICERRR6_status26_MASK) #define NOC_GICD_GICD_ICERRR6_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR6_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR6_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status27_SHIFT)) & NOC_GICD_GICD_ICERRR6_status27_MASK) #define NOC_GICD_GICD_ICERRR6_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR6_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR6_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status28_SHIFT)) & NOC_GICD_GICD_ICERRR6_status28_MASK) #define NOC_GICD_GICD_ICERRR6_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR6_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR6_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status29_SHIFT)) & NOC_GICD_GICD_ICERRR6_status29_MASK) #define NOC_GICD_GICD_ICERRR6_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR6_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR6_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status30_SHIFT)) & NOC_GICD_GICD_ICERRR6_status30_MASK) #define NOC_GICD_GICD_ICERRR6_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR6_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR6_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR6_status31_SHIFT)) & NOC_GICD_GICD_ICERRR6_status31_MASK) /*! @} */ /*! @name GICD_ICERRR7 - GICD_ICERRR7 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR7_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR7_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR7_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status0_SHIFT)) & NOC_GICD_GICD_ICERRR7_status0_MASK) #define NOC_GICD_GICD_ICERRR7_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR7_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR7_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status1_SHIFT)) & NOC_GICD_GICD_ICERRR7_status1_MASK) #define NOC_GICD_GICD_ICERRR7_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR7_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR7_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status2_SHIFT)) & NOC_GICD_GICD_ICERRR7_status2_MASK) #define NOC_GICD_GICD_ICERRR7_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR7_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR7_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status3_SHIFT)) & NOC_GICD_GICD_ICERRR7_status3_MASK) #define NOC_GICD_GICD_ICERRR7_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR7_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR7_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status4_SHIFT)) & NOC_GICD_GICD_ICERRR7_status4_MASK) #define NOC_GICD_GICD_ICERRR7_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR7_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR7_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status5_SHIFT)) & NOC_GICD_GICD_ICERRR7_status5_MASK) #define NOC_GICD_GICD_ICERRR7_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR7_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR7_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status6_SHIFT)) & NOC_GICD_GICD_ICERRR7_status6_MASK) #define NOC_GICD_GICD_ICERRR7_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR7_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR7_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status7_SHIFT)) & NOC_GICD_GICD_ICERRR7_status7_MASK) #define NOC_GICD_GICD_ICERRR7_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR7_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR7_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status8_SHIFT)) & NOC_GICD_GICD_ICERRR7_status8_MASK) #define NOC_GICD_GICD_ICERRR7_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR7_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR7_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status9_SHIFT)) & NOC_GICD_GICD_ICERRR7_status9_MASK) #define NOC_GICD_GICD_ICERRR7_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR7_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR7_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status10_SHIFT)) & NOC_GICD_GICD_ICERRR7_status10_MASK) #define NOC_GICD_GICD_ICERRR7_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR7_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR7_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status11_SHIFT)) & NOC_GICD_GICD_ICERRR7_status11_MASK) #define NOC_GICD_GICD_ICERRR7_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR7_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR7_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status12_SHIFT)) & NOC_GICD_GICD_ICERRR7_status12_MASK) #define NOC_GICD_GICD_ICERRR7_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR7_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR7_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status13_SHIFT)) & NOC_GICD_GICD_ICERRR7_status13_MASK) #define NOC_GICD_GICD_ICERRR7_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR7_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR7_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status14_SHIFT)) & NOC_GICD_GICD_ICERRR7_status14_MASK) #define NOC_GICD_GICD_ICERRR7_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR7_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR7_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status15_SHIFT)) & NOC_GICD_GICD_ICERRR7_status15_MASK) #define NOC_GICD_GICD_ICERRR7_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR7_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR7_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status16_SHIFT)) & NOC_GICD_GICD_ICERRR7_status16_MASK) #define NOC_GICD_GICD_ICERRR7_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR7_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR7_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status17_SHIFT)) & NOC_GICD_GICD_ICERRR7_status17_MASK) #define NOC_GICD_GICD_ICERRR7_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR7_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR7_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status18_SHIFT)) & NOC_GICD_GICD_ICERRR7_status18_MASK) #define NOC_GICD_GICD_ICERRR7_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR7_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR7_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status19_SHIFT)) & NOC_GICD_GICD_ICERRR7_status19_MASK) #define NOC_GICD_GICD_ICERRR7_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR7_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR7_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status20_SHIFT)) & NOC_GICD_GICD_ICERRR7_status20_MASK) #define NOC_GICD_GICD_ICERRR7_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR7_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR7_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status21_SHIFT)) & NOC_GICD_GICD_ICERRR7_status21_MASK) #define NOC_GICD_GICD_ICERRR7_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR7_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR7_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status22_SHIFT)) & NOC_GICD_GICD_ICERRR7_status22_MASK) #define NOC_GICD_GICD_ICERRR7_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR7_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR7_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status23_SHIFT)) & NOC_GICD_GICD_ICERRR7_status23_MASK) #define NOC_GICD_GICD_ICERRR7_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR7_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR7_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status24_SHIFT)) & NOC_GICD_GICD_ICERRR7_status24_MASK) #define NOC_GICD_GICD_ICERRR7_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR7_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR7_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status25_SHIFT)) & NOC_GICD_GICD_ICERRR7_status25_MASK) #define NOC_GICD_GICD_ICERRR7_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR7_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR7_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status26_SHIFT)) & NOC_GICD_GICD_ICERRR7_status26_MASK) #define NOC_GICD_GICD_ICERRR7_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR7_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR7_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status27_SHIFT)) & NOC_GICD_GICD_ICERRR7_status27_MASK) #define NOC_GICD_GICD_ICERRR7_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR7_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR7_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status28_SHIFT)) & NOC_GICD_GICD_ICERRR7_status28_MASK) #define NOC_GICD_GICD_ICERRR7_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR7_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR7_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status29_SHIFT)) & NOC_GICD_GICD_ICERRR7_status29_MASK) #define NOC_GICD_GICD_ICERRR7_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR7_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR7_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status30_SHIFT)) & NOC_GICD_GICD_ICERRR7_status30_MASK) #define NOC_GICD_GICD_ICERRR7_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR7_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR7_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR7_status31_SHIFT)) & NOC_GICD_GICD_ICERRR7_status31_MASK) /*! @} */ /*! @name GICD_ICERRR8 - GICD_ICERRR8 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR8_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR8_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR8_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status0_SHIFT)) & NOC_GICD_GICD_ICERRR8_status0_MASK) #define NOC_GICD_GICD_ICERRR8_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR8_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR8_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status1_SHIFT)) & NOC_GICD_GICD_ICERRR8_status1_MASK) #define NOC_GICD_GICD_ICERRR8_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR8_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR8_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status2_SHIFT)) & NOC_GICD_GICD_ICERRR8_status2_MASK) #define NOC_GICD_GICD_ICERRR8_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR8_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR8_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status3_SHIFT)) & NOC_GICD_GICD_ICERRR8_status3_MASK) #define NOC_GICD_GICD_ICERRR8_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR8_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR8_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status4_SHIFT)) & NOC_GICD_GICD_ICERRR8_status4_MASK) #define NOC_GICD_GICD_ICERRR8_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR8_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR8_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status5_SHIFT)) & NOC_GICD_GICD_ICERRR8_status5_MASK) #define NOC_GICD_GICD_ICERRR8_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR8_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR8_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status6_SHIFT)) & NOC_GICD_GICD_ICERRR8_status6_MASK) #define NOC_GICD_GICD_ICERRR8_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR8_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR8_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status7_SHIFT)) & NOC_GICD_GICD_ICERRR8_status7_MASK) #define NOC_GICD_GICD_ICERRR8_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR8_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR8_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status8_SHIFT)) & NOC_GICD_GICD_ICERRR8_status8_MASK) #define NOC_GICD_GICD_ICERRR8_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR8_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR8_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status9_SHIFT)) & NOC_GICD_GICD_ICERRR8_status9_MASK) #define NOC_GICD_GICD_ICERRR8_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR8_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR8_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status10_SHIFT)) & NOC_GICD_GICD_ICERRR8_status10_MASK) #define NOC_GICD_GICD_ICERRR8_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR8_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR8_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status11_SHIFT)) & NOC_GICD_GICD_ICERRR8_status11_MASK) #define NOC_GICD_GICD_ICERRR8_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR8_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR8_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status12_SHIFT)) & NOC_GICD_GICD_ICERRR8_status12_MASK) #define NOC_GICD_GICD_ICERRR8_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR8_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR8_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status13_SHIFT)) & NOC_GICD_GICD_ICERRR8_status13_MASK) #define NOC_GICD_GICD_ICERRR8_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR8_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR8_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status14_SHIFT)) & NOC_GICD_GICD_ICERRR8_status14_MASK) #define NOC_GICD_GICD_ICERRR8_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR8_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR8_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status15_SHIFT)) & NOC_GICD_GICD_ICERRR8_status15_MASK) #define NOC_GICD_GICD_ICERRR8_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR8_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR8_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status16_SHIFT)) & NOC_GICD_GICD_ICERRR8_status16_MASK) #define NOC_GICD_GICD_ICERRR8_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR8_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR8_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status17_SHIFT)) & NOC_GICD_GICD_ICERRR8_status17_MASK) #define NOC_GICD_GICD_ICERRR8_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR8_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR8_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status18_SHIFT)) & NOC_GICD_GICD_ICERRR8_status18_MASK) #define NOC_GICD_GICD_ICERRR8_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR8_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR8_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status19_SHIFT)) & NOC_GICD_GICD_ICERRR8_status19_MASK) #define NOC_GICD_GICD_ICERRR8_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR8_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR8_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status20_SHIFT)) & NOC_GICD_GICD_ICERRR8_status20_MASK) #define NOC_GICD_GICD_ICERRR8_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR8_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR8_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status21_SHIFT)) & NOC_GICD_GICD_ICERRR8_status21_MASK) #define NOC_GICD_GICD_ICERRR8_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR8_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR8_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status22_SHIFT)) & NOC_GICD_GICD_ICERRR8_status22_MASK) #define NOC_GICD_GICD_ICERRR8_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR8_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR8_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status23_SHIFT)) & NOC_GICD_GICD_ICERRR8_status23_MASK) #define NOC_GICD_GICD_ICERRR8_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR8_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR8_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status24_SHIFT)) & NOC_GICD_GICD_ICERRR8_status24_MASK) #define NOC_GICD_GICD_ICERRR8_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR8_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR8_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status25_SHIFT)) & NOC_GICD_GICD_ICERRR8_status25_MASK) #define NOC_GICD_GICD_ICERRR8_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR8_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR8_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status26_SHIFT)) & NOC_GICD_GICD_ICERRR8_status26_MASK) #define NOC_GICD_GICD_ICERRR8_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR8_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR8_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status27_SHIFT)) & NOC_GICD_GICD_ICERRR8_status27_MASK) #define NOC_GICD_GICD_ICERRR8_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR8_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR8_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status28_SHIFT)) & NOC_GICD_GICD_ICERRR8_status28_MASK) #define NOC_GICD_GICD_ICERRR8_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR8_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR8_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status29_SHIFT)) & NOC_GICD_GICD_ICERRR8_status29_MASK) #define NOC_GICD_GICD_ICERRR8_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR8_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR8_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status30_SHIFT)) & NOC_GICD_GICD_ICERRR8_status30_MASK) #define NOC_GICD_GICD_ICERRR8_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR8_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR8_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR8_status31_SHIFT)) & NOC_GICD_GICD_ICERRR8_status31_MASK) /*! @} */ /*! @name GICD_ICERRR9 - GICD_ICERRR9 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR9_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR9_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR9_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status0_SHIFT)) & NOC_GICD_GICD_ICERRR9_status0_MASK) #define NOC_GICD_GICD_ICERRR9_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR9_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR9_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status1_SHIFT)) & NOC_GICD_GICD_ICERRR9_status1_MASK) #define NOC_GICD_GICD_ICERRR9_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR9_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR9_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status2_SHIFT)) & NOC_GICD_GICD_ICERRR9_status2_MASK) #define NOC_GICD_GICD_ICERRR9_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR9_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR9_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status3_SHIFT)) & NOC_GICD_GICD_ICERRR9_status3_MASK) #define NOC_GICD_GICD_ICERRR9_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR9_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR9_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status4_SHIFT)) & NOC_GICD_GICD_ICERRR9_status4_MASK) #define NOC_GICD_GICD_ICERRR9_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR9_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR9_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status5_SHIFT)) & NOC_GICD_GICD_ICERRR9_status5_MASK) #define NOC_GICD_GICD_ICERRR9_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR9_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR9_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status6_SHIFT)) & NOC_GICD_GICD_ICERRR9_status6_MASK) #define NOC_GICD_GICD_ICERRR9_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR9_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR9_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status7_SHIFT)) & NOC_GICD_GICD_ICERRR9_status7_MASK) #define NOC_GICD_GICD_ICERRR9_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR9_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR9_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status8_SHIFT)) & NOC_GICD_GICD_ICERRR9_status8_MASK) #define NOC_GICD_GICD_ICERRR9_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR9_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR9_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status9_SHIFT)) & NOC_GICD_GICD_ICERRR9_status9_MASK) #define NOC_GICD_GICD_ICERRR9_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR9_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR9_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status10_SHIFT)) & NOC_GICD_GICD_ICERRR9_status10_MASK) #define NOC_GICD_GICD_ICERRR9_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR9_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR9_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status11_SHIFT)) & NOC_GICD_GICD_ICERRR9_status11_MASK) #define NOC_GICD_GICD_ICERRR9_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR9_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR9_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status12_SHIFT)) & NOC_GICD_GICD_ICERRR9_status12_MASK) #define NOC_GICD_GICD_ICERRR9_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR9_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR9_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status13_SHIFT)) & NOC_GICD_GICD_ICERRR9_status13_MASK) #define NOC_GICD_GICD_ICERRR9_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR9_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR9_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status14_SHIFT)) & NOC_GICD_GICD_ICERRR9_status14_MASK) #define NOC_GICD_GICD_ICERRR9_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR9_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR9_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status15_SHIFT)) & NOC_GICD_GICD_ICERRR9_status15_MASK) #define NOC_GICD_GICD_ICERRR9_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR9_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR9_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status16_SHIFT)) & NOC_GICD_GICD_ICERRR9_status16_MASK) #define NOC_GICD_GICD_ICERRR9_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR9_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR9_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status17_SHIFT)) & NOC_GICD_GICD_ICERRR9_status17_MASK) #define NOC_GICD_GICD_ICERRR9_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR9_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR9_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status18_SHIFT)) & NOC_GICD_GICD_ICERRR9_status18_MASK) #define NOC_GICD_GICD_ICERRR9_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR9_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR9_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status19_SHIFT)) & NOC_GICD_GICD_ICERRR9_status19_MASK) #define NOC_GICD_GICD_ICERRR9_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR9_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR9_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status20_SHIFT)) & NOC_GICD_GICD_ICERRR9_status20_MASK) #define NOC_GICD_GICD_ICERRR9_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR9_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR9_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status21_SHIFT)) & NOC_GICD_GICD_ICERRR9_status21_MASK) #define NOC_GICD_GICD_ICERRR9_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR9_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR9_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status22_SHIFT)) & NOC_GICD_GICD_ICERRR9_status22_MASK) #define NOC_GICD_GICD_ICERRR9_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR9_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR9_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status23_SHIFT)) & NOC_GICD_GICD_ICERRR9_status23_MASK) #define NOC_GICD_GICD_ICERRR9_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR9_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR9_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status24_SHIFT)) & NOC_GICD_GICD_ICERRR9_status24_MASK) #define NOC_GICD_GICD_ICERRR9_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR9_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR9_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status25_SHIFT)) & NOC_GICD_GICD_ICERRR9_status25_MASK) #define NOC_GICD_GICD_ICERRR9_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR9_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR9_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status26_SHIFT)) & NOC_GICD_GICD_ICERRR9_status26_MASK) #define NOC_GICD_GICD_ICERRR9_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR9_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR9_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status27_SHIFT)) & NOC_GICD_GICD_ICERRR9_status27_MASK) #define NOC_GICD_GICD_ICERRR9_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR9_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR9_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status28_SHIFT)) & NOC_GICD_GICD_ICERRR9_status28_MASK) #define NOC_GICD_GICD_ICERRR9_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR9_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR9_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status29_SHIFT)) & NOC_GICD_GICD_ICERRR9_status29_MASK) #define NOC_GICD_GICD_ICERRR9_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR9_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR9_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status30_SHIFT)) & NOC_GICD_GICD_ICERRR9_status30_MASK) #define NOC_GICD_GICD_ICERRR9_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR9_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR9_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR9_status31_SHIFT)) & NOC_GICD_GICD_ICERRR9_status31_MASK) /*! @} */ /*! @name GICD_ICERRR10 - GICD_ICERRR10 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR10_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR10_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR10_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status0_SHIFT)) & NOC_GICD_GICD_ICERRR10_status0_MASK) #define NOC_GICD_GICD_ICERRR10_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR10_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR10_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status1_SHIFT)) & NOC_GICD_GICD_ICERRR10_status1_MASK) #define NOC_GICD_GICD_ICERRR10_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR10_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR10_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status2_SHIFT)) & NOC_GICD_GICD_ICERRR10_status2_MASK) #define NOC_GICD_GICD_ICERRR10_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR10_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR10_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status3_SHIFT)) & NOC_GICD_GICD_ICERRR10_status3_MASK) #define NOC_GICD_GICD_ICERRR10_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR10_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR10_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status4_SHIFT)) & NOC_GICD_GICD_ICERRR10_status4_MASK) #define NOC_GICD_GICD_ICERRR10_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR10_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR10_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status5_SHIFT)) & NOC_GICD_GICD_ICERRR10_status5_MASK) #define NOC_GICD_GICD_ICERRR10_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR10_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR10_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status6_SHIFT)) & NOC_GICD_GICD_ICERRR10_status6_MASK) #define NOC_GICD_GICD_ICERRR10_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR10_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR10_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status7_SHIFT)) & NOC_GICD_GICD_ICERRR10_status7_MASK) #define NOC_GICD_GICD_ICERRR10_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR10_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR10_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status8_SHIFT)) & NOC_GICD_GICD_ICERRR10_status8_MASK) #define NOC_GICD_GICD_ICERRR10_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR10_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR10_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status9_SHIFT)) & NOC_GICD_GICD_ICERRR10_status9_MASK) #define NOC_GICD_GICD_ICERRR10_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR10_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR10_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status10_SHIFT)) & NOC_GICD_GICD_ICERRR10_status10_MASK) #define NOC_GICD_GICD_ICERRR10_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR10_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR10_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status11_SHIFT)) & NOC_GICD_GICD_ICERRR10_status11_MASK) #define NOC_GICD_GICD_ICERRR10_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR10_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR10_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status12_SHIFT)) & NOC_GICD_GICD_ICERRR10_status12_MASK) #define NOC_GICD_GICD_ICERRR10_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR10_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR10_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status13_SHIFT)) & NOC_GICD_GICD_ICERRR10_status13_MASK) #define NOC_GICD_GICD_ICERRR10_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR10_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR10_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status14_SHIFT)) & NOC_GICD_GICD_ICERRR10_status14_MASK) #define NOC_GICD_GICD_ICERRR10_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR10_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR10_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status15_SHIFT)) & NOC_GICD_GICD_ICERRR10_status15_MASK) #define NOC_GICD_GICD_ICERRR10_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR10_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR10_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status16_SHIFT)) & NOC_GICD_GICD_ICERRR10_status16_MASK) #define NOC_GICD_GICD_ICERRR10_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR10_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR10_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status17_SHIFT)) & NOC_GICD_GICD_ICERRR10_status17_MASK) #define NOC_GICD_GICD_ICERRR10_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR10_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR10_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status18_SHIFT)) & NOC_GICD_GICD_ICERRR10_status18_MASK) #define NOC_GICD_GICD_ICERRR10_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR10_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR10_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status19_SHIFT)) & NOC_GICD_GICD_ICERRR10_status19_MASK) #define NOC_GICD_GICD_ICERRR10_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR10_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR10_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status20_SHIFT)) & NOC_GICD_GICD_ICERRR10_status20_MASK) #define NOC_GICD_GICD_ICERRR10_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR10_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR10_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status21_SHIFT)) & NOC_GICD_GICD_ICERRR10_status21_MASK) #define NOC_GICD_GICD_ICERRR10_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR10_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR10_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status22_SHIFT)) & NOC_GICD_GICD_ICERRR10_status22_MASK) #define NOC_GICD_GICD_ICERRR10_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR10_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR10_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status23_SHIFT)) & NOC_GICD_GICD_ICERRR10_status23_MASK) #define NOC_GICD_GICD_ICERRR10_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR10_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR10_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status24_SHIFT)) & NOC_GICD_GICD_ICERRR10_status24_MASK) #define NOC_GICD_GICD_ICERRR10_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR10_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR10_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status25_SHIFT)) & NOC_GICD_GICD_ICERRR10_status25_MASK) #define NOC_GICD_GICD_ICERRR10_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR10_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR10_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status26_SHIFT)) & NOC_GICD_GICD_ICERRR10_status26_MASK) #define NOC_GICD_GICD_ICERRR10_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR10_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR10_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status27_SHIFT)) & NOC_GICD_GICD_ICERRR10_status27_MASK) #define NOC_GICD_GICD_ICERRR10_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR10_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR10_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status28_SHIFT)) & NOC_GICD_GICD_ICERRR10_status28_MASK) #define NOC_GICD_GICD_ICERRR10_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR10_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR10_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status29_SHIFT)) & NOC_GICD_GICD_ICERRR10_status29_MASK) #define NOC_GICD_GICD_ICERRR10_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR10_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR10_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status30_SHIFT)) & NOC_GICD_GICD_ICERRR10_status30_MASK) #define NOC_GICD_GICD_ICERRR10_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR10_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR10_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR10_status31_SHIFT)) & NOC_GICD_GICD_ICERRR10_status31_MASK) /*! @} */ /*! @name GICD_ICERRR11 - GICD_ICERRR11 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR11_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR11_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR11_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status0_SHIFT)) & NOC_GICD_GICD_ICERRR11_status0_MASK) #define NOC_GICD_GICD_ICERRR11_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR11_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR11_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status1_SHIFT)) & NOC_GICD_GICD_ICERRR11_status1_MASK) #define NOC_GICD_GICD_ICERRR11_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR11_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR11_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status2_SHIFT)) & NOC_GICD_GICD_ICERRR11_status2_MASK) #define NOC_GICD_GICD_ICERRR11_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR11_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR11_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status3_SHIFT)) & NOC_GICD_GICD_ICERRR11_status3_MASK) #define NOC_GICD_GICD_ICERRR11_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR11_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR11_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status4_SHIFT)) & NOC_GICD_GICD_ICERRR11_status4_MASK) #define NOC_GICD_GICD_ICERRR11_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR11_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR11_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status5_SHIFT)) & NOC_GICD_GICD_ICERRR11_status5_MASK) #define NOC_GICD_GICD_ICERRR11_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR11_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR11_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status6_SHIFT)) & NOC_GICD_GICD_ICERRR11_status6_MASK) #define NOC_GICD_GICD_ICERRR11_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR11_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR11_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status7_SHIFT)) & NOC_GICD_GICD_ICERRR11_status7_MASK) #define NOC_GICD_GICD_ICERRR11_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR11_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR11_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status8_SHIFT)) & NOC_GICD_GICD_ICERRR11_status8_MASK) #define NOC_GICD_GICD_ICERRR11_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR11_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR11_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status9_SHIFT)) & NOC_GICD_GICD_ICERRR11_status9_MASK) #define NOC_GICD_GICD_ICERRR11_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR11_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR11_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status10_SHIFT)) & NOC_GICD_GICD_ICERRR11_status10_MASK) #define NOC_GICD_GICD_ICERRR11_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR11_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR11_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status11_SHIFT)) & NOC_GICD_GICD_ICERRR11_status11_MASK) #define NOC_GICD_GICD_ICERRR11_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR11_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR11_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status12_SHIFT)) & NOC_GICD_GICD_ICERRR11_status12_MASK) #define NOC_GICD_GICD_ICERRR11_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR11_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR11_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status13_SHIFT)) & NOC_GICD_GICD_ICERRR11_status13_MASK) #define NOC_GICD_GICD_ICERRR11_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR11_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR11_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status14_SHIFT)) & NOC_GICD_GICD_ICERRR11_status14_MASK) #define NOC_GICD_GICD_ICERRR11_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR11_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR11_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status15_SHIFT)) & NOC_GICD_GICD_ICERRR11_status15_MASK) #define NOC_GICD_GICD_ICERRR11_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR11_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR11_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status16_SHIFT)) & NOC_GICD_GICD_ICERRR11_status16_MASK) #define NOC_GICD_GICD_ICERRR11_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR11_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR11_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status17_SHIFT)) & NOC_GICD_GICD_ICERRR11_status17_MASK) #define NOC_GICD_GICD_ICERRR11_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR11_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR11_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status18_SHIFT)) & NOC_GICD_GICD_ICERRR11_status18_MASK) #define NOC_GICD_GICD_ICERRR11_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR11_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR11_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status19_SHIFT)) & NOC_GICD_GICD_ICERRR11_status19_MASK) #define NOC_GICD_GICD_ICERRR11_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR11_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR11_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status20_SHIFT)) & NOC_GICD_GICD_ICERRR11_status20_MASK) #define NOC_GICD_GICD_ICERRR11_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR11_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR11_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status21_SHIFT)) & NOC_GICD_GICD_ICERRR11_status21_MASK) #define NOC_GICD_GICD_ICERRR11_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR11_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR11_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status22_SHIFT)) & NOC_GICD_GICD_ICERRR11_status22_MASK) #define NOC_GICD_GICD_ICERRR11_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR11_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR11_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status23_SHIFT)) & NOC_GICD_GICD_ICERRR11_status23_MASK) #define NOC_GICD_GICD_ICERRR11_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR11_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR11_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status24_SHIFT)) & NOC_GICD_GICD_ICERRR11_status24_MASK) #define NOC_GICD_GICD_ICERRR11_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR11_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR11_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status25_SHIFT)) & NOC_GICD_GICD_ICERRR11_status25_MASK) #define NOC_GICD_GICD_ICERRR11_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR11_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR11_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status26_SHIFT)) & NOC_GICD_GICD_ICERRR11_status26_MASK) #define NOC_GICD_GICD_ICERRR11_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR11_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR11_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status27_SHIFT)) & NOC_GICD_GICD_ICERRR11_status27_MASK) #define NOC_GICD_GICD_ICERRR11_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR11_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR11_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status28_SHIFT)) & NOC_GICD_GICD_ICERRR11_status28_MASK) #define NOC_GICD_GICD_ICERRR11_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR11_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR11_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status29_SHIFT)) & NOC_GICD_GICD_ICERRR11_status29_MASK) #define NOC_GICD_GICD_ICERRR11_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR11_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR11_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status30_SHIFT)) & NOC_GICD_GICD_ICERRR11_status30_MASK) #define NOC_GICD_GICD_ICERRR11_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR11_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR11_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR11_status31_SHIFT)) & NOC_GICD_GICD_ICERRR11_status31_MASK) /*! @} */ /*! @name GICD_ICERRR12 - GICD_ICERRR12 */ /*! @{ */ #define NOC_GICD_GICD_ICERRR12_status0_MASK (0x1U) #define NOC_GICD_GICD_ICERRR12_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICERRR12_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status0_SHIFT)) & NOC_GICD_GICD_ICERRR12_status0_MASK) #define NOC_GICD_GICD_ICERRR12_status1_MASK (0x2U) #define NOC_GICD_GICD_ICERRR12_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICERRR12_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status1_SHIFT)) & NOC_GICD_GICD_ICERRR12_status1_MASK) #define NOC_GICD_GICD_ICERRR12_status2_MASK (0x4U) #define NOC_GICD_GICD_ICERRR12_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICERRR12_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status2_SHIFT)) & NOC_GICD_GICD_ICERRR12_status2_MASK) #define NOC_GICD_GICD_ICERRR12_status3_MASK (0x8U) #define NOC_GICD_GICD_ICERRR12_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICERRR12_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status3_SHIFT)) & NOC_GICD_GICD_ICERRR12_status3_MASK) #define NOC_GICD_GICD_ICERRR12_status4_MASK (0x10U) #define NOC_GICD_GICD_ICERRR12_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICERRR12_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status4_SHIFT)) & NOC_GICD_GICD_ICERRR12_status4_MASK) #define NOC_GICD_GICD_ICERRR12_status5_MASK (0x20U) #define NOC_GICD_GICD_ICERRR12_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICERRR12_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status5_SHIFT)) & NOC_GICD_GICD_ICERRR12_status5_MASK) #define NOC_GICD_GICD_ICERRR12_status6_MASK (0x40U) #define NOC_GICD_GICD_ICERRR12_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICERRR12_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status6_SHIFT)) & NOC_GICD_GICD_ICERRR12_status6_MASK) #define NOC_GICD_GICD_ICERRR12_status7_MASK (0x80U) #define NOC_GICD_GICD_ICERRR12_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICERRR12_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status7_SHIFT)) & NOC_GICD_GICD_ICERRR12_status7_MASK) #define NOC_GICD_GICD_ICERRR12_status8_MASK (0x100U) #define NOC_GICD_GICD_ICERRR12_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICERRR12_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status8_SHIFT)) & NOC_GICD_GICD_ICERRR12_status8_MASK) #define NOC_GICD_GICD_ICERRR12_status9_MASK (0x200U) #define NOC_GICD_GICD_ICERRR12_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICERRR12_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status9_SHIFT)) & NOC_GICD_GICD_ICERRR12_status9_MASK) #define NOC_GICD_GICD_ICERRR12_status10_MASK (0x400U) #define NOC_GICD_GICD_ICERRR12_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICERRR12_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status10_SHIFT)) & NOC_GICD_GICD_ICERRR12_status10_MASK) #define NOC_GICD_GICD_ICERRR12_status11_MASK (0x800U) #define NOC_GICD_GICD_ICERRR12_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICERRR12_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status11_SHIFT)) & NOC_GICD_GICD_ICERRR12_status11_MASK) #define NOC_GICD_GICD_ICERRR12_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICERRR12_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICERRR12_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status12_SHIFT)) & NOC_GICD_GICD_ICERRR12_status12_MASK) #define NOC_GICD_GICD_ICERRR12_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICERRR12_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICERRR12_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status13_SHIFT)) & NOC_GICD_GICD_ICERRR12_status13_MASK) #define NOC_GICD_GICD_ICERRR12_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICERRR12_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICERRR12_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status14_SHIFT)) & NOC_GICD_GICD_ICERRR12_status14_MASK) #define NOC_GICD_GICD_ICERRR12_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICERRR12_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICERRR12_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status15_SHIFT)) & NOC_GICD_GICD_ICERRR12_status15_MASK) #define NOC_GICD_GICD_ICERRR12_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICERRR12_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICERRR12_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status16_SHIFT)) & NOC_GICD_GICD_ICERRR12_status16_MASK) #define NOC_GICD_GICD_ICERRR12_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICERRR12_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICERRR12_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status17_SHIFT)) & NOC_GICD_GICD_ICERRR12_status17_MASK) #define NOC_GICD_GICD_ICERRR12_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICERRR12_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICERRR12_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status18_SHIFT)) & NOC_GICD_GICD_ICERRR12_status18_MASK) #define NOC_GICD_GICD_ICERRR12_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICERRR12_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICERRR12_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status19_SHIFT)) & NOC_GICD_GICD_ICERRR12_status19_MASK) #define NOC_GICD_GICD_ICERRR12_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICERRR12_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICERRR12_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status20_SHIFT)) & NOC_GICD_GICD_ICERRR12_status20_MASK) #define NOC_GICD_GICD_ICERRR12_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICERRR12_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICERRR12_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status21_SHIFT)) & NOC_GICD_GICD_ICERRR12_status21_MASK) #define NOC_GICD_GICD_ICERRR12_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICERRR12_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICERRR12_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status22_SHIFT)) & NOC_GICD_GICD_ICERRR12_status22_MASK) #define NOC_GICD_GICD_ICERRR12_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICERRR12_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICERRR12_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status23_SHIFT)) & NOC_GICD_GICD_ICERRR12_status23_MASK) #define NOC_GICD_GICD_ICERRR12_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICERRR12_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICERRR12_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status24_SHIFT)) & NOC_GICD_GICD_ICERRR12_status24_MASK) #define NOC_GICD_GICD_ICERRR12_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICERRR12_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICERRR12_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status25_SHIFT)) & NOC_GICD_GICD_ICERRR12_status25_MASK) #define NOC_GICD_GICD_ICERRR12_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICERRR12_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICERRR12_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status26_SHIFT)) & NOC_GICD_GICD_ICERRR12_status26_MASK) #define NOC_GICD_GICD_ICERRR12_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICERRR12_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICERRR12_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status27_SHIFT)) & NOC_GICD_GICD_ICERRR12_status27_MASK) #define NOC_GICD_GICD_ICERRR12_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICERRR12_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICERRR12_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status28_SHIFT)) & NOC_GICD_GICD_ICERRR12_status28_MASK) #define NOC_GICD_GICD_ICERRR12_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICERRR12_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICERRR12_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status29_SHIFT)) & NOC_GICD_GICD_ICERRR12_status29_MASK) #define NOC_GICD_GICD_ICERRR12_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICERRR12_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICERRR12_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status30_SHIFT)) & NOC_GICD_GICD_ICERRR12_status30_MASK) #define NOC_GICD_GICD_ICERRR12_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICERRR12_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICERRR12_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICERRR12_status31_SHIFT)) & NOC_GICD_GICD_ICERRR12_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR1 - GICD_ICGERRR1 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR1_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR1_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR1_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status0_MASK) #define NOC_GICD_GICD_ICGERRR1_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR1_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR1_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status1_MASK) #define NOC_GICD_GICD_ICGERRR1_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR1_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR1_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status2_MASK) #define NOC_GICD_GICD_ICGERRR1_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR1_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR1_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status3_MASK) #define NOC_GICD_GICD_ICGERRR1_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR1_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR1_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status4_MASK) #define NOC_GICD_GICD_ICGERRR1_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR1_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR1_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status5_MASK) #define NOC_GICD_GICD_ICGERRR1_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR1_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR1_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status6_MASK) #define NOC_GICD_GICD_ICGERRR1_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR1_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR1_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status7_MASK) #define NOC_GICD_GICD_ICGERRR1_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR1_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR1_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status8_MASK) #define NOC_GICD_GICD_ICGERRR1_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR1_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR1_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status9_MASK) #define NOC_GICD_GICD_ICGERRR1_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR1_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR1_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status10_MASK) #define NOC_GICD_GICD_ICGERRR1_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR1_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR1_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status11_MASK) #define NOC_GICD_GICD_ICGERRR1_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR1_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR1_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status12_MASK) #define NOC_GICD_GICD_ICGERRR1_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR1_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR1_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status13_MASK) #define NOC_GICD_GICD_ICGERRR1_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR1_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR1_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status14_MASK) #define NOC_GICD_GICD_ICGERRR1_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR1_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR1_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status15_MASK) #define NOC_GICD_GICD_ICGERRR1_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR1_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR1_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status16_MASK) #define NOC_GICD_GICD_ICGERRR1_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR1_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR1_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status17_MASK) #define NOC_GICD_GICD_ICGERRR1_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR1_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR1_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status18_MASK) #define NOC_GICD_GICD_ICGERRR1_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR1_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR1_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status19_MASK) #define NOC_GICD_GICD_ICGERRR1_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR1_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR1_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status20_MASK) #define NOC_GICD_GICD_ICGERRR1_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR1_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR1_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status21_MASK) #define NOC_GICD_GICD_ICGERRR1_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR1_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR1_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status22_MASK) #define NOC_GICD_GICD_ICGERRR1_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR1_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR1_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status23_MASK) #define NOC_GICD_GICD_ICGERRR1_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR1_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR1_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status24_MASK) #define NOC_GICD_GICD_ICGERRR1_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR1_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR1_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status25_MASK) #define NOC_GICD_GICD_ICGERRR1_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR1_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR1_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status26_MASK) #define NOC_GICD_GICD_ICGERRR1_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR1_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR1_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status27_MASK) #define NOC_GICD_GICD_ICGERRR1_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR1_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR1_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status28_MASK) #define NOC_GICD_GICD_ICGERRR1_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR1_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR1_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status29_MASK) #define NOC_GICD_GICD_ICGERRR1_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR1_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR1_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status30_MASK) #define NOC_GICD_GICD_ICGERRR1_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR1_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR1_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR1_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR1_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR2 - GICD_ICGERRR2 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR2_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR2_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR2_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status0_MASK) #define NOC_GICD_GICD_ICGERRR2_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR2_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR2_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status1_MASK) #define NOC_GICD_GICD_ICGERRR2_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR2_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR2_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status2_MASK) #define NOC_GICD_GICD_ICGERRR2_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR2_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR2_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status3_MASK) #define NOC_GICD_GICD_ICGERRR2_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR2_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR2_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status4_MASK) #define NOC_GICD_GICD_ICGERRR2_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR2_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR2_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status5_MASK) #define NOC_GICD_GICD_ICGERRR2_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR2_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR2_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status6_MASK) #define NOC_GICD_GICD_ICGERRR2_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR2_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR2_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status7_MASK) #define NOC_GICD_GICD_ICGERRR2_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR2_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR2_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status8_MASK) #define NOC_GICD_GICD_ICGERRR2_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR2_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR2_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status9_MASK) #define NOC_GICD_GICD_ICGERRR2_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR2_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR2_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status10_MASK) #define NOC_GICD_GICD_ICGERRR2_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR2_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR2_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status11_MASK) #define NOC_GICD_GICD_ICGERRR2_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR2_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR2_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status12_MASK) #define NOC_GICD_GICD_ICGERRR2_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR2_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR2_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status13_MASK) #define NOC_GICD_GICD_ICGERRR2_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR2_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR2_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status14_MASK) #define NOC_GICD_GICD_ICGERRR2_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR2_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR2_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status15_MASK) #define NOC_GICD_GICD_ICGERRR2_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR2_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR2_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status16_MASK) #define NOC_GICD_GICD_ICGERRR2_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR2_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR2_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status17_MASK) #define NOC_GICD_GICD_ICGERRR2_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR2_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR2_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status18_MASK) #define NOC_GICD_GICD_ICGERRR2_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR2_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR2_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status19_MASK) #define NOC_GICD_GICD_ICGERRR2_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR2_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR2_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status20_MASK) #define NOC_GICD_GICD_ICGERRR2_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR2_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR2_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status21_MASK) #define NOC_GICD_GICD_ICGERRR2_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR2_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR2_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status22_MASK) #define NOC_GICD_GICD_ICGERRR2_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR2_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR2_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status23_MASK) #define NOC_GICD_GICD_ICGERRR2_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR2_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR2_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status24_MASK) #define NOC_GICD_GICD_ICGERRR2_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR2_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR2_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status25_MASK) #define NOC_GICD_GICD_ICGERRR2_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR2_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR2_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status26_MASK) #define NOC_GICD_GICD_ICGERRR2_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR2_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR2_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status27_MASK) #define NOC_GICD_GICD_ICGERRR2_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR2_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR2_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status28_MASK) #define NOC_GICD_GICD_ICGERRR2_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR2_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR2_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status29_MASK) #define NOC_GICD_GICD_ICGERRR2_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR2_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR2_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status30_MASK) #define NOC_GICD_GICD_ICGERRR2_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR2_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR2_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR2_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR2_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR3 - GICD_ICGERRR3 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR3_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR3_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR3_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status0_MASK) #define NOC_GICD_GICD_ICGERRR3_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR3_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR3_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status1_MASK) #define NOC_GICD_GICD_ICGERRR3_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR3_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR3_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status2_MASK) #define NOC_GICD_GICD_ICGERRR3_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR3_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR3_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status3_MASK) #define NOC_GICD_GICD_ICGERRR3_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR3_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR3_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status4_MASK) #define NOC_GICD_GICD_ICGERRR3_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR3_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR3_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status5_MASK) #define NOC_GICD_GICD_ICGERRR3_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR3_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR3_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status6_MASK) #define NOC_GICD_GICD_ICGERRR3_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR3_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR3_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status7_MASK) #define NOC_GICD_GICD_ICGERRR3_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR3_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR3_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status8_MASK) #define NOC_GICD_GICD_ICGERRR3_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR3_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR3_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status9_MASK) #define NOC_GICD_GICD_ICGERRR3_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR3_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR3_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status10_MASK) #define NOC_GICD_GICD_ICGERRR3_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR3_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR3_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status11_MASK) #define NOC_GICD_GICD_ICGERRR3_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR3_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR3_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status12_MASK) #define NOC_GICD_GICD_ICGERRR3_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR3_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR3_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status13_MASK) #define NOC_GICD_GICD_ICGERRR3_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR3_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR3_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status14_MASK) #define NOC_GICD_GICD_ICGERRR3_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR3_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR3_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status15_MASK) #define NOC_GICD_GICD_ICGERRR3_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR3_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR3_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status16_MASK) #define NOC_GICD_GICD_ICGERRR3_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR3_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR3_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status17_MASK) #define NOC_GICD_GICD_ICGERRR3_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR3_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR3_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status18_MASK) #define NOC_GICD_GICD_ICGERRR3_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR3_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR3_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status19_MASK) #define NOC_GICD_GICD_ICGERRR3_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR3_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR3_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status20_MASK) #define NOC_GICD_GICD_ICGERRR3_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR3_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR3_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status21_MASK) #define NOC_GICD_GICD_ICGERRR3_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR3_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR3_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status22_MASK) #define NOC_GICD_GICD_ICGERRR3_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR3_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR3_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status23_MASK) #define NOC_GICD_GICD_ICGERRR3_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR3_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR3_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status24_MASK) #define NOC_GICD_GICD_ICGERRR3_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR3_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR3_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status25_MASK) #define NOC_GICD_GICD_ICGERRR3_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR3_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR3_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status26_MASK) #define NOC_GICD_GICD_ICGERRR3_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR3_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR3_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status27_MASK) #define NOC_GICD_GICD_ICGERRR3_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR3_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR3_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status28_MASK) #define NOC_GICD_GICD_ICGERRR3_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR3_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR3_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status29_MASK) #define NOC_GICD_GICD_ICGERRR3_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR3_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR3_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status30_MASK) #define NOC_GICD_GICD_ICGERRR3_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR3_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR3_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR3_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR3_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR4 - GICD_ICGERRR4 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR4_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR4_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR4_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status0_MASK) #define NOC_GICD_GICD_ICGERRR4_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR4_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR4_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status1_MASK) #define NOC_GICD_GICD_ICGERRR4_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR4_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR4_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status2_MASK) #define NOC_GICD_GICD_ICGERRR4_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR4_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR4_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status3_MASK) #define NOC_GICD_GICD_ICGERRR4_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR4_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR4_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status4_MASK) #define NOC_GICD_GICD_ICGERRR4_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR4_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR4_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status5_MASK) #define NOC_GICD_GICD_ICGERRR4_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR4_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR4_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status6_MASK) #define NOC_GICD_GICD_ICGERRR4_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR4_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR4_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status7_MASK) #define NOC_GICD_GICD_ICGERRR4_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR4_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR4_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status8_MASK) #define NOC_GICD_GICD_ICGERRR4_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR4_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR4_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status9_MASK) #define NOC_GICD_GICD_ICGERRR4_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR4_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR4_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status10_MASK) #define NOC_GICD_GICD_ICGERRR4_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR4_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR4_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status11_MASK) #define NOC_GICD_GICD_ICGERRR4_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR4_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR4_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status12_MASK) #define NOC_GICD_GICD_ICGERRR4_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR4_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR4_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status13_MASK) #define NOC_GICD_GICD_ICGERRR4_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR4_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR4_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status14_MASK) #define NOC_GICD_GICD_ICGERRR4_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR4_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR4_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status15_MASK) #define NOC_GICD_GICD_ICGERRR4_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR4_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR4_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status16_MASK) #define NOC_GICD_GICD_ICGERRR4_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR4_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR4_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status17_MASK) #define NOC_GICD_GICD_ICGERRR4_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR4_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR4_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status18_MASK) #define NOC_GICD_GICD_ICGERRR4_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR4_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR4_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status19_MASK) #define NOC_GICD_GICD_ICGERRR4_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR4_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR4_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status20_MASK) #define NOC_GICD_GICD_ICGERRR4_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR4_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR4_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status21_MASK) #define NOC_GICD_GICD_ICGERRR4_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR4_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR4_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status22_MASK) #define NOC_GICD_GICD_ICGERRR4_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR4_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR4_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status23_MASK) #define NOC_GICD_GICD_ICGERRR4_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR4_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR4_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status24_MASK) #define NOC_GICD_GICD_ICGERRR4_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR4_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR4_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status25_MASK) #define NOC_GICD_GICD_ICGERRR4_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR4_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR4_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status26_MASK) #define NOC_GICD_GICD_ICGERRR4_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR4_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR4_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status27_MASK) #define NOC_GICD_GICD_ICGERRR4_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR4_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR4_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status28_MASK) #define NOC_GICD_GICD_ICGERRR4_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR4_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR4_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status29_MASK) #define NOC_GICD_GICD_ICGERRR4_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR4_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR4_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status30_MASK) #define NOC_GICD_GICD_ICGERRR4_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR4_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR4_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR4_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR4_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR5 - GICD_ICGERRR5 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR5_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR5_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR5_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status0_MASK) #define NOC_GICD_GICD_ICGERRR5_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR5_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR5_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status1_MASK) #define NOC_GICD_GICD_ICGERRR5_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR5_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR5_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status2_MASK) #define NOC_GICD_GICD_ICGERRR5_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR5_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR5_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status3_MASK) #define NOC_GICD_GICD_ICGERRR5_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR5_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR5_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status4_MASK) #define NOC_GICD_GICD_ICGERRR5_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR5_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR5_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status5_MASK) #define NOC_GICD_GICD_ICGERRR5_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR5_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR5_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status6_MASK) #define NOC_GICD_GICD_ICGERRR5_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR5_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR5_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status7_MASK) #define NOC_GICD_GICD_ICGERRR5_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR5_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR5_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status8_MASK) #define NOC_GICD_GICD_ICGERRR5_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR5_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR5_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status9_MASK) #define NOC_GICD_GICD_ICGERRR5_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR5_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR5_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status10_MASK) #define NOC_GICD_GICD_ICGERRR5_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR5_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR5_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status11_MASK) #define NOC_GICD_GICD_ICGERRR5_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR5_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR5_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status12_MASK) #define NOC_GICD_GICD_ICGERRR5_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR5_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR5_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status13_MASK) #define NOC_GICD_GICD_ICGERRR5_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR5_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR5_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status14_MASK) #define NOC_GICD_GICD_ICGERRR5_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR5_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR5_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status15_MASK) #define NOC_GICD_GICD_ICGERRR5_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR5_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR5_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status16_MASK) #define NOC_GICD_GICD_ICGERRR5_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR5_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR5_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status17_MASK) #define NOC_GICD_GICD_ICGERRR5_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR5_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR5_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status18_MASK) #define NOC_GICD_GICD_ICGERRR5_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR5_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR5_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status19_MASK) #define NOC_GICD_GICD_ICGERRR5_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR5_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR5_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status20_MASK) #define NOC_GICD_GICD_ICGERRR5_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR5_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR5_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status21_MASK) #define NOC_GICD_GICD_ICGERRR5_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR5_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR5_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status22_MASK) #define NOC_GICD_GICD_ICGERRR5_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR5_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR5_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status23_MASK) #define NOC_GICD_GICD_ICGERRR5_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR5_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR5_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status24_MASK) #define NOC_GICD_GICD_ICGERRR5_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR5_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR5_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status25_MASK) #define NOC_GICD_GICD_ICGERRR5_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR5_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR5_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status26_MASK) #define NOC_GICD_GICD_ICGERRR5_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR5_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR5_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status27_MASK) #define NOC_GICD_GICD_ICGERRR5_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR5_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR5_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status28_MASK) #define NOC_GICD_GICD_ICGERRR5_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR5_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR5_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status29_MASK) #define NOC_GICD_GICD_ICGERRR5_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR5_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR5_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status30_MASK) #define NOC_GICD_GICD_ICGERRR5_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR5_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR5_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR5_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR5_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR6 - GICD_ICGERRR6 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR6_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR6_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR6_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status0_MASK) #define NOC_GICD_GICD_ICGERRR6_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR6_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR6_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status1_MASK) #define NOC_GICD_GICD_ICGERRR6_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR6_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR6_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status2_MASK) #define NOC_GICD_GICD_ICGERRR6_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR6_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR6_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status3_MASK) #define NOC_GICD_GICD_ICGERRR6_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR6_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR6_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status4_MASK) #define NOC_GICD_GICD_ICGERRR6_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR6_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR6_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status5_MASK) #define NOC_GICD_GICD_ICGERRR6_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR6_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR6_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status6_MASK) #define NOC_GICD_GICD_ICGERRR6_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR6_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR6_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status7_MASK) #define NOC_GICD_GICD_ICGERRR6_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR6_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR6_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status8_MASK) #define NOC_GICD_GICD_ICGERRR6_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR6_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR6_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status9_MASK) #define NOC_GICD_GICD_ICGERRR6_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR6_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR6_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status10_MASK) #define NOC_GICD_GICD_ICGERRR6_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR6_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR6_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status11_MASK) #define NOC_GICD_GICD_ICGERRR6_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR6_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR6_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status12_MASK) #define NOC_GICD_GICD_ICGERRR6_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR6_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR6_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status13_MASK) #define NOC_GICD_GICD_ICGERRR6_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR6_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR6_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status14_MASK) #define NOC_GICD_GICD_ICGERRR6_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR6_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR6_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status15_MASK) #define NOC_GICD_GICD_ICGERRR6_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR6_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR6_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status16_MASK) #define NOC_GICD_GICD_ICGERRR6_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR6_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR6_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status17_MASK) #define NOC_GICD_GICD_ICGERRR6_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR6_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR6_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status18_MASK) #define NOC_GICD_GICD_ICGERRR6_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR6_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR6_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status19_MASK) #define NOC_GICD_GICD_ICGERRR6_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR6_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR6_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status20_MASK) #define NOC_GICD_GICD_ICGERRR6_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR6_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR6_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status21_MASK) #define NOC_GICD_GICD_ICGERRR6_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR6_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR6_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status22_MASK) #define NOC_GICD_GICD_ICGERRR6_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR6_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR6_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status23_MASK) #define NOC_GICD_GICD_ICGERRR6_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR6_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR6_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status24_MASK) #define NOC_GICD_GICD_ICGERRR6_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR6_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR6_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status25_MASK) #define NOC_GICD_GICD_ICGERRR6_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR6_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR6_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status26_MASK) #define NOC_GICD_GICD_ICGERRR6_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR6_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR6_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status27_MASK) #define NOC_GICD_GICD_ICGERRR6_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR6_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR6_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status28_MASK) #define NOC_GICD_GICD_ICGERRR6_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR6_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR6_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status29_MASK) #define NOC_GICD_GICD_ICGERRR6_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR6_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR6_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status30_MASK) #define NOC_GICD_GICD_ICGERRR6_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR6_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR6_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR6_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR6_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR7 - GICD_ICGERRR7 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR7_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR7_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR7_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status0_MASK) #define NOC_GICD_GICD_ICGERRR7_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR7_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR7_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status1_MASK) #define NOC_GICD_GICD_ICGERRR7_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR7_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR7_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status2_MASK) #define NOC_GICD_GICD_ICGERRR7_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR7_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR7_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status3_MASK) #define NOC_GICD_GICD_ICGERRR7_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR7_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR7_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status4_MASK) #define NOC_GICD_GICD_ICGERRR7_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR7_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR7_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status5_MASK) #define NOC_GICD_GICD_ICGERRR7_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR7_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR7_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status6_MASK) #define NOC_GICD_GICD_ICGERRR7_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR7_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR7_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status7_MASK) #define NOC_GICD_GICD_ICGERRR7_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR7_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR7_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status8_MASK) #define NOC_GICD_GICD_ICGERRR7_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR7_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR7_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status9_MASK) #define NOC_GICD_GICD_ICGERRR7_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR7_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR7_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status10_MASK) #define NOC_GICD_GICD_ICGERRR7_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR7_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR7_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status11_MASK) #define NOC_GICD_GICD_ICGERRR7_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR7_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR7_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status12_MASK) #define NOC_GICD_GICD_ICGERRR7_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR7_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR7_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status13_MASK) #define NOC_GICD_GICD_ICGERRR7_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR7_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR7_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status14_MASK) #define NOC_GICD_GICD_ICGERRR7_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR7_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR7_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status15_MASK) #define NOC_GICD_GICD_ICGERRR7_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR7_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR7_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status16_MASK) #define NOC_GICD_GICD_ICGERRR7_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR7_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR7_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status17_MASK) #define NOC_GICD_GICD_ICGERRR7_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR7_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR7_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status18_MASK) #define NOC_GICD_GICD_ICGERRR7_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR7_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR7_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status19_MASK) #define NOC_GICD_GICD_ICGERRR7_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR7_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR7_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status20_MASK) #define NOC_GICD_GICD_ICGERRR7_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR7_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR7_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status21_MASK) #define NOC_GICD_GICD_ICGERRR7_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR7_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR7_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status22_MASK) #define NOC_GICD_GICD_ICGERRR7_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR7_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR7_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status23_MASK) #define NOC_GICD_GICD_ICGERRR7_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR7_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR7_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status24_MASK) #define NOC_GICD_GICD_ICGERRR7_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR7_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR7_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status25_MASK) #define NOC_GICD_GICD_ICGERRR7_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR7_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR7_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status26_MASK) #define NOC_GICD_GICD_ICGERRR7_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR7_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR7_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status27_MASK) #define NOC_GICD_GICD_ICGERRR7_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR7_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR7_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status28_MASK) #define NOC_GICD_GICD_ICGERRR7_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR7_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR7_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status29_MASK) #define NOC_GICD_GICD_ICGERRR7_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR7_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR7_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status30_MASK) #define NOC_GICD_GICD_ICGERRR7_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR7_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR7_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR7_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR7_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR8 - GICD_ICGERRR8 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR8_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR8_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR8_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status0_MASK) #define NOC_GICD_GICD_ICGERRR8_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR8_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR8_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status1_MASK) #define NOC_GICD_GICD_ICGERRR8_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR8_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR8_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status2_MASK) #define NOC_GICD_GICD_ICGERRR8_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR8_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR8_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status3_MASK) #define NOC_GICD_GICD_ICGERRR8_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR8_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR8_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status4_MASK) #define NOC_GICD_GICD_ICGERRR8_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR8_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR8_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status5_MASK) #define NOC_GICD_GICD_ICGERRR8_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR8_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR8_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status6_MASK) #define NOC_GICD_GICD_ICGERRR8_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR8_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR8_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status7_MASK) #define NOC_GICD_GICD_ICGERRR8_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR8_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR8_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status8_MASK) #define NOC_GICD_GICD_ICGERRR8_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR8_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR8_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status9_MASK) #define NOC_GICD_GICD_ICGERRR8_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR8_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR8_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status10_MASK) #define NOC_GICD_GICD_ICGERRR8_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR8_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR8_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status11_MASK) #define NOC_GICD_GICD_ICGERRR8_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR8_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR8_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status12_MASK) #define NOC_GICD_GICD_ICGERRR8_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR8_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR8_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status13_MASK) #define NOC_GICD_GICD_ICGERRR8_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR8_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR8_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status14_MASK) #define NOC_GICD_GICD_ICGERRR8_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR8_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR8_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status15_MASK) #define NOC_GICD_GICD_ICGERRR8_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR8_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR8_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status16_MASK) #define NOC_GICD_GICD_ICGERRR8_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR8_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR8_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status17_MASK) #define NOC_GICD_GICD_ICGERRR8_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR8_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR8_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status18_MASK) #define NOC_GICD_GICD_ICGERRR8_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR8_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR8_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status19_MASK) #define NOC_GICD_GICD_ICGERRR8_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR8_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR8_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status20_MASK) #define NOC_GICD_GICD_ICGERRR8_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR8_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR8_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status21_MASK) #define NOC_GICD_GICD_ICGERRR8_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR8_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR8_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status22_MASK) #define NOC_GICD_GICD_ICGERRR8_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR8_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR8_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status23_MASK) #define NOC_GICD_GICD_ICGERRR8_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR8_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR8_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status24_MASK) #define NOC_GICD_GICD_ICGERRR8_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR8_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR8_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status25_MASK) #define NOC_GICD_GICD_ICGERRR8_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR8_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR8_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status26_MASK) #define NOC_GICD_GICD_ICGERRR8_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR8_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR8_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status27_MASK) #define NOC_GICD_GICD_ICGERRR8_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR8_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR8_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status28_MASK) #define NOC_GICD_GICD_ICGERRR8_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR8_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR8_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status29_MASK) #define NOC_GICD_GICD_ICGERRR8_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR8_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR8_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status30_MASK) #define NOC_GICD_GICD_ICGERRR8_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR8_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR8_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR8_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR8_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR9 - GICD_ICGERRR9 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR9_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR9_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR9_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status0_MASK) #define NOC_GICD_GICD_ICGERRR9_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR9_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR9_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status1_MASK) #define NOC_GICD_GICD_ICGERRR9_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR9_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR9_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status2_MASK) #define NOC_GICD_GICD_ICGERRR9_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR9_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR9_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status3_MASK) #define NOC_GICD_GICD_ICGERRR9_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR9_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR9_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status4_MASK) #define NOC_GICD_GICD_ICGERRR9_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR9_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR9_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status5_MASK) #define NOC_GICD_GICD_ICGERRR9_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR9_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR9_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status6_MASK) #define NOC_GICD_GICD_ICGERRR9_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR9_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR9_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status7_MASK) #define NOC_GICD_GICD_ICGERRR9_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR9_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR9_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status8_MASK) #define NOC_GICD_GICD_ICGERRR9_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR9_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR9_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status9_MASK) #define NOC_GICD_GICD_ICGERRR9_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR9_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR9_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status10_MASK) #define NOC_GICD_GICD_ICGERRR9_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR9_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR9_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status11_MASK) #define NOC_GICD_GICD_ICGERRR9_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR9_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR9_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status12_MASK) #define NOC_GICD_GICD_ICGERRR9_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR9_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR9_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status13_MASK) #define NOC_GICD_GICD_ICGERRR9_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR9_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR9_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status14_MASK) #define NOC_GICD_GICD_ICGERRR9_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR9_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR9_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status15_MASK) #define NOC_GICD_GICD_ICGERRR9_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR9_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR9_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status16_MASK) #define NOC_GICD_GICD_ICGERRR9_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR9_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR9_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status17_MASK) #define NOC_GICD_GICD_ICGERRR9_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR9_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR9_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status18_MASK) #define NOC_GICD_GICD_ICGERRR9_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR9_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR9_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status19_MASK) #define NOC_GICD_GICD_ICGERRR9_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR9_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR9_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status20_MASK) #define NOC_GICD_GICD_ICGERRR9_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR9_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR9_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status21_MASK) #define NOC_GICD_GICD_ICGERRR9_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR9_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR9_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status22_MASK) #define NOC_GICD_GICD_ICGERRR9_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR9_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR9_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status23_MASK) #define NOC_GICD_GICD_ICGERRR9_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR9_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR9_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status24_MASK) #define NOC_GICD_GICD_ICGERRR9_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR9_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR9_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status25_MASK) #define NOC_GICD_GICD_ICGERRR9_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR9_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR9_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status26_MASK) #define NOC_GICD_GICD_ICGERRR9_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR9_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR9_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status27_MASK) #define NOC_GICD_GICD_ICGERRR9_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR9_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR9_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status28_MASK) #define NOC_GICD_GICD_ICGERRR9_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR9_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR9_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status29_MASK) #define NOC_GICD_GICD_ICGERRR9_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR9_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR9_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status30_MASK) #define NOC_GICD_GICD_ICGERRR9_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR9_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR9_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR9_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR9_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR10 - GICD_ICGERRR10 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR10_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR10_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR10_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status0_MASK) #define NOC_GICD_GICD_ICGERRR10_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR10_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR10_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status1_MASK) #define NOC_GICD_GICD_ICGERRR10_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR10_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR10_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status2_MASK) #define NOC_GICD_GICD_ICGERRR10_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR10_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR10_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status3_MASK) #define NOC_GICD_GICD_ICGERRR10_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR10_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR10_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status4_MASK) #define NOC_GICD_GICD_ICGERRR10_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR10_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR10_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status5_MASK) #define NOC_GICD_GICD_ICGERRR10_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR10_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR10_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status6_MASK) #define NOC_GICD_GICD_ICGERRR10_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR10_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR10_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status7_MASK) #define NOC_GICD_GICD_ICGERRR10_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR10_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR10_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status8_MASK) #define NOC_GICD_GICD_ICGERRR10_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR10_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR10_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status9_MASK) #define NOC_GICD_GICD_ICGERRR10_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR10_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR10_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status10_MASK) #define NOC_GICD_GICD_ICGERRR10_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR10_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR10_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status11_MASK) #define NOC_GICD_GICD_ICGERRR10_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR10_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR10_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status12_MASK) #define NOC_GICD_GICD_ICGERRR10_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR10_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR10_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status13_MASK) #define NOC_GICD_GICD_ICGERRR10_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR10_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR10_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status14_MASK) #define NOC_GICD_GICD_ICGERRR10_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR10_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR10_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status15_MASK) #define NOC_GICD_GICD_ICGERRR10_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR10_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR10_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status16_MASK) #define NOC_GICD_GICD_ICGERRR10_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR10_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR10_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status17_MASK) #define NOC_GICD_GICD_ICGERRR10_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR10_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR10_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status18_MASK) #define NOC_GICD_GICD_ICGERRR10_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR10_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR10_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status19_MASK) #define NOC_GICD_GICD_ICGERRR10_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR10_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR10_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status20_MASK) #define NOC_GICD_GICD_ICGERRR10_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR10_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR10_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status21_MASK) #define NOC_GICD_GICD_ICGERRR10_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR10_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR10_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status22_MASK) #define NOC_GICD_GICD_ICGERRR10_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR10_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR10_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status23_MASK) #define NOC_GICD_GICD_ICGERRR10_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR10_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR10_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status24_MASK) #define NOC_GICD_GICD_ICGERRR10_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR10_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR10_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status25_MASK) #define NOC_GICD_GICD_ICGERRR10_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR10_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR10_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status26_MASK) #define NOC_GICD_GICD_ICGERRR10_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR10_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR10_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status27_MASK) #define NOC_GICD_GICD_ICGERRR10_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR10_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR10_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status28_MASK) #define NOC_GICD_GICD_ICGERRR10_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR10_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR10_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status29_MASK) #define NOC_GICD_GICD_ICGERRR10_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR10_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR10_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status30_MASK) #define NOC_GICD_GICD_ICGERRR10_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR10_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR10_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR10_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR10_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR11 - GICD_ICGERRR11 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR11_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR11_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR11_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status0_MASK) #define NOC_GICD_GICD_ICGERRR11_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR11_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR11_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status1_MASK) #define NOC_GICD_GICD_ICGERRR11_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR11_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR11_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status2_MASK) #define NOC_GICD_GICD_ICGERRR11_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR11_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR11_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status3_MASK) #define NOC_GICD_GICD_ICGERRR11_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR11_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR11_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status4_MASK) #define NOC_GICD_GICD_ICGERRR11_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR11_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR11_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status5_MASK) #define NOC_GICD_GICD_ICGERRR11_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR11_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR11_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status6_MASK) #define NOC_GICD_GICD_ICGERRR11_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR11_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR11_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status7_MASK) #define NOC_GICD_GICD_ICGERRR11_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR11_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR11_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status8_MASK) #define NOC_GICD_GICD_ICGERRR11_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR11_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR11_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status9_MASK) #define NOC_GICD_GICD_ICGERRR11_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR11_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR11_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status10_MASK) #define NOC_GICD_GICD_ICGERRR11_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR11_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR11_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status11_MASK) #define NOC_GICD_GICD_ICGERRR11_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR11_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR11_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status12_MASK) #define NOC_GICD_GICD_ICGERRR11_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR11_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR11_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status13_MASK) #define NOC_GICD_GICD_ICGERRR11_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR11_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR11_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status14_MASK) #define NOC_GICD_GICD_ICGERRR11_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR11_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR11_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status15_MASK) #define NOC_GICD_GICD_ICGERRR11_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR11_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR11_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status16_MASK) #define NOC_GICD_GICD_ICGERRR11_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR11_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR11_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status17_MASK) #define NOC_GICD_GICD_ICGERRR11_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR11_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR11_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status18_MASK) #define NOC_GICD_GICD_ICGERRR11_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR11_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR11_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status19_MASK) #define NOC_GICD_GICD_ICGERRR11_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR11_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR11_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status20_MASK) #define NOC_GICD_GICD_ICGERRR11_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR11_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR11_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status21_MASK) #define NOC_GICD_GICD_ICGERRR11_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR11_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR11_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status22_MASK) #define NOC_GICD_GICD_ICGERRR11_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR11_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR11_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status23_MASK) #define NOC_GICD_GICD_ICGERRR11_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR11_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR11_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status24_MASK) #define NOC_GICD_GICD_ICGERRR11_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR11_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR11_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status25_MASK) #define NOC_GICD_GICD_ICGERRR11_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR11_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR11_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status26_MASK) #define NOC_GICD_GICD_ICGERRR11_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR11_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR11_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status27_MASK) #define NOC_GICD_GICD_ICGERRR11_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR11_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR11_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status28_MASK) #define NOC_GICD_GICD_ICGERRR11_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR11_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR11_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status29_MASK) #define NOC_GICD_GICD_ICGERRR11_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR11_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR11_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status30_MASK) #define NOC_GICD_GICD_ICGERRR11_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR11_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR11_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR11_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR11_status31_MASK) /*! @} */ /*! @name GICD_ICGERRR12 - GICD_ICGERRR12 */ /*! @{ */ #define NOC_GICD_GICD_ICGERRR12_status0_MASK (0x1U) #define NOC_GICD_GICD_ICGERRR12_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ICGERRR12_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status0_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status0_MASK) #define NOC_GICD_GICD_ICGERRR12_status1_MASK (0x2U) #define NOC_GICD_GICD_ICGERRR12_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ICGERRR12_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status1_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status1_MASK) #define NOC_GICD_GICD_ICGERRR12_status2_MASK (0x4U) #define NOC_GICD_GICD_ICGERRR12_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ICGERRR12_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status2_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status2_MASK) #define NOC_GICD_GICD_ICGERRR12_status3_MASK (0x8U) #define NOC_GICD_GICD_ICGERRR12_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ICGERRR12_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status3_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status3_MASK) #define NOC_GICD_GICD_ICGERRR12_status4_MASK (0x10U) #define NOC_GICD_GICD_ICGERRR12_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ICGERRR12_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status4_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status4_MASK) #define NOC_GICD_GICD_ICGERRR12_status5_MASK (0x20U) #define NOC_GICD_GICD_ICGERRR12_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ICGERRR12_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status5_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status5_MASK) #define NOC_GICD_GICD_ICGERRR12_status6_MASK (0x40U) #define NOC_GICD_GICD_ICGERRR12_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ICGERRR12_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status6_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status6_MASK) #define NOC_GICD_GICD_ICGERRR12_status7_MASK (0x80U) #define NOC_GICD_GICD_ICGERRR12_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ICGERRR12_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status7_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status7_MASK) #define NOC_GICD_GICD_ICGERRR12_status8_MASK (0x100U) #define NOC_GICD_GICD_ICGERRR12_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ICGERRR12_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status8_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status8_MASK) #define NOC_GICD_GICD_ICGERRR12_status9_MASK (0x200U) #define NOC_GICD_GICD_ICGERRR12_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ICGERRR12_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status9_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status9_MASK) #define NOC_GICD_GICD_ICGERRR12_status10_MASK (0x400U) #define NOC_GICD_GICD_ICGERRR12_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ICGERRR12_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status10_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status10_MASK) #define NOC_GICD_GICD_ICGERRR12_status11_MASK (0x800U) #define NOC_GICD_GICD_ICGERRR12_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ICGERRR12_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status11_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status11_MASK) #define NOC_GICD_GICD_ICGERRR12_status12_MASK (0x1000U) #define NOC_GICD_GICD_ICGERRR12_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ICGERRR12_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status12_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status12_MASK) #define NOC_GICD_GICD_ICGERRR12_status13_MASK (0x2000U) #define NOC_GICD_GICD_ICGERRR12_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ICGERRR12_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status13_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status13_MASK) #define NOC_GICD_GICD_ICGERRR12_status14_MASK (0x4000U) #define NOC_GICD_GICD_ICGERRR12_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ICGERRR12_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status14_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status14_MASK) #define NOC_GICD_GICD_ICGERRR12_status15_MASK (0x8000U) #define NOC_GICD_GICD_ICGERRR12_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ICGERRR12_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status15_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status15_MASK) #define NOC_GICD_GICD_ICGERRR12_status16_MASK (0x10000U) #define NOC_GICD_GICD_ICGERRR12_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ICGERRR12_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status16_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status16_MASK) #define NOC_GICD_GICD_ICGERRR12_status17_MASK (0x20000U) #define NOC_GICD_GICD_ICGERRR12_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ICGERRR12_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status17_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status17_MASK) #define NOC_GICD_GICD_ICGERRR12_status18_MASK (0x40000U) #define NOC_GICD_GICD_ICGERRR12_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ICGERRR12_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status18_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status18_MASK) #define NOC_GICD_GICD_ICGERRR12_status19_MASK (0x80000U) #define NOC_GICD_GICD_ICGERRR12_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ICGERRR12_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status19_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status19_MASK) #define NOC_GICD_GICD_ICGERRR12_status20_MASK (0x100000U) #define NOC_GICD_GICD_ICGERRR12_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ICGERRR12_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status20_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status20_MASK) #define NOC_GICD_GICD_ICGERRR12_status21_MASK (0x200000U) #define NOC_GICD_GICD_ICGERRR12_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ICGERRR12_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status21_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status21_MASK) #define NOC_GICD_GICD_ICGERRR12_status22_MASK (0x400000U) #define NOC_GICD_GICD_ICGERRR12_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ICGERRR12_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status22_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status22_MASK) #define NOC_GICD_GICD_ICGERRR12_status23_MASK (0x800000U) #define NOC_GICD_GICD_ICGERRR12_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ICGERRR12_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status23_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status23_MASK) #define NOC_GICD_GICD_ICGERRR12_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ICGERRR12_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ICGERRR12_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status24_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status24_MASK) #define NOC_GICD_GICD_ICGERRR12_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ICGERRR12_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ICGERRR12_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status25_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status25_MASK) #define NOC_GICD_GICD_ICGERRR12_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ICGERRR12_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ICGERRR12_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status26_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status26_MASK) #define NOC_GICD_GICD_ICGERRR12_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ICGERRR12_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ICGERRR12_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status27_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status27_MASK) #define NOC_GICD_GICD_ICGERRR12_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ICGERRR12_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ICGERRR12_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status28_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status28_MASK) #define NOC_GICD_GICD_ICGERRR12_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ICGERRR12_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ICGERRR12_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status29_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status29_MASK) #define NOC_GICD_GICD_ICGERRR12_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ICGERRR12_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ICGERRR12_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status30_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status30_MASK) #define NOC_GICD_GICD_ICGERRR12_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ICGERRR12_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ICGERRR12_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ICGERRR12_status31_SHIFT)) & NOC_GICD_GICD_ICGERRR12_status31_MASK) /*! @} */ /*! @name GICD_ISERRR1 - GICD_ISERRR1 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR1_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR1_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR1_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status0_SHIFT)) & NOC_GICD_GICD_ISERRR1_status0_MASK) #define NOC_GICD_GICD_ISERRR1_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR1_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR1_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status1_SHIFT)) & NOC_GICD_GICD_ISERRR1_status1_MASK) #define NOC_GICD_GICD_ISERRR1_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR1_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR1_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status2_SHIFT)) & NOC_GICD_GICD_ISERRR1_status2_MASK) #define NOC_GICD_GICD_ISERRR1_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR1_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR1_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status3_SHIFT)) & NOC_GICD_GICD_ISERRR1_status3_MASK) #define NOC_GICD_GICD_ISERRR1_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR1_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR1_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status4_SHIFT)) & NOC_GICD_GICD_ISERRR1_status4_MASK) #define NOC_GICD_GICD_ISERRR1_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR1_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR1_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status5_SHIFT)) & NOC_GICD_GICD_ISERRR1_status5_MASK) #define NOC_GICD_GICD_ISERRR1_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR1_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR1_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status6_SHIFT)) & NOC_GICD_GICD_ISERRR1_status6_MASK) #define NOC_GICD_GICD_ISERRR1_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR1_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR1_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status7_SHIFT)) & NOC_GICD_GICD_ISERRR1_status7_MASK) #define NOC_GICD_GICD_ISERRR1_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR1_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR1_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status8_SHIFT)) & NOC_GICD_GICD_ISERRR1_status8_MASK) #define NOC_GICD_GICD_ISERRR1_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR1_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR1_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status9_SHIFT)) & NOC_GICD_GICD_ISERRR1_status9_MASK) #define NOC_GICD_GICD_ISERRR1_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR1_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR1_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status10_SHIFT)) & NOC_GICD_GICD_ISERRR1_status10_MASK) #define NOC_GICD_GICD_ISERRR1_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR1_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR1_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status11_SHIFT)) & NOC_GICD_GICD_ISERRR1_status11_MASK) #define NOC_GICD_GICD_ISERRR1_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR1_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR1_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status12_SHIFT)) & NOC_GICD_GICD_ISERRR1_status12_MASK) #define NOC_GICD_GICD_ISERRR1_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR1_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR1_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status13_SHIFT)) & NOC_GICD_GICD_ISERRR1_status13_MASK) #define NOC_GICD_GICD_ISERRR1_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR1_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR1_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status14_SHIFT)) & NOC_GICD_GICD_ISERRR1_status14_MASK) #define NOC_GICD_GICD_ISERRR1_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR1_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR1_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status15_SHIFT)) & NOC_GICD_GICD_ISERRR1_status15_MASK) #define NOC_GICD_GICD_ISERRR1_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR1_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR1_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status16_SHIFT)) & NOC_GICD_GICD_ISERRR1_status16_MASK) #define NOC_GICD_GICD_ISERRR1_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR1_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR1_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status17_SHIFT)) & NOC_GICD_GICD_ISERRR1_status17_MASK) #define NOC_GICD_GICD_ISERRR1_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR1_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR1_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status18_SHIFT)) & NOC_GICD_GICD_ISERRR1_status18_MASK) #define NOC_GICD_GICD_ISERRR1_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR1_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR1_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status19_SHIFT)) & NOC_GICD_GICD_ISERRR1_status19_MASK) #define NOC_GICD_GICD_ISERRR1_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR1_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR1_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status20_SHIFT)) & NOC_GICD_GICD_ISERRR1_status20_MASK) #define NOC_GICD_GICD_ISERRR1_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR1_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR1_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status21_SHIFT)) & NOC_GICD_GICD_ISERRR1_status21_MASK) #define NOC_GICD_GICD_ISERRR1_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR1_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR1_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status22_SHIFT)) & NOC_GICD_GICD_ISERRR1_status22_MASK) #define NOC_GICD_GICD_ISERRR1_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR1_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR1_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status23_SHIFT)) & NOC_GICD_GICD_ISERRR1_status23_MASK) #define NOC_GICD_GICD_ISERRR1_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR1_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR1_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status24_SHIFT)) & NOC_GICD_GICD_ISERRR1_status24_MASK) #define NOC_GICD_GICD_ISERRR1_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR1_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR1_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status25_SHIFT)) & NOC_GICD_GICD_ISERRR1_status25_MASK) #define NOC_GICD_GICD_ISERRR1_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR1_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR1_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status26_SHIFT)) & NOC_GICD_GICD_ISERRR1_status26_MASK) #define NOC_GICD_GICD_ISERRR1_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR1_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR1_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status27_SHIFT)) & NOC_GICD_GICD_ISERRR1_status27_MASK) #define NOC_GICD_GICD_ISERRR1_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR1_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR1_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status28_SHIFT)) & NOC_GICD_GICD_ISERRR1_status28_MASK) #define NOC_GICD_GICD_ISERRR1_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR1_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR1_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status29_SHIFT)) & NOC_GICD_GICD_ISERRR1_status29_MASK) #define NOC_GICD_GICD_ISERRR1_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR1_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR1_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status30_SHIFT)) & NOC_GICD_GICD_ISERRR1_status30_MASK) #define NOC_GICD_GICD_ISERRR1_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR1_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR1_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR1_status31_SHIFT)) & NOC_GICD_GICD_ISERRR1_status31_MASK) /*! @} */ /*! @name GICD_ISERRR2 - GICD_ISERRR2 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR2_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR2_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR2_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status0_SHIFT)) & NOC_GICD_GICD_ISERRR2_status0_MASK) #define NOC_GICD_GICD_ISERRR2_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR2_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR2_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status1_SHIFT)) & NOC_GICD_GICD_ISERRR2_status1_MASK) #define NOC_GICD_GICD_ISERRR2_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR2_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR2_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status2_SHIFT)) & NOC_GICD_GICD_ISERRR2_status2_MASK) #define NOC_GICD_GICD_ISERRR2_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR2_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR2_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status3_SHIFT)) & NOC_GICD_GICD_ISERRR2_status3_MASK) #define NOC_GICD_GICD_ISERRR2_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR2_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR2_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status4_SHIFT)) & NOC_GICD_GICD_ISERRR2_status4_MASK) #define NOC_GICD_GICD_ISERRR2_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR2_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR2_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status5_SHIFT)) & NOC_GICD_GICD_ISERRR2_status5_MASK) #define NOC_GICD_GICD_ISERRR2_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR2_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR2_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status6_SHIFT)) & NOC_GICD_GICD_ISERRR2_status6_MASK) #define NOC_GICD_GICD_ISERRR2_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR2_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR2_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status7_SHIFT)) & NOC_GICD_GICD_ISERRR2_status7_MASK) #define NOC_GICD_GICD_ISERRR2_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR2_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR2_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status8_SHIFT)) & NOC_GICD_GICD_ISERRR2_status8_MASK) #define NOC_GICD_GICD_ISERRR2_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR2_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR2_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status9_SHIFT)) & NOC_GICD_GICD_ISERRR2_status9_MASK) #define NOC_GICD_GICD_ISERRR2_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR2_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR2_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status10_SHIFT)) & NOC_GICD_GICD_ISERRR2_status10_MASK) #define NOC_GICD_GICD_ISERRR2_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR2_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR2_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status11_SHIFT)) & NOC_GICD_GICD_ISERRR2_status11_MASK) #define NOC_GICD_GICD_ISERRR2_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR2_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR2_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status12_SHIFT)) & NOC_GICD_GICD_ISERRR2_status12_MASK) #define NOC_GICD_GICD_ISERRR2_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR2_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR2_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status13_SHIFT)) & NOC_GICD_GICD_ISERRR2_status13_MASK) #define NOC_GICD_GICD_ISERRR2_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR2_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR2_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status14_SHIFT)) & NOC_GICD_GICD_ISERRR2_status14_MASK) #define NOC_GICD_GICD_ISERRR2_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR2_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR2_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status15_SHIFT)) & NOC_GICD_GICD_ISERRR2_status15_MASK) #define NOC_GICD_GICD_ISERRR2_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR2_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR2_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status16_SHIFT)) & NOC_GICD_GICD_ISERRR2_status16_MASK) #define NOC_GICD_GICD_ISERRR2_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR2_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR2_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status17_SHIFT)) & NOC_GICD_GICD_ISERRR2_status17_MASK) #define NOC_GICD_GICD_ISERRR2_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR2_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR2_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status18_SHIFT)) & NOC_GICD_GICD_ISERRR2_status18_MASK) #define NOC_GICD_GICD_ISERRR2_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR2_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR2_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status19_SHIFT)) & NOC_GICD_GICD_ISERRR2_status19_MASK) #define NOC_GICD_GICD_ISERRR2_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR2_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR2_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status20_SHIFT)) & NOC_GICD_GICD_ISERRR2_status20_MASK) #define NOC_GICD_GICD_ISERRR2_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR2_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR2_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status21_SHIFT)) & NOC_GICD_GICD_ISERRR2_status21_MASK) #define NOC_GICD_GICD_ISERRR2_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR2_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR2_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status22_SHIFT)) & NOC_GICD_GICD_ISERRR2_status22_MASK) #define NOC_GICD_GICD_ISERRR2_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR2_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR2_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status23_SHIFT)) & NOC_GICD_GICD_ISERRR2_status23_MASK) #define NOC_GICD_GICD_ISERRR2_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR2_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR2_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status24_SHIFT)) & NOC_GICD_GICD_ISERRR2_status24_MASK) #define NOC_GICD_GICD_ISERRR2_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR2_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR2_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status25_SHIFT)) & NOC_GICD_GICD_ISERRR2_status25_MASK) #define NOC_GICD_GICD_ISERRR2_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR2_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR2_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status26_SHIFT)) & NOC_GICD_GICD_ISERRR2_status26_MASK) #define NOC_GICD_GICD_ISERRR2_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR2_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR2_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status27_SHIFT)) & NOC_GICD_GICD_ISERRR2_status27_MASK) #define NOC_GICD_GICD_ISERRR2_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR2_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR2_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status28_SHIFT)) & NOC_GICD_GICD_ISERRR2_status28_MASK) #define NOC_GICD_GICD_ISERRR2_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR2_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR2_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status29_SHIFT)) & NOC_GICD_GICD_ISERRR2_status29_MASK) #define NOC_GICD_GICD_ISERRR2_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR2_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR2_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status30_SHIFT)) & NOC_GICD_GICD_ISERRR2_status30_MASK) #define NOC_GICD_GICD_ISERRR2_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR2_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR2_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR2_status31_SHIFT)) & NOC_GICD_GICD_ISERRR2_status31_MASK) /*! @} */ /*! @name GICD_ISERRR3 - GICD_ISERRR3 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR3_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR3_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR3_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status0_SHIFT)) & NOC_GICD_GICD_ISERRR3_status0_MASK) #define NOC_GICD_GICD_ISERRR3_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR3_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR3_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status1_SHIFT)) & NOC_GICD_GICD_ISERRR3_status1_MASK) #define NOC_GICD_GICD_ISERRR3_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR3_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR3_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status2_SHIFT)) & NOC_GICD_GICD_ISERRR3_status2_MASK) #define NOC_GICD_GICD_ISERRR3_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR3_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR3_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status3_SHIFT)) & NOC_GICD_GICD_ISERRR3_status3_MASK) #define NOC_GICD_GICD_ISERRR3_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR3_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR3_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status4_SHIFT)) & NOC_GICD_GICD_ISERRR3_status4_MASK) #define NOC_GICD_GICD_ISERRR3_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR3_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR3_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status5_SHIFT)) & NOC_GICD_GICD_ISERRR3_status5_MASK) #define NOC_GICD_GICD_ISERRR3_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR3_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR3_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status6_SHIFT)) & NOC_GICD_GICD_ISERRR3_status6_MASK) #define NOC_GICD_GICD_ISERRR3_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR3_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR3_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status7_SHIFT)) & NOC_GICD_GICD_ISERRR3_status7_MASK) #define NOC_GICD_GICD_ISERRR3_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR3_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR3_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status8_SHIFT)) & NOC_GICD_GICD_ISERRR3_status8_MASK) #define NOC_GICD_GICD_ISERRR3_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR3_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR3_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status9_SHIFT)) & NOC_GICD_GICD_ISERRR3_status9_MASK) #define NOC_GICD_GICD_ISERRR3_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR3_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR3_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status10_SHIFT)) & NOC_GICD_GICD_ISERRR3_status10_MASK) #define NOC_GICD_GICD_ISERRR3_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR3_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR3_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status11_SHIFT)) & NOC_GICD_GICD_ISERRR3_status11_MASK) #define NOC_GICD_GICD_ISERRR3_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR3_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR3_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status12_SHIFT)) & NOC_GICD_GICD_ISERRR3_status12_MASK) #define NOC_GICD_GICD_ISERRR3_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR3_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR3_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status13_SHIFT)) & NOC_GICD_GICD_ISERRR3_status13_MASK) #define NOC_GICD_GICD_ISERRR3_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR3_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR3_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status14_SHIFT)) & NOC_GICD_GICD_ISERRR3_status14_MASK) #define NOC_GICD_GICD_ISERRR3_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR3_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR3_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status15_SHIFT)) & NOC_GICD_GICD_ISERRR3_status15_MASK) #define NOC_GICD_GICD_ISERRR3_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR3_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR3_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status16_SHIFT)) & NOC_GICD_GICD_ISERRR3_status16_MASK) #define NOC_GICD_GICD_ISERRR3_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR3_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR3_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status17_SHIFT)) & NOC_GICD_GICD_ISERRR3_status17_MASK) #define NOC_GICD_GICD_ISERRR3_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR3_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR3_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status18_SHIFT)) & NOC_GICD_GICD_ISERRR3_status18_MASK) #define NOC_GICD_GICD_ISERRR3_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR3_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR3_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status19_SHIFT)) & NOC_GICD_GICD_ISERRR3_status19_MASK) #define NOC_GICD_GICD_ISERRR3_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR3_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR3_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status20_SHIFT)) & NOC_GICD_GICD_ISERRR3_status20_MASK) #define NOC_GICD_GICD_ISERRR3_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR3_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR3_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status21_SHIFT)) & NOC_GICD_GICD_ISERRR3_status21_MASK) #define NOC_GICD_GICD_ISERRR3_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR3_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR3_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status22_SHIFT)) & NOC_GICD_GICD_ISERRR3_status22_MASK) #define NOC_GICD_GICD_ISERRR3_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR3_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR3_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status23_SHIFT)) & NOC_GICD_GICD_ISERRR3_status23_MASK) #define NOC_GICD_GICD_ISERRR3_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR3_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR3_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status24_SHIFT)) & NOC_GICD_GICD_ISERRR3_status24_MASK) #define NOC_GICD_GICD_ISERRR3_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR3_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR3_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status25_SHIFT)) & NOC_GICD_GICD_ISERRR3_status25_MASK) #define NOC_GICD_GICD_ISERRR3_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR3_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR3_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status26_SHIFT)) & NOC_GICD_GICD_ISERRR3_status26_MASK) #define NOC_GICD_GICD_ISERRR3_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR3_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR3_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status27_SHIFT)) & NOC_GICD_GICD_ISERRR3_status27_MASK) #define NOC_GICD_GICD_ISERRR3_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR3_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR3_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status28_SHIFT)) & NOC_GICD_GICD_ISERRR3_status28_MASK) #define NOC_GICD_GICD_ISERRR3_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR3_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR3_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status29_SHIFT)) & NOC_GICD_GICD_ISERRR3_status29_MASK) #define NOC_GICD_GICD_ISERRR3_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR3_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR3_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status30_SHIFT)) & NOC_GICD_GICD_ISERRR3_status30_MASK) #define NOC_GICD_GICD_ISERRR3_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR3_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR3_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR3_status31_SHIFT)) & NOC_GICD_GICD_ISERRR3_status31_MASK) /*! @} */ /*! @name GICD_ISERRR4 - GICD_ISERRR4 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR4_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR4_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR4_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status0_SHIFT)) & NOC_GICD_GICD_ISERRR4_status0_MASK) #define NOC_GICD_GICD_ISERRR4_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR4_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR4_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status1_SHIFT)) & NOC_GICD_GICD_ISERRR4_status1_MASK) #define NOC_GICD_GICD_ISERRR4_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR4_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR4_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status2_SHIFT)) & NOC_GICD_GICD_ISERRR4_status2_MASK) #define NOC_GICD_GICD_ISERRR4_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR4_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR4_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status3_SHIFT)) & NOC_GICD_GICD_ISERRR4_status3_MASK) #define NOC_GICD_GICD_ISERRR4_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR4_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR4_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status4_SHIFT)) & NOC_GICD_GICD_ISERRR4_status4_MASK) #define NOC_GICD_GICD_ISERRR4_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR4_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR4_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status5_SHIFT)) & NOC_GICD_GICD_ISERRR4_status5_MASK) #define NOC_GICD_GICD_ISERRR4_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR4_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR4_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status6_SHIFT)) & NOC_GICD_GICD_ISERRR4_status6_MASK) #define NOC_GICD_GICD_ISERRR4_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR4_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR4_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status7_SHIFT)) & NOC_GICD_GICD_ISERRR4_status7_MASK) #define NOC_GICD_GICD_ISERRR4_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR4_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR4_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status8_SHIFT)) & NOC_GICD_GICD_ISERRR4_status8_MASK) #define NOC_GICD_GICD_ISERRR4_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR4_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR4_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status9_SHIFT)) & NOC_GICD_GICD_ISERRR4_status9_MASK) #define NOC_GICD_GICD_ISERRR4_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR4_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR4_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status10_SHIFT)) & NOC_GICD_GICD_ISERRR4_status10_MASK) #define NOC_GICD_GICD_ISERRR4_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR4_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR4_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status11_SHIFT)) & NOC_GICD_GICD_ISERRR4_status11_MASK) #define NOC_GICD_GICD_ISERRR4_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR4_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR4_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status12_SHIFT)) & NOC_GICD_GICD_ISERRR4_status12_MASK) #define NOC_GICD_GICD_ISERRR4_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR4_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR4_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status13_SHIFT)) & NOC_GICD_GICD_ISERRR4_status13_MASK) #define NOC_GICD_GICD_ISERRR4_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR4_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR4_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status14_SHIFT)) & NOC_GICD_GICD_ISERRR4_status14_MASK) #define NOC_GICD_GICD_ISERRR4_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR4_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR4_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status15_SHIFT)) & NOC_GICD_GICD_ISERRR4_status15_MASK) #define NOC_GICD_GICD_ISERRR4_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR4_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR4_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status16_SHIFT)) & NOC_GICD_GICD_ISERRR4_status16_MASK) #define NOC_GICD_GICD_ISERRR4_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR4_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR4_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status17_SHIFT)) & NOC_GICD_GICD_ISERRR4_status17_MASK) #define NOC_GICD_GICD_ISERRR4_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR4_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR4_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status18_SHIFT)) & NOC_GICD_GICD_ISERRR4_status18_MASK) #define NOC_GICD_GICD_ISERRR4_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR4_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR4_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status19_SHIFT)) & NOC_GICD_GICD_ISERRR4_status19_MASK) #define NOC_GICD_GICD_ISERRR4_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR4_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR4_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status20_SHIFT)) & NOC_GICD_GICD_ISERRR4_status20_MASK) #define NOC_GICD_GICD_ISERRR4_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR4_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR4_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status21_SHIFT)) & NOC_GICD_GICD_ISERRR4_status21_MASK) #define NOC_GICD_GICD_ISERRR4_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR4_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR4_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status22_SHIFT)) & NOC_GICD_GICD_ISERRR4_status22_MASK) #define NOC_GICD_GICD_ISERRR4_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR4_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR4_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status23_SHIFT)) & NOC_GICD_GICD_ISERRR4_status23_MASK) #define NOC_GICD_GICD_ISERRR4_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR4_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR4_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status24_SHIFT)) & NOC_GICD_GICD_ISERRR4_status24_MASK) #define NOC_GICD_GICD_ISERRR4_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR4_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR4_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status25_SHIFT)) & NOC_GICD_GICD_ISERRR4_status25_MASK) #define NOC_GICD_GICD_ISERRR4_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR4_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR4_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status26_SHIFT)) & NOC_GICD_GICD_ISERRR4_status26_MASK) #define NOC_GICD_GICD_ISERRR4_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR4_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR4_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status27_SHIFT)) & NOC_GICD_GICD_ISERRR4_status27_MASK) #define NOC_GICD_GICD_ISERRR4_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR4_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR4_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status28_SHIFT)) & NOC_GICD_GICD_ISERRR4_status28_MASK) #define NOC_GICD_GICD_ISERRR4_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR4_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR4_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status29_SHIFT)) & NOC_GICD_GICD_ISERRR4_status29_MASK) #define NOC_GICD_GICD_ISERRR4_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR4_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR4_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status30_SHIFT)) & NOC_GICD_GICD_ISERRR4_status30_MASK) #define NOC_GICD_GICD_ISERRR4_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR4_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR4_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR4_status31_SHIFT)) & NOC_GICD_GICD_ISERRR4_status31_MASK) /*! @} */ /*! @name GICD_ISERRR5 - GICD_ISERRR5 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR5_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR5_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR5_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status0_SHIFT)) & NOC_GICD_GICD_ISERRR5_status0_MASK) #define NOC_GICD_GICD_ISERRR5_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR5_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR5_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status1_SHIFT)) & NOC_GICD_GICD_ISERRR5_status1_MASK) #define NOC_GICD_GICD_ISERRR5_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR5_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR5_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status2_SHIFT)) & NOC_GICD_GICD_ISERRR5_status2_MASK) #define NOC_GICD_GICD_ISERRR5_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR5_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR5_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status3_SHIFT)) & NOC_GICD_GICD_ISERRR5_status3_MASK) #define NOC_GICD_GICD_ISERRR5_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR5_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR5_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status4_SHIFT)) & NOC_GICD_GICD_ISERRR5_status4_MASK) #define NOC_GICD_GICD_ISERRR5_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR5_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR5_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status5_SHIFT)) & NOC_GICD_GICD_ISERRR5_status5_MASK) #define NOC_GICD_GICD_ISERRR5_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR5_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR5_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status6_SHIFT)) & NOC_GICD_GICD_ISERRR5_status6_MASK) #define NOC_GICD_GICD_ISERRR5_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR5_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR5_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status7_SHIFT)) & NOC_GICD_GICD_ISERRR5_status7_MASK) #define NOC_GICD_GICD_ISERRR5_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR5_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR5_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status8_SHIFT)) & NOC_GICD_GICD_ISERRR5_status8_MASK) #define NOC_GICD_GICD_ISERRR5_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR5_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR5_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status9_SHIFT)) & NOC_GICD_GICD_ISERRR5_status9_MASK) #define NOC_GICD_GICD_ISERRR5_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR5_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR5_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status10_SHIFT)) & NOC_GICD_GICD_ISERRR5_status10_MASK) #define NOC_GICD_GICD_ISERRR5_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR5_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR5_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status11_SHIFT)) & NOC_GICD_GICD_ISERRR5_status11_MASK) #define NOC_GICD_GICD_ISERRR5_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR5_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR5_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status12_SHIFT)) & NOC_GICD_GICD_ISERRR5_status12_MASK) #define NOC_GICD_GICD_ISERRR5_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR5_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR5_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status13_SHIFT)) & NOC_GICD_GICD_ISERRR5_status13_MASK) #define NOC_GICD_GICD_ISERRR5_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR5_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR5_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status14_SHIFT)) & NOC_GICD_GICD_ISERRR5_status14_MASK) #define NOC_GICD_GICD_ISERRR5_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR5_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR5_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status15_SHIFT)) & NOC_GICD_GICD_ISERRR5_status15_MASK) #define NOC_GICD_GICD_ISERRR5_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR5_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR5_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status16_SHIFT)) & NOC_GICD_GICD_ISERRR5_status16_MASK) #define NOC_GICD_GICD_ISERRR5_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR5_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR5_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status17_SHIFT)) & NOC_GICD_GICD_ISERRR5_status17_MASK) #define NOC_GICD_GICD_ISERRR5_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR5_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR5_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status18_SHIFT)) & NOC_GICD_GICD_ISERRR5_status18_MASK) #define NOC_GICD_GICD_ISERRR5_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR5_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR5_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status19_SHIFT)) & NOC_GICD_GICD_ISERRR5_status19_MASK) #define NOC_GICD_GICD_ISERRR5_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR5_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR5_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status20_SHIFT)) & NOC_GICD_GICD_ISERRR5_status20_MASK) #define NOC_GICD_GICD_ISERRR5_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR5_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR5_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status21_SHIFT)) & NOC_GICD_GICD_ISERRR5_status21_MASK) #define NOC_GICD_GICD_ISERRR5_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR5_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR5_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status22_SHIFT)) & NOC_GICD_GICD_ISERRR5_status22_MASK) #define NOC_GICD_GICD_ISERRR5_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR5_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR5_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status23_SHIFT)) & NOC_GICD_GICD_ISERRR5_status23_MASK) #define NOC_GICD_GICD_ISERRR5_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR5_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR5_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status24_SHIFT)) & NOC_GICD_GICD_ISERRR5_status24_MASK) #define NOC_GICD_GICD_ISERRR5_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR5_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR5_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status25_SHIFT)) & NOC_GICD_GICD_ISERRR5_status25_MASK) #define NOC_GICD_GICD_ISERRR5_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR5_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR5_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status26_SHIFT)) & NOC_GICD_GICD_ISERRR5_status26_MASK) #define NOC_GICD_GICD_ISERRR5_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR5_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR5_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status27_SHIFT)) & NOC_GICD_GICD_ISERRR5_status27_MASK) #define NOC_GICD_GICD_ISERRR5_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR5_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR5_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status28_SHIFT)) & NOC_GICD_GICD_ISERRR5_status28_MASK) #define NOC_GICD_GICD_ISERRR5_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR5_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR5_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status29_SHIFT)) & NOC_GICD_GICD_ISERRR5_status29_MASK) #define NOC_GICD_GICD_ISERRR5_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR5_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR5_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status30_SHIFT)) & NOC_GICD_GICD_ISERRR5_status30_MASK) #define NOC_GICD_GICD_ISERRR5_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR5_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR5_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR5_status31_SHIFT)) & NOC_GICD_GICD_ISERRR5_status31_MASK) /*! @} */ /*! @name GICD_ISERRR6 - GICD_ISERRR6 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR6_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR6_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR6_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status0_SHIFT)) & NOC_GICD_GICD_ISERRR6_status0_MASK) #define NOC_GICD_GICD_ISERRR6_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR6_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR6_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status1_SHIFT)) & NOC_GICD_GICD_ISERRR6_status1_MASK) #define NOC_GICD_GICD_ISERRR6_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR6_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR6_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status2_SHIFT)) & NOC_GICD_GICD_ISERRR6_status2_MASK) #define NOC_GICD_GICD_ISERRR6_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR6_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR6_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status3_SHIFT)) & NOC_GICD_GICD_ISERRR6_status3_MASK) #define NOC_GICD_GICD_ISERRR6_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR6_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR6_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status4_SHIFT)) & NOC_GICD_GICD_ISERRR6_status4_MASK) #define NOC_GICD_GICD_ISERRR6_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR6_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR6_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status5_SHIFT)) & NOC_GICD_GICD_ISERRR6_status5_MASK) #define NOC_GICD_GICD_ISERRR6_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR6_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR6_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status6_SHIFT)) & NOC_GICD_GICD_ISERRR6_status6_MASK) #define NOC_GICD_GICD_ISERRR6_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR6_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR6_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status7_SHIFT)) & NOC_GICD_GICD_ISERRR6_status7_MASK) #define NOC_GICD_GICD_ISERRR6_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR6_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR6_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status8_SHIFT)) & NOC_GICD_GICD_ISERRR6_status8_MASK) #define NOC_GICD_GICD_ISERRR6_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR6_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR6_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status9_SHIFT)) & NOC_GICD_GICD_ISERRR6_status9_MASK) #define NOC_GICD_GICD_ISERRR6_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR6_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR6_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status10_SHIFT)) & NOC_GICD_GICD_ISERRR6_status10_MASK) #define NOC_GICD_GICD_ISERRR6_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR6_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR6_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status11_SHIFT)) & NOC_GICD_GICD_ISERRR6_status11_MASK) #define NOC_GICD_GICD_ISERRR6_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR6_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR6_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status12_SHIFT)) & NOC_GICD_GICD_ISERRR6_status12_MASK) #define NOC_GICD_GICD_ISERRR6_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR6_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR6_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status13_SHIFT)) & NOC_GICD_GICD_ISERRR6_status13_MASK) #define NOC_GICD_GICD_ISERRR6_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR6_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR6_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status14_SHIFT)) & NOC_GICD_GICD_ISERRR6_status14_MASK) #define NOC_GICD_GICD_ISERRR6_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR6_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR6_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status15_SHIFT)) & NOC_GICD_GICD_ISERRR6_status15_MASK) #define NOC_GICD_GICD_ISERRR6_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR6_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR6_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status16_SHIFT)) & NOC_GICD_GICD_ISERRR6_status16_MASK) #define NOC_GICD_GICD_ISERRR6_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR6_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR6_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status17_SHIFT)) & NOC_GICD_GICD_ISERRR6_status17_MASK) #define NOC_GICD_GICD_ISERRR6_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR6_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR6_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status18_SHIFT)) & NOC_GICD_GICD_ISERRR6_status18_MASK) #define NOC_GICD_GICD_ISERRR6_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR6_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR6_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status19_SHIFT)) & NOC_GICD_GICD_ISERRR6_status19_MASK) #define NOC_GICD_GICD_ISERRR6_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR6_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR6_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status20_SHIFT)) & NOC_GICD_GICD_ISERRR6_status20_MASK) #define NOC_GICD_GICD_ISERRR6_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR6_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR6_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status21_SHIFT)) & NOC_GICD_GICD_ISERRR6_status21_MASK) #define NOC_GICD_GICD_ISERRR6_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR6_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR6_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status22_SHIFT)) & NOC_GICD_GICD_ISERRR6_status22_MASK) #define NOC_GICD_GICD_ISERRR6_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR6_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR6_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status23_SHIFT)) & NOC_GICD_GICD_ISERRR6_status23_MASK) #define NOC_GICD_GICD_ISERRR6_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR6_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR6_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status24_SHIFT)) & NOC_GICD_GICD_ISERRR6_status24_MASK) #define NOC_GICD_GICD_ISERRR6_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR6_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR6_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status25_SHIFT)) & NOC_GICD_GICD_ISERRR6_status25_MASK) #define NOC_GICD_GICD_ISERRR6_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR6_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR6_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status26_SHIFT)) & NOC_GICD_GICD_ISERRR6_status26_MASK) #define NOC_GICD_GICD_ISERRR6_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR6_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR6_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status27_SHIFT)) & NOC_GICD_GICD_ISERRR6_status27_MASK) #define NOC_GICD_GICD_ISERRR6_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR6_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR6_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status28_SHIFT)) & NOC_GICD_GICD_ISERRR6_status28_MASK) #define NOC_GICD_GICD_ISERRR6_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR6_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR6_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status29_SHIFT)) & NOC_GICD_GICD_ISERRR6_status29_MASK) #define NOC_GICD_GICD_ISERRR6_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR6_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR6_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status30_SHIFT)) & NOC_GICD_GICD_ISERRR6_status30_MASK) #define NOC_GICD_GICD_ISERRR6_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR6_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR6_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR6_status31_SHIFT)) & NOC_GICD_GICD_ISERRR6_status31_MASK) /*! @} */ /*! @name GICD_ISERRR7 - GICD_ISERRR7 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR7_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR7_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR7_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status0_SHIFT)) & NOC_GICD_GICD_ISERRR7_status0_MASK) #define NOC_GICD_GICD_ISERRR7_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR7_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR7_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status1_SHIFT)) & NOC_GICD_GICD_ISERRR7_status1_MASK) #define NOC_GICD_GICD_ISERRR7_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR7_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR7_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status2_SHIFT)) & NOC_GICD_GICD_ISERRR7_status2_MASK) #define NOC_GICD_GICD_ISERRR7_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR7_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR7_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status3_SHIFT)) & NOC_GICD_GICD_ISERRR7_status3_MASK) #define NOC_GICD_GICD_ISERRR7_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR7_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR7_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status4_SHIFT)) & NOC_GICD_GICD_ISERRR7_status4_MASK) #define NOC_GICD_GICD_ISERRR7_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR7_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR7_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status5_SHIFT)) & NOC_GICD_GICD_ISERRR7_status5_MASK) #define NOC_GICD_GICD_ISERRR7_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR7_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR7_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status6_SHIFT)) & NOC_GICD_GICD_ISERRR7_status6_MASK) #define NOC_GICD_GICD_ISERRR7_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR7_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR7_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status7_SHIFT)) & NOC_GICD_GICD_ISERRR7_status7_MASK) #define NOC_GICD_GICD_ISERRR7_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR7_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR7_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status8_SHIFT)) & NOC_GICD_GICD_ISERRR7_status8_MASK) #define NOC_GICD_GICD_ISERRR7_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR7_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR7_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status9_SHIFT)) & NOC_GICD_GICD_ISERRR7_status9_MASK) #define NOC_GICD_GICD_ISERRR7_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR7_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR7_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status10_SHIFT)) & NOC_GICD_GICD_ISERRR7_status10_MASK) #define NOC_GICD_GICD_ISERRR7_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR7_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR7_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status11_SHIFT)) & NOC_GICD_GICD_ISERRR7_status11_MASK) #define NOC_GICD_GICD_ISERRR7_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR7_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR7_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status12_SHIFT)) & NOC_GICD_GICD_ISERRR7_status12_MASK) #define NOC_GICD_GICD_ISERRR7_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR7_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR7_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status13_SHIFT)) & NOC_GICD_GICD_ISERRR7_status13_MASK) #define NOC_GICD_GICD_ISERRR7_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR7_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR7_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status14_SHIFT)) & NOC_GICD_GICD_ISERRR7_status14_MASK) #define NOC_GICD_GICD_ISERRR7_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR7_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR7_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status15_SHIFT)) & NOC_GICD_GICD_ISERRR7_status15_MASK) #define NOC_GICD_GICD_ISERRR7_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR7_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR7_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status16_SHIFT)) & NOC_GICD_GICD_ISERRR7_status16_MASK) #define NOC_GICD_GICD_ISERRR7_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR7_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR7_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status17_SHIFT)) & NOC_GICD_GICD_ISERRR7_status17_MASK) #define NOC_GICD_GICD_ISERRR7_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR7_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR7_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status18_SHIFT)) & NOC_GICD_GICD_ISERRR7_status18_MASK) #define NOC_GICD_GICD_ISERRR7_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR7_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR7_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status19_SHIFT)) & NOC_GICD_GICD_ISERRR7_status19_MASK) #define NOC_GICD_GICD_ISERRR7_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR7_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR7_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status20_SHIFT)) & NOC_GICD_GICD_ISERRR7_status20_MASK) #define NOC_GICD_GICD_ISERRR7_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR7_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR7_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status21_SHIFT)) & NOC_GICD_GICD_ISERRR7_status21_MASK) #define NOC_GICD_GICD_ISERRR7_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR7_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR7_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status22_SHIFT)) & NOC_GICD_GICD_ISERRR7_status22_MASK) #define NOC_GICD_GICD_ISERRR7_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR7_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR7_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status23_SHIFT)) & NOC_GICD_GICD_ISERRR7_status23_MASK) #define NOC_GICD_GICD_ISERRR7_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR7_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR7_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status24_SHIFT)) & NOC_GICD_GICD_ISERRR7_status24_MASK) #define NOC_GICD_GICD_ISERRR7_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR7_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR7_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status25_SHIFT)) & NOC_GICD_GICD_ISERRR7_status25_MASK) #define NOC_GICD_GICD_ISERRR7_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR7_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR7_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status26_SHIFT)) & NOC_GICD_GICD_ISERRR7_status26_MASK) #define NOC_GICD_GICD_ISERRR7_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR7_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR7_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status27_SHIFT)) & NOC_GICD_GICD_ISERRR7_status27_MASK) #define NOC_GICD_GICD_ISERRR7_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR7_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR7_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status28_SHIFT)) & NOC_GICD_GICD_ISERRR7_status28_MASK) #define NOC_GICD_GICD_ISERRR7_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR7_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR7_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status29_SHIFT)) & NOC_GICD_GICD_ISERRR7_status29_MASK) #define NOC_GICD_GICD_ISERRR7_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR7_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR7_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status30_SHIFT)) & NOC_GICD_GICD_ISERRR7_status30_MASK) #define NOC_GICD_GICD_ISERRR7_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR7_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR7_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR7_status31_SHIFT)) & NOC_GICD_GICD_ISERRR7_status31_MASK) /*! @} */ /*! @name GICD_ISERRR8 - GICD_ISERRR8 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR8_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR8_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR8_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status0_SHIFT)) & NOC_GICD_GICD_ISERRR8_status0_MASK) #define NOC_GICD_GICD_ISERRR8_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR8_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR8_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status1_SHIFT)) & NOC_GICD_GICD_ISERRR8_status1_MASK) #define NOC_GICD_GICD_ISERRR8_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR8_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR8_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status2_SHIFT)) & NOC_GICD_GICD_ISERRR8_status2_MASK) #define NOC_GICD_GICD_ISERRR8_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR8_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR8_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status3_SHIFT)) & NOC_GICD_GICD_ISERRR8_status3_MASK) #define NOC_GICD_GICD_ISERRR8_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR8_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR8_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status4_SHIFT)) & NOC_GICD_GICD_ISERRR8_status4_MASK) #define NOC_GICD_GICD_ISERRR8_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR8_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR8_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status5_SHIFT)) & NOC_GICD_GICD_ISERRR8_status5_MASK) #define NOC_GICD_GICD_ISERRR8_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR8_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR8_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status6_SHIFT)) & NOC_GICD_GICD_ISERRR8_status6_MASK) #define NOC_GICD_GICD_ISERRR8_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR8_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR8_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status7_SHIFT)) & NOC_GICD_GICD_ISERRR8_status7_MASK) #define NOC_GICD_GICD_ISERRR8_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR8_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR8_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status8_SHIFT)) & NOC_GICD_GICD_ISERRR8_status8_MASK) #define NOC_GICD_GICD_ISERRR8_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR8_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR8_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status9_SHIFT)) & NOC_GICD_GICD_ISERRR8_status9_MASK) #define NOC_GICD_GICD_ISERRR8_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR8_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR8_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status10_SHIFT)) & NOC_GICD_GICD_ISERRR8_status10_MASK) #define NOC_GICD_GICD_ISERRR8_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR8_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR8_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status11_SHIFT)) & NOC_GICD_GICD_ISERRR8_status11_MASK) #define NOC_GICD_GICD_ISERRR8_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR8_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR8_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status12_SHIFT)) & NOC_GICD_GICD_ISERRR8_status12_MASK) #define NOC_GICD_GICD_ISERRR8_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR8_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR8_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status13_SHIFT)) & NOC_GICD_GICD_ISERRR8_status13_MASK) #define NOC_GICD_GICD_ISERRR8_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR8_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR8_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status14_SHIFT)) & NOC_GICD_GICD_ISERRR8_status14_MASK) #define NOC_GICD_GICD_ISERRR8_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR8_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR8_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status15_SHIFT)) & NOC_GICD_GICD_ISERRR8_status15_MASK) #define NOC_GICD_GICD_ISERRR8_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR8_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR8_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status16_SHIFT)) & NOC_GICD_GICD_ISERRR8_status16_MASK) #define NOC_GICD_GICD_ISERRR8_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR8_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR8_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status17_SHIFT)) & NOC_GICD_GICD_ISERRR8_status17_MASK) #define NOC_GICD_GICD_ISERRR8_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR8_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR8_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status18_SHIFT)) & NOC_GICD_GICD_ISERRR8_status18_MASK) #define NOC_GICD_GICD_ISERRR8_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR8_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR8_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status19_SHIFT)) & NOC_GICD_GICD_ISERRR8_status19_MASK) #define NOC_GICD_GICD_ISERRR8_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR8_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR8_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status20_SHIFT)) & NOC_GICD_GICD_ISERRR8_status20_MASK) #define NOC_GICD_GICD_ISERRR8_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR8_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR8_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status21_SHIFT)) & NOC_GICD_GICD_ISERRR8_status21_MASK) #define NOC_GICD_GICD_ISERRR8_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR8_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR8_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status22_SHIFT)) & NOC_GICD_GICD_ISERRR8_status22_MASK) #define NOC_GICD_GICD_ISERRR8_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR8_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR8_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status23_SHIFT)) & NOC_GICD_GICD_ISERRR8_status23_MASK) #define NOC_GICD_GICD_ISERRR8_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR8_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR8_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status24_SHIFT)) & NOC_GICD_GICD_ISERRR8_status24_MASK) #define NOC_GICD_GICD_ISERRR8_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR8_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR8_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status25_SHIFT)) & NOC_GICD_GICD_ISERRR8_status25_MASK) #define NOC_GICD_GICD_ISERRR8_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR8_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR8_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status26_SHIFT)) & NOC_GICD_GICD_ISERRR8_status26_MASK) #define NOC_GICD_GICD_ISERRR8_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR8_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR8_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status27_SHIFT)) & NOC_GICD_GICD_ISERRR8_status27_MASK) #define NOC_GICD_GICD_ISERRR8_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR8_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR8_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status28_SHIFT)) & NOC_GICD_GICD_ISERRR8_status28_MASK) #define NOC_GICD_GICD_ISERRR8_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR8_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR8_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status29_SHIFT)) & NOC_GICD_GICD_ISERRR8_status29_MASK) #define NOC_GICD_GICD_ISERRR8_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR8_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR8_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status30_SHIFT)) & NOC_GICD_GICD_ISERRR8_status30_MASK) #define NOC_GICD_GICD_ISERRR8_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR8_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR8_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR8_status31_SHIFT)) & NOC_GICD_GICD_ISERRR8_status31_MASK) /*! @} */ /*! @name GICD_ISERRR9 - GICD_ISERRR9 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR9_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR9_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR9_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status0_SHIFT)) & NOC_GICD_GICD_ISERRR9_status0_MASK) #define NOC_GICD_GICD_ISERRR9_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR9_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR9_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status1_SHIFT)) & NOC_GICD_GICD_ISERRR9_status1_MASK) #define NOC_GICD_GICD_ISERRR9_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR9_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR9_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status2_SHIFT)) & NOC_GICD_GICD_ISERRR9_status2_MASK) #define NOC_GICD_GICD_ISERRR9_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR9_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR9_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status3_SHIFT)) & NOC_GICD_GICD_ISERRR9_status3_MASK) #define NOC_GICD_GICD_ISERRR9_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR9_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR9_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status4_SHIFT)) & NOC_GICD_GICD_ISERRR9_status4_MASK) #define NOC_GICD_GICD_ISERRR9_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR9_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR9_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status5_SHIFT)) & NOC_GICD_GICD_ISERRR9_status5_MASK) #define NOC_GICD_GICD_ISERRR9_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR9_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR9_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status6_SHIFT)) & NOC_GICD_GICD_ISERRR9_status6_MASK) #define NOC_GICD_GICD_ISERRR9_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR9_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR9_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status7_SHIFT)) & NOC_GICD_GICD_ISERRR9_status7_MASK) #define NOC_GICD_GICD_ISERRR9_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR9_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR9_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status8_SHIFT)) & NOC_GICD_GICD_ISERRR9_status8_MASK) #define NOC_GICD_GICD_ISERRR9_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR9_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR9_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status9_SHIFT)) & NOC_GICD_GICD_ISERRR9_status9_MASK) #define NOC_GICD_GICD_ISERRR9_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR9_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR9_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status10_SHIFT)) & NOC_GICD_GICD_ISERRR9_status10_MASK) #define NOC_GICD_GICD_ISERRR9_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR9_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR9_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status11_SHIFT)) & NOC_GICD_GICD_ISERRR9_status11_MASK) #define NOC_GICD_GICD_ISERRR9_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR9_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR9_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status12_SHIFT)) & NOC_GICD_GICD_ISERRR9_status12_MASK) #define NOC_GICD_GICD_ISERRR9_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR9_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR9_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status13_SHIFT)) & NOC_GICD_GICD_ISERRR9_status13_MASK) #define NOC_GICD_GICD_ISERRR9_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR9_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR9_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status14_SHIFT)) & NOC_GICD_GICD_ISERRR9_status14_MASK) #define NOC_GICD_GICD_ISERRR9_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR9_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR9_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status15_SHIFT)) & NOC_GICD_GICD_ISERRR9_status15_MASK) #define NOC_GICD_GICD_ISERRR9_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR9_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR9_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status16_SHIFT)) & NOC_GICD_GICD_ISERRR9_status16_MASK) #define NOC_GICD_GICD_ISERRR9_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR9_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR9_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status17_SHIFT)) & NOC_GICD_GICD_ISERRR9_status17_MASK) #define NOC_GICD_GICD_ISERRR9_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR9_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR9_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status18_SHIFT)) & NOC_GICD_GICD_ISERRR9_status18_MASK) #define NOC_GICD_GICD_ISERRR9_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR9_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR9_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status19_SHIFT)) & NOC_GICD_GICD_ISERRR9_status19_MASK) #define NOC_GICD_GICD_ISERRR9_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR9_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR9_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status20_SHIFT)) & NOC_GICD_GICD_ISERRR9_status20_MASK) #define NOC_GICD_GICD_ISERRR9_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR9_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR9_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status21_SHIFT)) & NOC_GICD_GICD_ISERRR9_status21_MASK) #define NOC_GICD_GICD_ISERRR9_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR9_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR9_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status22_SHIFT)) & NOC_GICD_GICD_ISERRR9_status22_MASK) #define NOC_GICD_GICD_ISERRR9_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR9_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR9_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status23_SHIFT)) & NOC_GICD_GICD_ISERRR9_status23_MASK) #define NOC_GICD_GICD_ISERRR9_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR9_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR9_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status24_SHIFT)) & NOC_GICD_GICD_ISERRR9_status24_MASK) #define NOC_GICD_GICD_ISERRR9_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR9_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR9_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status25_SHIFT)) & NOC_GICD_GICD_ISERRR9_status25_MASK) #define NOC_GICD_GICD_ISERRR9_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR9_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR9_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status26_SHIFT)) & NOC_GICD_GICD_ISERRR9_status26_MASK) #define NOC_GICD_GICD_ISERRR9_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR9_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR9_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status27_SHIFT)) & NOC_GICD_GICD_ISERRR9_status27_MASK) #define NOC_GICD_GICD_ISERRR9_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR9_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR9_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status28_SHIFT)) & NOC_GICD_GICD_ISERRR9_status28_MASK) #define NOC_GICD_GICD_ISERRR9_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR9_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR9_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status29_SHIFT)) & NOC_GICD_GICD_ISERRR9_status29_MASK) #define NOC_GICD_GICD_ISERRR9_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR9_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR9_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status30_SHIFT)) & NOC_GICD_GICD_ISERRR9_status30_MASK) #define NOC_GICD_GICD_ISERRR9_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR9_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR9_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR9_status31_SHIFT)) & NOC_GICD_GICD_ISERRR9_status31_MASK) /*! @} */ /*! @name GICD_ISERRR10 - GICD_ISERRR10 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR10_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR10_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR10_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status0_SHIFT)) & NOC_GICD_GICD_ISERRR10_status0_MASK) #define NOC_GICD_GICD_ISERRR10_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR10_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR10_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status1_SHIFT)) & NOC_GICD_GICD_ISERRR10_status1_MASK) #define NOC_GICD_GICD_ISERRR10_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR10_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR10_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status2_SHIFT)) & NOC_GICD_GICD_ISERRR10_status2_MASK) #define NOC_GICD_GICD_ISERRR10_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR10_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR10_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status3_SHIFT)) & NOC_GICD_GICD_ISERRR10_status3_MASK) #define NOC_GICD_GICD_ISERRR10_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR10_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR10_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status4_SHIFT)) & NOC_GICD_GICD_ISERRR10_status4_MASK) #define NOC_GICD_GICD_ISERRR10_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR10_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR10_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status5_SHIFT)) & NOC_GICD_GICD_ISERRR10_status5_MASK) #define NOC_GICD_GICD_ISERRR10_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR10_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR10_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status6_SHIFT)) & NOC_GICD_GICD_ISERRR10_status6_MASK) #define NOC_GICD_GICD_ISERRR10_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR10_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR10_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status7_SHIFT)) & NOC_GICD_GICD_ISERRR10_status7_MASK) #define NOC_GICD_GICD_ISERRR10_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR10_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR10_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status8_SHIFT)) & NOC_GICD_GICD_ISERRR10_status8_MASK) #define NOC_GICD_GICD_ISERRR10_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR10_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR10_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status9_SHIFT)) & NOC_GICD_GICD_ISERRR10_status9_MASK) #define NOC_GICD_GICD_ISERRR10_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR10_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR10_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status10_SHIFT)) & NOC_GICD_GICD_ISERRR10_status10_MASK) #define NOC_GICD_GICD_ISERRR10_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR10_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR10_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status11_SHIFT)) & NOC_GICD_GICD_ISERRR10_status11_MASK) #define NOC_GICD_GICD_ISERRR10_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR10_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR10_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status12_SHIFT)) & NOC_GICD_GICD_ISERRR10_status12_MASK) #define NOC_GICD_GICD_ISERRR10_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR10_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR10_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status13_SHIFT)) & NOC_GICD_GICD_ISERRR10_status13_MASK) #define NOC_GICD_GICD_ISERRR10_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR10_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR10_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status14_SHIFT)) & NOC_GICD_GICD_ISERRR10_status14_MASK) #define NOC_GICD_GICD_ISERRR10_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR10_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR10_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status15_SHIFT)) & NOC_GICD_GICD_ISERRR10_status15_MASK) #define NOC_GICD_GICD_ISERRR10_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR10_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR10_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status16_SHIFT)) & NOC_GICD_GICD_ISERRR10_status16_MASK) #define NOC_GICD_GICD_ISERRR10_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR10_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR10_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status17_SHIFT)) & NOC_GICD_GICD_ISERRR10_status17_MASK) #define NOC_GICD_GICD_ISERRR10_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR10_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR10_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status18_SHIFT)) & NOC_GICD_GICD_ISERRR10_status18_MASK) #define NOC_GICD_GICD_ISERRR10_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR10_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR10_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status19_SHIFT)) & NOC_GICD_GICD_ISERRR10_status19_MASK) #define NOC_GICD_GICD_ISERRR10_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR10_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR10_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status20_SHIFT)) & NOC_GICD_GICD_ISERRR10_status20_MASK) #define NOC_GICD_GICD_ISERRR10_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR10_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR10_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status21_SHIFT)) & NOC_GICD_GICD_ISERRR10_status21_MASK) #define NOC_GICD_GICD_ISERRR10_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR10_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR10_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status22_SHIFT)) & NOC_GICD_GICD_ISERRR10_status22_MASK) #define NOC_GICD_GICD_ISERRR10_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR10_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR10_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status23_SHIFT)) & NOC_GICD_GICD_ISERRR10_status23_MASK) #define NOC_GICD_GICD_ISERRR10_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR10_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR10_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status24_SHIFT)) & NOC_GICD_GICD_ISERRR10_status24_MASK) #define NOC_GICD_GICD_ISERRR10_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR10_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR10_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status25_SHIFT)) & NOC_GICD_GICD_ISERRR10_status25_MASK) #define NOC_GICD_GICD_ISERRR10_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR10_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR10_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status26_SHIFT)) & NOC_GICD_GICD_ISERRR10_status26_MASK) #define NOC_GICD_GICD_ISERRR10_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR10_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR10_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status27_SHIFT)) & NOC_GICD_GICD_ISERRR10_status27_MASK) #define NOC_GICD_GICD_ISERRR10_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR10_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR10_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status28_SHIFT)) & NOC_GICD_GICD_ISERRR10_status28_MASK) #define NOC_GICD_GICD_ISERRR10_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR10_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR10_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status29_SHIFT)) & NOC_GICD_GICD_ISERRR10_status29_MASK) #define NOC_GICD_GICD_ISERRR10_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR10_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR10_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status30_SHIFT)) & NOC_GICD_GICD_ISERRR10_status30_MASK) #define NOC_GICD_GICD_ISERRR10_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR10_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR10_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR10_status31_SHIFT)) & NOC_GICD_GICD_ISERRR10_status31_MASK) /*! @} */ /*! @name GICD_ISERRR11 - GICD_ISERRR11 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR11_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR11_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR11_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status0_SHIFT)) & NOC_GICD_GICD_ISERRR11_status0_MASK) #define NOC_GICD_GICD_ISERRR11_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR11_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR11_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status1_SHIFT)) & NOC_GICD_GICD_ISERRR11_status1_MASK) #define NOC_GICD_GICD_ISERRR11_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR11_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR11_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status2_SHIFT)) & NOC_GICD_GICD_ISERRR11_status2_MASK) #define NOC_GICD_GICD_ISERRR11_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR11_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR11_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status3_SHIFT)) & NOC_GICD_GICD_ISERRR11_status3_MASK) #define NOC_GICD_GICD_ISERRR11_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR11_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR11_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status4_SHIFT)) & NOC_GICD_GICD_ISERRR11_status4_MASK) #define NOC_GICD_GICD_ISERRR11_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR11_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR11_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status5_SHIFT)) & NOC_GICD_GICD_ISERRR11_status5_MASK) #define NOC_GICD_GICD_ISERRR11_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR11_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR11_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status6_SHIFT)) & NOC_GICD_GICD_ISERRR11_status6_MASK) #define NOC_GICD_GICD_ISERRR11_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR11_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR11_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status7_SHIFT)) & NOC_GICD_GICD_ISERRR11_status7_MASK) #define NOC_GICD_GICD_ISERRR11_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR11_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR11_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status8_SHIFT)) & NOC_GICD_GICD_ISERRR11_status8_MASK) #define NOC_GICD_GICD_ISERRR11_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR11_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR11_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status9_SHIFT)) & NOC_GICD_GICD_ISERRR11_status9_MASK) #define NOC_GICD_GICD_ISERRR11_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR11_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR11_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status10_SHIFT)) & NOC_GICD_GICD_ISERRR11_status10_MASK) #define NOC_GICD_GICD_ISERRR11_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR11_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR11_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status11_SHIFT)) & NOC_GICD_GICD_ISERRR11_status11_MASK) #define NOC_GICD_GICD_ISERRR11_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR11_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR11_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status12_SHIFT)) & NOC_GICD_GICD_ISERRR11_status12_MASK) #define NOC_GICD_GICD_ISERRR11_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR11_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR11_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status13_SHIFT)) & NOC_GICD_GICD_ISERRR11_status13_MASK) #define NOC_GICD_GICD_ISERRR11_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR11_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR11_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status14_SHIFT)) & NOC_GICD_GICD_ISERRR11_status14_MASK) #define NOC_GICD_GICD_ISERRR11_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR11_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR11_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status15_SHIFT)) & NOC_GICD_GICD_ISERRR11_status15_MASK) #define NOC_GICD_GICD_ISERRR11_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR11_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR11_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status16_SHIFT)) & NOC_GICD_GICD_ISERRR11_status16_MASK) #define NOC_GICD_GICD_ISERRR11_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR11_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR11_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status17_SHIFT)) & NOC_GICD_GICD_ISERRR11_status17_MASK) #define NOC_GICD_GICD_ISERRR11_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR11_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR11_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status18_SHIFT)) & NOC_GICD_GICD_ISERRR11_status18_MASK) #define NOC_GICD_GICD_ISERRR11_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR11_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR11_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status19_SHIFT)) & NOC_GICD_GICD_ISERRR11_status19_MASK) #define NOC_GICD_GICD_ISERRR11_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR11_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR11_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status20_SHIFT)) & NOC_GICD_GICD_ISERRR11_status20_MASK) #define NOC_GICD_GICD_ISERRR11_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR11_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR11_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status21_SHIFT)) & NOC_GICD_GICD_ISERRR11_status21_MASK) #define NOC_GICD_GICD_ISERRR11_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR11_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR11_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status22_SHIFT)) & NOC_GICD_GICD_ISERRR11_status22_MASK) #define NOC_GICD_GICD_ISERRR11_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR11_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR11_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status23_SHIFT)) & NOC_GICD_GICD_ISERRR11_status23_MASK) #define NOC_GICD_GICD_ISERRR11_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR11_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR11_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status24_SHIFT)) & NOC_GICD_GICD_ISERRR11_status24_MASK) #define NOC_GICD_GICD_ISERRR11_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR11_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR11_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status25_SHIFT)) & NOC_GICD_GICD_ISERRR11_status25_MASK) #define NOC_GICD_GICD_ISERRR11_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR11_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR11_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status26_SHIFT)) & NOC_GICD_GICD_ISERRR11_status26_MASK) #define NOC_GICD_GICD_ISERRR11_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR11_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR11_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status27_SHIFT)) & NOC_GICD_GICD_ISERRR11_status27_MASK) #define NOC_GICD_GICD_ISERRR11_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR11_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR11_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status28_SHIFT)) & NOC_GICD_GICD_ISERRR11_status28_MASK) #define NOC_GICD_GICD_ISERRR11_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR11_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR11_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status29_SHIFT)) & NOC_GICD_GICD_ISERRR11_status29_MASK) #define NOC_GICD_GICD_ISERRR11_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR11_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR11_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status30_SHIFT)) & NOC_GICD_GICD_ISERRR11_status30_MASK) #define NOC_GICD_GICD_ISERRR11_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR11_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR11_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR11_status31_SHIFT)) & NOC_GICD_GICD_ISERRR11_status31_MASK) /*! @} */ /*! @name GICD_ISERRR12 - GICD_ISERRR12 */ /*! @{ */ #define NOC_GICD_GICD_ISERRR12_status0_MASK (0x1U) #define NOC_GICD_GICD_ISERRR12_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICD_GICD_ISERRR12_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status0_SHIFT)) & NOC_GICD_GICD_ISERRR12_status0_MASK) #define NOC_GICD_GICD_ISERRR12_status1_MASK (0x2U) #define NOC_GICD_GICD_ISERRR12_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICD_GICD_ISERRR12_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status1_SHIFT)) & NOC_GICD_GICD_ISERRR12_status1_MASK) #define NOC_GICD_GICD_ISERRR12_status2_MASK (0x4U) #define NOC_GICD_GICD_ISERRR12_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICD_GICD_ISERRR12_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status2_SHIFT)) & NOC_GICD_GICD_ISERRR12_status2_MASK) #define NOC_GICD_GICD_ISERRR12_status3_MASK (0x8U) #define NOC_GICD_GICD_ISERRR12_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICD_GICD_ISERRR12_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status3_SHIFT)) & NOC_GICD_GICD_ISERRR12_status3_MASK) #define NOC_GICD_GICD_ISERRR12_status4_MASK (0x10U) #define NOC_GICD_GICD_ISERRR12_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICD_GICD_ISERRR12_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status4_SHIFT)) & NOC_GICD_GICD_ISERRR12_status4_MASK) #define NOC_GICD_GICD_ISERRR12_status5_MASK (0x20U) #define NOC_GICD_GICD_ISERRR12_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICD_GICD_ISERRR12_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status5_SHIFT)) & NOC_GICD_GICD_ISERRR12_status5_MASK) #define NOC_GICD_GICD_ISERRR12_status6_MASK (0x40U) #define NOC_GICD_GICD_ISERRR12_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICD_GICD_ISERRR12_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status6_SHIFT)) & NOC_GICD_GICD_ISERRR12_status6_MASK) #define NOC_GICD_GICD_ISERRR12_status7_MASK (0x80U) #define NOC_GICD_GICD_ISERRR12_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICD_GICD_ISERRR12_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status7_SHIFT)) & NOC_GICD_GICD_ISERRR12_status7_MASK) #define NOC_GICD_GICD_ISERRR12_status8_MASK (0x100U) #define NOC_GICD_GICD_ISERRR12_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICD_GICD_ISERRR12_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status8_SHIFT)) & NOC_GICD_GICD_ISERRR12_status8_MASK) #define NOC_GICD_GICD_ISERRR12_status9_MASK (0x200U) #define NOC_GICD_GICD_ISERRR12_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICD_GICD_ISERRR12_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status9_SHIFT)) & NOC_GICD_GICD_ISERRR12_status9_MASK) #define NOC_GICD_GICD_ISERRR12_status10_MASK (0x400U) #define NOC_GICD_GICD_ISERRR12_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICD_GICD_ISERRR12_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status10_SHIFT)) & NOC_GICD_GICD_ISERRR12_status10_MASK) #define NOC_GICD_GICD_ISERRR12_status11_MASK (0x800U) #define NOC_GICD_GICD_ISERRR12_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICD_GICD_ISERRR12_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status11_SHIFT)) & NOC_GICD_GICD_ISERRR12_status11_MASK) #define NOC_GICD_GICD_ISERRR12_status12_MASK (0x1000U) #define NOC_GICD_GICD_ISERRR12_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICD_GICD_ISERRR12_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status12_SHIFT)) & NOC_GICD_GICD_ISERRR12_status12_MASK) #define NOC_GICD_GICD_ISERRR12_status13_MASK (0x2000U) #define NOC_GICD_GICD_ISERRR12_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICD_GICD_ISERRR12_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status13_SHIFT)) & NOC_GICD_GICD_ISERRR12_status13_MASK) #define NOC_GICD_GICD_ISERRR12_status14_MASK (0x4000U) #define NOC_GICD_GICD_ISERRR12_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICD_GICD_ISERRR12_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status14_SHIFT)) & NOC_GICD_GICD_ISERRR12_status14_MASK) #define NOC_GICD_GICD_ISERRR12_status15_MASK (0x8000U) #define NOC_GICD_GICD_ISERRR12_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICD_GICD_ISERRR12_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status15_SHIFT)) & NOC_GICD_GICD_ISERRR12_status15_MASK) #define NOC_GICD_GICD_ISERRR12_status16_MASK (0x10000U) #define NOC_GICD_GICD_ISERRR12_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICD_GICD_ISERRR12_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status16_SHIFT)) & NOC_GICD_GICD_ISERRR12_status16_MASK) #define NOC_GICD_GICD_ISERRR12_status17_MASK (0x20000U) #define NOC_GICD_GICD_ISERRR12_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICD_GICD_ISERRR12_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status17_SHIFT)) & NOC_GICD_GICD_ISERRR12_status17_MASK) #define NOC_GICD_GICD_ISERRR12_status18_MASK (0x40000U) #define NOC_GICD_GICD_ISERRR12_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICD_GICD_ISERRR12_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status18_SHIFT)) & NOC_GICD_GICD_ISERRR12_status18_MASK) #define NOC_GICD_GICD_ISERRR12_status19_MASK (0x80000U) #define NOC_GICD_GICD_ISERRR12_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICD_GICD_ISERRR12_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status19_SHIFT)) & NOC_GICD_GICD_ISERRR12_status19_MASK) #define NOC_GICD_GICD_ISERRR12_status20_MASK (0x100000U) #define NOC_GICD_GICD_ISERRR12_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICD_GICD_ISERRR12_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status20_SHIFT)) & NOC_GICD_GICD_ISERRR12_status20_MASK) #define NOC_GICD_GICD_ISERRR12_status21_MASK (0x200000U) #define NOC_GICD_GICD_ISERRR12_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICD_GICD_ISERRR12_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status21_SHIFT)) & NOC_GICD_GICD_ISERRR12_status21_MASK) #define NOC_GICD_GICD_ISERRR12_status22_MASK (0x400000U) #define NOC_GICD_GICD_ISERRR12_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICD_GICD_ISERRR12_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status22_SHIFT)) & NOC_GICD_GICD_ISERRR12_status22_MASK) #define NOC_GICD_GICD_ISERRR12_status23_MASK (0x800000U) #define NOC_GICD_GICD_ISERRR12_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICD_GICD_ISERRR12_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status23_SHIFT)) & NOC_GICD_GICD_ISERRR12_status23_MASK) #define NOC_GICD_GICD_ISERRR12_status24_MASK (0x1000000U) #define NOC_GICD_GICD_ISERRR12_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICD_GICD_ISERRR12_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status24_SHIFT)) & NOC_GICD_GICD_ISERRR12_status24_MASK) #define NOC_GICD_GICD_ISERRR12_status25_MASK (0x2000000U) #define NOC_GICD_GICD_ISERRR12_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICD_GICD_ISERRR12_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status25_SHIFT)) & NOC_GICD_GICD_ISERRR12_status25_MASK) #define NOC_GICD_GICD_ISERRR12_status26_MASK (0x4000000U) #define NOC_GICD_GICD_ISERRR12_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICD_GICD_ISERRR12_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status26_SHIFT)) & NOC_GICD_GICD_ISERRR12_status26_MASK) #define NOC_GICD_GICD_ISERRR12_status27_MASK (0x8000000U) #define NOC_GICD_GICD_ISERRR12_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICD_GICD_ISERRR12_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status27_SHIFT)) & NOC_GICD_GICD_ISERRR12_status27_MASK) #define NOC_GICD_GICD_ISERRR12_status28_MASK (0x10000000U) #define NOC_GICD_GICD_ISERRR12_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICD_GICD_ISERRR12_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status28_SHIFT)) & NOC_GICD_GICD_ISERRR12_status28_MASK) #define NOC_GICD_GICD_ISERRR12_status29_MASK (0x20000000U) #define NOC_GICD_GICD_ISERRR12_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICD_GICD_ISERRR12_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status29_SHIFT)) & NOC_GICD_GICD_ISERRR12_status29_MASK) #define NOC_GICD_GICD_ISERRR12_status30_MASK (0x40000000U) #define NOC_GICD_GICD_ISERRR12_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICD_GICD_ISERRR12_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status30_SHIFT)) & NOC_GICD_GICD_ISERRR12_status30_MASK) #define NOC_GICD_GICD_ISERRR12_status31_MASK (0x80000000U) #define NOC_GICD_GICD_ISERRR12_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICD_GICD_ISERRR12_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_ISERRR12_status31_SHIFT)) & NOC_GICD_GICD_ISERRR12_status31_MASK) /*! @} */ /*! @name GICD_CFGID - GICD_CFGID */ /*! @{ */ #define NOC_GICD_GICD_CFGID_SocketOnline_MASK (0x1U) #define NOC_GICD_GICD_CFGID_SocketOnline_SHIFT (0U) /*! SocketOnline - SocketOnline */ #define NOC_GICD_GICD_CFGID_SocketOnline(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_SocketOnline_SHIFT)) & NOC_GICD_GICD_CFGID_SocketOnline_MASK) #define NOC_GICD_GICD_CFGID_RESERVED0_MASK (0xEU) #define NOC_GICD_GICD_CFGID_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CFGID_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_RESERVED0_SHIFT)) & NOC_GICD_GICD_CFGID_RESERVED0_MASK) #define NOC_GICD_GICD_CFGID_SocketNumber_MASK (0xF0U) #define NOC_GICD_GICD_CFGID_SocketNumber_SHIFT (4U) /*! SocketNumber - SocketNumber */ #define NOC_GICD_GICD_CFGID_SocketNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_SocketNumber_SHIFT)) & NOC_GICD_GICD_CFGID_SocketNumber_MASK) #define NOC_GICD_GICD_CFGID_ITSCount_MASK (0xF00U) #define NOC_GICD_GICD_CFGID_ITSCount_SHIFT (8U) /*! ITSCount - ITSCount */ #define NOC_GICD_GICD_CFGID_ITSCount(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_ITSCount_SHIFT)) & NOC_GICD_GICD_CFGID_ITSCount_MASK) #define NOC_GICD_GICD_CFGID_LPISupport_MASK (0x1000U) #define NOC_GICD_GICD_CFGID_LPISupport_SHIFT (12U) /*! LPISupport - LPISupport */ #define NOC_GICD_GICD_CFGID_LPISupport(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_LPISupport_SHIFT)) & NOC_GICD_GICD_CFGID_LPISupport_MASK) #define NOC_GICD_GICD_CFGID_v41Support_MASK (0x2000U) #define NOC_GICD_GICD_CFGID_v41Support_SHIFT (13U) /*! v41Support - v41Support */ #define NOC_GICD_GICD_CFGID_v41Support(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_v41Support_SHIFT)) & NOC_GICD_GICD_CFGID_v41Support_MASK) #define NOC_GICD_GICD_CFGID_ChipAffinityLevel_MASK (0x4000U) #define NOC_GICD_GICD_CFGID_ChipAffinityLevel_SHIFT (14U) /*! ChipAffinityLevel - ChipAffinityLevel */ #define NOC_GICD_GICD_CFGID_ChipAffinityLevel(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_ChipAffinityLevel_SHIFT)) & NOC_GICD_GICD_CFGID_ChipAffinityLevel_MASK) #define NOC_GICD_GICD_CFGID_SPIGroups_MASK (0x1F8000U) #define NOC_GICD_GICD_CFGID_SPIGroups_SHIFT (15U) /*! SPIGroups - SPIGroups */ #define NOC_GICD_GICD_CFGID_SPIGroups(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_SPIGroups_SHIFT)) & NOC_GICD_GICD_CFGID_SPIGroups_MASK) #define NOC_GICD_GICD_CFGID_LocalChipAddressing_MASK (0x200000U) #define NOC_GICD_GICD_CFGID_LocalChipAddressing_SHIFT (21U) /*! LocalChipAddressing - LocalChipAddressing */ #define NOC_GICD_GICD_CFGID_LocalChipAddressing(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_LocalChipAddressing_SHIFT)) & NOC_GICD_GICD_CFGID_LocalChipAddressing_MASK) #define NOC_GICD_GICD_CFGID_RESERVED1_MASK (0xC00000U) #define NOC_GICD_GICD_CFGID_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_CFGID_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_RESERVED1_SHIFT)) & NOC_GICD_GICD_CFGID_RESERVED1_MASK) #define NOC_GICD_GICD_CFGID_RDCollapseSupport_MASK (0x1000000U) #define NOC_GICD_GICD_CFGID_RDCollapseSupport_SHIFT (24U) /*! RDCollapseSupport - RDCollapseSupport */ #define NOC_GICD_GICD_CFGID_RDCollapseSupport(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_RDCollapseSupport_SHIFT)) & NOC_GICD_GICD_CFGID_RDCollapseSupport_MASK) #define NOC_GICD_GICD_CFGID_ExtendedITSSupport_MASK (0x2000000U) #define NOC_GICD_GICD_CFGID_ExtendedITSSupport_SHIFT (25U) /*! ExtendedITSSupport - ExtendedITSSupport */ #define NOC_GICD_GICD_CFGID_ExtendedITSSupport(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_ExtendedITSSupport_SHIFT)) & NOC_GICD_GICD_CFGID_ExtendedITSSupport_MASK) #define NOC_GICD_GICD_CFGID_RESERVED2_MASK (0xC000000U) #define NOC_GICD_GICD_CFGID_RESERVED2_SHIFT (26U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICD_GICD_CFGID_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_RESERVED2_SHIFT)) & NOC_GICD_GICD_CFGID_RESERVED2_MASK) #define NOC_GICD_GICD_CFGID_Chips_MASK (0xF0000000U) #define NOC_GICD_GICD_CFGID_Chips_SHIFT (28U) /*! Chips - Chips */ #define NOC_GICD_GICD_CFGID_Chips(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_Chips_SHIFT)) & NOC_GICD_GICD_CFGID_Chips_MASK) #define NOC_GICD_GICD_CFGID_Affinity0Bits_MASK (0xF00000000U) #define NOC_GICD_GICD_CFGID_Affinity0Bits_SHIFT (32U) /*! Affinity0Bits - Affinity0Bits */ #define NOC_GICD_GICD_CFGID_Affinity0Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_Affinity0Bits_SHIFT)) & NOC_GICD_GICD_CFGID_Affinity0Bits_MASK) #define NOC_GICD_GICD_CFGID_Affinity1Bits_MASK (0xF000000000U) #define NOC_GICD_GICD_CFGID_Affinity1Bits_SHIFT (36U) /*! Affinity1Bits - Affinity1Bits */ #define NOC_GICD_GICD_CFGID_Affinity1Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_Affinity1Bits_SHIFT)) & NOC_GICD_GICD_CFGID_Affinity1Bits_MASK) #define NOC_GICD_GICD_CFGID_Affinity2Bits_MASK (0xF0000000000U) #define NOC_GICD_GICD_CFGID_Affinity2Bits_SHIFT (40U) /*! Affinity2Bits - Affinity2Bits */ #define NOC_GICD_GICD_CFGID_Affinity2Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_Affinity2Bits_SHIFT)) & NOC_GICD_GICD_CFGID_Affinity2Bits_MASK) #define NOC_GICD_GICD_CFGID_Affinity3Bits_MASK (0xF00000000000U) #define NOC_GICD_GICD_CFGID_Affinity3Bits_SHIFT (44U) /*! Affinity3Bits - Affinity3Bits */ #define NOC_GICD_GICD_CFGID_Affinity3Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_Affinity3Bits_SHIFT)) & NOC_GICD_GICD_CFGID_Affinity3Bits_MASK) #define NOC_GICD_GICD_CFGID_PEwidth_MASK (0x1F000000000000U) #define NOC_GICD_GICD_CFGID_PEwidth_SHIFT (48U) /*! PEwidth - PEwidth */ #define NOC_GICD_GICD_CFGID_PEwidth(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_PEwidth_SHIFT)) & NOC_GICD_GICD_CFGID_PEwidth_MASK) #define NOC_GICD_GICD_CFGID_RESERVED3_MASK (0xFFE0000000000000U) #define NOC_GICD_GICD_CFGID_RESERVED3_SHIFT (53U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICD_GICD_CFGID_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICD_GICD_CFGID_RESERVED3_SHIFT)) & NOC_GICD_GICD_CFGID_RESERVED3_MASK) /*! @} */ /*! @name GICD_PIDR4 - GICD_PIDR4 */ /*! @{ */ #define NOC_GICD_GICD_PIDR4_DES_2_MASK (0xFU) #define NOC_GICD_GICD_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICD_GICD_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR4_DES_2_SHIFT)) & NOC_GICD_GICD_PIDR4_DES_2_MASK) #define NOC_GICD_GICD_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICD_GICD_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICD_GICD_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR4_SIZE_SHIFT)) & NOC_GICD_GICD_PIDR4_SIZE_MASK) #define NOC_GICD_GICD_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR4_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICD_PIDR5 - GICD_PIDR5 */ /*! @{ */ #define NOC_GICD_GICD_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICD_GICD_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICD_GICD_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR5_RESERVED_SHIFT)) & NOC_GICD_GICD_PIDR5_RESERVED_MASK) #define NOC_GICD_GICD_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR5_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICD_PIDR6 - GICD_PIDR6 */ /*! @{ */ #define NOC_GICD_GICD_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICD_GICD_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICD_GICD_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR6_RESERVED_SHIFT)) & NOC_GICD_GICD_PIDR6_RESERVED_MASK) #define NOC_GICD_GICD_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR6_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICD_PIDR7 - GICD_PIDR7 */ /*! @{ */ #define NOC_GICD_GICD_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICD_GICD_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICD_GICD_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR7_RESERVED_SHIFT)) & NOC_GICD_GICD_PIDR7_RESERVED_MASK) #define NOC_GICD_GICD_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR7_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICD_PIDR0 - GICD_PIDR0 */ /*! @{ */ #define NOC_GICD_GICD_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICD_GICD_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICD_GICD_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR0_PART_0_SHIFT)) & NOC_GICD_GICD_PIDR0_PART_0_MASK) #define NOC_GICD_GICD_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR0_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICD_PIDR1 - GICD_PIDR1 */ /*! @{ */ #define NOC_GICD_GICD_PIDR1_PART_1_MASK (0xFU) #define NOC_GICD_GICD_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICD_GICD_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR1_PART_1_SHIFT)) & NOC_GICD_GICD_PIDR1_PART_1_MASK) #define NOC_GICD_GICD_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICD_GICD_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICD_GICD_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR1_DES_0_SHIFT)) & NOC_GICD_GICD_PIDR1_DES_0_MASK) #define NOC_GICD_GICD_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR1_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICD_PIDR2 - GICD_PIDR2 */ /*! @{ */ #define NOC_GICD_GICD_PIDR2_DES_1_MASK (0x7U) #define NOC_GICD_GICD_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICD_GICD_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR2_DES_1_SHIFT)) & NOC_GICD_GICD_PIDR2_DES_1_MASK) #define NOC_GICD_GICD_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICD_GICD_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICD_GICD_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR2_JEDEC_SHIFT)) & NOC_GICD_GICD_PIDR2_JEDEC_MASK) #define NOC_GICD_GICD_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICD_GICD_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICD_GICD_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR2_REVISION_SHIFT)) & NOC_GICD_GICD_PIDR2_REVISION_MASK) #define NOC_GICD_GICD_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR2_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICD_PIDR3 - GICD_PIDR3 */ /*! @{ */ #define NOC_GICD_GICD_PIDR3_CMOD_MASK (0x7U) #define NOC_GICD_GICD_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICD_GICD_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR3_CMOD_SHIFT)) & NOC_GICD_GICD_PIDR3_CMOD_MASK) #define NOC_GICD_GICD_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICD_GICD_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR3_RESERVED0_SHIFT)) & NOC_GICD_GICD_PIDR3_RESERVED0_MASK) #define NOC_GICD_GICD_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICD_GICD_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICD_GICD_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR3_REVAND_SHIFT)) & NOC_GICD_GICD_PIDR3_REVAND_MASK) #define NOC_GICD_GICD_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICD_GICD_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_PIDR3_RESERVED1_SHIFT)) & NOC_GICD_GICD_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICD_CIDR0 - GICD_CIDR0 */ /*! @{ */ #define NOC_GICD_GICD_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICD_GICD_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICD_GICD_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR0_PRMBL_0_SHIFT)) & NOC_GICD_GICD_CIDR0_PRMBL_0_MASK) #define NOC_GICD_GICD_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR0_RESERVED0_SHIFT)) & NOC_GICD_GICD_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICD_CIDR1 - GICD_CIDR1 */ /*! @{ */ #define NOC_GICD_GICD_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICD_GICD_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICD_GICD_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR1_PRMBL_1_SHIFT)) & NOC_GICD_GICD_CIDR1_PRMBL_1_MASK) #define NOC_GICD_GICD_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICD_GICD_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICD_GICD_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR1_CLASS_SHIFT)) & NOC_GICD_GICD_CIDR1_CLASS_MASK) #define NOC_GICD_GICD_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR1_RESERVED0_SHIFT)) & NOC_GICD_GICD_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICD_CIDR2 - GICD_CIDR2 */ /*! @{ */ #define NOC_GICD_GICD_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICD_GICD_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICD_GICD_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR2_PRMBL_2_SHIFT)) & NOC_GICD_GICD_CIDR2_PRMBL_2_MASK) #define NOC_GICD_GICD_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR2_RESERVED0_SHIFT)) & NOC_GICD_GICD_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICD_CIDR3 - GICD_CIDR3 */ /*! @{ */ #define NOC_GICD_GICD_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICD_GICD_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICD_GICD_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR3_PRMBL_3_SHIFT)) & NOC_GICD_GICD_CIDR3_PRMBL_3_MASK) #define NOC_GICD_GICD_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICD_GICD_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICD_GICD_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICD_GICD_CIDR3_RESERVED0_SHIFT)) & NOC_GICD_GICD_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICD_Register_Masks */ /* NOC_GICD - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICD base address */ #define NOC__GIC__GICD_BASE (0x48000000u) /** Peripheral NOC__GIC__GICD base pointer */ #define NOC__GIC__GICD ((NOC_GICD_Type *)NOC__GIC__GICD_BASE) /** Array initializer of NOC_GICD peripheral base addresses */ #define NOC_GICD_BASE_ADDRS { NOC__GIC__GICD_BASE } /** Array initializer of NOC_GICD peripheral base pointers */ #define NOC_GICD_BASE_PTRS { NOC__GIC__GICD } /*! * @} */ /* end of group NOC_GICD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICDA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICDA_Peripheral_Access_Layer NOC_GICDA Peripheral Access Layer * @{ */ /** NOC_GICDA - Register Layout Typedef */ typedef struct { __IO uint32_t GICDA_CTLR; /**< GICDA_CTLR, offset: 0x0 */ __I uint32_t GICDA_TYPER; /**< GICDA_TYPER, offset: 0x4 */ __I uint32_t GICDA_IIDR; /**< GICDA_IIDR, offset: 0x8 */ __I uint32_t GICDA_TYPER2; /**< GICDA_TYPER2, offset: 0xC */ __I uint32_t GICDA_STATUSR; /**< GICDA_STATUSR, offset: 0x10 */ uint8_t RESERVED_0[12]; __IO uint32_t GICDA_FCTLR; /**< GICDA_FCTLR, offset: 0x20 */ __IO uint32_t GICDA_SAC; /**< GICDA_SAC, offset: 0x24 */ uint8_t RESERVED_1[8]; __IO uint32_t GICDA_FCTLR2; /**< GICDA_FCTLR2, offset: 0x30 */ __IO uint32_t GICDA_UTILR; /**< GICDA_UTILR, offset: 0x34 */ __IO uint32_t GICDA_FCTLR3; /**< GICDA_FCTLR3, offset: 0x38 */ uint8_t RESERVED_2[4]; __O uint32_t GICDA_SETSPI_NSR; /**< GICDA_SETSPI_NSR, offset: 0x40 */ uint8_t RESERVED_3[4]; __O uint32_t GICDA_CLRSPI_NSR; /**< GICDA_CLRSPI_NSR, offset: 0x48 */ uint8_t RESERVED_4[4]; __O uint32_t GICDA_SETSPI_SR; /**< GICDA_SETSPI_SR, offset: 0x50 */ uint8_t RESERVED_5[4]; __O uint32_t GICDA_CLRSPI_SR; /**< GICDA_CLRSPI_SR, offset: 0x58 */ uint8_t RESERVED_6[40]; __IO uint32_t GICDA_IGROUPR1; /**< GICDA_IGROUPR1, offset: 0x84 */ __IO uint32_t GICDA_IGROUPR2; /**< GICDA_IGROUPR2, offset: 0x88 */ __IO uint32_t GICDA_IGROUPR3; /**< GICDA_IGROUPR3, offset: 0x8C */ __IO uint32_t GICDA_IGROUPR4; /**< GICDA_IGROUPR4, offset: 0x90 */ __IO uint32_t GICDA_IGROUPR5; /**< GICDA_IGROUPR5, offset: 0x94 */ __IO uint32_t GICDA_IGROUPR6; /**< GICDA_IGROUPR6, offset: 0x98 */ __IO uint32_t GICDA_IGROUPR7; /**< GICDA_IGROUPR7, offset: 0x9C */ __IO uint32_t GICDA_IGROUPR8; /**< GICDA_IGROUPR8, offset: 0xA0 */ __IO uint32_t GICDA_IGROUPR9; /**< GICDA_IGROUPR9, offset: 0xA4 */ __IO uint32_t GICDA_IGROUPR10; /**< GICDA_IGROUPR10, offset: 0xA8 */ __IO uint32_t GICDA_IGROUPR11; /**< GICDA_IGROUPR11, offset: 0xAC */ __IO uint32_t GICDA_IGROUPR12; /**< GICDA_IGROUPR12, offset: 0xB0 */ uint8_t RESERVED_7[80]; __IO uint32_t GICDA_ISENABLER1; /**< GICDA_ISENABLER1, offset: 0x104 */ __IO uint32_t GICDA_ISENABLER2; /**< GICDA_ISENABLER2, offset: 0x108 */ __IO uint32_t GICDA_ISENABLER3; /**< GICDA_ISENABLER3, offset: 0x10C */ __IO uint32_t GICDA_ISENABLER4; /**< GICDA_ISENABLER4, offset: 0x110 */ __IO uint32_t GICDA_ISENABLER5; /**< GICDA_ISENABLER5, offset: 0x114 */ __IO uint32_t GICDA_ISENABLER6; /**< GICDA_ISENABLER6, offset: 0x118 */ __IO uint32_t GICDA_ISENABLER7; /**< GICDA_ISENABLER7, offset: 0x11C */ __IO uint32_t GICDA_ISENABLER8; /**< GICDA_ISENABLER8, offset: 0x120 */ __IO uint32_t GICDA_ISENABLER9; /**< GICDA_ISENABLER9, offset: 0x124 */ __IO uint32_t GICDA_ISENABLER10; /**< GICDA_ISENABLER10, offset: 0x128 */ __IO uint32_t GICDA_ISENABLER11; /**< GICDA_ISENABLER11, offset: 0x12C */ __IO uint32_t GICDA_ISENABLER12; /**< GICDA_ISENABLER12, offset: 0x130 */ uint8_t RESERVED_8[80]; __IO uint32_t GICDA_ICENABLER1; /**< GICDA_ICENABLER1, offset: 0x184 */ __IO uint32_t GICDA_ICENABLER2; /**< GICDA_ICENABLER2, offset: 0x188 */ __IO uint32_t GICDA_ICENABLER3; /**< GICDA_ICENABLER3, offset: 0x18C */ __IO uint32_t GICDA_ICENABLER4; /**< GICDA_ICENABLER4, offset: 0x190 */ __IO uint32_t GICDA_ICENABLER5; /**< GICDA_ICENABLER5, offset: 0x194 */ __IO uint32_t GICDA_ICENABLER6; /**< GICDA_ICENABLER6, offset: 0x198 */ __IO uint32_t GICDA_ICENABLER7; /**< GICDA_ICENABLER7, offset: 0x19C */ __IO uint32_t GICDA_ICENABLER8; /**< GICDA_ICENABLER8, offset: 0x1A0 */ __IO uint32_t GICDA_ICENABLER9; /**< GICDA_ICENABLER9, offset: 0x1A4 */ __IO uint32_t GICDA_ICENABLER10; /**< GICDA_ICENABLER10, offset: 0x1A8 */ __IO uint32_t GICDA_ICENABLER11; /**< GICDA_ICENABLER11, offset: 0x1AC */ __IO uint32_t GICDA_ICENABLER12; /**< GICDA_ICENABLER12, offset: 0x1B0 */ uint8_t RESERVED_9[80]; __IO uint32_t GICDA_ISPENDR1; /**< GICDA_ISPENDR1, offset: 0x204 */ __IO uint32_t GICDA_ISPENDR2; /**< GICDA_ISPENDR2, offset: 0x208 */ __IO uint32_t GICDA_ISPENDR3; /**< GICDA_ISPENDR3, offset: 0x20C */ __IO uint32_t GICDA_ISPENDR4; /**< GICDA_ISPENDR4, offset: 0x210 */ __IO uint32_t GICDA_ISPENDR5; /**< GICDA_ISPENDR5, offset: 0x214 */ __IO uint32_t GICDA_ISPENDR6; /**< GICDA_ISPENDR6, offset: 0x218 */ __IO uint32_t GICDA_ISPENDR7; /**< GICDA_ISPENDR7, offset: 0x21C */ __IO uint32_t GICDA_ISPENDR8; /**< GICDA_ISPENDR8, offset: 0x220 */ __IO uint32_t GICDA_ISPENDR9; /**< GICDA_ISPENDR9, offset: 0x224 */ __IO uint32_t GICDA_ISPENDR10; /**< GICDA_ISPENDR10, offset: 0x228 */ __IO uint32_t GICDA_ISPENDR11; /**< GICDA_ISPENDR11, offset: 0x22C */ __IO uint32_t GICDA_ISPENDR12; /**< GICDA_ISPENDR12, offset: 0x230 */ uint8_t RESERVED_10[80]; __IO uint32_t GICDA_ICPENDR1; /**< GICDA_ICPENDR1, offset: 0x284 */ __IO uint32_t GICDA_ICPENDR2; /**< GICDA_ICPENDR2, offset: 0x288 */ __IO uint32_t GICDA_ICPENDR3; /**< GICDA_ICPENDR3, offset: 0x28C */ __IO uint32_t GICDA_ICPENDR4; /**< GICDA_ICPENDR4, offset: 0x290 */ __IO uint32_t GICDA_ICPENDR5; /**< GICDA_ICPENDR5, offset: 0x294 */ __IO uint32_t GICDA_ICPENDR6; /**< GICDA_ICPENDR6, offset: 0x298 */ __IO uint32_t GICDA_ICPENDR7; /**< GICDA_ICPENDR7, offset: 0x29C */ __IO uint32_t GICDA_ICPENDR8; /**< GICDA_ICPENDR8, offset: 0x2A0 */ __IO uint32_t GICDA_ICPENDR9; /**< GICDA_ICPENDR9, offset: 0x2A4 */ __IO uint32_t GICDA_ICPENDR10; /**< GICDA_ICPENDR10, offset: 0x2A8 */ __IO uint32_t GICDA_ICPENDR11; /**< GICDA_ICPENDR11, offset: 0x2AC */ __IO uint32_t GICDA_ICPENDR12; /**< GICDA_ICPENDR12, offset: 0x2B0 */ uint8_t RESERVED_11[80]; __IO uint32_t GICDA_ISACTIVER1; /**< GICDA_ISACTIVER1, offset: 0x304 */ __IO uint32_t GICDA_ISACTIVER2; /**< GICDA_ISACTIVER2, offset: 0x308 */ __IO uint32_t GICDA_ISACTIVER3; /**< GICDA_ISACTIVER3, offset: 0x30C */ __IO uint32_t GICDA_ISACTIVER4; /**< GICDA_ISACTIVER4, offset: 0x310 */ __IO uint32_t GICDA_ISACTIVER5; /**< GICDA_ISACTIVER5, offset: 0x314 */ __IO uint32_t GICDA_ISACTIVER6; /**< GICDA_ISACTIVER6, offset: 0x318 */ __IO uint32_t GICDA_ISACTIVER7; /**< GICDA_ISACTIVER7, offset: 0x31C */ __IO uint32_t GICDA_ISACTIVER8; /**< GICDA_ISACTIVER8, offset: 0x320 */ __IO uint32_t GICDA_ISACTIVER9; /**< GICDA_ISACTIVER9, offset: 0x324 */ __IO uint32_t GICDA_ISACTIVER10; /**< GICDA_ISACTIVER10, offset: 0x328 */ __IO uint32_t GICDA_ISACTIVER11; /**< GICDA_ISACTIVER11, offset: 0x32C */ __IO uint32_t GICDA_ISACTIVER12; /**< GICDA_ISACTIVER12, offset: 0x330 */ uint8_t RESERVED_12[80]; __IO uint32_t GICDA_ICACTIVER1; /**< GICDA_ICACTIVER1, offset: 0x384 */ __IO uint32_t GICDA_ICACTIVER2; /**< GICDA_ICACTIVER2, offset: 0x388 */ __IO uint32_t GICDA_ICACTIVER3; /**< GICDA_ICACTIVER3, offset: 0x38C */ __IO uint32_t GICDA_ICACTIVER4; /**< GICDA_ICACTIVER4, offset: 0x390 */ __IO uint32_t GICDA_ICACTIVER5; /**< GICDA_ICACTIVER5, offset: 0x394 */ __IO uint32_t GICDA_ICACTIVER6; /**< GICDA_ICACTIVER6, offset: 0x398 */ __IO uint32_t GICDA_ICACTIVER7; /**< GICDA_ICACTIVER7, offset: 0x39C */ __IO uint32_t GICDA_ICACTIVER8; /**< GICDA_ICACTIVER8, offset: 0x3A0 */ __IO uint32_t GICDA_ICACTIVER9; /**< GICDA_ICACTIVER9, offset: 0x3A4 */ __IO uint32_t GICDA_ICACTIVER10; /**< GICDA_ICACTIVER10, offset: 0x3A8 */ __IO uint32_t GICDA_ICACTIVER11; /**< GICDA_ICACTIVER11, offset: 0x3AC */ __IO uint32_t GICDA_ICACTIVER12; /**< GICDA_ICACTIVER12, offset: 0x3B0 */ uint8_t RESERVED_13[108]; __IO uint32_t GICDA_IPRIORITYR8; /**< GICDA_IPRIORITYR8, offset: 0x420 */ __IO uint32_t GICDA_IPRIORITYR9; /**< GICDA_IPRIORITYR9, offset: 0x424 */ __IO uint32_t GICDA_IPRIORITYR10; /**< GICDA_IPRIORITYR10, offset: 0x428 */ __IO uint32_t GICDA_IPRIORITYR11; /**< GICDA_IPRIORITYR11, offset: 0x42C */ __IO uint32_t GICDA_IPRIORITYR12; /**< GICDA_IPRIORITYR12, offset: 0x430 */ __IO uint32_t GICDA_IPRIORITYR13; /**< GICDA_IPRIORITYR13, offset: 0x434 */ __IO uint32_t GICDA_IPRIORITYR14; /**< GICDA_IPRIORITYR14, offset: 0x438 */ __IO uint32_t GICDA_IPRIORITYR15; /**< GICDA_IPRIORITYR15, offset: 0x43C */ __IO uint32_t GICDA_IPRIORITYR16; /**< GICDA_IPRIORITYR16, offset: 0x440 */ __IO uint32_t GICDA_IPRIORITYR17; /**< GICDA_IPRIORITYR17, offset: 0x444 */ __IO uint32_t GICDA_IPRIORITYR18; /**< GICDA_IPRIORITYR18, offset: 0x448 */ __IO uint32_t GICDA_IPRIORITYR19; /**< GICDA_IPRIORITYR19, offset: 0x44C */ __IO uint32_t GICDA_IPRIORITYR20; /**< GICDA_IPRIORITYR20, offset: 0x450 */ __IO uint32_t GICDA_IPRIORITYR21; /**< GICDA_IPRIORITYR21, offset: 0x454 */ __IO uint32_t GICDA_IPRIORITYR22; /**< GICDA_IPRIORITYR22, offset: 0x458 */ __IO uint32_t GICDA_IPRIORITYR23; /**< GICDA_IPRIORITYR23, offset: 0x45C */ __IO uint32_t GICDA_IPRIORITYR24; /**< GICDA_IPRIORITYR24, offset: 0x460 */ __IO uint32_t GICDA_IPRIORITYR25; /**< GICDA_IPRIORITYR25, offset: 0x464 */ __IO uint32_t GICDA_IPRIORITYR26; /**< GICDA_IPRIORITYR26, offset: 0x468 */ __IO uint32_t GICDA_IPRIORITYR27; /**< GICDA_IPRIORITYR27, offset: 0x46C */ __IO uint32_t GICDA_IPRIORITYR28; /**< GICDA_IPRIORITYR28, offset: 0x470 */ __IO uint32_t GICDA_IPRIORITYR29; /**< GICDA_IPRIORITYR29, offset: 0x474 */ __IO uint32_t GICDA_IPRIORITYR30; /**< GICDA_IPRIORITYR30, offset: 0x478 */ __IO uint32_t GICDA_IPRIORITYR31; /**< GICDA_IPRIORITYR31, offset: 0x47C */ __IO uint32_t GICDA_IPRIORITYR32; /**< GICDA_IPRIORITYR32, offset: 0x480 */ __IO uint32_t GICDA_IPRIORITYR33; /**< GICDA_IPRIORITYR33, offset: 0x484 */ __IO uint32_t GICDA_IPRIORITYR34; /**< GICDA_IPRIORITYR34, offset: 0x488 */ __IO uint32_t GICDA_IPRIORITYR35; /**< GICDA_IPRIORITYR35, offset: 0x48C */ __IO uint32_t GICDA_IPRIORITYR36; /**< GICDA_IPRIORITYR36, offset: 0x490 */ __IO uint32_t GICDA_IPRIORITYR37; /**< GICDA_IPRIORITYR37, offset: 0x494 */ __IO uint32_t GICDA_IPRIORITYR38; /**< GICDA_IPRIORITYR38, offset: 0x498 */ __IO uint32_t GICDA_IPRIORITYR39; /**< GICDA_IPRIORITYR39, offset: 0x49C */ __IO uint32_t GICDA_IPRIORITYR40; /**< GICDA_IPRIORITYR40, offset: 0x4A0 */ __IO uint32_t GICDA_IPRIORITYR41; /**< GICDA_IPRIORITYR41, offset: 0x4A4 */ __IO uint32_t GICDA_IPRIORITYR42; /**< GICDA_IPRIORITYR42, offset: 0x4A8 */ __IO uint32_t GICDA_IPRIORITYR43; /**< GICDA_IPRIORITYR43, offset: 0x4AC */ __IO uint32_t GICDA_IPRIORITYR44; /**< GICDA_IPRIORITYR44, offset: 0x4B0 */ __IO uint32_t GICDA_IPRIORITYR45; /**< GICDA_IPRIORITYR45, offset: 0x4B4 */ __IO uint32_t GICDA_IPRIORITYR46; /**< GICDA_IPRIORITYR46, offset: 0x4B8 */ __IO uint32_t GICDA_IPRIORITYR47; /**< GICDA_IPRIORITYR47, offset: 0x4BC */ __IO uint32_t GICDA_IPRIORITYR48; /**< GICDA_IPRIORITYR48, offset: 0x4C0 */ __IO uint32_t GICDA_IPRIORITYR49; /**< GICDA_IPRIORITYR49, offset: 0x4C4 */ __IO uint32_t GICDA_IPRIORITYR50; /**< GICDA_IPRIORITYR50, offset: 0x4C8 */ __IO uint32_t GICDA_IPRIORITYR51; /**< GICDA_IPRIORITYR51, offset: 0x4CC */ __IO uint32_t GICDA_IPRIORITYR52; /**< GICDA_IPRIORITYR52, offset: 0x4D0 */ __IO uint32_t GICDA_IPRIORITYR53; /**< GICDA_IPRIORITYR53, offset: 0x4D4 */ __IO uint32_t GICDA_IPRIORITYR54; /**< GICDA_IPRIORITYR54, offset: 0x4D8 */ __IO uint32_t GICDA_IPRIORITYR55; /**< GICDA_IPRIORITYR55, offset: 0x4DC */ __IO uint32_t GICDA_IPRIORITYR56; /**< GICDA_IPRIORITYR56, offset: 0x4E0 */ __IO uint32_t GICDA_IPRIORITYR57; /**< GICDA_IPRIORITYR57, offset: 0x4E4 */ __IO uint32_t GICDA_IPRIORITYR58; /**< GICDA_IPRIORITYR58, offset: 0x4E8 */ __IO uint32_t GICDA_IPRIORITYR59; /**< GICDA_IPRIORITYR59, offset: 0x4EC */ __IO uint32_t GICDA_IPRIORITYR60; /**< GICDA_IPRIORITYR60, offset: 0x4F0 */ __IO uint32_t GICDA_IPRIORITYR61; /**< GICDA_IPRIORITYR61, offset: 0x4F4 */ __IO uint32_t GICDA_IPRIORITYR62; /**< GICDA_IPRIORITYR62, offset: 0x4F8 */ __IO uint32_t GICDA_IPRIORITYR63; /**< GICDA_IPRIORITYR63, offset: 0x4FC */ __IO uint32_t GICDA_IPRIORITYR64; /**< GICDA_IPRIORITYR64, offset: 0x500 */ __IO uint32_t GICDA_IPRIORITYR65; /**< GICDA_IPRIORITYR65, offset: 0x504 */ __IO uint32_t GICDA_IPRIORITYR66; /**< GICDA_IPRIORITYR66, offset: 0x508 */ __IO uint32_t GICDA_IPRIORITYR67; /**< GICDA_IPRIORITYR67, offset: 0x50C */ __IO uint32_t GICDA_IPRIORITYR68; /**< GICDA_IPRIORITYR68, offset: 0x510 */ __IO uint32_t GICDA_IPRIORITYR69; /**< GICDA_IPRIORITYR69, offset: 0x514 */ __IO uint32_t GICDA_IPRIORITYR70; /**< GICDA_IPRIORITYR70, offset: 0x518 */ __IO uint32_t GICDA_IPRIORITYR71; /**< GICDA_IPRIORITYR71, offset: 0x51C */ __IO uint32_t GICDA_IPRIORITYR72; /**< GICDA_IPRIORITYR72, offset: 0x520 */ __IO uint32_t GICDA_IPRIORITYR73; /**< GICDA_IPRIORITYR73, offset: 0x524 */ __IO uint32_t GICDA_IPRIORITYR74; /**< GICDA_IPRIORITYR74, offset: 0x528 */ __IO uint32_t GICDA_IPRIORITYR75; /**< GICDA_IPRIORITYR75, offset: 0x52C */ __IO uint32_t GICDA_IPRIORITYR76; /**< GICDA_IPRIORITYR76, offset: 0x530 */ __IO uint32_t GICDA_IPRIORITYR77; /**< GICDA_IPRIORITYR77, offset: 0x534 */ __IO uint32_t GICDA_IPRIORITYR78; /**< GICDA_IPRIORITYR78, offset: 0x538 */ __IO uint32_t GICDA_IPRIORITYR79; /**< GICDA_IPRIORITYR79, offset: 0x53C */ __IO uint32_t GICDA_IPRIORITYR80; /**< GICDA_IPRIORITYR80, offset: 0x540 */ __IO uint32_t GICDA_IPRIORITYR81; /**< GICDA_IPRIORITYR81, offset: 0x544 */ __IO uint32_t GICDA_IPRIORITYR82; /**< GICDA_IPRIORITYR82, offset: 0x548 */ __IO uint32_t GICDA_IPRIORITYR83; /**< GICDA_IPRIORITYR83, offset: 0x54C */ __IO uint32_t GICDA_IPRIORITYR84; /**< GICDA_IPRIORITYR84, offset: 0x550 */ __IO uint32_t GICDA_IPRIORITYR85; /**< GICDA_IPRIORITYR85, offset: 0x554 */ __IO uint32_t GICDA_IPRIORITYR86; /**< GICDA_IPRIORITYR86, offset: 0x558 */ __IO uint32_t GICDA_IPRIORITYR87; /**< GICDA_IPRIORITYR87, offset: 0x55C */ __IO uint32_t GICDA_IPRIORITYR88; /**< GICDA_IPRIORITYR88, offset: 0x560 */ __IO uint32_t GICDA_IPRIORITYR89; /**< GICDA_IPRIORITYR89, offset: 0x564 */ __IO uint32_t GICDA_IPRIORITYR90; /**< GICDA_IPRIORITYR90, offset: 0x568 */ __IO uint32_t GICDA_IPRIORITYR91; /**< GICDA_IPRIORITYR91, offset: 0x56C */ __IO uint32_t GICDA_IPRIORITYR92; /**< GICDA_IPRIORITYR92, offset: 0x570 */ __IO uint32_t GICDA_IPRIORITYR93; /**< GICDA_IPRIORITYR93, offset: 0x574 */ __IO uint32_t GICDA_IPRIORITYR94; /**< GICDA_IPRIORITYR94, offset: 0x578 */ __IO uint32_t GICDA_IPRIORITYR95; /**< GICDA_IPRIORITYR95, offset: 0x57C */ __IO uint32_t GICDA_IPRIORITYR96; /**< GICDA_IPRIORITYR96, offset: 0x580 */ __IO uint32_t GICDA_IPRIORITYR97; /**< GICDA_IPRIORITYR97, offset: 0x584 */ __IO uint32_t GICDA_IPRIORITYR98; /**< GICDA_IPRIORITYR98, offset: 0x588 */ __IO uint32_t GICDA_IPRIORITYR99; /**< GICDA_IPRIORITYR99, offset: 0x58C */ __IO uint32_t GICDA_IPRIORITYR100; /**< GICDA_IPRIORITYR100, offset: 0x590 */ __IO uint32_t GICDA_IPRIORITYR101; /**< GICDA_IPRIORITYR101, offset: 0x594 */ __IO uint32_t GICDA_IPRIORITYR102; /**< GICDA_IPRIORITYR102, offset: 0x598 */ __IO uint32_t GICDA_IPRIORITYR103; /**< GICDA_IPRIORITYR103, offset: 0x59C */ uint8_t RESERVED_14[1640]; __IO uint32_t GICDA_ICFGR2; /**< GICDA_ICFGR2, offset: 0xC08 */ __IO uint32_t GICDA_ICFGR3; /**< GICDA_ICFGR3, offset: 0xC0C */ __IO uint32_t GICDA_ICFGR4; /**< GICDA_ICFGR4, offset: 0xC10 */ __IO uint32_t GICDA_ICFGR5; /**< GICDA_ICFGR5, offset: 0xC14 */ __IO uint32_t GICDA_ICFGR6; /**< GICDA_ICFGR6, offset: 0xC18 */ __IO uint32_t GICDA_ICFGR7; /**< GICDA_ICFGR7, offset: 0xC1C */ __IO uint32_t GICDA_ICFGR8; /**< GICDA_ICFGR8, offset: 0xC20 */ __IO uint32_t GICDA_ICFGR9; /**< GICDA_ICFGR9, offset: 0xC24 */ __IO uint32_t GICDA_ICFGR10; /**< GICDA_ICFGR10, offset: 0xC28 */ __IO uint32_t GICDA_ICFGR11; /**< GICDA_ICFGR11, offset: 0xC2C */ __IO uint32_t GICDA_ICFGR12; /**< GICDA_ICFGR12, offset: 0xC30 */ __IO uint32_t GICDA_ICFGR13; /**< GICDA_ICFGR13, offset: 0xC34 */ __IO uint32_t GICDA_ICFGR14; /**< GICDA_ICFGR14, offset: 0xC38 */ __IO uint32_t GICDA_ICFGR15; /**< GICDA_ICFGR15, offset: 0xC3C */ __IO uint32_t GICDA_ICFGR16; /**< GICDA_ICFGR16, offset: 0xC40 */ __IO uint32_t GICDA_ICFGR17; /**< GICDA_ICFGR17, offset: 0xC44 */ __IO uint32_t GICDA_ICFGR18; /**< GICDA_ICFGR18, offset: 0xC48 */ __IO uint32_t GICDA_ICFGR19; /**< GICDA_ICFGR19, offset: 0xC4C */ __IO uint32_t GICDA_ICFGR20; /**< GICDA_ICFGR20, offset: 0xC50 */ __IO uint32_t GICDA_ICFGR21; /**< GICDA_ICFGR21, offset: 0xC54 */ __IO uint32_t GICDA_ICFGR22; /**< GICDA_ICFGR22, offset: 0xC58 */ __IO uint32_t GICDA_ICFGR23; /**< GICDA_ICFGR23, offset: 0xC5C */ __IO uint32_t GICDA_ICFGR24; /**< GICDA_ICFGR24, offset: 0xC60 */ __IO uint32_t GICDA_ICFGR25; /**< GICDA_ICFGR25, offset: 0xC64 */ uint8_t RESERVED_15[156]; __IO uint32_t GICDA_IGRPMODR1; /**< GICDA_IGRPMODR1, offset: 0xD04 */ __IO uint32_t GICDA_IGRPMODR2; /**< GICDA_IGRPMODR2, offset: 0xD08 */ __IO uint32_t GICDA_IGRPMODR3; /**< GICDA_IGRPMODR3, offset: 0xD0C */ __IO uint32_t GICDA_IGRPMODR4; /**< GICDA_IGRPMODR4, offset: 0xD10 */ __IO uint32_t GICDA_IGRPMODR5; /**< GICDA_IGRPMODR5, offset: 0xD14 */ __IO uint32_t GICDA_IGRPMODR6; /**< GICDA_IGRPMODR6, offset: 0xD18 */ __IO uint32_t GICDA_IGRPMODR7; /**< GICDA_IGRPMODR7, offset: 0xD1C */ __IO uint32_t GICDA_IGRPMODR8; /**< GICDA_IGRPMODR8, offset: 0xD20 */ __IO uint32_t GICDA_IGRPMODR9; /**< GICDA_IGRPMODR9, offset: 0xD24 */ __IO uint32_t GICDA_IGRPMODR10; /**< GICDA_IGRPMODR10, offset: 0xD28 */ __IO uint32_t GICDA_IGRPMODR11; /**< GICDA_IGRPMODR11, offset: 0xD2C */ __IO uint32_t GICDA_IGRPMODR12; /**< GICDA_IGRPMODR12, offset: 0xD30 */ uint8_t RESERVED_16[212]; __IO uint32_t GICDA_NSACR2; /**< GICDA_NSACR2, offset: 0xE08 */ __IO uint32_t GICDA_NSACR3; /**< GICDA_NSACR3, offset: 0xE0C */ __IO uint32_t GICDA_NSACR4; /**< GICDA_NSACR4, offset: 0xE10 */ __IO uint32_t GICDA_NSACR5; /**< GICDA_NSACR5, offset: 0xE14 */ __IO uint32_t GICDA_NSACR6; /**< GICDA_NSACR6, offset: 0xE18 */ __IO uint32_t GICDA_NSACR7; /**< GICDA_NSACR7, offset: 0xE1C */ __IO uint32_t GICDA_NSACR8; /**< GICDA_NSACR8, offset: 0xE20 */ __IO uint32_t GICDA_NSACR9; /**< GICDA_NSACR9, offset: 0xE24 */ __IO uint32_t GICDA_NSACR10; /**< GICDA_NSACR10, offset: 0xE28 */ __IO uint32_t GICDA_NSACR11; /**< GICDA_NSACR11, offset: 0xE2C */ __IO uint32_t GICDA_NSACR12; /**< GICDA_NSACR12, offset: 0xE30 */ __IO uint32_t GICDA_NSACR13; /**< GICDA_NSACR13, offset: 0xE34 */ __IO uint32_t GICDA_NSACR14; /**< GICDA_NSACR14, offset: 0xE38 */ __IO uint32_t GICDA_NSACR15; /**< GICDA_NSACR15, offset: 0xE3C */ __IO uint32_t GICDA_NSACR16; /**< GICDA_NSACR16, offset: 0xE40 */ __IO uint32_t GICDA_NSACR17; /**< GICDA_NSACR17, offset: 0xE44 */ __IO uint32_t GICDA_NSACR18; /**< GICDA_NSACR18, offset: 0xE48 */ __IO uint32_t GICDA_NSACR19; /**< GICDA_NSACR19, offset: 0xE4C */ __IO uint32_t GICDA_NSACR20; /**< GICDA_NSACR20, offset: 0xE50 */ __IO uint32_t GICDA_NSACR21; /**< GICDA_NSACR21, offset: 0xE54 */ __IO uint32_t GICDA_NSACR22; /**< GICDA_NSACR22, offset: 0xE58 */ __IO uint32_t GICDA_NSACR23; /**< GICDA_NSACR23, offset: 0xE5C */ __IO uint32_t GICDA_NSACR24; /**< GICDA_NSACR24, offset: 0xE60 */ __IO uint32_t GICDA_NSACR25; /**< GICDA_NSACR25, offset: 0xE64 */ uint8_t RESERVED_17[21144]; __IO uint64_t GICDA_IROUTER32; /**< GICDA_IROUTER32, offset: 0x6100 */ __IO uint64_t GICDA_IROUTER33; /**< GICDA_IROUTER33, offset: 0x6108 */ __IO uint64_t GICDA_IROUTER34; /**< GICDA_IROUTER34, offset: 0x6110 */ __IO uint64_t GICDA_IROUTER35; /**< GICDA_IROUTER35, offset: 0x6118 */ __IO uint64_t GICDA_IROUTER36; /**< GICDA_IROUTER36, offset: 0x6120 */ __IO uint64_t GICDA_IROUTER37; /**< GICDA_IROUTER37, offset: 0x6128 */ __IO uint64_t GICDA_IROUTER38; /**< GICDA_IROUTER38, offset: 0x6130 */ __IO uint64_t GICDA_IROUTER39; /**< GICDA_IROUTER39, offset: 0x6138 */ __IO uint64_t GICDA_IROUTER40; /**< GICDA_IROUTER40, offset: 0x6140 */ __IO uint64_t GICDA_IROUTER41; /**< GICDA_IROUTER41, offset: 0x6148 */ __IO uint64_t GICDA_IROUTER42; /**< GICDA_IROUTER42, offset: 0x6150 */ __IO uint64_t GICDA_IROUTER43; /**< GICDA_IROUTER43, offset: 0x6158 */ __IO uint64_t GICDA_IROUTER44; /**< GICDA_IROUTER44, offset: 0x6160 */ __IO uint64_t GICDA_IROUTER45; /**< GICDA_IROUTER45, offset: 0x6168 */ __IO uint64_t GICDA_IROUTER46; /**< GICDA_IROUTER46, offset: 0x6170 */ __IO uint64_t GICDA_IROUTER47; /**< GICDA_IROUTER47, offset: 0x6178 */ __IO uint64_t GICDA_IROUTER48; /**< GICDA_IROUTER48, offset: 0x6180 */ __IO uint64_t GICDA_IROUTER49; /**< GICDA_IROUTER49, offset: 0x6188 */ __IO uint64_t GICDA_IROUTER50; /**< GICDA_IROUTER50, offset: 0x6190 */ __IO uint64_t GICDA_IROUTER51; /**< GICDA_IROUTER51, offset: 0x6198 */ __IO uint64_t GICDA_IROUTER52; /**< GICDA_IROUTER52, offset: 0x61A0 */ __IO uint64_t GICDA_IROUTER53; /**< GICDA_IROUTER53, offset: 0x61A8 */ __IO uint64_t GICDA_IROUTER54; /**< GICDA_IROUTER54, offset: 0x61B0 */ __IO uint64_t GICDA_IROUTER55; /**< GICDA_IROUTER55, offset: 0x61B8 */ __IO uint64_t GICDA_IROUTER56; /**< GICDA_IROUTER56, offset: 0x61C0 */ __IO uint64_t GICDA_IROUTER57; /**< GICDA_IROUTER57, offset: 0x61C8 */ __IO uint64_t GICDA_IROUTER58; /**< GICDA_IROUTER58, offset: 0x61D0 */ __IO uint64_t GICDA_IROUTER59; /**< GICDA_IROUTER59, offset: 0x61D8 */ __IO uint64_t GICDA_IROUTER60; /**< GICDA_IROUTER60, offset: 0x61E0 */ __IO uint64_t GICDA_IROUTER61; /**< GICDA_IROUTER61, offset: 0x61E8 */ __IO uint64_t GICDA_IROUTER62; /**< GICDA_IROUTER62, offset: 0x61F0 */ __IO uint64_t GICDA_IROUTER63; /**< GICDA_IROUTER63, offset: 0x61F8 */ __IO uint64_t GICDA_IROUTER64; /**< GICDA_IROUTER64, offset: 0x6200 */ __IO uint64_t GICDA_IROUTER65; /**< GICDA_IROUTER65, offset: 0x6208 */ __IO uint64_t GICDA_IROUTER66; /**< GICDA_IROUTER66, offset: 0x6210 */ __IO uint64_t GICDA_IROUTER67; /**< GICDA_IROUTER67, offset: 0x6218 */ __IO uint64_t GICDA_IROUTER68; /**< GICDA_IROUTER68, offset: 0x6220 */ __IO uint64_t GICDA_IROUTER69; /**< GICDA_IROUTER69, offset: 0x6228 */ __IO uint64_t GICDA_IROUTER70; /**< GICDA_IROUTER70, offset: 0x6230 */ __IO uint64_t GICDA_IROUTER71; /**< GICDA_IROUTER71, offset: 0x6238 */ __IO uint64_t GICDA_IROUTER72; /**< GICDA_IROUTER72, offset: 0x6240 */ __IO uint64_t GICDA_IROUTER73; /**< GICDA_IROUTER73, offset: 0x6248 */ __IO uint64_t GICDA_IROUTER74; /**< GICDA_IROUTER74, offset: 0x6250 */ __IO uint64_t GICDA_IROUTER75; /**< GICDA_IROUTER75, offset: 0x6258 */ __IO uint64_t GICDA_IROUTER76; /**< GICDA_IROUTER76, offset: 0x6260 */ __IO uint64_t GICDA_IROUTER77; /**< GICDA_IROUTER77, offset: 0x6268 */ __IO uint64_t GICDA_IROUTER78; /**< GICDA_IROUTER78, offset: 0x6270 */ __IO uint64_t GICDA_IROUTER79; /**< GICDA_IROUTER79, offset: 0x6278 */ __IO uint64_t GICDA_IROUTER80; /**< GICDA_IROUTER80, offset: 0x6280 */ __IO uint64_t GICDA_IROUTER81; /**< GICDA_IROUTER81, offset: 0x6288 */ __IO uint64_t GICDA_IROUTER82; /**< GICDA_IROUTER82, offset: 0x6290 */ __IO uint64_t GICDA_IROUTER83; /**< GICDA_IROUTER83, offset: 0x6298 */ __IO uint64_t GICDA_IROUTER84; /**< GICDA_IROUTER84, offset: 0x62A0 */ __IO uint64_t GICDA_IROUTER85; /**< GICDA_IROUTER85, offset: 0x62A8 */ __IO uint64_t GICDA_IROUTER86; /**< GICDA_IROUTER86, offset: 0x62B0 */ __IO uint64_t GICDA_IROUTER87; /**< GICDA_IROUTER87, offset: 0x62B8 */ __IO uint64_t GICDA_IROUTER88; /**< GICDA_IROUTER88, offset: 0x62C0 */ __IO uint64_t GICDA_IROUTER89; /**< GICDA_IROUTER89, offset: 0x62C8 */ __IO uint64_t GICDA_IROUTER90; /**< GICDA_IROUTER90, offset: 0x62D0 */ __IO uint64_t GICDA_IROUTER91; /**< GICDA_IROUTER91, offset: 0x62D8 */ __IO uint64_t GICDA_IROUTER92; /**< GICDA_IROUTER92, offset: 0x62E0 */ __IO uint64_t GICDA_IROUTER93; /**< GICDA_IROUTER93, offset: 0x62E8 */ __IO uint64_t GICDA_IROUTER94; /**< GICDA_IROUTER94, offset: 0x62F0 */ __IO uint64_t GICDA_IROUTER95; /**< GICDA_IROUTER95, offset: 0x62F8 */ __IO uint64_t GICDA_IROUTER96; /**< GICDA_IROUTER96, offset: 0x6300 */ __IO uint64_t GICDA_IROUTER97; /**< GICDA_IROUTER97, offset: 0x6308 */ __IO uint64_t GICDA_IROUTER98; /**< GICDA_IROUTER98, offset: 0x6310 */ __IO uint64_t GICDA_IROUTER99; /**< GICDA_IROUTER99, offset: 0x6318 */ __IO uint64_t GICDA_IROUTER100; /**< GICDA_IROUTER100, offset: 0x6320 */ __IO uint64_t GICDA_IROUTER101; /**< GICDA_IROUTER101, offset: 0x6328 */ __IO uint64_t GICDA_IROUTER102; /**< GICDA_IROUTER102, offset: 0x6330 */ __IO uint64_t GICDA_IROUTER103; /**< GICDA_IROUTER103, offset: 0x6338 */ __IO uint64_t GICDA_IROUTER104; /**< GICDA_IROUTER104, offset: 0x6340 */ __IO uint64_t GICDA_IROUTER105; /**< GICDA_IROUTER105, offset: 0x6348 */ __IO uint64_t GICDA_IROUTER106; /**< GICDA_IROUTER106, offset: 0x6350 */ __IO uint64_t GICDA_IROUTER107; /**< GICDA_IROUTER107, offset: 0x6358 */ __IO uint64_t GICDA_IROUTER108; /**< GICDA_IROUTER108, offset: 0x6360 */ __IO uint64_t GICDA_IROUTER109; /**< GICDA_IROUTER109, offset: 0x6368 */ __IO uint64_t GICDA_IROUTER110; /**< GICDA_IROUTER110, offset: 0x6370 */ __IO uint64_t GICDA_IROUTER111; /**< GICDA_IROUTER111, offset: 0x6378 */ __IO uint64_t GICDA_IROUTER112; /**< GICDA_IROUTER112, offset: 0x6380 */ __IO uint64_t GICDA_IROUTER113; /**< GICDA_IROUTER113, offset: 0x6388 */ __IO uint64_t GICDA_IROUTER114; /**< GICDA_IROUTER114, offset: 0x6390 */ __IO uint64_t GICDA_IROUTER115; /**< GICDA_IROUTER115, offset: 0x6398 */ __IO uint64_t GICDA_IROUTER116; /**< GICDA_IROUTER116, offset: 0x63A0 */ __IO uint64_t GICDA_IROUTER117; /**< GICDA_IROUTER117, offset: 0x63A8 */ __IO uint64_t GICDA_IROUTER118; /**< GICDA_IROUTER118, offset: 0x63B0 */ __IO uint64_t GICDA_IROUTER119; /**< GICDA_IROUTER119, offset: 0x63B8 */ __IO uint64_t GICDA_IROUTER120; /**< GICDA_IROUTER120, offset: 0x63C0 */ __IO uint64_t GICDA_IROUTER121; /**< GICDA_IROUTER121, offset: 0x63C8 */ __IO uint64_t GICDA_IROUTER122; /**< GICDA_IROUTER122, offset: 0x63D0 */ __IO uint64_t GICDA_IROUTER123; /**< GICDA_IROUTER123, offset: 0x63D8 */ __IO uint64_t GICDA_IROUTER124; /**< GICDA_IROUTER124, offset: 0x63E0 */ __IO uint64_t GICDA_IROUTER125; /**< GICDA_IROUTER125, offset: 0x63E8 */ __IO uint64_t GICDA_IROUTER126; /**< GICDA_IROUTER126, offset: 0x63F0 */ __IO uint64_t GICDA_IROUTER127; /**< GICDA_IROUTER127, offset: 0x63F8 */ __IO uint64_t GICDA_IROUTER128; /**< GICDA_IROUTER128, offset: 0x6400 */ __IO uint64_t GICDA_IROUTER129; /**< GICDA_IROUTER129, offset: 0x6408 */ __IO uint64_t GICDA_IROUTER130; /**< GICDA_IROUTER130, offset: 0x6410 */ __IO uint64_t GICDA_IROUTER131; /**< GICDA_IROUTER131, offset: 0x6418 */ __IO uint64_t GICDA_IROUTER132; /**< GICDA_IROUTER132, offset: 0x6420 */ __IO uint64_t GICDA_IROUTER133; /**< GICDA_IROUTER133, offset: 0x6428 */ __IO uint64_t GICDA_IROUTER134; /**< GICDA_IROUTER134, offset: 0x6430 */ __IO uint64_t GICDA_IROUTER135; /**< GICDA_IROUTER135, offset: 0x6438 */ __IO uint64_t GICDA_IROUTER136; /**< GICDA_IROUTER136, offset: 0x6440 */ __IO uint64_t GICDA_IROUTER137; /**< GICDA_IROUTER137, offset: 0x6448 */ __IO uint64_t GICDA_IROUTER138; /**< GICDA_IROUTER138, offset: 0x6450 */ __IO uint64_t GICDA_IROUTER139; /**< GICDA_IROUTER139, offset: 0x6458 */ __IO uint64_t GICDA_IROUTER140; /**< GICDA_IROUTER140, offset: 0x6460 */ __IO uint64_t GICDA_IROUTER141; /**< GICDA_IROUTER141, offset: 0x6468 */ __IO uint64_t GICDA_IROUTER142; /**< GICDA_IROUTER142, offset: 0x6470 */ __IO uint64_t GICDA_IROUTER143; /**< GICDA_IROUTER143, offset: 0x6478 */ __IO uint64_t GICDA_IROUTER144; /**< GICDA_IROUTER144, offset: 0x6480 */ __IO uint64_t GICDA_IROUTER145; /**< GICDA_IROUTER145, offset: 0x6488 */ __IO uint64_t GICDA_IROUTER146; /**< GICDA_IROUTER146, offset: 0x6490 */ __IO uint64_t GICDA_IROUTER147; /**< GICDA_IROUTER147, offset: 0x6498 */ __IO uint64_t GICDA_IROUTER148; /**< GICDA_IROUTER148, offset: 0x64A0 */ __IO uint64_t GICDA_IROUTER149; /**< GICDA_IROUTER149, offset: 0x64A8 */ __IO uint64_t GICDA_IROUTER150; /**< GICDA_IROUTER150, offset: 0x64B0 */ __IO uint64_t GICDA_IROUTER151; /**< GICDA_IROUTER151, offset: 0x64B8 */ __IO uint64_t GICDA_IROUTER152; /**< GICDA_IROUTER152, offset: 0x64C0 */ __IO uint64_t GICDA_IROUTER153; /**< GICDA_IROUTER153, offset: 0x64C8 */ __IO uint64_t GICDA_IROUTER154; /**< GICDA_IROUTER154, offset: 0x64D0 */ __IO uint64_t GICDA_IROUTER155; /**< GICDA_IROUTER155, offset: 0x64D8 */ __IO uint64_t GICDA_IROUTER156; /**< GICDA_IROUTER156, offset: 0x64E0 */ __IO uint64_t GICDA_IROUTER157; /**< GICDA_IROUTER157, offset: 0x64E8 */ __IO uint64_t GICDA_IROUTER158; /**< GICDA_IROUTER158, offset: 0x64F0 */ __IO uint64_t GICDA_IROUTER159; /**< GICDA_IROUTER159, offset: 0x64F8 */ __IO uint64_t GICDA_IROUTER160; /**< GICDA_IROUTER160, offset: 0x6500 */ __IO uint64_t GICDA_IROUTER161; /**< GICDA_IROUTER161, offset: 0x6508 */ __IO uint64_t GICDA_IROUTER162; /**< GICDA_IROUTER162, offset: 0x6510 */ __IO uint64_t GICDA_IROUTER163; /**< GICDA_IROUTER163, offset: 0x6518 */ __IO uint64_t GICDA_IROUTER164; /**< GICDA_IROUTER164, offset: 0x6520 */ __IO uint64_t GICDA_IROUTER165; /**< GICDA_IROUTER165, offset: 0x6528 */ __IO uint64_t GICDA_IROUTER166; /**< GICDA_IROUTER166, offset: 0x6530 */ __IO uint64_t GICDA_IROUTER167; /**< GICDA_IROUTER167, offset: 0x6538 */ __IO uint64_t GICDA_IROUTER168; /**< GICDA_IROUTER168, offset: 0x6540 */ __IO uint64_t GICDA_IROUTER169; /**< GICDA_IROUTER169, offset: 0x6548 */ __IO uint64_t GICDA_IROUTER170; /**< GICDA_IROUTER170, offset: 0x6550 */ __IO uint64_t GICDA_IROUTER171; /**< GICDA_IROUTER171, offset: 0x6558 */ __IO uint64_t GICDA_IROUTER172; /**< GICDA_IROUTER172, offset: 0x6560 */ __IO uint64_t GICDA_IROUTER173; /**< GICDA_IROUTER173, offset: 0x6568 */ __IO uint64_t GICDA_IROUTER174; /**< GICDA_IROUTER174, offset: 0x6570 */ __IO uint64_t GICDA_IROUTER175; /**< GICDA_IROUTER175, offset: 0x6578 */ __IO uint64_t GICDA_IROUTER176; /**< GICDA_IROUTER176, offset: 0x6580 */ __IO uint64_t GICDA_IROUTER177; /**< GICDA_IROUTER177, offset: 0x6588 */ __IO uint64_t GICDA_IROUTER178; /**< GICDA_IROUTER178, offset: 0x6590 */ __IO uint64_t GICDA_IROUTER179; /**< GICDA_IROUTER179, offset: 0x6598 */ __IO uint64_t GICDA_IROUTER180; /**< GICDA_IROUTER180, offset: 0x65A0 */ __IO uint64_t GICDA_IROUTER181; /**< GICDA_IROUTER181, offset: 0x65A8 */ __IO uint64_t GICDA_IROUTER182; /**< GICDA_IROUTER182, offset: 0x65B0 */ __IO uint64_t GICDA_IROUTER183; /**< GICDA_IROUTER183, offset: 0x65B8 */ __IO uint64_t GICDA_IROUTER184; /**< GICDA_IROUTER184, offset: 0x65C0 */ __IO uint64_t GICDA_IROUTER185; /**< GICDA_IROUTER185, offset: 0x65C8 */ __IO uint64_t GICDA_IROUTER186; /**< GICDA_IROUTER186, offset: 0x65D0 */ __IO uint64_t GICDA_IROUTER187; /**< GICDA_IROUTER187, offset: 0x65D8 */ __IO uint64_t GICDA_IROUTER188; /**< GICDA_IROUTER188, offset: 0x65E0 */ __IO uint64_t GICDA_IROUTER189; /**< GICDA_IROUTER189, offset: 0x65E8 */ __IO uint64_t GICDA_IROUTER190; /**< GICDA_IROUTER190, offset: 0x65F0 */ __IO uint64_t GICDA_IROUTER191; /**< GICDA_IROUTER191, offset: 0x65F8 */ __IO uint64_t GICDA_IROUTER192; /**< GICDA_IROUTER192, offset: 0x6600 */ __IO uint64_t GICDA_IROUTER193; /**< GICDA_IROUTER193, offset: 0x6608 */ __IO uint64_t GICDA_IROUTER194; /**< GICDA_IROUTER194, offset: 0x6610 */ __IO uint64_t GICDA_IROUTER195; /**< GICDA_IROUTER195, offset: 0x6618 */ __IO uint64_t GICDA_IROUTER196; /**< GICDA_IROUTER196, offset: 0x6620 */ __IO uint64_t GICDA_IROUTER197; /**< GICDA_IROUTER197, offset: 0x6628 */ __IO uint64_t GICDA_IROUTER198; /**< GICDA_IROUTER198, offset: 0x6630 */ __IO uint64_t GICDA_IROUTER199; /**< GICDA_IROUTER199, offset: 0x6638 */ __IO uint64_t GICDA_IROUTER200; /**< GICDA_IROUTER200, offset: 0x6640 */ __IO uint64_t GICDA_IROUTER201; /**< GICDA_IROUTER201, offset: 0x6648 */ __IO uint64_t GICDA_IROUTER202; /**< GICDA_IROUTER202, offset: 0x6650 */ __IO uint64_t GICDA_IROUTER203; /**< GICDA_IROUTER203, offset: 0x6658 */ __IO uint64_t GICDA_IROUTER204; /**< GICDA_IROUTER204, offset: 0x6660 */ __IO uint64_t GICDA_IROUTER205; /**< GICDA_IROUTER205, offset: 0x6668 */ __IO uint64_t GICDA_IROUTER206; /**< GICDA_IROUTER206, offset: 0x6670 */ __IO uint64_t GICDA_IROUTER207; /**< GICDA_IROUTER207, offset: 0x6678 */ __IO uint64_t GICDA_IROUTER208; /**< GICDA_IROUTER208, offset: 0x6680 */ __IO uint64_t GICDA_IROUTER209; /**< GICDA_IROUTER209, offset: 0x6688 */ __IO uint64_t GICDA_IROUTER210; /**< GICDA_IROUTER210, offset: 0x6690 */ __IO uint64_t GICDA_IROUTER211; /**< GICDA_IROUTER211, offset: 0x6698 */ __IO uint64_t GICDA_IROUTER212; /**< GICDA_IROUTER212, offset: 0x66A0 */ __IO uint64_t GICDA_IROUTER213; /**< GICDA_IROUTER213, offset: 0x66A8 */ __IO uint64_t GICDA_IROUTER214; /**< GICDA_IROUTER214, offset: 0x66B0 */ __IO uint64_t GICDA_IROUTER215; /**< GICDA_IROUTER215, offset: 0x66B8 */ __IO uint64_t GICDA_IROUTER216; /**< GICDA_IROUTER216, offset: 0x66C0 */ __IO uint64_t GICDA_IROUTER217; /**< GICDA_IROUTER217, offset: 0x66C8 */ __IO uint64_t GICDA_IROUTER218; /**< GICDA_IROUTER218, offset: 0x66D0 */ __IO uint64_t GICDA_IROUTER219; /**< GICDA_IROUTER219, offset: 0x66D8 */ __IO uint64_t GICDA_IROUTER220; /**< GICDA_IROUTER220, offset: 0x66E0 */ __IO uint64_t GICDA_IROUTER221; /**< GICDA_IROUTER221, offset: 0x66E8 */ __IO uint64_t GICDA_IROUTER222; /**< GICDA_IROUTER222, offset: 0x66F0 */ __IO uint64_t GICDA_IROUTER223; /**< GICDA_IROUTER223, offset: 0x66F8 */ __IO uint64_t GICDA_IROUTER224; /**< GICDA_IROUTER224, offset: 0x6700 */ __IO uint64_t GICDA_IROUTER225; /**< GICDA_IROUTER225, offset: 0x6708 */ __IO uint64_t GICDA_IROUTER226; /**< GICDA_IROUTER226, offset: 0x6710 */ __IO uint64_t GICDA_IROUTER227; /**< GICDA_IROUTER227, offset: 0x6718 */ __IO uint64_t GICDA_IROUTER228; /**< GICDA_IROUTER228, offset: 0x6720 */ __IO uint64_t GICDA_IROUTER229; /**< GICDA_IROUTER229, offset: 0x6728 */ __IO uint64_t GICDA_IROUTER230; /**< GICDA_IROUTER230, offset: 0x6730 */ __IO uint64_t GICDA_IROUTER231; /**< GICDA_IROUTER231, offset: 0x6738 */ __IO uint64_t GICDA_IROUTER232; /**< GICDA_IROUTER232, offset: 0x6740 */ __IO uint64_t GICDA_IROUTER233; /**< GICDA_IROUTER233, offset: 0x6748 */ __IO uint64_t GICDA_IROUTER234; /**< GICDA_IROUTER234, offset: 0x6750 */ __IO uint64_t GICDA_IROUTER235; /**< GICDA_IROUTER235, offset: 0x6758 */ __IO uint64_t GICDA_IROUTER236; /**< GICDA_IROUTER236, offset: 0x6760 */ __IO uint64_t GICDA_IROUTER237; /**< GICDA_IROUTER237, offset: 0x6768 */ __IO uint64_t GICDA_IROUTER238; /**< GICDA_IROUTER238, offset: 0x6770 */ __IO uint64_t GICDA_IROUTER239; /**< GICDA_IROUTER239, offset: 0x6778 */ __IO uint64_t GICDA_IROUTER240; /**< GICDA_IROUTER240, offset: 0x6780 */ __IO uint64_t GICDA_IROUTER241; /**< GICDA_IROUTER241, offset: 0x6788 */ __IO uint64_t GICDA_IROUTER242; /**< GICDA_IROUTER242, offset: 0x6790 */ __IO uint64_t GICDA_IROUTER243; /**< GICDA_IROUTER243, offset: 0x6798 */ __IO uint64_t GICDA_IROUTER244; /**< GICDA_IROUTER244, offset: 0x67A0 */ __IO uint64_t GICDA_IROUTER245; /**< GICDA_IROUTER245, offset: 0x67A8 */ __IO uint64_t GICDA_IROUTER246; /**< GICDA_IROUTER246, offset: 0x67B0 */ __IO uint64_t GICDA_IROUTER247; /**< GICDA_IROUTER247, offset: 0x67B8 */ __IO uint64_t GICDA_IROUTER248; /**< GICDA_IROUTER248, offset: 0x67C0 */ __IO uint64_t GICDA_IROUTER249; /**< GICDA_IROUTER249, offset: 0x67C8 */ __IO uint64_t GICDA_IROUTER250; /**< GICDA_IROUTER250, offset: 0x67D0 */ __IO uint64_t GICDA_IROUTER251; /**< GICDA_IROUTER251, offset: 0x67D8 */ __IO uint64_t GICDA_IROUTER252; /**< GICDA_IROUTER252, offset: 0x67E0 */ __IO uint64_t GICDA_IROUTER253; /**< GICDA_IROUTER253, offset: 0x67E8 */ __IO uint64_t GICDA_IROUTER254; /**< GICDA_IROUTER254, offset: 0x67F0 */ __IO uint64_t GICDA_IROUTER255; /**< GICDA_IROUTER255, offset: 0x67F8 */ __IO uint64_t GICDA_IROUTER256; /**< GICDA_IROUTER256, offset: 0x6800 */ __IO uint64_t GICDA_IROUTER257; /**< GICDA_IROUTER257, offset: 0x6808 */ __IO uint64_t GICDA_IROUTER258; /**< GICDA_IROUTER258, offset: 0x6810 */ __IO uint64_t GICDA_IROUTER259; /**< GICDA_IROUTER259, offset: 0x6818 */ __IO uint64_t GICDA_IROUTER260; /**< GICDA_IROUTER260, offset: 0x6820 */ __IO uint64_t GICDA_IROUTER261; /**< GICDA_IROUTER261, offset: 0x6828 */ __IO uint64_t GICDA_IROUTER262; /**< GICDA_IROUTER262, offset: 0x6830 */ __IO uint64_t GICDA_IROUTER263; /**< GICDA_IROUTER263, offset: 0x6838 */ __IO uint64_t GICDA_IROUTER264; /**< GICDA_IROUTER264, offset: 0x6840 */ __IO uint64_t GICDA_IROUTER265; /**< GICDA_IROUTER265, offset: 0x6848 */ __IO uint64_t GICDA_IROUTER266; /**< GICDA_IROUTER266, offset: 0x6850 */ __IO uint64_t GICDA_IROUTER267; /**< GICDA_IROUTER267, offset: 0x6858 */ __IO uint64_t GICDA_IROUTER268; /**< GICDA_IROUTER268, offset: 0x6860 */ __IO uint64_t GICDA_IROUTER269; /**< GICDA_IROUTER269, offset: 0x6868 */ __IO uint64_t GICDA_IROUTER270; /**< GICDA_IROUTER270, offset: 0x6870 */ __IO uint64_t GICDA_IROUTER271; /**< GICDA_IROUTER271, offset: 0x6878 */ __IO uint64_t GICDA_IROUTER272; /**< GICDA_IROUTER272, offset: 0x6880 */ __IO uint64_t GICDA_IROUTER273; /**< GICDA_IROUTER273, offset: 0x6888 */ __IO uint64_t GICDA_IROUTER274; /**< GICDA_IROUTER274, offset: 0x6890 */ __IO uint64_t GICDA_IROUTER275; /**< GICDA_IROUTER275, offset: 0x6898 */ __IO uint64_t GICDA_IROUTER276; /**< GICDA_IROUTER276, offset: 0x68A0 */ __IO uint64_t GICDA_IROUTER277; /**< GICDA_IROUTER277, offset: 0x68A8 */ __IO uint64_t GICDA_IROUTER278; /**< GICDA_IROUTER278, offset: 0x68B0 */ __IO uint64_t GICDA_IROUTER279; /**< GICDA_IROUTER279, offset: 0x68B8 */ __IO uint64_t GICDA_IROUTER280; /**< GICDA_IROUTER280, offset: 0x68C0 */ __IO uint64_t GICDA_IROUTER281; /**< GICDA_IROUTER281, offset: 0x68C8 */ __IO uint64_t GICDA_IROUTER282; /**< GICDA_IROUTER282, offset: 0x68D0 */ __IO uint64_t GICDA_IROUTER283; /**< GICDA_IROUTER283, offset: 0x68D8 */ __IO uint64_t GICDA_IROUTER284; /**< GICDA_IROUTER284, offset: 0x68E0 */ __IO uint64_t GICDA_IROUTER285; /**< GICDA_IROUTER285, offset: 0x68E8 */ __IO uint64_t GICDA_IROUTER286; /**< GICDA_IROUTER286, offset: 0x68F0 */ __IO uint64_t GICDA_IROUTER287; /**< GICDA_IROUTER287, offset: 0x68F8 */ __IO uint64_t GICDA_IROUTER288; /**< GICDA_IROUTER288, offset: 0x6900 */ __IO uint64_t GICDA_IROUTER289; /**< GICDA_IROUTER289, offset: 0x6908 */ __IO uint64_t GICDA_IROUTER290; /**< GICDA_IROUTER290, offset: 0x6910 */ __IO uint64_t GICDA_IROUTER291; /**< GICDA_IROUTER291, offset: 0x6918 */ __IO uint64_t GICDA_IROUTER292; /**< GICDA_IROUTER292, offset: 0x6920 */ __IO uint64_t GICDA_IROUTER293; /**< GICDA_IROUTER293, offset: 0x6928 */ __IO uint64_t GICDA_IROUTER294; /**< GICDA_IROUTER294, offset: 0x6930 */ __IO uint64_t GICDA_IROUTER295; /**< GICDA_IROUTER295, offset: 0x6938 */ __IO uint64_t GICDA_IROUTER296; /**< GICDA_IROUTER296, offset: 0x6940 */ __IO uint64_t GICDA_IROUTER297; /**< GICDA_IROUTER297, offset: 0x6948 */ __IO uint64_t GICDA_IROUTER298; /**< GICDA_IROUTER298, offset: 0x6950 */ __IO uint64_t GICDA_IROUTER299; /**< GICDA_IROUTER299, offset: 0x6958 */ __IO uint64_t GICDA_IROUTER300; /**< GICDA_IROUTER300, offset: 0x6960 */ __IO uint64_t GICDA_IROUTER301; /**< GICDA_IROUTER301, offset: 0x6968 */ __IO uint64_t GICDA_IROUTER302; /**< GICDA_IROUTER302, offset: 0x6970 */ __IO uint64_t GICDA_IROUTER303; /**< GICDA_IROUTER303, offset: 0x6978 */ __IO uint64_t GICDA_IROUTER304; /**< GICDA_IROUTER304, offset: 0x6980 */ __IO uint64_t GICDA_IROUTER305; /**< GICDA_IROUTER305, offset: 0x6988 */ __IO uint64_t GICDA_IROUTER306; /**< GICDA_IROUTER306, offset: 0x6990 */ __IO uint64_t GICDA_IROUTER307; /**< GICDA_IROUTER307, offset: 0x6998 */ __IO uint64_t GICDA_IROUTER308; /**< GICDA_IROUTER308, offset: 0x69A0 */ __IO uint64_t GICDA_IROUTER309; /**< GICDA_IROUTER309, offset: 0x69A8 */ __IO uint64_t GICDA_IROUTER310; /**< GICDA_IROUTER310, offset: 0x69B0 */ __IO uint64_t GICDA_IROUTER311; /**< GICDA_IROUTER311, offset: 0x69B8 */ __IO uint64_t GICDA_IROUTER312; /**< GICDA_IROUTER312, offset: 0x69C0 */ __IO uint64_t GICDA_IROUTER313; /**< GICDA_IROUTER313, offset: 0x69C8 */ __IO uint64_t GICDA_IROUTER314; /**< GICDA_IROUTER314, offset: 0x69D0 */ __IO uint64_t GICDA_IROUTER315; /**< GICDA_IROUTER315, offset: 0x69D8 */ __IO uint64_t GICDA_IROUTER316; /**< GICDA_IROUTER316, offset: 0x69E0 */ __IO uint64_t GICDA_IROUTER317; /**< GICDA_IROUTER317, offset: 0x69E8 */ __IO uint64_t GICDA_IROUTER318; /**< GICDA_IROUTER318, offset: 0x69F0 */ __IO uint64_t GICDA_IROUTER319; /**< GICDA_IROUTER319, offset: 0x69F8 */ __IO uint64_t GICDA_IROUTER320; /**< GICDA_IROUTER320, offset: 0x6A00 */ __IO uint64_t GICDA_IROUTER321; /**< GICDA_IROUTER321, offset: 0x6A08 */ __IO uint64_t GICDA_IROUTER322; /**< GICDA_IROUTER322, offset: 0x6A10 */ __IO uint64_t GICDA_IROUTER323; /**< GICDA_IROUTER323, offset: 0x6A18 */ __IO uint64_t GICDA_IROUTER324; /**< GICDA_IROUTER324, offset: 0x6A20 */ __IO uint64_t GICDA_IROUTER325; /**< GICDA_IROUTER325, offset: 0x6A28 */ __IO uint64_t GICDA_IROUTER326; /**< GICDA_IROUTER326, offset: 0x6A30 */ __IO uint64_t GICDA_IROUTER327; /**< GICDA_IROUTER327, offset: 0x6A38 */ __IO uint64_t GICDA_IROUTER328; /**< GICDA_IROUTER328, offset: 0x6A40 */ __IO uint64_t GICDA_IROUTER329; /**< GICDA_IROUTER329, offset: 0x6A48 */ __IO uint64_t GICDA_IROUTER330; /**< GICDA_IROUTER330, offset: 0x6A50 */ __IO uint64_t GICDA_IROUTER331; /**< GICDA_IROUTER331, offset: 0x6A58 */ __IO uint64_t GICDA_IROUTER332; /**< GICDA_IROUTER332, offset: 0x6A60 */ __IO uint64_t GICDA_IROUTER333; /**< GICDA_IROUTER333, offset: 0x6A68 */ __IO uint64_t GICDA_IROUTER334; /**< GICDA_IROUTER334, offset: 0x6A70 */ __IO uint64_t GICDA_IROUTER335; /**< GICDA_IROUTER335, offset: 0x6A78 */ __IO uint64_t GICDA_IROUTER336; /**< GICDA_IROUTER336, offset: 0x6A80 */ __IO uint64_t GICDA_IROUTER337; /**< GICDA_IROUTER337, offset: 0x6A88 */ __IO uint64_t GICDA_IROUTER338; /**< GICDA_IROUTER338, offset: 0x6A90 */ __IO uint64_t GICDA_IROUTER339; /**< GICDA_IROUTER339, offset: 0x6A98 */ __IO uint64_t GICDA_IROUTER340; /**< GICDA_IROUTER340, offset: 0x6AA0 */ __IO uint64_t GICDA_IROUTER341; /**< GICDA_IROUTER341, offset: 0x6AA8 */ __IO uint64_t GICDA_IROUTER342; /**< GICDA_IROUTER342, offset: 0x6AB0 */ __IO uint64_t GICDA_IROUTER343; /**< GICDA_IROUTER343, offset: 0x6AB8 */ __IO uint64_t GICDA_IROUTER344; /**< GICDA_IROUTER344, offset: 0x6AC0 */ __IO uint64_t GICDA_IROUTER345; /**< GICDA_IROUTER345, offset: 0x6AC8 */ __IO uint64_t GICDA_IROUTER346; /**< GICDA_IROUTER346, offset: 0x6AD0 */ __IO uint64_t GICDA_IROUTER347; /**< GICDA_IROUTER347, offset: 0x6AD8 */ __IO uint64_t GICDA_IROUTER348; /**< GICDA_IROUTER348, offset: 0x6AE0 */ __IO uint64_t GICDA_IROUTER349; /**< GICDA_IROUTER349, offset: 0x6AE8 */ __IO uint64_t GICDA_IROUTER350; /**< GICDA_IROUTER350, offset: 0x6AF0 */ __IO uint64_t GICDA_IROUTER351; /**< GICDA_IROUTER351, offset: 0x6AF8 */ __IO uint64_t GICDA_IROUTER352; /**< GICDA_IROUTER352, offset: 0x6B00 */ __IO uint64_t GICDA_IROUTER353; /**< GICDA_IROUTER353, offset: 0x6B08 */ __IO uint64_t GICDA_IROUTER354; /**< GICDA_IROUTER354, offset: 0x6B10 */ __IO uint64_t GICDA_IROUTER355; /**< GICDA_IROUTER355, offset: 0x6B18 */ __IO uint64_t GICDA_IROUTER356; /**< GICDA_IROUTER356, offset: 0x6B20 */ __IO uint64_t GICDA_IROUTER357; /**< GICDA_IROUTER357, offset: 0x6B28 */ __IO uint64_t GICDA_IROUTER358; /**< GICDA_IROUTER358, offset: 0x6B30 */ __IO uint64_t GICDA_IROUTER359; /**< GICDA_IROUTER359, offset: 0x6B38 */ __IO uint64_t GICDA_IROUTER360; /**< GICDA_IROUTER360, offset: 0x6B40 */ __IO uint64_t GICDA_IROUTER361; /**< GICDA_IROUTER361, offset: 0x6B48 */ __IO uint64_t GICDA_IROUTER362; /**< GICDA_IROUTER362, offset: 0x6B50 */ __IO uint64_t GICDA_IROUTER363; /**< GICDA_IROUTER363, offset: 0x6B58 */ __IO uint64_t GICDA_IROUTER364; /**< GICDA_IROUTER364, offset: 0x6B60 */ __IO uint64_t GICDA_IROUTER365; /**< GICDA_IROUTER365, offset: 0x6B68 */ __IO uint64_t GICDA_IROUTER366; /**< GICDA_IROUTER366, offset: 0x6B70 */ __IO uint64_t GICDA_IROUTER367; /**< GICDA_IROUTER367, offset: 0x6B78 */ __IO uint64_t GICDA_IROUTER368; /**< GICDA_IROUTER368, offset: 0x6B80 */ __IO uint64_t GICDA_IROUTER369; /**< GICDA_IROUTER369, offset: 0x6B88 */ __IO uint64_t GICDA_IROUTER370; /**< GICDA_IROUTER370, offset: 0x6B90 */ __IO uint64_t GICDA_IROUTER371; /**< GICDA_IROUTER371, offset: 0x6B98 */ __IO uint64_t GICDA_IROUTER372; /**< GICDA_IROUTER372, offset: 0x6BA0 */ __IO uint64_t GICDA_IROUTER373; /**< GICDA_IROUTER373, offset: 0x6BA8 */ __IO uint64_t GICDA_IROUTER374; /**< GICDA_IROUTER374, offset: 0x6BB0 */ __IO uint64_t GICDA_IROUTER375; /**< GICDA_IROUTER375, offset: 0x6BB8 */ __IO uint64_t GICDA_IROUTER376; /**< GICDA_IROUTER376, offset: 0x6BC0 */ __IO uint64_t GICDA_IROUTER377; /**< GICDA_IROUTER377, offset: 0x6BC8 */ __IO uint64_t GICDA_IROUTER378; /**< GICDA_IROUTER378, offset: 0x6BD0 */ __IO uint64_t GICDA_IROUTER379; /**< GICDA_IROUTER379, offset: 0x6BD8 */ __IO uint64_t GICDA_IROUTER380; /**< GICDA_IROUTER380, offset: 0x6BE0 */ __IO uint64_t GICDA_IROUTER381; /**< GICDA_IROUTER381, offset: 0x6BE8 */ __IO uint64_t GICDA_IROUTER382; /**< GICDA_IROUTER382, offset: 0x6BF0 */ __IO uint64_t GICDA_IROUTER383; /**< GICDA_IROUTER383, offset: 0x6BF8 */ __IO uint64_t GICDA_IROUTER384; /**< GICDA_IROUTER384, offset: 0x6C00 */ __IO uint64_t GICDA_IROUTER385; /**< GICDA_IROUTER385, offset: 0x6C08 */ __IO uint64_t GICDA_IROUTER386; /**< GICDA_IROUTER386, offset: 0x6C10 */ __IO uint64_t GICDA_IROUTER387; /**< GICDA_IROUTER387, offset: 0x6C18 */ __IO uint64_t GICDA_IROUTER388; /**< GICDA_IROUTER388, offset: 0x6C20 */ __IO uint64_t GICDA_IROUTER389; /**< GICDA_IROUTER389, offset: 0x6C28 */ __IO uint64_t GICDA_IROUTER390; /**< GICDA_IROUTER390, offset: 0x6C30 */ __IO uint64_t GICDA_IROUTER391; /**< GICDA_IROUTER391, offset: 0x6C38 */ __IO uint64_t GICDA_IROUTER392; /**< GICDA_IROUTER392, offset: 0x6C40 */ __IO uint64_t GICDA_IROUTER393; /**< GICDA_IROUTER393, offset: 0x6C48 */ __IO uint64_t GICDA_IROUTER394; /**< GICDA_IROUTER394, offset: 0x6C50 */ __IO uint64_t GICDA_IROUTER395; /**< GICDA_IROUTER395, offset: 0x6C58 */ __IO uint64_t GICDA_IROUTER396; /**< GICDA_IROUTER396, offset: 0x6C60 */ __IO uint64_t GICDA_IROUTER397; /**< GICDA_IROUTER397, offset: 0x6C68 */ __IO uint64_t GICDA_IROUTER398; /**< GICDA_IROUTER398, offset: 0x6C70 */ __IO uint64_t GICDA_IROUTER399; /**< GICDA_IROUTER399, offset: 0x6C78 */ __IO uint64_t GICDA_IROUTER400; /**< GICDA_IROUTER400, offset: 0x6C80 */ __IO uint64_t GICDA_IROUTER401; /**< GICDA_IROUTER401, offset: 0x6C88 */ __IO uint64_t GICDA_IROUTER402; /**< GICDA_IROUTER402, offset: 0x6C90 */ __IO uint64_t GICDA_IROUTER403; /**< GICDA_IROUTER403, offset: 0x6C98 */ __IO uint64_t GICDA_IROUTER404; /**< GICDA_IROUTER404, offset: 0x6CA0 */ __IO uint64_t GICDA_IROUTER405; /**< GICDA_IROUTER405, offset: 0x6CA8 */ __IO uint64_t GICDA_IROUTER406; /**< GICDA_IROUTER406, offset: 0x6CB0 */ __IO uint64_t GICDA_IROUTER407; /**< GICDA_IROUTER407, offset: 0x6CB8 */ __IO uint64_t GICDA_IROUTER408; /**< GICDA_IROUTER408, offset: 0x6CC0 */ __IO uint64_t GICDA_IROUTER409; /**< GICDA_IROUTER409, offset: 0x6CC8 */ __IO uint64_t GICDA_IROUTER410; /**< GICDA_IROUTER410, offset: 0x6CD0 */ __IO uint64_t GICDA_IROUTER411; /**< GICDA_IROUTER411, offset: 0x6CD8 */ __IO uint64_t GICDA_IROUTER412; /**< GICDA_IROUTER412, offset: 0x6CE0 */ __IO uint64_t GICDA_IROUTER413; /**< GICDA_IROUTER413, offset: 0x6CE8 */ __IO uint64_t GICDA_IROUTER414; /**< GICDA_IROUTER414, offset: 0x6CF0 */ __IO uint64_t GICDA_IROUTER415; /**< GICDA_IROUTER415, offset: 0x6CF8 */ uint8_t RESERVED_18[23296]; __O uint64_t GICDA_RDOFFR0; /**< GICDA_RDOFFR0, offset: 0xC800 */ uint8_t RESERVED_19[6144]; __IO uint32_t GICDA_ICLAR2; /**< GICDA_ICLAR2, offset: 0xE008 */ __IO uint32_t GICDA_ICLAR3; /**< GICDA_ICLAR3, offset: 0xE00C */ __IO uint32_t GICDA_ICLAR4; /**< GICDA_ICLAR4, offset: 0xE010 */ __IO uint32_t GICDA_ICLAR5; /**< GICDA_ICLAR5, offset: 0xE014 */ __IO uint32_t GICDA_ICLAR6; /**< GICDA_ICLAR6, offset: 0xE018 */ __IO uint32_t GICDA_ICLAR7; /**< GICDA_ICLAR7, offset: 0xE01C */ __IO uint32_t GICDA_ICLAR8; /**< GICDA_ICLAR8, offset: 0xE020 */ __IO uint32_t GICDA_ICLAR9; /**< GICDA_ICLAR9, offset: 0xE024 */ __IO uint32_t GICDA_ICLAR10; /**< GICDA_ICLAR10, offset: 0xE028 */ __IO uint32_t GICDA_ICLAR11; /**< GICDA_ICLAR11, offset: 0xE02C */ __IO uint32_t GICDA_ICLAR12; /**< GICDA_ICLAR12, offset: 0xE030 */ __IO uint32_t GICDA_ICLAR13; /**< GICDA_ICLAR13, offset: 0xE034 */ __IO uint32_t GICDA_ICLAR14; /**< GICDA_ICLAR14, offset: 0xE038 */ __IO uint32_t GICDA_ICLAR15; /**< GICDA_ICLAR15, offset: 0xE03C */ __IO uint32_t GICDA_ICLAR16; /**< GICDA_ICLAR16, offset: 0xE040 */ __IO uint32_t GICDA_ICLAR17; /**< GICDA_ICLAR17, offset: 0xE044 */ __IO uint32_t GICDA_ICLAR18; /**< GICDA_ICLAR18, offset: 0xE048 */ __IO uint32_t GICDA_ICLAR19; /**< GICDA_ICLAR19, offset: 0xE04C */ __IO uint32_t GICDA_ICLAR20; /**< GICDA_ICLAR20, offset: 0xE050 */ __IO uint32_t GICDA_ICLAR21; /**< GICDA_ICLAR21, offset: 0xE054 */ __IO uint32_t GICDA_ICLAR22; /**< GICDA_ICLAR22, offset: 0xE058 */ __IO uint32_t GICDA_ICLAR23; /**< GICDA_ICLAR23, offset: 0xE05C */ __IO uint32_t GICDA_ICLAR24; /**< GICDA_ICLAR24, offset: 0xE060 */ __IO uint32_t GICDA_ICLAR25; /**< GICDA_ICLAR25, offset: 0xE064 */ uint8_t RESERVED_20[156]; __IO uint32_t GICDA_ICERRR1; /**< GICDA_ICERRR1, offset: 0xE104 */ __IO uint32_t GICDA_ICERRR2; /**< GICDA_ICERRR2, offset: 0xE108 */ __IO uint32_t GICDA_ICERRR3; /**< GICDA_ICERRR3, offset: 0xE10C */ __IO uint32_t GICDA_ICERRR4; /**< GICDA_ICERRR4, offset: 0xE110 */ __IO uint32_t GICDA_ICERRR5; /**< GICDA_ICERRR5, offset: 0xE114 */ __IO uint32_t GICDA_ICERRR6; /**< GICDA_ICERRR6, offset: 0xE118 */ __IO uint32_t GICDA_ICERRR7; /**< GICDA_ICERRR7, offset: 0xE11C */ __IO uint32_t GICDA_ICERRR8; /**< GICDA_ICERRR8, offset: 0xE120 */ __IO uint32_t GICDA_ICERRR9; /**< GICDA_ICERRR9, offset: 0xE124 */ __IO uint32_t GICDA_ICERRR10; /**< GICDA_ICERRR10, offset: 0xE128 */ __IO uint32_t GICDA_ICERRR11; /**< GICDA_ICERRR11, offset: 0xE12C */ __IO uint32_t GICDA_ICERRR12; /**< GICDA_ICERRR12, offset: 0xE130 */ uint8_t RESERVED_21[80]; __IO uint32_t GICDA_ICGERRR1; /**< GICDA_ICGERRR1, offset: 0xE184 */ __IO uint32_t GICDA_ICGERRR2; /**< GICDA_ICGERRR2, offset: 0xE188 */ __IO uint32_t GICDA_ICGERRR3; /**< GICDA_ICGERRR3, offset: 0xE18C */ __IO uint32_t GICDA_ICGERRR4; /**< GICDA_ICGERRR4, offset: 0xE190 */ __IO uint32_t GICDA_ICGERRR5; /**< GICDA_ICGERRR5, offset: 0xE194 */ __IO uint32_t GICDA_ICGERRR6; /**< GICDA_ICGERRR6, offset: 0xE198 */ __IO uint32_t GICDA_ICGERRR7; /**< GICDA_ICGERRR7, offset: 0xE19C */ __IO uint32_t GICDA_ICGERRR8; /**< GICDA_ICGERRR8, offset: 0xE1A0 */ __IO uint32_t GICDA_ICGERRR9; /**< GICDA_ICGERRR9, offset: 0xE1A4 */ __IO uint32_t GICDA_ICGERRR10; /**< GICDA_ICGERRR10, offset: 0xE1A8 */ __IO uint32_t GICDA_ICGERRR11; /**< GICDA_ICGERRR11, offset: 0xE1AC */ __IO uint32_t GICDA_ICGERRR12; /**< GICDA_ICGERRR12, offset: 0xE1B0 */ uint8_t RESERVED_22[80]; __IO uint32_t GICDA_ISERRR1; /**< GICDA_ISERRR1, offset: 0xE204 */ __IO uint32_t GICDA_ISERRR2; /**< GICDA_ISERRR2, offset: 0xE208 */ __IO uint32_t GICDA_ISERRR3; /**< GICDA_ISERRR3, offset: 0xE20C */ __IO uint32_t GICDA_ISERRR4; /**< GICDA_ISERRR4, offset: 0xE210 */ __IO uint32_t GICDA_ISERRR5; /**< GICDA_ISERRR5, offset: 0xE214 */ __IO uint32_t GICDA_ISERRR6; /**< GICDA_ISERRR6, offset: 0xE218 */ __IO uint32_t GICDA_ISERRR7; /**< GICDA_ISERRR7, offset: 0xE21C */ __IO uint32_t GICDA_ISERRR8; /**< GICDA_ISERRR8, offset: 0xE220 */ __IO uint32_t GICDA_ISERRR9; /**< GICDA_ISERRR9, offset: 0xE224 */ __IO uint32_t GICDA_ISERRR10; /**< GICDA_ISERRR10, offset: 0xE228 */ __IO uint32_t GICDA_ISERRR11; /**< GICDA_ISERRR11, offset: 0xE22C */ __IO uint32_t GICDA_ISERRR12; /**< GICDA_ISERRR12, offset: 0xE230 */ uint8_t RESERVED_23[3532]; __I uint64_t GICDA_CFGID; /**< GICDA_CFGID, offset: 0xF000 */ uint8_t RESERVED_24[4040]; __I uint32_t GICDA_PIDR4; /**< GICDA_PIDR4, offset: 0xFFD0 */ __I uint32_t GICDA_PIDR5; /**< GICDA_PIDR5, offset: 0xFFD4 */ __I uint32_t GICDA_PIDR6; /**< GICDA_PIDR6, offset: 0xFFD8 */ __I uint32_t GICDA_PIDR7; /**< GICDA_PIDR7, offset: 0xFFDC */ __I uint32_t GICDA_PIDR0; /**< GICDA_PIDR0, offset: 0xFFE0 */ __I uint32_t GICDA_PIDR1; /**< GICDA_PIDR1, offset: 0xFFE4 */ __I uint32_t GICDA_PIDR2; /**< GICDA_PIDR2, offset: 0xFFE8 */ __I uint32_t GICDA_PIDR3; /**< GICDA_PIDR3, offset: 0xFFEC */ __I uint32_t GICDA_CIDR0; /**< GICDA_CIDR0, offset: 0xFFF0 */ __I uint32_t GICDA_CIDR1; /**< GICDA_CIDR1, offset: 0xFFF4 */ __I uint32_t GICDA_CIDR2; /**< GICDA_CIDR2, offset: 0xFFF8 */ __I uint32_t GICDA_CIDR3; /**< GICDA_CIDR3, offset: 0xFFFC */ } NOC_GICDA_Type; /* ---------------------------------------------------------------------------- -- NOC_GICDA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICDA_Register_Masks NOC_GICDA Register Masks * @{ */ /*! @name GICDA_CTLR - GICDA_CTLR */ /*! @{ */ #define NOC_GICDA_GICDA_CTLR_EnableGrp0_MASK (0x1U) #define NOC_GICDA_GICDA_CTLR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICDA_GICDA_CTLR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_EnableGrp0_SHIFT)) & NOC_GICDA_GICDA_CTLR_EnableGrp0_MASK) #define NOC_GICDA_GICDA_CTLR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICDA_GICDA_CTLR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICDA_GICDA_CTLR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_EnableGrp1_ns_SHIFT)) & NOC_GICDA_GICDA_CTLR_EnableGrp1_ns_MASK) #define NOC_GICDA_GICDA_CTLR_EnableGrp1_s_MASK (0x4U) #define NOC_GICDA_GICDA_CTLR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICDA_GICDA_CTLR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_EnableGrp1_s_SHIFT)) & NOC_GICDA_GICDA_CTLR_EnableGrp1_s_MASK) #define NOC_GICDA_GICDA_CTLR_RESERVED0_MASK (0x8U) #define NOC_GICDA_GICDA_CTLR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CTLR_RESERVED0_MASK) #define NOC_GICDA_GICDA_CTLR_ARE_S_MASK (0x10U) #define NOC_GICDA_GICDA_CTLR_ARE_S_SHIFT (4U) /*! ARE_S - ARE_S */ #define NOC_GICDA_GICDA_CTLR_ARE_S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_ARE_S_SHIFT)) & NOC_GICDA_GICDA_CTLR_ARE_S_MASK) #define NOC_GICDA_GICDA_CTLR_ARE_NS_MASK (0x20U) #define NOC_GICDA_GICDA_CTLR_ARE_NS_SHIFT (5U) /*! ARE_NS - ARE_NS */ #define NOC_GICDA_GICDA_CTLR_ARE_NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_ARE_NS_SHIFT)) & NOC_GICDA_GICDA_CTLR_ARE_NS_MASK) #define NOC_GICDA_GICDA_CTLR_DS_MASK (0x40U) #define NOC_GICDA_GICDA_CTLR_DS_SHIFT (6U) /*! DS - DS */ #define NOC_GICDA_GICDA_CTLR_DS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_DS_SHIFT)) & NOC_GICDA_GICDA_CTLR_DS_MASK) #define NOC_GICDA_GICDA_CTLR_E1NWF_MASK (0x80U) #define NOC_GICDA_GICDA_CTLR_E1NWF_SHIFT (7U) /*! E1NWF - E1NWF */ #define NOC_GICDA_GICDA_CTLR_E1NWF(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_E1NWF_SHIFT)) & NOC_GICDA_GICDA_CTLR_E1NWF_MASK) #define NOC_GICDA_GICDA_CTLR_RESERVED1_MASK (0x7FFFFF00U) #define NOC_GICDA_GICDA_CTLR_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_CTLR_RESERVED1_MASK) #define NOC_GICDA_GICDA_CTLR_RWP_MASK (0x80000000U) #define NOC_GICDA_GICDA_CTLR_RWP_SHIFT (31U) /*! RWP - RWP */ #define NOC_GICDA_GICDA_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CTLR_RWP_SHIFT)) & NOC_GICDA_GICDA_CTLR_RWP_MASK) /*! @} */ /*! @name GICDA_TYPER - GICDA_TYPER */ /*! @{ */ #define NOC_GICDA_GICDA_TYPER_ITLinesNumber_MASK (0x1FU) #define NOC_GICDA_GICDA_TYPER_ITLinesNumber_SHIFT (0U) /*! ITLinesNumber - ITLinesNumber */ #define NOC_GICDA_GICDA_TYPER_ITLinesNumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_ITLinesNumber_SHIFT)) & NOC_GICDA_GICDA_TYPER_ITLinesNumber_MASK) #define NOC_GICDA_GICDA_TYPER_CPUNumber_MASK (0xE0U) #define NOC_GICDA_GICDA_TYPER_CPUNumber_SHIFT (5U) /*! CPUNumber - CPUNumber */ #define NOC_GICDA_GICDA_TYPER_CPUNumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_CPUNumber_SHIFT)) & NOC_GICDA_GICDA_TYPER_CPUNumber_MASK) #define NOC_GICDA_GICDA_TYPER_Espi_MASK (0x100U) #define NOC_GICDA_GICDA_TYPER_Espi_SHIFT (8U) /*! Espi - Espi */ #define NOC_GICDA_GICDA_TYPER_Espi(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_Espi_SHIFT)) & NOC_GICDA_GICDA_TYPER_Espi_MASK) #define NOC_GICDA_GICDA_TYPER_RESERVED0_MASK (0x200U) #define NOC_GICDA_GICDA_TYPER_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_TYPER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_TYPER_RESERVED0_MASK) #define NOC_GICDA_GICDA_TYPER_SecurityExtn_MASK (0x400U) #define NOC_GICDA_GICDA_TYPER_SecurityExtn_SHIFT (10U) /*! SecurityExtn - SecurityExtn */ #define NOC_GICDA_GICDA_TYPER_SecurityExtn(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_SecurityExtn_SHIFT)) & NOC_GICDA_GICDA_TYPER_SecurityExtn_MASK) #define NOC_GICDA_GICDA_TYPER_LSPI_MASK (0xF800U) #define NOC_GICDA_GICDA_TYPER_LSPI_SHIFT (11U) /*! LSPI - LSPI */ #define NOC_GICDA_GICDA_TYPER_LSPI(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_LSPI_SHIFT)) & NOC_GICDA_GICDA_TYPER_LSPI_MASK) #define NOC_GICDA_GICDA_TYPER_MBIS_MASK (0x10000U) #define NOC_GICDA_GICDA_TYPER_MBIS_SHIFT (16U) /*! MBIS - MBIS */ #define NOC_GICDA_GICDA_TYPER_MBIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_MBIS_SHIFT)) & NOC_GICDA_GICDA_TYPER_MBIS_MASK) #define NOC_GICDA_GICDA_TYPER_LPIS_MASK (0x20000U) #define NOC_GICDA_GICDA_TYPER_LPIS_SHIFT (17U) /*! LPIS - LPIS */ #define NOC_GICDA_GICDA_TYPER_LPIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_LPIS_SHIFT)) & NOC_GICDA_GICDA_TYPER_LPIS_MASK) #define NOC_GICDA_GICDA_TYPER_DVIS_MASK (0x40000U) #define NOC_GICDA_GICDA_TYPER_DVIS_SHIFT (18U) /*! DVIS - DVIS */ #define NOC_GICDA_GICDA_TYPER_DVIS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_DVIS_SHIFT)) & NOC_GICDA_GICDA_TYPER_DVIS_MASK) #define NOC_GICDA_GICDA_TYPER_IDbits_MASK (0xF80000U) #define NOC_GICDA_GICDA_TYPER_IDbits_SHIFT (19U) /*! IDbits - IDbits */ #define NOC_GICDA_GICDA_TYPER_IDbits(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_IDbits_SHIFT)) & NOC_GICDA_GICDA_TYPER_IDbits_MASK) #define NOC_GICDA_GICDA_TYPER_A3V_MASK (0x1000000U) #define NOC_GICDA_GICDA_TYPER_A3V_SHIFT (24U) /*! A3V - A3V */ #define NOC_GICDA_GICDA_TYPER_A3V(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_A3V_SHIFT)) & NOC_GICDA_GICDA_TYPER_A3V_MASK) #define NOC_GICDA_GICDA_TYPER_No1N_MASK (0x2000000U) #define NOC_GICDA_GICDA_TYPER_No1N_SHIFT (25U) /*! No1N - No1N */ #define NOC_GICDA_GICDA_TYPER_No1N(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_No1N_SHIFT)) & NOC_GICDA_GICDA_TYPER_No1N_MASK) #define NOC_GICDA_GICDA_TYPER_RSS_MASK (0x4000000U) #define NOC_GICDA_GICDA_TYPER_RSS_SHIFT (26U) /*! RSS - RSS */ #define NOC_GICDA_GICDA_TYPER_RSS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_RSS_SHIFT)) & NOC_GICDA_GICDA_TYPER_RSS_MASK) #define NOC_GICDA_GICDA_TYPER_ESPI_range_MASK (0xF8000000U) #define NOC_GICDA_GICDA_TYPER_ESPI_range_SHIFT (27U) /*! ESPI_range - ESPI_range */ #define NOC_GICDA_GICDA_TYPER_ESPI_range(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER_ESPI_range_SHIFT)) & NOC_GICDA_GICDA_TYPER_ESPI_range_MASK) /*! @} */ /*! @name GICDA_IIDR - GICDA_IIDR */ /*! @{ */ #define NOC_GICDA_GICDA_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICDA_GICDA_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICDA_GICDA_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IIDR_Implementer_SHIFT)) & NOC_GICDA_GICDA_IIDR_Implementer_MASK) #define NOC_GICDA_GICDA_IIDR_Revision_MASK (0xF000U) #define NOC_GICDA_GICDA_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICDA_GICDA_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IIDR_Revision_SHIFT)) & NOC_GICDA_GICDA_IIDR_Revision_MASK) #define NOC_GICDA_GICDA_IIDR_Variant_MASK (0xF0000U) #define NOC_GICDA_GICDA_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICDA_GICDA_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IIDR_Variant_SHIFT)) & NOC_GICDA_GICDA_IIDR_Variant_MASK) #define NOC_GICDA_GICDA_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICDA_GICDA_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IIDR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IIDR_RESERVED0_MASK) #define NOC_GICDA_GICDA_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICDA_GICDA_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IIDR_ProductID_SHIFT)) & NOC_GICDA_GICDA_IIDR_ProductID_MASK) /*! @} */ /*! @name GICDA_TYPER2 - GICDA_TYPER2 */ /*! @{ */ #define NOC_GICDA_GICDA_TYPER2_VID_MASK (0x1FU) #define NOC_GICDA_GICDA_TYPER2_VID_SHIFT (0U) /*! VID - VID */ #define NOC_GICDA_GICDA_TYPER2_VID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER2_VID_SHIFT)) & NOC_GICDA_GICDA_TYPER2_VID_MASK) #define NOC_GICDA_GICDA_TYPER2_RESERVED0_MASK (0x60U) #define NOC_GICDA_GICDA_TYPER2_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_TYPER2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER2_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_TYPER2_RESERVED0_MASK) #define NOC_GICDA_GICDA_TYPER2_VIL_MASK (0x80U) #define NOC_GICDA_GICDA_TYPER2_VIL_SHIFT (7U) /*! VIL - VIL */ #define NOC_GICDA_GICDA_TYPER2_VIL(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER2_VIL_SHIFT)) & NOC_GICDA_GICDA_TYPER2_VIL_MASK) #define NOC_GICDA_GICDA_TYPER2_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_TYPER2_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_TYPER2_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_TYPER2_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_TYPER2_RESERVED1_MASK) /*! @} */ /*! @name GICDA_STATUSR - GICDA_STATUSR */ /*! @{ */ #define NOC_GICDA_GICDA_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICDA_GICDA_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICDA_GICDA_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_STATUSR_RESERVED_SHIFT)) & NOC_GICDA_GICDA_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICDA_FCTLR - GICDA_FCTLR */ /*! @{ */ #define NOC_GICDA_GICDA_FCTLR_SIP_MASK (0x1U) #define NOC_GICDA_GICDA_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICDA_GICDA_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_SIP_SHIFT)) & NOC_GICDA_GICDA_FCTLR_SIP_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED0_MASK (0x2U) #define NOC_GICDA_GICDA_FCTLR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED0_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED1_MASK (0x4U) #define NOC_GICDA_GICDA_FCTLR_RESERVED1_SHIFT (2U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED1_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED2_MASK (0x8U) #define NOC_GICDA_GICDA_FCTLR_RESERVED2_SHIFT (3U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED2_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED2_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED3_MASK (0xFFF0U) #define NOC_GICDA_GICDA_FCTLR_RESERVED3_SHIFT (4U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED3_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED3_MASK) #define NOC_GICDA_GICDA_FCTLR_NSACR_MASK (0x30000U) #define NOC_GICDA_GICDA_FCTLR_NSACR_SHIFT (16U) /*! NSACR - NSACR */ #define NOC_GICDA_GICDA_FCTLR_NSACR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_NSACR_SHIFT)) & NOC_GICDA_GICDA_FCTLR_NSACR_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED4_MASK (0x40000U) #define NOC_GICDA_GICDA_FCTLR_RESERVED4_SHIFT (18U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED4_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED4_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED5_MASK (0x80000U) #define NOC_GICDA_GICDA_FCTLR_RESERVED5_SHIFT (19U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED5_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED5_MASK) #define NOC_GICDA_GICDA_FCTLR_CLPL_MASK (0xF00000U) #define NOC_GICDA_GICDA_FCTLR_CLPL_SHIFT (20U) /*! CLPL - CLPL */ #define NOC_GICDA_GICDA_FCTLR_CLPL(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_CLPL_SHIFT)) & NOC_GICDA_GICDA_FCTLR_CLPL_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED6_MASK (0x3000000U) #define NOC_GICDA_GICDA_FCTLR_RESERVED6_SHIFT (24U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED6_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED6_MASK) #define NOC_GICDA_GICDA_FCTLR_POS_MASK (0x4000000U) #define NOC_GICDA_GICDA_FCTLR_POS_SHIFT (26U) /*! POS - POS */ #define NOC_GICDA_GICDA_FCTLR_POS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_POS_SHIFT)) & NOC_GICDA_GICDA_FCTLR_POS_MASK) #define NOC_GICDA_GICDA_FCTLR_RESERVED7_MASK (0xF8000000U) #define NOC_GICDA_GICDA_FCTLR_RESERVED7_SHIFT (27U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICDA_GICDA_FCTLR_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR_RESERVED7_SHIFT)) & NOC_GICDA_GICDA_FCTLR_RESERVED7_MASK) /*! @} */ /*! @name GICDA_SAC - GICDA_SAC */ /*! @{ */ #define NOC_GICDA_GICDA_SAC_RESERVED0_MASK (0x1U) #define NOC_GICDA_GICDA_SAC_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_SAC_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SAC_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_SAC_RESERVED0_MASK) #define NOC_GICDA_GICDA_SAC_GICTNS_MASK (0x2U) #define NOC_GICDA_GICDA_SAC_GICTNS_SHIFT (1U) /*! GICTNS - GICTNS */ #define NOC_GICDA_GICDA_SAC_GICTNS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SAC_GICTNS_SHIFT)) & NOC_GICDA_GICDA_SAC_GICTNS_MASK) #define NOC_GICDA_GICDA_SAC_GICPNS_MASK (0x4U) #define NOC_GICDA_GICDA_SAC_GICPNS_SHIFT (2U) /*! GICPNS - GICPNS */ #define NOC_GICDA_GICDA_SAC_GICPNS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SAC_GICPNS_SHIFT)) & NOC_GICDA_GICDA_SAC_GICPNS_MASK) #define NOC_GICDA_GICDA_SAC_RESERVED1_MASK (0xFFFFFFF8U) #define NOC_GICDA_GICDA_SAC_RESERVED1_SHIFT (3U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_SAC_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SAC_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_SAC_RESERVED1_MASK) /*! @} */ /*! @name GICDA_FCTLR2 - GICDA_FCTLR2 */ /*! @{ */ #define NOC_GICDA_GICDA_FCTLR2_CGO_MASK (0xFFFU) #define NOC_GICDA_GICDA_FCTLR2_CGO_SHIFT (0U) /*! CGO - CGO */ #define NOC_GICDA_GICDA_FCTLR2_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_CGO_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_CGO_MASK) #define NOC_GICDA_GICDA_FCTLR2_RESERVED0_MASK (0x7000U) #define NOC_GICDA_GICDA_FCTLR2_RESERVED0_SHIFT (12U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_FCTLR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_RESERVED0_MASK) #define NOC_GICDA_GICDA_FCTLR2_RESERVED1_MASK (0x8000U) #define NOC_GICDA_GICDA_FCTLR2_RESERVED1_SHIFT (15U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_FCTLR2_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_RESERVED1_MASK) #define NOC_GICDA_GICDA_FCTLR2_RWS_MASK (0x10000U) #define NOC_GICDA_GICDA_FCTLR2_RWS_SHIFT (16U) /*! RWS - RWS */ #define NOC_GICDA_GICDA_FCTLR2_RWS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_RWS_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_RWS_MASK) #define NOC_GICDA_GICDA_FCTLR2_DCC_MASK (0x20000U) #define NOC_GICDA_GICDA_FCTLR2_DCC_SHIFT (17U) /*! DCC - DCC */ #define NOC_GICDA_GICDA_FCTLR2_DCC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_DCC_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_DCC_MASK) #define NOC_GICDA_GICDA_FCTLR2_QDENY_MASK (0x40000U) #define NOC_GICDA_GICDA_FCTLR2_QDENY_SHIFT (18U) /*! QDENY - QDENY */ #define NOC_GICDA_GICDA_FCTLR2_QDENY(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_QDENY_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_QDENY_MASK) #define NOC_GICDA_GICDA_FCTLR2_RWC_MASK (0x80000U) #define NOC_GICDA_GICDA_FCTLR2_RWC_SHIFT (19U) /*! RWC - RWC */ #define NOC_GICDA_GICDA_FCTLR2_RWC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_RWC_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_RWC_MASK) #define NOC_GICDA_GICDA_FCTLR2_RESERVED2_MASK (0x1F00000U) #define NOC_GICDA_GICDA_FCTLR2_RESERVED2_SHIFT (20U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICDA_GICDA_FCTLR2_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_RESERVED2_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_RESERVED2_MASK) #define NOC_GICDA_GICDA_FCTLR2_SLC_MASK (0x2000000U) #define NOC_GICDA_GICDA_FCTLR2_SLC_SHIFT (25U) /*! SLC - SLC */ #define NOC_GICDA_GICDA_FCTLR2_SLC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_SLC_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_SLC_MASK) #define NOC_GICDA_GICDA_FCTLR2_RESERVED3_MASK (0xC000000U) #define NOC_GICDA_GICDA_FCTLR2_RESERVED3_SHIFT (26U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICDA_GICDA_FCTLR2_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_RESERVED3_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_RESERVED3_MASK) #define NOC_GICDA_GICDA_FCTLR2_RCD_MASK (0x10000000U) #define NOC_GICDA_GICDA_FCTLR2_RCD_SHIFT (28U) /*! RCD - RCD */ #define NOC_GICDA_GICDA_FCTLR2_RCD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_RCD_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_RCD_MASK) #define NOC_GICDA_GICDA_FCTLR2_IRP_MASK (0x20000000U) #define NOC_GICDA_GICDA_FCTLR2_IRP_SHIFT (29U) /*! IRP - IRP */ #define NOC_GICDA_GICDA_FCTLR2_IRP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_IRP_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_IRP_MASK) #define NOC_GICDA_GICDA_FCTLR2_AWP_MASK (0x40000000U) #define NOC_GICDA_GICDA_FCTLR2_AWP_SHIFT (30U) /*! AWP - AWP */ #define NOC_GICDA_GICDA_FCTLR2_AWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_AWP_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_AWP_MASK) #define NOC_GICDA_GICDA_FCTLR2_ARP_MASK (0x80000000U) #define NOC_GICDA_GICDA_FCTLR2_ARP_SHIFT (31U) /*! ARP - ARP */ #define NOC_GICDA_GICDA_FCTLR2_ARP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR2_ARP_SHIFT)) & NOC_GICDA_GICDA_FCTLR2_ARP_MASK) /*! @} */ /*! @name GICDA_UTILR - GICDA_UTILR */ /*! @{ */ #define NOC_GICDA_GICDA_UTILR_UEDU_MASK (0xFU) #define NOC_GICDA_GICDA_UTILR_UEDU_SHIFT (0U) /*! UEDU - UEDU */ #define NOC_GICDA_GICDA_UTILR_UEDU(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEDU_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEDU_MASK) #define NOC_GICDA_GICDA_UTILR_RESERVED0_MASK (0x1FF0U) #define NOC_GICDA_GICDA_UTILR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_UTILR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_UTILR_RESERVED0_MASK) #define NOC_GICDA_GICDA_UTILR_UEDA_MASK (0x2000U) #define NOC_GICDA_GICDA_UTILR_UEDA_SHIFT (13U) /*! UEDA - UEDA */ #define NOC_GICDA_GICDA_UTILR_UEDA(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEDA_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEDA_MASK) #define NOC_GICDA_GICDA_UTILR_UEDE_MASK (0x4000U) #define NOC_GICDA_GICDA_UTILR_UEDE_SHIFT (14U) /*! UEDE - UEDE */ #define NOC_GICDA_GICDA_UTILR_UEDE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEDE_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEDE_MASK) #define NOC_GICDA_GICDA_UTILR_UEDT_MASK (0x8000U) #define NOC_GICDA_GICDA_UTILR_UEDT_SHIFT (15U) /*! UEDT - UEDT */ #define NOC_GICDA_GICDA_UTILR_UEDT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEDT_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEDT_MASK) #define NOC_GICDA_GICDA_UTILR_UEOU_MASK (0xF0000U) #define NOC_GICDA_GICDA_UTILR_UEOU_SHIFT (16U) /*! UEOU - UEOU */ #define NOC_GICDA_GICDA_UTILR_UEOU(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEOU_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEOU_MASK) #define NOC_GICDA_GICDA_UTILR_RESERVED1_MASK (0x1FF00000U) #define NOC_GICDA_GICDA_UTILR_RESERVED1_SHIFT (20U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_UTILR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_UTILR_RESERVED1_MASK) #define NOC_GICDA_GICDA_UTILR_UEOA_MASK (0x20000000U) #define NOC_GICDA_GICDA_UTILR_UEOA_SHIFT (29U) /*! UEOA - UEOA */ #define NOC_GICDA_GICDA_UTILR_UEOA(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEOA_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEOA_MASK) #define NOC_GICDA_GICDA_UTILR_UEOE_MASK (0x40000000U) #define NOC_GICDA_GICDA_UTILR_UEOE_SHIFT (30U) /*! UEOE - UEOE */ #define NOC_GICDA_GICDA_UTILR_UEOE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEOE_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEOE_MASK) #define NOC_GICDA_GICDA_UTILR_UEOT_MASK (0x80000000U) #define NOC_GICDA_GICDA_UTILR_UEOT_SHIFT (31U) /*! UEOT - UEOT */ #define NOC_GICDA_GICDA_UTILR_UEOT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_UTILR_UEOT_SHIFT)) & NOC_GICDA_GICDA_UTILR_UEOT_MASK) /*! @} */ /*! @name GICDA_FCTLR3 - GICDA_FCTLR3 */ /*! @{ */ #define NOC_GICDA_GICDA_FCTLR3_NCP0_MASK (0x1FU) #define NOC_GICDA_GICDA_FCTLR3_NCP0_SHIFT (0U) /*! NCP0 - NCP0 */ #define NOC_GICDA_GICDA_FCTLR3_NCP0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR3_NCP0_SHIFT)) & NOC_GICDA_GICDA_FCTLR3_NCP0_MASK) #define NOC_GICDA_GICDA_FCTLR3_RESERVED0_MASK (0x60U) #define NOC_GICDA_GICDA_FCTLR3_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_FCTLR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR3_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_FCTLR3_RESERVED0_MASK) #define NOC_GICDA_GICDA_FCTLR3_SCP1_MASK (0x80U) #define NOC_GICDA_GICDA_FCTLR3_SCP1_SHIFT (7U) /*! SCP1 - SCP1 */ #define NOC_GICDA_GICDA_FCTLR3_SCP1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR3_SCP1_SHIFT)) & NOC_GICDA_GICDA_FCTLR3_SCP1_MASK) #define NOC_GICDA_GICDA_FCTLR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_FCTLR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_FCTLR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_FCTLR3_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_FCTLR3_RESERVED1_MASK) /*! @} */ /*! @name GICDA_SETSPI_NSR - GICDA_SETSPI_NSR */ /*! @{ */ #define NOC_GICDA_GICDA_SETSPI_NSR_ID_MASK (0xFFFFU) #define NOC_GICDA_GICDA_SETSPI_NSR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICDA_GICDA_SETSPI_NSR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SETSPI_NSR_ID_SHIFT)) & NOC_GICDA_GICDA_SETSPI_NSR_ID_MASK) #define NOC_GICDA_GICDA_SETSPI_NSR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICDA_GICDA_SETSPI_NSR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_SETSPI_NSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SETSPI_NSR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_SETSPI_NSR_RESERVED0_MASK) /*! @} */ /*! @name GICDA_CLRSPI_NSR - GICDA_CLRSPI_NSR */ /*! @{ */ #define NOC_GICDA_GICDA_CLRSPI_NSR_ID_MASK (0xFFFFU) #define NOC_GICDA_GICDA_CLRSPI_NSR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICDA_GICDA_CLRSPI_NSR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CLRSPI_NSR_ID_SHIFT)) & NOC_GICDA_GICDA_CLRSPI_NSR_ID_MASK) #define NOC_GICDA_GICDA_CLRSPI_NSR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICDA_GICDA_CLRSPI_NSR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CLRSPI_NSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CLRSPI_NSR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CLRSPI_NSR_RESERVED0_MASK) /*! @} */ /*! @name GICDA_SETSPI_SR - GICDA_SETSPI_SR */ /*! @{ */ #define NOC_GICDA_GICDA_SETSPI_SR_ID_MASK (0xFFFFU) #define NOC_GICDA_GICDA_SETSPI_SR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICDA_GICDA_SETSPI_SR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SETSPI_SR_ID_SHIFT)) & NOC_GICDA_GICDA_SETSPI_SR_ID_MASK) #define NOC_GICDA_GICDA_SETSPI_SR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICDA_GICDA_SETSPI_SR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_SETSPI_SR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_SETSPI_SR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_SETSPI_SR_RESERVED0_MASK) /*! @} */ /*! @name GICDA_CLRSPI_SR - GICDA_CLRSPI_SR */ /*! @{ */ #define NOC_GICDA_GICDA_CLRSPI_SR_ID_MASK (0xFFFFU) #define NOC_GICDA_GICDA_CLRSPI_SR_ID_SHIFT (0U) /*! ID - ID */ #define NOC_GICDA_GICDA_CLRSPI_SR_ID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CLRSPI_SR_ID_SHIFT)) & NOC_GICDA_GICDA_CLRSPI_SR_ID_MASK) #define NOC_GICDA_GICDA_CLRSPI_SR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICDA_GICDA_CLRSPI_SR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CLRSPI_SR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CLRSPI_SR_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CLRSPI_SR_RESERVED0_MASK) /*! @} */ /*! @name GICDA_IGROUPR1 - GICDA_IGROUPR1 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR1_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR1_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR1_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR2 - GICDA_IGROUPR2 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR2_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR2_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR2_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR3 - GICDA_IGROUPR3 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR3_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR3_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR3_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR4 - GICDA_IGROUPR4 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR4_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR4_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR4_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR5 - GICDA_IGROUPR5 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR5_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR5_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR5_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR6 - GICDA_IGROUPR6 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR6_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR6_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR6_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR7 - GICDA_IGROUPR7 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR7_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR7_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR7_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR8 - GICDA_IGROUPR8 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR8_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR8_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR8_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR9 - GICDA_IGROUPR9 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR9_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR9_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR9_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR10 - GICDA_IGROUPR10 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR10_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR10_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR10_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR11 - GICDA_IGROUPR11 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR11_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR11_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR11_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_IGROUPR12 - GICDA_IGROUPR12 */ /*! @{ */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit0_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit0_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit1_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit1_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit2_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit2_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit3_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit3_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit4_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit4_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit5_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit5_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit6_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit6_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit7_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit7_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit8_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit8_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit9_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit9_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit10_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit10_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit11_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit11_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit12_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit12_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit13_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit13_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit14_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit14_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit15_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit15_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit16_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit16_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit17_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit17_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit18_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit18_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit19_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit19_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit20_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit20_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit21_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit21_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit22_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit22_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit23_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit23_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit24_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit24_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit25_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit25_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit26_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit26_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit27_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit27_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit28_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit28_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit29_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit29_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit30_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit30_MASK) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICDA_GICDA_IGROUPR12_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGROUPR12_group_status_bit31_SHIFT)) & NOC_GICDA_GICDA_IGROUPR12_group_status_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER1 - GICDA_ISENABLER1 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER1_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER1_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER1_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER2 - GICDA_ISENABLER2 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER2_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER2_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER2_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER3 - GICDA_ISENABLER3 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER3_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER3_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER3_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER4 - GICDA_ISENABLER4 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER4_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER4_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER4_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER5 - GICDA_ISENABLER5 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER5_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER5_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER5_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER6 - GICDA_ISENABLER6 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER6_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER6_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER6_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER7 - GICDA_ISENABLER7 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER7_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER7_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER7_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER8 - GICDA_ISENABLER8 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER8_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER8_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER8_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER9 - GICDA_ISENABLER9 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER9_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER9_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER9_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER10 - GICDA_ISENABLER10 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER10_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER10_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER10_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER11 - GICDA_ISENABLER11 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER11_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER11_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER11_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISENABLER12 - GICDA_ISENABLER12 */ /*! @{ */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit0_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit1_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit2_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit3_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit4_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit5_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit6_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit7_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit8_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit9_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit10_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit11_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit12_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit13_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit14_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit15_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit16_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit17_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit18_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit19_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit20_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit21_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit22_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit23_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit24_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit25_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit26_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit27_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit28_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit29_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit30_MASK) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICDA_GICDA_ISENABLER12_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISENABLER12_set_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ISENABLER12_set_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER1 - GICDA_ICENABLER1 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER1_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER2 - GICDA_ICENABLER2 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER2_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER3 - GICDA_ICENABLER3 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER3_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER4 - GICDA_ICENABLER4 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER4_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER5 - GICDA_ICENABLER5 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER5_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER6 - GICDA_ICENABLER6 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER6_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER7 - GICDA_ICENABLER7 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER7_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER8 - GICDA_ICENABLER8 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER8_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER9 - GICDA_ICENABLER9 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER9_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER10 - GICDA_ICENABLER10 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER10_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER11 - GICDA_ICENABLER11 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER11_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ICENABLER12 - GICDA_ICENABLER12 */ /*! @{ */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit0_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit0_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit1_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit1_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit2_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit2_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit3_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit3_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit4_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit4_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit5_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit5_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit6_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit6_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit7_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit7_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit8_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit8_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit9_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit9_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit10_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit10_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit11_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit11_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit12_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit12_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit13_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit13_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit14_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit14_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit15_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit15_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit16_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit16_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit17_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit17_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit18_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit18_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit19_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit19_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit20_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit20_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit21_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit21_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit22_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit22_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit23_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit23_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit24_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit24_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit25_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit25_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit26_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit26_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit27_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit27_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit28_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit28_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit29_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit29_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit30_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit30_MASK) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit31_SHIFT)) & NOC_GICDA_GICDA_ICENABLER12_clear_enable_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR1 - GICDA_ISPENDR1 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR1_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR1_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR1_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR2 - GICDA_ISPENDR2 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR2_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR2_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR2_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR3 - GICDA_ISPENDR3 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR3_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR3_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR3_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR4 - GICDA_ISPENDR4 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR4_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR4_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR4_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR5 - GICDA_ISPENDR5 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR5_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR5_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR5_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR6 - GICDA_ISPENDR6 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR6_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR6_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR6_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR7 - GICDA_ISPENDR7 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR7_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR7_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR7_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR8 - GICDA_ISPENDR8 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR8_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR8_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR8_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR9 - GICDA_ISPENDR9 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR9_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR9_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR9_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR10 - GICDA_ISPENDR10 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR10_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR10_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR10_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR11 - GICDA_ISPENDR11 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR11_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR11_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR11_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISPENDR12 - GICDA_ISPENDR12 */ /*! @{ */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit0_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit1_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit2_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit3_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit4_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit5_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit6_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit7_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit8_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit9_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit10_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit11_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit12_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit13_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit14_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit15_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit16_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit17_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit18_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit19_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit20_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit21_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit22_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit23_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit24_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit25_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit26_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit27_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit28_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit29_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit30_MASK) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICDA_GICDA_ISPENDR12_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISPENDR12_set_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ISPENDR12_set_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR1 - GICDA_ICPENDR1 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR1_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR2 - GICDA_ICPENDR2 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR2_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR3 - GICDA_ICPENDR3 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR3_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR4 - GICDA_ICPENDR4 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR4_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR5 - GICDA_ICPENDR5 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR5_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR6 - GICDA_ICPENDR6 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR6_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR7 - GICDA_ICPENDR7 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR7_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR8 - GICDA_ICPENDR8 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR8_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR9 - GICDA_ICPENDR9 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR9_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR10 - GICDA_ICPENDR10 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR10_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR11 - GICDA_ICPENDR11 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR11_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ICPENDR12 - GICDA_ICPENDR12 */ /*! @{ */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit0_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit0_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit1_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit1_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit2_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit2_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit3_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit3_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit4_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit4_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit5_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit5_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit6_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit6_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit7_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit7_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit8_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit8_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit9_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit9_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit10_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit10_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit11_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit11_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit12_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit12_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit13_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit13_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit14_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit14_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit15_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit15_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit16_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit16_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit17_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit17_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit18_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit18_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit19_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit19_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit20_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit20_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit21_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit21_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit22_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit22_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit23_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit23_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit24_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit24_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit25_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit25_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit26_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit26_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit27_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit27_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit28_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit28_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit29_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit29_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit30_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit30_MASK) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit31_SHIFT)) & NOC_GICDA_GICDA_ICPENDR12_clear_pending_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER1 - GICDA_ISACTIVER1 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER1_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER1_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER1_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER2 - GICDA_ISACTIVER2 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER2_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER2_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER2_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER3 - GICDA_ISACTIVER3 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER3_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER3_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER3_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER4 - GICDA_ISACTIVER4 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER4_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER4_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER4_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER5 - GICDA_ISACTIVER5 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER5_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER5_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER5_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER6 - GICDA_ISACTIVER6 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER6_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER6_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER6_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER7 - GICDA_ISACTIVER7 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER7_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER7_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER7_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER8 - GICDA_ISACTIVER8 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER8_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER8_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER8_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER9 - GICDA_ISACTIVER9 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER9_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER9_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER9_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER10 - GICDA_ISACTIVER10 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER10_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER10_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER10_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER11 - GICDA_ISACTIVER11 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER11_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER11_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER11_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ISACTIVER12 - GICDA_ISACTIVER12 */ /*! @{ */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit0_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit1_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit2_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit3_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit4_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit5_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit6_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit7_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit8_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit9_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit10_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit11_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit12_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit13_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit14_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit15_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit16_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit17_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit18_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit19_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit20_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit21_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit22_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit23_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit24_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit25_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit26_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit27_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit28_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit29_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit30_MASK) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICDA_GICDA_ISACTIVER12_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISACTIVER12_set_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ISACTIVER12_set_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER1 - GICDA_ICACTIVER1 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER1_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER2 - GICDA_ICACTIVER2 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER2_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER3 - GICDA_ICACTIVER3 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER3_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER4 - GICDA_ICACTIVER4 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER4_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER5 - GICDA_ICACTIVER5 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER5_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER6 - GICDA_ICACTIVER6 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER6_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER7 - GICDA_ICACTIVER7 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER7_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER8 - GICDA_ICACTIVER8 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER8_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER9 - GICDA_ICACTIVER9 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER9_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER10 - GICDA_ICACTIVER10 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER10_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER11 - GICDA_ICACTIVER11 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER11_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_ICACTIVER12 - GICDA_ICACTIVER12 */ /*! @{ */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit0_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit0_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit1_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit1_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit2_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit2_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit3_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit3_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit4_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit4_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit5_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit5_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit6_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit6_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit7_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit7_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit8_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit8_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit9_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit9_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit10_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit10_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit11_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit11_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit12_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit12_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit13_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit13_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit14_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit14_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit15_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit15_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit16_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit16_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit17_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit17_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit18_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit18_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit19_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit19_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit20_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit20_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit21_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit21_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit22_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit22_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit23_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit23_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit24_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit24_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit25_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit25_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit26_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit26_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit27_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit27_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit28_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit28_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit29_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit29_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit30_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit30_MASK) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit31_SHIFT)) & NOC_GICDA_GICDA_ICACTIVER12_clear_active_bit31_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR8 - GICDA_IPRIORITYR8 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR8_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR8_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR8_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR8_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR8_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR8_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR8_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR8_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR8_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR8_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR8_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR8_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR8_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR8_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR8_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR8_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR8_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR8_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR8_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR8_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR9 - GICDA_IPRIORITYR9 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR9_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR9_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR9_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR9_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR9_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR9_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR9_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR9_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR9_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR9_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR9_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR9_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR9_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR9_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR9_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR9_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR9_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR9_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR9_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR9_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR10 - GICDA_IPRIORITYR10 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR10_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR10_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR10_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR10_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR10_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR10_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR10_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR10_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR10_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR10_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR10_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR10_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR10_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR10_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR10_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR10_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR10_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR10_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR10_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR10_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR11 - GICDA_IPRIORITYR11 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR11_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR11_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR11_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR11_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR11_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR11_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR11_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR11_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR11_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR11_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR11_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR11_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR11_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR11_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR11_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR11_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR11_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR11_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR11_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR11_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR12 - GICDA_IPRIORITYR12 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR12_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR12_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR12_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR12_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR12_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR12_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR12_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR12_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR12_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR12_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR12_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR12_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR12_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR12_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR12_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR12_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR12_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR12_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR12_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR12_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR13 - GICDA_IPRIORITYR13 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR13_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR13_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR13_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR13_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR13_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR13_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR13_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR13_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR13_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR13_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR13_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR13_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR13_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR13_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR13_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR13_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR13_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR13_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR13_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR13_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR14 - GICDA_IPRIORITYR14 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR14_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR14_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR14_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR14_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR14_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR14_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR14_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR14_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR14_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR14_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR14_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR14_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR14_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR14_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR14_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR14_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR14_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR14_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR14_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR14_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR15 - GICDA_IPRIORITYR15 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR15_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR15_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR15_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR15_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR15_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR15_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR15_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR15_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR15_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR15_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR15_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR15_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR15_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR15_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR15_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR15_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR15_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR15_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR15_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR15_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR16 - GICDA_IPRIORITYR16 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR16_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR16_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR16_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR16_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR16_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR16_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR16_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR16_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR16_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR16_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR16_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR16_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR16_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR16_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR16_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR16_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR16_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR16_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR16_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR16_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR17 - GICDA_IPRIORITYR17 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR17_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR17_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR17_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR17_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR17_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR17_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR17_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR17_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR17_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR17_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR17_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR17_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR17_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR17_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR17_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR17_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR17_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR17_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR17_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR17_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR18 - GICDA_IPRIORITYR18 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR18_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR18_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR18_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR18_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR18_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR18_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR18_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR18_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR18_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR18_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR18_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR18_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR18_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR18_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR18_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR18_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR18_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR18_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR18_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR18_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR19 - GICDA_IPRIORITYR19 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR19_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR19_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR19_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR19_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR19_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR19_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR19_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR19_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR19_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR19_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR19_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR19_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR19_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR19_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR19_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR19_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR19_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR19_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR19_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR19_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR20 - GICDA_IPRIORITYR20 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR20_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR20_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR20_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR20_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR20_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR20_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR20_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR20_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR20_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR20_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR20_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR20_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR20_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR20_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR20_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR20_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR20_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR20_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR20_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR20_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR21 - GICDA_IPRIORITYR21 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR21_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR21_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR21_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR21_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR21_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR21_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR21_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR21_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR21_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR21_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR21_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR21_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR21_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR21_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR21_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR21_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR21_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR21_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR21_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR21_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR22 - GICDA_IPRIORITYR22 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR22_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR22_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR22_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR22_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR22_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR22_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR22_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR22_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR22_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR22_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR22_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR22_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR22_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR22_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR22_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR22_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR22_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR22_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR22_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR22_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR23 - GICDA_IPRIORITYR23 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR23_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR23_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR23_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR23_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR23_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR23_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR23_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR23_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR23_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR23_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR23_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR23_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR23_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR23_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR23_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR23_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR23_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR23_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR23_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR23_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR24 - GICDA_IPRIORITYR24 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR24_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR24_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR24_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR24_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR24_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR24_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR24_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR24_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR24_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR24_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR24_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR24_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR24_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR24_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR24_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR24_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR24_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR24_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR24_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR24_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR25 - GICDA_IPRIORITYR25 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR25_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR25_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR25_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR25_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR25_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR25_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR25_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR25_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR25_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR25_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR25_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR25_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR25_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR25_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR25_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR25_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR25_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR25_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR25_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR25_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR26 - GICDA_IPRIORITYR26 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR26_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR26_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR26_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR26_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR26_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR26_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR26_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR26_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR26_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR26_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR26_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR26_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR26_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR26_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR26_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR26_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR26_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR26_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR26_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR26_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR27 - GICDA_IPRIORITYR27 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR27_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR27_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR27_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR27_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR27_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR27_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR27_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR27_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR27_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR27_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR27_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR27_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR27_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR27_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR27_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR27_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR27_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR27_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR27_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR27_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR28 - GICDA_IPRIORITYR28 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR28_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR28_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR28_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR28_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR28_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR28_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR28_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR28_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR28_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR28_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR28_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR28_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR28_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR28_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR28_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR28_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR28_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR28_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR28_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR28_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR29 - GICDA_IPRIORITYR29 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR29_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR29_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR29_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR29_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR29_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR29_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR29_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR29_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR29_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR29_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR29_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR29_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR29_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR29_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR29_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR29_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR29_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR29_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR29_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR29_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR30 - GICDA_IPRIORITYR30 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR30_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR30_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR30_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR30_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR30_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR30_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR30_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR30_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR30_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR30_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR30_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR30_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR30_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR30_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR30_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR30_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR30_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR30_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR30_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR30_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR31 - GICDA_IPRIORITYR31 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR31_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR31_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR31_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR31_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR31_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR31_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR31_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR31_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR31_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR31_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR31_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR31_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR31_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR31_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR31_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR31_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR31_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR31_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR31_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR31_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR32 - GICDA_IPRIORITYR32 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR32_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR32_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR32_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR32_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR32_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR32_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR32_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR32_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR32_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR32_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR32_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR32_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR32_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR32_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR32_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR32_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR32_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR32_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR32_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR32_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR33 - GICDA_IPRIORITYR33 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR33_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR33_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR33_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR33_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR33_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR33_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR33_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR33_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR33_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR33_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR33_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR33_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR33_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR33_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR33_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR33_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR33_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR33_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR33_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR33_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR34 - GICDA_IPRIORITYR34 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR34_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR34_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR34_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR34_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR34_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR34_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR34_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR34_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR34_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR34_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR34_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR34_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR34_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR34_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR34_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR34_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR34_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR34_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR34_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR34_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR35 - GICDA_IPRIORITYR35 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR35_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR35_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR35_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR35_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR35_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR35_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR35_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR35_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR35_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR35_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR35_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR35_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR35_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR35_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR35_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR35_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR35_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR35_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR35_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR35_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR36 - GICDA_IPRIORITYR36 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR36_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR36_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR36_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR36_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR36_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR36_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR36_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR36_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR36_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR36_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR36_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR36_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR36_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR36_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR36_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR36_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR36_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR36_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR36_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR36_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR37 - GICDA_IPRIORITYR37 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR37_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR37_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR37_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR37_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR37_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR37_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR37_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR37_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR37_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR37_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR37_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR37_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR37_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR37_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR37_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR37_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR37_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR37_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR37_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR37_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR38 - GICDA_IPRIORITYR38 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR38_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR38_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR38_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR38_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR38_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR38_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR38_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR38_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR38_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR38_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR38_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR38_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR38_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR38_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR38_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR38_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR38_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR38_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR38_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR38_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR39 - GICDA_IPRIORITYR39 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR39_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR39_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR39_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR39_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR39_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR39_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR39_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR39_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR39_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR39_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR39_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR39_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR39_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR39_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR39_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR39_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR39_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR39_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR39_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR39_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR40 - GICDA_IPRIORITYR40 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR40_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR40_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR40_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR40_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR40_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR40_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR40_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR40_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR40_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR40_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR40_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR40_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR40_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR40_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR40_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR40_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR40_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR40_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR40_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR40_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR41 - GICDA_IPRIORITYR41 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR41_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR41_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR41_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR41_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR41_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR41_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR41_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR41_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR41_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR41_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR41_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR41_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR41_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR41_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR41_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR41_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR41_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR41_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR41_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR41_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR42 - GICDA_IPRIORITYR42 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR42_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR42_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR42_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR42_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR42_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR42_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR42_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR42_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR42_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR42_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR42_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR42_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR42_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR42_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR42_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR42_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR42_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR42_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR42_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR42_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR43 - GICDA_IPRIORITYR43 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR43_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR43_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR43_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR43_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR43_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR43_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR43_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR43_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR43_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR43_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR43_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR43_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR43_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR43_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR43_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR43_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR43_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR43_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR43_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR43_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR44 - GICDA_IPRIORITYR44 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR44_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR44_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR44_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR44_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR44_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR44_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR44_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR44_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR44_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR44_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR44_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR44_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR44_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR44_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR44_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR44_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR44_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR44_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR44_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR44_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR45 - GICDA_IPRIORITYR45 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR45_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR45_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR45_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR45_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR45_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR45_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR45_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR45_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR45_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR45_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR45_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR45_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR45_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR45_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR45_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR45_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR45_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR45_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR45_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR45_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR46 - GICDA_IPRIORITYR46 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR46_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR46_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR46_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR46_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR46_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR46_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR46_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR46_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR46_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR46_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR46_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR46_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR46_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR46_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR46_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR46_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR46_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR46_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR46_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR46_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR47 - GICDA_IPRIORITYR47 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR47_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR47_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR47_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR47_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR47_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR47_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR47_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR47_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR47_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR47_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR47_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR47_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR47_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR47_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR47_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR47_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR47_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR47_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR47_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR47_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR48 - GICDA_IPRIORITYR48 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR48_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR48_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR48_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR48_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR48_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR48_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR48_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR48_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR48_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR48_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR48_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR48_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR48_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR48_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR48_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR48_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR48_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR48_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR48_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR48_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR49 - GICDA_IPRIORITYR49 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR49_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR49_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR49_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR49_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR49_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR49_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR49_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR49_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR49_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR49_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR49_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR49_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR49_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR49_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR49_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR49_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR49_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR49_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR49_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR49_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR50 - GICDA_IPRIORITYR50 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR50_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR50_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR50_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR50_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR50_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR50_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR50_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR50_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR50_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR50_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR50_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR50_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR50_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR50_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR50_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR50_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR50_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR50_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR50_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR50_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR51 - GICDA_IPRIORITYR51 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR51_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR51_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR51_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR51_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR51_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR51_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR51_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR51_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR51_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR51_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR51_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR51_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR51_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR51_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR51_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR51_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR51_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR51_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR51_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR51_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR52 - GICDA_IPRIORITYR52 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR52_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR52_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR52_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR52_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR52_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR52_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR52_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR52_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR52_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR52_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR52_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR52_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR52_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR52_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR52_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR52_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR52_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR52_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR52_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR52_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR53 - GICDA_IPRIORITYR53 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR53_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR53_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR53_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR53_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR53_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR53_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR53_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR53_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR53_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR53_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR53_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR53_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR53_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR53_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR53_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR53_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR53_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR53_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR53_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR53_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR54 - GICDA_IPRIORITYR54 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR54_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR54_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR54_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR54_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR54_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR54_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR54_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR54_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR54_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR54_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR54_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR54_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR54_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR54_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR54_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR54_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR54_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR54_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR54_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR54_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR55 - GICDA_IPRIORITYR55 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR55_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR55_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR55_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR55_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR55_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR55_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR55_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR55_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR55_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR55_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR55_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR55_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR55_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR55_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR55_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR55_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR55_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR55_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR55_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR55_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR56 - GICDA_IPRIORITYR56 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR56_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR56_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR56_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR56_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR56_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR56_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR56_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR56_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR56_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR56_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR56_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR56_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR56_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR56_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR56_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR56_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR56_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR56_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR56_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR56_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR57 - GICDA_IPRIORITYR57 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR57_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR57_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR57_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR57_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR57_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR57_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR57_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR57_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR57_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR57_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR57_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR57_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR57_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR57_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR57_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR57_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR57_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR57_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR57_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR57_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR58 - GICDA_IPRIORITYR58 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR58_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR58_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR58_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR58_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR58_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR58_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR58_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR58_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR58_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR58_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR58_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR58_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR58_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR58_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR58_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR58_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR58_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR58_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR58_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR58_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR59 - GICDA_IPRIORITYR59 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR59_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR59_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR59_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR59_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR59_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR59_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR59_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR59_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR59_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR59_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR59_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR59_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR59_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR59_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR59_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR59_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR59_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR59_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR59_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR59_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR60 - GICDA_IPRIORITYR60 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR60_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR60_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR60_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR60_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR60_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR60_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR60_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR60_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR60_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR60_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR60_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR60_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR60_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR60_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR60_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR60_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR60_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR60_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR60_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR60_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR61 - GICDA_IPRIORITYR61 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR61_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR61_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR61_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR61_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR61_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR61_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR61_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR61_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR61_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR61_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR61_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR61_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR61_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR61_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR61_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR61_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR61_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR61_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR61_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR61_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR62 - GICDA_IPRIORITYR62 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR62_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR62_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR62_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR62_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR62_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR62_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR62_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR62_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR62_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR62_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR62_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR62_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR62_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR62_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR62_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR62_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR62_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR62_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR62_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR62_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR63 - GICDA_IPRIORITYR63 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR63_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR63_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR63_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR63_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR63_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR63_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR63_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR63_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR63_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR63_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR63_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR63_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR63_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR63_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR63_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR63_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR63_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR63_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR63_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR63_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR64 - GICDA_IPRIORITYR64 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR64_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR64_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR64_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR64_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR64_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR64_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR64_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR64_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR64_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR64_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR64_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR64_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR64_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR64_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR64_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR64_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR64_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR64_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR64_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR64_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR65 - GICDA_IPRIORITYR65 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR65_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR65_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR65_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR65_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR65_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR65_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR65_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR65_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR65_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR65_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR65_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR65_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR65_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR65_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR65_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR65_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR65_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR65_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR65_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR65_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR66 - GICDA_IPRIORITYR66 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR66_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR66_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR66_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR66_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR66_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR66_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR66_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR66_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR66_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR66_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR66_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR66_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR66_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR66_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR66_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR66_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR66_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR66_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR66_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR66_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR67 - GICDA_IPRIORITYR67 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR67_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR67_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR67_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR67_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR67_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR67_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR67_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR67_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR67_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR67_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR67_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR67_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR67_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR67_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR67_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR67_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR67_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR67_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR67_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR67_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR68 - GICDA_IPRIORITYR68 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR68_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR68_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR68_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR68_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR68_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR68_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR68_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR68_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR68_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR68_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR68_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR68_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR68_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR68_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR68_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR68_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR68_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR68_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR68_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR68_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR69 - GICDA_IPRIORITYR69 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR69_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR69_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR69_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR69_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR69_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR69_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR69_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR69_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR69_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR69_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR69_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR69_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR69_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR69_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR69_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR69_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR69_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR69_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR69_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR69_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR70 - GICDA_IPRIORITYR70 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR70_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR70_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR70_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR70_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR70_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR70_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR70_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR70_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR70_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR70_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR70_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR70_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR70_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR70_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR70_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR70_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR70_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR70_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR70_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR70_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR71 - GICDA_IPRIORITYR71 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR71_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR71_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR71_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR71_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR71_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR71_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR71_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR71_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR71_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR71_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR71_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR71_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR71_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR71_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR71_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR71_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR71_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR71_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR71_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR71_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR72 - GICDA_IPRIORITYR72 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR72_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR72_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR72_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR72_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR72_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR72_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR72_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR72_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR72_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR72_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR72_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR72_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR72_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR72_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR72_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR72_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR72_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR72_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR72_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR72_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR73 - GICDA_IPRIORITYR73 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR73_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR73_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR73_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR73_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR73_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR73_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR73_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR73_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR73_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR73_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR73_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR73_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR73_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR73_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR73_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR73_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR73_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR73_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR73_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR73_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR74 - GICDA_IPRIORITYR74 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR74_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR74_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR74_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR74_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR74_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR74_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR74_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR74_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR74_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR74_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR74_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR74_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR74_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR74_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR74_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR74_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR74_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR74_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR74_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR74_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR75 - GICDA_IPRIORITYR75 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR75_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR75_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR75_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR75_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR75_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR75_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR75_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR75_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR75_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR75_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR75_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR75_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR75_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR75_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR75_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR75_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR75_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR75_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR75_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR75_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR76 - GICDA_IPRIORITYR76 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR76_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR76_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR76_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR76_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR76_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR76_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR76_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR76_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR76_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR76_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR76_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR76_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR76_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR76_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR76_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR76_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR76_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR76_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR76_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR76_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR77 - GICDA_IPRIORITYR77 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR77_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR77_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR77_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR77_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR77_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR77_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR77_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR77_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR77_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR77_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR77_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR77_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR77_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR77_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR77_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR77_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR77_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR77_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR77_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR77_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR78 - GICDA_IPRIORITYR78 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR78_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR78_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR78_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR78_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR78_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR78_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR78_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR78_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR78_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR78_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR78_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR78_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR78_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR78_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR78_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR78_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR78_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR78_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR78_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR78_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR79 - GICDA_IPRIORITYR79 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR79_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR79_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR79_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR79_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR79_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR79_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR79_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR79_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR79_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR79_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR79_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR79_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR79_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR79_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR79_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR79_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR79_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR79_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR79_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR79_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR80 - GICDA_IPRIORITYR80 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR80_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR80_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR80_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR80_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR80_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR80_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR80_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR80_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR80_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR80_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR80_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR80_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR80_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR80_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR80_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR80_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR80_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR80_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR80_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR80_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR81 - GICDA_IPRIORITYR81 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR81_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR81_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR81_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR81_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR81_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR81_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR81_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR81_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR81_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR81_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR81_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR81_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR81_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR81_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR81_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR81_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR81_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR81_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR81_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR81_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR82 - GICDA_IPRIORITYR82 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR82_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR82_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR82_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR82_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR82_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR82_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR82_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR82_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR82_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR82_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR82_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR82_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR82_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR82_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR82_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR82_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR82_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR82_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR82_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR82_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR83 - GICDA_IPRIORITYR83 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR83_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR83_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR83_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR83_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR83_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR83_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR83_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR83_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR83_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR83_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR83_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR83_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR83_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR83_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR83_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR83_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR83_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR83_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR83_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR83_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR84 - GICDA_IPRIORITYR84 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR84_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR84_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR84_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR84_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR84_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR84_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR84_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR84_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR84_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR84_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR84_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR84_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR84_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR84_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR84_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR84_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR84_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR84_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR84_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR84_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR85 - GICDA_IPRIORITYR85 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR85_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR85_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR85_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR85_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR85_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR85_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR85_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR85_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR85_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR85_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR85_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR85_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR85_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR85_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR85_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR85_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR85_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR85_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR85_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR85_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR86 - GICDA_IPRIORITYR86 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR86_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR86_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR86_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR86_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR86_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR86_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR86_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR86_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR86_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR86_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR86_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR86_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR86_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR86_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR86_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR86_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR86_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR86_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR86_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR86_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR87 - GICDA_IPRIORITYR87 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR87_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR87_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR87_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR87_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR87_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR87_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR87_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR87_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR87_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR87_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR87_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR87_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR87_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR87_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR87_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR87_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR87_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR87_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR87_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR87_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR88 - GICDA_IPRIORITYR88 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR88_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR88_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR88_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR88_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR88_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR88_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR88_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR88_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR88_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR88_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR88_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR88_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR88_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR88_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR88_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR88_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR88_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR88_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR88_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR88_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR89 - GICDA_IPRIORITYR89 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR89_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR89_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR89_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR89_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR89_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR89_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR89_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR89_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR89_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR89_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR89_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR89_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR89_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR89_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR89_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR89_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR89_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR89_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR89_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR89_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR90 - GICDA_IPRIORITYR90 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR90_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR90_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR90_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR90_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR90_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR90_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR90_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR90_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR90_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR90_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR90_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR90_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR90_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR90_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR90_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR90_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR90_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR90_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR90_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR90_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR91 - GICDA_IPRIORITYR91 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR91_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR91_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR91_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR91_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR91_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR91_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR91_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR91_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR91_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR91_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR91_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR91_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR91_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR91_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR91_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR91_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR91_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR91_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR91_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR91_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR92 - GICDA_IPRIORITYR92 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR92_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR92_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR92_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR92_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR92_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR92_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR92_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR92_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR92_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR92_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR92_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR92_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR92_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR92_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR92_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR92_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR92_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR92_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR92_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR92_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR93 - GICDA_IPRIORITYR93 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR93_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR93_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR93_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR93_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR93_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR93_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR93_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR93_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR93_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR93_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR93_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR93_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR93_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR93_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR93_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR93_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR93_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR93_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR93_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR93_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR94 - GICDA_IPRIORITYR94 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR94_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR94_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR94_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR94_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR94_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR94_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR94_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR94_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR94_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR94_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR94_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR94_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR94_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR94_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR94_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR94_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR94_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR94_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR94_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR94_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR95 - GICDA_IPRIORITYR95 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR95_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR95_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR95_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR95_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR95_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR95_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR95_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR95_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR95_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR95_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR95_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR95_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR95_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR95_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR95_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR95_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR95_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR95_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR95_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR95_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR96 - GICDA_IPRIORITYR96 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR96_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR96_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR96_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR96_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR96_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR96_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR96_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR96_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR96_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR96_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR96_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR96_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR96_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR96_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR96_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR96_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR96_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR96_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR96_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR96_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR97 - GICDA_IPRIORITYR97 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR97_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR97_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR97_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR97_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR97_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR97_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR97_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR97_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR97_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR97_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR97_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR97_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR97_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR97_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR97_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR97_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR97_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR97_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR97_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR97_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR98 - GICDA_IPRIORITYR98 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR98_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR98_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR98_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR98_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR98_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR98_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR98_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR98_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR98_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR98_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR98_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR98_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR98_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR98_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR98_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR98_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR98_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR98_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR98_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR98_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR99 - GICDA_IPRIORITYR99 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR99_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR99_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR99_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR99_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR99_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR99_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR99_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR99_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR99_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR99_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR99_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR99_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR99_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR99_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR99_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR99_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR99_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR99_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR99_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR99_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR100 - GICDA_IPRIORITYR100 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR100_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR100_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR100_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR100_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR100_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR100_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR100_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR100_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR100_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR100_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR100_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR100_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR100_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR100_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR100_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR100_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR100_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR100_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR100_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR100_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR101 - GICDA_IPRIORITYR101 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR101_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR101_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR101_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR101_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR101_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR101_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR101_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR101_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR101_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR101_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR101_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR101_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR101_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR101_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR101_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR101_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR101_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR101_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR101_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR101_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR102 - GICDA_IPRIORITYR102 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR102_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR102_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR102_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR102_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR102_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR102_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR102_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR102_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR102_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR102_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR102_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR102_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR102_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR102_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR102_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR102_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR102_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR102_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR102_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR102_offset3_MASK) /*! @} */ /*! @name GICDA_IPRIORITYR103 - GICDA_IPRIORITYR103 */ /*! @{ */ #define NOC_GICDA_GICDA_IPRIORITYR103_offset0_MASK (0xFFU) #define NOC_GICDA_GICDA_IPRIORITYR103_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR103_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR103_offset0_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR103_offset0_MASK) #define NOC_GICDA_GICDA_IPRIORITYR103_offset1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IPRIORITYR103_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR103_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR103_offset1_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR103_offset1_MASK) #define NOC_GICDA_GICDA_IPRIORITYR103_offset2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IPRIORITYR103_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR103_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR103_offset2_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR103_offset2_MASK) #define NOC_GICDA_GICDA_IPRIORITYR103_offset3_MASK (0xFF000000U) #define NOC_GICDA_GICDA_IPRIORITYR103_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICDA_GICDA_IPRIORITYR103_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IPRIORITYR103_offset3_SHIFT)) & NOC_GICDA_GICDA_IPRIORITYR103_offset3_MASK) /*! @} */ /*! @name GICDA_ICFGR2 - GICDA_ICFGR2 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR2_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR2_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR2_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR2_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR2_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR2_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR2_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR2_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR2_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR2_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR2_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR2_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR2_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR2_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR2_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR2_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR2_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR2_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR2_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR2_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR2_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR3 - GICDA_ICFGR3 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR3_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR3_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR3_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR3_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR3_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR3_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR3_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR3_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR3_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR3_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR3_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR3_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR3_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR3_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR3_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR3_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR3_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR3_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR3_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR3_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR3_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR4 - GICDA_ICFGR4 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR4_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR4_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR4_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR4_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR4_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR4_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR4_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR4_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR4_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR4_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR4_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR4_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR4_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR4_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR4_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR4_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR4_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR4_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR4_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR4_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR4_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR5 - GICDA_ICFGR5 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR5_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR5_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR5_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR5_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR5_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR5_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR5_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR5_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR5_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR5_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR5_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR5_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR5_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR5_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR5_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR5_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR5_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR5_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR5_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR5_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR5_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR6 - GICDA_ICFGR6 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR6_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR6_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR6_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR6_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR6_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR6_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR6_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR6_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR6_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR6_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR6_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR6_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR6_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR6_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR6_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR6_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR6_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR6_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR6_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR6_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR6_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR7 - GICDA_ICFGR7 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR7_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR7_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR7_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR7_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR7_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR7_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR7_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR7_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR7_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR7_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR7_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR7_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR7_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR7_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR7_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR7_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR7_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR7_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR7_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR7_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR7_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR8 - GICDA_ICFGR8 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR8_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR8_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR8_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR8_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR8_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR8_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR8_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR8_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR8_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR8_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR8_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR8_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR8_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR8_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR8_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR8_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR8_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR8_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR8_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR8_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR8_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR9 - GICDA_ICFGR9 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR9_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR9_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR9_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR9_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR9_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR9_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR9_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR9_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR9_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR9_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR9_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR9_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR9_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR9_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR9_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR9_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR9_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR9_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR9_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR9_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR9_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR10 - GICDA_ICFGR10 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR10_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR10_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR10_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR10_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR10_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR10_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR10_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR10_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR10_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR10_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR10_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR10_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR10_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR10_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR10_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR10_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR10_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR10_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR10_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR10_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR10_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR11 - GICDA_ICFGR11 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR11_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR11_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR11_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR11_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR11_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR11_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR11_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR11_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR11_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR11_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR11_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR11_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR11_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR11_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR11_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR11_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR11_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR11_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR11_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR11_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR11_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR12 - GICDA_ICFGR12 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR12_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR12_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR12_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR12_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR12_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR12_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR12_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR12_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR12_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR12_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR12_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR12_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR12_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR12_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR12_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR12_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR12_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR12_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR12_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR12_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR12_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR13 - GICDA_ICFGR13 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR13_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR13_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR13_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR13_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR13_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR13_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR13_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR13_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR13_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR13_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR13_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR13_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR13_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR13_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR13_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR13_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR13_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR13_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR13_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR13_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR13_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR14 - GICDA_ICFGR14 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR14_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR14_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR14_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR14_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR14_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR14_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR14_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR14_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR14_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR14_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR14_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR14_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR14_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR14_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR14_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR14_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR14_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR14_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR14_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR14_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR14_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR15 - GICDA_ICFGR15 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR15_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR15_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR15_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR15_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR15_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR15_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR15_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR15_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR15_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR15_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR15_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR15_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR15_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR15_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR15_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR15_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR15_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR15_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR15_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR15_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR15_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR16 - GICDA_ICFGR16 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR16_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR16_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR16_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR16_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR16_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR16_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR16_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR16_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR16_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR16_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR16_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR16_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR16_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR16_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR16_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR16_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR16_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR16_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR16_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR16_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR16_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR17 - GICDA_ICFGR17 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR17_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR17_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR17_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR17_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR17_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR17_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR17_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR17_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR17_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR17_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR17_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR17_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR17_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR17_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR17_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR17_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR17_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR17_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR17_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR17_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR17_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR18 - GICDA_ICFGR18 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR18_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR18_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR18_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR18_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR18_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR18_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR18_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR18_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR18_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR18_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR18_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR18_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR18_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR18_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR18_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR18_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR18_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR18_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR18_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR18_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR18_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR19 - GICDA_ICFGR19 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR19_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR19_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR19_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR19_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR19_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR19_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR19_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR19_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR19_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR19_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR19_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR19_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR19_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR19_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR19_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR19_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR19_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR19_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR19_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR19_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR19_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR20 - GICDA_ICFGR20 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR20_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR20_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR20_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR20_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR20_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR20_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR20_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR20_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR20_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR20_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR20_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR20_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR20_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR20_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR20_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR20_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR20_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR20_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR20_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR20_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR20_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR21 - GICDA_ICFGR21 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR21_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR21_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR21_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR21_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR21_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR21_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR21_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR21_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR21_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR21_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR21_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR21_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR21_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR21_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR21_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR21_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR21_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR21_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR21_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR21_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR21_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR22 - GICDA_ICFGR22 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR22_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR22_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR22_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR22_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR22_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR22_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR22_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR22_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR22_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR22_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR22_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR22_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR22_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR22_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR22_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR22_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR22_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR22_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR22_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR22_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR22_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR23 - GICDA_ICFGR23 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR23_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR23_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR23_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR23_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR23_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR23_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR23_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR23_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR23_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR23_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR23_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR23_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR23_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR23_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR23_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR23_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR23_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR23_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR23_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR23_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR23_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR24 - GICDA_ICFGR24 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR24_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR24_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR24_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR24_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR24_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR24_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR24_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR24_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR24_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR24_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR24_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR24_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR24_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR24_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR24_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR24_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR24_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR24_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR24_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR24_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR24_int_config15_MASK) /*! @} */ /*! @name GICDA_ICFGR25 - GICDA_ICFGR25 */ /*! @{ */ #define NOC_GICDA_GICDA_ICFGR25_int_config0_MASK (0x3U) #define NOC_GICDA_GICDA_ICFGR25_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config0_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config0_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config1_MASK (0xCU) #define NOC_GICDA_GICDA_ICFGR25_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config1_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config1_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config2_MASK (0x30U) #define NOC_GICDA_GICDA_ICFGR25_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config2_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config2_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICFGR25_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config3_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config3_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config4_MASK (0x300U) #define NOC_GICDA_GICDA_ICFGR25_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config4_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config4_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICFGR25_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config5_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config5_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICFGR25_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config6_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config6_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICFGR25_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config7_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config7_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICFGR25_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config8_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config8_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICFGR25_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config9_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config9_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICFGR25_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config10_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config10_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICFGR25_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config11_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config11_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICFGR25_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config12_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config12_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICFGR25_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config13_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config13_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICFGR25_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config14_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config14_MASK) #define NOC_GICDA_GICDA_ICFGR25_int_config15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICFGR25_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICDA_GICDA_ICFGR25_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICFGR25_int_config15_SHIFT)) & NOC_GICDA_GICDA_ICFGR25_int_config15_MASK) /*! @} */ /*! @name GICDA_IGRPMODR1 - GICDA_IGRPMODR1 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR1_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR2 - GICDA_IGRPMODR2 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR2_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR3 - GICDA_IGRPMODR3 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR3_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR4 - GICDA_IGRPMODR4 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR4_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR5 - GICDA_IGRPMODR5 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR5_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR6 - GICDA_IGRPMODR6 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR6_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR7 - GICDA_IGRPMODR7 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR7_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR8 - GICDA_IGRPMODR8 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR8_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR9 - GICDA_IGRPMODR9 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR9_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR10 - GICDA_IGRPMODR10 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR10_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR11 - GICDA_IGRPMODR11 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR11_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_IGRPMODR12 - GICDA_IGRPMODR12 */ /*! @{ */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit0_MASK (0x1U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit0_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit0_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit1_MASK (0x2U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit1_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit1_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit2_MASK (0x4U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit2_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit2_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit3_MASK (0x8U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit3_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit3_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit4_MASK (0x10U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit4_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit4_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit5_MASK (0x20U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit5_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit5_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit6_MASK (0x40U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit6_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit6_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit7_MASK (0x80U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit7_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit7_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit8_MASK (0x100U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit8_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit8_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit9_MASK (0x200U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit9_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit9_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit10_MASK (0x400U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit10_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit10_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit11_MASK (0x800U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit11_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit11_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit12_MASK (0x1000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit12_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit12_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit13_MASK (0x2000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit13_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit13_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit14_MASK (0x4000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit14_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit14_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit15_MASK (0x8000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit15_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit15_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit16_MASK (0x10000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit16_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit16_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit17_MASK (0x20000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit17_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit17_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit18_MASK (0x40000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit18_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit18_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit19_MASK (0x80000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit19_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit19_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit20_MASK (0x100000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit20_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit20_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit21_MASK (0x200000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit21_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit21_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit22_MASK (0x400000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit22_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit22_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit23_MASK (0x800000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit23_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit23_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit24_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit24_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit25_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit25_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit26_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit26_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit27_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit27_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit28_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit28_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit29_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit29_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit30_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit30_MASK) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit31_SHIFT)) & NOC_GICDA_GICDA_IGRPMODR12_group_modifier_bit31_MASK) /*! @} */ /*! @name GICDA_NSACR2 - GICDA_NSACR2 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR2_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR2_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR2_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR2_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR2_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR2_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR2_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR2_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR2_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR2_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR2_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR2_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR2_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR2_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR2_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR2_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR2_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR2_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR2_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR2_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR2_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR2_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR2_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR2_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR2_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR2_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR2_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR2_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR2_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR2_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR2_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR2_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR2_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR2_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR2_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR2_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR3 - GICDA_NSACR3 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR3_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR3_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR3_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR3_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR3_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR3_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR3_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR3_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR3_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR3_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR3_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR3_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR3_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR3_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR3_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR3_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR3_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR3_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR3_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR3_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR3_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR3_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR3_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR3_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR3_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR3_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR3_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR3_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR3_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR3_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR3_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR3_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR3_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR3_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR3_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR3_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR4 - GICDA_NSACR4 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR4_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR4_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR4_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR4_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR4_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR4_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR4_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR4_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR4_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR4_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR4_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR4_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR4_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR4_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR4_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR4_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR4_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR4_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR4_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR4_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR4_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR4_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR4_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR4_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR4_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR4_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR4_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR4_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR4_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR4_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR4_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR4_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR4_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR4_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR4_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR4_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR5 - GICDA_NSACR5 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR5_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR5_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR5_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR5_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR5_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR5_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR5_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR5_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR5_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR5_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR5_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR5_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR5_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR5_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR5_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR5_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR5_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR5_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR5_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR5_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR5_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR5_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR5_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR5_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR5_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR5_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR5_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR5_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR5_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR5_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR5_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR5_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR5_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR5_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR5_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR5_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR6 - GICDA_NSACR6 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR6_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR6_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR6_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR6_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR6_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR6_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR6_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR6_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR6_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR6_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR6_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR6_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR6_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR6_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR6_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR6_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR6_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR6_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR6_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR6_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR6_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR6_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR6_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR6_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR6_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR6_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR6_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR6_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR6_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR6_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR6_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR6_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR6_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR6_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR6_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR6_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR7 - GICDA_NSACR7 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR7_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR7_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR7_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR7_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR7_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR7_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR7_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR7_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR7_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR7_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR7_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR7_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR7_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR7_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR7_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR7_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR7_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR7_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR7_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR7_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR7_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR7_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR7_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR7_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR7_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR7_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR7_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR7_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR7_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR7_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR7_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR7_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR7_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR7_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR7_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR7_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR8 - GICDA_NSACR8 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR8_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR8_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR8_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR8_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR8_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR8_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR8_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR8_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR8_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR8_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR8_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR8_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR8_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR8_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR8_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR8_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR8_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR8_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR8_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR8_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR8_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR8_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR8_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR8_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR8_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR8_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR8_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR8_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR8_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR8_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR8_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR8_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR8_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR8_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR8_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR8_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR9 - GICDA_NSACR9 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR9_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR9_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR9_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR9_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR9_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR9_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR9_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR9_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR9_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR9_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR9_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR9_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR9_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR9_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR9_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR9_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR9_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR9_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR9_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR9_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR9_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR9_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR9_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR9_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR9_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR9_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR9_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR9_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR9_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR9_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR9_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR9_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR9_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR9_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR9_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR9_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR10 - GICDA_NSACR10 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR10_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR10_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR10_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR10_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR10_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR10_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR10_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR10_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR10_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR10_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR10_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR10_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR10_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR10_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR10_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR10_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR10_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR10_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR10_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR10_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR10_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR10_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR10_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR10_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR10_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR10_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR10_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR10_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR10_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR10_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR10_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR10_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR10_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR10_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR10_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR10_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR11 - GICDA_NSACR11 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR11_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR11_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR11_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR11_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR11_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR11_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR11_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR11_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR11_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR11_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR11_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR11_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR11_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR11_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR11_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR11_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR11_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR11_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR11_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR11_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR11_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR11_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR11_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR11_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR11_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR11_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR11_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR11_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR11_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR11_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR11_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR11_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR11_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR11_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR11_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR11_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR12 - GICDA_NSACR12 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR12_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR12_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR12_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR12_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR12_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR12_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR12_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR12_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR12_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR12_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR12_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR12_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR12_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR12_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR12_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR12_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR12_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR12_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR12_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR12_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR12_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR12_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR12_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR12_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR12_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR12_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR12_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR12_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR12_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR12_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR12_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR12_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR12_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR12_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR12_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR12_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR13 - GICDA_NSACR13 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR13_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR13_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR13_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR13_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR13_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR13_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR13_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR13_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR13_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR13_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR13_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR13_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR13_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR13_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR13_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR13_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR13_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR13_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR13_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR13_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR13_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR13_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR13_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR13_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR13_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR13_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR13_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR13_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR13_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR13_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR13_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR13_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR13_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR13_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR13_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR13_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR14 - GICDA_NSACR14 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR14_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR14_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR14_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR14_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR14_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR14_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR14_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR14_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR14_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR14_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR14_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR14_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR14_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR14_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR14_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR14_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR14_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR14_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR14_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR14_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR14_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR14_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR14_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR14_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR14_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR14_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR14_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR14_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR14_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR14_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR14_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR14_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR14_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR14_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR14_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR14_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR15 - GICDA_NSACR15 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR15_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR15_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR15_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR15_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR15_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR15_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR15_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR15_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR15_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR15_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR15_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR15_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR15_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR15_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR15_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR15_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR15_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR15_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR15_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR15_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR15_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR15_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR15_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR15_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR15_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR15_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR15_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR15_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR15_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR15_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR15_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR15_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR15_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR15_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR15_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR15_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR16 - GICDA_NSACR16 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR16_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR16_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR16_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR16_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR16_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR16_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR16_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR16_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR16_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR16_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR16_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR16_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR16_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR16_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR16_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR16_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR16_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR16_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR16_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR16_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR16_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR16_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR16_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR16_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR16_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR16_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR16_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR16_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR16_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR16_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR16_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR16_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR16_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR16_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR16_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR16_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR17 - GICDA_NSACR17 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR17_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR17_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR17_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR17_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR17_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR17_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR17_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR17_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR17_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR17_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR17_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR17_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR17_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR17_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR17_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR17_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR17_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR17_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR17_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR17_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR17_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR17_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR17_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR17_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR17_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR17_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR17_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR17_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR17_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR17_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR17_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR17_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR17_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR17_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR17_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR17_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR18 - GICDA_NSACR18 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR18_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR18_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR18_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR18_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR18_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR18_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR18_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR18_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR18_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR18_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR18_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR18_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR18_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR18_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR18_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR18_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR18_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR18_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR18_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR18_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR18_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR18_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR18_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR18_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR18_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR18_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR18_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR18_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR18_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR18_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR18_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR18_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR18_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR18_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR18_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR18_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR19 - GICDA_NSACR19 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR19_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR19_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR19_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR19_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR19_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR19_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR19_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR19_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR19_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR19_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR19_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR19_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR19_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR19_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR19_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR19_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR19_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR19_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR19_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR19_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR19_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR19_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR19_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR19_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR19_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR19_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR19_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR19_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR19_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR19_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR19_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR19_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR19_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR19_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR19_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR19_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR20 - GICDA_NSACR20 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR20_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR20_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR20_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR20_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR20_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR20_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR20_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR20_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR20_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR20_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR20_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR20_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR20_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR20_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR20_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR20_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR20_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR20_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR20_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR20_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR20_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR20_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR20_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR20_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR20_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR20_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR20_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR20_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR20_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR20_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR20_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR20_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR20_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR20_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR20_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR20_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR21 - GICDA_NSACR21 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR21_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR21_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR21_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR21_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR21_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR21_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR21_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR21_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR21_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR21_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR21_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR21_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR21_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR21_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR21_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR21_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR21_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR21_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR21_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR21_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR21_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR21_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR21_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR21_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR21_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR21_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR21_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR21_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR21_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR21_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR21_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR21_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR21_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR21_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR21_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR21_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR22 - GICDA_NSACR22 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR22_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR22_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR22_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR22_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR22_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR22_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR22_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR22_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR22_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR22_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR22_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR22_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR22_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR22_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR22_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR22_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR22_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR22_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR22_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR22_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR22_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR22_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR22_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR22_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR22_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR22_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR22_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR22_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR22_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR22_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR22_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR22_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR22_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR22_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR22_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR22_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR23 - GICDA_NSACR23 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR23_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR23_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR23_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR23_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR23_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR23_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR23_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR23_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR23_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR23_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR23_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR23_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR23_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR23_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR23_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR23_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR23_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR23_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR23_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR23_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR23_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR23_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR23_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR23_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR23_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR23_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR23_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR23_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR23_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR23_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR23_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR23_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR23_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR23_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR23_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR23_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR24 - GICDA_NSACR24 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR24_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR24_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR24_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR24_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR24_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR24_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR24_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR24_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR24_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR24_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR24_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR24_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR24_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR24_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR24_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR24_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR24_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR24_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR24_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR24_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR24_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR24_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR24_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR24_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR24_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR24_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR24_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR24_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR24_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR24_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR24_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR24_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR24_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR24_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR24_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR24_ns_access15_MASK) /*! @} */ /*! @name GICDA_NSACR25 - GICDA_NSACR25 */ /*! @{ */ #define NOC_GICDA_GICDA_NSACR25_ns_access0_MASK (0x3U) #define NOC_GICDA_GICDA_NSACR25_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICDA_GICDA_NSACR25_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access0_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access0_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access1_MASK (0xCU) #define NOC_GICDA_GICDA_NSACR25_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICDA_GICDA_NSACR25_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access1_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access1_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access2_MASK (0x30U) #define NOC_GICDA_GICDA_NSACR25_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICDA_GICDA_NSACR25_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access2_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access2_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access3_MASK (0xC0U) #define NOC_GICDA_GICDA_NSACR25_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICDA_GICDA_NSACR25_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access3_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access3_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access4_MASK (0x300U) #define NOC_GICDA_GICDA_NSACR25_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICDA_GICDA_NSACR25_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access4_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access4_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access5_MASK (0xC00U) #define NOC_GICDA_GICDA_NSACR25_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICDA_GICDA_NSACR25_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access5_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access5_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access6_MASK (0x3000U) #define NOC_GICDA_GICDA_NSACR25_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICDA_GICDA_NSACR25_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access6_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access6_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access7_MASK (0xC000U) #define NOC_GICDA_GICDA_NSACR25_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICDA_GICDA_NSACR25_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access7_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access7_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access8_MASK (0x30000U) #define NOC_GICDA_GICDA_NSACR25_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICDA_GICDA_NSACR25_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access8_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access8_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access9_MASK (0xC0000U) #define NOC_GICDA_GICDA_NSACR25_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICDA_GICDA_NSACR25_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access9_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access9_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access10_MASK (0x300000U) #define NOC_GICDA_GICDA_NSACR25_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICDA_GICDA_NSACR25_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access10_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access10_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access11_MASK (0xC00000U) #define NOC_GICDA_GICDA_NSACR25_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICDA_GICDA_NSACR25_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access11_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access11_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access12_MASK (0x3000000U) #define NOC_GICDA_GICDA_NSACR25_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICDA_GICDA_NSACR25_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access12_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access12_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access13_MASK (0xC000000U) #define NOC_GICDA_GICDA_NSACR25_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICDA_GICDA_NSACR25_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access13_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access13_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access14_MASK (0x30000000U) #define NOC_GICDA_GICDA_NSACR25_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICDA_GICDA_NSACR25_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access14_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access14_MASK) #define NOC_GICDA_GICDA_NSACR25_ns_access15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_NSACR25_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICDA_GICDA_NSACR25_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_NSACR25_ns_access15_SHIFT)) & NOC_GICDA_GICDA_NSACR25_ns_access15_MASK) /*! @} */ /*! @name GICDA_IROUTER32 - GICDA_IROUTER32 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER32_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER32_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER32_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER32_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER32_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER32_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER32_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER32_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER32_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER32_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER32_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER32_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER32_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER32_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER32_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER32_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER32_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER32_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER32_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER32_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER32_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER32_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER32_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER32_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER32_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER32_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER32_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER32_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER32_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER32_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER32_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER32_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER32_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER32_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER32_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER33 - GICDA_IROUTER33 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER33_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER33_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER33_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER33_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER33_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER33_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER33_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER33_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER33_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER33_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER33_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER33_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER33_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER33_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER33_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER33_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER33_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER33_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER33_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER33_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER33_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER33_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER33_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER33_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER33_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER33_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER33_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER33_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER33_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER33_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER33_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER33_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER33_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER33_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER33_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER34 - GICDA_IROUTER34 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER34_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER34_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER34_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER34_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER34_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER34_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER34_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER34_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER34_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER34_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER34_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER34_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER34_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER34_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER34_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER34_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER34_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER34_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER34_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER34_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER34_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER34_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER34_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER34_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER34_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER34_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER34_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER34_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER34_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER34_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER34_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER34_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER34_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER34_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER34_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER35 - GICDA_IROUTER35 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER35_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER35_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER35_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER35_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER35_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER35_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER35_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER35_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER35_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER35_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER35_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER35_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER35_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER35_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER35_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER35_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER35_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER35_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER35_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER35_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER35_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER35_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER35_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER35_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER35_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER35_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER35_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER35_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER35_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER35_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER35_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER35_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER35_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER35_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER35_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER36 - GICDA_IROUTER36 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER36_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER36_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER36_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER36_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER36_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER36_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER36_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER36_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER36_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER36_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER36_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER36_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER36_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER36_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER36_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER36_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER36_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER36_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER36_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER36_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER36_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER36_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER36_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER36_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER36_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER36_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER36_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER36_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER36_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER36_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER36_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER36_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER36_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER36_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER36_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER37 - GICDA_IROUTER37 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER37_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER37_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER37_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER37_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER37_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER37_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER37_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER37_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER37_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER37_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER37_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER37_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER37_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER37_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER37_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER37_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER37_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER37_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER37_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER37_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER37_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER37_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER37_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER37_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER37_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER37_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER37_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER37_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER37_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER37_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER37_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER37_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER37_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER37_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER37_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER38 - GICDA_IROUTER38 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER38_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER38_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER38_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER38_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER38_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER38_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER38_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER38_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER38_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER38_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER38_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER38_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER38_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER38_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER38_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER38_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER38_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER38_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER38_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER38_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER38_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER38_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER38_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER38_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER38_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER38_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER38_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER38_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER38_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER38_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER38_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER38_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER38_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER38_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER38_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER39 - GICDA_IROUTER39 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER39_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER39_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER39_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER39_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER39_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER39_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER39_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER39_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER39_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER39_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER39_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER39_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER39_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER39_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER39_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER39_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER39_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER39_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER39_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER39_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER39_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER39_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER39_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER39_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER39_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER39_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER39_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER39_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER39_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER39_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER39_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER39_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER39_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER39_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER39_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER40 - GICDA_IROUTER40 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER40_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER40_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER40_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER40_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER40_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER40_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER40_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER40_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER40_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER40_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER40_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER40_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER40_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER40_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER40_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER40_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER40_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER40_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER40_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER40_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER40_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER40_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER40_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER40_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER40_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER40_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER40_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER40_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER40_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER40_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER40_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER40_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER40_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER40_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER40_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER41 - GICDA_IROUTER41 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER41_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER41_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER41_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER41_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER41_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER41_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER41_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER41_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER41_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER41_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER41_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER41_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER41_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER41_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER41_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER41_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER41_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER41_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER41_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER41_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER41_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER41_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER41_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER41_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER41_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER41_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER41_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER41_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER41_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER41_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER41_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER41_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER41_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER41_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER41_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER42 - GICDA_IROUTER42 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER42_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER42_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER42_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER42_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER42_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER42_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER42_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER42_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER42_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER42_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER42_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER42_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER42_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER42_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER42_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER42_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER42_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER42_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER42_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER42_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER42_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER42_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER42_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER42_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER42_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER42_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER42_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER42_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER42_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER42_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER42_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER42_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER42_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER42_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER42_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER43 - GICDA_IROUTER43 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER43_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER43_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER43_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER43_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER43_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER43_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER43_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER43_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER43_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER43_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER43_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER43_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER43_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER43_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER43_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER43_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER43_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER43_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER43_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER43_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER43_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER43_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER43_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER43_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER43_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER43_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER43_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER43_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER43_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER43_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER43_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER43_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER43_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER43_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER43_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER44 - GICDA_IROUTER44 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER44_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER44_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER44_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER44_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER44_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER44_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER44_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER44_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER44_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER44_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER44_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER44_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER44_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER44_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER44_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER44_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER44_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER44_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER44_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER44_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER44_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER44_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER44_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER44_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER44_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER44_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER44_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER44_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER44_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER44_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER44_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER44_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER44_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER44_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER44_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER45 - GICDA_IROUTER45 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER45_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER45_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER45_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER45_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER45_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER45_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER45_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER45_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER45_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER45_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER45_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER45_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER45_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER45_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER45_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER45_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER45_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER45_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER45_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER45_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER45_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER45_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER45_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER45_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER45_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER45_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER45_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER45_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER45_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER45_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER45_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER45_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER45_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER45_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER45_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER46 - GICDA_IROUTER46 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER46_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER46_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER46_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER46_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER46_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER46_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER46_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER46_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER46_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER46_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER46_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER46_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER46_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER46_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER46_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER46_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER46_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER46_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER46_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER46_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER46_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER46_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER46_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER46_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER46_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER46_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER46_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER46_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER46_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER46_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER46_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER46_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER46_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER46_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER46_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER47 - GICDA_IROUTER47 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER47_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER47_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER47_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER47_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER47_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER47_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER47_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER47_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER47_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER47_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER47_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER47_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER47_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER47_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER47_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER47_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER47_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER47_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER47_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER47_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER47_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER47_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER47_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER47_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER47_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER47_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER47_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER47_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER47_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER47_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER47_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER47_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER47_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER47_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER47_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER48 - GICDA_IROUTER48 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER48_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER48_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER48_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER48_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER48_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER48_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER48_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER48_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER48_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER48_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER48_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER48_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER48_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER48_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER48_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER48_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER48_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER48_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER48_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER48_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER48_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER48_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER48_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER48_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER48_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER48_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER48_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER48_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER48_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER48_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER48_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER48_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER48_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER48_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER48_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER49 - GICDA_IROUTER49 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER49_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER49_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER49_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER49_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER49_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER49_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER49_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER49_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER49_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER49_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER49_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER49_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER49_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER49_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER49_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER49_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER49_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER49_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER49_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER49_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER49_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER49_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER49_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER49_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER49_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER49_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER49_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER49_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER49_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER49_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER49_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER49_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER49_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER49_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER49_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER50 - GICDA_IROUTER50 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER50_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER50_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER50_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER50_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER50_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER50_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER50_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER50_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER50_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER50_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER50_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER50_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER50_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER50_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER50_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER50_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER50_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER50_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER50_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER50_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER50_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER50_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER50_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER50_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER50_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER50_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER50_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER50_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER50_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER50_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER50_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER50_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER50_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER50_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER50_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER51 - GICDA_IROUTER51 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER51_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER51_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER51_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER51_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER51_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER51_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER51_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER51_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER51_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER51_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER51_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER51_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER51_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER51_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER51_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER51_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER51_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER51_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER51_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER51_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER51_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER51_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER51_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER51_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER51_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER51_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER51_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER51_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER51_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER51_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER51_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER51_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER51_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER51_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER51_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER52 - GICDA_IROUTER52 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER52_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER52_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER52_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER52_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER52_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER52_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER52_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER52_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER52_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER52_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER52_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER52_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER52_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER52_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER52_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER52_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER52_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER52_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER52_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER52_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER52_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER52_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER52_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER52_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER52_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER52_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER52_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER52_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER52_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER52_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER52_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER52_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER52_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER52_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER52_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER53 - GICDA_IROUTER53 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER53_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER53_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER53_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER53_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER53_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER53_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER53_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER53_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER53_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER53_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER53_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER53_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER53_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER53_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER53_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER53_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER53_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER53_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER53_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER53_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER53_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER53_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER53_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER53_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER53_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER53_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER53_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER53_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER53_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER53_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER53_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER53_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER53_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER53_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER53_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER54 - GICDA_IROUTER54 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER54_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER54_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER54_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER54_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER54_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER54_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER54_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER54_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER54_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER54_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER54_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER54_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER54_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER54_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER54_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER54_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER54_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER54_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER54_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER54_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER54_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER54_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER54_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER54_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER54_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER54_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER54_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER54_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER54_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER54_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER54_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER54_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER54_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER54_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER54_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER55 - GICDA_IROUTER55 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER55_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER55_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER55_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER55_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER55_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER55_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER55_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER55_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER55_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER55_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER55_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER55_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER55_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER55_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER55_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER55_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER55_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER55_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER55_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER55_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER55_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER55_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER55_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER55_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER55_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER55_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER55_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER55_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER55_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER55_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER55_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER55_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER55_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER55_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER55_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER56 - GICDA_IROUTER56 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER56_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER56_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER56_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER56_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER56_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER56_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER56_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER56_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER56_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER56_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER56_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER56_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER56_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER56_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER56_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER56_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER56_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER56_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER56_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER56_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER56_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER56_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER56_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER56_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER56_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER56_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER56_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER56_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER56_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER56_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER56_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER56_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER56_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER56_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER56_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER57 - GICDA_IROUTER57 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER57_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER57_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER57_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER57_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER57_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER57_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER57_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER57_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER57_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER57_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER57_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER57_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER57_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER57_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER57_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER57_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER57_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER57_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER57_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER57_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER57_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER57_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER57_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER57_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER57_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER57_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER57_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER57_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER57_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER57_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER57_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER57_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER57_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER57_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER57_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER58 - GICDA_IROUTER58 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER58_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER58_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER58_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER58_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER58_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER58_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER58_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER58_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER58_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER58_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER58_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER58_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER58_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER58_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER58_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER58_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER58_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER58_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER58_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER58_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER58_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER58_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER58_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER58_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER58_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER58_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER58_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER58_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER58_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER58_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER58_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER58_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER58_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER58_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER58_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER59 - GICDA_IROUTER59 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER59_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER59_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER59_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER59_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER59_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER59_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER59_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER59_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER59_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER59_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER59_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER59_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER59_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER59_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER59_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER59_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER59_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER59_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER59_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER59_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER59_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER59_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER59_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER59_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER59_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER59_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER59_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER59_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER59_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER59_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER59_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER59_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER59_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER59_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER59_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER60 - GICDA_IROUTER60 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER60_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER60_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER60_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER60_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER60_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER60_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER60_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER60_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER60_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER60_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER60_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER60_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER60_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER60_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER60_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER60_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER60_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER60_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER60_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER60_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER60_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER60_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER60_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER60_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER60_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER60_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER60_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER60_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER60_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER60_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER60_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER60_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER60_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER60_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER60_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER61 - GICDA_IROUTER61 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER61_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER61_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER61_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER61_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER61_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER61_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER61_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER61_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER61_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER61_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER61_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER61_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER61_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER61_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER61_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER61_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER61_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER61_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER61_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER61_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER61_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER61_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER61_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER61_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER61_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER61_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER61_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER61_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER61_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER61_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER61_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER61_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER61_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER61_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER61_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER62 - GICDA_IROUTER62 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER62_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER62_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER62_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER62_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER62_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER62_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER62_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER62_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER62_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER62_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER62_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER62_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER62_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER62_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER62_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER62_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER62_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER62_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER62_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER62_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER62_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER62_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER62_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER62_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER62_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER62_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER62_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER62_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER62_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER62_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER62_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER62_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER62_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER62_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER62_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER63 - GICDA_IROUTER63 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER63_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER63_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER63_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER63_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER63_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER63_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER63_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER63_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER63_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER63_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER63_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER63_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER63_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER63_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER63_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER63_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER63_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER63_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER63_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER63_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER63_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER63_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER63_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER63_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER63_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER63_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER63_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER63_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER63_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER63_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER63_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER63_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER63_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER63_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER63_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER64 - GICDA_IROUTER64 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER64_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER64_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER64_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER64_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER64_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER64_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER64_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER64_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER64_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER64_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER64_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER64_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER64_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER64_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER64_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER64_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER64_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER64_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER64_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER64_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER64_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER64_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER64_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER64_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER64_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER64_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER64_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER64_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER64_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER64_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER64_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER64_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER64_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER64_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER64_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER65 - GICDA_IROUTER65 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER65_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER65_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER65_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER65_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER65_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER65_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER65_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER65_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER65_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER65_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER65_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER65_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER65_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER65_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER65_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER65_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER65_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER65_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER65_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER65_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER65_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER65_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER65_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER65_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER65_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER65_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER65_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER65_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER65_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER65_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER65_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER65_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER65_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER65_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER65_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER66 - GICDA_IROUTER66 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER66_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER66_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER66_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER66_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER66_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER66_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER66_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER66_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER66_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER66_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER66_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER66_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER66_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER66_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER66_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER66_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER66_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER66_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER66_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER66_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER66_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER66_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER66_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER66_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER66_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER66_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER66_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER66_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER66_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER66_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER66_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER66_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER66_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER66_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER66_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER67 - GICDA_IROUTER67 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER67_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER67_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER67_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER67_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER67_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER67_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER67_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER67_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER67_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER67_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER67_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER67_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER67_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER67_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER67_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER67_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER67_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER67_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER67_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER67_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER67_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER67_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER67_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER67_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER67_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER67_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER67_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER67_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER67_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER67_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER67_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER67_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER67_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER67_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER67_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER68 - GICDA_IROUTER68 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER68_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER68_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER68_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER68_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER68_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER68_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER68_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER68_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER68_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER68_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER68_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER68_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER68_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER68_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER68_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER68_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER68_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER68_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER68_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER68_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER68_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER68_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER68_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER68_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER68_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER68_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER68_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER68_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER68_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER68_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER68_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER68_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER68_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER68_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER68_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER69 - GICDA_IROUTER69 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER69_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER69_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER69_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER69_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER69_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER69_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER69_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER69_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER69_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER69_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER69_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER69_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER69_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER69_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER69_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER69_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER69_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER69_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER69_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER69_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER69_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER69_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER69_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER69_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER69_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER69_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER69_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER69_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER69_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER69_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER69_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER69_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER69_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER69_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER69_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER70 - GICDA_IROUTER70 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER70_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER70_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER70_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER70_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER70_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER70_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER70_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER70_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER70_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER70_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER70_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER70_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER70_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER70_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER70_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER70_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER70_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER70_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER70_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER70_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER70_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER70_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER70_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER70_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER70_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER70_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER70_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER70_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER70_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER70_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER70_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER70_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER70_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER70_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER70_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER71 - GICDA_IROUTER71 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER71_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER71_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER71_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER71_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER71_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER71_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER71_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER71_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER71_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER71_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER71_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER71_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER71_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER71_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER71_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER71_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER71_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER71_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER71_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER71_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER71_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER71_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER71_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER71_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER71_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER71_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER71_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER71_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER71_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER71_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER71_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER71_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER71_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER71_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER71_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER72 - GICDA_IROUTER72 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER72_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER72_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER72_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER72_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER72_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER72_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER72_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER72_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER72_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER72_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER72_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER72_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER72_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER72_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER72_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER72_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER72_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER72_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER72_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER72_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER72_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER72_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER72_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER72_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER72_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER72_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER72_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER72_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER72_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER72_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER72_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER72_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER72_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER72_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER72_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER73 - GICDA_IROUTER73 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER73_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER73_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER73_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER73_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER73_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER73_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER73_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER73_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER73_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER73_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER73_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER73_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER73_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER73_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER73_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER73_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER73_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER73_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER73_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER73_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER73_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER73_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER73_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER73_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER73_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER73_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER73_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER73_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER73_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER73_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER73_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER73_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER73_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER73_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER73_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER74 - GICDA_IROUTER74 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER74_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER74_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER74_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER74_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER74_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER74_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER74_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER74_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER74_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER74_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER74_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER74_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER74_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER74_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER74_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER74_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER74_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER74_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER74_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER74_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER74_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER74_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER74_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER74_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER74_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER74_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER74_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER74_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER74_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER74_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER74_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER74_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER74_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER74_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER74_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER75 - GICDA_IROUTER75 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER75_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER75_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER75_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER75_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER75_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER75_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER75_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER75_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER75_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER75_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER75_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER75_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER75_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER75_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER75_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER75_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER75_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER75_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER75_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER75_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER75_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER75_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER75_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER75_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER75_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER75_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER75_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER75_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER75_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER75_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER75_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER75_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER75_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER75_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER75_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER76 - GICDA_IROUTER76 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER76_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER76_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER76_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER76_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER76_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER76_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER76_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER76_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER76_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER76_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER76_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER76_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER76_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER76_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER76_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER76_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER76_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER76_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER76_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER76_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER76_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER76_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER76_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER76_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER76_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER76_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER76_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER76_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER76_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER76_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER76_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER76_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER76_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER76_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER76_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER77 - GICDA_IROUTER77 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER77_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER77_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER77_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER77_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER77_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER77_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER77_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER77_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER77_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER77_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER77_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER77_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER77_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER77_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER77_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER77_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER77_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER77_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER77_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER77_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER77_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER77_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER77_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER77_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER77_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER77_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER77_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER77_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER77_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER77_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER77_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER77_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER77_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER77_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER77_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER78 - GICDA_IROUTER78 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER78_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER78_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER78_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER78_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER78_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER78_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER78_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER78_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER78_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER78_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER78_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER78_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER78_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER78_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER78_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER78_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER78_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER78_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER78_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER78_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER78_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER78_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER78_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER78_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER78_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER78_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER78_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER78_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER78_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER78_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER78_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER78_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER78_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER78_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER78_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER79 - GICDA_IROUTER79 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER79_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER79_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER79_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER79_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER79_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER79_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER79_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER79_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER79_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER79_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER79_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER79_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER79_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER79_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER79_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER79_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER79_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER79_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER79_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER79_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER79_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER79_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER79_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER79_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER79_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER79_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER79_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER79_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER79_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER79_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER79_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER79_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER79_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER79_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER79_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER80 - GICDA_IROUTER80 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER80_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER80_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER80_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER80_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER80_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER80_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER80_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER80_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER80_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER80_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER80_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER80_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER80_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER80_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER80_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER80_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER80_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER80_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER80_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER80_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER80_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER80_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER80_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER80_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER80_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER80_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER80_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER80_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER80_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER80_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER80_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER80_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER80_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER80_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER80_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER81 - GICDA_IROUTER81 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER81_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER81_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER81_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER81_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER81_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER81_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER81_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER81_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER81_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER81_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER81_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER81_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER81_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER81_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER81_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER81_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER81_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER81_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER81_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER81_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER81_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER81_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER81_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER81_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER81_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER81_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER81_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER81_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER81_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER81_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER81_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER81_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER81_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER81_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER81_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER82 - GICDA_IROUTER82 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER82_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER82_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER82_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER82_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER82_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER82_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER82_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER82_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER82_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER82_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER82_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER82_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER82_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER82_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER82_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER82_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER82_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER82_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER82_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER82_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER82_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER82_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER82_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER82_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER82_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER82_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER82_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER82_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER82_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER82_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER82_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER82_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER82_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER82_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER82_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER83 - GICDA_IROUTER83 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER83_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER83_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER83_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER83_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER83_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER83_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER83_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER83_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER83_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER83_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER83_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER83_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER83_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER83_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER83_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER83_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER83_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER83_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER83_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER83_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER83_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER83_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER83_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER83_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER83_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER83_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER83_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER83_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER83_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER83_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER83_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER83_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER83_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER83_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER83_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER84 - GICDA_IROUTER84 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER84_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER84_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER84_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER84_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER84_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER84_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER84_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER84_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER84_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER84_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER84_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER84_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER84_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER84_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER84_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER84_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER84_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER84_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER84_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER84_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER84_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER84_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER84_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER84_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER84_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER84_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER84_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER84_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER84_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER84_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER84_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER84_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER84_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER84_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER84_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER85 - GICDA_IROUTER85 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER85_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER85_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER85_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER85_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER85_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER85_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER85_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER85_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER85_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER85_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER85_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER85_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER85_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER85_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER85_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER85_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER85_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER85_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER85_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER85_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER85_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER85_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER85_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER85_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER85_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER85_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER85_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER85_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER85_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER85_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER85_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER85_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER85_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER85_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER85_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER86 - GICDA_IROUTER86 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER86_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER86_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER86_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER86_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER86_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER86_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER86_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER86_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER86_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER86_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER86_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER86_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER86_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER86_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER86_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER86_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER86_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER86_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER86_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER86_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER86_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER86_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER86_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER86_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER86_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER86_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER86_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER86_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER86_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER86_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER86_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER86_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER86_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER86_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER86_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER87 - GICDA_IROUTER87 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER87_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER87_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER87_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER87_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER87_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER87_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER87_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER87_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER87_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER87_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER87_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER87_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER87_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER87_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER87_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER87_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER87_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER87_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER87_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER87_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER87_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER87_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER87_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER87_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER87_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER87_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER87_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER87_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER87_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER87_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER87_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER87_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER87_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER87_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER87_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER88 - GICDA_IROUTER88 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER88_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER88_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER88_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER88_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER88_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER88_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER88_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER88_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER88_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER88_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER88_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER88_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER88_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER88_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER88_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER88_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER88_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER88_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER88_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER88_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER88_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER88_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER88_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER88_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER88_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER88_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER88_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER88_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER88_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER88_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER88_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER88_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER88_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER88_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER88_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER89 - GICDA_IROUTER89 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER89_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER89_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER89_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER89_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER89_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER89_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER89_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER89_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER89_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER89_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER89_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER89_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER89_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER89_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER89_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER89_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER89_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER89_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER89_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER89_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER89_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER89_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER89_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER89_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER89_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER89_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER89_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER89_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER89_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER89_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER89_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER89_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER89_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER89_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER89_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER90 - GICDA_IROUTER90 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER90_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER90_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER90_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER90_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER90_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER90_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER90_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER90_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER90_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER90_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER90_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER90_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER90_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER90_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER90_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER90_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER90_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER90_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER90_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER90_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER90_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER90_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER90_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER90_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER90_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER90_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER90_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER90_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER90_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER90_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER90_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER90_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER90_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER90_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER90_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER91 - GICDA_IROUTER91 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER91_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER91_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER91_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER91_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER91_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER91_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER91_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER91_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER91_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER91_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER91_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER91_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER91_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER91_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER91_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER91_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER91_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER91_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER91_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER91_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER91_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER91_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER91_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER91_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER91_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER91_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER91_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER91_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER91_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER91_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER91_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER91_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER91_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER91_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER91_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER92 - GICDA_IROUTER92 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER92_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER92_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER92_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER92_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER92_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER92_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER92_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER92_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER92_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER92_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER92_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER92_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER92_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER92_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER92_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER92_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER92_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER92_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER92_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER92_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER92_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER92_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER92_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER92_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER92_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER92_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER92_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER92_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER92_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER92_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER92_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER92_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER92_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER92_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER92_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER93 - GICDA_IROUTER93 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER93_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER93_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER93_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER93_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER93_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER93_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER93_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER93_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER93_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER93_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER93_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER93_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER93_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER93_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER93_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER93_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER93_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER93_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER93_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER93_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER93_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER93_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER93_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER93_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER93_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER93_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER93_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER93_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER93_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER93_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER93_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER93_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER93_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER93_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER93_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER94 - GICDA_IROUTER94 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER94_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER94_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER94_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER94_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER94_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER94_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER94_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER94_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER94_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER94_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER94_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER94_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER94_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER94_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER94_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER94_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER94_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER94_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER94_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER94_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER94_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER94_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER94_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER94_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER94_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER94_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER94_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER94_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER94_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER94_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER94_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER94_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER94_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER94_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER94_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER95 - GICDA_IROUTER95 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER95_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER95_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER95_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER95_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER95_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER95_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER95_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER95_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER95_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER95_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER95_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER95_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER95_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER95_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER95_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER95_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER95_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER95_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER95_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER95_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER95_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER95_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER95_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER95_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER95_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER95_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER95_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER95_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER95_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER95_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER95_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER95_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER95_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER95_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER95_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER96 - GICDA_IROUTER96 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER96_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER96_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER96_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER96_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER96_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER96_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER96_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER96_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER96_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER96_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER96_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER96_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER96_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER96_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER96_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER96_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER96_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER96_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER96_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER96_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER96_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER96_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER96_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER96_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER96_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER96_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER96_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER96_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER96_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER96_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER96_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER96_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER96_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER96_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER96_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER97 - GICDA_IROUTER97 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER97_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER97_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER97_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER97_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER97_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER97_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER97_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER97_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER97_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER97_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER97_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER97_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER97_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER97_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER97_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER97_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER97_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER97_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER97_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER97_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER97_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER97_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER97_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER97_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER97_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER97_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER97_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER97_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER97_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER97_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER97_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER97_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER97_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER97_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER97_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER98 - GICDA_IROUTER98 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER98_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER98_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER98_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER98_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER98_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER98_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER98_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER98_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER98_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER98_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER98_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER98_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER98_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER98_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER98_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER98_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER98_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER98_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER98_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER98_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER98_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER98_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER98_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER98_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER98_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER98_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER98_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER98_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER98_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER98_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER98_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER98_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER98_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER98_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER98_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER99 - GICDA_IROUTER99 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER99_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER99_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER99_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER99_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER99_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER99_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER99_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER99_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER99_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER99_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER99_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER99_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER99_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER99_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER99_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER99_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER99_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER99_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER99_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER99_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER99_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER99_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER99_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER99_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER99_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER99_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER99_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER99_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER99_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER99_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER99_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER99_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER99_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER99_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER99_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER100 - GICDA_IROUTER100 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER100_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER100_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER100_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER100_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER100_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER100_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER100_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER100_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER100_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER100_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER100_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER100_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER100_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER100_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER100_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER100_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER100_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER100_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER100_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER100_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER100_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER100_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER100_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER100_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER100_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER100_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER100_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER100_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER100_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER100_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER100_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER100_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER100_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER100_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER100_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER101 - GICDA_IROUTER101 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER101_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER101_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER101_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER101_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER101_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER101_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER101_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER101_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER101_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER101_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER101_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER101_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER101_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER101_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER101_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER101_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER101_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER101_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER101_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER101_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER101_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER101_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER101_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER101_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER101_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER101_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER101_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER101_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER101_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER101_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER101_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER101_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER101_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER101_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER101_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER102 - GICDA_IROUTER102 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER102_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER102_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER102_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER102_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER102_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER102_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER102_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER102_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER102_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER102_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER102_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER102_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER102_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER102_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER102_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER102_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER102_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER102_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER102_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER102_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER102_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER102_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER102_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER102_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER102_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER102_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER102_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER102_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER102_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER102_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER102_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER102_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER102_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER102_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER102_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER103 - GICDA_IROUTER103 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER103_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER103_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER103_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER103_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER103_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER103_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER103_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER103_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER103_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER103_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER103_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER103_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER103_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER103_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER103_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER103_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER103_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER103_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER103_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER103_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER103_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER103_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER103_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER103_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER103_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER103_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER103_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER103_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER103_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER103_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER103_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER103_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER103_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER103_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER103_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER104 - GICDA_IROUTER104 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER104_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER104_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER104_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER104_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER104_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER104_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER104_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER104_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER104_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER104_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER104_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER104_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER104_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER104_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER104_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER104_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER104_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER104_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER104_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER104_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER104_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER104_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER104_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER104_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER104_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER104_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER104_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER104_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER104_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER104_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER104_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER104_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER104_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER104_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER104_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER105 - GICDA_IROUTER105 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER105_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER105_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER105_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER105_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER105_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER105_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER105_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER105_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER105_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER105_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER105_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER105_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER105_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER105_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER105_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER105_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER105_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER105_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER105_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER105_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER105_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER105_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER105_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER105_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER105_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER105_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER105_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER105_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER105_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER105_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER105_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER105_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER105_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER105_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER105_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER106 - GICDA_IROUTER106 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER106_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER106_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER106_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER106_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER106_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER106_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER106_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER106_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER106_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER106_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER106_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER106_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER106_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER106_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER106_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER106_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER106_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER106_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER106_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER106_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER106_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER106_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER106_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER106_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER106_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER106_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER106_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER106_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER106_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER106_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER106_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER106_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER106_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER106_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER106_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER107 - GICDA_IROUTER107 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER107_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER107_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER107_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER107_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER107_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER107_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER107_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER107_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER107_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER107_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER107_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER107_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER107_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER107_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER107_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER107_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER107_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER107_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER107_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER107_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER107_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER107_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER107_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER107_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER107_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER107_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER107_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER107_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER107_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER107_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER107_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER107_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER107_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER107_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER107_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER108 - GICDA_IROUTER108 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER108_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER108_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER108_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER108_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER108_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER108_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER108_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER108_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER108_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER108_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER108_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER108_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER108_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER108_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER108_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER108_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER108_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER108_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER108_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER108_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER108_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER108_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER108_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER108_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER108_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER108_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER108_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER108_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER108_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER108_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER108_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER108_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER108_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER108_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER108_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER109 - GICDA_IROUTER109 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER109_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER109_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER109_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER109_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER109_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER109_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER109_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER109_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER109_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER109_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER109_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER109_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER109_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER109_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER109_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER109_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER109_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER109_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER109_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER109_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER109_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER109_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER109_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER109_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER109_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER109_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER109_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER109_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER109_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER109_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER109_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER109_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER109_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER109_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER109_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER110 - GICDA_IROUTER110 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER110_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER110_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER110_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER110_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER110_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER110_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER110_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER110_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER110_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER110_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER110_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER110_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER110_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER110_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER110_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER110_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER110_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER110_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER110_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER110_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER110_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER110_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER110_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER110_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER110_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER110_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER110_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER110_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER110_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER110_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER110_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER110_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER110_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER110_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER110_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER111 - GICDA_IROUTER111 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER111_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER111_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER111_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER111_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER111_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER111_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER111_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER111_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER111_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER111_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER111_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER111_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER111_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER111_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER111_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER111_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER111_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER111_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER111_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER111_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER111_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER111_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER111_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER111_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER111_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER111_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER111_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER111_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER111_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER111_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER111_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER111_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER111_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER111_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER111_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER112 - GICDA_IROUTER112 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER112_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER112_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER112_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER112_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER112_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER112_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER112_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER112_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER112_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER112_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER112_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER112_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER112_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER112_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER112_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER112_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER112_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER112_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER112_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER112_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER112_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER112_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER112_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER112_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER112_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER112_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER112_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER112_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER112_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER112_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER112_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER112_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER112_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER112_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER112_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER113 - GICDA_IROUTER113 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER113_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER113_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER113_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER113_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER113_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER113_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER113_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER113_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER113_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER113_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER113_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER113_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER113_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER113_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER113_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER113_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER113_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER113_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER113_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER113_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER113_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER113_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER113_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER113_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER113_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER113_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER113_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER113_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER113_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER113_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER113_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER113_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER113_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER113_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER113_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER114 - GICDA_IROUTER114 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER114_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER114_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER114_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER114_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER114_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER114_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER114_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER114_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER114_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER114_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER114_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER114_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER114_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER114_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER114_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER114_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER114_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER114_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER114_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER114_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER114_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER114_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER114_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER114_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER114_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER114_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER114_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER114_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER114_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER114_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER114_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER114_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER114_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER114_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER114_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER115 - GICDA_IROUTER115 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER115_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER115_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER115_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER115_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER115_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER115_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER115_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER115_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER115_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER115_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER115_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER115_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER115_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER115_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER115_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER115_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER115_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER115_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER115_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER115_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER115_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER115_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER115_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER115_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER115_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER115_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER115_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER115_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER115_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER115_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER115_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER115_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER115_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER115_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER115_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER116 - GICDA_IROUTER116 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER116_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER116_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER116_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER116_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER116_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER116_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER116_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER116_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER116_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER116_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER116_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER116_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER116_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER116_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER116_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER116_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER116_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER116_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER116_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER116_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER116_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER116_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER116_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER116_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER116_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER116_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER116_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER116_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER116_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER116_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER116_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER116_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER116_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER116_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER116_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER117 - GICDA_IROUTER117 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER117_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER117_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER117_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER117_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER117_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER117_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER117_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER117_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER117_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER117_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER117_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER117_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER117_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER117_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER117_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER117_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER117_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER117_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER117_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER117_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER117_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER117_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER117_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER117_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER117_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER117_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER117_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER117_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER117_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER117_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER117_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER117_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER117_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER117_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER117_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER118 - GICDA_IROUTER118 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER118_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER118_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER118_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER118_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER118_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER118_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER118_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER118_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER118_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER118_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER118_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER118_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER118_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER118_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER118_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER118_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER118_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER118_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER118_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER118_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER118_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER118_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER118_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER118_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER118_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER118_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER118_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER118_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER118_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER118_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER118_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER118_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER118_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER118_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER118_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER119 - GICDA_IROUTER119 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER119_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER119_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER119_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER119_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER119_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER119_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER119_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER119_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER119_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER119_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER119_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER119_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER119_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER119_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER119_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER119_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER119_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER119_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER119_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER119_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER119_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER119_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER119_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER119_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER119_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER119_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER119_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER119_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER119_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER119_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER119_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER119_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER119_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER119_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER119_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER120 - GICDA_IROUTER120 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER120_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER120_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER120_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER120_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER120_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER120_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER120_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER120_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER120_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER120_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER120_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER120_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER120_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER120_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER120_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER120_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER120_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER120_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER120_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER120_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER120_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER120_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER120_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER120_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER120_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER120_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER120_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER120_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER120_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER120_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER120_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER120_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER120_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER120_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER120_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER121 - GICDA_IROUTER121 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER121_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER121_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER121_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER121_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER121_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER121_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER121_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER121_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER121_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER121_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER121_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER121_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER121_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER121_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER121_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER121_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER121_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER121_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER121_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER121_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER121_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER121_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER121_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER121_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER121_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER121_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER121_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER121_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER121_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER121_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER121_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER121_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER121_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER121_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER121_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER122 - GICDA_IROUTER122 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER122_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER122_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER122_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER122_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER122_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER122_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER122_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER122_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER122_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER122_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER122_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER122_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER122_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER122_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER122_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER122_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER122_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER122_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER122_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER122_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER122_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER122_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER122_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER122_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER122_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER122_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER122_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER122_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER122_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER122_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER122_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER122_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER122_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER122_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER122_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER123 - GICDA_IROUTER123 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER123_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER123_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER123_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER123_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER123_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER123_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER123_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER123_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER123_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER123_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER123_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER123_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER123_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER123_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER123_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER123_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER123_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER123_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER123_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER123_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER123_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER123_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER123_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER123_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER123_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER123_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER123_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER123_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER123_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER123_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER123_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER123_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER123_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER123_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER123_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER124 - GICDA_IROUTER124 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER124_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER124_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER124_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER124_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER124_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER124_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER124_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER124_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER124_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER124_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER124_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER124_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER124_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER124_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER124_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER124_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER124_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER124_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER124_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER124_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER124_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER124_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER124_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER124_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER124_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER124_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER124_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER124_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER124_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER124_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER124_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER124_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER124_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER124_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER124_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER125 - GICDA_IROUTER125 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER125_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER125_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER125_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER125_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER125_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER125_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER125_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER125_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER125_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER125_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER125_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER125_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER125_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER125_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER125_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER125_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER125_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER125_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER125_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER125_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER125_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER125_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER125_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER125_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER125_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER125_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER125_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER125_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER125_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER125_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER125_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER125_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER125_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER125_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER125_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER126 - GICDA_IROUTER126 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER126_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER126_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER126_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER126_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER126_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER126_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER126_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER126_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER126_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER126_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER126_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER126_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER126_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER126_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER126_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER126_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER126_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER126_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER126_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER126_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER126_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER126_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER126_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER126_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER126_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER126_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER126_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER126_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER126_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER126_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER126_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER126_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER126_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER126_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER126_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER127 - GICDA_IROUTER127 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER127_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER127_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER127_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER127_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER127_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER127_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER127_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER127_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER127_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER127_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER127_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER127_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER127_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER127_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER127_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER127_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER127_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER127_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER127_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER127_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER127_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER127_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER127_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER127_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER127_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER127_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER127_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER127_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER127_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER127_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER127_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER127_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER127_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER127_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER127_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER128 - GICDA_IROUTER128 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER128_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER128_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER128_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER128_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER128_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER128_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER128_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER128_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER128_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER128_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER128_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER128_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER128_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER128_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER128_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER128_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER128_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER128_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER128_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER128_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER128_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER128_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER128_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER128_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER128_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER128_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER128_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER128_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER128_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER128_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER128_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER128_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER128_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER128_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER128_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER129 - GICDA_IROUTER129 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER129_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER129_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER129_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER129_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER129_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER129_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER129_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER129_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER129_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER129_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER129_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER129_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER129_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER129_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER129_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER129_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER129_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER129_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER129_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER129_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER129_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER129_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER129_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER129_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER129_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER129_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER129_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER129_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER129_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER129_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER129_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER129_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER129_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER129_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER129_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER130 - GICDA_IROUTER130 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER130_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER130_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER130_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER130_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER130_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER130_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER130_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER130_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER130_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER130_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER130_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER130_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER130_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER130_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER130_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER130_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER130_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER130_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER130_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER130_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER130_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER130_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER130_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER130_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER130_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER130_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER130_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER130_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER130_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER130_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER130_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER130_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER130_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER130_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER130_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER131 - GICDA_IROUTER131 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER131_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER131_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER131_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER131_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER131_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER131_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER131_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER131_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER131_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER131_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER131_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER131_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER131_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER131_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER131_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER131_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER131_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER131_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER131_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER131_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER131_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER131_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER131_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER131_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER131_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER131_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER131_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER131_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER131_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER131_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER131_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER131_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER131_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER131_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER131_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER132 - GICDA_IROUTER132 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER132_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER132_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER132_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER132_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER132_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER132_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER132_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER132_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER132_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER132_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER132_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER132_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER132_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER132_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER132_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER132_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER132_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER132_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER132_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER132_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER132_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER132_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER132_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER132_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER132_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER132_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER132_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER132_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER132_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER132_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER132_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER132_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER132_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER132_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER132_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER133 - GICDA_IROUTER133 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER133_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER133_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER133_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER133_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER133_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER133_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER133_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER133_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER133_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER133_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER133_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER133_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER133_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER133_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER133_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER133_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER133_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER133_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER133_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER133_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER133_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER133_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER133_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER133_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER133_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER133_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER133_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER133_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER133_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER133_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER133_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER133_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER133_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER133_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER133_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER134 - GICDA_IROUTER134 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER134_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER134_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER134_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER134_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER134_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER134_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER134_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER134_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER134_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER134_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER134_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER134_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER134_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER134_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER134_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER134_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER134_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER134_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER134_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER134_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER134_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER134_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER134_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER134_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER134_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER134_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER134_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER134_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER134_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER134_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER134_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER134_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER134_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER134_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER134_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER135 - GICDA_IROUTER135 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER135_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER135_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER135_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER135_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER135_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER135_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER135_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER135_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER135_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER135_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER135_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER135_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER135_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER135_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER135_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER135_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER135_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER135_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER135_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER135_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER135_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER135_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER135_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER135_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER135_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER135_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER135_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER135_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER135_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER135_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER135_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER135_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER135_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER135_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER135_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER136 - GICDA_IROUTER136 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER136_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER136_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER136_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER136_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER136_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER136_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER136_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER136_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER136_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER136_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER136_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER136_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER136_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER136_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER136_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER136_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER136_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER136_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER136_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER136_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER136_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER136_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER136_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER136_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER136_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER136_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER136_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER136_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER136_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER136_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER136_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER136_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER136_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER136_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER136_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER137 - GICDA_IROUTER137 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER137_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER137_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER137_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER137_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER137_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER137_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER137_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER137_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER137_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER137_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER137_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER137_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER137_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER137_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER137_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER137_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER137_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER137_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER137_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER137_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER137_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER137_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER137_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER137_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER137_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER137_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER137_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER137_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER137_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER137_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER137_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER137_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER137_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER137_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER137_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER138 - GICDA_IROUTER138 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER138_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER138_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER138_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER138_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER138_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER138_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER138_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER138_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER138_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER138_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER138_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER138_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER138_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER138_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER138_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER138_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER138_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER138_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER138_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER138_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER138_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER138_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER138_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER138_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER138_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER138_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER138_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER138_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER138_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER138_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER138_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER138_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER138_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER138_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER138_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER139 - GICDA_IROUTER139 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER139_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER139_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER139_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER139_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER139_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER139_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER139_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER139_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER139_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER139_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER139_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER139_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER139_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER139_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER139_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER139_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER139_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER139_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER139_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER139_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER139_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER139_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER139_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER139_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER139_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER139_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER139_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER139_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER139_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER139_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER139_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER139_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER139_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER139_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER139_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER140 - GICDA_IROUTER140 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER140_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER140_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER140_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER140_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER140_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER140_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER140_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER140_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER140_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER140_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER140_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER140_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER140_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER140_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER140_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER140_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER140_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER140_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER140_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER140_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER140_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER140_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER140_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER140_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER140_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER140_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER140_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER140_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER140_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER140_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER140_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER140_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER140_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER140_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER140_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER141 - GICDA_IROUTER141 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER141_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER141_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER141_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER141_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER141_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER141_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER141_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER141_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER141_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER141_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER141_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER141_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER141_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER141_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER141_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER141_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER141_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER141_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER141_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER141_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER141_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER141_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER141_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER141_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER141_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER141_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER141_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER141_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER141_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER141_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER141_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER141_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER141_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER141_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER141_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER142 - GICDA_IROUTER142 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER142_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER142_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER142_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER142_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER142_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER142_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER142_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER142_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER142_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER142_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER142_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER142_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER142_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER142_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER142_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER142_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER142_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER142_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER142_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER142_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER142_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER142_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER142_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER142_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER142_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER142_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER142_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER142_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER142_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER142_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER142_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER142_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER142_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER142_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER142_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER143 - GICDA_IROUTER143 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER143_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER143_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER143_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER143_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER143_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER143_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER143_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER143_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER143_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER143_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER143_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER143_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER143_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER143_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER143_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER143_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER143_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER143_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER143_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER143_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER143_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER143_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER143_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER143_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER143_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER143_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER143_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER143_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER143_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER143_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER143_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER143_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER143_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER143_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER143_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER144 - GICDA_IROUTER144 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER144_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER144_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER144_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER144_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER144_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER144_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER144_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER144_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER144_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER144_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER144_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER144_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER144_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER144_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER144_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER144_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER144_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER144_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER144_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER144_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER144_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER144_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER144_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER144_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER144_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER144_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER144_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER144_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER144_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER144_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER144_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER144_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER144_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER144_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER144_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER145 - GICDA_IROUTER145 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER145_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER145_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER145_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER145_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER145_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER145_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER145_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER145_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER145_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER145_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER145_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER145_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER145_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER145_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER145_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER145_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER145_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER145_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER145_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER145_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER145_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER145_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER145_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER145_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER145_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER145_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER145_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER145_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER145_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER145_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER145_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER145_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER145_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER145_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER145_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER146 - GICDA_IROUTER146 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER146_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER146_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER146_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER146_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER146_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER146_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER146_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER146_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER146_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER146_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER146_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER146_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER146_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER146_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER146_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER146_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER146_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER146_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER146_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER146_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER146_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER146_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER146_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER146_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER146_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER146_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER146_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER146_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER146_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER146_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER146_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER146_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER146_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER146_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER146_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER147 - GICDA_IROUTER147 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER147_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER147_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER147_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER147_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER147_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER147_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER147_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER147_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER147_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER147_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER147_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER147_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER147_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER147_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER147_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER147_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER147_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER147_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER147_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER147_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER147_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER147_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER147_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER147_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER147_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER147_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER147_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER147_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER147_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER147_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER147_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER147_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER147_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER147_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER147_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER148 - GICDA_IROUTER148 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER148_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER148_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER148_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER148_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER148_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER148_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER148_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER148_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER148_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER148_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER148_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER148_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER148_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER148_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER148_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER148_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER148_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER148_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER148_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER148_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER148_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER148_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER148_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER148_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER148_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER148_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER148_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER148_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER148_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER148_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER148_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER148_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER148_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER148_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER148_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER149 - GICDA_IROUTER149 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER149_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER149_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER149_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER149_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER149_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER149_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER149_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER149_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER149_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER149_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER149_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER149_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER149_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER149_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER149_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER149_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER149_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER149_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER149_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER149_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER149_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER149_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER149_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER149_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER149_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER149_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER149_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER149_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER149_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER149_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER149_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER149_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER149_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER149_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER149_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER150 - GICDA_IROUTER150 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER150_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER150_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER150_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER150_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER150_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER150_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER150_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER150_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER150_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER150_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER150_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER150_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER150_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER150_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER150_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER150_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER150_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER150_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER150_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER150_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER150_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER150_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER150_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER150_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER150_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER150_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER150_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER150_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER150_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER150_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER150_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER150_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER150_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER150_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER150_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER151 - GICDA_IROUTER151 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER151_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER151_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER151_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER151_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER151_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER151_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER151_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER151_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER151_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER151_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER151_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER151_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER151_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER151_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER151_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER151_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER151_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER151_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER151_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER151_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER151_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER151_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER151_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER151_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER151_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER151_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER151_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER151_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER151_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER151_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER151_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER151_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER151_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER151_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER151_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER152 - GICDA_IROUTER152 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER152_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER152_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER152_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER152_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER152_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER152_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER152_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER152_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER152_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER152_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER152_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER152_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER152_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER152_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER152_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER152_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER152_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER152_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER152_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER152_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER152_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER152_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER152_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER152_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER152_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER152_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER152_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER152_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER152_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER152_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER152_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER152_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER152_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER152_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER152_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER153 - GICDA_IROUTER153 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER153_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER153_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER153_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER153_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER153_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER153_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER153_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER153_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER153_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER153_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER153_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER153_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER153_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER153_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER153_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER153_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER153_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER153_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER153_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER153_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER153_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER153_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER153_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER153_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER153_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER153_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER153_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER153_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER153_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER153_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER153_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER153_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER153_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER153_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER153_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER154 - GICDA_IROUTER154 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER154_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER154_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER154_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER154_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER154_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER154_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER154_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER154_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER154_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER154_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER154_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER154_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER154_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER154_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER154_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER154_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER154_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER154_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER154_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER154_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER154_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER154_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER154_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER154_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER154_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER154_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER154_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER154_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER154_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER154_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER154_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER154_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER154_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER154_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER154_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER155 - GICDA_IROUTER155 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER155_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER155_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER155_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER155_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER155_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER155_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER155_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER155_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER155_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER155_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER155_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER155_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER155_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER155_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER155_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER155_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER155_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER155_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER155_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER155_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER155_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER155_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER155_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER155_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER155_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER155_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER155_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER155_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER155_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER155_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER155_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER155_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER155_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER155_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER155_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER156 - GICDA_IROUTER156 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER156_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER156_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER156_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER156_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER156_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER156_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER156_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER156_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER156_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER156_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER156_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER156_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER156_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER156_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER156_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER156_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER156_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER156_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER156_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER156_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER156_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER156_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER156_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER156_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER156_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER156_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER156_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER156_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER156_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER156_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER156_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER156_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER156_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER156_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER156_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER157 - GICDA_IROUTER157 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER157_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER157_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER157_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER157_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER157_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER157_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER157_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER157_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER157_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER157_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER157_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER157_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER157_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER157_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER157_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER157_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER157_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER157_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER157_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER157_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER157_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER157_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER157_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER157_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER157_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER157_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER157_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER157_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER157_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER157_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER157_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER157_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER157_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER157_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER157_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER158 - GICDA_IROUTER158 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER158_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER158_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER158_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER158_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER158_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER158_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER158_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER158_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER158_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER158_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER158_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER158_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER158_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER158_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER158_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER158_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER158_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER158_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER158_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER158_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER158_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER158_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER158_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER158_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER158_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER158_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER158_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER158_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER158_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER158_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER158_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER158_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER158_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER158_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER158_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER159 - GICDA_IROUTER159 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER159_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER159_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER159_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER159_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER159_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER159_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER159_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER159_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER159_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER159_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER159_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER159_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER159_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER159_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER159_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER159_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER159_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER159_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER159_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER159_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER159_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER159_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER159_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER159_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER159_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER159_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER159_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER159_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER159_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER159_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER159_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER159_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER159_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER159_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER159_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER160 - GICDA_IROUTER160 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER160_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER160_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER160_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER160_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER160_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER160_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER160_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER160_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER160_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER160_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER160_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER160_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER160_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER160_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER160_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER160_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER160_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER160_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER160_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER160_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER160_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER160_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER160_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER160_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER160_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER160_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER160_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER160_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER160_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER160_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER160_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER160_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER160_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER160_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER160_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER161 - GICDA_IROUTER161 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER161_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER161_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER161_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER161_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER161_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER161_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER161_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER161_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER161_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER161_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER161_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER161_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER161_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER161_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER161_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER161_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER161_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER161_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER161_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER161_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER161_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER161_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER161_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER161_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER161_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER161_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER161_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER161_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER161_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER161_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER161_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER161_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER161_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER161_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER161_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER162 - GICDA_IROUTER162 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER162_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER162_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER162_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER162_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER162_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER162_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER162_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER162_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER162_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER162_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER162_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER162_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER162_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER162_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER162_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER162_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER162_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER162_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER162_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER162_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER162_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER162_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER162_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER162_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER162_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER162_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER162_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER162_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER162_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER162_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER162_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER162_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER162_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER162_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER162_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER163 - GICDA_IROUTER163 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER163_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER163_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER163_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER163_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER163_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER163_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER163_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER163_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER163_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER163_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER163_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER163_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER163_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER163_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER163_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER163_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER163_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER163_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER163_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER163_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER163_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER163_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER163_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER163_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER163_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER163_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER163_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER163_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER163_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER163_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER163_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER163_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER163_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER163_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER163_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER164 - GICDA_IROUTER164 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER164_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER164_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER164_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER164_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER164_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER164_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER164_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER164_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER164_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER164_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER164_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER164_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER164_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER164_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER164_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER164_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER164_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER164_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER164_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER164_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER164_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER164_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER164_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER164_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER164_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER164_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER164_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER164_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER164_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER164_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER164_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER164_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER164_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER164_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER164_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER165 - GICDA_IROUTER165 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER165_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER165_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER165_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER165_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER165_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER165_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER165_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER165_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER165_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER165_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER165_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER165_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER165_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER165_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER165_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER165_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER165_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER165_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER165_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER165_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER165_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER165_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER165_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER165_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER165_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER165_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER165_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER165_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER165_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER165_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER165_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER165_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER165_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER165_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER165_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER166 - GICDA_IROUTER166 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER166_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER166_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER166_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER166_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER166_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER166_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER166_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER166_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER166_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER166_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER166_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER166_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER166_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER166_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER166_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER166_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER166_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER166_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER166_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER166_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER166_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER166_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER166_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER166_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER166_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER166_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER166_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER166_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER166_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER166_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER166_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER166_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER166_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER166_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER166_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER167 - GICDA_IROUTER167 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER167_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER167_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER167_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER167_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER167_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER167_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER167_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER167_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER167_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER167_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER167_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER167_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER167_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER167_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER167_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER167_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER167_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER167_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER167_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER167_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER167_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER167_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER167_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER167_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER167_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER167_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER167_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER167_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER167_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER167_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER167_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER167_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER167_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER167_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER167_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER168 - GICDA_IROUTER168 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER168_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER168_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER168_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER168_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER168_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER168_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER168_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER168_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER168_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER168_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER168_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER168_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER168_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER168_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER168_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER168_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER168_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER168_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER168_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER168_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER168_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER168_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER168_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER168_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER168_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER168_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER168_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER168_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER168_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER168_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER168_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER168_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER168_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER168_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER168_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER169 - GICDA_IROUTER169 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER169_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER169_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER169_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER169_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER169_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER169_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER169_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER169_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER169_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER169_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER169_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER169_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER169_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER169_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER169_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER169_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER169_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER169_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER169_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER169_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER169_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER169_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER169_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER169_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER169_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER169_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER169_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER169_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER169_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER169_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER169_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER169_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER169_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER169_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER169_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER170 - GICDA_IROUTER170 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER170_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER170_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER170_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER170_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER170_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER170_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER170_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER170_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER170_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER170_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER170_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER170_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER170_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER170_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER170_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER170_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER170_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER170_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER170_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER170_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER170_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER170_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER170_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER170_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER170_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER170_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER170_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER170_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER170_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER170_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER170_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER170_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER170_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER170_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER170_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER171 - GICDA_IROUTER171 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER171_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER171_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER171_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER171_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER171_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER171_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER171_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER171_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER171_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER171_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER171_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER171_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER171_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER171_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER171_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER171_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER171_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER171_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER171_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER171_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER171_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER171_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER171_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER171_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER171_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER171_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER171_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER171_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER171_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER171_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER171_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER171_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER171_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER171_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER171_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER172 - GICDA_IROUTER172 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER172_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER172_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER172_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER172_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER172_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER172_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER172_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER172_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER172_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER172_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER172_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER172_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER172_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER172_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER172_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER172_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER172_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER172_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER172_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER172_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER172_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER172_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER172_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER172_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER172_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER172_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER172_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER172_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER172_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER172_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER172_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER172_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER172_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER172_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER172_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER173 - GICDA_IROUTER173 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER173_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER173_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER173_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER173_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER173_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER173_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER173_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER173_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER173_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER173_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER173_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER173_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER173_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER173_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER173_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER173_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER173_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER173_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER173_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER173_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER173_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER173_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER173_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER173_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER173_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER173_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER173_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER173_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER173_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER173_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER173_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER173_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER173_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER173_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER173_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER174 - GICDA_IROUTER174 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER174_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER174_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER174_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER174_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER174_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER174_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER174_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER174_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER174_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER174_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER174_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER174_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER174_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER174_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER174_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER174_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER174_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER174_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER174_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER174_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER174_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER174_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER174_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER174_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER174_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER174_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER174_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER174_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER174_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER174_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER174_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER174_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER174_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER174_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER174_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER175 - GICDA_IROUTER175 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER175_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER175_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER175_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER175_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER175_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER175_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER175_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER175_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER175_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER175_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER175_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER175_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER175_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER175_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER175_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER175_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER175_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER175_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER175_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER175_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER175_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER175_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER175_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER175_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER175_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER175_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER175_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER175_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER175_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER175_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER175_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER175_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER175_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER175_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER175_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER176 - GICDA_IROUTER176 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER176_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER176_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER176_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER176_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER176_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER176_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER176_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER176_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER176_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER176_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER176_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER176_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER176_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER176_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER176_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER176_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER176_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER176_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER176_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER176_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER176_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER176_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER176_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER176_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER176_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER176_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER176_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER176_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER176_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER176_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER176_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER176_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER176_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER176_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER176_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER177 - GICDA_IROUTER177 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER177_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER177_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER177_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER177_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER177_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER177_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER177_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER177_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER177_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER177_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER177_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER177_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER177_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER177_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER177_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER177_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER177_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER177_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER177_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER177_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER177_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER177_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER177_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER177_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER177_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER177_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER177_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER177_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER177_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER177_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER177_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER177_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER177_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER177_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER177_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER178 - GICDA_IROUTER178 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER178_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER178_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER178_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER178_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER178_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER178_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER178_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER178_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER178_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER178_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER178_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER178_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER178_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER178_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER178_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER178_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER178_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER178_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER178_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER178_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER178_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER178_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER178_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER178_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER178_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER178_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER178_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER178_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER178_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER178_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER178_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER178_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER178_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER178_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER178_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER179 - GICDA_IROUTER179 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER179_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER179_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER179_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER179_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER179_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER179_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER179_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER179_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER179_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER179_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER179_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER179_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER179_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER179_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER179_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER179_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER179_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER179_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER179_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER179_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER179_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER179_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER179_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER179_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER179_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER179_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER179_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER179_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER179_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER179_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER179_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER179_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER179_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER179_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER179_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER180 - GICDA_IROUTER180 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER180_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER180_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER180_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER180_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER180_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER180_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER180_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER180_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER180_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER180_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER180_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER180_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER180_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER180_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER180_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER180_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER180_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER180_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER180_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER180_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER180_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER180_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER180_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER180_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER180_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER180_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER180_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER180_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER180_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER180_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER180_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER180_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER180_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER180_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER180_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER181 - GICDA_IROUTER181 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER181_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER181_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER181_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER181_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER181_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER181_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER181_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER181_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER181_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER181_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER181_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER181_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER181_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER181_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER181_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER181_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER181_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER181_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER181_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER181_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER181_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER181_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER181_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER181_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER181_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER181_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER181_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER181_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER181_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER181_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER181_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER181_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER181_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER181_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER181_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER182 - GICDA_IROUTER182 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER182_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER182_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER182_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER182_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER182_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER182_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER182_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER182_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER182_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER182_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER182_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER182_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER182_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER182_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER182_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER182_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER182_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER182_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER182_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER182_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER182_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER182_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER182_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER182_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER182_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER182_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER182_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER182_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER182_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER182_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER182_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER182_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER182_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER182_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER182_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER183 - GICDA_IROUTER183 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER183_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER183_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER183_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER183_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER183_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER183_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER183_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER183_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER183_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER183_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER183_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER183_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER183_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER183_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER183_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER183_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER183_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER183_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER183_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER183_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER183_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER183_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER183_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER183_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER183_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER183_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER183_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER183_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER183_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER183_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER183_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER183_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER183_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER183_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER183_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER184 - GICDA_IROUTER184 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER184_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER184_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER184_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER184_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER184_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER184_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER184_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER184_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER184_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER184_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER184_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER184_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER184_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER184_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER184_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER184_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER184_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER184_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER184_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER184_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER184_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER184_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER184_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER184_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER184_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER184_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER184_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER184_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER184_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER184_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER184_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER184_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER184_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER184_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER184_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER185 - GICDA_IROUTER185 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER185_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER185_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER185_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER185_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER185_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER185_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER185_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER185_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER185_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER185_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER185_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER185_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER185_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER185_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER185_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER185_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER185_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER185_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER185_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER185_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER185_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER185_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER185_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER185_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER185_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER185_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER185_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER185_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER185_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER185_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER185_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER185_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER185_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER185_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER185_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER186 - GICDA_IROUTER186 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER186_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER186_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER186_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER186_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER186_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER186_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER186_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER186_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER186_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER186_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER186_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER186_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER186_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER186_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER186_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER186_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER186_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER186_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER186_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER186_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER186_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER186_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER186_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER186_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER186_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER186_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER186_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER186_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER186_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER186_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER186_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER186_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER186_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER186_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER186_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER187 - GICDA_IROUTER187 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER187_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER187_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER187_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER187_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER187_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER187_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER187_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER187_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER187_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER187_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER187_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER187_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER187_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER187_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER187_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER187_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER187_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER187_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER187_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER187_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER187_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER187_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER187_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER187_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER187_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER187_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER187_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER187_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER187_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER187_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER187_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER187_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER187_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER187_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER187_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER188 - GICDA_IROUTER188 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER188_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER188_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER188_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER188_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER188_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER188_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER188_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER188_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER188_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER188_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER188_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER188_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER188_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER188_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER188_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER188_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER188_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER188_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER188_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER188_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER188_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER188_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER188_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER188_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER188_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER188_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER188_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER188_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER188_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER188_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER188_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER188_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER188_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER188_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER188_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER189 - GICDA_IROUTER189 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER189_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER189_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER189_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER189_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER189_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER189_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER189_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER189_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER189_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER189_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER189_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER189_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER189_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER189_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER189_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER189_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER189_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER189_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER189_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER189_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER189_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER189_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER189_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER189_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER189_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER189_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER189_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER189_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER189_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER189_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER189_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER189_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER189_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER189_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER189_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER190 - GICDA_IROUTER190 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER190_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER190_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER190_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER190_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER190_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER190_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER190_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER190_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER190_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER190_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER190_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER190_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER190_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER190_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER190_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER190_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER190_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER190_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER190_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER190_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER190_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER190_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER190_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER190_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER190_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER190_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER190_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER190_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER190_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER190_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER190_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER190_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER190_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER190_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER190_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER191 - GICDA_IROUTER191 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER191_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER191_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER191_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER191_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER191_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER191_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER191_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER191_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER191_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER191_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER191_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER191_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER191_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER191_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER191_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER191_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER191_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER191_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER191_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER191_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER191_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER191_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER191_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER191_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER191_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER191_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER191_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER191_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER191_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER191_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER191_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER191_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER191_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER191_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER191_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER192 - GICDA_IROUTER192 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER192_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER192_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER192_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER192_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER192_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER192_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER192_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER192_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER192_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER192_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER192_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER192_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER192_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER192_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER192_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER192_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER192_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER192_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER192_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER192_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER192_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER192_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER192_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER192_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER192_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER192_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER192_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER192_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER192_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER192_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER192_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER192_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER192_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER192_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER192_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER193 - GICDA_IROUTER193 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER193_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER193_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER193_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER193_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER193_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER193_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER193_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER193_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER193_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER193_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER193_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER193_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER193_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER193_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER193_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER193_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER193_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER193_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER193_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER193_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER193_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER193_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER193_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER193_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER193_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER193_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER193_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER193_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER193_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER193_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER193_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER193_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER193_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER193_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER193_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER194 - GICDA_IROUTER194 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER194_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER194_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER194_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER194_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER194_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER194_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER194_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER194_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER194_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER194_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER194_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER194_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER194_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER194_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER194_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER194_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER194_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER194_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER194_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER194_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER194_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER194_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER194_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER194_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER194_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER194_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER194_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER194_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER194_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER194_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER194_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER194_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER194_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER194_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER194_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER195 - GICDA_IROUTER195 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER195_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER195_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER195_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER195_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER195_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER195_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER195_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER195_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER195_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER195_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER195_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER195_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER195_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER195_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER195_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER195_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER195_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER195_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER195_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER195_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER195_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER195_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER195_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER195_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER195_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER195_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER195_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER195_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER195_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER195_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER195_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER195_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER195_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER195_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER195_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER196 - GICDA_IROUTER196 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER196_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER196_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER196_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER196_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER196_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER196_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER196_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER196_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER196_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER196_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER196_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER196_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER196_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER196_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER196_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER196_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER196_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER196_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER196_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER196_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER196_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER196_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER196_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER196_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER196_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER196_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER196_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER196_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER196_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER196_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER196_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER196_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER196_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER196_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER196_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER197 - GICDA_IROUTER197 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER197_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER197_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER197_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER197_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER197_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER197_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER197_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER197_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER197_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER197_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER197_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER197_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER197_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER197_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER197_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER197_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER197_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER197_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER197_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER197_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER197_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER197_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER197_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER197_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER197_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER197_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER197_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER197_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER197_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER197_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER197_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER197_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER197_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER197_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER197_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER198 - GICDA_IROUTER198 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER198_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER198_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER198_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER198_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER198_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER198_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER198_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER198_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER198_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER198_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER198_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER198_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER198_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER198_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER198_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER198_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER198_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER198_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER198_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER198_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER198_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER198_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER198_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER198_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER198_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER198_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER198_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER198_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER198_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER198_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER198_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER198_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER198_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER198_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER198_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER199 - GICDA_IROUTER199 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER199_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER199_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER199_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER199_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER199_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER199_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER199_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER199_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER199_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER199_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER199_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER199_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER199_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER199_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER199_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER199_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER199_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER199_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER199_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER199_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER199_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER199_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER199_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER199_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER199_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER199_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER199_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER199_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER199_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER199_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER199_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER199_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER199_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER199_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER199_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER200 - GICDA_IROUTER200 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER200_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER200_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER200_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER200_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER200_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER200_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER200_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER200_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER200_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER200_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER200_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER200_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER200_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER200_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER200_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER200_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER200_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER200_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER200_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER200_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER200_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER200_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER200_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER200_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER200_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER200_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER200_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER200_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER200_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER200_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER200_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER200_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER200_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER200_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER200_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER201 - GICDA_IROUTER201 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER201_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER201_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER201_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER201_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER201_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER201_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER201_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER201_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER201_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER201_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER201_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER201_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER201_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER201_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER201_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER201_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER201_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER201_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER201_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER201_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER201_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER201_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER201_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER201_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER201_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER201_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER201_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER201_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER201_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER201_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER201_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER201_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER201_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER201_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER201_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER202 - GICDA_IROUTER202 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER202_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER202_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER202_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER202_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER202_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER202_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER202_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER202_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER202_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER202_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER202_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER202_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER202_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER202_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER202_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER202_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER202_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER202_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER202_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER202_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER202_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER202_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER202_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER202_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER202_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER202_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER202_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER202_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER202_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER202_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER202_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER202_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER202_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER202_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER202_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER203 - GICDA_IROUTER203 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER203_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER203_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER203_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER203_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER203_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER203_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER203_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER203_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER203_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER203_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER203_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER203_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER203_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER203_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER203_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER203_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER203_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER203_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER203_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER203_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER203_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER203_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER203_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER203_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER203_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER203_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER203_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER203_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER203_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER203_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER203_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER203_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER203_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER203_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER203_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER204 - GICDA_IROUTER204 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER204_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER204_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER204_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER204_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER204_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER204_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER204_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER204_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER204_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER204_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER204_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER204_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER204_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER204_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER204_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER204_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER204_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER204_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER204_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER204_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER204_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER204_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER204_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER204_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER204_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER204_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER204_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER204_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER204_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER204_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER204_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER204_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER204_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER204_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER204_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER205 - GICDA_IROUTER205 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER205_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER205_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER205_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER205_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER205_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER205_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER205_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER205_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER205_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER205_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER205_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER205_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER205_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER205_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER205_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER205_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER205_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER205_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER205_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER205_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER205_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER205_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER205_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER205_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER205_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER205_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER205_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER205_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER205_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER205_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER205_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER205_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER205_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER205_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER205_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER206 - GICDA_IROUTER206 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER206_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER206_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER206_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER206_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER206_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER206_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER206_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER206_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER206_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER206_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER206_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER206_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER206_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER206_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER206_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER206_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER206_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER206_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER206_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER206_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER206_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER206_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER206_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER206_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER206_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER206_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER206_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER206_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER206_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER206_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER206_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER206_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER206_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER206_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER206_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER207 - GICDA_IROUTER207 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER207_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER207_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER207_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER207_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER207_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER207_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER207_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER207_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER207_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER207_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER207_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER207_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER207_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER207_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER207_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER207_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER207_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER207_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER207_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER207_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER207_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER207_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER207_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER207_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER207_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER207_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER207_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER207_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER207_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER207_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER207_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER207_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER207_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER207_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER207_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER208 - GICDA_IROUTER208 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER208_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER208_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER208_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER208_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER208_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER208_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER208_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER208_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER208_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER208_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER208_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER208_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER208_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER208_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER208_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER208_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER208_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER208_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER208_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER208_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER208_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER208_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER208_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER208_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER208_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER208_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER208_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER208_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER208_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER208_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER208_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER208_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER208_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER208_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER208_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER209 - GICDA_IROUTER209 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER209_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER209_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER209_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER209_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER209_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER209_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER209_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER209_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER209_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER209_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER209_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER209_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER209_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER209_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER209_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER209_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER209_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER209_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER209_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER209_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER209_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER209_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER209_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER209_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER209_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER209_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER209_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER209_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER209_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER209_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER209_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER209_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER209_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER209_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER209_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER210 - GICDA_IROUTER210 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER210_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER210_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER210_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER210_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER210_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER210_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER210_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER210_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER210_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER210_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER210_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER210_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER210_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER210_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER210_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER210_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER210_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER210_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER210_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER210_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER210_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER210_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER210_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER210_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER210_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER210_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER210_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER210_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER210_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER210_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER210_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER210_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER210_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER210_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER210_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER211 - GICDA_IROUTER211 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER211_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER211_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER211_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER211_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER211_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER211_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER211_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER211_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER211_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER211_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER211_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER211_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER211_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER211_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER211_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER211_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER211_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER211_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER211_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER211_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER211_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER211_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER211_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER211_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER211_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER211_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER211_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER211_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER211_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER211_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER211_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER211_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER211_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER211_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER211_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER212 - GICDA_IROUTER212 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER212_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER212_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER212_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER212_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER212_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER212_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER212_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER212_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER212_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER212_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER212_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER212_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER212_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER212_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER212_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER212_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER212_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER212_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER212_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER212_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER212_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER212_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER212_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER212_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER212_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER212_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER212_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER212_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER212_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER212_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER212_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER212_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER212_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER212_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER212_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER213 - GICDA_IROUTER213 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER213_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER213_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER213_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER213_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER213_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER213_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER213_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER213_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER213_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER213_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER213_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER213_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER213_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER213_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER213_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER213_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER213_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER213_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER213_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER213_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER213_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER213_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER213_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER213_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER213_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER213_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER213_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER213_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER213_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER213_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER213_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER213_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER213_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER213_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER213_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER214 - GICDA_IROUTER214 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER214_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER214_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER214_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER214_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER214_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER214_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER214_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER214_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER214_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER214_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER214_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER214_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER214_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER214_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER214_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER214_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER214_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER214_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER214_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER214_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER214_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER214_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER214_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER214_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER214_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER214_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER214_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER214_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER214_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER214_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER214_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER214_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER214_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER214_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER214_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER215 - GICDA_IROUTER215 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER215_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER215_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER215_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER215_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER215_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER215_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER215_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER215_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER215_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER215_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER215_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER215_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER215_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER215_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER215_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER215_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER215_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER215_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER215_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER215_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER215_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER215_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER215_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER215_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER215_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER215_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER215_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER215_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER215_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER215_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER215_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER215_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER215_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER215_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER215_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER216 - GICDA_IROUTER216 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER216_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER216_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER216_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER216_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER216_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER216_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER216_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER216_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER216_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER216_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER216_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER216_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER216_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER216_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER216_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER216_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER216_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER216_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER216_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER216_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER216_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER216_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER216_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER216_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER216_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER216_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER216_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER216_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER216_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER216_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER216_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER216_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER216_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER216_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER216_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER217 - GICDA_IROUTER217 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER217_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER217_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER217_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER217_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER217_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER217_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER217_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER217_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER217_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER217_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER217_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER217_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER217_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER217_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER217_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER217_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER217_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER217_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER217_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER217_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER217_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER217_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER217_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER217_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER217_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER217_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER217_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER217_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER217_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER217_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER217_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER217_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER217_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER217_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER217_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER218 - GICDA_IROUTER218 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER218_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER218_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER218_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER218_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER218_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER218_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER218_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER218_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER218_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER218_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER218_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER218_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER218_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER218_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER218_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER218_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER218_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER218_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER218_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER218_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER218_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER218_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER218_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER218_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER218_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER218_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER218_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER218_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER218_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER218_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER218_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER218_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER218_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER218_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER218_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER219 - GICDA_IROUTER219 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER219_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER219_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER219_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER219_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER219_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER219_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER219_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER219_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER219_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER219_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER219_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER219_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER219_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER219_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER219_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER219_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER219_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER219_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER219_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER219_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER219_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER219_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER219_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER219_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER219_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER219_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER219_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER219_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER219_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER219_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER219_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER219_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER219_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER219_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER219_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER220 - GICDA_IROUTER220 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER220_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER220_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER220_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER220_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER220_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER220_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER220_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER220_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER220_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER220_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER220_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER220_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER220_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER220_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER220_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER220_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER220_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER220_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER220_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER220_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER220_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER220_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER220_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER220_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER220_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER220_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER220_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER220_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER220_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER220_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER220_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER220_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER220_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER220_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER220_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER221 - GICDA_IROUTER221 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER221_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER221_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER221_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER221_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER221_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER221_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER221_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER221_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER221_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER221_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER221_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER221_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER221_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER221_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER221_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER221_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER221_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER221_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER221_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER221_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER221_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER221_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER221_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER221_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER221_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER221_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER221_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER221_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER221_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER221_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER221_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER221_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER221_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER221_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER221_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER222 - GICDA_IROUTER222 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER222_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER222_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER222_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER222_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER222_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER222_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER222_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER222_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER222_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER222_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER222_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER222_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER222_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER222_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER222_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER222_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER222_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER222_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER222_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER222_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER222_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER222_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER222_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER222_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER222_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER222_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER222_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER222_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER222_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER222_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER222_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER222_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER222_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER222_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER222_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER223 - GICDA_IROUTER223 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER223_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER223_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER223_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER223_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER223_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER223_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER223_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER223_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER223_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER223_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER223_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER223_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER223_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER223_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER223_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER223_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER223_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER223_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER223_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER223_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER223_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER223_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER223_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER223_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER223_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER223_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER223_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER223_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER223_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER223_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER223_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER223_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER223_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER223_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER223_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER224 - GICDA_IROUTER224 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER224_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER224_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER224_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER224_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER224_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER224_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER224_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER224_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER224_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER224_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER224_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER224_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER224_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER224_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER224_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER224_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER224_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER224_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER224_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER224_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER224_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER224_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER224_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER224_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER224_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER224_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER224_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER224_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER224_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER224_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER224_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER224_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER224_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER224_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER224_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER225 - GICDA_IROUTER225 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER225_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER225_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER225_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER225_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER225_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER225_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER225_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER225_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER225_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER225_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER225_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER225_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER225_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER225_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER225_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER225_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER225_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER225_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER225_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER225_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER225_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER225_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER225_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER225_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER225_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER225_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER225_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER225_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER225_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER225_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER225_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER225_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER225_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER225_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER225_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER226 - GICDA_IROUTER226 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER226_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER226_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER226_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER226_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER226_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER226_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER226_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER226_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER226_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER226_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER226_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER226_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER226_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER226_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER226_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER226_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER226_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER226_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER226_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER226_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER226_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER226_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER226_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER226_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER226_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER226_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER226_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER226_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER226_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER226_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER226_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER226_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER226_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER226_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER226_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER227 - GICDA_IROUTER227 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER227_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER227_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER227_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER227_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER227_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER227_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER227_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER227_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER227_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER227_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER227_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER227_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER227_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER227_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER227_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER227_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER227_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER227_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER227_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER227_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER227_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER227_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER227_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER227_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER227_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER227_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER227_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER227_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER227_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER227_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER227_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER227_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER227_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER227_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER227_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER228 - GICDA_IROUTER228 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER228_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER228_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER228_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER228_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER228_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER228_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER228_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER228_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER228_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER228_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER228_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER228_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER228_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER228_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER228_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER228_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER228_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER228_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER228_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER228_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER228_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER228_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER228_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER228_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER228_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER228_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER228_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER228_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER228_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER228_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER228_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER228_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER228_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER228_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER228_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER229 - GICDA_IROUTER229 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER229_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER229_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER229_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER229_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER229_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER229_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER229_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER229_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER229_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER229_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER229_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER229_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER229_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER229_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER229_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER229_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER229_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER229_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER229_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER229_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER229_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER229_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER229_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER229_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER229_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER229_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER229_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER229_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER229_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER229_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER229_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER229_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER229_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER229_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER229_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER230 - GICDA_IROUTER230 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER230_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER230_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER230_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER230_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER230_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER230_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER230_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER230_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER230_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER230_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER230_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER230_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER230_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER230_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER230_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER230_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER230_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER230_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER230_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER230_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER230_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER230_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER230_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER230_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER230_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER230_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER230_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER230_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER230_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER230_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER230_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER230_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER230_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER230_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER230_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER231 - GICDA_IROUTER231 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER231_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER231_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER231_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER231_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER231_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER231_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER231_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER231_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER231_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER231_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER231_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER231_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER231_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER231_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER231_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER231_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER231_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER231_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER231_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER231_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER231_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER231_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER231_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER231_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER231_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER231_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER231_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER231_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER231_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER231_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER231_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER231_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER231_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER231_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER231_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER232 - GICDA_IROUTER232 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER232_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER232_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER232_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER232_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER232_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER232_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER232_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER232_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER232_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER232_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER232_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER232_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER232_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER232_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER232_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER232_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER232_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER232_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER232_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER232_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER232_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER232_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER232_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER232_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER232_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER232_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER232_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER232_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER232_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER232_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER232_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER232_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER232_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER232_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER232_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER233 - GICDA_IROUTER233 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER233_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER233_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER233_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER233_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER233_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER233_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER233_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER233_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER233_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER233_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER233_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER233_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER233_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER233_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER233_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER233_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER233_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER233_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER233_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER233_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER233_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER233_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER233_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER233_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER233_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER233_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER233_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER233_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER233_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER233_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER233_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER233_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER233_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER233_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER233_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER234 - GICDA_IROUTER234 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER234_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER234_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER234_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER234_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER234_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER234_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER234_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER234_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER234_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER234_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER234_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER234_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER234_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER234_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER234_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER234_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER234_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER234_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER234_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER234_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER234_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER234_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER234_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER234_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER234_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER234_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER234_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER234_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER234_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER234_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER234_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER234_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER234_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER234_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER234_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER235 - GICDA_IROUTER235 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER235_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER235_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER235_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER235_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER235_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER235_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER235_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER235_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER235_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER235_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER235_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER235_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER235_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER235_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER235_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER235_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER235_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER235_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER235_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER235_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER235_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER235_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER235_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER235_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER235_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER235_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER235_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER235_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER235_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER235_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER235_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER235_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER235_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER235_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER235_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER236 - GICDA_IROUTER236 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER236_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER236_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER236_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER236_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER236_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER236_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER236_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER236_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER236_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER236_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER236_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER236_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER236_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER236_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER236_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER236_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER236_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER236_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER236_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER236_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER236_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER236_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER236_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER236_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER236_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER236_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER236_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER236_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER236_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER236_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER236_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER236_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER236_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER236_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER236_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER237 - GICDA_IROUTER237 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER237_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER237_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER237_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER237_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER237_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER237_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER237_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER237_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER237_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER237_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER237_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER237_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER237_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER237_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER237_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER237_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER237_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER237_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER237_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER237_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER237_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER237_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER237_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER237_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER237_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER237_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER237_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER237_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER237_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER237_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER237_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER237_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER237_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER237_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER237_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER238 - GICDA_IROUTER238 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER238_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER238_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER238_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER238_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER238_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER238_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER238_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER238_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER238_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER238_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER238_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER238_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER238_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER238_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER238_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER238_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER238_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER238_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER238_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER238_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER238_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER238_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER238_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER238_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER238_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER238_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER238_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER238_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER238_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER238_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER238_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER238_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER238_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER238_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER238_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER239 - GICDA_IROUTER239 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER239_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER239_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER239_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER239_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER239_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER239_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER239_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER239_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER239_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER239_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER239_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER239_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER239_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER239_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER239_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER239_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER239_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER239_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER239_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER239_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER239_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER239_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER239_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER239_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER239_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER239_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER239_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER239_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER239_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER239_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER239_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER239_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER239_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER239_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER239_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER240 - GICDA_IROUTER240 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER240_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER240_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER240_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER240_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER240_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER240_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER240_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER240_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER240_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER240_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER240_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER240_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER240_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER240_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER240_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER240_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER240_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER240_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER240_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER240_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER240_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER240_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER240_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER240_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER240_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER240_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER240_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER240_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER240_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER240_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER240_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER240_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER240_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER240_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER240_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER241 - GICDA_IROUTER241 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER241_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER241_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER241_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER241_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER241_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER241_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER241_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER241_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER241_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER241_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER241_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER241_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER241_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER241_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER241_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER241_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER241_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER241_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER241_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER241_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER241_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER241_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER241_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER241_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER241_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER241_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER241_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER241_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER241_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER241_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER241_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER241_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER241_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER241_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER241_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER242 - GICDA_IROUTER242 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER242_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER242_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER242_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER242_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER242_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER242_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER242_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER242_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER242_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER242_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER242_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER242_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER242_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER242_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER242_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER242_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER242_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER242_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER242_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER242_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER242_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER242_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER242_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER242_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER242_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER242_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER242_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER242_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER242_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER242_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER242_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER242_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER242_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER242_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER242_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER243 - GICDA_IROUTER243 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER243_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER243_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER243_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER243_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER243_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER243_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER243_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER243_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER243_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER243_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER243_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER243_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER243_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER243_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER243_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER243_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER243_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER243_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER243_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER243_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER243_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER243_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER243_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER243_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER243_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER243_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER243_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER243_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER243_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER243_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER243_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER243_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER243_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER243_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER243_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER244 - GICDA_IROUTER244 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER244_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER244_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER244_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER244_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER244_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER244_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER244_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER244_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER244_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER244_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER244_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER244_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER244_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER244_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER244_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER244_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER244_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER244_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER244_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER244_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER244_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER244_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER244_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER244_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER244_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER244_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER244_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER244_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER244_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER244_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER244_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER244_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER244_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER244_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER244_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER245 - GICDA_IROUTER245 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER245_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER245_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER245_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER245_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER245_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER245_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER245_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER245_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER245_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER245_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER245_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER245_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER245_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER245_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER245_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER245_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER245_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER245_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER245_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER245_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER245_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER245_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER245_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER245_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER245_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER245_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER245_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER245_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER245_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER245_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER245_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER245_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER245_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER245_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER245_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER246 - GICDA_IROUTER246 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER246_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER246_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER246_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER246_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER246_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER246_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER246_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER246_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER246_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER246_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER246_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER246_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER246_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER246_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER246_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER246_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER246_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER246_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER246_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER246_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER246_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER246_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER246_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER246_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER246_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER246_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER246_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER246_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER246_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER246_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER246_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER246_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER246_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER246_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER246_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER247 - GICDA_IROUTER247 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER247_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER247_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER247_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER247_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER247_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER247_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER247_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER247_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER247_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER247_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER247_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER247_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER247_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER247_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER247_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER247_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER247_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER247_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER247_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER247_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER247_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER247_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER247_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER247_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER247_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER247_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER247_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER247_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER247_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER247_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER247_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER247_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER247_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER247_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER247_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER248 - GICDA_IROUTER248 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER248_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER248_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER248_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER248_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER248_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER248_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER248_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER248_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER248_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER248_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER248_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER248_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER248_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER248_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER248_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER248_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER248_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER248_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER248_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER248_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER248_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER248_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER248_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER248_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER248_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER248_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER248_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER248_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER248_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER248_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER248_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER248_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER248_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER248_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER248_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER249 - GICDA_IROUTER249 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER249_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER249_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER249_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER249_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER249_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER249_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER249_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER249_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER249_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER249_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER249_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER249_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER249_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER249_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER249_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER249_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER249_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER249_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER249_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER249_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER249_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER249_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER249_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER249_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER249_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER249_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER249_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER249_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER249_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER249_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER249_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER249_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER249_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER249_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER249_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER250 - GICDA_IROUTER250 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER250_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER250_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER250_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER250_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER250_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER250_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER250_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER250_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER250_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER250_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER250_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER250_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER250_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER250_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER250_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER250_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER250_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER250_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER250_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER250_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER250_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER250_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER250_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER250_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER250_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER250_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER250_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER250_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER250_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER250_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER250_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER250_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER250_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER250_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER250_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER251 - GICDA_IROUTER251 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER251_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER251_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER251_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER251_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER251_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER251_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER251_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER251_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER251_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER251_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER251_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER251_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER251_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER251_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER251_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER251_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER251_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER251_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER251_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER251_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER251_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER251_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER251_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER251_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER251_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER251_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER251_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER251_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER251_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER251_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER251_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER251_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER251_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER251_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER251_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER252 - GICDA_IROUTER252 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER252_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER252_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER252_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER252_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER252_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER252_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER252_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER252_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER252_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER252_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER252_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER252_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER252_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER252_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER252_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER252_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER252_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER252_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER252_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER252_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER252_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER252_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER252_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER252_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER252_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER252_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER252_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER252_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER252_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER252_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER252_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER252_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER252_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER252_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER252_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER253 - GICDA_IROUTER253 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER253_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER253_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER253_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER253_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER253_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER253_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER253_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER253_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER253_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER253_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER253_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER253_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER253_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER253_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER253_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER253_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER253_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER253_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER253_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER253_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER253_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER253_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER253_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER253_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER253_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER253_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER253_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER253_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER253_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER253_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER253_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER253_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER253_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER253_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER253_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER254 - GICDA_IROUTER254 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER254_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER254_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER254_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER254_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER254_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER254_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER254_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER254_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER254_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER254_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER254_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER254_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER254_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER254_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER254_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER254_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER254_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER254_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER254_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER254_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER254_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER254_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER254_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER254_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER254_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER254_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER254_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER254_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER254_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER254_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER254_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER254_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER254_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER254_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER254_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER255 - GICDA_IROUTER255 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER255_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER255_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER255_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER255_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER255_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER255_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER255_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER255_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER255_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER255_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER255_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER255_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER255_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER255_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER255_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER255_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER255_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER255_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER255_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER255_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER255_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER255_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER255_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER255_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER255_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER255_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER255_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER255_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER255_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER255_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER255_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER255_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER255_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER255_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER255_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER256 - GICDA_IROUTER256 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER256_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER256_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER256_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER256_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER256_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER256_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER256_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER256_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER256_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER256_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER256_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER256_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER256_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER256_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER256_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER256_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER256_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER256_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER256_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER256_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER256_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER256_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER256_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER256_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER256_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER256_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER256_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER256_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER256_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER256_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER256_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER256_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER256_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER256_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER256_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER257 - GICDA_IROUTER257 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER257_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER257_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER257_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER257_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER257_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER257_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER257_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER257_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER257_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER257_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER257_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER257_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER257_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER257_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER257_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER257_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER257_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER257_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER257_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER257_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER257_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER257_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER257_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER257_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER257_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER257_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER257_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER257_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER257_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER257_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER257_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER257_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER257_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER257_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER257_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER258 - GICDA_IROUTER258 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER258_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER258_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER258_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER258_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER258_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER258_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER258_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER258_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER258_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER258_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER258_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER258_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER258_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER258_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER258_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER258_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER258_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER258_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER258_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER258_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER258_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER258_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER258_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER258_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER258_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER258_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER258_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER258_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER258_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER258_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER258_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER258_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER258_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER258_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER258_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER259 - GICDA_IROUTER259 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER259_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER259_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER259_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER259_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER259_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER259_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER259_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER259_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER259_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER259_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER259_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER259_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER259_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER259_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER259_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER259_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER259_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER259_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER259_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER259_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER259_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER259_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER259_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER259_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER259_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER259_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER259_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER259_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER259_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER259_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER259_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER259_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER259_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER259_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER259_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER260 - GICDA_IROUTER260 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER260_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER260_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER260_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER260_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER260_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER260_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER260_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER260_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER260_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER260_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER260_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER260_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER260_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER260_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER260_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER260_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER260_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER260_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER260_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER260_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER260_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER260_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER260_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER260_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER260_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER260_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER260_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER260_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER260_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER260_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER260_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER260_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER260_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER260_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER260_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER261 - GICDA_IROUTER261 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER261_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER261_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER261_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER261_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER261_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER261_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER261_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER261_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER261_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER261_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER261_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER261_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER261_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER261_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER261_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER261_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER261_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER261_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER261_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER261_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER261_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER261_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER261_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER261_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER261_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER261_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER261_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER261_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER261_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER261_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER261_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER261_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER261_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER261_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER261_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER262 - GICDA_IROUTER262 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER262_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER262_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER262_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER262_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER262_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER262_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER262_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER262_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER262_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER262_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER262_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER262_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER262_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER262_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER262_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER262_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER262_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER262_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER262_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER262_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER262_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER262_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER262_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER262_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER262_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER262_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER262_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER262_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER262_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER262_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER262_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER262_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER262_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER262_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER262_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER263 - GICDA_IROUTER263 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER263_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER263_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER263_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER263_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER263_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER263_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER263_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER263_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER263_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER263_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER263_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER263_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER263_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER263_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER263_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER263_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER263_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER263_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER263_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER263_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER263_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER263_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER263_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER263_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER263_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER263_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER263_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER263_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER263_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER263_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER263_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER263_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER263_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER263_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER263_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER264 - GICDA_IROUTER264 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER264_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER264_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER264_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER264_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER264_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER264_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER264_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER264_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER264_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER264_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER264_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER264_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER264_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER264_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER264_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER264_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER264_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER264_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER264_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER264_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER264_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER264_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER264_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER264_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER264_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER264_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER264_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER264_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER264_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER264_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER264_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER264_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER264_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER264_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER264_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER265 - GICDA_IROUTER265 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER265_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER265_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER265_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER265_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER265_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER265_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER265_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER265_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER265_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER265_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER265_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER265_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER265_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER265_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER265_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER265_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER265_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER265_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER265_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER265_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER265_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER265_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER265_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER265_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER265_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER265_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER265_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER265_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER265_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER265_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER265_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER265_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER265_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER265_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER265_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER266 - GICDA_IROUTER266 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER266_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER266_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER266_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER266_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER266_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER266_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER266_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER266_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER266_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER266_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER266_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER266_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER266_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER266_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER266_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER266_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER266_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER266_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER266_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER266_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER266_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER266_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER266_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER266_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER266_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER266_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER266_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER266_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER266_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER266_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER266_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER266_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER266_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER266_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER266_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER267 - GICDA_IROUTER267 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER267_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER267_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER267_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER267_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER267_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER267_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER267_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER267_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER267_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER267_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER267_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER267_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER267_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER267_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER267_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER267_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER267_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER267_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER267_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER267_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER267_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER267_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER267_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER267_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER267_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER267_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER267_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER267_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER267_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER267_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER267_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER267_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER267_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER267_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER267_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER268 - GICDA_IROUTER268 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER268_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER268_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER268_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER268_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER268_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER268_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER268_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER268_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER268_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER268_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER268_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER268_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER268_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER268_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER268_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER268_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER268_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER268_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER268_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER268_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER268_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER268_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER268_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER268_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER268_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER268_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER268_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER268_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER268_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER268_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER268_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER268_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER268_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER268_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER268_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER269 - GICDA_IROUTER269 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER269_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER269_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER269_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER269_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER269_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER269_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER269_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER269_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER269_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER269_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER269_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER269_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER269_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER269_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER269_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER269_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER269_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER269_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER269_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER269_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER269_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER269_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER269_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER269_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER269_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER269_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER269_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER269_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER269_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER269_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER269_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER269_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER269_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER269_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER269_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER270 - GICDA_IROUTER270 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER270_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER270_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER270_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER270_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER270_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER270_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER270_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER270_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER270_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER270_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER270_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER270_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER270_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER270_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER270_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER270_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER270_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER270_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER270_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER270_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER270_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER270_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER270_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER270_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER270_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER270_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER270_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER270_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER270_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER270_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER270_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER270_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER270_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER270_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER270_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER271 - GICDA_IROUTER271 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER271_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER271_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER271_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER271_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER271_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER271_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER271_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER271_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER271_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER271_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER271_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER271_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER271_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER271_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER271_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER271_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER271_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER271_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER271_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER271_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER271_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER271_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER271_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER271_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER271_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER271_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER271_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER271_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER271_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER271_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER271_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER271_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER271_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER271_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER271_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER272 - GICDA_IROUTER272 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER272_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER272_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER272_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER272_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER272_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER272_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER272_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER272_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER272_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER272_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER272_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER272_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER272_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER272_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER272_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER272_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER272_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER272_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER272_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER272_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER272_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER272_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER272_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER272_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER272_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER272_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER272_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER272_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER272_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER272_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER272_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER272_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER272_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER272_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER272_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER273 - GICDA_IROUTER273 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER273_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER273_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER273_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER273_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER273_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER273_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER273_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER273_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER273_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER273_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER273_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER273_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER273_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER273_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER273_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER273_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER273_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER273_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER273_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER273_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER273_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER273_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER273_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER273_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER273_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER273_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER273_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER273_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER273_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER273_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER273_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER273_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER273_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER273_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER273_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER274 - GICDA_IROUTER274 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER274_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER274_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER274_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER274_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER274_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER274_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER274_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER274_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER274_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER274_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER274_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER274_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER274_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER274_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER274_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER274_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER274_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER274_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER274_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER274_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER274_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER274_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER274_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER274_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER274_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER274_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER274_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER274_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER274_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER274_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER274_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER274_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER274_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER274_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER274_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER275 - GICDA_IROUTER275 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER275_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER275_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER275_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER275_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER275_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER275_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER275_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER275_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER275_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER275_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER275_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER275_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER275_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER275_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER275_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER275_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER275_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER275_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER275_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER275_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER275_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER275_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER275_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER275_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER275_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER275_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER275_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER275_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER275_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER275_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER275_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER275_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER275_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER275_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER275_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER276 - GICDA_IROUTER276 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER276_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER276_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER276_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER276_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER276_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER276_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER276_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER276_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER276_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER276_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER276_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER276_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER276_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER276_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER276_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER276_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER276_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER276_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER276_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER276_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER276_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER276_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER276_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER276_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER276_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER276_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER276_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER276_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER276_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER276_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER276_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER276_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER276_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER276_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER276_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER277 - GICDA_IROUTER277 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER277_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER277_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER277_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER277_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER277_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER277_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER277_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER277_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER277_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER277_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER277_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER277_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER277_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER277_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER277_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER277_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER277_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER277_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER277_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER277_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER277_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER277_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER277_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER277_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER277_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER277_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER277_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER277_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER277_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER277_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER277_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER277_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER277_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER277_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER277_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER278 - GICDA_IROUTER278 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER278_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER278_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER278_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER278_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER278_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER278_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER278_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER278_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER278_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER278_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER278_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER278_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER278_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER278_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER278_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER278_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER278_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER278_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER278_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER278_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER278_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER278_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER278_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER278_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER278_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER278_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER278_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER278_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER278_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER278_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER278_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER278_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER278_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER278_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER278_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER279 - GICDA_IROUTER279 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER279_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER279_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER279_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER279_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER279_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER279_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER279_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER279_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER279_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER279_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER279_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER279_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER279_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER279_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER279_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER279_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER279_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER279_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER279_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER279_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER279_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER279_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER279_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER279_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER279_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER279_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER279_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER279_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER279_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER279_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER279_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER279_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER279_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER279_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER279_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER280 - GICDA_IROUTER280 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER280_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER280_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER280_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER280_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER280_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER280_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER280_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER280_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER280_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER280_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER280_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER280_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER280_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER280_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER280_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER280_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER280_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER280_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER280_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER280_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER280_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER280_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER280_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER280_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER280_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER280_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER280_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER280_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER280_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER280_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER280_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER280_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER280_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER280_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER280_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER281 - GICDA_IROUTER281 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER281_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER281_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER281_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER281_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER281_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER281_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER281_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER281_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER281_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER281_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER281_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER281_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER281_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER281_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER281_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER281_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER281_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER281_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER281_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER281_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER281_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER281_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER281_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER281_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER281_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER281_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER281_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER281_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER281_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER281_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER281_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER281_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER281_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER281_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER281_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER282 - GICDA_IROUTER282 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER282_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER282_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER282_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER282_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER282_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER282_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER282_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER282_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER282_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER282_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER282_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER282_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER282_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER282_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER282_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER282_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER282_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER282_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER282_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER282_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER282_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER282_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER282_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER282_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER282_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER282_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER282_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER282_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER282_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER282_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER282_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER282_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER282_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER282_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER282_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER283 - GICDA_IROUTER283 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER283_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER283_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER283_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER283_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER283_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER283_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER283_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER283_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER283_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER283_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER283_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER283_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER283_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER283_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER283_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER283_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER283_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER283_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER283_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER283_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER283_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER283_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER283_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER283_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER283_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER283_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER283_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER283_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER283_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER283_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER283_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER283_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER283_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER283_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER283_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER284 - GICDA_IROUTER284 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER284_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER284_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER284_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER284_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER284_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER284_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER284_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER284_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER284_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER284_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER284_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER284_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER284_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER284_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER284_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER284_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER284_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER284_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER284_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER284_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER284_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER284_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER284_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER284_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER284_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER284_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER284_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER284_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER284_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER284_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER284_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER284_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER284_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER284_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER284_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER285 - GICDA_IROUTER285 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER285_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER285_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER285_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER285_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER285_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER285_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER285_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER285_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER285_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER285_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER285_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER285_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER285_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER285_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER285_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER285_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER285_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER285_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER285_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER285_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER285_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER285_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER285_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER285_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER285_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER285_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER285_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER285_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER285_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER285_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER285_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER285_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER285_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER285_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER285_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER286 - GICDA_IROUTER286 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER286_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER286_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER286_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER286_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER286_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER286_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER286_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER286_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER286_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER286_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER286_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER286_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER286_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER286_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER286_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER286_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER286_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER286_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER286_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER286_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER286_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER286_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER286_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER286_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER286_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER286_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER286_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER286_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER286_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER286_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER286_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER286_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER286_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER286_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER286_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER287 - GICDA_IROUTER287 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER287_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER287_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER287_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER287_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER287_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER287_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER287_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER287_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER287_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER287_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER287_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER287_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER287_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER287_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER287_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER287_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER287_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER287_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER287_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER287_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER287_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER287_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER287_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER287_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER287_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER287_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER287_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER287_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER287_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER287_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER287_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER287_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER287_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER287_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER287_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER288 - GICDA_IROUTER288 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER288_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER288_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER288_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER288_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER288_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER288_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER288_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER288_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER288_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER288_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER288_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER288_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER288_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER288_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER288_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER288_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER288_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER288_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER288_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER288_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER288_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER288_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER288_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER288_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER288_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER288_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER288_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER288_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER288_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER288_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER288_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER288_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER288_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER288_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER288_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER289 - GICDA_IROUTER289 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER289_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER289_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER289_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER289_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER289_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER289_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER289_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER289_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER289_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER289_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER289_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER289_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER289_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER289_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER289_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER289_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER289_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER289_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER289_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER289_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER289_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER289_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER289_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER289_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER289_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER289_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER289_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER289_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER289_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER289_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER289_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER289_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER289_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER289_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER289_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER290 - GICDA_IROUTER290 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER290_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER290_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER290_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER290_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER290_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER290_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER290_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER290_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER290_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER290_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER290_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER290_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER290_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER290_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER290_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER290_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER290_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER290_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER290_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER290_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER290_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER290_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER290_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER290_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER290_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER290_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER290_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER290_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER290_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER290_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER290_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER290_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER290_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER290_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER290_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER291 - GICDA_IROUTER291 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER291_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER291_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER291_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER291_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER291_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER291_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER291_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER291_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER291_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER291_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER291_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER291_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER291_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER291_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER291_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER291_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER291_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER291_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER291_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER291_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER291_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER291_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER291_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER291_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER291_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER291_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER291_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER291_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER291_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER291_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER291_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER291_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER291_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER291_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER291_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER292 - GICDA_IROUTER292 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER292_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER292_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER292_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER292_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER292_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER292_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER292_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER292_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER292_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER292_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER292_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER292_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER292_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER292_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER292_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER292_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER292_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER292_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER292_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER292_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER292_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER292_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER292_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER292_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER292_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER292_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER292_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER292_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER292_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER292_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER292_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER292_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER292_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER292_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER292_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER293 - GICDA_IROUTER293 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER293_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER293_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER293_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER293_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER293_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER293_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER293_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER293_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER293_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER293_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER293_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER293_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER293_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER293_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER293_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER293_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER293_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER293_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER293_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER293_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER293_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER293_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER293_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER293_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER293_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER293_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER293_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER293_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER293_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER293_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER293_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER293_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER293_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER293_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER293_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER294 - GICDA_IROUTER294 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER294_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER294_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER294_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER294_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER294_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER294_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER294_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER294_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER294_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER294_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER294_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER294_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER294_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER294_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER294_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER294_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER294_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER294_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER294_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER294_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER294_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER294_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER294_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER294_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER294_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER294_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER294_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER294_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER294_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER294_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER294_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER294_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER294_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER294_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER294_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER295 - GICDA_IROUTER295 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER295_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER295_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER295_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER295_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER295_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER295_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER295_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER295_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER295_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER295_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER295_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER295_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER295_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER295_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER295_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER295_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER295_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER295_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER295_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER295_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER295_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER295_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER295_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER295_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER295_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER295_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER295_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER295_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER295_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER295_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER295_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER295_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER295_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER295_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER295_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER296 - GICDA_IROUTER296 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER296_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER296_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER296_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER296_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER296_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER296_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER296_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER296_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER296_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER296_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER296_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER296_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER296_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER296_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER296_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER296_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER296_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER296_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER296_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER296_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER296_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER296_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER296_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER296_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER296_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER296_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER296_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER296_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER296_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER296_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER296_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER296_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER296_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER296_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER296_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER297 - GICDA_IROUTER297 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER297_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER297_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER297_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER297_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER297_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER297_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER297_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER297_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER297_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER297_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER297_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER297_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER297_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER297_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER297_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER297_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER297_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER297_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER297_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER297_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER297_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER297_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER297_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER297_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER297_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER297_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER297_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER297_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER297_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER297_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER297_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER297_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER297_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER297_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER297_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER298 - GICDA_IROUTER298 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER298_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER298_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER298_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER298_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER298_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER298_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER298_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER298_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER298_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER298_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER298_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER298_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER298_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER298_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER298_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER298_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER298_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER298_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER298_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER298_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER298_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER298_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER298_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER298_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER298_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER298_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER298_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER298_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER298_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER298_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER298_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER298_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER298_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER298_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER298_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER299 - GICDA_IROUTER299 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER299_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER299_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER299_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER299_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER299_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER299_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER299_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER299_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER299_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER299_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER299_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER299_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER299_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER299_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER299_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER299_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER299_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER299_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER299_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER299_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER299_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER299_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER299_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER299_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER299_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER299_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER299_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER299_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER299_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER299_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER299_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER299_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER299_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER299_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER299_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER300 - GICDA_IROUTER300 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER300_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER300_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER300_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER300_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER300_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER300_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER300_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER300_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER300_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER300_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER300_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER300_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER300_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER300_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER300_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER300_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER300_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER300_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER300_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER300_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER300_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER300_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER300_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER300_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER300_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER300_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER300_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER300_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER300_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER300_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER300_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER300_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER300_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER300_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER300_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER301 - GICDA_IROUTER301 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER301_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER301_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER301_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER301_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER301_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER301_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER301_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER301_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER301_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER301_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER301_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER301_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER301_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER301_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER301_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER301_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER301_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER301_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER301_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER301_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER301_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER301_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER301_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER301_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER301_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER301_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER301_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER301_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER301_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER301_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER301_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER301_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER301_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER301_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER301_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER302 - GICDA_IROUTER302 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER302_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER302_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER302_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER302_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER302_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER302_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER302_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER302_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER302_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER302_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER302_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER302_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER302_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER302_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER302_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER302_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER302_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER302_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER302_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER302_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER302_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER302_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER302_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER302_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER302_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER302_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER302_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER302_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER302_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER302_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER302_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER302_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER302_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER302_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER302_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER303 - GICDA_IROUTER303 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER303_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER303_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER303_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER303_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER303_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER303_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER303_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER303_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER303_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER303_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER303_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER303_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER303_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER303_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER303_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER303_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER303_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER303_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER303_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER303_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER303_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER303_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER303_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER303_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER303_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER303_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER303_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER303_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER303_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER303_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER303_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER303_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER303_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER303_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER303_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER304 - GICDA_IROUTER304 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER304_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER304_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER304_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER304_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER304_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER304_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER304_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER304_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER304_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER304_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER304_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER304_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER304_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER304_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER304_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER304_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER304_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER304_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER304_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER304_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER304_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER304_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER304_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER304_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER304_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER304_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER304_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER304_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER304_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER304_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER304_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER304_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER304_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER304_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER304_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER305 - GICDA_IROUTER305 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER305_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER305_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER305_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER305_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER305_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER305_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER305_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER305_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER305_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER305_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER305_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER305_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER305_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER305_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER305_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER305_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER305_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER305_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER305_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER305_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER305_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER305_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER305_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER305_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER305_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER305_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER305_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER305_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER305_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER305_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER305_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER305_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER305_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER305_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER305_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER306 - GICDA_IROUTER306 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER306_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER306_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER306_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER306_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER306_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER306_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER306_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER306_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER306_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER306_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER306_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER306_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER306_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER306_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER306_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER306_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER306_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER306_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER306_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER306_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER306_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER306_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER306_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER306_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER306_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER306_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER306_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER306_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER306_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER306_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER306_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER306_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER306_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER306_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER306_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER307 - GICDA_IROUTER307 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER307_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER307_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER307_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER307_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER307_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER307_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER307_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER307_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER307_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER307_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER307_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER307_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER307_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER307_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER307_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER307_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER307_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER307_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER307_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER307_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER307_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER307_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER307_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER307_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER307_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER307_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER307_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER307_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER307_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER307_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER307_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER307_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER307_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER307_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER307_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER308 - GICDA_IROUTER308 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER308_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER308_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER308_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER308_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER308_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER308_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER308_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER308_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER308_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER308_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER308_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER308_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER308_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER308_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER308_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER308_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER308_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER308_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER308_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER308_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER308_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER308_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER308_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER308_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER308_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER308_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER308_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER308_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER308_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER308_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER308_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER308_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER308_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER308_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER308_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER309 - GICDA_IROUTER309 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER309_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER309_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER309_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER309_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER309_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER309_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER309_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER309_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER309_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER309_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER309_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER309_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER309_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER309_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER309_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER309_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER309_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER309_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER309_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER309_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER309_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER309_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER309_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER309_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER309_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER309_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER309_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER309_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER309_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER309_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER309_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER309_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER309_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER309_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER309_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER310 - GICDA_IROUTER310 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER310_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER310_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER310_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER310_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER310_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER310_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER310_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER310_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER310_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER310_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER310_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER310_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER310_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER310_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER310_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER310_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER310_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER310_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER310_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER310_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER310_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER310_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER310_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER310_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER310_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER310_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER310_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER310_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER310_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER310_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER310_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER310_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER310_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER310_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER310_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER311 - GICDA_IROUTER311 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER311_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER311_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER311_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER311_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER311_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER311_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER311_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER311_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER311_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER311_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER311_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER311_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER311_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER311_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER311_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER311_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER311_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER311_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER311_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER311_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER311_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER311_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER311_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER311_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER311_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER311_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER311_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER311_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER311_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER311_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER311_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER311_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER311_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER311_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER311_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER312 - GICDA_IROUTER312 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER312_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER312_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER312_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER312_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER312_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER312_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER312_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER312_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER312_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER312_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER312_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER312_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER312_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER312_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER312_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER312_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER312_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER312_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER312_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER312_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER312_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER312_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER312_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER312_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER312_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER312_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER312_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER312_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER312_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER312_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER312_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER312_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER312_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER312_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER312_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER313 - GICDA_IROUTER313 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER313_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER313_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER313_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER313_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER313_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER313_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER313_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER313_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER313_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER313_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER313_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER313_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER313_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER313_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER313_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER313_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER313_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER313_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER313_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER313_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER313_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER313_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER313_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER313_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER313_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER313_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER313_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER313_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER313_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER313_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER313_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER313_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER313_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER313_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER313_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER314 - GICDA_IROUTER314 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER314_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER314_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER314_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER314_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER314_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER314_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER314_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER314_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER314_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER314_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER314_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER314_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER314_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER314_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER314_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER314_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER314_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER314_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER314_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER314_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER314_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER314_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER314_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER314_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER314_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER314_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER314_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER314_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER314_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER314_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER314_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER314_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER314_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER314_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER314_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER315 - GICDA_IROUTER315 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER315_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER315_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER315_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER315_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER315_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER315_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER315_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER315_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER315_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER315_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER315_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER315_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER315_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER315_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER315_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER315_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER315_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER315_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER315_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER315_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER315_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER315_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER315_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER315_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER315_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER315_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER315_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER315_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER315_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER315_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER315_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER315_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER315_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER315_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER315_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER316 - GICDA_IROUTER316 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER316_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER316_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER316_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER316_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER316_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER316_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER316_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER316_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER316_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER316_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER316_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER316_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER316_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER316_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER316_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER316_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER316_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER316_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER316_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER316_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER316_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER316_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER316_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER316_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER316_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER316_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER316_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER316_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER316_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER316_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER316_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER316_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER316_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER316_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER316_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER317 - GICDA_IROUTER317 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER317_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER317_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER317_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER317_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER317_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER317_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER317_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER317_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER317_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER317_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER317_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER317_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER317_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER317_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER317_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER317_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER317_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER317_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER317_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER317_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER317_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER317_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER317_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER317_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER317_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER317_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER317_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER317_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER317_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER317_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER317_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER317_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER317_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER317_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER317_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER318 - GICDA_IROUTER318 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER318_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER318_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER318_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER318_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER318_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER318_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER318_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER318_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER318_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER318_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER318_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER318_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER318_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER318_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER318_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER318_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER318_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER318_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER318_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER318_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER318_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER318_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER318_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER318_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER318_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER318_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER318_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER318_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER318_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER318_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER318_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER318_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER318_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER318_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER318_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER319 - GICDA_IROUTER319 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER319_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER319_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER319_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER319_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER319_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER319_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER319_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER319_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER319_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER319_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER319_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER319_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER319_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER319_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER319_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER319_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER319_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER319_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER319_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER319_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER319_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER319_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER319_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER319_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER319_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER319_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER319_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER319_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER319_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER319_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER319_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER319_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER319_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER319_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER319_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER320 - GICDA_IROUTER320 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER320_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER320_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER320_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER320_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER320_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER320_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER320_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER320_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER320_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER320_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER320_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER320_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER320_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER320_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER320_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER320_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER320_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER320_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER320_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER320_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER320_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER320_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER320_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER320_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER320_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER320_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER320_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER320_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER320_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER320_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER320_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER320_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER320_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER320_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER320_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER321 - GICDA_IROUTER321 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER321_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER321_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER321_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER321_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER321_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER321_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER321_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER321_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER321_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER321_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER321_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER321_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER321_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER321_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER321_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER321_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER321_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER321_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER321_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER321_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER321_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER321_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER321_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER321_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER321_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER321_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER321_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER321_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER321_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER321_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER321_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER321_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER321_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER321_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER321_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER322 - GICDA_IROUTER322 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER322_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER322_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER322_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER322_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER322_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER322_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER322_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER322_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER322_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER322_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER322_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER322_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER322_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER322_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER322_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER322_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER322_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER322_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER322_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER322_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER322_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER322_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER322_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER322_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER322_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER322_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER322_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER322_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER322_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER322_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER322_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER322_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER322_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER322_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER322_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER323 - GICDA_IROUTER323 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER323_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER323_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER323_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER323_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER323_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER323_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER323_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER323_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER323_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER323_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER323_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER323_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER323_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER323_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER323_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER323_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER323_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER323_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER323_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER323_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER323_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER323_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER323_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER323_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER323_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER323_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER323_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER323_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER323_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER323_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER323_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER323_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER323_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER323_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER323_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER324 - GICDA_IROUTER324 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER324_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER324_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER324_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER324_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER324_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER324_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER324_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER324_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER324_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER324_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER324_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER324_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER324_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER324_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER324_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER324_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER324_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER324_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER324_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER324_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER324_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER324_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER324_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER324_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER324_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER324_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER324_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER324_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER324_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER324_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER324_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER324_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER324_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER324_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER324_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER325 - GICDA_IROUTER325 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER325_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER325_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER325_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER325_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER325_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER325_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER325_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER325_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER325_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER325_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER325_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER325_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER325_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER325_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER325_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER325_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER325_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER325_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER325_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER325_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER325_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER325_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER325_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER325_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER325_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER325_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER325_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER325_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER325_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER325_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER325_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER325_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER325_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER325_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER325_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER326 - GICDA_IROUTER326 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER326_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER326_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER326_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER326_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER326_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER326_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER326_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER326_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER326_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER326_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER326_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER326_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER326_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER326_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER326_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER326_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER326_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER326_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER326_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER326_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER326_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER326_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER326_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER326_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER326_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER326_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER326_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER326_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER326_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER326_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER326_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER326_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER326_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER326_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER326_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER327 - GICDA_IROUTER327 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER327_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER327_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER327_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER327_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER327_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER327_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER327_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER327_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER327_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER327_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER327_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER327_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER327_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER327_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER327_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER327_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER327_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER327_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER327_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER327_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER327_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER327_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER327_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER327_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER327_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER327_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER327_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER327_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER327_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER327_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER327_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER327_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER327_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER327_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER327_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER328 - GICDA_IROUTER328 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER328_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER328_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER328_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER328_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER328_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER328_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER328_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER328_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER328_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER328_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER328_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER328_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER328_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER328_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER328_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER328_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER328_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER328_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER328_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER328_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER328_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER328_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER328_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER328_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER328_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER328_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER328_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER328_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER328_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER328_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER328_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER328_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER328_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER328_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER328_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER329 - GICDA_IROUTER329 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER329_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER329_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER329_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER329_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER329_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER329_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER329_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER329_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER329_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER329_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER329_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER329_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER329_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER329_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER329_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER329_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER329_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER329_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER329_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER329_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER329_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER329_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER329_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER329_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER329_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER329_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER329_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER329_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER329_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER329_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER329_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER329_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER329_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER329_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER329_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER330 - GICDA_IROUTER330 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER330_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER330_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER330_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER330_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER330_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER330_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER330_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER330_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER330_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER330_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER330_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER330_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER330_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER330_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER330_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER330_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER330_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER330_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER330_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER330_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER330_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER330_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER330_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER330_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER330_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER330_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER330_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER330_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER330_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER330_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER330_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER330_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER330_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER330_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER330_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER331 - GICDA_IROUTER331 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER331_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER331_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER331_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER331_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER331_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER331_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER331_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER331_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER331_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER331_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER331_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER331_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER331_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER331_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER331_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER331_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER331_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER331_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER331_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER331_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER331_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER331_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER331_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER331_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER331_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER331_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER331_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER331_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER331_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER331_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER331_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER331_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER331_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER331_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER331_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER332 - GICDA_IROUTER332 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER332_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER332_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER332_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER332_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER332_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER332_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER332_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER332_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER332_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER332_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER332_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER332_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER332_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER332_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER332_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER332_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER332_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER332_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER332_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER332_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER332_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER332_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER332_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER332_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER332_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER332_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER332_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER332_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER332_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER332_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER332_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER332_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER332_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER332_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER332_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER333 - GICDA_IROUTER333 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER333_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER333_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER333_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER333_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER333_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER333_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER333_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER333_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER333_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER333_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER333_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER333_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER333_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER333_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER333_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER333_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER333_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER333_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER333_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER333_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER333_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER333_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER333_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER333_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER333_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER333_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER333_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER333_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER333_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER333_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER333_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER333_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER333_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER333_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER333_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER334 - GICDA_IROUTER334 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER334_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER334_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER334_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER334_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER334_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER334_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER334_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER334_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER334_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER334_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER334_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER334_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER334_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER334_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER334_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER334_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER334_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER334_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER334_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER334_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER334_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER334_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER334_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER334_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER334_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER334_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER334_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER334_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER334_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER334_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER334_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER334_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER334_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER334_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER334_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER335 - GICDA_IROUTER335 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER335_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER335_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER335_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER335_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER335_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER335_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER335_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER335_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER335_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER335_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER335_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER335_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER335_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER335_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER335_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER335_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER335_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER335_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER335_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER335_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER335_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER335_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER335_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER335_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER335_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER335_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER335_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER335_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER335_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER335_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER335_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER335_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER335_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER335_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER335_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER336 - GICDA_IROUTER336 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER336_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER336_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER336_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER336_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER336_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER336_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER336_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER336_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER336_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER336_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER336_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER336_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER336_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER336_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER336_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER336_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER336_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER336_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER336_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER336_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER336_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER336_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER336_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER336_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER336_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER336_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER336_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER336_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER336_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER336_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER336_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER336_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER336_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER336_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER336_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER337 - GICDA_IROUTER337 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER337_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER337_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER337_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER337_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER337_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER337_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER337_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER337_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER337_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER337_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER337_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER337_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER337_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER337_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER337_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER337_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER337_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER337_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER337_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER337_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER337_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER337_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER337_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER337_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER337_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER337_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER337_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER337_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER337_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER337_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER337_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER337_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER337_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER337_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER337_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER338 - GICDA_IROUTER338 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER338_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER338_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER338_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER338_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER338_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER338_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER338_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER338_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER338_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER338_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER338_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER338_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER338_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER338_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER338_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER338_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER338_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER338_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER338_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER338_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER338_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER338_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER338_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER338_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER338_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER338_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER338_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER338_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER338_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER338_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER338_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER338_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER338_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER338_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER338_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER339 - GICDA_IROUTER339 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER339_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER339_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER339_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER339_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER339_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER339_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER339_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER339_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER339_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER339_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER339_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER339_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER339_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER339_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER339_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER339_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER339_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER339_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER339_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER339_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER339_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER339_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER339_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER339_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER339_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER339_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER339_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER339_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER339_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER339_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER339_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER339_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER339_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER339_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER339_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER340 - GICDA_IROUTER340 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER340_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER340_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER340_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER340_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER340_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER340_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER340_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER340_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER340_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER340_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER340_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER340_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER340_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER340_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER340_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER340_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER340_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER340_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER340_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER340_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER340_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER340_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER340_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER340_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER340_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER340_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER340_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER340_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER340_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER340_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER340_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER340_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER340_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER340_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER340_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER341 - GICDA_IROUTER341 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER341_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER341_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER341_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER341_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER341_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER341_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER341_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER341_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER341_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER341_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER341_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER341_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER341_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER341_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER341_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER341_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER341_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER341_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER341_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER341_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER341_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER341_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER341_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER341_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER341_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER341_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER341_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER341_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER341_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER341_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER341_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER341_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER341_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER341_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER341_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER342 - GICDA_IROUTER342 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER342_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER342_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER342_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER342_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER342_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER342_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER342_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER342_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER342_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER342_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER342_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER342_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER342_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER342_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER342_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER342_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER342_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER342_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER342_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER342_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER342_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER342_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER342_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER342_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER342_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER342_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER342_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER342_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER342_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER342_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER342_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER342_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER342_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER342_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER342_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER343 - GICDA_IROUTER343 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER343_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER343_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER343_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER343_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER343_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER343_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER343_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER343_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER343_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER343_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER343_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER343_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER343_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER343_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER343_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER343_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER343_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER343_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER343_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER343_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER343_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER343_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER343_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER343_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER343_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER343_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER343_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER343_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER343_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER343_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER343_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER343_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER343_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER343_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER343_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER344 - GICDA_IROUTER344 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER344_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER344_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER344_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER344_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER344_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER344_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER344_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER344_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER344_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER344_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER344_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER344_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER344_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER344_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER344_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER344_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER344_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER344_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER344_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER344_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER344_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER344_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER344_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER344_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER344_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER344_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER344_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER344_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER344_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER344_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER344_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER344_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER344_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER344_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER344_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER345 - GICDA_IROUTER345 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER345_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER345_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER345_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER345_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER345_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER345_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER345_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER345_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER345_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER345_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER345_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER345_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER345_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER345_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER345_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER345_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER345_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER345_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER345_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER345_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER345_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER345_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER345_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER345_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER345_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER345_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER345_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER345_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER345_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER345_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER345_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER345_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER345_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER345_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER345_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER346 - GICDA_IROUTER346 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER346_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER346_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER346_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER346_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER346_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER346_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER346_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER346_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER346_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER346_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER346_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER346_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER346_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER346_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER346_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER346_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER346_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER346_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER346_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER346_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER346_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER346_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER346_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER346_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER346_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER346_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER346_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER346_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER346_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER346_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER346_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER346_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER346_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER346_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER346_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER347 - GICDA_IROUTER347 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER347_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER347_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER347_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER347_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER347_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER347_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER347_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER347_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER347_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER347_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER347_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER347_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER347_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER347_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER347_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER347_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER347_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER347_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER347_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER347_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER347_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER347_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER347_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER347_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER347_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER347_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER347_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER347_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER347_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER347_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER347_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER347_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER347_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER347_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER347_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER348 - GICDA_IROUTER348 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER348_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER348_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER348_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER348_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER348_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER348_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER348_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER348_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER348_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER348_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER348_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER348_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER348_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER348_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER348_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER348_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER348_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER348_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER348_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER348_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER348_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER348_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER348_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER348_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER348_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER348_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER348_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER348_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER348_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER348_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER348_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER348_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER348_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER348_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER348_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER349 - GICDA_IROUTER349 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER349_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER349_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER349_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER349_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER349_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER349_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER349_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER349_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER349_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER349_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER349_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER349_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER349_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER349_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER349_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER349_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER349_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER349_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER349_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER349_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER349_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER349_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER349_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER349_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER349_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER349_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER349_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER349_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER349_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER349_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER349_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER349_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER349_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER349_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER349_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER350 - GICDA_IROUTER350 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER350_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER350_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER350_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER350_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER350_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER350_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER350_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER350_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER350_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER350_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER350_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER350_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER350_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER350_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER350_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER350_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER350_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER350_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER350_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER350_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER350_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER350_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER350_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER350_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER350_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER350_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER350_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER350_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER350_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER350_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER350_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER350_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER350_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER350_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER350_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER351 - GICDA_IROUTER351 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER351_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER351_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER351_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER351_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER351_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER351_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER351_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER351_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER351_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER351_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER351_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER351_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER351_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER351_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER351_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER351_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER351_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER351_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER351_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER351_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER351_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER351_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER351_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER351_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER351_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER351_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER351_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER351_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER351_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER351_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER351_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER351_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER351_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER351_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER351_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER352 - GICDA_IROUTER352 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER352_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER352_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER352_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER352_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER352_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER352_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER352_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER352_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER352_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER352_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER352_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER352_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER352_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER352_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER352_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER352_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER352_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER352_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER352_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER352_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER352_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER352_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER352_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER352_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER352_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER352_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER352_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER352_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER352_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER352_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER352_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER352_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER352_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER352_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER352_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER353 - GICDA_IROUTER353 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER353_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER353_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER353_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER353_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER353_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER353_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER353_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER353_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER353_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER353_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER353_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER353_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER353_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER353_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER353_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER353_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER353_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER353_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER353_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER353_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER353_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER353_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER353_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER353_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER353_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER353_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER353_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER353_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER353_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER353_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER353_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER353_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER353_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER353_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER353_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER354 - GICDA_IROUTER354 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER354_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER354_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER354_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER354_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER354_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER354_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER354_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER354_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER354_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER354_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER354_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER354_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER354_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER354_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER354_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER354_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER354_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER354_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER354_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER354_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER354_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER354_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER354_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER354_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER354_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER354_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER354_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER354_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER354_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER354_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER354_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER354_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER354_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER354_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER354_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER355 - GICDA_IROUTER355 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER355_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER355_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER355_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER355_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER355_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER355_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER355_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER355_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER355_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER355_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER355_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER355_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER355_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER355_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER355_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER355_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER355_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER355_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER355_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER355_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER355_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER355_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER355_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER355_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER355_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER355_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER355_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER355_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER355_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER355_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER355_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER355_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER355_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER355_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER355_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER356 - GICDA_IROUTER356 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER356_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER356_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER356_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER356_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER356_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER356_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER356_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER356_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER356_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER356_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER356_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER356_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER356_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER356_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER356_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER356_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER356_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER356_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER356_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER356_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER356_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER356_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER356_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER356_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER356_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER356_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER356_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER356_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER356_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER356_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER356_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER356_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER356_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER356_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER356_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER357 - GICDA_IROUTER357 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER357_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER357_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER357_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER357_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER357_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER357_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER357_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER357_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER357_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER357_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER357_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER357_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER357_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER357_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER357_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER357_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER357_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER357_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER357_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER357_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER357_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER357_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER357_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER357_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER357_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER357_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER357_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER357_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER357_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER357_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER357_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER357_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER357_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER357_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER357_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER358 - GICDA_IROUTER358 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER358_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER358_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER358_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER358_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER358_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER358_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER358_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER358_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER358_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER358_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER358_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER358_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER358_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER358_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER358_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER358_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER358_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER358_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER358_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER358_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER358_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER358_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER358_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER358_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER358_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER358_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER358_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER358_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER358_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER358_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER358_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER358_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER358_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER358_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER358_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER359 - GICDA_IROUTER359 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER359_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER359_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER359_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER359_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER359_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER359_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER359_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER359_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER359_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER359_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER359_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER359_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER359_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER359_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER359_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER359_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER359_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER359_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER359_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER359_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER359_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER359_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER359_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER359_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER359_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER359_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER359_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER359_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER359_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER359_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER359_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER359_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER359_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER359_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER359_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER360 - GICDA_IROUTER360 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER360_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER360_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER360_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER360_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER360_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER360_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER360_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER360_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER360_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER360_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER360_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER360_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER360_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER360_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER360_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER360_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER360_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER360_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER360_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER360_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER360_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER360_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER360_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER360_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER360_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER360_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER360_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER360_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER360_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER360_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER360_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER360_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER360_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER360_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER360_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER361 - GICDA_IROUTER361 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER361_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER361_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER361_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER361_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER361_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER361_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER361_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER361_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER361_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER361_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER361_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER361_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER361_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER361_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER361_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER361_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER361_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER361_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER361_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER361_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER361_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER361_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER361_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER361_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER361_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER361_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER361_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER361_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER361_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER361_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER361_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER361_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER361_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER361_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER361_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER362 - GICDA_IROUTER362 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER362_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER362_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER362_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER362_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER362_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER362_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER362_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER362_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER362_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER362_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER362_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER362_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER362_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER362_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER362_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER362_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER362_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER362_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER362_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER362_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER362_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER362_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER362_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER362_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER362_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER362_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER362_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER362_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER362_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER362_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER362_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER362_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER362_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER362_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER362_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER363 - GICDA_IROUTER363 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER363_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER363_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER363_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER363_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER363_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER363_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER363_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER363_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER363_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER363_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER363_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER363_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER363_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER363_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER363_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER363_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER363_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER363_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER363_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER363_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER363_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER363_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER363_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER363_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER363_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER363_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER363_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER363_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER363_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER363_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER363_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER363_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER363_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER363_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER363_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER364 - GICDA_IROUTER364 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER364_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER364_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER364_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER364_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER364_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER364_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER364_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER364_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER364_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER364_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER364_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER364_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER364_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER364_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER364_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER364_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER364_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER364_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER364_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER364_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER364_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER364_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER364_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER364_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER364_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER364_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER364_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER364_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER364_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER364_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER364_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER364_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER364_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER364_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER364_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER365 - GICDA_IROUTER365 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER365_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER365_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER365_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER365_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER365_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER365_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER365_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER365_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER365_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER365_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER365_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER365_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER365_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER365_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER365_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER365_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER365_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER365_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER365_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER365_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER365_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER365_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER365_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER365_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER365_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER365_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER365_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER365_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER365_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER365_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER365_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER365_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER365_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER365_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER365_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER366 - GICDA_IROUTER366 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER366_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER366_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER366_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER366_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER366_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER366_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER366_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER366_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER366_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER366_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER366_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER366_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER366_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER366_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER366_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER366_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER366_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER366_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER366_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER366_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER366_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER366_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER366_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER366_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER366_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER366_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER366_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER366_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER366_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER366_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER366_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER366_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER366_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER366_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER366_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER367 - GICDA_IROUTER367 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER367_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER367_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER367_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER367_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER367_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER367_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER367_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER367_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER367_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER367_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER367_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER367_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER367_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER367_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER367_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER367_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER367_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER367_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER367_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER367_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER367_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER367_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER367_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER367_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER367_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER367_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER367_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER367_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER367_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER367_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER367_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER367_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER367_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER367_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER367_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER368 - GICDA_IROUTER368 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER368_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER368_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER368_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER368_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER368_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER368_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER368_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER368_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER368_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER368_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER368_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER368_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER368_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER368_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER368_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER368_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER368_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER368_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER368_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER368_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER368_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER368_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER368_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER368_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER368_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER368_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER368_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER368_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER368_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER368_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER368_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER368_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER368_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER368_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER368_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER369 - GICDA_IROUTER369 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER369_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER369_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER369_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER369_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER369_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER369_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER369_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER369_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER369_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER369_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER369_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER369_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER369_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER369_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER369_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER369_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER369_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER369_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER369_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER369_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER369_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER369_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER369_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER369_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER369_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER369_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER369_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER369_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER369_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER369_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER369_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER369_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER369_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER369_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER369_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER370 - GICDA_IROUTER370 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER370_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER370_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER370_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER370_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER370_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER370_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER370_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER370_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER370_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER370_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER370_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER370_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER370_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER370_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER370_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER370_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER370_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER370_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER370_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER370_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER370_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER370_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER370_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER370_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER370_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER370_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER370_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER370_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER370_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER370_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER370_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER370_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER370_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER370_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER370_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER371 - GICDA_IROUTER371 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER371_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER371_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER371_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER371_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER371_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER371_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER371_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER371_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER371_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER371_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER371_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER371_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER371_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER371_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER371_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER371_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER371_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER371_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER371_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER371_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER371_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER371_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER371_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER371_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER371_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER371_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER371_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER371_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER371_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER371_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER371_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER371_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER371_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER371_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER371_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER372 - GICDA_IROUTER372 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER372_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER372_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER372_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER372_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER372_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER372_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER372_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER372_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER372_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER372_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER372_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER372_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER372_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER372_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER372_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER372_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER372_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER372_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER372_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER372_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER372_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER372_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER372_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER372_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER372_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER372_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER372_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER372_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER372_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER372_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER372_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER372_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER372_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER372_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER372_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER373 - GICDA_IROUTER373 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER373_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER373_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER373_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER373_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER373_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER373_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER373_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER373_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER373_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER373_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER373_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER373_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER373_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER373_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER373_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER373_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER373_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER373_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER373_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER373_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER373_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER373_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER373_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER373_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER373_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER373_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER373_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER373_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER373_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER373_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER373_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER373_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER373_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER373_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER373_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER374 - GICDA_IROUTER374 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER374_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER374_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER374_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER374_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER374_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER374_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER374_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER374_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER374_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER374_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER374_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER374_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER374_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER374_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER374_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER374_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER374_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER374_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER374_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER374_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER374_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER374_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER374_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER374_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER374_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER374_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER374_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER374_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER374_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER374_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER374_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER374_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER374_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER374_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER374_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER375 - GICDA_IROUTER375 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER375_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER375_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER375_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER375_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER375_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER375_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER375_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER375_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER375_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER375_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER375_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER375_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER375_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER375_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER375_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER375_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER375_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER375_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER375_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER375_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER375_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER375_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER375_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER375_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER375_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER375_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER375_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER375_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER375_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER375_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER375_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER375_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER375_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER375_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER375_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER376 - GICDA_IROUTER376 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER376_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER376_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER376_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER376_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER376_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER376_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER376_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER376_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER376_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER376_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER376_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER376_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER376_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER376_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER376_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER376_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER376_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER376_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER376_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER376_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER376_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER376_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER376_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER376_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER376_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER376_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER376_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER376_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER376_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER376_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER376_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER376_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER376_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER376_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER376_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER377 - GICDA_IROUTER377 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER377_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER377_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER377_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER377_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER377_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER377_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER377_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER377_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER377_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER377_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER377_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER377_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER377_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER377_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER377_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER377_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER377_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER377_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER377_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER377_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER377_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER377_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER377_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER377_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER377_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER377_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER377_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER377_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER377_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER377_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER377_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER377_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER377_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER377_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER377_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER378 - GICDA_IROUTER378 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER378_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER378_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER378_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER378_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER378_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER378_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER378_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER378_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER378_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER378_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER378_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER378_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER378_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER378_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER378_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER378_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER378_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER378_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER378_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER378_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER378_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER378_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER378_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER378_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER378_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER378_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER378_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER378_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER378_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER378_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER378_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER378_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER378_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER378_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER378_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER379 - GICDA_IROUTER379 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER379_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER379_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER379_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER379_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER379_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER379_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER379_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER379_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER379_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER379_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER379_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER379_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER379_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER379_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER379_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER379_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER379_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER379_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER379_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER379_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER379_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER379_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER379_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER379_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER379_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER379_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER379_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER379_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER379_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER379_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER379_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER379_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER379_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER379_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER379_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER380 - GICDA_IROUTER380 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER380_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER380_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER380_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER380_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER380_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER380_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER380_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER380_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER380_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER380_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER380_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER380_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER380_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER380_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER380_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER380_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER380_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER380_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER380_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER380_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER380_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER380_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER380_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER380_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER380_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER380_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER380_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER380_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER380_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER380_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER380_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER380_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER380_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER380_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER380_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER381 - GICDA_IROUTER381 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER381_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER381_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER381_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER381_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER381_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER381_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER381_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER381_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER381_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER381_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER381_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER381_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER381_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER381_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER381_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER381_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER381_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER381_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER381_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER381_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER381_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER381_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER381_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER381_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER381_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER381_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER381_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER381_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER381_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER381_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER381_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER381_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER381_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER381_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER381_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER382 - GICDA_IROUTER382 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER382_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER382_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER382_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER382_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER382_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER382_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER382_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER382_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER382_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER382_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER382_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER382_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER382_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER382_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER382_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER382_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER382_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER382_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER382_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER382_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER382_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER382_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER382_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER382_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER382_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER382_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER382_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER382_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER382_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER382_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER382_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER382_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER382_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER382_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER382_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER383 - GICDA_IROUTER383 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER383_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER383_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER383_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER383_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER383_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER383_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER383_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER383_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER383_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER383_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER383_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER383_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER383_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER383_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER383_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER383_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER383_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER383_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER383_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER383_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER383_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER383_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER383_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER383_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER383_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER383_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER383_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER383_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER383_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER383_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER383_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER383_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER383_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER383_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER383_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER384 - GICDA_IROUTER384 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER384_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER384_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER384_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER384_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER384_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER384_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER384_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER384_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER384_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER384_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER384_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER384_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER384_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER384_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER384_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER384_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER384_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER384_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER384_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER384_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER384_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER384_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER384_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER384_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER384_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER384_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER384_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER384_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER384_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER384_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER384_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER384_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER384_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER384_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER384_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER385 - GICDA_IROUTER385 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER385_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER385_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER385_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER385_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER385_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER385_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER385_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER385_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER385_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER385_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER385_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER385_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER385_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER385_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER385_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER385_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER385_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER385_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER385_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER385_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER385_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER385_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER385_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER385_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER385_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER385_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER385_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER385_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER385_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER385_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER385_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER385_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER385_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER385_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER385_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER386 - GICDA_IROUTER386 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER386_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER386_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER386_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER386_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER386_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER386_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER386_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER386_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER386_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER386_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER386_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER386_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER386_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER386_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER386_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER386_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER386_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER386_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER386_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER386_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER386_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER386_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER386_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER386_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER386_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER386_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER386_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER386_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER386_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER386_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER386_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER386_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER386_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER386_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER386_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER387 - GICDA_IROUTER387 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER387_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER387_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER387_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER387_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER387_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER387_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER387_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER387_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER387_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER387_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER387_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER387_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER387_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER387_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER387_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER387_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER387_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER387_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER387_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER387_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER387_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER387_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER387_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER387_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER387_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER387_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER387_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER387_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER387_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER387_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER387_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER387_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER387_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER387_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER387_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER388 - GICDA_IROUTER388 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER388_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER388_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER388_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER388_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER388_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER388_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER388_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER388_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER388_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER388_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER388_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER388_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER388_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER388_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER388_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER388_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER388_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER388_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER388_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER388_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER388_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER388_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER388_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER388_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER388_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER388_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER388_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER388_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER388_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER388_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER388_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER388_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER388_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER388_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER388_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER389 - GICDA_IROUTER389 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER389_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER389_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER389_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER389_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER389_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER389_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER389_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER389_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER389_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER389_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER389_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER389_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER389_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER389_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER389_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER389_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER389_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER389_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER389_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER389_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER389_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER389_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER389_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER389_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER389_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER389_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER389_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER389_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER389_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER389_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER389_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER389_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER389_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER389_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER389_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER390 - GICDA_IROUTER390 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER390_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER390_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER390_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER390_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER390_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER390_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER390_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER390_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER390_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER390_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER390_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER390_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER390_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER390_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER390_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER390_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER390_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER390_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER390_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER390_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER390_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER390_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER390_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER390_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER390_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER390_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER390_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER390_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER390_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER390_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER390_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER390_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER390_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER390_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER390_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER391 - GICDA_IROUTER391 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER391_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER391_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER391_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER391_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER391_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER391_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER391_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER391_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER391_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER391_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER391_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER391_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER391_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER391_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER391_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER391_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER391_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER391_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER391_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER391_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER391_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER391_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER391_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER391_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER391_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER391_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER391_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER391_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER391_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER391_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER391_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER391_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER391_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER391_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER391_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER392 - GICDA_IROUTER392 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER392_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER392_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER392_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER392_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER392_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER392_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER392_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER392_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER392_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER392_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER392_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER392_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER392_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER392_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER392_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER392_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER392_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER392_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER392_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER392_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER392_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER392_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER392_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER392_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER392_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER392_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER392_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER392_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER392_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER392_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER392_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER392_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER392_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER392_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER392_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER393 - GICDA_IROUTER393 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER393_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER393_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER393_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER393_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER393_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER393_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER393_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER393_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER393_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER393_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER393_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER393_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER393_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER393_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER393_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER393_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER393_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER393_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER393_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER393_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER393_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER393_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER393_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER393_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER393_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER393_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER393_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER393_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER393_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER393_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER393_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER393_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER393_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER393_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER393_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER394 - GICDA_IROUTER394 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER394_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER394_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER394_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER394_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER394_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER394_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER394_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER394_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER394_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER394_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER394_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER394_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER394_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER394_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER394_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER394_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER394_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER394_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER394_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER394_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER394_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER394_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER394_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER394_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER394_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER394_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER394_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER394_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER394_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER394_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER394_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER394_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER394_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER394_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER394_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER395 - GICDA_IROUTER395 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER395_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER395_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER395_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER395_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER395_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER395_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER395_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER395_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER395_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER395_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER395_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER395_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER395_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER395_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER395_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER395_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER395_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER395_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER395_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER395_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER395_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER395_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER395_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER395_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER395_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER395_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER395_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER395_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER395_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER395_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER395_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER395_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER395_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER395_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER395_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER396 - GICDA_IROUTER396 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER396_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER396_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER396_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER396_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER396_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER396_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER396_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER396_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER396_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER396_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER396_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER396_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER396_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER396_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER396_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER396_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER396_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER396_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER396_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER396_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER396_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER396_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER396_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER396_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER396_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER396_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER396_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER396_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER396_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER396_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER396_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER396_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER396_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER396_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER396_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER397 - GICDA_IROUTER397 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER397_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER397_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER397_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER397_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER397_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER397_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER397_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER397_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER397_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER397_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER397_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER397_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER397_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER397_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER397_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER397_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER397_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER397_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER397_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER397_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER397_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER397_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER397_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER397_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER397_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER397_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER397_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER397_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER397_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER397_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER397_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER397_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER397_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER397_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER397_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER398 - GICDA_IROUTER398 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER398_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER398_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER398_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER398_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER398_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER398_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER398_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER398_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER398_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER398_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER398_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER398_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER398_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER398_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER398_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER398_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER398_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER398_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER398_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER398_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER398_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER398_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER398_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER398_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER398_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER398_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER398_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER398_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER398_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER398_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER398_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER398_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER398_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER398_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER398_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER399 - GICDA_IROUTER399 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER399_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER399_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER399_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER399_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER399_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER399_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER399_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER399_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER399_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER399_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER399_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER399_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER399_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER399_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER399_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER399_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER399_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER399_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER399_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER399_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER399_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER399_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER399_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER399_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER399_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER399_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER399_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER399_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER399_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER399_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER399_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER399_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER399_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER399_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER399_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER400 - GICDA_IROUTER400 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER400_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER400_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER400_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER400_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER400_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER400_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER400_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER400_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER400_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER400_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER400_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER400_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER400_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER400_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER400_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER400_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER400_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER400_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER400_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER400_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER400_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER400_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER400_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER400_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER400_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER400_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER400_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER400_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER400_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER400_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER400_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER400_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER400_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER400_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER400_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER401 - GICDA_IROUTER401 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER401_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER401_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER401_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER401_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER401_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER401_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER401_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER401_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER401_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER401_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER401_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER401_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER401_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER401_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER401_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER401_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER401_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER401_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER401_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER401_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER401_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER401_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER401_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER401_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER401_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER401_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER401_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER401_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER401_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER401_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER401_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER401_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER401_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER401_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER401_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER402 - GICDA_IROUTER402 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER402_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER402_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER402_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER402_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER402_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER402_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER402_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER402_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER402_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER402_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER402_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER402_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER402_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER402_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER402_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER402_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER402_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER402_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER402_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER402_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER402_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER402_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER402_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER402_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER402_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER402_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER402_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER402_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER402_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER402_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER402_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER402_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER402_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER402_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER402_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER403 - GICDA_IROUTER403 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER403_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER403_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER403_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER403_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER403_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER403_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER403_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER403_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER403_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER403_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER403_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER403_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER403_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER403_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER403_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER403_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER403_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER403_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER403_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER403_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER403_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER403_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER403_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER403_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER403_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER403_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER403_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER403_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER403_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER403_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER403_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER403_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER403_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER403_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER403_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER404 - GICDA_IROUTER404 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER404_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER404_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER404_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER404_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER404_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER404_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER404_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER404_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER404_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER404_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER404_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER404_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER404_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER404_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER404_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER404_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER404_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER404_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER404_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER404_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER404_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER404_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER404_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER404_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER404_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER404_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER404_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER404_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER404_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER404_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER404_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER404_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER404_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER404_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER404_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER405 - GICDA_IROUTER405 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER405_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER405_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER405_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER405_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER405_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER405_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER405_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER405_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER405_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER405_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER405_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER405_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER405_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER405_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER405_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER405_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER405_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER405_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER405_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER405_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER405_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER405_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER405_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER405_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER405_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER405_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER405_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER405_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER405_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER405_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER405_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER405_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER405_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER405_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER405_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER406 - GICDA_IROUTER406 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER406_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER406_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER406_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER406_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER406_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER406_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER406_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER406_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER406_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER406_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER406_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER406_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER406_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER406_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER406_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER406_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER406_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER406_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER406_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER406_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER406_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER406_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER406_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER406_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER406_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER406_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER406_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER406_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER406_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER406_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER406_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER406_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER406_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER406_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER406_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER407 - GICDA_IROUTER407 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER407_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER407_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER407_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER407_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER407_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER407_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER407_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER407_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER407_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER407_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER407_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER407_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER407_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER407_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER407_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER407_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER407_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER407_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER407_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER407_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER407_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER407_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER407_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER407_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER407_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER407_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER407_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER407_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER407_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER407_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER407_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER407_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER407_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER407_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER407_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER408 - GICDA_IROUTER408 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER408_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER408_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER408_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER408_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER408_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER408_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER408_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER408_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER408_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER408_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER408_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER408_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER408_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER408_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER408_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER408_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER408_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER408_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER408_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER408_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER408_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER408_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER408_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER408_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER408_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER408_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER408_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER408_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER408_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER408_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER408_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER408_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER408_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER408_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER408_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER409 - GICDA_IROUTER409 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER409_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER409_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER409_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER409_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER409_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER409_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER409_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER409_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER409_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER409_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER409_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER409_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER409_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER409_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER409_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER409_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER409_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER409_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER409_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER409_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER409_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER409_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER409_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER409_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER409_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER409_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER409_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER409_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER409_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER409_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER409_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER409_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER409_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER409_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER409_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER410 - GICDA_IROUTER410 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER410_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER410_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER410_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER410_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER410_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER410_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER410_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER410_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER410_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER410_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER410_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER410_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER410_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER410_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER410_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER410_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER410_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER410_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER410_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER410_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER410_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER410_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER410_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER410_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER410_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER410_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER410_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER410_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER410_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER410_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER410_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER410_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER410_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER410_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER410_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER411 - GICDA_IROUTER411 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER411_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER411_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER411_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER411_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER411_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER411_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER411_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER411_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER411_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER411_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER411_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER411_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER411_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER411_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER411_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER411_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER411_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER411_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER411_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER411_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER411_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER411_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER411_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER411_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER411_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER411_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER411_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER411_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER411_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER411_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER411_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER411_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER411_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER411_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER411_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER412 - GICDA_IROUTER412 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER412_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER412_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER412_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER412_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER412_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER412_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER412_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER412_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER412_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER412_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER412_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER412_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER412_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER412_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER412_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER412_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER412_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER412_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER412_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER412_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER412_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER412_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER412_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER412_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER412_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER412_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER412_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER412_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER412_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER412_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER412_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER412_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER412_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER412_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER412_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER413 - GICDA_IROUTER413 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER413_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER413_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER413_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER413_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER413_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER413_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER413_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER413_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER413_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER413_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER413_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER413_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER413_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER413_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER413_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER413_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER413_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER413_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER413_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER413_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER413_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER413_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER413_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER413_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER413_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER413_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER413_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER413_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER413_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER413_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER413_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER413_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER413_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER413_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER413_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER414 - GICDA_IROUTER414 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER414_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER414_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER414_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER414_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER414_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER414_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER414_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER414_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER414_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER414_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER414_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER414_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER414_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER414_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER414_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER414_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER414_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER414_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER414_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER414_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER414_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER414_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER414_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER414_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER414_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER414_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER414_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER414_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER414_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER414_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER414_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER414_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER414_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER414_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER414_RESERVED1_MASK) /*! @} */ /*! @name GICDA_IROUTER415 - GICDA_IROUTER415 */ /*! @{ */ #define NOC_GICDA_GICDA_IROUTER415_Affinity0_MASK (0xFFU) #define NOC_GICDA_GICDA_IROUTER415_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICDA_GICDA_IROUTER415_Affinity0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER415_Affinity0_SHIFT)) & NOC_GICDA_GICDA_IROUTER415_Affinity0_MASK) #define NOC_GICDA_GICDA_IROUTER415_Affinity1_MASK (0xFF00U) #define NOC_GICDA_GICDA_IROUTER415_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 * 0b00000000.. * 0b00000001.. * 0b00000010.. * 0b00000011.. * 0b00000100.. * 0b00000101.. * 0b00000110.. * 0b00000111.. */ #define NOC_GICDA_GICDA_IROUTER415_Affinity1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER415_Affinity1_SHIFT)) & NOC_GICDA_GICDA_IROUTER415_Affinity1_MASK) #define NOC_GICDA_GICDA_IROUTER415_Affinity2_MASK (0xFF0000U) #define NOC_GICDA_GICDA_IROUTER415_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICDA_GICDA_IROUTER415_Affinity2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER415_Affinity2_SHIFT)) & NOC_GICDA_GICDA_IROUTER415_Affinity2_MASK) #define NOC_GICDA_GICDA_IROUTER415_RESERVED0_MASK (0x7F000000U) #define NOC_GICDA_GICDA_IROUTER415_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_IROUTER415_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER415_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_IROUTER415_RESERVED0_MASK) #define NOC_GICDA_GICDA_IROUTER415_InterruptRoutingMode_MASK (0x80000000U) #define NOC_GICDA_GICDA_IROUTER415_InterruptRoutingMode_SHIFT (31U) /*! InterruptRoutingMode - InterruptRoutingMode */ #define NOC_GICDA_GICDA_IROUTER415_InterruptRoutingMode(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER415_InterruptRoutingMode_SHIFT)) & NOC_GICDA_GICDA_IROUTER415_InterruptRoutingMode_MASK) #define NOC_GICDA_GICDA_IROUTER415_Affinity3_MASK (0xFF00000000U) #define NOC_GICDA_GICDA_IROUTER415_Affinity3_SHIFT (32U) /*! Affinity3 - Affinity3 */ #define NOC_GICDA_GICDA_IROUTER415_Affinity3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER415_Affinity3_SHIFT)) & NOC_GICDA_GICDA_IROUTER415_Affinity3_MASK) #define NOC_GICDA_GICDA_IROUTER415_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GICDA_GICDA_IROUTER415_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_IROUTER415_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_IROUTER415_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_IROUTER415_RESERVED1_MASK) /*! @} */ /*! @name GICDA_RDOFFR0 - GICDA_RDOFFR0 */ /*! @{ */ #define NOC_GICDA_GICDA_RDOFFR0_RD_OFF_MASK (0x3FU) #define NOC_GICDA_GICDA_RDOFFR0_RD_OFF_SHIFT (0U) /*! RD_OFF - RD_OFF */ #define NOC_GICDA_GICDA_RDOFFR0_RD_OFF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_RDOFFR0_RD_OFF_SHIFT)) & NOC_GICDA_GICDA_RDOFFR0_RD_OFF_MASK) #define NOC_GICDA_GICDA_RDOFFR0_RESERVED0_MASK (0xFFFFFFFFFFFFFFC0U) #define NOC_GICDA_GICDA_RDOFFR0_RESERVED0_SHIFT (6U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_RDOFFR0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_RDOFFR0_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_RDOFFR0_RESERVED0_MASK) /*! @} */ /*! @name GICDA_ICLAR2 - GICDA_ICLAR2 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR2_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR2_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR2_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR2_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR2_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR2_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR2_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR2_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR2_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR2_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR2_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR2_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR2_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR2_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR2_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR2_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR2_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR2_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR2_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR2_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR2_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR2_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR2_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR2_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR2_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR2_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR2_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR2_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR2_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR2_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR2_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR2_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR2_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR2_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR2_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR2_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR3 - GICDA_ICLAR3 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR3_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR3_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR3_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR3_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR3_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR3_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR3_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR3_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR3_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR3_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR3_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR3_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR3_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR3_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR3_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR3_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR3_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR3_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR3_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR3_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR3_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR3_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR3_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR3_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR3_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR3_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR3_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR3_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR3_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR3_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR3_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR3_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR3_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR3_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR3_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR3_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR4 - GICDA_ICLAR4 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR4_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR4_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR4_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR4_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR4_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR4_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR4_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR4_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR4_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR4_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR4_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR4_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR4_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR4_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR4_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR4_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR4_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR4_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR4_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR4_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR4_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR4_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR4_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR4_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR4_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR4_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR4_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR4_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR4_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR4_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR4_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR4_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR4_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR4_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR4_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR4_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR5 - GICDA_ICLAR5 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR5_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR5_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR5_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR5_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR5_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR5_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR5_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR5_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR5_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR5_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR5_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR5_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR5_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR5_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR5_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR5_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR5_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR5_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR5_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR5_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR5_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR5_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR5_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR5_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR5_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR5_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR5_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR5_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR5_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR5_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR5_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR5_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR5_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR5_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR5_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR5_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR6 - GICDA_ICLAR6 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR6_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR6_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR6_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR6_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR6_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR6_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR6_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR6_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR6_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR6_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR6_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR6_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR6_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR6_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR6_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR6_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR6_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR6_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR6_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR6_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR6_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR6_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR6_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR6_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR6_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR6_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR6_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR6_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR6_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR6_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR6_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR6_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR6_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR6_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR6_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR6_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR7 - GICDA_ICLAR7 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR7_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR7_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR7_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR7_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR7_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR7_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR7_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR7_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR7_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR7_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR7_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR7_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR7_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR7_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR7_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR7_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR7_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR7_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR7_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR7_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR7_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR7_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR7_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR7_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR7_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR7_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR7_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR7_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR7_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR7_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR7_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR7_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR7_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR7_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR7_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR7_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR8 - GICDA_ICLAR8 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR8_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR8_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR8_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR8_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR8_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR8_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR8_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR8_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR8_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR8_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR8_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR8_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR8_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR8_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR8_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR8_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR8_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR8_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR8_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR8_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR8_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR8_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR8_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR8_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR8_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR8_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR8_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR8_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR8_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR8_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR8_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR8_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR8_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR8_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR8_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR8_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR9 - GICDA_ICLAR9 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR9_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR9_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR9_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR9_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR9_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR9_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR9_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR9_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR9_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR9_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR9_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR9_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR9_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR9_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR9_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR9_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR9_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR9_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR9_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR9_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR9_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR9_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR9_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR9_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR9_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR9_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR9_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR9_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR9_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR9_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR9_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR9_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR9_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR9_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR9_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR9_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR10 - GICDA_ICLAR10 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR10_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR10_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR10_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR10_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR10_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR10_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR10_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR10_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR10_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR10_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR10_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR10_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR10_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR10_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR10_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR10_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR10_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR10_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR10_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR10_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR10_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR10_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR10_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR10_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR10_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR10_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR10_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR10_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR10_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR10_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR10_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR10_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR10_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR10_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR10_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR10_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR11 - GICDA_ICLAR11 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR11_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR11_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR11_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR11_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR11_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR11_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR11_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR11_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR11_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR11_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR11_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR11_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR11_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR11_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR11_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR11_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR11_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR11_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR11_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR11_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR11_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR11_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR11_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR11_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR11_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR11_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR11_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR11_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR11_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR11_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR11_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR11_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR11_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR11_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR11_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR11_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR12 - GICDA_ICLAR12 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR12_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR12_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR12_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR12_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR12_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR12_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR12_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR12_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR12_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR12_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR12_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR12_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR12_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR12_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR12_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR12_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR12_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR12_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR12_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR12_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR12_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR12_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR12_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR12_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR12_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR12_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR12_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR12_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR12_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR12_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR12_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR12_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR12_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR12_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR12_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR12_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR13 - GICDA_ICLAR13 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR13_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR13_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR13_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR13_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR13_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR13_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR13_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR13_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR13_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR13_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR13_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR13_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR13_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR13_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR13_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR13_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR13_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR13_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR13_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR13_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR13_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR13_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR13_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR13_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR13_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR13_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR13_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR13_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR13_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR13_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR13_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR13_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR13_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR13_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR13_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR13_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR14 - GICDA_ICLAR14 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR14_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR14_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR14_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR14_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR14_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR14_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR14_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR14_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR14_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR14_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR14_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR14_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR14_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR14_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR14_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR14_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR14_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR14_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR14_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR14_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR14_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR14_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR14_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR14_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR14_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR14_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR14_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR14_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR14_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR14_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR14_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR14_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR14_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR14_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR14_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR14_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR15 - GICDA_ICLAR15 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR15_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR15_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR15_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR15_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR15_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR15_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR15_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR15_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR15_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR15_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR15_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR15_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR15_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR15_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR15_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR15_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR15_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR15_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR15_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR15_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR15_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR15_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR15_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR15_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR15_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR15_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR15_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR15_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR15_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR15_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR15_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR15_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR15_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR15_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR15_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR15_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR16 - GICDA_ICLAR16 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR16_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR16_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR16_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR16_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR16_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR16_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR16_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR16_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR16_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR16_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR16_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR16_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR16_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR16_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR16_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR16_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR16_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR16_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR16_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR16_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR16_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR16_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR16_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR16_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR16_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR16_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR16_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR16_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR16_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR16_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR16_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR16_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR16_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR16_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR16_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR16_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR17 - GICDA_ICLAR17 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR17_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR17_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR17_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR17_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR17_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR17_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR17_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR17_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR17_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR17_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR17_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR17_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR17_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR17_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR17_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR17_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR17_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR17_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR17_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR17_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR17_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR17_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR17_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR17_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR17_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR17_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR17_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR17_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR17_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR17_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR17_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR17_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR17_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR17_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR17_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR17_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR18 - GICDA_ICLAR18 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR18_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR18_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR18_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR18_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR18_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR18_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR18_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR18_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR18_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR18_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR18_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR18_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR18_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR18_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR18_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR18_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR18_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR18_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR18_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR18_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR18_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR18_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR18_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR18_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR18_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR18_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR18_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR18_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR18_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR18_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR18_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR18_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR18_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR18_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR18_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR18_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR19 - GICDA_ICLAR19 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR19_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR19_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR19_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR19_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR19_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR19_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR19_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR19_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR19_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR19_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR19_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR19_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR19_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR19_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR19_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR19_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR19_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR19_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR19_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR19_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR19_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR19_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR19_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR19_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR19_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR19_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR19_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR19_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR19_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR19_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR19_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR19_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR19_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR19_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR19_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR19_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR20 - GICDA_ICLAR20 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR20_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR20_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR20_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR20_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR20_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR20_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR20_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR20_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR20_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR20_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR20_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR20_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR20_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR20_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR20_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR20_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR20_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR20_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR20_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR20_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR20_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR20_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR20_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR20_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR20_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR20_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR20_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR20_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR20_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR20_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR20_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR20_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR20_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR20_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR20_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR20_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR21 - GICDA_ICLAR21 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR21_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR21_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR21_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR21_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR21_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR21_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR21_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR21_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR21_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR21_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR21_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR21_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR21_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR21_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR21_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR21_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR21_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR21_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR21_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR21_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR21_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR21_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR21_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR21_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR21_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR21_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR21_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR21_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR21_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR21_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR21_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR21_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR21_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR21_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR21_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR21_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR22 - GICDA_ICLAR22 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR22_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR22_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR22_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR22_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR22_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR22_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR22_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR22_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR22_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR22_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR22_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR22_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR22_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR22_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR22_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR22_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR22_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR22_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR22_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR22_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR22_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR22_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR22_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR22_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR22_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR22_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR22_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR22_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR22_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR22_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR22_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR22_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR22_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR22_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR22_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR22_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR23 - GICDA_ICLAR23 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR23_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR23_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR23_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR23_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR23_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR23_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR23_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR23_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR23_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR23_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR23_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR23_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR23_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR23_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR23_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR23_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR23_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR23_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR23_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR23_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR23_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR23_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR23_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR23_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR23_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR23_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR23_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR23_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR23_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR23_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR23_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR23_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR23_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR23_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR23_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR23_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR24 - GICDA_ICLAR24 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR24_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR24_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR24_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR24_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR24_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR24_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR24_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR24_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR24_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR24_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR24_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR24_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR24_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR24_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR24_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR24_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR24_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR24_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR24_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR24_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR24_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR24_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR24_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR24_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR24_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR24_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR24_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR24_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR24_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR24_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR24_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR24_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR24_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR24_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR24_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR24_classes15_MASK) /*! @} */ /*! @name GICDA_ICLAR25 - GICDA_ICLAR25 */ /*! @{ */ #define NOC_GICDA_GICDA_ICLAR25_classes0_MASK (0x3U) #define NOC_GICDA_GICDA_ICLAR25_classes0_SHIFT (0U) /*! classes0 - classes0 */ #define NOC_GICDA_GICDA_ICLAR25_classes0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes0_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes0_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes1_MASK (0xCU) #define NOC_GICDA_GICDA_ICLAR25_classes1_SHIFT (2U) /*! classes1 - classes1 */ #define NOC_GICDA_GICDA_ICLAR25_classes1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes1_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes1_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes2_MASK (0x30U) #define NOC_GICDA_GICDA_ICLAR25_classes2_SHIFT (4U) /*! classes2 - classes2 */ #define NOC_GICDA_GICDA_ICLAR25_classes2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes2_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes2_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes3_MASK (0xC0U) #define NOC_GICDA_GICDA_ICLAR25_classes3_SHIFT (6U) /*! classes3 - classes3 */ #define NOC_GICDA_GICDA_ICLAR25_classes3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes3_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes3_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes4_MASK (0x300U) #define NOC_GICDA_GICDA_ICLAR25_classes4_SHIFT (8U) /*! classes4 - classes4 */ #define NOC_GICDA_GICDA_ICLAR25_classes4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes4_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes4_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes5_MASK (0xC00U) #define NOC_GICDA_GICDA_ICLAR25_classes5_SHIFT (10U) /*! classes5 - classes5 */ #define NOC_GICDA_GICDA_ICLAR25_classes5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes5_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes5_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes6_MASK (0x3000U) #define NOC_GICDA_GICDA_ICLAR25_classes6_SHIFT (12U) /*! classes6 - classes6 */ #define NOC_GICDA_GICDA_ICLAR25_classes6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes6_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes6_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes7_MASK (0xC000U) #define NOC_GICDA_GICDA_ICLAR25_classes7_SHIFT (14U) /*! classes7 - classes7 */ #define NOC_GICDA_GICDA_ICLAR25_classes7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes7_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes7_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes8_MASK (0x30000U) #define NOC_GICDA_GICDA_ICLAR25_classes8_SHIFT (16U) /*! classes8 - classes8 */ #define NOC_GICDA_GICDA_ICLAR25_classes8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes8_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes8_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes9_MASK (0xC0000U) #define NOC_GICDA_GICDA_ICLAR25_classes9_SHIFT (18U) /*! classes9 - classes9 */ #define NOC_GICDA_GICDA_ICLAR25_classes9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes9_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes9_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes10_MASK (0x300000U) #define NOC_GICDA_GICDA_ICLAR25_classes10_SHIFT (20U) /*! classes10 - classes10 */ #define NOC_GICDA_GICDA_ICLAR25_classes10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes10_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes10_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes11_MASK (0xC00000U) #define NOC_GICDA_GICDA_ICLAR25_classes11_SHIFT (22U) /*! classes11 - classes11 */ #define NOC_GICDA_GICDA_ICLAR25_classes11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes11_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes11_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes12_MASK (0x3000000U) #define NOC_GICDA_GICDA_ICLAR25_classes12_SHIFT (24U) /*! classes12 - classes12 */ #define NOC_GICDA_GICDA_ICLAR25_classes12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes12_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes12_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes13_MASK (0xC000000U) #define NOC_GICDA_GICDA_ICLAR25_classes13_SHIFT (26U) /*! classes13 - classes13 */ #define NOC_GICDA_GICDA_ICLAR25_classes13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes13_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes13_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes14_MASK (0x30000000U) #define NOC_GICDA_GICDA_ICLAR25_classes14_SHIFT (28U) /*! classes14 - classes14 */ #define NOC_GICDA_GICDA_ICLAR25_classes14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes14_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes14_MASK) #define NOC_GICDA_GICDA_ICLAR25_classes15_MASK (0xC0000000U) #define NOC_GICDA_GICDA_ICLAR25_classes15_SHIFT (30U) /*! classes15 - classes15 */ #define NOC_GICDA_GICDA_ICLAR25_classes15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICLAR25_classes15_SHIFT)) & NOC_GICDA_GICDA_ICLAR25_classes15_MASK) /*! @} */ /*! @name GICDA_ICERRR1 - GICDA_ICERRR1 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR1_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR1_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR1_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status0_MASK) #define NOC_GICDA_GICDA_ICERRR1_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR1_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR1_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status1_MASK) #define NOC_GICDA_GICDA_ICERRR1_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR1_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR1_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status2_MASK) #define NOC_GICDA_GICDA_ICERRR1_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR1_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR1_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status3_MASK) #define NOC_GICDA_GICDA_ICERRR1_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR1_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR1_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status4_MASK) #define NOC_GICDA_GICDA_ICERRR1_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR1_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR1_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status5_MASK) #define NOC_GICDA_GICDA_ICERRR1_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR1_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR1_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status6_MASK) #define NOC_GICDA_GICDA_ICERRR1_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR1_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR1_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status7_MASK) #define NOC_GICDA_GICDA_ICERRR1_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR1_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR1_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status8_MASK) #define NOC_GICDA_GICDA_ICERRR1_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR1_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR1_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status9_MASK) #define NOC_GICDA_GICDA_ICERRR1_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR1_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR1_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status10_MASK) #define NOC_GICDA_GICDA_ICERRR1_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR1_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR1_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status11_MASK) #define NOC_GICDA_GICDA_ICERRR1_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR1_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR1_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status12_MASK) #define NOC_GICDA_GICDA_ICERRR1_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR1_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR1_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status13_MASK) #define NOC_GICDA_GICDA_ICERRR1_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR1_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR1_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status14_MASK) #define NOC_GICDA_GICDA_ICERRR1_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR1_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR1_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status15_MASK) #define NOC_GICDA_GICDA_ICERRR1_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR1_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR1_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status16_MASK) #define NOC_GICDA_GICDA_ICERRR1_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR1_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR1_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status17_MASK) #define NOC_GICDA_GICDA_ICERRR1_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR1_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR1_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status18_MASK) #define NOC_GICDA_GICDA_ICERRR1_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR1_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR1_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status19_MASK) #define NOC_GICDA_GICDA_ICERRR1_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR1_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR1_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status20_MASK) #define NOC_GICDA_GICDA_ICERRR1_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR1_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR1_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status21_MASK) #define NOC_GICDA_GICDA_ICERRR1_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR1_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR1_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status22_MASK) #define NOC_GICDA_GICDA_ICERRR1_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR1_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR1_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status23_MASK) #define NOC_GICDA_GICDA_ICERRR1_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR1_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR1_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status24_MASK) #define NOC_GICDA_GICDA_ICERRR1_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR1_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR1_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status25_MASK) #define NOC_GICDA_GICDA_ICERRR1_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR1_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR1_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status26_MASK) #define NOC_GICDA_GICDA_ICERRR1_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR1_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR1_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status27_MASK) #define NOC_GICDA_GICDA_ICERRR1_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR1_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR1_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status28_MASK) #define NOC_GICDA_GICDA_ICERRR1_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR1_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR1_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status29_MASK) #define NOC_GICDA_GICDA_ICERRR1_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR1_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR1_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status30_MASK) #define NOC_GICDA_GICDA_ICERRR1_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR1_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR1_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR1_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR1_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR2 - GICDA_ICERRR2 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR2_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR2_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR2_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status0_MASK) #define NOC_GICDA_GICDA_ICERRR2_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR2_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR2_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status1_MASK) #define NOC_GICDA_GICDA_ICERRR2_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR2_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR2_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status2_MASK) #define NOC_GICDA_GICDA_ICERRR2_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR2_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR2_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status3_MASK) #define NOC_GICDA_GICDA_ICERRR2_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR2_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR2_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status4_MASK) #define NOC_GICDA_GICDA_ICERRR2_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR2_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR2_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status5_MASK) #define NOC_GICDA_GICDA_ICERRR2_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR2_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR2_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status6_MASK) #define NOC_GICDA_GICDA_ICERRR2_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR2_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR2_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status7_MASK) #define NOC_GICDA_GICDA_ICERRR2_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR2_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR2_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status8_MASK) #define NOC_GICDA_GICDA_ICERRR2_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR2_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR2_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status9_MASK) #define NOC_GICDA_GICDA_ICERRR2_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR2_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR2_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status10_MASK) #define NOC_GICDA_GICDA_ICERRR2_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR2_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR2_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status11_MASK) #define NOC_GICDA_GICDA_ICERRR2_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR2_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR2_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status12_MASK) #define NOC_GICDA_GICDA_ICERRR2_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR2_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR2_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status13_MASK) #define NOC_GICDA_GICDA_ICERRR2_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR2_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR2_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status14_MASK) #define NOC_GICDA_GICDA_ICERRR2_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR2_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR2_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status15_MASK) #define NOC_GICDA_GICDA_ICERRR2_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR2_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR2_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status16_MASK) #define NOC_GICDA_GICDA_ICERRR2_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR2_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR2_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status17_MASK) #define NOC_GICDA_GICDA_ICERRR2_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR2_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR2_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status18_MASK) #define NOC_GICDA_GICDA_ICERRR2_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR2_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR2_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status19_MASK) #define NOC_GICDA_GICDA_ICERRR2_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR2_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR2_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status20_MASK) #define NOC_GICDA_GICDA_ICERRR2_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR2_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR2_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status21_MASK) #define NOC_GICDA_GICDA_ICERRR2_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR2_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR2_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status22_MASK) #define NOC_GICDA_GICDA_ICERRR2_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR2_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR2_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status23_MASK) #define NOC_GICDA_GICDA_ICERRR2_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR2_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR2_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status24_MASK) #define NOC_GICDA_GICDA_ICERRR2_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR2_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR2_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status25_MASK) #define NOC_GICDA_GICDA_ICERRR2_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR2_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR2_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status26_MASK) #define NOC_GICDA_GICDA_ICERRR2_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR2_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR2_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status27_MASK) #define NOC_GICDA_GICDA_ICERRR2_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR2_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR2_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status28_MASK) #define NOC_GICDA_GICDA_ICERRR2_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR2_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR2_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status29_MASK) #define NOC_GICDA_GICDA_ICERRR2_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR2_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR2_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status30_MASK) #define NOC_GICDA_GICDA_ICERRR2_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR2_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR2_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR2_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR2_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR3 - GICDA_ICERRR3 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR3_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR3_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR3_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status0_MASK) #define NOC_GICDA_GICDA_ICERRR3_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR3_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR3_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status1_MASK) #define NOC_GICDA_GICDA_ICERRR3_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR3_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR3_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status2_MASK) #define NOC_GICDA_GICDA_ICERRR3_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR3_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR3_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status3_MASK) #define NOC_GICDA_GICDA_ICERRR3_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR3_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR3_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status4_MASK) #define NOC_GICDA_GICDA_ICERRR3_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR3_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR3_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status5_MASK) #define NOC_GICDA_GICDA_ICERRR3_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR3_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR3_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status6_MASK) #define NOC_GICDA_GICDA_ICERRR3_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR3_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR3_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status7_MASK) #define NOC_GICDA_GICDA_ICERRR3_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR3_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR3_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status8_MASK) #define NOC_GICDA_GICDA_ICERRR3_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR3_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR3_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status9_MASK) #define NOC_GICDA_GICDA_ICERRR3_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR3_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR3_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status10_MASK) #define NOC_GICDA_GICDA_ICERRR3_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR3_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR3_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status11_MASK) #define NOC_GICDA_GICDA_ICERRR3_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR3_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR3_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status12_MASK) #define NOC_GICDA_GICDA_ICERRR3_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR3_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR3_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status13_MASK) #define NOC_GICDA_GICDA_ICERRR3_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR3_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR3_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status14_MASK) #define NOC_GICDA_GICDA_ICERRR3_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR3_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR3_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status15_MASK) #define NOC_GICDA_GICDA_ICERRR3_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR3_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR3_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status16_MASK) #define NOC_GICDA_GICDA_ICERRR3_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR3_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR3_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status17_MASK) #define NOC_GICDA_GICDA_ICERRR3_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR3_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR3_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status18_MASK) #define NOC_GICDA_GICDA_ICERRR3_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR3_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR3_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status19_MASK) #define NOC_GICDA_GICDA_ICERRR3_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR3_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR3_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status20_MASK) #define NOC_GICDA_GICDA_ICERRR3_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR3_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR3_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status21_MASK) #define NOC_GICDA_GICDA_ICERRR3_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR3_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR3_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status22_MASK) #define NOC_GICDA_GICDA_ICERRR3_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR3_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR3_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status23_MASK) #define NOC_GICDA_GICDA_ICERRR3_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR3_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR3_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status24_MASK) #define NOC_GICDA_GICDA_ICERRR3_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR3_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR3_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status25_MASK) #define NOC_GICDA_GICDA_ICERRR3_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR3_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR3_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status26_MASK) #define NOC_GICDA_GICDA_ICERRR3_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR3_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR3_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status27_MASK) #define NOC_GICDA_GICDA_ICERRR3_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR3_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR3_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status28_MASK) #define NOC_GICDA_GICDA_ICERRR3_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR3_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR3_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status29_MASK) #define NOC_GICDA_GICDA_ICERRR3_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR3_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR3_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status30_MASK) #define NOC_GICDA_GICDA_ICERRR3_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR3_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR3_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR3_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR3_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR4 - GICDA_ICERRR4 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR4_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR4_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR4_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status0_MASK) #define NOC_GICDA_GICDA_ICERRR4_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR4_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR4_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status1_MASK) #define NOC_GICDA_GICDA_ICERRR4_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR4_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR4_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status2_MASK) #define NOC_GICDA_GICDA_ICERRR4_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR4_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR4_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status3_MASK) #define NOC_GICDA_GICDA_ICERRR4_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR4_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR4_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status4_MASK) #define NOC_GICDA_GICDA_ICERRR4_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR4_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR4_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status5_MASK) #define NOC_GICDA_GICDA_ICERRR4_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR4_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR4_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status6_MASK) #define NOC_GICDA_GICDA_ICERRR4_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR4_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR4_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status7_MASK) #define NOC_GICDA_GICDA_ICERRR4_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR4_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR4_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status8_MASK) #define NOC_GICDA_GICDA_ICERRR4_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR4_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR4_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status9_MASK) #define NOC_GICDA_GICDA_ICERRR4_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR4_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR4_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status10_MASK) #define NOC_GICDA_GICDA_ICERRR4_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR4_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR4_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status11_MASK) #define NOC_GICDA_GICDA_ICERRR4_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR4_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR4_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status12_MASK) #define NOC_GICDA_GICDA_ICERRR4_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR4_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR4_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status13_MASK) #define NOC_GICDA_GICDA_ICERRR4_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR4_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR4_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status14_MASK) #define NOC_GICDA_GICDA_ICERRR4_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR4_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR4_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status15_MASK) #define NOC_GICDA_GICDA_ICERRR4_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR4_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR4_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status16_MASK) #define NOC_GICDA_GICDA_ICERRR4_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR4_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR4_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status17_MASK) #define NOC_GICDA_GICDA_ICERRR4_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR4_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR4_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status18_MASK) #define NOC_GICDA_GICDA_ICERRR4_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR4_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR4_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status19_MASK) #define NOC_GICDA_GICDA_ICERRR4_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR4_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR4_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status20_MASK) #define NOC_GICDA_GICDA_ICERRR4_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR4_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR4_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status21_MASK) #define NOC_GICDA_GICDA_ICERRR4_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR4_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR4_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status22_MASK) #define NOC_GICDA_GICDA_ICERRR4_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR4_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR4_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status23_MASK) #define NOC_GICDA_GICDA_ICERRR4_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR4_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR4_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status24_MASK) #define NOC_GICDA_GICDA_ICERRR4_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR4_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR4_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status25_MASK) #define NOC_GICDA_GICDA_ICERRR4_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR4_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR4_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status26_MASK) #define NOC_GICDA_GICDA_ICERRR4_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR4_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR4_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status27_MASK) #define NOC_GICDA_GICDA_ICERRR4_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR4_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR4_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status28_MASK) #define NOC_GICDA_GICDA_ICERRR4_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR4_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR4_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status29_MASK) #define NOC_GICDA_GICDA_ICERRR4_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR4_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR4_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status30_MASK) #define NOC_GICDA_GICDA_ICERRR4_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR4_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR4_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR4_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR4_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR5 - GICDA_ICERRR5 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR5_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR5_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR5_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status0_MASK) #define NOC_GICDA_GICDA_ICERRR5_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR5_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR5_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status1_MASK) #define NOC_GICDA_GICDA_ICERRR5_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR5_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR5_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status2_MASK) #define NOC_GICDA_GICDA_ICERRR5_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR5_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR5_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status3_MASK) #define NOC_GICDA_GICDA_ICERRR5_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR5_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR5_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status4_MASK) #define NOC_GICDA_GICDA_ICERRR5_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR5_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR5_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status5_MASK) #define NOC_GICDA_GICDA_ICERRR5_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR5_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR5_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status6_MASK) #define NOC_GICDA_GICDA_ICERRR5_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR5_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR5_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status7_MASK) #define NOC_GICDA_GICDA_ICERRR5_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR5_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR5_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status8_MASK) #define NOC_GICDA_GICDA_ICERRR5_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR5_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR5_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status9_MASK) #define NOC_GICDA_GICDA_ICERRR5_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR5_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR5_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status10_MASK) #define NOC_GICDA_GICDA_ICERRR5_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR5_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR5_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status11_MASK) #define NOC_GICDA_GICDA_ICERRR5_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR5_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR5_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status12_MASK) #define NOC_GICDA_GICDA_ICERRR5_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR5_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR5_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status13_MASK) #define NOC_GICDA_GICDA_ICERRR5_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR5_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR5_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status14_MASK) #define NOC_GICDA_GICDA_ICERRR5_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR5_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR5_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status15_MASK) #define NOC_GICDA_GICDA_ICERRR5_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR5_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR5_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status16_MASK) #define NOC_GICDA_GICDA_ICERRR5_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR5_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR5_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status17_MASK) #define NOC_GICDA_GICDA_ICERRR5_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR5_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR5_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status18_MASK) #define NOC_GICDA_GICDA_ICERRR5_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR5_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR5_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status19_MASK) #define NOC_GICDA_GICDA_ICERRR5_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR5_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR5_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status20_MASK) #define NOC_GICDA_GICDA_ICERRR5_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR5_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR5_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status21_MASK) #define NOC_GICDA_GICDA_ICERRR5_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR5_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR5_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status22_MASK) #define NOC_GICDA_GICDA_ICERRR5_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR5_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR5_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status23_MASK) #define NOC_GICDA_GICDA_ICERRR5_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR5_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR5_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status24_MASK) #define NOC_GICDA_GICDA_ICERRR5_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR5_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR5_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status25_MASK) #define NOC_GICDA_GICDA_ICERRR5_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR5_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR5_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status26_MASK) #define NOC_GICDA_GICDA_ICERRR5_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR5_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR5_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status27_MASK) #define NOC_GICDA_GICDA_ICERRR5_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR5_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR5_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status28_MASK) #define NOC_GICDA_GICDA_ICERRR5_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR5_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR5_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status29_MASK) #define NOC_GICDA_GICDA_ICERRR5_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR5_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR5_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status30_MASK) #define NOC_GICDA_GICDA_ICERRR5_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR5_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR5_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR5_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR5_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR6 - GICDA_ICERRR6 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR6_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR6_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR6_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status0_MASK) #define NOC_GICDA_GICDA_ICERRR6_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR6_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR6_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status1_MASK) #define NOC_GICDA_GICDA_ICERRR6_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR6_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR6_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status2_MASK) #define NOC_GICDA_GICDA_ICERRR6_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR6_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR6_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status3_MASK) #define NOC_GICDA_GICDA_ICERRR6_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR6_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR6_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status4_MASK) #define NOC_GICDA_GICDA_ICERRR6_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR6_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR6_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status5_MASK) #define NOC_GICDA_GICDA_ICERRR6_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR6_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR6_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status6_MASK) #define NOC_GICDA_GICDA_ICERRR6_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR6_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR6_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status7_MASK) #define NOC_GICDA_GICDA_ICERRR6_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR6_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR6_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status8_MASK) #define NOC_GICDA_GICDA_ICERRR6_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR6_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR6_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status9_MASK) #define NOC_GICDA_GICDA_ICERRR6_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR6_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR6_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status10_MASK) #define NOC_GICDA_GICDA_ICERRR6_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR6_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR6_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status11_MASK) #define NOC_GICDA_GICDA_ICERRR6_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR6_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR6_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status12_MASK) #define NOC_GICDA_GICDA_ICERRR6_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR6_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR6_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status13_MASK) #define NOC_GICDA_GICDA_ICERRR6_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR6_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR6_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status14_MASK) #define NOC_GICDA_GICDA_ICERRR6_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR6_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR6_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status15_MASK) #define NOC_GICDA_GICDA_ICERRR6_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR6_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR6_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status16_MASK) #define NOC_GICDA_GICDA_ICERRR6_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR6_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR6_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status17_MASK) #define NOC_GICDA_GICDA_ICERRR6_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR6_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR6_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status18_MASK) #define NOC_GICDA_GICDA_ICERRR6_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR6_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR6_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status19_MASK) #define NOC_GICDA_GICDA_ICERRR6_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR6_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR6_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status20_MASK) #define NOC_GICDA_GICDA_ICERRR6_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR6_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR6_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status21_MASK) #define NOC_GICDA_GICDA_ICERRR6_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR6_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR6_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status22_MASK) #define NOC_GICDA_GICDA_ICERRR6_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR6_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR6_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status23_MASK) #define NOC_GICDA_GICDA_ICERRR6_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR6_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR6_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status24_MASK) #define NOC_GICDA_GICDA_ICERRR6_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR6_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR6_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status25_MASK) #define NOC_GICDA_GICDA_ICERRR6_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR6_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR6_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status26_MASK) #define NOC_GICDA_GICDA_ICERRR6_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR6_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR6_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status27_MASK) #define NOC_GICDA_GICDA_ICERRR6_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR6_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR6_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status28_MASK) #define NOC_GICDA_GICDA_ICERRR6_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR6_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR6_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status29_MASK) #define NOC_GICDA_GICDA_ICERRR6_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR6_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR6_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status30_MASK) #define NOC_GICDA_GICDA_ICERRR6_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR6_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR6_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR6_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR6_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR7 - GICDA_ICERRR7 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR7_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR7_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR7_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status0_MASK) #define NOC_GICDA_GICDA_ICERRR7_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR7_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR7_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status1_MASK) #define NOC_GICDA_GICDA_ICERRR7_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR7_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR7_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status2_MASK) #define NOC_GICDA_GICDA_ICERRR7_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR7_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR7_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status3_MASK) #define NOC_GICDA_GICDA_ICERRR7_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR7_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR7_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status4_MASK) #define NOC_GICDA_GICDA_ICERRR7_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR7_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR7_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status5_MASK) #define NOC_GICDA_GICDA_ICERRR7_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR7_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR7_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status6_MASK) #define NOC_GICDA_GICDA_ICERRR7_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR7_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR7_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status7_MASK) #define NOC_GICDA_GICDA_ICERRR7_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR7_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR7_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status8_MASK) #define NOC_GICDA_GICDA_ICERRR7_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR7_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR7_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status9_MASK) #define NOC_GICDA_GICDA_ICERRR7_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR7_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR7_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status10_MASK) #define NOC_GICDA_GICDA_ICERRR7_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR7_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR7_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status11_MASK) #define NOC_GICDA_GICDA_ICERRR7_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR7_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR7_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status12_MASK) #define NOC_GICDA_GICDA_ICERRR7_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR7_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR7_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status13_MASK) #define NOC_GICDA_GICDA_ICERRR7_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR7_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR7_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status14_MASK) #define NOC_GICDA_GICDA_ICERRR7_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR7_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR7_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status15_MASK) #define NOC_GICDA_GICDA_ICERRR7_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR7_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR7_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status16_MASK) #define NOC_GICDA_GICDA_ICERRR7_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR7_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR7_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status17_MASK) #define NOC_GICDA_GICDA_ICERRR7_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR7_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR7_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status18_MASK) #define NOC_GICDA_GICDA_ICERRR7_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR7_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR7_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status19_MASK) #define NOC_GICDA_GICDA_ICERRR7_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR7_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR7_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status20_MASK) #define NOC_GICDA_GICDA_ICERRR7_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR7_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR7_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status21_MASK) #define NOC_GICDA_GICDA_ICERRR7_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR7_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR7_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status22_MASK) #define NOC_GICDA_GICDA_ICERRR7_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR7_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR7_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status23_MASK) #define NOC_GICDA_GICDA_ICERRR7_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR7_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR7_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status24_MASK) #define NOC_GICDA_GICDA_ICERRR7_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR7_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR7_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status25_MASK) #define NOC_GICDA_GICDA_ICERRR7_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR7_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR7_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status26_MASK) #define NOC_GICDA_GICDA_ICERRR7_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR7_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR7_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status27_MASK) #define NOC_GICDA_GICDA_ICERRR7_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR7_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR7_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status28_MASK) #define NOC_GICDA_GICDA_ICERRR7_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR7_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR7_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status29_MASK) #define NOC_GICDA_GICDA_ICERRR7_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR7_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR7_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status30_MASK) #define NOC_GICDA_GICDA_ICERRR7_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR7_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR7_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR7_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR7_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR8 - GICDA_ICERRR8 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR8_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR8_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR8_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status0_MASK) #define NOC_GICDA_GICDA_ICERRR8_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR8_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR8_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status1_MASK) #define NOC_GICDA_GICDA_ICERRR8_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR8_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR8_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status2_MASK) #define NOC_GICDA_GICDA_ICERRR8_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR8_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR8_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status3_MASK) #define NOC_GICDA_GICDA_ICERRR8_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR8_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR8_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status4_MASK) #define NOC_GICDA_GICDA_ICERRR8_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR8_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR8_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status5_MASK) #define NOC_GICDA_GICDA_ICERRR8_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR8_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR8_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status6_MASK) #define NOC_GICDA_GICDA_ICERRR8_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR8_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR8_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status7_MASK) #define NOC_GICDA_GICDA_ICERRR8_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR8_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR8_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status8_MASK) #define NOC_GICDA_GICDA_ICERRR8_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR8_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR8_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status9_MASK) #define NOC_GICDA_GICDA_ICERRR8_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR8_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR8_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status10_MASK) #define NOC_GICDA_GICDA_ICERRR8_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR8_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR8_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status11_MASK) #define NOC_GICDA_GICDA_ICERRR8_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR8_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR8_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status12_MASK) #define NOC_GICDA_GICDA_ICERRR8_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR8_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR8_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status13_MASK) #define NOC_GICDA_GICDA_ICERRR8_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR8_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR8_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status14_MASK) #define NOC_GICDA_GICDA_ICERRR8_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR8_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR8_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status15_MASK) #define NOC_GICDA_GICDA_ICERRR8_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR8_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR8_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status16_MASK) #define NOC_GICDA_GICDA_ICERRR8_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR8_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR8_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status17_MASK) #define NOC_GICDA_GICDA_ICERRR8_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR8_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR8_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status18_MASK) #define NOC_GICDA_GICDA_ICERRR8_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR8_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR8_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status19_MASK) #define NOC_GICDA_GICDA_ICERRR8_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR8_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR8_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status20_MASK) #define NOC_GICDA_GICDA_ICERRR8_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR8_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR8_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status21_MASK) #define NOC_GICDA_GICDA_ICERRR8_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR8_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR8_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status22_MASK) #define NOC_GICDA_GICDA_ICERRR8_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR8_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR8_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status23_MASK) #define NOC_GICDA_GICDA_ICERRR8_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR8_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR8_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status24_MASK) #define NOC_GICDA_GICDA_ICERRR8_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR8_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR8_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status25_MASK) #define NOC_GICDA_GICDA_ICERRR8_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR8_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR8_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status26_MASK) #define NOC_GICDA_GICDA_ICERRR8_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR8_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR8_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status27_MASK) #define NOC_GICDA_GICDA_ICERRR8_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR8_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR8_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status28_MASK) #define NOC_GICDA_GICDA_ICERRR8_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR8_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR8_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status29_MASK) #define NOC_GICDA_GICDA_ICERRR8_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR8_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR8_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status30_MASK) #define NOC_GICDA_GICDA_ICERRR8_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR8_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR8_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR8_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR8_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR9 - GICDA_ICERRR9 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR9_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR9_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR9_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status0_MASK) #define NOC_GICDA_GICDA_ICERRR9_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR9_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR9_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status1_MASK) #define NOC_GICDA_GICDA_ICERRR9_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR9_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR9_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status2_MASK) #define NOC_GICDA_GICDA_ICERRR9_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR9_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR9_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status3_MASK) #define NOC_GICDA_GICDA_ICERRR9_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR9_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR9_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status4_MASK) #define NOC_GICDA_GICDA_ICERRR9_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR9_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR9_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status5_MASK) #define NOC_GICDA_GICDA_ICERRR9_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR9_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR9_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status6_MASK) #define NOC_GICDA_GICDA_ICERRR9_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR9_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR9_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status7_MASK) #define NOC_GICDA_GICDA_ICERRR9_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR9_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR9_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status8_MASK) #define NOC_GICDA_GICDA_ICERRR9_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR9_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR9_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status9_MASK) #define NOC_GICDA_GICDA_ICERRR9_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR9_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR9_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status10_MASK) #define NOC_GICDA_GICDA_ICERRR9_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR9_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR9_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status11_MASK) #define NOC_GICDA_GICDA_ICERRR9_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR9_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR9_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status12_MASK) #define NOC_GICDA_GICDA_ICERRR9_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR9_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR9_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status13_MASK) #define NOC_GICDA_GICDA_ICERRR9_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR9_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR9_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status14_MASK) #define NOC_GICDA_GICDA_ICERRR9_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR9_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR9_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status15_MASK) #define NOC_GICDA_GICDA_ICERRR9_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR9_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR9_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status16_MASK) #define NOC_GICDA_GICDA_ICERRR9_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR9_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR9_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status17_MASK) #define NOC_GICDA_GICDA_ICERRR9_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR9_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR9_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status18_MASK) #define NOC_GICDA_GICDA_ICERRR9_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR9_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR9_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status19_MASK) #define NOC_GICDA_GICDA_ICERRR9_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR9_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR9_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status20_MASK) #define NOC_GICDA_GICDA_ICERRR9_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR9_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR9_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status21_MASK) #define NOC_GICDA_GICDA_ICERRR9_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR9_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR9_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status22_MASK) #define NOC_GICDA_GICDA_ICERRR9_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR9_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR9_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status23_MASK) #define NOC_GICDA_GICDA_ICERRR9_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR9_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR9_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status24_MASK) #define NOC_GICDA_GICDA_ICERRR9_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR9_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR9_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status25_MASK) #define NOC_GICDA_GICDA_ICERRR9_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR9_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR9_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status26_MASK) #define NOC_GICDA_GICDA_ICERRR9_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR9_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR9_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status27_MASK) #define NOC_GICDA_GICDA_ICERRR9_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR9_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR9_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status28_MASK) #define NOC_GICDA_GICDA_ICERRR9_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR9_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR9_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status29_MASK) #define NOC_GICDA_GICDA_ICERRR9_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR9_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR9_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status30_MASK) #define NOC_GICDA_GICDA_ICERRR9_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR9_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR9_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR9_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR9_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR10 - GICDA_ICERRR10 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR10_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR10_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR10_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status0_MASK) #define NOC_GICDA_GICDA_ICERRR10_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR10_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR10_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status1_MASK) #define NOC_GICDA_GICDA_ICERRR10_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR10_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR10_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status2_MASK) #define NOC_GICDA_GICDA_ICERRR10_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR10_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR10_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status3_MASK) #define NOC_GICDA_GICDA_ICERRR10_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR10_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR10_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status4_MASK) #define NOC_GICDA_GICDA_ICERRR10_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR10_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR10_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status5_MASK) #define NOC_GICDA_GICDA_ICERRR10_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR10_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR10_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status6_MASK) #define NOC_GICDA_GICDA_ICERRR10_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR10_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR10_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status7_MASK) #define NOC_GICDA_GICDA_ICERRR10_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR10_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR10_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status8_MASK) #define NOC_GICDA_GICDA_ICERRR10_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR10_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR10_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status9_MASK) #define NOC_GICDA_GICDA_ICERRR10_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR10_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR10_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status10_MASK) #define NOC_GICDA_GICDA_ICERRR10_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR10_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR10_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status11_MASK) #define NOC_GICDA_GICDA_ICERRR10_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR10_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR10_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status12_MASK) #define NOC_GICDA_GICDA_ICERRR10_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR10_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR10_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status13_MASK) #define NOC_GICDA_GICDA_ICERRR10_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR10_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR10_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status14_MASK) #define NOC_GICDA_GICDA_ICERRR10_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR10_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR10_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status15_MASK) #define NOC_GICDA_GICDA_ICERRR10_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR10_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR10_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status16_MASK) #define NOC_GICDA_GICDA_ICERRR10_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR10_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR10_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status17_MASK) #define NOC_GICDA_GICDA_ICERRR10_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR10_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR10_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status18_MASK) #define NOC_GICDA_GICDA_ICERRR10_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR10_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR10_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status19_MASK) #define NOC_GICDA_GICDA_ICERRR10_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR10_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR10_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status20_MASK) #define NOC_GICDA_GICDA_ICERRR10_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR10_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR10_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status21_MASK) #define NOC_GICDA_GICDA_ICERRR10_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR10_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR10_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status22_MASK) #define NOC_GICDA_GICDA_ICERRR10_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR10_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR10_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status23_MASK) #define NOC_GICDA_GICDA_ICERRR10_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR10_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR10_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status24_MASK) #define NOC_GICDA_GICDA_ICERRR10_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR10_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR10_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status25_MASK) #define NOC_GICDA_GICDA_ICERRR10_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR10_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR10_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status26_MASK) #define NOC_GICDA_GICDA_ICERRR10_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR10_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR10_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status27_MASK) #define NOC_GICDA_GICDA_ICERRR10_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR10_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR10_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status28_MASK) #define NOC_GICDA_GICDA_ICERRR10_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR10_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR10_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status29_MASK) #define NOC_GICDA_GICDA_ICERRR10_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR10_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR10_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status30_MASK) #define NOC_GICDA_GICDA_ICERRR10_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR10_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR10_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR10_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR10_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR11 - GICDA_ICERRR11 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR11_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR11_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR11_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status0_MASK) #define NOC_GICDA_GICDA_ICERRR11_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR11_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR11_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status1_MASK) #define NOC_GICDA_GICDA_ICERRR11_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR11_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR11_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status2_MASK) #define NOC_GICDA_GICDA_ICERRR11_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR11_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR11_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status3_MASK) #define NOC_GICDA_GICDA_ICERRR11_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR11_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR11_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status4_MASK) #define NOC_GICDA_GICDA_ICERRR11_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR11_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR11_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status5_MASK) #define NOC_GICDA_GICDA_ICERRR11_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR11_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR11_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status6_MASK) #define NOC_GICDA_GICDA_ICERRR11_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR11_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR11_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status7_MASK) #define NOC_GICDA_GICDA_ICERRR11_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR11_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR11_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status8_MASK) #define NOC_GICDA_GICDA_ICERRR11_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR11_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR11_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status9_MASK) #define NOC_GICDA_GICDA_ICERRR11_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR11_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR11_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status10_MASK) #define NOC_GICDA_GICDA_ICERRR11_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR11_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR11_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status11_MASK) #define NOC_GICDA_GICDA_ICERRR11_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR11_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR11_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status12_MASK) #define NOC_GICDA_GICDA_ICERRR11_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR11_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR11_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status13_MASK) #define NOC_GICDA_GICDA_ICERRR11_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR11_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR11_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status14_MASK) #define NOC_GICDA_GICDA_ICERRR11_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR11_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR11_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status15_MASK) #define NOC_GICDA_GICDA_ICERRR11_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR11_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR11_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status16_MASK) #define NOC_GICDA_GICDA_ICERRR11_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR11_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR11_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status17_MASK) #define NOC_GICDA_GICDA_ICERRR11_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR11_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR11_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status18_MASK) #define NOC_GICDA_GICDA_ICERRR11_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR11_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR11_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status19_MASK) #define NOC_GICDA_GICDA_ICERRR11_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR11_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR11_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status20_MASK) #define NOC_GICDA_GICDA_ICERRR11_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR11_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR11_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status21_MASK) #define NOC_GICDA_GICDA_ICERRR11_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR11_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR11_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status22_MASK) #define NOC_GICDA_GICDA_ICERRR11_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR11_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR11_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status23_MASK) #define NOC_GICDA_GICDA_ICERRR11_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR11_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR11_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status24_MASK) #define NOC_GICDA_GICDA_ICERRR11_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR11_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR11_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status25_MASK) #define NOC_GICDA_GICDA_ICERRR11_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR11_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR11_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status26_MASK) #define NOC_GICDA_GICDA_ICERRR11_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR11_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR11_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status27_MASK) #define NOC_GICDA_GICDA_ICERRR11_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR11_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR11_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status28_MASK) #define NOC_GICDA_GICDA_ICERRR11_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR11_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR11_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status29_MASK) #define NOC_GICDA_GICDA_ICERRR11_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR11_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR11_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status30_MASK) #define NOC_GICDA_GICDA_ICERRR11_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR11_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR11_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR11_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR11_status31_MASK) /*! @} */ /*! @name GICDA_ICERRR12 - GICDA_ICERRR12 */ /*! @{ */ #define NOC_GICDA_GICDA_ICERRR12_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICERRR12_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICERRR12_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status0_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status0_MASK) #define NOC_GICDA_GICDA_ICERRR12_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICERRR12_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICERRR12_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status1_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status1_MASK) #define NOC_GICDA_GICDA_ICERRR12_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICERRR12_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICERRR12_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status2_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status2_MASK) #define NOC_GICDA_GICDA_ICERRR12_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICERRR12_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICERRR12_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status3_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status3_MASK) #define NOC_GICDA_GICDA_ICERRR12_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICERRR12_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICERRR12_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status4_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status4_MASK) #define NOC_GICDA_GICDA_ICERRR12_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICERRR12_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICERRR12_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status5_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status5_MASK) #define NOC_GICDA_GICDA_ICERRR12_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICERRR12_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICERRR12_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status6_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status6_MASK) #define NOC_GICDA_GICDA_ICERRR12_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICERRR12_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICERRR12_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status7_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status7_MASK) #define NOC_GICDA_GICDA_ICERRR12_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICERRR12_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICERRR12_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status8_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status8_MASK) #define NOC_GICDA_GICDA_ICERRR12_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICERRR12_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICERRR12_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status9_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status9_MASK) #define NOC_GICDA_GICDA_ICERRR12_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICERRR12_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICERRR12_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status10_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status10_MASK) #define NOC_GICDA_GICDA_ICERRR12_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICERRR12_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICERRR12_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status11_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status11_MASK) #define NOC_GICDA_GICDA_ICERRR12_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICERRR12_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICERRR12_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status12_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status12_MASK) #define NOC_GICDA_GICDA_ICERRR12_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICERRR12_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICERRR12_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status13_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status13_MASK) #define NOC_GICDA_GICDA_ICERRR12_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICERRR12_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICERRR12_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status14_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status14_MASK) #define NOC_GICDA_GICDA_ICERRR12_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICERRR12_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICERRR12_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status15_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status15_MASK) #define NOC_GICDA_GICDA_ICERRR12_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICERRR12_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICERRR12_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status16_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status16_MASK) #define NOC_GICDA_GICDA_ICERRR12_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICERRR12_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICERRR12_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status17_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status17_MASK) #define NOC_GICDA_GICDA_ICERRR12_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICERRR12_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICERRR12_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status18_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status18_MASK) #define NOC_GICDA_GICDA_ICERRR12_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICERRR12_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICERRR12_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status19_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status19_MASK) #define NOC_GICDA_GICDA_ICERRR12_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICERRR12_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICERRR12_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status20_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status20_MASK) #define NOC_GICDA_GICDA_ICERRR12_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICERRR12_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICERRR12_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status21_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status21_MASK) #define NOC_GICDA_GICDA_ICERRR12_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICERRR12_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICERRR12_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status22_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status22_MASK) #define NOC_GICDA_GICDA_ICERRR12_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICERRR12_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICERRR12_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status23_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status23_MASK) #define NOC_GICDA_GICDA_ICERRR12_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICERRR12_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICERRR12_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status24_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status24_MASK) #define NOC_GICDA_GICDA_ICERRR12_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICERRR12_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICERRR12_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status25_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status25_MASK) #define NOC_GICDA_GICDA_ICERRR12_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICERRR12_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICERRR12_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status26_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status26_MASK) #define NOC_GICDA_GICDA_ICERRR12_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICERRR12_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICERRR12_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status27_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status27_MASK) #define NOC_GICDA_GICDA_ICERRR12_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICERRR12_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICERRR12_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status28_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status28_MASK) #define NOC_GICDA_GICDA_ICERRR12_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICERRR12_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICERRR12_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status29_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status29_MASK) #define NOC_GICDA_GICDA_ICERRR12_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICERRR12_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICERRR12_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status30_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status30_MASK) #define NOC_GICDA_GICDA_ICERRR12_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICERRR12_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICERRR12_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICERRR12_status31_SHIFT)) & NOC_GICDA_GICDA_ICERRR12_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR1 - GICDA_ICGERRR1 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR1_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR1_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR1_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR1_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR1_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR1_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR1_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR1_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR1_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR1_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR1_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR1_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR1_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR1_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR1_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR1_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR1_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR1_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR1_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR1_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR1_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR1_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR1_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR1_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR1_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR1_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR1_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR1_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR1_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR1_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR1_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR1_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR1_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR1_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR1_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR1_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR1_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR1_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR1_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR1_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR1_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR1_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR1_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR1_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR1_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR1_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR1_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR1_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR1_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR1_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR1_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR1_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR1_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR1_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR1_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR1_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR1_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR1_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR1_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR1_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR1_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR1_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR1_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR1_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR1_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR1_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR1_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR1_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR2 - GICDA_ICGERRR2 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR2_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR2_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR2_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR2_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR2_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR2_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR2_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR2_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR2_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR2_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR2_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR2_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR2_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR2_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR2_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR2_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR2_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR2_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR2_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR2_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR2_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR2_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR2_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR2_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR2_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR2_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR2_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR2_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR2_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR2_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR2_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR2_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR2_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR2_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR2_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR2_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR2_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR2_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR2_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR2_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR2_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR2_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR2_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR2_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR2_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR2_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR2_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR2_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR2_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR2_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR2_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR2_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR2_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR2_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR2_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR2_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR2_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR2_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR2_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR2_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR2_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR2_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR2_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR2_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR2_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR2_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR2_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR2_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR3 - GICDA_ICGERRR3 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR3_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR3_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR3_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR3_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR3_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR3_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR3_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR3_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR3_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR3_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR3_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR3_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR3_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR3_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR3_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR3_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR3_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR3_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR3_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR3_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR3_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR3_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR3_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR3_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR3_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR3_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR3_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR3_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR3_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR3_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR3_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR3_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR3_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR3_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR3_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR3_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR3_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR3_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR3_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR3_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR3_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR3_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR3_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR3_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR3_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR3_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR3_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR3_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR3_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR3_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR3_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR3_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR3_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR3_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR3_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR3_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR3_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR3_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR3_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR3_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR3_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR3_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR3_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR3_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR3_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR3_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR3_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR3_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR4 - GICDA_ICGERRR4 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR4_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR4_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR4_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR4_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR4_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR4_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR4_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR4_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR4_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR4_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR4_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR4_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR4_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR4_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR4_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR4_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR4_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR4_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR4_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR4_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR4_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR4_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR4_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR4_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR4_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR4_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR4_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR4_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR4_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR4_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR4_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR4_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR4_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR4_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR4_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR4_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR4_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR4_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR4_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR4_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR4_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR4_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR4_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR4_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR4_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR4_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR4_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR4_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR4_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR4_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR4_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR4_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR4_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR4_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR4_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR4_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR4_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR4_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR4_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR4_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR4_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR4_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR4_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR4_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR4_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR4_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR4_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR4_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR5 - GICDA_ICGERRR5 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR5_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR5_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR5_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR5_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR5_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR5_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR5_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR5_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR5_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR5_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR5_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR5_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR5_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR5_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR5_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR5_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR5_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR5_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR5_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR5_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR5_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR5_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR5_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR5_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR5_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR5_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR5_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR5_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR5_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR5_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR5_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR5_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR5_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR5_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR5_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR5_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR5_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR5_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR5_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR5_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR5_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR5_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR5_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR5_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR5_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR5_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR5_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR5_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR5_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR5_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR5_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR5_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR5_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR5_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR5_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR5_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR5_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR5_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR5_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR5_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR5_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR5_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR5_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR5_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR5_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR5_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR5_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR5_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR6 - GICDA_ICGERRR6 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR6_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR6_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR6_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR6_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR6_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR6_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR6_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR6_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR6_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR6_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR6_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR6_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR6_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR6_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR6_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR6_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR6_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR6_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR6_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR6_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR6_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR6_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR6_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR6_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR6_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR6_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR6_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR6_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR6_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR6_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR6_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR6_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR6_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR6_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR6_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR6_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR6_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR6_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR6_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR6_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR6_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR6_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR6_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR6_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR6_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR6_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR6_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR6_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR6_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR6_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR6_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR6_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR6_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR6_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR6_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR6_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR6_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR6_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR6_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR6_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR6_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR6_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR6_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR6_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR6_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR6_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR6_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR6_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR7 - GICDA_ICGERRR7 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR7_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR7_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR7_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR7_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR7_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR7_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR7_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR7_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR7_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR7_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR7_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR7_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR7_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR7_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR7_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR7_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR7_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR7_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR7_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR7_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR7_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR7_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR7_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR7_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR7_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR7_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR7_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR7_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR7_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR7_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR7_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR7_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR7_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR7_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR7_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR7_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR7_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR7_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR7_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR7_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR7_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR7_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR7_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR7_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR7_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR7_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR7_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR7_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR7_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR7_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR7_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR7_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR7_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR7_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR7_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR7_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR7_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR7_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR7_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR7_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR7_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR7_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR7_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR7_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR7_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR7_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR7_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR7_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR8 - GICDA_ICGERRR8 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR8_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR8_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR8_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR8_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR8_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR8_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR8_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR8_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR8_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR8_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR8_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR8_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR8_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR8_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR8_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR8_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR8_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR8_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR8_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR8_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR8_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR8_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR8_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR8_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR8_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR8_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR8_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR8_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR8_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR8_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR8_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR8_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR8_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR8_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR8_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR8_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR8_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR8_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR8_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR8_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR8_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR8_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR8_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR8_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR8_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR8_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR8_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR8_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR8_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR8_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR8_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR8_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR8_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR8_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR8_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR8_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR8_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR8_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR8_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR8_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR8_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR8_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR8_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR8_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR8_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR8_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR8_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR8_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR9 - GICDA_ICGERRR9 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR9_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR9_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR9_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR9_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR9_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR9_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR9_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR9_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR9_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR9_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR9_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR9_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR9_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR9_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR9_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR9_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR9_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR9_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR9_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR9_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR9_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR9_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR9_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR9_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR9_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR9_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR9_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR9_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR9_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR9_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR9_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR9_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR9_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR9_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR9_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR9_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR9_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR9_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR9_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR9_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR9_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR9_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR9_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR9_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR9_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR9_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR9_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR9_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR9_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR9_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR9_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR9_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR9_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR9_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR9_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR9_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR9_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR9_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR9_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR9_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR9_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR9_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR9_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR9_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR9_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR9_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR9_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR9_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR10 - GICDA_ICGERRR10 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR10_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR10_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR10_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR10_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR10_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR10_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR10_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR10_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR10_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR10_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR10_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR10_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR10_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR10_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR10_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR10_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR10_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR10_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR10_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR10_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR10_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR10_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR10_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR10_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR10_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR10_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR10_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR10_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR10_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR10_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR10_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR10_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR10_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR10_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR10_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR10_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR10_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR10_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR10_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR10_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR10_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR10_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR10_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR10_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR10_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR10_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR10_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR10_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR10_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR10_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR10_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR10_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR10_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR10_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR10_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR10_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR10_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR10_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR10_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR10_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR10_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR10_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR10_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR10_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR10_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR10_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR10_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR10_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR11 - GICDA_ICGERRR11 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR11_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR11_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR11_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR11_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR11_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR11_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR11_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR11_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR11_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR11_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR11_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR11_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR11_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR11_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR11_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR11_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR11_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR11_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR11_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR11_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR11_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR11_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR11_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR11_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR11_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR11_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR11_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR11_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR11_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR11_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR11_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR11_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR11_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR11_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR11_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR11_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR11_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR11_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR11_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR11_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR11_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR11_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR11_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR11_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR11_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR11_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR11_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR11_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR11_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR11_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR11_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR11_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR11_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR11_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR11_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR11_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR11_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR11_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR11_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR11_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR11_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR11_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR11_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR11_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR11_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR11_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR11_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR11_status31_MASK) /*! @} */ /*! @name GICDA_ICGERRR12 - GICDA_ICGERRR12 */ /*! @{ */ #define NOC_GICDA_GICDA_ICGERRR12_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ICGERRR12_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ICGERRR12_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status0_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status0_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ICGERRR12_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ICGERRR12_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status1_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status1_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ICGERRR12_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ICGERRR12_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status2_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status2_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ICGERRR12_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ICGERRR12_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status3_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status3_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ICGERRR12_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ICGERRR12_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status4_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status4_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ICGERRR12_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ICGERRR12_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status5_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status5_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ICGERRR12_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ICGERRR12_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status6_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status6_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ICGERRR12_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ICGERRR12_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status7_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status7_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ICGERRR12_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ICGERRR12_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status8_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status8_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ICGERRR12_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ICGERRR12_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status9_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status9_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ICGERRR12_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ICGERRR12_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status10_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status10_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ICGERRR12_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ICGERRR12_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status11_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status11_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ICGERRR12_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ICGERRR12_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status12_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status12_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ICGERRR12_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ICGERRR12_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status13_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status13_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ICGERRR12_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ICGERRR12_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status14_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status14_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ICGERRR12_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ICGERRR12_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status15_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status15_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ICGERRR12_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ICGERRR12_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status16_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status16_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ICGERRR12_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ICGERRR12_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status17_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status17_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ICGERRR12_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ICGERRR12_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status18_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status18_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ICGERRR12_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ICGERRR12_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status19_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status19_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ICGERRR12_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ICGERRR12_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status20_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status20_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ICGERRR12_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ICGERRR12_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status21_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status21_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ICGERRR12_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ICGERRR12_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status22_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status22_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ICGERRR12_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ICGERRR12_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status23_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status23_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ICGERRR12_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ICGERRR12_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status24_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status24_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ICGERRR12_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ICGERRR12_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status25_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status25_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ICGERRR12_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ICGERRR12_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status26_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status26_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ICGERRR12_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ICGERRR12_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status27_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status27_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ICGERRR12_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ICGERRR12_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status28_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status28_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ICGERRR12_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ICGERRR12_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status29_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status29_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ICGERRR12_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ICGERRR12_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status30_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status30_MASK) #define NOC_GICDA_GICDA_ICGERRR12_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ICGERRR12_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ICGERRR12_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ICGERRR12_status31_SHIFT)) & NOC_GICDA_GICDA_ICGERRR12_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR1 - GICDA_ISERRR1 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR1_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR1_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR1_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status0_MASK) #define NOC_GICDA_GICDA_ISERRR1_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR1_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR1_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status1_MASK) #define NOC_GICDA_GICDA_ISERRR1_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR1_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR1_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status2_MASK) #define NOC_GICDA_GICDA_ISERRR1_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR1_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR1_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status3_MASK) #define NOC_GICDA_GICDA_ISERRR1_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR1_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR1_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status4_MASK) #define NOC_GICDA_GICDA_ISERRR1_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR1_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR1_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status5_MASK) #define NOC_GICDA_GICDA_ISERRR1_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR1_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR1_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status6_MASK) #define NOC_GICDA_GICDA_ISERRR1_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR1_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR1_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status7_MASK) #define NOC_GICDA_GICDA_ISERRR1_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR1_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR1_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status8_MASK) #define NOC_GICDA_GICDA_ISERRR1_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR1_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR1_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status9_MASK) #define NOC_GICDA_GICDA_ISERRR1_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR1_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR1_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status10_MASK) #define NOC_GICDA_GICDA_ISERRR1_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR1_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR1_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status11_MASK) #define NOC_GICDA_GICDA_ISERRR1_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR1_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR1_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status12_MASK) #define NOC_GICDA_GICDA_ISERRR1_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR1_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR1_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status13_MASK) #define NOC_GICDA_GICDA_ISERRR1_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR1_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR1_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status14_MASK) #define NOC_GICDA_GICDA_ISERRR1_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR1_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR1_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status15_MASK) #define NOC_GICDA_GICDA_ISERRR1_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR1_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR1_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status16_MASK) #define NOC_GICDA_GICDA_ISERRR1_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR1_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR1_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status17_MASK) #define NOC_GICDA_GICDA_ISERRR1_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR1_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR1_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status18_MASK) #define NOC_GICDA_GICDA_ISERRR1_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR1_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR1_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status19_MASK) #define NOC_GICDA_GICDA_ISERRR1_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR1_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR1_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status20_MASK) #define NOC_GICDA_GICDA_ISERRR1_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR1_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR1_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status21_MASK) #define NOC_GICDA_GICDA_ISERRR1_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR1_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR1_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status22_MASK) #define NOC_GICDA_GICDA_ISERRR1_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR1_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR1_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status23_MASK) #define NOC_GICDA_GICDA_ISERRR1_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR1_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR1_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status24_MASK) #define NOC_GICDA_GICDA_ISERRR1_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR1_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR1_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status25_MASK) #define NOC_GICDA_GICDA_ISERRR1_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR1_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR1_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status26_MASK) #define NOC_GICDA_GICDA_ISERRR1_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR1_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR1_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status27_MASK) #define NOC_GICDA_GICDA_ISERRR1_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR1_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR1_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status28_MASK) #define NOC_GICDA_GICDA_ISERRR1_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR1_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR1_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status29_MASK) #define NOC_GICDA_GICDA_ISERRR1_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR1_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR1_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status30_MASK) #define NOC_GICDA_GICDA_ISERRR1_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR1_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR1_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR1_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR1_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR2 - GICDA_ISERRR2 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR2_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR2_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR2_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status0_MASK) #define NOC_GICDA_GICDA_ISERRR2_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR2_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR2_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status1_MASK) #define NOC_GICDA_GICDA_ISERRR2_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR2_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR2_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status2_MASK) #define NOC_GICDA_GICDA_ISERRR2_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR2_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR2_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status3_MASK) #define NOC_GICDA_GICDA_ISERRR2_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR2_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR2_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status4_MASK) #define NOC_GICDA_GICDA_ISERRR2_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR2_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR2_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status5_MASK) #define NOC_GICDA_GICDA_ISERRR2_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR2_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR2_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status6_MASK) #define NOC_GICDA_GICDA_ISERRR2_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR2_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR2_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status7_MASK) #define NOC_GICDA_GICDA_ISERRR2_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR2_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR2_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status8_MASK) #define NOC_GICDA_GICDA_ISERRR2_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR2_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR2_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status9_MASK) #define NOC_GICDA_GICDA_ISERRR2_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR2_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR2_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status10_MASK) #define NOC_GICDA_GICDA_ISERRR2_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR2_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR2_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status11_MASK) #define NOC_GICDA_GICDA_ISERRR2_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR2_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR2_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status12_MASK) #define NOC_GICDA_GICDA_ISERRR2_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR2_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR2_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status13_MASK) #define NOC_GICDA_GICDA_ISERRR2_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR2_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR2_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status14_MASK) #define NOC_GICDA_GICDA_ISERRR2_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR2_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR2_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status15_MASK) #define NOC_GICDA_GICDA_ISERRR2_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR2_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR2_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status16_MASK) #define NOC_GICDA_GICDA_ISERRR2_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR2_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR2_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status17_MASK) #define NOC_GICDA_GICDA_ISERRR2_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR2_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR2_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status18_MASK) #define NOC_GICDA_GICDA_ISERRR2_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR2_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR2_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status19_MASK) #define NOC_GICDA_GICDA_ISERRR2_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR2_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR2_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status20_MASK) #define NOC_GICDA_GICDA_ISERRR2_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR2_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR2_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status21_MASK) #define NOC_GICDA_GICDA_ISERRR2_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR2_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR2_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status22_MASK) #define NOC_GICDA_GICDA_ISERRR2_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR2_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR2_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status23_MASK) #define NOC_GICDA_GICDA_ISERRR2_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR2_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR2_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status24_MASK) #define NOC_GICDA_GICDA_ISERRR2_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR2_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR2_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status25_MASK) #define NOC_GICDA_GICDA_ISERRR2_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR2_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR2_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status26_MASK) #define NOC_GICDA_GICDA_ISERRR2_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR2_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR2_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status27_MASK) #define NOC_GICDA_GICDA_ISERRR2_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR2_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR2_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status28_MASK) #define NOC_GICDA_GICDA_ISERRR2_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR2_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR2_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status29_MASK) #define NOC_GICDA_GICDA_ISERRR2_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR2_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR2_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status30_MASK) #define NOC_GICDA_GICDA_ISERRR2_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR2_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR2_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR2_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR2_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR3 - GICDA_ISERRR3 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR3_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR3_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR3_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status0_MASK) #define NOC_GICDA_GICDA_ISERRR3_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR3_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR3_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status1_MASK) #define NOC_GICDA_GICDA_ISERRR3_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR3_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR3_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status2_MASK) #define NOC_GICDA_GICDA_ISERRR3_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR3_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR3_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status3_MASK) #define NOC_GICDA_GICDA_ISERRR3_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR3_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR3_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status4_MASK) #define NOC_GICDA_GICDA_ISERRR3_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR3_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR3_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status5_MASK) #define NOC_GICDA_GICDA_ISERRR3_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR3_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR3_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status6_MASK) #define NOC_GICDA_GICDA_ISERRR3_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR3_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR3_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status7_MASK) #define NOC_GICDA_GICDA_ISERRR3_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR3_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR3_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status8_MASK) #define NOC_GICDA_GICDA_ISERRR3_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR3_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR3_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status9_MASK) #define NOC_GICDA_GICDA_ISERRR3_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR3_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR3_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status10_MASK) #define NOC_GICDA_GICDA_ISERRR3_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR3_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR3_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status11_MASK) #define NOC_GICDA_GICDA_ISERRR3_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR3_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR3_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status12_MASK) #define NOC_GICDA_GICDA_ISERRR3_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR3_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR3_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status13_MASK) #define NOC_GICDA_GICDA_ISERRR3_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR3_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR3_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status14_MASK) #define NOC_GICDA_GICDA_ISERRR3_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR3_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR3_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status15_MASK) #define NOC_GICDA_GICDA_ISERRR3_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR3_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR3_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status16_MASK) #define NOC_GICDA_GICDA_ISERRR3_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR3_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR3_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status17_MASK) #define NOC_GICDA_GICDA_ISERRR3_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR3_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR3_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status18_MASK) #define NOC_GICDA_GICDA_ISERRR3_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR3_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR3_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status19_MASK) #define NOC_GICDA_GICDA_ISERRR3_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR3_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR3_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status20_MASK) #define NOC_GICDA_GICDA_ISERRR3_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR3_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR3_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status21_MASK) #define NOC_GICDA_GICDA_ISERRR3_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR3_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR3_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status22_MASK) #define NOC_GICDA_GICDA_ISERRR3_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR3_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR3_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status23_MASK) #define NOC_GICDA_GICDA_ISERRR3_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR3_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR3_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status24_MASK) #define NOC_GICDA_GICDA_ISERRR3_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR3_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR3_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status25_MASK) #define NOC_GICDA_GICDA_ISERRR3_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR3_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR3_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status26_MASK) #define NOC_GICDA_GICDA_ISERRR3_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR3_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR3_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status27_MASK) #define NOC_GICDA_GICDA_ISERRR3_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR3_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR3_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status28_MASK) #define NOC_GICDA_GICDA_ISERRR3_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR3_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR3_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status29_MASK) #define NOC_GICDA_GICDA_ISERRR3_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR3_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR3_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status30_MASK) #define NOC_GICDA_GICDA_ISERRR3_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR3_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR3_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR3_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR3_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR4 - GICDA_ISERRR4 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR4_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR4_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR4_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status0_MASK) #define NOC_GICDA_GICDA_ISERRR4_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR4_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR4_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status1_MASK) #define NOC_GICDA_GICDA_ISERRR4_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR4_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR4_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status2_MASK) #define NOC_GICDA_GICDA_ISERRR4_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR4_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR4_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status3_MASK) #define NOC_GICDA_GICDA_ISERRR4_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR4_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR4_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status4_MASK) #define NOC_GICDA_GICDA_ISERRR4_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR4_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR4_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status5_MASK) #define NOC_GICDA_GICDA_ISERRR4_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR4_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR4_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status6_MASK) #define NOC_GICDA_GICDA_ISERRR4_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR4_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR4_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status7_MASK) #define NOC_GICDA_GICDA_ISERRR4_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR4_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR4_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status8_MASK) #define NOC_GICDA_GICDA_ISERRR4_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR4_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR4_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status9_MASK) #define NOC_GICDA_GICDA_ISERRR4_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR4_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR4_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status10_MASK) #define NOC_GICDA_GICDA_ISERRR4_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR4_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR4_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status11_MASK) #define NOC_GICDA_GICDA_ISERRR4_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR4_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR4_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status12_MASK) #define NOC_GICDA_GICDA_ISERRR4_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR4_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR4_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status13_MASK) #define NOC_GICDA_GICDA_ISERRR4_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR4_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR4_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status14_MASK) #define NOC_GICDA_GICDA_ISERRR4_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR4_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR4_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status15_MASK) #define NOC_GICDA_GICDA_ISERRR4_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR4_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR4_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status16_MASK) #define NOC_GICDA_GICDA_ISERRR4_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR4_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR4_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status17_MASK) #define NOC_GICDA_GICDA_ISERRR4_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR4_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR4_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status18_MASK) #define NOC_GICDA_GICDA_ISERRR4_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR4_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR4_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status19_MASK) #define NOC_GICDA_GICDA_ISERRR4_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR4_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR4_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status20_MASK) #define NOC_GICDA_GICDA_ISERRR4_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR4_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR4_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status21_MASK) #define NOC_GICDA_GICDA_ISERRR4_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR4_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR4_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status22_MASK) #define NOC_GICDA_GICDA_ISERRR4_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR4_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR4_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status23_MASK) #define NOC_GICDA_GICDA_ISERRR4_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR4_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR4_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status24_MASK) #define NOC_GICDA_GICDA_ISERRR4_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR4_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR4_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status25_MASK) #define NOC_GICDA_GICDA_ISERRR4_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR4_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR4_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status26_MASK) #define NOC_GICDA_GICDA_ISERRR4_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR4_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR4_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status27_MASK) #define NOC_GICDA_GICDA_ISERRR4_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR4_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR4_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status28_MASK) #define NOC_GICDA_GICDA_ISERRR4_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR4_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR4_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status29_MASK) #define NOC_GICDA_GICDA_ISERRR4_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR4_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR4_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status30_MASK) #define NOC_GICDA_GICDA_ISERRR4_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR4_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR4_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR4_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR4_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR5 - GICDA_ISERRR5 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR5_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR5_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR5_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status0_MASK) #define NOC_GICDA_GICDA_ISERRR5_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR5_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR5_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status1_MASK) #define NOC_GICDA_GICDA_ISERRR5_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR5_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR5_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status2_MASK) #define NOC_GICDA_GICDA_ISERRR5_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR5_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR5_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status3_MASK) #define NOC_GICDA_GICDA_ISERRR5_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR5_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR5_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status4_MASK) #define NOC_GICDA_GICDA_ISERRR5_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR5_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR5_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status5_MASK) #define NOC_GICDA_GICDA_ISERRR5_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR5_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR5_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status6_MASK) #define NOC_GICDA_GICDA_ISERRR5_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR5_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR5_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status7_MASK) #define NOC_GICDA_GICDA_ISERRR5_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR5_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR5_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status8_MASK) #define NOC_GICDA_GICDA_ISERRR5_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR5_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR5_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status9_MASK) #define NOC_GICDA_GICDA_ISERRR5_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR5_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR5_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status10_MASK) #define NOC_GICDA_GICDA_ISERRR5_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR5_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR5_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status11_MASK) #define NOC_GICDA_GICDA_ISERRR5_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR5_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR5_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status12_MASK) #define NOC_GICDA_GICDA_ISERRR5_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR5_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR5_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status13_MASK) #define NOC_GICDA_GICDA_ISERRR5_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR5_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR5_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status14_MASK) #define NOC_GICDA_GICDA_ISERRR5_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR5_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR5_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status15_MASK) #define NOC_GICDA_GICDA_ISERRR5_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR5_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR5_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status16_MASK) #define NOC_GICDA_GICDA_ISERRR5_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR5_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR5_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status17_MASK) #define NOC_GICDA_GICDA_ISERRR5_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR5_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR5_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status18_MASK) #define NOC_GICDA_GICDA_ISERRR5_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR5_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR5_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status19_MASK) #define NOC_GICDA_GICDA_ISERRR5_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR5_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR5_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status20_MASK) #define NOC_GICDA_GICDA_ISERRR5_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR5_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR5_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status21_MASK) #define NOC_GICDA_GICDA_ISERRR5_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR5_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR5_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status22_MASK) #define NOC_GICDA_GICDA_ISERRR5_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR5_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR5_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status23_MASK) #define NOC_GICDA_GICDA_ISERRR5_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR5_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR5_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status24_MASK) #define NOC_GICDA_GICDA_ISERRR5_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR5_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR5_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status25_MASK) #define NOC_GICDA_GICDA_ISERRR5_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR5_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR5_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status26_MASK) #define NOC_GICDA_GICDA_ISERRR5_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR5_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR5_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status27_MASK) #define NOC_GICDA_GICDA_ISERRR5_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR5_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR5_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status28_MASK) #define NOC_GICDA_GICDA_ISERRR5_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR5_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR5_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status29_MASK) #define NOC_GICDA_GICDA_ISERRR5_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR5_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR5_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status30_MASK) #define NOC_GICDA_GICDA_ISERRR5_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR5_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR5_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR5_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR5_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR6 - GICDA_ISERRR6 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR6_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR6_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR6_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status0_MASK) #define NOC_GICDA_GICDA_ISERRR6_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR6_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR6_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status1_MASK) #define NOC_GICDA_GICDA_ISERRR6_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR6_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR6_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status2_MASK) #define NOC_GICDA_GICDA_ISERRR6_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR6_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR6_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status3_MASK) #define NOC_GICDA_GICDA_ISERRR6_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR6_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR6_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status4_MASK) #define NOC_GICDA_GICDA_ISERRR6_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR6_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR6_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status5_MASK) #define NOC_GICDA_GICDA_ISERRR6_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR6_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR6_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status6_MASK) #define NOC_GICDA_GICDA_ISERRR6_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR6_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR6_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status7_MASK) #define NOC_GICDA_GICDA_ISERRR6_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR6_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR6_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status8_MASK) #define NOC_GICDA_GICDA_ISERRR6_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR6_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR6_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status9_MASK) #define NOC_GICDA_GICDA_ISERRR6_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR6_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR6_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status10_MASK) #define NOC_GICDA_GICDA_ISERRR6_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR6_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR6_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status11_MASK) #define NOC_GICDA_GICDA_ISERRR6_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR6_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR6_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status12_MASK) #define NOC_GICDA_GICDA_ISERRR6_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR6_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR6_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status13_MASK) #define NOC_GICDA_GICDA_ISERRR6_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR6_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR6_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status14_MASK) #define NOC_GICDA_GICDA_ISERRR6_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR6_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR6_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status15_MASK) #define NOC_GICDA_GICDA_ISERRR6_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR6_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR6_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status16_MASK) #define NOC_GICDA_GICDA_ISERRR6_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR6_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR6_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status17_MASK) #define NOC_GICDA_GICDA_ISERRR6_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR6_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR6_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status18_MASK) #define NOC_GICDA_GICDA_ISERRR6_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR6_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR6_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status19_MASK) #define NOC_GICDA_GICDA_ISERRR6_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR6_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR6_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status20_MASK) #define NOC_GICDA_GICDA_ISERRR6_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR6_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR6_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status21_MASK) #define NOC_GICDA_GICDA_ISERRR6_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR6_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR6_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status22_MASK) #define NOC_GICDA_GICDA_ISERRR6_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR6_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR6_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status23_MASK) #define NOC_GICDA_GICDA_ISERRR6_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR6_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR6_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status24_MASK) #define NOC_GICDA_GICDA_ISERRR6_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR6_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR6_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status25_MASK) #define NOC_GICDA_GICDA_ISERRR6_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR6_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR6_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status26_MASK) #define NOC_GICDA_GICDA_ISERRR6_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR6_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR6_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status27_MASK) #define NOC_GICDA_GICDA_ISERRR6_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR6_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR6_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status28_MASK) #define NOC_GICDA_GICDA_ISERRR6_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR6_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR6_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status29_MASK) #define NOC_GICDA_GICDA_ISERRR6_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR6_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR6_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status30_MASK) #define NOC_GICDA_GICDA_ISERRR6_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR6_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR6_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR6_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR6_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR7 - GICDA_ISERRR7 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR7_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR7_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR7_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status0_MASK) #define NOC_GICDA_GICDA_ISERRR7_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR7_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR7_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status1_MASK) #define NOC_GICDA_GICDA_ISERRR7_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR7_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR7_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status2_MASK) #define NOC_GICDA_GICDA_ISERRR7_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR7_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR7_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status3_MASK) #define NOC_GICDA_GICDA_ISERRR7_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR7_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR7_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status4_MASK) #define NOC_GICDA_GICDA_ISERRR7_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR7_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR7_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status5_MASK) #define NOC_GICDA_GICDA_ISERRR7_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR7_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR7_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status6_MASK) #define NOC_GICDA_GICDA_ISERRR7_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR7_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR7_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status7_MASK) #define NOC_GICDA_GICDA_ISERRR7_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR7_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR7_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status8_MASK) #define NOC_GICDA_GICDA_ISERRR7_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR7_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR7_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status9_MASK) #define NOC_GICDA_GICDA_ISERRR7_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR7_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR7_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status10_MASK) #define NOC_GICDA_GICDA_ISERRR7_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR7_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR7_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status11_MASK) #define NOC_GICDA_GICDA_ISERRR7_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR7_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR7_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status12_MASK) #define NOC_GICDA_GICDA_ISERRR7_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR7_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR7_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status13_MASK) #define NOC_GICDA_GICDA_ISERRR7_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR7_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR7_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status14_MASK) #define NOC_GICDA_GICDA_ISERRR7_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR7_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR7_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status15_MASK) #define NOC_GICDA_GICDA_ISERRR7_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR7_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR7_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status16_MASK) #define NOC_GICDA_GICDA_ISERRR7_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR7_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR7_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status17_MASK) #define NOC_GICDA_GICDA_ISERRR7_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR7_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR7_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status18_MASK) #define NOC_GICDA_GICDA_ISERRR7_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR7_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR7_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status19_MASK) #define NOC_GICDA_GICDA_ISERRR7_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR7_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR7_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status20_MASK) #define NOC_GICDA_GICDA_ISERRR7_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR7_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR7_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status21_MASK) #define NOC_GICDA_GICDA_ISERRR7_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR7_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR7_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status22_MASK) #define NOC_GICDA_GICDA_ISERRR7_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR7_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR7_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status23_MASK) #define NOC_GICDA_GICDA_ISERRR7_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR7_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR7_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status24_MASK) #define NOC_GICDA_GICDA_ISERRR7_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR7_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR7_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status25_MASK) #define NOC_GICDA_GICDA_ISERRR7_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR7_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR7_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status26_MASK) #define NOC_GICDA_GICDA_ISERRR7_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR7_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR7_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status27_MASK) #define NOC_GICDA_GICDA_ISERRR7_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR7_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR7_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status28_MASK) #define NOC_GICDA_GICDA_ISERRR7_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR7_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR7_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status29_MASK) #define NOC_GICDA_GICDA_ISERRR7_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR7_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR7_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status30_MASK) #define NOC_GICDA_GICDA_ISERRR7_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR7_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR7_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR7_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR7_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR8 - GICDA_ISERRR8 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR8_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR8_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR8_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status0_MASK) #define NOC_GICDA_GICDA_ISERRR8_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR8_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR8_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status1_MASK) #define NOC_GICDA_GICDA_ISERRR8_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR8_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR8_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status2_MASK) #define NOC_GICDA_GICDA_ISERRR8_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR8_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR8_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status3_MASK) #define NOC_GICDA_GICDA_ISERRR8_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR8_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR8_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status4_MASK) #define NOC_GICDA_GICDA_ISERRR8_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR8_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR8_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status5_MASK) #define NOC_GICDA_GICDA_ISERRR8_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR8_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR8_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status6_MASK) #define NOC_GICDA_GICDA_ISERRR8_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR8_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR8_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status7_MASK) #define NOC_GICDA_GICDA_ISERRR8_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR8_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR8_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status8_MASK) #define NOC_GICDA_GICDA_ISERRR8_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR8_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR8_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status9_MASK) #define NOC_GICDA_GICDA_ISERRR8_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR8_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR8_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status10_MASK) #define NOC_GICDA_GICDA_ISERRR8_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR8_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR8_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status11_MASK) #define NOC_GICDA_GICDA_ISERRR8_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR8_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR8_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status12_MASK) #define NOC_GICDA_GICDA_ISERRR8_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR8_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR8_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status13_MASK) #define NOC_GICDA_GICDA_ISERRR8_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR8_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR8_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status14_MASK) #define NOC_GICDA_GICDA_ISERRR8_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR8_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR8_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status15_MASK) #define NOC_GICDA_GICDA_ISERRR8_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR8_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR8_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status16_MASK) #define NOC_GICDA_GICDA_ISERRR8_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR8_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR8_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status17_MASK) #define NOC_GICDA_GICDA_ISERRR8_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR8_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR8_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status18_MASK) #define NOC_GICDA_GICDA_ISERRR8_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR8_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR8_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status19_MASK) #define NOC_GICDA_GICDA_ISERRR8_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR8_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR8_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status20_MASK) #define NOC_GICDA_GICDA_ISERRR8_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR8_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR8_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status21_MASK) #define NOC_GICDA_GICDA_ISERRR8_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR8_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR8_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status22_MASK) #define NOC_GICDA_GICDA_ISERRR8_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR8_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR8_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status23_MASK) #define NOC_GICDA_GICDA_ISERRR8_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR8_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR8_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status24_MASK) #define NOC_GICDA_GICDA_ISERRR8_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR8_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR8_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status25_MASK) #define NOC_GICDA_GICDA_ISERRR8_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR8_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR8_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status26_MASK) #define NOC_GICDA_GICDA_ISERRR8_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR8_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR8_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status27_MASK) #define NOC_GICDA_GICDA_ISERRR8_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR8_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR8_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status28_MASK) #define NOC_GICDA_GICDA_ISERRR8_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR8_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR8_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status29_MASK) #define NOC_GICDA_GICDA_ISERRR8_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR8_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR8_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status30_MASK) #define NOC_GICDA_GICDA_ISERRR8_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR8_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR8_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR8_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR8_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR9 - GICDA_ISERRR9 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR9_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR9_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR9_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status0_MASK) #define NOC_GICDA_GICDA_ISERRR9_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR9_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR9_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status1_MASK) #define NOC_GICDA_GICDA_ISERRR9_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR9_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR9_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status2_MASK) #define NOC_GICDA_GICDA_ISERRR9_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR9_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR9_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status3_MASK) #define NOC_GICDA_GICDA_ISERRR9_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR9_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR9_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status4_MASK) #define NOC_GICDA_GICDA_ISERRR9_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR9_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR9_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status5_MASK) #define NOC_GICDA_GICDA_ISERRR9_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR9_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR9_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status6_MASK) #define NOC_GICDA_GICDA_ISERRR9_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR9_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR9_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status7_MASK) #define NOC_GICDA_GICDA_ISERRR9_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR9_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR9_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status8_MASK) #define NOC_GICDA_GICDA_ISERRR9_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR9_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR9_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status9_MASK) #define NOC_GICDA_GICDA_ISERRR9_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR9_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR9_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status10_MASK) #define NOC_GICDA_GICDA_ISERRR9_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR9_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR9_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status11_MASK) #define NOC_GICDA_GICDA_ISERRR9_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR9_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR9_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status12_MASK) #define NOC_GICDA_GICDA_ISERRR9_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR9_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR9_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status13_MASK) #define NOC_GICDA_GICDA_ISERRR9_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR9_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR9_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status14_MASK) #define NOC_GICDA_GICDA_ISERRR9_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR9_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR9_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status15_MASK) #define NOC_GICDA_GICDA_ISERRR9_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR9_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR9_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status16_MASK) #define NOC_GICDA_GICDA_ISERRR9_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR9_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR9_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status17_MASK) #define NOC_GICDA_GICDA_ISERRR9_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR9_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR9_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status18_MASK) #define NOC_GICDA_GICDA_ISERRR9_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR9_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR9_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status19_MASK) #define NOC_GICDA_GICDA_ISERRR9_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR9_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR9_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status20_MASK) #define NOC_GICDA_GICDA_ISERRR9_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR9_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR9_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status21_MASK) #define NOC_GICDA_GICDA_ISERRR9_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR9_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR9_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status22_MASK) #define NOC_GICDA_GICDA_ISERRR9_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR9_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR9_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status23_MASK) #define NOC_GICDA_GICDA_ISERRR9_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR9_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR9_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status24_MASK) #define NOC_GICDA_GICDA_ISERRR9_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR9_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR9_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status25_MASK) #define NOC_GICDA_GICDA_ISERRR9_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR9_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR9_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status26_MASK) #define NOC_GICDA_GICDA_ISERRR9_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR9_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR9_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status27_MASK) #define NOC_GICDA_GICDA_ISERRR9_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR9_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR9_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status28_MASK) #define NOC_GICDA_GICDA_ISERRR9_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR9_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR9_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status29_MASK) #define NOC_GICDA_GICDA_ISERRR9_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR9_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR9_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status30_MASK) #define NOC_GICDA_GICDA_ISERRR9_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR9_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR9_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR9_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR9_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR10 - GICDA_ISERRR10 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR10_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR10_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR10_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status0_MASK) #define NOC_GICDA_GICDA_ISERRR10_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR10_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR10_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status1_MASK) #define NOC_GICDA_GICDA_ISERRR10_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR10_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR10_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status2_MASK) #define NOC_GICDA_GICDA_ISERRR10_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR10_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR10_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status3_MASK) #define NOC_GICDA_GICDA_ISERRR10_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR10_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR10_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status4_MASK) #define NOC_GICDA_GICDA_ISERRR10_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR10_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR10_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status5_MASK) #define NOC_GICDA_GICDA_ISERRR10_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR10_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR10_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status6_MASK) #define NOC_GICDA_GICDA_ISERRR10_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR10_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR10_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status7_MASK) #define NOC_GICDA_GICDA_ISERRR10_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR10_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR10_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status8_MASK) #define NOC_GICDA_GICDA_ISERRR10_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR10_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR10_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status9_MASK) #define NOC_GICDA_GICDA_ISERRR10_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR10_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR10_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status10_MASK) #define NOC_GICDA_GICDA_ISERRR10_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR10_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR10_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status11_MASK) #define NOC_GICDA_GICDA_ISERRR10_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR10_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR10_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status12_MASK) #define NOC_GICDA_GICDA_ISERRR10_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR10_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR10_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status13_MASK) #define NOC_GICDA_GICDA_ISERRR10_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR10_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR10_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status14_MASK) #define NOC_GICDA_GICDA_ISERRR10_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR10_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR10_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status15_MASK) #define NOC_GICDA_GICDA_ISERRR10_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR10_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR10_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status16_MASK) #define NOC_GICDA_GICDA_ISERRR10_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR10_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR10_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status17_MASK) #define NOC_GICDA_GICDA_ISERRR10_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR10_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR10_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status18_MASK) #define NOC_GICDA_GICDA_ISERRR10_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR10_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR10_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status19_MASK) #define NOC_GICDA_GICDA_ISERRR10_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR10_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR10_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status20_MASK) #define NOC_GICDA_GICDA_ISERRR10_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR10_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR10_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status21_MASK) #define NOC_GICDA_GICDA_ISERRR10_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR10_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR10_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status22_MASK) #define NOC_GICDA_GICDA_ISERRR10_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR10_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR10_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status23_MASK) #define NOC_GICDA_GICDA_ISERRR10_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR10_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR10_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status24_MASK) #define NOC_GICDA_GICDA_ISERRR10_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR10_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR10_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status25_MASK) #define NOC_GICDA_GICDA_ISERRR10_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR10_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR10_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status26_MASK) #define NOC_GICDA_GICDA_ISERRR10_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR10_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR10_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status27_MASK) #define NOC_GICDA_GICDA_ISERRR10_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR10_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR10_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status28_MASK) #define NOC_GICDA_GICDA_ISERRR10_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR10_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR10_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status29_MASK) #define NOC_GICDA_GICDA_ISERRR10_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR10_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR10_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status30_MASK) #define NOC_GICDA_GICDA_ISERRR10_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR10_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR10_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR10_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR10_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR11 - GICDA_ISERRR11 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR11_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR11_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR11_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status0_MASK) #define NOC_GICDA_GICDA_ISERRR11_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR11_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR11_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status1_MASK) #define NOC_GICDA_GICDA_ISERRR11_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR11_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR11_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status2_MASK) #define NOC_GICDA_GICDA_ISERRR11_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR11_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR11_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status3_MASK) #define NOC_GICDA_GICDA_ISERRR11_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR11_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR11_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status4_MASK) #define NOC_GICDA_GICDA_ISERRR11_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR11_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR11_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status5_MASK) #define NOC_GICDA_GICDA_ISERRR11_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR11_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR11_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status6_MASK) #define NOC_GICDA_GICDA_ISERRR11_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR11_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR11_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status7_MASK) #define NOC_GICDA_GICDA_ISERRR11_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR11_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR11_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status8_MASK) #define NOC_GICDA_GICDA_ISERRR11_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR11_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR11_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status9_MASK) #define NOC_GICDA_GICDA_ISERRR11_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR11_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR11_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status10_MASK) #define NOC_GICDA_GICDA_ISERRR11_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR11_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR11_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status11_MASK) #define NOC_GICDA_GICDA_ISERRR11_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR11_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR11_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status12_MASK) #define NOC_GICDA_GICDA_ISERRR11_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR11_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR11_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status13_MASK) #define NOC_GICDA_GICDA_ISERRR11_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR11_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR11_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status14_MASK) #define NOC_GICDA_GICDA_ISERRR11_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR11_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR11_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status15_MASK) #define NOC_GICDA_GICDA_ISERRR11_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR11_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR11_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status16_MASK) #define NOC_GICDA_GICDA_ISERRR11_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR11_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR11_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status17_MASK) #define NOC_GICDA_GICDA_ISERRR11_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR11_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR11_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status18_MASK) #define NOC_GICDA_GICDA_ISERRR11_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR11_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR11_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status19_MASK) #define NOC_GICDA_GICDA_ISERRR11_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR11_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR11_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status20_MASK) #define NOC_GICDA_GICDA_ISERRR11_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR11_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR11_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status21_MASK) #define NOC_GICDA_GICDA_ISERRR11_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR11_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR11_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status22_MASK) #define NOC_GICDA_GICDA_ISERRR11_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR11_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR11_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status23_MASK) #define NOC_GICDA_GICDA_ISERRR11_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR11_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR11_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status24_MASK) #define NOC_GICDA_GICDA_ISERRR11_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR11_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR11_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status25_MASK) #define NOC_GICDA_GICDA_ISERRR11_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR11_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR11_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status26_MASK) #define NOC_GICDA_GICDA_ISERRR11_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR11_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR11_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status27_MASK) #define NOC_GICDA_GICDA_ISERRR11_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR11_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR11_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status28_MASK) #define NOC_GICDA_GICDA_ISERRR11_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR11_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR11_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status29_MASK) #define NOC_GICDA_GICDA_ISERRR11_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR11_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR11_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status30_MASK) #define NOC_GICDA_GICDA_ISERRR11_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR11_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR11_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR11_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR11_status31_MASK) /*! @} */ /*! @name GICDA_ISERRR12 - GICDA_ISERRR12 */ /*! @{ */ #define NOC_GICDA_GICDA_ISERRR12_status0_MASK (0x1U) #define NOC_GICDA_GICDA_ISERRR12_status0_SHIFT (0U) /*! status0 - status0 */ #define NOC_GICDA_GICDA_ISERRR12_status0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status0_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status0_MASK) #define NOC_GICDA_GICDA_ISERRR12_status1_MASK (0x2U) #define NOC_GICDA_GICDA_ISERRR12_status1_SHIFT (1U) /*! status1 - status1 */ #define NOC_GICDA_GICDA_ISERRR12_status1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status1_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status1_MASK) #define NOC_GICDA_GICDA_ISERRR12_status2_MASK (0x4U) #define NOC_GICDA_GICDA_ISERRR12_status2_SHIFT (2U) /*! status2 - status2 */ #define NOC_GICDA_GICDA_ISERRR12_status2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status2_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status2_MASK) #define NOC_GICDA_GICDA_ISERRR12_status3_MASK (0x8U) #define NOC_GICDA_GICDA_ISERRR12_status3_SHIFT (3U) /*! status3 - status3 */ #define NOC_GICDA_GICDA_ISERRR12_status3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status3_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status3_MASK) #define NOC_GICDA_GICDA_ISERRR12_status4_MASK (0x10U) #define NOC_GICDA_GICDA_ISERRR12_status4_SHIFT (4U) /*! status4 - status4 */ #define NOC_GICDA_GICDA_ISERRR12_status4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status4_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status4_MASK) #define NOC_GICDA_GICDA_ISERRR12_status5_MASK (0x20U) #define NOC_GICDA_GICDA_ISERRR12_status5_SHIFT (5U) /*! status5 - status5 */ #define NOC_GICDA_GICDA_ISERRR12_status5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status5_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status5_MASK) #define NOC_GICDA_GICDA_ISERRR12_status6_MASK (0x40U) #define NOC_GICDA_GICDA_ISERRR12_status6_SHIFT (6U) /*! status6 - status6 */ #define NOC_GICDA_GICDA_ISERRR12_status6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status6_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status6_MASK) #define NOC_GICDA_GICDA_ISERRR12_status7_MASK (0x80U) #define NOC_GICDA_GICDA_ISERRR12_status7_SHIFT (7U) /*! status7 - status7 */ #define NOC_GICDA_GICDA_ISERRR12_status7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status7_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status7_MASK) #define NOC_GICDA_GICDA_ISERRR12_status8_MASK (0x100U) #define NOC_GICDA_GICDA_ISERRR12_status8_SHIFT (8U) /*! status8 - status8 */ #define NOC_GICDA_GICDA_ISERRR12_status8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status8_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status8_MASK) #define NOC_GICDA_GICDA_ISERRR12_status9_MASK (0x200U) #define NOC_GICDA_GICDA_ISERRR12_status9_SHIFT (9U) /*! status9 - status9 */ #define NOC_GICDA_GICDA_ISERRR12_status9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status9_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status9_MASK) #define NOC_GICDA_GICDA_ISERRR12_status10_MASK (0x400U) #define NOC_GICDA_GICDA_ISERRR12_status10_SHIFT (10U) /*! status10 - status10 */ #define NOC_GICDA_GICDA_ISERRR12_status10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status10_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status10_MASK) #define NOC_GICDA_GICDA_ISERRR12_status11_MASK (0x800U) #define NOC_GICDA_GICDA_ISERRR12_status11_SHIFT (11U) /*! status11 - status11 */ #define NOC_GICDA_GICDA_ISERRR12_status11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status11_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status11_MASK) #define NOC_GICDA_GICDA_ISERRR12_status12_MASK (0x1000U) #define NOC_GICDA_GICDA_ISERRR12_status12_SHIFT (12U) /*! status12 - status12 */ #define NOC_GICDA_GICDA_ISERRR12_status12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status12_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status12_MASK) #define NOC_GICDA_GICDA_ISERRR12_status13_MASK (0x2000U) #define NOC_GICDA_GICDA_ISERRR12_status13_SHIFT (13U) /*! status13 - status13 */ #define NOC_GICDA_GICDA_ISERRR12_status13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status13_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status13_MASK) #define NOC_GICDA_GICDA_ISERRR12_status14_MASK (0x4000U) #define NOC_GICDA_GICDA_ISERRR12_status14_SHIFT (14U) /*! status14 - status14 */ #define NOC_GICDA_GICDA_ISERRR12_status14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status14_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status14_MASK) #define NOC_GICDA_GICDA_ISERRR12_status15_MASK (0x8000U) #define NOC_GICDA_GICDA_ISERRR12_status15_SHIFT (15U) /*! status15 - status15 */ #define NOC_GICDA_GICDA_ISERRR12_status15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status15_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status15_MASK) #define NOC_GICDA_GICDA_ISERRR12_status16_MASK (0x10000U) #define NOC_GICDA_GICDA_ISERRR12_status16_SHIFT (16U) /*! status16 - status16 */ #define NOC_GICDA_GICDA_ISERRR12_status16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status16_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status16_MASK) #define NOC_GICDA_GICDA_ISERRR12_status17_MASK (0x20000U) #define NOC_GICDA_GICDA_ISERRR12_status17_SHIFT (17U) /*! status17 - status17 */ #define NOC_GICDA_GICDA_ISERRR12_status17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status17_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status17_MASK) #define NOC_GICDA_GICDA_ISERRR12_status18_MASK (0x40000U) #define NOC_GICDA_GICDA_ISERRR12_status18_SHIFT (18U) /*! status18 - status18 */ #define NOC_GICDA_GICDA_ISERRR12_status18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status18_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status18_MASK) #define NOC_GICDA_GICDA_ISERRR12_status19_MASK (0x80000U) #define NOC_GICDA_GICDA_ISERRR12_status19_SHIFT (19U) /*! status19 - status19 */ #define NOC_GICDA_GICDA_ISERRR12_status19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status19_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status19_MASK) #define NOC_GICDA_GICDA_ISERRR12_status20_MASK (0x100000U) #define NOC_GICDA_GICDA_ISERRR12_status20_SHIFT (20U) /*! status20 - status20 */ #define NOC_GICDA_GICDA_ISERRR12_status20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status20_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status20_MASK) #define NOC_GICDA_GICDA_ISERRR12_status21_MASK (0x200000U) #define NOC_GICDA_GICDA_ISERRR12_status21_SHIFT (21U) /*! status21 - status21 */ #define NOC_GICDA_GICDA_ISERRR12_status21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status21_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status21_MASK) #define NOC_GICDA_GICDA_ISERRR12_status22_MASK (0x400000U) #define NOC_GICDA_GICDA_ISERRR12_status22_SHIFT (22U) /*! status22 - status22 */ #define NOC_GICDA_GICDA_ISERRR12_status22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status22_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status22_MASK) #define NOC_GICDA_GICDA_ISERRR12_status23_MASK (0x800000U) #define NOC_GICDA_GICDA_ISERRR12_status23_SHIFT (23U) /*! status23 - status23 */ #define NOC_GICDA_GICDA_ISERRR12_status23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status23_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status23_MASK) #define NOC_GICDA_GICDA_ISERRR12_status24_MASK (0x1000000U) #define NOC_GICDA_GICDA_ISERRR12_status24_SHIFT (24U) /*! status24 - status24 */ #define NOC_GICDA_GICDA_ISERRR12_status24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status24_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status24_MASK) #define NOC_GICDA_GICDA_ISERRR12_status25_MASK (0x2000000U) #define NOC_GICDA_GICDA_ISERRR12_status25_SHIFT (25U) /*! status25 - status25 */ #define NOC_GICDA_GICDA_ISERRR12_status25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status25_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status25_MASK) #define NOC_GICDA_GICDA_ISERRR12_status26_MASK (0x4000000U) #define NOC_GICDA_GICDA_ISERRR12_status26_SHIFT (26U) /*! status26 - status26 */ #define NOC_GICDA_GICDA_ISERRR12_status26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status26_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status26_MASK) #define NOC_GICDA_GICDA_ISERRR12_status27_MASK (0x8000000U) #define NOC_GICDA_GICDA_ISERRR12_status27_SHIFT (27U) /*! status27 - status27 */ #define NOC_GICDA_GICDA_ISERRR12_status27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status27_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status27_MASK) #define NOC_GICDA_GICDA_ISERRR12_status28_MASK (0x10000000U) #define NOC_GICDA_GICDA_ISERRR12_status28_SHIFT (28U) /*! status28 - status28 */ #define NOC_GICDA_GICDA_ISERRR12_status28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status28_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status28_MASK) #define NOC_GICDA_GICDA_ISERRR12_status29_MASK (0x20000000U) #define NOC_GICDA_GICDA_ISERRR12_status29_SHIFT (29U) /*! status29 - status29 */ #define NOC_GICDA_GICDA_ISERRR12_status29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status29_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status29_MASK) #define NOC_GICDA_GICDA_ISERRR12_status30_MASK (0x40000000U) #define NOC_GICDA_GICDA_ISERRR12_status30_SHIFT (30U) /*! status30 - status30 */ #define NOC_GICDA_GICDA_ISERRR12_status30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status30_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status30_MASK) #define NOC_GICDA_GICDA_ISERRR12_status31_MASK (0x80000000U) #define NOC_GICDA_GICDA_ISERRR12_status31_SHIFT (31U) /*! status31 - status31 */ #define NOC_GICDA_GICDA_ISERRR12_status31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_ISERRR12_status31_SHIFT)) & NOC_GICDA_GICDA_ISERRR12_status31_MASK) /*! @} */ /*! @name GICDA_CFGID - GICDA_CFGID */ /*! @{ */ #define NOC_GICDA_GICDA_CFGID_SocketOnline_MASK (0x1U) #define NOC_GICDA_GICDA_CFGID_SocketOnline_SHIFT (0U) /*! SocketOnline - SocketOnline */ #define NOC_GICDA_GICDA_CFGID_SocketOnline(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_SocketOnline_SHIFT)) & NOC_GICDA_GICDA_CFGID_SocketOnline_MASK) #define NOC_GICDA_GICDA_CFGID_RESERVED0_MASK (0xEU) #define NOC_GICDA_GICDA_CFGID_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CFGID_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CFGID_RESERVED0_MASK) #define NOC_GICDA_GICDA_CFGID_SocketNumber_MASK (0xF0U) #define NOC_GICDA_GICDA_CFGID_SocketNumber_SHIFT (4U) /*! SocketNumber - SocketNumber */ #define NOC_GICDA_GICDA_CFGID_SocketNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_SocketNumber_SHIFT)) & NOC_GICDA_GICDA_CFGID_SocketNumber_MASK) #define NOC_GICDA_GICDA_CFGID_ITSCount_MASK (0xF00U) #define NOC_GICDA_GICDA_CFGID_ITSCount_SHIFT (8U) /*! ITSCount - ITSCount */ #define NOC_GICDA_GICDA_CFGID_ITSCount(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_ITSCount_SHIFT)) & NOC_GICDA_GICDA_CFGID_ITSCount_MASK) #define NOC_GICDA_GICDA_CFGID_LPISupport_MASK (0x1000U) #define NOC_GICDA_GICDA_CFGID_LPISupport_SHIFT (12U) /*! LPISupport - LPISupport */ #define NOC_GICDA_GICDA_CFGID_LPISupport(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_LPISupport_SHIFT)) & NOC_GICDA_GICDA_CFGID_LPISupport_MASK) #define NOC_GICDA_GICDA_CFGID_v41Support_MASK (0x2000U) #define NOC_GICDA_GICDA_CFGID_v41Support_SHIFT (13U) /*! v41Support - v41Support */ #define NOC_GICDA_GICDA_CFGID_v41Support(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_v41Support_SHIFT)) & NOC_GICDA_GICDA_CFGID_v41Support_MASK) #define NOC_GICDA_GICDA_CFGID_ChipAffinityLevel_MASK (0x4000U) #define NOC_GICDA_GICDA_CFGID_ChipAffinityLevel_SHIFT (14U) /*! ChipAffinityLevel - ChipAffinityLevel */ #define NOC_GICDA_GICDA_CFGID_ChipAffinityLevel(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_ChipAffinityLevel_SHIFT)) & NOC_GICDA_GICDA_CFGID_ChipAffinityLevel_MASK) #define NOC_GICDA_GICDA_CFGID_SPIGroups_MASK (0x1F8000U) #define NOC_GICDA_GICDA_CFGID_SPIGroups_SHIFT (15U) /*! SPIGroups - SPIGroups */ #define NOC_GICDA_GICDA_CFGID_SPIGroups(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_SPIGroups_SHIFT)) & NOC_GICDA_GICDA_CFGID_SPIGroups_MASK) #define NOC_GICDA_GICDA_CFGID_LocalChipAddressing_MASK (0x200000U) #define NOC_GICDA_GICDA_CFGID_LocalChipAddressing_SHIFT (21U) /*! LocalChipAddressing - LocalChipAddressing */ #define NOC_GICDA_GICDA_CFGID_LocalChipAddressing(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_LocalChipAddressing_SHIFT)) & NOC_GICDA_GICDA_CFGID_LocalChipAddressing_MASK) #define NOC_GICDA_GICDA_CFGID_RESERVED1_MASK (0xC00000U) #define NOC_GICDA_GICDA_CFGID_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_CFGID_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_CFGID_RESERVED1_MASK) #define NOC_GICDA_GICDA_CFGID_RDCollapseSupport_MASK (0x1000000U) #define NOC_GICDA_GICDA_CFGID_RDCollapseSupport_SHIFT (24U) /*! RDCollapseSupport - RDCollapseSupport */ #define NOC_GICDA_GICDA_CFGID_RDCollapseSupport(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_RDCollapseSupport_SHIFT)) & NOC_GICDA_GICDA_CFGID_RDCollapseSupport_MASK) #define NOC_GICDA_GICDA_CFGID_ExtendedITSSupport_MASK (0x2000000U) #define NOC_GICDA_GICDA_CFGID_ExtendedITSSupport_SHIFT (25U) /*! ExtendedITSSupport - ExtendedITSSupport */ #define NOC_GICDA_GICDA_CFGID_ExtendedITSSupport(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_ExtendedITSSupport_SHIFT)) & NOC_GICDA_GICDA_CFGID_ExtendedITSSupport_MASK) #define NOC_GICDA_GICDA_CFGID_RESERVED2_MASK (0xC000000U) #define NOC_GICDA_GICDA_CFGID_RESERVED2_SHIFT (26U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICDA_GICDA_CFGID_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_RESERVED2_SHIFT)) & NOC_GICDA_GICDA_CFGID_RESERVED2_MASK) #define NOC_GICDA_GICDA_CFGID_Chips_MASK (0xF0000000U) #define NOC_GICDA_GICDA_CFGID_Chips_SHIFT (28U) /*! Chips - Chips */ #define NOC_GICDA_GICDA_CFGID_Chips(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_Chips_SHIFT)) & NOC_GICDA_GICDA_CFGID_Chips_MASK) #define NOC_GICDA_GICDA_CFGID_Affinity0Bits_MASK (0xF00000000U) #define NOC_GICDA_GICDA_CFGID_Affinity0Bits_SHIFT (32U) /*! Affinity0Bits - Affinity0Bits */ #define NOC_GICDA_GICDA_CFGID_Affinity0Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_Affinity0Bits_SHIFT)) & NOC_GICDA_GICDA_CFGID_Affinity0Bits_MASK) #define NOC_GICDA_GICDA_CFGID_Affinity1Bits_MASK (0xF000000000U) #define NOC_GICDA_GICDA_CFGID_Affinity1Bits_SHIFT (36U) /*! Affinity1Bits - Affinity1Bits */ #define NOC_GICDA_GICDA_CFGID_Affinity1Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_Affinity1Bits_SHIFT)) & NOC_GICDA_GICDA_CFGID_Affinity1Bits_MASK) #define NOC_GICDA_GICDA_CFGID_Affinity2Bits_MASK (0xF0000000000U) #define NOC_GICDA_GICDA_CFGID_Affinity2Bits_SHIFT (40U) /*! Affinity2Bits - Affinity2Bits */ #define NOC_GICDA_GICDA_CFGID_Affinity2Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_Affinity2Bits_SHIFT)) & NOC_GICDA_GICDA_CFGID_Affinity2Bits_MASK) #define NOC_GICDA_GICDA_CFGID_Affinity3Bits_MASK (0xF00000000000U) #define NOC_GICDA_GICDA_CFGID_Affinity3Bits_SHIFT (44U) /*! Affinity3Bits - Affinity3Bits */ #define NOC_GICDA_GICDA_CFGID_Affinity3Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_Affinity3Bits_SHIFT)) & NOC_GICDA_GICDA_CFGID_Affinity3Bits_MASK) #define NOC_GICDA_GICDA_CFGID_PEwidth_MASK (0x1F000000000000U) #define NOC_GICDA_GICDA_CFGID_PEwidth_SHIFT (48U) /*! PEwidth - PEwidth */ #define NOC_GICDA_GICDA_CFGID_PEwidth(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_PEwidth_SHIFT)) & NOC_GICDA_GICDA_CFGID_PEwidth_MASK) #define NOC_GICDA_GICDA_CFGID_RESERVED3_MASK (0xFFE0000000000000U) #define NOC_GICDA_GICDA_CFGID_RESERVED3_SHIFT (53U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICDA_GICDA_CFGID_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICDA_GICDA_CFGID_RESERVED3_SHIFT)) & NOC_GICDA_GICDA_CFGID_RESERVED3_MASK) /*! @} */ /*! @name GICDA_PIDR4 - GICDA_PIDR4 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR4_DES_2_MASK (0xFU) #define NOC_GICDA_GICDA_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICDA_GICDA_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR4_DES_2_SHIFT)) & NOC_GICDA_GICDA_PIDR4_DES_2_MASK) #define NOC_GICDA_GICDA_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICDA_GICDA_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICDA_GICDA_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR4_SIZE_SHIFT)) & NOC_GICDA_GICDA_PIDR4_SIZE_MASK) #define NOC_GICDA_GICDA_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR4_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICDA_PIDR5 - GICDA_PIDR5 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICDA_GICDA_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICDA_GICDA_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR5_RESERVED_SHIFT)) & NOC_GICDA_GICDA_PIDR5_RESERVED_MASK) #define NOC_GICDA_GICDA_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR5_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICDA_PIDR6 - GICDA_PIDR6 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICDA_GICDA_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICDA_GICDA_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR6_RESERVED_SHIFT)) & NOC_GICDA_GICDA_PIDR6_RESERVED_MASK) #define NOC_GICDA_GICDA_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR6_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICDA_PIDR7 - GICDA_PIDR7 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICDA_GICDA_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICDA_GICDA_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR7_RESERVED_SHIFT)) & NOC_GICDA_GICDA_PIDR7_RESERVED_MASK) #define NOC_GICDA_GICDA_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR7_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICDA_PIDR0 - GICDA_PIDR0 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICDA_GICDA_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICDA_GICDA_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR0_PART_0_SHIFT)) & NOC_GICDA_GICDA_PIDR0_PART_0_MASK) #define NOC_GICDA_GICDA_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR0_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICDA_PIDR1 - GICDA_PIDR1 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR1_PART_1_MASK (0xFU) #define NOC_GICDA_GICDA_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICDA_GICDA_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR1_PART_1_SHIFT)) & NOC_GICDA_GICDA_PIDR1_PART_1_MASK) #define NOC_GICDA_GICDA_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICDA_GICDA_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICDA_GICDA_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR1_DES_0_SHIFT)) & NOC_GICDA_GICDA_PIDR1_DES_0_MASK) #define NOC_GICDA_GICDA_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR1_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICDA_PIDR2 - GICDA_PIDR2 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR2_DES_1_MASK (0x7U) #define NOC_GICDA_GICDA_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICDA_GICDA_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR2_DES_1_SHIFT)) & NOC_GICDA_GICDA_PIDR2_DES_1_MASK) #define NOC_GICDA_GICDA_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICDA_GICDA_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICDA_GICDA_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR2_JEDEC_SHIFT)) & NOC_GICDA_GICDA_PIDR2_JEDEC_MASK) #define NOC_GICDA_GICDA_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICDA_GICDA_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICDA_GICDA_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR2_REVISION_SHIFT)) & NOC_GICDA_GICDA_PIDR2_REVISION_MASK) #define NOC_GICDA_GICDA_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR2_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICDA_PIDR3 - GICDA_PIDR3 */ /*! @{ */ #define NOC_GICDA_GICDA_PIDR3_CMOD_MASK (0x7U) #define NOC_GICDA_GICDA_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICDA_GICDA_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR3_CMOD_SHIFT)) & NOC_GICDA_GICDA_PIDR3_CMOD_MASK) #define NOC_GICDA_GICDA_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICDA_GICDA_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR3_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_PIDR3_RESERVED0_MASK) #define NOC_GICDA_GICDA_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICDA_GICDA_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICDA_GICDA_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR3_REVAND_SHIFT)) & NOC_GICDA_GICDA_PIDR3_REVAND_MASK) #define NOC_GICDA_GICDA_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICDA_GICDA_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_PIDR3_RESERVED1_SHIFT)) & NOC_GICDA_GICDA_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICDA_CIDR0 - GICDA_CIDR0 */ /*! @{ */ #define NOC_GICDA_GICDA_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICDA_GICDA_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICDA_GICDA_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR0_PRMBL_0_SHIFT)) & NOC_GICDA_GICDA_CIDR0_PRMBL_0_MASK) #define NOC_GICDA_GICDA_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR0_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICDA_CIDR1 - GICDA_CIDR1 */ /*! @{ */ #define NOC_GICDA_GICDA_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICDA_GICDA_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICDA_GICDA_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR1_PRMBL_1_SHIFT)) & NOC_GICDA_GICDA_CIDR1_PRMBL_1_MASK) #define NOC_GICDA_GICDA_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICDA_GICDA_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICDA_GICDA_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR1_CLASS_SHIFT)) & NOC_GICDA_GICDA_CIDR1_CLASS_MASK) #define NOC_GICDA_GICDA_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR1_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICDA_CIDR2 - GICDA_CIDR2 */ /*! @{ */ #define NOC_GICDA_GICDA_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICDA_GICDA_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICDA_GICDA_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR2_PRMBL_2_SHIFT)) & NOC_GICDA_GICDA_CIDR2_PRMBL_2_MASK) #define NOC_GICDA_GICDA_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR2_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICDA_CIDR3 - GICDA_CIDR3 */ /*! @{ */ #define NOC_GICDA_GICDA_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICDA_GICDA_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICDA_GICDA_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR3_PRMBL_3_SHIFT)) & NOC_GICDA_GICDA_CIDR3_PRMBL_3_MASK) #define NOC_GICDA_GICDA_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICDA_GICDA_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICDA_GICDA_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICDA_GICDA_CIDR3_RESERVED0_SHIFT)) & NOC_GICDA_GICDA_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICDA_Register_Masks */ /* NOC_GICDA - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICDA base address */ #define NOC__GIC__GICDA_BASE (0x48120000u) /** Peripheral NOC__GIC__GICDA base pointer */ #define NOC__GIC__GICDA ((NOC_GICDA_Type *)NOC__GIC__GICDA_BASE) /** Array initializer of NOC_GICDA peripheral base addresses */ #define NOC_GICDA_BASE_ADDRS { NOC__GIC__GICDA_BASE } /** Array initializer of NOC_GICDA peripheral base pointers */ #define NOC_GICDA_BASE_PTRS { NOC__GIC__GICDA } /*! * @} */ /* end of group NOC_GICDA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICP_Peripheral_Access_Layer NOC_GICP Peripheral Access Layer * @{ */ /** NOC_GICP - Register Layout Typedef */ typedef struct { __IO uint32_t GICP_EVCNTR0; /**< GICP_EVCNTR0, offset: 0x0 */ __IO uint32_t GICP_EVCNTR1; /**< GICP_EVCNTR1, offset: 0x4 */ __IO uint32_t GICP_EVCNTR2; /**< GICP_EVCNTR2, offset: 0x8 */ __IO uint32_t GICP_EVCNTR3; /**< GICP_EVCNTR3, offset: 0xC */ __IO uint32_t GICP_EVCNTR4; /**< GICP_EVCNTR4, offset: 0x10 */ uint8_t RESERVED_0[1004]; __IO uint32_t GICP_EVTYPER0; /**< GICP_EVTYPER0, offset: 0x400 */ __IO uint32_t GICP_EVTYPER1; /**< GICP_EVTYPER1, offset: 0x404 */ __IO uint32_t GICP_EVTYPER2; /**< GICP_EVTYPER2, offset: 0x408 */ __IO uint32_t GICP_EVTYPER3; /**< GICP_EVTYPER3, offset: 0x40C */ __IO uint32_t GICP_EVTYPER4; /**< GICP_EVTYPER4, offset: 0x410 */ uint8_t RESERVED_1[492]; __I uint32_t GICP_SVR0; /**< GICP_SVR0, offset: 0x600 */ __I uint32_t GICP_SVR1; /**< GICP_SVR1, offset: 0x604 */ __I uint32_t GICP_SVR2; /**< GICP_SVR2, offset: 0x608 */ __I uint32_t GICP_SVR3; /**< GICP_SVR3, offset: 0x60C */ __I uint32_t GICP_SVR4; /**< GICP_SVR4, offset: 0x610 */ uint8_t RESERVED_2[1004]; __IO uint32_t GICP_FR0; /**< GICP_FR0, offset: 0xA00 */ __IO uint32_t GICP_FR1; /**< GICP_FR1, offset: 0xA04 */ __IO uint32_t GICP_FR2; /**< GICP_FR2, offset: 0xA08 */ __IO uint32_t GICP_FR3; /**< GICP_FR3, offset: 0xA0C */ __IO uint32_t GICP_FR4; /**< GICP_FR4, offset: 0xA10 */ uint8_t RESERVED_3[492]; __IO uint64_t GICP_CNTENSET0; /**< GICP_CNTENSET0, offset: 0xC00 */ uint8_t RESERVED_4[24]; __IO uint64_t GICP_CNTENCLR0; /**< GICP_CNTENCLR0, offset: 0xC20 */ uint8_t RESERVED_5[24]; __IO uint64_t GICP_INTENSET0; /**< GICP_INTENSET0, offset: 0xC40 */ uint8_t RESERVED_6[24]; __IO uint64_t GICP_INTENCLR0; /**< GICP_INTENCLR0, offset: 0xC60 */ uint8_t RESERVED_7[24]; __IO uint64_t GICP_OVSCLR0; /**< GICP_OVSCLR0, offset: 0xC80 */ uint8_t RESERVED_8[56]; __IO uint64_t GICP_OVSSET0; /**< GICP_OVSSET0, offset: 0xCC0 */ uint8_t RESERVED_9[192]; __O uint32_t GICP_CAPR; /**< GICP_CAPR, offset: 0xD88 */ uint8_t RESERVED_10[116]; __I uint32_t GICP_CFGR; /**< GICP_CFGR, offset: 0xE00 */ __IO uint32_t GICP_CR; /**< GICP_CR, offset: 0xE04 */ uint8_t RESERVED_11[72]; __IO uint32_t GICP_IRQCR; /**< GICP_IRQCR, offset: 0xE50 */ uint8_t RESERVED_12[356]; __I uint32_t GICP_PMAUTHSTATUS; /**< GICP_PMAUTHSTATUS, offset: 0xFB8 */ __I uint32_t GICP_PMDEVARCH; /**< GICP_PMDEVARCH, offset: 0xFBC */ uint8_t RESERVED_13[12]; __I uint32_t GICP_PMDEVTYPE; /**< GICP_PMDEVTYPE, offset: 0xFCC */ __I uint32_t GICP_PIDR4; /**< GICP_PIDR4, offset: 0xFD0 */ __I uint32_t GICP_PIDR5; /**< GICP_PIDR5, offset: 0xFD4 */ __I uint32_t GICP_PIDR6; /**< GICP_PIDR6, offset: 0xFD8 */ __I uint32_t GICP_PIDR7; /**< GICP_PIDR7, offset: 0xFDC */ __I uint32_t GICP_PIDR0; /**< GICP_PIDR0, offset: 0xFE0 */ __I uint32_t GICP_PIDR1; /**< GICP_PIDR1, offset: 0xFE4 */ __I uint32_t GICP_PIDR2; /**< GICP_PIDR2, offset: 0xFE8 */ __I uint32_t GICP_PIDR3; /**< GICP_PIDR3, offset: 0xFEC */ __I uint32_t GICP_CIDR0; /**< GICP_CIDR0, offset: 0xFF0 */ __I uint32_t GICP_CIDR1; /**< GICP_CIDR1, offset: 0xFF4 */ __I uint32_t GICP_CIDR2; /**< GICP_CIDR2, offset: 0xFF8 */ __I uint32_t GICP_CIDR3; /**< GICP_CIDR3, offset: 0xFFC */ } NOC_GICP_Type; /* ---------------------------------------------------------------------------- -- NOC_GICP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICP_Register_Masks NOC_GICP Register Masks * @{ */ /*! @name GICP_EVCNTR0 - GICP_EVCNTR0 */ /*! @{ */ #define NOC_GICP_GICP_EVCNTR0_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_EVCNTR0_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_EVCNTR0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVCNTR0_COUNT_SHIFT)) & NOC_GICP_GICP_EVCNTR0_COUNT_MASK) /*! @} */ /*! @name GICP_EVCNTR1 - GICP_EVCNTR1 */ /*! @{ */ #define NOC_GICP_GICP_EVCNTR1_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_EVCNTR1_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_EVCNTR1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVCNTR1_COUNT_SHIFT)) & NOC_GICP_GICP_EVCNTR1_COUNT_MASK) /*! @} */ /*! @name GICP_EVCNTR2 - GICP_EVCNTR2 */ /*! @{ */ #define NOC_GICP_GICP_EVCNTR2_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_EVCNTR2_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_EVCNTR2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVCNTR2_COUNT_SHIFT)) & NOC_GICP_GICP_EVCNTR2_COUNT_MASK) /*! @} */ /*! @name GICP_EVCNTR3 - GICP_EVCNTR3 */ /*! @{ */ #define NOC_GICP_GICP_EVCNTR3_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_EVCNTR3_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_EVCNTR3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVCNTR3_COUNT_SHIFT)) & NOC_GICP_GICP_EVCNTR3_COUNT_MASK) /*! @} */ /*! @name GICP_EVCNTR4 - GICP_EVCNTR4 */ /*! @{ */ #define NOC_GICP_GICP_EVCNTR4_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_EVCNTR4_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_EVCNTR4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVCNTR4_COUNT_SHIFT)) & NOC_GICP_GICP_EVCNTR4_COUNT_MASK) /*! @} */ /*! @name GICP_EVTYPER0 - GICP_EVTYPER0 */ /*! @{ */ #define NOC_GICP_GICP_EVTYPER0_EVENT_MASK (0xFFU) #define NOC_GICP_GICP_EVTYPER0_EVENT_SHIFT (0U) /*! EVENT - EVENT */ #define NOC_GICP_GICP_EVTYPER0_EVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER0_EVENT_SHIFT)) & NOC_GICP_GICP_EVTYPER0_EVENT_MASK) #define NOC_GICP_GICP_EVTYPER0_RESERVED0_MASK (0xFF00U) #define NOC_GICP_GICP_EVTYPER0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_EVTYPER0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER0_RESERVED0_SHIFT)) & NOC_GICP_GICP_EVTYPER0_RESERVED0_MASK) #define NOC_GICP_GICP_EVTYPER0_EVENT_TYPE_MASK (0x30000U) #define NOC_GICP_GICP_EVTYPER0_EVENT_TYPE_SHIFT (16U) /*! EVENT_TYPE - EVENT_TYPE */ #define NOC_GICP_GICP_EVTYPER0_EVENT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER0_EVENT_TYPE_SHIFT)) & NOC_GICP_GICP_EVTYPER0_EVENT_TYPE_MASK) #define NOC_GICP_GICP_EVTYPER0_RESERVED1_MASK (0x7FFC0000U) #define NOC_GICP_GICP_EVTYPER0_RESERVED1_SHIFT (18U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICP_GICP_EVTYPER0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER0_RESERVED1_SHIFT)) & NOC_GICP_GICP_EVTYPER0_RESERVED1_MASK) #define NOC_GICP_GICP_EVTYPER0_OVCAP_MASK (0x80000000U) #define NOC_GICP_GICP_EVTYPER0_OVCAP_SHIFT (31U) /*! OVCAP - OVCAP */ #define NOC_GICP_GICP_EVTYPER0_OVCAP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER0_OVCAP_SHIFT)) & NOC_GICP_GICP_EVTYPER0_OVCAP_MASK) /*! @} */ /*! @name GICP_EVTYPER1 - GICP_EVTYPER1 */ /*! @{ */ #define NOC_GICP_GICP_EVTYPER1_EVENT_MASK (0xFFU) #define NOC_GICP_GICP_EVTYPER1_EVENT_SHIFT (0U) /*! EVENT - EVENT */ #define NOC_GICP_GICP_EVTYPER1_EVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER1_EVENT_SHIFT)) & NOC_GICP_GICP_EVTYPER1_EVENT_MASK) #define NOC_GICP_GICP_EVTYPER1_RESERVED0_MASK (0xFF00U) #define NOC_GICP_GICP_EVTYPER1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_EVTYPER1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER1_RESERVED0_SHIFT)) & NOC_GICP_GICP_EVTYPER1_RESERVED0_MASK) #define NOC_GICP_GICP_EVTYPER1_EVENT_TYPE_MASK (0x30000U) #define NOC_GICP_GICP_EVTYPER1_EVENT_TYPE_SHIFT (16U) /*! EVENT_TYPE - EVENT_TYPE */ #define NOC_GICP_GICP_EVTYPER1_EVENT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER1_EVENT_TYPE_SHIFT)) & NOC_GICP_GICP_EVTYPER1_EVENT_TYPE_MASK) #define NOC_GICP_GICP_EVTYPER1_RESERVED1_MASK (0x7FFC0000U) #define NOC_GICP_GICP_EVTYPER1_RESERVED1_SHIFT (18U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICP_GICP_EVTYPER1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER1_RESERVED1_SHIFT)) & NOC_GICP_GICP_EVTYPER1_RESERVED1_MASK) #define NOC_GICP_GICP_EVTYPER1_OVCAP_MASK (0x80000000U) #define NOC_GICP_GICP_EVTYPER1_OVCAP_SHIFT (31U) /*! OVCAP - OVCAP */ #define NOC_GICP_GICP_EVTYPER1_OVCAP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER1_OVCAP_SHIFT)) & NOC_GICP_GICP_EVTYPER1_OVCAP_MASK) /*! @} */ /*! @name GICP_EVTYPER2 - GICP_EVTYPER2 */ /*! @{ */ #define NOC_GICP_GICP_EVTYPER2_EVENT_MASK (0xFFU) #define NOC_GICP_GICP_EVTYPER2_EVENT_SHIFT (0U) /*! EVENT - EVENT */ #define NOC_GICP_GICP_EVTYPER2_EVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER2_EVENT_SHIFT)) & NOC_GICP_GICP_EVTYPER2_EVENT_MASK) #define NOC_GICP_GICP_EVTYPER2_RESERVED0_MASK (0xFF00U) #define NOC_GICP_GICP_EVTYPER2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_EVTYPER2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER2_RESERVED0_SHIFT)) & NOC_GICP_GICP_EVTYPER2_RESERVED0_MASK) #define NOC_GICP_GICP_EVTYPER2_EVENT_TYPE_MASK (0x30000U) #define NOC_GICP_GICP_EVTYPER2_EVENT_TYPE_SHIFT (16U) /*! EVENT_TYPE - EVENT_TYPE */ #define NOC_GICP_GICP_EVTYPER2_EVENT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER2_EVENT_TYPE_SHIFT)) & NOC_GICP_GICP_EVTYPER2_EVENT_TYPE_MASK) #define NOC_GICP_GICP_EVTYPER2_RESERVED1_MASK (0x7FFC0000U) #define NOC_GICP_GICP_EVTYPER2_RESERVED1_SHIFT (18U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICP_GICP_EVTYPER2_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER2_RESERVED1_SHIFT)) & NOC_GICP_GICP_EVTYPER2_RESERVED1_MASK) #define NOC_GICP_GICP_EVTYPER2_OVCAP_MASK (0x80000000U) #define NOC_GICP_GICP_EVTYPER2_OVCAP_SHIFT (31U) /*! OVCAP - OVCAP */ #define NOC_GICP_GICP_EVTYPER2_OVCAP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER2_OVCAP_SHIFT)) & NOC_GICP_GICP_EVTYPER2_OVCAP_MASK) /*! @} */ /*! @name GICP_EVTYPER3 - GICP_EVTYPER3 */ /*! @{ */ #define NOC_GICP_GICP_EVTYPER3_EVENT_MASK (0xFFU) #define NOC_GICP_GICP_EVTYPER3_EVENT_SHIFT (0U) /*! EVENT - EVENT */ #define NOC_GICP_GICP_EVTYPER3_EVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER3_EVENT_SHIFT)) & NOC_GICP_GICP_EVTYPER3_EVENT_MASK) #define NOC_GICP_GICP_EVTYPER3_RESERVED0_MASK (0xFF00U) #define NOC_GICP_GICP_EVTYPER3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_EVTYPER3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER3_RESERVED0_SHIFT)) & NOC_GICP_GICP_EVTYPER3_RESERVED0_MASK) #define NOC_GICP_GICP_EVTYPER3_EVENT_TYPE_MASK (0x30000U) #define NOC_GICP_GICP_EVTYPER3_EVENT_TYPE_SHIFT (16U) /*! EVENT_TYPE - EVENT_TYPE */ #define NOC_GICP_GICP_EVTYPER3_EVENT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER3_EVENT_TYPE_SHIFT)) & NOC_GICP_GICP_EVTYPER3_EVENT_TYPE_MASK) #define NOC_GICP_GICP_EVTYPER3_RESERVED1_MASK (0x7FFC0000U) #define NOC_GICP_GICP_EVTYPER3_RESERVED1_SHIFT (18U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICP_GICP_EVTYPER3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER3_RESERVED1_SHIFT)) & NOC_GICP_GICP_EVTYPER3_RESERVED1_MASK) #define NOC_GICP_GICP_EVTYPER3_OVCAP_MASK (0x80000000U) #define NOC_GICP_GICP_EVTYPER3_OVCAP_SHIFT (31U) /*! OVCAP - OVCAP */ #define NOC_GICP_GICP_EVTYPER3_OVCAP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER3_OVCAP_SHIFT)) & NOC_GICP_GICP_EVTYPER3_OVCAP_MASK) /*! @} */ /*! @name GICP_EVTYPER4 - GICP_EVTYPER4 */ /*! @{ */ #define NOC_GICP_GICP_EVTYPER4_EVENT_MASK (0xFFU) #define NOC_GICP_GICP_EVTYPER4_EVENT_SHIFT (0U) /*! EVENT - EVENT */ #define NOC_GICP_GICP_EVTYPER4_EVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER4_EVENT_SHIFT)) & NOC_GICP_GICP_EVTYPER4_EVENT_MASK) #define NOC_GICP_GICP_EVTYPER4_RESERVED0_MASK (0xFF00U) #define NOC_GICP_GICP_EVTYPER4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_EVTYPER4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER4_RESERVED0_SHIFT)) & NOC_GICP_GICP_EVTYPER4_RESERVED0_MASK) #define NOC_GICP_GICP_EVTYPER4_EVENT_TYPE_MASK (0x30000U) #define NOC_GICP_GICP_EVTYPER4_EVENT_TYPE_SHIFT (16U) /*! EVENT_TYPE - EVENT_TYPE */ #define NOC_GICP_GICP_EVTYPER4_EVENT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER4_EVENT_TYPE_SHIFT)) & NOC_GICP_GICP_EVTYPER4_EVENT_TYPE_MASK) #define NOC_GICP_GICP_EVTYPER4_RESERVED1_MASK (0x7FFC0000U) #define NOC_GICP_GICP_EVTYPER4_RESERVED1_SHIFT (18U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICP_GICP_EVTYPER4_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER4_RESERVED1_SHIFT)) & NOC_GICP_GICP_EVTYPER4_RESERVED1_MASK) #define NOC_GICP_GICP_EVTYPER4_OVCAP_MASK (0x80000000U) #define NOC_GICP_GICP_EVTYPER4_OVCAP_SHIFT (31U) /*! OVCAP - OVCAP */ #define NOC_GICP_GICP_EVTYPER4_OVCAP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_EVTYPER4_OVCAP_SHIFT)) & NOC_GICP_GICP_EVTYPER4_OVCAP_MASK) /*! @} */ /*! @name GICP_SVR0 - GICP_SVR0 */ /*! @{ */ #define NOC_GICP_GICP_SVR0_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_SVR0_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_SVR0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_SVR0_COUNT_SHIFT)) & NOC_GICP_GICP_SVR0_COUNT_MASK) /*! @} */ /*! @name GICP_SVR1 - GICP_SVR1 */ /*! @{ */ #define NOC_GICP_GICP_SVR1_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_SVR1_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_SVR1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_SVR1_COUNT_SHIFT)) & NOC_GICP_GICP_SVR1_COUNT_MASK) /*! @} */ /*! @name GICP_SVR2 - GICP_SVR2 */ /*! @{ */ #define NOC_GICP_GICP_SVR2_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_SVR2_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_SVR2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_SVR2_COUNT_SHIFT)) & NOC_GICP_GICP_SVR2_COUNT_MASK) /*! @} */ /*! @name GICP_SVR3 - GICP_SVR3 */ /*! @{ */ #define NOC_GICP_GICP_SVR3_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_SVR3_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_SVR3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_SVR3_COUNT_SHIFT)) & NOC_GICP_GICP_SVR3_COUNT_MASK) /*! @} */ /*! @name GICP_SVR4 - GICP_SVR4 */ /*! @{ */ #define NOC_GICP_GICP_SVR4_COUNT_MASK (0xFFFFFFFFU) #define NOC_GICP_GICP_SVR4_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define NOC_GICP_GICP_SVR4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_SVR4_COUNT_SHIFT)) & NOC_GICP_GICP_SVR4_COUNT_MASK) /*! @} */ /*! @name GICP_FR0 - GICP_FR0 */ /*! @{ */ #define NOC_GICP_GICP_FR0_Filter_MASK (0xFFFFU) #define NOC_GICP_GICP_FR0_Filter_SHIFT (0U) /*! Filter - Filter */ #define NOC_GICP_GICP_FR0_Filter(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR0_Filter_SHIFT)) & NOC_GICP_GICP_FR0_Filter_MASK) #define NOC_GICP_GICP_FR0_RESERVED0_MASK (0x1FFF0000U) #define NOC_GICP_GICP_FR0_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_FR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR0_RESERVED0_SHIFT)) & NOC_GICP_GICP_FR0_RESERVED0_MASK) #define NOC_GICP_GICP_FR0_FilterEncoding_MASK (0x20000000U) #define NOC_GICP_GICP_FR0_FilterEncoding_SHIFT (29U) /*! FilterEncoding - FilterEncoding */ #define NOC_GICP_GICP_FR0_FilterEncoding(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR0_FilterEncoding_SHIFT)) & NOC_GICP_GICP_FR0_FilterEncoding_MASK) #define NOC_GICP_GICP_FR0_FilterType_MASK (0xC0000000U) #define NOC_GICP_GICP_FR0_FilterType_SHIFT (30U) /*! FilterType - FilterType */ #define NOC_GICP_GICP_FR0_FilterType(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR0_FilterType_SHIFT)) & NOC_GICP_GICP_FR0_FilterType_MASK) /*! @} */ /*! @name GICP_FR1 - GICP_FR1 */ /*! @{ */ #define NOC_GICP_GICP_FR1_Filter_MASK (0xFFFFU) #define NOC_GICP_GICP_FR1_Filter_SHIFT (0U) /*! Filter - Filter */ #define NOC_GICP_GICP_FR1_Filter(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR1_Filter_SHIFT)) & NOC_GICP_GICP_FR1_Filter_MASK) #define NOC_GICP_GICP_FR1_RESERVED0_MASK (0x1FFF0000U) #define NOC_GICP_GICP_FR1_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_FR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR1_RESERVED0_SHIFT)) & NOC_GICP_GICP_FR1_RESERVED0_MASK) #define NOC_GICP_GICP_FR1_FilterEncoding_MASK (0x20000000U) #define NOC_GICP_GICP_FR1_FilterEncoding_SHIFT (29U) /*! FilterEncoding - FilterEncoding */ #define NOC_GICP_GICP_FR1_FilterEncoding(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR1_FilterEncoding_SHIFT)) & NOC_GICP_GICP_FR1_FilterEncoding_MASK) #define NOC_GICP_GICP_FR1_FilterType_MASK (0xC0000000U) #define NOC_GICP_GICP_FR1_FilterType_SHIFT (30U) /*! FilterType - FilterType */ #define NOC_GICP_GICP_FR1_FilterType(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR1_FilterType_SHIFT)) & NOC_GICP_GICP_FR1_FilterType_MASK) /*! @} */ /*! @name GICP_FR2 - GICP_FR2 */ /*! @{ */ #define NOC_GICP_GICP_FR2_Filter_MASK (0xFFFFU) #define NOC_GICP_GICP_FR2_Filter_SHIFT (0U) /*! Filter - Filter */ #define NOC_GICP_GICP_FR2_Filter(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR2_Filter_SHIFT)) & NOC_GICP_GICP_FR2_Filter_MASK) #define NOC_GICP_GICP_FR2_RESERVED0_MASK (0x1FFF0000U) #define NOC_GICP_GICP_FR2_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_FR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR2_RESERVED0_SHIFT)) & NOC_GICP_GICP_FR2_RESERVED0_MASK) #define NOC_GICP_GICP_FR2_FilterEncoding_MASK (0x20000000U) #define NOC_GICP_GICP_FR2_FilterEncoding_SHIFT (29U) /*! FilterEncoding - FilterEncoding */ #define NOC_GICP_GICP_FR2_FilterEncoding(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR2_FilterEncoding_SHIFT)) & NOC_GICP_GICP_FR2_FilterEncoding_MASK) #define NOC_GICP_GICP_FR2_FilterType_MASK (0xC0000000U) #define NOC_GICP_GICP_FR2_FilterType_SHIFT (30U) /*! FilterType - FilterType */ #define NOC_GICP_GICP_FR2_FilterType(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR2_FilterType_SHIFT)) & NOC_GICP_GICP_FR2_FilterType_MASK) /*! @} */ /*! @name GICP_FR3 - GICP_FR3 */ /*! @{ */ #define NOC_GICP_GICP_FR3_Filter_MASK (0xFFFFU) #define NOC_GICP_GICP_FR3_Filter_SHIFT (0U) /*! Filter - Filter */ #define NOC_GICP_GICP_FR3_Filter(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR3_Filter_SHIFT)) & NOC_GICP_GICP_FR3_Filter_MASK) #define NOC_GICP_GICP_FR3_RESERVED0_MASK (0x1FFF0000U) #define NOC_GICP_GICP_FR3_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_FR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR3_RESERVED0_SHIFT)) & NOC_GICP_GICP_FR3_RESERVED0_MASK) #define NOC_GICP_GICP_FR3_FilterEncoding_MASK (0x20000000U) #define NOC_GICP_GICP_FR3_FilterEncoding_SHIFT (29U) /*! FilterEncoding - FilterEncoding */ #define NOC_GICP_GICP_FR3_FilterEncoding(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR3_FilterEncoding_SHIFT)) & NOC_GICP_GICP_FR3_FilterEncoding_MASK) #define NOC_GICP_GICP_FR3_FilterType_MASK (0xC0000000U) #define NOC_GICP_GICP_FR3_FilterType_SHIFT (30U) /*! FilterType - FilterType */ #define NOC_GICP_GICP_FR3_FilterType(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR3_FilterType_SHIFT)) & NOC_GICP_GICP_FR3_FilterType_MASK) /*! @} */ /*! @name GICP_FR4 - GICP_FR4 */ /*! @{ */ #define NOC_GICP_GICP_FR4_Filter_MASK (0xFFFFU) #define NOC_GICP_GICP_FR4_Filter_SHIFT (0U) /*! Filter - Filter */ #define NOC_GICP_GICP_FR4_Filter(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR4_Filter_SHIFT)) & NOC_GICP_GICP_FR4_Filter_MASK) #define NOC_GICP_GICP_FR4_RESERVED0_MASK (0x1FFF0000U) #define NOC_GICP_GICP_FR4_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_FR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR4_RESERVED0_SHIFT)) & NOC_GICP_GICP_FR4_RESERVED0_MASK) #define NOC_GICP_GICP_FR4_FilterEncoding_MASK (0x20000000U) #define NOC_GICP_GICP_FR4_FilterEncoding_SHIFT (29U) /*! FilterEncoding - FilterEncoding */ #define NOC_GICP_GICP_FR4_FilterEncoding(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR4_FilterEncoding_SHIFT)) & NOC_GICP_GICP_FR4_FilterEncoding_MASK) #define NOC_GICP_GICP_FR4_FilterType_MASK (0xC0000000U) #define NOC_GICP_GICP_FR4_FilterType_SHIFT (30U) /*! FilterType - FilterType */ #define NOC_GICP_GICP_FR4_FilterType(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_FR4_FilterType_SHIFT)) & NOC_GICP_GICP_FR4_FilterType_MASK) /*! @} */ /*! @name GICP_CNTENSET0 - GICP_CNTENSET0 */ /*! @{ */ #define NOC_GICP_GICP_CNTENSET0_CNTEN0_MASK (0x1U) #define NOC_GICP_GICP_CNTENSET0_CNTEN0_SHIFT (0U) /*! CNTEN0 - CNTEN0 */ #define NOC_GICP_GICP_CNTENSET0_CNTEN0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENSET0_CNTEN0_SHIFT)) & NOC_GICP_GICP_CNTENSET0_CNTEN0_MASK) #define NOC_GICP_GICP_CNTENSET0_CNTEN1_MASK (0x2U) #define NOC_GICP_GICP_CNTENSET0_CNTEN1_SHIFT (1U) /*! CNTEN1 - CNTEN1 */ #define NOC_GICP_GICP_CNTENSET0_CNTEN1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENSET0_CNTEN1_SHIFT)) & NOC_GICP_GICP_CNTENSET0_CNTEN1_MASK) #define NOC_GICP_GICP_CNTENSET0_CNTEN2_MASK (0x4U) #define NOC_GICP_GICP_CNTENSET0_CNTEN2_SHIFT (2U) /*! CNTEN2 - CNTEN2 */ #define NOC_GICP_GICP_CNTENSET0_CNTEN2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENSET0_CNTEN2_SHIFT)) & NOC_GICP_GICP_CNTENSET0_CNTEN2_MASK) #define NOC_GICP_GICP_CNTENSET0_CNTEN3_MASK (0x8U) #define NOC_GICP_GICP_CNTENSET0_CNTEN3_SHIFT (3U) /*! CNTEN3 - CNTEN3 */ #define NOC_GICP_GICP_CNTENSET0_CNTEN3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENSET0_CNTEN3_SHIFT)) & NOC_GICP_GICP_CNTENSET0_CNTEN3_MASK) #define NOC_GICP_GICP_CNTENSET0_CNTEN4_MASK (0x10U) #define NOC_GICP_GICP_CNTENSET0_CNTEN4_SHIFT (4U) /*! CNTEN4 - CNTEN4 */ #define NOC_GICP_GICP_CNTENSET0_CNTEN4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENSET0_CNTEN4_SHIFT)) & NOC_GICP_GICP_CNTENSET0_CNTEN4_MASK) #define NOC_GICP_GICP_CNTENSET0_RESERVED0_MASK (0xFFFFFFFFFFFFFFE0U) #define NOC_GICP_GICP_CNTENSET0_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CNTENSET0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENSET0_RESERVED0_SHIFT)) & NOC_GICP_GICP_CNTENSET0_RESERVED0_MASK) /*! @} */ /*! @name GICP_CNTENCLR0 - GICP_CNTENCLR0 */ /*! @{ */ #define NOC_GICP_GICP_CNTENCLR0_CNTEN0_MASK (0x1U) #define NOC_GICP_GICP_CNTENCLR0_CNTEN0_SHIFT (0U) /*! CNTEN0 - CNTEN0 */ #define NOC_GICP_GICP_CNTENCLR0_CNTEN0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENCLR0_CNTEN0_SHIFT)) & NOC_GICP_GICP_CNTENCLR0_CNTEN0_MASK) #define NOC_GICP_GICP_CNTENCLR0_CNTEN1_MASK (0x2U) #define NOC_GICP_GICP_CNTENCLR0_CNTEN1_SHIFT (1U) /*! CNTEN1 - CNTEN1 */ #define NOC_GICP_GICP_CNTENCLR0_CNTEN1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENCLR0_CNTEN1_SHIFT)) & NOC_GICP_GICP_CNTENCLR0_CNTEN1_MASK) #define NOC_GICP_GICP_CNTENCLR0_CNTEN2_MASK (0x4U) #define NOC_GICP_GICP_CNTENCLR0_CNTEN2_SHIFT (2U) /*! CNTEN2 - CNTEN2 */ #define NOC_GICP_GICP_CNTENCLR0_CNTEN2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENCLR0_CNTEN2_SHIFT)) & NOC_GICP_GICP_CNTENCLR0_CNTEN2_MASK) #define NOC_GICP_GICP_CNTENCLR0_CNTEN3_MASK (0x8U) #define NOC_GICP_GICP_CNTENCLR0_CNTEN3_SHIFT (3U) /*! CNTEN3 - CNTEN3 */ #define NOC_GICP_GICP_CNTENCLR0_CNTEN3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENCLR0_CNTEN3_SHIFT)) & NOC_GICP_GICP_CNTENCLR0_CNTEN3_MASK) #define NOC_GICP_GICP_CNTENCLR0_CNTEN4_MASK (0x10U) #define NOC_GICP_GICP_CNTENCLR0_CNTEN4_SHIFT (4U) /*! CNTEN4 - CNTEN4 */ #define NOC_GICP_GICP_CNTENCLR0_CNTEN4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENCLR0_CNTEN4_SHIFT)) & NOC_GICP_GICP_CNTENCLR0_CNTEN4_MASK) #define NOC_GICP_GICP_CNTENCLR0_RESERVED0_MASK (0xFFFFFFFFFFFFFFE0U) #define NOC_GICP_GICP_CNTENCLR0_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CNTENCLR0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_CNTENCLR0_RESERVED0_SHIFT)) & NOC_GICP_GICP_CNTENCLR0_RESERVED0_MASK) /*! @} */ /*! @name GICP_INTENSET0 - GICP_INTENSET0 */ /*! @{ */ #define NOC_GICP_GICP_INTENSET0_INTEN_MASK (0x1FU) #define NOC_GICP_GICP_INTENSET0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define NOC_GICP_GICP_INTENSET0_INTEN(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_INTENSET0_INTEN_SHIFT)) & NOC_GICP_GICP_INTENSET0_INTEN_MASK) #define NOC_GICP_GICP_INTENSET0_RESERVED0_MASK (0xFFFFFFFFFFFFFFE0U) #define NOC_GICP_GICP_INTENSET0_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_INTENSET0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_INTENSET0_RESERVED0_SHIFT)) & NOC_GICP_GICP_INTENSET0_RESERVED0_MASK) /*! @} */ /*! @name GICP_INTENCLR0 - GICP_INTENCLR0 */ /*! @{ */ #define NOC_GICP_GICP_INTENCLR0_INTEN_MASK (0x1FU) #define NOC_GICP_GICP_INTENCLR0_INTEN_SHIFT (0U) /*! INTEN - INTEN */ #define NOC_GICP_GICP_INTENCLR0_INTEN(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_INTENCLR0_INTEN_SHIFT)) & NOC_GICP_GICP_INTENCLR0_INTEN_MASK) #define NOC_GICP_GICP_INTENCLR0_RESERVED0_MASK (0xFFFFFFFFFFFFFFE0U) #define NOC_GICP_GICP_INTENCLR0_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_INTENCLR0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_INTENCLR0_RESERVED0_SHIFT)) & NOC_GICP_GICP_INTENCLR0_RESERVED0_MASK) /*! @} */ /*! @name GICP_OVSCLR0 - GICP_OVSCLR0 */ /*! @{ */ #define NOC_GICP_GICP_OVSCLR0_OVS_MASK (0x1FU) #define NOC_GICP_GICP_OVSCLR0_OVS_SHIFT (0U) /*! OVS - OVS */ #define NOC_GICP_GICP_OVSCLR0_OVS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_OVSCLR0_OVS_SHIFT)) & NOC_GICP_GICP_OVSCLR0_OVS_MASK) #define NOC_GICP_GICP_OVSCLR0_RESERVED0_MASK (0xFFFFFFFFFFFFFFE0U) #define NOC_GICP_GICP_OVSCLR0_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_OVSCLR0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_OVSCLR0_RESERVED0_SHIFT)) & NOC_GICP_GICP_OVSCLR0_RESERVED0_MASK) /*! @} */ /*! @name GICP_OVSSET0 - GICP_OVSSET0 */ /*! @{ */ #define NOC_GICP_GICP_OVSSET0_OVS_MASK (0x1FU) #define NOC_GICP_GICP_OVSSET0_OVS_SHIFT (0U) /*! OVS - OVS */ #define NOC_GICP_GICP_OVSSET0_OVS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_OVSSET0_OVS_SHIFT)) & NOC_GICP_GICP_OVSSET0_OVS_MASK) #define NOC_GICP_GICP_OVSSET0_RESERVED0_MASK (0xFFFFFFFFFFFFFFE0U) #define NOC_GICP_GICP_OVSSET0_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_OVSSET0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICP_GICP_OVSSET0_RESERVED0_SHIFT)) & NOC_GICP_GICP_OVSSET0_RESERVED0_MASK) /*! @} */ /*! @name GICP_CAPR - GICP_CAPR */ /*! @{ */ #define NOC_GICP_GICP_CAPR_CAPTURE_MASK (0x1U) #define NOC_GICP_GICP_CAPR_CAPTURE_SHIFT (0U) /*! CAPTURE - CAPTURE */ #define NOC_GICP_GICP_CAPR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CAPR_CAPTURE_SHIFT)) & NOC_GICP_GICP_CAPR_CAPTURE_MASK) #define NOC_GICP_GICP_CAPR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICP_GICP_CAPR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CAPR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CAPR_RESERVED0_SHIFT)) & NOC_GICP_GICP_CAPR_RESERVED0_MASK) /*! @} */ /*! @name GICP_CFGR - GICP_CFGR */ /*! @{ */ #define NOC_GICP_GICP_CFGR_NCTR_MASK (0x3FU) #define NOC_GICP_GICP_CFGR_NCTR_SHIFT (0U) /*! NCTR - NCTR */ #define NOC_GICP_GICP_CFGR_NCTR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CFGR_NCTR_SHIFT)) & NOC_GICP_GICP_CFGR_NCTR_MASK) #define NOC_GICP_GICP_CFGR_RESERVED0_MASK (0xC0U) #define NOC_GICP_GICP_CFGR_RESERVED0_SHIFT (6U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CFGR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CFGR_RESERVED0_SHIFT)) & NOC_GICP_GICP_CFGR_RESERVED0_MASK) #define NOC_GICP_GICP_CFGR_SIZE_MASK (0x3F00U) #define NOC_GICP_GICP_CFGR_SIZE_SHIFT (8U) /*! SIZE - SIZE */ #define NOC_GICP_GICP_CFGR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CFGR_SIZE_SHIFT)) & NOC_GICP_GICP_CFGR_SIZE_MASK) #define NOC_GICP_GICP_CFGR_RESERVED1_MASK (0x3FC000U) #define NOC_GICP_GICP_CFGR_RESERVED1_SHIFT (14U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICP_GICP_CFGR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CFGR_RESERVED1_SHIFT)) & NOC_GICP_GICP_CFGR_RESERVED1_MASK) #define NOC_GICP_GICP_CFGR_CAPTURE_MASK (0x400000U) #define NOC_GICP_GICP_CFGR_CAPTURE_SHIFT (22U) /*! CAPTURE - CAPTURE */ #define NOC_GICP_GICP_CFGR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CFGR_CAPTURE_SHIFT)) & NOC_GICP_GICP_CFGR_CAPTURE_MASK) #define NOC_GICP_GICP_CFGR_RESERVED2_MASK (0xFF800000U) #define NOC_GICP_GICP_CFGR_RESERVED2_SHIFT (23U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICP_GICP_CFGR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CFGR_RESERVED2_SHIFT)) & NOC_GICP_GICP_CFGR_RESERVED2_MASK) /*! @} */ /*! @name GICP_CR - GICP_CR */ /*! @{ */ #define NOC_GICP_GICP_CR_E_MASK (0x1U) #define NOC_GICP_GICP_CR_E_SHIFT (0U) /*! E - E */ #define NOC_GICP_GICP_CR_E(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CR_E_SHIFT)) & NOC_GICP_GICP_CR_E_MASK) #define NOC_GICP_GICP_CR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICP_GICP_CR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CR_RESERVED0_SHIFT)) & NOC_GICP_GICP_CR_RESERVED0_MASK) /*! @} */ /*! @name GICP_IRQCR - GICP_IRQCR */ /*! @{ */ #define NOC_GICP_GICP_IRQCR_SPIID_MASK (0x1FFFU) #define NOC_GICP_GICP_IRQCR_SPIID_SHIFT (0U) /*! SPIID - SPIID */ #define NOC_GICP_GICP_IRQCR_SPIID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_IRQCR_SPIID_SHIFT)) & NOC_GICP_GICP_IRQCR_SPIID_MASK) #define NOC_GICP_GICP_IRQCR_RESERVED0_MASK (0xFFFFE000U) #define NOC_GICP_GICP_IRQCR_RESERVED0_SHIFT (13U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_IRQCR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_IRQCR_RESERVED0_SHIFT)) & NOC_GICP_GICP_IRQCR_RESERVED0_MASK) /*! @} */ /*! @name GICP_PMAUTHSTATUS - GICP_PMAUTHSTATUS */ /*! @{ */ #define NOC_GICP_GICP_PMAUTHSTATUS_NSE_MASK (0x1U) #define NOC_GICP_GICP_PMAUTHSTATUS_NSE_SHIFT (0U) /*! NSE - NSE */ #define NOC_GICP_GICP_PMAUTHSTATUS_NSE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_NSE_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_NSE_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_NSI_MASK (0x2U) #define NOC_GICP_GICP_PMAUTHSTATUS_NSI_SHIFT (1U) /*! NSI - NSI */ #define NOC_GICP_GICP_PMAUTHSTATUS_NSI(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_NSI_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_NSI_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_NSNE_MASK (0x4U) #define NOC_GICP_GICP_PMAUTHSTATUS_NSNE_SHIFT (2U) /*! NSNE - NSNE */ #define NOC_GICP_GICP_PMAUTHSTATUS_NSNE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_NSNE_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_NSNE_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_NSNI_MASK (0x8U) #define NOC_GICP_GICP_PMAUTHSTATUS_NSNI_SHIFT (3U) /*! NSNI - NSNI */ #define NOC_GICP_GICP_PMAUTHSTATUS_NSNI(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_NSNI_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_NSNI_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_SE_MASK (0x10U) #define NOC_GICP_GICP_PMAUTHSTATUS_SE_SHIFT (4U) /*! SE - SE */ #define NOC_GICP_GICP_PMAUTHSTATUS_SE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_SE_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_SE_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_SI_MASK (0x20U) #define NOC_GICP_GICP_PMAUTHSTATUS_SI_SHIFT (5U) /*! SI - SI */ #define NOC_GICP_GICP_PMAUTHSTATUS_SI(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_SI_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_SI_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_SNE_MASK (0x40U) #define NOC_GICP_GICP_PMAUTHSTATUS_SNE_SHIFT (6U) /*! SNE - SNE */ #define NOC_GICP_GICP_PMAUTHSTATUS_SNE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_SNE_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_SNE_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_SNI_MASK (0x80U) #define NOC_GICP_GICP_PMAUTHSTATUS_SNI_SHIFT (7U) /*! SNI - SNI */ #define NOC_GICP_GICP_PMAUTHSTATUS_SNI(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_SNI_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_SNI_MASK) #define NOC_GICP_GICP_PMAUTHSTATUS_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PMAUTHSTATUS_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PMAUTHSTATUS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMAUTHSTATUS_RESERVED0_SHIFT)) & NOC_GICP_GICP_PMAUTHSTATUS_RESERVED0_MASK) /*! @} */ /*! @name GICP_PMDEVARCH - GICP_PMDEVARCH */ /*! @{ */ #define NOC_GICP_GICP_PMDEVARCH_ARCHID_MASK (0xFFFFU) #define NOC_GICP_GICP_PMDEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define NOC_GICP_GICP_PMDEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMDEVARCH_ARCHID_SHIFT)) & NOC_GICP_GICP_PMDEVARCH_ARCHID_MASK) #define NOC_GICP_GICP_PMDEVARCH_REVISION_MASK (0xF0000U) #define NOC_GICP_GICP_PMDEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define NOC_GICP_GICP_PMDEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMDEVARCH_REVISION_SHIFT)) & NOC_GICP_GICP_PMDEVARCH_REVISION_MASK) #define NOC_GICP_GICP_PMDEVARCH_PRESENT_MASK (0x100000U) #define NOC_GICP_GICP_PMDEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define NOC_GICP_GICP_PMDEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMDEVARCH_PRESENT_SHIFT)) & NOC_GICP_GICP_PMDEVARCH_PRESENT_MASK) #define NOC_GICP_GICP_PMDEVARCH_ARCHITECT_MASK (0xFFE00000U) #define NOC_GICP_GICP_PMDEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define NOC_GICP_GICP_PMDEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMDEVARCH_ARCHITECT_SHIFT)) & NOC_GICP_GICP_PMDEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name GICP_PMDEVTYPE - GICP_PMDEVTYPE */ /*! @{ */ #define NOC_GICP_GICP_PMDEVTYPE_Class_MASK (0xFU) #define NOC_GICP_GICP_PMDEVTYPE_Class_SHIFT (0U) /*! Class - Class */ #define NOC_GICP_GICP_PMDEVTYPE_Class(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMDEVTYPE_Class_SHIFT)) & NOC_GICP_GICP_PMDEVTYPE_Class_MASK) #define NOC_GICP_GICP_PMDEVTYPE_SubType_MASK (0xF0U) #define NOC_GICP_GICP_PMDEVTYPE_SubType_SHIFT (4U) /*! SubType - SubType */ #define NOC_GICP_GICP_PMDEVTYPE_SubType(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMDEVTYPE_SubType_SHIFT)) & NOC_GICP_GICP_PMDEVTYPE_SubType_MASK) #define NOC_GICP_GICP_PMDEVTYPE_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PMDEVTYPE_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PMDEVTYPE_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PMDEVTYPE_RESERVED0_SHIFT)) & NOC_GICP_GICP_PMDEVTYPE_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR4 - GICP_PIDR4 */ /*! @{ */ #define NOC_GICP_GICP_PIDR4_DES_2_MASK (0xFU) #define NOC_GICP_GICP_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICP_GICP_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR4_DES_2_SHIFT)) & NOC_GICP_GICP_PIDR4_DES_2_MASK) #define NOC_GICP_GICP_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICP_GICP_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICP_GICP_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR4_SIZE_SHIFT)) & NOC_GICP_GICP_PIDR4_SIZE_MASK) #define NOC_GICP_GICP_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR4_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR5 - GICP_PIDR5 */ /*! @{ */ #define NOC_GICP_GICP_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICP_GICP_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICP_GICP_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR5_RESERVED_SHIFT)) & NOC_GICP_GICP_PIDR5_RESERVED_MASK) #define NOC_GICP_GICP_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR5_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR6 - GICP_PIDR6 */ /*! @{ */ #define NOC_GICP_GICP_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICP_GICP_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICP_GICP_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR6_RESERVED_SHIFT)) & NOC_GICP_GICP_PIDR6_RESERVED_MASK) #define NOC_GICP_GICP_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR6_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR7 - GICP_PIDR7 */ /*! @{ */ #define NOC_GICP_GICP_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICP_GICP_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICP_GICP_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR7_RESERVED_SHIFT)) & NOC_GICP_GICP_PIDR7_RESERVED_MASK) #define NOC_GICP_GICP_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR7_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR0 - GICP_PIDR0 */ /*! @{ */ #define NOC_GICP_GICP_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICP_GICP_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICP_GICP_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR0_PART_0_SHIFT)) & NOC_GICP_GICP_PIDR0_PART_0_MASK) #define NOC_GICP_GICP_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR0_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR1 - GICP_PIDR1 */ /*! @{ */ #define NOC_GICP_GICP_PIDR1_PART_1_MASK (0xFU) #define NOC_GICP_GICP_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICP_GICP_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR1_PART_1_SHIFT)) & NOC_GICP_GICP_PIDR1_PART_1_MASK) #define NOC_GICP_GICP_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICP_GICP_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICP_GICP_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR1_DES_0_SHIFT)) & NOC_GICP_GICP_PIDR1_DES_0_MASK) #define NOC_GICP_GICP_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR1_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR2 - GICP_PIDR2 */ /*! @{ */ #define NOC_GICP_GICP_PIDR2_DES_1_MASK (0x7U) #define NOC_GICP_GICP_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICP_GICP_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR2_DES_1_SHIFT)) & NOC_GICP_GICP_PIDR2_DES_1_MASK) #define NOC_GICP_GICP_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICP_GICP_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICP_GICP_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR2_JEDEC_SHIFT)) & NOC_GICP_GICP_PIDR2_JEDEC_MASK) #define NOC_GICP_GICP_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICP_GICP_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICP_GICP_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR2_REVISION_SHIFT)) & NOC_GICP_GICP_PIDR2_REVISION_MASK) #define NOC_GICP_GICP_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR2_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICP_PIDR3 - GICP_PIDR3 */ /*! @{ */ #define NOC_GICP_GICP_PIDR3_CMOD_MASK (0x7U) #define NOC_GICP_GICP_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICP_GICP_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR3_CMOD_SHIFT)) & NOC_GICP_GICP_PIDR3_CMOD_MASK) #define NOC_GICP_GICP_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICP_GICP_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR3_RESERVED0_SHIFT)) & NOC_GICP_GICP_PIDR3_RESERVED0_MASK) #define NOC_GICP_GICP_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICP_GICP_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICP_GICP_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR3_REVAND_SHIFT)) & NOC_GICP_GICP_PIDR3_REVAND_MASK) #define NOC_GICP_GICP_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICP_GICP_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_PIDR3_RESERVED1_SHIFT)) & NOC_GICP_GICP_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICP_CIDR0 - GICP_CIDR0 */ /*! @{ */ #define NOC_GICP_GICP_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICP_GICP_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICP_GICP_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR0_PRMBL_0_SHIFT)) & NOC_GICP_GICP_CIDR0_PRMBL_0_MASK) #define NOC_GICP_GICP_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR0_RESERVED0_SHIFT)) & NOC_GICP_GICP_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICP_CIDR1 - GICP_CIDR1 */ /*! @{ */ #define NOC_GICP_GICP_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICP_GICP_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICP_GICP_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR1_PRMBL_1_SHIFT)) & NOC_GICP_GICP_CIDR1_PRMBL_1_MASK) #define NOC_GICP_GICP_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICP_GICP_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICP_GICP_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR1_CLASS_SHIFT)) & NOC_GICP_GICP_CIDR1_CLASS_MASK) #define NOC_GICP_GICP_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR1_RESERVED0_SHIFT)) & NOC_GICP_GICP_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICP_CIDR2 - GICP_CIDR2 */ /*! @{ */ #define NOC_GICP_GICP_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICP_GICP_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICP_GICP_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR2_PRMBL_2_SHIFT)) & NOC_GICP_GICP_CIDR2_PRMBL_2_MASK) #define NOC_GICP_GICP_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR2_RESERVED0_SHIFT)) & NOC_GICP_GICP_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICP_CIDR3 - GICP_CIDR3 */ /*! @{ */ #define NOC_GICP_GICP_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICP_GICP_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICP_GICP_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR3_PRMBL_3_SHIFT)) & NOC_GICP_GICP_CIDR3_PRMBL_3_MASK) #define NOC_GICP_GICP_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICP_GICP_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICP_GICP_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICP_GICP_CIDR3_RESERVED0_SHIFT)) & NOC_GICP_GICP_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICP_Register_Masks */ /* NOC_GICP - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICP base address */ #define NOC__GIC__GICP_BASE (0x48030000u) /** Peripheral NOC__GIC__GICP base pointer */ #define NOC__GIC__GICP ((NOC_GICP_Type *)NOC__GIC__GICP_BASE) /** Array initializer of NOC_GICP peripheral base addresses */ #define NOC_GICP_BASE_ADDRS { NOC__GIC__GICP_BASE } /** Array initializer of NOC_GICP peripheral base pointers */ #define NOC_GICP_BASE_PTRS { NOC__GIC__GICP } /*! * @} */ /* end of group NOC_GICP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRLPI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI0_Peripheral_Access_Layer NOC_GICRLPI0 Peripheral Access Layer * @{ */ /** NOC_GICRLPI0 - Register Layout Typedef */ typedef struct { __IO uint32_t GICR0_CTLR; /**< GICR0_CTLR, offset: 0x0 */ __I uint32_t GICR0_IIDR; /**< GICR0_IIDR, offset: 0x4 */ __I uint64_t GICR0_TYPER; /**< GICR0_TYPER, offset: 0x8 */ __I uint32_t GICR0_STATUSR; /**< GICR0_STATUSR, offset: 0x10 */ __IO uint32_t GICR0_WAKER; /**< GICR0_WAKER, offset: 0x14 */ __I uint32_t GICR0_MPAMIDR; /**< GICR0_MPAMIDR, offset: 0x18 */ __IO uint32_t GICR0_PARTIDR; /**< GICR0_PARTIDR, offset: 0x1C */ __IO uint32_t GICR0_FCTLR; /**< GICR0_FCTLR, offset: 0x20 */ __IO uint32_t GICR0_PWRR; /**< GICR0_PWRR, offset: 0x24 */ __IO uint32_t GICR0_CLASS; /**< GICR0_CLASS, offset: 0x28 */ uint8_t RESERVED_0[68]; __IO uint64_t GICR0_PROPBASER; /**< GICR0_PROPBASER, offset: 0x70 */ __IO uint64_t GICR0_PENDBASER; /**< GICR0_PENDBASER, offset: 0x78 */ uint8_t RESERVED_1[32]; __O uint64_t GICR0_INVLPIR; /**< GICR0_INVLPIR, offset: 0xA0 */ uint8_t RESERVED_2[8]; __O uint64_t GICR0_INVALLR; /**< GICR0_INVALLR, offset: 0xB0 */ uint8_t RESERVED_3[8]; __I uint32_t GICR0_SYNCR; /**< GICR0_SYNCR, offset: 0xC0 */ uint8_t RESERVED_4[60]; __O uint32_t GICR0_MPIDR; /**< GICR0_MPIDR, offset: 0x100 */ uint8_t RESERVED_5[65228]; __I uint32_t GICR0_PIDR4; /**< GICR0_PIDR4, offset: 0xFFD0 */ __I uint32_t GICR0_PIDR5; /**< GICR0_PIDR5, offset: 0xFFD4 */ __I uint32_t GICR0_PIDR6; /**< GICR0_PIDR6, offset: 0xFFD8 */ __I uint32_t GICR0_PIDR7; /**< GICR0_PIDR7, offset: 0xFFDC */ __I uint32_t GICR0_PIDR0; /**< GICR0_PIDR0, offset: 0xFFE0 */ __I uint32_t GICR0_PIDR1; /**< GICR0_PIDR1, offset: 0xFFE4 */ __I uint32_t GICR0_PIDR2; /**< GICR0_PIDR2, offset: 0xFFE8 */ __I uint32_t GICR0_PIDR3; /**< GICR0_PIDR3, offset: 0xFFEC */ __I uint32_t GICR0_CIDR0; /**< GICR0_CIDR0, offset: 0xFFF0 */ __I uint32_t GICR0_CIDR1; /**< GICR0_CIDR1, offset: 0xFFF4 */ __I uint32_t GICR0_CIDR2; /**< GICR0_CIDR2, offset: 0xFFF8 */ __I uint32_t GICR0_CIDR3; /**< GICR0_CIDR3, offset: 0xFFFC */ } NOC_GICRLPI0_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRLPI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI0_Register_Masks NOC_GICRLPI0 Register Masks * @{ */ /*! @name GICR0_CTLR - GICR0_CTLR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_CTLR_EnableLPIs_MASK (0x1U) #define NOC_GICRLPI0_GICR0_CTLR_EnableLPIs_SHIFT (0U) /*! EnableLPIs - EnableLPIs */ #define NOC_GICRLPI0_GICR0_CTLR_EnableLPIs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_EnableLPIs_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_EnableLPIs_MASK) #define NOC_GICRLPI0_GICR0_CTLR_CES_MASK (0x2U) #define NOC_GICRLPI0_GICR0_CTLR_CES_SHIFT (1U) /*! CES - CES */ #define NOC_GICRLPI0_GICR0_CTLR_CES(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_CES_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_CES_MASK) #define NOC_GICRLPI0_GICR0_CTLR_IR_MASK (0x4U) #define NOC_GICRLPI0_GICR0_CTLR_IR_SHIFT (2U) /*! IR - IR */ #define NOC_GICRLPI0_GICR0_CTLR_IR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_IR_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_IR_MASK) #define NOC_GICRLPI0_GICR0_CTLR_RWP_MASK (0x8U) #define NOC_GICRLPI0_GICR0_CTLR_RWP_SHIFT (3U) /*! RWP - RWP */ #define NOC_GICRLPI0_GICR0_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_RWP_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_RWP_MASK) #define NOC_GICRLPI0_GICR0_CTLR_RESERVED1_MASK (0xFFFFF0U) #define NOC_GICRLPI0_GICR0_CTLR_RESERVED1_SHIFT (4U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_RESERVED1_MASK) #define NOC_GICRLPI0_GICR0_CTLR_DPG0_MASK (0x1000000U) #define NOC_GICRLPI0_GICR0_CTLR_DPG0_SHIFT (24U) /*! DPG0 - DPG0 */ #define NOC_GICRLPI0_GICR0_CTLR_DPG0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_DPG0_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_DPG0_MASK) #define NOC_GICRLPI0_GICR0_CTLR_DPG1NS_MASK (0x2000000U) #define NOC_GICRLPI0_GICR0_CTLR_DPG1NS_SHIFT (25U) /*! DPG1NS - DPG1NS */ #define NOC_GICRLPI0_GICR0_CTLR_DPG1NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_DPG1NS_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_DPG1NS_MASK) #define NOC_GICRLPI0_GICR0_CTLR_DPG1S_MASK (0x4000000U) #define NOC_GICRLPI0_GICR0_CTLR_DPG1S_SHIFT (26U) /*! DPG1S - DPG1S */ #define NOC_GICRLPI0_GICR0_CTLR_DPG1S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_DPG1S_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_DPG1S_MASK) #define NOC_GICRLPI0_GICR0_CTLR_RESERVED2_MASK (0x78000000U) #define NOC_GICRLPI0_GICR0_CTLR_RESERVED2_SHIFT (27U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI0_GICR0_CTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_RESERVED2_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_RESERVED2_MASK) #define NOC_GICRLPI0_GICR0_CTLR_UWP_MASK (0x80000000U) #define NOC_GICRLPI0_GICR0_CTLR_UWP_SHIFT (31U) /*! UWP - UWP */ #define NOC_GICRLPI0_GICR0_CTLR_UWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CTLR_UWP_SHIFT)) & NOC_GICRLPI0_GICR0_CTLR_UWP_MASK) /*! @} */ /*! @name GICR0_IIDR - GICR0_IIDR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICRLPI0_GICR0_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICRLPI0_GICR0_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_IIDR_Implementer_SHIFT)) & NOC_GICRLPI0_GICR0_IIDR_Implementer_MASK) #define NOC_GICRLPI0_GICR0_IIDR_Revision_MASK (0xF000U) #define NOC_GICRLPI0_GICR0_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICRLPI0_GICR0_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_IIDR_Revision_SHIFT)) & NOC_GICRLPI0_GICR0_IIDR_Revision_MASK) #define NOC_GICRLPI0_GICR0_IIDR_Variant_MASK (0xF0000U) #define NOC_GICRLPI0_GICR0_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICRLPI0_GICR0_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_IIDR_Variant_SHIFT)) & NOC_GICRLPI0_GICR0_IIDR_Variant_MASK) #define NOC_GICRLPI0_GICR0_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICRLPI0_GICR0_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_IIDR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_IIDR_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICRLPI0_GICR0_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICRLPI0_GICR0_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_IIDR_ProductID_SHIFT)) & NOC_GICRLPI0_GICR0_IIDR_ProductID_MASK) /*! @} */ /*! @name GICR0_TYPER - GICR0_TYPER */ /*! @{ */ #define NOC_GICRLPI0_GICR0_TYPER_PLPIS_MASK (0x1U) #define NOC_GICRLPI0_GICR0_TYPER_PLPIS_SHIFT (0U) /*! PLPIS - PLPIS */ #define NOC_GICRLPI0_GICR0_TYPER_PLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_PLPIS_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_PLPIS_MASK) #define NOC_GICRLPI0_GICR0_TYPER_VLPIS_MASK (0x2U) #define NOC_GICRLPI0_GICR0_TYPER_VLPIS_SHIFT (1U) /*! VLPIS - VLPIS */ #define NOC_GICRLPI0_GICR0_TYPER_VLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_VLPIS_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_VLPIS_MASK) #define NOC_GICRLPI0_GICR0_TYPER_Dirty_MASK (0x4U) #define NOC_GICRLPI0_GICR0_TYPER_Dirty_SHIFT (2U) /*! Dirty - Dirty */ #define NOC_GICRLPI0_GICR0_TYPER_Dirty(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_Dirty_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_Dirty_MASK) #define NOC_GICRLPI0_GICR0_TYPER_DirectLPI_MASK (0x8U) #define NOC_GICRLPI0_GICR0_TYPER_DirectLPI_SHIFT (3U) /*! DirectLPI - DirectLPI */ #define NOC_GICRLPI0_GICR0_TYPER_DirectLPI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_DirectLPI_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_DirectLPI_MASK) #define NOC_GICRLPI0_GICR0_TYPER_Last_MASK (0x10U) #define NOC_GICRLPI0_GICR0_TYPER_Last_SHIFT (4U) /*! Last - Last */ #define NOC_GICRLPI0_GICR0_TYPER_Last(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_Last_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_Last_MASK) #define NOC_GICRLPI0_GICR0_TYPER_DPGS_MASK (0x20U) #define NOC_GICRLPI0_GICR0_TYPER_DPGS_SHIFT (5U) /*! DPGS - DPGS */ #define NOC_GICRLPI0_GICR0_TYPER_DPGS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_DPGS_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_DPGS_MASK) #define NOC_GICRLPI0_GICR0_TYPER_MPAM_MASK (0x40U) #define NOC_GICRLPI0_GICR0_TYPER_MPAM_SHIFT (6U) /*! MPAM - MPAM */ #define NOC_GICRLPI0_GICR0_TYPER_MPAM(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_MPAM_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_MPAM_MASK) #define NOC_GICRLPI0_GICR0_TYPER_RVPEID_MASK (0x80U) #define NOC_GICRLPI0_GICR0_TYPER_RVPEID_SHIFT (7U) /*! RVPEID - RVPEID */ #define NOC_GICRLPI0_GICR0_TYPER_RVPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_RVPEID_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_RVPEID_MASK) #define NOC_GICRLPI0_GICR0_TYPER_ProcessorNumber_MASK (0xFFFF00U) #define NOC_GICRLPI0_GICR0_TYPER_ProcessorNumber_SHIFT (8U) /*! ProcessorNumber - ProcessorNumber */ #define NOC_GICRLPI0_GICR0_TYPER_ProcessorNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_ProcessorNumber_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_ProcessorNumber_MASK) #define NOC_GICRLPI0_GICR0_TYPER_CommonLPIAff_MASK (0x3000000U) #define NOC_GICRLPI0_GICR0_TYPER_CommonLPIAff_SHIFT (24U) /*! CommonLPIAff - CommonLPIAff */ #define NOC_GICRLPI0_GICR0_TYPER_CommonLPIAff(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_CommonLPIAff_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_CommonLPIAff_MASK) #define NOC_GICRLPI0_GICR0_TYPER_VSGI_MASK (0x4000000U) #define NOC_GICRLPI0_GICR0_TYPER_VSGI_SHIFT (26U) /*! VSGI - VSGI */ #define NOC_GICRLPI0_GICR0_TYPER_VSGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_VSGI_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_VSGI_MASK) #define NOC_GICRLPI0_GICR0_TYPER_PPInum_MASK (0xF8000000U) #define NOC_GICRLPI0_GICR0_TYPER_PPInum_SHIFT (27U) /*! PPInum - PPInum */ #define NOC_GICRLPI0_GICR0_TYPER_PPInum(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_PPInum_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_PPInum_MASK) #define NOC_GICRLPI0_GICR0_TYPER_AffinityValue_MASK (0xFFFFFFFF00000000U) #define NOC_GICRLPI0_GICR0_TYPER_AffinityValue_SHIFT (32U) /*! AffinityValue - AffinityValue */ #define NOC_GICRLPI0_GICR0_TYPER_AffinityValue(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_TYPER_AffinityValue_SHIFT)) & NOC_GICRLPI0_GICR0_TYPER_AffinityValue_MASK) /*! @} */ /*! @name GICR0_STATUSR - GICR0_STATUSR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICRLPI0_GICR0_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI0_GICR0_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_STATUSR_RESERVED_SHIFT)) & NOC_GICRLPI0_GICR0_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICR0_WAKER - GICR0_WAKER */ /*! @{ */ #define NOC_GICRLPI0_GICR0_WAKER_Sleep_MASK (0x1U) #define NOC_GICRLPI0_GICR0_WAKER_Sleep_SHIFT (0U) /*! Sleep - Sleep */ #define NOC_GICRLPI0_GICR0_WAKER_Sleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_WAKER_Sleep_SHIFT)) & NOC_GICRLPI0_GICR0_WAKER_Sleep_MASK) #define NOC_GICRLPI0_GICR0_WAKER_ProcessorSleep_MASK (0x2U) #define NOC_GICRLPI0_GICR0_WAKER_ProcessorSleep_SHIFT (1U) /*! ProcessorSleep - ProcessorSleep */ #define NOC_GICRLPI0_GICR0_WAKER_ProcessorSleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_WAKER_ProcessorSleep_SHIFT)) & NOC_GICRLPI0_GICR0_WAKER_ProcessorSleep_MASK) #define NOC_GICRLPI0_GICR0_WAKER_ChildrenAsleep_MASK (0x4U) #define NOC_GICRLPI0_GICR0_WAKER_ChildrenAsleep_SHIFT (2U) /*! ChildrenAsleep - ChildrenAsleep */ #define NOC_GICRLPI0_GICR0_WAKER_ChildrenAsleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_WAKER_ChildrenAsleep_SHIFT)) & NOC_GICRLPI0_GICR0_WAKER_ChildrenAsleep_MASK) #define NOC_GICRLPI0_GICR0_WAKER_RESERVED0_MASK (0x7FFFFFF8U) #define NOC_GICRLPI0_GICR0_WAKER_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_WAKER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_WAKER_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_WAKER_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_WAKER_Quiescent_MASK (0x80000000U) #define NOC_GICRLPI0_GICR0_WAKER_Quiescent_SHIFT (31U) /*! Quiescent - Quiescent */ #define NOC_GICRLPI0_GICR0_WAKER_Quiescent(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_WAKER_Quiescent_SHIFT)) & NOC_GICRLPI0_GICR0_WAKER_Quiescent_MASK) /*! @} */ /*! @name GICR0_MPAMIDR - GICR0_MPAMIDR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_MPAMIDR_PARTID_MAX_MASK (0x1FFU) #define NOC_GICRLPI0_GICR0_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define NOC_GICRLPI0_GICR0_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPAMIDR_PARTID_MAX_SHIFT)) & NOC_GICRLPI0_GICR0_MPAMIDR_PARTID_MAX_MASK) #define NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_MPAMIDR_PMG_MAX_MASK (0x10000U) #define NOC_GICRLPI0_GICR0_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define NOC_GICRLPI0_GICR0_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPAMIDR_PMG_MAX_SHIFT)) & NOC_GICRLPI0_GICR0_MPAMIDR_PMG_MAX_MASK) #define NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_MPAMIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR0_PARTIDR - GICR0_PARTIDR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PARTIDR_PARTID_MASK (0x1FFU) #define NOC_GICRLPI0_GICR0_PARTIDR_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define NOC_GICRLPI0_GICR0_PARTIDR_PARTID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PARTIDR_PARTID_SHIFT)) & NOC_GICRLPI0_GICR0_PARTIDR_PARTID_MASK) #define NOC_GICRLPI0_GICR0_PARTIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI0_GICR0_PARTIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PARTIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PARTIDR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PARTIDR_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_PARTIDR_PMG_MASK (0x10000U) #define NOC_GICRLPI0_GICR0_PARTIDR_PMG_SHIFT (16U) /*! PMG - PMG */ #define NOC_GICRLPI0_GICR0_PARTIDR_PMG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PARTIDR_PMG_SHIFT)) & NOC_GICRLPI0_GICR0_PARTIDR_PMG_MASK) #define NOC_GICRLPI0_GICR0_PARTIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI0_GICR0_PARTIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_PARTIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PARTIDR_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_PARTIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR0_FCTLR - GICR0_FCTLR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_FCTLR_SIP_MASK (0x1U) #define NOC_GICRLPI0_GICR0_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICRLPI0_GICR0_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_FCTLR_SIP_SHIFT)) & NOC_GICRLPI0_GICR0_FCTLR_SIP_MASK) #define NOC_GICRLPI0_GICR0_FCTLR_QDeny_MASK (0x2U) #define NOC_GICRLPI0_GICR0_FCTLR_QDeny_SHIFT (1U) /*! QDeny - QDeny */ #define NOC_GICRLPI0_GICR0_FCTLR_QDeny(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_FCTLR_QDeny_SHIFT)) & NOC_GICRLPI0_GICR0_FCTLR_QDeny_MASK) #define NOC_GICRLPI0_GICR0_FCTLR_CGO_MASK (0x1CU) #define NOC_GICRLPI0_GICR0_FCTLR_CGO_SHIFT (2U) /*! CGO - CGO */ #define NOC_GICRLPI0_GICR0_FCTLR_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_FCTLR_CGO_SHIFT)) & NOC_GICRLPI0_GICR0_FCTLR_CGO_MASK) #define NOC_GICRLPI0_GICR0_FCTLR_RESERVED0_MASK (0x3E0U) #define NOC_GICRLPI0_GICR0_FCTLR_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_FCTLR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_FCTLR_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_FCTLR_RESERVED1_MASK (0xFFFFFC00U) #define NOC_GICRLPI0_GICR0_FCTLR_RESERVED1_SHIFT (10U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_FCTLR_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_FCTLR_RESERVED1_MASK) /*! @} */ /*! @name GICR0_PWRR - GICR0_PWRR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PWRR_RDPD_MASK (0x1U) #define NOC_GICRLPI0_GICR0_PWRR_RDPD_SHIFT (0U) /*! RDPD - RDPD */ #define NOC_GICRLPI0_GICR0_PWRR_RDPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RDPD_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RDPD_MASK) #define NOC_GICRLPI0_GICR0_PWRR_RDAG_MASK (0x2U) #define NOC_GICRLPI0_GICR0_PWRR_RDAG_SHIFT (1U) /*! RDAG - RDAG */ #define NOC_GICRLPI0_GICR0_PWRR_RDAG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RDAG_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RDAG_MASK) #define NOC_GICRLPI0_GICR0_PWRR_RDGPD_MASK (0x4U) #define NOC_GICRLPI0_GICR0_PWRR_RDGPD_SHIFT (2U) /*! RDGPD - RDGPD */ #define NOC_GICRLPI0_GICR0_PWRR_RDGPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RDGPD_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RDGPD_MASK) #define NOC_GICRLPI0_GICR0_PWRR_RDGPO_MASK (0x8U) #define NOC_GICRLPI0_GICR0_PWRR_RDGPO_SHIFT (3U) /*! RDGPO - RDGPO */ #define NOC_GICRLPI0_GICR0_PWRR_RDGPO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RDGPO_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RDGPO_MASK) #define NOC_GICRLPI0_GICR0_PWRR_RESERVED0_MASK (0xF0U) #define NOC_GICRLPI0_GICR0_PWRR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PWRR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_PWRR_RDGO_MASK (0x7F00U) #define NOC_GICRLPI0_GICR0_PWRR_RDGO_SHIFT (8U) /*! RDGO - RDGO */ #define NOC_GICRLPI0_GICR0_PWRR_RDGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RDGO_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RDGO_MASK) #define NOC_GICRLPI0_GICR0_PWRR_RDG_MASK (0xFF8000U) #define NOC_GICRLPI0_GICR0_PWRR_RDG_SHIFT (15U) /*! RDG - RDG */ #define NOC_GICRLPI0_GICR0_PWRR_RDG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RDG_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RDG_MASK) #define NOC_GICRLPI0_GICR0_PWRR_RESERVED1_MASK (0xFF000000U) #define NOC_GICRLPI0_GICR0_PWRR_RESERVED1_SHIFT (24U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_PWRR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PWRR_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_PWRR_RESERVED1_MASK) /*! @} */ /*! @name GICR0_CLASS - GICR0_CLASS */ /*! @{ */ #define NOC_GICRLPI0_GICR0_CLASS_Class_MASK (0x1U) #define NOC_GICRLPI0_GICR0_CLASS_Class_SHIFT (0U) /*! Class - Class */ #define NOC_GICRLPI0_GICR0_CLASS_Class(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CLASS_Class_SHIFT)) & NOC_GICRLPI0_GICR0_CLASS_Class_MASK) #define NOC_GICRLPI0_GICR0_CLASS_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI0_GICR0_CLASS_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_CLASS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CLASS_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_CLASS_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PROPBASER - GICR0_PROPBASER */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PROPBASER_IDBits_MASK (0x1FU) #define NOC_GICRLPI0_GICR0_PROPBASER_IDBits_SHIFT (0U) /*! IDBits - IDBits */ #define NOC_GICRLPI0_GICR0_PROPBASER_IDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_IDBits_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_IDBits_MASK) #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED0_MASK (0x60U) #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_PROPBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI0_GICR0_PROPBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI0_GICR0_PROPBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_Cacheability_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_Cacheability_MASK) #define NOC_GICRLPI0_GICR0_PROPBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI0_GICR0_PROPBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI0_GICR0_PROPBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_Shareability_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_Shareability_MASK) #define NOC_GICRLPI0_GICR0_PROPBASER_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GICRLPI0_GICR0_PROPBASER_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI0_GICR0_PROPBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_PhysicalAddress_MASK) #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED1_MASK (0xFFFFF000000000U) #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED1_SHIFT (36U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_RESERVED1_MASK) #define NOC_GICRLPI0_GICR0_PROPBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI0_GICR0_PROPBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI0_GICR0_PROPBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_OuterCacheability_MASK) #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED2_MASK (0xF800000000000000U) #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED2_SHIFT (59U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI0_GICR0_PROPBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PROPBASER_RESERVED2_SHIFT)) & NOC_GICRLPI0_GICR0_PROPBASER_RESERVED2_MASK) /*! @} */ /*! @name GICR0_PENDBASER - GICR0_PENDBASER */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED0_MASK (0x7FU) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI0_GICR0_PENDBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI0_GICR0_PENDBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_Cacheability_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_Cacheability_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI0_GICR0_PENDBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI0_GICR0_PENDBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_Shareability_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_Shareability_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED1_MASK (0xF000U) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_RESERVED1_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_PhysicalAddress_MASK (0xFFFFF0000U) #define NOC_GICRLPI0_GICR0_PENDBASER_PhysicalAddress_SHIFT (16U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI0_GICR0_PENDBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_PhysicalAddress_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED2_MASK (0xFFFFF000000000U) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED2_SHIFT (36U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_RESERVED2_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_RESERVED2_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI0_GICR0_PENDBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI0_GICR0_PENDBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_OuterCacheability_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED3_MASK (0x3800000000000000U) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED3_SHIFT (59U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_RESERVED3_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_RESERVED3_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_PendingTableZero_MASK (0x4000000000000000U) #define NOC_GICRLPI0_GICR0_PENDBASER_PendingTableZero_SHIFT (62U) /*! PendingTableZero - PendingTableZero */ #define NOC_GICRLPI0_GICR0_PENDBASER_PendingTableZero(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_PendingTableZero_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_PendingTableZero_MASK) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED4_MASK (0x8000000000000000U) #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED4_SHIFT (63U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRLPI0_GICR0_PENDBASER_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_PENDBASER_RESERVED4_SHIFT)) & NOC_GICRLPI0_GICR0_PENDBASER_RESERVED4_MASK) /*! @} */ /*! @name GICR0_INVLPIR - GICR0_INVLPIR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_INVLPIR_IntID_MASK (0xFFFFFFFFU) #define NOC_GICRLPI0_GICR0_INVLPIR_IntID_SHIFT (0U) /*! IntID - IntID */ #define NOC_GICRLPI0_GICR0_INVLPIR_IntID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVLPIR_IntID_SHIFT)) & NOC_GICRLPI0_GICR0_INVLPIR_IntID_MASK) #define NOC_GICRLPI0_GICR0_INVLPIR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI0_GICR0_INVLPIR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI0_GICR0_INVLPIR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVLPIR_VPEID_SHIFT)) & NOC_GICRLPI0_GICR0_INVLPIR_VPEID_MASK) #define NOC_GICRLPI0_GICR0_INVLPIR_RESERVED0_MASK (0x7FFF000000000000U) #define NOC_GICRLPI0_GICR0_INVLPIR_RESERVED0_SHIFT (48U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_INVLPIR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVLPIR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_INVLPIR_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_INVLPIR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI0_GICR0_INVLPIR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI0_GICR0_INVLPIR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVLPIR_V_SHIFT)) & NOC_GICRLPI0_GICR0_INVLPIR_V_MASK) /*! @} */ /*! @name GICR0_INVALLR - GICR0_INVALLR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_INVALLR_RESERVED0_MASK (0xFFFFFFFFU) #define NOC_GICRLPI0_GICR0_INVALLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_INVALLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVALLR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_INVALLR_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_INVALLR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI0_GICR0_INVALLR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI0_GICR0_INVALLR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVALLR_VPEID_SHIFT)) & NOC_GICRLPI0_GICR0_INVALLR_VPEID_MASK) #define NOC_GICRLPI0_GICR0_INVALLR_RESERVED1_MASK (0x7FFF000000000000U) #define NOC_GICRLPI0_GICR0_INVALLR_RESERVED1_SHIFT (48U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_INVALLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVALLR_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_INVALLR_RESERVED1_MASK) #define NOC_GICRLPI0_GICR0_INVALLR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI0_GICR0_INVALLR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI0_GICR0_INVALLR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI0_GICR0_INVALLR_V_SHIFT)) & NOC_GICRLPI0_GICR0_INVALLR_V_MASK) /*! @} */ /*! @name GICR0_SYNCR - GICR0_SYNCR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_SYNCR_Busy_MASK (0x1U) #define NOC_GICRLPI0_GICR0_SYNCR_Busy_SHIFT (0U) /*! Busy - Busy */ #define NOC_GICRLPI0_GICR0_SYNCR_Busy(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_SYNCR_Busy_SHIFT)) & NOC_GICRLPI0_GICR0_SYNCR_Busy_MASK) #define NOC_GICRLPI0_GICR0_SYNCR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI0_GICR0_SYNCR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_SYNCR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_SYNCR_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_SYNCR_RESERVED0_MASK) /*! @} */ /*! @name GICR0_MPIDR - GICR0_MPIDR */ /*! @{ */ #define NOC_GICRLPI0_GICR0_MPIDR_Affinity0_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_MPIDR_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICRLPI0_GICR0_MPIDR_Affinity0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPIDR_Affinity0_SHIFT)) & NOC_GICRLPI0_GICR0_MPIDR_Affinity0_MASK) #define NOC_GICRLPI0_GICR0_MPIDR_Affinity1_MASK (0xFF00U) #define NOC_GICRLPI0_GICR0_MPIDR_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 */ #define NOC_GICRLPI0_GICR0_MPIDR_Affinity1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPIDR_Affinity1_SHIFT)) & NOC_GICRLPI0_GICR0_MPIDR_Affinity1_MASK) #define NOC_GICRLPI0_GICR0_MPIDR_Affinity2_MASK (0xFF0000U) #define NOC_GICRLPI0_GICR0_MPIDR_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICRLPI0_GICR0_MPIDR_Affinity2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPIDR_Affinity2_SHIFT)) & NOC_GICRLPI0_GICR0_MPIDR_Affinity2_MASK) #define NOC_GICRLPI0_GICR0_MPIDR_Affinity3_MASK (0xFF000000U) #define NOC_GICRLPI0_GICR0_MPIDR_Affinity3_SHIFT (24U) /*! Affinity3 - Affinity3 */ #define NOC_GICRLPI0_GICR0_MPIDR_Affinity3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_MPIDR_Affinity3_SHIFT)) & NOC_GICRLPI0_GICR0_MPIDR_Affinity3_MASK) /*! @} */ /*! @name GICR0_PIDR4 - GICR0_PIDR4 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR4_DES_2_MASK (0xFU) #define NOC_GICRLPI0_GICR0_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICRLPI0_GICR0_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR4_DES_2_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR4_DES_2_MASK) #define NOC_GICRLPI0_GICR0_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICRLPI0_GICR0_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICRLPI0_GICR0_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR4_SIZE_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR4_SIZE_MASK) #define NOC_GICRLPI0_GICR0_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR4_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PIDR5 - GICR0_PIDR5 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI0_GICR0_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR5_RESERVED_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR5_RESERVED_MASK) #define NOC_GICRLPI0_GICR0_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR5_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PIDR6 - GICR0_PIDR6 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI0_GICR0_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR6_RESERVED_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR6_RESERVED_MASK) #define NOC_GICRLPI0_GICR0_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR6_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PIDR7 - GICR0_PIDR7 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI0_GICR0_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR7_RESERVED_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR7_RESERVED_MASK) #define NOC_GICRLPI0_GICR0_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR7_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PIDR0 - GICR0_PIDR0 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICRLPI0_GICR0_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR0_PART_0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR0_PART_0_MASK) #define NOC_GICRLPI0_GICR0_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PIDR1 - GICR0_PIDR1 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR1_PART_1_MASK (0xFU) #define NOC_GICRLPI0_GICR0_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICRLPI0_GICR0_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR1_PART_1_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR1_PART_1_MASK) #define NOC_GICRLPI0_GICR0_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICRLPI0_GICR0_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICRLPI0_GICR0_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR1_DES_0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR1_DES_0_MASK) #define NOC_GICRLPI0_GICR0_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PIDR2 - GICR0_PIDR2 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR2_DES_1_MASK (0x7U) #define NOC_GICRLPI0_GICR0_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICRLPI0_GICR0_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR2_DES_1_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR2_DES_1_MASK) #define NOC_GICRLPI0_GICR0_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICRLPI0_GICR0_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICRLPI0_GICR0_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR2_JEDEC_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR2_JEDEC_MASK) #define NOC_GICRLPI0_GICR0_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICRLPI0_GICR0_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICRLPI0_GICR0_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR2_REVISION_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR2_REVISION_MASK) #define NOC_GICRLPI0_GICR0_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR0_PIDR3 - GICR0_PIDR3 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_PIDR3_CMOD_MASK (0x7U) #define NOC_GICRLPI0_GICR0_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICRLPI0_GICR0_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR3_CMOD_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR3_CMOD_MASK) #define NOC_GICRLPI0_GICR0_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICRLPI0_GICR0_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR3_RESERVED0_MASK) #define NOC_GICRLPI0_GICR0_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICRLPI0_GICR0_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICRLPI0_GICR0_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR3_REVAND_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR3_REVAND_MASK) #define NOC_GICRLPI0_GICR0_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI0_GICR0_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_PIDR3_RESERVED1_SHIFT)) & NOC_GICRLPI0_GICR0_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICR0_CIDR0 - GICR0_CIDR0 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICRLPI0_GICR0_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR0_PRMBL_0_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR0_PRMBL_0_MASK) #define NOC_GICRLPI0_GICR0_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR0_CIDR1 - GICR0_CIDR1 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICRLPI0_GICR0_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICRLPI0_GICR0_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR1_PRMBL_1_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR1_PRMBL_1_MASK) #define NOC_GICRLPI0_GICR0_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICRLPI0_GICR0_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICRLPI0_GICR0_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR1_CLASS_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR1_CLASS_MASK) #define NOC_GICRLPI0_GICR0_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR0_CIDR2 - GICR0_CIDR2 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICRLPI0_GICR0_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR2_PRMBL_2_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR2_PRMBL_2_MASK) #define NOC_GICRLPI0_GICR0_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR0_CIDR3 - GICR0_CIDR3 */ /*! @{ */ #define NOC_GICRLPI0_GICR0_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICRLPI0_GICR0_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICRLPI0_GICR0_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR3_PRMBL_3_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR3_PRMBL_3_MASK) #define NOC_GICRLPI0_GICR0_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI0_GICR0_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI0_GICR0_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI0_GICR0_CIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI0_GICR0_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRLPI0_Register_Masks */ /* NOC_GICRLPI0 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRLPI0 base address */ #define NOC__GIC__GICRLPI0_BASE (0x48060000u) /** Peripheral NOC__GIC__GICRLPI0 base pointer */ #define NOC__GIC__GICRLPI0 ((NOC_GICRLPI0_Type *)NOC__GIC__GICRLPI0_BASE) /** Array initializer of NOC_GICRLPI0 peripheral base addresses */ #define NOC_GICRLPI0_BASE_ADDRS { NOC__GIC__GICRLPI0_BASE } /** Array initializer of NOC_GICRLPI0 peripheral base pointers */ #define NOC_GICRLPI0_BASE_PTRS { NOC__GIC__GICRLPI0 } /*! * @} */ /* end of group NOC_GICRLPI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRLPI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI1_Peripheral_Access_Layer NOC_GICRLPI1 Peripheral Access Layer * @{ */ /** NOC_GICRLPI1 - Register Layout Typedef */ typedef struct { __IO uint32_t GICR1_CTLR; /**< GICR1_CTLR, offset: 0x0 */ __I uint32_t GICR1_IIDR; /**< GICR1_IIDR, offset: 0x4 */ __I uint64_t GICR1_TYPER; /**< GICR1_TYPER, offset: 0x8 */ __I uint32_t GICR1_STATUSR; /**< GICR1_STATUSR, offset: 0x10 */ __IO uint32_t GICR1_WAKER; /**< GICR1_WAKER, offset: 0x14 */ __I uint32_t GICR1_MPAMIDR; /**< GICR1_MPAMIDR, offset: 0x18 */ __IO uint32_t GICR1_PARTIDR; /**< GICR1_PARTIDR, offset: 0x1C */ __IO uint32_t GICR1_FCTLR; /**< GICR1_FCTLR, offset: 0x20 */ __IO uint32_t GICR1_PWRR; /**< GICR1_PWRR, offset: 0x24 */ __IO uint32_t GICR1_CLASS; /**< GICR1_CLASS, offset: 0x28 */ uint8_t RESERVED_0[68]; __IO uint64_t GICR1_PROPBASER; /**< GICR1_PROPBASER, offset: 0x70 */ __IO uint64_t GICR1_PENDBASER; /**< GICR1_PENDBASER, offset: 0x78 */ uint8_t RESERVED_1[32]; __O uint64_t GICR1_INVLPIR; /**< GICR1_INVLPIR, offset: 0xA0 */ uint8_t RESERVED_2[8]; __O uint64_t GICR1_INVALLR; /**< GICR1_INVALLR, offset: 0xB0 */ uint8_t RESERVED_3[8]; __I uint32_t GICR1_SYNCR; /**< GICR1_SYNCR, offset: 0xC0 */ uint8_t RESERVED_4[60]; __O uint32_t GICR1_MPIDR; /**< GICR1_MPIDR, offset: 0x100 */ uint8_t RESERVED_5[65228]; __I uint32_t GICR1_PIDR4; /**< GICR1_PIDR4, offset: 0xFFD0 */ __I uint32_t GICR1_PIDR5; /**< GICR1_PIDR5, offset: 0xFFD4 */ __I uint32_t GICR1_PIDR6; /**< GICR1_PIDR6, offset: 0xFFD8 */ __I uint32_t GICR1_PIDR7; /**< GICR1_PIDR7, offset: 0xFFDC */ __I uint32_t GICR1_PIDR0; /**< GICR1_PIDR0, offset: 0xFFE0 */ __I uint32_t GICR1_PIDR1; /**< GICR1_PIDR1, offset: 0xFFE4 */ __I uint32_t GICR1_PIDR2; /**< GICR1_PIDR2, offset: 0xFFE8 */ __I uint32_t GICR1_PIDR3; /**< GICR1_PIDR3, offset: 0xFFEC */ __I uint32_t GICR1_CIDR0; /**< GICR1_CIDR0, offset: 0xFFF0 */ __I uint32_t GICR1_CIDR1; /**< GICR1_CIDR1, offset: 0xFFF4 */ __I uint32_t GICR1_CIDR2; /**< GICR1_CIDR2, offset: 0xFFF8 */ __I uint32_t GICR1_CIDR3; /**< GICR1_CIDR3, offset: 0xFFFC */ } NOC_GICRLPI1_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRLPI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI1_Register_Masks NOC_GICRLPI1 Register Masks * @{ */ /*! @name GICR1_CTLR - GICR1_CTLR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_CTLR_EnableLPIs_MASK (0x1U) #define NOC_GICRLPI1_GICR1_CTLR_EnableLPIs_SHIFT (0U) /*! EnableLPIs - EnableLPIs */ #define NOC_GICRLPI1_GICR1_CTLR_EnableLPIs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_EnableLPIs_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_EnableLPIs_MASK) #define NOC_GICRLPI1_GICR1_CTLR_CES_MASK (0x2U) #define NOC_GICRLPI1_GICR1_CTLR_CES_SHIFT (1U) /*! CES - CES */ #define NOC_GICRLPI1_GICR1_CTLR_CES(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_CES_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_CES_MASK) #define NOC_GICRLPI1_GICR1_CTLR_IR_MASK (0x4U) #define NOC_GICRLPI1_GICR1_CTLR_IR_SHIFT (2U) /*! IR - IR */ #define NOC_GICRLPI1_GICR1_CTLR_IR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_IR_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_IR_MASK) #define NOC_GICRLPI1_GICR1_CTLR_RWP_MASK (0x8U) #define NOC_GICRLPI1_GICR1_CTLR_RWP_SHIFT (3U) /*! RWP - RWP */ #define NOC_GICRLPI1_GICR1_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_RWP_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_RWP_MASK) #define NOC_GICRLPI1_GICR1_CTLR_RESERVED1_MASK (0xFFFFF0U) #define NOC_GICRLPI1_GICR1_CTLR_RESERVED1_SHIFT (4U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_RESERVED1_MASK) #define NOC_GICRLPI1_GICR1_CTLR_DPG0_MASK (0x1000000U) #define NOC_GICRLPI1_GICR1_CTLR_DPG0_SHIFT (24U) /*! DPG0 - DPG0 */ #define NOC_GICRLPI1_GICR1_CTLR_DPG0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_DPG0_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_DPG0_MASK) #define NOC_GICRLPI1_GICR1_CTLR_DPG1NS_MASK (0x2000000U) #define NOC_GICRLPI1_GICR1_CTLR_DPG1NS_SHIFT (25U) /*! DPG1NS - DPG1NS */ #define NOC_GICRLPI1_GICR1_CTLR_DPG1NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_DPG1NS_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_DPG1NS_MASK) #define NOC_GICRLPI1_GICR1_CTLR_DPG1S_MASK (0x4000000U) #define NOC_GICRLPI1_GICR1_CTLR_DPG1S_SHIFT (26U) /*! DPG1S - DPG1S */ #define NOC_GICRLPI1_GICR1_CTLR_DPG1S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_DPG1S_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_DPG1S_MASK) #define NOC_GICRLPI1_GICR1_CTLR_RESERVED2_MASK (0x78000000U) #define NOC_GICRLPI1_GICR1_CTLR_RESERVED2_SHIFT (27U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI1_GICR1_CTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_RESERVED2_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_RESERVED2_MASK) #define NOC_GICRLPI1_GICR1_CTLR_UWP_MASK (0x80000000U) #define NOC_GICRLPI1_GICR1_CTLR_UWP_SHIFT (31U) /*! UWP - UWP */ #define NOC_GICRLPI1_GICR1_CTLR_UWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CTLR_UWP_SHIFT)) & NOC_GICRLPI1_GICR1_CTLR_UWP_MASK) /*! @} */ /*! @name GICR1_IIDR - GICR1_IIDR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICRLPI1_GICR1_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICRLPI1_GICR1_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_IIDR_Implementer_SHIFT)) & NOC_GICRLPI1_GICR1_IIDR_Implementer_MASK) #define NOC_GICRLPI1_GICR1_IIDR_Revision_MASK (0xF000U) #define NOC_GICRLPI1_GICR1_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICRLPI1_GICR1_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_IIDR_Revision_SHIFT)) & NOC_GICRLPI1_GICR1_IIDR_Revision_MASK) #define NOC_GICRLPI1_GICR1_IIDR_Variant_MASK (0xF0000U) #define NOC_GICRLPI1_GICR1_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICRLPI1_GICR1_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_IIDR_Variant_SHIFT)) & NOC_GICRLPI1_GICR1_IIDR_Variant_MASK) #define NOC_GICRLPI1_GICR1_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICRLPI1_GICR1_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_IIDR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_IIDR_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICRLPI1_GICR1_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICRLPI1_GICR1_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_IIDR_ProductID_SHIFT)) & NOC_GICRLPI1_GICR1_IIDR_ProductID_MASK) /*! @} */ /*! @name GICR1_TYPER - GICR1_TYPER */ /*! @{ */ #define NOC_GICRLPI1_GICR1_TYPER_PLPIS_MASK (0x1U) #define NOC_GICRLPI1_GICR1_TYPER_PLPIS_SHIFT (0U) /*! PLPIS - PLPIS */ #define NOC_GICRLPI1_GICR1_TYPER_PLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_PLPIS_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_PLPIS_MASK) #define NOC_GICRLPI1_GICR1_TYPER_VLPIS_MASK (0x2U) #define NOC_GICRLPI1_GICR1_TYPER_VLPIS_SHIFT (1U) /*! VLPIS - VLPIS */ #define NOC_GICRLPI1_GICR1_TYPER_VLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_VLPIS_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_VLPIS_MASK) #define NOC_GICRLPI1_GICR1_TYPER_Dirty_MASK (0x4U) #define NOC_GICRLPI1_GICR1_TYPER_Dirty_SHIFT (2U) /*! Dirty - Dirty */ #define NOC_GICRLPI1_GICR1_TYPER_Dirty(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_Dirty_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_Dirty_MASK) #define NOC_GICRLPI1_GICR1_TYPER_DirectLPI_MASK (0x8U) #define NOC_GICRLPI1_GICR1_TYPER_DirectLPI_SHIFT (3U) /*! DirectLPI - DirectLPI */ #define NOC_GICRLPI1_GICR1_TYPER_DirectLPI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_DirectLPI_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_DirectLPI_MASK) #define NOC_GICRLPI1_GICR1_TYPER_Last_MASK (0x10U) #define NOC_GICRLPI1_GICR1_TYPER_Last_SHIFT (4U) /*! Last - Last */ #define NOC_GICRLPI1_GICR1_TYPER_Last(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_Last_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_Last_MASK) #define NOC_GICRLPI1_GICR1_TYPER_DPGS_MASK (0x20U) #define NOC_GICRLPI1_GICR1_TYPER_DPGS_SHIFT (5U) /*! DPGS - DPGS */ #define NOC_GICRLPI1_GICR1_TYPER_DPGS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_DPGS_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_DPGS_MASK) #define NOC_GICRLPI1_GICR1_TYPER_MPAM_MASK (0x40U) #define NOC_GICRLPI1_GICR1_TYPER_MPAM_SHIFT (6U) /*! MPAM - MPAM */ #define NOC_GICRLPI1_GICR1_TYPER_MPAM(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_MPAM_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_MPAM_MASK) #define NOC_GICRLPI1_GICR1_TYPER_RVPEID_MASK (0x80U) #define NOC_GICRLPI1_GICR1_TYPER_RVPEID_SHIFT (7U) /*! RVPEID - RVPEID */ #define NOC_GICRLPI1_GICR1_TYPER_RVPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_RVPEID_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_RVPEID_MASK) #define NOC_GICRLPI1_GICR1_TYPER_ProcessorNumber_MASK (0xFFFF00U) #define NOC_GICRLPI1_GICR1_TYPER_ProcessorNumber_SHIFT (8U) /*! ProcessorNumber - ProcessorNumber */ #define NOC_GICRLPI1_GICR1_TYPER_ProcessorNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_ProcessorNumber_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_ProcessorNumber_MASK) #define NOC_GICRLPI1_GICR1_TYPER_CommonLPIAff_MASK (0x3000000U) #define NOC_GICRLPI1_GICR1_TYPER_CommonLPIAff_SHIFT (24U) /*! CommonLPIAff - CommonLPIAff */ #define NOC_GICRLPI1_GICR1_TYPER_CommonLPIAff(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_CommonLPIAff_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_CommonLPIAff_MASK) #define NOC_GICRLPI1_GICR1_TYPER_VSGI_MASK (0x4000000U) #define NOC_GICRLPI1_GICR1_TYPER_VSGI_SHIFT (26U) /*! VSGI - VSGI */ #define NOC_GICRLPI1_GICR1_TYPER_VSGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_VSGI_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_VSGI_MASK) #define NOC_GICRLPI1_GICR1_TYPER_PPInum_MASK (0xF8000000U) #define NOC_GICRLPI1_GICR1_TYPER_PPInum_SHIFT (27U) /*! PPInum - PPInum */ #define NOC_GICRLPI1_GICR1_TYPER_PPInum(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_PPInum_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_PPInum_MASK) #define NOC_GICRLPI1_GICR1_TYPER_AffinityValue_MASK (0xFFFFFFFF00000000U) #define NOC_GICRLPI1_GICR1_TYPER_AffinityValue_SHIFT (32U) /*! AffinityValue - AffinityValue */ #define NOC_GICRLPI1_GICR1_TYPER_AffinityValue(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_TYPER_AffinityValue_SHIFT)) & NOC_GICRLPI1_GICR1_TYPER_AffinityValue_MASK) /*! @} */ /*! @name GICR1_STATUSR - GICR1_STATUSR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICRLPI1_GICR1_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI1_GICR1_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_STATUSR_RESERVED_SHIFT)) & NOC_GICRLPI1_GICR1_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICR1_WAKER - GICR1_WAKER */ /*! @{ */ #define NOC_GICRLPI1_GICR1_WAKER_Sleep_MASK (0x1U) #define NOC_GICRLPI1_GICR1_WAKER_Sleep_SHIFT (0U) /*! Sleep - Sleep */ #define NOC_GICRLPI1_GICR1_WAKER_Sleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_WAKER_Sleep_SHIFT)) & NOC_GICRLPI1_GICR1_WAKER_Sleep_MASK) #define NOC_GICRLPI1_GICR1_WAKER_ProcessorSleep_MASK (0x2U) #define NOC_GICRLPI1_GICR1_WAKER_ProcessorSleep_SHIFT (1U) /*! ProcessorSleep - ProcessorSleep */ #define NOC_GICRLPI1_GICR1_WAKER_ProcessorSleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_WAKER_ProcessorSleep_SHIFT)) & NOC_GICRLPI1_GICR1_WAKER_ProcessorSleep_MASK) #define NOC_GICRLPI1_GICR1_WAKER_ChildrenAsleep_MASK (0x4U) #define NOC_GICRLPI1_GICR1_WAKER_ChildrenAsleep_SHIFT (2U) /*! ChildrenAsleep - ChildrenAsleep */ #define NOC_GICRLPI1_GICR1_WAKER_ChildrenAsleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_WAKER_ChildrenAsleep_SHIFT)) & NOC_GICRLPI1_GICR1_WAKER_ChildrenAsleep_MASK) #define NOC_GICRLPI1_GICR1_WAKER_RESERVED0_MASK (0x7FFFFFF8U) #define NOC_GICRLPI1_GICR1_WAKER_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_WAKER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_WAKER_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_WAKER_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_WAKER_Quiescent_MASK (0x80000000U) #define NOC_GICRLPI1_GICR1_WAKER_Quiescent_SHIFT (31U) /*! Quiescent - Quiescent */ #define NOC_GICRLPI1_GICR1_WAKER_Quiescent(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_WAKER_Quiescent_SHIFT)) & NOC_GICRLPI1_GICR1_WAKER_Quiescent_MASK) /*! @} */ /*! @name GICR1_MPAMIDR - GICR1_MPAMIDR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_MPAMIDR_PARTID_MAX_MASK (0x1FFU) #define NOC_GICRLPI1_GICR1_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define NOC_GICRLPI1_GICR1_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPAMIDR_PARTID_MAX_SHIFT)) & NOC_GICRLPI1_GICR1_MPAMIDR_PARTID_MAX_MASK) #define NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_MPAMIDR_PMG_MAX_MASK (0x10000U) #define NOC_GICRLPI1_GICR1_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define NOC_GICRLPI1_GICR1_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPAMIDR_PMG_MAX_SHIFT)) & NOC_GICRLPI1_GICR1_MPAMIDR_PMG_MAX_MASK) #define NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_MPAMIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR1_PARTIDR - GICR1_PARTIDR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PARTIDR_PARTID_MASK (0x1FFU) #define NOC_GICRLPI1_GICR1_PARTIDR_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define NOC_GICRLPI1_GICR1_PARTIDR_PARTID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PARTIDR_PARTID_SHIFT)) & NOC_GICRLPI1_GICR1_PARTIDR_PARTID_MASK) #define NOC_GICRLPI1_GICR1_PARTIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI1_GICR1_PARTIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PARTIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PARTIDR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PARTIDR_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_PARTIDR_PMG_MASK (0x10000U) #define NOC_GICRLPI1_GICR1_PARTIDR_PMG_SHIFT (16U) /*! PMG - PMG */ #define NOC_GICRLPI1_GICR1_PARTIDR_PMG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PARTIDR_PMG_SHIFT)) & NOC_GICRLPI1_GICR1_PARTIDR_PMG_MASK) #define NOC_GICRLPI1_GICR1_PARTIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI1_GICR1_PARTIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_PARTIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PARTIDR_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_PARTIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR1_FCTLR - GICR1_FCTLR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_FCTLR_SIP_MASK (0x1U) #define NOC_GICRLPI1_GICR1_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICRLPI1_GICR1_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_FCTLR_SIP_SHIFT)) & NOC_GICRLPI1_GICR1_FCTLR_SIP_MASK) #define NOC_GICRLPI1_GICR1_FCTLR_QDeny_MASK (0x2U) #define NOC_GICRLPI1_GICR1_FCTLR_QDeny_SHIFT (1U) /*! QDeny - QDeny */ #define NOC_GICRLPI1_GICR1_FCTLR_QDeny(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_FCTLR_QDeny_SHIFT)) & NOC_GICRLPI1_GICR1_FCTLR_QDeny_MASK) #define NOC_GICRLPI1_GICR1_FCTLR_CGO_MASK (0x1CU) #define NOC_GICRLPI1_GICR1_FCTLR_CGO_SHIFT (2U) /*! CGO - CGO */ #define NOC_GICRLPI1_GICR1_FCTLR_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_FCTLR_CGO_SHIFT)) & NOC_GICRLPI1_GICR1_FCTLR_CGO_MASK) #define NOC_GICRLPI1_GICR1_FCTLR_RESERVED0_MASK (0x3E0U) #define NOC_GICRLPI1_GICR1_FCTLR_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_FCTLR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_FCTLR_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_FCTLR_RESERVED1_MASK (0xFFFFFC00U) #define NOC_GICRLPI1_GICR1_FCTLR_RESERVED1_SHIFT (10U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_FCTLR_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_FCTLR_RESERVED1_MASK) /*! @} */ /*! @name GICR1_PWRR - GICR1_PWRR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PWRR_RDPD_MASK (0x1U) #define NOC_GICRLPI1_GICR1_PWRR_RDPD_SHIFT (0U) /*! RDPD - RDPD */ #define NOC_GICRLPI1_GICR1_PWRR_RDPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RDPD_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RDPD_MASK) #define NOC_GICRLPI1_GICR1_PWRR_RDAG_MASK (0x2U) #define NOC_GICRLPI1_GICR1_PWRR_RDAG_SHIFT (1U) /*! RDAG - RDAG */ #define NOC_GICRLPI1_GICR1_PWRR_RDAG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RDAG_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RDAG_MASK) #define NOC_GICRLPI1_GICR1_PWRR_RDGPD_MASK (0x4U) #define NOC_GICRLPI1_GICR1_PWRR_RDGPD_SHIFT (2U) /*! RDGPD - RDGPD */ #define NOC_GICRLPI1_GICR1_PWRR_RDGPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RDGPD_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RDGPD_MASK) #define NOC_GICRLPI1_GICR1_PWRR_RDGPO_MASK (0x8U) #define NOC_GICRLPI1_GICR1_PWRR_RDGPO_SHIFT (3U) /*! RDGPO - RDGPO */ #define NOC_GICRLPI1_GICR1_PWRR_RDGPO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RDGPO_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RDGPO_MASK) #define NOC_GICRLPI1_GICR1_PWRR_RESERVED0_MASK (0xF0U) #define NOC_GICRLPI1_GICR1_PWRR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PWRR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_PWRR_RDGO_MASK (0x7F00U) #define NOC_GICRLPI1_GICR1_PWRR_RDGO_SHIFT (8U) /*! RDGO - RDGO */ #define NOC_GICRLPI1_GICR1_PWRR_RDGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RDGO_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RDGO_MASK) #define NOC_GICRLPI1_GICR1_PWRR_RDG_MASK (0xFF8000U) #define NOC_GICRLPI1_GICR1_PWRR_RDG_SHIFT (15U) /*! RDG - RDG */ #define NOC_GICRLPI1_GICR1_PWRR_RDG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RDG_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RDG_MASK) #define NOC_GICRLPI1_GICR1_PWRR_RESERVED1_MASK (0xFF000000U) #define NOC_GICRLPI1_GICR1_PWRR_RESERVED1_SHIFT (24U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_PWRR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PWRR_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_PWRR_RESERVED1_MASK) /*! @} */ /*! @name GICR1_CLASS - GICR1_CLASS */ /*! @{ */ #define NOC_GICRLPI1_GICR1_CLASS_Class_MASK (0x1U) #define NOC_GICRLPI1_GICR1_CLASS_Class_SHIFT (0U) /*! Class - Class */ #define NOC_GICRLPI1_GICR1_CLASS_Class(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CLASS_Class_SHIFT)) & NOC_GICRLPI1_GICR1_CLASS_Class_MASK) #define NOC_GICRLPI1_GICR1_CLASS_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI1_GICR1_CLASS_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_CLASS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CLASS_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_CLASS_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PROPBASER - GICR1_PROPBASER */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PROPBASER_IDBits_MASK (0x1FU) #define NOC_GICRLPI1_GICR1_PROPBASER_IDBits_SHIFT (0U) /*! IDBits - IDBits */ #define NOC_GICRLPI1_GICR1_PROPBASER_IDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_IDBits_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_IDBits_MASK) #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED0_MASK (0x60U) #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_PROPBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI1_GICR1_PROPBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI1_GICR1_PROPBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_Cacheability_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_Cacheability_MASK) #define NOC_GICRLPI1_GICR1_PROPBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI1_GICR1_PROPBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI1_GICR1_PROPBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_Shareability_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_Shareability_MASK) #define NOC_GICRLPI1_GICR1_PROPBASER_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GICRLPI1_GICR1_PROPBASER_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI1_GICR1_PROPBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_PhysicalAddress_MASK) #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED1_MASK (0xFFFFF000000000U) #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED1_SHIFT (36U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_RESERVED1_MASK) #define NOC_GICRLPI1_GICR1_PROPBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI1_GICR1_PROPBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI1_GICR1_PROPBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_OuterCacheability_MASK) #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED2_MASK (0xF800000000000000U) #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED2_SHIFT (59U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI1_GICR1_PROPBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PROPBASER_RESERVED2_SHIFT)) & NOC_GICRLPI1_GICR1_PROPBASER_RESERVED2_MASK) /*! @} */ /*! @name GICR1_PENDBASER - GICR1_PENDBASER */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED0_MASK (0x7FU) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI1_GICR1_PENDBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI1_GICR1_PENDBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_Cacheability_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_Cacheability_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI1_GICR1_PENDBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI1_GICR1_PENDBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_Shareability_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_Shareability_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED1_MASK (0xF000U) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_RESERVED1_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_PhysicalAddress_MASK (0xFFFFF0000U) #define NOC_GICRLPI1_GICR1_PENDBASER_PhysicalAddress_SHIFT (16U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI1_GICR1_PENDBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_PhysicalAddress_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED2_MASK (0xFFFFF000000000U) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED2_SHIFT (36U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_RESERVED2_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_RESERVED2_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI1_GICR1_PENDBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI1_GICR1_PENDBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_OuterCacheability_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED3_MASK (0x3800000000000000U) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED3_SHIFT (59U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_RESERVED3_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_RESERVED3_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_PendingTableZero_MASK (0x4000000000000000U) #define NOC_GICRLPI1_GICR1_PENDBASER_PendingTableZero_SHIFT (62U) /*! PendingTableZero - PendingTableZero */ #define NOC_GICRLPI1_GICR1_PENDBASER_PendingTableZero(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_PendingTableZero_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_PendingTableZero_MASK) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED4_MASK (0x8000000000000000U) #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED4_SHIFT (63U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRLPI1_GICR1_PENDBASER_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_PENDBASER_RESERVED4_SHIFT)) & NOC_GICRLPI1_GICR1_PENDBASER_RESERVED4_MASK) /*! @} */ /*! @name GICR1_INVLPIR - GICR1_INVLPIR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_INVLPIR_IntID_MASK (0xFFFFFFFFU) #define NOC_GICRLPI1_GICR1_INVLPIR_IntID_SHIFT (0U) /*! IntID - IntID */ #define NOC_GICRLPI1_GICR1_INVLPIR_IntID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVLPIR_IntID_SHIFT)) & NOC_GICRLPI1_GICR1_INVLPIR_IntID_MASK) #define NOC_GICRLPI1_GICR1_INVLPIR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI1_GICR1_INVLPIR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI1_GICR1_INVLPIR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVLPIR_VPEID_SHIFT)) & NOC_GICRLPI1_GICR1_INVLPIR_VPEID_MASK) #define NOC_GICRLPI1_GICR1_INVLPIR_RESERVED0_MASK (0x7FFF000000000000U) #define NOC_GICRLPI1_GICR1_INVLPIR_RESERVED0_SHIFT (48U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_INVLPIR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVLPIR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_INVLPIR_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_INVLPIR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI1_GICR1_INVLPIR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI1_GICR1_INVLPIR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVLPIR_V_SHIFT)) & NOC_GICRLPI1_GICR1_INVLPIR_V_MASK) /*! @} */ /*! @name GICR1_INVALLR - GICR1_INVALLR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_INVALLR_RESERVED0_MASK (0xFFFFFFFFU) #define NOC_GICRLPI1_GICR1_INVALLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_INVALLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVALLR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_INVALLR_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_INVALLR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI1_GICR1_INVALLR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI1_GICR1_INVALLR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVALLR_VPEID_SHIFT)) & NOC_GICRLPI1_GICR1_INVALLR_VPEID_MASK) #define NOC_GICRLPI1_GICR1_INVALLR_RESERVED1_MASK (0x7FFF000000000000U) #define NOC_GICRLPI1_GICR1_INVALLR_RESERVED1_SHIFT (48U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_INVALLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVALLR_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_INVALLR_RESERVED1_MASK) #define NOC_GICRLPI1_GICR1_INVALLR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI1_GICR1_INVALLR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI1_GICR1_INVALLR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI1_GICR1_INVALLR_V_SHIFT)) & NOC_GICRLPI1_GICR1_INVALLR_V_MASK) /*! @} */ /*! @name GICR1_SYNCR - GICR1_SYNCR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_SYNCR_Busy_MASK (0x1U) #define NOC_GICRLPI1_GICR1_SYNCR_Busy_SHIFT (0U) /*! Busy - Busy */ #define NOC_GICRLPI1_GICR1_SYNCR_Busy(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_SYNCR_Busy_SHIFT)) & NOC_GICRLPI1_GICR1_SYNCR_Busy_MASK) #define NOC_GICRLPI1_GICR1_SYNCR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI1_GICR1_SYNCR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_SYNCR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_SYNCR_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_SYNCR_RESERVED0_MASK) /*! @} */ /*! @name GICR1_MPIDR - GICR1_MPIDR */ /*! @{ */ #define NOC_GICRLPI1_GICR1_MPIDR_Affinity0_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_MPIDR_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICRLPI1_GICR1_MPIDR_Affinity0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPIDR_Affinity0_SHIFT)) & NOC_GICRLPI1_GICR1_MPIDR_Affinity0_MASK) #define NOC_GICRLPI1_GICR1_MPIDR_Affinity1_MASK (0xFF00U) #define NOC_GICRLPI1_GICR1_MPIDR_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 */ #define NOC_GICRLPI1_GICR1_MPIDR_Affinity1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPIDR_Affinity1_SHIFT)) & NOC_GICRLPI1_GICR1_MPIDR_Affinity1_MASK) #define NOC_GICRLPI1_GICR1_MPIDR_Affinity2_MASK (0xFF0000U) #define NOC_GICRLPI1_GICR1_MPIDR_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICRLPI1_GICR1_MPIDR_Affinity2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPIDR_Affinity2_SHIFT)) & NOC_GICRLPI1_GICR1_MPIDR_Affinity2_MASK) #define NOC_GICRLPI1_GICR1_MPIDR_Affinity3_MASK (0xFF000000U) #define NOC_GICRLPI1_GICR1_MPIDR_Affinity3_SHIFT (24U) /*! Affinity3 - Affinity3 */ #define NOC_GICRLPI1_GICR1_MPIDR_Affinity3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_MPIDR_Affinity3_SHIFT)) & NOC_GICRLPI1_GICR1_MPIDR_Affinity3_MASK) /*! @} */ /*! @name GICR1_PIDR4 - GICR1_PIDR4 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR4_DES_2_MASK (0xFU) #define NOC_GICRLPI1_GICR1_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICRLPI1_GICR1_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR4_DES_2_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR4_DES_2_MASK) #define NOC_GICRLPI1_GICR1_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICRLPI1_GICR1_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICRLPI1_GICR1_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR4_SIZE_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR4_SIZE_MASK) #define NOC_GICRLPI1_GICR1_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR4_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PIDR5 - GICR1_PIDR5 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI1_GICR1_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR5_RESERVED_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR5_RESERVED_MASK) #define NOC_GICRLPI1_GICR1_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR5_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PIDR6 - GICR1_PIDR6 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI1_GICR1_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR6_RESERVED_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR6_RESERVED_MASK) #define NOC_GICRLPI1_GICR1_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR6_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PIDR7 - GICR1_PIDR7 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI1_GICR1_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR7_RESERVED_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR7_RESERVED_MASK) #define NOC_GICRLPI1_GICR1_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR7_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PIDR0 - GICR1_PIDR0 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICRLPI1_GICR1_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR0_PART_0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR0_PART_0_MASK) #define NOC_GICRLPI1_GICR1_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PIDR1 - GICR1_PIDR1 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR1_PART_1_MASK (0xFU) #define NOC_GICRLPI1_GICR1_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICRLPI1_GICR1_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR1_PART_1_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR1_PART_1_MASK) #define NOC_GICRLPI1_GICR1_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICRLPI1_GICR1_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICRLPI1_GICR1_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR1_DES_0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR1_DES_0_MASK) #define NOC_GICRLPI1_GICR1_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PIDR2 - GICR1_PIDR2 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR2_DES_1_MASK (0x7U) #define NOC_GICRLPI1_GICR1_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICRLPI1_GICR1_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR2_DES_1_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR2_DES_1_MASK) #define NOC_GICRLPI1_GICR1_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICRLPI1_GICR1_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICRLPI1_GICR1_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR2_JEDEC_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR2_JEDEC_MASK) #define NOC_GICRLPI1_GICR1_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICRLPI1_GICR1_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICRLPI1_GICR1_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR2_REVISION_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR2_REVISION_MASK) #define NOC_GICRLPI1_GICR1_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR1_PIDR3 - GICR1_PIDR3 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_PIDR3_CMOD_MASK (0x7U) #define NOC_GICRLPI1_GICR1_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICRLPI1_GICR1_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR3_CMOD_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR3_CMOD_MASK) #define NOC_GICRLPI1_GICR1_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICRLPI1_GICR1_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR3_RESERVED0_MASK) #define NOC_GICRLPI1_GICR1_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICRLPI1_GICR1_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICRLPI1_GICR1_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR3_REVAND_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR3_REVAND_MASK) #define NOC_GICRLPI1_GICR1_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI1_GICR1_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_PIDR3_RESERVED1_SHIFT)) & NOC_GICRLPI1_GICR1_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICR1_CIDR0 - GICR1_CIDR0 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICRLPI1_GICR1_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR0_PRMBL_0_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR0_PRMBL_0_MASK) #define NOC_GICRLPI1_GICR1_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR1_CIDR1 - GICR1_CIDR1 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICRLPI1_GICR1_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICRLPI1_GICR1_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR1_PRMBL_1_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR1_PRMBL_1_MASK) #define NOC_GICRLPI1_GICR1_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICRLPI1_GICR1_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICRLPI1_GICR1_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR1_CLASS_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR1_CLASS_MASK) #define NOC_GICRLPI1_GICR1_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR1_CIDR2 - GICR1_CIDR2 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICRLPI1_GICR1_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR2_PRMBL_2_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR2_PRMBL_2_MASK) #define NOC_GICRLPI1_GICR1_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR1_CIDR3 - GICR1_CIDR3 */ /*! @{ */ #define NOC_GICRLPI1_GICR1_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICRLPI1_GICR1_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICRLPI1_GICR1_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR3_PRMBL_3_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR3_PRMBL_3_MASK) #define NOC_GICRLPI1_GICR1_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI1_GICR1_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI1_GICR1_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI1_GICR1_CIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI1_GICR1_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRLPI1_Register_Masks */ /* NOC_GICRLPI1 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRLPI1 base address */ #define NOC__GIC__GICRLPI1_BASE (0x48080000u) /** Peripheral NOC__GIC__GICRLPI1 base pointer */ #define NOC__GIC__GICRLPI1 ((NOC_GICRLPI1_Type *)NOC__GIC__GICRLPI1_BASE) /** Array initializer of NOC_GICRLPI1 peripheral base addresses */ #define NOC_GICRLPI1_BASE_ADDRS { NOC__GIC__GICRLPI1_BASE } /** Array initializer of NOC_GICRLPI1 peripheral base pointers */ #define NOC_GICRLPI1_BASE_PTRS { NOC__GIC__GICRLPI1 } /*! * @} */ /* end of group NOC_GICRLPI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRLPI2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI2_Peripheral_Access_Layer NOC_GICRLPI2 Peripheral Access Layer * @{ */ /** NOC_GICRLPI2 - Register Layout Typedef */ typedef struct { __IO uint32_t GICR2_CTLR; /**< GICR2_CTLR, offset: 0x0 */ __I uint32_t GICR2_IIDR; /**< GICR2_IIDR, offset: 0x4 */ __I uint64_t GICR2_TYPER; /**< GICR2_TYPER, offset: 0x8 */ __I uint32_t GICR2_STATUSR; /**< GICR2_STATUSR, offset: 0x10 */ __IO uint32_t GICR2_WAKER; /**< GICR2_WAKER, offset: 0x14 */ __I uint32_t GICR2_MPAMIDR; /**< GICR2_MPAMIDR, offset: 0x18 */ __IO uint32_t GICR2_PARTIDR; /**< GICR2_PARTIDR, offset: 0x1C */ __IO uint32_t GICR2_FCTLR; /**< GICR2_FCTLR, offset: 0x20 */ __IO uint32_t GICR2_PWRR; /**< GICR2_PWRR, offset: 0x24 */ __IO uint32_t GICR2_CLASS; /**< GICR2_CLASS, offset: 0x28 */ uint8_t RESERVED_0[68]; __IO uint64_t GICR2_PROPBASER; /**< GICR2_PROPBASER, offset: 0x70 */ __IO uint64_t GICR2_PENDBASER; /**< GICR2_PENDBASER, offset: 0x78 */ uint8_t RESERVED_1[32]; __O uint64_t GICR2_INVLPIR; /**< GICR2_INVLPIR, offset: 0xA0 */ uint8_t RESERVED_2[8]; __O uint64_t GICR2_INVALLR; /**< GICR2_INVALLR, offset: 0xB0 */ uint8_t RESERVED_3[8]; __I uint32_t GICR2_SYNCR; /**< GICR2_SYNCR, offset: 0xC0 */ uint8_t RESERVED_4[60]; __O uint32_t GICR2_MPIDR; /**< GICR2_MPIDR, offset: 0x100 */ uint8_t RESERVED_5[65228]; __I uint32_t GICR2_PIDR4; /**< GICR2_PIDR4, offset: 0xFFD0 */ __I uint32_t GICR2_PIDR5; /**< GICR2_PIDR5, offset: 0xFFD4 */ __I uint32_t GICR2_PIDR6; /**< GICR2_PIDR6, offset: 0xFFD8 */ __I uint32_t GICR2_PIDR7; /**< GICR2_PIDR7, offset: 0xFFDC */ __I uint32_t GICR2_PIDR0; /**< GICR2_PIDR0, offset: 0xFFE0 */ __I uint32_t GICR2_PIDR1; /**< GICR2_PIDR1, offset: 0xFFE4 */ __I uint32_t GICR2_PIDR2; /**< GICR2_PIDR2, offset: 0xFFE8 */ __I uint32_t GICR2_PIDR3; /**< GICR2_PIDR3, offset: 0xFFEC */ __I uint32_t GICR2_CIDR0; /**< GICR2_CIDR0, offset: 0xFFF0 */ __I uint32_t GICR2_CIDR1; /**< GICR2_CIDR1, offset: 0xFFF4 */ __I uint32_t GICR2_CIDR2; /**< GICR2_CIDR2, offset: 0xFFF8 */ __I uint32_t GICR2_CIDR3; /**< GICR2_CIDR3, offset: 0xFFFC */ } NOC_GICRLPI2_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRLPI2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI2_Register_Masks NOC_GICRLPI2 Register Masks * @{ */ /*! @name GICR2_CTLR - GICR2_CTLR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_CTLR_EnableLPIs_MASK (0x1U) #define NOC_GICRLPI2_GICR2_CTLR_EnableLPIs_SHIFT (0U) /*! EnableLPIs - EnableLPIs */ #define NOC_GICRLPI2_GICR2_CTLR_EnableLPIs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_EnableLPIs_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_EnableLPIs_MASK) #define NOC_GICRLPI2_GICR2_CTLR_CES_MASK (0x2U) #define NOC_GICRLPI2_GICR2_CTLR_CES_SHIFT (1U) /*! CES - CES */ #define NOC_GICRLPI2_GICR2_CTLR_CES(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_CES_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_CES_MASK) #define NOC_GICRLPI2_GICR2_CTLR_IR_MASK (0x4U) #define NOC_GICRLPI2_GICR2_CTLR_IR_SHIFT (2U) /*! IR - IR */ #define NOC_GICRLPI2_GICR2_CTLR_IR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_IR_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_IR_MASK) #define NOC_GICRLPI2_GICR2_CTLR_RWP_MASK (0x8U) #define NOC_GICRLPI2_GICR2_CTLR_RWP_SHIFT (3U) /*! RWP - RWP */ #define NOC_GICRLPI2_GICR2_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_RWP_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_RWP_MASK) #define NOC_GICRLPI2_GICR2_CTLR_RESERVED1_MASK (0xFFFFF0U) #define NOC_GICRLPI2_GICR2_CTLR_RESERVED1_SHIFT (4U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_RESERVED1_MASK) #define NOC_GICRLPI2_GICR2_CTLR_DPG0_MASK (0x1000000U) #define NOC_GICRLPI2_GICR2_CTLR_DPG0_SHIFT (24U) /*! DPG0 - DPG0 */ #define NOC_GICRLPI2_GICR2_CTLR_DPG0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_DPG0_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_DPG0_MASK) #define NOC_GICRLPI2_GICR2_CTLR_DPG1NS_MASK (0x2000000U) #define NOC_GICRLPI2_GICR2_CTLR_DPG1NS_SHIFT (25U) /*! DPG1NS - DPG1NS */ #define NOC_GICRLPI2_GICR2_CTLR_DPG1NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_DPG1NS_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_DPG1NS_MASK) #define NOC_GICRLPI2_GICR2_CTLR_DPG1S_MASK (0x4000000U) #define NOC_GICRLPI2_GICR2_CTLR_DPG1S_SHIFT (26U) /*! DPG1S - DPG1S */ #define NOC_GICRLPI2_GICR2_CTLR_DPG1S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_DPG1S_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_DPG1S_MASK) #define NOC_GICRLPI2_GICR2_CTLR_RESERVED2_MASK (0x78000000U) #define NOC_GICRLPI2_GICR2_CTLR_RESERVED2_SHIFT (27U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI2_GICR2_CTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_RESERVED2_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_RESERVED2_MASK) #define NOC_GICRLPI2_GICR2_CTLR_UWP_MASK (0x80000000U) #define NOC_GICRLPI2_GICR2_CTLR_UWP_SHIFT (31U) /*! UWP - UWP */ #define NOC_GICRLPI2_GICR2_CTLR_UWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CTLR_UWP_SHIFT)) & NOC_GICRLPI2_GICR2_CTLR_UWP_MASK) /*! @} */ /*! @name GICR2_IIDR - GICR2_IIDR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICRLPI2_GICR2_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICRLPI2_GICR2_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_IIDR_Implementer_SHIFT)) & NOC_GICRLPI2_GICR2_IIDR_Implementer_MASK) #define NOC_GICRLPI2_GICR2_IIDR_Revision_MASK (0xF000U) #define NOC_GICRLPI2_GICR2_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICRLPI2_GICR2_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_IIDR_Revision_SHIFT)) & NOC_GICRLPI2_GICR2_IIDR_Revision_MASK) #define NOC_GICRLPI2_GICR2_IIDR_Variant_MASK (0xF0000U) #define NOC_GICRLPI2_GICR2_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICRLPI2_GICR2_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_IIDR_Variant_SHIFT)) & NOC_GICRLPI2_GICR2_IIDR_Variant_MASK) #define NOC_GICRLPI2_GICR2_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICRLPI2_GICR2_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_IIDR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_IIDR_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICRLPI2_GICR2_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICRLPI2_GICR2_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_IIDR_ProductID_SHIFT)) & NOC_GICRLPI2_GICR2_IIDR_ProductID_MASK) /*! @} */ /*! @name GICR2_TYPER - GICR2_TYPER */ /*! @{ */ #define NOC_GICRLPI2_GICR2_TYPER_PLPIS_MASK (0x1U) #define NOC_GICRLPI2_GICR2_TYPER_PLPIS_SHIFT (0U) /*! PLPIS - PLPIS */ #define NOC_GICRLPI2_GICR2_TYPER_PLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_PLPIS_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_PLPIS_MASK) #define NOC_GICRLPI2_GICR2_TYPER_VLPIS_MASK (0x2U) #define NOC_GICRLPI2_GICR2_TYPER_VLPIS_SHIFT (1U) /*! VLPIS - VLPIS */ #define NOC_GICRLPI2_GICR2_TYPER_VLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_VLPIS_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_VLPIS_MASK) #define NOC_GICRLPI2_GICR2_TYPER_Dirty_MASK (0x4U) #define NOC_GICRLPI2_GICR2_TYPER_Dirty_SHIFT (2U) /*! Dirty - Dirty */ #define NOC_GICRLPI2_GICR2_TYPER_Dirty(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_Dirty_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_Dirty_MASK) #define NOC_GICRLPI2_GICR2_TYPER_DirectLPI_MASK (0x8U) #define NOC_GICRLPI2_GICR2_TYPER_DirectLPI_SHIFT (3U) /*! DirectLPI - DirectLPI */ #define NOC_GICRLPI2_GICR2_TYPER_DirectLPI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_DirectLPI_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_DirectLPI_MASK) #define NOC_GICRLPI2_GICR2_TYPER_Last_MASK (0x10U) #define NOC_GICRLPI2_GICR2_TYPER_Last_SHIFT (4U) /*! Last - Last */ #define NOC_GICRLPI2_GICR2_TYPER_Last(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_Last_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_Last_MASK) #define NOC_GICRLPI2_GICR2_TYPER_DPGS_MASK (0x20U) #define NOC_GICRLPI2_GICR2_TYPER_DPGS_SHIFT (5U) /*! DPGS - DPGS */ #define NOC_GICRLPI2_GICR2_TYPER_DPGS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_DPGS_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_DPGS_MASK) #define NOC_GICRLPI2_GICR2_TYPER_MPAM_MASK (0x40U) #define NOC_GICRLPI2_GICR2_TYPER_MPAM_SHIFT (6U) /*! MPAM - MPAM */ #define NOC_GICRLPI2_GICR2_TYPER_MPAM(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_MPAM_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_MPAM_MASK) #define NOC_GICRLPI2_GICR2_TYPER_RVPEID_MASK (0x80U) #define NOC_GICRLPI2_GICR2_TYPER_RVPEID_SHIFT (7U) /*! RVPEID - RVPEID */ #define NOC_GICRLPI2_GICR2_TYPER_RVPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_RVPEID_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_RVPEID_MASK) #define NOC_GICRLPI2_GICR2_TYPER_ProcessorNumber_MASK (0xFFFF00U) #define NOC_GICRLPI2_GICR2_TYPER_ProcessorNumber_SHIFT (8U) /*! ProcessorNumber - ProcessorNumber */ #define NOC_GICRLPI2_GICR2_TYPER_ProcessorNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_ProcessorNumber_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_ProcessorNumber_MASK) #define NOC_GICRLPI2_GICR2_TYPER_CommonLPIAff_MASK (0x3000000U) #define NOC_GICRLPI2_GICR2_TYPER_CommonLPIAff_SHIFT (24U) /*! CommonLPIAff - CommonLPIAff */ #define NOC_GICRLPI2_GICR2_TYPER_CommonLPIAff(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_CommonLPIAff_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_CommonLPIAff_MASK) #define NOC_GICRLPI2_GICR2_TYPER_VSGI_MASK (0x4000000U) #define NOC_GICRLPI2_GICR2_TYPER_VSGI_SHIFT (26U) /*! VSGI - VSGI */ #define NOC_GICRLPI2_GICR2_TYPER_VSGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_VSGI_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_VSGI_MASK) #define NOC_GICRLPI2_GICR2_TYPER_PPInum_MASK (0xF8000000U) #define NOC_GICRLPI2_GICR2_TYPER_PPInum_SHIFT (27U) /*! PPInum - PPInum */ #define NOC_GICRLPI2_GICR2_TYPER_PPInum(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_PPInum_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_PPInum_MASK) #define NOC_GICRLPI2_GICR2_TYPER_AffinityValue_MASK (0xFFFFFFFF00000000U) #define NOC_GICRLPI2_GICR2_TYPER_AffinityValue_SHIFT (32U) /*! AffinityValue - AffinityValue */ #define NOC_GICRLPI2_GICR2_TYPER_AffinityValue(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_TYPER_AffinityValue_SHIFT)) & NOC_GICRLPI2_GICR2_TYPER_AffinityValue_MASK) /*! @} */ /*! @name GICR2_STATUSR - GICR2_STATUSR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICRLPI2_GICR2_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI2_GICR2_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_STATUSR_RESERVED_SHIFT)) & NOC_GICRLPI2_GICR2_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICR2_WAKER - GICR2_WAKER */ /*! @{ */ #define NOC_GICRLPI2_GICR2_WAKER_Sleep_MASK (0x1U) #define NOC_GICRLPI2_GICR2_WAKER_Sleep_SHIFT (0U) /*! Sleep - Sleep */ #define NOC_GICRLPI2_GICR2_WAKER_Sleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_WAKER_Sleep_SHIFT)) & NOC_GICRLPI2_GICR2_WAKER_Sleep_MASK) #define NOC_GICRLPI2_GICR2_WAKER_ProcessorSleep_MASK (0x2U) #define NOC_GICRLPI2_GICR2_WAKER_ProcessorSleep_SHIFT (1U) /*! ProcessorSleep - ProcessorSleep */ #define NOC_GICRLPI2_GICR2_WAKER_ProcessorSleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_WAKER_ProcessorSleep_SHIFT)) & NOC_GICRLPI2_GICR2_WAKER_ProcessorSleep_MASK) #define NOC_GICRLPI2_GICR2_WAKER_ChildrenAsleep_MASK (0x4U) #define NOC_GICRLPI2_GICR2_WAKER_ChildrenAsleep_SHIFT (2U) /*! ChildrenAsleep - ChildrenAsleep */ #define NOC_GICRLPI2_GICR2_WAKER_ChildrenAsleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_WAKER_ChildrenAsleep_SHIFT)) & NOC_GICRLPI2_GICR2_WAKER_ChildrenAsleep_MASK) #define NOC_GICRLPI2_GICR2_WAKER_RESERVED0_MASK (0x7FFFFFF8U) #define NOC_GICRLPI2_GICR2_WAKER_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_WAKER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_WAKER_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_WAKER_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_WAKER_Quiescent_MASK (0x80000000U) #define NOC_GICRLPI2_GICR2_WAKER_Quiescent_SHIFT (31U) /*! Quiescent - Quiescent */ #define NOC_GICRLPI2_GICR2_WAKER_Quiescent(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_WAKER_Quiescent_SHIFT)) & NOC_GICRLPI2_GICR2_WAKER_Quiescent_MASK) /*! @} */ /*! @name GICR2_MPAMIDR - GICR2_MPAMIDR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_MPAMIDR_PARTID_MAX_MASK (0x1FFU) #define NOC_GICRLPI2_GICR2_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define NOC_GICRLPI2_GICR2_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPAMIDR_PARTID_MAX_SHIFT)) & NOC_GICRLPI2_GICR2_MPAMIDR_PARTID_MAX_MASK) #define NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_MPAMIDR_PMG_MAX_MASK (0x10000U) #define NOC_GICRLPI2_GICR2_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define NOC_GICRLPI2_GICR2_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPAMIDR_PMG_MAX_SHIFT)) & NOC_GICRLPI2_GICR2_MPAMIDR_PMG_MAX_MASK) #define NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_MPAMIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR2_PARTIDR - GICR2_PARTIDR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PARTIDR_PARTID_MASK (0x1FFU) #define NOC_GICRLPI2_GICR2_PARTIDR_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define NOC_GICRLPI2_GICR2_PARTIDR_PARTID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PARTIDR_PARTID_SHIFT)) & NOC_GICRLPI2_GICR2_PARTIDR_PARTID_MASK) #define NOC_GICRLPI2_GICR2_PARTIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI2_GICR2_PARTIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PARTIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PARTIDR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PARTIDR_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_PARTIDR_PMG_MASK (0x10000U) #define NOC_GICRLPI2_GICR2_PARTIDR_PMG_SHIFT (16U) /*! PMG - PMG */ #define NOC_GICRLPI2_GICR2_PARTIDR_PMG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PARTIDR_PMG_SHIFT)) & NOC_GICRLPI2_GICR2_PARTIDR_PMG_MASK) #define NOC_GICRLPI2_GICR2_PARTIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI2_GICR2_PARTIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_PARTIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PARTIDR_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_PARTIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR2_FCTLR - GICR2_FCTLR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_FCTLR_SIP_MASK (0x1U) #define NOC_GICRLPI2_GICR2_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICRLPI2_GICR2_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_FCTLR_SIP_SHIFT)) & NOC_GICRLPI2_GICR2_FCTLR_SIP_MASK) #define NOC_GICRLPI2_GICR2_FCTLR_QDeny_MASK (0x2U) #define NOC_GICRLPI2_GICR2_FCTLR_QDeny_SHIFT (1U) /*! QDeny - QDeny */ #define NOC_GICRLPI2_GICR2_FCTLR_QDeny(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_FCTLR_QDeny_SHIFT)) & NOC_GICRLPI2_GICR2_FCTLR_QDeny_MASK) #define NOC_GICRLPI2_GICR2_FCTLR_CGO_MASK (0x1CU) #define NOC_GICRLPI2_GICR2_FCTLR_CGO_SHIFT (2U) /*! CGO - CGO */ #define NOC_GICRLPI2_GICR2_FCTLR_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_FCTLR_CGO_SHIFT)) & NOC_GICRLPI2_GICR2_FCTLR_CGO_MASK) #define NOC_GICRLPI2_GICR2_FCTLR_RESERVED0_MASK (0x3E0U) #define NOC_GICRLPI2_GICR2_FCTLR_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_FCTLR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_FCTLR_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_FCTLR_RESERVED1_MASK (0xFFFFFC00U) #define NOC_GICRLPI2_GICR2_FCTLR_RESERVED1_SHIFT (10U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_FCTLR_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_FCTLR_RESERVED1_MASK) /*! @} */ /*! @name GICR2_PWRR - GICR2_PWRR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PWRR_RDPD_MASK (0x1U) #define NOC_GICRLPI2_GICR2_PWRR_RDPD_SHIFT (0U) /*! RDPD - RDPD */ #define NOC_GICRLPI2_GICR2_PWRR_RDPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RDPD_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RDPD_MASK) #define NOC_GICRLPI2_GICR2_PWRR_RDAG_MASK (0x2U) #define NOC_GICRLPI2_GICR2_PWRR_RDAG_SHIFT (1U) /*! RDAG - RDAG */ #define NOC_GICRLPI2_GICR2_PWRR_RDAG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RDAG_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RDAG_MASK) #define NOC_GICRLPI2_GICR2_PWRR_RDGPD_MASK (0x4U) #define NOC_GICRLPI2_GICR2_PWRR_RDGPD_SHIFT (2U) /*! RDGPD - RDGPD */ #define NOC_GICRLPI2_GICR2_PWRR_RDGPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RDGPD_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RDGPD_MASK) #define NOC_GICRLPI2_GICR2_PWRR_RDGPO_MASK (0x8U) #define NOC_GICRLPI2_GICR2_PWRR_RDGPO_SHIFT (3U) /*! RDGPO - RDGPO */ #define NOC_GICRLPI2_GICR2_PWRR_RDGPO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RDGPO_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RDGPO_MASK) #define NOC_GICRLPI2_GICR2_PWRR_RESERVED0_MASK (0xF0U) #define NOC_GICRLPI2_GICR2_PWRR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PWRR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_PWRR_RDGO_MASK (0x7F00U) #define NOC_GICRLPI2_GICR2_PWRR_RDGO_SHIFT (8U) /*! RDGO - RDGO */ #define NOC_GICRLPI2_GICR2_PWRR_RDGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RDGO_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RDGO_MASK) #define NOC_GICRLPI2_GICR2_PWRR_RDG_MASK (0xFF8000U) #define NOC_GICRLPI2_GICR2_PWRR_RDG_SHIFT (15U) /*! RDG - RDG */ #define NOC_GICRLPI2_GICR2_PWRR_RDG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RDG_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RDG_MASK) #define NOC_GICRLPI2_GICR2_PWRR_RESERVED1_MASK (0xFF000000U) #define NOC_GICRLPI2_GICR2_PWRR_RESERVED1_SHIFT (24U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_PWRR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PWRR_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_PWRR_RESERVED1_MASK) /*! @} */ /*! @name GICR2_CLASS - GICR2_CLASS */ /*! @{ */ #define NOC_GICRLPI2_GICR2_CLASS_Class_MASK (0x1U) #define NOC_GICRLPI2_GICR2_CLASS_Class_SHIFT (0U) /*! Class - Class */ #define NOC_GICRLPI2_GICR2_CLASS_Class(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CLASS_Class_SHIFT)) & NOC_GICRLPI2_GICR2_CLASS_Class_MASK) #define NOC_GICRLPI2_GICR2_CLASS_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI2_GICR2_CLASS_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_CLASS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CLASS_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_CLASS_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PROPBASER - GICR2_PROPBASER */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PROPBASER_IDBits_MASK (0x1FU) #define NOC_GICRLPI2_GICR2_PROPBASER_IDBits_SHIFT (0U) /*! IDBits - IDBits */ #define NOC_GICRLPI2_GICR2_PROPBASER_IDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_IDBits_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_IDBits_MASK) #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED0_MASK (0x60U) #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_PROPBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI2_GICR2_PROPBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI2_GICR2_PROPBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_Cacheability_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_Cacheability_MASK) #define NOC_GICRLPI2_GICR2_PROPBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI2_GICR2_PROPBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI2_GICR2_PROPBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_Shareability_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_Shareability_MASK) #define NOC_GICRLPI2_GICR2_PROPBASER_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GICRLPI2_GICR2_PROPBASER_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI2_GICR2_PROPBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_PhysicalAddress_MASK) #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED1_MASK (0xFFFFF000000000U) #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED1_SHIFT (36U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_RESERVED1_MASK) #define NOC_GICRLPI2_GICR2_PROPBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI2_GICR2_PROPBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI2_GICR2_PROPBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_OuterCacheability_MASK) #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED2_MASK (0xF800000000000000U) #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED2_SHIFT (59U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI2_GICR2_PROPBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PROPBASER_RESERVED2_SHIFT)) & NOC_GICRLPI2_GICR2_PROPBASER_RESERVED2_MASK) /*! @} */ /*! @name GICR2_PENDBASER - GICR2_PENDBASER */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED0_MASK (0x7FU) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI2_GICR2_PENDBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI2_GICR2_PENDBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_Cacheability_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_Cacheability_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI2_GICR2_PENDBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI2_GICR2_PENDBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_Shareability_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_Shareability_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED1_MASK (0xF000U) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_RESERVED1_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_PhysicalAddress_MASK (0xFFFFF0000U) #define NOC_GICRLPI2_GICR2_PENDBASER_PhysicalAddress_SHIFT (16U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI2_GICR2_PENDBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_PhysicalAddress_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED2_MASK (0xFFFFF000000000U) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED2_SHIFT (36U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_RESERVED2_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_RESERVED2_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI2_GICR2_PENDBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI2_GICR2_PENDBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_OuterCacheability_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED3_MASK (0x3800000000000000U) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED3_SHIFT (59U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_RESERVED3_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_RESERVED3_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_PendingTableZero_MASK (0x4000000000000000U) #define NOC_GICRLPI2_GICR2_PENDBASER_PendingTableZero_SHIFT (62U) /*! PendingTableZero - PendingTableZero */ #define NOC_GICRLPI2_GICR2_PENDBASER_PendingTableZero(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_PendingTableZero_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_PendingTableZero_MASK) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED4_MASK (0x8000000000000000U) #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED4_SHIFT (63U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRLPI2_GICR2_PENDBASER_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_PENDBASER_RESERVED4_SHIFT)) & NOC_GICRLPI2_GICR2_PENDBASER_RESERVED4_MASK) /*! @} */ /*! @name GICR2_INVLPIR - GICR2_INVLPIR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_INVLPIR_IntID_MASK (0xFFFFFFFFU) #define NOC_GICRLPI2_GICR2_INVLPIR_IntID_SHIFT (0U) /*! IntID - IntID */ #define NOC_GICRLPI2_GICR2_INVLPIR_IntID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVLPIR_IntID_SHIFT)) & NOC_GICRLPI2_GICR2_INVLPIR_IntID_MASK) #define NOC_GICRLPI2_GICR2_INVLPIR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI2_GICR2_INVLPIR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI2_GICR2_INVLPIR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVLPIR_VPEID_SHIFT)) & NOC_GICRLPI2_GICR2_INVLPIR_VPEID_MASK) #define NOC_GICRLPI2_GICR2_INVLPIR_RESERVED0_MASK (0x7FFF000000000000U) #define NOC_GICRLPI2_GICR2_INVLPIR_RESERVED0_SHIFT (48U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_INVLPIR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVLPIR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_INVLPIR_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_INVLPIR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI2_GICR2_INVLPIR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI2_GICR2_INVLPIR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVLPIR_V_SHIFT)) & NOC_GICRLPI2_GICR2_INVLPIR_V_MASK) /*! @} */ /*! @name GICR2_INVALLR - GICR2_INVALLR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_INVALLR_RESERVED0_MASK (0xFFFFFFFFU) #define NOC_GICRLPI2_GICR2_INVALLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_INVALLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVALLR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_INVALLR_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_INVALLR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI2_GICR2_INVALLR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI2_GICR2_INVALLR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVALLR_VPEID_SHIFT)) & NOC_GICRLPI2_GICR2_INVALLR_VPEID_MASK) #define NOC_GICRLPI2_GICR2_INVALLR_RESERVED1_MASK (0x7FFF000000000000U) #define NOC_GICRLPI2_GICR2_INVALLR_RESERVED1_SHIFT (48U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_INVALLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVALLR_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_INVALLR_RESERVED1_MASK) #define NOC_GICRLPI2_GICR2_INVALLR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI2_GICR2_INVALLR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI2_GICR2_INVALLR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI2_GICR2_INVALLR_V_SHIFT)) & NOC_GICRLPI2_GICR2_INVALLR_V_MASK) /*! @} */ /*! @name GICR2_SYNCR - GICR2_SYNCR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_SYNCR_Busy_MASK (0x1U) #define NOC_GICRLPI2_GICR2_SYNCR_Busy_SHIFT (0U) /*! Busy - Busy */ #define NOC_GICRLPI2_GICR2_SYNCR_Busy(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_SYNCR_Busy_SHIFT)) & NOC_GICRLPI2_GICR2_SYNCR_Busy_MASK) #define NOC_GICRLPI2_GICR2_SYNCR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI2_GICR2_SYNCR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_SYNCR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_SYNCR_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_SYNCR_RESERVED0_MASK) /*! @} */ /*! @name GICR2_MPIDR - GICR2_MPIDR */ /*! @{ */ #define NOC_GICRLPI2_GICR2_MPIDR_Affinity0_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_MPIDR_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICRLPI2_GICR2_MPIDR_Affinity0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPIDR_Affinity0_SHIFT)) & NOC_GICRLPI2_GICR2_MPIDR_Affinity0_MASK) #define NOC_GICRLPI2_GICR2_MPIDR_Affinity1_MASK (0xFF00U) #define NOC_GICRLPI2_GICR2_MPIDR_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 */ #define NOC_GICRLPI2_GICR2_MPIDR_Affinity1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPIDR_Affinity1_SHIFT)) & NOC_GICRLPI2_GICR2_MPIDR_Affinity1_MASK) #define NOC_GICRLPI2_GICR2_MPIDR_Affinity2_MASK (0xFF0000U) #define NOC_GICRLPI2_GICR2_MPIDR_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICRLPI2_GICR2_MPIDR_Affinity2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPIDR_Affinity2_SHIFT)) & NOC_GICRLPI2_GICR2_MPIDR_Affinity2_MASK) #define NOC_GICRLPI2_GICR2_MPIDR_Affinity3_MASK (0xFF000000U) #define NOC_GICRLPI2_GICR2_MPIDR_Affinity3_SHIFT (24U) /*! Affinity3 - Affinity3 */ #define NOC_GICRLPI2_GICR2_MPIDR_Affinity3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_MPIDR_Affinity3_SHIFT)) & NOC_GICRLPI2_GICR2_MPIDR_Affinity3_MASK) /*! @} */ /*! @name GICR2_PIDR4 - GICR2_PIDR4 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR4_DES_2_MASK (0xFU) #define NOC_GICRLPI2_GICR2_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICRLPI2_GICR2_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR4_DES_2_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR4_DES_2_MASK) #define NOC_GICRLPI2_GICR2_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICRLPI2_GICR2_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICRLPI2_GICR2_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR4_SIZE_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR4_SIZE_MASK) #define NOC_GICRLPI2_GICR2_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR4_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PIDR5 - GICR2_PIDR5 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI2_GICR2_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR5_RESERVED_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR5_RESERVED_MASK) #define NOC_GICRLPI2_GICR2_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR5_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PIDR6 - GICR2_PIDR6 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI2_GICR2_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR6_RESERVED_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR6_RESERVED_MASK) #define NOC_GICRLPI2_GICR2_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR6_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PIDR7 - GICR2_PIDR7 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI2_GICR2_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR7_RESERVED_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR7_RESERVED_MASK) #define NOC_GICRLPI2_GICR2_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR7_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PIDR0 - GICR2_PIDR0 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICRLPI2_GICR2_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR0_PART_0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR0_PART_0_MASK) #define NOC_GICRLPI2_GICR2_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PIDR1 - GICR2_PIDR1 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR1_PART_1_MASK (0xFU) #define NOC_GICRLPI2_GICR2_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICRLPI2_GICR2_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR1_PART_1_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR1_PART_1_MASK) #define NOC_GICRLPI2_GICR2_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICRLPI2_GICR2_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICRLPI2_GICR2_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR1_DES_0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR1_DES_0_MASK) #define NOC_GICRLPI2_GICR2_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PIDR2 - GICR2_PIDR2 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR2_DES_1_MASK (0x7U) #define NOC_GICRLPI2_GICR2_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICRLPI2_GICR2_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR2_DES_1_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR2_DES_1_MASK) #define NOC_GICRLPI2_GICR2_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICRLPI2_GICR2_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICRLPI2_GICR2_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR2_JEDEC_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR2_JEDEC_MASK) #define NOC_GICRLPI2_GICR2_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICRLPI2_GICR2_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICRLPI2_GICR2_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR2_REVISION_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR2_REVISION_MASK) #define NOC_GICRLPI2_GICR2_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR2_PIDR3 - GICR2_PIDR3 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_PIDR3_CMOD_MASK (0x7U) #define NOC_GICRLPI2_GICR2_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICRLPI2_GICR2_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR3_CMOD_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR3_CMOD_MASK) #define NOC_GICRLPI2_GICR2_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICRLPI2_GICR2_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR3_RESERVED0_MASK) #define NOC_GICRLPI2_GICR2_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICRLPI2_GICR2_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICRLPI2_GICR2_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR3_REVAND_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR3_REVAND_MASK) #define NOC_GICRLPI2_GICR2_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI2_GICR2_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_PIDR3_RESERVED1_SHIFT)) & NOC_GICRLPI2_GICR2_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICR2_CIDR0 - GICR2_CIDR0 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICRLPI2_GICR2_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR0_PRMBL_0_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR0_PRMBL_0_MASK) #define NOC_GICRLPI2_GICR2_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR2_CIDR1 - GICR2_CIDR1 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICRLPI2_GICR2_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICRLPI2_GICR2_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR1_PRMBL_1_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR1_PRMBL_1_MASK) #define NOC_GICRLPI2_GICR2_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICRLPI2_GICR2_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICRLPI2_GICR2_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR1_CLASS_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR1_CLASS_MASK) #define NOC_GICRLPI2_GICR2_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR2_CIDR2 - GICR2_CIDR2 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICRLPI2_GICR2_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR2_PRMBL_2_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR2_PRMBL_2_MASK) #define NOC_GICRLPI2_GICR2_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR2_CIDR3 - GICR2_CIDR3 */ /*! @{ */ #define NOC_GICRLPI2_GICR2_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICRLPI2_GICR2_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICRLPI2_GICR2_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR3_PRMBL_3_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR3_PRMBL_3_MASK) #define NOC_GICRLPI2_GICR2_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI2_GICR2_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI2_GICR2_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI2_GICR2_CIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI2_GICR2_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRLPI2_Register_Masks */ /* NOC_GICRLPI2 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRLPI2 base address */ #define NOC__GIC__GICRLPI2_BASE (0x480A0000u) /** Peripheral NOC__GIC__GICRLPI2 base pointer */ #define NOC__GIC__GICRLPI2 ((NOC_GICRLPI2_Type *)NOC__GIC__GICRLPI2_BASE) /** Array initializer of NOC_GICRLPI2 peripheral base addresses */ #define NOC_GICRLPI2_BASE_ADDRS { NOC__GIC__GICRLPI2_BASE } /** Array initializer of NOC_GICRLPI2 peripheral base pointers */ #define NOC_GICRLPI2_BASE_PTRS { NOC__GIC__GICRLPI2 } /*! * @} */ /* end of group NOC_GICRLPI2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRLPI3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI3_Peripheral_Access_Layer NOC_GICRLPI3 Peripheral Access Layer * @{ */ /** NOC_GICRLPI3 - Register Layout Typedef */ typedef struct { __IO uint32_t GICR3_CTLR; /**< GICR3_CTLR, offset: 0x0 */ __I uint32_t GICR3_IIDR; /**< GICR3_IIDR, offset: 0x4 */ __I uint64_t GICR3_TYPER; /**< GICR3_TYPER, offset: 0x8 */ __I uint32_t GICR3_STATUSR; /**< GICR3_STATUSR, offset: 0x10 */ __IO uint32_t GICR3_WAKER; /**< GICR3_WAKER, offset: 0x14 */ __I uint32_t GICR3_MPAMIDR; /**< GICR3_MPAMIDR, offset: 0x18 */ __IO uint32_t GICR3_PARTIDR; /**< GICR3_PARTIDR, offset: 0x1C */ __IO uint32_t GICR3_FCTLR; /**< GICR3_FCTLR, offset: 0x20 */ __IO uint32_t GICR3_PWRR; /**< GICR3_PWRR, offset: 0x24 */ __IO uint32_t GICR3_CLASS; /**< GICR3_CLASS, offset: 0x28 */ uint8_t RESERVED_0[68]; __IO uint64_t GICR3_PROPBASER; /**< GICR3_PROPBASER, offset: 0x70 */ __IO uint64_t GICR3_PENDBASER; /**< GICR3_PENDBASER, offset: 0x78 */ uint8_t RESERVED_1[32]; __O uint64_t GICR3_INVLPIR; /**< GICR3_INVLPIR, offset: 0xA0 */ uint8_t RESERVED_2[8]; __O uint64_t GICR3_INVALLR; /**< GICR3_INVALLR, offset: 0xB0 */ uint8_t RESERVED_3[8]; __I uint32_t GICR3_SYNCR; /**< GICR3_SYNCR, offset: 0xC0 */ uint8_t RESERVED_4[60]; __O uint32_t GICR3_MPIDR; /**< GICR3_MPIDR, offset: 0x100 */ uint8_t RESERVED_5[65228]; __I uint32_t GICR3_PIDR4; /**< GICR3_PIDR4, offset: 0xFFD0 */ __I uint32_t GICR3_PIDR5; /**< GICR3_PIDR5, offset: 0xFFD4 */ __I uint32_t GICR3_PIDR6; /**< GICR3_PIDR6, offset: 0xFFD8 */ __I uint32_t GICR3_PIDR7; /**< GICR3_PIDR7, offset: 0xFFDC */ __I uint32_t GICR3_PIDR0; /**< GICR3_PIDR0, offset: 0xFFE0 */ __I uint32_t GICR3_PIDR1; /**< GICR3_PIDR1, offset: 0xFFE4 */ __I uint32_t GICR3_PIDR2; /**< GICR3_PIDR2, offset: 0xFFE8 */ __I uint32_t GICR3_PIDR3; /**< GICR3_PIDR3, offset: 0xFFEC */ __I uint32_t GICR3_CIDR0; /**< GICR3_CIDR0, offset: 0xFFF0 */ __I uint32_t GICR3_CIDR1; /**< GICR3_CIDR1, offset: 0xFFF4 */ __I uint32_t GICR3_CIDR2; /**< GICR3_CIDR2, offset: 0xFFF8 */ __I uint32_t GICR3_CIDR3; /**< GICR3_CIDR3, offset: 0xFFFC */ } NOC_GICRLPI3_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRLPI3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI3_Register_Masks NOC_GICRLPI3 Register Masks * @{ */ /*! @name GICR3_CTLR - GICR3_CTLR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_CTLR_EnableLPIs_MASK (0x1U) #define NOC_GICRLPI3_GICR3_CTLR_EnableLPIs_SHIFT (0U) /*! EnableLPIs - EnableLPIs */ #define NOC_GICRLPI3_GICR3_CTLR_EnableLPIs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_EnableLPIs_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_EnableLPIs_MASK) #define NOC_GICRLPI3_GICR3_CTLR_CES_MASK (0x2U) #define NOC_GICRLPI3_GICR3_CTLR_CES_SHIFT (1U) /*! CES - CES */ #define NOC_GICRLPI3_GICR3_CTLR_CES(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_CES_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_CES_MASK) #define NOC_GICRLPI3_GICR3_CTLR_IR_MASK (0x4U) #define NOC_GICRLPI3_GICR3_CTLR_IR_SHIFT (2U) /*! IR - IR */ #define NOC_GICRLPI3_GICR3_CTLR_IR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_IR_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_IR_MASK) #define NOC_GICRLPI3_GICR3_CTLR_RWP_MASK (0x8U) #define NOC_GICRLPI3_GICR3_CTLR_RWP_SHIFT (3U) /*! RWP - RWP */ #define NOC_GICRLPI3_GICR3_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_RWP_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_RWP_MASK) #define NOC_GICRLPI3_GICR3_CTLR_RESERVED1_MASK (0xFFFFF0U) #define NOC_GICRLPI3_GICR3_CTLR_RESERVED1_SHIFT (4U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_RESERVED1_MASK) #define NOC_GICRLPI3_GICR3_CTLR_DPG0_MASK (0x1000000U) #define NOC_GICRLPI3_GICR3_CTLR_DPG0_SHIFT (24U) /*! DPG0 - DPG0 */ #define NOC_GICRLPI3_GICR3_CTLR_DPG0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_DPG0_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_DPG0_MASK) #define NOC_GICRLPI3_GICR3_CTLR_DPG1NS_MASK (0x2000000U) #define NOC_GICRLPI3_GICR3_CTLR_DPG1NS_SHIFT (25U) /*! DPG1NS - DPG1NS */ #define NOC_GICRLPI3_GICR3_CTLR_DPG1NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_DPG1NS_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_DPG1NS_MASK) #define NOC_GICRLPI3_GICR3_CTLR_DPG1S_MASK (0x4000000U) #define NOC_GICRLPI3_GICR3_CTLR_DPG1S_SHIFT (26U) /*! DPG1S - DPG1S */ #define NOC_GICRLPI3_GICR3_CTLR_DPG1S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_DPG1S_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_DPG1S_MASK) #define NOC_GICRLPI3_GICR3_CTLR_RESERVED2_MASK (0x78000000U) #define NOC_GICRLPI3_GICR3_CTLR_RESERVED2_SHIFT (27U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI3_GICR3_CTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_RESERVED2_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_RESERVED2_MASK) #define NOC_GICRLPI3_GICR3_CTLR_UWP_MASK (0x80000000U) #define NOC_GICRLPI3_GICR3_CTLR_UWP_SHIFT (31U) /*! UWP - UWP */ #define NOC_GICRLPI3_GICR3_CTLR_UWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CTLR_UWP_SHIFT)) & NOC_GICRLPI3_GICR3_CTLR_UWP_MASK) /*! @} */ /*! @name GICR3_IIDR - GICR3_IIDR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICRLPI3_GICR3_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICRLPI3_GICR3_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_IIDR_Implementer_SHIFT)) & NOC_GICRLPI3_GICR3_IIDR_Implementer_MASK) #define NOC_GICRLPI3_GICR3_IIDR_Revision_MASK (0xF000U) #define NOC_GICRLPI3_GICR3_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICRLPI3_GICR3_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_IIDR_Revision_SHIFT)) & NOC_GICRLPI3_GICR3_IIDR_Revision_MASK) #define NOC_GICRLPI3_GICR3_IIDR_Variant_MASK (0xF0000U) #define NOC_GICRLPI3_GICR3_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICRLPI3_GICR3_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_IIDR_Variant_SHIFT)) & NOC_GICRLPI3_GICR3_IIDR_Variant_MASK) #define NOC_GICRLPI3_GICR3_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICRLPI3_GICR3_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_IIDR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_IIDR_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICRLPI3_GICR3_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICRLPI3_GICR3_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_IIDR_ProductID_SHIFT)) & NOC_GICRLPI3_GICR3_IIDR_ProductID_MASK) /*! @} */ /*! @name GICR3_TYPER - GICR3_TYPER */ /*! @{ */ #define NOC_GICRLPI3_GICR3_TYPER_PLPIS_MASK (0x1U) #define NOC_GICRLPI3_GICR3_TYPER_PLPIS_SHIFT (0U) /*! PLPIS - PLPIS */ #define NOC_GICRLPI3_GICR3_TYPER_PLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_PLPIS_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_PLPIS_MASK) #define NOC_GICRLPI3_GICR3_TYPER_VLPIS_MASK (0x2U) #define NOC_GICRLPI3_GICR3_TYPER_VLPIS_SHIFT (1U) /*! VLPIS - VLPIS */ #define NOC_GICRLPI3_GICR3_TYPER_VLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_VLPIS_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_VLPIS_MASK) #define NOC_GICRLPI3_GICR3_TYPER_Dirty_MASK (0x4U) #define NOC_GICRLPI3_GICR3_TYPER_Dirty_SHIFT (2U) /*! Dirty - Dirty */ #define NOC_GICRLPI3_GICR3_TYPER_Dirty(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_Dirty_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_Dirty_MASK) #define NOC_GICRLPI3_GICR3_TYPER_DirectLPI_MASK (0x8U) #define NOC_GICRLPI3_GICR3_TYPER_DirectLPI_SHIFT (3U) /*! DirectLPI - DirectLPI */ #define NOC_GICRLPI3_GICR3_TYPER_DirectLPI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_DirectLPI_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_DirectLPI_MASK) #define NOC_GICRLPI3_GICR3_TYPER_Last_MASK (0x10U) #define NOC_GICRLPI3_GICR3_TYPER_Last_SHIFT (4U) /*! Last - Last */ #define NOC_GICRLPI3_GICR3_TYPER_Last(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_Last_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_Last_MASK) #define NOC_GICRLPI3_GICR3_TYPER_DPGS_MASK (0x20U) #define NOC_GICRLPI3_GICR3_TYPER_DPGS_SHIFT (5U) /*! DPGS - DPGS */ #define NOC_GICRLPI3_GICR3_TYPER_DPGS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_DPGS_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_DPGS_MASK) #define NOC_GICRLPI3_GICR3_TYPER_MPAM_MASK (0x40U) #define NOC_GICRLPI3_GICR3_TYPER_MPAM_SHIFT (6U) /*! MPAM - MPAM */ #define NOC_GICRLPI3_GICR3_TYPER_MPAM(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_MPAM_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_MPAM_MASK) #define NOC_GICRLPI3_GICR3_TYPER_RVPEID_MASK (0x80U) #define NOC_GICRLPI3_GICR3_TYPER_RVPEID_SHIFT (7U) /*! RVPEID - RVPEID */ #define NOC_GICRLPI3_GICR3_TYPER_RVPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_RVPEID_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_RVPEID_MASK) #define NOC_GICRLPI3_GICR3_TYPER_ProcessorNumber_MASK (0xFFFF00U) #define NOC_GICRLPI3_GICR3_TYPER_ProcessorNumber_SHIFT (8U) /*! ProcessorNumber - ProcessorNumber */ #define NOC_GICRLPI3_GICR3_TYPER_ProcessorNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_ProcessorNumber_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_ProcessorNumber_MASK) #define NOC_GICRLPI3_GICR3_TYPER_CommonLPIAff_MASK (0x3000000U) #define NOC_GICRLPI3_GICR3_TYPER_CommonLPIAff_SHIFT (24U) /*! CommonLPIAff - CommonLPIAff */ #define NOC_GICRLPI3_GICR3_TYPER_CommonLPIAff(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_CommonLPIAff_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_CommonLPIAff_MASK) #define NOC_GICRLPI3_GICR3_TYPER_VSGI_MASK (0x4000000U) #define NOC_GICRLPI3_GICR3_TYPER_VSGI_SHIFT (26U) /*! VSGI - VSGI */ #define NOC_GICRLPI3_GICR3_TYPER_VSGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_VSGI_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_VSGI_MASK) #define NOC_GICRLPI3_GICR3_TYPER_PPInum_MASK (0xF8000000U) #define NOC_GICRLPI3_GICR3_TYPER_PPInum_SHIFT (27U) /*! PPInum - PPInum */ #define NOC_GICRLPI3_GICR3_TYPER_PPInum(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_PPInum_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_PPInum_MASK) #define NOC_GICRLPI3_GICR3_TYPER_AffinityValue_MASK (0xFFFFFFFF00000000U) #define NOC_GICRLPI3_GICR3_TYPER_AffinityValue_SHIFT (32U) /*! AffinityValue - AffinityValue */ #define NOC_GICRLPI3_GICR3_TYPER_AffinityValue(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_TYPER_AffinityValue_SHIFT)) & NOC_GICRLPI3_GICR3_TYPER_AffinityValue_MASK) /*! @} */ /*! @name GICR3_STATUSR - GICR3_STATUSR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICRLPI3_GICR3_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI3_GICR3_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_STATUSR_RESERVED_SHIFT)) & NOC_GICRLPI3_GICR3_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICR3_WAKER - GICR3_WAKER */ /*! @{ */ #define NOC_GICRLPI3_GICR3_WAKER_Sleep_MASK (0x1U) #define NOC_GICRLPI3_GICR3_WAKER_Sleep_SHIFT (0U) /*! Sleep - Sleep */ #define NOC_GICRLPI3_GICR3_WAKER_Sleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_WAKER_Sleep_SHIFT)) & NOC_GICRLPI3_GICR3_WAKER_Sleep_MASK) #define NOC_GICRLPI3_GICR3_WAKER_ProcessorSleep_MASK (0x2U) #define NOC_GICRLPI3_GICR3_WAKER_ProcessorSleep_SHIFT (1U) /*! ProcessorSleep - ProcessorSleep */ #define NOC_GICRLPI3_GICR3_WAKER_ProcessorSleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_WAKER_ProcessorSleep_SHIFT)) & NOC_GICRLPI3_GICR3_WAKER_ProcessorSleep_MASK) #define NOC_GICRLPI3_GICR3_WAKER_ChildrenAsleep_MASK (0x4U) #define NOC_GICRLPI3_GICR3_WAKER_ChildrenAsleep_SHIFT (2U) /*! ChildrenAsleep - ChildrenAsleep */ #define NOC_GICRLPI3_GICR3_WAKER_ChildrenAsleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_WAKER_ChildrenAsleep_SHIFT)) & NOC_GICRLPI3_GICR3_WAKER_ChildrenAsleep_MASK) #define NOC_GICRLPI3_GICR3_WAKER_RESERVED0_MASK (0x7FFFFFF8U) #define NOC_GICRLPI3_GICR3_WAKER_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_WAKER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_WAKER_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_WAKER_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_WAKER_Quiescent_MASK (0x80000000U) #define NOC_GICRLPI3_GICR3_WAKER_Quiescent_SHIFT (31U) /*! Quiescent - Quiescent */ #define NOC_GICRLPI3_GICR3_WAKER_Quiescent(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_WAKER_Quiescent_SHIFT)) & NOC_GICRLPI3_GICR3_WAKER_Quiescent_MASK) /*! @} */ /*! @name GICR3_MPAMIDR - GICR3_MPAMIDR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_MPAMIDR_PARTID_MAX_MASK (0x1FFU) #define NOC_GICRLPI3_GICR3_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define NOC_GICRLPI3_GICR3_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPAMIDR_PARTID_MAX_SHIFT)) & NOC_GICRLPI3_GICR3_MPAMIDR_PARTID_MAX_MASK) #define NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_MPAMIDR_PMG_MAX_MASK (0x10000U) #define NOC_GICRLPI3_GICR3_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define NOC_GICRLPI3_GICR3_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPAMIDR_PMG_MAX_SHIFT)) & NOC_GICRLPI3_GICR3_MPAMIDR_PMG_MAX_MASK) #define NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_MPAMIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR3_PARTIDR - GICR3_PARTIDR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PARTIDR_PARTID_MASK (0x1FFU) #define NOC_GICRLPI3_GICR3_PARTIDR_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define NOC_GICRLPI3_GICR3_PARTIDR_PARTID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PARTIDR_PARTID_SHIFT)) & NOC_GICRLPI3_GICR3_PARTIDR_PARTID_MASK) #define NOC_GICRLPI3_GICR3_PARTIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI3_GICR3_PARTIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PARTIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PARTIDR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PARTIDR_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_PARTIDR_PMG_MASK (0x10000U) #define NOC_GICRLPI3_GICR3_PARTIDR_PMG_SHIFT (16U) /*! PMG - PMG */ #define NOC_GICRLPI3_GICR3_PARTIDR_PMG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PARTIDR_PMG_SHIFT)) & NOC_GICRLPI3_GICR3_PARTIDR_PMG_MASK) #define NOC_GICRLPI3_GICR3_PARTIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI3_GICR3_PARTIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_PARTIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PARTIDR_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_PARTIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR3_FCTLR - GICR3_FCTLR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_FCTLR_SIP_MASK (0x1U) #define NOC_GICRLPI3_GICR3_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICRLPI3_GICR3_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_FCTLR_SIP_SHIFT)) & NOC_GICRLPI3_GICR3_FCTLR_SIP_MASK) #define NOC_GICRLPI3_GICR3_FCTLR_QDeny_MASK (0x2U) #define NOC_GICRLPI3_GICR3_FCTLR_QDeny_SHIFT (1U) /*! QDeny - QDeny */ #define NOC_GICRLPI3_GICR3_FCTLR_QDeny(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_FCTLR_QDeny_SHIFT)) & NOC_GICRLPI3_GICR3_FCTLR_QDeny_MASK) #define NOC_GICRLPI3_GICR3_FCTLR_CGO_MASK (0x1CU) #define NOC_GICRLPI3_GICR3_FCTLR_CGO_SHIFT (2U) /*! CGO - CGO */ #define NOC_GICRLPI3_GICR3_FCTLR_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_FCTLR_CGO_SHIFT)) & NOC_GICRLPI3_GICR3_FCTLR_CGO_MASK) #define NOC_GICRLPI3_GICR3_FCTLR_RESERVED0_MASK (0x3E0U) #define NOC_GICRLPI3_GICR3_FCTLR_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_FCTLR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_FCTLR_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_FCTLR_RESERVED1_MASK (0xFFFFFC00U) #define NOC_GICRLPI3_GICR3_FCTLR_RESERVED1_SHIFT (10U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_FCTLR_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_FCTLR_RESERVED1_MASK) /*! @} */ /*! @name GICR3_PWRR - GICR3_PWRR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PWRR_RDPD_MASK (0x1U) #define NOC_GICRLPI3_GICR3_PWRR_RDPD_SHIFT (0U) /*! RDPD - RDPD */ #define NOC_GICRLPI3_GICR3_PWRR_RDPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RDPD_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RDPD_MASK) #define NOC_GICRLPI3_GICR3_PWRR_RDAG_MASK (0x2U) #define NOC_GICRLPI3_GICR3_PWRR_RDAG_SHIFT (1U) /*! RDAG - RDAG */ #define NOC_GICRLPI3_GICR3_PWRR_RDAG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RDAG_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RDAG_MASK) #define NOC_GICRLPI3_GICR3_PWRR_RDGPD_MASK (0x4U) #define NOC_GICRLPI3_GICR3_PWRR_RDGPD_SHIFT (2U) /*! RDGPD - RDGPD */ #define NOC_GICRLPI3_GICR3_PWRR_RDGPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RDGPD_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RDGPD_MASK) #define NOC_GICRLPI3_GICR3_PWRR_RDGPO_MASK (0x8U) #define NOC_GICRLPI3_GICR3_PWRR_RDGPO_SHIFT (3U) /*! RDGPO - RDGPO */ #define NOC_GICRLPI3_GICR3_PWRR_RDGPO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RDGPO_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RDGPO_MASK) #define NOC_GICRLPI3_GICR3_PWRR_RESERVED0_MASK (0xF0U) #define NOC_GICRLPI3_GICR3_PWRR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PWRR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_PWRR_RDGO_MASK (0x7F00U) #define NOC_GICRLPI3_GICR3_PWRR_RDGO_SHIFT (8U) /*! RDGO - RDGO */ #define NOC_GICRLPI3_GICR3_PWRR_RDGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RDGO_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RDGO_MASK) #define NOC_GICRLPI3_GICR3_PWRR_RDG_MASK (0xFF8000U) #define NOC_GICRLPI3_GICR3_PWRR_RDG_SHIFT (15U) /*! RDG - RDG */ #define NOC_GICRLPI3_GICR3_PWRR_RDG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RDG_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RDG_MASK) #define NOC_GICRLPI3_GICR3_PWRR_RESERVED1_MASK (0xFF000000U) #define NOC_GICRLPI3_GICR3_PWRR_RESERVED1_SHIFT (24U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_PWRR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PWRR_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_PWRR_RESERVED1_MASK) /*! @} */ /*! @name GICR3_CLASS - GICR3_CLASS */ /*! @{ */ #define NOC_GICRLPI3_GICR3_CLASS_Class_MASK (0x1U) #define NOC_GICRLPI3_GICR3_CLASS_Class_SHIFT (0U) /*! Class - Class */ #define NOC_GICRLPI3_GICR3_CLASS_Class(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CLASS_Class_SHIFT)) & NOC_GICRLPI3_GICR3_CLASS_Class_MASK) #define NOC_GICRLPI3_GICR3_CLASS_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI3_GICR3_CLASS_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_CLASS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CLASS_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_CLASS_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PROPBASER - GICR3_PROPBASER */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PROPBASER_IDBits_MASK (0x1FU) #define NOC_GICRLPI3_GICR3_PROPBASER_IDBits_SHIFT (0U) /*! IDBits - IDBits */ #define NOC_GICRLPI3_GICR3_PROPBASER_IDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_IDBits_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_IDBits_MASK) #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED0_MASK (0x60U) #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_PROPBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI3_GICR3_PROPBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI3_GICR3_PROPBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_Cacheability_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_Cacheability_MASK) #define NOC_GICRLPI3_GICR3_PROPBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI3_GICR3_PROPBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI3_GICR3_PROPBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_Shareability_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_Shareability_MASK) #define NOC_GICRLPI3_GICR3_PROPBASER_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GICRLPI3_GICR3_PROPBASER_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI3_GICR3_PROPBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_PhysicalAddress_MASK) #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED1_MASK (0xFFFFF000000000U) #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED1_SHIFT (36U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_RESERVED1_MASK) #define NOC_GICRLPI3_GICR3_PROPBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI3_GICR3_PROPBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI3_GICR3_PROPBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_OuterCacheability_MASK) #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED2_MASK (0xF800000000000000U) #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED2_SHIFT (59U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI3_GICR3_PROPBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PROPBASER_RESERVED2_SHIFT)) & NOC_GICRLPI3_GICR3_PROPBASER_RESERVED2_MASK) /*! @} */ /*! @name GICR3_PENDBASER - GICR3_PENDBASER */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED0_MASK (0x7FU) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI3_GICR3_PENDBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI3_GICR3_PENDBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_Cacheability_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_Cacheability_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI3_GICR3_PENDBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI3_GICR3_PENDBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_Shareability_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_Shareability_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED1_MASK (0xF000U) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_RESERVED1_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_PhysicalAddress_MASK (0xFFFFF0000U) #define NOC_GICRLPI3_GICR3_PENDBASER_PhysicalAddress_SHIFT (16U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI3_GICR3_PENDBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_PhysicalAddress_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED2_MASK (0xFFFFF000000000U) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED2_SHIFT (36U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_RESERVED2_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_RESERVED2_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI3_GICR3_PENDBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI3_GICR3_PENDBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_OuterCacheability_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED3_MASK (0x3800000000000000U) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED3_SHIFT (59U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_RESERVED3_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_RESERVED3_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_PendingTableZero_MASK (0x4000000000000000U) #define NOC_GICRLPI3_GICR3_PENDBASER_PendingTableZero_SHIFT (62U) /*! PendingTableZero - PendingTableZero */ #define NOC_GICRLPI3_GICR3_PENDBASER_PendingTableZero(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_PendingTableZero_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_PendingTableZero_MASK) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED4_MASK (0x8000000000000000U) #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED4_SHIFT (63U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRLPI3_GICR3_PENDBASER_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_PENDBASER_RESERVED4_SHIFT)) & NOC_GICRLPI3_GICR3_PENDBASER_RESERVED4_MASK) /*! @} */ /*! @name GICR3_INVLPIR - GICR3_INVLPIR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_INVLPIR_IntID_MASK (0xFFFFFFFFU) #define NOC_GICRLPI3_GICR3_INVLPIR_IntID_SHIFT (0U) /*! IntID - IntID */ #define NOC_GICRLPI3_GICR3_INVLPIR_IntID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVLPIR_IntID_SHIFT)) & NOC_GICRLPI3_GICR3_INVLPIR_IntID_MASK) #define NOC_GICRLPI3_GICR3_INVLPIR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI3_GICR3_INVLPIR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI3_GICR3_INVLPIR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVLPIR_VPEID_SHIFT)) & NOC_GICRLPI3_GICR3_INVLPIR_VPEID_MASK) #define NOC_GICRLPI3_GICR3_INVLPIR_RESERVED0_MASK (0x7FFF000000000000U) #define NOC_GICRLPI3_GICR3_INVLPIR_RESERVED0_SHIFT (48U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_INVLPIR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVLPIR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_INVLPIR_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_INVLPIR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI3_GICR3_INVLPIR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI3_GICR3_INVLPIR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVLPIR_V_SHIFT)) & NOC_GICRLPI3_GICR3_INVLPIR_V_MASK) /*! @} */ /*! @name GICR3_INVALLR - GICR3_INVALLR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_INVALLR_RESERVED0_MASK (0xFFFFFFFFU) #define NOC_GICRLPI3_GICR3_INVALLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_INVALLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVALLR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_INVALLR_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_INVALLR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI3_GICR3_INVALLR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI3_GICR3_INVALLR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVALLR_VPEID_SHIFT)) & NOC_GICRLPI3_GICR3_INVALLR_VPEID_MASK) #define NOC_GICRLPI3_GICR3_INVALLR_RESERVED1_MASK (0x7FFF000000000000U) #define NOC_GICRLPI3_GICR3_INVALLR_RESERVED1_SHIFT (48U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_INVALLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVALLR_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_INVALLR_RESERVED1_MASK) #define NOC_GICRLPI3_GICR3_INVALLR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI3_GICR3_INVALLR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI3_GICR3_INVALLR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI3_GICR3_INVALLR_V_SHIFT)) & NOC_GICRLPI3_GICR3_INVALLR_V_MASK) /*! @} */ /*! @name GICR3_SYNCR - GICR3_SYNCR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_SYNCR_Busy_MASK (0x1U) #define NOC_GICRLPI3_GICR3_SYNCR_Busy_SHIFT (0U) /*! Busy - Busy */ #define NOC_GICRLPI3_GICR3_SYNCR_Busy(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_SYNCR_Busy_SHIFT)) & NOC_GICRLPI3_GICR3_SYNCR_Busy_MASK) #define NOC_GICRLPI3_GICR3_SYNCR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI3_GICR3_SYNCR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_SYNCR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_SYNCR_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_SYNCR_RESERVED0_MASK) /*! @} */ /*! @name GICR3_MPIDR - GICR3_MPIDR */ /*! @{ */ #define NOC_GICRLPI3_GICR3_MPIDR_Affinity0_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_MPIDR_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICRLPI3_GICR3_MPIDR_Affinity0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPIDR_Affinity0_SHIFT)) & NOC_GICRLPI3_GICR3_MPIDR_Affinity0_MASK) #define NOC_GICRLPI3_GICR3_MPIDR_Affinity1_MASK (0xFF00U) #define NOC_GICRLPI3_GICR3_MPIDR_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 */ #define NOC_GICRLPI3_GICR3_MPIDR_Affinity1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPIDR_Affinity1_SHIFT)) & NOC_GICRLPI3_GICR3_MPIDR_Affinity1_MASK) #define NOC_GICRLPI3_GICR3_MPIDR_Affinity2_MASK (0xFF0000U) #define NOC_GICRLPI3_GICR3_MPIDR_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICRLPI3_GICR3_MPIDR_Affinity2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPIDR_Affinity2_SHIFT)) & NOC_GICRLPI3_GICR3_MPIDR_Affinity2_MASK) #define NOC_GICRLPI3_GICR3_MPIDR_Affinity3_MASK (0xFF000000U) #define NOC_GICRLPI3_GICR3_MPIDR_Affinity3_SHIFT (24U) /*! Affinity3 - Affinity3 */ #define NOC_GICRLPI3_GICR3_MPIDR_Affinity3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_MPIDR_Affinity3_SHIFT)) & NOC_GICRLPI3_GICR3_MPIDR_Affinity3_MASK) /*! @} */ /*! @name GICR3_PIDR4 - GICR3_PIDR4 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR4_DES_2_MASK (0xFU) #define NOC_GICRLPI3_GICR3_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICRLPI3_GICR3_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR4_DES_2_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR4_DES_2_MASK) #define NOC_GICRLPI3_GICR3_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICRLPI3_GICR3_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICRLPI3_GICR3_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR4_SIZE_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR4_SIZE_MASK) #define NOC_GICRLPI3_GICR3_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR4_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PIDR5 - GICR3_PIDR5 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI3_GICR3_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR5_RESERVED_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR5_RESERVED_MASK) #define NOC_GICRLPI3_GICR3_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR5_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PIDR6 - GICR3_PIDR6 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI3_GICR3_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR6_RESERVED_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR6_RESERVED_MASK) #define NOC_GICRLPI3_GICR3_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR6_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PIDR7 - GICR3_PIDR7 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI3_GICR3_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR7_RESERVED_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR7_RESERVED_MASK) #define NOC_GICRLPI3_GICR3_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR7_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PIDR0 - GICR3_PIDR0 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICRLPI3_GICR3_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR0_PART_0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR0_PART_0_MASK) #define NOC_GICRLPI3_GICR3_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PIDR1 - GICR3_PIDR1 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR1_PART_1_MASK (0xFU) #define NOC_GICRLPI3_GICR3_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICRLPI3_GICR3_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR1_PART_1_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR1_PART_1_MASK) #define NOC_GICRLPI3_GICR3_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICRLPI3_GICR3_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICRLPI3_GICR3_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR1_DES_0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR1_DES_0_MASK) #define NOC_GICRLPI3_GICR3_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PIDR2 - GICR3_PIDR2 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR2_DES_1_MASK (0x7U) #define NOC_GICRLPI3_GICR3_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICRLPI3_GICR3_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR2_DES_1_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR2_DES_1_MASK) #define NOC_GICRLPI3_GICR3_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICRLPI3_GICR3_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICRLPI3_GICR3_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR2_JEDEC_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR2_JEDEC_MASK) #define NOC_GICRLPI3_GICR3_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICRLPI3_GICR3_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICRLPI3_GICR3_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR2_REVISION_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR2_REVISION_MASK) #define NOC_GICRLPI3_GICR3_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR3_PIDR3 - GICR3_PIDR3 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_PIDR3_CMOD_MASK (0x7U) #define NOC_GICRLPI3_GICR3_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICRLPI3_GICR3_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR3_CMOD_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR3_CMOD_MASK) #define NOC_GICRLPI3_GICR3_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICRLPI3_GICR3_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR3_RESERVED0_MASK) #define NOC_GICRLPI3_GICR3_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICRLPI3_GICR3_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICRLPI3_GICR3_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR3_REVAND_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR3_REVAND_MASK) #define NOC_GICRLPI3_GICR3_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI3_GICR3_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_PIDR3_RESERVED1_SHIFT)) & NOC_GICRLPI3_GICR3_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICR3_CIDR0 - GICR3_CIDR0 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICRLPI3_GICR3_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR0_PRMBL_0_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR0_PRMBL_0_MASK) #define NOC_GICRLPI3_GICR3_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR3_CIDR1 - GICR3_CIDR1 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICRLPI3_GICR3_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICRLPI3_GICR3_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR1_PRMBL_1_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR1_PRMBL_1_MASK) #define NOC_GICRLPI3_GICR3_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICRLPI3_GICR3_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICRLPI3_GICR3_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR1_CLASS_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR1_CLASS_MASK) #define NOC_GICRLPI3_GICR3_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR3_CIDR2 - GICR3_CIDR2 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICRLPI3_GICR3_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR2_PRMBL_2_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR2_PRMBL_2_MASK) #define NOC_GICRLPI3_GICR3_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR3_CIDR3 - GICR3_CIDR3 */ /*! @{ */ #define NOC_GICRLPI3_GICR3_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICRLPI3_GICR3_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICRLPI3_GICR3_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR3_PRMBL_3_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR3_PRMBL_3_MASK) #define NOC_GICRLPI3_GICR3_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI3_GICR3_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI3_GICR3_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI3_GICR3_CIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI3_GICR3_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRLPI3_Register_Masks */ /* NOC_GICRLPI3 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRLPI3 base address */ #define NOC__GIC__GICRLPI3_BASE (0x480C0000u) /** Peripheral NOC__GIC__GICRLPI3 base pointer */ #define NOC__GIC__GICRLPI3 ((NOC_GICRLPI3_Type *)NOC__GIC__GICRLPI3_BASE) /** Array initializer of NOC_GICRLPI3 peripheral base addresses */ #define NOC_GICRLPI3_BASE_ADDRS { NOC__GIC__GICRLPI3_BASE } /** Array initializer of NOC_GICRLPI3 peripheral base pointers */ #define NOC_GICRLPI3_BASE_PTRS { NOC__GIC__GICRLPI3 } /*! * @} */ /* end of group NOC_GICRLPI3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRLPI4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI4_Peripheral_Access_Layer NOC_GICRLPI4 Peripheral Access Layer * @{ */ /** NOC_GICRLPI4 - Register Layout Typedef */ typedef struct { __IO uint32_t GICR4_CTLR; /**< GICR4_CTLR, offset: 0x0 */ __I uint32_t GICR4_IIDR; /**< GICR4_IIDR, offset: 0x4 */ __I uint64_t GICR4_TYPER; /**< GICR4_TYPER, offset: 0x8 */ __I uint32_t GICR4_STATUSR; /**< GICR4_STATUSR, offset: 0x10 */ __IO uint32_t GICR4_WAKER; /**< GICR4_WAKER, offset: 0x14 */ __I uint32_t GICR4_MPAMIDR; /**< GICR4_MPAMIDR, offset: 0x18 */ __IO uint32_t GICR4_PARTIDR; /**< GICR4_PARTIDR, offset: 0x1C */ __IO uint32_t GICR4_FCTLR; /**< GICR4_FCTLR, offset: 0x20 */ __IO uint32_t GICR4_PWRR; /**< GICR4_PWRR, offset: 0x24 */ __IO uint32_t GICR4_CLASS; /**< GICR4_CLASS, offset: 0x28 */ uint8_t RESERVED_0[68]; __IO uint64_t GICR4_PROPBASER; /**< GICR4_PROPBASER, offset: 0x70 */ __IO uint64_t GICR4_PENDBASER; /**< GICR4_PENDBASER, offset: 0x78 */ uint8_t RESERVED_1[32]; __O uint64_t GICR4_INVLPIR; /**< GICR4_INVLPIR, offset: 0xA0 */ uint8_t RESERVED_2[8]; __O uint64_t GICR4_INVALLR; /**< GICR4_INVALLR, offset: 0xB0 */ uint8_t RESERVED_3[8]; __I uint32_t GICR4_SYNCR; /**< GICR4_SYNCR, offset: 0xC0 */ uint8_t RESERVED_4[60]; __O uint32_t GICR4_MPIDR; /**< GICR4_MPIDR, offset: 0x100 */ uint8_t RESERVED_5[65228]; __I uint32_t GICR4_PIDR4; /**< GICR4_PIDR4, offset: 0xFFD0 */ __I uint32_t GICR4_PIDR5; /**< GICR4_PIDR5, offset: 0xFFD4 */ __I uint32_t GICR4_PIDR6; /**< GICR4_PIDR6, offset: 0xFFD8 */ __I uint32_t GICR4_PIDR7; /**< GICR4_PIDR7, offset: 0xFFDC */ __I uint32_t GICR4_PIDR0; /**< GICR4_PIDR0, offset: 0xFFE0 */ __I uint32_t GICR4_PIDR1; /**< GICR4_PIDR1, offset: 0xFFE4 */ __I uint32_t GICR4_PIDR2; /**< GICR4_PIDR2, offset: 0xFFE8 */ __I uint32_t GICR4_PIDR3; /**< GICR4_PIDR3, offset: 0xFFEC */ __I uint32_t GICR4_CIDR0; /**< GICR4_CIDR0, offset: 0xFFF0 */ __I uint32_t GICR4_CIDR1; /**< GICR4_CIDR1, offset: 0xFFF4 */ __I uint32_t GICR4_CIDR2; /**< GICR4_CIDR2, offset: 0xFFF8 */ __I uint32_t GICR4_CIDR3; /**< GICR4_CIDR3, offset: 0xFFFC */ } NOC_GICRLPI4_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRLPI4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI4_Register_Masks NOC_GICRLPI4 Register Masks * @{ */ /*! @name GICR4_CTLR - GICR4_CTLR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_CTLR_EnableLPIs_MASK (0x1U) #define NOC_GICRLPI4_GICR4_CTLR_EnableLPIs_SHIFT (0U) /*! EnableLPIs - EnableLPIs */ #define NOC_GICRLPI4_GICR4_CTLR_EnableLPIs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_EnableLPIs_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_EnableLPIs_MASK) #define NOC_GICRLPI4_GICR4_CTLR_CES_MASK (0x2U) #define NOC_GICRLPI4_GICR4_CTLR_CES_SHIFT (1U) /*! CES - CES */ #define NOC_GICRLPI4_GICR4_CTLR_CES(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_CES_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_CES_MASK) #define NOC_GICRLPI4_GICR4_CTLR_IR_MASK (0x4U) #define NOC_GICRLPI4_GICR4_CTLR_IR_SHIFT (2U) /*! IR - IR */ #define NOC_GICRLPI4_GICR4_CTLR_IR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_IR_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_IR_MASK) #define NOC_GICRLPI4_GICR4_CTLR_RWP_MASK (0x8U) #define NOC_GICRLPI4_GICR4_CTLR_RWP_SHIFT (3U) /*! RWP - RWP */ #define NOC_GICRLPI4_GICR4_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_RWP_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_RWP_MASK) #define NOC_GICRLPI4_GICR4_CTLR_RESERVED1_MASK (0xFFFFF0U) #define NOC_GICRLPI4_GICR4_CTLR_RESERVED1_SHIFT (4U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_RESERVED1_MASK) #define NOC_GICRLPI4_GICR4_CTLR_DPG0_MASK (0x1000000U) #define NOC_GICRLPI4_GICR4_CTLR_DPG0_SHIFT (24U) /*! DPG0 - DPG0 */ #define NOC_GICRLPI4_GICR4_CTLR_DPG0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_DPG0_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_DPG0_MASK) #define NOC_GICRLPI4_GICR4_CTLR_DPG1NS_MASK (0x2000000U) #define NOC_GICRLPI4_GICR4_CTLR_DPG1NS_SHIFT (25U) /*! DPG1NS - DPG1NS */ #define NOC_GICRLPI4_GICR4_CTLR_DPG1NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_DPG1NS_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_DPG1NS_MASK) #define NOC_GICRLPI4_GICR4_CTLR_DPG1S_MASK (0x4000000U) #define NOC_GICRLPI4_GICR4_CTLR_DPG1S_SHIFT (26U) /*! DPG1S - DPG1S */ #define NOC_GICRLPI4_GICR4_CTLR_DPG1S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_DPG1S_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_DPG1S_MASK) #define NOC_GICRLPI4_GICR4_CTLR_RESERVED2_MASK (0x78000000U) #define NOC_GICRLPI4_GICR4_CTLR_RESERVED2_SHIFT (27U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI4_GICR4_CTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_RESERVED2_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_RESERVED2_MASK) #define NOC_GICRLPI4_GICR4_CTLR_UWP_MASK (0x80000000U) #define NOC_GICRLPI4_GICR4_CTLR_UWP_SHIFT (31U) /*! UWP - UWP */ #define NOC_GICRLPI4_GICR4_CTLR_UWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CTLR_UWP_SHIFT)) & NOC_GICRLPI4_GICR4_CTLR_UWP_MASK) /*! @} */ /*! @name GICR4_IIDR - GICR4_IIDR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICRLPI4_GICR4_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICRLPI4_GICR4_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_IIDR_Implementer_SHIFT)) & NOC_GICRLPI4_GICR4_IIDR_Implementer_MASK) #define NOC_GICRLPI4_GICR4_IIDR_Revision_MASK (0xF000U) #define NOC_GICRLPI4_GICR4_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICRLPI4_GICR4_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_IIDR_Revision_SHIFT)) & NOC_GICRLPI4_GICR4_IIDR_Revision_MASK) #define NOC_GICRLPI4_GICR4_IIDR_Variant_MASK (0xF0000U) #define NOC_GICRLPI4_GICR4_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICRLPI4_GICR4_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_IIDR_Variant_SHIFT)) & NOC_GICRLPI4_GICR4_IIDR_Variant_MASK) #define NOC_GICRLPI4_GICR4_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICRLPI4_GICR4_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_IIDR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_IIDR_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICRLPI4_GICR4_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICRLPI4_GICR4_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_IIDR_ProductID_SHIFT)) & NOC_GICRLPI4_GICR4_IIDR_ProductID_MASK) /*! @} */ /*! @name GICR4_TYPER - GICR4_TYPER */ /*! @{ */ #define NOC_GICRLPI4_GICR4_TYPER_PLPIS_MASK (0x1U) #define NOC_GICRLPI4_GICR4_TYPER_PLPIS_SHIFT (0U) /*! PLPIS - PLPIS */ #define NOC_GICRLPI4_GICR4_TYPER_PLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_PLPIS_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_PLPIS_MASK) #define NOC_GICRLPI4_GICR4_TYPER_VLPIS_MASK (0x2U) #define NOC_GICRLPI4_GICR4_TYPER_VLPIS_SHIFT (1U) /*! VLPIS - VLPIS */ #define NOC_GICRLPI4_GICR4_TYPER_VLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_VLPIS_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_VLPIS_MASK) #define NOC_GICRLPI4_GICR4_TYPER_Dirty_MASK (0x4U) #define NOC_GICRLPI4_GICR4_TYPER_Dirty_SHIFT (2U) /*! Dirty - Dirty */ #define NOC_GICRLPI4_GICR4_TYPER_Dirty(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_Dirty_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_Dirty_MASK) #define NOC_GICRLPI4_GICR4_TYPER_DirectLPI_MASK (0x8U) #define NOC_GICRLPI4_GICR4_TYPER_DirectLPI_SHIFT (3U) /*! DirectLPI - DirectLPI */ #define NOC_GICRLPI4_GICR4_TYPER_DirectLPI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_DirectLPI_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_DirectLPI_MASK) #define NOC_GICRLPI4_GICR4_TYPER_Last_MASK (0x10U) #define NOC_GICRLPI4_GICR4_TYPER_Last_SHIFT (4U) /*! Last - Last */ #define NOC_GICRLPI4_GICR4_TYPER_Last(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_Last_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_Last_MASK) #define NOC_GICRLPI4_GICR4_TYPER_DPGS_MASK (0x20U) #define NOC_GICRLPI4_GICR4_TYPER_DPGS_SHIFT (5U) /*! DPGS - DPGS */ #define NOC_GICRLPI4_GICR4_TYPER_DPGS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_DPGS_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_DPGS_MASK) #define NOC_GICRLPI4_GICR4_TYPER_MPAM_MASK (0x40U) #define NOC_GICRLPI4_GICR4_TYPER_MPAM_SHIFT (6U) /*! MPAM - MPAM */ #define NOC_GICRLPI4_GICR4_TYPER_MPAM(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_MPAM_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_MPAM_MASK) #define NOC_GICRLPI4_GICR4_TYPER_RVPEID_MASK (0x80U) #define NOC_GICRLPI4_GICR4_TYPER_RVPEID_SHIFT (7U) /*! RVPEID - RVPEID */ #define NOC_GICRLPI4_GICR4_TYPER_RVPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_RVPEID_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_RVPEID_MASK) #define NOC_GICRLPI4_GICR4_TYPER_ProcessorNumber_MASK (0xFFFF00U) #define NOC_GICRLPI4_GICR4_TYPER_ProcessorNumber_SHIFT (8U) /*! ProcessorNumber - ProcessorNumber */ #define NOC_GICRLPI4_GICR4_TYPER_ProcessorNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_ProcessorNumber_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_ProcessorNumber_MASK) #define NOC_GICRLPI4_GICR4_TYPER_CommonLPIAff_MASK (0x3000000U) #define NOC_GICRLPI4_GICR4_TYPER_CommonLPIAff_SHIFT (24U) /*! CommonLPIAff - CommonLPIAff */ #define NOC_GICRLPI4_GICR4_TYPER_CommonLPIAff(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_CommonLPIAff_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_CommonLPIAff_MASK) #define NOC_GICRLPI4_GICR4_TYPER_VSGI_MASK (0x4000000U) #define NOC_GICRLPI4_GICR4_TYPER_VSGI_SHIFT (26U) /*! VSGI - VSGI */ #define NOC_GICRLPI4_GICR4_TYPER_VSGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_VSGI_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_VSGI_MASK) #define NOC_GICRLPI4_GICR4_TYPER_PPInum_MASK (0xF8000000U) #define NOC_GICRLPI4_GICR4_TYPER_PPInum_SHIFT (27U) /*! PPInum - PPInum */ #define NOC_GICRLPI4_GICR4_TYPER_PPInum(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_PPInum_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_PPInum_MASK) #define NOC_GICRLPI4_GICR4_TYPER_AffinityValue_MASK (0xFFFFFFFF00000000U) #define NOC_GICRLPI4_GICR4_TYPER_AffinityValue_SHIFT (32U) /*! AffinityValue - AffinityValue */ #define NOC_GICRLPI4_GICR4_TYPER_AffinityValue(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_TYPER_AffinityValue_SHIFT)) & NOC_GICRLPI4_GICR4_TYPER_AffinityValue_MASK) /*! @} */ /*! @name GICR4_STATUSR - GICR4_STATUSR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICRLPI4_GICR4_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI4_GICR4_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_STATUSR_RESERVED_SHIFT)) & NOC_GICRLPI4_GICR4_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICR4_WAKER - GICR4_WAKER */ /*! @{ */ #define NOC_GICRLPI4_GICR4_WAKER_Sleep_MASK (0x1U) #define NOC_GICRLPI4_GICR4_WAKER_Sleep_SHIFT (0U) /*! Sleep - Sleep */ #define NOC_GICRLPI4_GICR4_WAKER_Sleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_WAKER_Sleep_SHIFT)) & NOC_GICRLPI4_GICR4_WAKER_Sleep_MASK) #define NOC_GICRLPI4_GICR4_WAKER_ProcessorSleep_MASK (0x2U) #define NOC_GICRLPI4_GICR4_WAKER_ProcessorSleep_SHIFT (1U) /*! ProcessorSleep - ProcessorSleep */ #define NOC_GICRLPI4_GICR4_WAKER_ProcessorSleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_WAKER_ProcessorSleep_SHIFT)) & NOC_GICRLPI4_GICR4_WAKER_ProcessorSleep_MASK) #define NOC_GICRLPI4_GICR4_WAKER_ChildrenAsleep_MASK (0x4U) #define NOC_GICRLPI4_GICR4_WAKER_ChildrenAsleep_SHIFT (2U) /*! ChildrenAsleep - ChildrenAsleep */ #define NOC_GICRLPI4_GICR4_WAKER_ChildrenAsleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_WAKER_ChildrenAsleep_SHIFT)) & NOC_GICRLPI4_GICR4_WAKER_ChildrenAsleep_MASK) #define NOC_GICRLPI4_GICR4_WAKER_RESERVED0_MASK (0x7FFFFFF8U) #define NOC_GICRLPI4_GICR4_WAKER_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_WAKER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_WAKER_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_WAKER_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_WAKER_Quiescent_MASK (0x80000000U) #define NOC_GICRLPI4_GICR4_WAKER_Quiescent_SHIFT (31U) /*! Quiescent - Quiescent */ #define NOC_GICRLPI4_GICR4_WAKER_Quiescent(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_WAKER_Quiescent_SHIFT)) & NOC_GICRLPI4_GICR4_WAKER_Quiescent_MASK) /*! @} */ /*! @name GICR4_MPAMIDR - GICR4_MPAMIDR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_MPAMIDR_PARTID_MAX_MASK (0x1FFU) #define NOC_GICRLPI4_GICR4_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define NOC_GICRLPI4_GICR4_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPAMIDR_PARTID_MAX_SHIFT)) & NOC_GICRLPI4_GICR4_MPAMIDR_PARTID_MAX_MASK) #define NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_MPAMIDR_PMG_MAX_MASK (0x10000U) #define NOC_GICRLPI4_GICR4_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define NOC_GICRLPI4_GICR4_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPAMIDR_PMG_MAX_SHIFT)) & NOC_GICRLPI4_GICR4_MPAMIDR_PMG_MAX_MASK) #define NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_MPAMIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR4_PARTIDR - GICR4_PARTIDR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PARTIDR_PARTID_MASK (0x1FFU) #define NOC_GICRLPI4_GICR4_PARTIDR_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define NOC_GICRLPI4_GICR4_PARTIDR_PARTID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PARTIDR_PARTID_SHIFT)) & NOC_GICRLPI4_GICR4_PARTIDR_PARTID_MASK) #define NOC_GICRLPI4_GICR4_PARTIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI4_GICR4_PARTIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PARTIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PARTIDR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PARTIDR_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_PARTIDR_PMG_MASK (0x10000U) #define NOC_GICRLPI4_GICR4_PARTIDR_PMG_SHIFT (16U) /*! PMG - PMG */ #define NOC_GICRLPI4_GICR4_PARTIDR_PMG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PARTIDR_PMG_SHIFT)) & NOC_GICRLPI4_GICR4_PARTIDR_PMG_MASK) #define NOC_GICRLPI4_GICR4_PARTIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI4_GICR4_PARTIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_PARTIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PARTIDR_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_PARTIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR4_FCTLR - GICR4_FCTLR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_FCTLR_SIP_MASK (0x1U) #define NOC_GICRLPI4_GICR4_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICRLPI4_GICR4_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_FCTLR_SIP_SHIFT)) & NOC_GICRLPI4_GICR4_FCTLR_SIP_MASK) #define NOC_GICRLPI4_GICR4_FCTLR_QDeny_MASK (0x2U) #define NOC_GICRLPI4_GICR4_FCTLR_QDeny_SHIFT (1U) /*! QDeny - QDeny */ #define NOC_GICRLPI4_GICR4_FCTLR_QDeny(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_FCTLR_QDeny_SHIFT)) & NOC_GICRLPI4_GICR4_FCTLR_QDeny_MASK) #define NOC_GICRLPI4_GICR4_FCTLR_CGO_MASK (0x1CU) #define NOC_GICRLPI4_GICR4_FCTLR_CGO_SHIFT (2U) /*! CGO - CGO */ #define NOC_GICRLPI4_GICR4_FCTLR_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_FCTLR_CGO_SHIFT)) & NOC_GICRLPI4_GICR4_FCTLR_CGO_MASK) #define NOC_GICRLPI4_GICR4_FCTLR_RESERVED0_MASK (0x3E0U) #define NOC_GICRLPI4_GICR4_FCTLR_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_FCTLR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_FCTLR_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_FCTLR_RESERVED1_MASK (0xFFFFFC00U) #define NOC_GICRLPI4_GICR4_FCTLR_RESERVED1_SHIFT (10U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_FCTLR_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_FCTLR_RESERVED1_MASK) /*! @} */ /*! @name GICR4_PWRR - GICR4_PWRR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PWRR_RDPD_MASK (0x1U) #define NOC_GICRLPI4_GICR4_PWRR_RDPD_SHIFT (0U) /*! RDPD - RDPD */ #define NOC_GICRLPI4_GICR4_PWRR_RDPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RDPD_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RDPD_MASK) #define NOC_GICRLPI4_GICR4_PWRR_RDAG_MASK (0x2U) #define NOC_GICRLPI4_GICR4_PWRR_RDAG_SHIFT (1U) /*! RDAG - RDAG */ #define NOC_GICRLPI4_GICR4_PWRR_RDAG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RDAG_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RDAG_MASK) #define NOC_GICRLPI4_GICR4_PWRR_RDGPD_MASK (0x4U) #define NOC_GICRLPI4_GICR4_PWRR_RDGPD_SHIFT (2U) /*! RDGPD - RDGPD */ #define NOC_GICRLPI4_GICR4_PWRR_RDGPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RDGPD_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RDGPD_MASK) #define NOC_GICRLPI4_GICR4_PWRR_RDGPO_MASK (0x8U) #define NOC_GICRLPI4_GICR4_PWRR_RDGPO_SHIFT (3U) /*! RDGPO - RDGPO */ #define NOC_GICRLPI4_GICR4_PWRR_RDGPO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RDGPO_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RDGPO_MASK) #define NOC_GICRLPI4_GICR4_PWRR_RESERVED0_MASK (0xF0U) #define NOC_GICRLPI4_GICR4_PWRR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PWRR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_PWRR_RDGO_MASK (0x7F00U) #define NOC_GICRLPI4_GICR4_PWRR_RDGO_SHIFT (8U) /*! RDGO - RDGO */ #define NOC_GICRLPI4_GICR4_PWRR_RDGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RDGO_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RDGO_MASK) #define NOC_GICRLPI4_GICR4_PWRR_RDG_MASK (0xFF8000U) #define NOC_GICRLPI4_GICR4_PWRR_RDG_SHIFT (15U) /*! RDG - RDG */ #define NOC_GICRLPI4_GICR4_PWRR_RDG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RDG_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RDG_MASK) #define NOC_GICRLPI4_GICR4_PWRR_RESERVED1_MASK (0xFF000000U) #define NOC_GICRLPI4_GICR4_PWRR_RESERVED1_SHIFT (24U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_PWRR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PWRR_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_PWRR_RESERVED1_MASK) /*! @} */ /*! @name GICR4_CLASS - GICR4_CLASS */ /*! @{ */ #define NOC_GICRLPI4_GICR4_CLASS_Class_MASK (0x1U) #define NOC_GICRLPI4_GICR4_CLASS_Class_SHIFT (0U) /*! Class - Class */ #define NOC_GICRLPI4_GICR4_CLASS_Class(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CLASS_Class_SHIFT)) & NOC_GICRLPI4_GICR4_CLASS_Class_MASK) #define NOC_GICRLPI4_GICR4_CLASS_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI4_GICR4_CLASS_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_CLASS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CLASS_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_CLASS_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PROPBASER - GICR4_PROPBASER */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PROPBASER_IDBits_MASK (0x1FU) #define NOC_GICRLPI4_GICR4_PROPBASER_IDBits_SHIFT (0U) /*! IDBits - IDBits */ #define NOC_GICRLPI4_GICR4_PROPBASER_IDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_IDBits_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_IDBits_MASK) #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED0_MASK (0x60U) #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_PROPBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI4_GICR4_PROPBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI4_GICR4_PROPBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_Cacheability_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_Cacheability_MASK) #define NOC_GICRLPI4_GICR4_PROPBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI4_GICR4_PROPBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI4_GICR4_PROPBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_Shareability_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_Shareability_MASK) #define NOC_GICRLPI4_GICR4_PROPBASER_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GICRLPI4_GICR4_PROPBASER_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI4_GICR4_PROPBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_PhysicalAddress_MASK) #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED1_MASK (0xFFFFF000000000U) #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED1_SHIFT (36U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_RESERVED1_MASK) #define NOC_GICRLPI4_GICR4_PROPBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI4_GICR4_PROPBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI4_GICR4_PROPBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_OuterCacheability_MASK) #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED2_MASK (0xF800000000000000U) #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED2_SHIFT (59U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI4_GICR4_PROPBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PROPBASER_RESERVED2_SHIFT)) & NOC_GICRLPI4_GICR4_PROPBASER_RESERVED2_MASK) /*! @} */ /*! @name GICR4_PENDBASER - GICR4_PENDBASER */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED0_MASK (0x7FU) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI4_GICR4_PENDBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI4_GICR4_PENDBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_Cacheability_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_Cacheability_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI4_GICR4_PENDBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI4_GICR4_PENDBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_Shareability_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_Shareability_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED1_MASK (0xF000U) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_RESERVED1_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_PhysicalAddress_MASK (0xFFFFF0000U) #define NOC_GICRLPI4_GICR4_PENDBASER_PhysicalAddress_SHIFT (16U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI4_GICR4_PENDBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_PhysicalAddress_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED2_MASK (0xFFFFF000000000U) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED2_SHIFT (36U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_RESERVED2_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_RESERVED2_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI4_GICR4_PENDBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI4_GICR4_PENDBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_OuterCacheability_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED3_MASK (0x3800000000000000U) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED3_SHIFT (59U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_RESERVED3_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_RESERVED3_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_PendingTableZero_MASK (0x4000000000000000U) #define NOC_GICRLPI4_GICR4_PENDBASER_PendingTableZero_SHIFT (62U) /*! PendingTableZero - PendingTableZero */ #define NOC_GICRLPI4_GICR4_PENDBASER_PendingTableZero(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_PendingTableZero_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_PendingTableZero_MASK) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED4_MASK (0x8000000000000000U) #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED4_SHIFT (63U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRLPI4_GICR4_PENDBASER_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_PENDBASER_RESERVED4_SHIFT)) & NOC_GICRLPI4_GICR4_PENDBASER_RESERVED4_MASK) /*! @} */ /*! @name GICR4_INVLPIR - GICR4_INVLPIR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_INVLPIR_IntID_MASK (0xFFFFFFFFU) #define NOC_GICRLPI4_GICR4_INVLPIR_IntID_SHIFT (0U) /*! IntID - IntID */ #define NOC_GICRLPI4_GICR4_INVLPIR_IntID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVLPIR_IntID_SHIFT)) & NOC_GICRLPI4_GICR4_INVLPIR_IntID_MASK) #define NOC_GICRLPI4_GICR4_INVLPIR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI4_GICR4_INVLPIR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI4_GICR4_INVLPIR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVLPIR_VPEID_SHIFT)) & NOC_GICRLPI4_GICR4_INVLPIR_VPEID_MASK) #define NOC_GICRLPI4_GICR4_INVLPIR_RESERVED0_MASK (0x7FFF000000000000U) #define NOC_GICRLPI4_GICR4_INVLPIR_RESERVED0_SHIFT (48U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_INVLPIR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVLPIR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_INVLPIR_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_INVLPIR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI4_GICR4_INVLPIR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI4_GICR4_INVLPIR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVLPIR_V_SHIFT)) & NOC_GICRLPI4_GICR4_INVLPIR_V_MASK) /*! @} */ /*! @name GICR4_INVALLR - GICR4_INVALLR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_INVALLR_RESERVED0_MASK (0xFFFFFFFFU) #define NOC_GICRLPI4_GICR4_INVALLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_INVALLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVALLR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_INVALLR_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_INVALLR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI4_GICR4_INVALLR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI4_GICR4_INVALLR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVALLR_VPEID_SHIFT)) & NOC_GICRLPI4_GICR4_INVALLR_VPEID_MASK) #define NOC_GICRLPI4_GICR4_INVALLR_RESERVED1_MASK (0x7FFF000000000000U) #define NOC_GICRLPI4_GICR4_INVALLR_RESERVED1_SHIFT (48U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_INVALLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVALLR_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_INVALLR_RESERVED1_MASK) #define NOC_GICRLPI4_GICR4_INVALLR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI4_GICR4_INVALLR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI4_GICR4_INVALLR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI4_GICR4_INVALLR_V_SHIFT)) & NOC_GICRLPI4_GICR4_INVALLR_V_MASK) /*! @} */ /*! @name GICR4_SYNCR - GICR4_SYNCR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_SYNCR_Busy_MASK (0x1U) #define NOC_GICRLPI4_GICR4_SYNCR_Busy_SHIFT (0U) /*! Busy - Busy */ #define NOC_GICRLPI4_GICR4_SYNCR_Busy(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_SYNCR_Busy_SHIFT)) & NOC_GICRLPI4_GICR4_SYNCR_Busy_MASK) #define NOC_GICRLPI4_GICR4_SYNCR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI4_GICR4_SYNCR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_SYNCR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_SYNCR_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_SYNCR_RESERVED0_MASK) /*! @} */ /*! @name GICR4_MPIDR - GICR4_MPIDR */ /*! @{ */ #define NOC_GICRLPI4_GICR4_MPIDR_Affinity0_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_MPIDR_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICRLPI4_GICR4_MPIDR_Affinity0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPIDR_Affinity0_SHIFT)) & NOC_GICRLPI4_GICR4_MPIDR_Affinity0_MASK) #define NOC_GICRLPI4_GICR4_MPIDR_Affinity1_MASK (0xFF00U) #define NOC_GICRLPI4_GICR4_MPIDR_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 */ #define NOC_GICRLPI4_GICR4_MPIDR_Affinity1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPIDR_Affinity1_SHIFT)) & NOC_GICRLPI4_GICR4_MPIDR_Affinity1_MASK) #define NOC_GICRLPI4_GICR4_MPIDR_Affinity2_MASK (0xFF0000U) #define NOC_GICRLPI4_GICR4_MPIDR_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICRLPI4_GICR4_MPIDR_Affinity2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPIDR_Affinity2_SHIFT)) & NOC_GICRLPI4_GICR4_MPIDR_Affinity2_MASK) #define NOC_GICRLPI4_GICR4_MPIDR_Affinity3_MASK (0xFF000000U) #define NOC_GICRLPI4_GICR4_MPIDR_Affinity3_SHIFT (24U) /*! Affinity3 - Affinity3 */ #define NOC_GICRLPI4_GICR4_MPIDR_Affinity3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_MPIDR_Affinity3_SHIFT)) & NOC_GICRLPI4_GICR4_MPIDR_Affinity3_MASK) /*! @} */ /*! @name GICR4_PIDR4 - GICR4_PIDR4 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR4_DES_2_MASK (0xFU) #define NOC_GICRLPI4_GICR4_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICRLPI4_GICR4_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR4_DES_2_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR4_DES_2_MASK) #define NOC_GICRLPI4_GICR4_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICRLPI4_GICR4_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICRLPI4_GICR4_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR4_SIZE_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR4_SIZE_MASK) #define NOC_GICRLPI4_GICR4_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR4_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PIDR5 - GICR4_PIDR5 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI4_GICR4_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR5_RESERVED_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR5_RESERVED_MASK) #define NOC_GICRLPI4_GICR4_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR5_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PIDR6 - GICR4_PIDR6 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI4_GICR4_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR6_RESERVED_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR6_RESERVED_MASK) #define NOC_GICRLPI4_GICR4_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR6_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PIDR7 - GICR4_PIDR7 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI4_GICR4_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR7_RESERVED_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR7_RESERVED_MASK) #define NOC_GICRLPI4_GICR4_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR7_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PIDR0 - GICR4_PIDR0 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICRLPI4_GICR4_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR0_PART_0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR0_PART_0_MASK) #define NOC_GICRLPI4_GICR4_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PIDR1 - GICR4_PIDR1 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR1_PART_1_MASK (0xFU) #define NOC_GICRLPI4_GICR4_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICRLPI4_GICR4_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR1_PART_1_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR1_PART_1_MASK) #define NOC_GICRLPI4_GICR4_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICRLPI4_GICR4_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICRLPI4_GICR4_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR1_DES_0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR1_DES_0_MASK) #define NOC_GICRLPI4_GICR4_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PIDR2 - GICR4_PIDR2 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR2_DES_1_MASK (0x7U) #define NOC_GICRLPI4_GICR4_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICRLPI4_GICR4_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR2_DES_1_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR2_DES_1_MASK) #define NOC_GICRLPI4_GICR4_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICRLPI4_GICR4_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICRLPI4_GICR4_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR2_JEDEC_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR2_JEDEC_MASK) #define NOC_GICRLPI4_GICR4_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICRLPI4_GICR4_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICRLPI4_GICR4_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR2_REVISION_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR2_REVISION_MASK) #define NOC_GICRLPI4_GICR4_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR4_PIDR3 - GICR4_PIDR3 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_PIDR3_CMOD_MASK (0x7U) #define NOC_GICRLPI4_GICR4_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICRLPI4_GICR4_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR3_CMOD_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR3_CMOD_MASK) #define NOC_GICRLPI4_GICR4_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICRLPI4_GICR4_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR3_RESERVED0_MASK) #define NOC_GICRLPI4_GICR4_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICRLPI4_GICR4_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICRLPI4_GICR4_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR3_REVAND_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR3_REVAND_MASK) #define NOC_GICRLPI4_GICR4_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI4_GICR4_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_PIDR3_RESERVED1_SHIFT)) & NOC_GICRLPI4_GICR4_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICR4_CIDR0 - GICR4_CIDR0 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICRLPI4_GICR4_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR0_PRMBL_0_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR0_PRMBL_0_MASK) #define NOC_GICRLPI4_GICR4_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR4_CIDR1 - GICR4_CIDR1 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICRLPI4_GICR4_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICRLPI4_GICR4_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR1_PRMBL_1_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR1_PRMBL_1_MASK) #define NOC_GICRLPI4_GICR4_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICRLPI4_GICR4_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICRLPI4_GICR4_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR1_CLASS_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR1_CLASS_MASK) #define NOC_GICRLPI4_GICR4_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR4_CIDR2 - GICR4_CIDR2 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICRLPI4_GICR4_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR2_PRMBL_2_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR2_PRMBL_2_MASK) #define NOC_GICRLPI4_GICR4_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR4_CIDR3 - GICR4_CIDR3 */ /*! @{ */ #define NOC_GICRLPI4_GICR4_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICRLPI4_GICR4_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICRLPI4_GICR4_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR3_PRMBL_3_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR3_PRMBL_3_MASK) #define NOC_GICRLPI4_GICR4_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI4_GICR4_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI4_GICR4_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI4_GICR4_CIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI4_GICR4_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRLPI4_Register_Masks */ /* NOC_GICRLPI4 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRLPI4 base address */ #define NOC__GIC__GICRLPI4_BASE (0x480E0000u) /** Peripheral NOC__GIC__GICRLPI4 base pointer */ #define NOC__GIC__GICRLPI4 ((NOC_GICRLPI4_Type *)NOC__GIC__GICRLPI4_BASE) /** Array initializer of NOC_GICRLPI4 peripheral base addresses */ #define NOC_GICRLPI4_BASE_ADDRS { NOC__GIC__GICRLPI4_BASE } /** Array initializer of NOC_GICRLPI4 peripheral base pointers */ #define NOC_GICRLPI4_BASE_PTRS { NOC__GIC__GICRLPI4 } /*! * @} */ /* end of group NOC_GICRLPI4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRLPI5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI5_Peripheral_Access_Layer NOC_GICRLPI5 Peripheral Access Layer * @{ */ /** NOC_GICRLPI5 - Register Layout Typedef */ typedef struct { __IO uint32_t GICR5_CTLR; /**< GICR5_CTLR, offset: 0x0 */ __I uint32_t GICR5_IIDR; /**< GICR5_IIDR, offset: 0x4 */ __I uint64_t GICR5_TYPER; /**< GICR5_TYPER, offset: 0x8 */ __I uint32_t GICR5_STATUSR; /**< GICR5_STATUSR, offset: 0x10 */ __IO uint32_t GICR5_WAKER; /**< GICR5_WAKER, offset: 0x14 */ __I uint32_t GICR5_MPAMIDR; /**< GICR5_MPAMIDR, offset: 0x18 */ __IO uint32_t GICR5_PARTIDR; /**< GICR5_PARTIDR, offset: 0x1C */ __IO uint32_t GICR5_FCTLR; /**< GICR5_FCTLR, offset: 0x20 */ __IO uint32_t GICR5_PWRR; /**< GICR5_PWRR, offset: 0x24 */ __IO uint32_t GICR5_CLASS; /**< GICR5_CLASS, offset: 0x28 */ uint8_t RESERVED_0[68]; __IO uint64_t GICR5_PROPBASER; /**< GICR5_PROPBASER, offset: 0x70 */ __IO uint64_t GICR5_PENDBASER; /**< GICR5_PENDBASER, offset: 0x78 */ uint8_t RESERVED_1[32]; __O uint64_t GICR5_INVLPIR; /**< GICR5_INVLPIR, offset: 0xA0 */ uint8_t RESERVED_2[8]; __O uint64_t GICR5_INVALLR; /**< GICR5_INVALLR, offset: 0xB0 */ uint8_t RESERVED_3[8]; __I uint32_t GICR5_SYNCR; /**< GICR5_SYNCR, offset: 0xC0 */ uint8_t RESERVED_4[60]; __O uint32_t GICR5_MPIDR; /**< GICR5_MPIDR, offset: 0x100 */ uint8_t RESERVED_5[65228]; __I uint32_t GICR5_PIDR4; /**< GICR5_PIDR4, offset: 0xFFD0 */ __I uint32_t GICR5_PIDR5; /**< GICR5_PIDR5, offset: 0xFFD4 */ __I uint32_t GICR5_PIDR6; /**< GICR5_PIDR6, offset: 0xFFD8 */ __I uint32_t GICR5_PIDR7; /**< GICR5_PIDR7, offset: 0xFFDC */ __I uint32_t GICR5_PIDR0; /**< GICR5_PIDR0, offset: 0xFFE0 */ __I uint32_t GICR5_PIDR1; /**< GICR5_PIDR1, offset: 0xFFE4 */ __I uint32_t GICR5_PIDR2; /**< GICR5_PIDR2, offset: 0xFFE8 */ __I uint32_t GICR5_PIDR3; /**< GICR5_PIDR3, offset: 0xFFEC */ __I uint32_t GICR5_CIDR0; /**< GICR5_CIDR0, offset: 0xFFF0 */ __I uint32_t GICR5_CIDR1; /**< GICR5_CIDR1, offset: 0xFFF4 */ __I uint32_t GICR5_CIDR2; /**< GICR5_CIDR2, offset: 0xFFF8 */ __I uint32_t GICR5_CIDR3; /**< GICR5_CIDR3, offset: 0xFFFC */ } NOC_GICRLPI5_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRLPI5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRLPI5_Register_Masks NOC_GICRLPI5 Register Masks * @{ */ /*! @name GICR5_CTLR - GICR5_CTLR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_CTLR_EnableLPIs_MASK (0x1U) #define NOC_GICRLPI5_GICR5_CTLR_EnableLPIs_SHIFT (0U) /*! EnableLPIs - EnableLPIs */ #define NOC_GICRLPI5_GICR5_CTLR_EnableLPIs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_EnableLPIs_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_EnableLPIs_MASK) #define NOC_GICRLPI5_GICR5_CTLR_CES_MASK (0x2U) #define NOC_GICRLPI5_GICR5_CTLR_CES_SHIFT (1U) /*! CES - CES */ #define NOC_GICRLPI5_GICR5_CTLR_CES(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_CES_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_CES_MASK) #define NOC_GICRLPI5_GICR5_CTLR_IR_MASK (0x4U) #define NOC_GICRLPI5_GICR5_CTLR_IR_SHIFT (2U) /*! IR - IR */ #define NOC_GICRLPI5_GICR5_CTLR_IR(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_IR_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_IR_MASK) #define NOC_GICRLPI5_GICR5_CTLR_RWP_MASK (0x8U) #define NOC_GICRLPI5_GICR5_CTLR_RWP_SHIFT (3U) /*! RWP - RWP */ #define NOC_GICRLPI5_GICR5_CTLR_RWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_RWP_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_RWP_MASK) #define NOC_GICRLPI5_GICR5_CTLR_RESERVED1_MASK (0xFFFFF0U) #define NOC_GICRLPI5_GICR5_CTLR_RESERVED1_SHIFT (4U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_CTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_RESERVED1_MASK) #define NOC_GICRLPI5_GICR5_CTLR_DPG0_MASK (0x1000000U) #define NOC_GICRLPI5_GICR5_CTLR_DPG0_SHIFT (24U) /*! DPG0 - DPG0 */ #define NOC_GICRLPI5_GICR5_CTLR_DPG0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_DPG0_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_DPG0_MASK) #define NOC_GICRLPI5_GICR5_CTLR_DPG1NS_MASK (0x2000000U) #define NOC_GICRLPI5_GICR5_CTLR_DPG1NS_SHIFT (25U) /*! DPG1NS - DPG1NS */ #define NOC_GICRLPI5_GICR5_CTLR_DPG1NS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_DPG1NS_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_DPG1NS_MASK) #define NOC_GICRLPI5_GICR5_CTLR_DPG1S_MASK (0x4000000U) #define NOC_GICRLPI5_GICR5_CTLR_DPG1S_SHIFT (26U) /*! DPG1S - DPG1S */ #define NOC_GICRLPI5_GICR5_CTLR_DPG1S(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_DPG1S_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_DPG1S_MASK) #define NOC_GICRLPI5_GICR5_CTLR_RESERVED2_MASK (0x78000000U) #define NOC_GICRLPI5_GICR5_CTLR_RESERVED2_SHIFT (27U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI5_GICR5_CTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_RESERVED2_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_RESERVED2_MASK) #define NOC_GICRLPI5_GICR5_CTLR_UWP_MASK (0x80000000U) #define NOC_GICRLPI5_GICR5_CTLR_UWP_SHIFT (31U) /*! UWP - UWP */ #define NOC_GICRLPI5_GICR5_CTLR_UWP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CTLR_UWP_SHIFT)) & NOC_GICRLPI5_GICR5_CTLR_UWP_MASK) /*! @} */ /*! @name GICR5_IIDR - GICR5_IIDR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_IIDR_Implementer_MASK (0xFFFU) #define NOC_GICRLPI5_GICR5_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GICRLPI5_GICR5_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_IIDR_Implementer_SHIFT)) & NOC_GICRLPI5_GICR5_IIDR_Implementer_MASK) #define NOC_GICRLPI5_GICR5_IIDR_Revision_MASK (0xF000U) #define NOC_GICRLPI5_GICR5_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GICRLPI5_GICR5_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_IIDR_Revision_SHIFT)) & NOC_GICRLPI5_GICR5_IIDR_Revision_MASK) #define NOC_GICRLPI5_GICR5_IIDR_Variant_MASK (0xF0000U) #define NOC_GICRLPI5_GICR5_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GICRLPI5_GICR5_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_IIDR_Variant_SHIFT)) & NOC_GICRLPI5_GICR5_IIDR_Variant_MASK) #define NOC_GICRLPI5_GICR5_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GICRLPI5_GICR5_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_IIDR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_IIDR_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GICRLPI5_GICR5_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GICRLPI5_GICR5_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_IIDR_ProductID_SHIFT)) & NOC_GICRLPI5_GICR5_IIDR_ProductID_MASK) /*! @} */ /*! @name GICR5_TYPER - GICR5_TYPER */ /*! @{ */ #define NOC_GICRLPI5_GICR5_TYPER_PLPIS_MASK (0x1U) #define NOC_GICRLPI5_GICR5_TYPER_PLPIS_SHIFT (0U) /*! PLPIS - PLPIS */ #define NOC_GICRLPI5_GICR5_TYPER_PLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_PLPIS_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_PLPIS_MASK) #define NOC_GICRLPI5_GICR5_TYPER_VLPIS_MASK (0x2U) #define NOC_GICRLPI5_GICR5_TYPER_VLPIS_SHIFT (1U) /*! VLPIS - VLPIS */ #define NOC_GICRLPI5_GICR5_TYPER_VLPIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_VLPIS_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_VLPIS_MASK) #define NOC_GICRLPI5_GICR5_TYPER_Dirty_MASK (0x4U) #define NOC_GICRLPI5_GICR5_TYPER_Dirty_SHIFT (2U) /*! Dirty - Dirty */ #define NOC_GICRLPI5_GICR5_TYPER_Dirty(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_Dirty_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_Dirty_MASK) #define NOC_GICRLPI5_GICR5_TYPER_DirectLPI_MASK (0x8U) #define NOC_GICRLPI5_GICR5_TYPER_DirectLPI_SHIFT (3U) /*! DirectLPI - DirectLPI */ #define NOC_GICRLPI5_GICR5_TYPER_DirectLPI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_DirectLPI_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_DirectLPI_MASK) #define NOC_GICRLPI5_GICR5_TYPER_Last_MASK (0x10U) #define NOC_GICRLPI5_GICR5_TYPER_Last_SHIFT (4U) /*! Last - Last */ #define NOC_GICRLPI5_GICR5_TYPER_Last(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_Last_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_Last_MASK) #define NOC_GICRLPI5_GICR5_TYPER_DPGS_MASK (0x20U) #define NOC_GICRLPI5_GICR5_TYPER_DPGS_SHIFT (5U) /*! DPGS - DPGS */ #define NOC_GICRLPI5_GICR5_TYPER_DPGS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_DPGS_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_DPGS_MASK) #define NOC_GICRLPI5_GICR5_TYPER_MPAM_MASK (0x40U) #define NOC_GICRLPI5_GICR5_TYPER_MPAM_SHIFT (6U) /*! MPAM - MPAM */ #define NOC_GICRLPI5_GICR5_TYPER_MPAM(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_MPAM_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_MPAM_MASK) #define NOC_GICRLPI5_GICR5_TYPER_RVPEID_MASK (0x80U) #define NOC_GICRLPI5_GICR5_TYPER_RVPEID_SHIFT (7U) /*! RVPEID - RVPEID */ #define NOC_GICRLPI5_GICR5_TYPER_RVPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_RVPEID_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_RVPEID_MASK) #define NOC_GICRLPI5_GICR5_TYPER_ProcessorNumber_MASK (0xFFFF00U) #define NOC_GICRLPI5_GICR5_TYPER_ProcessorNumber_SHIFT (8U) /*! ProcessorNumber - ProcessorNumber */ #define NOC_GICRLPI5_GICR5_TYPER_ProcessorNumber(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_ProcessorNumber_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_ProcessorNumber_MASK) #define NOC_GICRLPI5_GICR5_TYPER_CommonLPIAff_MASK (0x3000000U) #define NOC_GICRLPI5_GICR5_TYPER_CommonLPIAff_SHIFT (24U) /*! CommonLPIAff - CommonLPIAff */ #define NOC_GICRLPI5_GICR5_TYPER_CommonLPIAff(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_CommonLPIAff_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_CommonLPIAff_MASK) #define NOC_GICRLPI5_GICR5_TYPER_VSGI_MASK (0x4000000U) #define NOC_GICRLPI5_GICR5_TYPER_VSGI_SHIFT (26U) /*! VSGI - VSGI */ #define NOC_GICRLPI5_GICR5_TYPER_VSGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_VSGI_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_VSGI_MASK) #define NOC_GICRLPI5_GICR5_TYPER_PPInum_MASK (0xF8000000U) #define NOC_GICRLPI5_GICR5_TYPER_PPInum_SHIFT (27U) /*! PPInum - PPInum */ #define NOC_GICRLPI5_GICR5_TYPER_PPInum(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_PPInum_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_PPInum_MASK) #define NOC_GICRLPI5_GICR5_TYPER_AffinityValue_MASK (0xFFFFFFFF00000000U) #define NOC_GICRLPI5_GICR5_TYPER_AffinityValue_SHIFT (32U) /*! AffinityValue - AffinityValue */ #define NOC_GICRLPI5_GICR5_TYPER_AffinityValue(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_TYPER_AffinityValue_SHIFT)) & NOC_GICRLPI5_GICR5_TYPER_AffinityValue_MASK) /*! @} */ /*! @name GICR5_STATUSR - GICR5_STATUSR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_STATUSR_RESERVED_MASK (0xFFFFFFFFU) #define NOC_GICRLPI5_GICR5_STATUSR_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI5_GICR5_STATUSR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_STATUSR_RESERVED_SHIFT)) & NOC_GICRLPI5_GICR5_STATUSR_RESERVED_MASK) /*! @} */ /*! @name GICR5_WAKER - GICR5_WAKER */ /*! @{ */ #define NOC_GICRLPI5_GICR5_WAKER_Sleep_MASK (0x1U) #define NOC_GICRLPI5_GICR5_WAKER_Sleep_SHIFT (0U) /*! Sleep - Sleep */ #define NOC_GICRLPI5_GICR5_WAKER_Sleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_WAKER_Sleep_SHIFT)) & NOC_GICRLPI5_GICR5_WAKER_Sleep_MASK) #define NOC_GICRLPI5_GICR5_WAKER_ProcessorSleep_MASK (0x2U) #define NOC_GICRLPI5_GICR5_WAKER_ProcessorSleep_SHIFT (1U) /*! ProcessorSleep - ProcessorSleep */ #define NOC_GICRLPI5_GICR5_WAKER_ProcessorSleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_WAKER_ProcessorSleep_SHIFT)) & NOC_GICRLPI5_GICR5_WAKER_ProcessorSleep_MASK) #define NOC_GICRLPI5_GICR5_WAKER_ChildrenAsleep_MASK (0x4U) #define NOC_GICRLPI5_GICR5_WAKER_ChildrenAsleep_SHIFT (2U) /*! ChildrenAsleep - ChildrenAsleep */ #define NOC_GICRLPI5_GICR5_WAKER_ChildrenAsleep(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_WAKER_ChildrenAsleep_SHIFT)) & NOC_GICRLPI5_GICR5_WAKER_ChildrenAsleep_MASK) #define NOC_GICRLPI5_GICR5_WAKER_RESERVED0_MASK (0x7FFFFFF8U) #define NOC_GICRLPI5_GICR5_WAKER_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_WAKER_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_WAKER_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_WAKER_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_WAKER_Quiescent_MASK (0x80000000U) #define NOC_GICRLPI5_GICR5_WAKER_Quiescent_SHIFT (31U) /*! Quiescent - Quiescent */ #define NOC_GICRLPI5_GICR5_WAKER_Quiescent(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_WAKER_Quiescent_SHIFT)) & NOC_GICRLPI5_GICR5_WAKER_Quiescent_MASK) /*! @} */ /*! @name GICR5_MPAMIDR - GICR5_MPAMIDR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_MPAMIDR_PARTID_MAX_MASK (0x1FFU) #define NOC_GICRLPI5_GICR5_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define NOC_GICRLPI5_GICR5_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPAMIDR_PARTID_MAX_SHIFT)) & NOC_GICRLPI5_GICR5_MPAMIDR_PARTID_MAX_MASK) #define NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_MPAMIDR_PMG_MAX_MASK (0x10000U) #define NOC_GICRLPI5_GICR5_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define NOC_GICRLPI5_GICR5_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPAMIDR_PMG_MAX_SHIFT)) & NOC_GICRLPI5_GICR5_MPAMIDR_PMG_MAX_MASK) #define NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_MPAMIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR5_PARTIDR - GICR5_PARTIDR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PARTIDR_PARTID_MASK (0x1FFU) #define NOC_GICRLPI5_GICR5_PARTIDR_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define NOC_GICRLPI5_GICR5_PARTIDR_PARTID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PARTIDR_PARTID_SHIFT)) & NOC_GICRLPI5_GICR5_PARTIDR_PARTID_MASK) #define NOC_GICRLPI5_GICR5_PARTIDR_RESERVED0_MASK (0xFE00U) #define NOC_GICRLPI5_GICR5_PARTIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PARTIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PARTIDR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PARTIDR_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_PARTIDR_PMG_MASK (0x10000U) #define NOC_GICRLPI5_GICR5_PARTIDR_PMG_SHIFT (16U) /*! PMG - PMG */ #define NOC_GICRLPI5_GICR5_PARTIDR_PMG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PARTIDR_PMG_SHIFT)) & NOC_GICRLPI5_GICR5_PARTIDR_PMG_MASK) #define NOC_GICRLPI5_GICR5_PARTIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GICRLPI5_GICR5_PARTIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_PARTIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PARTIDR_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_PARTIDR_RESERVED1_MASK) /*! @} */ /*! @name GICR5_FCTLR - GICR5_FCTLR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_FCTLR_SIP_MASK (0x1U) #define NOC_GICRLPI5_GICR5_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GICRLPI5_GICR5_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_FCTLR_SIP_SHIFT)) & NOC_GICRLPI5_GICR5_FCTLR_SIP_MASK) #define NOC_GICRLPI5_GICR5_FCTLR_QDeny_MASK (0x2U) #define NOC_GICRLPI5_GICR5_FCTLR_QDeny_SHIFT (1U) /*! QDeny - QDeny */ #define NOC_GICRLPI5_GICR5_FCTLR_QDeny(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_FCTLR_QDeny_SHIFT)) & NOC_GICRLPI5_GICR5_FCTLR_QDeny_MASK) #define NOC_GICRLPI5_GICR5_FCTLR_CGO_MASK (0x1CU) #define NOC_GICRLPI5_GICR5_FCTLR_CGO_SHIFT (2U) /*! CGO - CGO */ #define NOC_GICRLPI5_GICR5_FCTLR_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_FCTLR_CGO_SHIFT)) & NOC_GICRLPI5_GICR5_FCTLR_CGO_MASK) #define NOC_GICRLPI5_GICR5_FCTLR_RESERVED0_MASK (0x3E0U) #define NOC_GICRLPI5_GICR5_FCTLR_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_FCTLR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_FCTLR_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_FCTLR_RESERVED1_MASK (0xFFFFFC00U) #define NOC_GICRLPI5_GICR5_FCTLR_RESERVED1_SHIFT (10U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_FCTLR_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_FCTLR_RESERVED1_MASK) /*! @} */ /*! @name GICR5_PWRR - GICR5_PWRR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PWRR_RDPD_MASK (0x1U) #define NOC_GICRLPI5_GICR5_PWRR_RDPD_SHIFT (0U) /*! RDPD - RDPD */ #define NOC_GICRLPI5_GICR5_PWRR_RDPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RDPD_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RDPD_MASK) #define NOC_GICRLPI5_GICR5_PWRR_RDAG_MASK (0x2U) #define NOC_GICRLPI5_GICR5_PWRR_RDAG_SHIFT (1U) /*! RDAG - RDAG */ #define NOC_GICRLPI5_GICR5_PWRR_RDAG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RDAG_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RDAG_MASK) #define NOC_GICRLPI5_GICR5_PWRR_RDGPD_MASK (0x4U) #define NOC_GICRLPI5_GICR5_PWRR_RDGPD_SHIFT (2U) /*! RDGPD - RDGPD */ #define NOC_GICRLPI5_GICR5_PWRR_RDGPD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RDGPD_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RDGPD_MASK) #define NOC_GICRLPI5_GICR5_PWRR_RDGPO_MASK (0x8U) #define NOC_GICRLPI5_GICR5_PWRR_RDGPO_SHIFT (3U) /*! RDGPO - RDGPO */ #define NOC_GICRLPI5_GICR5_PWRR_RDGPO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RDGPO_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RDGPO_MASK) #define NOC_GICRLPI5_GICR5_PWRR_RESERVED0_MASK (0xF0U) #define NOC_GICRLPI5_GICR5_PWRR_RESERVED0_SHIFT (4U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PWRR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_PWRR_RDGO_MASK (0x7F00U) #define NOC_GICRLPI5_GICR5_PWRR_RDGO_SHIFT (8U) /*! RDGO - RDGO */ #define NOC_GICRLPI5_GICR5_PWRR_RDGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RDGO_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RDGO_MASK) #define NOC_GICRLPI5_GICR5_PWRR_RDG_MASK (0xFF8000U) #define NOC_GICRLPI5_GICR5_PWRR_RDG_SHIFT (15U) /*! RDG - RDG */ #define NOC_GICRLPI5_GICR5_PWRR_RDG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RDG_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RDG_MASK) #define NOC_GICRLPI5_GICR5_PWRR_RESERVED1_MASK (0xFF000000U) #define NOC_GICRLPI5_GICR5_PWRR_RESERVED1_SHIFT (24U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_PWRR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PWRR_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_PWRR_RESERVED1_MASK) /*! @} */ /*! @name GICR5_CLASS - GICR5_CLASS */ /*! @{ */ #define NOC_GICRLPI5_GICR5_CLASS_Class_MASK (0x1U) #define NOC_GICRLPI5_GICR5_CLASS_Class_SHIFT (0U) /*! Class - Class */ #define NOC_GICRLPI5_GICR5_CLASS_Class(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CLASS_Class_SHIFT)) & NOC_GICRLPI5_GICR5_CLASS_Class_MASK) #define NOC_GICRLPI5_GICR5_CLASS_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI5_GICR5_CLASS_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_CLASS_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CLASS_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_CLASS_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PROPBASER - GICR5_PROPBASER */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PROPBASER_IDBits_MASK (0x1FU) #define NOC_GICRLPI5_GICR5_PROPBASER_IDBits_SHIFT (0U) /*! IDBits - IDBits */ #define NOC_GICRLPI5_GICR5_PROPBASER_IDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_IDBits_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_IDBits_MASK) #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED0_MASK (0x60U) #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED0_SHIFT (5U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_PROPBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI5_GICR5_PROPBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI5_GICR5_PROPBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_Cacheability_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_Cacheability_MASK) #define NOC_GICRLPI5_GICR5_PROPBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI5_GICR5_PROPBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI5_GICR5_PROPBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_Shareability_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_Shareability_MASK) #define NOC_GICRLPI5_GICR5_PROPBASER_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GICRLPI5_GICR5_PROPBASER_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI5_GICR5_PROPBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_PhysicalAddress_MASK) #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED1_MASK (0xFFFFF000000000U) #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED1_SHIFT (36U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_RESERVED1_MASK) #define NOC_GICRLPI5_GICR5_PROPBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI5_GICR5_PROPBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI5_GICR5_PROPBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_OuterCacheability_MASK) #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED2_MASK (0xF800000000000000U) #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED2_SHIFT (59U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI5_GICR5_PROPBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PROPBASER_RESERVED2_SHIFT)) & NOC_GICRLPI5_GICR5_PROPBASER_RESERVED2_MASK) /*! @} */ /*! @name GICR5_PENDBASER - GICR5_PENDBASER */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED0_MASK (0x7FU) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_Cacheability_MASK (0x380U) #define NOC_GICRLPI5_GICR5_PENDBASER_Cacheability_SHIFT (7U) /*! Cacheability - Cacheability */ #define NOC_GICRLPI5_GICR5_PENDBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_Cacheability_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_Cacheability_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_Shareability_MASK (0xC00U) #define NOC_GICRLPI5_GICR5_PENDBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GICRLPI5_GICR5_PENDBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_Shareability_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_Shareability_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED1_MASK (0xF000U) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_RESERVED1_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_PhysicalAddress_MASK (0xFFFFF0000U) #define NOC_GICRLPI5_GICR5_PENDBASER_PhysicalAddress_SHIFT (16U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GICRLPI5_GICR5_PENDBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_PhysicalAddress_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_PhysicalAddress_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED2_MASK (0xFFFFF000000000U) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED2_SHIFT (36U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_RESERVED2_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_RESERVED2_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_OuterCacheability_MASK (0x700000000000000U) #define NOC_GICRLPI5_GICR5_PENDBASER_OuterCacheability_SHIFT (56U) /*! OuterCacheability - OuterCacheability */ #define NOC_GICRLPI5_GICR5_PENDBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_OuterCacheability_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_OuterCacheability_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED3_MASK (0x3800000000000000U) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED3_SHIFT (59U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_RESERVED3_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_RESERVED3_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_PendingTableZero_MASK (0x4000000000000000U) #define NOC_GICRLPI5_GICR5_PENDBASER_PendingTableZero_SHIFT (62U) /*! PendingTableZero - PendingTableZero */ #define NOC_GICRLPI5_GICR5_PENDBASER_PendingTableZero(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_PendingTableZero_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_PendingTableZero_MASK) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED4_MASK (0x8000000000000000U) #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED4_SHIFT (63U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRLPI5_GICR5_PENDBASER_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_PENDBASER_RESERVED4_SHIFT)) & NOC_GICRLPI5_GICR5_PENDBASER_RESERVED4_MASK) /*! @} */ /*! @name GICR5_INVLPIR - GICR5_INVLPIR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_INVLPIR_IntID_MASK (0xFFFFFFFFU) #define NOC_GICRLPI5_GICR5_INVLPIR_IntID_SHIFT (0U) /*! IntID - IntID */ #define NOC_GICRLPI5_GICR5_INVLPIR_IntID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVLPIR_IntID_SHIFT)) & NOC_GICRLPI5_GICR5_INVLPIR_IntID_MASK) #define NOC_GICRLPI5_GICR5_INVLPIR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI5_GICR5_INVLPIR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI5_GICR5_INVLPIR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVLPIR_VPEID_SHIFT)) & NOC_GICRLPI5_GICR5_INVLPIR_VPEID_MASK) #define NOC_GICRLPI5_GICR5_INVLPIR_RESERVED0_MASK (0x7FFF000000000000U) #define NOC_GICRLPI5_GICR5_INVLPIR_RESERVED0_SHIFT (48U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_INVLPIR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVLPIR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_INVLPIR_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_INVLPIR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI5_GICR5_INVLPIR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI5_GICR5_INVLPIR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVLPIR_V_SHIFT)) & NOC_GICRLPI5_GICR5_INVLPIR_V_MASK) /*! @} */ /*! @name GICR5_INVALLR - GICR5_INVALLR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_INVALLR_RESERVED0_MASK (0xFFFFFFFFU) #define NOC_GICRLPI5_GICR5_INVALLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_INVALLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVALLR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_INVALLR_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_INVALLR_VPEID_MASK (0xFFFF00000000U) #define NOC_GICRLPI5_GICR5_INVALLR_VPEID_SHIFT (32U) /*! VPEID - VPEID */ #define NOC_GICRLPI5_GICR5_INVALLR_VPEID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVALLR_VPEID_SHIFT)) & NOC_GICRLPI5_GICR5_INVALLR_VPEID_MASK) #define NOC_GICRLPI5_GICR5_INVALLR_RESERVED1_MASK (0x7FFF000000000000U) #define NOC_GICRLPI5_GICR5_INVALLR_RESERVED1_SHIFT (48U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_INVALLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVALLR_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_INVALLR_RESERVED1_MASK) #define NOC_GICRLPI5_GICR5_INVALLR_V_MASK (0x8000000000000000U) #define NOC_GICRLPI5_GICR5_INVALLR_V_SHIFT (63U) /*! V - V */ #define NOC_GICRLPI5_GICR5_INVALLR_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRLPI5_GICR5_INVALLR_V_SHIFT)) & NOC_GICRLPI5_GICR5_INVALLR_V_MASK) /*! @} */ /*! @name GICR5_SYNCR - GICR5_SYNCR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_SYNCR_Busy_MASK (0x1U) #define NOC_GICRLPI5_GICR5_SYNCR_Busy_SHIFT (0U) /*! Busy - Busy */ #define NOC_GICRLPI5_GICR5_SYNCR_Busy(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_SYNCR_Busy_SHIFT)) & NOC_GICRLPI5_GICR5_SYNCR_Busy_MASK) #define NOC_GICRLPI5_GICR5_SYNCR_RESERVED0_MASK (0xFFFFFFFEU) #define NOC_GICRLPI5_GICR5_SYNCR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_SYNCR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_SYNCR_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_SYNCR_RESERVED0_MASK) /*! @} */ /*! @name GICR5_MPIDR - GICR5_MPIDR */ /*! @{ */ #define NOC_GICRLPI5_GICR5_MPIDR_Affinity0_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_MPIDR_Affinity0_SHIFT (0U) /*! Affinity0 - Affinity0 */ #define NOC_GICRLPI5_GICR5_MPIDR_Affinity0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPIDR_Affinity0_SHIFT)) & NOC_GICRLPI5_GICR5_MPIDR_Affinity0_MASK) #define NOC_GICRLPI5_GICR5_MPIDR_Affinity1_MASK (0xFF00U) #define NOC_GICRLPI5_GICR5_MPIDR_Affinity1_SHIFT (8U) /*! Affinity1 - Affinity1 */ #define NOC_GICRLPI5_GICR5_MPIDR_Affinity1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPIDR_Affinity1_SHIFT)) & NOC_GICRLPI5_GICR5_MPIDR_Affinity1_MASK) #define NOC_GICRLPI5_GICR5_MPIDR_Affinity2_MASK (0xFF0000U) #define NOC_GICRLPI5_GICR5_MPIDR_Affinity2_SHIFT (16U) /*! Affinity2 - Affinity2 */ #define NOC_GICRLPI5_GICR5_MPIDR_Affinity2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPIDR_Affinity2_SHIFT)) & NOC_GICRLPI5_GICR5_MPIDR_Affinity2_MASK) #define NOC_GICRLPI5_GICR5_MPIDR_Affinity3_MASK (0xFF000000U) #define NOC_GICRLPI5_GICR5_MPIDR_Affinity3_SHIFT (24U) /*! Affinity3 - Affinity3 */ #define NOC_GICRLPI5_GICR5_MPIDR_Affinity3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_MPIDR_Affinity3_SHIFT)) & NOC_GICRLPI5_GICR5_MPIDR_Affinity3_MASK) /*! @} */ /*! @name GICR5_PIDR4 - GICR5_PIDR4 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR4_DES_2_MASK (0xFU) #define NOC_GICRLPI5_GICR5_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICRLPI5_GICR5_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR4_DES_2_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR4_DES_2_MASK) #define NOC_GICRLPI5_GICR5_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICRLPI5_GICR5_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICRLPI5_GICR5_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR4_SIZE_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR4_SIZE_MASK) #define NOC_GICRLPI5_GICR5_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR4_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PIDR5 - GICR5_PIDR5 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI5_GICR5_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR5_RESERVED_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR5_RESERVED_MASK) #define NOC_GICRLPI5_GICR5_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR5_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PIDR6 - GICR5_PIDR6 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI5_GICR5_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR6_RESERVED_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR6_RESERVED_MASK) #define NOC_GICRLPI5_GICR5_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR6_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PIDR7 - GICR5_PIDR7 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICRLPI5_GICR5_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR7_RESERVED_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR7_RESERVED_MASK) #define NOC_GICRLPI5_GICR5_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR7_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PIDR0 - GICR5_PIDR0 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICRLPI5_GICR5_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR0_PART_0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR0_PART_0_MASK) #define NOC_GICRLPI5_GICR5_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PIDR1 - GICR5_PIDR1 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR1_PART_1_MASK (0xFU) #define NOC_GICRLPI5_GICR5_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICRLPI5_GICR5_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR1_PART_1_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR1_PART_1_MASK) #define NOC_GICRLPI5_GICR5_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICRLPI5_GICR5_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICRLPI5_GICR5_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR1_DES_0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR1_DES_0_MASK) #define NOC_GICRLPI5_GICR5_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PIDR2 - GICR5_PIDR2 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR2_DES_1_MASK (0x7U) #define NOC_GICRLPI5_GICR5_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICRLPI5_GICR5_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR2_DES_1_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR2_DES_1_MASK) #define NOC_GICRLPI5_GICR5_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICRLPI5_GICR5_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICRLPI5_GICR5_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR2_JEDEC_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR2_JEDEC_MASK) #define NOC_GICRLPI5_GICR5_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICRLPI5_GICR5_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICRLPI5_GICR5_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR2_REVISION_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR2_REVISION_MASK) #define NOC_GICRLPI5_GICR5_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR5_PIDR3 - GICR5_PIDR3 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_PIDR3_CMOD_MASK (0x7U) #define NOC_GICRLPI5_GICR5_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICRLPI5_GICR5_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR3_CMOD_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR3_CMOD_MASK) #define NOC_GICRLPI5_GICR5_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICRLPI5_GICR5_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR3_RESERVED0_MASK) #define NOC_GICRLPI5_GICR5_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICRLPI5_GICR5_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICRLPI5_GICR5_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR3_REVAND_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR3_REVAND_MASK) #define NOC_GICRLPI5_GICR5_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRLPI5_GICR5_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_PIDR3_RESERVED1_SHIFT)) & NOC_GICRLPI5_GICR5_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICR5_CIDR0 - GICR5_CIDR0 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICRLPI5_GICR5_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR0_PRMBL_0_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR0_PRMBL_0_MASK) #define NOC_GICRLPI5_GICR5_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR0_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICR5_CIDR1 - GICR5_CIDR1 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICRLPI5_GICR5_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICRLPI5_GICR5_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR1_PRMBL_1_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR1_PRMBL_1_MASK) #define NOC_GICRLPI5_GICR5_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICRLPI5_GICR5_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICRLPI5_GICR5_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR1_CLASS_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR1_CLASS_MASK) #define NOC_GICRLPI5_GICR5_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR1_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICR5_CIDR2 - GICR5_CIDR2 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICRLPI5_GICR5_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR2_PRMBL_2_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR2_PRMBL_2_MASK) #define NOC_GICRLPI5_GICR5_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR2_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICR5_CIDR3 - GICR5_CIDR3 */ /*! @{ */ #define NOC_GICRLPI5_GICR5_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICRLPI5_GICR5_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICRLPI5_GICR5_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR3_PRMBL_3_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR3_PRMBL_3_MASK) #define NOC_GICRLPI5_GICR5_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICRLPI5_GICR5_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRLPI5_GICR5_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRLPI5_GICR5_CIDR3_RESERVED0_SHIFT)) & NOC_GICRLPI5_GICR5_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRLPI5_Register_Masks */ /* NOC_GICRLPI5 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRLPI5 base address */ #define NOC__GIC__GICRLPI5_BASE (0x48100000u) /** Peripheral NOC__GIC__GICRLPI5 base pointer */ #define NOC__GIC__GICRLPI5 ((NOC_GICRLPI5_Type *)NOC__GIC__GICRLPI5_BASE) /** Array initializer of NOC_GICRLPI5 peripheral base addresses */ #define NOC_GICRLPI5_BASE_ADDRS { NOC__GIC__GICRLPI5_BASE } /** Array initializer of NOC_GICRLPI5 peripheral base pointers */ #define NOC_GICRLPI5_BASE_PTRS { NOC__GIC__GICRLPI5 } /*! * @} */ /* end of group NOC_GICRLPI5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRSGI0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI0_Peripheral_Access_Layer NOC_GICRSGI0 Peripheral Access Layer * @{ */ /** NOC_GICRSGI0 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[128]; __IO uint32_t GICR0_IGROUPR0; /**< GICR0_IGROUPR0, offset: 0x80 */ uint8_t RESERVED_1[124]; __IO uint32_t GICR0_ISENABLER0; /**< GICR0_ISENABLER0, offset: 0x100 */ uint8_t RESERVED_2[124]; __IO uint32_t GICR0_ICENABLER0; /**< GICR0_ICENABLER0, offset: 0x180 */ uint8_t RESERVED_3[124]; __IO uint32_t GICR0_ISPENDR0; /**< GICR0_ISPENDR0, offset: 0x200 */ uint8_t RESERVED_4[124]; __IO uint32_t GICR0_ICPENDR0; /**< GICR0_ICPENDR0, offset: 0x280 */ uint8_t RESERVED_5[124]; __IO uint32_t GICR0_ISACTIVER0; /**< GICR0_ISACTIVER0, offset: 0x300 */ uint8_t RESERVED_6[124]; __IO uint32_t GICR0_ICACTIVER0; /**< GICR0_ICACTIVER0, offset: 0x380 */ uint8_t RESERVED_7[124]; __IO uint32_t GICR0_IPRIORITYR0; /**< GICR0_IPRIORITYR0, offset: 0x400 */ __IO uint32_t GICR0_IPRIORITYR1; /**< GICR0_IPRIORITYR1, offset: 0x404 */ __IO uint32_t GICR0_IPRIORITYR2; /**< GICR0_IPRIORITYR2, offset: 0x408 */ __IO uint32_t GICR0_IPRIORITYR3; /**< GICR0_IPRIORITYR3, offset: 0x40C */ __IO uint32_t GICR0_IPRIORITYR4; /**< GICR0_IPRIORITYR4, offset: 0x410 */ __IO uint32_t GICR0_IPRIORITYR5; /**< GICR0_IPRIORITYR5, offset: 0x414 */ __IO uint32_t GICR0_IPRIORITYR6; /**< GICR0_IPRIORITYR6, offset: 0x418 */ __IO uint32_t GICR0_IPRIORITYR7; /**< GICR0_IPRIORITYR7, offset: 0x41C */ uint8_t RESERVED_8[2016]; __I uint32_t GICR0_ICFGR0; /**< GICR0_ICFGR0, offset: 0xC00 */ __IO uint32_t GICR0_ICFGR1; /**< GICR0_ICFGR1, offset: 0xC04 */ uint8_t RESERVED_9[248]; __IO uint32_t GICR0_IGRPMODR0; /**< GICR0_IGRPMODR0, offset: 0xD00 */ uint8_t RESERVED_10[252]; __IO uint32_t GICR0_NSACR; /**< GICR0_NSACR, offset: 0xE00 */ uint8_t RESERVED_11[45564]; __I uint32_t GICR0_MISCSTATUSR; /**< GICR0_MISCSTATUSR, offset: 0xC000 */ uint8_t RESERVED_12[4]; __IO uint32_t GICR0_IERRVR; /**< GICR0_IERRVR, offset: 0xC008 */ uint8_t RESERVED_13[4]; __IO uint64_t GICR0_SGIDR; /**< GICR0_SGIDR, offset: 0xC010 */ __IO uint32_t GICR0_DPRIR; /**< GICR0_DPRIR, offset: 0xC018 */ uint8_t RESERVED_14[228]; __IO uint32_t GICR0_ICERRR0; /**< GICR0_ICERRR0, offset: 0xC100 */ uint8_t RESERVED_15[124]; __IO uint32_t GICR0_ISERRR0; /**< GICR0_ISERRR0, offset: 0xC180 */ uint8_t RESERVED_16[11900]; __I uint32_t GICR0_CFGID0; /**< GICR0_CFGID0, offset: 0xF000 */ __I uint32_t GICR0_CFGID1; /**< GICR0_CFGID1, offset: 0xF004 */ } NOC_GICRSGI0_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRSGI0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI0_Register_Masks NOC_GICRSGI0 Register Masks * @{ */ /*! @name GICR0_IGROUPR0 - GICR0_IGROUPR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit0_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit1_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit2_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit3_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit4_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit5_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit6_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit7_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit8_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit9_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit10_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit11_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit12_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit13_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit14_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit15_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit16_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit17_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit18_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit19_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit20_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit21_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit22_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit23_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit24_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit25_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit26_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit27_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit28_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit29_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit30_MASK) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_IGROUPR0_group_status_bit31_MASK) /*! @} */ /*! @name GICR0_ISENABLER0 - GICR0_ISENABLER0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit0_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit1_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit2_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit3_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit4_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit5_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit6_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit7_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit8_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit9_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit10_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit11_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit12_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit13_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit14_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit15_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit16_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit17_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit18_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit19_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit20_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit21_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit22_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit23_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit24_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit25_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit26_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit27_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit28_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit29_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit30_MASK) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ISENABLER0_set_enable_bit31_MASK) /*! @} */ /*! @name GICR0_ICENABLER0 - GICR0_ICENABLER0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit0_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit1_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit2_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit3_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit4_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit5_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit6_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit7_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit8_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit9_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit10_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit11_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit12_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit13_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit14_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit15_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit16_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit17_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit18_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit19_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit20_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit21_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit22_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit23_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit24_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit25_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit26_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit27_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit28_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit29_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit30_MASK) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ICENABLER0_clear_enable_bit31_MASK) /*! @} */ /*! @name GICR0_ISPENDR0 - GICR0_ISPENDR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit0_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit1_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit2_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit3_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit4_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit5_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit6_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit7_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit8_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit9_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit10_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit11_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit12_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit13_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit14_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit15_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit16_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit17_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit18_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit19_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit20_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit21_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit22_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit23_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit24_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit25_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit26_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit27_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit28_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit29_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit30_MASK) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ISPENDR0_set_pending_bit31_MASK) /*! @} */ /*! @name GICR0_ICPENDR0 - GICR0_ICPENDR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit0_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit1_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit2_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit3_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit4_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit5_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit6_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit7_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit8_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit9_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit10_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit11_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit12_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit13_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit14_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit15_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit16_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit17_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit18_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit19_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit20_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit21_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit22_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit23_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit24_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit25_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit26_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit27_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit28_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit29_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit30_MASK) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ICPENDR0_clear_pending_bit31_MASK) /*! @} */ /*! @name GICR0_ISACTIVER0 - GICR0_ISACTIVER0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit0_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit1_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit2_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit3_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit4_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit5_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit6_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit7_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit8_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit9_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit10_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit11_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit12_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit13_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit14_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit15_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit16_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit17_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit18_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit19_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit20_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit21_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit22_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit23_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit24_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit25_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit26_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit27_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit28_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit29_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit30_MASK) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ISACTIVER0_set_active_bit31_MASK) /*! @} */ /*! @name GICR0_ICACTIVER0 - GICR0_ICACTIVER0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit0_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit1_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit2_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit3_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit4_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit5_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit6_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit7_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit8_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit9_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit10_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit11_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit12_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit13_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit14_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit15_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit16_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit17_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit18_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit19_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit20_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit21_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit22_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit23_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit24_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit25_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit26_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit27_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit28_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit29_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit30_MASK) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ICACTIVER0_clear_active_bit31_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR0 - GICR0_IPRIORITYR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR0_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR0_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR0_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR0_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR0_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR0_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR0_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR0_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR0_offset3_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR1 - GICR0_IPRIORITYR1 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR1_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR1_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR1_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR1_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR1_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR1_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR1_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR1_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR1_offset3_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR2 - GICR0_IPRIORITYR2 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR2_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR2_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR2_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR2_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR2_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR2_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR2_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR2_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR2_offset3_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR3 - GICR0_IPRIORITYR3 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR3_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR3_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR3_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR3_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR3_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR3_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR3_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR3_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR3_offset3_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR4 - GICR0_IPRIORITYR4 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR4_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR4_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR4_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR4_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR4_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR4_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR4_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR4_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR4_offset3_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR5 - GICR0_IPRIORITYR5 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR5_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR5_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR5_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR5_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR5_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR5_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR5_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR5_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR5_offset3_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR6 - GICR0_IPRIORITYR6 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR6_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR6_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR6_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR6_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR6_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR6_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR6_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR6_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR6_offset3_MASK) /*! @} */ /*! @name GICR0_IPRIORITYR7 - GICR0_IPRIORITYR7 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset0_MASK (0xFFU) #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR7_offset0_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR7_offset0_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset1_MASK (0xFF00U) #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR7_offset1_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR7_offset1_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset2_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR7_offset2_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR7_offset2_MASK) #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset3_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI0_GICR0_IPRIORITYR7_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IPRIORITYR7_offset3_SHIFT)) & NOC_GICRSGI0_GICR0_IPRIORITYR7_offset3_MASK) /*! @} */ /*! @name GICR0_ICFGR0 - GICR0_ICFGR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config0_MASK (0x3U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config0_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config0_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config1_MASK (0xCU) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config1_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config1_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config2_MASK (0x30U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config2_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config2_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config3_MASK (0xC0U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config3_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config3_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config4_MASK (0x300U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config4_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config4_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config5_MASK (0xC00U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config5_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config5_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config6_MASK (0x3000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config6_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config6_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config7_MASK (0xC000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config7_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config7_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config8_MASK (0x30000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config8_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config8_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config9_MASK (0xC0000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config9_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config9_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config10_MASK (0x300000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config10_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config10_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config11_MASK (0xC00000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config11_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config11_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config12_MASK (0x3000000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config12_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config12_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config13_MASK (0xC000000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config13_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config13_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config14_MASK (0x30000000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config14_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config14_MASK) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI0_GICR0_ICFGR0_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR0_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR0_int_config15_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR0_int_config15_MASK) /*! @} */ /*! @name GICR0_ICFGR1 - GICR0_ICFGR1 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config0_MASK (0x3U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config0_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config0_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config1_MASK (0xCU) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config1_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config1_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config2_MASK (0x30U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config2_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config2_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config3_MASK (0xC0U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config3_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config3_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config4_MASK (0x300U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config4_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config4_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config5_MASK (0xC00U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config5_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config5_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config6_MASK (0x3000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config6_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config6_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config7_MASK (0xC000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config7_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config7_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config8_MASK (0x30000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config8_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config8_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config9_MASK (0xC0000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config9_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config9_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config10_MASK (0x300000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config10_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config10_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config11_MASK (0xC00000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config11_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config11_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config12_MASK (0x3000000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config12_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config12_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config13_MASK (0xC000000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config13_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config13_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config14_MASK (0x30000000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config14_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config14_MASK) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI0_GICR0_ICFGR1_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI0_GICR0_ICFGR1_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICFGR1_int_config15_SHIFT)) & NOC_GICRSGI0_GICR0_ICFGR1_int_config15_MASK) /*! @} */ /*! @name GICR0_IGRPMODR0 - GICR0_IGRPMODR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit0_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit1_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit2_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit3_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit4_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit5_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit6_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit7_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit8_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit9_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit10_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit11_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit12_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit13_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit14_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit15_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit16_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit17_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit18_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit19_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit20_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit21_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit22_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit23_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit24_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit25_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit26_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit27_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit28_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit29_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit30_MASK) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_IGRPMODR0_group_modifier_bit31_MASK) /*! @} */ /*! @name GICR0_NSACR - GICR0_NSACR */ /*! @{ */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access0_MASK (0x3U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access0_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access0_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access1_MASK (0xCU) #define NOC_GICRSGI0_GICR0_NSACR_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access1_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access1_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access2_MASK (0x30U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access2_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access2_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access3_MASK (0xC0U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access3_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access3_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access4_MASK (0x300U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access4_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access4_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access5_MASK (0xC00U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access5_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access5_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access6_MASK (0x3000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access6_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access6_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access7_MASK (0xC000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access7_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access7_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access8_MASK (0x30000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access8_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access8_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access9_MASK (0xC0000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access9_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access9_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access10_MASK (0x300000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access10_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access10_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access11_MASK (0xC00000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access11_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access11_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access12_MASK (0x3000000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access12_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access12_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access13_MASK (0xC000000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access13_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access13_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access14_MASK (0x30000000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access14_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access14_MASK) #define NOC_GICRSGI0_GICR0_NSACR_ns_access15_MASK (0xC0000000U) #define NOC_GICRSGI0_GICR0_NSACR_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICRSGI0_GICR0_NSACR_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_NSACR_ns_access15_SHIFT)) & NOC_GICRSGI0_GICR0_NSACR_ns_access15_MASK) /*! @} */ /*! @name GICR0_MISCSTATUSR - GICR0_MISCSTATUSR */ /*! @{ */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp0_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp0_MASK) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_ns_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_ns_MASK) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_s_MASK (0x4U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_s_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_EnableGrp1_s_MASK) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED0_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED0_MASK) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_access_type_MASK (0x10U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_access_type_SHIFT (4U) /*! access_type - access_type */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_access_type(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_access_type_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_access_type_MASK) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED1_MASK (0x3FFFFFE0U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED1_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_RESERVED1_MASK) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_wake_request_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_wake_request_SHIFT (30U) /*! wake_request - wake_request */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_wake_request(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_wake_request_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_wake_request_MASK) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_cpu_active_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_MISCSTATUSR_cpu_active_SHIFT (31U) /*! cpu_active - cpu_active */ #define NOC_GICRSGI0_GICR0_MISCSTATUSR_cpu_active(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_MISCSTATUSR_cpu_active_SHIFT)) & NOC_GICRSGI0_GICR0_MISCSTATUSR_cpu_active_MASK) /*! @} */ /*! @name GICR0_IERRVR - GICR0_IERRVR */ /*! @{ */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit0_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit1_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit2_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit3_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit4_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit5_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit6_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit7_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit8_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit9_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit10_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit11_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit12_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit13_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit14_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit15_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit16_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit17_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit18_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit19_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit20_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit21_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit22_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit23_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit24_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit25_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit26_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit27_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit28_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit29_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit30_MASK) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI0_GICR0_IERRVR_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_IERRVR_valid_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_IERRVR_valid_bit31_MASK) /*! @} */ /*! @name GICR0_SGIDR - GICR0_SGIDR */ /*! @{ */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr0_SHIFT (0U) /*! nsacr0 - nsacr0 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr0_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr0_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp0_MASK (0x2U) #define NOC_GICRSGI0_GICR0_SGIDR_grp0_SHIFT (1U) /*! grp0 - grp0 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp0_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp0_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod0_MASK (0x4U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod0_SHIFT (2U) /*! grpmod0 - grpmod0 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod0_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod0_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED0_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED0_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr1_MASK (0x10U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr1_SHIFT (4U) /*! nsacr1 - nsacr1 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr1_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr1_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp1_MASK (0x20U) #define NOC_GICRSGI0_GICR0_SGIDR_grp1_SHIFT (5U) /*! grp1 - grp1 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp1_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp1_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod1_MASK (0x40U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod1_SHIFT (6U) /*! grpmod1 - grpmod1 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod1_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod1_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED1_MASK (0x80U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED1_SHIFT (7U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED1_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED1_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr2_MASK (0x100U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr2_SHIFT (8U) /*! nsacr2 - nsacr2 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr2_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr2_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp2_MASK (0x200U) #define NOC_GICRSGI0_GICR0_SGIDR_grp2_SHIFT (9U) /*! grp2 - grp2 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp2_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp2_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod2_MASK (0x400U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod2_SHIFT (10U) /*! grpmod2 - grpmod2 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod2_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod2_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED2_MASK (0x800U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED2_SHIFT (11U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED2_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED2_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr3_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr3_SHIFT (12U) /*! nsacr3 - nsacr3 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr3_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr3_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp3_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp3_SHIFT (13U) /*! grp3 - grp3 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp3_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp3_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod3_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod3_SHIFT (14U) /*! grpmod3 - grpmod3 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod3_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod3_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED3_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED3_SHIFT (15U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED3_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED3_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr4_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr4_SHIFT (16U) /*! nsacr4 - nsacr4 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr4_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr4_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp4_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp4_SHIFT (17U) /*! grp4 - grp4 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp4_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp4_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod4_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod4_SHIFT (18U) /*! grpmod4 - grpmod4 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod4_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod4_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED4_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED4_SHIFT (19U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED4_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED4_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr5_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr5_SHIFT (20U) /*! nsacr5 - nsacr5 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr5_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr5_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp5_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp5_SHIFT (21U) /*! grp5 - grp5 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp5_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp5_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod5_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod5_SHIFT (22U) /*! grpmod5 - grpmod5 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod5_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod5_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED5_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED5_SHIFT (23U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED5_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED5_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr6_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr6_SHIFT (24U) /*! nsacr6 - nsacr6 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr6_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr6_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp6_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp6_SHIFT (25U) /*! grp6 - grp6 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp6_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp6_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod6_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod6_SHIFT (26U) /*! grpmod6 - grpmod6 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod6_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod6_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED6_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED6_SHIFT (27U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED6_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED6_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr7_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr7_SHIFT (28U) /*! nsacr7 - nsacr7 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr7_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr7_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp7_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp7_SHIFT (29U) /*! grp7 - grp7 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp7_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp7_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod7_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod7_SHIFT (30U) /*! grpmod7 - grpmod7 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod7_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod7_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED7_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED7_SHIFT (31U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED7_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED7_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr8_MASK (0x100000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr8_SHIFT (32U) /*! nsacr8 - nsacr8 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr8_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr8_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp8_MASK (0x200000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp8_SHIFT (33U) /*! grp8 - grp8 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp8_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp8_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod8_MASK (0x400000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod8_SHIFT (34U) /*! grpmod8 - grpmod8 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod8_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod8_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED8_MASK (0x800000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED8_SHIFT (35U) /*! RESERVED8 - RESERVED8 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED8_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED8_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr9_MASK (0x1000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr9_SHIFT (36U) /*! nsacr9 - nsacr9 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr9_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr9_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp9_MASK (0x2000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp9_SHIFT (37U) /*! grp9 - grp9 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp9_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp9_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod9_MASK (0x4000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod9_SHIFT (38U) /*! grpmod9 - grpmod9 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod9_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod9_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED9_MASK (0x8000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED9_SHIFT (39U) /*! RESERVED9 - RESERVED9 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED9_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED9_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr10_MASK (0x10000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr10_SHIFT (40U) /*! nsacr10 - nsacr10 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr10_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr10_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp10_MASK (0x20000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp10_SHIFT (41U) /*! grp10 - grp10 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp10_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp10_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod10_MASK (0x40000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod10_SHIFT (42U) /*! grpmod10 - grpmod10 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod10_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod10_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED10_MASK (0x80000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED10_SHIFT (43U) /*! RESERVED10 - RESERVED10 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED10_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED10_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr11_MASK (0x100000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr11_SHIFT (44U) /*! nsacr11 - nsacr11 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr11_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr11_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp11_MASK (0x200000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp11_SHIFT (45U) /*! grp11 - grp11 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp11_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp11_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod11_MASK (0x400000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod11_SHIFT (46U) /*! grpmod11 - grpmod11 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod11_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod11_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED11_MASK (0x800000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED11_SHIFT (47U) /*! RESERVED11 - RESERVED11 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED11_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED11_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr12_MASK (0x1000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr12_SHIFT (48U) /*! nsacr12 - nsacr12 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr12_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr12_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp12_MASK (0x2000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp12_SHIFT (49U) /*! grp12 - grp12 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp12_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp12_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod12_MASK (0x4000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod12_SHIFT (50U) /*! grpmod12 - grpmod12 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod12_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod12_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED12_MASK (0x8000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED12_SHIFT (51U) /*! RESERVED12 - RESERVED12 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED12_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED12_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr13_MASK (0x10000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr13_SHIFT (52U) /*! nsacr13 - nsacr13 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr13_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr13_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp13_MASK (0x20000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp13_SHIFT (53U) /*! grp13 - grp13 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp13_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp13_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod13_MASK (0x40000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod13_SHIFT (54U) /*! grpmod13 - grpmod13 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod13_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod13_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED13_MASK (0x80000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED13_SHIFT (55U) /*! RESERVED13 - RESERVED13 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED13_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED13_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr14_MASK (0x100000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr14_SHIFT (56U) /*! nsacr14 - nsacr14 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr14_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr14_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp14_MASK (0x200000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp14_SHIFT (57U) /*! grp14 - grp14 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp14_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp14_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod14_MASK (0x400000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod14_SHIFT (58U) /*! grpmod14 - grpmod14 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod14_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod14_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED15_MASK (0x800000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED15_SHIFT (59U) /*! RESERVED15 - RESERVED15 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED15_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED15_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr15_MASK (0x1000000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_nsacr15_SHIFT (60U) /*! nsacr15 - nsacr15 */ #define NOC_GICRSGI0_GICR0_SGIDR_nsacr15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_nsacr15_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_nsacr15_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grp15_MASK (0x2000000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grp15_SHIFT (61U) /*! grp15 - grp15 */ #define NOC_GICRSGI0_GICR0_SGIDR_grp15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grp15_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grp15_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod15_MASK (0x4000000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_grpmod15_SHIFT (62U) /*! grpmod15 - grpmod15 */ #define NOC_GICRSGI0_GICR0_SGIDR_grpmod15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_grpmod15_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_grpmod15_MASK) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED16_MASK (0x8000000000000000U) #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED16_SHIFT (63U) /*! RESERVED16 - RESERVED16 */ #define NOC_GICRSGI0_GICR0_SGIDR_RESERVED16(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI0_GICR0_SGIDR_RESERVED16_SHIFT)) & NOC_GICRSGI0_GICR0_SGIDR_RESERVED16_MASK) /*! @} */ /*! @name GICR0_DPRIR - GICR0_DPRIR */ /*! @{ */ #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED3_MASK (0x7U) #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED3_SHIFT (0U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_DPRIR_RESERVED3_SHIFT)) & NOC_GICRSGI0_GICR0_DPRIR_RESERVED3_MASK) #define NOC_GICRSGI0_GICR0_DPRIR_gpr0_pri_MASK (0xF8U) #define NOC_GICRSGI0_GICR0_DPRIR_gpr0_pri_SHIFT (3U) /*! gpr0_pri - gpr0_pri */ #define NOC_GICRSGI0_GICR0_DPRIR_gpr0_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_DPRIR_gpr0_pri_SHIFT)) & NOC_GICRSGI0_GICR0_DPRIR_gpr0_pri_MASK) #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED2_MASK (0x700U) #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED2_SHIFT (8U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_DPRIR_RESERVED2_SHIFT)) & NOC_GICRSGI0_GICR0_DPRIR_RESERVED2_MASK) #define NOC_GICRSGI0_GICR0_DPRIR_gpr1ns_pri_MASK (0xF800U) #define NOC_GICRSGI0_GICR0_DPRIR_gpr1ns_pri_SHIFT (11U) /*! gpr1ns_pri - gpr1ns_pri */ #define NOC_GICRSGI0_GICR0_DPRIR_gpr1ns_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_DPRIR_gpr1ns_pri_SHIFT)) & NOC_GICRSGI0_GICR0_DPRIR_gpr1ns_pri_MASK) #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED1_MASK (0x70000U) #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED1_SHIFT (16U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_DPRIR_RESERVED1_SHIFT)) & NOC_GICRSGI0_GICR0_DPRIR_RESERVED1_MASK) #define NOC_GICRSGI0_GICR0_DPRIR_gpr1sec_pri_MASK (0xF80000U) #define NOC_GICRSGI0_GICR0_DPRIR_gpr1sec_pri_SHIFT (19U) /*! gpr1sec_pri - gpr1sec_pri */ #define NOC_GICRSGI0_GICR0_DPRIR_gpr1sec_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_DPRIR_gpr1sec_pri_SHIFT)) & NOC_GICRSGI0_GICR0_DPRIR_gpr1sec_pri_MASK) #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED0_MASK (0xFF000000U) #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI0_GICR0_DPRIR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_DPRIR_RESERVED0_SHIFT)) & NOC_GICRSGI0_GICR0_DPRIR_RESERVED0_MASK) /*! @} */ /*! @name GICR0_ICERRR0 - GICR0_ICERRR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit0_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit1_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit2_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit3_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit4_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit5_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit6_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit7_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit8_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit9_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit10_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit11_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit12_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit13_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit14_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit15_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit16_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit17_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit18_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit19_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit20_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit21_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit22_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit23_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit24_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit25_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit26_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit27_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit28_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit29_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit30_MASK) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI0_GICR0_ICERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ICERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ICERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR0_ISERRR0 - GICR0_ISERRR0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit0_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit1_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit2_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit3_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit4_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit5_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit6_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit7_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit8_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit9_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit10_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit11_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit12_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit13_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit14_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit15_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit16_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit17_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit18_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit19_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit20_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit21_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit22_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit23_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit24_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit25_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit26_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit27_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit28_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit29_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit30_MASK) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI0_GICR0_ISERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_ISERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI0_GICR0_ISERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR0_CFGID0 - GICR0_CFGID0 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_CFGID0_PPINumber_MASK (0x1FFU) #define NOC_GICRSGI0_GICR0_CFGID0_PPINumber_SHIFT (0U) /*! PPINumber - PPINumber */ #define NOC_GICRSGI0_GICR0_CFGID0_PPINumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID0_PPINumber_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID0_PPINumber_MASK) #define NOC_GICRSGI0_GICR0_CFGID0_ECCSupport_MASK (0x200U) #define NOC_GICRSGI0_GICR0_CFGID0_ECCSupport_SHIFT (9U) /*! ECCSupport - ECCSupport */ #define NOC_GICRSGI0_GICR0_CFGID0_ECCSupport(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID0_ECCSupport_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID0_ECCSupport_MASK) #define NOC_GICRSGI0_GICR0_CFGID0_RESERVED0_MASK (0xFFFFFC00U) #define NOC_GICRSGI0_GICR0_CFGID0_RESERVED0_SHIFT (10U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI0_GICR0_CFGID0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID0_RESERVED0_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID0_RESERVED0_MASK) /*! @} */ /*! @name GICR0_CFGID1 - GICR0_CFGID1 */ /*! @{ */ #define NOC_GICRSGI0_GICR0_CFGID1_RESERVED0_MASK (0xFU) #define NOC_GICRSGI0_GICR0_CFGID1_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI0_GICR0_CFGID1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID1_RESERVED0_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID1_RESERVED0_MASK) #define NOC_GICRSGI0_GICR0_CFGID1_NumCPUs_MASK (0xFF0U) #define NOC_GICRSGI0_GICR0_CFGID1_NumCPUs_SHIFT (4U) /*! NumCPUs - NumCPUs */ #define NOC_GICRSGI0_GICR0_CFGID1_NumCPUs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID1_NumCPUs_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID1_NumCPUs_MASK) #define NOC_GICRSGI0_GICR0_CFGID1_RESERVED1_MASK (0xF000U) #define NOC_GICRSGI0_GICR0_CFGID1_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI0_GICR0_CFGID1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID1_RESERVED1_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID1_RESERVED1_MASK) #define NOC_GICRSGI0_GICR0_CFGID1_PPIsPerProcessor_MASK (0xFF0000U) #define NOC_GICRSGI0_GICR0_CFGID1_PPIsPerProcessor_SHIFT (16U) /*! PPIsPerProcessor - PPIsPerProcessor */ #define NOC_GICRSGI0_GICR0_CFGID1_PPIsPerProcessor(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID1_PPIsPerProcessor_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID1_PPIsPerProcessor_MASK) #define NOC_GICRSGI0_GICR0_CFGID1_REVAND_MASK (0xF000000U) #define NOC_GICRSGI0_GICR0_CFGID1_REVAND_SHIFT (24U) /*! REVAND - REVAND */ #define NOC_GICRSGI0_GICR0_CFGID1_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID1_REVAND_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID1_REVAND_MASK) #define NOC_GICRSGI0_GICR0_CFGID1_Version_MASK (0xF0000000U) #define NOC_GICRSGI0_GICR0_CFGID1_Version_SHIFT (28U) /*! Version - Version */ #define NOC_GICRSGI0_GICR0_CFGID1_Version(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI0_GICR0_CFGID1_Version_SHIFT)) & NOC_GICRSGI0_GICR0_CFGID1_Version_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRSGI0_Register_Masks */ /* NOC_GICRSGI0 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRSGI0 base address */ #define NOC__GIC__GICRSGI0_BASE (0x48070000u) /** Peripheral NOC__GIC__GICRSGI0 base pointer */ #define NOC__GIC__GICRSGI0 ((NOC_GICRSGI0_Type *)NOC__GIC__GICRSGI0_BASE) /** Array initializer of NOC_GICRSGI0 peripheral base addresses */ #define NOC_GICRSGI0_BASE_ADDRS { NOC__GIC__GICRSGI0_BASE } /** Array initializer of NOC_GICRSGI0 peripheral base pointers */ #define NOC_GICRSGI0_BASE_PTRS { NOC__GIC__GICRSGI0 } /*! * @} */ /* end of group NOC_GICRSGI0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRSGI1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI1_Peripheral_Access_Layer NOC_GICRSGI1 Peripheral Access Layer * @{ */ /** NOC_GICRSGI1 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[128]; __IO uint32_t GICR1_IGROUPR0; /**< GICR1_IGROUPR0, offset: 0x80 */ uint8_t RESERVED_1[124]; __IO uint32_t GICR1_ISENABLER0; /**< GICR1_ISENABLER0, offset: 0x100 */ uint8_t RESERVED_2[124]; __IO uint32_t GICR1_ICENABLER0; /**< GICR1_ICENABLER0, offset: 0x180 */ uint8_t RESERVED_3[124]; __IO uint32_t GICR1_ISPENDR0; /**< GICR1_ISPENDR0, offset: 0x200 */ uint8_t RESERVED_4[124]; __IO uint32_t GICR1_ICPENDR0; /**< GICR1_ICPENDR0, offset: 0x280 */ uint8_t RESERVED_5[124]; __IO uint32_t GICR1_ISACTIVER0; /**< GICR1_ISACTIVER0, offset: 0x300 */ uint8_t RESERVED_6[124]; __IO uint32_t GICR1_ICACTIVER0; /**< GICR1_ICACTIVER0, offset: 0x380 */ uint8_t RESERVED_7[124]; __IO uint32_t GICR1_IPRIORITYR0; /**< GICR1_IPRIORITYR0, offset: 0x400 */ __IO uint32_t GICR1_IPRIORITYR1; /**< GICR1_IPRIORITYR1, offset: 0x404 */ __IO uint32_t GICR1_IPRIORITYR2; /**< GICR1_IPRIORITYR2, offset: 0x408 */ __IO uint32_t GICR1_IPRIORITYR3; /**< GICR1_IPRIORITYR3, offset: 0x40C */ __IO uint32_t GICR1_IPRIORITYR4; /**< GICR1_IPRIORITYR4, offset: 0x410 */ __IO uint32_t GICR1_IPRIORITYR5; /**< GICR1_IPRIORITYR5, offset: 0x414 */ __IO uint32_t GICR1_IPRIORITYR6; /**< GICR1_IPRIORITYR6, offset: 0x418 */ __IO uint32_t GICR1_IPRIORITYR7; /**< GICR1_IPRIORITYR7, offset: 0x41C */ uint8_t RESERVED_8[2016]; __I uint32_t GICR1_ICFGR0; /**< GICR1_ICFGR0, offset: 0xC00 */ __IO uint32_t GICR1_ICFGR1; /**< GICR1_ICFGR1, offset: 0xC04 */ uint8_t RESERVED_9[248]; __IO uint32_t GICR1_IGRPMODR0; /**< GICR1_IGRPMODR0, offset: 0xD00 */ uint8_t RESERVED_10[252]; __IO uint32_t GICR1_NSACR; /**< GICR1_NSACR, offset: 0xE00 */ uint8_t RESERVED_11[45564]; __I uint32_t GICR1_MISCSTATUSR; /**< GICR1_MISCSTATUSR, offset: 0xC000 */ uint8_t RESERVED_12[4]; __IO uint32_t GICR1_IERRVR; /**< GICR1_IERRVR, offset: 0xC008 */ uint8_t RESERVED_13[4]; __IO uint64_t GICR1_SGIDR; /**< GICR1_SGIDR, offset: 0xC010 */ __IO uint32_t GICR1_DPRIR; /**< GICR1_DPRIR, offset: 0xC018 */ uint8_t RESERVED_14[228]; __IO uint32_t GICR1_ICERRR0; /**< GICR1_ICERRR0, offset: 0xC100 */ uint8_t RESERVED_15[124]; __IO uint32_t GICR1_ISERRR0; /**< GICR1_ISERRR0, offset: 0xC180 */ uint8_t RESERVED_16[11900]; __I uint32_t GICR1_CFGID0; /**< GICR1_CFGID0, offset: 0xF000 */ __I uint32_t GICR1_CFGID1; /**< GICR1_CFGID1, offset: 0xF004 */ } NOC_GICRSGI1_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRSGI1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI1_Register_Masks NOC_GICRSGI1 Register Masks * @{ */ /*! @name GICR1_IGROUPR0 - GICR1_IGROUPR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit0_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit1_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit2_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit3_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit4_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit5_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit6_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit7_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit8_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit9_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit10_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit11_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit12_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit13_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit14_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit15_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit16_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit17_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit18_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit19_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit20_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit21_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit22_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit23_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit24_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit25_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit26_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit27_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit28_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit29_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit30_MASK) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_IGROUPR0_group_status_bit31_MASK) /*! @} */ /*! @name GICR1_ISENABLER0 - GICR1_ISENABLER0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit0_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit1_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit2_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit3_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit4_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit5_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit6_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit7_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit8_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit9_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit10_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit11_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit12_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit13_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit14_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit15_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit16_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit17_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit18_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit19_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit20_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit21_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit22_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit23_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit24_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit25_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit26_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit27_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit28_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit29_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit30_MASK) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ISENABLER0_set_enable_bit31_MASK) /*! @} */ /*! @name GICR1_ICENABLER0 - GICR1_ICENABLER0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit0_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit1_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit2_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit3_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit4_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit5_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit6_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit7_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit8_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit9_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit10_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit11_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit12_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit13_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit14_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit15_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit16_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit17_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit18_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit19_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit20_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit21_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit22_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit23_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit24_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit25_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit26_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit27_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit28_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit29_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit30_MASK) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ICENABLER0_clear_enable_bit31_MASK) /*! @} */ /*! @name GICR1_ISPENDR0 - GICR1_ISPENDR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit0_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit1_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit2_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit3_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit4_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit5_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit6_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit7_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit8_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit9_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit10_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit11_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit12_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit13_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit14_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit15_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit16_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit17_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit18_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit19_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit20_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit21_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit22_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit23_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit24_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit25_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit26_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit27_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit28_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit29_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit30_MASK) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ISPENDR0_set_pending_bit31_MASK) /*! @} */ /*! @name GICR1_ICPENDR0 - GICR1_ICPENDR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit0_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit1_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit2_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit3_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit4_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit5_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit6_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit7_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit8_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit9_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit10_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit11_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit12_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit13_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit14_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit15_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit16_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit17_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit18_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit19_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit20_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit21_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit22_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit23_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit24_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit25_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit26_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit27_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit28_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit29_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit30_MASK) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ICPENDR0_clear_pending_bit31_MASK) /*! @} */ /*! @name GICR1_ISACTIVER0 - GICR1_ISACTIVER0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit0_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit1_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit2_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit3_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit4_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit5_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit6_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit7_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit8_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit9_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit10_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit11_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit12_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit13_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit14_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit15_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit16_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit17_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit18_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit19_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit20_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit21_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit22_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit23_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit24_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit25_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit26_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit27_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit28_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit29_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit30_MASK) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ISACTIVER0_set_active_bit31_MASK) /*! @} */ /*! @name GICR1_ICACTIVER0 - GICR1_ICACTIVER0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit0_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit1_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit2_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit3_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit4_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit5_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit6_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit7_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit8_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit9_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit10_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit11_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit12_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit13_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit14_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit15_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit16_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit17_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit18_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit19_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit20_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit21_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit22_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit23_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit24_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit25_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit26_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit27_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit28_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit29_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit30_MASK) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ICACTIVER0_clear_active_bit31_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR0 - GICR1_IPRIORITYR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR0_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR0_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR0_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR0_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR0_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR0_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR0_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR0_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR0_offset3_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR1 - GICR1_IPRIORITYR1 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR1_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR1_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR1_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR1_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR1_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR1_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR1_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR1_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR1_offset3_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR2 - GICR1_IPRIORITYR2 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR2_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR2_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR2_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR2_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR2_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR2_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR2_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR2_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR2_offset3_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR3 - GICR1_IPRIORITYR3 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR3_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR3_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR3_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR3_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR3_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR3_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR3_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR3_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR3_offset3_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR4 - GICR1_IPRIORITYR4 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR4_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR4_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR4_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR4_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR4_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR4_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR4_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR4_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR4_offset3_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR5 - GICR1_IPRIORITYR5 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR5_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR5_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR5_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR5_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR5_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR5_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR5_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR5_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR5_offset3_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR6 - GICR1_IPRIORITYR6 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR6_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR6_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR6_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR6_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR6_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR6_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR6_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR6_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR6_offset3_MASK) /*! @} */ /*! @name GICR1_IPRIORITYR7 - GICR1_IPRIORITYR7 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset0_MASK (0xFFU) #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR7_offset0_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR7_offset0_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset1_MASK (0xFF00U) #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR7_offset1_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR7_offset1_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset2_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR7_offset2_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR7_offset2_MASK) #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset3_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI1_GICR1_IPRIORITYR7_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IPRIORITYR7_offset3_SHIFT)) & NOC_GICRSGI1_GICR1_IPRIORITYR7_offset3_MASK) /*! @} */ /*! @name GICR1_ICFGR0 - GICR1_ICFGR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config0_MASK (0x3U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config0_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config0_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config1_MASK (0xCU) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config1_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config1_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config2_MASK (0x30U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config2_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config2_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config3_MASK (0xC0U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config3_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config3_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config4_MASK (0x300U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config4_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config4_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config5_MASK (0xC00U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config5_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config5_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config6_MASK (0x3000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config6_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config6_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config7_MASK (0xC000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config7_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config7_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config8_MASK (0x30000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config8_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config8_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config9_MASK (0xC0000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config9_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config9_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config10_MASK (0x300000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config10_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config10_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config11_MASK (0xC00000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config11_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config11_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config12_MASK (0x3000000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config12_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config12_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config13_MASK (0xC000000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config13_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config13_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config14_MASK (0x30000000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config14_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config14_MASK) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI1_GICR1_ICFGR0_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR0_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR0_int_config15_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR0_int_config15_MASK) /*! @} */ /*! @name GICR1_ICFGR1 - GICR1_ICFGR1 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config0_MASK (0x3U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config0_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config0_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config1_MASK (0xCU) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config1_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config1_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config2_MASK (0x30U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config2_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config2_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config3_MASK (0xC0U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config3_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config3_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config4_MASK (0x300U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config4_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config4_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config5_MASK (0xC00U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config5_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config5_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config6_MASK (0x3000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config6_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config6_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config7_MASK (0xC000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config7_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config7_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config8_MASK (0x30000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config8_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config8_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config9_MASK (0xC0000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config9_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config9_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config10_MASK (0x300000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config10_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config10_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config11_MASK (0xC00000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config11_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config11_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config12_MASK (0x3000000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config12_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config12_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config13_MASK (0xC000000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config13_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config13_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config14_MASK (0x30000000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config14_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config14_MASK) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI1_GICR1_ICFGR1_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI1_GICR1_ICFGR1_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICFGR1_int_config15_SHIFT)) & NOC_GICRSGI1_GICR1_ICFGR1_int_config15_MASK) /*! @} */ /*! @name GICR1_IGRPMODR0 - GICR1_IGRPMODR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit0_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit1_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit2_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit3_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit4_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit5_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit6_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit7_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit8_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit9_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit10_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit11_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit12_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit13_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit14_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit15_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit16_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit17_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit18_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit19_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit20_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit21_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit22_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit23_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit24_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit25_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit26_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit27_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit28_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit29_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit30_MASK) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_IGRPMODR0_group_modifier_bit31_MASK) /*! @} */ /*! @name GICR1_NSACR - GICR1_NSACR */ /*! @{ */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access0_MASK (0x3U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access0_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access0_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access1_MASK (0xCU) #define NOC_GICRSGI1_GICR1_NSACR_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access1_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access1_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access2_MASK (0x30U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access2_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access2_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access3_MASK (0xC0U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access3_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access3_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access4_MASK (0x300U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access4_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access4_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access5_MASK (0xC00U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access5_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access5_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access6_MASK (0x3000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access6_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access6_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access7_MASK (0xC000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access7_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access7_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access8_MASK (0x30000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access8_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access8_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access9_MASK (0xC0000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access9_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access9_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access10_MASK (0x300000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access10_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access10_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access11_MASK (0xC00000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access11_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access11_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access12_MASK (0x3000000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access12_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access12_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access13_MASK (0xC000000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access13_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access13_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access14_MASK (0x30000000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access14_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access14_MASK) #define NOC_GICRSGI1_GICR1_NSACR_ns_access15_MASK (0xC0000000U) #define NOC_GICRSGI1_GICR1_NSACR_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICRSGI1_GICR1_NSACR_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_NSACR_ns_access15_SHIFT)) & NOC_GICRSGI1_GICR1_NSACR_ns_access15_MASK) /*! @} */ /*! @name GICR1_MISCSTATUSR - GICR1_MISCSTATUSR */ /*! @{ */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp0_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp0_MASK) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_ns_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_ns_MASK) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_s_MASK (0x4U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_s_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_EnableGrp1_s_MASK) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED0_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED0_MASK) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_access_type_MASK (0x10U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_access_type_SHIFT (4U) /*! access_type - access_type */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_access_type(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_access_type_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_access_type_MASK) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED1_MASK (0x3FFFFFE0U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED1_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_RESERVED1_MASK) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_wake_request_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_wake_request_SHIFT (30U) /*! wake_request - wake_request */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_wake_request(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_wake_request_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_wake_request_MASK) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_cpu_active_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_MISCSTATUSR_cpu_active_SHIFT (31U) /*! cpu_active - cpu_active */ #define NOC_GICRSGI1_GICR1_MISCSTATUSR_cpu_active(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_MISCSTATUSR_cpu_active_SHIFT)) & NOC_GICRSGI1_GICR1_MISCSTATUSR_cpu_active_MASK) /*! @} */ /*! @name GICR1_IERRVR - GICR1_IERRVR */ /*! @{ */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit0_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit1_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit2_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit3_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit4_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit5_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit6_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit7_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit8_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit9_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit10_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit11_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit12_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit13_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit14_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit15_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit16_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit17_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit18_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit19_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit20_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit21_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit22_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit23_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit24_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit25_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit26_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit27_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit28_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit29_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit30_MASK) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI1_GICR1_IERRVR_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_IERRVR_valid_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_IERRVR_valid_bit31_MASK) /*! @} */ /*! @name GICR1_SGIDR - GICR1_SGIDR */ /*! @{ */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr0_SHIFT (0U) /*! nsacr0 - nsacr0 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr0_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr0_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp0_MASK (0x2U) #define NOC_GICRSGI1_GICR1_SGIDR_grp0_SHIFT (1U) /*! grp0 - grp0 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp0_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp0_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod0_MASK (0x4U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod0_SHIFT (2U) /*! grpmod0 - grpmod0 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod0_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod0_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED0_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED0_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr1_MASK (0x10U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr1_SHIFT (4U) /*! nsacr1 - nsacr1 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr1_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr1_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp1_MASK (0x20U) #define NOC_GICRSGI1_GICR1_SGIDR_grp1_SHIFT (5U) /*! grp1 - grp1 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp1_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp1_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod1_MASK (0x40U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod1_SHIFT (6U) /*! grpmod1 - grpmod1 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod1_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod1_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED1_MASK (0x80U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED1_SHIFT (7U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED1_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED1_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr2_MASK (0x100U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr2_SHIFT (8U) /*! nsacr2 - nsacr2 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr2_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr2_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp2_MASK (0x200U) #define NOC_GICRSGI1_GICR1_SGIDR_grp2_SHIFT (9U) /*! grp2 - grp2 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp2_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp2_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod2_MASK (0x400U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod2_SHIFT (10U) /*! grpmod2 - grpmod2 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod2_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod2_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED2_MASK (0x800U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED2_SHIFT (11U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED2_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED2_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr3_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr3_SHIFT (12U) /*! nsacr3 - nsacr3 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr3_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr3_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp3_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp3_SHIFT (13U) /*! grp3 - grp3 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp3_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp3_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod3_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod3_SHIFT (14U) /*! grpmod3 - grpmod3 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod3_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod3_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED3_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED3_SHIFT (15U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED3_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED3_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr4_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr4_SHIFT (16U) /*! nsacr4 - nsacr4 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr4_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr4_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp4_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp4_SHIFT (17U) /*! grp4 - grp4 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp4_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp4_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod4_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod4_SHIFT (18U) /*! grpmod4 - grpmod4 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod4_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod4_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED4_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED4_SHIFT (19U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED4_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED4_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr5_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr5_SHIFT (20U) /*! nsacr5 - nsacr5 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr5_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr5_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp5_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp5_SHIFT (21U) /*! grp5 - grp5 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp5_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp5_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod5_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod5_SHIFT (22U) /*! grpmod5 - grpmod5 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod5_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod5_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED5_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED5_SHIFT (23U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED5_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED5_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr6_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr6_SHIFT (24U) /*! nsacr6 - nsacr6 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr6_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr6_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp6_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp6_SHIFT (25U) /*! grp6 - grp6 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp6_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp6_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod6_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod6_SHIFT (26U) /*! grpmod6 - grpmod6 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod6_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod6_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED6_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED6_SHIFT (27U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED6_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED6_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr7_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr7_SHIFT (28U) /*! nsacr7 - nsacr7 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr7_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr7_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp7_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp7_SHIFT (29U) /*! grp7 - grp7 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp7_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp7_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod7_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod7_SHIFT (30U) /*! grpmod7 - grpmod7 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod7_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod7_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED7_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED7_SHIFT (31U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED7_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED7_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr8_MASK (0x100000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr8_SHIFT (32U) /*! nsacr8 - nsacr8 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr8_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr8_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp8_MASK (0x200000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp8_SHIFT (33U) /*! grp8 - grp8 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp8_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp8_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod8_MASK (0x400000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod8_SHIFT (34U) /*! grpmod8 - grpmod8 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod8_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod8_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED8_MASK (0x800000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED8_SHIFT (35U) /*! RESERVED8 - RESERVED8 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED8_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED8_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr9_MASK (0x1000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr9_SHIFT (36U) /*! nsacr9 - nsacr9 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr9_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr9_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp9_MASK (0x2000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp9_SHIFT (37U) /*! grp9 - grp9 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp9_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp9_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod9_MASK (0x4000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod9_SHIFT (38U) /*! grpmod9 - grpmod9 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod9_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod9_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED9_MASK (0x8000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED9_SHIFT (39U) /*! RESERVED9 - RESERVED9 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED9_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED9_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr10_MASK (0x10000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr10_SHIFT (40U) /*! nsacr10 - nsacr10 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr10_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr10_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp10_MASK (0x20000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp10_SHIFT (41U) /*! grp10 - grp10 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp10_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp10_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod10_MASK (0x40000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod10_SHIFT (42U) /*! grpmod10 - grpmod10 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod10_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod10_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED10_MASK (0x80000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED10_SHIFT (43U) /*! RESERVED10 - RESERVED10 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED10_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED10_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr11_MASK (0x100000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr11_SHIFT (44U) /*! nsacr11 - nsacr11 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr11_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr11_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp11_MASK (0x200000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp11_SHIFT (45U) /*! grp11 - grp11 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp11_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp11_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod11_MASK (0x400000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod11_SHIFT (46U) /*! grpmod11 - grpmod11 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod11_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod11_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED11_MASK (0x800000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED11_SHIFT (47U) /*! RESERVED11 - RESERVED11 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED11_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED11_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr12_MASK (0x1000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr12_SHIFT (48U) /*! nsacr12 - nsacr12 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr12_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr12_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp12_MASK (0x2000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp12_SHIFT (49U) /*! grp12 - grp12 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp12_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp12_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod12_MASK (0x4000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod12_SHIFT (50U) /*! grpmod12 - grpmod12 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod12_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod12_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED12_MASK (0x8000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED12_SHIFT (51U) /*! RESERVED12 - RESERVED12 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED12_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED12_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr13_MASK (0x10000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr13_SHIFT (52U) /*! nsacr13 - nsacr13 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr13_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr13_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp13_MASK (0x20000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp13_SHIFT (53U) /*! grp13 - grp13 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp13_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp13_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod13_MASK (0x40000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod13_SHIFT (54U) /*! grpmod13 - grpmod13 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod13_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod13_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED13_MASK (0x80000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED13_SHIFT (55U) /*! RESERVED13 - RESERVED13 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED13_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED13_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr14_MASK (0x100000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr14_SHIFT (56U) /*! nsacr14 - nsacr14 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr14_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr14_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp14_MASK (0x200000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp14_SHIFT (57U) /*! grp14 - grp14 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp14_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp14_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod14_MASK (0x400000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod14_SHIFT (58U) /*! grpmod14 - grpmod14 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod14_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod14_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED15_MASK (0x800000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED15_SHIFT (59U) /*! RESERVED15 - RESERVED15 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED15_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED15_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr15_MASK (0x1000000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_nsacr15_SHIFT (60U) /*! nsacr15 - nsacr15 */ #define NOC_GICRSGI1_GICR1_SGIDR_nsacr15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_nsacr15_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_nsacr15_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grp15_MASK (0x2000000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grp15_SHIFT (61U) /*! grp15 - grp15 */ #define NOC_GICRSGI1_GICR1_SGIDR_grp15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grp15_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grp15_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod15_MASK (0x4000000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_grpmod15_SHIFT (62U) /*! grpmod15 - grpmod15 */ #define NOC_GICRSGI1_GICR1_SGIDR_grpmod15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_grpmod15_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_grpmod15_MASK) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED16_MASK (0x8000000000000000U) #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED16_SHIFT (63U) /*! RESERVED16 - RESERVED16 */ #define NOC_GICRSGI1_GICR1_SGIDR_RESERVED16(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI1_GICR1_SGIDR_RESERVED16_SHIFT)) & NOC_GICRSGI1_GICR1_SGIDR_RESERVED16_MASK) /*! @} */ /*! @name GICR1_DPRIR - GICR1_DPRIR */ /*! @{ */ #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED3_MASK (0x7U) #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED3_SHIFT (0U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_DPRIR_RESERVED3_SHIFT)) & NOC_GICRSGI1_GICR1_DPRIR_RESERVED3_MASK) #define NOC_GICRSGI1_GICR1_DPRIR_gpr0_pri_MASK (0xF8U) #define NOC_GICRSGI1_GICR1_DPRIR_gpr0_pri_SHIFT (3U) /*! gpr0_pri - gpr0_pri */ #define NOC_GICRSGI1_GICR1_DPRIR_gpr0_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_DPRIR_gpr0_pri_SHIFT)) & NOC_GICRSGI1_GICR1_DPRIR_gpr0_pri_MASK) #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED2_MASK (0x700U) #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED2_SHIFT (8U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_DPRIR_RESERVED2_SHIFT)) & NOC_GICRSGI1_GICR1_DPRIR_RESERVED2_MASK) #define NOC_GICRSGI1_GICR1_DPRIR_gpr1ns_pri_MASK (0xF800U) #define NOC_GICRSGI1_GICR1_DPRIR_gpr1ns_pri_SHIFT (11U) /*! gpr1ns_pri - gpr1ns_pri */ #define NOC_GICRSGI1_GICR1_DPRIR_gpr1ns_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_DPRIR_gpr1ns_pri_SHIFT)) & NOC_GICRSGI1_GICR1_DPRIR_gpr1ns_pri_MASK) #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED1_MASK (0x70000U) #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED1_SHIFT (16U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_DPRIR_RESERVED1_SHIFT)) & NOC_GICRSGI1_GICR1_DPRIR_RESERVED1_MASK) #define NOC_GICRSGI1_GICR1_DPRIR_gpr1sec_pri_MASK (0xF80000U) #define NOC_GICRSGI1_GICR1_DPRIR_gpr1sec_pri_SHIFT (19U) /*! gpr1sec_pri - gpr1sec_pri */ #define NOC_GICRSGI1_GICR1_DPRIR_gpr1sec_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_DPRIR_gpr1sec_pri_SHIFT)) & NOC_GICRSGI1_GICR1_DPRIR_gpr1sec_pri_MASK) #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED0_MASK (0xFF000000U) #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI1_GICR1_DPRIR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_DPRIR_RESERVED0_SHIFT)) & NOC_GICRSGI1_GICR1_DPRIR_RESERVED0_MASK) /*! @} */ /*! @name GICR1_ICERRR0 - GICR1_ICERRR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit0_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit1_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit2_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit3_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit4_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit5_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit6_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit7_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit8_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit9_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit10_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit11_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit12_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit13_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit14_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit15_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit16_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit17_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit18_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit19_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit20_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit21_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit22_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit23_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit24_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit25_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit26_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit27_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit28_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit29_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit30_MASK) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI1_GICR1_ICERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ICERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ICERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR1_ISERRR0 - GICR1_ISERRR0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit0_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit1_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit2_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit3_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit4_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit5_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit6_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit7_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit8_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit9_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit10_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit11_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit12_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit13_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit14_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit15_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit16_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit17_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit18_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit19_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit20_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit21_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit22_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit23_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit24_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit25_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit26_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit27_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit28_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit29_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit30_MASK) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI1_GICR1_ISERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_ISERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI1_GICR1_ISERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR1_CFGID0 - GICR1_CFGID0 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_CFGID0_PPINumber_MASK (0x1FFU) #define NOC_GICRSGI1_GICR1_CFGID0_PPINumber_SHIFT (0U) /*! PPINumber - PPINumber */ #define NOC_GICRSGI1_GICR1_CFGID0_PPINumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID0_PPINumber_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID0_PPINumber_MASK) #define NOC_GICRSGI1_GICR1_CFGID0_ECCSupport_MASK (0x200U) #define NOC_GICRSGI1_GICR1_CFGID0_ECCSupport_SHIFT (9U) /*! ECCSupport - ECCSupport */ #define NOC_GICRSGI1_GICR1_CFGID0_ECCSupport(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID0_ECCSupport_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID0_ECCSupport_MASK) #define NOC_GICRSGI1_GICR1_CFGID0_RESERVED0_MASK (0xFFFFFC00U) #define NOC_GICRSGI1_GICR1_CFGID0_RESERVED0_SHIFT (10U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI1_GICR1_CFGID0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID0_RESERVED0_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID0_RESERVED0_MASK) /*! @} */ /*! @name GICR1_CFGID1 - GICR1_CFGID1 */ /*! @{ */ #define NOC_GICRSGI1_GICR1_CFGID1_RESERVED0_MASK (0xFU) #define NOC_GICRSGI1_GICR1_CFGID1_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI1_GICR1_CFGID1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID1_RESERVED0_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID1_RESERVED0_MASK) #define NOC_GICRSGI1_GICR1_CFGID1_NumCPUs_MASK (0xFF0U) #define NOC_GICRSGI1_GICR1_CFGID1_NumCPUs_SHIFT (4U) /*! NumCPUs - NumCPUs */ #define NOC_GICRSGI1_GICR1_CFGID1_NumCPUs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID1_NumCPUs_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID1_NumCPUs_MASK) #define NOC_GICRSGI1_GICR1_CFGID1_RESERVED1_MASK (0xF000U) #define NOC_GICRSGI1_GICR1_CFGID1_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI1_GICR1_CFGID1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID1_RESERVED1_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID1_RESERVED1_MASK) #define NOC_GICRSGI1_GICR1_CFGID1_PPIsPerProcessor_MASK (0xFF0000U) #define NOC_GICRSGI1_GICR1_CFGID1_PPIsPerProcessor_SHIFT (16U) /*! PPIsPerProcessor - PPIsPerProcessor */ #define NOC_GICRSGI1_GICR1_CFGID1_PPIsPerProcessor(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID1_PPIsPerProcessor_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID1_PPIsPerProcessor_MASK) #define NOC_GICRSGI1_GICR1_CFGID1_REVAND_MASK (0xF000000U) #define NOC_GICRSGI1_GICR1_CFGID1_REVAND_SHIFT (24U) /*! REVAND - REVAND */ #define NOC_GICRSGI1_GICR1_CFGID1_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID1_REVAND_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID1_REVAND_MASK) #define NOC_GICRSGI1_GICR1_CFGID1_Version_MASK (0xF0000000U) #define NOC_GICRSGI1_GICR1_CFGID1_Version_SHIFT (28U) /*! Version - Version */ #define NOC_GICRSGI1_GICR1_CFGID1_Version(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI1_GICR1_CFGID1_Version_SHIFT)) & NOC_GICRSGI1_GICR1_CFGID1_Version_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRSGI1_Register_Masks */ /* NOC_GICRSGI1 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRSGI1 base address */ #define NOC__GIC__GICRSGI1_BASE (0x48090000u) /** Peripheral NOC__GIC__GICRSGI1 base pointer */ #define NOC__GIC__GICRSGI1 ((NOC_GICRSGI1_Type *)NOC__GIC__GICRSGI1_BASE) /** Array initializer of NOC_GICRSGI1 peripheral base addresses */ #define NOC_GICRSGI1_BASE_ADDRS { NOC__GIC__GICRSGI1_BASE } /** Array initializer of NOC_GICRSGI1 peripheral base pointers */ #define NOC_GICRSGI1_BASE_PTRS { NOC__GIC__GICRSGI1 } /*! * @} */ /* end of group NOC_GICRSGI1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRSGI2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI2_Peripheral_Access_Layer NOC_GICRSGI2 Peripheral Access Layer * @{ */ /** NOC_GICRSGI2 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[128]; __IO uint32_t GICR2_IGROUPR0; /**< GICR2_IGROUPR0, offset: 0x80 */ uint8_t RESERVED_1[124]; __IO uint32_t GICR2_ISENABLER0; /**< GICR2_ISENABLER0, offset: 0x100 */ uint8_t RESERVED_2[124]; __IO uint32_t GICR2_ICENABLER0; /**< GICR2_ICENABLER0, offset: 0x180 */ uint8_t RESERVED_3[124]; __IO uint32_t GICR2_ISPENDR0; /**< GICR2_ISPENDR0, offset: 0x200 */ uint8_t RESERVED_4[124]; __IO uint32_t GICR2_ICPENDR0; /**< GICR2_ICPENDR0, offset: 0x280 */ uint8_t RESERVED_5[124]; __IO uint32_t GICR2_ISACTIVER0; /**< GICR2_ISACTIVER0, offset: 0x300 */ uint8_t RESERVED_6[124]; __IO uint32_t GICR2_ICACTIVER0; /**< GICR2_ICACTIVER0, offset: 0x380 */ uint8_t RESERVED_7[124]; __IO uint32_t GICR2_IPRIORITYR0; /**< GICR2_IPRIORITYR0, offset: 0x400 */ __IO uint32_t GICR2_IPRIORITYR1; /**< GICR2_IPRIORITYR1, offset: 0x404 */ __IO uint32_t GICR2_IPRIORITYR2; /**< GICR2_IPRIORITYR2, offset: 0x408 */ __IO uint32_t GICR2_IPRIORITYR3; /**< GICR2_IPRIORITYR3, offset: 0x40C */ __IO uint32_t GICR2_IPRIORITYR4; /**< GICR2_IPRIORITYR4, offset: 0x410 */ __IO uint32_t GICR2_IPRIORITYR5; /**< GICR2_IPRIORITYR5, offset: 0x414 */ __IO uint32_t GICR2_IPRIORITYR6; /**< GICR2_IPRIORITYR6, offset: 0x418 */ __IO uint32_t GICR2_IPRIORITYR7; /**< GICR2_IPRIORITYR7, offset: 0x41C */ uint8_t RESERVED_8[2016]; __I uint32_t GICR2_ICFGR0; /**< GICR2_ICFGR0, offset: 0xC00 */ __IO uint32_t GICR2_ICFGR1; /**< GICR2_ICFGR1, offset: 0xC04 */ uint8_t RESERVED_9[248]; __IO uint32_t GICR2_IGRPMODR0; /**< GICR2_IGRPMODR0, offset: 0xD00 */ uint8_t RESERVED_10[252]; __IO uint32_t GICR2_NSACR; /**< GICR2_NSACR, offset: 0xE00 */ uint8_t RESERVED_11[45564]; __I uint32_t GICR2_MISCSTATUSR; /**< GICR2_MISCSTATUSR, offset: 0xC000 */ uint8_t RESERVED_12[4]; __IO uint32_t GICR2_IERRVR; /**< GICR2_IERRVR, offset: 0xC008 */ uint8_t RESERVED_13[4]; __IO uint64_t GICR2_SGIDR; /**< GICR2_SGIDR, offset: 0xC010 */ __IO uint32_t GICR2_DPRIR; /**< GICR2_DPRIR, offset: 0xC018 */ uint8_t RESERVED_14[228]; __IO uint32_t GICR2_ICERRR0; /**< GICR2_ICERRR0, offset: 0xC100 */ uint8_t RESERVED_15[124]; __IO uint32_t GICR2_ISERRR0; /**< GICR2_ISERRR0, offset: 0xC180 */ uint8_t RESERVED_16[11900]; __I uint32_t GICR2_CFGID0; /**< GICR2_CFGID0, offset: 0xF000 */ __I uint32_t GICR2_CFGID1; /**< GICR2_CFGID1, offset: 0xF004 */ } NOC_GICRSGI2_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRSGI2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI2_Register_Masks NOC_GICRSGI2 Register Masks * @{ */ /*! @name GICR2_IGROUPR0 - GICR2_IGROUPR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit0_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit1_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit2_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit3_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit4_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit5_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit6_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit7_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit8_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit9_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit10_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit11_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit12_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit13_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit14_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit15_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit16_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit17_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit18_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit19_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit20_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit21_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit22_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit23_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit24_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit25_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit26_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit27_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit28_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit29_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit30_MASK) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_IGROUPR0_group_status_bit31_MASK) /*! @} */ /*! @name GICR2_ISENABLER0 - GICR2_ISENABLER0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit0_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit1_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit2_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit3_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit4_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit5_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit6_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit7_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit8_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit9_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit10_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit11_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit12_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit13_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit14_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit15_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit16_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit17_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit18_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit19_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit20_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit21_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit22_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit23_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit24_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit25_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit26_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit27_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit28_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit29_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit30_MASK) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ISENABLER0_set_enable_bit31_MASK) /*! @} */ /*! @name GICR2_ICENABLER0 - GICR2_ICENABLER0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit0_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit1_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit2_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit3_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit4_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit5_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit6_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit7_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit8_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit9_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit10_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit11_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit12_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit13_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit14_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit15_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit16_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit17_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit18_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit19_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit20_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit21_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit22_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit23_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit24_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit25_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit26_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit27_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit28_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit29_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit30_MASK) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ICENABLER0_clear_enable_bit31_MASK) /*! @} */ /*! @name GICR2_ISPENDR0 - GICR2_ISPENDR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit0_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit1_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit2_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit3_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit4_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit5_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit6_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit7_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit8_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit9_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit10_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit11_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit12_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit13_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit14_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit15_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit16_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit17_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit18_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit19_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit20_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit21_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit22_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit23_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit24_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit25_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit26_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit27_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit28_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit29_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit30_MASK) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ISPENDR0_set_pending_bit31_MASK) /*! @} */ /*! @name GICR2_ICPENDR0 - GICR2_ICPENDR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit0_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit1_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit2_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit3_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit4_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit5_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit6_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit7_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit8_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit9_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit10_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit11_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit12_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit13_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit14_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit15_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit16_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit17_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit18_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit19_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit20_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit21_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit22_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit23_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit24_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit25_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit26_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit27_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit28_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit29_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit30_MASK) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ICPENDR0_clear_pending_bit31_MASK) /*! @} */ /*! @name GICR2_ISACTIVER0 - GICR2_ISACTIVER0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit0_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit1_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit2_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit3_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit4_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit5_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit6_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit7_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit8_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit9_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit10_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit11_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit12_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit13_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit14_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit15_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit16_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit17_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit18_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit19_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit20_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit21_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit22_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit23_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit24_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit25_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit26_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit27_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit28_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit29_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit30_MASK) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ISACTIVER0_set_active_bit31_MASK) /*! @} */ /*! @name GICR2_ICACTIVER0 - GICR2_ICACTIVER0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit0_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit1_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit2_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit3_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit4_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit5_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit6_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit7_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit8_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit9_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit10_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit11_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit12_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit13_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit14_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit15_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit16_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit17_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit18_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit19_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit20_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit21_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit22_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit23_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit24_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit25_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit26_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit27_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit28_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit29_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit30_MASK) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ICACTIVER0_clear_active_bit31_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR0 - GICR2_IPRIORITYR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR0_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR0_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR0_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR0_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR0_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR0_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR0_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR0_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR0_offset3_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR1 - GICR2_IPRIORITYR1 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR1_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR1_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR1_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR1_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR1_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR1_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR1_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR1_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR1_offset3_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR2 - GICR2_IPRIORITYR2 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR2_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR2_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR2_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR2_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR2_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR2_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR2_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR2_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR2_offset3_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR3 - GICR2_IPRIORITYR3 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR3_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR3_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR3_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR3_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR3_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR3_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR3_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR3_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR3_offset3_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR4 - GICR2_IPRIORITYR4 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR4_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR4_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR4_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR4_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR4_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR4_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR4_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR4_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR4_offset3_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR5 - GICR2_IPRIORITYR5 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR5_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR5_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR5_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR5_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR5_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR5_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR5_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR5_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR5_offset3_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR6 - GICR2_IPRIORITYR6 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR6_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR6_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR6_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR6_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR6_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR6_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR6_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR6_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR6_offset3_MASK) /*! @} */ /*! @name GICR2_IPRIORITYR7 - GICR2_IPRIORITYR7 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset0_MASK (0xFFU) #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR7_offset0_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR7_offset0_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset1_MASK (0xFF00U) #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR7_offset1_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR7_offset1_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset2_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR7_offset2_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR7_offset2_MASK) #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset3_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI2_GICR2_IPRIORITYR7_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IPRIORITYR7_offset3_SHIFT)) & NOC_GICRSGI2_GICR2_IPRIORITYR7_offset3_MASK) /*! @} */ /*! @name GICR2_ICFGR0 - GICR2_ICFGR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config0_MASK (0x3U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config0_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config0_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config1_MASK (0xCU) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config1_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config1_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config2_MASK (0x30U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config2_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config2_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config3_MASK (0xC0U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config3_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config3_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config4_MASK (0x300U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config4_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config4_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config5_MASK (0xC00U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config5_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config5_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config6_MASK (0x3000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config6_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config6_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config7_MASK (0xC000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config7_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config7_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config8_MASK (0x30000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config8_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config8_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config9_MASK (0xC0000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config9_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config9_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config10_MASK (0x300000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config10_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config10_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config11_MASK (0xC00000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config11_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config11_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config12_MASK (0x3000000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config12_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config12_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config13_MASK (0xC000000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config13_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config13_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config14_MASK (0x30000000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config14_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config14_MASK) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI2_GICR2_ICFGR0_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR0_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR0_int_config15_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR0_int_config15_MASK) /*! @} */ /*! @name GICR2_ICFGR1 - GICR2_ICFGR1 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config0_MASK (0x3U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config0_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config0_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config1_MASK (0xCU) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config1_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config1_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config2_MASK (0x30U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config2_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config2_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config3_MASK (0xC0U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config3_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config3_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config4_MASK (0x300U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config4_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config4_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config5_MASK (0xC00U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config5_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config5_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config6_MASK (0x3000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config6_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config6_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config7_MASK (0xC000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config7_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config7_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config8_MASK (0x30000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config8_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config8_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config9_MASK (0xC0000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config9_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config9_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config10_MASK (0x300000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config10_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config10_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config11_MASK (0xC00000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config11_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config11_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config12_MASK (0x3000000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config12_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config12_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config13_MASK (0xC000000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config13_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config13_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config14_MASK (0x30000000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config14_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config14_MASK) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI2_GICR2_ICFGR1_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI2_GICR2_ICFGR1_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICFGR1_int_config15_SHIFT)) & NOC_GICRSGI2_GICR2_ICFGR1_int_config15_MASK) /*! @} */ /*! @name GICR2_IGRPMODR0 - GICR2_IGRPMODR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit0_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit1_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit2_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit3_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit4_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit5_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit6_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit7_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit8_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit9_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit10_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit11_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit12_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit13_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit14_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit15_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit16_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit17_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit18_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit19_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit20_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit21_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit22_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit23_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit24_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit25_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit26_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit27_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit28_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit29_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit30_MASK) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_IGRPMODR0_group_modifier_bit31_MASK) /*! @} */ /*! @name GICR2_NSACR - GICR2_NSACR */ /*! @{ */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access0_MASK (0x3U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access0_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access0_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access1_MASK (0xCU) #define NOC_GICRSGI2_GICR2_NSACR_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access1_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access1_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access2_MASK (0x30U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access2_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access2_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access3_MASK (0xC0U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access3_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access3_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access4_MASK (0x300U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access4_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access4_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access5_MASK (0xC00U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access5_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access5_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access6_MASK (0x3000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access6_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access6_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access7_MASK (0xC000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access7_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access7_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access8_MASK (0x30000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access8_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access8_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access9_MASK (0xC0000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access9_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access9_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access10_MASK (0x300000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access10_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access10_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access11_MASK (0xC00000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access11_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access11_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access12_MASK (0x3000000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access12_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access12_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access13_MASK (0xC000000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access13_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access13_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access14_MASK (0x30000000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access14_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access14_MASK) #define NOC_GICRSGI2_GICR2_NSACR_ns_access15_MASK (0xC0000000U) #define NOC_GICRSGI2_GICR2_NSACR_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICRSGI2_GICR2_NSACR_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_NSACR_ns_access15_SHIFT)) & NOC_GICRSGI2_GICR2_NSACR_ns_access15_MASK) /*! @} */ /*! @name GICR2_MISCSTATUSR - GICR2_MISCSTATUSR */ /*! @{ */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp0_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp0_MASK) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_ns_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_ns_MASK) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_s_MASK (0x4U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_s_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_EnableGrp1_s_MASK) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED0_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED0_MASK) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_access_type_MASK (0x10U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_access_type_SHIFT (4U) /*! access_type - access_type */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_access_type(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_access_type_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_access_type_MASK) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED1_MASK (0x3FFFFFE0U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED1_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_RESERVED1_MASK) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_wake_request_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_wake_request_SHIFT (30U) /*! wake_request - wake_request */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_wake_request(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_wake_request_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_wake_request_MASK) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_cpu_active_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_MISCSTATUSR_cpu_active_SHIFT (31U) /*! cpu_active - cpu_active */ #define NOC_GICRSGI2_GICR2_MISCSTATUSR_cpu_active(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_MISCSTATUSR_cpu_active_SHIFT)) & NOC_GICRSGI2_GICR2_MISCSTATUSR_cpu_active_MASK) /*! @} */ /*! @name GICR2_IERRVR - GICR2_IERRVR */ /*! @{ */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit0_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit1_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit2_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit3_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit4_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit5_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit6_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit7_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit8_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit9_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit10_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit11_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit12_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit13_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit14_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit15_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit16_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit17_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit18_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit19_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit20_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit21_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit22_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit23_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit24_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit25_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit26_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit27_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit28_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit29_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit30_MASK) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI2_GICR2_IERRVR_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_IERRVR_valid_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_IERRVR_valid_bit31_MASK) /*! @} */ /*! @name GICR2_SGIDR - GICR2_SGIDR */ /*! @{ */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr0_SHIFT (0U) /*! nsacr0 - nsacr0 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr0_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr0_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp0_MASK (0x2U) #define NOC_GICRSGI2_GICR2_SGIDR_grp0_SHIFT (1U) /*! grp0 - grp0 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp0_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp0_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod0_MASK (0x4U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod0_SHIFT (2U) /*! grpmod0 - grpmod0 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod0_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod0_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED0_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED0_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr1_MASK (0x10U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr1_SHIFT (4U) /*! nsacr1 - nsacr1 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr1_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr1_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp1_MASK (0x20U) #define NOC_GICRSGI2_GICR2_SGIDR_grp1_SHIFT (5U) /*! grp1 - grp1 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp1_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp1_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod1_MASK (0x40U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod1_SHIFT (6U) /*! grpmod1 - grpmod1 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod1_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod1_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED1_MASK (0x80U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED1_SHIFT (7U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED1_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED1_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr2_MASK (0x100U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr2_SHIFT (8U) /*! nsacr2 - nsacr2 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr2_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr2_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp2_MASK (0x200U) #define NOC_GICRSGI2_GICR2_SGIDR_grp2_SHIFT (9U) /*! grp2 - grp2 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp2_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp2_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod2_MASK (0x400U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod2_SHIFT (10U) /*! grpmod2 - grpmod2 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod2_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod2_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED2_MASK (0x800U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED2_SHIFT (11U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED2_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED2_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr3_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr3_SHIFT (12U) /*! nsacr3 - nsacr3 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr3_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr3_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp3_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp3_SHIFT (13U) /*! grp3 - grp3 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp3_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp3_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod3_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod3_SHIFT (14U) /*! grpmod3 - grpmod3 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod3_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod3_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED3_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED3_SHIFT (15U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED3_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED3_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr4_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr4_SHIFT (16U) /*! nsacr4 - nsacr4 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr4_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr4_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp4_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp4_SHIFT (17U) /*! grp4 - grp4 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp4_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp4_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod4_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod4_SHIFT (18U) /*! grpmod4 - grpmod4 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod4_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod4_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED4_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED4_SHIFT (19U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED4_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED4_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr5_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr5_SHIFT (20U) /*! nsacr5 - nsacr5 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr5_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr5_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp5_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp5_SHIFT (21U) /*! grp5 - grp5 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp5_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp5_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod5_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod5_SHIFT (22U) /*! grpmod5 - grpmod5 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod5_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod5_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED5_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED5_SHIFT (23U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED5_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED5_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr6_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr6_SHIFT (24U) /*! nsacr6 - nsacr6 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr6_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr6_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp6_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp6_SHIFT (25U) /*! grp6 - grp6 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp6_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp6_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod6_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod6_SHIFT (26U) /*! grpmod6 - grpmod6 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod6_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod6_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED6_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED6_SHIFT (27U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED6_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED6_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr7_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr7_SHIFT (28U) /*! nsacr7 - nsacr7 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr7_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr7_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp7_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp7_SHIFT (29U) /*! grp7 - grp7 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp7_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp7_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod7_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod7_SHIFT (30U) /*! grpmod7 - grpmod7 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod7_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod7_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED7_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED7_SHIFT (31U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED7_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED7_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr8_MASK (0x100000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr8_SHIFT (32U) /*! nsacr8 - nsacr8 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr8_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr8_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp8_MASK (0x200000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp8_SHIFT (33U) /*! grp8 - grp8 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp8_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp8_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod8_MASK (0x400000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod8_SHIFT (34U) /*! grpmod8 - grpmod8 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod8_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod8_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED8_MASK (0x800000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED8_SHIFT (35U) /*! RESERVED8 - RESERVED8 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED8_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED8_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr9_MASK (0x1000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr9_SHIFT (36U) /*! nsacr9 - nsacr9 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr9_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr9_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp9_MASK (0x2000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp9_SHIFT (37U) /*! grp9 - grp9 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp9_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp9_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod9_MASK (0x4000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod9_SHIFT (38U) /*! grpmod9 - grpmod9 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod9_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod9_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED9_MASK (0x8000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED9_SHIFT (39U) /*! RESERVED9 - RESERVED9 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED9_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED9_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr10_MASK (0x10000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr10_SHIFT (40U) /*! nsacr10 - nsacr10 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr10_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr10_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp10_MASK (0x20000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp10_SHIFT (41U) /*! grp10 - grp10 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp10_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp10_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod10_MASK (0x40000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod10_SHIFT (42U) /*! grpmod10 - grpmod10 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod10_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod10_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED10_MASK (0x80000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED10_SHIFT (43U) /*! RESERVED10 - RESERVED10 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED10_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED10_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr11_MASK (0x100000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr11_SHIFT (44U) /*! nsacr11 - nsacr11 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr11_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr11_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp11_MASK (0x200000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp11_SHIFT (45U) /*! grp11 - grp11 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp11_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp11_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod11_MASK (0x400000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod11_SHIFT (46U) /*! grpmod11 - grpmod11 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod11_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod11_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED11_MASK (0x800000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED11_SHIFT (47U) /*! RESERVED11 - RESERVED11 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED11_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED11_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr12_MASK (0x1000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr12_SHIFT (48U) /*! nsacr12 - nsacr12 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr12_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr12_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp12_MASK (0x2000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp12_SHIFT (49U) /*! grp12 - grp12 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp12_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp12_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod12_MASK (0x4000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod12_SHIFT (50U) /*! grpmod12 - grpmod12 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod12_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod12_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED12_MASK (0x8000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED12_SHIFT (51U) /*! RESERVED12 - RESERVED12 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED12_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED12_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr13_MASK (0x10000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr13_SHIFT (52U) /*! nsacr13 - nsacr13 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr13_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr13_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp13_MASK (0x20000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp13_SHIFT (53U) /*! grp13 - grp13 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp13_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp13_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod13_MASK (0x40000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod13_SHIFT (54U) /*! grpmod13 - grpmod13 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod13_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod13_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED13_MASK (0x80000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED13_SHIFT (55U) /*! RESERVED13 - RESERVED13 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED13_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED13_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr14_MASK (0x100000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr14_SHIFT (56U) /*! nsacr14 - nsacr14 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr14_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr14_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp14_MASK (0x200000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp14_SHIFT (57U) /*! grp14 - grp14 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp14_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp14_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod14_MASK (0x400000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod14_SHIFT (58U) /*! grpmod14 - grpmod14 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod14_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod14_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED15_MASK (0x800000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED15_SHIFT (59U) /*! RESERVED15 - RESERVED15 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED15_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED15_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr15_MASK (0x1000000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_nsacr15_SHIFT (60U) /*! nsacr15 - nsacr15 */ #define NOC_GICRSGI2_GICR2_SGIDR_nsacr15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_nsacr15_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_nsacr15_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grp15_MASK (0x2000000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grp15_SHIFT (61U) /*! grp15 - grp15 */ #define NOC_GICRSGI2_GICR2_SGIDR_grp15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grp15_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grp15_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod15_MASK (0x4000000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_grpmod15_SHIFT (62U) /*! grpmod15 - grpmod15 */ #define NOC_GICRSGI2_GICR2_SGIDR_grpmod15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_grpmod15_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_grpmod15_MASK) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED16_MASK (0x8000000000000000U) #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED16_SHIFT (63U) /*! RESERVED16 - RESERVED16 */ #define NOC_GICRSGI2_GICR2_SGIDR_RESERVED16(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI2_GICR2_SGIDR_RESERVED16_SHIFT)) & NOC_GICRSGI2_GICR2_SGIDR_RESERVED16_MASK) /*! @} */ /*! @name GICR2_DPRIR - GICR2_DPRIR */ /*! @{ */ #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED3_MASK (0x7U) #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED3_SHIFT (0U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_DPRIR_RESERVED3_SHIFT)) & NOC_GICRSGI2_GICR2_DPRIR_RESERVED3_MASK) #define NOC_GICRSGI2_GICR2_DPRIR_gpr0_pri_MASK (0xF8U) #define NOC_GICRSGI2_GICR2_DPRIR_gpr0_pri_SHIFT (3U) /*! gpr0_pri - gpr0_pri */ #define NOC_GICRSGI2_GICR2_DPRIR_gpr0_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_DPRIR_gpr0_pri_SHIFT)) & NOC_GICRSGI2_GICR2_DPRIR_gpr0_pri_MASK) #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED2_MASK (0x700U) #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED2_SHIFT (8U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_DPRIR_RESERVED2_SHIFT)) & NOC_GICRSGI2_GICR2_DPRIR_RESERVED2_MASK) #define NOC_GICRSGI2_GICR2_DPRIR_gpr1ns_pri_MASK (0xF800U) #define NOC_GICRSGI2_GICR2_DPRIR_gpr1ns_pri_SHIFT (11U) /*! gpr1ns_pri - gpr1ns_pri */ #define NOC_GICRSGI2_GICR2_DPRIR_gpr1ns_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_DPRIR_gpr1ns_pri_SHIFT)) & NOC_GICRSGI2_GICR2_DPRIR_gpr1ns_pri_MASK) #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED1_MASK (0x70000U) #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED1_SHIFT (16U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_DPRIR_RESERVED1_SHIFT)) & NOC_GICRSGI2_GICR2_DPRIR_RESERVED1_MASK) #define NOC_GICRSGI2_GICR2_DPRIR_gpr1sec_pri_MASK (0xF80000U) #define NOC_GICRSGI2_GICR2_DPRIR_gpr1sec_pri_SHIFT (19U) /*! gpr1sec_pri - gpr1sec_pri */ #define NOC_GICRSGI2_GICR2_DPRIR_gpr1sec_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_DPRIR_gpr1sec_pri_SHIFT)) & NOC_GICRSGI2_GICR2_DPRIR_gpr1sec_pri_MASK) #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED0_MASK (0xFF000000U) #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI2_GICR2_DPRIR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_DPRIR_RESERVED0_SHIFT)) & NOC_GICRSGI2_GICR2_DPRIR_RESERVED0_MASK) /*! @} */ /*! @name GICR2_ICERRR0 - GICR2_ICERRR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit0_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit1_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit2_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit3_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit4_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit5_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit6_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit7_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit8_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit9_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit10_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit11_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit12_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit13_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit14_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit15_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit16_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit17_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit18_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit19_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit20_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit21_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit22_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit23_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit24_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit25_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit26_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit27_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit28_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit29_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit30_MASK) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI2_GICR2_ICERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ICERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ICERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR2_ISERRR0 - GICR2_ISERRR0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit0_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit1_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit2_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit3_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit4_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit5_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit6_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit7_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit8_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit9_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit10_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit11_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit12_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit13_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit14_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit15_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit16_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit17_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit18_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit19_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit20_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit21_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit22_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit23_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit24_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit25_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit26_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit27_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit28_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit29_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit30_MASK) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI2_GICR2_ISERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_ISERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI2_GICR2_ISERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR2_CFGID0 - GICR2_CFGID0 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_CFGID0_PPINumber_MASK (0x1FFU) #define NOC_GICRSGI2_GICR2_CFGID0_PPINumber_SHIFT (0U) /*! PPINumber - PPINumber */ #define NOC_GICRSGI2_GICR2_CFGID0_PPINumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID0_PPINumber_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID0_PPINumber_MASK) #define NOC_GICRSGI2_GICR2_CFGID0_ECCSupport_MASK (0x200U) #define NOC_GICRSGI2_GICR2_CFGID0_ECCSupport_SHIFT (9U) /*! ECCSupport - ECCSupport */ #define NOC_GICRSGI2_GICR2_CFGID0_ECCSupport(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID0_ECCSupport_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID0_ECCSupport_MASK) #define NOC_GICRSGI2_GICR2_CFGID0_RESERVED0_MASK (0xFFFFFC00U) #define NOC_GICRSGI2_GICR2_CFGID0_RESERVED0_SHIFT (10U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI2_GICR2_CFGID0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID0_RESERVED0_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID0_RESERVED0_MASK) /*! @} */ /*! @name GICR2_CFGID1 - GICR2_CFGID1 */ /*! @{ */ #define NOC_GICRSGI2_GICR2_CFGID1_RESERVED0_MASK (0xFU) #define NOC_GICRSGI2_GICR2_CFGID1_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI2_GICR2_CFGID1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID1_RESERVED0_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID1_RESERVED0_MASK) #define NOC_GICRSGI2_GICR2_CFGID1_NumCPUs_MASK (0xFF0U) #define NOC_GICRSGI2_GICR2_CFGID1_NumCPUs_SHIFT (4U) /*! NumCPUs - NumCPUs */ #define NOC_GICRSGI2_GICR2_CFGID1_NumCPUs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID1_NumCPUs_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID1_NumCPUs_MASK) #define NOC_GICRSGI2_GICR2_CFGID1_RESERVED1_MASK (0xF000U) #define NOC_GICRSGI2_GICR2_CFGID1_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI2_GICR2_CFGID1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID1_RESERVED1_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID1_RESERVED1_MASK) #define NOC_GICRSGI2_GICR2_CFGID1_PPIsPerProcessor_MASK (0xFF0000U) #define NOC_GICRSGI2_GICR2_CFGID1_PPIsPerProcessor_SHIFT (16U) /*! PPIsPerProcessor - PPIsPerProcessor */ #define NOC_GICRSGI2_GICR2_CFGID1_PPIsPerProcessor(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID1_PPIsPerProcessor_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID1_PPIsPerProcessor_MASK) #define NOC_GICRSGI2_GICR2_CFGID1_REVAND_MASK (0xF000000U) #define NOC_GICRSGI2_GICR2_CFGID1_REVAND_SHIFT (24U) /*! REVAND - REVAND */ #define NOC_GICRSGI2_GICR2_CFGID1_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID1_REVAND_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID1_REVAND_MASK) #define NOC_GICRSGI2_GICR2_CFGID1_Version_MASK (0xF0000000U) #define NOC_GICRSGI2_GICR2_CFGID1_Version_SHIFT (28U) /*! Version - Version */ #define NOC_GICRSGI2_GICR2_CFGID1_Version(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI2_GICR2_CFGID1_Version_SHIFT)) & NOC_GICRSGI2_GICR2_CFGID1_Version_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRSGI2_Register_Masks */ /* NOC_GICRSGI2 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRSGI2 base address */ #define NOC__GIC__GICRSGI2_BASE (0x480B0000u) /** Peripheral NOC__GIC__GICRSGI2 base pointer */ #define NOC__GIC__GICRSGI2 ((NOC_GICRSGI2_Type *)NOC__GIC__GICRSGI2_BASE) /** Array initializer of NOC_GICRSGI2 peripheral base addresses */ #define NOC_GICRSGI2_BASE_ADDRS { NOC__GIC__GICRSGI2_BASE } /** Array initializer of NOC_GICRSGI2 peripheral base pointers */ #define NOC_GICRSGI2_BASE_PTRS { NOC__GIC__GICRSGI2 } /*! * @} */ /* end of group NOC_GICRSGI2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRSGI3 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI3_Peripheral_Access_Layer NOC_GICRSGI3 Peripheral Access Layer * @{ */ /** NOC_GICRSGI3 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[128]; __IO uint32_t GICR3_IGROUPR0; /**< GICR3_IGROUPR0, offset: 0x80 */ uint8_t RESERVED_1[124]; __IO uint32_t GICR3_ISENABLER0; /**< GICR3_ISENABLER0, offset: 0x100 */ uint8_t RESERVED_2[124]; __IO uint32_t GICR3_ICENABLER0; /**< GICR3_ICENABLER0, offset: 0x180 */ uint8_t RESERVED_3[124]; __IO uint32_t GICR3_ISPENDR0; /**< GICR3_ISPENDR0, offset: 0x200 */ uint8_t RESERVED_4[124]; __IO uint32_t GICR3_ICPENDR0; /**< GICR3_ICPENDR0, offset: 0x280 */ uint8_t RESERVED_5[124]; __IO uint32_t GICR3_ISACTIVER0; /**< GICR3_ISACTIVER0, offset: 0x300 */ uint8_t RESERVED_6[124]; __IO uint32_t GICR3_ICACTIVER0; /**< GICR3_ICACTIVER0, offset: 0x380 */ uint8_t RESERVED_7[124]; __IO uint32_t GICR3_IPRIORITYR0; /**< GICR3_IPRIORITYR0, offset: 0x400 */ __IO uint32_t GICR3_IPRIORITYR1; /**< GICR3_IPRIORITYR1, offset: 0x404 */ __IO uint32_t GICR3_IPRIORITYR2; /**< GICR3_IPRIORITYR2, offset: 0x408 */ __IO uint32_t GICR3_IPRIORITYR3; /**< GICR3_IPRIORITYR3, offset: 0x40C */ __IO uint32_t GICR3_IPRIORITYR4; /**< GICR3_IPRIORITYR4, offset: 0x410 */ __IO uint32_t GICR3_IPRIORITYR5; /**< GICR3_IPRIORITYR5, offset: 0x414 */ __IO uint32_t GICR3_IPRIORITYR6; /**< GICR3_IPRIORITYR6, offset: 0x418 */ __IO uint32_t GICR3_IPRIORITYR7; /**< GICR3_IPRIORITYR7, offset: 0x41C */ uint8_t RESERVED_8[2016]; __I uint32_t GICR3_ICFGR0; /**< GICR3_ICFGR0, offset: 0xC00 */ __IO uint32_t GICR3_ICFGR1; /**< GICR3_ICFGR1, offset: 0xC04 */ uint8_t RESERVED_9[248]; __IO uint32_t GICR3_IGRPMODR0; /**< GICR3_IGRPMODR0, offset: 0xD00 */ uint8_t RESERVED_10[252]; __IO uint32_t GICR3_NSACR; /**< GICR3_NSACR, offset: 0xE00 */ uint8_t RESERVED_11[45564]; __I uint32_t GICR3_MISCSTATUSR; /**< GICR3_MISCSTATUSR, offset: 0xC000 */ uint8_t RESERVED_12[4]; __IO uint32_t GICR3_IERRVR; /**< GICR3_IERRVR, offset: 0xC008 */ uint8_t RESERVED_13[4]; __IO uint64_t GICR3_SGIDR; /**< GICR3_SGIDR, offset: 0xC010 */ __IO uint32_t GICR3_DPRIR; /**< GICR3_DPRIR, offset: 0xC018 */ uint8_t RESERVED_14[228]; __IO uint32_t GICR3_ICERRR0; /**< GICR3_ICERRR0, offset: 0xC100 */ uint8_t RESERVED_15[124]; __IO uint32_t GICR3_ISERRR0; /**< GICR3_ISERRR0, offset: 0xC180 */ uint8_t RESERVED_16[11900]; __I uint32_t GICR3_CFGID0; /**< GICR3_CFGID0, offset: 0xF000 */ __I uint32_t GICR3_CFGID1; /**< GICR3_CFGID1, offset: 0xF004 */ } NOC_GICRSGI3_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRSGI3 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI3_Register_Masks NOC_GICRSGI3 Register Masks * @{ */ /*! @name GICR3_IGROUPR0 - GICR3_IGROUPR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit0_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit1_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit2_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit3_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit4_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit5_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit6_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit7_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit8_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit9_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit10_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit11_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit12_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit13_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit14_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit15_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit16_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit17_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit18_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit19_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit20_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit21_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit22_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit23_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit24_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit25_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit26_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit27_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit28_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit29_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit30_MASK) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_IGROUPR0_group_status_bit31_MASK) /*! @} */ /*! @name GICR3_ISENABLER0 - GICR3_ISENABLER0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit0_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit1_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit2_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit3_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit4_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit5_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit6_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit7_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit8_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit9_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit10_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit11_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit12_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit13_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit14_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit15_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit16_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit17_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit18_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit19_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit20_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit21_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit22_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit23_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit24_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit25_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit26_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit27_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit28_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit29_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit30_MASK) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ISENABLER0_set_enable_bit31_MASK) /*! @} */ /*! @name GICR3_ICENABLER0 - GICR3_ICENABLER0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit0_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit1_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit2_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit3_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit4_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit5_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit6_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit7_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit8_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit9_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit10_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit11_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit12_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit13_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit14_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit15_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit16_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit17_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit18_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit19_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit20_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit21_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit22_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit23_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit24_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit25_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit26_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit27_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit28_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit29_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit30_MASK) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ICENABLER0_clear_enable_bit31_MASK) /*! @} */ /*! @name GICR3_ISPENDR0 - GICR3_ISPENDR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit0_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit1_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit2_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit3_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit4_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit5_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit6_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit7_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit8_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit9_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit10_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit11_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit12_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit13_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit14_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit15_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit16_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit17_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit18_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit19_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit20_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit21_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit22_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit23_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit24_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit25_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit26_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit27_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit28_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit29_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit30_MASK) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ISPENDR0_set_pending_bit31_MASK) /*! @} */ /*! @name GICR3_ICPENDR0 - GICR3_ICPENDR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit0_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit1_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit2_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit3_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit4_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit5_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit6_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit7_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit8_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit9_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit10_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit11_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit12_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit13_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit14_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit15_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit16_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit17_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit18_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit19_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit20_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit21_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit22_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit23_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit24_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit25_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit26_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit27_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit28_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit29_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit30_MASK) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ICPENDR0_clear_pending_bit31_MASK) /*! @} */ /*! @name GICR3_ISACTIVER0 - GICR3_ISACTIVER0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit0_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit1_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit2_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit3_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit4_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit5_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit6_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit7_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit8_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit9_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit10_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit11_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit12_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit13_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit14_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit15_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit16_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit17_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit18_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit19_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit20_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit21_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit22_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit23_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit24_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit25_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit26_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit27_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit28_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit29_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit30_MASK) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ISACTIVER0_set_active_bit31_MASK) /*! @} */ /*! @name GICR3_ICACTIVER0 - GICR3_ICACTIVER0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit0_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit1_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit2_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit3_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit4_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit5_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit6_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit7_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit8_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit9_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit10_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit11_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit12_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit13_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit14_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit15_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit16_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit17_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit18_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit19_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit20_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit21_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit22_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit23_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit24_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit25_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit26_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit27_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit28_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit29_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit30_MASK) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ICACTIVER0_clear_active_bit31_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR0 - GICR3_IPRIORITYR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR0_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR0_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR0_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR0_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR0_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR0_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR0_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR0_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR0_offset3_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR1 - GICR3_IPRIORITYR1 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR1_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR1_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR1_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR1_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR1_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR1_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR1_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR1_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR1_offset3_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR2 - GICR3_IPRIORITYR2 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR2_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR2_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR2_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR2_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR2_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR2_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR2_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR2_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR2_offset3_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR3 - GICR3_IPRIORITYR3 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR3_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR3_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR3_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR3_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR3_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR3_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR3_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR3_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR3_offset3_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR4 - GICR3_IPRIORITYR4 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR4_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR4_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR4_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR4_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR4_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR4_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR4_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR4_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR4_offset3_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR5 - GICR3_IPRIORITYR5 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR5_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR5_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR5_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR5_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR5_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR5_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR5_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR5_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR5_offset3_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR6 - GICR3_IPRIORITYR6 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR6_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR6_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR6_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR6_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR6_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR6_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR6_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR6_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR6_offset3_MASK) /*! @} */ /*! @name GICR3_IPRIORITYR7 - GICR3_IPRIORITYR7 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset0_MASK (0xFFU) #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR7_offset0_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR7_offset0_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset1_MASK (0xFF00U) #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR7_offset1_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR7_offset1_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset2_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR7_offset2_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR7_offset2_MASK) #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset3_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI3_GICR3_IPRIORITYR7_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IPRIORITYR7_offset3_SHIFT)) & NOC_GICRSGI3_GICR3_IPRIORITYR7_offset3_MASK) /*! @} */ /*! @name GICR3_ICFGR0 - GICR3_ICFGR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config0_MASK (0x3U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config0_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config0_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config1_MASK (0xCU) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config1_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config1_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config2_MASK (0x30U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config2_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config2_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config3_MASK (0xC0U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config3_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config3_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config4_MASK (0x300U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config4_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config4_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config5_MASK (0xC00U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config5_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config5_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config6_MASK (0x3000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config6_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config6_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config7_MASK (0xC000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config7_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config7_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config8_MASK (0x30000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config8_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config8_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config9_MASK (0xC0000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config9_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config9_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config10_MASK (0x300000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config10_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config10_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config11_MASK (0xC00000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config11_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config11_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config12_MASK (0x3000000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config12_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config12_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config13_MASK (0xC000000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config13_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config13_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config14_MASK (0x30000000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config14_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config14_MASK) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI3_GICR3_ICFGR0_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR0_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR0_int_config15_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR0_int_config15_MASK) /*! @} */ /*! @name GICR3_ICFGR1 - GICR3_ICFGR1 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config0_MASK (0x3U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config0_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config0_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config1_MASK (0xCU) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config1_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config1_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config2_MASK (0x30U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config2_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config2_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config3_MASK (0xC0U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config3_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config3_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config4_MASK (0x300U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config4_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config4_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config5_MASK (0xC00U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config5_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config5_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config6_MASK (0x3000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config6_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config6_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config7_MASK (0xC000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config7_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config7_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config8_MASK (0x30000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config8_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config8_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config9_MASK (0xC0000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config9_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config9_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config10_MASK (0x300000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config10_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config10_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config11_MASK (0xC00000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config11_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config11_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config12_MASK (0x3000000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config12_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config12_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config13_MASK (0xC000000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config13_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config13_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config14_MASK (0x30000000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config14_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config14_MASK) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI3_GICR3_ICFGR1_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI3_GICR3_ICFGR1_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICFGR1_int_config15_SHIFT)) & NOC_GICRSGI3_GICR3_ICFGR1_int_config15_MASK) /*! @} */ /*! @name GICR3_IGRPMODR0 - GICR3_IGRPMODR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit0_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit1_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit2_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit3_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit4_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit5_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit6_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit7_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit8_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit9_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit10_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit11_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit12_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit13_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit14_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit15_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit16_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit17_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit18_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit19_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit20_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit21_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit22_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit23_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit24_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit25_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit26_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit27_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit28_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit29_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit30_MASK) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_IGRPMODR0_group_modifier_bit31_MASK) /*! @} */ /*! @name GICR3_NSACR - GICR3_NSACR */ /*! @{ */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access0_MASK (0x3U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access0_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access0_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access1_MASK (0xCU) #define NOC_GICRSGI3_GICR3_NSACR_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access1_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access1_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access2_MASK (0x30U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access2_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access2_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access3_MASK (0xC0U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access3_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access3_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access4_MASK (0x300U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access4_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access4_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access5_MASK (0xC00U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access5_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access5_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access6_MASK (0x3000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access6_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access6_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access7_MASK (0xC000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access7_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access7_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access8_MASK (0x30000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access8_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access8_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access9_MASK (0xC0000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access9_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access9_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access10_MASK (0x300000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access10_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access10_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access11_MASK (0xC00000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access11_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access11_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access12_MASK (0x3000000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access12_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access12_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access13_MASK (0xC000000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access13_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access13_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access14_MASK (0x30000000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access14_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access14_MASK) #define NOC_GICRSGI3_GICR3_NSACR_ns_access15_MASK (0xC0000000U) #define NOC_GICRSGI3_GICR3_NSACR_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICRSGI3_GICR3_NSACR_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_NSACR_ns_access15_SHIFT)) & NOC_GICRSGI3_GICR3_NSACR_ns_access15_MASK) /*! @} */ /*! @name GICR3_MISCSTATUSR - GICR3_MISCSTATUSR */ /*! @{ */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp0_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp0_MASK) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_ns_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_ns_MASK) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_s_MASK (0x4U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_s_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_EnableGrp1_s_MASK) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED0_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED0_MASK) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_access_type_MASK (0x10U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_access_type_SHIFT (4U) /*! access_type - access_type */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_access_type(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_access_type_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_access_type_MASK) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED1_MASK (0x3FFFFFE0U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED1_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_RESERVED1_MASK) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_wake_request_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_wake_request_SHIFT (30U) /*! wake_request - wake_request */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_wake_request(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_wake_request_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_wake_request_MASK) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_cpu_active_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_MISCSTATUSR_cpu_active_SHIFT (31U) /*! cpu_active - cpu_active */ #define NOC_GICRSGI3_GICR3_MISCSTATUSR_cpu_active(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_MISCSTATUSR_cpu_active_SHIFT)) & NOC_GICRSGI3_GICR3_MISCSTATUSR_cpu_active_MASK) /*! @} */ /*! @name GICR3_IERRVR - GICR3_IERRVR */ /*! @{ */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit0_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit1_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit2_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit3_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit4_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit5_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit6_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit7_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit8_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit9_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit10_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit11_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit12_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit13_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit14_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit15_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit16_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit17_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit18_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit19_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit20_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit21_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit22_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit23_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit24_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit25_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit26_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit27_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit28_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit29_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit30_MASK) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI3_GICR3_IERRVR_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_IERRVR_valid_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_IERRVR_valid_bit31_MASK) /*! @} */ /*! @name GICR3_SGIDR - GICR3_SGIDR */ /*! @{ */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr0_SHIFT (0U) /*! nsacr0 - nsacr0 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr0_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr0_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp0_MASK (0x2U) #define NOC_GICRSGI3_GICR3_SGIDR_grp0_SHIFT (1U) /*! grp0 - grp0 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp0_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp0_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod0_MASK (0x4U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod0_SHIFT (2U) /*! grpmod0 - grpmod0 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod0_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod0_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED0_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED0_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr1_MASK (0x10U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr1_SHIFT (4U) /*! nsacr1 - nsacr1 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr1_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr1_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp1_MASK (0x20U) #define NOC_GICRSGI3_GICR3_SGIDR_grp1_SHIFT (5U) /*! grp1 - grp1 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp1_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp1_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod1_MASK (0x40U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod1_SHIFT (6U) /*! grpmod1 - grpmod1 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod1_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod1_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED1_MASK (0x80U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED1_SHIFT (7U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED1_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED1_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr2_MASK (0x100U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr2_SHIFT (8U) /*! nsacr2 - nsacr2 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr2_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr2_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp2_MASK (0x200U) #define NOC_GICRSGI3_GICR3_SGIDR_grp2_SHIFT (9U) /*! grp2 - grp2 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp2_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp2_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod2_MASK (0x400U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod2_SHIFT (10U) /*! grpmod2 - grpmod2 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod2_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod2_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED2_MASK (0x800U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED2_SHIFT (11U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED2_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED2_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr3_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr3_SHIFT (12U) /*! nsacr3 - nsacr3 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr3_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr3_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp3_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp3_SHIFT (13U) /*! grp3 - grp3 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp3_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp3_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod3_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod3_SHIFT (14U) /*! grpmod3 - grpmod3 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod3_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod3_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED3_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED3_SHIFT (15U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED3_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED3_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr4_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr4_SHIFT (16U) /*! nsacr4 - nsacr4 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr4_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr4_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp4_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp4_SHIFT (17U) /*! grp4 - grp4 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp4_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp4_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod4_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod4_SHIFT (18U) /*! grpmod4 - grpmod4 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod4_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod4_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED4_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED4_SHIFT (19U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED4_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED4_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr5_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr5_SHIFT (20U) /*! nsacr5 - nsacr5 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr5_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr5_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp5_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp5_SHIFT (21U) /*! grp5 - grp5 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp5_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp5_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod5_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod5_SHIFT (22U) /*! grpmod5 - grpmod5 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod5_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod5_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED5_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED5_SHIFT (23U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED5_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED5_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr6_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr6_SHIFT (24U) /*! nsacr6 - nsacr6 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr6_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr6_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp6_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp6_SHIFT (25U) /*! grp6 - grp6 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp6_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp6_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod6_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod6_SHIFT (26U) /*! grpmod6 - grpmod6 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod6_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod6_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED6_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED6_SHIFT (27U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED6_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED6_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr7_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr7_SHIFT (28U) /*! nsacr7 - nsacr7 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr7_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr7_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp7_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp7_SHIFT (29U) /*! grp7 - grp7 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp7_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp7_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod7_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod7_SHIFT (30U) /*! grpmod7 - grpmod7 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod7_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod7_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED7_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED7_SHIFT (31U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED7_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED7_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr8_MASK (0x100000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr8_SHIFT (32U) /*! nsacr8 - nsacr8 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr8_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr8_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp8_MASK (0x200000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp8_SHIFT (33U) /*! grp8 - grp8 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp8_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp8_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod8_MASK (0x400000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod8_SHIFT (34U) /*! grpmod8 - grpmod8 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod8_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod8_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED8_MASK (0x800000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED8_SHIFT (35U) /*! RESERVED8 - RESERVED8 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED8_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED8_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr9_MASK (0x1000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr9_SHIFT (36U) /*! nsacr9 - nsacr9 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr9_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr9_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp9_MASK (0x2000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp9_SHIFT (37U) /*! grp9 - grp9 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp9_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp9_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod9_MASK (0x4000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod9_SHIFT (38U) /*! grpmod9 - grpmod9 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod9_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod9_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED9_MASK (0x8000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED9_SHIFT (39U) /*! RESERVED9 - RESERVED9 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED9_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED9_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr10_MASK (0x10000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr10_SHIFT (40U) /*! nsacr10 - nsacr10 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr10_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr10_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp10_MASK (0x20000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp10_SHIFT (41U) /*! grp10 - grp10 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp10_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp10_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod10_MASK (0x40000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod10_SHIFT (42U) /*! grpmod10 - grpmod10 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod10_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod10_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED10_MASK (0x80000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED10_SHIFT (43U) /*! RESERVED10 - RESERVED10 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED10_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED10_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr11_MASK (0x100000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr11_SHIFT (44U) /*! nsacr11 - nsacr11 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr11_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr11_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp11_MASK (0x200000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp11_SHIFT (45U) /*! grp11 - grp11 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp11_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp11_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod11_MASK (0x400000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod11_SHIFT (46U) /*! grpmod11 - grpmod11 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod11_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod11_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED11_MASK (0x800000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED11_SHIFT (47U) /*! RESERVED11 - RESERVED11 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED11_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED11_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr12_MASK (0x1000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr12_SHIFT (48U) /*! nsacr12 - nsacr12 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr12_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr12_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp12_MASK (0x2000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp12_SHIFT (49U) /*! grp12 - grp12 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp12_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp12_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod12_MASK (0x4000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod12_SHIFT (50U) /*! grpmod12 - grpmod12 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod12_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod12_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED12_MASK (0x8000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED12_SHIFT (51U) /*! RESERVED12 - RESERVED12 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED12_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED12_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr13_MASK (0x10000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr13_SHIFT (52U) /*! nsacr13 - nsacr13 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr13_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr13_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp13_MASK (0x20000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp13_SHIFT (53U) /*! grp13 - grp13 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp13_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp13_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod13_MASK (0x40000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod13_SHIFT (54U) /*! grpmod13 - grpmod13 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod13_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod13_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED13_MASK (0x80000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED13_SHIFT (55U) /*! RESERVED13 - RESERVED13 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED13_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED13_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr14_MASK (0x100000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr14_SHIFT (56U) /*! nsacr14 - nsacr14 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr14_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr14_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp14_MASK (0x200000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp14_SHIFT (57U) /*! grp14 - grp14 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp14_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp14_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod14_MASK (0x400000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod14_SHIFT (58U) /*! grpmod14 - grpmod14 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod14_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod14_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED15_MASK (0x800000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED15_SHIFT (59U) /*! RESERVED15 - RESERVED15 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED15_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED15_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr15_MASK (0x1000000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_nsacr15_SHIFT (60U) /*! nsacr15 - nsacr15 */ #define NOC_GICRSGI3_GICR3_SGIDR_nsacr15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_nsacr15_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_nsacr15_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grp15_MASK (0x2000000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grp15_SHIFT (61U) /*! grp15 - grp15 */ #define NOC_GICRSGI3_GICR3_SGIDR_grp15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grp15_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grp15_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod15_MASK (0x4000000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_grpmod15_SHIFT (62U) /*! grpmod15 - grpmod15 */ #define NOC_GICRSGI3_GICR3_SGIDR_grpmod15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_grpmod15_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_grpmod15_MASK) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED16_MASK (0x8000000000000000U) #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED16_SHIFT (63U) /*! RESERVED16 - RESERVED16 */ #define NOC_GICRSGI3_GICR3_SGIDR_RESERVED16(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI3_GICR3_SGIDR_RESERVED16_SHIFT)) & NOC_GICRSGI3_GICR3_SGIDR_RESERVED16_MASK) /*! @} */ /*! @name GICR3_DPRIR - GICR3_DPRIR */ /*! @{ */ #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED3_MASK (0x7U) #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED3_SHIFT (0U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_DPRIR_RESERVED3_SHIFT)) & NOC_GICRSGI3_GICR3_DPRIR_RESERVED3_MASK) #define NOC_GICRSGI3_GICR3_DPRIR_gpr0_pri_MASK (0xF8U) #define NOC_GICRSGI3_GICR3_DPRIR_gpr0_pri_SHIFT (3U) /*! gpr0_pri - gpr0_pri */ #define NOC_GICRSGI3_GICR3_DPRIR_gpr0_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_DPRIR_gpr0_pri_SHIFT)) & NOC_GICRSGI3_GICR3_DPRIR_gpr0_pri_MASK) #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED2_MASK (0x700U) #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED2_SHIFT (8U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_DPRIR_RESERVED2_SHIFT)) & NOC_GICRSGI3_GICR3_DPRIR_RESERVED2_MASK) #define NOC_GICRSGI3_GICR3_DPRIR_gpr1ns_pri_MASK (0xF800U) #define NOC_GICRSGI3_GICR3_DPRIR_gpr1ns_pri_SHIFT (11U) /*! gpr1ns_pri - gpr1ns_pri */ #define NOC_GICRSGI3_GICR3_DPRIR_gpr1ns_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_DPRIR_gpr1ns_pri_SHIFT)) & NOC_GICRSGI3_GICR3_DPRIR_gpr1ns_pri_MASK) #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED1_MASK (0x70000U) #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED1_SHIFT (16U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_DPRIR_RESERVED1_SHIFT)) & NOC_GICRSGI3_GICR3_DPRIR_RESERVED1_MASK) #define NOC_GICRSGI3_GICR3_DPRIR_gpr1sec_pri_MASK (0xF80000U) #define NOC_GICRSGI3_GICR3_DPRIR_gpr1sec_pri_SHIFT (19U) /*! gpr1sec_pri - gpr1sec_pri */ #define NOC_GICRSGI3_GICR3_DPRIR_gpr1sec_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_DPRIR_gpr1sec_pri_SHIFT)) & NOC_GICRSGI3_GICR3_DPRIR_gpr1sec_pri_MASK) #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED0_MASK (0xFF000000U) #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI3_GICR3_DPRIR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_DPRIR_RESERVED0_SHIFT)) & NOC_GICRSGI3_GICR3_DPRIR_RESERVED0_MASK) /*! @} */ /*! @name GICR3_ICERRR0 - GICR3_ICERRR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit0_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit1_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit2_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit3_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit4_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit5_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit6_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit7_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit8_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit9_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit10_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit11_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit12_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit13_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit14_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit15_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit16_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit17_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit18_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit19_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit20_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit21_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit22_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit23_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit24_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit25_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit26_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit27_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit28_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit29_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit30_MASK) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI3_GICR3_ICERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ICERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ICERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR3_ISERRR0 - GICR3_ISERRR0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit0_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit1_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit2_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit3_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit4_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit5_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit6_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit7_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit8_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit9_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit10_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit11_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit12_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit13_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit14_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit15_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit16_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit17_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit18_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit19_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit20_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit21_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit22_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit23_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit24_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit25_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit26_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit27_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit28_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit29_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit30_MASK) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI3_GICR3_ISERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_ISERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI3_GICR3_ISERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR3_CFGID0 - GICR3_CFGID0 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_CFGID0_PPINumber_MASK (0x1FFU) #define NOC_GICRSGI3_GICR3_CFGID0_PPINumber_SHIFT (0U) /*! PPINumber - PPINumber */ #define NOC_GICRSGI3_GICR3_CFGID0_PPINumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID0_PPINumber_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID0_PPINumber_MASK) #define NOC_GICRSGI3_GICR3_CFGID0_ECCSupport_MASK (0x200U) #define NOC_GICRSGI3_GICR3_CFGID0_ECCSupport_SHIFT (9U) /*! ECCSupport - ECCSupport */ #define NOC_GICRSGI3_GICR3_CFGID0_ECCSupport(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID0_ECCSupport_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID0_ECCSupport_MASK) #define NOC_GICRSGI3_GICR3_CFGID0_RESERVED0_MASK (0xFFFFFC00U) #define NOC_GICRSGI3_GICR3_CFGID0_RESERVED0_SHIFT (10U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI3_GICR3_CFGID0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID0_RESERVED0_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID0_RESERVED0_MASK) /*! @} */ /*! @name GICR3_CFGID1 - GICR3_CFGID1 */ /*! @{ */ #define NOC_GICRSGI3_GICR3_CFGID1_RESERVED0_MASK (0xFU) #define NOC_GICRSGI3_GICR3_CFGID1_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI3_GICR3_CFGID1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID1_RESERVED0_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID1_RESERVED0_MASK) #define NOC_GICRSGI3_GICR3_CFGID1_NumCPUs_MASK (0xFF0U) #define NOC_GICRSGI3_GICR3_CFGID1_NumCPUs_SHIFT (4U) /*! NumCPUs - NumCPUs */ #define NOC_GICRSGI3_GICR3_CFGID1_NumCPUs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID1_NumCPUs_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID1_NumCPUs_MASK) #define NOC_GICRSGI3_GICR3_CFGID1_RESERVED1_MASK (0xF000U) #define NOC_GICRSGI3_GICR3_CFGID1_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI3_GICR3_CFGID1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID1_RESERVED1_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID1_RESERVED1_MASK) #define NOC_GICRSGI3_GICR3_CFGID1_PPIsPerProcessor_MASK (0xFF0000U) #define NOC_GICRSGI3_GICR3_CFGID1_PPIsPerProcessor_SHIFT (16U) /*! PPIsPerProcessor - PPIsPerProcessor */ #define NOC_GICRSGI3_GICR3_CFGID1_PPIsPerProcessor(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID1_PPIsPerProcessor_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID1_PPIsPerProcessor_MASK) #define NOC_GICRSGI3_GICR3_CFGID1_REVAND_MASK (0xF000000U) #define NOC_GICRSGI3_GICR3_CFGID1_REVAND_SHIFT (24U) /*! REVAND - REVAND */ #define NOC_GICRSGI3_GICR3_CFGID1_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID1_REVAND_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID1_REVAND_MASK) #define NOC_GICRSGI3_GICR3_CFGID1_Version_MASK (0xF0000000U) #define NOC_GICRSGI3_GICR3_CFGID1_Version_SHIFT (28U) /*! Version - Version */ #define NOC_GICRSGI3_GICR3_CFGID1_Version(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI3_GICR3_CFGID1_Version_SHIFT)) & NOC_GICRSGI3_GICR3_CFGID1_Version_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRSGI3_Register_Masks */ /* NOC_GICRSGI3 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRSGI3 base address */ #define NOC__GIC__GICRSGI3_BASE (0x480D0000u) /** Peripheral NOC__GIC__GICRSGI3 base pointer */ #define NOC__GIC__GICRSGI3 ((NOC_GICRSGI3_Type *)NOC__GIC__GICRSGI3_BASE) /** Array initializer of NOC_GICRSGI3 peripheral base addresses */ #define NOC_GICRSGI3_BASE_ADDRS { NOC__GIC__GICRSGI3_BASE } /** Array initializer of NOC_GICRSGI3 peripheral base pointers */ #define NOC_GICRSGI3_BASE_PTRS { NOC__GIC__GICRSGI3 } /*! * @} */ /* end of group NOC_GICRSGI3_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRSGI4 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI4_Peripheral_Access_Layer NOC_GICRSGI4 Peripheral Access Layer * @{ */ /** NOC_GICRSGI4 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[128]; __IO uint32_t GICR4_IGROUPR0; /**< GICR4_IGROUPR0, offset: 0x80 */ uint8_t RESERVED_1[124]; __IO uint32_t GICR4_ISENABLER0; /**< GICR4_ISENABLER0, offset: 0x100 */ uint8_t RESERVED_2[124]; __IO uint32_t GICR4_ICENABLER0; /**< GICR4_ICENABLER0, offset: 0x180 */ uint8_t RESERVED_3[124]; __IO uint32_t GICR4_ISPENDR0; /**< GICR4_ISPENDR0, offset: 0x200 */ uint8_t RESERVED_4[124]; __IO uint32_t GICR4_ICPENDR0; /**< GICR4_ICPENDR0, offset: 0x280 */ uint8_t RESERVED_5[124]; __IO uint32_t GICR4_ISACTIVER0; /**< GICR4_ISACTIVER0, offset: 0x300 */ uint8_t RESERVED_6[124]; __IO uint32_t GICR4_ICACTIVER0; /**< GICR4_ICACTIVER0, offset: 0x380 */ uint8_t RESERVED_7[124]; __IO uint32_t GICR4_IPRIORITYR0; /**< GICR4_IPRIORITYR0, offset: 0x400 */ __IO uint32_t GICR4_IPRIORITYR1; /**< GICR4_IPRIORITYR1, offset: 0x404 */ __IO uint32_t GICR4_IPRIORITYR2; /**< GICR4_IPRIORITYR2, offset: 0x408 */ __IO uint32_t GICR4_IPRIORITYR3; /**< GICR4_IPRIORITYR3, offset: 0x40C */ __IO uint32_t GICR4_IPRIORITYR4; /**< GICR4_IPRIORITYR4, offset: 0x410 */ __IO uint32_t GICR4_IPRIORITYR5; /**< GICR4_IPRIORITYR5, offset: 0x414 */ __IO uint32_t GICR4_IPRIORITYR6; /**< GICR4_IPRIORITYR6, offset: 0x418 */ __IO uint32_t GICR4_IPRIORITYR7; /**< GICR4_IPRIORITYR7, offset: 0x41C */ uint8_t RESERVED_8[2016]; __I uint32_t GICR4_ICFGR0; /**< GICR4_ICFGR0, offset: 0xC00 */ __IO uint32_t GICR4_ICFGR1; /**< GICR4_ICFGR1, offset: 0xC04 */ uint8_t RESERVED_9[248]; __IO uint32_t GICR4_IGRPMODR0; /**< GICR4_IGRPMODR0, offset: 0xD00 */ uint8_t RESERVED_10[252]; __IO uint32_t GICR4_NSACR; /**< GICR4_NSACR, offset: 0xE00 */ uint8_t RESERVED_11[45564]; __I uint32_t GICR4_MISCSTATUSR; /**< GICR4_MISCSTATUSR, offset: 0xC000 */ uint8_t RESERVED_12[4]; __IO uint32_t GICR4_IERRVR; /**< GICR4_IERRVR, offset: 0xC008 */ uint8_t RESERVED_13[4]; __IO uint64_t GICR4_SGIDR; /**< GICR4_SGIDR, offset: 0xC010 */ __IO uint32_t GICR4_DPRIR; /**< GICR4_DPRIR, offset: 0xC018 */ uint8_t RESERVED_14[228]; __IO uint32_t GICR4_ICERRR0; /**< GICR4_ICERRR0, offset: 0xC100 */ uint8_t RESERVED_15[124]; __IO uint32_t GICR4_ISERRR0; /**< GICR4_ISERRR0, offset: 0xC180 */ uint8_t RESERVED_16[11900]; __I uint32_t GICR4_CFGID0; /**< GICR4_CFGID0, offset: 0xF000 */ __I uint32_t GICR4_CFGID1; /**< GICR4_CFGID1, offset: 0xF004 */ } NOC_GICRSGI4_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRSGI4 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI4_Register_Masks NOC_GICRSGI4 Register Masks * @{ */ /*! @name GICR4_IGROUPR0 - GICR4_IGROUPR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit0_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit1_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit2_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit3_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit4_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit5_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit6_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit7_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit8_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit9_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit10_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit11_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit12_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit13_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit14_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit15_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit16_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit17_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit18_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit19_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit20_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit21_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit22_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit23_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit24_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit25_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit26_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit27_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit28_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit29_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit30_MASK) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_IGROUPR0_group_status_bit31_MASK) /*! @} */ /*! @name GICR4_ISENABLER0 - GICR4_ISENABLER0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit0_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit1_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit2_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit3_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit4_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit5_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit6_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit7_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit8_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit9_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit10_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit11_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit12_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit13_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit14_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit15_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit16_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit17_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit18_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit19_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit20_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit21_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit22_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit23_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit24_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit25_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit26_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit27_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit28_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit29_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit30_MASK) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ISENABLER0_set_enable_bit31_MASK) /*! @} */ /*! @name GICR4_ICENABLER0 - GICR4_ICENABLER0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit0_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit1_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit2_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit3_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit4_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit5_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit6_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit7_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit8_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit9_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit10_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit11_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit12_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit13_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit14_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit15_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit16_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit17_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit18_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit19_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit20_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit21_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit22_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit23_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit24_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit25_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit26_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit27_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit28_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit29_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit30_MASK) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ICENABLER0_clear_enable_bit31_MASK) /*! @} */ /*! @name GICR4_ISPENDR0 - GICR4_ISPENDR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit0_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit1_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit2_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit3_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit4_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit5_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit6_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit7_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit8_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit9_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit10_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit11_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit12_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit13_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit14_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit15_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit16_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit17_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit18_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit19_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit20_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit21_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit22_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit23_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit24_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit25_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit26_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit27_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit28_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit29_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit30_MASK) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ISPENDR0_set_pending_bit31_MASK) /*! @} */ /*! @name GICR4_ICPENDR0 - GICR4_ICPENDR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit0_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit1_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit2_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit3_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit4_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit5_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit6_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit7_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit8_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit9_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit10_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit11_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit12_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit13_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit14_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit15_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit16_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit17_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit18_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit19_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit20_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit21_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit22_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit23_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit24_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit25_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit26_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit27_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit28_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit29_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit30_MASK) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ICPENDR0_clear_pending_bit31_MASK) /*! @} */ /*! @name GICR4_ISACTIVER0 - GICR4_ISACTIVER0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit0_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit1_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit2_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit3_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit4_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit5_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit6_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit7_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit8_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit9_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit10_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit11_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit12_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit13_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit14_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit15_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit16_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit17_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit18_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit19_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit20_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit21_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit22_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit23_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit24_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit25_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit26_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit27_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit28_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit29_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit30_MASK) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ISACTIVER0_set_active_bit31_MASK) /*! @} */ /*! @name GICR4_ICACTIVER0 - GICR4_ICACTIVER0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit0_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit1_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit2_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit3_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit4_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit5_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit6_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit7_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit8_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit9_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit10_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit11_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit12_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit13_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit14_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit15_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit16_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit17_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit18_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit19_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit20_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit21_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit22_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit23_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit24_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit25_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit26_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit27_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit28_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit29_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit30_MASK) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ICACTIVER0_clear_active_bit31_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR0 - GICR4_IPRIORITYR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR0_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR0_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR0_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR0_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR0_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR0_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR0_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR0_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR0_offset3_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR1 - GICR4_IPRIORITYR1 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR1_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR1_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR1_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR1_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR1_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR1_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR1_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR1_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR1_offset3_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR2 - GICR4_IPRIORITYR2 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR2_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR2_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR2_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR2_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR2_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR2_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR2_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR2_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR2_offset3_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR3 - GICR4_IPRIORITYR3 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR3_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR3_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR3_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR3_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR3_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR3_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR3_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR3_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR3_offset3_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR4 - GICR4_IPRIORITYR4 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR4_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR4_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR4_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR4_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR4_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR4_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR4_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR4_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR4_offset3_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR5 - GICR4_IPRIORITYR5 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR5_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR5_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR5_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR5_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR5_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR5_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR5_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR5_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR5_offset3_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR6 - GICR4_IPRIORITYR6 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR6_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR6_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR6_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR6_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR6_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR6_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR6_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR6_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR6_offset3_MASK) /*! @} */ /*! @name GICR4_IPRIORITYR7 - GICR4_IPRIORITYR7 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset0_MASK (0xFFU) #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR7_offset0_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR7_offset0_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset1_MASK (0xFF00U) #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR7_offset1_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR7_offset1_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset2_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR7_offset2_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR7_offset2_MASK) #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset3_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI4_GICR4_IPRIORITYR7_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IPRIORITYR7_offset3_SHIFT)) & NOC_GICRSGI4_GICR4_IPRIORITYR7_offset3_MASK) /*! @} */ /*! @name GICR4_ICFGR0 - GICR4_ICFGR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config0_MASK (0x3U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config0_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config0_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config1_MASK (0xCU) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config1_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config1_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config2_MASK (0x30U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config2_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config2_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config3_MASK (0xC0U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config3_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config3_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config4_MASK (0x300U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config4_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config4_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config5_MASK (0xC00U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config5_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config5_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config6_MASK (0x3000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config6_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config6_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config7_MASK (0xC000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config7_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config7_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config8_MASK (0x30000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config8_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config8_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config9_MASK (0xC0000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config9_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config9_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config10_MASK (0x300000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config10_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config10_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config11_MASK (0xC00000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config11_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config11_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config12_MASK (0x3000000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config12_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config12_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config13_MASK (0xC000000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config13_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config13_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config14_MASK (0x30000000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config14_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config14_MASK) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI4_GICR4_ICFGR0_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR0_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR0_int_config15_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR0_int_config15_MASK) /*! @} */ /*! @name GICR4_ICFGR1 - GICR4_ICFGR1 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config0_MASK (0x3U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config0_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config0_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config1_MASK (0xCU) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config1_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config1_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config2_MASK (0x30U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config2_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config2_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config3_MASK (0xC0U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config3_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config3_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config4_MASK (0x300U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config4_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config4_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config5_MASK (0xC00U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config5_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config5_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config6_MASK (0x3000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config6_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config6_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config7_MASK (0xC000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config7_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config7_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config8_MASK (0x30000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config8_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config8_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config9_MASK (0xC0000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config9_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config9_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config10_MASK (0x300000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config10_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config10_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config11_MASK (0xC00000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config11_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config11_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config12_MASK (0x3000000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config12_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config12_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config13_MASK (0xC000000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config13_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config13_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config14_MASK (0x30000000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config14_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config14_MASK) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI4_GICR4_ICFGR1_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI4_GICR4_ICFGR1_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICFGR1_int_config15_SHIFT)) & NOC_GICRSGI4_GICR4_ICFGR1_int_config15_MASK) /*! @} */ /*! @name GICR4_IGRPMODR0 - GICR4_IGRPMODR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit0_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit1_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit2_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit3_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit4_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit5_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit6_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit7_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit8_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit9_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit10_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit11_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit12_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit13_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit14_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit15_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit16_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit17_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit18_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit19_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit20_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit21_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit22_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit23_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit24_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit25_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit26_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit27_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit28_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit29_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit30_MASK) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_IGRPMODR0_group_modifier_bit31_MASK) /*! @} */ /*! @name GICR4_NSACR - GICR4_NSACR */ /*! @{ */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access0_MASK (0x3U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access0_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access0_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access1_MASK (0xCU) #define NOC_GICRSGI4_GICR4_NSACR_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access1_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access1_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access2_MASK (0x30U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access2_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access2_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access3_MASK (0xC0U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access3_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access3_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access4_MASK (0x300U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access4_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access4_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access5_MASK (0xC00U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access5_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access5_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access6_MASK (0x3000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access6_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access6_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access7_MASK (0xC000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access7_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access7_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access8_MASK (0x30000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access8_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access8_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access9_MASK (0xC0000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access9_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access9_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access10_MASK (0x300000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access10_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access10_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access11_MASK (0xC00000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access11_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access11_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access12_MASK (0x3000000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access12_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access12_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access13_MASK (0xC000000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access13_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access13_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access14_MASK (0x30000000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access14_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access14_MASK) #define NOC_GICRSGI4_GICR4_NSACR_ns_access15_MASK (0xC0000000U) #define NOC_GICRSGI4_GICR4_NSACR_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICRSGI4_GICR4_NSACR_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_NSACR_ns_access15_SHIFT)) & NOC_GICRSGI4_GICR4_NSACR_ns_access15_MASK) /*! @} */ /*! @name GICR4_MISCSTATUSR - GICR4_MISCSTATUSR */ /*! @{ */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp0_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp0_MASK) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_ns_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_ns_MASK) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_s_MASK (0x4U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_s_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_EnableGrp1_s_MASK) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED0_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED0_MASK) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_access_type_MASK (0x10U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_access_type_SHIFT (4U) /*! access_type - access_type */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_access_type(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_access_type_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_access_type_MASK) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED1_MASK (0x3FFFFFE0U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED1_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_RESERVED1_MASK) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_wake_request_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_wake_request_SHIFT (30U) /*! wake_request - wake_request */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_wake_request(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_wake_request_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_wake_request_MASK) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_cpu_active_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_MISCSTATUSR_cpu_active_SHIFT (31U) /*! cpu_active - cpu_active */ #define NOC_GICRSGI4_GICR4_MISCSTATUSR_cpu_active(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_MISCSTATUSR_cpu_active_SHIFT)) & NOC_GICRSGI4_GICR4_MISCSTATUSR_cpu_active_MASK) /*! @} */ /*! @name GICR4_IERRVR - GICR4_IERRVR */ /*! @{ */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit0_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit1_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit2_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit3_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit4_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit5_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit6_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit7_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit8_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit9_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit10_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit11_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit12_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit13_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit14_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit15_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit16_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit17_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit18_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit19_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit20_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit21_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit22_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit23_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit24_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit25_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit26_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit27_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit28_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit29_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit30_MASK) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI4_GICR4_IERRVR_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_IERRVR_valid_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_IERRVR_valid_bit31_MASK) /*! @} */ /*! @name GICR4_SGIDR - GICR4_SGIDR */ /*! @{ */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr0_SHIFT (0U) /*! nsacr0 - nsacr0 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr0_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr0_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp0_MASK (0x2U) #define NOC_GICRSGI4_GICR4_SGIDR_grp0_SHIFT (1U) /*! grp0 - grp0 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp0_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp0_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod0_MASK (0x4U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod0_SHIFT (2U) /*! grpmod0 - grpmod0 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod0_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod0_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED0_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED0_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr1_MASK (0x10U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr1_SHIFT (4U) /*! nsacr1 - nsacr1 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr1_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr1_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp1_MASK (0x20U) #define NOC_GICRSGI4_GICR4_SGIDR_grp1_SHIFT (5U) /*! grp1 - grp1 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp1_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp1_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod1_MASK (0x40U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod1_SHIFT (6U) /*! grpmod1 - grpmod1 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod1_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod1_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED1_MASK (0x80U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED1_SHIFT (7U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED1_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED1_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr2_MASK (0x100U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr2_SHIFT (8U) /*! nsacr2 - nsacr2 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr2_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr2_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp2_MASK (0x200U) #define NOC_GICRSGI4_GICR4_SGIDR_grp2_SHIFT (9U) /*! grp2 - grp2 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp2_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp2_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod2_MASK (0x400U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod2_SHIFT (10U) /*! grpmod2 - grpmod2 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod2_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod2_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED2_MASK (0x800U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED2_SHIFT (11U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED2_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED2_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr3_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr3_SHIFT (12U) /*! nsacr3 - nsacr3 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr3_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr3_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp3_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp3_SHIFT (13U) /*! grp3 - grp3 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp3_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp3_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod3_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod3_SHIFT (14U) /*! grpmod3 - grpmod3 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod3_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod3_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED3_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED3_SHIFT (15U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED3_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED3_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr4_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr4_SHIFT (16U) /*! nsacr4 - nsacr4 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr4_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr4_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp4_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp4_SHIFT (17U) /*! grp4 - grp4 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp4_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp4_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod4_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod4_SHIFT (18U) /*! grpmod4 - grpmod4 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod4_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod4_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED4_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED4_SHIFT (19U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED4_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED4_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr5_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr5_SHIFT (20U) /*! nsacr5 - nsacr5 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr5_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr5_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp5_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp5_SHIFT (21U) /*! grp5 - grp5 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp5_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp5_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod5_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod5_SHIFT (22U) /*! grpmod5 - grpmod5 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod5_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod5_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED5_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED5_SHIFT (23U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED5_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED5_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr6_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr6_SHIFT (24U) /*! nsacr6 - nsacr6 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr6_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr6_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp6_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp6_SHIFT (25U) /*! grp6 - grp6 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp6_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp6_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod6_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod6_SHIFT (26U) /*! grpmod6 - grpmod6 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod6_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod6_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED6_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED6_SHIFT (27U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED6_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED6_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr7_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr7_SHIFT (28U) /*! nsacr7 - nsacr7 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr7_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr7_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp7_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp7_SHIFT (29U) /*! grp7 - grp7 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp7_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp7_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod7_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod7_SHIFT (30U) /*! grpmod7 - grpmod7 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod7_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod7_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED7_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED7_SHIFT (31U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED7_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED7_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr8_MASK (0x100000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr8_SHIFT (32U) /*! nsacr8 - nsacr8 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr8_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr8_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp8_MASK (0x200000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp8_SHIFT (33U) /*! grp8 - grp8 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp8_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp8_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod8_MASK (0x400000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod8_SHIFT (34U) /*! grpmod8 - grpmod8 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod8_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod8_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED8_MASK (0x800000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED8_SHIFT (35U) /*! RESERVED8 - RESERVED8 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED8_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED8_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr9_MASK (0x1000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr9_SHIFT (36U) /*! nsacr9 - nsacr9 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr9_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr9_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp9_MASK (0x2000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp9_SHIFT (37U) /*! grp9 - grp9 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp9_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp9_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod9_MASK (0x4000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod9_SHIFT (38U) /*! grpmod9 - grpmod9 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod9_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod9_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED9_MASK (0x8000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED9_SHIFT (39U) /*! RESERVED9 - RESERVED9 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED9_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED9_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr10_MASK (0x10000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr10_SHIFT (40U) /*! nsacr10 - nsacr10 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr10_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr10_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp10_MASK (0x20000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp10_SHIFT (41U) /*! grp10 - grp10 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp10_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp10_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod10_MASK (0x40000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod10_SHIFT (42U) /*! grpmod10 - grpmod10 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod10_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod10_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED10_MASK (0x80000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED10_SHIFT (43U) /*! RESERVED10 - RESERVED10 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED10_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED10_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr11_MASK (0x100000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr11_SHIFT (44U) /*! nsacr11 - nsacr11 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr11_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr11_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp11_MASK (0x200000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp11_SHIFT (45U) /*! grp11 - grp11 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp11_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp11_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod11_MASK (0x400000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod11_SHIFT (46U) /*! grpmod11 - grpmod11 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod11_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod11_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED11_MASK (0x800000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED11_SHIFT (47U) /*! RESERVED11 - RESERVED11 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED11_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED11_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr12_MASK (0x1000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr12_SHIFT (48U) /*! nsacr12 - nsacr12 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr12_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr12_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp12_MASK (0x2000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp12_SHIFT (49U) /*! grp12 - grp12 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp12_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp12_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod12_MASK (0x4000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod12_SHIFT (50U) /*! grpmod12 - grpmod12 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod12_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod12_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED12_MASK (0x8000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED12_SHIFT (51U) /*! RESERVED12 - RESERVED12 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED12_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED12_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr13_MASK (0x10000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr13_SHIFT (52U) /*! nsacr13 - nsacr13 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr13_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr13_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp13_MASK (0x20000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp13_SHIFT (53U) /*! grp13 - grp13 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp13_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp13_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod13_MASK (0x40000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod13_SHIFT (54U) /*! grpmod13 - grpmod13 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod13_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod13_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED13_MASK (0x80000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED13_SHIFT (55U) /*! RESERVED13 - RESERVED13 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED13_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED13_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr14_MASK (0x100000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr14_SHIFT (56U) /*! nsacr14 - nsacr14 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr14_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr14_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp14_MASK (0x200000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp14_SHIFT (57U) /*! grp14 - grp14 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp14_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp14_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod14_MASK (0x400000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod14_SHIFT (58U) /*! grpmod14 - grpmod14 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod14_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod14_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED15_MASK (0x800000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED15_SHIFT (59U) /*! RESERVED15 - RESERVED15 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED15_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED15_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr15_MASK (0x1000000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_nsacr15_SHIFT (60U) /*! nsacr15 - nsacr15 */ #define NOC_GICRSGI4_GICR4_SGIDR_nsacr15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_nsacr15_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_nsacr15_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grp15_MASK (0x2000000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grp15_SHIFT (61U) /*! grp15 - grp15 */ #define NOC_GICRSGI4_GICR4_SGIDR_grp15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grp15_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grp15_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod15_MASK (0x4000000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_grpmod15_SHIFT (62U) /*! grpmod15 - grpmod15 */ #define NOC_GICRSGI4_GICR4_SGIDR_grpmod15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_grpmod15_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_grpmod15_MASK) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED16_MASK (0x8000000000000000U) #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED16_SHIFT (63U) /*! RESERVED16 - RESERVED16 */ #define NOC_GICRSGI4_GICR4_SGIDR_RESERVED16(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI4_GICR4_SGIDR_RESERVED16_SHIFT)) & NOC_GICRSGI4_GICR4_SGIDR_RESERVED16_MASK) /*! @} */ /*! @name GICR4_DPRIR - GICR4_DPRIR */ /*! @{ */ #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED3_MASK (0x7U) #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED3_SHIFT (0U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_DPRIR_RESERVED3_SHIFT)) & NOC_GICRSGI4_GICR4_DPRIR_RESERVED3_MASK) #define NOC_GICRSGI4_GICR4_DPRIR_gpr0_pri_MASK (0xF8U) #define NOC_GICRSGI4_GICR4_DPRIR_gpr0_pri_SHIFT (3U) /*! gpr0_pri - gpr0_pri */ #define NOC_GICRSGI4_GICR4_DPRIR_gpr0_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_DPRIR_gpr0_pri_SHIFT)) & NOC_GICRSGI4_GICR4_DPRIR_gpr0_pri_MASK) #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED2_MASK (0x700U) #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED2_SHIFT (8U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_DPRIR_RESERVED2_SHIFT)) & NOC_GICRSGI4_GICR4_DPRIR_RESERVED2_MASK) #define NOC_GICRSGI4_GICR4_DPRIR_gpr1ns_pri_MASK (0xF800U) #define NOC_GICRSGI4_GICR4_DPRIR_gpr1ns_pri_SHIFT (11U) /*! gpr1ns_pri - gpr1ns_pri */ #define NOC_GICRSGI4_GICR4_DPRIR_gpr1ns_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_DPRIR_gpr1ns_pri_SHIFT)) & NOC_GICRSGI4_GICR4_DPRIR_gpr1ns_pri_MASK) #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED1_MASK (0x70000U) #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED1_SHIFT (16U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_DPRIR_RESERVED1_SHIFT)) & NOC_GICRSGI4_GICR4_DPRIR_RESERVED1_MASK) #define NOC_GICRSGI4_GICR4_DPRIR_gpr1sec_pri_MASK (0xF80000U) #define NOC_GICRSGI4_GICR4_DPRIR_gpr1sec_pri_SHIFT (19U) /*! gpr1sec_pri - gpr1sec_pri */ #define NOC_GICRSGI4_GICR4_DPRIR_gpr1sec_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_DPRIR_gpr1sec_pri_SHIFT)) & NOC_GICRSGI4_GICR4_DPRIR_gpr1sec_pri_MASK) #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED0_MASK (0xFF000000U) #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI4_GICR4_DPRIR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_DPRIR_RESERVED0_SHIFT)) & NOC_GICRSGI4_GICR4_DPRIR_RESERVED0_MASK) /*! @} */ /*! @name GICR4_ICERRR0 - GICR4_ICERRR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit0_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit1_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit2_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit3_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit4_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit5_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit6_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit7_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit8_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit9_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit10_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit11_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit12_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit13_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit14_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit15_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit16_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit17_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit18_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit19_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit20_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit21_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit22_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit23_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit24_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit25_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit26_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit27_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit28_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit29_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit30_MASK) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI4_GICR4_ICERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ICERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ICERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR4_ISERRR0 - GICR4_ISERRR0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit0_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit1_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit2_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit3_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit4_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit5_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit6_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit7_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit8_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit9_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit10_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit11_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit12_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit13_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit14_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit15_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit16_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit17_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit18_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit19_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit20_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit21_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit22_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit23_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit24_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit25_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit26_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit27_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit28_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit29_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit30_MASK) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI4_GICR4_ISERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_ISERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI4_GICR4_ISERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR4_CFGID0 - GICR4_CFGID0 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_CFGID0_PPINumber_MASK (0x1FFU) #define NOC_GICRSGI4_GICR4_CFGID0_PPINumber_SHIFT (0U) /*! PPINumber - PPINumber */ #define NOC_GICRSGI4_GICR4_CFGID0_PPINumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID0_PPINumber_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID0_PPINumber_MASK) #define NOC_GICRSGI4_GICR4_CFGID0_ECCSupport_MASK (0x200U) #define NOC_GICRSGI4_GICR4_CFGID0_ECCSupport_SHIFT (9U) /*! ECCSupport - ECCSupport */ #define NOC_GICRSGI4_GICR4_CFGID0_ECCSupport(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID0_ECCSupport_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID0_ECCSupport_MASK) #define NOC_GICRSGI4_GICR4_CFGID0_RESERVED0_MASK (0xFFFFFC00U) #define NOC_GICRSGI4_GICR4_CFGID0_RESERVED0_SHIFT (10U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI4_GICR4_CFGID0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID0_RESERVED0_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID0_RESERVED0_MASK) /*! @} */ /*! @name GICR4_CFGID1 - GICR4_CFGID1 */ /*! @{ */ #define NOC_GICRSGI4_GICR4_CFGID1_RESERVED0_MASK (0xFU) #define NOC_GICRSGI4_GICR4_CFGID1_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI4_GICR4_CFGID1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID1_RESERVED0_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID1_RESERVED0_MASK) #define NOC_GICRSGI4_GICR4_CFGID1_NumCPUs_MASK (0xFF0U) #define NOC_GICRSGI4_GICR4_CFGID1_NumCPUs_SHIFT (4U) /*! NumCPUs - NumCPUs */ #define NOC_GICRSGI4_GICR4_CFGID1_NumCPUs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID1_NumCPUs_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID1_NumCPUs_MASK) #define NOC_GICRSGI4_GICR4_CFGID1_RESERVED1_MASK (0xF000U) #define NOC_GICRSGI4_GICR4_CFGID1_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI4_GICR4_CFGID1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID1_RESERVED1_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID1_RESERVED1_MASK) #define NOC_GICRSGI4_GICR4_CFGID1_PPIsPerProcessor_MASK (0xFF0000U) #define NOC_GICRSGI4_GICR4_CFGID1_PPIsPerProcessor_SHIFT (16U) /*! PPIsPerProcessor - PPIsPerProcessor */ #define NOC_GICRSGI4_GICR4_CFGID1_PPIsPerProcessor(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID1_PPIsPerProcessor_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID1_PPIsPerProcessor_MASK) #define NOC_GICRSGI4_GICR4_CFGID1_REVAND_MASK (0xF000000U) #define NOC_GICRSGI4_GICR4_CFGID1_REVAND_SHIFT (24U) /*! REVAND - REVAND */ #define NOC_GICRSGI4_GICR4_CFGID1_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID1_REVAND_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID1_REVAND_MASK) #define NOC_GICRSGI4_GICR4_CFGID1_Version_MASK (0xF0000000U) #define NOC_GICRSGI4_GICR4_CFGID1_Version_SHIFT (28U) /*! Version - Version */ #define NOC_GICRSGI4_GICR4_CFGID1_Version(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI4_GICR4_CFGID1_Version_SHIFT)) & NOC_GICRSGI4_GICR4_CFGID1_Version_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRSGI4_Register_Masks */ /* NOC_GICRSGI4 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRSGI4 base address */ #define NOC__GIC__GICRSGI4_BASE (0x480F0000u) /** Peripheral NOC__GIC__GICRSGI4 base pointer */ #define NOC__GIC__GICRSGI4 ((NOC_GICRSGI4_Type *)NOC__GIC__GICRSGI4_BASE) /** Array initializer of NOC_GICRSGI4 peripheral base addresses */ #define NOC_GICRSGI4_BASE_ADDRS { NOC__GIC__GICRSGI4_BASE } /** Array initializer of NOC_GICRSGI4 peripheral base pointers */ #define NOC_GICRSGI4_BASE_PTRS { NOC__GIC__GICRSGI4 } /*! * @} */ /* end of group NOC_GICRSGI4_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICRSGI5 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI5_Peripheral_Access_Layer NOC_GICRSGI5 Peripheral Access Layer * @{ */ /** NOC_GICRSGI5 - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[128]; __IO uint32_t GICR5_IGROUPR0; /**< GICR5_IGROUPR0, offset: 0x80 */ uint8_t RESERVED_1[124]; __IO uint32_t GICR5_ISENABLER0; /**< GICR5_ISENABLER0, offset: 0x100 */ uint8_t RESERVED_2[124]; __IO uint32_t GICR5_ICENABLER0; /**< GICR5_ICENABLER0, offset: 0x180 */ uint8_t RESERVED_3[124]; __IO uint32_t GICR5_ISPENDR0; /**< GICR5_ISPENDR0, offset: 0x200 */ uint8_t RESERVED_4[124]; __IO uint32_t GICR5_ICPENDR0; /**< GICR5_ICPENDR0, offset: 0x280 */ uint8_t RESERVED_5[124]; __IO uint32_t GICR5_ISACTIVER0; /**< GICR5_ISACTIVER0, offset: 0x300 */ uint8_t RESERVED_6[124]; __IO uint32_t GICR5_ICACTIVER0; /**< GICR5_ICACTIVER0, offset: 0x380 */ uint8_t RESERVED_7[124]; __IO uint32_t GICR5_IPRIORITYR0; /**< GICR5_IPRIORITYR0, offset: 0x400 */ __IO uint32_t GICR5_IPRIORITYR1; /**< GICR5_IPRIORITYR1, offset: 0x404 */ __IO uint32_t GICR5_IPRIORITYR2; /**< GICR5_IPRIORITYR2, offset: 0x408 */ __IO uint32_t GICR5_IPRIORITYR3; /**< GICR5_IPRIORITYR3, offset: 0x40C */ __IO uint32_t GICR5_IPRIORITYR4; /**< GICR5_IPRIORITYR4, offset: 0x410 */ __IO uint32_t GICR5_IPRIORITYR5; /**< GICR5_IPRIORITYR5, offset: 0x414 */ __IO uint32_t GICR5_IPRIORITYR6; /**< GICR5_IPRIORITYR6, offset: 0x418 */ __IO uint32_t GICR5_IPRIORITYR7; /**< GICR5_IPRIORITYR7, offset: 0x41C */ uint8_t RESERVED_8[2016]; __I uint32_t GICR5_ICFGR0; /**< GICR5_ICFGR0, offset: 0xC00 */ __IO uint32_t GICR5_ICFGR1; /**< GICR5_ICFGR1, offset: 0xC04 */ uint8_t RESERVED_9[248]; __IO uint32_t GICR5_IGRPMODR0; /**< GICR5_IGRPMODR0, offset: 0xD00 */ uint8_t RESERVED_10[252]; __IO uint32_t GICR5_NSACR; /**< GICR5_NSACR, offset: 0xE00 */ uint8_t RESERVED_11[45564]; __I uint32_t GICR5_MISCSTATUSR; /**< GICR5_MISCSTATUSR, offset: 0xC000 */ uint8_t RESERVED_12[4]; __IO uint32_t GICR5_IERRVR; /**< GICR5_IERRVR, offset: 0xC008 */ uint8_t RESERVED_13[4]; __IO uint64_t GICR5_SGIDR; /**< GICR5_SGIDR, offset: 0xC010 */ __IO uint32_t GICR5_DPRIR; /**< GICR5_DPRIR, offset: 0xC018 */ uint8_t RESERVED_14[228]; __IO uint32_t GICR5_ICERRR0; /**< GICR5_ICERRR0, offset: 0xC100 */ uint8_t RESERVED_15[124]; __IO uint32_t GICR5_ISERRR0; /**< GICR5_ISERRR0, offset: 0xC180 */ uint8_t RESERVED_16[11900]; __I uint32_t GICR5_CFGID0; /**< GICR5_CFGID0, offset: 0xF000 */ __I uint32_t GICR5_CFGID1; /**< GICR5_CFGID1, offset: 0xF004 */ } NOC_GICRSGI5_Type; /* ---------------------------------------------------------------------------- -- NOC_GICRSGI5 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICRSGI5_Register_Masks NOC_GICRSGI5 Register Masks * @{ */ /*! @name GICR5_IGROUPR0 - GICR5_IGROUPR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit0_SHIFT (0U) /*! group_status_bit0 - group_status_bit0 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit0_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit1_SHIFT (1U) /*! group_status_bit1 - group_status_bit1 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit1_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit2_SHIFT (2U) /*! group_status_bit2 - group_status_bit2 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit2_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit3_SHIFT (3U) /*! group_status_bit3 - group_status_bit3 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit3_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit4_SHIFT (4U) /*! group_status_bit4 - group_status_bit4 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit4_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit5_SHIFT (5U) /*! group_status_bit5 - group_status_bit5 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit5_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit6_SHIFT (6U) /*! group_status_bit6 - group_status_bit6 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit6_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit7_SHIFT (7U) /*! group_status_bit7 - group_status_bit7 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit7_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit8_SHIFT (8U) /*! group_status_bit8 - group_status_bit8 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit8_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit9_SHIFT (9U) /*! group_status_bit9 - group_status_bit9 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit9_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit10_SHIFT (10U) /*! group_status_bit10 - group_status_bit10 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit10_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit11_SHIFT (11U) /*! group_status_bit11 - group_status_bit11 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit11_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit12_SHIFT (12U) /*! group_status_bit12 - group_status_bit12 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit12_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit13_SHIFT (13U) /*! group_status_bit13 - group_status_bit13 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit13_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit14_SHIFT (14U) /*! group_status_bit14 - group_status_bit14 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit14_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit15_SHIFT (15U) /*! group_status_bit15 - group_status_bit15 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit15_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit16_SHIFT (16U) /*! group_status_bit16 - group_status_bit16 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit16_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit17_SHIFT (17U) /*! group_status_bit17 - group_status_bit17 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit17_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit18_SHIFT (18U) /*! group_status_bit18 - group_status_bit18 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit18_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit19_SHIFT (19U) /*! group_status_bit19 - group_status_bit19 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit19_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit20_SHIFT (20U) /*! group_status_bit20 - group_status_bit20 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit20_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit21_SHIFT (21U) /*! group_status_bit21 - group_status_bit21 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit21_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit22_SHIFT (22U) /*! group_status_bit22 - group_status_bit22 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit22_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit23_SHIFT (23U) /*! group_status_bit23 - group_status_bit23 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit23_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit24_SHIFT (24U) /*! group_status_bit24 - group_status_bit24 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit24_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit25_SHIFT (25U) /*! group_status_bit25 - group_status_bit25 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit25_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit26_SHIFT (26U) /*! group_status_bit26 - group_status_bit26 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit26_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit27_SHIFT (27U) /*! group_status_bit27 - group_status_bit27 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit27_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit28_SHIFT (28U) /*! group_status_bit28 - group_status_bit28 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit28_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit29_SHIFT (29U) /*! group_status_bit29 - group_status_bit29 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit29_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit30_SHIFT (30U) /*! group_status_bit30 - group_status_bit30 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit30_MASK) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit31_SHIFT (31U) /*! group_status_bit31 - group_status_bit31 */ #define NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_IGROUPR0_group_status_bit31_MASK) /*! @} */ /*! @name GICR5_ISENABLER0 - GICR5_ISENABLER0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit0_SHIFT (0U) /*! set_enable_bit0 - set_enable_bit0 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit0_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit1_SHIFT (1U) /*! set_enable_bit1 - set_enable_bit1 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit1_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit2_SHIFT (2U) /*! set_enable_bit2 - set_enable_bit2 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit2_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit3_SHIFT (3U) /*! set_enable_bit3 - set_enable_bit3 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit3_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit4_SHIFT (4U) /*! set_enable_bit4 - set_enable_bit4 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit4_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit5_SHIFT (5U) /*! set_enable_bit5 - set_enable_bit5 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit5_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit6_SHIFT (6U) /*! set_enable_bit6 - set_enable_bit6 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit6_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit7_SHIFT (7U) /*! set_enable_bit7 - set_enable_bit7 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit7_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit8_SHIFT (8U) /*! set_enable_bit8 - set_enable_bit8 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit8_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit9_SHIFT (9U) /*! set_enable_bit9 - set_enable_bit9 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit9_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit10_SHIFT (10U) /*! set_enable_bit10 - set_enable_bit10 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit10_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit11_SHIFT (11U) /*! set_enable_bit11 - set_enable_bit11 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit11_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit12_SHIFT (12U) /*! set_enable_bit12 - set_enable_bit12 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit12_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit13_SHIFT (13U) /*! set_enable_bit13 - set_enable_bit13 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit13_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit14_SHIFT (14U) /*! set_enable_bit14 - set_enable_bit14 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit14_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit15_SHIFT (15U) /*! set_enable_bit15 - set_enable_bit15 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit15_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit16_SHIFT (16U) /*! set_enable_bit16 - set_enable_bit16 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit16_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit17_SHIFT (17U) /*! set_enable_bit17 - set_enable_bit17 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit17_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit18_SHIFT (18U) /*! set_enable_bit18 - set_enable_bit18 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit18_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit19_SHIFT (19U) /*! set_enable_bit19 - set_enable_bit19 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit19_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit20_SHIFT (20U) /*! set_enable_bit20 - set_enable_bit20 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit20_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit21_SHIFT (21U) /*! set_enable_bit21 - set_enable_bit21 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit21_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit22_SHIFT (22U) /*! set_enable_bit22 - set_enable_bit22 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit22_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit23_SHIFT (23U) /*! set_enable_bit23 - set_enable_bit23 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit23_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit24_SHIFT (24U) /*! set_enable_bit24 - set_enable_bit24 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit24_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit25_SHIFT (25U) /*! set_enable_bit25 - set_enable_bit25 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit25_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit26_SHIFT (26U) /*! set_enable_bit26 - set_enable_bit26 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit26_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit27_SHIFT (27U) /*! set_enable_bit27 - set_enable_bit27 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit27_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit28_SHIFT (28U) /*! set_enable_bit28 - set_enable_bit28 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit28_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit29_SHIFT (29U) /*! set_enable_bit29 - set_enable_bit29 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit29_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit30_SHIFT (30U) /*! set_enable_bit30 - set_enable_bit30 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit30_MASK) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit31_SHIFT (31U) /*! set_enable_bit31 - set_enable_bit31 */ #define NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ISENABLER0_set_enable_bit31_MASK) /*! @} */ /*! @name GICR5_ICENABLER0 - GICR5_ICENABLER0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit0_SHIFT (0U) /*! clear_enable_bit0 - clear_enable_bit0 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit0_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit1_SHIFT (1U) /*! clear_enable_bit1 - clear_enable_bit1 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit1_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit2_SHIFT (2U) /*! clear_enable_bit2 - clear_enable_bit2 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit2_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit3_SHIFT (3U) /*! clear_enable_bit3 - clear_enable_bit3 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit3_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit4_SHIFT (4U) /*! clear_enable_bit4 - clear_enable_bit4 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit4_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit5_SHIFT (5U) /*! clear_enable_bit5 - clear_enable_bit5 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit5_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit6_SHIFT (6U) /*! clear_enable_bit6 - clear_enable_bit6 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit6_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit7_SHIFT (7U) /*! clear_enable_bit7 - clear_enable_bit7 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit7_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit8_SHIFT (8U) /*! clear_enable_bit8 - clear_enable_bit8 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit8_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit9_SHIFT (9U) /*! clear_enable_bit9 - clear_enable_bit9 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit9_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit10_SHIFT (10U) /*! clear_enable_bit10 - clear_enable_bit10 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit10_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit11_SHIFT (11U) /*! clear_enable_bit11 - clear_enable_bit11 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit11_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit12_SHIFT (12U) /*! clear_enable_bit12 - clear_enable_bit12 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit12_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit13_SHIFT (13U) /*! clear_enable_bit13 - clear_enable_bit13 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit13_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit14_SHIFT (14U) /*! clear_enable_bit14 - clear_enable_bit14 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit14_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit15_SHIFT (15U) /*! clear_enable_bit15 - clear_enable_bit15 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit15_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit16_SHIFT (16U) /*! clear_enable_bit16 - clear_enable_bit16 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit16_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit17_SHIFT (17U) /*! clear_enable_bit17 - clear_enable_bit17 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit17_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit18_SHIFT (18U) /*! clear_enable_bit18 - clear_enable_bit18 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit18_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit19_SHIFT (19U) /*! clear_enable_bit19 - clear_enable_bit19 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit19_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit20_SHIFT (20U) /*! clear_enable_bit20 - clear_enable_bit20 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit20_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit21_SHIFT (21U) /*! clear_enable_bit21 - clear_enable_bit21 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit21_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit22_SHIFT (22U) /*! clear_enable_bit22 - clear_enable_bit22 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit22_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit23_SHIFT (23U) /*! clear_enable_bit23 - clear_enable_bit23 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit23_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit24_SHIFT (24U) /*! clear_enable_bit24 - clear_enable_bit24 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit24_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit25_SHIFT (25U) /*! clear_enable_bit25 - clear_enable_bit25 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit25_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit26_SHIFT (26U) /*! clear_enable_bit26 - clear_enable_bit26 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit26_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit27_SHIFT (27U) /*! clear_enable_bit27 - clear_enable_bit27 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit27_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit28_SHIFT (28U) /*! clear_enable_bit28 - clear_enable_bit28 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit28_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit29_SHIFT (29U) /*! clear_enable_bit29 - clear_enable_bit29 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit29_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit30_SHIFT (30U) /*! clear_enable_bit30 - clear_enable_bit30 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit30_MASK) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit31_SHIFT (31U) /*! clear_enable_bit31 - clear_enable_bit31 */ #define NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ICENABLER0_clear_enable_bit31_MASK) /*! @} */ /*! @name GICR5_ISPENDR0 - GICR5_ISPENDR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit0_SHIFT (0U) /*! set_pending_bit0 - set_pending_bit0 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit0_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit1_SHIFT (1U) /*! set_pending_bit1 - set_pending_bit1 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit1_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit2_SHIFT (2U) /*! set_pending_bit2 - set_pending_bit2 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit2_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit3_SHIFT (3U) /*! set_pending_bit3 - set_pending_bit3 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit3_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit4_SHIFT (4U) /*! set_pending_bit4 - set_pending_bit4 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit4_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit5_SHIFT (5U) /*! set_pending_bit5 - set_pending_bit5 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit5_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit6_SHIFT (6U) /*! set_pending_bit6 - set_pending_bit6 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit6_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit7_SHIFT (7U) /*! set_pending_bit7 - set_pending_bit7 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit7_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit8_SHIFT (8U) /*! set_pending_bit8 - set_pending_bit8 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit8_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit9_SHIFT (9U) /*! set_pending_bit9 - set_pending_bit9 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit9_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit10_SHIFT (10U) /*! set_pending_bit10 - set_pending_bit10 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit10_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit11_SHIFT (11U) /*! set_pending_bit11 - set_pending_bit11 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit11_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit12_SHIFT (12U) /*! set_pending_bit12 - set_pending_bit12 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit12_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit13_SHIFT (13U) /*! set_pending_bit13 - set_pending_bit13 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit13_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit14_SHIFT (14U) /*! set_pending_bit14 - set_pending_bit14 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit14_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit15_SHIFT (15U) /*! set_pending_bit15 - set_pending_bit15 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit15_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit16_SHIFT (16U) /*! set_pending_bit16 - set_pending_bit16 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit16_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit17_SHIFT (17U) /*! set_pending_bit17 - set_pending_bit17 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit17_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit18_SHIFT (18U) /*! set_pending_bit18 - set_pending_bit18 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit18_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit19_SHIFT (19U) /*! set_pending_bit19 - set_pending_bit19 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit19_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit20_SHIFT (20U) /*! set_pending_bit20 - set_pending_bit20 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit20_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit21_SHIFT (21U) /*! set_pending_bit21 - set_pending_bit21 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit21_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit22_SHIFT (22U) /*! set_pending_bit22 - set_pending_bit22 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit22_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit23_SHIFT (23U) /*! set_pending_bit23 - set_pending_bit23 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit23_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit24_SHIFT (24U) /*! set_pending_bit24 - set_pending_bit24 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit24_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit25_SHIFT (25U) /*! set_pending_bit25 - set_pending_bit25 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit25_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit26_SHIFT (26U) /*! set_pending_bit26 - set_pending_bit26 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit26_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit27_SHIFT (27U) /*! set_pending_bit27 - set_pending_bit27 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit27_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit28_SHIFT (28U) /*! set_pending_bit28 - set_pending_bit28 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit28_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit29_SHIFT (29U) /*! set_pending_bit29 - set_pending_bit29 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit29_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit30_SHIFT (30U) /*! set_pending_bit30 - set_pending_bit30 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit30_MASK) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit31_SHIFT (31U) /*! set_pending_bit31 - set_pending_bit31 */ #define NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ISPENDR0_set_pending_bit31_MASK) /*! @} */ /*! @name GICR5_ICPENDR0 - GICR5_ICPENDR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit0_SHIFT (0U) /*! clear_pending_bit0 - clear_pending_bit0 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit0_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit1_SHIFT (1U) /*! clear_pending_bit1 - clear_pending_bit1 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit1_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit2_SHIFT (2U) /*! clear_pending_bit2 - clear_pending_bit2 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit2_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit3_SHIFT (3U) /*! clear_pending_bit3 - clear_pending_bit3 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit3_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit4_SHIFT (4U) /*! clear_pending_bit4 - clear_pending_bit4 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit4_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit5_SHIFT (5U) /*! clear_pending_bit5 - clear_pending_bit5 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit5_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit6_SHIFT (6U) /*! clear_pending_bit6 - clear_pending_bit6 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit6_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit7_SHIFT (7U) /*! clear_pending_bit7 - clear_pending_bit7 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit7_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit8_SHIFT (8U) /*! clear_pending_bit8 - clear_pending_bit8 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit8_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit9_SHIFT (9U) /*! clear_pending_bit9 - clear_pending_bit9 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit9_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit10_SHIFT (10U) /*! clear_pending_bit10 - clear_pending_bit10 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit10_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit11_SHIFT (11U) /*! clear_pending_bit11 - clear_pending_bit11 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit11_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit12_SHIFT (12U) /*! clear_pending_bit12 - clear_pending_bit12 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit12_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit13_SHIFT (13U) /*! clear_pending_bit13 - clear_pending_bit13 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit13_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit14_SHIFT (14U) /*! clear_pending_bit14 - clear_pending_bit14 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit14_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit15_SHIFT (15U) /*! clear_pending_bit15 - clear_pending_bit15 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit15_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit16_SHIFT (16U) /*! clear_pending_bit16 - clear_pending_bit16 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit16_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit17_SHIFT (17U) /*! clear_pending_bit17 - clear_pending_bit17 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit17_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit18_SHIFT (18U) /*! clear_pending_bit18 - clear_pending_bit18 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit18_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit19_SHIFT (19U) /*! clear_pending_bit19 - clear_pending_bit19 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit19_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit20_SHIFT (20U) /*! clear_pending_bit20 - clear_pending_bit20 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit20_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit21_SHIFT (21U) /*! clear_pending_bit21 - clear_pending_bit21 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit21_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit22_SHIFT (22U) /*! clear_pending_bit22 - clear_pending_bit22 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit22_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit23_SHIFT (23U) /*! clear_pending_bit23 - clear_pending_bit23 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit23_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit24_SHIFT (24U) /*! clear_pending_bit24 - clear_pending_bit24 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit24_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit25_SHIFT (25U) /*! clear_pending_bit25 - clear_pending_bit25 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit25_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit26_SHIFT (26U) /*! clear_pending_bit26 - clear_pending_bit26 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit26_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit27_SHIFT (27U) /*! clear_pending_bit27 - clear_pending_bit27 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit27_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit28_SHIFT (28U) /*! clear_pending_bit28 - clear_pending_bit28 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit28_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit29_SHIFT (29U) /*! clear_pending_bit29 - clear_pending_bit29 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit29_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit30_SHIFT (30U) /*! clear_pending_bit30 - clear_pending_bit30 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit30_MASK) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit31_SHIFT (31U) /*! clear_pending_bit31 - clear_pending_bit31 */ #define NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ICPENDR0_clear_pending_bit31_MASK) /*! @} */ /*! @name GICR5_ISACTIVER0 - GICR5_ISACTIVER0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit0_SHIFT (0U) /*! set_active_bit0 - set_active_bit0 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit0_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit1_SHIFT (1U) /*! set_active_bit1 - set_active_bit1 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit1_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit2_SHIFT (2U) /*! set_active_bit2 - set_active_bit2 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit2_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit3_SHIFT (3U) /*! set_active_bit3 - set_active_bit3 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit3_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit4_SHIFT (4U) /*! set_active_bit4 - set_active_bit4 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit4_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit5_SHIFT (5U) /*! set_active_bit5 - set_active_bit5 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit5_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit6_SHIFT (6U) /*! set_active_bit6 - set_active_bit6 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit6_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit7_SHIFT (7U) /*! set_active_bit7 - set_active_bit7 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit7_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit8_SHIFT (8U) /*! set_active_bit8 - set_active_bit8 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit8_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit9_SHIFT (9U) /*! set_active_bit9 - set_active_bit9 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit9_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit10_SHIFT (10U) /*! set_active_bit10 - set_active_bit10 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit10_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit11_SHIFT (11U) /*! set_active_bit11 - set_active_bit11 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit11_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit12_SHIFT (12U) /*! set_active_bit12 - set_active_bit12 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit12_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit13_SHIFT (13U) /*! set_active_bit13 - set_active_bit13 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit13_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit14_SHIFT (14U) /*! set_active_bit14 - set_active_bit14 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit14_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit15_SHIFT (15U) /*! set_active_bit15 - set_active_bit15 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit15_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit16_SHIFT (16U) /*! set_active_bit16 - set_active_bit16 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit16_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit17_SHIFT (17U) /*! set_active_bit17 - set_active_bit17 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit17_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit18_SHIFT (18U) /*! set_active_bit18 - set_active_bit18 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit18_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit19_SHIFT (19U) /*! set_active_bit19 - set_active_bit19 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit19_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit20_SHIFT (20U) /*! set_active_bit20 - set_active_bit20 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit20_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit21_SHIFT (21U) /*! set_active_bit21 - set_active_bit21 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit21_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit22_SHIFT (22U) /*! set_active_bit22 - set_active_bit22 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit22_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit23_SHIFT (23U) /*! set_active_bit23 - set_active_bit23 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit23_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit24_SHIFT (24U) /*! set_active_bit24 - set_active_bit24 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit24_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit25_SHIFT (25U) /*! set_active_bit25 - set_active_bit25 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit25_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit26_SHIFT (26U) /*! set_active_bit26 - set_active_bit26 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit26_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit27_SHIFT (27U) /*! set_active_bit27 - set_active_bit27 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit27_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit28_SHIFT (28U) /*! set_active_bit28 - set_active_bit28 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit28_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit29_SHIFT (29U) /*! set_active_bit29 - set_active_bit29 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit29_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit30_SHIFT (30U) /*! set_active_bit30 - set_active_bit30 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit30_MASK) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit31_SHIFT (31U) /*! set_active_bit31 - set_active_bit31 */ #define NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ISACTIVER0_set_active_bit31_MASK) /*! @} */ /*! @name GICR5_ICACTIVER0 - GICR5_ICACTIVER0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit0_SHIFT (0U) /*! clear_active_bit0 - clear_active_bit0 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit0_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit1_SHIFT (1U) /*! clear_active_bit1 - clear_active_bit1 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit1_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit2_SHIFT (2U) /*! clear_active_bit2 - clear_active_bit2 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit2_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit3_SHIFT (3U) /*! clear_active_bit3 - clear_active_bit3 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit3_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit4_SHIFT (4U) /*! clear_active_bit4 - clear_active_bit4 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit4_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit5_SHIFT (5U) /*! clear_active_bit5 - clear_active_bit5 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit5_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit6_SHIFT (6U) /*! clear_active_bit6 - clear_active_bit6 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit6_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit7_SHIFT (7U) /*! clear_active_bit7 - clear_active_bit7 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit7_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit8_SHIFT (8U) /*! clear_active_bit8 - clear_active_bit8 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit8_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit9_SHIFT (9U) /*! clear_active_bit9 - clear_active_bit9 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit9_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit10_SHIFT (10U) /*! clear_active_bit10 - clear_active_bit10 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit10_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit11_SHIFT (11U) /*! clear_active_bit11 - clear_active_bit11 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit11_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit12_SHIFT (12U) /*! clear_active_bit12 - clear_active_bit12 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit12_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit13_SHIFT (13U) /*! clear_active_bit13 - clear_active_bit13 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit13_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit14_SHIFT (14U) /*! clear_active_bit14 - clear_active_bit14 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit14_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit15_SHIFT (15U) /*! clear_active_bit15 - clear_active_bit15 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit15_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit16_SHIFT (16U) /*! clear_active_bit16 - clear_active_bit16 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit16_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit17_SHIFT (17U) /*! clear_active_bit17 - clear_active_bit17 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit17_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit18_SHIFT (18U) /*! clear_active_bit18 - clear_active_bit18 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit18_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit19_SHIFT (19U) /*! clear_active_bit19 - clear_active_bit19 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit19_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit20_SHIFT (20U) /*! clear_active_bit20 - clear_active_bit20 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit20_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit21_SHIFT (21U) /*! clear_active_bit21 - clear_active_bit21 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit21_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit22_SHIFT (22U) /*! clear_active_bit22 - clear_active_bit22 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit22_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit23_SHIFT (23U) /*! clear_active_bit23 - clear_active_bit23 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit23_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit24_SHIFT (24U) /*! clear_active_bit24 - clear_active_bit24 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit24_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit25_SHIFT (25U) /*! clear_active_bit25 - clear_active_bit25 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit25_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit26_SHIFT (26U) /*! clear_active_bit26 - clear_active_bit26 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit26_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit27_SHIFT (27U) /*! clear_active_bit27 - clear_active_bit27 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit27_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit28_SHIFT (28U) /*! clear_active_bit28 - clear_active_bit28 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit28_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit29_SHIFT (29U) /*! clear_active_bit29 - clear_active_bit29 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit29_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit30_SHIFT (30U) /*! clear_active_bit30 - clear_active_bit30 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit30_MASK) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit31_SHIFT (31U) /*! clear_active_bit31 - clear_active_bit31 */ #define NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ICACTIVER0_clear_active_bit31_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR0 - GICR5_IPRIORITYR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR0_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR0_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR0_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR0_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR0_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR0_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR0_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR0_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR0_offset3_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR1 - GICR5_IPRIORITYR1 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR1_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR1_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR1_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR1_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR1_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR1_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR1_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR1_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR1_offset3_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR2 - GICR5_IPRIORITYR2 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR2_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR2_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR2_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR2_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR2_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR2_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR2_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR2_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR2_offset3_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR3 - GICR5_IPRIORITYR3 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR3_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR3_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR3_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR3_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR3_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR3_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR3_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR3_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR3_offset3_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR4 - GICR5_IPRIORITYR4 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR4_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR4_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR4_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR4_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR4_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR4_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR4_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR4_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR4_offset3_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR5 - GICR5_IPRIORITYR5 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR5_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR5_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR5_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR5_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR5_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR5_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR5_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR5_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR5_offset3_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR6 - GICR5_IPRIORITYR6 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR6_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR6_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR6_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR6_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR6_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR6_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR6_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR6_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR6_offset3_MASK) /*! @} */ /*! @name GICR5_IPRIORITYR7 - GICR5_IPRIORITYR7 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset0_MASK (0xFFU) #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset0_SHIFT (0U) /*! offset0 - offset0 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR7_offset0_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR7_offset0_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset1_MASK (0xFF00U) #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset1_SHIFT (8U) /*! offset1 - offset1 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR7_offset1_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR7_offset1_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset2_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset2_SHIFT (16U) /*! offset2 - offset2 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR7_offset2_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR7_offset2_MASK) #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset3_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset3_SHIFT (24U) /*! offset3 - offset3 * 0b00000000.. * 0b00001000.. * 0b00010000.. * 0b00011000.. * 0b00100000.. * 0b00101000.. * 0b00110000.. * 0b00111000.. * 0b01000000.. * 0b01001000.. * 0b01010000.. * 0b01011000.. * 0b01100000.. * 0b01101000.. * 0b01110000.. * 0b01111000.. * 0b10000000.. * 0b10001000.. * 0b10010000.. * 0b10011000.. * 0b10100000.. * 0b10101000.. * 0b10110000.. * 0b10111000.. * 0b11000000.. * 0b11001000.. * 0b11010000.. * 0b11011000.. * 0b11100000.. * 0b11101000.. * 0b11110000.. * 0b11111000.. */ #define NOC_GICRSGI5_GICR5_IPRIORITYR7_offset3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IPRIORITYR7_offset3_SHIFT)) & NOC_GICRSGI5_GICR5_IPRIORITYR7_offset3_MASK) /*! @} */ /*! @name GICR5_ICFGR0 - GICR5_ICFGR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config0_MASK (0x3U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config0_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config0_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config1_MASK (0xCU) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config1_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config1_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config2_MASK (0x30U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config2_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config2_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config3_MASK (0xC0U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config3_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config3_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config4_MASK (0x300U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config4_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config4_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config5_MASK (0xC00U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config5_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config5_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config6_MASK (0x3000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config6_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config6_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config7_MASK (0xC000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config7_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config7_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config8_MASK (0x30000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config8_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config8_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config9_MASK (0xC0000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config9_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config9_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config10_MASK (0x300000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config10_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config10_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config11_MASK (0xC00000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config11_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config11_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config12_MASK (0x3000000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config12_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config12_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config13_MASK (0xC000000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config13_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config13_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config14_MASK (0x30000000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config14_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config14_MASK) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI5_GICR5_ICFGR0_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR0_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR0_int_config15_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR0_int_config15_MASK) /*! @} */ /*! @name GICR5_ICFGR1 - GICR5_ICFGR1 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config0_MASK (0x3U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config0_SHIFT (0U) /*! int_config0 - int_config0 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config0_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config0_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config1_MASK (0xCU) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config1_SHIFT (2U) /*! int_config1 - int_config1 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config1_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config1_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config2_MASK (0x30U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config2_SHIFT (4U) /*! int_config2 - int_config2 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config2_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config2_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config3_MASK (0xC0U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config3_SHIFT (6U) /*! int_config3 - int_config3 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config3_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config3_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config4_MASK (0x300U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config4_SHIFT (8U) /*! int_config4 - int_config4 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config4_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config4_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config5_MASK (0xC00U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config5_SHIFT (10U) /*! int_config5 - int_config5 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config5_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config5_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config6_MASK (0x3000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config6_SHIFT (12U) /*! int_config6 - int_config6 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config6_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config6_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config7_MASK (0xC000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config7_SHIFT (14U) /*! int_config7 - int_config7 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config7_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config7_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config8_MASK (0x30000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config8_SHIFT (16U) /*! int_config8 - int_config8 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config8_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config8_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config9_MASK (0xC0000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config9_SHIFT (18U) /*! int_config9 - int_config9 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config9_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config9_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config10_MASK (0x300000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config10_SHIFT (20U) /*! int_config10 - int_config10 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config10_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config10_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config11_MASK (0xC00000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config11_SHIFT (22U) /*! int_config11 - int_config11 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config11_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config11_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config12_MASK (0x3000000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config12_SHIFT (24U) /*! int_config12 - int_config12 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config12_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config12_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config13_MASK (0xC000000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config13_SHIFT (26U) /*! int_config13 - int_config13 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config13_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config13_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config14_MASK (0x30000000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config14_SHIFT (28U) /*! int_config14 - int_config14 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config14_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config14_MASK) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config15_MASK (0xC0000000U) #define NOC_GICRSGI5_GICR5_ICFGR1_int_config15_SHIFT (30U) /*! int_config15 - int_config15 * 0b00.. * 0b10.. */ #define NOC_GICRSGI5_GICR5_ICFGR1_int_config15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICFGR1_int_config15_SHIFT)) & NOC_GICRSGI5_GICR5_ICFGR1_int_config15_MASK) /*! @} */ /*! @name GICR5_IGRPMODR0 - GICR5_IGRPMODR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit0_SHIFT (0U) /*! group_modifier_bit0 - group_modifier_bit0 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit0_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit1_SHIFT (1U) /*! group_modifier_bit1 - group_modifier_bit1 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit1_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit2_SHIFT (2U) /*! group_modifier_bit2 - group_modifier_bit2 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit2_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit3_SHIFT (3U) /*! group_modifier_bit3 - group_modifier_bit3 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit3_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit4_SHIFT (4U) /*! group_modifier_bit4 - group_modifier_bit4 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit4_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit5_SHIFT (5U) /*! group_modifier_bit5 - group_modifier_bit5 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit5_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit6_SHIFT (6U) /*! group_modifier_bit6 - group_modifier_bit6 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit6_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit7_SHIFT (7U) /*! group_modifier_bit7 - group_modifier_bit7 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit7_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit8_SHIFT (8U) /*! group_modifier_bit8 - group_modifier_bit8 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit8_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit9_SHIFT (9U) /*! group_modifier_bit9 - group_modifier_bit9 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit9_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit10_SHIFT (10U) /*! group_modifier_bit10 - group_modifier_bit10 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit10_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit11_SHIFT (11U) /*! group_modifier_bit11 - group_modifier_bit11 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit11_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit12_SHIFT (12U) /*! group_modifier_bit12 - group_modifier_bit12 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit12_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit13_SHIFT (13U) /*! group_modifier_bit13 - group_modifier_bit13 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit13_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit14_SHIFT (14U) /*! group_modifier_bit14 - group_modifier_bit14 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit14_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit15_SHIFT (15U) /*! group_modifier_bit15 - group_modifier_bit15 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit15_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit16_SHIFT (16U) /*! group_modifier_bit16 - group_modifier_bit16 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit16_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit17_SHIFT (17U) /*! group_modifier_bit17 - group_modifier_bit17 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit17_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit18_SHIFT (18U) /*! group_modifier_bit18 - group_modifier_bit18 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit18_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit19_SHIFT (19U) /*! group_modifier_bit19 - group_modifier_bit19 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit19_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit20_SHIFT (20U) /*! group_modifier_bit20 - group_modifier_bit20 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit20_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit21_SHIFT (21U) /*! group_modifier_bit21 - group_modifier_bit21 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit21_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit22_SHIFT (22U) /*! group_modifier_bit22 - group_modifier_bit22 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit22_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit23_SHIFT (23U) /*! group_modifier_bit23 - group_modifier_bit23 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit23_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit24_SHIFT (24U) /*! group_modifier_bit24 - group_modifier_bit24 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit24_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit25_SHIFT (25U) /*! group_modifier_bit25 - group_modifier_bit25 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit25_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit26_SHIFT (26U) /*! group_modifier_bit26 - group_modifier_bit26 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit26_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit27_SHIFT (27U) /*! group_modifier_bit27 - group_modifier_bit27 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit27_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit28_SHIFT (28U) /*! group_modifier_bit28 - group_modifier_bit28 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit28_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit29_SHIFT (29U) /*! group_modifier_bit29 - group_modifier_bit29 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit29_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit30_SHIFT (30U) /*! group_modifier_bit30 - group_modifier_bit30 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit30_MASK) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit31_SHIFT (31U) /*! group_modifier_bit31 - group_modifier_bit31 */ #define NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_IGRPMODR0_group_modifier_bit31_MASK) /*! @} */ /*! @name GICR5_NSACR - GICR5_NSACR */ /*! @{ */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access0_MASK (0x3U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access0_SHIFT (0U) /*! ns_access0 - ns_access0 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access0_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access0_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access1_MASK (0xCU) #define NOC_GICRSGI5_GICR5_NSACR_ns_access1_SHIFT (2U) /*! ns_access1 - ns_access1 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access1_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access1_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access2_MASK (0x30U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access2_SHIFT (4U) /*! ns_access2 - ns_access2 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access2_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access2_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access3_MASK (0xC0U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access3_SHIFT (6U) /*! ns_access3 - ns_access3 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access3_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access3_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access4_MASK (0x300U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access4_SHIFT (8U) /*! ns_access4 - ns_access4 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access4_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access4_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access5_MASK (0xC00U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access5_SHIFT (10U) /*! ns_access5 - ns_access5 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access5_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access5_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access6_MASK (0x3000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access6_SHIFT (12U) /*! ns_access6 - ns_access6 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access6_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access6_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access7_MASK (0xC000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access7_SHIFT (14U) /*! ns_access7 - ns_access7 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access7_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access7_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access8_MASK (0x30000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access8_SHIFT (16U) /*! ns_access8 - ns_access8 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access8_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access8_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access9_MASK (0xC0000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access9_SHIFT (18U) /*! ns_access9 - ns_access9 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access9_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access9_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access10_MASK (0x300000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access10_SHIFT (20U) /*! ns_access10 - ns_access10 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access10_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access10_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access11_MASK (0xC00000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access11_SHIFT (22U) /*! ns_access11 - ns_access11 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access11_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access11_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access12_MASK (0x3000000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access12_SHIFT (24U) /*! ns_access12 - ns_access12 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access12_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access12_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access13_MASK (0xC000000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access13_SHIFT (26U) /*! ns_access13 - ns_access13 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access13_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access13_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access14_MASK (0x30000000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access14_SHIFT (28U) /*! ns_access14 - ns_access14 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access14_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access14_MASK) #define NOC_GICRSGI5_GICR5_NSACR_ns_access15_MASK (0xC0000000U) #define NOC_GICRSGI5_GICR5_NSACR_ns_access15_SHIFT (30U) /*! ns_access15 - ns_access15 */ #define NOC_GICRSGI5_GICR5_NSACR_ns_access15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_NSACR_ns_access15_SHIFT)) & NOC_GICRSGI5_GICR5_NSACR_ns_access15_MASK) /*! @} */ /*! @name GICR5_MISCSTATUSR - GICR5_MISCSTATUSR */ /*! @{ */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp0_SHIFT (0U) /*! EnableGrp0 - EnableGrp0 */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp0_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp0_MASK) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_ns_MASK (0x2U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_ns_SHIFT (1U) /*! EnableGrp1_ns - EnableGrp1_ns */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_ns(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_ns_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_ns_MASK) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_s_MASK (0x4U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_s_SHIFT (2U) /*! EnableGrp1_s - EnableGrp1_s */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_s(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_s_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_EnableGrp1_s_MASK) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED0_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED0_MASK) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_access_type_MASK (0x10U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_access_type_SHIFT (4U) /*! access_type - access_type */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_access_type(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_access_type_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_access_type_MASK) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED1_MASK (0x3FFFFFE0U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED1_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_RESERVED1_MASK) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_wake_request_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_wake_request_SHIFT (30U) /*! wake_request - wake_request */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_wake_request(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_wake_request_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_wake_request_MASK) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_cpu_active_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_MISCSTATUSR_cpu_active_SHIFT (31U) /*! cpu_active - cpu_active */ #define NOC_GICRSGI5_GICR5_MISCSTATUSR_cpu_active(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_MISCSTATUSR_cpu_active_SHIFT)) & NOC_GICRSGI5_GICR5_MISCSTATUSR_cpu_active_MASK) /*! @} */ /*! @name GICR5_IERRVR - GICR5_IERRVR */ /*! @{ */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit0_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit1_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit2_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit3_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit4_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit5_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit6_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit7_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit8_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit9_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit10_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit11_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit12_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit13_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit14_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit15_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit16_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit17_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit18_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit19_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit20_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit21_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit22_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit23_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit24_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit25_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit26_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit27_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit28_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit29_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit30_MASK) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI5_GICR5_IERRVR_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_IERRVR_valid_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_IERRVR_valid_bit31_MASK) /*! @} */ /*! @name GICR5_SGIDR - GICR5_SGIDR */ /*! @{ */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr0_SHIFT (0U) /*! nsacr0 - nsacr0 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr0_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr0_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp0_MASK (0x2U) #define NOC_GICRSGI5_GICR5_SGIDR_grp0_SHIFT (1U) /*! grp0 - grp0 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp0_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp0_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod0_MASK (0x4U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod0_SHIFT (2U) /*! grpmod0 - grpmod0 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod0_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod0_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED0_MASK (0x8U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED0_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED0_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr1_MASK (0x10U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr1_SHIFT (4U) /*! nsacr1 - nsacr1 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr1_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr1_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp1_MASK (0x20U) #define NOC_GICRSGI5_GICR5_SGIDR_grp1_SHIFT (5U) /*! grp1 - grp1 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp1_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp1_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod1_MASK (0x40U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod1_SHIFT (6U) /*! grpmod1 - grpmod1 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod1_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod1_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED1_MASK (0x80U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED1_SHIFT (7U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED1_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED1_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr2_MASK (0x100U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr2_SHIFT (8U) /*! nsacr2 - nsacr2 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr2_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr2_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp2_MASK (0x200U) #define NOC_GICRSGI5_GICR5_SGIDR_grp2_SHIFT (9U) /*! grp2 - grp2 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp2_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp2_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod2_MASK (0x400U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod2_SHIFT (10U) /*! grpmod2 - grpmod2 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod2_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod2_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED2_MASK (0x800U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED2_SHIFT (11U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED2_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED2_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr3_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr3_SHIFT (12U) /*! nsacr3 - nsacr3 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr3_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr3_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp3_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp3_SHIFT (13U) /*! grp3 - grp3 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp3_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp3_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod3_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod3_SHIFT (14U) /*! grpmod3 - grpmod3 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod3_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod3_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED3_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED3_SHIFT (15U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED3_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED3_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr4_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr4_SHIFT (16U) /*! nsacr4 - nsacr4 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr4_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr4_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp4_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp4_SHIFT (17U) /*! grp4 - grp4 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp4_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp4_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod4_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod4_SHIFT (18U) /*! grpmod4 - grpmod4 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod4_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod4_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED4_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED4_SHIFT (19U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED4_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED4_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr5_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr5_SHIFT (20U) /*! nsacr5 - nsacr5 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr5_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr5_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp5_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp5_SHIFT (21U) /*! grp5 - grp5 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp5_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp5_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod5_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod5_SHIFT (22U) /*! grpmod5 - grpmod5 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod5_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod5_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED5_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED5_SHIFT (23U) /*! RESERVED5 - RESERVED5 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED5(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED5_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED5_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr6_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr6_SHIFT (24U) /*! nsacr6 - nsacr6 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr6_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr6_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp6_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp6_SHIFT (25U) /*! grp6 - grp6 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp6_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp6_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod6_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod6_SHIFT (26U) /*! grpmod6 - grpmod6 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod6_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod6_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED6_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED6_SHIFT (27U) /*! RESERVED6 - RESERVED6 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED6(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED6_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED6_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr7_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr7_SHIFT (28U) /*! nsacr7 - nsacr7 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr7_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr7_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp7_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp7_SHIFT (29U) /*! grp7 - grp7 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp7_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp7_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod7_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod7_SHIFT (30U) /*! grpmod7 - grpmod7 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod7_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod7_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED7_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED7_SHIFT (31U) /*! RESERVED7 - RESERVED7 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED7(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED7_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED7_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr8_MASK (0x100000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr8_SHIFT (32U) /*! nsacr8 - nsacr8 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr8_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr8_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp8_MASK (0x200000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp8_SHIFT (33U) /*! grp8 - grp8 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp8_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp8_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod8_MASK (0x400000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod8_SHIFT (34U) /*! grpmod8 - grpmod8 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod8_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod8_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED8_MASK (0x800000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED8_SHIFT (35U) /*! RESERVED8 - RESERVED8 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED8(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED8_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED8_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr9_MASK (0x1000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr9_SHIFT (36U) /*! nsacr9 - nsacr9 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr9_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr9_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp9_MASK (0x2000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp9_SHIFT (37U) /*! grp9 - grp9 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp9_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp9_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod9_MASK (0x4000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod9_SHIFT (38U) /*! grpmod9 - grpmod9 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod9_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod9_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED9_MASK (0x8000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED9_SHIFT (39U) /*! RESERVED9 - RESERVED9 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED9(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED9_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED9_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr10_MASK (0x10000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr10_SHIFT (40U) /*! nsacr10 - nsacr10 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr10_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr10_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp10_MASK (0x20000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp10_SHIFT (41U) /*! grp10 - grp10 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp10_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp10_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod10_MASK (0x40000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod10_SHIFT (42U) /*! grpmod10 - grpmod10 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod10_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod10_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED10_MASK (0x80000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED10_SHIFT (43U) /*! RESERVED10 - RESERVED10 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED10(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED10_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED10_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr11_MASK (0x100000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr11_SHIFT (44U) /*! nsacr11 - nsacr11 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr11_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr11_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp11_MASK (0x200000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp11_SHIFT (45U) /*! grp11 - grp11 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp11_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp11_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod11_MASK (0x400000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod11_SHIFT (46U) /*! grpmod11 - grpmod11 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod11_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod11_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED11_MASK (0x800000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED11_SHIFT (47U) /*! RESERVED11 - RESERVED11 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED11(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED11_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED11_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr12_MASK (0x1000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr12_SHIFT (48U) /*! nsacr12 - nsacr12 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr12_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr12_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp12_MASK (0x2000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp12_SHIFT (49U) /*! grp12 - grp12 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp12_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp12_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod12_MASK (0x4000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod12_SHIFT (50U) /*! grpmod12 - grpmod12 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod12_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod12_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED12_MASK (0x8000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED12_SHIFT (51U) /*! RESERVED12 - RESERVED12 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED12(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED12_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED12_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr13_MASK (0x10000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr13_SHIFT (52U) /*! nsacr13 - nsacr13 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr13_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr13_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp13_MASK (0x20000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp13_SHIFT (53U) /*! grp13 - grp13 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp13_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp13_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod13_MASK (0x40000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod13_SHIFT (54U) /*! grpmod13 - grpmod13 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod13_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod13_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED13_MASK (0x80000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED13_SHIFT (55U) /*! RESERVED13 - RESERVED13 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED13(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED13_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED13_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr14_MASK (0x100000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr14_SHIFT (56U) /*! nsacr14 - nsacr14 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr14_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr14_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp14_MASK (0x200000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp14_SHIFT (57U) /*! grp14 - grp14 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp14_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp14_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod14_MASK (0x400000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod14_SHIFT (58U) /*! grpmod14 - grpmod14 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod14(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod14_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod14_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED15_MASK (0x800000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED15_SHIFT (59U) /*! RESERVED15 - RESERVED15 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED15_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED15_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr15_MASK (0x1000000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_nsacr15_SHIFT (60U) /*! nsacr15 - nsacr15 */ #define NOC_GICRSGI5_GICR5_SGIDR_nsacr15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_nsacr15_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_nsacr15_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grp15_MASK (0x2000000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grp15_SHIFT (61U) /*! grp15 - grp15 */ #define NOC_GICRSGI5_GICR5_SGIDR_grp15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grp15_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grp15_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod15_MASK (0x4000000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_grpmod15_SHIFT (62U) /*! grpmod15 - grpmod15 */ #define NOC_GICRSGI5_GICR5_SGIDR_grpmod15(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_grpmod15_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_grpmod15_MASK) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED16_MASK (0x8000000000000000U) #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED16_SHIFT (63U) /*! RESERVED16 - RESERVED16 */ #define NOC_GICRSGI5_GICR5_SGIDR_RESERVED16(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICRSGI5_GICR5_SGIDR_RESERVED16_SHIFT)) & NOC_GICRSGI5_GICR5_SGIDR_RESERVED16_MASK) /*! @} */ /*! @name GICR5_DPRIR - GICR5_DPRIR */ /*! @{ */ #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED3_MASK (0x7U) #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED3_SHIFT (0U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_DPRIR_RESERVED3_SHIFT)) & NOC_GICRSGI5_GICR5_DPRIR_RESERVED3_MASK) #define NOC_GICRSGI5_GICR5_DPRIR_gpr0_pri_MASK (0xF8U) #define NOC_GICRSGI5_GICR5_DPRIR_gpr0_pri_SHIFT (3U) /*! gpr0_pri - gpr0_pri */ #define NOC_GICRSGI5_GICR5_DPRIR_gpr0_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_DPRIR_gpr0_pri_SHIFT)) & NOC_GICRSGI5_GICR5_DPRIR_gpr0_pri_MASK) #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED2_MASK (0x700U) #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED2_SHIFT (8U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_DPRIR_RESERVED2_SHIFT)) & NOC_GICRSGI5_GICR5_DPRIR_RESERVED2_MASK) #define NOC_GICRSGI5_GICR5_DPRIR_gpr1ns_pri_MASK (0xF800U) #define NOC_GICRSGI5_GICR5_DPRIR_gpr1ns_pri_SHIFT (11U) /*! gpr1ns_pri - gpr1ns_pri */ #define NOC_GICRSGI5_GICR5_DPRIR_gpr1ns_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_DPRIR_gpr1ns_pri_SHIFT)) & NOC_GICRSGI5_GICR5_DPRIR_gpr1ns_pri_MASK) #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED1_MASK (0x70000U) #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED1_SHIFT (16U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_DPRIR_RESERVED1_SHIFT)) & NOC_GICRSGI5_GICR5_DPRIR_RESERVED1_MASK) #define NOC_GICRSGI5_GICR5_DPRIR_gpr1sec_pri_MASK (0xF80000U) #define NOC_GICRSGI5_GICR5_DPRIR_gpr1sec_pri_SHIFT (19U) /*! gpr1sec_pri - gpr1sec_pri */ #define NOC_GICRSGI5_GICR5_DPRIR_gpr1sec_pri(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_DPRIR_gpr1sec_pri_SHIFT)) & NOC_GICRSGI5_GICR5_DPRIR_gpr1sec_pri_MASK) #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED0_MASK (0xFF000000U) #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI5_GICR5_DPRIR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_DPRIR_RESERVED0_SHIFT)) & NOC_GICRSGI5_GICR5_DPRIR_RESERVED0_MASK) /*! @} */ /*! @name GICR5_ICERRR0 - GICR5_ICERRR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit0_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit1_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit2_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit3_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit4_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit5_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit6_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit7_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit8_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit9_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit10_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit11_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit12_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit13_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit14_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit15_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit16_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit17_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit18_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit19_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit20_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit21_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit22_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit23_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit24_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit25_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit26_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit27_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit28_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit29_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit30_MASK) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI5_GICR5_ICERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ICERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ICERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR5_ISERRR0 - GICR5_ISERRR0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit0_MASK (0x1U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit0_SHIFT (0U) /*! valid_bit0 - valid_bit0 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit0_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit0_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit1_MASK (0x2U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit1_SHIFT (1U) /*! valid_bit1 - valid_bit1 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit1_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit1_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit2_MASK (0x4U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit2_SHIFT (2U) /*! valid_bit2 - valid_bit2 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit2_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit2_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit3_MASK (0x8U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit3_SHIFT (3U) /*! valid_bit3 - valid_bit3 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit3_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit3_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit4_MASK (0x10U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit4_SHIFT (4U) /*! valid_bit4 - valid_bit4 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit4(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit4_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit4_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit5_MASK (0x20U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit5_SHIFT (5U) /*! valid_bit5 - valid_bit5 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit5(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit5_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit5_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit6_MASK (0x40U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit6_SHIFT (6U) /*! valid_bit6 - valid_bit6 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit6(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit6_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit6_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit7_MASK (0x80U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit7_SHIFT (7U) /*! valid_bit7 - valid_bit7 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit7(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit7_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit7_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit8_MASK (0x100U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit8_SHIFT (8U) /*! valid_bit8 - valid_bit8 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit8(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit8_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit8_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit9_MASK (0x200U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit9_SHIFT (9U) /*! valid_bit9 - valid_bit9 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit9(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit9_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit9_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit10_MASK (0x400U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit10_SHIFT (10U) /*! valid_bit10 - valid_bit10 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit10(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit10_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit10_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit11_MASK (0x800U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit11_SHIFT (11U) /*! valid_bit11 - valid_bit11 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit11(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit11_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit11_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit12_MASK (0x1000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit12_SHIFT (12U) /*! valid_bit12 - valid_bit12 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit12(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit12_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit12_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit13_MASK (0x2000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit13_SHIFT (13U) /*! valid_bit13 - valid_bit13 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit13(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit13_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit13_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit14_MASK (0x4000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit14_SHIFT (14U) /*! valid_bit14 - valid_bit14 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit14(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit14_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit14_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit15_MASK (0x8000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit15_SHIFT (15U) /*! valid_bit15 - valid_bit15 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit15(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit15_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit15_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit16_MASK (0x10000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit16_SHIFT (16U) /*! valid_bit16 - valid_bit16 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit16(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit16_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit16_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit17_MASK (0x20000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit17_SHIFT (17U) /*! valid_bit17 - valid_bit17 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit17(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit17_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit17_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit18_MASK (0x40000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit18_SHIFT (18U) /*! valid_bit18 - valid_bit18 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit18(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit18_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit18_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit19_MASK (0x80000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit19_SHIFT (19U) /*! valid_bit19 - valid_bit19 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit19(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit19_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit19_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit20_MASK (0x100000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit20_SHIFT (20U) /*! valid_bit20 - valid_bit20 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit20(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit20_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit20_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit21_MASK (0x200000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit21_SHIFT (21U) /*! valid_bit21 - valid_bit21 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit21(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit21_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit21_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit22_MASK (0x400000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit22_SHIFT (22U) /*! valid_bit22 - valid_bit22 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit22(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit22_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit22_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit23_MASK (0x800000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit23_SHIFT (23U) /*! valid_bit23 - valid_bit23 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit23(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit23_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit23_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit24_MASK (0x1000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit24_SHIFT (24U) /*! valid_bit24 - valid_bit24 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit24(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit24_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit24_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit25_MASK (0x2000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit25_SHIFT (25U) /*! valid_bit25 - valid_bit25 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit25(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit25_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit25_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit26_MASK (0x4000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit26_SHIFT (26U) /*! valid_bit26 - valid_bit26 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit26(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit26_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit26_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit27_MASK (0x8000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit27_SHIFT (27U) /*! valid_bit27 - valid_bit27 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit27(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit27_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit27_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit28_MASK (0x10000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit28_SHIFT (28U) /*! valid_bit28 - valid_bit28 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit28(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit28_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit28_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit29_MASK (0x20000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit29_SHIFT (29U) /*! valid_bit29 - valid_bit29 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit29(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit29_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit29_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit30_MASK (0x40000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit30_SHIFT (30U) /*! valid_bit30 - valid_bit30 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit30(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit30_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit30_MASK) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit31_MASK (0x80000000U) #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit31_SHIFT (31U) /*! valid_bit31 - valid_bit31 */ #define NOC_GICRSGI5_GICR5_ISERRR0_valid_bit31(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_ISERRR0_valid_bit31_SHIFT)) & NOC_GICRSGI5_GICR5_ISERRR0_valid_bit31_MASK) /*! @} */ /*! @name GICR5_CFGID0 - GICR5_CFGID0 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_CFGID0_PPINumber_MASK (0x1FFU) #define NOC_GICRSGI5_GICR5_CFGID0_PPINumber_SHIFT (0U) /*! PPINumber - PPINumber */ #define NOC_GICRSGI5_GICR5_CFGID0_PPINumber(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID0_PPINumber_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID0_PPINumber_MASK) #define NOC_GICRSGI5_GICR5_CFGID0_ECCSupport_MASK (0x200U) #define NOC_GICRSGI5_GICR5_CFGID0_ECCSupport_SHIFT (9U) /*! ECCSupport - ECCSupport */ #define NOC_GICRSGI5_GICR5_CFGID0_ECCSupport(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID0_ECCSupport_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID0_ECCSupport_MASK) #define NOC_GICRSGI5_GICR5_CFGID0_RESERVED0_MASK (0xFFFFFC00U) #define NOC_GICRSGI5_GICR5_CFGID0_RESERVED0_SHIFT (10U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI5_GICR5_CFGID0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID0_RESERVED0_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID0_RESERVED0_MASK) /*! @} */ /*! @name GICR5_CFGID1 - GICR5_CFGID1 */ /*! @{ */ #define NOC_GICRSGI5_GICR5_CFGID1_RESERVED0_MASK (0xFU) #define NOC_GICRSGI5_GICR5_CFGID1_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICRSGI5_GICR5_CFGID1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID1_RESERVED0_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID1_RESERVED0_MASK) #define NOC_GICRSGI5_GICR5_CFGID1_NumCPUs_MASK (0xFF0U) #define NOC_GICRSGI5_GICR5_CFGID1_NumCPUs_SHIFT (4U) /*! NumCPUs - NumCPUs */ #define NOC_GICRSGI5_GICR5_CFGID1_NumCPUs(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID1_NumCPUs_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID1_NumCPUs_MASK) #define NOC_GICRSGI5_GICR5_CFGID1_RESERVED1_MASK (0xF000U) #define NOC_GICRSGI5_GICR5_CFGID1_RESERVED1_SHIFT (12U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICRSGI5_GICR5_CFGID1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID1_RESERVED1_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID1_RESERVED1_MASK) #define NOC_GICRSGI5_GICR5_CFGID1_PPIsPerProcessor_MASK (0xFF0000U) #define NOC_GICRSGI5_GICR5_CFGID1_PPIsPerProcessor_SHIFT (16U) /*! PPIsPerProcessor - PPIsPerProcessor */ #define NOC_GICRSGI5_GICR5_CFGID1_PPIsPerProcessor(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID1_PPIsPerProcessor_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID1_PPIsPerProcessor_MASK) #define NOC_GICRSGI5_GICR5_CFGID1_REVAND_MASK (0xF000000U) #define NOC_GICRSGI5_GICR5_CFGID1_REVAND_SHIFT (24U) /*! REVAND - REVAND */ #define NOC_GICRSGI5_GICR5_CFGID1_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID1_REVAND_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID1_REVAND_MASK) #define NOC_GICRSGI5_GICR5_CFGID1_Version_MASK (0xF0000000U) #define NOC_GICRSGI5_GICR5_CFGID1_Version_SHIFT (28U) /*! Version - Version */ #define NOC_GICRSGI5_GICR5_CFGID1_Version(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICRSGI5_GICR5_CFGID1_Version_SHIFT)) & NOC_GICRSGI5_GICR5_CFGID1_Version_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICRSGI5_Register_Masks */ /* NOC_GICRSGI5 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICRSGI5 base address */ #define NOC__GIC__GICRSGI5_BASE (0x48110000u) /** Peripheral NOC__GIC__GICRSGI5 base pointer */ #define NOC__GIC__GICRSGI5 ((NOC_GICRSGI5_Type *)NOC__GIC__GICRSGI5_BASE) /** Array initializer of NOC_GICRSGI5 peripheral base addresses */ #define NOC_GICRSGI5_BASE_ADDRS { NOC__GIC__GICRSGI5_BASE } /** Array initializer of NOC_GICRSGI5 peripheral base pointers */ #define NOC_GICRSGI5_BASE_PTRS { NOC__GIC__GICRSGI5 } /*! * @} */ /* end of group NOC_GICRSGI5_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GICT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICT_Peripheral_Access_Layer NOC_GICT Peripheral Access Layer * @{ */ /** NOC_GICT - Register Layout Typedef */ typedef struct { __I uint64_t GICT_ERR0FR; /**< GICT_ERR0FR, offset: 0x0 */ __IO uint64_t GICT_ERR0CTLR; /**< GICT_ERR0CTLR, offset: 0x8 */ __IO uint64_t GICT_ERR0STATUS; /**< GICT_ERR0STATUS, offset: 0x10 */ __I uint64_t GICT_ERR0ADDR; /**< GICT_ERR0ADDR, offset: 0x18 */ __IO uint64_t GICT_ERR0MISC0; /**< GICT_ERR0MISC0, offset: 0x20 */ __IO uint64_t GICT_ERR0MISC1; /**< GICT_ERR0MISC1, offset: 0x28 */ uint8_t RESERVED_0[16]; __I uint64_t GICT_ERR1FR; /**< GICT_ERR1FR, offset: 0x40 */ __IO uint64_t GICT_ERR1CTLR; /**< GICT_ERR1CTLR, offset: 0x48 */ __IO uint64_t GICT_ERR1STATUS; /**< GICT_ERR1STATUS, offset: 0x50 */ __I uint64_t GICT_ERR1ADDR; /**< GICT_ERR1ADDR, offset: 0x58 */ __IO uint64_t GICT_ERR1MISC0; /**< GICT_ERR1MISC0, offset: 0x60 */ __IO uint64_t GICT_ERR1MISC1; /**< GICT_ERR1MISC1, offset: 0x68 */ uint8_t RESERVED_1[16]; __I uint64_t GICT_ERR2FR; /**< GICT_ERR2FR, offset: 0x80 */ __IO uint64_t GICT_ERR2CTLR; /**< GICT_ERR2CTLR, offset: 0x88 */ __IO uint64_t GICT_ERR2STATUS; /**< GICT_ERR2STATUS, offset: 0x90 */ __I uint64_t GICT_ERR2ADDR; /**< GICT_ERR2ADDR, offset: 0x98 */ __IO uint64_t GICT_ERR2MISC0; /**< GICT_ERR2MISC0, offset: 0xA0 */ __IO uint64_t GICT_ERR2MISC1; /**< GICT_ERR2MISC1, offset: 0xA8 */ uint8_t RESERVED_2[16]; __I uint64_t GICT_ERR3FR; /**< GICT_ERR3FR, offset: 0xC0 */ __IO uint64_t GICT_ERR3CTLR; /**< GICT_ERR3CTLR, offset: 0xC8 */ __IO uint64_t GICT_ERR3STATUS; /**< GICT_ERR3STATUS, offset: 0xD0 */ __I uint64_t GICT_ERR3ADDR; /**< GICT_ERR3ADDR, offset: 0xD8 */ __IO uint64_t GICT_ERR3MISC0; /**< GICT_ERR3MISC0, offset: 0xE0 */ __IO uint64_t GICT_ERR3MISC1; /**< GICT_ERR3MISC1, offset: 0xE8 */ uint8_t RESERVED_3[16]; __I uint64_t GICT_ERR4FR; /**< GICT_ERR4FR, offset: 0x100 */ __IO uint64_t GICT_ERR4CTLR; /**< GICT_ERR4CTLR, offset: 0x108 */ __IO uint64_t GICT_ERR4STATUS; /**< GICT_ERR4STATUS, offset: 0x110 */ __I uint64_t GICT_ERR4ADDR; /**< GICT_ERR4ADDR, offset: 0x118 */ __IO uint64_t GICT_ERR4MISC0; /**< GICT_ERR4MISC0, offset: 0x120 */ __IO uint64_t GICT_ERR4MISC1; /**< GICT_ERR4MISC1, offset: 0x128 */ uint8_t RESERVED_4[16]; __I uint64_t GICT_ERR5FR; /**< GICT_ERR5FR, offset: 0x140 */ __IO uint64_t GICT_ERR5CTLR; /**< GICT_ERR5CTLR, offset: 0x148 */ __IO uint64_t GICT_ERR5STATUS; /**< GICT_ERR5STATUS, offset: 0x150 */ __I uint64_t GICT_ERR5ADDR; /**< GICT_ERR5ADDR, offset: 0x158 */ __IO uint64_t GICT_ERR5MISC0; /**< GICT_ERR5MISC0, offset: 0x160 */ __IO uint64_t GICT_ERR5MISC1; /**< GICT_ERR5MISC1, offset: 0x168 */ uint8_t RESERVED_5[16]; __I uint64_t GICT_ERR6FR; /**< GICT_ERR6FR, offset: 0x180 */ __IO uint64_t GICT_ERR6CTLR; /**< GICT_ERR6CTLR, offset: 0x188 */ __IO uint64_t GICT_ERR6STATUS; /**< GICT_ERR6STATUS, offset: 0x190 */ __I uint64_t GICT_ERR6ADDR; /**< GICT_ERR6ADDR, offset: 0x198 */ __IO uint64_t GICT_ERR6MISC0; /**< GICT_ERR6MISC0, offset: 0x1A0 */ __IO uint64_t GICT_ERR6MISC1; /**< GICT_ERR6MISC1, offset: 0x1A8 */ uint8_t RESERVED_6[16]; __I uint64_t GICT_ERR7FR; /**< GICT_ERR7FR, offset: 0x1C0 */ __IO uint64_t GICT_ERR7CTLR; /**< GICT_ERR7CTLR, offset: 0x1C8 */ __IO uint64_t GICT_ERR7STATUS; /**< GICT_ERR7STATUS, offset: 0x1D0 */ __I uint64_t GICT_ERR7ADDR; /**< GICT_ERR7ADDR, offset: 0x1D8 */ __IO uint64_t GICT_ERR7MISC0; /**< GICT_ERR7MISC0, offset: 0x1E0 */ __IO uint64_t GICT_ERR7MISC1; /**< GICT_ERR7MISC1, offset: 0x1E8 */ uint8_t RESERVED_7[16]; __I uint64_t GICT_ERR8FR; /**< GICT_ERR8FR, offset: 0x200 */ __IO uint64_t GICT_ERR8CTLR; /**< GICT_ERR8CTLR, offset: 0x208 */ __IO uint64_t GICT_ERR8STATUS; /**< GICT_ERR8STATUS, offset: 0x210 */ __I uint64_t GICT_ERR8ADDR; /**< GICT_ERR8ADDR, offset: 0x218 */ __IO uint64_t GICT_ERR8MISC0; /**< GICT_ERR8MISC0, offset: 0x220 */ __IO uint64_t GICT_ERR8MISC1; /**< GICT_ERR8MISC1, offset: 0x228 */ uint8_t RESERVED_8[16]; __I uint64_t GICT_ERR9FR; /**< GICT_ERR9FR, offset: 0x240 */ __IO uint64_t GICT_ERR9CTLR; /**< GICT_ERR9CTLR, offset: 0x248 */ __IO uint64_t GICT_ERR9STATUS; /**< GICT_ERR9STATUS, offset: 0x250 */ __I uint64_t GICT_ERR9ADDR; /**< GICT_ERR9ADDR, offset: 0x258 */ __IO uint64_t GICT_ERR9MISC0; /**< GICT_ERR9MISC0, offset: 0x260 */ __IO uint64_t GICT_ERR9MISC1; /**< GICT_ERR9MISC1, offset: 0x268 */ uint8_t RESERVED_9[16]; __I uint64_t GICT_ERR10FR; /**< GICT_ERR10FR, offset: 0x280 */ __IO uint64_t GICT_ERR10CTLR; /**< GICT_ERR10CTLR, offset: 0x288 */ __IO uint64_t GICT_ERR10STATUS; /**< GICT_ERR10STATUS, offset: 0x290 */ __I uint64_t GICT_ERR10ADDR; /**< GICT_ERR10ADDR, offset: 0x298 */ __IO uint64_t GICT_ERR10MISC0; /**< GICT_ERR10MISC0, offset: 0x2A0 */ __IO uint64_t GICT_ERR10MISC1; /**< GICT_ERR10MISC1, offset: 0x2A8 */ uint8_t RESERVED_10[16]; __I uint64_t GICT_ERR11FR; /**< GICT_ERR11FR, offset: 0x2C0 */ __IO uint64_t GICT_ERR11CTLR; /**< GICT_ERR11CTLR, offset: 0x2C8 */ __IO uint64_t GICT_ERR11STATUS; /**< GICT_ERR11STATUS, offset: 0x2D0 */ __I uint64_t GICT_ERR11ADDR; /**< GICT_ERR11ADDR, offset: 0x2D8 */ __IO uint64_t GICT_ERR11MISC0; /**< GICT_ERR11MISC0, offset: 0x2E0 */ __IO uint64_t GICT_ERR11MISC1; /**< GICT_ERR11MISC1, offset: 0x2E8 */ uint8_t RESERVED_11[16]; __I uint64_t GICT_ERR12FR; /**< GICT_ERR12FR, offset: 0x300 */ __IO uint64_t GICT_ERR12CTLR; /**< GICT_ERR12CTLR, offset: 0x308 */ __IO uint64_t GICT_ERR12STATUS; /**< GICT_ERR12STATUS, offset: 0x310 */ __I uint64_t GICT_ERR12ADDR; /**< GICT_ERR12ADDR, offset: 0x318 */ __IO uint64_t GICT_ERR12MISC0; /**< GICT_ERR12MISC0, offset: 0x320 */ __IO uint64_t GICT_ERR12MISC1; /**< GICT_ERR12MISC1, offset: 0x328 */ uint8_t RESERVED_12[16]; __I uint64_t GICT_ERR13FR; /**< GICT_ERR13FR, offset: 0x340 */ __IO uint64_t GICT_ERR13CTLR; /**< GICT_ERR13CTLR, offset: 0x348 */ __IO uint64_t GICT_ERR13STATUS; /**< GICT_ERR13STATUS, offset: 0x350 */ __I uint64_t GICT_ERR13ADDR; /**< GICT_ERR13ADDR, offset: 0x358 */ __IO uint64_t GICT_ERR13MISC0; /**< GICT_ERR13MISC0, offset: 0x360 */ __IO uint64_t GICT_ERR13MISC1; /**< GICT_ERR13MISC1, offset: 0x368 */ uint8_t RESERVED_13[16]; __I uint64_t GICT_ERR14FR; /**< GICT_ERR14FR, offset: 0x380 */ __IO uint64_t GICT_ERR14CTLR; /**< GICT_ERR14CTLR, offset: 0x388 */ __IO uint64_t GICT_ERR14STATUS; /**< GICT_ERR14STATUS, offset: 0x390 */ __I uint64_t GICT_ERR14ADDR; /**< GICT_ERR14ADDR, offset: 0x398 */ __IO uint64_t GICT_ERR14MISC0; /**< GICT_ERR14MISC0, offset: 0x3A0 */ __IO uint64_t GICT_ERR14MISC1; /**< GICT_ERR14MISC1, offset: 0x3A8 */ uint8_t RESERVED_14[16]; __I uint64_t GICT_ERR15FR; /**< GICT_ERR15FR, offset: 0x3C0 */ __I uint64_t GICT_ERR15CTLR; /**< GICT_ERR15CTLR, offset: 0x3C8 */ __I uint64_t GICT_ERR15STATUS; /**< GICT_ERR15STATUS, offset: 0x3D0 */ __I uint64_t GICT_ERR15ADDR; /**< GICT_ERR15ADDR, offset: 0x3D8 */ __I uint64_t GICT_ERR15MISC0; /**< GICT_ERR15MISC0, offset: 0x3E0 */ __I uint64_t GICT_ERR15MISC1; /**< GICT_ERR15MISC1, offset: 0x3E8 */ uint8_t RESERVED_15[16]; __I uint64_t GICT_ERR16FR; /**< GICT_ERR16FR, offset: 0x400 */ __I uint64_t GICT_ERR16CTLR; /**< GICT_ERR16CTLR, offset: 0x408 */ __I uint64_t GICT_ERR16STATUS; /**< GICT_ERR16STATUS, offset: 0x410 */ __I uint64_t GICT_ERR16ADDR; /**< GICT_ERR16ADDR, offset: 0x418 */ __I uint64_t GICT_ERR16MISC0; /**< GICT_ERR16MISC0, offset: 0x420 */ __I uint64_t GICT_ERR16MISC1; /**< GICT_ERR16MISC1, offset: 0x428 */ uint8_t RESERVED_16[16]; __I uint64_t GICT_ERR17FR; /**< GICT_ERR17FR, offset: 0x440 */ __I uint64_t GICT_ERR17CTLR; /**< GICT_ERR17CTLR, offset: 0x448 */ __I uint64_t GICT_ERR17STATUS; /**< GICT_ERR17STATUS, offset: 0x450 */ __I uint64_t GICT_ERR17ADDR; /**< GICT_ERR17ADDR, offset: 0x458 */ __I uint64_t GICT_ERR17MISC0; /**< GICT_ERR17MISC0, offset: 0x460 */ __I uint64_t GICT_ERR17MISC1; /**< GICT_ERR17MISC1, offset: 0x468 */ uint8_t RESERVED_17[16]; __I uint64_t GICT_ERR18FR; /**< GICT_ERR18FR, offset: 0x480 */ __I uint64_t GICT_ERR18CTLR; /**< GICT_ERR18CTLR, offset: 0x488 */ __I uint64_t GICT_ERR18STATUS; /**< GICT_ERR18STATUS, offset: 0x490 */ __I uint64_t GICT_ERR18ADDR; /**< GICT_ERR18ADDR, offset: 0x498 */ __I uint64_t GICT_ERR18MISC0; /**< GICT_ERR18MISC0, offset: 0x4A0 */ __I uint64_t GICT_ERR18MISC1; /**< GICT_ERR18MISC1, offset: 0x4A8 */ uint8_t RESERVED_18[16]; __I uint64_t GICT_ERR19FR; /**< GICT_ERR19FR, offset: 0x4C0 */ __I uint64_t GICT_ERR19CTLR; /**< GICT_ERR19CTLR, offset: 0x4C8 */ __I uint64_t GICT_ERR19STATUS; /**< GICT_ERR19STATUS, offset: 0x4D0 */ __I uint64_t GICT_ERR19ADDR; /**< GICT_ERR19ADDR, offset: 0x4D8 */ __I uint64_t GICT_ERR19MISC0; /**< GICT_ERR19MISC0, offset: 0x4E0 */ __I uint64_t GICT_ERR19MISC1; /**< GICT_ERR19MISC1, offset: 0x4E8 */ uint8_t RESERVED_19[16]; __I uint64_t GICT_ERR20FR; /**< GICT_ERR20FR, offset: 0x500 */ __I uint64_t GICT_ERR20CTLR; /**< GICT_ERR20CTLR, offset: 0x508 */ __I uint64_t GICT_ERR20STATUS; /**< GICT_ERR20STATUS, offset: 0x510 */ __I uint64_t GICT_ERR20ADDR; /**< GICT_ERR20ADDR, offset: 0x518 */ __I uint64_t GICT_ERR20MISC0; /**< GICT_ERR20MISC0, offset: 0x520 */ __I uint64_t GICT_ERR20MISC1; /**< GICT_ERR20MISC1, offset: 0x528 */ uint8_t RESERVED_20[16]; __I uint64_t GICT_ERR21FR; /**< GICT_ERR21FR, offset: 0x540 */ __I uint64_t GICT_ERR21CTLR; /**< GICT_ERR21CTLR, offset: 0x548 */ __I uint64_t GICT_ERR21STATUS; /**< GICT_ERR21STATUS, offset: 0x550 */ __I uint64_t GICT_ERR21ADDR; /**< GICT_ERR21ADDR, offset: 0x558 */ __I uint64_t GICT_ERR21MISC0; /**< GICT_ERR21MISC0, offset: 0x560 */ __I uint64_t GICT_ERR21MISC1; /**< GICT_ERR21MISC1, offset: 0x568 */ uint8_t RESERVED_21[16]; __I uint64_t GICT_ERR22FR; /**< GICT_ERR22FR, offset: 0x580 */ __I uint64_t GICT_ERR22CTLR; /**< GICT_ERR22CTLR, offset: 0x588 */ __I uint64_t GICT_ERR22STATUS; /**< GICT_ERR22STATUS, offset: 0x590 */ __I uint64_t GICT_ERR22ADDR; /**< GICT_ERR22ADDR, offset: 0x598 */ __I uint64_t GICT_ERR22MISC0; /**< GICT_ERR22MISC0, offset: 0x5A0 */ __I uint64_t GICT_ERR22MISC1; /**< GICT_ERR22MISC1, offset: 0x5A8 */ uint8_t RESERVED_22[16]; __I uint64_t GICT_ERR23FR; /**< GICT_ERR23FR, offset: 0x5C0 */ __I uint64_t GICT_ERR23CTLR; /**< GICT_ERR23CTLR, offset: 0x5C8 */ __I uint64_t GICT_ERR23STATUS; /**< GICT_ERR23STATUS, offset: 0x5D0 */ __I uint64_t GICT_ERR23ADDR; /**< GICT_ERR23ADDR, offset: 0x5D8 */ __I uint64_t GICT_ERR23MISC0; /**< GICT_ERR23MISC0, offset: 0x5E0 */ __I uint64_t GICT_ERR23MISC1; /**< GICT_ERR23MISC1, offset: 0x5E8 */ uint8_t RESERVED_23[16]; __I uint64_t GICT_ERR24FR; /**< GICT_ERR24FR, offset: 0x600 */ __I uint64_t GICT_ERR24CTLR; /**< GICT_ERR24CTLR, offset: 0x608 */ __I uint64_t GICT_ERR24STATUS; /**< GICT_ERR24STATUS, offset: 0x610 */ __I uint64_t GICT_ERR24ADDR; /**< GICT_ERR24ADDR, offset: 0x618 */ __I uint64_t GICT_ERR24MISC0; /**< GICT_ERR24MISC0, offset: 0x620 */ __I uint64_t GICT_ERR24MISC1; /**< GICT_ERR24MISC1, offset: 0x628 */ uint8_t RESERVED_24[16]; __I uint64_t GICT_ERR25FR; /**< GICT_ERR25FR, offset: 0x640 */ __IO uint64_t GICT_ERR25CTLR; /**< GICT_ERR25CTLR, offset: 0x648 */ __IO uint64_t GICT_ERR25STATUS; /**< GICT_ERR25STATUS, offset: 0x650 */ __I uint64_t GICT_ERR25ADDR; /**< GICT_ERR25ADDR, offset: 0x658 */ __IO uint64_t GICT_ERR25MISC0; /**< GICT_ERR25MISC0, offset: 0x660 */ __IO uint64_t GICT_ERR25MISC1; /**< GICT_ERR25MISC1, offset: 0x668 */ uint8_t RESERVED_25[16]; __I uint64_t GICT_ERR26FR; /**< GICT_ERR26FR, offset: 0x680 */ __IO uint64_t GICT_ERR26CTLR; /**< GICT_ERR26CTLR, offset: 0x688 */ __IO uint64_t GICT_ERR26STATUS; /**< GICT_ERR26STATUS, offset: 0x690 */ __I uint64_t GICT_ERR26ADDR; /**< GICT_ERR26ADDR, offset: 0x698 */ __IO uint64_t GICT_ERR26MISC0; /**< GICT_ERR26MISC0, offset: 0x6A0 */ __IO uint64_t GICT_ERR26MISC1; /**< GICT_ERR26MISC1, offset: 0x6A8 */ uint8_t RESERVED_26[16]; __I uint64_t GICT_ERR27FR; /**< GICT_ERR27FR, offset: 0x6C0 */ __IO uint64_t GICT_ERR27CTLR; /**< GICT_ERR27CTLR, offset: 0x6C8 */ __IO uint64_t GICT_ERR27STATUS; /**< GICT_ERR27STATUS, offset: 0x6D0 */ __I uint64_t GICT_ERR27ADDR; /**< GICT_ERR27ADDR, offset: 0x6D8 */ __IO uint64_t GICT_ERR27MISC0; /**< GICT_ERR27MISC0, offset: 0x6E0 */ __IO uint64_t GICT_ERR27MISC1; /**< GICT_ERR27MISC1, offset: 0x6E8 */ uint8_t RESERVED_27[55568]; __I uint64_t GICT_ERRGSR0; /**< GICT_ERRGSR0, offset: 0xE000 */ uint8_t RESERVED_28[2040]; __IO uint64_t GICT_ERRIRQCR0; /**< GICT_ERRIRQCR0, offset: 0xE800 */ __IO uint64_t GICT_ERRIRQCR1; /**< GICT_ERRIRQCR1, offset: 0xE808 */ uint8_t RESERVED_29[6060]; __I uint32_t GICT_DEVARCH; /**< GICT_DEVARCH, offset: 0xFFBC */ uint8_t RESERVED_30[8]; __I uint32_t GICT_DEVID; /**< GICT_DEVID, offset: 0xFFC8 */ uint8_t RESERVED_31[4]; __I uint32_t GICT_PIDR4; /**< GICT_PIDR4, offset: 0xFFD0 */ __I uint32_t GICT_PIDR5; /**< GICT_PIDR5, offset: 0xFFD4 */ __I uint32_t GICT_PIDR6; /**< GICT_PIDR6, offset: 0xFFD8 */ __I uint32_t GICT_PIDR7; /**< GICT_PIDR7, offset: 0xFFDC */ __I uint32_t GICT_PIDR0; /**< GICT_PIDR0, offset: 0xFFE0 */ __I uint32_t GICT_PIDR1; /**< GICT_PIDR1, offset: 0xFFE4 */ __I uint32_t GICT_PIDR2; /**< GICT_PIDR2, offset: 0xFFE8 */ __I uint32_t GICT_PIDR3; /**< GICT_PIDR3, offset: 0xFFEC */ __I uint32_t GICT_CIDR0; /**< GICT_CIDR0, offset: 0xFFF0 */ __I uint32_t GICT_CIDR1; /**< GICT_CIDR1, offset: 0xFFF4 */ __I uint32_t GICT_CIDR2; /**< GICT_CIDR2, offset: 0xFFF8 */ __I uint32_t GICT_CIDR3; /**< GICT_CIDR3, offset: 0xFFFC */ } NOC_GICT_Type; /* ---------------------------------------------------------------------------- -- NOC_GICT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GICT_Register_Masks NOC_GICT Register Masks * @{ */ /*! @name GICT_ERR0FR - GICT_ERR0FR */ /*! @{ */ #define NOC_GICT_GICT_ERR0FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR0FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR0FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_ED_SHIFT)) & NOC_GICT_GICT_ERR0FR_ED_MASK) #define NOC_GICT_GICT_ERR0FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR0FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR0FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_DE_SHIFT)) & NOC_GICT_GICT_ERR0FR_DE_MASK) #define NOC_GICT_GICT_ERR0FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR0FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR0FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_UI_SHIFT)) & NOC_GICT_GICT_ERR0FR_UI_MASK) #define NOC_GICT_GICT_ERR0FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR0FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR0FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_FI_SHIFT)) & NOC_GICT_GICT_ERR0FR_FI_MASK) #define NOC_GICT_GICT_ERR0FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR0FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR0FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_UE_SHIFT)) & NOC_GICT_GICT_ERR0FR_UE_MASK) #define NOC_GICT_GICT_ERR0FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR0FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR0FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR0FR_CFI_MASK) #define NOC_GICT_GICT_ERR0FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR0FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR0FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR0FR_CEC_MASK) #define NOC_GICT_GICT_ERR0FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR0FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR0FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_RP_SHIFT)) & NOC_GICT_GICT_ERR0FR_RP_MASK) #define NOC_GICT_GICT_ERR0FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR0FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR0FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR0FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR0CTLR - GICT_ERR0CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR0CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR0CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR0CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR0CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR0CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR0CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_UI_MASK) #define NOC_GICT_GICT_ERR0CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR0CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR0CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_FI_MASK) #define NOC_GICT_GICT_ERR0CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR0CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR0CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_UE_MASK) #define NOC_GICT_GICT_ERR0CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR0CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR0CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR0CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR0CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR0CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR0CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR0CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR0CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR0CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR0CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR0CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_RP_MASK) #define NOC_GICT_GICT_ERR0CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR0CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR0CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR0CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR0CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR0CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR0CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR0CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR0CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR0CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR0CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR0CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR0CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR0CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR0CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR0CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR0CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR0CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR0CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR0CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR0CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR0CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR0CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR0CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR0CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR0STATUS - GICT_ERR0STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR0STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR0STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR0STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR0STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR0STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR0STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR0STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR0STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR0STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR0STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR0STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR0STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_UET_MASK) #define NOC_GICT_GICT_ERR0STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR0STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR0STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR0STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR0STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR0STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_CE_MASK) #define NOC_GICT_GICT_ERR0STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR0STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR0STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_MV_MASK) #define NOC_GICT_GICT_ERR0STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR0STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR0STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_OF_MASK) #define NOC_GICT_GICT_ERR0STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR0STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR0STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_ER_MASK) #define NOC_GICT_GICT_ERR0STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR0STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR0STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_UE_MASK) #define NOC_GICT_GICT_ERR0STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR0STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR0STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_V_MASK) #define NOC_GICT_GICT_ERR0STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR0STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR0STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_AV_MASK) #define NOC_GICT_GICT_ERR0STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR0STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR0STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR0STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR0ADDR - GICT_ERR0ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR0ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR0ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR0ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR0ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR0ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR0ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR0ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR0ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR0ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR0ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR0ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR0ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR0MISC0 - GICT_ERR0MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR0MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR0MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR0MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR0MISC0_Data_MASK) #define NOC_GICT_GICT_ERR0MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR0MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR0MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR0MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR0MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR0MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR0MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR0MISC0_OF_MASK) #define NOC_GICT_GICT_ERR0MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR0MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR0MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR0MISC0_RE_MASK) #define NOC_GICT_GICT_ERR0MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR0MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR0MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR0MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR0MISC1 - GICT_ERR0MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR0MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR0MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR0MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR0MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR0MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR1FR - GICT_ERR1FR */ /*! @{ */ #define NOC_GICT_GICT_ERR1FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR1FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR1FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_ED_SHIFT)) & NOC_GICT_GICT_ERR1FR_ED_MASK) #define NOC_GICT_GICT_ERR1FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR1FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR1FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_DE_SHIFT)) & NOC_GICT_GICT_ERR1FR_DE_MASK) #define NOC_GICT_GICT_ERR1FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR1FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR1FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_UI_SHIFT)) & NOC_GICT_GICT_ERR1FR_UI_MASK) #define NOC_GICT_GICT_ERR1FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR1FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR1FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_FI_SHIFT)) & NOC_GICT_GICT_ERR1FR_FI_MASK) #define NOC_GICT_GICT_ERR1FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR1FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR1FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_UE_SHIFT)) & NOC_GICT_GICT_ERR1FR_UE_MASK) #define NOC_GICT_GICT_ERR1FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR1FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR1FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR1FR_CFI_MASK) #define NOC_GICT_GICT_ERR1FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR1FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR1FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR1FR_CEC_MASK) #define NOC_GICT_GICT_ERR1FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR1FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR1FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_RP_SHIFT)) & NOC_GICT_GICT_ERR1FR_RP_MASK) #define NOC_GICT_GICT_ERR1FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR1FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR1FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR1FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR1CTLR - GICT_ERR1CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR1CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR1CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR1CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR1CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR1CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR1CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_UI_MASK) #define NOC_GICT_GICT_ERR1CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR1CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR1CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_FI_MASK) #define NOC_GICT_GICT_ERR1CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR1CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR1CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_UE_MASK) #define NOC_GICT_GICT_ERR1CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR1CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR1CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR1CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR1CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR1CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR1CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR1CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR1CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR1CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR1CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR1CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_RP_MASK) #define NOC_GICT_GICT_ERR1CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR1CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR1CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR1CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR1CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR1CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR1CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR1CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR1CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR1CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR1CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR1CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR1CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR1CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR1CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR1CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR1CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR1CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR1CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR1CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR1CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR1CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR1CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR1CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR1CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR1STATUS - GICT_ERR1STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR1STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR1STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR1STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR1STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR1STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR1STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR1STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR1STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR1STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR1STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR1STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR1STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_UET_MASK) #define NOC_GICT_GICT_ERR1STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR1STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR1STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR1STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR1STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR1STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_CE_MASK) #define NOC_GICT_GICT_ERR1STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR1STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR1STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_MV_MASK) #define NOC_GICT_GICT_ERR1STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR1STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR1STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_OF_MASK) #define NOC_GICT_GICT_ERR1STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR1STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR1STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_ER_MASK) #define NOC_GICT_GICT_ERR1STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR1STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR1STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_UE_MASK) #define NOC_GICT_GICT_ERR1STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR1STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR1STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_V_MASK) #define NOC_GICT_GICT_ERR1STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR1STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR1STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_AV_MASK) #define NOC_GICT_GICT_ERR1STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR1STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR1STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR1STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR1ADDR - GICT_ERR1ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR1ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR1ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR1ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR1ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR1ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR1ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR1ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR1ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR1ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR1ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR1ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR1ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR1MISC0 - GICT_ERR1MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR1MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR1MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR1MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR1MISC0_Data_MASK) #define NOC_GICT_GICT_ERR1MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR1MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR1MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR1MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR1MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR1MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR1MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR1MISC0_OF_MASK) #define NOC_GICT_GICT_ERR1MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR1MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR1MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR1MISC0_RE_MASK) #define NOC_GICT_GICT_ERR1MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR1MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR1MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR1MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR1MISC1 - GICT_ERR1MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR1MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR1MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR1MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR1MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR1MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR2FR - GICT_ERR2FR */ /*! @{ */ #define NOC_GICT_GICT_ERR2FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR2FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR2FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_ED_SHIFT)) & NOC_GICT_GICT_ERR2FR_ED_MASK) #define NOC_GICT_GICT_ERR2FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR2FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR2FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_DE_SHIFT)) & NOC_GICT_GICT_ERR2FR_DE_MASK) #define NOC_GICT_GICT_ERR2FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR2FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR2FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_UI_SHIFT)) & NOC_GICT_GICT_ERR2FR_UI_MASK) #define NOC_GICT_GICT_ERR2FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR2FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR2FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_FI_SHIFT)) & NOC_GICT_GICT_ERR2FR_FI_MASK) #define NOC_GICT_GICT_ERR2FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR2FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR2FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_UE_SHIFT)) & NOC_GICT_GICT_ERR2FR_UE_MASK) #define NOC_GICT_GICT_ERR2FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR2FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR2FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR2FR_CFI_MASK) #define NOC_GICT_GICT_ERR2FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR2FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR2FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR2FR_CEC_MASK) #define NOC_GICT_GICT_ERR2FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR2FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR2FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_RP_SHIFT)) & NOC_GICT_GICT_ERR2FR_RP_MASK) #define NOC_GICT_GICT_ERR2FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR2FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR2FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR2FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR2CTLR - GICT_ERR2CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR2CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR2CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR2CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR2CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR2CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR2CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_UI_MASK) #define NOC_GICT_GICT_ERR2CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR2CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR2CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_FI_MASK) #define NOC_GICT_GICT_ERR2CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR2CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR2CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_UE_MASK) #define NOC_GICT_GICT_ERR2CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR2CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR2CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR2CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR2CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR2CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR2CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR2CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR2CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR2CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR2CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR2CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_RP_MASK) #define NOC_GICT_GICT_ERR2CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR2CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR2CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR2CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR2CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR2CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR2CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR2CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR2CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR2CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR2CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR2CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR2CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR2CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR2CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR2CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR2CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR2CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR2CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR2CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR2CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR2CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR2CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR2CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR2CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR2STATUS - GICT_ERR2STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR2STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR2STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR2STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR2STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR2STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR2STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR2STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR2STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR2STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR2STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR2STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR2STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_UET_MASK) #define NOC_GICT_GICT_ERR2STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR2STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR2STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR2STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR2STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR2STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_CE_MASK) #define NOC_GICT_GICT_ERR2STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR2STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR2STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_MV_MASK) #define NOC_GICT_GICT_ERR2STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR2STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR2STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_OF_MASK) #define NOC_GICT_GICT_ERR2STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR2STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR2STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_ER_MASK) #define NOC_GICT_GICT_ERR2STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR2STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR2STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_UE_MASK) #define NOC_GICT_GICT_ERR2STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR2STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR2STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_V_MASK) #define NOC_GICT_GICT_ERR2STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR2STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR2STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_AV_MASK) #define NOC_GICT_GICT_ERR2STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR2STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR2STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR2STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR2ADDR - GICT_ERR2ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR2ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR2ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR2ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR2ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR2ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR2ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR2ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR2ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR2ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR2ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR2ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR2ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR2MISC0 - GICT_ERR2MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR2MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR2MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR2MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR2MISC0_Data_MASK) #define NOC_GICT_GICT_ERR2MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR2MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR2MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR2MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR2MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR2MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR2MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR2MISC0_OF_MASK) #define NOC_GICT_GICT_ERR2MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR2MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR2MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR2MISC0_RE_MASK) #define NOC_GICT_GICT_ERR2MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR2MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR2MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR2MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR2MISC1 - GICT_ERR2MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR2MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR2MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR2MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR2MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR2MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR3FR - GICT_ERR3FR */ /*! @{ */ #define NOC_GICT_GICT_ERR3FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR3FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR3FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_ED_SHIFT)) & NOC_GICT_GICT_ERR3FR_ED_MASK) #define NOC_GICT_GICT_ERR3FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR3FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR3FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_DE_SHIFT)) & NOC_GICT_GICT_ERR3FR_DE_MASK) #define NOC_GICT_GICT_ERR3FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR3FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR3FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_UI_SHIFT)) & NOC_GICT_GICT_ERR3FR_UI_MASK) #define NOC_GICT_GICT_ERR3FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR3FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR3FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_FI_SHIFT)) & NOC_GICT_GICT_ERR3FR_FI_MASK) #define NOC_GICT_GICT_ERR3FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR3FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR3FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_UE_SHIFT)) & NOC_GICT_GICT_ERR3FR_UE_MASK) #define NOC_GICT_GICT_ERR3FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR3FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR3FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR3FR_CFI_MASK) #define NOC_GICT_GICT_ERR3FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR3FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR3FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR3FR_CEC_MASK) #define NOC_GICT_GICT_ERR3FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR3FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR3FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_RP_SHIFT)) & NOC_GICT_GICT_ERR3FR_RP_MASK) #define NOC_GICT_GICT_ERR3FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR3FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR3FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR3FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR3CTLR - GICT_ERR3CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR3CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR3CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR3CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR3CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR3CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR3CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_UI_MASK) #define NOC_GICT_GICT_ERR3CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR3CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR3CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_FI_MASK) #define NOC_GICT_GICT_ERR3CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR3CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR3CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_UE_MASK) #define NOC_GICT_GICT_ERR3CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR3CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR3CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR3CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR3CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR3CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR3CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR3CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR3CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR3CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR3CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR3CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_RP_MASK) #define NOC_GICT_GICT_ERR3CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR3CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR3CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR3CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR3CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR3CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR3CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR3CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR3CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR3CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR3CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR3CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR3CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR3CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR3CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR3CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR3CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR3CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR3CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR3CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR3CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR3CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR3CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR3CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR3CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR3STATUS - GICT_ERR3STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR3STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR3STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR3STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR3STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR3STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR3STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR3STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR3STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR3STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR3STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR3STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR3STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_UET_MASK) #define NOC_GICT_GICT_ERR3STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR3STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR3STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR3STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR3STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR3STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_CE_MASK) #define NOC_GICT_GICT_ERR3STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR3STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR3STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_MV_MASK) #define NOC_GICT_GICT_ERR3STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR3STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR3STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_OF_MASK) #define NOC_GICT_GICT_ERR3STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR3STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR3STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_ER_MASK) #define NOC_GICT_GICT_ERR3STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR3STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR3STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_UE_MASK) #define NOC_GICT_GICT_ERR3STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR3STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR3STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_V_MASK) #define NOC_GICT_GICT_ERR3STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR3STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR3STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_AV_MASK) #define NOC_GICT_GICT_ERR3STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR3STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR3STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR3STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR3ADDR - GICT_ERR3ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR3ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR3ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR3ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR3ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR3ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR3ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR3ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR3ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR3ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR3ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR3ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR3ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR3MISC0 - GICT_ERR3MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR3MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR3MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR3MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR3MISC0_Data_MASK) #define NOC_GICT_GICT_ERR3MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR3MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR3MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR3MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR3MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR3MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR3MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR3MISC0_OF_MASK) #define NOC_GICT_GICT_ERR3MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR3MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR3MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR3MISC0_RE_MASK) #define NOC_GICT_GICT_ERR3MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR3MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR3MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR3MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR3MISC1 - GICT_ERR3MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR3MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR3MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR3MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR3MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR3MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR4FR - GICT_ERR4FR */ /*! @{ */ #define NOC_GICT_GICT_ERR4FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR4FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR4FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_ED_SHIFT)) & NOC_GICT_GICT_ERR4FR_ED_MASK) #define NOC_GICT_GICT_ERR4FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR4FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR4FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_DE_SHIFT)) & NOC_GICT_GICT_ERR4FR_DE_MASK) #define NOC_GICT_GICT_ERR4FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR4FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR4FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_UI_SHIFT)) & NOC_GICT_GICT_ERR4FR_UI_MASK) #define NOC_GICT_GICT_ERR4FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR4FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR4FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_FI_SHIFT)) & NOC_GICT_GICT_ERR4FR_FI_MASK) #define NOC_GICT_GICT_ERR4FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR4FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR4FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_UE_SHIFT)) & NOC_GICT_GICT_ERR4FR_UE_MASK) #define NOC_GICT_GICT_ERR4FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR4FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR4FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR4FR_CFI_MASK) #define NOC_GICT_GICT_ERR4FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR4FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR4FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR4FR_CEC_MASK) #define NOC_GICT_GICT_ERR4FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR4FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR4FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_RP_SHIFT)) & NOC_GICT_GICT_ERR4FR_RP_MASK) #define NOC_GICT_GICT_ERR4FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR4FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR4FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR4FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR4CTLR - GICT_ERR4CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR4CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR4CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR4CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR4CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR4CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR4CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_UI_MASK) #define NOC_GICT_GICT_ERR4CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR4CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR4CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_FI_MASK) #define NOC_GICT_GICT_ERR4CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR4CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR4CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_UE_MASK) #define NOC_GICT_GICT_ERR4CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR4CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR4CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR4CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR4CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR4CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR4CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR4CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR4CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR4CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR4CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR4CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_RP_MASK) #define NOC_GICT_GICT_ERR4CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR4CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR4CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR4CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR4CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR4CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR4CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR4CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR4CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR4CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR4CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR4CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR4CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR4CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR4CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR4CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR4CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR4CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR4CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR4CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR4CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR4CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR4CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR4CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR4CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR4STATUS - GICT_ERR4STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR4STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR4STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR4STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR4STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR4STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR4STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR4STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR4STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR4STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR4STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR4STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR4STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_UET_MASK) #define NOC_GICT_GICT_ERR4STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR4STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR4STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR4STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR4STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR4STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_CE_MASK) #define NOC_GICT_GICT_ERR4STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR4STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR4STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_MV_MASK) #define NOC_GICT_GICT_ERR4STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR4STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR4STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_OF_MASK) #define NOC_GICT_GICT_ERR4STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR4STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR4STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_ER_MASK) #define NOC_GICT_GICT_ERR4STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR4STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR4STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_UE_MASK) #define NOC_GICT_GICT_ERR4STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR4STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR4STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_V_MASK) #define NOC_GICT_GICT_ERR4STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR4STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR4STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_AV_MASK) #define NOC_GICT_GICT_ERR4STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR4STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR4STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR4STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR4ADDR - GICT_ERR4ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR4ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR4ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR4ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR4ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR4ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR4ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR4ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR4ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR4ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR4ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR4ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR4ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR4MISC0 - GICT_ERR4MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR4MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR4MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR4MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR4MISC0_Data_MASK) #define NOC_GICT_GICT_ERR4MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR4MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR4MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR4MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR4MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR4MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR4MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR4MISC0_OF_MASK) #define NOC_GICT_GICT_ERR4MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR4MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR4MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR4MISC0_RE_MASK) #define NOC_GICT_GICT_ERR4MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR4MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR4MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR4MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR4MISC1 - GICT_ERR4MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR4MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR4MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR4MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR4MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR4MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR5FR - GICT_ERR5FR */ /*! @{ */ #define NOC_GICT_GICT_ERR5FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR5FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR5FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_ED_SHIFT)) & NOC_GICT_GICT_ERR5FR_ED_MASK) #define NOC_GICT_GICT_ERR5FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR5FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR5FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_DE_SHIFT)) & NOC_GICT_GICT_ERR5FR_DE_MASK) #define NOC_GICT_GICT_ERR5FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR5FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR5FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_UI_SHIFT)) & NOC_GICT_GICT_ERR5FR_UI_MASK) #define NOC_GICT_GICT_ERR5FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR5FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR5FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_FI_SHIFT)) & NOC_GICT_GICT_ERR5FR_FI_MASK) #define NOC_GICT_GICT_ERR5FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR5FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR5FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_UE_SHIFT)) & NOC_GICT_GICT_ERR5FR_UE_MASK) #define NOC_GICT_GICT_ERR5FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR5FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR5FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR5FR_CFI_MASK) #define NOC_GICT_GICT_ERR5FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR5FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR5FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR5FR_CEC_MASK) #define NOC_GICT_GICT_ERR5FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR5FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR5FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_RP_SHIFT)) & NOC_GICT_GICT_ERR5FR_RP_MASK) #define NOC_GICT_GICT_ERR5FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR5FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR5FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR5FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR5CTLR - GICT_ERR5CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR5CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR5CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR5CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR5CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR5CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR5CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_UI_MASK) #define NOC_GICT_GICT_ERR5CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR5CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR5CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_FI_MASK) #define NOC_GICT_GICT_ERR5CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR5CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR5CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_UE_MASK) #define NOC_GICT_GICT_ERR5CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR5CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR5CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR5CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR5CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR5CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR5CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR5CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR5CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR5CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR5CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR5CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_RP_MASK) #define NOC_GICT_GICT_ERR5CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR5CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR5CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR5CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR5CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR5CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR5CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR5CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR5CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR5CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR5CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR5CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR5CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR5CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR5CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR5CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR5CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR5CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR5CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR5CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR5CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR5CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR5CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR5CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR5CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR5STATUS - GICT_ERR5STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR5STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR5STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR5STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR5STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR5STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR5STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR5STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR5STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR5STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR5STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR5STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR5STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_UET_MASK) #define NOC_GICT_GICT_ERR5STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR5STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR5STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR5STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR5STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR5STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_CE_MASK) #define NOC_GICT_GICT_ERR5STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR5STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR5STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_MV_MASK) #define NOC_GICT_GICT_ERR5STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR5STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR5STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_OF_MASK) #define NOC_GICT_GICT_ERR5STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR5STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR5STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_ER_MASK) #define NOC_GICT_GICT_ERR5STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR5STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR5STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_UE_MASK) #define NOC_GICT_GICT_ERR5STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR5STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR5STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_V_MASK) #define NOC_GICT_GICT_ERR5STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR5STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR5STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_AV_MASK) #define NOC_GICT_GICT_ERR5STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR5STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR5STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR5STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR5ADDR - GICT_ERR5ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR5ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR5ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR5ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR5ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR5ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR5ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR5ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR5ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR5ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR5ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR5ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR5ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR5MISC0 - GICT_ERR5MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR5MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR5MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR5MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR5MISC0_Data_MASK) #define NOC_GICT_GICT_ERR5MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR5MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR5MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR5MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR5MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR5MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR5MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR5MISC0_OF_MASK) #define NOC_GICT_GICT_ERR5MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR5MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR5MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR5MISC0_RE_MASK) #define NOC_GICT_GICT_ERR5MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR5MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR5MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR5MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR5MISC1 - GICT_ERR5MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR5MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR5MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR5MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR5MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR5MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR6FR - GICT_ERR6FR */ /*! @{ */ #define NOC_GICT_GICT_ERR6FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR6FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR6FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_ED_SHIFT)) & NOC_GICT_GICT_ERR6FR_ED_MASK) #define NOC_GICT_GICT_ERR6FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR6FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR6FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_DE_SHIFT)) & NOC_GICT_GICT_ERR6FR_DE_MASK) #define NOC_GICT_GICT_ERR6FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR6FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR6FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_UI_SHIFT)) & NOC_GICT_GICT_ERR6FR_UI_MASK) #define NOC_GICT_GICT_ERR6FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR6FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR6FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_FI_SHIFT)) & NOC_GICT_GICT_ERR6FR_FI_MASK) #define NOC_GICT_GICT_ERR6FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR6FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR6FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_UE_SHIFT)) & NOC_GICT_GICT_ERR6FR_UE_MASK) #define NOC_GICT_GICT_ERR6FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR6FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR6FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR6FR_CFI_MASK) #define NOC_GICT_GICT_ERR6FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR6FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR6FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR6FR_CEC_MASK) #define NOC_GICT_GICT_ERR6FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR6FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR6FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_RP_SHIFT)) & NOC_GICT_GICT_ERR6FR_RP_MASK) #define NOC_GICT_GICT_ERR6FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR6FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR6FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR6FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR6CTLR - GICT_ERR6CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR6CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR6CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR6CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR6CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR6CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR6CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_UI_MASK) #define NOC_GICT_GICT_ERR6CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR6CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR6CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_FI_MASK) #define NOC_GICT_GICT_ERR6CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR6CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR6CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_UE_MASK) #define NOC_GICT_GICT_ERR6CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR6CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR6CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR6CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR6CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR6CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR6CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR6CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR6CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR6CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR6CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR6CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_RP_MASK) #define NOC_GICT_GICT_ERR6CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR6CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR6CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR6CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR6CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR6CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR6CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR6CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR6CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR6CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR6CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR6CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR6CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR6CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR6CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR6CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR6CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR6CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR6CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR6CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR6CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR6CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR6CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR6CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR6CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR6STATUS - GICT_ERR6STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR6STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR6STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR6STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR6STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR6STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR6STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR6STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR6STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR6STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR6STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR6STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR6STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_UET_MASK) #define NOC_GICT_GICT_ERR6STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR6STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR6STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR6STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR6STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR6STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_CE_MASK) #define NOC_GICT_GICT_ERR6STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR6STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR6STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_MV_MASK) #define NOC_GICT_GICT_ERR6STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR6STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR6STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_OF_MASK) #define NOC_GICT_GICT_ERR6STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR6STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR6STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_ER_MASK) #define NOC_GICT_GICT_ERR6STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR6STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR6STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_UE_MASK) #define NOC_GICT_GICT_ERR6STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR6STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR6STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_V_MASK) #define NOC_GICT_GICT_ERR6STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR6STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR6STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_AV_MASK) #define NOC_GICT_GICT_ERR6STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR6STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR6STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR6STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR6ADDR - GICT_ERR6ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR6ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR6ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR6ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR6ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR6ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR6ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR6ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR6ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR6ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR6ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR6ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR6ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR6MISC0 - GICT_ERR6MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR6MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR6MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR6MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR6MISC0_Data_MASK) #define NOC_GICT_GICT_ERR6MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR6MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR6MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR6MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR6MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR6MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR6MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR6MISC0_OF_MASK) #define NOC_GICT_GICT_ERR6MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR6MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR6MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR6MISC0_RE_MASK) #define NOC_GICT_GICT_ERR6MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR6MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR6MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR6MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR6MISC1 - GICT_ERR6MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR6MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR6MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR6MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR6MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR6MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR7FR - GICT_ERR7FR */ /*! @{ */ #define NOC_GICT_GICT_ERR7FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR7FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR7FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_ED_SHIFT)) & NOC_GICT_GICT_ERR7FR_ED_MASK) #define NOC_GICT_GICT_ERR7FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR7FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR7FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_DE_SHIFT)) & NOC_GICT_GICT_ERR7FR_DE_MASK) #define NOC_GICT_GICT_ERR7FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR7FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR7FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_UI_SHIFT)) & NOC_GICT_GICT_ERR7FR_UI_MASK) #define NOC_GICT_GICT_ERR7FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR7FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR7FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_FI_SHIFT)) & NOC_GICT_GICT_ERR7FR_FI_MASK) #define NOC_GICT_GICT_ERR7FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR7FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR7FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_UE_SHIFT)) & NOC_GICT_GICT_ERR7FR_UE_MASK) #define NOC_GICT_GICT_ERR7FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR7FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR7FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR7FR_CFI_MASK) #define NOC_GICT_GICT_ERR7FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR7FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR7FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR7FR_CEC_MASK) #define NOC_GICT_GICT_ERR7FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR7FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR7FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_RP_SHIFT)) & NOC_GICT_GICT_ERR7FR_RP_MASK) #define NOC_GICT_GICT_ERR7FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR7FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR7FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR7FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR7CTLR - GICT_ERR7CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR7CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR7CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR7CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR7CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR7CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR7CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_UI_MASK) #define NOC_GICT_GICT_ERR7CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR7CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR7CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_FI_MASK) #define NOC_GICT_GICT_ERR7CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR7CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR7CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_UE_MASK) #define NOC_GICT_GICT_ERR7CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR7CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR7CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR7CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR7CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR7CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR7CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR7CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR7CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR7CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR7CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR7CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_RP_MASK) #define NOC_GICT_GICT_ERR7CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR7CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR7CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR7CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR7CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR7CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR7CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR7CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR7CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR7CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR7CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR7CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR7CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR7CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR7CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR7CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR7CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR7CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR7CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR7CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR7CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR7CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR7CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR7CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR7CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR7STATUS - GICT_ERR7STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR7STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR7STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR7STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR7STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR7STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR7STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR7STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR7STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR7STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR7STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR7STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR7STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_UET_MASK) #define NOC_GICT_GICT_ERR7STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR7STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR7STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR7STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR7STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR7STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_CE_MASK) #define NOC_GICT_GICT_ERR7STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR7STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR7STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_MV_MASK) #define NOC_GICT_GICT_ERR7STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR7STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR7STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_OF_MASK) #define NOC_GICT_GICT_ERR7STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR7STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR7STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_ER_MASK) #define NOC_GICT_GICT_ERR7STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR7STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR7STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_UE_MASK) #define NOC_GICT_GICT_ERR7STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR7STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR7STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_V_MASK) #define NOC_GICT_GICT_ERR7STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR7STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR7STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_AV_MASK) #define NOC_GICT_GICT_ERR7STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR7STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR7STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR7STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR7ADDR - GICT_ERR7ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR7ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR7ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR7ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR7ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR7ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR7ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR7ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR7ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR7ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR7ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR7ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR7ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR7MISC0 - GICT_ERR7MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR7MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR7MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR7MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR7MISC0_Data_MASK) #define NOC_GICT_GICT_ERR7MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR7MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR7MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR7MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR7MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR7MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR7MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR7MISC0_OF_MASK) #define NOC_GICT_GICT_ERR7MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR7MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR7MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR7MISC0_RE_MASK) #define NOC_GICT_GICT_ERR7MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR7MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR7MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR7MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR7MISC1 - GICT_ERR7MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR7MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR7MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR7MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR7MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR7MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR8FR - GICT_ERR8FR */ /*! @{ */ #define NOC_GICT_GICT_ERR8FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR8FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR8FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_ED_SHIFT)) & NOC_GICT_GICT_ERR8FR_ED_MASK) #define NOC_GICT_GICT_ERR8FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR8FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR8FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_DE_SHIFT)) & NOC_GICT_GICT_ERR8FR_DE_MASK) #define NOC_GICT_GICT_ERR8FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR8FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR8FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_UI_SHIFT)) & NOC_GICT_GICT_ERR8FR_UI_MASK) #define NOC_GICT_GICT_ERR8FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR8FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR8FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_FI_SHIFT)) & NOC_GICT_GICT_ERR8FR_FI_MASK) #define NOC_GICT_GICT_ERR8FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR8FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR8FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_UE_SHIFT)) & NOC_GICT_GICT_ERR8FR_UE_MASK) #define NOC_GICT_GICT_ERR8FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR8FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR8FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR8FR_CFI_MASK) #define NOC_GICT_GICT_ERR8FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR8FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR8FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR8FR_CEC_MASK) #define NOC_GICT_GICT_ERR8FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR8FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR8FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_RP_SHIFT)) & NOC_GICT_GICT_ERR8FR_RP_MASK) #define NOC_GICT_GICT_ERR8FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR8FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR8FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR8FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR8CTLR - GICT_ERR8CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR8CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR8CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR8CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR8CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR8CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR8CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_UI_MASK) #define NOC_GICT_GICT_ERR8CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR8CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR8CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_FI_MASK) #define NOC_GICT_GICT_ERR8CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR8CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR8CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_UE_MASK) #define NOC_GICT_GICT_ERR8CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR8CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR8CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR8CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR8CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR8CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR8CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR8CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR8CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR8CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR8CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR8CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_RP_MASK) #define NOC_GICT_GICT_ERR8CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR8CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR8CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR8CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR8CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR8CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR8CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR8CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR8CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR8CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR8CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR8CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR8CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR8CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR8CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR8CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR8CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR8CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR8CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR8CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR8CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR8CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR8CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR8CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR8CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR8STATUS - GICT_ERR8STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR8STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR8STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR8STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR8STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR8STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR8STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR8STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR8STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR8STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR8STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR8STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR8STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_UET_MASK) #define NOC_GICT_GICT_ERR8STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR8STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR8STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR8STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR8STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR8STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_CE_MASK) #define NOC_GICT_GICT_ERR8STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR8STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR8STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_MV_MASK) #define NOC_GICT_GICT_ERR8STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR8STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR8STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_OF_MASK) #define NOC_GICT_GICT_ERR8STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR8STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR8STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_ER_MASK) #define NOC_GICT_GICT_ERR8STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR8STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR8STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_UE_MASK) #define NOC_GICT_GICT_ERR8STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR8STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR8STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_V_MASK) #define NOC_GICT_GICT_ERR8STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR8STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR8STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_AV_MASK) #define NOC_GICT_GICT_ERR8STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR8STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR8STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR8STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR8ADDR - GICT_ERR8ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR8ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR8ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR8ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR8ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR8ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR8ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR8ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR8ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR8ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR8ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR8ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR8ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR8MISC0 - GICT_ERR8MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR8MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR8MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR8MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR8MISC0_Data_MASK) #define NOC_GICT_GICT_ERR8MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR8MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR8MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR8MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR8MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR8MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR8MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR8MISC0_OF_MASK) #define NOC_GICT_GICT_ERR8MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR8MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR8MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR8MISC0_RE_MASK) #define NOC_GICT_GICT_ERR8MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR8MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR8MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR8MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR8MISC1 - GICT_ERR8MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR8MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR8MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR8MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR8MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR8MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR9FR - GICT_ERR9FR */ /*! @{ */ #define NOC_GICT_GICT_ERR9FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR9FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR9FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_ED_SHIFT)) & NOC_GICT_GICT_ERR9FR_ED_MASK) #define NOC_GICT_GICT_ERR9FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR9FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR9FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_DE_SHIFT)) & NOC_GICT_GICT_ERR9FR_DE_MASK) #define NOC_GICT_GICT_ERR9FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR9FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR9FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_UI_SHIFT)) & NOC_GICT_GICT_ERR9FR_UI_MASK) #define NOC_GICT_GICT_ERR9FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR9FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR9FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_FI_SHIFT)) & NOC_GICT_GICT_ERR9FR_FI_MASK) #define NOC_GICT_GICT_ERR9FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR9FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR9FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_UE_SHIFT)) & NOC_GICT_GICT_ERR9FR_UE_MASK) #define NOC_GICT_GICT_ERR9FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR9FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR9FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR9FR_CFI_MASK) #define NOC_GICT_GICT_ERR9FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR9FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR9FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR9FR_CEC_MASK) #define NOC_GICT_GICT_ERR9FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR9FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR9FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_RP_SHIFT)) & NOC_GICT_GICT_ERR9FR_RP_MASK) #define NOC_GICT_GICT_ERR9FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR9FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR9FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR9FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR9CTLR - GICT_ERR9CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR9CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR9CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR9CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR9CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR9CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR9CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_UI_MASK) #define NOC_GICT_GICT_ERR9CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR9CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR9CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_FI_MASK) #define NOC_GICT_GICT_ERR9CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR9CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR9CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_UE_MASK) #define NOC_GICT_GICT_ERR9CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR9CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR9CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR9CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR9CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR9CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR9CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR9CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR9CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR9CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR9CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR9CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_RP_MASK) #define NOC_GICT_GICT_ERR9CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR9CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR9CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR9CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR9CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR9CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR9CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR9CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR9CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR9CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR9CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR9CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR9CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR9CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR9CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR9CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR9CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR9CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR9CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR9CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR9CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR9CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR9CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR9CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR9CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR9STATUS - GICT_ERR9STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR9STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR9STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR9STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR9STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR9STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR9STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR9STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR9STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR9STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR9STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR9STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR9STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_UET_MASK) #define NOC_GICT_GICT_ERR9STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR9STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR9STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR9STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR9STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR9STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_CE_MASK) #define NOC_GICT_GICT_ERR9STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR9STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR9STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_MV_MASK) #define NOC_GICT_GICT_ERR9STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR9STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR9STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_OF_MASK) #define NOC_GICT_GICT_ERR9STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR9STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR9STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_ER_MASK) #define NOC_GICT_GICT_ERR9STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR9STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR9STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_UE_MASK) #define NOC_GICT_GICT_ERR9STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR9STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR9STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_V_MASK) #define NOC_GICT_GICT_ERR9STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR9STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR9STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_AV_MASK) #define NOC_GICT_GICT_ERR9STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR9STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR9STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR9STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR9ADDR - GICT_ERR9ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR9ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR9ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR9ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR9ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR9ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR9ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR9ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR9ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR9ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR9ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR9ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR9ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR9MISC0 - GICT_ERR9MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR9MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR9MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR9MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR9MISC0_Data_MASK) #define NOC_GICT_GICT_ERR9MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR9MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR9MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR9MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR9MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR9MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR9MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR9MISC0_OF_MASK) #define NOC_GICT_GICT_ERR9MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR9MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR9MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR9MISC0_RE_MASK) #define NOC_GICT_GICT_ERR9MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR9MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR9MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR9MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR9MISC1 - GICT_ERR9MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR9MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR9MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR9MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR9MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR9MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR10FR - GICT_ERR10FR */ /*! @{ */ #define NOC_GICT_GICT_ERR10FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR10FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR10FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_ED_SHIFT)) & NOC_GICT_GICT_ERR10FR_ED_MASK) #define NOC_GICT_GICT_ERR10FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR10FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR10FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_DE_SHIFT)) & NOC_GICT_GICT_ERR10FR_DE_MASK) #define NOC_GICT_GICT_ERR10FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR10FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR10FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_UI_SHIFT)) & NOC_GICT_GICT_ERR10FR_UI_MASK) #define NOC_GICT_GICT_ERR10FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR10FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR10FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_FI_SHIFT)) & NOC_GICT_GICT_ERR10FR_FI_MASK) #define NOC_GICT_GICT_ERR10FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR10FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR10FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_UE_SHIFT)) & NOC_GICT_GICT_ERR10FR_UE_MASK) #define NOC_GICT_GICT_ERR10FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR10FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR10FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR10FR_CFI_MASK) #define NOC_GICT_GICT_ERR10FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR10FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR10FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR10FR_CEC_MASK) #define NOC_GICT_GICT_ERR10FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR10FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR10FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_RP_SHIFT)) & NOC_GICT_GICT_ERR10FR_RP_MASK) #define NOC_GICT_GICT_ERR10FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR10FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR10FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR10FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR10CTLR - GICT_ERR10CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR10CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR10CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR10CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR10CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR10CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR10CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_UI_MASK) #define NOC_GICT_GICT_ERR10CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR10CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR10CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_FI_MASK) #define NOC_GICT_GICT_ERR10CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR10CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR10CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_UE_MASK) #define NOC_GICT_GICT_ERR10CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR10CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR10CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR10CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR10CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR10CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR10CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR10CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR10CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR10CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR10CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR10CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_RP_MASK) #define NOC_GICT_GICT_ERR10CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR10CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR10CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR10CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR10CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR10CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR10CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR10CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR10CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR10CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR10CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR10CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR10CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR10CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR10CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR10CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR10CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR10CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR10CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR10CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR10CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR10CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR10CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR10CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR10CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR10STATUS - GICT_ERR10STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR10STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR10STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR10STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR10STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR10STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR10STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR10STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR10STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR10STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR10STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR10STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR10STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_UET_MASK) #define NOC_GICT_GICT_ERR10STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR10STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR10STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR10STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR10STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR10STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_CE_MASK) #define NOC_GICT_GICT_ERR10STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR10STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR10STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_MV_MASK) #define NOC_GICT_GICT_ERR10STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR10STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR10STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_OF_MASK) #define NOC_GICT_GICT_ERR10STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR10STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR10STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_ER_MASK) #define NOC_GICT_GICT_ERR10STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR10STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR10STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_UE_MASK) #define NOC_GICT_GICT_ERR10STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR10STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR10STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_V_MASK) #define NOC_GICT_GICT_ERR10STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR10STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR10STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_AV_MASK) #define NOC_GICT_GICT_ERR10STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR10STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR10STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR10STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR10ADDR - GICT_ERR10ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR10ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR10ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR10ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR10ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR10ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR10ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR10ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR10ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR10ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR10ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR10ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR10ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR10MISC0 - GICT_ERR10MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR10MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR10MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR10MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR10MISC0_Data_MASK) #define NOC_GICT_GICT_ERR10MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR10MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR10MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR10MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR10MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR10MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR10MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR10MISC0_OF_MASK) #define NOC_GICT_GICT_ERR10MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR10MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR10MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR10MISC0_RE_MASK) #define NOC_GICT_GICT_ERR10MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR10MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR10MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR10MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR10MISC1 - GICT_ERR10MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR10MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR10MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR10MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR10MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR10MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR11FR - GICT_ERR11FR */ /*! @{ */ #define NOC_GICT_GICT_ERR11FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR11FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR11FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_ED_SHIFT)) & NOC_GICT_GICT_ERR11FR_ED_MASK) #define NOC_GICT_GICT_ERR11FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR11FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR11FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_DE_SHIFT)) & NOC_GICT_GICT_ERR11FR_DE_MASK) #define NOC_GICT_GICT_ERR11FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR11FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR11FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_UI_SHIFT)) & NOC_GICT_GICT_ERR11FR_UI_MASK) #define NOC_GICT_GICT_ERR11FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR11FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR11FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_FI_SHIFT)) & NOC_GICT_GICT_ERR11FR_FI_MASK) #define NOC_GICT_GICT_ERR11FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR11FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR11FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_UE_SHIFT)) & NOC_GICT_GICT_ERR11FR_UE_MASK) #define NOC_GICT_GICT_ERR11FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR11FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR11FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR11FR_CFI_MASK) #define NOC_GICT_GICT_ERR11FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR11FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR11FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR11FR_CEC_MASK) #define NOC_GICT_GICT_ERR11FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR11FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR11FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_RP_SHIFT)) & NOC_GICT_GICT_ERR11FR_RP_MASK) #define NOC_GICT_GICT_ERR11FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR11FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR11FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR11FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR11CTLR - GICT_ERR11CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR11CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR11CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR11CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR11CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR11CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR11CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_UI_MASK) #define NOC_GICT_GICT_ERR11CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR11CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR11CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_FI_MASK) #define NOC_GICT_GICT_ERR11CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR11CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR11CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_UE_MASK) #define NOC_GICT_GICT_ERR11CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR11CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR11CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR11CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR11CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR11CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR11CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR11CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR11CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR11CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR11CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR11CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_RP_MASK) #define NOC_GICT_GICT_ERR11CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR11CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR11CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR11CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR11CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR11CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR11CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR11CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR11CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR11CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR11CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR11CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR11CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR11CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR11CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR11CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR11CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR11CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR11CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR11CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR11CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR11CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR11CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR11CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR11CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR11STATUS - GICT_ERR11STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR11STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR11STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR11STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR11STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR11STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR11STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR11STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR11STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR11STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR11STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR11STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR11STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_UET_MASK) #define NOC_GICT_GICT_ERR11STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR11STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR11STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR11STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR11STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR11STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_CE_MASK) #define NOC_GICT_GICT_ERR11STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR11STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR11STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_MV_MASK) #define NOC_GICT_GICT_ERR11STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR11STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR11STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_OF_MASK) #define NOC_GICT_GICT_ERR11STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR11STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR11STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_ER_MASK) #define NOC_GICT_GICT_ERR11STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR11STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR11STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_UE_MASK) #define NOC_GICT_GICT_ERR11STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR11STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR11STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_V_MASK) #define NOC_GICT_GICT_ERR11STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR11STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR11STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_AV_MASK) #define NOC_GICT_GICT_ERR11STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR11STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR11STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR11STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR11ADDR - GICT_ERR11ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR11ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR11ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR11ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR11ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR11ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR11ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR11ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR11ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR11ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR11ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR11ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR11ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR11MISC0 - GICT_ERR11MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR11MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR11MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR11MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR11MISC0_Data_MASK) #define NOC_GICT_GICT_ERR11MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR11MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR11MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR11MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR11MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR11MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR11MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR11MISC0_OF_MASK) #define NOC_GICT_GICT_ERR11MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR11MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR11MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR11MISC0_RE_MASK) #define NOC_GICT_GICT_ERR11MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR11MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR11MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR11MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR11MISC1 - GICT_ERR11MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR11MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR11MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR11MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR11MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR11MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR12FR - GICT_ERR12FR */ /*! @{ */ #define NOC_GICT_GICT_ERR12FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR12FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR12FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_ED_SHIFT)) & NOC_GICT_GICT_ERR12FR_ED_MASK) #define NOC_GICT_GICT_ERR12FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR12FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR12FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_DE_SHIFT)) & NOC_GICT_GICT_ERR12FR_DE_MASK) #define NOC_GICT_GICT_ERR12FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR12FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR12FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_UI_SHIFT)) & NOC_GICT_GICT_ERR12FR_UI_MASK) #define NOC_GICT_GICT_ERR12FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR12FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR12FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_FI_SHIFT)) & NOC_GICT_GICT_ERR12FR_FI_MASK) #define NOC_GICT_GICT_ERR12FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR12FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR12FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_UE_SHIFT)) & NOC_GICT_GICT_ERR12FR_UE_MASK) #define NOC_GICT_GICT_ERR12FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR12FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR12FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR12FR_CFI_MASK) #define NOC_GICT_GICT_ERR12FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR12FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR12FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR12FR_CEC_MASK) #define NOC_GICT_GICT_ERR12FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR12FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR12FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_RP_SHIFT)) & NOC_GICT_GICT_ERR12FR_RP_MASK) #define NOC_GICT_GICT_ERR12FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR12FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR12FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR12FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR12CTLR - GICT_ERR12CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR12CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR12CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR12CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR12CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR12CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR12CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_UI_MASK) #define NOC_GICT_GICT_ERR12CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR12CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR12CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_FI_MASK) #define NOC_GICT_GICT_ERR12CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR12CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR12CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_UE_MASK) #define NOC_GICT_GICT_ERR12CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR12CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR12CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR12CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR12CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR12CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR12CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR12CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR12CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR12CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR12CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR12CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_RP_MASK) #define NOC_GICT_GICT_ERR12CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR12CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR12CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR12CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR12CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR12CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR12CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR12CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR12CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR12CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR12CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR12CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR12CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR12CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR12CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR12CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR12CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR12CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR12CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR12CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR12CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR12CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR12CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR12CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR12CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR12STATUS - GICT_ERR12STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR12STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR12STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR12STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR12STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR12STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR12STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR12STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR12STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR12STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR12STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR12STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR12STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_UET_MASK) #define NOC_GICT_GICT_ERR12STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR12STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR12STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR12STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR12STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR12STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_CE_MASK) #define NOC_GICT_GICT_ERR12STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR12STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR12STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_MV_MASK) #define NOC_GICT_GICT_ERR12STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR12STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR12STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_OF_MASK) #define NOC_GICT_GICT_ERR12STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR12STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR12STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_ER_MASK) #define NOC_GICT_GICT_ERR12STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR12STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR12STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_UE_MASK) #define NOC_GICT_GICT_ERR12STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR12STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR12STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_V_MASK) #define NOC_GICT_GICT_ERR12STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR12STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR12STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_AV_MASK) #define NOC_GICT_GICT_ERR12STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR12STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR12STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR12STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR12ADDR - GICT_ERR12ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR12ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR12ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR12ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR12ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR12ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR12ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR12ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR12ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR12ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR12ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR12ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR12ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR12MISC0 - GICT_ERR12MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR12MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR12MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR12MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR12MISC0_Data_MASK) #define NOC_GICT_GICT_ERR12MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR12MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR12MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR12MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR12MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR12MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR12MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR12MISC0_OF_MASK) #define NOC_GICT_GICT_ERR12MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR12MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR12MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR12MISC0_RE_MASK) #define NOC_GICT_GICT_ERR12MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR12MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR12MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR12MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR12MISC1 - GICT_ERR12MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR12MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR12MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR12MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR12MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR12MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR13FR - GICT_ERR13FR */ /*! @{ */ #define NOC_GICT_GICT_ERR13FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR13FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR13FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_ED_SHIFT)) & NOC_GICT_GICT_ERR13FR_ED_MASK) #define NOC_GICT_GICT_ERR13FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR13FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR13FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_DE_SHIFT)) & NOC_GICT_GICT_ERR13FR_DE_MASK) #define NOC_GICT_GICT_ERR13FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR13FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR13FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_UI_SHIFT)) & NOC_GICT_GICT_ERR13FR_UI_MASK) #define NOC_GICT_GICT_ERR13FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR13FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR13FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_FI_SHIFT)) & NOC_GICT_GICT_ERR13FR_FI_MASK) #define NOC_GICT_GICT_ERR13FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR13FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR13FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_UE_SHIFT)) & NOC_GICT_GICT_ERR13FR_UE_MASK) #define NOC_GICT_GICT_ERR13FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR13FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR13FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR13FR_CFI_MASK) #define NOC_GICT_GICT_ERR13FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR13FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR13FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR13FR_CEC_MASK) #define NOC_GICT_GICT_ERR13FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR13FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR13FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_RP_SHIFT)) & NOC_GICT_GICT_ERR13FR_RP_MASK) #define NOC_GICT_GICT_ERR13FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR13FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR13FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR13FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR13CTLR - GICT_ERR13CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR13CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR13CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR13CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR13CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR13CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR13CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_UI_MASK) #define NOC_GICT_GICT_ERR13CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR13CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR13CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_FI_MASK) #define NOC_GICT_GICT_ERR13CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR13CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR13CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_UE_MASK) #define NOC_GICT_GICT_ERR13CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR13CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR13CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR13CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR13CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR13CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR13CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR13CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR13CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR13CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR13CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR13CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_RP_MASK) #define NOC_GICT_GICT_ERR13CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR13CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR13CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR13CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR13CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR13CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR13CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR13CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR13CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR13CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR13CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR13CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR13CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR13CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR13CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR13CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR13CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR13CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR13CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR13CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR13CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR13CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR13CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR13CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR13CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR13STATUS - GICT_ERR13STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR13STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR13STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR13STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR13STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR13STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR13STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR13STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR13STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR13STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR13STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR13STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR13STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_UET_MASK) #define NOC_GICT_GICT_ERR13STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR13STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR13STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR13STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR13STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR13STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_CE_MASK) #define NOC_GICT_GICT_ERR13STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR13STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR13STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_MV_MASK) #define NOC_GICT_GICT_ERR13STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR13STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR13STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_OF_MASK) #define NOC_GICT_GICT_ERR13STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR13STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR13STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_ER_MASK) #define NOC_GICT_GICT_ERR13STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR13STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR13STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_UE_MASK) #define NOC_GICT_GICT_ERR13STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR13STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR13STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_V_MASK) #define NOC_GICT_GICT_ERR13STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR13STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR13STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_AV_MASK) #define NOC_GICT_GICT_ERR13STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR13STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR13STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR13STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR13ADDR - GICT_ERR13ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR13ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR13ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR13ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR13ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR13ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR13ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR13ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR13ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR13ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR13ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR13ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR13ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR13MISC0 - GICT_ERR13MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR13MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR13MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR13MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR13MISC0_Data_MASK) #define NOC_GICT_GICT_ERR13MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR13MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR13MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR13MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR13MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR13MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR13MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR13MISC0_OF_MASK) #define NOC_GICT_GICT_ERR13MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR13MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR13MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR13MISC0_RE_MASK) #define NOC_GICT_GICT_ERR13MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR13MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR13MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR13MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR13MISC1 - GICT_ERR13MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR13MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR13MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR13MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR13MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR13MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR14FR - GICT_ERR14FR */ /*! @{ */ #define NOC_GICT_GICT_ERR14FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR14FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR14FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_ED_SHIFT)) & NOC_GICT_GICT_ERR14FR_ED_MASK) #define NOC_GICT_GICT_ERR14FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR14FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR14FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_DE_SHIFT)) & NOC_GICT_GICT_ERR14FR_DE_MASK) #define NOC_GICT_GICT_ERR14FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR14FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR14FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_UI_SHIFT)) & NOC_GICT_GICT_ERR14FR_UI_MASK) #define NOC_GICT_GICT_ERR14FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR14FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR14FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_FI_SHIFT)) & NOC_GICT_GICT_ERR14FR_FI_MASK) #define NOC_GICT_GICT_ERR14FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR14FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR14FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_UE_SHIFT)) & NOC_GICT_GICT_ERR14FR_UE_MASK) #define NOC_GICT_GICT_ERR14FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR14FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR14FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR14FR_CFI_MASK) #define NOC_GICT_GICT_ERR14FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR14FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR14FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR14FR_CEC_MASK) #define NOC_GICT_GICT_ERR14FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR14FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR14FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_RP_SHIFT)) & NOC_GICT_GICT_ERR14FR_RP_MASK) #define NOC_GICT_GICT_ERR14FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR14FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR14FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR14FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR14CTLR - GICT_ERR14CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR14CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR14CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR14CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR14CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR14CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR14CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_UI_MASK) #define NOC_GICT_GICT_ERR14CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR14CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR14CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_FI_MASK) #define NOC_GICT_GICT_ERR14CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR14CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR14CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_UE_MASK) #define NOC_GICT_GICT_ERR14CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR14CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR14CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR14CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR14CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR14CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR14CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR14CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR14CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR14CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR14CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR14CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_RP_MASK) #define NOC_GICT_GICT_ERR14CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR14CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR14CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR14CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR14CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR14CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR14CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR14CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR14CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR14CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR14CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR14CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR14CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR14CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR14CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR14CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR14CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR14CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR14CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR14CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR14CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR14CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR14CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR14CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR14CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR14STATUS - GICT_ERR14STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR14STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR14STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR14STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR14STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR14STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR14STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR14STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR14STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR14STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR14STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR14STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR14STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_UET_MASK) #define NOC_GICT_GICT_ERR14STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR14STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR14STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR14STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR14STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR14STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_CE_MASK) #define NOC_GICT_GICT_ERR14STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR14STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR14STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_MV_MASK) #define NOC_GICT_GICT_ERR14STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR14STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR14STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_OF_MASK) #define NOC_GICT_GICT_ERR14STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR14STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR14STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_ER_MASK) #define NOC_GICT_GICT_ERR14STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR14STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR14STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_UE_MASK) #define NOC_GICT_GICT_ERR14STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR14STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR14STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_V_MASK) #define NOC_GICT_GICT_ERR14STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR14STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR14STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_AV_MASK) #define NOC_GICT_GICT_ERR14STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR14STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR14STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR14STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR14ADDR - GICT_ERR14ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR14ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR14ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR14ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR14ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR14ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR14ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR14ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR14ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR14ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR14ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR14ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR14ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR14MISC0 - GICT_ERR14MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR14MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR14MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR14MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR14MISC0_Data_MASK) #define NOC_GICT_GICT_ERR14MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR14MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR14MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR14MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR14MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR14MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR14MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR14MISC0_OF_MASK) #define NOC_GICT_GICT_ERR14MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR14MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR14MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR14MISC0_RE_MASK) #define NOC_GICT_GICT_ERR14MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR14MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR14MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR14MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR14MISC1 - GICT_ERR14MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR14MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR14MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR14MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR14MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR14MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR15FR - GICT_ERR15FR */ /*! @{ */ #define NOC_GICT_GICT_ERR15FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR15FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR15FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_ED_SHIFT)) & NOC_GICT_GICT_ERR15FR_ED_MASK) #define NOC_GICT_GICT_ERR15FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR15FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR15FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_DE_SHIFT)) & NOC_GICT_GICT_ERR15FR_DE_MASK) #define NOC_GICT_GICT_ERR15FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR15FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR15FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_UI_SHIFT)) & NOC_GICT_GICT_ERR15FR_UI_MASK) #define NOC_GICT_GICT_ERR15FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR15FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR15FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_FI_SHIFT)) & NOC_GICT_GICT_ERR15FR_FI_MASK) #define NOC_GICT_GICT_ERR15FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR15FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR15FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_UE_SHIFT)) & NOC_GICT_GICT_ERR15FR_UE_MASK) #define NOC_GICT_GICT_ERR15FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR15FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR15FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR15FR_CFI_MASK) #define NOC_GICT_GICT_ERR15FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR15FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR15FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR15FR_CEC_MASK) #define NOC_GICT_GICT_ERR15FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR15FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR15FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_RP_SHIFT)) & NOC_GICT_GICT_ERR15FR_RP_MASK) #define NOC_GICT_GICT_ERR15FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR15FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR15FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR15FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR15CTLR - GICT_ERR15CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR15CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR15CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR15CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR15CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR15CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR15CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_UI_MASK) #define NOC_GICT_GICT_ERR15CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR15CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR15CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_FI_MASK) #define NOC_GICT_GICT_ERR15CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR15CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR15CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_UE_MASK) #define NOC_GICT_GICT_ERR15CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR15CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR15CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR15CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR15CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR15CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR15CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR15CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR15CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR15CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR15CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR15CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_RP_MASK) #define NOC_GICT_GICT_ERR15CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR15CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR15CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR15CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR15CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR15CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR15CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR15CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR15CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR15CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR15CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR15CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR15CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR15CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR15CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR15CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR15CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR15CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR15CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR15CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR15CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR15CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR15CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR15CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR15CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR15STATUS - GICT_ERR15STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR15STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR15STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR15STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR15STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR15STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR15STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR15STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR15STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR15STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR15STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR15STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR15STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_UET_MASK) #define NOC_GICT_GICT_ERR15STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR15STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR15STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR15STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR15STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR15STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_CE_MASK) #define NOC_GICT_GICT_ERR15STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR15STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR15STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_MV_MASK) #define NOC_GICT_GICT_ERR15STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR15STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR15STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_OF_MASK) #define NOC_GICT_GICT_ERR15STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR15STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR15STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_ER_MASK) #define NOC_GICT_GICT_ERR15STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR15STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR15STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_UE_MASK) #define NOC_GICT_GICT_ERR15STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR15STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR15STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_V_MASK) #define NOC_GICT_GICT_ERR15STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR15STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR15STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_AV_MASK) #define NOC_GICT_GICT_ERR15STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR15STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR15STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR15STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR15ADDR - GICT_ERR15ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR15ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR15ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR15ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR15ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR15ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR15ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR15ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR15ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR15ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR15ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR15ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR15ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR15MISC0 - GICT_ERR15MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR15MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR15MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR15MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR15MISC0_Data_MASK) #define NOC_GICT_GICT_ERR15MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR15MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR15MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR15MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR15MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR15MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR15MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR15MISC0_OF_MASK) #define NOC_GICT_GICT_ERR15MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR15MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR15MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR15MISC0_RE_MASK) #define NOC_GICT_GICT_ERR15MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR15MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR15MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR15MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR15MISC1 - GICT_ERR15MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR15MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR15MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR15MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR15MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR15MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR16FR - GICT_ERR16FR */ /*! @{ */ #define NOC_GICT_GICT_ERR16FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR16FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR16FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_ED_SHIFT)) & NOC_GICT_GICT_ERR16FR_ED_MASK) #define NOC_GICT_GICT_ERR16FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR16FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR16FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_DE_SHIFT)) & NOC_GICT_GICT_ERR16FR_DE_MASK) #define NOC_GICT_GICT_ERR16FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR16FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR16FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_UI_SHIFT)) & NOC_GICT_GICT_ERR16FR_UI_MASK) #define NOC_GICT_GICT_ERR16FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR16FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR16FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_FI_SHIFT)) & NOC_GICT_GICT_ERR16FR_FI_MASK) #define NOC_GICT_GICT_ERR16FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR16FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR16FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_UE_SHIFT)) & NOC_GICT_GICT_ERR16FR_UE_MASK) #define NOC_GICT_GICT_ERR16FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR16FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR16FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR16FR_CFI_MASK) #define NOC_GICT_GICT_ERR16FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR16FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR16FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR16FR_CEC_MASK) #define NOC_GICT_GICT_ERR16FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR16FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR16FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_RP_SHIFT)) & NOC_GICT_GICT_ERR16FR_RP_MASK) #define NOC_GICT_GICT_ERR16FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR16FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR16FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR16FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR16CTLR - GICT_ERR16CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR16CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR16CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR16CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR16CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR16CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR16CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_UI_MASK) #define NOC_GICT_GICT_ERR16CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR16CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR16CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_FI_MASK) #define NOC_GICT_GICT_ERR16CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR16CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR16CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_UE_MASK) #define NOC_GICT_GICT_ERR16CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR16CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR16CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR16CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR16CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR16CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR16CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR16CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR16CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR16CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR16CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR16CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_RP_MASK) #define NOC_GICT_GICT_ERR16CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR16CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR16CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR16CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR16CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR16CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR16CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR16CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR16CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR16CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR16CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR16CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR16CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR16CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR16CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR16CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR16CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR16CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR16CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR16CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR16CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR16CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR16CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR16CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR16CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR16STATUS - GICT_ERR16STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR16STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR16STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR16STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR16STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR16STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR16STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR16STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR16STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR16STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR16STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR16STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR16STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_UET_MASK) #define NOC_GICT_GICT_ERR16STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR16STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR16STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR16STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR16STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR16STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_CE_MASK) #define NOC_GICT_GICT_ERR16STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR16STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR16STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_MV_MASK) #define NOC_GICT_GICT_ERR16STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR16STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR16STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_OF_MASK) #define NOC_GICT_GICT_ERR16STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR16STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR16STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_ER_MASK) #define NOC_GICT_GICT_ERR16STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR16STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR16STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_UE_MASK) #define NOC_GICT_GICT_ERR16STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR16STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR16STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_V_MASK) #define NOC_GICT_GICT_ERR16STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR16STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR16STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_AV_MASK) #define NOC_GICT_GICT_ERR16STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR16STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR16STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR16STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR16ADDR - GICT_ERR16ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR16ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR16ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR16ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR16ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR16ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR16ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR16ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR16ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR16ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR16ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR16ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR16ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR16MISC0 - GICT_ERR16MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR16MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR16MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR16MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR16MISC0_Data_MASK) #define NOC_GICT_GICT_ERR16MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR16MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR16MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR16MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR16MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR16MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR16MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR16MISC0_OF_MASK) #define NOC_GICT_GICT_ERR16MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR16MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR16MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR16MISC0_RE_MASK) #define NOC_GICT_GICT_ERR16MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR16MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR16MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR16MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR16MISC1 - GICT_ERR16MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR16MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR16MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR16MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR16MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR16MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR17FR - GICT_ERR17FR */ /*! @{ */ #define NOC_GICT_GICT_ERR17FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR17FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR17FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_ED_SHIFT)) & NOC_GICT_GICT_ERR17FR_ED_MASK) #define NOC_GICT_GICT_ERR17FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR17FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR17FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_DE_SHIFT)) & NOC_GICT_GICT_ERR17FR_DE_MASK) #define NOC_GICT_GICT_ERR17FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR17FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR17FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_UI_SHIFT)) & NOC_GICT_GICT_ERR17FR_UI_MASK) #define NOC_GICT_GICT_ERR17FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR17FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR17FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_FI_SHIFT)) & NOC_GICT_GICT_ERR17FR_FI_MASK) #define NOC_GICT_GICT_ERR17FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR17FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR17FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_UE_SHIFT)) & NOC_GICT_GICT_ERR17FR_UE_MASK) #define NOC_GICT_GICT_ERR17FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR17FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR17FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR17FR_CFI_MASK) #define NOC_GICT_GICT_ERR17FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR17FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR17FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR17FR_CEC_MASK) #define NOC_GICT_GICT_ERR17FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR17FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR17FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_RP_SHIFT)) & NOC_GICT_GICT_ERR17FR_RP_MASK) #define NOC_GICT_GICT_ERR17FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR17FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR17FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR17FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR17CTLR - GICT_ERR17CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR17CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR17CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR17CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR17CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR17CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR17CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_UI_MASK) #define NOC_GICT_GICT_ERR17CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR17CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR17CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_FI_MASK) #define NOC_GICT_GICT_ERR17CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR17CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR17CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_UE_MASK) #define NOC_GICT_GICT_ERR17CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR17CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR17CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR17CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR17CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR17CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR17CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR17CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR17CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR17CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR17CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR17CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_RP_MASK) #define NOC_GICT_GICT_ERR17CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR17CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR17CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR17CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR17CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR17CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR17CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR17CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR17CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR17CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR17CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR17CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR17CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR17CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR17CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR17CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR17CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR17CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR17CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR17CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR17CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR17CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR17CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR17CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR17CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR17STATUS - GICT_ERR17STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR17STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR17STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR17STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR17STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR17STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR17STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR17STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR17STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR17STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR17STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR17STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR17STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_UET_MASK) #define NOC_GICT_GICT_ERR17STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR17STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR17STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR17STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR17STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR17STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_CE_MASK) #define NOC_GICT_GICT_ERR17STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR17STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR17STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_MV_MASK) #define NOC_GICT_GICT_ERR17STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR17STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR17STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_OF_MASK) #define NOC_GICT_GICT_ERR17STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR17STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR17STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_ER_MASK) #define NOC_GICT_GICT_ERR17STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR17STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR17STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_UE_MASK) #define NOC_GICT_GICT_ERR17STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR17STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR17STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_V_MASK) #define NOC_GICT_GICT_ERR17STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR17STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR17STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_AV_MASK) #define NOC_GICT_GICT_ERR17STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR17STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR17STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR17STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR17ADDR - GICT_ERR17ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR17ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR17ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR17ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR17ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR17ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR17ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR17ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR17ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR17ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR17ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR17ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR17ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR17MISC0 - GICT_ERR17MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR17MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR17MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR17MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR17MISC0_Data_MASK) #define NOC_GICT_GICT_ERR17MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR17MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR17MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR17MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR17MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR17MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR17MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR17MISC0_OF_MASK) #define NOC_GICT_GICT_ERR17MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR17MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR17MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR17MISC0_RE_MASK) #define NOC_GICT_GICT_ERR17MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR17MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR17MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR17MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR17MISC1 - GICT_ERR17MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR17MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR17MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR17MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR17MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR17MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR18FR - GICT_ERR18FR */ /*! @{ */ #define NOC_GICT_GICT_ERR18FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR18FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR18FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_ED_SHIFT)) & NOC_GICT_GICT_ERR18FR_ED_MASK) #define NOC_GICT_GICT_ERR18FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR18FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR18FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_DE_SHIFT)) & NOC_GICT_GICT_ERR18FR_DE_MASK) #define NOC_GICT_GICT_ERR18FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR18FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR18FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_UI_SHIFT)) & NOC_GICT_GICT_ERR18FR_UI_MASK) #define NOC_GICT_GICT_ERR18FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR18FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR18FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_FI_SHIFT)) & NOC_GICT_GICT_ERR18FR_FI_MASK) #define NOC_GICT_GICT_ERR18FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR18FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR18FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_UE_SHIFT)) & NOC_GICT_GICT_ERR18FR_UE_MASK) #define NOC_GICT_GICT_ERR18FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR18FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR18FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR18FR_CFI_MASK) #define NOC_GICT_GICT_ERR18FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR18FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR18FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR18FR_CEC_MASK) #define NOC_GICT_GICT_ERR18FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR18FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR18FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_RP_SHIFT)) & NOC_GICT_GICT_ERR18FR_RP_MASK) #define NOC_GICT_GICT_ERR18FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR18FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR18FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR18FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR18CTLR - GICT_ERR18CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR18CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR18CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR18CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR18CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR18CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR18CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_UI_MASK) #define NOC_GICT_GICT_ERR18CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR18CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR18CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_FI_MASK) #define NOC_GICT_GICT_ERR18CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR18CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR18CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_UE_MASK) #define NOC_GICT_GICT_ERR18CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR18CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR18CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR18CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR18CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR18CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR18CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR18CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR18CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR18CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR18CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR18CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_RP_MASK) #define NOC_GICT_GICT_ERR18CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR18CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR18CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR18CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR18CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR18CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR18CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR18CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR18CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR18CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR18CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR18CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR18CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR18CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR18CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR18CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR18CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR18CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR18CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR18CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR18CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR18CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR18CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR18CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR18CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR18STATUS - GICT_ERR18STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR18STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR18STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR18STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR18STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR18STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR18STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR18STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR18STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR18STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR18STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR18STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR18STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_UET_MASK) #define NOC_GICT_GICT_ERR18STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR18STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR18STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR18STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR18STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR18STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_CE_MASK) #define NOC_GICT_GICT_ERR18STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR18STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR18STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_MV_MASK) #define NOC_GICT_GICT_ERR18STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR18STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR18STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_OF_MASK) #define NOC_GICT_GICT_ERR18STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR18STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR18STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_ER_MASK) #define NOC_GICT_GICT_ERR18STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR18STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR18STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_UE_MASK) #define NOC_GICT_GICT_ERR18STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR18STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR18STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_V_MASK) #define NOC_GICT_GICT_ERR18STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR18STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR18STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_AV_MASK) #define NOC_GICT_GICT_ERR18STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR18STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR18STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR18STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR18ADDR - GICT_ERR18ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR18ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR18ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR18ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR18ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR18ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR18ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR18ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR18ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR18ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR18ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR18ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR18ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR18MISC0 - GICT_ERR18MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR18MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR18MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR18MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR18MISC0_Data_MASK) #define NOC_GICT_GICT_ERR18MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR18MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR18MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR18MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR18MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR18MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR18MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR18MISC0_OF_MASK) #define NOC_GICT_GICT_ERR18MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR18MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR18MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR18MISC0_RE_MASK) #define NOC_GICT_GICT_ERR18MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR18MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR18MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR18MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR18MISC1 - GICT_ERR18MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR18MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR18MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR18MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR18MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR18MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR19FR - GICT_ERR19FR */ /*! @{ */ #define NOC_GICT_GICT_ERR19FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR19FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR19FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_ED_SHIFT)) & NOC_GICT_GICT_ERR19FR_ED_MASK) #define NOC_GICT_GICT_ERR19FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR19FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR19FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_DE_SHIFT)) & NOC_GICT_GICT_ERR19FR_DE_MASK) #define NOC_GICT_GICT_ERR19FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR19FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR19FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_UI_SHIFT)) & NOC_GICT_GICT_ERR19FR_UI_MASK) #define NOC_GICT_GICT_ERR19FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR19FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR19FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_FI_SHIFT)) & NOC_GICT_GICT_ERR19FR_FI_MASK) #define NOC_GICT_GICT_ERR19FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR19FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR19FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_UE_SHIFT)) & NOC_GICT_GICT_ERR19FR_UE_MASK) #define NOC_GICT_GICT_ERR19FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR19FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR19FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR19FR_CFI_MASK) #define NOC_GICT_GICT_ERR19FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR19FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR19FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR19FR_CEC_MASK) #define NOC_GICT_GICT_ERR19FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR19FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR19FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_RP_SHIFT)) & NOC_GICT_GICT_ERR19FR_RP_MASK) #define NOC_GICT_GICT_ERR19FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR19FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR19FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR19FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR19CTLR - GICT_ERR19CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR19CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR19CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR19CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR19CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR19CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR19CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_UI_MASK) #define NOC_GICT_GICT_ERR19CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR19CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR19CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_FI_MASK) #define NOC_GICT_GICT_ERR19CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR19CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR19CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_UE_MASK) #define NOC_GICT_GICT_ERR19CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR19CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR19CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR19CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR19CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR19CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR19CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR19CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR19CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR19CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR19CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR19CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_RP_MASK) #define NOC_GICT_GICT_ERR19CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR19CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR19CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR19CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR19CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR19CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR19CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR19CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR19CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR19CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR19CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR19CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR19CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR19CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR19CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR19CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR19CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR19CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR19CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR19CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR19CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR19CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR19CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR19CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR19CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR19STATUS - GICT_ERR19STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR19STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR19STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR19STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR19STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR19STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR19STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR19STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR19STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR19STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR19STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR19STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR19STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_UET_MASK) #define NOC_GICT_GICT_ERR19STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR19STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR19STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR19STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR19STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR19STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_CE_MASK) #define NOC_GICT_GICT_ERR19STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR19STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR19STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_MV_MASK) #define NOC_GICT_GICT_ERR19STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR19STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR19STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_OF_MASK) #define NOC_GICT_GICT_ERR19STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR19STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR19STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_ER_MASK) #define NOC_GICT_GICT_ERR19STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR19STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR19STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_UE_MASK) #define NOC_GICT_GICT_ERR19STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR19STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR19STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_V_MASK) #define NOC_GICT_GICT_ERR19STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR19STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR19STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_AV_MASK) #define NOC_GICT_GICT_ERR19STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR19STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR19STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR19STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR19ADDR - GICT_ERR19ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR19ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR19ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR19ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR19ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR19ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR19ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR19ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR19ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR19ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR19ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR19ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR19ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR19MISC0 - GICT_ERR19MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR19MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR19MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR19MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR19MISC0_Data_MASK) #define NOC_GICT_GICT_ERR19MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR19MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR19MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR19MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR19MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR19MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR19MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR19MISC0_OF_MASK) #define NOC_GICT_GICT_ERR19MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR19MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR19MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR19MISC0_RE_MASK) #define NOC_GICT_GICT_ERR19MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR19MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR19MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR19MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR19MISC1 - GICT_ERR19MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR19MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR19MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR19MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR19MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR19MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR20FR - GICT_ERR20FR */ /*! @{ */ #define NOC_GICT_GICT_ERR20FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR20FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR20FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_ED_SHIFT)) & NOC_GICT_GICT_ERR20FR_ED_MASK) #define NOC_GICT_GICT_ERR20FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR20FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR20FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_DE_SHIFT)) & NOC_GICT_GICT_ERR20FR_DE_MASK) #define NOC_GICT_GICT_ERR20FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR20FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR20FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_UI_SHIFT)) & NOC_GICT_GICT_ERR20FR_UI_MASK) #define NOC_GICT_GICT_ERR20FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR20FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR20FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_FI_SHIFT)) & NOC_GICT_GICT_ERR20FR_FI_MASK) #define NOC_GICT_GICT_ERR20FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR20FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR20FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_UE_SHIFT)) & NOC_GICT_GICT_ERR20FR_UE_MASK) #define NOC_GICT_GICT_ERR20FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR20FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR20FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR20FR_CFI_MASK) #define NOC_GICT_GICT_ERR20FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR20FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR20FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR20FR_CEC_MASK) #define NOC_GICT_GICT_ERR20FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR20FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR20FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_RP_SHIFT)) & NOC_GICT_GICT_ERR20FR_RP_MASK) #define NOC_GICT_GICT_ERR20FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR20FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR20FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR20FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR20CTLR - GICT_ERR20CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR20CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR20CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR20CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR20CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR20CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR20CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_UI_MASK) #define NOC_GICT_GICT_ERR20CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR20CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR20CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_FI_MASK) #define NOC_GICT_GICT_ERR20CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR20CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR20CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_UE_MASK) #define NOC_GICT_GICT_ERR20CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR20CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR20CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR20CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR20CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR20CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR20CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR20CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR20CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR20CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR20CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR20CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_RP_MASK) #define NOC_GICT_GICT_ERR20CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR20CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR20CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR20CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR20CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR20CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR20CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR20CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR20CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR20CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR20CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR20CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR20CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR20CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR20CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR20CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR20CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR20CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR20CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR20CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR20CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR20CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR20CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR20CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR20CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR20STATUS - GICT_ERR20STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR20STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR20STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR20STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR20STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR20STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR20STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR20STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR20STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR20STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR20STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR20STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR20STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_UET_MASK) #define NOC_GICT_GICT_ERR20STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR20STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR20STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR20STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR20STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR20STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_CE_MASK) #define NOC_GICT_GICT_ERR20STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR20STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR20STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_MV_MASK) #define NOC_GICT_GICT_ERR20STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR20STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR20STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_OF_MASK) #define NOC_GICT_GICT_ERR20STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR20STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR20STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_ER_MASK) #define NOC_GICT_GICT_ERR20STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR20STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR20STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_UE_MASK) #define NOC_GICT_GICT_ERR20STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR20STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR20STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_V_MASK) #define NOC_GICT_GICT_ERR20STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR20STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR20STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_AV_MASK) #define NOC_GICT_GICT_ERR20STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR20STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR20STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR20STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR20ADDR - GICT_ERR20ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR20ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR20ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR20ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR20ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR20ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR20ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR20ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR20ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR20ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR20ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR20ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR20ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR20MISC0 - GICT_ERR20MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR20MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR20MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR20MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR20MISC0_Data_MASK) #define NOC_GICT_GICT_ERR20MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR20MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR20MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR20MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR20MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR20MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR20MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR20MISC0_OF_MASK) #define NOC_GICT_GICT_ERR20MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR20MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR20MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR20MISC0_RE_MASK) #define NOC_GICT_GICT_ERR20MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR20MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR20MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR20MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR20MISC1 - GICT_ERR20MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR20MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR20MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR20MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR20MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR20MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR21FR - GICT_ERR21FR */ /*! @{ */ #define NOC_GICT_GICT_ERR21FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR21FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR21FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_ED_SHIFT)) & NOC_GICT_GICT_ERR21FR_ED_MASK) #define NOC_GICT_GICT_ERR21FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR21FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR21FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_DE_SHIFT)) & NOC_GICT_GICT_ERR21FR_DE_MASK) #define NOC_GICT_GICT_ERR21FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR21FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR21FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_UI_SHIFT)) & NOC_GICT_GICT_ERR21FR_UI_MASK) #define NOC_GICT_GICT_ERR21FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR21FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR21FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_FI_SHIFT)) & NOC_GICT_GICT_ERR21FR_FI_MASK) #define NOC_GICT_GICT_ERR21FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR21FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR21FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_UE_SHIFT)) & NOC_GICT_GICT_ERR21FR_UE_MASK) #define NOC_GICT_GICT_ERR21FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR21FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR21FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR21FR_CFI_MASK) #define NOC_GICT_GICT_ERR21FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR21FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR21FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR21FR_CEC_MASK) #define NOC_GICT_GICT_ERR21FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR21FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR21FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_RP_SHIFT)) & NOC_GICT_GICT_ERR21FR_RP_MASK) #define NOC_GICT_GICT_ERR21FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR21FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR21FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR21FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR21CTLR - GICT_ERR21CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR21CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR21CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR21CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR21CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR21CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR21CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_UI_MASK) #define NOC_GICT_GICT_ERR21CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR21CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR21CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_FI_MASK) #define NOC_GICT_GICT_ERR21CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR21CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR21CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_UE_MASK) #define NOC_GICT_GICT_ERR21CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR21CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR21CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR21CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR21CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR21CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR21CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR21CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR21CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR21CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR21CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR21CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_RP_MASK) #define NOC_GICT_GICT_ERR21CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR21CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR21CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR21CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR21CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR21CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR21CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR21CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR21CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR21CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR21CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR21CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR21CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR21CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR21CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR21CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR21CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR21CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR21CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR21CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR21CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR21CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR21CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR21CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR21CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR21STATUS - GICT_ERR21STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR21STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR21STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR21STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR21STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR21STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR21STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR21STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR21STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR21STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR21STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR21STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR21STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_UET_MASK) #define NOC_GICT_GICT_ERR21STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR21STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR21STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR21STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR21STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR21STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_CE_MASK) #define NOC_GICT_GICT_ERR21STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR21STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR21STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_MV_MASK) #define NOC_GICT_GICT_ERR21STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR21STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR21STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_OF_MASK) #define NOC_GICT_GICT_ERR21STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR21STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR21STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_ER_MASK) #define NOC_GICT_GICT_ERR21STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR21STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR21STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_UE_MASK) #define NOC_GICT_GICT_ERR21STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR21STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR21STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_V_MASK) #define NOC_GICT_GICT_ERR21STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR21STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR21STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_AV_MASK) #define NOC_GICT_GICT_ERR21STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR21STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR21STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR21STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR21ADDR - GICT_ERR21ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR21ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR21ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR21ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR21ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR21ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR21ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR21ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR21ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR21ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR21ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR21ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR21ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR21MISC0 - GICT_ERR21MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR21MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR21MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR21MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR21MISC0_Data_MASK) #define NOC_GICT_GICT_ERR21MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR21MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR21MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR21MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR21MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR21MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR21MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR21MISC0_OF_MASK) #define NOC_GICT_GICT_ERR21MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR21MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR21MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR21MISC0_RE_MASK) #define NOC_GICT_GICT_ERR21MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR21MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR21MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR21MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR21MISC1 - GICT_ERR21MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR21MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR21MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR21MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR21MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR21MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR22FR - GICT_ERR22FR */ /*! @{ */ #define NOC_GICT_GICT_ERR22FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR22FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR22FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_ED_SHIFT)) & NOC_GICT_GICT_ERR22FR_ED_MASK) #define NOC_GICT_GICT_ERR22FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR22FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR22FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_DE_SHIFT)) & NOC_GICT_GICT_ERR22FR_DE_MASK) #define NOC_GICT_GICT_ERR22FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR22FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR22FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_UI_SHIFT)) & NOC_GICT_GICT_ERR22FR_UI_MASK) #define NOC_GICT_GICT_ERR22FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR22FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR22FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_FI_SHIFT)) & NOC_GICT_GICT_ERR22FR_FI_MASK) #define NOC_GICT_GICT_ERR22FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR22FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR22FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_UE_SHIFT)) & NOC_GICT_GICT_ERR22FR_UE_MASK) #define NOC_GICT_GICT_ERR22FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR22FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR22FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR22FR_CFI_MASK) #define NOC_GICT_GICT_ERR22FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR22FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR22FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR22FR_CEC_MASK) #define NOC_GICT_GICT_ERR22FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR22FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR22FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_RP_SHIFT)) & NOC_GICT_GICT_ERR22FR_RP_MASK) #define NOC_GICT_GICT_ERR22FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR22FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR22FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR22FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR22CTLR - GICT_ERR22CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR22CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR22CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR22CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR22CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR22CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR22CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_UI_MASK) #define NOC_GICT_GICT_ERR22CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR22CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR22CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_FI_MASK) #define NOC_GICT_GICT_ERR22CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR22CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR22CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_UE_MASK) #define NOC_GICT_GICT_ERR22CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR22CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR22CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR22CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR22CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR22CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR22CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR22CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR22CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR22CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR22CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR22CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_RP_MASK) #define NOC_GICT_GICT_ERR22CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR22CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR22CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR22CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR22CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR22CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR22CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR22CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR22CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR22CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR22CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR22CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR22CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR22CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR22CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR22CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR22CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR22CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR22CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR22CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR22CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR22CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR22CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR22CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR22CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR22STATUS - GICT_ERR22STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR22STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR22STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR22STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR22STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR22STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR22STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR22STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR22STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR22STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR22STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR22STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR22STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_UET_MASK) #define NOC_GICT_GICT_ERR22STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR22STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR22STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR22STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR22STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR22STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_CE_MASK) #define NOC_GICT_GICT_ERR22STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR22STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR22STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_MV_MASK) #define NOC_GICT_GICT_ERR22STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR22STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR22STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_OF_MASK) #define NOC_GICT_GICT_ERR22STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR22STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR22STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_ER_MASK) #define NOC_GICT_GICT_ERR22STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR22STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR22STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_UE_MASK) #define NOC_GICT_GICT_ERR22STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR22STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR22STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_V_MASK) #define NOC_GICT_GICT_ERR22STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR22STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR22STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_AV_MASK) #define NOC_GICT_GICT_ERR22STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR22STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR22STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR22STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR22ADDR - GICT_ERR22ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR22ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR22ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR22ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR22ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR22ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR22ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR22ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR22ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR22ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR22ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR22ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR22ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR22MISC0 - GICT_ERR22MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR22MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR22MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR22MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR22MISC0_Data_MASK) #define NOC_GICT_GICT_ERR22MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR22MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR22MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR22MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR22MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR22MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR22MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR22MISC0_OF_MASK) #define NOC_GICT_GICT_ERR22MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR22MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR22MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR22MISC0_RE_MASK) #define NOC_GICT_GICT_ERR22MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR22MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR22MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR22MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR22MISC1 - GICT_ERR22MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR22MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR22MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR22MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR22MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR22MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR23FR - GICT_ERR23FR */ /*! @{ */ #define NOC_GICT_GICT_ERR23FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR23FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR23FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_ED_SHIFT)) & NOC_GICT_GICT_ERR23FR_ED_MASK) #define NOC_GICT_GICT_ERR23FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR23FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR23FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_DE_SHIFT)) & NOC_GICT_GICT_ERR23FR_DE_MASK) #define NOC_GICT_GICT_ERR23FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR23FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR23FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_UI_SHIFT)) & NOC_GICT_GICT_ERR23FR_UI_MASK) #define NOC_GICT_GICT_ERR23FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR23FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR23FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_FI_SHIFT)) & NOC_GICT_GICT_ERR23FR_FI_MASK) #define NOC_GICT_GICT_ERR23FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR23FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR23FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_UE_SHIFT)) & NOC_GICT_GICT_ERR23FR_UE_MASK) #define NOC_GICT_GICT_ERR23FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR23FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR23FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR23FR_CFI_MASK) #define NOC_GICT_GICT_ERR23FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR23FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR23FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR23FR_CEC_MASK) #define NOC_GICT_GICT_ERR23FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR23FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR23FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_RP_SHIFT)) & NOC_GICT_GICT_ERR23FR_RP_MASK) #define NOC_GICT_GICT_ERR23FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR23FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR23FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR23FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR23CTLR - GICT_ERR23CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR23CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR23CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR23CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR23CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR23CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR23CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_UI_MASK) #define NOC_GICT_GICT_ERR23CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR23CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR23CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_FI_MASK) #define NOC_GICT_GICT_ERR23CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR23CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR23CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_UE_MASK) #define NOC_GICT_GICT_ERR23CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR23CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR23CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR23CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR23CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR23CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR23CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR23CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR23CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR23CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR23CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR23CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_RP_MASK) #define NOC_GICT_GICT_ERR23CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR23CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR23CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR23CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR23CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR23CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR23CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR23CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR23CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR23CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR23CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR23CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR23CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR23CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR23CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR23CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR23CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR23CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR23CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR23CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR23CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR23CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR23CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR23CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR23CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR23STATUS - GICT_ERR23STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR23STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR23STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR23STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR23STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR23STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR23STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR23STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR23STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR23STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR23STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR23STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR23STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_UET_MASK) #define NOC_GICT_GICT_ERR23STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR23STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR23STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR23STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR23STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR23STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_CE_MASK) #define NOC_GICT_GICT_ERR23STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR23STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR23STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_MV_MASK) #define NOC_GICT_GICT_ERR23STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR23STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR23STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_OF_MASK) #define NOC_GICT_GICT_ERR23STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR23STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR23STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_ER_MASK) #define NOC_GICT_GICT_ERR23STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR23STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR23STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_UE_MASK) #define NOC_GICT_GICT_ERR23STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR23STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR23STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_V_MASK) #define NOC_GICT_GICT_ERR23STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR23STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR23STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_AV_MASK) #define NOC_GICT_GICT_ERR23STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR23STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR23STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR23STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR23ADDR - GICT_ERR23ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR23ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR23ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR23ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR23ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR23ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR23ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR23ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR23ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR23ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR23ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR23ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR23ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR23MISC0 - GICT_ERR23MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR23MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR23MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR23MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR23MISC0_Data_MASK) #define NOC_GICT_GICT_ERR23MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR23MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR23MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR23MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR23MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR23MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR23MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR23MISC0_OF_MASK) #define NOC_GICT_GICT_ERR23MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR23MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR23MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR23MISC0_RE_MASK) #define NOC_GICT_GICT_ERR23MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR23MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR23MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR23MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR23MISC1 - GICT_ERR23MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR23MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR23MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR23MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR23MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR23MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR24FR - GICT_ERR24FR */ /*! @{ */ #define NOC_GICT_GICT_ERR24FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR24FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR24FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_ED_SHIFT)) & NOC_GICT_GICT_ERR24FR_ED_MASK) #define NOC_GICT_GICT_ERR24FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR24FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR24FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_DE_SHIFT)) & NOC_GICT_GICT_ERR24FR_DE_MASK) #define NOC_GICT_GICT_ERR24FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR24FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR24FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_UI_SHIFT)) & NOC_GICT_GICT_ERR24FR_UI_MASK) #define NOC_GICT_GICT_ERR24FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR24FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR24FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_FI_SHIFT)) & NOC_GICT_GICT_ERR24FR_FI_MASK) #define NOC_GICT_GICT_ERR24FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR24FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR24FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_UE_SHIFT)) & NOC_GICT_GICT_ERR24FR_UE_MASK) #define NOC_GICT_GICT_ERR24FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR24FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR24FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR24FR_CFI_MASK) #define NOC_GICT_GICT_ERR24FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR24FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR24FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR24FR_CEC_MASK) #define NOC_GICT_GICT_ERR24FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR24FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR24FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_RP_SHIFT)) & NOC_GICT_GICT_ERR24FR_RP_MASK) #define NOC_GICT_GICT_ERR24FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR24FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR24FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR24FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR24CTLR - GICT_ERR24CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR24CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR24CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR24CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR24CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR24CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR24CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_UI_MASK) #define NOC_GICT_GICT_ERR24CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR24CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR24CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_FI_MASK) #define NOC_GICT_GICT_ERR24CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR24CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR24CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_UE_MASK) #define NOC_GICT_GICT_ERR24CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR24CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR24CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR24CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR24CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR24CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR24CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR24CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR24CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR24CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR24CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR24CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_RP_MASK) #define NOC_GICT_GICT_ERR24CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR24CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR24CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR24CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR24CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR24CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR24CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR24CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR24CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR24CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR24CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR24CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR24CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR24CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR24CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR24CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR24CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR24CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR24CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR24CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR24CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR24CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR24CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR24CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR24CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR24STATUS - GICT_ERR24STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR24STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR24STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR24STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR24STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR24STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR24STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR24STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR24STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR24STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR24STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR24STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR24STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_UET_MASK) #define NOC_GICT_GICT_ERR24STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR24STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR24STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR24STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR24STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR24STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_CE_MASK) #define NOC_GICT_GICT_ERR24STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR24STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR24STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_MV_MASK) #define NOC_GICT_GICT_ERR24STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR24STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR24STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_OF_MASK) #define NOC_GICT_GICT_ERR24STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR24STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR24STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_ER_MASK) #define NOC_GICT_GICT_ERR24STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR24STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR24STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_UE_MASK) #define NOC_GICT_GICT_ERR24STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR24STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR24STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_V_MASK) #define NOC_GICT_GICT_ERR24STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR24STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR24STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_AV_MASK) #define NOC_GICT_GICT_ERR24STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR24STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR24STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR24STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR24ADDR - GICT_ERR24ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR24ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR24ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR24ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR24ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR24ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR24ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR24ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR24ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR24ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR24ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR24ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR24ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR24MISC0 - GICT_ERR24MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR24MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR24MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR24MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR24MISC0_Data_MASK) #define NOC_GICT_GICT_ERR24MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR24MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR24MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR24MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR24MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR24MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR24MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR24MISC0_OF_MASK) #define NOC_GICT_GICT_ERR24MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR24MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR24MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR24MISC0_RE_MASK) #define NOC_GICT_GICT_ERR24MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR24MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR24MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR24MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR24MISC1 - GICT_ERR24MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR24MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR24MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR24MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR24MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR24MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR25FR - GICT_ERR25FR */ /*! @{ */ #define NOC_GICT_GICT_ERR25FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR25FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR25FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_ED_SHIFT)) & NOC_GICT_GICT_ERR25FR_ED_MASK) #define NOC_GICT_GICT_ERR25FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR25FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR25FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_DE_SHIFT)) & NOC_GICT_GICT_ERR25FR_DE_MASK) #define NOC_GICT_GICT_ERR25FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR25FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR25FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_UI_SHIFT)) & NOC_GICT_GICT_ERR25FR_UI_MASK) #define NOC_GICT_GICT_ERR25FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR25FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR25FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_FI_SHIFT)) & NOC_GICT_GICT_ERR25FR_FI_MASK) #define NOC_GICT_GICT_ERR25FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR25FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR25FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_UE_SHIFT)) & NOC_GICT_GICT_ERR25FR_UE_MASK) #define NOC_GICT_GICT_ERR25FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR25FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR25FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR25FR_CFI_MASK) #define NOC_GICT_GICT_ERR25FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR25FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR25FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR25FR_CEC_MASK) #define NOC_GICT_GICT_ERR25FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR25FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR25FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_RP_SHIFT)) & NOC_GICT_GICT_ERR25FR_RP_MASK) #define NOC_GICT_GICT_ERR25FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR25FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR25FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR25FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR25CTLR - GICT_ERR25CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR25CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR25CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR25CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR25CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR25CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR25CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_UI_MASK) #define NOC_GICT_GICT_ERR25CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR25CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR25CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_FI_MASK) #define NOC_GICT_GICT_ERR25CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR25CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR25CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_UE_MASK) #define NOC_GICT_GICT_ERR25CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR25CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR25CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR25CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR25CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR25CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR25CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR25CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR25CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR25CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR25CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR25CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_RP_MASK) #define NOC_GICT_GICT_ERR25CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR25CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR25CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR25CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR25CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR25CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR25CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR25CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR25CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR25CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR25CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR25CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR25CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR25CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR25CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR25CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR25CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR25CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR25CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR25CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR25CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR25CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR25CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR25CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR25CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR25STATUS - GICT_ERR25STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR25STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR25STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR25STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR25STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR25STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR25STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR25STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR25STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR25STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR25STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR25STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR25STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_UET_MASK) #define NOC_GICT_GICT_ERR25STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR25STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR25STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR25STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR25STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR25STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_CE_MASK) #define NOC_GICT_GICT_ERR25STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR25STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR25STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_MV_MASK) #define NOC_GICT_GICT_ERR25STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR25STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR25STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_OF_MASK) #define NOC_GICT_GICT_ERR25STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR25STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR25STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_ER_MASK) #define NOC_GICT_GICT_ERR25STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR25STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR25STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_UE_MASK) #define NOC_GICT_GICT_ERR25STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR25STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR25STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_V_MASK) #define NOC_GICT_GICT_ERR25STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR25STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR25STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_AV_MASK) #define NOC_GICT_GICT_ERR25STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR25STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR25STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR25STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR25ADDR - GICT_ERR25ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR25ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR25ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR25ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR25ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR25ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR25ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR25ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR25ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR25ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR25ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR25ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR25ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR25MISC0 - GICT_ERR25MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR25MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR25MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR25MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR25MISC0_Data_MASK) #define NOC_GICT_GICT_ERR25MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR25MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR25MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR25MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR25MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR25MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR25MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR25MISC0_OF_MASK) #define NOC_GICT_GICT_ERR25MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR25MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR25MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR25MISC0_RE_MASK) #define NOC_GICT_GICT_ERR25MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR25MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR25MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR25MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR25MISC1 - GICT_ERR25MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR25MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR25MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR25MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR25MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR25MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR26FR - GICT_ERR26FR */ /*! @{ */ #define NOC_GICT_GICT_ERR26FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR26FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR26FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_ED_SHIFT)) & NOC_GICT_GICT_ERR26FR_ED_MASK) #define NOC_GICT_GICT_ERR26FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR26FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR26FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_DE_SHIFT)) & NOC_GICT_GICT_ERR26FR_DE_MASK) #define NOC_GICT_GICT_ERR26FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR26FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR26FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_UI_SHIFT)) & NOC_GICT_GICT_ERR26FR_UI_MASK) #define NOC_GICT_GICT_ERR26FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR26FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR26FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_FI_SHIFT)) & NOC_GICT_GICT_ERR26FR_FI_MASK) #define NOC_GICT_GICT_ERR26FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR26FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR26FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_UE_SHIFT)) & NOC_GICT_GICT_ERR26FR_UE_MASK) #define NOC_GICT_GICT_ERR26FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR26FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR26FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR26FR_CFI_MASK) #define NOC_GICT_GICT_ERR26FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR26FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR26FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR26FR_CEC_MASK) #define NOC_GICT_GICT_ERR26FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR26FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR26FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_RP_SHIFT)) & NOC_GICT_GICT_ERR26FR_RP_MASK) #define NOC_GICT_GICT_ERR26FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR26FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR26FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR26FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR26CTLR - GICT_ERR26CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR26CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR26CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR26CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR26CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR26CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR26CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_UI_MASK) #define NOC_GICT_GICT_ERR26CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR26CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR26CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_FI_MASK) #define NOC_GICT_GICT_ERR26CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR26CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR26CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_UE_MASK) #define NOC_GICT_GICT_ERR26CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR26CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR26CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR26CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR26CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR26CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR26CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR26CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR26CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR26CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR26CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR26CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_RP_MASK) #define NOC_GICT_GICT_ERR26CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR26CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR26CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR26CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR26CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR26CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR26CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR26CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR26CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR26CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR26CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR26CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR26CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR26CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR26CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR26CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR26CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR26CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR26CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR26CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR26CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR26CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR26CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR26CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR26CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR26STATUS - GICT_ERR26STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR26STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR26STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR26STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR26STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR26STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR26STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR26STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR26STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR26STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR26STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR26STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR26STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_UET_MASK) #define NOC_GICT_GICT_ERR26STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR26STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR26STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR26STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR26STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR26STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_CE_MASK) #define NOC_GICT_GICT_ERR26STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR26STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR26STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_MV_MASK) #define NOC_GICT_GICT_ERR26STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR26STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR26STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_OF_MASK) #define NOC_GICT_GICT_ERR26STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR26STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR26STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_ER_MASK) #define NOC_GICT_GICT_ERR26STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR26STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR26STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_UE_MASK) #define NOC_GICT_GICT_ERR26STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR26STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR26STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_V_MASK) #define NOC_GICT_GICT_ERR26STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR26STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR26STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_AV_MASK) #define NOC_GICT_GICT_ERR26STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR26STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR26STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR26STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR26ADDR - GICT_ERR26ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR26ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR26ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR26ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR26ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR26ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR26ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR26ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR26ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR26ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR26ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR26ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR26ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR26MISC0 - GICT_ERR26MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR26MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR26MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR26MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR26MISC0_Data_MASK) #define NOC_GICT_GICT_ERR26MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR26MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR26MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR26MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR26MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR26MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR26MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR26MISC0_OF_MASK) #define NOC_GICT_GICT_ERR26MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR26MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR26MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR26MISC0_RE_MASK) #define NOC_GICT_GICT_ERR26MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR26MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR26MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR26MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR26MISC1 - GICT_ERR26MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR26MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR26MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR26MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR26MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR26MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERR27FR - GICT_ERR27FR */ /*! @{ */ #define NOC_GICT_GICT_ERR27FR_ED_MASK (0x3U) #define NOC_GICT_GICT_ERR27FR_ED_SHIFT (0U) /*! ED - ED */ #define NOC_GICT_GICT_ERR27FR_ED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_ED_SHIFT)) & NOC_GICT_GICT_ERR27FR_ED_MASK) #define NOC_GICT_GICT_ERR27FR_DE_MASK (0xCU) #define NOC_GICT_GICT_ERR27FR_DE_SHIFT (2U) /*! DE - DE */ #define NOC_GICT_GICT_ERR27FR_DE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_DE_SHIFT)) & NOC_GICT_GICT_ERR27FR_DE_MASK) #define NOC_GICT_GICT_ERR27FR_UI_MASK (0x30U) #define NOC_GICT_GICT_ERR27FR_UI_SHIFT (4U) /*! UI - UI */ #define NOC_GICT_GICT_ERR27FR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_UI_SHIFT)) & NOC_GICT_GICT_ERR27FR_UI_MASK) #define NOC_GICT_GICT_ERR27FR_FI_MASK (0xC0U) #define NOC_GICT_GICT_ERR27FR_FI_SHIFT (6U) /*! FI - FI */ #define NOC_GICT_GICT_ERR27FR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_FI_SHIFT)) & NOC_GICT_GICT_ERR27FR_FI_MASK) #define NOC_GICT_GICT_ERR27FR_UE_MASK (0x300U) #define NOC_GICT_GICT_ERR27FR_UE_SHIFT (8U) /*! UE - UE */ #define NOC_GICT_GICT_ERR27FR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_UE_SHIFT)) & NOC_GICT_GICT_ERR27FR_UE_MASK) #define NOC_GICT_GICT_ERR27FR_CFI_MASK (0xC00U) #define NOC_GICT_GICT_ERR27FR_CFI_SHIFT (10U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR27FR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_CFI_SHIFT)) & NOC_GICT_GICT_ERR27FR_CFI_MASK) #define NOC_GICT_GICT_ERR27FR_CEC_MASK (0x7000U) #define NOC_GICT_GICT_ERR27FR_CEC_SHIFT (12U) /*! CEC - CEC */ #define NOC_GICT_GICT_ERR27FR_CEC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_CEC_SHIFT)) & NOC_GICT_GICT_ERR27FR_CEC_MASK) #define NOC_GICT_GICT_ERR27FR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR27FR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR27FR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_RP_SHIFT)) & NOC_GICT_GICT_ERR27FR_RP_MASK) #define NOC_GICT_GICT_ERR27FR_RESERVED0_MASK (0xFFFFFFFFFFFF0000U) #define NOC_GICT_GICT_ERR27FR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR27FR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27FR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR27FR_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR27CTLR - GICT_ERR27CTLR */ /*! @{ */ #define NOC_GICT_GICT_ERR27CTLR_RESERVED0_MASK (0x3U) #define NOC_GICT_GICT_ERR27CTLR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR27CTLR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR27CTLR_UI_MASK (0x4U) #define NOC_GICT_GICT_ERR27CTLR_UI_SHIFT (2U) /*! UI - UI */ #define NOC_GICT_GICT_ERR27CTLR_UI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_UI_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_UI_MASK) #define NOC_GICT_GICT_ERR27CTLR_FI_MASK (0x8U) #define NOC_GICT_GICT_ERR27CTLR_FI_SHIFT (3U) /*! FI - FI */ #define NOC_GICT_GICT_ERR27CTLR_FI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_FI_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_FI_MASK) #define NOC_GICT_GICT_ERR27CTLR_UE_MASK (0x10U) #define NOC_GICT_GICT_ERR27CTLR_UE_SHIFT (4U) /*! UE - UE */ #define NOC_GICT_GICT_ERR27CTLR_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_UE_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_UE_MASK) #define NOC_GICT_GICT_ERR27CTLR_RESERVED1_MASK (0xE0U) #define NOC_GICT_GICT_ERR27CTLR_RESERVED1_SHIFT (5U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR27CTLR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_RESERVED1_MASK) #define NOC_GICT_GICT_ERR27CTLR_CFI_MASK (0x100U) #define NOC_GICT_GICT_ERR27CTLR_CFI_SHIFT (8U) /*! CFI - CFI */ #define NOC_GICT_GICT_ERR27CTLR_CFI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_CFI_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_CFI_MASK) #define NOC_GICT_GICT_ERR27CTLR_RESERVED2_MASK (0x7E00U) #define NOC_GICT_GICT_ERR27CTLR_RESERVED2_SHIFT (9U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR27CTLR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_RESERVED2_MASK) #define NOC_GICT_GICT_ERR27CTLR_RP_MASK (0x8000U) #define NOC_GICT_GICT_ERR27CTLR_RP_SHIFT (15U) /*! RP - RP */ #define NOC_GICT_GICT_ERR27CTLR_RP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_RP_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_RP_MASK) #define NOC_GICT_GICT_ERR27CTLR_RESERVED3_MASK (0xFFFF0000U) #define NOC_GICT_GICT_ERR27CTLR_RESERVED3_SHIFT (16U) /*! RESERVED3 - RESERVED3 */ #define NOC_GICT_GICT_ERR27CTLR_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_RESERVED3_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_RESERVED3_MASK) #define NOC_GICT_GICT_ERR27CTLR_DIS_COL_OOR_MASK (0x100000000U) #define NOC_GICT_GICT_ERR27CTLR_DIS_COL_OOR_SHIFT (32U) /*! DIS_COL_OOR - DIS_COL_OOR */ #define NOC_GICT_GICT_ERR27CTLR_DIS_COL_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_DIS_COL_OOR_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_DIS_COL_OOR_MASK) #define NOC_GICT_GICT_ERR27CTLR_DIS_DEACT_MASK (0x200000000U) #define NOC_GICT_GICT_ERR27CTLR_DIS_DEACT_SHIFT (33U) /*! DIS_DEACT - DIS_DEACT */ #define NOC_GICT_GICT_ERR27CTLR_DIS_DEACT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_DIS_DEACT_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_DIS_DEACT_MASK) #define NOC_GICT_GICT_ERR27CTLR_DIS_SPI_OOR_MASK (0xC00000000U) #define NOC_GICT_GICT_ERR27CTLR_DIS_SPI_OOR_SHIFT (34U) /*! DIS_SPI_OOR - DIS_SPI_OOR */ #define NOC_GICT_GICT_ERR27CTLR_DIS_SPI_OOR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_DIS_SPI_OOR_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_DIS_SPI_OOR_MASK) #define NOC_GICT_GICT_ERR27CTLR_DIS_SPI_DST_MASK (0x1000000000U) #define NOC_GICT_GICT_ERR27CTLR_DIS_SPI_DST_SHIFT (36U) /*! DIS_SPI_DST - DIS_SPI_DST */ #define NOC_GICT_GICT_ERR27CTLR_DIS_SPI_DST(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_DIS_SPI_DST_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_DIS_SPI_DST_MASK) #define NOC_GICT_GICT_ERR27CTLR_DIS_SGI_MASK (0x2000000000U) #define NOC_GICT_GICT_ERR27CTLR_DIS_SGI_SHIFT (37U) /*! DIS_SGI - DIS_SGI */ #define NOC_GICT_GICT_ERR27CTLR_DIS_SGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_DIS_SGI_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_DIS_SGI_MASK) #define NOC_GICT_GICT_ERR27CTLR_DIS_ACE_MASK (0x4000000000U) #define NOC_GICT_GICT_ERR27CTLR_DIS_ACE_SHIFT (38U) /*! DIS_ACE - DIS_ACE */ #define NOC_GICT_GICT_ERR27CTLR_DIS_ACE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_DIS_ACE_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_DIS_ACE_MASK) #define NOC_GICT_GICT_ERR27CTLR_RESERVED4_MASK (0xFFFFFF8000000000U) #define NOC_GICT_GICT_ERR27CTLR_RESERVED4_SHIFT (39U) /*! RESERVED4 - RESERVED4 */ #define NOC_GICT_GICT_ERR27CTLR_RESERVED4(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27CTLR_RESERVED4_SHIFT)) & NOC_GICT_GICT_ERR27CTLR_RESERVED4_MASK) /*! @} */ /*! @name GICT_ERR27STATUS - GICT_ERR27STATUS */ /*! @{ */ #define NOC_GICT_GICT_ERR27STATUS_SERR_MASK (0xFFU) #define NOC_GICT_GICT_ERR27STATUS_SERR_SHIFT (0U) /*! SERR - SERR */ #define NOC_GICT_GICT_ERR27STATUS_SERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_SERR_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_SERR_MASK) #define NOC_GICT_GICT_ERR27STATUS_IERR_MASK (0xFF00U) #define NOC_GICT_GICT_ERR27STATUS_IERR_SHIFT (8U) /*! IERR - IERR */ #define NOC_GICT_GICT_ERR27STATUS_IERR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_IERR_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_IERR_MASK) #define NOC_GICT_GICT_ERR27STATUS_RESERVED0_MASK (0xF0000U) #define NOC_GICT_GICT_ERR27STATUS_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR27STATUS_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_RESERVED0_MASK) #define NOC_GICT_GICT_ERR27STATUS_UET_MASK (0x300000U) #define NOC_GICT_GICT_ERR27STATUS_UET_SHIFT (20U) /*! UET - UET */ #define NOC_GICT_GICT_ERR27STATUS_UET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_UET_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_UET_MASK) #define NOC_GICT_GICT_ERR27STATUS_RESERVED1_MASK (0xC00000U) #define NOC_GICT_GICT_ERR27STATUS_RESERVED1_SHIFT (22U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_ERR27STATUS_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_RESERVED1_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_RESERVED1_MASK) #define NOC_GICT_GICT_ERR27STATUS_CE_MASK (0x3000000U) #define NOC_GICT_GICT_ERR27STATUS_CE_SHIFT (24U) /*! CE - CE */ #define NOC_GICT_GICT_ERR27STATUS_CE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_CE_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_CE_MASK) #define NOC_GICT_GICT_ERR27STATUS_MV_MASK (0x4000000U) #define NOC_GICT_GICT_ERR27STATUS_MV_SHIFT (26U) /*! MV - MV */ #define NOC_GICT_GICT_ERR27STATUS_MV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_MV_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_MV_MASK) #define NOC_GICT_GICT_ERR27STATUS_OF_MASK (0x8000000U) #define NOC_GICT_GICT_ERR27STATUS_OF_SHIFT (27U) /*! OF - OF */ #define NOC_GICT_GICT_ERR27STATUS_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_OF_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_OF_MASK) #define NOC_GICT_GICT_ERR27STATUS_ER_MASK (0x10000000U) #define NOC_GICT_GICT_ERR27STATUS_ER_SHIFT (28U) /*! ER - ER */ #define NOC_GICT_GICT_ERR27STATUS_ER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_ER_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_ER_MASK) #define NOC_GICT_GICT_ERR27STATUS_UE_MASK (0x20000000U) #define NOC_GICT_GICT_ERR27STATUS_UE_SHIFT (29U) /*! UE - UE */ #define NOC_GICT_GICT_ERR27STATUS_UE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_UE_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_UE_MASK) #define NOC_GICT_GICT_ERR27STATUS_V_MASK (0x40000000U) #define NOC_GICT_GICT_ERR27STATUS_V_SHIFT (30U) /*! V - V */ #define NOC_GICT_GICT_ERR27STATUS_V(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_V_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_V_MASK) #define NOC_GICT_GICT_ERR27STATUS_AV_MASK (0x80000000U) #define NOC_GICT_GICT_ERR27STATUS_AV_SHIFT (31U) /*! AV - AV */ #define NOC_GICT_GICT_ERR27STATUS_AV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_AV_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_AV_MASK) #define NOC_GICT_GICT_ERR27STATUS_RESERVED2_MASK (0xFFFFFFFF00000000U) #define NOC_GICT_GICT_ERR27STATUS_RESERVED2_SHIFT (32U) /*! RESERVED2 - RESERVED2 */ #define NOC_GICT_GICT_ERR27STATUS_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27STATUS_RESERVED2_SHIFT)) & NOC_GICT_GICT_ERR27STATUS_RESERVED2_MASK) /*! @} */ /*! @name GICT_ERR27ADDR - GICT_ERR27ADDR */ /*! @{ */ #define NOC_GICT_GICT_ERR27ADDR_PADDR_MASK (0xFFFFFFFFFU) #define NOC_GICT_GICT_ERR27ADDR_PADDR_SHIFT (0U) /*! PADDR - PADDR */ #define NOC_GICT_GICT_ERR27ADDR_PADDR(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27ADDR_PADDR_SHIFT)) & NOC_GICT_GICT_ERR27ADDR_PADDR_MASK) #define NOC_GICT_GICT_ERR27ADDR_RESERVED0_MASK (0x7FFFFFF000000000U) #define NOC_GICT_GICT_ERR27ADDR_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR27ADDR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27ADDR_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR27ADDR_RESERVED0_MASK) #define NOC_GICT_GICT_ERR27ADDR_NS_MASK (0x8000000000000000U) #define NOC_GICT_GICT_ERR27ADDR_NS_SHIFT (63U) /*! NS - NS */ #define NOC_GICT_GICT_ERR27ADDR_NS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27ADDR_NS_SHIFT)) & NOC_GICT_GICT_ERR27ADDR_NS_MASK) /*! @} */ /*! @name GICT_ERR27MISC0 - GICT_ERR27MISC0 */ /*! @{ */ #define NOC_GICT_GICT_ERR27MISC0_Data_MASK (0xFFFFFFFFU) #define NOC_GICT_GICT_ERR27MISC0_Data_SHIFT (0U) /*! Data - Data */ #define NOC_GICT_GICT_ERR27MISC0_Data(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27MISC0_Data_SHIFT)) & NOC_GICT_GICT_ERR27MISC0_Data_MASK) #define NOC_GICT_GICT_ERR27MISC0_CNT_MASK (0xFF00000000U) #define NOC_GICT_GICT_ERR27MISC0_CNT_SHIFT (32U) /*! CNT - CNT */ #define NOC_GICT_GICT_ERR27MISC0_CNT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27MISC0_CNT_SHIFT)) & NOC_GICT_GICT_ERR27MISC0_CNT_MASK) #define NOC_GICT_GICT_ERR27MISC0_OF_MASK (0x10000000000U) #define NOC_GICT_GICT_ERR27MISC0_OF_SHIFT (40U) /*! OF - OF */ #define NOC_GICT_GICT_ERR27MISC0_OF(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27MISC0_OF_SHIFT)) & NOC_GICT_GICT_ERR27MISC0_OF_MASK) #define NOC_GICT_GICT_ERR27MISC0_RE_MASK (0x20000000000U) #define NOC_GICT_GICT_ERR27MISC0_RE_SHIFT (41U) /*! RE - RE */ #define NOC_GICT_GICT_ERR27MISC0_RE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27MISC0_RE_SHIFT)) & NOC_GICT_GICT_ERR27MISC0_RE_MASK) #define NOC_GICT_GICT_ERR27MISC0_RESERVED0_MASK (0xFFFFFC0000000000U) #define NOC_GICT_GICT_ERR27MISC0_RESERVED0_SHIFT (42U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERR27MISC0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27MISC0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERR27MISC0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERR27MISC1 - GICT_ERR27MISC1 */ /*! @{ */ #define NOC_GICT_GICT_ERR27MISC1_DATA_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERR27MISC1_DATA_SHIFT (0U) /*! DATA - DATA */ #define NOC_GICT_GICT_ERR27MISC1_DATA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERR27MISC1_DATA_SHIFT)) & NOC_GICT_GICT_ERR27MISC1_DATA_MASK) /*! @} */ /*! @name GICT_ERRGSR0 - GICT_ERRGSR0 */ /*! @{ */ #define NOC_GICT_GICT_ERRGSR0_Status_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GICT_GICT_ERRGSR0_Status_SHIFT (0U) /*! Status - Status */ #define NOC_GICT_GICT_ERRGSR0_Status(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERRGSR0_Status_SHIFT)) & NOC_GICT_GICT_ERRGSR0_Status_MASK) /*! @} */ /*! @name GICT_ERRIRQCR0 - GICT_ERRIRQCR0 */ /*! @{ */ #define NOC_GICT_GICT_ERRIRQCR0_SPIID_MASK (0x1FFFU) #define NOC_GICT_GICT_ERRIRQCR0_SPIID_SHIFT (0U) /*! SPIID - SPIID */ #define NOC_GICT_GICT_ERRIRQCR0_SPIID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERRIRQCR0_SPIID_SHIFT)) & NOC_GICT_GICT_ERRIRQCR0_SPIID_MASK) #define NOC_GICT_GICT_ERRIRQCR0_RESERVED0_MASK (0xFFFFFFFFFFFFE000U) #define NOC_GICT_GICT_ERRIRQCR0_RESERVED0_SHIFT (13U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERRIRQCR0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERRIRQCR0_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERRIRQCR0_RESERVED0_MASK) /*! @} */ /*! @name GICT_ERRIRQCR1 - GICT_ERRIRQCR1 */ /*! @{ */ #define NOC_GICT_GICT_ERRIRQCR1_SPIID_MASK (0x1FFFU) #define NOC_GICT_GICT_ERRIRQCR1_SPIID_SHIFT (0U) /*! SPIID - SPIID */ #define NOC_GICT_GICT_ERRIRQCR1_SPIID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERRIRQCR1_SPIID_SHIFT)) & NOC_GICT_GICT_ERRIRQCR1_SPIID_MASK) #define NOC_GICT_GICT_ERRIRQCR1_RESERVED0_MASK (0xFFFFFFFFFFFFE000U) #define NOC_GICT_GICT_ERRIRQCR1_RESERVED0_SHIFT (13U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_ERRIRQCR1_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GICT_GICT_ERRIRQCR1_RESERVED0_SHIFT)) & NOC_GICT_GICT_ERRIRQCR1_RESERVED0_MASK) /*! @} */ /*! @name GICT_DEVARCH - GICT_DEVARCH */ /*! @{ */ #define NOC_GICT_GICT_DEVARCH_ARCHID_MASK (0xFFFU) #define NOC_GICT_GICT_DEVARCH_ARCHID_SHIFT (0U) /*! ARCHID - ARCHID */ #define NOC_GICT_GICT_DEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_DEVARCH_ARCHID_SHIFT)) & NOC_GICT_GICT_DEVARCH_ARCHID_MASK) #define NOC_GICT_GICT_DEVARCH_RESERVED0_MASK (0xF000U) #define NOC_GICT_GICT_DEVARCH_RESERVED0_SHIFT (12U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_DEVARCH_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_DEVARCH_RESERVED0_SHIFT)) & NOC_GICT_GICT_DEVARCH_RESERVED0_MASK) #define NOC_GICT_GICT_DEVARCH_REVISION_MASK (0xF0000U) #define NOC_GICT_GICT_DEVARCH_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define NOC_GICT_GICT_DEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_DEVARCH_REVISION_SHIFT)) & NOC_GICT_GICT_DEVARCH_REVISION_MASK) #define NOC_GICT_GICT_DEVARCH_PRESENT_MASK (0x100000U) #define NOC_GICT_GICT_DEVARCH_PRESENT_SHIFT (20U) /*! PRESENT - PRESENT */ #define NOC_GICT_GICT_DEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_DEVARCH_PRESENT_SHIFT)) & NOC_GICT_GICT_DEVARCH_PRESENT_MASK) #define NOC_GICT_GICT_DEVARCH_ARCHITECT_MASK (0xFFE00000U) #define NOC_GICT_GICT_DEVARCH_ARCHITECT_SHIFT (21U) /*! ARCHITECT - ARCHITECT */ #define NOC_GICT_GICT_DEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_DEVARCH_ARCHITECT_SHIFT)) & NOC_GICT_GICT_DEVARCH_ARCHITECT_MASK) /*! @} */ /*! @name GICT_DEVID - GICT_DEVID */ /*! @{ */ #define NOC_GICT_GICT_DEVID_NumRecords_MASK (0xFFFFU) #define NOC_GICT_GICT_DEVID_NumRecords_SHIFT (0U) /*! NumRecords - NumRecords */ #define NOC_GICT_GICT_DEVID_NumRecords(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_DEVID_NumRecords_SHIFT)) & NOC_GICT_GICT_DEVID_NumRecords_MASK) #define NOC_GICT_GICT_DEVID_RESERVED0_MASK (0xFFFF0000U) #define NOC_GICT_GICT_DEVID_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_DEVID_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_DEVID_RESERVED0_SHIFT)) & NOC_GICT_GICT_DEVID_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR4 - GICT_PIDR4 */ /*! @{ */ #define NOC_GICT_GICT_PIDR4_DES_2_MASK (0xFU) #define NOC_GICT_GICT_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GICT_GICT_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR4_DES_2_SHIFT)) & NOC_GICT_GICT_PIDR4_DES_2_MASK) #define NOC_GICT_GICT_PIDR4_SIZE_MASK (0xF0U) #define NOC_GICT_GICT_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GICT_GICT_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR4_SIZE_SHIFT)) & NOC_GICT_GICT_PIDR4_SIZE_MASK) #define NOC_GICT_GICT_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR4_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR5 - GICT_PIDR5 */ /*! @{ */ #define NOC_GICT_GICT_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GICT_GICT_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICT_GICT_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR5_RESERVED_SHIFT)) & NOC_GICT_GICT_PIDR5_RESERVED_MASK) #define NOC_GICT_GICT_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR5_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR6 - GICT_PIDR6 */ /*! @{ */ #define NOC_GICT_GICT_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GICT_GICT_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICT_GICT_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR6_RESERVED_SHIFT)) & NOC_GICT_GICT_PIDR6_RESERVED_MASK) #define NOC_GICT_GICT_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR6_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR7 - GICT_PIDR7 */ /*! @{ */ #define NOC_GICT_GICT_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GICT_GICT_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GICT_GICT_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR7_RESERVED_SHIFT)) & NOC_GICT_GICT_PIDR7_RESERVED_MASK) #define NOC_GICT_GICT_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR7_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR0 - GICT_PIDR0 */ /*! @{ */ #define NOC_GICT_GICT_PIDR0_PART_0_MASK (0xFFU) #define NOC_GICT_GICT_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GICT_GICT_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR0_PART_0_SHIFT)) & NOC_GICT_GICT_PIDR0_PART_0_MASK) #define NOC_GICT_GICT_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR0_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR1 - GICT_PIDR1 */ /*! @{ */ #define NOC_GICT_GICT_PIDR1_PART_1_MASK (0xFU) #define NOC_GICT_GICT_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GICT_GICT_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR1_PART_1_SHIFT)) & NOC_GICT_GICT_PIDR1_PART_1_MASK) #define NOC_GICT_GICT_PIDR1_DES_0_MASK (0xF0U) #define NOC_GICT_GICT_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GICT_GICT_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR1_DES_0_SHIFT)) & NOC_GICT_GICT_PIDR1_DES_0_MASK) #define NOC_GICT_GICT_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR1_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR2 - GICT_PIDR2 */ /*! @{ */ #define NOC_GICT_GICT_PIDR2_DES_1_MASK (0x7U) #define NOC_GICT_GICT_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GICT_GICT_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR2_DES_1_SHIFT)) & NOC_GICT_GICT_PIDR2_DES_1_MASK) #define NOC_GICT_GICT_PIDR2_JEDEC_MASK (0x8U) #define NOC_GICT_GICT_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GICT_GICT_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR2_JEDEC_SHIFT)) & NOC_GICT_GICT_PIDR2_JEDEC_MASK) #define NOC_GICT_GICT_PIDR2_REVISION_MASK (0xF0U) #define NOC_GICT_GICT_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GICT_GICT_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR2_REVISION_SHIFT)) & NOC_GICT_GICT_PIDR2_REVISION_MASK) #define NOC_GICT_GICT_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR2_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICT_PIDR3 - GICT_PIDR3 */ /*! @{ */ #define NOC_GICT_GICT_PIDR3_CMOD_MASK (0x7U) #define NOC_GICT_GICT_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GICT_GICT_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR3_CMOD_SHIFT)) & NOC_GICT_GICT_PIDR3_CMOD_MASK) #define NOC_GICT_GICT_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GICT_GICT_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR3_RESERVED0_SHIFT)) & NOC_GICT_GICT_PIDR3_RESERVED0_MASK) #define NOC_GICT_GICT_PIDR3_REVAND_MASK (0xF0U) #define NOC_GICT_GICT_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GICT_GICT_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR3_REVAND_SHIFT)) & NOC_GICT_GICT_PIDR3_REVAND_MASK) #define NOC_GICT_GICT_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GICT_GICT_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_PIDR3_RESERVED1_SHIFT)) & NOC_GICT_GICT_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GICT_CIDR0 - GICT_CIDR0 */ /*! @{ */ #define NOC_GICT_GICT_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GICT_GICT_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GICT_GICT_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR0_PRMBL_0_SHIFT)) & NOC_GICT_GICT_CIDR0_PRMBL_0_MASK) #define NOC_GICT_GICT_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR0_RESERVED0_SHIFT)) & NOC_GICT_GICT_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GICT_CIDR1 - GICT_CIDR1 */ /*! @{ */ #define NOC_GICT_GICT_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GICT_GICT_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GICT_GICT_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR1_PRMBL_1_SHIFT)) & NOC_GICT_GICT_CIDR1_PRMBL_1_MASK) #define NOC_GICT_GICT_CIDR1_CLASS_MASK (0xF0U) #define NOC_GICT_GICT_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GICT_GICT_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR1_CLASS_SHIFT)) & NOC_GICT_GICT_CIDR1_CLASS_MASK) #define NOC_GICT_GICT_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR1_RESERVED0_SHIFT)) & NOC_GICT_GICT_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GICT_CIDR2 - GICT_CIDR2 */ /*! @{ */ #define NOC_GICT_GICT_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GICT_GICT_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GICT_GICT_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR2_PRMBL_2_SHIFT)) & NOC_GICT_GICT_CIDR2_PRMBL_2_MASK) #define NOC_GICT_GICT_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR2_RESERVED0_SHIFT)) & NOC_GICT_GICT_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GICT_CIDR3 - GICT_CIDR3 */ /*! @{ */ #define NOC_GICT_GICT_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GICT_GICT_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GICT_GICT_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR3_PRMBL_3_SHIFT)) & NOC_GICT_GICT_CIDR3_PRMBL_3_MASK) #define NOC_GICT_GICT_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GICT_GICT_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GICT_GICT_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GICT_GICT_CIDR3_RESERVED0_SHIFT)) & NOC_GICT_GICT_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GICT_Register_Masks */ /* NOC_GICT - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GICT base address */ #define NOC__GIC__GICT_BASE (0x48020000u) /** Peripheral NOC__GIC__GICT base pointer */ #define NOC__GIC__GICT ((NOC_GICT_Type *)NOC__GIC__GICT_BASE) /** Array initializer of NOC_GICT peripheral base addresses */ #define NOC_GICT_BASE_ADDRS { NOC__GIC__GICT_BASE } /** Array initializer of NOC_GICT peripheral base pointers */ #define NOC_GICT_BASE_PTRS { NOC__GIC__GICT } /*! * @} */ /* end of group NOC_GICT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GITS0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GITS0_Peripheral_Access_Layer NOC_GITS0 Peripheral Access Layer * @{ */ /** NOC_GITS0 - Register Layout Typedef */ typedef struct { __IO uint32_t GITS0_CTLR; /**< GITS0_CTLR, offset: 0x0 */ __I uint32_t GITS0_IIDR; /**< GITS0_IIDR, offset: 0x4 */ __I uint64_t GITS0_TYPER; /**< GITS0_TYPER, offset: 0x8 */ __I uint32_t GITS0_MPAMIDR; /**< GITS0_MPAMIDR, offset: 0x10 */ __IO uint32_t GITS0_PARTIDR; /**< GITS0_PARTIDR, offset: 0x14 */ __I uint32_t GITS0_MPIDR; /**< GITS0_MPIDR, offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t GITS0_FCTLR; /**< GITS0_FCTLR, offset: 0x20 */ uint8_t RESERVED_1[4]; __IO uint64_t GITS0_OPR; /**< GITS0_OPR, offset: 0x28 */ __I uint64_t GITS0_OPSR; /**< GITS0_OPSR, offset: 0x30 */ uint8_t RESERVED_2[72]; __IO uint64_t GITS0_CBASER; /**< GITS0_CBASER, offset: 0x80 */ __IO uint64_t GITS0_CWRITER; /**< GITS0_CWRITER, offset: 0x88 */ __I uint64_t GITS0_CREADR; /**< GITS0_CREADR, offset: 0x90 */ uint8_t RESERVED_3[104]; __IO uint64_t GITS0_BASER0; /**< GITS0_BASER0, offset: 0x100 */ __IO uint64_t GITS0_BASER1; /**< GITS0_BASER1, offset: 0x108 */ __I uint64_t GITS0_BASER2; /**< GITS0_BASER2, offset: 0x110 */ __I uint64_t GITS0_BASER3; /**< GITS0_BASER3, offset: 0x118 */ __I uint64_t GITS0_BASER4; /**< GITS0_BASER4, offset: 0x120 */ __I uint64_t GITS0_BASER5; /**< GITS0_BASER5, offset: 0x128 */ __I uint64_t GITS0_BASER6; /**< GITS0_BASER6, offset: 0x130 */ __I uint64_t GITS0_BASER7; /**< GITS0_BASER7, offset: 0x138 */ uint8_t RESERVED_4[61120]; __I uint64_t GITS0_CFGID; /**< GITS0_CFGID, offset: 0xF000 */ uint8_t RESERVED_5[4040]; __I uint32_t GITS0_PIDR4; /**< GITS0_PIDR4, offset: 0xFFD0 */ __I uint32_t GITS0_PIDR5; /**< GITS0_PIDR5, offset: 0xFFD4 */ __I uint32_t GITS0_PIDR6; /**< GITS0_PIDR6, offset: 0xFFD8 */ __I uint32_t GITS0_PIDR7; /**< GITS0_PIDR7, offset: 0xFFDC */ __I uint32_t GITS0_PIDR0; /**< GITS0_PIDR0, offset: 0xFFE0 */ __I uint32_t GITS0_PIDR1; /**< GITS0_PIDR1, offset: 0xFFE4 */ __I uint32_t GITS0_PIDR2; /**< GITS0_PIDR2, offset: 0xFFE8 */ __I uint32_t GITS0_PIDR3; /**< GITS0_PIDR3, offset: 0xFFEC */ __I uint32_t GITS0_CIDR0; /**< GITS0_CIDR0, offset: 0xFFF0 */ __I uint32_t GITS0_CIDR1; /**< GITS0_CIDR1, offset: 0xFFF4 */ __I uint32_t GITS0_CIDR2; /**< GITS0_CIDR2, offset: 0xFFF8 */ __I uint32_t GITS0_CIDR3; /**< GITS0_CIDR3, offset: 0xFFFC */ } NOC_GITS0_Type; /* ---------------------------------------------------------------------------- -- NOC_GITS0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GITS0_Register_Masks NOC_GITS0 Register Masks * @{ */ /*! @name GITS0_CTLR - GITS0_CTLR */ /*! @{ */ #define NOC_GITS0_GITS0_CTLR_Enabled_MASK (0x1U) #define NOC_GITS0_GITS0_CTLR_Enabled_SHIFT (0U) /*! Enabled - Enabled */ #define NOC_GITS0_GITS0_CTLR_Enabled(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CTLR_Enabled_SHIFT)) & NOC_GITS0_GITS0_CTLR_Enabled_MASK) #define NOC_GITS0_GITS0_CTLR_RESERVED0_MASK (0x7FFFFFFEU) #define NOC_GITS0_GITS0_CTLR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CTLR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CTLR_RESERVED0_MASK) #define NOC_GITS0_GITS0_CTLR_Quiescent_MASK (0x80000000U) #define NOC_GITS0_GITS0_CTLR_Quiescent_SHIFT (31U) /*! Quiescent - Quiescent */ #define NOC_GITS0_GITS0_CTLR_Quiescent(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CTLR_Quiescent_SHIFT)) & NOC_GITS0_GITS0_CTLR_Quiescent_MASK) /*! @} */ /*! @name GITS0_IIDR - GITS0_IIDR */ /*! @{ */ #define NOC_GITS0_GITS0_IIDR_Implementer_MASK (0xFFFU) #define NOC_GITS0_GITS0_IIDR_Implementer_SHIFT (0U) /*! Implementer - Implementer */ #define NOC_GITS0_GITS0_IIDR_Implementer(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_IIDR_Implementer_SHIFT)) & NOC_GITS0_GITS0_IIDR_Implementer_MASK) #define NOC_GITS0_GITS0_IIDR_Revision_MASK (0xF000U) #define NOC_GITS0_GITS0_IIDR_Revision_SHIFT (12U) /*! Revision - Revision */ #define NOC_GITS0_GITS0_IIDR_Revision(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_IIDR_Revision_SHIFT)) & NOC_GITS0_GITS0_IIDR_Revision_MASK) #define NOC_GITS0_GITS0_IIDR_Variant_MASK (0xF0000U) #define NOC_GITS0_GITS0_IIDR_Variant_SHIFT (16U) /*! Variant - Variant */ #define NOC_GITS0_GITS0_IIDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_IIDR_Variant_SHIFT)) & NOC_GITS0_GITS0_IIDR_Variant_MASK) #define NOC_GITS0_GITS0_IIDR_RESERVED0_MASK (0xF00000U) #define NOC_GITS0_GITS0_IIDR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_IIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_IIDR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_IIDR_RESERVED0_MASK) #define NOC_GITS0_GITS0_IIDR_ProductID_MASK (0xFF000000U) #define NOC_GITS0_GITS0_IIDR_ProductID_SHIFT (24U) /*! ProductID - ProductID */ #define NOC_GITS0_GITS0_IIDR_ProductID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_IIDR_ProductID_SHIFT)) & NOC_GITS0_GITS0_IIDR_ProductID_MASK) /*! @} */ /*! @name GITS0_TYPER - GITS0_TYPER */ /*! @{ */ #define NOC_GITS0_GITS0_TYPER_Physical_MASK (0x1U) #define NOC_GITS0_GITS0_TYPER_Physical_SHIFT (0U) /*! Physical - Physical */ #define NOC_GITS0_GITS0_TYPER_Physical(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_Physical_SHIFT)) & NOC_GITS0_GITS0_TYPER_Physical_MASK) #define NOC_GITS0_GITS0_TYPER_Virtual_MASK (0x2U) #define NOC_GITS0_GITS0_TYPER_Virtual_SHIFT (1U) /*! Virtual - Virtual */ #define NOC_GITS0_GITS0_TYPER_Virtual(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_Virtual_SHIFT)) & NOC_GITS0_GITS0_TYPER_Virtual_MASK) #define NOC_GITS0_GITS0_TYPER_CCT_MASK (0x4U) #define NOC_GITS0_GITS0_TYPER_CCT_SHIFT (2U) /*! CCT - CCT */ #define NOC_GITS0_GITS0_TYPER_CCT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_CCT_SHIFT)) & NOC_GITS0_GITS0_TYPER_CCT_MASK) #define NOC_GITS0_GITS0_TYPER_RESERVED0_MASK (0x8U) #define NOC_GITS0_GITS0_TYPER_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_TYPER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_TYPER_RESERVED0_MASK) #define NOC_GITS0_GITS0_TYPER_ITTEntrySize_MASK (0xF0U) #define NOC_GITS0_GITS0_TYPER_ITTEntrySize_SHIFT (4U) /*! ITTEntrySize - ITTEntrySize */ #define NOC_GITS0_GITS0_TYPER_ITTEntrySize(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_ITTEntrySize_SHIFT)) & NOC_GITS0_GITS0_TYPER_ITTEntrySize_MASK) #define NOC_GITS0_GITS0_TYPER_IDBits_MASK (0x1F00U) #define NOC_GITS0_GITS0_TYPER_IDBits_SHIFT (8U) /*! IDBits - IDBits */ #define NOC_GITS0_GITS0_TYPER_IDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_IDBits_SHIFT)) & NOC_GITS0_GITS0_TYPER_IDBits_MASK) #define NOC_GITS0_GITS0_TYPER_DevBits_MASK (0x3E000U) #define NOC_GITS0_GITS0_TYPER_DevBits_SHIFT (13U) /*! DevBits - DevBits */ #define NOC_GITS0_GITS0_TYPER_DevBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_DevBits_SHIFT)) & NOC_GITS0_GITS0_TYPER_DevBits_MASK) #define NOC_GITS0_GITS0_TYPER_SEIS_MASK (0x40000U) #define NOC_GITS0_GITS0_TYPER_SEIS_SHIFT (18U) /*! SEIS - SEIS */ #define NOC_GITS0_GITS0_TYPER_SEIS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_SEIS_SHIFT)) & NOC_GITS0_GITS0_TYPER_SEIS_MASK) #define NOC_GITS0_GITS0_TYPER_PTA_MASK (0x80000U) #define NOC_GITS0_GITS0_TYPER_PTA_SHIFT (19U) /*! PTA - PTA */ #define NOC_GITS0_GITS0_TYPER_PTA(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_PTA_SHIFT)) & NOC_GITS0_GITS0_TYPER_PTA_MASK) #define NOC_GITS0_GITS0_TYPER_RESERVED1_MASK (0xF00000U) #define NOC_GITS0_GITS0_TYPER_RESERVED1_SHIFT (20U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_TYPER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_TYPER_RESERVED1_MASK) #define NOC_GITS0_GITS0_TYPER_HCC_MASK (0xFF000000U) #define NOC_GITS0_GITS0_TYPER_HCC_SHIFT (24U) /*! HCC - HCC */ #define NOC_GITS0_GITS0_TYPER_HCC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_HCC_SHIFT)) & NOC_GITS0_GITS0_TYPER_HCC_MASK) #define NOC_GITS0_GITS0_TYPER_CIDBits_MASK (0xF00000000U) #define NOC_GITS0_GITS0_TYPER_CIDBits_SHIFT (32U) /*! CIDBits - CIDBits */ #define NOC_GITS0_GITS0_TYPER_CIDBits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_CIDBits_SHIFT)) & NOC_GITS0_GITS0_TYPER_CIDBits_MASK) #define NOC_GITS0_GITS0_TYPER_CIL_MASK (0x1000000000U) #define NOC_GITS0_GITS0_TYPER_CIL_SHIFT (36U) /*! CIL - CIL */ #define NOC_GITS0_GITS0_TYPER_CIL(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_CIL_SHIFT)) & NOC_GITS0_GITS0_TYPER_CIL_MASK) #define NOC_GITS0_GITS0_TYPER_VMOVP_MASK (0x2000000000U) #define NOC_GITS0_GITS0_TYPER_VMOVP_SHIFT (37U) /*! VMOVP - VMOVP */ #define NOC_GITS0_GITS0_TYPER_VMOVP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_VMOVP_SHIFT)) & NOC_GITS0_GITS0_TYPER_VMOVP_MASK) #define NOC_GITS0_GITS0_TYPER_MPAM_MASK (0x4000000000U) #define NOC_GITS0_GITS0_TYPER_MPAM_SHIFT (38U) /*! MPAM - MPAM */ #define NOC_GITS0_GITS0_TYPER_MPAM(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_MPAM_SHIFT)) & NOC_GITS0_GITS0_TYPER_MPAM_MASK) #define NOC_GITS0_GITS0_TYPER_VSGI_MASK (0x8000000000U) #define NOC_GITS0_GITS0_TYPER_VSGI_SHIFT (39U) /*! VSGI - VSGI */ #define NOC_GITS0_GITS0_TYPER_VSGI(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_VSGI_SHIFT)) & NOC_GITS0_GITS0_TYPER_VSGI_MASK) #define NOC_GITS0_GITS0_TYPER_VMAPP_MASK (0x10000000000U) #define NOC_GITS0_GITS0_TYPER_VMAPP_SHIFT (40U) /*! VMAPP - VMAPP */ #define NOC_GITS0_GITS0_TYPER_VMAPP(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_VMAPP_SHIFT)) & NOC_GITS0_GITS0_TYPER_VMAPP_MASK) #define NOC_GITS0_GITS0_TYPER_SVPET_MASK (0x60000000000U) #define NOC_GITS0_GITS0_TYPER_SVPET_SHIFT (41U) /*! SVPET - SVPET */ #define NOC_GITS0_GITS0_TYPER_SVPET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_SVPET_SHIFT)) & NOC_GITS0_GITS0_TYPER_SVPET_MASK) #define NOC_GITS0_GITS0_TYPER_nID_MASK (0x80000000000U) #define NOC_GITS0_GITS0_TYPER_nID_SHIFT (43U) /*! nID - nID */ #define NOC_GITS0_GITS0_TYPER_nID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_nID_SHIFT)) & NOC_GITS0_GITS0_TYPER_nID_MASK) #define NOC_GITS0_GITS0_TYPER_RESERVED2_MASK (0x300000000000U) #define NOC_GITS0_GITS0_TYPER_RESERVED2_SHIFT (44U) /*! RESERVED2 - RESERVED2 */ #define NOC_GITS0_GITS0_TYPER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_RESERVED2_SHIFT)) & NOC_GITS0_GITS0_TYPER_RESERVED2_MASK) #define NOC_GITS0_GITS0_TYPER_INV_MASK (0x400000000000U) #define NOC_GITS0_GITS0_TYPER_INV_SHIFT (46U) /*! INV - INV */ #define NOC_GITS0_GITS0_TYPER_INV(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_INV_SHIFT)) & NOC_GITS0_GITS0_TYPER_INV_MASK) #define NOC_GITS0_GITS0_TYPER_RESERVED3_MASK (0xFFFF800000000000U) #define NOC_GITS0_GITS0_TYPER_RESERVED3_SHIFT (47U) /*! RESERVED3 - RESERVED3 */ #define NOC_GITS0_GITS0_TYPER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_TYPER_RESERVED3_SHIFT)) & NOC_GITS0_GITS0_TYPER_RESERVED3_MASK) /*! @} */ /*! @name GITS0_MPAMIDR - GITS0_MPAMIDR */ /*! @{ */ #define NOC_GITS0_GITS0_MPAMIDR_PARTID_MAX_MASK (0xFFFFU) #define NOC_GITS0_GITS0_MPAMIDR_PARTID_MAX_SHIFT (0U) /*! PARTID_MAX - PARTID_MAX */ #define NOC_GITS0_GITS0_MPAMIDR_PARTID_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_MPAMIDR_PARTID_MAX_SHIFT)) & NOC_GITS0_GITS0_MPAMIDR_PARTID_MAX_MASK) #define NOC_GITS0_GITS0_MPAMIDR_PMG_MAX_MASK (0xFF0000U) #define NOC_GITS0_GITS0_MPAMIDR_PMG_MAX_SHIFT (16U) /*! PMG_MAX - PMG_MAX */ #define NOC_GITS0_GITS0_MPAMIDR_PMG_MAX(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_MPAMIDR_PMG_MAX_SHIFT)) & NOC_GITS0_GITS0_MPAMIDR_PMG_MAX_MASK) #define NOC_GITS0_GITS0_MPAMIDR_RESERVED0_MASK (0xFF000000U) #define NOC_GITS0_GITS0_MPAMIDR_RESERVED0_SHIFT (24U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_MPAMIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_MPAMIDR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_MPAMIDR_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PARTIDR - GITS0_PARTIDR */ /*! @{ */ #define NOC_GITS0_GITS0_PARTIDR_PARTID_MASK (0x1FFU) #define NOC_GITS0_GITS0_PARTIDR_PARTID_SHIFT (0U) /*! PARTID - PARTID */ #define NOC_GITS0_GITS0_PARTIDR_PARTID(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PARTIDR_PARTID_SHIFT)) & NOC_GITS0_GITS0_PARTIDR_PARTID_MASK) #define NOC_GITS0_GITS0_PARTIDR_RESERVED0_MASK (0xFE00U) #define NOC_GITS0_GITS0_PARTIDR_RESERVED0_SHIFT (9U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PARTIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PARTIDR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PARTIDR_RESERVED0_MASK) #define NOC_GITS0_GITS0_PARTIDR_PMG_MASK (0x10000U) #define NOC_GITS0_GITS0_PARTIDR_PMG_SHIFT (16U) /*! PMG - PMG */ #define NOC_GITS0_GITS0_PARTIDR_PMG(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PARTIDR_PMG_SHIFT)) & NOC_GITS0_GITS0_PARTIDR_PMG_MASK) #define NOC_GITS0_GITS0_PARTIDR_RESERVED1_MASK (0xFFFE0000U) #define NOC_GITS0_GITS0_PARTIDR_RESERVED1_SHIFT (17U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_PARTIDR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PARTIDR_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_PARTIDR_RESERVED1_MASK) /*! @} */ /*! @name GITS0_MPIDR - GITS0_MPIDR */ /*! @{ */ #define NOC_GITS0_GITS0_MPIDR_RESERVED0_MASK (0xFFU) #define NOC_GITS0_GITS0_MPIDR_RESERVED0_SHIFT (0U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_MPIDR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_MPIDR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_MPIDR_RESERVED0_MASK) #define NOC_GITS0_GITS0_MPIDR_Aff1_MASK (0xFF00U) #define NOC_GITS0_GITS0_MPIDR_Aff1_SHIFT (8U) /*! Aff1 - Aff1 */ #define NOC_GITS0_GITS0_MPIDR_Aff1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_MPIDR_Aff1_SHIFT)) & NOC_GITS0_GITS0_MPIDR_Aff1_MASK) #define NOC_GITS0_GITS0_MPIDR_Aff2_MASK (0xFF0000U) #define NOC_GITS0_GITS0_MPIDR_Aff2_SHIFT (16U) /*! Aff2 - Aff2 */ #define NOC_GITS0_GITS0_MPIDR_Aff2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_MPIDR_Aff2_SHIFT)) & NOC_GITS0_GITS0_MPIDR_Aff2_MASK) #define NOC_GITS0_GITS0_MPIDR_Aff3_MASK (0xFF000000U) #define NOC_GITS0_GITS0_MPIDR_Aff3_SHIFT (24U) /*! Aff3 - Aff3 */ #define NOC_GITS0_GITS0_MPIDR_Aff3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_MPIDR_Aff3_SHIFT)) & NOC_GITS0_GITS0_MPIDR_Aff3_MASK) /*! @} */ /*! @name GITS0_FCTLR - GITS0_FCTLR */ /*! @{ */ #define NOC_GITS0_GITS0_FCTLR_SIP_MASK (0x1U) #define NOC_GITS0_GITS0_FCTLR_SIP_SHIFT (0U) /*! SIP - SIP */ #define NOC_GITS0_GITS0_FCTLR_SIP(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_SIP_SHIFT)) & NOC_GITS0_GITS0_FCTLR_SIP_MASK) #define NOC_GITS0_GITS0_FCTLR_LTE_MASK (0x2U) #define NOC_GITS0_GITS0_FCTLR_LTE_SHIFT (1U) /*! LTE - LTE */ #define NOC_GITS0_GITS0_FCTLR_LTE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_LTE_SHIFT)) & NOC_GITS0_GITS0_FCTLR_LTE_MASK) #define NOC_GITS0_GITS0_FCTLR_UEE_MASK (0x4U) #define NOC_GITS0_GITS0_FCTLR_UEE_SHIFT (2U) /*! UEE - UEE */ #define NOC_GITS0_GITS0_FCTLR_UEE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_UEE_SHIFT)) & NOC_GITS0_GITS0_FCTLR_UEE_MASK) #define NOC_GITS0_GITS0_FCTLR_CEE_MASK (0x8U) #define NOC_GITS0_GITS0_FCTLR_CEE_SHIFT (3U) /*! CEE - CEE */ #define NOC_GITS0_GITS0_FCTLR_CEE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_CEE_SHIFT)) & NOC_GITS0_GITS0_FCTLR_CEE_MASK) #define NOC_GITS0_GITS0_FCTLR_CGO_MASK (0x70U) #define NOC_GITS0_GITS0_FCTLR_CGO_SHIFT (4U) /*! CGO - CGO */ #define NOC_GITS0_GITS0_FCTLR_CGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_CGO_SHIFT)) & NOC_GITS0_GITS0_FCTLR_CGO_MASK) #define NOC_GITS0_GITS0_FCTLR_LEO_MASK (0x80U) #define NOC_GITS0_GITS0_FCTLR_LEO_SHIFT (7U) /*! LEO - LEO */ #define NOC_GITS0_GITS0_FCTLR_LEO(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_LEO_SHIFT)) & NOC_GITS0_GITS0_FCTLR_LEO_MASK) #define NOC_GITS0_GITS0_FCTLR_AEE_MASK (0x100U) #define NOC_GITS0_GITS0_FCTLR_AEE_SHIFT (8U) /*! AEE - AEE */ #define NOC_GITS0_GITS0_FCTLR_AEE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_AEE_SHIFT)) & NOC_GITS0_GITS0_FCTLR_AEE_MASK) #define NOC_GITS0_GITS0_FCTLR_QD_MASK (0x200U) #define NOC_GITS0_GITS0_FCTLR_QD_SHIFT (9U) /*! QD - QD */ #define NOC_GITS0_GITS0_FCTLR_QD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_QD_SHIFT)) & NOC_GITS0_GITS0_FCTLR_QD_MASK) #define NOC_GITS0_GITS0_FCTLR_QAK_MASK (0x400U) #define NOC_GITS0_GITS0_FCTLR_QAK_SHIFT (10U) /*! QAK - QAK */ #define NOC_GITS0_GITS0_FCTLR_QAK(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_QAK_SHIFT)) & NOC_GITS0_GITS0_FCTLR_QAK_MASK) #define NOC_GITS0_GITS0_FCTLR_poison_check_MASK (0x800U) #define NOC_GITS0_GITS0_FCTLR_poison_check_SHIFT (11U) /*! poison_check - poison_check */ #define NOC_GITS0_GITS0_FCTLR_poison_check(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_poison_check_SHIFT)) & NOC_GITS0_GITS0_FCTLR_poison_check_MASK) #define NOC_GITS0_GITS0_FCTLR_ll_lpi_cr_init_MASK (0x3000U) #define NOC_GITS0_GITS0_FCTLR_ll_lpi_cr_init_SHIFT (12U) /*! ll_lpi_cr_init - ll_lpi_cr_init */ #define NOC_GITS0_GITS0_FCTLR_ll_lpi_cr_init(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_ll_lpi_cr_init_SHIFT)) & NOC_GITS0_GITS0_FCTLR_ll_lpi_cr_init_MASK) #define NOC_GITS0_GITS0_FCTLR_RESERVED0_MASK (0xC000U) #define NOC_GITS0_GITS0_FCTLR_RESERVED0_SHIFT (14U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_FCTLR_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_FCTLR_RESERVED0_MASK) #define NOC_GITS0_GITS0_FCTLR_ICC_MASK (0x10000U) #define NOC_GITS0_GITS0_FCTLR_ICC_SHIFT (16U) /*! ICC - ICC */ #define NOC_GITS0_GITS0_FCTLR_ICC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_ICC_SHIFT)) & NOC_GITS0_GITS0_FCTLR_ICC_MASK) #define NOC_GITS0_GITS0_FCTLR_IDC_MASK (0x20000U) #define NOC_GITS0_GITS0_FCTLR_IDC_SHIFT (17U) /*! IDC - IDC */ #define NOC_GITS0_GITS0_FCTLR_IDC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_IDC_SHIFT)) & NOC_GITS0_GITS0_FCTLR_IDC_MASK) #define NOC_GITS0_GITS0_FCTLR_IEC_MASK (0x40000U) #define NOC_GITS0_GITS0_FCTLR_IEC_SHIFT (18U) /*! IEC - IEC */ #define NOC_GITS0_GITS0_FCTLR_IEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_IEC_SHIFT)) & NOC_GITS0_GITS0_FCTLR_IEC_MASK) #define NOC_GITS0_GITS0_FCTLR_RESERVED1_MASK (0x80000U) #define NOC_GITS0_GITS0_FCTLR_RESERVED1_SHIFT (19U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_FCTLR_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_FCTLR_RESERVED1_MASK) #define NOC_GITS0_GITS0_FCTLR_lpi_cr_init_MASK (0xF00000U) #define NOC_GITS0_GITS0_FCTLR_lpi_cr_init_SHIFT (20U) /*! lpi_cr_init - lpi_cr_init */ #define NOC_GITS0_GITS0_FCTLR_lpi_cr_init(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_lpi_cr_init_SHIFT)) & NOC_GITS0_GITS0_FCTLR_lpi_cr_init_MASK) #define NOC_GITS0_GITS0_FCTLR_RESERVED2_MASK (0xF000000U) #define NOC_GITS0_GITS0_FCTLR_RESERVED2_SHIFT (24U) /*! RESERVED2 - RESERVED2 */ #define NOC_GITS0_GITS0_FCTLR_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_RESERVED2_SHIFT)) & NOC_GITS0_GITS0_FCTLR_RESERVED2_MASK) #define NOC_GITS0_GITS0_FCTLR_cmd_flush_MASK (0x30000000U) #define NOC_GITS0_GITS0_FCTLR_cmd_flush_SHIFT (28U) /*! cmd_flush - cmd_flush */ #define NOC_GITS0_GITS0_FCTLR_cmd_flush(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_cmd_flush_SHIFT)) & NOC_GITS0_GITS0_FCTLR_cmd_flush_MASK) #define NOC_GITS0_GITS0_FCTLR_PWE_MASK (0x40000000U) #define NOC_GITS0_GITS0_FCTLR_PWE_SHIFT (30U) /*! PWE - PWE */ #define NOC_GITS0_GITS0_FCTLR_PWE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_PWE_SHIFT)) & NOC_GITS0_GITS0_FCTLR_PWE_MASK) #define NOC_GITS0_GITS0_FCTLR_DCC_MASK (0x80000000U) #define NOC_GITS0_GITS0_FCTLR_DCC_SHIFT (31U) /*! DCC - DCC */ #define NOC_GITS0_GITS0_FCTLR_DCC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_FCTLR_DCC_SHIFT)) & NOC_GITS0_GITS0_FCTLR_DCC_MASK) /*! @} */ /*! @name GITS0_OPR - GITS0_OPR */ /*! @{ */ #define NOC_GITS0_GITS0_OPR_EVENT_ID_MASK (0xFFFFFU) #define NOC_GITS0_GITS0_OPR_EVENT_ID_SHIFT (0U) /*! EVENT_ID - EVENT_ID */ #define NOC_GITS0_GITS0_OPR_EVENT_ID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPR_EVENT_ID_SHIFT)) & NOC_GITS0_GITS0_OPR_EVENT_ID_MASK) #define NOC_GITS0_GITS0_OPR_RESERVED0_MASK (0xFFF00000U) #define NOC_GITS0_GITS0_OPR_RESERVED0_SHIFT (20U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_OPR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_OPR_RESERVED0_MASK) #define NOC_GITS0_GITS0_OPR_DEVICE_ID_MASK (0xFFFFFF00000000U) #define NOC_GITS0_GITS0_OPR_DEVICE_ID_SHIFT (32U) /*! DEVICE_ID - DEVICE_ID */ #define NOC_GITS0_GITS0_OPR_DEVICE_ID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPR_DEVICE_ID_SHIFT)) & NOC_GITS0_GITS0_OPR_DEVICE_ID_MASK) #define NOC_GITS0_GITS0_OPR_RESERVED1_MASK (0xF00000000000000U) #define NOC_GITS0_GITS0_OPR_RESERVED1_SHIFT (56U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_OPR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPR_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_OPR_RESERVED1_MASK) #define NOC_GITS0_GITS0_OPR_LOCK_TYPE_MASK (0xF000000000000000U) #define NOC_GITS0_GITS0_OPR_LOCK_TYPE_SHIFT (60U) /*! LOCK_TYPE - LOCK_TYPE */ #define NOC_GITS0_GITS0_OPR_LOCK_TYPE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPR_LOCK_TYPE_SHIFT)) & NOC_GITS0_GITS0_OPR_LOCK_TYPE_MASK) /*! @} */ /*! @name GITS0_OPSR - GITS0_OPSR */ /*! @{ */ #define NOC_GITS0_GITS0_OPSR_PID_MASK (0xFFFFU) #define NOC_GITS0_GITS0_OPSR_PID_SHIFT (0U) /*! PID - PID */ #define NOC_GITS0_GITS0_OPSR_PID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_PID_SHIFT)) & NOC_GITS0_GITS0_OPSR_PID_MASK) #define NOC_GITS0_GITS0_OPSR_RESERVED0_MASK (0xFFFF0000U) #define NOC_GITS0_GITS0_OPSR_RESERVED0_SHIFT (16U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_OPSR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_OPSR_RESERVED0_MASK) #define NOC_GITS0_GITS0_OPSR_TARGET_MASK (0x3FFF00000000U) #define NOC_GITS0_GITS0_OPSR_TARGET_SHIFT (32U) /*! TARGET - TARGET */ #define NOC_GITS0_GITS0_OPSR_TARGET(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_TARGET_SHIFT)) & NOC_GITS0_GITS0_OPSR_TARGET_MASK) #define NOC_GITS0_GITS0_OPSR_RESERVED1_MASK (0xC00000000000U) #define NOC_GITS0_GITS0_OPSR_RESERVED1_SHIFT (46U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_OPSR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_OPSR_RESERVED1_MASK) #define NOC_GITS0_GITS0_OPSR_ENTRY_LOCKED_MASK (0x1000000000000U) #define NOC_GITS0_GITS0_OPSR_ENTRY_LOCKED_SHIFT (48U) /*! ENTRY_LOCKED - ENTRY_LOCKED */ #define NOC_GITS0_GITS0_OPSR_ENTRY_LOCKED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_ENTRY_LOCKED_SHIFT)) & NOC_GITS0_GITS0_OPSR_ENTRY_LOCKED_MASK) #define NOC_GITS0_GITS0_OPSR_VIRT_MASK (0x2000000000000U) #define NOC_GITS0_GITS0_OPSR_VIRT_SHIFT (49U) /*! VIRT - VIRT */ #define NOC_GITS0_GITS0_OPSR_VIRT(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_VIRT_SHIFT)) & NOC_GITS0_GITS0_OPSR_VIRT_MASK) #define NOC_GITS0_GITS0_OPSR_RESERVED2_MASK (0x1FFC000000000000U) #define NOC_GITS0_GITS0_OPSR_RESERVED2_SHIFT (50U) /*! RESERVED2 - RESERVED2 */ #define NOC_GITS0_GITS0_OPSR_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_RESERVED2_SHIFT)) & NOC_GITS0_GITS0_OPSR_RESERVED2_MASK) #define NOC_GITS0_GITS0_OPSR_REQUEST_IN_PROGRESS_MASK (0x2000000000000000U) #define NOC_GITS0_GITS0_OPSR_REQUEST_IN_PROGRESS_SHIFT (61U) /*! REQUEST_IN_PROGRESS - REQUEST_IN_PROGRESS */ #define NOC_GITS0_GITS0_OPSR_REQUEST_IN_PROGRESS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_REQUEST_IN_PROGRESS_SHIFT)) & NOC_GITS0_GITS0_OPSR_REQUEST_IN_PROGRESS_MASK) #define NOC_GITS0_GITS0_OPSR_REQUEST_PASS_MASK (0x4000000000000000U) #define NOC_GITS0_GITS0_OPSR_REQUEST_PASS_SHIFT (62U) /*! REQUEST_PASS - REQUEST_PASS */ #define NOC_GITS0_GITS0_OPSR_REQUEST_PASS(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_REQUEST_PASS_SHIFT)) & NOC_GITS0_GITS0_OPSR_REQUEST_PASS_MASK) #define NOC_GITS0_GITS0_OPSR_REQUEST_COMPLETE_MASK (0x8000000000000000U) #define NOC_GITS0_GITS0_OPSR_REQUEST_COMPLETE_SHIFT (63U) /*! REQUEST_COMPLETE - REQUEST_COMPLETE */ #define NOC_GITS0_GITS0_OPSR_REQUEST_COMPLETE(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_OPSR_REQUEST_COMPLETE_SHIFT)) & NOC_GITS0_GITS0_OPSR_REQUEST_COMPLETE_MASK) /*! @} */ /*! @name GITS0_CBASER - GITS0_CBASER */ /*! @{ */ #define NOC_GITS0_GITS0_CBASER_Size_MASK (0xFFU) #define NOC_GITS0_GITS0_CBASER_Size_SHIFT (0U) /*! Size - Size */ #define NOC_GITS0_GITS0_CBASER_Size(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_Size_SHIFT)) & NOC_GITS0_GITS0_CBASER_Size_MASK) #define NOC_GITS0_GITS0_CBASER_RESERVED0_MASK (0x300U) #define NOC_GITS0_GITS0_CBASER_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CBASER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CBASER_RESERVED0_MASK) #define NOC_GITS0_GITS0_CBASER_Shareability_MASK (0xC00U) #define NOC_GITS0_GITS0_CBASER_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GITS0_GITS0_CBASER_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_Shareability_SHIFT)) & NOC_GITS0_GITS0_CBASER_Shareability_MASK) #define NOC_GITS0_GITS0_CBASER_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GITS0_GITS0_CBASER_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GITS0_GITS0_CBASER_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_PhysicalAddress_SHIFT)) & NOC_GITS0_GITS0_CBASER_PhysicalAddress_MASK) #define NOC_GITS0_GITS0_CBASER_RESERVED1_MASK (0x1FFFF000000000U) #define NOC_GITS0_GITS0_CBASER_RESERVED1_SHIFT (36U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_CBASER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_CBASER_RESERVED1_MASK) #define NOC_GITS0_GITS0_CBASER_OuterCacheability_MASK (0xE0000000000000U) #define NOC_GITS0_GITS0_CBASER_OuterCacheability_SHIFT (53U) /*! OuterCacheability - OuterCacheability */ #define NOC_GITS0_GITS0_CBASER_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_OuterCacheability_SHIFT)) & NOC_GITS0_GITS0_CBASER_OuterCacheability_MASK) #define NOC_GITS0_GITS0_CBASER_RESERVED2_MASK (0x700000000000000U) #define NOC_GITS0_GITS0_CBASER_RESERVED2_SHIFT (56U) /*! RESERVED2 - RESERVED2 */ #define NOC_GITS0_GITS0_CBASER_RESERVED2(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_RESERVED2_SHIFT)) & NOC_GITS0_GITS0_CBASER_RESERVED2_MASK) #define NOC_GITS0_GITS0_CBASER_Cacheability_MASK (0x3800000000000000U) #define NOC_GITS0_GITS0_CBASER_Cacheability_SHIFT (59U) /*! Cacheability - Cacheability */ #define NOC_GITS0_GITS0_CBASER_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_Cacheability_SHIFT)) & NOC_GITS0_GITS0_CBASER_Cacheability_MASK) #define NOC_GITS0_GITS0_CBASER_RESERVED3_MASK (0x4000000000000000U) #define NOC_GITS0_GITS0_CBASER_RESERVED3_SHIFT (62U) /*! RESERVED3 - RESERVED3 */ #define NOC_GITS0_GITS0_CBASER_RESERVED3(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_RESERVED3_SHIFT)) & NOC_GITS0_GITS0_CBASER_RESERVED3_MASK) #define NOC_GITS0_GITS0_CBASER_Valid_MASK (0x8000000000000000U) #define NOC_GITS0_GITS0_CBASER_Valid_SHIFT (63U) /*! Valid - Valid */ #define NOC_GITS0_GITS0_CBASER_Valid(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CBASER_Valid_SHIFT)) & NOC_GITS0_GITS0_CBASER_Valid_MASK) /*! @} */ /*! @name GITS0_CWRITER - GITS0_CWRITER */ /*! @{ */ #define NOC_GITS0_GITS0_CWRITER_Retry_MASK (0x1U) #define NOC_GITS0_GITS0_CWRITER_Retry_SHIFT (0U) /*! Retry - Retry */ #define NOC_GITS0_GITS0_CWRITER_Retry(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CWRITER_Retry_SHIFT)) & NOC_GITS0_GITS0_CWRITER_Retry_MASK) #define NOC_GITS0_GITS0_CWRITER_RESERVED0_MASK (0x1EU) #define NOC_GITS0_GITS0_CWRITER_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CWRITER_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CWRITER_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CWRITER_RESERVED0_MASK) #define NOC_GITS0_GITS0_CWRITER_Offset_MASK (0xFFFE0U) #define NOC_GITS0_GITS0_CWRITER_Offset_SHIFT (5U) /*! Offset - Offset */ #define NOC_GITS0_GITS0_CWRITER_Offset(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CWRITER_Offset_SHIFT)) & NOC_GITS0_GITS0_CWRITER_Offset_MASK) #define NOC_GITS0_GITS0_CWRITER_RESERVED1_MASK (0xFFFFFFFFFFF00000U) #define NOC_GITS0_GITS0_CWRITER_RESERVED1_SHIFT (20U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_CWRITER_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CWRITER_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_CWRITER_RESERVED1_MASK) /*! @} */ /*! @name GITS0_CREADR - GITS0_CREADR */ /*! @{ */ #define NOC_GITS0_GITS0_CREADR_Stalled_MASK (0x1U) #define NOC_GITS0_GITS0_CREADR_Stalled_SHIFT (0U) /*! Stalled - Stalled */ #define NOC_GITS0_GITS0_CREADR_Stalled(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CREADR_Stalled_SHIFT)) & NOC_GITS0_GITS0_CREADR_Stalled_MASK) #define NOC_GITS0_GITS0_CREADR_RESERVED0_MASK (0x1EU) #define NOC_GITS0_GITS0_CREADR_RESERVED0_SHIFT (1U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CREADR_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CREADR_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CREADR_RESERVED0_MASK) #define NOC_GITS0_GITS0_CREADR_Offset_MASK (0xFFFE0U) #define NOC_GITS0_GITS0_CREADR_Offset_SHIFT (5U) /*! Offset - Offset */ #define NOC_GITS0_GITS0_CREADR_Offset(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CREADR_Offset_SHIFT)) & NOC_GITS0_GITS0_CREADR_Offset_MASK) #define NOC_GITS0_GITS0_CREADR_RESERVED1_MASK (0xFFFFFFFFFFF00000U) #define NOC_GITS0_GITS0_CREADR_RESERVED1_SHIFT (20U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_CREADR_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CREADR_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_CREADR_RESERVED1_MASK) /*! @} */ /*! @name GITS0_BASER0 - GITS0_BASER0 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER0_Size_MASK (0xFFU) #define NOC_GITS0_GITS0_BASER0_Size_SHIFT (0U) /*! Size - Size */ #define NOC_GITS0_GITS0_BASER0_Size(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_Size_SHIFT)) & NOC_GITS0_GITS0_BASER0_Size_MASK) #define NOC_GITS0_GITS0_BASER0_PageSize_MASK (0x300U) #define NOC_GITS0_GITS0_BASER0_PageSize_SHIFT (8U) /*! PageSize - PageSize */ #define NOC_GITS0_GITS0_BASER0_PageSize(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_PageSize_SHIFT)) & NOC_GITS0_GITS0_BASER0_PageSize_MASK) #define NOC_GITS0_GITS0_BASER0_Shareability_MASK (0xC00U) #define NOC_GITS0_GITS0_BASER0_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GITS0_GITS0_BASER0_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_Shareability_SHIFT)) & NOC_GITS0_GITS0_BASER0_Shareability_MASK) #define NOC_GITS0_GITS0_BASER0_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GITS0_GITS0_BASER0_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GITS0_GITS0_BASER0_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_PhysicalAddress_SHIFT)) & NOC_GITS0_GITS0_BASER0_PhysicalAddress_MASK) #define NOC_GITS0_GITS0_BASER0_RESERVED0_MASK (0xFFF000000000U) #define NOC_GITS0_GITS0_BASER0_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_BASER0_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_BASER0_RESERVED0_MASK) #define NOC_GITS0_GITS0_BASER0_EntrySize_MASK (0x1F000000000000U) #define NOC_GITS0_GITS0_BASER0_EntrySize_SHIFT (48U) /*! EntrySize - EntrySize */ #define NOC_GITS0_GITS0_BASER0_EntrySize(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_EntrySize_SHIFT)) & NOC_GITS0_GITS0_BASER0_EntrySize_MASK) #define NOC_GITS0_GITS0_BASER0_OuterCacheability_MASK (0xE0000000000000U) #define NOC_GITS0_GITS0_BASER0_OuterCacheability_SHIFT (53U) /*! OuterCacheability - OuterCacheability */ #define NOC_GITS0_GITS0_BASER0_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_OuterCacheability_SHIFT)) & NOC_GITS0_GITS0_BASER0_OuterCacheability_MASK) #define NOC_GITS0_GITS0_BASER0_Type_MASK (0x700000000000000U) #define NOC_GITS0_GITS0_BASER0_Type_SHIFT (56U) /*! Type - Type */ #define NOC_GITS0_GITS0_BASER0_Type(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_Type_SHIFT)) & NOC_GITS0_GITS0_BASER0_Type_MASK) #define NOC_GITS0_GITS0_BASER0_Cacheability_MASK (0x3800000000000000U) #define NOC_GITS0_GITS0_BASER0_Cacheability_SHIFT (59U) /*! Cacheability - Cacheability */ #define NOC_GITS0_GITS0_BASER0_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_Cacheability_SHIFT)) & NOC_GITS0_GITS0_BASER0_Cacheability_MASK) #define NOC_GITS0_GITS0_BASER0_Indirect_MASK (0x4000000000000000U) #define NOC_GITS0_GITS0_BASER0_Indirect_SHIFT (62U) /*! Indirect - Indirect */ #define NOC_GITS0_GITS0_BASER0_Indirect(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_Indirect_SHIFT)) & NOC_GITS0_GITS0_BASER0_Indirect_MASK) #define NOC_GITS0_GITS0_BASER0_Valid_MASK (0x8000000000000000U) #define NOC_GITS0_GITS0_BASER0_Valid_SHIFT (63U) /*! Valid - Valid */ #define NOC_GITS0_GITS0_BASER0_Valid(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER0_Valid_SHIFT)) & NOC_GITS0_GITS0_BASER0_Valid_MASK) /*! @} */ /*! @name GITS0_BASER1 - GITS0_BASER1 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER1_Size_MASK (0xFFU) #define NOC_GITS0_GITS0_BASER1_Size_SHIFT (0U) /*! Size - Size */ #define NOC_GITS0_GITS0_BASER1_Size(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_Size_SHIFT)) & NOC_GITS0_GITS0_BASER1_Size_MASK) #define NOC_GITS0_GITS0_BASER1_PageSize_MASK (0x300U) #define NOC_GITS0_GITS0_BASER1_PageSize_SHIFT (8U) /*! PageSize - PageSize */ #define NOC_GITS0_GITS0_BASER1_PageSize(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_PageSize_SHIFT)) & NOC_GITS0_GITS0_BASER1_PageSize_MASK) #define NOC_GITS0_GITS0_BASER1_Shareability_MASK (0xC00U) #define NOC_GITS0_GITS0_BASER1_Shareability_SHIFT (10U) /*! Shareability - Shareability */ #define NOC_GITS0_GITS0_BASER1_Shareability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_Shareability_SHIFT)) & NOC_GITS0_GITS0_BASER1_Shareability_MASK) #define NOC_GITS0_GITS0_BASER1_PhysicalAddress_MASK (0xFFFFFF000U) #define NOC_GITS0_GITS0_BASER1_PhysicalAddress_SHIFT (12U) /*! PhysicalAddress - PhysicalAddress */ #define NOC_GITS0_GITS0_BASER1_PhysicalAddress(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_PhysicalAddress_SHIFT)) & NOC_GITS0_GITS0_BASER1_PhysicalAddress_MASK) #define NOC_GITS0_GITS0_BASER1_RESERVED0_MASK (0xFFF000000000U) #define NOC_GITS0_GITS0_BASER1_RESERVED0_SHIFT (36U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_BASER1_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_BASER1_RESERVED0_MASK) #define NOC_GITS0_GITS0_BASER1_EntrySize_MASK (0x1F000000000000U) #define NOC_GITS0_GITS0_BASER1_EntrySize_SHIFT (48U) /*! EntrySize - EntrySize */ #define NOC_GITS0_GITS0_BASER1_EntrySize(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_EntrySize_SHIFT)) & NOC_GITS0_GITS0_BASER1_EntrySize_MASK) #define NOC_GITS0_GITS0_BASER1_OuterCacheability_MASK (0xE0000000000000U) #define NOC_GITS0_GITS0_BASER1_OuterCacheability_SHIFT (53U) /*! OuterCacheability - OuterCacheability */ #define NOC_GITS0_GITS0_BASER1_OuterCacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_OuterCacheability_SHIFT)) & NOC_GITS0_GITS0_BASER1_OuterCacheability_MASK) #define NOC_GITS0_GITS0_BASER1_Type_MASK (0x700000000000000U) #define NOC_GITS0_GITS0_BASER1_Type_SHIFT (56U) /*! Type - Type */ #define NOC_GITS0_GITS0_BASER1_Type(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_Type_SHIFT)) & NOC_GITS0_GITS0_BASER1_Type_MASK) #define NOC_GITS0_GITS0_BASER1_Cacheability_MASK (0x3800000000000000U) #define NOC_GITS0_GITS0_BASER1_Cacheability_SHIFT (59U) /*! Cacheability - Cacheability */ #define NOC_GITS0_GITS0_BASER1_Cacheability(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_Cacheability_SHIFT)) & NOC_GITS0_GITS0_BASER1_Cacheability_MASK) #define NOC_GITS0_GITS0_BASER1_Indirect_MASK (0x4000000000000000U) #define NOC_GITS0_GITS0_BASER1_Indirect_SHIFT (62U) /*! Indirect - Indirect */ #define NOC_GITS0_GITS0_BASER1_Indirect(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_Indirect_SHIFT)) & NOC_GITS0_GITS0_BASER1_Indirect_MASK) #define NOC_GITS0_GITS0_BASER1_Valid_MASK (0x8000000000000000U) #define NOC_GITS0_GITS0_BASER1_Valid_SHIFT (63U) /*! Valid - Valid */ #define NOC_GITS0_GITS0_BASER1_Valid(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER1_Valid_SHIFT)) & NOC_GITS0_GITS0_BASER1_Valid_MASK) /*! @} */ /*! @name GITS0_BASER2 - GITS0_BASER2 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER2_RESERVED_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GITS0_GITS0_BASER2_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_BASER2_RESERVED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER2_RESERVED_SHIFT)) & NOC_GITS0_GITS0_BASER2_RESERVED_MASK) /*! @} */ /*! @name GITS0_BASER3 - GITS0_BASER3 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER3_RESERVED_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GITS0_GITS0_BASER3_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_BASER3_RESERVED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER3_RESERVED_SHIFT)) & NOC_GITS0_GITS0_BASER3_RESERVED_MASK) /*! @} */ /*! @name GITS0_BASER4 - GITS0_BASER4 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER4_RESERVED_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GITS0_GITS0_BASER4_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_BASER4_RESERVED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER4_RESERVED_SHIFT)) & NOC_GITS0_GITS0_BASER4_RESERVED_MASK) /*! @} */ /*! @name GITS0_BASER5 - GITS0_BASER5 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER5_RESERVED_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GITS0_GITS0_BASER5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_BASER5_RESERVED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER5_RESERVED_SHIFT)) & NOC_GITS0_GITS0_BASER5_RESERVED_MASK) /*! @} */ /*! @name GITS0_BASER6 - GITS0_BASER6 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER6_RESERVED_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GITS0_GITS0_BASER6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_BASER6_RESERVED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER6_RESERVED_SHIFT)) & NOC_GITS0_GITS0_BASER6_RESERVED_MASK) /*! @} */ /*! @name GITS0_BASER7 - GITS0_BASER7 */ /*! @{ */ #define NOC_GITS0_GITS0_BASER7_RESERVED_MASK (0xFFFFFFFFFFFFFFFFU) #define NOC_GITS0_GITS0_BASER7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_BASER7_RESERVED(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_BASER7_RESERVED_SHIFT)) & NOC_GITS0_GITS0_BASER7_RESERVED_MASK) /*! @} */ /*! @name GITS0_CFGID - GITS0_CFGID */ /*! @{ */ #define NOC_GITS0_GITS0_CFGID_ITS_NUMBER_MASK (0xFFU) #define NOC_GITS0_GITS0_CFGID_ITS_NUMBER_SHIFT (0U) /*! ITS_NUMBER - ITS_NUMBER */ #define NOC_GITS0_GITS0_CFGID_ITS_NUMBER(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_ITS_NUMBER_SHIFT)) & NOC_GITS0_GITS0_CFGID_ITS_NUMBER_MASK) #define NOC_GITS0_GITS0_CFGID_LPI_Credit_Count_MASK (0xF00U) #define NOC_GITS0_GITS0_CFGID_LPI_Credit_Count_SHIFT (8U) /*! LPI_Credit_Count - LPI_Credit_Count */ #define NOC_GITS0_GITS0_CFGID_LPI_Credit_Count(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_LPI_Credit_Count_SHIFT)) & NOC_GITS0_GITS0_CFGID_LPI_Credit_Count_MASK) #define NOC_GITS0_GITS0_CFGID_Target_Bits_MASK (0xF000U) #define NOC_GITS0_GITS0_CFGID_Target_Bits_SHIFT (12U) /*! Target_Bits - Target_Bits */ #define NOC_GITS0_GITS0_CFGID_Target_Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Target_Bits_SHIFT)) & NOC_GITS0_GITS0_CFGID_Target_Bits_MASK) #define NOC_GITS0_GITS0_CFGID_MSI_64_MASK (0x10000U) #define NOC_GITS0_GITS0_CFGID_MSI_64_SHIFT (16U) /*! MSI_64 - MSI_64 */ #define NOC_GITS0_GITS0_CFGID_MSI_64(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_MSI_64_SHIFT)) & NOC_GITS0_GITS0_CFGID_MSI_64_MASK) #define NOC_GITS0_GITS0_CFGID_Low_Latency_Support_MASK (0x20000U) #define NOC_GITS0_GITS0_CFGID_Low_Latency_Support_SHIFT (17U) /*! Low_Latency_Support - Low_Latency_Support */ #define NOC_GITS0_GITS0_CFGID_Low_Latency_Support(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Low_Latency_Support_SHIFT)) & NOC_GITS0_GITS0_CFGID_Low_Latency_Support_MASK) #define NOC_GITS0_GITS0_CFGID_Cache_ECC_MASK (0x40000U) #define NOC_GITS0_GITS0_CFGID_Cache_ECC_SHIFT (18U) /*! Cache_ECC - Cache_ECC */ #define NOC_GITS0_GITS0_CFGID_Cache_ECC(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Cache_ECC_SHIFT)) & NOC_GITS0_GITS0_CFGID_Cache_ECC_MASK) #define NOC_GITS0_GITS0_CFGID_RESERVED0_MASK (0x80000U) #define NOC_GITS0_GITS0_CFGID_RESERVED0_SHIFT (19U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CFGID_RESERVED0(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CFGID_RESERVED0_MASK) #define NOC_GITS0_GITS0_CFGID_Collection_Cache_Index_Bits_MASK (0xF00000U) #define NOC_GITS0_GITS0_CFGID_Collection_Cache_Index_Bits_SHIFT (20U) /*! Collection_Cache_Index_Bits - Collection_Cache_Index_Bits */ #define NOC_GITS0_GITS0_CFGID_Collection_Cache_Index_Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Collection_Cache_Index_Bits_SHIFT)) & NOC_GITS0_GITS0_CFGID_Collection_Cache_Index_Bits_MASK) #define NOC_GITS0_GITS0_CFGID_Device_Cache_Index_Bits_MASK (0xF000000U) #define NOC_GITS0_GITS0_CFGID_Device_Cache_Index_Bits_SHIFT (24U) /*! Device_Cache_Index_Bits - Device_Cache_Index_Bits */ #define NOC_GITS0_GITS0_CFGID_Device_Cache_Index_Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Device_Cache_Index_Bits_SHIFT)) & NOC_GITS0_GITS0_CFGID_Device_Cache_Index_Bits_MASK) #define NOC_GITS0_GITS0_CFGID_Event_Cache_Index_Bits_MASK (0xF0000000U) #define NOC_GITS0_GITS0_CFGID_Event_Cache_Index_Bits_SHIFT (28U) /*! Event_Cache_Index_Bits - Event_Cache_Index_Bits */ #define NOC_GITS0_GITS0_CFGID_Event_Cache_Index_Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Event_Cache_Index_Bits_SHIFT)) & NOC_GITS0_GITS0_CFGID_Event_Cache_Index_Bits_MASK) #define NOC_GITS0_GITS0_CFGID_Vpe_Bits_MASK (0xF00000000U) #define NOC_GITS0_GITS0_CFGID_Vpe_Bits_SHIFT (32U) /*! Vpe_Bits - Vpe_Bits */ #define NOC_GITS0_GITS0_CFGID_Vpe_Bits(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Vpe_Bits_SHIFT)) & NOC_GITS0_GITS0_CFGID_Vpe_Bits_MASK) #define NOC_GITS0_GITS0_CFGID_Low_Latency_Lpi_Credit_Count_MASK (0xF000000000U) #define NOC_GITS0_GITS0_CFGID_Low_Latency_Lpi_Credit_Count_SHIFT (36U) /*! Low_Latency_Lpi_Credit_Count - Low_Latency_Lpi_Credit_Count */ #define NOC_GITS0_GITS0_CFGID_Low_Latency_Lpi_Credit_Count(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_Low_Latency_Lpi_Credit_Count_SHIFT)) & NOC_GITS0_GITS0_CFGID_Low_Latency_Lpi_Credit_Count_MASK) #define NOC_GITS0_GITS0_CFGID_RESERVED1_MASK (0xFFFFFF0000000000U) #define NOC_GITS0_GITS0_CFGID_RESERVED1_SHIFT (40U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_CFGID_RESERVED1(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0_GITS0_CFGID_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_CFGID_RESERVED1_MASK) /*! @} */ /*! @name GITS0_PIDR4 - GITS0_PIDR4 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR4_DES_2_MASK (0xFU) #define NOC_GITS0_GITS0_PIDR4_DES_2_SHIFT (0U) /*! DES_2 - DES_2 */ #define NOC_GITS0_GITS0_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR4_DES_2_SHIFT)) & NOC_GITS0_GITS0_PIDR4_DES_2_MASK) #define NOC_GITS0_GITS0_PIDR4_SIZE_MASK (0xF0U) #define NOC_GITS0_GITS0_PIDR4_SIZE_SHIFT (4U) /*! SIZE - SIZE */ #define NOC_GITS0_GITS0_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR4_SIZE_SHIFT)) & NOC_GITS0_GITS0_PIDR4_SIZE_MASK) #define NOC_GITS0_GITS0_PIDR4_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR4_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR4_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR4_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR4_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PIDR5 - GITS0_PIDR5 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR5_RESERVED_MASK (0xFFU) #define NOC_GITS0_GITS0_PIDR5_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_PIDR5_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR5_RESERVED_SHIFT)) & NOC_GITS0_GITS0_PIDR5_RESERVED_MASK) #define NOC_GITS0_GITS0_PIDR5_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR5_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR5_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR5_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR5_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PIDR6 - GITS0_PIDR6 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR6_RESERVED_MASK (0xFFU) #define NOC_GITS0_GITS0_PIDR6_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_PIDR6_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR6_RESERVED_SHIFT)) & NOC_GITS0_GITS0_PIDR6_RESERVED_MASK) #define NOC_GITS0_GITS0_PIDR6_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR6_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR6_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR6_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR6_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PIDR7 - GITS0_PIDR7 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR7_RESERVED_MASK (0xFFU) #define NOC_GITS0_GITS0_PIDR7_RESERVED_SHIFT (0U) /*! RESERVED - RESERVED */ #define NOC_GITS0_GITS0_PIDR7_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR7_RESERVED_SHIFT)) & NOC_GITS0_GITS0_PIDR7_RESERVED_MASK) #define NOC_GITS0_GITS0_PIDR7_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR7_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR7_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR7_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR7_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PIDR0 - GITS0_PIDR0 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR0_PART_0_MASK (0xFFU) #define NOC_GITS0_GITS0_PIDR0_PART_0_SHIFT (0U) /*! PART_0 - PART_0 */ #define NOC_GITS0_GITS0_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR0_PART_0_SHIFT)) & NOC_GITS0_GITS0_PIDR0_PART_0_MASK) #define NOC_GITS0_GITS0_PIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR0_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR0_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PIDR1 - GITS0_PIDR1 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR1_PART_1_MASK (0xFU) #define NOC_GITS0_GITS0_PIDR1_PART_1_SHIFT (0U) /*! PART_1 - PART_1 */ #define NOC_GITS0_GITS0_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR1_PART_1_SHIFT)) & NOC_GITS0_GITS0_PIDR1_PART_1_MASK) #define NOC_GITS0_GITS0_PIDR1_DES_0_MASK (0xF0U) #define NOC_GITS0_GITS0_PIDR1_DES_0_SHIFT (4U) /*! DES_0 - DES_0 */ #define NOC_GITS0_GITS0_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR1_DES_0_SHIFT)) & NOC_GITS0_GITS0_PIDR1_DES_0_MASK) #define NOC_GITS0_GITS0_PIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR1_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR1_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PIDR2 - GITS0_PIDR2 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR2_DES_1_MASK (0x7U) #define NOC_GITS0_GITS0_PIDR2_DES_1_SHIFT (0U) /*! DES_1 - DES_1 */ #define NOC_GITS0_GITS0_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR2_DES_1_SHIFT)) & NOC_GITS0_GITS0_PIDR2_DES_1_MASK) #define NOC_GITS0_GITS0_PIDR2_JEDEC_MASK (0x8U) #define NOC_GITS0_GITS0_PIDR2_JEDEC_SHIFT (3U) /*! JEDEC - JEDEC */ #define NOC_GITS0_GITS0_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR2_JEDEC_SHIFT)) & NOC_GITS0_GITS0_PIDR2_JEDEC_MASK) #define NOC_GITS0_GITS0_PIDR2_REVISION_MASK (0xF0U) #define NOC_GITS0_GITS0_PIDR2_REVISION_SHIFT (4U) /*! REVISION - REVISION */ #define NOC_GITS0_GITS0_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR2_REVISION_SHIFT)) & NOC_GITS0_GITS0_PIDR2_REVISION_MASK) #define NOC_GITS0_GITS0_PIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR2_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR2_RESERVED0_MASK) /*! @} */ /*! @name GITS0_PIDR3 - GITS0_PIDR3 */ /*! @{ */ #define NOC_GITS0_GITS0_PIDR3_CMOD_MASK (0x7U) #define NOC_GITS0_GITS0_PIDR3_CMOD_SHIFT (0U) /*! CMOD - CMOD */ #define NOC_GITS0_GITS0_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR3_CMOD_SHIFT)) & NOC_GITS0_GITS0_PIDR3_CMOD_MASK) #define NOC_GITS0_GITS0_PIDR3_RESERVED0_MASK (0x8U) #define NOC_GITS0_GITS0_PIDR3_RESERVED0_SHIFT (3U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_PIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR3_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_PIDR3_RESERVED0_MASK) #define NOC_GITS0_GITS0_PIDR3_REVAND_MASK (0xF0U) #define NOC_GITS0_GITS0_PIDR3_REVAND_SHIFT (4U) /*! REVAND - REVAND */ #define NOC_GITS0_GITS0_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR3_REVAND_SHIFT)) & NOC_GITS0_GITS0_PIDR3_REVAND_MASK) #define NOC_GITS0_GITS0_PIDR3_RESERVED1_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_PIDR3_RESERVED1_SHIFT (8U) /*! RESERVED1 - RESERVED1 */ #define NOC_GITS0_GITS0_PIDR3_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_PIDR3_RESERVED1_SHIFT)) & NOC_GITS0_GITS0_PIDR3_RESERVED1_MASK) /*! @} */ /*! @name GITS0_CIDR0 - GITS0_CIDR0 */ /*! @{ */ #define NOC_GITS0_GITS0_CIDR0_PRMBL_0_MASK (0xFFU) #define NOC_GITS0_GITS0_CIDR0_PRMBL_0_SHIFT (0U) /*! PRMBL_0 - PRMBL_0 */ #define NOC_GITS0_GITS0_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR0_PRMBL_0_SHIFT)) & NOC_GITS0_GITS0_CIDR0_PRMBL_0_MASK) #define NOC_GITS0_GITS0_CIDR0_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_CIDR0_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CIDR0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR0_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CIDR0_RESERVED0_MASK) /*! @} */ /*! @name GITS0_CIDR1 - GITS0_CIDR1 */ /*! @{ */ #define NOC_GITS0_GITS0_CIDR1_PRMBL_1_MASK (0xFU) #define NOC_GITS0_GITS0_CIDR1_PRMBL_1_SHIFT (0U) /*! PRMBL_1 - PRMBL_1 */ #define NOC_GITS0_GITS0_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR1_PRMBL_1_SHIFT)) & NOC_GITS0_GITS0_CIDR1_PRMBL_1_MASK) #define NOC_GITS0_GITS0_CIDR1_CLASS_MASK (0xF0U) #define NOC_GITS0_GITS0_CIDR1_CLASS_SHIFT (4U) /*! CLASS - CLASS */ #define NOC_GITS0_GITS0_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR1_CLASS_SHIFT)) & NOC_GITS0_GITS0_CIDR1_CLASS_MASK) #define NOC_GITS0_GITS0_CIDR1_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_CIDR1_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CIDR1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR1_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CIDR1_RESERVED0_MASK) /*! @} */ /*! @name GITS0_CIDR2 - GITS0_CIDR2 */ /*! @{ */ #define NOC_GITS0_GITS0_CIDR2_PRMBL_2_MASK (0xFFU) #define NOC_GITS0_GITS0_CIDR2_PRMBL_2_SHIFT (0U) /*! PRMBL_2 - PRMBL_2 */ #define NOC_GITS0_GITS0_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR2_PRMBL_2_SHIFT)) & NOC_GITS0_GITS0_CIDR2_PRMBL_2_MASK) #define NOC_GITS0_GITS0_CIDR2_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_CIDR2_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CIDR2_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR2_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CIDR2_RESERVED0_MASK) /*! @} */ /*! @name GITS0_CIDR3 - GITS0_CIDR3 */ /*! @{ */ #define NOC_GITS0_GITS0_CIDR3_PRMBL_3_MASK (0xFFU) #define NOC_GITS0_GITS0_CIDR3_PRMBL_3_SHIFT (0U) /*! PRMBL_3 - PRMBL_3 */ #define NOC_GITS0_GITS0_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR3_PRMBL_3_SHIFT)) & NOC_GITS0_GITS0_CIDR3_PRMBL_3_MASK) #define NOC_GITS0_GITS0_CIDR3_RESERVED0_MASK (0xFFFFFF00U) #define NOC_GITS0_GITS0_CIDR3_RESERVED0_SHIFT (8U) /*! RESERVED0 - RESERVED0 */ #define NOC_GITS0_GITS0_CIDR3_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << NOC_GITS0_GITS0_CIDR3_RESERVED0_SHIFT)) & NOC_GITS0_GITS0_CIDR3_RESERVED0_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GITS0_Register_Masks */ /* NOC_GITS0 - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GITS0 base address */ #define NOC__GIC__GITS0_BASE (0x48040000u) /** Peripheral NOC__GIC__GITS0 base pointer */ #define NOC__GIC__GITS0 ((NOC_GITS0_Type *)NOC__GIC__GITS0_BASE) /** Array initializer of NOC_GITS0 peripheral base addresses */ #define NOC_GITS0_BASE_ADDRS { NOC__GIC__GITS0_BASE } /** Array initializer of NOC_GITS0 peripheral base pointers */ #define NOC_GITS0_BASE_PTRS { NOC__GIC__GITS0 } /*! * @} */ /* end of group NOC_GITS0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_GITS0TRANSLATER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GITS0TRANSLATER_Peripheral_Access_Layer NOC_GITS0TRANSLATER Peripheral Access Layer * @{ */ /** NOC_GITS0TRANSLATER - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[64]; __O uint64_t GITS0_TRANSLATER; /**< GITS0_TRANSLATER, offset: 0x40 */ } NOC_GITS0TRANSLATER_Type; /* ---------------------------------------------------------------------------- -- NOC_GITS0TRANSLATER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_GITS0TRANSLATER_Register_Masks NOC_GITS0TRANSLATER Register Masks * @{ */ /*! @name GITS0_TRANSLATER - GITS0_TRANSLATER */ /*! @{ */ #define NOC_GITS0TRANSLATER_GITS0_TRANSLATER_InterruptID_MASK (0xFFFFFFFFU) #define NOC_GITS0TRANSLATER_GITS0_TRANSLATER_InterruptID_SHIFT (0U) /*! InterruptID - InterruptID */ #define NOC_GITS0TRANSLATER_GITS0_TRANSLATER_InterruptID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0TRANSLATER_GITS0_TRANSLATER_InterruptID_SHIFT)) & NOC_GITS0TRANSLATER_GITS0_TRANSLATER_InterruptID_MASK) #define NOC_GITS0TRANSLATER_GITS0_TRANSLATER_DeviceID_MASK (0xFFFFFFFF00000000U) #define NOC_GITS0TRANSLATER_GITS0_TRANSLATER_DeviceID_SHIFT (32U) /*! DeviceID - DeviceID */ #define NOC_GITS0TRANSLATER_GITS0_TRANSLATER_DeviceID(x) (((uint64_t)(((uint64_t)(x)) << NOC_GITS0TRANSLATER_GITS0_TRANSLATER_DeviceID_SHIFT)) & NOC_GITS0TRANSLATER_GITS0_TRANSLATER_DeviceID_MASK) /*! @} */ /*! * @} */ /* end of group NOC_GITS0TRANSLATER_Register_Masks */ /* NOC_GITS0TRANSLATER - Peripheral instance base addresses */ /** Peripheral NOC__GIC__GITS0TRANSLATER base address */ #define NOC__GIC__GITS0TRANSLATER_BASE (0x48050000u) /** Peripheral NOC__GIC__GITS0TRANSLATER base pointer */ #define NOC__GIC__GITS0TRANSLATER ((NOC_GITS0TRANSLATER_Type *)NOC__GIC__GITS0TRANSLATER_BASE) /** Array initializer of NOC_GITS0TRANSLATER peripheral base addresses */ #define NOC_GITS0TRANSLATER_BASE_ADDRS { NOC__GIC__GITS0TRANSLATER_BASE } /** Array initializer of NOC_GITS0TRANSLATER peripheral base pointers */ #define NOC_GITS0TRANSLATER_BASE_PTRS { NOC__GIC__GITS0TRANSLATER } /*! * @} */ /* end of group NOC_GITS0TRANSLATER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_MAIN_PROBE_Peripheral_Access_Layer NOC_ISI_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_ISI_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_ISI_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_MAIN_PROBE_Register_Masks NOC_ISI_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_ISI_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_ISI_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_ISI_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_ISI_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_ISI_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_ISI_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_ISI_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_ISI_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_ISI_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_ISI_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_ISI_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_ISI_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_ISI_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_ISI_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_ISI_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_ISI_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_ISI_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_ISI_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_ISI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_ISI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_ISI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_ISI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_ISI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_ISI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_ISI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_ISI_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_ISI_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_ISI_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_ISI_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_ISI_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_ISI_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_ISI_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_ISI_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_ISI_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_ISI_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_ISI_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_ISI_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_ISI_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_ISI_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_ISI_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_ISI_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_ISI_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_ISI_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_ISI_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_ISI_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_ISI_MAIN_PROBE_SRC */ #define NOC_ISI_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_ISI_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_ISI_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_ISI_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_ISI_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_ISI_MAIN_PROBE_VAL */ #define NOC_ISI_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_ISI_MAIN_PROBE_Register_Masks */ /* NOC_ISI_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__PROBE_ISI_MAIN_PROBE base address */ #define CAMERA__GPV__PROBE_ISI_MAIN_PROBE_BASE (0x4AFF0000u) /** Peripheral CAMERA__GPV__PROBE_ISI_MAIN_PROBE base pointer */ #define CAMERA__GPV__PROBE_ISI_MAIN_PROBE ((NOC_ISI_MAIN_PROBE_Type *)CAMERA__GPV__PROBE_ISI_MAIN_PROBE_BASE) /** Array initializer of NOC_ISI_MAIN_PROBE peripheral base addresses */ #define NOC_ISI_MAIN_PROBE_BASE_ADDRS { CAMERA__GPV__PROBE_ISI_MAIN_PROBE_BASE } /** Array initializer of NOC_ISI_MAIN_PROBE peripheral base pointers */ #define NOC_ISI_MAIN_PROBE_BASE_PTRS { CAMERA__GPV__PROBE_ISI_MAIN_PROBE } /*! * @} */ /* end of group NOC_ISI_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_ISI_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISI_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISI_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_RD_I_QOSGENERATOR_Register_Masks NOC_ISI_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISI_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISI_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISI_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISI_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISI_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_ISI_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR_BASE (0x4AFF0C00u) /** Peripheral CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR ((NOC_ISI_RD_I_QOSGENERATOR_Type *)CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISI_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_ISI_RD_I_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISI_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_ISI_RD_I_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISI_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_RD_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_RD_XSTATFILTER_Peripheral_Access_Layer NOC_ISI_RD_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISI_RD_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISI_RD_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_RD_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_RD_XSTATFILTER_Register_Masks NOC_ISI_RD_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_RD_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_RD_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_RD_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_RD_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_RD_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_RD_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_RD_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISI_RD_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISI_RD_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISI_RD_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISI_RD_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFFU) #define NOC_ISI_RD_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISI_RD_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISI_RD_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISI_RD_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISI_RD_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISI_RD_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISI_RD_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISI_RD_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISI_RD_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISI_RD_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISI_RD_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISI_RD_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISI_RD_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISI_RD_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISI_RD_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_RD_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISI_RD_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_RD_XSTATFILTER_Register_Masks */ /* NOC_ISI_RD_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1000u) /** Peripheral CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISI_RD_XSTATFILTER_Type *)CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISI_RD_XSTATFILTER peripheral base addresses */ #define NOC_ISI_RD_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISI_RD_XSTATFILTER peripheral base pointers */ #define NOC_ISI_RD_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISI_RD_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_U_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_U_QOSGENERATOR_Peripheral_Access_Layer NOC_ISI_WR_U_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISI_WR_U_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISI_WR_U_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_U_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_U_QOSGENERATOR_Register_Masks NOC_ISI_WR_U_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_WR_U_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISI_WR_U_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISI_WR_U_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISI_WR_U_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISI_WR_U_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISI_WR_U_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISI_WR_U_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISI_WR_U_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISI_WR_U_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISI_WR_U_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_WR_U_QOSGENERATOR_Register_Masks */ /* NOC_ISI_WR_U_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR_BASE (0x4AFF0C80u) /** Peripheral CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR ((NOC_ISI_WR_U_QOSGENERATOR_Type *)CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISI_WR_U_QOSGENERATOR peripheral base addresses */ #define NOC_ISI_WR_U_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISI_WR_U_QOSGENERATOR peripheral base pointers */ #define NOC_ISI_WR_U_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISI_WR_U_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_U_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_U_XSTATFILTER_Peripheral_Access_Layer NOC_ISI_WR_U_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISI_WR_U_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISI_WR_U_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_U_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_U_XSTATFILTER_Register_Masks NOC_ISI_WR_U_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISI_WR_U_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFFU) #define NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISI_WR_U_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISI_WR_U_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISI_WR_U_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISI_WR_U_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISI_WR_U_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISI_WR_U_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISI_WR_U_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISI_WR_U_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISI_WR_U_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_U_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISI_WR_U_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_WR_U_XSTATFILTER_Register_Masks */ /* NOC_ISI_WR_U_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1080u) /** Peripheral CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISI_WR_U_XSTATFILTER_Type *)CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISI_WR_U_XSTATFILTER peripheral base addresses */ #define NOC_ISI_WR_U_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISI_WR_U_XSTATFILTER peripheral base pointers */ #define NOC_ISI_WR_U_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISI_WR_U_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_V_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_V_QOSGENERATOR_Peripheral_Access_Layer NOC_ISI_WR_V_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISI_WR_V_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISI_WR_V_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_V_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_V_QOSGENERATOR_Register_Masks NOC_ISI_WR_V_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_WR_V_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISI_WR_V_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISI_WR_V_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISI_WR_V_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISI_WR_V_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISI_WR_V_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISI_WR_V_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISI_WR_V_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISI_WR_V_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISI_WR_V_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_WR_V_QOSGENERATOR_Register_Masks */ /* NOC_ISI_WR_V_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR_BASE (0x4AFF0D00u) /** Peripheral CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR ((NOC_ISI_WR_V_QOSGENERATOR_Type *)CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISI_WR_V_QOSGENERATOR peripheral base addresses */ #define NOC_ISI_WR_V_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISI_WR_V_QOSGENERATOR peripheral base pointers */ #define NOC_ISI_WR_V_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISI_WR_V_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_V_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_V_XSTATFILTER_Peripheral_Access_Layer NOC_ISI_WR_V_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISI_WR_V_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISI_WR_V_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_V_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_V_XSTATFILTER_Register_Masks NOC_ISI_WR_V_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISI_WR_V_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFFU) #define NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISI_WR_V_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISI_WR_V_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISI_WR_V_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISI_WR_V_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISI_WR_V_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISI_WR_V_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISI_WR_V_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISI_WR_V_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISI_WR_V_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_V_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISI_WR_V_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_WR_V_XSTATFILTER_Register_Masks */ /* NOC_ISI_WR_V_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1100u) /** Peripheral CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISI_WR_V_XSTATFILTER_Type *)CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISI_WR_V_XSTATFILTER peripheral base addresses */ #define NOC_ISI_WR_V_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISI_WR_V_XSTATFILTER peripheral base pointers */ #define NOC_ISI_WR_V_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISI_WR_V_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_Y_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_Y_QOSGENERATOR_Peripheral_Access_Layer NOC_ISI_WR_Y_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISI_WR_Y_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISI_WR_Y_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_Y_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_Y_QOSGENERATOR_Register_Masks NOC_ISI_WR_Y_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_WR_Y_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISI_WR_Y_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISI_WR_Y_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISI_WR_Y_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISI_WR_Y_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISI_WR_Y_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISI_WR_Y_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISI_WR_Y_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISI_WR_Y_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISI_WR_Y_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_WR_Y_QOSGENERATOR_Register_Masks */ /* NOC_ISI_WR_Y_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR_BASE (0x4AFF0D80u) /** Peripheral CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR ((NOC_ISI_WR_Y_QOSGENERATOR_Type *)CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISI_WR_Y_QOSGENERATOR peripheral base addresses */ #define NOC_ISI_WR_Y_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISI_WR_Y_QOSGENERATOR peripheral base pointers */ #define NOC_ISI_WR_Y_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISI_WR_Y_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_Y_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_Y_XSTATFILTER_Peripheral_Access_Layer NOC_ISI_WR_Y_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISI_WR_Y_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISI_WR_Y_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISI_WR_Y_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISI_WR_Y_XSTATFILTER_Register_Masks NOC_ISI_WR_Y_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISI_WR_Y_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFFU) #define NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISI_WR_Y_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISI_WR_Y_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISI_WR_Y_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISI_WR_Y_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISI_WR_Y_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISI_WR_Y_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISI_WR_Y_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISI_WR_Y_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISI_WR_Y_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISI_WR_Y_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISI_WR_Y_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISI_WR_Y_XSTATFILTER_Register_Masks */ /* NOC_ISI_WR_Y_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1180u) /** Peripheral CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISI_WR_Y_XSTATFILTER_Type *)CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISI_WR_Y_XSTATFILTER peripheral base addresses */ #define NOC_ISI_WR_Y_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISI_WR_Y_XSTATFILTER peripheral base pointers */ #define NOC_ISI_WR_Y_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISI_WR_Y_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_MAIN_PROBE_Peripheral_Access_Layer NOC_ISP_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_ISP_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_ISP_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_MAIN_PROBE_Register_Masks NOC_ISP_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_ISP_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_ISP_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_ISP_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_ISP_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_ISP_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_ISP_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_ISP_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_ISP_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_ISP_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_ISP_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_ISP_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_ISP_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_ISP_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_ISP_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_ISP_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_ISP_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_ISP_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_ISP_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_ISP_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_ISP_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_ISP_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_ISP_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_ISP_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_ISP_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_ISP_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_ISP_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_ISP_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_ISP_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_ISP_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_ISP_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_ISP_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_ISP_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_ISP_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_ISP_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_ISP_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_ISP_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_ISP_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_ISP_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_ISP_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_ISP_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_ISP_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_ISP_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_ISP_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_ISP_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_ISP_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_ISP_MAIN_PROBE_SRC */ #define NOC_ISP_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_ISP_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_ISP_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_ISP_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_ISP_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_ISP_MAIN_PROBE_VAL */ #define NOC_ISP_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_ISP_MAIN_PROBE_Register_Masks */ /* NOC_ISP_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__PROBE_ISP_MAIN_PROBE base address */ #define CAMERA__GPV__PROBE_ISP_MAIN_PROBE_BASE (0x4AFF0400u) /** Peripheral CAMERA__GPV__PROBE_ISP_MAIN_PROBE base pointer */ #define CAMERA__GPV__PROBE_ISP_MAIN_PROBE ((NOC_ISP_MAIN_PROBE_Type *)CAMERA__GPV__PROBE_ISP_MAIN_PROBE_BASE) /** Array initializer of NOC_ISP_MAIN_PROBE peripheral base addresses */ #define NOC_ISP_MAIN_PROBE_BASE_ADDRS { CAMERA__GPV__PROBE_ISP_MAIN_PROBE_BASE } /** Array initializer of NOC_ISP_MAIN_PROBE peripheral base pointers */ #define NOC_ISP_MAIN_PROBE_BASE_PTRS { CAMERA__GPV__PROBE_ISP_MAIN_PROBE } /*! * @} */ /* end of group NOC_ISP_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_0_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_0_QOSGENERATOR_Peripheral_Access_Layer NOC_ISP_RD_0_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISP_RD_0_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISP_RD_0_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_0_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_0_QOSGENERATOR_Register_Masks NOC_ISP_RD_0_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_RD_0_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISP_RD_0_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISP_RD_0_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISP_RD_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISP_RD_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISP_RD_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISP_RD_0_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISP_RD_0_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISP_RD_0_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISP_RD_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_RD_0_QOSGENERATOR_Register_Masks */ /* NOC_ISP_RD_0_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR_BASE (0x4AFF0E00u) /** Peripheral CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR ((NOC_ISP_RD_0_QOSGENERATOR_Type *)CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISP_RD_0_QOSGENERATOR peripheral base addresses */ #define NOC_ISP_RD_0_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISP_RD_0_QOSGENERATOR peripheral base pointers */ #define NOC_ISP_RD_0_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISP_RD_0_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_0_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_0_XSTATFILTER_Peripheral_Access_Layer NOC_ISP_RD_0_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISP_RD_0_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISP_RD_0_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_0_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_0_XSTATFILTER_Register_Masks NOC_ISP_RD_0_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISP_RD_0_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISP_RD_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISP_RD_0_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISP_RD_0_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISP_RD_0_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISP_RD_0_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISP_RD_0_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISP_RD_0_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISP_RD_0_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISP_RD_0_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_0_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISP_RD_0_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_RD_0_XSTATFILTER_Register_Masks */ /* NOC_ISP_RD_0_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1200u) /** Peripheral CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISP_RD_0_XSTATFILTER_Type *)CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISP_RD_0_XSTATFILTER peripheral base addresses */ #define NOC_ISP_RD_0_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISP_RD_0_XSTATFILTER peripheral base pointers */ #define NOC_ISP_RD_0_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISP_RD_0_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_1_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_1_QOSGENERATOR_Peripheral_Access_Layer NOC_ISP_RD_1_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISP_RD_1_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISP_RD_1_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_1_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_1_QOSGENERATOR_Register_Masks NOC_ISP_RD_1_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_RD_1_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISP_RD_1_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISP_RD_1_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISP_RD_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISP_RD_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISP_RD_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISP_RD_1_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISP_RD_1_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISP_RD_1_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISP_RD_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_RD_1_QOSGENERATOR_Register_Masks */ /* NOC_ISP_RD_1_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR_BASE (0x4AFF0E80u) /** Peripheral CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR ((NOC_ISP_RD_1_QOSGENERATOR_Type *)CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISP_RD_1_QOSGENERATOR peripheral base addresses */ #define NOC_ISP_RD_1_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISP_RD_1_QOSGENERATOR peripheral base pointers */ #define NOC_ISP_RD_1_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISP_RD_1_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_1_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_1_XSTATFILTER_Peripheral_Access_Layer NOC_ISP_RD_1_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISP_RD_1_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISP_RD_1_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_RD_1_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_RD_1_XSTATFILTER_Register_Masks NOC_ISP_RD_1_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISP_RD_1_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISP_RD_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISP_RD_1_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISP_RD_1_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISP_RD_1_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISP_RD_1_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISP_RD_1_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISP_RD_1_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISP_RD_1_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISP_RD_1_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_RD_1_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISP_RD_1_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_RD_1_XSTATFILTER_Register_Masks */ /* NOC_ISP_RD_1_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1280u) /** Peripheral CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISP_RD_1_XSTATFILTER_Type *)CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISP_RD_1_XSTATFILTER peripheral base addresses */ #define NOC_ISP_RD_1_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISP_RD_1_XSTATFILTER peripheral base pointers */ #define NOC_ISP_RD_1_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISP_RD_1_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_0_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_0_QOSGENERATOR_Peripheral_Access_Layer NOC_ISP_WR_0_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISP_WR_0_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISP_WR_0_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_0_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_0_QOSGENERATOR_Register_Masks NOC_ISP_WR_0_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_WR_0_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISP_WR_0_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISP_WR_0_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISP_WR_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISP_WR_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISP_WR_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISP_WR_0_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISP_WR_0_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISP_WR_0_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISP_WR_0_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_WR_0_QOSGENERATOR_Register_Masks */ /* NOC_ISP_WR_0_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR_BASE (0x4AFF0F00u) /** Peripheral CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR ((NOC_ISP_WR_0_QOSGENERATOR_Type *)CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISP_WR_0_QOSGENERATOR peripheral base addresses */ #define NOC_ISP_WR_0_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISP_WR_0_QOSGENERATOR peripheral base pointers */ #define NOC_ISP_WR_0_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISP_WR_0_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_0_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_0_XSTATFILTER_Peripheral_Access_Layer NOC_ISP_WR_0_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISP_WR_0_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISP_WR_0_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_0_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_0_XSTATFILTER_Register_Masks NOC_ISP_WR_0_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISP_WR_0_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISP_WR_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISP_WR_0_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISP_WR_0_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISP_WR_0_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISP_WR_0_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISP_WR_0_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISP_WR_0_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISP_WR_0_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISP_WR_0_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_0_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISP_WR_0_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_WR_0_XSTATFILTER_Register_Masks */ /* NOC_ISP_WR_0_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1300u) /** Peripheral CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISP_WR_0_XSTATFILTER_Type *)CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISP_WR_0_XSTATFILTER peripheral base addresses */ #define NOC_ISP_WR_0_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISP_WR_0_XSTATFILTER peripheral base pointers */ #define NOC_ISP_WR_0_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISP_WR_0_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_1_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_1_QOSGENERATOR_Peripheral_Access_Layer NOC_ISP_WR_1_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_ISP_WR_1_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_ISP_WR_1_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_1_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_1_QOSGENERATOR_Register_Masks NOC_ISP_WR_1_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_WR_1_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_ISP_WR_1_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_ISP_WR_1_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_ISP_WR_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_ISP_WR_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_ISP_WR_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_ISP_WR_1_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_ISP_WR_1_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_ISP_WR_1_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_ISP_WR_1_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_WR_1_QOSGENERATOR_Register_Masks */ /* NOC_ISP_WR_1_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR base address */ #define CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR_BASE (0x4AFF0F80u) /** Peripheral CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR base pointer */ #define CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR ((NOC_ISP_WR_1_QOSGENERATOR_Type *)CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_ISP_WR_1_QOSGENERATOR peripheral base addresses */ #define NOC_ISP_WR_1_QOSGENERATOR_BASE_ADDRS { CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_ISP_WR_1_QOSGENERATOR peripheral base pointers */ #define NOC_ISP_WR_1_QOSGENERATOR_BASE_PTRS { CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_ISP_WR_1_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_1_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_1_XSTATFILTER_Peripheral_Access_Layer NOC_ISP_WR_1_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_ISP_WR_1_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_ISP_WR_1_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_ISP_WR_1_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_ISP_WR_1_XSTATFILTER_Register_Masks NOC_ISP_WR_1_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_ISP_WR_1_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_ISP_WR_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_ISP_WR_1_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_ISP_WR_1_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_ISP_WR_1_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_ISP_WR_1_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_USERBASE_USERBASE_MASK (0x7FFFFFFFU) #define NOC_ISP_WR_1_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_ISP_WR_1_XSTATFILTER_USERMASK_USERMASK_MASK (0x7FFFFFFFU) #define NOC_ISP_WR_1_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_ISP_WR_1_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_ISP_WR_1_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_ISP_WR_1_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_ISP_WR_1_XSTATFILTER_Register_Masks */ /* NOC_ISP_WR_1_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER base address */ #define CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1380u) /** Peripheral CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER ((NOC_ISP_WR_1_XSTATFILTER_Type *)CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_ISP_WR_1_XSTATFILTER peripheral base addresses */ #define NOC_ISP_WR_1_XSTATFILTER_BASE_ADDRS { CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_ISP_WR_1_XSTATFILTER peripheral base pointers */ #define NOC_ISP_WR_1_XSTATFILTER_BASE_PTRS { CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_ISP_WR_1_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_MAIN_PROBE_Peripheral_Access_Layer NOC_JPEG_DEC_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_JPEG_DEC_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_JPEG_DEC_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_MAIN_PROBE_Register_Masks NOC_JPEG_DEC_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_JPEG_DEC_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_JPEG_DEC_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_JPEG_DEC_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_JPEG_DEC_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_JPEG_DEC_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_JPEG_DEC_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_JPEG_DEC_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_JPEG_DEC_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_JPEG_DEC_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_JPEG_DEC_MAIN_PROBE_SRC */ #define NOC_JPEG_DEC_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_JPEG_DEC_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_JPEG_DEC_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_JPEG_DEC_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_JPEG_DEC_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_JPEG_DEC_MAIN_PROBE_VAL */ #define NOC_JPEG_DEC_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_JPEG_DEC_MAIN_PROBE_Register_Masks */ /* NOC_JPEG_DEC_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE base address */ #define VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE_BASE (0x4C801000u) /** Peripheral VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE base pointer */ #define VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE ((NOC_JPEG_DEC_MAIN_PROBE_Type *)VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE_BASE) /** Array initializer of NOC_JPEG_DEC_MAIN_PROBE peripheral base addresses */ #define NOC_JPEG_DEC_MAIN_PROBE_BASE_ADDRS { VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE_BASE } /** Array initializer of NOC_JPEG_DEC_MAIN_PROBE peripheral base pointers */ #define NOC_JPEG_DEC_MAIN_PROBE_BASE_PTRS { VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE } /*! * @} */ /* end of group NOC_JPEG_DEC_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_PROBE_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_PROBE_XSTATPROFILER_Peripheral_Access_Layer NOC_JPEG_DEC_PROBE_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_JPEG_DEC_PROBE_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES_0; /**< Number of Transaction Probe Lines, offset: 0x20 */ uint8_t RESERVED_1[8]; __IO uint32_t TRANSACTIONSTATPROFILER_THRESHOLDS_[2][4]; /**< Transaction Profiler Thresholds Register, array offset: 0x2C, array step: index*0x10, index2*0x4 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_JPEG_DEC_PROBE_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_PROBE_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_PROBE_XSTATPROFILER_Register_Masks NOC_JPEG_DEC_PROBE_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_EN_EN_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES_0 - Number of Transaction Probe Lines */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK (0x3U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_THRESHOLDS_ - Transaction Profiler Thresholds Register */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK (0x7FFU) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT (0U) /*! THRESHOLDS - Thresholds 1 3 */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK) /*! @} */ /* The count of NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT (2U) /* The count of NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT2 (4U) /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_JPEG_DEC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_DEC_PROBE_XSTATPROFILER_Register_Masks */ /* NOC_JPEG_DEC_PROBE_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER base * address */ #define VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C801580u) /** Peripheral VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER base * pointer */ #define VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER ((NOC_JPEG_DEC_PROBE_XSTATPROFILER_Type *)VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_JPEG_DEC_PROBE_XSTATPROFILER peripheral base * addresses */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_BASE_ADDRS { VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_JPEG_DEC_PROBE_XSTATPROFILER peripheral base * pointers */ #define NOC_JPEG_DEC_PROBE_XSTATPROFILER_BASE_PTRS { VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_JPEG_DEC_PROBE_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_JPEG_DEC_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_JPEG_DEC_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ uint8_t RESERVED_0[4]; __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_1[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_JPEG_DEC_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_RD_I_XSTATFILTER_Register_Masks NOC_JPEG_DEC_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_JPEG_DEC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_DEC_RD_I_XSTATFILTER_Register_Masks */ /* NOC_JPEG_DEC_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C801480u) /** Peripheral VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_JPEG_DEC_RD_I_XSTATFILTER_Type *)VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_JPEG_DEC_RD_I_XSTATFILTER peripheral base addresses * */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_BASE_ADDRS { VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_JPEG_DEC_RD_I_XSTATFILTER peripheral base pointers * */ #define NOC_JPEG_DEC_RD_I_XSTATFILTER_BASE_PTRS { VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_JPEG_DEC_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_JPEG_DEC_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_JPEG_DEC_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_JPEG_DEC_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_WR_I_QOSGENERATOR_Register_Masks NOC_JPEG_DEC_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_JPEG_DEC_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_DEC_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_JPEG_DEC_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR base address */ #define VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR_BASE (0x4C801400u) /** Peripheral VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR base pointer */ #define VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR ((NOC_JPEG_DEC_WR_I_QOSGENERATOR_Type *)VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_JPEG_DEC_WR_I_QOSGENERATOR peripheral base * addresses */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_BASE_ADDRS { VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_JPEG_DEC_WR_I_QOSGENERATOR peripheral base pointers * */ #define NOC_JPEG_DEC_WR_I_QOSGENERATOR_BASE_PTRS { VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_JPEG_DEC_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_JPEG_DEC_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_JPEG_DEC_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ uint8_t RESERVED_0[4]; __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_1[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_JPEG_DEC_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_DEC_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_DEC_WR_I_XSTATFILTER_Register_Masks NOC_JPEG_DEC_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_JPEG_DEC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_DEC_WR_I_XSTATFILTER_Register_Masks */ /* NOC_JPEG_DEC_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C801500u) /** Peripheral VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_JPEG_DEC_WR_I_XSTATFILTER_Type *)VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_JPEG_DEC_WR_I_XSTATFILTER peripheral base addresses * */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_BASE_ADDRS { VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_JPEG_DEC_WR_I_XSTATFILTER peripheral base pointers * */ #define NOC_JPEG_DEC_WR_I_XSTATFILTER_BASE_PTRS { VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_JPEG_DEC_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_MAIN_PROBE_Peripheral_Access_Layer NOC_JPEG_ENC_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_JPEG_ENC_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_JPEG_ENC_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_MAIN_PROBE_Register_Masks NOC_JPEG_ENC_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_JPEG_ENC_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_JPEG_ENC_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_JPEG_ENC_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_JPEG_ENC_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_JPEG_ENC_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_JPEG_ENC_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_JPEG_ENC_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_JPEG_ENC_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_JPEG_ENC_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_JPEG_ENC_MAIN_PROBE_SRC */ #define NOC_JPEG_ENC_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_JPEG_ENC_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_JPEG_ENC_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_JPEG_ENC_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_JPEG_ENC_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_JPEG_ENC_MAIN_PROBE_VAL */ #define NOC_JPEG_ENC_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_JPEG_ENC_MAIN_PROBE_Register_Masks */ /* NOC_JPEG_ENC_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE base address */ #define VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE_BASE (0x4C802000u) /** Peripheral VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE base pointer */ #define VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE ((NOC_JPEG_ENC_MAIN_PROBE_Type *)VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE_BASE) /** Array initializer of NOC_JPEG_ENC_MAIN_PROBE peripheral base addresses */ #define NOC_JPEG_ENC_MAIN_PROBE_BASE_ADDRS { VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE_BASE } /** Array initializer of NOC_JPEG_ENC_MAIN_PROBE peripheral base pointers */ #define NOC_JPEG_ENC_MAIN_PROBE_BASE_PTRS { VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE } /*! * @} */ /* end of group NOC_JPEG_ENC_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_PROBE_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_PROBE_XSTATPROFILER_Peripheral_Access_Layer NOC_JPEG_ENC_PROBE_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_JPEG_ENC_PROBE_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES_0; /**< Number of Transaction Probe Lines, offset: 0x20 */ uint8_t RESERVED_1[8]; __IO uint32_t TRANSACTIONSTATPROFILER_THRESHOLDS_[2][4]; /**< Transaction Profiler Thresholds Register, array offset: 0x2C, array step: index*0x10, index2*0x4 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_JPEG_ENC_PROBE_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_PROBE_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_PROBE_XSTATPROFILER_Register_Masks NOC_JPEG_ENC_PROBE_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_EN_EN_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES_0 - Number of Transaction Probe Lines */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK (0x7U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_THRESHOLDS_ - Transaction Profiler Thresholds Register */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK (0x7FFU) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT (0U) /*! THRESHOLDS - Thresholds 1 3 */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK) /*! @} */ /* The count of NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT (2U) /* The count of NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT2 (4U) /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_JPEG_ENC_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_ENC_PROBE_XSTATPROFILER_Register_Masks */ /* NOC_JPEG_ENC_PROBE_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER base * address */ #define VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C802580u) /** Peripheral VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER base * pointer */ #define VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER ((NOC_JPEG_ENC_PROBE_XSTATPROFILER_Type *)VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_JPEG_ENC_PROBE_XSTATPROFILER peripheral base * addresses */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_BASE_ADDRS { VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_JPEG_ENC_PROBE_XSTATPROFILER peripheral base * pointers */ #define NOC_JPEG_ENC_PROBE_XSTATPROFILER_BASE_PTRS { VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_JPEG_ENC_PROBE_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_JPEG_ENC_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_JPEG_ENC_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_JPEG_ENC_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_RD_I_QOSGENERATOR_Register_Masks NOC_JPEG_ENC_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_JPEG_ENC_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_ENC_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_JPEG_ENC_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR base address */ #define VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR_BASE (0x4C802400u) /** Peripheral VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR base pointer */ #define VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR ((NOC_JPEG_ENC_RD_I_QOSGENERATOR_Type *)VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_JPEG_ENC_RD_I_QOSGENERATOR peripheral base * addresses */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_BASE_ADDRS { VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_JPEG_ENC_RD_I_QOSGENERATOR peripheral base pointers * */ #define NOC_JPEG_ENC_RD_I_QOSGENERATOR_BASE_PTRS { VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_JPEG_ENC_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_JPEG_ENC_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_JPEG_ENC_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ uint8_t RESERVED_0[4]; __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_1[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_JPEG_ENC_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_RD_I_XSTATFILTER_Register_Masks NOC_JPEG_ENC_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_JPEG_ENC_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_ENC_RD_I_XSTATFILTER_Register_Masks */ /* NOC_JPEG_ENC_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C802480u) /** Peripheral VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_JPEG_ENC_RD_I_XSTATFILTER_Type *)VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_JPEG_ENC_RD_I_XSTATFILTER peripheral base addresses * */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_BASE_ADDRS { VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_JPEG_ENC_RD_I_XSTATFILTER peripheral base pointers * */ #define NOC_JPEG_ENC_RD_I_XSTATFILTER_BASE_PTRS { VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_JPEG_ENC_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_JPEG_ENC_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_JPEG_ENC_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ uint8_t RESERVED_0[4]; __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_1[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_JPEG_ENC_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_JPEG_ENC_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_JPEG_ENC_WR_I_XSTATFILTER_Register_Masks NOC_JPEG_ENC_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_JPEG_ENC_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_JPEG_ENC_WR_I_XSTATFILTER_Register_Masks */ /* NOC_JPEG_ENC_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C802500u) /** Peripheral VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_JPEG_ENC_WR_I_XSTATFILTER_Type *)VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_JPEG_ENC_WR_I_XSTATFILTER peripheral base addresses * */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_BASE_ADDRS { VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_JPEG_ENC_WR_I_XSTATFILTER peripheral base pointers * */ #define NOC_JPEG_ENC_WR_I_XSTATFILTER_BASE_PTRS { VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_JPEG_ENC_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_LSTCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_LSTCU_Peripheral_Access_Layer NOC_LSTCU Peripheral Access Layer * @{ */ /** NOC_LSTCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x10 */ uint8_t RESERVED_2[76]; __I uint32_t MB_RSTAT0; /**< MBIST Run Status 0, offset: 0x60 */ uint8_t RESERVED_3[284]; __IO uint32_t MBFM0; /**< MBIST Fault Mapping 0, offset: 0x180 */ uint8_t RESERVED_4[220]; __IO uint32_t STAG; /**< Stagger, offset: 0x260 */ uint8_t RESERVED_5[12]; __IO uint32_t PH1_DUR; /**< Phase 1 Duration, offset: 0x270 */ uint8_t RESERVED_6[140]; __IO uint32_t MBPTR[1]; /**< MBIST Scheduler Pointer, array offset: 0x300, array step: 0x4 */ } NOC_LSTCU_Type; /* ---------------------------------------------------------------------------- -- NOC_LSTCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_LSTCU_Register_Masks NOC_LSTCU Register Masks * @{ */ /*! @name ERR_STAT - Error Status */ /*! @{ */ #define NOC_LSTCU_ERR_STAT_INVP_MB_MASK (0x2U) #define NOC_LSTCU_ERR_STAT_INVP_MB_SHIFT (1U) /*! INVP_MB - Invalid Pointer MBIST * 0b0..No invalid pointer * 0b1..Invalid BIST pointer specified */ #define NOC_LSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_ERR_STAT_INVP_MB_SHIFT)) & NOC_LSTCU_ERR_STAT_INVP_MB_MASK) #define NOC_LSTCU_ERR_STAT_UFSF_MASK (0x10000U) #define NOC_LSTCU_ERR_STAT_UFSF_SHIFT (16U) /*! UFSF - Unrecoverable Fault Status * 0b0..No unrecoverable fault * 0b1..Unrecoverable fault */ #define NOC_LSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_ERR_STAT_UFSF_SHIFT)) & NOC_LSTCU_ERR_STAT_UFSF_MASK) #define NOC_LSTCU_ERR_STAT_RFSF_MASK (0x20000U) #define NOC_LSTCU_ERR_STAT_RFSF_SHIFT (17U) /*! RFSF - Recoverable Fault Status * 0b0..No recoverable fault * 0b1..Recoverable fault */ #define NOC_LSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_ERR_STAT_RFSF_SHIFT)) & NOC_LSTCU_ERR_STAT_RFSF_MASK) /*! @} */ /*! @name ERR_FM - Error Fault Mapping */ /*! @{ */ #define NOC_LSTCU_ERR_FM_INVPFMMB_MASK (0x2U) #define NOC_LSTCU_ERR_FM_INVPFMMB_SHIFT (1U) /*! INVPFMMB - Invalid BIST Pointer Fault Mapping During MBIST Scheduling * 0b0..Recoverable * 0b1..Unrecoverable */ #define NOC_LSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_ERR_FM_INVPFMMB_SHIFT)) & NOC_LSTCU_ERR_FM_INVPFMMB_MASK) /*! @} */ /*! @name MB_RSTAT0 - MBIST Run Status 0 */ /*! @{ */ #define NOC_LSTCU_MB_RSTAT0_MBSTAT0_MASK (0x1U) #define NOC_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT (0U) /*! MBSTAT0 - MBIST Run Result Status 0 * 0b0..Pass * 0b1..Fail */ #define NOC_LSTCU_MB_RSTAT0_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT)) & NOC_LSTCU_MB_RSTAT0_MBSTAT0_MASK) /*! @} */ /*! @name MBFM0 - MBIST Fault Mapping 0 */ /*! @{ */ #define NOC_LSTCU_MBFM0_MBSTATFM0_MASK (0x1U) #define NOC_LSTCU_MBFM0_MBSTATFM0_SHIFT (0U) /*! MBSTATFM0 - MBIST Fault Mapping n * 0b0..Recoverable * 0b1..Unrecoverable */ #define NOC_LSTCU_MBFM0_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_MBFM0_MBSTATFM0_SHIFT)) & NOC_LSTCU_MBFM0_MBSTATFM0_MASK) /*! @} */ /*! @name STAG - Stagger */ /*! @{ */ #define NOC_LSTCU_STAG_MB_DELAY_MASK (0xFF00U) #define NOC_LSTCU_STAG_MB_DELAY_SHIFT (8U) /*! MB_DELAY - MBIST Delay */ #define NOC_LSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_STAG_MB_DELAY_SHIFT)) & NOC_LSTCU_STAG_MB_DELAY_MASK) /*! @} */ /*! @name PH1_DUR - Phase 1 Duration */ /*! @{ */ #define NOC_LSTCU_PH1_DUR_PH1DUR_MASK (0x3FFU) #define NOC_LSTCU_PH1_DUR_PH1DUR_SHIFT (0U) /*! PH1DUR - Phase 1 Duration */ #define NOC_LSTCU_PH1_DUR_PH1DUR(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_PH1_DUR_PH1DUR_SHIFT)) & NOC_LSTCU_PH1_DUR_PH1DUR_MASK) /*! @} */ /*! @name MBPTR - MBIST Scheduler Pointer */ /*! @{ */ #define NOC_LSTCU_MBPTR_MBPTR_MASK (0xFFU) #define NOC_LSTCU_MBPTR_MBPTR_SHIFT (0U) /*! MBPTR - MBIST Pointer */ #define NOC_LSTCU_MBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_MBPTR_MBPTR_SHIFT)) & NOC_LSTCU_MBPTR_MBPTR_MASK) #define NOC_LSTCU_MBPTR_MBCSM_MASK (0x100U) #define NOC_LSTCU_MBPTR_MBCSM_SHIFT (8U) /*! MBCSM - MBIST Mode * 0b0..Sequential * 0b1..Concurrent */ #define NOC_LSTCU_MBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_MBPTR_MBCSM_SHIFT)) & NOC_LSTCU_MBPTR_MBCSM_MASK) #define NOC_LSTCU_MBPTR_MBEOL_MASK (0x80000000U) #define NOC_LSTCU_MBPTR_MBEOL_SHIFT (31U) /*! MBEOL - MBIST End of List * 0b0..Not end of list * 0b1..End of list */ #define NOC_LSTCU_MBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << NOC_LSTCU_MBPTR_MBEOL_SHIFT)) & NOC_LSTCU_MBPTR_MBEOL_MASK) /*! @} */ /* The count of NOC_LSTCU_MBPTR */ #define NOC_LSTCU_MBPTR_COUNT (1U) /*! * @} */ /* end of group NOC_LSTCU_Register_Masks */ /* NOC_LSTCU - Peripheral instance base addresses */ /** Peripheral NOC__LSTCUN base address */ #define NOC__LSTCUN_BASE (0x490B0000u) /** Peripheral NOC__LSTCUN base pointer */ #define NOC__LSTCUN ((NOC_LSTCU_Type *)NOC__LSTCUN_BASE) /** Array initializer of NOC_LSTCU peripheral base addresses */ #define NOC_LSTCU_BASE_ADDRS { NOC__LSTCUN_BASE } /** Array initializer of NOC_LSTCU peripheral base pointers */ #define NOC_LSTCU_BASE_PTRS { NOC__LSTCUN } /*! * @} */ /* end of group NOC_LSTCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_0_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_0_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_0_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_0_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_0_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_MAIN_PROBE_Register_Masks NOC_M_E_0_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_0_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_0_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_0_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_0_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_0_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_0_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_0_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_0_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_0_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_0_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_0_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_0_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_0_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_0_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_0_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_0_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_0_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_0_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_0_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_0_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_0_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_0_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_0_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_0_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_0_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_0_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_0_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_0_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_0_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_0_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_0_MAIN_PROBE_SRC */ #define NOC_M_E_0_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_0_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_0_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_0_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_0_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_0_MAIN_PROBE_VAL */ #define NOC_M_E_0_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_0_MAIN_PROBE_Register_Masks */ /* NOC_M_E_0_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_0_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_0_MAIN_PROBE_BASE (0x49060000u) /** Peripheral NOC__GPV__PROBE_M_E_0_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_0_MAIN_PROBE ((NOC_M_E_0_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_0_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_0_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_0_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_0_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_0_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_0_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_0_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_0_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_0_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_0_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_0_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_0_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_0_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_0_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_0_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_0_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_0_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_0_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_M_E_0_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_0_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_0_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_0_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_0_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_0_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_0_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_0_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR_BASE (0x49062400u) /** Peripheral NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_0_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_0_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_0_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_0_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_0_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_0_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_0_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_0_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_0_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_0_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_0_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_RD_I_XSTATFILTER_Register_Masks NOC_M_E_0_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_0_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_0_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_0_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_0_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_0_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_0_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_0_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_0_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063100u) /** Peripheral NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_0_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_0_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_0_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_0_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_0_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_0_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_0_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_0_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_0_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_0_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_0_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_0_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_0_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_0_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_0_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_0_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_M_E_0_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_0_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_0_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_0_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_0_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_0_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_0_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_0_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR_BASE (0x49062480u) /** Peripheral NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_0_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_0_WR_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_0_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_0_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_0_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_0_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_0_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_0_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_0_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_0_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_0_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_0_WR_I_XSTATFILTER_Register_Masks NOC_M_E_0_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_0_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_0_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_0_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_0_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_0_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_0_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_0_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_0_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_0_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063180u) /** Peripheral NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_0_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_0_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_0_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_0_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_0_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_0_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_10_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_10_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_10_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_10_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_10_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_MAIN_PROBE_Register_Masks NOC_M_E_10_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_10_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_10_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_10_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_10_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_10_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_10_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_10_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_10_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_10_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_10_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_10_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_10_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_10_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_10_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_10_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_10_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_10_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_10_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_10_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_10_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_10_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_10_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_10_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_10_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_10_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_10_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_10_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_10_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_10_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_10_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_10_MAIN_PROBE_SRC */ #define NOC_M_E_10_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_10_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_10_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_10_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_10_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_10_MAIN_PROBE_VAL */ #define NOC_M_E_10_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_10_MAIN_PROBE_Register_Masks */ /* NOC_M_E_10_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_10_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_10_MAIN_PROBE_BASE (0x49061C00u) /** Peripheral NOC__GPV__PROBE_M_E_10_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_10_MAIN_PROBE ((NOC_M_E_10_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_10_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_10_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_10_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_10_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_10_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_10_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_10_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_10_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_10_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_10_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_10_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_10_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_10_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_10_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_10_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_10_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_10_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_10_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_10_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_10_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_10_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_10_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_10_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_10_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_10_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_10_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR_BASE (0x49062E80u) /** Peripheral NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_10_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_10_RD_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_10_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_10_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_10_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_10_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_10_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_10_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_10_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_10_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_10_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_RD_I_XSTATFILTER_Register_Masks NOC_M_E_10_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_10_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_10_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_10_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_10_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_10_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_10_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_10_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_10_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063780u) /** Peripheral NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_10_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_10_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_10_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_10_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_10_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_10_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_10_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_10_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_10_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_10_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_10_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_10_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_10_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_10_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_10_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_10_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_10_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_10_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_10_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_10_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_10_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_10_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_10_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_10_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR_BASE (0x49062F00u) /** Peripheral NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_10_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_10_WR_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_10_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_10_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_10_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_10_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_10_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_10_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_10_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_10_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_10_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_10_WR_I_XSTATFILTER_Register_Masks NOC_M_E_10_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_10_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_10_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_10_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_10_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_10_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_10_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_10_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_10_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_10_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063800u) /** Peripheral NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_10_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_10_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_10_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_10_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_10_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_10_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_11_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_11_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_11_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_11_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_11_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_MAIN_PROBE_Register_Masks NOC_M_E_11_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_11_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_11_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_11_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_11_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_11_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_11_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_11_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_11_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_11_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_11_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_11_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_11_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_11_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_11_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_11_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_11_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_11_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_11_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_11_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_11_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_11_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_11_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_11_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_11_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_11_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_11_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_11_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_11_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_11_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_11_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_11_MAIN_PROBE_SRC */ #define NOC_M_E_11_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_11_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_11_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_11_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_11_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_11_MAIN_PROBE_VAL */ #define NOC_M_E_11_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_11_MAIN_PROBE_Register_Masks */ /* NOC_M_E_11_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_11_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_11_MAIN_PROBE_BASE (0x49062000u) /** Peripheral NOC__GPV__PROBE_M_E_11_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_11_MAIN_PROBE ((NOC_M_E_11_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_11_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_11_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_11_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_11_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_11_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_11_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_11_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_11_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_11_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_11_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_11_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_11_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_11_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_11_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_11_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_11_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_11_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_11_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_11_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_11_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_11_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_11_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_11_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_11_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_11_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_11_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR_BASE (0x49062F80u) /** Peripheral NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_11_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_11_RD_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_11_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_11_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_11_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_11_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_11_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_11_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_11_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_11_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_11_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_RD_I_XSTATFILTER_Register_Masks NOC_M_E_11_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_11_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_11_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_11_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_11_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_11_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_11_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_11_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_11_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063880u) /** Peripheral NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_11_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_11_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_11_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_11_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_11_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_11_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_11_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_11_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_11_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_11_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_11_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_11_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_11_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_11_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_11_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_11_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_11_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_11_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_11_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_11_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_11_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_11_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_11_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_11_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR_BASE (0x49063000u) /** Peripheral NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_11_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_11_WR_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_11_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_11_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_11_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_11_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_11_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_11_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_11_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_11_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_11_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_11_WR_I_XSTATFILTER_Register_Masks NOC_M_E_11_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_11_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_11_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_11_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_11_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_11_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_11_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_11_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_11_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_11_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063900u) /** Peripheral NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_11_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_11_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_11_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_11_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_11_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_11_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_1A_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1A_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_1A_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_1A_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_1A_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_1A_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1A_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_1A_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_1A_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_1A_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_1A_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_1A_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_1A_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR_BASE (0x49062500u) /** Peripheral NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_1A_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_1A_RD_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_1A_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_1A_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_1A_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_1A_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1A_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_1A_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_1A_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_1A_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_1A_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1A_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_1A_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_1A_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_1A_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_1A_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_1A_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_1A_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR_BASE (0x49062580u) /** Peripheral NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_1A_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_1A_WR_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_1A_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_1A_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_1A_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_1B_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1B_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_1B_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_1B_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_1B_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_1B_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1B_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_1B_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_1B_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_1B_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_1B_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_1B_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_1B_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR_BASE (0x49062600u) /** Peripheral NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_1B_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_1B_RD_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_1B_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_1B_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_1B_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_1B_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1B_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_1B_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_1B_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_1B_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_1B_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_1B_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_1B_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_1B_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_1B_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_1B_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_1B_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_1B_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR_BASE (0x49062680u) /** Peripheral NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_1B_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_1B_WR_I_QOSGENERATOR peripheral base addresses * */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_1B_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_1B_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_1B_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_3_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_3_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_3_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_3_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_3_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_MAIN_PROBE_Register_Masks NOC_M_E_3_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_3_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_3_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_3_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_3_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_3_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_3_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_3_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_3_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_3_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_3_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_3_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_3_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_3_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_3_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_3_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_3_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_3_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_3_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_3_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_3_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_3_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_3_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_3_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_3_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_3_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_3_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_3_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_3_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_3_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_3_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_3_MAIN_PROBE_SRC */ #define NOC_M_E_3_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_3_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_3_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_3_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_3_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_3_MAIN_PROBE_VAL */ #define NOC_M_E_3_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_3_MAIN_PROBE_Register_Masks */ /* NOC_M_E_3_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_3_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_3_MAIN_PROBE_BASE (0x49060400u) /** Peripheral NOC__GPV__PROBE_M_E_3_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_3_MAIN_PROBE ((NOC_M_E_3_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_3_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_3_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_3_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_3_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_3_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_3_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_3_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_3_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_3_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_3_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_3_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_3_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_3_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_3_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_3_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_3_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_3_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_3_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_3_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_3_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_3_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_3_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_3_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_3_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_3_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_3_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR_BASE (0x49062800u) /** Peripheral NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_3_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_3_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_3_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_3_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_3_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_3_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_3_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_3_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_3_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_3_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_3_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_RD_I_XSTATFILTER_Register_Masks NOC_M_E_3_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_3_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_3_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_3_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_3_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_3_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_3_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_3_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_3_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063200u) /** Peripheral NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_3_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_3_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_3_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_3_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_3_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_3_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_3_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_3_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_3_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_3_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_3_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_3_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_3_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_3_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_3_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_3_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_3_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_3_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_3_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_3_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_3_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_3_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_3_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_3_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR_BASE (0x49062880u) /** Peripheral NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_3_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_3_WR_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_3_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_3_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_3_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_3_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_3_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_3_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_3_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_3_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_3_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_3_WR_I_XSTATFILTER_Register_Masks NOC_M_E_3_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_3_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_3_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_3_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_3_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_3_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_3_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_3_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_3_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_3_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063280u) /** Peripheral NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_3_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_3_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_3_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_3_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_3_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_3_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_4_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_4_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_4_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_4_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_4_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_MAIN_PROBE_Register_Masks NOC_M_E_4_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_4_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_4_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_4_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_4_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_4_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_4_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_4_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_4_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_4_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_4_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_4_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_4_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_4_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_4_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_4_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_4_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_4_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_4_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_4_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_4_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_4_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_4_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_4_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_4_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_4_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_4_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_4_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_4_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_4_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_4_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_4_MAIN_PROBE_SRC */ #define NOC_M_E_4_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_4_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_4_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_4_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_4_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_4_MAIN_PROBE_VAL */ #define NOC_M_E_4_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_4_MAIN_PROBE_Register_Masks */ /* NOC_M_E_4_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_4_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_4_MAIN_PROBE_BASE (0x49060800u) /** Peripheral NOC__GPV__PROBE_M_E_4_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_4_MAIN_PROBE ((NOC_M_E_4_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_4_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_4_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_4_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_4_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_4_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_4_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_4_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_4_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_4_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_4_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_4_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_4_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_4_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_4_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_4_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_4_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_4_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_4_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_4_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_4_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_4_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_4_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_4_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_4_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_4_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_4_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR_BASE (0x49062900u) /** Peripheral NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_4_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_4_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_4_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_4_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_4_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_4_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_4_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_4_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_4_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_4_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_4_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_RD_I_XSTATFILTER_Register_Masks NOC_M_E_4_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_4_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_4_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_4_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_4_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_4_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_4_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_4_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_4_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063300u) /** Peripheral NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_4_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_4_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_4_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_4_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_4_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_4_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_4_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_4_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_4_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_4_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_4_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_4_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_4_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_4_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_4_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_4_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_4_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_4_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_4_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_4_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_4_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_4_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_4_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_4_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR_BASE (0x49062980u) /** Peripheral NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_4_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_4_WR_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_4_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_4_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_4_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_4_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_4_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_4_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_4_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_4_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_4_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_4_WR_I_XSTATFILTER_Register_Masks NOC_M_E_4_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_4_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_4_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_4_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_4_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_4_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_4_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_4_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_4_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_4_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063380u) /** Peripheral NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_4_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_4_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_4_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_4_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_4_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_4_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_5_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_5_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_5_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_5_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_5_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_MAIN_PROBE_Register_Masks NOC_M_E_5_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_5_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_5_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_5_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_5_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_5_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_5_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_5_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_5_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_5_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_5_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_5_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_5_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_5_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_5_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_5_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_5_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_5_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_5_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_5_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_5_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_5_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_5_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_5_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_5_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_5_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_5_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_5_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_5_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_5_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_5_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_5_MAIN_PROBE_SRC */ #define NOC_M_E_5_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_5_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_5_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_5_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_5_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_5_MAIN_PROBE_VAL */ #define NOC_M_E_5_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_5_MAIN_PROBE_Register_Masks */ /* NOC_M_E_5_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_5_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_5_MAIN_PROBE_BASE (0x49060C00u) /** Peripheral NOC__GPV__PROBE_M_E_5_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_5_MAIN_PROBE ((NOC_M_E_5_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_5_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_5_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_5_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_5_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_5_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_5_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_5_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_5_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_5_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_5_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_5_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_5_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_5_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_5_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_5_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_5_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_5_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_5_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_5_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_5_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_5_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_5_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_5_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_5_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_5_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_5_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR_BASE (0x49062A00u) /** Peripheral NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_5_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_5_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_5_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_5_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_5_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_5_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_5_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_5_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_5_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_5_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_5_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_RD_I_XSTATFILTER_Register_Masks NOC_M_E_5_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_5_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_5_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_5_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_5_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_5_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_5_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_5_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_5_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063400u) /** Peripheral NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_5_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_5_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_5_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_5_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_5_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_5_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_5_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_5_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_5_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_5_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_5_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_5_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_5_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_5_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_5_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_5_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_5_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_5_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_5_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_5_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_5_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_5_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_5_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_5_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR_BASE (0x49062A80u) /** Peripheral NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_5_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_5_WR_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_5_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_5_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_5_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_5_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_5_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_5_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_5_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_5_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_5_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_5_WR_I_XSTATFILTER_Register_Masks NOC_M_E_5_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_5_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_5_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_5_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_5_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_5_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_5_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_5_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_5_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_5_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063480u) /** Peripheral NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_5_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_5_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_5_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_5_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_5_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_5_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_6_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_6_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_6_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_6_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_6_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_6_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_6_MAIN_PROBE_Register_Masks NOC_M_E_6_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_6_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_6_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_6_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_6_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_6_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_6_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_6_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_6_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_6_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_6_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_6_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_6_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_6_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_6_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_6_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_6_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_6_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_6_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_6_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_6_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_6_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_6_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_6_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_6_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_6_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_6_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_6_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_6_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_6_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_6_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_6_MAIN_PROBE_SRC */ #define NOC_M_E_6_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_6_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_6_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_6_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_6_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_6_MAIN_PROBE_VAL */ #define NOC_M_E_6_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_6_MAIN_PROBE_Register_Masks */ /* NOC_M_E_6_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_6_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_6_MAIN_PROBE_BASE (0x49061000u) /** Peripheral NOC__GPV__PROBE_M_E_6_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_6_MAIN_PROBE ((NOC_M_E_6_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_6_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_6_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_6_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_6_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_6_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_6_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_6_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_6_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_6_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_6_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_6_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_6_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_6_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_6_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_6_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_6_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_6_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_6_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_6_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_6_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_6_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_6_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_6_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_6_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_6_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_6_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_6_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_6_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR_BASE (0x49062B00u) /** Peripheral NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_6_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_6_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_6_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_6_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_6_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_6_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_6_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_6_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_6_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_6_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_6_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_6_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_6_RD_I_XSTATFILTER_Register_Masks NOC_M_E_6_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_6_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_6_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_6_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_6_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_6_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_6_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_6_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_6_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_6_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063500u) /** Peripheral NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_6_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_6_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_6_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_6_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_6_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_6_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_7_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_7_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_7_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_7_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_7_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_MAIN_PROBE_Register_Masks NOC_M_E_7_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_7_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_7_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_7_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_7_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_7_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_7_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_7_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_7_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_7_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_7_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_7_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_7_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_7_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_7_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_7_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_7_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_7_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_7_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_7_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_7_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_7_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_7_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_7_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_7_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_7_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_7_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_7_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_7_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_7_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_7_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_7_MAIN_PROBE_SRC */ #define NOC_M_E_7_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_7_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_7_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_7_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_7_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_7_MAIN_PROBE_VAL */ #define NOC_M_E_7_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_7_MAIN_PROBE_Register_Masks */ /* NOC_M_E_7_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_7_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_7_MAIN_PROBE_BASE (0x49061400u) /** Peripheral NOC__GPV__PROBE_M_E_7_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_7_MAIN_PROBE ((NOC_M_E_7_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_7_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_7_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_7_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_7_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_7_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_7_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_7_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_7_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_7_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_7_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_7_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_7_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_7_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_7_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_7_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_7_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_7_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_7_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_M_E_7_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_7_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_7_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_7_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_7_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_7_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_7_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_7_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR_BASE (0x49062B80u) /** Peripheral NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_7_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_7_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_7_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_7_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_7_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_7_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_7_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_7_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_7_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_7_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_7_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_RD_I_XSTATFILTER_Register_Masks NOC_M_E_7_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_7_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_7_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_7_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_7_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_7_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_7_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_7_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_7_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063580u) /** Peripheral NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_7_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_7_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_7_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_7_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_7_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_7_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_7_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_7_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_7_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_7_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_7_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_7_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_7_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_7_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_7_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_7_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_M_E_7_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_7_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_7_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_7_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_7_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_7_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_7_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_7_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR_BASE (0x49062C00u) /** Peripheral NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_7_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_7_WR_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_7_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_7_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_7_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_7_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_7_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_7_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_7_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_7_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_7_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_7_WR_I_XSTATFILTER_Register_Masks NOC_M_E_7_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_7_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_7_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_7_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_7_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_7_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_7_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_7_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_7_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_7_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063600u) /** Peripheral NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_7_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_7_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_7_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_7_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_7_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_7_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_8_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_8_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_8_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_8_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_8_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_8_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_8_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_8_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_8_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_8_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_8_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_8_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_8_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_8_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_8_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_8_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_8_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_8_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_8_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_8_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR_BASE (0x49062C80u) /** Peripheral NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_8_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_8_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_8_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_8_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_8_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_8_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_8_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_8_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_8_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_8_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_8_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_8_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_8_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_8_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_8_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_8_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_8_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_8_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_8_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_8_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_8_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_8_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_8_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_8_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_8_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_8_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR_BASE (0x49062D00u) /** Peripheral NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_8_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_8_WR_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_8_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_8_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_8_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_8_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_9_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_MAIN_PROBE_Peripheral_Access_Layer NOC_M_E_9_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_M_E_9_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_M_E_9_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_9_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_MAIN_PROBE_Register_Masks NOC_M_E_9_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_9_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_9_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_9_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_9_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_9_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_9_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_9_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_9_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_M_E_9_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_M_E_9_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_M_E_9_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_M_E_9_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_M_E_9_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_M_E_9_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_M_E_9_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_M_E_9_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_M_E_9_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_M_E_9_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_M_E_9_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_M_E_9_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_M_E_9_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_M_E_9_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_M_E_9_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_M_E_9_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_M_E_9_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_M_E_9_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_M_E_9_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_M_E_9_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_M_E_9_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_M_E_9_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_M_E_9_MAIN_PROBE_SRC */ #define NOC_M_E_9_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_M_E_9_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0x3FFFFFFU) #define NOC_M_E_9_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_M_E_9_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_M_E_9_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_M_E_9_MAIN_PROBE_VAL */ #define NOC_M_E_9_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_M_E_9_MAIN_PROBE_Register_Masks */ /* NOC_M_E_9_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_9_MAIN_PROBE base address */ #define NOC__GPV__PROBE_M_E_9_MAIN_PROBE_BASE (0x49061800u) /** Peripheral NOC__GPV__PROBE_M_E_9_MAIN_PROBE base pointer */ #define NOC__GPV__PROBE_M_E_9_MAIN_PROBE ((NOC_M_E_9_MAIN_PROBE_Type *)NOC__GPV__PROBE_M_E_9_MAIN_PROBE_BASE) /** Array initializer of NOC_M_E_9_MAIN_PROBE peripheral base addresses */ #define NOC_M_E_9_MAIN_PROBE_BASE_ADDRS { NOC__GPV__PROBE_M_E_9_MAIN_PROBE_BASE } /** Array initializer of NOC_M_E_9_MAIN_PROBE peripheral base pointers */ #define NOC_M_E_9_MAIN_PROBE_BASE_PTRS { NOC__GPV__PROBE_M_E_9_MAIN_PROBE } /*! * @} */ /* end of group NOC_M_E_9_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_9_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_9_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_9_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_9_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_9_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_RD_I_QOSGENERATOR_Register_Masks NOC_M_E_9_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_9_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_9_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_9_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_9_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_9_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_9_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_9_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_9_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_9_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_9_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_9_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_9_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR_BASE (0x49062D80u) /** Peripheral NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR ((NOC_M_E_9_RD_I_QOSGENERATOR_Type *)NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_9_RD_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_9_RD_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_9_RD_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_9_RD_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_9_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_9_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_9_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_9_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_9_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_9_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_RD_I_XSTATFILTER_Register_Masks NOC_M_E_9_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_9_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_9_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_9_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_9_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_9_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_9_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_9_RD_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_9_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063680u) /** Peripheral NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_9_RD_I_XSTATFILTER_Type *)NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_9_RD_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_9_RD_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_9_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_9_RD_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_9_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_9_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_M_E_9_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_M_E_9_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_M_E_9_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_9_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_WR_I_QOSGENERATOR_Register_Masks NOC_M_E_9_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_9_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_M_E_9_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_M_E_9_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_M_E_9_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_M_E_9_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_M_E_9_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_M_E_9_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_M_E_9_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_M_E_9_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_M_E_9_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_9_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_M_E_9_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR base address */ #define NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR_BASE (0x49062E00u) /** Peripheral NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR base pointer */ #define NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR ((NOC_M_E_9_WR_I_QOSGENERATOR_Type *)NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_M_E_9_WR_I_QOSGENERATOR peripheral base addresses */ #define NOC_M_E_9_WR_I_QOSGENERATOR_BASE_ADDRS { NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_M_E_9_WR_I_QOSGENERATOR peripheral base pointers */ #define NOC_M_E_9_WR_I_QOSGENERATOR_BASE_PTRS { NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_M_E_9_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_M_E_9_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_M_E_9_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_M_E_9_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ } NOC_M_E_9_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_M_E_9_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_M_E_9_WR_I_XSTATFILTER_Register_Masks NOC_M_E_9_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_M_E_9_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFU) #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_M_E_9_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_M_E_9_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_M_E_9_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_M_E_9_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_M_E_9_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_M_E_9_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_M_E_9_WR_I_XSTATFILTER_Register_Masks */ /* NOC_M_E_9_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063700u) /** Peripheral NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_M_E_9_WR_I_XSTATFILTER_Type *)NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_M_E_9_WR_I_XSTATFILTER peripheral base addresses */ #define NOC_M_E_9_WR_I_XSTATFILTER_BASE_ADDRS { NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_M_E_9_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_M_E_9_WR_I_XSTATFILTER_BASE_PTRS { NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_M_E_9_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks */ /* NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0480u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * addresses */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * pointers */ #define NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_PCIE1_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks */ /* NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0400u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * addresses */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * pointers */ #define NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_PCIE1_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks */ /* NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0380u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * addresses */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * pointers */ #define NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_PCIE2_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks */ /* NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0300u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * addresses */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * pointers */ #define NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_PCIE2_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_POWER_MAIN_RESFAULTCONTROLLER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_POWER_MAIN_RESFAULTCONTROLLER_Peripheral_Access_Layer NOC_POWER_MAIN_RESFAULTCONTROLLER Peripheral Access Layer * @{ */ /** NOC_POWER_MAIN_RESFAULTCONTROLLER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __I uint32_t MISSIONFAULT[4]; /**< Mission Fault n, array offset: 0x8, array step: 0x4 */ __I uint32_t LATENTFAULT[4]; /**< Latent Fault n, array offset: 0x18, array step: 0x4 */ __I uint32_t FAULTS; /**< Interrupt Enable, offset: 0x28 */ __IO uint32_t INTEN; /**< Interrupt Enable, offset: 0x2C */ __O uint32_t INTCLR; /**< InterruptClear, offset: 0x30 */ __O uint32_t BISTCTL; /**< BistControl, offset: 0x34 */ __I uint32_t BISTDONE; /**< BistDone, offset: 0x38 */ __IO uint32_t BISTTO1; /**< Bist T01, offset: 0x3C */ __IO uint32_t BISTTO2; /**< Bist T02, offset: 0x40 */ } NOC_POWER_MAIN_RESFAULTCONTROLLER_Type; /* ---------------------------------------------------------------------------- -- NOC_POWER_MAIN_RESFAULTCONTROLLER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_POWER_MAIN_RESFAULTCONTROLLER_Register_Masks NOC_POWER_MAIN_RESFAULTCONTROLLER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORETYPEID_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORETYPEID_MASK) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_USERID_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_USERID_MASK) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_NOCID_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MISSIONFAULT - Mission Fault n */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_MASK (0xFFFFFFFFU) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_MASK) /*! @} */ /* The count of NOC_POWER_MAIN_RESFAULTCONTROLLER_MISSIONFAULT */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_MISSIONFAULT_COUNT (4U) /*! @name LATENTFAULT - Latent Fault n */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_MASK (0xFFFFFFFFU) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_LATENTFAULT_LATENTFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_MASK) /*! @} */ /* The count of NOC_POWER_MAIN_RESFAULTCONTROLLER_LATENTFAULT */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_LATENTFAULT_COUNT (4U) /*! @name FAULTS - Interrupt Enable */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_LATENTFAULT_MASK (0x1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_LATENTFAULT_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_LATENTFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_LATENTFAULT_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_LATENTFAULT_MASK) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_MISSIONFAULT_MASK (0x2U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_MISSIONFAULT_SHIFT (1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_MISSIONFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_MISSIONFAULT_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_FAULTS_MISSIONFAULT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_BISTDONEEN_MASK (0x1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_BISTDONEEN_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_BISTDONEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_BISTDONEEN_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_BISTDONEEN_MASK) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_MISSIONFAULTEN_MASK (0x2U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_MISSIONFAULTEN_SHIFT (1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_MISSIONFAULTEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_MISSIONFAULTEN_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_INTEN_MISSIONFAULTEN_MASK) /*! @} */ /*! @name INTCLR - InterruptClear */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_MASK (0x1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_LATENTFAULTCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_MASK) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_MASK (0x2U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_SHIFT (1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_MASK) /*! @} */ /*! @name BISTCTL - BistControl */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTSTART_MASK (0x1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTSTART_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTSTART(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTSTART_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTSTART_MASK) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTDONECLR_MASK (0x2U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTDONECLR_SHIFT (1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTDONECLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTDONECLR_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTCTL_BISTDONECLR_MASK) /*! @} */ /*! @name BISTDONE - BistDone */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_BISTDONE_MASK (0x1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_BISTDONE_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_BISTDONE(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_BISTDONE_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_BISTDONE_MASK) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_MISSIONMODE_MASK (0x2U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_MISSIONMODE_SHIFT (1U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_MISSIONMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_MISSIONMODE_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTDONE_MISSIONMODE_MASK) /*! @} */ /*! @name BISTTO1 - Bist T01 */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO1_BISTTO1_MASK (0xFFFFU) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO1_BISTTO1_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO1_BISTTO1(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO1_BISTTO1_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO1_BISTTO1_MASK) /*! @} */ /*! @name BISTTO2 - Bist T02 */ /*! @{ */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO2_BISTTO2_MASK (0xFFU) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO2_BISTTO2_SHIFT (0U) #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO2_BISTTO2(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO2_BISTTO2_SHIFT)) & NOC_POWER_MAIN_RESFAULTCONTROLLER_BISTTO2_BISTTO2_MASK) /*! @} */ /*! * @} */ /* end of group NOC_POWER_MAIN_RESFAULTCONTROLLER_Register_Masks */ /* NOC_POWER_MAIN_RESFAULTCONTROLLER - Peripheral instance base addresses */ /** Peripheral WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER base * address */ #define WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER_BASE (0x42830000u) /** Peripheral WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER base * pointer */ #define WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER ((NOC_POWER_MAIN_RESFAULTCONTROLLER_Type *)WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER_BASE) /** Array initializer of NOC_POWER_MAIN_RESFAULTCONTROLLER peripheral base * addresses */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BASE_ADDRS { WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER_BASE } /** Array initializer of NOC_POWER_MAIN_RESFAULTCONTROLLER peripheral base * pointers */ #define NOC_POWER_MAIN_RESFAULTCONTROLLER_BASE_PTRS { WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER } /*! * @} */ /* end of group NOC_POWER_MAIN_RESFAULTCONTROLLER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_POWER_RESILIENCEFAULTCONTROLLER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_POWER_RESILIENCEFAULTCONTROLLER_Peripheral_Access_Layer NOC_POWER_RESILIENCEFAULTCONTROLLER Peripheral Access Layer * @{ */ /** NOC_POWER_RESILIENCEFAULTCONTROLLER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __I uint32_t MISSIONFAULT[4]; /**< Mission Fault n, array offset: 0x8, array step: 0x4 */ __I uint32_t LATENTFAULT[4]; /**< Latent Fault n, array offset: 0x18, array step: 0x4 */ __I uint32_t FAULTS; /**< Faults, offset: 0x28 */ __IO uint32_t INTEN; /**< Interrupt Enable, offset: 0x2C */ __O uint32_t INTCLR; /**< InterruptClear, offset: 0x30 */ __O uint32_t BISTCTL; /**< BistControl, offset: 0x34 */ __I uint32_t BISTDONE; /**< BistDone, offset: 0x38 */ __IO uint32_t BISTTO1; /**< Bist T01, offset: 0x3C */ __IO uint32_t BISTTO2; /**< Bist T02, offset: 0x40 */ } NOC_POWER_RESILIENCEFAULTCONTROLLER_Type; /* ---------------------------------------------------------------------------- -- NOC_POWER_RESILIENCEFAULTCONTROLLER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_POWER_RESILIENCEFAULTCONTROLLER_Register_Masks NOC_POWER_RESILIENCEFAULTCONTROLLER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORETYPEID_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORETYPEID_MASK) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_USERID_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_USERID_MASK) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_NOCID_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MISSIONFAULT - Mission Fault n */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_MASK (0xFFFFFFFFU) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_MISSIONFAULT_MISSIONFAULT_MASK) /*! @} */ /* The count of NOC_POWER_RESILIENCEFAULTCONTROLLER_MISSIONFAULT */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_MISSIONFAULT_COUNT (4U) /*! @name LATENTFAULT - Latent Fault n */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_MASK (0xFFFFFFFFU) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_LATENTFAULT_LATENTFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_LATENTFAULT_LATENTFAULT_MASK) /*! @} */ /* The count of NOC_POWER_RESILIENCEFAULTCONTROLLER_LATENTFAULT */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_LATENTFAULT_COUNT (4U) /*! @name FAULTS - Faults */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_LATENTFAULT_MASK (0x1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_LATENTFAULT_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_LATENTFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_LATENTFAULT_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_LATENTFAULT_MASK) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_MISSIONFAULT_MASK (0x2U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_MISSIONFAULT_SHIFT (1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_MISSIONFAULT(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_MISSIONFAULT_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_FAULTS_MISSIONFAULT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_BISTDONEEN_MASK (0x1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_BISTDONEEN_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_BISTDONEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_BISTDONEEN_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_BISTDONEEN_MASK) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_MISSIONFAULTEN_MASK (0x2U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_MISSIONFAULTEN_SHIFT (1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_MISSIONFAULTEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_MISSIONFAULTEN_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_INTEN_MISSIONFAULTEN_MASK) /*! @} */ /*! @name INTCLR - InterruptClear */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_MASK (0x1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_LATENTFAULTCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_LATENTFAULTCLR_MASK) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_MASK (0x2U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_SHIFT (1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_INTCLR_MISSIONFAULTCLR_MASK) /*! @} */ /*! @name BISTCTL - BistControl */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTSTART_MASK (0x1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTSTART_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTSTART(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTSTART_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTSTART_MASK) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTDONECLR_MASK (0x2U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTDONECLR_SHIFT (1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTDONECLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTDONECLR_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTCTL_BISTDONECLR_MASK) /*! @} */ /*! @name BISTDONE - BistDone */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_BISTDONE_MASK (0x1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_BISTDONE_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_BISTDONE(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_BISTDONE_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_BISTDONE_MASK) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_MISSIONMODE_MASK (0x2U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_MISSIONMODE_SHIFT (1U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_MISSIONMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_MISSIONMODE_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTDONE_MISSIONMODE_MASK) /*! @} */ /*! @name BISTTO1 - Bist T01 */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO1_BISTTO1_MASK (0xFFFFU) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO1_BISTTO1_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO1_BISTTO1(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO1_BISTTO1_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO1_BISTTO1_MASK) /*! @} */ /*! @name BISTTO2 - Bist T02 */ /*! @{ */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO2_BISTTO2_MASK (0xFFU) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO2_BISTTO2_SHIFT (0U) #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO2_BISTTO2(x) (((uint32_t)(((uint32_t)(x)) << NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO2_BISTTO2_SHIFT)) & NOC_POWER_RESILIENCEFAULTCONTROLLER_BISTTO2_BISTTO2_MASK) /*! @} */ /*! * @} */ /* end of group NOC_POWER_RESILIENCEFAULTCONTROLLER_Register_Masks */ /* NOC_POWER_RESILIENCEFAULTCONTROLLER - Peripheral instance base addresses */ /** Peripheral WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER base * address */ #define WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER_BASE (0x43900000u) /** Peripheral WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER base * pointer */ #define WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER ((NOC_POWER_RESILIENCEFAULTCONTROLLER_Type *)WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER_BASE) /** Array initializer of NOC_POWER_RESILIENCEFAULTCONTROLLER peripheral base * addresses */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BASE_ADDRS { WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER_BASE } /** Array initializer of NOC_POWER_RESILIENCEFAULTCONTROLLER peripheral base * pointers */ #define NOC_POWER_RESILIENCEFAULTCONTROLLER_BASE_PTRS { WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER } /*! * @} */ /* end of group NOC_POWER_RESILIENCEFAULTCONTROLLER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE1_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE1_MAIN_PROBE_Peripheral_Access_Layer NOC_PROBE1_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_PROBE1_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_PROBE1_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE1_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE1_MAIN_PROBE_Register_Masks NOC_PROBE1_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE1_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE1_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE1_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE1_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE1_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE1_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE1_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE1_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_PROBE1_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_PROBE1_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_PROBE1_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_PROBE1_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_PROBE1_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_PROBE1_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_PROBE1_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_PROBE1_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_PROBE1_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_PROBE1_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_PROBE1_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_PROBE1_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_PROBE1_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_PROBE1_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_PROBE1_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_PROBE1_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_PROBE1_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_PROBE1_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_PROBE1_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_PROBE1_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_PROBE1_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_PROBE1_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_PROBE1_MAIN_PROBE_SRC */ #define NOC_PROBE1_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_PROBE1_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_PROBE1_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_PROBE1_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_PROBE1_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_PROBE1_MAIN_PROBE_VAL */ #define NOC_PROBE1_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_PROBE1_MAIN_PROBE_Register_Masks */ /* NOC_PROBE1_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__PROBE1_MAIN_PROBE base address */ #define DISPLAY__GPV__PROBE1_MAIN_PROBE_BASE (0x4B7E0000u) /** Peripheral DISPLAY__GPV__PROBE1_MAIN_PROBE base pointer */ #define DISPLAY__GPV__PROBE1_MAIN_PROBE ((NOC_PROBE1_MAIN_PROBE_Type *)DISPLAY__GPV__PROBE1_MAIN_PROBE_BASE) /** Array initializer of NOC_PROBE1_MAIN_PROBE peripheral base addresses */ #define NOC_PROBE1_MAIN_PROBE_BASE_ADDRS { DISPLAY__GPV__PROBE1_MAIN_PROBE_BASE } /** Array initializer of NOC_PROBE1_MAIN_PROBE peripheral base pointers */ #define NOC_PROBE1_MAIN_PROBE_BASE_PTRS { DISPLAY__GPV__PROBE1_MAIN_PROBE } /*! * @} */ /* end of group NOC_PROBE1_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE1_MAIN_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE1_MAIN_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE1_MAIN_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE1_MAIN_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[4]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ __IO uint32_t NTENURELINES[3]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ __IO uint32_t TRANSACTIONSTATPROFILER_THRESHOLDS_[4][4]; /**< Transaction Profiler Thresholds, array offset: 0x2C, array step: index*0x10, index2*0x4 */ __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE1_MAIN_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE1_MAIN_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE1_MAIN_XSTATPROFILER_Register_Masks NOC_PROBE1_MAIN_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE1_MAIN_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_MODE_MODE_MASK (0xFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0xFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (4U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0x3FU) #define NOC_PROBE1_MAIN_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_2 */ #define NOC_PROBE1_MAIN_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE1_MAIN_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE1_MAIN_XSTATPROFILER_NTENURELINES_COUNT (3U) /*! @name TRANSACTIONSTATPROFILER_THRESHOLDS_ - Transaction Profiler Thresholds */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK (0x3FFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT (0U) /*! THRESHOLDS - Thresholds 3 3 */ #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK) /*! @} */ /* The count of NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT (4U) /* The count of NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT2 (4U) /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0xFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0xFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE1_MAIN_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE1_MAIN_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE1_MAIN_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE1_MAIN_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE1_MAIN_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE1_MAIN_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE1_MAIN_XSTATPROFILER_Register_Masks */ /* NOC_PROBE1_MAIN_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER base address */ #define DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4B7E1180u) /** Peripheral DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE1_MAIN_XSTATPROFILER_Type *)DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE1_MAIN_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE1_MAIN_XSTATPROFILER_BASE_ADDRS { DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE1_MAIN_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE1_MAIN_XSTATPROFILER_BASE_PTRS { DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE1_MAIN_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_ISI_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_ISI_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_ISI_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_ISI_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[4]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ __IO uint32_t NTENURELINES[3]; /**< NTENURELINES n, array offset: 0x20, array step: 0x4 */ __IO uint32_t TRANSACTIONSTATPROFILER_THRESHOLDS_[4][4]; /**< Transaction Profiler Thresholds, array offset: 0x2C, array step: index*0x10, index2*0x4 */ __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_ISI_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_ISI_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_ISI_XSTATPROFILER_Register_Masks NOC_PROBE_ISI_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_ISI_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_MODE_MODE_MASK (0xFU) #define NOC_PROBE_ISI_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x3U) #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) /*! OBSERVEDSEL - ObservedSel n */ #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (4U) /*! @name NTENURELINES - NTENURELINES n */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_0_MASK (0xFU) #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_0_SHIFT (0U) /*! NTenurelines_0 - Ntenurelines n */ #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_0_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_0_MASK) #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_1_MASK (0xFU) #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_1_SHIFT (0U) /*! NTenurelines_1 - Ntenurelines n */ #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_1_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_1_MASK) #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_2_MASK (0xFU) #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_2_SHIFT (0U) /*! NTenurelines_2 - Ntenurelines n */ #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_2_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_NTenurelines_2_MASK) /*! @} */ /* The count of NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_ISI_XSTATPROFILER_NTENURELINES_COUNT (3U) /*! @name TRANSACTIONSTATPROFILER_THRESHOLDS_ - Transaction Profiler Thresholds */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK (0x7FFU) #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK) /*! @} */ /* The count of NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT (4U) /* The count of NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_PROBE_ISI_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT2 (4U) /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0xFU) #define NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0xFU) #define NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_ISI_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_ISI_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_ISI_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_ISI_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISI_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_ISI_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_ISI_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_ISI_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER base address * */ #define CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4AFF1400u) /** Peripheral CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER base pointer * */ #define CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_ISI_XSTATPROFILER_Type *)CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_ISI_XSTATPROFILER peripheral base addresses */ #define NOC_PROBE_ISI_XSTATPROFILER_BASE_ADDRS { CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_ISI_XSTATPROFILER peripheral base pointers */ #define NOC_PROBE_ISI_XSTATPROFILER_BASE_PTRS { CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_ISI_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_ISP_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_ISP_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_ISP_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_ISP_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[4]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ __IO uint32_t NTENURELINES[3]; /**< NTENURELINES n, array offset: 0x20, array step: 0x4 */ __IO uint32_t TRANSACTIONSTATPROFILER_THRESHOLDS_[4][4]; /**< Transaction Profiler Thresholds, array offset: 0x2C, array step: index*0x10, index2*0x4 */ __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_ISP_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_ISP_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_ISP_XSTATPROFILER_Register_Masks NOC_PROBE_ISP_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_ISP_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_MODE_MODE_MASK (0xFU) #define NOC_PROBE_ISP_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x3U) #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) /*! OBSERVEDSEL - ObservedSel n */ #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (4U) /*! @name NTENURELINES - NTENURELINES n */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_0_MASK (0xFU) #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_0_SHIFT (0U) /*! NTenurelines_0 - Ntenurelines n */ #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_0_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_0_MASK) #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_1_MASK (0xFU) #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_1_SHIFT (0U) /*! NTenurelines_1 - Ntenurelines n */ #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_1_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_1_MASK) #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_2_MASK (0xFU) #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_2_SHIFT (0U) /*! NTenurelines_2 - Ntenurelines n */ #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_2_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_NTenurelines_2_MASK) /*! @} */ /* The count of NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_ISP_XSTATPROFILER_NTENURELINES_COUNT (3U) /*! @name TRANSACTIONSTATPROFILER_THRESHOLDS_ - Transaction Profiler Thresholds */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK (0x7FFU) #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK) /*! @} */ /* The count of NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT (4U) /* The count of NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_PROBE_ISP_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT2 (4U) /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0xFU) #define NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0xFU) #define NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_ISP_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_ISP_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_ISP_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_ISP_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_ISP_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_ISP_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_ISP_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_ISP_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER base address * */ #define CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4AFF1480u) /** Peripheral CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER base pointer * */ #define CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_ISP_XSTATPROFILER_Type *)CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_ISP_XSTATPROFILER peripheral base addresses */ #define NOC_PROBE_ISP_XSTATPROFILER_BASE_ADDRS { CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_ISP_XSTATPROFILER peripheral base pointers */ #define NOC_PROBE_ISP_XSTATPROFILER_BASE_PTRS { CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_ISP_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_MAIN_PROBE_Peripheral_Access_Layer NOC_PROBE_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_PROBE_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ __IO uint32_t TRACEPORTSEL; /**< Trace Port Select, offset: 0x10 */ __IO uint32_t FILTERLUT; /**< Filter Lookup Table, offset: 0x14 */ __IO uint32_t TRACEALARMEN; /**< Trace Alarm Enable, offset: 0x18 */ __I uint32_t TRACEALARMSTATUS; /**< Trace Alarm Status, offset: 0x1C */ __O uint32_t TRACEALARMCLR; /**< Trace Alarm Clear, offset: 0x20 */ __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_0[84]; __IO uint32_t FILTERS_0_ROUTEIDBASE; /**< Filter n Route ID Base, offset: 0x80 */ __IO uint32_t FILTERS_0_ROUTEIDMASK; /**< Filter n Route ID Mask, offset: 0x84 */ __IO uint32_t FILTERS_0_ADDRBASE_LOW; /**< Filter n Addr Base Low, offset: 0x88 */ __IO uint32_t FILTERS_0_ADDRBASE_HIGH; /**< Filter n Addr Base High, offset: 0x8C */ __IO uint32_t FILTERS_0_WINDOWSIZE; /**< Filter n Window Size, offset: 0x90 */ __IO uint32_t FILTERS_0_SECURITYBASE; /**< Filter n Security Base, offset: 0x94 */ __IO uint32_t FILTERS_0_SECURITYMASK; /**< Filter n Security Mask, offset: 0x98 */ __IO uint32_t FILTERS_0_OPCODE; /**< Filter n Packet Probe, offset: 0x9C */ __IO uint32_t FILTERS_0_STATUS; /**< Filter n Status, offset: 0xA0 */ __IO uint32_t FILTERS_0_LENGTH; /**< Filter n Length, offset: 0xA4 */ __IO uint32_t PROBE_MAIN_PROBE_FILTERS_0_URGENCY; /**< offset: 0xA8 */ uint8_t RESERVED_1[52]; __IO uint32_t FILTERS_1_ROUTEIDBASE; /**< Filter n Route ID Base, offset: 0xE0 */ __IO uint32_t FILTERS_1_ROUTEIDMASK; /**< Filter n Route ID Mask, offset: 0xE4 */ __IO uint32_t FILTERS_1_ADDRBASE_LOW; /**< Filter n Addr Base Low, offset: 0xE8 */ __IO uint32_t FILTERS_1_ADDRBASE_HIGH; /**< Filter n Addr Base High, offset: 0xEC */ __IO uint32_t FILTERS_1_WINDOWSIZE; /**< Filter n Window Size, offset: 0xF0 */ __IO uint32_t FILTERS_1_SECURITYBASE; /**< Filter n Security Base, offset: 0xF4 */ __IO uint32_t FILTERS_1_SECURITYMASK; /**< Filter n Security Mask, offset: 0xF8 */ __IO uint32_t FILTERS_1_OPCODE; /**< Filter n Packet Probe, offset: 0xFC */ __IO uint32_t FILTERS_1_STATUS; /**< Filter n Status, offset: 0x100 */ __IO uint32_t FILTERS_1_LENGTH; /**< Filter n Length, offset: 0x104 */ __IO uint32_t PROBE_MAIN_PROBE_FILTERS_1_URGENCY; /**< offset: 0x108 */ uint8_t RESERVED_2[244]; struct { /* offset: 0x200, array step: 0x10 */ __IO uint32_t PORTSEL; /**< Counters n Port Select, array offset: 0x200, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ } COUNTERS[10]; } NOC_PROBE_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_MAIN_PROBE_Register_Masks NOC_PROBE_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_PROBE_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_PROBE_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_PROBE_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_PROBE_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_PROBE_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_PROBE_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_PROBE_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_PROBE_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_PROBE_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_PROBE_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_PROBE_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_PROBE_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name TRACEPORTSEL - Trace Port Select */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SHIFT)) & NOC_PROBE_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_MASK) /*! @} */ /*! @name FILTERLUT - Filter Lookup Table */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERLUT_FILTERLUT_MASK (0xFU) #define NOC_PROBE_MAIN_PROBE_FILTERLUT_FILTERLUT_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_FILTERLUT_FILTERLUT(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERLUT_FILTERLUT_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERLUT_FILTERLUT_MASK) /*! @} */ /*! @name TRACEALARMEN - Trace Alarm Enable */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MASK (0x7U) #define NOC_PROBE_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MASK) /*! @} */ /*! @name TRACEALARMSTATUS - Trace Alarm Status */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MASK (0x7U) #define NOC_PROBE_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SHIFT)) & NOC_PROBE_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MASK) /*! @} */ /*! @name TRACEALARMCLR - Trace Alarm Clear */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MASK (0x7U) #define NOC_PROBE_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SHIFT)) & NOC_PROBE_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_PROBE_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_PROBE_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_PROBE_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name FILTERS_0_ROUTEIDBASE - Filter n Route ID Base */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK (0xFFFFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT (0U) /*! FILTERS_ROUTEIDBASE - Filter n Route ID Base */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_ROUTEIDBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK) /*! @} */ /*! @name FILTERS_0_ROUTEIDMASK - Filter n Route ID Mask */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK (0xFFFFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT (0U) /*! FILTERS_ROUTEIDMASK - Filter n Route ID Mask */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_ROUTEIDMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK) /*! @} */ /*! @name FILTERS_0_ADDRBASE_LOW - Filter n Addr Base Low */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT (0U) /*! FILTERS_ADDRBASE_LOW - Address LSB register */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK) /*! @} */ /*! @name FILTERS_0_ADDRBASE_HIGH - Filter n Addr Base High */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT (0U) /*! FILTERS_ADDRBASE_HIGH - Address MSB register */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name FILTERS_0_WINDOWSIZE - Filter n Window Size */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK (0x3FU) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT (0U) /*! FILTERS_WINDOWSIZE - Window Size */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_WINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK) /*! @} */ /*! @name FILTERS_0_SECURITYBASE - Filter n Security Base */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_SECURITYBASE_MASK (0x7U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_SECURITYBASE_SHIFT (0U) /*! FILTERS_SECURITYBASE - Security Base */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_SECURITYBASE_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYBASE_FILTERS_SECURITYBASE_MASK) /*! @} */ /*! @name FILTERS_0_SECURITYMASK - Filter n Security Mask */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_MASK (0x7U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SHIFT (0U) /*! FILTERS_0_SECURITYMASK - Security Mask */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_SECURITYMASK_FILTERS_0_SECURITYMASK_MASK) /*! @} */ /*! @name FILTERS_0_OPCODE - Filter n Packet Probe */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_RDEN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_WREN_MASK (0x2U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SHIFT (1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_WREN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_WREN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_MASK (0x4U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SHIFT (2U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_LOCKEN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_MASK (0x8U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SHIFT (3U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_URGEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_OPCODE_URGEN_MASK) /*! @} */ /*! @name FILTERS_0_STATUS - Filter n Status */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_REQEN_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_REQEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_REQEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_REQEN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_MASK (0x2U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SHIFT (1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_RSPEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_STATUS_RSPEN_MASK) /*! @} */ /*! @name FILTERS_0_LENGTH - Filter n Length */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_MASK (0xFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SHIFT (0U) /*! FILTERS_0_LENGTH - Length */ #define NOC_PROBE_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_0_LENGTH_FILTERS_0_LENGTH_MASK) /*! @} */ /*! @name PROBE_MAIN_PROBE_FILTERS_0_URGENCY - */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_MASK (0x3U) #define NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_SHIFT)) & NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_0_URGENCY_FILTERS_0_URGENCY_MASK) /*! @} */ /*! @name FILTERS_1_ROUTEIDBASE - Filter n Route ID Base */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK (0xFFFFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT (0U) /*! FILTERS_ROUTEIDBASE - Filter n Route ID Base */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_ROUTEIDBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK) /*! @} */ /*! @name FILTERS_1_ROUTEIDMASK - Filter n Route ID Mask */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK (0xFFFFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT (0U) /*! FILTERS_ROUTEIDMASK - Filter n Route ID Mask */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_ROUTEIDMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK) /*! @} */ /*! @name FILTERS_1_ADDRBASE_LOW - Filter n Addr Base Low */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT (0U) /*! FILTERS_ADDRBASE_LOW - Address LSB register */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK) /*! @} */ /*! @name FILTERS_1_ADDRBASE_HIGH - Filter n Addr Base High */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT (0U) /*! FILTERS_ADDRBASE_HIGH - Address MSB register */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name FILTERS_1_WINDOWSIZE - Filter n Window Size */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK (0x3FU) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT (0U) /*! FILTERS_WINDOWSIZE - Window Size */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_WINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK) /*! @} */ /*! @name FILTERS_1_SECURITYBASE - Filter n Security Base */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_SECURITYBASE_MASK (0x7U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_SECURITYBASE_SHIFT (0U) /*! FILTERS_SECURITYBASE - Security Base */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_SECURITYBASE_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYBASE_FILTERS_SECURITYBASE_MASK) /*! @} */ /*! @name FILTERS_1_SECURITYMASK - Filter n Security Mask */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_MASK (0x7U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SHIFT (0U) /*! FILTERS_1_SECURITYMASK - Security Mask */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_SECURITYMASK_FILTERS_1_SECURITYMASK_MASK) /*! @} */ /*! @name FILTERS_1_OPCODE - Filter n Packet Probe */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_RDEN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_WREN_MASK (0x2U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SHIFT (1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_WREN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_WREN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_MASK (0x4U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SHIFT (2U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_LOCKEN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_MASK (0x8U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SHIFT (3U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_URGEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_OPCODE_URGEN_MASK) /*! @} */ /*! @name FILTERS_1_STATUS - Filter n Status */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_REQEN_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_REQEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_REQEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_REQEN_MASK) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_MASK (0x2U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SHIFT (1U) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_RSPEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_STATUS_RSPEN_MASK) /*! @} */ /*! @name FILTERS_1_LENGTH - Filter n Length */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_MASK (0xFU) #define NOC_PROBE_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SHIFT (0U) /*! FILTERS_1_LENGTH - Length */ #define NOC_PROBE_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_SHIFT)) & NOC_PROBE_MAIN_PROBE_FILTERS_1_LENGTH_FILTERS_1_LENGTH_MASK) /*! @} */ /*! @name PROBE_MAIN_PROBE_FILTERS_1_URGENCY - */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_MASK (0x3U) #define NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SHIFT (0U) #define NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_SHIFT)) & NOC_PROBE_MAIN_PROBE_PROBE_MAIN_PROBE_FILTERS_1_URGENCY_FILTERS_1_URGENCY_MASK) /*! @} */ /*! @name PORTSEL - Counters n Port Select */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_MASK (0x1U) #define NOC_PROBE_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_SHIFT (0U) /*! COUNTERS_PORTSEL - Port Select */ #define NOC_PROBE_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_SHIFT)) & NOC_PROBE_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_MASK) /*! @} */ /* The count of NOC_PROBE_MAIN_PROBE_PORTSEL */ #define NOC_PROBE_MAIN_PROBE_PORTSEL_COUNT (10U) /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_PROBE_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_PROBE_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_PROBE_MAIN_PROBE_SRC_INTEVENT_MASK) /*! @} */ /* The count of NOC_PROBE_MAIN_PROBE_SRC */ #define NOC_PROBE_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_PROBE_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_PROBE_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_PROBE_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_PROBE_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_PROBE_MAIN_PROBE_VAL */ #define NOC_PROBE_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_PROBE_MAIN_PROBE_Register_Masks */ /* NOC_PROBE_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__PROBE_MAIN_PROBE base address */ #define DISPLAY__GPV__PROBE_MAIN_PROBE_BASE (0x4B7E0400u) /** Peripheral DISPLAY__GPV__PROBE_MAIN_PROBE base pointer */ #define DISPLAY__GPV__PROBE_MAIN_PROBE ((NOC_PROBE_MAIN_PROBE_Type *)DISPLAY__GPV__PROBE_MAIN_PROBE_BASE) /** Array initializer of NOC_PROBE_MAIN_PROBE peripheral base addresses */ #define NOC_PROBE_MAIN_PROBE_BASE_ADDRS { DISPLAY__GPV__PROBE_MAIN_PROBE_BASE } /** Array initializer of NOC_PROBE_MAIN_PROBE peripheral base pointers */ #define NOC_PROBE_MAIN_PROBE_BASE_PTRS { DISPLAY__GPV__PROBE_MAIN_PROBE } /*! * @} */ /* end of group NOC_PROBE_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_0_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_0_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_0_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_0_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_0_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_0_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_0_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_0_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_0_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_0_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_0_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_0_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_0_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0xFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_0_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_0_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_0_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_0_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_0_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_0_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_0_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_0_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_0_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_0_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER base address */ #define NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063980u) /** Peripheral NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_0_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_0_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE_M_E_0_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_0_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_0_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_0_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_10_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_10_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_10_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_10_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_10_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_10_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_10_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_10_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_10_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_10_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_10_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_10_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_10_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0xFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_10_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_10_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_10_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_10_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_10_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_10_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_10_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_10_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_10_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_10_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER base address * */ #define NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063D00u) /** Peripheral NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER base pointer * */ #define NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_10_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_10_XSTATPROFILER peripheral base * addresses */ #define NOC_PROBE_M_E_10_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_10_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_10_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_10_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_11_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_11_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_11_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_11_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_11_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_11_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_11_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_11_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_11_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_11_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_11_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_11_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_11_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0x7U) #define NOC_PROBE_M_E_11_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_11_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_11_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_11_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_11_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_11_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_11_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_11_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_11_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_11_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_11_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER base address * */ #define NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063D80u) /** Peripheral NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER base pointer * */ #define NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_11_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_11_XSTATPROFILER peripheral base * addresses */ #define NOC_PROBE_M_E_11_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_11_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_11_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_11_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_3_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_3_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_3_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_3_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_3_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_3_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_3_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_3_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_3_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_3_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_3_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_3_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_3_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0xFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_3_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_3_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_3_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_3_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_3_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_3_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_3_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_3_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_3_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_3_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER base address */ #define NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063A00u) /** Peripheral NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_3_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_3_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE_M_E_3_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_3_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_3_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_3_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_4_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_4_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_4_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_4_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_4_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_4_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_4_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_4_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_4_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_4_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_4_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_4_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_4_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0xFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_4_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_4_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_4_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_4_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_4_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_4_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_4_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_4_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_4_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_4_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER base address */ #define NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063A80u) /** Peripheral NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_4_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_4_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE_M_E_4_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_4_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_4_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_4_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_5_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_5_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_5_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_5_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_5_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_5_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_5_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_5_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_5_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_5_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_5_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_5_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_5_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0xFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_5_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_5_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_5_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_5_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_5_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_5_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_5_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_5_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_5_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_5_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER base address */ #define NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063B00u) /** Peripheral NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_5_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_5_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE_M_E_5_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_5_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_5_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_5_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_6_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_6_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_6_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_6_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ uint8_t RESERVED_0[28]; __IO uint32_t PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ uint8_t RESERVED_1[48]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_6_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_6_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_6_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_6_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_6_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_MODE_MODE_MASK (0x1U) #define NOC_PROBE_M_E_6_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x1U) #define NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x1U) #define NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_6_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_6_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_6_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_6_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_6_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_6_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_6_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_6_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER base address */ #define NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063B80u) /** Peripheral NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_6_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_6_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE_M_E_6_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_6_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_6_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_6_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_7_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_7_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_7_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_7_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_7_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_7_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_7_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_7_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_7_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_7_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_7_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_7_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_7_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0x7U) #define NOC_PROBE_M_E_7_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_7_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_7_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_7_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_7_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_7_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_7_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_7_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_7_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_7_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_7_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER base address */ #define NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063C00u) /** Peripheral NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_7_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_7_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE_M_E_7_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_7_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_7_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_7_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_9_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_9_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_M_E_9_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_M_E_9_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES[1]; /**< NTenureLines n, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1; /**< offset: 0x30 */ __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2; /**< offset: 0x34 */ __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3; /**< offset: 0x38 */ __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1; /**< offset: 0x40 */ __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2; /**< offset: 0x44 */ __IO uint32_t PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3; /**< offset: 0x48 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_PROBE_M_E_9_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_M_E_9_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_M_E_9_XSTATPROFILER_Register_Masks NOC_PROBE_M_E_9_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_M_E_9_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_PROBE_M_E_9_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_PROBE_M_E_9_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_9_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_PROBE_M_E_9_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES - NTenureLines n */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK (0x7U) #define NOC_PROBE_M_E_9_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT (0U) /*! NTENURELINES_n - NTenureLines_0 */ #define NOC_PROBE_M_E_9_XSTATPROFILER_NTENURELINES_NTENURELINES_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_NTENURELINES_NTENURELINES_n_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_NTENURELINES_NTENURELINES_n_MASK) /*! @} */ /* The count of NOC_PROBE_M_E_9_XSTATPROFILER_NTENURELINES */ #define NOC_PROBE_M_E_9_XSTATPROFILER_NTENURELINES_COUNT (1U) /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MASK) /*! @} */ /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MASK) /*! @} */ /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_3_THRESHOLDS_0_3_MASK) /*! @} */ /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_1_THRESHOLDS_1_1_MASK) /*! @} */ /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_2_THRESHOLDS_1_2_MASK) /*! @} */ /*! @name PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3 - */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK (0x3FFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_3_THRESHOLDS_1_3_MASK) /*! @} */ /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_PROBE_M_E_9_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_M_E_9_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_M_E_9_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_M_E_9_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_M_E_9_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_M_E_9_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_M_E_9_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER base address */ #define NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063C80u) /** Peripheral NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_M_E_9_XSTATPROFILER_Type *)NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_M_E_9_XSTATPROFILER peripheral base addresses * */ #define NOC_PROBE_M_E_9_XSTATPROFILER_BASE_ADDRS { NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_M_E_9_XSTATPROFILER peripheral base pointers * */ #define NOC_PROBE_M_E_9_XSTATPROFILER_BASE_PTRS { NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_M_E_9_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_PROBE_TRANSACTION_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_TRANSACTION_XSTATPROFILER_Peripheral_Access_Layer NOC_PROBE_TRANSACTION_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_PROBE_TRANSACTION_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_EN; /**< offset: 0x8 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_MODE; /**< offset: 0xC */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0; /**< offset: 0x10 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1; /**< offset: 0x14 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_2; /**< offset: 0x18 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_3; /**< offset: 0x1C */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0; /**< offset: 0x20 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_1; /**< offset: 0x24 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_2; /**< offset: 0x28 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0; /**< offset: 0x2C */ uint8_t RESERVED_0[12]; __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0; /**< offset: 0x3C */ uint8_t RESERVED_1[12]; __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_2_0; /**< offset: 0x4C */ uint8_t RESERVED_2[12]; __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_3_0; /**< offset: 0x5C */ uint8_t RESERVED_3[12]; __I uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS; /**< offset: 0x6C */ __O uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET; /**< offset: 0x70 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE; /**< offset: 0x74 */ __IO uint32_t PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PRESCALER; /**< offset: 0x78 */ } NOC_PROBE_TRANSACTION_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_PROBE_TRANSACTION_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_PROBE_TRANSACTION_XSTATPROFILER_Register_Masks NOC_PROBE_TRANSACTION_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_EN - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_EN_EN_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_MODE - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_MODE_MODE_MASK (0xFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_MODE_MODE_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0_OBSERVEDSEL_0_MASK (0x7U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0_OBSERVEDSEL_0_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0_OBSERVEDSEL_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0_OBSERVEDSEL_0_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_0_OBSERVEDSEL_0_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1_OBSERVEDSEL_1_MASK (0x7U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1_OBSERVEDSEL_1_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1_OBSERVEDSEL_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1_OBSERVEDSEL_1_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_1_OBSERVEDSEL_1_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_2 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_2_OBSERVEDSEL_2_MASK (0x7U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_2_OBSERVEDSEL_2_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_2_OBSERVEDSEL_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_2_OBSERVEDSEL_2_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_2_OBSERVEDSEL_2_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_3 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_3_OBSERVEDSEL_3_MASK (0x7U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_3_OBSERVEDSEL_3_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_3_OBSERVEDSEL_3(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_3_OBSERVEDSEL_3_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OBSERVEDSEL_3_OBSERVEDSEL_3_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK (0x7U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0_NTENURELINES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_1 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_1_NTENURELINES_1_MASK (0x7U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_1_NTENURELINES_1_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_1_NTENURELINES_1(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_1_NTENURELINES_1_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_1_NTENURELINES_1_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_2 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_2_NTENURELINES_2_MASK (0x7U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_2_NTENURELINES_2_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_2_NTENURELINES_2(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_2_NTENURELINES_2_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_NTENURELINES_2_NTENURELINES_2_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK (0xFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK (0xFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_1_0_THRESHOLDS_1_0_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_2_0 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_2_0_THRESHOLDS_2_0_MASK (0xFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_2_0_THRESHOLDS_2_0_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_2_0_THRESHOLDS_2_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_2_0_THRESHOLDS_2_0_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_2_0_THRESHOLDS_2_0_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_3_0 - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_3_0_THRESHOLDS_3_0_MASK (0xFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_3_0_THRESHOLDS_3_0_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_3_0_THRESHOLDS_3_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_3_0_THRESHOLDS_3_0_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_THRESHOLDS_3_0_THRESHOLDS_3_0_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0xFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0xFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PRESCALER - */ /*! @{ */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_PROBE_TRANSACTION_XSTATPROFILER_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_PROBE_TRANSACTION_XSTATPROFILER_Register_Masks */ /* NOC_PROBE_TRANSACTION_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_BASE (0x980C0280u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER ((NOC_PROBE_TRANSACTION_XSTATPROFILER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_PROBE_TRANSACTION_XSTATPROFILER peripheral base * addresses */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_PROBE_TRANSACTION_XSTATPROFILER peripheral base * pointers */ #define NOC_PROBE_TRANSACTION_XSTATPROFILER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_PROBE_TRANSACTION_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_RD_TRANSACTION_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_RD_TRANSACTION_PROBE_Peripheral_Access_Layer NOC_RD_TRANSACTION_PROBE Peripheral Access Layer * @{ */ /** NOC_RD_TRANSACTION_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PROBE_TRANSACTION_MAIN_PROBE_MAINCTL; /**< offset: 0x8 */ __IO uint32_t PROBE_TRANSACTION_MAIN_PROBE_CFGCTL; /**< offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t PROBE_TRANSACTION_MAIN_PROBE_STATPERIOD; /**< offset: 0x24 */ __O uint32_t PROBE_TRANSACTION_MAIN_PROBE_STATGO; /**< offset: 0x28 */ uint8_t RESERVED_1[472]; __IO uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC; /**< offset: 0x204 */ uint8_t RESERVED_2[4]; __I uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_VAL; /**< offset: 0x20C */ uint8_t RESERVED_3[4]; __IO uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC; /**< offset: 0x214 */ uint8_t RESERVED_4[4]; __I uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_VAL; /**< offset: 0x21C */ uint8_t RESERVED_5[4]; __IO uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC; /**< offset: 0x224 */ uint8_t RESERVED_6[4]; __I uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_VAL; /**< offset: 0x22C */ uint8_t RESERVED_7[4]; __IO uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC; /**< offset: 0x234 */ uint8_t RESERVED_8[4]; __I uint32_t PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_VAL; /**< offset: 0x23C */ } NOC_RD_TRANSACTION_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_RD_TRANSACTION_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_RD_TRANSACTION_PROBE_Register_Masks NOC_RD_TRANSACTION_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_RD_TRANSACTION_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_RD_TRANSACTION_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_RD_TRANSACTION_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_RD_TRANSACTION_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_RD_TRANSACTION_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_RD_TRANSACTION_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_RD_TRANSACTION_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_MAINCTL - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_CFGCTL - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_STATPERIOD - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_STATGO - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_MASK (0x1FU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_INTEVENT_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_EXTEVENT_MASK (0x20U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_EXTEVENT_SHIFT (5U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_EXTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_SRC_EXTEVENT_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_VAL - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_MASK (0xFFFFFFFFU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_0_VAL_COUNTERS_0_VAL_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_MASK (0x1FU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_INTEVENT_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_EXTEVENT_MASK (0x20U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_EXTEVENT_SHIFT (5U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_EXTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_SRC_EXTEVENT_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_VAL - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_MASK (0xFFFFFFFFU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_1_VAL_COUNTERS_1_VAL_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_MASK (0x1FU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_INTEVENT_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_EXTEVENT_MASK (0x20U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_EXTEVENT_SHIFT (5U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_EXTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_SRC_EXTEVENT_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_VAL - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_MASK (0xFFFFFFFFU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_2_VAL_COUNTERS_2_VAL_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_MASK (0x1FU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_INTEVENT_MASK) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_EXTEVENT_MASK (0x20U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_EXTEVENT_SHIFT (5U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_EXTEVENT_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_SRC_EXTEVENT_MASK) /*! @} */ /*! @name PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_VAL - */ /*! @{ */ #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_MASK (0xFFFFFFFFU) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_SHIFT (0U) #define NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_SHIFT)) & NOC_RD_TRANSACTION_PROBE_PROBE_TRANSACTION_MAIN_PROBE_COUNTERS_3_VAL_COUNTERS_3_VAL_MASK) /*! @} */ /*! * @} */ /* end of group NOC_RD_TRANSACTION_PROBE_Register_Masks */ /* NOC_RD_TRANSACTION_PROBE - Peripheral instance base addresses */ /** Peripheral HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE base * address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE_BASE (0x980C0800u) /** Peripheral HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE base * pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE ((NOC_RD_TRANSACTION_PROBE_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE_BASE) /** Array initializer of NOC_RD_TRANSACTION_PROBE peripheral base addresses */ #define NOC_RD_TRANSACTION_PROBE_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE_BASE } /** Array initializer of NOC_RD_TRANSACTION_PROBE peripheral base pointers */ #define NOC_RD_TRANSACTION_PROBE_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE } /*! * @} */ /* end of group NOC_RD_TRANSACTION_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_Register_Masks NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P0_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P0_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P0_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P0_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P1_MASK (0x300U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P1_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P1_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_MODE_MODE_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_SATURATION_SATURATION_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_SATURATION_SATURATION_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTTHREN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_INTCLKEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR * base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR_BASE (0x4B7E0800u) /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR * base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR ((NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_0_QOS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_Register_Masks NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0A00u) /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_0_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_Register_Masks NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P0_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P0_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P0_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P0_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P1_MASK (0x300U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P1_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P1_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_MODE_MODE_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_SATURATION_SATURATION_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_SATURATION_SATURATION_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTTHREN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_INTCLKEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR * base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR_BASE (0x4B7E0880u) /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR * base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR ((NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_1_QOS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_Register_Masks NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0A80u) /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_1_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_Register_Masks NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P0_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P0_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P0_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P0_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P1_MASK (0x300U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P1_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P1_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_MODE_MODE_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_SATURATION_SATURATION_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_SATURATION_SATURATION_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTTHREN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_INTCLKEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR * base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR_BASE (0x4B7E0900u) /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR * base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR ((NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_2_QOS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_Register_Masks NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0B00u) /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_FU_RD_2_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_STORE_WR_QOS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_STORE_WR_QOS Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_STORE_WR_QOS - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_STORE_WR_QOS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_Register_Masks NOC_SEERIS_2D_BLITTER_STORE_WR_QOS Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P0_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P0_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P0_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P0_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P1_MASK (0x300U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P1_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P1_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_MODE_MODE_MASK (0x3U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_BANDWIDTH_BANDWIDTH_MASK (0xFFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_SATURATION_SATURATION_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_SATURATION_SATURATION_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTTHREN_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_INTCLKEN_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_STORE_WR_QOS - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR * base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR_BASE (0x4B7E0980u) /** Peripheral DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR * base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR ((NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_STORE_WR_QOS peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_STORE_WR_QOS peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_STORE_WR_QOS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_Peripheral_Access_Layer NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_Register_Masks NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_Register_Masks */ /* NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0B80u) /** Peripheral * DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT peripheral base * addresses */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT peripheral base * pointers */ #define NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_2D_BLITTER_STORE_WR_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_CMD_SEQ_RD_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_CMD_SEQ_RD_XSTAT_Peripheral_Access_Layer NOC_SEERIS_CMD_SEQ_RD_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_CMD_SEQ_RD_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_CMD_SEQ_RD_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_CMD_SEQ_RD_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_CMD_SEQ_RD_XSTAT_Register_Masks NOC_SEERIS_CMD_SEQ_RD_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_CMD_SEQ_RD_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_CMD_SEQ_RD_XSTAT_Register_Masks */ /* NOC_SEERIS_CMD_SEQ_RD_XSTAT - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER * base address */ #define DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0C00u) /** Peripheral DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER * base pointer */ #define DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_CMD_SEQ_RD_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_CMD_SEQ_RD_XSTAT peripheral base addresses */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_CMD_SEQ_RD_XSTAT peripheral base pointers */ #define NOC_SEERIS_CMD_SEQ_RD_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_CMD_SEQ_RD_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_CMD_SEQ_WR_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_CMD_SEQ_WR_XSTAT_Peripheral_Access_Layer NOC_SEERIS_CMD_SEQ_WR_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_CMD_SEQ_WR_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_CMD_SEQ_WR_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_CMD_SEQ_WR_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_CMD_SEQ_WR_XSTAT_Register_Masks NOC_SEERIS_CMD_SEQ_WR_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_CMD_SEQ_WR_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_CMD_SEQ_WR_XSTAT_Register_Masks */ /* NOC_SEERIS_CMD_SEQ_WR_XSTAT - Peripheral instance base addresses */ /** Peripheral DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER * base address */ #define DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0C80u) /** Peripheral DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER * base pointer */ #define DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_CMD_SEQ_WR_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_CMD_SEQ_WR_XSTAT peripheral base addresses */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_CMD_SEQ_WR_XSTAT peripheral base pointers */ #define NOC_SEERIS_CMD_SEQ_WR_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_CMD_SEQ_WR_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0D00u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_0_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0D80u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_1_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0E00u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_2_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0E80u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_3_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0F00u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_4_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0F80u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_5_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1000u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_6_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1080u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_7_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_Peripheral_Access_Layer NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT Peripheral Access Layer * @{ */ /** NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_Type; /* ---------------------------------------------------------------------------- -- NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_Register_Masks NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORETYPEID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORETYPEID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_USERID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_USERID_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_NOCID_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_MODE_MODE_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_MODE_MODE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_MODE_MODE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_RDEN_MASK (0x1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_RDEN_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_RDEN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_RDEN_MASK) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_WREN_MASK (0x2U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_WREN_SHIFT (1U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_WREN_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERBASE_USERBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERBASE_USERBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERMASK_USERMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERMASK_USERMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_Register_Masks */ /* NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT - Peripheral instance base addresses */ /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER base address */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1100u) /** Peripheral * DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER ((NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_Type *)DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT peripheral base * addresses */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_BASE_ADDRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT peripheral base * pointers */ #define NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_BASE_PTRS { DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_SEERIS_DISPLAY_CTRL_RD_8_XSTAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SRAMCTL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SRAMCTL_Peripheral_Access_Layer NOC_SRAMCTL Peripheral Access Layer * @{ */ /** NOC_SRAMCTL - Register Layout Typedef */ typedef struct { __IO uint32_t RAMCR; /**< RAM Control, offset: 0x0 */ __IO uint32_t RAMIAS; /**< RAM Initialization Address Start, offset: 0x4 */ __IO uint32_t RAMIAE; /**< RAM Initialization Address End, offset: 0x8 */ __IO uint32_t RAMSR; /**< RAM Status, offset: 0xC */ __I uint32_t RAMMEMA; /**< RAM ECC Address, offset: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t RAMSYSA; /**< RAM System Address, offset: 0x18 */ __IO uint32_t RAMECCNT; /**< RAM Correctable Error Count, offset: 0x1C */ __IO uint32_t RAMEID0; /**< RAM Error Injection Data 0, offset: 0x20 */ __IO uint32_t RAMEID1; /**< RAM Error Injection Data 1, offset: 0x24 */ __IO uint32_t RAMEIDC; /**< RAM Error Injection Data Control, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t RAMEIA; /**< RAM Error Injection Base Address, offset: 0x30 */ __IO uint32_t RAMEIAM; /**< RAM Error Injection Address Mask, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t RAMMAXA; /**< RAM Maximum-Value Address, offset: 0x40 */ uint8_t RESERVED_3[60]; __IO uint32_t RAMCR2; /**< RAM Control 2, offset: 0x80 */ } NOC_SRAMCTL_Type; /* ---------------------------------------------------------------------------- -- NOC_SRAMCTL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SRAMCTL_Register_Masks NOC_SRAMCTL Register Masks * @{ */ /*! @name RAMCR - RAM Control */ /*! @{ */ #define NOC_SRAMCTL_RAMCR_INIT_MASK (0x1U) #define NOC_SRAMCTL_RAMCR_INIT_SHIFT (0U) /*! INIT - Initialization Request * 0b0..Not requested * 0b1..Requested */ #define NOC_SRAMCTL_RAMCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMCR_INIT_SHIFT)) & NOC_SRAMCTL_RAMCR_INIT_MASK) #define NOC_SRAMCTL_RAMCR_IWS_MASK (0x6U) #define NOC_SRAMCTL_RAMCR_IWS_SHIFT (1U) /*! IWS - Initialization Wait States * 0b00..Zero * 0b01..One * 0b10..Two * 0b11..Three */ #define NOC_SRAMCTL_RAMCR_IWS(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMCR_IWS_SHIFT)) & NOC_SRAMCTL_RAMCR_IWS_MASK) #define NOC_SRAMCTL_RAMCR_INIT_SYSA_MASK (0x100U) #define NOC_SRAMCTL_RAMCR_INIT_SYSA_SHIFT (8U) /*! INIT_SYSA - Initialize With System Address * 0b0..Local * 0b1..System */ #define NOC_SRAMCTL_RAMCR_INIT_SYSA(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMCR_INIT_SYSA_SHIFT)) & NOC_SRAMCTL_RAMCR_INIT_SYSA_MASK) /*! @} */ /*! @name RAMIAS - RAM Initialization Address Start */ /*! @{ */ #define NOC_SRAMCTL_RAMIAS_IAS_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMIAS_IAS_SHIFT (0U) /*! IAS - Initialization Address Start */ #define NOC_SRAMCTL_RAMIAS_IAS(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMIAS_IAS_SHIFT)) & NOC_SRAMCTL_RAMIAS_IAS_MASK) /*! @} */ /*! @name RAMIAE - RAM Initialization Address End */ /*! @{ */ #define NOC_SRAMCTL_RAMIAE_IAE_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMIAE_IAE_SHIFT (0U) /*! IAE - Initialization Address End */ #define NOC_SRAMCTL_RAMIAE_IAE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMIAE_IAE_SHIFT)) & NOC_SRAMCTL_RAMIAE_IAE_MASK) /*! @} */ /*! @name RAMSR - RAM Status */ /*! @{ */ #define NOC_SRAMCTL_RAMSR_IDONE_MASK (0x1U) #define NOC_SRAMCTL_RAMSR_IDONE_SHIFT (0U) /*! IDONE - Initialization Done * 0b0..An initialization was not requested, is in progress, or did not complete * 0b1..An initialization completed successfully */ #define NOC_SRAMCTL_RAMSR_IDONE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_IDONE_SHIFT)) & NOC_SRAMCTL_RAMSR_IDONE_MASK) #define NOC_SRAMCTL_RAMSR_BUSERR_MASK (0x2U) #define NOC_SRAMCTL_RAMSR_BUSERR_SHIFT (1U) /*! BUSERR - Bus Error * 0b0..No error occurred since the last time this field was cleared * 0b1..An error occurred */ #define NOC_SRAMCTL_RAMSR_BUSERR(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_BUSERR_SHIFT)) & NOC_SRAMCTL_RAMSR_BUSERR_MASK) #define NOC_SRAMCTL_RAMSR_IPEND_MASK (0x4U) #define NOC_SRAMCTL_RAMSR_IPEND_SHIFT (2U) /*! IPEND - Initialization Pending * 0b0..Not in progress * 0b1..In progress */ #define NOC_SRAMCTL_RAMSR_IPEND(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_IPEND_SHIFT)) & NOC_SRAMCTL_RAMSR_IPEND_MASK) #define NOC_SRAMCTL_RAMSR_AVALID_MASK (0x8U) #define NOC_SRAMCTL_RAMSR_AVALID_SHIFT (3U) /*! AVALID - Addresses Valid * 0b0..Addresses do not correspond to an event * 0b1..Addresses correspond to an event */ #define NOC_SRAMCTL_RAMSR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_AVALID_SHIFT)) & NOC_SRAMCTL_RAMSR_AVALID_MASK) #define NOC_SRAMCTL_RAMSR_AERR_MASK (0x20U) #define NOC_SRAMCTL_RAMSR_AERR_SHIFT (5U) /*! AERR - ECC Address Error * 0b0..No error occurred * 0b1..An error occurred */ #define NOC_SRAMCTL_RAMSR_AERR(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_AERR_SHIFT)) & NOC_SRAMCTL_RAMSR_AERR_MASK) #define NOC_SRAMCTL_RAMSR_MLTERR_MASK (0x40U) #define NOC_SRAMCTL_RAMSR_MLTERR_SHIFT (6U) /*! MLTERR - ECC Multi-Bit Error * 0b0..No error occurred * 0b1..An error occurred */ #define NOC_SRAMCTL_RAMSR_MLTERR(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_MLTERR_SHIFT)) & NOC_SRAMCTL_RAMSR_MLTERR_MASK) #define NOC_SRAMCTL_RAMSR_SGLERR_MASK (0x80U) #define NOC_SRAMCTL_RAMSR_SGLERR_SHIFT (7U) /*! SGLERR - ECC Single-Bit Error * 0b0..No error occurred * 0b1..An error occurred */ #define NOC_SRAMCTL_RAMSR_SGLERR(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_SGLERR_SHIFT)) & NOC_SRAMCTL_RAMSR_SGLERR_MASK) #define NOC_SRAMCTL_RAMSR_SYND_MASK (0xFF00U) #define NOC_SRAMCTL_RAMSR_SYND_SHIFT (8U) /*! SYND - ECC Syndrome Value */ #define NOC_SRAMCTL_RAMSR_SYND(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_SYND_SHIFT)) & NOC_SRAMCTL_RAMSR_SYND_MASK) #define NOC_SRAMCTL_RAMSR_EINFO_MASK (0xFF0000U) #define NOC_SRAMCTL_RAMSR_EINFO_SHIFT (16U) /*! EINFO - Event Information */ #define NOC_SRAMCTL_RAMSR_EINFO(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSR_EINFO_SHIFT)) & NOC_SRAMCTL_RAMSR_EINFO_MASK) /*! @} */ /*! @name RAMMEMA - RAM ECC Address */ /*! @{ */ #define NOC_SRAMCTL_RAMMEMA_MEMA_MASK (0x1FFFFU) #define NOC_SRAMCTL_RAMMEMA_MEMA_SHIFT (0U) /*! MEMA - RAM Bank Address */ #define NOC_SRAMCTL_RAMMEMA_MEMA(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMMEMA_MEMA_SHIFT)) & NOC_SRAMCTL_RAMMEMA_MEMA_MASK) #define NOC_SRAMCTL_RAMMEMA_BANK_MASK (0x1F00000U) #define NOC_SRAMCTL_RAMMEMA_BANK_SHIFT (20U) /*! BANK - RAM Bank ID */ #define NOC_SRAMCTL_RAMMEMA_BANK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMMEMA_BANK_SHIFT)) & NOC_SRAMCTL_RAMMEMA_BANK_MASK) /*! @} */ /*! @name RAMSYSA - RAM System Address */ /*! @{ */ #define NOC_SRAMCTL_RAMSYSA_SYSA_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMSYSA_SYSA_SHIFT (0U) /*! SYSA - System Address */ #define NOC_SRAMCTL_RAMSYSA_SYSA(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMSYSA_SYSA_SHIFT)) & NOC_SRAMCTL_RAMSYSA_SYSA_MASK) /*! @} */ /*! @name RAMECCNT - RAM Correctable Error Count */ /*! @{ */ #define NOC_SRAMCTL_RAMECCNT_ECCNT_MASK (0xFFU) #define NOC_SRAMCTL_RAMECCNT_ECCNT_SHIFT (0U) /*! ECCNT - ECC Correctable Error Count */ #define NOC_SRAMCTL_RAMECCNT_ECCNT(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMECCNT_ECCNT_SHIFT)) & NOC_SRAMCTL_RAMECCNT_ECCNT_MASK) /*! @} */ /*! @name RAMEID0 - RAM Error Injection Data 0 */ /*! @{ */ #define NOC_SRAMCTL_RAMEID0_EID_W0_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMEID0_EID_W0_SHIFT (0U) /*! EID_W0 - Error Injection Data Word 0 */ #define NOC_SRAMCTL_RAMEID0_EID_W0(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEID0_EID_W0_SHIFT)) & NOC_SRAMCTL_RAMEID0_EID_W0_MASK) /*! @} */ /*! @name RAMEID1 - RAM Error Injection Data 1 */ /*! @{ */ #define NOC_SRAMCTL_RAMEID1_EID_W1_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMEID1_EID_W1_SHIFT (0U) /*! EID_W1 - Error Injection Data Word 1 */ #define NOC_SRAMCTL_RAMEID1_EID_W1(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEID1_EID_W1_SHIFT)) & NOC_SRAMCTL_RAMEID1_EID_W1_MASK) /*! @} */ /*! @name RAMEIDC - RAM Error Injection Data Control */ /*! @{ */ #define NOC_SRAMCTL_RAMEIDC_EID_CKB_MASK (0xFFU) #define NOC_SRAMCTL_RAMEIDC_EID_CKB_SHIFT (0U) /*! EID_CKB - Error Injection Data Checkbits */ #define NOC_SRAMCTL_RAMEIDC_EID_CKB(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEIDC_EID_CKB_SHIFT)) & NOC_SRAMCTL_RAMEIDC_EID_CKB_MASK) #define NOC_SRAMCTL_RAMEIDC_EIP_EN_MASK (0x1000000U) #define NOC_SRAMCTL_RAMEIDC_EIP_EN_SHIFT (24U) /*! EIP_EN - Error Injection Into Pipeline Enable * 0b0..No error injected * 0b1..Error injected */ #define NOC_SRAMCTL_RAMEIDC_EIP_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEIDC_EIP_EN_SHIFT)) & NOC_SRAMCTL_RAMEIDC_EIP_EN_MASK) #define NOC_SRAMCTL_RAMEIDC_EIA_EN_MASK (0x40000000U) #define NOC_SRAMCTL_RAMEIDC_EIA_EN_SHIFT (30U) /*! EIA_EN - Error Injection Address Enable * 0b0..Ignore RAMEIA and RAMEIAM * 0b1..Enable RAMEIA and RAMEIAM */ #define NOC_SRAMCTL_RAMEIDC_EIA_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEIDC_EIA_EN_SHIFT)) & NOC_SRAMCTL_RAMEIDC_EIA_EN_MASK) #define NOC_SRAMCTL_RAMEIDC_EID_EN_MASK (0x80000000U) #define NOC_SRAMCTL_RAMEIDC_EID_EN_SHIFT (31U) /*! EID_EN - Error Injection Data Enable * 0b0..No injection * 0b1..Local injection */ #define NOC_SRAMCTL_RAMEIDC_EID_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEIDC_EID_EN_SHIFT)) & NOC_SRAMCTL_RAMEIDC_EID_EN_MASK) /*! @} */ /*! @name RAMEIA - RAM Error Injection Base Address */ /*! @{ */ #define NOC_SRAMCTL_RAMEIA_EIA_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMEIA_EIA_SHIFT (0U) /*! EIA - Error Injection Base Address */ #define NOC_SRAMCTL_RAMEIA_EIA(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEIA_EIA_SHIFT)) & NOC_SRAMCTL_RAMEIA_EIA_MASK) /*! @} */ /*! @name RAMEIAM - RAM Error Injection Address Mask */ /*! @{ */ #define NOC_SRAMCTL_RAMEIAM_EIAM_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMEIAM_EIAM_SHIFT (0U) /*! EIAM - Error Injection Address Mask */ #define NOC_SRAMCTL_RAMEIAM_EIAM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMEIAM_EIAM_SHIFT)) & NOC_SRAMCTL_RAMEIAM_EIAM_MASK) /*! @} */ /*! @name RAMMAXA - RAM Maximum-Value Address */ /*! @{ */ #define NOC_SRAMCTL_RAMMAXA_MAXA_MASK (0xFFFFFFFFU) #define NOC_SRAMCTL_RAMMAXA_MAXA_SHIFT (0U) /*! MAXA - Maximum Address */ #define NOC_SRAMCTL_RAMMAXA_MAXA(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMMAXA_MAXA_SHIFT)) & NOC_SRAMCTL_RAMMAXA_MAXA_MASK) /*! @} */ /*! @name RAMCR2 - RAM Control 2 */ /*! @{ */ #define NOC_SRAMCTL_RAMCR2_DEM_MASK (0x8U) #define NOC_SRAMCTL_RAMCR2_DEM_SHIFT (3U) /*! DEM - Disable Exclusive Monitor * 0b0..Enabled * 0b1..Disabled */ #define NOC_SRAMCTL_RAMCR2_DEM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SRAMCTL_RAMCR2_DEM_SHIFT)) & NOC_SRAMCTL_RAMCR2_DEM_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SRAMCTL_Register_Masks */ /* NOC_SRAMCTL - Peripheral instance base addresses */ /** Peripheral NOC__SRAMCTL base address */ #define NOC__SRAMCTL_BASE (0x490A0000u) /** Peripheral NOC__SRAMCTL base pointer */ #define NOC__SRAMCTL ((NOC_SRAMCTL_Type *)NOC__SRAMCTL_BASE) /** Array initializer of NOC_SRAMCTL peripheral base addresses */ #define NOC_SRAMCTL_BASE_ADDRS { NOC__SRAMCTL_BASE } /** Array initializer of NOC_SRAMCTL peripheral base pointers */ #define NOC_SRAMCTL_BASE_PTRS { NOC__SRAMCTL } /*! * @} */ /* end of group NOC_SRAMCTL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SSI_FWD_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SSI_FWD_MAIN_PROBE_Peripheral_Access_Layer NOC_SSI_FWD_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_SSI_FWD_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ __IO uint32_t TRACEPORTSEL; /**< Trace Port Select, offset: 0x10 */ __IO uint32_t FILTERLUT; /**< Filter Lookup Table, offset: 0x14 */ __IO uint32_t TRACEALARMEN; /**< Trace Alarm Enable, offset: 0x18 */ __I uint32_t TRACEALARMSTATUS; /**< Trace Alarm Status, offset: 0x1C */ __O uint32_t TRACEALARMCLR; /**< Trace Alarm Clear, offset: 0x20 */ __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_0[84]; struct { /* offset: 0x80, array step: 0x60 */ __IO uint32_t FILTERS_ROUTEIDBASE; /**< Filter n Route ID Base, array offset: 0x80, array step: 0x60 */ __IO uint32_t FILTERS_ROUTEIDMASK; /**< Filter n Route ID Mask, array offset: 0x84, array step: 0x60 */ __IO uint32_t FILTERS_ADDRBASE_LOW; /**< Filter n Addr Base Low, array offset: 0x88, array step: 0x60 */ __IO uint32_t FILTERS_ADDRBASE_HIGH; /**< Filter n Addr Base High, array offset: 0x8C, array step: 0x60 */ __IO uint32_t FILTERS_WINDOWSIZE; /**< Filter n Window Size, array offset: 0x90, array step: 0x60 */ uint8_t RESERVED_0[8]; __IO uint32_t FILTERS_OPCODE; /**< Filter n Packet Probe, array offset: 0x9C, array step: 0x60 */ __IO uint32_t FILTERS_STATUS; /**< Filter n Status, array offset: 0xA0, array step: 0x60 */ __IO uint32_t FILTERS_LENGTH; /**< Filter n Length, array offset: 0xA4, array step: 0x60 */ __IO uint32_t FILTERS_URGENCY; /**< Filter n Urgency, array offset: 0xA8, array step: 0x60 */ uint8_t RESERVED_1[52]; } ROUTEIDBASE[2]; uint8_t RESERVED_1[192]; struct { /* offset: 0x200, array step: 0x10 */ __IO uint32_t PORTSEL; /**< Counters n Port Select, array offset: 0x200, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ } COUNTERS[10]; } NOC_SSI_FWD_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_SSI_FWD_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SSI_FWD_MAIN_PROBE_Register_Masks NOC_SSI_FWD_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_SSI_FWD_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_SSI_FWD_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_SSI_FWD_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_SSI_FWD_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name TRACEPORTSEL - Trace Port Select */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_MASK (0x1U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_MASK) /*! @} */ /*! @name FILTERLUT - Filter Lookup Table */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERLUT_FILTERLUT_MASK (0xFU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERLUT_FILTERLUT_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERLUT_FILTERLUT(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERLUT_FILTERLUT_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERLUT_FILTERLUT_MASK) /*! @} */ /*! @name TRACEALARMEN - Trace Alarm Enable */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MASK (0x7U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MASK) /*! @} */ /*! @name TRACEALARMSTATUS - Trace Alarm Status */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MASK (0x7U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MASK) /*! @} */ /*! @name TRACEALARMCLR - Trace Alarm Clear */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MASK (0x7U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_SSI_FWD_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_SSI_FWD_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name FILTERS_ROUTEIDBASE - Filter n Route ID Base */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK (0x1FFFFFU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT (0U) /*! FILTERS_ROUTEIDBASE - Filter n Route ID Base */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDBASE */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDBASE_COUNT (2U) /*! @name FILTERS_ROUTEIDMASK - Filter n Route ID Mask */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK (0x1FFFFFU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT (0U) /*! FILTERS_ROUTEIDMASK - Filter n Route ID Mask */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDMASK */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ROUTEIDMASK_COUNT (2U) /*! @name FILTERS_ADDRBASE_LOW - Filter n Addr Base Low */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT (0U) /*! FILTERS_ADDRBASE_LOW - Address LSB register */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_LOW */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_LOW_COUNT (2U) /*! @name FILTERS_ADDRBASE_HIGH - Filter n Addr Base High */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK (0x1FFFU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT (0U) /*! FILTERS_ADDRBASE_HIGH - Address MSB register */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_HIGH */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_COUNT (2U) /*! @name FILTERS_WINDOWSIZE - Filter n Window Size */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK (0x3FU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT (0U) /*! FILTERS_WINDOWSIZE - Window Size */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_WINDOWSIZE */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_WINDOWSIZE_COUNT (2U) /*! @name FILTERS_OPCODE - Filter n Packet Probe */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_RDEN_MASK (0x1U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_RDEN_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_RDEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_RDEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_WREN_MASK (0x2U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_WREN_SHIFT (1U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_WREN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_WREN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_MASK (0x4U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_SHIFT (2U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_LOCKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_URGEN_MASK (0x8U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_URGEN_SHIFT (3U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_URGEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_URGEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_URGEN_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_OPCODE_COUNT (2U) /*! @name FILTERS_STATUS - Filter n Status */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_REQEN_MASK (0x1U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_REQEN_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_REQEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_REQEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_REQEN_MASK) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_RSPEN_MASK (0x2U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_RSPEN_SHIFT (1U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_RSPEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_RSPEN_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_RSPEN_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_STATUS_COUNT (2U) /*! @name FILTERS_LENGTH - Filter n Length */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_MASK (0xFU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_MASK) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_MASK (0xFU) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_LENGTH_COUNT (2U) /*! @name FILTERS_URGENCY - Filter n Urgency */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_MASK (0x3U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_MASK) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_MASK (0x3U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_SHIFT (0U) #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY */ #define NOC_SSI_FWD_MAIN_PROBE_FILTERS_URGENCY_COUNT (2U) /*! @name PORTSEL - Counters n Port Select */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_MASK (0x1U) #define NOC_SSI_FWD_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_SHIFT (0U) /*! COUNTERS_PORTSEL - Port Select */ #define NOC_SSI_FWD_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_PORTSEL */ #define NOC_SSI_FWD_MAIN_PROBE_PORTSEL_COUNT (10U) /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_SSI_FWD_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_SSI_FWD_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_SRC_INTEVENT_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_SRC */ #define NOC_SSI_FWD_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_SSI_FWD_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_SSI_FWD_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_SSI_FWD_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_FWD_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_SSI_FWD_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_SSI_FWD_MAIN_PROBE_VAL */ #define NOC_SSI_FWD_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_SSI_FWD_MAIN_PROBE_Register_Masks */ /* NOC_SSI_FWD_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE base address */ #define CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE_BASE (0x4AFF0800u) /** Peripheral CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE base pointer */ #define CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE ((NOC_SSI_FWD_MAIN_PROBE_Type *)CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE_BASE) /** Array initializer of NOC_SSI_FWD_MAIN_PROBE peripheral base addresses */ #define NOC_SSI_FWD_MAIN_PROBE_BASE_ADDRS { CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE_BASE } /** Array initializer of NOC_SSI_FWD_MAIN_PROBE peripheral base pointers */ #define NOC_SSI_FWD_MAIN_PROBE_BASE_PTRS { CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE } /*! * @} */ /* end of group NOC_SSI_FWD_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SSI_MASTER_ERROR_ERRLOG_0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SSI_MASTER_ERROR_ERRLOG_0_Peripheral_Access_Layer NOC_SSI_MASTER_ERROR_ERRLOG_0 Peripheral Access Layer * @{ */ /** NOC_SSI_MASTER_ERROR_ERRLOG_0 - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_FAULTEN; /**< offset: 0x8 */ __I uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRVLD; /**< offset: 0xC */ __O uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRCLR; /**< offset: 0x10 */ __I uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0; /**< offset: 0x14 */ __I uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG1; /**< offset: 0x18 */ uint8_t RESERVED_0[4]; __I uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG3; /**< offset: 0x20 */ __I uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG4; /**< offset: 0x24 */ uint8_t RESERVED_1[36]; __IO uint32_t OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_STALLEN; /**< offset: 0x4C */ } NOC_SSI_MASTER_ERROR_ERRLOG_0_Type; /* ---------------------------------------------------------------------------- -- NOC_SSI_MASTER_ERROR_ERRLOG_0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SSI_MASTER_ERROR_ERRLOG_0_Register_Masks NOC_SSI_MASTER_ERROR_ERRLOG_0 Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORETYPEID_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORETYPEID_MASK) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_USERID_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_USERID_MASK) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_NOCID_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_FAULTEN - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_FAULTEN_FAULTEN_MASK (0x1U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_FAULTEN_FAULTEN_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_FAULTEN_FAULTEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_FAULTEN_FAULTEN_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_FAULTEN_FAULTEN_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRVLD - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRVLD_ERRVLD_MASK (0x1U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRVLD_ERRVLD_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRVLD_ERRVLD(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRVLD_ERRVLD_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRVLD_ERRVLD_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRCLR - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRCLR_ERRCLR_MASK (0x1U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRCLR_ERRCLR_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRCLR_ERRCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRCLR_ERRCLR_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRCLR_ERRCLR_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0 - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LOCK_MASK (0x1U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LOCK_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LOCK_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LOCK_MASK) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_OPC_MASK (0x1EU) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_OPC_SHIFT (1U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_OPC(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_OPC_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_OPC_MASK) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_ERRCODE_MASK (0x700U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_ERRCODE_SHIFT (8U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_ERRCODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_ERRCODE_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_ERRCODE_MASK) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LEN1_MASK (0xFF0000U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LEN1_SHIFT (16U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LEN1(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LEN1_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_LEN1_MASK) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_FORMAT_MASK (0x80000000U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_FORMAT_SHIFT (31U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_FORMAT_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG0_FORMAT_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG1 - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG1_ERRLOG1_MASK (0xFFFFFU) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG1_ERRLOG1_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG1_ERRLOG1(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG1_ERRLOG1_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG1_ERRLOG1_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG3 - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG3_ERRLOG3_MASK (0xFFFFFFFFU) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG3_ERRLOG3_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG3_ERRLOG3(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG3_ERRLOG3_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG3_ERRLOG3_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG4 - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG4_ERRLOG4_MASK (0x1FFFFU) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG4_ERRLOG4_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG4_ERRLOG4(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG4_ERRLOG4_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_ERRLOG4_ERRLOG4_MASK) /*! @} */ /*! @name OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_STALLEN - */ /*! @{ */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_STALLEN_STALLEN_MASK (0x1U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_STALLEN_STALLEN_SHIFT (0U) #define NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_STALLEN_STALLEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_STALLEN_STALLEN_SHIFT)) & NOC_SSI_MASTER_ERROR_ERRLOG_0_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_STALLEN_STALLEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_SSI_MASTER_ERROR_ERRLOG_0_Register_Masks */ /* NOC_SSI_MASTER_ERROR_ERRLOG_0 - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0 base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_BASE (0x980C0000u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0 base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0 ((NOC_SSI_MASTER_ERROR_ERRLOG_0_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_BASE) /** Array initializer of NOC_SSI_MASTER_ERROR_ERRLOG_0 peripheral base addresses * */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_BASE } /** Array initializer of NOC_SSI_MASTER_ERROR_ERRLOG_0 peripheral base pointers * */ #define NOC_SSI_MASTER_ERROR_ERRLOG_0_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0 } /*! * @} */ /* end of group NOC_SSI_MASTER_ERROR_ERRLOG_0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_SSI_PRI_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SSI_PRI_MAIN_PROBE_Peripheral_Access_Layer NOC_SSI_PRI_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_SSI_PRI_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ __IO uint32_t TRACEPORTSEL; /**< Trace Port Select, offset: 0x10 */ __IO uint32_t FILTERLUT; /**< Filter Lookup Table, offset: 0x14 */ __IO uint32_t TRACEALARMEN; /**< Trace Alarm Enable, offset: 0x18 */ __I uint32_t TRACEALARMSTATUS; /**< Trace Alarm Status, offset: 0x1C */ __O uint32_t TRACEALARMCLR; /**< Trace Alarm Clear, offset: 0x20 */ __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_0[84]; struct { /* offset: 0x80, array step: 0x60 */ __IO uint32_t FILTERS_ROUTEIDBASE; /**< Filter n Route ID Base, array offset: 0x80, array step: 0x60 */ __IO uint32_t FILTERS_ROUTEIDMASK; /**< Filter n Route ID Mask, array offset: 0x84, array step: 0x60 */ __IO uint32_t FILTERS_ADDRBASE_LOW; /**< Filter n Addr Base Low, array offset: 0x88, array step: 0x60 */ __IO uint32_t FILTERS_ADDRBASE_HIGH; /**< Filter n Addr Base High, array offset: 0x8C, array step: 0x60 */ __IO uint32_t FILTERS_WINDOWSIZE; /**< Filter n Window Size, array offset: 0x90, array step: 0x60 */ __IO uint32_t FILTERS_SECURITYBASE; /**< Filter n Security Base, array offset: 0x94, array step: 0x60 */ __IO uint32_t FILTERS_SECURITYMASK; /**< Filter n Security Mask, array offset: 0x98, array step: 0x60 */ __IO uint32_t FILTERS_OPCODE; /**< Filter n Packet Probe, array offset: 0x9C, array step: 0x60 */ __IO uint32_t FILTERS_STATUS; /**< Filter n Status, array offset: 0xA0, array step: 0x60 */ __IO uint32_t FILTERS_LENGTH; /**< Filter n Length, array offset: 0xA4, array step: 0x60 */ __IO uint32_t FILTERS_URGENCY; /**< Filter n Urgency, array offset: 0xA8, array step: 0x60 */ uint8_t RESERVED_0[52]; } ROUTEIDBASE[2]; uint8_t RESERVED_1[192]; struct { /* offset: 0x200, array step: 0x10 */ __IO uint32_t PORTSEL; /**< Counters n Port Select, array offset: 0x200, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ } COUNTERS[10]; } NOC_SSI_PRI_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_SSI_PRI_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_SSI_PRI_MAIN_PROBE_Register_Masks NOC_SSI_PRI_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_SSI_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_SSI_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_SSI_PRI_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_SSI_PRI_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name TRACEPORTSEL - Trace Port Select */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_MASK (0x1U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_TRACEPORTSEL_TRACEPORTSEL_MASK) /*! @} */ /*! @name FILTERLUT - Filter Lookup Table */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERLUT_FILTERLUT_MASK (0xFU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERLUT_FILTERLUT_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERLUT_FILTERLUT(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERLUT_FILTERLUT_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERLUT_FILTERLUT_MASK) /*! @} */ /*! @name TRACEALARMEN - Trace Alarm Enable */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MASK (0x7U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_TRACEALARMEN_TRACEALARMEN_MASK) /*! @} */ /*! @name TRACEALARMSTATUS - Trace Alarm Status */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MASK (0x7U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_TRACEALARMSTATUS_TRACEALARMSTATUS_MASK) /*! @} */ /*! @name TRACEALARMCLR - Trace Alarm Clear */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MASK (0x7U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_TRACEALARMCLR_TRACEALARMCLR_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_SSI_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_SSI_PRI_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name FILTERS_ROUTEIDBASE - Filter n Route ID Base */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK (0xFFFFFU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT (0U) /*! FILTERS_ROUTEIDBASE - Filter n Route ID Base */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDBASE_FILTERS_ROUTEIDBASE_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDBASE */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDBASE_COUNT (2U) /*! @name FILTERS_ROUTEIDMASK - Filter n Route ID Mask */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK (0xFFFFFU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT (0U) /*! FILTERS_ROUTEIDMASK - Filter n Route ID Mask */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDMASK_FILTERS_ROUTEIDMASK_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDMASK */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ROUTEIDMASK_COUNT (2U) /*! @name FILTERS_ADDRBASE_LOW - Filter n Addr Base Low */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT (0U) /*! FILTERS_ADDRBASE_LOW - Address LSB register */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_LOW_FILTERS_ADDRBASE_LOW_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_LOW */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_LOW_COUNT (2U) /*! @name FILTERS_ADDRBASE_HIGH - Filter n Addr Base High */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT (0U) /*! FILTERS_ADDRBASE_HIGH - Address MSB register */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_FILTERS_ADDRBASE_HIGH_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_HIGH */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_ADDRBASE_HIGH_COUNT (2U) /*! @name FILTERS_WINDOWSIZE - Filter n Window Size */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK (0x3FU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT (0U) /*! FILTERS_WINDOWSIZE - Window Size */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_WINDOWSIZE_FILTERS_WINDOWSIZE_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_WINDOWSIZE */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_WINDOWSIZE_COUNT (2U) /*! @name FILTERS_SECURITYBASE - Filter n Security Base */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYBASE_FILTERS_SECURITYBASE_MASK (0x7U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYBASE_FILTERS_SECURITYBASE_SHIFT (0U) /*! FILTERS_SECURITYBASE - Security Base */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYBASE_FILTERS_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYBASE_FILTERS_SECURITYBASE_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYBASE_FILTERS_SECURITYBASE_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYBASE */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYBASE_COUNT (2U) /*! @name FILTERS_SECURITYMASK - Filter n Security Mask */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_0_SECURITYMASK_MASK (0x7U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_0_SECURITYMASK_SHIFT (0U) /*! FILTERS_0_SECURITYMASK - Security Mask */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_0_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_0_SECURITYMASK_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_0_SECURITYMASK_MASK) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_1_SECURITYMASK_MASK (0x7U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_1_SECURITYMASK_SHIFT (0U) /*! FILTERS_1_SECURITYMASK - Security Mask */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_1_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_1_SECURITYMASK_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_FILTERS_1_SECURITYMASK_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_SECURITYMASK_COUNT (2U) /*! @name FILTERS_OPCODE - Filter n Packet Probe */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_RDEN_MASK (0x1U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_RDEN_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_RDEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_RDEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_WREN_MASK (0x2U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_WREN_SHIFT (1U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_WREN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_WREN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_MASK (0x4U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_SHIFT (2U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_LOCKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_LOCKEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_URGEN_MASK (0x8U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_URGEN_SHIFT (3U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_URGEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_URGEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_URGEN_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_OPCODE_COUNT (2U) /*! @name FILTERS_STATUS - Filter n Status */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_REQEN_MASK (0x1U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_REQEN_SHIFT (0U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_REQEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_REQEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_REQEN_MASK) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_RSPEN_MASK (0x2U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_RSPEN_SHIFT (1U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_RSPEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_RSPEN_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_RSPEN_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_STATUS_COUNT (2U) /*! @name FILTERS_LENGTH - Filter n Length */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_MASK (0xFU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_SHIFT (0U) /*! FILTERS_0_LENGTH - Length */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_0_LENGTH_MASK) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_MASK (0xFU) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_SHIFT (0U) /*! FILTERS_1_LENGTH - Length */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_FILTERS_1_LENGTH_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_LENGTH_COUNT (2U) /*! @name FILTERS_URGENCY - Filter n Urgency */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_MASK (0x3U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_SHIFT (0U) /*! FILTERS_0_URGENCY - Urgency */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_0_URGENCY_MASK) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_MASK (0x3U) #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_SHIFT (0U) /*! FILTERS_1_URGENCY - Urgency */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_FILTERS_1_URGENCY_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY */ #define NOC_SSI_PRI_MAIN_PROBE_FILTERS_URGENCY_COUNT (2U) /*! @name PORTSEL - Counters n Port Select */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_MASK (0x1U) #define NOC_SSI_PRI_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_SHIFT (0U) /*! COUNTERS_PORTSEL - Port Select */ #define NOC_SSI_PRI_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_PORTSEL_COUNTERS_PORTSEL_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_PORTSEL */ #define NOC_SSI_PRI_MAIN_PROBE_PORTSEL_COUNT (10U) /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_SSI_PRI_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_SSI_PRI_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_SRC_INTEVENT_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_SRC */ #define NOC_SSI_PRI_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_SSI_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_SSI_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_SSI_PRI_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_SSI_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_SSI_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_SSI_PRI_MAIN_PROBE_VAL */ #define NOC_SSI_PRI_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_SSI_PRI_MAIN_PROBE_Register_Masks */ /* NOC_SSI_PRI_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE base address */ #define VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE_BASE (0x4C800000u) /** Peripheral VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE base pointer */ #define VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE ((NOC_SSI_PRI_MAIN_PROBE_Type *)VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE_BASE) /** Array initializer of NOC_SSI_PRI_MAIN_PROBE peripheral base addresses */ #define NOC_SSI_PRI_MAIN_PROBE_BASE_ADDRS { VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE_BASE } /** Array initializer of NOC_SSI_PRI_MAIN_PROBE peripheral base pointers */ #define NOC_SSI_PRI_MAIN_PROBE_BASE_PTRS { VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE } /*! * @} */ /* end of group NOC_SSI_PRI_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_TCU_Peripheral_Access_Layer NOC_TCU Peripheral Access Layer * @{ */ /** NOC_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ } NOC_TCU_Type; /* ---------------------------------------------------------------------------- -- NOC_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_TCU_Register_Masks NOC_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define NOC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define NOC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define NOC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & NOC_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define NOC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define NOC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define NOC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & NOC_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define NOC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define NOC_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & NOC_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define NOC_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & NOC_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define NOC_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & NOC_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define NOC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & NOC_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define NOC_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & NOC_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define NOC_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define NOC_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << NOC_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & NOC_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! * @} */ /* end of group NOC_TCU_Register_Masks */ /* NOC_TCU - Peripheral instance base addresses */ /** Peripheral NOC__TCU base address */ #define NOC__TCU_BASE (0x49040000u) /** Peripheral NOC__TCU base pointer */ #define NOC__TCU ((NOC_TCU_Type *)NOC__TCU_BASE) /** Array initializer of NOC_TCU peripheral base addresses */ #define NOC_TCU_BASE_ADDRS { NOC__TCU_BASE } /** Array initializer of NOC_TCU peripheral base pointers */ #define NOC_TCU_BASE_PTRS { NOC__TCU } /*! * @} */ /* end of group NOC_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks */ /* NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0200u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * addresses */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * pointers */ #define NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_USB1_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks */ /* NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0180u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * addresses */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * pointers */ #define NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_USB1_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_Register_Masks */ /* NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0100u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * addresses */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER peripheral base * pointers */ #define NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_USB2_AXI_SLAVE_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE; /**< offset: 0x8 */ __IO uint32_t USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW; /**< offset: 0xC */ __IO uint32_t USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH; /**< offset: 0x10 */ __IO uint32_t USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE; /**< offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE; /**< offset: 0x20 */ } NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0x1FFFFU) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE - */ /*! @{ */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_RDEN_MASK) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_Register_Masks */ /* NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0080u) /** Peripheral * HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_Type *)HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * addresses */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_BASE_ADDRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER peripheral base * pointers */ #define NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_BASE_PTRS { HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_USB2_AXI_SLAVE_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_MAIN_PROBE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_MAIN_PROBE_Peripheral_Access_Layer NOC_VPU_PRI_MAIN_PROBE Peripheral Access Layer * @{ */ /** NOC_VPU_PRI_MAIN_PROBE - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MAINCTL; /**< Main Control, offset: 0x8 */ __IO uint32_t CFGCTL; /**< Configuration Control, offset: 0xC */ uint8_t RESERVED_0[20]; __IO uint32_t STATPERIOD; /**< Statistics Period, offset: 0x24 */ __O uint32_t STATGO; /**< StatGo, offset: 0x28 */ uint8_t RESERVED_1[472]; struct { /* offset: 0x204, array step: 0x10 */ __IO uint32_t SRC; /**< Counters n Source, array offset: 0x204, array step: 0x10 */ uint8_t RESERVED_0[4]; __I uint32_t VAL; /**< Counters n Value, array offset: 0x20C, array step: 0x10 */ uint8_t RESERVED_1[4]; } COUNTERS[10]; } NOC_VPU_PRI_MAIN_PROBE_Type; /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_MAIN_PROBE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_MAIN_PROBE_Register_Masks NOC_VPU_PRI_MAIN_PROBE Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORETYPEID_MASK) #define NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_USERID_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_USERID_MASK) #define NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MAINCTL - Main Control */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ERREN_MASK (0x1U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ERREN_SHIFT (0U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ERREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ERREN_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ERREN_MASK) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_TRACEEN_MASK (0x2U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT (1U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_TRACEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_TRACEEN_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_TRACEEN_MASK) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK (0x4U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT (2U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_PAYLOADEN_MASK) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATEN_MASK (0x8U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATEN_SHIFT (3U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATEN_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATEN_MASK) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ALARMEN_MASK (0x10U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT (4U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ALARMEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ALARMEN_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_ALARMEN_MASK) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK (0x20U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT (5U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_STATCONDDUMP_MASK) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK (0x40U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT (6U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_INTRUSIVEMODE_MASK) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK (0x80U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT (7U) #define NOC_VPU_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MASK) /*! @} */ /*! @name CFGCTL - Configuration Control */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_MASK (0x1U) #define NOC_VPU_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT (0U) #define NOC_VPU_PRI_MAIN_PROBE_CFGCTL_GLOBALEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_CFGCTL_GLOBALEN_MASK) #define NOC_VPU_PRI_MAIN_PROBE_CFGCTL_ACTIVE_MASK (0x2U) #define NOC_VPU_PRI_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT (1U) #define NOC_VPU_PRI_MAIN_PROBE_CFGCTL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_CFGCTL_ACTIVE_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_CFGCTL_ACTIVE_MASK) /*! @} */ /*! @name STATPERIOD - Statistics Period */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK (0x1FU) #define NOC_VPU_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT (0U) #define NOC_VPU_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_STATPERIOD_STATPERIOD_MASK) /*! @} */ /*! @name STATGO - StatGo */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_STATGO_STATGO_MASK (0x1U) #define NOC_VPU_PRI_MAIN_PROBE_STATGO_STATGO_SHIFT (0U) #define NOC_VPU_PRI_MAIN_PROBE_STATGO_STATGO(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_STATGO_STATGO_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_STATGO_STATGO_MASK) /*! @} */ /*! @name SRC - Counters n Source */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_SRC_INTEVENT_MASK (0x1FU) #define NOC_VPU_PRI_MAIN_PROBE_SRC_INTEVENT_SHIFT (0U) /*! INTEVENT * 0b00000..the counter is disabled. * 0b00001..counts Idle cycles (Vld=0 out of a packet). * 0b00010..counts effective transfer cycles (Vld=1 and Rdy=1). * 0b00011..counts busy cycles (Vld=1 and Rdy=0). * 0b00100..counts wait cycles (Vld=0 inside a packet). * 0b00101..counts locked-idle cycles (Vld=0 out of a packet and inside a Lock). * 0b00110..counts packets (Vld=1 and Head=1 and Rdy=1). * 0b00111..counts the packet candidates after the LUT (can be used also as "always" count). * 0b01000..counts the total number of bytes (count += 2**Len). * 0b01001..counts the cycles where pressure level > 0 (Press[0]=1). * 0b01010..counts the cycles where pressure level > 1 (Press[1]=1). * 0b01011..counts the cycles where pressure level > 2 (Press[2]=1). * 0b01100..counts the packet candidates after the Filter 0. * 0b01101..counts the packet candidates after the Filter 1. * 0b01110..counts the packet candidates after the Filter 2. * 0b01111..counts the packet candidates after the Filter 3. * 0b10000..counts the wrap-arround of the counter 2N in the counter 2N+1 (OFF for counter 2N). * 0b10001..counts the packet enabled byte on each LUT hit. * 0b10010..counts the packet len in byte unit on each LUT hit. * 0b10011..counts the packet enabled byte on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10100..counts the packet len in byte unit on each FILT_i hit (connected only counter idx = i % nFilter). * 0b10101..counts the cycles where pressure level > 0 (Press[3]=1). * 0b10110..counts the cycles where pressure level > 0 (Press[4]=1). * 0b10111..counts the cycles where pressure level > 0 (Press[5]=1). * 0b11000..counts the cycles where pressure level > 0 (Press[6]=1). * 0b11001..reserved * 0b11010..reserved * 0b11011..reserved * 0b11100..reserved * 0b11101..reserved * 0b11110..reserved * 0b11111..reserved */ #define NOC_VPU_PRI_MAIN_PROBE_SRC_INTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_SRC_INTEVENT_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_SRC_INTEVENT_MASK) #define NOC_VPU_PRI_MAIN_PROBE_SRC_EXTEVENT_MASK (0x20U) #define NOC_VPU_PRI_MAIN_PROBE_SRC_EXTEVENT_SHIFT (5U) #define NOC_VPU_PRI_MAIN_PROBE_SRC_EXTEVENT(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_SRC_EXTEVENT_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_SRC_EXTEVENT_MASK) /*! @} */ /* The count of NOC_VPU_PRI_MAIN_PROBE_SRC */ #define NOC_VPU_PRI_MAIN_PROBE_SRC_COUNT (10U) /*! @name VAL - Counters n Value */ /*! @{ */ #define NOC_VPU_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_MASK (0xFFFFFU) #define NOC_VPU_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT (0U) /*! COUNTERS_VAL - Value */ #define NOC_VPU_PRI_MAIN_PROBE_VAL_COUNTERS_VAL(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_SHIFT)) & NOC_VPU_PRI_MAIN_PROBE_VAL_COUNTERS_VAL_MASK) /*! @} */ /* The count of NOC_VPU_PRI_MAIN_PROBE_VAL */ #define NOC_VPU_PRI_MAIN_PROBE_VAL_COUNT (10U) /*! * @} */ /* end of group NOC_VPU_PRI_MAIN_PROBE_Register_Masks */ /* NOC_VPU_PRI_MAIN_PROBE - Peripheral instance base addresses */ /** Peripheral VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE base address */ #define VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE_BASE (0x4C800400u) /** Peripheral VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE base pointer */ #define VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE ((NOC_VPU_PRI_MAIN_PROBE_Type *)VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE_BASE) /** Array initializer of NOC_VPU_PRI_MAIN_PROBE peripheral base addresses */ #define NOC_VPU_PRI_MAIN_PROBE_BASE_ADDRS { VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE_BASE } /** Array initializer of NOC_VPU_PRI_MAIN_PROBE peripheral base pointers */ #define NOC_VPU_PRI_MAIN_PROBE_BASE_PTRS { VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE } /*! * @} */ /* end of group NOC_VPU_PRI_MAIN_PROBE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_PROBE_XSTATPROFILER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_PROBE_XSTATPROFILER_Peripheral_Access_Layer NOC_VPU_PRI_PROBE_XSTATPROFILER Peripheral Access Layer * @{ */ /** NOC_VPU_PRI_PROBE_XSTATPROFILER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t EN; /**< Enable, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t TRANSACTIONSTATPROFILER_OBSERVEDSEL[2]; /**< ObservedSel n, array offset: 0x10, array step: 0x4 */ uint8_t RESERVED_0[8]; __IO uint32_t NTENURELINES_0; /**< Number of Transaction Probe Lines, offset: 0x20 */ uint8_t RESERVED_1[8]; __IO uint32_t TRANSACTIONSTATPROFILER_THRESHOLDS_[2][4]; /**< Transaction Profiler Thresholds Register, array offset: 0x2C, array step: index*0x10, index2*0x4 */ uint8_t RESERVED_2[32]; __I uint32_t OVERFLOWSTATUS; /**< Overflow Status, offset: 0x6C */ __O uint32_t OVERFLOWRESET; /**< Overflow Reset, offset: 0x70 */ __IO uint32_t PENDINGEVENTMODE; /**< Pending Event Mode, offset: 0x74 */ __IO uint32_t PRESCALER; /**< Pre Scaler, offset: 0x78 */ } NOC_VPU_PRI_PROBE_XSTATPROFILER_Type; /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_PROBE_XSTATPROFILER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_PROBE_XSTATPROFILER_Register_Masks NOC_VPU_PRI_PROBE_XSTATPROFILER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORETYPEID_MASK) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_USERID_MASK) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name EN - Enable */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_EN_EN_MASK (0x1U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_EN_EN_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_EN_EN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_EN_EN_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_EN_EN_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_MODE_MODE_MASK (0x3U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_MODE_MODE_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_MODE_MODE_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_MODE_MODE_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_OBSERVEDSEL - ObservedSel n */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK (0x1U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_OBSERVEDSEL_MASK) /*! @} */ /* The count of NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_OBSERVEDSEL_COUNT (2U) /*! @name NTENURELINES_0 - Number of Transaction Probe Lines */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK (0xFU) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_NTENURELINES_0_NTENURELINES_0_MASK) /*! @} */ /*! @name TRANSACTIONSTATPROFILER_THRESHOLDS_ - Transaction Profiler Thresholds Register */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK (0x7FFU) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT (0U) /*! THRESHOLDS - Thresholds 1 3 */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__THRESHOLDS_MASK) /*! @} */ /* The count of NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT (2U) /* The count of NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS_ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_TRANSACTIONSTATPROFILER_THRESHOLDS__COUNT2 (4U) /*! @name OVERFLOWSTATUS - Overflow Status */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK (0x3U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWSTATUS_OVERFLOWSTATUS_MASK) /*! @} */ /*! @name OVERFLOWRESET - Overflow Reset */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK (0x3U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_OVERFLOWRESET_OVERFLOWRESET_MASK) /*! @} */ /*! @name PENDINGEVENTMODE - Pending Event Mode */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK (0x1U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_PENDINGEVENTMODE_PENDINGEVENTMODE_MASK) /*! @} */ /*! @name PRESCALER - Pre Scaler */ /*! @{ */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_MASK (0xFFU) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT (0U) #define NOC_VPU_PRI_PROBE_XSTATPROFILER_PRESCALER_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_SHIFT)) & NOC_VPU_PRI_PROBE_XSTATPROFILER_PRESCALER_PRESCALER_MASK) /*! @} */ /*! * @} */ /* end of group NOC_VPU_PRI_PROBE_XSTATPROFILER_Register_Masks */ /* NOC_VPU_PRI_PROBE_XSTATPROFILER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER base address * */ #define VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C800A00u) /** Peripheral VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER base pointer * */ #define VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER ((NOC_VPU_PRI_PROBE_XSTATPROFILER_Type *)VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE) /** Array initializer of NOC_VPU_PRI_PROBE_XSTATPROFILER peripheral base * addresses */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_BASE_ADDRS { VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE } /** Array initializer of NOC_VPU_PRI_PROBE_XSTATPROFILER peripheral base * pointers */ #define NOC_VPU_PRI_PROBE_XSTATPROFILER_BASE_PTRS { VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER } /*! * @} */ /* end of group NOC_VPU_PRI_PROBE_XSTATPROFILER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_RD_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_RD_I_QOSGENERATOR_Peripheral_Access_Layer NOC_VPU_PRI_RD_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_VPU_PRI_RD_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_VPU_PRI_RD_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_RD_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_RD_I_QOSGENERATOR_Register_Masks NOC_VPU_PRI_RD_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_VPU_PRI_RD_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_VPU_PRI_RD_I_QOSGENERATOR_Register_Masks */ /* NOC_VPU_PRI_RD_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR base address */ #define VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR_BASE (0x4C800800u) /** Peripheral VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR base pointer */ #define VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR ((NOC_VPU_PRI_RD_I_QOSGENERATOR_Type *)VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_VPU_PRI_RD_I_QOSGENERATOR peripheral base addresses * */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_BASE_ADDRS { VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_VPU_PRI_RD_I_QOSGENERATOR peripheral base pointers * */ #define NOC_VPU_PRI_RD_I_QOSGENERATOR_BASE_PTRS { VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_VPU_PRI_RD_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_RD_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_RD_I_XSTATFILTER_Peripheral_Access_Layer NOC_VPU_PRI_RD_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_VPU_PRI_RD_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_VPU_PRI_RD_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_RD_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_RD_I_XSTATFILTER_Register_Masks NOC_VPU_PRI_RD_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_VPU_PRI_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_VPU_PRI_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_VPU_PRI_RD_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_VPU_PRI_RD_I_XSTATFILTER_Register_Masks */ /* NOC_VPU_PRI_RD_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER base address */ #define VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C800900u) /** Peripheral VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER ((NOC_VPU_PRI_RD_I_XSTATFILTER_Type *)VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_VPU_PRI_RD_I_XSTATFILTER peripheral base addresses * */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_BASE_ADDRS { VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_VPU_PRI_RD_I_XSTATFILTER peripheral base pointers */ #define NOC_VPU_PRI_RD_I_XSTATFILTER_BASE_PTRS { VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_VPU_PRI_RD_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_WR_I_QOSGENERATOR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_WR_I_QOSGENERATOR_Peripheral_Access_Layer NOC_VPU_PRI_WR_I_QOSGENERATOR Peripheral Access Layer * @{ */ /** NOC_VPU_PRI_WR_I_QOSGENERATOR - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t PRIORITY; /**< Priority, offset: 0x8 */ __IO uint32_t MODE; /**< Mode, offset: 0xC */ __IO uint32_t BANDWIDTH; /**< Bandwidth, offset: 0x10 */ __IO uint32_t SATURATION; /**< Saturation, offset: 0x14 */ __IO uint32_t EXTCONTROL; /**< External Inputs Control, offset: 0x18 */ } NOC_VPU_PRI_WR_I_QOSGENERATOR_Type; /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_WR_I_QOSGENERATOR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_WR_I_QOSGENERATOR_Register_Masks NOC_VPU_PRI_WR_I_QOSGENERATOR Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORETYPEID_MASK) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_USERID_MASK) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name PRIORITY - Priority */ /*! @{ */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P0_MASK (0x3U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT (0U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P0(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P0_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P0_MASK) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P1_MASK (0x300U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT (8U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P1(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P1_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_PRIORITY_P1_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_MODE_MODE_MASK (0x3U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_MODE_MODE_SHIFT (0U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_MODE_MODE_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_MODE_MODE_MASK) /*! @} */ /*! @name BANDWIDTH - Bandwidth */ /*! @{ */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK (0x1FFFU) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT (0U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_BANDWIDTH_BANDWIDTH_MASK) /*! @} */ /*! @name SATURATION - Saturation */ /*! @{ */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK (0x3FFU) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT (0U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_SATURATION_SATURATION(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_SATURATION_SATURATION_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_SATURATION_SATURATION_MASK) /*! @} */ /*! @name EXTCONTROL - External Inputs Control */ /*! @{ */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK (0x1U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT (0U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_SOCKETQOSEN_MASK) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK (0x2U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT (1U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTTHREN_MASK) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK (0x4U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT (2U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_INTCLKEN_MASK) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK (0x8U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT (3U) #define NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_SHIFT)) & NOC_VPU_PRI_WR_I_QOSGENERATOR_EXTCONTROL_EXTLIMITEN_MASK) /*! @} */ /*! * @} */ /* end of group NOC_VPU_PRI_WR_I_QOSGENERATOR_Register_Masks */ /* NOC_VPU_PRI_WR_I_QOSGENERATOR - Peripheral instance base addresses */ /** Peripheral VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR base address */ #define VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR_BASE (0x4C800880u) /** Peripheral VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR base pointer */ #define VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR ((NOC_VPU_PRI_WR_I_QOSGENERATOR_Type *)VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR_BASE) /** Array initializer of NOC_VPU_PRI_WR_I_QOSGENERATOR peripheral base addresses * */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_BASE_ADDRS { VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR_BASE } /** Array initializer of NOC_VPU_PRI_WR_I_QOSGENERATOR peripheral base pointers * */ #define NOC_VPU_PRI_WR_I_QOSGENERATOR_BASE_PTRS { VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR } /*! * @} */ /* end of group NOC_VPU_PRI_WR_I_QOSGENERATOR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_WR_I_XSTATFILTER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_WR_I_XSTATFILTER_Peripheral_Access_Layer NOC_VPU_PRI_WR_I_XSTATFILTER Peripheral Access Layer * @{ */ /** NOC_VPU_PRI_WR_I_XSTATFILTER - Register Layout Typedef */ typedef struct { __I uint32_t ID_COREID; /**< Core ID, offset: 0x0 */ __I uint32_t ID_REVISIONID; /**< Revision ID, offset: 0x4 */ __IO uint32_t MODE; /**< Mode, offset: 0x8 */ __IO uint32_t ADDRBASE_LOW; /**< Address Base LSB, offset: 0xC */ __IO uint32_t ADDRBASE_HIGH; /**< Address Base MSB, offset: 0x10 */ __IO uint32_t ADDRWINDOWSIZE; /**< Address Window Size, offset: 0x14 */ uint8_t RESERVED_0[8]; __IO uint32_t OPCODE; /**< Packet Opcode, offset: 0x20 */ __IO uint32_t USERBASE; /**< User Base, offset: 0x24 */ __IO uint32_t USERMASK; /**< User Mask, offset: 0x28 */ __IO uint32_t SECURITYBASE; /**< Security Base, offset: 0x2C */ __IO uint32_t SECURITYMASK; /**< Security Mask, offset: 0x30 */ } NOC_VPU_PRI_WR_I_XSTATFILTER_Type; /* ---------------------------------------------------------------------------- -- NOC_VPU_PRI_WR_I_XSTATFILTER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NOC_VPU_PRI_WR_I_XSTATFILTER_Register_Masks NOC_VPU_PRI_WR_I_XSTATFILTER Register Masks * @{ */ /*! @name ID_COREID - Core ID */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK (0xFFU) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORETYPEID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORETYPEID_MASK) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT (8U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_ID_COREID_CORECHECKSUM_MASK) /*! @} */ /*! @name ID_REVISIONID - Revision ID */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK (0xFFU) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_USERID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_USERID_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_USERID_MASK) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK (0xFFFFFF00U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT (8U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_NOCID(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_ID_REVISIONID_NOCID_MASK) /*! @} */ /*! @name MODE - Mode */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_MODE_MODE_MASK (0x1U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_MODE_MODE_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_MODE_MODE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_MODE_MODE_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_MODE_MODE_MASK) /*! @} */ /*! @name ADDRBASE_LOW - Address Base LSB */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK (0xFFFFFFFFU) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_LOW_ADDRBASE_LOW_MASK) /*! @} */ /*! @name ADDRBASE_HIGH - Address Base MSB */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK (0xFFU) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRBASE_HIGH_ADDRBASE_HIGH_MASK) /*! @} */ /*! @name ADDRWINDOWSIZE - Address Window Size */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK (0x3FU) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_ADDRWINDOWSIZE_ADDRWINDOWSIZE_MASK) /*! @} */ /*! @name OPCODE - Packet Opcode */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_RDEN_MASK (0x1U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_RDEN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_RDEN_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_RDEN_MASK) #define NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_WREN_MASK (0x2U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT (1U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_WREN(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_WREN_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_OPCODE_WREN_MASK) /*! @} */ /*! @name USERBASE - User Base */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK (0xFFFFFFFU) #define NOC_VPU_PRI_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_USERBASE_USERBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_USERBASE_USERBASE_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_USERBASE_USERBASE_MASK) /*! @} */ /*! @name USERMASK - User Mask */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK (0xFFFFFFFU) #define NOC_VPU_PRI_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_USERMASK_USERMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_USERMASK_USERMASK_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_USERMASK_USERMASK_MASK) /*! @} */ /*! @name SECURITYBASE - Security Base */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK (0x7U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYBASE_SECURITYBASE_MASK) /*! @} */ /*! @name SECURITYMASK - Security Mask */ /*! @{ */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK (0x7U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT (0U) #define NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK(x) (((uint32_t)(((uint32_t)(x)) << NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_SHIFT)) & NOC_VPU_PRI_WR_I_XSTATFILTER_SECURITYMASK_SECURITYMASK_MASK) /*! @} */ /*! * @} */ /* end of group NOC_VPU_PRI_WR_I_XSTATFILTER_Register_Masks */ /* NOC_VPU_PRI_WR_I_XSTATFILTER - Peripheral instance base addresses */ /** Peripheral VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER base address */ #define VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C800980u) /** Peripheral VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER base pointer */ #define VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER ((NOC_VPU_PRI_WR_I_XSTATFILTER_Type *)VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE) /** Array initializer of NOC_VPU_PRI_WR_I_XSTATFILTER peripheral base addresses * */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_BASE_ADDRS { VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE } /** Array initializer of NOC_VPU_PRI_WR_I_XSTATFILTER peripheral base pointers */ #define NOC_VPU_PRI_WR_I_XSTATFILTER_BASE_PTRS { VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER } /*! * @} */ /* end of group NOC_VPU_PRI_WR_I_XSTATFILTER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NPU_EIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NPU_EIM_Peripheral_Access_Layer NPU_EIM Peripheral Access Layer * @{ */ /** NPU_EIM - Register Layout Typedef */ typedef struct { __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ uint8_t RESERVED_0[248]; __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ __IO uint32_t EICHD0_WORD2; /**< Error Injection Channel Descriptor 0, Word2, offset: 0x108 */ __IO uint32_t EICHD0_WORD3; /**< Error Injection Channel Descriptor 0, Word3, offset: 0x10C */ __IO uint32_t EICHD0_WORD4; /**< Error Injection Channel Descriptor 0, Word4, offset: 0x110 */ uint8_t RESERVED_1[44]; __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ } NPU_EIM_Type; /* ---------------------------------------------------------------------------- -- NPU_EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NPU_EIM_Register_Masks NPU_EIM Register Masks * @{ */ /*! @name EIMCR - Error Injection Module Configuration Register */ /*! @{ */ #define NPU_EIM_EIMCR_GEIEN_MASK (0x1U) #define NPU_EIM_EIMCR_GEIEN_SHIFT (0U) /*! GEIEN - Global Error Injection Enable * 0b0..Disabled * 0b1..Enabled */ #define NPU_EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EIMCR_GEIEN_SHIFT)) & NPU_EIM_EIMCR_GEIEN_MASK) /*! @} */ /*! @name EICHEN - Error Injection Channel Enable register */ /*! @{ */ #define NPU_EIM_EICHEN_EICH1EN_MASK (0x40000000U) #define NPU_EIM_EICHEN_EICH1EN_SHIFT (30U) /*! EICH1EN - Error Injection Channel 1 Enable * 0b0..Error injection is disabled on Error Injection Channel 1 * 0b1..Error injection is enabled on Error Injection Channel 1 */ #define NPU_EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHEN_EICH1EN_SHIFT)) & NPU_EIM_EICHEN_EICH1EN_MASK) #define NPU_EIM_EICHEN_EICH0EN_MASK (0x80000000U) #define NPU_EIM_EICHEN_EICH0EN_SHIFT (31U) /*! EICH0EN - Error Injection Channel 0 Enable * 0b0..Error injection is disabled on Error Injection Channel 0 * 0b1..Error injection is enabled on Error Injection Channel 0 */ #define NPU_EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHEN_EICH0EN_SHIFT)) & NPU_EIM_EICHEN_EICH0EN_MASK) /*! @} */ /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ /*! @{ */ #define NPU_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFFFFF000U) #define NPU_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (12U) /*! CHKBIT_MASK - Checkbit Mask */ #define NPU_EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & NPU_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ /*! @{ */ #define NPU_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define NPU_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define NPU_EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & NPU_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD2 - Error Injection Channel Descriptor 0, Word2 */ /*! @{ */ #define NPU_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define NPU_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define NPU_EIM_EICHD0_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT)) & NPU_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD3 - Error Injection Channel Descriptor 0, Word3 */ /*! @{ */ #define NPU_EIM_EICHD0_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) #define NPU_EIM_EICHD0_WORD3_B8_11DATA_MASK_SHIFT (0U) /*! B8_11DATA_MASK - Data Mask Bytes 8-11 */ #define NPU_EIM_EICHD0_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHD0_WORD3_B8_11DATA_MASK_SHIFT)) & NPU_EIM_EICHD0_WORD3_B8_11DATA_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD4 - Error Injection Channel Descriptor 0, Word4 */ /*! @{ */ #define NPU_EIM_EICHD0_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) #define NPU_EIM_EICHD0_WORD4_B12_15DATA_MASK_SHIFT (0U) /*! B12_15DATA_MASK - Data Mask Bytes 12-15 */ #define NPU_EIM_EICHD0_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHD0_WORD4_B12_15DATA_MASK_SHIFT)) & NPU_EIM_EICHD0_WORD4_B12_15DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ /*! @{ */ #define NPU_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0x80000000U) #define NPU_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (31U) /*! CHKBIT_MASK - Checkbit Mask */ #define NPU_EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & NPU_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ /*! @{ */ #define NPU_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0x1U) #define NPU_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define NPU_EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << NPU_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & NPU_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! * @} */ /* end of group NPU_EIM_Register_Masks */ /* NPU_EIM - Peripheral instance base addresses */ /** Peripheral NPU__EIM_NPUMIX base address */ #define NPU__EIM_NPUMIX_BASE (0x4A860000u) /** Peripheral NPU__EIM_NPUMIX base pointer */ #define NPU__EIM_NPUMIX ((NPU_EIM_Type *)NPU__EIM_NPUMIX_BASE) /** Array initializer of NPU_EIM peripheral base addresses */ #define NPU_EIM_BASE_ADDRS { NPU__EIM_NPUMIX_BASE } /** Array initializer of NPU_EIM peripheral base pointers */ #define NPU_EIM_BASE_PTRS { NPU__EIM_NPUMIX } /*! * @} */ /* end of group NPU_EIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NPU_LSTCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NPU_LSTCU_Peripheral_Access_Layer NPU_LSTCU Peripheral Access Layer * @{ */ /** NPU_LSTCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x10 */ uint8_t RESERVED_2[76]; __I uint32_t MB_RSTAT0; /**< MBIST Run Status 0, offset: 0x60 */ uint8_t RESERVED_3[284]; __IO uint32_t MBFM0; /**< MBIST Fault Mapping 0, offset: 0x180 */ uint8_t RESERVED_4[220]; __IO uint32_t STAG; /**< Stagger, offset: 0x260 */ uint8_t RESERVED_5[12]; __IO uint32_t PH1_DUR; /**< Phase 1 Duration, offset: 0x270 */ uint8_t RESERVED_6[140]; __IO uint32_t MBPTR[1]; /**< MBIST Scheduler Pointer, array offset: 0x300, array step: 0x4 */ } NPU_LSTCU_Type; /* ---------------------------------------------------------------------------- -- NPU_LSTCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NPU_LSTCU_Register_Masks NPU_LSTCU Register Masks * @{ */ /*! @name ERR_STAT - Error Status */ /*! @{ */ #define NPU_LSTCU_ERR_STAT_INVP_MB_MASK (0x2U) #define NPU_LSTCU_ERR_STAT_INVP_MB_SHIFT (1U) /*! INVP_MB - Invalid Pointer MBIST * 0b0..No invalid pointer * 0b1..Invalid BIST pointer specified */ #define NPU_LSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_ERR_STAT_INVP_MB_SHIFT)) & NPU_LSTCU_ERR_STAT_INVP_MB_MASK) #define NPU_LSTCU_ERR_STAT_UFSF_MASK (0x10000U) #define NPU_LSTCU_ERR_STAT_UFSF_SHIFT (16U) /*! UFSF - Unrecoverable Fault Status * 0b0..No unrecoverable fault * 0b1..Unrecoverable fault */ #define NPU_LSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_ERR_STAT_UFSF_SHIFT)) & NPU_LSTCU_ERR_STAT_UFSF_MASK) #define NPU_LSTCU_ERR_STAT_RFSF_MASK (0x20000U) #define NPU_LSTCU_ERR_STAT_RFSF_SHIFT (17U) /*! RFSF - Recoverable Fault Status * 0b0..No recoverable fault * 0b1..Recoverable fault */ #define NPU_LSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_ERR_STAT_RFSF_SHIFT)) & NPU_LSTCU_ERR_STAT_RFSF_MASK) /*! @} */ /*! @name ERR_FM - Error Fault Mapping */ /*! @{ */ #define NPU_LSTCU_ERR_FM_INVPFMMB_MASK (0x2U) #define NPU_LSTCU_ERR_FM_INVPFMMB_SHIFT (1U) /*! INVPFMMB - Invalid BIST Pointer Fault Mapping During MBIST Scheduling * 0b0..Recoverable * 0b1..Unrecoverable */ #define NPU_LSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_ERR_FM_INVPFMMB_SHIFT)) & NPU_LSTCU_ERR_FM_INVPFMMB_MASK) /*! @} */ /*! @name MB_RSTAT0 - MBIST Run Status 0 */ /*! @{ */ #define NPU_LSTCU_MB_RSTAT0_MBSTAT0_MASK (0x1U) #define NPU_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT (0U) /*! MBSTAT0 - MBIST Run Result Status 0 * 0b0..Pass * 0b1..Fail */ #define NPU_LSTCU_MB_RSTAT0_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_MB_RSTAT0_MBSTAT0_SHIFT)) & NPU_LSTCU_MB_RSTAT0_MBSTAT0_MASK) /*! @} */ /*! @name MBFM0 - MBIST Fault Mapping 0 */ /*! @{ */ #define NPU_LSTCU_MBFM0_MBSTATFM0_MASK (0x1U) #define NPU_LSTCU_MBFM0_MBSTATFM0_SHIFT (0U) /*! MBSTATFM0 - MBIST Fault Mapping n * 0b0..Recoverable * 0b1..Unrecoverable */ #define NPU_LSTCU_MBFM0_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_MBFM0_MBSTATFM0_SHIFT)) & NPU_LSTCU_MBFM0_MBSTATFM0_MASK) /*! @} */ /*! @name STAG - Stagger */ /*! @{ */ #define NPU_LSTCU_STAG_MB_DELAY_MASK (0xFF00U) #define NPU_LSTCU_STAG_MB_DELAY_SHIFT (8U) /*! MB_DELAY - MBIST Delay */ #define NPU_LSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_STAG_MB_DELAY_SHIFT)) & NPU_LSTCU_STAG_MB_DELAY_MASK) /*! @} */ /*! @name PH1_DUR - Phase 1 Duration */ /*! @{ */ #define NPU_LSTCU_PH1_DUR_PH1DUR_MASK (0x3FFU) #define NPU_LSTCU_PH1_DUR_PH1DUR_SHIFT (0U) /*! PH1DUR - Phase 1 Duration */ #define NPU_LSTCU_PH1_DUR_PH1DUR(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_PH1_DUR_PH1DUR_SHIFT)) & NPU_LSTCU_PH1_DUR_PH1DUR_MASK) /*! @} */ /*! @name MBPTR - MBIST Scheduler Pointer */ /*! @{ */ #define NPU_LSTCU_MBPTR_MBPTR_MASK (0xFFU) #define NPU_LSTCU_MBPTR_MBPTR_SHIFT (0U) /*! MBPTR - MBIST Pointer */ #define NPU_LSTCU_MBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_MBPTR_MBPTR_SHIFT)) & NPU_LSTCU_MBPTR_MBPTR_MASK) #define NPU_LSTCU_MBPTR_MBCSM_MASK (0x100U) #define NPU_LSTCU_MBPTR_MBCSM_SHIFT (8U) /*! MBCSM - MBIST Mode * 0b0..Sequential * 0b1..Concurrent */ #define NPU_LSTCU_MBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_MBPTR_MBCSM_SHIFT)) & NPU_LSTCU_MBPTR_MBCSM_MASK) #define NPU_LSTCU_MBPTR_MBEOL_MASK (0x80000000U) #define NPU_LSTCU_MBPTR_MBEOL_SHIFT (31U) /*! MBEOL - MBIST End of List * 0b0..Not end of list * 0b1..End of list */ #define NPU_LSTCU_MBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << NPU_LSTCU_MBPTR_MBEOL_SHIFT)) & NPU_LSTCU_MBPTR_MBEOL_MASK) /*! @} */ /* The count of NPU_LSTCU_MBPTR */ #define NPU_LSTCU_MBPTR_COUNT (1U) /*! * @} */ /* end of group NPU_LSTCU_Register_Masks */ /* NPU_LSTCU - Peripheral instance base addresses */ /** Peripheral NPU__LSTCU_NPUMIX base address */ #define NPU__LSTCU_NPUMIX_BASE (0x4A850000u) /** Peripheral NPU__LSTCU_NPUMIX base pointer */ #define NPU__LSTCU_NPUMIX ((NPU_LSTCU_Type *)NPU__LSTCU_NPUMIX_BASE) /** Array initializer of NPU_LSTCU peripheral base addresses */ #define NPU_LSTCU_BASE_ADDRS { NPU__LSTCU_NPUMIX_BASE } /** Array initializer of NPU_LSTCU peripheral base pointers */ #define NPU_LSTCU_BASE_PTRS { NPU__LSTCU_NPUMIX } /*! * @} */ /* end of group NPU_LSTCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NPU_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NPU_TCU_Peripheral_Access_Layer NPU_TCU Peripheral Access Layer * @{ */ /** NPU_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_3[60]; __IO uint32_t TCU_DFT_FUSE; /**< observe MIX fuse state and override it, offset: 0xC40 */ } NPU_TCU_Type; /* ---------------------------------------------------------------------------- -- NPU_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NPU_TCU_Register_Masks NPU_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define NPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define NPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define NPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & NPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define NPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define NPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define NPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & NPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define NPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define NPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & NPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define NPU_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & NPU_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define NPU_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & NPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define NPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & NPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define NPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & NPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define NPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define NPU_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & NPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - observe MIX fuse state and override it */ /*! @{ */ #define NPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define NPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define NPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & NPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define NPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0x2U) #define NPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define NPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << NPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & NPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group NPU_TCU_Register_Masks */ /* NPU_TCU - Peripheral instance base addresses */ /** Peripheral NPU__TCU base address */ #define NPU__TCU_BASE (0x4A800000u) /** Peripheral NPU__TCU base pointer */ #define NPU__TCU ((NPU_TCU_Type *)NPU__TCU_BASE) /** Array initializer of NPU_TCU peripheral base addresses */ #define NPU_TCU_BASE_ADDRS { NPU__TCU_BASE } /** Array initializer of NPU_TCU peripheral base pointers */ #define NPU_TCU_BASE_PTRS { NPU__TCU } /*! * @} */ /* end of group NPU_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NR_Peripheral_Access_Layer NR Peripheral Access Layer * @{ */ /** NR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x14 */ __IO uint32_t CTRL_CAM; /**< Camera 0 NR Control Register, array offset: 0x0, array step: 0x14 */ __IO uint32_t BLEND_SCALE_CAM; /**< Camera 0 NR Blending Scale Register, array offset: 0x4, array step: 0x14 */ __IO uint32_t BLEND_TH0_CAM; /**< Camera 0 NR Blend Threshold 0 Register, array offset: 0x8, array step: 0x14 */ uint8_t RESERVED_0[4]; __I uint32_t EDGECNT_CAM; /**< Camera 0 NR Edge Count Register, array offset: 0x10, array step: 0x14 */ } NEO_PIPE2_NR_CONF[1]; } NR_Type; /* ---------------------------------------------------------------------------- -- NR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NR_Register_Masks NR Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 NR Control Register */ /*! @{ */ #define NR_CTRL_CAM_DEBUG_MASK (0x300U) #define NR_CTRL_CAM_DEBUG_SHIFT (8U) /*! DEBUG - Debug / Tuning view * 0b00..off * 0b01..non-filtered+texture * 0b10..non-filtered+black */ #define NR_CTRL_CAM_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << NR_CTRL_CAM_DEBUG_SHIFT)) & NR_CTRL_CAM_DEBUG_MASK) #define NR_CTRL_CAM_ENABLE_MASK (0x80000000U) #define NR_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..off * 0b1..on */ #define NR_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NR_CTRL_CAM_ENABLE_SHIFT)) & NR_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of NR_CTRL_CAM */ #define NR_CTRL_CAM_COUNT (1U) /*! @name BLEND_SCALE_CAM - Camera 0 NR Blending Scale Register */ /*! @{ */ #define NR_BLEND_SCALE_CAM_SCALE_MASK (0xFFFFU) #define NR_BLEND_SCALE_CAM_SCALE_SHIFT (0U) #define NR_BLEND_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << NR_BLEND_SCALE_CAM_SCALE_SHIFT)) & NR_BLEND_SCALE_CAM_SCALE_MASK) #define NR_BLEND_SCALE_CAM_SHIFT_MASK (0xFF0000U) #define NR_BLEND_SCALE_CAM_SHIFT_SHIFT (16U) #define NR_BLEND_SCALE_CAM_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << NR_BLEND_SCALE_CAM_SHIFT_SHIFT)) & NR_BLEND_SCALE_CAM_SHIFT_MASK) #define NR_BLEND_SCALE_CAM_GAIN_MASK (0xFF000000U) #define NR_BLEND_SCALE_CAM_GAIN_SHIFT (24U) #define NR_BLEND_SCALE_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << NR_BLEND_SCALE_CAM_GAIN_SHIFT)) & NR_BLEND_SCALE_CAM_GAIN_MASK) /*! @} */ /* The count of NR_BLEND_SCALE_CAM */ #define NR_BLEND_SCALE_CAM_COUNT (1U) /*! @name BLEND_TH0_CAM - Camera 0 NR Blend Threshold 0 Register */ /*! @{ */ #define NR_BLEND_TH0_CAM_TH_MASK (0xFFFFFU) #define NR_BLEND_TH0_CAM_TH_SHIFT (0U) #define NR_BLEND_TH0_CAM_TH(x) (((uint32_t)(((uint32_t)(x)) << NR_BLEND_TH0_CAM_TH_SHIFT)) & NR_BLEND_TH0_CAM_TH_MASK) /*! @} */ /* The count of NR_BLEND_TH0_CAM */ #define NR_BLEND_TH0_CAM_COUNT (1U) /*! @name EDGECNT_CAM - Camera 0 NR Edge Count Register */ /*! @{ */ #define NR_EDGECNT_CAM_EDGE_PIXELS_MASK (0xFFFFFFU) #define NR_EDGECNT_CAM_EDGE_PIXELS_SHIFT (0U) #define NR_EDGECNT_CAM_EDGE_PIXELS(x) (((uint32_t)(((uint32_t)(x)) << NR_EDGECNT_CAM_EDGE_PIXELS_SHIFT)) & NR_EDGECNT_CAM_EDGE_PIXELS_MASK) /*! @} */ /* The count of NR_EDGECNT_CAM */ #define NR_EDGECNT_CAM_COUNT (1U) /*! * @} */ /* end of group NR_Register_Masks */ /* NR - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__NR base address */ #define CAMERA__ISP__NR_BASE (0x4AE01400u) /** Peripheral CAMERA__ISP__NR base pointer */ #define CAMERA__ISP__NR ((NR_Type *)CAMERA__ISP__NR_BASE) /** Array initializer of NR peripheral base addresses */ #define NR_BASE_ADDRS { CAMERA__ISP__NR_BASE } /** Array initializer of NR peripheral base pointers */ #define NR_BASE_PTRS { CAMERA__ISP__NR } /*! * @} */ /* end of group NR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OB_WB0 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OB_WB0_Peripheral_Access_Layer OB_WB0 Peripheral Access Layer * @{ */ /** OB_WB0 - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x14 */ __IO uint32_t CTRL_CAM; /**< Camera 0 OB WB Control Register, array offset: 0x0, array step: 0x14 */ __IO uint32_t R_CTRL_CAM; /**< Camera 0 OB_WB Red Channel Control Register, array offset: 0x4, array step: 0x14 */ __IO uint32_t GR_CTRL_CAM; /**< Camera 0 OB_WB GreenR Channel Control Register, array offset: 0x8, array step: 0x14 */ __IO uint32_t GB_CTRL_CAM; /**< Camera 0 OB_WB GreenB Channel Control Register, array offset: 0xC, array step: 0x14 */ __IO uint32_t B_CTRL_CAM; /**< Camera 0 OB_WB Blue Channel Control Register, array offset: 0x10, array step: 0x14 */ } NEO_PIPE1_OB_WB_CONF[1]; } OB_WB0_Type; /* ---------------------------------------------------------------------------- -- OB_WB0 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OB_WB0_Register_Masks OB_WB0 Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 OB WB Control Register */ /*! @{ */ #define OB_WB0_CTRL_CAM_OBPP_MASK (0xCU) #define OB_WB0_CTRL_CAM_OBPP_SHIFT (2U) /*! OBPP * 0b00..12bpp * 0b01..14bpp * 0b10..16bpp * 0b11..20bpp */ #define OB_WB0_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_CTRL_CAM_OBPP_SHIFT)) & OB_WB0_CTRL_CAM_OBPP_MASK) /*! @} */ /* The count of OB_WB0_CTRL_CAM */ #define OB_WB0_CTRL_CAM_COUNT (1U) /*! @name R_CTRL_CAM - Camera 0 OB_WB Red Channel Control Register */ /*! @{ */ #define OB_WB0_R_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB0_R_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB0_R_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_R_CTRL_CAM_OFFSET_SHIFT)) & OB_WB0_R_CTRL_CAM_OFFSET_MASK) #define OB_WB0_R_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB0_R_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB0_R_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_R_CTRL_CAM_GAIN_SHIFT)) & OB_WB0_R_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB0_R_CTRL_CAM */ #define OB_WB0_R_CTRL_CAM_COUNT (1U) /*! @name GR_CTRL_CAM - Camera 0 OB_WB GreenR Channel Control Register */ /*! @{ */ #define OB_WB0_GR_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB0_GR_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB0_GR_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_GR_CTRL_CAM_OFFSET_SHIFT)) & OB_WB0_GR_CTRL_CAM_OFFSET_MASK) #define OB_WB0_GR_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB0_GR_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB0_GR_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_GR_CTRL_CAM_GAIN_SHIFT)) & OB_WB0_GR_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB0_GR_CTRL_CAM */ #define OB_WB0_GR_CTRL_CAM_COUNT (1U) /*! @name GB_CTRL_CAM - Camera 0 OB_WB GreenB Channel Control Register */ /*! @{ */ #define OB_WB0_GB_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB0_GB_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB0_GB_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_GB_CTRL_CAM_OFFSET_SHIFT)) & OB_WB0_GB_CTRL_CAM_OFFSET_MASK) #define OB_WB0_GB_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB0_GB_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB0_GB_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_GB_CTRL_CAM_GAIN_SHIFT)) & OB_WB0_GB_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB0_GB_CTRL_CAM */ #define OB_WB0_GB_CTRL_CAM_COUNT (1U) /*! @name B_CTRL_CAM - Camera 0 OB_WB Blue Channel Control Register */ /*! @{ */ #define OB_WB0_B_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB0_B_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB0_B_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_B_CTRL_CAM_OFFSET_SHIFT)) & OB_WB0_B_CTRL_CAM_OFFSET_MASK) #define OB_WB0_B_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB0_B_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB0_B_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB0_B_CTRL_CAM_GAIN_SHIFT)) & OB_WB0_B_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB0_B_CTRL_CAM */ #define OB_WB0_B_CTRL_CAM_COUNT (1U) /*! * @} */ /* end of group OB_WB0_Register_Masks */ /* OB_WB0 - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__OB_WB0 base address */ #define CAMERA__ISP__OB_WB0_BASE (0x4AE00200u) /** Peripheral CAMERA__ISP__OB_WB0 base pointer */ #define CAMERA__ISP__OB_WB0 ((OB_WB0_Type *)CAMERA__ISP__OB_WB0_BASE) /** Array initializer of OB_WB0 peripheral base addresses */ #define OB_WB0_BASE_ADDRS { CAMERA__ISP__OB_WB0_BASE } /** Array initializer of OB_WB0 peripheral base pointers */ #define OB_WB0_BASE_PTRS { CAMERA__ISP__OB_WB0 } /*! * @} */ /* end of group OB_WB0_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OB_WB1 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OB_WB1_Peripheral_Access_Layer OB_WB1 Peripheral Access Layer * @{ */ /** OB_WB1 - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x14 */ __IO uint32_t CTRL_CAM; /**< Camera 0 OB WB Control Register, array offset: 0x0, array step: 0x14 */ __IO uint32_t R_CTRL_CAM; /**< Camera 0 OB_WB Red Channel Control Register, array offset: 0x4, array step: 0x14 */ __IO uint32_t GR_CTRL_CAM; /**< Camera 0 OB_WB GreenR Channel Control Register, array offset: 0x8, array step: 0x14 */ __IO uint32_t GB_CTRL_CAM; /**< Camera 0 OB_WB GreenB Channel Control Register, array offset: 0xC, array step: 0x14 */ __IO uint32_t B_CTRL_CAM; /**< Camera 0 OB_WB Blue Channel Control Register, array offset: 0x10, array step: 0x14 */ } NEO_PIPE1_OB_WB_CONF[1]; } OB_WB1_Type; /* ---------------------------------------------------------------------------- -- OB_WB1 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OB_WB1_Register_Masks OB_WB1 Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 OB WB Control Register */ /*! @{ */ #define OB_WB1_CTRL_CAM_OBPP_MASK (0xCU) #define OB_WB1_CTRL_CAM_OBPP_SHIFT (2U) /*! OBPP * 0b00..12bpp * 0b01..14bpp * 0b10..16bpp */ #define OB_WB1_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_CTRL_CAM_OBPP_SHIFT)) & OB_WB1_CTRL_CAM_OBPP_MASK) /*! @} */ /* The count of OB_WB1_CTRL_CAM */ #define OB_WB1_CTRL_CAM_COUNT (1U) /*! @name R_CTRL_CAM - Camera 0 OB_WB Red Channel Control Register */ /*! @{ */ #define OB_WB1_R_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB1_R_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB1_R_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_R_CTRL_CAM_OFFSET_SHIFT)) & OB_WB1_R_CTRL_CAM_OFFSET_MASK) #define OB_WB1_R_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB1_R_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB1_R_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_R_CTRL_CAM_GAIN_SHIFT)) & OB_WB1_R_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB1_R_CTRL_CAM */ #define OB_WB1_R_CTRL_CAM_COUNT (1U) /*! @name GR_CTRL_CAM - Camera 0 OB_WB GreenR Channel Control Register */ /*! @{ */ #define OB_WB1_GR_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB1_GR_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB1_GR_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_GR_CTRL_CAM_OFFSET_SHIFT)) & OB_WB1_GR_CTRL_CAM_OFFSET_MASK) #define OB_WB1_GR_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB1_GR_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB1_GR_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_GR_CTRL_CAM_GAIN_SHIFT)) & OB_WB1_GR_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB1_GR_CTRL_CAM */ #define OB_WB1_GR_CTRL_CAM_COUNT (1U) /*! @name GB_CTRL_CAM - Camera 0 OB_WB GreenB Channel Control Register */ /*! @{ */ #define OB_WB1_GB_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB1_GB_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB1_GB_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_GB_CTRL_CAM_OFFSET_SHIFT)) & OB_WB1_GB_CTRL_CAM_OFFSET_MASK) #define OB_WB1_GB_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB1_GB_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB1_GB_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_GB_CTRL_CAM_GAIN_SHIFT)) & OB_WB1_GB_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB1_GB_CTRL_CAM */ #define OB_WB1_GB_CTRL_CAM_COUNT (1U) /*! @name B_CTRL_CAM - Camera 0 OB_WB Blue Channel Control Register */ /*! @{ */ #define OB_WB1_B_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB1_B_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB1_B_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_B_CTRL_CAM_OFFSET_SHIFT)) & OB_WB1_B_CTRL_CAM_OFFSET_MASK) #define OB_WB1_B_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB1_B_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB1_B_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB1_B_CTRL_CAM_GAIN_SHIFT)) & OB_WB1_B_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB1_B_CTRL_CAM */ #define OB_WB1_B_CTRL_CAM_COUNT (1U) /*! * @} */ /* end of group OB_WB1_Register_Masks */ /* OB_WB1 - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__OB_WB1 base address */ #define CAMERA__ISP__OB_WB1_BASE (0x4AE00240u) /** Peripheral CAMERA__ISP__OB_WB1 base pointer */ #define CAMERA__ISP__OB_WB1 ((OB_WB1_Type *)CAMERA__ISP__OB_WB1_BASE) /** Array initializer of OB_WB1 peripheral base addresses */ #define OB_WB1_BASE_ADDRS { CAMERA__ISP__OB_WB1_BASE } /** Array initializer of OB_WB1 peripheral base pointers */ #define OB_WB1_BASE_PTRS { CAMERA__ISP__OB_WB1 } /*! * @} */ /* end of group OB_WB1_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OB_WB2 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OB_WB2_Peripheral_Access_Layer OB_WB2 Peripheral Access Layer * @{ */ /** OB_WB2 - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x14 */ __IO uint32_t CTRL_CAM; /**< Camera 0 OB WB Control Register, array offset: 0x0, array step: 0x14 */ __IO uint32_t R_CTRL_CAM; /**< Camera 0 OB_WB Red Channel Control Register, array offset: 0x4, array step: 0x14 */ __IO uint32_t GR_CTRL_CAM; /**< Camera 0 OB_WB GreenR Channel Control Register, array offset: 0x8, array step: 0x14 */ __IO uint32_t GB_CTRL_CAM; /**< Camera 0 OB_WB GreenB Channel Control Register, array offset: 0xC, array step: 0x14 */ __IO uint32_t B_CTRL_CAM; /**< Camera 0 OB_WB Blue Channel Control Register, array offset: 0x10, array step: 0x14 */ } NEO_PIPE1_OB_WB_CONF[1]; } OB_WB2_Type; /* ---------------------------------------------------------------------------- -- OB_WB2 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OB_WB2_Register_Masks OB_WB2 Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 OB WB Control Register */ /*! @{ */ #define OB_WB2_CTRL_CAM_OBPP_MASK (0xCU) #define OB_WB2_CTRL_CAM_OBPP_SHIFT (2U) /*! OBPP * 0b00..12bpp * 0b01..14bpp * 0b10..16bpp * 0b11..20bpp */ #define OB_WB2_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_CTRL_CAM_OBPP_SHIFT)) & OB_WB2_CTRL_CAM_OBPP_MASK) /*! @} */ /* The count of OB_WB2_CTRL_CAM */ #define OB_WB2_CTRL_CAM_COUNT (1U) /*! @name R_CTRL_CAM - Camera 0 OB_WB Red Channel Control Register */ /*! @{ */ #define OB_WB2_R_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB2_R_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB2_R_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_R_CTRL_CAM_OFFSET_SHIFT)) & OB_WB2_R_CTRL_CAM_OFFSET_MASK) #define OB_WB2_R_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB2_R_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB2_R_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_R_CTRL_CAM_GAIN_SHIFT)) & OB_WB2_R_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB2_R_CTRL_CAM */ #define OB_WB2_R_CTRL_CAM_COUNT (1U) /*! @name GR_CTRL_CAM - Camera 0 OB_WB GreenR Channel Control Register */ /*! @{ */ #define OB_WB2_GR_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB2_GR_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB2_GR_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_GR_CTRL_CAM_OFFSET_SHIFT)) & OB_WB2_GR_CTRL_CAM_OFFSET_MASK) #define OB_WB2_GR_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB2_GR_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB2_GR_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_GR_CTRL_CAM_GAIN_SHIFT)) & OB_WB2_GR_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB2_GR_CTRL_CAM */ #define OB_WB2_GR_CTRL_CAM_COUNT (1U) /*! @name GB_CTRL_CAM - Camera 0 OB_WB GreenB Channel Control Register */ /*! @{ */ #define OB_WB2_GB_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB2_GB_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB2_GB_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_GB_CTRL_CAM_OFFSET_SHIFT)) & OB_WB2_GB_CTRL_CAM_OFFSET_MASK) #define OB_WB2_GB_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB2_GB_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB2_GB_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_GB_CTRL_CAM_GAIN_SHIFT)) & OB_WB2_GB_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB2_GB_CTRL_CAM */ #define OB_WB2_GB_CTRL_CAM_COUNT (1U) /*! @name B_CTRL_CAM - Camera 0 OB_WB Blue Channel Control Register */ /*! @{ */ #define OB_WB2_B_CTRL_CAM_OFFSET_MASK (0xFFFFU) #define OB_WB2_B_CTRL_CAM_OFFSET_SHIFT (0U) #define OB_WB2_B_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_B_CTRL_CAM_OFFSET_SHIFT)) & OB_WB2_B_CTRL_CAM_OFFSET_MASK) #define OB_WB2_B_CTRL_CAM_GAIN_MASK (0xFFFF0000U) #define OB_WB2_B_CTRL_CAM_GAIN_SHIFT (16U) #define OB_WB2_B_CTRL_CAM_GAIN(x) (((uint32_t)(((uint32_t)(x)) << OB_WB2_B_CTRL_CAM_GAIN_SHIFT)) & OB_WB2_B_CTRL_CAM_GAIN_MASK) /*! @} */ /* The count of OB_WB2_B_CTRL_CAM */ #define OB_WB2_B_CTRL_CAM_COUNT (1U) /*! * @} */ /* end of group OB_WB2_Register_Masks */ /* OB_WB2 - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__OB_WB2 base address */ #define CAMERA__ISP__OB_WB2_BASE (0x4AE00280u) /** Peripheral CAMERA__ISP__OB_WB2 base pointer */ #define CAMERA__ISP__OB_WB2 ((OB_WB2_Type *)CAMERA__ISP__OB_WB2_BASE) /** Array initializer of OB_WB2 peripheral base addresses */ #define OB_WB2_BASE_ADDRS { CAMERA__ISP__OB_WB2_BASE } /** Array initializer of OB_WB2 peripheral base pointers */ #define OB_WB2_BASE_PTRS { CAMERA__ISP__OB_WB2 } /*! * @} */ /* end of group OB_WB2_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PACKETIZER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PACKETIZER_Peripheral_Access_Layer PACKETIZER Peripheral Access Layer * @{ */ /** PACKETIZER - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0xC */ __IO uint32_t CH0_CTRL_CAM; /**< Camera 0 Channel 0 Control Register, array offset: 0x0, array step: 0xC */ __IO uint32_t CH12_CTRL_CAM; /**< Camera 0 Channel 1,2 Control Register, array offset: 0x4, array step: 0xC */ __IO uint32_t PACK_CTRL_CAM; /**< Camera 0 Pack Control Register, array offset: 0x8, array step: 0xC */ } NEO_PIPE2_PACK_CONF[1]; } PACKETIZER_Type; /* ---------------------------------------------------------------------------- -- PACKETIZER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PACKETIZER_Register_Masks PACKETIZER Register Masks * @{ */ /*! @name CH0_CTRL_CAM - Camera 0 Channel 0 Control Register */ /*! @{ */ #define PACKETIZER_CH0_CTRL_CAM_OBPP_MASK (0xFU) #define PACKETIZER_CH0_CTRL_CAM_OBPP_SHIFT (0U) /*! OBPP * 0b0000..12bpp * 0b0010..16bpp * 0b0100..10bpp * 0b0110..8bpp */ #define PACKETIZER_CH0_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_CH0_CTRL_CAM_OBPP_SHIFT)) & PACKETIZER_CH0_CTRL_CAM_OBPP_MASK) #define PACKETIZER_CH0_CTRL_CAM_RSA_MASK (0x700U) #define PACKETIZER_CH0_CTRL_CAM_RSA_SHIFT (8U) #define PACKETIZER_CH0_CTRL_CAM_RSA(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_CH0_CTRL_CAM_RSA_SHIFT)) & PACKETIZER_CH0_CTRL_CAM_RSA_MASK) #define PACKETIZER_CH0_CTRL_CAM_LSA_MASK (0x7000U) #define PACKETIZER_CH0_CTRL_CAM_LSA_SHIFT (12U) #define PACKETIZER_CH0_CTRL_CAM_LSA(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_CH0_CTRL_CAM_LSA_SHIFT)) & PACKETIZER_CH0_CTRL_CAM_LSA_MASK) /*! @} */ /* The count of PACKETIZER_CH0_CTRL_CAM */ #define PACKETIZER_CH0_CTRL_CAM_COUNT (1U) /*! @name CH12_CTRL_CAM - Camera 0 Channel 1,2 Control Register */ /*! @{ */ #define PACKETIZER_CH12_CTRL_CAM_OBPP_MASK (0xFU) #define PACKETIZER_CH12_CTRL_CAM_OBPP_SHIFT (0U) /*! OBPP * 0b0000..12bpp * 0b0010..16bpp - Should be set only for YUV Semiplanar storage type * 0b0100..10bpp * 0b0110..8bpp */ #define PACKETIZER_CH12_CTRL_CAM_OBPP(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_CH12_CTRL_CAM_OBPP_SHIFT)) & PACKETIZER_CH12_CTRL_CAM_OBPP_MASK) #define PACKETIZER_CH12_CTRL_CAM_RSA_MASK (0x700U) #define PACKETIZER_CH12_CTRL_CAM_RSA_SHIFT (8U) #define PACKETIZER_CH12_CTRL_CAM_RSA(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_CH12_CTRL_CAM_RSA_SHIFT)) & PACKETIZER_CH12_CTRL_CAM_RSA_MASK) #define PACKETIZER_CH12_CTRL_CAM_LSA_MASK (0x7000U) #define PACKETIZER_CH12_CTRL_CAM_LSA_SHIFT (12U) #define PACKETIZER_CH12_CTRL_CAM_LSA(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_CH12_CTRL_CAM_LSA_SHIFT)) & PACKETIZER_CH12_CTRL_CAM_LSA_MASK) #define PACKETIZER_CH12_CTRL_CAM_SUBSAMPLE_MASK (0x30000U) #define PACKETIZER_CH12_CTRL_CAM_SUBSAMPLE_SHIFT (16U) /*! SUBSAMPLE * 0b00..No subsample. For YUV444 storage. * 0b01..Horizontal subsampling. For YUV422 storage. * 0b10..Horizontal & vertical subsampling. For YUV420 storage. */ #define PACKETIZER_CH12_CTRL_CAM_SUBSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_CH12_CTRL_CAM_SUBSAMPLE_SHIFT)) & PACKETIZER_CH12_CTRL_CAM_SUBSAMPLE_MASK) /*! @} */ /* The count of PACKETIZER_CH12_CTRL_CAM */ #define PACKETIZER_CH12_CTRL_CAM_COUNT (1U) /*! @name PACK_CTRL_CAM - Camera 0 Pack Control Register */ /*! @{ */ #define PACKETIZER_PACK_CTRL_CAM_TYPE_MASK (0x1U) #define PACKETIZER_PACK_CTRL_CAM_TYPE_SHIFT (0U) /*! TYPE * 0b0..Semi-planar: Y as a separate plane, in memory location pointed by Y base address * 0b1..Interleaved: Y in same plane as UV, in memory location pointed by UV base address */ #define PACKETIZER_PACK_CTRL_CAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_PACK_CTRL_CAM_TYPE_SHIFT)) & PACKETIZER_PACK_CTRL_CAM_TYPE_MASK) #define PACKETIZER_PACK_CTRL_CAM_ORDER0_MASK (0x300U) #define PACKETIZER_PACK_CTRL_CAM_ORDER0_SHIFT (8U) #define PACKETIZER_PACK_CTRL_CAM_ORDER0(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_PACK_CTRL_CAM_ORDER0_SHIFT)) & PACKETIZER_PACK_CTRL_CAM_ORDER0_MASK) #define PACKETIZER_PACK_CTRL_CAM_ORDER1_MASK (0xC00U) #define PACKETIZER_PACK_CTRL_CAM_ORDER1_SHIFT (10U) #define PACKETIZER_PACK_CTRL_CAM_ORDER1(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_PACK_CTRL_CAM_ORDER1_SHIFT)) & PACKETIZER_PACK_CTRL_CAM_ORDER1_MASK) #define PACKETIZER_PACK_CTRL_CAM_ORDER2_MASK (0x3000U) #define PACKETIZER_PACK_CTRL_CAM_ORDER2_SHIFT (12U) #define PACKETIZER_PACK_CTRL_CAM_ORDER2(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_PACK_CTRL_CAM_ORDER2_SHIFT)) & PACKETIZER_PACK_CTRL_CAM_ORDER2_MASK) #define PACKETIZER_PACK_CTRL_CAM_A0S_MASK (0xF0000U) #define PACKETIZER_PACK_CTRL_CAM_A0S_SHIFT (16U) #define PACKETIZER_PACK_CTRL_CAM_A0S(x) (((uint32_t)(((uint32_t)(x)) << PACKETIZER_PACK_CTRL_CAM_A0S_SHIFT)) & PACKETIZER_PACK_CTRL_CAM_A0S_MASK) /*! @} */ /* The count of PACKETIZER_PACK_CTRL_CAM */ #define PACKETIZER_PACK_CTRL_CAM_COUNT (1U) /*! * @} */ /* end of group PACKETIZER_Register_Masks */ /* PACKETIZER - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__PACKETIZER base address */ #define CAMERA__ISP__PACKETIZER_BASE (0x4AE01580u) /** Peripheral CAMERA__ISP__PACKETIZER base pointer */ #define CAMERA__ISP__PACKETIZER ((PACKETIZER_Type *)CAMERA__ISP__PACKETIZER_BASE) /** Array initializer of PACKETIZER peripheral base addresses */ #define PACKETIZER_BASE_ADDRS { CAMERA__ISP__PACKETIZER_BASE } /** Array initializer of PACKETIZER peripheral base pointers */ #define PACKETIZER_BASE_PTRS { CAMERA__ISP__PACKETIZER } /*! * @} */ /* end of group PACKETIZER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCIE_DMA_IATU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_DMA_IATU_Peripheral_Access_Layer PCIE_DMA_IATU Peripheral Access Layer * @{ */ /** PCIE_DMA_IATU - Register Layout Typedef */ typedef struct { __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_0; /**< iATU Region Control 1 Register., offset: 0x0 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_0; /**< iATU Region Control 2 Register., offset: 0x4 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0; /**< iATU Lower Base Address Register., offset: 0x8 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0; /**< iATU Upper Base Address Register., offset: 0xC */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_0; /**< iATU Limit Address Register., offset: 0x10 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0; /**< iATU Lower Target Address Register., offset: 0x14 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0; /**< iATU Upper Target Address Register., offset: 0x18 */ uint8_t RESERVED_0[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0; /**< iATU Upper Limit Address Register., offset: 0x20 */ uint8_t RESERVED_1[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_0; /**< iATU Region Control 1 Register., offset: 0x100 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_0; /**< iATU Region Control 2 Register., offset: 0x104 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_0; /**< iATU Lower Base Address Register., offset: 0x108 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_0; /**< iATU Upper Base Address Register., offset: 0x10C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_0; /**< iATU Limit Address Register., offset: 0x110 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_0; /**< iATU Lower Target Address Register., offset: 0x114 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0; /**< iATU Upper Target Address Register., offset: 0x118 */ uint8_t RESERVED_2[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0; /**< iATU Upper Limit Address Register., offset: 0x120 */ uint8_t RESERVED_3[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_1; /**< iATU Region Control 1 Register., offset: 0x200 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_1; /**< iATU Region Control 2 Register., offset: 0x204 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1; /**< iATU Lower Base Address Register., offset: 0x208 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1; /**< iATU Upper Base Address Register., offset: 0x20C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_1; /**< iATU Limit Address Register., offset: 0x210 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1; /**< iATU Lower Target Address Register., offset: 0x214 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1; /**< iATU Upper Target Address Register., offset: 0x218 */ uint8_t RESERVED_4[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1; /**< iATU Upper Limit Address Register., offset: 0x220 */ uint8_t RESERVED_5[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_1; /**< iATU Region Control 1 Register., offset: 0x300 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_1; /**< iATU Region Control 2 Register., offset: 0x304 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_1; /**< iATU Lower Base Address Register., offset: 0x308 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_1; /**< iATU Upper Base Address Register., offset: 0x30C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_1; /**< iATU Limit Address Register., offset: 0x310 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_1; /**< iATU Lower Target Address Register., offset: 0x314 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1; /**< iATU Upper Target Address Register., offset: 0x318 */ uint8_t RESERVED_6[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1; /**< iATU Upper Limit Address Register., offset: 0x320 */ uint8_t RESERVED_7[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_2; /**< iATU Region Control 1 Register., offset: 0x400 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_2; /**< iATU Region Control 2 Register., offset: 0x404 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2; /**< iATU Lower Base Address Register., offset: 0x408 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2; /**< iATU Upper Base Address Register., offset: 0x40C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_2; /**< iATU Limit Address Register., offset: 0x410 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2; /**< iATU Lower Target Address Register., offset: 0x414 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2; /**< iATU Upper Target Address Register., offset: 0x418 */ uint8_t RESERVED_8[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2; /**< iATU Upper Limit Address Register., offset: 0x420 */ uint8_t RESERVED_9[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_2; /**< iATU Region Control 1 Register., offset: 0x500 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_2; /**< iATU Region Control 2 Register., offset: 0x504 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_2; /**< iATU Lower Base Address Register., offset: 0x508 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_2; /**< iATU Upper Base Address Register., offset: 0x50C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_2; /**< iATU Limit Address Register., offset: 0x510 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_2; /**< iATU Lower Target Address Register., offset: 0x514 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2; /**< iATU Upper Target Address Register., offset: 0x518 */ uint8_t RESERVED_10[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2; /**< iATU Upper Limit Address Register., offset: 0x520 */ uint8_t RESERVED_11[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_3; /**< iATU Region Control 1 Register., offset: 0x600 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_3; /**< iATU Region Control 2 Register., offset: 0x604 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3; /**< iATU Lower Base Address Register., offset: 0x608 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3; /**< iATU Upper Base Address Register., offset: 0x60C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_3; /**< iATU Limit Address Register., offset: 0x610 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3; /**< iATU Lower Target Address Register., offset: 0x614 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3; /**< iATU Upper Target Address Register., offset: 0x618 */ uint8_t RESERVED_12[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3; /**< iATU Upper Limit Address Register., offset: 0x620 */ uint8_t RESERVED_13[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_3; /**< iATU Region Control 1 Register., offset: 0x700 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_3; /**< iATU Region Control 2 Register., offset: 0x704 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_3; /**< iATU Lower Base Address Register., offset: 0x708 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_3; /**< iATU Upper Base Address Register., offset: 0x70C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_3; /**< iATU Limit Address Register., offset: 0x710 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_3; /**< iATU Lower Target Address Register., offset: 0x714 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3; /**< iATU Upper Target Address Register., offset: 0x718 */ uint8_t RESERVED_14[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3; /**< iATU Upper Limit Address Register., offset: 0x720 */ uint8_t RESERVED_15[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_4; /**< iATU Region Control 1 Register., offset: 0x800 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_4; /**< iATU Region Control 2 Register., offset: 0x804 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4; /**< iATU Lower Base Address Register., offset: 0x808 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4; /**< iATU Upper Base Address Register., offset: 0x80C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_4; /**< iATU Limit Address Register., offset: 0x810 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4; /**< iATU Lower Target Address Register., offset: 0x814 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4; /**< iATU Upper Target Address Register., offset: 0x818 */ uint8_t RESERVED_16[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4; /**< iATU Upper Limit Address Register., offset: 0x820 */ uint8_t RESERVED_17[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_4; /**< iATU Region Control 1 Register., offset: 0x900 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_4; /**< iATU Region Control 2 Register., offset: 0x904 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_4; /**< iATU Lower Base Address Register., offset: 0x908 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_4; /**< iATU Upper Base Address Register., offset: 0x90C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_4; /**< iATU Limit Address Register., offset: 0x910 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_4; /**< iATU Lower Target Address Register., offset: 0x914 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4; /**< iATU Upper Target Address Register., offset: 0x918 */ uint8_t RESERVED_18[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4; /**< iATU Upper Limit Address Register., offset: 0x920 */ uint8_t RESERVED_19[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_5; /**< iATU Region Control 1 Register., offset: 0xA00 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_5; /**< iATU Region Control 2 Register., offset: 0xA04 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5; /**< iATU Lower Base Address Register., offset: 0xA08 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5; /**< iATU Upper Base Address Register., offset: 0xA0C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_5; /**< iATU Limit Address Register., offset: 0xA10 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5; /**< iATU Lower Target Address Register., offset: 0xA14 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5; /**< iATU Upper Target Address Register., offset: 0xA18 */ uint8_t RESERVED_20[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5; /**< iATU Upper Limit Address Register., offset: 0xA20 */ uint8_t RESERVED_21[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_5; /**< iATU Region Control 1 Register., offset: 0xB00 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_5; /**< iATU Region Control 2 Register., offset: 0xB04 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_5; /**< iATU Lower Base Address Register., offset: 0xB08 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_5; /**< iATU Upper Base Address Register., offset: 0xB0C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_5; /**< iATU Limit Address Register., offset: 0xB10 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_5; /**< iATU Lower Target Address Register., offset: 0xB14 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5; /**< iATU Upper Target Address Register., offset: 0xB18 */ uint8_t RESERVED_22[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5; /**< iATU Upper Limit Address Register., offset: 0xB20 */ uint8_t RESERVED_23[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_6; /**< iATU Region Control 1 Register., offset: 0xC00 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_6; /**< iATU Region Control 2 Register., offset: 0xC04 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6; /**< iATU Lower Base Address Register., offset: 0xC08 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6; /**< iATU Upper Base Address Register., offset: 0xC0C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_6; /**< iATU Limit Address Register., offset: 0xC10 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6; /**< iATU Lower Target Address Register., offset: 0xC14 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6; /**< iATU Upper Target Address Register., offset: 0xC18 */ uint8_t RESERVED_24[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6; /**< iATU Upper Limit Address Register., offset: 0xC20 */ uint8_t RESERVED_25[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_6; /**< iATU Region Control 1 Register., offset: 0xD00 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_6; /**< iATU Region Control 2 Register., offset: 0xD04 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_6; /**< iATU Lower Base Address Register., offset: 0xD08 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_6; /**< iATU Upper Base Address Register., offset: 0xD0C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_6; /**< iATU Limit Address Register., offset: 0xD10 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_6; /**< iATU Lower Target Address Register., offset: 0xD14 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6; /**< iATU Upper Target Address Register., offset: 0xD18 */ uint8_t RESERVED_26[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6; /**< iATU Upper Limit Address Register., offset: 0xD20 */ uint8_t RESERVED_27[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_7; /**< iATU Region Control 1 Register., offset: 0xE00 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_7; /**< iATU Region Control 2 Register., offset: 0xE04 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7; /**< iATU Lower Base Address Register., offset: 0xE08 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7; /**< iATU Upper Base Address Register., offset: 0xE0C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_7; /**< iATU Limit Address Register., offset: 0xE10 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7; /**< iATU Lower Target Address Register., offset: 0xE14 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7; /**< iATU Upper Target Address Register., offset: 0xE18 */ uint8_t RESERVED_28[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7; /**< iATU Upper Limit Address Register., offset: 0xE20 */ uint8_t RESERVED_29[220]; __IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_7; /**< iATU Region Control 1 Register., offset: 0xF00 */ __IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_7; /**< iATU Region Control 2 Register., offset: 0xF04 */ __IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_7; /**< iATU Lower Base Address Register., offset: 0xF08 */ __IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_7; /**< iATU Upper Base Address Register., offset: 0xF0C */ __IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_7; /**< iATU Limit Address Register., offset: 0xF10 */ __IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_7; /**< iATU Lower Target Address Register., offset: 0xF14 */ __IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7; /**< iATU Upper Target Address Register., offset: 0xF18 */ uint8_t RESERVED_30[4]; __IO uint32_t IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7; /**< iATU Upper Limit Address Register., offset: 0xF20 */ uint8_t RESERVED_31[61660]; __IO uint32_t DMA_CTRL_DATA_ARB_PRIOR_OFF; /**< DMA Arbitration Scheme for TRGT1 Interface., offset: 0x10000 */ uint8_t RESERVED_32[4]; __IO uint32_t DMA_CTRL_OFF; /**< DMA Number of Channels Register., offset: 0x10008 */ __IO uint32_t DMA_WRITE_ENGINE_EN_OFF; /**< DMA Write Engine Enable Register., offset: 0x1000C */ __IO uint32_t DMA_WRITE_DOORBELL_OFF; /**< DMA Write Doorbell Register., offset: 0x10010 */ uint8_t RESERVED_33[4]; __IO uint32_t DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF; /**< DMA Write Engine Channel Arbitration Weight Low Register., offset: 0x10018 */ uint8_t RESERVED_34[16]; __IO uint32_t DMA_READ_ENGINE_EN_OFF; /**< DMA Read Engine Enable Register., offset: 0x1002C */ __IO uint32_t DMA_READ_DOORBELL_OFF; /**< DMA Read Doorbell Register., offset: 0x10030 */ uint8_t RESERVED_35[4]; __IO uint32_t DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF; /**< DMA Read Engine Channel Arbitration Weight Low Register., offset: 0x10038 */ uint8_t RESERVED_36[16]; __IO uint32_t DMA_WRITE_INT_STATUS_OFF; /**< DMA Write Interrupt Status Register., offset: 0x1004C */ uint8_t RESERVED_37[4]; __IO uint32_t DMA_WRITE_INT_MASK_OFF; /**< DMA Write Interrupt Mask Register., offset: 0x10054 */ __O uint32_t DMA_WRITE_INT_CLEAR_OFF; /**< DMA Write Interrupt Clear Register., offset: 0x10058 */ __I uint32_t DMA_WRITE_ERR_STATUS_OFF; /**< DMA Write Error Status Register., offset: 0x1005C */ __IO uint32_t DMA_WRITE_DONE_IMWR_LOW_OFF; /**< DMA Write Done IMWr Address Low Register., offset: 0x10060 */ __IO uint32_t DMA_WRITE_DONE_IMWR_HIGH_OFF; /**< DMA Write Done IMWr Interrupt Address High Register., offset: 0x10064 */ __IO uint32_t DMA_WRITE_ABORT_IMWR_LOW_OFF; /**< DMA Write Abort IMWr Address Low Register., offset: 0x10068 */ __IO uint32_t DMA_WRITE_ABORT_IMWR_HIGH_OFF; /**< DMA Write Abort IMWr Address High Register., offset: 0x1006C */ __IO uint32_t DMA_WRITE_CH01_IMWR_DATA_OFF; /**< DMA Write Channel 1 and 0 IMWr Data Register., offset: 0x10070 */ __IO uint32_t DMA_WRITE_CH23_IMWR_DATA_OFF; /**< DMA Write Channel 3 and 2 IMWr Data Register., offset: 0x10074 */ uint8_t RESERVED_38[24]; __IO uint32_t DMA_WRITE_LINKED_LIST_ERR_EN_OFF; /**< DMA Write Linked List Error Enable Register., offset: 0x10090 */ uint8_t RESERVED_39[12]; __IO uint32_t DMA_READ_INT_STATUS_OFF; /**< DMA Read Interrupt Status Register., offset: 0x100A0 */ uint8_t RESERVED_40[4]; __IO uint32_t DMA_READ_INT_MASK_OFF; /**< DMA Read Interrupt Mask Register., offset: 0x100A8 */ __O uint32_t DMA_READ_INT_CLEAR_OFF; /**< DMA Read Interrupt Clear Register., offset: 0x100AC */ uint8_t RESERVED_41[4]; __I uint32_t DMA_READ_ERR_STATUS_LOW_OFF; /**< DMA Read Error Status Low Register., offset: 0x100B4 */ __I uint32_t DMA_READ_ERR_STATUS_HIGH_OFF; /**< DMA Read Error Status High Register., offset: 0x100B8 */ uint8_t RESERVED_42[8]; __IO uint32_t DMA_READ_LINKED_LIST_ERR_EN_OFF; /**< DMA Read Linked List Error Enable Register., offset: 0x100C4 */ uint8_t RESERVED_43[4]; __IO uint32_t DMA_READ_DONE_IMWR_LOW_OFF; /**< DMA Read Done IMWr Address Low Register., offset: 0x100CC */ __IO uint32_t DMA_READ_DONE_IMWR_HIGH_OFF; /**< DMA Read Done IMWr Address High Register., offset: 0x100D0 */ __IO uint32_t DMA_READ_ABORT_IMWR_LOW_OFF; /**< DMA Read Abort IMWr Address Low Register., offset: 0x100D4 */ __IO uint32_t DMA_READ_ABORT_IMWR_HIGH_OFF; /**< DMA Read Abort IMWr Address High Register., offset: 0x100D8 */ __IO uint32_t DMA_READ_CH01_IMWR_DATA_OFF; /**< DMA Read Channel 1 and 0 IMWr Data Register., offset: 0x100DC */ __IO uint32_t DMA_READ_CH23_IMWR_DATA_OFF; /**< DMA Read Channel 3 and 2 IMWr Data Register., offset: 0x100E0 */ uint8_t RESERVED_44[36]; __I uint32_t DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF; /**< DMA Write Engine Handshake Counter Channel 0/1/2/3 Register., offset: 0x10108 */ uint8_t RESERVED_45[12]; __I uint32_t DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF; /**< DMA Read Engine Handshake Counter Channel 0/1/2/3 Register., offset: 0x10118 */ uint8_t RESERVED_46[12]; __IO uint32_t DMA_WRITE_CH0_PWR_EN_OFF; /**< DMA Write Channel 0 Power Enable Register., offset: 0x10128 */ __IO uint32_t DMA_WRITE_CH1_PWR_EN_OFF; /**< DMA Write Channel 1 Power Enable Register., offset: 0x1012C */ __IO uint32_t DMA_WRITE_CH2_PWR_EN_OFF; /**< DMA Write Channel 2 Power Enable Register., offset: 0x10130 */ __IO uint32_t DMA_WRITE_CH3_PWR_EN_OFF; /**< DMA Write Channel 3 Power Enable Register., offset: 0x10134 */ uint8_t RESERVED_47[48]; __IO uint32_t DMA_READ_CH0_PWR_EN_OFF; /**< DMA Read Channel 0 Power Enable Register., offset: 0x10168 */ __IO uint32_t DMA_READ_CH1_PWR_EN_OFF; /**< DMA Read Channel 1 Power Enable Register., offset: 0x1016C */ __IO uint32_t DMA_READ_CH2_PWR_EN_OFF; /**< DMA Read Channel 2 Power Enable Register., offset: 0x10170 */ __IO uint32_t DMA_READ_CH3_PWR_EN_OFF; /**< DMA Read Channel 3 Power Enable Register., offset: 0x10174 */ uint8_t RESERVED_48[136]; __IO uint32_t DMA_CH_CONTROL1_OFF_WRCH_0; /**< DMA Write Channel Control 1 Register., offset: 0x10200 */ uint8_t RESERVED_49[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_WRCH_0; /**< DMA Write Transfer Size Register., offset: 0x10208 */ __IO uint32_t DMA_SAR_LOW_OFF_WRCH_0; /**< DMA Write SAR Low Register., offset: 0x1020C */ __IO uint32_t DMA_SAR_HIGH_OFF_WRCH_0; /**< DMA Write SAR High Register., offset: 0x10210 */ __IO uint32_t DMA_DAR_LOW_OFF_WRCH_0; /**< DMA Write DAR Low Register., offset: 0x10214 */ __IO uint32_t DMA_DAR_HIGH_OFF_WRCH_0; /**< DMA Write DAR High Register., offset: 0x10218 */ __IO uint32_t DMA_LLP_LOW_OFF_WRCH_0; /**< DMA Write Linked List Pointer Low Register., offset: 0x1021C */ __IO uint32_t DMA_LLP_HIGH_OFF_WRCH_0; /**< DMA Write Linked List Pointer High Register., offset: 0x10220 */ uint8_t RESERVED_50[220]; __IO uint32_t DMA_CH_CONTROL1_OFF_RDCH_0; /**< DMA Read Channel Control 1 Register., offset: 0x10300 */ uint8_t RESERVED_51[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_RDCH_0; /**< DMA Read Transfer Size Register., offset: 0x10308 */ __IO uint32_t DMA_SAR_LOW_OFF_RDCH_0; /**< DMA Read SAR Low Register., offset: 0x1030C */ __IO uint32_t DMA_SAR_HIGH_OFF_RDCH_0; /**< DMA Read SAR High Register., offset: 0x10310 */ __IO uint32_t DMA_DAR_LOW_OFF_RDCH_0; /**< DMA Read DAR Low Register., offset: 0x10314 */ __IO uint32_t DMA_DAR_HIGH_OFF_RDCH_0; /**< DMA Read DAR High Register., offset: 0x10318 */ __IO uint32_t DMA_LLP_LOW_OFF_RDCH_0; /**< DMA Read Linked List Pointer Low Register., offset: 0x1031C */ __IO uint32_t DMA_LLP_HIGH_OFF_RDCH_0; /**< DMA Read Linked List Pointer High Register., offset: 0x10320 */ uint8_t RESERVED_52[220]; __IO uint32_t DMA_CH_CONTROL1_OFF_WRCH_1; /**< DMA Write Channel Control 1 Register., offset: 0x10400 */ uint8_t RESERVED_53[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_WRCH_1; /**< DMA Write Transfer Size Register., offset: 0x10408 */ __IO uint32_t DMA_SAR_LOW_OFF_WRCH_1; /**< DMA Write SAR Low Register., offset: 0x1040C */ __IO uint32_t DMA_SAR_HIGH_OFF_WRCH_1; /**< DMA Write SAR High Register., offset: 0x10410 */ __IO uint32_t DMA_DAR_LOW_OFF_WRCH_1; /**< DMA Write DAR Low Register., offset: 0x10414 */ __IO uint32_t DMA_DAR_HIGH_OFF_WRCH_1; /**< DMA Write DAR High Register., offset: 0x10418 */ __IO uint32_t DMA_LLP_LOW_OFF_WRCH_1; /**< DMA Write Linked List Pointer Low Register., offset: 0x1041C */ __IO uint32_t DMA_LLP_HIGH_OFF_WRCH_1; /**< DMA Write Linked List Pointer High Register., offset: 0x10420 */ uint8_t RESERVED_54[220]; __IO uint32_t DMA_CH_CONTROL1_OFF_RDCH_1; /**< DMA Read Channel Control 1 Register., offset: 0x10500 */ uint8_t RESERVED_55[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_RDCH_1; /**< DMA Read Transfer Size Register., offset: 0x10508 */ __IO uint32_t DMA_SAR_LOW_OFF_RDCH_1; /**< DMA Read SAR Low Register., offset: 0x1050C */ __IO uint32_t DMA_SAR_HIGH_OFF_RDCH_1; /**< DMA Read SAR High Register., offset: 0x10510 */ __IO uint32_t DMA_DAR_LOW_OFF_RDCH_1; /**< DMA Read DAR Low Register., offset: 0x10514 */ __IO uint32_t DMA_DAR_HIGH_OFF_RDCH_1; /**< DMA Read DAR High Register., offset: 0x10518 */ __IO uint32_t DMA_LLP_LOW_OFF_RDCH_1; /**< DMA Read Linked List Pointer Low Register., offset: 0x1051C */ __IO uint32_t DMA_LLP_HIGH_OFF_RDCH_1; /**< DMA Read Linked List Pointer High Register., offset: 0x10520 */ uint8_t RESERVED_56[220]; __IO uint32_t DMA_CH_CONTROL1_OFF_WRCH_2; /**< DMA Write Channel Control 1 Register., offset: 0x10600 */ uint8_t RESERVED_57[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_WRCH_2; /**< DMA Write Transfer Size Register., offset: 0x10608 */ __IO uint32_t DMA_SAR_LOW_OFF_WRCH_2; /**< DMA Write SAR Low Register., offset: 0x1060C */ __IO uint32_t DMA_SAR_HIGH_OFF_WRCH_2; /**< DMA Write SAR High Register., offset: 0x10610 */ __IO uint32_t DMA_DAR_LOW_OFF_WRCH_2; /**< DMA Write DAR Low Register., offset: 0x10614 */ __IO uint32_t DMA_DAR_HIGH_OFF_WRCH_2; /**< DMA Write DAR High Register., offset: 0x10618 */ __IO uint32_t DMA_LLP_LOW_OFF_WRCH_2; /**< DMA Write Linked List Pointer Low Register., offset: 0x1061C */ __IO uint32_t DMA_LLP_HIGH_OFF_WRCH_2; /**< DMA Write Linked List Pointer High Register., offset: 0x10620 */ uint8_t RESERVED_58[220]; __IO uint32_t DMA_CH_CONTROL1_OFF_RDCH_2; /**< DMA Read Channel Control 1 Register., offset: 0x10700 */ uint8_t RESERVED_59[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_RDCH_2; /**< DMA Read Transfer Size Register., offset: 0x10708 */ __IO uint32_t DMA_SAR_LOW_OFF_RDCH_2; /**< DMA Read SAR Low Register., offset: 0x1070C */ __IO uint32_t DMA_SAR_HIGH_OFF_RDCH_2; /**< DMA Read SAR High Register., offset: 0x10710 */ __IO uint32_t DMA_DAR_LOW_OFF_RDCH_2; /**< DMA Read DAR Low Register., offset: 0x10714 */ __IO uint32_t DMA_DAR_HIGH_OFF_RDCH_2; /**< DMA Read DAR High Register., offset: 0x10718 */ __IO uint32_t DMA_LLP_LOW_OFF_RDCH_2; /**< DMA Read Linked List Pointer Low Register., offset: 0x1071C */ __IO uint32_t DMA_LLP_HIGH_OFF_RDCH_2; /**< DMA Read Linked List Pointer High Register., offset: 0x10720 */ uint8_t RESERVED_60[220]; __IO uint32_t DMA_CH_CONTROL1_OFF_WRCH_3; /**< DMA Write Channel Control 1 Register., offset: 0x10800 */ uint8_t RESERVED_61[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_WRCH_3; /**< DMA Write Transfer Size Register., offset: 0x10808 */ __IO uint32_t DMA_SAR_LOW_OFF_WRCH_3; /**< DMA Write SAR Low Register., offset: 0x1080C */ __IO uint32_t DMA_SAR_HIGH_OFF_WRCH_3; /**< DMA Write SAR High Register., offset: 0x10810 */ __IO uint32_t DMA_DAR_LOW_OFF_WRCH_3; /**< DMA Write DAR Low Register., offset: 0x10814 */ __IO uint32_t DMA_DAR_HIGH_OFF_WRCH_3; /**< DMA Write DAR High Register., offset: 0x10818 */ __IO uint32_t DMA_LLP_LOW_OFF_WRCH_3; /**< DMA Write Linked List Pointer Low Register., offset: 0x1081C */ __IO uint32_t DMA_LLP_HIGH_OFF_WRCH_3; /**< DMA Write Linked List Pointer High Register., offset: 0x10820 */ uint8_t RESERVED_62[220]; __IO uint32_t DMA_CH_CONTROL1_OFF_RDCH_3; /**< DMA Read Channel Control 1 Register., offset: 0x10900 */ uint8_t RESERVED_63[4]; __IO uint32_t DMA_TRANSFER_SIZE_OFF_RDCH_3; /**< DMA Read Transfer Size Register., offset: 0x10908 */ __IO uint32_t DMA_SAR_LOW_OFF_RDCH_3; /**< DMA Read SAR Low Register., offset: 0x1090C */ __IO uint32_t DMA_SAR_HIGH_OFF_RDCH_3; /**< DMA Read SAR High Register., offset: 0x10910 */ __IO uint32_t DMA_DAR_LOW_OFF_RDCH_3; /**< DMA Read DAR Low Register., offset: 0x10914 */ __IO uint32_t DMA_DAR_HIGH_OFF_RDCH_3; /**< DMA Read DAR High Register., offset: 0x10918 */ __IO uint32_t DMA_LLP_LOW_OFF_RDCH_3; /**< DMA Read Linked List Pointer Low Register., offset: 0x1091C */ __IO uint32_t DMA_LLP_HIGH_OFF_RDCH_3; /**< DMA Read Linked List Pointer High Register., offset: 0x10920 */ } PCIE_DMA_IATU_Type; /* ---------------------------------------------------------------------------- -- PCIE_DMA_IATU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_DMA_IATU_Register_Masks PCIE_DMA_IATU Register Masks * @{ */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_0 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_0 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_0 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_0 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_0 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_0 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_0 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_0 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_0_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_0_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_1 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_1 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_1 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_1_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_1 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_1 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_1 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_1 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_1 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_1 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_1_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_1_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_2 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_2 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_2 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_2_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_2 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_2 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_2 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_2 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_2 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_2 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_2_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_2_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_3 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is determined by 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_3 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_3 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_3_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_3 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is determined by 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_3 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_3 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_3 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_3 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_3 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_3_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_3_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_4 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_4_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_4 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_4_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_4_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_4_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_4 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_4_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_4_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_4_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_4_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_4 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_4_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_4 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_4_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_4 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_4_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_4 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_4_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_4 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_4_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_4 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_4_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_4_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_4_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_5 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_5_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_5 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_5_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_5_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_5_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_5 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_5_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_5_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_5_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_5_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_5 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_5_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_5 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_5_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_5 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_5_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_5 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_5_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_5 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_5_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_5 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_5_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_5_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_5_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_6 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_6_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_6 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_6_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_6_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_6_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_6 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_6_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_6_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_6_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_6_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_6 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_6_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_6 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_6_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_6 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_6_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_6 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_6_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_6 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_6_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_6 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_6_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_6_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_6_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_7 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SHIFT (0U) /*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SHIFT (5U) /*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP * is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SHIFT (8U) /*! TD - This is a reserved field. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SHIFT (9U) /*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the * TLP is changed to the value in this register. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_OUTBOUND_7_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_7 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MASK (0xFF00U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SHIFT (8U) /*! TAG - TAG. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SHIFT (16U) /*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TAG_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SHIFT (19U) /*! FUNC_BYPASS - Function Number Translation Bypass. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_FUNC_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MASK (0x100000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SHIFT (20U) /*! SNP - Serialize Non-Posted Requests. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_SNP_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SHIFT (21U) /*! TLP_HEADER_FIELDS_BYPASS - TLP Header Fields Translation Bypass. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_TLP_HEADER_FIELDS_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MASK (0x400000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SHIFT (22U) /*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. * 0b1..Fmt[1] =0 so that only TLP type without data is sent. For example, a Msg instead of MsgD will be sent. * 0b0..Fmt[1] =0/1 so that TLPs with or without data can be sent. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INHIBIT_PAYLOAD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SHIFT (23U) /*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. * 0b1..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used to fill bytes 8-to-11 (for 3 * DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the translated TLP header. * 0b0..LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register forms the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_HEADER_SUBSTITUTE_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SHIFT (27U) /*! DMA_BYPASS - DMA Bypass Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_DMA_BYPASS_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Mode. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_OUTBOUND_7_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_7_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_7_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_7 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_OUTBOUND_7_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SHIFT (0U) /*! LWR_TARGET_RW_OUTBOUND - LWR_TARGET_RW_OUTBOUND */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_7_LWR_TARGET_RW_OUTBOUND_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_7_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_7_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_1_OFF_INBOUND_7 - iATU Region Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MASK (0x1FU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SHIFT (0U) /*! TYPE - TYPE */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TYPE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MASK (0xE0U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SHIFT (5U) /*! TC - TC */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TC_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MASK (0x100U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SHIFT (8U) /*! TD - TD */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_TD_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MASK (0x600U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SHIFT (9U) /*! ATTR - ATTR */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_ATTR_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SHIFT (13U) /*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. * 0b0..Maximum ATU Region size is 4 GB (default) * 0b1..Maximum ATU Region size is 1TB */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_INCREASE_REGION_SIZE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MASK (0x700000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SHIFT (20U) /*! CTRL_1_FUNC_NUM - Function Number. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_1_OFF_INBOUND_7_CTRL_1_FUNC_NUM_MASK) /*! @} */ /*! @name IATU_REGION_CTRL_2_OFF_INBOUND_7 - iATU Region Control 2 Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SHIFT (0U) /*! MSG_CODE - MSG TLPs: (Message Code). */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MASK (0x700U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SHIFT (8U) /*! BAR_NUM - BAR Number. * 0b000..BAR0 * 0b001..BAR1 * 0b010..BAR2 * 0b011..BAR3 * 0b100..BAR4 * 0b101..BAR5 * 0b110..ROM * 0b111..reserved */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_BAR_NUM_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MASK (0x2000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SHIFT (13U) /*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_TYPE_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MASK (0x4000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SHIFT (14U) /*! TC_MATCH_EN - TC Match Enable. * 0b0..TC Match Disable * 0b1..TC Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TC_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MASK (0x8000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SHIFT (15U) /*! TD_MATCH_EN - TD Match Enable. * 0b0..TD Match Disable * 0b1..TD Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_TD_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MASK (0x10000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SHIFT (16U) /*! ATTR_MATCH_EN - ATTR Match Enable. * 0b0..ATTR Match Disable * 0b1..ATTR Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_ATTR_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MASK (0x80000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SHIFT (19U) /*! FUNC_NUM_MATCH_EN - Function Number Match Enable. * 0b0..Function Number Match Disable * 0b1..Function Number Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUNC_NUM_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MASK (0x200000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SHIFT (21U) /*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). * 0b0..Virtual Function Number Match Disable * 0b1..Message Code Match Enable (for Msg TLPS) or ST Match Enable (for Mem TLPs) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MSG_CODE_MATCH_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U) /*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_SINGLE_ADDR_LOC_TRANS_EN_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MASK (0x3000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SHIFT (24U) /*! RESPONSE_CODE - Response Code. * 0b10..Completer abort (CA) * 0b00..Normal RADM filter response is used. * 0b11..Not used / undefined / reserved * 0b01..Unsupported request (UR) */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_RESPONSE_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SHIFT (27U) /*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Enable. * 0b0..Fuzzy Type Match Disable * 0b1..Fuzzy Type Match Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_FUZZY_TYPE_MATCH_CODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MASK (0x10000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SHIFT (28U) /*! CFG_SHIFT_MODE - CFG Shift Enable. * 0b0..CFG Shift Disable * 0b1..CFG Shift Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_CFG_SHIFT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MASK (0x20000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SHIFT (29U) /*! INVERT_MODE - Invert Mode Enable. * 0b0..Invert Mode Disable * 0b1..Invert Mode Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_INVERT_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MASK (0x40000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SHIFT (30U) /*! MATCH_MODE - Match Mode. * 0b1..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. * 0b0..The interpretation is dependent on TLP type, that is, MEM/IO, CFG0, or MSG/MSGD TLPs. */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_MATCH_MODE_MASK) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MASK (0x80000000U) #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SHIFT (31U) /*! REGION_EN - Region Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_SHIFT)) & PCIE_DMA_IATU_IATU_REGION_CTRL_2_OFF_INBOUND_7_REGION_EN_MASK) /*! @} */ /*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_7 - iATU Lower Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SHIFT (0U) /*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SHIFT (12U) /*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_BASE_ADDR_OFF_INBOUND_7_LWR_BASE_RW_MASK) /*! @} */ /*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_7 - iATU Upper Base Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SHIFT (0U) /*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_BASE_ADDR_OFF_INBOUND_7_UPPER_BASE_RW_MASK) /*! @} */ /*! @name IATU_LIMIT_ADDR_OFF_INBOUND_7 - iATU Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_CBUF_INCR_MASK (0xFU) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_CBUF_INCR_SHIFT (0U) /*! CBUF_INCR - Circular Buffer Increment. * 0b0000..0 (Default; legacy Single Address Location mode) * 0b1001..1024 * 0b0110..128 * 0b0011..16 * 0b1010..2048 * 0b0111..256 * 0b0100..32 * 0b0001..4 * 0b1011..4096 * 0b1000..512 * 0b0101..64 * 0b0010..8 * 0b1100..8192 * 0b1101..rsvd. * 0b1110..rsvd. * 0b1111..rsvd. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_CBUF_INCR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_CBUF_INCR_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_CBUF_INCR_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MASK (0xFF0U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SHIFT (4U) /*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_HW_MASK) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SHIFT (12U) /*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. */ #define PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LIMIT_ADDR_OFF_INBOUND_7_LIMIT_ADDR_RW_MASK) /*! @} */ /*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_7 - iATU Lower Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MASK (0xFFFU) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SHIFT (0U) /*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_HW_MASK) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MASK (0xFFFFF000U) #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SHIFT (12U) /*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_LWR_TARGET_ADDR_OFF_INBOUND_7_LWR_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7 - iATU Upper Target Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SHIFT (0U) /*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. */ #define PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPER_TARGET_ADDR_OFF_INBOUND_7_UPPER_TARGET_RW_MASK) /*! @} */ /*! @name IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7 - iATU Upper Limit Address Register. */ /*! @{ */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MASK (0xFFU) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SHIFT (0U) /*! UPPR_LIMIT_ADDR_RW - Forms the LSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_RW_MASK) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MASK (0xFFFFFF00U) #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SHIFT (8U) /*! UPPR_LIMIT_ADDR_HW - Forms MSB's of the Upper Limit part of the region "end address" to be translated. */ #define PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_SHIFT)) & PCIE_DMA_IATU_IATU_UPPR_LIMIT_ADDR_OFF_INBOUND_7_UPPR_LIMIT_ADDR_HW_MASK) /*! @} */ /*! @name DMA_CTRL_DATA_ARB_PRIOR_OFF - DMA Arbitration Scheme for TRGT1 Interface. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MASK (0x7U) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SHIFT (0U) /*! RTRGT1_WEIGHT - Non-DMA Rx Requests. */ #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MASK (0x38U) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SHIFT (3U) /*! WR_CTRL_TRGT_WEIGHT - DMA Write Channel MRd Requests (for DMA data requests and LL element/descriptor access). */ #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MASK (0x1C0U) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SHIFT (6U) /*! RD_CTRL_TRGT_WEIGHT - DMA Read Channel MRd Requests (for LL element/descriptor access). */ #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MASK (0xE00U) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SHIFT (9U) /*! RDBUFF_TRGT_WEIGHT - DMA Read Channel MWr Requests. */ #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_VERSION_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_VERSION_SHIFT (12U) /*! VERSION - Reports the version of Register Map of eDMA. */ #define PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_VERSION_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_DATA_ARB_PRIOR_OFF_VERSION_MASK) /*! @} */ /*! @name DMA_CTRL_OFF - DMA Number of Channels Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MASK (0xFU) #define PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SHIFT (0U) /*! NUM_DMA_WR_CHAN - Number of Write Channels. */ #define PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_WR_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MASK) #define PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SHIFT (16U) /*! NUM_DMA_RD_CHAN - Number of Read Channels. */ #define PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_RD_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MASK) #define PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SHIFT (24U) /*! DIS_C2W_CACHE_WR - Disable DMA Write Channel's "completion to memory write" context cache pre-fetch function. */ #define PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_WR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MASK) #define PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SHIFT (25U) /*! DIS_C2W_CACHE_RD - Disable DMA Read Channel's "completion to memory write" context cache pre-fetch function. */ #define PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_RD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SHIFT)) & PCIE_DMA_IATU_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MASK) /*! @} */ /*! @name DMA_WRITE_ENGINE_EN_OFF - DMA Write Engine Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MASK (0x1U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SHIFT (0U) /*! DMA_WRITE_ENGINE - DMA Write Engine Enable. * 0b0..Disable (Soft Reset) * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MASK (0x10000U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SHIFT (16U) /*! DMA_WRITE_ENGINE_EN_HSHAKE_CH0 - Enable Handshake for DMA Write Engine Channel 0. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH0_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MASK (0x20000U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SHIFT (17U) /*! DMA_WRITE_ENGINE_EN_HSHAKE_CH1 - Enable Handshake for DMA Write Engine Channel 1. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH1_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MASK (0x40000U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SHIFT (18U) /*! DMA_WRITE_ENGINE_EN_HSHAKE_CH2 - Enable Handshake for DMA Write Engine Channel 2. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH2_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MASK (0x80000U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SHIFT (19U) /*! DMA_WRITE_ENGINE_EN_HSHAKE_CH3 - Enable Handshake for DMA Write Engine Channel 3. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_EN_HSHAKE_CH3_MASK) /*! @} */ /*! @name DMA_WRITE_DOORBELL_OFF - DMA Write Doorbell Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MASK (0x7U) #define PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SHIFT (0U) /*! WR_DOORBELL_NUM - Doorbell Number. */ #define PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MASK) #define PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_STOP_MASK (0x80000000U) #define PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_STOP_SHIFT (31U) /*! WR_STOP - Stop. */ #define PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_STOP_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_DOORBELL_OFF_WR_STOP_MASK) /*! @} */ /*! @name DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF - DMA Write Engine Channel Arbitration Weight Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MASK (0x1FU) #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SHIFT (0U) /*! WRITE_CHANNEL0_WEIGHT - Channel 0 Weight. */ #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MASK (0x3E0U) #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SHIFT (5U) /*! WRITE_CHANNEL1_WEIGHT - Channel 1 Weight. */ #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MASK (0x7C00U) #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SHIFT (10U) /*! WRITE_CHANNEL2_WEIGHT - Channel 2 Weight. */ #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MASK (0xF8000U) #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SHIFT (15U) /*! WRITE_CHANNEL3_WEIGHT - Channel 3 Weight. */ #define PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MASK) /*! @} */ /*! @name DMA_READ_ENGINE_EN_OFF - DMA Read Engine Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MASK (0x1U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SHIFT (0U) /*! DMA_READ_ENGINE - DMA Read Engine Enable. * 0b0..Disable (Soft Reset) * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MASK) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MASK (0x10000U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SHIFT (16U) /*! DMA_READ_ENGINE_EN_HSHAKE_CH0 - Enable Handshake for DMA Read Engine Channel 0. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH0_MASK) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MASK (0x20000U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SHIFT (17U) /*! DMA_READ_ENGINE_EN_HSHAKE_CH1 - Enable Handshake for DMA Read Engine Channel 1. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH1_MASK) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MASK (0x40000U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SHIFT (18U) /*! DMA_READ_ENGINE_EN_HSHAKE_CH2 - Enable Handshake for DMA Read Engine Channel 2. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH2_MASK) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MASK (0x80000U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SHIFT (19U) /*! DMA_READ_ENGINE_EN_HSHAKE_CH3 - Enable Handshake for DMA Read Engine Channel 3. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_EN_HSHAKE_CH3_MASK) /*! @} */ /*! @name DMA_READ_DOORBELL_OFF - DMA Read Doorbell Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MASK (0x7U) #define PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SHIFT (0U) /*! RD_DOORBELL_NUM - Doorbell Number. */ #define PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MASK) #define PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_STOP_MASK (0x80000000U) #define PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_STOP_SHIFT (31U) /*! RD_STOP - Stop. */ #define PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_STOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_STOP_SHIFT)) & PCIE_DMA_IATU_DMA_READ_DOORBELL_OFF_RD_STOP_MASK) /*! @} */ /*! @name DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF - DMA Read Engine Channel Arbitration Weight Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MASK (0x1FU) #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SHIFT (0U) /*! READ_CHANNEL0_WEIGHT - Channel 0 Weight. */ #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MASK (0x3E0U) #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SHIFT (5U) /*! READ_CHANNEL1_WEIGHT - Channel 1 Weight. */ #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MASK (0x7C00U) #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SHIFT (10U) /*! READ_CHANNEL2_WEIGHT - Channel 2 Weight. */ #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MASK) #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MASK (0xF8000U) #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SHIFT (15U) /*! READ_CHANNEL3_WEIGHT - Channel 3 Weight. */ #define PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MASK) /*! @} */ /*! @name DMA_WRITE_INT_STATUS_OFF - DMA Write Interrupt Status Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MASK (0xFU) #define PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SHIFT (0U) /*! WR_DONE_INT_STATUS - Done Interrupt Status. */ #define PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MASK) #define PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SHIFT (16U) /*! WR_ABORT_INT_STATUS - Abort Interrupt Status. */ #define PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MASK) /*! @} */ /*! @name DMA_WRITE_INT_MASK_OFF - DMA Write Interrupt Mask Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MASK (0xFU) #define PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SHIFT (0U) /*! WR_DONE_INT_MASK - Done Interrupt Mask. */ #define PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MASK) #define PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SHIFT (16U) /*! WR_ABORT_INT_MASK - Abort Interrupt Mask. */ #define PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MASK) /*! @} */ /*! @name DMA_WRITE_INT_CLEAR_OFF - DMA Write Interrupt Clear Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MASK (0xFU) #define PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SHIFT (0U) /*! WR_DONE_INT_CLEAR - Done Interrupt Clear. */ #define PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MASK) #define PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SHIFT (16U) /*! WR_ABORT_INT_CLEAR - Abort Interrupt Clear. */ #define PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MASK) /*! @} */ /*! @name DMA_WRITE_ERR_STATUS_OFF - DMA Write Error Status Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MASK (0xFFU) #define PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SHIFT (0U) /*! APP_READ_ERR_DETECT - Application Read Error Detected. */ #define PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MASK (0xFF0000U) #define PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SHIFT (16U) /*! LINKLIST_ELEMENT_FETCH_ERR_DETECT - Linked List Element Fetch Error Detected. */ #define PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MASK) /*! @} */ /*! @name DMA_WRITE_DONE_IMWR_LOW_OFF - DMA Write Done IMWr Address Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SHIFT (0U) /*! DMA_WRITE_DONE_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. */ #define PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MASK) /*! @} */ /*! @name DMA_WRITE_DONE_IMWR_HIGH_OFF - DMA Write Done IMWr Interrupt Address High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SHIFT (0U) /*! DMA_WRITE_DONE_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. */ #define PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MASK) /*! @} */ /*! @name DMA_WRITE_ABORT_IMWR_LOW_OFF - DMA Write Abort IMWr Address Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SHIFT (0U) /*! DMA_WRITE_ABORT_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. */ #define PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MASK) /*! @} */ /*! @name DMA_WRITE_ABORT_IMWR_HIGH_OFF - DMA Write Abort IMWr Address High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SHIFT (0U) /*! DMA_WRITE_ABORT_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. */ #define PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MASK) /*! @} */ /*! @name DMA_WRITE_CH01_IMWR_DATA_OFF - DMA Write Channel 1 and 0 IMWr Data Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MASK (0xFFFFU) #define PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SHIFT (0U) /*! WR_CHANNEL_0_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. */ #define PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MASK) #define PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MASK (0xFFFF0000U) #define PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SHIFT (16U) /*! WR_CHANNEL_1_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. */ #define PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MASK) /*! @} */ /*! @name DMA_WRITE_CH23_IMWR_DATA_OFF - DMA Write Channel 3 and 2 IMWr Data Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MASK (0xFFFFU) #define PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SHIFT (0U) /*! WR_CHANNEL_2_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. */ #define PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MASK) #define PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MASK (0xFFFF0000U) #define PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SHIFT (16U) /*! WR_CHANNEL_3_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. */ #define PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MASK) /*! @} */ /*! @name DMA_WRITE_LINKED_LIST_ERR_EN_OFF - DMA Write Linked List Error Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MASK (0xFU) #define PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SHIFT (0U) /*! WR_CHANNEL_LLRAIE - Write Channel LL Remote Abort Interrupt Enable (LLRAIE). */ #define PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MASK) #define PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SHIFT (16U) /*! WR_CHANNEL_LLLAIE - Write Channel LL Local Abort Interrupt Enable (LLLAIE). */ #define PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MASK) /*! @} */ /*! @name DMA_READ_INT_STATUS_OFF - DMA Read Interrupt Status Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MASK (0xFU) #define PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SHIFT (0U) /*! RD_DONE_INT_STATUS - Done Interrupt Status. */ #define PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SHIFT)) & PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MASK) #define PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SHIFT (16U) /*! RD_ABORT_INT_STATUS - Abort Interrupt Status. */ #define PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SHIFT)) & PCIE_DMA_IATU_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MASK) /*! @} */ /*! @name DMA_READ_INT_MASK_OFF - DMA Read Interrupt Mask Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MASK (0xFU) #define PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SHIFT (0U) /*! RD_DONE_INT_MASK - Done Interrupt Mask. */ #define PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SHIFT)) & PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MASK) #define PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SHIFT (16U) /*! RD_ABORT_INT_MASK - Abort Interrupt Mask. */ #define PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SHIFT)) & PCIE_DMA_IATU_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MASK) /*! @} */ /*! @name DMA_READ_INT_CLEAR_OFF - DMA Read Interrupt Clear Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MASK (0xFFU) #define PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SHIFT (0U) /*! RD_DONE_INT_CLEAR - Done Interrupt Clear. */ #define PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SHIFT)) & PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MASK) #define PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MASK (0xFF0000U) #define PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SHIFT (16U) /*! RD_ABORT_INT_CLEAR - Abort Interrupt Clear. */ #define PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SHIFT)) & PCIE_DMA_IATU_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MASK) /*! @} */ /*! @name DMA_READ_ERR_STATUS_LOW_OFF - DMA Read Error Status Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MASK (0xFFU) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SHIFT (0U) /*! APP_WR_ERR_DETECT - Application Write Error Detected. */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MASK) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MASK (0xFF0000U) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SHIFT (16U) /*! LINK_LIST_ELEMENT_FETCH_ERR_DETECT - Linked List Element Fetch Error Detected. */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MASK) /*! @} */ /*! @name DMA_READ_ERR_STATUS_HIGH_OFF - DMA Read Error Status High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MASK (0xFFU) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SHIFT (0U) /*! UNSUPPORTED_REQ - Unsupported Request. */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MASK) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MASK (0xFF00U) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SHIFT (8U) /*! CPL_ABORT - Completer Abort. */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MASK) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MASK (0xFF0000U) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SHIFT (16U) /*! CPL_TIMEOUT - Completion Time Out. */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MASK) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MASK (0xFF000000U) #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SHIFT (24U) /*! DATA_POISIONING - Data Poisoning. */ #define PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MASK) /*! @} */ /*! @name DMA_READ_LINKED_LIST_ERR_EN_OFF - DMA Read Linked List Error Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MASK (0xFU) #define PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SHIFT (0U) /*! RD_CHANNEL_LLRAIE - Read Channel LL Remote Abort Interrupt Enable (LLRAIE). */ #define PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SHIFT)) & PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MASK) #define PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MASK (0xF0000U) #define PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SHIFT (16U) /*! RD_CHANNEL_LLLAIE - Read Channel LL Local Abort Interrupt Enable (LLLAIE). */ #define PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SHIFT)) & PCIE_DMA_IATU_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MASK) /*! @} */ /*! @name DMA_READ_DONE_IMWR_LOW_OFF - DMA Read Done IMWr Address Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SHIFT (0U) /*! DMA_READ_DONE_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. */ #define PCIE_DMA_IATU_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SHIFT)) & PCIE_DMA_IATU_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MASK) /*! @} */ /*! @name DMA_READ_DONE_IMWR_HIGH_OFF - DMA Read Done IMWr Address High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SHIFT (0U) /*! DMA_READ_DONE_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. */ #define PCIE_DMA_IATU_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SHIFT)) & PCIE_DMA_IATU_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MASK) /*! @} */ /*! @name DMA_READ_ABORT_IMWR_LOW_OFF - DMA Read Abort IMWr Address Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SHIFT (0U) /*! DMA_READ_ABORT_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. */ #define PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MASK) /*! @} */ /*! @name DMA_READ_ABORT_IMWR_HIGH_OFF - DMA Read Abort IMWr Address High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SHIFT (0U) /*! DMA_READ_ABORT_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. */ #define PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MASK) /*! @} */ /*! @name DMA_READ_CH01_IMWR_DATA_OFF - DMA Read Channel 1 and 0 IMWr Data Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MASK (0xFFFFU) #define PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SHIFT (0U) /*! RD_CHANNEL_0_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. */ #define PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MASK) #define PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MASK (0xFFFF0000U) #define PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SHIFT (16U) /*! RD_CHANNEL_1_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. */ #define PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MASK) /*! @} */ /*! @name DMA_READ_CH23_IMWR_DATA_OFF - DMA Read Channel 3 and 2 IMWr Data Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MASK (0xFFFFU) #define PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SHIFT (0U) /*! RD_CHANNEL_2_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. */ #define PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MASK) #define PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MASK (0xFFFF0000U) #define PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SHIFT (16U) /*! RD_CHANNEL_3_DATA - The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. */ #define PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MASK) /*! @} */ /*! @name DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF - DMA Write Engine Handshake Counter Channel 0/1/2/3 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MASK (0x1FU) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SHIFT (0U) /*! DMA_WRITE_ENGINE_HSHAKE_CNT_CH0 - DMA handshake counter for DMA Write Engine Channel 0. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH0_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MASK (0x1F00U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SHIFT (8U) /*! DMA_WRITE_ENGINE_HSHAKE_CNT_CH1 - DMA handshake counter for DMA Write Engine Channel 1. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH1_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MASK (0x1F0000U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SHIFT (16U) /*! DMA_WRITE_ENGINE_HSHAKE_CNT_CH2 - DMA handshake counter for DMA Write Engine Channel 2. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH2_MASK) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MASK (0x1F000000U) #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SHIFT (24U) /*! DMA_WRITE_ENGINE_HSHAKE_CNT_CH3 - DMA handshake counter for DMA Write Engine Channel 3. */ #define PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_WRITE_ENGINE_HSHAKE_CNT_CH3_MASK) /*! @} */ /*! @name DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF - DMA Read Engine Handshake Counter Channel 0/1/2/3 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MASK (0x1FU) #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SHIFT (0U) /*! DMA_READ_ENGINE_HSHAKE_CNT_CH0 - DMA handshake counter for DMA Read Engine Channel 0. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH0_MASK) #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MASK (0x1F00U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SHIFT (8U) /*! DMA_READ_ENGINE_HSHAKE_CNT_CH1 - DMA handshake counter for DMA Read Engine Channel 1. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH1_MASK) #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MASK (0x1F0000U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SHIFT (16U) /*! DMA_READ_ENGINE_HSHAKE_CNT_CH2 - DMA handshake counter for DMA Read Engine Channel 2. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH2_MASK) #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MASK (0x1F000000U) #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SHIFT (24U) /*! DMA_READ_ENGINE_HSHAKE_CNT_CH3 - DMA handshake counter for DMA Read Engine Channel 3. */ #define PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_SHIFT)) & PCIE_DMA_IATU_DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF_DMA_READ_ENGINE_HSHAKE_CNT_CH3_MASK) /*! @} */ /*! @name DMA_WRITE_CH0_PWR_EN_OFF - DMA Write Channel 0 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_CH0_PWR_EN_OFF_DMA_WRITE_CH0_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_WRITE_CH0_PWR_EN_OFF_DMA_WRITE_CH0_PWR_EN_SHIFT (0U) /*! DMA_WRITE_CH0_PWR_EN - DMA Write Channel 0 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_WRITE_CH0_PWR_EN_OFF_DMA_WRITE_CH0_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH0_PWR_EN_OFF_DMA_WRITE_CH0_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH0_PWR_EN_OFF_DMA_WRITE_CH0_PWR_EN_MASK) /*! @} */ /*! @name DMA_WRITE_CH1_PWR_EN_OFF - DMA Write Channel 1 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_CH1_PWR_EN_OFF_DMA_WRITE_CH1_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_WRITE_CH1_PWR_EN_OFF_DMA_WRITE_CH1_PWR_EN_SHIFT (0U) /*! DMA_WRITE_CH1_PWR_EN - DMA Write Channel 1 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_WRITE_CH1_PWR_EN_OFF_DMA_WRITE_CH1_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH1_PWR_EN_OFF_DMA_WRITE_CH1_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH1_PWR_EN_OFF_DMA_WRITE_CH1_PWR_EN_MASK) /*! @} */ /*! @name DMA_WRITE_CH2_PWR_EN_OFF - DMA Write Channel 2 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_CH2_PWR_EN_OFF_DMA_WRITE_CH2_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_WRITE_CH2_PWR_EN_OFF_DMA_WRITE_CH2_PWR_EN_SHIFT (0U) /*! DMA_WRITE_CH2_PWR_EN - DMA Write Channel 2 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_WRITE_CH2_PWR_EN_OFF_DMA_WRITE_CH2_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH2_PWR_EN_OFF_DMA_WRITE_CH2_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH2_PWR_EN_OFF_DMA_WRITE_CH2_PWR_EN_MASK) /*! @} */ /*! @name DMA_WRITE_CH3_PWR_EN_OFF - DMA Write Channel 3 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_WRITE_CH3_PWR_EN_OFF_DMA_WRITE_CH3_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_WRITE_CH3_PWR_EN_OFF_DMA_WRITE_CH3_PWR_EN_SHIFT (0U) /*! DMA_WRITE_CH3_PWR_EN - DMA Write Channel 3 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_WRITE_CH3_PWR_EN_OFF_DMA_WRITE_CH3_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_WRITE_CH3_PWR_EN_OFF_DMA_WRITE_CH3_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_WRITE_CH3_PWR_EN_OFF_DMA_WRITE_CH3_PWR_EN_MASK) /*! @} */ /*! @name DMA_READ_CH0_PWR_EN_OFF - DMA Read Channel 0 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_CH0_PWR_EN_OFF_DMA_READ_CH0_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_READ_CH0_PWR_EN_OFF_DMA_READ_CH0_PWR_EN_SHIFT (0U) /*! DMA_READ_CH0_PWR_EN - DMA Read Channel 0 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_READ_CH0_PWR_EN_OFF_DMA_READ_CH0_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH0_PWR_EN_OFF_DMA_READ_CH0_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH0_PWR_EN_OFF_DMA_READ_CH0_PWR_EN_MASK) /*! @} */ /*! @name DMA_READ_CH1_PWR_EN_OFF - DMA Read Channel 1 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_CH1_PWR_EN_OFF_DMA_READ_CH1_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_READ_CH1_PWR_EN_OFF_DMA_READ_CH1_PWR_EN_SHIFT (0U) /*! DMA_READ_CH1_PWR_EN - DMA Read Channel 1 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_READ_CH1_PWR_EN_OFF_DMA_READ_CH1_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH1_PWR_EN_OFF_DMA_READ_CH1_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH1_PWR_EN_OFF_DMA_READ_CH1_PWR_EN_MASK) /*! @} */ /*! @name DMA_READ_CH2_PWR_EN_OFF - DMA Read Channel 2 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_CH2_PWR_EN_OFF_DMA_READ_CH2_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_READ_CH2_PWR_EN_OFF_DMA_READ_CH2_PWR_EN_SHIFT (0U) /*! DMA_READ_CH2_PWR_EN - DMA Read Channel 2 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_READ_CH2_PWR_EN_OFF_DMA_READ_CH2_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH2_PWR_EN_OFF_DMA_READ_CH2_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH2_PWR_EN_OFF_DMA_READ_CH2_PWR_EN_MASK) /*! @} */ /*! @name DMA_READ_CH3_PWR_EN_OFF - DMA Read Channel 3 Power Enable Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_READ_CH3_PWR_EN_OFF_DMA_READ_CH3_PWR_EN_MASK (0x1U) #define PCIE_DMA_IATU_DMA_READ_CH3_PWR_EN_OFF_DMA_READ_CH3_PWR_EN_SHIFT (0U) /*! DMA_READ_CH3_PWR_EN - DMA Read Channel 3 Power enable/disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_DMA_IATU_DMA_READ_CH3_PWR_EN_OFF_DMA_READ_CH3_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_READ_CH3_PWR_EN_OFF_DMA_READ_CH3_PWR_EN_SHIFT)) & PCIE_DMA_IATU_DMA_READ_CH3_PWR_EN_OFF_DMA_READ_CH3_PWR_EN_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_WRCH_0 - DMA Write Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..An error condition has been detected, and the DMA has stopped this channel * 0b00..Reserved * 0b01..This channel is active and transferring data * 0b11..The DMA has transferred all data for this channel, or you have prematurely stopped this channel by * writing to the Stop field of the DMA Write Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell * Register (DMA_READ_DOORBELL_OFF) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..memory type * 0b0..peripheral type */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_WRCH_0 - DMA Write Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_WRCH_0 - DMA Write SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_WRCH_0 - DMA Write SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_WRCH_0 - DMA Write DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_WRCH_0 - DMA Write DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_WRCH_0 - DMA Write Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_WRCH_0 - DMA Write Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_RDCH_0 - DMA Read Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..Halted. An error condition has been detected, and the DMA has stopped this channel. * 0b00..Reserved * 0b01..Running. This channel is active and transferring data. * 0b11..Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel * by writing to the Stop field of the DMA Read Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read * Doorbell Register (DMA_READ_DOORBELL_OFF). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..main memory * 0b0..peripheral */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_RDCH_0 - DMA Read Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_RDCH_0 - DMA Read SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_RDCH_0 - DMA Read SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_RDCH_0 - DMA Read DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_RDCH_0 - DMA Read DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_RDCH_0 - DMA Read Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_RDCH_0 - DMA Read Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_WRCH_1 - DMA Write Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..An error condition has been detected, and the DMA has stopped this channel * 0b00..Reserved * 0b01..This channel is active and transferring data * 0b11..The DMA has transferred all data for this channel, or you have prematurely stopped this channel by * writing to the Stop field of the DMA Write Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell * Register (DMA_READ_DOORBELL_OFF) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..memory type * 0b0..peripheral type */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_1_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_WRCH_1 - DMA Write Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_1_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_WRCH_1 - DMA Write SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_1_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_WRCH_1 - DMA Write SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_1_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_WRCH_1 - DMA Write DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_1_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_WRCH_1 - DMA Write DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_1_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_WRCH_1 - DMA Write Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_1_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_WRCH_1 - DMA Write Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_1_LLP_HIGH_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_RDCH_1 - DMA Read Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..Halted. An error condition has been detected, and the DMA has stopped this channel. * 0b00..Reserved * 0b01..Running. This channel is active and transferring data. * 0b11..Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel * by writing to the Stop field of the DMA Read Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read * Doorbell Register (DMA_READ_DOORBELL_OFF). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..main memory * 0b0..peripheral */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_1_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_RDCH_1 - DMA Read Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_1_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_RDCH_1 - DMA Read SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_1_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_RDCH_1 - DMA Read SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_1_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_RDCH_1 - DMA Read DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_1_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_RDCH_1 - DMA Read DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_1_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_RDCH_1 - DMA Read Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_1_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_RDCH_1 - DMA Read Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_1_LLP_HIGH_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_WRCH_2 - DMA Write Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..An error condition has been detected, and the DMA has stopped this channel * 0b00..Reserved * 0b01..This channel is active and transferring data * 0b11..The DMA has transferred all data for this channel, or you have prematurely stopped this channel by * writing to the Stop field of the DMA Write Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell * Register (DMA_READ_DOORBELL_OFF) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..memory type * 0b0..peripheral type */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_2_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_WRCH_2 - DMA Write Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_2_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_WRCH_2 - DMA Write SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_2_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_WRCH_2 - DMA Write SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_2_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_WRCH_2 - DMA Write DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_2_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_WRCH_2 - DMA Write DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_2_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_WRCH_2 - DMA Write Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_2_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_WRCH_2 - DMA Write Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_2_LLP_HIGH_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_RDCH_2 - DMA Read Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..Halted. An error condition has been detected, and the DMA has stopped this channel. * 0b00..Reserved * 0b01..Running. This channel is active and transferring data. * 0b11..Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel * by writing to the Stop field of the DMA Read Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read * Doorbell Register (DMA_READ_DOORBELL_OFF). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..main memory * 0b0..peripheral */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_2_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_RDCH_2 - DMA Read Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_2_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_RDCH_2 - DMA Read SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_2_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_RDCH_2 - DMA Read SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_2_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_RDCH_2 - DMA Read DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_2_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_RDCH_2 - DMA Read DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_2_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_RDCH_2 - DMA Read Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_2_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_RDCH_2 - DMA Read Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_2_LLP_HIGH_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_WRCH_3 - DMA Write Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..An error condition has been detected, and the DMA has stopped this channel * 0b00..Reserved * 0b01..This channel is active and transferring data * 0b11..The DMA has transferred all data for this channel, or you have prematurely stopped this channel by * writing to the Stop field of the DMA Write Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read Doorbell * Register (DMA_READ_DOORBELL_OFF) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..memory type * 0b0..peripheral type */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_WRCH_3_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_WRCH_3 - DMA Write Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_WRCH_3_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_WRCH_3 - DMA Write SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_WRCH_3_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_WRCH_3 - DMA Write SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_WRCH_3_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_WRCH_3 - DMA Write DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_WRCH_3_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_WRCH_3 - DMA Write DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_WRCH_3_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_WRCH_3 - DMA Write Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_WRCH_3_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_WRCH_3 - DMA Write Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_WRCH_3_LLP_HIGH_MASK) /*! @} */ /*! @name DMA_CH_CONTROL1_OFF_RDCH_3 - DMA Read Channel Control 1 Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MASK (0x1U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SHIFT (0U) /*! CB - Cycle Bit (CB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MASK (0x2U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SHIFT (1U) /*! TCB - Toggle Cycle Bit (TCB). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_TCB_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MASK (0x4U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SHIFT (2U) /*! LLP - Load Link Pointer (LLP). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLP_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MASK (0x8U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SHIFT (3U) /*! LIE - Local Interrupt Enable (LIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MASK (0x10U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SHIFT (4U) /*! RIE - Remote Interrupt Enable (RIE). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_RIE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MASK (0x60U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SHIFT (5U) /*! CS - Channel Status (CS). * 0b10..Halted. An error condition has been detected, and the DMA has stopped this channel. * 0b00..Reserved * 0b01..Running. This channel is active and transferring data. * 0b11..Stopped. The DMA has transferred all data for this channel, or you have prematurely stopped this channel * by writing to the Stop field of the DMA Read Doorbell Register (DMA_WRITE_DOORBELL_OFF) or DMA Read * Doorbell Register (DMA_READ_DOORBELL_OFF). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MASK (0x80U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SHIFT (7U) /*! DMA_RESERVED0 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED0_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MASK (0x100U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SHIFT (8U) /*! CCS - Consumer Cycle State (CCS). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_CCS_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MASK (0x200U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SHIFT (9U) /*! LLE - Linked List Enable (LLE). * 0b0..Disable linked list operation * 0b1..Enable linked list operation */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_LLE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MASK (0xC00U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SHIFT (10U) /*! DMA_RESERVED1 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED1_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MASK (0x1F000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SHIFT (12U) /*! DMA_FUNC_NUM - DMA Channel Physical Function Number. * 0b11111..The maximum number of Physical Functions is given by CX_NFUNC, so the maximum value of this field is CX_NFUNC-1. * 0b00000..Physical Channel Function Number starts at 0. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_FUNC_NUM_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MASK (0x400000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SHIFT (22U) /*! DMA_MEM_TYPE - Master AXI ACE-Lite Cache Coherency Control. * 0b1..main memory * 0b0..peripheral */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_MEM_TYPE_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MASK (0x800000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SHIFT (23U) /*! DMA_NS_DST - Destination No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_DST_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MASK (0x1000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SHIFT (24U) /*! DMA_NS_SRC - Source No Snoop TLP Header Bit. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_NS_SRC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MASK (0x2000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SHIFT (25U) /*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RO_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MASK (0x4000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SHIFT (26U) /*! DMA_RESERVED5 - Reserved. */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_RESERVED5_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MASK (0x38000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SHIFT (27U) /*! DMA_TC - Traffic Class TLP Header Bit (TC). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_TC_MASK) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MASK (0xC0000000U) #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SHIFT (30U) /*! DMA_AT - Address Translation TLP Header Bit (AT). */ #define PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_SHIFT)) & PCIE_DMA_IATU_DMA_CH_CONTROL1_OFF_RDCH_3_DMA_AT_MASK) /*! @} */ /*! @name DMA_TRANSFER_SIZE_OFF_RDCH_3 - DMA Read Transfer Size Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SHIFT (0U) /*! DMA_TRANSFER_SIZE - DMA Transfer Size. */ #define PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_IATU_DMA_TRANSFER_SIZE_OFF_RDCH_3_DMA_TRANSFER_SIZE_MASK) /*! @} */ /*! @name DMA_SAR_LOW_OFF_RDCH_3 - DMA Read SAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SHIFT (0U) /*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_LOW_OFF_RDCH_3_SRC_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_SAR_HIGH_OFF_RDCH_3 - DMA Read SAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SHIFT (0U) /*! SRC_ADDR_REG_HIGH - Source Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_SAR_HIGH_OFF_RDCH_3_SRC_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_DAR_LOW_OFF_RDCH_3 - DMA Read DAR Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SHIFT (0U) /*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_LOW_OFF_RDCH_3_DST_ADDR_REG_LOW_MASK) /*! @} */ /*! @name DMA_DAR_HIGH_OFF_RDCH_3 - DMA Read DAR High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SHIFT (0U) /*! DST_ADDR_REG_HIGH - Destination Address Register (higher 32 bits). */ #define PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_DAR_HIGH_OFF_RDCH_3_DST_ADDR_REG_HIGH_MASK) /*! @} */ /*! @name DMA_LLP_LOW_OFF_RDCH_3 - DMA Read Linked List Pointer Low Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SHIFT (0U) /*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_LOW_OFF_RDCH_3_LLP_LOW_MASK) /*! @} */ /*! @name DMA_LLP_HIGH_OFF_RDCH_3 - DMA Read Linked List Pointer High Register. */ /*! @{ */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MASK (0xFFFFFFFFU) #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SHIFT (0U) /*! LLP_HIGH - Higher 32 bits of the address of the linked list transfer list in local memory. */ #define PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_SHIFT)) & PCIE_DMA_IATU_DMA_LLP_HIGH_OFF_RDCH_3_LLP_HIGH_MASK) /*! @} */ /*! * @} */ /* end of group PCIE_DMA_IATU_Register_Masks */ /* PCIE_DMA_IATU - Peripheral instance base addresses */ /** Peripheral HSIO__PCIE1__PCIE_DMA_IATU base address */ #define HSIO__PCIE1__PCIE_DMA_IATU_BASE (0x4C360000u) /** Peripheral HSIO__PCIE1__PCIE_DMA_IATU base pointer */ #define HSIO__PCIE1__PCIE_DMA_IATU ((PCIE_DMA_IATU_Type *)HSIO__PCIE1__PCIE_DMA_IATU_BASE) /** Peripheral HSIO__PCIE2__PCIE_DMA_IATU base address */ #define HSIO__PCIE2__PCIE_DMA_IATU_BASE (0x4C3E0000u) /** Peripheral HSIO__PCIE2__PCIE_DMA_IATU base pointer */ #define HSIO__PCIE2__PCIE_DMA_IATU ((PCIE_DMA_IATU_Type *)HSIO__PCIE2__PCIE_DMA_IATU_BASE) /** Array initializer of PCIE_DMA_IATU peripheral base addresses */ #define PCIE_DMA_IATU_BASE_ADDRS { HSIO__PCIE1__PCIE_DMA_IATU_BASE, HSIO__PCIE2__PCIE_DMA_IATU_BASE } /** Array initializer of PCIE_DMA_IATU peripheral base pointers */ #define PCIE_DMA_IATU_BASE_PTRS { HSIO__PCIE1__PCIE_DMA_IATU, HSIO__PCIE2__PCIE_DMA_IATU } /*! * @} */ /* end of group PCIE_DMA_IATU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCIE_EP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_EP_Peripheral_Access_Layer PCIE_EP Peripheral Access Layer * @{ */ /** PCIE_EP - Register Layout Typedef */ typedef struct { __I uint32_t DEVICE_ID_VENDOR_ID_REG; /**< Device ID , RCRB next offset pointer and Vendor ID Register., offset: 0x0 */ __IO uint32_t STATUS_COMMAND_REG; /**< Status and Command Register., offset: 0x4 */ __I uint32_t CLASS_CODE_REVISION_ID; /**< Class Code and Revision ID Register., offset: 0x8 */ __IO uint32_t BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG; /**< BIST, Header Type, Latency Timer, and Cache Line Size Register., offset: 0xC */ __IO uint32_t BAR0_REG; /**< BAR0 Register., offset: 0x10 */ __IO uint32_t BAR1_REG; /**< BAR1 Register., offset: 0x14 */ __IO uint32_t BAR2_REG; /**< BAR2 Register., offset: 0x18 */ __IO uint32_t BAR3_REG; /**< BAR3 Register., offset: 0x1C */ __IO uint32_t BAR4_REG; /**< BAR4 Register., offset: 0x20 */ __IO uint32_t BAR5_REG; /**< BAR5 Register., offset: 0x24 */ __I uint32_t CARDBUS_CIS_PTR_REG; /**< CardBus CIS Pointer Register., offset: 0x28 */ __I uint32_t SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG; /**< Subsystem ID and Subsystem Vendor ID Register., offset: 0x2C */ __IO uint32_t EXP_ROM_BASE_ADDR_REG; /**< Expansion ROM BAR Register., offset: 0x30 */ __I uint32_t PCI_CAP_PTR_REG; /**< Capabilities Pointer Register., offset: 0x34 */ uint8_t RESERVED_0[4]; __IO uint32_t MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG; /**< Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register., offset: 0x3C */ __I uint32_t CAP_ID_NXT_PTR_REG; /**< Power Management Capabilities Register., offset: 0x40 */ __IO uint32_t CON_STATUS_REG; /**< Power Management Control and Status Register., offset: 0x44 */ uint8_t RESERVED_1[8]; __IO uint32_t PCI_MSI_CAP_ID_NEXT_CTRL_REG; /**< MSI Capability Header and Message Control Register., offset: 0x50 */ __IO uint32_t MSI_CAP_OFF_04H_REG; /**< Message Address Register for MSI (Offset 04h)., offset: 0x54 */ __IO uint32_t MSI_CAP_OFF_08H_REG; /**< Message Address Register for MSI (Offset 08h)., offset: 0x58 */ __IO uint32_t MSI_CAP_OFF_0CH_REG; /**< Message Address Register for MSI (Offset 0Ch)., offset: 0x5C */ __IO uint32_t MSI_CAP_OFF_10H_REG; /**< Message Address Register for MSI (Offset 10h)., offset: 0x60 */ __I uint32_t MSI_CAP_OFF_14H_REG; /**< Message Address Register for MSI (Offset 14h)., offset: 0x64 */ uint8_t RESERVED_2[8]; __I uint32_t PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG; /**< PCI Express Capabilities, ID, Next Pointer Register., offset: 0x70 */ __I uint32_t DEVICE_CAPABILITIES_REG; /**< Device Capabilities Register., offset: 0x74 */ __IO uint32_t DEVICE_CONTROL_DEVICE_STATUS; /**< Device Control and Device Status Register., offset: 0x78 */ __I uint32_t LINK_CAPABILITIES_REG; /**< Link Capabilities Register., offset: 0x7C */ __IO uint32_t LINK_CONTROL_LINK_STATUS_REG; /**< Link Control and Link Status Register., offset: 0x80 */ uint8_t RESERVED_3[16]; __I uint32_t DEVICE_CAPABILITIES2_REG; /**< Device Capabilities 2 Register., offset: 0x94 */ __IO uint32_t DEVICE_CONTROL2_DEVICE_STATUS2_REG; /**< Device Control 2 and Status 2 Register., offset: 0x98 */ __I uint32_t LINK_CAPABILITIES2_REG; /**< Link Capabilities 2 Register., offset: 0x9C */ __IO uint32_t LINK_CONTROL2_LINK_STATUS2_REG; /**< Link Control 2 and Status 2 Register., offset: 0xA0 */ uint8_t RESERVED_4[92]; __I uint32_t AER_EXT_CAP_HDR_OFF; /**< Advanced Error Reporting Extended Capability Header., offset: 0x100 */ __IO uint32_t UNCORR_ERR_STATUS_OFF; /**< Uncorrectable Error Status Register., offset: 0x104 */ __IO uint32_t UNCORR_ERR_MASK_OFF; /**< Uncorrectable Error Mask Register., offset: 0x108 */ __IO uint32_t UNCORR_ERR_SEV_OFF; /**< Uncorrectable Error Severity Register., offset: 0x10C */ __IO uint32_t CORR_ERR_STATUS_OFF; /**< Correctable Error Status Register., offset: 0x110 */ __IO uint32_t CORR_ERR_MASK_OFF; /**< Correctable Error Mask Register., offset: 0x114 */ __IO uint32_t ADV_ERR_CAP_CTRL_OFF; /**< Advanced Error Capabilities and Control Register., offset: 0x118 */ __I uint32_t HDR_LOG_0_OFF; /**< Header Log Register 0., offset: 0x11C */ __I uint32_t HDR_LOG_1_OFF; /**< Header Log Register 1., offset: 0x120 */ __I uint32_t HDR_LOG_2_OFF; /**< Header Log Register 2., offset: 0x124 */ __I uint32_t HDR_LOG_3_OFF; /**< Header Log Register 3., offset: 0x128 */ uint8_t RESERVED_5[12]; __I uint32_t TLP_PREFIX_LOG_1_OFF; /**< TLP Prefix Log Register 1., offset: 0x138 */ __I uint32_t TLP_PREFIX_LOG_2_OFF; /**< TLP Prefix Log Register 2., offset: 0x13C */ __I uint32_t TLP_PREFIX_LOG_3_OFF; /**< TLP Prefix Log Register 3., offset: 0x140 */ __I uint32_t TLP_PREFIX_LOG_4_OFF; /**< TLP Prefix Log Register 4., offset: 0x144 */ __I uint32_t SPCIE_CAP_HEADER_REG; /**< SPCIE Capability Header., offset: 0x148 */ __I uint32_t LINK_CONTROL3_REG; /**< Link Control 3 Register., offset: 0x14C */ __IO uint32_t LANE_ERR_STATUS_REG; /**< Lane Error Status Register., offset: 0x150 */ __I uint32_t SPCIE_CAP_OFF_0CH_REG; /**< Lane Equalization Control Register for lanes 1 and 0., offset: 0x154 */ __I uint32_t LTR_CAP_HDR_REG; /**< LTR Extended Capability Header., offset: 0x158 */ __IO uint32_t LTR_LATENCY_REG; /**< LTR Max Snoop and No-Snoop Latency Register., offset: 0x15C */ __I uint32_t L1SUB_CAP_HEADER_REG; /**< L1 Substates Extended Capability Header., offset: 0x160 */ __IO uint32_t L1SUB_CAPABILITY_REG; /**< L1 Substates Capability Register., offset: 0x164 */ __IO uint32_t L1SUB_CONTROL1_REG; /**< L1 Substates Control 1 Register., offset: 0x168 */ __IO uint32_t L1SUB_CONTROL2_REG; /**< L1 Substates Control 2 Register., offset: 0x16C */ __I uint32_t VSECDMA_EXT_CAP_HDR_OFF; /**< PCIe Extended Capability ID, Capability Version, and Next Capability Offset Register., offset: 0x170 */ __I uint32_t VSECDMA_VENDOR_SPECIFIC_HDR_OFF; /**< Vendor Specific Header Register., offset: 0x174 */ __I uint32_t VSECDMA_DEVICE_INFORMATION_OFF; /**< DMA and related AXI Bridge Implementation Information., offset: 0x178 */ __I uint32_t VSECDMA_NUM_CHAN_OFF; /**< Number of Implemented Channels Register., offset: 0x17C */ __I uint32_t VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF; /**< DMA Register Map Start Address Offset Low Register., offset: 0x180 */ __I uint32_t VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF; /**< DMA Register Map Start Address Offset High Register., offset: 0x184 */ uint8_t RESERVED_6[1400]; __IO uint32_t ACK_LATENCY_TIMER_OFF; /**< Ack Latency Timer and Replay Timer Register., offset: 0x700 */ __IO uint32_t VENDOR_SPEC_DLLP_OFF; /**< Vendor Specific DLLP Register., offset: 0x704 */ __IO uint32_t PORT_FORCE_OFF; /**< Port Force Link Register., offset: 0x708 */ __IO uint32_t ACK_F_ASPM_CTRL_OFF; /**< Ack Frequency and L0-L1 ASPM Control Register., offset: 0x70C */ __IO uint32_t PORT_LINK_CTRL_OFF; /**< Port Link Control Register., offset: 0x710 */ uint8_t RESERVED_7[4]; __IO uint32_t TIMER_CTRL_MAX_FUNC_NUM_OFF; /**< Timer Control and Max Function Number Register., offset: 0x718 */ __IO uint32_t SYMBOL_TIMER_FILTER_1_OFF; /**< Symbol Timer Register and Filter Mask 1 Register., offset: 0x71C */ __IO uint32_t FILTER_MASK_2_OFF; /**< Filter Mask 2 Register., offset: 0x720 */ uint8_t RESERVED_8[4]; __I uint32_t PL_DEBUG0_OFF; /**< Debug Register 0., offset: 0x728 */ __I uint32_t PL_DEBUG1_OFF; /**< Debug Register 1., offset: 0x72C */ __I uint32_t TX_P_FC_CREDIT_STATUS_OFF; /**< Transmit Posted FC Credit Status., offset: 0x730 */ __I uint32_t TX_NP_FC_CREDIT_STATUS_OFF; /**< Transmit Non-Posted FC Credit Status., offset: 0x734 */ __I uint32_t TX_CPL_FC_CREDIT_STATUS_OFF; /**< Transmit Completion FC Credit Status, offset: 0x738 */ __IO uint32_t QUEUE_STATUS_OFF; /**< Queue Status., offset: 0x73C */ __I uint32_t VC_TX_ARBI_1_OFF; /**< VC Transmit Arbitration Register 1., offset: 0x740 */ __I uint32_t VC_TX_ARBI_2_OFF; /**< VC Transmit Arbitration Register 2., offset: 0x744 */ __IO uint32_t VC0_P_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Posted Receive Queue Control., offset: 0x748 */ __IO uint32_t VC0_NP_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Non-Posted Receive Queue Control., offset: 0x74C */ __IO uint32_t VC0_CPL_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Completion Receive Queue Control., offset: 0x750 */ uint8_t RESERVED_9[184]; __IO uint32_t GEN2_CTRL_OFF; /**< Link Width and Speed Change Control Register., offset: 0x80C */ __I uint32_t PHY_STATUS_OFF; /**< PHY Status Register., offset: 0x810 */ __IO uint32_t PHY_CONTROL_OFF; /**< PHY Control Register., offset: 0x814 */ uint8_t RESERVED_10[4]; __IO uint32_t TRGT_MAP_CTRL_OFF; /**< Programmable Target Map Control Register., offset: 0x81C */ uint8_t RESERVED_11[108]; __IO uint32_t CLOCK_GATING_CTRL_OFF; /**< Clock Gating Control Register., offset: 0x88C */ __IO uint32_t GEN3_RELATED_OFF; /**< Gen3 Control Register., offset: 0x890 */ uint8_t RESERVED_12[20]; __IO uint32_t GEN3_EQ_CONTROL_OFF; /**< Gen3 EQ Control Register., offset: 0x8A8 */ __IO uint32_t GEN3_EQ_FB_MODE_DIR_CHANGE_OFF; /**< Gen3 EQ Direction Change Feedback Mode Control Register., offset: 0x8AC */ uint8_t RESERVED_13[4]; __IO uint32_t ORDER_RULE_CTRL_OFF; /**< Order Rule Control Register., offset: 0x8B4 */ __IO uint32_t PIPE_LOOPBACK_CONTROL_OFF; /**< PIPE Loopback Control Register., offset: 0x8B8 */ __IO uint32_t MISC_CONTROL_1_OFF; /**< DBI Read-Only Write Enable Register., offset: 0x8BC */ __IO uint32_t MULTI_LANE_CONTROL_OFF; /**< UpConfigure Multi-lane Control Register., offset: 0x8C0 */ __IO uint32_t PHY_INTEROP_CTRL_OFF; /**< PHY Interoperability Control Register., offset: 0x8C4 */ __IO uint32_t TRGT_CPL_LUT_DELETE_ENTRY_OFF; /**< TRGT_CPL_LUT Delete Entry Control register., offset: 0x8C8 */ __IO uint32_t LINK_FLUSH_CONTROL_OFF; /**< Link Reset Request Flush Control Register., offset: 0x8CC */ __IO uint32_t AMBA_ERROR_RESPONSE_DEFAULT_OFF; /**< AXI Bridge Slave Error Response Register., offset: 0x8D0 */ __IO uint32_t AMBA_LINK_TIMEOUT_OFF; /**< Link Down AXI Bridge Slave Timeout Register., offset: 0x8D4 */ __IO uint32_t AMBA_ORDERING_CTRL_OFF; /**< AXI Bridge Ordering Control., offset: 0x8D8 */ uint8_t RESERVED_14[4]; __IO uint32_t COHERENCY_CONTROL_1_OFF; /**< Cache Coherency Control Register 1., offset: 0x8E0 */ __IO uint32_t COHERENCY_CONTROL_2_OFF; /**< Cache Coherency Control Register 2., offset: 0x8E4 */ __IO uint32_t COHERENCY_CONTROL_3_OFF; /**< Cache Coherency Control Register 3., offset: 0x8E8 */ uint8_t RESERVED_15[4]; __IO uint32_t AXI_MSTR_MSG_ADDR_LOW_OFF; /**< Lower 32-bits of the Programmable AXI Address., offset: 0x8F0 */ __IO uint32_t AXI_MSTR_MSG_ADDR_HIGH_OFF; /**< Upper 32-bits of the Programmable AXI Address., offset: 0x8F4 */ __I uint32_t PCIE_VERSION_NUMBER_OFF; /**< PCIe Controller IIP Release Version Number., offset: 0x8F8 */ __I uint32_t PCIE_VERSION_TYPE_OFF; /**< PCIe Controller IIP Release Version Type., offset: 0x8FC */ uint8_t RESERVED_16[528]; __I uint32_t PL_APP_BUS_DEV_NUM_STATUS_OFF; /**< Application driven bus and device number register., offset: 0xB10 */ uint8_t RESERVED_17[8]; __IO uint32_t PCIPM_TRAFFIC_CTRL_OFF; /**< TLP Traffic during Non-D0 State Control Register., offset: 0xB1C */ uint8_t RESERVED_18[16]; __IO uint32_t PL_LTR_LATENCY_OFF; /**< LTR Latency Register., offset: 0xB30 */ uint8_t RESERVED_19[12]; __IO uint32_t AUX_CLK_FREQ_OFF; /**< Auxiliary Clock Frequency Control Register., offset: 0xB40 */ __IO uint32_t L1_SUBSTATES_OFF; /**< L1 Substates Timing Register., offset: 0xB44 */ __IO uint32_t POWERDOWN_CTRL_STATUS_OFF; /**< Powerdown Control and Status Register., offset: 0xB48 */ __IO uint32_t PHY_INTEROP_CTRL_2_OFF; /**< PHY Interoperability Control 2 Register., offset: 0xB4C */ uint8_t RESERVED_20[300]; __IO uint32_t DBI_FUNCTION_BANK_CTRL_REG_OFF; /**< DBI Function Bank Control Register., offset: 0xC7C */ __IO uint32_t UTILITY_OFF; /**< UTILITY register (Reserved)., offset: 0xC80 */ uint8_t RESERVED_21[4]; __I uint32_t PM_UTILITY_OFF; /**< PM Shadow of UTILITY register (Reserved)., offset: 0xC88 */ } PCIE_EP_Type; /* ---------------------------------------------------------------------------- -- PCIE_EP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_EP_Register_Masks PCIE_EP Register Masks * @{ */ /*! @name DEVICE_ID_VENDOR_ID_REG - Device ID , RCRB next offset pointer and Vendor ID Register. */ /*! @{ */ #define PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_MASK (0xFFFFU) #define PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SHIFT (0U) /*! PCI_TYPE0_VENDOR_ID - Vendor ID. */ #define PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SHIFT)) & PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_MASK) #define PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_MASK (0xFFFF0000U) #define PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SHIFT (16U) /*! PCI_TYPE0_DEVICE_ID - DEVICE_ID [31:16] */ #define PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SHIFT)) & PCIE_EP_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_MASK) /*! @} */ /*! @name STATUS_COMMAND_REG - Status and Command Register. */ /*! @{ */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_MASK (0x1U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SHIFT (0U) /*! PCI_TYPE0_IO_EN - IO Space Enable. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_MASK (0x2U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SHIFT (1U) /*! PCI_TYPE0_MEM_SPACE_EN - Memory Space Enable. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_MASK (0x4U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SHIFT (2U) /*! PCI_TYPE0_BUS_MASTER_EN - Bus Master Enable. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_MASK (0x8U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SHIFT (3U) /*! PCI_TYPE0_SPECIAL_CYCLE_OPERATION - Special Cycle Enable. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_MASK (0x10U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SHIFT (4U) /*! PCI_TYPE_MWI_ENABLE - Memory Write and Invalidate. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_MASK (0x20U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SHIFT (5U) /*! PCI_TYPE_VGA_PALETTE_SNOOP - VGA Palette Snoop. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_MASK (0x40U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SHIFT (6U) /*! PCI_TYPE0_PARITY_ERR_EN - Parity Error Response. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_MASK (0x80U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SHIFT (7U) /*! PCI_TYPE_IDSEL_STEPPING - IDSEL Stepping/Wait Cycle Control. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_MASK (0x100U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SHIFT (8U) /*! PCI_TYPE0_SERREN - SERR# Enable. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SERREN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_MASK (0x400U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SHIFT (10U) /*! PCI_TYPE0_INT_EN - Interrupt Disable. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_MASK) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_RESERV_MASK (0xF800U) #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SHIFT (11U) /*! PCI_TYPE_RESERV - Reserved. */ #define PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_PCI_TYPE_RESERV_MASK) #define PCIE_EP_STATUS_COMMAND_REG_INT_STATUS_MASK (0x80000U) #define PCIE_EP_STATUS_COMMAND_REG_INT_STATUS_SHIFT (19U) /*! INT_STATUS - Emulation interrupt pending. */ #define PCIE_EP_STATUS_COMMAND_REG_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_INT_STATUS_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_INT_STATUS_MASK) #define PCIE_EP_STATUS_COMMAND_REG_CAP_LIST_MASK (0x100000U) #define PCIE_EP_STATUS_COMMAND_REG_CAP_LIST_SHIFT (20U) /*! CAP_LIST - Capabilities List. */ #define PCIE_EP_STATUS_COMMAND_REG_CAP_LIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_CAP_LIST_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_CAP_LIST_MASK) #define PCIE_EP_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK (0x200000U) #define PCIE_EP_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT (21U) /*! FAST_66MHZ_CAP - 66MHz Capable. */ #define PCIE_EP_STATUS_COMMAND_REG_FAST_66MHZ_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK) #define PCIE_EP_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK (0x800000U) #define PCIE_EP_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT (23U) /*! FAST_B2B_CAP - Fast Back to Back Transaction Capable. */ #define PCIE_EP_STATUS_COMMAND_REG_FAST_B2B_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK) #define PCIE_EP_STATUS_COMMAND_REG_MASTER_DPE_MASK (0x1000000U) #define PCIE_EP_STATUS_COMMAND_REG_MASTER_DPE_SHIFT (24U) /*! MASTER_DPE - Master Data Parity Error. */ #define PCIE_EP_STATUS_COMMAND_REG_MASTER_DPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_MASTER_DPE_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_MASTER_DPE_MASK) #define PCIE_EP_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK (0x6000000U) #define PCIE_EP_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT (25U) /*! DEV_SEL_TIMING - DEVSEL Timing. */ #define PCIE_EP_STATUS_COMMAND_REG_DEV_SEL_TIMING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK) #define PCIE_EP_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK (0x8000000U) #define PCIE_EP_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT (27U) /*! SIGNALED_TARGET_ABORT - Signaled Target Abort. * 0b1..This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. */ #define PCIE_EP_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK) #define PCIE_EP_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK (0x10000000U) #define PCIE_EP_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT (28U) /*! RCVD_TARGET_ABORT - Received Target Abort. * 0b1..This bit is set when a Requester receives a Completion with Completer Abort Completion Status. */ #define PCIE_EP_STATUS_COMMAND_REG_RCVD_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK) #define PCIE_EP_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK (0x20000000U) #define PCIE_EP_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT (29U) /*! RCVD_MASTER_ABORT - Received Master Abort. * 0b1..This bit is set when a Requester receives a Completion with Unsupported Request Completion Status. */ #define PCIE_EP_STATUS_COMMAND_REG_RCVD_MASTER_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK) #define PCIE_EP_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_MASK (0x40000000U) #define PCIE_EP_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SHIFT (30U) /*! SIGNALED_SYS_ERR - Signaled System Error. * 0b1..This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL message, and the SERR# Enable bit in the Command register is 1b. */ #define PCIE_EP_STATUS_COMMAND_REG_SIGNALED_SYS_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_MASK) #define PCIE_EP_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_MASK (0x80000000U) #define PCIE_EP_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SHIFT (31U) /*! DETECTED_PARITY_ERR - Detected Parity Error. * 0b1..This bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity * Error Response bit in the Command register. */ #define PCIE_EP_STATUS_COMMAND_REG_DETECTED_PARITY_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SHIFT)) & PCIE_EP_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_MASK) /*! @} */ /*! @name CLASS_CODE_REVISION_ID - Class Code and Revision ID Register. */ /*! @{ */ #define PCIE_EP_CLASS_CODE_REVISION_ID_REVISION_ID_MASK (0xFFU) #define PCIE_EP_CLASS_CODE_REVISION_ID_REVISION_ID_SHIFT (0U) /*! REVISION_ID - Revision ID. */ #define PCIE_EP_CLASS_CODE_REVISION_ID_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CLASS_CODE_REVISION_ID_REVISION_ID_SHIFT)) & PCIE_EP_CLASS_CODE_REVISION_ID_REVISION_ID_MASK) #define PCIE_EP_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_MASK (0xFF00U) #define PCIE_EP_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SHIFT (8U) /*! PROGRAM_INTERFACE - Programming Interface. */ #define PCIE_EP_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SHIFT)) & PCIE_EP_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_MASK) #define PCIE_EP_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_MASK (0xFF0000U) #define PCIE_EP_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SHIFT (16U) /*! SUBCLASS_CODE - Sub-Class Code. */ #define PCIE_EP_CLASS_CODE_REVISION_ID_SUBCLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SHIFT)) & PCIE_EP_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_MASK) #define PCIE_EP_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_MASK (0xFF000000U) #define PCIE_EP_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SHIFT (24U) /*! BASE_CLASS_CODE - Base Class Code. */ #define PCIE_EP_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SHIFT)) & PCIE_EP_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_MASK) /*! @} */ /*! @name BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG - BIST, Header Type, Latency Timer, and Cache Line Size Register. */ /*! @{ */ #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK (0xFFU) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT (0U) /*! CACHE_LINE_SIZE - Cache Line Size. */ #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT)) & PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK (0xFF00U) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT (8U) /*! LATENCY_MASTER_TIMER - Latency Timer. */ #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT)) & PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK (0x7F0000U) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT (16U) /*! HEADER_TYPE - Header Layout. */ #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT)) & PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK (0x800000U) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT (23U) /*! MULTI_FUNC - Multi-Function Device. * 0b0..Software must not probe for Functions other than Function 0 unless explicitly indicated by another * mechanism, such as an ARI or SR-IOV Capability structure. * 0b1..Indicates that the Device may contain multiple Functions, but not necessarily. Software is permitted to * probe for Functions other than Function 0 */ #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT)) & PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_MASK (0xFF000000U) #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SHIFT (24U) /*! BIST - BIST. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SHIFT)) & PCIE_EP_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_MASK) /*! @} */ /*! @name BAR0_REG - BAR0 Register. */ /*! @{ */ #define PCIE_EP_BAR0_REG_BAR0_MEM_IO_MASK (0x1U) #define PCIE_EP_BAR0_REG_BAR0_MEM_IO_SHIFT (0U) /*! BAR0_MEM_IO - - BAR0 Memory Space Indicator. */ #define PCIE_EP_BAR0_REG_BAR0_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR0_REG_BAR0_MEM_IO_SHIFT)) & PCIE_EP_BAR0_REG_BAR0_MEM_IO_MASK) #define PCIE_EP_BAR0_REG_BAR0_TYPE_MASK (0x6U) #define PCIE_EP_BAR0_REG_BAR0_TYPE_SHIFT (1U) /*! BAR0_TYPE - - BAR0 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_EP_BAR0_REG_BAR0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR0_REG_BAR0_TYPE_SHIFT)) & PCIE_EP_BAR0_REG_BAR0_TYPE_MASK) #define PCIE_EP_BAR0_REG_BAR0_PREFETCH_MASK (0x8U) #define PCIE_EP_BAR0_REG_BAR0_PREFETCH_SHIFT (3U) /*! BAR0_PREFETCH - - BAR0 Prefetchable. */ #define PCIE_EP_BAR0_REG_BAR0_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR0_REG_BAR0_PREFETCH_SHIFT)) & PCIE_EP_BAR0_REG_BAR0_PREFETCH_MASK) #define PCIE_EP_BAR0_REG_BAR0_START_MASK (0xFFFFFFF0U) #define PCIE_EP_BAR0_REG_BAR0_START_SHIFT (4U) /*! BAR0_START - - BAR0_START. */ #define PCIE_EP_BAR0_REG_BAR0_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR0_REG_BAR0_START_SHIFT)) & PCIE_EP_BAR0_REG_BAR0_START_MASK) /*! @} */ /*! @name BAR1_REG - BAR1 Register. */ /*! @{ */ #define PCIE_EP_BAR1_REG_BAR1_MEM_IO_MASK (0x1U) #define PCIE_EP_BAR1_REG_BAR1_MEM_IO_SHIFT (0U) /*! BAR1_MEM_IO - - BAR1 Memory Space Indicator. */ #define PCIE_EP_BAR1_REG_BAR1_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR1_REG_BAR1_MEM_IO_SHIFT)) & PCIE_EP_BAR1_REG_BAR1_MEM_IO_MASK) #define PCIE_EP_BAR1_REG_BAR1_TYPE_MASK (0x6U) #define PCIE_EP_BAR1_REG_BAR1_TYPE_SHIFT (1U) /*! BAR1_TYPE - - BAR1 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_EP_BAR1_REG_BAR1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR1_REG_BAR1_TYPE_SHIFT)) & PCIE_EP_BAR1_REG_BAR1_TYPE_MASK) #define PCIE_EP_BAR1_REG_BAR1_PREFETCH_MASK (0x8U) #define PCIE_EP_BAR1_REG_BAR1_PREFETCH_SHIFT (3U) /*! BAR1_PREFETCH - - BAR1 Prefetchable. */ #define PCIE_EP_BAR1_REG_BAR1_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR1_REG_BAR1_PREFETCH_SHIFT)) & PCIE_EP_BAR1_REG_BAR1_PREFETCH_MASK) #define PCIE_EP_BAR1_REG_BAR1_START_MASK (0xFFFFFFF0U) #define PCIE_EP_BAR1_REG_BAR1_START_SHIFT (4U) /*! BAR1_START - - BAR1 Base Address. */ #define PCIE_EP_BAR1_REG_BAR1_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR1_REG_BAR1_START_SHIFT)) & PCIE_EP_BAR1_REG_BAR1_START_MASK) /*! @} */ /*! @name BAR2_REG - BAR2 Register. */ /*! @{ */ #define PCIE_EP_BAR2_REG_BAR2_MEM_IO_MASK (0x1U) #define PCIE_EP_BAR2_REG_BAR2_MEM_IO_SHIFT (0U) /*! BAR2_MEM_IO - BAR2 Memory Space Indicator. */ #define PCIE_EP_BAR2_REG_BAR2_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR2_REG_BAR2_MEM_IO_SHIFT)) & PCIE_EP_BAR2_REG_BAR2_MEM_IO_MASK) #define PCIE_EP_BAR2_REG_BAR2_TYPE_MASK (0x6U) #define PCIE_EP_BAR2_REG_BAR2_TYPE_SHIFT (1U) /*! BAR2_TYPE - BAR2 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_EP_BAR2_REG_BAR2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR2_REG_BAR2_TYPE_SHIFT)) & PCIE_EP_BAR2_REG_BAR2_TYPE_MASK) #define PCIE_EP_BAR2_REG_BAR2_PREFETCH_MASK (0x8U) #define PCIE_EP_BAR2_REG_BAR2_PREFETCH_SHIFT (3U) /*! BAR2_PREFETCH - BAR2 Prefetchable. */ #define PCIE_EP_BAR2_REG_BAR2_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR2_REG_BAR2_PREFETCH_SHIFT)) & PCIE_EP_BAR2_REG_BAR2_PREFETCH_MASK) #define PCIE_EP_BAR2_REG_BAR2_START_MASK (0xFFFFFFF0U) #define PCIE_EP_BAR2_REG_BAR2_START_SHIFT (4U) /*! BAR2_START - BAR2 Base Address. */ #define PCIE_EP_BAR2_REG_BAR2_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR2_REG_BAR2_START_SHIFT)) & PCIE_EP_BAR2_REG_BAR2_START_MASK) /*! @} */ /*! @name BAR3_REG - BAR3 Register. */ /*! @{ */ #define PCIE_EP_BAR3_REG_BAR3_MEM_IO_MASK (0x1U) #define PCIE_EP_BAR3_REG_BAR3_MEM_IO_SHIFT (0U) /*! BAR3_MEM_IO - BAR3 Memory Space Indicator. */ #define PCIE_EP_BAR3_REG_BAR3_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR3_REG_BAR3_MEM_IO_SHIFT)) & PCIE_EP_BAR3_REG_BAR3_MEM_IO_MASK) #define PCIE_EP_BAR3_REG_BAR3_TYPE_MASK (0x6U) #define PCIE_EP_BAR3_REG_BAR3_TYPE_SHIFT (1U) /*! BAR3_TYPE - BAR3 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_EP_BAR3_REG_BAR3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR3_REG_BAR3_TYPE_SHIFT)) & PCIE_EP_BAR3_REG_BAR3_TYPE_MASK) #define PCIE_EP_BAR3_REG_BAR3_PREFETCH_MASK (0x8U) #define PCIE_EP_BAR3_REG_BAR3_PREFETCH_SHIFT (3U) /*! BAR3_PREFETCH - BAR3 Prefetchable. */ #define PCIE_EP_BAR3_REG_BAR3_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR3_REG_BAR3_PREFETCH_SHIFT)) & PCIE_EP_BAR3_REG_BAR3_PREFETCH_MASK) #define PCIE_EP_BAR3_REG_BAR3_START_MASK (0xFFFFFFF0U) #define PCIE_EP_BAR3_REG_BAR3_START_SHIFT (4U) /*! BAR3_START - BAR3 Base Address. */ #define PCIE_EP_BAR3_REG_BAR3_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR3_REG_BAR3_START_SHIFT)) & PCIE_EP_BAR3_REG_BAR3_START_MASK) /*! @} */ /*! @name BAR4_REG - BAR4 Register. */ /*! @{ */ #define PCIE_EP_BAR4_REG_BAR4_MEM_IO_MASK (0x1U) #define PCIE_EP_BAR4_REG_BAR4_MEM_IO_SHIFT (0U) /*! BAR4_MEM_IO - BAR4 Memory Space Indicator. */ #define PCIE_EP_BAR4_REG_BAR4_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR4_REG_BAR4_MEM_IO_SHIFT)) & PCIE_EP_BAR4_REG_BAR4_MEM_IO_MASK) #define PCIE_EP_BAR4_REG_BAR4_TYPE_MASK (0x6U) #define PCIE_EP_BAR4_REG_BAR4_TYPE_SHIFT (1U) /*! BAR4_TYPE - BAR4 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_EP_BAR4_REG_BAR4_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR4_REG_BAR4_TYPE_SHIFT)) & PCIE_EP_BAR4_REG_BAR4_TYPE_MASK) #define PCIE_EP_BAR4_REG_BAR4_PREFETCH_MASK (0x8U) #define PCIE_EP_BAR4_REG_BAR4_PREFETCH_SHIFT (3U) /*! BAR4_PREFETCH - BAR4 Prefetchable. */ #define PCIE_EP_BAR4_REG_BAR4_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR4_REG_BAR4_PREFETCH_SHIFT)) & PCIE_EP_BAR4_REG_BAR4_PREFETCH_MASK) #define PCIE_EP_BAR4_REG_BAR4_START_MASK (0xFFFFFFF0U) #define PCIE_EP_BAR4_REG_BAR4_START_SHIFT (4U) /*! BAR4_START - BAR4 Base Address. */ #define PCIE_EP_BAR4_REG_BAR4_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR4_REG_BAR4_START_SHIFT)) & PCIE_EP_BAR4_REG_BAR4_START_MASK) /*! @} */ /*! @name BAR5_REG - BAR5 Register. */ /*! @{ */ #define PCIE_EP_BAR5_REG_BAR5_MEM_IO_MASK (0x1U) #define PCIE_EP_BAR5_REG_BAR5_MEM_IO_SHIFT (0U) /*! BAR5_MEM_IO - BAR5 Memory Space Indicator. */ #define PCIE_EP_BAR5_REG_BAR5_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR5_REG_BAR5_MEM_IO_SHIFT)) & PCIE_EP_BAR5_REG_BAR5_MEM_IO_MASK) #define PCIE_EP_BAR5_REG_BAR5_TYPE_MASK (0x6U) #define PCIE_EP_BAR5_REG_BAR5_TYPE_SHIFT (1U) /*! BAR5_TYPE - BAR5 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_EP_BAR5_REG_BAR5_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR5_REG_BAR5_TYPE_SHIFT)) & PCIE_EP_BAR5_REG_BAR5_TYPE_MASK) #define PCIE_EP_BAR5_REG_BAR5_PREFETCH_MASK (0x8U) #define PCIE_EP_BAR5_REG_BAR5_PREFETCH_SHIFT (3U) /*! BAR5_PREFETCH - BAR5 Prefetchable. */ #define PCIE_EP_BAR5_REG_BAR5_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR5_REG_BAR5_PREFETCH_SHIFT)) & PCIE_EP_BAR5_REG_BAR5_PREFETCH_MASK) #define PCIE_EP_BAR5_REG_BAR5_START_MASK (0xFFFFFFF0U) #define PCIE_EP_BAR5_REG_BAR5_START_SHIFT (4U) /*! BAR5_START - BAR5 Base Address. */ #define PCIE_EP_BAR5_REG_BAR5_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_BAR5_REG_BAR5_START_SHIFT)) & PCIE_EP_BAR5_REG_BAR5_START_MASK) /*! @} */ /*! @name CARDBUS_CIS_PTR_REG - CardBus CIS Pointer Register. */ /*! @{ */ #define PCIE_EP_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_MASK (0xFFFFFFFFU) #define PCIE_EP_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_SHIFT (0U) /*! CARDBUS_CIS_POINTER - CardBus CIS Pointer. */ #define PCIE_EP_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_SHIFT)) & PCIE_EP_CARDBUS_CIS_PTR_REG_CARDBUS_CIS_POINTER_MASK) /*! @} */ /*! @name SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG - Subsystem ID and Subsystem Vendor ID Register. */ /*! @{ */ #define PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_MASK (0xFFFFU) #define PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SHIFT (0U) /*! SUBSYS_VENDOR_ID - Subsystem Vendor ID. */ #define PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SHIFT)) & PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_MASK) #define PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_MASK (0xFFFF0000U) #define PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SHIFT (16U) /*! SUBSYS_DEV_ID - Subsystem ID. */ #define PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SHIFT)) & PCIE_EP_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_MASK) /*! @} */ /*! @name EXP_ROM_BASE_ADDR_REG - Expansion ROM BAR Register. */ /*! @{ */ #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_MASK (0x1U) #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_SHIFT (0U) /*! ROM_BAR_ENABLE - Expansion ROM Enable. * 0b1..When the bit is 1b, address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register. * 0b0..When this bit is 0b, the Function's expansion ROM address space is disabled. */ #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_SHIFT)) & PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_MASK) #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_STATUS_MASK (0xEU) #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_STATUS_SHIFT (1U) /*! ROM_BAR_VALIDATION_STATUS - Expansion ROM Validation Status. * 0b101..Validation Fail Valid but untrusted contents (For example, Out of Date, Expired or Revoked Certificate). * 0b100..Validation Fail Invalid contents. * 0b001..Validation in Progress. * 0b111..Warning Pass Validation Passed with implementation-specific warning. Valid and trusted contents. * 0b110..Warning Pass Validation Passed with implementation-specific warning. Valid contents, trust test was not performed. * 0b011..Validation Pass Valid and trusted contents. * 0b010..Validation Pass Valid contents, trust test was not performed. * 0b000..Validation not supported. */ #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_STATUS_SHIFT)) & PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_STATUS_MASK) #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_DETAILS_MASK (0xF0U) #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_DETAILS_SHIFT (4U) /*! ROM_BAR_VALIDATION_DETAILS - Expansion ROM Validation Details. */ #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_DETAILS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_DETAILS_SHIFT)) & PCIE_EP_EXP_ROM_BASE_ADDR_REG_ROM_BAR_VALIDATION_DETAILS_MASK) #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_MASK (0xFFFFF800U) #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_SHIFT (11U) /*! EXP_ROM_BASE_ADDRESS - Expansion ROM Base Address. */ #define PCIE_EP_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_SHIFT)) & PCIE_EP_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_MASK) /*! @} */ /*! @name PCI_CAP_PTR_REG - Capabilities Pointer Register. */ /*! @{ */ #define PCIE_EP_PCI_CAP_PTR_REG_CAP_POINTER_MASK (0xFFU) #define PCIE_EP_PCI_CAP_PTR_REG_CAP_POINTER_SHIFT (0U) /*! CAP_POINTER - Capabilities Pointer. */ #define PCIE_EP_PCI_CAP_PTR_REG_CAP_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_CAP_PTR_REG_CAP_POINTER_SHIFT)) & PCIE_EP_PCI_CAP_PTR_REG_CAP_POINTER_MASK) /*! @} */ /*! @name MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG - Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register. */ /*! @{ */ #define PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_MASK (0xFFU) #define PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SHIFT (0U) /*! INT_LINE - Interrupt Line. */ #define PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SHIFT)) & PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_MASK) #define PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_MASK (0xFF00U) #define PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SHIFT (8U) /*! INT_PIN - Interrupt Pin. * 0b00000001..Map to legacy interrupt Messages for INTA * 0b00000010..Map to legacy interrupt Messages for INTB * 0b00000011..Map to legacy interrupt Messages for INTC * 0b00000100..Map to legacy interrupt Messages for INTD * 0b00000000..Indicates that the Function uses no legacy interrupt Message(s). */ #define PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SHIFT)) & PCIE_EP_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_MASK) /*! @} */ /*! @name CAP_ID_NXT_PTR_REG - Power Management Capabilities Register. */ /*! @{ */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK (0xFFU) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT (0U) /*! PM_CAP_ID - Capability ID. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK (0xFF00U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT (8U) /*! PM_NEXT_POINTER - Next Capability Pointer. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK (0x70000U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT (16U) /*! PM_SPEC_VER - Version. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PME_CLK_MASK (0x80000U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT (19U) /*! PME_CLK - PME Clock. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_PME_CLK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_PME_CLK_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_DSI_MASK (0x200000U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_DSI_SHIFT (21U) /*! DSI - Device Specific Initialization. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_DSI(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_DSI_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_DSI_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK (0x1C00000U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT (22U) /*! AUX_CURR - Aux_Current. * 0b000..0 self powered * 0b001..55mA Vaux Max. Current Required * 0b010..100mA Vaux Max. Current Required * 0b011..160mA Vaux Max. Current Required * 0b100..220mA Vaux Max. Current Required * 0b101..270mA Vaux Max. Current Required * 0b110..320mA Vaux Max. Current Required * 0b111..375mA Vaux Max. Current Required */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_AUX_CURR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK (0x2000000U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT (25U) /*! D1_SUPPORT - D1_Support. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_D1_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK (0x4000000U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT (26U) /*! D2_SUPPORT - D2_Support. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_D2_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK (0xF8000000U) #define PCIE_EP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT (27U) /*! PME_SUPPORT - PME_Support. */ #define PCIE_EP_CAP_ID_NXT_PTR_REG_PME_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT)) & PCIE_EP_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK) /*! @} */ /*! @name CON_STATUS_REG - Power Management Control and Status Register. */ /*! @{ */ #define PCIE_EP_CON_STATUS_REG_POWER_STATE_MASK (0x3U) #define PCIE_EP_CON_STATUS_REG_POWER_STATE_SHIFT (0U) /*! POWER_STATE - PowerState. * 0b00..D0 power state * 0b01..D1 power state * 0b10..D2 power state * 0b11..D3hot D3hot power state */ #define PCIE_EP_CON_STATUS_REG_POWER_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_POWER_STATE_SHIFT)) & PCIE_EP_CON_STATUS_REG_POWER_STATE_MASK) #define PCIE_EP_CON_STATUS_REG_NO_SOFT_RST_MASK (0x8U) #define PCIE_EP_CON_STATUS_REG_NO_SOFT_RST_SHIFT (3U) /*! NO_SOFT_RST - No_Soft_Reset. */ #define PCIE_EP_CON_STATUS_REG_NO_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_NO_SOFT_RST_SHIFT)) & PCIE_EP_CON_STATUS_REG_NO_SOFT_RST_MASK) #define PCIE_EP_CON_STATUS_REG_PME_ENABLE_MASK (0x100U) #define PCIE_EP_CON_STATUS_REG_PME_ENABLE_SHIFT (8U) /*! PME_ENABLE - PME_En. */ #define PCIE_EP_CON_STATUS_REG_PME_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_PME_ENABLE_SHIFT)) & PCIE_EP_CON_STATUS_REG_PME_ENABLE_MASK) #define PCIE_EP_CON_STATUS_REG_DATA_SELECT_MASK (0x1E00U) #define PCIE_EP_CON_STATUS_REG_DATA_SELECT_SHIFT (9U) /*! DATA_SELECT - Data_Select. */ #define PCIE_EP_CON_STATUS_REG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_DATA_SELECT_SHIFT)) & PCIE_EP_CON_STATUS_REG_DATA_SELECT_MASK) #define PCIE_EP_CON_STATUS_REG_DATA_SCALE_MASK (0x6000U) #define PCIE_EP_CON_STATUS_REG_DATA_SCALE_SHIFT (13U) /*! DATA_SCALE - Data_Scale. */ #define PCIE_EP_CON_STATUS_REG_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_DATA_SCALE_SHIFT)) & PCIE_EP_CON_STATUS_REG_DATA_SCALE_MASK) #define PCIE_EP_CON_STATUS_REG_PME_STATUS_MASK (0x8000U) #define PCIE_EP_CON_STATUS_REG_PME_STATUS_SHIFT (15U) /*! PME_STATUS - PME_Status. */ #define PCIE_EP_CON_STATUS_REG_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_PME_STATUS_SHIFT)) & PCIE_EP_CON_STATUS_REG_PME_STATUS_MASK) #define PCIE_EP_CON_STATUS_REG_B2_B3_SUPPORT_MASK (0x400000U) #define PCIE_EP_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT (22U) /*! B2_B3_SUPPORT - B2B3 Support for D3hot. */ #define PCIE_EP_CON_STATUS_REG_B2_B3_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT)) & PCIE_EP_CON_STATUS_REG_B2_B3_SUPPORT_MASK) #define PCIE_EP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK (0x800000U) #define PCIE_EP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT (23U) /*! BUS_PWR_CLK_CON_EN - Bus Power/Clock Control Enable. */ #define PCIE_EP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT)) & PCIE_EP_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK) #define PCIE_EP_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK (0xFF000000U) #define PCIE_EP_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT (24U) /*! DATA_REG_ADD_INFO - Data. */ #define PCIE_EP_CON_STATUS_REG_DATA_REG_ADD_INFO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT)) & PCIE_EP_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK) /*! @} */ /*! @name PCI_MSI_CAP_ID_NEXT_CTRL_REG - MSI Capability Header and Message Control Register. */ /*! @{ */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK (0xFFU) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT (0U) /*! PCI_MSI_CAP_ID - Capability ID. */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK (0xFF00U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT (8U) /*! PCI_MSI_CAP_NEXT_OFFSET - Next Capability Pointer. */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK (0x10000U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT (16U) /*! PCI_MSI_ENABLE - MSI Enable. */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK (0xE0000U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT (17U) /*! PCI_MSI_MULTIPLE_MSG_CAP - Multiple Message Capable. * 0b100..16 vectors requested * 0b000..1 vector requested * 0b001..2 vectors requested * 0b101..32 vectors requested * 0b010..4 vectors requested * 0b011..8 vectors requested */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK (0x700000U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT (20U) /*! PCI_MSI_MULTIPLE_MSG_EN - Multiple Message Enable. * 0b100..16 vectors allocated * 0b000..1 vector allocated * 0b001..2 vectors allocated * 0b101..32 vectors allocated * 0b010..4 vectors allocated * 0b011..8 vectors allocated */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK (0x800000U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT (23U) /*! PCI_MSI_64_BIT_ADDR_CAP - 64 bit address capable. * 0b0..If set, the function is capable of sending a 64-bit message address. * 0b1..If clear, the function is not capable of sending a 64-bit message address. */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK (0x1000000U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT (24U) /*! PCI_PVM_SUPPORT - Per-Vector Masking Capable. */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK (0x2000000U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT (25U) /*! PCI_MSI_EXT_DATA_CAP - Extended Message Data Capable. */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK (0x4000000U) #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT (26U) /*! PCI_MSI_EXT_DATA_EN - Extended Message Data Enable. */ #define PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT)) & PCIE_EP_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK) /*! @} */ /*! @name MSI_CAP_OFF_04H_REG - Message Address Register for MSI (Offset 04h). */ /*! @{ */ #define PCIE_EP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK (0xFFFFFFFCU) #define PCIE_EP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT (2U) /*! PCI_MSI_CAP_OFF_04H - Message Address - System-specified message address. */ #define PCIE_EP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT)) & PCIE_EP_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK) /*! @} */ /*! @name MSI_CAP_OFF_08H_REG - Message Address Register for MSI (Offset 08h). */ /*! @{ */ #define PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK (0xFFFFU) #define PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT (0U) /*! PCI_MSI_CAP_OFF_08H - For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). */ #define PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT)) & PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK) #define PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK (0xFFFF0000U) #define PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT (16U) /*! PCI_MSI_CAP_OFF_0AH - For a function that supports a 32-bit message address, this field contains * Extended Message Data (System-specified message data). */ #define PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT)) & PCIE_EP_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK) /*! @} */ /*! @name MSI_CAP_OFF_0CH_REG - Message Address Register for MSI (Offset 0Ch). */ /*! @{ */ #define PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK (0xFFFFU) #define PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT (0U) /*! PCI_MSI_CAP_OFF_0CH - PCI_MSI_CAP_OFF_0CH */ #define PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT)) & PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK) #define PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK (0xFFFF0000U) #define PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT (16U) /*! PCI_MSI_CAP_OFF_0EH - PCI_MSI_CAP_OFF_0EH */ #define PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT)) & PCIE_EP_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK) /*! @} */ /*! @name MSI_CAP_OFF_10H_REG - Message Address Register for MSI (Offset 10h). */ /*! @{ */ #define PCIE_EP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK (0xFFFFFFFFU) #define PCIE_EP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT (0U) /*! PCI_MSI_CAP_OFF_10H - Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG. */ #define PCIE_EP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT)) & PCIE_EP_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK) /*! @} */ /*! @name MSI_CAP_OFF_14H_REG - Message Address Register for MSI (Offset 14h). */ /*! @{ */ #define PCIE_EP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK (0xFFFFFFFFU) #define PCIE_EP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT (0U) /*! PCI_MSI_CAP_OFF_14H - Pending Bits. */ #define PCIE_EP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT)) & PCIE_EP_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK) /*! @} */ /*! @name PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG - PCI Express Capabilities, ID, Next Pointer Register. */ /*! @{ */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK (0xFFU) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT (0U) /*! PCIE_CAP_ID - Capability ID. */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT)) & PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK (0xFF00U) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT (8U) /*! PCIE_CAP_NEXT_PTR - Next Capability Pointer. */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT)) & PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK (0xF0000U) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT (16U) /*! PCIE_CAP_REG - Capability Version. */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT)) & PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK (0xF00000U) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT (20U) /*! PCIE_DEV_PORT_TYPE - Device/Port Type. * 0b0110..Downstream Port of PCI Express Switch * 0b0000..PCI Express Endpoint * 0b0001..Legacy PCI Express Endpoint * 0b0100..Root Port of PCI Express Root Complex * 0b0101..Upstream Port of PCI Express Switch */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT)) & PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK (0x1000000U) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT (24U) /*! PCIE_SLOT_IMP - Slot Implemented. */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT)) & PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK (0x3E000000U) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT (25U) /*! PCIE_INT_MSG_NUM - PCIE Interrupt Message Number. */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT)) & PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK (0x40000000U) #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT (30U) /*! RSVD - Reserved. */ #define PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT)) & PCIE_EP_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK) /*! @} */ /*! @name DEVICE_CAPABILITIES_REG - Device Capabilities Register. */ /*! @{ */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK (0x7U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT (0U) /*! PCIE_CAP_MAX_PAYLOAD_SIZE - Max_Payload_Size Supported. * 0b011..1024 bytes max payload size * 0b000..128 bytes max payload size * 0b100..2048 bytes max payload size * 0b001..256 bytes max payload size * 0b101..4096 bytes max payload size * 0b010..512 bytes max payload size */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK (0x18U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT (3U) /*! PCIE_CAP_PHANTOM_FUNC_SUPPORT - Phantom Functions Supported. * 0b01..The most significant bit of the Function number in Requester ID is used for Phantom Functions; a * Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use * Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. * 0b10..The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a * Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers * 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as * Phantom Functions. * 0b00..No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. * 0b11..All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single * Function 0 that is permitted to use all other Function Numbers as Phantom Functions. */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK (0x20U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT (5U) /*! PCIE_CAP_EXT_TAG_SUPP - Extended Tag Field Supported. * 0b0..5-bit Tag field supported * 0b1..8-bit Tag field supported */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_MASK (0x1C0U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SHIFT (6U) /*! PCIE_CAP_EP_L0S_ACCPT_LATENCY - Endpoint L0s Acceptable Latency. * 0b001..Maximum of 128 ns * 0b100..Maximum of 1 us * 0b010..Maximum of 256 ns * 0b101..Maximum of 2 us * 0b110..Maximum of 4 us * 0b011..Maximum of 512 ns * 0b000..Maximum of 64 ns * 0b111..No limit */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_MASK (0xE00U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SHIFT (9U) /*! PCIE_CAP_EP_L1_ACCPT_LATENCY - Endpoint L1 Acceptable Latency. * 0b100..Maximum of 16 us * 0b000..Maximum of 1 us * 0b001..Maximum of 2 us * 0b101..Maximum of 32 us * 0b010..Maximum of 4 us * 0b110..Maximum of 64 us * 0b011..Maximum of 8 us * 0b111..No limit */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK (0x8000U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT (15U) /*! PCIE_CAP_ROLE_BASED_ERR_REPORT - Role-Based Error Reporting. */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_MASK (0x3FC0000U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SHIFT (18U) /*! PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE - Captured Slot Power Limit Value. */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_MASK (0xC000000U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SHIFT (26U) /*! PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE - Captured Slot Power Limit Scale. * 0b11..0.001x * 0b10..0.01x * 0b01..0.1x * 0b00..1.0x */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_MASK) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_MASK (0x10000000U) #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SHIFT (28U) /*! PCIE_CAP_FLR_CAP - Function Level Reset Capability. */ #define PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_MASK) /*! @} */ /*! @name DEVICE_CONTROL_DEVICE_STATUS - Device Control and Device Status Register. */ /*! @{ */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK (0x1U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT (0U) /*! PCIE_CAP_CORR_ERR_REPORT_EN - Correctable Error Reporting Enable. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK (0x2U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT (1U) /*! PCIE_CAP_NON_FATAL_ERR_REPORT_EN - Non-Fatal Error Reporting Enable. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK (0x4U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT (2U) /*! PCIE_CAP_FATAL_ERR_REPORT_EN - Fatal Error Reporting Enable. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK (0x8U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT (3U) /*! PCIE_CAP_UNSUPPORT_REQ_REP_EN - Unsupported Request Reporting Enable. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK (0x10U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT (4U) /*! PCIE_CAP_EN_REL_ORDER - Enable Relaxed Ordering. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK (0xE0U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT (5U) /*! PCIE_CAP_MAX_PAYLOAD_SIZE_CS - Max_Payload_Size. * 0b011..1024 bytes maximum Read Request size * 0b000..128 bytes maximum Read Request size * 0b100..2048 bytes maximum Read Request size * 0b001..256 bytes maximum Read Request size * 0b101..4096 bytes maximum Read Request size * 0b010..512 bytes maximum Read Request size * 0b110..RESERVED * 0b111..RESERVED */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK (0x100U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT (8U) /*! PCIE_CAP_EXT_TAG_EN - Extended Tag Field Enable. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK (0x400U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT (10U) /*! PCIE_CAP_AUX_POWER_PM_EN - Aux Power PM Enable. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK (0x800U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT (11U) /*! PCIE_CAP_EN_NO_SNOOP - Enable No Snoop. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK (0x7000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT (12U) /*! PCIE_CAP_MAX_READ_REQ_SIZE - Max_Read_Request_Size. * 0b011..1024 bytes maximum Read Request size * 0b000..128 bytes maximum Read Request size * 0b100..2048 bytes maximum Read Request size * 0b001..256 bytes maximum Read Request size * 0b101..4096 bytes maximum Read Request size * 0b010..512 bytes maximum Read Request size * 0b110..RESERVED * 0b111..RESERVED */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK (0x8000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT (15U) /*! PCIE_CAP_INITIATE_FLR - Initiate Function Level Reset. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK (0x10000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT (16U) /*! PCIE_CAP_CORR_ERR_DETECTED - Correctable Error Detected. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK (0x20000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT (17U) /*! PCIE_CAP_NON_FATAL_ERR_DETECTED - Non-Fatal Error Detected. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK (0x40000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT (18U) /*! PCIE_CAP_FATAL_ERR_DETECTED - Fatal Error Detected. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK (0x80000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT (19U) /*! PCIE_CAP_UNSUPPORTED_REQ_DETECTED - Unsupported Request Detected. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK (0x100000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT (20U) /*! PCIE_CAP_AUX_POWER_DETECTED - AUX Power Detected. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK (0x200000U) #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT (21U) /*! PCIE_CAP_TRANS_PENDING - Transactions Pending. */ #define PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT)) & PCIE_EP_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK) /*! @} */ /*! @name LINK_CAPABILITIES_REG - Link Capabilities Register. */ /*! @{ */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK (0xFU) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT (0U) /*! PCIE_CAP_MAX_LINK_SPEED - Max Link Speed. * 0b0001..Supported Link Speeds Vector field bit 0 * 0b0010..Supported Link Speeds Vector field bit 1 * 0b0011..Supported Link Speeds Vector field bit 2 * 0b0100..Supported Link Speeds Vector field bit 3 * 0b0101..Supported Link Speeds Vector field bit 4 * 0b0110..Supported Link Speeds Vector field bit 5 * 0b0111..Supported Link Speeds Vector field bit 6 */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK (0x3F0U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT (4U) /*! PCIE_CAP_MAX_LINK_WIDTH - Maximum Link Width. * 0b000001..x1 * 0b001100..x12 * 0b010000..x16 * 0b000010..x2 * 0b100000..x32 * 0b000100..x4 * 0b001000..x8 */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK (0xC00U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT (10U) /*! PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT - Active State Power Management (ASPM) Support. * 0b11..L0s and L1 Supported * 0b01..L0s Supported * 0b10..L1 Supported * 0b00..No ASPM Support */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK (0x7000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT (12U) /*! PCIE_CAP_L0S_EXIT_LATENCY - L0s Exit Latency. * 0b111..More than 4 us * 0b000..Less than 64 ns * 0b010..128 ns to less than 256 ns * 0b101..1 us to less than 2 us * 0b011..256 ns to less than 512 ns * 0b110..2 us to 4 us * 0b100..512 ns to less than 1 us * 0b001..64 ns to less than 128 ns */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK (0x38000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT (15U) /*! PCIE_CAP_L1_EXIT_LATENCY - L1 Exit Latency. * 0b111..More than 64 us * 0b000..Less than 1us * 0b101..16 us to less than 32 us * 0b001..1 us to less than 2 us * 0b010..2 us to less than 4 us * 0b110..32 us to 64 us * 0b011..4 us to less than 8 us * 0b100..8 us to less than 16 us */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK (0x40000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT (18U) /*! PCIE_CAP_CLOCK_POWER_MAN - Clock Power Management. */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK (0x80000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT (19U) /*! PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP - Surprise Down Error Reporting Capable. */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK (0x100000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT (20U) /*! PCIE_CAP_DLL_ACTIVE_REP_CAP - Data Link Layer Link Active Reporting Capable. */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK (0x200000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT (21U) /*! PCIE_CAP_LINK_BW_NOT_CAP - Link Bandwidth Notification Capability. */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK (0x400000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT (22U) /*! PCIE_CAP_ASPM_OPT_COMPLIANCE - ASPM Optionality Compliance. */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK (0xFF000000U) #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT (24U) /*! PCIE_CAP_PORT_NUM - Port Number. */ #define PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT)) & PCIE_EP_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK) /*! @} */ /*! @name LINK_CONTROL_LINK_STATUS_REG - Link Control and Link Status Register. */ /*! @{ */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK (0x3U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT (0U) /*! PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL - Active State Power Management (ASPM) Control. * 0b00..Disabled * 0b01..L0s Entry Enabled * 0b11..L0s and L1 Entry Enabled * 0b10..L1 Entry Enabled */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK (0x8U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT (3U) /*! PCIE_CAP_RCB - Read Completion Boundary (RCB). * 0b1..128 byte * 0b0..64 byte */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK (0x10U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT (4U) /*! PCIE_CAP_LINK_DISABLE - Link Disable. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK (0x20U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT (5U) /*! PCIE_CAP_RETRAIN_LINK - Retrain Link. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK (0x40U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT (6U) /*! PCIE_CAP_COMMON_CLK_CONFIG - Common Clock Configuration. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK (0x80U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT (7U) /*! PCIE_CAP_EXTENDED_SYNCH - Extended Synch. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK (0x100U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT (8U) /*! PCIE_CAP_EN_CLK_POWER_MAN - Enable Clock Power Management. * 0b1..When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according * to protocol defined in appropriate form factor specification. * 0b0..Clock power management is disabled and device must hold CLKREQ# signal low. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK (0x200U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT (9U) /*! PCIE_CAP_HW_AUTO_WIDTH_DISABLE - Hardware Autonomous Width Disable. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK (0x400U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT (10U) /*! PCIE_CAP_LINK_BW_MAN_INT_EN - Link Bandwidth Management Interrupt Enable. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK (0x800U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT (11U) /*! PCIE_CAP_LINK_AUTO_BW_INT_EN - Link Autonomous Bandwidth Management Interrupt Enable. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK (0xC000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT (14U) /*! PCIE_CAP_DRS_SIGNALING_CONTROL - DRS Signaling Control. * 0b01..DRS Interrupt Enabled * 0b00..DRS not Reported * 0b10..DRS to FRS Signaling Enabled */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK (0xF0000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT (16U) /*! PCIE_CAP_LINK_SPEED - Current Link Speed. * 0b0001..Supported Link Speeds Vector field bit 0 * 0b0010..Supported Link Speeds Vector field bit 1 * 0b0011..Supported Link Speeds Vector field bit 2 * 0b0100..Supported Link Speeds Vector field bit 3 * 0b0101..Supported Link Speeds Vector field bit 4 * 0b0110..Supported Link Speeds Vector field bit 5 * 0b0111..Supported Link Speeds Vector field bit 6 */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK (0x3F00000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT (20U) /*! PCIE_CAP_NEGO_LINK_WIDTH - Negotiated Link Width. * 0b000001..x1 * 0b001100..x12 * 0b010000..x16 * 0b000010..x2 * 0b100000..x32 * 0b000100..x4 * 0b001000..x8 */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK (0x8000000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT (27U) /*! PCIE_CAP_LINK_TRAINING - Link Training. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK (0x10000000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT (28U) /*! PCIE_CAP_SLOT_CLK_CONFIG - Slot Clock Configuration. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK (0x20000000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT (29U) /*! PCIE_CAP_DLL_ACTIVE - Data Link Layer Link Active. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK (0x40000000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT (30U) /*! PCIE_CAP_LINK_BW_MAN_STATUS - Link Bandwidth Management Status. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK (0x80000000U) #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT (31U) /*! PCIE_CAP_LINK_AUTO_BW_STATUS - Link Autonomous Bandwidth Status. */ #define PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT)) & PCIE_EP_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK) /*! @} */ /*! @name DEVICE_CAPABILITIES2_REG - Device Capabilities 2 Register. */ /*! @{ */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK (0xFU) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT (0U) /*! PCIE_CAP_CPL_TIMEOUT_RANGE - Completion Timeout Ranges Supported. * 0b0000..Completion Timeout programming not supported, the Function must implement a timeout value in the range 50 us to 50 ms. * 0b0001..Range A * 0b0011..Ranges A and B * 0b0111..Ranges A, B, and C * 0b1111..Ranges A, B, C, and D * 0b0010..Range B * 0b0110..Ranges B and C * 0b1110..Ranges B, C, and D */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK (0x10U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT (4U) /*! PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT - Completion Timeout Disable Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK (0x20U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT (5U) /*! PCIE_CAP_ARI_FORWARD_SUPPORT - ARI Forwarding Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK (0x40U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT (6U) /*! PCIE_CAP_ATOMIC_ROUTING_SUPP - AtomicOp Routing Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK (0x80U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT (7U) /*! PCIE_CAP_32_ATOMIC_CPL_SUPP - 32-bit AtomicOp Completer Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK (0x100U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT (8U) /*! PCIE_CAP_64_ATOMIC_CPL_SUPP - 64-bit AtomicOp Completer Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK (0x200U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT (9U) /*! PCIE_CAP_128_CAS_CPL_SUPP - 128-bit CAS Completer Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK (0x400U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT (10U) /*! PCIE_CAP_NO_RO_EN_PR2PR_PAR - No RO-enabled PR-PR Passing. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK (0x800U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT (11U) /*! PCIE_CAP_LTR_SUPP - LTR Mechanism Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK (0x1000U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT (12U) /*! PCIE_CAP_TPH_CMPLT_SUPPORT_0 - TPH Completer Supported Bit 0. * 0b0..TPH and Extended TPH Completer not supported (if TPH Completer Supported Bit is 0) or Reserved ((if TPH Completer Supported Bit is 1). * 0b1..TPH Completer supported; Extended TPH Completer not supported(if TPH Completer Supported Bit is 0) or * Both TPH and Extended TPH Completer supported ((if TPH Completer Supported Bit is 1). */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK (0x2000U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT (13U) /*! PCIE_CAP_TPH_CMPLT_SUPPORT_1 - TPH Completer Supported Bit 1. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MASK (0xC000U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SHIFT (14U) /*! PCIE_CAP2_LN_SYS_CLS - LN System CLS. * 0b10..LN Completer with 128-byte cachelines in effect * 0b01..LN Completer with 64-byte cachelines in effect * 0b00..LN Completer either not supported or not in effect */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_LN_SYS_CLS_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK (0x10000U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT (16U) /*! PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT - 10-Bit Tag Completer Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK (0x20000U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT (17U) /*! PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT - 10-Bit Tag Requester Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_MASK (0x10000000U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_SHIFT (28U) /*! PCIE_CAP_DMWR_CPL_SUPP - Deferrable Memory Write (DMWr) Completer Supported. */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_MASK) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_MASK (0x60000000U) #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_SHIFT (29U) /*! PCIE_CAP_DMWR_LEN_SUPP - Deferrable Memory Write (DMWr) Lengths Supported. * 0b01..1 up to 128 bytes * 0b00..0 up to 64 bytes */ #define PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_SHIFT)) & PCIE_EP_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_MASK) /*! @} */ /*! @name DEVICE_CONTROL2_DEVICE_STATUS2_REG - Device Control 2 and Status 2 Register. */ /*! @{ */ #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK (0xFU) #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT (0U) /*! PCIE_CAP_CPL_TIMEOUT_VALUE - Completion Timeout Value. * 0b0000..Default range: 50 us to 50 ms * 0b0101..16 ms to 55 ms * 0b1110..17 s to 64 s * 0b0010..1 ms to 10 ms * 0b1010..1 s to 3.5 s * 0b1001..260 ms to 900 ms * 0b1101..4 s to 13 s * 0b0001..50 us to 100 us * 0b0110..65 ms to 210 ms */ #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT)) & PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK) #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK (0x10U) #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT (4U) /*! PCIE_CAP_CPL_TIMEOUT_DISABLE - Completion Timeout Disable. */ #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT)) & PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK) #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK (0x20U) #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT (5U) /*! PCIE_CAP_ARI_FORWARD_SUPPORT_CS - ARI Forwarding Enable. */ #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT)) & PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK) #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MASK (0x400U) #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SHIFT (10U) /*! PCIE_CAP_LTR_EN - LTR Mechanism Enable. */ #define PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SHIFT)) & PCIE_EP_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MASK) /*! @} */ /*! @name LINK_CAPABILITIES2_REG - Link Capabilities 2 Register. */ /*! @{ */ #define PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK (0xFEU) #define PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT (1U) /*! PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR - Supported Link Speeds Vector. * 0b1111111..last default value. * 0b0000000..Zero value. */ #define PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT)) & PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK) #define PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK (0x100U) #define PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT (8U) /*! PCIE_CAP_CROSS_LINK_SUPPORT - Crosslink Supported. */ #define PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT)) & PCIE_EP_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK) /*! @} */ /*! @name LINK_CONTROL2_LINK_STATUS2_REG - Link Control 2 and Status 2 Register. */ /*! @{ */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK (0xFU) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT (0U) /*! PCIE_CAP_TARGET_LINK_SPEED - Target Link Speed. * 0b0001..Supported Link Speeds Vector field bit 0 * 0b0010..Supported Link Speeds Vector field bit 1 * 0b0011..Supported Link Speeds Vector field bit 2 * 0b0100..Supported Link Speeds Vector field bit 3 * 0b0101..Supported Link Speeds Vector field bit 4 * 0b0110..Supported Link Speeds Vector field bit 5 * 0b0111..Supported Link Speeds Vector field bit 6 */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK (0x10U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT (4U) /*! PCIE_CAP_ENTER_COMPLIANCE - Enter Compliance. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK (0x20U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT (5U) /*! PCIE_CAP_HW_AUTO_SPEED_DISABLE - Hardware Autonomous Speed Disable. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK (0x40U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT (6U) /*! PCIE_CAP_SEL_DEEMPHASIS - Selectable De-emphasis. * 0b1..-3.5 dB * 0b0..-6 dB */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK (0x380U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT (7U) /*! PCIE_CAP_TX_MARGIN - Transmit Margin. This field controls the value of the non-deemphasized voltage level at the Transmitter pins. * 0b000..Normal operating range */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK (0x400U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT (10U) /*! PCIE_CAP_ENTER_MODIFIED_COMPLIANCE - Enter Modified Compliance. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK (0x800U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT (11U) /*! PCIE_CAP_COMPLIANCE_SOS - Compliance SOS. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK (0xF000U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT (12U) /*! PCIE_CAP_COMPLIANCE_PRESET - Compliance Preset/De-emphasis. * 0b0001..-3.5 dB (for 5.0 GT/s Data Rate) * 0b0000..-6 dB (for 5.0 GT/s Data Rate) */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK (0x10000U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT (16U) /*! PCIE_CAP_CURR_DEEMPHASIS - Current De-emphasis Level. * 0b1..-3.5 dB * 0b0..-6 dB */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MASK (0x20000U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SHIFT (17U) /*! PCIE_CAP_EQ_CPL - Equalization 8. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MASK (0x40000U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SHIFT (18U) /*! PCIE_CAP_EQ_CPL_P1 - Equalization 8. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MASK (0x80000U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SHIFT (19U) /*! PCIE_CAP_EQ_CPL_P2 - Equalization 8. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MASK (0x100000U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SHIFT (20U) /*! PCIE_CAP_EQ_CPL_P3 - Equalization 8. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MASK) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MASK (0x200000U) #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SHIFT (21U) /*! PCIE_CAP_LINK_EQ_REQ - Link Equalization Request 8. */ #define PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SHIFT)) & PCIE_EP_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MASK) /*! @} */ /*! @name AER_EXT_CAP_HDR_OFF - Advanced Error Reporting Extended Capability Header. */ /*! @{ */ #define PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK (0xFFFFU) #define PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT (0U) /*! CAP_ID - AER Extended Capability ID. */ #define PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT)) & PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK) #define PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK (0xF0000U) #define PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT (16U) /*! CAP_VERSION - Capability Version. */ #define PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT)) & PCIE_EP_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK) #define PCIE_EP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_EP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. */ #define PCIE_EP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT)) & PCIE_EP_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK) /*! @} */ /*! @name UNCORR_ERR_STATUS_OFF - Uncorrectable Error Status Register. */ /*! @{ */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK (0x10U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT (4U) /*! DL_PROTOCOL_ERR_STATUS - Data Link Protocol Error Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK (0x20U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT (5U) /*! SURPRISE_DOWN_ERR_STATUS - Surprise Down Error Status (Optional). */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK (0x1000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT (12U) /*! POIS_TLP_ERR_STATUS - Poisoned TLP Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK (0x2000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT (13U) /*! FC_PROTOCOL_ERR_STATUS - Flow Control Protocol Error Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK (0x4000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT (14U) /*! CMPLT_TIMEOUT_ERR_STATUS - Completion Timeout Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK (0x8000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT (15U) /*! CMPLT_ABORT_ERR_STATUS - Completer Abort Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK (0x10000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT (16U) /*! UNEXP_CMPLT_ERR_STATUS - Unexpected Completion Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK (0x20000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT (17U) /*! REC_OVERFLOW_ERR_STATUS - Receiver Overflow Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK (0x40000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT (18U) /*! MALF_TLP_ERR_STATUS - Malformed TLP Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK (0x80000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT (19U) /*! ECRC_ERR_STATUS - ECRC Error Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK (0x100000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT (20U) /*! UNSUPPORTED_REQ_ERR_STATUS - Unsupported Request Error Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK (0x400000U) #define PCIE_EP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT (22U) /*! INTERNAL_ERR_STATUS - Uncorrectable Internal Error Status. */ #define PCIE_EP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT)) & PCIE_EP_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK) /*! @} */ /*! @name UNCORR_ERR_MASK_OFF - Uncorrectable Error Mask Register. */ /*! @{ */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK (0x10U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT (4U) /*! DL_PROTOCOL_ERR_MASK - Data Link Protocol Error Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK (0x20U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT (5U) /*! SURPRISE_DOWN_ERR_MASK - Surprise Down Error Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK (0x1000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT (12U) /*! POIS_TLP_ERR_MASK - Poisoned TLP Error Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK (0x2000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT (13U) /*! FC_PROTOCOL_ERR_MASK - Flow Control Protocol Error Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK (0x4000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT (14U) /*! CMPLT_TIMEOUT_ERR_MASK - Completion Timeout Error Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK (0x8000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT (15U) /*! CMPLT_ABORT_ERR_MASK - Completer Abort Error Mask (Optional). */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK (0x10000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT (16U) /*! UNEXP_CMPLT_ERR_MASK - Unexpected Completion Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK (0x20000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT (17U) /*! REC_OVERFLOW_ERR_MASK - Receiver Overflow Mask (Optional). */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK (0x40000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT (18U) /*! MALF_TLP_ERR_MASK - Malformed TLP Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK (0x80000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT (19U) /*! ECRC_ERR_MASK - ECRC Error Mask (Optional). */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK (0x100000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT (20U) /*! UNSUPPORTED_REQ_ERR_MASK - Unsupported Request Error Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK (0x400000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT (22U) /*! INTERNAL_ERR_MASK - Uncorrectable Internal Error Mask (Optional). */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MASK (0x1000000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SHIFT (24U) /*! ATOMIC_EGRESS_BLOCKED_ERR_MASK - AtomicOp Egress Block Mask (Optional). */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_MASK (0x2000000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_SHIFT (25U) /*! TLP_PRFX_BLOCKED_ERR_MASK - TLP Prefix Blocked Error Mask. */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_MASK) #define PCIE_EP_UNCORR_ERR_MASK_OFF_DMWR_EGRESS_BLOCKED_ERR_MASK_MASK (0x8000000U) #define PCIE_EP_UNCORR_ERR_MASK_OFF_DMWR_EGRESS_BLOCKED_ERR_MASK_SHIFT (27U) /*! DMWR_EGRESS_BLOCKED_ERR_MASK - Deferrable Memory Write Egress Block Mask (Optional). */ #define PCIE_EP_UNCORR_ERR_MASK_OFF_DMWR_EGRESS_BLOCKED_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_MASK_OFF_DMWR_EGRESS_BLOCKED_ERR_MASK_SHIFT)) & PCIE_EP_UNCORR_ERR_MASK_OFF_DMWR_EGRESS_BLOCKED_ERR_MASK_MASK) /*! @} */ /*! @name UNCORR_ERR_SEV_OFF - Uncorrectable Error Severity Register. */ /*! @{ */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK (0x10U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT (4U) /*! DL_PROTOCOL_ERR_SEVERITY - Data Link Protocol Error Severity. */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK (0x20U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT (5U) /*! SURPRISE_DOWN_ERR_SVRITY - Surprise Down Error Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK (0x1000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT (12U) /*! POIS_TLP_ERR_SEVERITY - Poisoned TLP Severity. */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK (0x2000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT (13U) /*! FC_PROTOCOL_ERR_SEVERITY - Flow Control Protocol Error Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK (0x4000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT (14U) /*! CMPLT_TIMEOUT_ERR_SEVERITY - Completion Timeout Error Severity. */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK (0x8000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT (15U) /*! CMPLT_ABORT_ERR_SEVERITY - Completer Abort Error Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK (0x10000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT (16U) /*! UNEXP_CMPLT_ERR_SEVERITY - Unexpected Completion Error Severity. */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK (0x20000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT (17U) /*! REC_OVERFLOW_ERR_SEVERITY - Receiver Overflow Error Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK (0x40000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT (18U) /*! MALF_TLP_ERR_SEVERITY - Malformed TLP Severity. */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK (0x80000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT (19U) /*! ECRC_ERR_SEVERITY - ECRC Error Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK (0x100000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT (20U) /*! UNSUPPORTED_REQ_ERR_SEVERITY - Unsupported Request Error Severity. */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK (0x400000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT (22U) /*! INTERNAL_ERR_SEVERITY - Uncorrectable Internal Error Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_MASK (0x2000000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_SHIFT (25U) /*! TLP_PRFX_BLOCKED_ERR_SEVERITY - TLP Prefix Blocked Error Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_MASK) #define PCIE_EP_UNCORR_ERR_SEV_OFF_DMWR_EGRESS_BLOCKED_ERR_SEVERITY_MASK (0x8000000U) #define PCIE_EP_UNCORR_ERR_SEV_OFF_DMWR_EGRESS_BLOCKED_ERR_SEVERITY_SHIFT (27U) /*! DMWR_EGRESS_BLOCKED_ERR_SEVERITY - Deferrable Memory Write Egress Blocked Severity (Optional). */ #define PCIE_EP_UNCORR_ERR_SEV_OFF_DMWR_EGRESS_BLOCKED_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UNCORR_ERR_SEV_OFF_DMWR_EGRESS_BLOCKED_ERR_SEVERITY_SHIFT)) & PCIE_EP_UNCORR_ERR_SEV_OFF_DMWR_EGRESS_BLOCKED_ERR_SEVERITY_MASK) /*! @} */ /*! @name CORR_ERR_STATUS_OFF - Correctable Error Status Register. */ /*! @{ */ #define PCIE_EP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK (0x1U) #define PCIE_EP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT (0U) /*! RX_ERR_STATUS - Receiver Error Status (Optional). */ #define PCIE_EP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK) #define PCIE_EP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK (0x40U) #define PCIE_EP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT (6U) /*! BAD_TLP_STATUS - Bad TLP Status. */ #define PCIE_EP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK) #define PCIE_EP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK (0x80U) #define PCIE_EP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT (7U) /*! BAD_DLLP_STATUS - Bad DLLP Status. */ #define PCIE_EP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK) #define PCIE_EP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK (0x100U) #define PCIE_EP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT (8U) /*! REPLAY_NO_ROLEOVER_STATUS - REPLAY_NUM Rollover Status. */ #define PCIE_EP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK) #define PCIE_EP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK (0x1000U) #define PCIE_EP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT (12U) /*! RPL_TIMER_TIMEOUT_STATUS - Replay Timer Timeout Status. */ #define PCIE_EP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK) #define PCIE_EP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK (0x2000U) #define PCIE_EP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT (13U) /*! ADVISORY_NON_FATAL_ERR_STATUS - Advisory Non-Fatal Error Status. */ #define PCIE_EP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK) #define PCIE_EP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK (0x4000U) #define PCIE_EP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT (14U) /*! CORRECTED_INT_ERR_STATUS - Corrected Internal Error Status (Optional). */ #define PCIE_EP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK) #define PCIE_EP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK (0x8000U) #define PCIE_EP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT (15U) /*! HEADER_LOG_OVERFLOW_STATUS - Header Log Overflow Error Status (Optional). */ #define PCIE_EP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT)) & PCIE_EP_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK) /*! @} */ /*! @name CORR_ERR_MASK_OFF - Correctable Error Mask Register. */ /*! @{ */ #define PCIE_EP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK (0x1U) #define PCIE_EP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT (0U) /*! RX_ERR_MASK - Receiver Error Mask (Optional). */ #define PCIE_EP_CORR_ERR_MASK_OFF_RX_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK) #define PCIE_EP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK (0x40U) #define PCIE_EP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT (6U) /*! BAD_TLP_MASK - Bad TLP Mask. */ #define PCIE_EP_CORR_ERR_MASK_OFF_BAD_TLP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK) #define PCIE_EP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK (0x80U) #define PCIE_EP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT (7U) /*! BAD_DLLP_MASK - Bad DLLP Mask. */ #define PCIE_EP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK) #define PCIE_EP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK (0x100U) #define PCIE_EP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT (8U) /*! REPLAY_NO_ROLEOVER_MASK - REPLAY_NUM Rollover Mask. */ #define PCIE_EP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK) #define PCIE_EP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK (0x1000U) #define PCIE_EP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT (12U) /*! RPL_TIMER_TIMEOUT_MASK - Replay Timer Timeout Mask. */ #define PCIE_EP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK) #define PCIE_EP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK (0x2000U) #define PCIE_EP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT (13U) /*! ADVISORY_NON_FATAL_ERR_MASK - Advisory Non-Fatal Error Mask. */ #define PCIE_EP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK) #define PCIE_EP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK (0x4000U) #define PCIE_EP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT (14U) /*! CORRECTED_INT_ERR_MASK - Corrected Internal Error Mask (Optional). */ #define PCIE_EP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK) #define PCIE_EP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK (0x8000U) #define PCIE_EP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT (15U) /*! HEADER_LOG_OVERFLOW_MASK - Header Log Overflow Error Mask (Optional). */ #define PCIE_EP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT)) & PCIE_EP_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK) /*! @} */ /*! @name ADV_ERR_CAP_CTRL_OFF - Advanced Error Capabilities and Control Register. */ /*! @{ */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK (0x1FU) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT (0U) /*! FIRST_ERR_POINTER - First Error Pointer. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK (0x20U) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT (5U) /*! ECRC_GEN_CAP - ECRC Generation Capable. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK (0x40U) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT (6U) /*! ECRC_GEN_EN - ECRC Generation Enable. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK (0x80U) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT (7U) /*! ECRC_CHECK_CAP - ECRC Check Capable. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK (0x100U) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT (8U) /*! ECRC_CHECK_EN - ECRC Check Enable. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK (0x200U) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT (9U) /*! MULTIPLE_HEADER_CAP - Multiple Header Recording Capable. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK (0x400U) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT (10U) /*! MULTIPLE_HEADER_EN - Multiple Header Recording Enable. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MASK (0x1000U) #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SHIFT (12U) /*! CTO_PRFX_HDR_LOG_CAP - Completion Timeout Prefix/Header Log Capable. */ #define PCIE_EP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SHIFT)) & PCIE_EP_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MASK) /*! @} */ /*! @name HDR_LOG_0_OFF - Header Log Register 0. */ /*! @{ */ #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT (0U) /*! FIRST_DWORD_FIRST_BYTE - Byte 0 of Header log register of First 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK) #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT (8U) /*! FIRST_DWORD_SECOND_BYTE - Byte 1 of Header log register of First 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK) #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT (16U) /*! FIRST_DWORD_THIRD_BYTE - Byte 2 of Header log register of First 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK) #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT (24U) /*! FIRST_DWORD_FOURTH_BYTE - Byte 3 of Header log register of First 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name HDR_LOG_1_OFF - Header Log Register 1. */ /*! @{ */ #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT (0U) /*! SECOND_DWORD_FIRST_BYTE - Byte 0 of Header log register of Second 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK) #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT (8U) /*! SECOND_DWORD_SECOND_BYTE - Byte 1 of Header log register of Second 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK) #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT (16U) /*! SECOND_DWORD_THIRD_BYTE - Byte 2 of Header log register of Second 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK) #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT (24U) /*! SECOND_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Second 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name HDR_LOG_2_OFF - Header Log Register 2. */ /*! @{ */ #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT (0U) /*! THIRD_DWORD_FIRST_BYTE - Byte 0 of Header log register of Third 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK) #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT (8U) /*! THIRD_DWORD_SECOND_BYTE - Byte 1 of Header log register of Third 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK) #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT (16U) /*! THIRD_DWORD_THIRD_BYTE - Byte 2 of Header log register of Third 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK) #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT (24U) /*! THIRD_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Third 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name HDR_LOG_3_OFF - Header Log Register 3. */ /*! @{ */ #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT (0U) /*! FOURTH_DWORD_FIRST_BYTE - Byte 0 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK) #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT (8U) /*! FOURTH_DWORD_SECOND_BYTE - Byte 1 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK) #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT (16U) /*! FOURTH_DWORD_THIRD_BYTE - Byte 2 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK) #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT (24U) /*! FOURTH_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_EP_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_1_OFF - TLP Prefix Log Register 1. */ /*! @{ */ #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_1_FIRST_BYTE - Byte 0 of Error TLP Prefix Log 1. */ #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_1_SECOND_BYTE - Byte 1 of Error TLP Prefix Log 1. */ #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_1_THIRD_BYTE - Byte 2 of Error TLP Prefix Log 1. */ #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_1_FOURTH_BYTE - Byte 3 of Error TLP Prefix Log 1. */ #define PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_2_OFF - TLP Prefix Log Register 2. */ /*! @{ */ #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_2_FIRST_BYTE - Byte 0 Error TLP Prefix Log 2. */ #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_2_SECOND_BYTE - Byte 1 Error TLP Prefix Log 2. */ #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_2_THIRD_BYTE - Byte 2 Error TLP Prefix Log 2. */ #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_2_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 2. */ #define PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_3_OFF - TLP Prefix Log Register 3. */ /*! @{ */ #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_3_FIRST_BYTE - Byte 0 Error TLP Prefix Log 3. */ #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_3_SECOND_BYTE - Byte 1 Error TLP Prefix Log 3. */ #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_3_THIRD_BYTE - Byte 2 Error TLP Prefix Log 3. */ #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_3_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 3. */ #define PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_4_OFF - TLP Prefix Log Register 4. */ /*! @{ */ #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK (0xFFU) #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_4_FIRST_BYTE - Byte 0 Error TLP Prefix Log 4. */ #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK (0xFF00U) #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_4_SECOND_BYTE - Byte 1 Error TLP Prefix Log 4. */ #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_4_THIRD_BYTE - Byte 2 Error TLP Prefix Log 4. */ #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK) #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_4_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 4. */ #define PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT)) & PCIE_EP_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK) /*! @} */ /*! @name SPCIE_CAP_HEADER_REG - SPCIE Capability Header. */ /*! @{ */ #define PCIE_EP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK (0xFFFFU) #define PCIE_EP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT (0U) /*! EXTENDED_CAP_ID - Secondary PCI Express Extended Capability ID. * 0b1111111111111111..Max value * 0b0000000000000000..Min value */ #define PCIE_EP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT)) & PCIE_EP_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK) #define PCIE_EP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MASK (0xF0000U) #define PCIE_EP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SHIFT (16U) /*! CAP_VERSION - Capability Version. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_EP_SPCIE_CAP_HEADER_REG_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_HEADER_REG_CAP_VERSION_SHIFT)) & PCIE_EP_SPCIE_CAP_HEADER_REG_CAP_VERSION_MASK) #define PCIE_EP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_EP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. * 0b111111111111..Max value. * 0b000000000000..Min value */ #define PCIE_EP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SHIFT)) & PCIE_EP_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MASK) /*! @} */ /*! @name LINK_CONTROL3_REG - Link Control 3 Register. */ /*! @{ */ #define PCIE_EP_LINK_CONTROL3_REG_PERFORM_EQ_MASK (0x1U) #define PCIE_EP_LINK_CONTROL3_REG_PERFORM_EQ_SHIFT (0U) /*! PERFORM_EQ - Perform Equalization. * 0b0..Clear * 0b1..When this bit is 1b and a 1b is written to the Retrain Link bit with the Target Link Speed field set to * 8.0 GT/s or higher, the Downstream Port must perform Link Equalization. */ #define PCIE_EP_LINK_CONTROL3_REG_PERFORM_EQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL3_REG_PERFORM_EQ_SHIFT)) & PCIE_EP_LINK_CONTROL3_REG_PERFORM_EQ_MASK) #define PCIE_EP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MASK (0x2U) #define PCIE_EP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SHIFT (1U) /*! EQ_REQ_INT_EN - Link Equalization Request Interrupt Enable. * 0b0..Clear * 0b1..When set, this bit enables the generation of an interrupt to indicate that the Link Equalization Request * 8.0 GT/s bit, the Link Equalization Request 16.0 GT/s bit, or the Link Equalization Request 32.0 GT/s bit * has been set. */ #define PCIE_EP_LINK_CONTROL3_REG_EQ_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SHIFT)) & PCIE_EP_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MASK) /*! @} */ /*! @name LANE_ERR_STATUS_REG - Lane Error Status Register. */ /*! @{ */ #define PCIE_EP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MASK (0x3U) #define PCIE_EP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SHIFT (0U) /*! LANE_ERR_STATUS - Lane Error Status Bits per Lane. */ #define PCIE_EP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SHIFT)) & PCIE_EP_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MASK) #define PCIE_EP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MASK (0xFFFFFFFCU) #define PCIE_EP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SHIFT (2U) /*! RSVDP_LANE_ERR_STATUS - Reserved */ #define PCIE_EP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SHIFT)) & PCIE_EP_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MASK) /*! @} */ /*! @name SPCIE_CAP_OFF_0CH_REG - Lane Equalization Control Register for lanes 1 and 0. */ /*! @{ */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MASK (0xFU) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SHIFT (0U) /*! DSP_TX_PRESET0 - Downstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MASK) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MASK (0x70U) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SHIFT (4U) /*! DSP_RX_PRESET_HINT0 - Downstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MASK) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MASK (0xF00U) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SHIFT (8U) /*! USP_TX_PRESET0 - Upstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MASK) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MASK (0x7000U) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SHIFT (12U) /*! USP_RX_PRESET_HINT0 - Upstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MASK) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MASK (0xF0000U) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SHIFT (16U) /*! DSP_TX_PRESET1 - Downstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MASK) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MASK (0x700000U) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SHIFT (20U) /*! DSP_RX_PRESET_HINT1 - Downstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MASK) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MASK (0xF000000U) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SHIFT (24U) /*! USP_TX_PRESET1 - Upstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MASK) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MASK (0x70000000U) #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SHIFT (28U) /*! USP_RX_PRESET_HINT1 - Upstream Port 8. */ #define PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SHIFT)) & PCIE_EP_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MASK) /*! @} */ /*! @name LTR_CAP_HDR_REG - LTR Extended Capability Header. */ /*! @{ */ #define PCIE_EP_LTR_CAP_HDR_REG_CAP_ID_MASK (0xFFFFU) #define PCIE_EP_LTR_CAP_HDR_REG_CAP_ID_SHIFT (0U) /*! CAP_ID - LTR Extended Capacity ID. */ #define PCIE_EP_LTR_CAP_HDR_REG_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LTR_CAP_HDR_REG_CAP_ID_SHIFT)) & PCIE_EP_LTR_CAP_HDR_REG_CAP_ID_MASK) #define PCIE_EP_LTR_CAP_HDR_REG_CAP_VERSION_MASK (0xF0000U) #define PCIE_EP_LTR_CAP_HDR_REG_CAP_VERSION_SHIFT (16U) /*! CAP_VERSION - Capability Version. */ #define PCIE_EP_LTR_CAP_HDR_REG_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LTR_CAP_HDR_REG_CAP_VERSION_SHIFT)) & PCIE_EP_LTR_CAP_HDR_REG_CAP_VERSION_MASK) #define PCIE_EP_LTR_CAP_HDR_REG_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_EP_LTR_CAP_HDR_REG_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. */ #define PCIE_EP_LTR_CAP_HDR_REG_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LTR_CAP_HDR_REG_NEXT_OFFSET_SHIFT)) & PCIE_EP_LTR_CAP_HDR_REG_NEXT_OFFSET_MASK) /*! @} */ /*! @name LTR_LATENCY_REG - LTR Max Snoop and No-Snoop Latency Register. */ /*! @{ */ #define PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_MASK (0x3FFU) #define PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SHIFT (0U) /*! MAX_SNOOP_LAT - Max Snoop Latency Value. */ #define PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SHIFT)) & PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_MASK) #define PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_MASK (0x1C00U) #define PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_SHIFT (10U) /*! MAX_SNOOP_LAT_SCALE - Max Snoop Latency Scale. */ #define PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_SHIFT)) & PCIE_EP_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_MASK) #define PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_MASK (0x3FF0000U) #define PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SHIFT (16U) /*! MAX_NO_SNOOP_LAT - Max No-Snoop Latency Value. */ #define PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SHIFT)) & PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_MASK) #define PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_MASK (0x1C000000U) #define PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_SHIFT (26U) /*! MAX_NO_SNOOP_LAT_SCALE - Max No-Snoop Latency Scale. */ #define PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_SHIFT)) & PCIE_EP_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_MASK) /*! @} */ /*! @name L1SUB_CAP_HEADER_REG - L1 Substates Extended Capability Header. */ /*! @{ */ #define PCIE_EP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK (0xFFFFU) #define PCIE_EP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT (0U) /*! EXTENDED_CAP_ID - L1SUB Extended Capability ID. */ #define PCIE_EP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT)) & PCIE_EP_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK) #define PCIE_EP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK (0xF0000U) #define PCIE_EP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT (16U) /*! CAP_VERSION - Capability Version. */ #define PCIE_EP_L1SUB_CAP_HEADER_REG_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT)) & PCIE_EP_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK) #define PCIE_EP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_EP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. */ #define PCIE_EP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT)) & PCIE_EP_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK) /*! @} */ /*! @name L1SUB_CAPABILITY_REG - L1 Substates Capability Register. */ /*! @{ */ #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK (0x1U) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT (0U) /*! L1_2_PCIPM_SUPPORT - PCI-PM L12 Supported. */ #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK (0x2U) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT (1U) /*! L1_1_PCIPM_SUPPORT - PCI-PM L11 Supported. */ #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK (0x4U) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT (2U) /*! L1_2_ASPM_SUPPORT - ASPM L12 Supported. */ #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK (0x8U) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT (3U) /*! L1_1_ASPM_SUPPORT - ASPM L11 Supported. */ #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK (0x10U) #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT (4U) /*! L1_PMSUB_SUPPORT - L1 PM Substates ECN Supported. */ #define PCIE_EP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK) #define PCIE_EP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK (0xFF00U) #define PCIE_EP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT (8U) /*! COMM_MODE_SUPPORT - Port Common Mode Restore Time. */ #define PCIE_EP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK) #define PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK (0x30000U) #define PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT (16U) /*! PWR_ON_SCALE_SUPPORT - Port T Power On Scale. * 0b11..Reserved * 0b10..Scale is 100us * 0b01..Scale is 10us * 0b00..Scale is 2us */ #define PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK) #define PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK (0xF80000U) #define PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT (19U) /*! PWR_ON_VALUE_SUPPORT - Port T Power On Value. */ #define PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT)) & PCIE_EP_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK) /*! @} */ /*! @name L1SUB_CONTROL1_REG - L1 Substates Control 1 Register. */ /*! @{ */ #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK (0x1U) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT (0U) /*! L1_2_PCIPM_EN - PCI-PM L12 Enable. */ #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT)) & PCIE_EP_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK (0x2U) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT (1U) /*! L1_1_PCIPM_EN - PCI-PM L11 Enable. */ #define PCIE_EP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT)) & PCIE_EP_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK (0x4U) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT (2U) /*! L1_2_ASPM_EN - ASPM L12 Enable. */ #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT)) & PCIE_EP_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK (0x8U) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT (3U) /*! L1_1_ASPM_EN - ASPM L11 Enable. */ #define PCIE_EP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT)) & PCIE_EP_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK) #define PCIE_EP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK (0xFF00U) #define PCIE_EP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT (8U) /*! T_COMMON_MODE - Common Mode Restore Time. */ #define PCIE_EP_L1SUB_CONTROL1_REG_T_COMMON_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT)) & PCIE_EP_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK (0x3FF0000U) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT (16U) /*! L1_2_TH_VAL - LTR L12 Threshold Value. */ #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_VAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT)) & PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK (0xE0000000U) #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT (29U) /*! L1_2_TH_SCA - LTR L12 Threshold Scale. */ #define PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_SCA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT)) & PCIE_EP_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK) /*! @} */ /*! @name L1SUB_CONTROL2_REG - L1 Substates Control 2 Register. */ /*! @{ */ #define PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK (0x3U) #define PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT (0U) /*! T_POWER_ON_SCALE - T Power On Scale. * 0b11..Reserved * 0b10..Scale is 100us * 0b01..Scale is 10us * 0b00..Scale is 2us */ #define PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT)) & PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK) #define PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK (0xF8U) #define PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT (3U) /*! T_POWER_ON_VALUE - T Power On Value. */ #define PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT)) & PCIE_EP_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK) /*! @} */ /*! @name VSECDMA_EXT_CAP_HDR_OFF - PCIe Extended Capability ID, Capability Version, and Next Capability Offset Register. */ /*! @{ */ #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_ID_MASK (0xFFFFU) #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_ID_SHIFT (0U) /*! ID - PCI Express Extended Capability ID. */ #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_ID_SHIFT)) & PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_ID_MASK) #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_CAP_MASK (0xF0000U) #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_CAP_SHIFT (16U) /*! CAP - Capability Version. */ #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_CAP_SHIFT)) & PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_CAP_MASK) #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. */ #define PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT)) & PCIE_EP_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK) /*! @} */ /*! @name VSECDMA_VENDOR_SPECIFIC_HDR_OFF - Vendor Specific Header Register. */ /*! @{ */ #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MASK (0xFFFFU) #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SHIFT (0U) /*! VSEC_ID - VSEC ID. */ #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SHIFT)) & PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MASK) #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MASK (0xF0000U) #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SHIFT (16U) /*! VSEC_REV - VSEC Rev. */ #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SHIFT)) & PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MASK) #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MASK (0xFFF00000U) #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SHIFT (20U) /*! VSEC_LENGTH - VSEC Length. */ #define PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SHIFT)) & PCIE_EP_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MASK) /*! @} */ /*! @name VSECDMA_DEVICE_INFORMATION_OFF - DMA and related AXI Bridge Implementation Information. */ /*! @{ */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_MASK (0x7U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_SHIFT (0U) /*! MAP_FORMAT - Defines the register map format and features to be one of the following values: * 0b000..Legacy DMA register map accessed by the port-logic registers * 0b001..Legacy DMA register map, mapped to a PF/BAR * 0b101..HDMA compatibility mode (CC_LEGACY_DMA_MAP =1) register map, mapped to a PF/BAR * 0b100..HDMA/DMA compatibility (CC_LEGACY_DMA_MAP =1) register map without access through the Wire * 0b111..HDMA native (CC_LEGACY_DMA_MAP =0) register map, mapped to a PF/BAR * 0b110..HDMA native (CC_LEGACY_DMA_MAP =0) register map without access through the Wire */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_MASK) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_BARN_MASK (0x700U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_BARN_SHIFT (8U) /*! BARN - Bar Number. */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_BARN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_BARN_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_BARN_MASK) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_PFN_MASK (0xF800U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_PFN_SHIFT (11U) /*! PFN - Physical Function Number. */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_PFN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_PFN_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_PFN_MASK) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_MASK (0x70000U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_SHIFT (16U) /*! CHANNEL_SEPARATION - If the MAP_FORMAT is set to HDMA_NATIVE, this field specifies the read write channel address separation. * 0b110..16k separated * 0b010..1k separated * 0b000..256 separated * 0b011..2k separated * 0b111..32k separated * 0b100..4k separated * 0b001..512 separated * 0b101..8k separated */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_MASK) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_AXI_MASK (0x80000U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_AXI_SHIFT (19U) /*! AXI - This field provides information about AXI interface usage. */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_AXI(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_AXI_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_AXI_MASK) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_MASK (0x700000U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_SHIFT (20U) /*! MASTER_BUS_WIDTH - This field provides information regarding the AXI master data bus width. * 0b010..128 bits * 0b011..256 bits * 0b000..32 bits * 0b100..512 bits * 0b001..64 bits */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_MASK) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_MASK (0x3800000U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_SHIFT (23U) /*! MASTER_BURST_LENGTH - Reports the CC_MSTR_BURST_LEN configuration parameter. * 0b000..Reserved * 0b110..128 beats * 0b011..16 beats * 0b111..256 beats * 0b100..32 beats * 0b001..4 beats * 0b101..64 beats * 0b010..8 beats */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_MASK) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_MASK (0x3C000000U) #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_SHIFT (26U) /*! MASTER_PAGE_BOUNDARY_POINTER_WIDTH - This field provides address page boundary information. */ #define PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_SHIFT)) & PCIE_EP_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_MASK) /*! @} */ /*! @name VSECDMA_NUM_CHAN_OFF - Number of Implemented Channels Register. */ /*! @{ */ #define PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_MASK (0x3FFU) #define PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_SHIFT (0U) /*! NUM_DMA_WR_CHAN - This field provides information regarding the number of implemented write channels. */ #define PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_SHIFT)) & PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_MASK) #define PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_MASK (0x3FF0000U) #define PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_SHIFT (16U) /*! NUM_DMA_RD_CHAN - This field provides information regarding the number of implemented read channels. */ #define PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_SHIFT)) & PCIE_EP_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_MASK) /*! @} */ /*! @name VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF - DMA Register Map Start Address Offset Low Register. */ /*! @{ */ #define PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_MASK (0xFFFFFFFFU) #define PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_SHIFT (0U) /*! UNROLL_ADDR_OFFSET_LOW - BAR address offset, 32-bit LSB. */ #define PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_SHIFT)) & PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_MASK) /*! @} */ /*! @name VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF - DMA Register Map Start Address Offset High Register. */ /*! @{ */ #define PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_MASK (0xFFFFFFFFU) #define PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_SHIFT (0U) /*! UNROLL_ADDR_OFFSET_HIGH - BAR address offset, 32-bit MSB. */ #define PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_SHIFT)) & PCIE_EP_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_MASK) /*! @} */ /*! @name ACK_LATENCY_TIMER_OFF - Ack Latency Timer and Replay Timer Register. */ /*! @{ */ #define PCIE_EP_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK (0xFFFFU) #define PCIE_EP_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT (0U) /*! ROUND_TRIP_LATENCY_TIME_LIMIT - Ack Latency Timer Limit. */ #define PCIE_EP_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT)) & PCIE_EP_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK) #define PCIE_EP_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK (0xFFFF0000U) #define PCIE_EP_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT (16U) /*! REPLAY_TIME_LIMIT - Replay Timer Limit. */ #define PCIE_EP_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT)) & PCIE_EP_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK) /*! @} */ /*! @name VENDOR_SPEC_DLLP_OFF - Vendor Specific DLLP Register. */ /*! @{ */ #define PCIE_EP_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK (0xFFFFFFFFU) #define PCIE_EP_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT (0U) /*! VENDOR_SPEC_DLLP - Vendor Specific DLLP Register. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_EP_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT)) & PCIE_EP_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK) /*! @} */ /*! @name PORT_FORCE_OFF - Port Force Link Register. */ /*! @{ */ #define PCIE_EP_PORT_FORCE_OFF_LINK_NUM_MASK (0xFFU) #define PCIE_EP_PORT_FORCE_OFF_LINK_NUM_SHIFT (0U) /*! LINK_NUM - Link Number. */ #define PCIE_EP_PORT_FORCE_OFF_LINK_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_FORCE_OFF_LINK_NUM_SHIFT)) & PCIE_EP_PORT_FORCE_OFF_LINK_NUM_MASK) #define PCIE_EP_PORT_FORCE_OFF_FORCED_LTSSM_MASK (0xF00U) #define PCIE_EP_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT (8U) /*! FORCED_LTSSM - Forced Link Command. */ #define PCIE_EP_PORT_FORCE_OFF_FORCED_LTSSM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT)) & PCIE_EP_PORT_FORCE_OFF_FORCED_LTSSM_MASK) #define PCIE_EP_PORT_FORCE_OFF_FORCE_EN_MASK (0x8000U) #define PCIE_EP_PORT_FORCE_OFF_FORCE_EN_SHIFT (15U) /*! FORCE_EN - Force Link. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_PORT_FORCE_OFF_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_FORCE_OFF_FORCE_EN_SHIFT)) & PCIE_EP_PORT_FORCE_OFF_FORCE_EN_MASK) #define PCIE_EP_PORT_FORCE_OFF_LINK_STATE_MASK (0x3F0000U) #define PCIE_EP_PORT_FORCE_OFF_LINK_STATE_SHIFT (16U) /*! LINK_STATE - Forced LTSSM State. */ #define PCIE_EP_PORT_FORCE_OFF_LINK_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_FORCE_OFF_LINK_STATE_SHIFT)) & PCIE_EP_PORT_FORCE_OFF_LINK_STATE_MASK) #define PCIE_EP_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_MASK (0x400000U) #define PCIE_EP_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_SHIFT (22U) /*! SUPPORT_PART_LANES_RXEI_EXIT - Support LTSSM transition from Polling. * 0b1..Any lanes receives 8 consecutive TS OSs, LTSSM moves from Polling.Active to Polling.Config. If all lanes * do not receive 8 consecutive TS OSs and any predetermined lanes are still on Rx ElecIdle, LTSSM moves from * Polling.Active to Polling.Compliance. * 0b0..Any lanes receives 8 consecutive TS OS and all predetermined lanes have Rx ElecIdle exit, LTSSM moves * from Polling.Active to Polling.Config. This is legacy mode from Base Spec. Any predetermined lanes are still * on Rx ElecIdle, LTSSM moves from Polling.Active to Polling.Compliance. */ #define PCIE_EP_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_SHIFT)) & PCIE_EP_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_MASK) #define PCIE_EP_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK (0x800000U) #define PCIE_EP_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT (23U) /*! DO_DESKEW_FOR_SRIS - DO_DESKEW_FOR_SRIS */ #define PCIE_EP_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT)) & PCIE_EP_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK) /*! @} */ /*! @name ACK_F_ASPM_CTRL_OFF - Ack Frequency and L0-L1 ASPM Control Register. */ /*! @{ */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK (0xFFU) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT (0U) /*! ACK_FREQ - Ack Frequency. * 0b11111111..Any value between 1 and 255 indicates that the controller will schedule a high-priority ACK after receiving the specified number of TLPs. * 0b00000000..The value '0' indicates that this Ack Frequency Counter feature is turned off. */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT)) & PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK (0xFF00U) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT (8U) /*! ACK_N_FTS - The number of Fast Training Sequence(N_FTS) ordered sets to be transmitted when transitioning from L0s to L0. * 0b11111111..The maximum number of FTS ordered-sets that a component can request is 255. * 0b00000000..The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT)) & PCIE_EP_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK (0xFF0000U) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT (16U) /*! COMMON_CLK_N_FTS - Common Clock N_FTS. * 0b11111111..The maximum number of FTS ordered-sets that a component can request is 255. * 0b00000000..The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT)) & PCIE_EP_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK (0x7000000U) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT (24U) /*! L0S_ENTRANCE_LATENCY - L0s Entrance Latency. * 0b000..1 us * 0b001..2 us * 0b010..3 us * 0b011..4 us * 0b100..5 us * 0b101..6 us * 0b111..7 us * 0b110..7 US */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT)) & PCIE_EP_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK (0x38000000U) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT (27U) /*! L1_ENTRANCE_LATENCY - L1 Entrance Latency. * 0b100..16 us * 0b000..1 us * 0b001..2 us * 0b101..32 us * 0b010..4 us * 0b111..64 us * 0b110..64Us * 0b011..8 us */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT)) & PCIE_EP_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK (0x40000000U) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT (30U) /*! ENTER_ASPM - ASPM L1 Entry Control. * 0b1..Controller enters ASPM L1 after a period in which it has been idle. * 0b0..Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT)) & PCIE_EP_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_MASK (0x80000000U) #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_SHIFT (31U) /*! ASPM_L1_TIMER_ENABLE - ASPM L1 Timer Enable. * 0b0..PM controller will initiate entry into L1 as soon as all the L1 idle conditions are bypassed. This * setting is only recommended when the application implements its own timers. * 0b1..PM controller starts the ASPM L1 timer whenever all the L1 idle conditions are met. This is the default recommended behavior */ #define PCIE_EP_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_SHIFT)) & PCIE_EP_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_MASK) /*! @} */ /*! @name PORT_LINK_CTRL_OFF - Port Link Control Register. */ /*! @{ */ #define PCIE_EP_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK (0x1U) #define PCIE_EP_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT (0U) /*! VENDOR_SPECIFIC_DLLP_REQ - Vendor Specific DLLP Request. * 0b0..This is a self clearing register * 0b1..When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF */ #define PCIE_EP_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK (0x2U) #define PCIE_EP_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT (1U) /*! SCRAMBLE_DISABLE - Scramble Disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK (0x4U) #define PCIE_EP_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT (2U) /*! LOOPBACK_ENABLE - Loopback Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK (0x8U) #define PCIE_EP_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT (3U) /*! RESET_ASSERT - Reset Assert. * 0b0..Clear * 0b1..Set */ #define PCIE_EP_PORT_LINK_CTRL_OFF_RESET_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK (0x20U) #define PCIE_EP_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT (5U) /*! DLL_LINK_EN - DLL Link Enable. * 0b0..The controller does not transmit InitFC DLLPs and does not establish a link. * 0b1..Enables link initialization. */ #define PCIE_EP_PORT_LINK_CTRL_OFF_DLL_LINK_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK (0x40U) #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT (6U) /*! LINK_DISABLE - LINK_DISABLE is an internally reserved field. */ #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK (0x80U) #define PCIE_EP_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT (7U) /*! FAST_LINK_MODE - Fast Link Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_PORT_LINK_CTRL_OFF_FAST_LINK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_RATE_MASK (0xF00U) #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT (8U) /*! LINK_RATE - LINK_RATE is an internally reserved field. */ #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_RATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_LINK_RATE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK (0x3F0000U) #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT (16U) /*! LINK_CAPABLE - Link Mode Enable. * 0b000001..x1 * 0b011111..x16 * 0b000011..x2 * 0b111111..x32 (not supported) * 0b000111..x4 * 0b001111..x8 */ #define PCIE_EP_PORT_LINK_CTRL_OFF_LINK_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK (0x1000000U) #define PCIE_EP_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT (24U) /*! BEACON_ENABLE - BEACON_ENABLE is an internally reserved field. */ #define PCIE_EP_PORT_LINK_CTRL_OFF_BEACON_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK (0x2000000U) #define PCIE_EP_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT (25U) /*! CORRUPT_LCRC_ENABLE - CORRUPT_LCRC_ENABLE is an internally reserved field. */ #define PCIE_EP_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK (0x4000000U) #define PCIE_EP_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT (26U) /*! EXTENDED_SYNCH - EXTENDED_SYNCH is an internally reserved field. */ #define PCIE_EP_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK) #define PCIE_EP_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK (0x8000000U) #define PCIE_EP_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT (27U) /*! TRANSMIT_LANE_REVERSALE_ENABLE - TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. */ #define PCIE_EP_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT)) & PCIE_EP_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK) /*! @} */ /*! @name TIMER_CTRL_MAX_FUNC_NUM_OFF - Timer Control and Max Function Number Register. */ /*! @{ */ #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK (0xFFU) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT (0U) /*! MAX_FUNC_NUM - Maximum function number that can be used in a request. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT)) & PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK (0x7C000U) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT (14U) /*! TIMER_MOD_REPLAY_TIMER - Replay Timer Limit Modifier. */ #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT)) & PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK (0xF80000U) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT (19U) /*! TIMER_MOD_ACK_NAK - Ack Latency Timer Modifier. */ #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT)) & PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK (0x1F000000U) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT (24U) /*! UPDATE_FREQ_TIMER - UPDATE_FREQ_TIMER is an internally reserved field. */ #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT)) & PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK (0x60000000U) #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT (29U) /*! FAST_LINK_SCALING_FACTOR - Fast Link Timer Scaling Factor. * 0b00..Scaling Factor is 1024 (1ms is 1us). When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, * 2ms timer is 4us and 3ms timer is 6us. * 0b11..Scaling Factor is 16 (1ms is 64us) * 0b01..Scaling Factor is 256 (1ms is 4us) * 0b10..Scaling Factor is 64 (1ms is 16us) */ #define PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT)) & PCIE_EP_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK) /*! @} */ /*! @name SYMBOL_TIMER_FILTER_1_OFF - Symbol Timer Register and Filter Mask 1 Register. */ /*! @{ */ #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK (0x7FFU) #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT (0U) /*! SKP_INT_VAL - SKP Interval Value. */ #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT)) & PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK) #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK (0x7800U) #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT (11U) /*! EIDLE_TIMER - EIDLE_TIMER is an internally reserved field. */ #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT)) & PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK) #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK (0x8000U) #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT (15U) /*! DISABLE_FC_WD_TIMER - Disable FC Watchdog Timer. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT)) & PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK) #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK (0xFFFF0000U) #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT (16U) /*! MASK_RADM_1 - Filter Mask 1. * 0b1111111111111111..Max value * 0b0000000000000000..Zero value */ #define PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT)) & PCIE_EP_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK) /*! @} */ /*! @name FILTER_MASK_2_OFF - Filter Mask 2 Register. */ /*! @{ */ #define PCIE_EP_FILTER_MASK_2_OFF_MASK_RADM_2_MASK (0xFFFFFFFFU) #define PCIE_EP_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT (0U) /*! MASK_RADM_2 - Filter Mask 2. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_EP_FILTER_MASK_2_OFF_MASK_RADM_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT)) & PCIE_EP_FILTER_MASK_2_OFF_MASK_RADM_2_MASK) /*! @} */ /*! @name PL_DEBUG0_OFF - Debug Register 0. */ /*! @{ */ #define PCIE_EP_PL_DEBUG0_OFF_DEB_REG_0_MASK (0xFFFFFFFFU) #define PCIE_EP_PL_DEBUG0_OFF_DEB_REG_0_SHIFT (0U) /*! DEB_REG_0 - The value on cxpl_debug_info[31:0]. * 0b11111111111111111111111111111111..Max value. * 0b00000000000000000000000000000000..Zero value. */ #define PCIE_EP_PL_DEBUG0_OFF_DEB_REG_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_DEBUG0_OFF_DEB_REG_0_SHIFT)) & PCIE_EP_PL_DEBUG0_OFF_DEB_REG_0_MASK) /*! @} */ /*! @name PL_DEBUG1_OFF - Debug Register 1. */ /*! @{ */ #define PCIE_EP_PL_DEBUG1_OFF_DEB_REG_1_MASK (0xFFFFFFFFU) #define PCIE_EP_PL_DEBUG1_OFF_DEB_REG_1_SHIFT (0U) /*! DEB_REG_1 - The value on cxpl_debug_info[63:32]. * 0b11111111111111111111111111111111..Max value. * 0b00000000000000000000000000000000..Zero value. */ #define PCIE_EP_PL_DEBUG1_OFF_DEB_REG_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_DEBUG1_OFF_DEB_REG_1_SHIFT)) & PCIE_EP_PL_DEBUG1_OFF_DEB_REG_1_MASK) /*! @} */ /*! @name TX_P_FC_CREDIT_STATUS_OFF - Transmit Posted FC Credit Status. */ /*! @{ */ #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK (0xFFFU) #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT (0U) /*! TX_P_DATA_FC_CREDIT - Transmit Posted Data FC Credits. */ #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT)) & PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK) #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK (0xFF000U) #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT (12U) /*! TX_P_HEADER_FC_CREDIT - Transmit Posted Header FC Credits. */ #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT)) & PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK) #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MASK (0xFFF00000U) #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SHIFT (20U) /*! RSVDP_TX_P_FC_CREDIT_STATUS - Reserved */ #define PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SHIFT)) & PCIE_EP_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MASK) /*! @} */ /*! @name TX_NP_FC_CREDIT_STATUS_OFF - Transmit Non-Posted FC Credit Status. */ /*! @{ */ #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK (0xFFFU) #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT (0U) /*! TX_NP_DATA_FC_CREDIT - Transmit Non-Posted Data FC Credits. */ #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT)) & PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK) #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK (0xFF000U) #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT (12U) /*! TX_NP_HEADER_FC_CREDIT - Transmit Non-Posted Header FC Credits. */ #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT)) & PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK) #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MASK (0xFFF00000U) #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SHIFT (20U) /*! RSVDP_TX_NP_FC_CREDIT_STATUS - Reserved */ #define PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SHIFT)) & PCIE_EP_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MASK) /*! @} */ /*! @name TX_CPL_FC_CREDIT_STATUS_OFF - Transmit Completion FC Credit Status */ /*! @{ */ #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK (0xFFFU) #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT (0U) /*! TX_CPL_DATA_FC_CREDIT - Transmit Completion Data FC Credits. */ #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT)) & PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK) #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK (0xFF000U) #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT (12U) /*! TX_CPL_HEADER_FC_CREDIT - Transmit Completion Header FC Credits. */ #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT)) & PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK) #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MASK (0xFFF00000U) #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SHIFT (20U) /*! RSVDP_TX_CPL_FC_CREDIT_STATUS - Reserved */ #define PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SHIFT)) & PCIE_EP_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MASK) /*! @} */ /*! @name QUEUE_STATUS_OFF - Queue Status. */ /*! @{ */ #define PCIE_EP_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK (0x1U) #define PCIE_EP_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT (0U) /*! RX_TLP_FC_CREDIT_NON_RETURN - Received TLP FC Credits Not Returned. * 0b0..Clear * 0b1..Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that * the credits for that TLP have been restored by the receiver at the other end of the link. */ #define PCIE_EP_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT)) & PCIE_EP_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK) #define PCIE_EP_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK (0x2U) #define PCIE_EP_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT (1U) /*! TX_RETRY_BUFFER_NE - Transmit Retry Buffer Not Empty. * 0b0..Clear * 0b1..Indicates that there is data in the transmit retry buffer. */ #define PCIE_EP_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT)) & PCIE_EP_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK) #define PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK (0x4U) #define PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT (2U) /*! RX_QUEUE_NON_EMPTY - Receive Credit Queue Not Empty. * 0b0..Clear * 0b1..Indicates there is data in one or more of the receive buffers. */ #define PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT)) & PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK) #define PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK (0x8U) #define PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT (3U) /*! RX_QUEUE_OVERFLOW - Receive Credit Queue Overflow. * 0b0..Clear * 0b1..Indicates insufficient buffer space available to write to the P/NP/CPL credit queue. */ #define PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT)) & PCIE_EP_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK) #define PCIE_EP_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK (0x2000U) #define PCIE_EP_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT (13U) /*! RX_SERIALIZATION_Q_NON_EMPTY - Receive Serialization Queue Not Empty. * 0b0..Clear * 0b1..Indicates there is data in the serialization queue. */ #define PCIE_EP_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT)) & PCIE_EP_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK) #define PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK (0x1FFF0000U) #define PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT (16U) /*! TIMER_MOD_FLOW_CONTROL - FC Latency Timer Override Value. */ #define PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT)) & PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK) #define PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK (0x80000000U) #define PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT (31U) /*! TIMER_MOD_FLOW_CONTROL_EN - FC Latency Timer Override Enable. * 0b0..Clear * 0b1..When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will * override the FC latency timer value that the controller calculates according to the PCIe specification. */ #define PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT)) & PCIE_EP_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK) /*! @} */ /*! @name VC_TX_ARBI_1_OFF - VC Transmit Arbitration Register 1. */ /*! @{ */ #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK (0xFFU) #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT (0U) /*! WRR_WEIGHT_VC_0 - WRR Weight for VC0. */ #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT)) & PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK) #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MASK (0xFF00U) #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SHIFT (8U) /*! WRR_WEIGHT_VC_1 - WRR Weight for VC1. */ #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SHIFT)) & PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MASK) #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MASK (0xFF0000U) #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SHIFT (16U) /*! WRR_WEIGHT_VC_2 - WRR Weight for VC2. */ #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SHIFT)) & PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MASK) #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MASK (0xFF000000U) #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SHIFT (24U) /*! WRR_WEIGHT_VC_3 - WRR Weight for VC3. */ #define PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SHIFT)) & PCIE_EP_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MASK) /*! @} */ /*! @name VC_TX_ARBI_2_OFF - VC Transmit Arbitration Register 2. */ /*! @{ */ #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MASK (0xFFU) #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SHIFT (0U) /*! WRR_WEIGHT_VC_4 - WRR Weight for VC4. */ #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SHIFT)) & PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MASK) #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MASK (0xFF00U) #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SHIFT (8U) /*! WRR_WEIGHT_VC_5 - WRR Weight for VC5. */ #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SHIFT)) & PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MASK) #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MASK (0xFF0000U) #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SHIFT (16U) /*! WRR_WEIGHT_VC_6 - WRR Weight for VC6. */ #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SHIFT)) & PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MASK) #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MASK (0xFF000000U) #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SHIFT (24U) /*! WRR_WEIGHT_VC_7 - WRR Weight for VC7. */ #define PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SHIFT)) & PCIE_EP_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MASK) /*! @} */ /*! @name VC0_P_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Posted Receive Queue Control. */ /*! @{ */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK (0xFFFU) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT (0U) /*! VC0_P_DATA_CREDIT - VC0 Posted Data Credits. * 0b111111111111..Max value * 0b000000000000..Zero value */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK (0xFF000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT (12U) /*! VC0_P_HEADER_CREDIT - VC0 Posted Header Credits. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK (0x100000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT (20U) /*! RESERVED4 - Reserved. */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK (0xE00000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT (21U) /*! VC0_P_TLP_Q_MODE - Reserved. */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK (0x3000000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT (24U) /*! VC0_P_HDR_SCALE - VC0 Scale Posted Header Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK (0xC000000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT (26U) /*! VC0_P_DATA_SCALE - VC0 Scale Posted Data Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK (0x30000000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT (28U) /*! RESERVED5 - Reserved. */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK (0x40000000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT (30U) /*! TLP_TYPE_ORDERING_VC0 - TLP Type Ordering for VC0. * 0b1..PCIe ordering rules (recommended) * 0b0..Strict ordering: posted, completion, then non-posted */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK (0x80000000U) #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT (31U) /*! VC_ORDERING_RX_Q - VC Ordering for Receive Queues. * 0b0..Round robin * 0b1..Strict ordering, higher numbered VCs have higher priority */ #define PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT)) & PCIE_EP_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK) /*! @} */ /*! @name VC0_NP_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Non-Posted Receive Queue Control. */ /*! @{ */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK (0xFFFU) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT (0U) /*! VC0_NP_DATA_CREDIT - VC0 Non-Posted Data Credits. * 0b111111111111..Max value * 0b000000000000..Zero value */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT)) & PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK (0xFF000U) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT (12U) /*! VC0_NP_HEADER_CREDIT - VC0 Non-Posted Header Credits. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT)) & PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK (0x100000U) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT (20U) /*! RESERVED6 - Reserved. */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT)) & PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK (0xE00000U) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT (21U) /*! VC0_NP_TLP_Q_MODE - Reserved. */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT)) & PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK (0x3000000U) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT (24U) /*! VC0_NP_HDR_SCALE - VC0 Scale Non-Posted Header Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT)) & PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK (0xC000000U) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT (26U) /*! VC0_NP_DATA_SCALE - VC0 Scale Non-Posted Data Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT)) & PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK (0xF0000000U) #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT (28U) /*! RESERVED7 - Reserved. */ #define PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT)) & PCIE_EP_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK) /*! @} */ /*! @name VC0_CPL_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Completion Receive Queue Control. */ /*! @{ */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK (0xFFFU) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT (0U) /*! VC0_CPL_DATA_CREDIT - VC0 Completion Data Credits. * 0b111111111111..Max value * 0b000000000000..Zero value */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT)) & PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK (0xFF000U) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT (12U) /*! VC0_CPL_HEADER_CREDIT - VC0 Completion Header Credits. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT)) & PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK (0x100000U) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT (20U) /*! RESERVED8 - Reserved. */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT)) & PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK (0xE00000U) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT (21U) /*! VC0_CPL_TLP_Q_MODE - Reserved. */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT)) & PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK (0x3000000U) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT (24U) /*! VC0_CPL_HDR_SCALE - VC0 Scale CPL Header Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT)) & PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK (0xC000000U) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT (26U) /*! VC0_CPL_DATA_SCALE - VC0 Scale CPL Data Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT)) & PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK (0xF0000000U) #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT (28U) /*! RESERVED9 - Reserved. */ #define PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT)) & PCIE_EP_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK) /*! @} */ /*! @name GEN2_CTRL_OFF - Link Width and Speed Change Control Register. */ /*! @{ */ #define PCIE_EP_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK (0xFFU) #define PCIE_EP_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT (0U) /*! FAST_TRAINING_SEQ - Sets the Number of Fast Training Sequences (N_FTS) that the controller * advertises as its N_FTS during Gen2 or Gen3 link training. */ #define PCIE_EP_GEN2_CTRL_OFF_FAST_TRAINING_SEQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK) #define PCIE_EP_GEN2_CTRL_OFF_NUM_OF_LANES_MASK (0x1F00U) #define PCIE_EP_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT (8U) /*! NUM_OF_LANES - Predetermined Number of Lanes. * 0b00001..1 lane * 0b00010..2 lanes * 0b00011..3 lanes */ #define PCIE_EP_GEN2_CTRL_OFF_NUM_OF_LANES(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_NUM_OF_LANES_MASK) #define PCIE_EP_GEN2_CTRL_OFF_PRE_DET_LANE_MASK (0xE000U) #define PCIE_EP_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT (13U) /*! PRE_DET_LANE - Predetermined Lane for Auto Flip. */ #define PCIE_EP_GEN2_CTRL_OFF_PRE_DET_LANE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_PRE_DET_LANE_MASK) #define PCIE_EP_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK (0x10000U) #define PCIE_EP_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT (16U) /*! AUTO_LANE_FLIP_CTRL_EN - Enable Auto flipping of the lanes. */ #define PCIE_EP_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK) #define PCIE_EP_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK (0x20000U) #define PCIE_EP_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT (17U) /*! DIRECT_SPEED_CHANGE - Directed Speed Change. * 0b0..Clear * 0b1..Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. */ #define PCIE_EP_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK) #define PCIE_EP_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK (0x40000U) #define PCIE_EP_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT (18U) /*! CONFIG_PHY_TX_CHANGE - Config PHY Tx Swing. * 0b0..Full Swing * 0b1..Low Swing */ #define PCIE_EP_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK) #define PCIE_EP_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK (0x80000U) #define PCIE_EP_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT (19U) /*! CONFIG_TX_COMP_RX - Config Tx Compliance Receive Bit. * 0b0..Clear * 0b1..When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). */ #define PCIE_EP_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK) #define PCIE_EP_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK (0x100000U) #define PCIE_EP_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT (20U) /*! SEL_DEEMPHASIS - Used to set the de-emphasis level for upstream ports. * 0b1..-3.5 dB * 0b0..-6 dB */ #define PCIE_EP_GEN2_CTRL_OFF_SEL_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK) #define PCIE_EP_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK (0x200000U) #define PCIE_EP_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT (21U) /*! GEN1_EI_INFERENCE - Electrical Idle Inference Mode at Gen1 Rate. * 0b0..Use RxElecIdle signal to infer Electrical Idle * 0b1..Use RxValid signal to infer Electrical Idle */ #define PCIE_EP_GEN2_CTRL_OFF_GEN1_EI_INFERENCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK) #define PCIE_EP_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_MASK (0x400000U) #define PCIE_EP_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_SHIFT (22U) /*! SELECT_DEEMPH_VAR_MUX - The select_deemphasis variable for DSP on entry to Recovery. * 0b1..The value from the Selectable De-emphasis field in the Link Control 2 register * 0b0..The value requested by USP in Recovery.RcvrLock state through Tx TS1s from USP */ #define PCIE_EP_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_MASK) #define PCIE_EP_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_MASK (0x800000U) #define PCIE_EP_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_SHIFT (23U) /*! SELECTABLE_DEEMPH_BIT_MUX - The selectable deemphasis bit (Symbol 4 bit 6) of the transmitted TS2 Ordered Sets for DSP in Recovery. * 0b0..The value from the Selectable De-emphasis field in the Link Control 2 register * 0b1..The value requested by USP in Recovery.RcvrLock state through Tx TS1s from USP */ #define PCIE_EP_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_MASK) #define PCIE_EP_GEN2_CTRL_OFF_LANE_UNDER_TEST_MASK (0xF000000U) #define PCIE_EP_GEN2_CTRL_OFF_LANE_UNDER_TEST_SHIFT (24U) /*! LANE_UNDER_TEST - The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. * 0b0001..One * 0b0000..Zero */ #define PCIE_EP_GEN2_CTRL_OFF_LANE_UNDER_TEST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_LANE_UNDER_TEST_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_LANE_UNDER_TEST_MASK) #define PCIE_EP_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MASK (0x40000000U) #define PCIE_EP_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SHIFT (30U) /*! FORCE_LANE_FLIP - Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_GEN2_CTRL_OFF_FORCE_LANE_FLIP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SHIFT)) & PCIE_EP_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MASK) /*! @} */ /*! @name PHY_STATUS_OFF - PHY Status Register. */ /*! @{ */ #define PCIE_EP_PHY_STATUS_OFF_PHY_STATUS_MASK (0xFFFFFFFFU) #define PCIE_EP_PHY_STATUS_OFF_PHY_STATUS_SHIFT (0U) /*! PHY_STATUS - PHY Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_EP_PHY_STATUS_OFF_PHY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_STATUS_OFF_PHY_STATUS_SHIFT)) & PCIE_EP_PHY_STATUS_OFF_PHY_STATUS_MASK) /*! @} */ /*! @name PHY_CONTROL_OFF - PHY Control Register. */ /*! @{ */ #define PCIE_EP_PHY_CONTROL_OFF_PHY_CONTROL_MASK (0xFFFFFFFFU) #define PCIE_EP_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT (0U) /*! PHY_CONTROL - PHY Control. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_EP_PHY_CONTROL_OFF_PHY_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT)) & PCIE_EP_PHY_CONTROL_OFF_PHY_CONTROL_MASK) /*! @} */ /*! @name TRGT_MAP_CTRL_OFF - Programmable Target Map Control Register. */ /*! @{ */ #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK (0x3FU) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT (0U) /*! TARGET_MAP_PF - Target Values for each BAR on the PF Function selected by the index number. */ #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT)) & PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK (0x40U) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT (6U) /*! TARGET_MAP_ROM - Target Value for the ROM page of the PF Function selected by the index number. */ #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT)) & PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK (0xE000U) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT (13U) /*! TARGET_MAP_RESERVED_13_15 - Reserved. */ #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT)) & PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK (0x1F0000U) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT (16U) /*! TARGET_MAP_INDEX - The number of the PF Function on which the Target Values are set. */ #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT)) & PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK (0xFFE00000U) #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT (21U) /*! TARGET_MAP_RESERVED_21_31 - Reserved. */ #define PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT)) & PCIE_EP_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK) /*! @} */ /*! @name CLOCK_GATING_CTRL_OFF - Clock Gating Control Register. */ /*! @{ */ #define PCIE_EP_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK (0x1U) #define PCIE_EP_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT (0U) /*! RADM_CLK_GATING_EN - RADM Clock Gating Enable. * 0b0..Disable * 0b1..Enable (default) */ #define PCIE_EP_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT)) & PCIE_EP_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK) #define PCIE_EP_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MASK (0x2U) #define PCIE_EP_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SHIFT (1U) /*! AXI_CLK_GATING_EN - AXI Clock Gating Enable. * 0b0..Disable * 0b1..Enable (default) */ #define PCIE_EP_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SHIFT)) & PCIE_EP_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MASK) /*! @} */ /*! @name GEN3_RELATED_OFF - Gen3 Control Register. */ /*! @{ */ #define PCIE_EP_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MASK (0x1U) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SHIFT (0U) /*! GEN3_ZRXDC_NONCOMPL - Gen3 Receiver Impedance ZRX-DC Not Compliant. * 0b0..The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. * 0b1..The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. */ #define PCIE_EP_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MASK) #define PCIE_EP_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_MASK (0x2U) #define PCIE_EP_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_SHIFT (1U) /*! NO_SEED_VALUE_CHANGE - If this bit is set to 1, the seed value of LFSR for scrambler at Gen3 rate does not change after LinkUp = 1. * 0b1..Not Change */ #define PCIE_EP_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_MASK) #define PCIE_EP_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MASK (0x100U) #define PCIE_EP_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SHIFT (8U) /*! DISABLE_SCRAMBLER_GEN_3 - Disable Scrambler for Gen3 and Gen4 Data Rate. */ #define PCIE_EP_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MASK) #define PCIE_EP_GEN3_RELATED_OFF_EQ_PHASE_2_3_MASK (0x200U) #define PCIE_EP_GEN3_RELATED_OFF_EQ_PHASE_2_3_SHIFT (9U) /*! EQ_PHASE_2_3 - Equalization Phase 2 and Phase 3 Disable. * 0b0..Rx equalization in phase 0/1 * 0b1..No Rx equalization */ #define PCIE_EP_GEN3_RELATED_OFF_EQ_PHASE_2_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_EQ_PHASE_2_3_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_EQ_PHASE_2_3_MASK) #define PCIE_EP_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MASK (0x400U) #define PCIE_EP_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SHIFT (10U) /*! EQ_EIEOS_CNT - Equalization EIEOS Count Reset Disable. * 0b1..Disable */ #define PCIE_EP_GEN3_RELATED_OFF_EQ_EIEOS_CNT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MASK) #define PCIE_EP_GEN3_RELATED_OFF_EQ_REDO_MASK (0x800U) #define PCIE_EP_GEN3_RELATED_OFF_EQ_REDO_SHIFT (11U) /*! EQ_REDO - Equalization Redo Disable. */ #define PCIE_EP_GEN3_RELATED_OFF_EQ_REDO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_EQ_REDO_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_EQ_REDO_MASK) #define PCIE_EP_GEN3_RELATED_OFF_RXEQ_PH01_EN_MASK (0x1000U) #define PCIE_EP_GEN3_RELATED_OFF_RXEQ_PH01_EN_SHIFT (12U) /*! RXEQ_PH01_EN - Rx Equalization Phase 0/Phase 1 Hold Enable. * 0b1..No Tx equalization * 0b0..Tx equalization only in phase 2/3 */ #define PCIE_EP_GEN3_RELATED_OFF_RXEQ_PH01_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_RXEQ_PH01_EN_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_RXEQ_PH01_EN_MASK) #define PCIE_EP_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MASK (0x2000U) #define PCIE_EP_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SHIFT (13U) /*! RXEQ_RGRDLESS_RXTS - RXEQ_RGRDLESS_RXTS * 0b0..mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. * 0b1..mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not. */ #define PCIE_EP_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MASK) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MASK (0x10000U) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SHIFT (16U) /*! GEN3_EQUALIZATION_DISABLE - Equalization Disable. */ #define PCIE_EP_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MASK) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MASK (0x20000U) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SHIFT (17U) /*! GEN3_DLLP_XMT_DELAY_DISABLE - DLLP Transmission Delay Disable. */ #define PCIE_EP_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MASK) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MASK (0x40000U) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SHIFT (18U) /*! GEN3_DC_BALANCE_DISABLE - DC Balance Disable. */ #define PCIE_EP_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MASK) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MASK (0x800000U) #define PCIE_EP_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SHIFT (23U) /*! GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE - Eq InvalidRequest and RxEqEval Different Time Assertion Disable. */ #define PCIE_EP_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SHIFT)) & PCIE_EP_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MASK) /*! @} */ /*! @name GEN3_EQ_CONTROL_OFF - Gen3 EQ Control Register. */ /*! @{ */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MASK (0xFU) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SHIFT (0U) /*! GEN3_EQ_FB_MODE - Feedback Mode. * 0b0000..Direction Change * 0b0001..Figure Of Merit */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MASK (0x10U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SHIFT (4U) /*! GEN3_EQ_PHASE23_EXIT_MODE - Behavior After 24 ms Timeout (when optimal settings are not found). * 0b1..USP: Recovery.Equalization.Phase3; DSP: Recovery.Equalization.RcvrLock * 0b0..Recovery.Speed */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MASK (0x20U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SHIFT (5U) /*! GEN3_EQ_EVAL_2MS_DISABLE - Phase2_3 2 ms Timeout Disable. * 0b0..Abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout * 0b1..Ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to * respond to the assertion of RxEqEval. */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MASK (0x40U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SHIFT (6U) /*! GEN3_LOWER_RATE_EQ_REDO_ENABLE - Support EQ redo and lower rate change. * 0b0..Not supported * 0b1..Supported */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MASK (0xFFFF00U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SHIFT (8U) /*! GEN3_EQ_PSET_REQ_VEC - Preset Request Vector. * 0b1111111111111111..Max value * 0b0000000000000000..Zero value */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MASK (0x1000000U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SHIFT (24U) /*! GEN3_EQ_FOM_INC_INITIAL_EVAL - Include Initial FOM. * 0b0..Do not include * 0b1..Include */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MASK (0x2000000U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SHIFT (25U) /*! GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MASK (0x4000000U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SHIFT (26U) /*! GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP - Request controller to send back-to-back EIEOS in Recovery. * 0b0..Do not request * 0b1..Request */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_MASK (0x38000000U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_SHIFT (27U) /*! GEN3_EQ_REQ_NUM - The number of back-to-back equalization redo requests at a given Gen3, Gen4 and Gen5 data rate for USP. * 0b111..Max value * 0b000..Min value */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_MASK) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_MASK (0x40000000U) #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_SHIFT (30U) /*! GEN3_SUPPORT_FINITE_EQ_REQUEST - Support finite EQ requests for USP. * 0b1..Support * 0b0..Do not support */ #define PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_SHIFT)) & PCIE_EP_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_MASK) /*! @} */ /*! @name GEN3_EQ_FB_MODE_DIR_CHANGE_OFF - Gen3 EQ Direction Change Feedback Mode Control Register. */ /*! @{ */ #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MASK (0x1FU) #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SHIFT (0U) /*! GEN3_EQ_FMDC_T_MIN_PHASE23 - Minimum Time (in ms) To Remain in EQ Master Phase. * 0b11000..Max value * 0b00000..Min value */ #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SHIFT)) & PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MASK) #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MASK (0x3E0U) #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SHIFT (5U) /*! GEN3_EQ_FMDC_N_EVALS - Convergence Window Depth. * 0b11111..Maximum of CX_GEN3_EQ_COEFQ_DEPTH * 0b00000..Min value */ #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SHIFT)) & PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MASK) #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MASK (0x3C00U) #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SHIFT (10U) /*! GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - Convergence Window Aperture for C-1. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SHIFT)) & PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MASK) #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MASK (0x3C000U) #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SHIFT (14U) /*! GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA - Convergence Window Aperture for C+1. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SHIFT)) & PCIE_EP_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MASK) /*! @} */ /*! @name ORDER_RULE_CTRL_OFF - Order Rule Control Register. */ /*! @{ */ #define PCIE_EP_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK (0xFFU) #define PCIE_EP_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT (0U) /*! NP_PASS_P - Non-Posted Passing Posted Ordering Rule Control. * 0b00000000..NP cannot pass P (recommended). * 0b00000001..NP can pass P */ #define PCIE_EP_ORDER_RULE_CTRL_OFF_NP_PASS_P(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT)) & PCIE_EP_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK) #define PCIE_EP_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK (0xFF00U) #define PCIE_EP_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT (8U) /*! CPL_PASS_P - Completion Passing Posted Ordering Rule Control. * 0b00000000..CPL cannot pass P (recommended) * 0b00000001..CPL can pass P */ #define PCIE_EP_ORDER_RULE_CTRL_OFF_CPL_PASS_P(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT)) & PCIE_EP_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK) /*! @} */ /*! @name PIPE_LOOPBACK_CONTROL_OFF - PIPE Loopback Control Register. */ /*! @{ */ #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK (0xFFFFU) #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT (0U) /*! LPBK_RXVALID - LPBK_RXVALID is an internally reserved field. */ #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT)) & PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK) #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK (0x3F0000U) #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT (16U) /*! RXSTATUS_LANE - RXSTATUS_LANE is an internally reserved field. */ #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT)) & PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK) #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK (0x7000000U) #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT (24U) /*! RXSTATUS_VALUE - RXSTATUS_VALUE is an internally reserved field. */ #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT)) & PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK) #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK (0x80000000U) #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT (31U) /*! PIPE_LOOPBACK - PIPE Loopback Enable. */ #define PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT)) & PCIE_EP_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK) /*! @} */ /*! @name MISC_CONTROL_1_OFF - DBI Read-Only Write Enable Register. */ /*! @{ */ #define PCIE_EP_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK (0x1U) #define PCIE_EP_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT (0U) /*! DBI_RO_WR_EN - Write to RO Registers Using DBI. * 0b0..Clear * 0b1..Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. */ #define PCIE_EP_MISC_CONTROL_1_OFF_DBI_RO_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK (0x2U) #define PCIE_EP_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT (1U) /*! DEFAULT_TARGET - Default target for an IO or MEM request with UR/CA/CRS received. * 0b0..The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion * with UR status is generated for non-posted requests. * 0b1..The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application. */ #define PCIE_EP_MISC_CONTROL_1_OFF_DEFAULT_TARGET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK (0x4U) #define PCIE_EP_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT (2U) /*! UR_CA_MASK_4_TRGT1 - UR_CA_MASK_4_TRGT1 * 0b0..Clear * 0b1..Set */ #define PCIE_EP_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK (0x8U) #define PCIE_EP_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT (3U) /*! SIMPLIFIED_REPLAY_TIMER - Enables Simplified Replay Timer (Gen4). * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MASK (0x10U) #define PCIE_EP_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SHIFT (4U) /*! DISABLE_AUTO_LTR_CLR_MSG - Disable the autonomous generation of LTR clear message in upstream port. * 0b0..Allow the autonomous generation of LTR clear message. * 0b1..Disable the autonomous generation of LTR clear message. */ #define PCIE_EP_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK (0x20U) #define PCIE_EP_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT (5U) /*! ARI_DEVICE_NUMBER - When ARI is enabled, this field enables use of the device ID. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MASK (0x40U) #define PCIE_EP_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SHIFT (6U) /*! CPLQ_MNG_EN - This field enables the Completion Queue Management feature. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_MISC_CONTROL_1_OFF_CPLQ_MNG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MASK (0x80U) #define PCIE_EP_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SHIFT (7U) /*! CFG_TLP_BYPASS_EN_REG - Setting of this field defines how to decide the destination of Configuration requests. * 0b1..Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG, regardless the value of CONFIG_LIMIT_REG. * 0b0..Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG, depending on the * setting of CONFIG_LIMIT_REG. Refer to the definition of CONFIG_LIMIT_REG for details. */ #define PCIE_EP_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MASK (0x3FF00U) #define PCIE_EP_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SHIFT (8U) /*! CONFIG_LIMIT_REG - Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. */ #define PCIE_EP_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MASK (0xC0000U) #define PCIE_EP_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SHIFT (18U) /*! TARGET_ABOVE_CONFIG_LIMIT_REG - TARGET_ABOVE_CONFIG_LIMIT_REG * 0b01..ELBI * 0b10..TRGT1 */ #define PCIE_EP_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MASK (0x100000U) #define PCIE_EP_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SHIFT (20U) /*! P2P_TRACK_CPL_TO_REG - Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. * 0b0..Do not track completion * 0b1..Track completion */ #define PCIE_EP_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MASK (0x200000U) #define PCIE_EP_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SHIFT (21U) /*! P2P_ERR_RPT_CTRL - Determines whether to enable Peer to Peer (P2P) error reporting. * 0b0..Disable P2P error reporting * 0b1..Enable P2P error reporting */ #define PCIE_EP_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MASK) #define PCIE_EP_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_MASK (0x400000U) #define PCIE_EP_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_SHIFT (22U) /*! PORT_LOGIC_WR_DISABLE - Disable port logic register write from wire side. */ #define PCIE_EP_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_SHIFT)) & PCIE_EP_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_MASK) /*! @} */ /*! @name MULTI_LANE_CONTROL_OFF - UpConfigure Multi-lane Control Register. */ /*! @{ */ #define PCIE_EP_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK (0x3FU) #define PCIE_EP_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT (0U) /*! TARGET_LINK_WIDTH - Target Link Width. * 0b000000..Controller does not start upconfigure or autonomous width downsizing in the Configuration state. * 0b000001..x1 * 0b010000..x16 * 0b000010..x2 * 0b100000..x32 * 0b000100..x4 * 0b001000..x8 */ #define PCIE_EP_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT)) & PCIE_EP_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK) #define PCIE_EP_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK (0x40U) #define PCIE_EP_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT (6U) /*! DIRECT_LINK_WIDTH_CHANGE - Directed Link Width Change. * 0b0..Clear * 0b1..The controller always moves to Configuration state through Recovery state when this bit is set to '1'. */ #define PCIE_EP_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT)) & PCIE_EP_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK) #define PCIE_EP_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK (0x80U) #define PCIE_EP_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT (7U) /*! UPCONFIGURE_SUPPORT - Upconfigure Support. */ #define PCIE_EP_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT)) & PCIE_EP_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK) /*! @} */ /*! @name PHY_INTEROP_CTRL_OFF - PHY Interoperability Control Register. */ /*! @{ */ #define PCIE_EP_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK (0x7FU) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT (0U) /*! RXSTANDBY_CONTROL - Rxstandby Control. * 0b1111111..Max value * 0b0000000..Zero value */ #define PCIE_EP_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK (0x100U) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT (8U) /*! L1SUB_EXIT_MODE - L1 Exit Control Using phy_mac_pclkack_n. * 0b1..Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. * 0b0..Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1. */ #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK (0x200U) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT (9U) /*! L1_NOWAIT_P1 - L1 entry control bit. * 0b1..Controller does not wait for PHY to acknowledge transition to P1 before entering L1. * 0b0..Controller waits for the PHY to acknowledge transition to P1 before entering L1. */ #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK (0x400U) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT (10U) /*! L1_CLK_SEL - L1 Clock control bit. * 0b0..Controller requests aux_clk switch and core_clk gating in L1. * 0b1..Controller does not request aux_clk switch and core_clk gating in L1. */ #define PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_MASK (0x3FFFF000U) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_SHIFT (12U) /*! PHY_RST_TIMER - Control the duration of the PHY reset (PIPE and PMA). * 0b111111111111111111..Max value. * 0b000000000000000000..Zero value. */ #define PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_MASK) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_MASK (0x40000000U) #define PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_SHIFT (30U) /*! PHY_PERST_ON_WARM_RESET - Control whether the Power Management Controller will drive * pm_req_phy_perst during a Warm Reset (PERST# assertion without cycling of power). * 0b0..DO NOT Drive pm_req_phy_perst during a Warm Reset. * 0b1..Drive pm_req_phy_perst during a Warm Reset. */ #define PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_MASK) /*! @} */ /*! @name TRGT_CPL_LUT_DELETE_ENTRY_OFF - TRGT_CPL_LUT Delete Entry Control register. */ /*! @{ */ #define PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK (0x7FFFFFFFU) #define PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT (0U) /*! LOOK_UP_ID - This number selects one entry to delete of the TRGT_CPL_LUT. */ #define PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT)) & PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK) #define PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK (0x80000000U) #define PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT (31U) /*! DELETE_EN - This is a one-shot bit. * 0b0..Clear * 0b1..A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. */ #define PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT)) & PCIE_EP_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK) /*! @} */ /*! @name LINK_FLUSH_CONTROL_OFF - Link Reset Request Flush Control Register. */ /*! @{ */ #define PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK (0x1U) #define PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT (0U) /*! AUTO_FLUSH_EN - AUTO_FLUSH_EN * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT)) & PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK) #define PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_MASK (0xFF000000U) #define PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_SHIFT (24U) /*! AUTO_FLUSH_TIMEOUT - Timeout Value (ms) for automatic flushing. */ #define PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_SHIFT)) & PCIE_EP_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_MASK) /*! @} */ /*! @name AMBA_ERROR_RESPONSE_DEFAULT_OFF - AXI Bridge Slave Error Response Register. */ /*! @{ */ #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK (0x1U) #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT (0U) /*! AMBA_ERROR_RESPONSE_GLOBAL - Global Slave Error Response Mapping. * 0b1..SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping) * 0b0..OKAY (with FFFF data for non-posted requests) */ #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT)) & PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK) #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK (0x4U) #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT (2U) /*! AMBA_ERROR_RESPONSE_VENDORID - Vendor ID Non-existent Slave Error Response Mapping. * 0b1..SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping) * 0b0..OKAY (with FFFF data). */ #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT)) & PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK) #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK (0x18U) #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT (3U) /*! AMBA_ERROR_RESPONSE_CRS - CRS Slave Error Response Mapping. * 0b00..OKAY * 0b01..OKAY with all FFFF_FFFF data for all CRS completions * 0b10..OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions * 0b11..SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping) */ #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT)) & PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK) #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK (0xFC00U) #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT (10U) /*! AMBA_ERROR_RESPONSE_MAP - AXI Slave Response Error Map. * 0b111111..Max value * 0b000000..Zero value */ #define PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT)) & PCIE_EP_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK) /*! @} */ /*! @name AMBA_LINK_TIMEOUT_OFF - Link Down AXI Bridge Slave Timeout Register. */ /*! @{ */ #define PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK (0xFFU) #define PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT (0U) /*! LINK_TIMEOUT_PERIOD_DEFAULT - Timeout Value (ms). */ #define PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT)) & PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK) #define PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK (0x100U) #define PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT (8U) /*! LINK_TIMEOUT_ENABLE_DEFAULT - Disable Flush. * 0b1..You can disable the flush feature by setting this field to '1'. * 0b0..Enable */ #define PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT)) & PCIE_EP_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK) /*! @} */ /*! @name AMBA_ORDERING_CTRL_OFF - AXI Bridge Ordering Control. */ /*! @{ */ #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK (0x2U) #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT (1U) /*! AX_SNP_EN - AXI Serialize Non-Posted Requests Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT)) & PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK) #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK (0x18U) #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT (3U) /*! AX_MSTR_ORDR_P_EVENT_SEL - AXI Master Posted Ordering Event Selector. * 0b01..AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. * 0b00..B'last event: wait for the all of the write responses on the B channel thereby ensuring that the * complete Posted transaction has effectively reached the application slave (default). * 0b11..Reserved * 0b10..W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. */ #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT)) & PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK) #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK (0x80U) #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT (7U) /*! AX_MSTR_ZEROLREAD_FW - AXI Master Zero Length Read Forward to the application. * 0b1..The zero length Read is forward to the application. * 0b0..The zero length Read is terminated at the DW PCIe AXI bridge master */ #define PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT)) & PCIE_EP_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK) /*! @} */ /*! @name COHERENCY_CONTROL_1_OFF - Cache Coherency Control Register 1. */ /*! @{ */ #define PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MASK (0x1U) #define PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SHIFT (0U) /*! CFG_MEMTYPE_VALUE - Sets the memory type for the lower and upper parts of the address space: * 0b1..lower = Memory type; upper = Peripheral * 0b0..lower = Peripheral; upper = Memory */ #define PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MASK) #define PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK (0xFFFFFFFCU) #define PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SHIFT (2U) /*! CFG_MEMTYPE_BOUNDARY_LOW_ADDR - Boundary Lower Address For Memory Type. */ #define PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK) /*! @} */ /*! @name COHERENCY_CONTROL_2_OFF - Cache Coherency Control Register 2. */ /*! @{ */ #define PCIE_EP_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MASK (0xFFFFFFFFU) #define PCIE_EP_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SHIFT (0U) /*! CFG_MEMTYPE_BOUNDARY_HIGH_ADDR - Boundary Upper Address For Memory Type. */ #define PCIE_EP_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MASK) /*! @} */ /*! @name COHERENCY_CONTROL_3_OFF - Cache Coherency Control Register 3. */ /*! @{ */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_MASK (0x3U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_SHIFT (0U) /*! CFG_MSTR_ARDOMAIN_MODE - Master Read DOMAIN Signal Behavior. * 0b00..set automatically by the AXI master * 0b01..set the value of the corresponding bit of the CFG_MSTR_ARDOMAIN_VALUE field */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_MASK) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MASK (0x78U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SHIFT (3U) /*! CFG_MSTR_ARCACHE_MODE - Master Read CACHE Signal Behavior. * 0b0000..set automatically by the AXI master * 0b0001..set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MASK) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_MASK (0x300U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_SHIFT (8U) /*! CFG_MSTR_AWDOMAIN_MODE - Master Write DOMAIN Signal Behavior. * 0b00..set automatically by the AXI master * 0b01..set by the value of the corresponding bit of the CFG_MSTR_AWDOMAIN_VALUE field */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_MASK) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MASK (0x7800U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SHIFT (11U) /*! CFG_MSTR_AWCACHE_MODE - Master Write CACHE Signal Behavior. * 0b0000..set automatically by the AXI master * 0b0001..set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MASK) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_MASK (0x30000U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_SHIFT (16U) /*! CFG_MSTR_ARDOMAIN_VALUE - Master Read DOMAIN Signal Value. */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_MASK) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MASK (0x780000U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SHIFT (19U) /*! CFG_MSTR_ARCACHE_VALUE - Master Read CACHE Signal Value. */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MASK) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_MASK (0x3000000U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_SHIFT (24U) /*! CFG_MSTR_AWDOMAIN_VALUE - Master Write DOMAIN Signal Value. */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_MASK) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MASK (0x78000000U) #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SHIFT (27U) /*! CFG_MSTR_AWCACHE_VALUE - Master Write CACHE Signal Value. */ #define PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SHIFT)) & PCIE_EP_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MASK) /*! @} */ /*! @name AXI_MSTR_MSG_ADDR_LOW_OFF - Lower 32-bits of the Programmable AXI Address. */ /*! @{ */ #define PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK (0xFFFU) #define PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT (0U) /*! CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED - Reserved for future use. */ #define PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT)) & PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK) #define PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK (0xFFFFF000U) #define PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT (12U) /*! CFG_AXIMSTR_MSG_ADDR_LOW - Lower 20-bits of the programmable AXI address for Messages. */ #define PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT)) & PCIE_EP_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK) /*! @} */ /*! @name AXI_MSTR_MSG_ADDR_HIGH_OFF - Upper 32-bits of the Programmable AXI Address. */ /*! @{ */ #define PCIE_EP_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK (0xFFFFFFFFU) #define PCIE_EP_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT (0U) /*! CFG_AXIMSTR_MSG_ADDR_HIGH - Upper 32 bits of the programmable AXI address for Messages. */ #define PCIE_EP_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT)) & PCIE_EP_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK) /*! @} */ /*! @name PCIE_VERSION_NUMBER_OFF - PCIe Controller IIP Release Version Number. */ /*! @{ */ #define PCIE_EP_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK (0xFFFFFFFFU) #define PCIE_EP_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT (0U) /*! VERSION_NUMBER - Version Number. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_EP_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT)) & PCIE_EP_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK) /*! @} */ /*! @name PCIE_VERSION_TYPE_OFF - PCIe Controller IIP Release Version Type. */ /*! @{ */ #define PCIE_EP_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK (0xFFFFFFFFU) #define PCIE_EP_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT (0U) /*! VERSION_TYPE - Version Type. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_EP_PCIE_VERSION_TYPE_OFF_VERSION_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT)) & PCIE_EP_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK) /*! @} */ /*! @name PL_APP_BUS_DEV_NUM_STATUS_OFF - Application driven bus and device number register. */ /*! @{ */ #define PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_MASK (0xF8U) #define PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_SHIFT (3U) /*! RC_DSW_DEV_NUM - This field reflects the value of device number driven on app_device_num input signal by your application. */ #define PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_SHIFT)) & PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_MASK) #define PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_MASK (0xFF00U) #define PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_SHIFT (8U) /*! RC_DSW_BUS_NUM - This field reflects the value of bus number driven on app_bus_num input signal by your application. */ #define PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_SHIFT)) & PCIE_EP_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_MASK) /*! @} */ /*! @name PCIPM_TRAFFIC_CTRL_OFF - TLP Traffic during Non-D0 State Control Register. */ /*! @{ */ #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_MASK (0x1U) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_SHIFT (0U) /*! PCIPM_VDM_TRAFFIC_BLOCKED - This field indicates that VDM Message TLPs are blocked during non-D0 states. */ #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_SHIFT)) & PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_MASK) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_MASK (0x2U) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_SHIFT (1U) /*! PCIPM_NEW_TLP_CLIENT0_BLOCKED - This field indicates that all TLPs transmitted by Client 0 interface are blocked during non-D0 states. */ #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_SHIFT)) & PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_MASK) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_MASK (0x4U) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_SHIFT (2U) /*! PCIPM_NEW_TLP_CLIENT1_BLOCKED - This field indicates that all TLPs transmitted by Client 1 interface are blocked during non-D0 states. */ #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_SHIFT)) & PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_MASK) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_MASK (0x8U) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_SHIFT (3U) /*! PCIPM_NEW_TLP_CLIENT2_BLOCKED - This field indicates that all TLPs transmitted by Client 2 interface are blocked during non-D0 states. */ #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_SHIFT)) & PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_MASK) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_MASK (0xF0U) #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_SHIFT (4U) /*! PCIPM_RESERVED_4_7 - Reserved. */ #define PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_SHIFT)) & PCIE_EP_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_MASK) /*! @} */ /*! @name PL_LTR_LATENCY_OFF - LTR Latency Register. */ /*! @{ */ #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MASK (0x3FFU) #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SHIFT (0U) /*! SNOOP_LATENCY_VALUE - Snoop Latency Value. */ #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SHIFT)) & PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MASK) #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MASK (0x1C00U) #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SHIFT (10U) /*! SNOOP_LATENCY_SCALE - Snoop Latency Scale. */ #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SHIFT)) & PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MASK) #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MASK (0x8000U) #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SHIFT (15U) /*! SNOOP_LATENCY_REQUIRE - Snoop Latency Requirement. */ #define PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SHIFT)) & PCIE_EP_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MASK) #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MASK (0x3FF0000U) #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SHIFT (16U) /*! NO_SNOOP_LATENCY_VALUE - No Snoop Latency Value. */ #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SHIFT)) & PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MASK) #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MASK (0x1C000000U) #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SHIFT (26U) /*! NO_SNOOP_LATENCY_SCALE - No Snoop Latency Scale. */ #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SHIFT)) & PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MASK) #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MASK (0x80000000U) #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SHIFT (31U) /*! NO_SNOOP_LATENCY_REQUIRE - No Snoop Latency Requirement. */ #define PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SHIFT)) & PCIE_EP_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MASK) /*! @} */ /*! @name AUX_CLK_FREQ_OFF - Auxiliary Clock Frequency Control Register. */ /*! @{ */ #define PCIE_EP_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK (0x3FFU) #define PCIE_EP_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT (0U) /*! AUX_CLK_FREQ - The aux_clk frequency in MHz. */ #define PCIE_EP_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT)) & PCIE_EP_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK) /*! @} */ /*! @name L1_SUBSTATES_OFF - L1 Substates Timing Register. */ /*! @{ */ #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK (0x3U) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT (0U) /*! L1SUB_T_POWER_OFF - Duration (in 1us units) of L1. * 0b11..Max value * 0b00..Min value */ #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT)) & PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK (0x3CU) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT (2U) /*! L1SUB_T_L1_2 - Duration (in 1us units) of L1. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_L1_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT)) & PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_MASK (0xC0U) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_SHIFT (6U) /*! L1SUB_T_PCLKACK_LOW - Lower 2-bits of L1SUB_T_PCLKACK. * 0b11..Max value * 0b00..Min value */ #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_SHIFT)) & PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_MASK) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MASK (0x100U) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SHIFT (8U) /*! L1SUB_LOW_POWER_CLOCK_SWITCH_MODE - L1SUB_LOW_POWER_CLOCK_SWITCH_MODE * 0b0..The reference clock may be gated off when CLKREQ# is de-asserted. * 0b1..The reference clock shall be kept running regardless of the CLKREQ# setting. */ #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SHIFT)) & PCIE_EP_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MASK) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_MASK (0x3E00U) #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_SHIFT (9U) /*! L1SUB_T_PCLKACK_HIGH - Higher 5-bits of L1SUB_T_PCLKACK. * 0b11111..Max value * 0b00000..Min value */ #define PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_SHIFT)) & PCIE_EP_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_MASK) /*! @} */ /*! @name POWERDOWN_CTRL_STATUS_OFF - Powerdown Control and Status Register. */ /*! @{ */ #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MASK (0x1U) #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SHIFT (0U) /*! POWERDOWN_FORCE - This field is a one shot field. * 0b0..Clear * 0b1..Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake * regardless of whether the PHY has returned Phystatus. */ #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SHIFT)) & PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MASK) #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_MASK (0x2U) #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_SHIFT (1U) /*! POWERDOWN_VMAIN_ACK - Set this bit to 1 if you do not want to perform the handshake with the power-switch after PERST# assertion. * 0b0..Clear * 0b1..If you do not want to perform the handshake with the power-switch after PERST# assertion. */ #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_SHIFT)) & PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_MASK) #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MASK (0xF0U) #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SHIFT (4U) /*! POWERDOWN_MAC_POWERDOWN - This field represents the Powerdown value driven by the controller to the PHY. */ #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SHIFT)) & PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MASK) #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MASK (0xF00U) #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SHIFT (8U) /*! POWERDOWN_PHY_POWERDOWN - This field represents the Powerdown value that has been acknowledged by the PHY. */ #define PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SHIFT)) & PCIE_EP_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MASK) /*! @} */ /*! @name PHY_INTEROP_CTRL_2_OFF - PHY Interoperability Control 2 Register. */ /*! @{ */ #define PCIE_EP_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_MASK (0x3FU) #define PCIE_EP_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_SHIFT (0U) /*! PMA_PIPE_RST_DELAY_TIMER - Control how long the controller should wait to release a PIPE reset * (pm_req_phy_rst) after releasing a PMA reset (pm_req_phy_perst). * 0b111111..Max value. * 0b001010..Min value. */ #define PCIE_EP_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_MASK) #define PCIE_EP_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_MASK (0xF00U) #define PCIE_EP_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_SHIFT (8U) /*! DSP_PCIPM_L1_ENTER_DELAY - DSP_PCIPM_L1_ENTER_DELAY * 0b1111..Max value. * 0b0000..Zero value. */ #define PCIE_EP_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_SHIFT)) & PCIE_EP_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_MASK) /*! @} */ /*! @name DBI_FUNCTION_BANK_CTRL_REG_OFF - DBI Function Bank Control Register. */ /*! @{ */ #define PCIE_EP_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_MASK (0x1U) #define PCIE_EP_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_SHIFT (0U) /*! DBI_FUNCTION_BANK_CTRL_REG - DBI Function Bank Select. * 0b0..Functions 0 to 31 are accessible from DBI. * 0b1..Functions 32 to 63 are accessible from DBI. */ #define PCIE_EP_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_SHIFT)) & PCIE_EP_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_MASK) /*! @} */ /*! @name UTILITY_OFF - UTILITY register (Reserved). */ /*! @{ */ #define PCIE_EP_UTILITY_OFF_UTILITY_MASK (0xFFFFFFFFU) #define PCIE_EP_UTILITY_OFF_UTILITY_SHIFT (0U) /*! UTILITY - Reserved. */ #define PCIE_EP_UTILITY_OFF_UTILITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_UTILITY_OFF_UTILITY_SHIFT)) & PCIE_EP_UTILITY_OFF_UTILITY_MASK) /*! @} */ /*! @name PM_UTILITY_OFF - PM Shadow of UTILITY register (Reserved). */ /*! @{ */ #define PCIE_EP_PM_UTILITY_OFF_PM_UTILITY_MASK (0xFFFFFFFFU) #define PCIE_EP_PM_UTILITY_OFF_PM_UTILITY_SHIFT (0U) /*! PM_UTILITY - Reserved. */ #define PCIE_EP_PM_UTILITY_OFF_PM_UTILITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_EP_PM_UTILITY_OFF_PM_UTILITY_SHIFT)) & PCIE_EP_PM_UTILITY_OFF_PM_UTILITY_MASK) /*! @} */ /*! * @} */ /* end of group PCIE_EP_Register_Masks */ /* PCIE_EP - Peripheral instance base addresses */ /** Peripheral HSIO__PCIE1__PCIE_EP base address */ #define HSIO__PCIE1__PCIE_EP_BASE (0x4C300000u) /** Peripheral HSIO__PCIE1__PCIE_EP base pointer */ #define HSIO__PCIE1__PCIE_EP ((PCIE_EP_Type *)HSIO__PCIE1__PCIE_EP_BASE) /** Peripheral HSIO__PCIE2__PCIE_EP base address */ #define HSIO__PCIE2__PCIE_EP_BASE (0x4C380000u) /** Peripheral HSIO__PCIE2__PCIE_EP base pointer */ #define HSIO__PCIE2__PCIE_EP ((PCIE_EP_Type *)HSIO__PCIE2__PCIE_EP_BASE) /** Array initializer of PCIE_EP peripheral base addresses */ #define PCIE_EP_BASE_ADDRS { HSIO__PCIE1__PCIE_EP_BASE, HSIO__PCIE2__PCIE_EP_BASE } /** Array initializer of PCIE_EP peripheral base pointers */ #define PCIE_EP_BASE_PTRS { HSIO__PCIE1__PCIE_EP, HSIO__PCIE2__PCIE_EP } /*! * @} */ /* end of group PCIE_EP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCIE_RC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_RC_Peripheral_Access_Layer PCIE_RC Peripheral Access Layer * @{ */ /** PCIE_RC - Register Layout Typedef */ typedef struct { __I uint32_t TYPE1_DEV_ID_VEND_ID_REG; /**< Device ID, RCRB Next offset pointer and Vendor ID Register., offset: 0x0 */ __IO uint32_t TYPE1_STATUS_COMMAND_REG; /**< Status and Command Register., offset: 0x4 */ __I uint32_t TYPE1_CLASS_CODE_REV_ID_REG; /**< Class Code and Revision ID Register., offset: 0x8 */ __IO uint32_t TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG; /**< BIST, Header Type, Latency Timer, and Cache Line Size Register., offset: 0xC */ __IO uint32_t BAR0_REG; /**< BAR0 Register., offset: 0x10 */ __IO uint32_t BAR1_REG; /**< BAR1 Register., offset: 0x14 */ __IO uint32_t SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG; /**< Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register., offset: 0x18 */ __IO uint32_t SEC_STAT_IO_LIMIT_IO_BASE_REG; /**< Secondary Status, and I/O Limit and Base Register., offset: 0x1C */ __IO uint32_t MEM_LIMIT_MEM_BASE_REG; /**< Memory Limit and Base Register., offset: 0x20 */ __IO uint32_t PREF_MEM_LIMIT_PREF_MEM_BASE_REG; /**< Prefetchable Memory Limit and Base Register., offset: 0x24 */ __IO uint32_t PREF_BASE_UPPER_REG; /**< Prefetchable Base Upper 32 Bits Register., offset: 0x28 */ __IO uint32_t PREF_LIMIT_UPPER_REG; /**< Prefetchable Limit Upper 32 Bits Register., offset: 0x2C */ __I uint32_t IO_LIMIT_UPPER_IO_BASE_UPPER_REG; /**< I/O Limit and Base Upper 16 Bits Register., offset: 0x30 */ __I uint32_t TYPE1_CAP_PTR_REG; /**< Capabilities Pointer Register., offset: 0x34 */ __IO uint32_t TYPE1_EXP_ROM_BASE_REG; /**< Expansion ROM BAR Register., offset: 0x38 */ __IO uint32_t BRIDGE_CTRL_INT_PIN_INT_LINE_REG; /**< Bridge Control, Interrupt Pin, and Interrupt Line Register., offset: 0x3C */ __I uint32_t CAP_ID_NXT_PTR_REG; /**< Power Management Capabilities Register., offset: 0x40 */ __IO uint32_t CON_STATUS_REG; /**< Power Management Control and Status Register., offset: 0x44 */ uint8_t RESERVED_0[8]; __IO uint32_t PCI_MSI_CAP_ID_NEXT_CTRL_REG; /**< MSI Capability Header and Message Control Register., offset: 0x50 */ __IO uint32_t MSI_CAP_OFF_04H_REG; /**< Message Address Register for MSI (Offset 04h)., offset: 0x54 */ __IO uint32_t MSI_CAP_OFF_08H_REG; /**< Message Address Register for MSI (Offset 08h)., offset: 0x58 */ __IO uint32_t MSI_CAP_OFF_0CH_REG; /**< Message Address Register for MSI (Offset 0Ch)., offset: 0x5C */ __IO uint32_t MSI_CAP_OFF_10H_REG; /**< Message Address Register for MSI (Offset 10h)., offset: 0x60 */ __I uint32_t MSI_CAP_OFF_14H_REG; /**< Message Address Register for MSI (Offset 14h)., offset: 0x64 */ uint8_t RESERVED_1[8]; __I uint32_t PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG; /**< PCI Express Capabilities, ID, Next Pointer Register., offset: 0x70 */ __I uint32_t DEVICE_CAPABILITIES_REG; /**< Device Capabilities Register., offset: 0x74 */ __IO uint32_t DEVICE_CONTROL_DEVICE_STATUS; /**< Device Control and Device Status Register., offset: 0x78 */ __I uint32_t LINK_CAPABILITIES_REG; /**< Link Capabilities Register., offset: 0x7C */ __IO uint32_t LINK_CONTROL_LINK_STATUS_REG; /**< Link Control and Link Status Register., offset: 0x80 */ __I uint32_t SLOT_CAPABILITIES_REG; /**< Slot Capabilities Register., offset: 0x84 */ __IO uint32_t SLOT_CONTROL_SLOT_STATUS; /**< Slot Control and Status Register., offset: 0x88 */ __IO uint32_t ROOT_CONTROL_ROOT_CAPABILITIES_REG; /**< Root Control and Capabilities Register., offset: 0x8C */ __IO uint32_t ROOT_STATUS_REG; /**< Root Status Register., offset: 0x90 */ __I uint32_t DEVICE_CAPABILITIES2_REG; /**< Device Capabilities 2 Register., offset: 0x94 */ __IO uint32_t DEVICE_CONTROL2_DEVICE_STATUS2_REG; /**< Device Control 2 and Status 2 Register., offset: 0x98 */ __I uint32_t LINK_CAPABILITIES2_REG; /**< Link Capabilities 2 Register., offset: 0x9C */ __IO uint32_t LINK_CONTROL2_LINK_STATUS2_REG; /**< Link Control 2 and Status 2 Register., offset: 0xA0 */ uint8_t RESERVED_2[92]; __I uint32_t AER_EXT_CAP_HDR_OFF; /**< Advanced Error Reporting Extended Capability Header., offset: 0x100 */ __IO uint32_t UNCORR_ERR_STATUS_OFF; /**< Uncorrectable Error Status Register., offset: 0x104 */ __IO uint32_t UNCORR_ERR_MASK_OFF; /**< Uncorrectable Error Mask Register., offset: 0x108 */ __IO uint32_t UNCORR_ERR_SEV_OFF; /**< Uncorrectable Error Severity Register., offset: 0x10C */ __IO uint32_t CORR_ERR_STATUS_OFF; /**< Correctable Error Status Register., offset: 0x110 */ __IO uint32_t CORR_ERR_MASK_OFF; /**< Correctable Error Mask Register., offset: 0x114 */ __IO uint32_t ADV_ERR_CAP_CTRL_OFF; /**< Advanced Error Capabilities and Control Register., offset: 0x118 */ __I uint32_t HDR_LOG_0_OFF; /**< Header Log Register 0., offset: 0x11C */ __I uint32_t HDR_LOG_1_OFF; /**< Header Log Register 1., offset: 0x120 */ __I uint32_t HDR_LOG_2_OFF; /**< Header Log Register 2., offset: 0x124 */ __I uint32_t HDR_LOG_3_OFF; /**< Header Log Register 3., offset: 0x128 */ __IO uint32_t ROOT_ERR_CMD_OFF; /**< Root Error Command Register., offset: 0x12C */ __IO uint32_t ROOT_ERR_STATUS_OFF; /**< Root Error Status Register., offset: 0x130 */ __I uint32_t ERR_SRC_ID_OFF; /**< Error Source Identification Register., offset: 0x134 */ __I uint32_t TLP_PREFIX_LOG_1_OFF; /**< TLP Prefix Log Register 1., offset: 0x138 */ __I uint32_t TLP_PREFIX_LOG_2_OFF; /**< TLP Prefix Log Register 2., offset: 0x13C */ __I uint32_t TLP_PREFIX_LOG_3_OFF; /**< TLP Prefix Log Register 3., offset: 0x140 */ __I uint32_t TLP_PREFIX_LOG_4_OFF; /**< TLP Prefix Log Register 4., offset: 0x144 */ __I uint32_t SPCIE_CAP_HEADER_REG; /**< SPCIE Capability Header., offset: 0x148 */ __IO uint32_t LINK_CONTROL3_REG; /**< Link Control 3 Register., offset: 0x14C */ __IO uint32_t LANE_ERR_STATUS_REG; /**< Lane Error Status Register., offset: 0x150 */ __I uint32_t SPCIE_CAP_OFF_0CH_REG; /**< Lane Equalization Control Register for lanes 1 and 0., offset: 0x154 */ uint8_t RESERVED_3[8]; __I uint32_t L1SUB_CAP_HEADER_REG; /**< L1 Substates Extended Capability Header., offset: 0x160 */ __IO uint32_t L1SUB_CAPABILITY_REG; /**< L1 Substates Capability Register., offset: 0x164 */ __IO uint32_t L1SUB_CONTROL1_REG; /**< L1 Substates Control 1 Register., offset: 0x168 */ __IO uint32_t L1SUB_CONTROL2_REG; /**< L1 Substates Control 2 Register., offset: 0x16C */ __I uint32_t VSECDMA_EXT_CAP_HDR_OFF; /**< PCIe Extended Capability ID, Capability Version, and Next Capability Offset Register., offset: 0x170 */ __I uint32_t VSECDMA_VENDOR_SPECIFIC_HDR_OFF; /**< Vendor Specific Header Register., offset: 0x174 */ __I uint32_t VSECDMA_DEVICE_INFORMATION_OFF; /**< DMA and related AXI Bridge Implementation Information., offset: 0x178 */ __I uint32_t VSECDMA_NUM_CHAN_OFF; /**< Number of Implemented Channels Register., offset: 0x17C */ __I uint32_t VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF; /**< DMA Register Map Start Address Offset Low Register., offset: 0x180 */ __I uint32_t VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF; /**< DMA Register Map Start Address Offset High Register., offset: 0x184 */ uint8_t RESERVED_4[1400]; __IO uint32_t ACK_LATENCY_TIMER_OFF; /**< Ack Latency Timer and Replay Timer Register., offset: 0x700 */ __IO uint32_t VENDOR_SPEC_DLLP_OFF; /**< Vendor Specific DLLP Register., offset: 0x704 */ __IO uint32_t PORT_FORCE_OFF; /**< Port Force Link Register., offset: 0x708 */ __IO uint32_t ACK_F_ASPM_CTRL_OFF; /**< Ack Frequency and L0-L1 ASPM Control Register., offset: 0x70C */ __IO uint32_t PORT_LINK_CTRL_OFF; /**< Port Link Control Register., offset: 0x710 */ __IO uint32_t LANE_SKEW_OFF; /**< Lane Skew Register., offset: 0x714 */ __IO uint32_t TIMER_CTRL_MAX_FUNC_NUM_OFF; /**< Timer Control and Max Function Number Register., offset: 0x718 */ __IO uint32_t SYMBOL_TIMER_FILTER_1_OFF; /**< Symbol Timer Register and Filter Mask 1 Register., offset: 0x71C */ __IO uint32_t FILTER_MASK_2_OFF; /**< Filter Mask 2 Register., offset: 0x720 */ uint8_t RESERVED_5[4]; __I uint32_t PL_DEBUG0_OFF; /**< Debug Register 0., offset: 0x728 */ __I uint32_t PL_DEBUG1_OFF; /**< Debug Register 1., offset: 0x72C */ __I uint32_t TX_P_FC_CREDIT_STATUS_OFF; /**< Transmit Posted FC Credit Status., offset: 0x730 */ __I uint32_t TX_NP_FC_CREDIT_STATUS_OFF; /**< Transmit Non-Posted FC Credit Status., offset: 0x734 */ __I uint32_t TX_CPL_FC_CREDIT_STATUS_OFF; /**< Transmit Completion FC Credit Status, offset: 0x738 */ __IO uint32_t QUEUE_STATUS_OFF; /**< Queue Status., offset: 0x73C */ __I uint32_t VC_TX_ARBI_1_OFF; /**< VC Transmit Arbitration Register 1., offset: 0x740 */ __I uint32_t VC_TX_ARBI_2_OFF; /**< VC Transmit Arbitration Register 2., offset: 0x744 */ __IO uint32_t VC0_P_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Posted Receive Queue Control., offset: 0x748 */ __IO uint32_t VC0_NP_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Non-Posted Receive Queue Control., offset: 0x74C */ __IO uint32_t VC0_CPL_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Completion Receive Queue Control., offset: 0x750 */ uint8_t RESERVED_6[184]; __IO uint32_t GEN2_CTRL_OFF; /**< Link Width and Speed Change Control Register., offset: 0x80C */ __I uint32_t PHY_STATUS_OFF; /**< PHY Status Register., offset: 0x810 */ __IO uint32_t PHY_CONTROL_OFF; /**< PHY Control Register., offset: 0x814 */ uint8_t RESERVED_7[4]; __IO uint32_t TRGT_MAP_CTRL_OFF; /**< Programmable Target Map Control Register., offset: 0x81C */ __IO uint32_t MSI_CTRL_ADDR_OFF; /**< Integrated MSI Reception Module (iMRM) Address Register., offset: 0x820 */ __IO uint32_t MSI_CTRL_UPPER_ADDR_OFF; /**< Integrated MSI Reception Module Upper Address Register., offset: 0x824 */ __IO uint32_t MSI_CTRL_INT_0_EN_OFF; /**< Integrated MSI Reception Module Interrupt0 Enable Register., offset: 0x828 */ __IO uint32_t MSI_CTRL_INT_0_MASK_OFF; /**< Integrated MSI Reception Module Interrupt0 Mask Register., offset: 0x82C */ __IO uint32_t MSI_CTRL_INT_0_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt0 Status Register., offset: 0x830 */ __IO uint32_t MSI_CTRL_INT_1_EN_OFF; /**< Integrated MSI Reception Module Interrupt1 Enable Register., offset: 0x834 */ __IO uint32_t MSI_CTRL_INT_1_MASK_OFF; /**< Integrated MSI Reception Module Interrupt1 Mask Register., offset: 0x838 */ __IO uint32_t MSI_CTRL_INT_1_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt1 Status Register., offset: 0x83C */ __IO uint32_t MSI_CTRL_INT_2_EN_OFF; /**< Integrated MSI Reception Module Interrupt2 Enable Register., offset: 0x840 */ __IO uint32_t MSI_CTRL_INT_2_MASK_OFF; /**< Integrated MSI Reception Module Interrupt2 Mask Register., offset: 0x844 */ __IO uint32_t MSI_CTRL_INT_2_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt2 Status Register., offset: 0x848 */ __IO uint32_t MSI_CTRL_INT_3_EN_OFF; /**< Integrated MSI Reception Module Interrupt3 Enable Register., offset: 0x84C */ __IO uint32_t MSI_CTRL_INT_3_MASK_OFF; /**< Integrated MSI Reception Module Interrupt3 Mask Register., offset: 0x850 */ __IO uint32_t MSI_CTRL_INT_3_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt3 Status Register., offset: 0x854 */ __IO uint32_t MSI_CTRL_INT_4_EN_OFF; /**< Integrated MSI Reception Module Interrupt4 Enable Register., offset: 0x858 */ __IO uint32_t MSI_CTRL_INT_4_MASK_OFF; /**< Integrated MSI Reception Module Interrupt4 Mask Register., offset: 0x85C */ __IO uint32_t MSI_CTRL_INT_4_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt4 Status Register., offset: 0x860 */ __IO uint32_t MSI_CTRL_INT_5_EN_OFF; /**< Integrated MSI Reception Module Interrupt5 Enable Register., offset: 0x864 */ __IO uint32_t MSI_CTRL_INT_5_MASK_OFF; /**< Integrated MSI Reception Module Interrupt5 Mask Register., offset: 0x868 */ __IO uint32_t MSI_CTRL_INT_5_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt5 Status Register., offset: 0x86C */ __IO uint32_t MSI_CTRL_INT_6_EN_OFF; /**< Integrated MSI Reception Module Interrupt6 Enable Register., offset: 0x870 */ __IO uint32_t MSI_CTRL_INT_6_MASK_OFF; /**< Integrated MSI Reception Module Interrupt6 Mask Register., offset: 0x874 */ __IO uint32_t MSI_CTRL_INT_6_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt6 Status Register., offset: 0x878 */ __IO uint32_t MSI_CTRL_INT_7_EN_OFF; /**< Integrated MSI Reception Module Interrupt7 Enable Register., offset: 0x87C */ __IO uint32_t MSI_CTRL_INT_7_MASK_OFF; /**< Integrated MSI Reception Module Interrupt7 Mask Register., offset: 0x880 */ __IO uint32_t MSI_CTRL_INT_7_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt7 Status Register., offset: 0x884 */ __IO uint32_t MSI_GPIO_IO_OFF; /**< Integrated MSI Reception Module General Purpose IO Register., offset: 0x888 */ __IO uint32_t CLOCK_GATING_CTRL_OFF; /**< Clock Gating Control Register., offset: 0x88C */ __IO uint32_t GEN3_RELATED_OFF; /**< Gen3 Control Register., offset: 0x890 */ uint8_t RESERVED_8[20]; __IO uint32_t GEN3_EQ_CONTROL_OFF; /**< Gen3 EQ Control Register., offset: 0x8A8 */ __IO uint32_t GEN3_EQ_FB_MODE_DIR_CHANGE_OFF; /**< Gen3 EQ Direction Change Feedback Mode Control Register., offset: 0x8AC */ uint8_t RESERVED_9[4]; __IO uint32_t ORDER_RULE_CTRL_OFF; /**< Order Rule Control Register., offset: 0x8B4 */ __IO uint32_t PIPE_LOOPBACK_CONTROL_OFF; /**< PIPE Loopback Control Register., offset: 0x8B8 */ __IO uint32_t MISC_CONTROL_1_OFF; /**< DBI Read-Only Write Enable Register., offset: 0x8BC */ __IO uint32_t MULTI_LANE_CONTROL_OFF; /**< UpConfigure Multi-lane Control Register., offset: 0x8C0 */ __IO uint32_t PHY_INTEROP_CTRL_OFF; /**< PHY Interoperability Control Register., offset: 0x8C4 */ __IO uint32_t TRGT_CPL_LUT_DELETE_ENTRY_OFF; /**< TRGT_CPL_LUT Delete Entry Control register., offset: 0x8C8 */ __IO uint32_t LINK_FLUSH_CONTROL_OFF; /**< Link Reset Request Flush Control Register., offset: 0x8CC */ __IO uint32_t AMBA_ERROR_RESPONSE_DEFAULT_OFF; /**< AXI Bridge Slave Error Response Register., offset: 0x8D0 */ __IO uint32_t AMBA_LINK_TIMEOUT_OFF; /**< Link Down AXI Bridge Slave Timeout Register., offset: 0x8D4 */ __IO uint32_t AMBA_ORDERING_CTRL_OFF; /**< AXI Bridge Ordering Control., offset: 0x8D8 */ uint8_t RESERVED_10[4]; __IO uint32_t COHERENCY_CONTROL_1_OFF; /**< Cache Coherency Control Register 1., offset: 0x8E0 */ __IO uint32_t COHERENCY_CONTROL_2_OFF; /**< Cache Coherency Control Register 2., offset: 0x8E4 */ __IO uint32_t COHERENCY_CONTROL_3_OFF; /**< Cache Coherency Control Register 3., offset: 0x8E8 */ uint8_t RESERVED_11[4]; __IO uint32_t AXI_MSTR_MSG_ADDR_LOW_OFF; /**< Lower 32-bits of the Programmable AXI Address., offset: 0x8F0 */ __IO uint32_t AXI_MSTR_MSG_ADDR_HIGH_OFF; /**< Upper 32-bits of the Programmable AXI Address., offset: 0x8F4 */ __I uint32_t PCIE_VERSION_NUMBER_OFF; /**< PCIe Controller IIP Release Version Number., offset: 0x8F8 */ __I uint32_t PCIE_VERSION_TYPE_OFF; /**< PCIe Controller IIP Release Version Type., offset: 0x8FC */ uint8_t RESERVED_12[528]; __I uint32_t PL_APP_BUS_DEV_NUM_STATUS_OFF; /**< Application driven bus and device number register., offset: 0xB10 */ uint8_t RESERVED_13[8]; __IO uint32_t PCIPM_TRAFFIC_CTRL_OFF; /**< TLP Traffic during Non-D0 State Control Register., offset: 0xB1C */ uint8_t RESERVED_14[16]; __IO uint32_t PL_LTR_LATENCY_OFF; /**< LTR Latency Register., offset: 0xB30 */ uint8_t RESERVED_15[12]; __IO uint32_t AUX_CLK_FREQ_OFF; /**< Auxiliary Clock Frequency Control Register., offset: 0xB40 */ __IO uint32_t L1_SUBSTATES_OFF; /**< L1 Substates Timing Register., offset: 0xB44 */ __IO uint32_t POWERDOWN_CTRL_STATUS_OFF; /**< Powerdown Control and Status Register., offset: 0xB48 */ __IO uint32_t PHY_INTEROP_CTRL_2_OFF; /**< PHY Interoperability Control 2 Register., offset: 0xB4C */ uint8_t RESERVED_16[64]; __IO uint32_t PIPE_RELATED_OFF; /**< PIPE Related Register., offset: 0xB90 */ uint8_t RESERVED_17[232]; __IO uint32_t DBI_FUNCTION_BANK_CTRL_REG_OFF; /**< DBI Function Bank Control Register., offset: 0xC7C */ __IO uint32_t UTILITY_OFF; /**< UTILITY register (Reserved)., offset: 0xC80 */ uint8_t RESERVED_18[4]; __I uint32_t PM_UTILITY_OFF; /**< PM Shadow of UTILITY register (Reserved)., offset: 0xC88 */ } PCIE_RC_Type; /* ---------------------------------------------------------------------------- -- PCIE_RC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_RC_Register_Masks PCIE_RC Register Masks * @{ */ /*! @name TYPE1_DEV_ID_VEND_ID_REG - Device ID, RCRB Next offset pointer and Vendor ID Register. */ /*! @{ */ #define PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MASK (0xFFFFU) #define PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SHIFT (0U) /*! VENDOR_ID - Vendor ID. */ #define PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SHIFT)) & PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MASK) #define PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MASK (0xFFFF0000U) #define PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SHIFT (16U) /*! DEVICE_ID - Device ID. */ #define PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SHIFT)) & PCIE_RC_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MASK) /*! @} */ /*! @name TYPE1_STATUS_COMMAND_REG - Status and Command Register. */ /*! @{ */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_IO_EN_MASK (0x1U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_IO_EN_SHIFT (0U) /*! IO_EN - IO Space Enable. * 0b0..All received I/O accesses are caused to be handled as Unsupported Requests. * 0b1..The Function is enabled to decode the address and further process I/O Space accesses. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_IO_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_IO_EN_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_IO_EN_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MSE_MASK (0x2U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MSE_SHIFT (1U) /*! MSE - Memory Space Enable. * 0b0..All received Memory Space accesses are caused to be handled as Unsupported Requests. * 0b1..The Function is enabled to decode the address and further process Memory Space accesses. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MSE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_MSE_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_MSE_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_BME_MASK (0x4U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_BME_SHIFT (2U) /*! BME - Bus Master Enable. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_BME(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_BME_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_BME_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SCO_MASK (0x8U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SCO_SHIFT (3U) /*! SCO - Special Cycle Enable. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SCO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_SCO_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_SCO_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MWI_EN_MASK (0x10U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MWI_EN_SHIFT (4U) /*! MWI_EN - Memory Write and Invalidate. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MWI_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_MWI_EN_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_MWI_EN_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_VGAPS_MASK (0x20U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_VGAPS_SHIFT (5U) /*! VGAPS - VGA Palette Snoop. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_VGAPS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_VGAPS_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_VGAPS_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_PERREN_MASK (0x40U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_PERREN_SHIFT (6U) /*! PERREN - Parity Error Response. * 0b0..Parity Error Response disable * 0b1..Parity Error Response enable */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_PERREN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_PERREN_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_PERREN_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_IDSEL_MASK (0x80U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_IDSEL_SHIFT (7U) /*! IDSEL - IDSEL Stepping/Wait Cycle Control. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_IDSEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_IDSEL_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_IDSEL_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SERREN_MASK (0x100U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SERREN_SHIFT (8U) /*! SERREN - SERR# Enable. * 0b1..This bit enables reporting upstream of non-fatal and Fatal errors detected by the Function. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SERREN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_SERREN_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_SERREN_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_EN_MASK (0x400U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_EN_SHIFT (10U) /*! INT_EN - Interrupt Disable. * 0b1..When set, Functions are prevented from asserting INTx interrupts. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_EN_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_EN_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RESERV_MASK (0xF800U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RESERV_SHIFT (11U) /*! RESERV - Reserved. * 0b00000..Reserved */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_RESERV_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_RESERV_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MASK (0x80000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SHIFT (19U) /*! INT_STATUS - Interrupt Status. * 0b1..Indicates that an INTx emulation interrupt is pending internally in the Function. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MASK (0x100000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SHIFT (20U) /*! CAP_LIST - Capabilities List. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_CAP_LIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK (0x200000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT (21U) /*! FAST_66MHZ_CAP - 66 MHz Capable. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK (0x800000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT (23U) /*! FAST_B2B_CAP - Fast Back-to-Back Transactions Capable. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MASK (0x1000000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SHIFT (24U) /*! MASTER_DPE - Master Data Parity Error. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_MASTER_DPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK (0x6000000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT (25U) /*! DEV_SEL_TIMING - DEVSEL Timing. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK (0x8000000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT (27U) /*! SIGNALED_TARGET_ABORT - Signaled Target Abort. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK (0x10000000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT (28U) /*! RCVD_TARGET_ABORT - Received Target Abort. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK (0x20000000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT (29U) /*! RCVD_MASTER_ABORT - Received Master Abort. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MASK (0x40000000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SHIFT (30U) /*! SIGNALED_SYS_ERROR - Signaled System Error. * 0b1..This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR# Enable bit in the Command register is 1b. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MASK) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MASK (0x80000000U) #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SHIFT (31U) /*! DETECTED_PARITY_ERROR - Detected Parity Error. * 0b1..This bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity * Error Response bit in the Command register. */ #define PCIE_RC_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SHIFT)) & PCIE_RC_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MASK) /*! @} */ /*! @name TYPE1_CLASS_CODE_REV_ID_REG - Class Code and Revision ID Register. */ /*! @{ */ #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MASK (0xFFU) #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SHIFT (0U) /*! REVISION_ID - Revision ID. */ #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SHIFT)) & PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MASK) #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MASK (0xFF00U) #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SHIFT (8U) /*! PROGRAM_INTERFACE - Programming Interface. */ #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SHIFT)) & PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MASK) #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MASK (0xFF0000U) #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SHIFT (16U) /*! SUBCLASS_CODE - Sub-Class Code. */ #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SHIFT)) & PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MASK) #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MASK (0xFF000000U) #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SHIFT (24U) /*! BASE_CLASS_CODE - Base Class Code. */ #define PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SHIFT)) & PCIE_RC_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MASK) /*! @} */ /*! @name TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG - BIST, Header Type, Latency Timer, and Cache Line Size Register. */ /*! @{ */ #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK (0xFFU) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT (0U) /*! CACHE_LINE_SIZE - Cache Line Size. */ #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT)) & PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK (0xFF00U) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT (8U) /*! LATENCY_MASTER_TIMER - Latency Timer. */ #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT)) & PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK (0x7F0000U) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT (16U) /*! HEADER_TYPE - Header Layout. */ #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT)) & PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK (0x800000U) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT (23U) /*! MULTI_FUNC - Multi-Function Device. * 0b0..Software must not probe for Functions other than Function 0 unless explicitly indicated by another * mechanism, such as an ARI or SR-IOV Capability structure. * 0b1..Indicates that the device may contain multiple Functions, but not necessarily. Software is permitted to * probe for Functions other than Function 0. */ #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT)) & PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MASK (0xFF000000U) #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SHIFT (24U) /*! BIST - BIST. * 0b00000000..DEFAULT value. * 0b11111111..LAST value. */ #define PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SHIFT)) & PCIE_RC_TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MASK) /*! @} */ /*! @name BAR0_REG - BAR0 Register. */ /*! @{ */ #define PCIE_RC_BAR0_REG_BAR0_MEM_IO_MASK (0x1U) #define PCIE_RC_BAR0_REG_BAR0_MEM_IO_SHIFT (0U) /*! BAR0_MEM_IO - - BAR0 Memory Space Indicator. */ #define PCIE_RC_BAR0_REG_BAR0_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR0_REG_BAR0_MEM_IO_SHIFT)) & PCIE_RC_BAR0_REG_BAR0_MEM_IO_MASK) #define PCIE_RC_BAR0_REG_BAR0_TYPE_MASK (0x6U) #define PCIE_RC_BAR0_REG_BAR0_TYPE_SHIFT (1U) /*! BAR0_TYPE - - BAR0 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_RC_BAR0_REG_BAR0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR0_REG_BAR0_TYPE_SHIFT)) & PCIE_RC_BAR0_REG_BAR0_TYPE_MASK) #define PCIE_RC_BAR0_REG_BAR0_PREFETCH_MASK (0x8U) #define PCIE_RC_BAR0_REG_BAR0_PREFETCH_SHIFT (3U) /*! BAR0_PREFETCH - - BAR0 Prefetchable. */ #define PCIE_RC_BAR0_REG_BAR0_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR0_REG_BAR0_PREFETCH_SHIFT)) & PCIE_RC_BAR0_REG_BAR0_PREFETCH_MASK) #define PCIE_RC_BAR0_REG_BAR0_START_MASK (0xFFFFFFF0U) #define PCIE_RC_BAR0_REG_BAR0_START_SHIFT (4U) /*! BAR0_START - - BAR0_START. */ #define PCIE_RC_BAR0_REG_BAR0_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR0_REG_BAR0_START_SHIFT)) & PCIE_RC_BAR0_REG_BAR0_START_MASK) /*! @} */ /*! @name BAR1_REG - BAR1 Register. */ /*! @{ */ #define PCIE_RC_BAR1_REG_BAR1_MEM_IO_MASK (0x1U) #define PCIE_RC_BAR1_REG_BAR1_MEM_IO_SHIFT (0U) /*! BAR1_MEM_IO - - BAR1 Memory Space Indicator. */ #define PCIE_RC_BAR1_REG_BAR1_MEM_IO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR1_REG_BAR1_MEM_IO_SHIFT)) & PCIE_RC_BAR1_REG_BAR1_MEM_IO_MASK) #define PCIE_RC_BAR1_REG_BAR1_TYPE_MASK (0x6U) #define PCIE_RC_BAR1_REG_BAR1_TYPE_SHIFT (1U) /*! BAR1_TYPE - - BAR1 Type. * 0b00..Base register is 32 bits wide and can be mapped anywhere in the 32 address bit Memory Space. * 0b10..Base register is 64 bits wide and can be mapped anywhere in the 64 address bit Memory Space. * 0b01..Reserved. * 0b11..Reserved. */ #define PCIE_RC_BAR1_REG_BAR1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR1_REG_BAR1_TYPE_SHIFT)) & PCIE_RC_BAR1_REG_BAR1_TYPE_MASK) #define PCIE_RC_BAR1_REG_BAR1_PREFETCH_MASK (0x8U) #define PCIE_RC_BAR1_REG_BAR1_PREFETCH_SHIFT (3U) /*! BAR1_PREFETCH - - BAR1 Prefetchable. */ #define PCIE_RC_BAR1_REG_BAR1_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR1_REG_BAR1_PREFETCH_SHIFT)) & PCIE_RC_BAR1_REG_BAR1_PREFETCH_MASK) #define PCIE_RC_BAR1_REG_BAR1_START_MASK (0xFFFFFFF0U) #define PCIE_RC_BAR1_REG_BAR1_START_SHIFT (4U) /*! BAR1_START - - BAR1 Base Address. */ #define PCIE_RC_BAR1_REG_BAR1_START(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BAR1_REG_BAR1_START_SHIFT)) & PCIE_RC_BAR1_REG_BAR1_START_MASK) /*! @} */ /*! @name SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG - Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register. */ /*! @{ */ #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MASK (0xFFU) #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SHIFT (0U) /*! PRIM_BUS - Primary Bus Number. */ #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SHIFT)) & PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MASK) #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MASK (0xFF00U) #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SHIFT (8U) /*! SEC_BUS - Secondary Bus Number. */ #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SHIFT)) & PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MASK) #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MASK (0xFF0000U) #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SHIFT (16U) /*! SUB_BUS - Subordinate Bus Number. */ #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SHIFT)) & PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MASK) #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MASK (0xFF000000U) #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SHIFT (24U) /*! SEC_LAT_TIMER - Secondary Latency Timer. */ #define PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SHIFT)) & PCIE_RC_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MASK) /*! @} */ /*! @name SEC_STAT_IO_LIMIT_IO_BASE_REG - Secondary Status, and I/O Limit and Base Register. */ /*! @{ */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MASK (0x1U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SHIFT (0U) /*! IO_DECODE - I/O Addressing Encode (IO Base Address). * 0b0..The bridge supports only 16-bit I/O addressing (for ISA compatibility). * 0b1..The bridge supports 32-bit I/O addressing. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MASK (0xEU) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SHIFT (1U) /*! IO_RESERV - Reserved. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MASK (0xF0U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SHIFT (4U) /*! IO_BASE - I/O Base Address. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MASK (0x100U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SHIFT (8U) /*! IO_DECODE_BIT8 - I/O Addressing Encode (IO Limit Address). * 0b0..The bridge supports only 16-bit I/O addressing (for ISA compatibility). * 0b1..The bridge supports 32-bit I/O addressing. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MASK (0xE00U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SHIFT (9U) /*! IO_RESERV1 - Reserved. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MASK (0xF000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SHIFT (12U) /*! IO_LIMIT - I/O Limit Address. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MASK (0x7F0000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SHIFT (16U) /*! SEC_STAT_RESERV - Reserved. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MASK (0x1000000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SHIFT (24U) /*! SEC_STAT_MDPE - Master Data Parity Error. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MASK (0x8000000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SHIFT (27U) /*! SEC_STAT_SIG_TRGT_ABRT - Signaled Target Abort. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MASK (0x10000000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SHIFT (28U) /*! SEC_STAT_RCVD_TRGT_ABRT - Received Target Abort. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MASK (0x20000000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SHIFT (29U) /*! SEC_STAT_RCVD_MSTR_ABRT - Received Master Abort. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MASK (0x40000000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SHIFT (30U) /*! SEC_STAT_RCVD_SYS_ERR - Received System Error. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MASK) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MASK (0x80000000U) #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SHIFT (31U) /*! SEC_STAT_DPE - Detected Parity Error. */ #define PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SHIFT)) & PCIE_RC_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MASK) /*! @} */ /*! @name MEM_LIMIT_MEM_BASE_REG - Memory Limit and Base Register. */ /*! @{ */ #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MASK (0xFU) #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SHIFT (0U) /*! MEM_BASE_RESERV - Reserved. */ #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SHIFT)) & PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MASK) #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MASK (0xFFF0U) #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SHIFT (4U) /*! MEM_BASE - Memory Base Address. */ #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SHIFT)) & PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MASK) #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MASK (0xF0000U) #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SHIFT (16U) /*! MEM_LIMIT_RESERV - Reserved. */ #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SHIFT)) & PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MASK) #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MASK (0xFFF00000U) #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SHIFT (20U) /*! MEM_LIMIT - Memory Limit Address. */ #define PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SHIFT)) & PCIE_RC_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MASK) /*! @} */ /*! @name PREF_MEM_LIMIT_PREF_MEM_BASE_REG - Prefetchable Memory Limit and Base Register. */ /*! @{ */ #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MASK (0x1U) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SHIFT (0U) /*! PREF_MEM_DECODE - Prefetchable Memory Base Decode. * 0b0..Indicates that the bridge supports only 32 bit addresses. * 0b1..Indicates that the bridge supports 64 bit addresses. Prefetchable Base Upper 32 Bits registers holds the * rest of the 64-bit prefetchable base address. */ #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SHIFT)) & PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MASK) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MASK (0xEU) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SHIFT (1U) /*! PREF_RESERV - Reserved. */ #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SHIFT)) & PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MASK) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MASK (0xFFF0U) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SHIFT (4U) /*! PREF_MEM_BASE - Prefetchable Memory Base Address. */ #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SHIFT)) & PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MASK) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MASK (0x10000U) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SHIFT (16U) /*! PREF_MEM_LIMIT_DECODE - Prefetchable Memory Limit Decode. * 0b0..Indicates that the bridge supports only 32 bit addresses. * 0b1..Indicates that the bridge supports 64 bit addresses. Prefetchable Limit Upper 32 Bits registers holds the * rest of the 64-bit prefetchable limit address. */ #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SHIFT)) & PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MASK) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MASK (0xE0000U) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SHIFT (17U) /*! PREF_RESERV1 - Reserved. */ #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SHIFT)) & PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MASK) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MASK (0xFFF00000U) #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SHIFT (20U) /*! PREF_MEM_LIMIT - Prefetchable Memory Limit Address. */ #define PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SHIFT)) & PCIE_RC_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MASK) /*! @} */ /*! @name PREF_BASE_UPPER_REG - Prefetchable Base Upper 32 Bits Register. */ /*! @{ */ #define PCIE_RC_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MASK (0xFFFFFFFFU) #define PCIE_RC_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SHIFT (0U) /*! PREF_MEM_BASE_UPPER - Prefetchable Base Upper 32 Bit. */ #define PCIE_RC_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SHIFT)) & PCIE_RC_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MASK) /*! @} */ /*! @name PREF_LIMIT_UPPER_REG - Prefetchable Limit Upper 32 Bits Register. */ /*! @{ */ #define PCIE_RC_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MASK (0xFFFFFFFFU) #define PCIE_RC_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SHIFT (0U) /*! PREF_MEM_LIMIT_UPPER - Prefetchable Limit Upper 32 Bit. */ #define PCIE_RC_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SHIFT)) & PCIE_RC_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MASK) /*! @} */ /*! @name IO_LIMIT_UPPER_IO_BASE_UPPER_REG - I/O Limit and Base Upper 16 Bits Register. */ /*! @{ */ #define PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MASK (0xFFFFU) #define PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SHIFT (0U) /*! IO_BASE_UPPER - I/O Base Upper 16 Bits. */ #define PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SHIFT)) & PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MASK) #define PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MASK (0xFFFF0000U) #define PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SHIFT (16U) /*! IO_LIMIT_UPPER - I/O Limit Upper 16 Bits. */ #define PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SHIFT)) & PCIE_RC_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MASK) /*! @} */ /*! @name TYPE1_CAP_PTR_REG - Capabilities Pointer Register. */ /*! @{ */ #define PCIE_RC_TYPE1_CAP_PTR_REG_CAP_POINTER_MASK (0xFFU) #define PCIE_RC_TYPE1_CAP_PTR_REG_CAP_POINTER_SHIFT (0U) /*! CAP_POINTER - Capabilities Pointer. */ #define PCIE_RC_TYPE1_CAP_PTR_REG_CAP_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_CAP_PTR_REG_CAP_POINTER_SHIFT)) & PCIE_RC_TYPE1_CAP_PTR_REG_CAP_POINTER_MASK) /*! @} */ /*! @name TYPE1_EXP_ROM_BASE_REG - Expansion ROM BAR Register. */ /*! @{ */ #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MASK (0x1U) #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SHIFT (0U) /*! ROM_BAR_ENABLE - Expansion ROM Enable. * 0b1..Address decoding is enabled using the parameters in the other part of the Expansion ROM Base Address register. * 0b0..Function's expansion ROM address space is disabled. */ #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SHIFT)) & PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MASK) #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_STATUS_MASK (0xEU) #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_STATUS_SHIFT (1U) /*! ROM_BAR_VALIDATION_STATUS - Expansion ROM Validation Status. * 0b101..Validation Fail Valid but untrusted contents (For example, Out of Date, Expired or Revoked Certificate). * 0b100..Validation Fail Invalid contents. * 0b001..Validation in Progress. * 0b111..Warning Pass Validation Passed with implementation-specific warning. Valid and trusted contents. * 0b110..Warning Pass Validation Passed with implementation-specific warning. Valid contents, trust test was not performed. * 0b011..Validation Pass Valid and trusted contents. * 0b010..Validation Pass Valid contents, trust test was not performed. * 0b000..Validation not supported. */ #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_STATUS_SHIFT)) & PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_STATUS_MASK) #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_DETAILS_MASK (0xF0U) #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_DETAILS_SHIFT (4U) /*! ROM_BAR_VALIDATION_DETAILS - Expansion ROM Validation Details. */ #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_DETAILS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_DETAILS_SHIFT)) & PCIE_RC_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_VALIDATION_DETAILS_MASK) #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MASK (0xFFFFF800U) #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SHIFT (11U) /*! EXP_ROM_BASE_ADDRESS - Expansion ROM Base Address. */ #define PCIE_RC_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SHIFT)) & PCIE_RC_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MASK) /*! @} */ /*! @name BRIDGE_CTRL_INT_PIN_INT_LINE_REG - Bridge Control, Interrupt Pin, and Interrupt Line Register. */ /*! @{ */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MASK (0xFFU) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SHIFT (0U) /*! INT_LINE - Interrupt Line. */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MASK (0xFF00U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SHIFT (8U) /*! INT_PIN - Interrupt PIN. * 0b00000001..Map to legacy interrupt Messages for INTA * 0b00000010..Map to legacy interrupt Messages for INTB * 0b00000011..Map to legacy interrupt Messages for INTC * 0b00000100..Map to legacy interrupt Messages for INTD * 0b00000000..Indicates that the Function uses no legacy interrupt Message(s). */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MASK (0x10000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SHIFT (16U) /*! PERE - Parity Error Response Enable. */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MASK (0x20000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SHIFT (17U) /*! SERR_EN - SERR# Enable. */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MASK (0x40000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SHIFT (18U) /*! ISA_EN - ISA Enable. * 0b0..Forward downstream all I/O addresses in the address range defined by the I/O Base and I/O Limit registers * 0b1..Forward upstream ISA I/O addresses in the address range defined by the I/O Base and I/O Limit registers * that are in the first 64 KB of PCI I/O address space (top 768 bytes of each 1-KB block. */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MASK (0x80000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SHIFT (19U) /*! VGA_EN - VGA Enable. * 0b1..Forward VGA compatible memory and I/O addresses (addresses defined above) from the primary interface to * the secondary interface (if the I/O Space Enable and Memory Space Enable bits are set) independent of the * I/O and memory address ranges and independent of the ISA Enable bit * 0b0..Do not forward VGA compatible memory and I/O addresses from the primary to the secondary interface * (addresses defined above) unless they are enabled for forwarding by the defined I/O and memory address ranges */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MASK (0x100000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SHIFT (20U) /*! VGA_16B_DEC - VGA 16 bit decode. * 0b0..Execute 10-bit address decodes on VGA I/O accesses * 0b1..Execute 16-bit address decodes on VGA I/O accesses */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MASK (0x200000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SHIFT (21U) /*! MSTR_ABORT_MODE - Master Abort Mode. */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MASK (0x400000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SHIFT (22U) /*! SBR - Secondary Bus Reset. */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MASK) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MASK (0xFF800000U) #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SHIFT (23U) /*! BRIDGE_CTRL_RESERV - Reserved. */ #define PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SHIFT)) & PCIE_RC_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MASK) /*! @} */ /*! @name CAP_ID_NXT_PTR_REG - Power Management Capabilities Register. */ /*! @{ */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK (0xFFU) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT (0U) /*! PM_CAP_ID - Capability ID. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK (0xFF00U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT (8U) /*! PM_NEXT_POINTER - Next Capability Pointer. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK (0x70000U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT (16U) /*! PM_SPEC_VER - Version. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_PM_SPEC_VER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PME_CLK_MASK (0x80000U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT (19U) /*! PME_CLK - PME Clock. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_PME_CLK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_PME_CLK_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_DSI_MASK (0x200000U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_DSI_SHIFT (21U) /*! DSI - Device Specific Initialization. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_DSI(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_DSI_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_DSI_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK (0x1C00000U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT (22U) /*! AUX_CURR - Aux_Current. * 0b000..0 self powered * 0b001..55mA Vaux Max. Current Required * 0b010..100mA Vaux Max. Current Required * 0b011..160mA Vaux Max. Current Required * 0b100..220mA Vaux Max. Current Required * 0b101..270mA Vaux Max. Current Required * 0b110..320mA Vaux Max. Current Required * 0b111..375mA Vaux Max. Current Required */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_AUX_CURR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK (0x2000000U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT (25U) /*! D1_SUPPORT - D1_Support. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_D1_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK (0x4000000U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT (26U) /*! D2_SUPPORT - D2_Support. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_D2_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK (0xF8000000U) #define PCIE_RC_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT (27U) /*! PME_SUPPORT - PME_Support. */ #define PCIE_RC_CAP_ID_NXT_PTR_REG_PME_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT)) & PCIE_RC_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK) /*! @} */ /*! @name CON_STATUS_REG - Power Management Control and Status Register. */ /*! @{ */ #define PCIE_RC_CON_STATUS_REG_POWER_STATE_MASK (0x3U) #define PCIE_RC_CON_STATUS_REG_POWER_STATE_SHIFT (0U) /*! POWER_STATE - PowerState. * 0b00..D0 power state * 0b01..D1 power state * 0b10..D2 power state * 0b11..D3hot D3hot power state */ #define PCIE_RC_CON_STATUS_REG_POWER_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_POWER_STATE_SHIFT)) & PCIE_RC_CON_STATUS_REG_POWER_STATE_MASK) #define PCIE_RC_CON_STATUS_REG_NO_SOFT_RST_MASK (0x8U) #define PCIE_RC_CON_STATUS_REG_NO_SOFT_RST_SHIFT (3U) /*! NO_SOFT_RST - No_Soft_Reset. */ #define PCIE_RC_CON_STATUS_REG_NO_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_NO_SOFT_RST_SHIFT)) & PCIE_RC_CON_STATUS_REG_NO_SOFT_RST_MASK) #define PCIE_RC_CON_STATUS_REG_PME_ENABLE_MASK (0x100U) #define PCIE_RC_CON_STATUS_REG_PME_ENABLE_SHIFT (8U) /*! PME_ENABLE - PME_En. */ #define PCIE_RC_CON_STATUS_REG_PME_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_PME_ENABLE_SHIFT)) & PCIE_RC_CON_STATUS_REG_PME_ENABLE_MASK) #define PCIE_RC_CON_STATUS_REG_DATA_SELECT_MASK (0x1E00U) #define PCIE_RC_CON_STATUS_REG_DATA_SELECT_SHIFT (9U) /*! DATA_SELECT - Data_Select. */ #define PCIE_RC_CON_STATUS_REG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_DATA_SELECT_SHIFT)) & PCIE_RC_CON_STATUS_REG_DATA_SELECT_MASK) #define PCIE_RC_CON_STATUS_REG_DATA_SCALE_MASK (0x6000U) #define PCIE_RC_CON_STATUS_REG_DATA_SCALE_SHIFT (13U) /*! DATA_SCALE - Data_Scale. */ #define PCIE_RC_CON_STATUS_REG_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_DATA_SCALE_SHIFT)) & PCIE_RC_CON_STATUS_REG_DATA_SCALE_MASK) #define PCIE_RC_CON_STATUS_REG_PME_STATUS_MASK (0x8000U) #define PCIE_RC_CON_STATUS_REG_PME_STATUS_SHIFT (15U) /*! PME_STATUS - PME_Status. */ #define PCIE_RC_CON_STATUS_REG_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_PME_STATUS_SHIFT)) & PCIE_RC_CON_STATUS_REG_PME_STATUS_MASK) #define PCIE_RC_CON_STATUS_REG_B2_B3_SUPPORT_MASK (0x400000U) #define PCIE_RC_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT (22U) /*! B2_B3_SUPPORT - B2B3 Support for D3hot. */ #define PCIE_RC_CON_STATUS_REG_B2_B3_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT)) & PCIE_RC_CON_STATUS_REG_B2_B3_SUPPORT_MASK) #define PCIE_RC_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK (0x800000U) #define PCIE_RC_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT (23U) /*! BUS_PWR_CLK_CON_EN - Bus Power/Clock Control Enable. */ #define PCIE_RC_CON_STATUS_REG_BUS_PWR_CLK_CON_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT)) & PCIE_RC_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK) #define PCIE_RC_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK (0xFF000000U) #define PCIE_RC_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT (24U) /*! DATA_REG_ADD_INFO - Data. */ #define PCIE_RC_CON_STATUS_REG_DATA_REG_ADD_INFO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT)) & PCIE_RC_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK) /*! @} */ /*! @name PCI_MSI_CAP_ID_NEXT_CTRL_REG - MSI Capability Header and Message Control Register. */ /*! @{ */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK (0xFFU) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT (0U) /*! PCI_MSI_CAP_ID - Capability ID. */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK (0xFF00U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT (8U) /*! PCI_MSI_CAP_NEXT_OFFSET - Next Capability Pointer. */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK (0x10000U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT (16U) /*! PCI_MSI_ENABLE - MSI Enable. */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK (0xE0000U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT (17U) /*! PCI_MSI_MULTIPLE_MSG_CAP - Multiple Message Capable. * 0b100..16 vectors requested * 0b000..1 vector requested * 0b001..2 vectors requested * 0b101..32 vectors requested * 0b010..4 vectors requested * 0b011..8 vectors requested */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK (0x700000U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT (20U) /*! PCI_MSI_MULTIPLE_MSG_EN - Multiple Message Enable. * 0b100..16 vectors allocated * 0b000..1 vector allocated * 0b001..2 vectors allocated * 0b101..32 vectors allocated * 0b010..4 vectors allocated * 0b011..8 vectors allocated */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK (0x800000U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT (23U) /*! PCI_MSI_64_BIT_ADDR_CAP - 64 bit address capable. * 0b0..If set, the function is capable of sending a 64-bit message address. * 0b1..If clear, the function is not capable of sending a 64-bit message address. */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK (0x1000000U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT (24U) /*! PCI_PVM_SUPPORT - Per-Vector Masking Capable. */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK (0x2000000U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT (25U) /*! PCI_MSI_EXT_DATA_CAP - Extended Message Data Capable. */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK (0x4000000U) #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT (26U) /*! PCI_MSI_EXT_DATA_EN - Extended Message Data Enable. */ #define PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT)) & PCIE_RC_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK) /*! @} */ /*! @name MSI_CAP_OFF_04H_REG - Message Address Register for MSI (Offset 04h). */ /*! @{ */ #define PCIE_RC_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK (0xFFFFFFFCU) #define PCIE_RC_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT (2U) /*! PCI_MSI_CAP_OFF_04H - Message Address - System-specified message address. */ #define PCIE_RC_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT)) & PCIE_RC_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK) /*! @} */ /*! @name MSI_CAP_OFF_08H_REG - Message Address Register for MSI (Offset 08h). */ /*! @{ */ #define PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK (0xFFFFU) #define PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT (0U) /*! PCI_MSI_CAP_OFF_08H - For a function that supports a 32-bit message address, this field contains Message Data (System-specified message data). */ #define PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT)) & PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK) #define PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK (0xFFFF0000U) #define PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT (16U) /*! PCI_MSI_CAP_OFF_0AH - For a function that supports a 32-bit message address, this field contains * Extended Message Data (System-specified message data). */ #define PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT)) & PCIE_RC_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK) /*! @} */ /*! @name MSI_CAP_OFF_0CH_REG - Message Address Register for MSI (Offset 0Ch). */ /*! @{ */ #define PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK (0xFFFFU) #define PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT (0U) /*! PCI_MSI_CAP_OFF_0CH - PCI_MSI_CAP_OFF_0CH */ #define PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT)) & PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK) #define PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK (0xFFFF0000U) #define PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT (16U) /*! PCI_MSI_CAP_OFF_0EH - PCI_MSI_CAP_OFF_0EH */ #define PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT)) & PCIE_RC_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK) /*! @} */ /*! @name MSI_CAP_OFF_10H_REG - Message Address Register for MSI (Offset 10h). */ /*! @{ */ #define PCIE_RC_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT (0U) /*! PCI_MSI_CAP_OFF_10H - Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG. */ #define PCIE_RC_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT)) & PCIE_RC_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK) /*! @} */ /*! @name MSI_CAP_OFF_14H_REG - Message Address Register for MSI (Offset 14h). */ /*! @{ */ #define PCIE_RC_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT (0U) /*! PCI_MSI_CAP_OFF_14H - Pending Bits. */ #define PCIE_RC_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT)) & PCIE_RC_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK) /*! @} */ /*! @name PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG - PCI Express Capabilities, ID, Next Pointer Register. */ /*! @{ */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK (0xFFU) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT (0U) /*! PCIE_CAP_ID - Capability ID. */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT)) & PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK (0xFF00U) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT (8U) /*! PCIE_CAP_NEXT_PTR - Next Capability Pointer. */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT)) & PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK (0xF0000U) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT (16U) /*! PCIE_CAP_REG - Capability Version. */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT)) & PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK (0xF00000U) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT (20U) /*! PCIE_DEV_PORT_TYPE - Device/Port Type. * 0b0110..Downstream Port of PCI Express Switch * 0b0000..PCI Express Endpoint * 0b0001..Legacy PCI Express Endpoint * 0b0100..Root Port of PCI Express Root Complex * 0b0101..Upstream Port of PCI Express Switch */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT)) & PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK (0x1000000U) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT (24U) /*! PCIE_SLOT_IMP - Slot Implemented. */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT)) & PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK (0x3E000000U) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT (25U) /*! PCIE_INT_MSG_NUM - PCIE Interrupt Message Number. */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT)) & PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK (0x40000000U) #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT (30U) /*! RSVD - Reserved. */ #define PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT)) & PCIE_RC_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK) /*! @} */ /*! @name DEVICE_CAPABILITIES_REG - Device Capabilities Register. */ /*! @{ */ #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK (0x7U) #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT (0U) /*! PCIE_CAP_MAX_PAYLOAD_SIZE - Max_Payload_Size Supported. * 0b011..1024 bytes max payload size * 0b000..128 bytes max payload size * 0b100..2048 bytes max payload size * 0b001..256 bytes max payload size * 0b101..4096 bytes max payload size * 0b010..512 bytes max payload size */ #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK) #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK (0x18U) #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT (3U) /*! PCIE_CAP_PHANTOM_FUNC_SUPPORT - Phantom Functions Supported. * 0b01..The most significant bit of the Function number in Requester ID is used for Phantom Functions; a * Multi-Function Device is permitted to implement Functions 0-3. Functions 0, 1, 2, and 3 are permitted to use * Function Numbers 4, 5, 6, and 7 respectively as Phantom Functions. * 0b10..The two most significant bits of Function Number in Requester ID are used for Phantom Functions; a * Multi-Function Device is permitted to implement Functions 0-1. Function 0 is permitted to use Function Numbers * 2, 4, and 6 for Phantom Functions. Function 1 is permitted to use Function Numbers 3, 5, and 7 as * Phantom Functions. * 0b00..No Function Number bits are used for Phantom Functions. Multi-Function Devices are permitted to implement up to 8 independent functions. * 0b11..All 3 bits of Function Number in Requester ID used for Phantom Functions. The device must have a single * Function 0 that is permitted to use all other Function Numbers as Phantom Functions. */ #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK) #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK (0x20U) #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT (5U) /*! PCIE_CAP_EXT_TAG_SUPP - Extended Tag Field Supported. * 0b0..5-bit Tag field supported * 0b1..8-bit Tag field supported */ #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK) #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK (0x8000U) #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT (15U) /*! PCIE_CAP_ROLE_BASED_ERR_REPORT - Role-Based Error Reporting. */ #define PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK) /*! @} */ /*! @name DEVICE_CONTROL_DEVICE_STATUS - Device Control and Device Status Register. */ /*! @{ */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK (0x1U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT (0U) /*! PCIE_CAP_CORR_ERR_REPORT_EN - Correctable Error Reporting Enable. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK (0x2U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT (1U) /*! PCIE_CAP_NON_FATAL_ERR_REPORT_EN - Non-Fatal Error Reporting Enable. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK (0x4U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT (2U) /*! PCIE_CAP_FATAL_ERR_REPORT_EN - Fatal Error Reporting Enable. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK (0x8U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT (3U) /*! PCIE_CAP_UNSUPPORT_REQ_REP_EN - Unsupported Request Reporting Enable. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK (0x10U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT (4U) /*! PCIE_CAP_EN_REL_ORDER - Enable Relaxed Ordering. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK (0xE0U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT (5U) /*! PCIE_CAP_MAX_PAYLOAD_SIZE_CS - Max_Payload_Size. * 0b011..1024 bytes maximum Read Request size * 0b000..128 bytes maximum Read Request size * 0b100..2048 bytes maximum Read Request size * 0b001..256 bytes maximum Read Request size * 0b101..4096 bytes maximum Read Request size * 0b010..512 bytes maximum Read Request size * 0b110..RESERVED * 0b111..RESERVED */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK (0x100U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT (8U) /*! PCIE_CAP_EXT_TAG_EN - Extended Tag Field Enable. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MASK (0x200U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT (9U) /*! PCIE_CAP_PHANTOM_FUNC_EN - Phantom Functions Enable. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK (0x400U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT (10U) /*! PCIE_CAP_AUX_POWER_PM_EN - Aux Power PM Enable. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK (0x800U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT (11U) /*! PCIE_CAP_EN_NO_SNOOP - Enable No Snoop. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK (0x7000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT (12U) /*! PCIE_CAP_MAX_READ_REQ_SIZE - Max_Read_Request_Size. * 0b011..1024 bytes maximum Read Request size * 0b000..128 bytes maximum Read Request size * 0b100..2048 bytes maximum Read Request size * 0b001..256 bytes maximum Read Request size * 0b101..4096 bytes maximum Read Request size * 0b010..512 bytes maximum Read Request size * 0b110..RESERVED * 0b111..RESERVED */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK (0x8000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT (15U) /*! PCIE_CAP_INITIATE_FLR - Initiate Function Level Reset. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK (0x10000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT (16U) /*! PCIE_CAP_CORR_ERR_DETECTED - Correctable Error Detected. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK (0x20000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT (17U) /*! PCIE_CAP_NON_FATAL_ERR_DETECTED - Non-Fatal Error Detected. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK (0x40000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT (18U) /*! PCIE_CAP_FATAL_ERR_DETECTED - Fatal Error Detected. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK (0x80000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT (19U) /*! PCIE_CAP_UNSUPPORTED_REQ_DETECTED - Unsupported Request Detected. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK (0x100000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT (20U) /*! PCIE_CAP_AUX_POWER_DETECTED - AUX Power Detected. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK (0x200000U) #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT (21U) /*! PCIE_CAP_TRANS_PENDING - Transactions Pending. */ #define PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT)) & PCIE_RC_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK) /*! @} */ /*! @name LINK_CAPABILITIES_REG - Link Capabilities Register. */ /*! @{ */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK (0xFU) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT (0U) /*! PCIE_CAP_MAX_LINK_SPEED - Max Link Speed. * 0b0001..Supported Link Speeds Vector field bit 0 * 0b0010..Supported Link Speeds Vector field bit 1 * 0b0011..Supported Link Speeds Vector field bit 2 * 0b0100..Supported Link Speeds Vector field bit 3 * 0b0101..Supported Link Speeds Vector field bit 4 * 0b0110..Supported Link Speeds Vector field bit 5 * 0b0111..Supported Link Speeds Vector field bit 6 */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK (0x3F0U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT (4U) /*! PCIE_CAP_MAX_LINK_WIDTH - Maximum Link Width. * 0b000001..x1 * 0b001100..x12 * 0b010000..x16 * 0b000010..x2 * 0b100000..x32 * 0b000100..x4 * 0b001000..x8 */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK (0xC00U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT (10U) /*! PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT - Active State Power Management (ASPM) Support. * 0b11..L0s and L1 Supported * 0b01..L0s Supported * 0b10..L1 Supported * 0b00..No ASPM Support */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK (0x7000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT (12U) /*! PCIE_CAP_L0S_EXIT_LATENCY - L0s Exit Latency. * 0b111..More than 4 us * 0b000..Less than 64 ns * 0b010..128 ns to less than 256 ns * 0b101..1 us to less than 2 us * 0b011..256 ns to less than 512 ns * 0b110..2 us to 4 us * 0b100..512 ns to less than 1 us * 0b001..64 ns to less than 128 ns */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK (0x38000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT (15U) /*! PCIE_CAP_L1_EXIT_LATENCY - L1 Exit Latency. * 0b111..More than 64 us * 0b000..Less than 1us * 0b101..16 us to less than 32 us * 0b001..1 us to less than 2 us * 0b010..2 us to less than 4 us * 0b110..32 us to 64 us * 0b011..4 us to less than 8 us * 0b100..8 us to less than 16 us */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK (0x40000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT (18U) /*! PCIE_CAP_CLOCK_POWER_MAN - Clock Power Management. */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK (0x80000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT (19U) /*! PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP - Surprise Down Error Reporting Capable. */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK (0x100000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT (20U) /*! PCIE_CAP_DLL_ACTIVE_REP_CAP - Data Link Layer Link Active Reporting Capable. */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK (0x200000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT (21U) /*! PCIE_CAP_LINK_BW_NOT_CAP - Link Bandwidth Notification Capability. */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK (0x400000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT (22U) /*! PCIE_CAP_ASPM_OPT_COMPLIANCE - ASPM Optionality Compliance. */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK (0xFF000000U) #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT (24U) /*! PCIE_CAP_PORT_NUM - Port Number. */ #define PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT)) & PCIE_RC_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK) /*! @} */ /*! @name LINK_CONTROL_LINK_STATUS_REG - Link Control and Link Status Register. */ /*! @{ */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK (0x3U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT (0U) /*! PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL - Active State Power Management (ASPM) Control. * 0b00..Disabled * 0b01..L0s Entry Enabled * 0b11..L0s and L1 Entry Enabled * 0b10..L1 Entry Enabled */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK (0x8U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT (3U) /*! PCIE_CAP_RCB - Read Completion Boundary (RCB). * 0b1..128 byte * 0b0..64 byte */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK (0x10U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT (4U) /*! PCIE_CAP_LINK_DISABLE - Link Disable. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK (0x20U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT (5U) /*! PCIE_CAP_RETRAIN_LINK - Retrain Link. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK (0x40U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT (6U) /*! PCIE_CAP_COMMON_CLK_CONFIG - Common Clock Configuration. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK (0x80U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT (7U) /*! PCIE_CAP_EXTENDED_SYNCH - Extended Synch. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK (0x100U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT (8U) /*! PCIE_CAP_EN_CLK_POWER_MAN - Enable Clock Power Management. * 0b1..When this bit is set, the device is permitted to use CLKREQ# signal to power manage Link clock according * to protocol defined in appropriate form factor specification. * 0b0..Clock power management is disabled and device must hold CLKREQ# signal low. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK (0x200U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT (9U) /*! PCIE_CAP_HW_AUTO_WIDTH_DISABLE - Hardware Autonomous Width Disable. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK (0x400U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT (10U) /*! PCIE_CAP_LINK_BW_MAN_INT_EN - Link Bandwidth Management Interrupt Enable. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK (0x800U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT (11U) /*! PCIE_CAP_LINK_AUTO_BW_INT_EN - Link Autonomous Bandwidth Management Interrupt Enable. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK (0xC000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT (14U) /*! PCIE_CAP_DRS_SIGNALING_CONTROL - DRS Signaling Control. * 0b01..DRS Interrupt Enabled * 0b00..DRS not Reported * 0b10..DRS to FRS Signaling Enabled */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK (0xF0000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT (16U) /*! PCIE_CAP_LINK_SPEED - Current Link Speed. * 0b0001..Supported Link Speeds Vector field bit 0 * 0b0010..Supported Link Speeds Vector field bit 1 * 0b0011..Supported Link Speeds Vector field bit 2 * 0b0100..Supported Link Speeds Vector field bit 3 * 0b0101..Supported Link Speeds Vector field bit 4 * 0b0110..Supported Link Speeds Vector field bit 5 * 0b0111..Supported Link Speeds Vector field bit 6 */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK (0x3F00000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT (20U) /*! PCIE_CAP_NEGO_LINK_WIDTH - Negotiated Link Width. * 0b000001..x1 * 0b001100..x12 * 0b010000..x16 * 0b000010..x2 * 0b100000..x32 * 0b000100..x4 * 0b001000..x8 */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK (0x8000000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT (27U) /*! PCIE_CAP_LINK_TRAINING - Link Training. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK (0x10000000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT (28U) /*! PCIE_CAP_SLOT_CLK_CONFIG - Slot Clock Configuration. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK (0x20000000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT (29U) /*! PCIE_CAP_DLL_ACTIVE - Data Link Layer Link Active. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK (0x40000000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT (30U) /*! PCIE_CAP_LINK_BW_MAN_STATUS - Link Bandwidth Management Status. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK (0x80000000U) #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT (31U) /*! PCIE_CAP_LINK_AUTO_BW_STATUS - Link Autonomous Bandwidth Status. */ #define PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT)) & PCIE_RC_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK) /*! @} */ /*! @name SLOT_CAPABILITIES_REG - Slot Capabilities Register. */ /*! @{ */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MASK (0x1U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SHIFT (0U) /*! PCIE_CAP_ATTENTION_INDICATOR_BUTTON - Attention Button Present. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MASK (0x2U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SHIFT (1U) /*! PCIE_CAP_POWER_CONTROLLER - Power Controller Present. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MASK (0x4U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SHIFT (2U) /*! PCIE_CAP_MRL_SENSOR - MRL Sensor Present. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MASK (0x8U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SHIFT (3U) /*! PCIE_CAP_ATTENTION_INDICATOR - Attention Indicator Present. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MASK (0x10U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SHIFT (4U) /*! PCIE_CAP_POWER_INDICATOR - Power Indicator Present. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MASK (0x20U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SHIFT (5U) /*! PCIE_CAP_HOT_PLUG_SURPRISE - Hot-Plug Surprise. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MASK (0x40U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SHIFT (6U) /*! PCIE_CAP_HOT_PLUG_CAPABLE - Hot-Plug Capable. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MASK (0x7F80U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SHIFT (7U) /*! PCIE_CAP_SLOT_POWER_LIMIT_VALUE - Slot Power Limit Value. * 0b11110000..250 W Slot Power Limit * 0b11110001..275 W Slot Power Limit * 0b11110010..300 W Slot Power Limit */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MASK (0x18000U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SHIFT (15U) /*! PCIE_CAP_SLOT_POWER_LIMIT_SCALE - Slot Power Limit Scale. * 0b11..0.001x * 0b10..0.01x * 0b01..0.1x * 0b00..1.0x */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MASK (0x20000U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SHIFT (17U) /*! PCIE_CAP_ELECTROMECH_INTERLOCK - Electromechanical Interlock Present. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MASK (0x40000U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SHIFT (18U) /*! PCIE_CAP_NO_CMD_CPL_SUPPORT - No Command Completed Support. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MASK) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MASK (0xFFF80000U) #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SHIFT (19U) /*! PCIE_CAP_PHY_SLOT_NUM - Physical Slot Number. */ #define PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SHIFT)) & PCIE_RC_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MASK) /*! @} */ /*! @name SLOT_CONTROL_SLOT_STATUS - Slot Control and Status Register. */ /*! @{ */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MASK (0x1U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SHIFT (0U) /*! PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN - Attention Button Pressed Enable. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MASK (0x2U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SHIFT (1U) /*! PCIE_CAP_POWER_FAULT_DETECTED_EN - Power Fault Detected Enable. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MASK (0x4U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SHIFT (2U) /*! PCIE_CAP_MRL_SENSOR_CHANGED_EN - MRL Sensor Changed Enable. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MASK (0x8U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SHIFT (3U) /*! PCIE_CAP_PRESENCE_DETECT_CHANGE_EN - Presence Detect Changed Enable. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MASK (0x10U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SHIFT (4U) /*! PCIE_CAP_CMD_CPL_INT_EN - Command Completed Interrupt Enable. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MASK (0x20U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SHIFT (5U) /*! PCIE_CAP_HOT_PLUG_INT_EN - Hot-Plug Interrupt Enable. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MASK (0xC0U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SHIFT (6U) /*! PCIE_CAP_ATTENTION_INDICATOR_CTRL - Attention Indicator Control. * 0b10..Blink * 0b11..Off * 0b01..On * 0b00..Reserved */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MASK (0x300U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SHIFT (8U) /*! PCIE_CAP_POWER_INDICATOR_CTRL - Power Indicator Control. * 0b10..Blink * 0b11..Off * 0b01..On * 0b00..Reserved */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MASK (0x400U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SHIFT (10U) /*! PCIE_CAP_POWER_CONTROLLER_CTRL - Power Controller Control. * 0b1..Power Off * 0b0..Power On */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MASK (0x800U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SHIFT (11U) /*! PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL - Electromechanical Interlock Control. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MASK (0x1000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SHIFT (12U) /*! PCIE_CAP_DLL_STATE_CHANGED_EN - Data Link Layer State Changed Enable. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MASK (0x10000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SHIFT (16U) /*! PCIE_CAP_ATTENTION_BUTTON_PRESSED - Attention Button Pressed. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MASK (0x20000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SHIFT (17U) /*! PCIE_CAP_POWER_FAULT_DETECTED - Power Fault Detected. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MASK (0x40000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SHIFT (18U) /*! PCIE_CAP_MRL_SENSOR_CHANGED - MRL Sensor Changed. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MASK (0x80000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SHIFT (19U) /*! PCIE_CAP_PRESENCE_DETECTED_CHANGED - Presence Detect Changed. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MASK (0x100000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SHIFT (20U) /*! PCIE_CAP_CMD_CPLD - Command Completed. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MASK (0x200000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SHIFT (21U) /*! PCIE_CAP_MRL_SENSOR_STATE - MRL Sensor State. * 0b0..MRL Closed * 0b1..MRL Open */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MASK (0x400000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SHIFT (22U) /*! PCIE_CAP_PRESENCE_DETECT_STATE - Presence Detect State. * 0b1..Adapter Present in slot * 0b0..Slot Empty */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MASK (0x800000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SHIFT (23U) /*! PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS - Electromechanical Interlock Status. * 0b0..Electromechanical Interlock Disengaged * 0b1..Electromechanical Interlock Engaged */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MASK) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MASK (0x1000000U) #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SHIFT (24U) /*! PCIE_CAP_DLL_STATE_CHANGED - Data Link Layer State Changed. */ #define PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SHIFT)) & PCIE_RC_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MASK) /*! @} */ /*! @name ROOT_CONTROL_ROOT_CAPABILITIES_REG - Root Control and Capabilities Register. */ /*! @{ */ #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MASK (0x1U) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SHIFT (0U) /*! PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN - System Error on Correctable Error Enable. */ #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SHIFT)) & PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MASK) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MASK (0x2U) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SHIFT (1U) /*! PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN - System Error on non-Fatal Error Enable. */ #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SHIFT)) & PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MASK) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MASK (0x4U) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SHIFT (2U) /*! PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN - System Error on Fatal Error Enable. */ #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SHIFT)) & PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MASK) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MASK (0x8U) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SHIFT (3U) /*! PCIE_CAP_PME_INT_EN - PME Interrupt Enable. */ #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SHIFT)) & PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MASK) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MASK (0x10U) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SHIFT (4U) /*! PCIE_CAP_CRS_SW_VISIBILITY_EN - Configuration RRS Software Visibility Enable. */ #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SHIFT)) & PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MASK) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MASK (0x10000U) #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SHIFT (16U) /*! PCIE_CAP_CRS_SW_VISIBILITY - Configuration RRS Software Visibility Capable. */ #define PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SHIFT)) & PCIE_RC_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MASK) /*! @} */ /*! @name ROOT_STATUS_REG - Root Status Register. */ /*! @{ */ #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MASK (0xFFFFU) #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SHIFT (0U) /*! PCIE_CAP_PME_REQ_ID - PME Requester ID. */ #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SHIFT)) & PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MASK) #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MASK (0x10000U) #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SHIFT (16U) /*! PCIE_CAP_PME_STATUS - PME Status. */ #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SHIFT)) & PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MASK) #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MASK (0x20000U) #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SHIFT (17U) /*! PCIE_CAP_PME_PENDING - PME Pending. */ #define PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SHIFT)) & PCIE_RC_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MASK) /*! @} */ /*! @name DEVICE_CAPABILITIES2_REG - Device Capabilities 2 Register. */ /*! @{ */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK (0xFU) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT (0U) /*! PCIE_CAP_CPL_TIMEOUT_RANGE - Completion Timeout Ranges Supported. * 0b0000..Completion Timeout programming not supported, the Function must implement a timeout value in the range 50 us to 50 ms. * 0b0001..Range A * 0b0011..Ranges A and B * 0b0111..Ranges A, B, and C * 0b1111..Ranges A, B, C, and D * 0b0010..Range B * 0b0110..Ranges B and C * 0b1110..Ranges B, C, and D */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK (0x10U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT (4U) /*! PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT - Completion Timeout Disable Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK (0x20U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT (5U) /*! PCIE_CAP_ARI_FORWARD_SUPPORT - ARI Forwarding Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK (0x40U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT (6U) /*! PCIE_CAP_ATOMIC_ROUTING_SUPP - AtomicOp Routing Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK (0x80U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT (7U) /*! PCIE_CAP_32_ATOMIC_CPL_SUPP - 32-bit AtomicOp Completer Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK (0x100U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT (8U) /*! PCIE_CAP_64_ATOMIC_CPL_SUPP - 64-bit AtomicOp Completer Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK (0x200U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT (9U) /*! PCIE_CAP_128_CAS_CPL_SUPP - 128-bit CAS Completer Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK (0x400U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT (10U) /*! PCIE_CAP_NO_RO_EN_PR2PR_PAR - No RO-enabled PR-PR Passing. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK (0x800U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT (11U) /*! PCIE_CAP_LTR_SUPP - LTR Mechanism Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK (0x1000U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT (12U) /*! PCIE_CAP_TPH_CMPLT_SUPPORT_0 - TPH Completer Supported Bit 0. * 0b0..TPH and Extended TPH Completer not supported (if TPH Completer Supported Bit is 0) or Reserved ((if TPH Completer Supported Bit is 1). * 0b1..TPH Completer supported; Extended TPH Completer not supported(if TPH Completer Supported Bit is 0) or * Both TPH and Extended TPH Completer supported ((if TPH Completer Supported Bit is 1). */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK (0x2000U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT (13U) /*! PCIE_CAP_TPH_CMPLT_SUPPORT_1 - TPH Completer Supported Bit 1. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK (0x10000U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT (16U) /*! PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT - 10-Bit Tag Completer Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK (0x20000U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT (17U) /*! PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT - 10-Bit Tag Requester Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_MASK (0x10000000U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_SHIFT (28U) /*! PCIE_CAP_DMWR_CPL_SUPP - Deferrable Memory Write (DMWr) Completer Supported. */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_CPL_SUPP_MASK) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_MASK (0x60000000U) #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_SHIFT (29U) /*! PCIE_CAP_DMWR_LEN_SUPP - Deferrable Memory Write (DMWr) Lengths Supported. * 0b01..1 up to 128 bytes * 0b00..0 up to 64 bytes */ #define PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_SHIFT)) & PCIE_RC_DEVICE_CAPABILITIES2_REG_PCIE_CAP_DMWR_LEN_SUPP_MASK) /*! @} */ /*! @name DEVICE_CONTROL2_DEVICE_STATUS2_REG - Device Control 2 and Status 2 Register. */ /*! @{ */ #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK (0xFU) #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT (0U) /*! PCIE_CAP_CPL_TIMEOUT_VALUE - Completion Timeout Value. * 0b0000..Default range: 50 us to 50 ms * 0b0101..16 ms to 55 ms * 0b1110..17 s to 64 s * 0b0010..1 ms to 10 ms * 0b1010..1 s to 3.5 s * 0b1001..260 ms to 900 ms * 0b1101..4 s to 13 s * 0b0001..50 us to 100 us * 0b0110..65 ms to 210 ms */ #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT)) & PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK) #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK (0x10U) #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT (4U) /*! PCIE_CAP_CPL_TIMEOUT_DISABLE - Completion Timeout Disable. */ #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT)) & PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK) #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK (0x20U) #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT (5U) /*! PCIE_CAP_ARI_FORWARD_SUPPORT_CS - ARI Forwarding Enable. */ #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT)) & PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK) #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MASK (0x400U) #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SHIFT (10U) /*! PCIE_CAP_LTR_EN - LTR Mechanism Enable. */ #define PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SHIFT)) & PCIE_RC_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_MASK) /*! @} */ /*! @name LINK_CAPABILITIES2_REG - Link Capabilities 2 Register. */ /*! @{ */ #define PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK (0xFEU) #define PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT (1U) /*! PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR - Supported Link Speeds Vector. * 0b1111111..last default value. * 0b0000000..Zero value. */ #define PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT)) & PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK) #define PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK (0x100U) #define PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT (8U) /*! PCIE_CAP_CROSS_LINK_SUPPORT - Crosslink Supported. */ #define PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT)) & PCIE_RC_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK) /*! @} */ /*! @name LINK_CONTROL2_LINK_STATUS2_REG - Link Control 2 and Status 2 Register. */ /*! @{ */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK (0xFU) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT (0U) /*! PCIE_CAP_TARGET_LINK_SPEED - Target Link Speed. * 0b0001..Supported Link Speeds Vector field bit 0 * 0b0010..Supported Link Speeds Vector field bit 1 * 0b0011..Supported Link Speeds Vector field bit 2 * 0b0100..Supported Link Speeds Vector field bit 3 * 0b0101..Supported Link Speeds Vector field bit 4 * 0b0110..Supported Link Speeds Vector field bit 5 * 0b0111..Supported Link Speeds Vector field bit 6 */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK (0x10U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT (4U) /*! PCIE_CAP_ENTER_COMPLIANCE - Enter Compliance. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK (0x20U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT (5U) /*! PCIE_CAP_HW_AUTO_SPEED_DISABLE - Hardware Autonomous Speed Disable. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK (0x40U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT (6U) /*! PCIE_CAP_SEL_DEEMPHASIS - Selectable De-emphasis. * 0b1..-3.5 dB * 0b0..-6 dB */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK (0x380U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT (7U) /*! PCIE_CAP_TX_MARGIN - Transmit Margin, This field controls the value of the non-deemphasized voltage level at the Transmitter pins. * 0b000..Normal operating range */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK (0x400U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT (10U) /*! PCIE_CAP_ENTER_MODIFIED_COMPLIANCE - Enter Modified Compliance. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK (0x800U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT (11U) /*! PCIE_CAP_COMPLIANCE_SOS - Compliance SOS. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK (0xF000U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT (12U) /*! PCIE_CAP_COMPLIANCE_PRESET - Compliance Preset/De-emphasis. * 0b0001..-3.5 dB (for 5.0 GT/s Data Rate) * 0b0000..-6 dB (for 5.0 GT/s Data Rate) */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK (0x10000U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT (16U) /*! PCIE_CAP_CURR_DEEMPHASIS - Current De-emphasis Level. * 0b1..-3.5 dB * 0b0..-6 dB */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MASK (0x20000U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SHIFT (17U) /*! PCIE_CAP_EQ_CPL - Equalization 8. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MASK (0x40000U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SHIFT (18U) /*! PCIE_CAP_EQ_CPL_P1 - Equalization 8. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MASK (0x80000U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SHIFT (19U) /*! PCIE_CAP_EQ_CPL_P2 - Equalization 8. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MASK (0x100000U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SHIFT (20U) /*! PCIE_CAP_EQ_CPL_P3 - Equalization 8. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_MASK) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MASK (0x200000U) #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SHIFT (21U) /*! PCIE_CAP_LINK_EQ_REQ - Link Equalization Request 8. */ #define PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_SHIFT)) & PCIE_RC_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_MASK) /*! @} */ /*! @name AER_EXT_CAP_HDR_OFF - Advanced Error Reporting Extended Capability Header. */ /*! @{ */ #define PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK (0xFFFFU) #define PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT (0U) /*! CAP_ID - AER Extended Capability ID. */ #define PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT)) & PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK) #define PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK (0xF0000U) #define PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT (16U) /*! CAP_VERSION - Capability Version. */ #define PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT)) & PCIE_RC_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK) #define PCIE_RC_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_RC_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. */ #define PCIE_RC_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT)) & PCIE_RC_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK) /*! @} */ /*! @name UNCORR_ERR_STATUS_OFF - Uncorrectable Error Status Register. */ /*! @{ */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK (0x10U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT (4U) /*! DL_PROTOCOL_ERR_STATUS - Data Link Protocol Error Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK (0x20U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT (5U) /*! SURPRISE_DOWN_ERR_STATUS - Surprise Down Error Status (Optional). */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK (0x1000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT (12U) /*! POIS_TLP_ERR_STATUS - Poisoned TLP Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK (0x2000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT (13U) /*! FC_PROTOCOL_ERR_STATUS - Flow Control Protocol Error Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK (0x4000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT (14U) /*! CMPLT_TIMEOUT_ERR_STATUS - Completion Timeout Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK (0x8000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT (15U) /*! CMPLT_ABORT_ERR_STATUS - Completer Abort Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK (0x10000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT (16U) /*! UNEXP_CMPLT_ERR_STATUS - Unexpected Completion Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK (0x20000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT (17U) /*! REC_OVERFLOW_ERR_STATUS - Receiver Overflow Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK (0x40000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT (18U) /*! MALF_TLP_ERR_STATUS - Malformed TLP Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK (0x80000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT (19U) /*! ECRC_ERR_STATUS - ECRC Error Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK (0x100000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT (20U) /*! UNSUPPORTED_REQ_ERR_STATUS - Unsupported Request Error Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK (0x400000U) #define PCIE_RC_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT (22U) /*! INTERNAL_ERR_STATUS - Uncorrectable Internal Error Status. */ #define PCIE_RC_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT)) & PCIE_RC_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK) /*! @} */ /*! @name UNCORR_ERR_MASK_OFF - Uncorrectable Error Mask Register. */ /*! @{ */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK (0x10U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT (4U) /*! DL_PROTOCOL_ERR_MASK - Data Link Protocol Error Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK (0x20U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT (5U) /*! SURPRISE_DOWN_ERR_MASK - Surprise Down Error Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK (0x1000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT (12U) /*! POIS_TLP_ERR_MASK - Poisoned TLP Error Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK (0x2000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT (13U) /*! FC_PROTOCOL_ERR_MASK - Flow Control Protocol Error Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK (0x4000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT (14U) /*! CMPLT_TIMEOUT_ERR_MASK - Completion Timeout Error Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK (0x8000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT (15U) /*! CMPLT_ABORT_ERR_MASK - Completer Abort Error Mask (Optional). */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK (0x10000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT (16U) /*! UNEXP_CMPLT_ERR_MASK - Unexpected Completion Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK (0x20000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT (17U) /*! REC_OVERFLOW_ERR_MASK - Receiver Overflow Mask (Optional). */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK (0x40000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT (18U) /*! MALF_TLP_ERR_MASK - Malformed TLP Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK (0x80000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT (19U) /*! ECRC_ERR_MASK - ECRC Error Mask (Optional). */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK (0x100000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT (20U) /*! UNSUPPORTED_REQ_ERR_MASK - Unsupported Request Error Mask. */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK) #define PCIE_RC_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK (0x400000U) #define PCIE_RC_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT (22U) /*! INTERNAL_ERR_MASK - Uncorrectable Internal Error Mask (Optional). */ #define PCIE_RC_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT)) & PCIE_RC_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK) /*! @} */ /*! @name UNCORR_ERR_SEV_OFF - Uncorrectable Error Severity Register. */ /*! @{ */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK (0x10U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT (4U) /*! DL_PROTOCOL_ERR_SEVERITY - Data Link Protocol Error Severity. */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK (0x20U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT (5U) /*! SURPRISE_DOWN_ERR_SVRITY - Surprise Down Error Severity (Optional). */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK (0x1000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT (12U) /*! POIS_TLP_ERR_SEVERITY - Poisoned TLP Severity. */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK (0x2000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT (13U) /*! FC_PROTOCOL_ERR_SEVERITY - Flow Control Protocol Error Severity (Optional). */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK (0x4000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT (14U) /*! CMPLT_TIMEOUT_ERR_SEVERITY - Completion Timeout Error Severity. */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK (0x8000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT (15U) /*! CMPLT_ABORT_ERR_SEVERITY - Completer Abort Error Severity (Optional). */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK (0x10000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT (16U) /*! UNEXP_CMPLT_ERR_SEVERITY - Unexpected Completion Error Severity. */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK (0x20000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT (17U) /*! REC_OVERFLOW_ERR_SEVERITY - Receiver Overflow Error Severity (Optional). */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK (0x40000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT (18U) /*! MALF_TLP_ERR_SEVERITY - Malformed TLP Severity. */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK (0x80000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT (19U) /*! ECRC_ERR_SEVERITY - ECRC Error Severity (Optional). */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK (0x100000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT (20U) /*! UNSUPPORTED_REQ_ERR_SEVERITY - Unsupported Request Error Severity. */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK) #define PCIE_RC_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK (0x400000U) #define PCIE_RC_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT (22U) /*! INTERNAL_ERR_SEVERITY - Uncorrectable Internal Error Severity (Optional). */ #define PCIE_RC_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT)) & PCIE_RC_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK) /*! @} */ /*! @name CORR_ERR_STATUS_OFF - Correctable Error Status Register. */ /*! @{ */ #define PCIE_RC_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK (0x1U) #define PCIE_RC_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT (0U) /*! RX_ERR_STATUS - Receiver Error Status (Optional). */ #define PCIE_RC_CORR_ERR_STATUS_OFF_RX_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK) #define PCIE_RC_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK (0x40U) #define PCIE_RC_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT (6U) /*! BAD_TLP_STATUS - Bad TLP Status. */ #define PCIE_RC_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK) #define PCIE_RC_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK (0x80U) #define PCIE_RC_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT (7U) /*! BAD_DLLP_STATUS - Bad DLLP Status. */ #define PCIE_RC_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK) #define PCIE_RC_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK (0x100U) #define PCIE_RC_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT (8U) /*! REPLAY_NO_ROLEOVER_STATUS - REPLAY_NUM Rollover Status. */ #define PCIE_RC_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK) #define PCIE_RC_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK (0x1000U) #define PCIE_RC_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT (12U) /*! RPL_TIMER_TIMEOUT_STATUS - Replay Timer Timeout Status. */ #define PCIE_RC_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK) #define PCIE_RC_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK (0x2000U) #define PCIE_RC_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT (13U) /*! ADVISORY_NON_FATAL_ERR_STATUS - Advisory Non-Fatal Error Status. */ #define PCIE_RC_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK) #define PCIE_RC_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK (0x4000U) #define PCIE_RC_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT (14U) /*! CORRECTED_INT_ERR_STATUS - Corrected Internal Error Status (Optional). */ #define PCIE_RC_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK) #define PCIE_RC_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK (0x8000U) #define PCIE_RC_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT (15U) /*! HEADER_LOG_OVERFLOW_STATUS - Header Log Overflow Error Status (Optional). */ #define PCIE_RC_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT)) & PCIE_RC_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK) /*! @} */ /*! @name CORR_ERR_MASK_OFF - Correctable Error Mask Register. */ /*! @{ */ #define PCIE_RC_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK (0x1U) #define PCIE_RC_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT (0U) /*! RX_ERR_MASK - Receiver Error Mask (Optional). */ #define PCIE_RC_CORR_ERR_MASK_OFF_RX_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK) #define PCIE_RC_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK (0x40U) #define PCIE_RC_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT (6U) /*! BAD_TLP_MASK - Bad TLP Mask. */ #define PCIE_RC_CORR_ERR_MASK_OFF_BAD_TLP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK) #define PCIE_RC_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK (0x80U) #define PCIE_RC_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT (7U) /*! BAD_DLLP_MASK - Bad DLLP Mask. */ #define PCIE_RC_CORR_ERR_MASK_OFF_BAD_DLLP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK) #define PCIE_RC_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK (0x100U) #define PCIE_RC_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT (8U) /*! REPLAY_NO_ROLEOVER_MASK - REPLAY_NUM Rollover Mask. */ #define PCIE_RC_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK) #define PCIE_RC_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK (0x1000U) #define PCIE_RC_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT (12U) /*! RPL_TIMER_TIMEOUT_MASK - Replay Timer Timeout Mask. */ #define PCIE_RC_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK) #define PCIE_RC_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK (0x2000U) #define PCIE_RC_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT (13U) /*! ADVISORY_NON_FATAL_ERR_MASK - Advisory Non-Fatal Error Mask. */ #define PCIE_RC_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK) #define PCIE_RC_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK (0x4000U) #define PCIE_RC_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT (14U) /*! CORRECTED_INT_ERR_MASK - Corrected Internal Error Mask (Optional). */ #define PCIE_RC_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK) #define PCIE_RC_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK (0x8000U) #define PCIE_RC_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT (15U) /*! HEADER_LOG_OVERFLOW_MASK - Header Log Overflow Error Mask (Optional). */ #define PCIE_RC_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT)) & PCIE_RC_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK) /*! @} */ /*! @name ADV_ERR_CAP_CTRL_OFF - Advanced Error Capabilities and Control Register. */ /*! @{ */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK (0x1FU) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT (0U) /*! FIRST_ERR_POINTER - First Error Pointer. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK (0x20U) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT (5U) /*! ECRC_GEN_CAP - ECRC Generation Capable. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK (0x40U) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT (6U) /*! ECRC_GEN_EN - ECRC Generation Enable. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK (0x80U) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT (7U) /*! ECRC_CHECK_CAP - ECRC Check Capable. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK (0x100U) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT (8U) /*! ECRC_CHECK_EN - ECRC Check Enable. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK (0x200U) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT (9U) /*! MULTIPLE_HEADER_CAP - Multiple Header Recording Capable. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK (0x400U) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT (10U) /*! MULTIPLE_HEADER_EN - Multiple Header Recording Enable. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MASK (0x1000U) #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SHIFT (12U) /*! CTO_PRFX_HDR_LOG_CAP - Completion Timeout Prefix/Header Log Capable. */ #define PCIE_RC_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_SHIFT)) & PCIE_RC_ADV_ERR_CAP_CTRL_OFF_CTO_PRFX_HDR_LOG_CAP_MASK) /*! @} */ /*! @name HDR_LOG_0_OFF - Header Log Register 0. */ /*! @{ */ #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT (0U) /*! FIRST_DWORD_FIRST_BYTE - Byte 0 of Header log register of First 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK) #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT (8U) /*! FIRST_DWORD_SECOND_BYTE - Byte 1 of Header log register of First 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK) #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT (16U) /*! FIRST_DWORD_THIRD_BYTE - Byte 2 of Header log register of First 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK) #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT (24U) /*! FIRST_DWORD_FOURTH_BYTE - Byte 3 of Header log register of First 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name HDR_LOG_1_OFF - Header Log Register 1. */ /*! @{ */ #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT (0U) /*! SECOND_DWORD_FIRST_BYTE - Byte 0 of Header log register of Second 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK) #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT (8U) /*! SECOND_DWORD_SECOND_BYTE - Byte 1 of Header log register of Second 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK) #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT (16U) /*! SECOND_DWORD_THIRD_BYTE - Byte 2 of Header log register of Second 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK) #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT (24U) /*! SECOND_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Second 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name HDR_LOG_2_OFF - Header Log Register 2. */ /*! @{ */ #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT (0U) /*! THIRD_DWORD_FIRST_BYTE - Byte 0 of Header log register of Third 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK) #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT (8U) /*! THIRD_DWORD_SECOND_BYTE - Byte 1 of Header log register of Third 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK) #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT (16U) /*! THIRD_DWORD_THIRD_BYTE - Byte 2 of Header log register of Third 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK) #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT (24U) /*! THIRD_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Third 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name HDR_LOG_3_OFF - Header Log Register 3. */ /*! @{ */ #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT (0U) /*! FOURTH_DWORD_FIRST_BYTE - Byte 0 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK) #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT (8U) /*! FOURTH_DWORD_SECOND_BYTE - Byte 1 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK) #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT (16U) /*! FOURTH_DWORD_THIRD_BYTE - Byte 2 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK) #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT (24U) /*! FOURTH_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Fourth 32-bit Data Word. */ #define PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_RC_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK) /*! @} */ /*! @name ROOT_ERR_CMD_OFF - Root Error Command Register. */ /*! @{ */ #define PCIE_RC_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MASK (0x1U) #define PCIE_RC_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SHIFT (0U) /*! CORR_ERR_REPORTING_EN - Correctable Error Reporting Enable. */ #define PCIE_RC_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SHIFT)) & PCIE_RC_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MASK) #define PCIE_RC_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MASK (0x2U) #define PCIE_RC_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SHIFT (1U) /*! NON_FATAL_ERR_REPORTING_EN - Non-Fatal Error Reporting Enable. */ #define PCIE_RC_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SHIFT)) & PCIE_RC_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MASK) #define PCIE_RC_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MASK (0x4U) #define PCIE_RC_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SHIFT (2U) /*! FATAL_ERR_REPORTING_EN - Fatal Error Reporting Enable. */ #define PCIE_RC_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SHIFT)) & PCIE_RC_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MASK) /*! @} */ /*! @name ROOT_ERR_STATUS_OFF - Root Error Status Register. */ /*! @{ */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MASK (0x1U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SHIFT (0U) /*! ERR_COR_RX - Correctable Error Received. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_COR_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MASK) #define PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MASK (0x2U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SHIFT (1U) /*! MUL_ERR_COR_RX - Multiple Correctable Errors Received. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MASK) #define PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MASK (0x4U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SHIFT (2U) /*! ERR_FATAL_NON_FATAL_RX - Fatal or Non-Fatal Error Received. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MASK) #define PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MASK (0x8U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SHIFT (3U) /*! MUL_ERR_FATAL_NON_FATAL_RX - Multiple Fatal or Non-Fatal Errors Received. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MASK) #define PCIE_RC_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MASK (0x10U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SHIFT (4U) /*! FIRST_UNCORR_FATAL - First Uncorrectable Error is Fatal. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MASK) #define PCIE_RC_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MASK (0x20U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SHIFT (5U) /*! NON_FATAL_ERR_MSG_RX - One or more Non-Fatal Error Messages Received. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MASK) #define PCIE_RC_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MASK (0x40U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SHIFT (6U) /*! FATAL_ERR_MSG_RX - One or more Fatal Error Messages Received. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MASK) #define PCIE_RC_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MASK (0xF8000000U) #define PCIE_RC_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SHIFT (27U) /*! ADV_ERR_INT_MSG_NUM - Advanced Error Interrupt Message Number. */ #define PCIE_RC_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SHIFT)) & PCIE_RC_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MASK) /*! @} */ /*! @name ERR_SRC_ID_OFF - Error Source Identification Register. */ /*! @{ */ #define PCIE_RC_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MASK (0xFFFFU) #define PCIE_RC_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SHIFT (0U) /*! ERR_COR_SOURCE_ID - Source of Correctable Error. */ #define PCIE_RC_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SHIFT)) & PCIE_RC_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MASK) #define PCIE_RC_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MASK (0xFFFF0000U) #define PCIE_RC_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SHIFT (16U) /*! ERR_FATAL_NON_FATAL_SOURCE_ID - Source of Fatal/Non-Fatal Error. */ #define PCIE_RC_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SHIFT)) & PCIE_RC_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_1_OFF - TLP Prefix Log Register 1. */ /*! @{ */ #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_1_FIRST_BYTE - Byte 0 of Error TLP Prefix Log 1. */ #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_1_SECOND_BYTE - Byte 1 of Error TLP Prefix Log 1. */ #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_1_THIRD_BYTE - Byte 2 of Error TLP Prefix Log 1. */ #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_1_FOURTH_BYTE - Byte 3 of Error TLP Prefix Log 1. */ #define PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_2_OFF - TLP Prefix Log Register 2. */ /*! @{ */ #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_2_FIRST_BYTE - Byte 0 Error TLP Prefix Log 2. */ #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_2_SECOND_BYTE - Byte 1 Error TLP Prefix Log 2. */ #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_2_THIRD_BYTE - Byte 2 Error TLP Prefix Log 2. */ #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_2_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 2. */ #define PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_3_OFF - TLP Prefix Log Register 3. */ /*! @{ */ #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_3_FIRST_BYTE - Byte 0 Error TLP Prefix Log 3. */ #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_3_SECOND_BYTE - Byte 1 Error TLP Prefix Log 3. */ #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_3_THIRD_BYTE - Byte 2 Error TLP Prefix Log 3. */ #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_3_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 3. */ #define PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK) /*! @} */ /*! @name TLP_PREFIX_LOG_4_OFF - TLP Prefix Log Register 4. */ /*! @{ */ #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK (0xFFU) #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT (0U) /*! CFG_TLP_PFX_LOG_4_FIRST_BYTE - Byte 0 Error TLP Prefix Log 4. */ #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK (0xFF00U) #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT (8U) /*! CFG_TLP_PFX_LOG_4_SECOND_BYTE - Byte 1 Error TLP Prefix Log 4. */ #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK (0xFF0000U) #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT (16U) /*! CFG_TLP_PFX_LOG_4_THIRD_BYTE - Byte 2 Error TLP Prefix Log 4. */ #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK) #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK (0xFF000000U) #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT (24U) /*! CFG_TLP_PFX_LOG_4_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 4. */ #define PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT)) & PCIE_RC_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK) /*! @} */ /*! @name SPCIE_CAP_HEADER_REG - SPCIE Capability Header. */ /*! @{ */ #define PCIE_RC_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK (0xFFFFU) #define PCIE_RC_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT (0U) /*! EXTENDED_CAP_ID - Secondary PCI Express Extended Capability ID. * 0b1111111111111111..Max value * 0b0000000000000000..Min value */ #define PCIE_RC_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT)) & PCIE_RC_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK) #define PCIE_RC_SPCIE_CAP_HEADER_REG_CAP_VERSION_MASK (0xF0000U) #define PCIE_RC_SPCIE_CAP_HEADER_REG_CAP_VERSION_SHIFT (16U) /*! CAP_VERSION - Capability Version. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_RC_SPCIE_CAP_HEADER_REG_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_HEADER_REG_CAP_VERSION_SHIFT)) & PCIE_RC_SPCIE_CAP_HEADER_REG_CAP_VERSION_MASK) #define PCIE_RC_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_RC_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. * 0b111111111111..Max value. * 0b000000000000..Min value */ #define PCIE_RC_SPCIE_CAP_HEADER_REG_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_SHIFT)) & PCIE_RC_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_MASK) /*! @} */ /*! @name LINK_CONTROL3_REG - Link Control 3 Register. */ /*! @{ */ #define PCIE_RC_LINK_CONTROL3_REG_PERFORM_EQ_MASK (0x1U) #define PCIE_RC_LINK_CONTROL3_REG_PERFORM_EQ_SHIFT (0U) /*! PERFORM_EQ - Perform Equalization. * 0b0..Clear * 0b1..When this bit is 1b and a 1b is written to the Retrain Link bit with the Target Link Speed field set to * 8.0 GT/s or higher, the Downstream Port must perform Link Equalization. */ #define PCIE_RC_LINK_CONTROL3_REG_PERFORM_EQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL3_REG_PERFORM_EQ_SHIFT)) & PCIE_RC_LINK_CONTROL3_REG_PERFORM_EQ_MASK) #define PCIE_RC_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MASK (0x2U) #define PCIE_RC_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SHIFT (1U) /*! EQ_REQ_INT_EN - Link Equalization Request Interrupt Enable. * 0b0..Clear * 0b1..When Set, this bit enables the generation of an interrupt to indicate that the Link Equalization Request * 8.0 GT/s bit, the Link Equalization Request 16.0 GT/s bit, or the Link Equalization Request 32.0 GT/s bit * has been set. */ #define PCIE_RC_LINK_CONTROL3_REG_EQ_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_CONTROL3_REG_EQ_REQ_INT_EN_SHIFT)) & PCIE_RC_LINK_CONTROL3_REG_EQ_REQ_INT_EN_MASK) /*! @} */ /*! @name LANE_ERR_STATUS_REG - Lane Error Status Register. */ /*! @{ */ #define PCIE_RC_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MASK (0x3U) #define PCIE_RC_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SHIFT (0U) /*! LANE_ERR_STATUS - Lane Error Status Bits per Lane. */ #define PCIE_RC_LANE_ERR_STATUS_REG_LANE_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_SHIFT)) & PCIE_RC_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_MASK) #define PCIE_RC_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MASK (0xFFFFFFFCU) #define PCIE_RC_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SHIFT (2U) /*! RSVDP_LANE_ERR_STATUS - Reserved for future use. */ #define PCIE_RC_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_SHIFT)) & PCIE_RC_LANE_ERR_STATUS_REG_RSVDP_LANE_ERR_STATUS_MASK) /*! @} */ /*! @name SPCIE_CAP_OFF_0CH_REG - Lane Equalization Control Register for lanes 1 and 0. */ /*! @{ */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MASK (0xFU) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SHIFT (0U) /*! DSP_TX_PRESET0 - Downstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_MASK) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MASK (0x70U) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SHIFT (4U) /*! DSP_RX_PRESET_HINT0 - Downstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_MASK) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MASK (0xF00U) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SHIFT (8U) /*! USP_TX_PRESET0 - Upstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_MASK) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MASK (0x7000U) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SHIFT (12U) /*! USP_RX_PRESET_HINT0 - Upstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_MASK) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MASK (0xF0000U) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SHIFT (16U) /*! DSP_TX_PRESET1 - Downstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_MASK) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MASK (0x700000U) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SHIFT (20U) /*! DSP_RX_PRESET_HINT1 - Downstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_MASK) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MASK (0xF000000U) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SHIFT (24U) /*! USP_TX_PRESET1 - Upstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_MASK) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MASK (0x70000000U) #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SHIFT (28U) /*! USP_RX_PRESET_HINT1 - Upstream Port 8. */ #define PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_SHIFT)) & PCIE_RC_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_MASK) /*! @} */ /*! @name L1SUB_CAP_HEADER_REG - L1 Substates Extended Capability Header. */ /*! @{ */ #define PCIE_RC_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK (0xFFFFU) #define PCIE_RC_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT (0U) /*! EXTENDED_CAP_ID - L1SUB Extended Capability ID. */ #define PCIE_RC_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT)) & PCIE_RC_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK) #define PCIE_RC_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK (0xF0000U) #define PCIE_RC_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT (16U) /*! CAP_VERSION - Capability Version. */ #define PCIE_RC_L1SUB_CAP_HEADER_REG_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT)) & PCIE_RC_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK) #define PCIE_RC_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_RC_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. */ #define PCIE_RC_L1SUB_CAP_HEADER_REG_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT)) & PCIE_RC_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK) /*! @} */ /*! @name L1SUB_CAPABILITY_REG - L1 Substates Capability Register. */ /*! @{ */ #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK (0x1U) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT (0U) /*! L1_2_PCIPM_SUPPORT - PCI-PM L12 Supported. */ #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK (0x2U) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT (1U) /*! L1_1_PCIPM_SUPPORT - PCI-PM L11 Supported. */ #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK (0x4U) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT (2U) /*! L1_2_ASPM_SUPPORT - ASPM L12 Supported. */ #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK (0x8U) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT (3U) /*! L1_1_ASPM_SUPPORT - ASPM L11 Supported. */ #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK (0x10U) #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT (4U) /*! L1_PMSUB_SUPPORT - L1 PM Substates ECN Supported. */ #define PCIE_RC_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK) #define PCIE_RC_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK (0xFF00U) #define PCIE_RC_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT (8U) /*! COMM_MODE_SUPPORT - Port Common Mode Restore Time. */ #define PCIE_RC_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK) #define PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK (0x30000U) #define PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT (16U) /*! PWR_ON_SCALE_SUPPORT - Port T Power On Scale. * 0b11..Reserved * 0b10..Scale is 100us * 0b01..Scale is 10us * 0b00..Scale is 2us */ #define PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK) #define PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK (0xF80000U) #define PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT (19U) /*! PWR_ON_VALUE_SUPPORT - Port T Power On Value. */ #define PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT)) & PCIE_RC_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK) /*! @} */ /*! @name L1SUB_CONTROL1_REG - L1 Substates Control 1 Register. */ /*! @{ */ #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK (0x1U) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT (0U) /*! L1_2_PCIPM_EN - PCI-PM L12 Enable. */ #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT)) & PCIE_RC_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK (0x2U) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT (1U) /*! L1_1_PCIPM_EN - PCI-PM L11 Enable. */ #define PCIE_RC_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT)) & PCIE_RC_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK (0x4U) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT (2U) /*! L1_2_ASPM_EN - ASPM L12 Enable. */ #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_ASPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT)) & PCIE_RC_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK (0x8U) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT (3U) /*! L1_1_ASPM_EN - ASPM L11 Enable. */ #define PCIE_RC_L1SUB_CONTROL1_REG_L1_1_ASPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT)) & PCIE_RC_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK) #define PCIE_RC_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK (0xFF00U) #define PCIE_RC_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT (8U) /*! T_COMMON_MODE - Common Mode Restore Time. */ #define PCIE_RC_L1SUB_CONTROL1_REG_T_COMMON_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT)) & PCIE_RC_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK (0x3FF0000U) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT (16U) /*! L1_2_TH_VAL - LTR L12 Threshold Value. */ #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_VAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT)) & PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK (0xE0000000U) #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT (29U) /*! L1_2_TH_SCA - LTR L12 Threshold Scale. */ #define PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_SCA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT)) & PCIE_RC_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK) /*! @} */ /*! @name L1SUB_CONTROL2_REG - L1 Substates Control 2 Register. */ /*! @{ */ #define PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK (0x3U) #define PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT (0U) /*! T_POWER_ON_SCALE - T Power On Scale. * 0b11..Reserved * 0b10..Scale is 100us * 0b01..Scale is 10us * 0b00..Scale is 2us */ #define PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT)) & PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK) #define PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK (0xF8U) #define PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT (3U) /*! T_POWER_ON_VALUE - T Power On Value. */ #define PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT)) & PCIE_RC_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK) /*! @} */ /*! @name VSECDMA_EXT_CAP_HDR_OFF - PCIe Extended Capability ID, Capability Version, and Next Capability Offset Register. */ /*! @{ */ #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_ID_MASK (0xFFFFU) #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_ID_SHIFT (0U) /*! ID - PCI Express Extended Capability ID. */ #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_ID_SHIFT)) & PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_ID_MASK) #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_CAP_MASK (0xF0000U) #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_CAP_SHIFT (16U) /*! CAP - Capability Version. */ #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_CAP_SHIFT)) & PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_CAP_MASK) #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK (0xFFF00000U) #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT (20U) /*! NEXT_OFFSET - Next Capability Offset. */ #define PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT)) & PCIE_RC_VSECDMA_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK) /*! @} */ /*! @name VSECDMA_VENDOR_SPECIFIC_HDR_OFF - Vendor Specific Header Register. */ /*! @{ */ #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MASK (0xFFFFU) #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SHIFT (0U) /*! VSEC_ID - VSEC ID. */ #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SHIFT)) & PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_MASK) #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MASK (0xF0000U) #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SHIFT (16U) /*! VSEC_REV - VSEC Rev. */ #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SHIFT)) & PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_MASK) #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MASK (0xFFF00000U) #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SHIFT (20U) /*! VSEC_LENGTH - VSEC Length. */ #define PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SHIFT)) & PCIE_RC_VSECDMA_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_MASK) /*! @} */ /*! @name VSECDMA_DEVICE_INFORMATION_OFF - DMA and related AXI Bridge Implementation Information. */ /*! @{ */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_MASK (0x7U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_SHIFT (0U) /*! MAP_FORMAT - Defines the register map format and features to be one of the following values: Other values are reserved. * 0b000..Legacy DMA register map accessed by the port-logic registers * 0b001..Legacy DMA register map, mapped to a PF/BAR * 0b101..HDMA compatibility mode (CC_LEGACY_DMA_MAP =1) register map, mapped to a PF/BAR * 0b100..HDMA/DMA compatibility (CC_LEGACY_DMA_MAP =1) register map without access through the Wire * 0b111..HDMA native (CC_LEGACY_DMA_MAP =0) register map, mapped to a PF/BAR * 0b110..HDMA native (CC_LEGACY_DMA_MAP =0) register map without access through the Wire */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MAP_FORMAT_MASK) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_BARN_MASK (0x700U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_BARN_SHIFT (8U) /*! BARN - Bar Number. */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_BARN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_BARN_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_BARN_MASK) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_PFN_MASK (0xF800U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_PFN_SHIFT (11U) /*! PFN - Physical Function Number. */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_PFN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_PFN_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_PFN_MASK) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_MASK (0x70000U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_SHIFT (16U) /*! CHANNEL_SEPARATION - If the MAP_FORMAT is set to HDMA_NATIVE, this field specifies the read write channel address separation. * 0b110..16k separated * 0b010..1k separated * 0b000..256 separated * 0b011..2k separated * 0b111..32k separated * 0b100..4k separated * 0b001..512 separated * 0b101..8k separated */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_CHANNEL_SEPARATION_MASK) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_AXI_MASK (0x80000U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_AXI_SHIFT (19U) /*! AXI - This field provides information about AXI interface usage. */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_AXI(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_AXI_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_AXI_MASK) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_MASK (0x700000U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_SHIFT (20U) /*! MASTER_BUS_WIDTH - This field provides information regarding the AXI master data bus width. * 0b010..128 bits * 0b011..256 bits * 0b000..32 bits * 0b100..512 bits * 0b001..64 bits */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BUS_WIDTH_MASK) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_MASK (0x3800000U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_SHIFT (23U) /*! MASTER_BURST_LENGTH - Reports the CC_MSTR_BURST_LEN configuration parameter. * 0b000..Reserved * 0b110..128 beats * 0b011..16 beats * 0b111..256 beats * 0b100..32 beats * 0b001..4 beats * 0b101..64 beats * 0b010..8 beats */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_BURST_LENGTH_MASK) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_MASK (0x3C000000U) #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_SHIFT (26U) /*! MASTER_PAGE_BOUNDARY_POINTER_WIDTH - This field provides address page boundary information. */ #define PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_SHIFT)) & PCIE_RC_VSECDMA_DEVICE_INFORMATION_OFF_MASTER_PAGE_BOUNDARY_POINTER_WIDTH_MASK) /*! @} */ /*! @name VSECDMA_NUM_CHAN_OFF - Number of Implemented Channels Register. */ /*! @{ */ #define PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_MASK (0x3FFU) #define PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_SHIFT (0U) /*! NUM_DMA_WR_CHAN - This field provides information regarding the number of implemented write channels. */ #define PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_SHIFT)) & PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_WR_CHAN_MASK) #define PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_MASK (0x3FF0000U) #define PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_SHIFT (16U) /*! NUM_DMA_RD_CHAN - This field provides information regarding the number of implemented read channels. */ #define PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_SHIFT)) & PCIE_RC_VSECDMA_NUM_CHAN_OFF_NUM_DMA_RD_CHAN_MASK) /*! @} */ /*! @name VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF - DMA Register Map Start Address Offset Low Register. */ /*! @{ */ #define PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_MASK (0xFFFFFFFFU) #define PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_SHIFT (0U) /*! UNROLL_ADDR_OFFSET_LOW - BAR address offset, 32-bit LSB. */ #define PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_SHIFT)) & PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_LOW_OFF_UNROLL_ADDR_OFFSET_LOW_MASK) /*! @} */ /*! @name VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF - DMA Register Map Start Address Offset High Register. */ /*! @{ */ #define PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_MASK (0xFFFFFFFFU) #define PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_SHIFT (0U) /*! UNROLL_ADDR_OFFSET_HIGH - BAR address offset, 32-bit MSB. */ #define PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_SHIFT)) & PCIE_RC_VSECDMA_UNROLL_ADDR_OFFSET_HIGH_OFF_UNROLL_ADDR_OFFSET_HIGH_MASK) /*! @} */ /*! @name ACK_LATENCY_TIMER_OFF - Ack Latency Timer and Replay Timer Register. */ /*! @{ */ #define PCIE_RC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK (0xFFFFU) #define PCIE_RC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT (0U) /*! ROUND_TRIP_LATENCY_TIME_LIMIT - Ack Latency Timer Limit. */ #define PCIE_RC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT)) & PCIE_RC_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK) #define PCIE_RC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK (0xFFFF0000U) #define PCIE_RC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT (16U) /*! REPLAY_TIME_LIMIT - Replay Timer Limit. */ #define PCIE_RC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT)) & PCIE_RC_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK) /*! @} */ /*! @name VENDOR_SPEC_DLLP_OFF - Vendor Specific DLLP Register. */ /*! @{ */ #define PCIE_RC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK (0xFFFFFFFFU) #define PCIE_RC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT (0U) /*! VENDOR_SPEC_DLLP - Vendor Specific DLLP Register. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT)) & PCIE_RC_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK) /*! @} */ /*! @name PORT_FORCE_OFF - Port Force Link Register. */ /*! @{ */ #define PCIE_RC_PORT_FORCE_OFF_LINK_NUM_MASK (0xFFU) #define PCIE_RC_PORT_FORCE_OFF_LINK_NUM_SHIFT (0U) /*! LINK_NUM - Link Number. */ #define PCIE_RC_PORT_FORCE_OFF_LINK_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_FORCE_OFF_LINK_NUM_SHIFT)) & PCIE_RC_PORT_FORCE_OFF_LINK_NUM_MASK) #define PCIE_RC_PORT_FORCE_OFF_FORCED_LTSSM_MASK (0xF00U) #define PCIE_RC_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT (8U) /*! FORCED_LTSSM - Forced Link Command. */ #define PCIE_RC_PORT_FORCE_OFF_FORCED_LTSSM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT)) & PCIE_RC_PORT_FORCE_OFF_FORCED_LTSSM_MASK) #define PCIE_RC_PORT_FORCE_OFF_FORCE_EN_MASK (0x8000U) #define PCIE_RC_PORT_FORCE_OFF_FORCE_EN_SHIFT (15U) /*! FORCE_EN - Force Link. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_PORT_FORCE_OFF_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_FORCE_OFF_FORCE_EN_SHIFT)) & PCIE_RC_PORT_FORCE_OFF_FORCE_EN_MASK) #define PCIE_RC_PORT_FORCE_OFF_LINK_STATE_MASK (0x3F0000U) #define PCIE_RC_PORT_FORCE_OFF_LINK_STATE_SHIFT (16U) /*! LINK_STATE - Forced LTSSM State. */ #define PCIE_RC_PORT_FORCE_OFF_LINK_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_FORCE_OFF_LINK_STATE_SHIFT)) & PCIE_RC_PORT_FORCE_OFF_LINK_STATE_MASK) #define PCIE_RC_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_MASK (0x400000U) #define PCIE_RC_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_SHIFT (22U) /*! SUPPORT_PART_LANES_RXEI_EXIT - Support LTSSM transition from Polling. * 0b1..Any lanes receives 8 consecutive TS OSs, LTSSM moves from Polling.Active to Polling.Config. If all lanes * do not receive 8 consecutive TS OSs and any predetermined lanes are still on Rx ElecIdle, LTSSM moves from * Polling.Active to Polling.Compliance. * 0b0..Any lanes receives 8 consecutive TS OS and all predetermined lanes have Rx ElecIdle exit, LTSSM moves * from Polling.Active to Polling.Config. This is legacy mode from Base Spec. Any predetermined lanes are still * on Rx ElecIdle, LTSSM moves from Polling.Active to Polling.Compliance. */ #define PCIE_RC_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_SHIFT)) & PCIE_RC_PORT_FORCE_OFF_SUPPORT_PART_LANES_RXEI_EXIT_MASK) #define PCIE_RC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK (0x800000U) #define PCIE_RC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT (23U) /*! DO_DESKEW_FOR_SRIS - DO_DESKEW_FOR_SRIS */ #define PCIE_RC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT)) & PCIE_RC_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK) /*! @} */ /*! @name ACK_F_ASPM_CTRL_OFF - Ack Frequency and L0-L1 ASPM Control Register. */ /*! @{ */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK (0xFFU) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT (0U) /*! ACK_FREQ - Ack Frequency. * 0b11111111..Any value between 1 and 255 indicates that the controller will schedule a high-priority ACK after receiving the specified number of TLPs. * 0b00000000..The value '0' indicates that this Ack Frequency Counter feature is turned off. */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT)) & PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK (0xFF00U) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT (8U) /*! ACK_N_FTS - The number of Fast Training Sequence(N_FTS) ordered sets to be transmitted when transitioning from L0s to L0. * 0b11111111..The maximum number of FTS ordered-sets that a component can request is 255. * 0b00000000..The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT)) & PCIE_RC_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK (0xFF0000U) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT (16U) /*! COMMON_CLK_N_FTS - Common Clock N_FTS. * 0b11111111..The maximum number of FTS ordered-sets that a component can request is 255. * 0b00000000..The controller does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT)) & PCIE_RC_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK (0x7000000U) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT (24U) /*! L0S_ENTRANCE_LATENCY - L0s Entrance Latency. * 0b000..1 us * 0b001..2 us * 0b010..3 us * 0b011..4 us * 0b100..5 us * 0b101..6 us * 0b111..7 us * 0b110..7 US */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT)) & PCIE_RC_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK (0x38000000U) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT (27U) /*! L1_ENTRANCE_LATENCY - L1 Entrance Latency. * 0b100..16 us * 0b000..1 us * 0b001..2 us * 0b101..32 us * 0b010..4 us * 0b111..64 us * 0b110..64Us * 0b011..8 us */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT)) & PCIE_RC_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK (0x40000000U) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT (30U) /*! ENTER_ASPM - ASPM L1 Entry Control. * 0b1..Controller enters ASPM L1 after a period in which it has been idle. * 0b0..Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT)) & PCIE_RC_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_MASK (0x80000000U) #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_SHIFT (31U) /*! ASPM_L1_TIMER_ENABLE - ASPM L1 Timer Enable. * 0b0..PM controller will initiate entry into L1 as soon as all the L1 idle conditions are bypassed. This * setting is only recommended when the application implements its own timers. * 0b1..PM controller starts the ASPM L1 timer whenever all the L1 idle conditions are met. This is the default recommended behavior */ #define PCIE_RC_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_SHIFT)) & PCIE_RC_ACK_F_ASPM_CTRL_OFF_ASPM_L1_TIMER_ENABLE_MASK) /*! @} */ /*! @name PORT_LINK_CTRL_OFF - Port Link Control Register. */ /*! @{ */ #define PCIE_RC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK (0x1U) #define PCIE_RC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT (0U) /*! VENDOR_SPECIFIC_DLLP_REQ - Vendor Specific DLLP Request. * 0b0..This is a self clearing register * 0b1..When software writes a '1' to this bit, the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF */ #define PCIE_RC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK (0x2U) #define PCIE_RC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT (1U) /*! SCRAMBLE_DISABLE - Scramble Disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK (0x4U) #define PCIE_RC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT (2U) /*! LOOPBACK_ENABLE - Loopback Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK (0x8U) #define PCIE_RC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT (3U) /*! RESET_ASSERT - Reset Assert. * 0b0..Clear * 0b1..Set */ #define PCIE_RC_PORT_LINK_CTRL_OFF_RESET_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK (0x20U) #define PCIE_RC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT (5U) /*! DLL_LINK_EN - DLL Link Enable. * 0b0..The controller does not transmit InitFC DLLPs and does not establish a link. * 0b1..Enables link initialization. */ #define PCIE_RC_PORT_LINK_CTRL_OFF_DLL_LINK_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK (0x40U) #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT (6U) /*! LINK_DISABLE - LINK_DISABLE is an internally reserved field. */ #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK (0x80U) #define PCIE_RC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT (7U) /*! FAST_LINK_MODE - Fast Link Mode. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_RATE_MASK (0xF00U) #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT (8U) /*! LINK_RATE - LINK_RATE is an internally reserved field. */ #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_RATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_LINK_RATE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK (0x3F0000U) #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT (16U) /*! LINK_CAPABLE - Link Mode Enable. * 0b000001..x1 * 0b011111..x16 * 0b000011..x2 * 0b111111..x32 (not supported) * 0b000111..x4 * 0b001111..x8 */ #define PCIE_RC_PORT_LINK_CTRL_OFF_LINK_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK (0x1000000U) #define PCIE_RC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT (24U) /*! BEACON_ENABLE - BEACON_ENABLE is an internally reserved field. */ #define PCIE_RC_PORT_LINK_CTRL_OFF_BEACON_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK (0x2000000U) #define PCIE_RC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT (25U) /*! CORRUPT_LCRC_ENABLE - CORRUPT_LCRC_ENABLE is an internally reserved field. */ #define PCIE_RC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK (0x4000000U) #define PCIE_RC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT (26U) /*! EXTENDED_SYNCH - EXTENDED_SYNCH is an internally reserved field. */ #define PCIE_RC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK) #define PCIE_RC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK (0x8000000U) #define PCIE_RC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT (27U) /*! TRANSMIT_LANE_REVERSALE_ENABLE - TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. */ #define PCIE_RC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT)) & PCIE_RC_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK) /*! @} */ /*! @name LANE_SKEW_OFF - Lane Skew Register. */ /*! @{ */ #define PCIE_RC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MASK (0xFFFFFFU) #define PCIE_RC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SHIFT (0U) /*! INSERT_LANE_SKEW - INSERT_LANE_SKEW is an internally reserved field. * 0b000000000000000011111111..Max value * 0b000000000000000000000000..Zero value */ #define PCIE_RC_LANE_SKEW_OFF_INSERT_LANE_SKEW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_SKEW_OFF_INSERT_LANE_SKEW_SHIFT)) & PCIE_RC_LANE_SKEW_OFF_INSERT_LANE_SKEW_MASK) #define PCIE_RC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MASK (0x1000000U) #define PCIE_RC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SHIFT (24U) /*! FLOW_CTRL_DISABLE - Flow Control Disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SHIFT)) & PCIE_RC_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MASK) #define PCIE_RC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MASK (0x2000000U) #define PCIE_RC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SHIFT (25U) /*! ACK_NAK_DISABLE - Ack/Nak Disable. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_LANE_SKEW_OFF_ACK_NAK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_SKEW_OFF_ACK_NAK_DISABLE_SHIFT)) & PCIE_RC_LANE_SKEW_OFF_ACK_NAK_DISABLE_MASK) #define PCIE_RC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MASK (0x4000000U) #define PCIE_RC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SHIFT (26U) /*! ELASTIC_BUFFER_MODE - Selects Elasticity Buffer operating mode: * 0b1..Nominal Empty Buffer Mode * 0b0..Nominal Half Full Buffer mode */ #define PCIE_RC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_SHIFT)) & PCIE_RC_LANE_SKEW_OFF_ELASTIC_BUFFER_MODE_MASK) #define PCIE_RC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MASK (0x78000000U) #define PCIE_RC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SHIFT (27U) /*! IMPLEMENT_NUM_LANES - Implementation-specific Number of Lanes. * 0b1111..16 lanes * 0b0000..1 lane * 0b0001..2 lanes * 0b0011..4 lanes * 0b0111..8 lanes */ #define PCIE_RC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SHIFT)) & PCIE_RC_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MASK) #define PCIE_RC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MASK (0x80000000U) #define PCIE_RC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SHIFT (31U) /*! DISABLE_LANE_TO_LANE_DESKEW - Disable Lane-to-Lane Deskew. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SHIFT)) & PCIE_RC_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MASK) /*! @} */ /*! @name TIMER_CTRL_MAX_FUNC_NUM_OFF - Timer Control and Max Function Number Register. */ /*! @{ */ #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK (0xFFU) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT (0U) /*! MAX_FUNC_NUM - Maximum function number that can be used in a request. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT)) & PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK (0x7C000U) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT (14U) /*! TIMER_MOD_REPLAY_TIMER - Replay Timer Limit Modifier. */ #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT)) & PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK (0xF80000U) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT (19U) /*! TIMER_MOD_ACK_NAK - Ack Latency Timer Modifier. */ #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT)) & PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK (0x1F000000U) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT (24U) /*! UPDATE_FREQ_TIMER - UPDATE_FREQ_TIMER is an internally reserved field. */ #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT)) & PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK (0x60000000U) #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT (29U) /*! FAST_LINK_SCALING_FACTOR - Fast Link Timer Scaling Factor. * 0b00..Scaling Factor is 1024 (1ms is 1us). When the LTSSM is in Config or L12 Entry State, 1ms timer is 2us, * 2ms timer is 4us and 3ms timer is 6us. * 0b11..Scaling Factor is 16 (1ms is 64us) * 0b01..Scaling Factor is 256 (1ms is 4us) * 0b10..Scaling Factor is 64 (1ms is 16us) */ #define PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT)) & PCIE_RC_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK) /*! @} */ /*! @name SYMBOL_TIMER_FILTER_1_OFF - Symbol Timer Register and Filter Mask 1 Register. */ /*! @{ */ #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK (0x7FFU) #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT (0U) /*! SKP_INT_VAL - SKP Interval Value. */ #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT)) & PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK) #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK (0x7800U) #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT (11U) /*! EIDLE_TIMER - EIDLE_TIMER is an internally reserved field. */ #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT)) & PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK) #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK (0x8000U) #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT (15U) /*! DISABLE_FC_WD_TIMER - Disable FC Watchdog Timer. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT)) & PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK) #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK (0xFFFF0000U) #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT (16U) /*! MASK_RADM_1 - Filter Mask 1. * 0b1111111111111111..Max value * 0b0000000000000000..Zero value */ #define PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT)) & PCIE_RC_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK) /*! @} */ /*! @name FILTER_MASK_2_OFF - Filter Mask 2 Register. */ /*! @{ */ #define PCIE_RC_FILTER_MASK_2_OFF_MASK_RADM_2_MASK (0xFFFFFFFFU) #define PCIE_RC_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT (0U) /*! MASK_RADM_2 - Filter Mask 2. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_FILTER_MASK_2_OFF_MASK_RADM_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT)) & PCIE_RC_FILTER_MASK_2_OFF_MASK_RADM_2_MASK) /*! @} */ /*! @name PL_DEBUG0_OFF - Debug Register 0. */ /*! @{ */ #define PCIE_RC_PL_DEBUG0_OFF_DEB_REG_0_MASK (0xFFFFFFFFU) #define PCIE_RC_PL_DEBUG0_OFF_DEB_REG_0_SHIFT (0U) /*! DEB_REG_0 - The value on cxpl_debug_info[31:0]. * 0b11111111111111111111111111111111..Max value. * 0b00000000000000000000000000000000..Zero value. */ #define PCIE_RC_PL_DEBUG0_OFF_DEB_REG_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_DEBUG0_OFF_DEB_REG_0_SHIFT)) & PCIE_RC_PL_DEBUG0_OFF_DEB_REG_0_MASK) /*! @} */ /*! @name PL_DEBUG1_OFF - Debug Register 1. */ /*! @{ */ #define PCIE_RC_PL_DEBUG1_OFF_DEB_REG_1_MASK (0xFFFFFFFFU) #define PCIE_RC_PL_DEBUG1_OFF_DEB_REG_1_SHIFT (0U) /*! DEB_REG_1 - The value on cxpl_debug_info[63:32]. * 0b11111111111111111111111111111111..Max value. * 0b00000000000000000000000000000000..Zero value. */ #define PCIE_RC_PL_DEBUG1_OFF_DEB_REG_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_DEBUG1_OFF_DEB_REG_1_SHIFT)) & PCIE_RC_PL_DEBUG1_OFF_DEB_REG_1_MASK) /*! @} */ /*! @name TX_P_FC_CREDIT_STATUS_OFF - Transmit Posted FC Credit Status. */ /*! @{ */ #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK (0xFFFU) #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT (0U) /*! TX_P_DATA_FC_CREDIT - Transmit Posted Data FC Credits. */ #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT)) & PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK) #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK (0xFF000U) #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT (12U) /*! TX_P_HEADER_FC_CREDIT - Transmit Posted Header FC Credits. */ #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT)) & PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK) #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MASK (0xFFF00000U) #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SHIFT (20U) /*! RSVDP_TX_P_FC_CREDIT_STATUS - Reserved */ #define PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_SHIFT)) & PCIE_RC_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_TX_P_FC_CREDIT_STATUS_MASK) /*! @} */ /*! @name TX_NP_FC_CREDIT_STATUS_OFF - Transmit Non-Posted FC Credit Status. */ /*! @{ */ #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK (0xFFFU) #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT (0U) /*! TX_NP_DATA_FC_CREDIT - Transmit Non-Posted Data FC Credits. */ #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT)) & PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK) #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK (0xFF000U) #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT (12U) /*! TX_NP_HEADER_FC_CREDIT - Transmit Non-Posted Header FC Credits. */ #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT)) & PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK) #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MASK (0xFFF00000U) #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SHIFT (20U) /*! RSVDP_TX_NP_FC_CREDIT_STATUS - Reserved */ #define PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_SHIFT)) & PCIE_RC_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_TX_NP_FC_CREDIT_STATUS_MASK) /*! @} */ /*! @name TX_CPL_FC_CREDIT_STATUS_OFF - Transmit Completion FC Credit Status */ /*! @{ */ #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK (0xFFFU) #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT (0U) /*! TX_CPL_DATA_FC_CREDIT - Transmit Completion Data FC Credits. */ #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT)) & PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK) #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK (0xFF000U) #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT (12U) /*! TX_CPL_HEADER_FC_CREDIT - Transmit Completion Header FC Credits. */ #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT)) & PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK) #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MASK (0xFFF00000U) #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SHIFT (20U) /*! RSVDP_TX_CPL_FC_CREDIT_STATUS - Reserved */ #define PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_SHIFT)) & PCIE_RC_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_TX_CPL_FC_CREDIT_STATUS_MASK) /*! @} */ /*! @name QUEUE_STATUS_OFF - Queue Status. */ /*! @{ */ #define PCIE_RC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK (0x1U) #define PCIE_RC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT (0U) /*! RX_TLP_FC_CREDIT_NON_RETURN - Received TLP FC Credits Not Returned. * 0b0..Clear * 0b1..Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that * the credits for that TLP have been restored by the receiver at the other end of the link. */ #define PCIE_RC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT)) & PCIE_RC_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK) #define PCIE_RC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK (0x2U) #define PCIE_RC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT (1U) /*! TX_RETRY_BUFFER_NE - Transmit Retry Buffer Not Empty. * 0b0..Clear * 0b1..Indicates that there is data in the transmit retry buffer. */ #define PCIE_RC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT)) & PCIE_RC_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK) #define PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK (0x4U) #define PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT (2U) /*! RX_QUEUE_NON_EMPTY - Receive Credit Queue Not Empty. * 0b0..Clear * 0b1..Indicates there is data in one or more of the receive buffers. */ #define PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT)) & PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK) #define PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK (0x8U) #define PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT (3U) /*! RX_QUEUE_OVERFLOW - Receive Credit Queue Overflow. * 0b0..Clear * 0b1..Indicates insufficient buffer space available to write to the P/NP/CPL credit queue. */ #define PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT)) & PCIE_RC_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK) #define PCIE_RC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK (0x2000U) #define PCIE_RC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT (13U) /*! RX_SERIALIZATION_Q_NON_EMPTY - Receive Serialization Queue Not Empty. * 0b0..Clear * 0b1..Indicates there is data in the serialization queue. */ #define PCIE_RC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT)) & PCIE_RC_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK) #define PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK (0x1FFF0000U) #define PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT (16U) /*! TIMER_MOD_FLOW_CONTROL - FC Latency Timer Override Value. */ #define PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT)) & PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK) #define PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK (0x80000000U) #define PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT (31U) /*! TIMER_MOD_FLOW_CONTROL_EN - FC Latency Timer Override Enable. * 0b0..Clear * 0b1..When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will * override the FC latency timer value that the controller calculates according to the PCIe specification. */ #define PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT)) & PCIE_RC_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK) /*! @} */ /*! @name VC_TX_ARBI_1_OFF - VC Transmit Arbitration Register 1. */ /*! @{ */ #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK (0xFFU) #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT (0U) /*! WRR_WEIGHT_VC_0 - WRR Weight for VC0. */ #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT)) & PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK) #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MASK (0xFF00U) #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SHIFT (8U) /*! WRR_WEIGHT_VC_1 - WRR Weight for VC1. */ #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SHIFT)) & PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_MASK) #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MASK (0xFF0000U) #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SHIFT (16U) /*! WRR_WEIGHT_VC_2 - WRR Weight for VC2. */ #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SHIFT)) & PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_MASK) #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MASK (0xFF000000U) #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SHIFT (24U) /*! WRR_WEIGHT_VC_3 - WRR Weight for VC3. */ #define PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SHIFT)) & PCIE_RC_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_MASK) /*! @} */ /*! @name VC_TX_ARBI_2_OFF - VC Transmit Arbitration Register 2. */ /*! @{ */ #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MASK (0xFFU) #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SHIFT (0U) /*! WRR_WEIGHT_VC_4 - WRR Weight for VC4. */ #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SHIFT)) & PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_MASK) #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MASK (0xFF00U) #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SHIFT (8U) /*! WRR_WEIGHT_VC_5 - WRR Weight for VC5. */ #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SHIFT)) & PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_MASK) #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MASK (0xFF0000U) #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SHIFT (16U) /*! WRR_WEIGHT_VC_6 - WRR Weight for VC6. */ #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SHIFT)) & PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_MASK) #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MASK (0xFF000000U) #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SHIFT (24U) /*! WRR_WEIGHT_VC_7 - WRR Weight for VC7. */ #define PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SHIFT)) & PCIE_RC_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_MASK) /*! @} */ /*! @name VC0_P_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Posted Receive Queue Control. */ /*! @{ */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK (0xFFFU) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT (0U) /*! VC0_P_DATA_CREDIT - VC0 Posted Data Credits. * 0b111111111111..Max value * 0b000000000000..Zero value */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK (0xFF000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT (12U) /*! VC0_P_HEADER_CREDIT - VC0 Posted Header Credits. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK (0x100000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT (20U) /*! RESERVED4 - Reserved. */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK (0xE00000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT (21U) /*! VC0_P_TLP_Q_MODE - Reserved. */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK (0x3000000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT (24U) /*! VC0_P_HDR_SCALE - VC0 Scale Posted Header Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK (0xC000000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT (26U) /*! VC0_P_DATA_SCALE - VC0 Scale Posted Data Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK (0x30000000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT (28U) /*! RESERVED5 - Reserved. */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK (0x40000000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT (30U) /*! TLP_TYPE_ORDERING_VC0 - TLP Type Ordering for VC0. * 0b1..PCIe ordering rules (recommended) * 0b0..Strict ordering: posted, completion, then non-posted */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK (0x80000000U) #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT (31U) /*! VC_ORDERING_RX_Q - VC Ordering for Receive Queues. * 0b0..Round robin * 0b1..Strict ordering, higher numbered VCs have higher priority */ #define PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT)) & PCIE_RC_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK) /*! @} */ /*! @name VC0_NP_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Non-Posted Receive Queue Control. */ /*! @{ */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK (0xFFFU) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT (0U) /*! VC0_NP_DATA_CREDIT - VC0 Non-Posted Data Credits. * 0b111111111111..Max value * 0b000000000000..Zero value */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT)) & PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK (0xFF000U) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT (12U) /*! VC0_NP_HEADER_CREDIT - VC0 Non-Posted Header Credits. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT)) & PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK (0x100000U) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT (20U) /*! RESERVED6 - Reserved. */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT)) & PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK (0xE00000U) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT (21U) /*! VC0_NP_TLP_Q_MODE - Reserved. */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT)) & PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK (0x3000000U) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT (24U) /*! VC0_NP_HDR_SCALE - VC0 Scale Non-Posted Header Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT)) & PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK (0xC000000U) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT (26U) /*! VC0_NP_DATA_SCALE - VC0 Scale Non-Posted Data Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT)) & PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK (0xF0000000U) #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT (28U) /*! RESERVED7 - Reserved. */ #define PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT)) & PCIE_RC_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK) /*! @} */ /*! @name VC0_CPL_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Completion Receive Queue Control. */ /*! @{ */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK (0xFFFU) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT (0U) /*! VC0_CPL_DATA_CREDIT - VC0 Completion Data Credits. * 0b111111111111..Max value * 0b000000000000..Zero value */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT)) & PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK (0xFF000U) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT (12U) /*! VC0_CPL_HEADER_CREDIT - VC0 Completion Header Credits. * 0b11111111..Max value * 0b00000000..Zero value */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT)) & PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK (0x100000U) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT (20U) /*! RESERVED8 - Reserved. */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT)) & PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK (0xE00000U) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT (21U) /*! VC0_CPL_TLP_Q_MODE - Reserved. */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT)) & PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK (0x3000000U) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT (24U) /*! VC0_CPL_HDR_SCALE - VC0 Scale CPL Header Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT)) & PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK (0xC000000U) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT (26U) /*! VC0_CPL_DATA_SCALE - VC0 Scale CPL Data Credits. * 0b11..Max value * 0b00..Zero value */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT)) & PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK (0xF0000000U) #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT (28U) /*! RESERVED9 - Reserved. */ #define PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT)) & PCIE_RC_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK) /*! @} */ /*! @name GEN2_CTRL_OFF - Link Width and Speed Change Control Register. */ /*! @{ */ #define PCIE_RC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK (0xFFU) #define PCIE_RC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT (0U) /*! FAST_TRAINING_SEQ - Sets the Number of Fast Training Sequences (N_FTS) that the controller * advertises as its N_FTS during Gen2 or Gen3 link training. */ #define PCIE_RC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK) #define PCIE_RC_GEN2_CTRL_OFF_NUM_OF_LANES_MASK (0x1F00U) #define PCIE_RC_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT (8U) /*! NUM_OF_LANES - Predetermined Number of Lanes. * 0b00001..1 lane * 0b00010..2 lanes * 0b00011..3 lanes */ #define PCIE_RC_GEN2_CTRL_OFF_NUM_OF_LANES(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_NUM_OF_LANES_MASK) #define PCIE_RC_GEN2_CTRL_OFF_PRE_DET_LANE_MASK (0xE000U) #define PCIE_RC_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT (13U) /*! PRE_DET_LANE - Predetermined Lane for Auto Flip. * 0b000..Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detected * 0b001..Connect logical Lane0 to physical lane 1 * 0b100..Connect logical Lane0 to physical lane 15 * 0b010..Connect logical Lane0 to physical lane 3 * 0b011..connect logical lane0 to physical lane 7 */ #define PCIE_RC_GEN2_CTRL_OFF_PRE_DET_LANE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_PRE_DET_LANE_MASK) #define PCIE_RC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK (0x10000U) #define PCIE_RC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT (16U) /*! AUTO_LANE_FLIP_CTRL_EN - Enable Auto flipping of the lanes. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK) #define PCIE_RC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK (0x20000U) #define PCIE_RC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT (17U) /*! DIRECT_SPEED_CHANGE - Directed Speed Change. * 0b0..Clear * 0b1..Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. */ #define PCIE_RC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK) #define PCIE_RC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK (0x40000U) #define PCIE_RC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT (18U) /*! CONFIG_PHY_TX_CHANGE - Config PHY Tx Swing. * 0b0..Full Swing * 0b1..Low Swing */ #define PCIE_RC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK) #define PCIE_RC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK (0x80000U) #define PCIE_RC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT (19U) /*! CONFIG_TX_COMP_RX - Config Tx Compliance Receive Bit. * 0b0..Clear * 0b1..When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). */ #define PCIE_RC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK) #define PCIE_RC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK (0x100000U) #define PCIE_RC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT (20U) /*! SEL_DEEMPHASIS - Used to set the de-emphasis level for upstream ports. * 0b1..-3.5 dB * 0b0..-6 dB */ #define PCIE_RC_GEN2_CTRL_OFF_SEL_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK) #define PCIE_RC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK (0x200000U) #define PCIE_RC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT (21U) /*! GEN1_EI_INFERENCE - Electrical Idle Inference Mode at Gen1 Rate. * 0b0..Use RxElecIdle signal to infer Electrical Idle * 0b1..Use RxValid signal to infer Electrical Idle */ #define PCIE_RC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK) #define PCIE_RC_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_MASK (0x400000U) #define PCIE_RC_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_SHIFT (22U) /*! SELECT_DEEMPH_VAR_MUX - The select_deemphasis variable for DSP on entry to Recovery. * 0b1..The value from the Selectable De-emphasis field in the Link Control 2 register * 0b0..The value requested by USP in Recovery.RcvrLock state through Tx TS1s from USP */ #define PCIE_RC_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_SELECT_DEEMPH_VAR_MUX_MASK) #define PCIE_RC_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_MASK (0x800000U) #define PCIE_RC_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_SHIFT (23U) /*! SELECTABLE_DEEMPH_BIT_MUX - The selectable deemphasis bit (Symbol 4 bit 6) of the transmitted TS2 Ordered Sets for DSP in Recovery. * 0b0..The value from the Selectable De-emphasis field in the Link Control 2 register * 0b1..The value requested by USP in Recovery.RcvrLock state through Tx TS1s from USP */ #define PCIE_RC_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_SELECTABLE_DEEMPH_BIT_MUX_MASK) #define PCIE_RC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MASK (0xF000000U) #define PCIE_RC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SHIFT (24U) /*! LANE_UNDER_TEST - The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. * 0b0001..CX_NL * 0b0000..Zero */ #define PCIE_RC_GEN2_CTRL_OFF_LANE_UNDER_TEST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_LANE_UNDER_TEST_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_LANE_UNDER_TEST_MASK) #define PCIE_RC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MASK (0x40000000U) #define PCIE_RC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SHIFT (30U) /*! FORCE_LANE_FLIP - Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_GEN2_CTRL_OFF_FORCE_LANE_FLIP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_SHIFT)) & PCIE_RC_GEN2_CTRL_OFF_FORCE_LANE_FLIP_MASK) /*! @} */ /*! @name PHY_STATUS_OFF - PHY Status Register. */ /*! @{ */ #define PCIE_RC_PHY_STATUS_OFF_PHY_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_PHY_STATUS_OFF_PHY_STATUS_SHIFT (0U) /*! PHY_STATUS - PHY Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_PHY_STATUS_OFF_PHY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_STATUS_OFF_PHY_STATUS_SHIFT)) & PCIE_RC_PHY_STATUS_OFF_PHY_STATUS_MASK) /*! @} */ /*! @name PHY_CONTROL_OFF - PHY Control Register. */ /*! @{ */ #define PCIE_RC_PHY_CONTROL_OFF_PHY_CONTROL_MASK (0xFFFFFFFFU) #define PCIE_RC_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT (0U) /*! PHY_CONTROL - PHY Control. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_PHY_CONTROL_OFF_PHY_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT)) & PCIE_RC_PHY_CONTROL_OFF_PHY_CONTROL_MASK) /*! @} */ /*! @name TRGT_MAP_CTRL_OFF - Programmable Target Map Control Register. */ /*! @{ */ #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK (0x3FU) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT (0U) /*! TARGET_MAP_PF - Target Values for each BAR on the PF Function selected by the index number. */ #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT)) & PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK (0x40U) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT (6U) /*! TARGET_MAP_ROM - Target Value for the ROM page of the PF Function selected by the index number. */ #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT)) & PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK (0xE000U) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT (13U) /*! TARGET_MAP_RESERVED_13_15 - Reserved. */ #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT)) & PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK (0x1F0000U) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT (16U) /*! TARGET_MAP_INDEX - The number of the PF Function on which the Target Values are set. */ #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT)) & PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK (0xFFE00000U) #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT (21U) /*! TARGET_MAP_RESERVED_21_31 - Reserved. */ #define PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT)) & PCIE_RC_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK) /*! @} */ /*! @name MSI_CTRL_ADDR_OFF - Integrated MSI Reception Module (iMRM) Address Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SHIFT (0U) /*! MSI_CTRL_ADDR - Integrated MSI Reception Module Address. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SHIFT)) & PCIE_RC_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MASK) /*! @} */ /*! @name MSI_CTRL_UPPER_ADDR_OFF - Integrated MSI Reception Module Upper Address Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SHIFT (0U) /*! MSI_CTRL_UPPER_ADDR - Integrated MSI Reception Module Upper Address. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SHIFT)) & PCIE_RC_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MASK) /*! @} */ /*! @name MSI_CTRL_INT_0_EN_OFF - Integrated MSI Reception Module Interrupt0 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SHIFT (0U) /*! MSI_CTRL_INT_0_EN - MSI Interrupt0 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_0_MASK_OFF - Integrated MSI Reception Module Interrupt0 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SHIFT (0U) /*! MSI_CTRL_INT_0_MASK - MSI Interrupt0 Mask. */ #define PCIE_RC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_0_STATUS_OFF - Integrated MSI Reception Module Interrupt0 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_0_STATUS - MSI Interrupt0 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MASK) /*! @} */ /*! @name MSI_CTRL_INT_1_EN_OFF - Integrated MSI Reception Module Interrupt1 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SHIFT (0U) /*! MSI_CTRL_INT_1_EN - MSI Interrupt1 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_1_MASK_OFF - Integrated MSI Reception Module Interrupt1 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SHIFT (0U) /*! MSI_CTRL_INT_1_MASK - MSI Interrupt1 Mask. */ #define PCIE_RC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_1_STATUS_OFF - Integrated MSI Reception Module Interrupt1 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_1_STATUS - MSI Interrupt1 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MASK) /*! @} */ /*! @name MSI_CTRL_INT_2_EN_OFF - Integrated MSI Reception Module Interrupt2 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SHIFT (0U) /*! MSI_CTRL_INT_2_EN - MSI Interrupt2 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_2_MASK_OFF - Integrated MSI Reception Module Interrupt2 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SHIFT (0U) /*! MSI_CTRL_INT_2_MASK - MSI Interrupt2 Mask. */ #define PCIE_RC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_2_STATUS_OFF - Integrated MSI Reception Module Interrupt2 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_2_STATUS - MSI Interrupt2 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MASK) /*! @} */ /*! @name MSI_CTRL_INT_3_EN_OFF - Integrated MSI Reception Module Interrupt3 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SHIFT (0U) /*! MSI_CTRL_INT_3_EN - MSI Interrupt3 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_3_MASK_OFF - Integrated MSI Reception Module Interrupt3 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SHIFT (0U) /*! MSI_CTRL_INT_3_MASK - MSI Interrupt3 Mask. */ #define PCIE_RC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_3_STATUS_OFF - Integrated MSI Reception Module Interrupt3 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_3_STATUS - MSI Interrupt3 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MASK) /*! @} */ /*! @name MSI_CTRL_INT_4_EN_OFF - Integrated MSI Reception Module Interrupt4 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SHIFT (0U) /*! MSI_CTRL_INT_4_EN - MSI Interrupt4 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_4_MASK_OFF - Integrated MSI Reception Module Interrupt4 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SHIFT (0U) /*! MSI_CTRL_INT_4_MASK - MSI Interrupt4 Mask. */ #define PCIE_RC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_4_STATUS_OFF - Integrated MSI Reception Module Interrupt4 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_4_STATUS - MSI Interrupt4 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MASK) /*! @} */ /*! @name MSI_CTRL_INT_5_EN_OFF - Integrated MSI Reception Module Interrupt5 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SHIFT (0U) /*! MSI_CTRL_INT_5_EN - MSI Interrupt5 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_5_MASK_OFF - Integrated MSI Reception Module Interrupt5 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SHIFT (0U) /*! MSI_CTRL_INT_5_MASK - MSI Interrupt5 Mask. */ #define PCIE_RC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_5_STATUS_OFF - Integrated MSI Reception Module Interrupt5 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_5_STATUS - MSI Interrupt5 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MASK) /*! @} */ /*! @name MSI_CTRL_INT_6_EN_OFF - Integrated MSI Reception Module Interrupt6 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SHIFT (0U) /*! MSI_CTRL_INT_6_EN - MSI Interrupt6 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_6_MASK_OFF - Integrated MSI Reception Module Interrupt6 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SHIFT (0U) /*! MSI_CTRL_INT_6_MASK - MSI Interrupt6 Mask. */ #define PCIE_RC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_6_STATUS_OFF - Integrated MSI Reception Module Interrupt6 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_6_STATUS - MSI Interrupt6 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MASK) /*! @} */ /*! @name MSI_CTRL_INT_7_EN_OFF - Integrated MSI Reception Module Interrupt7 Enable Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SHIFT (0U) /*! MSI_CTRL_INT_7_EN - MSI Interrupt7 Enable. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SHIFT)) & PCIE_RC_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MASK) /*! @} */ /*! @name MSI_CTRL_INT_7_MASK_OFF - Integrated MSI Reception Module Interrupt7 Mask Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SHIFT (0U) /*! MSI_CTRL_INT_7_MASK - MSI Interrupt7 Mask. */ #define PCIE_RC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SHIFT)) & PCIE_RC_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MASK) /*! @} */ /*! @name MSI_CTRL_INT_7_STATUS_OFF - Integrated MSI Reception Module Interrupt7 Status Register. */ /*! @{ */ #define PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SHIFT (0U) /*! MSI_CTRL_INT_7_STATUS - MSI Interrupt7 Status. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SHIFT)) & PCIE_RC_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MASK) /*! @} */ /*! @name MSI_GPIO_IO_OFF - Integrated MSI Reception Module General Purpose IO Register. */ /*! @{ */ #define PCIE_RC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MASK (0xFFFFFFFFU) #define PCIE_RC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SHIFT (0U) /*! MSI_GPIO_REG - MSI GPIO Register. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_MSI_GPIO_IO_OFF_MSI_GPIO_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SHIFT)) & PCIE_RC_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MASK) /*! @} */ /*! @name CLOCK_GATING_CTRL_OFF - Clock Gating Control Register. */ /*! @{ */ #define PCIE_RC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK (0x1U) #define PCIE_RC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT (0U) /*! RADM_CLK_GATING_EN - RADM Clock Gating Enable. * 0b0..Disable * 0b1..Enable (default) */ #define PCIE_RC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT)) & PCIE_RC_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK) #define PCIE_RC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MASK (0x2U) #define PCIE_RC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SHIFT (1U) /*! AXI_CLK_GATING_EN - AXI Clock Gating Enable. * 0b0..Disable * 0b1..Enable (default) */ #define PCIE_RC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_SHIFT)) & PCIE_RC_CLOCK_GATING_CTRL_OFF_AXI_CLK_GATING_EN_MASK) /*! @} */ /*! @name GEN3_RELATED_OFF - Gen3 Control Register. */ /*! @{ */ #define PCIE_RC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MASK (0x1U) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SHIFT (0U) /*! GEN3_ZRXDC_NONCOMPL - Gen3 Receiver Impedance ZRX-DC Not Compliant. * 0b0..The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. * 0b1..The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. */ #define PCIE_RC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_MASK) #define PCIE_RC_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_MASK (0x2U) #define PCIE_RC_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_SHIFT (1U) /*! NO_SEED_VALUE_CHANGE - If this bit is set to 1, the seed value of LFSR for scrambler at Gen3 rate does not change after LinkUp = 1. * 0b1..Not Change */ #define PCIE_RC_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_NO_SEED_VALUE_CHANGE_MASK) #define PCIE_RC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MASK (0x100U) #define PCIE_RC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SHIFT (8U) /*! DISABLE_SCRAMBLER_GEN_3 - Disable Scrambler for Gen3 and Gen4 Data Rate. */ #define PCIE_RC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_MASK) #define PCIE_RC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MASK (0x200U) #define PCIE_RC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SHIFT (9U) /*! EQ_PHASE_2_3 - Equalization Phase 2 and Phase 3 Disable. * 0b0..Rx equalization in phase 0/1 * 0b1..No Rx equalization */ #define PCIE_RC_GEN3_RELATED_OFF_EQ_PHASE_2_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_EQ_PHASE_2_3_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_EQ_PHASE_2_3_MASK) #define PCIE_RC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MASK (0x400U) #define PCIE_RC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SHIFT (10U) /*! EQ_EIEOS_CNT - Equalization EIEOS Count Reset Disable. * 0b1..Disable */ #define PCIE_RC_GEN3_RELATED_OFF_EQ_EIEOS_CNT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_EQ_EIEOS_CNT_MASK) #define PCIE_RC_GEN3_RELATED_OFF_EQ_REDO_MASK (0x800U) #define PCIE_RC_GEN3_RELATED_OFF_EQ_REDO_SHIFT (11U) /*! EQ_REDO - Equalization Redo Disable. */ #define PCIE_RC_GEN3_RELATED_OFF_EQ_REDO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_EQ_REDO_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_EQ_REDO_MASK) #define PCIE_RC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MASK (0x1000U) #define PCIE_RC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SHIFT (12U) /*! RXEQ_PH01_EN - Rx Equalization Phase 0/Phase 1 Hold Enable. * 0b1..No Tx equalization * 0b0..Tx equalization only in phase 2/3 */ #define PCIE_RC_GEN3_RELATED_OFF_RXEQ_PH01_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_RXEQ_PH01_EN_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_RXEQ_PH01_EN_MASK) #define PCIE_RC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MASK (0x2000U) #define PCIE_RC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SHIFT (13U) /*! RXEQ_RGRDLESS_RXTS - RXEQ_RGRDLESS_RXTS * 0b0..mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. * 0b1..mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not. */ #define PCIE_RC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_MASK) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MASK (0x10000U) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SHIFT (16U) /*! GEN3_EQUALIZATION_DISABLE - Equalization Disable. */ #define PCIE_RC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_MASK) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MASK (0x20000U) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SHIFT (17U) /*! GEN3_DLLP_XMT_DELAY_DISABLE - DLLP Transmission Delay Disable. */ #define PCIE_RC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_MASK) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MASK (0x40000U) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SHIFT (18U) /*! GEN3_DC_BALANCE_DISABLE - DC Balance Disable. */ #define PCIE_RC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_MASK) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MASK (0x800000U) #define PCIE_RC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SHIFT (23U) /*! GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE - Eq InvalidRequest and RxEqEval Different Time Assertion Disable. */ #define PCIE_RC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_SHIFT)) & PCIE_RC_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_MASK) /*! @} */ /*! @name GEN3_EQ_CONTROL_OFF - Gen3 EQ Control Register. */ /*! @{ */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MASK (0xFU) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SHIFT (0U) /*! GEN3_EQ_FB_MODE - Feedback Mode. * 0b0000..Direction Change * 0b0001..Figure Of Merit */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MASK (0x10U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SHIFT (4U) /*! GEN3_EQ_PHASE23_EXIT_MODE - Behavior After 24 ms Timeout (when optimal settings are not found). * 0b1..USP: Recovery.Equalization.Phase3; DSP: Recovery.Equalization.RcvrLock * 0b0..Recovery.Speed */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MASK (0x20U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SHIFT (5U) /*! GEN3_EQ_EVAL_2MS_DISABLE - Phase2_3 2 ms Timeout Disable. * 0b0..Abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout * 0b1..Ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to * respond to the assertion of RxEqEval. */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MASK (0x40U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SHIFT (6U) /*! GEN3_LOWER_RATE_EQ_REDO_ENABLE - Support EQ redo and lower rate change. * 0b0..Not supported * 0b1..Supported */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_LOWER_RATE_EQ_REDO_ENABLE_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MASK (0xFFFF00U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SHIFT (8U) /*! GEN3_EQ_PSET_REQ_VEC - Preset Request Vector. * 0b1111111111111111..Max value * 0b0000000000000000..Zero value */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MASK (0x1000000U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SHIFT (24U) /*! GEN3_EQ_FOM_INC_INITIAL_EVAL - Include Initial FOM. * 0b0..Do not include * 0b1..Include */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MASK (0x2000000U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SHIFT (25U) /*! GEN3_EQ_PSET_REQ_AS_COEF - GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MASK (0x4000000U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SHIFT (26U) /*! GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP - Request controller to send back-to-back EIEOS in Recovery. * 0b0..Do not request * 0b1..Request */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_MASK (0x38000000U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_SHIFT (27U) /*! GEN3_EQ_REQ_NUM - The number of back-to-back equalization redo requests at a given Gen3, Gen4 and Gen5 data rate for USP. * 0b111..Max value * 0b000..Min value */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_EQ_REQ_NUM_MASK) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_MASK (0x40000000U) #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_SHIFT (30U) /*! GEN3_SUPPORT_FINITE_EQ_REQUEST - Support finite EQ requests for USP. * 0b1..Support * 0b0..Do not support */ #define PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_SHIFT)) & PCIE_RC_GEN3_EQ_CONTROL_OFF_GEN3_SUPPORT_FINITE_EQ_REQUEST_MASK) /*! @} */ /*! @name GEN3_EQ_FB_MODE_DIR_CHANGE_OFF - Gen3 EQ Direction Change Feedback Mode Control Register. */ /*! @{ */ #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MASK (0x1FU) #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SHIFT (0U) /*! GEN3_EQ_FMDC_T_MIN_PHASE23 - Minimum Time (in ms) To Remain in EQ Master Phase. * 0b11000..Max value * 0b00000..Min value */ #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_SHIFT)) & PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_MASK) #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MASK (0x3E0U) #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SHIFT (5U) /*! GEN3_EQ_FMDC_N_EVALS - Convergence Window Depth. * 0b11111..Maximum of CX_GEN3_EQ_COEFQ_DEPTH * 0b00000..Min value */ #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_SHIFT)) & PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_MASK) #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MASK (0x3C00U) #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SHIFT (10U) /*! GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA - Convergence Window Aperture for C-1. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_SHIFT)) & PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_MASK) #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MASK (0x3C000U) #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SHIFT (14U) /*! GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA - Convergence Window Aperture for C+1. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_SHIFT)) & PCIE_RC_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_MASK) /*! @} */ /*! @name ORDER_RULE_CTRL_OFF - Order Rule Control Register. */ /*! @{ */ #define PCIE_RC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK (0xFFU) #define PCIE_RC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT (0U) /*! NP_PASS_P - Non-Posted Passing Posted Ordering Rule Control. * 0b00000000..NP can not pass P (recommended). * 0b00000001..NP can pass P */ #define PCIE_RC_ORDER_RULE_CTRL_OFF_NP_PASS_P(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT)) & PCIE_RC_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK) #define PCIE_RC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK (0xFF00U) #define PCIE_RC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT (8U) /*! CPL_PASS_P - Completion Passing Posted Ordering Rule Control. * 0b00000000..CPL can not pass P (recommended) * 0b00000001..CPL can pass P */ #define PCIE_RC_ORDER_RULE_CTRL_OFF_CPL_PASS_P(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT)) & PCIE_RC_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK) /*! @} */ /*! @name PIPE_LOOPBACK_CONTROL_OFF - PIPE Loopback Control Register. */ /*! @{ */ #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK (0xFFFFU) #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT (0U) /*! LPBK_RXVALID - LPBK_RXVALID is an internally reserved field. */ #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT)) & PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK) #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK (0x3F0000U) #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT (16U) /*! RXSTATUS_LANE - RXSTATUS_LANE is an internally reserved field. */ #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT)) & PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK) #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK (0x7000000U) #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT (24U) /*! RXSTATUS_VALUE - RXSTATUS_VALUE is an internally reserved field. */ #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT)) & PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK) #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK (0x80000000U) #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT (31U) /*! PIPE_LOOPBACK - PIPE Loopback Enable. */ #define PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT)) & PCIE_RC_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK) /*! @} */ /*! @name MISC_CONTROL_1_OFF - DBI Read-Only Write Enable Register. */ /*! @{ */ #define PCIE_RC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK (0x1U) #define PCIE_RC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT (0U) /*! DBI_RO_WR_EN - Write to RO Registers Using DBI. * 0b0..Clear * 0b1..Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. */ #define PCIE_RC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK (0x2U) #define PCIE_RC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT (1U) /*! DEFAULT_TARGET - Default target for an IO or MEM request with UR/CA/CRS received. * 0b0..The controller drops all incoming I/O or MEM requests (after corresponding error reporting). A completion * with UR status is generated for non-posted requests. * 0b1..The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application. */ #define PCIE_RC_MISC_CONTROL_1_OFF_DEFAULT_TARGET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK (0x4U) #define PCIE_RC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT (2U) /*! UR_CA_MASK_4_TRGT1 - UR_CA_MASK_4_TRGT1 * 0b0..Clear * 0b1..Set */ #define PCIE_RC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK (0x8U) #define PCIE_RC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT (3U) /*! SIMPLIFIED_REPLAY_TIMER - Enables Simplified Replay Timer (Gen4). * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MASK (0x10U) #define PCIE_RC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SHIFT (4U) /*! DISABLE_AUTO_LTR_CLR_MSG - Disable the autonomous generation of LTR clear message in upstream port. * 0b0..Allow the autonomous generation of LTR clear message. * 0b1..Disable the autonomous generation of LTR clear message. */ #define PCIE_RC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_DISABLE_AUTO_LTR_CLR_MSG_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK (0x20U) #define PCIE_RC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT (5U) /*! ARI_DEVICE_NUMBER - When ARI is enabled, this field enables use of the device ID. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MASK (0x40U) #define PCIE_RC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SHIFT (6U) /*! CPLQ_MNG_EN - This field enables the Completion Queue Management feature. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_CPLQ_MNG_EN_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MASK (0x80U) #define PCIE_RC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SHIFT (7U) /*! CFG_TLP_BYPASS_EN_REG - Setting of this field defines how to decide the destination of Configuration requests. * 0b1..Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG, regardless the value of CONFIG_LIMIT_REG. * 0b0..Configuration TLPs are routed according to the setting of TARGET_ABOVE_CONFIG_LIMIT_REG, depending on the * setting of CONFIG_LIMIT_REG. Refer to the definition of CONFIG_LIMIT_REG for details. */ #define PCIE_RC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_CFG_TLP_BYPASS_EN_REG_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MASK (0x3FF00U) #define PCIE_RC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SHIFT (8U) /*! CONFIG_LIMIT_REG - Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. */ #define PCIE_RC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_CONFIG_LIMIT_REG_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MASK (0xC0000U) #define PCIE_RC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SHIFT (18U) /*! TARGET_ABOVE_CONFIG_LIMIT_REG - TARGET_ABOVE_CONFIG_LIMIT_REG * 0b01..ELBI * 0b10..TRGT1 */ #define PCIE_RC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_TARGET_ABOVE_CONFIG_LIMIT_REG_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MASK (0x100000U) #define PCIE_RC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SHIFT (20U) /*! P2P_TRACK_CPL_TO_REG - Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. * 0b0..Do not track completion * 0b1..Track completion */ #define PCIE_RC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_P2P_TRACK_CPL_TO_REG_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MASK (0x200000U) #define PCIE_RC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SHIFT (21U) /*! P2P_ERR_RPT_CTRL - Determines whether to enable Peer to Peer (P2P) error reporting. * 0b0..Disable P2P error reporting * 0b1..Enable P2P error reporting */ #define PCIE_RC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_P2P_ERR_RPT_CTRL_MASK) #define PCIE_RC_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_MASK (0x400000U) #define PCIE_RC_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_SHIFT (22U) /*! PORT_LOGIC_WR_DISABLE - Disable port logic register write from wire side. */ #define PCIE_RC_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_SHIFT)) & PCIE_RC_MISC_CONTROL_1_OFF_PORT_LOGIC_WR_DISABLE_MASK) /*! @} */ /*! @name MULTI_LANE_CONTROL_OFF - UpConfigure Multi-lane Control Register. */ /*! @{ */ #define PCIE_RC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK (0x3FU) #define PCIE_RC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT (0U) /*! TARGET_LINK_WIDTH - Target Link Width. * 0b000000..Controller does not start upconfigure or autonomous width downsizing in the Configuration state. * 0b000001..x1 * 0b010000..x16 * 0b000010..x2 * 0b100000..x32 * 0b000100..x4 * 0b001000..x8 */ #define PCIE_RC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT)) & PCIE_RC_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK) #define PCIE_RC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK (0x40U) #define PCIE_RC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT (6U) /*! DIRECT_LINK_WIDTH_CHANGE - Directed Link Width Change. * 0b0..Clear * 0b1..The controller always moves to Configuration state through Recovery state when this bit is set to '1'. */ #define PCIE_RC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT)) & PCIE_RC_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK) #define PCIE_RC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK (0x80U) #define PCIE_RC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT (7U) /*! UPCONFIGURE_SUPPORT - Upconfigure Support. */ #define PCIE_RC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT)) & PCIE_RC_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK) /*! @} */ /*! @name PHY_INTEROP_CTRL_OFF - PHY Interoperability Control Register. */ /*! @{ */ #define PCIE_RC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK (0x7FU) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT (0U) /*! RXSTANDBY_CONTROL - Rxstandby Control. * 0b1111111..Max value * 0b0000000..Zero value */ #define PCIE_RC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK (0x100U) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT (8U) /*! L1SUB_EXIT_MODE - L1 Exit Control Using phy_mac_pclkack_n. * 0b1..Controller exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. * 0b0..Controller waits for the PHY to assert phy_mac_pclkack_n before exiting L1. */ #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK (0x200U) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT (9U) /*! L1_NOWAIT_P1 - L1 entry control bit. * 0b1..Controller does not wait for PHY to acknowledge transition to P1 before entering L1. * 0b0..Controller waits for the PHY to acknowledge transition to P1 before entering L1. */ #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK (0x400U) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT (10U) /*! L1_CLK_SEL - L1 Clock control bit. * 0b0..Controller requests aux_clk switch and core_clk gating in L1. * 0b1..Controller does not request aux_clk switch and core_clk gating in L1. */ #define PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_MASK (0x3FFFF000U) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_SHIFT (12U) /*! PHY_RST_TIMER - Control the duration of the PHY reset (PIPE and PMA). * 0b111111111111111111..Max value. * 0b000000000000000000..Zero value. */ #define PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_RST_TIMER_MASK) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_MASK (0x40000000U) #define PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_SHIFT (30U) /*! PHY_PERST_ON_WARM_RESET - Control whether the Power Management Controller will drive * pm_req_phy_perst during a Warm Reset (PERST# assertion without cycling of power). * 0b0..DO NOT Drive pm_req_phy_perst during a Warm Reset. * 0b1..Drive pm_req_phy_perst during a Warm Reset. */ #define PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_OFF_PHY_PERST_ON_WARM_RESET_MASK) /*! @} */ /*! @name TRGT_CPL_LUT_DELETE_ENTRY_OFF - TRGT_CPL_LUT Delete Entry Control register. */ /*! @{ */ #define PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK (0x7FFFFFFFU) #define PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT (0U) /*! LOOK_UP_ID - This number selects one entry to delete of the TRGT_CPL_LUT. */ #define PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT)) & PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK) #define PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK (0x80000000U) #define PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT (31U) /*! DELETE_EN - This is a one-shot bit. * 0b0..Clear * 0b1..A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. */ #define PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT)) & PCIE_RC_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK) /*! @} */ /*! @name LINK_FLUSH_CONTROL_OFF - Link Reset Request Flush Control Register. */ /*! @{ */ #define PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK (0x1U) #define PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT (0U) /*! AUTO_FLUSH_EN - AUTO_FLUSH_EN * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT)) & PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK) #define PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_MASK (0xFF000000U) #define PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_SHIFT (24U) /*! AUTO_FLUSH_TIMEOUT - Timeout Value (ms) for automatic flushing. */ #define PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_SHIFT)) & PCIE_RC_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_TIMEOUT_MASK) /*! @} */ /*! @name AMBA_ERROR_RESPONSE_DEFAULT_OFF - AXI Bridge Slave Error Response Register. */ /*! @{ */ #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK (0x1U) #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT (0U) /*! AMBA_ERROR_RESPONSE_GLOBAL - Global Slave Error Response Mapping. * 0b1..SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping) * 0b0..OKAY (with FFFF data for non-posted requests) */ #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT)) & PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK) #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK (0x4U) #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT (2U) /*! AMBA_ERROR_RESPONSE_VENDORID - Vendor ID Non-existent Slave Error Response Mapping. * 0b1..SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping) * 0b0..OKAY (with FFFF data). */ #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT)) & PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK) #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK (0x18U) #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT (3U) /*! AMBA_ERROR_RESPONSE_CRS - CRS Slave Error Response Mapping. * 0b00..OKAY * 0b01..OKAY with all FFFF_FFFF data for all CRS completions * 0b10..OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY with FFFF_FFFF data for all other CRS completions * 0b11..SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error response mapping) */ #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT)) & PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK) #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK (0xFC00U) #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT (10U) /*! AMBA_ERROR_RESPONSE_MAP - AXI Slave Response Error Map. * 0b111111..Max value * 0b000000..Zero value */ #define PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT)) & PCIE_RC_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK) /*! @} */ /*! @name AMBA_LINK_TIMEOUT_OFF - Link Down AXI Bridge Slave Timeout Register. */ /*! @{ */ #define PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK (0xFFU) #define PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT (0U) /*! LINK_TIMEOUT_PERIOD_DEFAULT - Timeout Value (ms). */ #define PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT)) & PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK) #define PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK (0x100U) #define PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT (8U) /*! LINK_TIMEOUT_ENABLE_DEFAULT - Disable Flush. * 0b1..You can disable the flush feature by setting this field to '1'. * 0b0..Enable */ #define PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT)) & PCIE_RC_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK) /*! @} */ /*! @name AMBA_ORDERING_CTRL_OFF - AXI Bridge Ordering Control. */ /*! @{ */ #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK (0x2U) #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT (1U) /*! AX_SNP_EN - AXI Serialize Non-Posted Requests Enable. * 0b0..Disable * 0b1..Enable */ #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT)) & PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK) #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK (0x18U) #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT (3U) /*! AX_MSTR_ORDR_P_EVENT_SEL - AXI Master Posted Ordering Event Selector. * 0b01..AW'last event: wait until the complete Posted transaction has left the AXI address channel at the bridge master. * 0b00..B'last event: wait for all of the write responses on the B channel thereby ensuring that the complete * Posted transaction has effectively reached the application slave (default). * 0b11..Reserved * 0b10..W'last event: wait until the complete Posted transaction has left the AXI data channel at the bridge master. */ #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT)) & PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK) #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK (0x80U) #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT (7U) /*! AX_MSTR_ZEROLREAD_FW - AXI Master Zero Length Read Forward to the application. * 0b1..The zero length Read is forward to the application. * 0b0..The zero length Read is terminated at the DW PCIe AXI bridge master */ #define PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT)) & PCIE_RC_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK) /*! @} */ /*! @name COHERENCY_CONTROL_1_OFF - Cache Coherency Control Register 1. */ /*! @{ */ #define PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MASK (0x1U) #define PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SHIFT (0U) /*! CFG_MEMTYPE_VALUE - Sets the memory type for the lower and upper parts of the address space: * 0b1..lower = Memory type; upper = Peripheral * 0b0..lower = Peripheral; upper = Memory */ #define PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_VALUE_MASK) #define PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK (0xFFFFFFFCU) #define PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SHIFT (2U) /*! CFG_MEMTYPE_BOUNDARY_LOW_ADDR - Boundary Lower Address For Memory Type. */ #define PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_1_OFF_CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK) /*! @} */ /*! @name COHERENCY_CONTROL_2_OFF - Cache Coherency Control Register 2. */ /*! @{ */ #define PCIE_RC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MASK (0xFFFFFFFFU) #define PCIE_RC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SHIFT (0U) /*! CFG_MEMTYPE_BOUNDARY_HIGH_ADDR - Boundary Upper Address For Memory Type. */ #define PCIE_RC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_2_OFF_CFG_MEMTYPE_BOUNDARY_HIGH_ADDR_MASK) /*! @} */ /*! @name COHERENCY_CONTROL_3_OFF - Cache Coherency Control Register 3. */ /*! @{ */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_MASK (0x3U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_SHIFT (0U) /*! CFG_MSTR_ARDOMAIN_MODE - Master Read DOMAIN Signal Behavior. * 0b00..set automatically by the AXI master * 0b01..set the value of the corresponding bit of the CFG_MSTR_ARDOMAIN_VALUE field */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_MODE_MASK) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MASK (0x78U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SHIFT (3U) /*! CFG_MSTR_ARCACHE_MODE - Master Read CACHE Signal Behavior. * 0b0000..set automatically by the AXI master * 0b0001..set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_MODE_MASK) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_MASK (0x300U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_SHIFT (8U) /*! CFG_MSTR_AWDOMAIN_MODE - Master Write DOMAIN Signal Behavior. * 0b00..set automatically by the AXI master * 0b01..set by the value of the corresponding bit of the CFG_MSTR_AWDOMAIN_VALUE field */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_MODE_MASK) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MASK (0x7800U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SHIFT (11U) /*! CFG_MSTR_AWCACHE_MODE - Master Write CACHE Signal Behavior. * 0b0000..set automatically by the AXI master * 0b0001..set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_MODE_MASK) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_MASK (0x30000U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_SHIFT (16U) /*! CFG_MSTR_ARDOMAIN_VALUE - Master Read DOMAIN Signal Value. */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARDOMAIN_VALUE_MASK) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MASK (0x780000U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SHIFT (19U) /*! CFG_MSTR_ARCACHE_VALUE - Master Read CACHE Signal Value. */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_ARCACHE_VALUE_MASK) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_MASK (0x3000000U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_SHIFT (24U) /*! CFG_MSTR_AWDOMAIN_VALUE - Master Write DOMAIN Signal Value. */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWDOMAIN_VALUE_MASK) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MASK (0x78000000U) #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SHIFT (27U) /*! CFG_MSTR_AWCACHE_VALUE - Master Write CACHE Signal Value. */ #define PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_SHIFT)) & PCIE_RC_COHERENCY_CONTROL_3_OFF_CFG_MSTR_AWCACHE_VALUE_MASK) /*! @} */ /*! @name AXI_MSTR_MSG_ADDR_LOW_OFF - Lower 32-bits of the Programmable AXI Address. */ /*! @{ */ #define PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK (0xFFFU) #define PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT (0U) /*! CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED - Reserved for future use. */ #define PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT)) & PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK) #define PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK (0xFFFFF000U) #define PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT (12U) /*! CFG_AXIMSTR_MSG_ADDR_LOW - Lower 20-bits of the programmable AXI address for Messages. */ #define PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT)) & PCIE_RC_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK) /*! @} */ /*! @name AXI_MSTR_MSG_ADDR_HIGH_OFF - Upper 32-bits of the Programmable AXI Address. */ /*! @{ */ #define PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK (0xFFFFFFFFU) #define PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT (0U) /*! CFG_AXIMSTR_MSG_ADDR_HIGH - Upper 32 bits of the programmable AXI address for Messages. */ #define PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT)) & PCIE_RC_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK) /*! @} */ /*! @name PCIE_VERSION_NUMBER_OFF - PCIe Controller IIP Release Version Number. */ /*! @{ */ #define PCIE_RC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK (0xFFFFFFFFU) #define PCIE_RC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT (0U) /*! VERSION_NUMBER - Version Number. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT)) & PCIE_RC_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK) /*! @} */ /*! @name PCIE_VERSION_TYPE_OFF - PCIe Controller IIP Release Version Type. */ /*! @{ */ #define PCIE_RC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK (0xFFFFFFFFU) #define PCIE_RC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT (0U) /*! VERSION_TYPE - Version Type. * 0b11111111111111111111111111111111..Max value * 0b00000000000000000000000000000000..Zero value */ #define PCIE_RC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT)) & PCIE_RC_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK) /*! @} */ /*! @name PL_APP_BUS_DEV_NUM_STATUS_OFF - Application driven bus and device number register. */ /*! @{ */ #define PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_MASK (0xF8U) #define PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_SHIFT (3U) /*! RC_DSW_DEV_NUM - This field reflects the value of device number driven on app_device_num input signal by your application. */ #define PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_SHIFT)) & PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_DEV_NUM_MASK) #define PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_MASK (0xFF00U) #define PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_SHIFT (8U) /*! RC_DSW_BUS_NUM - This field reflects the value of bus number driven on app_bus_num input signal by your application. */ #define PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_SHIFT)) & PCIE_RC_PL_APP_BUS_DEV_NUM_STATUS_OFF_RC_DSW_BUS_NUM_MASK) /*! @} */ /*! @name PCIPM_TRAFFIC_CTRL_OFF - TLP Traffic during Non-D0 State Control Register. */ /*! @{ */ #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_MASK (0x1U) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_SHIFT (0U) /*! PCIPM_VDM_TRAFFIC_BLOCKED - This field indicates that VDM Message TLPs are blocked during non-D0 states. */ #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_SHIFT)) & PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_VDM_TRAFFIC_BLOCKED_MASK) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_MASK (0x2U) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_SHIFT (1U) /*! PCIPM_NEW_TLP_CLIENT0_BLOCKED - This field indicates that all TLPs transmitted by Client 0 interface are blocked during non-D0 states. */ #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_SHIFT)) & PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT0_BLOCKED_MASK) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_MASK (0x4U) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_SHIFT (2U) /*! PCIPM_NEW_TLP_CLIENT1_BLOCKED - This field indicates that all TLPs transmitted by Client 1 interface are blocked during non-D0 states. */ #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_SHIFT)) & PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT1_BLOCKED_MASK) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_MASK (0x8U) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_SHIFT (3U) /*! PCIPM_NEW_TLP_CLIENT2_BLOCKED - This field indicates that all TLPs transmitted by Client 2 interface are blocked during non-D0 states. */ #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_SHIFT)) & PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_NEW_TLP_CLIENT2_BLOCKED_MASK) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_MASK (0xF0U) #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_SHIFT (4U) /*! PCIPM_RESERVED_4_7 - Reserved. */ #define PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_SHIFT)) & PCIE_RC_PCIPM_TRAFFIC_CTRL_OFF_PCIPM_RESERVED_4_7_MASK) /*! @} */ /*! @name PL_LTR_LATENCY_OFF - LTR Latency Register. */ /*! @{ */ #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MASK (0x3FFU) #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SHIFT (0U) /*! SNOOP_LATENCY_VALUE - Snoop Latency Value. */ #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SHIFT)) & PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_MASK) #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MASK (0x1C00U) #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SHIFT (10U) /*! SNOOP_LATENCY_SCALE - Snoop Latency Scale. */ #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SHIFT)) & PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_MASK) #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MASK (0x8000U) #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SHIFT (15U) /*! SNOOP_LATENCY_REQUIRE - Snoop Latency Requirement. */ #define PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SHIFT)) & PCIE_RC_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_MASK) #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MASK (0x3FF0000U) #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SHIFT (16U) /*! NO_SNOOP_LATENCY_VALUE - No Snoop Latency Value. */ #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SHIFT)) & PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_MASK) #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MASK (0x1C000000U) #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SHIFT (26U) /*! NO_SNOOP_LATENCY_SCALE - No Snoop Latency Scale. */ #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SHIFT)) & PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_MASK) #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MASK (0x80000000U) #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SHIFT (31U) /*! NO_SNOOP_LATENCY_REQUIRE - No Snoop Latency Requirement. */ #define PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SHIFT)) & PCIE_RC_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_MASK) /*! @} */ /*! @name AUX_CLK_FREQ_OFF - Auxiliary Clock Frequency Control Register. */ /*! @{ */ #define PCIE_RC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK (0x3FFU) #define PCIE_RC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT (0U) /*! AUX_CLK_FREQ - The aux_clk frequency in MHz. */ #define PCIE_RC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT)) & PCIE_RC_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK) /*! @} */ /*! @name L1_SUBSTATES_OFF - L1 Substates Timing Register. */ /*! @{ */ #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK (0x3U) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT (0U) /*! L1SUB_T_POWER_OFF - Duration (in 1us units) of L1. * 0b11..Max value * 0b00..Min value */ #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT)) & PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK (0x3CU) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT (2U) /*! L1SUB_T_L1_2 - Duration (in 1us units) of L1. * 0b1111..Max value * 0b0000..Min value */ #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_L1_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT)) & PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_MASK (0xC0U) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_SHIFT (6U) /*! L1SUB_T_PCLKACK_LOW - Lower 2-bits of L1SUB_T_PCLKACK. * 0b11..Max value * 0b00..Min value */ #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_SHIFT)) & PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_LOW_MASK) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MASK (0x100U) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SHIFT (8U) /*! L1SUB_LOW_POWER_CLOCK_SWITCH_MODE - L1SUB_LOW_POWER_CLOCK_SWITCH_MODE * 0b0..The reference clock may be gated off when CLKREQ# is de-asserted. * 0b1..The reference clock shall be kept running regardless of the CLKREQ# setting. */ #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_SHIFT)) & PCIE_RC_L1_SUBSTATES_OFF_L1SUB_LOW_POWER_CLOCK_SWITCH_MODE_MASK) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_MASK (0x3E00U) #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_SHIFT (9U) /*! L1SUB_T_PCLKACK_HIGH - Higher 5-bits of L1SUB_T_PCLKACK. * 0b11111..Max value * 0b00000..Min value */ #define PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_SHIFT)) & PCIE_RC_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_HIGH_MASK) /*! @} */ /*! @name POWERDOWN_CTRL_STATUS_OFF - Powerdown Control and Status Register. */ /*! @{ */ #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MASK (0x1U) #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SHIFT (0U) /*! POWERDOWN_FORCE - This field is a one shot field. * 0b0..Clear * 0b1..Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake * regardless of whether the PHY has returned Phystatus. */ #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_SHIFT)) & PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_FORCE_MASK) #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_MASK (0x2U) #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_SHIFT (1U) /*! POWERDOWN_VMAIN_ACK - Set this bit to 1 if you do not want to perform the handshake with the power-switch after PERST# assertion. * 0b0..Clear * 0b1..If you do not want to perform the handshake with the power-switch after PERST# assertion. */ #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_SHIFT)) & PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_VMAIN_ACK_MASK) #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MASK (0xF0U) #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SHIFT (4U) /*! POWERDOWN_MAC_POWERDOWN - This field represents the Powerdown value driven by the controller to the PHY. */ #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_SHIFT)) & PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_MAC_POWERDOWN_MASK) #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MASK (0xF00U) #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SHIFT (8U) /*! POWERDOWN_PHY_POWERDOWN - This field represents the Powerdown value that has been acknowledged by the PHY. */ #define PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_SHIFT)) & PCIE_RC_POWERDOWN_CTRL_STATUS_OFF_POWERDOWN_PHY_POWERDOWN_MASK) /*! @} */ /*! @name PHY_INTEROP_CTRL_2_OFF - PHY Interoperability Control 2 Register. */ /*! @{ */ #define PCIE_RC_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_MASK (0x3FU) #define PCIE_RC_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_SHIFT (0U) /*! PMA_PIPE_RST_DELAY_TIMER - Control how long the controller should wait to release a PIPE reset * (pm_req_phy_rst) after releasing a PMA reset (pm_req_phy_perst). * 0b111111..Max value. * 0b001010..Min value. */ #define PCIE_RC_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_2_OFF_PMA_PIPE_RST_DELAY_TIMER_MASK) #define PCIE_RC_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_MASK (0xF00U) #define PCIE_RC_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_SHIFT (8U) /*! DSP_PCIPM_L1_ENTER_DELAY - DSP_PCIPM_L1_ENTER_DELAY * 0b1111..Max value. * 0b0000..Zero value. */ #define PCIE_RC_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_SHIFT)) & PCIE_RC_PHY_INTEROP_CTRL_2_OFF_DSP_PCIPM_L1_ENTER_DELAY_MASK) /*! @} */ /*! @name PIPE_RELATED_OFF - PIPE Related Register. */ /*! @{ */ #define PCIE_RC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MASK (0x100U) #define PCIE_RC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SHIFT (8U) /*! PIPE_GARBAGE_DATA_MODE - PIPE Garbage Data Mode. * 0b0..PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is de-asserted. * 0b1..Special PHY Support mode: The MAC discards any symbols received after the electrical idle ordered-set * until when any of the following three conditions are true: */ #define PCIE_RC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_SHIFT)) & PCIE_RC_PIPE_RELATED_OFF_PIPE_GARBAGE_DATA_MODE_MASK) /*! @} */ /*! @name DBI_FUNCTION_BANK_CTRL_REG_OFF - DBI Function Bank Control Register. */ /*! @{ */ #define PCIE_RC_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_MASK (0x1U) #define PCIE_RC_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_SHIFT (0U) /*! DBI_FUNCTION_BANK_CTRL_REG - DBI Function Bank Select. * 0b0..Functions 0 to 31 are accessible from DBI. * 0b1..Functions 32 to 63 are accessible from DBI. */ #define PCIE_RC_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_SHIFT)) & PCIE_RC_DBI_FUNCTION_BANK_CTRL_REG_OFF_DBI_FUNCTION_BANK_CTRL_REG_MASK) /*! @} */ /*! @name UTILITY_OFF - UTILITY register (Reserved). */ /*! @{ */ #define PCIE_RC_UTILITY_OFF_UTILITY_MASK (0xFFFFFFFFU) #define PCIE_RC_UTILITY_OFF_UTILITY_SHIFT (0U) /*! UTILITY - Reserved. */ #define PCIE_RC_UTILITY_OFF_UTILITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_UTILITY_OFF_UTILITY_SHIFT)) & PCIE_RC_UTILITY_OFF_UTILITY_MASK) /*! @} */ /*! @name PM_UTILITY_OFF - PM Shadow of UTILITY register (Reserved). */ /*! @{ */ #define PCIE_RC_PM_UTILITY_OFF_PM_UTILITY_MASK (0xFFFFFFFFU) #define PCIE_RC_PM_UTILITY_OFF_PM_UTILITY_SHIFT (0U) /*! PM_UTILITY - Reserved. */ #define PCIE_RC_PM_UTILITY_OFF_PM_UTILITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_RC_PM_UTILITY_OFF_PM_UTILITY_SHIFT)) & PCIE_RC_PM_UTILITY_OFF_PM_UTILITY_MASK) /*! @} */ /*! * @} */ /* end of group PCIE_RC_Register_Masks */ /* PCIE_RC - Peripheral instance base addresses */ /** Peripheral HSIO__PCIE1__PCIE_RC base address */ #define HSIO__PCIE1__PCIE_RC_BASE (0x4C300000u) /** Peripheral HSIO__PCIE1__PCIE_RC base pointer */ #define HSIO__PCIE1__PCIE_RC ((PCIE_RC_Type *)HSIO__PCIE1__PCIE_RC_BASE) /** Peripheral HSIO__PCIE2__PCIE_RC base address */ #define HSIO__PCIE2__PCIE_RC_BASE (0x4C380000u) /** Peripheral HSIO__PCIE2__PCIE_RC base pointer */ #define HSIO__PCIE2__PCIE_RC ((PCIE_RC_Type *)HSIO__PCIE2__PCIE_RC_BASE) /** Array initializer of PCIE_RC peripheral base addresses */ #define PCIE_RC_BASE_ADDRS { HSIO__PCIE1__PCIE_RC_BASE, HSIO__PCIE2__PCIE_RC_BASE } /** Array initializer of PCIE_RC peripheral base pointers */ #define PCIE_RC_BASE_PTRS { HSIO__PCIE1__PCIE_RC, HSIO__PCIE2__PCIE_RC } /*! * @} */ /* end of group PCIE_RC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PCIE_SHADOW_EP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_SHADOW_EP_Peripheral_Access_Layer PCIE_SHADOW_EP Peripheral Access Layer * @{ */ /** PCIE_SHADOW_EP - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[16]; __O uint32_t BAR0_MASK_REG; /**< BAR0 Mask Register., offset: 0x10 */ __O uint32_t BAR1_MASK_REG; /**< BAR1 Mask Register., offset: 0x14 */ __O uint32_t BAR2_MASK_REG; /**< BAR2 Mask Register., offset: 0x18 */ __O uint32_t BAR3_MASK_REG; /**< BAR3 Mask Register., offset: 0x1C */ __O uint32_t BAR4_MASK_REG; /**< BAR4 Mask Register., offset: 0x20 */ __O uint32_t BAR5_MASK_REG; /**< BAR5 Mask Register., offset: 0x24 */ uint8_t RESERVED_1[8]; __O uint32_t EXP_ROM_BAR_MASK_REG; /**< Expansion ROM BAR Mask Register., offset: 0x30 */ } PCIE_SHADOW_EP_Type; /* ---------------------------------------------------------------------------- -- PCIE_SHADOW_EP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PCIE_SHADOW_EP_Register_Masks PCIE_SHADOW_EP Register Masks * @{ */ /*! @name BAR0_MASK_REG - BAR0 Mask Register. */ /*! @{ */ #define PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_MASK (0x1U) #define PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_SHIFT (0U) /*! PCI_TYPE0_BAR0_ENABLED - - BAR0 Mask Enabled. */ #define PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_SHIFT)) & PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_MASK) #define PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_MASK (0xFFFFFFFEU) #define PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_SHIFT (1U) /*! PCI_TYPE0_BAR0_MASK - - BAR0 Mask. */ #define PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_SHIFT)) & PCIE_SHADOW_EP_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_MASK) /*! @} */ /*! @name BAR1_MASK_REG - BAR1 Mask Register. */ /*! @{ */ #define PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_MASK (0x1U) #define PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_SHIFT (0U) /*! PCI_TYPE0_BAR1_ENABLED - - BAR1 Mask Enabled. */ #define PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_SHIFT)) & PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_MASK) #define PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_MASK (0xFFFFFFFEU) #define PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_SHIFT (1U) /*! PCI_TYPE0_BAR1_MASK - - BAR1 Mask. */ #define PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_SHIFT)) & PCIE_SHADOW_EP_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_MASK) /*! @} */ /*! @name BAR2_MASK_REG - BAR2 Mask Register. */ /*! @{ */ #define PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_MASK (0x1U) #define PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_SHIFT (0U) /*! PCI_TYPE0_BAR2_ENABLED - BAR2 Mask Enabled. */ #define PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_SHIFT)) & PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_ENABLED_MASK) #define PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_MASK (0xFFFFFFFEU) #define PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_SHIFT (1U) /*! PCI_TYPE0_BAR2_MASK - BAR2 Mask. */ #define PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_SHIFT)) & PCIE_SHADOW_EP_BAR2_MASK_REG_PCI_TYPE0_BAR2_MASK_MASK) /*! @} */ /*! @name BAR3_MASK_REG - BAR3 Mask Register. */ /*! @{ */ #define PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_MASK (0x1U) #define PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_SHIFT (0U) /*! PCI_TYPE0_BAR3_ENABLED - BAR3 Mask Enabled. */ #define PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_SHIFT)) & PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_ENABLED_MASK) #define PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_MASK (0xFFFFFFFEU) #define PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_SHIFT (1U) /*! PCI_TYPE0_BAR3_MASK - BAR3 Mask. */ #define PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_SHIFT)) & PCIE_SHADOW_EP_BAR3_MASK_REG_PCI_TYPE0_BAR3_MASK_MASK) /*! @} */ /*! @name BAR4_MASK_REG - BAR4 Mask Register. */ /*! @{ */ #define PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_MASK (0x1U) #define PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_SHIFT (0U) /*! PCI_TYPE0_BAR4_ENABLED - BAR4 Mask Enabled. */ #define PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_SHIFT)) & PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_MASK) #define PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_MASK (0xFFFFFFFEU) #define PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_SHIFT (1U) /*! PCI_TYPE0_BAR4_MASK - BAR4 Mask. */ #define PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_SHIFT)) & PCIE_SHADOW_EP_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_MASK) /*! @} */ /*! @name BAR5_MASK_REG - BAR5 Mask Register. */ /*! @{ */ #define PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_MASK (0x1U) #define PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_SHIFT (0U) /*! PCI_TYPE0_BAR5_ENABLED - BAR5 Mask Enabled. */ #define PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_SHIFT)) & PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_MASK) #define PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_MASK (0xFFFFFFFEU) #define PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_SHIFT (1U) /*! PCI_TYPE0_BAR5_MASK - BAR5 Mask. */ #define PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_SHIFT)) & PCIE_SHADOW_EP_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_MASK) /*! @} */ /*! @name EXP_ROM_BAR_MASK_REG - Expansion ROM BAR Mask Register. */ /*! @{ */ #define PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_MASK (0x1U) #define PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_SHIFT (0U) /*! ROM_BAR_ENABLED - Expansion ROM Bar Mask Register Enabled. */ #define PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_SHIFT)) & PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_MASK) #define PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_MASK_MASK (0xFFFFFFFEU) #define PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_MASK_SHIFT (1U) /*! ROM_MASK - Expansion ROM Mask. */ #define PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_MASK_SHIFT)) & PCIE_SHADOW_EP_EXP_ROM_BAR_MASK_REG_ROM_MASK_MASK) /*! @} */ /*! * @} */ /* end of group PCIE_SHADOW_EP_Register_Masks */ /* PCIE_SHADOW_EP - Peripheral instance base addresses */ /** Peripheral HSIO__PCIE1__PCIE_SHADOW_EP base address */ #define HSIO__PCIE1__PCIE_SHADOW_EP_BASE (0x4C320000u) /** Peripheral HSIO__PCIE1__PCIE_SHADOW_EP base pointer */ #define HSIO__PCIE1__PCIE_SHADOW_EP ((PCIE_SHADOW_EP_Type *)HSIO__PCIE1__PCIE_SHADOW_EP_BASE) /** Peripheral HSIO__PCIE2__PCIE_SHADOW_EP base address */ #define HSIO__PCIE2__PCIE_SHADOW_EP_BASE (0x4C3A0000u) /** Peripheral HSIO__PCIE2__PCIE_SHADOW_EP base pointer */ #define HSIO__PCIE2__PCIE_SHADOW_EP ((PCIE_SHADOW_EP_Type *)HSIO__PCIE2__PCIE_SHADOW_EP_BASE) /** Array initializer of PCIE_SHADOW_EP peripheral base addresses */ #define PCIE_SHADOW_EP_BASE_ADDRS { HSIO__PCIE1__PCIE_SHADOW_EP_BASE, HSIO__PCIE2__PCIE_SHADOW_EP_BASE } /** Array initializer of PCIE_SHADOW_EP peripheral base pointers */ #define PCIE_SHADOW_EP_BASE_PTRS { HSIO__PCIE1__PCIE_SHADOW_EP, HSIO__PCIE2__PCIE_SHADOW_EP } /*! * @} */ /* end of group PCIE_SHADOW_EP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PDM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer * @{ */ /** PDM - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL_1; /**< MICFIL Control 1, offset: 0x0 */ __IO uint32_t CTRL_2; /**< MICFIL Control 2, offset: 0x4 */ __IO uint32_t STAT; /**< MICFIL Status, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control, offset: 0x10 */ __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status, offset: 0x14 */ uint8_t RESERVED_1[12]; __I uint32_t DATACH[8]; /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */ uint8_t RESERVED_2[32]; __IO uint32_t DC_CTRL; /**< MICFIL DC Remover Control, offset: 0x64 */ __IO uint32_t DC_OUT_CTRL; /**< MICFIL Output DC Remover Control, offset: 0x68 */ uint8_t RESERVED_3[8]; __IO uint32_t RANGE_CTRL; /**< MICFIL Range Control, offset: 0x74 */ uint8_t RESERVED_4[4]; __IO uint32_t RANGE_STAT; /**< MICFIL Range Status, offset: 0x7C */ __IO uint32_t FSYNC_CTRL; /**< Frame Synchronization Control, offset: 0x80 */ __I uint32_t VERID; /**< Version ID, offset: 0x84 */ __I uint32_t PARAM; /**< Parameter, offset: 0x88 */ uint8_t RESERVED_5[4]; __IO uint32_t VAD0_CTRL_1; /**< Voice Activity Detector 0 Control, offset: 0x90 */ __IO uint32_t VAD0_CTRL_2; /**< Voice Activity Detector 0 Control, offset: 0x94 */ __IO uint32_t VAD0_STAT; /**< Voice Activity Detector 0 Status, offset: 0x98 */ __IO uint32_t VAD0_SCONFIG; /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */ __IO uint32_t VAD0_NCONFIG; /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */ __I uint32_t VAD0_NDATA; /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */ __IO uint32_t VAD0_ZCD; /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */ } PDM_Type; /* ---------------------------------------------------------------------------- -- PDM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PDM_Register_Masks PDM Register Masks * @{ */ /*! @name CTRL_1 - MICFIL Control 1 */ /*! @{ */ #define PDM_CTRL_1_CH0EN_MASK (0x1U) #define PDM_CTRL_1_CH0EN_SHIFT (0U) /*! CH0EN - Channel 0 Enable */ #define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) #define PDM_CTRL_1_CH1EN_MASK (0x2U) #define PDM_CTRL_1_CH1EN_SHIFT (1U) /*! CH1EN - Channel 1 Enable */ #define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) #define PDM_CTRL_1_CH2EN_MASK (0x4U) #define PDM_CTRL_1_CH2EN_SHIFT (2U) /*! CH2EN - Channel 2 Enable */ #define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) #define PDM_CTRL_1_CH3EN_MASK (0x8U) #define PDM_CTRL_1_CH3EN_SHIFT (3U) /*! CH3EN - Channel 3 Enable */ #define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) #define PDM_CTRL_1_CH4EN_MASK (0x10U) #define PDM_CTRL_1_CH4EN_SHIFT (4U) /*! CH4EN - Channel 4 Enable */ #define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK) #define PDM_CTRL_1_CH5EN_MASK (0x20U) #define PDM_CTRL_1_CH5EN_SHIFT (5U) /*! CH5EN - Channel 5 Enable */ #define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK) #define PDM_CTRL_1_CH6EN_MASK (0x40U) #define PDM_CTRL_1_CH6EN_SHIFT (6U) /*! CH6EN - Channel 6 Enable */ #define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK) #define PDM_CTRL_1_CH7EN_MASK (0x80U) #define PDM_CTRL_1_CH7EN_SHIFT (7U) /*! CH7EN - Channel 7 Enable */ #define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK) #define PDM_CTRL_1_FSYNCEN_MASK (0x10000U) #define PDM_CTRL_1_FSYNCEN_SHIFT (16U) /*! FSYNCEN - Frame Synchronization Enable * 0b0..Disables * 0b1..Enables */ #define PDM_CTRL_1_FSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK) #define PDM_CTRL_1_DECFILS_MASK (0x100000U) #define PDM_CTRL_1_DECFILS_SHIFT (20U) /*! DECFILS - Decimation Filter Enable in Stop * 0b0..Stops decimation filter * 0b1..Keeps decimation filter running */ #define PDM_CTRL_1_DECFILS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK) #define PDM_CTRL_1_ERREN_MASK (0x800000U) #define PDM_CTRL_1_ERREN_SHIFT (23U) /*! ERREN - Error Interruption Enable * 0b0..Disables * 0b1..Enables */ #define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) #define PDM_CTRL_1_DISEL_MASK (0x3000000U) #define PDM_CTRL_1_DISEL_SHIFT (24U) /*! DISEL - DMA Interrupt Selection * 0b00..Disables DMA and interrupt requests * 0b01..Enables DMA requests * 0b10..Enables interrupt requests * 0b11..Reserved */ #define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) #define PDM_CTRL_1_DBGE_MASK (0x4000000U) #define PDM_CTRL_1_DBGE_SHIFT (26U) /*! DBGE - Module Enable in Debug * 0b0..Disables after completing the current frame * 0b1..Enables operation */ #define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) #define PDM_CTRL_1_SRES_MASK (0x8000000U) #define PDM_CTRL_1_SRES_SHIFT (27U) /*! SRES - Software Reset * 0b0..No action * 0b1..Software reset */ #define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) #define PDM_CTRL_1_DBG_MASK (0x10000000U) #define PDM_CTRL_1_DBG_SHIFT (28U) /*! DBG - Debug Mode * 0b0..Normal * 0b1..Debug */ #define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) #define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) #define PDM_CTRL_1_PDMIEN_SHIFT (29U) /*! PDMIEN - MICFIL Enable * 0b0..Stops MICFIL operation * 0b1..Starts MICFIL operation */ #define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) #define PDM_CTRL_1_DOZEN_MASK (0x40000000U) #define PDM_CTRL_1_DOZEN_SHIFT (30U) /*! DOZEN - Doze Enable * 0b0..Disables * 0b1..Enables */ #define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) #define PDM_CTRL_1_MDIS_MASK (0x80000000U) #define PDM_CTRL_1_MDIS_SHIFT (31U) /*! MDIS - Module Disable * 0b0..Normal mode * 0b1..DLL mode */ #define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) /*! @} */ /*! @name CTRL_2 - MICFIL Control 2 */ /*! @{ */ #define PDM_CTRL_2_CLKDIV_MASK (0xFFU) #define PDM_CTRL_2_CLKDIV_SHIFT (0U) /*! CLKDIV - Clock Divider * 0b00000000..Internal clock divider value = 0 * 0b00000001..Internal clock divider value = 1 * 0b00000010-0b11111110..... * 0b11111111..Internal clock divider value = 255 */ #define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) #define PDM_CTRL_2_CICOSR_MASK (0xF0000U) #define PDM_CTRL_2_CICOSR_SHIFT (16U) /*! CICOSR - CIC Decimation Rate * 0b0000..CIC oversampling rate = 0 * 0b0001..CIC oversampling rate = 1 * 0b0010-0b1110..... * 0b1111..CIC oversampling rate = 15 */ #define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) #define PDM_CTRL_2_QSEL_MASK (0xE000000U) #define PDM_CTRL_2_QSEL_SHIFT (25U) /*! QSEL - Quality Mode * 0b001..High-Quality mode * 0b000..Medium-Quality mode * 0b111..Low-Quality mode * 0b110..Very-Low-Quality 0 mode * 0b101..Very-Low-Quality 1 mode * 0b100..Very-Low-Quality 2 mode */ #define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) /*! @} */ /*! @name STAT - MICFIL Status */ /*! @{ */ #define PDM_STAT_CH0F_MASK (0x1U) #define PDM_STAT_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) #define PDM_STAT_CH1F_MASK (0x2U) #define PDM_STAT_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) #define PDM_STAT_CH2F_MASK (0x4U) #define PDM_STAT_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) #define PDM_STAT_CH3F_MASK (0x8U) #define PDM_STAT_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) #define PDM_STAT_CH4F_MASK (0x10U) #define PDM_STAT_CH4F_SHIFT (4U) /*! CH4F - Channel 4 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK) #define PDM_STAT_CH5F_MASK (0x20U) #define PDM_STAT_CH5F_SHIFT (5U) /*! CH5F - Channel 5 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK) #define PDM_STAT_CH6F_MASK (0x40U) #define PDM_STAT_CH6F_SHIFT (6U) /*! CH6F - Channel 6 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK) #define PDM_STAT_CH7F_MASK (0x80U) #define PDM_STAT_CH7F_SHIFT (7U) /*! CH7F - Channel 7 Output Data Flag * 0b0..Not surpassed * 0b1..Surpassed */ #define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK) #define PDM_STAT_LOWFREQF_MASK (0x20000000U) #define PDM_STAT_LOWFREQF_SHIFT (29U) /*! LOWFREQF - Low Frequency Flag * 0b0..CLKDIV value is OK * 0b1..CLKDIV value is too low */ #define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK) #define PDM_STAT_FIR_RDY_MASK (0x40000000U) #define PDM_STAT_FIR_RDY_SHIFT (30U) /*! FIR_RDY - Filter Data Ready * 0b0..Not reliable * 0b1..Reliable */ #define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK) #define PDM_STAT_BSY_FIL_MASK (0x80000000U) #define PDM_STAT_BSY_FIL_SHIFT (31U) /*! BSY_FIL - Busy Flag * 0b1..MICFIL is running * 0b0..MICFIL is stopped */ #define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) /*! @} */ /*! @name FIFO_CTRL - MICFIL FIFO Control */ /*! @{ */ #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x1FU) #define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) /*! FIFOWMK - FIFO Watermark Control */ #define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) /*! @} */ /*! @name FIFO_STAT - MICFIL FIFO Status */ /*! @{ */ #define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) #define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) /*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) #define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) #define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) /*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) #define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) #define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) /*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) #define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) #define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) /*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) #define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U) #define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U) /*! FIFOOVF4 - FIFO Overflow Exception Flag for Channel 4 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK) #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) #define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U) /*! FIFOOVF5 - FIFO Overflow Exception Flag for Channel 5 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK) #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) #define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U) /*! FIFOOVF6 - FIFO Overflow Exception Flag for Channel 6 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK) #define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U) #define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U) /*! FIFOOVF7 - FIFO Overflow Exception Flag for Channel 7 * 0b0..No exception by FIFO overflow * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK) #define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) #define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) /*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) #define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) #define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) /*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) #define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) #define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) /*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) #define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) #define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) /*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) #define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U) #define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U) /*! FIFOUND4 - FIFO Underflow Exception Flag for Channel 4 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK) #define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U) #define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U) /*! FIFOUND5 - FIFO Underflow Exception Flag for Channel 5 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK) #define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U) #define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U) /*! FIFOUND6 - FIFO Underflow Exception Flag for Channel 6 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK) #define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U) #define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U) /*! FIFOUND7 - FIFO Underflow Exception Flag for Channel 7 * 0b0..No exception by FIFO underflow * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK) /*! @} */ /*! @name DATACH - MICFIL Output Result */ /*! @{ */ #define PDM_DATACH_DATA_MASK (0xFFFFFFFFU) #define PDM_DATACH_DATA_SHIFT (0U) /*! DATA - Channel n Data */ #define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK) /*! @} */ /* The count of PDM_DATACH */ #define PDM_DATACH_COUNT (8U) /*! @name DC_CTRL - MICFIL DC Remover Control */ /*! @{ */ #define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) #define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) #define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) #define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) #define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U) #define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U) /*! DCCONFIG4 - Channel 4 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK) #define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U) #define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U) /*! DCCONFIG5 - Channel 5 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK) #define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U) #define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U) /*! DCCONFIG6 - Channel 6 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK) #define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U) #define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U) /*! DCCONFIG7 - Channel 7 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (PDM_CLK = 3.072 MHz) * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) * 0b10..40 Hz (PDM_CLK = 3.072 MHz) */ #define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK) /*! @} */ /*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */ /*! @{ */ #define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG4_MASK (0x300U) #define PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT (8U) /*! DCCONFIG4 - Channel 4 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG4_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG5_MASK (0xC00U) #define PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT (10U) /*! DCCONFIG5 - Channel 5 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG5_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG6_MASK (0x3000U) #define PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT (12U) /*! DCCONFIG6 - Channel 6 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG6_MASK) #define PDM_DC_OUT_CTRL_DCCONFIG7_MASK (0xC000U) #define PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT (14U) /*! DCCONFIG7 - Channel 7 DC Remover Configuration * 0b11..DC remover is bypassed * 0b00..20 Hz (FS = 48 kHz) * 0b01..13.3 Hz (FS = 48 kHz) * 0b10..40 Hz (FS = 48 kHz) */ #define PDM_DC_OUT_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG7_MASK) /*! @} */ /*! @name RANGE_CTRL - MICFIL Range Control */ /*! @{ */ #define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) /*! RANGEADJ0 - Channel 0 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) #define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) /*! RANGEADJ1 - Channel 1 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) #define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) /*! RANGEADJ2 - Channel 2 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) #define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) /*! RANGEADJ3 - Channel 3 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) #define PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U) #define PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U) /*! RANGEADJ4 - Channel 4 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK) #define PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U) #define PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U) /*! RANGEADJ5 - Channel 5 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK) #define PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U) #define PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U) /*! RANGEADJ6 - Channel 6 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK) #define PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U) #define PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U) /*! RANGEADJ7 - Channel 7 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK) /*! @} */ /*! @name RANGE_STAT - MICFIL Range Status */ /*! @{ */ #define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) #define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) #define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) #define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) #define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) #define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) #define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) #define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) #define PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U) #define PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U) /*! RANGEOVF4 - Channel 4 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK) #define PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U) #define PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U) /*! RANGEOVF5 - Channel 5 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK) #define PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U) #define PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U) /*! RANGEOVF6 - Channel 6 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK) #define PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U) #define PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U) /*! RANGEOVF7 - Channel 7 Range Overflow Error Flag * 0b0..No exception by range overflow * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK) #define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) #define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) #define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) #define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) #define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) #define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) #define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) #define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) #define PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U) #define PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U) /*! RANGEUNF4 - Channel 4 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK) #define PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U) #define PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U) /*! RANGEUNF5 - Channel 5 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK) #define PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U) #define PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U) /*! RANGEUNF6 - Channel 6 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK) #define PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U) #define PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U) /*! RANGEUNF7 - Channel 7 Range Underflow Error Flag * 0b0..No exception by range underflow * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK) /*! @} */ /*! @name FSYNC_CTRL - Frame Synchronization Control */ /*! @{ */ #define PDM_FSYNC_CTRL_FSYNCLEN_MASK (0xFFFFFFFFU) #define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT (0U) /*! FSYNCLEN - Frame Synchronization Window Length */ #define PDM_FSYNC_CTRL_FSYNCLEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK) /*! @} */ /*! @name VERID - Version ID */ /*! @{ */ #define PDM_VERID_FEATURE_MASK (0xFFFFU) #define PDM_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number */ #define PDM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK) #define PDM_VERID_MINOR_MASK (0xFF0000U) #define PDM_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define PDM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK) #define PDM_VERID_MAJOR_MASK (0xFF000000U) #define PDM_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define PDM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define PDM_PARAM_NPAIR_MASK (0xFU) #define PDM_PARAM_NPAIR_SHIFT (0U) /*! NPAIR - Number of Microphone Pairs * 0b0000..None * 0b0001..1 pair * 0b0010..2 pairs * 0b0011-0b1110..... * 0b1111..15 pairs */ #define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) #define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) #define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) /*! FIFO_PTRWID - FIFO Pointer Width * 0b0000..0 bits * 0b0001..1 bit * 0b0010..2 bits * 0b0011-0b1110..... * 0b1111..15 bits */ #define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) #define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) #define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT (8U) /*! FIL_OUT_WIDTH_24B - Filter Output Width * 0b0..16 bits * 0b1..24 bits */ #define PDM_PARAM_FIL_OUT_WIDTH_24B(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK) #define PDM_PARAM_LOW_POWER_MASK (0x200U) #define PDM_PARAM_LOW_POWER_SHIFT (9U) /*! LOW_POWER - Low-Power Decimation Filter * 0b0..Disables * 0b1..Enables */ #define PDM_PARAM_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK) #define PDM_PARAM_DC_BYPASS_MASK (0x400U) #define PDM_PARAM_DC_BYPASS_SHIFT (10U) /*! DC_BYPASS - Input DC Remover Bypass * 0b0..Active * 0b1..Disabled */ #define PDM_PARAM_DC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK) #define PDM_PARAM_DC_OUT_BYPASS_MASK (0x800U) #define PDM_PARAM_DC_OUT_BYPASS_SHIFT (11U) /*! DC_OUT_BYPASS - Output DC Remover Bypass * 0b0..Active * 0b1..Disabled */ #define PDM_PARAM_DC_OUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK) #define PDM_PARAM_HWVAD_MASK (0x10000U) #define PDM_PARAM_HWVAD_SHIFT (16U) /*! HWVAD - HWVAD Active * 0b0..Disabled * 0b1..Active */ #define PDM_PARAM_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_SHIFT)) & PDM_PARAM_HWVAD_MASK) #define PDM_PARAM_HWVAD_ENERGY_MODE_MASK (0x20000U) #define PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT (17U) /*! HWVAD_ENERGY_MODE - HWVAD Energy Mode Active * 0b0..Disabled * 0b1..Active */ #define PDM_PARAM_HWVAD_ENERGY_MODE(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ENERGY_MODE_SHIFT)) & PDM_PARAM_HWVAD_ENERGY_MODE_MASK) #define PDM_PARAM_HWVAD_ZCD_MASK (0x80000U) #define PDM_PARAM_HWVAD_ZCD_SHIFT (19U) /*! HWVAD_ZCD - HWVAD ZCD Active * 0b0..Disabled * 0b1..Active */ #define PDM_PARAM_HWVAD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_HWVAD_ZCD_SHIFT)) & PDM_PARAM_HWVAD_ZCD_MASK) #define PDM_PARAM_NUM_HWVAD_MASK (0xF000000U) #define PDM_PARAM_NUM_HWVAD_SHIFT (24U) /*! NUM_HWVAD - Number of HWVADs */ #define PDM_PARAM_NUM_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NUM_HWVAD_SHIFT)) & PDM_PARAM_NUM_HWVAD_MASK) /*! @} */ /*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control */ /*! @{ */ #define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U) #define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U) /*! VADEN - HWVAD Enable * 0b0..Disables * 0b1..Enables */ #define PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK) #define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U) #define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U) /*! VADRST - HWVAD Reset */ #define PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK) #define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U) #define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U) /*! VADIE - Interruption Enable * 0b0..Disables * 0b1..Enables */ #define PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK) #define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U) #define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U) /*! VADERIE - Error Interruption Enable * 0b0..Disables * 0b1..Enables */ #define PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK) #define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U) #define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U) /*! VADST10 - Internal Filters Initialization * 0b0..Normal operation * 0b1..Filters initialized */ #define PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK) #define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U) #define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U) /*! VADINITT - Initialization Time * 0b00000..0 * 0b00001..1 * 0b00010-0b11110..... * 0b11111..31 */ #define PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK) #define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U) #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U) /*! VADCICOSR - CIC Oversampling Rate */ #define PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK) #define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U) #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U) /*! VADCHSEL - Channel Selector * 0b000..PDM Microphone 0 Left * 0b001..PDM Microphone 0 Right * 0b010..PDM Microphone 1 Left * 0b011-0b101..... * 0b110..PDM Microphone 3 Left * 0b111..PDM Microphone 3 Right */ #define PDM_VAD0_CTRL_1_VADCHSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK) /*! @} */ /*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control */ /*! @{ */ #define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U) #define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U) /*! VADHPF - High-Pass Filter * 0b00..Filter bypassed * 0b01..Cut-off frequency at 1750 Hz * 0b10..Cut-off frequency at 215 Hz * 0b11..Cut-off frequency at 102 Hz */ #define PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK) #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U) #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U) /*! VADINPGAIN - Input Gain * 0b0000..No shift * 0b0001..Shift 1 bit to the left * 0b0010..Shift 2 bits to the left * 0b0011-0b0110..... * 0b0111..Shift 7 bits to the left * 0b1000..Shift 8 bits to the right * 0b1001..Shift 7 bits to the right * 0b1010-0b1110..... * 0b1111..Shift 1 bits to the right */ #define PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK) #define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U) #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U) /*! VADFRAMET - Frame Time * 0b000000..1 * 0b000001..2 * 0b000010-0b111110..... * 0b111111..63 */ #define PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK) #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U) #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U) /*! VADFOUTDIS - Force Output Disable * 0b0..Enables * 0b1..Disables */ #define PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK) #define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U) #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U) /*! VADPREFEN - Pre Filter Enable * 0b0..Pre-filter bypassed * 0b1..Pre-filter enabled */ #define PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK) #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U) #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U) /*! VADFRENDIS - Frame Energy Disable * 0b1..Disables * 0b0..Enables */ #define PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK) /*! @} */ /*! @name VAD0_STAT - Voice Activity Detector 0 Status */ /*! @{ */ #define PDM_VAD0_STAT_VADIF_MASK (0x1U) #define PDM_VAD0_STAT_VADIF_SHIFT (0U) /*! VADIF - Interrupt Flag * 0b0..Not detected * 0b1..Detected */ #define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK) #define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U) #define PDM_VAD0_STAT_VADINSATF_SHIFT (16U) /*! VADINSATF - Input Saturation Flag * 0b0..No exception * 0b1..Exception */ #define PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK) #define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U) #define PDM_VAD0_STAT_VADINITF_SHIFT (31U) /*! VADINITF - Initialization Flag * 0b0..Not being initialized * 0b1..Being initialized */ #define PDM_VAD0_STAT_VADINITF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK) /*! @} */ /*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */ /*! @{ */ #define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU) #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U) /*! VADSGAIN - Signal Gain * 0b0000, 0b0001..Multiplier = 1 * 0b0010..Multiplier = 2 * 0b0011-0b1110..... * 0b1111..Multiplier = 15 */ #define PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK) #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U) #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U) /*! VADSMAXEN - Signal Maximum Enable * 0b0..Maximum block bypassed * 0b1..Maximum block enabled */ #define PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK) #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U) /*! VADSFILEN - Signal Filter Enable * 0b0..Disables * 0b1..Enables */ #define PDM_VAD0_SCONFIG_VADSFILEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK) /*! @} */ /*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */ /*! @{ */ #define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU) #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U) /*! VADNGAIN - Noise Gain * 0b0000, 0b0001..Multiplier = 1 * 0b0010..Multiplier = 2 * 0b0011-0b1110..... * 0b1111..Multiplier = 15 */ #define PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK) #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U) #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U) /*! VADNFILADJ - Noise Filter Adjustment * 0b00000..0 * 0b00001..1 * 0b00010-0b11110..... * 0b11111..31 */ #define PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK) #define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U) #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U) /*! VADNOREN - Noise OR Enable * 0b0..Not decimated * 0b1..Decimated */ #define PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK) #define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U) #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U) /*! VADNDECEN - Noise Decimation Enable * 0b0..Not decimated * 0b1..Decimated */ #define PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK) #define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U) #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U) /*! VADNMINEN - Noise Minimum Enable * 0b0..Minimum block bypassed * 0b1..Minimum block enabled */ #define PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK) #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U) #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U) /*! VADNFILAUTO - Noise Filter Auto * 0b0..Always enabled * 0b1..Enabled or disabled based on voice activity information */ #define PDM_VAD0_NCONFIG_VADNFILAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK) /*! @} */ /*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */ /*! @{ */ #define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU) #define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U) /*! VADNDATA - Noise Data */ #define PDM_VAD0_NDATA_VADNDATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK) /*! @} */ /*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */ /*! @{ */ #define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U) #define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U) /*! VADZCDEN - ZCD Enable * 0b0..Disables * 0b1..Enables */ #define PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK) #define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U) #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U) /*! VADZCDAUTO - ZCD Automatic Threshold * 0b0..Disables * 0b1..Enables */ #define PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK) #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) #define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U) /*! VADZCDAND - ZCD AND Behavior * 0b0..OR * 0b1..AND */ #define PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK) #define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U) #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U) /*! VADZCDADJ - ZCD Adjustment * 0b0000..0 * 0b0001..1 * 0b0010-0b1110..... * 0b1111..15 */ #define PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK) #define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U) #define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U) /*! VADZCDTH - ZCD Threshold */ #define PDM_VAD0_ZCD_VADZCDTH(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK) /*! @} */ /*! * @} */ /* end of group PDM_Register_Masks */ /* PDM - Peripheral instance base addresses */ /** Peripheral PDM base address */ #define PDM_BASE (0x44520000u) /** Peripheral PDM base pointer */ #define PDM ((PDM_Type *)PDM_BASE) /** Array initializer of PDM peripheral base addresses */ #define PDM_BASE_ADDRS { PDM_BASE } /** Array initializer of PDM peripheral base pointers */ #define PDM_BASE_PTRS { PDM } /*! * @} */ /* end of group PDM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PIPE_CONF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PIPE_CONF_Peripheral_Access_Layer PIPE_CONF Peripheral Access Layer * @{ */ /** PIPE_CONF - Register Layout Typedef */ typedef struct { __IO uint32_t SOFT_RESET; /**< NEO Soft Reset, offset: 0x0 */ __IO uint32_t BUS_TXPARAM; /**< NEO Bus Transaction Parameter Register, offset: 0x4 */ __IO uint32_t REG_XFR_DIS; /**< NEO Register Transfer Error Disable, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t CSI_CTRL; /**< NEO CSI Control, offset: 0x10 */ __IO uint32_t FRAME_NUM; /**< NEO Frame Number, offset: 0x14 */ __IO uint32_t REG_SHD_CTRL; /**< NEO Register Shadowing Control, offset: 0x18 */ __IO uint32_t REG_SHD_CMD; /**< NEO Register Shadowing Command, offset: 0x1C */ __IO uint32_t TRIG_CAM[1]; /**< NEO Camera 0 Trigger, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_1[12]; struct { /* offset: 0x30, array step: 0x40 */ __IO uint32_t IMG_CONF_CAM; /**< NEO Camera 0 Image Configuration, array offset: 0x30, array step: 0x40 */ __IO uint32_t IMG_SIZE_CAM; /**< NEO Camera 0 Image Size Register, array offset: 0x34, array step: 0x40 */ uint8_t RESERVED_0[4]; __IO uint32_t IMG0_IN_ADDR_CAM; /**< NEO Camera 0 Input Image 0 Base Address Register, array offset: 0x3C, array step: 0x40 */ __IO uint32_t IMG1_IN_ADDR_CAM; /**< NEO Camera 0 Input Image 1 Base Address, array offset: 0x40, array step: 0x40 */ __IO uint32_t OUTCH0_ADDR_CAM; /**< NEO Camera 0 Output Channel 0 Base Address Register, array offset: 0x44, array step: 0x40 */ __IO uint32_t OUTCH1_ADDR_CAM; /**< NEO Camera 0 Output Channel 1 Base Address Register, array offset: 0x48, array step: 0x40 */ __IO uint32_t OUTIR_ADDR_CAM; /**< NEO Camera 0 Output IR Component Base Address Register, array offset: 0x4C, array step: 0x40 */ __IO uint32_t IMG0_IN_LS_CAM; /**< NEO Camera 0 Input Image 0 Line Stride Register, array offset: 0x50, array step: 0x40 */ __IO uint32_t IMG1_IN_LS_CAM; /**< NEO Camera 0 Input Image 1 Line Stride Register, array offset: 0x54, array step: 0x40 */ __IO uint32_t OUTCH0_LS_CAM; /**< NEO Camera 0 Output Y Component Line Stride Register, array offset: 0x58, array step: 0x40 */ __IO uint32_t OUTCH1_LS_CAM; /**< NEO Camera 0 Output Channel 1 Component Line Stride Register, array offset: 0x5C, array step: 0x40 */ __IO uint32_t OUTIR_LS_CAM; /**< NEO Camera 0 Output IR Component Line Stride Register, array offset: 0x60, array step: 0x40 */ __IO uint32_t SKIP_CTRL; /**< NEO Camera 0 Pixel Skip Control Register, array offset: 0x64, array step: 0x40 */ __IO uint32_t INT_EN; /**< NEO Camera 0 Interrupt Enable Register, array offset: 0x68, array step: 0x40 */ __IO uint32_t INT_STAT; /**< NEO Camera 0 Interrupt Status Register, array offset: 0x6C, array step: 0x40 */ } NEO_PIPE_IMG_CONF_ARRAY[1]; __IO uint32_t CSI_STAT; /**< NEO CSI Timing Status Register, offset: 0x70 */ } PIPE_CONF_Type; /* ---------------------------------------------------------------------------- -- PIPE_CONF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PIPE_CONF_Register_Masks PIPE_CONF Register Masks * @{ */ /*! @name SOFT_RESET - NEO Soft Reset */ /*! @{ */ #define PIPE_CONF_SOFT_RESET_SOFT_RESET_MASK (0x1U) #define PIPE_CONF_SOFT_RESET_SOFT_RESET_SHIFT (0U) #define PIPE_CONF_SOFT_RESET_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_SOFT_RESET_SOFT_RESET_SHIFT)) & PIPE_CONF_SOFT_RESET_SOFT_RESET_MASK) #define PIPE_CONF_SOFT_RESET_HARD_RESET_MASK (0x2U) #define PIPE_CONF_SOFT_RESET_HARD_RESET_SHIFT (1U) #define PIPE_CONF_SOFT_RESET_HARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_SOFT_RESET_HARD_RESET_SHIFT)) & PIPE_CONF_SOFT_RESET_HARD_RESET_MASK) /*! @} */ /*! @name BUS_TXPARAM - NEO Bus Transaction Parameter Register */ /*! @{ */ #define PIPE_CONF_BUS_TXPARAM_OTLT_MASK (0xFFU) #define PIPE_CONF_BUS_TXPARAM_OTLT_SHIFT (0U) #define PIPE_CONF_BUS_TXPARAM_OTLT(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_BUS_TXPARAM_OTLT_SHIFT)) & PIPE_CONF_BUS_TXPARAM_OTLT_MASK) #define PIPE_CONF_BUS_TXPARAM_OTHT_MASK (0xFF00U) #define PIPE_CONF_BUS_TXPARAM_OTHT_SHIFT (8U) #define PIPE_CONF_BUS_TXPARAM_OTHT(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_BUS_TXPARAM_OTHT_SHIFT)) & PIPE_CONF_BUS_TXPARAM_OTHT_MASK) #define PIPE_CONF_BUS_TXPARAM_POSTQOS_MASK (0xFF0000U) #define PIPE_CONF_BUS_TXPARAM_POSTQOS_SHIFT (16U) /*! POSTQOS * 0b00000000..Post QOS threshold is 10 * 0b00000001..Post QOS threshold is 64 (that is 64 * field value) * 0b00000010..Post QOS threshold is 128 (that is 64 * field value) * 0b00000011..Post QOS threshold is 192 (that is 64 * field value) * 0b11111110..Post QOS threshold is 16256 (that is 64 * field value) * 0b11111111..Post QOS is disabled */ #define PIPE_CONF_BUS_TXPARAM_POSTQOS(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_BUS_TXPARAM_POSTQOS_SHIFT)) & PIPE_CONF_BUS_TXPARAM_POSTQOS_MASK) #define PIPE_CONF_BUS_TXPARAM_BSIZE_MASK (0xFF000000U) #define PIPE_CONF_BUS_TXPARAM_BSIZE_SHIFT (24U) /*! BSIZE * 0b00000000..Each burst has maximum of 4 beats * 0b00000001..Each burst has maximum of 8 beats * 0b00000010..Each burst has maximum of 16 beats */ #define PIPE_CONF_BUS_TXPARAM_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_BUS_TXPARAM_BSIZE_SHIFT)) & PIPE_CONF_BUS_TXPARAM_BSIZE_MASK) /*! @} */ /*! @name REG_XFR_DIS - NEO Register Transfer Error Disable */ /*! @{ */ #define PIPE_CONF_REG_XFR_DIS_XFR_ERR_DIS_MASK (0x80000000U) #define PIPE_CONF_REG_XFR_DIS_XFR_ERR_DIS_SHIFT (31U) #define PIPE_CONF_REG_XFR_DIS_XFR_ERR_DIS(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_REG_XFR_DIS_XFR_ERR_DIS_SHIFT)) & PIPE_CONF_REG_XFR_DIS_XFR_ERR_DIS_MASK) /*! @} */ /*! @name CSI_CTRL - NEO CSI Control */ /*! @{ */ #define PIPE_CONF_CSI_CTRL_VID0_MASK (0x1FU) #define PIPE_CONF_CSI_CTRL_VID0_SHIFT (0U) #define PIPE_CONF_CSI_CTRL_VID0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_CTRL_VID0_SHIFT)) & PIPE_CONF_CSI_CTRL_VID0_MASK) #define PIPE_CONF_CSI_CTRL_VID1_MASK (0x1F00U) #define PIPE_CONF_CSI_CTRL_VID1_SHIFT (8U) #define PIPE_CONF_CSI_CTRL_VID1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_CTRL_VID1_SHIFT)) & PIPE_CONF_CSI_CTRL_VID1_MASK) #define PIPE_CONF_CSI_CTRL_SSEN_MASK (0x20000000U) #define PIPE_CONF_CSI_CTRL_SSEN_SHIFT (29U) #define PIPE_CONF_CSI_CTRL_SSEN(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_CTRL_SSEN_SHIFT)) & PIPE_CONF_CSI_CTRL_SSEN_MASK) #define PIPE_CONF_CSI_CTRL_DEVL_MASK (0x40000000U) #define PIPE_CONF_CSI_CTRL_DEVL_SHIFT (30U) #define PIPE_CONF_CSI_CTRL_DEVL(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_CTRL_DEVL_SHIFT)) & PIPE_CONF_CSI_CTRL_DEVL_MASK) #define PIPE_CONF_CSI_CTRL_CSI_EN_MASK (0x80000000U) #define PIPE_CONF_CSI_CTRL_CSI_EN_SHIFT (31U) /*! CSI_EN * 0b0..CSI streaming is disabled. Input image(s) are read from system memory. * 0b1..CSI streaming is enabled. No read operation is done on system memory. Minimum image width that can be programmed is 256 pixels. */ #define PIPE_CONF_CSI_CTRL_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_CTRL_CSI_EN_SHIFT)) & PIPE_CONF_CSI_CTRL_CSI_EN_MASK) /*! @} */ /*! @name FRAME_NUM - NEO Frame Number */ /*! @{ */ #define PIPE_CONF_FRAME_NUM_CURR_FRAME_MASK (0xFFFFU) #define PIPE_CONF_FRAME_NUM_CURR_FRAME_SHIFT (0U) #define PIPE_CONF_FRAME_NUM_CURR_FRAME(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_FRAME_NUM_CURR_FRAME_SHIFT)) & PIPE_CONF_FRAME_NUM_CURR_FRAME_MASK) #define PIPE_CONF_FRAME_NUM_SHD_FRAME_MASK (0xFFFF0000U) #define PIPE_CONF_FRAME_NUM_SHD_FRAME_SHIFT (16U) #define PIPE_CONF_FRAME_NUM_SHD_FRAME(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_FRAME_NUM_SHD_FRAME_SHIFT)) & PIPE_CONF_FRAME_NUM_SHD_FRAME_MASK) /*! @} */ /*! @name REG_SHD_CTRL - NEO Register Shadowing Control */ /*! @{ */ #define PIPE_CONF_REG_SHD_CTRL_CTRL_MASK (0x80000000U) #define PIPE_CONF_REG_SHD_CTRL_CTRL_SHIFT (31U) /*! CTRL * 0b0..Register shadowing is done at every frame/context start. * 0b1..Register shadowing is done at frame/context start if the shadowing command register is set to 1. */ #define PIPE_CONF_REG_SHD_CTRL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_REG_SHD_CTRL_CTRL_SHIFT)) & PIPE_CONF_REG_SHD_CTRL_CTRL_MASK) /*! @} */ /*! @name REG_SHD_CMD - NEO Register Shadowing Command */ /*! @{ */ #define PIPE_CONF_REG_SHD_CMD_CMD_MASK (0xFFFFFFFFU) #define PIPE_CONF_REG_SHD_CMD_CMD_SHIFT (0U) #define PIPE_CONF_REG_SHD_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_REG_SHD_CMD_CMD_SHIFT)) & PIPE_CONF_REG_SHD_CMD_CMD_MASK) /*! @} */ /*! @name TRIG_CAM - NEO Camera 0 Trigger */ /*! @{ */ #define PIPE_CONF_TRIG_CAM_TRIGGER_MASK (0xFFFFFFFFU) #define PIPE_CONF_TRIG_CAM_TRIGGER_SHIFT (0U) #define PIPE_CONF_TRIG_CAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_TRIG_CAM_TRIGGER_SHIFT)) & PIPE_CONF_TRIG_CAM_TRIGGER_MASK) /*! @} */ /* The count of PIPE_CONF_TRIG_CAM */ #define PIPE_CONF_TRIG_CAM_COUNT (1U) /*! @name IMG_CONF_CAM - NEO Camera 0 Image Configuration */ /*! @{ */ #define PIPE_CONF_IMG_CONF_CAM_IBPP0_MASK (0xFU) #define PIPE_CONF_IMG_CONF_CAM_IBPP0_SHIFT (0U) /*! IBPP0 * 0b0000..12 bpp (packed into 16 bits) * 0b0001..14 bpp (packed into 16 bits) * 0b0010..16 bpp (packed into 16 bits) * 0b0011..20 bpp (packed into 32 bits) * 0b0100..10 bpp (packed into 16 bits) * 0b0101..10 bpp packed (3 pixels packed into 32 bits) * 0b0110..8 bpp (packed into 8 bits) */ #define PIPE_CONF_IMG_CONF_CAM_IBPP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_CONF_CAM_IBPP0_SHIFT)) & PIPE_CONF_IMG_CONF_CAM_IBPP0_MASK) #define PIPE_CONF_IMG_CONF_CAM_INALIGN0_MASK (0x10U) #define PIPE_CONF_IMG_CONF_CAM_INALIGN0_SHIFT (4U) /*! INALIGN0 * 0b0..LSB aligned - lower order bits hold pixel value * 0b1..MSB aligned - higher order bits hold pixel values */ #define PIPE_CONF_IMG_CONF_CAM_INALIGN0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_CONF_CAM_INALIGN0_SHIFT)) & PIPE_CONF_IMG_CONF_CAM_INALIGN0_MASK) #define PIPE_CONF_IMG_CONF_CAM_LPALIGN0_MASK (0x20U) #define PIPE_CONF_IMG_CONF_CAM_LPALIGN0_SHIFT (5U) /*! LPALIGN0 * 0b0..LSB aligned - load the active pixel value towards the LSBs * 0b1..MSB aligned - load the active pixel value towards the MSBs */ #define PIPE_CONF_IMG_CONF_CAM_LPALIGN0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_CONF_CAM_LPALIGN0_SHIFT)) & PIPE_CONF_IMG_CONF_CAM_LPALIGN0_MASK) #define PIPE_CONF_IMG_CONF_CAM_IBPP1_MASK (0xF0000U) #define PIPE_CONF_IMG_CONF_CAM_IBPP1_SHIFT (16U) /*! IBPP1 * 0b0000..12 bpp (packed into 16 bits) * 0b0001..14 bpp (packed into 16 bits) * 0b0010..16 bpp (packed into 16 bits) * 0b0011..Reserved * 0b0100..10 bpp (packed into 16 bits) * 0b0101..10 bpp packed (3 pixels packed into 32 bits) * 0b0110..8 bpp (packed into 8 bits) */ #define PIPE_CONF_IMG_CONF_CAM_IBPP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_CONF_CAM_IBPP1_SHIFT)) & PIPE_CONF_IMG_CONF_CAM_IBPP1_MASK) #define PIPE_CONF_IMG_CONF_CAM_INALIGN1_MASK (0x100000U) #define PIPE_CONF_IMG_CONF_CAM_INALIGN1_SHIFT (20U) /*! INALIGN1 * 0b0..LSB aligned - lower order bits hold pixel value * 0b1..MSB aligned - higher order bits hold pixel values */ #define PIPE_CONF_IMG_CONF_CAM_INALIGN1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_CONF_CAM_INALIGN1_SHIFT)) & PIPE_CONF_IMG_CONF_CAM_INALIGN1_MASK) #define PIPE_CONF_IMG_CONF_CAM_LPALIGN1_MASK (0x200000U) #define PIPE_CONF_IMG_CONF_CAM_LPALIGN1_SHIFT (21U) /*! LPALIGN1 * 0b0..LSB aligned - load the active pixel value towards the LSBs * 0b1..MSB aligned - load the active pixel value towards the MSBs */ #define PIPE_CONF_IMG_CONF_CAM_LPALIGN1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_CONF_CAM_LPALIGN1_SHIFT)) & PIPE_CONF_IMG_CONF_CAM_LPALIGN1_MASK) /*! @} */ /* The count of PIPE_CONF_IMG_CONF_CAM */ #define PIPE_CONF_IMG_CONF_CAM_COUNT (1U) /*! @name IMG_SIZE_CAM - NEO Camera 0 Image Size Register */ /*! @{ */ #define PIPE_CONF_IMG_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define PIPE_CONF_IMG_SIZE_CAM_WIDTH_SHIFT (0U) #define PIPE_CONF_IMG_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_SIZE_CAM_WIDTH_SHIFT)) & PIPE_CONF_IMG_SIZE_CAM_WIDTH_MASK) #define PIPE_CONF_IMG_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define PIPE_CONF_IMG_SIZE_CAM_HEIGHT_SHIFT (16U) #define PIPE_CONF_IMG_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG_SIZE_CAM_HEIGHT_SHIFT)) & PIPE_CONF_IMG_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of PIPE_CONF_IMG_SIZE_CAM */ #define PIPE_CONF_IMG_SIZE_CAM_COUNT (1U) /*! @name IMG0_IN_ADDR_CAM - NEO Camera 0 Input Image 0 Base Address Register */ /*! @{ */ #define PIPE_CONF_IMG0_IN_ADDR_CAM_ADDR_MASK (0xFFFFFFFFU) #define PIPE_CONF_IMG0_IN_ADDR_CAM_ADDR_SHIFT (0U) #define PIPE_CONF_IMG0_IN_ADDR_CAM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG0_IN_ADDR_CAM_ADDR_SHIFT)) & PIPE_CONF_IMG0_IN_ADDR_CAM_ADDR_MASK) /*! @} */ /* The count of PIPE_CONF_IMG0_IN_ADDR_CAM */ #define PIPE_CONF_IMG0_IN_ADDR_CAM_COUNT (1U) /*! @name IMG1_IN_ADDR_CAM - NEO Camera 0 Input Image 1 Base Address */ /*! @{ */ #define PIPE_CONF_IMG1_IN_ADDR_CAM_ADDR_MASK (0xFFFFFFFFU) #define PIPE_CONF_IMG1_IN_ADDR_CAM_ADDR_SHIFT (0U) #define PIPE_CONF_IMG1_IN_ADDR_CAM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG1_IN_ADDR_CAM_ADDR_SHIFT)) & PIPE_CONF_IMG1_IN_ADDR_CAM_ADDR_MASK) /*! @} */ /* The count of PIPE_CONF_IMG1_IN_ADDR_CAM */ #define PIPE_CONF_IMG1_IN_ADDR_CAM_COUNT (1U) /*! @name OUTCH0_ADDR_CAM - NEO Camera 0 Output Channel 0 Base Address Register */ /*! @{ */ #define PIPE_CONF_OUTCH0_ADDR_CAM_ADDR_MASK (0xFFFFFFFFU) #define PIPE_CONF_OUTCH0_ADDR_CAM_ADDR_SHIFT (0U) #define PIPE_CONF_OUTCH0_ADDR_CAM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_OUTCH0_ADDR_CAM_ADDR_SHIFT)) & PIPE_CONF_OUTCH0_ADDR_CAM_ADDR_MASK) /*! @} */ /* The count of PIPE_CONF_OUTCH0_ADDR_CAM */ #define PIPE_CONF_OUTCH0_ADDR_CAM_COUNT (1U) /*! @name OUTCH1_ADDR_CAM - NEO Camera 0 Output Channel 1 Base Address Register */ /*! @{ */ #define PIPE_CONF_OUTCH1_ADDR_CAM_ADDR_MASK (0xFFFFFFFFU) #define PIPE_CONF_OUTCH1_ADDR_CAM_ADDR_SHIFT (0U) #define PIPE_CONF_OUTCH1_ADDR_CAM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_OUTCH1_ADDR_CAM_ADDR_SHIFT)) & PIPE_CONF_OUTCH1_ADDR_CAM_ADDR_MASK) /*! @} */ /* The count of PIPE_CONF_OUTCH1_ADDR_CAM */ #define PIPE_CONF_OUTCH1_ADDR_CAM_COUNT (1U) /*! @name OUTIR_ADDR_CAM - NEO Camera 0 Output IR Component Base Address Register */ /*! @{ */ #define PIPE_CONF_OUTIR_ADDR_CAM_ADDR_MASK (0xFFFFFFFFU) #define PIPE_CONF_OUTIR_ADDR_CAM_ADDR_SHIFT (0U) #define PIPE_CONF_OUTIR_ADDR_CAM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_OUTIR_ADDR_CAM_ADDR_SHIFT)) & PIPE_CONF_OUTIR_ADDR_CAM_ADDR_MASK) /*! @} */ /* The count of PIPE_CONF_OUTIR_ADDR_CAM */ #define PIPE_CONF_OUTIR_ADDR_CAM_COUNT (1U) /*! @name IMG0_IN_LS_CAM - NEO Camera 0 Input Image 0 Line Stride Register */ /*! @{ */ #define PIPE_CONF_IMG0_IN_LS_CAM_LS_MASK (0xFFFFFFF0U) #define PIPE_CONF_IMG0_IN_LS_CAM_LS_SHIFT (4U) #define PIPE_CONF_IMG0_IN_LS_CAM_LS(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG0_IN_LS_CAM_LS_SHIFT)) & PIPE_CONF_IMG0_IN_LS_CAM_LS_MASK) /*! @} */ /* The count of PIPE_CONF_IMG0_IN_LS_CAM */ #define PIPE_CONF_IMG0_IN_LS_CAM_COUNT (1U) /*! @name IMG1_IN_LS_CAM - NEO Camera 0 Input Image 1 Line Stride Register */ /*! @{ */ #define PIPE_CONF_IMG1_IN_LS_CAM_LS_MASK (0xFFFFFFF0U) #define PIPE_CONF_IMG1_IN_LS_CAM_LS_SHIFT (4U) #define PIPE_CONF_IMG1_IN_LS_CAM_LS(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_IMG1_IN_LS_CAM_LS_SHIFT)) & PIPE_CONF_IMG1_IN_LS_CAM_LS_MASK) /*! @} */ /* The count of PIPE_CONF_IMG1_IN_LS_CAM */ #define PIPE_CONF_IMG1_IN_LS_CAM_COUNT (1U) /*! @name OUTCH0_LS_CAM - NEO Camera 0 Output Y Component Line Stride Register */ /*! @{ */ #define PIPE_CONF_OUTCH0_LS_CAM_LS_MASK (0xFFFFFFF0U) #define PIPE_CONF_OUTCH0_LS_CAM_LS_SHIFT (4U) #define PIPE_CONF_OUTCH0_LS_CAM_LS(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_OUTCH0_LS_CAM_LS_SHIFT)) & PIPE_CONF_OUTCH0_LS_CAM_LS_MASK) /*! @} */ /* The count of PIPE_CONF_OUTCH0_LS_CAM */ #define PIPE_CONF_OUTCH0_LS_CAM_COUNT (1U) /*! @name OUTCH1_LS_CAM - NEO Camera 0 Output Channel 1 Component Line Stride Register */ /*! @{ */ #define PIPE_CONF_OUTCH1_LS_CAM_LS_MASK (0xFFFFFFF0U) #define PIPE_CONF_OUTCH1_LS_CAM_LS_SHIFT (4U) #define PIPE_CONF_OUTCH1_LS_CAM_LS(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_OUTCH1_LS_CAM_LS_SHIFT)) & PIPE_CONF_OUTCH1_LS_CAM_LS_MASK) /*! @} */ /* The count of PIPE_CONF_OUTCH1_LS_CAM */ #define PIPE_CONF_OUTCH1_LS_CAM_COUNT (1U) /*! @name OUTIR_LS_CAM - NEO Camera 0 Output IR Component Line Stride Register */ /*! @{ */ #define PIPE_CONF_OUTIR_LS_CAM_LS_MASK (0xFFFFFFF0U) #define PIPE_CONF_OUTIR_LS_CAM_LS_SHIFT (4U) #define PIPE_CONF_OUTIR_LS_CAM_LS(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_OUTIR_LS_CAM_LS_SHIFT)) & PIPE_CONF_OUTIR_LS_CAM_LS_MASK) /*! @} */ /* The count of PIPE_CONF_OUTIR_LS_CAM */ #define PIPE_CONF_OUTIR_LS_CAM_COUNT (1U) /*! @name SKIP_CTRL - NEO Camera 0 Pixel Skip Control Register */ /*! @{ */ #define PIPE_CONF_SKIP_CTRL_PRESKIP_MASK (0xFFFFU) #define PIPE_CONF_SKIP_CTRL_PRESKIP_SHIFT (0U) #define PIPE_CONF_SKIP_CTRL_PRESKIP(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_SKIP_CTRL_PRESKIP_SHIFT)) & PIPE_CONF_SKIP_CTRL_PRESKIP_MASK) #define PIPE_CONF_SKIP_CTRL_POSTSKIP_MASK (0xFFFF0000U) #define PIPE_CONF_SKIP_CTRL_POSTSKIP_SHIFT (16U) #define PIPE_CONF_SKIP_CTRL_POSTSKIP(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_SKIP_CTRL_POSTSKIP_SHIFT)) & PIPE_CONF_SKIP_CTRL_POSTSKIP_MASK) /*! @} */ /* The count of PIPE_CONF_SKIP_CTRL */ #define PIPE_CONF_SKIP_CTRL_COUNT (1U) /*! @name INT_EN - NEO Camera 0 Interrupt Enable Register */ /*! @{ */ #define PIPE_CONF_INT_EN_EN_FS1_MASK (0x1U) #define PIPE_CONF_INT_EN_EN_FS1_SHIFT (0U) #define PIPE_CONF_INT_EN_EN_FS1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_FS1_SHIFT)) & PIPE_CONF_INT_EN_EN_FS1_MASK) #define PIPE_CONF_INT_EN_EN_FS2_MASK (0x2U) #define PIPE_CONF_INT_EN_EN_FS2_SHIFT (1U) #define PIPE_CONF_INT_EN_EN_FS2(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_FS2_SHIFT)) & PIPE_CONF_INT_EN_EN_FS2_MASK) #define PIPE_CONF_INT_EN_EN_FD1_MASK (0x4U) #define PIPE_CONF_INT_EN_EN_FD1_SHIFT (2U) #define PIPE_CONF_INT_EN_EN_FD1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_FD1_SHIFT)) & PIPE_CONF_INT_EN_EN_FD1_MASK) #define PIPE_CONF_INT_EN_EN_FD2_MASK (0x8U) #define PIPE_CONF_INT_EN_EN_FD2_SHIFT (3U) #define PIPE_CONF_INT_EN_EN_FD2(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_FD2_SHIFT)) & PIPE_CONF_INT_EN_EN_FD2_MASK) #define PIPE_CONF_INT_EN_EN_STATD_MASK (0x10U) #define PIPE_CONF_INT_EN_EN_STATD_SHIFT (4U) #define PIPE_CONF_INT_EN_EN_STATD(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_STATD_SHIFT)) & PIPE_CONF_INT_EN_EN_STATD_MASK) #define PIPE_CONF_INT_EN_EN_DRCD_MASK (0x20U) #define PIPE_CONF_INT_EN_EN_DRCD_SHIFT (5U) #define PIPE_CONF_INT_EN_EN_DRCD(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_DRCD_SHIFT)) & PIPE_CONF_INT_EN_EN_DRCD_MASK) #define PIPE_CONF_INT_EN_EN_BUS_ERR_MASK (0xF0000U) #define PIPE_CONF_INT_EN_EN_BUS_ERR_SHIFT (16U) #define PIPE_CONF_INT_EN_EN_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_BUS_ERR_SHIFT)) & PIPE_CONF_INT_EN_EN_BUS_ERR_MASK) #define PIPE_CONF_INT_EN_EN_CSI_TERR_MASK (0x20000000U) #define PIPE_CONF_INT_EN_EN_CSI_TERR_SHIFT (29U) #define PIPE_CONF_INT_EN_EN_CSI_TERR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_CSI_TERR_SHIFT)) & PIPE_CONF_INT_EN_EN_CSI_TERR_MASK) #define PIPE_CONF_INT_EN_EN_TRIG_ERR_MASK (0x40000000U) #define PIPE_CONF_INT_EN_EN_TRIG_ERR_SHIFT (30U) #define PIPE_CONF_INT_EN_EN_TRIG_ERR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_EN_EN_TRIG_ERR_SHIFT)) & PIPE_CONF_INT_EN_EN_TRIG_ERR_MASK) /*! @} */ /* The count of PIPE_CONF_INT_EN */ #define PIPE_CONF_INT_EN_COUNT (1U) /*! @name INT_STAT - NEO Camera 0 Interrupt Status Register */ /*! @{ */ #define PIPE_CONF_INT_STAT_S_FS1_MASK (0x1U) #define PIPE_CONF_INT_STAT_S_FS1_SHIFT (0U) #define PIPE_CONF_INT_STAT_S_FS1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_FS1_SHIFT)) & PIPE_CONF_INT_STAT_S_FS1_MASK) #define PIPE_CONF_INT_STAT_S_FS2_MASK (0x2U) #define PIPE_CONF_INT_STAT_S_FS2_SHIFT (1U) #define PIPE_CONF_INT_STAT_S_FS2(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_FS2_SHIFT)) & PIPE_CONF_INT_STAT_S_FS2_MASK) #define PIPE_CONF_INT_STAT_S_FD1_MASK (0x4U) #define PIPE_CONF_INT_STAT_S_FD1_SHIFT (2U) #define PIPE_CONF_INT_STAT_S_FD1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_FD1_SHIFT)) & PIPE_CONF_INT_STAT_S_FD1_MASK) #define PIPE_CONF_INT_STAT_S_FD2_MASK (0x8U) #define PIPE_CONF_INT_STAT_S_FD2_SHIFT (3U) #define PIPE_CONF_INT_STAT_S_FD2(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_FD2_SHIFT)) & PIPE_CONF_INT_STAT_S_FD2_MASK) #define PIPE_CONF_INT_STAT_S_STATD_MASK (0x10U) #define PIPE_CONF_INT_STAT_S_STATD_SHIFT (4U) #define PIPE_CONF_INT_STAT_S_STATD(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_STATD_SHIFT)) & PIPE_CONF_INT_STAT_S_STATD_MASK) #define PIPE_CONF_INT_STAT_S_DRCD_MASK (0x20U) #define PIPE_CONF_INT_STAT_S_DRCD_SHIFT (5U) #define PIPE_CONF_INT_STAT_S_DRCD(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_DRCD_SHIFT)) & PIPE_CONF_INT_STAT_S_DRCD_MASK) #define PIPE_CONF_INT_STAT_S_BUS_ERR_MASK (0xF0000U) #define PIPE_CONF_INT_STAT_S_BUS_ERR_SHIFT (16U) #define PIPE_CONF_INT_STAT_S_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_BUS_ERR_SHIFT)) & PIPE_CONF_INT_STAT_S_BUS_ERR_MASK) #define PIPE_CONF_INT_STAT_S_CSI_TERR_MASK (0x20000000U) #define PIPE_CONF_INT_STAT_S_CSI_TERR_SHIFT (29U) #define PIPE_CONF_INT_STAT_S_CSI_TERR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_CSI_TERR_SHIFT)) & PIPE_CONF_INT_STAT_S_CSI_TERR_MASK) #define PIPE_CONF_INT_STAT_S_TRIG_ERR_MASK (0x40000000U) #define PIPE_CONF_INT_STAT_S_TRIG_ERR_SHIFT (30U) /*! S_TRIG_ERR * 0b0..No trigger error * 0b1..Trigger error generated */ #define PIPE_CONF_INT_STAT_S_TRIG_ERR(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_S_TRIG_ERR_SHIFT)) & PIPE_CONF_INT_STAT_S_TRIG_ERR_MASK) #define PIPE_CONF_INT_STAT_BUSY_MASK (0x80000000U) #define PIPE_CONF_INT_STAT_BUSY_SHIFT (31U) /*! BUSY * 0b0..Pipeline is ready to accept more triggers * 0b1..Pipeline is busy, and cannot accept more triggers */ #define PIPE_CONF_INT_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_INT_STAT_BUSY_SHIFT)) & PIPE_CONF_INT_STAT_BUSY_MASK) /*! @} */ /* The count of PIPE_CONF_INT_STAT */ #define PIPE_CONF_INT_STAT_COUNT (1U) /*! @name CSI_STAT - NEO CSI Timing Status Register */ /*! @{ */ #define PIPE_CONF_CSI_STAT_S_SL_LP0_MASK (0x1U) #define PIPE_CONF_CSI_STAT_S_SL_LP0_SHIFT (0U) #define PIPE_CONF_CSI_STAT_S_SL_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_SL_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_SL_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_SF_LP0_MASK (0x2U) #define PIPE_CONF_CSI_STAT_S_SF_LP0_SHIFT (1U) #define PIPE_CONF_CSI_STAT_S_SF_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_SF_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_SF_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_DO_LP0_MASK (0x4U) #define PIPE_CONF_CSI_STAT_S_DO_LP0_SHIFT (2U) #define PIPE_CONF_CSI_STAT_S_DO_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_DO_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_DO_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_LOC_LP0_MASK (0x8U) #define PIPE_CONF_CSI_STAT_S_LOC_LP0_SHIFT (3U) #define PIPE_CONF_CSI_STAT_S_LOC_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_LOC_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_LOC_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_LO_LP0_MASK (0x10U) #define PIPE_CONF_CSI_STAT_S_LO_LP0_SHIFT (4U) #define PIPE_CONF_CSI_STAT_S_LO_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_LO_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_LO_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_CMD_LP0_MASK (0x20U) #define PIPE_CONF_CSI_STAT_S_CMD_LP0_SHIFT (5U) #define PIPE_CONF_CSI_STAT_S_CMD_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_CMD_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_CMD_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_LL_LP0_MASK (0x40U) #define PIPE_CONF_CSI_STAT_S_LL_LP0_SHIFT (6U) #define PIPE_CONF_CSI_STAT_S_LL_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_LL_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_LL_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_DATA_LP0_MASK (0x80U) #define PIPE_CONF_CSI_STAT_S_DATA_LP0_SHIFT (7U) #define PIPE_CONF_CSI_STAT_S_DATA_LP0(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_DATA_LP0_SHIFT)) & PIPE_CONF_CSI_STAT_S_DATA_LP0_MASK) #define PIPE_CONF_CSI_STAT_S_SL_LP1_MASK (0x10000U) #define PIPE_CONF_CSI_STAT_S_SL_LP1_SHIFT (16U) #define PIPE_CONF_CSI_STAT_S_SL_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_SL_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_SL_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_SF_LP1_MASK (0x20000U) #define PIPE_CONF_CSI_STAT_S_SF_LP1_SHIFT (17U) #define PIPE_CONF_CSI_STAT_S_SF_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_SF_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_SF_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_DO_LP1_MASK (0x40000U) #define PIPE_CONF_CSI_STAT_S_DO_LP1_SHIFT (18U) #define PIPE_CONF_CSI_STAT_S_DO_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_DO_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_DO_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_LOC_LP1_MASK (0x80000U) #define PIPE_CONF_CSI_STAT_S_LOC_LP1_SHIFT (19U) #define PIPE_CONF_CSI_STAT_S_LOC_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_LOC_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_LOC_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_LO_LP1_MASK (0x100000U) #define PIPE_CONF_CSI_STAT_S_LO_LP1_SHIFT (20U) #define PIPE_CONF_CSI_STAT_S_LO_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_LO_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_LO_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_CMD_LP1_MASK (0x200000U) #define PIPE_CONF_CSI_STAT_S_CMD_LP1_SHIFT (21U) #define PIPE_CONF_CSI_STAT_S_CMD_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_CMD_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_CMD_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_LL_LP1_MASK (0x400000U) #define PIPE_CONF_CSI_STAT_S_LL_LP1_SHIFT (22U) #define PIPE_CONF_CSI_STAT_S_LL_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_LL_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_LL_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_DATA_LP1_MASK (0x800000U) #define PIPE_CONF_CSI_STAT_S_DATA_LP1_SHIFT (23U) #define PIPE_CONF_CSI_STAT_S_DATA_LP1(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_DATA_LP1_SHIFT)) & PIPE_CONF_CSI_STAT_S_DATA_LP1_MASK) #define PIPE_CONF_CSI_STAT_S_STOP_MASK (0x80000000U) #define PIPE_CONF_CSI_STAT_S_STOP_SHIFT (31U) #define PIPE_CONF_CSI_STAT_S_STOP(x) (((uint32_t)(((uint32_t)(x)) << PIPE_CONF_CSI_STAT_S_STOP_SHIFT)) & PIPE_CONF_CSI_STAT_S_STOP_MASK) /*! @} */ /*! * @} */ /* end of group PIPE_CONF_Register_Masks */ /* PIPE_CONF - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__PIPE_CONF base address */ #define CAMERA__ISP__PIPE_CONF_BASE (0x4AE00000u) /** Peripheral CAMERA__ISP__PIPE_CONF base pointer */ #define CAMERA__ISP__PIPE_CONF ((PIPE_CONF_Type *)CAMERA__ISP__PIPE_CONF_BASE) /** Array initializer of PIPE_CONF peripheral base addresses */ #define PIPE_CONF_BASE_ADDRS { CAMERA__ISP__PIPE_CONF_BASE } /** Array initializer of PIPE_CONF peripheral base pointers */ #define PIPE_CONF_BASE_PTRS { CAMERA__ISP__PIPE_CONF } /*! * @} */ /* end of group PIPE_CONF_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PLL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PLL_Peripheral_Access_Layer PLL Peripheral Access Layer * @{ */ /** PLL - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ __IO uint32_t RW; /**< PLL Control, offset: 0x0 */ __IO uint32_t SET; /**< PLL Control, offset: 0x4 */ __IO uint32_t CLR; /**< PLL Control, offset: 0x8 */ __IO uint32_t TOG; /**< PLL Control, offset: 0xC */ } CTRL; uint8_t RESERVED_0[32]; struct { /* offset: 0x30 */ __IO uint32_t RW; /**< Spread Spectrum, offset: 0x30, not available in all instances (available on 36 out of 42) */ __IO uint32_t SET; /**< Spread Spectrum, offset: 0x34, not available in all instances (available on 36 out of 42) */ __IO uint32_t CLR; /**< Spread Spectrum, offset: 0x38, not available in all instances (available on 36 out of 42) */ __IO uint32_t TOG; /**< Spread Spectrum, offset: 0x3C, not available in all instances (available on 36 out of 42) */ } SPREAD_SPECTRUM; struct { /* offset: 0x40 */ __IO uint32_t RW; /**< Numerator, offset: 0x40, not available in all instances (available on 36 out of 42) */ __IO uint32_t SET; /**< Numerator, offset: 0x44, not available in all instances (available on 36 out of 42) */ __IO uint32_t CLR; /**< Numerator, offset: 0x48, not available in all instances (available on 36 out of 42) */ __IO uint32_t TOG; /**< Numerator, offset: 0x4C, not available in all instances (available on 36 out of 42) */ } NUMERATOR; struct { /* offset: 0x50 */ __IO uint32_t RW; /**< Denominator, offset: 0x50, not available in all instances (available on 36 out of 42) */ __IO uint32_t SET; /**< Denominator, offset: 0x54, not available in all instances (available on 36 out of 42) */ __IO uint32_t CLR; /**< Denominator, offset: 0x58, not available in all instances (available on 36 out of 42) */ __IO uint32_t TOG; /**< Denominator, offset: 0x5C, not available in all instances (available on 36 out of 42) */ } DENOMINATOR; struct { /* offset: 0x60 */ __IO uint32_t RW; /**< PLL Dividers, offset: 0x60 */ __IO uint32_t SET; /**< PLL Dividers, offset: 0x64 */ __IO uint32_t CLR; /**< PLL Dividers, offset: 0x68 */ __IO uint32_t TOG; /**< PLL Dividers, offset: 0x6C */ } DIV; struct { /* offset: 0x70, array step: 0x20 */ struct { /* offset: 0x70 */ __IO uint32_t RW; /**< DFS Control, offset: 0x70, irregular array, not all indices are valid */ __IO uint32_t SET; /**< DFS Control, offset: 0x74, irregular array, not all indices are valid */ __IO uint32_t CLR; /**< DFS Control, offset: 0x78, irregular array, not all indices are valid */ __IO uint32_t TOG; /**< DFS Control, offset: 0x7C, irregular array, not all indices are valid */ } DFS_CTRL; struct { /* offset: 0x80 */ __IO uint32_t RW; /**< DFS Division_0..DFS Division_3, offset: 0x80, irregular array, not all indices are valid */ __IO uint32_t SET; /**< DFS Division_0..DFS Division_3, offset: 0x84, irregular array, not all indices are valid */ __IO uint32_t CLR; /**< DFS Division_0..DFS Division_3, offset: 0x88, irregular array, not all indices are valid */ __IO uint32_t TOG; /**< DFS Division_0..DFS Division_3, offset: 0x8C, irregular array, not all indices are valid */ } DFS_DIV; } DFS[4]; __I uint32_t PLL_STATUS; /**< PLL Status, offset: 0xF0 */ __I uint32_t DFS_STATUS; /**< DFS Status, offset: 0xF4, not available in all instances (available on 12 out of 42) */ } PLL_Type; /* ---------------------------------------------------------------------------- -- PLL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PLL_Register_Masks PLL Register Masks * @{ */ /*! @name CTRL - PLL Control */ /*! @{ */ #define PLL_CTRL_POWERUP_MASK (0x1U) #define PLL_CTRL_POWERUP_SHIFT (0U) /*! POWERUP - Power Up * 0b0..Disables PLL. * 0b1..Enables PLL */ #define PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_POWERUP_SHIFT)) & PLL_CTRL_POWERUP_MASK) #define PLL_CTRL_CLKMUX_EN_MASK (0x2U) #define PLL_CTRL_CLKMUX_EN_SHIFT (1U) /*! CLKMUX_EN - CLKMUX Enable * 0b0..Disables output clock mux. * 0b1..Enables output clock mux. */ #define PLL_CTRL_CLKMUX_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_CLKMUX_EN_SHIFT)) & PLL_CTRL_CLKMUX_EN_MASK) #define PLL_CTRL_CLKMUX_BYPASS_MASK (0x4U) #define PLL_CTRL_CLKMUX_BYPASS_SHIFT (2U) /*! CLKMUX_BYPASS - CLKMUX_Bypass * 0b0..Normal mode * 0b1..PLL bypass mode */ #define PLL_CTRL_CLKMUX_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_CLKMUX_BYPASS_SHIFT)) & PLL_CTRL_CLKMUX_BYPASS_MASK) #define PLL_CTRL_SPREADCTL_MASK (0x100U) #define PLL_CTRL_SPREADCTL_SHIFT (8U) /*! SPREADCTL - Modulation Type Select * 0b0..Modulation is centered around nominal frequency. * 0b1..Modulation is spread below nominal frequency. */ #define PLL_CTRL_SPREADCTL(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_SPREADCTL_SHIFT)) & PLL_CTRL_SPREADCTL_MASK) #define PLL_CTRL_HW_CTRL_SEL_MASK (0x10000U) #define PLL_CTRL_HW_CTRL_SEL_SHIFT (16U) /*! HW_CTRL_SEL - Hardware Control Select * 0b0..Disables hardware control. PLL is controlled by register. * 0b1..Enables hardware control. PLL is controlled by hardware inputs. In this case, NUMERATOR[MFN] cannot be changed dynamically. */ #define PLL_CTRL_HW_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_HW_CTRL_SEL_SHIFT)) & PLL_CTRL_HW_CTRL_SEL_MASK) #define PLL_CTRL_LOCK_BYPASS_MASK (0x80000000U) #define PLL_CTRL_LOCK_BYPASS_SHIFT (31U) /*! LOCK_BYPASS - Lock Bypass * 0b0..Disables bypass for the lock detector. * 0b1..Enables bypass for the lock detector. */ #define PLL_CTRL_LOCK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PLL_CTRL_LOCK_BYPASS_SHIFT)) & PLL_CTRL_LOCK_BYPASS_MASK) /*! @} */ /*! @name SPREAD_SPECTRUM - Spread Spectrum */ /*! @{ */ #define PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) #define PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) /*! STEP - Step */ #define PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & PLL_SPREAD_SPECTRUM_STEP_MASK) #define PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) #define PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) /*! ENABLE - Enable * 0b0..Disables the spread spectrum modulation. * 0b1..Enables the spread spectrum modulation. */ #define PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & PLL_SPREAD_SPECTRUM_ENABLE_MASK) #define PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) #define PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) /*! STOP - Stop */ #define PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & PLL_SPREAD_SPECTRUM_STOP_MASK) /*! @} */ /*! @name NUMERATOR - Numerator */ /*! @{ */ #define PLL_NUMERATOR_MFN_MASK (0xFFFFFFFCU) #define PLL_NUMERATOR_MFN_SHIFT (2U) /*! MFN - Numerator */ #define PLL_NUMERATOR_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_NUMERATOR_MFN_SHIFT)) & PLL_NUMERATOR_MFN_MASK) /*! @} */ /*! @name DENOMINATOR - Denominator */ /*! @{ */ #define PLL_DENOMINATOR_MFD_MASK (0x3FFFFFFFU) #define PLL_DENOMINATOR_MFD_SHIFT (0U) /*! MFD - Denominator */ #define PLL_DENOMINATOR_MFD(x) (((uint32_t)(((uint32_t)(x)) << PLL_DENOMINATOR_MFD_SHIFT)) & PLL_DENOMINATOR_MFD_MASK) /*! @} */ /*! @name DIV - PLL Dividers */ /*! @{ */ #define PLL_DIV_ODIV_MASK (0xFFU) #define PLL_DIV_ODIV_SHIFT (0U) /*! ODIV - Output Frequency Divider for Clock Output * 0b00000000..Divide by 2 * 0b00000001..Divide by 3 * 0b00000010..Divide by 2 * 0b00000011..Divide by 3 * 0b00000100..Divide by 4 * 0b00000101..Divide by 5 * 0b00000110..Divide by 6 * 0b00001010..Divide by 10 * 0b10000010..Divide by 130 * 0b11111111..Divide by 255 */ #define PLL_DIV_ODIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_ODIV_SHIFT)) & PLL_DIV_ODIV_MASK) #define PLL_DIV_RDIV_MASK (0xE000U) #define PLL_DIV_RDIV_SHIFT (13U) /*! RDIV - Input Clock Predivider * 0b000..Divide by 1 * 0b001..Divide by 1 * 0b010..Divide by 2 * 0b011..Divide by 3 * 0b100..Divide by 4 * 0b101..Divide by 5 * 0b110..Divide by 6 * 0b111..Divide by 7 */ #define PLL_DIV_RDIV(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_RDIV_SHIFT)) & PLL_DIV_RDIV_MASK) #define PLL_DIV_MFI_MASK (0x1FF0000U) #define PLL_DIV_MFI_SHIFT (16U) /*! MFI - Integer Portion of Loop Divider */ #define PLL_DIV_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLL_DIV_MFI_SHIFT)) & PLL_DIV_MFI_MASK) /*! @} */ /*! @name DFS - DFS Control */ /*! @{ */ #define PLL_DFS_HW_CTRL_SEL_MASK (0x10000U) #define PLL_DFS_HW_CTRL_SEL_SHIFT (16U) /*! HW_CTRL_SEL - Hardware Control Select * 0b0..Disables hardware control. DFS is controlled by register * 0b1..Enables hardware control. DFS is controlled by hardware inputs. */ #define PLL_DFS_HW_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_HW_CTRL_SEL_SHIFT)) & PLL_DFS_HW_CTRL_SEL_MASK) #define PLL_DFS_BYPASS_EN_MASK (0x800000U) #define PLL_DFS_BYPASS_EN_SHIFT (23U) /*! BYPASS_EN - Bypass Enable * 0b0..Disables bypass for DFS. * 0b1..Enables bypass for DFS. */ #define PLL_DFS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_BYPASS_EN_SHIFT)) & PLL_DFS_BYPASS_EN_MASK) #define PLL_DFS_CLKOUT_DIVBY2_EN_MASK (0x20000000U) #define PLL_DFS_CLKOUT_DIVBY2_EN_SHIFT (29U) /*! CLKOUT_DIVBY2_EN - DFS Clock Output Divide by 2 Enable * 0b0..Disables DFS divide by 2 clock output. * 0b1..Enables DFS divide by 2 clock output. */ #define PLL_DFS_CLKOUT_DIVBY2_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_CLKOUT_DIVBY2_EN_SHIFT)) & PLL_DFS_CLKOUT_DIVBY2_EN_MASK) #define PLL_DFS_CLKOUT_EN_MASK (0x40000000U) #define PLL_DFS_CLKOUT_EN_SHIFT (30U) /*! CLKOUT_EN - DFS Clock Output Enable * 0b0..Disables DFS clock output. * 0b1..Enables DFS clock output. */ #define PLL_DFS_CLKOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_CLKOUT_EN_SHIFT)) & PLL_DFS_CLKOUT_EN_MASK) #define PLL_DFS_ENABLE_MASK (0x80000000U) #define PLL_DFS_ENABLE_SHIFT (31U) /*! ENABLE - DFS Block Enable * 0b0..Disables DFS Block. * 0b1..Enables DFS Block. */ #define PLL_DFS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_ENABLE_SHIFT)) & PLL_DFS_ENABLE_MASK) /*! @} */ /*! @name DFS - DFS Division_0..DFS Division_3 */ /*! @{ */ #define PLL_DFS_MFN_MASK (0x7U) #define PLL_DFS_MFN_SHIFT (0U) /*! MFN - MFN */ #define PLL_DFS_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_MFN_SHIFT)) & PLL_DFS_MFN_MASK) #define PLL_DFS_MFI_MASK (0xFF00U) #define PLL_DFS_MFI_SHIFT (8U) /*! MFI - MFI */ #define PLL_DFS_MFI(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_MFI_SHIFT)) & PLL_DFS_MFI_MASK) /*! @} */ /*! @name PLL_STATUS - PLL Status */ /*! @{ */ #define PLL_PLL_STATUS_PLL_LOCK_MASK (0x1U) #define PLL_PLL_STATUS_PLL_LOCK_SHIFT (0U) /*! PLL_LOCK - PLL_LOCK */ #define PLL_PLL_STATUS_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_PLL_LOCK_SHIFT)) & PLL_PLL_STATUS_PLL_LOCK_MASK) #define PLL_PLL_STATUS_PLL_LOL_MASK (0x2U) #define PLL_PLL_STATUS_PLL_LOL_SHIFT (1U) /*! PLL_LOL - PLL_LOL */ #define PLL_PLL_STATUS_PLL_LOL(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_PLL_LOL_SHIFT)) & PLL_PLL_STATUS_PLL_LOL_MASK) #define PLL_PLL_STATUS_ANA_MFN_MASK (0xFFFFFFFCU) #define PLL_PLL_STATUS_ANA_MFN_SHIFT (2U) /*! ANA_MFN - ANA_MFN */ #define PLL_PLL_STATUS_ANA_MFN(x) (((uint32_t)(((uint32_t)(x)) << PLL_PLL_STATUS_ANA_MFN_SHIFT)) & PLL_PLL_STATUS_ANA_MFN_MASK) /*! @} */ /*! @name DFS_STATUS - DFS Status */ /*! @{ */ #define PLL_DFS_STATUS_DFS_OK_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ #define PLL_DFS_STATUS_DFS_OK_SHIFT (0U) /*! DFS_OK - DFS OK * 0b0000..The corresponding DFS output clock is not valid. * 0b0001..The corresponding DFS output clock is valid. */ #define PLL_DFS_STATUS_DFS_OK(x) (((uint32_t)(((uint32_t)(x)) << PLL_DFS_STATUS_DFS_OK_SHIFT)) & PLL_DFS_STATUS_DFS_OK_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ /*! @} */ /*! * @} */ /* end of group PLL_Register_Masks */ /* PLL - Peripheral instance base addresses */ /** Peripheral ANALOG__SYS_FRACT_PLL1 base address */ #define ANALOG__SYS_FRACT_PLL1_BASE (0x44481000u) /** Peripheral ANALOG__SYS_FRACT_PLL1 base pointer */ #define ANALOG__SYS_FRACT_PLL1 ((PLL_Type *)ANALOG__SYS_FRACT_PLL1_BASE) /** Peripheral ANALOG__AUDIO_FRACT_PLL1 base address */ #define ANALOG__AUDIO_FRACT_PLL1_BASE (0x44481100u) /** Peripheral ANALOG__AUDIO_FRACT_PLL1 base pointer */ #define ANALOG__AUDIO_FRACT_PLL1 ((PLL_Type *)ANALOG__AUDIO_FRACT_PLL1_BASE) /** Peripheral ANALOG__AUDIO_FRACT_PLL2 base address */ #define ANALOG__AUDIO_FRACT_PLL2_BASE (0x44481200u) /** Peripheral ANALOG__AUDIO_FRACT_PLL2 base pointer */ #define ANALOG__AUDIO_FRACT_PLL2 ((PLL_Type *)ANALOG__AUDIO_FRACT_PLL2_BASE) /** Peripheral ANALOG__VIDEO_FRACT_PLL1 base address */ #define ANALOG__VIDEO_FRACT_PLL1_BASE (0x44481300u) /** Peripheral ANALOG__VIDEO_FRACT_PLL1 base pointer */ #define ANALOG__VIDEO_FRACT_PLL1 ((PLL_Type *)ANALOG__VIDEO_FRACT_PLL1_BASE) /** Peripheral CORTEXA__FRACT_PLL_ARMPLL base address */ #define CORTEXA__FRACT_PLL_ARMPLL_BASE (0x44481600u) /** Peripheral CORTEXA__FRACT_PLL_ARMPLL base pointer */ #define CORTEXA__FRACT_PLL_ARMPLL ((PLL_Type *)CORTEXA__FRACT_PLL_ARMPLL_BASE) /** Peripheral DDRC__FRACT_PLL base address */ #define DDRC__FRACT_PLL_BASE (0x44481700u) /** Peripheral DDRC__FRACT_PLL base pointer */ #define DDRC__FRACT_PLL ((PLL_Type *)DDRC__FRACT_PLL_BASE) /** Peripheral DISPLAY__FRACT_PLL base address */ #define DISPLAY__FRACT_PLL_BASE (0x44481900u) /** Peripheral DISPLAY__FRACT_PLL base pointer */ #define DISPLAY__FRACT_PLL ((PLL_Type *)DISPLAY__FRACT_PLL_BASE) /** Array initializer of PLL peripheral base addresses */ #define PLL_BASE_ADDRS { ANALOG__SYS_FRACT_PLL1_BASE, ANALOG__AUDIO_FRACT_PLL1_BASE, ANALOG__AUDIO_FRACT_PLL2_BASE, ANALOG__VIDEO_FRACT_PLL1_BASE, CORTEXA__FRACT_PLL_ARMPLL_BASE, DDRC__FRACT_PLL_BASE, DISPLAY__FRACT_PLL_BASE } /** Array initializer of PLL peripheral base pointers */ #define PLL_BASE_PTRS { ANALOG__SYS_FRACT_PLL1, ANALOG__AUDIO_FRACT_PLL1, ANALOG__AUDIO_FRACT_PLL2, ANALOG__VIDEO_FRACT_PLL1, CORTEXA__FRACT_PLL_ARMPLL, DDRC__FRACT_PLL, DISPLAY__FRACT_PLL } /*! * @} */ /* end of group PLL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RGBIR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RGBIR_Peripheral_Access_Layer RGBIR Peripheral Access Layer * @{ */ /** RGBIR - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x40 */ __IO uint32_t CTRL_CAM; /**< Camera 0 RGBIR Control Register, array offset: 0x0, array step: 0x40 */ __IO uint32_t CCM0_CAM; /**< Camera 0 Color 0 Correction Register, array offset: 0x4, array step: 0x40 */ __IO uint32_t CCM1_CAM; /**< Camera 0 Color 1/2 Correction Register, array offset: 0x8, array step: 0x40 */ __IO uint32_t CCM2_CAM; /**< Camera 0 Color 2 Correction Register, array offset: 0xC, array step: 0x40 */ __IO uint32_t CCM0_TH_CAM; /**< Camera 0 channel 3 (IR) to channel 0 (Red) Crosstalk Threshold Register, array offset: 0x10, array step: 0x40 */ __IO uint32_t CCM1_TH_CAM; /**< Camera 0 channel 3 (IR) to channel 1 (Green) Crosstalk Threshold Register, array offset: 0x14, array step: 0x40 */ __IO uint32_t CCM2_TH_CAM; /**< Camera 0 channel 3 (IR) to channel 2 (Blue) Crosstalk Threshold Register, array offset: 0x18, array step: 0x40 */ uint8_t RESERVED_0[4]; __IO uint32_t ROI0_POS_CAM; /**< Camera 0 Statistics Region of Interest 0 Position Register, array offset: 0x20, array step: 0x40 */ __IO uint32_t ROI0_SIZE_CAM; /**< Camera 0 Statistics Region of Interest 0 Size Register, array offset: 0x24, array step: 0x40 */ __IO uint32_t ROI1_POS_CAM; /**< Camera 0 Statistics Region of Interest 1 Position Register, array offset: 0x28, array step: 0x40 */ __IO uint32_t ROI1_SIZE_CAM; /**< Camera 0 Statistics Region of Interest 1 Size Register, array offset: 0x2C, array step: 0x40 */ struct { /* offset: 0x30, array step: index*0x40, index2*0x8 */ __IO uint32_t CTRL_CAM; /**< Camera 0 RGBIR Histogram 0 Control Register..Camera 0 RGBIR Histogram 1 Control Register, array offset: 0x30, array step: index*0x40, index2*0x8 */ __IO uint32_t SCALE_CAM; /**< Camera 0 RGBIR Histogram 0 Scale Register..Camera 0 RGBIR Histogram 1 Scale Register, array offset: 0x34, array step: index*0x40, index2*0x8 */ } HIST[2]; } NEO_PIPE1_RGBIR_CONF[1]; } RGBIR_Type; /* ---------------------------------------------------------------------------- -- RGBIR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RGBIR_Register_Masks RGBIR Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 RGBIR Control Register */ /*! @{ */ #define RGBIR_CTRL_CAM_ENABLE_MASK (0x80000000U) #define RGBIR_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..Disabled, RGBIR output is same format is input * 0b1..Enabled */ #define RGBIR_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CTRL_CAM_ENABLE_SHIFT)) & RGBIR_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of RGBIR_CTRL_CAM */ #define RGBIR_CTRL_CAM_COUNT (1U) /*! @name CCM0_CAM - Camera 0 Color 0 Correction Register */ /*! @{ */ #define RGBIR_CCM0_CAM_CCM_MASK (0xFFFFU) #define RGBIR_CCM0_CAM_CCM_SHIFT (0U) #define RGBIR_CCM0_CAM_CCM(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CCM0_CAM_CCM_SHIFT)) & RGBIR_CCM0_CAM_CCM_MASK) /*! @} */ /* The count of RGBIR_CCM0_CAM */ #define RGBIR_CCM0_CAM_COUNT (1U) /*! @name CCM1_CAM - Camera 0 Color 1/2 Correction Register */ /*! @{ */ #define RGBIR_CCM1_CAM_CCM_MASK (0xFFFFU) #define RGBIR_CCM1_CAM_CCM_SHIFT (0U) #define RGBIR_CCM1_CAM_CCM(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CCM1_CAM_CCM_SHIFT)) & RGBIR_CCM1_CAM_CCM_MASK) /*! @} */ /* The count of RGBIR_CCM1_CAM */ #define RGBIR_CCM1_CAM_COUNT (1U) /*! @name CCM2_CAM - Camera 0 Color 2 Correction Register */ /*! @{ */ #define RGBIR_CCM2_CAM_CCM_MASK (0xFFFFU) #define RGBIR_CCM2_CAM_CCM_SHIFT (0U) #define RGBIR_CCM2_CAM_CCM(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CCM2_CAM_CCM_SHIFT)) & RGBIR_CCM2_CAM_CCM_MASK) /*! @} */ /* The count of RGBIR_CCM2_CAM */ #define RGBIR_CCM2_CAM_COUNT (1U) /*! @name CCM0_TH_CAM - Camera 0 channel 3 (IR) to channel 0 (Red) Crosstalk Threshold Register */ /*! @{ */ #define RGBIR_CCM0_TH_CAM_THRESHOLD_MASK (0xFFFFFU) #define RGBIR_CCM0_TH_CAM_THRESHOLD_SHIFT (0U) #define RGBIR_CCM0_TH_CAM_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CCM0_TH_CAM_THRESHOLD_SHIFT)) & RGBIR_CCM0_TH_CAM_THRESHOLD_MASK) /*! @} */ /* The count of RGBIR_CCM0_TH_CAM */ #define RGBIR_CCM0_TH_CAM_COUNT (1U) /*! @name CCM1_TH_CAM - Camera 0 channel 3 (IR) to channel 1 (Green) Crosstalk Threshold Register */ /*! @{ */ #define RGBIR_CCM1_TH_CAM_THRESHOLD_MASK (0xFFFFFU) #define RGBIR_CCM1_TH_CAM_THRESHOLD_SHIFT (0U) #define RGBIR_CCM1_TH_CAM_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CCM1_TH_CAM_THRESHOLD_SHIFT)) & RGBIR_CCM1_TH_CAM_THRESHOLD_MASK) /*! @} */ /* The count of RGBIR_CCM1_TH_CAM */ #define RGBIR_CCM1_TH_CAM_COUNT (1U) /*! @name CCM2_TH_CAM - Camera 0 channel 3 (IR) to channel 2 (Blue) Crosstalk Threshold Register */ /*! @{ */ #define RGBIR_CCM2_TH_CAM_THRESHOLD_MASK (0xFFFFFU) #define RGBIR_CCM2_TH_CAM_THRESHOLD_SHIFT (0U) #define RGBIR_CCM2_TH_CAM_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CCM2_TH_CAM_THRESHOLD_SHIFT)) & RGBIR_CCM2_TH_CAM_THRESHOLD_MASK) /*! @} */ /* The count of RGBIR_CCM2_TH_CAM */ #define RGBIR_CCM2_TH_CAM_COUNT (1U) /*! @name ROI0_POS_CAM - Camera 0 Statistics Region of Interest 0 Position Register */ /*! @{ */ #define RGBIR_ROI0_POS_CAM_XPOS_MASK (0xFFFFU) #define RGBIR_ROI0_POS_CAM_XPOS_SHIFT (0U) #define RGBIR_ROI0_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI0_POS_CAM_XPOS_SHIFT)) & RGBIR_ROI0_POS_CAM_XPOS_MASK) #define RGBIR_ROI0_POS_CAM_YPOS_MASK (0xFFFF0000U) #define RGBIR_ROI0_POS_CAM_YPOS_SHIFT (16U) #define RGBIR_ROI0_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI0_POS_CAM_YPOS_SHIFT)) & RGBIR_ROI0_POS_CAM_YPOS_MASK) /*! @} */ /* The count of RGBIR_ROI0_POS_CAM */ #define RGBIR_ROI0_POS_CAM_COUNT (1U) /*! @name ROI0_SIZE_CAM - Camera 0 Statistics Region of Interest 0 Size Register */ /*! @{ */ #define RGBIR_ROI0_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define RGBIR_ROI0_SIZE_CAM_WIDTH_SHIFT (0U) #define RGBIR_ROI0_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI0_SIZE_CAM_WIDTH_SHIFT)) & RGBIR_ROI0_SIZE_CAM_WIDTH_MASK) #define RGBIR_ROI0_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define RGBIR_ROI0_SIZE_CAM_HEIGHT_SHIFT (16U) #define RGBIR_ROI0_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI0_SIZE_CAM_HEIGHT_SHIFT)) & RGBIR_ROI0_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of RGBIR_ROI0_SIZE_CAM */ #define RGBIR_ROI0_SIZE_CAM_COUNT (1U) /*! @name ROI1_POS_CAM - Camera 0 Statistics Region of Interest 1 Position Register */ /*! @{ */ #define RGBIR_ROI1_POS_CAM_XPOS_MASK (0xFFFFU) #define RGBIR_ROI1_POS_CAM_XPOS_SHIFT (0U) #define RGBIR_ROI1_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI1_POS_CAM_XPOS_SHIFT)) & RGBIR_ROI1_POS_CAM_XPOS_MASK) #define RGBIR_ROI1_POS_CAM_YPOS_MASK (0xFFFF0000U) #define RGBIR_ROI1_POS_CAM_YPOS_SHIFT (16U) #define RGBIR_ROI1_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI1_POS_CAM_YPOS_SHIFT)) & RGBIR_ROI1_POS_CAM_YPOS_MASK) /*! @} */ /* The count of RGBIR_ROI1_POS_CAM */ #define RGBIR_ROI1_POS_CAM_COUNT (1U) /*! @name ROI1_SIZE_CAM - Camera 0 Statistics Region of Interest 1 Size Register */ /*! @{ */ #define RGBIR_ROI1_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define RGBIR_ROI1_SIZE_CAM_WIDTH_SHIFT (0U) #define RGBIR_ROI1_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI1_SIZE_CAM_WIDTH_SHIFT)) & RGBIR_ROI1_SIZE_CAM_WIDTH_MASK) #define RGBIR_ROI1_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define RGBIR_ROI1_SIZE_CAM_HEIGHT_SHIFT (16U) #define RGBIR_ROI1_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_ROI1_SIZE_CAM_HEIGHT_SHIFT)) & RGBIR_ROI1_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of RGBIR_ROI1_SIZE_CAM */ #define RGBIR_ROI1_SIZE_CAM_COUNT (1U) /*! @name CTRL_CAM - Camera 0 RGBIR Histogram 0 Control Register..Camera 0 RGBIR Histogram 1 Control Register */ /*! @{ */ #define RGBIR_CTRL_CAM_LIN_VS_LOG_MASK (0x1U) #define RGBIR_CTRL_CAM_LIN_VS_LOG_SHIFT (0U) /*! LIN_VS_LOG * 0b0..Linear: Scaled pixel value provides the bin number. * 0b1..Logarithmic: Log operation is performed scaled pixel value for providing the bin number. */ #define RGBIR_CTRL_CAM_LIN_VS_LOG(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CTRL_CAM_LIN_VS_LOG_SHIFT)) & RGBIR_CTRL_CAM_LIN_VS_LOG_MASK) #define RGBIR_CTRL_CAM_DIR_VS_DIF_MASK (0x2U) #define RGBIR_CTRL_CAM_DIR_VS_DIF_SHIFT (1U) /*! DIR_VS_DIF * 0b0..Direct: After correcting the black level offset, use the pixel value as is for scaling. * 0b1..Difference: After correcting the black level offset, use the difference with neighbouring pixel for scaling. */ #define RGBIR_CTRL_CAM_DIR_VS_DIF(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CTRL_CAM_DIR_VS_DIF_SHIFT)) & RGBIR_CTRL_CAM_DIR_VS_DIF_MASK) #define RGBIR_CTRL_CAM_PATTERN_MASK (0x4U) #define RGBIR_CTRL_CAM_PATTERN_SHIFT (2U) /*! PATTERN * 0b0..1x1: Neighbouring pixel is 1 position to the left * 0b1..2x2: Neighbouring pixel is 2 position to the left */ #define RGBIR_CTRL_CAM_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CTRL_CAM_PATTERN_SHIFT)) & RGBIR_CTRL_CAM_PATTERN_MASK) #define RGBIR_CTRL_CAM_CHANNEL_MASK (0xF00U) #define RGBIR_CTRL_CAM_CHANNEL_SHIFT (8U) /*! CHANNEL * 0b0001..1st channel of a 2x2 window of input image. * 0b0010..2nd channel of a 2x2 window of input image. * 0b0100..3rd channel of a 2x2 window of input image. This channel is only enabled when the 1st channel is disabled. * 0b1000..4th channel of a 2x2 window of input image. This channel is only enabled when the 2nd channel is disabled. */ #define RGBIR_CTRL_CAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CTRL_CAM_CHANNEL_SHIFT)) & RGBIR_CTRL_CAM_CHANNEL_MASK) #define RGBIR_CTRL_CAM_OFFSET_MASK (0xFFFF0000U) #define RGBIR_CTRL_CAM_OFFSET_SHIFT (16U) #define RGBIR_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_CTRL_CAM_OFFSET_SHIFT)) & RGBIR_CTRL_CAM_OFFSET_MASK) /*! @} */ /* The count of RGBIR_CTRL_CAM */ #define RGBIR_NEO_PIPE1_RGBIR_CONF_HIST_CTRL_CAM_COUNT (1U) /* The count of RGBIR_CTRL_CAM */ #define RGBIR_CTRL_CAM_COUNT2 (2U) /*! @name SCALE_CAM - Camera 0 RGBIR Histogram 0 Scale Register..Camera 0 RGBIR Histogram 1 Scale Register */ /*! @{ */ #define RGBIR_SCALE_CAM_SCALE_MASK (0xFFFFFFU) #define RGBIR_SCALE_CAM_SCALE_SHIFT (0U) #define RGBIR_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << RGBIR_SCALE_CAM_SCALE_SHIFT)) & RGBIR_SCALE_CAM_SCALE_MASK) /*! @} */ /* The count of RGBIR_SCALE_CAM */ #define RGBIR_SCALE_CAM_COUNT (1U) /* The count of RGBIR_SCALE_CAM */ #define RGBIR_SCALE_CAM_COUNT2 (2U) /*! * @} */ /* end of group RGBIR_Register_Masks */ /* RGBIR - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__RGBIR base address */ #define CAMERA__ISP__RGBIR_BASE (0x4AE00600u) /** Peripheral CAMERA__ISP__RGBIR base pointer */ #define CAMERA__ISP__RGBIR ((RGBIR_Type *)CAMERA__ISP__RGBIR_BASE) /** Array initializer of RGBIR peripheral base addresses */ #define RGBIR_BASE_ADDRS { CAMERA__ISP__RGBIR_BASE } /** Array initializer of RGBIR peripheral base pointers */ #define RGBIR_BASE_PTRS { CAMERA__ISP__RGBIR } /*! * @} */ /* end of group RGBIR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RGB_TO_YUV Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RGB_TO_YUV_Peripheral_Access_Layer RGB_TO_YUV Peripheral Access Layer * @{ */ /** RGB_TO_YUV - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x2C */ __IO uint32_t GAIN_CTRL_CAM; /**< Camera 0 CSC Gain Control Register, array offset: 0x0, array step: 0x2C */ __IO uint32_t MAT0_CAM; /**< Camera 0 CSC Matrix 0 Register, array offset: 0x4, array step: 0x2C */ __IO uint32_t MAT1_CAM; /**< Camera 0 CSC Matrix 1 Register, array offset: 0x8, array step: 0x2C */ __IO uint32_t MAT2_CAM; /**< Camera 0 CSC Matrix 2 Register, array offset: 0xC, array step: 0x2C */ __IO uint32_t MAT3_CAM; /**< Camera 0 CSC Matrix 3 Register, array offset: 0x10, array step: 0x2C */ __IO uint32_t MAT4_CAM; /**< Camera 0 CSC Matrix 4 Register, array offset: 0x14, array step: 0x2C */ __IO uint32_t MAT5_CAM; /**< Camera 0 CSC Matrix 5 Register, array offset: 0x18, array step: 0x2C */ uint8_t RESERVED_0[4]; __IO uint32_t OFFSET0_CAM; /**< Camera 0 CSC Offset 0 Register, array offset: 0x20, array step: 0x2C */ __IO uint32_t OFFSET1_CAM; /**< Camera 0 CSC Offset 1 Register, array offset: 0x24, array step: 0x2C */ __IO uint32_t OFFSET2_CAM; /**< Camera 0 CSC Offset 2 Register, array offset: 0x28, array step: 0x2C */ } NEO_PIPE2_CSC_CONF[1]; } RGB_TO_YUV_Type; /* ---------------------------------------------------------------------------- -- RGB_TO_YUV Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RGB_TO_YUV_Register_Masks RGB_TO_YUV Register Masks * @{ */ /*! @name GAIN_CTRL_CAM - Camera 0 CSC Gain Control Register */ /*! @{ */ #define RGB_TO_YUV_GAIN_CTRL_CAM_RGAIN_MASK (0xFFFFU) #define RGB_TO_YUV_GAIN_CTRL_CAM_RGAIN_SHIFT (0U) #define RGB_TO_YUV_GAIN_CTRL_CAM_RGAIN(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_GAIN_CTRL_CAM_RGAIN_SHIFT)) & RGB_TO_YUV_GAIN_CTRL_CAM_RGAIN_MASK) #define RGB_TO_YUV_GAIN_CTRL_CAM_BGAIN_MASK (0xFFFF0000U) #define RGB_TO_YUV_GAIN_CTRL_CAM_BGAIN_SHIFT (16U) #define RGB_TO_YUV_GAIN_CTRL_CAM_BGAIN(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_GAIN_CTRL_CAM_BGAIN_SHIFT)) & RGB_TO_YUV_GAIN_CTRL_CAM_BGAIN_MASK) /*! @} */ /* The count of RGB_TO_YUV_GAIN_CTRL_CAM */ #define RGB_TO_YUV_GAIN_CTRL_CAM_COUNT (1U) /*! @name MAT0_CAM - Camera 0 CSC Matrix 0 Register */ /*! @{ */ #define RGB_TO_YUV_MAT0_CAM_R0C0_MASK (0xFFFFU) #define RGB_TO_YUV_MAT0_CAM_R0C0_SHIFT (0U) #define RGB_TO_YUV_MAT0_CAM_R0C0(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT0_CAM_R0C0_SHIFT)) & RGB_TO_YUV_MAT0_CAM_R0C0_MASK) #define RGB_TO_YUV_MAT0_CAM_R0C1_MASK (0xFFFF0000U) #define RGB_TO_YUV_MAT0_CAM_R0C1_SHIFT (16U) #define RGB_TO_YUV_MAT0_CAM_R0C1(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT0_CAM_R0C1_SHIFT)) & RGB_TO_YUV_MAT0_CAM_R0C1_MASK) /*! @} */ /* The count of RGB_TO_YUV_MAT0_CAM */ #define RGB_TO_YUV_MAT0_CAM_COUNT (1U) /*! @name MAT1_CAM - Camera 0 CSC Matrix 1 Register */ /*! @{ */ #define RGB_TO_YUV_MAT1_CAM_R0C2_MASK (0xFFFFU) #define RGB_TO_YUV_MAT1_CAM_R0C2_SHIFT (0U) #define RGB_TO_YUV_MAT1_CAM_R0C2(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT1_CAM_R0C2_SHIFT)) & RGB_TO_YUV_MAT1_CAM_R0C2_MASK) /*! @} */ /* The count of RGB_TO_YUV_MAT1_CAM */ #define RGB_TO_YUV_MAT1_CAM_COUNT (1U) /*! @name MAT2_CAM - Camera 0 CSC Matrix 2 Register */ /*! @{ */ #define RGB_TO_YUV_MAT2_CAM_R1C0_MASK (0xFFFFU) #define RGB_TO_YUV_MAT2_CAM_R1C0_SHIFT (0U) #define RGB_TO_YUV_MAT2_CAM_R1C0(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT2_CAM_R1C0_SHIFT)) & RGB_TO_YUV_MAT2_CAM_R1C0_MASK) #define RGB_TO_YUV_MAT2_CAM_R1C1_MASK (0xFFFF0000U) #define RGB_TO_YUV_MAT2_CAM_R1C1_SHIFT (16U) #define RGB_TO_YUV_MAT2_CAM_R1C1(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT2_CAM_R1C1_SHIFT)) & RGB_TO_YUV_MAT2_CAM_R1C1_MASK) /*! @} */ /* The count of RGB_TO_YUV_MAT2_CAM */ #define RGB_TO_YUV_MAT2_CAM_COUNT (1U) /*! @name MAT3_CAM - Camera 0 CSC Matrix 3 Register */ /*! @{ */ #define RGB_TO_YUV_MAT3_CAM_R1C2_MASK (0xFFFFU) #define RGB_TO_YUV_MAT3_CAM_R1C2_SHIFT (0U) #define RGB_TO_YUV_MAT3_CAM_R1C2(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT3_CAM_R1C2_SHIFT)) & RGB_TO_YUV_MAT3_CAM_R1C2_MASK) /*! @} */ /* The count of RGB_TO_YUV_MAT3_CAM */ #define RGB_TO_YUV_MAT3_CAM_COUNT (1U) /*! @name MAT4_CAM - Camera 0 CSC Matrix 4 Register */ /*! @{ */ #define RGB_TO_YUV_MAT4_CAM_R2C0_MASK (0xFFFFU) #define RGB_TO_YUV_MAT4_CAM_R2C0_SHIFT (0U) #define RGB_TO_YUV_MAT4_CAM_R2C0(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT4_CAM_R2C0_SHIFT)) & RGB_TO_YUV_MAT4_CAM_R2C0_MASK) #define RGB_TO_YUV_MAT4_CAM_R2C1_MASK (0xFFFF0000U) #define RGB_TO_YUV_MAT4_CAM_R2C1_SHIFT (16U) #define RGB_TO_YUV_MAT4_CAM_R2C1(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT4_CAM_R2C1_SHIFT)) & RGB_TO_YUV_MAT4_CAM_R2C1_MASK) /*! @} */ /* The count of RGB_TO_YUV_MAT4_CAM */ #define RGB_TO_YUV_MAT4_CAM_COUNT (1U) /*! @name MAT5_CAM - Camera 0 CSC Matrix 5 Register */ /*! @{ */ #define RGB_TO_YUV_MAT5_CAM_R2C2_MASK (0xFFFFU) #define RGB_TO_YUV_MAT5_CAM_R2C2_SHIFT (0U) #define RGB_TO_YUV_MAT5_CAM_R2C2(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_MAT5_CAM_R2C2_SHIFT)) & RGB_TO_YUV_MAT5_CAM_R2C2_MASK) /*! @} */ /* The count of RGB_TO_YUV_MAT5_CAM */ #define RGB_TO_YUV_MAT5_CAM_COUNT (1U) /*! @name OFFSET0_CAM - Camera 0 CSC Offset 0 Register */ /*! @{ */ #define RGB_TO_YUV_OFFSET0_CAM_OFFSET_MASK (0x1FFFFFU) #define RGB_TO_YUV_OFFSET0_CAM_OFFSET_SHIFT (0U) #define RGB_TO_YUV_OFFSET0_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_OFFSET0_CAM_OFFSET_SHIFT)) & RGB_TO_YUV_OFFSET0_CAM_OFFSET_MASK) /*! @} */ /* The count of RGB_TO_YUV_OFFSET0_CAM */ #define RGB_TO_YUV_OFFSET0_CAM_COUNT (1U) /*! @name OFFSET1_CAM - Camera 0 CSC Offset 1 Register */ /*! @{ */ #define RGB_TO_YUV_OFFSET1_CAM_OFFSET_MASK (0x1FFFFFU) #define RGB_TO_YUV_OFFSET1_CAM_OFFSET_SHIFT (0U) #define RGB_TO_YUV_OFFSET1_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_OFFSET1_CAM_OFFSET_SHIFT)) & RGB_TO_YUV_OFFSET1_CAM_OFFSET_MASK) /*! @} */ /* The count of RGB_TO_YUV_OFFSET1_CAM */ #define RGB_TO_YUV_OFFSET1_CAM_COUNT (1U) /*! @name OFFSET2_CAM - Camera 0 CSC Offset 2 Register */ /*! @{ */ #define RGB_TO_YUV_OFFSET2_CAM_OFFSET_MASK (0x1FFFFFU) #define RGB_TO_YUV_OFFSET2_CAM_OFFSET_SHIFT (0U) #define RGB_TO_YUV_OFFSET2_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << RGB_TO_YUV_OFFSET2_CAM_OFFSET_SHIFT)) & RGB_TO_YUV_OFFSET2_CAM_OFFSET_MASK) /*! @} */ /* The count of RGB_TO_YUV_OFFSET2_CAM */ #define RGB_TO_YUV_OFFSET2_CAM_COUNT (1U) /*! * @} */ /* end of group RGB_TO_YUV_Register_Masks */ /* RGB_TO_YUV - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__RGB_TO_YUV base address */ #define CAMERA__ISP__RGB_TO_YUV_BASE (0x4AE011C0u) /** Peripheral CAMERA__ISP__RGB_TO_YUV base pointer */ #define CAMERA__ISP__RGB_TO_YUV ((RGB_TO_YUV_Type *)CAMERA__ISP__RGB_TO_YUV_BASE) /** Array initializer of RGB_TO_YUV peripheral base addresses */ #define RGB_TO_YUV_BASE_ADDRS { CAMERA__ISP__RGB_TO_YUV_BASE } /** Array initializer of RGB_TO_YUV peripheral base pointers */ #define RGB_TO_YUV_BASE_PTRS { CAMERA__ISP__RGB_TO_YUV } /*! * @} */ /* end of group RGB_TO_YUV_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RGPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer * @{ */ /** RGPIO - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[4]; __IO uint32_t LOCK; /**< Lock, offset: 0xC */ __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ uint8_t RESERVED_1[32]; __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ uint8_t RESERVED_2[4]; __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ uint8_t RESERVED_3[24]; __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ } RGPIO_Type; /* ---------------------------------------------------------------------------- -- RGPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RGPIO_Register_Masks RGPIO Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define RGPIO_VERID_FEATURE_MASK (0xFFFFU) #define RGPIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Basic implementation * 0b0000000000000001..Protection registers implemented */ #define RGPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_FEATURE_SHIFT)) & RGPIO_VERID_FEATURE_MASK) #define RGPIO_VERID_MINOR_MASK (0xFF0000U) #define RGPIO_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define RGPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MINOR_SHIFT)) & RGPIO_VERID_MINOR_MASK) #define RGPIO_VERID_MAJOR_MASK (0xFF000000U) #define RGPIO_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define RGPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_VERID_MAJOR_SHIFT)) & RGPIO_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define RGPIO_PARAM_IRQNUM_MASK (0xFU) #define RGPIO_PARAM_IRQNUM_SHIFT (0U) /*! IRQNUM - Interrupt Number */ #define RGPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PARAM_IRQNUM_SHIFT)) & RGPIO_PARAM_IRQNUM_MASK) /*! @} */ /*! @name LOCK - Lock */ /*! @{ */ #define RGPIO_LOCK_PCNS_MASK (0x1U) #define RGPIO_LOCK_PCNS_SHIFT (0U) /*! PCNS - Lock PCNS * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define RGPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNS_SHIFT)) & RGPIO_LOCK_PCNS_MASK) #define RGPIO_LOCK_ICNS_MASK (0x2U) #define RGPIO_LOCK_ICNS_SHIFT (1U) /*! ICNS - Lock ICNS * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define RGPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNS_SHIFT)) & RGPIO_LOCK_ICNS_MASK) #define RGPIO_LOCK_PCNP_MASK (0x4U) #define RGPIO_LOCK_PCNP_SHIFT (2U) /*! PCNP - Lock PCNP * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define RGPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_PCNP_SHIFT)) & RGPIO_LOCK_PCNP_MASK) #define RGPIO_LOCK_ICNP_MASK (0x8U) #define RGPIO_LOCK_ICNP_SHIFT (3U) /*! ICNP - Lock ICNP * 0b0..Writable in Secure-Privilege state * 0b1..Not writable until the next reset */ #define RGPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_LOCK_ICNP_SHIFT)) & RGPIO_LOCK_ICNP_MASK) /*! @} */ /*! @name PCNS - Pin Control Nonsecure */ /*! @{ */ #define RGPIO_PCNS_NSE0_MASK (0x1U) #define RGPIO_PCNS_NSE0_SHIFT (0U) /*! NSE0 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE0_SHIFT)) & RGPIO_PCNS_NSE0_MASK) #define RGPIO_PCNS_NSE1_MASK (0x2U) #define RGPIO_PCNS_NSE1_SHIFT (1U) /*! NSE1 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE1_SHIFT)) & RGPIO_PCNS_NSE1_MASK) #define RGPIO_PCNS_NSE2_MASK (0x4U) #define RGPIO_PCNS_NSE2_SHIFT (2U) /*! NSE2 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE2_SHIFT)) & RGPIO_PCNS_NSE2_MASK) #define RGPIO_PCNS_NSE3_MASK (0x8U) #define RGPIO_PCNS_NSE3_SHIFT (3U) /*! NSE3 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE3_SHIFT)) & RGPIO_PCNS_NSE3_MASK) #define RGPIO_PCNS_NSE4_MASK (0x10U) #define RGPIO_PCNS_NSE4_SHIFT (4U) /*! NSE4 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE4_SHIFT)) & RGPIO_PCNS_NSE4_MASK) #define RGPIO_PCNS_NSE5_MASK (0x20U) #define RGPIO_PCNS_NSE5_SHIFT (5U) /*! NSE5 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE5_SHIFT)) & RGPIO_PCNS_NSE5_MASK) #define RGPIO_PCNS_NSE6_MASK (0x40U) #define RGPIO_PCNS_NSE6_SHIFT (6U) /*! NSE6 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE6_SHIFT)) & RGPIO_PCNS_NSE6_MASK) #define RGPIO_PCNS_NSE7_MASK (0x80U) #define RGPIO_PCNS_NSE7_SHIFT (7U) /*! NSE7 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE7_SHIFT)) & RGPIO_PCNS_NSE7_MASK) #define RGPIO_PCNS_NSE8_MASK (0x100U) #define RGPIO_PCNS_NSE8_SHIFT (8U) /*! NSE8 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE8_SHIFT)) & RGPIO_PCNS_NSE8_MASK) #define RGPIO_PCNS_NSE9_MASK (0x200U) #define RGPIO_PCNS_NSE9_SHIFT (9U) /*! NSE9 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE9_SHIFT)) & RGPIO_PCNS_NSE9_MASK) #define RGPIO_PCNS_NSE10_MASK (0x400U) #define RGPIO_PCNS_NSE10_SHIFT (10U) /*! NSE10 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE10_SHIFT)) & RGPIO_PCNS_NSE10_MASK) #define RGPIO_PCNS_NSE11_MASK (0x800U) #define RGPIO_PCNS_NSE11_SHIFT (11U) /*! NSE11 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE11_SHIFT)) & RGPIO_PCNS_NSE11_MASK) #define RGPIO_PCNS_NSE12_MASK (0x1000U) #define RGPIO_PCNS_NSE12_SHIFT (12U) /*! NSE12 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE12_SHIFT)) & RGPIO_PCNS_NSE12_MASK) #define RGPIO_PCNS_NSE13_MASK (0x2000U) #define RGPIO_PCNS_NSE13_SHIFT (13U) /*! NSE13 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE13_SHIFT)) & RGPIO_PCNS_NSE13_MASK) #define RGPIO_PCNS_NSE14_MASK (0x4000U) #define RGPIO_PCNS_NSE14_SHIFT (14U) /*! NSE14 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE14_SHIFT)) & RGPIO_PCNS_NSE14_MASK) #define RGPIO_PCNS_NSE15_MASK (0x8000U) #define RGPIO_PCNS_NSE15_SHIFT (15U) /*! NSE15 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE15_SHIFT)) & RGPIO_PCNS_NSE15_MASK) #define RGPIO_PCNS_NSE16_MASK (0x10000U) #define RGPIO_PCNS_NSE16_SHIFT (16U) /*! NSE16 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE16_SHIFT)) & RGPIO_PCNS_NSE16_MASK) #define RGPIO_PCNS_NSE17_MASK (0x20000U) #define RGPIO_PCNS_NSE17_SHIFT (17U) /*! NSE17 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE17_SHIFT)) & RGPIO_PCNS_NSE17_MASK) #define RGPIO_PCNS_NSE18_MASK (0x40000U) #define RGPIO_PCNS_NSE18_SHIFT (18U) /*! NSE18 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE18_SHIFT)) & RGPIO_PCNS_NSE18_MASK) #define RGPIO_PCNS_NSE19_MASK (0x80000U) #define RGPIO_PCNS_NSE19_SHIFT (19U) /*! NSE19 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE19_SHIFT)) & RGPIO_PCNS_NSE19_MASK) #define RGPIO_PCNS_NSE20_MASK (0x100000U) #define RGPIO_PCNS_NSE20_SHIFT (20U) /*! NSE20 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE20_SHIFT)) & RGPIO_PCNS_NSE20_MASK) #define RGPIO_PCNS_NSE21_MASK (0x200000U) #define RGPIO_PCNS_NSE21_SHIFT (21U) /*! NSE21 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE21_SHIFT)) & RGPIO_PCNS_NSE21_MASK) #define RGPIO_PCNS_NSE22_MASK (0x400000U) #define RGPIO_PCNS_NSE22_SHIFT (22U) /*! NSE22 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE22_SHIFT)) & RGPIO_PCNS_NSE22_MASK) #define RGPIO_PCNS_NSE23_MASK (0x800000U) #define RGPIO_PCNS_NSE23_SHIFT (23U) /*! NSE23 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE23_SHIFT)) & RGPIO_PCNS_NSE23_MASK) #define RGPIO_PCNS_NSE24_MASK (0x1000000U) #define RGPIO_PCNS_NSE24_SHIFT (24U) /*! NSE24 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE24_SHIFT)) & RGPIO_PCNS_NSE24_MASK) #define RGPIO_PCNS_NSE25_MASK (0x2000000U) #define RGPIO_PCNS_NSE25_SHIFT (25U) /*! NSE25 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE25_SHIFT)) & RGPIO_PCNS_NSE25_MASK) #define RGPIO_PCNS_NSE26_MASK (0x4000000U) #define RGPIO_PCNS_NSE26_SHIFT (26U) /*! NSE26 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE26_SHIFT)) & RGPIO_PCNS_NSE26_MASK) #define RGPIO_PCNS_NSE27_MASK (0x8000000U) #define RGPIO_PCNS_NSE27_SHIFT (27U) /*! NSE27 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE27_SHIFT)) & RGPIO_PCNS_NSE27_MASK) #define RGPIO_PCNS_NSE28_MASK (0x10000000U) #define RGPIO_PCNS_NSE28_SHIFT (28U) /*! NSE28 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE28_SHIFT)) & RGPIO_PCNS_NSE28_MASK) #define RGPIO_PCNS_NSE29_MASK (0x20000000U) #define RGPIO_PCNS_NSE29_SHIFT (29U) /*! NSE29 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE29_SHIFT)) & RGPIO_PCNS_NSE29_MASK) #define RGPIO_PCNS_NSE30_MASK (0x40000000U) #define RGPIO_PCNS_NSE30_SHIFT (30U) /*! NSE30 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE30_SHIFT)) & RGPIO_PCNS_NSE30_MASK) #define RGPIO_PCNS_NSE31_MASK (0x80000000U) #define RGPIO_PCNS_NSE31_SHIFT (31U) /*! NSE31 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNS_NSE31_SHIFT)) & RGPIO_PCNS_NSE31_MASK) /*! @} */ /*! @name ICNS - Interrupt Control Nonsecure */ /*! @{ */ #define RGPIO_ICNS_NSE0_MASK (0x1U) #define RGPIO_ICNS_NSE0_SHIFT (0U) /*! NSE0 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE0_SHIFT)) & RGPIO_ICNS_NSE0_MASK) #define RGPIO_ICNS_NSE1_MASK (0x2U) #define RGPIO_ICNS_NSE1_SHIFT (1U) /*! NSE1 - Nonsecure Enable * 0b0..Secure access * 0b1..Nonsecure access */ #define RGPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNS_NSE1_SHIFT)) & RGPIO_ICNS_NSE1_MASK) /*! @} */ /*! @name PCNP - Pin Control Nonprivilege */ /*! @{ */ #define RGPIO_PCNP_NPE0_MASK (0x1U) #define RGPIO_PCNP_NPE0_SHIFT (0U) /*! NPE0 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE0_SHIFT)) & RGPIO_PCNP_NPE0_MASK) #define RGPIO_PCNP_NPE1_MASK (0x2U) #define RGPIO_PCNP_NPE1_SHIFT (1U) /*! NPE1 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE1_SHIFT)) & RGPIO_PCNP_NPE1_MASK) #define RGPIO_PCNP_NPE2_MASK (0x4U) #define RGPIO_PCNP_NPE2_SHIFT (2U) /*! NPE2 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE2_SHIFT)) & RGPIO_PCNP_NPE2_MASK) #define RGPIO_PCNP_NPE3_MASK (0x8U) #define RGPIO_PCNP_NPE3_SHIFT (3U) /*! NPE3 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE3_SHIFT)) & RGPIO_PCNP_NPE3_MASK) #define RGPIO_PCNP_NPE4_MASK (0x10U) #define RGPIO_PCNP_NPE4_SHIFT (4U) /*! NPE4 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE4_SHIFT)) & RGPIO_PCNP_NPE4_MASK) #define RGPIO_PCNP_NPE5_MASK (0x20U) #define RGPIO_PCNP_NPE5_SHIFT (5U) /*! NPE5 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE5_SHIFT)) & RGPIO_PCNP_NPE5_MASK) #define RGPIO_PCNP_NPE6_MASK (0x40U) #define RGPIO_PCNP_NPE6_SHIFT (6U) /*! NPE6 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE6_SHIFT)) & RGPIO_PCNP_NPE6_MASK) #define RGPIO_PCNP_NPE7_MASK (0x80U) #define RGPIO_PCNP_NPE7_SHIFT (7U) /*! NPE7 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE7_SHIFT)) & RGPIO_PCNP_NPE7_MASK) #define RGPIO_PCNP_NPE8_MASK (0x100U) #define RGPIO_PCNP_NPE8_SHIFT (8U) /*! NPE8 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE8_SHIFT)) & RGPIO_PCNP_NPE8_MASK) #define RGPIO_PCNP_NPE9_MASK (0x200U) #define RGPIO_PCNP_NPE9_SHIFT (9U) /*! NPE9 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE9_SHIFT)) & RGPIO_PCNP_NPE9_MASK) #define RGPIO_PCNP_NPE10_MASK (0x400U) #define RGPIO_PCNP_NPE10_SHIFT (10U) /*! NPE10 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE10_SHIFT)) & RGPIO_PCNP_NPE10_MASK) #define RGPIO_PCNP_NPE11_MASK (0x800U) #define RGPIO_PCNP_NPE11_SHIFT (11U) /*! NPE11 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE11_SHIFT)) & RGPIO_PCNP_NPE11_MASK) #define RGPIO_PCNP_NPE12_MASK (0x1000U) #define RGPIO_PCNP_NPE12_SHIFT (12U) /*! NPE12 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE12_SHIFT)) & RGPIO_PCNP_NPE12_MASK) #define RGPIO_PCNP_NPE13_MASK (0x2000U) #define RGPIO_PCNP_NPE13_SHIFT (13U) /*! NPE13 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE13_SHIFT)) & RGPIO_PCNP_NPE13_MASK) #define RGPIO_PCNP_NPE14_MASK (0x4000U) #define RGPIO_PCNP_NPE14_SHIFT (14U) /*! NPE14 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE14_SHIFT)) & RGPIO_PCNP_NPE14_MASK) #define RGPIO_PCNP_NPE15_MASK (0x8000U) #define RGPIO_PCNP_NPE15_SHIFT (15U) /*! NPE15 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE15_SHIFT)) & RGPIO_PCNP_NPE15_MASK) #define RGPIO_PCNP_NPE16_MASK (0x10000U) #define RGPIO_PCNP_NPE16_SHIFT (16U) /*! NPE16 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE16_SHIFT)) & RGPIO_PCNP_NPE16_MASK) #define RGPIO_PCNP_NPE17_MASK (0x20000U) #define RGPIO_PCNP_NPE17_SHIFT (17U) /*! NPE17 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE17_SHIFT)) & RGPIO_PCNP_NPE17_MASK) #define RGPIO_PCNP_NPE18_MASK (0x40000U) #define RGPIO_PCNP_NPE18_SHIFT (18U) /*! NPE18 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE18_SHIFT)) & RGPIO_PCNP_NPE18_MASK) #define RGPIO_PCNP_NPE19_MASK (0x80000U) #define RGPIO_PCNP_NPE19_SHIFT (19U) /*! NPE19 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE19_SHIFT)) & RGPIO_PCNP_NPE19_MASK) #define RGPIO_PCNP_NPE20_MASK (0x100000U) #define RGPIO_PCNP_NPE20_SHIFT (20U) /*! NPE20 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE20_SHIFT)) & RGPIO_PCNP_NPE20_MASK) #define RGPIO_PCNP_NPE21_MASK (0x200000U) #define RGPIO_PCNP_NPE21_SHIFT (21U) /*! NPE21 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE21_SHIFT)) & RGPIO_PCNP_NPE21_MASK) #define RGPIO_PCNP_NPE22_MASK (0x400000U) #define RGPIO_PCNP_NPE22_SHIFT (22U) /*! NPE22 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE22_SHIFT)) & RGPIO_PCNP_NPE22_MASK) #define RGPIO_PCNP_NPE23_MASK (0x800000U) #define RGPIO_PCNP_NPE23_SHIFT (23U) /*! NPE23 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE23_SHIFT)) & RGPIO_PCNP_NPE23_MASK) #define RGPIO_PCNP_NPE24_MASK (0x1000000U) #define RGPIO_PCNP_NPE24_SHIFT (24U) /*! NPE24 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE24_SHIFT)) & RGPIO_PCNP_NPE24_MASK) #define RGPIO_PCNP_NPE25_MASK (0x2000000U) #define RGPIO_PCNP_NPE25_SHIFT (25U) /*! NPE25 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE25_SHIFT)) & RGPIO_PCNP_NPE25_MASK) #define RGPIO_PCNP_NPE26_MASK (0x4000000U) #define RGPIO_PCNP_NPE26_SHIFT (26U) /*! NPE26 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE26_SHIFT)) & RGPIO_PCNP_NPE26_MASK) #define RGPIO_PCNP_NPE27_MASK (0x8000000U) #define RGPIO_PCNP_NPE27_SHIFT (27U) /*! NPE27 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE27_SHIFT)) & RGPIO_PCNP_NPE27_MASK) #define RGPIO_PCNP_NPE28_MASK (0x10000000U) #define RGPIO_PCNP_NPE28_SHIFT (28U) /*! NPE28 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE28_SHIFT)) & RGPIO_PCNP_NPE28_MASK) #define RGPIO_PCNP_NPE29_MASK (0x20000000U) #define RGPIO_PCNP_NPE29_SHIFT (29U) /*! NPE29 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE29_SHIFT)) & RGPIO_PCNP_NPE29_MASK) #define RGPIO_PCNP_NPE30_MASK (0x40000000U) #define RGPIO_PCNP_NPE30_SHIFT (30U) /*! NPE30 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE30_SHIFT)) & RGPIO_PCNP_NPE30_MASK) #define RGPIO_PCNP_NPE31_MASK (0x80000000U) #define RGPIO_PCNP_NPE31_SHIFT (31U) /*! NPE31 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCNP_NPE31_SHIFT)) & RGPIO_PCNP_NPE31_MASK) /*! @} */ /*! @name ICNP - Interrupt Control Nonprivilege */ /*! @{ */ #define RGPIO_ICNP_NPE0_MASK (0x1U) #define RGPIO_ICNP_NPE0_SHIFT (0U) /*! NPE0 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE0_SHIFT)) & RGPIO_ICNP_NPE0_MASK) #define RGPIO_ICNP_NPE1_MASK (0x2U) #define RGPIO_ICNP_NPE1_SHIFT (1U) /*! NPE1 - Nonprivilege Enable * 0b0..Privilege access * 0b1..Nonprivilege access */ #define RGPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICNP_NPE1_SHIFT)) & RGPIO_ICNP_NPE1_MASK) /*! @} */ /*! @name PDOR - Port Data Output */ /*! @{ */ #define RGPIO_PDOR_PDO0_MASK (0x1U) #define RGPIO_PDOR_PDO0_SHIFT (0U) /*! PDO0 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO0_SHIFT)) & RGPIO_PDOR_PDO0_MASK) #define RGPIO_PDOR_PDO1_MASK (0x2U) #define RGPIO_PDOR_PDO1_SHIFT (1U) /*! PDO1 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO1_SHIFT)) & RGPIO_PDOR_PDO1_MASK) #define RGPIO_PDOR_PDO2_MASK (0x4U) #define RGPIO_PDOR_PDO2_SHIFT (2U) /*! PDO2 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO2_SHIFT)) & RGPIO_PDOR_PDO2_MASK) #define RGPIO_PDOR_PDO3_MASK (0x8U) #define RGPIO_PDOR_PDO3_SHIFT (3U) /*! PDO3 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO3_SHIFT)) & RGPIO_PDOR_PDO3_MASK) #define RGPIO_PDOR_PDO4_MASK (0x10U) #define RGPIO_PDOR_PDO4_SHIFT (4U) /*! PDO4 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO4_SHIFT)) & RGPIO_PDOR_PDO4_MASK) #define RGPIO_PDOR_PDO5_MASK (0x20U) #define RGPIO_PDOR_PDO5_SHIFT (5U) /*! PDO5 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO5_SHIFT)) & RGPIO_PDOR_PDO5_MASK) #define RGPIO_PDOR_PDO6_MASK (0x40U) #define RGPIO_PDOR_PDO6_SHIFT (6U) /*! PDO6 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO6_SHIFT)) & RGPIO_PDOR_PDO6_MASK) #define RGPIO_PDOR_PDO7_MASK (0x80U) #define RGPIO_PDOR_PDO7_SHIFT (7U) /*! PDO7 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO7_SHIFT)) & RGPIO_PDOR_PDO7_MASK) #define RGPIO_PDOR_PDO8_MASK (0x100U) #define RGPIO_PDOR_PDO8_SHIFT (8U) /*! PDO8 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO8_SHIFT)) & RGPIO_PDOR_PDO8_MASK) #define RGPIO_PDOR_PDO9_MASK (0x200U) #define RGPIO_PDOR_PDO9_SHIFT (9U) /*! PDO9 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO9_SHIFT)) & RGPIO_PDOR_PDO9_MASK) #define RGPIO_PDOR_PDO10_MASK (0x400U) #define RGPIO_PDOR_PDO10_SHIFT (10U) /*! PDO10 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO10_SHIFT)) & RGPIO_PDOR_PDO10_MASK) #define RGPIO_PDOR_PDO11_MASK (0x800U) #define RGPIO_PDOR_PDO11_SHIFT (11U) /*! PDO11 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO11_SHIFT)) & RGPIO_PDOR_PDO11_MASK) #define RGPIO_PDOR_PDO12_MASK (0x1000U) #define RGPIO_PDOR_PDO12_SHIFT (12U) /*! PDO12 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO12_SHIFT)) & RGPIO_PDOR_PDO12_MASK) #define RGPIO_PDOR_PDO13_MASK (0x2000U) #define RGPIO_PDOR_PDO13_SHIFT (13U) /*! PDO13 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO13_SHIFT)) & RGPIO_PDOR_PDO13_MASK) #define RGPIO_PDOR_PDO14_MASK (0x4000U) #define RGPIO_PDOR_PDO14_SHIFT (14U) /*! PDO14 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO14_SHIFT)) & RGPIO_PDOR_PDO14_MASK) #define RGPIO_PDOR_PDO15_MASK (0x8000U) #define RGPIO_PDOR_PDO15_SHIFT (15U) /*! PDO15 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO15_SHIFT)) & RGPIO_PDOR_PDO15_MASK) #define RGPIO_PDOR_PDO16_MASK (0x10000U) #define RGPIO_PDOR_PDO16_SHIFT (16U) /*! PDO16 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO16_SHIFT)) & RGPIO_PDOR_PDO16_MASK) #define RGPIO_PDOR_PDO17_MASK (0x20000U) #define RGPIO_PDOR_PDO17_SHIFT (17U) /*! PDO17 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO17_SHIFT)) & RGPIO_PDOR_PDO17_MASK) #define RGPIO_PDOR_PDO18_MASK (0x40000U) #define RGPIO_PDOR_PDO18_SHIFT (18U) /*! PDO18 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO18_SHIFT)) & RGPIO_PDOR_PDO18_MASK) #define RGPIO_PDOR_PDO19_MASK (0x80000U) #define RGPIO_PDOR_PDO19_SHIFT (19U) /*! PDO19 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO19_SHIFT)) & RGPIO_PDOR_PDO19_MASK) #define RGPIO_PDOR_PDO20_MASK (0x100000U) #define RGPIO_PDOR_PDO20_SHIFT (20U) /*! PDO20 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO20_SHIFT)) & RGPIO_PDOR_PDO20_MASK) #define RGPIO_PDOR_PDO21_MASK (0x200000U) #define RGPIO_PDOR_PDO21_SHIFT (21U) /*! PDO21 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO21_SHIFT)) & RGPIO_PDOR_PDO21_MASK) #define RGPIO_PDOR_PDO22_MASK (0x400000U) #define RGPIO_PDOR_PDO22_SHIFT (22U) /*! PDO22 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO22_SHIFT)) & RGPIO_PDOR_PDO22_MASK) #define RGPIO_PDOR_PDO23_MASK (0x800000U) #define RGPIO_PDOR_PDO23_SHIFT (23U) /*! PDO23 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO23_SHIFT)) & RGPIO_PDOR_PDO23_MASK) #define RGPIO_PDOR_PDO24_MASK (0x1000000U) #define RGPIO_PDOR_PDO24_SHIFT (24U) /*! PDO24 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO24_SHIFT)) & RGPIO_PDOR_PDO24_MASK) #define RGPIO_PDOR_PDO25_MASK (0x2000000U) #define RGPIO_PDOR_PDO25_SHIFT (25U) /*! PDO25 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO25_SHIFT)) & RGPIO_PDOR_PDO25_MASK) #define RGPIO_PDOR_PDO26_MASK (0x4000000U) #define RGPIO_PDOR_PDO26_SHIFT (26U) /*! PDO26 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO26_SHIFT)) & RGPIO_PDOR_PDO26_MASK) #define RGPIO_PDOR_PDO27_MASK (0x8000000U) #define RGPIO_PDOR_PDO27_SHIFT (27U) /*! PDO27 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO27_SHIFT)) & RGPIO_PDOR_PDO27_MASK) #define RGPIO_PDOR_PDO28_MASK (0x10000000U) #define RGPIO_PDOR_PDO28_SHIFT (28U) /*! PDO28 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO28_SHIFT)) & RGPIO_PDOR_PDO28_MASK) #define RGPIO_PDOR_PDO29_MASK (0x20000000U) #define RGPIO_PDOR_PDO29_SHIFT (29U) /*! PDO29 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO29_SHIFT)) & RGPIO_PDOR_PDO29_MASK) #define RGPIO_PDOR_PDO30_MASK (0x40000000U) #define RGPIO_PDOR_PDO30_SHIFT (30U) /*! PDO30 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO30_SHIFT)) & RGPIO_PDOR_PDO30_MASK) #define RGPIO_PDOR_PDO31_MASK (0x80000000U) #define RGPIO_PDOR_PDO31_SHIFT (31U) /*! PDO31 - Port Data Output * 0b0..Logic level 0 * 0b1..Logic level 1 */ #define RGPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO31_SHIFT)) & RGPIO_PDOR_PDO31_MASK) /*! @} */ /*! @name PSOR - Port Set Output */ /*! @{ */ #define RGPIO_PSOR_PTSO0_MASK (0x1U) #define RGPIO_PSOR_PTSO0_SHIFT (0U) /*! PTSO0 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO0_SHIFT)) & RGPIO_PSOR_PTSO0_MASK) #define RGPIO_PSOR_PTSO1_MASK (0x2U) #define RGPIO_PSOR_PTSO1_SHIFT (1U) /*! PTSO1 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO1_SHIFT)) & RGPIO_PSOR_PTSO1_MASK) #define RGPIO_PSOR_PTSO2_MASK (0x4U) #define RGPIO_PSOR_PTSO2_SHIFT (2U) /*! PTSO2 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO2_SHIFT)) & RGPIO_PSOR_PTSO2_MASK) #define RGPIO_PSOR_PTSO3_MASK (0x8U) #define RGPIO_PSOR_PTSO3_SHIFT (3U) /*! PTSO3 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO3_SHIFT)) & RGPIO_PSOR_PTSO3_MASK) #define RGPIO_PSOR_PTSO4_MASK (0x10U) #define RGPIO_PSOR_PTSO4_SHIFT (4U) /*! PTSO4 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO4_SHIFT)) & RGPIO_PSOR_PTSO4_MASK) #define RGPIO_PSOR_PTSO5_MASK (0x20U) #define RGPIO_PSOR_PTSO5_SHIFT (5U) /*! PTSO5 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO5_SHIFT)) & RGPIO_PSOR_PTSO5_MASK) #define RGPIO_PSOR_PTSO6_MASK (0x40U) #define RGPIO_PSOR_PTSO6_SHIFT (6U) /*! PTSO6 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO6_SHIFT)) & RGPIO_PSOR_PTSO6_MASK) #define RGPIO_PSOR_PTSO7_MASK (0x80U) #define RGPIO_PSOR_PTSO7_SHIFT (7U) /*! PTSO7 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO7_SHIFT)) & RGPIO_PSOR_PTSO7_MASK) #define RGPIO_PSOR_PTSO8_MASK (0x100U) #define RGPIO_PSOR_PTSO8_SHIFT (8U) /*! PTSO8 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO8_SHIFT)) & RGPIO_PSOR_PTSO8_MASK) #define RGPIO_PSOR_PTSO9_MASK (0x200U) #define RGPIO_PSOR_PTSO9_SHIFT (9U) /*! PTSO9 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO9_SHIFT)) & RGPIO_PSOR_PTSO9_MASK) #define RGPIO_PSOR_PTSO10_MASK (0x400U) #define RGPIO_PSOR_PTSO10_SHIFT (10U) /*! PTSO10 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO10_SHIFT)) & RGPIO_PSOR_PTSO10_MASK) #define RGPIO_PSOR_PTSO11_MASK (0x800U) #define RGPIO_PSOR_PTSO11_SHIFT (11U) /*! PTSO11 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO11_SHIFT)) & RGPIO_PSOR_PTSO11_MASK) #define RGPIO_PSOR_PTSO12_MASK (0x1000U) #define RGPIO_PSOR_PTSO12_SHIFT (12U) /*! PTSO12 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO12_SHIFT)) & RGPIO_PSOR_PTSO12_MASK) #define RGPIO_PSOR_PTSO13_MASK (0x2000U) #define RGPIO_PSOR_PTSO13_SHIFT (13U) /*! PTSO13 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO13_SHIFT)) & RGPIO_PSOR_PTSO13_MASK) #define RGPIO_PSOR_PTSO14_MASK (0x4000U) #define RGPIO_PSOR_PTSO14_SHIFT (14U) /*! PTSO14 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO14_SHIFT)) & RGPIO_PSOR_PTSO14_MASK) #define RGPIO_PSOR_PTSO15_MASK (0x8000U) #define RGPIO_PSOR_PTSO15_SHIFT (15U) /*! PTSO15 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO15_SHIFT)) & RGPIO_PSOR_PTSO15_MASK) #define RGPIO_PSOR_PTSO16_MASK (0x10000U) #define RGPIO_PSOR_PTSO16_SHIFT (16U) /*! PTSO16 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO16_SHIFT)) & RGPIO_PSOR_PTSO16_MASK) #define RGPIO_PSOR_PTSO17_MASK (0x20000U) #define RGPIO_PSOR_PTSO17_SHIFT (17U) /*! PTSO17 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO17_SHIFT)) & RGPIO_PSOR_PTSO17_MASK) #define RGPIO_PSOR_PTSO18_MASK (0x40000U) #define RGPIO_PSOR_PTSO18_SHIFT (18U) /*! PTSO18 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO18_SHIFT)) & RGPIO_PSOR_PTSO18_MASK) #define RGPIO_PSOR_PTSO19_MASK (0x80000U) #define RGPIO_PSOR_PTSO19_SHIFT (19U) /*! PTSO19 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO19_SHIFT)) & RGPIO_PSOR_PTSO19_MASK) #define RGPIO_PSOR_PTSO20_MASK (0x100000U) #define RGPIO_PSOR_PTSO20_SHIFT (20U) /*! PTSO20 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO20_SHIFT)) & RGPIO_PSOR_PTSO20_MASK) #define RGPIO_PSOR_PTSO21_MASK (0x200000U) #define RGPIO_PSOR_PTSO21_SHIFT (21U) /*! PTSO21 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO21_SHIFT)) & RGPIO_PSOR_PTSO21_MASK) #define RGPIO_PSOR_PTSO22_MASK (0x400000U) #define RGPIO_PSOR_PTSO22_SHIFT (22U) /*! PTSO22 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO22_SHIFT)) & RGPIO_PSOR_PTSO22_MASK) #define RGPIO_PSOR_PTSO23_MASK (0x800000U) #define RGPIO_PSOR_PTSO23_SHIFT (23U) /*! PTSO23 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO23_SHIFT)) & RGPIO_PSOR_PTSO23_MASK) #define RGPIO_PSOR_PTSO24_MASK (0x1000000U) #define RGPIO_PSOR_PTSO24_SHIFT (24U) /*! PTSO24 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO24_SHIFT)) & RGPIO_PSOR_PTSO24_MASK) #define RGPIO_PSOR_PTSO25_MASK (0x2000000U) #define RGPIO_PSOR_PTSO25_SHIFT (25U) /*! PTSO25 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO25_SHIFT)) & RGPIO_PSOR_PTSO25_MASK) #define RGPIO_PSOR_PTSO26_MASK (0x4000000U) #define RGPIO_PSOR_PTSO26_SHIFT (26U) /*! PTSO26 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO26_SHIFT)) & RGPIO_PSOR_PTSO26_MASK) #define RGPIO_PSOR_PTSO27_MASK (0x8000000U) #define RGPIO_PSOR_PTSO27_SHIFT (27U) /*! PTSO27 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO27_SHIFT)) & RGPIO_PSOR_PTSO27_MASK) #define RGPIO_PSOR_PTSO28_MASK (0x10000000U) #define RGPIO_PSOR_PTSO28_SHIFT (28U) /*! PTSO28 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO28_SHIFT)) & RGPIO_PSOR_PTSO28_MASK) #define RGPIO_PSOR_PTSO29_MASK (0x20000000U) #define RGPIO_PSOR_PTSO29_SHIFT (29U) /*! PTSO29 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO29_SHIFT)) & RGPIO_PSOR_PTSO29_MASK) #define RGPIO_PSOR_PTSO30_MASK (0x40000000U) #define RGPIO_PSOR_PTSO30_SHIFT (30U) /*! PTSO30 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO30_SHIFT)) & RGPIO_PSOR_PTSO30_MASK) #define RGPIO_PSOR_PTSO31_MASK (0x80000000U) #define RGPIO_PSOR_PTSO31_SHIFT (31U) /*! PTSO31 - Port Set Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 1 */ #define RGPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO31_SHIFT)) & RGPIO_PSOR_PTSO31_MASK) /*! @} */ /*! @name PCOR - Port Clear Output */ /*! @{ */ #define RGPIO_PCOR_PTCO0_MASK (0x1U) #define RGPIO_PCOR_PTCO0_SHIFT (0U) /*! PTCO0 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO0_SHIFT)) & RGPIO_PCOR_PTCO0_MASK) #define RGPIO_PCOR_PTCO1_MASK (0x2U) #define RGPIO_PCOR_PTCO1_SHIFT (1U) /*! PTCO1 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO1_SHIFT)) & RGPIO_PCOR_PTCO1_MASK) #define RGPIO_PCOR_PTCO2_MASK (0x4U) #define RGPIO_PCOR_PTCO2_SHIFT (2U) /*! PTCO2 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO2_SHIFT)) & RGPIO_PCOR_PTCO2_MASK) #define RGPIO_PCOR_PTCO3_MASK (0x8U) #define RGPIO_PCOR_PTCO3_SHIFT (3U) /*! PTCO3 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO3_SHIFT)) & RGPIO_PCOR_PTCO3_MASK) #define RGPIO_PCOR_PTCO4_MASK (0x10U) #define RGPIO_PCOR_PTCO4_SHIFT (4U) /*! PTCO4 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO4_SHIFT)) & RGPIO_PCOR_PTCO4_MASK) #define RGPIO_PCOR_PTCO5_MASK (0x20U) #define RGPIO_PCOR_PTCO5_SHIFT (5U) /*! PTCO5 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO5_SHIFT)) & RGPIO_PCOR_PTCO5_MASK) #define RGPIO_PCOR_PTCO6_MASK (0x40U) #define RGPIO_PCOR_PTCO6_SHIFT (6U) /*! PTCO6 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO6_SHIFT)) & RGPIO_PCOR_PTCO6_MASK) #define RGPIO_PCOR_PTCO7_MASK (0x80U) #define RGPIO_PCOR_PTCO7_SHIFT (7U) /*! PTCO7 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO7_SHIFT)) & RGPIO_PCOR_PTCO7_MASK) #define RGPIO_PCOR_PTCO8_MASK (0x100U) #define RGPIO_PCOR_PTCO8_SHIFT (8U) /*! PTCO8 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO8_SHIFT)) & RGPIO_PCOR_PTCO8_MASK) #define RGPIO_PCOR_PTCO9_MASK (0x200U) #define RGPIO_PCOR_PTCO9_SHIFT (9U) /*! PTCO9 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO9_SHIFT)) & RGPIO_PCOR_PTCO9_MASK) #define RGPIO_PCOR_PTCO10_MASK (0x400U) #define RGPIO_PCOR_PTCO10_SHIFT (10U) /*! PTCO10 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO10_SHIFT)) & RGPIO_PCOR_PTCO10_MASK) #define RGPIO_PCOR_PTCO11_MASK (0x800U) #define RGPIO_PCOR_PTCO11_SHIFT (11U) /*! PTCO11 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO11_SHIFT)) & RGPIO_PCOR_PTCO11_MASK) #define RGPIO_PCOR_PTCO12_MASK (0x1000U) #define RGPIO_PCOR_PTCO12_SHIFT (12U) /*! PTCO12 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO12_SHIFT)) & RGPIO_PCOR_PTCO12_MASK) #define RGPIO_PCOR_PTCO13_MASK (0x2000U) #define RGPIO_PCOR_PTCO13_SHIFT (13U) /*! PTCO13 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO13_SHIFT)) & RGPIO_PCOR_PTCO13_MASK) #define RGPIO_PCOR_PTCO14_MASK (0x4000U) #define RGPIO_PCOR_PTCO14_SHIFT (14U) /*! PTCO14 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO14_SHIFT)) & RGPIO_PCOR_PTCO14_MASK) #define RGPIO_PCOR_PTCO15_MASK (0x8000U) #define RGPIO_PCOR_PTCO15_SHIFT (15U) /*! PTCO15 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO15_SHIFT)) & RGPIO_PCOR_PTCO15_MASK) #define RGPIO_PCOR_PTCO16_MASK (0x10000U) #define RGPIO_PCOR_PTCO16_SHIFT (16U) /*! PTCO16 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO16_SHIFT)) & RGPIO_PCOR_PTCO16_MASK) #define RGPIO_PCOR_PTCO17_MASK (0x20000U) #define RGPIO_PCOR_PTCO17_SHIFT (17U) /*! PTCO17 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO17_SHIFT)) & RGPIO_PCOR_PTCO17_MASK) #define RGPIO_PCOR_PTCO18_MASK (0x40000U) #define RGPIO_PCOR_PTCO18_SHIFT (18U) /*! PTCO18 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO18_SHIFT)) & RGPIO_PCOR_PTCO18_MASK) #define RGPIO_PCOR_PTCO19_MASK (0x80000U) #define RGPIO_PCOR_PTCO19_SHIFT (19U) /*! PTCO19 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO19_SHIFT)) & RGPIO_PCOR_PTCO19_MASK) #define RGPIO_PCOR_PTCO20_MASK (0x100000U) #define RGPIO_PCOR_PTCO20_SHIFT (20U) /*! PTCO20 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO20_SHIFT)) & RGPIO_PCOR_PTCO20_MASK) #define RGPIO_PCOR_PTCO21_MASK (0x200000U) #define RGPIO_PCOR_PTCO21_SHIFT (21U) /*! PTCO21 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO21_SHIFT)) & RGPIO_PCOR_PTCO21_MASK) #define RGPIO_PCOR_PTCO22_MASK (0x400000U) #define RGPIO_PCOR_PTCO22_SHIFT (22U) /*! PTCO22 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO22_SHIFT)) & RGPIO_PCOR_PTCO22_MASK) #define RGPIO_PCOR_PTCO23_MASK (0x800000U) #define RGPIO_PCOR_PTCO23_SHIFT (23U) /*! PTCO23 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO23_SHIFT)) & RGPIO_PCOR_PTCO23_MASK) #define RGPIO_PCOR_PTCO24_MASK (0x1000000U) #define RGPIO_PCOR_PTCO24_SHIFT (24U) /*! PTCO24 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO24_SHIFT)) & RGPIO_PCOR_PTCO24_MASK) #define RGPIO_PCOR_PTCO25_MASK (0x2000000U) #define RGPIO_PCOR_PTCO25_SHIFT (25U) /*! PTCO25 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO25_SHIFT)) & RGPIO_PCOR_PTCO25_MASK) #define RGPIO_PCOR_PTCO26_MASK (0x4000000U) #define RGPIO_PCOR_PTCO26_SHIFT (26U) /*! PTCO26 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO26_SHIFT)) & RGPIO_PCOR_PTCO26_MASK) #define RGPIO_PCOR_PTCO27_MASK (0x8000000U) #define RGPIO_PCOR_PTCO27_SHIFT (27U) /*! PTCO27 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO27_SHIFT)) & RGPIO_PCOR_PTCO27_MASK) #define RGPIO_PCOR_PTCO28_MASK (0x10000000U) #define RGPIO_PCOR_PTCO28_SHIFT (28U) /*! PTCO28 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO28_SHIFT)) & RGPIO_PCOR_PTCO28_MASK) #define RGPIO_PCOR_PTCO29_MASK (0x20000000U) #define RGPIO_PCOR_PTCO29_SHIFT (29U) /*! PTCO29 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO29_SHIFT)) & RGPIO_PCOR_PTCO29_MASK) #define RGPIO_PCOR_PTCO30_MASK (0x40000000U) #define RGPIO_PCOR_PTCO30_SHIFT (30U) /*! PTCO30 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO30_SHIFT)) & RGPIO_PCOR_PTCO30_MASK) #define RGPIO_PCOR_PTCO31_MASK (0x80000000U) #define RGPIO_PCOR_PTCO31_SHIFT (31U) /*! PTCO31 - Port Clear Output * 0b0..No change * 0b1..Corresponding field in PDOR becomes 0 */ #define RGPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO31_SHIFT)) & RGPIO_PCOR_PTCO31_MASK) /*! @} */ /*! @name PTOR - Port Toggle Output */ /*! @{ */ #define RGPIO_PTOR_PTTO0_MASK (0x1U) #define RGPIO_PTOR_PTTO0_SHIFT (0U) /*! PTTO0 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO0_SHIFT)) & RGPIO_PTOR_PTTO0_MASK) #define RGPIO_PTOR_PTTO1_MASK (0x2U) #define RGPIO_PTOR_PTTO1_SHIFT (1U) /*! PTTO1 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO1_SHIFT)) & RGPIO_PTOR_PTTO1_MASK) #define RGPIO_PTOR_PTTO2_MASK (0x4U) #define RGPIO_PTOR_PTTO2_SHIFT (2U) /*! PTTO2 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO2_SHIFT)) & RGPIO_PTOR_PTTO2_MASK) #define RGPIO_PTOR_PTTO3_MASK (0x8U) #define RGPIO_PTOR_PTTO3_SHIFT (3U) /*! PTTO3 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO3_SHIFT)) & RGPIO_PTOR_PTTO3_MASK) #define RGPIO_PTOR_PTTO4_MASK (0x10U) #define RGPIO_PTOR_PTTO4_SHIFT (4U) /*! PTTO4 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO4_SHIFT)) & RGPIO_PTOR_PTTO4_MASK) #define RGPIO_PTOR_PTTO5_MASK (0x20U) #define RGPIO_PTOR_PTTO5_SHIFT (5U) /*! PTTO5 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO5_SHIFT)) & RGPIO_PTOR_PTTO5_MASK) #define RGPIO_PTOR_PTTO6_MASK (0x40U) #define RGPIO_PTOR_PTTO6_SHIFT (6U) /*! PTTO6 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO6_SHIFT)) & RGPIO_PTOR_PTTO6_MASK) #define RGPIO_PTOR_PTTO7_MASK (0x80U) #define RGPIO_PTOR_PTTO7_SHIFT (7U) /*! PTTO7 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO7_SHIFT)) & RGPIO_PTOR_PTTO7_MASK) #define RGPIO_PTOR_PTTO8_MASK (0x100U) #define RGPIO_PTOR_PTTO8_SHIFT (8U) /*! PTTO8 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO8_SHIFT)) & RGPIO_PTOR_PTTO8_MASK) #define RGPIO_PTOR_PTTO9_MASK (0x200U) #define RGPIO_PTOR_PTTO9_SHIFT (9U) /*! PTTO9 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO9_SHIFT)) & RGPIO_PTOR_PTTO9_MASK) #define RGPIO_PTOR_PTTO10_MASK (0x400U) #define RGPIO_PTOR_PTTO10_SHIFT (10U) /*! PTTO10 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO10_SHIFT)) & RGPIO_PTOR_PTTO10_MASK) #define RGPIO_PTOR_PTTO11_MASK (0x800U) #define RGPIO_PTOR_PTTO11_SHIFT (11U) /*! PTTO11 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO11_SHIFT)) & RGPIO_PTOR_PTTO11_MASK) #define RGPIO_PTOR_PTTO12_MASK (0x1000U) #define RGPIO_PTOR_PTTO12_SHIFT (12U) /*! PTTO12 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO12_SHIFT)) & RGPIO_PTOR_PTTO12_MASK) #define RGPIO_PTOR_PTTO13_MASK (0x2000U) #define RGPIO_PTOR_PTTO13_SHIFT (13U) /*! PTTO13 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO13_SHIFT)) & RGPIO_PTOR_PTTO13_MASK) #define RGPIO_PTOR_PTTO14_MASK (0x4000U) #define RGPIO_PTOR_PTTO14_SHIFT (14U) /*! PTTO14 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO14_SHIFT)) & RGPIO_PTOR_PTTO14_MASK) #define RGPIO_PTOR_PTTO15_MASK (0x8000U) #define RGPIO_PTOR_PTTO15_SHIFT (15U) /*! PTTO15 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO15_SHIFT)) & RGPIO_PTOR_PTTO15_MASK) #define RGPIO_PTOR_PTTO16_MASK (0x10000U) #define RGPIO_PTOR_PTTO16_SHIFT (16U) /*! PTTO16 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO16_SHIFT)) & RGPIO_PTOR_PTTO16_MASK) #define RGPIO_PTOR_PTTO17_MASK (0x20000U) #define RGPIO_PTOR_PTTO17_SHIFT (17U) /*! PTTO17 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO17_SHIFT)) & RGPIO_PTOR_PTTO17_MASK) #define RGPIO_PTOR_PTTO18_MASK (0x40000U) #define RGPIO_PTOR_PTTO18_SHIFT (18U) /*! PTTO18 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO18_SHIFT)) & RGPIO_PTOR_PTTO18_MASK) #define RGPIO_PTOR_PTTO19_MASK (0x80000U) #define RGPIO_PTOR_PTTO19_SHIFT (19U) /*! PTTO19 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO19_SHIFT)) & RGPIO_PTOR_PTTO19_MASK) #define RGPIO_PTOR_PTTO20_MASK (0x100000U) #define RGPIO_PTOR_PTTO20_SHIFT (20U) /*! PTTO20 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO20_SHIFT)) & RGPIO_PTOR_PTTO20_MASK) #define RGPIO_PTOR_PTTO21_MASK (0x200000U) #define RGPIO_PTOR_PTTO21_SHIFT (21U) /*! PTTO21 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO21_SHIFT)) & RGPIO_PTOR_PTTO21_MASK) #define RGPIO_PTOR_PTTO22_MASK (0x400000U) #define RGPIO_PTOR_PTTO22_SHIFT (22U) /*! PTTO22 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO22_SHIFT)) & RGPIO_PTOR_PTTO22_MASK) #define RGPIO_PTOR_PTTO23_MASK (0x800000U) #define RGPIO_PTOR_PTTO23_SHIFT (23U) /*! PTTO23 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO23_SHIFT)) & RGPIO_PTOR_PTTO23_MASK) #define RGPIO_PTOR_PTTO24_MASK (0x1000000U) #define RGPIO_PTOR_PTTO24_SHIFT (24U) /*! PTTO24 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO24_SHIFT)) & RGPIO_PTOR_PTTO24_MASK) #define RGPIO_PTOR_PTTO25_MASK (0x2000000U) #define RGPIO_PTOR_PTTO25_SHIFT (25U) /*! PTTO25 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO25_SHIFT)) & RGPIO_PTOR_PTTO25_MASK) #define RGPIO_PTOR_PTTO26_MASK (0x4000000U) #define RGPIO_PTOR_PTTO26_SHIFT (26U) /*! PTTO26 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO26_SHIFT)) & RGPIO_PTOR_PTTO26_MASK) #define RGPIO_PTOR_PTTO27_MASK (0x8000000U) #define RGPIO_PTOR_PTTO27_SHIFT (27U) /*! PTTO27 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO27_SHIFT)) & RGPIO_PTOR_PTTO27_MASK) #define RGPIO_PTOR_PTTO28_MASK (0x10000000U) #define RGPIO_PTOR_PTTO28_SHIFT (28U) /*! PTTO28 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO28_SHIFT)) & RGPIO_PTOR_PTTO28_MASK) #define RGPIO_PTOR_PTTO29_MASK (0x20000000U) #define RGPIO_PTOR_PTTO29_SHIFT (29U) /*! PTTO29 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO29_SHIFT)) & RGPIO_PTOR_PTTO29_MASK) #define RGPIO_PTOR_PTTO30_MASK (0x40000000U) #define RGPIO_PTOR_PTTO30_SHIFT (30U) /*! PTTO30 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO30_SHIFT)) & RGPIO_PTOR_PTTO30_MASK) #define RGPIO_PTOR_PTTO31_MASK (0x80000000U) #define RGPIO_PTOR_PTTO31_SHIFT (31U) /*! PTTO31 - Port Toggle Output * 0b0..No change * 0b1..Set to the inverse of its current logic state */ #define RGPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO31_SHIFT)) & RGPIO_PTOR_PTTO31_MASK) /*! @} */ /*! @name PDIR - Port Data Input */ /*! @{ */ #define RGPIO_PDIR_PDI0_MASK (0x1U) #define RGPIO_PDIR_PDI0_SHIFT (0U) /*! PDI0 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI0_SHIFT)) & RGPIO_PDIR_PDI0_MASK) #define RGPIO_PDIR_PDI1_MASK (0x2U) #define RGPIO_PDIR_PDI1_SHIFT (1U) /*! PDI1 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI1_SHIFT)) & RGPIO_PDIR_PDI1_MASK) #define RGPIO_PDIR_PDI2_MASK (0x4U) #define RGPIO_PDIR_PDI2_SHIFT (2U) /*! PDI2 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI2_SHIFT)) & RGPIO_PDIR_PDI2_MASK) #define RGPIO_PDIR_PDI3_MASK (0x8U) #define RGPIO_PDIR_PDI3_SHIFT (3U) /*! PDI3 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI3_SHIFT)) & RGPIO_PDIR_PDI3_MASK) #define RGPIO_PDIR_PDI4_MASK (0x10U) #define RGPIO_PDIR_PDI4_SHIFT (4U) /*! PDI4 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI4_SHIFT)) & RGPIO_PDIR_PDI4_MASK) #define RGPIO_PDIR_PDI5_MASK (0x20U) #define RGPIO_PDIR_PDI5_SHIFT (5U) /*! PDI5 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI5_SHIFT)) & RGPIO_PDIR_PDI5_MASK) #define RGPIO_PDIR_PDI6_MASK (0x40U) #define RGPIO_PDIR_PDI6_SHIFT (6U) /*! PDI6 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI6_SHIFT)) & RGPIO_PDIR_PDI6_MASK) #define RGPIO_PDIR_PDI7_MASK (0x80U) #define RGPIO_PDIR_PDI7_SHIFT (7U) /*! PDI7 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI7_SHIFT)) & RGPIO_PDIR_PDI7_MASK) #define RGPIO_PDIR_PDI8_MASK (0x100U) #define RGPIO_PDIR_PDI8_SHIFT (8U) /*! PDI8 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI8_SHIFT)) & RGPIO_PDIR_PDI8_MASK) #define RGPIO_PDIR_PDI9_MASK (0x200U) #define RGPIO_PDIR_PDI9_SHIFT (9U) /*! PDI9 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI9_SHIFT)) & RGPIO_PDIR_PDI9_MASK) #define RGPIO_PDIR_PDI10_MASK (0x400U) #define RGPIO_PDIR_PDI10_SHIFT (10U) /*! PDI10 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI10_SHIFT)) & RGPIO_PDIR_PDI10_MASK) #define RGPIO_PDIR_PDI11_MASK (0x800U) #define RGPIO_PDIR_PDI11_SHIFT (11U) /*! PDI11 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI11_SHIFT)) & RGPIO_PDIR_PDI11_MASK) #define RGPIO_PDIR_PDI12_MASK (0x1000U) #define RGPIO_PDIR_PDI12_SHIFT (12U) /*! PDI12 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI12_SHIFT)) & RGPIO_PDIR_PDI12_MASK) #define RGPIO_PDIR_PDI13_MASK (0x2000U) #define RGPIO_PDIR_PDI13_SHIFT (13U) /*! PDI13 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI13_SHIFT)) & RGPIO_PDIR_PDI13_MASK) #define RGPIO_PDIR_PDI14_MASK (0x4000U) #define RGPIO_PDIR_PDI14_SHIFT (14U) /*! PDI14 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI14_SHIFT)) & RGPIO_PDIR_PDI14_MASK) #define RGPIO_PDIR_PDI15_MASK (0x8000U) #define RGPIO_PDIR_PDI15_SHIFT (15U) /*! PDI15 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI15_SHIFT)) & RGPIO_PDIR_PDI15_MASK) #define RGPIO_PDIR_PDI16_MASK (0x10000U) #define RGPIO_PDIR_PDI16_SHIFT (16U) /*! PDI16 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI16_SHIFT)) & RGPIO_PDIR_PDI16_MASK) #define RGPIO_PDIR_PDI17_MASK (0x20000U) #define RGPIO_PDIR_PDI17_SHIFT (17U) /*! PDI17 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI17_SHIFT)) & RGPIO_PDIR_PDI17_MASK) #define RGPIO_PDIR_PDI18_MASK (0x40000U) #define RGPIO_PDIR_PDI18_SHIFT (18U) /*! PDI18 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI18_SHIFT)) & RGPIO_PDIR_PDI18_MASK) #define RGPIO_PDIR_PDI19_MASK (0x80000U) #define RGPIO_PDIR_PDI19_SHIFT (19U) /*! PDI19 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI19_SHIFT)) & RGPIO_PDIR_PDI19_MASK) #define RGPIO_PDIR_PDI20_MASK (0x100000U) #define RGPIO_PDIR_PDI20_SHIFT (20U) /*! PDI20 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI20_SHIFT)) & RGPIO_PDIR_PDI20_MASK) #define RGPIO_PDIR_PDI21_MASK (0x200000U) #define RGPIO_PDIR_PDI21_SHIFT (21U) /*! PDI21 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI21_SHIFT)) & RGPIO_PDIR_PDI21_MASK) #define RGPIO_PDIR_PDI22_MASK (0x400000U) #define RGPIO_PDIR_PDI22_SHIFT (22U) /*! PDI22 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI22_SHIFT)) & RGPIO_PDIR_PDI22_MASK) #define RGPIO_PDIR_PDI23_MASK (0x800000U) #define RGPIO_PDIR_PDI23_SHIFT (23U) /*! PDI23 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI23_SHIFT)) & RGPIO_PDIR_PDI23_MASK) #define RGPIO_PDIR_PDI24_MASK (0x1000000U) #define RGPIO_PDIR_PDI24_SHIFT (24U) /*! PDI24 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI24_SHIFT)) & RGPIO_PDIR_PDI24_MASK) #define RGPIO_PDIR_PDI25_MASK (0x2000000U) #define RGPIO_PDIR_PDI25_SHIFT (25U) /*! PDI25 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI25_SHIFT)) & RGPIO_PDIR_PDI25_MASK) #define RGPIO_PDIR_PDI26_MASK (0x4000000U) #define RGPIO_PDIR_PDI26_SHIFT (26U) /*! PDI26 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI26_SHIFT)) & RGPIO_PDIR_PDI26_MASK) #define RGPIO_PDIR_PDI27_MASK (0x8000000U) #define RGPIO_PDIR_PDI27_SHIFT (27U) /*! PDI27 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI27_SHIFT)) & RGPIO_PDIR_PDI27_MASK) #define RGPIO_PDIR_PDI28_MASK (0x10000000U) #define RGPIO_PDIR_PDI28_SHIFT (28U) /*! PDI28 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI28_SHIFT)) & RGPIO_PDIR_PDI28_MASK) #define RGPIO_PDIR_PDI29_MASK (0x20000000U) #define RGPIO_PDIR_PDI29_SHIFT (29U) /*! PDI29 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI29_SHIFT)) & RGPIO_PDIR_PDI29_MASK) #define RGPIO_PDIR_PDI30_MASK (0x40000000U) #define RGPIO_PDIR_PDI30_SHIFT (30U) /*! PDI30 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI30_SHIFT)) & RGPIO_PDIR_PDI30_MASK) #define RGPIO_PDIR_PDI31_MASK (0x80000000U) #define RGPIO_PDIR_PDI31_SHIFT (31U) /*! PDI31 - Port Data Input * 0b0..Logic 0 * 0b1..Logic 1 */ #define RGPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI31_SHIFT)) & RGPIO_PDIR_PDI31_MASK) /*! @} */ /*! @name PDDR - Port Data Direction */ /*! @{ */ #define RGPIO_PDDR_PDD0_MASK (0x1U) #define RGPIO_PDDR_PDD0_SHIFT (0U) /*! PDD0 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD0_SHIFT)) & RGPIO_PDDR_PDD0_MASK) #define RGPIO_PDDR_PDD1_MASK (0x2U) #define RGPIO_PDDR_PDD1_SHIFT (1U) /*! PDD1 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD1_SHIFT)) & RGPIO_PDDR_PDD1_MASK) #define RGPIO_PDDR_PDD2_MASK (0x4U) #define RGPIO_PDDR_PDD2_SHIFT (2U) /*! PDD2 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD2_SHIFT)) & RGPIO_PDDR_PDD2_MASK) #define RGPIO_PDDR_PDD3_MASK (0x8U) #define RGPIO_PDDR_PDD3_SHIFT (3U) /*! PDD3 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD3_SHIFT)) & RGPIO_PDDR_PDD3_MASK) #define RGPIO_PDDR_PDD4_MASK (0x10U) #define RGPIO_PDDR_PDD4_SHIFT (4U) /*! PDD4 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD4_SHIFT)) & RGPIO_PDDR_PDD4_MASK) #define RGPIO_PDDR_PDD5_MASK (0x20U) #define RGPIO_PDDR_PDD5_SHIFT (5U) /*! PDD5 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD5_SHIFT)) & RGPIO_PDDR_PDD5_MASK) #define RGPIO_PDDR_PDD6_MASK (0x40U) #define RGPIO_PDDR_PDD6_SHIFT (6U) /*! PDD6 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD6_SHIFT)) & RGPIO_PDDR_PDD6_MASK) #define RGPIO_PDDR_PDD7_MASK (0x80U) #define RGPIO_PDDR_PDD7_SHIFT (7U) /*! PDD7 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD7_SHIFT)) & RGPIO_PDDR_PDD7_MASK) #define RGPIO_PDDR_PDD8_MASK (0x100U) #define RGPIO_PDDR_PDD8_SHIFT (8U) /*! PDD8 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD8_SHIFT)) & RGPIO_PDDR_PDD8_MASK) #define RGPIO_PDDR_PDD9_MASK (0x200U) #define RGPIO_PDDR_PDD9_SHIFT (9U) /*! PDD9 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD9_SHIFT)) & RGPIO_PDDR_PDD9_MASK) #define RGPIO_PDDR_PDD10_MASK (0x400U) #define RGPIO_PDDR_PDD10_SHIFT (10U) /*! PDD10 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD10_SHIFT)) & RGPIO_PDDR_PDD10_MASK) #define RGPIO_PDDR_PDD11_MASK (0x800U) #define RGPIO_PDDR_PDD11_SHIFT (11U) /*! PDD11 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD11_SHIFT)) & RGPIO_PDDR_PDD11_MASK) #define RGPIO_PDDR_PDD12_MASK (0x1000U) #define RGPIO_PDDR_PDD12_SHIFT (12U) /*! PDD12 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD12_SHIFT)) & RGPIO_PDDR_PDD12_MASK) #define RGPIO_PDDR_PDD13_MASK (0x2000U) #define RGPIO_PDDR_PDD13_SHIFT (13U) /*! PDD13 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD13_SHIFT)) & RGPIO_PDDR_PDD13_MASK) #define RGPIO_PDDR_PDD14_MASK (0x4000U) #define RGPIO_PDDR_PDD14_SHIFT (14U) /*! PDD14 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD14_SHIFT)) & RGPIO_PDDR_PDD14_MASK) #define RGPIO_PDDR_PDD15_MASK (0x8000U) #define RGPIO_PDDR_PDD15_SHIFT (15U) /*! PDD15 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD15_SHIFT)) & RGPIO_PDDR_PDD15_MASK) #define RGPIO_PDDR_PDD16_MASK (0x10000U) #define RGPIO_PDDR_PDD16_SHIFT (16U) /*! PDD16 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD16_SHIFT)) & RGPIO_PDDR_PDD16_MASK) #define RGPIO_PDDR_PDD17_MASK (0x20000U) #define RGPIO_PDDR_PDD17_SHIFT (17U) /*! PDD17 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD17_SHIFT)) & RGPIO_PDDR_PDD17_MASK) #define RGPIO_PDDR_PDD18_MASK (0x40000U) #define RGPIO_PDDR_PDD18_SHIFT (18U) /*! PDD18 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD18_SHIFT)) & RGPIO_PDDR_PDD18_MASK) #define RGPIO_PDDR_PDD19_MASK (0x80000U) #define RGPIO_PDDR_PDD19_SHIFT (19U) /*! PDD19 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD19_SHIFT)) & RGPIO_PDDR_PDD19_MASK) #define RGPIO_PDDR_PDD20_MASK (0x100000U) #define RGPIO_PDDR_PDD20_SHIFT (20U) /*! PDD20 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD20_SHIFT)) & RGPIO_PDDR_PDD20_MASK) #define RGPIO_PDDR_PDD21_MASK (0x200000U) #define RGPIO_PDDR_PDD21_SHIFT (21U) /*! PDD21 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD21_SHIFT)) & RGPIO_PDDR_PDD21_MASK) #define RGPIO_PDDR_PDD22_MASK (0x400000U) #define RGPIO_PDDR_PDD22_SHIFT (22U) /*! PDD22 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD22_SHIFT)) & RGPIO_PDDR_PDD22_MASK) #define RGPIO_PDDR_PDD23_MASK (0x800000U) #define RGPIO_PDDR_PDD23_SHIFT (23U) /*! PDD23 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD23_SHIFT)) & RGPIO_PDDR_PDD23_MASK) #define RGPIO_PDDR_PDD24_MASK (0x1000000U) #define RGPIO_PDDR_PDD24_SHIFT (24U) /*! PDD24 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD24_SHIFT)) & RGPIO_PDDR_PDD24_MASK) #define RGPIO_PDDR_PDD25_MASK (0x2000000U) #define RGPIO_PDDR_PDD25_SHIFT (25U) /*! PDD25 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD25_SHIFT)) & RGPIO_PDDR_PDD25_MASK) #define RGPIO_PDDR_PDD26_MASK (0x4000000U) #define RGPIO_PDDR_PDD26_SHIFT (26U) /*! PDD26 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD26_SHIFT)) & RGPIO_PDDR_PDD26_MASK) #define RGPIO_PDDR_PDD27_MASK (0x8000000U) #define RGPIO_PDDR_PDD27_SHIFT (27U) /*! PDD27 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD27_SHIFT)) & RGPIO_PDDR_PDD27_MASK) #define RGPIO_PDDR_PDD28_MASK (0x10000000U) #define RGPIO_PDDR_PDD28_SHIFT (28U) /*! PDD28 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD28_SHIFT)) & RGPIO_PDDR_PDD28_MASK) #define RGPIO_PDDR_PDD29_MASK (0x20000000U) #define RGPIO_PDDR_PDD29_SHIFT (29U) /*! PDD29 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD29_SHIFT)) & RGPIO_PDDR_PDD29_MASK) #define RGPIO_PDDR_PDD30_MASK (0x40000000U) #define RGPIO_PDDR_PDD30_SHIFT (30U) /*! PDD30 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD30_SHIFT)) & RGPIO_PDDR_PDD30_MASK) #define RGPIO_PDDR_PDD31_MASK (0x80000000U) #define RGPIO_PDDR_PDD31_SHIFT (31U) /*! PDD31 - Port Data Direction * 0b0..Input * 0b1..Output */ #define RGPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD31_SHIFT)) & RGPIO_PDDR_PDD31_MASK) /*! @} */ /*! @name PIDR - Port Input Disable */ /*! @{ */ #define RGPIO_PIDR_PID0_MASK (0x1U) #define RGPIO_PIDR_PID0_SHIFT (0U) /*! PID0 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID0_SHIFT)) & RGPIO_PIDR_PID0_MASK) #define RGPIO_PIDR_PID1_MASK (0x2U) #define RGPIO_PIDR_PID1_SHIFT (1U) /*! PID1 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID1_SHIFT)) & RGPIO_PIDR_PID1_MASK) #define RGPIO_PIDR_PID2_MASK (0x4U) #define RGPIO_PIDR_PID2_SHIFT (2U) /*! PID2 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID2_SHIFT)) & RGPIO_PIDR_PID2_MASK) #define RGPIO_PIDR_PID3_MASK (0x8U) #define RGPIO_PIDR_PID3_SHIFT (3U) /*! PID3 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID3_SHIFT)) & RGPIO_PIDR_PID3_MASK) #define RGPIO_PIDR_PID4_MASK (0x10U) #define RGPIO_PIDR_PID4_SHIFT (4U) /*! PID4 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID4_SHIFT)) & RGPIO_PIDR_PID4_MASK) #define RGPIO_PIDR_PID5_MASK (0x20U) #define RGPIO_PIDR_PID5_SHIFT (5U) /*! PID5 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID5_SHIFT)) & RGPIO_PIDR_PID5_MASK) #define RGPIO_PIDR_PID6_MASK (0x40U) #define RGPIO_PIDR_PID6_SHIFT (6U) /*! PID6 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID6_SHIFT)) & RGPIO_PIDR_PID6_MASK) #define RGPIO_PIDR_PID7_MASK (0x80U) #define RGPIO_PIDR_PID7_SHIFT (7U) /*! PID7 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID7_SHIFT)) & RGPIO_PIDR_PID7_MASK) #define RGPIO_PIDR_PID8_MASK (0x100U) #define RGPIO_PIDR_PID8_SHIFT (8U) /*! PID8 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID8_SHIFT)) & RGPIO_PIDR_PID8_MASK) #define RGPIO_PIDR_PID9_MASK (0x200U) #define RGPIO_PIDR_PID9_SHIFT (9U) /*! PID9 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID9_SHIFT)) & RGPIO_PIDR_PID9_MASK) #define RGPIO_PIDR_PID10_MASK (0x400U) #define RGPIO_PIDR_PID10_SHIFT (10U) /*! PID10 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID10_SHIFT)) & RGPIO_PIDR_PID10_MASK) #define RGPIO_PIDR_PID11_MASK (0x800U) #define RGPIO_PIDR_PID11_SHIFT (11U) /*! PID11 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID11_SHIFT)) & RGPIO_PIDR_PID11_MASK) #define RGPIO_PIDR_PID12_MASK (0x1000U) #define RGPIO_PIDR_PID12_SHIFT (12U) /*! PID12 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID12_SHIFT)) & RGPIO_PIDR_PID12_MASK) #define RGPIO_PIDR_PID13_MASK (0x2000U) #define RGPIO_PIDR_PID13_SHIFT (13U) /*! PID13 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID13_SHIFT)) & RGPIO_PIDR_PID13_MASK) #define RGPIO_PIDR_PID14_MASK (0x4000U) #define RGPIO_PIDR_PID14_SHIFT (14U) /*! PID14 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID14_SHIFT)) & RGPIO_PIDR_PID14_MASK) #define RGPIO_PIDR_PID15_MASK (0x8000U) #define RGPIO_PIDR_PID15_SHIFT (15U) /*! PID15 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID15_SHIFT)) & RGPIO_PIDR_PID15_MASK) #define RGPIO_PIDR_PID16_MASK (0x10000U) #define RGPIO_PIDR_PID16_SHIFT (16U) /*! PID16 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID16_SHIFT)) & RGPIO_PIDR_PID16_MASK) #define RGPIO_PIDR_PID17_MASK (0x20000U) #define RGPIO_PIDR_PID17_SHIFT (17U) /*! PID17 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID17_SHIFT)) & RGPIO_PIDR_PID17_MASK) #define RGPIO_PIDR_PID18_MASK (0x40000U) #define RGPIO_PIDR_PID18_SHIFT (18U) /*! PID18 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID18_SHIFT)) & RGPIO_PIDR_PID18_MASK) #define RGPIO_PIDR_PID19_MASK (0x80000U) #define RGPIO_PIDR_PID19_SHIFT (19U) /*! PID19 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID19_SHIFT)) & RGPIO_PIDR_PID19_MASK) #define RGPIO_PIDR_PID20_MASK (0x100000U) #define RGPIO_PIDR_PID20_SHIFT (20U) /*! PID20 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID20_SHIFT)) & RGPIO_PIDR_PID20_MASK) #define RGPIO_PIDR_PID21_MASK (0x200000U) #define RGPIO_PIDR_PID21_SHIFT (21U) /*! PID21 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID21_SHIFT)) & RGPIO_PIDR_PID21_MASK) #define RGPIO_PIDR_PID22_MASK (0x400000U) #define RGPIO_PIDR_PID22_SHIFT (22U) /*! PID22 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID22_SHIFT)) & RGPIO_PIDR_PID22_MASK) #define RGPIO_PIDR_PID23_MASK (0x800000U) #define RGPIO_PIDR_PID23_SHIFT (23U) /*! PID23 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID23_SHIFT)) & RGPIO_PIDR_PID23_MASK) #define RGPIO_PIDR_PID24_MASK (0x1000000U) #define RGPIO_PIDR_PID24_SHIFT (24U) /*! PID24 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID24_SHIFT)) & RGPIO_PIDR_PID24_MASK) #define RGPIO_PIDR_PID25_MASK (0x2000000U) #define RGPIO_PIDR_PID25_SHIFT (25U) /*! PID25 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID25_SHIFT)) & RGPIO_PIDR_PID25_MASK) #define RGPIO_PIDR_PID26_MASK (0x4000000U) #define RGPIO_PIDR_PID26_SHIFT (26U) /*! PID26 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID26_SHIFT)) & RGPIO_PIDR_PID26_MASK) #define RGPIO_PIDR_PID27_MASK (0x8000000U) #define RGPIO_PIDR_PID27_SHIFT (27U) /*! PID27 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID27_SHIFT)) & RGPIO_PIDR_PID27_MASK) #define RGPIO_PIDR_PID28_MASK (0x10000000U) #define RGPIO_PIDR_PID28_SHIFT (28U) /*! PID28 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID28_SHIFT)) & RGPIO_PIDR_PID28_MASK) #define RGPIO_PIDR_PID29_MASK (0x20000000U) #define RGPIO_PIDR_PID29_SHIFT (29U) /*! PID29 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID29_SHIFT)) & RGPIO_PIDR_PID29_MASK) #define RGPIO_PIDR_PID30_MASK (0x40000000U) #define RGPIO_PIDR_PID30_SHIFT (30U) /*! PID30 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID30_SHIFT)) & RGPIO_PIDR_PID30_MASK) #define RGPIO_PIDR_PID31_MASK (0x80000000U) #define RGPIO_PIDR_PID31_SHIFT (31U) /*! PID31 - Port Input Disable * 0b0..Configured for general-purpose input * 0b1..Disabled for general-purpose input */ #define RGPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PIDR_PID31_SHIFT)) & RGPIO_PIDR_PID31_MASK) /*! @} */ /*! @name PDR - Pin Data */ /*! @{ */ #define RGPIO_PDR_PD_MASK (0x1U) #define RGPIO_PDR_PD_SHIFT (0U) /*! PD - Pin Data (I/O) * 0b0..Logic zero * 0b1..Logic one */ #define RGPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << RGPIO_PDR_PD_SHIFT)) & RGPIO_PDR_PD_MASK) /*! @} */ /* The count of RGPIO_PDR */ #define RGPIO_PDR_COUNT (32U) /*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ /*! @{ */ #define RGPIO_ICR_IRQC_MASK (0xF0000U) #define RGPIO_ICR_IRQC_SHIFT (16U) /*! IRQC - Interrupt Configuration * 0b0000..ISF is disabled * 0b0001..ISF and DMA request on rising edge * 0b0010..ISF and DMA request on falling edge * 0b0011..ISF and DMA request on either edge * 0b0100..Reserved * 0b0101..ISF sets on rising edge * 0b0110..ISF sets on falling edge * 0b0111..ISF sets on either edge * 0b1000..ISF and interrupt when logic 0 * 0b1001..ISF and interrupt on rising edge * 0b1010..ISF and interrupt on falling edge * 0b1011..ISF and Interrupt on either edge * 0b1100..ISF and interrupt when logic 1 * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers * to generate the output trigger for use by other peripherals) * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other * enabled triggers to generate the output trigger for use by other peripherals) * 0b1111..Reserved */ #define RGPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQC_SHIFT)) & RGPIO_ICR_IRQC_MASK) #define RGPIO_ICR_IRQS_MASK (0x100000U) #define RGPIO_ICR_IRQS_SHIFT (20U) /*! IRQS - Interrupt Select * 0b0..Interrupt, trigger output, or DMA request 0 * 0b1..Interrupt, trigger output, or DMA request 1 */ #define RGPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_IRQS_SHIFT)) & RGPIO_ICR_IRQS_MASK) #define RGPIO_ICR_LK_MASK (0x800000U) #define RGPIO_ICR_LK_SHIFT (23U) /*! LK - Lock * 0b0..Lock * 0b1..Do not lock */ #define RGPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_LK_SHIFT)) & RGPIO_ICR_LK_MASK) #define RGPIO_ICR_ISF_MASK (0x1000000U) #define RGPIO_ICR_ISF_SHIFT (24U) /*! ISF - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ICR_ISF_SHIFT)) & RGPIO_ICR_ISF_MASK) /*! @} */ /* The count of RGPIO_ICR */ #define RGPIO_ICR_COUNT (32U) /*! @name GICLR - Global Interrupt Control Low */ /*! @{ */ #define RGPIO_GICLR_GIWE0_MASK (0x1U) #define RGPIO_GICLR_GIWE0_SHIFT (0U) /*! GIWE0 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE0_SHIFT)) & RGPIO_GICLR_GIWE0_MASK) #define RGPIO_GICLR_GIWE1_MASK (0x2U) #define RGPIO_GICLR_GIWE1_SHIFT (1U) /*! GIWE1 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE1_SHIFT)) & RGPIO_GICLR_GIWE1_MASK) #define RGPIO_GICLR_GIWE2_MASK (0x4U) #define RGPIO_GICLR_GIWE2_SHIFT (2U) /*! GIWE2 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE2_SHIFT)) & RGPIO_GICLR_GIWE2_MASK) #define RGPIO_GICLR_GIWE3_MASK (0x8U) #define RGPIO_GICLR_GIWE3_SHIFT (3U) /*! GIWE3 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE3_SHIFT)) & RGPIO_GICLR_GIWE3_MASK) #define RGPIO_GICLR_GIWE4_MASK (0x10U) #define RGPIO_GICLR_GIWE4_SHIFT (4U) /*! GIWE4 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE4_SHIFT)) & RGPIO_GICLR_GIWE4_MASK) #define RGPIO_GICLR_GIWE5_MASK (0x20U) #define RGPIO_GICLR_GIWE5_SHIFT (5U) /*! GIWE5 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE5_SHIFT)) & RGPIO_GICLR_GIWE5_MASK) #define RGPIO_GICLR_GIWE6_MASK (0x40U) #define RGPIO_GICLR_GIWE6_SHIFT (6U) /*! GIWE6 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE6_SHIFT)) & RGPIO_GICLR_GIWE6_MASK) #define RGPIO_GICLR_GIWE7_MASK (0x80U) #define RGPIO_GICLR_GIWE7_SHIFT (7U) /*! GIWE7 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE7_SHIFT)) & RGPIO_GICLR_GIWE7_MASK) #define RGPIO_GICLR_GIWE8_MASK (0x100U) #define RGPIO_GICLR_GIWE8_SHIFT (8U) /*! GIWE8 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE8_SHIFT)) & RGPIO_GICLR_GIWE8_MASK) #define RGPIO_GICLR_GIWE9_MASK (0x200U) #define RGPIO_GICLR_GIWE9_SHIFT (9U) /*! GIWE9 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE9_SHIFT)) & RGPIO_GICLR_GIWE9_MASK) #define RGPIO_GICLR_GIWE10_MASK (0x400U) #define RGPIO_GICLR_GIWE10_SHIFT (10U) /*! GIWE10 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE10_SHIFT)) & RGPIO_GICLR_GIWE10_MASK) #define RGPIO_GICLR_GIWE11_MASK (0x800U) #define RGPIO_GICLR_GIWE11_SHIFT (11U) /*! GIWE11 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE11_SHIFT)) & RGPIO_GICLR_GIWE11_MASK) #define RGPIO_GICLR_GIWE12_MASK (0x1000U) #define RGPIO_GICLR_GIWE12_SHIFT (12U) /*! GIWE12 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE12_SHIFT)) & RGPIO_GICLR_GIWE12_MASK) #define RGPIO_GICLR_GIWE13_MASK (0x2000U) #define RGPIO_GICLR_GIWE13_SHIFT (13U) /*! GIWE13 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE13_SHIFT)) & RGPIO_GICLR_GIWE13_MASK) #define RGPIO_GICLR_GIWE14_MASK (0x4000U) #define RGPIO_GICLR_GIWE14_SHIFT (14U) /*! GIWE14 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE14_SHIFT)) & RGPIO_GICLR_GIWE14_MASK) #define RGPIO_GICLR_GIWE15_MASK (0x8000U) #define RGPIO_GICLR_GIWE15_SHIFT (15U) /*! GIWE15 - Global Interrupt Write Enable * 0b0..Not updated * 0b1..Updated */ #define RGPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWE15_SHIFT)) & RGPIO_GICLR_GIWE15_MASK) #define RGPIO_GICLR_GIWD_MASK (0xFFFF0000U) #define RGPIO_GICLR_GIWD_SHIFT (16U) /*! GIWD - Global Interrupt Write Data */ #define RGPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICLR_GIWD_SHIFT)) & RGPIO_GICLR_GIWD_MASK) /*! @} */ /*! @name GICHR - Global Interrupt Control High */ /*! @{ */ #define RGPIO_GICHR_GIWE16_MASK (0x1U) #define RGPIO_GICHR_GIWE16_SHIFT (0U) /*! GIWE16 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE16_SHIFT)) & RGPIO_GICHR_GIWE16_MASK) #define RGPIO_GICHR_GIWE17_MASK (0x2U) #define RGPIO_GICHR_GIWE17_SHIFT (1U) /*! GIWE17 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE17_SHIFT)) & RGPIO_GICHR_GIWE17_MASK) #define RGPIO_GICHR_GIWE18_MASK (0x4U) #define RGPIO_GICHR_GIWE18_SHIFT (2U) /*! GIWE18 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE18_SHIFT)) & RGPIO_GICHR_GIWE18_MASK) #define RGPIO_GICHR_GIWE19_MASK (0x8U) #define RGPIO_GICHR_GIWE19_SHIFT (3U) /*! GIWE19 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE19_SHIFT)) & RGPIO_GICHR_GIWE19_MASK) #define RGPIO_GICHR_GIWE20_MASK (0x10U) #define RGPIO_GICHR_GIWE20_SHIFT (4U) /*! GIWE20 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE20_SHIFT)) & RGPIO_GICHR_GIWE20_MASK) #define RGPIO_GICHR_GIWE21_MASK (0x20U) #define RGPIO_GICHR_GIWE21_SHIFT (5U) /*! GIWE21 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE21_SHIFT)) & RGPIO_GICHR_GIWE21_MASK) #define RGPIO_GICHR_GIWE22_MASK (0x40U) #define RGPIO_GICHR_GIWE22_SHIFT (6U) /*! GIWE22 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE22_SHIFT)) & RGPIO_GICHR_GIWE22_MASK) #define RGPIO_GICHR_GIWE23_MASK (0x80U) #define RGPIO_GICHR_GIWE23_SHIFT (7U) /*! GIWE23 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE23_SHIFT)) & RGPIO_GICHR_GIWE23_MASK) #define RGPIO_GICHR_GIWE24_MASK (0x100U) #define RGPIO_GICHR_GIWE24_SHIFT (8U) /*! GIWE24 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE24_SHIFT)) & RGPIO_GICHR_GIWE24_MASK) #define RGPIO_GICHR_GIWE25_MASK (0x200U) #define RGPIO_GICHR_GIWE25_SHIFT (9U) /*! GIWE25 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE25_SHIFT)) & RGPIO_GICHR_GIWE25_MASK) #define RGPIO_GICHR_GIWE26_MASK (0x400U) #define RGPIO_GICHR_GIWE26_SHIFT (10U) /*! GIWE26 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE26_SHIFT)) & RGPIO_GICHR_GIWE26_MASK) #define RGPIO_GICHR_GIWE27_MASK (0x800U) #define RGPIO_GICHR_GIWE27_SHIFT (11U) /*! GIWE27 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE27_SHIFT)) & RGPIO_GICHR_GIWE27_MASK) #define RGPIO_GICHR_GIWE28_MASK (0x1000U) #define RGPIO_GICHR_GIWE28_SHIFT (12U) /*! GIWE28 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE28_SHIFT)) & RGPIO_GICHR_GIWE28_MASK) #define RGPIO_GICHR_GIWE29_MASK (0x2000U) #define RGPIO_GICHR_GIWE29_SHIFT (13U) /*! GIWE29 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE29_SHIFT)) & RGPIO_GICHR_GIWE29_MASK) #define RGPIO_GICHR_GIWE30_MASK (0x4000U) #define RGPIO_GICHR_GIWE30_SHIFT (14U) /*! GIWE30 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE30_SHIFT)) & RGPIO_GICHR_GIWE30_MASK) #define RGPIO_GICHR_GIWE31_MASK (0x8000U) #define RGPIO_GICHR_GIWE31_SHIFT (15U) /*! GIWE31 - Global Interrupt Write Enable * 0b0..Not updated. * 0b1..Updated */ #define RGPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWE31_SHIFT)) & RGPIO_GICHR_GIWE31_MASK) #define RGPIO_GICHR_GIWD_MASK (0xFFFF0000U) #define RGPIO_GICHR_GIWD_SHIFT (16U) /*! GIWD - Global Interrupt Write Data */ #define RGPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_GICHR_GIWD_SHIFT)) & RGPIO_GICHR_GIWD_MASK) /*! @} */ /*! @name ISFR - Interrupt Status Flag */ /*! @{ */ #define RGPIO_ISFR_ISF0_MASK (0x1U) #define RGPIO_ISFR_ISF0_SHIFT (0U) /*! ISF0 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF0_SHIFT)) & RGPIO_ISFR_ISF0_MASK) #define RGPIO_ISFR_ISF1_MASK (0x2U) #define RGPIO_ISFR_ISF1_SHIFT (1U) /*! ISF1 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF1_SHIFT)) & RGPIO_ISFR_ISF1_MASK) #define RGPIO_ISFR_ISF2_MASK (0x4U) #define RGPIO_ISFR_ISF2_SHIFT (2U) /*! ISF2 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF2_SHIFT)) & RGPIO_ISFR_ISF2_MASK) #define RGPIO_ISFR_ISF3_MASK (0x8U) #define RGPIO_ISFR_ISF3_SHIFT (3U) /*! ISF3 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF3_SHIFT)) & RGPIO_ISFR_ISF3_MASK) #define RGPIO_ISFR_ISF4_MASK (0x10U) #define RGPIO_ISFR_ISF4_SHIFT (4U) /*! ISF4 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF4_SHIFT)) & RGPIO_ISFR_ISF4_MASK) #define RGPIO_ISFR_ISF5_MASK (0x20U) #define RGPIO_ISFR_ISF5_SHIFT (5U) /*! ISF5 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF5_SHIFT)) & RGPIO_ISFR_ISF5_MASK) #define RGPIO_ISFR_ISF6_MASK (0x40U) #define RGPIO_ISFR_ISF6_SHIFT (6U) /*! ISF6 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF6_SHIFT)) & RGPIO_ISFR_ISF6_MASK) #define RGPIO_ISFR_ISF7_MASK (0x80U) #define RGPIO_ISFR_ISF7_SHIFT (7U) /*! ISF7 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF7_SHIFT)) & RGPIO_ISFR_ISF7_MASK) #define RGPIO_ISFR_ISF8_MASK (0x100U) #define RGPIO_ISFR_ISF8_SHIFT (8U) /*! ISF8 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF8_SHIFT)) & RGPIO_ISFR_ISF8_MASK) #define RGPIO_ISFR_ISF9_MASK (0x200U) #define RGPIO_ISFR_ISF9_SHIFT (9U) /*! ISF9 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF9_SHIFT)) & RGPIO_ISFR_ISF9_MASK) #define RGPIO_ISFR_ISF10_MASK (0x400U) #define RGPIO_ISFR_ISF10_SHIFT (10U) /*! ISF10 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF10_SHIFT)) & RGPIO_ISFR_ISF10_MASK) #define RGPIO_ISFR_ISF11_MASK (0x800U) #define RGPIO_ISFR_ISF11_SHIFT (11U) /*! ISF11 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF11_SHIFT)) & RGPIO_ISFR_ISF11_MASK) #define RGPIO_ISFR_ISF12_MASK (0x1000U) #define RGPIO_ISFR_ISF12_SHIFT (12U) /*! ISF12 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF12_SHIFT)) & RGPIO_ISFR_ISF12_MASK) #define RGPIO_ISFR_ISF13_MASK (0x2000U) #define RGPIO_ISFR_ISF13_SHIFT (13U) /*! ISF13 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF13_SHIFT)) & RGPIO_ISFR_ISF13_MASK) #define RGPIO_ISFR_ISF14_MASK (0x4000U) #define RGPIO_ISFR_ISF14_SHIFT (14U) /*! ISF14 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF14_SHIFT)) & RGPIO_ISFR_ISF14_MASK) #define RGPIO_ISFR_ISF15_MASK (0x8000U) #define RGPIO_ISFR_ISF15_SHIFT (15U) /*! ISF15 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF15_SHIFT)) & RGPIO_ISFR_ISF15_MASK) #define RGPIO_ISFR_ISF16_MASK (0x10000U) #define RGPIO_ISFR_ISF16_SHIFT (16U) /*! ISF16 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF16_SHIFT)) & RGPIO_ISFR_ISF16_MASK) #define RGPIO_ISFR_ISF17_MASK (0x20000U) #define RGPIO_ISFR_ISF17_SHIFT (17U) /*! ISF17 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF17_SHIFT)) & RGPIO_ISFR_ISF17_MASK) #define RGPIO_ISFR_ISF18_MASK (0x40000U) #define RGPIO_ISFR_ISF18_SHIFT (18U) /*! ISF18 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF18_SHIFT)) & RGPIO_ISFR_ISF18_MASK) #define RGPIO_ISFR_ISF19_MASK (0x80000U) #define RGPIO_ISFR_ISF19_SHIFT (19U) /*! ISF19 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF19_SHIFT)) & RGPIO_ISFR_ISF19_MASK) #define RGPIO_ISFR_ISF20_MASK (0x100000U) #define RGPIO_ISFR_ISF20_SHIFT (20U) /*! ISF20 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF20_SHIFT)) & RGPIO_ISFR_ISF20_MASK) #define RGPIO_ISFR_ISF21_MASK (0x200000U) #define RGPIO_ISFR_ISF21_SHIFT (21U) /*! ISF21 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF21_SHIFT)) & RGPIO_ISFR_ISF21_MASK) #define RGPIO_ISFR_ISF22_MASK (0x400000U) #define RGPIO_ISFR_ISF22_SHIFT (22U) /*! ISF22 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF22_SHIFT)) & RGPIO_ISFR_ISF22_MASK) #define RGPIO_ISFR_ISF23_MASK (0x800000U) #define RGPIO_ISFR_ISF23_SHIFT (23U) /*! ISF23 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF23_SHIFT)) & RGPIO_ISFR_ISF23_MASK) #define RGPIO_ISFR_ISF24_MASK (0x1000000U) #define RGPIO_ISFR_ISF24_SHIFT (24U) /*! ISF24 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF24_SHIFT)) & RGPIO_ISFR_ISF24_MASK) #define RGPIO_ISFR_ISF25_MASK (0x2000000U) #define RGPIO_ISFR_ISF25_SHIFT (25U) /*! ISF25 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF25_SHIFT)) & RGPIO_ISFR_ISF25_MASK) #define RGPIO_ISFR_ISF26_MASK (0x4000000U) #define RGPIO_ISFR_ISF26_SHIFT (26U) /*! ISF26 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF26_SHIFT)) & RGPIO_ISFR_ISF26_MASK) #define RGPIO_ISFR_ISF27_MASK (0x8000000U) #define RGPIO_ISFR_ISF27_SHIFT (27U) /*! ISF27 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF27_SHIFT)) & RGPIO_ISFR_ISF27_MASK) #define RGPIO_ISFR_ISF28_MASK (0x10000000U) #define RGPIO_ISFR_ISF28_SHIFT (28U) /*! ISF28 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF28_SHIFT)) & RGPIO_ISFR_ISF28_MASK) #define RGPIO_ISFR_ISF29_MASK (0x20000000U) #define RGPIO_ISFR_ISF29_SHIFT (29U) /*! ISF29 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF29_SHIFT)) & RGPIO_ISFR_ISF29_MASK) #define RGPIO_ISFR_ISF30_MASK (0x40000000U) #define RGPIO_ISFR_ISF30_SHIFT (30U) /*! ISF30 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF30_SHIFT)) & RGPIO_ISFR_ISF30_MASK) #define RGPIO_ISFR_ISF31_MASK (0x80000000U) #define RGPIO_ISFR_ISF31_SHIFT (31U) /*! ISF31 - Interrupt Status Flag * 0b0..Not detected * 0b1..Detected * 0b0..No effect * 0b1..Clear the flag */ #define RGPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_ISFR_ISF31_SHIFT)) & RGPIO_ISFR_ISF31_MASK) /*! @} */ /* The count of RGPIO_ISFR */ #define RGPIO_ISFR_COUNT (2U) /*! * @} */ /* end of group RGPIO_Register_Masks */ /* RGPIO - Peripheral instance base addresses */ /** Peripheral GPIO1 base address */ #define GPIO1_BASE (0x47400000u) /** Peripheral GPIO1 base pointer */ #define GPIO1 ((RGPIO_Type *)GPIO1_BASE) /** Peripheral GPIO2 base address */ #define GPIO2_BASE (0x43810000u) /** Peripheral GPIO2 base pointer */ #define GPIO2 ((RGPIO_Type *)GPIO2_BASE) /** Peripheral GPIO3 base address */ #define GPIO3_BASE (0x43820000u) /** Peripheral GPIO3 base pointer */ #define GPIO3 ((RGPIO_Type *)GPIO3_BASE) /** Peripheral GPIO4 base address */ #define GPIO4_BASE (0x43840000u) /** Peripheral GPIO4 base pointer */ #define GPIO4 ((RGPIO_Type *)GPIO4_BASE) /** Peripheral GPIO5 base address */ #define GPIO5_BASE (0x43850000u) /** Peripheral GPIO5 base pointer */ #define GPIO5 ((RGPIO_Type *)GPIO5_BASE) /** Array initializer of RGPIO peripheral base addresses */ #define RGPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } /** Array initializer of RGPIO peripheral base pointers */ #define RGPIO_BASE_PTRS { (RGPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } /*! * @} */ /* end of group RGPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SEMA42 Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Peripheral_Access_Layer SEMA42 Peripheral Access Layer * @{ */ /** SEMA42 - Register Layout Typedef */ typedef struct { __IO uint8_t GATE3; /**< Gate, offset: 0x0 */ __IO uint8_t GATE2; /**< Gate, offset: 0x1 */ __IO uint8_t GATE1; /**< Gate, offset: 0x2 */ __IO uint8_t GATE0; /**< Gate, offset: 0x3 */ __IO uint8_t GATE7; /**< Gate, offset: 0x4 */ __IO uint8_t GATE6; /**< Gate, offset: 0x5 */ __IO uint8_t GATE5; /**< Gate, offset: 0x6 */ __IO uint8_t GATE4; /**< Gate, offset: 0x7 */ __IO uint8_t GATE11; /**< Gate, offset: 0x8 */ __IO uint8_t GATE10; /**< Gate, offset: 0x9 */ __IO uint8_t GATE9; /**< Gate, offset: 0xA */ __IO uint8_t GATE8; /**< Gate, offset: 0xB */ __IO uint8_t GATE15; /**< Gate, offset: 0xC */ __IO uint8_t GATE14; /**< Gate, offset: 0xD */ __IO uint8_t GATE13; /**< Gate, offset: 0xE */ __IO uint8_t GATE12; /**< Gate, offset: 0xF */ __IO uint8_t GATE19; /**< Gate, offset: 0x10 */ __IO uint8_t GATE18; /**< Gate, offset: 0x11 */ __IO uint8_t GATE17; /**< Gate, offset: 0x12 */ __IO uint8_t GATE16; /**< Gate, offset: 0x13 */ __IO uint8_t GATE23; /**< Gate, offset: 0x14 */ __IO uint8_t GATE22; /**< Gate, offset: 0x15 */ __IO uint8_t GATE21; /**< Gate, offset: 0x16 */ __IO uint8_t GATE20; /**< Gate, offset: 0x17 */ __IO uint8_t GATE27; /**< Gate, offset: 0x18 */ __IO uint8_t GATE26; /**< Gate, offset: 0x19 */ __IO uint8_t GATE25; /**< Gate, offset: 0x1A */ __IO uint8_t GATE24; /**< Gate, offset: 0x1B */ __IO uint8_t GATE31; /**< Gate, offset: 0x1C */ __IO uint8_t GATE30; /**< Gate, offset: 0x1D */ __IO uint8_t GATE29; /**< Gate, offset: 0x1E */ __IO uint8_t GATE28; /**< Gate, offset: 0x1F */ __IO uint8_t GATE35; /**< Gate, offset: 0x20 */ __IO uint8_t GATE34; /**< Gate, offset: 0x21 */ __IO uint8_t GATE33; /**< Gate, offset: 0x22 */ __IO uint8_t GATE32; /**< Gate, offset: 0x23 */ __IO uint8_t GATE39; /**< Gate, offset: 0x24 */ __IO uint8_t GATE38; /**< Gate, offset: 0x25 */ __IO uint8_t GATE37; /**< Gate, offset: 0x26 */ __IO uint8_t GATE36; /**< Gate, offset: 0x27 */ __IO uint8_t GATE43; /**< Gate, offset: 0x28 */ __IO uint8_t GATE42; /**< Gate, offset: 0x29 */ __IO uint8_t GATE41; /**< Gate, offset: 0x2A */ __IO uint8_t GATE40; /**< Gate, offset: 0x2B */ __IO uint8_t GATE47; /**< Gate, offset: 0x2C */ __IO uint8_t GATE46; /**< Gate, offset: 0x2D */ __IO uint8_t GATE45; /**< Gate, offset: 0x2E */ __IO uint8_t GATE44; /**< Gate, offset: 0x2F */ __IO uint8_t GATE51; /**< Gate, offset: 0x30 */ __IO uint8_t GATE50; /**< Gate, offset: 0x31 */ __IO uint8_t GATE49; /**< Gate, offset: 0x32 */ __IO uint8_t GATE48; /**< Gate, offset: 0x33 */ __IO uint8_t GATE55; /**< Gate, offset: 0x34 */ __IO uint8_t GATE54; /**< Gate, offset: 0x35 */ __IO uint8_t GATE53; /**< Gate, offset: 0x36 */ __IO uint8_t GATE52; /**< Gate, offset: 0x37 */ __IO uint8_t GATE59; /**< Gate, offset: 0x38 */ __IO uint8_t GATE58; /**< Gate, offset: 0x39 */ __IO uint8_t GATE57; /**< Gate, offset: 0x3A */ __IO uint8_t GATE56; /**< Gate, offset: 0x3B */ __IO uint8_t GATE63; /**< Gate, offset: 0x3C */ __IO uint8_t GATE62; /**< Gate, offset: 0x3D */ __IO uint8_t GATE61; /**< Gate, offset: 0x3E */ __IO uint8_t GATE60; /**< Gate, offset: 0x3F */ uint8_t RESERVED_0[2]; union { /* offset: 0x42 */ __I uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ __O uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ }; } SEMA42_Type; /* ---------------------------------------------------------------------------- -- SEMA42 Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SEMA42_Register_Masks SEMA42 Register Masks * @{ */ /*! @name GATE3 - Gate */ /*! @{ */ #define SEMA42_GATE3_GTFSM_MASK (0xFU) #define SEMA42_GATE3_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE3_GTFSM_SHIFT)) & SEMA42_GATE3_GTFSM_MASK) /*! @} */ /*! @name GATE2 - Gate */ /*! @{ */ #define SEMA42_GATE2_GTFSM_MASK (0xFU) #define SEMA42_GATE2_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE2_GTFSM_SHIFT)) & SEMA42_GATE2_GTFSM_MASK) /*! @} */ /*! @name GATE1 - Gate */ /*! @{ */ #define SEMA42_GATE1_GTFSM_MASK (0xFU) #define SEMA42_GATE1_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE1_GTFSM_SHIFT)) & SEMA42_GATE1_GTFSM_MASK) /*! @} */ /*! @name GATE0 - Gate */ /*! @{ */ #define SEMA42_GATE0_GTFSM_MASK (0xFU) #define SEMA42_GATE0_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE0_GTFSM_SHIFT)) & SEMA42_GATE0_GTFSM_MASK) /*! @} */ /*! @name GATE7 - Gate */ /*! @{ */ #define SEMA42_GATE7_GTFSM_MASK (0xFU) #define SEMA42_GATE7_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE7_GTFSM_SHIFT)) & SEMA42_GATE7_GTFSM_MASK) /*! @} */ /*! @name GATE6 - Gate */ /*! @{ */ #define SEMA42_GATE6_GTFSM_MASK (0xFU) #define SEMA42_GATE6_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE6_GTFSM_SHIFT)) & SEMA42_GATE6_GTFSM_MASK) /*! @} */ /*! @name GATE5 - Gate */ /*! @{ */ #define SEMA42_GATE5_GTFSM_MASK (0xFU) #define SEMA42_GATE5_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE5_GTFSM_SHIFT)) & SEMA42_GATE5_GTFSM_MASK) /*! @} */ /*! @name GATE4 - Gate */ /*! @{ */ #define SEMA42_GATE4_GTFSM_MASK (0xFU) #define SEMA42_GATE4_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE4_GTFSM_SHIFT)) & SEMA42_GATE4_GTFSM_MASK) /*! @} */ /*! @name GATE11 - Gate */ /*! @{ */ #define SEMA42_GATE11_GTFSM_MASK (0xFU) #define SEMA42_GATE11_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE11_GTFSM_SHIFT)) & SEMA42_GATE11_GTFSM_MASK) /*! @} */ /*! @name GATE10 - Gate */ /*! @{ */ #define SEMA42_GATE10_GTFSM_MASK (0xFU) #define SEMA42_GATE10_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE10_GTFSM_SHIFT)) & SEMA42_GATE10_GTFSM_MASK) /*! @} */ /*! @name GATE9 - Gate */ /*! @{ */ #define SEMA42_GATE9_GTFSM_MASK (0xFU) #define SEMA42_GATE9_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE9_GTFSM_SHIFT)) & SEMA42_GATE9_GTFSM_MASK) /*! @} */ /*! @name GATE8 - Gate */ /*! @{ */ #define SEMA42_GATE8_GTFSM_MASK (0xFU) #define SEMA42_GATE8_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE8_GTFSM_SHIFT)) & SEMA42_GATE8_GTFSM_MASK) /*! @} */ /*! @name GATE15 - Gate */ /*! @{ */ #define SEMA42_GATE15_GTFSM_MASK (0xFU) #define SEMA42_GATE15_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE15_GTFSM_SHIFT)) & SEMA42_GATE15_GTFSM_MASK) /*! @} */ /*! @name GATE14 - Gate */ /*! @{ */ #define SEMA42_GATE14_GTFSM_MASK (0xFU) #define SEMA42_GATE14_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE14_GTFSM_SHIFT)) & SEMA42_GATE14_GTFSM_MASK) /*! @} */ /*! @name GATE13 - Gate */ /*! @{ */ #define SEMA42_GATE13_GTFSM_MASK (0xFU) #define SEMA42_GATE13_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE13_GTFSM_SHIFT)) & SEMA42_GATE13_GTFSM_MASK) /*! @} */ /*! @name GATE12 - Gate */ /*! @{ */ #define SEMA42_GATE12_GTFSM_MASK (0xFU) #define SEMA42_GATE12_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE12_GTFSM_SHIFT)) & SEMA42_GATE12_GTFSM_MASK) /*! @} */ /*! @name GATE19 - Gate */ /*! @{ */ #define SEMA42_GATE19_GTFSM_MASK (0xFU) #define SEMA42_GATE19_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE19_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE19_GTFSM_SHIFT)) & SEMA42_GATE19_GTFSM_MASK) /*! @} */ /*! @name GATE18 - Gate */ /*! @{ */ #define SEMA42_GATE18_GTFSM_MASK (0xFU) #define SEMA42_GATE18_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE18_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE18_GTFSM_SHIFT)) & SEMA42_GATE18_GTFSM_MASK) /*! @} */ /*! @name GATE17 - Gate */ /*! @{ */ #define SEMA42_GATE17_GTFSM_MASK (0xFU) #define SEMA42_GATE17_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE17_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE17_GTFSM_SHIFT)) & SEMA42_GATE17_GTFSM_MASK) /*! @} */ /*! @name GATE16 - Gate */ /*! @{ */ #define SEMA42_GATE16_GTFSM_MASK (0xFU) #define SEMA42_GATE16_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE16_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE16_GTFSM_SHIFT)) & SEMA42_GATE16_GTFSM_MASK) /*! @} */ /*! @name GATE23 - Gate */ /*! @{ */ #define SEMA42_GATE23_GTFSM_MASK (0xFU) #define SEMA42_GATE23_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE23_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE23_GTFSM_SHIFT)) & SEMA42_GATE23_GTFSM_MASK) /*! @} */ /*! @name GATE22 - Gate */ /*! @{ */ #define SEMA42_GATE22_GTFSM_MASK (0xFU) #define SEMA42_GATE22_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE22_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE22_GTFSM_SHIFT)) & SEMA42_GATE22_GTFSM_MASK) /*! @} */ /*! @name GATE21 - Gate */ /*! @{ */ #define SEMA42_GATE21_GTFSM_MASK (0xFU) #define SEMA42_GATE21_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE21_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE21_GTFSM_SHIFT)) & SEMA42_GATE21_GTFSM_MASK) /*! @} */ /*! @name GATE20 - Gate */ /*! @{ */ #define SEMA42_GATE20_GTFSM_MASK (0xFU) #define SEMA42_GATE20_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE20_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE20_GTFSM_SHIFT)) & SEMA42_GATE20_GTFSM_MASK) /*! @} */ /*! @name GATE27 - Gate */ /*! @{ */ #define SEMA42_GATE27_GTFSM_MASK (0xFU) #define SEMA42_GATE27_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE27_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE27_GTFSM_SHIFT)) & SEMA42_GATE27_GTFSM_MASK) /*! @} */ /*! @name GATE26 - Gate */ /*! @{ */ #define SEMA42_GATE26_GTFSM_MASK (0xFU) #define SEMA42_GATE26_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE26_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE26_GTFSM_SHIFT)) & SEMA42_GATE26_GTFSM_MASK) /*! @} */ /*! @name GATE25 - Gate */ /*! @{ */ #define SEMA42_GATE25_GTFSM_MASK (0xFU) #define SEMA42_GATE25_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE25_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE25_GTFSM_SHIFT)) & SEMA42_GATE25_GTFSM_MASK) /*! @} */ /*! @name GATE24 - Gate */ /*! @{ */ #define SEMA42_GATE24_GTFSM_MASK (0xFU) #define SEMA42_GATE24_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE24_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE24_GTFSM_SHIFT)) & SEMA42_GATE24_GTFSM_MASK) /*! @} */ /*! @name GATE31 - Gate */ /*! @{ */ #define SEMA42_GATE31_GTFSM_MASK (0xFU) #define SEMA42_GATE31_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE31_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE31_GTFSM_SHIFT)) & SEMA42_GATE31_GTFSM_MASK) /*! @} */ /*! @name GATE30 - Gate */ /*! @{ */ #define SEMA42_GATE30_GTFSM_MASK (0xFU) #define SEMA42_GATE30_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE30_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE30_GTFSM_SHIFT)) & SEMA42_GATE30_GTFSM_MASK) /*! @} */ /*! @name GATE29 - Gate */ /*! @{ */ #define SEMA42_GATE29_GTFSM_MASK (0xFU) #define SEMA42_GATE29_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE29_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE29_GTFSM_SHIFT)) & SEMA42_GATE29_GTFSM_MASK) /*! @} */ /*! @name GATE28 - Gate */ /*! @{ */ #define SEMA42_GATE28_GTFSM_MASK (0xFU) #define SEMA42_GATE28_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE28_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE28_GTFSM_SHIFT)) & SEMA42_GATE28_GTFSM_MASK) /*! @} */ /*! @name GATE35 - Gate */ /*! @{ */ #define SEMA42_GATE35_GTFSM_MASK (0xFU) #define SEMA42_GATE35_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE35_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE35_GTFSM_SHIFT)) & SEMA42_GATE35_GTFSM_MASK) /*! @} */ /*! @name GATE34 - Gate */ /*! @{ */ #define SEMA42_GATE34_GTFSM_MASK (0xFU) #define SEMA42_GATE34_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE34_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE34_GTFSM_SHIFT)) & SEMA42_GATE34_GTFSM_MASK) /*! @} */ /*! @name GATE33 - Gate */ /*! @{ */ #define SEMA42_GATE33_GTFSM_MASK (0xFU) #define SEMA42_GATE33_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE33_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE33_GTFSM_SHIFT)) & SEMA42_GATE33_GTFSM_MASK) /*! @} */ /*! @name GATE32 - Gate */ /*! @{ */ #define SEMA42_GATE32_GTFSM_MASK (0xFU) #define SEMA42_GATE32_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE32_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE32_GTFSM_SHIFT)) & SEMA42_GATE32_GTFSM_MASK) /*! @} */ /*! @name GATE39 - Gate */ /*! @{ */ #define SEMA42_GATE39_GTFSM_MASK (0xFU) #define SEMA42_GATE39_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE39_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE39_GTFSM_SHIFT)) & SEMA42_GATE39_GTFSM_MASK) /*! @} */ /*! @name GATE38 - Gate */ /*! @{ */ #define SEMA42_GATE38_GTFSM_MASK (0xFU) #define SEMA42_GATE38_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE38_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE38_GTFSM_SHIFT)) & SEMA42_GATE38_GTFSM_MASK) /*! @} */ /*! @name GATE37 - Gate */ /*! @{ */ #define SEMA42_GATE37_GTFSM_MASK (0xFU) #define SEMA42_GATE37_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE37_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE37_GTFSM_SHIFT)) & SEMA42_GATE37_GTFSM_MASK) /*! @} */ /*! @name GATE36 - Gate */ /*! @{ */ #define SEMA42_GATE36_GTFSM_MASK (0xFU) #define SEMA42_GATE36_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE36_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE36_GTFSM_SHIFT)) & SEMA42_GATE36_GTFSM_MASK) /*! @} */ /*! @name GATE43 - Gate */ /*! @{ */ #define SEMA42_GATE43_GTFSM_MASK (0xFU) #define SEMA42_GATE43_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE43_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE43_GTFSM_SHIFT)) & SEMA42_GATE43_GTFSM_MASK) /*! @} */ /*! @name GATE42 - Gate */ /*! @{ */ #define SEMA42_GATE42_GTFSM_MASK (0xFU) #define SEMA42_GATE42_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE42_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE42_GTFSM_SHIFT)) & SEMA42_GATE42_GTFSM_MASK) /*! @} */ /*! @name GATE41 - Gate */ /*! @{ */ #define SEMA42_GATE41_GTFSM_MASK (0xFU) #define SEMA42_GATE41_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE41_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE41_GTFSM_SHIFT)) & SEMA42_GATE41_GTFSM_MASK) /*! @} */ /*! @name GATE40 - Gate */ /*! @{ */ #define SEMA42_GATE40_GTFSM_MASK (0xFU) #define SEMA42_GATE40_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE40_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE40_GTFSM_SHIFT)) & SEMA42_GATE40_GTFSM_MASK) /*! @} */ /*! @name GATE47 - Gate */ /*! @{ */ #define SEMA42_GATE47_GTFSM_MASK (0xFU) #define SEMA42_GATE47_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE47_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE47_GTFSM_SHIFT)) & SEMA42_GATE47_GTFSM_MASK) /*! @} */ /*! @name GATE46 - Gate */ /*! @{ */ #define SEMA42_GATE46_GTFSM_MASK (0xFU) #define SEMA42_GATE46_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE46_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE46_GTFSM_SHIFT)) & SEMA42_GATE46_GTFSM_MASK) /*! @} */ /*! @name GATE45 - Gate */ /*! @{ */ #define SEMA42_GATE45_GTFSM_MASK (0xFU) #define SEMA42_GATE45_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE45_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE45_GTFSM_SHIFT)) & SEMA42_GATE45_GTFSM_MASK) /*! @} */ /*! @name GATE44 - Gate */ /*! @{ */ #define SEMA42_GATE44_GTFSM_MASK (0xFU) #define SEMA42_GATE44_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE44_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE44_GTFSM_SHIFT)) & SEMA42_GATE44_GTFSM_MASK) /*! @} */ /*! @name GATE51 - Gate */ /*! @{ */ #define SEMA42_GATE51_GTFSM_MASK (0xFU) #define SEMA42_GATE51_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE51_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE51_GTFSM_SHIFT)) & SEMA42_GATE51_GTFSM_MASK) /*! @} */ /*! @name GATE50 - Gate */ /*! @{ */ #define SEMA42_GATE50_GTFSM_MASK (0xFU) #define SEMA42_GATE50_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE50_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE50_GTFSM_SHIFT)) & SEMA42_GATE50_GTFSM_MASK) /*! @} */ /*! @name GATE49 - Gate */ /*! @{ */ #define SEMA42_GATE49_GTFSM_MASK (0xFU) #define SEMA42_GATE49_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE49_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE49_GTFSM_SHIFT)) & SEMA42_GATE49_GTFSM_MASK) /*! @} */ /*! @name GATE48 - Gate */ /*! @{ */ #define SEMA42_GATE48_GTFSM_MASK (0xFU) #define SEMA42_GATE48_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE48_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE48_GTFSM_SHIFT)) & SEMA42_GATE48_GTFSM_MASK) /*! @} */ /*! @name GATE55 - Gate */ /*! @{ */ #define SEMA42_GATE55_GTFSM_MASK (0xFU) #define SEMA42_GATE55_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE55_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE55_GTFSM_SHIFT)) & SEMA42_GATE55_GTFSM_MASK) /*! @} */ /*! @name GATE54 - Gate */ /*! @{ */ #define SEMA42_GATE54_GTFSM_MASK (0xFU) #define SEMA42_GATE54_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE54_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE54_GTFSM_SHIFT)) & SEMA42_GATE54_GTFSM_MASK) /*! @} */ /*! @name GATE53 - Gate */ /*! @{ */ #define SEMA42_GATE53_GTFSM_MASK (0xFU) #define SEMA42_GATE53_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE53_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE53_GTFSM_SHIFT)) & SEMA42_GATE53_GTFSM_MASK) /*! @} */ /*! @name GATE52 - Gate */ /*! @{ */ #define SEMA42_GATE52_GTFSM_MASK (0xFU) #define SEMA42_GATE52_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE52_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE52_GTFSM_SHIFT)) & SEMA42_GATE52_GTFSM_MASK) /*! @} */ /*! @name GATE59 - Gate */ /*! @{ */ #define SEMA42_GATE59_GTFSM_MASK (0xFU) #define SEMA42_GATE59_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE59_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE59_GTFSM_SHIFT)) & SEMA42_GATE59_GTFSM_MASK) /*! @} */ /*! @name GATE58 - Gate */ /*! @{ */ #define SEMA42_GATE58_GTFSM_MASK (0xFU) #define SEMA42_GATE58_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE58_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE58_GTFSM_SHIFT)) & SEMA42_GATE58_GTFSM_MASK) /*! @} */ /*! @name GATE57 - Gate */ /*! @{ */ #define SEMA42_GATE57_GTFSM_MASK (0xFU) #define SEMA42_GATE57_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE57_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE57_GTFSM_SHIFT)) & SEMA42_GATE57_GTFSM_MASK) /*! @} */ /*! @name GATE56 - Gate */ /*! @{ */ #define SEMA42_GATE56_GTFSM_MASK (0xFU) #define SEMA42_GATE56_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE56_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE56_GTFSM_SHIFT)) & SEMA42_GATE56_GTFSM_MASK) /*! @} */ /*! @name GATE63 - Gate */ /*! @{ */ #define SEMA42_GATE63_GTFSM_MASK (0xFU) #define SEMA42_GATE63_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE63_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE63_GTFSM_SHIFT)) & SEMA42_GATE63_GTFSM_MASK) /*! @} */ /*! @name GATE62 - Gate */ /*! @{ */ #define SEMA42_GATE62_GTFSM_MASK (0xFU) #define SEMA42_GATE62_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE62_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE62_GTFSM_SHIFT)) & SEMA42_GATE62_GTFSM_MASK) /*! @} */ /*! @name GATE61 - Gate */ /*! @{ */ #define SEMA42_GATE61_GTFSM_MASK (0xFU) #define SEMA42_GATE61_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE61_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE61_GTFSM_SHIFT)) & SEMA42_GATE61_GTFSM_MASK) /*! @} */ /*! @name GATE60 - Gate */ /*! @{ */ #define SEMA42_GATE60_GTFSM_MASK (0xFU) #define SEMA42_GATE60_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine * 0b0000..The gate is unlocked (free). * 0b0001..Domain 0 locked the gate. * 0b0010..Domain 1 locked the gate. * 0b0011..Domain 2 locked the gate. * 0b0100..Domain 3 locked the gate. * 0b0101..Domain 4 locked the gate. * 0b0110..Domain 5 locked the gate. * 0b0111..Domain 6 locked the gate. * 0b1000..Domain 7 locked the gate. * 0b1001..Domain 8 locked the gate. * 0b1010..Domain 9 locked the gate. * 0b1011..Domain 10 locked the gate. * 0b1100..Domain 11 locked the gate. * 0b1101..Domain 12 locked the gate. * 0b1110..Domain 13 locked the gate. * 0b1111..Domain 14 locked the gate. */ #define SEMA42_GATE60_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA42_GATE60_GTFSM_SHIFT)) & SEMA42_GATE60_GTFSM_MASK) /*! @} */ /*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ #define SEMA42_RSTGT_R_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_R_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ #define SEMA42_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGTN_SHIFT)) & SEMA42_RSTGT_R_RSTGTN_MASK) #define SEMA42_RSTGT_R_RSTGMS_MASK (0xF00U) #define SEMA42_RSTGT_R_RSTGMS_SHIFT (8U) /*! RSTGMS - Reset Gate Domain */ #define SEMA42_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGMS_SHIFT)) & SEMA42_RSTGT_R_RSTGMS_MASK) #define SEMA42_RSTGT_R_RSTGSM_MASK (0x3000U) #define SEMA42_RSTGT_R_RSTGSM_SHIFT (12U) /*! RSTGSM - Reset Gate Finite State Machine * 0b00..Idle, waiting for the first data pattern write. * 0b01..Waiting for the second data pattern write * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, * this machine returns to the idle (waiting for first data pattern write) state. * 0b11..This state encoding is never used and therefore reserved. */ #define SEMA42_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_R_RSTGSM_SHIFT)) & SEMA42_RSTGT_R_RSTGSM_MASK) /*! @} */ /*! @name RSTGT_W - Reset Gate Write */ /*! @{ */ #define SEMA42_RSTGT_W_RSTGTN_MASK (0xFFU) #define SEMA42_RSTGT_W_RSTGTN_SHIFT (0U) /*! RSTGTN - Reset Gate Number */ #define SEMA42_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGTN_SHIFT)) & SEMA42_RSTGT_W_RSTGTN_MASK) #define SEMA42_RSTGT_W_RSTGDP_MASK (0xFF00U) #define SEMA42_RSTGT_W_RSTGDP_SHIFT (8U) /*! RSTGDP - Reset Gate Data Pattern */ #define SEMA42_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA42_RSTGT_W_RSTGDP_SHIFT)) & SEMA42_RSTGT_W_RSTGDP_MASK) /*! @} */ /*! * @} */ /* end of group SEMA42_Register_Masks */ /* SEMA42 - Peripheral instance base addresses */ /** Peripheral SEMA42_1 base address */ #define SEMA42_1_BASE (0x44260000u) /** Peripheral SEMA42_1 base pointer */ #define SEMA42_1 ((SEMA42_Type *)SEMA42_1_BASE) /** Peripheral SEMA42_2 base address */ #define SEMA42_2_BASE (0x42450000u) /** Peripheral SEMA42_2 base pointer */ #define SEMA42_2 ((SEMA42_Type *)SEMA42_2_BASE) /** Array initializer of SEMA42 peripheral base addresses */ #define SEMA42_BASE_ADDRS { 0u, SEMA42_1_BASE, SEMA42_2_BASE } /** Array initializer of SEMA42 peripheral base pointers */ #define SEMA42_BASE_PTRS { (SEMA42_Type *)0u, SEMA42_1, SEMA42_2 } /*! * @} */ /* end of group SEMA42_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SRC_GENERAL_REG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_GENERAL_REG_Peripheral_Access_Layer SRC_GENERAL_REG Peripheral Access Layer * @{ */ /** SRC_GENERAL_REG - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t AUTHEN_CTRL; /**< Authentication Control, offset: 0x4 */ uint8_t RESERVED_1[12]; __IO uint32_t SRTMR; /**< SRC Reset Trigger Mode Register, offset: 0x14 */ __IO uint32_t SRMASK; /**< SRC Reset Trigger Mode Mask Register, offset: 0x18 */ uint8_t RESERVED_2[36]; __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x40 */ __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x44 */ uint8_t RESERVED_3[4]; __IO uint32_t SMRSR; /**< SRC Mix Slices Reset Status Register, offset: 0x4C */ __IO uint32_t SRESR; /**< SRC Reset Event Status Register, offset: 0x50 */ __IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x54 */ __IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x58 */ __IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x5C */ __IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x60 */ __IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x64 */ __IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x68 */ __IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x6C */ __IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x70 */ __IO uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x74 */ __IO uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x78 */ __IO uint32_t GPR11; /**< SRC General Purpose Register 11, offset: 0x7C */ __IO uint32_t GPR12; /**< SRC General Purpose Register 12, offset: 0x80 */ __IO uint32_t GPR13; /**< SRC General Purpose Register 13, offset: 0x84 */ __IO uint32_t GPR14; /**< SRC General Purpose Register 14, offset: 0x88 */ __IO uint32_t GPR15; /**< SRC General Purpose Register 16, offset: 0x8C */ __IO uint32_t GPR16; /**< SRC General Purpose Register 16, offset: 0x90 */ __IO uint32_t GPR17; /**< SRC General Purpose Register 17, offset: 0x94 */ __IO uint32_t GPR18; /**< SRC General Purpose Register 18, offset: 0x98 */ __IO uint32_t GPR19; /**< SRC General Purpose Register 19, offset: 0x9C */ uint8_t RESERVED_4[96]; __IO uint32_t GPR20; /**< SRC General Purpose Register 20, offset: 0x100 */ __IO uint32_t CM_QUIESCE; /**< SRC_CORTEX_M_QUIESCE, offset: 0x104 */ __IO uint32_t COLD_RESET_SSAR_ACK_CTRL; /**< Cold reset SSAR acknowledge control, offset: 0x108 */ uint8_t RESERVED_5[4]; __IO uint32_t ROM_LP_CTRL; /**< ROM Low Power Control, offset: 0x110 */ __I uint32_t A55_DENY_STAT; /**< A55 Q_Channel Deny Status, offset: 0x114 */ __IO uint32_t EVENT_RESET_SYSMAN_ACK_CTRL; /**< Event Reset SYSMAN acknowledge control, offset: 0x118 */ uint8_t RESERVED_6[4]; __IO uint32_t SRMR[14]; /**< SRC Reset Mode Register (SRMR), array offset: 0x120, array step: 0x4 */ uint8_t RESERVED_7[104]; __IO uint32_t SRDR; /**< SRC Reset Disable Register, offset: 0x1C0 */ } SRC_GENERAL_REG_Type; /* ---------------------------------------------------------------------------- -- SRC_GENERAL_REG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_GENERAL_REG_Register_Masks SRC_GENERAL_REG Register Masks * @{ */ /*! @name AUTHEN_CTRL - Authentication Control */ /*! @{ */ #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) /*! LOCK_CFG - Configuration lock * 0b0..General registers are not locked. * 0b1..LOCK_CFG and registers in the list are locked. */ #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_CFG_MASK) #define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_MASK (0x100U) #define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_SHIFT (8U) /*! TZ_USER - Allow user mode access * 0b0..General registers can only be written in privilege mode. * 0b1..General registers can be written either in privilege mode or user mode. */ #define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_TZ_USER_MASK) #define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_MASK (0x200U) #define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_SHIFT (9U) /*! TZ_NS - Allow non-secure mode access * 0b0..General registers can only be written in secure mode. * 0b1..General registers can be written either in secure mode or non-secure mode. */ #define SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_TZ_NS_MASK) #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_MASK (0x800U) #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock TZ_NS and TZ_USER bits * 0b0..TZ_NS and TZ_USER value can be changed. * 0b1..LOCK_TZ, TZ_NS and TZ_USER value cannot be changed. */ #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_TZ_MASK) #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - White list lock * 0b0..WHITE_LIST value can be changed. * 0b1..LOCK_LIST and WHITE_LIST value cannot be changed. */ #define SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_LOCK_LIST_MASK) #define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) #define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list * 0b0000000000000001..Core with domain ID=0 can write General registers. * 0b0000000000000010..Core with domain ID=1 can write General registers. * 0b0000000000000100..Core with domain ID=2 can write General registers. * 0b0000000000001000..Core with domain ID=3 can write General registers. * 0b0000000000010000..Core with domain ID=4 can write General registers. * 0b0000000000100000..Core with domain ID=5 can write General registers. * 0b0000000001000000..Core with domain ID=6 can write General registers. * 0b0000000010000000..Core with domain ID=7 can write General registers. * 0b0000000100000000..Core with domain ID=8 can write General registers. * 0b0000001000000000..Core with domain ID=9 can write General registers. * 0b0000010000000000..Core with domain ID=10 can write General registers. * 0b0000100000000000..Core with domain ID=11 can write General registers. * 0b0001000000000000..Core with domain ID=12 can write General registers. * 0b0010000000000000..Core with domain ID=13 can write General registers. * 0b0100000000000000..Core with domain ID=14 can write General registers. * 0b1000000000000000..Core with domain ID=16 can write General registers. */ #define SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_GENERAL_REG_AUTHEN_CTRL_WHITE_LIST_MASK) /*! @} */ /*! @name SRTMR - SRC Reset Trigger Mode Register */ /*! @{ */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_0_MODE_MASK (0x1U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_0_MODE_SHIFT (0U) /*! RST_EVT_0_MODE - mode configuration bit for reset event CM33_LOCKUP_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as CM33_LOCKUP_RST_EVT is active * 0b1..edge mode : affected region enters reset when CM33_LOCKUP_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_0_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_0_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_0_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_1_MODE_MASK (0x2U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_1_MODE_SHIFT (1U) /*! RST_EVT_1_MODE - mode configuration bit for reset event CM33_SYS_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as CM33_SYS_RST_EVT is active * 0b1..edge mode : affected region enters reset when CM33_SYS_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_1_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_1_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_1_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_2_MODE_MASK (0x4U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_2_MODE_SHIFT (2U) /*! RST_EVT_2_MODE - mode configuration bit for reset event CM7_LOCKUP_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as CM7_LOCKUP_RST_EVT is active * 0b1..edge mode : affected region enters reset when CM7_LOCKUP_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_2_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_2_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_2_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_3_MODE_MASK (0x8U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_3_MODE_SHIFT (3U) /*! RST_EVT_3_MODE - mode configuration bit for reset event CM7_SYS_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as CM7_SYS_RST_EVT is active * 0b1..edge mode : affected region enters reset when CM7_SYS_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_3_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_3_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_3_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_4_MODE_MASK (0x10U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_4_MODE_SHIFT (4U) /*! RST_EVT_4_MODE - mode configuration bit for reset event FCCU_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as FCCU_RST_EVT is active * 0b1..edge mode : affected region enters reset when FCCU_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_4_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_4_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_4_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_5_MODE_MASK (0x20U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_5_MODE_SHIFT (5U) /*! RST_EVT_5_MODE - mode configuration bit for reset event JTAG_SW_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as JTAG_SW_RST_EVT is active * 0b1..edge mode : affected region enters reset when JTAG_SW_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_5_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_5_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_5_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_6_MODE_MASK (0x40U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_6_MODE_SHIFT (6U) /*! RST_EVT_6_MODE - mode configuration bit for reset event ELE_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as ELE_RST_EVT is active * 0b1..edge mode : affected region enters reset when ELE_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_6_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_6_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_6_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_7_MODE_MASK (0x80U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_7_MODE_SHIFT (7U) /*! RST_EVT_7_MODE - mode configuration bit for reset event TEMPSENSE_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as TEMPSENSE_RST_EVT is active * 0b1..edge mode : affected region enters reset when TEMPSENSE_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_7_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_7_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_7_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_8_MODE_MASK (0x100U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_8_MODE_SHIFT (8U) /*! RST_EVT_8_MODE - mode configuration bit for reset event WDOG1_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as WDOG1_RST_EVT is active * 0b1..edge mode : affected region enters reset when WDOG1_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_8_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_8_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_8_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_9_MODE_MASK (0x200U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_9_MODE_SHIFT (9U) /*! RST_EVT_9_MODE - mode configuration bit for reset event WDOG2_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as WDOG2_RST_EVT is active * 0b1..edge mode : affected region enters reset when WDOG2_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_9_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_9_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_9_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_10_MODE_MASK (0x400U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_10_MODE_SHIFT (10U) /*! RST_EVT_10_MODE - mode configuration bit for reset event WDOG3_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as WDOG3_RST_EVT is active * 0b1..edge mode : affected region enters reset when WDOG3_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_10_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_10_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_10_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_11_MODE_MASK (0x800U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_11_MODE_SHIFT (11U) /*! RST_EVT_11_MODE - mode configuration bit for reset event WDOG4_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as WDOG4_RST_EVT is active * 0b1..edge mode : affected region enters reset when WDOG4_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_11_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_11_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_11_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_12_MODE_MASK (0x1000U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_12_MODE_SHIFT (12U) /*! RST_EVT_12_MODE - mode configuration bit for reset event WDOG5_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as WDOG5_RST_EVT is active * 0b1..edge mode : affected region enters reset when WDOG5_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_12_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_12_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_12_MODE_MASK) #define SRC_GENERAL_REG_SRTMR_RST_EVT_13_MODE_MASK (0x2000U) #define SRC_GENERAL_REG_SRTMR_RST_EVT_13_MODE_SHIFT (13U) /*! RST_EVT_13_MODE - mode configuration bit for reset event JTAG_RST_B_RST_EVT * 0b0..level mode : affected region enters and stays in reset as long as JTAG_RST_B_RST_EVT is active * 0b1..edge mode : affected region enters reset when JTAG_RST_B_RST_EVT becomes active and will leave reset even if event is active */ #define SRC_GENERAL_REG_SRTMR_RST_EVT_13_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRTMR_RST_EVT_13_MODE_SHIFT)) & SRC_GENERAL_REG_SRTMR_RST_EVT_13_MODE_MASK) /*! @} */ /*! @name SRMASK - SRC Reset Trigger Mode Mask Register */ /*! @{ */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_0_MASK_MASK (0x1U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_0_MASK_SHIFT (0U) /*! RST_EVT_0_MASK - mask bit for reset event CM33_LOCKUP_RST_EVT * 0b0..reset event CM33_LOCKUP_RST_EVT is not masked * 0b1..reset event CM33_LOCKUP_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_0_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_0_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_0_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_1_MASK_MASK (0x2U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_1_MASK_SHIFT (1U) /*! RST_EVT_1_MASK - mask bit for reset event CM33_SYS_RST_EVT * 0b0..reset event CM33_SYS_RST_EVT is not masked * 0b1..reset event CM33_SYS_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_1_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_1_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_1_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_2_MASK_MASK (0x4U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_2_MASK_SHIFT (2U) /*! RST_EVT_2_MASK - mask bit for reset event CM7_LOCKUP_RST_EVT * 0b0..reset event CM7_LOCKUP_RST_EVT is not masked * 0b1..reset event CM7_LOCKUP_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_2_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_2_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_2_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_3_MASK_MASK (0x8U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_3_MASK_SHIFT (3U) /*! RST_EVT_3_MASK - mask bit for reset event CM7_SYS_RST_EVT * 0b0..reset event CM7_SYS_RST_EVT is not masked * 0b1..reset event CM7_SYS_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_3_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_3_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_3_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_4_MASK_MASK (0x10U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_4_MASK_SHIFT (4U) /*! RST_EVT_4_MASK - mask bit for reset event FCCU_RST_EVT * 0b0..reset event FCCU_RST_EVT is not masked * 0b1..reset event FCCU_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_4_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_4_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_4_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_5_MASK_MASK (0x20U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_5_MASK_SHIFT (5U) /*! RST_EVT_5_MASK - mask bit for reset event JTAG_SW_RST_EVT * 0b0..reset event JTAG_SW_RST_EVT is not masked * 0b1..reset event JTAG_SW_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_5_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_5_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_5_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_6_MASK_MASK (0x40U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_6_MASK_SHIFT (6U) /*! RST_EVT_6_MASK - mask bit for reset event ELE_RST_EVT * 0b0..reset event ELE_RST_EVT is not masked * 0b1..reset event ELE_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_6_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_6_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_6_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_7_MASK_MASK (0x80U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_7_MASK_SHIFT (7U) /*! RST_EVT_7_MASK - mask bit for reset event TEMPSENSE_RST_EVT * 0b0..reset event TEMPSENSE_RST_EVT is not masked * 0b1..reset event TEMPSENSE_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_7_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_7_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_7_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_8_MASK_MASK (0x100U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_8_MASK_SHIFT (8U) /*! RST_EVT_8_MASK - mask bit for reset event WDOG1_RST_EVT * 0b0..reset event WDOG1_RST_EVT is not masked * 0b1..reset event WDOG1_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_8_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_8_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_8_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_9_MASK_MASK (0x200U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_9_MASK_SHIFT (9U) /*! RST_EVT_9_MASK - mask bit for reset event WDOG2_RST_EVT * 0b0..reset event WDOG2_RST_EVT is not masked * 0b1..reset event WDOG2_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_9_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_9_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_9_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_10_MASK_MASK (0x400U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_10_MASK_SHIFT (10U) /*! RST_EVT_10_MASK - mask bit for reset event WDOG3_RST_EVT * 0b0..reset event WDOG3_RST_EVT is not masked * 0b1..reset event WDOG3_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_10_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_10_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_10_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_11_MASK_MASK (0x800U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_11_MASK_SHIFT (11U) /*! RST_EVT_11_MASK - mask bit for reset event WDOG4_RST_EVT * 0b0..reset event WDOG4_RST_EVT is not masked * 0b1..reset event WDOG4_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_11_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_11_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_11_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_12_MASK_MASK (0x1000U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_12_MASK_SHIFT (12U) /*! RST_EVT_12_MASK - mask bit for reset event WDOG5_RST_EVT * 0b0..reset event WDOG5_RST_EVT is not masked * 0b1..reset event WDOG5_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_12_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_12_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_12_MASK_MASK) #define SRC_GENERAL_REG_SRMASK_RST_EVT_13_MASK_MASK (0x2000U) #define SRC_GENERAL_REG_SRMASK_RST_EVT_13_MASK_SHIFT (13U) /*! RST_EVT_13_MASK - mask bit for reset event JTAG_RST_B_RST_EVT * 0b0..reset event JTAG_RST_B_RST_EVT is not masked * 0b1..reset event JTAG_RST_B_RST_EVT is masked */ #define SRC_GENERAL_REG_SRMASK_RST_EVT_13_MASK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMASK_RST_EVT_13_MASK_SHIFT)) & SRC_GENERAL_REG_SRMASK_RST_EVT_13_MASK_MASK) /*! @} */ /*! @name SBMR1 - SRC Boot Mode Register 1 */ /*! @{ */ #define SRC_GENERAL_REG_SBMR1_BOOT_CFG0_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_SBMR1_BOOT_CFG0_SHIFT (0U) /*! BOOT_CFG0 - This bit field stores the BOOT_CFG8 fuse values. Please refer to the Fusemap for the fuse details. */ #define SRC_GENERAL_REG_SBMR1_BOOT_CFG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR1_BOOT_CFG0_SHIFT)) & SRC_GENERAL_REG_SBMR1_BOOT_CFG0_MASK) /*! @} */ /*! @name SBMR2 - SRC Boot Mode Register 2 */ /*! @{ */ #define SRC_GENERAL_REG_SBMR2_BOOT_CFG1_MASK (0xFFFFU) #define SRC_GENERAL_REG_SBMR2_BOOT_CFG1_SHIFT (0U) /*! BOOT_CFG1 - This bit field stores the BOOT_CFG0[16:0] fuse values. Please refer to the Fusemap for the fuse details. */ #define SRC_GENERAL_REG_SBMR2_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_BOOT_CFG1_SHIFT)) & SRC_GENERAL_REG_SBMR2_BOOT_CFG1_MASK) #define SRC_GENERAL_REG_SBMR2_SDP_DIS_MASK (0x10000U) #define SRC_GENERAL_REG_SBMR2_SDP_DIS_SHIFT (16U) /*! SDP_DIS - Stores the value of SDP_DIS from fusemap. Please see the fusemap for fuse details. */ #define SRC_GENERAL_REG_SBMR2_SDP_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_SDP_DIS_SHIFT)) & SRC_GENERAL_REG_SBMR2_SDP_DIS_MASK) #define SRC_GENERAL_REG_SBMR2_BOOT_CFG2_MASK (0x3C0000U) #define SRC_GENERAL_REG_SBMR2_BOOT_CFG2_SHIFT (18U) /*! BOOT_CFG2 - This bit field stores the BOOT_CFG0[31:28] fuse values. Please refer to the Fusemap for the fuse details. */ #define SRC_GENERAL_REG_SBMR2_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_BOOT_CFG2_SHIFT)) & SRC_GENERAL_REG_SBMR2_BOOT_CFG2_MASK) #define SRC_GENERAL_REG_SBMR2_CCMSRCGPCMIX_BLK_CTRL_MASK (0xC00000U) #define SRC_GENERAL_REG_SBMR2_CCMSRCGPCMIX_BLK_CTRL_SHIFT (22U) /*! CCMSRCGPCMIX_BLK_CTRL - Stores the value of CCMSRCGPCMIX_BLK_CTRL[1:0] from fusemap. Please see the fusemap for fuse details. */ #define SRC_GENERAL_REG_SBMR2_CCMSRCGPCMIX_BLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_CCMSRCGPCMIX_BLK_CTRL_SHIFT)) & SRC_GENERAL_REG_SBMR2_CCMSRCGPCMIX_BLK_CTRL_MASK) #define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_MASK (0x3F000000U) #define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_SHIFT (24U) /*! IPP_BOOT_MODE - Boot mode from pins */ #define SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_GENERAL_REG_SBMR2_IPP_BOOT_MODE_MASK) #define SRC_GENERAL_REG_SBMR2_DIR_BT_DIS_MASK (0x80000000U) #define SRC_GENERAL_REG_SBMR2_DIR_BT_DIS_SHIFT (31U) /*! DIR_BT_DIS - Stores the value of DIR_BT_DIS from fusemap. Please see the fusemap for fuse details. */ #define SRC_GENERAL_REG_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_GENERAL_REG_SBMR2_DIR_BT_DIS_MASK) /*! @} */ /*! @name SMRSR - SRC Mix Slices Reset Status Register */ /*! @{ */ #define SRC_GENERAL_REG_SMRSR_RESET_DOMAIN_FLAG_MASK (0x1FFFFFFFU) #define SRC_GENERAL_REG_SMRSR_RESET_DOMAIN_FLAG_SHIFT (0U) /*! RESET_DOMAIN_FLAG - Indicates which reset event request asserted the reset */ #define SRC_GENERAL_REG_SMRSR_RESET_DOMAIN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SMRSR_RESET_DOMAIN_FLAG_SHIFT)) & SRC_GENERAL_REG_SMRSR_RESET_DOMAIN_FLAG_MASK) /*! @} */ /*! @name SRESR - SRC Reset Event Status Register */ /*! @{ */ #define SRC_GENERAL_REG_SRESR_RST_EVT_0_FLAG_MASK (0x1U) #define SRC_GENERAL_REG_SRESR_RST_EVT_0_FLAG_SHIFT (0U) /*! RST_EVT_0_FLAG - CM33_LOCKUP_RST_EVT reset event flag * 0b0..CM33_LOCKUP_RST_EVT reset event not occurred * 0b1..CM33_LOCKUP_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_0_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_0_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_1_FLAG_MASK (0x2U) #define SRC_GENERAL_REG_SRESR_RST_EVT_1_FLAG_SHIFT (1U) /*! RST_EVT_1_FLAG - CM33_SYS_RST_EVT reset event flag * 0b0..CM33_SYS_RST_EVT reset event not occurred * 0b1..CM33_SYS_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_1_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_1_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_2_FLAG_MASK (0x4U) #define SRC_GENERAL_REG_SRESR_RST_EVT_2_FLAG_SHIFT (2U) /*! RST_EVT_2_FLAG - CM7_LOCKUP_RST_EVT reset event flag * 0b0..CM7_LOCKUP_RST_EVT reset event not occurred * 0b1..CM7_LOCKUP_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_2_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_2_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_2_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_3_FLAG_MASK (0x8U) #define SRC_GENERAL_REG_SRESR_RST_EVT_3_FLAG_SHIFT (3U) /*! RST_EVT_3_FLAG - CM7_SYS_RST_EVT reset event flag * 0b0..CM7_SYS_RST_EVT reset event not occurred * 0b1..CM7_SYS_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_3_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_3_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_3_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_4_FLAG_MASK (0x10U) #define SRC_GENERAL_REG_SRESR_RST_EVT_4_FLAG_SHIFT (4U) /*! RST_EVT_4_FLAG - FCCU_RST_EVT reset event flag * 0b0..FCCU_RST_EVT reset event not occurred * 0b1..FCCU_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_4_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_4_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_4_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_5_FLAG_MASK (0x20U) #define SRC_GENERAL_REG_SRESR_RST_EVT_5_FLAG_SHIFT (5U) /*! RST_EVT_5_FLAG - JTAG_SW_RST_EVT reset event flag * 0b0..JTAG_SW_RST_EVT reset event not occurred * 0b1..JTAG_SW_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_5_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_5_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_5_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_6_FLAG_MASK (0x40U) #define SRC_GENERAL_REG_SRESR_RST_EVT_6_FLAG_SHIFT (6U) /*! RST_EVT_6_FLAG - ELE_RST_EVT reset event flag * 0b0..ELE_RST_EVT reset event not occurred * 0b1..ELE_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_6_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_6_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_6_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_7_FLAG_MASK (0x80U) #define SRC_GENERAL_REG_SRESR_RST_EVT_7_FLAG_SHIFT (7U) /*! RST_EVT_7_FLAG - TEMPSENSE_RST_EVT reset event flag * 0b0..TEMPSENSE_RST_EVT reset event not occurred * 0b1..TEMPSENSE_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_7_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_7_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_7_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_8_FLAG_MASK (0x100U) #define SRC_GENERAL_REG_SRESR_RST_EVT_8_FLAG_SHIFT (8U) /*! RST_EVT_8_FLAG - WDOG1_RST_EVT reset event flag * 0b0..WDOG1_RST_EVT reset event not occurred * 0b1..WDOG1_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_8_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_8_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_8_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_9_FLAG_MASK (0x200U) #define SRC_GENERAL_REG_SRESR_RST_EVT_9_FLAG_SHIFT (9U) /*! RST_EVT_9_FLAG - WDOG2_RST_EVT reset event flag * 0b0..WDOG2_RST_EVT reset event not occurred * 0b1..WDOG2_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_9_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_9_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_9_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_10_FLAG_MASK (0x400U) #define SRC_GENERAL_REG_SRESR_RST_EVT_10_FLAG_SHIFT (10U) /*! RST_EVT_10_FLAG - WDOG3_RST_EVT reset event flag * 0b0..WDOG3_RST_EVT reset event not occurred * 0b1..WDOG3_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_10_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_10_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_10_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_11_FLAG_MASK (0x800U) #define SRC_GENERAL_REG_SRESR_RST_EVT_11_FLAG_SHIFT (11U) /*! RST_EVT_11_FLAG - WDOG4_RST_EVT reset event flag * 0b0..WDOG4_RST_EVT reset event not occurred * 0b1..WDOG4_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_11_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_11_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_11_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_12_FLAG_MASK (0x1000U) #define SRC_GENERAL_REG_SRESR_RST_EVT_12_FLAG_SHIFT (12U) /*! RST_EVT_12_FLAG - WDOG5_RST_EVT reset event flag * 0b0..WDOG5_RST_EVT reset event not occurred * 0b1..WDOG5_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_12_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_12_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_12_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_RST_EVT_13_FLAG_MASK (0x2000U) #define SRC_GENERAL_REG_SRESR_RST_EVT_13_FLAG_SHIFT (13U) /*! RST_EVT_13_FLAG - JTAG_RST_B_RST_EVT reset event flag * 0b0..JTAG_RST_B_RST_EVT reset event not occurred * 0b1..JTAG_RST_B_RST_EVT reset event occurred */ #define SRC_GENERAL_REG_SRESR_RST_EVT_13_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_RST_EVT_13_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_RST_EVT_13_FLAG_MASK) #define SRC_GENERAL_REG_SRESR_SOC_POR_B_FLAG_MASK (0x80000000U) #define SRC_GENERAL_REG_SRESR_SOC_POR_B_FLAG_SHIFT (31U) /*! SOC_POR_B_FLAG - SOC_POR_B reset flag * 0b0..SOC_POR_B reset not occurred * 0b1..SOC_POR_B reset occurred */ #define SRC_GENERAL_REG_SRESR_SOC_POR_B_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRESR_SOC_POR_B_FLAG_SHIFT)) & SRC_GENERAL_REG_SRESR_SOC_POR_B_FLAG_MASK) /*! @} */ /*! @name GPR1 - SRC General Purpose Register 1 */ /*! @{ */ #define SRC_GENERAL_REG_GPR1_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR1_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR1_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR1_GPR_SHIFT)) & SRC_GENERAL_REG_GPR1_GPR_MASK) /*! @} */ /*! @name GPR2 - SRC General Purpose Register 2 */ /*! @{ */ #define SRC_GENERAL_REG_GPR2_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR2_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR2_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR2_GPR_SHIFT)) & SRC_GENERAL_REG_GPR2_GPR_MASK) /*! @} */ /*! @name GPR3 - SRC General Purpose Register 3 */ /*! @{ */ #define SRC_GENERAL_REG_GPR3_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR3_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR3_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR3_GPR_SHIFT)) & SRC_GENERAL_REG_GPR3_GPR_MASK) /*! @} */ /*! @name GPR4 - SRC General Purpose Register 4 */ /*! @{ */ #define SRC_GENERAL_REG_GPR4_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR4_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR4_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR4_GPR_SHIFT)) & SRC_GENERAL_REG_GPR4_GPR_MASK) /*! @} */ /*! @name GPR5 - SRC General Purpose Register 5 */ /*! @{ */ #define SRC_GENERAL_REG_GPR5_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR5_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR5_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR5_GPR_SHIFT)) & SRC_GENERAL_REG_GPR5_GPR_MASK) /*! @} */ /*! @name GPR6 - SRC General Purpose Register 6 */ /*! @{ */ #define SRC_GENERAL_REG_GPR6_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR6_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR6_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR6_GPR_SHIFT)) & SRC_GENERAL_REG_GPR6_GPR_MASK) /*! @} */ /*! @name GPR7 - SRC General Purpose Register 7 */ /*! @{ */ #define SRC_GENERAL_REG_GPR7_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR7_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR7_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR7_GPR_SHIFT)) & SRC_GENERAL_REG_GPR7_GPR_MASK) /*! @} */ /*! @name GPR8 - SRC General Purpose Register 8 */ /*! @{ */ #define SRC_GENERAL_REG_GPR8_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR8_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR8_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR8_GPR_SHIFT)) & SRC_GENERAL_REG_GPR8_GPR_MASK) /*! @} */ /*! @name GPR9 - SRC General Purpose Register 9 */ /*! @{ */ #define SRC_GENERAL_REG_GPR9_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR9_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR9_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR9_GPR_SHIFT)) & SRC_GENERAL_REG_GPR9_GPR_MASK) /*! @} */ /*! @name GPR10 - SRC General Purpose Register 10 */ /*! @{ */ #define SRC_GENERAL_REG_GPR10_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR10_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR10_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR10_GPR_SHIFT)) & SRC_GENERAL_REG_GPR10_GPR_MASK) /*! @} */ /*! @name GPR11 - SRC General Purpose Register 11 */ /*! @{ */ #define SRC_GENERAL_REG_GPR11_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR11_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR11_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR11_GPR_SHIFT)) & SRC_GENERAL_REG_GPR11_GPR_MASK) /*! @} */ /*! @name GPR12 - SRC General Purpose Register 12 */ /*! @{ */ #define SRC_GENERAL_REG_GPR12_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR12_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR12_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR12_GPR_SHIFT)) & SRC_GENERAL_REG_GPR12_GPR_MASK) /*! @} */ /*! @name GPR13 - SRC General Purpose Register 13 */ /*! @{ */ #define SRC_GENERAL_REG_GPR13_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR13_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR13_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR13_GPR_SHIFT)) & SRC_GENERAL_REG_GPR13_GPR_MASK) /*! @} */ /*! @name GPR14 - SRC General Purpose Register 14 */ /*! @{ */ #define SRC_GENERAL_REG_GPR14_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR14_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR14_GPR_SHIFT)) & SRC_GENERAL_REG_GPR14_GPR_MASK) /*! @} */ /*! @name GPR15 - SRC General Purpose Register 16 */ /*! @{ */ #define SRC_GENERAL_REG_GPR15_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR15_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR15_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR15_GPR_SHIFT)) & SRC_GENERAL_REG_GPR15_GPR_MASK) /*! @} */ /*! @name GPR16 - SRC General Purpose Register 16 */ /*! @{ */ #define SRC_GENERAL_REG_GPR16_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR16_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR16_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR16_GPR_SHIFT)) & SRC_GENERAL_REG_GPR16_GPR_MASK) /*! @} */ /*! @name GPR17 - SRC General Purpose Register 17 */ /*! @{ */ #define SRC_GENERAL_REG_GPR17_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR17_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR17_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR17_GPR_SHIFT)) & SRC_GENERAL_REG_GPR17_GPR_MASK) /*! @} */ /*! @name GPR18 - SRC General Purpose Register 18 */ /*! @{ */ #define SRC_GENERAL_REG_GPR18_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR18_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR18_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR18_GPR_SHIFT)) & SRC_GENERAL_REG_GPR18_GPR_MASK) /*! @} */ /*! @name GPR19 - SRC General Purpose Register 19 */ /*! @{ */ #define SRC_GENERAL_REG_GPR19_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR19_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR19_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR19_GPR_SHIFT)) & SRC_GENERAL_REG_GPR19_GPR_MASK) /*! @} */ /*! @name GPR20 - SRC General Purpose Register 20 */ /*! @{ */ #define SRC_GENERAL_REG_GPR20_GPR_MASK (0xFFFFFFFFU) #define SRC_GENERAL_REG_GPR20_GPR_SHIFT (0U) /*! GPR - General purpose register */ #define SRC_GENERAL_REG_GPR20_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_GPR20_GPR_SHIFT)) & SRC_GENERAL_REG_GPR20_GPR_MASK) /*! @} */ /*! @name CM_QUIESCE - SRC_CORTEX_M_QUIESCE */ /*! @{ */ #define SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_REQ_MASK (0x1U) #define SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_REQ_SHIFT (0U) /*! SAFE_CM33_AHB_REQ - CM33 platform safe reset req control * 0b0..No effect * 0b1..request CM33 platform to be reset at safe state */ #define SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_REQ_SHIFT)) & SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_REQ_MASK) #define SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_ACK_STAT_MASK (0x2U) #define SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_ACK_STAT_SHIFT (1U) /*! SAFE_CM33_AHB_ACK_STAT - CM33 platform safe reset ahb ack status * 0b0..No CM33 platform safe reset req or it could not be placed in safe state for reset sequencing * 0b1..CM33 platform is in safe state for reset sequencing */ #define SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_ACK_STAT_SHIFT)) & SRC_GENERAL_REG_CM_QUIESCE_SAFE_CM33_AHB_ACK_STAT_MASK) /*! @} */ /*! @name COLD_RESET_SSAR_ACK_CTRL - Cold reset SSAR acknowledge control */ /*! @{ */ #define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK (0x3FFFU) #define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT (0U) /*! SSAR_CNT_CFG - ssar count configure. Usage depends on CNT_MODE */ #define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT)) & SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK) #define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) #define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_SHIFT (30U) /*! CNT_MODE - Configure the acknowledge counter working mode * 0b00..Not use counter, raise done to cold_reset_controller once get EdgeLock Enclave ack * 0b01..Delay after receiving EdgeLock Enclave ack, delay cycle number is CNT_CFG * 0b10..Ignore EdgeLock Enclave ack, raise done to cold_reset_controller when counting to CNT_CFG value * 0b11..Time out mode, raise done to cold_reset_controller when either EdgeLock Enclave ack received or counting to CNT_CFG value */ #define SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_GENERAL_REG_COLD_RESET_SSAR_ACK_CTRL_CNT_MODE_MASK) /*! @} */ /*! @name ROM_LP_CTRL - ROM Low Power Control */ /*! @{ */ #define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_MASK (0x1U) #define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_SHIFT (0U) /*! AONMIX_ROM_LP_EN - Low power control enable for ROM in AONMIX */ #define SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_SHIFT)) & SRC_GENERAL_REG_ROM_LP_CTRL_AONMIX_ROM_LP_EN_MASK) /*! @} */ /*! @name A55_DENY_STAT - A55 Q_Channel Deny Status */ /*! @{ */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_MASK (0x1U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_SHIFT (0U) /*! A55_CORE0_PWRDN_DENY_STAT - A55 CORE 0 Q_Channel pwrdn deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE0_PWRDN_DENY_STAT_MASK) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE1_PWRDN_DENY_STAT_MASK (0x2U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE1_PWRDN_DENY_STAT_SHIFT (1U) /*! A55_CORE1_PWRDN_DENY_STAT - A55 CORE 1 Q_Channel pwrdn deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE1_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE1_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE1_PWRDN_DENY_STAT_MASK) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE2_PWRDN_DENY_STAT_MASK (0x4U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE2_PWRDN_DENY_STAT_SHIFT (2U) /*! A55_CORE2_PWRDN_DENY_STAT - A55 CORE 2 Q_Channel pwrdn deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE2_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE2_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE2_PWRDN_DENY_STAT_MASK) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE3_PWRDN_DENY_STAT_MASK (0x8U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE3_PWRDN_DENY_STAT_SHIFT (3U) /*! A55_CORE3_PWRDN_DENY_STAT - A55 CORE 3 Q_Channel pwrdn deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE3_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE3_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE3_PWRDN_DENY_STAT_MASK) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE4_PWRDN_DENY_STAT_MASK (0x10U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE4_PWRDN_DENY_STAT_SHIFT (4U) /*! A55_CORE4_PWRDN_DENY_STAT - A55 CORE 4 Q_Channel pwrdn deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE4_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE4_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE4_PWRDN_DENY_STAT_MASK) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE5_PWRDN_DENY_STAT_MASK (0x20U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE5_PWRDN_DENY_STAT_SHIFT (5U) /*! A55_CORE5_PWRDN_DENY_STAT - A55 CORE 5 Q_Channel pwrdn deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE5_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE5_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CORE5_PWRDN_DENY_STAT_MASK) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_MASK (0x40U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_SHIFT (6U) /*! A55_CLUSTER_PWRDN_DENY_STAT - A55 Cluster Q_Channel pwrdn deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_PWRDN_DENY_STAT_MASK) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_MASK (0x80U) #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_SHIFT (7U) /*! A55_CLUSTER_CLKOFF_DENY_STAT - A55 Cluster Q_Channel clockoff deny status */ #define SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_SHIFT)) & SRC_GENERAL_REG_A55_DENY_STAT_A55_CLUSTER_CLKOFF_DENY_STAT_MASK) /*! @} */ /*! @name EVENT_RESET_SYSMAN_ACK_CTRL - Event Reset SYSMAN acknowledge control */ /*! @{ */ #define SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_CFG_MASK (0xFFU) #define SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_CFG_SHIFT (0U) /*! CNT_CFG - sysman count configure. Usage depends on CNT_MODE */ #define SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_CFG_SHIFT)) & SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_CFG_MASK) #define SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) #define SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_MODE_SHIFT (30U) /*! CNT_MODE - Configure the acknowledge counter working mode * 0b00..Not use counter, raise done to cold_reset_controller once get EdgeLock Enclave ack * 0b01..Delay after receiving EdgeLock Enclave ack, delay cycle number is CNT_CFG * 0b10..Ignore EdgeLock Enclave ack, raise done to cold_reset_controller when counting to CNT_CFG value * 0b11..Time out mode, raise done to cold_reset_controller when either EdgeLock Enclave ack received or counting to CNT_CFG value */ #define SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_GENERAL_REG_EVENT_RESET_SYSMAN_ACK_CTRL_CNT_MODE_MASK) /*! @} */ /*! @name SRMR - SRC Reset Mode Register (SRMR) */ /*! @{ */ #define SRC_GENERAL_REG_SRMR_RSTR_0_MASK (0x1U) #define SRC_GENERAL_REG_SRMR_RSTR_0_SHIFT (0U) /*! RSTR_0 - configuration bit for independent reset of reset region ANAMIX by event * 0b0..independent reset of reset region ANAMIX by event is disabled */ #define SRC_GENERAL_REG_SRMR_RSTR_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_0_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_0_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_1_MASK (0x2U) #define SRC_GENERAL_REG_SRMR_RSTR_1_SHIFT (1U) /*! RSTR_1 - configuration bit for independent reset of reset region AONMIX_TOP by event * 0b0..independent reset of reset region AONMIX_TOP by event is disabled * 0b1..independent reset of reset region AONMIX_TOP by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_1_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_1_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_2_MASK (0x4U) #define SRC_GENERAL_REG_SRMR_RSTR_2_SHIFT (2U) /*! RSTR_2 - configuration bit for independent reset of reset region AONMIX_M33 by event * 0b0..independent reset of reset region AONMIX_M33 by event is disabled * 0b1..independent reset of reset region AONMIX_M33 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_2_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_2_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_3_MASK (0x8U) #define SRC_GENERAL_REG_SRMR_RSTR_3_SHIFT (3U) /*! RSTR_3 - configuration bit for independent reset of reset region AONMIX_ELE by event * 0b0..independent reset of reset region AONMIX_ELE by event is disabled */ #define SRC_GENERAL_REG_SRMR_RSTR_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_3_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_3_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_4_MASK (0x10U) #define SRC_GENERAL_REG_SRMR_RSTR_4_SHIFT (4U) /*! RSTR_4 - configuration bit for independent reset of reset region BBSMMIX by event * 0b0..independent reset of reset region BBSMMIX by event is disabled */ #define SRC_GENERAL_REG_SRMR_RSTR_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_4_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_4_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_5_MASK (0x20U) #define SRC_GENERAL_REG_SRMR_RSTR_5_SHIFT (5U) /*! RSTR_5 - configuration bit for independent reset of reset region CAMERAMIX by event * 0b0..independent reset of reset region CAMERAMIX by event is disabled * 0b1..independent reset of reset region CAMERAMIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_5_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_5_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_6_MASK (0x40U) #define SRC_GENERAL_REG_SRMR_RSTR_6_SHIFT (6U) /*! RSTR_6 - configuration bit for independent reset of reset region CCMSRCGPCMIX by event * 0b0..independent reset of reset region CCMSRCGPCMIX by event is disabled */ #define SRC_GENERAL_REG_SRMR_RSTR_6(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_6_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_6_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_7_MASK (0x80U) #define SRC_GENERAL_REG_SRMR_RSTR_7_SHIFT (7U) /*! RSTR_7 - configuration bit for independent reset of reset region CORTEXAMIX_CORE0 by event * 0b0..independent reset of reset region CORTEXAMIX_CORE0 by event is disabled * 0b1..independent reset of reset region CORTEXAMIX_CORE0 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_7(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_7_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_7_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_8_MASK (0x100U) #define SRC_GENERAL_REG_SRMR_RSTR_8_SHIFT (8U) /*! RSTR_8 - configuration bit for independent reset of reset region CORTEXAMIX_CORE1 by event * 0b0..independent reset of reset region CORTEXAMIX_CORE1 by event is disabled * 0b1..independent reset of reset region CORTEXAMIX_CORE1 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_8(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_8_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_8_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_9_MASK (0x200U) #define SRC_GENERAL_REG_SRMR_RSTR_9_SHIFT (9U) /*! RSTR_9 - configuration bit for independent reset of reset region CORTEXAMIX_CORE2 by event * 0b0..independent reset of reset region CORTEXAMIX_CORE2 by event is disabled * 0b1..independent reset of reset region CORTEXAMIX_CORE2 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_9(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_9_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_9_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_10_MASK (0x400U) #define SRC_GENERAL_REG_SRMR_RSTR_10_SHIFT (10U) /*! RSTR_10 - configuration bit for independent reset of reset region CORTEXAMIX_CORE3 by event * 0b0..independent reset of reset region CORTEXAMIX_CORE3 by event is disabled * 0b1..independent reset of reset region CORTEXAMIX_CORE3 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_10(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_10_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_10_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_11_MASK (0x800U) #define SRC_GENERAL_REG_SRMR_RSTR_11_SHIFT (11U) /*! RSTR_11 - configuration bit for independent reset of reset region CORTEXAMIX_CORE4 by event * 0b0..independent reset of reset region CORTEXAMIX_CORE4 by event is disabled * 0b1..independent reset of reset region CORTEXAMIX_CORE4 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_11(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_11_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_11_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_12_MASK (0x1000U) #define SRC_GENERAL_REG_SRMR_RSTR_12_SHIFT (12U) /*! RSTR_12 - configuration bit for independent reset of reset region CORTEXAMIX_CORE5 by event * 0b0..independent reset of reset region CORTEXAMIX_CORE5 by event is disabled * 0b1..independent reset of reset region CORTEXAMIX_CORE5 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_12(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_12_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_12_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_13_MASK (0x2000U) #define SRC_GENERAL_REG_SRMR_RSTR_13_SHIFT (13U) /*! RSTR_13 - configuration bit for independent reset of reset region CORTEXAMIX_PLATFORM by event * 0b0..independent reset of reset region CORTEXAMIX_PLATFORM by event is disabled * 0b1..independent reset of reset region CORTEXAMIX_PLATFORM by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_13(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_13_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_13_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_14_MASK (0x4000U) #define SRC_GENERAL_REG_SRMR_RSTR_14_SHIFT (14U) /*! RSTR_14 - configuration bit for independent reset of reset region DDRMIX_TOP by event * 0b0..independent reset of reset region DDRMIX_TOP by event is disabled * 0b1..independent reset of reset region DDRMIX_TOP by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_14(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_14_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_14_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_15_MASK (0x8000U) #define SRC_GENERAL_REG_SRMR_RSTR_15_SHIFT (15U) /*! RSTR_15 - configuration bit for independent reset of reset region DDRMIX_PHY by event * 0b0..independent reset of reset region DDRMIX_PHY by event is disabled * 0b1..independent reset of reset region DDRMIX_PHY by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_15(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_15_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_15_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_16_MASK (0x10000U) #define SRC_GENERAL_REG_SRMR_RSTR_16_SHIFT (16U) /*! RSTR_16 - configuration bit for independent reset of reset region DISPLAYMIX by event * 0b0..independent reset of reset region DISPLAYMIX by event is disabled * 0b1..independent reset of reset region DISPLAYMIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_16(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_16_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_16_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_17_MASK (0x20000U) #define SRC_GENERAL_REG_SRMR_RSTR_17_SHIFT (17U) /*! RSTR_17 - configuration bit for independent reset of reset region GPUMIX by event * 0b0..independent reset of reset region GPUMIX by event is disabled * 0b1..independent reset of reset region GPUMIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_17(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_17_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_17_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_18_MASK (0x40000U) #define SRC_GENERAL_REG_SRMR_RSTR_18_SHIFT (18U) /*! RSTR_18 - configuration bit for independent reset of reset region HSIOMIX_TOP by event * 0b0..independent reset of reset region HSIOMIX_TOP by event is disabled * 0b1..independent reset of reset region HSIOMIX_TOP by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_18(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_18_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_18_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_19_MASK (0x80000U) #define SRC_GENERAL_REG_SRMR_RSTR_19_SHIFT (19U) /*! RSTR_19 - configuration bit for independent reset of reset region HSIOMIX_WAON by event * 0b0..independent reset of reset region HSIOMIX_WAON by event is disabled * 0b1..independent reset of reset region HSIOMIX_WAON by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_19(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_19_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_19_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_20_MASK (0x100000U) #define SRC_GENERAL_REG_SRMR_RSTR_20_SHIFT (20U) /*! RSTR_20 - configuration bit for independent reset of reset region M7MIX by event * 0b0..independent reset of reset region M7MIX by event is disabled * 0b1..independent reset of reset region M7MIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_20(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_20_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_20_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_21_MASK (0x200000U) #define SRC_GENERAL_REG_SRMR_RSTR_21_SHIFT (21U) /*! RSTR_21 - configuration bit for independent reset of reset region NETCMIX by event * 0b0..independent reset of reset region NETCMIX by event is disabled * 0b1..independent reset of reset region NETCMIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_21(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_21_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_21_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_22_MASK (0x400000U) #define SRC_GENERAL_REG_SRMR_RSTR_22_SHIFT (22U) /*! RSTR_22 - configuration bit for independent reset of reset region NOCMIX by event * 0b0..independent reset of reset region NOCMIX by event is disabled * 0b1..independent reset of reset region NOCMIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_22(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_22_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_22_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_23_MASK (0x800000U) #define SRC_GENERAL_REG_SRMR_RSTR_23_SHIFT (23U) /*! RSTR_23 - configuration bit for independent reset of reset region NPUMIX by event * 0b0..independent reset of reset region NPUMIX by event is disabled * 0b1..independent reset of reset region NPUMIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_23(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_23_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_23_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_24_MASK (0x1000000U) #define SRC_GENERAL_REG_SRMR_RSTR_24_SHIFT (24U) /*! RSTR_24 - configuration bit for independent reset of reset region VPUMIX by event * 0b0..independent reset of reset region VPUMIX by event is disabled * 0b1..independent reset of reset region VPUMIX by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_24(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_24_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_24_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_25_MASK (0x2000000U) #define SRC_GENERAL_REG_SRMR_RSTR_25_SHIFT (25U) /*! RSTR_25 - configuration bit for independent reset of reset region WAKEUPMIX_TOP by event * 0b0..independent reset of reset region WAKEUPMIX_TOP by event is disabled * 0b1..independent reset of reset region WAKEUPMIX_TOP by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_25(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_25_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_25_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_26_MASK (0x4000000U) #define SRC_GENERAL_REG_SRMR_RSTR_26_SHIFT (26U) /*! RSTR_26 - configuration bit for independent reset of reset region WAKEUPMIX_JTAG by event * 0b0..independent reset of reset region WAKEUPMIX_JTAG by event is disabled * 0b1..independent reset of reset region WAKEUPMIX_JTAG by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_26(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_26_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_26_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_27_MASK (0x8000000U) #define SRC_GENERAL_REG_SRMR_RSTR_27_SHIFT (27U) /*! RSTR_27 - configuration bit for independent reset of reset region WAKEUPMIX_WDOG_3_4 by event * 0b0..independent reset of reset region WAKEUPMIX_WDOG_3_4 by event is disabled * 0b1..independent reset of reset region WAKEUPMIX_WDOG_3_4 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_27(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_27_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_27_MASK) #define SRC_GENERAL_REG_SRMR_RSTR_28_MASK (0x10000000U) #define SRC_GENERAL_REG_SRMR_RSTR_28_SHIFT (28U) /*! RSTR_28 - configuration bit for independent reset of reset region WAKEUPMIX_WDOG_5 by event * 0b0..independent reset of reset region WAKEUPMIX_WDOG_5 by event is disabled * 0b1..independent reset of reset region WAKEUPMIX_WDOG_5 by event is enabled */ #define SRC_GENERAL_REG_SRMR_RSTR_28(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRMR_RSTR_28_SHIFT)) & SRC_GENERAL_REG_SRMR_RSTR_28_MASK) /*! @} */ /* The count of SRC_GENERAL_REG_SRMR */ #define SRC_GENERAL_REG_SRMR_COUNT (14U) /*! @name SRDR - SRC Reset Disable Register */ /*! @{ */ #define SRC_GENERAL_REG_SRDR_RSTR_0_RDIS_MASK (0x1U) #define SRC_GENERAL_REG_SRDR_RSTR_0_RDIS_SHIFT (0U) /*! RSTR_0_RDIS - configuration bit to disbale reset of reset region ANAMIX by reset event * 0b0..reset of reset region ANAMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_0_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_0_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_0_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_1_RDIS_MASK (0x2U) #define SRC_GENERAL_REG_SRDR_RSTR_1_RDIS_SHIFT (1U) /*! RSTR_1_RDIS - configuration bit to disbale reset of reset region AONMIX_TOP by reset event * 0b0..reset of reset region AONMIX_TOP by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_1_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_1_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_1_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_2_RDIS_MASK (0x4U) #define SRC_GENERAL_REG_SRDR_RSTR_2_RDIS_SHIFT (2U) /*! RSTR_2_RDIS - configuration bit to disbale reset of reset region AONMIX_M33 by reset event * 0b0..reset of reset region AONMIX_M33 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_2_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_2_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_2_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_3_RDIS_MASK (0x8U) #define SRC_GENERAL_REG_SRDR_RSTR_3_RDIS_SHIFT (3U) /*! RSTR_3_RDIS - configuration bit to disbale reset of reset region AONMIX_ELE by reset event * 0b0..reset of reset region AONMIX_ELE by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_3_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_3_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_3_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_4_RDIS_MASK (0x10U) #define SRC_GENERAL_REG_SRDR_RSTR_4_RDIS_SHIFT (4U) /*! RSTR_4_RDIS - configuration bit to disbale reset of reset region BBSMMIX by reset event * 0b0..reset of reset region BBSMMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_4_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_4_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_4_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_5_RDIS_MASK (0x20U) #define SRC_GENERAL_REG_SRDR_RSTR_5_RDIS_SHIFT (5U) /*! RSTR_5_RDIS - configuration bit to disbale reset of reset region CAMERAMIX by reset event * 0b0..reset of reset region CAMERAMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_5_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_5_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_5_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_6_RDIS_MASK (0x40U) #define SRC_GENERAL_REG_SRDR_RSTR_6_RDIS_SHIFT (6U) /*! RSTR_6_RDIS - configuration bit to disbale reset of reset region CCMSRCGPCMIX by reset event * 0b0..reset of reset region CCMSRCGPCMIX by reset event is not disabled * 0b1..reset of reset region CCMSRCGPCMIX by reset event is disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_6_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_6_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_6_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_7_RDIS_MASK (0x80U) #define SRC_GENERAL_REG_SRDR_RSTR_7_RDIS_SHIFT (7U) /*! RSTR_7_RDIS - configuration bit to disbale reset of reset region CORTEXAMIX_CORE0 by reset event * 0b0..reset of reset region CORTEXAMIX_CORE0 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_7_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_7_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_7_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_8_RDIS_MASK (0x100U) #define SRC_GENERAL_REG_SRDR_RSTR_8_RDIS_SHIFT (8U) /*! RSTR_8_RDIS - configuration bit to disbale reset of reset region CORTEXAMIX_CORE1 by reset event * 0b0..reset of reset region CORTEXAMIX_CORE1 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_8_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_8_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_8_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_9_RDIS_MASK (0x200U) #define SRC_GENERAL_REG_SRDR_RSTR_9_RDIS_SHIFT (9U) /*! RSTR_9_RDIS - configuration bit to disbale reset of reset region CORTEXAMIX_CORE2 by reset event * 0b0..reset of reset region CORTEXAMIX_CORE2 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_9_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_9_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_9_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_10_RDIS_MASK (0x400U) #define SRC_GENERAL_REG_SRDR_RSTR_10_RDIS_SHIFT (10U) /*! RSTR_10_RDIS - configuration bit to disbale reset of reset region CORTEXAMIX_CORE3 by reset event * 0b0..reset of reset region CORTEXAMIX_CORE3 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_10_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_10_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_10_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_11_RDIS_MASK (0x800U) #define SRC_GENERAL_REG_SRDR_RSTR_11_RDIS_SHIFT (11U) /*! RSTR_11_RDIS - configuration bit to disbale reset of reset region CORTEXAMIX_CORE4 by reset event * 0b0..reset of reset region CORTEXAMIX_CORE4 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_11_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_11_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_11_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_12_RDIS_MASK (0x1000U) #define SRC_GENERAL_REG_SRDR_RSTR_12_RDIS_SHIFT (12U) /*! RSTR_12_RDIS - configuration bit to disbale reset of reset region CORTEXAMIX_CORE5 by reset event * 0b0..reset of reset region CORTEXAMIX_CORE5 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_12_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_12_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_12_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_13_RDIS_MASK (0x2000U) #define SRC_GENERAL_REG_SRDR_RSTR_13_RDIS_SHIFT (13U) /*! RSTR_13_RDIS - configuration bit to disbale reset of reset region CORTEXAMIX_PLATFORM by reset event * 0b0..reset of reset region CORTEXAMIX_PLATFORM by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_13_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_13_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_13_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_14_RDIS_MASK (0x4000U) #define SRC_GENERAL_REG_SRDR_RSTR_14_RDIS_SHIFT (14U) /*! RSTR_14_RDIS - configuration bit to disbale reset of reset region DDRMIX_TOP by reset event * 0b0..reset of reset region DDRMIX_TOP by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_14_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_14_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_14_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_15_RDIS_MASK (0x8000U) #define SRC_GENERAL_REG_SRDR_RSTR_15_RDIS_SHIFT (15U) /*! RSTR_15_RDIS - configuration bit to disbale reset of reset region DDRMIX_PHY by reset event * 0b0..reset of reset region DDRMIX_PHY by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_15_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_15_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_15_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_16_RDIS_MASK (0x10000U) #define SRC_GENERAL_REG_SRDR_RSTR_16_RDIS_SHIFT (16U) /*! RSTR_16_RDIS - configuration bit to disbale reset of reset region DISPLAYMIX by reset event * 0b0..reset of reset region DISPLAYMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_16_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_16_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_16_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_17_RDIS_MASK (0x20000U) #define SRC_GENERAL_REG_SRDR_RSTR_17_RDIS_SHIFT (17U) /*! RSTR_17_RDIS - configuration bit to disbale reset of reset region GPUMIX by reset event * 0b0..reset of reset region GPUMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_17_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_17_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_17_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_18_RDIS_MASK (0x40000U) #define SRC_GENERAL_REG_SRDR_RSTR_18_RDIS_SHIFT (18U) /*! RSTR_18_RDIS - configuration bit to disbale reset of reset region HSIOMIX_TOP by reset event * 0b0..reset of reset region HSIOMIX_TOP by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_18_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_18_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_18_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_19_RDIS_MASK (0x80000U) #define SRC_GENERAL_REG_SRDR_RSTR_19_RDIS_SHIFT (19U) /*! RSTR_19_RDIS - configuration bit to disbale reset of reset region HSIOMIX_WAON by reset event * 0b0..reset of reset region HSIOMIX_WAON by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_19_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_19_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_19_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_20_RDIS_MASK (0x100000U) #define SRC_GENERAL_REG_SRDR_RSTR_20_RDIS_SHIFT (20U) /*! RSTR_20_RDIS - configuration bit to disbale reset of reset region M7MIX by reset event * 0b0..reset of reset region M7MIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_20_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_20_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_20_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_21_RDIS_MASK (0x200000U) #define SRC_GENERAL_REG_SRDR_RSTR_21_RDIS_SHIFT (21U) /*! RSTR_21_RDIS - configuration bit to disbale reset of reset region NETCMIX by reset event * 0b0..reset of reset region NETCMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_21_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_21_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_21_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_22_RDIS_MASK (0x400000U) #define SRC_GENERAL_REG_SRDR_RSTR_22_RDIS_SHIFT (22U) /*! RSTR_22_RDIS - configuration bit to disbale reset of reset region NOCMIX by reset event * 0b0..reset of reset region NOCMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_22_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_22_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_22_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_23_RDIS_MASK (0x800000U) #define SRC_GENERAL_REG_SRDR_RSTR_23_RDIS_SHIFT (23U) /*! RSTR_23_RDIS - configuration bit to disbale reset of reset region NPUMIX by reset event * 0b0..reset of reset region NPUMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_23_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_23_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_23_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_24_RDIS_MASK (0x1000000U) #define SRC_GENERAL_REG_SRDR_RSTR_24_RDIS_SHIFT (24U) /*! RSTR_24_RDIS - configuration bit to disbale reset of reset region VPUMIX by reset event * 0b0..reset of reset region VPUMIX by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_24_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_24_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_24_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_25_RDIS_MASK (0x2000000U) #define SRC_GENERAL_REG_SRDR_RSTR_25_RDIS_SHIFT (25U) /*! RSTR_25_RDIS - configuration bit to disbale reset of reset region WAKEUPMIX_TOP by reset event * 0b0..reset of reset region WAKEUPMIX_TOP by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_25_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_25_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_25_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_26_RDIS_MASK (0x4000000U) #define SRC_GENERAL_REG_SRDR_RSTR_26_RDIS_SHIFT (26U) /*! RSTR_26_RDIS - configuration bit to disbale reset of reset region WAKEUPMIX_JTAG by reset event * 0b0..reset of reset region WAKEUPMIX_JTAG by reset event is not disabled * 0b1..reset of reset region WAKEUPMIX_JTAG by reset event is disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_26_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_26_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_26_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_27_RDIS_MASK (0x8000000U) #define SRC_GENERAL_REG_SRDR_RSTR_27_RDIS_SHIFT (27U) /*! RSTR_27_RDIS - configuration bit to disbale reset of reset region WAKEUPMIX_WDOG_3_4 by reset event * 0b0..reset of reset region WAKEUPMIX_WDOG_3_4 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_27_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_27_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_27_RDIS_MASK) #define SRC_GENERAL_REG_SRDR_RSTR_28_RDIS_MASK (0x10000000U) #define SRC_GENERAL_REG_SRDR_RSTR_28_RDIS_SHIFT (28U) /*! RSTR_28_RDIS - configuration bit to disbale reset of reset region WAKEUPMIX_WDOG_5 by reset event * 0b0..reset of reset region WAKEUPMIX_WDOG_5 by reset event is not disabled */ #define SRC_GENERAL_REG_SRDR_RSTR_28_RDIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_GENERAL_REG_SRDR_RSTR_28_RDIS_SHIFT)) & SRC_GENERAL_REG_SRDR_RSTR_28_RDIS_MASK) /*! @} */ /*! * @} */ /* end of group SRC_GENERAL_REG_Register_Masks */ /* SRC_GENERAL_REG - Peripheral instance base addresses */ /** Peripheral CCMSRCGPC__SRC__SRC_CENTRAL_REG base address */ #define CCMSRCGPC__SRC__SRC_CENTRAL_REG_BASE (0x44460000u) /** Peripheral CCMSRCGPC__SRC__SRC_CENTRAL_REG base pointer */ #define CCMSRCGPC__SRC__SRC_CENTRAL_REG ((SRC_GENERAL_REG_Type *)CCMSRCGPC__SRC__SRC_CENTRAL_REG_BASE) /** Array initializer of SRC_GENERAL_REG peripheral base addresses */ #define SRC_GENERAL_REG_BASE_ADDRS { CCMSRCGPC__SRC__SRC_CENTRAL_REG_BASE } /** Array initializer of SRC_GENERAL_REG peripheral base pointers */ #define SRC_GENERAL_REG_BASE_PTRS { CCMSRCGPC__SRC__SRC_CENTRAL_REG } /*! * @} */ /* end of group SRC_GENERAL_REG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SRC_MEM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_MEM_Peripheral_Access_Layer SRC_MEM Peripheral Access Layer * @{ */ /** SRC_MEM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t MEM_CTRL; /**< MEM Low Power Control, offset: 0x4 */ __IO uint32_t MEMLP_CTRL_0; /**< MEM Low Power Control_0, offset: 0x8 */ uint8_t RESERVED_1[4]; __IO uint32_t MEMLP_CTRL_1; /**< MEM Low Power Control_1, offset: 0x10 */ __IO uint32_t MEMLP_CTRL_2; /**< MEM Low Power Control_2, offset: 0x14 */ __I uint32_t MEM_STAT; /**< MEM Status, offset: 0x18 */ } SRC_MEM_Type; /* ---------------------------------------------------------------------------- -- SRC_MEM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_MEM_Register_Masks SRC_MEM Register Masks * @{ */ /*! @name MEM_CTRL - MEM Low Power Control */ /*! @{ */ #define SRC_MEM_MEM_CTRL_MEM_LP_MODE_MASK (0x2U) #define SRC_MEM_MEM_CTRL_MEM_LP_MODE_SHIFT (1U) /*! MEM_LP_MODE - Memory Low Power Mode configuration. Locked by LOCK_CFG field. * 0b0..Power Down * 0b1..Retention Mode */ #define SRC_MEM_MEM_CTRL_MEM_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_CTRL_MEM_LP_MODE_SHIFT)) & SRC_MEM_MEM_CTRL_MEM_LP_MODE_MASK) #define SRC_MEM_MEM_CTRL_MEM_LF_CNT_CFG_MASK (0xFF00U) #define SRC_MEM_MEM_CTRL_MEM_LF_CNT_CFG_SHIFT (8U) /*! MEM_LF_CNT_CFG - MEM power up counter */ #define SRC_MEM_MEM_CTRL_MEM_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_CTRL_MEM_LF_CNT_CFG_SHIFT)) & SRC_MEM_MEM_CTRL_MEM_LF_CNT_CFG_MASK) #define SRC_MEM_MEM_CTRL_MEM_HF_CNT_CFG_MASK (0xFF0000U) #define SRC_MEM_MEM_CTRL_MEM_HF_CNT_CFG_SHIFT (16U) /*! MEM_HF_CNT_CFG - MEM power up counter */ #define SRC_MEM_MEM_CTRL_MEM_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_CTRL_MEM_HF_CNT_CFG_SHIFT)) & SRC_MEM_MEM_CTRL_MEM_HF_CNT_CFG_MASK) #define SRC_MEM_MEM_CTRL_LOCK_CFG_MASK (0x1000000U) #define SRC_MEM_MEM_CTRL_LOCK_CFG_SHIFT (24U) /*! LOCK_CFG - Configuration lock * 0b0..Not locked. * 0b1..Locked. */ #define SRC_MEM_MEM_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_CTRL_LOCK_CFG_SHIFT)) & SRC_MEM_MEM_CTRL_LOCK_CFG_MASK) /*! @} */ /*! @name MEMLP_CTRL_0 - MEM Low Power Control_0 */ /*! @{ */ #define SRC_MEM_MEMLP_CTRL_0_MEMLP_ENT_CNT_MASK (0xFFFFFFFFU) #define SRC_MEM_MEMLP_CTRL_0_MEMLP_ENT_CNT_SHIFT (0U) /*! MEMLP_ENT_CNT - Delay counter to start entering to memory low power mode. Locked by LOCK_CFG field */ #define SRC_MEM_MEMLP_CTRL_0_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEMLP_CTRL_0_MEMLP_ENT_CNT_SHIFT)) & SRC_MEM_MEMLP_CTRL_0_MEMLP_ENT_CNT_MASK) /*! @} */ /*! @name MEMLP_CTRL_1 - MEM Low Power Control_1 */ /*! @{ */ #define SRC_MEM_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_MASK (0xFFFFFFFFU) #define SRC_MEM_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_SHIFT (0U) /*! MEMLP_RET_PGEN_CNT - Delay counter to interval for retn to pgen. Locked by LOCK_CFG field */ #define SRC_MEM_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_SHIFT)) & SRC_MEM_MEMLP_CTRL_1_MEMLP_RET_PGEN_CNT_MASK) /*! @} */ /*! @name MEMLP_CTRL_2 - MEM Low Power Control_2 */ /*! @{ */ #define SRC_MEM_MEMLP_CTRL_2_MEMLP_EXT_CNT_MASK (0xFFFFFFFFU) #define SRC_MEM_MEMLP_CTRL_2_MEMLP_EXT_CNT_SHIFT (0U) /*! MEMLP_EXT_CNT - Delay counter to start exiting from memory low power mode. Locked by LOCK_CFG field */ #define SRC_MEM_MEMLP_CTRL_2_MEMLP_EXT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEMLP_CTRL_2_MEMLP_EXT_CNT_SHIFT)) & SRC_MEM_MEMLP_CTRL_2_MEMLP_EXT_CNT_MASK) /*! @} */ /*! @name MEM_STAT - MEM Status */ /*! @{ */ #define SRC_MEM_MEM_STAT_MEM_FSM_STAT_MASK (0xFU) #define SRC_MEM_MEM_STAT_MEM_FSM_STAT_SHIFT (0U) /*! MEM_FSM_STAT - MEM FSM status * 0b0000..MEM_IDLE_POR * 0b0001..MEM_IDLE_RUN * 0b0010..MEM_OFF_PRE * 0b0011..MEM_ENT_RET * 0b0100..MEM_ENT_PGEN * 0b0101..MEM_OFF_RSP * 0b0110..MEM_IDLE_SLEEP * 0b0111..MEM_ON_PRE * 0b1000..MEM_EXT_PGEN * 0b1001..MEM_EXT_RET * 0b1010..MEM_ON_RSP * 0b1011..Reserved * 0b1100..Reserved * 0b1101..Reserved * 0b1110..Reserved * 0b1111..Reserved */ #define SRC_MEM_MEM_STAT_MEM_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_STAT_MEM_FSM_STAT_SHIFT)) & SRC_MEM_MEM_STAT_MEM_FSM_STAT_MASK) #define SRC_MEM_MEM_STAT_RET2N_STAT_MASK (0x10U) #define SRC_MEM_MEM_STAT_RET2N_STAT_SHIFT (4U) /*! RET2N_STAT - RET2N status * 0b0..Memory RET2N pin is low * 0b1..Memory RET2N pin is high */ #define SRC_MEM_MEM_STAT_RET2N_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_STAT_RET2N_STAT_SHIFT)) & SRC_MEM_MEM_STAT_RET2N_STAT_MASK) #define SRC_MEM_MEM_STAT_RET1N_STAT_MASK (0x20U) #define SRC_MEM_MEM_STAT_RET1N_STAT_SHIFT (5U) /*! RET1N_STAT - RET1N status * 0b1..Memory RET1N pin is high * 0b0..Memory RET1N pin is low */ #define SRC_MEM_MEM_STAT_RET1N_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_STAT_RET1N_STAT_SHIFT)) & SRC_MEM_MEM_STAT_RET1N_STAT_MASK) #define SRC_MEM_MEM_STAT_PGEN_STAT_MASK (0x40U) #define SRC_MEM_MEM_STAT_PGEN_STAT_SHIFT (6U) /*! PGEN_STAT - Power gate enable status * 0b0..Memory PGEN pin is low * 0b1..Memory PGEN pin is high */ #define SRC_MEM_MEM_STAT_PGEN_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_STAT_PGEN_STAT_SHIFT)) & SRC_MEM_MEM_STAT_PGEN_STAT_MASK) #define SRC_MEM_MEM_STAT_MEM_STAT_MASK (0x100U) #define SRC_MEM_MEM_STAT_MEM_STAT_SHIFT (8U) /*! MEM_STAT - MEM status * 0b0..MEM exit low power * 0b1..MEM enter low power - retention1 mode or power down mode */ #define SRC_MEM_MEM_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEM_MEM_STAT_MEM_STAT_SHIFT)) & SRC_MEM_MEM_STAT_MEM_STAT_MASK) /*! @} */ /*! * @} */ /* end of group SRC_MEM_Register_Masks */ /* SRC_MEM - Peripheral instance base addresses */ /** Peripheral CCMSRCGPC__SRC__XSPR_AONMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_AONMIX_MEM_BASE (0x44460900u) /** Peripheral CCMSRCGPC__SRC__XSPR_AONMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_AONMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_AONMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM_BASE (0x44461100u) /** Peripheral CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM_BASE (0x44461900u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM_BASE (0x44461D00u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM_BASE (0x44462100u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM_BASE (0x44462500u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM_BASE (0x44462900u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM_BASE (0x44462D00u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0_BASE (0x44463100u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0 ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1_BASE (0x44463120u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1 ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_DDRMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_DDRMIX_MEM_BASE (0x44463500u) /** Peripheral CCMSRCGPC__SRC__XSPR_DDRMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_DDRMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_DDRMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM_BASE (0x44463900u) /** Peripheral CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_GPUMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_GPUMIX_MEM_BASE (0x44463D00u) /** Peripheral CCMSRCGPC__SRC__XSPR_GPUMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_GPUMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_GPUMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM_BASE (0x44464100u) /** Peripheral CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_M7MIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_M7MIX_MEM_BASE (0x44464900u) /** Peripheral CCMSRCGPC__SRC__XSPR_M7MIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_M7MIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_M7MIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_NETCMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_NETCMIX_MEM_BASE (0x44464D00u) /** Peripheral CCMSRCGPC__SRC__XSPR_NETCMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_NETCMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_NETCMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0 base address */ #define CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0_BASE (0x44465100u) /** Peripheral CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0 base pointer */ #define CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0 ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1 base address */ #define CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1_BASE (0x44465120u) /** Peripheral CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1 base pointer */ #define CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1 ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_NPUMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_NPUMIX_MEM_BASE (0x44465500u) /** Peripheral CCMSRCGPC__SRC__XSPR_NPUMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_NPUMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_NPUMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_VPUMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_VPUMIX_MEM_BASE (0x44465900u) /** Peripheral CCMSRCGPC__SRC__XSPR_VPUMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_VPUMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_VPUMIX_MEM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM base address */ #define CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM_BASE (0x44465D00u) /** Peripheral CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM base pointer */ #define CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM ((SRC_MEM_Type *)CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM_BASE) /** Array initializer of SRC_MEM peripheral base addresses */ #define SRC_MEM_BASE_ADDRS { CCMSRCGPC__SRC__XSPR_AONMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1_BASE, CCMSRCGPC__SRC__XSPR_DDRMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_GPUMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_M7MIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_NETCMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0_BASE, CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1_BASE, CCMSRCGPC__SRC__XSPR_NPUMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_VPUMIX_MEM_BASE, CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM_BASE } /** Array initializer of SRC_MEM peripheral base pointers */ #define SRC_MEM_BASE_PTRS { CCMSRCGPC__SRC__XSPR_AONMIX_MEM, CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM, CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0, CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1, CCMSRCGPC__SRC__XSPR_DDRMIX_MEM, CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM, CCMSRCGPC__SRC__XSPR_GPUMIX_MEM, CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM, CCMSRCGPC__SRC__XSPR_M7MIX_MEM, CCMSRCGPC__SRC__XSPR_NETCMIX_MEM, CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0, CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1, CCMSRCGPC__SRC__XSPR_NPUMIX_MEM, CCMSRCGPC__SRC__XSPR_VPUMIX_MEM, CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM } /*! * @} */ /* end of group SRC_MEM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SRC_XSPR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_XSPR_Peripheral_Access_Layer SRC_XSPR Peripheral Access Layer * @{ */ /** SRC_XSPR - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t AUTHEN_CTRL; /**< Authentication Control, offset: 0x4 */ uint8_t RESERVED_1[8]; __IO uint32_t LPM_SETTING_0; /**< LPM Setting 0, offset: 0x10 */ __IO uint32_t LPM_SETTING_1; /**< LPM Setting 1, offset: 0x14 */ __IO uint32_t LPM_SETTING_2; /**< LPM Setting 2, offset: 0x18 */ uint8_t RESERVED_2[4]; __IO uint32_t SLICE_SW_CTRL; /**< Slice Software Control Register, offset: 0x20 */ __IO uint32_t IRST_REQ_CTRL; /**< Individual Reset Request Control, offset: 0x24 */ uint8_t RESERVED_3[24]; __IO uint32_t A55_HDSK_ACK_CTRL; /**< A55 handshake acknowledge control, offset: 0x40 */ __I uint32_t A55_HDSK_ACK_STAT; /**< A55 handshake acknowledge status, offset: 0x44 */ __IO uint32_t SYSMAN_ACK_CTRL; /**< System Manager handshake acknowledge control, offset: 0x48 */ __I uint32_t SYSMAN_ACK_STAT; /**< System manager handshake acknowledge status, offset: 0x4C */ __IO uint32_t SSAR_ACK_CTRL; /**< SSAR acknowledge control, offset: 0x50 */ __I uint32_t SSAR_ACK_STAT; /**< SSAR acknowledge status, offset: 0x54 */ uint8_t RESERVED_4[4]; __IO uint32_t ISO_OFF_DLY_POR; /**< iso off delay control when por, offset: 0x5C */ __IO uint32_t ISO_ON_DLY; /**< iso on delay control, offset: 0x60 */ __IO uint32_t ISO_OFF_DLY; /**< iso off delay control, offset: 0x64 */ __IO uint32_t PSW_OFF_LF_DLY; /**< psw off lf delay control, offset: 0x68 */ uint8_t RESERVED_5[4]; __IO uint32_t PSW_OFF_HF_DLY; /**< psw off hf delay control, offset: 0x70 */ __IO uint32_t PSW_ON_LF_DLY; /**< psw on lf delay control, offset: 0x74 */ __IO uint32_t PSW_ON_HF_DLY; /**< psw on hf delay control, offset: 0x78 */ uint8_t RESERVED_6[4]; __IO uint32_t PSW_ACK_CTRL_0; /**< Power switch acknowledge control, offset: 0x80 */ __IO uint32_t PSW_ACK_CTRL_1; /**< Power switch acknowledge control, offset: 0x84 */ __I uint32_t PSW_ACK_STAT; /**< PSW acknowledge status, offset: 0x88 */ uint8_t RESERVED_7[20]; __I uint32_t UPI_STAT_0; /**< UPI status 0, offset: 0xA0 */ __I uint32_t UPI_STAT_1; /**< UPI status 1, offset: 0xA4 */ __I uint32_t UPI_STAT_2; /**< UPI status 2, offset: 0xA8 */ __I uint32_t UPI_STAT_3; /**< UPI status 3, offset: 0xAC */ __I uint32_t FSM_STAT; /**< FSM status, offset: 0xB0 */ __I uint32_t FUNC_STAT; /**< function status, offset: 0xB4 */ __I uint32_t RSTR_STAT; /**< Reset Region Status Register, offset: 0xB8 */ } SRC_XSPR_Type; /* ---------------------------------------------------------------------------- -- SRC_XSPR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SRC_XSPR_Register_Masks SRC_XSPR Register Masks * @{ */ /*! @name AUTHEN_CTRL - Authentication Control */ /*! @{ */ #define SRC_XSPR_AUTHEN_CTRL_LPM_MODE_MASK (0x4U) #define SRC_XSPR_AUTHEN_CTRL_LPM_MODE_SHIFT (2U) /*! LPM_MODE - Low power control mode * 0b0..Low power mode controlled by software * 0b1..Low power mode controlled by GPC hardware */ #define SRC_XSPR_AUTHEN_CTRL_LPM_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_AUTHEN_CTRL_LPM_MODE_SHIFT)) & SRC_XSPR_AUTHEN_CTRL_LPM_MODE_MASK) #define SRC_XSPR_AUTHEN_CTRL_LOCK_CFG_MASK (0x80U) #define SRC_XSPR_AUTHEN_CTRL_LOCK_CFG_SHIFT (7U) /*! LOCK_CFG - Configuration lock * 0b0..Low power configuration fields are not locked. * 0b1..Low power configuration fields are locked. */ #define SRC_XSPR_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & SRC_XSPR_AUTHEN_CTRL_LOCK_CFG_MASK) #define SRC_XSPR_AUTHEN_CTRL_TZ_USER_MASK (0x100U) #define SRC_XSPR_AUTHEN_CTRL_TZ_USER_SHIFT (8U) /*! TZ_USER - Allow user mode access * 0b0..This MIX SLICE registers can only be written in privilege mode. * 0b1..This MIX SLICE registers can be written either in privilege mode or user mode. */ #define SRC_XSPR_AUTHEN_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_AUTHEN_CTRL_TZ_USER_SHIFT)) & SRC_XSPR_AUTHEN_CTRL_TZ_USER_MASK) #define SRC_XSPR_AUTHEN_CTRL_TZ_NS_MASK (0x200U) #define SRC_XSPR_AUTHEN_CTRL_TZ_NS_SHIFT (9U) /*! TZ_NS - Allow non-secure mode access * 0b0..This MIX SLICE registers can only be written in secure mode. * 0b1..This MIX SLICE registers can be written either in secure mode or non-secure mode. */ #define SRC_XSPR_AUTHEN_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_AUTHEN_CTRL_TZ_NS_SHIFT)) & SRC_XSPR_AUTHEN_CTRL_TZ_NS_MASK) #define SRC_XSPR_AUTHEN_CTRL_LOCK_TZ_MASK (0x800U) #define SRC_XSPR_AUTHEN_CTRL_LOCK_TZ_SHIFT (11U) /*! LOCK_TZ - Lock NONSECURE and USER * 0b0..TZ_NS and TZ_USER value can be changed. * 0b1..TZ_NS and TZ_USER value cannot be changed. */ #define SRC_XSPR_AUTHEN_CTRL_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_AUTHEN_CTRL_LOCK_TZ_SHIFT)) & SRC_XSPR_AUTHEN_CTRL_LOCK_TZ_MASK) #define SRC_XSPR_AUTHEN_CTRL_LOCK_LIST_MASK (0x8000U) #define SRC_XSPR_AUTHEN_CTRL_LOCK_LIST_SHIFT (15U) /*! LOCK_LIST - White list lock * 0b0..WHITE_LIST value can be changed. * 0b1..WHITE_LIST value cannot be changed. */ #define SRC_XSPR_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & SRC_XSPR_AUTHEN_CTRL_LOCK_LIST_MASK) #define SRC_XSPR_AUTHEN_CTRL_WHITE_LIST_MASK (0xFFFF0000U) #define SRC_XSPR_AUTHEN_CTRL_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list * 0b0000000000000001..Core with TRDC domain (resp. GPC domain) ID=0 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000000000010..Core with TRDC domain (resp. GPC domain) ID=1 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000000000100..Core with TRDC domain (resp. GPC domain) ID=2 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000000001000..Core with TRDC domain (resp. GPC domain) ID=3 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000000010000..Core with TRDC domain (resp. GPC domain) ID=4 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000000100000..Core with TRDC domain (resp. GPC domain) ID=5 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000001000000..Core with TRDC domain (resp. GPC domain) ID=6 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000010000000..Core with TRDC domain (resp. GPC domain) ID=7 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000000100000000..Core with TRDC domain (resp. GPC domain) ID=8 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000001000000000..Core with TRDC domain (resp. GPC domain) ID=9 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000010000000000..Core with TRDC domain (resp. GPC domain) ID=10 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0000100000000000..Core with TRDC domain (resp. GPC domain) ID=11 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0001000000000000..Core with TRDC domain (resp. GPC domain) ID=12 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0010000000000000..Core with TRDC domain (resp. GPC domain) ID=13 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b0100000000000000..Core with TRDC domain (resp. GPC domain) ID=14 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). * 0b1000000000000000..Core with TRDC domain (resp. GPC domain) ID=15 can write SRC MIX SLICE registers (resp. trigger SRC MIX SLICE powering down). */ #define SRC_XSPR_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & SRC_XSPR_AUTHEN_CTRL_WHITE_LIST_MASK) /*! @} */ /*! @name LPM_SETTING_0 - LPM Setting 0 */ /*! @{ */ #define SRC_XSPR_LPM_SETTING_0_LPM_SETTING_CD_MASK (0x7U) #define SRC_XSPR_LPM_SETTING_0_LPM_SETTING_CD_SHIFT (0U) /*! LPM_SETTING_CD - LPM setting of current domain */ #define SRC_XSPR_LPM_SETTING_0_LPM_SETTING_CD(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_0_LPM_SETTING_CD_SHIFT)) & SRC_XSPR_LPM_SETTING_0_LPM_SETTING_CD_MASK) /*! @} */ /*! @name LPM_SETTING_1 - LPM Setting 1 */ /*! @{ */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D0_MASK (0x7U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D0_SHIFT (0U) /*! LPM_SETTING_D0 - LPM setting of domain 0 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D0(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D0_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D0_MASK) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D1_MASK (0x70U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D1_SHIFT (4U) /*! LPM_SETTING_D1 - LPM setting of domain 1 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D1(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D1_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D1_MASK) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D2_MASK (0x700U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D2_SHIFT (8U) /*! LPM_SETTING_D2 - LPM setting of domain 2 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D2(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D2_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D2_MASK) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D3_MASK (0x7000U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D3_SHIFT (12U) /*! LPM_SETTING_D3 - LPM setting of domain 3 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D3(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D3_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D3_MASK) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D4_MASK (0x70000U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D4_SHIFT (16U) /*! LPM_SETTING_D4 - LPM setting of domain 4 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D4(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D4_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D4_MASK) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D5_MASK (0x700000U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D5_SHIFT (20U) /*! LPM_SETTING_D5 - LPM setting of domain 5 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D5(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D5_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D5_MASK) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D6_MASK (0x7000000U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D6_SHIFT (24U) /*! LPM_SETTING_D6 - LPM setting of domain 6 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D6(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D6_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D6_MASK) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D7_MASK (0x70000000U) #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D7_SHIFT (28U) /*! LPM_SETTING_D7 - LPM setting of domain 7 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D7(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D7_SHIFT)) & SRC_XSPR_LPM_SETTING_1_LPM_SETTING_D7_MASK) /*! @} */ /*! @name LPM_SETTING_2 - LPM Setting 2 */ /*! @{ */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D8_MASK (0x7U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D8_SHIFT (0U) /*! LPM_SETTING_D8 - LPM setting of domain 8 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D8(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D8_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D8_MASK) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D9_MASK (0x70U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D9_SHIFT (4U) /*! LPM_SETTING_D9 - LPM setting of domain 9 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D9(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D9_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D9_MASK) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D10_MASK (0x700U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D10_SHIFT (8U) /*! LPM_SETTING_D10 - LPM setting of domain 10 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D10(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D10_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D10_MASK) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D11_MASK (0x7000U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D11_SHIFT (12U) /*! LPM_SETTING_D11 - LPM setting of domain 11 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D11(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D11_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D11_MASK) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D12_MASK (0x70000U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D12_SHIFT (16U) /*! LPM_SETTING_D12 - LPM setting of domain 12 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D12(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D12_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D12_MASK) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D13_MASK (0x700000U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D13_SHIFT (20U) /*! LPM_SETTING_D13 - LPM setting of domain 13 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D13(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D13_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D13_MASK) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D14_MASK (0x7000000U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D14_SHIFT (24U) /*! LPM_SETTING_D14 - LPM setting of domain 14 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D14(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D14_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D14_MASK) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D15_MASK (0x70000000U) #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D15_SHIFT (28U) /*! LPM_SETTING_D15 - LPM setting of domain 15 * 0b000..Power always off * 0b001..power on when domain n is in RUN, off in WAIT/STOP/SUSPEND * 0b010..power on when domain n is in RUN/WAIT, off in STOP/SUSPEND * 0b011..power on when domain n is in RUN/WAIT/STOP, off in SUSPEND * 0b100..power always on * 0b101..power always on * 0b110..power always on * 0b111..power always on */ #define SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D15(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D15_SHIFT)) & SRC_XSPR_LPM_SETTING_2_LPM_SETTING_D15_MASK) /*! @} */ /*! @name SLICE_SW_CTRL - Slice Software Control Register */ /*! @{ */ #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_0_MASK (0x100000U) #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_0_SHIFT (20U) /*! RST_RSTR_0 - Reset Control for Reset Region 0. * 0b0..no software control over reset of reset region 0 * 0b1..assert reset of reset region 0 */ #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_0_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_0_MASK) #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_1_MASK (0x200000U) #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_1_SHIFT (21U) /*! RST_RSTR_1 - Reset Control for Reset Region 1. * 0b0..no software control over reset of reset region 1 * 0b1..assert reset of reset region 1 */ #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_1_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_1_MASK) #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_2_MASK (0x400000U) #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_2_SHIFT (22U) /*! RST_RSTR_2 - Reset Control for Reset Region 2. * 0b0..no software control over reset of reset region 2 * 0b1..assert reset of reset region 2 */ #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_2_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_2_MASK) #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_3_MASK (0x800000U) #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_3_SHIFT (23U) /*! RST_RSTR_3 - Reset Control for Reset Region 3. * 0b0..no software control over reset of reset region 3 * 0b1..assert reset of reset region 3 */ #define SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_3_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_RST_RSTR_3_MASK) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_0_MASK (0x1000000U) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_0_SHIFT (24U) /*! ISO_CTRL_0 - Isolation control for IP 0. * 0b0..disable isolation of IP 0 * 0b1..enable isolation of IP 0 */ #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_0_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_0_MASK) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_1_MASK (0x2000000U) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_1_SHIFT (25U) /*! ISO_CTRL_1 - Isolation control for IP 1. * 0b0..disable isolation of IP 1 * 0b1..enable isolation of IP 1 */ #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_1_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_1_MASK) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_2_MASK (0x4000000U) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_2_SHIFT (26U) /*! ISO_CTRL_2 - Isolation control for IP 2. * 0b0..disable isolation of IP 2 * 0b1..enable isolation of IP 2 */ #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_2_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_2_MASK) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_3_MASK (0x8000000U) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_3_SHIFT (27U) /*! ISO_CTRL_3 - Isolation control for IP 3. * 0b0..disable isolation of IP 3 * 0b1..enable isolation of IP 3 */ #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_3_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_3_MASK) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_4_MASK (0x10000000U) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_4_SHIFT (28U) /*! ISO_CTRL_4 - Isolation control for IP 4. * 0b0..disable isolation of IP 4 * 0b1..enable isolation of IP 4 */ #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_4_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_4_MASK) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_5_MASK (0x20000000U) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_5_SHIFT (29U) /*! ISO_CTRL_5 - Isolation control for IP 5. * 0b0..disable isolation of IP 5 * 0b1..enable isolation of IP 5 */ #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_5_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_5_MASK) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_6_MASK (0x40000000U) #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_6_SHIFT (30U) /*! ISO_CTRL_6 - Isolation control for IP 6. * 0b0..disable isolation of IP 6 * 0b1..enable isolation of IP 6 */ #define SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_6(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_6_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_ISO_CTRL_6_MASK) #define SRC_XSPR_SLICE_SW_CTRL_PDN_SOFT_MASK (0x80000000U) #define SRC_XSPR_SLICE_SW_CTRL_PDN_SOFT_SHIFT (31U) /*! PDN_SOFT - Software power trans control, including reset, iso, and power switch. * 0b0..Power Up Request * 0b1..Power Down Request */ #define SRC_XSPR_SLICE_SW_CTRL_PDN_SOFT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SLICE_SW_CTRL_PDN_SOFT_SHIFT)) & SRC_XSPR_SLICE_SW_CTRL_PDN_SOFT_MASK) /*! @} */ /*! @name IRST_REQ_CTRL - Individual Reset Request Control */ /*! @{ */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_0_MASK (0x1U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_0_SHIFT (0U) /*! RSTR_0_IRST_0 - reset request control for individual reset 0 in reset region 0 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_0_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_0_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_1_MASK (0x2U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_1_SHIFT (1U) /*! RSTR_0_IRST_1 - reset request control for individual reset 1 in reset region 0 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_1_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_1_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_2_MASK (0x4U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_2_SHIFT (2U) /*! RSTR_0_IRST_2 - reset request control for individual reset 2 in reset region 0 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_2_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_2_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_3_MASK (0x8U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_3_SHIFT (3U) /*! RSTR_0_IRST_3 - reset request control for individual reset 3 in reset region 0 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_3_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_3_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_4_MASK (0x10U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_4_SHIFT (4U) /*! RSTR_0_IRST_4 - reset request control for individual reset 4 in reset region 0 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_4_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_4_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_5_MASK (0x20U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_5_SHIFT (5U) /*! RSTR_0_IRST_5 - reset request control for individual reset 5 in reset region 0 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_5_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_0_IRST_5_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_0_MASK (0x100U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_0_SHIFT (8U) /*! RSTR_1_IRST_0 - reset request control for individual reset 0 in reset region 1 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_0_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_0_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_1_MASK (0x200U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_1_SHIFT (9U) /*! RSTR_1_IRST_1 - reset request control for individual reset 1 in reset region 1 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_1_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_1_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_2_MASK (0x400U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_2_SHIFT (10U) /*! RSTR_1_IRST_2 - reset request control for individual reset 2 in reset region 1 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_2_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_2_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_3_MASK (0x800U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_3_SHIFT (11U) /*! RSTR_1_IRST_3 - reset request control for individual reset 3 in reset region 1 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_3_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_3_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_4_MASK (0x1000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_4_SHIFT (12U) /*! RSTR_1_IRST_4 - reset request control for individual reset 4 in reset region 1 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_4_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_4_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_5_MASK (0x2000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_5_SHIFT (13U) /*! RSTR_1_IRST_5 - reset request control for individual reset 5 in reset region 1 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_5_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_1_IRST_5_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_0_MASK (0x10000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_0_SHIFT (16U) /*! RSTR_2_IRST_0 - reset request control for individual reset 0 in reset region 2 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_0_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_0_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_1_MASK (0x20000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_1_SHIFT (17U) /*! RSTR_2_IRST_1 - reset request control for individual reset 1 in reset region 2 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_1_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_1_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_2_MASK (0x40000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_2_SHIFT (18U) /*! RSTR_2_IRST_2 - reset request control for individual reset 2 in reset region 2 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_2_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_2_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_3_MASK (0x80000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_3_SHIFT (19U) /*! RSTR_2_IRST_3 - reset request control for individual reset 3 in reset region 2 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_3_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_3_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_4_MASK (0x100000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_4_SHIFT (20U) /*! RSTR_2_IRST_4 - reset request control for individual reset 4 in reset region 2 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_4_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_4_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_5_MASK (0x200000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_5_SHIFT (21U) /*! RSTR_2_IRST_5 - reset request control for individual reset 5 in reset region 2 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_5_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_2_IRST_5_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_0_MASK (0x1000000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_0_SHIFT (24U) /*! RSTR_3_IRST_0 - reset request control for individual reset 0 in reset region 3 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_0(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_0_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_0_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_1_MASK (0x2000000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_1_SHIFT (25U) /*! RSTR_3_IRST_1 - reset request control for individual reset 1 in reset region 3 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_1(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_1_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_1_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_2_MASK (0x4000000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_2_SHIFT (26U) /*! RSTR_3_IRST_2 - reset request control for individual reset 2 in reset region 3 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_2(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_2_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_2_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_3_MASK (0x8000000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_3_SHIFT (27U) /*! RSTR_3_IRST_3 - reset request control for individual reset 3 in reset region 3 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_3(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_3_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_3_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_4_MASK (0x10000000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_4_SHIFT (28U) /*! RSTR_3_IRST_4 - reset request control for individual reset 4 in reset region 3 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_4(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_4_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_4_MASK) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_5_MASK (0x20000000U) #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_5_SHIFT (29U) /*! RSTR_3_IRST_5 - reset request control for individual reset 5 in reset region 3 * 0b0..de-assert reset request * 0b1..assert reset request */ #define SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_5(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_5_SHIFT)) & SRC_XSPR_IRST_REQ_CTRL_RSTR_3_IRST_5_MASK) /*! @} */ /*! @name A55_HDSK_ACK_CTRL - A55 handshake acknowledge control */ /*! @{ */ #define SRC_XSPR_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_MASK (0xFFU) #define SRC_XSPR_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_SHIFT (0U) /*! A55_HDSK_CNT_CFG - A55 handshake count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ #define SRC_XSPR_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_SHIFT)) & SRC_XSPR_A55_HDSK_ACK_CTRL_A55_HDSK_CNT_CFG_MASK) #define SRC_XSPR_A55_HDSK_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) #define SRC_XSPR_A55_HDSK_ACK_CTRL_CNT_MODE_SHIFT (30U) /*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. * 0b00..Not use counter, raise a55_hdsk done to GPC once get A55 ack * 0b01..Delay after receiving a55 ack, delay cycle number is CNT_CFG * 0b10..Ignore A55 ack, raise a55_hdsk done to GPC when counting to CNT_CFG value * 0b11..Time out mode, raise a55_hdsk done to GPC when either A55 ack received or counting to CNT_CFG value */ #define SRC_XSPR_A55_HDSK_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_A55_HDSK_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_XSPR_A55_HDSK_ACK_CTRL_CNT_MODE_MASK) /*! @} */ /*! @name A55_HDSK_ACK_STAT - A55 handshake acknowledge status */ /*! @{ */ #define SRC_XSPR_A55_HDSK_ACK_STAT_PDN_ACK_CNT_MASK (0xFFU) #define SRC_XSPR_A55_HDSK_ACK_STAT_PDN_ACK_CNT_SHIFT (0U) /*! PDN_ACK_CNT - A55 handshake power down acknowledge count. */ #define SRC_XSPR_A55_HDSK_ACK_STAT_PDN_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_A55_HDSK_ACK_STAT_PDN_ACK_CNT_SHIFT)) & SRC_XSPR_A55_HDSK_ACK_STAT_PDN_ACK_CNT_MASK) #define SRC_XSPR_A55_HDSK_ACK_STAT_PUP_ACK_CNT_MASK (0xFF0000U) #define SRC_XSPR_A55_HDSK_ACK_STAT_PUP_ACK_CNT_SHIFT (16U) /*! PUP_ACK_CNT - A55 handshake power up acknowledge count */ #define SRC_XSPR_A55_HDSK_ACK_STAT_PUP_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_A55_HDSK_ACK_STAT_PUP_ACK_CNT_SHIFT)) & SRC_XSPR_A55_HDSK_ACK_STAT_PUP_ACK_CNT_MASK) #define SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_MASK (0x40000000U) #define SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_SHIFT (30U) /*! BUSY_A55_PDN_HDSK - Busy requesting A55 power down handshake */ #define SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_SHIFT)) & SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PDN_HDSK_MASK) #define SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_MASK (0x80000000U) #define SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_SHIFT (31U) /*! BUSY_A55_PUP_HDSK - Busy requesting A55 power up handshake */ #define SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_SHIFT)) & SRC_XSPR_A55_HDSK_ACK_STAT_BUSY_A55_PUP_HDSK_MASK) /*! @} */ /*! @name SYSMAN_ACK_CTRL - System Manager handshake acknowledge control */ /*! @{ */ #define SRC_XSPR_SYSMAN_ACK_CTRL_SYSMAN_CNT_CFG_MASK (0xFFU) #define SRC_XSPR_SYSMAN_ACK_CTRL_SYSMAN_CNT_CFG_SHIFT (0U) /*! SYSMAN_CNT_CFG - System Manager handshake count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ #define SRC_XSPR_SYSMAN_ACK_CTRL_SYSMAN_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SYSMAN_ACK_CTRL_SYSMAN_CNT_CFG_SHIFT)) & SRC_XSPR_SYSMAN_ACK_CTRL_SYSMAN_CNT_CFG_MASK) #define SRC_XSPR_SYSMAN_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) #define SRC_XSPR_SYSMAN_ACK_CTRL_CNT_MODE_SHIFT (30U) /*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. * 0b00..Not use counter, raise sysman_hdsk done to GPC once get System manager ack * 0b01..Delay after receiving system manager ack, delay cycle number is CNT_CFG * 0b10..Ignore system manager ack, raise sysman_hdsk done to GPC when counting to CNT_CFG value * 0b11..Time out mode, raise sysman_hdsk done to GPC when either system manager ack received or counting to CNT_CFG value */ #define SRC_XSPR_SYSMAN_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SYSMAN_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_XSPR_SYSMAN_ACK_CTRL_CNT_MODE_MASK) /*! @} */ /*! @name SYSMAN_ACK_STAT - System manager handshake acknowledge status */ /*! @{ */ #define SRC_XSPR_SYSMAN_ACK_STAT_PDN_ACK_CNT_MASK (0xFFU) #define SRC_XSPR_SYSMAN_ACK_STAT_PDN_ACK_CNT_SHIFT (0U) /*! PDN_ACK_CNT - System manager handshake power down acknowledge count. */ #define SRC_XSPR_SYSMAN_ACK_STAT_PDN_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SYSMAN_ACK_STAT_PDN_ACK_CNT_SHIFT)) & SRC_XSPR_SYSMAN_ACK_STAT_PDN_ACK_CNT_MASK) #define SRC_XSPR_SYSMAN_ACK_STAT_PUP_ACK_CNT_MASK (0xFF0000U) #define SRC_XSPR_SYSMAN_ACK_STAT_PUP_ACK_CNT_SHIFT (16U) /*! PUP_ACK_CNT - System manager handshake power up acknowledge count */ #define SRC_XSPR_SYSMAN_ACK_STAT_PUP_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SYSMAN_ACK_STAT_PUP_ACK_CNT_SHIFT)) & SRC_XSPR_SYSMAN_ACK_STAT_PUP_ACK_CNT_MASK) #define SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PDN_MASK (0x40000000U) #define SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PDN_SHIFT (30U) /*! BUSY_SYSMAN_PDN - Busy requesting System Manager power down handshake */ #define SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PDN(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PDN_SHIFT)) & SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PDN_MASK) #define SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PUP_MASK (0x80000000U) #define SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PUP_SHIFT (31U) /*! BUSY_SYSMAN_PUP - Busy requesting System manager power up handshake */ #define SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PUP(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PUP_SHIFT)) & SRC_XSPR_SYSMAN_ACK_STAT_BUSY_SYSMAN_PUP_MASK) /*! @} */ /*! @name SSAR_ACK_CTRL - SSAR acknowledge control */ /*! @{ */ #define SRC_XSPR_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK (0x3FFFU) #define SRC_XSPR_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT (0U) /*! SSAR_CNT_CFG - ssar count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ #define SRC_XSPR_SSAR_ACK_CTRL_SSAR_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SSAR_ACK_CTRL_SSAR_CNT_CFG_SHIFT)) & SRC_XSPR_SSAR_ACK_CTRL_SSAR_CNT_CFG_MASK) #define SRC_XSPR_SSAR_ACK_CTRL_CNT_MODE_MASK (0xC0000000U) #define SRC_XSPR_SSAR_ACK_CTRL_CNT_MODE_SHIFT (30U) /*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. * 0b00..Not use counter, raise ssar_save/restore done to GPC once get Edgelock Enclave ack * 0b01..Delay after receiving Edgelock Enclave ack, delay cycle number is CNT_CFG * 0b10..Ignore Edgelock Enclave ack, raise ssar_save/restore done to GPC when counting to CNT_CFG value * 0b11..Time out mode, raise ssar_save/restore done to GPC when either Edgelock Enclave ack received or counting to CNT_CFG value */ #define SRC_XSPR_SSAR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SSAR_ACK_CTRL_CNT_MODE_SHIFT)) & SRC_XSPR_SSAR_ACK_CTRL_CNT_MODE_MASK) /*! @} */ /*! @name SSAR_ACK_STAT - SSAR acknowledge status */ /*! @{ */ #define SRC_XSPR_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK (0x3FFFU) #define SRC_XSPR_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT (0U) /*! SAVE_ACK_CNT - SAVE acknowledge count, record the delay from stat change to acknowledge received */ #define SRC_XSPR_SSAR_ACK_STAT_SAVE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT)) & SRC_XSPR_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK) #define SRC_XSPR_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK (0xFFFC000U) #define SRC_XSPR_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT (14U) /*! RESTORE_ACK_CNT - RESTORE acknowledge count, record the delay from stat change to acknowledge received */ #define SRC_XSPR_SSAR_ACK_STAT_RESTORE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT)) & SRC_XSPR_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK) #define SRC_XSPR_SSAR_ACK_STAT_SAVED_MASK (0x20000000U) #define SRC_XSPR_SSAR_ACK_STAT_SAVED_SHIFT (29U) /*! SAVED - Indicate this mix power down info have accepted Edgelock Enclave ack */ #define SRC_XSPR_SSAR_ACK_STAT_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SSAR_ACK_STAT_SAVED_SHIFT)) & SRC_XSPR_SSAR_ACK_STAT_SAVED_MASK) #define SRC_XSPR_SSAR_ACK_STAT_BUSY_SAVED_MASK (0x40000000U) #define SRC_XSPR_SSAR_ACK_STAT_BUSY_SAVED_SHIFT (30U) /*! BUSY_SAVED - Busy requesting SSAR save */ #define SRC_XSPR_SSAR_ACK_STAT_BUSY_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SSAR_ACK_STAT_BUSY_SAVED_SHIFT)) & SRC_XSPR_SSAR_ACK_STAT_BUSY_SAVED_MASK) #define SRC_XSPR_SSAR_ACK_STAT_BUSY_RESTORE_MASK (0x80000000U) #define SRC_XSPR_SSAR_ACK_STAT_BUSY_RESTORE_SHIFT (31U) /*! BUSY_RESTORE - Busy requesting SSAR restore */ #define SRC_XSPR_SSAR_ACK_STAT_BUSY_RESTORE(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_SSAR_ACK_STAT_BUSY_RESTORE_SHIFT)) & SRC_XSPR_SSAR_ACK_STAT_BUSY_RESTORE_MASK) /*! @} */ /*! @name ISO_OFF_DLY_POR - iso off delay control when por */ /*! @{ */ #define SRC_XSPR_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_MASK (0xFFFFFFFFU) #define SRC_XSPR_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_SHIFT (0U) /*! DLY_PRE_ISO_OFF_POR - Delay from receiving iso off request to isolation disable. Locked by LOCK_CFG field. */ #define SRC_XSPR_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_SHIFT)) & SRC_XSPR_ISO_OFF_DLY_POR_DLY_PRE_ISO_OFF_POR_MASK) /*! @} */ /*! @name ISO_ON_DLY - iso on delay control */ /*! @{ */ #define SRC_XSPR_ISO_ON_DLY_DLY_PRE_ISO_ON_MASK (0xFFFFFFFFU) #define SRC_XSPR_ISO_ON_DLY_DLY_PRE_ISO_ON_SHIFT (0U) /*! DLY_PRE_ISO_ON - Delay from receiving iso_on request to isolation enable. Locked by LOCK_CFG field. */ #define SRC_XSPR_ISO_ON_DLY_DLY_PRE_ISO_ON(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_ISO_ON_DLY_DLY_PRE_ISO_ON_SHIFT)) & SRC_XSPR_ISO_ON_DLY_DLY_PRE_ISO_ON_MASK) /*! @} */ /*! @name ISO_OFF_DLY - iso off delay control */ /*! @{ */ #define SRC_XSPR_ISO_OFF_DLY_DLY_PRE_ISO_OFF_MASK (0xFFFFFFFFU) #define SRC_XSPR_ISO_OFF_DLY_DLY_PRE_ISO_OFF_SHIFT (0U) /*! DLY_PRE_ISO_OFF - Delay from receiving iso off request to isolation disable. Locked by LOCK_CFG field. */ #define SRC_XSPR_ISO_OFF_DLY_DLY_PRE_ISO_OFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_ISO_OFF_DLY_DLY_PRE_ISO_OFF_SHIFT)) & SRC_XSPR_ISO_OFF_DLY_DLY_PRE_ISO_OFF_MASK) /*! @} */ /*! @name PSW_OFF_LF_DLY - psw off lf delay control */ /*! @{ */ #define SRC_XSPR_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_MASK (0xFFFFFFFFU) #define SRC_XSPR_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_SHIFT (0U) /*! DLY_PRE_PSW_OFF_LF - Delay from receiving power off lf request to power switch shut off. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_SHIFT)) & SRC_XSPR_PSW_OFF_LF_DLY_DLY_PRE_PSW_OFF_LF_MASK) /*! @} */ /*! @name PSW_OFF_HF_DLY - psw off hf delay control */ /*! @{ */ #define SRC_XSPR_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_MASK (0xFFFFFFFFU) #define SRC_XSPR_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_SHIFT (0U) /*! DLY_PRE_PSW_OFF_HF - Delay from receiving power off hf request to power switch shut off. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_SHIFT)) & SRC_XSPR_PSW_OFF_HF_DLY_DLY_PRE_PSW_OFF_HF_MASK) /*! @} */ /*! @name PSW_ON_LF_DLY - psw on lf delay control */ /*! @{ */ #define SRC_XSPR_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_MASK (0xFFFFFFFFU) #define SRC_XSPR_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_SHIFT (0U) /*! DLY_PRE_PSW_ON_LF - Delay from receiving power on lf request to power switch turns on. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_SHIFT)) & SRC_XSPR_PSW_ON_LF_DLY_DLY_PRE_PSW_ON_LF_MASK) /*! @} */ /*! @name PSW_ON_HF_DLY - psw on hf delay control */ /*! @{ */ #define SRC_XSPR_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_MASK (0xFFFFFFFFU) #define SRC_XSPR_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_SHIFT (0U) /*! DLY_PRE_PSW_ON_HF - Delay from receiving power on lf request to power switch turns on. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_SHIFT)) & SRC_XSPR_PSW_ON_HF_DLY_DLY_PRE_PSW_ON_HF_MASK) /*! @} */ /*! @name PSW_ACK_CTRL_0 - Power switch acknowledge control */ /*! @{ */ #define SRC_XSPR_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_MASK (0x3FFU) #define SRC_XSPR_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_SHIFT (0U) /*! PUP_LF_CNT_CFG - PUP LF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_SHIFT)) & SRC_XSPR_PSW_ACK_CTRL_0_PUP_LF_CNT_CFG_MASK) #define SRC_XSPR_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_MASK (0x3FF0000U) #define SRC_XSPR_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_SHIFT (16U) /*! PUP_HF_CNT_CFG - PUP HF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_SHIFT)) & SRC_XSPR_PSW_ACK_CTRL_0_PUP_HF_CNT_CFG_MASK) #define SRC_XSPR_PSW_ACK_CTRL_0_CNT_MODE_MASK (0x30000000U) #define SRC_XSPR_PSW_ACK_CTRL_0_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Configure the acknowledge counter working mode. Locked by LOCK_CFG field. * 0b00..Not use counter, raise power_on/off done to GPC once get psw ack * 0b01..Delay after receiving psw ack, delay cycle number is CNT_CFG * 0b10..Ignore psw ack, raise power_on/off done to GPC when counting to CNT_CFG value * 0b11..Time out mode, raise power_on/off done to GPC when either psw ack received or counting to CNT_CFG value */ #define SRC_XSPR_PSW_ACK_CTRL_0_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_CTRL_0_CNT_MODE_SHIFT)) & SRC_XSPR_PSW_ACK_CTRL_0_CNT_MODE_MASK) #define SRC_XSPR_PSW_ACK_CTRL_0_LF_ACK_INVERT_MASK (0x40000000U) #define SRC_XSPR_PSW_ACK_CTRL_0_LF_ACK_INVERT_SHIFT (30U) /*! LF_ACK_INVERT - LF Acknowledge value is inverted from power switch control. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ACK_CTRL_0_LF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_CTRL_0_LF_ACK_INVERT_SHIFT)) & SRC_XSPR_PSW_ACK_CTRL_0_LF_ACK_INVERT_MASK) #define SRC_XSPR_PSW_ACK_CTRL_0_HF_ACK_INVERT_MASK (0x80000000U) #define SRC_XSPR_PSW_ACK_CTRL_0_HF_ACK_INVERT_SHIFT (31U) /*! HF_ACK_INVERT - HF Acknowledge value is inverted from power switch control. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ACK_CTRL_0_HF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_CTRL_0_HF_ACK_INVERT_SHIFT)) & SRC_XSPR_PSW_ACK_CTRL_0_HF_ACK_INVERT_MASK) /*! @} */ /*! @name PSW_ACK_CTRL_1 - Power switch acknowledge control */ /*! @{ */ #define SRC_XSPR_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_MASK (0x3FFU) #define SRC_XSPR_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_SHIFT (0U) /*! PDN_LF_CNT_CFG - PDN LF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_SHIFT)) & SRC_XSPR_PSW_ACK_CTRL_1_PDN_LF_CNT_CFG_MASK) #define SRC_XSPR_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_MASK (0x3FF0000U) #define SRC_XSPR_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_SHIFT (16U) /*! PDN_HF_CNT_CFG - PDN HF Count configure. Usage depends on CNT_MODE. Locked by LOCK_CFG field. */ #define SRC_XSPR_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_SHIFT)) & SRC_XSPR_PSW_ACK_CTRL_1_PDN_HF_CNT_CFG_MASK) /*! @} */ /*! @name PSW_ACK_STAT - PSW acknowledge status */ /*! @{ */ #define SRC_XSPR_PSW_ACK_STAT_LF_ACK_CNT_MASK (0x3FFU) #define SRC_XSPR_PSW_ACK_STAT_LF_ACK_CNT_SHIFT (0U) /*! LF_ACK_CNT - LF PSW acknowledge count */ #define SRC_XSPR_PSW_ACK_STAT_LF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_STAT_LF_ACK_CNT_SHIFT)) & SRC_XSPR_PSW_ACK_STAT_LF_ACK_CNT_MASK) #define SRC_XSPR_PSW_ACK_STAT_HF_ACK_CNT_MASK (0x3FF0000U) #define SRC_XSPR_PSW_ACK_STAT_HF_ACK_CNT_SHIFT (16U) /*! HF_ACK_CNT - HF PSW acknowledge count */ #define SRC_XSPR_PSW_ACK_STAT_HF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_STAT_HF_ACK_CNT_SHIFT)) & SRC_XSPR_PSW_ACK_STAT_HF_ACK_CNT_MASK) #define SRC_XSPR_PSW_ACK_STAT_LF_ACK_STAT_MASK (0x40000000U) #define SRC_XSPR_PSW_ACK_STAT_LF_ACK_STAT_SHIFT (30U) /*! LF_ACK_STAT - LF PSW acknowledge status */ #define SRC_XSPR_PSW_ACK_STAT_LF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_STAT_LF_ACK_STAT_SHIFT)) & SRC_XSPR_PSW_ACK_STAT_LF_ACK_STAT_MASK) #define SRC_XSPR_PSW_ACK_STAT_HF_ACK_STAT_MASK (0x80000000U) #define SRC_XSPR_PSW_ACK_STAT_HF_ACK_STAT_SHIFT (31U) /*! HF_ACK_STAT - HF PSW acknowledge status */ #define SRC_XSPR_PSW_ACK_STAT_HF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_PSW_ACK_STAT_HF_ACK_STAT_SHIFT)) & SRC_XSPR_PSW_ACK_STAT_HF_ACK_STAT_MASK) /*! @} */ /*! @name UPI_STAT_0 - UPI status 0 */ /*! @{ */ #define SRC_XSPR_UPI_STAT_0_UPI_ISO_REQUEST_MASK (0xFFFFU) #define SRC_XSPR_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT (0U) /*! UPI_ISO_REQUEST - CPU mode trans iso request of 16 domains */ #define SRC_XSPR_UPI_STAT_0_UPI_ISO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_UPI_STAT_0_UPI_ISO_REQUEST_SHIFT)) & SRC_XSPR_UPI_STAT_0_UPI_ISO_REQUEST_MASK) #define SRC_XSPR_UPI_STAT_0_UPI_POWER_REQUEST_MASK (0xFFFF0000U) #define SRC_XSPR_UPI_STAT_0_UPI_POWER_REQUEST_SHIFT (16U) /*! UPI_POWER_REQUEST - CPU mode trans power request of 16 domains */ #define SRC_XSPR_UPI_STAT_0_UPI_POWER_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_UPI_STAT_0_UPI_POWER_REQUEST_SHIFT)) & SRC_XSPR_UPI_STAT_0_UPI_POWER_REQUEST_MASK) /*! @} */ /*! @name UPI_STAT_1 - UPI status 1 */ /*! @{ */ #define SRC_XSPR_UPI_STAT_1_UPI_RESET_REQUEST_MASK (0xFFFFU) #define SRC_XSPR_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT (0U) /*! UPI_RESET_REQUEST - CPU mode trans reset request of 16 domains */ #define SRC_XSPR_UPI_STAT_1_UPI_RESET_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_UPI_STAT_1_UPI_RESET_REQUEST_SHIFT)) & SRC_XSPR_UPI_STAT_1_UPI_RESET_REQUEST_MASK) #define SRC_XSPR_UPI_STAT_1_UPI_SSAR_REQUEST_MASK (0xFFFF0000U) #define SRC_XSPR_UPI_STAT_1_UPI_SSAR_REQUEST_SHIFT (16U) /*! UPI_SSAR_REQUEST - CPU mode trans ssar request of 16 domains */ #define SRC_XSPR_UPI_STAT_1_UPI_SSAR_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_UPI_STAT_1_UPI_SSAR_REQUEST_SHIFT)) & SRC_XSPR_UPI_STAT_1_UPI_SSAR_REQUEST_MASK) /*! @} */ /*! @name UPI_STAT_2 - UPI status 2 */ /*! @{ */ #define SRC_XSPR_UPI_STAT_2_UPI_A55_HDSK_REQUEST_MASK (0xFFFF0000U) #define SRC_XSPR_UPI_STAT_2_UPI_A55_HDSK_REQUEST_SHIFT (16U) /*! UPI_A55_HDSK_REQUEST - CPU mode trans A55 handshake request of 16 domains */ #define SRC_XSPR_UPI_STAT_2_UPI_A55_HDSK_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_UPI_STAT_2_UPI_A55_HDSK_REQUEST_SHIFT)) & SRC_XSPR_UPI_STAT_2_UPI_A55_HDSK_REQUEST_MASK) /*! @} */ /*! @name UPI_STAT_3 - UPI status 3 */ /*! @{ */ #define SRC_XSPR_UPI_STAT_3_UPI_MEM_REQUEST_MASK (0xFFFFU) #define SRC_XSPR_UPI_STAT_3_UPI_MEM_REQUEST_SHIFT (0U) /*! UPI_MEM_REQUEST - CPU mode trans mem request of 16 domains */ #define SRC_XSPR_UPI_STAT_3_UPI_MEM_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_UPI_STAT_3_UPI_MEM_REQUEST_SHIFT)) & SRC_XSPR_UPI_STAT_3_UPI_MEM_REQUEST_MASK) #define SRC_XSPR_UPI_STAT_3_UPI_SYSMAN_REQUEST_MASK (0xFFFF0000U) #define SRC_XSPR_UPI_STAT_3_UPI_SYSMAN_REQUEST_SHIFT (16U) /*! UPI_SYSMAN_REQUEST - CPU mode trans system manager request of 16 domains */ #define SRC_XSPR_UPI_STAT_3_UPI_SYSMAN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_UPI_STAT_3_UPI_SYSMAN_REQUEST_SHIFT)) & SRC_XSPR_UPI_STAT_3_UPI_SYSMAN_REQUEST_MASK) /*! @} */ /*! @name FSM_STAT - FSM status */ /*! @{ */ #define SRC_XSPR_FSM_STAT_PSW_STAT_MASK (0xFU) #define SRC_XSPR_FSM_STAT_PSW_STAT_SHIFT (0U) /*! PSW_STAT - Power switch FSM status */ #define SRC_XSPR_FSM_STAT_PSW_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FSM_STAT_PSW_STAT_SHIFT)) & SRC_XSPR_FSM_STAT_PSW_STAT_MASK) #define SRC_XSPR_FSM_STAT_RST_STAT_MASK (0xF0U) #define SRC_XSPR_FSM_STAT_RST_STAT_SHIFT (4U) /*! RST_STAT - Reset FSM status */ #define SRC_XSPR_FSM_STAT_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FSM_STAT_RST_STAT_SHIFT)) & SRC_XSPR_FSM_STAT_RST_STAT_MASK) #define SRC_XSPR_FSM_STAT_ISO_STAT_MASK (0xF00U) #define SRC_XSPR_FSM_STAT_ISO_STAT_SHIFT (8U) /*! ISO_STAT - Isolation FSM status */ #define SRC_XSPR_FSM_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FSM_STAT_ISO_STAT_SHIFT)) & SRC_XSPR_FSM_STAT_ISO_STAT_MASK) #define SRC_XSPR_FSM_STAT_SSAR_STAT_MASK (0x70000U) #define SRC_XSPR_FSM_STAT_SSAR_STAT_SHIFT (16U) /*! SSAR_STAT - SSAR FSM status */ #define SRC_XSPR_FSM_STAT_SSAR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FSM_STAT_SSAR_STAT_SHIFT)) & SRC_XSPR_FSM_STAT_SSAR_STAT_MASK) #define SRC_XSPR_FSM_STAT_A55_HDSK_STAT_MASK (0xF00000U) #define SRC_XSPR_FSM_STAT_A55_HDSK_STAT_SHIFT (20U) /*! A55_HDSK_STAT - A55 handshake FSM status */ #define SRC_XSPR_FSM_STAT_A55_HDSK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FSM_STAT_A55_HDSK_STAT_SHIFT)) & SRC_XSPR_FSM_STAT_A55_HDSK_STAT_MASK) #define SRC_XSPR_FSM_STAT_MEM_STAT_MASK (0x7000000U) #define SRC_XSPR_FSM_STAT_MEM_STAT_SHIFT (24U) /*! MEM_STAT - Memory FSM status */ #define SRC_XSPR_FSM_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FSM_STAT_MEM_STAT_SHIFT)) & SRC_XSPR_FSM_STAT_MEM_STAT_MASK) #define SRC_XSPR_FSM_STAT_SYSMAN_STAT_MASK (0xF0000000U) #define SRC_XSPR_FSM_STAT_SYSMAN_STAT_SHIFT (28U) /*! SYSMAN_STAT - System Manager handshake FSM status */ #define SRC_XSPR_FSM_STAT_SYSMAN_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FSM_STAT_SYSMAN_STAT_SHIFT)) & SRC_XSPR_FSM_STAT_SYSMAN_STAT_MASK) /*! @} */ /*! @name FUNC_STAT - function status */ /*! @{ */ #define SRC_XSPR_FUNC_STAT_PSW_STAT_MASK (0x1U) #define SRC_XSPR_FUNC_STAT_PSW_STAT_SHIFT (0U) /*! PSW_STAT - Power switch status * 0b0..Power switch on * 0b1..Power switch off */ #define SRC_XSPR_FUNC_STAT_PSW_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FUNC_STAT_PSW_STAT_SHIFT)) & SRC_XSPR_FUNC_STAT_PSW_STAT_MASK) #define SRC_XSPR_FUNC_STAT_RST_STAT_MASK (0x4U) #define SRC_XSPR_FUNC_STAT_RST_STAT_SHIFT (2U) /*! RST_STAT - Reset status * 0b0..Reset assert * 0b1..Reset release */ #define SRC_XSPR_FUNC_STAT_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FUNC_STAT_RST_STAT_SHIFT)) & SRC_XSPR_FUNC_STAT_RST_STAT_MASK) #define SRC_XSPR_FUNC_STAT_ISO_STAT_MASK (0x10U) #define SRC_XSPR_FUNC_STAT_ISO_STAT_SHIFT (4U) /*! ISO_STAT - Isolation status * 0b0..Isolation off * 0b1..Isolation on */ #define SRC_XSPR_FUNC_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FUNC_STAT_ISO_STAT_SHIFT)) & SRC_XSPR_FUNC_STAT_ISO_STAT_MASK) #define SRC_XSPR_FUNC_STAT_SSAR_STAT_MASK (0x100U) #define SRC_XSPR_FUNC_STAT_SSAR_STAT_SHIFT (8U) /*! SSAR_STAT - ssar status * 0b0..No effect or power up handshake with Edgelock Enclave done * 0b1..Power down handshake with Edgelock Enclave done */ #define SRC_XSPR_FUNC_STAT_SSAR_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FUNC_STAT_SSAR_STAT_SHIFT)) & SRC_XSPR_FUNC_STAT_SSAR_STAT_MASK) #define SRC_XSPR_FUNC_STAT_A55_HDSK_STAT_MASK (0x400U) #define SRC_XSPR_FUNC_STAT_A55_HDSK_STAT_SHIFT (10U) /*! A55_HDSK_STAT - A55 handshake status * 0b0..No effect or power up handshake with A55 done(just for A55 SLICE) * 0b1..Power down handshake with A55 done(just for A55 SLICE) */ #define SRC_XSPR_FUNC_STAT_A55_HDSK_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FUNC_STAT_A55_HDSK_STAT_SHIFT)) & SRC_XSPR_FUNC_STAT_A55_HDSK_STAT_MASK) #define SRC_XSPR_FUNC_STAT_MEM_STAT_MASK (0x1000U) #define SRC_XSPR_FUNC_STAT_MEM_STAT_SHIFT (12U) /*! MEM_STAT - Memory w/ status * 0b0..No effect or memory w/ exit LP done * 0b1..Memory w/ enter LP done */ #define SRC_XSPR_FUNC_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FUNC_STAT_MEM_STAT_SHIFT)) & SRC_XSPR_FUNC_STAT_MEM_STAT_MASK) #define SRC_XSPR_FUNC_STAT_SYSMAN_STAT_MASK (0x4000U) #define SRC_XSPR_FUNC_STAT_SYSMAN_STAT_SHIFT (14U) /*! SYSMAN_STAT - System Manager handshake status * 0b0..No effect or power up handshake with SYSMAN done * 0b1..Power down handshake with SYSMAN done */ #define SRC_XSPR_FUNC_STAT_SYSMAN_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_FUNC_STAT_SYSMAN_STAT_SHIFT)) & SRC_XSPR_FUNC_STAT_SYSMAN_STAT_MASK) /*! @} */ /*! @name RSTR_STAT - Reset Region Status Register */ /*! @{ */ #define SRC_XSPR_RSTR_STAT_RSTR_0_RST_STAT_MASK (0x1U) #define SRC_XSPR_RSTR_STAT_RSTR_0_RST_STAT_SHIFT (0U) /*! RSTR_0_RST_STAT - Reset Status of Reset Region 0 * 0b0..Reset Region 0 is out of reset * 0b1..Reset Region 0 is in reset */ #define SRC_XSPR_RSTR_STAT_RSTR_0_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_0_RST_STAT_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_0_RST_STAT_MASK) #define SRC_XSPR_RSTR_STAT_RSTR_1_RST_STAT_MASK (0x2U) #define SRC_XSPR_RSTR_STAT_RSTR_1_RST_STAT_SHIFT (1U) /*! RSTR_1_RST_STAT - Reset Status of Reset Region 1 * 0b0..Reset Region 1 is out of reset * 0b1..Reset Region 1 is in reset */ #define SRC_XSPR_RSTR_STAT_RSTR_1_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_1_RST_STAT_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_1_RST_STAT_MASK) #define SRC_XSPR_RSTR_STAT_RSTR_2_RST_STAT_MASK (0x4U) #define SRC_XSPR_RSTR_STAT_RSTR_2_RST_STAT_SHIFT (2U) /*! RSTR_2_RST_STAT - Reset Status of Reset Region 2 * 0b0..Reset Region 2 is out of reset * 0b1..Reset Region 2 is in reset */ #define SRC_XSPR_RSTR_STAT_RSTR_2_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_2_RST_STAT_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_2_RST_STAT_MASK) #define SRC_XSPR_RSTR_STAT_RSTR_3_RST_STAT_MASK (0x8U) #define SRC_XSPR_RSTR_STAT_RSTR_3_RST_STAT_SHIFT (3U) /*! RSTR_3_RST_STAT - Reset Status of Reset Region 3 * 0b0..Reset Region 3 is out of reset * 0b1..Reset Region 3 is in reset */ #define SRC_XSPR_RSTR_STAT_RSTR_3_RST_STAT(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_3_RST_STAT_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_3_RST_STAT_MASK) #define SRC_XSPR_RSTR_STAT_RSTR_0_RST_BUSY_MASK (0x10000U) #define SRC_XSPR_RSTR_STAT_RSTR_0_RST_BUSY_SHIFT (16U) /*! RSTR_0_RST_BUSY - Reset Sequence Busy of Reset Region 0 * 0b0..Reset Region 0 reset sequence not running * 0b1..Reset Region 0 reset sequence is running */ #define SRC_XSPR_RSTR_STAT_RSTR_0_RST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_0_RST_BUSY_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_0_RST_BUSY_MASK) #define SRC_XSPR_RSTR_STAT_RSTR_1_RST_BUSY_MASK (0x20000U) #define SRC_XSPR_RSTR_STAT_RSTR_1_RST_BUSY_SHIFT (17U) /*! RSTR_1_RST_BUSY - Reset Sequence Busy of Reset Region 1 * 0b0..Reset Region 1 reset sequence not running * 0b1..Reset Region 1 reset sequence is running */ #define SRC_XSPR_RSTR_STAT_RSTR_1_RST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_1_RST_BUSY_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_1_RST_BUSY_MASK) #define SRC_XSPR_RSTR_STAT_RSTR_2_RST_BUSY_MASK (0x40000U) #define SRC_XSPR_RSTR_STAT_RSTR_2_RST_BUSY_SHIFT (18U) /*! RSTR_2_RST_BUSY - Reset Sequence Busy of Reset Region 2 * 0b0..Reset Region 2 reset sequence not running * 0b1..Reset Region 2 reset sequence is running */ #define SRC_XSPR_RSTR_STAT_RSTR_2_RST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_2_RST_BUSY_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_2_RST_BUSY_MASK) #define SRC_XSPR_RSTR_STAT_RSTR_3_RST_BUSY_MASK (0x80000U) #define SRC_XSPR_RSTR_STAT_RSTR_3_RST_BUSY_SHIFT (19U) /*! RSTR_3_RST_BUSY - Reset Sequence Busy of Reset Region 3 * 0b0..Reset Region 3 reset sequence not running * 0b1..Reset Region 3 reset sequence is running */ #define SRC_XSPR_RSTR_STAT_RSTR_3_RST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SRC_XSPR_RSTR_STAT_RSTR_3_RST_BUSY_SHIFT)) & SRC_XSPR_RSTR_STAT_RSTR_3_RST_BUSY_MASK) /*! @} */ /*! * @} */ /* end of group SRC_XSPR_Register_Masks */ /* SRC_XSPR - Peripheral instance base addresses */ /** Peripheral CCMSRCGPC__SRC__XSPR_ANAMIX base address */ #define CCMSRCGPC__SRC__XSPR_ANAMIX_BASE (0x44460400u) /** Peripheral CCMSRCGPC__SRC__XSPR_ANAMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_ANAMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_ANAMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_AONMIX base address */ #define CCMSRCGPC__SRC__XSPR_AONMIX_BASE (0x44460800u) /** Peripheral CCMSRCGPC__SRC__XSPR_AONMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_AONMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_AONMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_BBSMMIX base address */ #define CCMSRCGPC__SRC__XSPR_BBSMMIX_BASE (0x44460C00u) /** Peripheral CCMSRCGPC__SRC__XSPR_BBSMMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_BBSMMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_BBSMMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CAMERAMIX base address */ #define CCMSRCGPC__SRC__XSPR_CAMERAMIX_BASE (0x44461000u) /** Peripheral CCMSRCGPC__SRC__XSPR_CAMERAMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_CAMERAMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CAMERAMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX base address */ #define CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX_BASE (0x44461400u) /** Peripheral CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_BASE (0x44461800u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0 ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_BASE (0x44461C00u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1 ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_BASE (0x44462000u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2 ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_BASE (0x44462400u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3 ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_BASE (0x44462800u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4 ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5 base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_BASE (0x44462C00u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5 base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5 ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM base address */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_BASE (0x44463000u) /** Peripheral CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM base pointer */ #define CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_DDRMIX base address */ #define CCMSRCGPC__SRC__XSPR_DDRMIX_BASE (0x44463400u) /** Peripheral CCMSRCGPC__SRC__XSPR_DDRMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_DDRMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_DDRMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_DISPLAYMIX base address */ #define CCMSRCGPC__SRC__XSPR_DISPLAYMIX_BASE (0x44463800u) /** Peripheral CCMSRCGPC__SRC__XSPR_DISPLAYMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_DISPLAYMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_DISPLAYMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_GPUMIX base address */ #define CCMSRCGPC__SRC__XSPR_GPUMIX_BASE (0x44463C00u) /** Peripheral CCMSRCGPC__SRC__XSPR_GPUMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_GPUMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_GPUMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP base address */ #define CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP_BASE (0x44464000u) /** Peripheral CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP base pointer */ #define CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON base address */ #define CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON_BASE (0x44464400u) /** Peripheral CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON base pointer */ #define CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_M7MIX base address */ #define CCMSRCGPC__SRC__XSPR_M7MIX_BASE (0x44464800u) /** Peripheral CCMSRCGPC__SRC__XSPR_M7MIX base pointer */ #define CCMSRCGPC__SRC__XSPR_M7MIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_M7MIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_NETCMIX base address */ #define CCMSRCGPC__SRC__XSPR_NETCMIX_BASE (0x44464C00u) /** Peripheral CCMSRCGPC__SRC__XSPR_NETCMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_NETCMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_NETCMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_NOCMIX base address */ #define CCMSRCGPC__SRC__XSPR_NOCMIX_BASE (0x44465000u) /** Peripheral CCMSRCGPC__SRC__XSPR_NOCMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_NOCMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_NOCMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_NPUMIX base address */ #define CCMSRCGPC__SRC__XSPR_NPUMIX_BASE (0x44465400u) /** Peripheral CCMSRCGPC__SRC__XSPR_NPUMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_NPUMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_NPUMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_VPUMIX base address */ #define CCMSRCGPC__SRC__XSPR_VPUMIX_BASE (0x44465800u) /** Peripheral CCMSRCGPC__SRC__XSPR_VPUMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_VPUMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_VPUMIX_BASE) /** Peripheral CCMSRCGPC__SRC__XSPR_WAKEUPMIX base address */ #define CCMSRCGPC__SRC__XSPR_WAKEUPMIX_BASE (0x44465C00u) /** Peripheral CCMSRCGPC__SRC__XSPR_WAKEUPMIX base pointer */ #define CCMSRCGPC__SRC__XSPR_WAKEUPMIX ((SRC_XSPR_Type *)CCMSRCGPC__SRC__XSPR_WAKEUPMIX_BASE) /** Array initializer of SRC_XSPR peripheral base addresses */ #define SRC_XSPR_BASE_ADDRS { CCMSRCGPC__SRC__XSPR_ANAMIX_BASE, CCMSRCGPC__SRC__XSPR_AONMIX_BASE, CCMSRCGPC__SRC__XSPR_BBSMMIX_BASE, CCMSRCGPC__SRC__XSPR_CAMERAMIX_BASE, CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_BASE, CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_BASE, CCMSRCGPC__SRC__XSPR_DDRMIX_BASE, CCMSRCGPC__SRC__XSPR_DISPLAYMIX_BASE, CCMSRCGPC__SRC__XSPR_GPUMIX_BASE, CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP_BASE, CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON_BASE, CCMSRCGPC__SRC__XSPR_M7MIX_BASE, CCMSRCGPC__SRC__XSPR_NETCMIX_BASE, CCMSRCGPC__SRC__XSPR_NOCMIX_BASE, CCMSRCGPC__SRC__XSPR_NPUMIX_BASE, CCMSRCGPC__SRC__XSPR_VPUMIX_BASE, CCMSRCGPC__SRC__XSPR_WAKEUPMIX_BASE } /** Array initializer of SRC_XSPR peripheral base pointers */ #define SRC_XSPR_BASE_PTRS { CCMSRCGPC__SRC__XSPR_ANAMIX, CCMSRCGPC__SRC__XSPR_AONMIX, CCMSRCGPC__SRC__XSPR_BBSMMIX, CCMSRCGPC__SRC__XSPR_CAMERAMIX, CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4, CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5, CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM, CCMSRCGPC__SRC__XSPR_DDRMIX, CCMSRCGPC__SRC__XSPR_DISPLAYMIX, CCMSRCGPC__SRC__XSPR_GPUMIX, CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP, CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON, CCMSRCGPC__SRC__XSPR_M7MIX, CCMSRCGPC__SRC__XSPR_NETCMIX, CCMSRCGPC__SRC__XSPR_NOCMIX, CCMSRCGPC__SRC__XSPR_NPUMIX, CCMSRCGPC__SRC__XSPR_VPUMIX, CCMSRCGPC__SRC__XSPR_WAKEUPMIX } /*! * @} */ /* end of group SRC_XSPR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- STAT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup STAT_Peripheral_Access_Layer STAT Peripheral Access Layer * @{ */ /** STAT - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x40 */ __IO uint32_t ROI0_POS_CAM; /**< Camera 0 Statistics Region of Interest 0 Position Register, array offset: 0x0, array step: 0x40 */ __IO uint32_t ROI0_SIZE_CAM; /**< Camera 0 Statistics Region of Interest 0 Size Register, array offset: 0x4, array step: 0x40 */ __IO uint32_t ROI1_POS_CAM; /**< Camera 0 Statistics Region of Interest 1 Position Register, array offset: 0x8, array step: 0x40 */ __IO uint32_t ROI1_SIZE_CAM; /**< Camera 0 Statistics Region of Interest 1 Size Register, array offset: 0xC, array step: 0x40 */ uint8_t RESERVED_0[16]; struct { /* offset: 0x20, array step: index*0x40, index2*0x8 */ __IO uint32_t CTRL_CAM; /**< Camera 0 Histogram 0 Control Register..Camera 0 Histogram 3 Control Register, array offset: 0x20, array step: index*0x40, index2*0x8 */ __IO uint32_t SCALE_CAM; /**< Camera 0 Histogram 0 Scale Register..Camera 0 Histogram 3 Scale Register, array offset: 0x24, array step: index*0x40, index2*0x8 */ } HIST[4]; } NEO_PIPE1_STAT[1]; } STAT_Type; /* ---------------------------------------------------------------------------- -- STAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup STAT_Register_Masks STAT Register Masks * @{ */ /*! @name ROI0_POS_CAM - Camera 0 Statistics Region of Interest 0 Position Register */ /*! @{ */ #define STAT_ROI0_POS_CAM_XPOS_MASK (0xFFFFU) #define STAT_ROI0_POS_CAM_XPOS_SHIFT (0U) #define STAT_ROI0_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI0_POS_CAM_XPOS_SHIFT)) & STAT_ROI0_POS_CAM_XPOS_MASK) #define STAT_ROI0_POS_CAM_YPOS_MASK (0xFFFF0000U) #define STAT_ROI0_POS_CAM_YPOS_SHIFT (16U) #define STAT_ROI0_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI0_POS_CAM_YPOS_SHIFT)) & STAT_ROI0_POS_CAM_YPOS_MASK) /*! @} */ /* The count of STAT_ROI0_POS_CAM */ #define STAT_ROI0_POS_CAM_COUNT (1U) /*! @name ROI0_SIZE_CAM - Camera 0 Statistics Region of Interest 0 Size Register */ /*! @{ */ #define STAT_ROI0_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define STAT_ROI0_SIZE_CAM_WIDTH_SHIFT (0U) #define STAT_ROI0_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI0_SIZE_CAM_WIDTH_SHIFT)) & STAT_ROI0_SIZE_CAM_WIDTH_MASK) #define STAT_ROI0_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define STAT_ROI0_SIZE_CAM_HEIGHT_SHIFT (16U) #define STAT_ROI0_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI0_SIZE_CAM_HEIGHT_SHIFT)) & STAT_ROI0_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of STAT_ROI0_SIZE_CAM */ #define STAT_ROI0_SIZE_CAM_COUNT (1U) /*! @name ROI1_POS_CAM - Camera 0 Statistics Region of Interest 1 Position Register */ /*! @{ */ #define STAT_ROI1_POS_CAM_XPOS_MASK (0xFFFFU) #define STAT_ROI1_POS_CAM_XPOS_SHIFT (0U) #define STAT_ROI1_POS_CAM_XPOS(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI1_POS_CAM_XPOS_SHIFT)) & STAT_ROI1_POS_CAM_XPOS_MASK) #define STAT_ROI1_POS_CAM_YPOS_MASK (0xFFFF0000U) #define STAT_ROI1_POS_CAM_YPOS_SHIFT (16U) #define STAT_ROI1_POS_CAM_YPOS(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI1_POS_CAM_YPOS_SHIFT)) & STAT_ROI1_POS_CAM_YPOS_MASK) /*! @} */ /* The count of STAT_ROI1_POS_CAM */ #define STAT_ROI1_POS_CAM_COUNT (1U) /*! @name ROI1_SIZE_CAM - Camera 0 Statistics Region of Interest 1 Size Register */ /*! @{ */ #define STAT_ROI1_SIZE_CAM_WIDTH_MASK (0xFFFFU) #define STAT_ROI1_SIZE_CAM_WIDTH_SHIFT (0U) #define STAT_ROI1_SIZE_CAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI1_SIZE_CAM_WIDTH_SHIFT)) & STAT_ROI1_SIZE_CAM_WIDTH_MASK) #define STAT_ROI1_SIZE_CAM_HEIGHT_MASK (0xFFFF0000U) #define STAT_ROI1_SIZE_CAM_HEIGHT_SHIFT (16U) #define STAT_ROI1_SIZE_CAM_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << STAT_ROI1_SIZE_CAM_HEIGHT_SHIFT)) & STAT_ROI1_SIZE_CAM_HEIGHT_MASK) /*! @} */ /* The count of STAT_ROI1_SIZE_CAM */ #define STAT_ROI1_SIZE_CAM_COUNT (1U) /*! @name CTRL_CAM - Camera 0 Histogram 0 Control Register..Camera 0 Histogram 3 Control Register */ /*! @{ */ #define STAT_CTRL_CAM_LIN_VS_LOG_MASK (0x1U) #define STAT_CTRL_CAM_LIN_VS_LOG_SHIFT (0U) /*! LIN_VS_LOG * 0b0..Linear: Scaled pixel value provides the bin number. * 0b1..Logarithmic: Log operation is performed scaled pixel value for providing the bin number. */ #define STAT_CTRL_CAM_LIN_VS_LOG(x) (((uint32_t)(((uint32_t)(x)) << STAT_CTRL_CAM_LIN_VS_LOG_SHIFT)) & STAT_CTRL_CAM_LIN_VS_LOG_MASK) #define STAT_CTRL_CAM_DIR_VS_DIF_MASK (0x2U) #define STAT_CTRL_CAM_DIR_VS_DIF_SHIFT (1U) /*! DIR_VS_DIF * 0b0..Direct: Use pixel value for correcting the black level offset & scaling. * 0b1..Difference: Use difference with left neighboring pixel of same channel for the black level offset & scaling. */ #define STAT_CTRL_CAM_DIR_VS_DIF(x) (((uint32_t)(((uint32_t)(x)) << STAT_CTRL_CAM_DIR_VS_DIF_SHIFT)) & STAT_CTRL_CAM_DIR_VS_DIF_MASK) #define STAT_CTRL_CAM_PATTERN_MASK (0x4U) #define STAT_CTRL_CAM_PATTERN_SHIFT (2U) /*! PATTERN * 0b0..1x1: Neighboring pixel is 1 position to the left * 0b1..2x2: Neighboring pixel is 2 position to the left */ #define STAT_CTRL_CAM_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << STAT_CTRL_CAM_PATTERN_SHIFT)) & STAT_CTRL_CAM_PATTERN_MASK) #define STAT_CTRL_CAM_CHANNEL_MASK (0xF00U) #define STAT_CTRL_CAM_CHANNEL_SHIFT (8U) /*! CHANNEL * 0b0001..Position of 1 indicates, Red (R) pixels of a RGGB Bayer pattern * 0b0010..Position of 1 indicates, Green (Gr) pixels of a RGGB Bayer pattern * 0b0100..Position of 1 indicates, Green (Gb) pixels of a RGGB Bayer pattern * 0b1000..Position of 1 indicates, Blue (B) pixels of a RGGB Bayer pattern */ #define STAT_CTRL_CAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << STAT_CTRL_CAM_CHANNEL_SHIFT)) & STAT_CTRL_CAM_CHANNEL_MASK) #define STAT_CTRL_CAM_OFFSET_MASK (0xFFFF0000U) #define STAT_CTRL_CAM_OFFSET_SHIFT (16U) #define STAT_CTRL_CAM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << STAT_CTRL_CAM_OFFSET_SHIFT)) & STAT_CTRL_CAM_OFFSET_MASK) /*! @} */ /* The count of STAT_CTRL_CAM */ #define STAT_CTRL_CAM_COUNT (1U) /* The count of STAT_CTRL_CAM */ #define STAT_CTRL_CAM_COUNT2 (4U) /*! @name SCALE_CAM - Camera 0 Histogram 0 Scale Register..Camera 0 Histogram 3 Scale Register */ /*! @{ */ #define STAT_SCALE_CAM_SCALE_MASK (0xFFFFFFU) #define STAT_SCALE_CAM_SCALE_SHIFT (0U) #define STAT_SCALE_CAM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << STAT_SCALE_CAM_SCALE_SHIFT)) & STAT_SCALE_CAM_SCALE_MASK) /*! @} */ /* The count of STAT_SCALE_CAM */ #define STAT_SCALE_CAM_COUNT (1U) /* The count of STAT_SCALE_CAM */ #define STAT_SCALE_CAM_COUNT2 (4U) /*! * @} */ /* end of group STAT_Register_Masks */ /* STAT - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__STAT base address */ #define CAMERA__ISP__STAT_BASE (0x4AE00700u) /** Peripheral CAMERA__ISP__STAT base pointer */ #define CAMERA__ISP__STAT ((STAT_Type *)CAMERA__ISP__STAT_BASE) /** Array initializer of STAT peripheral base addresses */ #define STAT_BASE_ADDRS { CAMERA__ISP__STAT_BASE } /** Array initializer of STAT peripheral base pointers */ #define STAT_BASE_PTRS { CAMERA__ISP__STAT } /*! * @} */ /* end of group STAT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SYS_CTR_COMPARE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SYS_CTR_COMPARE_Peripheral_Access_Layer SYS_CTR_COMPARE Peripheral Access Layer * @{ */ /** SYS_CTR_COMPARE - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[32]; __IO uint32_t CMPCVL0; /**< Compare Count Value Low, offset: 0x20 */ __IO uint32_t CMPCVH0; /**< Compare Count Value High, offset: 0x24 */ uint8_t RESERVED_1[4]; __IO uint32_t CMPCR0; /**< Compare Control, offset: 0x2C */ uint8_t RESERVED_2[240]; __IO uint32_t CMPCVL1; /**< Compare Count Value Low, offset: 0x120 */ __IO uint32_t CMPCVH1; /**< Compare Count Value High, offset: 0x124 */ uint8_t RESERVED_3[4]; __IO uint32_t CMPCR1; /**< Compare Control, offset: 0x12C */ uint8_t RESERVED_4[3744]; __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ } SYS_CTR_COMPARE_Type; /* ---------------------------------------------------------------------------- -- SYS_CTR_COMPARE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SYS_CTR_COMPARE_Register_Masks SYS_CTR_COMPARE Register Masks * @{ */ /*! @name CMPCVL0 - Compare Count Value Low */ /*! @{ */ #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK (0xFFFFFFFFU) #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT (0U) /*! CMPCV0 - Compare Count Value Bits [31:0] */ #define SYS_CTR_COMPARE_CMPCVL0_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK) /*! @} */ /*! @name CMPCVH0 - Compare Count Value High */ /*! @{ */ #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK (0xFFFFFFU) #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT (0U) /*! CMPCV1 - Compare Count Value Bits [55:32] */ #define SYS_CTR_COMPARE_CMPCVH0_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK) /*! @} */ /*! @name CMPCR0 - Compare Control */ /*! @{ */ #define SYS_CTR_COMPARE_CMPCR0_EN_MASK (0x1U) #define SYS_CTR_COMPARE_CMPCR0_EN_SHIFT (0U) /*! EN - Compare Enable * 0b0..Disable * 0b1..Enable */ #define SYS_CTR_COMPARE_CMPCR0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_EN_MASK) #define SYS_CTR_COMPARE_CMPCR0_IMASK_MASK (0x2U) #define SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT (1U) /*! IMASK - Interrupt Request Mask * 0b0..Not masked * 0b1..Masked */ #define SYS_CTR_COMPARE_CMPCR0_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_IMASK_MASK) #define SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK (0x4U) #define SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT (2U) /*! ISTAT - Compare Interrupt Status * 0b0..Either less than the compare value or compare is disabled * 0b1..Greater than or equal to the compare value and compare is enabled */ #define SYS_CTR_COMPARE_CMPCR0_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK) /*! @} */ /*! @name CMPCVL1 - Compare Count Value Low */ /*! @{ */ #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK (0xFFFFFFFFU) #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT (0U) /*! CMPCV0 - Compare Count Value Bits [31:0] */ #define SYS_CTR_COMPARE_CMPCVL1_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK) /*! @} */ /*! @name CMPCVH1 - Compare Count Value High */ /*! @{ */ #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK (0xFFFFFFU) #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT (0U) /*! CMPCV1 - Compare Count Value Bits [55:32] */ #define SYS_CTR_COMPARE_CMPCVH1_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK) /*! @} */ /*! @name CMPCR1 - Compare Control */ /*! @{ */ #define SYS_CTR_COMPARE_CMPCR1_EN_MASK (0x1U) #define SYS_CTR_COMPARE_CMPCR1_EN_SHIFT (0U) /*! EN - Compare Enable * 0b0..Disable * 0b1..Enable */ #define SYS_CTR_COMPARE_CMPCR1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_EN_MASK) #define SYS_CTR_COMPARE_CMPCR1_IMASK_MASK (0x2U) #define SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT (1U) /*! IMASK - Interrupt Request Mask * 0b0..Not masked * 0b1..Masked */ #define SYS_CTR_COMPARE_CMPCR1_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_IMASK_MASK) #define SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK (0x4U) #define SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT (2U) /*! ISTAT - Compare Interrupt Status * 0b0..Either less than the compare value or compare is disabled * 0b1..Greater than or equal to the compare value and compare is enabled */ #define SYS_CTR_COMPARE_CMPCR1_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR1_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR1_ISTAT_MASK) /*! @} */ /*! @name CNTID0 - Counter ID */ /*! @{ */ #define SYS_CTR_COMPARE_CNTID0_CNTID_MASK (0xFFFFFFFFU) #define SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT (0U) /*! CNTID - Counter Identification */ #define SYS_CTR_COMPARE_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT)) & SYS_CTR_COMPARE_CNTID0_CNTID_MASK) /*! @} */ /*! * @} */ /* end of group SYS_CTR_COMPARE_Register_Masks */ /* SYS_CTR_COMPARE - Peripheral instance base addresses */ /** Peripheral AON__SYS_CTR1__SYS_CTR_COMPARE base address */ #define AON__SYS_CTR1__SYS_CTR_COMPARE_BASE (0x442A0000u) /** Peripheral AON__SYS_CTR1__SYS_CTR_COMPARE base pointer */ #define AON__SYS_CTR1__SYS_CTR_COMPARE ((SYS_CTR_COMPARE_Type *)AON__SYS_CTR1__SYS_CTR_COMPARE_BASE) /** Array initializer of SYS_CTR_COMPARE peripheral base addresses */ #define SYS_CTR_COMPARE_BASE_ADDRS { AON__SYS_CTR1__SYS_CTR_COMPARE_BASE } /** Array initializer of SYS_CTR_COMPARE peripheral base pointers */ #define SYS_CTR_COMPARE_BASE_PTRS { AON__SYS_CTR1__SYS_CTR_COMPARE } /*! * @} */ /* end of group SYS_CTR_COMPARE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SYS_CTR_CONTROL Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SYS_CTR_CONTROL_Peripheral_Access_Layer SYS_CTR_CONTROL Peripheral Access Layer * @{ */ /** SYS_CTR_CONTROL - Register Layout Typedef */ typedef struct { __IO uint32_t CNTCR; /**< Counter Control, offset: 0x0 */ __I uint32_t CNTSR; /**< Counter Status, offset: 0x4 */ __IO uint32_t CNTCV0; /**< Counter Count Value Low, offset: 0x8 */ __IO uint32_t CNTCV1; /**< Counter Count Value High, offset: 0xC */ uint8_t RESERVED_0[16]; __I uint32_t CNTFID0; /**< Frequency-Modes Table 0, offset: 0x20 */ __I uint32_t CNTFID1; /**< Frequency-Modes Table 1, offset: 0x24 */ __I uint32_t CNTFID2; /**< Frequency-Modes Table 2, offset: 0x28 */ uint8_t RESERVED_1[4004]; __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ } SYS_CTR_CONTROL_Type; /* ---------------------------------------------------------------------------- -- SYS_CTR_CONTROL Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SYS_CTR_CONTROL_Register_Masks SYS_CTR_CONTROL Register Masks * @{ */ /*! @name CNTCR - Counter Control */ /*! @{ */ #define SYS_CTR_CONTROL_CNTCR_EN_MASK (0x1U) #define SYS_CTR_CONTROL_CNTCR_EN_SHIFT (0U) /*! EN - Enable Counting * 0b0..Disable * 0b1..Enable */ #define SYS_CTR_CONTROL_CNTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR_EN_MASK) #define SYS_CTR_CONTROL_CNTCR_HDBG_MASK (0x2U) #define SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT (1U) /*! HDBG - Enable Debug Halt * 0b0..Ignored * 0b1..Causes SYS_CTR to halt */ #define SYS_CTR_CONTROL_CNTCR_HDBG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT)) & SYS_CTR_CONTROL_CNTCR_HDBG_MASK) #define SYS_CTR_CONTROL_CNTCR_FCR0_MASK (0x100U) #define SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT (8U) /*! FCR0 - Frequency Change Request, ID 0 * 0b0..No change * 0b1..Base frequency */ #define SYS_CTR_CONTROL_CNTCR_FCR0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR0_MASK) #define SYS_CTR_CONTROL_CNTCR_FCR1_MASK (0x200U) #define SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT (9U) /*! FCR1 - Frequency Change Request, ID 1 * 0b0..No change * 0b1..Alternate frequency */ #define SYS_CTR_CONTROL_CNTCR_FCR1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR1_MASK) /*! @} */ /*! @name CNTSR - Counter Status */ /*! @{ */ #define SYS_CTR_CONTROL_CNTSR_DBGH_MASK (0x1U) #define SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT (0U) /*! DBGH - Debug Halt * 0b0..Did not halt * 0b1..Halted */ #define SYS_CTR_CONTROL_CNTSR_DBGH(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT)) & SYS_CTR_CONTROL_CNTSR_DBGH_MASK) #define SYS_CTR_CONTROL_CNTSR_FCA0_MASK (0x100U) #define SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT (8U) /*! FCA0 - Frequency Change Acknowledge, ID 0 * 0b0..Not selected * 0b1..Selected */ #define SYS_CTR_CONTROL_CNTSR_FCA0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA0_MASK) #define SYS_CTR_CONTROL_CNTSR_FCA1_MASK (0x200U) #define SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT (9U) /*! FCA1 - Frequency Change Acknowledge, ID 1 * 0b0..Not selected * 0b1..Selected */ #define SYS_CTR_CONTROL_CNTSR_FCA1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA1_MASK) /*! @} */ /*! @name CNTCV0 - Counter Count Value Low */ /*! @{ */ #define SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU) #define SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT (0U) /*! CNTCV0 - Counter Count Value Bits [31:0] */ #define SYS_CTR_CONTROL_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK) /*! @} */ /*! @name CNTCV1 - Counter Count Value High */ /*! @{ */ #define SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK (0xFFFFFFU) #define SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT (0U) /*! CNTCV1 - Counter Count Value Bits [55:32] */ #define SYS_CTR_CONTROL_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK) /*! @} */ /*! @name CNTFID0 - Frequency-Modes Table 0 */ /*! @{ */ #define SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK (0xFFFFFFFFU) #define SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT (0U) /*! CNTFID0 - Counter Frequency ID 0 */ #define SYS_CTR_CONTROL_CNTFID0_CNTFID0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT)) & SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK) /*! @} */ /*! @name CNTFID1 - Frequency-Modes Table 1 */ /*! @{ */ #define SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK (0xFFFFFFFFU) #define SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT (0U) /*! CNTFID1 - Counter Frequency ID 1 */ #define SYS_CTR_CONTROL_CNTFID1_CNTFID1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT)) & SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK) /*! @} */ /*! @name CNTFID2 - Frequency-Modes Table 2 */ /*! @{ */ #define SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK (0xFFFFFFFFU) #define SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT (0U) /*! CNTFID2 - Counter Frequency ID 2 */ #define SYS_CTR_CONTROL_CNTFID2_CNTFID2(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT)) & SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK) /*! @} */ /*! @name CNTID0 - Counter ID */ /*! @{ */ #define SYS_CTR_CONTROL_CNTID0_CNTID_MASK (0xFFFFFFFFU) #define SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT (0U) /*! CNTID - Counter Identification */ #define SYS_CTR_CONTROL_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT)) & SYS_CTR_CONTROL_CNTID0_CNTID_MASK) /*! @} */ /*! * @} */ /* end of group SYS_CTR_CONTROL_Register_Masks */ /* SYS_CTR_CONTROL - Peripheral instance base addresses */ /** Peripheral AON__SYS_CTR1__SYS_CTR_CONTROL base address */ #define AON__SYS_CTR1__SYS_CTR_CONTROL_BASE (0x44290000u) /** Peripheral AON__SYS_CTR1__SYS_CTR_CONTROL base pointer */ #define AON__SYS_CTR1__SYS_CTR_CONTROL ((SYS_CTR_CONTROL_Type *)AON__SYS_CTR1__SYS_CTR_CONTROL_BASE) /** Array initializer of SYS_CTR_CONTROL peripheral base addresses */ #define SYS_CTR_CONTROL_BASE_ADDRS { AON__SYS_CTR1__SYS_CTR_CONTROL_BASE } /** Array initializer of SYS_CTR_CONTROL peripheral base pointers */ #define SYS_CTR_CONTROL_BASE_PTRS { AON__SYS_CTR1__SYS_CTR_CONTROL } /*! * @} */ /* end of group SYS_CTR_CONTROL_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SYS_CTR_READ Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SYS_CTR_READ_Peripheral_Access_Layer SYS_CTR_READ Peripheral Access Layer * @{ */ /** SYS_CTR_READ - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __I uint32_t CNTCV0; /**< Counter Count Value Low, offset: 0x8 */ __I uint32_t CNTCV1; /**< Counter Count Value High, offset: 0xC */ uint8_t RESERVED_1[4032]; __I uint32_t CNTID0; /**< Counter ID, offset: 0xFD0 */ } SYS_CTR_READ_Type; /* ---------------------------------------------------------------------------- -- SYS_CTR_READ Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SYS_CTR_READ_Register_Masks SYS_CTR_READ Register Masks * @{ */ /*! @name CNTCV0 - Counter Count Value Low */ /*! @{ */ #define SYS_CTR_READ_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU) #define SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT (0U) /*! CNTCV0 - Counter Count Value Bits [31:0] */ #define SYS_CTR_READ_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_READ_CNTCV0_CNTCV0_MASK) /*! @} */ /*! @name CNTCV1 - Counter Count Value High */ /*! @{ */ #define SYS_CTR_READ_CNTCV1_CNTCV1_MASK (0xFFFFFFU) #define SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT (0U) /*! CNTCV1 - Counter Count Value Bits [55:32] */ #define SYS_CTR_READ_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_READ_CNTCV1_CNTCV1_MASK) /*! @} */ /*! @name CNTID0 - Counter ID */ /*! @{ */ #define SYS_CTR_READ_CNTID0_CNTID_MASK (0xFFFFFFFFU) #define SYS_CTR_READ_CNTID0_CNTID_SHIFT (0U) /*! CNTID - Counter Identification */ #define SYS_CTR_READ_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTID0_CNTID_SHIFT)) & SYS_CTR_READ_CNTID0_CNTID_MASK) /*! @} */ /*! * @} */ /* end of group SYS_CTR_READ_Register_Masks */ /* SYS_CTR_READ - Peripheral instance base addresses */ /** Peripheral AON__SYS_CTR1__SYS_CTR_READ base address */ #define AON__SYS_CTR1__SYS_CTR_READ_BASE (0x442B0000u) /** Peripheral AON__SYS_CTR1__SYS_CTR_READ base pointer */ #define AON__SYS_CTR1__SYS_CTR_READ ((SYS_CTR_READ_Type *)AON__SYS_CTR1__SYS_CTR_READ_BASE) /** Array initializer of SYS_CTR_READ peripheral base addresses */ #define SYS_CTR_READ_BASE_ADDRS { AON__SYS_CTR1__SYS_CTR_READ_BASE } /** Array initializer of SYS_CTR_READ peripheral base pointers */ #define SYS_CTR_READ_BASE_PTRS { AON__SYS_CTR1__SYS_CTR_READ } /*! * @} */ /* end of group SYS_CTR_READ_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SerDes_SS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SerDes_SS_Peripheral_Access_Layer SerDes_SS Peripheral Access Layer * @{ */ /** SerDes_SS - Register Layout Typedef */ typedef struct { __IO uint32_t PCIE_PHY_GEN_CTRL; /**< PCIe PHY General Control, offset: 0x0 */ __IO uint32_t PCIE_PHY_LPBK_CTRL; /**< PCIe PHY Loopback Control, offset: 0x4 */ __IO uint32_t PCIE_PHY_SRAM_CSR; /**< PCIe PHY SRAM Control And Status, offset: 0x8 */ __IO uint32_t PCIE_PHY_PM_CTRL; /**< PCIe PHY power management control, offset: 0xC */ __IO uint32_t PCIE_PHY_MPLLA_CTRL; /**< PCIe PHY MPLLA Control, offset: 0x10 */ __IO uint32_t PCIE_PHY_MPLLB_CTRL; /**< PCIe PHY MPLLB Control, offset: 0x14 */ __IO uint32_t PCIE_PHY_EXT_CTRL_SEL; /**< PCIe PHY Setting External Control, offset: 0x18 */ __IO uint32_t PCIE_PHY_EXT_BS_CTRL; /**< PCIe PHY Boundary Scan Control, offset: 0x1C */ __IO uint32_t PCIE_PHY_REF_CLK_CTRL; /**< PCIe Reference Clock Control, offset: 0x20 */ uint8_t RESERVED_0[12]; __IO uint32_t PCIE_PHY_EXT_MPLLA_CTRL_1; /**< PCIe PHY MPLLA Control 1, offset: 0x30 */ __IO uint32_t PCIE_PHY_EXT_MPLLA_CTRL_2; /**< PCIe PHY MPLLA Control 2, offset: 0x34 */ __IO uint32_t PCIE_PHY_EXT_MPLLA_CTRL_3; /**< PCIe PHY MPLLA Control 3, offset: 0x38 */ uint8_t RESERVED_1[4]; __IO uint32_t PCIE_PHY_EXT_MPLLB_CTRL_1; /**< PCIe PHY MPLLB Control 1, offset: 0x40 */ __IO uint32_t PCIE_PHY_EXT_MPLLB_CTRL_2; /**< PCIe PHY MPLLB Control 2, offset: 0x44 */ __IO uint32_t PCIE_PHY_EXT_MPLLB_CTRL_3; /**< PCIe PHY MPLLB Control 3, offset: 0x48 */ uint8_t RESERVED_2[4]; __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_1A; /**< PCIe PHY RX Equalization Control 1 For Gen1 Speed, offset: 0x50 */ __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_1B; /**< PCIe PHY RX Equalization Control 2 For Gen1 Speed, offset: 0x54 */ __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_1C; /**< PCIe PHY RX Equalization Control 3 For Gen1 Speed, offset: 0x58 */ uint8_t RESERVED_3[4]; __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_2A; /**< PCIe PHY RX Equalization Control 1 For Gen2 Speed, offset: 0x60 */ __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_2B; /**< PCIe PHY RX Equalization Control 2 For Gen2 Speed, offset: 0x64 */ __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_2C; /**< PCIe PHY RX Equalization Control 3 For Gen2 Speed, offset: 0x68 */ uint8_t RESERVED_4[4]; __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_3A; /**< PCIe PHY RX Equalization Control 1 For Gen3 Speed, offset: 0x70 */ __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_3B; /**< PCIe PHY RX Equalization Control 2 For Gen3 Speed, offset: 0x74 */ __IO uint32_t PCIE_PHY_EXT_RX_EQ_CTRL_3C; /**< PCIe PHY RX Equalization Control 3 For Gen3 Speed, offset: 0x78 */ uint8_t RESERVED_5[20]; __IO uint32_t PCIE_PHY_EXT_CALI_CTRL_1; /**< PCIe PHY Calibration Control For Gen1 Speed, offset: 0x90 */ __IO uint32_t PCIE_PHY_EXT_CALI_CTRL_2; /**< PCIe PHY Calibration Control For Gen2 Speed, offset: 0x94 */ __IO uint32_t PCIE_PHY_EXT_CALI_CTRL_3; /**< PCIe PHY Calibration Control For Gen3 Speed, offset: 0x98 */ uint8_t RESERVED_6[4]; __IO uint32_t PCIE_PHY_EXT_MISC_CTRL_1; /**< PCIe PHY Miscellaneous Control 1, offset: 0xA0 */ __IO uint32_t PCIE_PHY_EXT_MISC_CTRL_2; /**< PCIe PHY Miscellaneous Control 2, offset: 0xA4 */ uint8_t RESERVED_7[8]; __IO uint32_t PCIE_PHY_EXT_TX_EQ_CTRL_1; /**< PCIe PHY TX Equalization Control For Gen1 Speed, offset: 0xB0 */ __IO uint32_t PCIE_PHY_EXT_TX_EQ_CTRL_2; /**< PCIe PHY TX Equalization Control For Gen2 Speed, offset: 0xB4 */ __IO uint32_t PCIE_PHY_EXT_TX_EQ_CTRL_3; /**< PCIe PHY TX Equalization Control For Gen3 Speed, offset: 0xB8 */ uint8_t RESERVED_8[36]; __I uint32_t SS_RO_REG_0; /**< Subsystem Read-Only Register 0, offset: 0xE0 */ __I uint32_t SS_RO_REG_1; /**< Subsystem Read-Only Register 1, offset: 0xE4 */ __I uint32_t SS_RO_REG_2; /**< Subsystem Read-Only Register 2, offset: 0xE8 */ __I uint32_t SS_RO_REG_3; /**< Subsystem Read-Only Register 3, offset: 0xEC */ __IO uint32_t SS_RW_REG_0; /**< Subsystem Read/Write Register 0, offset: 0xF0 */ __IO uint32_t SS_RW_REG_1; /**< Subsystem Read/Write Register 1, offset: 0xF4 */ __IO uint32_t SS_RW_REG_2; /**< Subsystem Read/Write Register 2, offset: 0xF8 */ __IO uint32_t SS_RW_REG_3; /**< Subsystem Read/Write Register 3, offset: 0xFC */ __IO uint32_t SS_RW_REG_4; /**< Subsystem Read/Write Register 4, offset: 0x100 */ __IO uint32_t SS_RW_REG_5; /**< Subsystem Read/Write Register 5, offset: 0x104 */ uint8_t RESERVED_9[3832]; __I uint32_t PCIE_SUBSYSTEM_VERSION; /**< PCIe Subsystem Version, offset: 0x1000 */ __IO uint32_t PE0_CLKREQ_CTRL; /**< PCIe Controller Clock Request Override, offset: 0x1004 */ __IO uint32_t PE0_LUT_ACSCTRL; /**< LUT access Control, offset: 0x1008 */ __IO uint32_t PE0_LUT_DATA1; /**< LUT Data1 register, offset: 0x100C */ __IO uint32_t PE0_LUT_DATA2; /**< LUT Data2 register, offset: 0x1010 */ __IO uint32_t PE0_LUT_INT_STS; /**< LUT Interrupt Status, offset: 0x1014 */ __IO uint32_t PE0_LUT_INT_CTRL; /**< LUT Interrupt Control, offset: 0x1018 */ __I uint32_t PE0_LUT_CREQID; /**< LUT Request ID Register, offset: 0x101C */ __IO uint32_t FLR_CTRL_STS; /**< Function Level Reset (FLR) Control and Status Register, offset: 0x1020 */ uint8_t RESERVED_10[28]; __IO uint32_t LINK_INT_CTRL_STS; /**< Link Interrupt Control And Status, offset: 0x1040 */ uint8_t RESERVED_11[12]; __IO uint32_t PE0_GEN_CTRL_1; /**< PCIe Controller 0 General Control 1, offset: 0x1050 */ __IO uint32_t PE0_GEN_CTRL_2; /**< PCIe Controller 0 General Control 2, offset: 0x1054 */ __IO uint32_t PE0_GEN_CTRL_3; /**< PCIe Controller 0 General Control 3, offset: 0x1058 */ __IO uint32_t PE0_GEN_CTRL_4; /**< PCIe Controller 0 General Control 4, offset: 0x105C */ __IO uint32_t PE0_PM_CTRL; /**< PCIe Controller 0 PM Control, offset: 0x1060 */ __I uint32_t PE0_PM_STS; /**< PCIe Controller 0 PM Status, offset: 0x1064 */ __IO uint32_t PE0_TX_LTR_MSG_LATENCY; /**< PCIe Controller LTR message latency, offset: 0x1068 */ __IO uint32_t PE0_TX_LTR_MSG_FUNC_NUM; /**< Function number that is requesting to send an LTR message., offset: 0x106C */ __IO uint32_t PE0_TX_MSG_HDR_1; /**< PCIe Controller 0 Transmit Message Header 1, offset: 0x1070 */ __IO uint32_t PE0_TX_MSG_HDR_2; /**< PCIe Controller 0 Transmit Message Header 2, offset: 0x1074 */ __IO uint32_t PE0_TX_MSG_HDR_3; /**< PCIe Controller 0 Transmit Message Header 3, offset: 0x1078 */ __IO uint32_t PE0_TX_MSG_HDR_4; /**< PCIe controller 0 transmit message header 4, offset: 0x107C */ __IO uint32_t PE0_TX_MSG_REQ; /**< PCIe Controller 0 Transmit Message Request, offset: 0x1080 */ __I uint32_t PE0_RX_SLOT_PWR_PAYLD; /**< DW data of Set_Slot_Power_Limit message, offset: 0x1084 */ __I uint32_t PE0_RX_CURR_LTR_LATENCY; /**< Current LTR values, offset: 0x1088 */ uint8_t RESERVED_12[4]; __I uint32_t PE0_RX_MSG_HDR_1; /**< PCIe Controller 0 Receive Message Header 1, offset: 0x1090 */ __I uint32_t PE0_RX_MSG_HDR_2; /**< PCIe Controller 0 Receive Message Header 2, offset: 0x1094 */ __I uint32_t PE0_RX_MSG_HDR_3; /**< PCIe Controller 0 Receive Message Header 3, offset: 0x1098 */ __I uint32_t PE0_RX_MSG_HDR_4; /**< PCIe Controller 0 Receive Message Header 4, offset: 0x109C */ __IO uint32_t PE0_RX_MSG_STS; /**< PCIe Controller 0 Receive Message Status, offset: 0x10A0 */ __IO uint32_t PE0_RX_MSG_CAP_CTRL; /**< PCIe Controller 0 Receive Message Capture Control, offset: 0x10A4 */ __IO uint32_t PE0_RX_MSG_INT_CTRL; /**< PCIe Controller 0 Receive Message Interrupt Control, offset: 0x10A8 */ uint8_t RESERVED_13[4]; __I uint32_t PE0_LINK_DBG_1; /**< PCIe Controller 0 Link Debug 1, offset: 0x10B0 */ __I uint32_t PE0_LINK_DBG_2; /**< PCIe Controller 0 Link Debug 2, offset: 0x10B4 */ uint8_t RESERVED_14[8]; __I uint32_t PE0_AXI_MSTR_DBG_1; /**< PCIe Controller 0 AXI Master Debug 1, offset: 0x10C0 */ __I uint32_t PE0_AXI_MSTR_DBG_2; /**< PCIe Controller 0 AXI Master Debug 2, offset: 0x10C4 */ uint8_t RESERVED_15[8]; __I uint32_t PE0_AXI_SLV_DBG_1; /**< PCIe Controller 0 AXI Slave Debug 1, offset: 0x10D0 */ __I uint32_t PE0_AXI_SLV_DBG_2; /**< PCIe Controller 0 AXI Slave Debug 2, offset: 0x10D4 */ uint8_t RESERVED_16[8]; __IO uint32_t PE0_ERR_STS; /**< PCIe Controller 0 Error Status, offset: 0x10E0 */ __IO uint32_t PE0_ERR_INT_CTRL; /**< PCIe Controller 0 Error Interrupt Control, offset: 0x10E4 */ __IO uint32_t PE0_INT_STS; /**< PCIe Controller 0 Interrupt Status, offset: 0x10E8 */ __IO uint32_t PE0_MSI_GEN_CTRL; /**< PCIe Controller 0 MSI Generation Control, offset: 0x10EC */ __IO uint32_t PE0_FSM_TRACK_1; /**< PCIe Controller 0 FSM Track 1, offset: 0x10F0 */ __I uint32_t PE0_FSM_TRACK_2; /**< PCIe Controller 0 FSM Track 2, offset: 0x10F4 */ uint8_t RESERVED_17[7944]; __IO uint32_t APB_BRIDGE_TO_CTRL; /**< APB Bridge Timeout Control, offset: 0x3000 */ uint8_t RESERVED_18[4]; __IO uint32_t PHY_REG_ADDR; /**< PHY Register Address, offset: 0x3008 */ __IO uint32_t PHY_REG_DATA; /**< PHY Register Data, offset: 0x300C */ __IO uint32_t RST_CTRL; /**< Reset Control, offset: 0x3010 */ } SerDes_SS_Type; /* ---------------------------------------------------------------------------- -- SerDes_SS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SerDes_SS_Register_Masks SerDes_SS Register Masks * @{ */ /*! @name PCIE_PHY_GEN_CTRL - PCIe PHY General Control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_EXT_PCLK_REQ_MASK (0x1U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_EXT_PCLK_REQ_SHIFT (0U) /*! EXT_PCLK_REQ - pipeP_pclk Required By External Logic * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_EXT_PCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_EXT_PCLK_REQ_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_EXT_PCLK_REQ_MASK) #define SerDes_SS_PCIE_PHY_GEN_CTRL_CR_PARA_CLK_DIV2_EN_MASK (0x4U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_CR_PARA_CLK_DIV2_EN_SHIFT (2U) /*! CR_PARA_CLK_DIV2_EN - CR Parallel Clock Divider Control * 0b0..Same as PHY ref_dig_fr_clk * 0b1..Half of ref_dig_fr_clk */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_CR_PARA_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_CR_PARA_CLK_DIV2_EN_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_CR_PARA_CLK_DIV2_EN_MASK) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX_SRIS_MODE_MASK (0x200U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX_SRIS_MODE_SHIFT (9U) /*! RX_SRIS_MODE - SRIS Enable, As Defined In PCIe ECN * 0b0..Disables * 0b1..Enables */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX_SRIS_MODE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_RX_SRIS_MODE_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_RX_SRIS_MODE_MASK) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_TERM_ACDC_MASK (0x400U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_TERM_ACDC_SHIFT (10U) /*! RX0_TERM_ACDC - Receiver Termination Control For Rx0 * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_TERM_ACDC(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_TERM_ACDC_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_TERM_ACDC_MASK) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_125MHZ_CLK_EN_MASK (0x4000U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_125MHZ_CLK_EN_SHIFT (14U) /*! RX0_125MHZ_CLK_EN - Enable signal for 125MHz clock * 0b0..Disabled * 0b1..Enabled */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_125MHZ_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_125MHZ_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_125MHZ_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_DIV16P5_CLK_EN_MASK (0x8000U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_DIV16P5_CLK_EN_SHIFT (15U) /*! RX0_DIV16P5_CLK_EN - Enable signal for div 16.5 clock * 0b0..Disabled * 0b1..Enabled */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_DIV16P5_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_DIV16P5_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_RX0_DIV16P5_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_GEN_CTRL_REF_REPEAT_CLK_EN_MASK (0x10000U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_REF_REPEAT_CLK_EN_SHIFT (16U) /*! REF_REPEAT_CLK_EN - Repeat Reference Clock Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_REF_REPEAT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_REF_REPEAT_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_REF_REPEAT_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_GEN_CTRL_REF_USE_PAD_MASK (0x20000U) #define SerDes_SS_PCIE_PHY_GEN_CTRL_REF_USE_PAD_SHIFT (17U) /*! REF_USE_PAD - Reference Is From External Pad * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_GEN_CTRL_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_GEN_CTRL_REF_USE_PAD_SHIFT)) & SerDes_SS_PCIE_PHY_GEN_CTRL_REF_USE_PAD_MASK) /*! @} */ /*! @name PCIE_PHY_LPBK_CTRL - PCIe PHY Loopback Control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_TX2RX_LOOPBK_MASK (0x1U) #define SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_TX2RX_LOOPBK_SHIFT (0U) /*! LANE0_TX2RX_LOOPBK - Lane0 Analog Serial Loopback Control * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_TX2RX_LOOPBK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_TX2RX_LOOPBK_SHIFT)) & SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_TX2RX_LOOPBK_MASK) #define SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_RX2TX_PAR_LB_EN_MASK (0x2U) #define SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_RX2TX_PAR_LB_EN_SHIFT (1U) /*! LANE0_RX2TX_PAR_LB_EN - Lane0 Parallel (RX to TX) Loopback Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_RX2TX_PAR_LB_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_RX2TX_PAR_LB_EN_SHIFT)) & SerDes_SS_PCIE_PHY_LPBK_CTRL_LANE0_RX2TX_PAR_LB_EN_MASK) /*! @} */ /*! @name PCIE_PHY_SRAM_CSR - PCIe PHY SRAM Control And Status */ /*! @{ */ #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_BYPASS_MASK (0x1U) #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_BYPASS_SHIFT (0U) /*! SRAM_BYPASS - SRAM Bypass * 0b0..Disables SRAM Bypass * 0b1..Enables SRAM Bypass */ #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_BYPASS_SHIFT)) & SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_BYPASS_MASK) #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_EXT_LD_DONE_MASK (0x2U) #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_EXT_LD_DONE_SHIFT (1U) /*! SRAM_EXT_LD_DONE - SRAM External Load Done * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_EXT_LD_DONE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_EXT_LD_DONE_SHIFT)) & SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_EXT_LD_DONE_MASK) #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_INIT_DONE_MASK (0x4U) #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_INIT_DONE_SHIFT (2U) /*! SRAM_INIT_DONE - SRAM Initialization Done * 0b0..0 * 0b1..1 */ #define SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_INIT_DONE_SHIFT)) & SerDes_SS_PCIE_PHY_SRAM_CSR_SRAM_INIT_DONE_MASK) #define SerDes_SS_PCIE_PHY_SRAM_CSR_TX_ACK_MASK (0x10U) #define SerDes_SS_PCIE_PHY_SRAM_CSR_TX_ACK_SHIFT (4U) /*! TX_ACK - Transmitter acknowledge * 0b0..Request not completed * 0b1..Request completed */ #define SerDes_SS_PCIE_PHY_SRAM_CSR_TX_ACK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_SRAM_CSR_TX_ACK_SHIFT)) & SerDes_SS_PCIE_PHY_SRAM_CSR_TX_ACK_MASK) #define SerDes_SS_PCIE_PHY_SRAM_CSR_RX_ACK_MASK (0x40U) #define SerDes_SS_PCIE_PHY_SRAM_CSR_RX_ACK_SHIFT (6U) /*! RX_ACK - Receiver acknowledge * 0b0..Request not completed * 0b1..Request completed */ #define SerDes_SS_PCIE_PHY_SRAM_CSR_RX_ACK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_SRAM_CSR_RX_ACK_SHIFT)) & SerDes_SS_PCIE_PHY_SRAM_CSR_RX_ACK_MASK) /*! @} */ /*! @name PCIE_PHY_PM_CTRL - PCIe PHY power management control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_MASK (0x1U) #define SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_SHIFT (0U) /*! TX0_BEACON_EN - Transmitter beaconing/LFPS (low frequency period signaling) enable. */ #define SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_SHIFT)) & SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_MASK) #define SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_OVRD_MASK (0x10U) #define SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_OVRD_SHIFT (4U) /*! TX0_BEACON_EN_OVRD - TX0_BEACON override enable */ #define SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_OVRD_SHIFT)) & SerDes_SS_PCIE_PHY_PM_CTRL_TX0_BEACON_EN_OVRD_MASK) /*! @} */ /*! @name PCIE_PHY_MPLLA_CTRL - PCIe PHY MPLLA Control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_FORCE_EN_MASK (0x1U) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_FORCE_EN_SHIFT (0U) /*! MPLLA_FORCE_EN - MPLLA Force Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_FORCE_EN_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_FORCE_EN_MASK) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_MASK (0x10U) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_SHIFT (4U) /*! MPLLA_INIT_CAL_DISABLE - MPLLA calibration disable control * 0b0..Enabled MPLLA calibration * 0b1..Disabled MPLLA calibration */ #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_MASK) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_OVRD_MASK (0x20U) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_OVRD_SHIFT (5U) /*! MPLLA_INIT_CAL_DISABLE_OVRD - MPLLA calibration disable override * 0b0..Calibration Disable override disabled * 0b1..Calibration disable override enabled */ #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_OVRD_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_INIT_CAL_DISABLE_OVRD_MASK) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLL_STATE_MASK (0x40000000U) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLL_STATE_SHIFT (30U) /*! MPLL_STATE - MPLLA or MPLLB State Indicator * 0b0..phy0_mplla_state and phy0_mpllb_state are 0 * 0b1..phy0_mplla_state or phy0_mpllb_state is 1 */ #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLL_STATE_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLL_STATE_MASK) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_STATE_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_STATE_SHIFT (31U) /*! MPLLA_STATE - MPLLA State Indicator * 0b0..PLL is not locked * 0b1..PLL is locked */ #define SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_STATE_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLA_CTRL_MPLLA_STATE_MASK) /*! @} */ /*! @name PCIE_PHY_MPLLB_CTRL - PCIe PHY MPLLB Control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_FORCE_EN_MASK (0x1U) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_FORCE_EN_SHIFT (0U) /*! MPLLB_FORCE_EN - MPLLB Force Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_FORCE_EN_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_FORCE_EN_MASK) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_MASK (0x10U) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_SHIFT (4U) /*! MPLLB_INIT_CAL_DISABLE - MPLLB calibration disable control * 0b0..Enabled MPLLB calibration * 0b1..Disabled MPLLB calibration */ #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_MASK) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_OVRD_MASK (0x20U) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_OVRD_SHIFT (5U) /*! MPLLB_INIT_CAL_DISABLE_OVRD - MPLLB calibration disable override * 0b0..Calibration Disable override disabled * 0b1..Calibration disable override enabled */ #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_OVRD_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_INIT_CAL_DISABLE_OVRD_MASK) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLL_STATE_MASK (0x40000000U) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLL_STATE_SHIFT (30U) /*! MPLL_STATE - MPLLA or MPLLB State Indicator * 0b0..phy0_mplla_state and phy0_mpllb_state are 0 * 0b1..phy0_mplla_state or phy0_mpllb_state is 1 */ #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLL_STATE_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLL_STATE_MASK) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_STATE_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_STATE_SHIFT (31U) /*! MPLLB_STATE - MPLLB State Indicator * 0b0..0 * 0b1..1 */ #define SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_STATE_SHIFT)) & SerDes_SS_PCIE_PHY_MPLLB_CTRL_MPLLB_STATE_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_CTRL_SEL - PCIe PHY Setting External Control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_CTRL_SEL_EXT_PHY_CTRL_SEL_MASK (0x1U) #define SerDes_SS_PCIE_PHY_EXT_CTRL_SEL_EXT_PHY_CTRL_SEL_SHIFT (0U) /*! EXT_PHY_CTRL_SEL - External Control Of PHY Setting * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_CTRL_SEL_EXT_PHY_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CTRL_SEL_EXT_PHY_CTRL_SEL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CTRL_SEL_EXT_PHY_CTRL_SEL_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_BS_CTRL - PCIe PHY Boundary Scan Control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_LEVEL_MASK (0x1FU) #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_LEVEL_SHIFT (0U) /*! EXT_BS_RX_LEVEL - ACJTAG Receiver Sensitivity Level Control */ #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_LEVEL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_LEVEL_MASK) #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_BIGSWING_MASK (0x20U) #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_BIGSWING_SHIFT (5U) /*! EXT_BS_RX_BIGSWING - RX Boundary Scan Big Swing * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_BIGSWING(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_BIGSWING_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_RX_BIGSWING_MASK) #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_TX_LOWSWING_MASK (0x40U) #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_TX_LOWSWING_SHIFT (6U) /*! EXT_BS_TX_LOWSWING - TX Boundary Scan Low Swing * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_TX_LOWSWING(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_TX_LOWSWING_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_BS_CTRL_EXT_BS_TX_LOWSWING_MASK) /*! @} */ /*! @name PCIE_PHY_REF_CLK_CTRL - PCIe Reference Clock Control */ /*! @{ */ #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLA_DIV2_EN_MASK (0x1U) #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLA_DIV2_EN_SHIFT (0U) /*! REF_CLK_MPLLA_DIV2_EN - MPLLA Reference Clock Divider Control * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLA_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLA_DIV2_EN_SHIFT)) & SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLA_DIV2_EN_MASK) #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLB_DIV2_EN_MASK (0x2U) #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLB_DIV2_EN_SHIFT (1U) /*! REF_CLK_MPLLB_DIV2_EN - MPLLB Reference Clock Divider Control * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLB_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLB_DIV2_EN_SHIFT)) & SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_MPLLB_DIV2_EN_MASK) #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_DIV2_EN_MASK (0x4U) #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_DIV2_EN_SHIFT (2U) /*! REF_CLK_DIV2_EN - Input Reference Clock Divider Control * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_DIV2_EN_SHIFT)) & SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_CLK_DIV2_EN_MASK) #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_RANGE_MASK (0x38U) #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_RANGE_SHIFT (3U) /*! REF_RANGE - Input Reference Clock frequency Range */ #define SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_RANGE_SHIFT)) & SerDes_SS_PCIE_PHY_REF_CLK_CTRL_REF_RANGE_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MPLLA_CTRL_1 - PCIe PHY MPLLA Control 1 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_BANDWIDTH_MASK (0xFFFFU) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_BANDWIDTH_SHIFT (0U) /*! EXT_MPLLA_BANDWIDTH - MPLLA Bandwidth Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_BANDWIDTH_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_BANDWIDTH_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV10_CLK_EN_MASK (0x10000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV10_CLK_EN_SHIFT (16U) /*! EXT_MPLLA_DIV10_CLK_EN - MPLLA Divide by 10 Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV10_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV10_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV10_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV16P5_CLK_EN_MASK (0x20000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV16P5_CLK_EN_SHIFT (17U) /*! EXT_MPLLA_DIV16P5_CLK_EN - MPLLA Divide by 16.5 Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV16P5_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV16P5_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV16P5_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV8_CLK_EN_MASK (0x40000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV8_CLK_EN_SHIFT (18U) /*! EXT_MPLLA_DIV8_CLK_EN - MPLLA Divide by 8 Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV8_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV8_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV8_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_CLK_EN_MASK (0x80000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_CLK_EN_SHIFT (19U) /*! EXT_MPLLA_DIV_CLK_EN - MPLLA Divide Clock Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_MULTIPLIER_MASK (0xFF000000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_MULTIPLIER_SHIFT (24U) /*! EXT_MPLLA_DIV_MULTIPLIER - MPLLA Output Frequency Multiplier Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_MULTIPLIER(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_MULTIPLIER_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_1_EXT_MPLLA_DIV_MULTIPLIER_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MPLLA_CTRL_2 - PCIe PHY MPLLA Control 2 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_MULTIPLIER_MASK (0xFFU) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_MULTIPLIER_SHIFT (0U) /*! EXT_MPLLA_MULTIPLIER - MPLLA Frequency Multiplier Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_MULTIPLIER(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_MULTIPLIER_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_MULTIPLIER_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_FRACN_CTRL_MASK (0x7FF000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_FRACN_CTRL_SHIFT (12U) /*! EXT_MPLLA_FRACN_CTRL - MPLLA Fractional Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_FRACN_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_FRACN_CTRL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_2_EXT_MPLLA_FRACN_CTRL_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MPLLA_CTRL_3 - PCIe PHY MPLLA Control 3 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_TX_CLK_DIV_MASK (0x70000000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_TX_CLK_DIV_SHIFT (28U) /*! EXT_MPLLA_TX_CLK_DIV - MPLLA Tx Clock Divide */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_TX_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_TX_CLK_DIV_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_TX_CLK_DIV_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_WORD_DIV2_EN_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_WORD_DIV2_EN_SHIFT (31U) /*! EXT_MPLLA_WORD_DIV2_EN - MPLLA Word Clock Divide by 2 * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_WORD_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_WORD_DIV2_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLA_CTRL_3_EXT_MPLLA_WORD_DIV2_EN_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MPLLB_CTRL_1 - PCIe PHY MPLLB Control 1 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_BANDWIDTH_MASK (0xFFFFU) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_BANDWIDTH_SHIFT (0U) /*! EXT_MPLLB_BANDWIDTH - MPLLB Bandwidth Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_BANDWIDTH(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_BANDWIDTH_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_BANDWIDTH_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV10_CLK_EN_MASK (0x10000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV10_CLK_EN_SHIFT (16U) /*! EXT_MPLLB_DIV10_CLK_EN - MPLLB Divide by 10 Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV10_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV10_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV10_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV8_CLK_EN_MASK (0x40000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV8_CLK_EN_SHIFT (18U) /*! EXT_MPLLB_DIV8_CLK_EN - MPLLB Divide by 8 Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV8_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV8_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV8_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_CLK_EN_MASK (0x80000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_CLK_EN_SHIFT (19U) /*! EXT_MPLLB_DIV_CLK_EN - MPLLB Divide Clock Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_CLK_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_CLK_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_MULTIPLIER_MASK (0xFF000000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_MULTIPLIER_SHIFT (24U) /*! EXT_MPLLB_DIV_MULTIPLIER - MPLLB Output Frequency Multiplier Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_MULTIPLIER(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_MULTIPLIER_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_1_EXT_MPLLB_DIV_MULTIPLIER_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MPLLB_CTRL_2 - PCIe PHY MPLLB Control 2 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_MULTIPLIER_MASK (0xFFU) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_MULTIPLIER_SHIFT (0U) /*! EXT_MPLLB_MULTIPLIER - MPLLB Frequency Multiplier Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_MULTIPLIER(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_MULTIPLIER_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_MULTIPLIER_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_FRACN_CTRL_MASK (0x7FF000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_FRACN_CTRL_SHIFT (12U) /*! EXT_MPLLB_FRACN_CTRL - MPLLB Fractional Control */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_FRACN_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_FRACN_CTRL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_2_EXT_MPLLB_FRACN_CTRL_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MPLLB_CTRL_3 - PCIe PHY MPLLB Control 3 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_TX_CLK_DIV_MASK (0x70000000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_TX_CLK_DIV_SHIFT (28U) /*! EXT_MPLLB_TX_CLK_DIV - MPLLB Tx Clock Divide */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_TX_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_TX_CLK_DIV_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_TX_CLK_DIV_MASK) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_WORD_DIV2_EN_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_WORD_DIV2_EN_SHIFT (31U) /*! EXT_MPLLB_WORD_DIV2_EN - MPLLB Word Clock Divide by 2 * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_WORD_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_WORD_DIV2_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MPLLB_CTRL_3_EXT_MPLLB_WORD_DIV2_EN_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_1A - PCIe PHY RX Equalization Control 1 For Gen1 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_AFE_EN_G1_MASK (0x1U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_AFE_EN_G1_SHIFT (0U) /*! EXT_RX_ADAPT_AFE_EN_G1 - RX Adaptation Enable */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_AFE_EN_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_AFE_EN_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_AFE_EN_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_DFE_EN_G1_MASK (0x4U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_DFE_EN_G1_SHIFT (2U) /*! EXT_RX_ADAPT_DFE_EN_G1 - RX DFE Enable */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_DFE_EN_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_DFE_EN_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_ADAPT_DFE_EN_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_ATT_LVL_G1_MASK (0x70U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_ATT_LVL_G1_SHIFT (4U) /*! EXT_RX_EQ_ATT_LVL_G1 - RX Equalization Attenuation Level */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_ATT_LVL_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_ATT_LVL_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_ATT_LVL_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_BOOST_G1_MASK (0x1F0000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_BOOST_G1_SHIFT (16U) /*! EXT_RX_EQ_CTLE_BOOST_G1 - RX Equalization CTLE Boost */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_BOOST_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_BOOST_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_BOOST_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_POLE_G1_MASK (0x1E000000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_POLE_G1_SHIFT (25U) /*! EXT_RX_EQ_CTLE_POLE_G1 - RX Equalization CTLE Pole */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_POLE_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_POLE_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1A_EXT_RX_EQ_CTLE_POLE_G1_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_1B - PCIe PHY RX Equalization Control 2 For Gen1 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_DFE_TAP1_G1_MASK (0xFFFFU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_DFE_TAP1_G1_SHIFT (0U) /*! EXT_RX_EQ_DFE_TAP1_G1 - RX Equalization DFE Tap1 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_DFE_TAP1_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_DFE_TAP1_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_DFE_TAP1_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA1_GAIN_G1_MASK (0xFF0000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA1_GAIN_G1_SHIFT (16U) /*! EXT_RX_EQ_VGA1_GAIN_G1 - RX Equalization VGA Gain 1 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA1_GAIN_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA1_GAIN_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA1_GAIN_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA2_GAIN_G1_MASK (0xFF000000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA2_GAIN_G1_SHIFT (24U) /*! EXT_RX_EQ_VGA2_GAIN_G1 - RX Equalization VGA Gain 2 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA2_GAIN_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA2_GAIN_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1B_EXT_RX_EQ_VGA2_GAIN_G1_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_1C - PCIe PHY RX Equalization Control 3 For Gen1 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1C_EXT_RX_EQ_DELTA_IQ_G1_MASK (0xFFU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1C_EXT_RX_EQ_DELTA_IQ_G1_SHIFT (0U) /*! EXT_RX_EQ_DELTA_IQ_G1 - RX Equalization DELTA IQ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1C_EXT_RX_EQ_DELTA_IQ_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1C_EXT_RX_EQ_DELTA_IQ_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_1C_EXT_RX_EQ_DELTA_IQ_G1_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_2A - PCIe PHY RX Equalization Control 1 For Gen2 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_AFE_EN_G2_MASK (0x3U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_AFE_EN_G2_SHIFT (0U) /*! EXT_RX_ADAPT_AFE_EN_G2 - RX Adaptation Enable */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_AFE_EN_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_AFE_EN_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_AFE_EN_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_DFE_EN_G2_MASK (0xCU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_DFE_EN_G2_SHIFT (2U) /*! EXT_RX_ADAPT_DFE_EN_G2 - RX DFE Enable */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_DFE_EN_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_DFE_EN_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_ADAPT_DFE_EN_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_ATT_LVL_G2_MASK (0x3F0U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_ATT_LVL_G2_SHIFT (4U) /*! EXT_RX_EQ_ATT_LVL_G2 - RX Equalization Attenuation Level */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_ATT_LVL_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_ATT_LVL_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_ATT_LVL_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_BOOST_G2_MASK (0x3FF0000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_BOOST_G2_SHIFT (16U) /*! EXT_RX_EQ_CTLE_BOOST_G2 - RX Equalization CTLE Boost */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_BOOST_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_BOOST_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_BOOST_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_POLE_G2_MASK (0xFC000000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_POLE_G2_SHIFT (26U) /*! EXT_RX_EQ_CTLE_POLE_G2 - RX Equalization CTLE Pole */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_POLE_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_POLE_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2A_EXT_RX_EQ_CTLE_POLE_G2_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_2B - PCIe PHY RX Equalization Control 2 For Gen2 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_DFE_TAP1_G2_MASK (0xFFFFU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_DFE_TAP1_G2_SHIFT (0U) /*! EXT_RX_EQ_DFE_TAP1_G2 - RX Equalization DFE Tap1 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_DFE_TAP1_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_DFE_TAP1_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_DFE_TAP1_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA1_GAIN_G2_MASK (0xFF0000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA1_GAIN_G2_SHIFT (16U) /*! EXT_RX_EQ_VGA1_GAIN_G2 - RX Equalization VGA Gain 1 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA1_GAIN_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA1_GAIN_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA1_GAIN_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA2_GAIN_G2_MASK (0xFF000000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA2_GAIN_G2_SHIFT (24U) /*! EXT_RX_EQ_VGA2_GAIN_G2 - RX Equalization VGA Gain 2 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA2_GAIN_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA2_GAIN_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2B_EXT_RX_EQ_VGA2_GAIN_G2_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_2C - PCIe PHY RX Equalization Control 3 For Gen2 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2C_EXT_RX_EQ_DELTA_IQ_G2_MASK (0xFFU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2C_EXT_RX_EQ_DELTA_IQ_G2_SHIFT (0U) /*! EXT_RX_EQ_DELTA_IQ_G2 - RX Equalization DELTA IQ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2C_EXT_RX_EQ_DELTA_IQ_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2C_EXT_RX_EQ_DELTA_IQ_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_2C_EXT_RX_EQ_DELTA_IQ_G2_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_3A - PCIe PHY RX Equalization Control 1 For Gen3 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_AFE_EN_G3_MASK (0x3U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_AFE_EN_G3_SHIFT (0U) /*! EXT_RX_ADAPT_AFE_EN_G3 - RX Adaptation Enable */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_AFE_EN_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_AFE_EN_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_AFE_EN_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_DFE_EN_G3_MASK (0xCU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_DFE_EN_G3_SHIFT (2U) /*! EXT_RX_ADAPT_DFE_EN_G3 - RX DFE Enable */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_DFE_EN_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_DFE_EN_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_ADAPT_DFE_EN_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_ATT_LVL_G3_MASK (0x3F0U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_ATT_LVL_G3_SHIFT (4U) /*! EXT_RX_EQ_ATT_LVL_G3 - RX Equalization Attenuation Level */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_ATT_LVL_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_ATT_LVL_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_ATT_LVL_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_BOOST_G3_MASK (0x3FF0000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_BOOST_G3_SHIFT (16U) /*! EXT_RX_EQ_CTLE_BOOST_G3 - RX Equalization CTLE Boost */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_BOOST_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_BOOST_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_BOOST_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_POLE_G3_MASK (0xFC000000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_POLE_G3_SHIFT (26U) /*! EXT_RX_EQ_CTLE_POLE_G3 - RX Equalization CTLE Pole */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_POLE_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_POLE_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3A_EXT_RX_EQ_CTLE_POLE_G3_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_3B - PCIe PHY RX Equalization Control 2 For Gen3 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_DFE_TAP1_G3_MASK (0xFFFFU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_DFE_TAP1_G3_SHIFT (0U) /*! EXT_RX_EQ_DFE_TAP1_G3 - RX Equalization DFE Tap1 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_DFE_TAP1_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_DFE_TAP1_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_DFE_TAP1_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA1_GAIN_G3_MASK (0xFF0000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA1_GAIN_G3_SHIFT (16U) /*! EXT_RX_EQ_VGA1_GAIN_G3 - RX Equalization VGA Gain 1 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA1_GAIN_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA1_GAIN_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA1_GAIN_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA2_GAIN_G3_MASK (0xFF000000U) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA2_GAIN_G3_SHIFT (24U) /*! EXT_RX_EQ_VGA2_GAIN_G3 - RX Equalization VGA Gain 2 */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA2_GAIN_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA2_GAIN_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3B_EXT_RX_EQ_VGA2_GAIN_G3_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_RX_EQ_CTRL_3C - PCIe PHY RX Equalization Control 3 For Gen3 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3C_EXT_RX_EQ_DELTA_IQ_G3_MASK (0xFFU) #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3C_EXT_RX_EQ_DELTA_IQ_G3_SHIFT (0U) /*! EXT_RX_EQ_DELTA_IQ_G3 - RX Equalization DELTA IQ */ #define SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3C_EXT_RX_EQ_DELTA_IQ_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3C_EXT_RX_EQ_DELTA_IQ_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_RX_EQ_CTRL_3C_EXT_RX_EQ_DELTA_IQ_G3_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_CALI_CTRL_1 - PCIe PHY Calibration Control For Gen1 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_VCO_LD_VAL_G1_MASK (0x1FFFU) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_VCO_LD_VAL_G1_SHIFT (0U) /*! EXT_RX_VCO_LD_VAL_G1 - RX VCO Calibration Load Value */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_VCO_LD_VAL_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_VCO_LD_VAL_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_VCO_LD_VAL_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_REF_LD_VAL_G1_MASK (0x3F0000U) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_REF_LD_VAL_G1_SHIFT (16U) /*! EXT_RX_REF_LD_VAL_G1 - RX VCO Calibration Reference Load Value */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_REF_LD_VAL_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_REF_LD_VAL_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_EXT_RX_REF_LD_VAL_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1_SHIFT (31U) /*! PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1 - Overrides settings for receiver vco */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_1_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_CALI_CTRL_2 - PCIe PHY Calibration Control For Gen2 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_VCO_LD_VAL_G2_MASK (0x1FFFU) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_VCO_LD_VAL_G2_SHIFT (0U) /*! EXT_RX_VCO_LD_VAL_G2 - RX VCO Calibration Load Value */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_VCO_LD_VAL_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_VCO_LD_VAL_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_VCO_LD_VAL_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_REF_LD_VAL_G2_MASK (0x3F0000U) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_REF_LD_VAL_G2_SHIFT (16U) /*! EXT_RX_REF_LD_VAL_G2 - RX VCO Calibration Reference Load Value */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_REF_LD_VAL_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_REF_LD_VAL_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_EXT_RX_REF_LD_VAL_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2_SHIFT (31U) /*! PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2 - Overrides settings for receiver vco */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_2_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_CALI_CTRL_3 - PCIe PHY Calibration Control For Gen3 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_VCO_LD_VAL_G3_MASK (0x1FFFU) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_VCO_LD_VAL_G3_SHIFT (0U) /*! EXT_RX_VCO_LD_VAL_G3 - RX VCO Calibration Load Value */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_VCO_LD_VAL_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_VCO_LD_VAL_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_VCO_LD_VAL_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_REF_LD_VAL_G3_MASK (0x3F0000U) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_REF_LD_VAL_G3_SHIFT (16U) /*! EXT_RX_REF_LD_VAL_G3 - RX VCO Calibration Reference Load Value */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_REF_LD_VAL_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_REF_LD_VAL_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_EXT_RX_REF_LD_VAL_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3_SHIFT (31U) /*! PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3 - Overrides settings for receiver vco */ #define SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_CALI_CTRL_3_PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MISC_CTRL_1 - PCIe PHY Miscellaneous Control 1 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_LFPS_EN_MASK (0x1U) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_LFPS_EN_SHIFT (0U) /*! EXT_RX_LOS_LFPS_EN - Receiver LOS LFPS Enable * 0b0..Driven to 0 * 0b1..Driven to 1 */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_LFPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_LFPS_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_LFPS_EN_MASK) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_THRESHOLD_MASK (0xEU) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_THRESHOLD_SHIFT (1U) /*! EXT_RX_LOS_THRESHOLD - Receiver LOS Threshold */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_THRESHOLD_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_LOS_THRESHOLD_MASK) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_VREF_CTRL_MASK (0x1F000000U) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_VREF_CTRL_SHIFT (24U) /*! EXT_RX_VREF_CTRL - RX Biasing Current Control */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_VREF_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_VREF_CTRL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_VREF_CTRL_MASK) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_TERM_CTRL_MASK (0xE0000000U) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_TERM_CTRL_SHIFT (29U) /*! EXT_RX_TERM_CTRL - RX Term Control */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_TERM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_TERM_CTRL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_1_EXT_RX_TERM_CTRL_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_MISC_CTRL_2 - PCIe PHY Miscellaneous Control 2 */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_IBOOST_LVL_MASK (0xFU) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_IBOOST_LVL_SHIFT (0U) /*! EXT_TX_IBOOST_LVL - Transmitter Current Boost Level */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_IBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_IBOOST_LVL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_IBOOST_LVL_MASK) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_VBOOST_LVL_MASK (0x70000U) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_VBOOST_LVL_SHIFT (16U) /*! EXT_TX_VBOOST_LVL - TX Voltage Boost Maximum Level */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_VBOOST_LVL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_VBOOST_LVL_MASK) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_TERM_CTRL_MASK (0x7000000U) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_TERM_CTRL_SHIFT (24U) /*! EXT_TX_TERM_CTRL - Tx Term Control */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_TERM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_TERM_CTRL_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_EXT_TX_TERM_CTRL_MASK) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_PROTOCOL0_EXT_TX_VBOOST_EN_MASK (0x80000000U) #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_PROTOCOL0_EXT_TX_VBOOST_EN_SHIFT (31U) /*! PROTOCOL0_EXT_TX_VBOOST_EN - Transmitter voltage boost enable * 0b0..Disabled * 0b1..Enabled */ #define SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_PROTOCOL0_EXT_TX_VBOOST_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_PROTOCOL0_EXT_TX_VBOOST_EN_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_MISC_CTRL_2_PROTOCOL0_EXT_TX_VBOOST_EN_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_TX_EQ_CTRL_1 - PCIe PHY TX Equalization Control For Gen1 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_POST_G1_MASK (0xFU) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_POST_G1_SHIFT (0U) /*! EXT_TX_EQ_POST_G1 - TX Equalization Post-Emphasis Level Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_POST_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_POST_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_POST_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_PRE_G1_MASK (0xF00U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_PRE_G1_SHIFT (8U) /*! EXT_TX_EQ_PRE_G1 - TX Equalization Pre-Emphasis Level Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_PRE_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_PRE_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_PRE_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_MAIN_G1_MASK (0x1F0000U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_MAIN_G1_SHIFT (16U) /*! EXT_TX_EQ_MAIN_G1 - TX Equalization Amplitude Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_MAIN_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_MAIN_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_MAIN_G1_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_OVRD_G1_MASK (0x10000000U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_OVRD_G1_SHIFT (28U) /*! EXT_TX_EQ_OVRD_G1 - TX Equalization Override Enable */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_OVRD_G1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_OVRD_G1_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_1_EXT_TX_EQ_OVRD_G1_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_TX_EQ_CTRL_2 - PCIe PHY TX Equalization Control For Gen2 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_POST_G2_MASK (0xFU) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_POST_G2_SHIFT (0U) /*! EXT_TX_EQ_POST_G2 - TX Equalization Post-Emphasis Level Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_POST_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_POST_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_POST_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_PRE_G2_MASK (0xF00U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_PRE_G2_SHIFT (8U) /*! EXT_TX_EQ_PRE_G2 - TX Equalization Pre-Emphasis Level Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_PRE_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_PRE_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_PRE_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_MAIN_G2_MASK (0x1F0000U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_MAIN_G2_SHIFT (16U) /*! EXT_TX_EQ_MAIN_G2 - TX Equalization Amplitude Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_MAIN_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_MAIN_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_MAIN_G2_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_OVRD_G2_MASK (0x30000000U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_OVRD_G2_SHIFT (28U) /*! EXT_TX_EQ_OVRD_G2 - TX Equalization Override Enable */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_OVRD_G2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_OVRD_G2_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_2_EXT_TX_EQ_OVRD_G2_MASK) /*! @} */ /*! @name PCIE_PHY_EXT_TX_EQ_CTRL_3 - PCIe PHY TX Equalization Control For Gen3 Speed */ /*! @{ */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_POST_G3_MASK (0xFU) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_POST_G3_SHIFT (0U) /*! EXT_TX_EQ_POST_G3 - TX Equalization Post-Emphasis Level Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_POST_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_POST_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_POST_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_PRE_G3_MASK (0xF00U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_PRE_G3_SHIFT (8U) /*! EXT_TX_EQ_PRE_G3 - TX Equalization Pre-Emphasis Level Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_PRE_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_PRE_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_PRE_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_MAIN_G3_MASK (0x1F0000U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_MAIN_G3_SHIFT (16U) /*! EXT_TX_EQ_MAIN_G3 - TX Equalization Amplitude Adjustment Control */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_MAIN_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_MAIN_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_MAIN_G3_MASK) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_OVRD_G3_MASK (0x30000000U) #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_OVRD_G3_SHIFT (28U) /*! EXT_TX_EQ_OVRD_G3 - TX Equalization Override Enable */ #define SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_OVRD_G3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_OVRD_G3_SHIFT)) & SerDes_SS_PCIE_PHY_EXT_TX_EQ_CTRL_3_EXT_TX_EQ_OVRD_G3_MASK) /*! @} */ /*! @name SS_RO_REG_0 - Subsystem Read-Only Register 0 */ /*! @{ */ #define SerDes_SS_SS_RO_REG_0_PHY_RX0_LOS_MASK (0x2U) #define SerDes_SS_SS_RO_REG_0_PHY_RX0_LOS_SHIFT (1U) /*! PHY_RX0_LOS - Receive Loss Of Signal (LOS) Output 0 * 0b0..The receiver has not lost the signal. * 0b1..The receiver has lost the signal. */ #define SerDes_SS_SS_RO_REG_0_PHY_RX0_LOS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_0_PHY_RX0_LOS_SHIFT)) & SerDes_SS_SS_RO_REG_0_PHY_RX0_LOS_MASK) #define SerDes_SS_SS_RO_REG_0_MSTR_AWMISC_INFO_LAST_DCMP_TLP_MASK (0x8U) #define SerDes_SS_SS_RO_REG_0_MSTR_AWMISC_INFO_LAST_DCMP_TLP_SHIFT (3U) /*! MSTR_AWMISC_INFO_LAST_DCMP_TLP - Last TLP Of The PCIe controller's AXI Master Write Request * 0b0..The TLP in the transaction is not the last TLP of the write request. * 0b1..The TLP in the transaction is the last TLP of the write request. */ #define SerDes_SS_SS_RO_REG_0_MSTR_AWMISC_INFO_LAST_DCMP_TLP(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_0_MSTR_AWMISC_INFO_LAST_DCMP_TLP_SHIFT)) & SerDes_SS_SS_RO_REG_0_MSTR_AWMISC_INFO_LAST_DCMP_TLP_MASK) #define SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_LAST_DCMP_TLP_MASK (0x10U) #define SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_LAST_DCMP_TLP_SHIFT (4U) /*! MSTR_ARMISC_INFO_LAST_DCMP_TLP - Last TLP Of The PCIe Controller's AXI Master Read Request * 0b0..The TLP in the transaction is not the last TLP of the read request. * 0b1..The TLP in the transaction is the last TLP of the read request. */ #define SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_LAST_DCMP_TLP(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_LAST_DCMP_TLP_SHIFT)) & SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_LAST_DCMP_TLP_MASK) #define SerDes_SS_SS_RO_REG_0_MSI_CTRL_INT_VEC_MASK (0x1FE0U) #define SerDes_SS_SS_RO_REG_0_MSI_CTRL_INT_VEC_SHIFT (5U) /*! MSI_CTRL_INT_VEC - DSP AXI MSI Interrupt Vector */ #define SerDes_SS_SS_RO_REG_0_MSI_CTRL_INT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_0_MSI_CTRL_INT_VEC_SHIFT)) & SerDes_SS_SS_RO_REG_0_MSI_CTRL_INT_VEC_MASK) #define SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_DMA_MASK (0xFC000000U) #define SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_DMA_SHIFT (26U) /*! MSTR_ARMISC_INFO_DMA - DMA Bits Of The AXI Read Master Transaction */ #define SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_DMA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_DMA_SHIFT)) & SerDes_SS_SS_RO_REG_0_MSTR_ARMISC_INFO_DMA_MASK) /*! @} */ /*! @name SS_RO_REG_1 - Subsystem Read-Only Register 1 */ /*! @{ */ #define SerDes_SS_SS_RO_REG_1_MSTR_AWMISC_INFO_DMA_MASK (0x3FU) #define SerDes_SS_SS_RO_REG_1_MSTR_AWMISC_INFO_DMA_SHIFT (0U) /*! MSTR_AWMISC_INFO_DMA - DMA Bits Of The AXI Write Master Transaction */ #define SerDes_SS_SS_RO_REG_1_MSTR_AWMISC_INFO_DMA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_1_MSTR_AWMISC_INFO_DMA_SHIFT)) & SerDes_SS_SS_RO_REG_1_MSTR_AWMISC_INFO_DMA_MASK) #define SerDes_SS_SS_RO_REG_1_SLV_BMISC_INFO_MASK (0x1FFC0U) #define SerDes_SS_SS_RO_REG_1_SLV_BMISC_INFO_SHIFT (6U) /*! SLV_BMISC_INFO - Miscellaneous Write Information */ #define SerDes_SS_SS_RO_REG_1_SLV_BMISC_INFO(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_1_SLV_BMISC_INFO_SHIFT)) & SerDes_SS_SS_RO_REG_1_SLV_BMISC_INFO_MASK) #define SerDes_SS_SS_RO_REG_1_SLV_RMISC_INFO_MASK (0xFFE0000U) #define SerDes_SS_SS_RO_REG_1_SLV_RMISC_INFO_SHIFT (17U) /*! SLV_RMISC_INFO - Miscellaneous Read Information */ #define SerDes_SS_SS_RO_REG_1_SLV_RMISC_INFO(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_1_SLV_RMISC_INFO_SHIFT)) & SerDes_SS_SS_RO_REG_1_SLV_RMISC_INFO_MASK) /*! @} */ /*! @name SS_RO_REG_2 - Subsystem Read-Only Register 2 */ /*! @{ */ #define SerDes_SS_SS_RO_REG_2_REG2_MASK (0xFFFFFFFFU) #define SerDes_SS_SS_RO_REG_2_REG2_SHIFT (0U) /*! REG2 - Subsystem Read Only Register 2 */ #define SerDes_SS_SS_RO_REG_2_REG2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_2_REG2_SHIFT)) & SerDes_SS_SS_RO_REG_2_REG2_MASK) /*! @} */ /*! @name SS_RO_REG_3 - Subsystem Read-Only Register 3 */ /*! @{ */ #define SerDes_SS_SS_RO_REG_3_REG3_MASK (0xFFFFFFFFU) #define SerDes_SS_SS_RO_REG_3_REG3_SHIFT (0U) /*! REG3 - Subsystem Read Only Register 3 */ #define SerDes_SS_SS_RO_REG_3_REG3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RO_REG_3_REG3_SHIFT)) & SerDes_SS_SS_RO_REG_3_REG3_MASK) /*! @} */ /*! @name SS_RW_REG_0 - Subsystem Read/Write Register 0 */ /*! @{ */ #define SerDes_SS_SS_RW_REG_0_MSTR_RMISC_INFO_CPL_STAT_MASK (0x7U) #define SerDes_SS_SS_RW_REG_0_MSTR_RMISC_INFO_CPL_STAT_SHIFT (0U) /*! MSTR_RMISC_INFO_CPL_STAT - AXI Master Read Response Selection Bus * 0b000..Successful completion * 0b001..Unsupported request * 0b010..Request retry status * 0b100..Completer abort * *.. */ #define SerDes_SS_SS_RW_REG_0_MSTR_RMISC_INFO_CPL_STAT(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_MSTR_RMISC_INFO_CPL_STAT_SHIFT)) & SerDes_SS_SS_RW_REG_0_MSTR_RMISC_INFO_CPL_STAT_MASK) #define SerDes_SS_SS_RW_REG_0_SYS_ATTEN_BUTTON_PRESSED_MASK (0x8U) #define SerDes_SS_SS_RW_REG_0_SYS_ATTEN_BUTTON_PRESSED_SHIFT (3U) /*! SYS_ATTEN_BUTTON_PRESSED - Attention Button Pressed */ #define SerDes_SS_SS_RW_REG_0_SYS_ATTEN_BUTTON_PRESSED(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_SYS_ATTEN_BUTTON_PRESSED_SHIFT)) & SerDes_SS_SS_RW_REG_0_SYS_ATTEN_BUTTON_PRESSED_MASK) #define SerDes_SS_SS_RW_REG_0_SYS_CMD_CPLED_INT_MASK (0x10U) #define SerDes_SS_SS_RW_REG_0_SYS_CMD_CPLED_INT_SHIFT (4U) /*! SYS_CMD_CPLED_INT - Command Completed Interrupt * 0b0..Command not completed * 0b1..Command completed */ #define SerDes_SS_SS_RW_REG_0_SYS_CMD_CPLED_INT(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_SYS_CMD_CPLED_INT_SHIFT)) & SerDes_SS_SS_RW_REG_0_SYS_CMD_CPLED_INT_MASK) #define SerDes_SS_SS_RW_REG_0_SYS_EML_INTERLOCK_ENGAGED_MASK (0x20U) #define SerDes_SS_SS_RW_REG_0_SYS_EML_INTERLOCK_ENGAGED_SHIFT (5U) /*! SYS_EML_INTERLOCK_ENGAGED - System Electromechanical Interlock Engaged * 0b0..Electromechanical interlock is not engaged * 0b1..Electromechanical interlock is engaged */ #define SerDes_SS_SS_RW_REG_0_SYS_EML_INTERLOCK_ENGAGED(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_SYS_EML_INTERLOCK_ENGAGED_SHIFT)) & SerDes_SS_SS_RW_REG_0_SYS_EML_INTERLOCK_ENGAGED_MASK) #define SerDes_SS_SS_RW_REG_0_SYS_INT_MASK (0x40U) #define SerDes_SS_SS_RW_REG_0_SYS_INT_SHIFT (6U) /*! SYS_INT - System Interrupt */ #define SerDes_SS_SS_RW_REG_0_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_SYS_INT_SHIFT)) & SerDes_SS_SS_RW_REG_0_SYS_INT_MASK) #define SerDes_SS_SS_RW_REG_0_APP_XFER_PENDING_MASK (0x80U) #define SerDes_SS_SS_RW_REG_0_APP_XFER_PENDING_SHIFT (7U) /*! APP_XFER_PENDING - Application Transfer Pending * 0b0..No transactions exist outside the core * 0b1..Transactions exist outside the core, and the core must transmit these */ #define SerDes_SS_SS_RW_REG_0_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_APP_XFER_PENDING_SHIFT)) & SerDes_SS_SS_RW_REG_0_APP_XFER_PENDING_MASK) #define SerDes_SS_SS_RW_REG_0_PHY0_CR_PARA_SEL_MASK (0x200U) #define SerDes_SS_SS_RW_REG_0_PHY0_CR_PARA_SEL_SHIFT (9U) /*! PHY0_CR_PARA_SEL - Control Register (CR) Parallel Interface Select * 0b0..Select the JTAG interface. * 0b1..Select the CR interface. */ #define SerDes_SS_SS_RW_REG_0_PHY0_CR_PARA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_PHY0_CR_PARA_SEL_SHIFT)) & SerDes_SS_SS_RW_REG_0_PHY0_CR_PARA_SEL_MASK) #define SerDes_SS_SS_RW_REG_0_CLKEN_MASK (0x800000U) #define SerDes_SS_SS_RW_REG_0_CLKEN_SHIFT (23U) /*! CLKEN - PCIe Reference Clock Enable * 0b0..External clock (phy0_ref_pad_clk_m, phy0_ref_pad_clk_p) is the reference clock for the PCIe PHY PLL. * 0b1..Internal clock (PCIE_REF_CLK) is the reference clock for the PCIe PHY PLL. */ #define SerDes_SS_SS_RW_REG_0_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_CLKEN_SHIFT)) & SerDes_SS_SS_RW_REG_0_CLKEN_MASK) #define SerDes_SS_SS_RW_REG_0_PHY_TEST_TX_REF_CLK_EN_MASK (0x20000000U) #define SerDes_SS_SS_RW_REG_0_PHY_TEST_TX_REF_CLK_EN_SHIFT (29U) /*! PHY_TEST_TX_REF_CLK_EN - TX Reference Clock Output Enable * 0b0..Normal functional operation * 0b1..The reference clock inputs (ref_pad_clk_{p,m} or ref_alt_clk_{p,m}) are directly output to txN_{p,m} */ #define SerDes_SS_SS_RW_REG_0_PHY_TEST_TX_REF_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_0_PHY_TEST_TX_REF_CLK_EN_SHIFT)) & SerDes_SS_SS_RW_REG_0_PHY_TEST_TX_REF_CLK_EN_MASK) /*! @} */ /*! @name SS_RW_REG_1 - Subsystem Read/Write Register 1 */ /*! @{ */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_DATA_MASK (0x1U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_DATA_SHIFT (0U) /*! PARITY_MODE_MSTR_RD_DATA - Parity Error Injection In AXI Master Read Data Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_DATA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_DATA_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_DATA_MASK) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_ADDR_MASK (0x2U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_ADDR_SHIFT (1U) /*! PARITY_MODE_SLV_RD_ADDR - Parity Error Injection In AXI Slave Read Address Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_ADDR_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_ADDR_MASK) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_ADDR_MASK (0x4U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_ADDR_SHIFT (2U) /*! PARITY_MODE_SLV_WR_ADDR - Parity Error Injection In AXI Slave Write Address Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_ADDR_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_ADDR_MASK) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_DATA_MASK (0x8U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_DATA_SHIFT (3U) /*! PARITY_MODE_SLV_WR_DATA - Parity Error Injection In AXI Slave Write Data Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_DATA_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_WR_DATA_MASK) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_ADDR_MASK (0x10U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_ADDR_SHIFT (4U) /*! PARITY_MODE_MSTR_RD_ADDR - Parity Error Injection In AXI Master Read Address Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_ADDR_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_RD_ADDR_MASK) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_ADDR_MASK (0x20U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_ADDR_SHIFT (5U) /*! PARITY_MODE_MSTR_WR_ADDR - Parity Error Injection In AXI Master Write Address Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_ADDR_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_ADDR_MASK) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_DATA_MASK (0x40U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_DATA_SHIFT (6U) /*! PARITY_MODE_MSTR_WR_DATA - Parity Error Injection In AXI Master Write Data Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_DATA_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_MSTR_WR_DATA_MASK) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_DATA_MASK (0x80U) #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_DATA_SHIFT (7U) /*! PARITY_MODE_SLV_RD_DATA - Parity Error Injection In AXI Slave Read Data Bus * 0b0..No error injected * 0b1..Error injected */ #define SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_DATA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_DATA_SHIFT)) & SerDes_SS_SS_RW_REG_1_PARITY_MODE_SLV_RD_DATA_MASK) #define SerDes_SS_SS_RW_REG_1_SYS_AUX_PWR_DET_MASK (0x80000000U) #define SerDes_SS_SS_RW_REG_1_SYS_AUX_PWR_DET_SHIFT (31U) /*! SYS_AUX_PWR_DET - System AUX Power Detection * 0b0..AUX power is available * 0b1..No AUX power is available */ #define SerDes_SS_SS_RW_REG_1_SYS_AUX_PWR_DET(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_1_SYS_AUX_PWR_DET_SHIFT)) & SerDes_SS_SS_RW_REG_1_SYS_AUX_PWR_DET_MASK) /*! @} */ /*! @name SS_RW_REG_2 - Subsystem Read/Write Register 2 */ /*! @{ */ #define SerDes_SS_SS_RW_REG_2_SLV_ARMISC_INFO_MASK (0x3FFFFFU) #define SerDes_SS_SS_RW_REG_2_SLV_ARMISC_INFO_SHIFT (0U) /*! SLV_ARMISC_INFO - Miscellaneous Information Associated With The AXI Slave Read Transaction */ #define SerDes_SS_SS_RW_REG_2_SLV_ARMISC_INFO(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_2_SLV_ARMISC_INFO_SHIFT)) & SerDes_SS_SS_RW_REG_2_SLV_ARMISC_INFO_MASK) /*! @} */ /*! @name SS_RW_REG_3 - Subsystem Read/Write Register 3 */ /*! @{ */ #define SerDes_SS_SS_RW_REG_3_SLV_AWMISC_INFO_MASK (0x3FFFFFU) #define SerDes_SS_SS_RW_REG_3_SLV_AWMISC_INFO_SHIFT (0U) /*! SLV_AWMISC_INFO - Miscellaneous Information Associated With The AXI Slave Write Transaction */ #define SerDes_SS_SS_RW_REG_3_SLV_AWMISC_INFO(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_3_SLV_AWMISC_INFO_SHIFT)) & SerDes_SS_SS_RW_REG_3_SLV_AWMISC_INFO_MASK) /*! @} */ /*! @name SS_RW_REG_4 - Subsystem Read/Write Register 4 */ /*! @{ */ #define SerDes_SS_SS_RW_REG_4_SLV_AWMISC_INFO_HDR_3DW_MASK (0xFFFFFFFFU) #define SerDes_SS_SS_RW_REG_4_SLV_AWMISC_INFO_HDR_3DW_SHIFT (0U) /*! SLV_AWMISC_INFO_HDR_3DW - AXI Slave Third Header DWs */ #define SerDes_SS_SS_RW_REG_4_SLV_AWMISC_INFO_HDR_3DW(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_4_SLV_AWMISC_INFO_HDR_3DW_SHIFT)) & SerDes_SS_SS_RW_REG_4_SLV_AWMISC_INFO_HDR_3DW_MASK) /*! @} */ /*! @name SS_RW_REG_5 - Subsystem Read/Write Register 5 */ /*! @{ */ #define SerDes_SS_SS_RW_REG_5_SLV_AWMISC_INFO_HDR_4DW_MASK (0xFFFFFFFFU) #define SerDes_SS_SS_RW_REG_5_SLV_AWMISC_INFO_HDR_4DW_SHIFT (0U) /*! SLV_AWMISC_INFO_HDR_4DW - AXI Slave Fourth Header DWs */ #define SerDes_SS_SS_RW_REG_5_SLV_AWMISC_INFO_HDR_4DW(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_SS_RW_REG_5_SLV_AWMISC_INFO_HDR_4DW_SHIFT)) & SerDes_SS_SS_RW_REG_5_SLV_AWMISC_INFO_HDR_4DW_MASK) /*! @} */ /*! @name PCIE_SUBSYSTEM_VERSION - PCIe Subsystem Version */ /*! @{ */ #define SerDes_SS_PCIE_SUBSYSTEM_VERSION_VERSION_MASK (0xFFFFFFFFU) #define SerDes_SS_PCIE_SUBSYSTEM_VERSION_VERSION_SHIFT (0U) /*! VERSION - PCIe Subsystem Version */ #define SerDes_SS_PCIE_SUBSYSTEM_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PCIE_SUBSYSTEM_VERSION_VERSION_SHIFT)) & SerDes_SS_PCIE_SUBSYSTEM_VERSION_VERSION_MASK) /*! @} */ /*! @name PE0_CLKREQ_CTRL - PCIe Controller Clock Request Override */ /*! @{ */ #define SerDes_SS_PE0_CLKREQ_CTRL_CLKREQ_OVER_MASK (0x1U) #define SerDes_SS_PE0_CLKREQ_CTRL_CLKREQ_OVER_SHIFT (0U) /*! CLKREQ_OVER - CLKREQ override * 0b0..CLKREQ is driven by system * 0b1..CLKREQ is driven by software */ #define SerDes_SS_PE0_CLKREQ_CTRL_CLKREQ_OVER(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_CLKREQ_CTRL_CLKREQ_OVER_SHIFT)) & SerDes_SS_PE0_CLKREQ_CTRL_CLKREQ_OVER_MASK) #define SerDes_SS_PE0_CLKREQ_CTRL_SW_CLK_REQ_MASK (0x2U) #define SerDes_SS_PE0_CLKREQ_CTRL_SW_CLK_REQ_SHIFT (1U) /*! SW_CLK_REQ - Software override for clkreq input of pcie controller. */ #define SerDes_SS_PE0_CLKREQ_CTRL_SW_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_CLKREQ_CTRL_SW_CLK_REQ_SHIFT)) & SerDes_SS_PE0_CLKREQ_CTRL_SW_CLK_REQ_MASK) /*! @} */ /*! @name PE0_LUT_ACSCTRL - LUT access Control */ /*! @{ */ #define SerDes_SS_PE0_LUT_ACSCTRL_ENLOC_MASK (0x1FU) #define SerDes_SS_PE0_LUT_ACSCTRL_ENLOC_SHIFT (0U) /*! ENLOC - LUT Entry location to be accessed */ #define SerDes_SS_PE0_LUT_ACSCTRL_ENLOC(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_ACSCTRL_ENLOC_SHIFT)) & SerDes_SS_PE0_LUT_ACSCTRL_ENLOC_MASK) #define SerDes_SS_PE0_LUT_ACSCTRL_RWA_MASK (0x10000U) #define SerDes_SS_PE0_LUT_ACSCTRL_RWA_SHIFT (16U) /*! RWA - LUT Entry Read/Write access control * 0b0..Write into RBP_LUT entry specified in ENTRY_LOC field * 0b1..Read from the RBP_LUT entry specified in ENTRY_LOC field */ #define SerDes_SS_PE0_LUT_ACSCTRL_RWA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_ACSCTRL_RWA_SHIFT)) & SerDes_SS_PE0_LUT_ACSCTRL_RWA_MASK) /*! @} */ /*! @name PE0_LUT_DATA1 - LUT Data1 register */ /*! @{ */ #define SerDes_SS_PE0_LUT_DATA1_STREAM_ID_MASK (0x3FU) #define SerDes_SS_PE0_LUT_DATA1_STREAM_ID_SHIFT (0U) /*! STREAM_ID - VFID of VF at the target port corresponding to REQID */ #define SerDes_SS_PE0_LUT_DATA1_STREAM_ID(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_DATA1_STREAM_ID_SHIFT)) & SerDes_SS_PE0_LUT_DATA1_STREAM_ID_MASK) #define SerDes_SS_PE0_LUT_DATA1_DAC_ID_MASK (0x700U) #define SerDes_SS_PE0_LUT_DATA1_DAC_ID_SHIFT (8U) /*! DAC_ID - DAC Index */ #define SerDes_SS_PE0_LUT_DATA1_DAC_ID(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_DATA1_DAC_ID_SHIFT)) & SerDes_SS_PE0_LUT_DATA1_DAC_ID_MASK) #define SerDes_SS_PE0_LUT_DATA1_VLD_MASK (0x80000000U) #define SerDes_SS_PE0_LUT_DATA1_VLD_SHIFT (31U) /*! VLD - LUT Entry is valid for matching * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_LUT_DATA1_VLD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_DATA1_VLD_SHIFT)) & SerDes_SS_PE0_LUT_DATA1_VLD_MASK) /*! @} */ /*! @name PE0_LUT_DATA2 - LUT Data2 register */ /*! @{ */ #define SerDes_SS_PE0_LUT_DATA2_MASK_MASK (0xFFFFU) #define SerDes_SS_PE0_LUT_DATA2_MASK_SHIFT (0U) /*! MASK - Mask to be used for matching with REQID field */ #define SerDes_SS_PE0_LUT_DATA2_MASK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_DATA2_MASK_SHIFT)) & SerDes_SS_PE0_LUT_DATA2_MASK_MASK) #define SerDes_SS_PE0_LUT_DATA2_REQID_MASK (0xFFFF0000U) #define SerDes_SS_PE0_LUT_DATA2_REQID_SHIFT (16U) /*! REQID - REQID value to matched with master port RID (in RC mode) and {BAR#, PF#, VFA, VF# } (in EP mode) */ #define SerDes_SS_PE0_LUT_DATA2_REQID(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_DATA2_REQID_SHIFT)) & SerDes_SS_PE0_LUT_DATA2_REQID_MASK) /*! @} */ /*! @name PE0_LUT_INT_STS - LUT Interrupt Status */ /*! @{ */ #define SerDes_SS_PE0_LUT_INT_STS_LUTRMS_MASK (0x40000000U) #define SerDes_SS_PE0_LUT_INT_STS_LUTRMS_SHIFT (30U) /*! LUTRMS - LUT Read Request Miss Status */ #define SerDes_SS_PE0_LUT_INT_STS_LUTRMS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_INT_STS_LUTRMS_SHIFT)) & SerDes_SS_PE0_LUT_INT_STS_LUTRMS_MASK) #define SerDes_SS_PE0_LUT_INT_STS_LUTWMS_MASK (0x80000000U) #define SerDes_SS_PE0_LUT_INT_STS_LUTWMS_SHIFT (31U) /*! LUTWMS - LUT Write Request Miss Status */ #define SerDes_SS_PE0_LUT_INT_STS_LUTWMS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_INT_STS_LUTWMS_SHIFT)) & SerDes_SS_PE0_LUT_INT_STS_LUTWMS_MASK) /*! @} */ /*! @name PE0_LUT_INT_CTRL - LUT Interrupt Control */ /*! @{ */ #define SerDes_SS_PE0_LUT_INT_CTRL_DEFAULT_MATCH_ERR_EN_MASK (0x1U) #define SerDes_SS_PE0_LUT_INT_CTRL_DEFAULT_MATCH_ERR_EN_SHIFT (0U) /*! DEFAULT_MATCH_ERR_EN - Default entry match error reporting enable * 0b0..Disabled, no error reporting on default match. * 0b1..Error reported on default entry match. */ #define SerDes_SS_PE0_LUT_INT_CTRL_DEFAULT_MATCH_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_INT_CTRL_DEFAULT_MATCH_ERR_EN_SHIFT)) & SerDes_SS_PE0_LUT_INT_CTRL_DEFAULT_MATCH_ERR_EN_MASK) #define SerDes_SS_PE0_LUT_INT_CTRL_LUTRMIE_MASK (0x40000000U) #define SerDes_SS_PE0_LUT_INT_CTRL_LUTRMIE_SHIFT (30U) /*! LUTRMIE - LUT Read request Miss Interrupt Enable * 0b0..Interrupt Disable * 0b1..Interrupt Enable */ #define SerDes_SS_PE0_LUT_INT_CTRL_LUTRMIE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_INT_CTRL_LUTRMIE_SHIFT)) & SerDes_SS_PE0_LUT_INT_CTRL_LUTRMIE_MASK) #define SerDes_SS_PE0_LUT_INT_CTRL_LUTWMIE_MASK (0x80000000U) #define SerDes_SS_PE0_LUT_INT_CTRL_LUTWMIE_SHIFT (31U) /*! LUTWMIE - LUT Write request Miss Interrupt Enable * 0b0..Interrupt Disable * 0b1..Interrupt Enable */ #define SerDes_SS_PE0_LUT_INT_CTRL_LUTWMIE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_INT_CTRL_LUTWMIE_SHIFT)) & SerDes_SS_PE0_LUT_INT_CTRL_LUTWMIE_MASK) /*! @} */ /*! @name PE0_LUT_CREQID - LUT Request ID Register */ /*! @{ */ #define SerDes_SS_PE0_LUT_CREQID_CREQID_RD_MASK (0xFFFFU) #define SerDes_SS_PE0_LUT_CREQID_CREQID_RD_SHIFT (0U) /*! CREQID_RD - Captured Read Requester ID Field */ #define SerDes_SS_PE0_LUT_CREQID_CREQID_RD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_CREQID_CREQID_RD_SHIFT)) & SerDes_SS_PE0_LUT_CREQID_CREQID_RD_MASK) #define SerDes_SS_PE0_LUT_CREQID_CREQID_WR_MASK (0xFFFF0000U) #define SerDes_SS_PE0_LUT_CREQID_CREQID_WR_SHIFT (16U) /*! CREQID_WR - Captured Write Requester ID Field */ #define SerDes_SS_PE0_LUT_CREQID_CREQID_WR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LUT_CREQID_CREQID_WR_SHIFT)) & SerDes_SS_PE0_LUT_CREQID_CREQID_WR_MASK) /*! @} */ /*! @name FLR_CTRL_STS - Function Level Reset (FLR) Control and Status Register */ /*! @{ */ #define SerDes_SS_FLR_CTRL_STS_FLRIS_MASK (0x1U) #define SerDes_SS_FLR_CTRL_STS_FLRIS_SHIFT (0U) /*! FLRIS - Indicates the FLR request . * 0b0..No FLR request pending * 0b1..FLR request arrived , approval pending. */ #define SerDes_SS_FLR_CTRL_STS_FLRIS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_FLR_CTRL_STS_FLRIS_SHIFT)) & SerDes_SS_FLR_CTRL_STS_FLRIS_MASK) #define SerDes_SS_FLR_CTRL_STS_FLRDNBYP_MASK (0x80000000U) #define SerDes_SS_FLR_CTRL_STS_FLRDNBYP_SHIFT (31U) /*! FLRDNBYP - Bypass SW wait for FLR DONE confirmation * 0b0..NOT BYPASSED * 0b1..BYPASSED */ #define SerDes_SS_FLR_CTRL_STS_FLRDNBYP(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_FLR_CTRL_STS_FLRDNBYP_SHIFT)) & SerDes_SS_FLR_CTRL_STS_FLRDNBYP_MASK) /*! @} */ /*! @name LINK_INT_CTRL_STS - Link Interrupt Control And Status */ /*! @{ */ #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_STS_MASK (0x1U) #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_STS_SHIFT (0U) /*! LINK_REQ_RST_NOT_STS - Link Request Reset Status * 0b0..Not set * 0b1..Set */ #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_STS_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_STS_MASK) #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_INT_EN_MASK (0x2U) #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_INT_EN_SHIFT (1U) /*! LINK_REQ_RST_NOT_INT_EN - Link Request Reset Interrupt Enable Control * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_INT_EN_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_INT_EN_MASK) #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_CLR_MASK (0x4U) #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_CLR_SHIFT (2U) /*! LINK_REQ_RST_NOT_CLR - Clear Link Request Reset Status * 0b0..Do not change LINK_REQ_RST_NOT_STS * 0b1..Change LINK_REQ_RST_NOT_STS to 0 */ #define SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_CLR_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_LINK_REQ_RST_NOT_CLR_MASK) #define SerDes_SS_LINK_INT_CTRL_STS_LTSSM_STATE_RCVRY_EQ_MASK (0x40U) #define SerDes_SS_LINK_INT_CTRL_STS_LTSSM_STATE_RCVRY_EQ_SHIFT (6U) /*! LTSSM_STATE_RCVRY_EQ - Recovery Equalization State Status * 0b0..Not in Recovery Equalization state * 0b1..In Recovery Equalization state */ #define SerDes_SS_LINK_INT_CTRL_STS_LTSSM_STATE_RCVRY_EQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_LTSSM_STATE_RCVRY_EQ_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_LTSSM_STATE_RCVRY_EQ_MASK) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_EN_MASK (0x100U) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_EN_SHIFT (8U) /*! RDLH_LINK_UP_INT_EN - Interrupt enable for RDLH Link up event * 0b0..Interrupt disable * 0b1..Interrupt enable */ #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_EN_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_EN_MASK) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_STS_MASK (0x200U) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_STS_SHIFT (9U) /*! RDLH_LINK_UP_INT_STS - RDLH Link up event interrupt status * 0b0..No interrupt pending * 0b1..Interrupt is pending */ #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_STS_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_UP_INT_STS_MASK) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_EN_MASK (0x400U) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_EN_SHIFT (10U) /*! RDLH_LINK_DOWN_INT_EN - Interrupt enable for RDLH Link down event * 0b0..Interrupt disable * 0b1..Interrupt enable */ #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_EN_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_EN_MASK) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_STS_MASK (0x800U) #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_STS_SHIFT (11U) /*! RDLH_LINK_DOWN_INT_STS - RDLH Link down event interrupt status * 0b0..No interrupt pending * 0b1..Interrupt is pending */ #define SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_STS_SHIFT)) & SerDes_SS_LINK_INT_CTRL_STS_RDLH_LINK_DOWN_INT_STS_MASK) /*! @} */ /*! @name PE0_GEN_CTRL_1 - PCIe Controller 0 General Control 1 */ /*! @{ */ #define SerDes_SS_PE0_GEN_CTRL_1_DEVICE_TYPE_MASK (0xFU) #define SerDes_SS_PE0_GEN_CTRL_1_DEVICE_TYPE_SHIFT (0U) /*! DEVICE_TYPE - Device Type * 0b0000..Endpoint * 0b0100..Root port of root complex * *.. */ #define SerDes_SS_PE0_GEN_CTRL_1_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_1_DEVICE_TYPE_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_1_DEVICE_TYPE_MASK) #define SerDes_SS_PE0_GEN_CTRL_1_SRIS_MODE_MASK (0x100U) #define SerDes_SS_PE0_GEN_CTRL_1_SRIS_MODE_SHIFT (8U) /*! SRIS_MODE - SRIS Operation Mode * 0b0..Non-SRIS * 0b1..SRIS */ #define SerDes_SS_PE0_GEN_CTRL_1_SRIS_MODE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_1_SRIS_MODE_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_1_SRIS_MODE_MASK) #define SerDes_SS_PE0_GEN_CTRL_1_ECAM_BUS_ERR_CTRL_MASK (0x1000U) #define SerDes_SS_PE0_GEN_CTRL_1_ECAM_BUS_ERR_CTRL_SHIFT (12U) /*! ECAM_BUS_ERR_CTRL - Return error on system bus for invalid ECAM accesses from system * 0b0..Do not return error * 0b1..Return error */ #define SerDes_SS_PE0_GEN_CTRL_1_ECAM_BUS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_1_ECAM_BUS_ERR_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_1_ECAM_BUS_ERR_CTRL_MASK) /*! @} */ /*! @name PE0_GEN_CTRL_2 - PCIe Controller 0 General Control 2 */ /*! @{ */ #define SerDes_SS_PE0_GEN_CTRL_2_CFG_AER_RC_ERR_INT_CTRL_MASK (0x1U) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_AER_RC_ERR_INT_CTRL_SHIFT (0U) /*! CFG_AER_RC_ERR_INT_CTRL - INTA interrupt mapping control for PE0_INT_STS[AER_RC_ERR_INT_STS] * 0b0..Error is mapped to register bit * 0b1..Error is mapped to INTA interrupt */ #define SerDes_SS_PE0_GEN_CTRL_2_CFG_AER_RC_ERR_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_CFG_AER_RC_ERR_INT_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_CFG_AER_RC_ERR_INT_CTRL_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_PME_INT_CTRL_MASK (0x2U) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_PME_INT_CTRL_SHIFT (1U) /*! CFG_PME_INT_CTRL - INTA interrupt mapping control for PE0_INT_STS[PME_INT_STS] * 0b0..Error is mapped to register bit * 0b1..Error is mapped to INTA interrupt */ #define SerDes_SS_PE0_GEN_CTRL_2_CFG_PME_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_CFG_PME_INT_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_CFG_PME_INT_CTRL_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_HP_INT_CTRL_MASK (0x4U) #define SerDes_SS_PE0_GEN_CTRL_2_HP_INT_CTRL_SHIFT (2U) /*! HP_INT_CTRL - INTA interrupt mapping control for PE0_INT_STS[HP_INT_STS] * 0b0..Error is mapped to register bit * 0b1..Error is mapped to INTA interrupt */ #define SerDes_SS_PE0_GEN_CTRL_2_HP_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_HP_INT_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_HP_INT_CTRL_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_AUTO_BW_INT_CTRL_MASK (0x8U) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_AUTO_BW_INT_CTRL_SHIFT (3U) /*! CFG_LINK_AUTO_BW_INT_CTRL - INTA interrupt mapping control for PE0_INT_STS[LINK_AUTO_BW_MSI_STS] * 0b0..Error is mapped to register bit * 0b1..Error is mapped to INTA interrupt */ #define SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_AUTO_BW_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_AUTO_BW_INT_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_AUTO_BW_INT_CTRL_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_BW_MGT_INT_CTRL_MASK (0x10U) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_BW_MGT_INT_CTRL_SHIFT (4U) /*! CFG_BW_MGT_INT_CTRL - INTA interrupt mapping control for PE0_INT_STS[BW_MGT_MSI_STS] * 0b0..Error is mapped to register bit * 0b1..Error is mapped to INTA interrupt */ #define SerDes_SS_PE0_GEN_CTRL_2_CFG_BW_MGT_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_CFG_BW_MGT_INT_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_CFG_BW_MGT_INT_CTRL_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_EQ_REQ_INT_CTRL_MASK (0x20U) #define SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_EQ_REQ_INT_CTRL_SHIFT (5U) /*! CFG_LINK_EQ_REQ_INT_CTRL - INTA interrupt mapping control for PE0_INT_STS[LINK_EQ_REQ_INT_STS] * 0b0..Error is mapped to register bit * 0b1..Error is mapped to INTA interrupt */ #define SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_EQ_REQ_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_EQ_REQ_INT_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_CFG_LINK_EQ_REQ_INT_CTRL_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_MSTR_ACLK_UNGATE_MASK (0x100U) #define SerDes_SS_PE0_GEN_CTRL_2_MSTR_ACLK_UNGATE_SHIFT (8U) /*! MSTR_ACLK_UNGATE - AXI Master Clock Gating Control * 0b0..Gate * 0b1..Do not gate */ #define SerDes_SS_PE0_GEN_CTRL_2_MSTR_ACLK_UNGATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_MSTR_ACLK_UNGATE_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_MSTR_ACLK_UNGATE_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_SLV_ACLK_UNGATE_MASK (0x200U) #define SerDes_SS_PE0_GEN_CTRL_2_SLV_ACLK_UNGATE_SHIFT (9U) /*! SLV_ACLK_UNGATE - AXI Slave Clock Gating Control * 0b0..Gate * 0b1..Do not gate */ #define SerDes_SS_PE0_GEN_CTRL_2_SLV_ACLK_UNGATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_SLV_ACLK_UNGATE_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_SLV_ACLK_UNGATE_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_MSI_INT_CTRL_MASK (0x400U) #define SerDes_SS_PE0_GEN_CTRL_2_MSI_INT_CTRL_SHIFT (10U) /*! MSI_INT_CTRL - MSI interrupt mapping Control * 0b0..Interrupt is mapped to pcie0_msi_ctrl_int * 0b1..Interrupt is mapped to INTA interrupt */ #define SerDes_SS_PE0_GEN_CTRL_2_MSI_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_MSI_INT_CTRL_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_MSI_INT_CTRL_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_LTR_MSG_RCVD_INT_EN_MASK (0x800U) #define SerDes_SS_PE0_GEN_CTRL_2_LTR_MSG_RCVD_INT_EN_SHIFT (11U) /*! LTR_MSG_RCVD_INT_EN - Interrupt enable for LTR_MSG_RCVD * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_GEN_CTRL_2_LTR_MSG_RCVD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_LTR_MSG_RCVD_INT_EN_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_LTR_MSG_RCVD_INT_EN_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_PM_LINKST_ENTR_L1SUB_INT_EN_MASK (0x1000000U) #define SerDes_SS_PE0_GEN_CTRL_2_PM_LINKST_ENTR_L1SUB_INT_EN_SHIFT (24U) /*! PM_LINKST_ENTR_L1SUB_INT_EN - Interrupt enable for PM_LINKST_ENTR_L1SUB_STS * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_GEN_CTRL_2_PM_LINKST_ENTR_L1SUB_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_PM_LINKST_ENTR_L1SUB_INT_EN_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_PM_LINKST_ENTR_L1SUB_INT_EN_MASK) #define SerDes_SS_PE0_GEN_CTRL_2_FLRIE_MASK (0x20000000U) #define SerDes_SS_PE0_GEN_CTRL_2_FLRIE_SHIFT (29U) /*! FLRIE - Interrupt enable for FLR request PE0_ERR_STS[FLRIN_STS] * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_GEN_CTRL_2_FLRIE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_2_FLRIE_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_2_FLRIE_MASK) /*! @} */ /*! @name PE0_GEN_CTRL_3 - PCIe Controller 0 General Control 3 */ /*! @{ */ #define SerDes_SS_PE0_GEN_CTRL_3_LTSSM_EN_MASK (0x1U) #define SerDes_SS_PE0_GEN_CTRL_3_LTSSM_EN_SHIFT (0U) /*! LTSSM_EN - LTSSM Enable * 0b0..Hold LTSSM in the Detect state until your application is ready * 0b1..Allow LTSSM to continue link establishment and normal operation */ #define SerDes_SS_PE0_GEN_CTRL_3_LTSSM_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_3_LTSSM_EN_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_3_LTSSM_EN_MASK) #define SerDes_SS_PE0_GEN_CTRL_3_CRS_EN_MASK (0x2U) #define SerDes_SS_PE0_GEN_CTRL_3_CRS_EN_SHIFT (1U) /*! CRS_EN - Configuration Request Retry Status (CRS) Enable * 0b0..PCIe controller does not complete incoming configuration requests with a Configuration Request Retry Status. * 0b1..PCIe controller completes incoming configuration requests with a Configuration Request Retry Status. * Other incoming requests complete with unsupported request status. */ #define SerDes_SS_PE0_GEN_CTRL_3_CRS_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_3_CRS_EN_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_3_CRS_EN_MASK) #define SerDes_SS_PE0_GEN_CTRL_3_HOT_RESET_MASK (0x4U) #define SerDes_SS_PE0_GEN_CTRL_3_HOT_RESET_SHIFT (2U) /*! HOT_RESET - Hot Reset * 0b1..Trigger a hot reset */ #define SerDes_SS_PE0_GEN_CTRL_3_HOT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_3_HOT_RESET_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_3_HOT_RESET_MASK) #define SerDes_SS_PE0_GEN_CTRL_3_DIAG_CTRL_BUS_MASK (0xE000U) #define SerDes_SS_PE0_GEN_CTRL_3_DIAG_CTRL_BUS_SHIFT (13U) /*! DIAG_CTRL_BUS - Diagnostic Control Bus */ #define SerDes_SS_PE0_GEN_CTRL_3_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_3_DIAG_CTRL_BUS_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_3_DIAG_CTRL_BUS_MASK) /*! @} */ /*! @name PE0_GEN_CTRL_4 - PCIe Controller 0 General Control 4 */ /*! @{ */ #define SerDes_SS_PE0_GEN_CTRL_4_LTSSM_EN_CLR_MASK_MASK (0x40000000U) #define SerDes_SS_PE0_GEN_CTRL_4_LTSSM_EN_CLR_MASK_SHIFT (30U) /*! LTSSM_EN_CLR_MASK - LTSSM_EN Clear Mask * 0b0..LTSSM_EN does not change * 0b1..LTSSM_EN goes to its reset value */ #define SerDes_SS_PE0_GEN_CTRL_4_LTSSM_EN_CLR_MASK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_4_LTSSM_EN_CLR_MASK_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_4_LTSSM_EN_CLR_MASK_MASK) #define SerDes_SS_PE0_GEN_CTRL_4_CRS_EN_CLR_MASK_MASK (0x80000000U) #define SerDes_SS_PE0_GEN_CTRL_4_CRS_EN_CLR_MASK_SHIFT (31U) /*! CRS_EN_CLR_MASK - CRS_EN Clear Mask * 0b0..CRS_EN does not change * 0b1..CRS_EN goes to its reset value */ #define SerDes_SS_PE0_GEN_CTRL_4_CRS_EN_CLR_MASK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_GEN_CTRL_4_CRS_EN_CLR_MASK_SHIFT)) & SerDes_SS_PE0_GEN_CTRL_4_CRS_EN_CLR_MASK_MASK) /*! @} */ /*! @name PE0_PM_CTRL - PCIe Controller 0 PM Control */ /*! @{ */ #define SerDes_SS_PE0_PM_CTRL_PME_PF_INDEX_MASK (0x1FU) #define SerDes_SS_PE0_PM_CTRL_PME_PF_INDEX_SHIFT (0U) /*! PME_PF_INDEX - PF Index Of PM_PME Request And PM Status */ #define SerDes_SS_PE0_PM_CTRL_PME_PF_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_PME_PF_INDEX_SHIFT)) & SerDes_SS_PE0_PM_CTRL_PME_PF_INDEX_MASK) #define SerDes_SS_PE0_PM_CTRL_APP_L1SUB_DISABLE_MASK (0x80U) #define SerDes_SS_PE0_PM_CTRL_APP_L1SUB_DISABLE_SHIFT (7U) /*! APP_L1SUB_DISABLE - Disable L1 sub-states entry * 0b0..Entry to L1 sub-states is not gated * 0b1..Entry to L1 sub-states is gated */ #define SerDes_SS_PE0_PM_CTRL_APP_L1SUB_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_APP_L1SUB_DISABLE_SHIFT)) & SerDes_SS_PE0_PM_CTRL_APP_L1SUB_DISABLE_MASK) #define SerDes_SS_PE0_PM_CTRL_PM_PME_REQ_MASK (0x10000U) #define SerDes_SS_PE0_PM_CTRL_PM_PME_REQ_SHIFT (16U) /*! PM_PME_REQ - PM_PME Message Request */ #define SerDes_SS_PE0_PM_CTRL_PM_PME_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_PM_PME_REQ_SHIFT)) & SerDes_SS_PE0_PM_CTRL_PM_PME_REQ_MASK) #define SerDes_SS_PE0_PM_CTRL_ENTER_ASPM_L1_MASK (0x20000U) #define SerDes_SS_PE0_PM_CTRL_ENTER_ASPM_L1_SHIFT (17U) /*! ENTER_ASPM_L1 - Request To Enter ASPM State L1 * 0b0..No request to enter * 0b1..Explicit request to enter */ #define SerDes_SS_PE0_PM_CTRL_ENTER_ASPM_L1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_ENTER_ASPM_L1_SHIFT)) & SerDes_SS_PE0_PM_CTRL_ENTER_ASPM_L1_MASK) #define SerDes_SS_PE0_PM_CTRL_EXIT_ASPM_L1_MASK (0x40000U) #define SerDes_SS_PE0_PM_CTRL_EXIT_ASPM_L1_SHIFT (18U) /*! EXIT_ASPM_L1 - Request To Exit ASPM State L1 * 0b0..No request to exit * 0b1..Explicit request to exit */ #define SerDes_SS_PE0_PM_CTRL_EXIT_ASPM_L1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_EXIT_ASPM_L1_SHIFT)) & SerDes_SS_PE0_PM_CTRL_EXIT_ASPM_L1_MASK) #define SerDes_SS_PE0_PM_CTRL_READY_ENTER_L23_MASK (0x80000U) #define SerDes_SS_PE0_PM_CTRL_READY_ENTER_L23_SHIFT (19U) /*! READY_ENTER_L23 - Ready To Enter L23 * 0b0..Not ready * 0b1..Ready */ #define SerDes_SS_PE0_PM_CTRL_READY_ENTER_L23(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_READY_ENTER_L23_SHIFT)) & SerDes_SS_PE0_PM_CTRL_READY_ENTER_L23_MASK) #define SerDes_SS_PE0_PM_CTRL_APP_CLK_REQ_MASK (0x100000U) #define SerDes_SS_PE0_PM_CTRL_APP_CLK_REQ_SHIFT (20U) /*! APP_CLK_REQ - Wake Up Reference Clock * 0b0..No request to wake up * 0b1..Explicit request to wake up */ #define SerDes_SS_PE0_PM_CTRL_APP_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_APP_CLK_REQ_SHIFT)) & SerDes_SS_PE0_PM_CTRL_APP_CLK_REQ_MASK) #define SerDes_SS_PE0_PM_CTRL_APP_CLK_PM_EN_MASK (0x200000U) #define SerDes_SS_PE0_PM_CTRL_APP_CLK_PM_EN_SHIFT (21U) /*! APP_CLK_PM_EN - Clock PM Feature Enable * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_PM_CTRL_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_APP_CLK_PM_EN_SHIFT)) & SerDes_SS_PE0_PM_CTRL_APP_CLK_PM_EN_MASK) #define SerDes_SS_PE0_PM_CTRL_BEACON_INT_EN_MASK (0x80000000U) #define SerDes_SS_PE0_PM_CTRL_BEACON_INT_EN_SHIFT (31U) /*! BEACON_INT_EN - Beacon Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_PM_CTRL_BEACON_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_CTRL_BEACON_INT_EN_SHIFT)) & SerDes_SS_PE0_PM_CTRL_BEACON_INT_EN_MASK) /*! @} */ /*! @name PE0_PM_STS - PCIe Controller 0 PM Status */ /*! @{ */ #define SerDes_SS_PE0_PM_STS_PM_DSTATE_MASK (0x7U) #define SerDes_SS_PE0_PM_STS_PM_DSTATE_SHIFT (0U) /*! PM_DSTATE - Current Power Management D-State * 0b000..D0 * 0b001..D1 * 0b010..D2 * 0b011..D3 * 0b100..Uninitialized * *.. */ #define SerDes_SS_PE0_PM_STS_PM_DSTATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_DSTATE_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_DSTATE_MASK) #define SerDes_SS_PE0_PM_STS_PM_PME_EN_MASK (0x8U) #define SerDes_SS_PE0_PM_STS_PM_PME_EN_SHIFT (3U) /*! PM_PME_EN - PME Enable Mirror */ #define SerDes_SS_PE0_PM_STS_PM_PME_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_PME_EN_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_PME_EN_MASK) #define SerDes_SS_PE0_PM_STS_PM_STATUS_MASK (0x10U) #define SerDes_SS_PE0_PM_STS_PM_STATUS_SHIFT (4U) /*! PM_STATUS - PME Status Mirror */ #define SerDes_SS_PE0_PM_STS_PM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_STATUS_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_STATUS_MASK) #define SerDes_SS_PE0_PM_STS_L1_SUBSTATE_FSM_MASK (0xE0U) #define SerDes_SS_PE0_PM_STS_L1_SUBSTATE_FSM_SHIFT (5U) /*! L1_SUBSTATE_FSM - Power management L1 sub-states FSM state * 0b000..S_L1_U: idle state * 0b001..S_L1_0: wait for aux_clk_active * 0b010..S_L1_0_WAIT4_ACK: wait for pclkack * 0b011..S_L1_0_WAIT4_CLKREQ: wait for clkreq * 0b100..S_L1_N_ENTRY: check clkreq_in_n is de-asserted for t_power_off time (only for L1.2, reduces to one cycle for L1.1) * 0b101..S_L1_N: L1 substate, turn off txcommonmode circuits (L1.2 only) and rx electrical idle detection circuits * 0b110..S_L1_N_EXIT: locally/remotely initiated exit, assert pclkreq, wait for pclkack * 0b111..S_L1_N_ABORT: wait for pclkack when aborting an attempt to enter L1_N */ #define SerDes_SS_PE0_PM_STS_L1_SUBSTATE_FSM(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_L1_SUBSTATE_FSM_SHIFT)) & SerDes_SS_PE0_PM_STS_L1_SUBSTATE_FSM_MASK) #define SerDes_SS_PE0_PM_STS_PM_CURNT_STATE_MASK (0x700U) #define SerDes_SS_PE0_PM_STS_PM_CURNT_STATE_SHIFT (8U) /*! PM_CURNT_STATE - PM Controller's Current Power State * 0b000..L0 and others * 0b001..L0S * 0b010..L1 * 0b011..L2 * 0b100..L3 */ #define SerDes_SS_PE0_PM_STS_PM_CURNT_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_CURNT_STATE_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_CURNT_STATE_MASK) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L0S_MASK (0x800U) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L0S_SHIFT (11U) /*! PM_LINKST_IN_L0S - Power Management In L0s State * 0b0..Not in L0s * 0b1..In L0s */ #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L0S(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L0S_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L0S_MASK) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1_MASK (0x1000U) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1_SHIFT (12U) /*! PM_LINKST_IN_L1 - Power Management In L1 State * 0b0..Not in L1 * 0b1..In L1 */ #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1_MASK) #define SerDes_SS_PE0_PM_STS_PM_ASPM_L1_ENTR_RDY_MASK (0x2000U) #define SerDes_SS_PE0_PM_STS_PM_ASPM_L1_ENTR_RDY_SHIFT (13U) /*! PM_ASPM_L1_ENTR_RDY - Power Management L1 Entry Ready */ #define SerDes_SS_PE0_PM_STS_PM_ASPM_L1_ENTR_RDY(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_ASPM_L1_ENTR_RDY_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_ASPM_L1_ENTR_RDY_MASK) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L2_MASK (0x4000U) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L2_SHIFT (14U) /*! PM_LINKST_IN_L2 - Power Management in L2 State * 0b0..Not in L2 * 0b1..In L2 */ #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L2_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L2_MASK) #define SerDes_SS_PE0_PM_STS_PM_LINKST_L2_EXIT_MASK (0x8000U) #define SerDes_SS_PE0_PM_STS_PM_LINKST_L2_EXIT_SHIFT (15U) /*! PM_LINKST_L2_EXIT - Power Management is Exiting L2 State * 0b0..Not in L2 exit * 0b1..In L2 exit */ #define SerDes_SS_PE0_PM_STS_PM_LINKST_L2_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_LINKST_L2_EXIT_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_LINKST_L2_EXIT_MASK) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1SUB_STS_MASK (0x10000U) #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1SUB_STS_SHIFT (16U) /*! PM_LINKST_IN_L1SUB_STS - Power management is in L1 substate */ #define SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1SUB_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1SUB_STS_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_LINKST_IN_L1SUB_STS_MASK) #define SerDes_SS_PE0_PM_STS_PM_MASTER_STATE_MASK (0x1F00000U) #define SerDes_SS_PE0_PM_STS_PM_MASTER_STATE_SHIFT (20U) /*! PM_MASTER_STATE - Power management master FSM state */ #define SerDes_SS_PE0_PM_STS_PM_MASTER_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_MASTER_STATE_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_MASTER_STATE_MASK) #define SerDes_SS_PE0_PM_STS_PM_SLAVE_STATE_MASK (0x3E000000U) #define SerDes_SS_PE0_PM_STS_PM_SLAVE_STATE_SHIFT (25U) /*! PM_SLAVE_STATE - Power management slave FSM state */ #define SerDes_SS_PE0_PM_STS_PM_SLAVE_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_PM_STS_PM_SLAVE_STATE_SHIFT)) & SerDes_SS_PE0_PM_STS_PM_SLAVE_STATE_MASK) /*! @} */ /*! @name PE0_TX_LTR_MSG_LATENCY - PCIe Controller LTR message latency */ /*! @{ */ #define SerDes_SS_PE0_TX_LTR_MSG_LATENCY_LTR_MSG_LATENCY_MASK (0xFFFFFFFFU) #define SerDes_SS_PE0_TX_LTR_MSG_LATENCY_LTR_MSG_LATENCY_SHIFT (0U) /*! LTR_MSG_LATENCY - LTR message to be sent. */ #define SerDes_SS_PE0_TX_LTR_MSG_LATENCY_LTR_MSG_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_LTR_MSG_LATENCY_LTR_MSG_LATENCY_SHIFT)) & SerDes_SS_PE0_TX_LTR_MSG_LATENCY_LTR_MSG_LATENCY_MASK) /*! @} */ /*! @name PE0_TX_LTR_MSG_FUNC_NUM - Function number that is requesting to send an LTR message. */ /*! @{ */ #define SerDes_SS_PE0_TX_LTR_MSG_FUNC_NUM_LTR_MSG_FUNC_NUM_MASK (0x7U) #define SerDes_SS_PE0_TX_LTR_MSG_FUNC_NUM_LTR_MSG_FUNC_NUM_SHIFT (0U) /*! LTR_MSG_FUNC_NUM - Function number that is requesting to send an LTR message. Function numbering starts at '0'. */ #define SerDes_SS_PE0_TX_LTR_MSG_FUNC_NUM_LTR_MSG_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_LTR_MSG_FUNC_NUM_LTR_MSG_FUNC_NUM_SHIFT)) & SerDes_SS_PE0_TX_LTR_MSG_FUNC_NUM_LTR_MSG_FUNC_NUM_MASK) /*! @} */ /*! @name PE0_TX_MSG_HDR_1 - PCIe Controller 0 Transmit Message Header 1 */ /*! @{ */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_LENGTH_MASK (0x3FFU) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_LENGTH_SHIFT (0U) /*! MSG_HDR_LENGTH - Tied to 0. */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_LENGTH_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_LENGTH_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_ATTR_MASK (0x3000U) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_ATTR_SHIFT (12U) /*! MSG_HDR_ATTR - Attribute[1:0], Relaxing Ordering and No Snoop */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_ATTR_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_ATTR_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_EP_MASK (0x4000U) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_EP_SHIFT (14U) /*! MSG_HDR_EP - Poisoned TLP (EP) */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_EP(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_EP_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_EP_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TD_MASK (0x8000U) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TD_SHIFT (15U) /*! MSG_HDR_TD - TLP Digest (TD) */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TD_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TD_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TC_MASK (0x700000U) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TC_SHIFT (20U) /*! MSG_HDR_TC - Traffic Class */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TC(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TC_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TC_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TYPE_MASK (0x1F000000U) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TYPE_SHIFT (24U) /*! MSG_HDR_TYPE - Type Field */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TYPE_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_TYPE_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_FM_MASK (0x60000000U) #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_FM_SHIFT (29U) /*! MSG_HDR_FM - Format Field */ #define SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_FM(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_FM_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_1_MSG_HDR_FM_MASK) /*! @} */ /*! @name PE0_TX_MSG_HDR_2 - PCIe Controller 0 Transmit Message Header 2 */ /*! @{ */ #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE7_MASK (0xFFU) #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE7_SHIFT (0U) /*! MSG_HDR_BYTE7 - Message Code, Byte 7 */ #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE7(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE7_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE7_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE6_MASK (0xFF00U) #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE6_SHIFT (8U) /*! MSG_HDR_BYTE6 - Message Tag, Byte 6 */ #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE6(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE6_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE6_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE5_MASK (0xFF0000U) #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE5_SHIFT (16U) /*! MSG_HDR_BYTE5 - Requester ID[7:0], Byte 5 */ #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE5(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE5_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE5_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE4_MASK (0xFF000000U) #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE4_SHIFT (24U) /*! MSG_HDR_BYTE4 - Requester ID[15:8], Byte 4 */ #define SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE4(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE4_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_2_MSG_HDR_BYTE4_MASK) /*! @} */ /*! @name PE0_TX_MSG_HDR_3 - PCIe Controller 0 Transmit Message Header 3 */ /*! @{ */ #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE11_MASK (0xFFU) #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE11_SHIFT (0U) /*! MSG_HDR_BYTE11 - Byte 11 */ #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE11(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE11_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE11_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE10_MASK (0xFF00U) #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE10_SHIFT (8U) /*! MSG_HDR_BYTE10 - Byte 10 */ #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE10(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE10_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE10_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE9_MASK (0xFF0000U) #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE9_SHIFT (16U) /*! MSG_HDR_BYTE9 - Byte 9 */ #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE9(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE9_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE9_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE8_MASK (0xFF000000U) #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE8_SHIFT (24U) /*! MSG_HDR_BYTE8 - Byte 8 */ #define SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE8(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE8_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_3_MSG_HDR_BYTE8_MASK) /*! @} */ /*! @name PE0_TX_MSG_HDR_4 - PCIe controller 0 transmit message header 4 */ /*! @{ */ #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE15_MASK (0xFFU) #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE15_SHIFT (0U) /*! MSG_HDR_BYTE15 - Byte 15 */ #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE15(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE15_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE15_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE14_MASK (0xFF00U) #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE14_SHIFT (8U) /*! MSG_HDR_BYTE14 - Byte 14 */ #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE14(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE14_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE14_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE13_MASK (0xFF0000U) #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE13_SHIFT (16U) /*! MSG_HDR_BYTE13 - Byte 13 */ #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE13(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE13_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE13_MASK) #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE12_MASK (0xFF000000U) #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE12_SHIFT (24U) /*! MSG_HDR_BYTE12 - Byte 12 */ #define SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE12(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE12_SHIFT)) & SerDes_SS_PE0_TX_MSG_HDR_4_MSG_HDR_BYTE12_MASK) /*! @} */ /*! @name PE0_TX_MSG_REQ - PCIe Controller 0 Transmit Message Request */ /*! @{ */ #define SerDes_SS_PE0_TX_MSG_REQ_LTR_MSG_REQ_MASK (0x10000U) #define SerDes_SS_PE0_TX_MSG_REQ_LTR_MSG_REQ_SHIFT (16U) /*! LTR_MSG_REQ - Request to send an LTR message * 0b0..LTR message request is not pending * 0b1..Send LTR message */ #define SerDes_SS_PE0_TX_MSG_REQ_LTR_MSG_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_REQ_LTR_MSG_REQ_SHIFT)) & SerDes_SS_PE0_TX_MSG_REQ_LTR_MSG_REQ_MASK) #define SerDes_SS_PE0_TX_MSG_REQ_VEN_MSG_REQ_MASK (0x20000U) #define SerDes_SS_PE0_TX_MSG_REQ_VEN_MSG_REQ_SHIFT (17U) /*! VEN_MSG_REQ - Vendor-Defined Message Request * 0b0..Normal operation * 0b1..Trigger a vendor-defined message request */ #define SerDes_SS_PE0_TX_MSG_REQ_VEN_MSG_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_REQ_VEN_MSG_REQ_SHIFT)) & SerDes_SS_PE0_TX_MSG_REQ_VEN_MSG_REQ_MASK) #define SerDes_SS_PE0_TX_MSG_REQ_PME_TURN_OFF_REQ_MASK (0x80000U) #define SerDes_SS_PE0_TX_MSG_REQ_PME_TURN_OFF_REQ_SHIFT (19U) /*! PME_TURN_OFF_REQ - PME_Turn_Off Message Request */ #define SerDes_SS_PE0_TX_MSG_REQ_PME_TURN_OFF_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_REQ_PME_TURN_OFF_REQ_SHIFT)) & SerDes_SS_PE0_TX_MSG_REQ_PME_TURN_OFF_REQ_MASK) #define SerDes_SS_PE0_TX_MSG_REQ_UNLOCK_REQ_MASK (0x100000U) #define SerDes_SS_PE0_TX_MSG_REQ_UNLOCK_REQ_SHIFT (20U) /*! UNLOCK_REQ - Unlock message */ #define SerDes_SS_PE0_TX_MSG_REQ_UNLOCK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_TX_MSG_REQ_UNLOCK_REQ_SHIFT)) & SerDes_SS_PE0_TX_MSG_REQ_UNLOCK_REQ_MASK) /*! @} */ /*! @name PE0_RX_SLOT_PWR_PAYLD - DW data of Set_Slot_Power_Limit message */ /*! @{ */ #define SerDes_SS_PE0_RX_SLOT_PWR_PAYLD_SLOT_PWR_PAYLD_MASK (0xFFFFFFFFU) #define SerDes_SS_PE0_RX_SLOT_PWR_PAYLD_SLOT_PWR_PAYLD_SHIFT (0U) /*! SLOT_PWR_PAYLD - MDW data of Set_Slot_Power_Limit message */ #define SerDes_SS_PE0_RX_SLOT_PWR_PAYLD_SLOT_PWR_PAYLD(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_SLOT_PWR_PAYLD_SLOT_PWR_PAYLD_SHIFT)) & SerDes_SS_PE0_RX_SLOT_PWR_PAYLD_SLOT_PWR_PAYLD_MASK) /*! @} */ /*! @name PE0_RX_CURR_LTR_LATENCY - Current LTR values */ /*! @{ */ #define SerDes_SS_PE0_RX_CURR_LTR_LATENCY_CURR_LTR_LATENCY_MASK (0xFFFFFFFFU) #define SerDes_SS_PE0_RX_CURR_LTR_LATENCY_CURR_LTR_LATENCY_SHIFT (0U) /*! CURR_LTR_LATENCY - The current LTR values reported and in-use by the downstream device. */ #define SerDes_SS_PE0_RX_CURR_LTR_LATENCY_CURR_LTR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_CURR_LTR_LATENCY_CURR_LTR_LATENCY_SHIFT)) & SerDes_SS_PE0_RX_CURR_LTR_LATENCY_CURR_LTR_LATENCY_MASK) /*! @} */ /*! @name PE0_RX_MSG_HDR_1 - PCIe Controller 0 Receive Message Header 1 */ /*! @{ */ #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE3_MASK (0xFFU) #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE3_SHIFT (0U) /*! MSG_HDR_BYTE3 - Byte 3 */ #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE3_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE3_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE2_MASK (0xFF00U) #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE2_SHIFT (8U) /*! MSG_HDR_BYTE2 - Byte 2 */ #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE2_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE2_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE1_MASK (0xFF0000U) #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE1_SHIFT (16U) /*! MSG_HDR_BYTE1 - Byte 1 */ #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE1_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE1_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE0_MASK (0xFF000000U) #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE0_SHIFT (24U) /*! MSG_HDR_BYTE0 - Byte 0 */ #define SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE0(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE0_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_1_MSG_HDR_BYTE0_MASK) /*! @} */ /*! @name PE0_RX_MSG_HDR_2 - PCIe Controller 0 Receive Message Header 2 */ /*! @{ */ #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE7_MASK (0xFFU) #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE7_SHIFT (0U) /*! MSG_HDR_BYTE7 - Byte 7 */ #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE7(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE7_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE7_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE6_MASK (0xFF00U) #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE6_SHIFT (8U) /*! MSG_HDR_BYTE6 - Byte 6 */ #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE6(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE6_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE6_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE5_MASK (0xFF0000U) #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE5_SHIFT (16U) /*! MSG_HDR_BYTE5 - Byte 5 */ #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE5(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE5_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE5_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE4_MASK (0xFF000000U) #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE4_SHIFT (24U) /*! MSG_HDR_BYTE4 - Byte 4 */ #define SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE4(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE4_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_2_MSG_HDR_BYTE4_MASK) /*! @} */ /*! @name PE0_RX_MSG_HDR_3 - PCIe Controller 0 Receive Message Header 3 */ /*! @{ */ #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE11_MASK (0xFFU) #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE11_SHIFT (0U) /*! MSG_HDR_BYTE11 - Byte 11 */ #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE11(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE11_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE11_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE10_MASK (0xFF00U) #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE10_SHIFT (8U) /*! MSG_HDR_BYTE10 - Byte 10 */ #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE10(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE10_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE10_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE9_MASK (0xFF0000U) #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE9_SHIFT (16U) /*! MSG_HDR_BYTE9 - Byte 9 */ #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE9(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE9_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE9_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE8_MASK (0xFF000000U) #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE8_SHIFT (24U) /*! MSG_HDR_BYTE8 - Byte 8 */ #define SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE8(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE8_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_3_MSG_HDR_BYTE8_MASK) /*! @} */ /*! @name PE0_RX_MSG_HDR_4 - PCIe Controller 0 Receive Message Header 4 */ /*! @{ */ #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE15_MASK (0xFFU) #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE15_SHIFT (0U) /*! MSG_HDR_BYTE15 - Byte 15 */ #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE15(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE15_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE15_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE14_MASK (0xFF00U) #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE14_SHIFT (8U) /*! MSG_HDR_BYTE14 - Byte 14 */ #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE14(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE14_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE14_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE13_MASK (0xFF0000U) #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE13_SHIFT (16U) /*! MSG_HDR_BYTE13 - Byte 13 */ #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE13(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE13_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE13_MASK) #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE12_MASK (0xFF000000U) #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE12_SHIFT (24U) /*! MSG_HDR_BYTE12 - Byte 12 */ #define SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE12(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE12_SHIFT)) & SerDes_SS_PE0_RX_MSG_HDR_4_MSG_HDR_BYTE12_MASK) /*! @} */ /*! @name PE0_RX_MSG_STS - PCIe Controller 0 Receive Message Status */ /*! @{ */ #define SerDes_SS_PE0_RX_MSG_STS_LTR_MSG_RCVD_STS_MASK (0x1U) #define SerDes_SS_PE0_RX_MSG_STS_LTR_MSG_RCVD_STS_SHIFT (0U) /*! LTR_MSG_RCVD_STS - LTR message receive indication * 0b0..No new LTR message is received * 0b1..Controller has received and LTR message */ #define SerDes_SS_PE0_RX_MSG_STS_LTR_MSG_RCVD_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_LTR_MSG_RCVD_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_LTR_MSG_RCVD_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_SET_SLOT_PWR_RCVD_STS_MASK (0x2U) #define SerDes_SS_PE0_RX_MSG_STS_SET_SLOT_PWR_RCVD_STS_SHIFT (1U) /*! SET_SLOT_PWR_RCVD_STS - Set_Slot_Power_Limit message * 0b0..Message not received * 0b1..Message received */ #define SerDes_SS_PE0_RX_MSG_STS_SET_SLOT_PWR_RCVD_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_SET_SLOT_PWR_RCVD_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_SET_SLOT_PWR_RCVD_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_PME_TO_ACK_STS_MASK (0x800U) #define SerDes_SS_PE0_RX_MSG_STS_PME_TO_ACK_STS_SHIFT (11U) /*! PME_TO_ACK_STS - PME_TO_Ack message status * 0b0..Not captured * 0b1..Captured */ #define SerDes_SS_PE0_RX_MSG_STS_PME_TO_ACK_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_PME_TO_ACK_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_PME_TO_ACK_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_PM_PME_STS_MASK (0x1000U) #define SerDes_SS_PE0_RX_MSG_STS_PM_PME_STS_SHIFT (12U) /*! PM_PME_STS - PM_PME Message Status * 0b0..Not captured * 0b1..Captured */ #define SerDes_SS_PE0_RX_MSG_STS_PM_PME_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_PM_PME_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_PM_PME_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE0_STS_MASK (0x20000U) #define SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE0_STS_SHIFT (17U) /*! VDM_TYPE0_STS - Vendor-Defined Type 0 Message Status * 0b0..Not captured * 0b1..Captured */ #define SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE0_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE0_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE0_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE1_STS_MASK (0x40000U) #define SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE1_STS_SHIFT (18U) /*! VDM_TYPE1_STS - Vendor-Defined Type 1 Message Status * 0b0..Not captured * 0b1..Captured */ #define SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE1_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE1_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_VDM_TYPE1_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_PME_TURN_OFF_STS_MASK (0x80000U) #define SerDes_SS_PE0_RX_MSG_STS_PME_TURN_OFF_STS_SHIFT (19U) /*! PME_TURN_OFF_STS - PME_Turn_Off Message Status * 0b0..Not captured * 0b1..Captured */ #define SerDes_SS_PE0_RX_MSG_STS_PME_TURN_OFF_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_PME_TURN_OFF_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_PME_TURN_OFF_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_UNLOCK_STS_MASK (0x100000U) #define SerDes_SS_PE0_RX_MSG_STS_UNLOCK_STS_SHIFT (20U) /*! UNLOCK_STS - Unlock Message Status * 0b0..Not captured * 0b1..Captured */ #define SerDes_SS_PE0_RX_MSG_STS_UNLOCK_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_UNLOCK_STS_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_UNLOCK_STS_MASK) #define SerDes_SS_PE0_RX_MSG_STS_MSGQ_OVERFLOW_MASK (0x80000000U) #define SerDes_SS_PE0_RX_MSG_STS_MSGQ_OVERFLOW_SHIFT (31U) /*! MSGQ_OVERFLOW - Receive Message Queue Overflow Status */ #define SerDes_SS_PE0_RX_MSG_STS_MSGQ_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_STS_MSGQ_OVERFLOW_SHIFT)) & SerDes_SS_PE0_RX_MSG_STS_MSGQ_OVERFLOW_MASK) /*! @} */ /*! @name PE0_RX_MSG_CAP_CTRL - PCIe Controller 0 Receive Message Capture Control */ /*! @{ */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TO_ACK_MASK (0x800U) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TO_ACK_SHIFT (11U) /*! CAP_PME_TO_ACK - Capture PME_TO_Ack Message In Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TO_ACK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TO_ACK_SHIFT)) & SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TO_ACK_MASK) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PM_PME_MASK (0x1000U) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PM_PME_SHIFT (12U) /*! CAP_PM_PME - Capture PM_PME Message In Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PM_PME(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PM_PME_SHIFT)) & SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PM_PME_MASK) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_LTR_MSG_MASK (0x10000U) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_LTR_MSG_SHIFT (16U) /*! CAP_LTR_MSG - Received message header capture enable for LTR messages. * 0b0..Disable Header capture * 0b1..Enable capture enabled */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_LTR_MSG(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_LTR_MSG_SHIFT)) & SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_LTR_MSG_MASK) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE0_MASK (0x20000U) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE0_SHIFT (17U) /*! CAP_VDM_TYPE0 - Capture Vendor-Defined Type 0 Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE0(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE0_SHIFT)) & SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE0_MASK) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE1_MASK (0x40000U) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE1_SHIFT (18U) /*! CAP_VDM_TYPE1 - Capture Vendor-Defined Type 1 Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE1_SHIFT)) & SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_VDM_TYPE1_MASK) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TURN_OFF_MASK (0x80000U) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TURN_OFF_SHIFT (19U) /*! CAP_PME_TURN_OFF - Capture PME_Turn_Off Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TURN_OFF(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TURN_OFF_SHIFT)) & SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_PME_TURN_OFF_MASK) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_UNLOCK_MASK (0x100000U) #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_UNLOCK_SHIFT (20U) /*! CAP_UNLOCK - Capture Unlock message in received Message Header register. * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_UNLOCK_SHIFT)) & SerDes_SS_PE0_RX_MSG_CAP_CTRL_CAP_UNLOCK_MASK) /*! @} */ /*! @name PE0_RX_MSG_INT_CTRL - PCIe Controller 0 Receive Message Interrupt Control */ /*! @{ */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TO_ACK_INT_EN_MASK (0x800U) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TO_ACK_INT_EN_SHIFT (11U) /*! PME_TO_ACK_INT_EN - Interrupt Enable when PME_TO_Ack Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TO_ACK_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TO_ACK_INT_EN_SHIFT)) & SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TO_ACK_INT_EN_MASK) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PM_PME_INT_EN_MASK (0x1000U) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PM_PME_INT_EN_SHIFT (12U) /*! PM_PME_INT_EN - Interrupt Enable when PM_PME Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PM_PME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_INT_CTRL_PM_PME_INT_EN_SHIFT)) & SerDes_SS_PE0_RX_MSG_INT_CTRL_PM_PME_INT_EN_MASK) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE0_INT_EN_MASK (0x20000U) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE0_INT_EN_SHIFT (17U) /*! VDM_TYPE0_INT_EN - Interrupt Enable when Vendor-Defined Type 0 Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE0_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE0_INT_EN_SHIFT)) & SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE0_INT_EN_MASK) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE1_INT_EN_MASK (0x40000U) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE1_INT_EN_SHIFT (18U) /*! VDM_TYPE1_INT_EN - Interrupt Enable when Vendor-Defined Type 1 Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE1_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE1_INT_EN_SHIFT)) & SerDes_SS_PE0_RX_MSG_INT_CTRL_VDM_TYPE1_INT_EN_MASK) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TURN_OFF_INT_EN_MASK (0x80000U) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TURN_OFF_INT_EN_SHIFT (19U) /*! PME_TURN_OFF_INT_EN - Interrupt Enable when PME_Turn_Off Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TURN_OFF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TURN_OFF_INT_EN_SHIFT)) & SerDes_SS_PE0_RX_MSG_INT_CTRL_PME_TURN_OFF_INT_EN_MASK) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_UNLOCK_INT_EN_MASK (0x100000U) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_UNLOCK_INT_EN_SHIFT (20U) /*! UNLOCK_INT_EN - Interrupt Enable when Unlock Message in Received Message Header Register * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_UNLOCK_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_INT_CTRL_UNLOCK_INT_EN_SHIFT)) & SerDes_SS_PE0_RX_MSG_INT_CTRL_UNLOCK_INT_EN_MASK) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_MSGQ_OVERFLOW_INT_EN_MASK (0x80000000U) #define SerDes_SS_PE0_RX_MSG_INT_CTRL_MSGQ_OVERFLOW_INT_EN_SHIFT (31U) /*! MSGQ_OVERFLOW_INT_EN - Interrupt Enable when Message Queue Overflows * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_RX_MSG_INT_CTRL_MSGQ_OVERFLOW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_RX_MSG_INT_CTRL_MSGQ_OVERFLOW_INT_EN_SHIFT)) & SerDes_SS_PE0_RX_MSG_INT_CTRL_MSGQ_OVERFLOW_INT_EN_MASK) /*! @} */ /*! @name PE0_LINK_DBG_1 - PCIe Controller 0 Link Debug 1 */ /*! @{ */ #define SerDes_SS_PE0_LINK_DBG_1_RECEIVER_DETECTED_MASK (0x1U) #define SerDes_SS_PE0_LINK_DBG_1_RECEIVER_DETECTED_SHIFT (0U) /*! RECEIVER_DETECTED - Receiver Detected On Lanes */ #define SerDes_SS_PE0_LINK_DBG_1_RECEIVER_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_1_RECEIVER_DETECTED_SHIFT)) & SerDes_SS_PE0_LINK_DBG_1_RECEIVER_DETECTED_MASK) #define SerDes_SS_PE0_LINK_DBG_1_SYMBOL_LOCK_MASK (0x10000U) #define SerDes_SS_PE0_LINK_DBG_1_SYMBOL_LOCK_SHIFT (16U) /*! SYMBOL_LOCK - Symbol Lock */ #define SerDes_SS_PE0_LINK_DBG_1_SYMBOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_1_SYMBOL_LOCK_SHIFT)) & SerDes_SS_PE0_LINK_DBG_1_SYMBOL_LOCK_MASK) /*! @} */ /*! @name PE0_LINK_DBG_2 - PCIe Controller 0 Link Debug 2 */ /*! @{ */ #define SerDes_SS_PE0_LINK_DBG_2_SMLH_LTSSM_STATE_MASK (0x3FU) #define SerDes_SS_PE0_LINK_DBG_2_SMLH_LTSSM_STATE_SHIFT (0U) /*! SMLH_LTSSM_STATE - LTSSM State * 0b000000..S_DETECT_QUIET * 0b000001..S_DETECT_ACT * 0b000010..S_POLL_ACTIVE * 0b000011..S_POLL_COMPLIANCE * 0b000100..S_POLL_CONFIG * 0b000101..S_PRE_DETECT_QUIET * 0b000110..S_DETECT_WAIT * 0b000111..S_CFG_LINKWD_START * 0b001000..S_CFG_LINKWD_ACEPT * 0b001001..S_CFG_LANENUM_WAI * 0b001010..S_CFG_LANENUM_ACEPT * 0b001011..S_CFG_COMPLETE * 0b001100..S_CFG_IDLE * 0b001101..S_RCVRY_LOCK * 0b001110..S_RCVRY_SPEED * 0b001111..S_RCVRY_RCVRCFG * 0b010000..S_RCVRY_IDLE * 0b010001..S_L0 * 0b010010..S_L0S * 0b010011..S_L123_SEND_EIDLE * 0b010100..S_L1_IDLE * 0b010101..S_L2_IDLE * 0b010110..S_L2_WAKE * 0b010111..S_DISABLED_ENTRY * 0b011000..S_DISABLED_IDLE * 0b011001..S_DISABLED * 0b011010..S_LPBK_ENTRY * 0b011011..S_LPBK_ACTIVE * 0b011100..S_LPBK_EXIT * 0b011101..S_LPBK_EXIT_TIMEOUT * 0b011110..S_HOT_RESET_ENTRY * 0b011111..S_HOT_RESET * 0b100000..S_RCVRY_EQ0 * 0b100001..S_RCVRY_EQ1 * 0b100010..S_RCVRY_EQ2 * 0b100011..S_RCVRY_EQ3 */ #define SerDes_SS_PE0_LINK_DBG_2_SMLH_LTSSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_SMLH_LTSSM_STATE_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_SMLH_LTSSM_STATE_MASK) #define SerDes_SS_PE0_LINK_DBG_2_SMLH_LINK_UP_MASK (0x40U) #define SerDes_SS_PE0_LINK_DBG_2_SMLH_LINK_UP_SHIFT (6U) /*! SMLH_LINK_UP - PHY Link Up or Down Indicator * 0b0..Down * 0b1..Up */ #define SerDes_SS_PE0_LINK_DBG_2_SMLH_LINK_UP(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_SMLH_LINK_UP_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_SMLH_LINK_UP_MASK) #define SerDes_SS_PE0_LINK_DBG_2_RDLH_LINK_UP_MASK (0x80U) #define SerDes_SS_PE0_LINK_DBG_2_RDLH_LINK_UP_SHIFT (7U) /*! RDLH_LINK_UP - Data Link Layer Up or Down Indicator */ #define SerDes_SS_PE0_LINK_DBG_2_RDLH_LINK_UP(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_RDLH_LINK_UP_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_RDLH_LINK_UP_MASK) #define SerDes_SS_PE0_LINK_DBG_2_RATE_MASK (0x300U) #define SerDes_SS_PE0_LINK_DBG_2_RATE_SHIFT (8U) /*! RATE - Link Signaling Rate * 0b00..2.5 GT/s * 0b01..5.0 GT/s * 0b10..8.0 GT/s * 0b11..Reserved */ #define SerDes_SS_PE0_LINK_DBG_2_RATE(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_RATE_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_RATE_MASK) #define SerDes_SS_PE0_LINK_DBG_2_PHY_POWRDOWN_MASK (0x1C00U) #define SerDes_SS_PE0_LINK_DBG_2_PHY_POWRDOWN_SHIFT (10U) /*! PHY_POWRDOWN - PHY Power State * 0b000..P0 (L0): Normal * 0b001..P0s (L0s): Low recovery time, power saving * 0b010..P1 (L1): Longer recovery time, additional power saving * 0b011..P2 (L2): Lowest power state * *.. */ #define SerDes_SS_PE0_LINK_DBG_2_PHY_POWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_PHY_POWRDOWN_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_PHY_POWRDOWN_MASK) #define SerDes_SS_PE0_LINK_DBG_2_VC0_Q_NOT_EMPTY_MASK (0x10000U) #define SerDes_SS_PE0_LINK_DBG_2_VC0_Q_NOT_EMPTY_SHIFT (16U) /*! VC0_Q_NOT_EMPTY - VC0 Queue Not Empty * 0b0..Empty * 0b1..Not empty */ #define SerDes_SS_PE0_LINK_DBG_2_VC0_Q_NOT_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_VC0_Q_NOT_EMPTY_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_VC0_Q_NOT_EMPTY_MASK) #define SerDes_SS_PE0_LINK_DBG_2_RADM_XFER_PENDING_MASK (0x100000U) #define SerDes_SS_PE0_LINK_DBG_2_RADM_XFER_PENDING_SHIFT (20U) /*! RADM_XFER_PENDING - Receive Request Pending Status * 0b0..No pending request * 0b1..Pending request exists */ #define SerDes_SS_PE0_LINK_DBG_2_RADM_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_RADM_XFER_PENDING_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_RADM_XFER_PENDING_MASK) #define SerDes_SS_PE0_LINK_DBG_2_EDMA_XFER_PENDING_MASK (0x200000U) #define SerDes_SS_PE0_LINK_DBG_2_EDMA_XFER_PENDING_SHIFT (21U) /*! EDMA_XFER_PENDING - eDMA Transfer Pending Status * 0b0..No pending request * 0b1..Pending request exists */ #define SerDes_SS_PE0_LINK_DBG_2_EDMA_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_EDMA_XFER_PENDING_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_EDMA_XFER_PENDING_MASK) #define SerDes_SS_PE0_LINK_DBG_2_BRDG_DBI_XFER_PENDING_MASK (0x400000U) #define SerDes_SS_PE0_LINK_DBG_2_BRDG_DBI_XFER_PENDING_SHIFT (22U) /*! BRDG_DBI_XFER_PENDING - AXI Slave DBI Transfer Pending Status * 0b0..No pending request * 0b1..Pending request exists */ #define SerDes_SS_PE0_LINK_DBG_2_BRDG_DBI_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_BRDG_DBI_XFER_PENDING_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_BRDG_DBI_XFER_PENDING_MASK) #define SerDes_SS_PE0_LINK_DBG_2_BRDG_SLV_XFER_PENDING_MASK (0x800000U) #define SerDes_SS_PE0_LINK_DBG_2_BRDG_SLV_XFER_PENDING_SHIFT (23U) /*! BRDG_SLV_XFER_PENDING - AXI Slave Non-DBI Transfer Pending Status * 0b0..No pending request * 0b1..Pending request exists */ #define SerDes_SS_PE0_LINK_DBG_2_BRDG_SLV_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_BRDG_SLV_XFER_PENDING_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_BRDG_SLV_XFER_PENDING_MASK) #define SerDes_SS_PE0_LINK_DBG_2_CDM_IN_RESET_MASK (0x1000000U) #define SerDes_SS_PE0_LINK_DBG_2_CDM_IN_RESET_SHIFT (24U) /*! CDM_IN_RESET - CDM Register In Reset * 0b0..Not in reset, or will not be reset * 0b1..In reset, or will be reset */ #define SerDes_SS_PE0_LINK_DBG_2_CDM_IN_RESET(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_LINK_DBG_2_CDM_IN_RESET_SHIFT)) & SerDes_SS_PE0_LINK_DBG_2_CDM_IN_RESET_MASK) /*! @} */ /*! @name PE0_AXI_MSTR_DBG_1 - PCIe Controller 0 AXI Master Debug 1 */ /*! @{ */ #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_MASK (0xFFFFU) #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_SHIFT (0U) /*! MSTR_WR_REQ - AXI Master Write Request Counter */ #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_SHIFT)) & SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_MASK) #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_PEND_MASK (0xFF0000U) #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_PEND_SHIFT (16U) /*! MSTR_WR_REQ_PEND - AXI Master Write Pending Request Counter */ #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_PEND(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_PEND_SHIFT)) & SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_REQ_PEND_MASK) #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_ERR_MASK (0xFF000000U) #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_ERR_SHIFT (24U) /*! MSTR_WR_ERR - AXI Master Write Response Error Counter */ #define SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_ERR_SHIFT)) & SerDes_SS_PE0_AXI_MSTR_DBG_1_MSTR_WR_ERR_MASK) /*! @} */ /*! @name PE0_AXI_MSTR_DBG_2 - PCIe Controller 0 AXI Master Debug 2 */ /*! @{ */ #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_MASK (0xFFFFU) #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_SHIFT (0U) /*! MSTR_RD_REQ - AXI Master Read Request Counter */ #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_SHIFT)) & SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_MASK) #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_PEND_MASK (0xFF0000U) #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_PEND_SHIFT (16U) /*! MSTR_RD_REQ_PEND - AXI Master Read Pending Request Counter */ #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_PEND(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_PEND_SHIFT)) & SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_REQ_PEND_MASK) #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_ERR_MASK (0xFF000000U) #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_ERR_SHIFT (24U) /*! MSTR_RD_ERR - AXI Master Read Response Error Counter */ #define SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_ERR_SHIFT)) & SerDes_SS_PE0_AXI_MSTR_DBG_2_MSTR_RD_ERR_MASK) /*! @} */ /*! @name PE0_AXI_SLV_DBG_1 - PCIe Controller 0 AXI Slave Debug 1 */ /*! @{ */ #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_MASK (0xFFFFU) #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_SHIFT (0U) /*! SLV_WR_REQ - AXI Slave Write Request Counter */ #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_SHIFT)) & SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_MASK) #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_PEND_MASK (0xFF0000U) #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_PEND_SHIFT (16U) /*! SLV_WR_REQ_PEND - AXI Slave Write Pending Request Counter */ #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_PEND(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_PEND_SHIFT)) & SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_REQ_PEND_MASK) #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_ERR_MASK (0xFF000000U) #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_ERR_SHIFT (24U) /*! SLV_WR_ERR - AXI Slave Write Response Error Counter */ #define SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_ERR_SHIFT)) & SerDes_SS_PE0_AXI_SLV_DBG_1_SLV_WR_ERR_MASK) /*! @} */ /*! @name PE0_AXI_SLV_DBG_2 - PCIe Controller 0 AXI Slave Debug 2 */ /*! @{ */ #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_MASK (0xFFFFU) #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_SHIFT (0U) /*! SLV_RD_REQ - AXI Slave Read Request Counter */ #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_SHIFT)) & SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_MASK) #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_PEND_MASK (0xFF0000U) #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_PEND_SHIFT (16U) /*! SLV_RD_REQ_PEND - AXI Slave Read Pending Request Counter */ #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_PEND(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_PEND_SHIFT)) & SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_REQ_PEND_MASK) #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_ERR_MASK (0xFF000000U) #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_ERR_SHIFT (24U) /*! SLV_RD_ERR - AXI Slave Read Response Error Counter */ #define SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_ERR_SHIFT)) & SerDes_SS_PE0_AXI_SLV_DBG_2_SLV_RD_ERR_MASK) /*! @} */ /*! @name PE0_ERR_STS - PCIe Controller 0 Error Status */ /*! @{ */ #define SerDes_SS_PE0_ERR_STS_RTLH_REQ_LINK_RETRAIN_MASK (0x4U) #define SerDes_SS_PE0_ERR_STS_RTLH_REQ_LINK_RETRAIN_SHIFT (2U) /*! RTLH_REQ_LINK_RETRAIN - Received watchdog timer expired * 0b0..Watchdog timer not expired * 0b1..Watchdog timer expired */ #define SerDes_SS_PE0_ERR_STS_RTLH_REQ_LINK_RETRAIN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_RTLH_REQ_LINK_RETRAIN_SHIFT)) & SerDes_SS_PE0_ERR_STS_RTLH_REQ_LINK_RETRAIN_MASK) #define SerDes_SS_PE0_ERR_STS_XDLH_SMLH_START_LINK_RETRAIN_MASK (0x8U) #define SerDes_SS_PE0_ERR_STS_XDLH_SMLH_START_LINK_RETRAIN_SHIFT (3U) /*! XDLH_SMLH_START_LINK_RETRAIN - Received watchdog timer expired * 0b0..No link retrain request active * 0b1..Link retrain request is active */ #define SerDes_SS_PE0_ERR_STS_XDLH_SMLH_START_LINK_RETRAIN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_XDLH_SMLH_START_LINK_RETRAIN_SHIFT)) & SerDes_SS_PE0_ERR_STS_XDLH_SMLH_START_LINK_RETRAIN_MASK) #define SerDes_SS_PE0_ERR_STS_VC_QOVERFLOW_MASK (0x10000U) #define SerDes_SS_PE0_ERR_STS_VC_QOVERFLOW_SHIFT (16U) /*! VC_QOVERFLOW - RADM Queue Overflow Error * 0b0..No overflow error detected * 0b0..No effect * 0b1..Overflow error detected * 0b1..Return this field's value to 0 */ #define SerDes_SS_PE0_ERR_STS_VC_QOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_VC_QOVERFLOW_SHIFT)) & SerDes_SS_PE0_ERR_STS_VC_QOVERFLOW_MASK) #define SerDes_SS_PE0_ERR_STS_SMLH_RCVD_LANE_REV_MASK (0x8000000U) #define SerDes_SS_PE0_ERR_STS_SMLH_RCVD_LANE_REV_SHIFT (27U) /*! SMLH_RCVD_LANE_REV - Receiver detected lane reversal. * 0b0..No lane reversal detected * 0b1..Lane reversal detected */ #define SerDes_SS_PE0_ERR_STS_SMLH_RCVD_LANE_REV(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_SMLH_RCVD_LANE_REV_SHIFT)) & SerDes_SS_PE0_ERR_STS_SMLH_RCVD_LANE_REV_MASK) #define SerDes_SS_PE0_ERR_STS_RMLH_DESKEW_ALIGNMENT_ERR_MASK (0x10000000U) #define SerDes_SS_PE0_ERR_STS_RMLH_DESKEW_ALIGNMENT_ERR_SHIFT (28U) /*! RMLH_DESKEW_ALIGNMENT_ERR - Deskew logic overflow. */ #define SerDes_SS_PE0_ERR_STS_RMLH_DESKEW_ALIGNMENT_ERR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_RMLH_DESKEW_ALIGNMENT_ERR_SHIFT)) & SerDes_SS_PE0_ERR_STS_RMLH_DESKEW_ALIGNMENT_ERR_MASK) #define SerDes_SS_PE0_ERR_STS_LINK_DOWN_STS_MASK (0x40000000U) #define SerDes_SS_PE0_ERR_STS_LINK_DOWN_STS_SHIFT (30U) /*! LINK_DOWN_STS - Link Down Event * 0b0..No link down error detected * 0b0..No effect * 0b1..Link down error detected * 0b1..Return this field's value to 0 */ #define SerDes_SS_PE0_ERR_STS_LINK_DOWN_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_LINK_DOWN_STS_SHIFT)) & SerDes_SS_PE0_ERR_STS_LINK_DOWN_STS_MASK) #define SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_MASK (0x80000000U) #define SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_SHIFT (31U) /*! APBSLV_TIMEOUT_STS - APB Slave Timeout Error * 0b0..No timeout error detected * 0b0..No effect * 0b1..Timeout error detected * 0b1..Return this field's value to 0 */ #define SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_SHIFT)) & SerDes_SS_PE0_ERR_STS_APBSLV_TIMEOUT_STS_MASK) /*! @} */ /*! @name PE0_ERR_INT_CTRL - PCIe Controller 0 Error Interrupt Control */ /*! @{ */ #define SerDes_SS_PE0_ERR_INT_CTRL_SET_SLOT_PWR_RCVD_INT_EN_MASK (0x2U) #define SerDes_SS_PE0_ERR_INT_CTRL_SET_SLOT_PWR_RCVD_INT_EN_SHIFT (1U) /*! SET_SLOT_PWR_RCVD_INT_EN - Interrupt enable for SET_SLOT_PWR_RCVD * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_ERR_INT_CTRL_SET_SLOT_PWR_RCVD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_SET_SLOT_PWR_RCVD_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_SET_SLOT_PWR_RCVD_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_RTLH_REQ_LINK_RETRAIN_INT_EN_MASK (0x4U) #define SerDes_SS_PE0_ERR_INT_CTRL_RTLH_REQ_LINK_RETRAIN_INT_EN_SHIFT (2U) /*! RTLH_REQ_LINK_RETRAIN_INT_EN - Interrupt enable for PE0_ERR_STS[RTLH_REQ_LINK_RETRAIN] * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_ERR_INT_CTRL_RTLH_REQ_LINK_RETRAIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_RTLH_REQ_LINK_RETRAIN_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_RTLH_REQ_LINK_RETRAIN_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_XDLH_SMLH_START_LINK_RETRAIN_INT_EN_MASK (0x8U) #define SerDes_SS_PE0_ERR_INT_CTRL_XDLH_SMLH_START_LINK_RETRAIN_INT_EN_SHIFT (3U) /*! XDLH_SMLH_START_LINK_RETRAIN_INT_EN - Interrupt enable for PE0_ERR_STS[XDLH_SMLH_START_LINK_RETRAIN] * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_ERR_INT_CTRL_XDLH_SMLH_START_LINK_RETRAIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_XDLH_SMLH_START_LINK_RETRAIN_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_XDLH_SMLH_START_LINK_RETRAIN_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_USP_EQ_REDO_EXECUTED_INT_EN_MASK (0x10U) #define SerDes_SS_PE0_ERR_INT_CTRL_USP_EQ_REDO_EXECUTED_INT_EN_SHIFT (4U) /*! USP_EQ_REDO_EXECUTED_INT_EN - Enabled interrupt corresponding to USP_EQ_REDO_EXECUTED_INT_STAT * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_ERR_INT_CTRL_USP_EQ_REDO_EXECUTED_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_USP_EQ_REDO_EXECUTED_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_USP_EQ_REDO_EXECUTED_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_FRONT_INT_EN_MASK (0x20U) #define SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_FRONT_INT_EN_SHIFT (5U) /*! TXDATA_PERR_FRONT_INT_EN - Interrupt Enable for Parity Error at Front End of the Transmit Datapath * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_FRONT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_FRONT_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_FRONT_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_BACK_INT_EN_MASK (0x40U) #define SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_BACK_INT_EN_SHIFT (6U) /*! TXDATA_PERR_BACK_INT_EN - Interrupt Enable for Parity Error at Back End of the Transmit Datapath * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_BACK_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_BACK_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_TXDATA_PERR_BACK_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_RXDATA_PERR_INT_EN_MASK (0x80U) #define SerDes_SS_PE0_ERR_INT_CTRL_RXDATA_PERR_INT_EN_SHIFT (7U) /*! RXDATA_PERR_INT_EN - Interrupt Enable for Parity Error in the Receive Datapath * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_ERR_INT_CTRL_RXDATA_PERR_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_RXDATA_PERR_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_RXDATA_PERR_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_VC_QOVERFLOW_INT_EN_MASK (0x10000U) #define SerDes_SS_PE0_ERR_INT_CTRL_VC_QOVERFLOW_INT_EN_SHIFT (16U) /*! VC_QOVERFLOW_INT_EN - Interrupt Enable for RADM Queue Overflow Error * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_ERR_INT_CTRL_VC_QOVERFLOW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_VC_QOVERFLOW_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_VC_QOVERFLOW_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_SMLH_RCVD_LANE_REV_INT_EN_MASK (0x8000000U) #define SerDes_SS_PE0_ERR_INT_CTRL_SMLH_RCVD_LANE_REV_INT_EN_SHIFT (27U) /*! SMLH_RCVD_LANE_REV_INT_EN - Interrupt enable for PE0_ERR_STS[SMLH_RCVD_LANE_REV] * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_ERR_INT_CTRL_SMLH_RCVD_LANE_REV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_SMLH_RCVD_LANE_REV_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_SMLH_RCVD_LANE_REV_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_RMLH_DESKEW_ALIGNMENT_ERR_INT_EN_MASK (0x10000000U) #define SerDes_SS_PE0_ERR_INT_CTRL_RMLH_DESKEW_ALIGNMENT_ERR_INT_EN_SHIFT (28U) /*! RMLH_DESKEW_ALIGNMENT_ERR_INT_EN - Interrupt enable for PE0_ERR_STS[RMLH_DESKEW_ALIGNMENT_ERR] * 0b0..Interrupt Disabled * 0b1..Interrupt Enabled */ #define SerDes_SS_PE0_ERR_INT_CTRL_RMLH_DESKEW_ALIGNMENT_ERR_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_RMLH_DESKEW_ALIGNMENT_ERR_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_RMLH_DESKEW_ALIGNMENT_ERR_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_LINK_DOWN_INT_EN_MASK (0x40000000U) #define SerDes_SS_PE0_ERR_INT_CTRL_LINK_DOWN_INT_EN_SHIFT (30U) /*! LINK_DOWN_INT_EN - Interrupt Enable for Link Down Event * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_ERR_INT_CTRL_LINK_DOWN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_LINK_DOWN_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_LINK_DOWN_INT_EN_MASK) #define SerDes_SS_PE0_ERR_INT_CTRL_APBSLV_TIMEOUT_INT_EN_MASK (0x80000000U) #define SerDes_SS_PE0_ERR_INT_CTRL_APBSLV_TIMEOUT_INT_EN_SHIFT (31U) /*! APBSLV_TIMEOUT_INT_EN - Interrupt Enable for APB Slave Timeout Error * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_ERR_INT_CTRL_APBSLV_TIMEOUT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_ERR_INT_CTRL_APBSLV_TIMEOUT_INT_EN_SHIFT)) & SerDes_SS_PE0_ERR_INT_CTRL_APBSLV_TIMEOUT_INT_EN_MASK) /*! @} */ /*! @name PE0_INT_STS - PCIe Controller 0 Interrupt Status */ /*! @{ */ #define SerDes_SS_PE0_INT_STS_RX_MSG_INT_STS_MASK (0x2U) #define SerDes_SS_PE0_INT_STS_RX_MSG_INT_STS_SHIFT (1U) /*! RX_MSG_INT_STS - Receive Message Interrupt Status */ #define SerDes_SS_PE0_INT_STS_RX_MSG_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_RX_MSG_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_RX_MSG_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_ERR_INT_STS_MASK (0x4U) #define SerDes_SS_PE0_INT_STS_ERR_INT_STS_SHIFT (2U) /*! ERR_INT_STS - Internal Error Interrupt Status */ #define SerDes_SS_PE0_INT_STS_ERR_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_ERR_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_ERR_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_USP_EQ_REDO_EXECUTED_INT_STAT_MASK (0x8U) #define SerDes_SS_PE0_INT_STS_USP_EQ_REDO_EXECUTED_INT_STAT_SHIFT (3U) /*! USP_EQ_REDO_EXECUTED_INT_STAT - Interrupt indicating the EQ redo is executed by USP * 0b0..EQ Redo is executed * 0b1..No EQ Redo executed */ #define SerDes_SS_PE0_INT_STS_USP_EQ_REDO_EXECUTED_INT_STAT(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_USP_EQ_REDO_EXECUTED_INT_STAT_SHIFT)) & SerDes_SS_PE0_INT_STS_USP_EQ_REDO_EXECUTED_INT_STAT_MASK) #define SerDes_SS_PE0_INT_STS_AER_RC_ERR_INT_STS_MASK (0x10U) #define SerDes_SS_PE0_INT_STS_AER_RC_ERR_INT_STS_SHIFT (4U) /*! AER_RC_ERR_INT_STS - Root Complex Advanced Error Reporting Status * 0b0..Fields in ROOT_ERR_STATUS_OFF are 0 or fields in ROOT_ERR_CMD_OFF are 0 * 0b1..A field in ROOT_ERR_STATUS_OFF is 1 and its associated error reporting enable field in ROOT_ERR_CMD_OFF is 1 */ #define SerDes_SS_PE0_INT_STS_AER_RC_ERR_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_AER_RC_ERR_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_AER_RC_ERR_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_PME_INT_STS_MASK (0x20U) #define SerDes_SS_PE0_INT_STS_PME_INT_STS_SHIFT (5U) /*! PME_INT_STS - PME Interrupt Status * 0b0..ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] = 0 or ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 0 * 0b1..ROOT_CONTROL_ROOT_CAPABILITIES_REG[PCIE_CAP_PME_INT_EN] = ROOT_STATUS_REG[PCIE_CAP_PME_STATUS] = 1 */ #define SerDes_SS_PE0_INT_STS_PME_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_PME_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_PME_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_HP_INT_STS_MASK (0x40U) #define SerDes_SS_PE0_INT_STS_HP_INT_STS_SHIFT (6U) /*! HP_INT_STS - Hot-Plug Status */ #define SerDes_SS_PE0_INT_STS_HP_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_HP_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_HP_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_SYS_ERR_RC_STS_MASK (0x80U) #define SerDes_SS_PE0_INT_STS_SYS_ERR_RC_STS_SHIFT (7U) /*! SYS_ERR_RC_STS - System Error Status * 0b0..No device reports any system error, or the error-reporting enable fields in ROOT_CONTROL_ROOT_CAPABILITIES_REG are 0 * 0b1..A device reports a system error and the associated error-reporting enable field in ROOT_CONTROL_ROOT_CAPABILITIES_REG = 1 */ #define SerDes_SS_PE0_INT_STS_SYS_ERR_RC_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_SYS_ERR_RC_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_SYS_ERR_RC_STS_MASK) #define SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_INT_STS_MASK (0x100U) #define SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_INT_STS_SHIFT (8U) /*! LINK_AUTO_BW_INT_STS - Link Autonomous Bandwidth Interrupt Status * 0b0..The conditions in the field description are not met * 0b1..The conditions in the field description are met */ #define SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_BW_MGT_INT_STS_MASK (0x200U) #define SerDes_SS_PE0_INT_STS_BW_MGT_INT_STS_SHIFT (9U) /*! BW_MGT_INT_STS - Link Bandwidth Management Interrupt Status * 0b0..The conditions in the field description are not met * 0b1..The conditions in the field description are met */ #define SerDes_SS_PE0_INT_STS_BW_MGT_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_BW_MGT_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_BW_MGT_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_LINK_EQ_REQ_INT_STS_MASK (0x400U) #define SerDes_SS_PE0_INT_STS_LINK_EQ_REQ_INT_STS_SHIFT (10U) /*! LINK_EQ_REQ_INT_STS - Link Equalization Request Interrupt Status * 0b0..LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = 0 or LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 0 * 0b1..LINK_CONTROL2_LINK_STATUS2_REG[PCIE_CAP_LINK_EQ_REQ] = LINK_CONTROL3_REG[EQ_REQ_INT_EN] = 1 */ #define SerDes_SS_PE0_INT_STS_LINK_EQ_REQ_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_LINK_EQ_REQ_INT_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_LINK_EQ_REQ_INT_STS_MASK) #define SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_MSI_STS_MASK (0x1000U) #define SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_MSI_STS_SHIFT (12U) /*! LINK_AUTO_BW_MSI_STS - Link Autonomous Bandwidth MSI Status * 0b0..The conditions in the field description are not met * 0b1..The conditions in the field description are met */ #define SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_MSI_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_MSI_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_LINK_AUTO_BW_MSI_STS_MASK) #define SerDes_SS_PE0_INT_STS_BW_MGT_MSI_STS_MASK (0x2000U) #define SerDes_SS_PE0_INT_STS_BW_MGT_MSI_STS_SHIFT (13U) /*! BW_MGT_MSI_STS - Link Bandwidth Management MSI Status * 0b0..The conditions in the field description are not met * 0b1..The conditions in the field description are met */ #define SerDes_SS_PE0_INT_STS_BW_MGT_MSI_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_BW_MGT_MSI_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_BW_MGT_MSI_STS_MASK) #define SerDes_SS_PE0_INT_STS_PM_LINKST_ENTR_L1SUB_STS_MASK (0x1000000U) #define SerDes_SS_PE0_INT_STS_PM_LINKST_ENTR_L1SUB_STS_SHIFT (24U) /*! PM_LINKST_ENTR_L1SUB_STS - Indicates that the controller has entered in the L1 substate. */ #define SerDes_SS_PE0_INT_STS_PM_LINKST_ENTR_L1SUB_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_PM_LINKST_ENTR_L1SUB_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_PM_LINKST_ENTR_L1SUB_STS_MASK) #define SerDes_SS_PE0_INT_STS_FLRIN_STS_MASK (0x20000000U) #define SerDes_SS_PE0_INT_STS_FLRIN_STS_SHIFT (29U) /*! FLRIN_STS - FLR Interrupt Status * 0b0..No interrupt pending * 0b1..Interrupt is pending */ #define SerDes_SS_PE0_INT_STS_FLRIN_STS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_INT_STS_FLRIN_STS_SHIFT)) & SerDes_SS_PE0_INT_STS_FLRIN_STS_MASK) /*! @} */ /*! @name PE0_MSI_GEN_CTRL - PCIe Controller 0 MSI Generation Control */ /*! @{ */ #define SerDes_SS_PE0_MSI_GEN_CTRL_MSI_INT_MASK (0xFFFFFFFFU) #define SerDes_SS_PE0_MSI_GEN_CTRL_MSI_INT_SHIFT (0U) /*! MSI_INT - MSI Vector */ #define SerDes_SS_PE0_MSI_GEN_CTRL_MSI_INT(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_MSI_GEN_CTRL_MSI_INT_SHIFT)) & SerDes_SS_PE0_MSI_GEN_CTRL_MSI_INT_MASK) /*! @} */ /*! @name PE0_FSM_TRACK_1 - PCIe Controller 0 FSM Track 1 */ /*! @{ */ #define SerDes_SS_PE0_FSM_TRACK_1_FSM_TRIG_MASK (0x3FU) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_TRIG_SHIFT (0U) /*! FSM_TRIG - Trigger State Of FSM Track */ #define SerDes_SS_PE0_FSM_TRACK_1_FSM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_FSM_TRIG_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_FSM_TRIG_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_MON_EN_MASK (0x40U) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_MON_EN_SHIFT (6U) /*! FSM_MON_EN - FSM Track Enable * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PE0_FSM_TRACK_1_FSM_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_FSM_MON_EN_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_FSM_MON_EN_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_1_MASK (0x3F00U) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_1_SHIFT (8U) /*! FSM_1 - FSM State 1 */ #define SerDes_SS_PE0_FSM_TRACK_1_FSM_1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_FSM_1_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_FSM_1_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_1_MASK (0x4000U) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_1_SHIFT (14U) /*! EVENT_A_1 - TS1 Status In FSM State 1 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_1_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_1_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_1_MASK (0x8000U) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_1_SHIFT (15U) /*! EVENT_B_1 - TS2 Status In FSM State 1 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_1(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_1_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_1_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_2_MASK (0x3F0000U) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_2_SHIFT (16U) /*! FSM_2 - FSM State 2 */ #define SerDes_SS_PE0_FSM_TRACK_1_FSM_2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_FSM_2_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_FSM_2_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_2_MASK (0x400000U) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_2_SHIFT (22U) /*! EVENT_A_2 - TS1 Status In FSM State 2 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_2_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_2_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_2_MASK (0x800000U) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_2_SHIFT (23U) /*! EVENT_B_2 - TS2 Status In FSM State 2 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_2(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_2_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_2_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_3_MASK (0x3F000000U) #define SerDes_SS_PE0_FSM_TRACK_1_FSM_3_SHIFT (24U) /*! FSM_3 - FSM State 3 */ #define SerDes_SS_PE0_FSM_TRACK_1_FSM_3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_FSM_3_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_FSM_3_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_3_MASK (0x40000000U) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_3_SHIFT (30U) /*! EVENT_A_3 - TS1 Status in FSM State 3 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_3_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_EVENT_A_3_MASK) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_3_MASK (0x80000000U) #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_3_SHIFT (31U) /*! EVENT_B_3 - TS2 Status in FSM State 3 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_3(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_3_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_1_EVENT_B_3_MASK) /*! @} */ /*! @name PE0_FSM_TRACK_2 - PCIe Controller 0 FSM Track 2 */ /*! @{ */ #define SerDes_SS_PE0_FSM_TRACK_2_FSM_4_MASK (0x3FU) #define SerDes_SS_PE0_FSM_TRACK_2_FSM_4_SHIFT (0U) /*! FSM_4 - FSM State 4 */ #define SerDes_SS_PE0_FSM_TRACK_2_FSM_4(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_FSM_4_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_FSM_4_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_4_MASK (0x40U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_4_SHIFT (6U) /*! EVENT_A_4 - TS1 Status in FSM State 4 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_4(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_4_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_4_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_4_MASK (0x80U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_4_SHIFT (7U) /*! EVENT_B_4 - TS2 Status in FSM State 4 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_4(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_4_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_4_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_FSM_5_MASK (0x3F00U) #define SerDes_SS_PE0_FSM_TRACK_2_FSM_5_SHIFT (8U) /*! FSM_5 - FSM State 5 */ #define SerDes_SS_PE0_FSM_TRACK_2_FSM_5(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_FSM_5_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_FSM_5_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_5_MASK (0x4000U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_5_SHIFT (14U) /*! EVENT_A_5 - TS1 Status in FSM State 5 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_5(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_5_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_5_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_5_MASK (0x8000U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_5_SHIFT (15U) /*! EVENT_B_5 - TS2 Status in FSM State 5 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_5(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_5_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_5_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_FSM_6_MASK (0x3F0000U) #define SerDes_SS_PE0_FSM_TRACK_2_FSM_6_SHIFT (16U) /*! FSM_6 - FSM State 6 */ #define SerDes_SS_PE0_FSM_TRACK_2_FSM_6(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_FSM_6_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_FSM_6_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_6_MASK (0x400000U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_6_SHIFT (22U) /*! EVENT_A_6 - TS1 Status in FSM State 6 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_6(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_6_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_6_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_6_MASK (0x800000U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_6_SHIFT (23U) /*! EVENT_B_6 - TS2 Status in FSM State 6 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_6(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_6_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_6_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_FSM_7_MASK (0x3F000000U) #define SerDes_SS_PE0_FSM_TRACK_2_FSM_7_SHIFT (24U) /*! FSM_7 - FSM State 7 */ #define SerDes_SS_PE0_FSM_TRACK_2_FSM_7(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_FSM_7_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_FSM_7_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_7_MASK (0x40000000U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_7_SHIFT (30U) /*! EVENT_A_7 - TS1 Status in FSM State 7 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_7(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_7_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_A_7_MASK) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_7_MASK (0x80000000U) #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_7_SHIFT (31U) /*! EVENT_B_7 - TS2 Status in FSM State 7 * 0b0..Not received * 0b1..Received */ #define SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_7(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_7_SHIFT)) & SerDes_SS_PE0_FSM_TRACK_2_EVENT_B_7_MASK) /*! @} */ /*! @name APB_BRIDGE_TO_CTRL - APB Bridge Timeout Control */ /*! @{ */ #define SerDes_SS_APB_BRIDGE_TO_CTRL_APBCLK_FREQ_MASK (0x3FFU) #define SerDes_SS_APB_BRIDGE_TO_CTRL_APBCLK_FREQ_SHIFT (0U) /*! APBCLK_FREQ - APB Clock Frequency (MHz) */ #define SerDes_SS_APB_BRIDGE_TO_CTRL_APBCLK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_APB_BRIDGE_TO_CTRL_APBCLK_FREQ_SHIFT)) & SerDes_SS_APB_BRIDGE_TO_CTRL_APBCLK_FREQ_MASK) #define SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMEOUT_DIS_MASK (0x400U) #define SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMEOUT_DIS_SHIFT (10U) /*! APB_TIMEOUT_DIS - APB Timeout Control Disable * 0b0..Enable * 0b1..Disable */ #define SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMEOUT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMEOUT_DIS_SHIFT)) & SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMEOUT_DIS_MASK) #define SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMER_LIMT_MASK (0xFFFF0000U) #define SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMER_LIMT_SHIFT (16U) /*! APB_TIMER_LIMT - APB Watchdog Timeout Threshold (us) */ #define SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMER_LIMT(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMER_LIMT_SHIFT)) & SerDes_SS_APB_BRIDGE_TO_CTRL_APB_TIMER_LIMT_MASK) /*! @} */ /*! @name PHY_REG_ADDR - PHY Register Address */ /*! @{ */ #define SerDes_SS_PHY_REG_ADDR_ADDR_MASK (0xFFFFU) #define SerDes_SS_PHY_REG_ADDR_ADDR_SHIFT (0U) /*! ADDR - Indirect PHY Register Access Address */ #define SerDes_SS_PHY_REG_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PHY_REG_ADDR_ADDR_SHIFT)) & SerDes_SS_PHY_REG_ADDR_ADDR_MASK) #define SerDes_SS_PHY_REG_ADDR_PHY_REG_EN_MASK (0x80000000U) #define SerDes_SS_PHY_REG_ADDR_PHY_REG_EN_SHIFT (31U) /*! PHY_REG_EN - Indirect PHY Register Access Enable * 0b0..Disable * 0b1..Enable */ #define SerDes_SS_PHY_REG_ADDR_PHY_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PHY_REG_ADDR_PHY_REG_EN_SHIFT)) & SerDes_SS_PHY_REG_ADDR_PHY_REG_EN_MASK) /*! @} */ /*! @name PHY_REG_DATA - PHY Register Data */ /*! @{ */ #define SerDes_SS_PHY_REG_DATA_DATA_MASK (0xFFFFU) #define SerDes_SS_PHY_REG_DATA_DATA_SHIFT (0U) /*! DATA - Indirect PHY Register Access Data */ #define SerDes_SS_PHY_REG_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_PHY_REG_DATA_DATA_SHIFT)) & SerDes_SS_PHY_REG_DATA_DATA_MASK) /*! @} */ /*! @name RST_CTRL - Reset Control */ /*! @{ */ #define SerDes_SS_RST_CTRL_COLD_RST_MASK (0x1U) #define SerDes_SS_RST_CTRL_COLD_RST_SHIFT (0U) /*! COLD_RST - Cold Reset Control * 0b0..Deassert * 0b1..Assert */ #define SerDes_SS_RST_CTRL_COLD_RST(x) (((uint32_t)(((uint32_t)(x)) << SerDes_SS_RST_CTRL_COLD_RST_SHIFT)) & SerDes_SS_RST_CTRL_COLD_RST_MASK) /*! @} */ /*! * @} */ /* end of group SerDes_SS_Register_Masks */ /* SerDes_SS - Peripheral instance base addresses */ /** Peripheral HSIO__PCIE1__SERDES_SS base address */ #define HSIO__PCIE1__SERDES_SS_BASE (0x4C340000u) /** Peripheral HSIO__PCIE1__SERDES_SS base pointer */ #define HSIO__PCIE1__SERDES_SS ((SerDes_SS_Type *)HSIO__PCIE1__SERDES_SS_BASE) /** Peripheral HSIO__PCIE2__SERDES_SS base address */ #define HSIO__PCIE2__SERDES_SS_BASE (0x4C3C0000u) /** Peripheral HSIO__PCIE2__SERDES_SS base pointer */ #define HSIO__PCIE2__SERDES_SS ((SerDes_SS_Type *)HSIO__PCIE2__SERDES_SS_BASE) /** Array initializer of SerDes_SS peripheral base addresses */ #define SerDes_SS_BASE_ADDRS { HSIO__PCIE1__SERDES_SS_BASE, HSIO__PCIE2__SERDES_SS_BASE } /** Array initializer of SerDes_SS peripheral base pointers */ #define SerDes_SS_BASE_PTRS { HSIO__PCIE1__SERDES_SS, HSIO__PCIE2__SERDES_SS } /*! * @} */ /* end of group SerDes_SS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TCM_ECC_MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TCM_ECC_MCM_Peripheral_Access_Layer TCM_ECC_MCM Peripheral Access Layer * @{ */ /** TCM_ECC_MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t TCMECCR; /**< TCM ECC Control, offset: 0x4 */ uint8_t RESERVED_1[24]; __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x20 */ __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable, offset: 0x24 */ __IO uint32_t INT_SIG_EN; /**< Interrupt Enable, offset: 0x28 */ uint8_t RESERVED_2[48]; __I uint32_t CODE_TCM_ECC_SINGLE_ERROR_INFO; /**< Code TCM Single-Bit ECC Error Information, offset: 0x5C */ __I uint32_t CODE_TCM_ECC_SINGLE_ERROR_ADDR; /**< Code TCM Single-Bit ECC Error Address, offset: 0x60 */ uint8_t RESERVED_3[4]; __I uint32_t CODE_TCM_ECC_MULTI_ERROR_INFO; /**< Code TCM Multibit ECC Error Information, offset: 0x68 */ __I uint32_t CODE_TCM_ECC_MULTI_ERROR_ADDR; /**< Code TCM Multibit ECC Error Address, offset: 0x6C */ uint8_t RESERVED_4[4]; __I uint32_t SYS_TCM_ECC_SINGLE_ERROR_INFO; /**< System TCM Single-Bit ECC Error Information, offset: 0x74 */ __I uint32_t SYS_TCM_ECC_SINGLE_ERROR_ADDR; /**< System TCM Single-Bit ECC Error Address, offset: 0x78 */ uint8_t RESERVED_5[4]; __I uint32_t SYS_TCM_ECC_MULTI_ERROR_INFO; /**< System TCM Multibit ECC Error Information, offset: 0x80 */ __I uint32_t SYS_TCM_ECC_MULTI_ERROR_ADDR; /**< System TCM Multibit ECC Error Address, offset: 0x84 */ uint8_t RESERVED_6[12]; __IO uint32_t CODE_TCM_ECC_ERROR_INJEC; /**< Code TCM ECC Error Injection, offset: 0x94 */ __IO uint32_t SYS_TCM_ECC_ERROR_INJEC; /**< System TCM ECC Error Injection, offset: 0x98 */ } TCM_ECC_MCM_Type; /* ---------------------------------------------------------------------------- -- TCM_ECC_MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TCM_ECC_MCM_Register_Masks TCM_ECC_MCM Register Masks * @{ */ /*! @name TCMECCR - TCM ECC Control */ /*! @{ */ #define TCM_ECC_MCM_TCMECCR_WECC_DIS_MASK (0x1U) #define TCM_ECC_MCM_TCMECCR_WECC_DIS_SHIFT (0U) /*! WECC_DIS - TCM ECC Write Generation Disable * 0b1..Disable * 0b0..Enable */ #define TCM_ECC_MCM_TCMECCR_WECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_TCMECCR_WECC_DIS_SHIFT)) & TCM_ECC_MCM_TCMECCR_WECC_DIS_MASK) #define TCM_ECC_MCM_TCMECCR_RECC_DIS_MASK (0x2U) #define TCM_ECC_MCM_TCMECCR_RECC_DIS_SHIFT (1U) /*! RECC_DIS - TCM ECC Read Check Disable * 0b1..Disable * 0b0..Enable */ #define TCM_ECC_MCM_TCMECCR_RECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_TCMECCR_RECC_DIS_SHIFT)) & TCM_ECC_MCM_TCMECCR_RECC_DIS_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_MASK (0x400U) #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_SHIFT (10U) /*! CODE_TCM_ECC_ERRM_INT - Code TCM Access Multibit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRM_INT_MASK) #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_MASK (0x800U) #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_SHIFT (11U) /*! CODE_TCM_ECC_ERRS_INT - Code TCM Access Single-Bit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_CODE_TCM_ECC_ERRS_INT_MASK) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_MASK (0x1000U) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_SHIFT (12U) /*! SYS_TCM_ECC_ERRM_INT - System TCM Access Multibit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRM_INT_MASK) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_MASK (0x2000U) #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_SHIFT (13U) /*! SYS_TCM_ECC_ERRS_INT - System TCM Access Single-Bit ECC Error Interrupt Status * 0b0..No error * 0b1..Error * 0b0..No effect * 0b1..Clear the flag */ #define TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_SHIFT)) & TCM_ECC_MCM_INT_STATUS_SYS_TCM_ECC_ERRS_INT_MASK) /*! @} */ /*! @name INT_STAT_EN - Interrupt Status Enable */ /*! @{ */ #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_MASK (0x400U) #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_SHIFT (10U) /*! CODE_TCM_ERRM_INT_EN - Code TCM Access Multibit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRM_INT_EN_MASK) #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_MASK (0x800U) #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_SHIFT (11U) /*! CODE_TCM_ERRS_INT_EN - Code TCM Access Single-Bit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_CODE_TCM_ERRS_INT_EN_MASK) #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_MASK (0x1000U) #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_SHIFT (12U) /*! SYS_TCM_ERRM_INT_EN - System TCM Access Multibit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRM_INT_EN_MASK) #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_MASK (0x2000U) #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_SHIFT (13U) /*! SYS_TCM_ERRS_INT_EN - System TCM Access Single-Bit ECC Error Interrupt Status Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_SHIFT)) & TCM_ECC_MCM_INT_STAT_EN_SYS_TCM_ERRS_INT_EN_MASK) /*! @} */ /*! @name INT_SIG_EN - Interrupt Enable */ /*! @{ */ #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_MASK (0x400U) #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_SHIFT (10U) /*! CODE_TCM_ERRM_INT_SIG_EN - Code TCM Access Multibit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRM_INT_SIG_EN_MASK) #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_MASK (0x800U) #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_SHIFT (11U) /*! CODE_TCM_ERRS_INT_SIG_EN - Code TCM Access Single-Bit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_CODE_TCM_ERRS_INT_SIG_EN_MASK) #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_MASK (0x1000U) #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_SHIFT (12U) /*! SYS_TCM_ERRM_INT_SIG_EN - System TCM Access Multibit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRM_INT_SIG_EN_MASK) #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_MASK (0x2000U) #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_SHIFT (13U) /*! SYS_TCM_ERRS_INT_SIG_EN - System TCM Access Single-Bit ECC Error Interrupt Signal Enable * 0b0..Mask * 0b1..Enable */ #define TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_SHIFT)) & TCM_ECC_MCM_INT_SIG_EN_SYS_TCM_ERRS_INT_SIG_EN_MASK) /*! @} */ /*! @name CODE_TCM_ECC_SINGLE_ERROR_INFO - Code TCM Single-Bit ECC Error Information */ /*! @{ */ #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_MASK (0xEU) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_SHIFT (1U) /*! CODE_TCM_ECCS_EFSIZ - Code TCM Single-Bit ECC Error for Corresponding TCM Access Size */ #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSIZ_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_MASK (0xF0U) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_SHIFT (4U) /*! CODE_TCM_ECCS_EFMST - Code TCM Single-Bit ECC Error for Corresponding TCM Master */ #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFMST_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_MASK (0xF00U) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_SHIFT (8U) /*! CODE_TCM_ECCS_EFPRT - Code TCM Single-Bit ECC Error for Corresponding TCM Access Protection */ #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFPRT_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_MASK (0x7F000U) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_SHIFT (12U) /*! CODE_TCM_ECCS_EFSYN - Code TCM Single-Bit ECC Error Corresponding Syndrome */ #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_INFO_CODE_TCM_ECCS_EFSYN_MASK) /*! @} */ /*! @name CODE_TCM_ECC_SINGLE_ERROR_ADDR - Code TCM Single-Bit ECC Error Address */ /*! @{ */ #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! CODE_TCM_ECCS_ERRED_ADDR - Code TCM Single-Bit ECC Error Address */ #define TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_SINGLE_ERROR_ADDR_CODE_TCM_ECCS_ERRED_ADDR_MASK) /*! @} */ /*! @name CODE_TCM_ECC_MULTI_ERROR_INFO - Code TCM Multibit ECC Error Information */ /*! @{ */ #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_MASK (0xEU) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_SHIFT (1U) /*! CODE_TCM_ECCM_EFSIZ - Code TCM Multibit ECC Error for Corresponding TCM Access Size */ #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSIZ_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_MASK (0xF0U) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_SHIFT (4U) /*! CODE_TCM_ECCM_EFMST - Code TCM Multibit ECC Error for Corresponding TCM Master */ #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFMST_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_MASK (0xF00U) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_SHIFT (8U) /*! CODE_TCM_ECCM_EFPRT - CODE_TCM Multibit ECC Error for Corresponding Access Protection Attribute */ #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFPRT_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_MASK (0x7F000U) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_SHIFT (12U) /*! CODE_TCM_ECCM_EFSYN - Code TCM Multibit ECC Error for Corresponding Syndrome */ #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_INFO_CODE_TCM_ECCM_EFSYN_MASK) /*! @} */ /*! @name CODE_TCM_ECC_MULTI_ERROR_ADDR - Code TCM Multibit ECC Error Address */ /*! @{ */ #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! CODE_TCM_ECCM_ERRED_ADDR - Code TCM Multibit ECC Error Address */ #define TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_MULTI_ERROR_ADDR_CODE_TCM_ECCM_ERRED_ADDR_MASK) /*! @} */ /*! @name SYS_TCM_ECC_SINGLE_ERROR_INFO - System TCM Single-Bit ECC Error Information */ /*! @{ */ #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_MASK (0xEU) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_SHIFT (1U) /*! SYS_TCM_ECCS_EFSIZ - System TCM Single-Bit ECC Error for Corresponding TCM Access Size */ #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSIZ_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_MASK (0xF0U) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_SHIFT (4U) /*! SYS_TCM_ECCS_EFMST - System TCM Single-Bit ECC Error for Corresponding TCM Master */ #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFMST_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_MASK (0xF00U) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_SHIFT (8U) /*! SYS_TCM_ECCS_EFPRT - System TCM Single-Bit ECC Error for Corresponding Access Protection Attribute */ #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFPRT_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_MASK (0x7F000U) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_SHIFT (12U) /*! SYS_TCM_ECCS_EFSYN - System TCM Single-Bit ECC Error for Corresponding Syndrome */ #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_INFO_SYS_TCM_ECCS_EFSYN_MASK) /*! @} */ /*! @name SYS_TCM_ECC_SINGLE_ERROR_ADDR - System TCM Single-Bit ECC Error Address */ /*! @{ */ #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! SYS_TCM_ECCS_ERRED_ADDR - System TCM Single-Bit ECC Error Address */ #define TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_SINGLE_ERROR_ADDR_SYS_TCM_ECCS_ERRED_ADDR_MASK) /*! @} */ /*! @name SYS_TCM_ECC_MULTI_ERROR_INFO - System TCM Multibit ECC Error Information */ /*! @{ */ #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_MASK (0xEU) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_SHIFT (1U) /*! SYS_TCM_ECCM_EFSIZ - System TCM Multibit ECC Error for Corresponding TCM Access Size */ #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSIZ_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_MASK (0xF0U) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_SHIFT (4U) /*! SYS_TCM_ECCM_EFMST - System TCM Multibit ECC Error for Corresponding TCM Master */ #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFMST_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_MASK (0xF00U) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_SHIFT (8U) /*! SYS_TCM_ECCM_EFPRT - System TCM Multibit ECC Error for Corresponding Access Protection Attribute */ #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFPRT_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_MASK (0x7F000U) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_SHIFT (12U) /*! SYS_TCM_ECCM_EFSYN - System TCM Multibit ECC Error for Corresponding Syndrome */ #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_INFO_SYS_TCM_ECCM_EFSYN_MASK) /*! @} */ /*! @name SYS_TCM_ECC_MULTI_ERROR_ADDR - System TCM Multibit ECC Error Address */ /*! @{ */ #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! SYS_TCM_ECCM_ERRED_ADDR - System TCM Multibit ECC Error Address */ #define TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_MULTI_ERROR_ADDR_SYS_TCM_ECCM_ERRED_ADDR_MASK) /*! @} */ /*! @name CODE_TCM_ECC_ERROR_INJEC - Code TCM ECC Error Injection */ /*! @{ */ #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_MASK (0xFFU) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_SHIFT (0U) /*! CODE_TCM_ERR1BIT - Position of First Bit to Inject ECC Error */ #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR1BIT_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_MASK (0xFF00U) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_SHIFT (8U) /*! CODE_TCM_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_ERR2BIT_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_MASK (0x10000U) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_SHIFT (16U) /*! CODE_TCM_FR11BI - Force One 1-Bit Data Inversion on Code TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR11BI_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_MASK (0x20000U) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_SHIFT (17U) /*! CODE_TCM_FR1NCI - Force One Noncorrectable Data Inversion on Code TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FR1NCI_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_MASK (0x40000U) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_SHIFT (18U) /*! CODE_TCM_FRC1BI - Force Continuous 1-Bit Data Inversions on Code TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRC1BI_MASK) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_MASK (0x80000U) #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_SHIFT (19U) /*! CODE_TCM_FRCNCI - Force Continuous Noncorrectable Data Inversions on Code TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_SHIFT)) & TCM_ECC_MCM_CODE_TCM_ECC_ERROR_INJEC_CODE_TCM_FRCNCI_MASK) /*! @} */ /*! @name SYS_TCM_ECC_ERROR_INJEC - System TCM ECC Error Injection */ /*! @{ */ #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_MASK (0xFFU) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_SHIFT (0U) /*! SYS_TCM_ERR1BIT - Position of First Bit to Inject ECC Error */ #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR1BIT_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_MASK (0xFF00U) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_SHIFT (8U) /*! SYS_TCM_ERR2BIT - Position of Second Bit to Inject ECC Error */ #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_ERR2BIT_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_MASK (0x10000U) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_SHIFT (16U) /*! SYS_TCM_FR11BI - Force One 1-Bit Data Inversion on System TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR11BI_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_MASK (0x20000U) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_SHIFT (17U) /*! SYS_TCM_FR1NCI - Force One Noncorrectable Data Inversion on System TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FR1NCI_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_MASK (0x40000U) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_SHIFT (18U) /*! SYS_TCM_FRC1BI - Force Continuous 1-Bit Data Inversions on System TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRC1BI_MASK) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_MASK (0x80000U) #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_SHIFT (19U) /*! SYS_TCM_FRCNCI - Force Continuous Noncorrectable Data Inversions on System TCM Write Access * 0b0..Disable injection * 0b1..Enable injection */ #define TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI(x) (((uint32_t)(((uint32_t)(x)) << TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_SHIFT)) & TCM_ECC_MCM_SYS_TCM_ECC_ERROR_INJEC_SYS_TCM_FRCNCI_MASK) /*! @} */ /*! * @} */ /* end of group TCM_ECC_MCM_Register_Masks */ /* TCM_ECC_MCM - Peripheral instance base addresses */ /** Peripheral AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM base address */ #define AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM_BASE (0x44420000u) /** Peripheral AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM base pointer */ #define AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM ((TCM_ECC_MCM_Type *)AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM_BASE) /** Array initializer of TCM_ECC_MCM peripheral base addresses */ #define TCM_ECC_MCM_BASE_ADDRS { AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM_BASE } /** Array initializer of TCM_ECC_MCM peripheral base pointers */ #define TCM_ECC_MCM_BASE_PTRS { AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM } /*! * @} */ /* end of group TCM_ECC_MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TMPSNS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TMPSNS_Peripheral_Access_Layer TMPSNS Peripheral Access Layer * @{ */ /** TMPSNS - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL0; /**< Control 0, offset: 0x0 */ __IO uint32_t CTRL0_SET; /**< Control 0, offset: 0x4 */ __IO uint32_t CTRL0_CLR; /**< Control 0, offset: 0x8 */ __IO uint32_t CTRL0_TOG; /**< Control 0, offset: 0xC */ __IO uint32_t STAT0; /**< Status 0, offset: 0x10 */ __IO uint32_t STAT0_SET; /**< Status 0, offset: 0x14 */ __IO uint32_t STAT0_CLR; /**< Status 0, offset: 0x18 */ __IO uint32_t STAT0_TOG; /**< Status 0, offset: 0x1C */ __IO uint32_t DATA0; /**< Data 0, offset: 0x20 */ __IO uint32_t DATA0_SET; /**< Data 0, offset: 0x24 */ __IO uint32_t DATA0_CLR; /**< Data 0, offset: 0x28 */ __IO uint32_t DATA0_TOG; /**< Data 0, offset: 0x2C */ __IO uint32_t THR_CTRL01; /**< Threshold Control 01, offset: 0x30 */ __IO uint32_t THR_CTRL01_SET; /**< Threshold Control 01, offset: 0x34 */ __IO uint32_t THR_CTRL01_CLR; /**< Threshold Control 01, offset: 0x38 */ __IO uint32_t THR_CTRL01_TOG; /**< Threshold Control 01, offset: 0x3C */ __IO uint32_t THR_CTRL23; /**< Threshold Control 23, offset: 0x40 */ __IO uint32_t THR_CTRL23_SET; /**< Threshold Control 23, offset: 0x44 */ __IO uint32_t THR_CTRL23_CLR; /**< Threshold Control 23, offset: 0x48 */ __IO uint32_t THR_CTRL23_TOG; /**< Threshold Control 23, offset: 0x4C */ uint8_t RESERVED_0[432]; __IO uint32_t CTRL1; /**< Control 1, offset: 0x200 */ __IO uint32_t CTRL1_SET; /**< Control 1, offset: 0x204 */ __IO uint32_t CTRL1_CLR; /**< Control 1, offset: 0x208 */ __IO uint32_t CTRL1_TOG; /**< Control 1, offset: 0x20C */ __IO uint32_t STAT1; /**< Status 1, offset: 0x210 */ __IO uint32_t STAT1_SET; /**< Status 1, offset: 0x214 */ __IO uint32_t STAT1_CLR; /**< Status 1, offset: 0x218 */ __IO uint32_t STAT1_TOG; /**< Status 1, offset: 0x21C */ __IO uint32_t DATA1; /**< Data 1, offset: 0x220 */ __IO uint32_t DATA1_SET; /**< Data 1, offset: 0x224 */ __IO uint32_t DATA1_CLR; /**< Data 1, offset: 0x228 */ __IO uint32_t DATA1_TOG; /**< Data 1, offset: 0x22C */ uint8_t RESERVED_1[32]; __IO uint32_t THR_CTRL45; /**< Threshold Control 45, offset: 0x250 */ __IO uint32_t THR_CTRL45_SET; /**< Threshold Control 45, offset: 0x254 */ __IO uint32_t THR_CTRL45_CLR; /**< Threshold Control 45, offset: 0x258 */ __IO uint32_t THR_CTRL45_TOG; /**< Threshold Control 45, offset: 0x25C */ uint8_t RESERVED_2[16]; __IO uint32_t PERIOD_CTRL; /**< Measurement Period Control, offset: 0x270 */ __IO uint32_t PERIOD_CTRL_SET; /**< Measurement Period Control, offset: 0x274 */ __IO uint32_t PERIOD_CTRL_CLR; /**< Measurement Period Control, offset: 0x278 */ __IO uint32_t PERIOD_CTRL_TOG; /**< Measurement Period Control, offset: 0x27C */ __IO uint32_t REF_DIV; /**< Reference Clock Divider Control, offset: 0x280 */ uint8_t RESERVED_3[44]; __IO uint32_t PUD_ST_CTRL; /**< Power-Up Delay and Self-Test Control, offset: 0x2B0 */ __IO uint32_t PUD_ST_CTRL_SET; /**< Power-Up Delay and Self-Test Control, offset: 0x2B4 */ __IO uint32_t PUD_ST_CTRL_CLR; /**< Power-Up Delay and Self-Test Control, offset: 0x2B8 */ __IO uint32_t PUD_ST_CTRL_TOG; /**< Power-Up Delay and Self-Test Control, offset: 0x2BC */ uint8_t RESERVED_4[32]; __IO uint32_t TRIM1; /**< Trim Control 1, offset: 0x2E0 */ __IO uint32_t TRIM1_SET; /**< Trim Control 1, offset: 0x2E4 */ __IO uint32_t TRIM1_CLR; /**< Trim Control 1, offset: 0x2E8 */ __IO uint32_t TRIM1_TOG; /**< Trim Control 1, offset: 0x2EC */ __IO uint32_t TRIM2; /**< Trim Control 2, offset: 0x2F0 */ __IO uint32_t TRIM2_SET; /**< Trim Control 2, offset: 0x2F4 */ __IO uint32_t TRIM2_CLR; /**< Trim Control 2, offset: 0x2F8 */ __IO uint32_t TRIM2_TOG; /**< Trim Control 2, offset: 0x2FC */ } TMPSNS_Type; /* ---------------------------------------------------------------------------- -- TMPSNS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TMPSNS_Register_Masks TMPSNS Register Masks * @{ */ /*! @name CTRL0 - Control 0 */ /*! @{ */ #define TMPSNS_CTRL0_THR0_MODE_MASK (0x3U) #define TMPSNS_CTRL0_THR0_MODE_SHIFT (0U) /*! THR0_MODE - Threshold0 Comparator Mode * 0b00..Less than or equal to threshold * 0b01..Greater than threshold * 0b10..High to low temperature data transition at threshold * 0b11..Low to high temperature data transition at threshold */ #define TMPSNS_CTRL0_THR0_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_THR0_MODE_SHIFT)) & TMPSNS_CTRL0_THR0_MODE_MASK) #define TMPSNS_CTRL0_THR1_MODE_MASK (0xCU) #define TMPSNS_CTRL0_THR1_MODE_SHIFT (2U) /*! THR1_MODE - Threshold1 Comparator Mode * 0b00..Less than or equal to threshold * 0b01..Greater than threshold * 0b10..High to low temperature data transition at threshold * 0b11..Low to high temperature data transition at threshold */ #define TMPSNS_CTRL0_THR1_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_THR1_MODE_SHIFT)) & TMPSNS_CTRL0_THR1_MODE_MASK) #define TMPSNS_CTRL0_THR2_MODE_MASK (0x30U) #define TMPSNS_CTRL0_THR2_MODE_SHIFT (4U) /*! THR2_MODE - Threshold2 Comparator Mode * 0b00..Less than or equal to threshold * 0b01..Greater than threshold * 0b10..High to low temperature data transition at threshold * 0b11..Low to high temperature data transition at threshold */ #define TMPSNS_CTRL0_THR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_THR2_MODE_SHIFT)) & TMPSNS_CTRL0_THR2_MODE_MASK) #define TMPSNS_CTRL0_THR0_IE_MASK (0x100U) #define TMPSNS_CTRL0_THR0_IE_SHIFT (8U) /*! THR0_IE - Threshold0 Comparator Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL0_THR0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_THR0_IE_SHIFT)) & TMPSNS_CTRL0_THR0_IE_MASK) #define TMPSNS_CTRL0_THR1_IE_MASK (0x200U) #define TMPSNS_CTRL0_THR1_IE_SHIFT (9U) /*! THR1_IE - Threshold1 Comparator Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL0_THR1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_THR1_IE_SHIFT)) & TMPSNS_CTRL0_THR1_IE_MASK) #define TMPSNS_CTRL0_THR2_IE_MASK (0x400U) #define TMPSNS_CTRL0_THR2_IE_SHIFT (10U) /*! THR2_IE - Threshold2 Comparator Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL0_THR2_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_THR2_IE_SHIFT)) & TMPSNS_CTRL0_THR2_IE_MASK) #define TMPSNS_CTRL0_N_FILT_0_MASK (0xF000U) #define TMPSNS_CTRL0_N_FILT_0_SHIFT (12U) /*! N_FILT_0 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL0_N_FILT_0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_N_FILT_0_SHIFT)) & TMPSNS_CTRL0_N_FILT_0_MASK) #define TMPSNS_CTRL0_DRDY0_IE_MASK (0x10000U) #define TMPSNS_CTRL0_DRDY0_IE_SHIFT (16U) /*! DRDY0_IE - Data-Ready Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL0_DRDY0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_DRDY0_IE_SHIFT)) & TMPSNS_CTRL0_DRDY0_IE_MASK) #define TMPSNS_CTRL0_FILT0_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL0_FILT0_CNT_CLR_SHIFT (20U) /*! FILT0_CNT_CLR - Filter 0 Counter Clear * 0b0..Settle to 0 after clearing the counter * 0b1..Clear the internal counter */ #define TMPSNS_CTRL0_FILT0_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_FILT0_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_FILT0_CNT_CLR_MASK) #define TMPSNS_CTRL0_FILT1_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL0_FILT1_CNT_CLR_SHIFT (21U) /*! FILT1_CNT_CLR - Filter 1 Counter Clear * 0b0..Settle to 0 after clearing the counter * 0b1..Clear the internal counter */ #define TMPSNS_CTRL0_FILT1_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_FILT1_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_FILT1_CNT_CLR_MASK) #define TMPSNS_CTRL0_FILT2_CNT_CLR_MASK (0x400000U) #define TMPSNS_CTRL0_FILT2_CNT_CLR_SHIFT (22U) /*! FILT2_CNT_CLR - Filter 2 Counter Clear * 0b0..Settle to 0 after clearing the counter * 0b1..Clear the internal counter */ #define TMPSNS_CTRL0_FILT2_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_FILT2_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_FILT2_CNT_CLR_MASK) /*! @} */ /*! @name CTRL0_SET - Control 0 */ /*! @{ */ #define TMPSNS_CTRL0_SET_THR0_MODE_MASK (0x3U) #define TMPSNS_CTRL0_SET_THR0_MODE_SHIFT (0U) /*! THR0_MODE - Threshold0 Comparator Mode */ #define TMPSNS_CTRL0_SET_THR0_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_THR0_MODE_SHIFT)) & TMPSNS_CTRL0_SET_THR0_MODE_MASK) #define TMPSNS_CTRL0_SET_THR1_MODE_MASK (0xCU) #define TMPSNS_CTRL0_SET_THR1_MODE_SHIFT (2U) /*! THR1_MODE - Threshold1 Comparator Mode */ #define TMPSNS_CTRL0_SET_THR1_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_THR1_MODE_SHIFT)) & TMPSNS_CTRL0_SET_THR1_MODE_MASK) #define TMPSNS_CTRL0_SET_THR2_MODE_MASK (0x30U) #define TMPSNS_CTRL0_SET_THR2_MODE_SHIFT (4U) /*! THR2_MODE - Threshold2 Comparator Mode */ #define TMPSNS_CTRL0_SET_THR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_THR2_MODE_SHIFT)) & TMPSNS_CTRL0_SET_THR2_MODE_MASK) #define TMPSNS_CTRL0_SET_THR0_IE_MASK (0x100U) #define TMPSNS_CTRL0_SET_THR0_IE_SHIFT (8U) /*! THR0_IE - Threshold0 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_SET_THR0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_THR0_IE_SHIFT)) & TMPSNS_CTRL0_SET_THR0_IE_MASK) #define TMPSNS_CTRL0_SET_THR1_IE_MASK (0x200U) #define TMPSNS_CTRL0_SET_THR1_IE_SHIFT (9U) /*! THR1_IE - Threshold1 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_SET_THR1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_THR1_IE_SHIFT)) & TMPSNS_CTRL0_SET_THR1_IE_MASK) #define TMPSNS_CTRL0_SET_THR2_IE_MASK (0x400U) #define TMPSNS_CTRL0_SET_THR2_IE_SHIFT (10U) /*! THR2_IE - Threshold2 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_SET_THR2_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_THR2_IE_SHIFT)) & TMPSNS_CTRL0_SET_THR2_IE_MASK) #define TMPSNS_CTRL0_SET_N_FILT_0_MASK (0xF000U) #define TMPSNS_CTRL0_SET_N_FILT_0_SHIFT (12U) /*! N_FILT_0 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL0_SET_N_FILT_0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_N_FILT_0_SHIFT)) & TMPSNS_CTRL0_SET_N_FILT_0_MASK) #define TMPSNS_CTRL0_SET_DRDY0_IE_MASK (0x10000U) #define TMPSNS_CTRL0_SET_DRDY0_IE_SHIFT (16U) /*! DRDY0_IE - Data-Ready Interrupt Enable */ #define TMPSNS_CTRL0_SET_DRDY0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_DRDY0_IE_SHIFT)) & TMPSNS_CTRL0_SET_DRDY0_IE_MASK) #define TMPSNS_CTRL0_SET_FILT0_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL0_SET_FILT0_CNT_CLR_SHIFT (20U) /*! FILT0_CNT_CLR - Filter 0 Counter Clear */ #define TMPSNS_CTRL0_SET_FILT0_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_FILT0_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_SET_FILT0_CNT_CLR_MASK) #define TMPSNS_CTRL0_SET_FILT1_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL0_SET_FILT1_CNT_CLR_SHIFT (21U) /*! FILT1_CNT_CLR - Filter 1 Counter Clear */ #define TMPSNS_CTRL0_SET_FILT1_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_FILT1_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_SET_FILT1_CNT_CLR_MASK) #define TMPSNS_CTRL0_SET_FILT2_CNT_CLR_MASK (0x400000U) #define TMPSNS_CTRL0_SET_FILT2_CNT_CLR_SHIFT (22U) /*! FILT2_CNT_CLR - Filter 2 Counter Clear */ #define TMPSNS_CTRL0_SET_FILT2_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_FILT2_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_SET_FILT2_CNT_CLR_MASK) /*! @} */ /*! @name CTRL0_CLR - Control 0 */ /*! @{ */ #define TMPSNS_CTRL0_CLR_THR0_MODE_MASK (0x3U) #define TMPSNS_CTRL0_CLR_THR0_MODE_SHIFT (0U) /*! THR0_MODE - Threshold0 Comparator Mode */ #define TMPSNS_CTRL0_CLR_THR0_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_THR0_MODE_SHIFT)) & TMPSNS_CTRL0_CLR_THR0_MODE_MASK) #define TMPSNS_CTRL0_CLR_THR1_MODE_MASK (0xCU) #define TMPSNS_CTRL0_CLR_THR1_MODE_SHIFT (2U) /*! THR1_MODE - Threshold1 Comparator Mode */ #define TMPSNS_CTRL0_CLR_THR1_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_THR1_MODE_SHIFT)) & TMPSNS_CTRL0_CLR_THR1_MODE_MASK) #define TMPSNS_CTRL0_CLR_THR2_MODE_MASK (0x30U) #define TMPSNS_CTRL0_CLR_THR2_MODE_SHIFT (4U) /*! THR2_MODE - Threshold2 Comparator Mode */ #define TMPSNS_CTRL0_CLR_THR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_THR2_MODE_SHIFT)) & TMPSNS_CTRL0_CLR_THR2_MODE_MASK) #define TMPSNS_CTRL0_CLR_THR0_IE_MASK (0x100U) #define TMPSNS_CTRL0_CLR_THR0_IE_SHIFT (8U) /*! THR0_IE - Threshold0 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_CLR_THR0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_THR0_IE_SHIFT)) & TMPSNS_CTRL0_CLR_THR0_IE_MASK) #define TMPSNS_CTRL0_CLR_THR1_IE_MASK (0x200U) #define TMPSNS_CTRL0_CLR_THR1_IE_SHIFT (9U) /*! THR1_IE - Threshold1 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_CLR_THR1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_THR1_IE_SHIFT)) & TMPSNS_CTRL0_CLR_THR1_IE_MASK) #define TMPSNS_CTRL0_CLR_THR2_IE_MASK (0x400U) #define TMPSNS_CTRL0_CLR_THR2_IE_SHIFT (10U) /*! THR2_IE - Threshold2 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_CLR_THR2_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_THR2_IE_SHIFT)) & TMPSNS_CTRL0_CLR_THR2_IE_MASK) #define TMPSNS_CTRL0_CLR_N_FILT_0_MASK (0xF000U) #define TMPSNS_CTRL0_CLR_N_FILT_0_SHIFT (12U) /*! N_FILT_0 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL0_CLR_N_FILT_0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_N_FILT_0_SHIFT)) & TMPSNS_CTRL0_CLR_N_FILT_0_MASK) #define TMPSNS_CTRL0_CLR_DRDY0_IE_MASK (0x10000U) #define TMPSNS_CTRL0_CLR_DRDY0_IE_SHIFT (16U) /*! DRDY0_IE - Data-Ready Interrupt Enable */ #define TMPSNS_CTRL0_CLR_DRDY0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_DRDY0_IE_SHIFT)) & TMPSNS_CTRL0_CLR_DRDY0_IE_MASK) #define TMPSNS_CTRL0_CLR_FILT0_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL0_CLR_FILT0_CNT_CLR_SHIFT (20U) /*! FILT0_CNT_CLR - Filter 0 Counter Clear */ #define TMPSNS_CTRL0_CLR_FILT0_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_FILT0_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_CLR_FILT0_CNT_CLR_MASK) #define TMPSNS_CTRL0_CLR_FILT1_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL0_CLR_FILT1_CNT_CLR_SHIFT (21U) /*! FILT1_CNT_CLR - Filter 1 Counter Clear */ #define TMPSNS_CTRL0_CLR_FILT1_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_FILT1_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_CLR_FILT1_CNT_CLR_MASK) #define TMPSNS_CTRL0_CLR_FILT2_CNT_CLR_MASK (0x400000U) #define TMPSNS_CTRL0_CLR_FILT2_CNT_CLR_SHIFT (22U) /*! FILT2_CNT_CLR - Filter 2 Counter Clear */ #define TMPSNS_CTRL0_CLR_FILT2_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_FILT2_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_CLR_FILT2_CNT_CLR_MASK) /*! @} */ /*! @name CTRL0_TOG - Control 0 */ /*! @{ */ #define TMPSNS_CTRL0_TOG_THR0_MODE_MASK (0x3U) #define TMPSNS_CTRL0_TOG_THR0_MODE_SHIFT (0U) /*! THR0_MODE - Threshold0 Comparator Mode */ #define TMPSNS_CTRL0_TOG_THR0_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_THR0_MODE_SHIFT)) & TMPSNS_CTRL0_TOG_THR0_MODE_MASK) #define TMPSNS_CTRL0_TOG_THR1_MODE_MASK (0xCU) #define TMPSNS_CTRL0_TOG_THR1_MODE_SHIFT (2U) /*! THR1_MODE - Threshold1 Comparator Mode */ #define TMPSNS_CTRL0_TOG_THR1_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_THR1_MODE_SHIFT)) & TMPSNS_CTRL0_TOG_THR1_MODE_MASK) #define TMPSNS_CTRL0_TOG_THR2_MODE_MASK (0x30U) #define TMPSNS_CTRL0_TOG_THR2_MODE_SHIFT (4U) /*! THR2_MODE - Threshold2 Comparator Mode */ #define TMPSNS_CTRL0_TOG_THR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_THR2_MODE_SHIFT)) & TMPSNS_CTRL0_TOG_THR2_MODE_MASK) #define TMPSNS_CTRL0_TOG_THR0_IE_MASK (0x100U) #define TMPSNS_CTRL0_TOG_THR0_IE_SHIFT (8U) /*! THR0_IE - Threshold0 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_TOG_THR0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_THR0_IE_SHIFT)) & TMPSNS_CTRL0_TOG_THR0_IE_MASK) #define TMPSNS_CTRL0_TOG_THR1_IE_MASK (0x200U) #define TMPSNS_CTRL0_TOG_THR1_IE_SHIFT (9U) /*! THR1_IE - Threshold1 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_TOG_THR1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_THR1_IE_SHIFT)) & TMPSNS_CTRL0_TOG_THR1_IE_MASK) #define TMPSNS_CTRL0_TOG_THR2_IE_MASK (0x400U) #define TMPSNS_CTRL0_TOG_THR2_IE_SHIFT (10U) /*! THR2_IE - Threshold2 Comparator Interrupt Enable */ #define TMPSNS_CTRL0_TOG_THR2_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_THR2_IE_SHIFT)) & TMPSNS_CTRL0_TOG_THR2_IE_MASK) #define TMPSNS_CTRL0_TOG_N_FILT_0_MASK (0xF000U) #define TMPSNS_CTRL0_TOG_N_FILT_0_SHIFT (12U) /*! N_FILT_0 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL0_TOG_N_FILT_0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_N_FILT_0_SHIFT)) & TMPSNS_CTRL0_TOG_N_FILT_0_MASK) #define TMPSNS_CTRL0_TOG_DRDY0_IE_MASK (0x10000U) #define TMPSNS_CTRL0_TOG_DRDY0_IE_SHIFT (16U) /*! DRDY0_IE - Data-Ready Interrupt Enable */ #define TMPSNS_CTRL0_TOG_DRDY0_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_DRDY0_IE_SHIFT)) & TMPSNS_CTRL0_TOG_DRDY0_IE_MASK) #define TMPSNS_CTRL0_TOG_FILT0_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL0_TOG_FILT0_CNT_CLR_SHIFT (20U) /*! FILT0_CNT_CLR - Filter 0 Counter Clear */ #define TMPSNS_CTRL0_TOG_FILT0_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_FILT0_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_TOG_FILT0_CNT_CLR_MASK) #define TMPSNS_CTRL0_TOG_FILT1_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL0_TOG_FILT1_CNT_CLR_SHIFT (21U) /*! FILT1_CNT_CLR - Filter 1 Counter Clear */ #define TMPSNS_CTRL0_TOG_FILT1_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_FILT1_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_TOG_FILT1_CNT_CLR_MASK) #define TMPSNS_CTRL0_TOG_FILT2_CNT_CLR_MASK (0x400000U) #define TMPSNS_CTRL0_TOG_FILT2_CNT_CLR_SHIFT (22U) /*! FILT2_CNT_CLR - Filter 2 Counter Clear */ #define TMPSNS_CTRL0_TOG_FILT2_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_FILT2_CNT_CLR_SHIFT)) & TMPSNS_CTRL0_TOG_FILT2_CNT_CLR_MASK) /*! @} */ /*! @name STAT0 - Status 0 */ /*! @{ */ #define TMPSNS_STAT0_THR0_IF_MASK (0x100U) #define TMPSNS_STAT0_THR0_IF_SHIFT (8U) /*! THR0_IF - Threshold0 Status Flag * 0b0..Event did not occur * 0b1..Event occurred * 0b0..No effect * 0b1..Clear the flag */ #define TMPSNS_STAT0_THR0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR0_IF_SHIFT)) & TMPSNS_STAT0_THR0_IF_MASK) #define TMPSNS_STAT0_THR1_IF_MASK (0x200U) #define TMPSNS_STAT0_THR1_IF_SHIFT (9U) /*! THR1_IF - Threshold1 Status Flag * 0b0..Event did not occur * 0b1..Event occurred * 0b0..No effect * 0b1..Clear the flag */ #define TMPSNS_STAT0_THR1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR1_IF_SHIFT)) & TMPSNS_STAT0_THR1_IF_MASK) #define TMPSNS_STAT0_THR2_IF_MASK (0x400U) #define TMPSNS_STAT0_THR2_IF_SHIFT (10U) /*! THR2_IF - Threshold2 Status Flag * 0b0..Event did not occur * 0b1..Event occurred * 0b0..No effect * 0b1..Clear the flag */ #define TMPSNS_STAT0_THR2_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR2_IF_SHIFT)) & TMPSNS_STAT0_THR2_IF_MASK) #define TMPSNS_STAT0_THR0_STAT_MASK (0x1000U) #define TMPSNS_STAT0_THR0_STAT_SHIFT (12U) /*! THR0_STAT - Threshold0 State */ #define TMPSNS_STAT0_THR0_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR0_STAT_SHIFT)) & TMPSNS_STAT0_THR0_STAT_MASK) #define TMPSNS_STAT0_THR1_STAT_MASK (0x2000U) #define TMPSNS_STAT0_THR1_STAT_SHIFT (13U) /*! THR1_STAT - Threshold1 State */ #define TMPSNS_STAT0_THR1_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR1_STAT_SHIFT)) & TMPSNS_STAT0_THR1_STAT_MASK) #define TMPSNS_STAT0_THR2_STAT_MASK (0x4000U) #define TMPSNS_STAT0_THR2_STAT_SHIFT (14U) /*! THR2_STAT - Threshold2 State */ #define TMPSNS_STAT0_THR2_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_THR2_STAT_SHIFT)) & TMPSNS_STAT0_THR2_STAT_MASK) #define TMPSNS_STAT0_DRDY0_IF_MASK (0x10000U) #define TMPSNS_STAT0_DRDY0_IF_SHIFT (16U) /*! DRDY0_IF - Data Ready Flag * 0b0..No new data available * 0b1..New data available */ #define TMPSNS_STAT0_DRDY0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_DRDY0_IF_SHIFT)) & TMPSNS_STAT0_DRDY0_IF_MASK) #define TMPSNS_STAT0_IDLE_MASK (0x80000000U) #define TMPSNS_STAT0_IDLE_SHIFT (31U) /*! IDLE - Idle State * 0b0..Conversion * 0b1..Idle */ #define TMPSNS_STAT0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_IDLE_SHIFT)) & TMPSNS_STAT0_IDLE_MASK) /*! @} */ /*! @name STAT0_SET - Status 0 */ /*! @{ */ #define TMPSNS_STAT0_SET_THR0_IF_MASK (0x100U) #define TMPSNS_STAT0_SET_THR0_IF_SHIFT (8U) /*! THR0_IF - Threshold0 Status Flag */ #define TMPSNS_STAT0_SET_THR0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_THR0_IF_SHIFT)) & TMPSNS_STAT0_SET_THR0_IF_MASK) #define TMPSNS_STAT0_SET_THR1_IF_MASK (0x200U) #define TMPSNS_STAT0_SET_THR1_IF_SHIFT (9U) /*! THR1_IF - Threshold1 Status Flag */ #define TMPSNS_STAT0_SET_THR1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_THR1_IF_SHIFT)) & TMPSNS_STAT0_SET_THR1_IF_MASK) #define TMPSNS_STAT0_SET_THR2_IF_MASK (0x400U) #define TMPSNS_STAT0_SET_THR2_IF_SHIFT (10U) /*! THR2_IF - Threshold2 Status Flag */ #define TMPSNS_STAT0_SET_THR2_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_THR2_IF_SHIFT)) & TMPSNS_STAT0_SET_THR2_IF_MASK) #define TMPSNS_STAT0_SET_THR0_STAT_MASK (0x1000U) #define TMPSNS_STAT0_SET_THR0_STAT_SHIFT (12U) /*! THR0_STAT - Threshold0 State */ #define TMPSNS_STAT0_SET_THR0_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_THR0_STAT_SHIFT)) & TMPSNS_STAT0_SET_THR0_STAT_MASK) #define TMPSNS_STAT0_SET_THR1_STAT_MASK (0x2000U) #define TMPSNS_STAT0_SET_THR1_STAT_SHIFT (13U) /*! THR1_STAT - Threshold1 State */ #define TMPSNS_STAT0_SET_THR1_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_THR1_STAT_SHIFT)) & TMPSNS_STAT0_SET_THR1_STAT_MASK) #define TMPSNS_STAT0_SET_THR2_STAT_MASK (0x4000U) #define TMPSNS_STAT0_SET_THR2_STAT_SHIFT (14U) /*! THR2_STAT - Threshold2 State */ #define TMPSNS_STAT0_SET_THR2_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_THR2_STAT_SHIFT)) & TMPSNS_STAT0_SET_THR2_STAT_MASK) #define TMPSNS_STAT0_SET_DRDY0_IF_MASK (0x10000U) #define TMPSNS_STAT0_SET_DRDY0_IF_SHIFT (16U) /*! DRDY0_IF - Data Ready Flag */ #define TMPSNS_STAT0_SET_DRDY0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_DRDY0_IF_SHIFT)) & TMPSNS_STAT0_SET_DRDY0_IF_MASK) #define TMPSNS_STAT0_SET_IDLE_MASK (0x80000000U) #define TMPSNS_STAT0_SET_IDLE_SHIFT (31U) /*! IDLE - Idle State */ #define TMPSNS_STAT0_SET_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_SET_IDLE_SHIFT)) & TMPSNS_STAT0_SET_IDLE_MASK) /*! @} */ /*! @name STAT0_CLR - Status 0 */ /*! @{ */ #define TMPSNS_STAT0_CLR_THR0_IF_MASK (0x100U) #define TMPSNS_STAT0_CLR_THR0_IF_SHIFT (8U) /*! THR0_IF - Threshold0 Status Flag */ #define TMPSNS_STAT0_CLR_THR0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_THR0_IF_SHIFT)) & TMPSNS_STAT0_CLR_THR0_IF_MASK) #define TMPSNS_STAT0_CLR_THR1_IF_MASK (0x200U) #define TMPSNS_STAT0_CLR_THR1_IF_SHIFT (9U) /*! THR1_IF - Threshold1 Status Flag */ #define TMPSNS_STAT0_CLR_THR1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_THR1_IF_SHIFT)) & TMPSNS_STAT0_CLR_THR1_IF_MASK) #define TMPSNS_STAT0_CLR_THR2_IF_MASK (0x400U) #define TMPSNS_STAT0_CLR_THR2_IF_SHIFT (10U) /*! THR2_IF - Threshold2 Status Flag */ #define TMPSNS_STAT0_CLR_THR2_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_THR2_IF_SHIFT)) & TMPSNS_STAT0_CLR_THR2_IF_MASK) #define TMPSNS_STAT0_CLR_THR0_STAT_MASK (0x1000U) #define TMPSNS_STAT0_CLR_THR0_STAT_SHIFT (12U) /*! THR0_STAT - Threshold0 State */ #define TMPSNS_STAT0_CLR_THR0_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_THR0_STAT_SHIFT)) & TMPSNS_STAT0_CLR_THR0_STAT_MASK) #define TMPSNS_STAT0_CLR_THR1_STAT_MASK (0x2000U) #define TMPSNS_STAT0_CLR_THR1_STAT_SHIFT (13U) /*! THR1_STAT - Threshold1 State */ #define TMPSNS_STAT0_CLR_THR1_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_THR1_STAT_SHIFT)) & TMPSNS_STAT0_CLR_THR1_STAT_MASK) #define TMPSNS_STAT0_CLR_THR2_STAT_MASK (0x4000U) #define TMPSNS_STAT0_CLR_THR2_STAT_SHIFT (14U) /*! THR2_STAT - Threshold2 State */ #define TMPSNS_STAT0_CLR_THR2_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_THR2_STAT_SHIFT)) & TMPSNS_STAT0_CLR_THR2_STAT_MASK) #define TMPSNS_STAT0_CLR_DRDY0_IF_MASK (0x10000U) #define TMPSNS_STAT0_CLR_DRDY0_IF_SHIFT (16U) /*! DRDY0_IF - Data Ready Flag */ #define TMPSNS_STAT0_CLR_DRDY0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_DRDY0_IF_SHIFT)) & TMPSNS_STAT0_CLR_DRDY0_IF_MASK) #define TMPSNS_STAT0_CLR_IDLE_MASK (0x80000000U) #define TMPSNS_STAT0_CLR_IDLE_SHIFT (31U) /*! IDLE - Idle State */ #define TMPSNS_STAT0_CLR_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_CLR_IDLE_SHIFT)) & TMPSNS_STAT0_CLR_IDLE_MASK) /*! @} */ /*! @name STAT0_TOG - Status 0 */ /*! @{ */ #define TMPSNS_STAT0_TOG_THR0_IF_MASK (0x100U) #define TMPSNS_STAT0_TOG_THR0_IF_SHIFT (8U) /*! THR0_IF - Threshold0 Status Flag */ #define TMPSNS_STAT0_TOG_THR0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_THR0_IF_SHIFT)) & TMPSNS_STAT0_TOG_THR0_IF_MASK) #define TMPSNS_STAT0_TOG_THR1_IF_MASK (0x200U) #define TMPSNS_STAT0_TOG_THR1_IF_SHIFT (9U) /*! THR1_IF - Threshold1 Status Flag */ #define TMPSNS_STAT0_TOG_THR1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_THR1_IF_SHIFT)) & TMPSNS_STAT0_TOG_THR1_IF_MASK) #define TMPSNS_STAT0_TOG_THR2_IF_MASK (0x400U) #define TMPSNS_STAT0_TOG_THR2_IF_SHIFT (10U) /*! THR2_IF - Threshold2 Status Flag */ #define TMPSNS_STAT0_TOG_THR2_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_THR2_IF_SHIFT)) & TMPSNS_STAT0_TOG_THR2_IF_MASK) #define TMPSNS_STAT0_TOG_THR0_STAT_MASK (0x1000U) #define TMPSNS_STAT0_TOG_THR0_STAT_SHIFT (12U) /*! THR0_STAT - Threshold0 State */ #define TMPSNS_STAT0_TOG_THR0_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_THR0_STAT_SHIFT)) & TMPSNS_STAT0_TOG_THR0_STAT_MASK) #define TMPSNS_STAT0_TOG_THR1_STAT_MASK (0x2000U) #define TMPSNS_STAT0_TOG_THR1_STAT_SHIFT (13U) /*! THR1_STAT - Threshold1 State */ #define TMPSNS_STAT0_TOG_THR1_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_THR1_STAT_SHIFT)) & TMPSNS_STAT0_TOG_THR1_STAT_MASK) #define TMPSNS_STAT0_TOG_THR2_STAT_MASK (0x4000U) #define TMPSNS_STAT0_TOG_THR2_STAT_SHIFT (14U) /*! THR2_STAT - Threshold2 State */ #define TMPSNS_STAT0_TOG_THR2_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_THR2_STAT_SHIFT)) & TMPSNS_STAT0_TOG_THR2_STAT_MASK) #define TMPSNS_STAT0_TOG_DRDY0_IF_MASK (0x10000U) #define TMPSNS_STAT0_TOG_DRDY0_IF_SHIFT (16U) /*! DRDY0_IF - Data Ready Flag */ #define TMPSNS_STAT0_TOG_DRDY0_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_DRDY0_IF_SHIFT)) & TMPSNS_STAT0_TOG_DRDY0_IF_MASK) #define TMPSNS_STAT0_TOG_IDLE_MASK (0x80000000U) #define TMPSNS_STAT0_TOG_IDLE_SHIFT (31U) /*! IDLE - Idle State */ #define TMPSNS_STAT0_TOG_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT0_TOG_IDLE_SHIFT)) & TMPSNS_STAT0_TOG_IDLE_MASK) /*! @} */ /*! @name DATA0 - Data 0 */ /*! @{ */ #define TMPSNS_DATA0_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA0_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA0_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA0_DATA_VAL_SHIFT)) & TMPSNS_DATA0_DATA_VAL_MASK) /*! @} */ /*! @name DATA0_SET - Data 0 */ /*! @{ */ #define TMPSNS_DATA0_SET_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA0_SET_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA0_SET_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA0_SET_DATA_VAL_SHIFT)) & TMPSNS_DATA0_SET_DATA_VAL_MASK) /*! @} */ /*! @name DATA0_CLR - Data 0 */ /*! @{ */ #define TMPSNS_DATA0_CLR_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA0_CLR_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA0_CLR_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA0_CLR_DATA_VAL_SHIFT)) & TMPSNS_DATA0_CLR_DATA_VAL_MASK) /*! @} */ /*! @name DATA0_TOG - Data 0 */ /*! @{ */ #define TMPSNS_DATA0_TOG_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA0_TOG_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA0_TOG_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA0_TOG_DATA_VAL_SHIFT)) & TMPSNS_DATA0_TOG_DATA_VAL_MASK) /*! @} */ /*! @name THR_CTRL01 - Threshold Control 01 */ /*! @{ */ #define TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD0_MASK (0xFFFFU) #define TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD0_SHIFT (0U) /*! TEMPERATURE_THRESHOLD0 - Temperature Threshold0 */ #define TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD0_SHIFT)) & TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD0_MASK) #define TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD1_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD1_SHIFT (16U) /*! TEMPERATURE_THRESHOLD1 - Temperature Threshold1 */ #define TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD1_SHIFT)) & TMPSNS_THR_CTRL01_TEMPERATURE_THRESHOLD1_MASK) /*! @} */ /*! @name THR_CTRL01_SET - Threshold Control 01 */ /*! @{ */ #define TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD0_MASK (0xFFFFU) #define TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD0_SHIFT (0U) /*! TEMPERATURE_THRESHOLD0 - Temperature Threshold0 */ #define TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD0_SHIFT)) & TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD0_MASK) #define TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD1_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD1_SHIFT (16U) /*! TEMPERATURE_THRESHOLD1 - Temperature Threshold1 */ #define TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD1_SHIFT)) & TMPSNS_THR_CTRL01_SET_TEMPERATURE_THRESHOLD1_MASK) /*! @} */ /*! @name THR_CTRL01_CLR - Threshold Control 01 */ /*! @{ */ #define TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD0_MASK (0xFFFFU) #define TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD0_SHIFT (0U) /*! TEMPERATURE_THRESHOLD0 - Temperature Threshold0 */ #define TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD0_SHIFT)) & TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD0_MASK) #define TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD1_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD1_SHIFT (16U) /*! TEMPERATURE_THRESHOLD1 - Temperature Threshold1 */ #define TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD1_SHIFT)) & TMPSNS_THR_CTRL01_CLR_TEMPERATURE_THRESHOLD1_MASK) /*! @} */ /*! @name THR_CTRL01_TOG - Threshold Control 01 */ /*! @{ */ #define TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD0_MASK (0xFFFFU) #define TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD0_SHIFT (0U) /*! TEMPERATURE_THRESHOLD0 - Temperature Threshold0 */ #define TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD0(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD0_SHIFT)) & TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD0_MASK) #define TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD1_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD1_SHIFT (16U) /*! TEMPERATURE_THRESHOLD1 - Temperature Threshold1 */ #define TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD1_SHIFT)) & TMPSNS_THR_CTRL01_TOG_TEMPERATURE_THRESHOLD1_MASK) /*! @} */ /*! @name THR_CTRL23 - Threshold Control 23 */ /*! @{ */ #define TMPSNS_THR_CTRL23_TEMPERATURE_THRESHOLD2_MASK (0xFFFFU) #define TMPSNS_THR_CTRL23_TEMPERATURE_THRESHOLD2_SHIFT (0U) /*! TEMPERATURE_THRESHOLD2 - Temperature Threshold2 */ #define TMPSNS_THR_CTRL23_TEMPERATURE_THRESHOLD2(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL23_TEMPERATURE_THRESHOLD2_SHIFT)) & TMPSNS_THR_CTRL23_TEMPERATURE_THRESHOLD2_MASK) /*! @} */ /*! @name THR_CTRL23_SET - Threshold Control 23 */ /*! @{ */ #define TMPSNS_THR_CTRL23_SET_TEMPERATURE_THRESHOLD2_MASK (0xFFFFU) #define TMPSNS_THR_CTRL23_SET_TEMPERATURE_THRESHOLD2_SHIFT (0U) /*! TEMPERATURE_THRESHOLD2 - Temperature Threshold2 */ #define TMPSNS_THR_CTRL23_SET_TEMPERATURE_THRESHOLD2(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL23_SET_TEMPERATURE_THRESHOLD2_SHIFT)) & TMPSNS_THR_CTRL23_SET_TEMPERATURE_THRESHOLD2_MASK) /*! @} */ /*! @name THR_CTRL23_CLR - Threshold Control 23 */ /*! @{ */ #define TMPSNS_THR_CTRL23_CLR_TEMPERATURE_THRESHOLD2_MASK (0xFFFFU) #define TMPSNS_THR_CTRL23_CLR_TEMPERATURE_THRESHOLD2_SHIFT (0U) /*! TEMPERATURE_THRESHOLD2 - Temperature Threshold2 */ #define TMPSNS_THR_CTRL23_CLR_TEMPERATURE_THRESHOLD2(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL23_CLR_TEMPERATURE_THRESHOLD2_SHIFT)) & TMPSNS_THR_CTRL23_CLR_TEMPERATURE_THRESHOLD2_MASK) /*! @} */ /*! @name THR_CTRL23_TOG - Threshold Control 23 */ /*! @{ */ #define TMPSNS_THR_CTRL23_TOG_TEMPERATURE_THRESHOLD2_MASK (0xFFFFU) #define TMPSNS_THR_CTRL23_TOG_TEMPERATURE_THRESHOLD2_SHIFT (0U) /*! TEMPERATURE_THRESHOLD2 - Temperature Threshold2 */ #define TMPSNS_THR_CTRL23_TOG_TEMPERATURE_THRESHOLD2(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL23_TOG_TEMPERATURE_THRESHOLD2_SHIFT)) & TMPSNS_THR_CTRL23_TOG_TEMPERATURE_THRESHOLD2_MASK) /*! @} */ /*! @name CTRL1 - Control 1 */ /*! @{ */ #define TMPSNS_CTRL1_THR4_MODE_MASK (0x3U) #define TMPSNS_CTRL1_THR4_MODE_SHIFT (0U) /*! THR4_MODE - Threshold4 Comparator Mode * 0b00..Less than or equal to threshold * 0b01..Greater than threshold * 0b10..High to low temperature data transition at threshold * 0b11..Low to high temperature data transition at threshold */ #define TMPSNS_CTRL1_THR4_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_THR4_MODE_SHIFT)) & TMPSNS_CTRL1_THR4_MODE_MASK) #define TMPSNS_CTRL1_THR5_MODE_MASK (0xCU) #define TMPSNS_CTRL1_THR5_MODE_SHIFT (2U) /*! THR5_MODE - Threshold5 Comparator Mode * 0b00..Less than or equal to threshold * 0b01..Greater than threshold * 0b10..High to low temperature data transition at threshold * 0b11..Low to high temperature data transition at threshold */ #define TMPSNS_CTRL1_THR5_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_THR5_MODE_SHIFT)) & TMPSNS_CTRL1_THR5_MODE_MASK) #define TMPSNS_CTRL1_THR4_IE_MASK (0x100U) #define TMPSNS_CTRL1_THR4_IE_SHIFT (8U) /*! THR4_IE - Threshold Comparator4 Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL1_THR4_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_THR4_IE_SHIFT)) & TMPSNS_CTRL1_THR4_IE_MASK) #define TMPSNS_CTRL1_THR5_IE_MASK (0x200U) #define TMPSNS_CTRL1_THR5_IE_SHIFT (9U) /*! THR5_IE - Threshold Comparator5 Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL1_THR5_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_THR5_IE_SHIFT)) & TMPSNS_CTRL1_THR5_IE_MASK) #define TMPSNS_CTRL1_N_FILT_1_MASK (0xF000U) #define TMPSNS_CTRL1_N_FILT_1_SHIFT (12U) /*! N_FILT_1 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL1_N_FILT_1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_N_FILT_1_SHIFT)) & TMPSNS_CTRL1_N_FILT_1_MASK) #define TMPSNS_CTRL1_DRDY1_IE_MASK (0x10000U) #define TMPSNS_CTRL1_DRDY1_IE_SHIFT (16U) /*! DRDY1_IE - Data-Ready Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL1_DRDY1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_DRDY1_IE_SHIFT)) & TMPSNS_CTRL1_DRDY1_IE_MASK) #define TMPSNS_CTRL1_RESOLUTION_MASK (0xC0000U) #define TMPSNS_CTRL1_RESOLUTION_SHIFT (18U) /*! RESOLUTION - Resolution Mode * 0b00..0.59325 ms * 0b01..1.10525 ms * 0b10..2.12925 ms * 0b11..4.17725 ms */ #define TMPSNS_CTRL1_RESOLUTION(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RESOLUTION_SHIFT)) & TMPSNS_CTRL1_RESOLUTION_MASK) #define TMPSNS_CTRL1_FILT4_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL1_FILT4_CNT_CLR_SHIFT (20U) /*! FILT4_CNT_CLR - Filter 4 Counter Clear * 0b0..Settle to 0 after clearing the counter * 0b1..Clear the internal counter */ #define TMPSNS_CTRL1_FILT4_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FILT4_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_FILT4_CNT_CLR_MASK) #define TMPSNS_CTRL1_FILT5_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL1_FILT5_CNT_CLR_SHIFT (21U) /*! FILT5_CNT_CLR - Filter 5 Counter Clear * 0b0..Settle to 0 after clearing the counter * 0b1..Clear the internal counter */ #define TMPSNS_CTRL1_FILT5_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FILT5_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_FILT5_CNT_CLR_MASK) #define TMPSNS_CTRL1_MEAS_MODE_MASK (0x3000000U) #define TMPSNS_CTRL1_MEAS_MODE_SHIFT (24U) /*! MEAS_MODE - Measurement Mode * 0b00..Single One-Shot Measurement * 0b01..Continuous Measurement * 0b10..Periodic One-Shot Measurement * 0b11..Reserved */ #define TMPSNS_CTRL1_MEAS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_MEAS_MODE_SHIFT)) & TMPSNS_CTRL1_MEAS_MODE_MASK) #define TMPSNS_CTRL1_STOP_MASK (0x20000000U) #define TMPSNS_CTRL1_STOP_SHIFT (29U) /*! STOP - Stop Measurement * 0b0..Clear after conversion is over * 0b1..Stop the conversion */ #define TMPSNS_CTRL1_STOP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_STOP_SHIFT)) & TMPSNS_CTRL1_STOP_MASK) #define TMPSNS_CTRL1_START_MASK (0x40000000U) #define TMPSNS_CTRL1_START_SHIFT (30U) /*! START - Start Measurement * 0b0..No effect * 0b1..Start the measurement */ #define TMPSNS_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK) #define TMPSNS_CTRL1_ENABLE_MASK (0x80000000U) #define TMPSNS_CTRL1_ENABLE_SHIFT (31U) /*! ENABLE - TEMPSENSE Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_CTRL1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_ENABLE_SHIFT)) & TMPSNS_CTRL1_ENABLE_MASK) /*! @} */ /*! @name CTRL1_SET - Control 1 */ /*! @{ */ #define TMPSNS_CTRL1_SET_THR4_MODE_MASK (0x3U) #define TMPSNS_CTRL1_SET_THR4_MODE_SHIFT (0U) /*! THR4_MODE - Threshold4 Comparator Mode */ #define TMPSNS_CTRL1_SET_THR4_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_THR4_MODE_SHIFT)) & TMPSNS_CTRL1_SET_THR4_MODE_MASK) #define TMPSNS_CTRL1_SET_THR5_MODE_MASK (0xCU) #define TMPSNS_CTRL1_SET_THR5_MODE_SHIFT (2U) /*! THR5_MODE - Threshold5 Comparator Mode */ #define TMPSNS_CTRL1_SET_THR5_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_THR5_MODE_SHIFT)) & TMPSNS_CTRL1_SET_THR5_MODE_MASK) #define TMPSNS_CTRL1_SET_THR4_IE_MASK (0x100U) #define TMPSNS_CTRL1_SET_THR4_IE_SHIFT (8U) /*! THR4_IE - Threshold Comparator4 Interrupt Enable */ #define TMPSNS_CTRL1_SET_THR4_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_THR4_IE_SHIFT)) & TMPSNS_CTRL1_SET_THR4_IE_MASK) #define TMPSNS_CTRL1_SET_THR5_IE_MASK (0x200U) #define TMPSNS_CTRL1_SET_THR5_IE_SHIFT (9U) /*! THR5_IE - Threshold Comparator5 Interrupt Enable */ #define TMPSNS_CTRL1_SET_THR5_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_THR5_IE_SHIFT)) & TMPSNS_CTRL1_SET_THR5_IE_MASK) #define TMPSNS_CTRL1_SET_N_FILT_1_MASK (0xF000U) #define TMPSNS_CTRL1_SET_N_FILT_1_SHIFT (12U) /*! N_FILT_1 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL1_SET_N_FILT_1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_N_FILT_1_SHIFT)) & TMPSNS_CTRL1_SET_N_FILT_1_MASK) #define TMPSNS_CTRL1_SET_DRDY1_IE_MASK (0x10000U) #define TMPSNS_CTRL1_SET_DRDY1_IE_SHIFT (16U) /*! DRDY1_IE - Data-Ready Interrupt Enable */ #define TMPSNS_CTRL1_SET_DRDY1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_DRDY1_IE_SHIFT)) & TMPSNS_CTRL1_SET_DRDY1_IE_MASK) #define TMPSNS_CTRL1_SET_RESOLUTION_MASK (0xC0000U) #define TMPSNS_CTRL1_SET_RESOLUTION_SHIFT (18U) /*! RESOLUTION - Resolution Mode */ #define TMPSNS_CTRL1_SET_RESOLUTION(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RESOLUTION_SHIFT)) & TMPSNS_CTRL1_SET_RESOLUTION_MASK) #define TMPSNS_CTRL1_SET_FILT4_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL1_SET_FILT4_CNT_CLR_SHIFT (20U) /*! FILT4_CNT_CLR - Filter 4 Counter Clear */ #define TMPSNS_CTRL1_SET_FILT4_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FILT4_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_SET_FILT4_CNT_CLR_MASK) #define TMPSNS_CTRL1_SET_FILT5_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL1_SET_FILT5_CNT_CLR_SHIFT (21U) /*! FILT5_CNT_CLR - Filter 5 Counter Clear */ #define TMPSNS_CTRL1_SET_FILT5_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FILT5_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_SET_FILT5_CNT_CLR_MASK) #define TMPSNS_CTRL1_SET_MEAS_MODE_MASK (0x3000000U) #define TMPSNS_CTRL1_SET_MEAS_MODE_SHIFT (24U) /*! MEAS_MODE - Measurement Mode */ #define TMPSNS_CTRL1_SET_MEAS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_MEAS_MODE_SHIFT)) & TMPSNS_CTRL1_SET_MEAS_MODE_MASK) #define TMPSNS_CTRL1_SET_STOP_MASK (0x20000000U) #define TMPSNS_CTRL1_SET_STOP_SHIFT (29U) /*! STOP - Stop Measurement */ #define TMPSNS_CTRL1_SET_STOP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_STOP_SHIFT)) & TMPSNS_CTRL1_SET_STOP_MASK) #define TMPSNS_CTRL1_SET_START_MASK (0x40000000U) #define TMPSNS_CTRL1_SET_START_SHIFT (30U) /*! START - Start Measurement */ #define TMPSNS_CTRL1_SET_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK) #define TMPSNS_CTRL1_SET_ENABLE_MASK (0x80000000U) #define TMPSNS_CTRL1_SET_ENABLE_SHIFT (31U) /*! ENABLE - TEMPSENSE Enable */ #define TMPSNS_CTRL1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_ENABLE_SHIFT)) & TMPSNS_CTRL1_SET_ENABLE_MASK) /*! @} */ /*! @name CTRL1_CLR - Control 1 */ /*! @{ */ #define TMPSNS_CTRL1_CLR_THR4_MODE_MASK (0x3U) #define TMPSNS_CTRL1_CLR_THR4_MODE_SHIFT (0U) /*! THR4_MODE - Threshold4 Comparator Mode */ #define TMPSNS_CTRL1_CLR_THR4_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_THR4_MODE_SHIFT)) & TMPSNS_CTRL1_CLR_THR4_MODE_MASK) #define TMPSNS_CTRL1_CLR_THR5_MODE_MASK (0xCU) #define TMPSNS_CTRL1_CLR_THR5_MODE_SHIFT (2U) /*! THR5_MODE - Threshold5 Comparator Mode */ #define TMPSNS_CTRL1_CLR_THR5_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_THR5_MODE_SHIFT)) & TMPSNS_CTRL1_CLR_THR5_MODE_MASK) #define TMPSNS_CTRL1_CLR_THR4_IE_MASK (0x100U) #define TMPSNS_CTRL1_CLR_THR4_IE_SHIFT (8U) /*! THR4_IE - Threshold Comparator4 Interrupt Enable */ #define TMPSNS_CTRL1_CLR_THR4_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_THR4_IE_SHIFT)) & TMPSNS_CTRL1_CLR_THR4_IE_MASK) #define TMPSNS_CTRL1_CLR_THR5_IE_MASK (0x200U) #define TMPSNS_CTRL1_CLR_THR5_IE_SHIFT (9U) /*! THR5_IE - Threshold Comparator5 Interrupt Enable */ #define TMPSNS_CTRL1_CLR_THR5_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_THR5_IE_SHIFT)) & TMPSNS_CTRL1_CLR_THR5_IE_MASK) #define TMPSNS_CTRL1_CLR_N_FILT_1_MASK (0xF000U) #define TMPSNS_CTRL1_CLR_N_FILT_1_SHIFT (12U) /*! N_FILT_1 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL1_CLR_N_FILT_1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_N_FILT_1_SHIFT)) & TMPSNS_CTRL1_CLR_N_FILT_1_MASK) #define TMPSNS_CTRL1_CLR_DRDY1_IE_MASK (0x10000U) #define TMPSNS_CTRL1_CLR_DRDY1_IE_SHIFT (16U) /*! DRDY1_IE - Data-Ready Interrupt Enable */ #define TMPSNS_CTRL1_CLR_DRDY1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_DRDY1_IE_SHIFT)) & TMPSNS_CTRL1_CLR_DRDY1_IE_MASK) #define TMPSNS_CTRL1_CLR_RESOLUTION_MASK (0xC0000U) #define TMPSNS_CTRL1_CLR_RESOLUTION_SHIFT (18U) /*! RESOLUTION - Resolution Mode */ #define TMPSNS_CTRL1_CLR_RESOLUTION(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RESOLUTION_SHIFT)) & TMPSNS_CTRL1_CLR_RESOLUTION_MASK) #define TMPSNS_CTRL1_CLR_FILT4_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL1_CLR_FILT4_CNT_CLR_SHIFT (20U) /*! FILT4_CNT_CLR - Filter 4 Counter Clear */ #define TMPSNS_CTRL1_CLR_FILT4_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FILT4_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_CLR_FILT4_CNT_CLR_MASK) #define TMPSNS_CTRL1_CLR_FILT5_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL1_CLR_FILT5_CNT_CLR_SHIFT (21U) /*! FILT5_CNT_CLR - Filter 5 Counter Clear */ #define TMPSNS_CTRL1_CLR_FILT5_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FILT5_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_CLR_FILT5_CNT_CLR_MASK) #define TMPSNS_CTRL1_CLR_MEAS_MODE_MASK (0x3000000U) #define TMPSNS_CTRL1_CLR_MEAS_MODE_SHIFT (24U) /*! MEAS_MODE - Measurement Mode */ #define TMPSNS_CTRL1_CLR_MEAS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_MEAS_MODE_SHIFT)) & TMPSNS_CTRL1_CLR_MEAS_MODE_MASK) #define TMPSNS_CTRL1_CLR_STOP_MASK (0x20000000U) #define TMPSNS_CTRL1_CLR_STOP_SHIFT (29U) /*! STOP - Stop Measurement */ #define TMPSNS_CTRL1_CLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_STOP_SHIFT)) & TMPSNS_CTRL1_CLR_STOP_MASK) #define TMPSNS_CTRL1_CLR_START_MASK (0x40000000U) #define TMPSNS_CTRL1_CLR_START_SHIFT (30U) /*! START - Start Measurement */ #define TMPSNS_CTRL1_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK) #define TMPSNS_CTRL1_CLR_ENABLE_MASK (0x80000000U) #define TMPSNS_CTRL1_CLR_ENABLE_SHIFT (31U) /*! ENABLE - TEMPSENSE Enable */ #define TMPSNS_CTRL1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_ENABLE_SHIFT)) & TMPSNS_CTRL1_CLR_ENABLE_MASK) /*! @} */ /*! @name CTRL1_TOG - Control 1 */ /*! @{ */ #define TMPSNS_CTRL1_TOG_THR4_MODE_MASK (0x3U) #define TMPSNS_CTRL1_TOG_THR4_MODE_SHIFT (0U) /*! THR4_MODE - Threshold4 Comparator Mode */ #define TMPSNS_CTRL1_TOG_THR4_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_THR4_MODE_SHIFT)) & TMPSNS_CTRL1_TOG_THR4_MODE_MASK) #define TMPSNS_CTRL1_TOG_THR5_MODE_MASK (0xCU) #define TMPSNS_CTRL1_TOG_THR5_MODE_SHIFT (2U) /*! THR5_MODE - Threshold5 Comparator Mode */ #define TMPSNS_CTRL1_TOG_THR5_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_THR5_MODE_SHIFT)) & TMPSNS_CTRL1_TOG_THR5_MODE_MASK) #define TMPSNS_CTRL1_TOG_THR4_IE_MASK (0x100U) #define TMPSNS_CTRL1_TOG_THR4_IE_SHIFT (8U) /*! THR4_IE - Threshold Comparator4 Interrupt Enable */ #define TMPSNS_CTRL1_TOG_THR4_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_THR4_IE_SHIFT)) & TMPSNS_CTRL1_TOG_THR4_IE_MASK) #define TMPSNS_CTRL1_TOG_THR5_IE_MASK (0x200U) #define TMPSNS_CTRL1_TOG_THR5_IE_SHIFT (9U) /*! THR5_IE - Threshold Comparator5 Interrupt Enable */ #define TMPSNS_CTRL1_TOG_THR5_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_THR5_IE_SHIFT)) & TMPSNS_CTRL1_TOG_THR5_IE_MASK) #define TMPSNS_CTRL1_TOG_N_FILT_1_MASK (0xF000U) #define TMPSNS_CTRL1_TOG_N_FILT_1_SHIFT (12U) /*! N_FILT_1 - Filter Length for Threshold Flag */ #define TMPSNS_CTRL1_TOG_N_FILT_1(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_N_FILT_1_SHIFT)) & TMPSNS_CTRL1_TOG_N_FILT_1_MASK) #define TMPSNS_CTRL1_TOG_DRDY1_IE_MASK (0x10000U) #define TMPSNS_CTRL1_TOG_DRDY1_IE_SHIFT (16U) /*! DRDY1_IE - Data-Ready Interrupt Enable */ #define TMPSNS_CTRL1_TOG_DRDY1_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_DRDY1_IE_SHIFT)) & TMPSNS_CTRL1_TOG_DRDY1_IE_MASK) #define TMPSNS_CTRL1_TOG_RESOLUTION_MASK (0xC0000U) #define TMPSNS_CTRL1_TOG_RESOLUTION_SHIFT (18U) /*! RESOLUTION - Resolution Mode */ #define TMPSNS_CTRL1_TOG_RESOLUTION(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RESOLUTION_SHIFT)) & TMPSNS_CTRL1_TOG_RESOLUTION_MASK) #define TMPSNS_CTRL1_TOG_FILT4_CNT_CLR_MASK (0x100000U) #define TMPSNS_CTRL1_TOG_FILT4_CNT_CLR_SHIFT (20U) /*! FILT4_CNT_CLR - Filter 4 Counter Clear */ #define TMPSNS_CTRL1_TOG_FILT4_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FILT4_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_TOG_FILT4_CNT_CLR_MASK) #define TMPSNS_CTRL1_TOG_FILT5_CNT_CLR_MASK (0x200000U) #define TMPSNS_CTRL1_TOG_FILT5_CNT_CLR_SHIFT (21U) /*! FILT5_CNT_CLR - Filter 5 Counter Clear */ #define TMPSNS_CTRL1_TOG_FILT5_CNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FILT5_CNT_CLR_SHIFT)) & TMPSNS_CTRL1_TOG_FILT5_CNT_CLR_MASK) #define TMPSNS_CTRL1_TOG_MEAS_MODE_MASK (0x3000000U) #define TMPSNS_CTRL1_TOG_MEAS_MODE_SHIFT (24U) /*! MEAS_MODE - Measurement Mode */ #define TMPSNS_CTRL1_TOG_MEAS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_MEAS_MODE_SHIFT)) & TMPSNS_CTRL1_TOG_MEAS_MODE_MASK) #define TMPSNS_CTRL1_TOG_STOP_MASK (0x20000000U) #define TMPSNS_CTRL1_TOG_STOP_SHIFT (29U) /*! STOP - Stop Measurement */ #define TMPSNS_CTRL1_TOG_STOP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_STOP_SHIFT)) & TMPSNS_CTRL1_TOG_STOP_MASK) #define TMPSNS_CTRL1_TOG_START_MASK (0x40000000U) #define TMPSNS_CTRL1_TOG_START_SHIFT (30U) /*! START - Start Measurement */ #define TMPSNS_CTRL1_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK) #define TMPSNS_CTRL1_TOG_ENABLE_MASK (0x80000000U) #define TMPSNS_CTRL1_TOG_ENABLE_SHIFT (31U) /*! ENABLE - TEMPSENSE Enable */ #define TMPSNS_CTRL1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_ENABLE_SHIFT)) & TMPSNS_CTRL1_TOG_ENABLE_MASK) /*! @} */ /*! @name STAT1 - Status 1 */ /*! @{ */ #define TMPSNS_STAT1_THR4_IF_MASK (0x100U) #define TMPSNS_STAT1_THR4_IF_SHIFT (8U) /*! THR4_IF - Threshold4 Status Flag * 0b0..Event did not occur * 0b1..Event occurred * 0b0..No effect * 0b1..Clear the flag */ #define TMPSNS_STAT1_THR4_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_THR4_IF_SHIFT)) & TMPSNS_STAT1_THR4_IF_MASK) #define TMPSNS_STAT1_THR5_IF_MASK (0x200U) #define TMPSNS_STAT1_THR5_IF_SHIFT (9U) /*! THR5_IF - Threshold5 Status Flag * 0b0..Event did not occur * 0b1..Event occurred * 0b0..No effect * 0b1..Clear the flag */ #define TMPSNS_STAT1_THR5_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_THR5_IF_SHIFT)) & TMPSNS_STAT1_THR5_IF_MASK) #define TMPSNS_STAT1_THR4_STAT_MASK (0x1000U) #define TMPSNS_STAT1_THR4_STAT_SHIFT (12U) /*! THR4_STAT - Threshold4 State */ #define TMPSNS_STAT1_THR4_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_THR4_STAT_SHIFT)) & TMPSNS_STAT1_THR4_STAT_MASK) #define TMPSNS_STAT1_THR5_STAT_MASK (0x2000U) #define TMPSNS_STAT1_THR5_STAT_SHIFT (13U) /*! THR5_STAT - Threshold5 State */ #define TMPSNS_STAT1_THR5_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_THR5_STAT_SHIFT)) & TMPSNS_STAT1_THR5_STAT_MASK) #define TMPSNS_STAT1_DRDY1_IF_MASK (0x10000U) #define TMPSNS_STAT1_DRDY1_IF_SHIFT (16U) /*! DRDY1_IF - Data Ready Flag * 0b0..No new data * 0b1..New data */ #define TMPSNS_STAT1_DRDY1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_DRDY1_IF_SHIFT)) & TMPSNS_STAT1_DRDY1_IF_MASK) #define TMPSNS_STAT1_IDLE_MASK (0x80000000U) #define TMPSNS_STAT1_IDLE_SHIFT (31U) /*! IDLE - Idle State * 0b0..Conversion * 0b1..Idle */ #define TMPSNS_STAT1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_IDLE_SHIFT)) & TMPSNS_STAT1_IDLE_MASK) /*! @} */ /*! @name STAT1_SET - Status 1 */ /*! @{ */ #define TMPSNS_STAT1_SET_THR4_IF_MASK (0x100U) #define TMPSNS_STAT1_SET_THR4_IF_SHIFT (8U) /*! THR4_IF - Threshold4 Status Flag */ #define TMPSNS_STAT1_SET_THR4_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_SET_THR4_IF_SHIFT)) & TMPSNS_STAT1_SET_THR4_IF_MASK) #define TMPSNS_STAT1_SET_THR5_IF_MASK (0x200U) #define TMPSNS_STAT1_SET_THR5_IF_SHIFT (9U) /*! THR5_IF - Threshold5 Status Flag */ #define TMPSNS_STAT1_SET_THR5_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_SET_THR5_IF_SHIFT)) & TMPSNS_STAT1_SET_THR5_IF_MASK) #define TMPSNS_STAT1_SET_THR4_STAT_MASK (0x1000U) #define TMPSNS_STAT1_SET_THR4_STAT_SHIFT (12U) /*! THR4_STAT - Threshold4 State */ #define TMPSNS_STAT1_SET_THR4_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_SET_THR4_STAT_SHIFT)) & TMPSNS_STAT1_SET_THR4_STAT_MASK) #define TMPSNS_STAT1_SET_THR5_STAT_MASK (0x2000U) #define TMPSNS_STAT1_SET_THR5_STAT_SHIFT (13U) /*! THR5_STAT - Threshold5 State */ #define TMPSNS_STAT1_SET_THR5_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_SET_THR5_STAT_SHIFT)) & TMPSNS_STAT1_SET_THR5_STAT_MASK) #define TMPSNS_STAT1_SET_DRDY1_IF_MASK (0x10000U) #define TMPSNS_STAT1_SET_DRDY1_IF_SHIFT (16U) /*! DRDY1_IF - Data Ready Flag */ #define TMPSNS_STAT1_SET_DRDY1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_SET_DRDY1_IF_SHIFT)) & TMPSNS_STAT1_SET_DRDY1_IF_MASK) #define TMPSNS_STAT1_SET_IDLE_MASK (0x80000000U) #define TMPSNS_STAT1_SET_IDLE_SHIFT (31U) /*! IDLE - Idle State */ #define TMPSNS_STAT1_SET_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_SET_IDLE_SHIFT)) & TMPSNS_STAT1_SET_IDLE_MASK) /*! @} */ /*! @name STAT1_CLR - Status 1 */ /*! @{ */ #define TMPSNS_STAT1_CLR_THR4_IF_MASK (0x100U) #define TMPSNS_STAT1_CLR_THR4_IF_SHIFT (8U) /*! THR4_IF - Threshold4 Status Flag */ #define TMPSNS_STAT1_CLR_THR4_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_CLR_THR4_IF_SHIFT)) & TMPSNS_STAT1_CLR_THR4_IF_MASK) #define TMPSNS_STAT1_CLR_THR5_IF_MASK (0x200U) #define TMPSNS_STAT1_CLR_THR5_IF_SHIFT (9U) /*! THR5_IF - Threshold5 Status Flag */ #define TMPSNS_STAT1_CLR_THR5_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_CLR_THR5_IF_SHIFT)) & TMPSNS_STAT1_CLR_THR5_IF_MASK) #define TMPSNS_STAT1_CLR_THR4_STAT_MASK (0x1000U) #define TMPSNS_STAT1_CLR_THR4_STAT_SHIFT (12U) /*! THR4_STAT - Threshold4 State */ #define TMPSNS_STAT1_CLR_THR4_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_CLR_THR4_STAT_SHIFT)) & TMPSNS_STAT1_CLR_THR4_STAT_MASK) #define TMPSNS_STAT1_CLR_THR5_STAT_MASK (0x2000U) #define TMPSNS_STAT1_CLR_THR5_STAT_SHIFT (13U) /*! THR5_STAT - Threshold5 State */ #define TMPSNS_STAT1_CLR_THR5_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_CLR_THR5_STAT_SHIFT)) & TMPSNS_STAT1_CLR_THR5_STAT_MASK) #define TMPSNS_STAT1_CLR_DRDY1_IF_MASK (0x10000U) #define TMPSNS_STAT1_CLR_DRDY1_IF_SHIFT (16U) /*! DRDY1_IF - Data Ready Flag */ #define TMPSNS_STAT1_CLR_DRDY1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_CLR_DRDY1_IF_SHIFT)) & TMPSNS_STAT1_CLR_DRDY1_IF_MASK) #define TMPSNS_STAT1_CLR_IDLE_MASK (0x80000000U) #define TMPSNS_STAT1_CLR_IDLE_SHIFT (31U) /*! IDLE - Idle State */ #define TMPSNS_STAT1_CLR_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_CLR_IDLE_SHIFT)) & TMPSNS_STAT1_CLR_IDLE_MASK) /*! @} */ /*! @name STAT1_TOG - Status 1 */ /*! @{ */ #define TMPSNS_STAT1_TOG_THR4_IF_MASK (0x100U) #define TMPSNS_STAT1_TOG_THR4_IF_SHIFT (8U) /*! THR4_IF - Threshold4 Status Flag */ #define TMPSNS_STAT1_TOG_THR4_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_TOG_THR4_IF_SHIFT)) & TMPSNS_STAT1_TOG_THR4_IF_MASK) #define TMPSNS_STAT1_TOG_THR5_IF_MASK (0x200U) #define TMPSNS_STAT1_TOG_THR5_IF_SHIFT (9U) /*! THR5_IF - Threshold5 Status Flag */ #define TMPSNS_STAT1_TOG_THR5_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_TOG_THR5_IF_SHIFT)) & TMPSNS_STAT1_TOG_THR5_IF_MASK) #define TMPSNS_STAT1_TOG_THR4_STAT_MASK (0x1000U) #define TMPSNS_STAT1_TOG_THR4_STAT_SHIFT (12U) /*! THR4_STAT - Threshold4 State */ #define TMPSNS_STAT1_TOG_THR4_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_TOG_THR4_STAT_SHIFT)) & TMPSNS_STAT1_TOG_THR4_STAT_MASK) #define TMPSNS_STAT1_TOG_THR5_STAT_MASK (0x2000U) #define TMPSNS_STAT1_TOG_THR5_STAT_SHIFT (13U) /*! THR5_STAT - Threshold5 State */ #define TMPSNS_STAT1_TOG_THR5_STAT(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_TOG_THR5_STAT_SHIFT)) & TMPSNS_STAT1_TOG_THR5_STAT_MASK) #define TMPSNS_STAT1_TOG_DRDY1_IF_MASK (0x10000U) #define TMPSNS_STAT1_TOG_DRDY1_IF_SHIFT (16U) /*! DRDY1_IF - Data Ready Flag */ #define TMPSNS_STAT1_TOG_DRDY1_IF(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_TOG_DRDY1_IF_SHIFT)) & TMPSNS_STAT1_TOG_DRDY1_IF_MASK) #define TMPSNS_STAT1_TOG_IDLE_MASK (0x80000000U) #define TMPSNS_STAT1_TOG_IDLE_SHIFT (31U) /*! IDLE - Idle State */ #define TMPSNS_STAT1_TOG_IDLE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STAT1_TOG_IDLE_SHIFT)) & TMPSNS_STAT1_TOG_IDLE_MASK) /*! @} */ /*! @name DATA1 - Data 1 */ /*! @{ */ #define TMPSNS_DATA1_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA1_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA1_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA1_DATA_VAL_SHIFT)) & TMPSNS_DATA1_DATA_VAL_MASK) /*! @} */ /*! @name DATA1_SET - Data 1 */ /*! @{ */ #define TMPSNS_DATA1_SET_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA1_SET_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA1_SET_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA1_SET_DATA_VAL_SHIFT)) & TMPSNS_DATA1_SET_DATA_VAL_MASK) /*! @} */ /*! @name DATA1_CLR - Data 1 */ /*! @{ */ #define TMPSNS_DATA1_CLR_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA1_CLR_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA1_CLR_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA1_CLR_DATA_VAL_SHIFT)) & TMPSNS_DATA1_CLR_DATA_VAL_MASK) /*! @} */ /*! @name DATA1_TOG - Data 1 */ /*! @{ */ #define TMPSNS_DATA1_TOG_DATA_VAL_MASK (0xFFFFU) #define TMPSNS_DATA1_TOG_DATA_VAL_SHIFT (0U) /*! DATA_VAL - Temperature Data Value */ #define TMPSNS_DATA1_TOG_DATA_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_DATA1_TOG_DATA_VAL_SHIFT)) & TMPSNS_DATA1_TOG_DATA_VAL_MASK) /*! @} */ /*! @name THR_CTRL45 - Threshold Control 45 */ /*! @{ */ #define TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD4_MASK (0xFFFFU) #define TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD4_SHIFT (0U) /*! TEMPERATURE_THRESHOLD4 - Temperature Threshold4 */ #define TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD4(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD4_SHIFT)) & TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD4_MASK) #define TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD5_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD5_SHIFT (16U) /*! TEMPERATURE_THRESHOLD5 - Temperature Threshold5 */ #define TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD5(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD5_SHIFT)) & TMPSNS_THR_CTRL45_TEMPERATURE_THRESHOLD5_MASK) /*! @} */ /*! @name THR_CTRL45_SET - Threshold Control 45 */ /*! @{ */ #define TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD4_MASK (0xFFFFU) #define TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD4_SHIFT (0U) /*! TEMPERATURE_THRESHOLD4 - Temperature Threshold4 */ #define TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD4(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD4_SHIFT)) & TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD4_MASK) #define TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD5_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD5_SHIFT (16U) /*! TEMPERATURE_THRESHOLD5 - Temperature Threshold5 */ #define TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD5(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD5_SHIFT)) & TMPSNS_THR_CTRL45_SET_TEMPERATURE_THRESHOLD5_MASK) /*! @} */ /*! @name THR_CTRL45_CLR - Threshold Control 45 */ /*! @{ */ #define TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD4_MASK (0xFFFFU) #define TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD4_SHIFT (0U) /*! TEMPERATURE_THRESHOLD4 - Temperature Threshold4 */ #define TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD4(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD4_SHIFT)) & TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD4_MASK) #define TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD5_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD5_SHIFT (16U) /*! TEMPERATURE_THRESHOLD5 - Temperature Threshold5 */ #define TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD5(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD5_SHIFT)) & TMPSNS_THR_CTRL45_CLR_TEMPERATURE_THRESHOLD5_MASK) /*! @} */ /*! @name THR_CTRL45_TOG - Threshold Control 45 */ /*! @{ */ #define TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD4_MASK (0xFFFFU) #define TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD4_SHIFT (0U) /*! TEMPERATURE_THRESHOLD4 - Temperature Threshold4 */ #define TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD4(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD4_SHIFT)) & TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD4_MASK) #define TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD5_MASK (0xFFFF0000U) #define TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD5_SHIFT (16U) /*! TEMPERATURE_THRESHOLD5 - Temperature Threshold5 */ #define TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD5(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD5_SHIFT)) & TMPSNS_THR_CTRL45_TOG_TEMPERATURE_THRESHOLD5_MASK) /*! @} */ /*! @name PERIOD_CTRL - Measurement Period Control */ /*! @{ */ #define TMPSNS_PERIOD_CTRL_MEAS_FREQ_MASK (0xFFFFFFU) #define TMPSNS_PERIOD_CTRL_MEAS_FREQ_SHIFT (0U) /*! MEAS_FREQ - TEMPSENSE Periodic Measurement Frequency */ #define TMPSNS_PERIOD_CTRL_MEAS_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PERIOD_CTRL_MEAS_FREQ_SHIFT)) & TMPSNS_PERIOD_CTRL_MEAS_FREQ_MASK) /*! @} */ /*! @name PERIOD_CTRL_SET - Measurement Period Control */ /*! @{ */ #define TMPSNS_PERIOD_CTRL_SET_MEAS_FREQ_MASK (0xFFFFFFU) #define TMPSNS_PERIOD_CTRL_SET_MEAS_FREQ_SHIFT (0U) /*! MEAS_FREQ - TEMPSENSE Periodic Measurement Frequency */ #define TMPSNS_PERIOD_CTRL_SET_MEAS_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PERIOD_CTRL_SET_MEAS_FREQ_SHIFT)) & TMPSNS_PERIOD_CTRL_SET_MEAS_FREQ_MASK) /*! @} */ /*! @name PERIOD_CTRL_CLR - Measurement Period Control */ /*! @{ */ #define TMPSNS_PERIOD_CTRL_CLR_MEAS_FREQ_MASK (0xFFFFFFU) #define TMPSNS_PERIOD_CTRL_CLR_MEAS_FREQ_SHIFT (0U) /*! MEAS_FREQ - TEMPSENSE Periodic Measurement Frequency */ #define TMPSNS_PERIOD_CTRL_CLR_MEAS_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PERIOD_CTRL_CLR_MEAS_FREQ_SHIFT)) & TMPSNS_PERIOD_CTRL_CLR_MEAS_FREQ_MASK) /*! @} */ /*! @name PERIOD_CTRL_TOG - Measurement Period Control */ /*! @{ */ #define TMPSNS_PERIOD_CTRL_TOG_MEAS_FREQ_MASK (0xFFFFFFU) #define TMPSNS_PERIOD_CTRL_TOG_MEAS_FREQ_SHIFT (0U) /*! MEAS_FREQ - TEMPSENSE Periodic Measurement Frequency */ #define TMPSNS_PERIOD_CTRL_TOG_MEAS_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PERIOD_CTRL_TOG_MEAS_FREQ_SHIFT)) & TMPSNS_PERIOD_CTRL_TOG_MEAS_FREQ_MASK) /*! @} */ /*! @name REF_DIV - Reference Clock Divider Control */ /*! @{ */ #define TMPSNS_REF_DIV_DIV_MASK (0xFF0000U) #define TMPSNS_REF_DIV_DIV_SHIFT (16U) /*! DIV - Divider Value * 0b00000000..Output clock frequency = input clock frequency * 0b00000001..Output clock frequency = input clock frequency / 2 * 0b00000010..Output clock frequency = input clock frequency / 3 * 0b00000011..... * 0b11111111..Output clock frequency = input clock frequency / 256 */ #define TMPSNS_REF_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_REF_DIV_DIV_SHIFT)) & TMPSNS_REF_DIV_DIV_MASK) #define TMPSNS_REF_DIV_DE_MASK (0x80000000U) #define TMPSNS_REF_DIV_DE_SHIFT (31U) /*! DE - Divider Enable * 0b0..Disable * 0b1..Enable */ #define TMPSNS_REF_DIV_DE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_REF_DIV_DE_SHIFT)) & TMPSNS_REF_DIV_DE_MASK) /*! @} */ /*! @name PUD_ST_CTRL - Power-Up Delay and Self-Test Control */ /*! @{ */ #define TMPSNS_PUD_ST_CTRL_PUD_MASK (0xFF0000U) #define TMPSNS_PUD_ST_CTRL_PUD_SHIFT (16U) /*! PUD - Power-Up Delay */ #define TMPSNS_PUD_ST_CTRL_PUD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PUD_ST_CTRL_PUD_SHIFT)) & TMPSNS_PUD_ST_CTRL_PUD_MASK) /*! @} */ /*! @name PUD_ST_CTRL_SET - Power-Up Delay and Self-Test Control */ /*! @{ */ #define TMPSNS_PUD_ST_CTRL_SET_PUD_MASK (0xFF0000U) #define TMPSNS_PUD_ST_CTRL_SET_PUD_SHIFT (16U) /*! PUD - Power-Up Delay */ #define TMPSNS_PUD_ST_CTRL_SET_PUD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PUD_ST_CTRL_SET_PUD_SHIFT)) & TMPSNS_PUD_ST_CTRL_SET_PUD_MASK) /*! @} */ /*! @name PUD_ST_CTRL_CLR - Power-Up Delay and Self-Test Control */ /*! @{ */ #define TMPSNS_PUD_ST_CTRL_CLR_PUD_MASK (0xFF0000U) #define TMPSNS_PUD_ST_CTRL_CLR_PUD_SHIFT (16U) /*! PUD - Power-Up Delay */ #define TMPSNS_PUD_ST_CTRL_CLR_PUD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PUD_ST_CTRL_CLR_PUD_SHIFT)) & TMPSNS_PUD_ST_CTRL_CLR_PUD_MASK) /*! @} */ /*! @name PUD_ST_CTRL_TOG - Power-Up Delay and Self-Test Control */ /*! @{ */ #define TMPSNS_PUD_ST_CTRL_TOG_PUD_MASK (0xFF0000U) #define TMPSNS_PUD_ST_CTRL_TOG_PUD_SHIFT (16U) /*! PUD - Power-Up Delay */ #define TMPSNS_PUD_ST_CTRL_TOG_PUD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_PUD_ST_CTRL_TOG_PUD_SHIFT)) & TMPSNS_PUD_ST_CTRL_TOG_PUD_MASK) /*! @} */ /*! @name TRIM1 - Trim Control 1 */ /*! @{ */ #define TMPSNS_TRIM1_VAL_A_MASK (0xFFFFU) #define TMPSNS_TRIM1_VAL_A_SHIFT (0U) /*! VAL_A - VAL_A */ #define TMPSNS_TRIM1_VAL_A(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_VAL_A_SHIFT)) & TMPSNS_TRIM1_VAL_A_MASK) #define TMPSNS_TRIM1_VAL_B_MASK (0xFFFF0000U) #define TMPSNS_TRIM1_VAL_B_SHIFT (16U) /*! VAL_B - VAL_B */ #define TMPSNS_TRIM1_VAL_B(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_VAL_B_SHIFT)) & TMPSNS_TRIM1_VAL_B_MASK) /*! @} */ /*! @name TRIM1_SET - Trim Control 1 */ /*! @{ */ #define TMPSNS_TRIM1_SET_VAL_A_MASK (0xFFFFU) #define TMPSNS_TRIM1_SET_VAL_A_SHIFT (0U) /*! VAL_A - VAL_A */ #define TMPSNS_TRIM1_SET_VAL_A(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_SET_VAL_A_SHIFT)) & TMPSNS_TRIM1_SET_VAL_A_MASK) #define TMPSNS_TRIM1_SET_VAL_B_MASK (0xFFFF0000U) #define TMPSNS_TRIM1_SET_VAL_B_SHIFT (16U) /*! VAL_B - VAL_B */ #define TMPSNS_TRIM1_SET_VAL_B(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_SET_VAL_B_SHIFT)) & TMPSNS_TRIM1_SET_VAL_B_MASK) /*! @} */ /*! @name TRIM1_CLR - Trim Control 1 */ /*! @{ */ #define TMPSNS_TRIM1_CLR_VAL_A_MASK (0xFFFFU) #define TMPSNS_TRIM1_CLR_VAL_A_SHIFT (0U) /*! VAL_A - VAL_A */ #define TMPSNS_TRIM1_CLR_VAL_A(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_CLR_VAL_A_SHIFT)) & TMPSNS_TRIM1_CLR_VAL_A_MASK) #define TMPSNS_TRIM1_CLR_VAL_B_MASK (0xFFFF0000U) #define TMPSNS_TRIM1_CLR_VAL_B_SHIFT (16U) /*! VAL_B - VAL_B */ #define TMPSNS_TRIM1_CLR_VAL_B(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_CLR_VAL_B_SHIFT)) & TMPSNS_TRIM1_CLR_VAL_B_MASK) /*! @} */ /*! @name TRIM1_TOG - Trim Control 1 */ /*! @{ */ #define TMPSNS_TRIM1_TOG_VAL_A_MASK (0xFFFFU) #define TMPSNS_TRIM1_TOG_VAL_A_SHIFT (0U) /*! VAL_A - VAL_A */ #define TMPSNS_TRIM1_TOG_VAL_A(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_TOG_VAL_A_SHIFT)) & TMPSNS_TRIM1_TOG_VAL_A_MASK) #define TMPSNS_TRIM1_TOG_VAL_B_MASK (0xFFFF0000U) #define TMPSNS_TRIM1_TOG_VAL_B_SHIFT (16U) /*! VAL_B - VAL_B */ #define TMPSNS_TRIM1_TOG_VAL_B(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM1_TOG_VAL_B_SHIFT)) & TMPSNS_TRIM1_TOG_VAL_B_MASK) /*! @} */ /*! @name TRIM2 - Trim Control 2 */ /*! @{ */ #define TMPSNS_TRIM2_VAL_ALPHA_MASK (0xFFFFU) #define TMPSNS_TRIM2_VAL_ALPHA_SHIFT (0U) /*! VAL_ALPHA - VAL_ALPHA */ #define TMPSNS_TRIM2_VAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_VAL_ALPHA_SHIFT)) & TMPSNS_TRIM2_VAL_ALPHA_MASK) #define TMPSNS_TRIM2_VAL_OFFSET_MASK (0xFFFF0000U) #define TMPSNS_TRIM2_VAL_OFFSET_SHIFT (16U) /*! VAL_OFFSET - VAL_OFFSET */ #define TMPSNS_TRIM2_VAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_VAL_OFFSET_SHIFT)) & TMPSNS_TRIM2_VAL_OFFSET_MASK) /*! @} */ /*! @name TRIM2_SET - Trim Control 2 */ /*! @{ */ #define TMPSNS_TRIM2_SET_VAL_ALPHA_MASK (0xFFFFU) #define TMPSNS_TRIM2_SET_VAL_ALPHA_SHIFT (0U) /*! VAL_ALPHA - VAL_ALPHA */ #define TMPSNS_TRIM2_SET_VAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_SET_VAL_ALPHA_SHIFT)) & TMPSNS_TRIM2_SET_VAL_ALPHA_MASK) #define TMPSNS_TRIM2_SET_VAL_OFFSET_MASK (0xFFFF0000U) #define TMPSNS_TRIM2_SET_VAL_OFFSET_SHIFT (16U) /*! VAL_OFFSET - VAL_OFFSET */ #define TMPSNS_TRIM2_SET_VAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_SET_VAL_OFFSET_SHIFT)) & TMPSNS_TRIM2_SET_VAL_OFFSET_MASK) /*! @} */ /*! @name TRIM2_CLR - Trim Control 2 */ /*! @{ */ #define TMPSNS_TRIM2_CLR_VAL_ALPHA_MASK (0xFFFFU) #define TMPSNS_TRIM2_CLR_VAL_ALPHA_SHIFT (0U) /*! VAL_ALPHA - VAL_ALPHA */ #define TMPSNS_TRIM2_CLR_VAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_CLR_VAL_ALPHA_SHIFT)) & TMPSNS_TRIM2_CLR_VAL_ALPHA_MASK) #define TMPSNS_TRIM2_CLR_VAL_OFFSET_MASK (0xFFFF0000U) #define TMPSNS_TRIM2_CLR_VAL_OFFSET_SHIFT (16U) /*! VAL_OFFSET - VAL_OFFSET */ #define TMPSNS_TRIM2_CLR_VAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_CLR_VAL_OFFSET_SHIFT)) & TMPSNS_TRIM2_CLR_VAL_OFFSET_MASK) /*! @} */ /*! @name TRIM2_TOG - Trim Control 2 */ /*! @{ */ #define TMPSNS_TRIM2_TOG_VAL_ALPHA_MASK (0xFFFFU) #define TMPSNS_TRIM2_TOG_VAL_ALPHA_SHIFT (0U) /*! VAL_ALPHA - VAL_ALPHA */ #define TMPSNS_TRIM2_TOG_VAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_TOG_VAL_ALPHA_SHIFT)) & TMPSNS_TRIM2_TOG_VAL_ALPHA_MASK) #define TMPSNS_TRIM2_TOG_VAL_OFFSET_MASK (0xFFFF0000U) #define TMPSNS_TRIM2_TOG_VAL_OFFSET_SHIFT (16U) /*! VAL_OFFSET - VAL_OFFSET */ #define TMPSNS_TRIM2_TOG_VAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_TRIM2_TOG_VAL_OFFSET_SHIFT)) & TMPSNS_TRIM2_TOG_VAL_OFFSET_MASK) /*! @} */ /*! * @} */ /* end of group TMPSNS_Register_Masks */ /* TMPSNS - Peripheral instance base addresses */ /** Peripheral TMPSNS1 base address */ #define TMPSNS1_BASE (0x44482000u) /** Peripheral TMPSNS1 base pointer */ #define TMPSNS1 ((TMPSNS_Type *)TMPSNS1_BASE) /** Peripheral TMPSNS2 base address */ #define TMPSNS2_BASE (0x4A440000u) /** Peripheral TMPSNS2 base pointer */ #define TMPSNS2 ((TMPSNS_Type *)TMPSNS2_BASE) /** Array initializer of TMPSNS peripheral base addresses */ #define TMPSNS_BASE_ADDRS { TMPSNS1_BASE, TMPSNS2_BASE } /** Array initializer of TMPSNS peripheral base pointers */ #define TMPSNS_BASE_PTRS { TMPSNS1, TMPSNS2 } /*! * @} */ /* end of group TMPSNS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer * @{ */ /** TPM - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ __IO uint32_t GLOBAL; /**< TPM Global, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t SC; /**< Status and Control, offset: 0x10 */ __IO uint32_t CNT; /**< Counter, offset: 0x14 */ __IO uint32_t MOD; /**< Modulo, offset: 0x18 */ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x1C */ struct { /* offset: 0x20, array step: 0x8 */ __IO uint32_t CnSC; /**< Channel n Status and Control, array offset: 0x20, array step: 0x8 */ __IO uint32_t CnV; /**< Channel n Value, array offset: 0x24, array step: 0x8 */ } CONTROLS[4]; uint8_t RESERVED_1[36]; __IO uint32_t COMBINE; /**< Combine Channel, offset: 0x64 */ uint8_t RESERVED_2[4]; __IO uint32_t TRIG; /**< Channel Trigger, offset: 0x6C */ __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ uint8_t RESERVED_3[4]; __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ uint8_t RESERVED_4[4]; __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ } TPM_Type; /* ---------------------------------------------------------------------------- -- TPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Register_Masks TPM Register Masks * @{ */ /*! @name VERID - Version ID */ /*! @{ */ #define TPM_VERID_FEATURE_MASK (0xFFFFU) #define TPM_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number * 0b0000000000000001..Standard feature set * 0b0000000000000011..Standard feature set with the filter and combine registers implemented * 0b0000000000000101..Standard feature set with the quadrature register implemented * 0b0000000000000111..Standard feature set with the filter, combine, and quadrature registers implemented */ #define TPM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_FEATURE_SHIFT)) & TPM_VERID_FEATURE_MASK) #define TPM_VERID_MINOR_MASK (0xFF0000U) #define TPM_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define TPM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MINOR_SHIFT)) & TPM_VERID_MINOR_MASK) #define TPM_VERID_MAJOR_MASK (0xFF000000U) #define TPM_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number */ #define TPM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << TPM_VERID_MAJOR_SHIFT)) & TPM_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter */ /*! @{ */ #define TPM_PARAM_CHAN_MASK (0xFFU) #define TPM_PARAM_CHAN_SHIFT (0U) /*! CHAN - Channel Count */ #define TPM_PARAM_CHAN(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_CHAN_SHIFT)) & TPM_PARAM_CHAN_MASK) #define TPM_PARAM_TRIG_MASK (0xFF00U) #define TPM_PARAM_TRIG_SHIFT (8U) /*! TRIG - Trigger Count */ #define TPM_PARAM_TRIG(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_TRIG_SHIFT)) & TPM_PARAM_TRIG_MASK) #define TPM_PARAM_WIDTH_MASK (0xFF0000U) #define TPM_PARAM_WIDTH_SHIFT (16U) /*! WIDTH - Counter Width */ #define TPM_PARAM_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << TPM_PARAM_WIDTH_SHIFT)) & TPM_PARAM_WIDTH_MASK) /*! @} */ /*! @name GLOBAL - TPM Global */ /*! @{ */ #define TPM_GLOBAL_NOUPDATE_MASK (0x1U) #define TPM_GLOBAL_NOUPDATE_SHIFT (0U) /*! NOUPDATE - No Update * 0b0..Internal double-buffered registers update as normal * 0b1..Internal double-buffered registers do not update */ #define TPM_GLOBAL_NOUPDATE(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_NOUPDATE_SHIFT)) & TPM_GLOBAL_NOUPDATE_MASK) #define TPM_GLOBAL_RST_MASK (0x2U) #define TPM_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset * 0b0..Module is not reset * 0b1..Module is reset */ #define TPM_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << TPM_GLOBAL_RST_SHIFT)) & TPM_GLOBAL_RST_MASK) /*! @} */ /*! @name SC - Status and Control */ /*! @{ */ #define TPM_SC_PS_MASK (0x7U) #define TPM_SC_PS_SHIFT (0U) /*! PS - Prescale Factor Selection * 0b000..Divide by 1 * 0b001..Divide by 2 * 0b010..Divide by 4 * 0b011..Divide by 8 * 0b100..Divide by 16 * 0b101..Divide by 32 * 0b110..Divide by 64 * 0b111..Divide by 128 */ #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) #define TPM_SC_CMOD_MASK (0x18U) #define TPM_SC_CMOD_SHIFT (3U) /*! CMOD - Clock Mode Selection * 0b00..TPM counter is disabled * 0b01..TPM counter increments on every TPM counter clock * 0b10..TPM counter increments on the rising edge of EXTCLK synchronized to the TPM counter clock * 0b11..TPM counter increments on the rising edge of the selected external input trigger */ #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) #define TPM_SC_CPWMS_MASK (0x20U) #define TPM_SC_CPWMS_SHIFT (5U) /*! CPWMS - Center-Aligned PWM Select * 0b0..Up counting mode * 0b1..Up-down counting mode */ #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) #define TPM_SC_TOIE_MASK (0x40U) #define TPM_SC_TOIE_SHIFT (6U) /*! TOIE - Timer Overflow Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) #define TPM_SC_TOF_MASK (0x80U) #define TPM_SC_TOF_SHIFT (7U) /*! TOF - Timer Overflow Flag * 0b0..No overflow * 0b1..Overflow */ #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) #define TPM_SC_DMA_MASK (0x100U) #define TPM_SC_DMA_SHIFT (8U) /*! DMA - DMA Enable * 0b0..Disable * 0b1..Enable */ #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) /*! @} */ /*! @name CNT - Counter */ /*! @{ */ #define TPM_CNT_COUNT_MASK (0xFFFFFFFFU) #define TPM_CNT_COUNT_SHIFT (0U) /*! COUNT - Counter Value */ #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) /*! @} */ /*! @name MOD - Modulo */ /*! @{ */ #define TPM_MOD_MOD_MASK (0xFFFFFFFFU) #define TPM_MOD_MOD_SHIFT (0U) /*! MOD - Modulo Value */ #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) /*! @} */ /*! @name STATUS - Capture and Compare Status */ /*! @{ */ #define TPM_STATUS_CH0F_MASK (0x1U) #define TPM_STATUS_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Flag * 0b0..Event not occurred * 0b1..Event occurred */ #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) #define TPM_STATUS_CH1F_MASK (0x2U) #define TPM_STATUS_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Flag * 0b0..Event not occurred * 0b1..Event occurred */ #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) #define TPM_STATUS_CH2F_MASK (0x4U) #define TPM_STATUS_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Flag * 0b0..Event not occurred * 0b1..Event occurred */ #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) #define TPM_STATUS_CH3F_MASK (0x8U) #define TPM_STATUS_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Flag * 0b0..Event not occurred * 0b1..Event occurred */ #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) #define TPM_STATUS_TOF_MASK (0x100U) #define TPM_STATUS_TOF_SHIFT (8U) /*! TOF - Timer Overflow Flag * 0b0..No overflow * 0b1..Overflow */ #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) /*! @} */ /*! @name CnSC - Channel n Status and Control */ /*! @{ */ #define TPM_CnSC_DMA_MASK (0x1U) #define TPM_CnSC_DMA_SHIFT (0U) /*! DMA - DMA Enable * 0b0..Disable * 0b1..Enable */ #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) #define TPM_CnSC_ELSA_MASK (0x4U) #define TPM_CnSC_ELSA_SHIFT (2U) /*! ELSA - Edge or Level Select A */ #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) #define TPM_CnSC_ELSB_MASK (0x8U) #define TPM_CnSC_ELSB_SHIFT (3U) /*! ELSB - Edge or Level Select B */ #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) #define TPM_CnSC_MSA_MASK (0x10U) #define TPM_CnSC_MSA_SHIFT (4U) /*! MSA - Channel Mode Select A */ #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) #define TPM_CnSC_MSB_MASK (0x20U) #define TPM_CnSC_MSB_SHIFT (5U) /*! MSB - Channel Mode Select B */ #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) #define TPM_CnSC_CHIE_MASK (0x40U) #define TPM_CnSC_CHIE_SHIFT (6U) /*! CHIE - Channel Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) #define TPM_CnSC_CHF_MASK (0x80U) #define TPM_CnSC_CHF_SHIFT (7U) /*! CHF - Channel Flag * 0b0..Event not occurred * 0b1..Event occurred */ #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) /*! @} */ /* The count of TPM_CnSC */ #define TPM_CnSC_COUNT (4U) /*! @name CnV - Channel n Value */ /*! @{ */ #define TPM_CnV_VAL_MASK (0xFFFFFFFFU) #define TPM_CnV_VAL_SHIFT (0U) /*! VAL - Channel Value */ #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) /*! @} */ /* The count of TPM_CnV */ #define TPM_CnV_COUNT (4U) /*! @name COMBINE - Combine Channel */ /*! @{ */ #define TPM_COMBINE_COMBINE0_MASK (0x1U) #define TPM_COMBINE_COMBINE0_SHIFT (0U) /*! COMBINE0 - Combine Channels 0 and 1 * 0b0..Independent * 0b1..Combined */ #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) #define TPM_COMBINE_COMSWAP0_MASK (0x2U) #define TPM_COMBINE_COMSWAP0_SHIFT (1U) /*! COMSWAP0 - Combine Channel 0 and 1 Swap * 0b0..Even channel * 0b1..Odd channel */ #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) #define TPM_COMBINE_COMBINE1_MASK (0x100U) #define TPM_COMBINE_COMBINE1_SHIFT (8U) /*! COMBINE1 - Combine Channels 2 and 3 * 0b0..Independent * 0b1..Combined */ #define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) #define TPM_COMBINE_COMSWAP1_MASK (0x200U) #define TPM_COMBINE_COMSWAP1_SHIFT (9U) /*! COMSWAP1 - Combine Channels 2 and 3 Swap * 0b0..Even channel * 0b1..Odd channel */ #define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) /*! @} */ /*! @name TRIG - Channel Trigger */ /*! @{ */ #define TPM_TRIG_TRIG0_MASK (0x1U) #define TPM_TRIG_TRIG0_SHIFT (0U) /*! TRIG0 - Channel 0 Trigger * 0b0..No effect * 0b1..Configures trigger input 0 to be used by channel 0 */ #define TPM_TRIG_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG0_SHIFT)) & TPM_TRIG_TRIG0_MASK) #define TPM_TRIG_TRIG1_MASK (0x2U) #define TPM_TRIG_TRIG1_SHIFT (1U) /*! TRIG1 - Channel 1 Trigger * 0b0..No effect * 0b1..Configures trigger input 1 to be used by channel 1 */ #define TPM_TRIG_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG1_SHIFT)) & TPM_TRIG_TRIG1_MASK) #define TPM_TRIG_TRIG2_MASK (0x4U) #define TPM_TRIG_TRIG2_SHIFT (2U) /*! TRIG2 - Channel 2 Trigger * 0b0..No effect * 0b1..Configures trigger input 0 to be used by channel 2 */ #define TPM_TRIG_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG2_SHIFT)) & TPM_TRIG_TRIG2_MASK) #define TPM_TRIG_TRIG3_MASK (0x8U) #define TPM_TRIG_TRIG3_SHIFT (3U) /*! TRIG3 - Channel 3 Trigger * 0b0..No effect * 0b1..Configures trigger input 1 to be used by channel 3 */ #define TPM_TRIG_TRIG3(x) (((uint32_t)(((uint32_t)(x)) << TPM_TRIG_TRIG3_SHIFT)) & TPM_TRIG_TRIG3_MASK) /*! @} */ /*! @name POL - Channel Polarity */ /*! @{ */ #define TPM_POL_POL0_MASK (0x1U) #define TPM_POL_POL0_SHIFT (0U) /*! POL0 - Channel 0 Polarity * 0b0..Active high * 0b1..Active low */ #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) #define TPM_POL_POL1_MASK (0x2U) #define TPM_POL_POL1_SHIFT (1U) /*! POL1 - Channel 1 Polarity * 0b0..Active high * 0b1..Active low */ #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) #define TPM_POL_POL2_MASK (0x4U) #define TPM_POL_POL2_SHIFT (2U) /*! POL2 - Channel 2 Polarity * 0b0..Active high * 0b1..Active low */ #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) #define TPM_POL_POL3_MASK (0x8U) #define TPM_POL_POL3_SHIFT (3U) /*! POL3 - Channel 3 Polarity * 0b0..Active high * 0b1..Active low */ #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) /*! @} */ /*! @name FILTER - Filter Control */ /*! @{ */ #define TPM_FILTER_CH0FVAL_MASK (0xFU) #define TPM_FILTER_CH0FVAL_SHIFT (0U) /*! CH0FVAL - Channel 0 Filter Value */ #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) #define TPM_FILTER_CH1FVAL_MASK (0xF0U) #define TPM_FILTER_CH1FVAL_SHIFT (4U) /*! CH1FVAL - Channel 1 Filter Value */ #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) #define TPM_FILTER_CH2FVAL_MASK (0xF00U) #define TPM_FILTER_CH2FVAL_SHIFT (8U) /*! CH2FVAL - Channel 2 Filter Value */ #define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) #define TPM_FILTER_CH3FVAL_MASK (0xF000U) #define TPM_FILTER_CH3FVAL_SHIFT (12U) /*! CH3FVAL - Channel 3 Filter Value */ #define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) /*! @} */ /*! @name QDCTRL - Quadrature Decoder Control and Status */ /*! @{ */ #define TPM_QDCTRL_QUADEN_MASK (0x1U) #define TPM_QDCTRL_QUADEN_SHIFT (0U) /*! QUADEN - Quadrature Decoder Enable * 0b0..Disable * 0b1..Enable */ #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK) #define TPM_QDCTRL_TOFDIR_MASK (0x2U) #define TPM_QDCTRL_TOFDIR_SHIFT (1U) /*! TOFDIR - Timer Overflow Direction * 0b0..Bottom of counting * 0b1..Top of counting */ #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK) #define TPM_QDCTRL_QUADIR_MASK (0x4U) #define TPM_QDCTRL_QUADIR_SHIFT (2U) /*! QUADIR - Counter Direction in Quadrature Decode Mode * 0b0..Decreasing (counter decrement) * 0b1..Increasing (counter increment) */ #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK) #define TPM_QDCTRL_QUADMODE_MASK (0x8U) #define TPM_QDCTRL_QUADMODE_SHIFT (3U) /*! QUADMODE - Quadrature Decoder Mode * 0b0..Phase encoding mode * 0b1..Count and direction encoding mode */ #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK) /*! @} */ /*! @name CONF - Configuration */ /*! @{ */ #define TPM_CONF_DOZEEN_MASK (0x20U) #define TPM_CONF_DOZEEN_SHIFT (5U) /*! DOZEEN - Doze Enable * 0b0..TPM counter continues * 0b1..TPM counter pauses */ #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) #define TPM_CONF_DBGMODE_MASK (0xC0U) #define TPM_CONF_DBGMODE_SHIFT (6U) /*! DBGMODE - Debug Mode * 0b00..TPM counter pauses * 0b11..TPM counter continues */ #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) #define TPM_CONF_CSOT_MASK (0x10000U) #define TPM_CONF_CSOT_SHIFT (16U) /*! CSOT - Counter Start on Trigger * 0b0..Counter starts immediately * 0b1..Counter starts after detection of a rising edge on the selected input trigger */ #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) #define TPM_CONF_CSOO_MASK (0x20000U) #define TPM_CONF_CSOO_SHIFT (17U) /*! CSOO - Counter Stop on Overflow * 0b0..TPM counter continues * 0b1..TPM counter stops */ #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) #define TPM_CONF_CROT_MASK (0x40000U) #define TPM_CONF_CROT_SHIFT (18U) /*! CROT - Counter Reload on Trigger * 0b0..No reload * 0b1..Reload */ #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) #define TPM_CONF_CPOT_MASK (0x80000U) #define TPM_CONF_CPOT_SHIFT (19U) /*! CPOT - Counter Pause on Trigger * 0b0..TPM counter continues * 0b1..TPM counter pauses */ #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) #define TPM_CONF_TRGPOL_MASK (0x400000U) #define TPM_CONF_TRGPOL_SHIFT (22U) /*! TRGPOL - Trigger Polarity * 0b0..Active high * 0b1..Active low */ #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) #define TPM_CONF_TRGSRC_MASK (0x800000U) #define TPM_CONF_TRGSRC_SHIFT (23U) /*! TRGSRC - Trigger Source * 0b0..External * 0b1..Internal (channel pin input capture) */ #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) #define TPM_CONF_TRGSEL_MASK (0x3000000U) #define TPM_CONF_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select * 0b01..Channel 0 pin input capture * 0b10..Channel 1 pin input capture * 0b11..Channel 0 or channel 1 pin input capture */ #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) /*! @} */ /*! * @} */ /* end of group TPM_Register_Masks */ /* TPM - Peripheral instance base addresses */ /** Peripheral TPM1 base address */ #define TPM1_BASE (0x44310000u) /** Peripheral TPM1 base pointer */ #define TPM1 ((TPM_Type *)TPM1_BASE) /** Peripheral TPM2 base address */ #define TPM2_BASE (0x44320000u) /** Peripheral TPM2 base pointer */ #define TPM2 ((TPM_Type *)TPM2_BASE) /** Peripheral TPM3 base address */ #define TPM3_BASE (0x424E0000u) /** Peripheral TPM3 base pointer */ #define TPM3 ((TPM_Type *)TPM3_BASE) /** Peripheral TPM4 base address */ #define TPM4_BASE (0x424F0000u) /** Peripheral TPM4 base pointer */ #define TPM4 ((TPM_Type *)TPM4_BASE) /** Peripheral TPM5 base address */ #define TPM5_BASE (0x42500000u) /** Peripheral TPM5 base pointer */ #define TPM5 ((TPM_Type *)TPM5_BASE) /** Peripheral TPM6 base address */ #define TPM6_BASE (0x42510000u) /** Peripheral TPM6 base pointer */ #define TPM6 ((TPM_Type *)TPM6_BASE) /** Array initializer of TPM peripheral base addresses */ #define TPM_BASE_ADDRS { TPM1_BASE, TPM2_BASE, TPM3_BASE, TPM4_BASE, TPM5_BASE, TPM6_BASE } /** Array initializer of TPM peripheral base pointers */ #define TPM_BASE_PTRS { TPM1, TPM2, TPM3, TPM4, TPM5, TPM6 } /** Interrupt vectors for the TPM peripheral type */ #define TPM_IRQS { TPM1_IRQn, TPM2_IRQn, TPM3_IRQn, TPM4_IRQn, TPM5_IRQn, TPM6_IRQn } /*! * @} */ /* end of group TPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TSTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TSTMR_Peripheral_Access_Layer TSTMR Peripheral Access Layer * @{ */ /** TSTMR - Register Layout Typedef */ typedef struct { __I uint32_t L; /**< Timestamp Timer Low, offset: 0x0 */ __I uint32_t H; /**< Timestamp Timer High, offset: 0x4 */ } TSTMR_Type; /* ---------------------------------------------------------------------------- -- TSTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TSTMR_Register_Masks TSTMR Register Masks * @{ */ /*! @name L - Timestamp Timer Low */ /*! @{ */ #define TSTMR_L_VALUE_MASK (0xFFFFFFFFU) #define TSTMR_L_VALUE_SHIFT (0U) /*! VALUE - Timestamp Timer Low */ #define TSTMR_L_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_L_VALUE_SHIFT)) & TSTMR_L_VALUE_MASK) /*! @} */ /*! @name H - Timestamp Timer High */ /*! @{ */ #define TSTMR_H_VALUE_MASK (0xFFFFFFU) #define TSTMR_H_VALUE_SHIFT (0U) /*! VALUE - Timestamp Timer High */ #define TSTMR_H_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSTMR_H_VALUE_SHIFT)) & TSTMR_H_VALUE_MASK) /*! @} */ /*! * @} */ /* end of group TSTMR_Register_Masks */ /* TSTMR - Peripheral instance base addresses */ /** Peripheral TSTMR1 base address */ #define TSTMR1_BASE (0x442C0000u) /** Peripheral TSTMR1 base pointer */ #define TSTMR1 ((TSTMR_Type *)TSTMR1_BASE) /** Peripheral TSTMR2 base address */ #define TSTMR2_BASE (0x42480000u) /** Peripheral TSTMR2 base pointer */ #define TSTMR2 ((TSTMR_Type *)TSTMR2_BASE) /** Array initializer of TSTMR peripheral base addresses */ #define TSTMR_BASE_ADDRS { 0u, TSTMR1_BASE, TSTMR2_BASE } /** Array initializer of TSTMR peripheral base pointers */ #define TSTMR_BASE_PTRS { (TSTMR_Type *)0u, TSTMR1, TSTMR2 } /* Extra definition */ #define TSTMR_CLOCK_FREQUENCY_MHZ (24U) /*! * @} */ /* end of group TSTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer * @{ */ /** USB - Register Layout Typedef */ typedef struct { __I uint32_t ID; /**< Identification, offset: 0x0 */ __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ uint8_t RESERVED_0[104]; __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ uint8_t RESERVED_1[108]; __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ uint8_t RESERVED_2[1]; __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ uint8_t RESERVED_3[20]; __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ uint8_t RESERVED_4[2]; __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ uint8_t RESERVED_5[24]; __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ uint8_t RESERVED_6[4]; union { /* offset: 0x154 */ __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ }; union { /* offset: 0x158 */ __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ }; uint8_t RESERVED_7[4]; __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ uint8_t RESERVED_8[16]; __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ uint8_t RESERVED_9[28]; __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ } USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /*! @name ID - Identification */ /*! @{ */ #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) /*! ID - ID */ #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) #define USB_ID_NID_MASK (0x3F00U) #define USB_ID_NID_SHIFT (8U) /*! NID - NID */ #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) /*! REVISION - REVISION */ #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) /*! @} */ /*! @name HWGENERAL - Hardware General */ /*! @{ */ #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) /*! PHYW - PHYW * 0b00..8 bit wide data bus (Software non-programmable) * 0b01..16 bit wide data bus (Software non-programmable) * 0b10..Reset to 8 bit wide data bus (Software programmable) * 0b11..Reset to 16 bit wide data bus (Software programmable) */ #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) #define USB_HWGENERAL_PHYM_MASK (0x3C0U) #define USB_HWGENERAL_PHYM_SHIFT (6U) /*! PHYM - PHYM * 0b0000..UTMI/UMTI+ * 0b0001..ULPI DDR * 0b0010..ULPI * 0b0011..Serial only * 0b0100..Software programmable - reset to UTMI/UTMI+ * 0b0101..Software programmable - reset to ULPI DDR * 0b0110..Software programmable - reset to ULPI * 0b0111..Software programmable - reset to serial * 0b1000..IC - USB * 0b1001..Software programmable - reset to IC - USB * 0b1010..HSIC * 0b1011..Software programmable - reset to HSIC * 0b1100..Reserved * 0b1111..Reserved */ #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) #define USB_HWGENERAL_SM_MASK (0xC00U) #define USB_HWGENERAL_SM_SHIFT (10U) /*! SM - SM * 0b00..No Serial Engine, always use parallel signalling. * 0b01..Serial Engine present, always use serial signalling for FS/LS. * 0b10..Software programmable - Reset to use parallel signalling for FS/LS * 0b11..Software programmable - Reset to use serial signalling for FS/LS */ #define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) /*! @} */ /*! @name HWHOST - Host Hardware Parameters */ /*! @{ */ #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) /*! HC - HC * 0b1..Supported * 0b0..Not supported */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) /*! NPORT - NPORT */ #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) /*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ /*! @{ */ #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) /*! DC - DC * 0b1..Supported * 0b0..Not supported */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) /*! DEVEP - DEVEP */ #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) /*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) /*! TXBURST - TXBURST */ #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) /*! TXCHANADD - TXCHANADD */ #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) /*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ /*! @{ */ #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) /*! RXBURST - RXBURST */ #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) /*! RXADD - RXADD */ #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) /*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ /*! @{ */ #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) /*! GPTLD - GPTLD */ #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ /*! @{ */ #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) /*! GPTCNT - GPTCNT */ #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE - GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) /*! GPTRST - GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN - GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) /*! @} */ /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ /*! @{ */ #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) /*! GPTLD - GPTLD */ #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ /*! @{ */ #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) /*! GPTCNT - GPTCNT */ #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) /*! GPTMODE - GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) /*! GPTRST - GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) /*! GPTRUN - GPTRUN * 0b0..Stop counting * 0b1..Run */ #define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) /*! @} */ /*! @name SBUSCFG - System Bus Config */ /*! @{ */ #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) /*! AHBBRST - AHBBRST * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer * 0b100..Reserved, don't use * 0b101..INCR4 burst, then incremental burst of unspecified length * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length */ #define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) /*! @} */ /*! @name CAPLENGTH - Capability Registers Length */ /*! @{ */ #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) /*! CAPLENGTH - CAPLENGTH */ #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ /*! @{ */ #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) /*! HCIVERSION - HCIVERSION */ #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) /*! N_PORTS - N_PORTS */ #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) #define USB_HCSPARAMS_PPC_MASK (0x10U) #define USB_HCSPARAMS_PPC_SHIFT (4U) /*! PPC - PPC */ #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) #define USB_HCSPARAMS_N_PCC_MASK (0xF00U) #define USB_HCSPARAMS_N_PCC_SHIFT (8U) /*! N_PCC - N_PCC */ #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) #define USB_HCSPARAMS_N_CC_MASK (0xF000U) #define USB_HCSPARAMS_N_CC_SHIFT (12U) /*! N_CC - N_CC * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. */ #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) #define USB_HCSPARAMS_PI_MASK (0x10000U) #define USB_HCSPARAMS_PI_SHIFT (16U) /*! PI - PI */ #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USB_HCSPARAMS_N_PTT_SHIFT (20U) /*! N_PTT - N_PTT */ #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) /*! N_TT - N_TT */ #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) /*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ /*! @{ */ #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) /*! ADC - ADC */ #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) #define USB_HCCPARAMS_PFL_MASK (0x2U) #define USB_HCCPARAMS_PFL_SHIFT (1U) /*! PFL - PFL */ #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) #define USB_HCCPARAMS_ASP_MASK (0x4U) #define USB_HCCPARAMS_ASP_SHIFT (2U) /*! ASP - ASP */ #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) #define USB_HCCPARAMS_IST_MASK (0xF0U) #define USB_HCCPARAMS_IST_SHIFT (4U) /*! IST - IST */ #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) /*! EECP - EECP */ #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) /*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ /*! @{ */ #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) /*! DCIVERSION - DCIVERSION */ #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) /*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ /*! @{ */ #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) /*! DEN - DEN */ #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) #define USB_DCCPARAMS_DC_MASK (0x80U) #define USB_DCCPARAMS_DC_SHIFT (7U) /*! DC - DC */ #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) /*! HC - HC */ #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) /*! @} */ /*! @name USBCMD - USB Command */ /*! @{ */ #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) /*! RS - RS */ #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) #define USB_USBCMD_RST_MASK (0x2U) #define USB_USBCMD_RST_SHIFT (1U) /*! RST - RST */ #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) #define USB_USBCMD_FS_1_MASK (0xCU) #define USB_USBCMD_FS_1_SHIFT (2U) /*! FS_1 - FS_1 */ #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) #define USB_USBCMD_PSE_MASK (0x10U) #define USB_USBCMD_PSE_SHIFT (4U) /*! PSE - PSE * 0b0..Do not process the Periodic Schedule * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. */ #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) #define USB_USBCMD_ASE_MASK (0x20U) #define USB_USBCMD_ASE_SHIFT (5U) /*! ASE - ASE * 0b0..Do not process the Asynchronous Schedule. * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */ #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) #define USB_USBCMD_IAA_MASK (0x40U) #define USB_USBCMD_IAA_SHIFT (6U) /*! IAA - IAA */ #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) #define USB_USBCMD_ASP_MASK (0x300U) #define USB_USBCMD_ASP_SHIFT (8U) /*! ASP - ASP */ #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) #define USB_USBCMD_ASPE_MASK (0x800U) #define USB_USBCMD_ASPE_SHIFT (11U) /*! ASPE - ASPE */ #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) #define USB_USBCMD_SUTW_MASK (0x2000U) #define USB_USBCMD_SUTW_SHIFT (13U) /*! SUTW - SUTW */ #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) #define USB_USBCMD_ATDTW_MASK (0x4000U) #define USB_USBCMD_ATDTW_SHIFT (14U) /*! ATDTW - ATDTW */ #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) #define USB_USBCMD_FS_2_MASK (0x8000U) #define USB_USBCMD_FS_2_SHIFT (15U) /*! FS_2 - FS_2 */ #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) /*! ITC - ITC * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames * 0b00000100..4 micro-frames * 0b00001000..8 micro-frames * 0b00010000..16 micro-frames * 0b00100000..32 micro-frames * 0b01000000..64 micro-frames */ #define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) /*! @} */ /*! @name USBSTS - USB Status */ /*! @{ */ #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) /*! UI - UI */ #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) #define USB_USBSTS_UEI_MASK (0x2U) #define USB_USBSTS_UEI_SHIFT (1U) /*! UEI - UEI */ #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) #define USB_USBSTS_PCI_MASK (0x4U) #define USB_USBSTS_PCI_SHIFT (2U) /*! PCI - PCI */ #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) #define USB_USBSTS_FRI_MASK (0x8U) #define USB_USBSTS_FRI_SHIFT (3U) /*! FRI - FRI */ #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) #define USB_USBSTS_SEI_MASK (0x10U) #define USB_USBSTS_SEI_SHIFT (4U) /*! SEI - SEI */ #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) #define USB_USBSTS_AAI_MASK (0x20U) #define USB_USBSTS_AAI_SHIFT (5U) /*! AAI - AAI */ #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) #define USB_USBSTS_URI_MASK (0x40U) #define USB_USBSTS_URI_SHIFT (6U) /*! URI - URI */ #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) #define USB_USBSTS_SRI_MASK (0x80U) #define USB_USBSTS_SRI_SHIFT (7U) /*! SRI - SRI */ #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) #define USB_USBSTS_SLI_MASK (0x100U) #define USB_USBSTS_SLI_SHIFT (8U) /*! SLI - SLI */ #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) #define USB_USBSTS_ULPII_MASK (0x400U) #define USB_USBSTS_ULPII_SHIFT (10U) /*! ULPII - ULPII */ #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) #define USB_USBSTS_HCH_MASK (0x1000U) #define USB_USBSTS_HCH_SHIFT (12U) /*! HCH - HCH */ #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) #define USB_USBSTS_RCL_MASK (0x2000U) #define USB_USBSTS_RCL_SHIFT (13U) /*! RCL - RCL */ #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) #define USB_USBSTS_PS_MASK (0x4000U) #define USB_USBSTS_PS_SHIFT (14U) /*! PS - PS */ #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) #define USB_USBSTS_AS_MASK (0x8000U) #define USB_USBSTS_AS_SHIFT (15U) /*! AS - AS */ #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) #define USB_USBSTS_NAKI_MASK (0x10000U) #define USB_USBSTS_NAKI_SHIFT (16U) /*! NAKI - NAKI */ #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) #define USB_USBSTS_UAI_MASK (0x40000U) #define USB_USBSTS_UAI_SHIFT (18U) /*! UAI - USB Host Asynchronous Interrupt * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UAI_SHIFT)) & USB_USBSTS_UAI_MASK) #define USB_USBSTS_UPI_MASK (0x80000U) #define USB_USBSTS_UPI_SHIFT (19U) /*! UPI - USB Host Periodic Interrupt * 0b0..Interrupt did not occur * 0b1..Interrupt occurred * 0b0..No effect * 0b1..Clear the flag */ #define USB_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UPI_SHIFT)) & USB_USBSTS_UPI_MASK) #define USB_USBSTS_TI0_MASK (0x1000000U) #define USB_USBSTS_TI0_SHIFT (24U) /*! TI0 - TI0 */ #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) /*! TI1 - TI1 */ #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) /*! @} */ /*! @name USBINTR - Interrupt Enable */ /*! @{ */ #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) /*! UE - UE */ #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) #define USB_USBINTR_UEE_MASK (0x2U) #define USB_USBINTR_UEE_SHIFT (1U) /*! UEE - UEE */ #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) #define USB_USBINTR_PCE_MASK (0x4U) #define USB_USBINTR_PCE_SHIFT (2U) /*! PCE - PCE */ #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) #define USB_USBINTR_FRE_MASK (0x8U) #define USB_USBINTR_FRE_SHIFT (3U) /*! FRE - FRE */ #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) #define USB_USBINTR_SEE_MASK (0x10U) #define USB_USBINTR_SEE_SHIFT (4U) /*! SEE - SEE */ #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) #define USB_USBINTR_AAE_MASK (0x20U) #define USB_USBINTR_AAE_SHIFT (5U) /*! AAE - AAE */ #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) #define USB_USBINTR_URE_MASK (0x40U) #define USB_USBINTR_URE_SHIFT (6U) /*! URE - URE */ #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) #define USB_USBINTR_SRE_MASK (0x80U) #define USB_USBINTR_SRE_SHIFT (7U) /*! SRE - SRE */ #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) #define USB_USBINTR_SLE_MASK (0x100U) #define USB_USBINTR_SLE_SHIFT (8U) /*! SLE - SLE */ #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) #define USB_USBINTR_NAKE_MASK (0x10000U) #define USB_USBINTR_NAKE_SHIFT (16U) /*! NAKE - NAKE */ #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) #define USB_USBINTR_UAIE_MASK (0x40000U) #define USB_USBINTR_UAIE_SHIFT (18U) /*! UAIE - UAIE */ #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) #define USB_USBINTR_UPIE_MASK (0x80000U) #define USB_USBINTR_UPIE_SHIFT (19U) /*! UPIE - UPIE */ #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) #define USB_USBINTR_TIE0_MASK (0x1000000U) #define USB_USBINTR_TIE0_SHIFT (24U) /*! TIE0 - TIE0 */ #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) /*! TIE1 - TIE1 */ #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) /*! @} */ /*! @name FRINDEX - USB Frame Index */ /*! @{ */ #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) /*! FRINDEX - FRINDEX * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 * 0b00000000000011..(128) 9 * 0b00000000000100..(64) 8 * 0b00000000000101..(32) 7 * 0b00000000000110..(16) 6 * 0b00000000000111..(8) 5 */ #define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) /*! @} */ /*! @name DEVICEADDR - Device Address */ /*! @{ */ #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) /*! USBADRA - USBADRA */ #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) /*! USBADR - USBADR */ #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) /*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ /*! @{ */ #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) /*! BASEADR - BASEADR */ #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ /*! @{ */ #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) /*! ASYBASE - ASYBASE */ #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ /*! @{ */ #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) /*! EPBASE - EPBASE */ #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ /*! @{ */ #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) /*! RXPBURST - RXPBURST */ #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) #define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) /*! TXPBURST - TXPBURST */ #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) /*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ /*! @{ */ #define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) /*! TXSCHOH - TXSCHOH */ #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) /*! TXSCHHEALTH - TXSCHHEALTH */ #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) /*! TXFIFOTHRES - TXFIFOTHRES */ #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ /*! @{ */ #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) /*! EPRN - EPRN */ #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) /*! EPTN - EPTN */ #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) /*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ /*! @{ */ #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) /*! EPRNE - EPRNE */ #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) /*! EPTNE - EPTNE */ #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) /*! @} */ /*! @name CONFIGFLAG - Configure Flag */ /*! @{ */ #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) /*! CF - CF * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. * 0b1..Port routing control logic default-routes all ports to this host controller. */ #define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) /*! @} */ /*! @name PORTSC1 - Port Status & Control */ /*! @{ */ #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) /*! CCS - CCS */ #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) #define USB_PORTSC1_CSC_MASK (0x2U) #define USB_PORTSC1_CSC_SHIFT (1U) /*! CSC - CSC */ #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) #define USB_PORTSC1_PE_MASK (0x4U) #define USB_PORTSC1_PE_SHIFT (2U) /*! PE - PE */ #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) #define USB_PORTSC1_PEC_MASK (0x8U) #define USB_PORTSC1_PEC_SHIFT (3U) /*! PEC - PEC */ #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) /*! OCA - OCA * 0b1..This port currently has an over-current condition * 0b0..This port does not have an over-current condition. */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) #define USB_PORTSC1_OCC_MASK (0x20U) #define USB_PORTSC1_OCC_SHIFT (5U) /*! OCC - OCC */ #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) #define USB_PORTSC1_FPR_MASK (0x40U) #define USB_PORTSC1_FPR_SHIFT (6U) /*! FPR - FPR */ #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) #define USB_PORTSC1_SUSP_MASK (0x80U) #define USB_PORTSC1_SUSP_SHIFT (7U) /*! SUSP - SUSP */ #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) #define USB_PORTSC1_PR_MASK (0x100U) #define USB_PORTSC1_PR_SHIFT (8U) /*! PR - PR */ #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) #define USB_PORTSC1_HSP_MASK (0x200U) #define USB_PORTSC1_HSP_SHIFT (9U) /*! HSP - HSP */ #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) #define USB_PORTSC1_LS_MASK (0xC00U) #define USB_PORTSC1_LS_SHIFT (10U) /*! LS - LS * 0b00..SE0 * 0b10..J-state * 0b01..K-state * 0b11..Undefined */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) #define USB_PORTSC1_PP_MASK (0x1000U) #define USB_PORTSC1_PP_SHIFT (12U) /*! PP - PP */ #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) #define USB_PORTSC1_PO_MASK (0x2000U) #define USB_PORTSC1_PO_SHIFT (13U) /*! PO - PO */ #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) #define USB_PORTSC1_PIC_MASK (0xC000U) #define USB_PORTSC1_PIC_SHIFT (14U) /*! PIC - PIC * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green * 0b11..Undefined */ #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) #define USB_PORTSC1_PTC_MASK (0xF0000U) #define USB_PORTSC1_PTC_SHIFT (16U) /*! PTC - PTC * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE * 0b0011..SE0 (host) / NAK (device) * 0b0100..Packet * 0b0101..FORCE_ENABLE_HS * 0b0110..FORCE_ENABLE_FS * 0b0111..FORCE_ENABLE_LS * 0b1000-0b1111..Reserved */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) #define USB_PORTSC1_WKCN_MASK (0x100000U) #define USB_PORTSC1_WKCN_SHIFT (20U) /*! WKCN - WKCN */ #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) #define USB_PORTSC1_WKDC_MASK (0x200000U) #define USB_PORTSC1_WKDC_SHIFT (21U) /*! WKDC - WKDC */ #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) #define USB_PORTSC1_WKOC_MASK (0x400000U) #define USB_PORTSC1_WKOC_SHIFT (22U) /*! WKOC - WKOC */ #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) /*! PHCD - PHCD * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) /*! PFSC - PFSC * 0b1..Forced to full speed * 0b0..Normal operation */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) #define USB_PORTSC1_PTS_2_MASK (0x2000000U) #define USB_PORTSC1_PTS_2_SHIFT (25U) /*! PTS_2 - PTS_2 */ #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) #define USB_PORTSC1_PSPD_MASK (0xC000000U) #define USB_PORTSC1_PSPD_SHIFT (26U) /*! PSPD - PSPD * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed * 0b11..Undefined */ #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) #define USB_PORTSC1_PTW_MASK (0x10000000U) #define USB_PORTSC1_PTW_SHIFT (28U) /*! PTW - PTW * 0b0..Select the 8-bit UTMI interface [60MHz] * 0b1..Select the 16-bit UTMI interface [30MHz] */ #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) #define USB_PORTSC1_STS_MASK (0x20000000U) #define USB_PORTSC1_STS_SHIFT (29U) /*! STS - STS */ #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) /*! PTS_1 - PTS_1 */ #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) /*! @} */ /*! @name OTGSC - On-The-Go Status & control */ /*! @{ */ #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) /*! VD - VD */ #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) #define USB_OTGSC_VC_MASK (0x2U) #define USB_OTGSC_VC_SHIFT (1U) /*! VC - VC */ #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) #define USB_OTGSC_OT_MASK (0x8U) #define USB_OTGSC_OT_SHIFT (3U) /*! OT - OT */ #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) #define USB_OTGSC_DP_MASK (0x10U) #define USB_OTGSC_DP_SHIFT (4U) /*! DP - DP */ #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) #define USB_OTGSC_IDPU_MASK (0x20U) #define USB_OTGSC_IDPU_SHIFT (5U) /*! IDPU - IDPU */ #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) #define USB_OTGSC_ID_MASK (0x100U) #define USB_OTGSC_ID_SHIFT (8U) /*! ID - ID */ #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) #define USB_OTGSC_AVV_MASK (0x200U) #define USB_OTGSC_AVV_SHIFT (9U) /*! AVV - AVV */ #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) #define USB_OTGSC_ASV_MASK (0x400U) #define USB_OTGSC_ASV_SHIFT (10U) /*! ASV - ASV */ #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) #define USB_OTGSC_BSV_MASK (0x800U) #define USB_OTGSC_BSV_SHIFT (11U) /*! BSV - BSV */ #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) #define USB_OTGSC_BSE_MASK (0x1000U) #define USB_OTGSC_BSE_SHIFT (12U) /*! BSE - BSE */ #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) #define USB_OTGSC_TOG_1MS_MASK (0x2000U) #define USB_OTGSC_TOG_1MS_SHIFT (13U) /*! TOG_1MS - TOG_1MS */ #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) #define USB_OTGSC_DPS_MASK (0x4000U) #define USB_OTGSC_DPS_SHIFT (14U) /*! DPS - DPS */ #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) #define USB_OTGSC_IDIS_MASK (0x10000U) #define USB_OTGSC_IDIS_SHIFT (16U) /*! IDIS - IDIS */ #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) #define USB_OTGSC_AVVIS_MASK (0x20000U) #define USB_OTGSC_AVVIS_SHIFT (17U) /*! AVVIS - AVVIS */ #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) #define USB_OTGSC_ASVIS_MASK (0x40000U) #define USB_OTGSC_ASVIS_SHIFT (18U) /*! ASVIS - ASVIS */ #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) #define USB_OTGSC_BSVIS_MASK (0x80000U) #define USB_OTGSC_BSVIS_SHIFT (19U) /*! BSVIS - BSVIS */ #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) #define USB_OTGSC_BSEIS_MASK (0x100000U) #define USB_OTGSC_BSEIS_SHIFT (20U) /*! BSEIS - BSEIS */ #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) #define USB_OTGSC_STATUS_1MS_MASK (0x200000U) #define USB_OTGSC_STATUS_1MS_SHIFT (21U) /*! STATUS_1MS - STATUS_1MS */ #define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) #define USB_OTGSC_DPIS_MASK (0x400000U) #define USB_OTGSC_DPIS_SHIFT (22U) /*! DPIS - DPIS */ #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) #define USB_OTGSC_IDIE_MASK (0x1000000U) #define USB_OTGSC_IDIE_SHIFT (24U) /*! IDIE - IDIE */ #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) #define USB_OTGSC_AVVIE_MASK (0x2000000U) #define USB_OTGSC_AVVIE_SHIFT (25U) /*! AVVIE - AVVIE */ #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) #define USB_OTGSC_ASVIE_MASK (0x4000000U) #define USB_OTGSC_ASVIE_SHIFT (26U) /*! ASVIE - ASVIE */ #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) #define USB_OTGSC_BSVIE_MASK (0x8000000U) #define USB_OTGSC_BSVIE_SHIFT (27U) /*! BSVIE - BSVIE */ #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) #define USB_OTGSC_BSEIE_MASK (0x10000000U) #define USB_OTGSC_BSEIE_SHIFT (28U) /*! BSEIE - BSEIE */ #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) #define USB_OTGSC_EN_1MS_MASK (0x20000000U) #define USB_OTGSC_EN_1MS_SHIFT (29U) /*! EN_1MS - EN_1MS */ #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) /*! DPIE - DPIE */ #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) /*! @} */ /*! @name USBMODE - USB Device Mode */ /*! @{ */ #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) /*! CM - CM * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] * 0b11..Host Controller [Default for host only controller] */ #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) #define USB_USBMODE_ES_MASK (0x4U) #define USB_USBMODE_ES_SHIFT (2U) /*! ES - ES * 0b0..Little Endian [Default] * 0b1..Big Endian */ #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) #define USB_USBMODE_SLOM_MASK (0x8U) #define USB_USBMODE_SLOM_SHIFT (3U) /*! SLOM - SLOM * 0b0..Setup Lockouts On (default); * 0b1..Setup Lockouts Off */ #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) /*! SDIS - SDIS */ #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) /*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ /*! @{ */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) /*! ENDPTSETUPSTAT - ENDPTSETUPSTAT */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ /*! @{ */ #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) /*! PERB - PERB */ #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) /*! PETB - PETB */ #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) /*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ /*! @{ */ #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) /*! FERB - FERB */ #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) /*! FETB - FETB */ #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) /*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ /*! @{ */ #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) /*! ERBR - ERBR */ #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) /*! ETBR - ETBR */ #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) /*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ /*! @{ */ #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) /*! ERCE - ERCE */ #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) /*! ETCE - ETCE */ #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control0 */ /*! @{ */ #define USB_ENDPTCTRL0_RXS_MASK (0x1U) #define USB_ENDPTCTRL0_RXS_SHIFT (0U) /*! RXS - RXS */ #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) #define USB_ENDPTCTRL0_RXT_MASK (0xCU) #define USB_ENDPTCTRL0_RXT_SHIFT (2U) /*! RXT - RXT */ #define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) #define USB_ENDPTCTRL0_RXE_MASK (0x80U) #define USB_ENDPTCTRL0_RXE_SHIFT (7U) /*! RXE - RXE */ #define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) #define USB_ENDPTCTRL0_TXS_MASK (0x10000U) #define USB_ENDPTCTRL0_TXS_SHIFT (16U) /*! TXS - TXS */ #define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) #define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL0_TXT_SHIFT (18U) /*! TXT - TXT */ #define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) #define USB_ENDPTCTRL0_TXE_MASK (0x800000U) #define USB_ENDPTCTRL0_TXE_SHIFT (23U) /*! TXE - TXE */ #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) /*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ /*! @{ */ #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) /*! RXS - RXS */ #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) #define USB_ENDPTCTRL_RXD_MASK (0x2U) #define USB_ENDPTCTRL_RXD_SHIFT (1U) /*! RXD - RXD */ #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) #define USB_ENDPTCTRL_RXT_MASK (0xCU) #define USB_ENDPTCTRL_RXT_SHIFT (2U) /*! RXT - RXT */ #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) #define USB_ENDPTCTRL_RXI_MASK (0x20U) #define USB_ENDPTCTRL_RXI_SHIFT (5U) /*! RXI - RXI */ #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) #define USB_ENDPTCTRL_RXR_MASK (0x40U) #define USB_ENDPTCTRL_RXR_SHIFT (6U) /*! RXR - RXR */ #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) #define USB_ENDPTCTRL_RXE_MASK (0x80U) #define USB_ENDPTCTRL_RXE_SHIFT (7U) /*! RXE - RXE */ #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) #define USB_ENDPTCTRL_TXS_MASK (0x10000U) #define USB_ENDPTCTRL_TXS_SHIFT (16U) /*! TXS - TXS */ #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) #define USB_ENDPTCTRL_TXD_MASK (0x20000U) #define USB_ENDPTCTRL_TXD_SHIFT (17U) /*! TXD - TXD */ #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) #define USB_ENDPTCTRL_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL_TXT_SHIFT (18U) /*! TXT - TXT */ #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) #define USB_ENDPTCTRL_TXI_MASK (0x200000U) #define USB_ENDPTCTRL_TXI_SHIFT (21U) /*! TXI - TXI */ #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) #define USB_ENDPTCTRL_TXR_MASK (0x400000U) #define USB_ENDPTCTRL_TXR_SHIFT (22U) /*! TXR - TXR */ #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) /*! TXE - TXE */ #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) /*! @} */ /* The count of USB_ENDPTCTRL */ #define USB_ENDPTCTRL_COUNT (7U) /*! * @} */ /* end of group USB_Register_Masks */ /* USB - Peripheral instance base addresses */ /** Peripheral USBC base address */ #define USBC_BASE (0x4C200000u) /** Peripheral USBC base pointer */ #define USBC ((USB_Type *)USBC_BASE) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { USBC_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { USBC } /* Backward compatibility */ #define GPTIMER0CTL GPTIMER0CTRL #define GPTIMER1CTL GPTIMER1CTRL #define USB_SBUSCFG SBUSCFG #define EPLISTADDR ENDPTLISTADDR #define EPSETUPSR ENDPTSETUPSTAT #define EPPRIME ENDPTPRIME #define EPFLUSH ENDPTFLUSH #define EPSR ENDPTSTAT #define EPCOMPLETE ENDPTCOMPLETE #define EPCR ENDPTCTRL #define EPCR0 ENDPTCTRL0 #define USBHS_ID_ID_MASK USB_ID_ID_MASK #define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT #define USBHS_ID_ID(x) USB_ID_ID(x) #define USBHS_ID_NID_MASK USB_ID_NID_MASK #define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT #define USBHS_ID_NID(x) USB_ID_NID(x) #define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK #define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT #define USBHS_ID_REVISION(x) USB_ID_REVISION(x) #define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK #define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT #define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) #define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK #define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT #define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) #define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK #define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT #define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) #define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK #define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT #define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) #define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK #define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT #define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) #define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK #define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT #define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) #define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK #define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT #define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) #define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK #define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT #define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) #define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK #define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT #define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) #define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK #define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT #define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) #define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK #define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT #define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) #define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK #define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT #define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) #define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT #define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) #define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK #define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT #define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) #define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK #define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT #define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) #define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK #define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT #define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) #define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK #define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT #define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) #define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT #define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) #define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK #define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT #define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) #define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK #define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT #define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) #define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK #define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT #define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) #define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT #define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) #define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) #define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK #define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT #define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) #define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK #define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT #define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) #define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK #define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT #define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) #define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK #define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT #define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) #define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK #define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT #define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) #define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK #define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT #define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) #define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK #define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT #define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) #define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK #define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT #define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) #define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK #define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT #define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) #define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK #define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT #define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) #define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK #define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT #define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) #define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK #define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT #define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) #define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK #define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT #define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) #define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK #define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT #define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) #define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK #define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT #define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) #define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK #define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT #define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) #define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK #define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT #define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) #define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK #define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT #define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) #define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK #define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT #define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) #define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK #define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT #define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) #define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK #define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT #define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) #define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK #define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT #define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) #define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK #define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT #define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) #define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK #define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT #define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) #define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK #define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT #define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) #define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK #define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT #define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) #define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK #define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT #define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) #define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK #define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT #define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) #define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK #define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT #define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) #define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK #define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT #define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) #define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK #define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT #define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) #define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK #define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT #define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) #define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK #define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT #define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) #define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK #define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT #define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) #define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK #define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT #define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) #define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK #define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT #define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) #define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK #define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT #define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) #define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK #define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT #define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) #define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK #define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT #define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) #define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK #define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT #define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) #define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK #define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT #define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) #define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK #define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT #define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) #define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK #define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT #define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) #define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK #define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT #define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) #define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK #define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT #define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) #define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK #define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT #define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) #define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK #define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT #define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) #define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK #define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT #define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) #define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK #define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT #define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) #define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK #define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT #define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) #define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK #define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT #define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) #define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK #define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT #define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) #define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK #define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT #define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) #define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK #define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT #define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) #define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK #define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT #define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) #define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK #define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT #define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) #define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK #define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT #define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) #define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK #define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT #define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) #define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK #define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT #define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) #define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK #define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT #define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) #define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK #define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT #define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) #define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK #define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT #define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) #define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK #define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT #define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) #define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK #define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT #define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) #define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT #define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) #define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT #define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) #define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK #define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT #define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) #define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK #define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT #define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) #define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK #define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT #define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) #define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT #define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT #define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT #define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) #define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK #define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT #define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) #define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK #define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT #define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) #define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK #define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT #define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) #define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK #define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT #define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) #define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK #define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT #define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) #define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK #define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT #define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) #define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK #define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT #define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) #define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK #define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT #define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) #define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK #define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT #define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) #define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK #define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT #define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) #define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK #define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT #define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) #define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK #define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT #define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) #define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK #define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT #define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) #define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK #define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT #define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) #define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK #define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT #define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) #define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK #define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT #define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) #define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK #define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT #define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) #define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK #define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT #define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) #define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK #define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT #define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) #define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK #define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT #define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) #define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK #define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT #define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) #define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK #define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT #define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) #define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK #define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT #define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) #define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK #define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT #define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) #define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK #define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT #define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) #define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK #define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT #define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) #define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK #define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT #define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) #define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK #define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT #define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) #define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK #define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT #define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) #define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK #define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT #define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) #define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK #define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT #define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) #define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK #define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT #define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) #define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK #define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT #define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) #define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK #define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT #define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) #define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK #define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT #define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) #define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK #define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT #define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) #define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK #define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT #define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) #define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK #define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT #define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) #define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK #define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT #define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) #define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK #define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT #define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) #define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK #define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT #define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) #define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK #define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT #define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) #define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK #define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT #define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) #define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK #define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT #define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) #define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK #define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT #define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) #define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK #define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT #define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) #define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK #define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT #define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) #define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK #define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT #define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) #define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK #define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT #define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) #define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK #define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT #define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) #define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK #define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT #define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) #define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK #define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT #define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) #define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK #define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT #define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) #define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK #define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT #define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) #define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK #define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT #define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) #define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK #define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT #define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) #define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK #define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT #define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) #define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK #define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT #define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) #define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK #define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT #define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) #define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK #define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT #define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT #define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) #define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK #define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT #define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) #define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK #define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT #define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) #define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK #define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT #define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) #define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK #define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT #define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) #define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK #define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT #define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) #define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK #define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT #define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) #define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK #define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT #define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) #define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK #define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT #define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) #define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK #define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT #define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) #define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK #define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT #define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) #define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK #define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT #define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) #define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK #define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT #define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) #define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK #define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT #define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) #define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK #define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT #define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) #define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK #define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT #define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) #define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK #define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT #define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) #define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK #define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT #define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) #define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK #define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT #define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) #define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK #define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT #define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) #define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK #define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT #define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) #define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK #define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT #define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) #define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK #define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT #define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) #define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK #define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT #define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) #define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK #define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT #define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) #define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK #define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT #define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) #define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK #define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT #define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) #define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT #define USBHS_Type USB_Type #define USBHS_BASE_ADDRS USB_BASE_ADDRS #define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } #define USBHS_IRQHandler USB_OTG1_IRQHandler #define USBHS_STACK_BASE_ADDRS { USB_OTG1_BASE, USB_OTG2_BASE } /*! * @} */ /* end of group USB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB3_CORE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_CORE_Peripheral_Access_Layer USB3_CORE Peripheral Access Layer * @{ */ /** USB3_CORE - Register Layout Typedef */ typedef struct { __I uint32_t CAPLENGTH; /**< Capability Registers Length and Host Controller Operational Registers, offset: 0x0 */ __I uint32_t HCSPARAMS1; /**< Structural Parameters 1, offset: 0x4 */ __I uint32_t HCSPARAMS2; /**< Structural Parameters 2, offset: 0x8 */ __I uint32_t HCSPARAMS3; /**< Structural Parameters 3, offset: 0xC */ __I uint32_t HCCPARAMS1; /**< Host Controller Capability Parameters 1, offset: 0x10 */ __I uint32_t DBOFF; /**< Doorbell Offset, offset: 0x14 */ __I uint32_t RTSOFF; /**< Runtime Register Space Offset, offset: 0x18 */ __I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Status, offset: 0x24 */ __I uint32_t PAGESIZE; /**< Page Size, offset: 0x28 */ uint8_t RESERVED_0[8]; __IO uint32_t DNCTRL; /**< Device Notification, offset: 0x34 */ __IO uint32_t CRCR_LO; /**< Command Ring Control - Low, offset: 0x38 */ __IO uint32_t CRCR_HI; /**< Command Ring Control - High, offset: 0x3C */ uint8_t RESERVED_1[16]; __IO uint32_t DCBAAP_LO; /**< Device Context Base Address Array Pointer - Low, offset: 0x50 */ __IO uint32_t DCBAAP_HI; /**< Device Context Base Address Array Pointer -High, offset: 0x54 */ __IO uint32_t CONFIG; /**< Configuration, offset: 0x58 */ uint8_t RESERVED_2[964]; __IO uint32_t PORTSC_20; /**< USB2 Port Status and Control, offset: 0x420 */ __IO uint32_t PORTPMSC_20; /**< USB2 Port Power Management Status and Control, offset: 0x424 */ uint32_t PORTLI_20; /**< USB2 Port Link Information, offset: 0x428 */ __IO uint32_t PORTHLPMC_20; /**< USB2 Port Hardware LPM Control, offset: 0x42C */ __IO uint32_t PORTSC_30; /**< USB3 Port Status and Control, offset: 0x430 */ __IO uint32_t PORTPMSC_30; /**< USB3 Port Power Management Status and Control, offset: 0x434 */ __I uint32_t PORTLI_30; /**< USB3 Port Link Information, offset: 0x438 */ uint32_t PORTHLPMC_30; /**< USB3 Port Hardware LPM Control, offset: 0x43C */ __I uint32_t MFINDEX; /**< Microframe Index, offset: 0x440 */ uint8_t RESERVED_3[28]; __IO uint32_t IMAN; /**< Interrupter Management, offset: 0x460 */ __IO uint32_t IMOD; /**< Interrupter Moderation, offset: 0x464 */ __IO uint32_t ERSTSZ; /**< Event Ring Segment Table Size, offset: 0x468 */ uint8_t RESERVED_4[4]; __IO uint32_t ERSTBA_LO; /**< Event Ring Segment Table Base Address - Low, offset: 0x470 */ __IO uint32_t ERSTBA_HI; /**< Event Ring Segment Table Base Address -Low, offset: 0x474 */ __IO uint32_t ERDP_LO; /**< Event Ring Dequeue - Low, offset: 0x478 */ __IO uint32_t ERDP_HI; /**< Event Ring Dequeue - Low, offset: 0x47C */ __IO uint32_t DB[64]; /**< Doorbell 0..Doorbell 63, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_5[768]; __IO uint32_t USBLEGSUP; /**< USB Legacy Support Capability, offset: 0x880 */ __IO uint32_t USBLEGCTLSTS; /**< USB Legacy Support Control and Status, offset: 0x884 */ uint8_t RESERVED_6[8]; __I uint32_t SUPTPRT2_DW0; /**< USB2 xHCI Supported Protocol Capability Data Word 0, offset: 0x890 */ __I uint32_t SUPTPRT2_DW1; /**< USB2 xHCI Supported Protocol Capability Data Word 1, offset: 0x894 */ __I uint32_t SUPTPRT2_DW2; /**< USB2 xHCI Supported Protocol Capability Data Word 2, offset: 0x898 */ __I uint32_t SUPTPRT2_DW3; /**< USB2 xHCI Supported Protocol Capability Data Word 3, offset: 0x89C */ __I uint32_t SUPTPRT3_DW0; /**< USB3 xHCI Supported Protocol Capability Data Word 0, offset: 0x8A0 */ __I uint32_t SUPTPRT3_DW1; /**< USB3 xHCI Supported Protocol Capability Data Word 1, offset: 0x8A4 */ __I uint32_t SUPTPRT3_DW2; /**< USB3 xHCI Supported Protocol Capability Data Word 2, offset: 0x8A8 */ __I uint32_t SUPTPRT3_DW3; /**< USB3 xHCI Supported Protocol Capability Data Word 3, offset: 0x8AC */ uint8_t RESERVED_7[47184]; __IO uint32_t GSBUSCFG0; /**< Global SoC Bus Configuration 0, offset: 0xC100 */ __IO uint32_t GSBUSCFG1; /**< Global SoC Bus Configuration 1, offset: 0xC104 */ __IO uint32_t GTXTHRCFG; /**< Global TX Threshold Control, offset: 0xC108 */ __IO uint32_t GRXTHRCFG; /**< Global RX Threshold Control, offset: 0xC10C */ __IO uint32_t GCTL; /**< Global Core Control, offset: 0xC110 */ uint8_t RESERVED_8[4]; __IO uint32_t GSTS; /**< Global Status, offset: 0xC118 */ __IO uint32_t GUCTL1; /**< Global User Control 1, offset: 0xC11C */ uint8_t RESERVED_9[8]; __IO uint32_t GUID; /**< Global User ID, offset: 0xC128 */ __IO uint32_t GUCTL; /**< Global User Control, offset: 0xC12C */ __I uint32_t GBUSERRADDRLO; /**< Global SoC Bus Error Address - Low, offset: 0xC130 */ __I uint32_t GBUSERRADDRHI; /**< Global SoC Bus Error Address - High, offset: 0xC134 */ __IO uint32_t GPRTBIMAPLO; /**< Global SS Port to Bus Instance Mapping - Low, offset: 0xC138 */ uint8_t RESERVED_10[4]; __I uint32_t GHWPARAMS0; /**< Global Hardware Parameters 0, offset: 0xC140 */ __I uint32_t GHWPARAMS1; /**< Global Hardware Parameters 1, offset: 0xC144 */ __I uint32_t GHWPARAMS2; /**< Global Hardware Parameters 2, offset: 0xC148 */ __I uint32_t GHWPARAMS3; /**< Global Hardware Parameters 3, offset: 0xC14C */ __I uint32_t GHWPARAMS4; /**< Global Hardware Parameters 4, offset: 0xC150 */ __I uint32_t GHWPARAMS5; /**< Global Hardware Parameters 5, offset: 0xC154 */ __I uint32_t GHWPARAMS6; /**< Global Hardware Parameters 6, offset: 0xC158 */ __I uint32_t GHWPARAMS7; /**< Global Hardware Parameters 7, offset: 0xC15C */ uint8_t RESERVED_11[32]; __IO uint32_t GPRTBIMAP_HSLO; /**< Global High-Speed Port to Bus Instance Mapping - Low, offset: 0xC180 */ uint8_t RESERVED_12[4]; __IO uint32_t GPRTBIMAP_FSLO; /**< Global Full-Speed Port to Bus Instance Mapping - Low, offset: 0xC188 */ uint8_t RESERVED_13[8]; uint32_t GERRINJCTL[2]; /**< Global Error Injection 1 Control..Global Error Injection 2 Control, array offset: 0xC194, array step: 0x4 */ __IO uint32_t GUCTL2; /**< Global User Control 2, offset: 0xC19C */ uint8_t RESERVED_14[96]; __IO uint32_t GUSB2PHYCFG; /**< Global USB2 PHY Configuration, offset: 0xC200 */ uint8_t RESERVED_15[188]; __IO uint32_t GUSB3PIPECTL; /**< Global USB 3.0 PIPE Control, offset: 0xC2C0 */ uint8_t RESERVED_16[60]; __IO uint32_t GTXFIFOSIZ[8]; /**< Global Transmit FIFO Size, array offset: 0xC300, array step: 0x4 */ uint8_t RESERVED_17[96]; __IO uint32_t GRXFIFOSIZ[3]; /**< Global Receive FIFO Size, array offset: 0xC380, array step: 0x4 */ uint8_t RESERVED_18[116]; __IO uint32_t GEVNTADRLO; /**< Global Event Buffer Address Low, offset: 0xC400 */ __IO uint32_t GEVNTADRHI; /**< Global Event Buffer Address High, offset: 0xC404 */ __IO uint32_t GEVNTSIZ; /**< Global Event Buffer Size, offset: 0xC408 */ __IO uint32_t GEVNTCOUNT; /**< Global Event Buffer Count, offset: 0xC40C */ uint8_t RESERVED_19[496]; __I uint32_t GHWPARAMS8; /**< Global Hardware Parameters 8, offset: 0xC600 */ uint8_t RESERVED_20[8]; __IO uint32_t GUCTL3; /**< Global User Control 3, offset: 0xC60C */ __IO uint32_t GTXFIFOPRIDEV; /**< Global Device TX FIFO DMA Priority, offset: 0xC610 */ uint8_t RESERVED_21[4]; __IO uint32_t GTXFIFOPRIHST; /**< Global Host TX FIFO DMA Priority, offset: 0xC618 */ __IO uint32_t GRXFIFOPRIHST; /**< Global Host RX FIFO DMA Priority, offset: 0xC61C */ __IO uint32_t GFIFOPRIDBC; /**< Global Host Debug Capability DMA Priority, offset: 0xC620 */ __IO uint32_t GDMAHLRATIO; /**< Global Host FIFO DMA High-Low Priority Ratio, offset: 0xC624 */ uint8_t RESERVED_22[8]; __IO uint32_t GFLADJ; /**< Global Frame Length Adjustment, offset: 0xC630 */ uint8_t RESERVED_23[12]; __IO uint32_t GUSB2RHBCTL; /**< Global USB 2.0 Root Hub Control, offset: 0xC640 */ uint8_t RESERVED_24[188]; __IO uint32_t DCFG; /**< Device Configuration, offset: 0xC700 */ __IO uint32_t DCTL; /**< Device Control 0, offset: 0xC704 */ __IO uint32_t DEVTEN; /**< Device Event Enable, offset: 0xC708 */ __I uint32_t DSTS; /**< Device Status, offset: 0xC70C */ __IO uint32_t DGCMDPAR; /**< Device Generic Command Parameter, offset: 0xC710 */ __IO uint32_t DGCMD; /**< Device Generic Command, offset: 0xC714 */ uint8_t RESERVED_25[8]; __IO uint32_t DALEPENA; /**< Device Active USB Endpoint Enable, offset: 0xC720 */ uint8_t RESERVED_26[220]; __IO uint32_t DEPCMDPAR20; /**< Device Physical Endpoint-0 Command Parameter 2, offset: 0xC800 */ __IO uint32_t DEPCMDPAR10; /**< Device Physical Endpoint-0 Command Parameter 1, offset: 0xC804 */ __IO uint32_t DEPCMDPAR00; /**< Device Physical Endpoint-0 Command Parameter 0, offset: 0xC808 */ __IO uint32_t DEPCMD0; /**< Device Physical Endpoint-0 Command, offset: 0xC80C */ __IO uint32_t DEPCMDPAR21; /**< Device Physical Endpoint-1 Command Parameter 2, offset: 0xC810 */ __IO uint32_t DEPCMDPAR11; /**< Device Physical Endpoint-1 Command Parameter 1, offset: 0xC814 */ __IO uint32_t DEPCMDPAR01; /**< Device Physical Endpoint-1 Command Parameter 0, offset: 0xC818 */ __IO uint32_t DEPCMD1; /**< Device Physical Endpoint-1 Command, offset: 0xC81C */ __IO uint32_t DEPCMDPAR22; /**< Device Physical Endpoint-2 Command Parameter 2, offset: 0xC820 */ __IO uint32_t DEPCMDPAR12; /**< Device Physical Endpoint-2 Command Parameter 1, offset: 0xC824 */ __IO uint32_t DEPCMDPAR02; /**< Device Physical Endpoint-2 Command Parameter 0, offset: 0xC828 */ __IO uint32_t DEPCMD2; /**< Device Physical Endpoint-2 Command, offset: 0xC82C */ __IO uint32_t DEPCMDPAR23; /**< Device Physical Endpoint-3 Command Parameter 2, offset: 0xC830 */ __IO uint32_t DEPCMDPAR13; /**< Device Physical Endpoint-3 Command Parameter 1, offset: 0xC834 */ __IO uint32_t DEPCMDPAR03; /**< Device Physical Endpoint-3 Command Parameter 0, offset: 0xC838 */ __IO uint32_t DEPCMD3; /**< Device Physical Endpoint-3 Command, offset: 0xC83C */ __IO uint32_t DEPCMDPAR24; /**< Device Physical Endpoint-4 Command Parameter 2, offset: 0xC840 */ __IO uint32_t DEPCMDPAR14; /**< Device Physical Endpoint-4 Command Parameter 1, offset: 0xC844 */ __IO uint32_t DEPCMDPAR04; /**< Device Physical Endpoint-4 Command Parameter 0, offset: 0xC848 */ __IO uint32_t DEPCMD4; /**< Device Physical Endpoint-4 Command, offset: 0xC84C */ __IO uint32_t DEPCMDPAR25; /**< Device Physical Endpoint-5 Command Parameter 2, offset: 0xC850 */ __IO uint32_t DEPCMDPAR15; /**< Device Physical Endpoint-5 Command Parameter 1, offset: 0xC854 */ __IO uint32_t DEPCMDPAR05; /**< Device Physical Endpoint-5 Command Parameter 0, offset: 0xC858 */ __IO uint32_t DEPCMD5; /**< Device Physical Endpoint-5 Command, offset: 0xC85C */ __IO uint32_t DEPCMDPAR26; /**< Device Physical Endpoint-6 Command Parameter 2, offset: 0xC860 */ __IO uint32_t DEPCMDPAR16; /**< Device Physical Endpoint-6 Command Parameter 1, offset: 0xC864 */ __IO uint32_t DEPCMDPAR06; /**< Device Physical Endpoint-6 Command Parameter 0, offset: 0xC868 */ __IO uint32_t DEPCMD6; /**< Device Physical Endpoint-6 Command, offset: 0xC86C */ __IO uint32_t DEPCMDPAR27; /**< Device Physical Endpoint-7 Command Parameter 2, offset: 0xC870 */ __IO uint32_t DEPCMDPAR17; /**< Device Physical Endpoint-7 Command Parameter 1, offset: 0xC874 */ __IO uint32_t DEPCMDPAR07; /**< Device Physical Endpoint-7 Command Parameter 0, offset: 0xC878 */ __IO uint32_t DEPCMD7; /**< Device Physical Endpoint-7 Command, offset: 0xC87C */ __IO uint32_t DEPCMDPAR28; /**< Device Physical Endpoint-8 Command Parameter 2, offset: 0xC880 */ __IO uint32_t DEPCMDPAR18; /**< Device Physical Endpoint-8 Command Parameter 1, offset: 0xC884 */ __IO uint32_t DEPCMDPAR08; /**< Device Physical Endpoint-8 Command Parameter 0, offset: 0xC888 */ __IO uint32_t DEPCMD8; /**< Device Physical Endpoint-8 Command, offset: 0xC88C */ __IO uint32_t DEPCMDPAR29; /**< Device Physical Endpoint-9 Command Parameter 2, offset: 0xC890 */ __IO uint32_t DEPCMDPAR19; /**< Device Physical Endpoint-9 Command Parameter 1, offset: 0xC894 */ __IO uint32_t DEPCMDPAR09; /**< Device Physical Endpoint-9 Command Parameter 0, offset: 0xC898 */ __IO uint32_t DEPCMD9; /**< Device Physical Endpoint-9 Command, offset: 0xC89C */ __IO uint32_t DEPCMDPAR210; /**< Device Physical Endpoint-10 Command Parameter 2, offset: 0xC8A0 */ __IO uint32_t DEPCMDPAR110; /**< Device Physical Endpoint-10 Command Parameter 1, offset: 0xC8A4 */ __IO uint32_t DEPCMDPAR010; /**< Device Physical Endpoint-10 Command Parameter 0, offset: 0xC8A8 */ __IO uint32_t DEPCMD10; /**< Device Physical Endpoint-10 Command, offset: 0xC8AC */ __IO uint32_t DEPCMDPAR211; /**< Device Physical Endpoint-11 Command Parameter 2, offset: 0xC8B0 */ __IO uint32_t DEPCMDPAR111; /**< Device Physical Endpoint-11 Command Parameter 1, offset: 0xC8B4 */ __IO uint32_t DEPCMDPAR011; /**< Device Physical Endpoint-11 Command Parameter 0, offset: 0xC8B8 */ __IO uint32_t DEPCMD11; /**< Device Physical Endpoint-11 Command, offset: 0xC8BC */ __IO uint32_t DEPCMDPAR212; /**< Device Physical Endpoint-12 Command Parameter 2, offset: 0xC8C0 */ __IO uint32_t DEPCMDPAR112; /**< Device Physical Endpoint-12 Command Parameter 1, offset: 0xC8C4 */ __IO uint32_t DEPCMDPAR012; /**< Device Physical Endpoint-12 Command Parameter 0, offset: 0xC8C8 */ __IO uint32_t DEPCMD12; /**< Device Physical Endpoint-12 Command, offset: 0xC8CC */ __IO uint32_t DEPCMDPAR213; /**< Device Physical Endpoint-13 Command Parameter 2, offset: 0xC8D0 */ __IO uint32_t DEPCMDPAR113; /**< Device Physical Endpoint-13 Command Parameter 1, offset: 0xC8D4 */ __IO uint32_t DEPCMDPAR013; /**< Device Physical Endpoint-13 Command Parameter 0, offset: 0xC8D8 */ __IO uint32_t DEPCMD13; /**< Device Physical Endpoint-13 Command, offset: 0xC8DC */ __IO uint32_t DEPCMDPAR214; /**< Device Physical Endpoint-14 Command Parameter 2, offset: 0xC8E0 */ __IO uint32_t DEPCMDPAR114; /**< Device Physical Endpoint-14 Command Parameter 1, offset: 0xC8E4 */ __IO uint32_t DEPCMDPAR014; /**< Device Physical Endpoint-14 Command Parameter 0, offset: 0xC8E8 */ __IO uint32_t DEPCMD14; /**< Device Physical Endpoint-14 Command, offset: 0xC8EC */ __IO uint32_t DEPCMDPAR215; /**< Device Physical Endpoint-15 Command Parameter 2, offset: 0xC8F0 */ __IO uint32_t DEPCMDPAR115; /**< Device Physical Endpoint-15 Command Parameter 1, offset: 0xC8F4 */ __IO uint32_t DEPCMDPAR015; /**< Device Physical Endpoint-15 Command Parameter 0, offset: 0xC8F8 */ __IO uint32_t DEPCMD15; /**< Device Physical Endpoint-15 Command, offset: 0xC8FC */ uint8_t RESERVED_27[256]; __IO uint32_t DEV_IMOD; /**< Device Interrupt Moderation, offset: 0xCA00 */ uint8_t RESERVED_28[556]; __IO uint32_t BCFG; /**< BC Configuration, offset: 0xCC30 */ uint8_t RESERVED_29[4]; __IO uint32_t BCEVT; /**< BC Event, offset: 0xCC38 */ __IO uint32_t BCEVTEN; /**< BC Event Enable, offset: 0xCC3C */ uint8_t RESERVED_30[960]; __IO uint32_t LU1LFPSRXTIM0; /**< U1/U2 LFPS RX Timer, offset: 0xD000 */ uint8_t RESERVED_31[28]; __IO uint32_t LINK_SETTINGS0; /**< Link Setting, offset: 0xD020 */ __IO uint32_t LLUCTL0; /**< Link User Control, offset: 0xD024 */ __IO uint32_t LPTMDPDELAY0; /**< Link Datapath Delay, offset: 0xD028 */ uint8_t RESERVED_32[2004]; __IO uint32_t BU3RHBDBG; /**< U3 Root Hub Debug, offset: 0xD800 */ uint8_t RESERVED_33[76]; __I uint32_t BRSERRCNT; /**< Block RAM Single Bit Error Count, offset: 0xD850 */ __I uint32_t BRMERRCNT; /**< Block RAM Multiple Bit Error Count, offset: 0xD854 */ __I uint32_t BRMECCERR; /**< Block RAM ECC Error Vector, offset: 0xD858 */ __IO uint32_t BRERRCTL; /**< Block RAM ECC Error Control, offset: 0xD85C */ __I uint32_t BRAMADDRERR[3]; /**< Block RAM0 Address Error..Block RAM2 Address Error, array offset: 0xD860, array step: 0x4 */ } USB3_CORE_Type; /* ---------------------------------------------------------------------------- -- USB3_CORE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_CORE_Register_Masks USB3_CORE Register Masks * @{ */ /*! @name CAPLENGTH - Capability Registers Length and Host Controller Operational Registers */ /*! @{ */ #define USB3_CORE_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB3_CORE_CAPLENGTH_CAPLENGTH_SHIFT (0U) /*! CAPLENGTH - Capability Registers Length */ #define USB3_CORE_CAPLENGTH_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CAPLENGTH_CAPLENGTH_SHIFT)) & USB3_CORE_CAPLENGTH_CAPLENGTH_MASK) #define USB3_CORE_CAPLENGTH_HCIVERSION_MASK (0xFFFF0000U) #define USB3_CORE_CAPLENGTH_HCIVERSION_SHIFT (16U) /*! HCIVERSION - Host Controller Interface Version Number */ #define USB3_CORE_CAPLENGTH_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CAPLENGTH_HCIVERSION_SHIFT)) & USB3_CORE_CAPLENGTH_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS1 - Structural Parameters 1 */ /*! @{ */ #define USB3_CORE_HCSPARAMS1_MAXSLOTS_MASK (0xFFU) #define USB3_CORE_HCSPARAMS1_MAXSLOTS_SHIFT (0U) /*! MAXSLOTS - Number of Device Slots */ #define USB3_CORE_HCSPARAMS1_MAXSLOTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS1_MAXSLOTS_SHIFT)) & USB3_CORE_HCSPARAMS1_MAXSLOTS_MASK) #define USB3_CORE_HCSPARAMS1_MAXINTRS_MASK (0x7FF00U) #define USB3_CORE_HCSPARAMS1_MAXINTRS_SHIFT (8U) /*! MAXINTRS - Number of Interrupters */ #define USB3_CORE_HCSPARAMS1_MAXINTRS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS1_MAXINTRS_SHIFT)) & USB3_CORE_HCSPARAMS1_MAXINTRS_MASK) #define USB3_CORE_HCSPARAMS1_MAXPORTS_MASK (0xFF000000U) #define USB3_CORE_HCSPARAMS1_MAXPORTS_SHIFT (24U) /*! MAXPORTS - Number of Ports */ #define USB3_CORE_HCSPARAMS1_MAXPORTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS1_MAXPORTS_SHIFT)) & USB3_CORE_HCSPARAMS1_MAXPORTS_MASK) /*! @} */ /*! @name HCSPARAMS2 - Structural Parameters 2 */ /*! @{ */ #define USB3_CORE_HCSPARAMS2_IST_MASK (0xFU) #define USB3_CORE_HCSPARAMS2_IST_SHIFT (0U) #define USB3_CORE_HCSPARAMS2_IST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS2_IST_SHIFT)) & USB3_CORE_HCSPARAMS2_IST_MASK) #define USB3_CORE_HCSPARAMS2_ERSTMAX_MASK (0xF0U) #define USB3_CORE_HCSPARAMS2_ERSTMAX_SHIFT (4U) #define USB3_CORE_HCSPARAMS2_ERSTMAX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS2_ERSTMAX_SHIFT)) & USB3_CORE_HCSPARAMS2_ERSTMAX_MASK) #define USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_MASK (0x3E00000U) #define USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_SHIFT (21U) /*! MAXSCRATCHPADBUFS_HI - Max Scratchpad Bufs High */ #define USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_HI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_SHIFT)) & USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_MASK) #define USB3_CORE_HCSPARAMS2_SPR_MASK (0x4000000U) #define USB3_CORE_HCSPARAMS2_SPR_SHIFT (26U) #define USB3_CORE_HCSPARAMS2_SPR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS2_SPR_SHIFT)) & USB3_CORE_HCSPARAMS2_SPR_MASK) #define USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_MASK (0xF8000000U) #define USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_SHIFT (27U) /*! MAXSCRATCHPADBUFS - Max Scratchpad Bufs Low */ #define USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_SHIFT)) & USB3_CORE_HCSPARAMS2_MAXSCRATCHPADBUFS_MASK) /*! @} */ /*! @name HCSPARAMS3 - Structural Parameters 3 */ /*! @{ */ #define USB3_CORE_HCSPARAMS3_U1_DEVICE_EXIT_LAT_MASK (0xFFU) #define USB3_CORE_HCSPARAMS3_U1_DEVICE_EXIT_LAT_SHIFT (0U) /*! U1_DEVICE_EXIT_LAT - U1 Device Exit Latency */ #define USB3_CORE_HCSPARAMS3_U1_DEVICE_EXIT_LAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS3_U1_DEVICE_EXIT_LAT_SHIFT)) & USB3_CORE_HCSPARAMS3_U1_DEVICE_EXIT_LAT_MASK) #define USB3_CORE_HCSPARAMS3_U2_DEVICE_EXIT_LAT_MASK (0xFFFF0000U) #define USB3_CORE_HCSPARAMS3_U2_DEVICE_EXIT_LAT_SHIFT (16U) /*! U2_DEVICE_EXIT_LAT - U2 Device Exit Latency */ #define USB3_CORE_HCSPARAMS3_U2_DEVICE_EXIT_LAT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCSPARAMS3_U2_DEVICE_EXIT_LAT_SHIFT)) & USB3_CORE_HCSPARAMS3_U2_DEVICE_EXIT_LAT_MASK) /*! @} */ /*! @name HCCPARAMS1 - Host Controller Capability Parameters 1 */ /*! @{ */ #define USB3_CORE_HCCPARAMS1_AC64_MASK (0x1U) #define USB3_CORE_HCCPARAMS1_AC64_SHIFT (0U) /*! AC64 - 64-bit Addressing Capability */ #define USB3_CORE_HCCPARAMS1_AC64(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_AC64_SHIFT)) & USB3_CORE_HCCPARAMS1_AC64_MASK) #define USB3_CORE_HCCPARAMS1_BNC_MASK (0x2U) #define USB3_CORE_HCCPARAMS1_BNC_SHIFT (1U) /*! BNC - BW Negotiation Capability */ #define USB3_CORE_HCCPARAMS1_BNC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_BNC_SHIFT)) & USB3_CORE_HCCPARAMS1_BNC_MASK) #define USB3_CORE_HCCPARAMS1_CSZ_MASK (0x4U) #define USB3_CORE_HCCPARAMS1_CSZ_SHIFT (2U) /*! CSZ - Context Size */ #define USB3_CORE_HCCPARAMS1_CSZ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_CSZ_SHIFT)) & USB3_CORE_HCCPARAMS1_CSZ_MASK) #define USB3_CORE_HCCPARAMS1_PPC_MASK (0x8U) #define USB3_CORE_HCCPARAMS1_PPC_SHIFT (3U) /*! PPC - Port Power Control */ #define USB3_CORE_HCCPARAMS1_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_PPC_SHIFT)) & USB3_CORE_HCCPARAMS1_PPC_MASK) #define USB3_CORE_HCCPARAMS1_PIND_MASK (0x10U) #define USB3_CORE_HCCPARAMS1_PIND_SHIFT (4U) /*! PIND - Port Indicators */ #define USB3_CORE_HCCPARAMS1_PIND(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_PIND_SHIFT)) & USB3_CORE_HCCPARAMS1_PIND_MASK) #define USB3_CORE_HCCPARAMS1_LHRC_MASK (0x20U) #define USB3_CORE_HCCPARAMS1_LHRC_SHIFT (5U) /*! LHRC - Light HC Reset Capability */ #define USB3_CORE_HCCPARAMS1_LHRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_LHRC_SHIFT)) & USB3_CORE_HCCPARAMS1_LHRC_MASK) #define USB3_CORE_HCCPARAMS1_LTC_MASK (0x40U) #define USB3_CORE_HCCPARAMS1_LTC_SHIFT (6U) /*! LTC - Latency Tolerance Messaging Capability */ #define USB3_CORE_HCCPARAMS1_LTC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_LTC_SHIFT)) & USB3_CORE_HCCPARAMS1_LTC_MASK) #define USB3_CORE_HCCPARAMS1_NSS_MASK (0x80U) #define USB3_CORE_HCCPARAMS1_NSS_SHIFT (7U) /*! NSS - No Secondary SID Support */ #define USB3_CORE_HCCPARAMS1_NSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_NSS_SHIFT)) & USB3_CORE_HCCPARAMS1_NSS_MASK) #define USB3_CORE_HCCPARAMS1_PAE_MASK (0x100U) #define USB3_CORE_HCCPARAMS1_PAE_SHIFT (8U) /*! PAE - Parse All Event Data */ #define USB3_CORE_HCCPARAMS1_PAE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_PAE_SHIFT)) & USB3_CORE_HCCPARAMS1_PAE_MASK) #define USB3_CORE_HCCPARAMS1_SPC_MASK (0x200U) #define USB3_CORE_HCCPARAMS1_SPC_SHIFT (9U) /*! SPC - Short Packet Capability */ #define USB3_CORE_HCCPARAMS1_SPC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_SPC_SHIFT)) & USB3_CORE_HCCPARAMS1_SPC_MASK) #define USB3_CORE_HCCPARAMS1_SEC_MASK (0x400U) #define USB3_CORE_HCCPARAMS1_SEC_SHIFT (10U) /*! SEC - Stopped EDLTA Capability */ #define USB3_CORE_HCCPARAMS1_SEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_SEC_SHIFT)) & USB3_CORE_HCCPARAMS1_SEC_MASK) #define USB3_CORE_HCCPARAMS1_CFC_MASK (0x800U) #define USB3_CORE_HCCPARAMS1_CFC_SHIFT (11U) /*! CFC - Contiguous Frame ID Capability */ #define USB3_CORE_HCCPARAMS1_CFC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_CFC_SHIFT)) & USB3_CORE_HCCPARAMS1_CFC_MASK) #define USB3_CORE_HCCPARAMS1_MAXPSASIZE_MASK (0xF000U) #define USB3_CORE_HCCPARAMS1_MAXPSASIZE_SHIFT (12U) /*! MAXPSASIZE - Maximum Primary Stream Array Size */ #define USB3_CORE_HCCPARAMS1_MAXPSASIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_MAXPSASIZE_SHIFT)) & USB3_CORE_HCCPARAMS1_MAXPSASIZE_MASK) #define USB3_CORE_HCCPARAMS1_XECP_MASK (0xFFFF0000U) #define USB3_CORE_HCCPARAMS1_XECP_SHIFT (16U) /*! XECP - xHCI Extended Capabilities Pointer */ #define USB3_CORE_HCCPARAMS1_XECP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS1_XECP_SHIFT)) & USB3_CORE_HCCPARAMS1_XECP_MASK) /*! @} */ /*! @name DBOFF - Doorbell Offset */ /*! @{ */ #define USB3_CORE_DBOFF_DOORBELL_ARRAY_OFFSET_MASK (0xFFFFFFFCU) #define USB3_CORE_DBOFF_DOORBELL_ARRAY_OFFSET_SHIFT (2U) /*! DOORBELL_ARRAY_OFFSET - Doorbell Array Offset */ #define USB3_CORE_DBOFF_DOORBELL_ARRAY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DBOFF_DOORBELL_ARRAY_OFFSET_SHIFT)) & USB3_CORE_DBOFF_DOORBELL_ARRAY_OFFSET_MASK) /*! @} */ /*! @name RTSOFF - Runtime Register Space Offset */ /*! @{ */ #define USB3_CORE_RTSOFF_RUNTIME_REG_SPACE_OFFSET_MASK (0xFFFFFFE0U) #define USB3_CORE_RTSOFF_RUNTIME_REG_SPACE_OFFSET_SHIFT (5U) /*! RUNTIME_REG_SPACE_OFFSET - Runtime Register Space Offset */ #define USB3_CORE_RTSOFF_RUNTIME_REG_SPACE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_RTSOFF_RUNTIME_REG_SPACE_OFFSET_SHIFT)) & USB3_CORE_RTSOFF_RUNTIME_REG_SPACE_OFFSET_MASK) /*! @} */ /*! @name HCCPARAMS2 - Host Controller Capability Parameters 2 */ /*! @{ */ #define USB3_CORE_HCCPARAMS2_U3C_MASK (0x1U) #define USB3_CORE_HCCPARAMS2_U3C_SHIFT (0U) /*! U3C - U3 Entry Capability */ #define USB3_CORE_HCCPARAMS2_U3C(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS2_U3C_SHIFT)) & USB3_CORE_HCCPARAMS2_U3C_MASK) #define USB3_CORE_HCCPARAMS2_CMC_MASK (0x2U) #define USB3_CORE_HCCPARAMS2_CMC_SHIFT (1U) /*! CMC - Configure Endpoint Command Max Exit Latency Too Large Capability */ #define USB3_CORE_HCCPARAMS2_CMC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS2_CMC_SHIFT)) & USB3_CORE_HCCPARAMS2_CMC_MASK) #define USB3_CORE_HCCPARAMS2_FSC_MASK (0x4U) #define USB3_CORE_HCCPARAMS2_FSC_SHIFT (2U) /*! FSC - Force Save Context Capability */ #define USB3_CORE_HCCPARAMS2_FSC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS2_FSC_SHIFT)) & USB3_CORE_HCCPARAMS2_FSC_MASK) #define USB3_CORE_HCCPARAMS2_CTC_MASK (0x8U) #define USB3_CORE_HCCPARAMS2_CTC_SHIFT (3U) /*! CTC - Compliance Transition Capability */ #define USB3_CORE_HCCPARAMS2_CTC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS2_CTC_SHIFT)) & USB3_CORE_HCCPARAMS2_CTC_MASK) #define USB3_CORE_HCCPARAMS2_LEC_MASK (0x10U) #define USB3_CORE_HCCPARAMS2_LEC_SHIFT (4U) /*! LEC - Large ESIT Payload Capability */ #define USB3_CORE_HCCPARAMS2_LEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS2_LEC_SHIFT)) & USB3_CORE_HCCPARAMS2_LEC_MASK) #define USB3_CORE_HCCPARAMS2_CIC_MASK (0x20U) #define USB3_CORE_HCCPARAMS2_CIC_SHIFT (5U) /*! CIC - Configuration Information Capability */ #define USB3_CORE_HCCPARAMS2_CIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_HCCPARAMS2_CIC_SHIFT)) & USB3_CORE_HCCPARAMS2_CIC_MASK) /*! @} */ /*! @name USBCMD - USB Command */ /*! @{ */ #define USB3_CORE_USBCMD_R_S_MASK (0x1U) #define USB3_CORE_USBCMD_R_S_SHIFT (0U) /*! R_S - Run/Stop */ #define USB3_CORE_USBCMD_R_S(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_R_S_SHIFT)) & USB3_CORE_USBCMD_R_S_MASK) #define USB3_CORE_USBCMD_HCRST_MASK (0x2U) #define USB3_CORE_USBCMD_HCRST_SHIFT (1U) /*! HCRST - Host Controller Reset */ #define USB3_CORE_USBCMD_HCRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_HCRST_SHIFT)) & USB3_CORE_USBCMD_HCRST_MASK) #define USB3_CORE_USBCMD_INTE_MASK (0x4U) #define USB3_CORE_USBCMD_INTE_SHIFT (2U) /*! INTE - Interrupter Enable */ #define USB3_CORE_USBCMD_INTE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_INTE_SHIFT)) & USB3_CORE_USBCMD_INTE_MASK) #define USB3_CORE_USBCMD_HSEE_MASK (0x8U) #define USB3_CORE_USBCMD_HSEE_SHIFT (3U) /*! HSEE - Host System Error Enable */ #define USB3_CORE_USBCMD_HSEE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_HSEE_SHIFT)) & USB3_CORE_USBCMD_HSEE_MASK) #define USB3_CORE_USBCMD_LHCRST_MASK (0x80U) #define USB3_CORE_USBCMD_LHCRST_SHIFT (7U) /*! LHCRST - Light Host Controller Reset */ #define USB3_CORE_USBCMD_LHCRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_LHCRST_SHIFT)) & USB3_CORE_USBCMD_LHCRST_MASK) #define USB3_CORE_USBCMD_CSS_MASK (0x100U) #define USB3_CORE_USBCMD_CSS_SHIFT (8U) /*! CSS - Controller Save State */ #define USB3_CORE_USBCMD_CSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_CSS_SHIFT)) & USB3_CORE_USBCMD_CSS_MASK) #define USB3_CORE_USBCMD_CRS_MASK (0x200U) #define USB3_CORE_USBCMD_CRS_SHIFT (9U) /*! CRS - Controller Restore State */ #define USB3_CORE_USBCMD_CRS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_CRS_SHIFT)) & USB3_CORE_USBCMD_CRS_MASK) #define USB3_CORE_USBCMD_EWE_MASK (0x400U) #define USB3_CORE_USBCMD_EWE_SHIFT (10U) /*! EWE - Enable Wrap Event */ #define USB3_CORE_USBCMD_EWE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_EWE_SHIFT)) & USB3_CORE_USBCMD_EWE_MASK) #define USB3_CORE_USBCMD_EU3S_MASK (0x800U) #define USB3_CORE_USBCMD_EU3S_SHIFT (11U) /*! EU3S - Enable U3 MFINDEX Stop */ #define USB3_CORE_USBCMD_EU3S(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_EU3S_SHIFT)) & USB3_CORE_USBCMD_EU3S_MASK) #define USB3_CORE_USBCMD_CME_MASK (0x2000U) #define USB3_CORE_USBCMD_CME_SHIFT (13U) /*! CME - CEM Enable */ #define USB3_CORE_USBCMD_CME(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBCMD_CME_SHIFT)) & USB3_CORE_USBCMD_CME_MASK) /*! @} */ /*! @name USBSTS - USB Status */ /*! @{ */ #define USB3_CORE_USBSTS_HCH_MASK (0x1U) #define USB3_CORE_USBSTS_HCH_SHIFT (0U) /*! HCH - HC Halted */ #define USB3_CORE_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_HCH_SHIFT)) & USB3_CORE_USBSTS_HCH_MASK) #define USB3_CORE_USBSTS_HSE_MASK (0x4U) #define USB3_CORE_USBSTS_HSE_SHIFT (2U) /*! HSE - Host System Error */ #define USB3_CORE_USBSTS_HSE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_HSE_SHIFT)) & USB3_CORE_USBSTS_HSE_MASK) #define USB3_CORE_USBSTS_EINT_MASK (0x8U) #define USB3_CORE_USBSTS_EINT_SHIFT (3U) /*! EINT - Event Interrupt */ #define USB3_CORE_USBSTS_EINT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_EINT_SHIFT)) & USB3_CORE_USBSTS_EINT_MASK) #define USB3_CORE_USBSTS_PCD_MASK (0x10U) #define USB3_CORE_USBSTS_PCD_SHIFT (4U) /*! PCD - Port Change Detect */ #define USB3_CORE_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_PCD_SHIFT)) & USB3_CORE_USBSTS_PCD_MASK) #define USB3_CORE_USBSTS_SSS_MASK (0x100U) #define USB3_CORE_USBSTS_SSS_SHIFT (8U) /*! SSS - Save State Status */ #define USB3_CORE_USBSTS_SSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_SSS_SHIFT)) & USB3_CORE_USBSTS_SSS_MASK) #define USB3_CORE_USBSTS_RSS_MASK (0x200U) #define USB3_CORE_USBSTS_RSS_SHIFT (9U) /*! RSS - Restore State Status */ #define USB3_CORE_USBSTS_RSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_RSS_SHIFT)) & USB3_CORE_USBSTS_RSS_MASK) #define USB3_CORE_USBSTS_SRE_MASK (0x400U) #define USB3_CORE_USBSTS_SRE_SHIFT (10U) /*! SRE - Save/Restore Error */ #define USB3_CORE_USBSTS_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_SRE_SHIFT)) & USB3_CORE_USBSTS_SRE_MASK) #define USB3_CORE_USBSTS_CNR_MASK (0x800U) #define USB3_CORE_USBSTS_CNR_SHIFT (11U) /*! CNR - Controller Not Ready * 0b0..Ready * 0b1..Not ready */ #define USB3_CORE_USBSTS_CNR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_CNR_SHIFT)) & USB3_CORE_USBSTS_CNR_MASK) #define USB3_CORE_USBSTS_HCE_MASK (0x1000U) #define USB3_CORE_USBSTS_HCE_SHIFT (12U) /*! HCE - Host Controller Error * 0b0..No internal xHC error conditions exist * 0b1..Internal xHC error condition */ #define USB3_CORE_USBSTS_HCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBSTS_HCE_SHIFT)) & USB3_CORE_USBSTS_HCE_MASK) /*! @} */ /*! @name PAGESIZE - Page Size */ /*! @{ */ #define USB3_CORE_PAGESIZE_PAGE_SIZE_MASK (0xFFFFU) #define USB3_CORE_PAGESIZE_PAGE_SIZE_SHIFT (0U) /*! PAGE_SIZE - Page Size */ #define USB3_CORE_PAGESIZE_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PAGESIZE_PAGE_SIZE_SHIFT)) & USB3_CORE_PAGESIZE_PAGE_SIZE_MASK) /*! @} */ /*! @name DNCTRL - Device Notification */ /*! @{ */ #define USB3_CORE_DNCTRL_N0_N15_MASK (0xFFFFU) #define USB3_CORE_DNCTRL_N0_N15_SHIFT (0U) /*! N0_N15 - Notification Enable */ #define USB3_CORE_DNCTRL_N0_N15(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DNCTRL_N0_N15_SHIFT)) & USB3_CORE_DNCTRL_N0_N15_MASK) /*! @} */ /*! @name CRCR_LO - Command Ring Control - Low */ /*! @{ */ #define USB3_CORE_CRCR_LO_RCS_MASK (0x1U) #define USB3_CORE_CRCR_LO_RCS_SHIFT (0U) /*! RCS - Ring Cycle State */ #define USB3_CORE_CRCR_LO_RCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CRCR_LO_RCS_SHIFT)) & USB3_CORE_CRCR_LO_RCS_MASK) #define USB3_CORE_CRCR_LO_CS_MASK (0x2U) #define USB3_CORE_CRCR_LO_CS_SHIFT (1U) /*! CS - Command Stop */ #define USB3_CORE_CRCR_LO_CS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CRCR_LO_CS_SHIFT)) & USB3_CORE_CRCR_LO_CS_MASK) #define USB3_CORE_CRCR_LO_CA_MASK (0x4U) #define USB3_CORE_CRCR_LO_CA_SHIFT (2U) /*! CA - Command Abort */ #define USB3_CORE_CRCR_LO_CA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CRCR_LO_CA_SHIFT)) & USB3_CORE_CRCR_LO_CA_MASK) #define USB3_CORE_CRCR_LO_CRR_MASK (0x8U) #define USB3_CORE_CRCR_LO_CRR_SHIFT (3U) /*! CRR - Command Ring Running */ #define USB3_CORE_CRCR_LO_CRR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CRCR_LO_CRR_SHIFT)) & USB3_CORE_CRCR_LO_CRR_MASK) #define USB3_CORE_CRCR_LO_CMD_RING_PNTR_MASK (0xFFFFFFC0U) #define USB3_CORE_CRCR_LO_CMD_RING_PNTR_SHIFT (6U) /*! CMD_RING_PNTR - Command Ring Pointer */ #define USB3_CORE_CRCR_LO_CMD_RING_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CRCR_LO_CMD_RING_PNTR_SHIFT)) & USB3_CORE_CRCR_LO_CMD_RING_PNTR_MASK) /*! @} */ /*! @name CRCR_HI - Command Ring Control - High */ /*! @{ */ #define USB3_CORE_CRCR_HI_CMD_RING_PNTR_MASK (0xFFFF0000U) #define USB3_CORE_CRCR_HI_CMD_RING_PNTR_SHIFT (16U) /*! CMD_RING_PNTR - Command Ring Pointer */ #define USB3_CORE_CRCR_HI_CMD_RING_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CRCR_HI_CMD_RING_PNTR_SHIFT)) & USB3_CORE_CRCR_HI_CMD_RING_PNTR_MASK) /*! @} */ /*! @name DCBAAP_LO - Device Context Base Address Array Pointer - Low */ /*! @{ */ #define USB3_CORE_DCBAAP_LO_DEVICE_CONTEXT_BAAP_MASK (0xFFFFFFC0U) #define USB3_CORE_DCBAAP_LO_DEVICE_CONTEXT_BAAP_SHIFT (6U) /*! DEVICE_CONTEXT_BAAP - Device Context Base Address Array Pointer */ #define USB3_CORE_DCBAAP_LO_DEVICE_CONTEXT_BAAP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCBAAP_LO_DEVICE_CONTEXT_BAAP_SHIFT)) & USB3_CORE_DCBAAP_LO_DEVICE_CONTEXT_BAAP_MASK) /*! @} */ /*! @name DCBAAP_HI - Device Context Base Address Array Pointer -High */ /*! @{ */ #define USB3_CORE_DCBAAP_HI_DEVICE_CONTEXT_BAAP_MASK (0xFFFFFFFFU) #define USB3_CORE_DCBAAP_HI_DEVICE_CONTEXT_BAAP_SHIFT (0U) /*! DEVICE_CONTEXT_BAAP - Device Context Base Address Array Pointer */ #define USB3_CORE_DCBAAP_HI_DEVICE_CONTEXT_BAAP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCBAAP_HI_DEVICE_CONTEXT_BAAP_SHIFT)) & USB3_CORE_DCBAAP_HI_DEVICE_CONTEXT_BAAP_MASK) /*! @} */ /*! @name CONFIG - Configuration */ /*! @{ */ #define USB3_CORE_CONFIG_MAXSLOTSEN_MASK (0xFFU) #define USB3_CORE_CONFIG_MAXSLOTSEN_SHIFT (0U) /*! MAXSLOTSEN - Max Device Slots Enabled */ #define USB3_CORE_CONFIG_MAXSLOTSEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CONFIG_MAXSLOTSEN_SHIFT)) & USB3_CORE_CONFIG_MAXSLOTSEN_MASK) #define USB3_CORE_CONFIG_U3E_MASK (0x100U) #define USB3_CORE_CONFIG_U3E_SHIFT (8U) /*! U3E - U3 Entry Enable */ #define USB3_CORE_CONFIG_U3E(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CONFIG_U3E_SHIFT)) & USB3_CORE_CONFIG_U3E_MASK) #define USB3_CORE_CONFIG_CIE_MASK (0x200U) #define USB3_CORE_CONFIG_CIE_SHIFT (9U) /*! CIE - Configuration Information Enable */ #define USB3_CORE_CONFIG_CIE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_CONFIG_CIE_SHIFT)) & USB3_CORE_CONFIG_CIE_MASK) /*! @} */ /*! @name PORTSC_20 - USB2 Port Status and Control */ /*! @{ */ #define USB3_CORE_PORTSC_20_CCS_MASK (0x1U) #define USB3_CORE_PORTSC_20_CCS_SHIFT (0U) /*! CCS - Current Connect Status */ #define USB3_CORE_PORTSC_20_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_CCS_SHIFT)) & USB3_CORE_PORTSC_20_CCS_MASK) #define USB3_CORE_PORTSC_20_PED_MASK (0x2U) #define USB3_CORE_PORTSC_20_PED_SHIFT (1U) /*! PED - Port Enabled/Disabled */ #define USB3_CORE_PORTSC_20_PED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PED_SHIFT)) & USB3_CORE_PORTSC_20_PED_MASK) #define USB3_CORE_PORTSC_20_OCA_MASK (0x8U) #define USB3_CORE_PORTSC_20_OCA_SHIFT (3U) /*! OCA - Over Current Active */ #define USB3_CORE_PORTSC_20_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_OCA_SHIFT)) & USB3_CORE_PORTSC_20_OCA_MASK) #define USB3_CORE_PORTSC_20_PR_MASK (0x10U) #define USB3_CORE_PORTSC_20_PR_SHIFT (4U) /*! PR - Port Reset */ #define USB3_CORE_PORTSC_20_PR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PR_SHIFT)) & USB3_CORE_PORTSC_20_PR_MASK) #define USB3_CORE_PORTSC_20_PLS_MASK (0x1E0U) #define USB3_CORE_PORTSC_20_PLS_SHIFT (5U) /*! PLS - Port Link State */ #define USB3_CORE_PORTSC_20_PLS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PLS_SHIFT)) & USB3_CORE_PORTSC_20_PLS_MASK) #define USB3_CORE_PORTSC_20_PP_MASK (0x200U) #define USB3_CORE_PORTSC_20_PP_SHIFT (9U) /*! PP - Port Power */ #define USB3_CORE_PORTSC_20_PP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PP_SHIFT)) & USB3_CORE_PORTSC_20_PP_MASK) #define USB3_CORE_PORTSC_20_PORTSPEED_MASK (0x3C00U) #define USB3_CORE_PORTSC_20_PORTSPEED_SHIFT (10U) /*! PORTSPEED - Port Speed */ #define USB3_CORE_PORTSC_20_PORTSPEED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PORTSPEED_SHIFT)) & USB3_CORE_PORTSC_20_PORTSPEED_MASK) #define USB3_CORE_PORTSC_20_PIC_MASK (0xC000U) #define USB3_CORE_PORTSC_20_PIC_SHIFT (14U) /*! PIC - Port Indicator Control */ #define USB3_CORE_PORTSC_20_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PIC_SHIFT)) & USB3_CORE_PORTSC_20_PIC_MASK) #define USB3_CORE_PORTSC_20_LWS_MASK (0x10000U) #define USB3_CORE_PORTSC_20_LWS_SHIFT (16U) /*! LWS - Port Link State Write Strobe */ #define USB3_CORE_PORTSC_20_LWS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_LWS_SHIFT)) & USB3_CORE_PORTSC_20_LWS_MASK) #define USB3_CORE_PORTSC_20_CSC_MASK (0x20000U) #define USB3_CORE_PORTSC_20_CSC_SHIFT (17U) /*! CSC - Connect Status Change */ #define USB3_CORE_PORTSC_20_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_CSC_SHIFT)) & USB3_CORE_PORTSC_20_CSC_MASK) #define USB3_CORE_PORTSC_20_PEC_MASK (0x40000U) #define USB3_CORE_PORTSC_20_PEC_SHIFT (18U) /*! PEC - Port Enabled/Disabled Change */ #define USB3_CORE_PORTSC_20_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PEC_SHIFT)) & USB3_CORE_PORTSC_20_PEC_MASK) #define USB3_CORE_PORTSC_20_OCC_MASK (0x100000U) #define USB3_CORE_PORTSC_20_OCC_SHIFT (20U) /*! OCC - Over Current Change */ #define USB3_CORE_PORTSC_20_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_OCC_SHIFT)) & USB3_CORE_PORTSC_20_OCC_MASK) #define USB3_CORE_PORTSC_20_PRC_MASK (0x200000U) #define USB3_CORE_PORTSC_20_PRC_SHIFT (21U) /*! PRC - Port Reset Change */ #define USB3_CORE_PORTSC_20_PRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PRC_SHIFT)) & USB3_CORE_PORTSC_20_PRC_MASK) #define USB3_CORE_PORTSC_20_PLC_MASK (0x400000U) #define USB3_CORE_PORTSC_20_PLC_SHIFT (22U) /*! PLC - Port Link State Change */ #define USB3_CORE_PORTSC_20_PLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_PLC_SHIFT)) & USB3_CORE_PORTSC_20_PLC_MASK) #define USB3_CORE_PORTSC_20_CAS_MASK (0x1000000U) #define USB3_CORE_PORTSC_20_CAS_SHIFT (24U) /*! CAS - Cold Attach Status */ #define USB3_CORE_PORTSC_20_CAS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_CAS_SHIFT)) & USB3_CORE_PORTSC_20_CAS_MASK) #define USB3_CORE_PORTSC_20_WCE_MASK (0x2000000U) #define USB3_CORE_PORTSC_20_WCE_SHIFT (25U) /*! WCE - Wake on Connect Enable */ #define USB3_CORE_PORTSC_20_WCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_WCE_SHIFT)) & USB3_CORE_PORTSC_20_WCE_MASK) #define USB3_CORE_PORTSC_20_WDE_MASK (0x4000000U) #define USB3_CORE_PORTSC_20_WDE_SHIFT (26U) /*! WDE - Wake on Disconnect Enable */ #define USB3_CORE_PORTSC_20_WDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_WDE_SHIFT)) & USB3_CORE_PORTSC_20_WDE_MASK) #define USB3_CORE_PORTSC_20_WOE_MASK (0x8000000U) #define USB3_CORE_PORTSC_20_WOE_SHIFT (27U) /*! WOE - Wake on Overcurrent Enable */ #define USB3_CORE_PORTSC_20_WOE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_WOE_SHIFT)) & USB3_CORE_PORTSC_20_WOE_MASK) #define USB3_CORE_PORTSC_20_DR_MASK (0x40000000U) #define USB3_CORE_PORTSC_20_DR_SHIFT (30U) /*! DR - Device Removable */ #define USB3_CORE_PORTSC_20_DR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_20_DR_SHIFT)) & USB3_CORE_PORTSC_20_DR_MASK) /*! @} */ /*! @name PORTPMSC_20 - USB2 Port Power Management Status and Control */ /*! @{ */ #define USB3_CORE_PORTPMSC_20_L1S_MASK (0x7U) #define USB3_CORE_PORTPMSC_20_L1S_SHIFT (0U) /*! L1S - L1 Status */ #define USB3_CORE_PORTPMSC_20_L1S(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_20_L1S_SHIFT)) & USB3_CORE_PORTPMSC_20_L1S_MASK) #define USB3_CORE_PORTPMSC_20_RWE_MASK (0x8U) #define USB3_CORE_PORTPMSC_20_RWE_SHIFT (3U) /*! RWE - Remote Wake Enable */ #define USB3_CORE_PORTPMSC_20_RWE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_20_RWE_SHIFT)) & USB3_CORE_PORTPMSC_20_RWE_MASK) #define USB3_CORE_PORTPMSC_20_BESL_MASK (0xF0U) #define USB3_CORE_PORTPMSC_20_BESL_SHIFT (4U) /*! BESL - Best Effort Service Latency */ #define USB3_CORE_PORTPMSC_20_BESL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_20_BESL_SHIFT)) & USB3_CORE_PORTPMSC_20_BESL_MASK) #define USB3_CORE_PORTPMSC_20_L1DSLOT_MASK (0xFF00U) #define USB3_CORE_PORTPMSC_20_L1DSLOT_SHIFT (8U) /*! L1DSLOT - L1 Device Slot */ #define USB3_CORE_PORTPMSC_20_L1DSLOT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_20_L1DSLOT_SHIFT)) & USB3_CORE_PORTPMSC_20_L1DSLOT_MASK) #define USB3_CORE_PORTPMSC_20_HLE_MASK (0x10000U) #define USB3_CORE_PORTPMSC_20_HLE_SHIFT (16U) /*! HLE - Hardware LPM Enable */ #define USB3_CORE_PORTPMSC_20_HLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_20_HLE_SHIFT)) & USB3_CORE_PORTPMSC_20_HLE_MASK) #define USB3_CORE_PORTPMSC_20_PRTTSTCTRL_MASK (0xF0000000U) #define USB3_CORE_PORTPMSC_20_PRTTSTCTRL_SHIFT (28U) /*! PRTTSTCTRL * 0b0000..Test mode not enabled * 0b0001..Test J_STATE * 0b0010..Test K_STATE * 0b0011..Test SE0_NAK * 0b0100..Test packet * 0b0101..Test FORCE_ENABLE * 0b0110-0b1110..Reserved * 0b1111..Port test control error */ #define USB3_CORE_PORTPMSC_20_PRTTSTCTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_20_PRTTSTCTRL_SHIFT)) & USB3_CORE_PORTPMSC_20_PRTTSTCTRL_MASK) /*! @} */ /*! @name PORTHLPMC_20 - USB2 Port Hardware LPM Control */ /*! @{ */ #define USB3_CORE_PORTHLPMC_20_HIRDM_MASK (0x3U) #define USB3_CORE_PORTHLPMC_20_HIRDM_SHIFT (0U) /*! HIRDM - Host Initiated Resume Duration Mode */ #define USB3_CORE_PORTHLPMC_20_HIRDM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTHLPMC_20_HIRDM_SHIFT)) & USB3_CORE_PORTHLPMC_20_HIRDM_MASK) #define USB3_CORE_PORTHLPMC_20_L1_TIMEOUT_MASK (0x3FCU) #define USB3_CORE_PORTHLPMC_20_L1_TIMEOUT_SHIFT (2U) /*! L1_TIMEOUT - L1 Timeout */ #define USB3_CORE_PORTHLPMC_20_L1_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTHLPMC_20_L1_TIMEOUT_SHIFT)) & USB3_CORE_PORTHLPMC_20_L1_TIMEOUT_MASK) #define USB3_CORE_PORTHLPMC_20_BESLD_MASK (0x3C00U) #define USB3_CORE_PORTHLPMC_20_BESLD_SHIFT (10U) /*! BESLD - Best Effort Service Latency Deep */ #define USB3_CORE_PORTHLPMC_20_BESLD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTHLPMC_20_BESLD_SHIFT)) & USB3_CORE_PORTHLPMC_20_BESLD_MASK) /*! @} */ /*! @name PORTSC_30 - USB3 Port Status and Control */ /*! @{ */ #define USB3_CORE_PORTSC_30_CCS_MASK (0x1U) #define USB3_CORE_PORTSC_30_CCS_SHIFT (0U) /*! CCS - Current Connect Status */ #define USB3_CORE_PORTSC_30_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_CCS_SHIFT)) & USB3_CORE_PORTSC_30_CCS_MASK) #define USB3_CORE_PORTSC_30_PED_MASK (0x2U) #define USB3_CORE_PORTSC_30_PED_SHIFT (1U) /*! PED - Port Enabled/Disabled */ #define USB3_CORE_PORTSC_30_PED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PED_SHIFT)) & USB3_CORE_PORTSC_30_PED_MASK) #define USB3_CORE_PORTSC_30_OCA_MASK (0x8U) #define USB3_CORE_PORTSC_30_OCA_SHIFT (3U) /*! OCA - Over Current Active */ #define USB3_CORE_PORTSC_30_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_OCA_SHIFT)) & USB3_CORE_PORTSC_30_OCA_MASK) #define USB3_CORE_PORTSC_30_PR_MASK (0x10U) #define USB3_CORE_PORTSC_30_PR_SHIFT (4U) /*! PR - Port Reset */ #define USB3_CORE_PORTSC_30_PR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PR_SHIFT)) & USB3_CORE_PORTSC_30_PR_MASK) #define USB3_CORE_PORTSC_30_PLS_MASK (0x1E0U) #define USB3_CORE_PORTSC_30_PLS_SHIFT (5U) /*! PLS - Port Link State */ #define USB3_CORE_PORTSC_30_PLS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PLS_SHIFT)) & USB3_CORE_PORTSC_30_PLS_MASK) #define USB3_CORE_PORTSC_30_PP_MASK (0x200U) #define USB3_CORE_PORTSC_30_PP_SHIFT (9U) /*! PP - Port Power */ #define USB3_CORE_PORTSC_30_PP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PP_SHIFT)) & USB3_CORE_PORTSC_30_PP_MASK) #define USB3_CORE_PORTSC_30_PORTSPEED_MASK (0x3C00U) #define USB3_CORE_PORTSC_30_PORTSPEED_SHIFT (10U) /*! PORTSPEED - Port Speed */ #define USB3_CORE_PORTSC_30_PORTSPEED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PORTSPEED_SHIFT)) & USB3_CORE_PORTSC_30_PORTSPEED_MASK) #define USB3_CORE_PORTSC_30_PIC_MASK (0xC000U) #define USB3_CORE_PORTSC_30_PIC_SHIFT (14U) /*! PIC - Port Indicator Control */ #define USB3_CORE_PORTSC_30_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PIC_SHIFT)) & USB3_CORE_PORTSC_30_PIC_MASK) #define USB3_CORE_PORTSC_30_LWS_MASK (0x10000U) #define USB3_CORE_PORTSC_30_LWS_SHIFT (16U) /*! LWS - Port Link State Write Strobe */ #define USB3_CORE_PORTSC_30_LWS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_LWS_SHIFT)) & USB3_CORE_PORTSC_30_LWS_MASK) #define USB3_CORE_PORTSC_30_CSC_MASK (0x20000U) #define USB3_CORE_PORTSC_30_CSC_SHIFT (17U) /*! CSC - Connect Status Change */ #define USB3_CORE_PORTSC_30_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_CSC_SHIFT)) & USB3_CORE_PORTSC_30_CSC_MASK) #define USB3_CORE_PORTSC_30_PEC_MASK (0x40000U) #define USB3_CORE_PORTSC_30_PEC_SHIFT (18U) /*! PEC - Port Enabled/Disabled Change */ #define USB3_CORE_PORTSC_30_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PEC_SHIFT)) & USB3_CORE_PORTSC_30_PEC_MASK) #define USB3_CORE_PORTSC_30_WRC_MASK (0x80000U) #define USB3_CORE_PORTSC_30_WRC_SHIFT (19U) /*! WRC - Warm Port Reset Change */ #define USB3_CORE_PORTSC_30_WRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_WRC_SHIFT)) & USB3_CORE_PORTSC_30_WRC_MASK) #define USB3_CORE_PORTSC_30_OCC_MASK (0x100000U) #define USB3_CORE_PORTSC_30_OCC_SHIFT (20U) /*! OCC - Over Current Change */ #define USB3_CORE_PORTSC_30_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_OCC_SHIFT)) & USB3_CORE_PORTSC_30_OCC_MASK) #define USB3_CORE_PORTSC_30_PRC_MASK (0x200000U) #define USB3_CORE_PORTSC_30_PRC_SHIFT (21U) /*! PRC - Port Reset Change */ #define USB3_CORE_PORTSC_30_PRC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PRC_SHIFT)) & USB3_CORE_PORTSC_30_PRC_MASK) #define USB3_CORE_PORTSC_30_PLC_MASK (0x400000U) #define USB3_CORE_PORTSC_30_PLC_SHIFT (22U) /*! PLC - Port Link State Change */ #define USB3_CORE_PORTSC_30_PLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_PLC_SHIFT)) & USB3_CORE_PORTSC_30_PLC_MASK) #define USB3_CORE_PORTSC_30_CEC_MASK (0x800000U) #define USB3_CORE_PORTSC_30_CEC_SHIFT (23U) /*! CEC - Port Config Error Change */ #define USB3_CORE_PORTSC_30_CEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_CEC_SHIFT)) & USB3_CORE_PORTSC_30_CEC_MASK) #define USB3_CORE_PORTSC_30_CAS_MASK (0x1000000U) #define USB3_CORE_PORTSC_30_CAS_SHIFT (24U) /*! CAS - Cold Attach Status */ #define USB3_CORE_PORTSC_30_CAS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_CAS_SHIFT)) & USB3_CORE_PORTSC_30_CAS_MASK) #define USB3_CORE_PORTSC_30_WCE_MASK (0x2000000U) #define USB3_CORE_PORTSC_30_WCE_SHIFT (25U) /*! WCE - Wake on Connect Enable */ #define USB3_CORE_PORTSC_30_WCE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_WCE_SHIFT)) & USB3_CORE_PORTSC_30_WCE_MASK) #define USB3_CORE_PORTSC_30_WDE_MASK (0x4000000U) #define USB3_CORE_PORTSC_30_WDE_SHIFT (26U) /*! WDE - Wake on Disconnect Enable */ #define USB3_CORE_PORTSC_30_WDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_WDE_SHIFT)) & USB3_CORE_PORTSC_30_WDE_MASK) #define USB3_CORE_PORTSC_30_WOE_MASK (0x8000000U) #define USB3_CORE_PORTSC_30_WOE_SHIFT (27U) /*! WOE - Wake on Overcurrent Enable */ #define USB3_CORE_PORTSC_30_WOE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_WOE_SHIFT)) & USB3_CORE_PORTSC_30_WOE_MASK) #define USB3_CORE_PORTSC_30_DR_MASK (0x40000000U) #define USB3_CORE_PORTSC_30_DR_SHIFT (30U) /*! DR - Device Removable */ #define USB3_CORE_PORTSC_30_DR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_DR_SHIFT)) & USB3_CORE_PORTSC_30_DR_MASK) #define USB3_CORE_PORTSC_30_WPR_MASK (0x80000000U) #define USB3_CORE_PORTSC_30_WPR_SHIFT (31U) /*! WPR - Warm Port Reset */ #define USB3_CORE_PORTSC_30_WPR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTSC_30_WPR_SHIFT)) & USB3_CORE_PORTSC_30_WPR_MASK) /*! @} */ /*! @name PORTPMSC_30 - USB3 Port Power Management Status and Control */ /*! @{ */ #define USB3_CORE_PORTPMSC_30_U1_TIMEOUT_MASK (0xFFU) #define USB3_CORE_PORTPMSC_30_U1_TIMEOUT_SHIFT (0U) /*! U1_TIMEOUT - U1 Timeout */ #define USB3_CORE_PORTPMSC_30_U1_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_30_U1_TIMEOUT_SHIFT)) & USB3_CORE_PORTPMSC_30_U1_TIMEOUT_MASK) #define USB3_CORE_PORTPMSC_30_U2_TIMEOUT_MASK (0xFF00U) #define USB3_CORE_PORTPMSC_30_U2_TIMEOUT_SHIFT (8U) /*! U2_TIMEOUT - U2 Timeout */ #define USB3_CORE_PORTPMSC_30_U2_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_30_U2_TIMEOUT_SHIFT)) & USB3_CORE_PORTPMSC_30_U2_TIMEOUT_MASK) #define USB3_CORE_PORTPMSC_30_FLA_MASK (0x10000U) #define USB3_CORE_PORTPMSC_30_FLA_SHIFT (16U) /*! FLA - Force Link PM Accept */ #define USB3_CORE_PORTPMSC_30_FLA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTPMSC_30_FLA_SHIFT)) & USB3_CORE_PORTPMSC_30_FLA_MASK) /*! @} */ /*! @name PORTLI_30 - USB3 Port Link Information */ /*! @{ */ #define USB3_CORE_PORTLI_30_LINK_ERROR_COUNT_MASK (0xFFFFU) #define USB3_CORE_PORTLI_30_LINK_ERROR_COUNT_SHIFT (0U) /*! LINK_ERROR_COUNT - Link Error Count */ #define USB3_CORE_PORTLI_30_LINK_ERROR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_PORTLI_30_LINK_ERROR_COUNT_SHIFT)) & USB3_CORE_PORTLI_30_LINK_ERROR_COUNT_MASK) /*! @} */ /*! @name MFINDEX - Microframe Index */ /*! @{ */ #define USB3_CORE_MFINDEX_MICROFRAME_INDEX_MASK (0x3FFFU) #define USB3_CORE_MFINDEX_MICROFRAME_INDEX_SHIFT (0U) /*! MICROFRAME_INDEX - Microframe Index */ #define USB3_CORE_MFINDEX_MICROFRAME_INDEX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_MFINDEX_MICROFRAME_INDEX_SHIFT)) & USB3_CORE_MFINDEX_MICROFRAME_INDEX_MASK) /*! @} */ /*! @name IMAN - Interrupter Management */ /*! @{ */ #define USB3_CORE_IMAN_IP_MASK (0x1U) #define USB3_CORE_IMAN_IP_SHIFT (0U) /*! IP - Interrupt Pending */ #define USB3_CORE_IMAN_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_IMAN_IP_SHIFT)) & USB3_CORE_IMAN_IP_MASK) #define USB3_CORE_IMAN_IE_MASK (0x2U) #define USB3_CORE_IMAN_IE_SHIFT (1U) /*! IE - Interrupt Enable */ #define USB3_CORE_IMAN_IE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_IMAN_IE_SHIFT)) & USB3_CORE_IMAN_IE_MASK) /*! @} */ /*! @name IMOD - Interrupter Moderation */ /*! @{ */ #define USB3_CORE_IMOD_IMODI_MASK (0xFFFFU) #define USB3_CORE_IMOD_IMODI_SHIFT (0U) /*! IMODI - Interrupt Moderation Interval */ #define USB3_CORE_IMOD_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_IMOD_IMODI_SHIFT)) & USB3_CORE_IMOD_IMODI_MASK) #define USB3_CORE_IMOD_IMODC_MASK (0xFFFF0000U) #define USB3_CORE_IMOD_IMODC_SHIFT (16U) /*! IMODC - Interrupt Moderation Counter */ #define USB3_CORE_IMOD_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_IMOD_IMODC_SHIFT)) & USB3_CORE_IMOD_IMODC_MASK) /*! @} */ /*! @name ERSTSZ - Event Ring Segment Table Size */ /*! @{ */ #define USB3_CORE_ERSTSZ_ERS_TABLE_SIZE_MASK (0xFFFFU) #define USB3_CORE_ERSTSZ_ERS_TABLE_SIZE_SHIFT (0U) /*! ERS_TABLE_SIZE - Event Ring Segment Table Size */ #define USB3_CORE_ERSTSZ_ERS_TABLE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_ERSTSZ_ERS_TABLE_SIZE_SHIFT)) & USB3_CORE_ERSTSZ_ERS_TABLE_SIZE_MASK) /*! @} */ /*! @name ERSTBA_LO - Event Ring Segment Table Base Address - Low */ /*! @{ */ #define USB3_CORE_ERSTBA_LO_ERS_TABLE_BAR_MASK (0xFFFFFFC0U) #define USB3_CORE_ERSTBA_LO_ERS_TABLE_BAR_SHIFT (6U) /*! ERS_TABLE_BAR - Event Ring Segment Table Base Address */ #define USB3_CORE_ERSTBA_LO_ERS_TABLE_BAR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_ERSTBA_LO_ERS_TABLE_BAR_SHIFT)) & USB3_CORE_ERSTBA_LO_ERS_TABLE_BAR_MASK) /*! @} */ /*! @name ERSTBA_HI - Event Ring Segment Table Base Address -Low */ /*! @{ */ #define USB3_CORE_ERSTBA_HI_ERS_TABLE_BAR_MASK (0xFFFFFFFFU) #define USB3_CORE_ERSTBA_HI_ERS_TABLE_BAR_SHIFT (0U) /*! ERS_TABLE_BAR - Event Ring Segment Table Base Address */ #define USB3_CORE_ERSTBA_HI_ERS_TABLE_BAR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_ERSTBA_HI_ERS_TABLE_BAR_SHIFT)) & USB3_CORE_ERSTBA_HI_ERS_TABLE_BAR_MASK) /*! @} */ /*! @name ERDP_LO - Event Ring Dequeue - Low */ /*! @{ */ #define USB3_CORE_ERDP_LO_DESI_MASK (0x7U) #define USB3_CORE_ERDP_LO_DESI_SHIFT (0U) /*! DESI - Dequeue ERST Segment Index */ #define USB3_CORE_ERDP_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_ERDP_LO_DESI_SHIFT)) & USB3_CORE_ERDP_LO_DESI_MASK) #define USB3_CORE_ERDP_LO_EHB_MASK (0x8U) #define USB3_CORE_ERDP_LO_EHB_SHIFT (3U) /*! EHB - Event Handler Busy */ #define USB3_CORE_ERDP_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_ERDP_LO_EHB_SHIFT)) & USB3_CORE_ERDP_LO_EHB_MASK) #define USB3_CORE_ERDP_LO_ERD_PNTR_MASK (0xFFFFFFF0U) #define USB3_CORE_ERDP_LO_ERD_PNTR_SHIFT (4U) /*! ERD_PNTR - Event Ring Dequeue Pointer */ #define USB3_CORE_ERDP_LO_ERD_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_ERDP_LO_ERD_PNTR_SHIFT)) & USB3_CORE_ERDP_LO_ERD_PNTR_MASK) /*! @} */ /*! @name ERDP_HI - Event Ring Dequeue - Low */ /*! @{ */ #define USB3_CORE_ERDP_HI_ERD_PNTR_MASK (0xFFFFFFFFU) #define USB3_CORE_ERDP_HI_ERD_PNTR_SHIFT (0U) /*! ERD_PNTR - Event Ring Dequeue Pointer */ #define USB3_CORE_ERDP_HI_ERD_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_ERDP_HI_ERD_PNTR_SHIFT)) & USB3_CORE_ERDP_HI_ERD_PNTR_MASK) /*! @} */ /*! @name DB - Doorbell 0..Doorbell 63 */ /*! @{ */ #define USB3_CORE_DB_DB_TARGET_MASK (0xFFU) #define USB3_CORE_DB_DB_TARGET_SHIFT (0U) /*! DB_TARGET - Doorbell Target */ #define USB3_CORE_DB_DB_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DB_DB_TARGET_SHIFT)) & USB3_CORE_DB_DB_TARGET_MASK) #define USB3_CORE_DB_DB_STREAM_ID_MASK (0xFFFF0000U) #define USB3_CORE_DB_DB_STREAM_ID_SHIFT (16U) /*! DB_STREAM_ID - Doorbell Stream ID */ #define USB3_CORE_DB_DB_STREAM_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DB_DB_STREAM_ID_SHIFT)) & USB3_CORE_DB_DB_STREAM_ID_MASK) /*! @} */ /* The count of USB3_CORE_DB */ #define USB3_CORE_DB_COUNT (64U) /*! @name USBLEGSUP - USB Legacy Support Capability */ /*! @{ */ #define USB3_CORE_USBLEGSUP_CAPABILITY_ID_MASK (0xFFU) #define USB3_CORE_USBLEGSUP_CAPABILITY_ID_SHIFT (0U) /*! CAPABILITY_ID - Capability ID */ #define USB3_CORE_USBLEGSUP_CAPABILITY_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGSUP_CAPABILITY_ID_SHIFT)) & USB3_CORE_USBLEGSUP_CAPABILITY_ID_MASK) #define USB3_CORE_USBLEGSUP_NEXT_CAPABILITY_POINTER_MASK (0xFF00U) #define USB3_CORE_USBLEGSUP_NEXT_CAPABILITY_POINTER_SHIFT (8U) /*! NEXT_CAPABILITY_POINTER - Next Capability Pointer */ #define USB3_CORE_USBLEGSUP_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGSUP_NEXT_CAPABILITY_POINTER_SHIFT)) & USB3_CORE_USBLEGSUP_NEXT_CAPABILITY_POINTER_MASK) #define USB3_CORE_USBLEGSUP_HC_BIOS_OWNED_MASK (0x10000U) #define USB3_CORE_USBLEGSUP_HC_BIOS_OWNED_SHIFT (16U) /*! HC_BIOS_OWNED - HC BIOS Owned Semaphore */ #define USB3_CORE_USBLEGSUP_HC_BIOS_OWNED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGSUP_HC_BIOS_OWNED_SHIFT)) & USB3_CORE_USBLEGSUP_HC_BIOS_OWNED_MASK) #define USB3_CORE_USBLEGSUP_HC_OS_OWNED_MASK (0x1000000U) #define USB3_CORE_USBLEGSUP_HC_OS_OWNED_SHIFT (24U) /*! HC_OS_OWNED - HC OS Owned Semaphore */ #define USB3_CORE_USBLEGSUP_HC_OS_OWNED(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGSUP_HC_OS_OWNED_SHIFT)) & USB3_CORE_USBLEGSUP_HC_OS_OWNED_MASK) /*! @} */ /*! @name USBLEGCTLSTS - USB Legacy Support Control and Status */ /*! @{ */ #define USB3_CORE_USBLEGCTLSTS_USB_SMI_ENABLE_MASK (0x1U) #define USB3_CORE_USBLEGCTLSTS_USB_SMI_ENABLE_SHIFT (0U) /*! USB_SMI_ENABLE - USB SMI Enable */ #define USB3_CORE_USBLEGCTLSTS_USB_SMI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_USB_SMI_ENABLE_SHIFT)) & USB3_CORE_USBLEGCTLSTS_USB_SMI_ENABLE_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_E_MASK (0x10U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_E_SHIFT (4U) /*! SMI_ON_HOST_E - SMI on Host System Error Enable */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_E(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_E_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_E_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_E_MASK (0x2000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_E_SHIFT (13U) /*! SMI_ON_OS_E - SMI on OS Ownership Enable */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_E(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_E_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_E_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_E_MASK (0x4000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_E_SHIFT (14U) /*! SMI_ON_PCI_E - SMI on PCI Command Enable */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_E(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_E_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_E_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_E_MASK (0x8000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_E_SHIFT (15U) /*! SMI_ON_BAR_E - SMI on BAR Enable */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_E(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_E_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_E_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_EVENT_MASK (0x10000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_EVENT_SHIFT (16U) /*! SMI_ON_EVENT - SMI on Event Enable */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_EVENT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_EVENT_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_EVENT_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_MASK (0x100000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_SHIFT (20U) /*! SMI_ON_HOST - SMI on Host System Error */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_HOST_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_MASK (0x20000000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_SHIFT (29U) /*! SMI_ON_OS - SMI on Ownership Change */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_OS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_OS_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_MASK (0x40000000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_SHIFT (30U) /*! SMI_ON_PCI - SMI on PCI Command */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_PCI_MASK) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_MASK (0x80000000U) #define USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_SHIFT (31U) /*! SMI_ON_BAR - SMI on BAR */ #define USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_SHIFT)) & USB3_CORE_USBLEGCTLSTS_SMI_ON_BAR_MASK) /*! @} */ /*! @name SUPTPRT2_DW0 - USB2 xHCI Supported Protocol Capability Data Word 0 */ /*! @{ */ #define USB3_CORE_SUPTPRT2_DW0_CAPABILITY_ID_MASK (0xFFU) #define USB3_CORE_SUPTPRT2_DW0_CAPABILITY_ID_SHIFT (0U) /*! CAPABILITY_ID - Capability ID */ #define USB3_CORE_SUPTPRT2_DW0_CAPABILITY_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW0_CAPABILITY_ID_SHIFT)) & USB3_CORE_SUPTPRT2_DW0_CAPABILITY_ID_MASK) #define USB3_CORE_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_MASK (0xFF00U) #define USB3_CORE_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_SHIFT (8U) /*! NEXT_CAPABILITY_POINTER - Next Capability Pointer */ #define USB3_CORE_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_SHIFT)) & USB3_CORE_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_MASK) #define USB3_CORE_SUPTPRT2_DW0_MINOR_REVISION_MASK (0xFF0000U) #define USB3_CORE_SUPTPRT2_DW0_MINOR_REVISION_SHIFT (16U) /*! MINOR_REVISION - Minor Revision */ #define USB3_CORE_SUPTPRT2_DW0_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW0_MINOR_REVISION_SHIFT)) & USB3_CORE_SUPTPRT2_DW0_MINOR_REVISION_MASK) #define USB3_CORE_SUPTPRT2_DW0_MAJOR_REVISION_MASK (0xFF000000U) #define USB3_CORE_SUPTPRT2_DW0_MAJOR_REVISION_SHIFT (24U) /*! MAJOR_REVISION - Major Revision */ #define USB3_CORE_SUPTPRT2_DW0_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW0_MAJOR_REVISION_SHIFT)) & USB3_CORE_SUPTPRT2_DW0_MAJOR_REVISION_MASK) /*! @} */ /*! @name SUPTPRT2_DW1 - USB2 xHCI Supported Protocol Capability Data Word 1 */ /*! @{ */ #define USB3_CORE_SUPTPRT2_DW1_NAME_STRING_MASK (0xFFFFFFFFU) #define USB3_CORE_SUPTPRT2_DW1_NAME_STRING_SHIFT (0U) /*! NAME_STRING - Name String */ #define USB3_CORE_SUPTPRT2_DW1_NAME_STRING(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW1_NAME_STRING_SHIFT)) & USB3_CORE_SUPTPRT2_DW1_NAME_STRING_MASK) /*! @} */ /*! @name SUPTPRT2_DW2 - USB2 xHCI Supported Protocol Capability Data Word 2 */ /*! @{ */ #define USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_MASK (0xFFU) #define USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_SHIFT (0U) /*! COMPATIBLE_PORT_OFFSET - Compatible Port Offset */ #define USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_MASK) #define USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_MASK (0xFF00U) #define USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_SHIFT (8U) /*! COMPATIBLE_PORT_COUNT - Compatible Port Count */ #define USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_MASK) #define USB3_CORE_SUPTPRT2_DW2_HSO_MASK (0x20000U) #define USB3_CORE_SUPTPRT2_DW2_HSO_SHIFT (17U) /*! HSO - High-Speed Only */ #define USB3_CORE_SUPTPRT2_DW2_HSO(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_HSO_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_HSO_MASK) #define USB3_CORE_SUPTPRT2_DW2_IHI_MASK (0x40000U) #define USB3_CORE_SUPTPRT2_DW2_IHI_SHIFT (18U) /*! IHI - Integrated Hub Implemented */ #define USB3_CORE_SUPTPRT2_DW2_IHI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_IHI_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_IHI_MASK) #define USB3_CORE_SUPTPRT2_DW2_HLC_MASK (0x80000U) #define USB3_CORE_SUPTPRT2_DW2_HLC_SHIFT (19U) /*! HLC - Compatible Port Offset */ #define USB3_CORE_SUPTPRT2_DW2_HLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_HLC_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_HLC_MASK) #define USB3_CORE_SUPTPRT2_DW2_BLC_MASK (0x100000U) #define USB3_CORE_SUPTPRT2_DW2_BLC_SHIFT (20U) /*! BLC - BESL LPM Capability * 0b0..The ports described by this xHCI Supported Protocol Capability applies HIRD timing to the BESL and BESLD * fields of the PORTPMSC and PORTHLPMC registers. * 0b1..The ports described by this xHCI Supported Protocol Capability applies BESL timing to the BESL and BESLD * fields of the PORTPMSC and PORTHLPMC registers. */ #define USB3_CORE_SUPTPRT2_DW2_BLC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_BLC_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_BLC_MASK) #define USB3_CORE_SUPTPRT2_DW2_MHD_MASK (0xE000000U) #define USB3_CORE_SUPTPRT2_DW2_MHD_SHIFT (25U) /*! MHD - Hub Depth */ #define USB3_CORE_SUPTPRT2_DW2_MHD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_MHD_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_MHD_MASK) #define USB3_CORE_SUPTPRT2_DW2_PSIC_MASK (0xF0000000U) #define USB3_CORE_SUPTPRT2_DW2_PSIC_SHIFT (28U) /*! PSIC - Protocol Speed ID Count */ #define USB3_CORE_SUPTPRT2_DW2_PSIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW2_PSIC_SHIFT)) & USB3_CORE_SUPTPRT2_DW2_PSIC_MASK) /*! @} */ /*! @name SUPTPRT2_DW3 - USB2 xHCI Supported Protocol Capability Data Word 3 */ /*! @{ */ #define USB3_CORE_SUPTPRT2_DW3_PROTCL_SLT_TY_MASK (0x1FU) #define USB3_CORE_SUPTPRT2_DW3_PROTCL_SLT_TY_SHIFT (0U) /*! PROTCL_SLT_TY - Protocol Slot Type */ #define USB3_CORE_SUPTPRT2_DW3_PROTCL_SLT_TY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT2_DW3_PROTCL_SLT_TY_SHIFT)) & USB3_CORE_SUPTPRT2_DW3_PROTCL_SLT_TY_MASK) /*! @} */ /*! @name SUPTPRT3_DW0 - USB3 xHCI Supported Protocol Capability Data Word 0 */ /*! @{ */ #define USB3_CORE_SUPTPRT3_DW0_CAPABILITY_ID_MASK (0xFFU) #define USB3_CORE_SUPTPRT3_DW0_CAPABILITY_ID_SHIFT (0U) /*! CAPABILITY_ID - Capability ID */ #define USB3_CORE_SUPTPRT3_DW0_CAPABILITY_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW0_CAPABILITY_ID_SHIFT)) & USB3_CORE_SUPTPRT3_DW0_CAPABILITY_ID_MASK) #define USB3_CORE_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_MASK (0xFF00U) #define USB3_CORE_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_SHIFT (8U) /*! NEXT_CAPABILITY_POINTER - Next Capability Pointer */ #define USB3_CORE_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_SHIFT)) & USB3_CORE_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_MASK) #define USB3_CORE_SUPTPRT3_DW0_MINOR_REVISION_MASK (0xFF0000U) #define USB3_CORE_SUPTPRT3_DW0_MINOR_REVISION_SHIFT (16U) /*! MINOR_REVISION - Minor Revision */ #define USB3_CORE_SUPTPRT3_DW0_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW0_MINOR_REVISION_SHIFT)) & USB3_CORE_SUPTPRT3_DW0_MINOR_REVISION_MASK) #define USB3_CORE_SUPTPRT3_DW0_MAJOR_REVISION_MASK (0xFF000000U) #define USB3_CORE_SUPTPRT3_DW0_MAJOR_REVISION_SHIFT (24U) /*! MAJOR_REVISION - Major Revision */ #define USB3_CORE_SUPTPRT3_DW0_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW0_MAJOR_REVISION_SHIFT)) & USB3_CORE_SUPTPRT3_DW0_MAJOR_REVISION_MASK) /*! @} */ /*! @name SUPTPRT3_DW1 - USB3 xHCI Supported Protocol Capability Data Word 1 */ /*! @{ */ #define USB3_CORE_SUPTPRT3_DW1_NAME_STRING_MASK (0xFFFFFFFFU) #define USB3_CORE_SUPTPRT3_DW1_NAME_STRING_SHIFT (0U) /*! NAME_STRING - Name String */ #define USB3_CORE_SUPTPRT3_DW1_NAME_STRING(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW1_NAME_STRING_SHIFT)) & USB3_CORE_SUPTPRT3_DW1_NAME_STRING_MASK) /*! @} */ /*! @name SUPTPRT3_DW2 - USB3 xHCI Supported Protocol Capability Data Word 2 */ /*! @{ */ #define USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_MASK (0xFFU) #define USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_SHIFT (0U) /*! COMPATIBLE_PORT_OFFSET - Compatible Port Offset */ #define USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_SHIFT)) & USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_MASK) #define USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_MASK (0xFF00U) #define USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_SHIFT (8U) /*! COMPATIBLE_PORT_COUNT - Compatible Port Count */ #define USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_SHIFT)) & USB3_CORE_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_MASK) #define USB3_CORE_SUPTPRT3_DW2_MHD_MASK (0xE000000U) #define USB3_CORE_SUPTPRT3_DW2_MHD_SHIFT (25U) /*! MHD - Hub Depth */ #define USB3_CORE_SUPTPRT3_DW2_MHD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW2_MHD_SHIFT)) & USB3_CORE_SUPTPRT3_DW2_MHD_MASK) #define USB3_CORE_SUPTPRT3_DW2_PSIC_MASK (0xF0000000U) #define USB3_CORE_SUPTPRT3_DW2_PSIC_SHIFT (28U) /*! PSIC - Protocol Speed ID Count */ #define USB3_CORE_SUPTPRT3_DW2_PSIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW2_PSIC_SHIFT)) & USB3_CORE_SUPTPRT3_DW2_PSIC_MASK) /*! @} */ /*! @name SUPTPRT3_DW3 - USB3 xHCI Supported Protocol Capability Data Word 3 */ /*! @{ */ #define USB3_CORE_SUPTPRT3_DW3_PROTCL_SLT_TY_MASK (0x1FU) #define USB3_CORE_SUPTPRT3_DW3_PROTCL_SLT_TY_SHIFT (0U) /*! PROTCL_SLT_TY - Protocol Slot Type */ #define USB3_CORE_SUPTPRT3_DW3_PROTCL_SLT_TY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_SUPTPRT3_DW3_PROTCL_SLT_TY_SHIFT)) & USB3_CORE_SUPTPRT3_DW3_PROTCL_SLT_TY_MASK) /*! @} */ /*! @name GSBUSCFG0 - Global SoC Bus Configuration 0 */ /*! @{ */ #define USB3_CORE_GSBUSCFG0_INCRBRSTENA_MASK (0x1U) #define USB3_CORE_GSBUSCFG0_INCRBRSTENA_SHIFT (0U) /*! INCRBRSTENA - Undefined Length INCR Burst Type Enable * 0b0..INCRX burst mode * 0b1..INCR (undefined length) burst mode */ #define USB3_CORE_GSBUSCFG0_INCRBRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCRBRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCRBRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_INCR4BRSTENA_MASK (0x2U) #define USB3_CORE_GSBUSCFG0_INCR4BRSTENA_SHIFT (1U) /*! INCR4BRSTENA - INCR4 Burst Type Enable Input to BUS-GM */ #define USB3_CORE_GSBUSCFG0_INCR4BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCR4BRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCR4BRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_INCR8BRSTENA_MASK (0x4U) #define USB3_CORE_GSBUSCFG0_INCR8BRSTENA_SHIFT (2U) /*! INCR8BRSTENA - INCR8 Burst Type Enable */ #define USB3_CORE_GSBUSCFG0_INCR8BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCR8BRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCR8BRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_INCR16BRSTENA_MASK (0x8U) #define USB3_CORE_GSBUSCFG0_INCR16BRSTENA_SHIFT (3U) /*! INCR16BRSTENA - INCR16 Burst Type Enable */ #define USB3_CORE_GSBUSCFG0_INCR16BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCR16BRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCR16BRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_INCR32BRSTENA_MASK (0x10U) #define USB3_CORE_GSBUSCFG0_INCR32BRSTENA_SHIFT (4U) /*! INCR32BRSTENA - INCR32 Burst Type Enable */ #define USB3_CORE_GSBUSCFG0_INCR32BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCR32BRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCR32BRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_INCR64BRSTENA_MASK (0x20U) #define USB3_CORE_GSBUSCFG0_INCR64BRSTENA_SHIFT (5U) /*! INCR64BRSTENA - INCR64 Burst Type Enable */ #define USB3_CORE_GSBUSCFG0_INCR64BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCR64BRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCR64BRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_INCR128BRSTENA_MASK (0x40U) #define USB3_CORE_GSBUSCFG0_INCR128BRSTENA_SHIFT (6U) /*! INCR128BRSTENA - INCR128 Burst Type Enable */ #define USB3_CORE_GSBUSCFG0_INCR128BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCR128BRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCR128BRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_INCR256BRSTENA_MASK (0x80U) #define USB3_CORE_GSBUSCFG0_INCR256BRSTENA_SHIFT (7U) /*! INCR256BRSTENA - INCR256 Burst Type Enable */ #define USB3_CORE_GSBUSCFG0_INCR256BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_INCR256BRSTENA_SHIFT)) & USB3_CORE_GSBUSCFG0_INCR256BRSTENA_MASK) #define USB3_CORE_GSBUSCFG0_DESBIGEND_MASK (0x400U) #define USB3_CORE_GSBUSCFG0_DESBIGEND_SHIFT (10U) /*! DESBIGEND - Descriptor Access Is Big Endian */ #define USB3_CORE_GSBUSCFG0_DESBIGEND(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_DESBIGEND_SHIFT)) & USB3_CORE_GSBUSCFG0_DESBIGEND_MASK) #define USB3_CORE_GSBUSCFG0_DATBIGEND_MASK (0x800U) #define USB3_CORE_GSBUSCFG0_DATBIGEND_SHIFT (11U) /*! DATBIGEND - Data Access Is Big Endian */ #define USB3_CORE_GSBUSCFG0_DATBIGEND(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_DATBIGEND_SHIFT)) & USB3_CORE_GSBUSCFG0_DATBIGEND_MASK) #define USB3_CORE_GSBUSCFG0_DESWRREQINFO_MASK (0xF0000U) #define USB3_CORE_GSBUSCFG0_DESWRREQINFO_SHIFT (16U) /*! DESWRREQINFO - AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write */ #define USB3_CORE_GSBUSCFG0_DESWRREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_DESWRREQINFO_SHIFT)) & USB3_CORE_GSBUSCFG0_DESWRREQINFO_MASK) #define USB3_CORE_GSBUSCFG0_DATWRREQINFO_MASK (0xF00000U) #define USB3_CORE_GSBUSCFG0_DATWRREQINFO_SHIFT (20U) /*! DATWRREQINFO - AHB-prot/AXI-cache/OCP-ReqInfo for Data Write */ #define USB3_CORE_GSBUSCFG0_DATWRREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_DATWRREQINFO_SHIFT)) & USB3_CORE_GSBUSCFG0_DATWRREQINFO_MASK) #define USB3_CORE_GSBUSCFG0_DESRDREQINFO_MASK (0xF000000U) #define USB3_CORE_GSBUSCFG0_DESRDREQINFO_SHIFT (24U) /*! DESRDREQINFO - AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read */ #define USB3_CORE_GSBUSCFG0_DESRDREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_DESRDREQINFO_SHIFT)) & USB3_CORE_GSBUSCFG0_DESRDREQINFO_MASK) #define USB3_CORE_GSBUSCFG0_DATRDREQINFO_MASK (0xF0000000U) #define USB3_CORE_GSBUSCFG0_DATRDREQINFO_SHIFT (28U) /*! DATRDREQINFO - AHB-prot/AXI-cache/OCP-ReqInfo for Data Read */ #define USB3_CORE_GSBUSCFG0_DATRDREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG0_DATRDREQINFO_SHIFT)) & USB3_CORE_GSBUSCFG0_DATRDREQINFO_MASK) /*! @} */ /*! @name GSBUSCFG1 - Global SoC Bus Configuration 1 */ /*! @{ */ #define USB3_CORE_GSBUSCFG1_PIPETRANSLIMIT_MASK (0xF00U) #define USB3_CORE_GSBUSCFG1_PIPETRANSLIMIT_SHIFT (8U) /*! PIPETRANSLIMIT - AXI Pipelined Transfers Burst Request Limit * 0b0000..1 request * 0b0001..2 requests * 0b0010-0b1111..3 - 16 requests */ #define USB3_CORE_GSBUSCFG1_PIPETRANSLIMIT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG1_PIPETRANSLIMIT_SHIFT)) & USB3_CORE_GSBUSCFG1_PIPETRANSLIMIT_MASK) #define USB3_CORE_GSBUSCFG1_EN1KPAGE_MASK (0x1000U) #define USB3_CORE_GSBUSCFG1_EN1KPAGE_SHIFT (12U) /*! EN1KPAGE - 1k Page Boundary Enable */ #define USB3_CORE_GSBUSCFG1_EN1KPAGE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSBUSCFG1_EN1KPAGE_SHIFT)) & USB3_CORE_GSBUSCFG1_EN1KPAGE_MASK) /*! @} */ /*! @name GTXTHRCFG - Global TX Threshold Control */ /*! @{ */ #define USB3_CORE_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK (0xFF0000U) #define USB3_CORE_GTXTHRCFG_USBMAXTXBURSTSIZE_SHIFT (16U) /*! USBMAXTXBURSTSIZE - USB Maximum TX Burst Size */ #define USB3_CORE_GTXTHRCFG_USBMAXTXBURSTSIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GTXTHRCFG_USBMAXTXBURSTSIZE_SHIFT)) & USB3_CORE_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK) #define USB3_CORE_GTXTHRCFG_USBTXPKTCNT_MASK (0xF000000U) #define USB3_CORE_GTXTHRCFG_USBTXPKTCNT_SHIFT (24U) /*! USBTXPKTCNT - USB Transmit Packet Count */ #define USB3_CORE_GTXTHRCFG_USBTXPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GTXTHRCFG_USBTXPKTCNT_SHIFT)) & USB3_CORE_GTXTHRCFG_USBTXPKTCNT_MASK) #define USB3_CORE_GTXTHRCFG_USBTXPKTCNTSEL_MASK (0x20000000U) #define USB3_CORE_GTXTHRCFG_USBTXPKTCNTSEL_SHIFT (29U) /*! USBTXPKTCNTSEL - USB Transmit Packet Count Enable * 0b0..Disabled, the core can start transmission on the USB after the entire (one full) packet has been fetched into the corresponding TXFIFO. * 0b1..Enabled, the core can only start transmission on the USB after USB Transmit Packet Count amount of * packets for the USB transaction (burst) are already in the corresponding TXFIFO. This mode is valid in both host * and device modes. It is only used for SuperSpeed operation. */ #define USB3_CORE_GTXTHRCFG_USBTXPKTCNTSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GTXTHRCFG_USBTXPKTCNTSEL_SHIFT)) & USB3_CORE_GTXTHRCFG_USBTXPKTCNTSEL_MASK) /*! @} */ /*! @name GRXTHRCFG - Global RX Threshold Control */ /*! @{ */ #define USB3_CORE_GRXTHRCFG_RESVISOCOUTSPC_MASK (0x1FFFU) #define USB3_CORE_GRXTHRCFG_RESVISOCOUTSPC_SHIFT (0U) /*! RESVISOCOUTSPC - Space Reserved In RX FIFO For ISOC OUT */ #define USB3_CORE_GRXTHRCFG_RESVISOCOUTSPC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GRXTHRCFG_RESVISOCOUTSPC_SHIFT)) & USB3_CORE_GRXTHRCFG_RESVISOCOUTSPC_MASK) #define USB3_CORE_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK (0xF80000U) #define USB3_CORE_GRXTHRCFG_USBMAXRXBURSTSIZE_SHIFT (19U) /*! USBMAXRXBURSTSIZE - USB Maximum Receive Burst Size */ #define USB3_CORE_GRXTHRCFG_USBMAXRXBURSTSIZE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GRXTHRCFG_USBMAXRXBURSTSIZE_SHIFT)) & USB3_CORE_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK) #define USB3_CORE_GRXTHRCFG_USBRXPKTCNT_MASK (0xF000000U) #define USB3_CORE_GRXTHRCFG_USBRXPKTCNT_SHIFT (24U) /*! USBRXPKTCNT - USB Receive Packet Count */ #define USB3_CORE_GRXTHRCFG_USBRXPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GRXTHRCFG_USBRXPKTCNT_SHIFT)) & USB3_CORE_GRXTHRCFG_USBRXPKTCNT_MASK) #define USB3_CORE_GRXTHRCFG_USBRXPKTCNTSEL_MASK (0x20000000U) #define USB3_CORE_GRXTHRCFG_USBRXPKTCNTSEL_SHIFT (29U) /*! USBRXPKTCNTSEL - USB Receive Packet Count Enable * 0b0..The core can only start reception on the USB when the RX FIFO has space for at least one packet. * 0b1..The core can only start reception on the USB when the RX FIFO has space for at least UsbRxPktCnt amount * of packets. This mode is valid in both host and device mode. It is only used for SuperSpeed. In device * mode, setting this bit to 1 also enables the functionality of reporting NUMP in the ACK TP based on the RX * FIFO space instead of reporting a fixed NUMP derived from DCFG.NUMP for non-control endpoints. */ #define USB3_CORE_GRXTHRCFG_USBRXPKTCNTSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GRXTHRCFG_USBRXPKTCNTSEL_SHIFT)) & USB3_CORE_GRXTHRCFG_USBRXPKTCNTSEL_MASK) /*! @} */ /*! @name GCTL - Global Core Control */ /*! @{ */ #define USB3_CORE_GCTL_DSBLCLKGTNG_MASK (0x1U) #define USB3_CORE_GCTL_DSBLCLKGTNG_SHIFT (0U) /*! DSBLCLKGTNG - Disable Clock Gating */ #define USB3_CORE_GCTL_DSBLCLKGTNG(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_DSBLCLKGTNG_SHIFT)) & USB3_CORE_GCTL_DSBLCLKGTNG_MASK) #define USB3_CORE_GCTL_GblHibernationEn_MASK (0x2U) #define USB3_CORE_GCTL_GblHibernationEn_SHIFT (1U) /*! GblHibernationEn - Global Hibernation Enable */ #define USB3_CORE_GCTL_GblHibernationEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_GblHibernationEn_SHIFT)) & USB3_CORE_GCTL_GblHibernationEn_MASK) #define USB3_CORE_GCTL_U2EXIT_LFPS_MASK (0x4U) #define USB3_CORE_GCTL_U2EXIT_LFPS_SHIFT (2U) /*! U2EXIT_LFPS * 0b0..The link treats 248ns LFPS as a valid U2 exit. * 0b1..The link waits for 8 us of LFPS before it detects a valid U2 exit. */ #define USB3_CORE_GCTL_U2EXIT_LFPS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_U2EXIT_LFPS_SHIFT)) & USB3_CORE_GCTL_U2EXIT_LFPS_MASK) #define USB3_CORE_GCTL_DISSCRAMBLE_MASK (0x8U) #define USB3_CORE_GCTL_DISSCRAMBLE_SHIFT (3U) /*! DISSCRAMBLE - Disable Scrambling */ #define USB3_CORE_GCTL_DISSCRAMBLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_DISSCRAMBLE_SHIFT)) & USB3_CORE_GCTL_DISSCRAMBLE_MASK) #define USB3_CORE_GCTL_SCALEDOWN_MASK (0x30U) #define USB3_CORE_GCTL_SCALEDOWN_SHIFT (4U) /*! SCALEDOWN - Scale-Down Mode * 0b00..Disables all scale-downs. Actual timing values are used. * 0b01..In HS/FS/LS Modes: Enables scale-down of all timing values except Device mode suspend and resume. These * include Speed enumeration, and Host mode suspend and resume. In SS Mode: Enables scaled down SS timing * and repeat values including: (1) Number of TxEq training sequences reduce to 8; (2) LFPS polling burst time * reduce to 256 nS; (3) LFPS warm reset receive reduce to 30 us. * 0b10..In HS/FS/LS Modes: Enables scale-down of Device mode suspend and resume timing values only. In SS Mode: * No TxEq training sequences are sent. Overrides Bit 4. * 0b11..Enables bit 0 and bit 1 scale-down timing values. */ #define USB3_CORE_GCTL_SCALEDOWN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_SCALEDOWN_SHIFT)) & USB3_CORE_GCTL_SCALEDOWN_MASK) #define USB3_CORE_GCTL_RAMCLKSEL_MASK (0xC0U) #define USB3_CORE_GCTL_RAMCLKSEL_SHIFT (6U) /*! RAMCLKSEL - RAM Clock Select * 0b00..Bus clock * 0b01..Pipe clock (Only used in device mode) * 0b10..In device mode , pipe/2 clock. In host mode, controller switches ram_clk between pipe/2 clock, mac2_clk * and bus_clk based on the status of the U2/U3 ports * 0b11..In device mode, selects mac2_clk as ram_clk (when 8-bit UTMI or ULPI used. Not supported in 16-bit UTMI * mode). In host mode, controller switches ram_clk between pipe_clk, mac2_clk and bus_clk based on the * status of the U2/U3 ports */ #define USB3_CORE_GCTL_RAMCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_RAMCLKSEL_SHIFT)) & USB3_CORE_GCTL_RAMCLKSEL_MASK) #define USB3_CORE_GCTL_DEBUGATTACH_MASK (0x100U) #define USB3_CORE_GCTL_DEBUGATTACH_SHIFT (8U) /*! DEBUGATTACH - Debug Attach */ #define USB3_CORE_GCTL_DEBUGATTACH(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_DEBUGATTACH_SHIFT)) & USB3_CORE_GCTL_DEBUGATTACH_MASK) #define USB3_CORE_GCTL_U1U2TimerScale_MASK (0x200U) #define USB3_CORE_GCTL_U1U2TimerScale_SHIFT (9U) /*! U1U2TimerScale - Disable U1/U2 timer Scaledown */ #define USB3_CORE_GCTL_U1U2TimerScale(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_U1U2TimerScale_SHIFT)) & USB3_CORE_GCTL_U1U2TimerScale_MASK) #define USB3_CORE_GCTL_SOFITPSYNC_MASK (0x400U) #define USB3_CORE_GCTL_SOFITPSYNC_SHIFT (10U) #define USB3_CORE_GCTL_SOFITPSYNC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_SOFITPSYNC_SHIFT)) & USB3_CORE_GCTL_SOFITPSYNC_MASK) #define USB3_CORE_GCTL_CORESOFTRESET_MASK (0x800U) #define USB3_CORE_GCTL_CORESOFTRESET_SHIFT (11U) /*! CORESOFTRESET - Core Soft Reset * 0b0..No soft reset * 0b1..Soft reset to core */ #define USB3_CORE_GCTL_CORESOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_CORESOFTRESET_SHIFT)) & USB3_CORE_GCTL_CORESOFTRESET_MASK) #define USB3_CORE_GCTL_PRTCAPDIR_MASK (0x3000U) #define USB3_CORE_GCTL_PRTCAPDIR_SHIFT (12U) /*! PRTCAPDIR - Port Capability Direction * 0b01..For Host configurations * 0b10..For Device configurations */ #define USB3_CORE_GCTL_PRTCAPDIR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_PRTCAPDIR_SHIFT)) & USB3_CORE_GCTL_PRTCAPDIR_MASK) #define USB3_CORE_GCTL_FRMSCLDWN_MASK (0xC000U) #define USB3_CORE_GCTL_FRMSCLDWN_SHIFT (14U) /*! FRMSCLDWN * 0b00..For SS/HS mode, implements interval to be 125 us. If DWC_USB3_EN_DBC = 1, scales down the MaxPacketSize to 1024 bytes * 0b01..For SS/HS mode, implements interval to be 62.5 us. If DWC_USB3_EN_DBC = 1, scales down the MaxPacketSize to 512 bytes * 0b10..For SS/HS mode, implements interval to be 31.25 us. If DWC_USB3_EN_DBC = 1, scales down the MaxPacketSize to 256 bytes * 0b11..For SS/HS mode, implements interval to be 15.625 us. If DWC_USB3_EN_DBC = 1, scales down the MaxPacketSize to 128 bytes */ #define USB3_CORE_GCTL_FRMSCLDWN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_FRMSCLDWN_SHIFT)) & USB3_CORE_GCTL_FRMSCLDWN_MASK) #define USB3_CORE_GCTL_U2RSTECN_MASK (0x10000U) #define USB3_CORE_GCTL_U2RSTECN_SHIFT (16U) #define USB3_CORE_GCTL_U2RSTECN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_U2RSTECN_SHIFT)) & USB3_CORE_GCTL_U2RSTECN_MASK) #define USB3_CORE_GCTL_BYPSSETADDR_MASK (0x20000U) #define USB3_CORE_GCTL_BYPSSETADDR_SHIFT (17U) /*! BYPSSETADDR - Bypass SetAddress In Device Mode */ #define USB3_CORE_GCTL_BYPSSETADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_BYPSSETADDR_SHIFT)) & USB3_CORE_GCTL_BYPSSETADDR_MASK) #define USB3_CORE_GCTL_MASTERFILTBYPASS_MASK (0x40000U) #define USB3_CORE_GCTL_MASTERFILTBYPASS_SHIFT (18U) /*! MASTERFILTBYPASS - Master Filter Bypass */ #define USB3_CORE_GCTL_MASTERFILTBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_MASTERFILTBYPASS_SHIFT)) & USB3_CORE_GCTL_MASTERFILTBYPASS_MASK) #define USB3_CORE_GCTL_PWRDNSCALE_MASK (0xFFF80000U) #define USB3_CORE_GCTL_PWRDNSCALE_SHIFT (19U) /*! PWRDNSCALE - Power Down Scale */ #define USB3_CORE_GCTL_PWRDNSCALE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GCTL_PWRDNSCALE_SHIFT)) & USB3_CORE_GCTL_PWRDNSCALE_MASK) /*! @} */ /*! @name GSTS - Global Status */ /*! @{ */ #define USB3_CORE_GSTS_CURMOD_MASK (0x3U) #define USB3_CORE_GSTS_CURMOD_SHIFT (0U) /*! CURMOD - Current Mode of Operation * 0b00..Device mode * 0b01..Host mode */ #define USB3_CORE_GSTS_CURMOD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_CURMOD_SHIFT)) & USB3_CORE_GSTS_CURMOD_MASK) #define USB3_CORE_GSTS_BUSERRADDRVLD_MASK (0x10U) #define USB3_CORE_GSTS_BUSERRADDRVLD_SHIFT (4U) /*! BUSERRADDRVLD - Bus Error Address Valid */ #define USB3_CORE_GSTS_BUSERRADDRVLD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_BUSERRADDRVLD_SHIFT)) & USB3_CORE_GSTS_BUSERRADDRVLD_MASK) #define USB3_CORE_GSTS_CSRTimeout_MASK (0x20U) #define USB3_CORE_GSTS_CSRTimeout_SHIFT (5U) /*! CSRTimeout - CSR Timeout */ #define USB3_CORE_GSTS_CSRTimeout(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_CSRTimeout_SHIFT)) & USB3_CORE_GSTS_CSRTimeout_MASK) #define USB3_CORE_GSTS_Device_IP_MASK (0x40U) #define USB3_CORE_GSTS_Device_IP_SHIFT (6U) /*! Device_IP - Device Interrupt Pending */ #define USB3_CORE_GSTS_Device_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_Device_IP_SHIFT)) & USB3_CORE_GSTS_Device_IP_MASK) #define USB3_CORE_GSTS_Host_IP_MASK (0x80U) #define USB3_CORE_GSTS_Host_IP_SHIFT (7U) /*! Host_IP - Host Interrupt Pending */ #define USB3_CORE_GSTS_Host_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_Host_IP_SHIFT)) & USB3_CORE_GSTS_Host_IP_MASK) #define USB3_CORE_GSTS_BC_IP_MASK (0x200U) #define USB3_CORE_GSTS_BC_IP_SHIFT (9U) /*! BC_IP - Battery Charger Interrupt Pending */ #define USB3_CORE_GSTS_BC_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_BC_IP_SHIFT)) & USB3_CORE_GSTS_BC_IP_MASK) #define USB3_CORE_GSTS_SSIC_IP_MASK (0x800U) #define USB3_CORE_GSTS_SSIC_IP_SHIFT (11U) /*! SSIC_IP - SSIC Interrupt Pending */ #define USB3_CORE_GSTS_SSIC_IP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_SSIC_IP_SHIFT)) & USB3_CORE_GSTS_SSIC_IP_MASK) #define USB3_CORE_GSTS_CBELT_MASK (0xFFF00000U) #define USB3_CORE_GSTS_CBELT_SHIFT (20U) /*! CBELT - Current BELT Value */ #define USB3_CORE_GSTS_CBELT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GSTS_CBELT_SHIFT)) & USB3_CORE_GSTS_CBELT_MASK) /*! @} */ /*! @name GUCTL1 - Global User Control 1 */ /*! @{ */ #define USB3_CORE_GUCTL1_LOA_FILTER_EN_MASK (0x1U) #define USB3_CORE_GUCTL1_LOA_FILTER_EN_SHIFT (0U) #define USB3_CORE_GUCTL1_LOA_FILTER_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_LOA_FILTER_EN_SHIFT)) & USB3_CORE_GUCTL1_LOA_FILTER_EN_MASK) #define USB3_CORE_GUCTL1_OVRLD_L1_SUSP_COM_MASK (0x2U) #define USB3_CORE_GUCTL1_OVRLD_L1_SUSP_COM_SHIFT (1U) #define USB3_CORE_GUCTL1_OVRLD_L1_SUSP_COM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_OVRLD_L1_SUSP_COM_SHIFT)) & USB3_CORE_GUCTL1_OVRLD_L1_SUSP_COM_MASK) #define USB3_CORE_GUCTL1_HC_PARCHK_DISABLE_MASK (0x4U) #define USB3_CORE_GUCTL1_HC_PARCHK_DISABLE_SHIFT (2U) /*! HC_PARCHK_DISABLE - Host Parameter Check Disable */ #define USB3_CORE_GUCTL1_HC_PARCHK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_HC_PARCHK_DISABLE_SHIFT)) & USB3_CORE_GUCTL1_HC_PARCHK_DISABLE_MASK) #define USB3_CORE_GUCTL1_HC_ERRATA_ENABLE_MASK (0x8U) #define USB3_CORE_GUCTL1_HC_ERRATA_ENABLE_SHIFT (3U) /*! HC_ERRATA_ENABLE - Host ELD Enable */ #define USB3_CORE_GUCTL1_HC_ERRATA_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_HC_ERRATA_ENABLE_SHIFT)) & USB3_CORE_GUCTL1_HC_ERRATA_ENABLE_MASK) #define USB3_CORE_GUCTL1_L1_SUSP_THRLD_FOR_HOST_MASK (0xF0U) #define USB3_CORE_GUCTL1_L1_SUSP_THRLD_FOR_HOST_SHIFT (4U) #define USB3_CORE_GUCTL1_L1_SUSP_THRLD_FOR_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_L1_SUSP_THRLD_FOR_HOST_SHIFT)) & USB3_CORE_GUCTL1_L1_SUSP_THRLD_FOR_HOST_MASK) #define USB3_CORE_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_MASK (0x100U) #define USB3_CORE_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_SHIFT (8U) #define USB3_CORE_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_SHIFT)) & USB3_CORE_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_MASK) #define USB3_CORE_GUCTL1_DEV_HS_NYET_BULK_SPR_MASK (0x200U) #define USB3_CORE_GUCTL1_DEV_HS_NYET_BULK_SPR_SHIFT (9U) /*! DEV_HS_NYET_BULK_SPR * 0b0..Default behavior, no change in device response * 0b1..Feature enabled, HS bulk OUT short packet gets NYET response */ #define USB3_CORE_GUCTL1_DEV_HS_NYET_BULK_SPR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DEV_HS_NYET_BULK_SPR_SHIFT)) & USB3_CORE_GUCTL1_DEV_HS_NYET_BULK_SPR_MASK) #define USB3_CORE_GUCTL1_RESUME_OPMODE_HS_HOST_MASK (0x400U) #define USB3_CORE_GUCTL1_RESUME_OPMODE_HS_HOST_SHIFT (10U) /*! RESUME_OPMODE_HS_HOST * 0b0..The UTMI/ULPI opmode will be changed to "normal" 2 us after HS terminations change after EOR. This is the default behavior. * 0b1..The UTMI/ULPI opmode will be changed to "normal" along with HS terminations after EOR. This option is to * support certain legacy UTMI/ULPI PHYs. */ #define USB3_CORE_GUCTL1_RESUME_OPMODE_HS_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_RESUME_OPMODE_HS_HOST_SHIFT)) & USB3_CORE_GUCTL1_RESUME_OPMODE_HS_HOST_MASK) #define USB3_CORE_GUCTL1_DISABLE_FIX_FOR_HANDLE_DATA_TOGGLE_ERR_MASK (0x4000U) #define USB3_CORE_GUCTL1_DISABLE_FIX_FOR_HANDLE_DATA_TOGGLE_ERR_SHIFT (14U) /*! DISABLE_FIX_FOR_HANDLE_DATA_TOGGLE_ERR - Disable Fix for Handle Data Toggle Error * 0b0..Fix applied (default) * 0b1..Fix disabled */ #define USB3_CORE_GUCTL1_DISABLE_FIX_FOR_HANDLE_DATA_TOGGLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DISABLE_FIX_FOR_HANDLE_DATA_TOGGLE_ERR_SHIFT)) & USB3_CORE_GUCTL1_DISABLE_FIX_FOR_HANDLE_DATA_TOGGLE_ERR_MASK) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_FSLS_MASK (0x8000U) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_FSLS_SHIFT (15U) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_FSLS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_PARKMODE_DISABLE_FSLS_SHIFT)) & USB3_CORE_GUCTL1_PARKMODE_DISABLE_FSLS_MASK) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_HS_MASK (0x10000U) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_HS_SHIFT (16U) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_HS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_PARKMODE_DISABLE_HS_SHIFT)) & USB3_CORE_GUCTL1_PARKMODE_DISABLE_HS_MASK) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_SS_MASK (0x20000U) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_SS_SHIFT (17U) #define USB3_CORE_GUCTL1_PARKMODE_DISABLE_SS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_PARKMODE_DISABLE_SS_SHIFT)) & USB3_CORE_GUCTL1_PARKMODE_DISABLE_SS_MASK) #define USB3_CORE_GUCTL1_NAK_PER_ENH_HS_MASK (0x40000U) #define USB3_CORE_GUCTL1_NAK_PER_ENH_HS_SHIFT (18U) /*! NAK_PER_ENH_HS * 0b0..Enhancement not applied. If a periodic endpoint is present, and if a bulk endpoint which is also active * is being NAKed by the device, then this could result in decrease in performance of other High Speed bulk * endpoint which is ACked by the device. * 0b1..Enables performance enhancement for HS async endpoints in the presence of NAKs. */ #define USB3_CORE_GUCTL1_NAK_PER_ENH_HS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_NAK_PER_ENH_HS_SHIFT)) & USB3_CORE_GUCTL1_NAK_PER_ENH_HS_MASK) #define USB3_CORE_GUCTL1_NAK_PER_ENH_FS_MASK (0x80000U) #define USB3_CORE_GUCTL1_NAK_PER_ENH_FS_SHIFT (19U) /*! NAK_PER_ENH_FS * 0b0..Enhancement not applied. If a periodic endpoint is present , and if a bulk endpoint which is also active * is being NAKed by the device, then this could result in a decrease in performance of other Full Speed bulk * endpoint which is ACked by the device. * 0b1..Enables performance enhancement for FS async endpoints in the presence of NAKs. */ #define USB3_CORE_GUCTL1_NAK_PER_ENH_FS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_NAK_PER_ENH_FS_SHIFT)) & USB3_CORE_GUCTL1_NAK_PER_ENH_FS_MASK) #define USB3_CORE_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_MASK (0x100000U) #define USB3_CORE_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_SHIFT (20U) /*! DEV_LSP_TAIL_LOCK_DIS * 0b0..Default behavior, enables device lsp lock logic for tail TRB update * 0b1..Fix disabled */ #define USB3_CORE_GUCTL1_DEV_LSP_TAIL_LOCK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_SHIFT)) & USB3_CORE_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_MASK) #define USB3_CORE_GUCTL1_IP_GAP_ADD_ON_MASK (0xE00000U) #define USB3_CORE_GUCTL1_IP_GAP_ADD_ON_SHIFT (21U) #define USB3_CORE_GUCTL1_IP_GAP_ADD_ON(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_IP_GAP_ADD_ON_SHIFT)) & USB3_CORE_GUCTL1_IP_GAP_ADD_ON_MASK) #define USB3_CORE_GUCTL1_DEV_L1_EXIT_BY_HW_MASK (0x1000000U) #define USB3_CORE_GUCTL1_DEV_L1_EXIT_BY_HW_SHIFT (24U) /*! DEV_L1_EXIT_BY_HW * 0b0..Default behavior, disables device L1 hardware exit logic * 0b1..Feature enabled */ #define USB3_CORE_GUCTL1_DEV_L1_EXIT_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DEV_L1_EXIT_BY_HW_SHIFT)) & USB3_CORE_GUCTL1_DEV_L1_EXIT_BY_HW_MASK) #define USB3_CORE_GUCTL1_P3_IN_U2_MASK (0x2000000U) #define USB3_CORE_GUCTL1_P3_IN_U2_SHIFT (25U) /*! P3_IN_U2 * 0b0..Default behavior, When SuperSpeed link is in U2, PowerState P2 is attempted on the PIPE Interface. * 0b1..When SuperSpeed link is in U2, PowerState P3 is attempted if GUSB3PIPECTL[17] is set. */ #define USB3_CORE_GUCTL1_P3_IN_U2(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_P3_IN_U2_SHIFT)) & USB3_CORE_GUCTL1_P3_IN_U2_MASK) #define USB3_CORE_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_MASK (0x4000000U) #define USB3_CORE_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_SHIFT (26U) /*! DEV_FORCE_20_CLK_FOR_30_CLK * 0b0..Default behavior, uses 3.0 clock when operating in 2.0 mode * 0b1..Feature enabled */ #define USB3_CORE_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_SHIFT)) & USB3_CORE_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_MASK) #define USB3_CORE_GUCTL1_DEV_TRB_OUT_SPR_IND_MASK (0x8000000U) #define USB3_CORE_GUCTL1_DEV_TRB_OUT_SPR_IND_SHIFT (27U) /*! DEV_TRB_OUT_SPR_IND * 0b0..Default behavior, no change in TRB status dword * 0b1..Feature enabled, OUT TRB status indicates Short Packet */ #define USB3_CORE_GUCTL1_DEV_TRB_OUT_SPR_IND(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DEV_TRB_OUT_SPR_IND_SHIFT)) & USB3_CORE_GUCTL1_DEV_TRB_OUT_SPR_IND_MASK) #define USB3_CORE_GUCTL1_TX_IPGAP_LINECHECK_DIS_MASK (0x10000000U) #define USB3_CORE_GUCTL1_TX_IPGAP_LINECHECK_DIS_SHIFT (28U) /*! TX_IPGAP_LINECHECK_DIS * 0b0..Default behavior, no change in Linestate check * 0b1..Feature enabled, 2.0 MAC disables Linestate check during HS transmit */ #define USB3_CORE_GUCTL1_TX_IPGAP_LINECHECK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_TX_IPGAP_LINECHECK_DIS_SHIFT)) & USB3_CORE_GUCTL1_TX_IPGAP_LINECHECK_DIS_MASK) #define USB3_CORE_GUCTL1_FILTER_SE0_FSLS_EOP_MASK (0x20000000U) #define USB3_CORE_GUCTL1_FILTER_SE0_FSLS_EOP_SHIFT (29U) /*! FILTER_SE0_FSLS_EOP * 0b0..Default behavior, no change in Linestate check for SE0 detection in FS/LS * 0b1..Feature enabled, FS/LS SE0 is filtered for 2 clocks for detecting EOP */ #define USB3_CORE_GUCTL1_FILTER_SE0_FSLS_EOP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_FILTER_SE0_FSLS_EOP_SHIFT)) & USB3_CORE_GUCTL1_FILTER_SE0_FSLS_EOP_MASK) #define USB3_CORE_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_MASK (0x40000000U) #define USB3_CORE_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_SHIFT (30U) /*! DS_RXDET_MAX_TOUT_CTRL * 0b0..Default behavior; 12 ms is used as tRxDetectTimeoutDFP. * 0b1..120 ms is used as the tRxDetectTimeoutDFP. */ #define USB3_CORE_GUCTL1_DS_RXDET_MAX_TOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_SHIFT)) & USB3_CORE_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_MASK) #define USB3_CORE_GUCTL1_DEV_DECOUPLE_L1L2_EVT_MASK (0x80000000U) #define USB3_CORE_GUCTL1_DEV_DECOUPLE_L1L2_EVT_SHIFT (31U) /*! DEV_DECOUPLE_L1L2_EVT * 0b0..Default behavior, no change in device events L1/L2U3 events are not decoupled (old behavior of v2.90a and before) * 0b1..Feature enabled, L1 and L2 events are separated when operating in 2.0 mode. Separate event enable bits for L1 suspend and wake events */ #define USB3_CORE_GUCTL1_DEV_DECOUPLE_L1L2_EVT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL1_DEV_DECOUPLE_L1L2_EVT_SHIFT)) & USB3_CORE_GUCTL1_DEV_DECOUPLE_L1L2_EVT_MASK) /*! @} */ /*! @name GUID - Global User ID */ /*! @{ */ #define USB3_CORE_GUID_USERID_MASK (0xFFFFFFFFU) #define USB3_CORE_GUID_USERID_SHIFT (0U) /*! USERID - User ID */ #define USB3_CORE_GUID_USERID(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUID_USERID_SHIFT)) & USB3_CORE_GUID_USERID_MASK) /*! @} */ /*! @name GUCTL - Global User Control */ /*! @{ */ #define USB3_CORE_GUCTL_DTFT_MASK (0x1FFU) #define USB3_CORE_GUCTL_DTFT_SHIFT (0U) /*! DTFT - Device Timeout Fine Tuning * 0b000000010..2*256*8 = 4 us timeout * 0b000000101..5*256*8 = 10 us timeout * 0b000001010..10*256*8 = 20 us timeout * 0b000010000..16*256*8 = 32 us timeout * 0b000011001..25*256*8 = 51 us timeout * 0b000110001..49*256*8 = 100 us timeout * 0b001100010..98*256*8 = 200 us timeout */ #define USB3_CORE_GUCTL_DTFT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_DTFT_SHIFT)) & USB3_CORE_GUCTL_DTFT_MASK) #define USB3_CORE_GUCTL_DTCT_MASK (0x600U) #define USB3_CORE_GUCTL_DTCT_SHIFT (9U) /*! DTCT - Device Timeout Coarse Tuning * 0b00..0 us -> use DTFT value instead * 0b01..500 us * 0b10..1.5 ms * 0b11..6.5 ms */ #define USB3_CORE_GUCTL_DTCT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_DTCT_SHIFT)) & USB3_CORE_GUCTL_DTCT_MASK) #define USB3_CORE_GUCTL_InsrtExtrFSBODI_MASK (0x800U) #define USB3_CORE_GUCTL_InsrtExtrFSBODI_SHIFT (11U) /*! InsrtExtrFSBODI - Insert Extra Delay Between FS Bulk OUT Transactions * 0b0..Host doesn't insert extra delay between consecutive Bulk OUT transactions to a FS Endpoint. * 0b1..Host inserts about 12 us extra delay between consecutive Bulk OUT transactions to a FS Endpoint to work around the device issue. */ #define USB3_CORE_GUCTL_InsrtExtrFSBODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_InsrtExtrFSBODI_SHIFT)) & USB3_CORE_GUCTL_InsrtExtrFSBODI_MASK) #define USB3_CORE_GUCTL_ExtCapSupptEN_MASK (0x1000U) #define USB3_CORE_GUCTL_ExtCapSupptEN_SHIFT (12U) /*! ExtCapSupptEN - External Extended Capability Support Enable */ #define USB3_CORE_GUCTL_ExtCapSupptEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_ExtCapSupptEN_SHIFT)) & USB3_CORE_GUCTL_ExtCapSupptEN_MASK) #define USB3_CORE_GUCTL_EnOverlapChk_MASK (0x2000U) #define USB3_CORE_GUCTL_EnOverlapChk_SHIFT (13U) /*! EnOverlapChk - Enable Check for LFPS Overlap During Remote Ux Exit * 0b0..When the link exists U1/U2/U3 because of a remote exit, it does not look for an LFPS overlap. * 0b1..The SuperSpeed link when exiting U1/U2/U3 waits for either the remote link LFPS or TS1/TS2 training * symbols before it confirms that the LFPS handshake is complete. This is done to handle the case where the LFPS * glitch causes the link to start exiting from the low power state. Looking for the LFPS overlap makes sure * that the link partner also sees the LFPS. */ #define USB3_CORE_GUCTL_EnOverlapChk(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_EnOverlapChk_SHIFT)) & USB3_CORE_GUCTL_EnOverlapChk_MASK) #define USB3_CORE_GUCTL_USBHstInAutoRetryEn_MASK (0x4000U) #define USB3_CORE_GUCTL_USBHstInAutoRetryEn_SHIFT (14U) /*! USBHstInAutoRetryEn - Host IN Auto Retry * 0b0..Auto retry disabled * 0b1..Auto retry enabled. Note: When enabling Auto Retry feature, if the system latency is large enough to * cause the internal PSQ full (PSQ can be full as the result of messages not being processed because of pending * fetches before flushing the TxQ due to NRDY/ERDY conditions), then the host controller can generate a * transaction error. */ #define USB3_CORE_GUCTL_USBHstInAutoRetryEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_USBHstInAutoRetryEn_SHIFT)) & USB3_CORE_GUCTL_USBHstInAutoRetryEn_MASK) #define USB3_CORE_GUCTL_ResBwHSEPS_MASK (0x10000U) #define USB3_CORE_GUCTL_ResBwHSEPS_SHIFT (16U) /*! ResBwHSEPS - Reserving 85% Bandwidth For HS Periodic EPs */ #define USB3_CORE_GUCTL_ResBwHSEPS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_ResBwHSEPS_SHIFT)) & USB3_CORE_GUCTL_ResBwHSEPS_MASK) #define USB3_CORE_GUCTL_SprsCtrlTransEn_MASK (0x20000U) #define USB3_CORE_GUCTL_SprsCtrlTransEn_SHIFT (17U) /*! SprsCtrlTransEn - Sparse Control Transaction Enable */ #define USB3_CORE_GUCTL_SprsCtrlTransEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_SprsCtrlTransEn_SHIFT)) & USB3_CORE_GUCTL_SprsCtrlTransEn_MASK) #define USB3_CORE_GUCTL_NoExtrDl_MASK (0x200000U) #define USB3_CORE_GUCTL_NoExtrDl_SHIFT (21U) /*! NoExtrDl - No Extra Delay Between SOF And The First Packet * 0b0..Host waits for 2 microseconds after a SOF before it sends the first USB packet. * 0b1..Host doesn't wait after a SOF before it sends the first USB packet. */ #define USB3_CORE_GUCTL_NoExtrDl(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_NoExtrDl_SHIFT)) & USB3_CORE_GUCTL_NoExtrDl_MASK) #define USB3_CORE_GUCTL_REFCLKPER_MASK (0xFFC00000U) #define USB3_CORE_GUCTL_REFCLKPER_SHIFT (22U) #define USB3_CORE_GUCTL_REFCLKPER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL_REFCLKPER_SHIFT)) & USB3_CORE_GUCTL_REFCLKPER_MASK) /*! @} */ /*! @name GBUSERRADDRLO - Global SoC Bus Error Address - Low */ /*! @{ */ #define USB3_CORE_GBUSERRADDRLO_BUSERRADDR_MASK (0xFFFFFFFFU) #define USB3_CORE_GBUSERRADDRLO_BUSERRADDR_SHIFT (0U) /*! BUSERRADDR - Bus Address - Low */ #define USB3_CORE_GBUSERRADDRLO_BUSERRADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GBUSERRADDRLO_BUSERRADDR_SHIFT)) & USB3_CORE_GBUSERRADDRLO_BUSERRADDR_MASK) /*! @} */ /*! @name GBUSERRADDRHI - Global SoC Bus Error Address - High */ /*! @{ */ #define USB3_CORE_GBUSERRADDRHI_BUSERRADDR_MASK (0xFFFFFFFFU) #define USB3_CORE_GBUSERRADDRHI_BUSERRADDR_SHIFT (0U) /*! BUSERRADDR - Bus Address - High */ #define USB3_CORE_GBUSERRADDRHI_BUSERRADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GBUSERRADDRHI_BUSERRADDR_SHIFT)) & USB3_CORE_GBUSERRADDRHI_BUSERRADDR_MASK) /*! @} */ /*! @name GPRTBIMAPLO - Global SS Port to Bus Instance Mapping - Low */ /*! @{ */ #define USB3_CORE_GPRTBIMAPLO_BINUM1_MASK (0xFU) #define USB3_CORE_GPRTBIMAPLO_BINUM1_SHIFT (0U) /*! BINUM1 - SS USB Instance Number for Port 1 */ #define USB3_CORE_GPRTBIMAPLO_BINUM1(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GPRTBIMAPLO_BINUM1_SHIFT)) & USB3_CORE_GPRTBIMAPLO_BINUM1_MASK) /*! @} */ /*! @name GHWPARAMS0 - Global Hardware Parameters 0 */ /*! @{ */ #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_2_0_MASK (0x7U) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_2_0_SHIFT (0U) /*! GHWPARAMS0_2_0 - DWC_USB3_MODE */ #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_2_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS0_GHWPARAMS0_2_0_SHIFT)) & USB3_CORE_GHWPARAMS0_GHWPARAMS0_2_0_MASK) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_5_3_MASK (0x38U) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_5_3_SHIFT (3U) /*! GHWPARAMS0_5_3 - DWC_USB3_MBUS_TYPE */ #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_5_3(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS0_GHWPARAMS0_5_3_SHIFT)) & USB3_CORE_GHWPARAMS0_GHWPARAMS0_5_3_MASK) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_7_6_MASK (0xC0U) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_7_6_SHIFT (6U) /*! GHWPARAMS0_7_6 - DWC_USB3_SBUS_TYPE */ #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_7_6(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS0_GHWPARAMS0_7_6_SHIFT)) & USB3_CORE_GHWPARAMS0_GHWPARAMS0_7_6_MASK) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_15_8_MASK (0xFF00U) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_15_8_SHIFT (8U) /*! GHWPARAMS0_15_8 - DWC_USB3_MDWIDTH */ #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_15_8(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS0_GHWPARAMS0_15_8_SHIFT)) & USB3_CORE_GHWPARAMS0_GHWPARAMS0_15_8_MASK) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_23_16_MASK (0xFF0000U) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_23_16_SHIFT (16U) /*! GHWPARAMS0_23_16 - DWC_USB3_SDWIDTH */ #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_23_16(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS0_GHWPARAMS0_23_16_SHIFT)) & USB3_CORE_GHWPARAMS0_GHWPARAMS0_23_16_MASK) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_31_24_MASK (0xFF000000U) #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_31_24_SHIFT (24U) /*! GHWPARAMS0_31_24 - DWC_USB3_AWIDTH */ #define USB3_CORE_GHWPARAMS0_GHWPARAMS0_31_24(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS0_GHWPARAMS0_31_24_SHIFT)) & USB3_CORE_GHWPARAMS0_GHWPARAMS0_31_24_MASK) /*! @} */ /*! @name GHWPARAMS1 - Global Hardware Parameters 1 */ /*! @{ */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_2_0_MASK (0x7U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_2_0_SHIFT (0U) /*! GHWPARAMS1_2_0 - DWC_USB3_IDWIDTH-1 */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_2_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_2_0_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_2_0_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_5_3_MASK (0x38U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_5_3_SHIFT (3U) /*! GHWPARAMS1_5_3 - DWC_USB3_BURSTWIDTH-1 */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_5_3(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_5_3_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_5_3_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_8_6_MASK (0x1C0U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_8_6_SHIFT (6U) /*! GHWPARAMS1_8_6 - DWC_USB3_DATAINFOWIDTH */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_8_6(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_8_6_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_8_6_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_11_9_MASK (0xE00U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_11_9_SHIFT (9U) /*! GHWPARAMS1_11_9 - DWC_USB3_REQINFOWIDTH */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_11_9(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_11_9_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_11_9_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_14_12_MASK (0x7000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_14_12_SHIFT (12U) /*! GHWPARAMS1_14_12 - DWC_USB3_ASPACEWIDTH */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_14_12(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_14_12_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_14_12_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_20_15_MASK (0x1F8000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_20_15_SHIFT (15U) /*! GHWPARAMS1_20_15 - DWC_USB3_DEVICE_NUM_INT */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_20_15(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_20_15_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_20_15_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_22_21_MASK (0x600000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_22_21_SHIFT (21U) /*! GHWPARAMS1_22_21 - DWC_USB3_NUM_RAMS */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_22_21(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_22_21_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_22_21_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_23_MASK (0x800000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_23_SHIFT (23U) /*! GHWPARAMS1_23 - DWC_USB3_SPRAM_TYP */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_23(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_23_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_23_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_25_24_MASK (0x3000000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_25_24_SHIFT (24U) /*! GHWPARAMS1_25_24 - DWC_USB3_EN_PWROPT */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_25_24(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_25_24_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_25_24_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_26_MASK (0x4000000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_26_SHIFT (26U) /*! GHWPARAMS1_26 - DWC_USB3_MAC_PHY_CLKS_SYNC */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_26(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_26_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_26_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_27_MASK (0x8000000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_27_SHIFT (27U) /*! GHWPARAMS1_27 - DWC_USB3_MAC_RAM_CLKS_SYNC */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_27(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_27_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_27_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_28_MASK (0x10000000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_28_SHIFT (28U) /*! GHWPARAMS1_28 - DWC_USB3_RAM_BUS_CLKS_SYNC */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_28(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_28_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_28_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_29_MASK (0x20000000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_29_SHIFT (29U) /*! GHWPARAMS1_29 - Reserved */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_29(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_29_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_29_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_30_MASK (0x40000000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_30_SHIFT (30U) /*! GHWPARAMS1_30 - DWC_USB3_RM_OPT_FEATURES */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_30(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_30_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_30_MASK) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_31_MASK (0x80000000U) #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_31_SHIFT (31U) /*! GHWPARAMS1_31 - DWC_USB3_EN_DBC */ #define USB3_CORE_GHWPARAMS1_GHWPARAMS1_31(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS1_GHWPARAMS1_31_SHIFT)) & USB3_CORE_GHWPARAMS1_GHWPARAMS1_31_MASK) /*! @} */ /*! @name GHWPARAMS2 - Global Hardware Parameters 2 */ /*! @{ */ #define USB3_CORE_GHWPARAMS2_GHWPARAMS2_31_0_MASK (0xFFFFFFFFU) #define USB3_CORE_GHWPARAMS2_GHWPARAMS2_31_0_SHIFT (0U) /*! GHWPARAMS2_31_0 - DWC_USB3_USERID */ #define USB3_CORE_GHWPARAMS2_GHWPARAMS2_31_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS2_GHWPARAMS2_31_0_SHIFT)) & USB3_CORE_GHWPARAMS2_GHWPARAMS2_31_0_MASK) /*! @} */ /*! @name GHWPARAMS3 - Global Hardware Parameters 3 */ /*! @{ */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_1_0_MASK (0x3U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_1_0_SHIFT (0U) /*! GHWPARAMS3_1_0 - DWC_USB3_SSPHY_INTERFACE */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_1_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_1_0_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_1_0_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_3_2_MASK (0xCU) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_3_2_SHIFT (2U) /*! GHWPARAMS3_3_2 - DWC_USB3_HSPHY_INTERFACE */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_3_2(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_3_2_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_3_2_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_5_4_MASK (0x30U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_5_4_SHIFT (4U) /*! GHWPARAMS3_5_4 - DWC_USB3_FSPHY_INTERFACE */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_5_4(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_5_4_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_5_4_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_7_6_MASK (0xC0U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_7_6_SHIFT (6U) /*! GHWPARAMS3_7_6 - DWC_USB3_HSPHY_DWIDTH */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_7_6(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_7_6_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_7_6_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_10_MASK (0x400U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_10_SHIFT (10U) /*! GHWPARAMS3_10 - DWC_USB3_VENDOR_CTL_INTERFACE */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_10(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_10_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_10_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_11_MASK (0x800U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_11_SHIFT (11U) /*! GHWPARAMS3_11 - DWC_USB3_ULPI_CARKIT */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_11(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_11_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_11_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_17_12_MASK (0x3F000U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_17_12_SHIFT (12U) /*! GHWPARAMS3_17_12 - DWC_USB3_NUM_EPS */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_17_12(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_17_12_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_17_12_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_22_18_MASK (0x7C0000U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_22_18_SHIFT (18U) /*! GHWPARAMS3_22_18 - DWC_USB3_NUM_IN_EPS */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_22_18(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_22_18_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_22_18_MASK) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_30_23_MASK (0x7F800000U) #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_30_23_SHIFT (23U) /*! GHWPARAMS3_30_23 - DWC_USB3_CACHE_TOTAL_XFER_RESOURCES */ #define USB3_CORE_GHWPARAMS3_GHWPARAMS3_30_23(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS3_GHWPARAMS3_30_23_SHIFT)) & USB3_CORE_GHWPARAMS3_GHWPARAMS3_30_23_MASK) /*! @} */ /*! @name GHWPARAMS4 - Global Hardware Parameters 4 */ /*! @{ */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_5_0_MASK (0x3FU) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_5_0_SHIFT (0U) /*! GHWPARAMS4_5_0 - DWC_USB3_CACHE_TRBS_PER_TRANSFER */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_5_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_5_0_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_5_0_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_8_7_MASK (0x180U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_8_7_SHIFT (7U) /*! GHWPARAMS4_8_7 - DWC_USB3_NUM_SSIC_NUM_LANE * 0b00..4 lanes * 0b01..1 lane * 0b10..2 lanes * 0b11..Reserved */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_8_7(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_8_7_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_8_7_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_10_9_MASK (0x600U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_10_9_SHIFT (9U) /*! GHWPARAMS4_10_9 - DWC_USB3_SSIC_GEAR * 0b00..Reserved * 0b01..HS-G1 * 0b10..HS-G2 * 0b11..HS-G3 */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_10_9(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_10_9_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_10_9_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_11_MASK (0x800U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_11_SHIFT (11U) /*! GHWPARAMS4_11 - DWC_USB3_SSIC_NON_SNPS_MPHY * 0b0..M-PHY * 0b1..Third-party M-PHY */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_11(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_11_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_11_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_12_MASK (0x1000U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_12_SHIFT (12U) /*! GHWPARAMS4_12 - DWC_USB3_EN_SSIC * 0b0..If DWC_USB3_EN_SSIC == 0 * 0b1..If DWC_USB3_EN_SSIC != 0 */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_12(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_12_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_12_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_16_13_MASK (0x1E000U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_16_13_SHIFT (13U) /*! GHWPARAMS4_16_13 - DWC_USB3_HIBER_SCRATCHBUFS */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_16_13(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_16_13_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_16_13_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_20_17_MASK (0x1E0000U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_20_17_SHIFT (17U) /*! GHWPARAMS4_20_17 - DWC_USB3_NUM_SS_USB_INSTANCES */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_20_17(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_20_17_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_20_17_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_21_MASK (0x200000U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_21_SHIFT (21U) /*! GHWPARAMS4_21 - DWC_USB3_EXT_BUFF_CONTROL */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_21(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_21_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_21_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_23_MASK (0x800000U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_23_SHIFT (23U) /*! GHWPARAMS4_23 - DWC_USB3_EN_ISOC_SUPT */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_23(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_23_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_23_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_27_24_MASK (0xF000000U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_27_24_SHIFT (24U) /*! GHWPARAMS4_27_24 - DWC_USB3_BMU_PTL_DEPTH-1 */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_27_24(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_27_24_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_27_24_MASK) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_31_28_MASK (0xF0000000U) #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_31_28_SHIFT (28U) /*! GHWPARAMS4_31_28 - DWC_USB3_BMU_LSP_DEPTH */ #define USB3_CORE_GHWPARAMS4_GHWPARAMS4_31_28(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS4_GHWPARAMS4_31_28_SHIFT)) & USB3_CORE_GHWPARAMS4_GHWPARAMS4_31_28_MASK) /*! @} */ /*! @name GHWPARAMS5 - Global Hardware Parameters 5 */ /*! @{ */ #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_3_0_MASK (0xFU) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_3_0_SHIFT (0U) /*! GHWPARAMS5_3_0 - DWC_USB3_BMU_BUSGM_DEPTH */ #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_3_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS5_GHWPARAMS5_3_0_SHIFT)) & USB3_CORE_GHWPARAMS5_GHWPARAMS5_3_0_MASK) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_9_4_MASK (0x3F0U) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_9_4_SHIFT (4U) /*! GHWPARAMS5_9_4 - DWC_USB3_RXQ_FIFO_DEPTH */ #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_9_4(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS5_GHWPARAMS5_9_4_SHIFT)) & USB3_CORE_GHWPARAMS5_GHWPARAMS5_9_4_MASK) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_15_10_MASK (0xFC00U) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_15_10_SHIFT (10U) /*! GHWPARAMS5_15_10 - DWC_USB3_TXQ_FIFO_DEPTH */ #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_15_10(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS5_GHWPARAMS5_15_10_SHIFT)) & USB3_CORE_GHWPARAMS5_GHWPARAMS5_15_10_MASK) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_21_16_MASK (0x3F0000U) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_21_16_SHIFT (16U) /*! GHWPARAMS5_21_16 - DWC_USB3_DWQ_FIFO_DEPTH */ #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_21_16(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS5_GHWPARAMS5_21_16_SHIFT)) & USB3_CORE_GHWPARAMS5_GHWPARAMS5_21_16_MASK) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_27_22_MASK (0xFC00000U) #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_27_22_SHIFT (22U) /*! GHWPARAMS5_27_22 - DWC_USB3_DFQ_FIFO_DEPTH */ #define USB3_CORE_GHWPARAMS5_GHWPARAMS5_27_22(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS5_GHWPARAMS5_27_22_SHIFT)) & USB3_CORE_GHWPARAMS5_GHWPARAMS5_27_22_MASK) /*! @} */ /*! @name GHWPARAMS6 - Global Hardware Parameters 6 */ /*! @{ */ #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_5_0_MASK (0x3FU) #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_5_0_SHIFT (0U) /*! GHWPARAMS6_5_0 - DWC_USB3_PSQ_FIFO_DEPTH */ #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_5_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS6_GHWPARAMS6_5_0_SHIFT)) & USB3_CORE_GHWPARAMS6_GHWPARAMS6_5_0_MASK) #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_6_MASK (0x40U) #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_6_SHIFT (6U) /*! GHWPARAMS6_6 - DWC_USB3_EN_DBG_PORTS */ #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_6(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS6_GHWPARAMS6_6_SHIFT)) & USB3_CORE_GHWPARAMS6_GHWPARAMS6_6_MASK) #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_7_MASK (0x80U) #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_7_SHIFT (7U) /*! GHWPARAMS6_7 - DWC_USB3_EN_FPGA */ #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_7(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS6_GHWPARAMS6_7_SHIFT)) & USB3_CORE_GHWPARAMS6_GHWPARAMS6_7_MASK) #define USB3_CORE_GHWPARAMS6_BCSupport_MASK (0x4000U) #define USB3_CORE_GHWPARAMS6_BCSupport_SHIFT (14U) /*! BCSupport - DWC_USB3_EN_BC */ #define USB3_CORE_GHWPARAMS6_BCSupport(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS6_BCSupport_SHIFT)) & USB3_CORE_GHWPARAMS6_BCSupport_MASK) #define USB3_CORE_GHWPARAMS6_BUSFLTRSSUPPORT_MASK (0x8000U) #define USB3_CORE_GHWPARAMS6_BUSFLTRSSUPPORT_SHIFT (15U) /*! BUSFLTRSSUPPORT - DWC_USB3_EN_BUS_FILTERS */ #define USB3_CORE_GHWPARAMS6_BUSFLTRSSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS6_BUSFLTRSSUPPORT_SHIFT)) & USB3_CORE_GHWPARAMS6_BUSFLTRSSUPPORT_MASK) #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_31_16_MASK (0xFFFF0000U) #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_31_16_SHIFT (16U) /*! GHWPARAMS6_31_16 - DWC_USB3_RAM0_DEPTH */ #define USB3_CORE_GHWPARAMS6_GHWPARAMS6_31_16(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS6_GHWPARAMS6_31_16_SHIFT)) & USB3_CORE_GHWPARAMS6_GHWPARAMS6_31_16_MASK) /*! @} */ /*! @name GHWPARAMS7 - Global Hardware Parameters 7 */ /*! @{ */ #define USB3_CORE_GHWPARAMS7_GHWPARAMS7_15_0_MASK (0xFFFFU) #define USB3_CORE_GHWPARAMS7_GHWPARAMS7_15_0_SHIFT (0U) /*! GHWPARAMS7_15_0 - DWC_USB3_RAM1_DEPTH */ #define USB3_CORE_GHWPARAMS7_GHWPARAMS7_15_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS7_GHWPARAMS7_15_0_SHIFT)) & USB3_CORE_GHWPARAMS7_GHWPARAMS7_15_0_MASK) #define USB3_CORE_GHWPARAMS7_GHWPARAMS7_31_16_MASK (0xFFFF0000U) #define USB3_CORE_GHWPARAMS7_GHWPARAMS7_31_16_SHIFT (16U) /*! GHWPARAMS7_31_16 - DWC_USB3_RAM2_DEPTH */ #define USB3_CORE_GHWPARAMS7_GHWPARAMS7_31_16(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS7_GHWPARAMS7_31_16_SHIFT)) & USB3_CORE_GHWPARAMS7_GHWPARAMS7_31_16_MASK) /*! @} */ /*! @name GPRTBIMAP_HSLO - Global High-Speed Port to Bus Instance Mapping - Low */ /*! @{ */ #define USB3_CORE_GPRTBIMAP_HSLO_BINUM1_MASK (0xFU) #define USB3_CORE_GPRTBIMAP_HSLO_BINUM1_SHIFT (0U) /*! BINUM1 - HS USB Instance Number for Port 1 */ #define USB3_CORE_GPRTBIMAP_HSLO_BINUM1(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GPRTBIMAP_HSLO_BINUM1_SHIFT)) & USB3_CORE_GPRTBIMAP_HSLO_BINUM1_MASK) /*! @} */ /*! @name GPRTBIMAP_FSLO - Global Full-Speed Port to Bus Instance Mapping - Low */ /*! @{ */ #define USB3_CORE_GPRTBIMAP_FSLO_BINUM1_MASK (0xFU) #define USB3_CORE_GPRTBIMAP_FSLO_BINUM1_SHIFT (0U) /*! BINUM1 - FS USB Instance Number for Port 1 */ #define USB3_CORE_GPRTBIMAP_FSLO_BINUM1(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GPRTBIMAP_FSLO_BINUM1_SHIFT)) & USB3_CORE_GPRTBIMAP_FSLO_BINUM1_MASK) /*! @} */ /* The count of USB3_CORE_GERRINJCTL */ #define USB3_CORE_GERRINJCTL_COUNT (2U) /*! @name GUCTL2 - Global User Control 2 */ /*! @{ */ #define USB3_CORE_GUCTL2_TXPINGDURATION_MASK (0x1FU) #define USB3_CORE_GUCTL2_TXPINGDURATION_SHIFT (0U) /*! TXPINGDURATION - Transmit Ping Maximum Duration */ #define USB3_CORE_GUCTL2_TXPINGDURATION(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL2_TXPINGDURATION_SHIFT)) & USB3_CORE_GUCTL2_TXPINGDURATION_MASK) #define USB3_CORE_GUCTL2_RXPINGDURATION_MASK (0x7E0U) #define USB3_CORE_GUCTL2_RXPINGDURATION_SHIFT (5U) /*! RXPINGDURATION - Receive Ping Maximum Duration */ #define USB3_CORE_GUCTL2_RXPINGDURATION(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL2_RXPINGDURATION_SHIFT)) & USB3_CORE_GUCTL2_RXPINGDURATION_MASK) #define USB3_CORE_GUCTL2_DISABLECFC_MASK (0x800U) #define USB3_CORE_GUCTL2_DISABLECFC_SHIFT (11U) /*! DISABLECFC - Disable xHCI Errata Feature Contiguous Frame ID Capability */ #define USB3_CORE_GUCTL2_DISABLECFC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL2_DISABLECFC_SHIFT)) & USB3_CORE_GUCTL2_DISABLECFC_MASK) #define USB3_CORE_GUCTL2_ENABLEEPCACHEEVICT_MASK (0x1000U) #define USB3_CORE_GUCTL2_ENABLEEPCACHEEVICT_SHIFT (12U) /*! ENABLEEPCACHEEVICT - Enable Evicting Endpoint Cache After Flow Control For Bulk Endpoints */ #define USB3_CORE_GUCTL2_ENABLEEPCACHEEVICT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL2_ENABLEEPCACHEEVICT_SHIFT)) & USB3_CORE_GUCTL2_ENABLEEPCACHEEVICT_MASK) #define USB3_CORE_GUCTL2_RST_ACTBITLATER_MASK (0x4000U) #define USB3_CORE_GUCTL2_RST_ACTBITLATER_SHIFT (14U) #define USB3_CORE_GUCTL2_RST_ACTBITLATER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL2_RST_ACTBITLATER_SHIFT)) & USB3_CORE_GUCTL2_RST_ACTBITLATER_MASK) #define USB3_CORE_GUCTL2_NOLOWPWRDUR_MASK (0x78000U) #define USB3_CORE_GUCTL2_NOLOWPWRDUR_SHIFT (15U) /*! NOLOWPWRDUR - No Low Power Duration */ #define USB3_CORE_GUCTL2_NOLOWPWRDUR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL2_NOLOWPWRDUR_SHIFT)) & USB3_CORE_GUCTL2_NOLOWPWRDUR_MASK) #define USB3_CORE_GUCTL2_EN_HP_PM_TIMER_MASK (0x3F80000U) #define USB3_CORE_GUCTL2_EN_HP_PM_TIMER_SHIFT (19U) #define USB3_CORE_GUCTL2_EN_HP_PM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL2_EN_HP_PM_TIMER_SHIFT)) & USB3_CORE_GUCTL2_EN_HP_PM_TIMER_MASK) /*! @} */ /*! @name GUSB2PHYCFG - Global USB2 PHY Configuration */ /*! @{ */ #define USB3_CORE_GUSB2PHYCFG_TOutCal_MASK (0x7U) #define USB3_CORE_GUSB2PHYCFG_TOutCal_SHIFT (0U) /*! TOutCal - HS/FS Timeout Calibration */ #define USB3_CORE_GUSB2PHYCFG_TOutCal(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_TOutCal_SHIFT)) & USB3_CORE_GUSB2PHYCFG_TOutCal_MASK) #define USB3_CORE_GUSB2PHYCFG_PHYIF_MASK (0x8U) #define USB3_CORE_GUSB2PHYCFG_PHYIF_SHIFT (3U) /*! PHYIF - PHY Interface */ #define USB3_CORE_GUSB2PHYCFG_PHYIF(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_PHYIF_SHIFT)) & USB3_CORE_GUSB2PHYCFG_PHYIF_MASK) #define USB3_CORE_GUSB2PHYCFG_ULPI_UTMI_Sel_MASK (0x10U) #define USB3_CORE_GUSB2PHYCFG_ULPI_UTMI_Sel_SHIFT (4U) /*! ULPI_UTMI_Sel - ULPI or UTMI+ Select */ #define USB3_CORE_GUSB2PHYCFG_ULPI_UTMI_Sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_ULPI_UTMI_Sel_SHIFT)) & USB3_CORE_GUSB2PHYCFG_ULPI_UTMI_Sel_MASK) #define USB3_CORE_GUSB2PHYCFG_FSINTF_MASK (0x20U) #define USB3_CORE_GUSB2PHYCFG_FSINTF_SHIFT (5U) /*! FSINTF - Full-Speed Serial Interface Select */ #define USB3_CORE_GUSB2PHYCFG_FSINTF(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_FSINTF_SHIFT)) & USB3_CORE_GUSB2PHYCFG_FSINTF_MASK) #define USB3_CORE_GUSB2PHYCFG_SUSPENDUSB20_MASK (0x40U) #define USB3_CORE_GUSB2PHYCFG_SUSPENDUSB20_SHIFT (6U) /*! SUSPENDUSB20 - Suspend USB2.0 HS/FS/LS PHY */ #define USB3_CORE_GUSB2PHYCFG_SUSPENDUSB20(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_SUSPENDUSB20_SHIFT)) & USB3_CORE_GUSB2PHYCFG_SUSPENDUSB20_MASK) #define USB3_CORE_GUSB2PHYCFG_PHYSEL_MASK (0x80U) #define USB3_CORE_GUSB2PHYCFG_PHYSEL_SHIFT (7U) /*! PHYSEL - USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select */ #define USB3_CORE_GUSB2PHYCFG_PHYSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_PHYSEL_SHIFT)) & USB3_CORE_GUSB2PHYCFG_PHYSEL_MASK) #define USB3_CORE_GUSB2PHYCFG_ENBLSLPM_MASK (0x100U) #define USB3_CORE_GUSB2PHYCFG_ENBLSLPM_SHIFT (8U) /*! ENBLSLPM - Enable utmi_sleep_n and utmi_l1_suspend_ */ #define USB3_CORE_GUSB2PHYCFG_ENBLSLPM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_ENBLSLPM_SHIFT)) & USB3_CORE_GUSB2PHYCFG_ENBLSLPM_MASK) #define USB3_CORE_GUSB2PHYCFG_XCVRDLY_MASK (0x200U) #define USB3_CORE_GUSB2PHYCFG_XCVRDLY_SHIFT (9U) /*! XCVRDLY - Transceiver Delay */ #define USB3_CORE_GUSB2PHYCFG_XCVRDLY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_XCVRDLY_SHIFT)) & USB3_CORE_GUSB2PHYCFG_XCVRDLY_MASK) #define USB3_CORE_GUSB2PHYCFG_USBTRDTIM_MASK (0x3C00U) #define USB3_CORE_GUSB2PHYCFG_USBTRDTIM_SHIFT (10U) /*! USBTRDTIM - USB 2.0 Turnaround Time */ #define USB3_CORE_GUSB2PHYCFG_USBTRDTIM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_USBTRDTIM_SHIFT)) & USB3_CORE_GUSB2PHYCFG_USBTRDTIM_MASK) #define USB3_CORE_GUSB2PHYCFG_ULPIAUTORES_MASK (0x8000U) #define USB3_CORE_GUSB2PHYCFG_ULPIAUTORES_SHIFT (15U) /*! ULPIAUTORES - ULPI Auto Resume */ #define USB3_CORE_GUSB2PHYCFG_ULPIAUTORES(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_ULPIAUTORES_SHIFT)) & USB3_CORE_GUSB2PHYCFG_ULPIAUTORES_MASK) #define USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK (0x20000U) #define USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT (17U) /*! ULPIEXTVBUSDRV - ULPI External VBUS Drive */ #define USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSDRV(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT)) & USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK) #define USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_MASK (0x40000U) #define USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHIFT (18U) /*! ULPIEXTVBUSINDIACTOR - ULPI External VBUS Indicator */ #define USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHIFT)) & USB3_CORE_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_MASK) #define USB3_CORE_GUSB2PHYCFG_LSIPD_MASK (0x380000U) #define USB3_CORE_GUSB2PHYCFG_LSIPD_SHIFT (19U) /*! LSIPD - LS Inter-Packet Time */ #define USB3_CORE_GUSB2PHYCFG_LSIPD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_LSIPD_SHIFT)) & USB3_CORE_GUSB2PHYCFG_LSIPD_MASK) #define USB3_CORE_GUSB2PHYCFG_LSTRD_MASK (0x1C00000U) #define USB3_CORE_GUSB2PHYCFG_LSTRD_SHIFT (22U) /*! LSTRD - LS Turnaround Time */ #define USB3_CORE_GUSB2PHYCFG_LSTRD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_LSTRD_SHIFT)) & USB3_CORE_GUSB2PHYCFG_LSTRD_MASK) #define USB3_CORE_GUSB2PHYCFG_OVRD_FSLS_DISC_TIME_MASK (0x2000000U) #define USB3_CORE_GUSB2PHYCFG_OVRD_FSLS_DISC_TIME_SHIFT (25U) /*! OVRD_FSLS_DISC_TIME - Overriding the FS/LS Disconnect Time * 0b0..The FS/LS disconnect time is set to 2.5 us as per the USB specification. * 0b1..The disconnect detection time is set to 32 us. */ #define USB3_CORE_GUSB2PHYCFG_OVRD_FSLS_DISC_TIME(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_OVRD_FSLS_DISC_TIME_SHIFT)) & USB3_CORE_GUSB2PHYCFG_OVRD_FSLS_DISC_TIME_MASK) #define USB3_CORE_GUSB2PHYCFG_INV_SEL_HSIC_MASK (0x4000000U) #define USB3_CORE_GUSB2PHYCFG_INV_SEL_HSIC_SHIFT (26U) #define USB3_CORE_GUSB2PHYCFG_INV_SEL_HSIC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_INV_SEL_HSIC_SHIFT)) & USB3_CORE_GUSB2PHYCFG_INV_SEL_HSIC_MASK) #define USB3_CORE_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_MASK (0x18000000U) #define USB3_CORE_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_SHIFT (27U) #define USB3_CORE_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_SHIFT)) & USB3_CORE_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_MASK) #define USB3_CORE_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_MASK (0x20000000U) #define USB3_CORE_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_SHIFT (29U) /*! ULPI_LPM_WITH_OPMODE_CHK * 0b0..A NOPID is sent before sending an EXTPID for LPM. * 0b1..An EXTPID is sent without previously sending a NOPID. */ #define USB3_CORE_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_SHIFT)) & USB3_CORE_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_MASK) #define USB3_CORE_GUSB2PHYCFG_U2_FREECLK_EXISTS_MASK (0x40000000U) #define USB3_CORE_GUSB2PHYCFG_U2_FREECLK_EXISTS_SHIFT (30U) /*! U2_FREECLK_EXISTS - U2_FREECLK_EXISTS * 0b0..USB 2.0 free clock does not exist. * 0b1..USB 2.0 free clock exists. */ #define USB3_CORE_GUSB2PHYCFG_U2_FREECLK_EXISTS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_U2_FREECLK_EXISTS_SHIFT)) & USB3_CORE_GUSB2PHYCFG_U2_FREECLK_EXISTS_MASK) #define USB3_CORE_GUSB2PHYCFG_PHYSOFTRST_MASK (0x80000000U) #define USB3_CORE_GUSB2PHYCFG_PHYSOFTRST_SHIFT (31U) /*! PHYSOFTRST - UTMI PHY Soft Reset */ #define USB3_CORE_GUSB2PHYCFG_PHYSOFTRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2PHYCFG_PHYSOFTRST_SHIFT)) & USB3_CORE_GUSB2PHYCFG_PHYSOFTRST_MASK) /*! @} */ /*! @name GUSB3PIPECTL - Global USB 3.0 PIPE Control */ /*! @{ */ #define USB3_CORE_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_MASK (0x1U) #define USB3_CORE_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHIFT (0U) /*! ELASTIC_BUFFER_MODE - Elastic Buffer Mode */ #define USB3_CORE_GUSB3PIPECTL_ELASTIC_BUFFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHIFT)) & USB3_CORE_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_MASK) #define USB3_CORE_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_MASK (0x6U) #define USB3_CORE_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_SHIFT (1U) /*! SS_TX_DE_EMPHASIS - TX De Emphasis */ #define USB3_CORE_GUSB3PIPECTL_SS_TX_DE_EMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_SHIFT)) & USB3_CORE_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_MASK) #define USB3_CORE_GUSB3PIPECTL_TX_MARGIN_MASK (0x38U) #define USB3_CORE_GUSB3PIPECTL_TX_MARGIN_SHIFT (3U) /*! TX_MARGIN - TX Margin [2:0] */ #define USB3_CORE_GUSB3PIPECTL_TX_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_TX_MARGIN_SHIFT)) & USB3_CORE_GUSB3PIPECTL_TX_MARGIN_MASK) #define USB3_CORE_GUSB3PIPECTL_TX_SWING_MASK (0x40U) #define USB3_CORE_GUSB3PIPECTL_TX_SWING_SHIFT (6U) /*! TX_SWING - TX Swing */ #define USB3_CORE_GUSB3PIPECTL_TX_SWING(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_TX_SWING_SHIFT)) & USB3_CORE_GUSB3PIPECTL_TX_SWING_MASK) #define USB3_CORE_GUSB3PIPECTL_SSICEn_MASK (0x80U) #define USB3_CORE_GUSB3PIPECTL_SSICEn_SHIFT (7U) /*! SSICEn - USB3 SSIC Enable */ #define USB3_CORE_GUSB3PIPECTL_SSICEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_SSICEn_SHIFT)) & USB3_CORE_GUSB3PIPECTL_SSICEn_MASK) #define USB3_CORE_GUSB3PIPECTL_RX_DETECT_to_Polling_LFPS_Control_MASK (0x100U) #define USB3_CORE_GUSB3PIPECTL_RX_DETECT_to_Polling_LFPS_Control_SHIFT (8U) /*! RX_DETECT_to_Polling_LFPS_Control - RX_DETECT to Polling LFPS Control * 0b0..Enables a 400 us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level * 0b1..Disables the 400 us delay to start Polling LFPS after RX_DETECT */ #define USB3_CORE_GUSB3PIPECTL_RX_DETECT_to_Polling_LFPS_Control(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_RX_DETECT_to_Polling_LFPS_Control_SHIFT)) & USB3_CORE_GUSB3PIPECTL_RX_DETECT_to_Polling_LFPS_Control_MASK) #define USB3_CORE_GUSB3PIPECTL_LFPSFILTER_MASK (0x200U) #define USB3_CORE_GUSB3PIPECTL_LFPSFILTER_SHIFT (9U) /*! LFPSFILTER - LFPS Filter */ #define USB3_CORE_GUSB3PIPECTL_LFPSFILTER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_LFPSFILTER_SHIFT)) & USB3_CORE_GUSB3PIPECTL_LFPSFILTER_MASK) #define USB3_CORE_GUSB3PIPECTL_P3ExSigP2_MASK (0x400U) #define USB3_CORE_GUSB3PIPECTL_P3ExSigP2_SHIFT (10U) /*! P3ExSigP2 - P3 Exit Signal in P2 */ #define USB3_CORE_GUSB3PIPECTL_P3ExSigP2(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_P3ExSigP2_SHIFT)) & USB3_CORE_GUSB3PIPECTL_P3ExSigP2_MASK) #define USB3_CORE_GUSB3PIPECTL_P3P2TranOK_MASK (0x800U) #define USB3_CORE_GUSB3PIPECTL_P3P2TranOK_SHIFT (11U) /*! P3P2TranOK - P3 P2 Transitions OK */ #define USB3_CORE_GUSB3PIPECTL_P3P2TranOK(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_P3P2TranOK_SHIFT)) & USB3_CORE_GUSB3PIPECTL_P3P2TranOK_MASK) #define USB3_CORE_GUSB3PIPECTL_LFPSP0Algn_MASK (0x1000U) #define USB3_CORE_GUSB3PIPECTL_LFPSP0Algn_SHIFT (12U) /*! LFPSP0Algn - LFPS P0 Align */ #define USB3_CORE_GUSB3PIPECTL_LFPSP0Algn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_LFPSP0Algn_SHIFT)) & USB3_CORE_GUSB3PIPECTL_LFPSP0Algn_MASK) #define USB3_CORE_GUSB3PIPECTL_SkipRxDet_MASK (0x2000U) #define USB3_CORE_GUSB3PIPECTL_SkipRxDet_SHIFT (13U) /*! SkipRxDet - Skip RX Detect */ #define USB3_CORE_GUSB3PIPECTL_SkipRxDet(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_SkipRxDet_SHIFT)) & USB3_CORE_GUSB3PIPECTL_SkipRxDet_MASK) #define USB3_CORE_GUSB3PIPECTL_AbortRxDetInU2_MASK (0x4000U) #define USB3_CORE_GUSB3PIPECTL_AbortRxDetInU2_SHIFT (14U) /*! AbortRxDetInU2 - Abort RX Detect in U2 */ #define USB3_CORE_GUSB3PIPECTL_AbortRxDetInU2(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_AbortRxDetInU2_SHIFT)) & USB3_CORE_GUSB3PIPECTL_AbortRxDetInU2_MASK) #define USB3_CORE_GUSB3PIPECTL_DATWIDTH_MASK (0x18000U) #define USB3_CORE_GUSB3PIPECTL_DATWIDTH_SHIFT (15U) /*! DATWIDTH - PIPE Data Width * 0b00..32 bits * 0b01..16 bits */ #define USB3_CORE_GUSB3PIPECTL_DATWIDTH(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_DATWIDTH_SHIFT)) & USB3_CORE_GUSB3PIPECTL_DATWIDTH_MASK) #define USB3_CORE_GUSB3PIPECTL_SUSPENDENABLE_MASK (0x20000U) #define USB3_CORE_GUSB3PIPECTL_SUSPENDENABLE_SHIFT (17U) /*! SUSPENDENABLE - Suspend USB3 SS PHY */ #define USB3_CORE_GUSB3PIPECTL_SUSPENDENABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_SUSPENDENABLE_SHIFT)) & USB3_CORE_GUSB3PIPECTL_SUSPENDENABLE_MASK) #define USB3_CORE_GUSB3PIPECTL_DELAYP1TRANS_MASK (0x40000U) #define USB3_CORE_GUSB3PIPECTL_DELAYP1TRANS_SHIFT (18U) /*! DELAYP1TRANS - Delay PHY Power * 0b0..When entering U1/U2/U3, transition to P1/P2/P3 without checking for Pipe3_RxElecIdle and pipe3_RxValid. * 0b1..When entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals, Pipe3_RxElecIdle is 1 and pipe3_RxValid is 0. */ #define USB3_CORE_GUSB3PIPECTL_DELAYP1TRANS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_DELAYP1TRANS_SHIFT)) & USB3_CORE_GUSB3PIPECTL_DELAYP1TRANS_MASK) #define USB3_CORE_GUSB3PIPECTL_DelayP1P2P3_MASK (0x380000U) #define USB3_CORE_GUSB3PIPECTL_DelayP1P2P3_SHIFT (19U) /*! DelayP1P2P3 - Delay P1P2P3 */ #define USB3_CORE_GUSB3PIPECTL_DelayP1P2P3(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_DelayP1P2P3_SHIFT)) & USB3_CORE_GUSB3PIPECTL_DelayP1P2P3_MASK) #define USB3_CORE_GUSB3PIPECTL_DisRxDetU3RxDet_MASK (0x400000U) #define USB3_CORE_GUSB3PIPECTL_DisRxDetU3RxDet_SHIFT (22U) /*! DisRxDetU3RxDet - Disable Receiver Detection in U3/RX.Detect */ #define USB3_CORE_GUSB3PIPECTL_DisRxDetU3RxDet(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_DisRxDetU3RxDet_SHIFT)) & USB3_CORE_GUSB3PIPECTL_DisRxDetU3RxDet_MASK) #define USB3_CORE_GUSB3PIPECTL_StartRxDetU3RxDet_MASK (0x800000U) #define USB3_CORE_GUSB3PIPECTL_StartRxDetU3RxDet_SHIFT (23U) /*! StartRxDetU3RxDet - Start Receiver Detection in U3/RX.Detect */ #define USB3_CORE_GUSB3PIPECTL_StartRxDetU3RxDet(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_StartRxDetU3RxDet_SHIFT)) & USB3_CORE_GUSB3PIPECTL_StartRxDetU3RxDet_MASK) #define USB3_CORE_GUSB3PIPECTL_request_p1p2p3_MASK (0x1000000U) #define USB3_CORE_GUSB3PIPECTL_request_p1p2p3_SHIFT (24U) /*! request_p1p2p3 - Always Request P1/P2/P3 for U1/U2/U3 */ #define USB3_CORE_GUSB3PIPECTL_request_p1p2p3(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_request_p1p2p3_SHIFT)) & USB3_CORE_GUSB3PIPECTL_request_p1p2p3_MASK) #define USB3_CORE_GUSB3PIPECTL_u1u2exitfail_to_recov_MASK (0x2000000U) #define USB3_CORE_GUSB3PIPECTL_u1u2exitfail_to_recov_SHIFT (25U) /*! u1u2exitfail_to_recov - U1U2exitfail to Recovery */ #define USB3_CORE_GUSB3PIPECTL_u1u2exitfail_to_recov(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_u1u2exitfail_to_recov_SHIFT)) & USB3_CORE_GUSB3PIPECTL_u1u2exitfail_to_recov_MASK) #define USB3_CORE_GUSB3PIPECTL_ping_enhancement_en_MASK (0x4000000U) #define USB3_CORE_GUSB3PIPECTL_ping_enhancement_en_SHIFT (26U) /*! ping_enhancement_en - Ping Enhancement Enable */ #define USB3_CORE_GUSB3PIPECTL_ping_enhancement_en(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_ping_enhancement_en_SHIFT)) & USB3_CORE_GUSB3PIPECTL_ping_enhancement_en_MASK) #define USB3_CORE_GUSB3PIPECTL_Ux_exit_in_Px_MASK (0x8000000U) #define USB3_CORE_GUSB3PIPECTL_Ux_exit_in_Px_SHIFT (27U) /*! Ux_exit_in_Px - Ux Exit in Px * 0b0..The core does U1/U2/U3 exit in PHY power state P0 (default behavior). * 0b1..The controller does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively. */ #define USB3_CORE_GUSB3PIPECTL_Ux_exit_in_Px(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_Ux_exit_in_Px_SHIFT)) & USB3_CORE_GUSB3PIPECTL_Ux_exit_in_Px_MASK) #define USB3_CORE_GUSB3PIPECTL_DisRxDetP3_MASK (0x10000000U) #define USB3_CORE_GUSB3PIPECTL_DisRxDetP3_SHIFT (28U) /*! DisRxDetP3 - Disabled Receiver Detection in P3 * 0b0..If PHY is in P3 and controller needs to perform receiver detection, the controller performs receiver detection in P3. (Default) * 0b1..If PHY is in P3 and controller needs to perform receiver detection, the controller changes the PHY power * state to P2 and then performs receiver detection. After receiver detection, the cores changes PHY power * state to P3. */ #define USB3_CORE_GUSB3PIPECTL_DisRxDetP3(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_DisRxDetP3_SHIFT)) & USB3_CORE_GUSB3PIPECTL_DisRxDetP3_MASK) #define USB3_CORE_GUSB3PIPECTL_U2P3ok_MASK (0x20000000U) #define USB3_CORE_GUSB3PIPECTL_U2P3ok_SHIFT (29U) /*! U2P3ok - P3 OK for U2 * 0b0..During link state U2/SS.Inactive, put PHY in P2 (Default). * 0b1..During link state U2/SS.Inactive, put PHY in P3. */ #define USB3_CORE_GUSB3PIPECTL_U2P3ok(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_U2P3ok_SHIFT)) & USB3_CORE_GUSB3PIPECTL_U2P3ok_MASK) #define USB3_CORE_GUSB3PIPECTL_HstPrtCmpl_MASK (0x40000000U) #define USB3_CORE_GUSB3PIPECTL_HstPrtCmpl_SHIFT (30U) #define USB3_CORE_GUSB3PIPECTL_HstPrtCmpl(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_HstPrtCmpl_SHIFT)) & USB3_CORE_GUSB3PIPECTL_HstPrtCmpl_MASK) #define USB3_CORE_GUSB3PIPECTL_PHYSoftRst_MASK (0x80000000U) #define USB3_CORE_GUSB3PIPECTL_PHYSoftRst_SHIFT (31U) /*! PHYSoftRst - USB3_PHY Soft Reset */ #define USB3_CORE_GUSB3PIPECTL_PHYSoftRst(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB3PIPECTL_PHYSoftRst_SHIFT)) & USB3_CORE_GUSB3PIPECTL_PHYSoftRst_MASK) /*! @} */ /*! @name GTXFIFOSIZ - Global Transmit FIFO Size */ /*! @{ */ #define USB3_CORE_GTXFIFOSIZ_TXFDEP_N_MASK (0xFFFFU) #define USB3_CORE_GTXFIFOSIZ_TXFDEP_N_SHIFT (0U) /*! TXFDEP_N - TXFIFO depth */ #define USB3_CORE_GTXFIFOSIZ_TXFDEP_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GTXFIFOSIZ_TXFDEP_N_SHIFT)) & USB3_CORE_GTXFIFOSIZ_TXFDEP_N_MASK) #define USB3_CORE_GTXFIFOSIZ_TXFSTADDR_N_MASK (0xFFFF0000U) #define USB3_CORE_GTXFIFOSIZ_TXFSTADDR_N_SHIFT (16U) /*! TXFSTADDR_N - Transmit FIFOn RAM Start Address */ #define USB3_CORE_GTXFIFOSIZ_TXFSTADDR_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GTXFIFOSIZ_TXFSTADDR_N_SHIFT)) & USB3_CORE_GTXFIFOSIZ_TXFSTADDR_N_MASK) /*! @} */ /* The count of USB3_CORE_GTXFIFOSIZ */ #define USB3_CORE_GTXFIFOSIZ_COUNT (8U) /*! @name GRXFIFOSIZ - Global Receive FIFO Size */ /*! @{ */ #define USB3_CORE_GRXFIFOSIZ_RXFDEP_N_MASK (0xFFFFU) #define USB3_CORE_GRXFIFOSIZ_RXFDEP_N_SHIFT (0U) /*! RXFDEP_N - RxFIFO Depth */ #define USB3_CORE_GRXFIFOSIZ_RXFDEP_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GRXFIFOSIZ_RXFDEP_N_SHIFT)) & USB3_CORE_GRXFIFOSIZ_RXFDEP_N_MASK) #define USB3_CORE_GRXFIFOSIZ_RXFSTADDR_N_MASK (0xFFFF0000U) #define USB3_CORE_GRXFIFOSIZ_RXFSTADDR_N_SHIFT (16U) /*! RXFSTADDR_N - RxFIFOn RAM Start Address */ #define USB3_CORE_GRXFIFOSIZ_RXFSTADDR_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GRXFIFOSIZ_RXFSTADDR_N_SHIFT)) & USB3_CORE_GRXFIFOSIZ_RXFSTADDR_N_MASK) /*! @} */ /* The count of USB3_CORE_GRXFIFOSIZ */ #define USB3_CORE_GRXFIFOSIZ_COUNT (3U) /*! @name GEVNTADRLO - Global Event Buffer Address Low */ /*! @{ */ #define USB3_CORE_GEVNTADRLO_EVNTADRLO_MASK (0xFFFFFFFFU) #define USB3_CORE_GEVNTADRLO_EVNTADRLO_SHIFT (0U) /*! EVNTADRLO - Event Buffer Address */ #define USB3_CORE_GEVNTADRLO_EVNTADRLO(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GEVNTADRLO_EVNTADRLO_SHIFT)) & USB3_CORE_GEVNTADRLO_EVNTADRLO_MASK) /*! @} */ /*! @name GEVNTADRHI - Global Event Buffer Address High */ /*! @{ */ #define USB3_CORE_GEVNTADRHI_EVNTADRHI_MASK (0xFFFFFFFFU) #define USB3_CORE_GEVNTADRHI_EVNTADRHI_SHIFT (0U) /*! EVNTADRHI - Event Buffer Address */ #define USB3_CORE_GEVNTADRHI_EVNTADRHI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GEVNTADRHI_EVNTADRHI_SHIFT)) & USB3_CORE_GEVNTADRHI_EVNTADRHI_MASK) /*! @} */ /*! @name GEVNTSIZ - Global Event Buffer Size */ /*! @{ */ #define USB3_CORE_GEVNTSIZ_EVENTSIZ_MASK (0xFFFFU) #define USB3_CORE_GEVNTSIZ_EVENTSIZ_SHIFT (0U) /*! EVENTSIZ - Event Buffer Size in Bytes */ #define USB3_CORE_GEVNTSIZ_EVENTSIZ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GEVNTSIZ_EVENTSIZ_SHIFT)) & USB3_CORE_GEVNTSIZ_EVENTSIZ_MASK) #define USB3_CORE_GEVNTSIZ_EVNTINTRPTMASK_MASK (0x80000000U) #define USB3_CORE_GEVNTSIZ_EVNTINTRPTMASK_SHIFT (31U) #define USB3_CORE_GEVNTSIZ_EVNTINTRPTMASK(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GEVNTSIZ_EVNTINTRPTMASK_SHIFT)) & USB3_CORE_GEVNTSIZ_EVNTINTRPTMASK_MASK) /*! @} */ /*! @name GEVNTCOUNT - Global Event Buffer Count */ /*! @{ */ #define USB3_CORE_GEVNTCOUNT_EVNTCOUNT_MASK (0xFFFFU) #define USB3_CORE_GEVNTCOUNT_EVNTCOUNT_SHIFT (0U) /*! EVNTCOUNT - Event Count */ #define USB3_CORE_GEVNTCOUNT_EVNTCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GEVNTCOUNT_EVNTCOUNT_SHIFT)) & USB3_CORE_GEVNTCOUNT_EVNTCOUNT_MASK) #define USB3_CORE_GEVNTCOUNT_EVNT_HANDLER_BUSY_MASK (0x80000000U) #define USB3_CORE_GEVNTCOUNT_EVNT_HANDLER_BUSY_SHIFT (31U) /*! EVNT_HANDLER_BUSY - Event Handler Busy */ #define USB3_CORE_GEVNTCOUNT_EVNT_HANDLER_BUSY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GEVNTCOUNT_EVNT_HANDLER_BUSY_SHIFT)) & USB3_CORE_GEVNTCOUNT_EVNT_HANDLER_BUSY_MASK) /*! @} */ /*! @name GHWPARAMS8 - Global Hardware Parameters 8 */ /*! @{ */ #define USB3_CORE_GHWPARAMS8_GHWPARAMS8_32_0_MASK (0xFFFFFFFFU) #define USB3_CORE_GHWPARAMS8_GHWPARAMS8_32_0_SHIFT (0U) /*! GHWPARAMS8_32_0 - DWC_USB3_DCACHE_DEPTH_INFO */ #define USB3_CORE_GHWPARAMS8_GHWPARAMS8_32_0(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GHWPARAMS8_GHWPARAMS8_32_0_SHIFT)) & USB3_CORE_GHWPARAMS8_GHWPARAMS8_32_0_MASK) /*! @} */ /*! @name GUCTL3 - Global User Control 3 */ /*! @{ */ #define USB3_CORE_GUCTL3_SCH_PING_EARLY_MASK (0x10000U) #define USB3_CORE_GUCTL3_SCH_PING_EARLY_SHIFT (16U) #define USB3_CORE_GUCTL3_SCH_PING_EARLY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUCTL3_SCH_PING_EARLY_SHIFT)) & USB3_CORE_GUCTL3_SCH_PING_EARLY_MASK) /*! @} */ /*! @name GTXFIFOPRIDEV - Global Device TX FIFO DMA Priority */ /*! @{ */ #define USB3_CORE_GTXFIFOPRIDEV_gtxfifopridev_MASK (0xFFU) #define USB3_CORE_GTXFIFOPRIDEV_gtxfifopridev_SHIFT (0U) /*! gtxfifopridev - Device TxFIFO Priority */ #define USB3_CORE_GTXFIFOPRIDEV_gtxfifopridev(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GTXFIFOPRIDEV_gtxfifopridev_SHIFT)) & USB3_CORE_GTXFIFOPRIDEV_gtxfifopridev_MASK) /*! @} */ /*! @name GTXFIFOPRIHST - Global Host TX FIFO DMA Priority */ /*! @{ */ #define USB3_CORE_GTXFIFOPRIHST_gtxfifoprihst_MASK (0xFU) #define USB3_CORE_GTXFIFOPRIHST_gtxfifoprihst_SHIFT (0U) /*! gtxfifoprihst - Host TxFIFO Priority */ #define USB3_CORE_GTXFIFOPRIHST_gtxfifoprihst(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GTXFIFOPRIHST_gtxfifoprihst_SHIFT)) & USB3_CORE_GTXFIFOPRIHST_gtxfifoprihst_MASK) /*! @} */ /*! @name GRXFIFOPRIHST - Global Host RX FIFO DMA Priority */ /*! @{ */ #define USB3_CORE_GRXFIFOPRIHST_grxfifoprihst_MASK (0x7U) #define USB3_CORE_GRXFIFOPRIHST_grxfifoprihst_SHIFT (0U) /*! grxfifoprihst - Host RxFIFO Priority */ #define USB3_CORE_GRXFIFOPRIHST_grxfifoprihst(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GRXFIFOPRIHST_grxfifoprihst_SHIFT)) & USB3_CORE_GRXFIFOPRIHST_grxfifoprihst_MASK) /*! @} */ /*! @name GFIFOPRIDBC - Global Host Debug Capability DMA Priority */ /*! @{ */ #define USB3_CORE_GFIFOPRIDBC_gfifopridbc_MASK (0x3U) #define USB3_CORE_GFIFOPRIDBC_gfifopridbc_SHIFT (0U) /*! gfifopridbc - Host DbC DMA Priority */ #define USB3_CORE_GFIFOPRIDBC_gfifopridbc(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GFIFOPRIDBC_gfifopridbc_SHIFT)) & USB3_CORE_GFIFOPRIDBC_gfifopridbc_MASK) /*! @} */ /*! @name GDMAHLRATIO - Global Host FIFO DMA High-Low Priority Ratio */ /*! @{ */ #define USB3_CORE_GDMAHLRATIO_hsttxfifo_MASK (0x1FU) #define USB3_CORE_GDMAHLRATIO_hsttxfifo_SHIFT (0U) /*! hsttxfifo - Host TXFIFO DMA High-Low Priority */ #define USB3_CORE_GDMAHLRATIO_hsttxfifo(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GDMAHLRATIO_hsttxfifo_SHIFT)) & USB3_CORE_GDMAHLRATIO_hsttxfifo_MASK) #define USB3_CORE_GDMAHLRATIO_hstrxfifo_MASK (0x1F00U) #define USB3_CORE_GDMAHLRATIO_hstrxfifo_SHIFT (8U) /*! hstrxfifo - Host RXFIFO DMA High-Low Priority */ #define USB3_CORE_GDMAHLRATIO_hstrxfifo(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GDMAHLRATIO_hstrxfifo_SHIFT)) & USB3_CORE_GDMAHLRATIO_hstrxfifo_MASK) /*! @} */ /*! @name GFLADJ - Global Frame Length Adjustment */ /*! @{ */ #define USB3_CORE_GFLADJ_GFLADJ_30MHZ_MASK (0x3FU) #define USB3_CORE_GFLADJ_GFLADJ_30MHZ_SHIFT (0U) #define USB3_CORE_GFLADJ_GFLADJ_30MHZ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GFLADJ_GFLADJ_30MHZ_SHIFT)) & USB3_CORE_GFLADJ_GFLADJ_30MHZ_MASK) #define USB3_CORE_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_MASK (0x80U) #define USB3_CORE_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_SHIFT (7U) /*! GFLADJ_30MHZ_SDBND_SEL * 0b0..The controller uses the input signal fladj_30mhz_reg value * 0b1..The controller uses the register field GFLADJ.GFLADJ_30MHZ value */ #define USB3_CORE_GFLADJ_GFLADJ_30MHZ_SDBND_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_SHIFT)) & USB3_CORE_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_MASK) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK (0x3FFF00U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT (8U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT)) & USB3_CORE_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_LPM_SEL_MASK (0x800000U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_LPM_SEL_SHIFT (23U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_LPM_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GFLADJ_GFLADJ_REFCLK_LPM_SEL_SHIFT)) & USB3_CORE_GFLADJ_GFLADJ_REFCLK_LPM_SEL_MASK) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_MASK (0x7F000000U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_SHIFT (24U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_SHIFT)) & USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_MASK) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_MASK (0x80000000U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_SHIFT (31U) #define USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_SHIFT)) & USB3_CORE_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_MASK) /*! @} */ /*! @name GUSB2RHBCTL - Global USB 2.0 Root Hub Control */ /*! @{ */ #define USB3_CORE_GUSB2RHBCTL_OVRD_L1TIMEOUT_MASK (0xFU) #define USB3_CORE_GUSB2RHBCTL_OVRD_L1TIMEOUT_SHIFT (0U) /*! OVRD_L1TIMEOUT - Overriding Driver Programmed L1Timeout Value */ #define USB3_CORE_GUSB2RHBCTL_OVRD_L1TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_GUSB2RHBCTL_OVRD_L1TIMEOUT_SHIFT)) & USB3_CORE_GUSB2RHBCTL_OVRD_L1TIMEOUT_MASK) /*! @} */ /*! @name DCFG - Device Configuration */ /*! @{ */ #define USB3_CORE_DCFG_DEVSPD_MASK (0x7U) #define USB3_CORE_DCFG_DEVSPD_SHIFT (0U) /*! DEVSPD - Device Speed * 0b001..Full-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) * 0b000..High-speed (USB 2.0 PHY clock is 30 MHz or 60 MHz) * 0b100..SuperSpeed (USB 3.0 PHY clock is 125 MHz or 250 MHz) */ #define USB3_CORE_DCFG_DEVSPD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCFG_DEVSPD_SHIFT)) & USB3_CORE_DCFG_DEVSPD_MASK) #define USB3_CORE_DCFG_DEVADDR_MASK (0x3F8U) #define USB3_CORE_DCFG_DEVADDR_SHIFT (3U) /*! DEVADDR - Device Address */ #define USB3_CORE_DCFG_DEVADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCFG_DEVADDR_SHIFT)) & USB3_CORE_DCFG_DEVADDR_MASK) #define USB3_CORE_DCFG_INTRNUM_MASK (0x1F000U) #define USB3_CORE_DCFG_INTRNUM_SHIFT (12U) /*! INTRNUM - Interrupt Number */ #define USB3_CORE_DCFG_INTRNUM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCFG_INTRNUM_SHIFT)) & USB3_CORE_DCFG_INTRNUM_MASK) #define USB3_CORE_DCFG_NUMP_MASK (0x3E0000U) #define USB3_CORE_DCFG_NUMP_SHIFT (17U) /*! NUMP - Number of Receive Buffers */ #define USB3_CORE_DCFG_NUMP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCFG_NUMP_SHIFT)) & USB3_CORE_DCFG_NUMP_MASK) #define USB3_CORE_DCFG_LPMCAP_MASK (0x400000U) #define USB3_CORE_DCFG_LPMCAP_SHIFT (22U) /*! LPMCAP - LPM Capable * 0b0..LPM capability is not enabled. * 0b1..LPM capability is enabled. */ #define USB3_CORE_DCFG_LPMCAP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCFG_LPMCAP_SHIFT)) & USB3_CORE_DCFG_LPMCAP_MASK) #define USB3_CORE_DCFG_IgnStrmPP_MASK (0x800000U) #define USB3_CORE_DCFG_IgnStrmPP_SHIFT (23U) /*! IgnStrmPP - Ignore Stream PP * 0b0..Not ignore * 0b1..Ignores */ #define USB3_CORE_DCFG_IgnStrmPP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCFG_IgnStrmPP_SHIFT)) & USB3_CORE_DCFG_IgnStrmPP_MASK) /*! @} */ /*! @name DCTL - Device Control 0 */ /*! @{ */ #define USB3_CORE_DCTL_TSTCTL_MASK (0x1EU) #define USB3_CORE_DCTL_TSTCTL_SHIFT (1U) /*! TSTCTL - Test Control * 0b0000..Test mode disabled * 0b0001..Test_J mode * 0b0010..Test_K mode * 0b0011..Test_SE0_NAK mode * 0b0100..Test_Packet mode * 0b0101..Test_Force_Enable * 0b0110-0b1111..Reserved */ #define USB3_CORE_DCTL_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_TSTCTL_SHIFT)) & USB3_CORE_DCTL_TSTCTL_MASK) #define USB3_CORE_DCTL_ULSTCHNGREQ_MASK (0x1E0U) #define USB3_CORE_DCTL_ULSTCHNGREQ_SHIFT (5U) /*! ULSTCHNGREQ * 0b0000..Value Requested Link State Transition/Action: no Action (in SS mode) * 0b0001-0b0011..Reserved * 0b0100..SS.Disabled (SS) * 0b0101..RX.Detect (SS) * 0b0110..SS.Inactive (SS) * 0b0111..Reserved * 0b1000..Recovery (SS), ValueRequested USB state transition: remote wakeup request (in HS/FS/LS mode) * 0b1001..Reserved * 0b1010..Compliance (SS) * 0b1011-0b1111..Reserved */ #define USB3_CORE_DCTL_ULSTCHNGREQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_ULSTCHNGREQ_SHIFT)) & USB3_CORE_DCTL_ULSTCHNGREQ_MASK) #define USB3_CORE_DCTL_ACCEPTU1ENA_MASK (0x200U) #define USB3_CORE_DCTL_ACCEPTU1ENA_SHIFT (9U) /*! ACCEPTU1ENA - Accept U1 Enable * 0b0..Core rejects U1 except when Force_LinkPM_Accept bit is set (default) * 0b1..Core accepts transition to U1 state if nothing is pending on the application side. On USB reset, hardware clears this bit to 0 */ #define USB3_CORE_DCTL_ACCEPTU1ENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_ACCEPTU1ENA_SHIFT)) & USB3_CORE_DCTL_ACCEPTU1ENA_MASK) #define USB3_CORE_DCTL_INITU1ENA_MASK (0x400U) #define USB3_CORE_DCTL_INITU1ENA_SHIFT (10U) /*! INITU1ENA - Initiate U1 Enable * 0b0..May not initiate U1 (default) * 0b1..May initiate U1. On USB reset, hardware clears this bit to 0 */ #define USB3_CORE_DCTL_INITU1ENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_INITU1ENA_SHIFT)) & USB3_CORE_DCTL_INITU1ENA_MASK) #define USB3_CORE_DCTL_ACCEPTU2ENA_MASK (0x800U) #define USB3_CORE_DCTL_ACCEPTU2ENA_SHIFT (11U) /*! ACCEPTU2ENA - Accept U2 Enable * 0b0..Reject U2 except when Force_LinkPM_Accept bit is set (default) * 0b1..Core accepts transition to U2 state if nothing is pending on the application side. On USB reset, hardware clears this bit to 0 */ #define USB3_CORE_DCTL_ACCEPTU2ENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_ACCEPTU2ENA_SHIFT)) & USB3_CORE_DCTL_ACCEPTU2ENA_MASK) #define USB3_CORE_DCTL_INITU2ENA_MASK (0x1000U) #define USB3_CORE_DCTL_INITU2ENA_SHIFT (12U) /*! INITU2ENA - Initiate U2 Enable * 0b0..May not initiate U2 (default) * 0b1..May initiate U2 On USB reset, hardware clears this bit to 0 */ #define USB3_CORE_DCTL_INITU2ENA(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_INITU2ENA_SHIFT)) & USB3_CORE_DCTL_INITU2ENA_MASK) #define USB3_CORE_DCTL_CSS_MASK (0x10000U) #define USB3_CORE_DCTL_CSS_SHIFT (16U) /*! CSS - Controller Save State */ #define USB3_CORE_DCTL_CSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_CSS_SHIFT)) & USB3_CORE_DCTL_CSS_MASK) #define USB3_CORE_DCTL_CRS_MASK (0x20000U) #define USB3_CORE_DCTL_CRS_SHIFT (17U) /*! CRS - Controller Restore State */ #define USB3_CORE_DCTL_CRS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_CRS_SHIFT)) & USB3_CORE_DCTL_CRS_MASK) #define USB3_CORE_DCTL_L1HibernationEn_MASK (0x40000U) #define USB3_CORE_DCTL_L1HibernationEn_SHIFT (18U) /*! L1HibernationEn - L1 Hibernation Enable */ #define USB3_CORE_DCTL_L1HibernationEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_L1HibernationEn_SHIFT)) & USB3_CORE_DCTL_L1HibernationEn_MASK) #define USB3_CORE_DCTL_KeepConnect_MASK (0x80000U) #define USB3_CORE_DCTL_KeepConnect_SHIFT (19U) /*! KeepConnect - Keep Connect */ #define USB3_CORE_DCTL_KeepConnect(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_KeepConnect_SHIFT)) & USB3_CORE_DCTL_KeepConnect_MASK) #define USB3_CORE_DCTL_LPM_NYET_thres_MASK (0xF00000U) #define USB3_CORE_DCTL_LPM_NYET_thres_SHIFT (20U) /*! LPM_NYET_thres - LPM NYET Threshold */ #define USB3_CORE_DCTL_LPM_NYET_thres(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_LPM_NYET_thres_SHIFT)) & USB3_CORE_DCTL_LPM_NYET_thres_MASK) #define USB3_CORE_DCTL_HIRDTHRES_MASK (0x1F000000U) #define USB3_CORE_DCTL_HIRDTHRES_SHIFT (24U) /*! HIRDTHRES - HIRD Threshold */ #define USB3_CORE_DCTL_HIRDTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_HIRDTHRES_SHIFT)) & USB3_CORE_DCTL_HIRDTHRES_MASK) #define USB3_CORE_DCTL_CSFTRST_MASK (0x40000000U) #define USB3_CORE_DCTL_CSFTRST_SHIFT (30U) /*! CSFTRST - Core Soft Reset */ #define USB3_CORE_DCTL_CSFTRST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_CSFTRST_SHIFT)) & USB3_CORE_DCTL_CSFTRST_MASK) #define USB3_CORE_DCTL_RUN_STOP_MASK (0x80000000U) #define USB3_CORE_DCTL_RUN_STOP_SHIFT (31U) /*! RUN_STOP - Run/Stop */ #define USB3_CORE_DCTL_RUN_STOP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DCTL_RUN_STOP_SHIFT)) & USB3_CORE_DCTL_RUN_STOP_MASK) /*! @} */ /*! @name DEVTEN - Device Event Enable */ /*! @{ */ #define USB3_CORE_DEVTEN_DISSCONNEVTEN_MASK (0x1U) #define USB3_CORE_DEVTEN_DISSCONNEVTEN_SHIFT (0U) #define USB3_CORE_DEVTEN_DISSCONNEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_DISSCONNEVTEN_SHIFT)) & USB3_CORE_DEVTEN_DISSCONNEVTEN_MASK) #define USB3_CORE_DEVTEN_USBRSTEVTEN_MASK (0x2U) #define USB3_CORE_DEVTEN_USBRSTEVTEN_SHIFT (1U) #define USB3_CORE_DEVTEN_USBRSTEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_USBRSTEVTEN_SHIFT)) & USB3_CORE_DEVTEN_USBRSTEVTEN_MASK) #define USB3_CORE_DEVTEN_CONNECTDONEEVTEN_MASK (0x4U) #define USB3_CORE_DEVTEN_CONNECTDONEEVTEN_SHIFT (2U) #define USB3_CORE_DEVTEN_CONNECTDONEEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_CONNECTDONEEVTEN_SHIFT)) & USB3_CORE_DEVTEN_CONNECTDONEEVTEN_MASK) #define USB3_CORE_DEVTEN_ULSTCNGEN_MASK (0x8U) #define USB3_CORE_DEVTEN_ULSTCNGEN_SHIFT (3U) #define USB3_CORE_DEVTEN_ULSTCNGEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_ULSTCNGEN_SHIFT)) & USB3_CORE_DEVTEN_ULSTCNGEN_MASK) #define USB3_CORE_DEVTEN_WKUPEVTEN_MASK (0x10U) #define USB3_CORE_DEVTEN_WKUPEVTEN_SHIFT (4U) /*! WKUPEVTEN - U3/L2 or U3/L2L1 Resume Detected Event Enable */ #define USB3_CORE_DEVTEN_WKUPEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_WKUPEVTEN_SHIFT)) & USB3_CORE_DEVTEN_WKUPEVTEN_MASK) #define USB3_CORE_DEVTEN_HibernationReqEvtEn_MASK (0x20U) #define USB3_CORE_DEVTEN_HibernationReqEvtEn_SHIFT (5U) /*! HibernationReqEvtEn - Hibernation Request Event */ #define USB3_CORE_DEVTEN_HibernationReqEvtEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_HibernationReqEvtEn_SHIFT)) & USB3_CORE_DEVTEN_HibernationReqEvtEn_MASK) #define USB3_CORE_DEVTEN_U3L2L1SuspEn_MASK (0x40U) #define USB3_CORE_DEVTEN_U3L2L1SuspEn_SHIFT (6U) /*! U3L2L1SuspEn - U3/L2 or U3/L2L1 Suspend Event Enable */ #define USB3_CORE_DEVTEN_U3L2L1SuspEn(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_U3L2L1SuspEn_SHIFT)) & USB3_CORE_DEVTEN_U3L2L1SuspEn_MASK) #define USB3_CORE_DEVTEN_SOFTEVTEN_MASK (0x80U) #define USB3_CORE_DEVTEN_SOFTEVTEN_SHIFT (7U) #define USB3_CORE_DEVTEN_SOFTEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_SOFTEVTEN_SHIFT)) & USB3_CORE_DEVTEN_SOFTEVTEN_MASK) #define USB3_CORE_DEVTEN_L1SUSPEN_MASK (0x100U) #define USB3_CORE_DEVTEN_L1SUSPEN_SHIFT (8U) /*! L1SUSPEN - L1 Suspend Event Enable */ #define USB3_CORE_DEVTEN_L1SUSPEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_L1SUSPEN_SHIFT)) & USB3_CORE_DEVTEN_L1SUSPEN_MASK) #define USB3_CORE_DEVTEN_ERRTICERREVTEN_MASK (0x200U) #define USB3_CORE_DEVTEN_ERRTICERREVTEN_SHIFT (9U) #define USB3_CORE_DEVTEN_ERRTICERREVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_ERRTICERREVTEN_SHIFT)) & USB3_CORE_DEVTEN_ERRTICERREVTEN_MASK) #define USB3_CORE_DEVTEN_VENDEVTSTRCVDEN_MASK (0x1000U) #define USB3_CORE_DEVTEN_VENDEVTSTRCVDEN_SHIFT (12U) #define USB3_CORE_DEVTEN_VENDEVTSTRCVDEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_VENDEVTSTRCVDEN_SHIFT)) & USB3_CORE_DEVTEN_VENDEVTSTRCVDEN_MASK) #define USB3_CORE_DEVTEN_L1WKUPEVTEN_MASK (0x4000U) #define USB3_CORE_DEVTEN_L1WKUPEVTEN_SHIFT (14U) /*! L1WKUPEVTEN - L1 Resume Detected Event Enable */ #define USB3_CORE_DEVTEN_L1WKUPEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_L1WKUPEVTEN_SHIFT)) & USB3_CORE_DEVTEN_L1WKUPEVTEN_MASK) #define USB3_CORE_DEVTEN_ECCERREN_MASK (0x10000U) #define USB3_CORE_DEVTEN_ECCERREN_SHIFT (16U) /*! ECCERREN - ECC Error Enable */ #define USB3_CORE_DEVTEN_ECCERREN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEVTEN_ECCERREN_SHIFT)) & USB3_CORE_DEVTEN_ECCERREN_MASK) /*! @} */ /*! @name DSTS - Device Status */ /*! @{ */ #define USB3_CORE_DSTS_CONNECTSPD_MASK (0x7U) #define USB3_CORE_DSTS_CONNECTSPD_SHIFT (0U) /*! CONNECTSPD - Connected Speed * 0b001..Full-speed (PHY clock is running at 30 or 60 MHz) * 0b000..High-speed (PHY clock is running at 30 or 60 MHz) * 0b100..SuperSpeed (PHY clock is running at 125 or 250 MHz) */ #define USB3_CORE_DSTS_CONNECTSPD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_CONNECTSPD_SHIFT)) & USB3_CORE_DSTS_CONNECTSPD_MASK) #define USB3_CORE_DSTS_SOFFN_MASK (0x1FFF8U) #define USB3_CORE_DSTS_SOFFN_SHIFT (3U) /*! SOFFN - Frame/Microframe Number of the Received SOF */ #define USB3_CORE_DSTS_SOFFN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_SOFFN_SHIFT)) & USB3_CORE_DSTS_SOFFN_MASK) #define USB3_CORE_DSTS_RXFIFOEMPTY_MASK (0x20000U) #define USB3_CORE_DSTS_RXFIFOEMPTY_SHIFT (17U) /*! RXFIFOEMPTY - RxFIFO Empty */ #define USB3_CORE_DSTS_RXFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_RXFIFOEMPTY_SHIFT)) & USB3_CORE_DSTS_RXFIFOEMPTY_MASK) #define USB3_CORE_DSTS_USBLNKST_MASK (0x3C0000U) #define USB3_CORE_DSTS_USBLNKST_SHIFT (18U) /*! USBLNKST - USB/Link State * 0b0000..LTSSM State U0 (in SS mode), On state (in HS/FS/LS mode) * 0b0001..LTSSM State U1 (SS) * 0b0010..LTSSM State U2 (SS), Sleep (L1) state (HS/FS/LS) * 0b0011..LTSSM State U3 (SS), Suspend (L2) state (HS/FS/LS) * 0b0100..LTSSM State SS_DIS (SS), Disconnected state (HS/FS/LS) * 0b0101..LTSSM State RX_DET (SS), Early Suspend state (in HS/FS/LS mode, valid only when Hibernation is disabled, GCTL[1].GblHibernationEn = 0) * 0b0110..LTSSM State SS_INACT (SS) * 0b0111..LTSSM State POLL (SS) * 0b1000..LTSSM State RECOV (SS) * 0b1001..LTSSM State HRESET (SS) * 0b1010..LTSSM State CMPLY (SS) * 0b1011..LTSSM State LPBK (SS) * 0b1110..Reset (HS/FS/LS, valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1) * 0b1111..LTSSM State Resume/Reset (SS), Resume (HS/FS/LS, valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1) */ #define USB3_CORE_DSTS_USBLNKST(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_USBLNKST_SHIFT)) & USB3_CORE_DSTS_USBLNKST_MASK) #define USB3_CORE_DSTS_DEVCTRLHLT_MASK (0x400000U) #define USB3_CORE_DSTS_DEVCTRLHLT_SHIFT (22U) /*! DEVCTRLHLT - Device Controller Halted */ #define USB3_CORE_DSTS_DEVCTRLHLT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_DEVCTRLHLT_SHIFT)) & USB3_CORE_DSTS_DEVCTRLHLT_MASK) #define USB3_CORE_DSTS_COREIDLE_MASK (0x800000U) #define USB3_CORE_DSTS_COREIDLE_SHIFT (23U) /*! COREIDLE - Core Idle */ #define USB3_CORE_DSTS_COREIDLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_COREIDLE_SHIFT)) & USB3_CORE_DSTS_COREIDLE_MASK) #define USB3_CORE_DSTS_SSS_MASK (0x1000000U) #define USB3_CORE_DSTS_SSS_SHIFT (24U) /*! SSS - Save State Status */ #define USB3_CORE_DSTS_SSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_SSS_SHIFT)) & USB3_CORE_DSTS_SSS_MASK) #define USB3_CORE_DSTS_RSS_MASK (0x2000000U) #define USB3_CORE_DSTS_RSS_SHIFT (25U) /*! RSS - Restore State Status */ #define USB3_CORE_DSTS_RSS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_RSS_SHIFT)) & USB3_CORE_DSTS_RSS_MASK) #define USB3_CORE_DSTS_DCNRD_MASK (0x20000000U) #define USB3_CORE_DSTS_DCNRD_SHIFT (29U) /*! DCNRD - Device Controller Not Ready */ #define USB3_CORE_DSTS_DCNRD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DSTS_DCNRD_SHIFT)) & USB3_CORE_DSTS_DCNRD_MASK) /*! @} */ /*! @name DGCMDPAR - Device Generic Command Parameter */ /*! @{ */ #define USB3_CORE_DGCMDPAR_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DGCMDPAR_PARAMETER_SHIFT (0U) #define USB3_CORE_DGCMDPAR_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DGCMDPAR_PARAMETER_SHIFT)) & USB3_CORE_DGCMDPAR_PARAMETER_MASK) /*! @} */ /*! @name DGCMD - Device Generic Command */ /*! @{ */ #define USB3_CORE_DGCMD_CMDTYP_MASK (0xFFU) #define USB3_CORE_DGCMD_CMDTYP_SHIFT (0U) /*! CMDTYP - Generic Command Type * 0b00000010..Set periodic parameters * 0b00000100..Set scratchpad buffer array address low * 0b00000101..Set Scratchpad buffer array address high * 0b00000111..Transmit device notification * 0b00001001..Selected FIFO flush * 0b00001010..All FIFO flush * 0b00001100..Set endpoint NRDY * 0b00010000..Run SoC bus loopback test * 0b00010001..Restart after disconnect */ #define USB3_CORE_DGCMD_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DGCMD_CMDTYP_SHIFT)) & USB3_CORE_DGCMD_CMDTYP_MASK) #define USB3_CORE_DGCMD_CMDIOC_MASK (0x100U) #define USB3_CORE_DGCMD_CMDIOC_SHIFT (8U) /*! CMDIOC - Command Interrupt on Complete */ #define USB3_CORE_DGCMD_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DGCMD_CMDIOC_SHIFT)) & USB3_CORE_DGCMD_CMDIOC_MASK) #define USB3_CORE_DGCMD_CMDACT_MASK (0x400U) #define USB3_CORE_DGCMD_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DGCMD_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DGCMD_CMDACT_SHIFT)) & USB3_CORE_DGCMD_CMDACT_MASK) #define USB3_CORE_DGCMD_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DGCMD_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Status * 0b0000..Indicates command success * 0b0001..CmdErr: Indicates that the device controller encountered an error while processing the command */ #define USB3_CORE_DGCMD_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DGCMD_CMDSTATUS_SHIFT)) & USB3_CORE_DGCMD_CMDSTATUS_MASK) /*! @} */ /*! @name DALEPENA - Device Active USB Endpoint Enable */ /*! @{ */ #define USB3_CORE_DALEPENA_USBACTEP_MASK (0xFFFFFFFFU) #define USB3_CORE_DALEPENA_USBACTEP_SHIFT (0U) /*! USBACTEP - USB Active Endpoints */ #define USB3_CORE_DALEPENA_USBACTEP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DALEPENA_USBACTEP_SHIFT)) & USB3_CORE_DALEPENA_USBACTEP_MASK) /*! @} */ /*! @name DEPCMDPAR20 - Device Physical Endpoint-0 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR20_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR20_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR20_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR20_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR20_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR10 - Device Physical Endpoint-0 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR10_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR10_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR10_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR10_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR10_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR00 - Device Physical Endpoint-0 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR00_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR00_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR00_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR00_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR00_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD0 - Device Physical Endpoint-0 Command */ /*! @{ */ #define USB3_CORE_DEPCMD0_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD0_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD0_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD0_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD0_CMDTYP_MASK) #define USB3_CORE_DEPCMD0_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD0_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD0_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD0_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD0_CMDIOC_MASK) #define USB3_CORE_DEPCMD0_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD0_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD0_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD0_CMDACT_SHIFT)) & USB3_CORE_DEPCMD0_CMDACT_MASK) #define USB3_CORE_DEPCMD0_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD0_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD0_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD0_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD0_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD0_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD0_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD0_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD0_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD0_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD0_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD0_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD0_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD0_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD0_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR21 - Device Physical Endpoint-1 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR21_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR21_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR21_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR21_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR21_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR11 - Device Physical Endpoint-1 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR11_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR11_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR11_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR11_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR11_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR01 - Device Physical Endpoint-1 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR01_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR01_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR01_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR01_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR01_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD1 - Device Physical Endpoint-1 Command */ /*! @{ */ #define USB3_CORE_DEPCMD1_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD1_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD1_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD1_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD1_CMDTYP_MASK) #define USB3_CORE_DEPCMD1_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD1_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD1_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD1_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD1_CMDIOC_MASK) #define USB3_CORE_DEPCMD1_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD1_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD1_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD1_CMDACT_SHIFT)) & USB3_CORE_DEPCMD1_CMDACT_MASK) #define USB3_CORE_DEPCMD1_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD1_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD1_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD1_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD1_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD1_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD1_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD1_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD1_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD1_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD1_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD1_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD1_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD1_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD1_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR22 - Device Physical Endpoint-2 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR22_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR22_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR22_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR22_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR22_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR12 - Device Physical Endpoint-2 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR12_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR12_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR12_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR12_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR12_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR02 - Device Physical Endpoint-2 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR02_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR02_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR02_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR02_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR02_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD2 - Device Physical Endpoint-2 Command */ /*! @{ */ #define USB3_CORE_DEPCMD2_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD2_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD2_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD2_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD2_CMDTYP_MASK) #define USB3_CORE_DEPCMD2_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD2_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD2_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD2_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD2_CMDIOC_MASK) #define USB3_CORE_DEPCMD2_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD2_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD2_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD2_CMDACT_SHIFT)) & USB3_CORE_DEPCMD2_CMDACT_MASK) #define USB3_CORE_DEPCMD2_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD2_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD2_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD2_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD2_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD2_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD2_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD2_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD2_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD2_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD2_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD2_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD2_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD2_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD2_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR23 - Device Physical Endpoint-3 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR23_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR23_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR23_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR23_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR23_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR13 - Device Physical Endpoint-3 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR13_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR13_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR13_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR13_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR13_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR03 - Device Physical Endpoint-3 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR03_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR03_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR03_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR03_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR03_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD3 - Device Physical Endpoint-3 Command */ /*! @{ */ #define USB3_CORE_DEPCMD3_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD3_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD3_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD3_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD3_CMDTYP_MASK) #define USB3_CORE_DEPCMD3_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD3_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD3_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD3_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD3_CMDIOC_MASK) #define USB3_CORE_DEPCMD3_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD3_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD3_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD3_CMDACT_SHIFT)) & USB3_CORE_DEPCMD3_CMDACT_MASK) #define USB3_CORE_DEPCMD3_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD3_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD3_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD3_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD3_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD3_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD3_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD3_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD3_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD3_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD3_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD3_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD3_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD3_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD3_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR24 - Device Physical Endpoint-4 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR24_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR24_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR24_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR24_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR24_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR14 - Device Physical Endpoint-4 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR14_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR14_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR14_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR14_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR14_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR04 - Device Physical Endpoint-4 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR04_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR04_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR04_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR04_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR04_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD4 - Device Physical Endpoint-4 Command */ /*! @{ */ #define USB3_CORE_DEPCMD4_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD4_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD4_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD4_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD4_CMDTYP_MASK) #define USB3_CORE_DEPCMD4_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD4_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD4_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD4_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD4_CMDIOC_MASK) #define USB3_CORE_DEPCMD4_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD4_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD4_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD4_CMDACT_SHIFT)) & USB3_CORE_DEPCMD4_CMDACT_MASK) #define USB3_CORE_DEPCMD4_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD4_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD4_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD4_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD4_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD4_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD4_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD4_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD4_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD4_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD4_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD4_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD4_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD4_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD4_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR25 - Device Physical Endpoint-5 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR25_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR25_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR25_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR25_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR25_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR15 - Device Physical Endpoint-5 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR15_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR15_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR15_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR15_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR15_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR05 - Device Physical Endpoint-5 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR05_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR05_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR05_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR05_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR05_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD5 - Device Physical Endpoint-5 Command */ /*! @{ */ #define USB3_CORE_DEPCMD5_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD5_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD5_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD5_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD5_CMDTYP_MASK) #define USB3_CORE_DEPCMD5_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD5_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD5_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD5_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD5_CMDIOC_MASK) #define USB3_CORE_DEPCMD5_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD5_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD5_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD5_CMDACT_SHIFT)) & USB3_CORE_DEPCMD5_CMDACT_MASK) #define USB3_CORE_DEPCMD5_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD5_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD5_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD5_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD5_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD5_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD5_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD5_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD5_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD5_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD5_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD5_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD5_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD5_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD5_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR26 - Device Physical Endpoint-6 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR26_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR26_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR26_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR26_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR26_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR16 - Device Physical Endpoint-6 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR16_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR16_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR16_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR16_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR16_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR06 - Device Physical Endpoint-6 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR06_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR06_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR06_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR06_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR06_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD6 - Device Physical Endpoint-6 Command */ /*! @{ */ #define USB3_CORE_DEPCMD6_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD6_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD6_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD6_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD6_CMDTYP_MASK) #define USB3_CORE_DEPCMD6_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD6_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD6_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD6_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD6_CMDIOC_MASK) #define USB3_CORE_DEPCMD6_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD6_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD6_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD6_CMDACT_SHIFT)) & USB3_CORE_DEPCMD6_CMDACT_MASK) #define USB3_CORE_DEPCMD6_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD6_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD6_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD6_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD6_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD6_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD6_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD6_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD6_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD6_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD6_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD6_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD6_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD6_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD6_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR27 - Device Physical Endpoint-7 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR27_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR27_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR27_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR27_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR27_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR17 - Device Physical Endpoint-7 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR17_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR17_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR17_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR17_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR17_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR07 - Device Physical Endpoint-7 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR07_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR07_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR07_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR07_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR07_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD7 - Device Physical Endpoint-7 Command */ /*! @{ */ #define USB3_CORE_DEPCMD7_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD7_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD7_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD7_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD7_CMDTYP_MASK) #define USB3_CORE_DEPCMD7_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD7_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD7_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD7_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD7_CMDIOC_MASK) #define USB3_CORE_DEPCMD7_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD7_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD7_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD7_CMDACT_SHIFT)) & USB3_CORE_DEPCMD7_CMDACT_MASK) #define USB3_CORE_DEPCMD7_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD7_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD7_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD7_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD7_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD7_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD7_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD7_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD7_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD7_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD7_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD7_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD7_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD7_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD7_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR28 - Device Physical Endpoint-8 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR28_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR28_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR28_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR28_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR28_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR18 - Device Physical Endpoint-8 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR18_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR18_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR18_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR18_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR18_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR08 - Device Physical Endpoint-8 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR08_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR08_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR08_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR08_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR08_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD8 - Device Physical Endpoint-8 Command */ /*! @{ */ #define USB3_CORE_DEPCMD8_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD8_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD8_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD8_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD8_CMDTYP_MASK) #define USB3_CORE_DEPCMD8_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD8_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD8_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD8_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD8_CMDIOC_MASK) #define USB3_CORE_DEPCMD8_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD8_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD8_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD8_CMDACT_SHIFT)) & USB3_CORE_DEPCMD8_CMDACT_MASK) #define USB3_CORE_DEPCMD8_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD8_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD8_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD8_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD8_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD8_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD8_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD8_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD8_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD8_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD8_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD8_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD8_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD8_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD8_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR29 - Device Physical Endpoint-9 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR29_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR29_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR29_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR29_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR29_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR19 - Device Physical Endpoint-9 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR19_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR19_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR19_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR19_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR19_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR09 - Device Physical Endpoint-9 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR09_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR09_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR09_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR09_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR09_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD9 - Device Physical Endpoint-9 Command */ /*! @{ */ #define USB3_CORE_DEPCMD9_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD9_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD9_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD9_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD9_CMDTYP_MASK) #define USB3_CORE_DEPCMD9_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD9_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD9_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD9_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD9_CMDIOC_MASK) #define USB3_CORE_DEPCMD9_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD9_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD9_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD9_CMDACT_SHIFT)) & USB3_CORE_DEPCMD9_CMDACT_MASK) #define USB3_CORE_DEPCMD9_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD9_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD9_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD9_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD9_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD9_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD9_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD9_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD9_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD9_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD9_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD9_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD9_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD9_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD9_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR210 - Device Physical Endpoint-10 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR210_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR210_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR210_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR210_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR210_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR110 - Device Physical Endpoint-10 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR110_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR110_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR110_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR110_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR110_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR010 - Device Physical Endpoint-10 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR010_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR010_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR010_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR010_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR010_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD10 - Device Physical Endpoint-10 Command */ /*! @{ */ #define USB3_CORE_DEPCMD10_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD10_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD10_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD10_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD10_CMDTYP_MASK) #define USB3_CORE_DEPCMD10_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD10_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD10_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD10_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD10_CMDIOC_MASK) #define USB3_CORE_DEPCMD10_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD10_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD10_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD10_CMDACT_SHIFT)) & USB3_CORE_DEPCMD10_CMDACT_MASK) #define USB3_CORE_DEPCMD10_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD10_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD10_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD10_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD10_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD10_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD10_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD10_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD10_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD10_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD10_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD10_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD10_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD10_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD10_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR211 - Device Physical Endpoint-11 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR211_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR211_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR211_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR211_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR211_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR111 - Device Physical Endpoint-11 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR111_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR111_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR111_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR111_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR111_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR011 - Device Physical Endpoint-11 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR011_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR011_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR011_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR011_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR011_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD11 - Device Physical Endpoint-11 Command */ /*! @{ */ #define USB3_CORE_DEPCMD11_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD11_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD11_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD11_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD11_CMDTYP_MASK) #define USB3_CORE_DEPCMD11_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD11_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD11_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD11_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD11_CMDIOC_MASK) #define USB3_CORE_DEPCMD11_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD11_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD11_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD11_CMDACT_SHIFT)) & USB3_CORE_DEPCMD11_CMDACT_MASK) #define USB3_CORE_DEPCMD11_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD11_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD11_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD11_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD11_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD11_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD11_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD11_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD11_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD11_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD11_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD11_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD11_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD11_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD11_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR212 - Device Physical Endpoint-12 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR212_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR212_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR212_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR212_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR212_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR112 - Device Physical Endpoint-12 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR112_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR112_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR112_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR112_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR112_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR012 - Device Physical Endpoint-12 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR012_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR012_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR012_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR012_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR012_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD12 - Device Physical Endpoint-12 Command */ /*! @{ */ #define USB3_CORE_DEPCMD12_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD12_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD12_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD12_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD12_CMDTYP_MASK) #define USB3_CORE_DEPCMD12_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD12_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD12_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD12_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD12_CMDIOC_MASK) #define USB3_CORE_DEPCMD12_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD12_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD12_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD12_CMDACT_SHIFT)) & USB3_CORE_DEPCMD12_CMDACT_MASK) #define USB3_CORE_DEPCMD12_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD12_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD12_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD12_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD12_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD12_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD12_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD12_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD12_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD12_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD12_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD12_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD12_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD12_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD12_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR213 - Device Physical Endpoint-13 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR213_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR213_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR213_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR213_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR213_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR113 - Device Physical Endpoint-13 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR113_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR113_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR113_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR113_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR113_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR013 - Device Physical Endpoint-13 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR013_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR013_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR013_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR013_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR013_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD13 - Device Physical Endpoint-13 Command */ /*! @{ */ #define USB3_CORE_DEPCMD13_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD13_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD13_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD13_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD13_CMDTYP_MASK) #define USB3_CORE_DEPCMD13_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD13_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD13_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD13_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD13_CMDIOC_MASK) #define USB3_CORE_DEPCMD13_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD13_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD13_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD13_CMDACT_SHIFT)) & USB3_CORE_DEPCMD13_CMDACT_MASK) #define USB3_CORE_DEPCMD13_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD13_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD13_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD13_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD13_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD13_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD13_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD13_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD13_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD13_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD13_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD13_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD13_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD13_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD13_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR214 - Device Physical Endpoint-14 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR214_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR214_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR214_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR214_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR214_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR114 - Device Physical Endpoint-14 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR114_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR114_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR114_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR114_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR114_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR014 - Device Physical Endpoint-14 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR014_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR014_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR014_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR014_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR014_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD14 - Device Physical Endpoint-14 Command */ /*! @{ */ #define USB3_CORE_DEPCMD14_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD14_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD14_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD14_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD14_CMDTYP_MASK) #define USB3_CORE_DEPCMD14_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD14_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD14_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD14_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD14_CMDIOC_MASK) #define USB3_CORE_DEPCMD14_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD14_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD14_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD14_CMDACT_SHIFT)) & USB3_CORE_DEPCMD14_CMDACT_MASK) #define USB3_CORE_DEPCMD14_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD14_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD14_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD14_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD14_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD14_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD14_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD14_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD14_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD14_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD14_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD14_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD14_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD14_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD14_COMMANDPARAM_MASK) /*! @} */ /*! @name DEPCMDPAR215 - Device Physical Endpoint-15 Command Parameter 2 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR215_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR215_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR215_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR215_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR215_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR115 - Device Physical Endpoint-15 Command Parameter 1 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR115_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR115_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR115_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR115_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR115_PARAMETER_MASK) /*! @} */ /*! @name DEPCMDPAR015 - Device Physical Endpoint-15 Command Parameter 0 */ /*! @{ */ #define USB3_CORE_DEPCMDPAR015_PARAMETER_MASK (0xFFFFFFFFU) #define USB3_CORE_DEPCMDPAR015_PARAMETER_SHIFT (0U) #define USB3_CORE_DEPCMDPAR015_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMDPAR015_PARAMETER_SHIFT)) & USB3_CORE_DEPCMDPAR015_PARAMETER_MASK) /*! @} */ /*! @name DEPCMD15 - Device Physical Endpoint-15 Command */ /*! @{ */ #define USB3_CORE_DEPCMD15_CMDTYP_MASK (0xFU) #define USB3_CORE_DEPCMD15_CMDTYP_SHIFT (0U) /*! CMDTYP - Command Type * 0b0001..Set Endpoint Configuration 64 or 96-bit Parameter */ #define USB3_CORE_DEPCMD15_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD15_CMDTYP_SHIFT)) & USB3_CORE_DEPCMD15_CMDTYP_MASK) #define USB3_CORE_DEPCMD15_CMDIOC_MASK (0x100U) #define USB3_CORE_DEPCMD15_CMDIOC_SHIFT (8U) /*! CMDIOC - CMDIOC Command Interrupt on Complete */ #define USB3_CORE_DEPCMD15_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD15_CMDIOC_SHIFT)) & USB3_CORE_DEPCMD15_CMDIOC_MASK) #define USB3_CORE_DEPCMD15_CMDACT_MASK (0x400U) #define USB3_CORE_DEPCMD15_CMDACT_SHIFT (10U) /*! CMDACT - Command Active */ #define USB3_CORE_DEPCMD15_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD15_CMDACT_SHIFT)) & USB3_CORE_DEPCMD15_CMDACT_MASK) #define USB3_CORE_DEPCMD15_HIPRI_FORCERM_MASK (0x800U) #define USB3_CORE_DEPCMD15_HIPRI_FORCERM_SHIFT (11U) /*! HIPRI_FORCERM - High Priority/Force RM */ #define USB3_CORE_DEPCMD15_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD15_HIPRI_FORCERM_SHIFT)) & USB3_CORE_DEPCMD15_HIPRI_FORCERM_MASK) #define USB3_CORE_DEPCMD15_CMDSTATUS_MASK (0xF000U) #define USB3_CORE_DEPCMD15_CMDSTATUS_SHIFT (12U) /*! CMDSTATUS - Command Completion Status */ #define USB3_CORE_DEPCMD15_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD15_CMDSTATUS_SHIFT)) & USB3_CORE_DEPCMD15_CMDSTATUS_MASK) #define USB3_CORE_DEPCMD15_COMMANDPARAM_MASK (0xFFFF0000U) #define USB3_CORE_DEPCMD15_COMMANDPARAM_SHIFT (16U) /*! COMMANDPARAM - Command Parameters or Event Parameters Command Parameters */ #define USB3_CORE_DEPCMD15_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEPCMD15_COMMANDPARAM_SHIFT)) & USB3_CORE_DEPCMD15_COMMANDPARAM_MASK) /*! @} */ /*! @name DEV_IMOD - Device Interrupt Moderation */ /*! @{ */ #define USB3_CORE_DEV_IMOD_DEVICE_IMODI_MASK (0xFFFFU) #define USB3_CORE_DEV_IMOD_DEVICE_IMODI_SHIFT (0U) /*! DEVICE_IMODI - Moderation Interval */ #define USB3_CORE_DEV_IMOD_DEVICE_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEV_IMOD_DEVICE_IMODI_SHIFT)) & USB3_CORE_DEV_IMOD_DEVICE_IMODI_MASK) #define USB3_CORE_DEV_IMOD_DEVICE_IMODC_MASK (0xFFFF0000U) #define USB3_CORE_DEV_IMOD_DEVICE_IMODC_SHIFT (16U) /*! DEVICE_IMODC - Interrupt Moderation Down Counter */ #define USB3_CORE_DEV_IMOD_DEVICE_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_DEV_IMOD_DEVICE_IMODC_SHIFT)) & USB3_CORE_DEV_IMOD_DEVICE_IMODC_MASK) /*! @} */ /*! @name BCFG - BC Configuration */ /*! @{ */ #define USB3_CORE_BCFG_CHIRP_EN_MASK (0x1U) #define USB3_CORE_BCFG_CHIRP_EN_SHIFT (0U) /*! CHIRP_EN - Chirp Enable */ #define USB3_CORE_BCFG_CHIRP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BCFG_CHIRP_EN_SHIFT)) & USB3_CORE_BCFG_CHIRP_EN_MASK) #define USB3_CORE_BCFG_IDDIG_SEL_MASK (0x2U) #define USB3_CORE_BCFG_IDDIG_SEL_SHIFT (1U) /*! IDDIG_SEL - IDDIG Select * 0b0..The core determines the ID pin value from utmiotg_iddig input. * 0b1..The core determines the ID pin value from RID_A and RID_GND inputs of the Battery Charger. */ #define USB3_CORE_BCFG_IDDIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BCFG_IDDIG_SEL_SHIFT)) & USB3_CORE_BCFG_IDDIG_SEL_MASK) /*! @} */ /*! @name BCEVT - BC Event */ /*! @{ */ #define USB3_CORE_BCEVT_MultValIdBc_MASK (0x1FU) #define USB3_CORE_BCEVT_MultValIdBc_SHIFT (0U) /*! MultValIdBc - Multi Valued ID pin */ #define USB3_CORE_BCEVT_MultValIdBc(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BCEVT_MultValIdBc_SHIFT)) & USB3_CORE_BCEVT_MultValIdBc_MASK) #define USB3_CORE_BCEVT_MV_ChngEvnt_MASK (0x1000000U) #define USB3_CORE_BCEVT_MV_ChngEvnt_SHIFT (24U) /*! MV_ChngEvnt - Multi-Valued Input Changed Event */ #define USB3_CORE_BCEVT_MV_ChngEvnt(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BCEVT_MV_ChngEvnt_SHIFT)) & USB3_CORE_BCEVT_MV_ChngEvnt_MASK) /*! @} */ /*! @name BCEVTEN - BC Event Enable */ /*! @{ */ #define USB3_CORE_BCEVTEN_MV_ChngEvntEna_MASK (0x1000000U) #define USB3_CORE_BCEVTEN_MV_ChngEvntEna_SHIFT (24U) /*! MV_ChngEvntEna - Multi-Valued Input changed Event Enable */ #define USB3_CORE_BCEVTEN_MV_ChngEvntEna(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BCEVTEN_MV_ChngEvntEna_SHIFT)) & USB3_CORE_BCEVTEN_MV_ChngEvntEna_MASK) /*! @} */ /*! @name LU1LFPSRXTIM0 - U1/U2 LFPS RX Timer */ /*! @{ */ #define USB3_CORE_LU1LFPSRXTIM0_U1U2_EXIT_RSP_RX_CLK_MASK (0xFFU) #define USB3_CORE_LU1LFPSRXTIM0_U1U2_EXIT_RSP_RX_CLK_SHIFT (0U) /*! U1U2_EXIT_RSP_RX_CLK - Programmable U1U2 EXIT RESP RX CLKS * 0b00000001..8ns * 0b00000010..16ns * 0b00000011..24ns, and so on */ #define USB3_CORE_LU1LFPSRXTIM0_U1U2_EXIT_RSP_RX_CLK(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LU1LFPSRXTIM0_U1U2_EXIT_RSP_RX_CLK_SHIFT)) & USB3_CORE_LU1LFPSRXTIM0_U1U2_EXIT_RSP_RX_CLK_MASK) #define USB3_CORE_LU1LFPSRXTIM0_U1U2_LFPS_EXIT_RX_CLK_MASK (0xFF00U) #define USB3_CORE_LU1LFPSRXTIM0_U1U2_LFPS_EXIT_RX_CLK_SHIFT (8U) /*! U1U2_LFPS_EXIT_RX_CLK - Programmable U1U2 LFPS EXIT RX CLKS * 0b00000001..8ns * 0b00000010..16ns * 0b00000011..24ns, and so on */ #define USB3_CORE_LU1LFPSRXTIM0_U1U2_LFPS_EXIT_RX_CLK(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LU1LFPSRXTIM0_U1U2_LFPS_EXIT_RX_CLK_SHIFT)) & USB3_CORE_LU1LFPSRXTIM0_U1U2_LFPS_EXIT_RX_CLK_MASK) /*! @} */ /*! @name LINK_SETTINGS0 - Link Setting */ /*! @{ */ #define USB3_CORE_LINK_SETTINGS0_PM_ENTRY_TIMER_US_MASK (0xF00000U) #define USB3_CORE_LINK_SETTINGS0_PM_ENTRY_TIMER_US_SHIFT (20U) /*! PM_ENTRY_TIMER_US - Programmable PM_ENTRY_TIMER */ #define USB3_CORE_LINK_SETTINGS0_PM_ENTRY_TIMER_US(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LINK_SETTINGS0_PM_ENTRY_TIMER_US_SHIFT)) & USB3_CORE_LINK_SETTINGS0_PM_ENTRY_TIMER_US_MASK) #define USB3_CORE_LINK_SETTINGS0_PM_LC_TIMER_US_MASK (0x7000000U) #define USB3_CORE_LINK_SETTINGS0_PM_LC_TIMER_US_SHIFT (24U) /*! PM_LC_TIMER_US - Programmable PM_LC_TIMER */ #define USB3_CORE_LINK_SETTINGS0_PM_LC_TIMER_US(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LINK_SETTINGS0_PM_LC_TIMER_US_SHIFT)) & USB3_CORE_LINK_SETTINGS0_PM_LC_TIMER_US_MASK) #define USB3_CORE_LINK_SETTINGS0_U1_RESID_TIMER_US_MASK (0x70000000U) #define USB3_CORE_LINK_SETTINGS0_U1_RESID_TIMER_US_SHIFT (28U) /*! U1_RESID_TIMER_US - Programmable U1 MIN RESIDENCY TIMER */ #define USB3_CORE_LINK_SETTINGS0_U1_RESID_TIMER_US(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LINK_SETTINGS0_U1_RESID_TIMER_US_SHIFT)) & USB3_CORE_LINK_SETTINGS0_U1_RESID_TIMER_US_MASK) /*! @} */ /*! @name LLUCTL0 - Link User Control */ /*! @{ */ #define USB3_CORE_LLUCTL0_NO_UX_EXIT_P0_TRANS_MASK (0x20U) #define USB3_CORE_LLUCTL0_NO_UX_EXIT_P0_TRANS_SHIFT (5U) #define USB3_CORE_LLUCTL0_NO_UX_EXIT_P0_TRANS(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LLUCTL0_NO_UX_EXIT_P0_TRANS_SHIFT)) & USB3_CORE_LLUCTL0_NO_UX_EXIT_P0_TRANS_MASK) #define USB3_CORE_LLUCTL0_MASK_PIPE_RESET_MASK (0x80U) #define USB3_CORE_LLUCTL0_MASK_PIPE_RESET_SHIFT (7U) /*! MASK_PIPE_RESET - Mask Pipe Reset */ #define USB3_CORE_LLUCTL0_MASK_PIPE_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LLUCTL0_MASK_PIPE_RESET_SHIFT)) & USB3_CORE_LLUCTL0_MASK_PIPE_RESET_MASK) #define USB3_CORE_LLUCTL0_EN_RESET_PIPE_AFTER_PHY_MUX_MASK (0x800U) #define USB3_CORE_LLUCTL0_EN_RESET_PIPE_AFTER_PHY_MUX_SHIFT (11U) #define USB3_CORE_LLUCTL0_EN_RESET_PIPE_AFTER_PHY_MUX(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LLUCTL0_EN_RESET_PIPE_AFTER_PHY_MUX_SHIFT)) & USB3_CORE_LLUCTL0_EN_RESET_PIPE_AFTER_PHY_MUX_MASK) #define USB3_CORE_LLUCTL0_U2P3CPMok_MASK (0x1000U) #define USB3_CORE_LLUCTL0_U2P3CPMok_SHIFT (12U) /*! U2P3CPMok - P3CPM OK for U2/SSInactive * 0b0..During link state U2/SS.Inactive, put PHY in P2 * 0b1..During link state U2/SS.Inactive, put PHY in P3CPM */ #define USB3_CORE_LLUCTL0_U2P3CPMok(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LLUCTL0_U2P3CPMok_SHIFT)) & USB3_CORE_LLUCTL0_U2P3CPMok_MASK) #define USB3_CORE_LLUCTL0_DISRXDET_LTSSM_TIMER_OVRRD_MASK (0x800000U) #define USB3_CORE_LLUCTL0_DISRXDET_LTSSM_TIMER_OVRRD_SHIFT (23U) #define USB3_CORE_LLUCTL0_DISRXDET_LTSSM_TIMER_OVRRD(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LLUCTL0_DISRXDET_LTSSM_TIMER_OVRRD_SHIFT)) & USB3_CORE_LLUCTL0_DISRXDET_LTSSM_TIMER_OVRRD_MASK) #define USB3_CORE_LLUCTL0_SUPPORT_P4_MASK (0x10000000U) #define USB3_CORE_LLUCTL0_SUPPORT_P4_SHIFT (28U) /*! SUPPORT_P4 - Support PHY P3.CPM and P4 Power States */ #define USB3_CORE_LLUCTL0_SUPPORT_P4(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LLUCTL0_SUPPORT_P4_SHIFT)) & USB3_CORE_LLUCTL0_SUPPORT_P4_MASK) #define USB3_CORE_LLUCTL0_SUPPORT_P4_PG_MASK (0x20000000U) #define USB3_CORE_LLUCTL0_SUPPORT_P4_PG_SHIFT (29U) /*! SUPPORT_P4_PG - PHY P4 Power Gate Mode (PG) Enabled */ #define USB3_CORE_LLUCTL0_SUPPORT_P4_PG(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LLUCTL0_SUPPORT_P4_PG_SHIFT)) & USB3_CORE_LLUCTL0_SUPPORT_P4_PG_MASK) /*! @} */ /*! @name LPTMDPDELAY0 - Link Datapath Delay */ /*! @{ */ #define USB3_CORE_LPTMDPDELAY0_P3CPMP4_RESIDENCY_MASK (0x3FFC00U) #define USB3_CORE_LPTMDPDELAY0_P3CPMP4_RESIDENCY_SHIFT (10U) /*! P3CPMP4_RESIDENCY - Programmable PM_ENTRY_TIMER */ #define USB3_CORE_LPTMDPDELAY0_P3CPMP4_RESIDENCY(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_LPTMDPDELAY0_P3CPMP4_RESIDENCY_SHIFT)) & USB3_CORE_LPTMDPDELAY0_P3CPMP4_RESIDENCY_MASK) /*! @} */ /*! @name BU3RHBDBG - U3 Root Hub Debug */ /*! @{ */ #define USB3_CORE_BU3RHBDBG_TPCFG_TOUT_CTRL_MASK (0x8U) #define USB3_CORE_BU3RHBDBG_TPCFG_TOUT_CTRL_SHIFT (3U) /*! TPCFG_TOUT_CTRL * 0b0..The port configuration timeout counter does not reset if the link enters recovery or exits U0. * 0b1..The port configuration timeout counter resets when the link is not in U0. */ #define USB3_CORE_BU3RHBDBG_TPCFG_TOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BU3RHBDBG_TPCFG_TOUT_CTRL_SHIFT)) & USB3_CORE_BU3RHBDBG_TPCFG_TOUT_CTRL_MASK) /*! @} */ /*! @name BRSERRCNT - Block RAM Single Bit Error Count */ /*! @{ */ #define USB3_CORE_BRSERRCNT_RAM0SERRCNT_MASK (0xFFU) #define USB3_CORE_BRSERRCNT_RAM0SERRCNT_SHIFT (0U) /*! RAM0SERRCNT - RAM0 Single bit Error Count */ #define USB3_CORE_BRSERRCNT_RAM0SERRCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRSERRCNT_RAM0SERRCNT_SHIFT)) & USB3_CORE_BRSERRCNT_RAM0SERRCNT_MASK) #define USB3_CORE_BRSERRCNT_RAM1SERRCNT_MASK (0xFF00U) #define USB3_CORE_BRSERRCNT_RAM1SERRCNT_SHIFT (8U) /*! RAM1SERRCNT - RAM1 Single bit Error Count */ #define USB3_CORE_BRSERRCNT_RAM1SERRCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRSERRCNT_RAM1SERRCNT_SHIFT)) & USB3_CORE_BRSERRCNT_RAM1SERRCNT_MASK) #define USB3_CORE_BRSERRCNT_RAM2SERRCNT_MASK (0xFF0000U) #define USB3_CORE_BRSERRCNT_RAM2SERRCNT_SHIFT (16U) /*! RAM2SERRCNT - RAM2 Single bit Error Count */ #define USB3_CORE_BRSERRCNT_RAM2SERRCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRSERRCNT_RAM2SERRCNT_SHIFT)) & USB3_CORE_BRSERRCNT_RAM2SERRCNT_MASK) /*! @} */ /*! @name BRMERRCNT - Block RAM Multiple Bit Error Count */ /*! @{ */ #define USB3_CORE_BRMERRCNT_RAM0MERRCNT_MASK (0xFFU) #define USB3_CORE_BRMERRCNT_RAM0MERRCNT_SHIFT (0U) /*! RAM0MERRCNT - RAM0 Multiple bit Error Count */ #define USB3_CORE_BRMERRCNT_RAM0MERRCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRMERRCNT_RAM0MERRCNT_SHIFT)) & USB3_CORE_BRMERRCNT_RAM0MERRCNT_MASK) #define USB3_CORE_BRMERRCNT_RAM1MERRCNT_MASK (0xFF00U) #define USB3_CORE_BRMERRCNT_RAM1MERRCNT_SHIFT (8U) /*! RAM1MERRCNT - RAM1 Multiple bit Error Count */ #define USB3_CORE_BRMERRCNT_RAM1MERRCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRMERRCNT_RAM1MERRCNT_SHIFT)) & USB3_CORE_BRMERRCNT_RAM1MERRCNT_MASK) #define USB3_CORE_BRMERRCNT_RAM2MERRCNT_MASK (0xFF0000U) #define USB3_CORE_BRMERRCNT_RAM2MERRCNT_SHIFT (16U) /*! RAM2MERRCNT - RAM2 Multiple bit Error Count */ #define USB3_CORE_BRMERRCNT_RAM2MERRCNT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRMERRCNT_RAM2MERRCNT_SHIFT)) & USB3_CORE_BRMERRCNT_RAM2MERRCNT_MASK) /*! @} */ /*! @name BRMECCERR - Block RAM ECC Error Vector */ /*! @{ */ #define USB3_CORE_BRMECCERR_RAMMERRVEC_MASK (0x7U) #define USB3_CORE_BRMECCERR_RAMMERRVEC_SHIFT (0U) /*! RAMMERRVEC - RAM Multiple Error Vector */ #define USB3_CORE_BRMECCERR_RAMMERRVEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRMECCERR_RAMMERRVEC_SHIFT)) & USB3_CORE_BRMECCERR_RAMMERRVEC_MASK) #define USB3_CORE_BRMECCERR_RAMSERRVEC_MASK (0x38U) #define USB3_CORE_BRMECCERR_RAMSERRVEC_SHIFT (3U) /*! RAMSERRVEC - RAM Single Error Vector */ #define USB3_CORE_BRMECCERR_RAMSERRVEC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRMECCERR_RAMSERRVEC_SHIFT)) & USB3_CORE_BRMECCERR_RAMSERRVEC_MASK) #define USB3_CORE_BRMECCERR_RAMMERR_MASK (0x40U) #define USB3_CORE_BRMECCERR_RAMMERR_SHIFT (6U) /*! RAMMERR - RAM Multiple bit Error Status */ #define USB3_CORE_BRMECCERR_RAMMERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRMECCERR_RAMMERR_SHIFT)) & USB3_CORE_BRMECCERR_RAMMERR_MASK) #define USB3_CORE_BRMECCERR_RAMSERR_MASK (0x80U) #define USB3_CORE_BRMECCERR_RAMSERR_SHIFT (7U) /*! RAMSERR - RAM Single bit Error Status */ #define USB3_CORE_BRMECCERR_RAMSERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRMECCERR_RAMSERR_SHIFT)) & USB3_CORE_BRMECCERR_RAMSERR_MASK) /*! @} */ /*! @name BRERRCTL - Block RAM ECC Error Control */ /*! @{ */ #define USB3_CORE_BRERRCTL_RMERRCLR_MASK (0x1U) #define USB3_CORE_BRERRCTL_RMERRCLR_SHIFT (0U) /*! RMERRCLR - RAM Multiple bit Error Clear */ #define USB3_CORE_BRERRCTL_RMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRERRCTL_RMERRCLR_SHIFT)) & USB3_CORE_BRERRCTL_RMERRCLR_MASK) #define USB3_CORE_BRERRCTL_RSERRCLR_MASK (0x2U) #define USB3_CORE_BRERRCTL_RSERRCLR_SHIFT (1U) /*! RSERRCLR - RAM Single bit Error Clear */ #define USB3_CORE_BRERRCTL_RSERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRERRCTL_RSERRCLR_SHIFT)) & USB3_CORE_BRERRCTL_RSERRCLR_MASK) #define USB3_CORE_BRERRCTL_ECCEN_MASK (0x4U) #define USB3_CORE_BRERRCTL_ECCEN_SHIFT (2U) /*! ECCEN - ECC Enable (1) or Disable (0) */ #define USB3_CORE_BRERRCTL_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRERRCTL_ECCEN_SHIFT)) & USB3_CORE_BRERRCTL_ECCEN_MASK) #define USB3_CORE_BRERRCTL_ECCERRINJECT_MASK (0x8U) #define USB3_CORE_BRERRCTL_ECCERRINJECT_SHIFT (3U) /*! ECCERRINJECT * 0b0..No ECC error injected * 0b1..Inject ECC error */ #define USB3_CORE_BRERRCTL_ECCERRINJECT(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRERRCTL_ECCERRINJECT_SHIFT)) & USB3_CORE_BRERRCTL_ECCERRINJECT_MASK) /*! @} */ /*! @name BRAMADDRERR - Block RAM0 Address Error..Block RAM2 Address Error */ /*! @{ */ #define USB3_CORE_BRAMADDRERR_RAM0ADDRLOC_MASK (0xFFFFU) #define USB3_CORE_BRAMADDRERR_RAM0ADDRLOC_SHIFT (0U) /*! RAM0ADDRLOC - RAM0 Address Location */ #define USB3_CORE_BRAMADDRERR_RAM0ADDRLOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRAMADDRERR_RAM0ADDRLOC_SHIFT)) & USB3_CORE_BRAMADDRERR_RAM0ADDRLOC_MASK) #define USB3_CORE_BRAMADDRERR_RAM1ADDRLOC_MASK (0xFFFFU) #define USB3_CORE_BRAMADDRERR_RAM1ADDRLOC_SHIFT (0U) /*! RAM1ADDRLOC - RAM1 Address Location */ #define USB3_CORE_BRAMADDRERR_RAM1ADDRLOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRAMADDRERR_RAM1ADDRLOC_SHIFT)) & USB3_CORE_BRAMADDRERR_RAM1ADDRLOC_MASK) #define USB3_CORE_BRAMADDRERR_RAM2ADDRLOC_MASK (0xFFFFU) #define USB3_CORE_BRAMADDRERR_RAM2ADDRLOC_SHIFT (0U) /*! RAM2ADDRLOC - RAM2 Address Location */ #define USB3_CORE_BRAMADDRERR_RAM2ADDRLOC(x) (((uint32_t)(((uint32_t)(x)) << USB3_CORE_BRAMADDRERR_RAM2ADDRLOC_SHIFT)) & USB3_CORE_BRAMADDRERR_RAM2ADDRLOC_MASK) /*! @} */ /* The count of USB3_CORE_BRAMADDRERR */ #define USB3_CORE_BRAMADDRERR_COUNT (3U) /*! * @} */ /* end of group USB3_CORE_Register_Masks */ /* USB3_CORE - Peripheral instance base addresses */ /** Peripheral HSIO__USB_3_01__USB3 base address */ #define HSIO__USB_3_01__USB3_BASE (0x4C100000u) /** Peripheral HSIO__USB_3_01__USB3 base pointer */ #define HSIO__USB_3_01__USB3 ((USB3_CORE_Type *)HSIO__USB_3_01__USB3_BASE) /** Array initializer of USB3_CORE peripheral base addresses */ #define USB3_CORE_BASE_ADDRS { HSIO__USB_3_01__USB3_BASE } /** Array initializer of USB3_CORE peripheral base pointers */ #define USB3_CORE_BASE_PTRS { HSIO__USB_3_01__USB3 } /*! * @} */ /* end of group USB3_CORE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB3_GLUE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_GLUE_Peripheral_Access_Layer USB3_GLUE Peripheral Access Layer * @{ */ /** USB3_GLUE - Register Layout Typedef */ typedef struct { __IO uint32_t USB3_CTRL0; /**< USB3 Controller 0, offset: 0x0 */ __IO uint32_t USB3_CTRL1; /**< USB3 Controller 1, offset: 0x4 */ uint8_t RESERVED_0[8]; uint32_t USB3_DBG0; /**< USB3 Debug 0, offset: 0x10 */ uint32_t USB3_DBG1; /**< USB3 Debug 1, offset: 0x14 */ uint32_t USB3_DBG2; /**< USB3 Debug 2, offset: 0x18 */ uint8_t RESERVED_1[4]; __I uint32_t USB3_STS0; /**< USB3 Status 0, offset: 0x20 */ uint8_t RESERVED_2[28]; __IO uint32_t PHY_CTRL0; /**< USBPHY Control 0, offset: 0x40 */ __IO uint32_t PHY_CTRL1; /**< USBPHY Control 1, offset: 0x44 */ __IO uint32_t PHY_CTRL2; /**< USBPHY Control 2, offset: 0x48 */ __IO uint32_t PHY_CTRL3; /**< USBPHY Control 3, offset: 0x4C */ __IO uint32_t PHY_CTRL4; /**< USBPHY Control 4, offset: 0x50 */ __IO uint32_t PHY_CTRL5; /**< USBPHY Control 5, offset: 0x54 */ __IO uint32_t PHY_CTRL6; /**< USBPHY Control 6, offset: 0x58 */ uint8_t RESERVED_3[20]; __IO uint32_t PHY_CRCTL; /**< USB3_PHY CR Control, offset: 0x70 */ __I uint32_t PHY_CRSR; /**< USB3_PHY CR Status, offset: 0x74 */ uint8_t RESERVED_4[8]; __IO uint32_t PHY_STATUS0; /**< USB3_PHY Status 0, offset: 0x80 */ } USB3_GLUE_Type; /* ---------------------------------------------------------------------------- -- USB3_GLUE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_GLUE_Register_Masks USB3_GLUE Register Masks * @{ */ /*! @name USB3_CTRL0 - USB3 Controller 0 */ /*! @{ */ #define USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GS_MASK (0x1U) #define USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GS_SHIFT (0U) /*! BUS_CLKEN_GS - AHB/AXI/OCP Slave Interface Clock Enable * 0b0..Disables clock * 0b1..Enables clock */ #define USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GS(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GS_SHIFT)) & USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GS_MASK) #define USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GM_MASK (0x2U) #define USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GM_SHIFT (1U) /*! BUS_CLKEN_GM - AHB/AXI/OCP Master Interface Clock Enable * 0b0..Disables clock * 0b1..Enables clock */ #define USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GM(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GM_SHIFT)) & USB3_GLUE_USB3_CTRL0_BUS_CLKEN_GM_MASK) #define USB3_GLUE_USB3_CTRL0_BIGENDIAN_GS_MASK (0x4U) #define USB3_GLUE_USB3_CTRL0_BIGENDIAN_GS_SHIFT (2U) /*! BIGENDIAN_GS - Slave Big Endian Select (AHB/AXI/Native) * 0b0..Little endian * 0b1..Big endian */ #define USB3_GLUE_USB3_CTRL0_BIGENDIAN_GS(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_BIGENDIAN_GS_SHIFT)) & USB3_GLUE_USB3_CTRL0_BIGENDIAN_GS_MASK) #define USB3_GLUE_USB3_CTRL0_PME_EN_MASK (0x8U) #define USB3_GLUE_USB3_CTRL0_PME_EN_SHIFT (3U) /*! PME_EN - PME Enable * 0b0..Disables PME generation * 0b1..Enables PME generation */ #define USB3_GLUE_USB3_CTRL0_PME_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_PME_EN_SHIFT)) & USB3_GLUE_USB3_CTRL0_PME_EN_MASK) #define USB3_GLUE_USB3_CTRL0_HOST_U2_PORT_DISABLE_MASK (0x40U) #define USB3_GLUE_USB3_CTRL0_HOST_U2_PORT_DISABLE_SHIFT (6U) /*! HOST_U2_PORT_DISABLE - USB 2.0 Port Disable Control * 0b0..Port enabled * 0b1..Port disabled. This signal stops reporting connect/disconnect events of USB2 port and keeps the port in disabled state */ #define USB3_GLUE_USB3_CTRL0_HOST_U2_PORT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_HOST_U2_PORT_DISABLE_SHIFT)) & USB3_GLUE_USB3_CTRL0_HOST_U2_PORT_DISABLE_MASK) #define USB3_GLUE_USB3_CTRL0_HOST_U3_PORT_DISABLE_MASK (0x80U) #define USB3_GLUE_USB3_CTRL0_HOST_U3_PORT_DISABLE_SHIFT (7U) /*! HOST_U3_PORT_DISABLE - USB 3.0 SS Port Disable Control * 0b0..Port enabled * 0b1..Port disabled */ #define USB3_GLUE_USB3_CTRL0_HOST_U3_PORT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_HOST_U3_PORT_DISABLE_SHIFT)) & USB3_GLUE_USB3_CTRL0_HOST_U3_PORT_DISABLE_MASK) #define USB3_GLUE_USB3_CTRL0_BUS_FILTER_BYPASS_MASK (0xF00U) #define USB3_GLUE_USB3_CTRL0_BUS_FILTER_BYPASS_SHIFT (8U) /*! BUS_FILTER_BYPASS - Bus Filter Bypass */ #define USB3_GLUE_USB3_CTRL0_BUS_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_BUS_FILTER_BYPASS_SHIFT)) & USB3_GLUE_USB3_CTRL0_BUS_FILTER_BYPASS_MASK) #define USB3_GLUE_USB3_CTRL0_HOST_PORT_POWER_CONTROL_PRESENT_MASK (0x1000U) #define USB3_GLUE_USB3_CTRL0_HOST_PORT_POWER_CONTROL_PRESENT_SHIFT (12U) /*! HOST_PORT_POWER_CONTROL_PRESENT - Host Port Power Control * 0b0..Indicates that the port does not have port power switches * 0b1..Indicates that the port has port power switches */ #define USB3_GLUE_USB3_CTRL0_HOST_PORT_POWER_CONTROL_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_HOST_PORT_POWER_CONTROL_PRESENT_SHIFT)) & USB3_GLUE_USB3_CTRL0_HOST_PORT_POWER_CONTROL_PRESENT_MASK) #define USB3_GLUE_USB3_CTRL0_xHC_BME_MASK (0x4000U) #define USB3_GLUE_USB3_CTRL0_xHC_BME_SHIFT (14U) /*! xHC_BME - Disable Bus Mastering Capability of xHC * 0b0..Bus mastering capability is disabled. The host controller cannot use the bus master interface * 0b1..Bus mastering capability is enabled */ #define USB3_GLUE_USB3_CTRL0_xHC_BME(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_xHC_BME_SHIFT)) & USB3_GLUE_USB3_CTRL0_xHC_BME_MASK) #define USB3_GLUE_USB3_CTRL0_FLADJ_30MHZ_REG_MASK (0x3F0000U) #define USB3_GLUE_USB3_CTRL0_FLADJ_30MHZ_REG_SHIFT (16U) /*! FLADJ_30MHZ_REG - HS Jitter Adjustment */ #define USB3_GLUE_USB3_CTRL0_FLADJ_30MHZ_REG(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_FLADJ_30MHZ_REG_SHIFT)) & USB3_GLUE_USB3_CTRL0_FLADJ_30MHZ_REG_MASK) #define USB3_GLUE_USB3_CTRL0_HUB_PORT_PERM_ATTACH_MASK (0xC00000U) #define USB3_GLUE_USB3_CTRL0_HUB_PORT_PERM_ATTACH_SHIFT (22U) /*! HUB_PORT_PERM_ATTACH - Hub Port Permanently Attached * 0b00..Not permanently attached * 0b01..Permanently attached */ #define USB3_GLUE_USB3_CTRL0_HUB_PORT_PERM_ATTACH(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_HUB_PORT_PERM_ATTACH_SHIFT)) & USB3_GLUE_USB3_CTRL0_HUB_PORT_PERM_ATTACH_MASK) #define USB3_GLUE_USB3_CTRL0_UTMIOTG_IDDIG_SEL_MASK (0x1000000U) #define USB3_GLUE_USB3_CTRL0_UTMIOTG_IDDIG_SEL_SHIFT (24U) /*! UTMIOTG_IDDIG_SEL - IDDIG Source Select Signal */ #define USB3_GLUE_USB3_CTRL0_UTMIOTG_IDDIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_UTMIOTG_IDDIG_SEL_SHIFT)) & USB3_GLUE_USB3_CTRL0_UTMIOTG_IDDIG_SEL_MASK) #define USB3_GLUE_USB3_CTRL0_StartRxDetU3RxDet_MASK (0x2000000U) #define USB3_GLUE_USB3_CTRL0_StartRxDetU3RxDet_SHIFT (25U) /*! StartRxDetU3RxDet - StartRxdetU3RxDet of USB 3.0 SS Ports */ #define USB3_GLUE_USB3_CTRL0_StartRxDetU3RxDet(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_StartRxDetU3RxDet_SHIFT)) & USB3_GLUE_USB3_CTRL0_StartRxDetU3RxDet_MASK) #define USB3_GLUE_USB3_CTRL0_USB3_CTRL_RESET_MASK (0x80000000U) #define USB3_GLUE_USB3_CTRL0_USB3_CTRL_RESET_SHIFT (31U) /*! USB3_CTRL_RESET - Reset Controller * 0b0..Do not reset the controller * 0b1..Resets the controller */ #define USB3_GLUE_USB3_CTRL0_USB3_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL0_USB3_CTRL_RESET_SHIFT)) & USB3_GLUE_USB3_CTRL0_USB3_CTRL_RESET_MASK) /*! @} */ /*! @name USB3_CTRL1 - USB3 Controller 1 */ /*! @{ */ #define USB3_GLUE_USB3_CTRL1_OB_SEL_MASK (0x1FU) #define USB3_GLUE_USB3_CTRL1_OB_SEL_SHIFT (0U) /*! OB_SEL - Observe Select */ #define USB3_GLUE_USB3_CTRL1_OB_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL1_OB_SEL_SHIFT)) & USB3_GLUE_USB3_CTRL1_OB_SEL_MASK) #define USB3_GLUE_USB3_CTRL1_OC_POLARITY_MASK (0x10000U) #define USB3_GLUE_USB3_CTRL1_OC_POLARITY_SHIFT (16U) /*! OC_POLARITY - OC Pin Polarity Control * 0b0..ipp_ind_usb3_overcurrent takes effect when it is high * 0b1..ipp_ind_usb3_overcurrent takes effect when it is low */ #define USB3_GLUE_USB3_CTRL1_OC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL1_OC_POLARITY_SHIFT)) & USB3_GLUE_USB3_CTRL1_OC_POLARITY_MASK) #define USB3_GLUE_USB3_CTRL1_POWER_POLARITY_MASK (0x20000U) #define USB3_GLUE_USB3_CTRL1_POWER_POLARITY_SHIFT (17U) /*! POWER_POLARITY - Power Pin Polarity Control * 0b0..ipp_do_usb3_power takes effect when usb3_utmi_drvvbus0 is high * 0b1..ipp_do_usb3_power takes effect when usb3_utmi_drvvbus0 is low */ #define USB3_GLUE_USB3_CTRL1_POWER_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_CTRL1_POWER_POLARITY_SHIFT)) & USB3_GLUE_USB3_CTRL1_POWER_POLARITY_MASK) /*! @} */ /*! @name USB3_STS0 - USB3 Status 0 */ /*! @{ */ #define USB3_GLUE_USB3_STS0_HOST_CURRENT_BELT_MASK (0xFFFU) #define USB3_GLUE_USB3_STS0_HOST_CURRENT_BELT_SHIFT (0U) /*! HOST_CURRENT_BELT - Current Belt Value */ #define USB3_GLUE_USB3_STS0_HOST_CURRENT_BELT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_STS0_HOST_CURRENT_BELT_SHIFT)) & USB3_GLUE_USB3_STS0_HOST_CURRENT_BELT_MASK) #define USB3_GLUE_USB3_STS0_HOST_SYSTEM_ERR_MASK (0x1000U) #define USB3_GLUE_USB3_STS0_HOST_SYSTEM_ERR_SHIFT (12U) /*! HOST_SYSTEM_ERR - Host System Error */ #define USB3_GLUE_USB3_STS0_HOST_SYSTEM_ERR(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_STS0_HOST_SYSTEM_ERR_SHIFT)) & USB3_GLUE_USB3_STS0_HOST_SYSTEM_ERR_MASK) #define USB3_GLUE_USB3_STS0_BC_CHIRP_ON_MASK (0x2000U) #define USB3_GLUE_USB3_STS0_BC_CHIRP_ON_SHIFT (13U) /*! BC_CHIRP_ON - Chirp Signal Enable */ #define USB3_GLUE_USB3_STS0_BC_CHIRP_ON(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_STS0_BC_CHIRP_ON_SHIFT)) & USB3_GLUE_USB3_STS0_BC_CHIRP_ON_MASK) #define USB3_GLUE_USB3_STS0_PME_GENERATION_MASK (0x4000U) #define USB3_GLUE_USB3_STS0_PME_GENERATION_SHIFT (14U) /*! PME_GENERATION - PME# Generation */ #define USB3_GLUE_USB3_STS0_PME_GENERATION(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_STS0_PME_GENERATION_SHIFT)) & USB3_GLUE_USB3_STS0_PME_GENERATION_MASK) #define USB3_GLUE_USB3_STS0_IDDIG_MASK (0x8000U) #define USB3_GLUE_USB3_STS0_IDDIG_SHIFT (15U) /*! IDDIG - IDDIG * 0b1..Connected plug is a mini-B plug * 0b0..Connected plug is a mini-A plug */ #define USB3_GLUE_USB3_STS0_IDDIG(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_STS0_IDDIG_SHIFT)) & USB3_GLUE_USB3_STS0_IDDIG_MASK) #define USB3_GLUE_USB3_STS0_DisRxDetU3RxDet_ACK_MASK (0x10000U) #define USB3_GLUE_USB3_STS0_DisRxDetU3RxDet_ACK_SHIFT (16U) /*! DisRxDetU3RxDet_ACK - DisRxDetU3RxDet Acknowledgement */ #define USB3_GLUE_USB3_STS0_DisRxDetU3RxDet_ACK(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_STS0_DisRxDetU3RxDet_ACK_SHIFT)) & USB3_GLUE_USB3_STS0_DisRxDetU3RxDet_ACK_MASK) #define USB3_GLUE_USB3_STS0_CLK_GATE_CTRL_MASK (0xE0000U) #define USB3_GLUE_USB3_STS0_CLK_GATE_CTRL_SHIFT (17U) /*! CLK_GATE_CTRL - Clock Gating Control */ #define USB3_GLUE_USB3_STS0_CLK_GATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_USB3_STS0_CLK_GATE_CTRL_SHIFT)) & USB3_GLUE_USB3_STS0_CLK_GATE_CTRL_MASK) /*! @} */ /*! @name PHY_CTRL0 - USBPHY Control 0 */ /*! @{ */ #define USB3_GLUE_PHY_CTRL0_REF_USE_PAD_MASK (0x1U) #define USB3_GLUE_PHY_CTRL0_REF_USE_PAD_SHIFT (0U) /*! REF_USE_PAD - Reference clock Use Pad */ #define USB3_GLUE_PHY_CTRL0_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_REF_USE_PAD_SHIFT)) & USB3_GLUE_PHY_CTRL0_REF_USE_PAD_MASK) #define USB3_GLUE_PHY_CTRL0_REF_CLKDIV2_MASK (0x2U) #define USB3_GLUE_PHY_CTRL0_REF_CLKDIV2_SHIFT (1U) /*! REF_CLKDIV2 - Input Reference Clock Divider Control */ #define USB3_GLUE_PHY_CTRL0_REF_CLKDIV2(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_REF_CLKDIV2_SHIFT)) & USB3_GLUE_PHY_CTRL0_REF_CLKDIV2_MASK) #define USB3_GLUE_PHY_CTRL0_REF_SSP_EN_MASK (0x4U) #define USB3_GLUE_PHY_CTRL0_REF_SSP_EN_SHIFT (2U) /*! REF_SSP_EN - Reference Clock Enable for SS Prescaler */ #define USB3_GLUE_PHY_CTRL0_REF_SSP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_REF_SSP_EN_SHIFT)) & USB3_GLUE_PHY_CTRL0_REF_SSP_EN_MASK) #define USB3_GLUE_PHY_CTRL0_REFCLKSEL_MASK (0x18U) #define USB3_GLUE_PHY_CTRL0_REFCLKSEL_SHIFT (3U) /*! REFCLKSEL - Reference Clock Select for PLL Block */ #define USB3_GLUE_PHY_CTRL0_REFCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_REFCLKSEL_SHIFT)) & USB3_GLUE_PHY_CTRL0_REFCLKSEL_MASK) #define USB3_GLUE_PHY_CTRL0_FSEL_MASK (0x7E0U) #define USB3_GLUE_PHY_CTRL0_FSEL_SHIFT (5U) /*! FSEL - FSEL * 0b100111..100 MHz ref clock * 0b101010..24 MHz ref clock */ #define USB3_GLUE_PHY_CTRL0_FSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_FSEL_SHIFT)) & USB3_GLUE_PHY_CTRL0_FSEL_MASK) #define USB3_GLUE_PHY_CTRL0_SSC_EN_MASK (0x800U) #define USB3_GLUE_PHY_CTRL0_SSC_EN_SHIFT (11U) /*! SSC_EN - Spread Spectrum Enable */ #define USB3_GLUE_PHY_CTRL0_SSC_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_SSC_EN_SHIFT)) & USB3_GLUE_PHY_CTRL0_SSC_EN_MASK) #define USB3_GLUE_PHY_CTRL0_SSC_REF_CLK_SEL_MASK (0x1FF000U) #define USB3_GLUE_PHY_CTRL0_SSC_REF_CLK_SEL_SHIFT (12U) /*! SSC_REF_CLK_SEL - Spread Spectrum Reference Clock Shifting */ #define USB3_GLUE_PHY_CTRL0_SSC_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_SSC_REF_CLK_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL0_SSC_REF_CLK_SEL_MASK) #define USB3_GLUE_PHY_CTRL0_SSC_RANGE_MASK (0xE00000U) #define USB3_GLUE_PHY_CTRL0_SSC_RANGE_SHIFT (21U) /*! SSC_RANGE - Spread Spectrum Clock Range * 0b000..4980 * 0b001..4492 * 0b010..4003 */ #define USB3_GLUE_PHY_CTRL0_SSC_RANGE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_SSC_RANGE_SHIFT)) & USB3_GLUE_PHY_CTRL0_SSC_RANGE_MASK) #define USB3_GLUE_PHY_CTRL0_MPLL_REFSSC_CLK_EN_MASK (0x1000000U) #define USB3_GLUE_PHY_CTRL0_MPLL_REFSSC_CLK_EN_SHIFT (24U) /*! MPLL_REFSSC_CLK_EN - Double-Word Clock Enable */ #define USB3_GLUE_PHY_CTRL0_MPLL_REFSSC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_MPLL_REFSSC_CLK_EN_SHIFT)) & USB3_GLUE_PHY_CTRL0_MPLL_REFSSC_CLK_EN_MASK) #define USB3_GLUE_PHY_CTRL0_MPLL_MULTIPLIER_MASK (0xFE000000U) #define USB3_GLUE_PHY_CTRL0_MPLL_MULTIPLIER_SHIFT (25U) /*! MPLL_MULTIPLIER - MPLL Frequency Multiplier Control */ #define USB3_GLUE_PHY_CTRL0_MPLL_MULTIPLIER(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL0_MPLL_MULTIPLIER_SHIFT)) & USB3_GLUE_PHY_CTRL0_MPLL_MULTIPLIER_MASK) /*! @} */ /*! @name PHY_CTRL1 - USBPHY Control 1 */ /*! @{ */ #define USB3_GLUE_PHY_CTRL1_PHY_RESET_MASK (0x1U) #define USB3_GLUE_PHY_CTRL1_PHY_RESET_SHIFT (0U) /*! PHY_RESET - Core and State Machine Reset */ #define USB3_GLUE_PHY_CTRL1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_PHY_RESET_SHIFT)) & USB3_GLUE_PHY_CTRL1_PHY_RESET_MASK) #define USB3_GLUE_PHY_CTRL1_COMMONONN_MASK (0x2U) #define USB3_GLUE_PHY_CTRL1_COMMONONN_SHIFT (1U) /*! COMMONONN - Common Block Power-Down Control * 0b1..In Suspend or Sleep mode, the PLL block is powered down * 0b0..In Suspend or Sleep mode, the PLL block remains powered and continues to draw current */ #define USB3_GLUE_PHY_CTRL1_COMMONONN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_COMMONONN_SHIFT)) & USB3_GLUE_PHY_CTRL1_COMMONONN_MASK) #define USB3_GLUE_PHY_CTRL1_RETENABLEN_MASK (0x4U) #define USB3_GLUE_PHY_CTRL1_RETENABLEN_SHIFT (2U) /*! RETENABLEN - Lowered Digital Supply */ #define USB3_GLUE_PHY_CTRL1_RETENABLEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_RETENABLEN_SHIFT)) & USB3_GLUE_PHY_CTRL1_RETENABLEN_MASK) #define USB3_GLUE_PHY_CTRL1_ATERESET_MASK (0x8U) #define USB3_GLUE_PHY_CTRL1_ATERESET_SHIFT (3U) #define USB3_GLUE_PHY_CTRL1_ATERESET(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_ATERESET_SHIFT)) & USB3_GLUE_PHY_CTRL1_ATERESET_MASK) #define USB3_GLUE_PHY_CTRL1_ACJT_LEVEL_MASK (0x1F0U) #define USB3_GLUE_PHY_CTRL1_ACJT_LEVEL_SHIFT (4U) /*! ACJT_LEVEL - 1149.6 Receiver Sensitivity Level Control */ #define USB3_GLUE_PHY_CTRL1_ACJT_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_ACJT_LEVEL_SHIFT)) & USB3_GLUE_PHY_CTRL1_ACJT_LEVEL_MASK) #define USB3_GLUE_PHY_CTRL1_LOOPBACKENB0_MASK (0x200U) #define USB3_GLUE_PHY_CTRL1_LOOPBACKENB0_SHIFT (9U) /*! LOOPBACKENB0 - Loopback Enable */ #define USB3_GLUE_PHY_CTRL1_LOOPBACKENB0(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_LOOPBACKENB0_SHIFT)) & USB3_GLUE_PHY_CTRL1_LOOPBACKENB0_MASK) #define USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_SSP_MASK (0x400U) #define USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_SSP_SHIFT (10U) /*! PHY_TEST_POWERDOWN_SSP - Power Down SS in PHY */ #define USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_SSP(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_SSP_SHIFT)) & USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_SSP_MASK) #define USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_HSP_MASK (0x800U) #define USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_HSP_SHIFT (11U) /*! PHY_TEST_POWERDOWN_HSP - Power Down HS in PHY */ #define USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_HSP_SHIFT)) & USB3_GLUE_PHY_CTRL1_PHY_TEST_POWERDOWN_HSP_MASK) #define USB3_GLUE_PHY_CTRL1_VATESTENB_MASK (0x3000U) #define USB3_GLUE_PHY_CTRL1_VATESTENB_SHIFT (12U) /*! VATESTENB - Analog Test Voltage Enable */ #define USB3_GLUE_PHY_CTRL1_VATESTENB(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_VATESTENB_SHIFT)) & USB3_GLUE_PHY_CTRL1_VATESTENB_MASK) #define USB3_GLUE_PHY_CTRL1_TEST_BURNIN_MASK (0x4000U) #define USB3_GLUE_PHY_CTRL1_TEST_BURNIN_SHIFT (14U) /*! TEST_BURNIN - Test Burning */ #define USB3_GLUE_PHY_CTRL1_TEST_BURNIN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_TEST_BURNIN_SHIFT)) & USB3_GLUE_PHY_CTRL1_TEST_BURNIN_MASK) #define USB3_GLUE_PHY_CTRL1_RTUNE_REQ_MASK (0x8000U) #define USB3_GLUE_PHY_CTRL1_RTUNE_REQ_SHIFT (15U) /*! RTUNE_REQ - Resistor Tune Request */ #define USB3_GLUE_PHY_CTRL1_RTUNE_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_RTUNE_REQ_SHIFT)) & USB3_GLUE_PHY_CTRL1_RTUNE_REQ_MASK) #define USB3_GLUE_PHY_CTRL1_AUTORSMENB0_MASK (0x10000U) #define USB3_GLUE_PHY_CTRL1_AUTORSMENB0_SHIFT (16U) /*! AUTORSMENB0 - AutoResume Mode Enable */ #define USB3_GLUE_PHY_CTRL1_AUTORSMENB0(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_AUTORSMENB0_SHIFT)) & USB3_GLUE_PHY_CTRL1_AUTORSMENB0_MASK) #define USB3_GLUE_PHY_CTRL1_DCDENB_MASK (0x20000U) #define USB3_GLUE_PHY_CTRL1_DCDENB_SHIFT (17U) /*! DCDENB - Data Contact Detection Enable * 0b1..IDP_SRC current is sourced onto DP<#>, pull-down resistance on DM<#> is enabled * 0b0..IDP_SRC current is disabled, pull-down resistance on DM<#> is disabled */ #define USB3_GLUE_PHY_CTRL1_DCDENB(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_DCDENB_SHIFT)) & USB3_GLUE_PHY_CTRL1_DCDENB_MASK) #define USB3_GLUE_PHY_CTRL1_CHRGSEL_MASK (0x40000U) #define USB3_GLUE_PHY_CTRL1_CHRGSEL_SHIFT (18U) /*! CHRGSEL - Battery Charging Source Select * 0b1..Data source voltage (VDAT_SRC) is sourced onto DM<#> and sunk from DP<#> * 0b0..Data source voltage (VDAT_SRC) is sourced onto DP<#> and sunk from DM<#> */ #define USB3_GLUE_PHY_CTRL1_CHRGSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_CHRGSEL_SHIFT)) & USB3_GLUE_PHY_CTRL1_CHRGSEL_MASK) #define USB3_GLUE_PHY_CTRL1_VDATSRCENB_MASK (0x80000U) #define USB3_GLUE_PHY_CTRL1_VDATSRCENB_SHIFT (19U) /*! VDATSRCENB - Battery Charging Sourcing Select * 0b1..Data source voltage (VDAT_SRC) is enabled * 0b0..Data source voltage (VDAT_SRC) is disabled */ #define USB3_GLUE_PHY_CTRL1_VDATSRCENB(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_VDATSRCENB_SHIFT)) & USB3_GLUE_PHY_CTRL1_VDATSRCENB_MASK) #define USB3_GLUE_PHY_CTRL1_VDATDETENB_MASK (0x100000U) #define USB3_GLUE_PHY_CTRL1_VDATDETENB_SHIFT (20U) /*! VDATDETENB - Battery Charging Attach/Connect Detection Enable * 0b1..Data detect voltage (CHG_DET) is enabled * 0b0..Data detect voltage (CHG_DET) is disabled */ #define USB3_GLUE_PHY_CTRL1_VDATDETENB(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_VDATDETENB_SHIFT)) & USB3_GLUE_PHY_CTRL1_VDATDETENB_MASK) #define USB3_GLUE_PHY_CTRL1_CHRGSRCPUENB0_MASK (0x600000U) #define USB3_GLUE_PHY_CTRL1_CHRGSRCPUENB0_SHIFT (21U) /*! CHRGSRCPUENB0 - Charger Source Pull-Up Enable * 0b01..Charger source pull up is enabled * 0b00..Charger source pull up is disabled */ #define USB3_GLUE_PHY_CTRL1_CHRGSRCPUENB0(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_CHRGSRCPUENB0_SHIFT)) & USB3_GLUE_PHY_CTRL1_CHRGSRCPUENB0_MASK) #define USB3_GLUE_PHY_CTRL1_VDATREFTUNE0_MASK (0x1800000U) #define USB3_GLUE_PHY_CTRL1_VDATREFTUNE0_SHIFT (23U) /*! VDATREFTUNE0 - Data Detect Voltage Adjustment * 0b11..- 20% * 0b10..- 10% * 0b01..0 (default) * 0b00..+ 10% */ #define USB3_GLUE_PHY_CTRL1_VDATREFTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_VDATREFTUNE0_SHIFT)) & USB3_GLUE_PHY_CTRL1_VDATREFTUNE0_MASK) #define USB3_GLUE_PHY_CTRL1_HSXCVREXTCTL0_MASK (0x2000000U) #define USB3_GLUE_PHY_CTRL1_HSXCVREXTCTL0_SHIFT (25U) /*! HSXCVREXTCTL0 - HS Transceiver Asynchronous Control * 0b1..HS TX/RX path is selected * 0b0..FS TX/RX path is selected */ #define USB3_GLUE_PHY_CTRL1_HSXCVREXTCTL0(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_HSXCVREXTCTL0_SHIFT)) & USB3_GLUE_PHY_CTRL1_HSXCVREXTCTL0_MASK) #define USB3_GLUE_PHY_CTRL1_TYPEC_FLIP_INVERT_MASK (0x4000000U) #define USB3_GLUE_PHY_CTRL1_TYPEC_FLIP_INVERT_SHIFT (26U) /*! TYPEC_FLIP_INVERT - Flip Invert to Type-C PHY */ #define USB3_GLUE_PHY_CTRL1_TYPEC_FLIP_INVERT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_TYPEC_FLIP_INVERT_SHIFT)) & USB3_GLUE_PHY_CTRL1_TYPEC_FLIP_INVERT_MASK) #define USB3_GLUE_PHY_CTRL1_SYS_VBUSVALID_SW_MASK (0x10000000U) #define USB3_GLUE_PHY_CTRL1_SYS_VBUSVALID_SW_SHIFT (28U) /*! SYS_VBUSVALID_SW - System VBUS Valid */ #define USB3_GLUE_PHY_CTRL1_SYS_VBUSVALID_SW(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_SYS_VBUSVALID_SW_SHIFT)) & USB3_GLUE_PHY_CTRL1_SYS_VBUSVALID_SW_MASK) #define USB3_GLUE_PHY_CTRL1_USB_DEV_POR_MASK (0x20000000U) #define USB3_GLUE_PHY_CTRL1_USB_DEV_POR_SHIFT (29U) /*! USB_DEV_POR - PoR as USB Device */ #define USB3_GLUE_PHY_CTRL1_USB_DEV_POR(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_USB_DEV_POR_SHIFT)) & USB3_GLUE_PHY_CTRL1_USB_DEV_POR_MASK) #define USB3_GLUE_PHY_CTRL1_TAC_APB_RESET_SW_MASK (0x40000000U) #define USB3_GLUE_PHY_CTRL1_TAC_APB_RESET_SW_SHIFT (30U) /*! TAC_APB_RESET_SW - TCA Reset SW Control * 0b1..TCA reset is enabled * 0b0..TCA reset is disabled */ #define USB3_GLUE_PHY_CTRL1_TAC_APB_RESET_SW(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL1_TAC_APB_RESET_SW_SHIFT)) & USB3_GLUE_PHY_CTRL1_TAC_APB_RESET_SW_MASK) /*! @} */ /*! @name PHY_CTRL2 - USBPHY Control 2 */ /*! @{ */ #define USB3_GLUE_PHY_CTRL2_BYPASSSEL_MASK (0x1U) #define USB3_GLUE_PHY_CTRL2_BYPASSSEL_SHIFT (0U) /*! BYPASSSEL - Bypass Select */ #define USB3_GLUE_PHY_CTRL2_BYPASSSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_BYPASSSEL_SHIFT)) & USB3_GLUE_PHY_CTRL2_BYPASSSEL_MASK) #define USB3_GLUE_PHY_CTRL2_BYPASSDPEN_MASK (0x2U) #define USB3_GLUE_PHY_CTRL2_BYPASSDPEN_SHIFT (1U) /*! BYPASSDPEN - Bypass DP Enable */ #define USB3_GLUE_PHY_CTRL2_BYPASSDPEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_BYPASSDPEN_SHIFT)) & USB3_GLUE_PHY_CTRL2_BYPASSDPEN_MASK) #define USB3_GLUE_PHY_CTRL2_BYPASSDPDATA_MASK (0x4U) #define USB3_GLUE_PHY_CTRL2_BYPASSDPDATA_SHIFT (2U) /*! BYPASSDPDATA - Bypass DP Data */ #define USB3_GLUE_PHY_CTRL2_BYPASSDPDATA(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_BYPASSDPDATA_SHIFT)) & USB3_GLUE_PHY_CTRL2_BYPASSDPDATA_MASK) #define USB3_GLUE_PHY_CTRL2_BYPASSDMEN_MASK (0x8U) #define USB3_GLUE_PHY_CTRL2_BYPASSDMEN_SHIFT (3U) /*! BYPASSDMEN - Bypass DM Enable */ #define USB3_GLUE_PHY_CTRL2_BYPASSDMEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_BYPASSDMEN_SHIFT)) & USB3_GLUE_PHY_CTRL2_BYPASSDMEN_MASK) #define USB3_GLUE_PHY_CTRL2_BYPASSDMDATA_MASK (0x10U) #define USB3_GLUE_PHY_CTRL2_BYPASSDMDATA_SHIFT (4U) /*! BYPASSDMDATA - Bypass DM Data */ #define USB3_GLUE_PHY_CTRL2_BYPASSDMDATA(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_BYPASSDMDATA_SHIFT)) & USB3_GLUE_PHY_CTRL2_BYPASSDMDATA_MASK) #define USB3_GLUE_PHY_CTRL2_FSDATAEXT_MASK (0x20U) #define USB3_GLUE_PHY_CTRL2_FSDATAEXT_SHIFT (5U) /*! FSDATAEXT - USB 1.1 SE0 Generation */ #define USB3_GLUE_PHY_CTRL2_FSDATAEXT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_FSDATAEXT_SHIFT)) & USB3_GLUE_PHY_CTRL2_FSDATAEXT_MASK) #define USB3_GLUE_PHY_CTRL2_FSSE0EXT_MASK (0x40U) #define USB3_GLUE_PHY_CTRL2_FSSE0EXT_SHIFT (6U) /*! FSSE0EXT - USB 1.1 Transmit Data * 0b1..D+ and D- lines are driven to a Differential 1 * 0b0..D+ and D- lines are driven to a Differential 0 */ #define USB3_GLUE_PHY_CTRL2_FSSE0EXT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_FSSE0EXT_SHIFT)) & USB3_GLUE_PHY_CTRL2_FSSE0EXT_MASK) #define USB3_GLUE_PHY_CTRL2_FSXCVROWNER_MASK (0x80U) #define USB3_GLUE_PHY_CTRL2_FSXCVROWNER_SHIFT (7U) /*! FSXCVROWNER - UTMI+/Serial Interface Select * 0b1..TXENABLEN<#>, FSDATAEXT<#>, and FSSE0EXT<#> inputs drive USB 2.0 data output onto the D+ and D- lines. * Data that the USB 3.0 femtoPHY receives from the D+ and D- lines appears on the FSVMINUS<#> and FSVPLUS<#> * outputs * 0b0..Data on the D+ and D- lines is transmitted and received through the UTMI+ */ #define USB3_GLUE_PHY_CTRL2_FSXCVROWNER(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_FSXCVROWNER_SHIFT)) & USB3_GLUE_PHY_CTRL2_FSXCVROWNER_MASK) #define USB3_GLUE_PHY_CTRL2_TXENABLEN_MASK (0x100U) #define USB3_GLUE_PHY_CTRL2_TXENABLEN_SHIFT (8U) /*! TXENABLEN - USB 1.1 Data Enable * 0b1..FSDATAEXT<#> and FSSE0EXT<#> are disabled * 0b0..FSDATAEXT<#> and FSSE0EXT<#> are enabled */ #define USB3_GLUE_PHY_CTRL2_TXENABLEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_TXENABLEN_SHIFT)) & USB3_GLUE_PHY_CTRL2_TXENABLEN_MASK) #define USB3_GLUE_PHY_CTRL2_OTGDISABLE_MASK (0x200U) #define USB3_GLUE_PHY_CTRL2_OTGDISABLE_SHIFT (9U) /*! OTGDISABLE - OTG Disable */ #define USB3_GLUE_PHY_CTRL2_OTGDISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_OTGDISABLE_SHIFT)) & USB3_GLUE_PHY_CTRL2_OTGDISABLE_MASK) #define USB3_GLUE_PHY_CTRL2_VBUSVLDEXT_MASK (0x400U) #define USB3_GLUE_PHY_CTRL2_VBUSVLDEXT_SHIFT (10U) /*! VBUSVLDEXT - External VBUS Valid Indicator * 0b1..VBUS<#> signal is valid, and the pull-up resistor on D+ is enabled * 0b0..VBUS<#> signal is not valid, and the pull-up resistor on D+ is disabled */ #define USB3_GLUE_PHY_CTRL2_VBUSVLDEXT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_VBUSVLDEXT_SHIFT)) & USB3_GLUE_PHY_CTRL2_VBUSVLDEXT_MASK) #define USB3_GLUE_PHY_CTRL2_VBUSVLDEXTSEL_MASK (0x800U) #define USB3_GLUE_PHY_CTRL2_VBUSVLDEXTSEL_SHIFT (11U) /*! VBUSVLDEXTSEL - External VBUS Valid Indicator Select * 0b1..VBUSVLDEXT<#> input is used * 0b0..Internal Session Valid comparator is used */ #define USB3_GLUE_PHY_CTRL2_VBUSVLDEXTSEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_VBUSVLDEXTSEL_SHIFT)) & USB3_GLUE_PHY_CTRL2_VBUSVLDEXTSEL_MASK) #define USB3_GLUE_PHY_CTRL2_TXBITSTUFFENH_MASK (0x1000U) #define USB3_GLUE_PHY_CTRL2_TXBITSTUFFENH_SHIFT (12U) /*! TXBITSTUFFENH - TX Bit Stuff Enable High */ #define USB3_GLUE_PHY_CTRL2_TXBITSTUFFENH(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_TXBITSTUFFENH_SHIFT)) & USB3_GLUE_PHY_CTRL2_TXBITSTUFFENH_MASK) #define USB3_GLUE_PHY_CTRL2_TXBITSTUFFEN_MASK (0x2000U) #define USB3_GLUE_PHY_CTRL2_TXBITSTUFFEN_SHIFT (13U) /*! TXBITSTUFFEN - TX Bit Stuff Enable */ #define USB3_GLUE_PHY_CTRL2_TXBITSTUFFEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_TXBITSTUFFEN_SHIFT)) & USB3_GLUE_PHY_CTRL2_TXBITSTUFFEN_MASK) #define USB3_GLUE_PHY_CTRL2_UTMOTG_IDPULLUP_MASK (0x4000U) #define USB3_GLUE_PHY_CTRL2_UTMOTG_IDPULLUP_SHIFT (14U) /*! UTMOTG_IDPULLUP - Analog ID Input Sample Enable * 0b1..IDN pin sampling is enabled, and the IDDIG0 output is valid * 0b0..IDN pin sampling is disabled, and the IDDIG0 output is not valid */ #define USB3_GLUE_PHY_CTRL2_UTMOTG_IDPULLUP(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_UTMOTG_IDPULLUP_SHIFT)) & USB3_GLUE_PHY_CTRL2_UTMOTG_IDPULLUP_MASK) #define USB3_GLUE_PHY_CTRL2_REF_REPEAT_CLK_EN_MASK (0x8000U) #define USB3_GLUE_PHY_CTRL2_REF_REPEAT_CLK_EN_SHIFT (15U) /*! REF_REPEAT_CLK_EN - Clock Repeater Buffer Enable */ #define USB3_GLUE_PHY_CTRL2_REF_REPEAT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_REF_REPEAT_CLK_EN_SHIFT)) & USB3_GLUE_PHY_CTRL2_REF_REPEAT_CLK_EN_MASK) #define USB3_GLUE_PHY_CTRL2_RX0LOSLFPSEN_MASK (0x10000U) #define USB3_GLUE_PHY_CTRL2_RX0LOSLFPSEN_SHIFT (16U) /*! RX0LOSLFPSEN - RX0 LOS LFPS Filter Enable * 0b1..Enables RX LOS LFPS filter * 0b0..Disables RX LOS LFPS filter */ #define USB3_GLUE_PHY_CTRL2_RX0LOSLFPSEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_RX0LOSLFPSEN_SHIFT)) & USB3_GLUE_PHY_CTRL2_RX0LOSLFPSEN_MASK) #define USB3_GLUE_PHY_CTRL2_REF_USE_XO_MASK (0x20000U) #define USB3_GLUE_PHY_CTRL2_REF_USE_XO_SHIFT (17U) /*! REF_USE_XO - Use External Crystal Oscillator */ #define USB3_GLUE_PHY_CTRL2_REF_USE_XO(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_REF_USE_XO_SHIFT)) & USB3_GLUE_PHY_CTRL2_REF_USE_XO_MASK) #define USB3_GLUE_PHY_CTRL2_REF_XO_EN_MASK (0x40000U) #define USB3_GLUE_PHY_CTRL2_REF_XO_EN_SHIFT (18U) /*! REF_XO_EN - Crystal Oscillator Always On Enable */ #define USB3_GLUE_PHY_CTRL2_REF_XO_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_REF_XO_EN_SHIFT)) & USB3_GLUE_PHY_CTRL2_REF_XO_EN_MASK) #define USB3_GLUE_PHY_CTRL2_DRVVBUS_GF_EN_MASK (0x80000U) #define USB3_GLUE_PHY_CTRL2_DRVVBUS_GF_EN_SHIFT (19U) /*! DRVVBUS_GF_EN - DRV VBUS Enable * 0b1..Enables Vbus * 0b0..Disables Vbus */ #define USB3_GLUE_PHY_CTRL2_DRVVBUS_GF_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_DRVVBUS_GF_EN_SHIFT)) & USB3_GLUE_PHY_CTRL2_DRVVBUS_GF_EN_MASK) #define USB3_GLUE_PHY_CTRL2_RX1LOSLFPSEN_MASK (0x100000U) #define USB3_GLUE_PHY_CTRL2_RX1LOSLFPSEN_SHIFT (20U) /*! RX1LOSLFPSEN - RX1 LOS LFPS Filter Enable * 0b1..Enables RX LOS LFPS filter * 0b0..Disables RX LOS LFPS filter */ #define USB3_GLUE_PHY_CTRL2_RX1LOSLFPSEN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_RX1LOSLFPSEN_SHIFT)) & USB3_GLUE_PHY_CTRL2_RX1LOSLFPSEN_MASK) #define USB3_GLUE_PHY_CTRL2_sys_vbusvalid_sel_MASK (0x600000U) #define USB3_GLUE_PHY_CTRL2_sys_vbusvalid_sel_SHIFT (21U) /*! sys_vbusvalid_sel - PHY sys_vbusvalid input mux selection * 0b01..PHY VBUSVALID0 output * 0b00..PHY pipe0_power_present * 0b10..PHY OTGSESSLVD0 output (for device role) * 0b11..PHY_CTRL1[28] - sys_vbusvalid_sw (for flexibility) */ #define USB3_GLUE_PHY_CTRL2_sys_vbusvalid_sel(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL2_sys_vbusvalid_sel_SHIFT)) & USB3_GLUE_PHY_CTRL2_sys_vbusvalid_sel_MASK) /*! @} */ /*! @name PHY_CTRL3 - USBPHY Control 3 */ /*! @{ */ #define USB3_GLUE_PHY_CTRL3_COMPDISTUNE_MASK (0x7U) #define USB3_GLUE_PHY_CTRL3_COMPDISTUNE_SHIFT (0U) /*! COMPDISTUNE - Disconnect Threshold Adjustment * 0b111..+ 15.54% * 0b110..+ 11.86% * 0b101..+ 7.52% * 0b100..+ 4.08% * 0b011..0 (default) * 0b010..- 3.04% * 0b001..- 6.5% * 0b000..- 9.01% */ #define USB3_GLUE_PHY_CTRL3_COMPDISTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_COMPDISTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_COMPDISTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_OTGTUNE_MASK (0x38U) #define USB3_GLUE_PHY_CTRL3_OTGTUNE_SHIFT (3U) /*! OTGTUNE - VBUS Valid Threshold Adjustment * 0b111..+ 5.8% * 0b110..+ 2.9% * 0b101..0 (default) * 0b100..- 2.9% * 0b011..- 5.8% * 0b010..- 8.7% * 0b001..- 11.6% * 0b000..- 14.5% */ #define USB3_GLUE_PHY_CTRL3_OTGTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_OTGTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_OTGTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_SQRXTUNE_MASK (0x1C0U) #define USB3_GLUE_PHY_CTRL3_SQRXTUNE_SHIFT (6U) /*! SQRXTUNE - Squelch Threshold Adjustment * 0b111..- 22.32% * 0b110..- 16.07% * 0b101..- 10.71% * 0b100..- 5.36% * 0b011..0 (default) * 0b010..+ 5.36% * 0b001..+ 10.71% * 0b000..+ 16.07% */ #define USB3_GLUE_PHY_CTRL3_SQRXTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_SQRXTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_SQRXTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_TXFSLSTUNE_MASK (0x1E00U) #define USB3_GLUE_PHY_CTRL3_TXFSLSTUNE_SHIFT (9U) /*! TXFSLSTUNE - FS/LS Source Impedance Adjustment * 0b1111..- 3.5% * 0b0111..- 1.7% * 0b0011..0 (default) * 0b0001..+ 1.8% * 0b0000..+ 3.5% */ #define USB3_GLUE_PHY_CTRL3_TXFSLSTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TXFSLSTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_TXFSLSTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_TXHSXVTUNE_MASK (0x6000U) #define USB3_GLUE_PHY_CTRL3_TXHSXVTUNE_SHIFT (13U) /*! TXHSXVTUNE - Transmitter High-Speed Crossover Adjustment * 0b11..0 (default) * 0b10..+ 14 mV * 0b01..- 16 mV * 0b00..Reserved */ #define USB3_GLUE_PHY_CTRL3_TXHSXVTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TXHSXVTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_TXHSXVTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_TXPREEMPAMPTUNE_MASK (0x18000U) #define USB3_GLUE_PHY_CTRL3_TXPREEMPAMPTUNE_SHIFT (15U) /*! TXPREEMPAMPTUNE - HS Transmitter Pre-Emphasis Current Control * 0b11..3x pre-emphasis current * 0b10..2x pre-emphasis current * 0b01..1x pre-emphasis current * 0b00..Disabled (default) */ #define USB3_GLUE_PHY_CTRL3_TXPREEMPAMPTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TXPREEMPAMPTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_TXPREEMPAMPTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_TXPREEMPPULSETUNE_MASK (0x20000U) #define USB3_GLUE_PHY_CTRL3_TXPREEMPPULSETUNE_SHIFT (17U) /*! TXPREEMPPULSETUNE - HS Transmitter Pre-Emphasis Duration Control * 0b1..Short * 0b0..Long (default) */ #define USB3_GLUE_PHY_CTRL3_TXPREEMPPULSETUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TXPREEMPPULSETUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_TXPREEMPPULSETUNE_MASK) #define USB3_GLUE_PHY_CTRL3_TXRESTUNE_MASK (0xC0000U) #define USB3_GLUE_PHY_CTRL3_TXRESTUNE_SHIFT (18U) /*! TXRESTUNE - USB Source Impedance Adjustment * 0b11..- 4.5 Ohms * 0b10..- 3 Ohms * 0b01..0 (default) * 0b00..+ 2 Ohms */ #define USB3_GLUE_PHY_CTRL3_TXRESTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TXRESTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_TXRESTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_TXRISETUNE_MASK (0x300000U) #define USB3_GLUE_PHY_CTRL3_TXRISETUNE_SHIFT (20U) /*! TXRISETUNE - HS Transmitter Rise/Fall Time Adjustment * 0b11..- 3% * 0b10..- 1% * 0b01..0 (default) * 0b00..+ 3% */ #define USB3_GLUE_PHY_CTRL3_TXRISETUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TXRISETUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_TXRISETUNE_MASK) #define USB3_GLUE_PHY_CTRL3_TXVREFTUNE_MASK (0x3C00000U) #define USB3_GLUE_PHY_CTRL3_TXVREFTUNE_SHIFT (22U) /*! TXVREFTUNE - HS DC Voltage Level Adjustment */ #define USB3_GLUE_PHY_CTRL3_TXVREFTUNE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TXVREFTUNE_SHIFT)) & USB3_GLUE_PHY_CTRL3_TXVREFTUNE_MASK) #define USB3_GLUE_PHY_CTRL3_LOS_BIAS_MASK (0x1C000000U) #define USB3_GLUE_PHY_CTRL3_LOS_BIAS_SHIFT (26U) /*! LOS_BIAS - Loss-of-Signal Detector Threshold Level Control * 0b111..135 mV * 0b110..120 mV * 0b101..105 mV * 0b100..90 mV * 0b011..75 mV * 0b010..60 mV (default) * 0b001..45 mV * 0b000..Invalid */ #define USB3_GLUE_PHY_CTRL3_LOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_LOS_BIAS_SHIFT)) & USB3_GLUE_PHY_CTRL3_LOS_BIAS_MASK) #define USB3_GLUE_PHY_CTRL3_TX_VBOOST_lvl_MASK (0xE0000000U) #define USB3_GLUE_PHY_CTRL3_TX_VBOOST_lvl_SHIFT (29U) /*! TX_VBOOST_lvl - TX Voltage Boost Level * 0b011..Corresponds to a launch amplitude of 1.12 V * 0b010..Corresponds to a launch amplitude of 1.04 V * 0b000..Corresponds to a launch amplitude of 0.88 V */ #define USB3_GLUE_PHY_CTRL3_TX_VBOOST_lvl(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL3_TX_VBOOST_lvl_SHIFT)) & USB3_GLUE_PHY_CTRL3_TX_VBOOST_lvl_MASK) /*! @} */ /*! @name PHY_CTRL4 - USBPHY Control 4 */ /*! @{ */ #define USB3_GLUE_PHY_CTRL4_LOS_LEVEL_MASK (0x1FU) #define USB3_GLUE_PHY_CTRL4_LOS_LEVEL_SHIFT (0U) /*! LOS_LEVEL - Loss-of-Signal Detector Sensitivity Level Control */ #define USB3_GLUE_PHY_CTRL4_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL4_LOS_LEVEL_SHIFT)) & USB3_GLUE_PHY_CTRL4_LOS_LEVEL_MASK) #define USB3_GLUE_PHY_CTRL4_PCS_RX_LOS_MASK_VAL_MASK (0x7FE0U) #define USB3_GLUE_PHY_CTRL4_PCS_RX_LOS_MASK_VAL_SHIFT (5U) /*! PCS_RX_LOS_MASK_VAL - Configurable Loss-of-Signal Mask Width */ #define USB3_GLUE_PHY_CTRL4_PCS_RX_LOS_MASK_VAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL4_PCS_RX_LOS_MASK_VAL_SHIFT)) & USB3_GLUE_PHY_CTRL4_PCS_RX_LOS_MASK_VAL_MASK) #define USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK (0x1F8000U) #define USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT (15U) /*! PCS_TX_DEEMPH_3P5DB - TX De-Emphasis at 3.5 dB */ #define USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_3P5DB(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT)) & USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK) #define USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_6DB_MASK (0x7E00000U) #define USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_6DB_SHIFT (21U) /*! PCS_TX_DEEMPH_6DB - TX De-Emphasis at 6 dB */ #define USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_6DB(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_6DB_SHIFT)) & USB3_GLUE_PHY_CTRL4_PCS_TX_DEEMPH_6DB_MASK) #define USB3_GLUE_PHY_CTRL4_LANE0_TX_TERM_OFFSET_MASK (0xF8000000U) #define USB3_GLUE_PHY_CTRL4_LANE0_TX_TERM_OFFSET_SHIFT (27U) /*! LANE0_TX_TERM_OFFSET - Transmitter Termination Offset */ #define USB3_GLUE_PHY_CTRL4_LANE0_TX_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL4_LANE0_TX_TERM_OFFSET_SHIFT)) & USB3_GLUE_PHY_CTRL4_LANE0_TX_TERM_OFFSET_MASK) /*! @} */ /*! @name PHY_CTRL5 - USBPHY Control 5 */ /*! @{ */ #define USB3_GLUE_PHY_CTRL5_PCS_TX_SWING_FULL_MASK (0x7FU) #define USB3_GLUE_PHY_CTRL5_PCS_TX_SWING_FULL_SHIFT (0U) /*! PCS_TX_SWING_FULL - TX Amplitude (Full Swing Mode) */ #define USB3_GLUE_PHY_CTRL5_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_PCS_TX_SWING_FULL_SHIFT)) & USB3_GLUE_PHY_CTRL5_PCS_TX_SWING_FULL_MASK) #define USB3_GLUE_PHY_CTRL5_LANE1_TX_TERM_OFFSET_MASK (0xF80U) #define USB3_GLUE_PHY_CTRL5_LANE1_TX_TERM_OFFSET_SHIFT (7U) /*! LANE1_TX_TERM_OFFSET - Transmitter Termination Offset for Lane1 */ #define USB3_GLUE_PHY_CTRL5_LANE1_TX_TERM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_LANE1_TX_TERM_OFFSET_SHIFT)) & USB3_GLUE_PHY_CTRL5_LANE1_TX_TERM_OFFSET_MASK) #define USB3_GLUE_PHY_CTRL5_TERMSEL_OVERRIDE_MASK (0x1000U) #define USB3_GLUE_PHY_CTRL5_TERMSEL_OVERRIDE_SHIFT (12U) /*! TERMSEL_OVERRIDE - Utmi Term Select Value Override * 0b1..Override value is 1 * 0b0..Override value is 0 */ #define USB3_GLUE_PHY_CTRL5_TERMSEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_TERMSEL_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_TERMSEL_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_PHY_TERMSEL_OVERRIDE_SEL_MASK (0x2000U) #define USB3_GLUE_PHY_CTRL5_PHY_TERMSEL_OVERRIDE_SEL_SHIFT (13U) /*! PHY_TERMSEL_OVERRIDE_SEL - Utmi Term Select Value Override Selection * 0b1..Select utmi term select value from register * 0b0..Select utmi term select value from core */ #define USB3_GLUE_PHY_CTRL5_PHY_TERMSEL_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_PHY_TERMSEL_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_PHY_TERMSEL_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_MASK (0xC000U) #define USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_SHIFT (14U) /*! OPMODE_OVERRIDE - Utmi Opmode Value Override * 0b01..Enables Utmi opmode * 0b00..Disables Utmi opmode */ #define USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_SEL_MASK (0x10000U) #define USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_SEL_SHIFT (16U) /*! OPMODE_OVERRIDE_SEL - Utmi Opmode Value Override Selection * 0b1..Select utmi opmode override value from register * 0b0..Select utmi opmode override value from core */ #define USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_OPMODE_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_MASK (0x60000U) #define USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_SHIFT (17U) /*! XCVRSEL_OVERRIDE - Utmi Xcvr Value Override * 0b01..Enables Utmi XCVR * 0b00..Disables Utmi XCVR */ #define USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_SEL_MASK (0x80000U) #define USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_SEL_SHIFT (19U) /*! XCVRSEL_OVERRIDE_SEL - Utmi Xcvr Value Override Selection * 0b1..Select xcvrsel override value from register * 0b0..Select xcvrsel override value from core */ #define USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_XCVRSEL_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_MASK (0x100000U) #define USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_SHIFT (20U) /*! DPPULLDOWN_OVERRIDE - Utmi OTG Dp_pulldown Value Override * 0b1..Enables OTG dp_pulldown * 0b0..Disables OTG dp_pulldown */ #define USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_SEL_MASK (0x200000U) #define USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_SEL_SHIFT (21U) /*! DPPULLDOWN_OVERRIDE_SEL - Utmi OTG Dp_pulldown Value Override Selection * 0b1..Select otg dp_pulldown override value from register * 0b0..Select otg dp_pulldown override value from core */ #define USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_DPPULLDOWN_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_MASK (0x400000U) #define USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_SHIFT (22U) /*! DMPULLDOWN_OVERRIDE - Utmi OTG Dm_pulldown Value Override * 0b1..Enables OTG dm_pulldown * 0b0..Disables OTG dm_pulldown */ #define USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_SEL_MASK (0x800000U) #define USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_SEL_SHIFT (23U) /*! DMPULLDOWN_OVERRIDE_SEL - Utmi OTG Dm_pulldown Value Override Selection * 0b1..Select otg dm_pulldown override value from register * 0b0..Select otg dm_pulldown override value from core */ #define USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_DMPULLDOWN_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_MASK (0x1000000U) #define USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_SHIFT (24U) /*! SLEEP_N_OVERRIDE - Utmi Sleep_n Value Override * 0b1..OTG core is not in sleep mode * 0b0..OTG core is in sleep mode */ #define USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_SEL_MASK (0x2000000U) #define USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_SEL_SHIFT (25U) /*! SLEEP_N_OVERRIDE_SEL - Utmi Sleep_n Value Override Selection * 0b1..Select sleep_n value override from register * 0b0..Select sleep_n value from core */ #define USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_SLEEP_N_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_MASK (0x4000000U) #define USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_SHIFT (26U) /*! SUSPEND_N_OVERRIDE - Utmi Suspend_n Value Override * 0b1..Put UTMI PHY in suspend mode * 0b0..Do not put UTMI PHY in suspend mode */ #define USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_SEL_MASK (0x8000000U) #define USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_SEL_SHIFT (27U) /*! SUSPEND_N_OVERRIDE_SEL - Utmi Suspend_n Value Override Selection * 0b1..Select suspend_n value override from register * 0b0..Select suspend_n value from core */ #define USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_SUSPEND_N_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_MASK (0x10000000U) #define USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_SHIFT (28U) /*! DRVVBUS_OVERRIDE - Utmi Drv Vbus Override Value * 0b1..Reset drive vbus * 0b0..Do not reset drive vbus */ #define USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_SEL_MASK (0x20000000U) #define USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_SEL_SHIFT (29U) /*! DRVVBUS_OVERRIDE_SEL - Utmi Drv Vbus Value Override Selection * 0b1..Select utmi drv vbus value override from register * 0b0..Select utmi drv vbus value from core */ #define USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_DRVVBUS_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_MASK (0x40000000U) #define USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_SHIFT (30U) /*! USB2PHY_RESET_OVERRIDE - USB2PHY Reset Override * 0b1..Reset PHY * 0b0..Do not reset PHY */ #define USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_SEL_MASK (0x80000000U) #define USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_SEL_SHIFT (31U) /*! USB2PHY_RESET_OVERRIDE_SEL - USB2PHY Reset Override Selection * 0b1..Select usb2phy reset value override from register * 0b0..Select usb2phy reset value from core */ #define USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL5_USB2PHY_RESET_OVERRIDE_SEL_MASK) /*! @} */ /*! @name PHY_CTRL6 - USBPHY Control 6 */ /*! @{ */ #define USB3_GLUE_PHY_CTRL6_ALT_CLK_SEL_MASK (0x1U) #define USB3_GLUE_PHY_CTRL6_ALT_CLK_SEL_SHIFT (0U) /*! ALT_CLK_SEL - Alternate Clock Source Select * 0b1..Uses alternate clocks * 0b0..Uses internal MPLL clocks */ #define USB3_GLUE_PHY_CTRL6_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_ALT_CLK_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL6_ALT_CLK_SEL_MASK) #define USB3_GLUE_PHY_CTRL6_ALT_CLK_EN_MASK (0x2U) #define USB3_GLUE_PHY_CTRL6_ALT_CLK_EN_SHIFT (1U) /*! ALT_CLK_EN - Alternate Clock Enable */ #define USB3_GLUE_PHY_CTRL6_ALT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_ALT_CLK_EN_SHIFT)) & USB3_GLUE_PHY_CTRL6_ALT_CLK_EN_MASK) #define USB3_GLUE_PHY_CTRL6_LANE0_TX2RX_LOOPBK_MASK (0x4U) #define USB3_GLUE_PHY_CTRL6_LANE0_TX2RX_LOOPBK_SHIFT (2U) /*! LANE0_TX2RX_LOOPBK - Loopback */ #define USB3_GLUE_PHY_CTRL6_LANE0_TX2RX_LOOPBK(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_LANE0_TX2RX_LOOPBK_SHIFT)) & USB3_GLUE_PHY_CTRL6_LANE0_TX2RX_LOOPBK_MASK) #define USB3_GLUE_PHY_CTRL6_LANE0_EXT_PCLK_REQ_MASK (0x8U) #define USB3_GLUE_PHY_CTRL6_LANE0_EXT_PCLK_REQ_SHIFT (3U) /*! LANE0_EXT_PCLK_REQ - External PIPE Clock Enable Request */ #define USB3_GLUE_PHY_CTRL6_LANE0_EXT_PCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_LANE0_EXT_PCLK_REQ_SHIFT)) & USB3_GLUE_PHY_CTRL6_LANE0_EXT_PCLK_REQ_MASK) #define USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_MASK (0x80000U) #define USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_SHIFT (19U) /*! PIPE3_RESET_N_OVERRIDE - Pipe3_reset_n Value Override * 0b1..Do not reset pipe3 PHY * 0b0..Resets pipe3 PHY */ #define USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_SEL_MASK (0x100000U) #define USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_SEL_SHIFT (20U) /*! PIPE3_RESET_N_OVERRIDE_SEL - Pipe3_reset_n Value Override Selection * 0b1..Select pipe3_reset_n value from register * 0b0..Select pipe3_reset_n value from core */ #define USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL6_PIPE3_RESET_N_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_MASK (0x200000U) #define USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_SHIFT (21U) /*! TxDetectRxLoopbk_OVERRIDE - Pipe3_TxDetectRxLoopbk Value Override * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_SEL_MASK (0x400000U) #define USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_SEL_SHIFT (22U) /*! TxDetectRxLoopbk_OVERRIDE_SEL - Pipe3_TxDetectRxLoopbk Value Override Selection * 0b1..Select pipe3_TxDetectRxLoopbk value from register * 0b0..Select pipe3_TxDetectRxLoopbk value from core */ #define USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL6_TxDetectRxLoopbk_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_MASK (0x800000U) #define USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_SHIFT (23U) /*! TxElecIdle_OVERRIDE - Pipe3_TxElecIdle Value Override * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_SEL_MASK (0x1000000U) #define USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_SEL_SHIFT (24U) /*! TxElecIdle_OVERRIDE_SEL - Pipe3_TxElecIdle Value Override Selection * 0b1..Select pipe3_TxElecIdle value from register * 0b0..Select pipe3_TxElecIdle value from core */ #define USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL6_TxElecIdle_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL6_PowerDown_OVERRIDE_MASK (0x6000000U) #define USB3_GLUE_PHY_CTRL6_PowerDown_OVERRIDE_SHIFT (25U) /*! PowerDown_OVERRIDE - Pipe3_PowerDown Value Override * 0b01..Active * 0b00..Inactive */ #define USB3_GLUE_PHY_CTRL6_PowerDown_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_PowerDown_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL6_PowerDown_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL6_POWERDOWN_OVERRIDE_SEL_MASK (0x8000000U) #define USB3_GLUE_PHY_CTRL6_POWERDOWN_OVERRIDE_SEL_SHIFT (27U) /*! POWERDOWN_OVERRIDE_SEL - Pipe3_PowerDown Value Override Selection * 0b1..Select pipe3_PowerDown value from register * 0b0..Select pipe3_PowerDown value from core */ #define USB3_GLUE_PHY_CTRL6_POWERDOWN_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_POWERDOWN_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL6_POWERDOWN_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_MASK (0x10000000U) #define USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_SHIFT (28U) /*! RXTERMINATION_OVERRIDE - Pipe3_RxTermination Value Override * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_SEL_MASK (0x20000000U) #define USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_SEL_SHIFT (29U) /*! RXTERMINATION_OVERRIDE_SEL - Pipe3_RxTermination Value Override Selection * 0b1..Select pipe3_RxTermination value from register * 0b0..Select pipe3_RxTermination value from core */ #define USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL6_RXTERMINATION_OVERRIDE_SEL_MASK) #define USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_MASK (0x40000000U) #define USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_SHIFT (30U) /*! TxOnesZeros_OVERRIDE - Pipe3_TxOnesZeros Value Override * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_SHIFT)) & USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_MASK) #define USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_SEL_MASK (0x80000000U) #define USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_SEL_SHIFT (31U) /*! TxOnesZeros_OVERRIDE_SEL - Pipe3_TxOnesZeros Value Override Selection * 0b1..Select pipe3_TxOnesZeros value from register * 0b0..Select pipe3_TxOnesZeros value from core */ #define USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_SEL_SHIFT)) & USB3_GLUE_PHY_CTRL6_TxOnesZeros_OVERRIDE_SEL_MASK) /*! @} */ /*! @name PHY_CRCTL - USB3_PHY CR Control */ /*! @{ */ #define USB3_GLUE_PHY_CRCTL_CR_DATA_IN_MASK (0xFFFFU) #define USB3_GLUE_PHY_CRCTL_CR_DATA_IN_SHIFT (0U) /*! CR_DATA_IN - PHY Control Register Address and Write Data Input Bus */ #define USB3_GLUE_PHY_CRCTL_CR_DATA_IN(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CRCTL_CR_DATA_IN_SHIFT)) & USB3_GLUE_PHY_CRCTL_CR_DATA_IN_MASK) #define USB3_GLUE_PHY_CRCTL_CR_CAP_ADDR_MASK (0x10000U) #define USB3_GLUE_PHY_CRCTL_CR_CAP_ADDR_SHIFT (16U) /*! CR_CAP_ADDR - PHY Control Register Capture Address * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CRCTL_CR_CAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CRCTL_CR_CAP_ADDR_SHIFT)) & USB3_GLUE_PHY_CRCTL_CR_CAP_ADDR_MASK) #define USB3_GLUE_PHY_CRCTL_CR_CAP_DATA_MASK (0x20000U) #define USB3_GLUE_PHY_CRCTL_CR_CAP_DATA_SHIFT (17U) /*! CR_CAP_DATA - PHY Control Register Capture Data * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CRCTL_CR_CAP_DATA(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CRCTL_CR_CAP_DATA_SHIFT)) & USB3_GLUE_PHY_CRCTL_CR_CAP_DATA_MASK) #define USB3_GLUE_PHY_CRCTL_CR_WRITE_MASK (0x40000U) #define USB3_GLUE_PHY_CRCTL_CR_WRITE_SHIFT (18U) /*! CR_WRITE - PHY Control Register Write * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CRCTL_CR_WRITE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CRCTL_CR_WRITE_SHIFT)) & USB3_GLUE_PHY_CRCTL_CR_WRITE_MASK) #define USB3_GLUE_PHY_CRCTL_CR_READ_MASK (0x80000U) #define USB3_GLUE_PHY_CRCTL_CR_READ_SHIFT (19U) /*! CR_READ - PHY Control Register Read * 0b1..Active * 0b0..Inactive */ #define USB3_GLUE_PHY_CRCTL_CR_READ(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CRCTL_CR_READ_SHIFT)) & USB3_GLUE_PHY_CRCTL_CR_READ_MASK) /*! @} */ /*! @name PHY_CRSR - USB3_PHY CR Status */ /*! @{ */ #define USB3_GLUE_PHY_CRSR_CR_DATA_OUT_MASK (0xFFFFU) #define USB3_GLUE_PHY_CRSR_CR_DATA_OUT_SHIFT (0U) /*! CR_DATA_OUT - PHY Control Register Data Output Bus */ #define USB3_GLUE_PHY_CRSR_CR_DATA_OUT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CRSR_CR_DATA_OUT_SHIFT)) & USB3_GLUE_PHY_CRSR_CR_DATA_OUT_MASK) #define USB3_GLUE_PHY_CRSR_CR_ACK_MASK (0x10000U) #define USB3_GLUE_PHY_CRSR_CR_ACK_SHIFT (16U) /*! CR_ACK - PHY Control Register Acknowledgment */ #define USB3_GLUE_PHY_CRSR_CR_ACK(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_CRSR_CR_ACK_SHIFT)) & USB3_GLUE_PHY_CRSR_CR_ACK_MASK) /*! @} */ /*! @name PHY_STATUS0 - USB3_PHY Status 0 */ /*! @{ */ #define USB3_GLUE_PHY_STATUS0_PIPE0_POWER_PRESENT_MASK (0x1U) #define USB3_GLUE_PHY_STATUS0_PIPE0_POWER_PRESENT_SHIFT (0U) /*! PIPE0_POWER_PRESENT - PIPE Power Present */ #define USB3_GLUE_PHY_STATUS0_PIPE0_POWER_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_PIPE0_POWER_PRESENT_SHIFT)) & USB3_GLUE_PHY_STATUS0_PIPE0_POWER_PRESENT_MASK) #define USB3_GLUE_PHY_STATUS0_FSLSRCV_MASK (0x2U) #define USB3_GLUE_PHY_STATUS0_FSLSRCV_SHIFT (1U) /*! FSLSRCV - Differential Data Receive Indicator * 0b1..Voltage on D+ is greater than the voltage on D- * 0b0..Voltage on D+ is less than the voltage on D- */ #define USB3_GLUE_PHY_STATUS0_FSLSRCV(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_FSLSRCV_SHIFT)) & USB3_GLUE_PHY_STATUS0_FSLSRCV_MASK) #define USB3_GLUE_PHY_STATUS0_FSVMINUS_MASK (0x4U) #define USB3_GLUE_PHY_STATUS0_FSVMINUS_SHIFT (2U) /*! FSVMINUS - Single-Ended D- Indicator * 0b1..Voltage on D- is high * 0b0..Voltage on D- is low */ #define USB3_GLUE_PHY_STATUS0_FSVMINUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_FSVMINUS_SHIFT)) & USB3_GLUE_PHY_STATUS0_FSVMINUS_MASK) #define USB3_GLUE_PHY_STATUS0_FSVPLUS_MASK (0x8U) #define USB3_GLUE_PHY_STATUS0_FSVPLUS_SHIFT (3U) /*! FSVPLUS - Single-Ended D+ Indicator * 0b1..Voltage on D+ is high * 0b0..Voltage on D+ is low */ #define USB3_GLUE_PHY_STATUS0_FSVPLUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_FSVPLUS_SHIFT)) & USB3_GLUE_PHY_STATUS0_FSVPLUS_MASK) #define USB3_GLUE_PHY_STATUS0_CHGDET_MASK (0x10U) #define USB3_GLUE_PHY_STATUS0_CHGDET_SHIFT (4U) /*! CHGDET - Battery Charger Detection Output * 0b1..VDP > VDAT_REF (for CHRGSEL<#> = 1'b1) or VDM > VDAT_REF (for CHRGSEL<#> = 1'b0) * 0b0..VDP < VDAT_REF (for CHRGSEL<#> = 1'b1) or VDM < VDAT_REF (for CHRGSEL<#> = 1'b0) */ #define USB3_GLUE_PHY_STATUS0_CHGDET(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_CHGDET_SHIFT)) & USB3_GLUE_PHY_STATUS0_CHGDET_MASK) #define USB3_GLUE_PHY_STATUS0_REF_CLKREQ_N_MASK (0x20U) #define USB3_GLUE_PHY_STATUS0_REF_CLKREQ_N_SHIFT (5U) /*! REF_CLKREQ_N - Reference Clock Removal Acknowledge */ #define USB3_GLUE_PHY_STATUS0_REF_CLKREQ_N(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_REF_CLKREQ_N_SHIFT)) & USB3_GLUE_PHY_STATUS0_REF_CLKREQ_N_MASK) #define USB3_GLUE_PHY_STATUS0_RTUNE_ACK_MASK (0x40U) #define USB3_GLUE_PHY_STATUS0_RTUNE_ACK_SHIFT (6U) /*! RTUNE_ACK - Resistor Tune Acknowledge */ #define USB3_GLUE_PHY_STATUS0_RTUNE_ACK(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_RTUNE_ACK_SHIFT)) & USB3_GLUE_PHY_STATUS0_RTUNE_ACK_MASK) #define USB3_GLUE_PHY_STATUS0_OTGSESSVLD_MASK (0x80U) #define USB3_GLUE_PHY_STATUS0_OTGSESSVLD_SHIFT (7U) /*! OTGSESSVLD - OTG Device Session Valid Indicator * 0b1..The voltage on VBUS is above the OTG Device Session Valid threshold * 0b0..The voltage on VBUS is below the OTG Device Session Valid threshold */ #define USB3_GLUE_PHY_STATUS0_OTGSESSVLD(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_OTGSESSVLD_SHIFT)) & USB3_GLUE_PHY_STATUS0_OTGSESSVLD_MASK) #define USB3_GLUE_PHY_STATUS0_TCAMISCCTRL_MASK (0x3F00U) #define USB3_GLUE_PHY_STATUS0_TCAMISCCTRL_SHIFT (8U) /*! TCAMISCCTRL - Type-C Miscellaneous Control to USB Subsystem from TCA */ #define USB3_GLUE_PHY_STATUS0_TCAMISCCTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_TCAMISCCTRL_SHIFT)) & USB3_GLUE_PHY_STATUS0_TCAMISCCTRL_MASK) #define USB3_GLUE_PHY_STATUS0_LINESTATE_DELAY_MASK (0xC000U) #define USB3_GLUE_PHY_STATUS0_LINESTATE_DELAY_SHIFT (14U) /*! LINESTATE_DELAY - Linestate Delay */ #define USB3_GLUE_PHY_STATUS0_LINESTATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_LINESTATE_DELAY_SHIFT)) & USB3_GLUE_PHY_STATUS0_LINESTATE_DELAY_MASK) #define USB3_GLUE_PHY_STATUS0_LINESTATE_MASK (0x30000U) #define USB3_GLUE_PHY_STATUS0_LINESTATE_SHIFT (16U) /*! LINESTATE - Realtime Linestate */ #define USB3_GLUE_PHY_STATUS0_LINESTATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_LINESTATE_SHIFT)) & USB3_GLUE_PHY_STATUS0_LINESTATE_MASK) #define USB3_GLUE_PHY_STATUS0_VBUSVALID_MASK (0x40000U) #define USB3_GLUE_PHY_STATUS0_VBUSVALID_SHIFT (18U) /*! VBUSVALID - Vbus Valid * 0b0..Vbus is less than 4.4 V * 0b1..Vbus is larger than 4.75 V */ #define USB3_GLUE_PHY_STATUS0_VBUSVALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_VBUSVALID_SHIFT)) & USB3_GLUE_PHY_STATUS0_VBUSVALID_MASK) #define USB3_GLUE_PHY_STATUS0_BVALID_MASK (0x80000U) #define USB3_GLUE_PHY_STATUS0_BVALID_SHIFT (19U) /*! BVALID - Session Valid for Peripheral * 0b0..Vbus is less than 4.4 V * 0b1..Vbus is larger than 4.75 V */ #define USB3_GLUE_PHY_STATUS0_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_BVALID_SHIFT)) & USB3_GLUE_PHY_STATUS0_BVALID_MASK) #define USB3_GLUE_PHY_STATUS0_TCAIDDIG_MASK (0x100000U) #define USB3_GLUE_PHY_STATUS0_TCAIDDIG_SHIFT (20U) /*! TCAIDDIG - Type-C OTG IDDIG Indication to USB Subsystem from TCA */ #define USB3_GLUE_PHY_STATUS0_TCAIDDIG(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_TCAIDDIG_SHIFT)) & USB3_GLUE_PHY_STATUS0_TCAIDDIG_MASK) #define USB3_GLUE_PHY_STATUS0_SSRXDETDIS_MASK (0x200000U) #define USB3_GLUE_PHY_STATUS0_SSRXDETDIS_SHIFT (21U) /*! SSRXDETDIS - SuperSpeed RxDetect Disable/Enable Request */ #define USB3_GLUE_PHY_STATUS0_SSRXDETDIS(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_SSRXDETDIS_SHIFT)) & USB3_GLUE_PHY_STATUS0_SSRXDETDIS_MASK) #define USB3_GLUE_PHY_STATUS0_tca_drv_host_vbus_MASK (0x400000U) #define USB3_GLUE_PHY_STATUS0_tca_drv_host_vbus_SHIFT (22U) /*! tca_drv_host_vbus - Type-C Host Drive VBUS From TCA */ #define USB3_GLUE_PHY_STATUS0_tca_drv_host_vbus(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_tca_drv_host_vbus_SHIFT)) & USB3_GLUE_PHY_STATUS0_tca_drv_host_vbus_MASK) #define USB3_GLUE_PHY_STATUS0_PIPE_CLK_VLD_MASK (0x40000000U) #define USB3_GLUE_PHY_STATUS0_PIPE_CLK_VLD_SHIFT (30U) /*! PIPE_CLK_VLD - Pipe 3 Clock Valid */ #define USB3_GLUE_PHY_STATUS0_PIPE_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_PIPE_CLK_VLD_SHIFT)) & USB3_GLUE_PHY_STATUS0_PIPE_CLK_VLD_MASK) #define USB3_GLUE_PHY_STATUS0_UTMI_CLK_VLD_MASK (0x80000000U) #define USB3_GLUE_PHY_STATUS0_UTMI_CLK_VLD_SHIFT (31U) /*! UTMI_CLK_VLD - UTMI Clock Valid */ #define USB3_GLUE_PHY_STATUS0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USB3_GLUE_PHY_STATUS0_UTMI_CLK_VLD_SHIFT)) & USB3_GLUE_PHY_STATUS0_UTMI_CLK_VLD_MASK) /*! @} */ /*! * @} */ /* end of group USB3_GLUE_Register_Masks */ /* USB3_GLUE - Peripheral instance base addresses */ /** Peripheral HSIO__USB_3_01__GLUE base address */ #define HSIO__USB_3_01__GLUE_BASE (0x4C1F0000u) /** Peripheral HSIO__USB_3_01__GLUE base pointer */ #define HSIO__USB_3_01__GLUE ((USB3_GLUE_Type *)HSIO__USB_3_01__GLUE_BASE) /** Array initializer of USB3_GLUE peripheral base addresses */ #define USB3_GLUE_BASE_ADDRS { HSIO__USB_3_01__GLUE_BASE } /** Array initializer of USB3_GLUE peripheral base pointers */ #define USB3_GLUE_BASE_PTRS { HSIO__USB_3_01__GLUE } /*! * @} */ /* end of group USB3_GLUE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB3_PHY_TCA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_PHY_TCA_Peripheral_Access_Layer USB3_PHY_TCA Peripheral Access Layer * @{ */ /** USB3_PHY_TCA - Register Layout Typedef */ typedef struct { __IO uint32_t TCA_CLK_RST; /**< TCA Block Clock and Reset Control, offset: 0x0 */ __IO uint32_t TCA_INTR_EN; /**< TCA Block Interrupt Enable, offset: 0x4 */ __IO uint32_t TCA_INTR_STS; /**< TCA Block Interrupt Status and Clear, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t TCA_GCFG; /**< TCA Global Configuration, offset: 0x10 */ __IO uint32_t TCA_TCPC; /**< TCA TCPC, offset: 0x14 */ __IO uint32_t TCA_SYSMODE_CFG; /**< TCA Register for TypeC_MUX Direct Control, offset: 0x18 */ uint8_t RESERVED_1[4]; __IO uint32_t TCA_CTRLSYNCMODE_CFG0; /**< Configuration Register 0 for Controller Synced Mode, offset: 0x20 */ __IO uint32_t TCA_CTRLSYNCMODE_CFG1; /**< Configuration Register 1 for Controller Synced Mode, offset: 0x24 */ __IO uint32_t TCA_CTRLSYNCMODE_DBG0; /**< Debug Register 0 for Controller Synced Mode, offset: 0x28 */ __I uint32_t TCA_CTRLSYNCMODE_DBG1; /**< Debug Register 1 for Controller Synced Mode, offset: 0x2C */ __I uint32_t TCA_PSTATE; /**< TCA PSTATE Status, offset: 0x30 */ __I uint32_t TCA_GEN_STATUS; /**< TCA General Status, offset: 0x34 */ uint8_t RESERVED_2[8]; __IO uint32_t TCA_VBUS_CTRL; /**< TCA VBus Assist Control, offset: 0x40 */ __I uint32_t TCA_VBUS_STATUS; /**< TCA VBus Assist Status, offset: 0x44 */ uint8_t RESERVED_3[180]; __I uint32_t TCA_INFO; /**< TCA Information For Version ID, offset: 0xFC */ } USB3_PHY_TCA_Type; /* ---------------------------------------------------------------------------- -- USB3_PHY_TCA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB3_PHY_TCA_Register_Masks USB3_PHY_TCA Register Masks * @{ */ /*! @name TCA_CLK_RST - TCA Block Clock and Reset Control */ /*! @{ */ #define USB3_PHY_TCA_TCA_CLK_RST_SUSPEND_CLK_EN_MASK (0x1U) #define USB3_PHY_TCA_TCA_CLK_RST_SUSPEND_CLK_EN_SHIFT (0U) /*! SUSPEND_CLK_EN - Suspend Clock Enable * 0b0..PHY ref_clk_sel decides the tca_clk. If ref_clk_sel is 1b ref_clk from PHY is the tca_clk, else suspend_clk is the tca_clk * 0b1..suspend_clk is used as the tca_clk */ #define USB3_PHY_TCA_TCA_CLK_RST_SUSPEND_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CLK_RST_SUSPEND_CLK_EN_SHIFT)) & USB3_PHY_TCA_TCA_CLK_RST_SUSPEND_CLK_EN_MASK) #define USB3_PHY_TCA_TCA_CLK_RST_TCA_REF_CLK_EN_MASK (0x2U) #define USB3_PHY_TCA_TCA_CLK_RST_TCA_REF_CLK_EN_SHIFT (1U) /*! TCA_REF_CLK_EN - TCA Reference Clock Enable * 0b0..No request from TCA for ref_clk. ref_clk is enabled based on request from SS protocol layer * 0b1..Request from TCA for ref_clk to be enabled */ #define USB3_PHY_TCA_TCA_CLK_RST_TCA_REF_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CLK_RST_TCA_REF_CLK_EN_SHIFT)) & USB3_PHY_TCA_TCA_CLK_RST_TCA_REF_CLK_EN_MASK) #define USB3_PHY_TCA_TCA_CLK_RST_PHY_RST_SW_MASK (0x100U) #define USB3_PHY_TCA_TCA_CLK_RST_PHY_RST_SW_SHIFT (8U) /*! PHY_RST_SW - phy_reset SW Override * 0b0..No phy_reset override * 0b1..phy_reset is asserted (override on phy_reset coming from Type-C Combo PHY top) to Hard macro and PCS. * Soft tca_phy_reset can be driven by asserting this Bit for the required duration */ #define USB3_PHY_TCA_TCA_CLK_RST_PHY_RST_SW(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CLK_RST_PHY_RST_SW_SHIFT)) & USB3_PHY_TCA_TCA_CLK_RST_PHY_RST_SW_MASK) #define USB3_PHY_TCA_TCA_CLK_RST_XA_RST_SW_MASK (0x200U) #define USB3_PHY_TCA_TCA_CLK_RST_XA_RST_SW_SHIFT (9U) /*! XA_RST_SW - XBar Assist Soft Reset * 0b1..Soft reset is not applied * 0b0..Soft reset is applied */ #define USB3_PHY_TCA_TCA_CLK_RST_XA_RST_SW(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CLK_RST_XA_RST_SW_SHIFT)) & USB3_PHY_TCA_TCA_CLK_RST_XA_RST_SW_MASK) /*! @} */ /*! @name TCA_INTR_EN - TCA Block Interrupt Enable */ /*! @{ */ #define USB3_PHY_TCA_TCA_INTR_EN_XA_ACK_EVT_EN_MASK (0x1U) #define USB3_PHY_TCA_TCA_INTR_EN_XA_ACK_EVT_EN_SHIFT (0U) /*! XA_ACK_EVT_EN - XBar Assist Ack Event Enable * 0b0..Ack event is disabled * 0b1..Ack event is enabled */ #define USB3_PHY_TCA_TCA_INTR_EN_XA_ACK_EVT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_EN_XA_ACK_EVT_EN_SHIFT)) & USB3_PHY_TCA_TCA_INTR_EN_XA_ACK_EVT_EN_MASK) #define USB3_PHY_TCA_TCA_INTR_EN_XA_TIMEOUT_EVT_EN_MASK (0x2U) #define USB3_PHY_TCA_TCA_INTR_EN_XA_TIMEOUT_EVT_EN_SHIFT (1U) /*! XA_TIMEOUT_EVT_EN - XBar Assist Timeout Event Enable * 0b0..Timeout event is disabled * 0b1..Timeout event is enabled */ #define USB3_PHY_TCA_TCA_INTR_EN_XA_TIMEOUT_EVT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_EN_XA_TIMEOUT_EVT_EN_SHIFT)) & USB3_PHY_TCA_TCA_INTR_EN_XA_TIMEOUT_EVT_EN_MASK) #define USB3_PHY_TCA_TCA_INTR_EN_SYS_VBUSVALID_EVT_EN_MASK (0x100U) #define USB3_PHY_TCA_TCA_INTR_EN_SYS_VBUSVALID_EVT_EN_SHIFT (8U) /*! SYS_VBUSVALID_EVT_EN - SYS_VBUSVALID Change Event Enable * 0b0..Change event is disabled * 0b1..Change event is enabled */ #define USB3_PHY_TCA_TCA_INTR_EN_SYS_VBUSVALID_EVT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_EN_SYS_VBUSVALID_EVT_EN_SHIFT)) & USB3_PHY_TCA_TCA_INTR_EN_SYS_VBUSVALID_EVT_EN_MASK) #define USB3_PHY_TCA_TCA_INTR_EN_TCA_VBUSVALID_EVT_EN_MASK (0x400U) #define USB3_PHY_TCA_TCA_INTR_EN_TCA_VBUSVALID_EVT_EN_SHIFT (10U) /*! TCA_VBUSVALID_EVT_EN - TCA_VBUSVALID Change Event Enable * 0b0..Change event is disabled * 0b1..Change event is enabled */ #define USB3_PHY_TCA_TCA_INTR_EN_TCA_VBUSVALID_EVT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_EN_TCA_VBUSVALID_EVT_EN_SHIFT)) & USB3_PHY_TCA_TCA_INTR_EN_TCA_VBUSVALID_EVT_EN_MASK) #define USB3_PHY_TCA_TCA_INTR_EN_TCA_DRV_HOST_VBUS_EVT_EN_MASK (0x1000U) #define USB3_PHY_TCA_TCA_INTR_EN_TCA_DRV_HOST_VBUS_EVT_EN_SHIFT (12U) /*! TCA_DRV_HOST_VBUS_EVT_EN - TCA_DRV_HOST_VBUS Change Event Enable * 0b0..Change event is disabled * 0b1..Change event is enabled */ #define USB3_PHY_TCA_TCA_INTR_EN_TCA_DRV_HOST_VBUS_EVT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_EN_TCA_DRV_HOST_VBUS_EVT_EN_SHIFT)) & USB3_PHY_TCA_TCA_INTR_EN_TCA_DRV_HOST_VBUS_EVT_EN_MASK) /*! @} */ /*! @name TCA_INTR_STS - TCA Block Interrupt Status and Clear */ /*! @{ */ #define USB3_PHY_TCA_TCA_INTR_STS_XA_ACK_EVT_MASK (0x1U) #define USB3_PHY_TCA_TCA_INTR_STS_XA_ACK_EVT_SHIFT (0U) /*! XA_ACK_EVT - XBar Assist Ack Event * 0b0..Ack event has not occurred (or been cleared when 1b is written) * 0b1..Ack event has occurred with tca_int interrupt asserted indicating XBar_Assist TCPC request completion */ #define USB3_PHY_TCA_TCA_INTR_STS_XA_ACK_EVT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_XA_ACK_EVT_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_XA_ACK_EVT_MASK) #define USB3_PHY_TCA_TCA_INTR_STS_XA_TIMEOUT_EVT_MASK (0x2U) #define USB3_PHY_TCA_TCA_INTR_STS_XA_TIMEOUT_EVT_SHIFT (1U) /*! XA_TIMEOUT_EVT - XBar Assist Timeout Event Status * 0b0..Timeout event has not occurred (or been cleared when 1b is written) * 0b1..Timeout event has occurred with tca_int bc_interrupt asserted indicating timeout of the TCPC request */ #define USB3_PHY_TCA_TCA_INTR_STS_XA_TIMEOUT_EVT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_XA_TIMEOUT_EVT_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_XA_TIMEOUT_EVT_MASK) #define USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_EVT_MASK (0x100U) #define USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_EVT_SHIFT (8U) /*! SYS_VBUSVALID_EVT - SYS_VBUSVALID Change Event Status * 0b0..Change event has not occurred (or been cleared when 1b is written) * 0b1..Change event has occurred with tca_int interrupt asserted indicating sys_vbusvalid change */ #define USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_EVT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_EVT_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_EVT_MASK) #define USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_MASK (0x200U) #define USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_SHIFT (9U) /*! SYS_VBUSVALID - SYS_VBUSVALID Status/Value */ #define USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_SYS_VBUSVALID_MASK) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_EVT_MASK (0x400U) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_EVT_SHIFT (10U) /*! TCA_VBUSVALID_EVT - TCA_VBUSVALID Change Event Status * 0b0..Change event has not occurred (or been cleared when 1b is written) * 0b1..Change event has occurred with tca_int interrupt asserted indicating tca_vbusvalid change */ #define USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_EVT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_EVT_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_EVT_MASK) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_MASK (0x800U) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_SHIFT (11U) /*! TCA_VBUSVALID - TCA_VBUSVALID Status/Value */ #define USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_TCA_VBUSVALID_MASK) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_EVT_MASK (0x1000U) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_EVT_SHIFT (12U) /*! TCA_DRV_HOST_VBUS_EVT - TCA_DRV_HOST_VBUS Change Event Status * 0b0..Change event has not occurred (or been cleared when 1b is written) * 0b1..Change event has occurred with tca_int interrupt asserted indicating TCA_DRV_HOST_VBUS change */ #define USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_EVT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_EVT_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_EVT_MASK) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_MASK (0x2000U) #define USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_SHIFT (13U) /*! TCA_DRV_HOST_VBUS - TCA_DRV_HOST_VBUS" Status/Value */ #define USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_SHIFT)) & USB3_PHY_TCA_TCA_INTR_STS_TCA_DRV_HOST_VBUS_MASK) /*! @} */ /*! @name TCA_GCFG - TCA Global Configuration */ /*! @{ */ #define USB3_PHY_TCA_TCA_GCFG_OP_MODE_MASK (0x3U) #define USB3_PHY_TCA_TCA_GCFG_OP_MODE_SHIFT (0U) /*! OP_MODE - Type-C Mux Operational Mode * 0bx0..System Configuration Mode, use TCA_SYSMODE_CFG Register for TypeC_MUX direct control * 0bx1..Controller Synced Mode, use TCA_TCPC Register for TypeC_MUX control */ #define USB3_PHY_TCA_TCA_GCFG_OP_MODE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_GCFG_OP_MODE_SHIFT)) & USB3_PHY_TCA_TCA_GCFG_OP_MODE_MASK) #define USB3_PHY_TCA_TCA_GCFG_ROLE_HSTDEV_MASK (0x10U) #define USB3_PHY_TCA_TCA_GCFG_ROLE_HSTDEV_SHIFT (4U) /*! ROLE_HSTDEV - USB Host/Device Mode * 0b0..Default mode, USB Subsystem is in DRP/Host mode * 0b1..Device mode operation, USB Subsystem is in Device mode */ #define USB3_PHY_TCA_TCA_GCFG_ROLE_HSTDEV(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_GCFG_ROLE_HSTDEV_SHIFT)) & USB3_PHY_TCA_TCA_GCFG_ROLE_HSTDEV_MASK) /*! @} */ /*! @name TCA_TCPC - TCA TCPC */ /*! @{ */ #define USB3_PHY_TCA_TCA_TCPC_TCPC_MUX_CONTROL_MASK (0x3U) #define USB3_PHY_TCA_TCA_TCPC_TCPC_MUX_CONTROL_SHIFT (0U) /*! TCPC_MUX_CONTROL - TCPC Mux Control * 0b00..No connection (default) * 0b01..USB3.0 Connected * 0b10.. * 0b11.. */ #define USB3_PHY_TCA_TCA_TCPC_TCPC_MUX_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_TCPC_TCPC_MUX_CONTROL_SHIFT)) & USB3_PHY_TCA_TCA_TCPC_TCPC_MUX_CONTROL_MASK) #define USB3_PHY_TCA_TCA_TCPC_TCPC_CONNECTOR_ORIENTATION_MASK (0x4U) #define USB3_PHY_TCA_TCA_TCPC_TCPC_CONNECTOR_ORIENTATION_SHIFT (2U) /*! TCPC_CONNECTOR_ORIENTATION - Connector Orientation From TCPM * 0b0..Normal (CC1=A5, CC2=B5, TX1=A2/A3, RX1=B10/B11) default * 0b1..Flipped (CC2=A5, CC1=B5, TX1=B2/B3, RX1=A10/A11) */ #define USB3_PHY_TCA_TCA_TCPC_TCPC_CONNECTOR_ORIENTATION(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_TCPC_TCPC_CONNECTOR_ORIENTATION_SHIFT)) & USB3_PHY_TCA_TCA_TCPC_TCPC_CONNECTOR_ORIENTATION_MASK) #define USB3_PHY_TCA_TCA_TCPC_TCPC_LOW_POWER_EN_MASK (0x8U) #define USB3_PHY_TCA_TCA_TCPC_TCPC_LOW_POWER_EN_SHIFT (3U) /*! TCPC_LOW_POWER_EN - TCPC Low Power Enable * 0b0..Standard operation * 0b1..Disable PHY and use advanced low power strategy (P3.Disable on all PHY lanes with even lower power * consumption than P3). Also puts all the PHY lanes in USB Safe state */ #define USB3_PHY_TCA_TCA_TCPC_TCPC_LOW_POWER_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_TCPC_TCPC_LOW_POWER_EN_SHIFT)) & USB3_PHY_TCA_TCA_TCPC_TCPC_LOW_POWER_EN_MASK) #define USB3_PHY_TCA_TCA_TCPC_TCPC_VALID_MASK (0x10U) #define USB3_PHY_TCA_TCA_TCPC_TCPC_VALID_SHIFT (4U) /*! TCPC_VALID - TCPC Valid */ #define USB3_PHY_TCA_TCA_TCPC_TCPC_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_TCPC_TCPC_VALID_SHIFT)) & USB3_PHY_TCA_TCA_TCPC_TCPC_VALID_MASK) /*! @} */ /*! @name TCA_SYSMODE_CFG - TCA Register for TypeC_MUX Direct Control */ /*! @{ */ #define USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_FLIP_MASK (0x4U) #define USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_FLIP_SHIFT (2U) /*! TYPEC_FLIP - Type-C Flip * 0b0..Normal (CC1=A5, CC2=B5, TX1=A2/A3, RX1=B10/B11) default * 0b1..Flipped (CC2=A5, CC1=B5, TX1=B2/B3, RX1=A10/A11) */ #define USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_FLIP(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_FLIP_SHIFT)) & USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_FLIP_MASK) #define USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_DISABLE_MASK (0x8U) #define USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_DISABLE_SHIFT (3U) /*! TYPEC_DISABLE - Type-C Disable * 0b0..Standard operation * 0b1..Low power/"USB Safe State" operation */ #define USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_DISABLE_SHIFT)) & USB3_PHY_TCA_TCA_SYSMODE_CFG_TYPEC_DISABLE_MASK) /*! @} */ /*! @name TCA_CTRLSYNCMODE_CFG0 - Configuration Register 0 for Controller Synced Mode */ /*! @{ */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SSTX_DETRX_REQ_BLOCK_EN_MASK (0x8U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SSTX_DETRX_REQ_BLOCK_EN_SHIFT (3U) /*! SSTX_DETRX_REQ_BLOCK_EN - SSTX_DETRX_REQ Block Enable * 0b0..Doesn't block sstx_detrx_req to PHY. Relies on controller to disable RxDetect when ss_rxdet_disable is asserted * 0b1..Block sstx_detrx_req to PHY when ss_rxdet_disable to controller is asserted */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SSTX_DETRX_REQ_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SSTX_DETRX_REQ_BLOCK_EN_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SSTX_DETRX_REQ_BLOCK_EN_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SS_HDSHK_REQ_MASK (0x100U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SS_HDSHK_REQ_SHIFT (8U) /*! SS_HDSHK_REQ - Handshake Mechanism With USB Controller * 0b0..Relies on "USB TX/RX lanes reaching P3" * 0b1..Relies on ss_rxdet_disable_ack handshake along with "USB TX/RX lanes reaching P3" */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SS_HDSHK_REQ(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SS_HDSHK_REQ_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_SS_HDSHK_REQ_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_AUTO_SAFE_STATE_MASK (0x10000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_AUTO_SAFE_STATE_SHIFT (16U) /*! AUTO_SAFE_STATE - Automatic Safe State * 0b0..Transient Safe Mode is not used * 0b1..Transient Safe Mode is used asserting typec_disable before the flip change; typec_disable is de-asserted after the configuration change */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_AUTO_SAFE_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_AUTO_SAFE_STATE_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG0_AUTO_SAFE_STATE_MASK) /*! @} */ /*! @name TCA_CTRLSYNCMODE_CFG1 - Configuration Register 1 for Controller Synced Mode */ /*! @{ */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL_MASK (0xFFFFFU) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL_SHIFT (0U) /*! XA_TIMEOUT_VAL - XBar Assist TCPC Request Timeout Value */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_CFG1_XA_TIMEOUT_VAL_MASK) /*! @} */ /*! @name TCA_CTRLSYNCMODE_DBG0 - Debug Register 0 for Controller Synced Mode */ /*! @{ */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_MASK (0x10U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_SHIFT (4U) /*! SS_RXDETECT_DISABLE - SS_RXDETECT_DISABLE Status/Value */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_ACK_MASK (0x20U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_ACK_SHIFT (5U) /*! SS_RXDETECT_DISABLE_ACK - SS_RXDETECT_DISABLE_ACK Status/Value */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_ACK(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_ACK_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_SS_RXDETECT_DISABLE_ACK_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XBAR_READY_MASK (0x1000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XBAR_READY_SHIFT (12U) /*! XBAR_READY - XBAR_READY Status/Value */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XBAR_READY(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XBAR_READY_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XBAR_READY_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_SYNCED_MASK (0x2000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_SYNCED_SHIFT (13U) /*! PSTATE_SYNCED - TCA_CLK Synchronized Status In TCA_PSTATE * 0b0..Status is not synchronized in tca_clk * 0b1..Status is synchronized in tca_clk */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_SYNCED(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_SYNCED_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_SYNCED_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_TIMEOUT_VAL_MASK (0x4000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_TIMEOUT_VAL_SHIFT (14U) /*! PSTATE_TIMEOUT_VAL - PSTATE Timeout Value * 0b0..Current values are shown * 0b1..Values captured at the moment when TCPC request Timeout occurs */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_TIMEOUT_VAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_TIMEOUT_VAL_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_PSTATE_TIMEOUT_VAL_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XA_REQ_COMPL_MULT_MASK (0xF8000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XA_REQ_COMPL_MULT_SHIFT (15U) /*! XA_REQ_COMPL_MULT - Multiplier Value For xa_req_compl_cycles[15:0] Status In TCA_CTRLSYNCMODE_DBG1 */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XA_REQ_COMPL_MULT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XA_REQ_COMPL_MULT_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_XA_REQ_COMPL_MULT_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_EN_MASK (0x1800000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_EN_SHIFT (23U) /*! CTRL_IF_OVRRD_EN - Control If Override Enable */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_EN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_EN_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_EN_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_VAL_MASK (0x30000000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_VAL_SHIFT (28U) /*! CTRL_IF_OVRRD_VAL - Control If Override Value */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_VAL(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_VAL_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG0_CTRL_IF_OVRRD_VAL_MASK) /*! @} */ /*! @name TCA_CTRLSYNCMODE_DBG1 - Debug Register 1 for Controller Synced Mode */ /*! @{ */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_MASK (0xFFFFU) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_SHIFT (0U) /*! XA_REQ_COMPL_CYCLES - TCPC Req Completion Cycles */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_MASK) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_OVERRUN_MASK (0x10000U) #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_OVERRUN_SHIFT (16U) /*! XA_REQ_COMPL_CYCLES_OVERRUN - TCPC Req Completion Cycles Overrun */ #define USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_OVERRUN_SHIFT)) & USB3_PHY_TCA_TCA_CTRLSYNCMODE_DBG1_XA_REQ_COMPL_CYCLES_OVERRUN_MASK) /*! @} */ /*! @name TCA_PSTATE - TCA PSTATE Status */ /*! @{ */ #define USB3_PHY_TCA_TCA_PSTATE_PIPE0_POWERDOWN_MASK (0x3U) #define USB3_PHY_TCA_TCA_PSTATE_PIPE0_POWERDOWN_SHIFT (0U) /*! PIPE0_POWERDOWN - PIPE0 Power Down */ #define USB3_PHY_TCA_TCA_PSTATE_PIPE0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_PSTATE_PIPE0_POWERDOWN_SHIFT)) & USB3_PHY_TCA_TCA_PSTATE_PIPE0_POWERDOWN_MASK) #define USB3_PHY_TCA_TCA_PSTATE_RX_PLL_STATE_MASK (0x4U) #define USB3_PHY_TCA_TCA_PSTATE_RX_PLL_STATE_SHIFT (2U) /*! RX_PLL_STATE - RX PLL State */ #define USB3_PHY_TCA_TCA_PSTATE_RX_PLL_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_PSTATE_RX_PLL_STATE_SHIFT)) & USB3_PHY_TCA_TCA_PSTATE_RX_PLL_STATE_MASK) #define USB3_PHY_TCA_TCA_PSTATE_TX_STATE_MASK (0x8U) #define USB3_PHY_TCA_TCA_PSTATE_TX_STATE_SHIFT (3U) /*! TX_STATE - TX State */ #define USB3_PHY_TCA_TCA_PSTATE_TX_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_PSTATE_TX_STATE_SHIFT)) & USB3_PHY_TCA_TCA_PSTATE_TX_STATE_MASK) #define USB3_PHY_TCA_TCA_PSTATE_TX_CM_STATE_MASK (0x10U) #define USB3_PHY_TCA_TCA_PSTATE_TX_CM_STATE_SHIFT (4U) /*! TX_CM_STATE - TX CM State */ #define USB3_PHY_TCA_TCA_PSTATE_TX_CM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_PSTATE_TX_CM_STATE_SHIFT)) & USB3_PHY_TCA_TCA_PSTATE_TX_CM_STATE_MASK) /*! @} */ /*! @name TCA_GEN_STATUS - TCA General Status */ /*! @{ */ #define USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_FLIP_MASK (0x4U) #define USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_FLIP_SHIFT (2U) /*! PHY_TYPEC_FLIP - PHY Type-C Flip */ #define USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_FLIP(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_FLIP_SHIFT)) & USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_FLIP_MASK) #define USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_DISABLE_MASK (0x8U) #define USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_DISABLE_SHIFT (3U) /*! PHY_TYPEC_DISABLE - PHY Type-C Disable */ #define USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_DISABLE_SHIFT)) & USB3_PHY_TCA_TCA_GEN_STATUS_PHY_TYPEC_DISABLE_MASK) #define USB3_PHY_TCA_TCA_GEN_STATUS_TYPEC_FLIP_INVERT_MASK (0x10U) #define USB3_PHY_TCA_TCA_GEN_STATUS_TYPEC_FLIP_INVERT_SHIFT (4U) /*! TYPEC_FLIP_INVERT - Type-C Flip Invert */ #define USB3_PHY_TCA_TCA_GEN_STATUS_TYPEC_FLIP_INVERT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_GEN_STATUS_TYPEC_FLIP_INVERT_SHIFT)) & USB3_PHY_TCA_TCA_GEN_STATUS_TYPEC_FLIP_INVERT_MASK) #define USB3_PHY_TCA_TCA_GEN_STATUS_REF_CLK_SEL_MASK (0x100U) #define USB3_PHY_TCA_TCA_GEN_STATUS_REF_CLK_SEL_SHIFT (8U) /*! REF_CLK_SEL - Reference Clock Select */ #define USB3_PHY_TCA_TCA_GEN_STATUS_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_GEN_STATUS_REF_CLK_SEL_SHIFT)) & USB3_PHY_TCA_TCA_GEN_STATUS_REF_CLK_SEL_MASK) #define USB3_PHY_TCA_TCA_GEN_STATUS_USB_DEV_POR_MASK (0x1000U) #define USB3_PHY_TCA_TCA_GEN_STATUS_USB_DEV_POR_SHIFT (12U) /*! USB_DEV_POR - USB Device PoR */ #define USB3_PHY_TCA_TCA_GEN_STATUS_USB_DEV_POR(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_GEN_STATUS_USB_DEV_POR_SHIFT)) & USB3_PHY_TCA_TCA_GEN_STATUS_USB_DEV_POR_MASK) /*! @} */ /*! @name TCA_VBUS_CTRL - TCA VBus Assist Control */ /*! @{ */ #define USB3_PHY_TCA_TCA_VBUS_CTRL_VBUSVALID_OVERRD_MASK (0x3U) #define USB3_PHY_TCA_TCA_VBUS_CTRL_VBUSVALID_OVERRD_SHIFT (0U) /*! VBUSVALID_OVERRD - TCA_VBUSVALID Override * 0b00..Drive 0 * 0b01..Drive 1 * 0b10..Follow sys_vbusvalid * 0b11..Follow sys_vbusvalid with XBar_Assist associated override using xbar_ready */ #define USB3_PHY_TCA_TCA_VBUS_CTRL_VBUSVALID_OVERRD(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_CTRL_VBUSVALID_OVERRD_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_CTRL_VBUSVALID_OVERRD_MASK) #define USB3_PHY_TCA_TCA_VBUS_CTRL_POWERPRESENT_OVERRD_MASK (0xCU) #define USB3_PHY_TCA_TCA_VBUS_CTRL_POWERPRESENT_OVERRD_SHIFT (2U) /*! POWERPRESENT_OVERRD - TCA_POWERPRESENT Override * 0b00..Drive 0 * 0b01..Drive 1 * 0b10..Follow sys_vbusvalid * 0b11..Follow sys_vbusvalid with XBar_Assist associated override using xbar_ready */ #define USB3_PHY_TCA_TCA_VBUS_CTRL_POWERPRESENT_OVERRD(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_CTRL_POWERPRESENT_OVERRD_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_CTRL_POWERPRESENT_OVERRD_MASK) #define USB3_PHY_TCA_TCA_VBUS_CTRL_DRV_HOST_VBUS_OVERRD_MASK (0x30U) #define USB3_PHY_TCA_TCA_VBUS_CTRL_DRV_HOST_VBUS_OVERRD_SHIFT (4U) /*! DRV_HOST_VBUS_OVERRD - TCA_DRV_HOST_VBUS Overdrive * 0b00..Drive 0 * 0b01..Drive 1 * 0b10..Drive 0 * 0b11..Use XBar_Assist to drive TCA_DRV_HOST_VBUS */ #define USB3_PHY_TCA_TCA_VBUS_CTRL_DRV_HOST_VBUS_OVERRD(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_CTRL_DRV_HOST_VBUS_OVERRD_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_CTRL_DRV_HOST_VBUS_OVERRD_MASK) #define USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_IDDIG_MASK (0x100U) #define USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_IDDIG_SHIFT (8U) /*! TCA_IDDIG - TCA_IDDIG Control * 0b0..Drive 0 * 0b1..Drive 1 */ #define USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_IDDIG(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_IDDIG_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_IDDIG_MASK) #define USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_MISC_CTRL_MASK (0x7E00U) #define USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_MISC_CTRL_SHIFT (9U) /*! TCA_MISC_CTRL - TCA Miscellaneous Control * 0b000000..Drive 0 * 0b000001..Drive 1 */ #define USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_MISC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_MISC_CTRL_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_CTRL_TCA_MISC_CTRL_MASK) /*! @} */ /*! @name TCA_VBUS_STATUS - TCA VBus Assist Status */ /*! @{ */ #define USB3_PHY_TCA_TCA_VBUS_STATUS_SYS_VBUSVALID_MASK (0x1U) #define USB3_PHY_TCA_TCA_VBUS_STATUS_SYS_VBUSVALID_SHIFT (0U) /*! SYS_VBUSVALID - System VBus Valid */ #define USB3_PHY_TCA_TCA_VBUS_STATUS_SYS_VBUSVALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_STATUS_SYS_VBUSVALID_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_STATUS_SYS_VBUSVALID_MASK) #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_VBUSVALID_MASK (0x2U) #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_VBUSVALID_SHIFT (1U) /*! TCA_VBUSVALID - TCA VBus Valid */ #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_VBUSVALID(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_VBUSVALID_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_VBUSVALID_MASK) #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_POWERPRESENT_MASK (0x4U) #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_POWERPRESENT_SHIFT (2U) /*! TCA_POWERPRESENT - TCA Power Present */ #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_POWERPRESENT(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_POWERPRESENT_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_POWERPRESENT_MASK) #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_DRV_HOST_VBUS_MASK (0x8U) #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_DRV_HOST_VBUS_SHIFT (3U) /*! TCA_DRV_HOST_VBUS - TCA Drive Host VBus */ #define USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_DRV_HOST_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_DRV_HOST_VBUS_SHIFT)) & USB3_PHY_TCA_TCA_VBUS_STATUS_TCA_DRV_HOST_VBUS_MASK) /*! @} */ /*! @name TCA_INFO - TCA Information For Version ID */ /*! @{ */ #define USB3_PHY_TCA_TCA_INFO_VERSION_ID_MASK (0xFFFFFFFFU) #define USB3_PHY_TCA_TCA_INFO_VERSION_ID_SHIFT (0U) /*! VERSION_ID - Version ID For TCA */ #define USB3_PHY_TCA_TCA_INFO_VERSION_ID(x) (((uint32_t)(((uint32_t)(x)) << USB3_PHY_TCA_TCA_INFO_VERSION_ID_SHIFT)) & USB3_PHY_TCA_TCA_INFO_VERSION_ID_MASK) /*! @} */ /*! * @} */ /* end of group USB3_PHY_TCA_Register_Masks */ /* USB3_PHY_TCA - Peripheral instance base addresses */ /** Peripheral HSIO__USB_3_0_PHY__TCA base address */ #define HSIO__USB_3_0_PHY__TCA_BASE (0x4C1FC000u) /** Peripheral HSIO__USB_3_0_PHY__TCA base pointer */ #define HSIO__USB_3_0_PHY__TCA ((USB3_PHY_TCA_Type *)HSIO__USB_3_0_PHY__TCA_BASE) /** Array initializer of USB3_PHY_TCA peripheral base addresses */ #define USB3_PHY_TCA_BASE_ADDRS { HSIO__USB_3_0_PHY__TCA_BASE } /** Array initializer of USB3_PHY_TCA peripheral base pointers */ #define USB3_PHY_TCA_BASE_PTRS { HSIO__USB_3_0_PHY__TCA } /*! * @} */ /* end of group USB3_PHY_TCA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USBNC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer * @{ */ /** USBNC - Register Layout Typedef */ typedef struct { __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ uint8_t RESERVED_0[40]; __IO uint32_t UTMIPHY_CFG1; /**< PHY Configure 1, offset: 0x30 */ } USBNC_Type; /* ---------------------------------------------------------------------------- -- USBNC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBNC_Register_Masks USBNC Register Masks * @{ */ /*! @name CTRL1 - USB OTG Control 1 */ /*! @{ */ #define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) /*! OVER_CUR_DIS - OVER_CUR_DIS * 0b1..Disables overcurrent detection * 0b0..Enables overcurrent detection */ #define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) #define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) #define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) /*! OVER_CUR_POL - OVER_CUR_POL * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ #define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) #define USBNC_CTRL1_PWR_POL_MASK (0x200U) #define USBNC_CTRL1_PWR_POL_SHIFT (9U) /*! PWR_POL - PWR_POL * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ #define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) #define USBNC_CTRL1_WIE_MASK (0x400U) #define USBNC_CTRL1_WIE_SHIFT (10U) /*! WIE - WIE * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ #define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) #define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) #define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) /*! WKUP_SW_EN - WKUP_SW_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) #define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) #define USBNC_CTRL1_WKUP_SW_SHIFT (15U) /*! WKUP_SW - WKUP_SW * 0b1..Force wake-up * 0b0..Inactive */ #define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) #define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) #define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) /*! WKUP_ID_EN - WKUP_ID_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) #define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) /*! WKUP_VBUS_EN - WKUP_VBUS_EN * 0b1..Enable * 0b0..Disable */ #define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) #define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) /*! WKUP_DPDM_EN - Wake-up on DP/DM change enable * 0b1..(Default) DP/DM changes wake-up to be enabled, it is for device only. * 0b0..DP/DM changes wake-up to be disabled only when VBUS is 0. */ #define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) #define USBNC_CTRL1_WIR_MASK (0x80000000U) #define USBNC_CTRL1_WIR_SHIFT (31U) /*! WIR - WIR * 0b1..Wake-up Interrupt Request received * 0b0..No wake-up interrupt request received */ #define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) /*! @} */ /*! @name CTRL2 - USB OTG Control 2 */ /*! @{ */ #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) /*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL * 0b00..vbus_valid * 0b01..sess_valid * 0b10..sess_valid * 0b11..sess_valid */ #define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) #define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) #define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) /*! AUTURESUME_EN - Auto Resume Enable * 0b0..Default */ #define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) #define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) #define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) /*! LOWSPEED_EN - Low speed enable * 0b0..Default */ #define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) #define USBNC_CTRL2_SHORT_PKT_EN_MASK (0x800000U) #define USBNC_CTRL2_SHORT_PKT_EN_SHIFT (23U) /*! SHORT_PKT_EN - Short Packet Interrupt * 0b0..Default */ #define USBNC_CTRL2_SHORT_PKT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_SHORT_PKT_EN_SHIFT)) & USBNC_CTRL2_SHORT_PKT_EN_MASK) #define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) /*! UTMI_CLK_VLD - UTMI_CLK_VLD * 0b0..Default */ #define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) /*! @} */ /*! @name UTMIPHY_CFG1 - PHY Configure 1 */ /*! @{ */ #define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_MASK (0x70U) #define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_SHIFT (4U) /*! COMPDISTUNE0 - Disconnect Threshold Adjustment * 0b000..-9.71% * 0b001..-6.85% * 0b010..-3.36% * 0b011..0, Design default * 0b100..+4.04% * 0b101..+8.22% * 0b110..+13.18% * 0b111..+18.39% */ #define USBNC_UTMIPHY_CFG1_COMPDISTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_COMPDISTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_COMPDISTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_SQRXTUNE0_MASK (0x380U) #define USBNC_UTMIPHY_CFG1_SQRXTUNE0_SHIFT (7U) /*! SQRXTUNE0 - Squelch Threshold Adjustment * 0b000..+15.19% * 0b001..+10.04% * 0b010..+5.14% * 0b011..0, design default * 0b100..-5.04% * 0b101..-10.19% * 0b110..-15.09% * 0b111..-20.24% */ #define USBNC_UTMIPHY_CFG1_SQRXTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_SQRXTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_SQRXTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_OTGTUNE0_MASK (0x1C00U) #define USBNC_UTMIPHY_CFG1_OTGTUNE0_SHIFT (10U) /*! OTGTUNE0 - VBUS Valid Threshold Adjustment * 0b000..-9% * 0b001..-6% * 0b010..-3% * 0b011..0, Design default * 0b100..+3% * 0b101..+6% * 0b110..+9% * 0b111..+12% */ #define USBNC_UTMIPHY_CFG1_OTGTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_OTGTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_OTGTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_MASK (0x6000U) #define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_SHIFT (13U) /*! TXHSXVTUNE0 - Transmitter High-Speed Crossover Adjustment * 0b00..Reserved * 0b01..-17.31 mV * 0b10..-16.69 mV * 0b11..0, design default */ #define USBNC_UTMIPHY_CFG1_TXHSXVTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXHSXVTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_PHY_POR_SW_MASK (0x8000U) #define USBNC_UTMIPHY_CFG1_PHY_POR_SW_SHIFT (15U) /*! PHY_POR_SW - PHY software POR * 0b0..Do not perform the Power-On Reset by software. * 0b1..Perform the Power-On Reset by software. */ #define USBNC_UTMIPHY_CFG1_PHY_POR_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_PHY_POR_SW_SHIFT)) & USBNC_UTMIPHY_CFG1_PHY_POR_SW_MASK) #define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_MASK (0xF0000U) #define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_SHIFT (16U) /*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment * 0b0000..+6.27% * 0b0001..+3.02% * 0b0011..0, design default * 0b0111..-3.23% * 0b1111..-6.25% */ #define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_MASK (0xF00000U) #define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_SHIFT (20U) /*! TXVREFTUNE0 - HS DC Voltage Level Adjustment * 0b0000..-5.88% * 0b0001..-3.92% * 0b0010..-1.96% * 0b0011..0, design default * 0b0100..+1.96% * 0b0101..+3.92% * 0b0110..+5.88% * 0b0111..+7.84% * 0b1000..+9.80% * 0b1001..+11.75% * 0b1010..+13.71% * 0b1011..+15.67% * 0b1100..+17.63% * 0b1101..+19.59% * 0b1110..+21.55% * 0b1111..+23.51% */ #define USBNC_UTMIPHY_CFG1_TXVREFTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXVREFTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXVREFTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_TXRISETUNE0_MASK (0x3000000U) #define USBNC_UTMIPHY_CFG1_TXRISETUNE0_SHIFT (24U) /*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment * 0b00..+3.46% * 0b01..0, Design default * 0b10..-1.47% * 0b11..-3.33% */ #define USBNC_UTMIPHY_CFG1_TXRISETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXRISETUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXRISETUNE0_MASK) #define USBNC_UTMIPHY_CFG1_TXRESTUNE0_MASK (0xC000000U) #define USBNC_UTMIPHY_CFG1_TXRESTUNE0_SHIFT (26U) /*! TXRESTUNE0 - USB Source Impedance Adjustment * 0b00..Source impedance is increased by approximately 3.01 ohm * 0b01..00, design default * 0b10..Source impedance is decreased by approximately 1.32 ohm * 0b11..Source impedance is decreased by approximately 3.71 ohm */ #define USBNC_UTMIPHY_CFG1_TXRESTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXRESTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXRESTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_MASK (0x30000000U) #define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_SHIFT (28U) /*! TXPREEMPAMPTUNE0 - HS Transmitter Pre-Emphasis Current Control * 0b00..HS Transmitter pre-emphasis is disabled. * 0b01..HS Transmitter pre-emphasis circuit sources 1x pre-emphasis current. * 0b10..HS Transmitter pre-emphasis circuit sources 2x pre-emphasis current. * 0b11..HS Transmitter pre-emphasis circuit sources 3x pre-emphasis current. */ #define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_MASK) #define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_MASK (0x40000000U) #define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_SHIFT (30U) /*! TXPREEMPPULSETUNE0 - HS Transmitter Pre-Emphasis Duration Control * 0b0..Design default. Long pre-emphasis current duration * 0b1..Short pre-emphasis current duration */ #define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0(x) (((uint32_t)(((uint32_t)(x)) << USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_SHIFT)) & USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0_MASK) /*! @} */ /*! * @} */ /* end of group USBNC_Register_Masks */ /* USBNC - Peripheral instance base addresses */ /** Peripheral USBNC base address */ #define USBNC_BASE (0x4C200200u) /** Peripheral USBNC base pointer */ #define USBNC ((USBNC_Type *)USBNC_BASE) /** Array initializer of USBNC peripheral base addresses */ #define USBNC_BASE_ADDRS { USBNC_BASE } /** Array initializer of USBNC peripheral base pointers */ #define USBNC_BASE_PTRS { USBNC } /*! * @} */ /* end of group USBNC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VIGNETTING Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VIGNETTING_Peripheral_Access_Layer VIGNETTING Peripheral Access Layer * @{ */ /** VIGNETTING - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x2C */ __IO uint32_t CTRL_CAM; /**< Camera 0 VIGNETTING Control Register, array offset: 0x0, array step: 0x2C */ __IO uint32_t BLK_CONF_CAM; /**< Camera 0 Block Configuration Register, array offset: 0x4, array step: 0x2C */ __IO uint32_t BLK_SIZE_CAM; /**< Camera 0 Block Size Register, array offset: 0x8, array step: 0x2C */ __IO uint32_t BLK_STEPY_CAM; /**< Camera 0 Block Y Step Register, array offset: 0xC, array step: 0x2C */ __IO uint32_t BLK_STEPX_CAM; /**< Camera 0 Block X Step Register, array offset: 0x10, array step: 0x2C */ uint8_t RESERVED_0[12]; __I uint32_t BLK_C_LINE_CAM; /**< Camera 0 Current Line Inside Block Register, array offset: 0x20, array step: 0x2C */ __I uint32_t BLK_C_ROW_CAM; /**< Camera 0 Current Block Row Register, array offset: 0x24, array step: 0x2C */ __I uint32_t BLK_C_FRACY_CAM; /**< Camera 0 Current Y Step Register, array offset: 0x28, array step: 0x2C */ } NEO_PIPE1_VIGNETTING_CONF[1]; } VIGNETTING_Type; /* ---------------------------------------------------------------------------- -- VIGNETTING Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VIGNETTING_Register_Masks VIGNETTING Register Masks * @{ */ /*! @name CTRL_CAM - Camera 0 VIGNETTING Control Register */ /*! @{ */ #define VIGNETTING_CTRL_CAM_ENABLE_MASK (0x80000000U) #define VIGNETTING_CTRL_CAM_ENABLE_SHIFT (31U) /*! ENABLE * 0b0..Disabled; the input pixels are passed unchanged to the output. * 0b1..Enabled */ #define VIGNETTING_CTRL_CAM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_CTRL_CAM_ENABLE_SHIFT)) & VIGNETTING_CTRL_CAM_ENABLE_MASK) /*! @} */ /* The count of VIGNETTING_CTRL_CAM */ #define VIGNETTING_CTRL_CAM_COUNT (1U) /*! @name BLK_CONF_CAM - Camera 0 Block Configuration Register */ /*! @{ */ #define VIGNETTING_BLK_CONF_CAM_COLS_MASK (0xFFU) #define VIGNETTING_BLK_CONF_CAM_COLS_SHIFT (0U) #define VIGNETTING_BLK_CONF_CAM_COLS(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_CONF_CAM_COLS_SHIFT)) & VIGNETTING_BLK_CONF_CAM_COLS_MASK) #define VIGNETTING_BLK_CONF_CAM_ROWS_MASK (0xFF0000U) #define VIGNETTING_BLK_CONF_CAM_ROWS_SHIFT (16U) #define VIGNETTING_BLK_CONF_CAM_ROWS(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_CONF_CAM_ROWS_SHIFT)) & VIGNETTING_BLK_CONF_CAM_ROWS_MASK) /*! @} */ /* The count of VIGNETTING_BLK_CONF_CAM */ #define VIGNETTING_BLK_CONF_CAM_COUNT (1U) /*! @name BLK_SIZE_CAM - Camera 0 Block Size Register */ /*! @{ */ #define VIGNETTING_BLK_SIZE_CAM_XSIZE_MASK (0xFFFFU) #define VIGNETTING_BLK_SIZE_CAM_XSIZE_SHIFT (0U) #define VIGNETTING_BLK_SIZE_CAM_XSIZE(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_SIZE_CAM_XSIZE_SHIFT)) & VIGNETTING_BLK_SIZE_CAM_XSIZE_MASK) #define VIGNETTING_BLK_SIZE_CAM_YSIZE_MASK (0xFFFF0000U) #define VIGNETTING_BLK_SIZE_CAM_YSIZE_SHIFT (16U) #define VIGNETTING_BLK_SIZE_CAM_YSIZE(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_SIZE_CAM_YSIZE_SHIFT)) & VIGNETTING_BLK_SIZE_CAM_YSIZE_MASK) /*! @} */ /* The count of VIGNETTING_BLK_SIZE_CAM */ #define VIGNETTING_BLK_SIZE_CAM_COUNT (1U) /*! @name BLK_STEPY_CAM - Camera 0 Block Y Step Register */ /*! @{ */ #define VIGNETTING_BLK_STEPY_CAM_STEP_MASK (0xFFFFU) #define VIGNETTING_BLK_STEPY_CAM_STEP_SHIFT (0U) #define VIGNETTING_BLK_STEPY_CAM_STEP(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_STEPY_CAM_STEP_SHIFT)) & VIGNETTING_BLK_STEPY_CAM_STEP_MASK) /*! @} */ /* The count of VIGNETTING_BLK_STEPY_CAM */ #define VIGNETTING_BLK_STEPY_CAM_COUNT (1U) /*! @name BLK_STEPX_CAM - Camera 0 Block X Step Register */ /*! @{ */ #define VIGNETTING_BLK_STEPX_CAM_STEP_MASK (0xFFFFU) #define VIGNETTING_BLK_STEPX_CAM_STEP_SHIFT (0U) #define VIGNETTING_BLK_STEPX_CAM_STEP(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_STEPX_CAM_STEP_SHIFT)) & VIGNETTING_BLK_STEPX_CAM_STEP_MASK) /*! @} */ /* The count of VIGNETTING_BLK_STEPX_CAM */ #define VIGNETTING_BLK_STEPX_CAM_COUNT (1U) /*! @name BLK_C_LINE_CAM - Camera 0 Current Line Inside Block Register */ /*! @{ */ #define VIGNETTING_BLK_C_LINE_CAM_LINE_MASK (0xFFFFU) #define VIGNETTING_BLK_C_LINE_CAM_LINE_SHIFT (0U) #define VIGNETTING_BLK_C_LINE_CAM_LINE(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_C_LINE_CAM_LINE_SHIFT)) & VIGNETTING_BLK_C_LINE_CAM_LINE_MASK) /*! @} */ /* The count of VIGNETTING_BLK_C_LINE_CAM */ #define VIGNETTING_BLK_C_LINE_CAM_COUNT (1U) /*! @name BLK_C_ROW_CAM - Camera 0 Current Block Row Register */ /*! @{ */ #define VIGNETTING_BLK_C_ROW_CAM_BLKROW_MASK (0xFFU) #define VIGNETTING_BLK_C_ROW_CAM_BLKROW_SHIFT (0U) #define VIGNETTING_BLK_C_ROW_CAM_BLKROW(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_C_ROW_CAM_BLKROW_SHIFT)) & VIGNETTING_BLK_C_ROW_CAM_BLKROW_MASK) /*! @} */ /* The count of VIGNETTING_BLK_C_ROW_CAM */ #define VIGNETTING_BLK_C_ROW_CAM_COUNT (1U) /*! @name BLK_C_FRACY_CAM - Camera 0 Current Y Step Register */ /*! @{ */ #define VIGNETTING_BLK_C_FRACY_CAM_FRAC_MASK (0xFFFFFFFFU) #define VIGNETTING_BLK_C_FRACY_CAM_FRAC_SHIFT (0U) #define VIGNETTING_BLK_C_FRACY_CAM_FRAC(x) (((uint32_t)(((uint32_t)(x)) << VIGNETTING_BLK_C_FRACY_CAM_FRAC_SHIFT)) & VIGNETTING_BLK_C_FRACY_CAM_FRAC_MASK) /*! @} */ /* The count of VIGNETTING_BLK_C_FRACY_CAM */ #define VIGNETTING_BLK_C_FRACY_CAM_COUNT (1U) /*! * @} */ /* end of group VIGNETTING_Register_Masks */ /* VIGNETTING - Peripheral instance base addresses */ /** Peripheral CAMERA__ISP__VIGNETTING base address */ #define CAMERA__ISP__VIGNETTING_BASE (0x4AE00900u) /** Peripheral CAMERA__ISP__VIGNETTING base pointer */ #define CAMERA__ISP__VIGNETTING ((VIGNETTING_Type *)CAMERA__ISP__VIGNETTING_BASE) /** Array initializer of VIGNETTING peripheral base addresses */ #define VIGNETTING_BASE_ADDRS { CAMERA__ISP__VIGNETTING_BASE } /** Array initializer of VIGNETTING peripheral base pointers */ #define VIGNETTING_BASE_PTRS { CAMERA__ISP__VIGNETTING } /*! * @} */ /* end of group VIGNETTING_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VPU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_Peripheral_Access_Layer VPU Peripheral Access Layer * @{ */ /** VPU - Register Layout Typedef */ typedef struct { __IO uint32_t CMD_CONTROL_REG_HOST_GLOBAL_WR; /**< HOST_GLOBAL_WR, offset: 0x0 */ __I uint32_t CMD_CONTROL_REG_OPTION; /**< Current PC, offset: 0x4 */ __I uint32_t CMD_CONTROL_REG_RET_SUCCESS; /**< Current LR, offset: 0x8 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_17; /**< Debugging message, offset: 0xC */ __I uint32_t CMD_CONTROL_REG_INSTANCE_INFO; /**< Debugging message, offset: 0x10 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_19; /**< Debugging message, offset: 0x14 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_20; /**< Debugging message, offset: 0x18 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_21; /**< Debugging message, offset: 0x1C */ __IO uint32_t CMD_CONTROL_REG_VPU_FIO_ADDR; /**< FastIO Control/Address, offset: 0x20 */ __IO uint32_t CMD_CONTROL_REG_VPU_FIO_DATA; /**< FastIO Data, offset: 0x24 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_0; /**< Debugging message, offset: 0x28 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_1; /**< Debugging message, offset: 0x2C */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_22; /**< Debugging message, offset: 0x30 */ __O uint32_t CMD_CONTROL_REG_VPU_VINT_REASON_CLR; /**< Interrupt Reason Clear, offset: 0x34 */ __O uint32_t CMD_CONTROL_REG_VPU_HOST_INT_REQ; /**< Host Interrupt Request, offset: 0x38 */ __O uint32_t CMD_CONTROL_REG_VPU_VINT_CLEAR; /**< VPU Interrupt Clear, offset: 0x3C */ __I uint32_t CMD_CONTROL_REG_VPU_HINT_CLEAR; /**< Host Interrupt Clear, offset: 0x40 */ __I uint32_t CMD_CONTROL_REG_VPU_VPU_INT_STS; /**< VPU Interrupt Status, offset: 0x44 */ __IO uint32_t CMD_CONTROL_REG_VPU_VINT_ENABLE; /**< VPU Interrupt Enable, offset: 0x48 */ __IO uint32_t CMD_CONTROL_REG_VPU_VINT_REASON; /**< VPU Interrupt Reason, offset: 0x4C */ uint8_t RESERVED_0[32]; __IO uint32_t CMD_CONTROL_REG_VCPU_CMD_BUSY_STATUS; /**< V-CPU Busy Status, offset: 0x70 */ __I uint32_t CMD_CONTROL_REG_VPU_HALT_STATUS; /**< VPU Halt Status, offset: 0x74 */ __I uint32_t CMD_CONTROL_REG_VPU_VCPU_STATUS; /**< VPU_VCPU_STATUS, offset: 0x78 */ __I uint32_t CMD_CONTROL_REG_VPU_BUSY_STATUS; /**< VPU Busy Status, offset: 0x7C */ __I uint32_t CMD_CONTROL_REG_RET_FIO_STATUS; /**< ret_fio_status, offset: 0x80 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_3; /**< Debugging message, offset: 0x84 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_4; /**< Debugging message, offset: 0x88 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_5; /**< Debugging message, offset: 0x8C */ __I uint32_t CMD_CONTROL_REG_RET_PRODUCT_NAME; /**< HW product name, offset: 0x90 */ __I uint32_t CMD_CONTROL_REG_RET_PRODUCT_VERSION; /**< HW product version, offset: 0x94 */ __I uint32_t CMD_CONTROL_REG_RET_VCPU_CONFIG0; /**< Configuration Information #0, offset: 0x98 */ __I uint32_t CMD_CONTROL_REG_RET_VCPU_CONFIG1; /**< Configuration Information #1, offset: 0x9C */ __I uint32_t CMD_CONTROL_REG_RET_CODEC_STD; /**< Standard Definition, offset: 0xA0 */ __I uint32_t CMD_CONTROL_REG_RET_CONF_DATE; /**< Configuration Date, offset: 0xA4 */ __I uint32_t CMD_CONTROL_REG_RET_CONF_REVISION; /**< The revision of H/W configuration, offset: 0xA8 */ __I uint32_t CMD_CONTROL_REG_RET_CONF_TYPE; /**< The define value of H/W configuration, offset: 0xAC */ __I uint32_t CMD_CONTROL_REG_RET_VCORE0_CFG; /**< Configuration Information of VCORE0, offset: 0xB0 */ __I uint32_t CMD_CONTROL_REG_RET_VCORE1_CFG; /**< Configuration Information of VCORE1, offset: 0xB4 */ __I uint32_t CMD_CONTROL_REG_RET_VCORE2_CFG; /**< Configuration Information of VCORE2, offset: 0xB8 */ __I uint32_t CMD_CONTROL_REG_RET_VCORE3_CFG; /**< Configuration Information of VCORE3, offset: 0xBC */ __I uint32_t CMD_CONTROL_REG_VPU_RET_VCORE_PRESENT; /**< Number of VCOREs present, offset: 0xC0 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_6; /**< Debugging message, offset: 0xC4 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_7; /**< Debugging message, offset: 0xC8 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_8; /**< Debugging message, offset: 0xCC */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_9; /**< Debugging message, offset: 0xD0 */ uint8_t RESERVED_1[4]; __I uint32_t CMD_CONTROL_REG_DBG_MSG_10; /**< Debugging message, offset: 0xD8 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_11; /**< Debugging message, offset: 0xDC */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_12; /**< Debugging message, offset: 0xE0 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_13; /**< Debugging message, offset: 0xE4 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_14; /**< Debugging message, offset: 0xE8 */ __I uint32_t CMD_CONTROL_REG_DBG_MSG_15; /**< Debugging message, offset: 0xEC */ __IO uint32_t CMD_CONTROL_REG_VPU_DBG_SW_UART_STATUS; /**< VPU_dbg_sw_uart_status, offset: 0xF0 */ __IO uint32_t CMD_CONTROL_REG_VPU_DBG_SW_UART_TX; /**< VPU_ dbg_sw_uart_tx, offset: 0xF4 */ __IO uint32_t CMD_CONTROL_REG_VPU_DBG_REG_0; /**< VPU_dbg_reg, offset: 0xF8 */ __IO uint32_t CMD_CONTROL_REG_VPU_DBG_REG_1; /**< VPU_dbg_reg, offset: 0xFC */ uint8_t RESERVED_2[28]; __IO uint32_t CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL; /**< VPU SFS Control, offset: 0x11C */ uint8_t RESERVED_3[224]; __IO uint32_t CMD_COMMAND; /**< Command, offset: 0x200 */ union { /* offset: 0x204 */ __IO uint32_t CMD_COMMAND_OPTION; /**< Command Option, offset: 0x204 */ __IO uint32_t CMD_DEC_PIC_OPTION; /**< decoding picture option, offset: 0x204 */ __IO uint32_t CMD_ENC_SET_PARAM_OPTION; /**< CMD_ENC_SET_PARAM option, offset: 0x204 */ __IO uint32_t CMD_INIT_SEQ_OPTION; /**< Run command option, offset: 0x204 */ __IO uint32_t CMD_SET_DISP_OPTION; /**< SET_DISP_command option, offset: 0x204 */ __IO uint32_t CMD_SET_FB_OPTION; /**< SET_FB command option, offset: 0x204 */ __IO uint32_t CMD_SET_FB_UPDATE_OPTION; /**< Run command option, offset: 0x204 */ }; __IO uint32_t CMD_COMMAND_RET_SUCCESS; /**< Result of the command, offset: 0x208 */ __IO uint32_t CMD_COMMAND_RET_FAIL_REASON; /**< Fail reason of the run command, offset: 0x20C */ __IO uint32_t CMD_COMMAND_INSTANCE_INFO; /**< Instance information, offset: 0x210 */ __IO uint32_t CMD_COMMAND_QUE_FULL_IDC; /**< cmd queue full indicator, offset: 0x214 */ __IO uint32_t CMD_COMMAND_RET_QUE_EMPTY_IDC; /**< cmd queue empty indicator, offset: 0x218 */ __IO uint32_t CMD_COMMAND_DONE_INST_IDC; /**< cmd done instance id, offset: 0x21C */ __IO uint32_t CMD_COMMAND_RET_CREATE_INSTANCE_ID; /**< instance id, offset: 0x220 */ uint8_t RESERVED_4[24]; __IO uint32_t CMD_COMMAND_RET_CMD_CQ_IN_TICK; /**< cmd queue in tick, offset: 0x23C */ __IO uint32_t CMD_COMMAND_RET_CMD_FW_RUN_TICK; /**< cmd fw run tick, offset: 0x240 */ __IO uint32_t CMD_COMMAND_RET_CMD_HW_RUN_TICK; /**< cmd hw_core run tick, offset: 0x244 */ __IO uint32_t CMD_COMMON_RET_CMD_HW_DONE_TICK; /**< cmd hw_core done tick, offset: 0x248 */ __IO uint32_t CMD_COMMON_RET_CMD_FW_DONE_TICK; /**< cmd fw done tick, offset: 0x24C */ __IO uint32_t CMD_COMMON_RET_CMD_RQ_OUT_TICK; /**< cmd return queue out tick, offset: 0x250 */ __IO uint32_t CMD_COMMON_RET_CMD_FW_PRE_RUN_TICK; /**< cmd fw pre-core run tick, offset: 0x254 */ __IO uint32_t CMD_COMMON_RET_CMD_HW_PRE_RUN_TICK; /**< cmd hw pre-core run tick, offset: 0x258 */ __IO uint32_t CMD_COMMON_RET_CMD_HW_PRE_DONE_TICK; /**< cmd hw pre-core done tick, offset: 0x25C */ __IO uint32_t CMD_COMMON_RET_CMD_FW_PRE_DONE_TICK; /**< cmd fw pre-core done tick, offset: 0x260 */ uint8_t RESERVED_5[156]; union { /* offset: 0x300 */ __IO uint32_t CMD_CREATE_INST_WORK_BASE; /**< Work buffer base address, offset: 0x300 */ __IO uint32_t CMD_DEC_GET_RESULT_ADDR_USERDATA_BASE; /**< User Data Buffer Base Address, offset: 0x300 */ __IO uint32_t CMD_DEC_PIC_BS_RD_PTR; /**< Bistream Buffer Read Pointer, offset: 0x300 */ __IO uint32_t CMD_ENC_GET_RESULT_RD_PTR; /**< bitstream buffer read pointer, offset: 0x300 */ __IO uint32_t CMD_ENC_PIC_BS_START; /**< Bitstream buffer start address, offset: 0x300 */ __IO uint32_t CMD_ENC_SET_PARAM_ENABLE; /**< Change parameter enable flags, offset: 0x300 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM; /**< Bitstream sequence parameter information, offset: 0x300 */ __IO uint32_t CMD_INIT_SEQ_BS_RD_PTR; /**< Bitstream buffer read pointer, offset: 0x300 */ __IO uint32_t CMD_SET_DISP_COMMON_PIC_INFO; /**< DPB information, offset: 0x300 */ __IO uint32_t CMD_SET_FB_PIC_INFO; /**< DPB information, offset: 0x300 */ __IO uint32_t CMD_SET_FB_UPDATE_COMMON_PIC_INFO; /**< DPB information, offset: 0x300 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_0; /**< bitstream buffer read pointer, offset: 0x300 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_0; /**< Display picture address for release, offset: 0x300 */ }; union { /* offset: 0x304 */ __IO uint32_t CMD_CREATE_INST_WORK_BUF_SIZE; /**< Work buffer size, offset: 0x304 */ __IO uint32_t CMD_DEC_GET_RESULT_USERDATA_SIZE; /**< User Data Buffer Size, offset: 0x304 */ __IO uint32_t CMD_DEC_PIC_BS_WR_PTR; /**< Bistream Buffer Write Pointer, offset: 0x304 */ __IO uint32_t CMD_ENC_GET_RESULT_WR_PTR; /**< bitstream buffer write pointer, offset: 0x304 */ __IO uint32_t CMD_ENC_PIC_BS_SIZE; /**< Bitstream buffer size, offset: 0x304 */ __IO uint32_t CMD_ENC_SET_PARAM_SRC_SIZE; /**< A size of source picture, offset: 0x304 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO; /**< Color Sample Information, offset: 0x304 */ __IO uint32_t CMD_INIT_SEQ_BS_WR_PTR; /**< Bitstream buffer write pointer, offset: 0x304 */ __IO uint32_t CMD_SET_DISP_PIC_SIZE; /**< Picture size parsed form stream, offset: 0x304 */ __IO uint32_t CMD_SET_FB_PIC_SIZE; /**< Decoded picture size, offset: 0x304 */ __IO uint32_t CMD_SET_FB_UPDATE_PIC_SIZE; /**< FBC Picture Size, offset: 0x304 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_1; /**< bitstream buffer read pointer, offset: 0x304 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1; /**< Display picture address for release, offset: 0x304 */ }; union { /* offset: 0x308 */ __IO uint32_t CMD_DEC_PIC_BS_OPTION; /**< Bitstream buffer option, offset: 0x308 */ __IO uint32_t CMD_ENC_GET_RESULT_NUM_REQUIRED_FB; /**< Minimum number of reference frame buffer required for encoding, offset: 0x308 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_MAP_ENDIAN; /**< Custom map endianness, offset: 0x308 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO; /**< Sample Aspect Ratio, offset: 0x308 */ __IO uint32_t CMD_INIT_SEQ_BS_OPTION; /**< Bitstream buffer option, offset: 0x308 */ __IO uint32_t CMD_SET_DISP_PIC_INFO; /**< Input DPB information, offset: 0x308 */ __IO uint32_t CMD_SET_FB_NUM; /**< The number of start/end frame buffer to set, offset: 0x308 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_2; /**< bitstream buffer read pointer, offset: 0x308 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_2; /**< Display picture address for release, offset: 0x308 */ }; union { /* offset: 0x30C */ __IO uint32_t CMD_DEC_GET_RESULT_BS_RD_PTR; /**< Bitstream buffer read pointer, offset: 0x30C */ __IO uint32_t CMD_DEC_PIC_USE_SEC_AXI; /**< Secondary AXI usage option, offset: 0x30C */ __IO uint32_t CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM; /**< Minimum number of source frame buffer required for encoding, offset: 0x30C */ __IO uint32_t CMD_ENC_PIC_USE_SEC_AXI; /**< Secondary AXI usage option, offset: 0x30C */ __IO uint32_t CMD_ENC_SET_FB_FBC_STRIDE; /**< Frame buffer setting for compressed frame, offset: 0x30C */ __IO uint32_t CMD_ENC_SET_PARAM_SPS_PARAM; /**< Encoder sequence parameters, offset: 0x30C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_BIT_RATE; /**< Maximum Bit Rate, offset: 0x30C */ __IO uint32_t CMD_SET_DISP_ADDR_Y_BASE; /**< Luma base, offset: 0x30C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_3; /**< bitstream buffer read pointer, offset: 0x30C */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_3; /**< Display picture address for release, offset: 0x30C */ }; union { /* offset: 0x310 */ __IO uint32_t CMD_CREATE_INST_BS_PARAM; /**< Bitstream buffer param, offset: 0x310 */ __IO uint32_t CMD_DEC_GET_RESULT_SEQ_PARAM; /**< Bitstream sequence parameter information, offset: 0x310 */ __IO uint32_t CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG; /**< Sequence change flag, offset: 0x310 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_TYPE; /**< Encoded picture type, offset: 0x310 */ __IO uint32_t CMD_ENC_PIC_REPORT_PARAM; /**< Report parameters, offset: 0x310 */ __IO uint32_t CMD_ENC_SET_PARAM_PPS_PARAM; /**< encoder picture parameters, offset: 0x310 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_NR; /**< Frame Rate Numerator, offset: 0x310 */ __IO uint32_t CMD_SET_DISP_ADDR_CB_BASE; /**< Cb base, offset: 0x310 */ __IO uint32_t CMD_SET_FB_FBC_Y0; /**< Luma base of index0, offset: 0x310 */ __IO uint32_t CMD_SET_FB_UPDATE_FBC_Y; /**< Luma base of FBC idx to be update, offset: 0x310 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_4; /**< bitstream buffer read pointer, offset: 0x310 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_4; /**< Display picture address for release, offset: 0x310 */ }; union { /* offset: 0x314 */ __IO uint32_t CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO; /**< Color Sample Information, offset: 0x314 */ __IO uint32_t CMD_DEC_PIC_USERDATA_MASK; /**< User Data Mask, offset: 0x314 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_POC; /**< A POC value of encoded picture, offset: 0x314 */ __IO uint32_t CMD_ENC_SET_PARAM_GOP_PARAM; /**< GOP parameters, offset: 0x314 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_DR; /**< Frame Rate Denominator, offset: 0x314 */ __IO uint32_t CMD_INIT_SEQ_SEI_MASK; /**< User Data Mask, offset: 0x314 */ __IO uint32_t CMD_SET_DISP_ADDR_CR_BASE; /**< Cr base, offset: 0x314 */ __IO uint32_t CMD_SET_FB_FBC_C0; /**< Cb base of index0, offset: 0x314 */ __IO uint32_t CMD_SET_FB_UPDATE_FBC_C; /**< Cb base of FBC idx to be update, offset: 0x314 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_5; /**< bitstream buffer read pointer, offset: 0x314 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_5; /**< Display picture address for release, offset: 0x314 */ }; union { /* offset: 0x318 */ __IO uint32_t CMD_CREATE_INST_ADDR_EXT; /**< AXI Address Extension, offset: 0x318 */ __IO uint32_t CMD_DEC_GET_RESULT_ASPECT_RATIO; /**< Sample Aspect Ratio, offset: 0x318 */ __IO uint32_t CMD_DEC_PIC_TEMPORAL_ID_PLUS1; /**< Max Decode Temporal ID, offset: 0x318 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_IDX; /**< Frame buffer index of encoded picture, offset: 0x318 */ __IO uint32_t CMD_ENC_PIC_MV_HISTO_CLASS0; /**< MV histogram threshold, offset: 0x318 */ __IO uint32_t CMD_ENC_SET_PARAM_INTRA_PARAM; /**< Intra picture coding parameters, offset: 0x318 */ __IO uint32_t CMD_ENC_SET_PARAM_INTRA_PARAM_AVC; /**< Intra picture coding parameters, offset: 0x318 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_FBC_FB; /**< Required Number of Minimum fbc DPB, offset: 0x318 */ __IO uint32_t CMD_SET_DISP_DEC_PP_SCL_PARAM; /**< scaler control paramter, offset: 0x318 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET0; /**< FBC luma offset base of index0, offset: 0x318 */ __IO uint32_t CMD_SET_FB_UPDATE_FBC_Y_OFFSET; /**< FBC luma offset base of updated index, offset: 0x318 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_6; /**< bitstream buffer read pointer, offset: 0x318 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_6; /**< Display picture address for release, offset: 0x318 */ }; union { /* offset: 0x31C */ __IO uint32_t CMD_CREATE_INST_DISP_MODE; /**< Display order for BWB output, offset: 0x31C */ __IO uint32_t CMD_DEC_GET_RESULT_BIT_RATE; /**< Maximum Bit Rate, offset: 0x31C */ __IO uint32_t CMD_DEC_PIC_FORCE_FB_LATENCY_PLUS1; /**< User define display latency, offset: 0x31C */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_SLICE_NUM; /**< Number of slice, offset: 0x31C */ __IO uint32_t CMD_ENC_PIC_MV_HISTO_CLASS1; /**< MV histogram threshold, offset: 0x31C */ __IO uint32_t CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT; /**< Top and bottom size for conformance window, offset: 0x31C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_NUM_REORDER_DELAY; /**< Reorder frame number, offset: 0x31C */ __IO uint32_t CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE; /**< Scaled picture size, offset: 0x31C */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET0; /**< FBC chroma offset base of index0, offset: 0x31C */ __IO uint32_t CMD_SET_FB_UPDATE_FBC_C_OFFSET; /**< FBC chroma offset base of updated index, offset: 0x31C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_7; /**< bitstream buffer read pointer, offset: 0x31C */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_7; /**< Display picture address for release, offset: 0x31C */ }; union { /* offset: 0x320 */ __IO uint32_t CMD_DEC_GET_RESULT_FRAME_RATE_NR; /**< Frame Rate Numerator, offset: 0x320 */ __IO uint32_t CMD_DEC_PIC_USERDATA_BASE; /**< User Data Buffer Base Address, offset: 0x320 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_SKIP; /**< A picture skip flag, offset: 0x320 */ __IO uint32_t CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM; /**< Custom map parameters, offset: 0x320 */ __IO uint32_t CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT; /**< Left and right size for conformance window, offset: 0x320 */ __IO uint32_t CMD_INIT_SEQ_ADDR_USERDATA_BASE; /**< User Data Buffer Base Address, offset: 0x320 */ __IO uint32_t CMD_SET_DISP_DEC_PP_CROP_PARAM; /**< Crop ctrl parameter, offset: 0x320 */ __IO uint32_t CMD_SET_FB_MV_COL0; /**< info base of index0, offset: 0x320 */ __IO uint32_t CMD_SET_FB_UPDATE_MV_COL; /**< Col base of col idx to be update, offset: 0x320 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_8; /**< bitstream buffer read pointer, offset: 0x320 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_8; /**< Display picture address for release, offset: 0x320 */ }; union { /* offset: 0x324 */ __IO uint32_t CMD_DEC_GET_RESULT_FRAME_RATE_DR; /**< Frame Rate Denominator, offset: 0x324 */ __IO uint32_t CMD_DEC_PIC_USERDATA_SIZE; /**< User Data Buffer Size, offset: 0x324 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_NUM_INTRA; /**< Number of intra block, offset: 0x324 */ __IO uint32_t CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR; /**< Custom map address, offset: 0x324 */ __IO uint32_t CMD_ENC_SET_PARAM_RDO_PARAM; /**< RDO coding options, offset: 0x324 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_PIC_SIZE; /**< Decoded Picture Size, offset: 0x324 */ __IO uint32_t CMD_INIT_SEQ_USERDATA_SIZE; /**< User Data Buffer Size, offset: 0x324 */ __IO uint32_t CMD_SET_DISP_DEC_PP_CROP_POS; /**< Crop start position for output image, offset: 0x324 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED0; /**< Sub sampled base of index0, offset: 0x324 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_9; /**< bitstream buffer read pointer, offset: 0x324 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_9; /**< Display picture address for release, offset: 0x324 */ }; union { /* offset: 0x328 */ __IO uint32_t CMD_DEC_GET_RESULT_NUM_REQUIRED_FBC_FB; /**< Required Number of Minimum fbc DPB, offset: 0x328 */ __IO uint32_t CMD_DEC_PIC_USERDATA_PARAM; /**< User Data Buffer Parameter, offset: 0x328 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_NUM_MERGE; /**< Number of merge block, offset: 0x328 */ __IO uint32_t CMD_ENC_SET_PARAM_SLICE_PARAM; /**< Slice parameters, offset: 0x328 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM; /**< Display Crop Offset Top/Bottom, offset: 0x328 */ __IO uint32_t CMD_INIT_SEQ_USERDATA_PARAM; /**< User Data Buffer Parameter, offset: 0x328 */ __IO uint32_t CMD_SET_DISP_DEC_PP_CROP_SIZE; /**< Crop size for output image, offset: 0x328 */ __IO uint32_t CMD_SET_FB_FBC_Y1; /**< Luma base of index1, offset: 0x328 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_A; /**< bitstream buffer read pointer, offset: 0x328 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_A; /**< Display picture address for release, offset: 0x328 */ }; union { /* offset: 0x32C */ __IO uint32_t CMD_DEC_GET_RESULT_NUM_REORDER_DELAY; /**< Reorder frame number, offset: 0x32C */ __IO uint32_t CMD_DEC_PIC_TIMESTAMP; /**< CMD_DEC_PIC_TIMESTAMP, offset: 0x32C */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_NON_REF_PIC_FLAG; /**< Non reference picture flag, offset: 0x32C */ __IO uint32_t CMD_ENC_PIC_SRC_PIC_IDX; /**< Buffer index of source picture, offset: 0x32C */ __IO uint32_t CMD_ENC_SET_PARAM_INTRA_REFRESH; /**< Intra refresh mode, offset: 0x32C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT; /**< Display Crop Offset Left/Right, offset: 0x32C */ __IO uint32_t CMD_SET_FB_FBC_C1; /**< Cb base of index1, offset: 0x32C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_B; /**< bitstream buffer read pointer, offset: 0x32C */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_B; /**< Display picture address for release, offset: 0x32C */ }; union { /* offset: 0x330 */ __IO uint32_t CMD_CREATE_INST_CORE_INFO; /**< Dual Core information, offset: 0x330 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_NUM_SKIP; /**< Number of skip block, offset: 0x330 */ __IO uint32_t CMD_ENC_PIC_SRC_ADDR_Y; /**< Y component source address, offset: 0x330 */ __IO uint32_t CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP; /**< Min/Max QP for Intra pictures, offset: 0x330 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_COL_BUF; /**< Required Number of Minimum col buf, offset: 0x330 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET1; /**< FBC luma offset base of index1, offset: 0x330 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_C; /**< bitstream buffer read pointer, offset: 0x330 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_C; /**< Display picture address for release, offset: 0x330 */ }; union { /* offset: 0x334 */ __IO uint32_t CMD_CREATE_INST_PRIORITY; /**< Instance priority, offset: 0x334 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_AVG_CTU_QP; /**< CTU QP on average, offset: 0x334 */ __IO uint32_t CMD_ENC_PIC_SRC_ADDR_U; /**< Cb component source address, offset: 0x334 */ __IO uint32_t CMD_ENC_SET_PARAM_RC_FRAME_RATE; /**< Frame rate for rate control, offset: 0x334 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_NOTIFICATION; /**< Sequence change flag, offset: 0x334 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET1; /**< FBC chroma offset base of index1, offset: 0x334 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_D; /**< bitstream buffer read pointer, offset: 0x334 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_D; /**< Display picture address for release, offset: 0x334 */ }; union { /* offset: 0x338 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_BYTE; /**< Byte size of encoded picture, offset: 0x338 */ __IO uint32_t CMD_ENC_PIC_SRC_ADDR_V; /**< Cr component source address, offset: 0x338 */ __IO uint32_t CMD_ENC_SET_PARAM_RC_TARGET_RATE; /**< Target bitrate, offset: 0x338 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_FB_OPT; /**< Frame_buffer_full_option, offset: 0x338 */ __IO uint32_t CMD_SET_DISP_DEC_PP_PVRIC_CTRL; /**< PVRIC control resigster, offset: 0x338 */ __IO uint32_t CMD_SET_FB_MV_COL1; /**< COL base of index1, offset: 0x338 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_E; /**< bitstream buffer read pointer, offset: 0x338 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_E; /**< Display picture address for release, offset: 0x338 */ }; union { /* offset: 0x33C */ __IO uint32_t CMD_ENC_GET_RESULT_GOP_PIC_IDX; /**< A picture index in GOP, offset: 0x33C */ __IO uint32_t CMD_ENC_PIC_SRC_STRIDE; /**< Stride of source picture, offset: 0x33C */ __IO uint32_t CMD_ENC_SET_PARAM_RC_PARAM; /**< Rate control parameters, offset: 0x33C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_NUM; /**< Number of valid release linear buffer address, offset: 0x33C */ __IO uint32_t CMD_SET_DISP_DEC_PP_AFBC_COMMON; /**< AFBC control paramter, offset: 0x33C */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED1; /**< Sub sampled base of index1, offset: 0x33C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_F; /**< bitstream buffer read pointer, offset: 0x33C */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_F; /**< Display picture address for release, offset: 0x33C */ }; union { /* offset: 0x340 */ __IO uint32_t CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM; /**< Display Crop Offset Top/Bottom, offset: 0x340 */ __IO uint32_t CMD_ENC_GET_RESULT_USED_SRC_IDX; /**< Buffer index of source picture that is used for encoding, offset: 0x340 */ __IO uint32_t CMD_ENC_PIC_SRC_FORMAT; /**< Format of source picture, offset: 0x340 */ __IO uint32_t CMD_ENC_SET_PARAM_HVS_PARAM; /**< HVS parameters, offset: 0x340 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_0; /**< Display picture address for release, offset: 0x340 */ __IO uint32_t CMD_SET_FB_FBC_Y2; /**< Luma base of index2, offset: 0x340 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_10; /**< bitstream buffer read pointer, offset: 0x340 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_10; /**< Display picture address for release, offset: 0x340 */ }; union { /* offset: 0x344 */ __IO uint32_t CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT; /**< Display Crop Offset Left/Right, offset: 0x344 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_NUM; /**< Encoded picture number, offset: 0x344 */ __IO uint32_t CMD_ENC_SET_PARAM_RC_MAX_BITRATE; /**< RC_MAX_BITRATE, offset: 0x344 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1; /**< Display picture address for release, offset: 0x344 */ __IO uint32_t CMD_SET_FB_FBC_C2; /**< Cb base of index2, offset: 0x344 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_11; /**< bitstream buffer read pointer, offset: 0x344 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_11; /**< Display picture address for release, offset: 0x344 */ }; union { /* offset: 0x348 */ __IO uint32_t CMD_CREATE_INST_TEMP_BASE; /**< Temporal buffer base address, offset: 0x348 */ __IO uint32_t CMD_DEC_GET_RESULT_AU_START_POS; /**< AU Bitstream Start Position, offset: 0x348 */ __IO uint32_t CMD_ENC_GET_RESULT_VCL_NUT; /**< Encoded NAL unit type of VCL, offset: 0x348 */ __IO uint32_t CMD_ENC_PIC_SRC_AXI_SEL; /**< Selection of source AXI port, offset: 0x348 */ __IO uint32_t CMD_ENC_SET_PARAM_RC_VBV_BUFFER_SIZE; /**< RC_VBV_BUFFER_SIZE, offset: 0x348 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_2; /**< Display picture address for release, offset: 0x348 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET2; /**< FBC luma offset base of index2, offset: 0x348 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_12; /**< bitstream buffer read pointer, offset: 0x348 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_12; /**< Display picture address for release, offset: 0x348 */ }; union { /* offset: 0x34C */ __IO uint32_t CMD_CREATE_INST_TEMP_SIZE; /**< Temporal buffer size, offset: 0x34C */ __IO uint32_t CMD_DEC_GET_RESULT_AU_END_POS; /**< AU Bitstream End Position, offset: 0x34C */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_PADD_BYTE; /**< Encoded NAL padding byte num, offset: 0x34C */ __IO uint32_t CMD_ENC_PIC_CODE_OPTION; /**< NAL unit coding options, offset: 0x34C */ __IO uint32_t CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP; /**< Min/Max QP for Inter pictures, offset: 0x34C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_3; /**< Display picture address for release, offset: 0x34C */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET2; /**< FBC chroma offset base of index2, offset: 0x34C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_13; /**< bitstream buffer read pointer, offset: 0x34C */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_13; /**< Display picture address for release, offset: 0x34C */ }; union { /* offset: 0x350 */ __IO uint32_t CMD_DEC_GET_RESULT_PIC_TYPE; /**< Decoded picture type, offset: 0x350 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_DIST_LOW; /**< Low 32bit SSD, offset: 0x350 */ __IO uint32_t CMD_ENC_PIC_PIC_PARAM; /**< HEVC encoder picture level parameter, offset: 0x350 */ __IO uint32_t CMD_ENC_SET_PARAM_ROT_PARAM; /**< Rotation and mirror mode, offset: 0x350 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_4; /**< Display picture address for release, offset: 0x350 */ __IO uint32_t CMD_SET_FB_MV_COL2; /**< COL base of index2, offset: 0x350 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_14; /**< bitstream buffer read pointer, offset: 0x350 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_14; /**< Display picture address for release, offset: 0x350 */ }; union { /* offset: 0x354 */ __IO uint32_t CMD_DEC_GET_RESULT_PIC_POC; /**< Picture Order Count, offset: 0x354 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_DIST_HIGH; /**< High 32bit SSD, offset: 0x354 */ __IO uint32_t CMD_ENC_PIC_LONGTERM_PIC; /**< Longterm picture setting, offset: 0x354 */ __IO uint32_t CMD_ENC_SET_PARAM_NUM_UNITS_IN_TICK; /**< NUM_UNITS_IN_TICK, offset: 0x354 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_5; /**< Display picture address for release, offset: 0x354 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED2; /**< Sub sampled base of index2, offset: 0x354 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_15; /**< bitstream buffer read pointer, offset: 0x354 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_15; /**< Display picture address for release, offset: 0x354 */ }; union { /* offset: 0x358 */ __IO uint32_t CMD_CREATE_INST_AR_TABLE_BASE; /**< AdaptiveRound Table base address, offset: 0x358 */ __IO uint32_t CMD_DEC_GET_RESULT_RECOVERY_POINT; /**< Recovery point, offset: 0x358 */ __IO uint32_t CMD_ENC_GET_RESULT_MAX_LATENCY_PICTURES; /**< The number of latency picture, offset: 0x358 */ __IO uint32_t CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR; /**< Address of prefix SEI nal data, offset: 0x358 */ __IO uint32_t CMD_ENC_SET_PARAM_TIME_SCALE; /**< TIME_SCALE, offset: 0x358 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_6; /**< Display picture address for release, offset: 0x358 */ __IO uint32_t CMD_SET_FB_FBC_Y3; /**< Luma base of index3, offset: 0x358 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_16; /**< bitstream buffer read pointer, offset: 0x358 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_16; /**< Display picture address for release, offset: 0x358 */ }; union { /* offset: 0x35C */ __IO uint32_t CMD_DEC_GET_RESULT_DEBUG_INDEX; /**< FBC and BWB frame buffer index for internal use, offset: 0x35C */ __IO uint32_t CMD_ENC_PIC_PREFIX_SEI_INFO; /**< Information of prefix SEI nal data, offset: 0x35C */ __IO uint32_t CMD_ENC_SET_PARAM_NUM_TICKS_POC_DIFF_ONE; /**< NUM_TICKS_POC_DIFF_ONE, offset: 0x35C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_7; /**< Display picture address for release, offset: 0x35C */ __IO uint32_t CMD_SET_FB_FBC_C3; /**< Cb base of index3, offset: 0x35C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_17; /**< bitstream buffer read pointer, offset: 0x35C */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_17; /**< Display picture address for release, offset: 0x35C */ }; union { /* offset: 0x360 */ __IO uint32_t CMD_DEC_GET_RESULT_DECODED_ADDRESS; /**< Decoded picture address, offset: 0x360 */ __IO uint32_t CMD_ENC_GET_RESULT_HISTO_CNT_0; /**< MV histogram count, offset: 0x360 */ __IO uint32_t CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR; /**< Address of suffix SEI nal data, offset: 0x360 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_8; /**< Display picture address for release, offset: 0x360 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET3; /**< FBC luma offset base of index3, offset: 0x360 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_18; /**< bitstream buffer read pointer, offset: 0x360 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_18; /**< Display picture address for release, offset: 0x360 */ }; union { /* offset: 0x364 */ __IO uint32_t CMD_CREATE_INST_SEC_AXI_BASE_CORE0; /**< Secondary AXI base address for core 0, offset: 0x364 */ __IO uint32_t CMD_DEC_GET_RESULT_DISPLAY_ADDR; /**< Display picture address of DPB, offset: 0x364 */ __IO uint32_t CMD_ENC_GET_RESULT_HISTO_CNT_1; /**< MV histogram count, offset: 0x364 */ __IO uint32_t CMD_ENC_PIC_SUFFIX_SEI_INFO; /**< Information of suffix SEI nal data, offset: 0x364 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_9; /**< Display picture address for release, offset: 0x364 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET3; /**< FBC chroma offset base of index3, offset: 0x364 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_19; /**< bitstream buffer read pointer, offset: 0x364 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_19; /**< Display picture address for release, offset: 0x364 */ }; union { /* offset: 0x368 */ __IO uint32_t CMD_CREATE_INST_SEC_AXI_SIZE_CORE0; /**< Seconary AXI memory size core 0, offset: 0x368 */ __IO uint32_t CMD_ENC_GET_RESULT_HISTO_CNT_2; /**< MV histogram count, offset: 0x368 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_A; /**< Display picture address for release, offset: 0x368 */ __IO uint32_t CMD_SET_FB_MV_COL3; /**< info base of index3, offset: 0x368 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_1A; /**< bitstream buffer read pointer, offset: 0x368 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1A; /**< Display picture address for release, offset: 0x368 */ }; union { /* offset: 0x36C */ __IO uint32_t CMD_CREATE_INST_SEC_AXI_BASE_CORE1; /**< Secondary AXI base address for core 1, offset: 0x36C */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_IDC; /**< Display flag, offset: 0x36C */ __IO uint32_t CMD_ENC_GET_RESULT_HISTO_CNT_3; /**< MV histogram count, offset: 0x36C */ __IO uint32_t CMD_ENC_SET_PARAM_BG_PARAM; /**< Background encoding parameter, offset: 0x36C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_B; /**< Display picture address for release, offset: 0x36C */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED3; /**< Sub sampled base of index3, offset: 0x36C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_1B; /**< bitstream buffer read pointer, offset: 0x36C */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1B; /**< Display picture address for release, offset: 0x36C */ }; union { /* offset: 0x370 */ __IO uint32_t CMD_CREATE_INST_SEC_AXI_SIZE_CORE1; /**< Seconary AXI memory size core 1, offset: 0x370 */ __IO uint32_t CMD_DEC_GET_RESULT_NUM_ERR_CTB; /**< Number of error CTU, offset: 0x370 */ __IO uint32_t CMD_ENC_GET_RESULT_HISTO_CNT_4; /**< MV histogram count, offset: 0x370 */ __IO uint32_t CMD_ENC_SET_PARAM_NON_VCL_PARAM; /**< CMD_ENC_SET_PARAM_SEQ_NON_VCL, offset: 0x370 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_C; /**< Display picture address for release, offset: 0x370 */ __IO uint32_t CMD_SET_FB_FBC_Y4; /**< Luma base of index4, offset: 0x370 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_1C; /**< bitstream buffer read pointer, offset: 0x370 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1C; /**< Display picture address for release, offset: 0x370 */ }; union { /* offset: 0x374 */ __IO uint32_t CMD_ENC_GET_RESULT_NUM_TILE_COL; /**< Number of tile columns, offset: 0x374 */ __IO uint32_t CMD_ENC_PIC_CSC_COEFF_0; /**< Control register of CSC, offset: 0x374 */ __IO uint32_t CMD_ENC_SET_PARAM_VUI_RBSP_ADDR; /**< VUI RBSP buffer address, offset: 0x374 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_D; /**< Display picture address for release, offset: 0x374 */ __IO uint32_t CMD_SET_FB_FBC_C4; /**< Cb base of index4, offset: 0x374 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_1D; /**< bitstream buffer read pointer, offset: 0x374 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1D; /**< Display picture address for release, offset: 0x374 */ }; union { /* offset: 0x378 */ __IO uint32_t CMD_ENC_GET_RESULT_NUM_TILE_ROW; /**< Number of tile rows, offset: 0x378 */ __IO uint32_t CMD_ENC_PIC_CSC_COEFF_1; /**< Control register of CSC, offset: 0x378 */ __IO uint32_t CMD_ENC_SET_PARAM_HRD_RBSP_ADDR; /**< HRD RBSP buffer address, offset: 0x378 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_E; /**< Display picture address for release, offset: 0x378 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET4; /**< FBC luma offset base of index4, offset: 0x378 */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_1E; /**< bitstream buffer read pointer, offset: 0x378 */ __IO uint32_t RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1E; /**< Display picture address for release, offset: 0x378 */ }; union { /* offset: 0x37C */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_WIDTH; /**< Encoded picture width, offset: 0x37C */ __IO uint32_t CMD_ENC_PIC_CSC_COEFF_2; /**< Control register of CSC, offset: 0x37C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_F; /**< Display picture address for release, offset: 0x37C */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET4; /**< FBC chroma offset base of index4, offset: 0x37C */ __IO uint32_t RET_ENC_FLUSH_CMD_RD_PTR_1F; /**< bitstream buffer read pointer, offset: 0x37C */ }; union { /* offset: 0x380 */ __IO uint32_t CMD_ENC_GET_RESULT_PIC_HEIGHT; /**< Encoded picture height, offset: 0x380 */ __IO uint32_t CMD_ENC_PIC_CSC_COEFF_3; /**< Control register of CSC, offset: 0x380 */ __IO uint32_t CMD_ENC_SET_PARAM_QROUND_OFFSET; /**< Quantization rounding offset, offset: 0x380 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_10; /**< Display picture address for release, offset: 0x380 */ __IO uint32_t CMD_SET_FB_MV_COL4; /**< info base of index4, offset: 0x380 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_0; /**< Y component source address used for current ENC_PIC, offset: 0x380 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_0; /**< Bitstream buffer address, offset: 0x380 */ }; union { /* offset: 0x384 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_0; /**< additional Control reg of pvric, offset: 0x384 */ __IO uint32_t CMD_ENC_SET_PARAM_QUANT_PARAM_1; /**< AV1 Qindex offset, offset: 0x384 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_11; /**< Display picture address for release, offset: 0x384 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED4; /**< Sub sampled base of index4, offset: 0x384 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1; /**< Y component source address used for current ENC_PIC, offset: 0x384 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_1; /**< Bitstream buffer address, offset: 0x384 */ }; union { /* offset: 0x388 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_1; /**< additional Control reg of pvric, offset: 0x388 */ __IO uint32_t CMD_ENC_SET_PARAM_QUANT_PARAM_2; /**< Lambda delta QP for customized mode decision, offset: 0x388 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_12; /**< Display picture address for release, offset: 0x388 */ __IO uint32_t CMD_SET_FB_FBC_Y5; /**< Luma base of index5, offset: 0x388 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_2; /**< Y component source address used for current ENC_PIC, offset: 0x388 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_2; /**< Bitstream buffer address, offset: 0x388 */ }; union { /* offset: 0x38C */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_2; /**< additional Control reg of pvric, offset: 0x38C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PARAM; /**< Size of source pictures of custom GOP, offset: 0x38C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_13; /**< Display picture address for release, offset: 0x38C */ __IO uint32_t CMD_SET_FB_FBC_C5; /**< Cb base of index5, offset: 0x38C */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_3; /**< Y component source address used for current ENC_PIC, offset: 0x38C */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_3; /**< Bitstream buffer address, offset: 0x38C */ }; union { /* offset: 0x390 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_3; /**< additional Control reg of pvric, offset: 0x390 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0; /**< Parameters for the 0th picture of custom GOP, offset: 0x390 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_14; /**< Display picture address for release, offset: 0x390 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET5; /**< FBC luma offset base of index5, offset: 0x390 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_4; /**< Y component source address used for current ENC_PIC, offset: 0x390 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_4; /**< Bitstream buffer address, offset: 0x390 */ }; union { /* offset: 0x394 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_4; /**< additional Control reg of pvric, offset: 0x394 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1; /**< Parameters for the 1st picture of custom GOP, offset: 0x394 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_15; /**< Display picture address for release, offset: 0x394 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET5; /**< FBC chroma offset base of index5, offset: 0x394 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_5; /**< Y component source address used for current ENC_PIC, offset: 0x394 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_5; /**< Bitstream buffer address, offset: 0x394 */ }; union { /* offset: 0x398 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_5; /**< additional Control reg of pvric, offset: 0x398 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2; /**< Parameters for the 2nd picture of custom GOP, offset: 0x398 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_16; /**< Display picture address for release, offset: 0x398 */ __IO uint32_t CMD_SET_FB_MV_COL5; /**< info base of index5, offset: 0x398 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_6; /**< Y component source address used for current ENC_PIC, offset: 0x398 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_6; /**< Bitstream buffer address, offset: 0x398 */ }; union { /* offset: 0x39C */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_6; /**< additional Control reg of pvric, offset: 0x39C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3; /**< Parameters for the 3rd picture of custom GOP, offset: 0x39C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_17; /**< Display picture address for release, offset: 0x39C */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED5; /**< Sub sampled base of index5, offset: 0x39C */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_7; /**< Y component source address used for current ENC_PIC, offset: 0x39C */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_7; /**< Bitstream buffer address, offset: 0x39C */ }; union { /* offset: 0x3A0 */ __IO uint32_t CMD_DEC_GET_RESULT_CORE_IDC; /**< Used core idc, offset: 0x3A0 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_7; /**< additional Control reg of pvric, offset: 0x3A0 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4; /**< Parameters for the 4th picture of custom GOP, offset: 0x3A0 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_18; /**< Display picture address for release, offset: 0x3A0 */ __IO uint32_t CMD_SET_FB_FBC_Y6; /**< Luma base of index6, offset: 0x3A0 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_8; /**< Y component source address used for current ENC_PIC, offset: 0x3A0 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_8; /**< Bitstream buffer address, offset: 0x3A0 */ }; union { /* offset: 0x3A4 */ __IO uint32_t CMD_DEC_GET_RESULT_PIC_PARAM; /**< Bitstream sequence/pic parameter information, offset: 0x3A4 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_8; /**< additional Control reg of pvric, offset: 0x3A4 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5; /**< Parameters for the 5th picture of custom GOP, offset: 0x3A4 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_19; /**< Display picture address for release, offset: 0x3A4 */ __IO uint32_t CMD_SET_FB_FBC_C6; /**< Cb base of index6, offset: 0x3A4 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_9; /**< Y component source address used for current ENC_PIC, offset: 0x3A4 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_9; /**< Bitstream buffer address, offset: 0x3A4 */ }; union { /* offset: 0x3A8 */ __IO uint32_t CMD_DEC_GET_RESULT_DISPLAY_FLAG; /**< Validation for display address, offset: 0x3A8 */ __IO uint32_t CMD_ENC_GET_RESULT_CORE_IDC; /**< Used core idc, offset: 0x3A8 */ __IO uint32_t CMD_ENC_PIC_PVRIC_AD_CTRL_9; /**< additional Control reg of pvric, offset: 0x3A8 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6; /**< Parameters for the 6th picture of custom GOP, offset: 0x3A8 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1A; /**< Display picture address for release, offset: 0x3A8 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET6; /**< FBC luma offset base of index6, offset: 0x3A8 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_A; /**< Y component source address used for current ENC_PIC, offset: 0x3A8 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_A; /**< Bitstream buffer address, offset: 0x3A8 */ }; union { /* offset: 0x3AC */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_NUM; /**< Number of valid release address, offset: 0x3AC */ __IO uint32_t CMD_ENC_GET_RESULT_HOST_WARN_INFO; /**< Warning Info, offset: 0x3AC */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7; /**< Parameters for the 7th picture of custom GOP, offset: 0x3AC */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1B; /**< Display picture address for release, offset: 0x3AC */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET6; /**< FBC chroma offset base of index6, offset: 0x3AC */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_B; /**< Y component source address used for current ENC_PIC, offset: 0x3AC */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_B; /**< Bitstream buffer address, offset: 0x3AC */ }; union { /* offset: 0x3B0 */ __IO uint32_t CMD_ENC_GET_RESULT_HOST_ERR_INFO; /**< Error Info, offset: 0x3B0 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1C; /**< Display picture address for release, offset: 0x3B0 */ __IO uint32_t CMD_SET_FB_MV_COL6; /**< info base of index6, offset: 0x3B0 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_C; /**< Y component source address used for current ENC_PIC, offset: 0x3B0 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_C; /**< Bitstream buffer address, offset: 0x3B0 */ }; union { /* offset: 0x3B4 */ __IO uint32_t CMD_ENC_GET_RESULT_HOST_SUCCESS; /**< Host command Reture Value, offset: 0x3B4 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1D; /**< Display picture address for release, offset: 0x3B4 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED6; /**< Sub sampled base of index6, offset: 0x3B4 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_D; /**< Y component source address used for current ENC_PIC, offset: 0x3B4 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_D; /**< Bitstream buffer address, offset: 0x3B4 */ }; union { /* offset: 0x3B8 */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_LOWER; /**< mv x sum lower, offset: 0x3B8 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1E; /**< Display picture address for release, offset: 0x3B8 */ __IO uint32_t CMD_SET_FB_FBC_Y7; /**< Luma base of index7, offset: 0x3B8 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_E; /**< Y component source address used for current ENC_PIC, offset: 0x3B8 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_E; /**< Bitstream buffer address, offset: 0x3B8 */ }; union { /* offset: 0x3BC */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_HIGHER; /**< mv x sum higher, offset: 0x3BC */ __IO uint32_t CMD_SET_FB_FBC_C7; /**< Cb base of index7, offset: 0x3BC */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_F; /**< Y component source address used for current ENC_PIC, offset: 0x3BC */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_F; /**< Bitstream buffer address, offset: 0x3BC */ }; union { /* offset: 0x3C0 */ __IO uint32_t CMD_DEC_GET_RESULT_DETECTED_STREAM_END; /**< cmd_dec_get_result_detected_stream_end, offset: 0x3C0 */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_LOWER; /**< mv y sum lower, offset: 0x3C0 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_0; /**< Linear buffer address to be displayed, offset: 0x3C0 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET7; /**< FBC luma offset base of index7, offset: 0x3C0 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_10; /**< Y component source address used for current ENC_PIC, offset: 0x3C0 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_10; /**< Bitstream buffer address, offset: 0x3C0 */ }; union { /* offset: 0x3C4 */ __IO uint32_t CMD_DEC_GET_RESULT_DECODED_FLAG; /**< Validation for decoded address, offset: 0x3C4 */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_HIGHER; /**< mv y sum higher, offset: 0x3C4 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1; /**< Linear buffer address to be displayed, offset: 0x3C4 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET7; /**< FBC chroma offset base of index7, offset: 0x3C4 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_11; /**< Y component source address used for current ENC_PIC, offset: 0x3C4 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_11; /**< Bitstream buffer address, offset: 0x3C4 */ }; union { /* offset: 0x3C8 */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_LOWER; /**< mv x sum lower, offset: 0x3C8 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_2; /**< Linear buffer address to be displayed, offset: 0x3C8 */ __IO uint32_t CMD_SET_FB_MV_COL7; /**< info base of index7, offset: 0x3C8 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_12; /**< Y component source address used for current ENC_PIC, offset: 0x3C8 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_12; /**< Bitstream buffer address, offset: 0x3C8 */ }; union { /* offset: 0x3CC */ __IO uint32_t CMD_DEC_GET_RESULT_WARN_INFO; /**< Warning information, offset: 0x3CC */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_HIGHER; /**< mv x sum higher, offset: 0x3CC */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_3; /**< Linear buffer address to be displayed, offset: 0x3CC */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED7; /**< Sub sampled base of index7, offset: 0x3CC */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_13; /**< Y component source address used for current ENC_PIC, offset: 0x3CC */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_13; /**< Bitstream buffer address, offset: 0x3CC */ }; union { /* offset: 0x3D0 */ __IO uint32_t CMD_DEC_GET_RESULT_ERR_INFO; /**< Error information, offset: 0x3D0 */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_LOWER; /**< mv y sum lower, offset: 0x3D0 */ __IO uint32_t CMD_ENC_SET_PARAM_TILE_PARAM; /**< Tile parameters, offset: 0x3D0 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_4; /**< Linear buffer address to be displayed, offset: 0x3D0 */ __IO uint32_t CMD_SET_FB_FBC_Y8; /**< Luma base of index8, offset: 0x3D0 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_14; /**< Y component source address used for current ENC_PIC, offset: 0x3D0 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_14; /**< Bitstream buffer address, offset: 0x3D0 */ }; union { /* offset: 0x3D4 */ __IO uint32_t CMD_DEC_GET_RESULT_DECODING_SUCCESS; /**< Query result, offset: 0x3D4 */ __IO uint32_t CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_HIGHER; /**< mv y sum higher, offset: 0x3D4 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0; /**< CUSTOM_LAMBDA_DATA, offset: 0x3D4 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_5; /**< Linear buffer address to be displayed, offset: 0x3D4 */ __IO uint32_t CMD_SET_FB_FBC_C8; /**< Cb base of index8, offset: 0x3D4 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_15; /**< Y component source address used for current ENC_PIC, offset: 0x3D4 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_15; /**< Bitstream buffer address, offset: 0x3D4 */ }; union { /* offset: 0x3D8 */ __IO uint32_t CMD_DEC_GET_RESULT_TIMESTAMP; /**< cmd_dec_get_result_timestamp, offset: 0x3D8 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1; /**< CUSTOM_LAMBDA_DATA, offset: 0x3D8 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_6; /**< Linear buffer address to be displayed, offset: 0x3D8 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET8; /**< FBC luma offset base of index8, offset: 0x3D8 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_16; /**< Y component source address used for current ENC_PIC, offset: 0x3D8 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_16; /**< Bitstream buffer address, offset: 0x3D8 */ }; union { /* offset: 0x3DC */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2; /**< CUSTOM_LAMBDA_DATA, offset: 0x3DC */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_7; /**< Linear buffer address to be displayed, offset: 0x3DC */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET8; /**< FBC chroma offset base of index8, offset: 0x3DC */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_17; /**< Y component source address used for current ENC_PIC, offset: 0x3DC */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_17; /**< Bitstream buffer address, offset: 0x3DC */ }; union { /* offset: 0x3E0 */ __IO uint32_t CMD_DEC_GET_RESULT_LAST_FRAME_FLAG; /**< ret_last_frame_flag, offset: 0x3E0 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3; /**< CUSTOM_LAMBDA_DATA, offset: 0x3E0 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_8; /**< Linear buffer address to be displayed, offset: 0x3E0 */ __IO uint32_t CMD_SET_FB_MV_COL8; /**< info base of index8, offset: 0x3E0 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_18; /**< Y component source address used for current ENC_PIC, offset: 0x3E0 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_18; /**< Bitstream buffer address, offset: 0x3E0 */ }; union { /* offset: 0x3E4 */ __IO uint32_t CMD_DEC_GET_RESULT_NUM_REQUIRED_COL_BUF; /**< Required Number of Minimum col buf, offset: 0x3E4 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4; /**< CUSTOM_LAMBDA_DATA, offset: 0x3E4 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_9; /**< Linear buffer address to be displayed, offset: 0x3E4 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED8; /**< Sub sampled base of index8, offset: 0x3E4 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_19; /**< Y component source address used for current ENC_PIC, offset: 0x3E4 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_19; /**< Bitstream buffer address, offset: 0x3E4 */ }; union { /* offset: 0x3E8 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_0; /**< Display picture address for release, offset: 0x3E8 */ __IO uint32_t CMD_ENC_GET_RESULT_SRC_ADDR_Y; /**< Y component source address used for current ENC_PIC, offset: 0x3E8 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5; /**< CUSTOM_LAMBDA_DATA, offset: 0x3E8 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_A; /**< Linear buffer address to be displayed, offset: 0x3E8 */ __IO uint32_t CMD_SET_FB_FBC_Y9; /**< Luma base of index9, offset: 0x3E8 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1A; /**< Y component source address used for current ENC_PIC, offset: 0x3E8 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_1A; /**< Bitstream buffer address, offset: 0x3E8 */ }; union { /* offset: 0x3EC */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1; /**< Display picture address for release, offset: 0x3EC */ __IO uint32_t CMD_ENC_GET_RESULT_CUSTOM_MAP_OPTION_ADDR; /**< Custom map address used for current ENC_PIC, offset: 0x3EC */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6; /**< CUSTOM_LAMBDA_DATA, offset: 0x3EC */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_B; /**< Linear buffer address to be displayed, offset: 0x3EC */ __IO uint32_t CMD_SET_FB_FBC_C9; /**< Cb base of index9, offset: 0x3EC */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1B; /**< Y component source address used for current ENC_PIC, offset: 0x3EC */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_1B; /**< Bitstream buffer address, offset: 0x3EC */ }; union { /* offset: 0x3F0 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_2; /**< Display picture address for release, offset: 0x3F0 */ __IO uint32_t CMD_ENC_GET_RESULT_PREFIX_SEI_NAL_ADDR; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x3F0 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7; /**< CUSTOM_LAMBDA_DATA, offset: 0x3F0 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_C; /**< Linear buffer address to be displayed, offset: 0x3F0 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET9; /**< FBC luma offset base of index9, offset: 0x3F0 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1C; /**< Y component source address used for current ENC_PIC, offset: 0x3F0 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_1C; /**< Bitstream buffer address, offset: 0x3F0 */ }; union { /* offset: 0x3F4 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_3; /**< Display picture address for release, offset: 0x3F4 */ __IO uint32_t CMD_ENC_GET_RESULT_SUFFIX_SEI_NAL_ADDR; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x3F4 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8; /**< CUSTOM_LAMBDA_DATA, offset: 0x3F4 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_D; /**< Linear buffer address to be displayed, offset: 0x3F4 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET9; /**< FBC chroma offset base of index9, offset: 0x3F4 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1D; /**< Y component source address used for current ENC_PIC, offset: 0x3F4 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_1D; /**< Bitstream buffer address, offset: 0x3F4 */ }; union { /* offset: 0x3F8 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_4; /**< Display picture address for release, offset: 0x3F8 */ __IO uint32_t CMD_ENC_GET_RESULT_SRC_DEBUG_0; /**< cmd_enc_get_result_src_debug_0, offset: 0x3F8 */ __IO uint32_t CMD_ENC_PIC_TIMESTAMP; /**< cmd_enc_pic_timestamp, offset: 0x3F8 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9; /**< CUSTOM_LAMBDA_DATA, offset: 0x3F8 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_E; /**< Linear buffer address to be displayed, offset: 0x3F8 */ __IO uint32_t CMD_SET_FB_MV_COL9; /**< info base of index9, offset: 0x3F8 */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1E; /**< Y component source address used for current ENC_PIC, offset: 0x3F8 */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_1E; /**< Bitstream buffer address, offset: 0x3F8 */ }; union { /* offset: 0x3FC */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_5; /**< Display picture address for release, offset: 0x3FC */ __IO uint32_t CMD_ENC_GET_RESULT_SRC_DEBUG_1; /**< cmd_enc_get_result_src_debug_1, offset: 0x3FC */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10; /**< CUSTOM_LAMBDA_DATA, offset: 0x3FC */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_F; /**< Linear buffer address to be displayed, offset: 0x3FC */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED9; /**< Sub sampled base of index9, offset: 0x3FC */ __IO uint32_t RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1F; /**< Y component source address used for current ENC_PIC, offset: 0x3FC */ __IO uint32_t RET_FLUSH_CMD_INFO_BS_RD_ADDR_1F; /**< Bitstream buffer address, offset: 0x3FC */ }; union { /* offset: 0x400 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_6; /**< Display picture address for release, offset: 0x400 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11; /**< CUSTOM_LAMBDA_DATA, offset: 0x400 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_10; /**< Linear buffer address to be displayed, offset: 0x400 */ __IO uint32_t CMD_SET_FB_FBC_Y10; /**< Luma base of index10, offset: 0x400 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_0; /**< Custom map address used for current ENC_PIC, offset: 0x400 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_0; /**< User data buffer address, offset: 0x400 */ }; union { /* offset: 0x404 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_7; /**< Display picture address for release, offset: 0x404 */ __IO uint32_t CMD_ENC_GET_RESULT_NUM_REQUIRED_COL_FB; /**< Minimum number of col frame buffer required for encoding, offset: 0x404 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12; /**< CUSTOM_LAMBDA_DATA, offset: 0x404 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_11; /**< Linear buffer address to be displayed, offset: 0x404 */ __IO uint32_t CMD_SET_FB_FBC_C10; /**< Cb base of index10, offset: 0x404 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1; /**< Custom map address used for current ENC_PIC, offset: 0x404 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_1; /**< User data buffer address, offset: 0x404 */ }; union { /* offset: 0x408 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_8; /**< Display picture address for release, offset: 0x408 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13; /**< CUSTOM_LAMBDA_DATA, offset: 0x408 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_12; /**< Linear buffer address to be displayed, offset: 0x408 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET10; /**< FBC luma offset base of index10, offset: 0x408 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_2; /**< Custom map address used for current ENC_PIC, offset: 0x408 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_2; /**< User data buffer address, offset: 0x408 */ }; union { /* offset: 0x40C */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_9; /**< Display picture address for release, offset: 0x40C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14; /**< CUSTOM_LAMBDA_DATA, offset: 0x40C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_13; /**< Linear buffer address to be displayed, offset: 0x40C */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET10; /**< FBC chroma offset base of index10, offset: 0x40C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_3; /**< Custom map address used for current ENC_PIC, offset: 0x40C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_3; /**< User data buffer address, offset: 0x40C */ }; union { /* offset: 0x410 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_A; /**< Display picture address for release, offset: 0x410 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15; /**< CUSTOM_LAMBDA_DATA, offset: 0x410 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_14; /**< Linear buffer address to be displayed, offset: 0x410 */ __IO uint32_t CMD_SET_FB_MV_COL10; /**< info base of index10, offset: 0x410 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_4; /**< Custom map address used for current ENC_PIC, offset: 0x410 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_4; /**< User data buffer address, offset: 0x410 */ }; union { /* offset: 0x414 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_B; /**< Display picture address for release, offset: 0x414 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16; /**< CUSTOM_LAMBDA_DATA, offset: 0x414 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_15; /**< Linear buffer address to be displayed, offset: 0x414 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED10; /**< Sub sampled base of index10, offset: 0x414 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_5; /**< Custom map address used for current ENC_PIC, offset: 0x414 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_5; /**< User data buffer address, offset: 0x414 */ }; union { /* offset: 0x418 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_C; /**< Display picture address for release, offset: 0x418 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17; /**< CUSTOM_LAMBDA_DATA, offset: 0x418 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_16; /**< Linear buffer address to be displayed, offset: 0x418 */ __IO uint32_t CMD_SET_FB_FBC_Y11; /**< Luma base of index11, offset: 0x418 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_6; /**< Custom map address used for current ENC_PIC, offset: 0x418 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_6; /**< User data buffer address, offset: 0x418 */ }; union { /* offset: 0x41C */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_D; /**< Display picture address for release, offset: 0x41C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18; /**< CUSTOM_LAMBDA_DATA, offset: 0x41C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_17; /**< Linear buffer address to be displayed, offset: 0x41C */ __IO uint32_t CMD_SET_FB_FBC_C11; /**< Cb base of index11, offset: 0x41C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_7; /**< Custom map address used for current ENC_PIC, offset: 0x41C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_7; /**< User data buffer address, offset: 0x41C */ }; union { /* offset: 0x420 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_E; /**< Display picture address for release, offset: 0x420 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19; /**< CUSTOM_LAMBDA_DATA, offset: 0x420 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_18; /**< Linear buffer address to be displayed, offset: 0x420 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET11; /**< FBC luma offset base of index11, offset: 0x420 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_8; /**< Custom map address used for current ENC_PIC, offset: 0x420 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_8; /**< User data buffer address, offset: 0x420 */ }; union { /* offset: 0x424 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_F; /**< Display picture address for release, offset: 0x424 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20; /**< CUSTOM_LAMBDA_DATA, offset: 0x424 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_19; /**< Linear buffer address to be displayed, offset: 0x424 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET11; /**< FBC chroma offset base of index11, offset: 0x424 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_9; /**< Custom map address used for current ENC_PIC, offset: 0x424 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_9; /**< User data buffer address, offset: 0x424 */ }; union { /* offset: 0x428 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_10; /**< Display picture address for release, offset: 0x428 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21; /**< CUSTOM_LAMBDA_DATA, offset: 0x428 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1A; /**< Linear buffer address to be displayed, offset: 0x428 */ __IO uint32_t CMD_SET_FB_MV_COL11; /**< info base of index11, offset: 0x428 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_A; /**< Custom map address used for current ENC_PIC, offset: 0x428 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_A; /**< User data buffer address, offset: 0x428 */ }; union { /* offset: 0x42C */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_11; /**< Display picture address for release, offset: 0x42C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22; /**< CUSTOM_LAMBDA_DATA, offset: 0x42C */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1B; /**< Linear buffer address to be displayed, offset: 0x42C */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED11; /**< Sub sampled base of index11, offset: 0x42C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_B; /**< Custom map address used for current ENC_PIC, offset: 0x42C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_B; /**< User data buffer address, offset: 0x42C */ }; union { /* offset: 0x430 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_12; /**< Display picture address for release, offset: 0x430 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23; /**< CUSTOM_LAMBDA_DATA, offset: 0x430 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1C; /**< Linear buffer address to be displayed, offset: 0x430 */ __IO uint32_t CMD_SET_FB_FBC_Y12; /**< Luma base of index12, offset: 0x430 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_C; /**< Custom map address used for current ENC_PIC, offset: 0x430 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_C; /**< User data buffer address, offset: 0x430 */ }; union { /* offset: 0x434 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_13; /**< Display picture address for release, offset: 0x434 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24; /**< CUSTOM_LAMBDA_DATA, offset: 0x434 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1D; /**< Linear buffer address to be displayed, offset: 0x434 */ __IO uint32_t CMD_SET_FB_FBC_C12; /**< Cb base of index12, offset: 0x434 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_D; /**< Custom map address used for current ENC_PIC, offset: 0x434 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_D; /**< User data buffer address, offset: 0x434 */ }; union { /* offset: 0x438 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_14; /**< Display picture address for release, offset: 0x438 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25; /**< CUSTOM_LAMBDA_DATA, offset: 0x438 */ __IO uint32_t CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1E; /**< Linear buffer address to be displayed, offset: 0x438 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET12; /**< FBC luma offset base of index12, offset: 0x438 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_E; /**< Custom map address used for current ENC_PIC, offset: 0x438 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_E; /**< User data buffer address, offset: 0x438 */ }; union { /* offset: 0x43C */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_15; /**< Display picture address for release, offset: 0x43C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26; /**< CUSTOM_LAMBDA_DATA, offset: 0x43C */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET12; /**< FBC chroma offset base of index12, offset: 0x43C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_F; /**< Custom map address used for current ENC_PIC, offset: 0x43C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_F; /**< User data buffer address, offset: 0x43C */ }; union { /* offset: 0x440 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_16; /**< Display picture address for release, offset: 0x440 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27; /**< CUSTOM_LAMBDA_DATA, offset: 0x440 */ __IO uint32_t CMD_SET_FB_MV_COL12; /**< info base of index12, offset: 0x440 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_10; /**< Custom map address used for current ENC_PIC, offset: 0x440 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_10; /**< User data buffer address, offset: 0x440 */ }; union { /* offset: 0x444 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_17; /**< Display picture address for release, offset: 0x444 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28; /**< CUSTOM_LAMBDA_DATA, offset: 0x444 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED12; /**< Sub sampled base of index12, offset: 0x444 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_11; /**< Custom map address used for current ENC_PIC, offset: 0x444 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_11; /**< User data buffer address, offset: 0x444 */ }; union { /* offset: 0x448 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_18; /**< Display picture address for release, offset: 0x448 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29; /**< CUSTOM_LAMBDA_DATA, offset: 0x448 */ __IO uint32_t CMD_SET_FB_FBC_Y13; /**< Luma base of index13, offset: 0x448 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_12; /**< Custom map address used for current ENC_PIC, offset: 0x448 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_12; /**< User data buffer address, offset: 0x448 */ }; union { /* offset: 0x44C */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_19; /**< Display picture address for release, offset: 0x44C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30; /**< CUSTOM_LAMBDA_DATA, offset: 0x44C */ __IO uint32_t CMD_SET_FB_FBC_C13; /**< Cb base of index13, offset: 0x44C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_13; /**< Custom map address used for current ENC_PIC, offset: 0x44C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_13; /**< User data buffer address, offset: 0x44C */ }; union { /* offset: 0x450 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1A; /**< Display picture address for release, offset: 0x450 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31; /**< CUSTOM_LAMBDA_DATA, offset: 0x450 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET13; /**< FBC luma offset base of index13, offset: 0x450 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_14; /**< Custom map address used for current ENC_PIC, offset: 0x450 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_14; /**< User data buffer address, offset: 0x450 */ }; union { /* offset: 0x454 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1B; /**< Display picture address for release, offset: 0x454 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32; /**< CUSTOM_LAMBDA_DATA, offset: 0x454 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET13; /**< FBC chroma offset base of index13, offset: 0x454 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_15; /**< Custom map address used for current ENC_PIC, offset: 0x454 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_15; /**< User data buffer address, offset: 0x454 */ }; union { /* offset: 0x458 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1C; /**< Display picture address for release, offset: 0x458 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33; /**< CUSTOM_LAMBDA_DATA, offset: 0x458 */ __IO uint32_t CMD_SET_FB_MV_COL13; /**< info base of index13, offset: 0x458 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_16; /**< Custom map address used for current ENC_PIC, offset: 0x458 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_16; /**< User data buffer address, offset: 0x458 */ }; union { /* offset: 0x45C */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1D; /**< Display picture address for release, offset: 0x45C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34; /**< CUSTOM_LAMBDA_DATA, offset: 0x45C */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED13; /**< Sub sampled base of index13, offset: 0x45C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_17; /**< Custom map address used for current ENC_PIC, offset: 0x45C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_17; /**< User data buffer address, offset: 0x45C */ }; union { /* offset: 0x460 */ __IO uint32_t CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1E; /**< Display picture address for release, offset: 0x460 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35; /**< CUSTOM_LAMBDA_DATA, offset: 0x460 */ __IO uint32_t CMD_SET_FB_FBC_Y14; /**< Luma base of index14, offset: 0x460 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_18; /**< Custom map address used for current ENC_PIC, offset: 0x460 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_18; /**< User data buffer address, offset: 0x460 */ }; union { /* offset: 0x464 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36; /**< CUSTOM_LAMBDA_DATA, offset: 0x464 */ __IO uint32_t CMD_SET_FB_FBC_C14; /**< Cb base of index14, offset: 0x464 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_19; /**< Custom map address used for current ENC_PIC, offset: 0x464 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_19; /**< User data buffer address, offset: 0x464 */ }; union { /* offset: 0x468 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37; /**< CUSTOM_LAMBDA_DATA, offset: 0x468 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET14; /**< FBC luma offset base of index14, offset: 0x468 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1A; /**< Custom map address used for current ENC_PIC, offset: 0x468 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_1A; /**< User data buffer address, offset: 0x468 */ }; union { /* offset: 0x46C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38; /**< CUSTOM_LAMBDA_DATA, offset: 0x46C */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET14; /**< FBC chroma offset base of index14, offset: 0x46C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1B; /**< Custom map address used for current ENC_PIC, offset: 0x46C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_1B; /**< User data buffer address, offset: 0x46C */ }; union { /* offset: 0x470 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39; /**< CUSTOM_LAMBDA_DATA, offset: 0x470 */ __IO uint32_t CMD_SET_FB_MV_COL14; /**< info base of index14, offset: 0x470 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1C; /**< Custom map address used for current ENC_PIC, offset: 0x470 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_1C; /**< User data buffer address, offset: 0x470 */ }; union { /* offset: 0x474 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40; /**< CUSTOM_LAMBDA_DATA, offset: 0x474 */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED14; /**< Sub sampled base of index14, offset: 0x474 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1D; /**< Custom map address used for current ENC_PIC, offset: 0x474 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_1D; /**< User data buffer address, offset: 0x474 */ }; union { /* offset: 0x478 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41; /**< CUSTOM_LAMBDA_DATA, offset: 0x478 */ __IO uint32_t CMD_SET_FB_FBC_Y15; /**< Luma base of index15, offset: 0x478 */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1E; /**< Custom map address used for current ENC_PIC, offset: 0x478 */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_1E; /**< User data buffer address, offset: 0x478 */ }; union { /* offset: 0x47C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42; /**< CUSTOM_LAMBDA_DATA, offset: 0x47C */ __IO uint32_t CMD_SET_FB_FBC_C15; /**< Cb base of index15, offset: 0x47C */ __IO uint32_t RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1F; /**< Custom map address used for current ENC_PIC, offset: 0x47C */ __IO uint32_t RET_FLUSH_CMD_INFO_USER_DATA_1F; /**< User data buffer address, offset: 0x47C */ }; union { /* offset: 0x480 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43; /**< CUSTOM_LAMBDA_DATA, offset: 0x480 */ __IO uint32_t CMD_SET_FB_FBC_Y_OFFSET15; /**< FBC luma offset base of index15, offset: 0x480 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_0; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x480 */ }; union { /* offset: 0x484 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44; /**< CUSTOM_LAMBDA_DATA, offset: 0x484 */ __IO uint32_t CMD_SET_FB_FBC_C_OFFSET15; /**< FBC chroma offset base of index15, offset: 0x484 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x484 */ }; union { /* offset: 0x488 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45; /**< CUSTOM_LAMBDA_DATA, offset: 0x488 */ __IO uint32_t CMD_SET_FB_MV_COL15; /**< info base of index15, offset: 0x488 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_2; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x488 */ }; union { /* offset: 0x48C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46; /**< CUSTOM_LAMBDA_DATA, offset: 0x48C */ __IO uint32_t CMD_SET_FB_SUB_SAMPLED15; /**< Sub sampled base of index15, offset: 0x48C */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_3; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x48C */ }; union { /* offset: 0x490 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47; /**< CUSTOM_LAMBDA_DATA, offset: 0x490 */ __IO uint32_t CMD_SET_FB_ADDR_REPORT_BUFFER; /**< Report buffer start address, offset: 0x490 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_4; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x490 */ }; union { /* offset: 0x494 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48; /**< CUSTOM_LAMBDA_DATA, offset: 0x494 */ __IO uint32_t CMD_SET_FB_DEFAULT_CDF; /**< base of default cdf buffer, offset: 0x494 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_5; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x494 */ }; union { /* offset: 0x498 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49; /**< CUSTOM_LAMBDA_DATA, offset: 0x498 */ __IO uint32_t CMD_SET_FB_SEGMAP; /**< base of seg map buffer, offset: 0x498 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_6; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x498 */ }; union { /* offset: 0x49C */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50; /**< CUSTOM_LAMBDA_DATA, offset: 0x49C */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_7; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x49C */ }; union { /* offset: 0x4A0 */ __IO uint32_t CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51; /**< CUSTOM_LAMBDA_DATA, offset: 0x4A0 */ __IO uint32_t CMD_SET_FB_UPDATE_INDICES; /**< DPB index to be updated, offset: 0x4A0 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_8; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4A0 */ }; union { /* offset: 0x4A4 */ __IO uint32_t CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP; /**< TEMPORAL_LAYER_0_QP, offset: 0x4A4 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_9; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4A4 */ }; union { /* offset: 0x4A8 */ __IO uint32_t CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP; /**< TEMPORAL_LAYER_1_QP, offset: 0x4A8 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_A; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4A8 */ }; union { /* offset: 0x4AC */ __IO uint32_t CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP; /**< TEMPORAL_LAYER_2_QP, offset: 0x4AC */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_B; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4AC */ }; union { /* offset: 0x4B0 */ __IO uint32_t CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP; /**< TEMPORAL_LAYER_3_QP, offset: 0x4B0 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_C; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4B0 */ }; union { /* offset: 0x4B4 */ __IO uint32_t CMD_ENC_SET_PARAM_SCL_SRC_SIZE; /**< SCALER SRC SIZE, offset: 0x4B4 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_D; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4B4 */ }; union { /* offset: 0x4B8 */ __IO uint32_t CMD_ENC_SET_PARAM_SCL_PARAM; /**< SCALER PARAMETER, offset: 0x4B8 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_E; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4B8 */ }; union { /* offset: 0x4BC */ __IO uint32_t CMD_ENC_SET_PARAM_Y2Y_PARAM; /**< Y2Y PARAMETER, offset: 0x4BC */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_F; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4BC */ }; __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_10; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4C0 */ union { /* offset: 0x4C4 */ __IO uint32_t CMD_ENC_SET_PARAM_SFS_PARAM; /**< CONTROL REGISTER OF SUB FRAME SYNC, offset: 0x4C4 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_11; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4C4 */ }; union { /* offset: 0x4C8 */ __IO uint32_t CMD_ENC_SET_PARAM_CROP_ENABLE; /**< PRE PROCESSING CROP DATA, offset: 0x4C8 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_12; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4C8 */ }; union { /* offset: 0x4CC */ __IO uint32_t CMD_ENC_SET_PARAM_CROP_POS; /**< CONTROL REGISTER OF CROP START, offset: 0x4CC */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_13; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4CC */ }; union { /* offset: 0x4D0 */ __IO uint32_t CMD_ENC_SET_PARAM_CROP_SRC_SIZE; /**< CROP_SRC SIZE, offset: 0x4D0 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_14; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4D0 */ }; __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_15; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4D4 */ union { /* offset: 0x4D8 */ __IO uint32_t CMD_ENC_SET_PARAM_Y2Y_DATA_0; /**< Y2Y DATA, offset: 0x4D8 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_16; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4D8 */ }; union { /* offset: 0x4DC */ __IO uint32_t CMD_ENC_SET_PARAM_Y2Y_DATA_1; /**< Y2Y DATA, offset: 0x4DC */ __IO uint32_t CMD_SET_FB_MV_COL_PRE_ENT; /**< Dual col buffer address, offset: 0x4DC */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_17; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4DC */ }; union { /* offset: 0x4E0 */ __IO uint32_t CMD_ENC_SET_PARAM_Y2Y_DATA_2; /**< Y2Y DATA, offset: 0x4E0 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_18; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4E0 */ }; __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_19; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4E4 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1A; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4E8 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1B; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4EC */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1C; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4F0 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1D; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4F4 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1E; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4F8 */ __IO uint32_t RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1F; /**< Address of prefix SEI nal data for current ENC_PIC, offset: 0x4FC */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_0; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x500 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x504 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_2; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x508 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_3; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x50C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_4; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x510 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_5; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x514 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_6; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x518 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_7; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x51C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_8; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x520 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_9; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x524 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_A; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x528 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_B; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x52C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_C; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x530 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_D; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x534 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_E; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x538 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_F; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x53C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_10; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x540 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_11; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x544 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_12; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x548 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_13; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x54C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_14; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x550 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_15; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x554 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_16; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x558 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_17; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x55C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_18; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x560 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_19; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x564 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1A; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x568 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1B; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x56C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1C; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x570 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1D; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x574 */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1E; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x578 */ union { /* offset: 0x57C */ __IO uint32_t RET_DEC_COLOR_CONFIG; /**< Color config, offset: 0x57C */ __IO uint32_t RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1F; /**< Address of suffix SEI nal data for current ENC_PIC, offset: 0x57C */ }; uint8_t RESERVED_6[128]; __O uint32_t CMD_CONTROL_REG_VPU_PDBG_CTRL; /**< V-CPU Debugger Control, offset: 0x600 */ __O uint32_t CMD_CONTROL_REG_VPU_PDBG_IDX_REG; /**< V-CPU Debugger Index, offset: 0x604 */ __O uint32_t CMD_CONTROL_REG_VPU_PDBG_WDATA_REG; /**< V-CPU Debugger Write Data, offset: 0x608 */ __I uint32_t CMD_CONTROL_REG_VPU_PDBG_RDATA_REG; /**< V-CPU Debugger Read Data, offset: 0x60C */ __IO uint32_t CMD_CONTROL_REG_VPU_PDBG_STEP_MASK; /**< V-CPU Debugger Step Mask, offset: 0x610 */ uint8_t RESERVED_7[14916]; __O uint32_t CMD_GLOBAL_REG_VCPU_RESTART; /**< V-CPU Restart Request, offset: 0x4058 */ uint8_t RESERVED_8[4]; __O uint32_t CMD_GLOBAL_REG_OPTION; /**< Remap Control, offset: 0x4060 */ __O uint32_t CMD_GLOBAL_REG_VPU_REMAP_VADDR; /**< Remap Virutal Address, offset: 0x4064 */ __O uint32_t CMD_GLOBAL_REG_VPU_REMAP_PADDR; /**< Remap Physical Address, offset: 0x4068 */ __O uint32_t CMD_GLOBAL_REG_VPU_REMAP_CORE_START_GLOBAL; /**< VPU Start Request, offset: 0x406C */ uint8_t RESERVED_9[148]; __O uint32_t CMD_GLOBAL_REG_COMMAND_GLOBAL; /**< Command, offset: 0x4104 */ } VPU_Type; /* ---------------------------------------------------------------------------- -- VPU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_Register_Masks VPU Register Masks * @{ */ /*! @name CMD_CONTROL_REG_HOST_GLOBAL_WR - HOST_GLOBAL_WR */ /*! @{ */ #define VPU_CMD_CONTROL_REG_HOST_GLOBAL_WR_HOST_GLOBAL_WR_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_HOST_GLOBAL_WR_HOST_GLOBAL_WR_SHIFT (0U) #define VPU_CMD_CONTROL_REG_HOST_GLOBAL_WR_HOST_GLOBAL_WR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_HOST_GLOBAL_WR_HOST_GLOBAL_WR_SHIFT)) & VPU_CMD_CONTROL_REG_HOST_GLOBAL_WR_HOST_GLOBAL_WR_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_OPTION - Current PC */ /*! @{ */ #define VPU_CMD_CONTROL_REG_OPTION_CUR_PC_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_OPTION_CUR_PC_SHIFT (0U) #define VPU_CMD_CONTROL_REG_OPTION_CUR_PC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_OPTION_CUR_PC_SHIFT)) & VPU_CMD_CONTROL_REG_OPTION_CUR_PC_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_SUCCESS - Current LR */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_SUCCESS_CUR_LR_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_SUCCESS_CUR_LR_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_SUCCESS_CUR_LR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_SUCCESS_CUR_LR_SHIFT)) & VPU_CMD_CONTROL_REG_RET_SUCCESS_CUR_LR_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_17 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_17_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_17_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_17_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_17_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_17_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_INSTANCE_INFO - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_INSTANCE_INFO_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_INSTANCE_INFO_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_INSTANCE_INFO_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_INSTANCE_INFO_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_INSTANCE_INFO_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_19 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_19_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_19_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_19_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_19_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_19_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_20 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_20_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_20_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_20_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_20_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_20_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_21 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_21_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_21_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_21_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_21_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_21_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_FIO_ADDR - FastIO Control/Address */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_FIO_ADDR_MASK (0xFFFFU) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_FIO_ADDR_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_FIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_FIO_ADDR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_FIO_ADDR_MASK) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_RW_FLAG_MASK (0x10000U) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_RW_FLAG_SHIFT (16U) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_RW_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_RW_FLAG_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_RW_FLAG_MASK) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_READY_MASK (0x80000000U) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_READY_SHIFT (31U) #define VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_READY(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_READY_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_FIO_ADDR_READY_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_FIO_DATA - FastIO Data */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_FIO_DATA_FIO_DATA_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_VPU_FIO_DATA_FIO_DATA_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_FIO_DATA_FIO_DATA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_FIO_DATA_FIO_DATA_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_FIO_DATA_FIO_DATA_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_0 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_0_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_0_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_0_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_0_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_0_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_1 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_1_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_1_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_1_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_1_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_1_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_22 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_22_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_22_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_22_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_22_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_22_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_VINT_REASON_CLR - Interrupt Reason Clear */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD0_CLR_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD0_CLR_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD0_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD0_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD0_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD1_CLR_MASK (0x2U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD1_CLR_SHIFT (1U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD1_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD1_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD1_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD2_CLR_MASK (0x4U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD2_CLR_SHIFT (2U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD2_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD2_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD2_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD3_CLR_MASK (0x8U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD3_CLR_SHIFT (3U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD3_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD3_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD3_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD4_CLR_MASK (0x10U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD4_CLR_SHIFT (4U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD4_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD4_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD4_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD5_CLR_MASK (0x20U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD5_CLR_SHIFT (5U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD5_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD5_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD5_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD6_CLR_MASK (0x40U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD6_CLR_SHIFT (6U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD6_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD6_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD6_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD7_CLR_MASK (0x80U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD7_CLR_SHIFT (7U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD7_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD7_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD7_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD8_CLR_MASK (0x100U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD8_CLR_SHIFT (8U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD8_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD8_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD8_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD9_CLR_MASK (0x200U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD9_CLR_SHIFT (9U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD9_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD9_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMD9_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDA_CLR_MASK (0x400U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDA_CLR_SHIFT (10U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDA_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDA_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDA_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDB_CLR_MASK (0x800U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDB_CLR_SHIFT (11U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDB_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDB_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDB_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDD_CLR_MASK (0x2000U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDD_CLR_SHIFT (13U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDD_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDD_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_CMDD_CLR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_BSEMPTY_CLR_MASK (0x8000U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_BSEMPTY_CLR_SHIFT (15U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_BSEMPTY_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_BSEMPTY_CLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CLR_BSEMPTY_CLR_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_HOST_INT_REQ - Host Interrupt Request */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_HOST_INT_REQ_HINTREQ_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_HOST_INT_REQ_HINTREQ_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_HOST_INT_REQ_HINTREQ(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_HOST_INT_REQ_HINTREQ_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_HOST_INT_REQ_HINTREQ_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_VINT_CLEAR - VPU Interrupt Clear */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_VINT_CLEAR_VINTCLR_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_VINT_CLEAR_VINTCLR_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_VINT_CLEAR_VINTCLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_CLEAR_VINTCLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_CLEAR_VINTCLR_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_HINT_CLEAR - Host Interrupt Clear */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_HINT_CLEAR_HINTCLR_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_HINT_CLEAR_HINTCLR_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_HINT_CLEAR_HINTCLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_HINT_CLEAR_HINTCLR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_HINT_CLEAR_HINTCLR_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_VPU_INT_STS - VPU Interrupt Status */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_VPU_INT_STS_VPU_VPU_INT_STS_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_VPU_INT_STS_VPU_VPU_INT_STS_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_VPU_INT_STS_VPU_VPU_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VPU_INT_STS_VPU_VPU_INT_STS_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VPU_INT_STS_VPU_VPU_INT_STS_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_VINT_ENABLE - VPU Interrupt Enable */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD0_EN_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD0_EN_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD0_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD0_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD0_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD1_EN_MASK (0x2U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD1_EN_SHIFT (1U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD1_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD1_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD1_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD2_EN_MASK (0x4U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD2_EN_SHIFT (2U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD2_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD2_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD2_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD3_EN_MASK (0x8U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD3_EN_SHIFT (3U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD3_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD3_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD3_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD4_EN_MASK (0x10U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD4_EN_SHIFT (4U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD4_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD4_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD4_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD5_EN_MASK (0x20U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD5_EN_SHIFT (5U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD5_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD5_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD5_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD6_EN_MASK (0x40U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD6_EN_SHIFT (6U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD6_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD6_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD6_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD7_EN_MASK (0x80U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD7_EN_SHIFT (7U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD7_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD7_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD7_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD8_EN_MASK (0x100U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD8_EN_SHIFT (8U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD8_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD8_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD8_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD9_EN_MASK (0x200U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD9_EN_SHIFT (9U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD9_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD9_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMD9_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDA_EN_MASK (0x400U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDA_EN_SHIFT (10U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDA_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDA_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDA_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDB_EN_MASK (0x800U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDB_EN_SHIFT (11U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDB_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDB_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDB_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDD_EN_MASK (0x2000U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDD_EN_SHIFT (13U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDD_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDD_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_CMDD_EN_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_BSEMPTY_EN_MASK (0x8000U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_BSEMPTY_EN_SHIFT (15U) #define VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_BSEMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_BSEMPTY_EN_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_ENABLE_BSEMPTY_EN_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_VINT_REASON - VPU Interrupt Reason */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD0_INTR_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD0_INTR_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD0_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD0_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD0_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD1_INTR_MASK (0x2U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD1_INTR_SHIFT (1U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD1_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD1_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD1_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD2_INTR_MASK (0x4U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD2_INTR_SHIFT (2U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD2_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD2_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD2_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD3_INTR_MASK (0x8U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD3_INTR_SHIFT (3U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD3_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD3_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD3_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD4_INTR_MASK (0x10U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD4_INTR_SHIFT (4U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD4_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD4_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD4_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD5_INTR_MASK (0x20U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD5_INTR_SHIFT (5U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD5_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD5_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD5_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD6_INTR_MASK (0x40U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD6_INTR_SHIFT (6U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD6_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD6_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD6_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD7_INTR_MASK (0x80U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD7_INTR_SHIFT (7U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD7_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD7_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD7_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD8_INTR_MASK (0x100U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD8_INTR_SHIFT (8U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD8_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD8_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD8_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD9_INTR_MASK (0x200U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD9_INTR_SHIFT (9U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD9_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD9_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMD9_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDA_INTR_MASK (0x400U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDA_INTR_SHIFT (10U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDA_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDA_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDA_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDB_INTR_MASK (0x800U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDB_INTR_SHIFT (11U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDB_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDB_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDB_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDD_INTR_MASK (0x2000U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDD_INTR_SHIFT (13U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDD_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDD_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_CMDD_INTR_MASK) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_BSEMPTY_INTR_MASK (0x8000U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_BSEMPTY_INTR_SHIFT (15U) #define VPU_CMD_CONTROL_REG_VPU_VINT_REASON_BSEMPTY_INTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VINT_REASON_BSEMPTY_INTR_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VINT_REASON_BSEMPTY_INTR_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VCPU_CMD_BUSY_STATUS - V-CPU Busy Status */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VCPU_CMD_BUSY_STATUS_VCPU_CMD_BUSY_STATUS_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VCPU_CMD_BUSY_STATUS_VCPU_CMD_BUSY_STATUS_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VCPU_CMD_BUSY_STATUS_VCPU_CMD_BUSY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VCPU_CMD_BUSY_STATUS_VCPU_CMD_BUSY_STATUS_SHIFT)) & VPU_CMD_CONTROL_REG_VCPU_CMD_BUSY_STATUS_VCPU_CMD_BUSY_STATUS_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_HALT_STATUS - VPU Halt Status */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_DEBUG_MASK (0xFU) #define VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_DEBUG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_DEBUG_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_DEBUG_MASK) #define VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_MASK (0x10U) #define VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_SHIFT (4U) #define VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_HALT_STATUS_VPU_HALT_STATUS_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_VCPU_STATUS - VPU_VCPU_STATUS */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_VCPU_STATUS_VPU_VCPU_STATUS_MASK (0x7FFFU) #define VPU_CMD_CONTROL_REG_VPU_VCPU_STATUS_VPU_VCPU_STATUS_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_VCPU_STATUS_VPU_VCPU_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_VCPU_STATUS_VPU_VCPU_STATUS_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_VCPU_STATUS_VPU_VCPU_STATUS_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_BUSY_STATUS - VPU Busy Status */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_BUSY_STATUS_VPU_BUSY_STATUS_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_BUSY_STATUS_VPU_BUSY_STATUS_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_BUSY_STATUS_VPU_BUSY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_BUSY_STATUS_VPU_BUSY_STATUS_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_BUSY_STATUS_VPU_BUSY_STATUS_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_FIO_STATUS - ret_fio_status */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_FIO_STATUS_FIO_STATUS_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_FIO_STATUS_FIO_STATUS_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_FIO_STATUS_FIO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_FIO_STATUS_FIO_STATUS_SHIFT)) & VPU_CMD_CONTROL_REG_RET_FIO_STATUS_FIO_STATUS_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_3 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_3_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_3_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_3_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_3_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_3_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_4 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_4_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_4_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_4_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_4_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_4_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_5 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_5_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_5_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_5_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_5_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_5_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_PRODUCT_NAME - HW product name */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_PRODUCT_NAME_HW_NAME_MASK (0xFU) #define VPU_CMD_CONTROL_REG_RET_PRODUCT_NAME_HW_NAME_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_PRODUCT_NAME_HW_NAME(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_PRODUCT_NAME_HW_NAME_SHIFT)) & VPU_CMD_CONTROL_REG_RET_PRODUCT_NAME_HW_NAME_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_PRODUCT_VERSION - HW product version */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_PRODUCT_VERSION_PRODUCT_NUMBER_MASK (0xFU) #define VPU_CMD_CONTROL_REG_RET_PRODUCT_VERSION_PRODUCT_NUMBER_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_PRODUCT_VERSION_PRODUCT_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_PRODUCT_VERSION_PRODUCT_NUMBER_SHIFT)) & VPU_CMD_CONTROL_REG_RET_PRODUCT_VERSION_PRODUCT_NUMBER_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_VCPU_CONFIG0 - Configuration Information #0 */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG0_CONFIG_VCPU0_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG0_CONFIG_VCPU0_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG0_CONFIG_VCPU0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG0_CONFIG_VCPU0_SHIFT)) & VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG0_CONFIG_VCPU0_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_VCPU_CONFIG1 - Configuration Information #1 */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG1_CONFIG_VCPU1_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG1_CONFIG_VCPU1_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG1_CONFIG_VCPU1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG1_CONFIG_VCPU1_SHIFT)) & VPU_CMD_CONTROL_REG_RET_VCPU_CONFIG1_CONFIG_VCPU1_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_CODEC_STD - Standard Definition */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_CODEC_STD_CODEC_STD_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_CODEC_STD_CODEC_STD_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_CODEC_STD_CODEC_STD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_CODEC_STD_CODEC_STD_SHIFT)) & VPU_CMD_CONTROL_REG_RET_CODEC_STD_CODEC_STD_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_CONF_DATE - Configuration Date */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_CONF_DATE_HW_DATE_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_CONF_DATE_HW_DATE_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_CONF_DATE_HW_DATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_CONF_DATE_HW_DATE_SHIFT)) & VPU_CMD_CONTROL_REG_RET_CONF_DATE_HW_DATE_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_CONF_REVISION - The revision of H/W configuration */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_CONF_REVISION_HW_REVISION_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_CONF_REVISION_HW_REVISION_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_CONF_REVISION_HW_REVISION(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_CONF_REVISION_HW_REVISION_SHIFT)) & VPU_CMD_CONTROL_REG_RET_CONF_REVISION_HW_REVISION_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_CONF_TYPE - The define value of H/W configuration */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_CONF_TYPE_HW_TYPE_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_CONF_TYPE_HW_TYPE_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_CONF_TYPE_HW_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_CONF_TYPE_HW_TYPE_SHIFT)) & VPU_CMD_CONTROL_REG_RET_CONF_TYPE_HW_TYPE_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_VCORE0_CFG - Configuration Information of VCORE0 */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_VCORE0_CFG_CONFIG_VCORE0_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_VCORE0_CFG_CONFIG_VCORE0_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_VCORE0_CFG_CONFIG_VCORE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_VCORE0_CFG_CONFIG_VCORE0_SHIFT)) & VPU_CMD_CONTROL_REG_RET_VCORE0_CFG_CONFIG_VCORE0_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_VCORE1_CFG - Configuration Information of VCORE1 */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_VCORE1_CFG_CONFIG_VCORE1_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_VCORE1_CFG_CONFIG_VCORE1_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_VCORE1_CFG_CONFIG_VCORE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_VCORE1_CFG_CONFIG_VCORE1_SHIFT)) & VPU_CMD_CONTROL_REG_RET_VCORE1_CFG_CONFIG_VCORE1_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_VCORE2_CFG - Configuration Information of VCORE2 */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_VCORE2_CFG_CONFIG_VCORE2_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_VCORE2_CFG_CONFIG_VCORE2_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_VCORE2_CFG_CONFIG_VCORE2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_VCORE2_CFG_CONFIG_VCORE2_SHIFT)) & VPU_CMD_CONTROL_REG_RET_VCORE2_CFG_CONFIG_VCORE2_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_RET_VCORE3_CFG - Configuration Information of VCORE3 */ /*! @{ */ #define VPU_CMD_CONTROL_REG_RET_VCORE3_CFG_CONFIG_VCORE3_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_RET_VCORE3_CFG_CONFIG_VCORE3_SHIFT (0U) #define VPU_CMD_CONTROL_REG_RET_VCORE3_CFG_CONFIG_VCORE3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_RET_VCORE3_CFG_CONFIG_VCORE3_SHIFT)) & VPU_CMD_CONTROL_REG_RET_VCORE3_CFG_CONFIG_VCORE3_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_RET_VCORE_PRESENT - Number of VCOREs present */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_RET_VCORE_PRESENT_VCORE_PRESENT_MASK (0xFU) #define VPU_CMD_CONTROL_REG_VPU_RET_VCORE_PRESENT_VCORE_PRESENT_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_RET_VCORE_PRESENT_VCORE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_RET_VCORE_PRESENT_VCORE_PRESENT_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_RET_VCORE_PRESENT_VCORE_PRESENT_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_6 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_6_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_6_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_6_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_6_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_6_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_7 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_7_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_7_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_7_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_7_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_7_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_8 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_8_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_8_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_8_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_8_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_8_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_9 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_9_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_9_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_9_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_9_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_9_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_10 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_10_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_10_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_10_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_10_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_10_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_11 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_11_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_11_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_11_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_11_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_11_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_12 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_12_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_12_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_12_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_12_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_12_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_13 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_13_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_13_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_13_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_13_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_13_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_14 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_14_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_14_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_14_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_14_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_14_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_DBG_MSG_15 - Debugging message */ /*! @{ */ #define VPU_CMD_CONTROL_REG_DBG_MSG_15_DBG_MSG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_DBG_MSG_15_DBG_MSG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_DBG_MSG_15_DBG_MSG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_DBG_MSG_15_DBG_MSG_SHIFT)) & VPU_CMD_CONTROL_REG_DBG_MSG_15_DBG_MSG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_DBG_SW_UART_STATUS - VPU_dbg_sw_uart_status */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_STATUS_VPU_DBG_SW_UART_STATUS_MASK (0xFU) #define VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_STATUS_VPU_DBG_SW_UART_STATUS_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_STATUS_VPU_DBG_SW_UART_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_STATUS_VPU_DBG_SW_UART_STATUS_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_STATUS_VPU_DBG_SW_UART_STATUS_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_DBG_SW_UART_TX - VPU_ dbg_sw_uart_tx */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_TX_VPU_DBG_SW_UART_TX_MASK (0xFU) #define VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_TX_VPU_DBG_SW_UART_TX_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_TX_VPU_DBG_SW_UART_TX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_TX_VPU_DBG_SW_UART_TX_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_DBG_SW_UART_TX_VPU_DBG_SW_UART_TX_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_DBG_REG_0 - VPU_dbg_reg */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_DBG_REG_0_VPU_DBG_REG_0_MASK (0xFU) #define VPU_CMD_CONTROL_REG_VPU_DBG_REG_0_VPU_DBG_REG_0_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_DBG_REG_0_VPU_DBG_REG_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_DBG_REG_0_VPU_DBG_REG_0_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_DBG_REG_0_VPU_DBG_REG_0_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_DBG_REG_1 - VPU_dbg_reg */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_DBG_REG_1_VPU_DBG_REG_1_MASK (0xFU) #define VPU_CMD_CONTROL_REG_VPU_DBG_REG_1_VPU_DBG_REG_1_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_DBG_REG_1_VPU_DBG_REG_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_DBG_REG_1_VPU_DBG_REG_1_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_DBG_REG_1_VPU_DBG_REG_1_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL - VPU SFS Control */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_end_of_row_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_end_of_row_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_end_of_row(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_end_of_row_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_end_of_row_MASK) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_new_frame_MASK (0x2U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_new_frame_SHIFT (1U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_new_frame(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_new_frame_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_new_frame_MASK) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_current_buffer_MASK (0x7CU) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_current_buffer_SHIFT (2U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_current_buffer(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_current_buffer_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_current_buffer_MASK) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_valid_MASK (0x8000U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_valid_SHIFT (15U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_valid(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_valid_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_valid_MASK) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_cnt_MASK (0xFFFF0000U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_cnt_SHIFT (16U) #define VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_cnt(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_cnt_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_SUB_FRAME_SYNC_CTRL_ipu_frame_row_cnt_MASK) /*! @} */ /*! @name CMD_COMMAND - Command */ /*! @{ */ #define VPU_CMD_COMMAND_COMMAND_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_COMMAND_SHIFT (0U) #define VPU_CMD_COMMAND_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_COMMAND_SHIFT)) & VPU_CMD_COMMAND_COMMAND_MASK) /*! @} */ /*! @name CMD_COMMAND_OPTION - Command Option */ /*! @{ */ #define VPU_CMD_COMMAND_OPTION_COMMAND_OPTION_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_OPTION_COMMAND_OPTION_SHIFT (0U) #define VPU_CMD_COMMAND_OPTION_COMMAND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_OPTION_COMMAND_OPTION_SHIFT)) & VPU_CMD_COMMAND_OPTION_COMMAND_OPTION_MASK) /*! @} */ /*! @name CMD_DEC_PIC_OPTION - decoding picture option */ /*! @{ */ #define VPU_CMD_DEC_PIC_OPTION_SKIP_MODE_MASK (0x3FU) #define VPU_CMD_DEC_PIC_OPTION_SKIP_MODE_SHIFT (0U) #define VPU_CMD_DEC_PIC_OPTION_SKIP_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_OPTION_SKIP_MODE_SHIFT)) & VPU_CMD_DEC_PIC_OPTION_SKIP_MODE_MASK) #define VPU_CMD_DEC_PIC_OPTION_FORCE_FILM_GRAIN_OFF_MASK (0x40U) #define VPU_CMD_DEC_PIC_OPTION_FORCE_FILM_GRAIN_OFF_SHIFT (6U) #define VPU_CMD_DEC_PIC_OPTION_FORCE_FILM_GRAIN_OFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_OPTION_FORCE_FILM_GRAIN_OFF_SHIFT)) & VPU_CMD_DEC_PIC_OPTION_FORCE_FILM_GRAIN_OFF_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_OPTION - CMD_ENC_SET_PARAM option */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_OPTION_SET_PARAM_OPTION_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_OPTION_SET_PARAM_OPTION_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_OPTION_SET_PARAM_OPTION(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_OPTION_SET_PARAM_OPTION_SHIFT)) & VPU_CMD_ENC_SET_PARAM_OPTION_SET_PARAM_OPTION_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_OPTION - Run command option */ /*! @{ */ #define VPU_CMD_INIT_SEQ_OPTION_INIT_SEQ_OPTION_MASK (0x3FU) #define VPU_CMD_INIT_SEQ_OPTION_INIT_SEQ_OPTION_SHIFT (0U) #define VPU_CMD_INIT_SEQ_OPTION_INIT_SEQ_OPTION(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_OPTION_INIT_SEQ_OPTION_SHIFT)) & VPU_CMD_INIT_SEQ_OPTION_INIT_SEQ_OPTION_MASK) /*! @} */ /*! @name CMD_SET_DISP_OPTION - SET_DISP_command option */ /*! @{ */ #define VPU_CMD_SET_DISP_OPTION_FB_ENDIAN_MASK (0xF0000U) #define VPU_CMD_SET_DISP_OPTION_FB_ENDIAN_SHIFT (16U) #define VPU_CMD_SET_DISP_OPTION_FB_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_OPTION_FB_ENDIAN_SHIFT)) & VPU_CMD_SET_DISP_OPTION_FB_ENDIAN_MASK) /*! @} */ /*! @name CMD_SET_FB_OPTION - SET_FB command option */ /*! @{ */ #define VPU_CMD_SET_FB_OPTION_SET_FB_MODE_MASK (0x7U) #define VPU_CMD_SET_FB_OPTION_SET_FB_MODE_SHIFT (0U) #define VPU_CMD_SET_FB_OPTION_SET_FB_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_OPTION_SET_FB_MODE_SHIFT)) & VPU_CMD_SET_FB_OPTION_SET_FB_MODE_MASK) #define VPU_CMD_SET_FB_OPTION_FB_GROUP_INDICATOR_MASK (0x8U) #define VPU_CMD_SET_FB_OPTION_FB_GROUP_INDICATOR_SHIFT (3U) #define VPU_CMD_SET_FB_OPTION_FB_GROUP_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_OPTION_FB_GROUP_INDICATOR_SHIFT)) & VPU_CMD_SET_FB_OPTION_FB_GROUP_INDICATOR_MASK) #define VPU_CMD_SET_FB_OPTION_SETUP_DONE_MASK (0x10U) #define VPU_CMD_SET_FB_OPTION_SETUP_DONE_SHIFT (4U) #define VPU_CMD_SET_FB_OPTION_SETUP_DONE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_OPTION_SETUP_DONE_SHIFT)) & VPU_CMD_SET_FB_OPTION_SETUP_DONE_MASK) #define VPU_CMD_SET_FB_OPTION_FB_ENDIAN_MASK (0xF0000U) #define VPU_CMD_SET_FB_OPTION_FB_ENDIAN_SHIFT (16U) #define VPU_CMD_SET_FB_OPTION_FB_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_OPTION_FB_ENDIAN_SHIFT)) & VPU_CMD_SET_FB_OPTION_FB_ENDIAN_MASK) #define VPU_CMD_SET_FB_OPTION_NON_REF_FBC_WRITING_MASK (0x4000000U) #define VPU_CMD_SET_FB_OPTION_NON_REF_FBC_WRITING_SHIFT (26U) #define VPU_CMD_SET_FB_OPTION_NON_REF_FBC_WRITING(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_OPTION_NON_REF_FBC_WRITING_SHIFT)) & VPU_CMD_SET_FB_OPTION_NON_REF_FBC_WRITING_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_OPTION - Run command option */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_OPTION_SET_FB_MODE_MASK (0x7U) #define VPU_CMD_SET_FB_UPDATE_OPTION_SET_FB_MODE_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_OPTION_SET_FB_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_OPTION_SET_FB_MODE_SHIFT)) & VPU_CMD_SET_FB_UPDATE_OPTION_SET_FB_MODE_MASK) /*! @} */ /*! @name CMD_COMMAND_RET_SUCCESS - Result of the command */ /*! @{ */ #define VPU_CMD_COMMAND_RET_SUCCESS_RUN_CMD_STATUS_MASK (0x3U) #define VPU_CMD_COMMAND_RET_SUCCESS_RUN_CMD_STATUS_SHIFT (0U) #define VPU_CMD_COMMAND_RET_SUCCESS_RUN_CMD_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_RET_SUCCESS_RUN_CMD_STATUS_SHIFT)) & VPU_CMD_COMMAND_RET_SUCCESS_RUN_CMD_STATUS_MASK) /*! @} */ /*! @name CMD_COMMAND_RET_FAIL_REASON - Fail reason of the run command */ /*! @{ */ #define VPU_CMD_COMMAND_RET_FAIL_REASON_FAIL_REASON_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_RET_FAIL_REASON_FAIL_REASON_SHIFT (0U) #define VPU_CMD_COMMAND_RET_FAIL_REASON_FAIL_REASON(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_RET_FAIL_REASON_FAIL_REASON_SHIFT)) & VPU_CMD_COMMAND_RET_FAIL_REASON_FAIL_REASON_MASK) /*! @} */ /*! @name CMD_COMMAND_INSTANCE_INFO - Instance information */ /*! @{ */ #define VPU_CMD_COMMAND_INSTANCE_INFO_INST_ID_MASK (0xFFFFU) #define VPU_CMD_COMMAND_INSTANCE_INFO_INST_ID_SHIFT (0U) #define VPU_CMD_COMMAND_INSTANCE_INFO_INST_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_INSTANCE_INFO_INST_ID_SHIFT)) & VPU_CMD_COMMAND_INSTANCE_INFO_INST_ID_MASK) #define VPU_CMD_COMMAND_INSTANCE_INFO_CODEC_STD_MASK (0xFFFF0000U) #define VPU_CMD_COMMAND_INSTANCE_INFO_CODEC_STD_SHIFT (16U) #define VPU_CMD_COMMAND_INSTANCE_INFO_CODEC_STD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_INSTANCE_INFO_CODEC_STD_SHIFT)) & VPU_CMD_COMMAND_INSTANCE_INFO_CODEC_STD_MASK) /*! @} */ /*! @name CMD_COMMAND_QUE_FULL_IDC - cmd queue full indicator */ /*! @{ */ #define VPU_CMD_COMMAND_QUE_FULL_IDC_CMD_QUEUE_FULLNESS_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_QUE_FULL_IDC_CMD_QUEUE_FULLNESS_SHIFT (0U) #define VPU_CMD_COMMAND_QUE_FULL_IDC_CMD_QUEUE_FULLNESS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_QUE_FULL_IDC_CMD_QUEUE_FULLNESS_SHIFT)) & VPU_CMD_COMMAND_QUE_FULL_IDC_CMD_QUEUE_FULLNESS_MASK) /*! @} */ /*! @name CMD_COMMAND_RET_QUE_EMPTY_IDC - cmd queue empty indicator */ /*! @{ */ #define VPU_CMD_COMMAND_RET_QUE_EMPTY_IDC_RET_QUEUE_EMPTY_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_RET_QUE_EMPTY_IDC_RET_QUEUE_EMPTY_SHIFT (0U) #define VPU_CMD_COMMAND_RET_QUE_EMPTY_IDC_RET_QUEUE_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_RET_QUE_EMPTY_IDC_RET_QUEUE_EMPTY_SHIFT)) & VPU_CMD_COMMAND_RET_QUE_EMPTY_IDC_RET_QUEUE_EMPTY_MASK) /*! @} */ /*! @name CMD_COMMAND_DONE_INST_IDC - cmd done instance id */ /*! @{ */ #define VPU_CMD_COMMAND_DONE_INST_IDC_DONE_INST_IDC_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_DONE_INST_IDC_DONE_INST_IDC_SHIFT (0U) #define VPU_CMD_COMMAND_DONE_INST_IDC_DONE_INST_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_DONE_INST_IDC_DONE_INST_IDC_SHIFT)) & VPU_CMD_COMMAND_DONE_INST_IDC_DONE_INST_IDC_MASK) /*! @} */ /*! @name CMD_COMMAND_RET_CREATE_INSTANCE_ID - instance id */ /*! @{ */ #define VPU_CMD_COMMAND_RET_CREATE_INSTANCE_ID_INSTANCE_ID_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_RET_CREATE_INSTANCE_ID_INSTANCE_ID_SHIFT (0U) #define VPU_CMD_COMMAND_RET_CREATE_INSTANCE_ID_INSTANCE_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_RET_CREATE_INSTANCE_ID_INSTANCE_ID_SHIFT)) & VPU_CMD_COMMAND_RET_CREATE_INSTANCE_ID_INSTANCE_ID_MASK) /*! @} */ /*! @name CMD_COMMAND_RET_CMD_CQ_IN_TICK - cmd queue in tick */ /*! @{ */ #define VPU_CMD_COMMAND_RET_CMD_CQ_IN_TICK_CMD_CQ_IN_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_RET_CMD_CQ_IN_TICK_CMD_CQ_IN_TICK_SHIFT (0U) #define VPU_CMD_COMMAND_RET_CMD_CQ_IN_TICK_CMD_CQ_IN_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_RET_CMD_CQ_IN_TICK_CMD_CQ_IN_TICK_SHIFT)) & VPU_CMD_COMMAND_RET_CMD_CQ_IN_TICK_CMD_CQ_IN_TICK_MASK) /*! @} */ /*! @name CMD_COMMAND_RET_CMD_FW_RUN_TICK - cmd fw run tick */ /*! @{ */ #define VPU_CMD_COMMAND_RET_CMD_FW_RUN_TICK_CMD_FW_RUN_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_RET_CMD_FW_RUN_TICK_CMD_FW_RUN_TICK_SHIFT (0U) #define VPU_CMD_COMMAND_RET_CMD_FW_RUN_TICK_CMD_FW_RUN_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_RET_CMD_FW_RUN_TICK_CMD_FW_RUN_TICK_SHIFT)) & VPU_CMD_COMMAND_RET_CMD_FW_RUN_TICK_CMD_FW_RUN_TICK_MASK) /*! @} */ /*! @name CMD_COMMAND_RET_CMD_HW_RUN_TICK - cmd hw_core run tick */ /*! @{ */ #define VPU_CMD_COMMAND_RET_CMD_HW_RUN_TICK_CMD_HW_RUN_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMAND_RET_CMD_HW_RUN_TICK_CMD_HW_RUN_TICK_SHIFT (0U) #define VPU_CMD_COMMAND_RET_CMD_HW_RUN_TICK_CMD_HW_RUN_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMAND_RET_CMD_HW_RUN_TICK_CMD_HW_RUN_TICK_SHIFT)) & VPU_CMD_COMMAND_RET_CMD_HW_RUN_TICK_CMD_HW_RUN_TICK_MASK) /*! @} */ /*! @name CMD_COMMON_RET_CMD_HW_DONE_TICK - cmd hw_core done tick */ /*! @{ */ #define VPU_CMD_COMMON_RET_CMD_HW_DONE_TICK_CMD_HW_DONE_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMON_RET_CMD_HW_DONE_TICK_CMD_HW_DONE_TICK_SHIFT (0U) #define VPU_CMD_COMMON_RET_CMD_HW_DONE_TICK_CMD_HW_DONE_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMON_RET_CMD_HW_DONE_TICK_CMD_HW_DONE_TICK_SHIFT)) & VPU_CMD_COMMON_RET_CMD_HW_DONE_TICK_CMD_HW_DONE_TICK_MASK) /*! @} */ /*! @name CMD_COMMON_RET_CMD_FW_DONE_TICK - cmd fw done tick */ /*! @{ */ #define VPU_CMD_COMMON_RET_CMD_FW_DONE_TICK_CMD_FW_DONE_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMON_RET_CMD_FW_DONE_TICK_CMD_FW_DONE_TICK_SHIFT (0U) #define VPU_CMD_COMMON_RET_CMD_FW_DONE_TICK_CMD_FW_DONE_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMON_RET_CMD_FW_DONE_TICK_CMD_FW_DONE_TICK_SHIFT)) & VPU_CMD_COMMON_RET_CMD_FW_DONE_TICK_CMD_FW_DONE_TICK_MASK) /*! @} */ /*! @name CMD_COMMON_RET_CMD_RQ_OUT_TICK - cmd return queue out tick */ /*! @{ */ #define VPU_CMD_COMMON_RET_CMD_RQ_OUT_TICK_CMD_RQ_OUT_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMON_RET_CMD_RQ_OUT_TICK_CMD_RQ_OUT_TICK_SHIFT (0U) #define VPU_CMD_COMMON_RET_CMD_RQ_OUT_TICK_CMD_RQ_OUT_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMON_RET_CMD_RQ_OUT_TICK_CMD_RQ_OUT_TICK_SHIFT)) & VPU_CMD_COMMON_RET_CMD_RQ_OUT_TICK_CMD_RQ_OUT_TICK_MASK) /*! @} */ /*! @name CMD_COMMON_RET_CMD_FW_PRE_RUN_TICK - cmd fw pre-core run tick */ /*! @{ */ #define VPU_CMD_COMMON_RET_CMD_FW_PRE_RUN_TICK_CMD_FW_PRE_RUN_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMON_RET_CMD_FW_PRE_RUN_TICK_CMD_FW_PRE_RUN_TICK_SHIFT (0U) #define VPU_CMD_COMMON_RET_CMD_FW_PRE_RUN_TICK_CMD_FW_PRE_RUN_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMON_RET_CMD_FW_PRE_RUN_TICK_CMD_FW_PRE_RUN_TICK_SHIFT)) & VPU_CMD_COMMON_RET_CMD_FW_PRE_RUN_TICK_CMD_FW_PRE_RUN_TICK_MASK) /*! @} */ /*! @name CMD_COMMON_RET_CMD_HW_PRE_RUN_TICK - cmd hw pre-core run tick */ /*! @{ */ #define VPU_CMD_COMMON_RET_CMD_HW_PRE_RUN_TICK_CMD_HW_PRE_RUN_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMON_RET_CMD_HW_PRE_RUN_TICK_CMD_HW_PRE_RUN_TICK_SHIFT (0U) #define VPU_CMD_COMMON_RET_CMD_HW_PRE_RUN_TICK_CMD_HW_PRE_RUN_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMON_RET_CMD_HW_PRE_RUN_TICK_CMD_HW_PRE_RUN_TICK_SHIFT)) & VPU_CMD_COMMON_RET_CMD_HW_PRE_RUN_TICK_CMD_HW_PRE_RUN_TICK_MASK) /*! @} */ /*! @name CMD_COMMON_RET_CMD_HW_PRE_DONE_TICK - cmd hw pre-core done tick */ /*! @{ */ #define VPU_CMD_COMMON_RET_CMD_HW_PRE_DONE_TICK_CMD_HW_PRE_DONE_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMON_RET_CMD_HW_PRE_DONE_TICK_CMD_HW_PRE_DONE_TICK_SHIFT (0U) #define VPU_CMD_COMMON_RET_CMD_HW_PRE_DONE_TICK_CMD_HW_PRE_DONE_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMON_RET_CMD_HW_PRE_DONE_TICK_CMD_HW_PRE_DONE_TICK_SHIFT)) & VPU_CMD_COMMON_RET_CMD_HW_PRE_DONE_TICK_CMD_HW_PRE_DONE_TICK_MASK) /*! @} */ /*! @name CMD_COMMON_RET_CMD_FW_PRE_DONE_TICK - cmd fw pre-core done tick */ /*! @{ */ #define VPU_CMD_COMMON_RET_CMD_FW_PRE_DONE_TICK_CMD_FW_PRE_DONE_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_COMMON_RET_CMD_FW_PRE_DONE_TICK_CMD_FW_PRE_DONE_TICK_SHIFT (0U) #define VPU_CMD_COMMON_RET_CMD_FW_PRE_DONE_TICK_CMD_FW_PRE_DONE_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_COMMON_RET_CMD_FW_PRE_DONE_TICK_CMD_FW_PRE_DONE_TICK_SHIFT)) & VPU_CMD_COMMON_RET_CMD_FW_PRE_DONE_TICK_CMD_FW_PRE_DONE_TICK_MASK) /*! @} */ /*! @name CMD_CREATE_INST_WORK_BASE - Work buffer base address */ /*! @{ */ #define VPU_CMD_CREATE_INST_WORK_BASE_WORK_BUF_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_WORK_BASE_WORK_BUF_BASE_SHIFT (0U) #define VPU_CMD_CREATE_INST_WORK_BASE_WORK_BUF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_WORK_BASE_WORK_BUF_BASE_SHIFT)) & VPU_CMD_CREATE_INST_WORK_BASE_WORK_BUF_BASE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_ADDR_USERDATA_BASE - User Data Buffer Base Address */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_MASK) /*! @} */ /*! @name CMD_DEC_PIC_BS_RD_PTR - Bistream Buffer Read Pointer */ /*! @{ */ #define VPU_CMD_DEC_PIC_BS_RD_PTR_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_PIC_BS_RD_PTR_RD_PTR_SHIFT (0U) #define VPU_CMD_DEC_PIC_BS_RD_PTR_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_BS_RD_PTR_RD_PTR_SHIFT)) & VPU_CMD_DEC_PIC_BS_RD_PTR_RD_PTR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_RD_PTR - bitstream buffer read pointer */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_RD_PTR_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_RD_PTR_RD_PTR_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_RD_PTR_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_RD_PTR_RD_PTR_SHIFT)) & VPU_CMD_ENC_GET_RESULT_RD_PTR_RD_PTR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_BS_START - Bitstream buffer start address */ /*! @{ */ #define VPU_CMD_ENC_PIC_BS_START_BS_START_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_BS_START_BS_START_ADDR_SHIFT (0U) #define VPU_CMD_ENC_PIC_BS_START_BS_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_BS_START_BS_START_ADDR_SHIFT)) & VPU_CMD_ENC_PIC_BS_START_BS_START_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_ENABLE - Change parameter enable flags */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_PPS_PARAM_MASK (0x1U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_PPS_PARAM_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_PPS_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_PPS_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_PPS_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_COUNT_PARAM_MASK (0x2U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_COUNT_PARAM_SHIFT (1U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_COUNT_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_COUNT_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_COUNT_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_INTRA_PARAM_MASK (0x4U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_INTRA_PARAM_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_INTRA_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_INTRA_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_INTRA_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_QP_PARAM_MASK (0x10U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_QP_PARAM_SHIFT (4U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_QP_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_QP_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_TEMPORAL_QP_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_SLICE_PARAM_MASK (0x40U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_SLICE_PARAM_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_SLICE_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_SLICE_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_SLICE_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_TARGET_RATE_MASK (0x400U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_TARGET_RATE_SHIFT (10U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_TARGET_RATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_TARGET_RATE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_TARGET_RATE_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_PARAM_MASK (0x800U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_PARAM_SHIFT (11U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_MIN_MAX_QP_MASK (0x1000U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_MIN_MAX_QP_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_MIN_MAX_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_MIN_MAX_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_MIN_MAX_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_MAX_BITRATE_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_MAX_BITRATE_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_MAX_BITRATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_MAX_BITRATE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_MAX_BITRATE_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_VBV_BUFFER_SIZE_MASK (0x4000U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_VBV_BUFFER_SIZE_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_VBV_BUFFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_VBV_BUFFER_SIZE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_RC_VBV_BUFFER_SIZE_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_VUI_HRD_PARAM_MASK (0x100000U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_VUI_HRD_PARAM_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_VUI_HRD_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_VUI_HRD_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_VUI_HRD_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_BG_PARAM_MASK (0x400000U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_BG_PARAM_SHIFT (22U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_BG_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_BG_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_BG_PARAM_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QROUND_OFFSET_MASK (0x4000000U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QROUND_OFFSET_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QROUND_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QROUND_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QROUND_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QUANT_PARAM_MASK (0x8000000U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QUANT_PARAM_SHIFT (27U) #define VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QUANT_PARAM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QUANT_PARAM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ENABLE_ENABLE_SET_QUANT_PARAM_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM - Bitstream sequence parameter information */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_LEVEL_IDC_MASK (0xFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_LEVEL_IDC_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_LEVEL_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_LEVEL_IDC_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_LEVEL_IDC_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_MASK (0x100U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_SHIFT (8U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_MASK (0x200U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_SHIFT (9U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_INTERLACE_SOURCE_FLAG_MASK (0x400U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_INTERLACE_SOURCE_FLAG_SHIFT (10U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_INTERLACE_SOURCE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_INTERLACE_SOURCE_FLAG_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_INTERLACE_SOURCE_FLAG_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROGRESS_SOURCE_FLAG_MASK (0x800U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROGRESS_SOURCE_FLAG_SHIFT (11U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROGRESS_SOURCE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROGRESS_SOURCE_FLAG_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROGRESS_SOURCE_FLAG_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_MASK (0xFF000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_SHIFT (12U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_SPS_MAX_SUB_LAYER_MASK (0xE00000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_SPS_MAX_SUB_LAYER_SHIFT (21U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_SPS_MAX_SUB_LAYER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_SPS_MAX_SUB_LAYER_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_SPS_MAX_SUB_LAYER_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_IDC_MASK (0x1F000000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_IDC_SHIFT (24U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_IDC_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_IDC_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_TIER_FLAG_MASK (0x20000000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_TIER_FLAG_SHIFT (29U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_TIER_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_TIER_FLAG_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_TIER_FLAG_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_SPACE_MASK (0xC0000000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_SPACE_SHIFT (30U) #define VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_SPACE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_SPACE_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_SEQ_PARAM_PROFILE_SPACE_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_BS_RD_PTR - Bitstream buffer read pointer */ /*! @{ */ #define VPU_CMD_INIT_SEQ_BS_RD_PTR_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_CMD_INIT_SEQ_BS_RD_PTR_RD_PTR_SHIFT (0U) #define VPU_CMD_INIT_SEQ_BS_RD_PTR_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_BS_RD_PTR_RD_PTR_SHIFT)) & VPU_CMD_INIT_SEQ_BS_RD_PTR_RD_PTR_MASK) /*! @} */ /*! @name CMD_SET_DISP_COMMON_PIC_INFO - DPB information */ /*! @{ */ #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_FB_STRIDE_MASK (0xFFFFU) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_FB_STRIDE_SHIFT (0U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_FB_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_FB_STRIDE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_FB_STRIDE_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_CHROMA_OUTPUT_FORMAT_MASK (0x70000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_CHROMA_OUTPUT_FORMAT_SHIFT (16U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_CHROMA_OUTPUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_CHROMA_OUTPUT_FORMAT_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_CHROMA_OUTPUT_FORMAT_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_OUTPUT_MODE_MASK (0x700000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_OUTPUT_MODE_SHIFT (20U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_OUTPUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_OUTPUT_MODE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_OUTPUT_MODE_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_ORDER_MODE_MASK (0x800000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_ORDER_MODE_SHIFT (23U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_ORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_ORDER_MODE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_PIXEL_ORDER_MODE_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_OUTPUT_CHROMA_FORMAT_IDC_MASK (0x3000000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_OUTPUT_CHROMA_FORMAT_IDC_SHIFT (24U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_OUTPUT_CHROMA_FORMAT_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_OUTPUT_CHROMA_FORMAT_IDC_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_OUTPUT_CHROMA_FORMAT_IDC_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_ONE_PLANE_OUTPUT_ENABLE_MASK (0x4000000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_ONE_PLANE_OUTPUT_ENABLE_SHIFT (26U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_ONE_PLANE_OUTPUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_ONE_PLANE_OUTPUT_ENABLE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_ONE_PLANE_OUTPUT_ENABLE_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_CSC_ENABLE_MASK (0x8000000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_CSC_ENABLE_SHIFT (27U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_CSC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_CSC_ENABLE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_CSC_ENABLE_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_BWB_ENABLE_MASK (0x10000000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_BWB_ENABLE_SHIFT (28U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_BWB_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_BWB_ENABLE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_BWB_ENABLE_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_AFBC_ENABLE_MASK (0x40000000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_AFBC_ENABLE_SHIFT (30U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_AFBC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_AFBC_ENABLE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_AFBC_ENABLE_MASK) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PVRIC_ENABLE_MASK (0x80000000U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PVRIC_ENABLE_SHIFT (31U) #define VPU_CMD_SET_DISP_COMMON_PIC_INFO_PVRIC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_COMMON_PIC_INFO_PVRIC_ENABLE_SHIFT)) & VPU_CMD_SET_DISP_COMMON_PIC_INFO_PVRIC_ENABLE_MASK) /*! @} */ /*! @name CMD_SET_FB_PIC_INFO - DPB information */ /*! @{ */ #define VPU_CMD_SET_FB_PIC_INFO_CHROMA_BIT_DEPTH_MASK (0x1E0000U) #define VPU_CMD_SET_FB_PIC_INFO_CHROMA_BIT_DEPTH_SHIFT (17U) #define VPU_CMD_SET_FB_PIC_INFO_CHROMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_PIC_INFO_CHROMA_BIT_DEPTH_SHIFT)) & VPU_CMD_SET_FB_PIC_INFO_CHROMA_BIT_DEPTH_MASK) #define VPU_CMD_SET_FB_PIC_INFO_LUMA_BIT_DEPTH_MASK (0x1E00000U) #define VPU_CMD_SET_FB_PIC_INFO_LUMA_BIT_DEPTH_SHIFT (21U) #define VPU_CMD_SET_FB_PIC_INFO_LUMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_PIC_INFO_LUMA_BIT_DEPTH_SHIFT)) & VPU_CMD_SET_FB_PIC_INFO_LUMA_BIT_DEPTH_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_COMMON_PIC_INFO - DPB information */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_CHROMA_BIT_DEPTH_MASK (0x1E0000U) #define VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_CHROMA_BIT_DEPTH_SHIFT (17U) #define VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_CHROMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_CHROMA_BIT_DEPTH_SHIFT)) & VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_CHROMA_BIT_DEPTH_MASK) #define VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_LUMA_BIT_DEPTH_MASK (0x1E00000U) #define VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_LUMA_BIT_DEPTH_SHIFT (21U) #define VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_LUMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_LUMA_BIT_DEPTH_SHIFT)) & VPU_CMD_SET_FB_UPDATE_COMMON_PIC_INFO_LUMA_BIT_DEPTH_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_0 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_0_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_0_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_0_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_0_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_0_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_0 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_0_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_0_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_0_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_0_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_0_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_WORK_BUF_SIZE - Work buffer size */ /*! @{ */ #define VPU_CMD_CREATE_INST_WORK_BUF_SIZE_WORK_BUF_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_WORK_BUF_SIZE_WORK_BUF_SIZE_SHIFT (0U) #define VPU_CMD_CREATE_INST_WORK_BUF_SIZE_WORK_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_WORK_BUF_SIZE_WORK_BUF_SIZE_SHIFT)) & VPU_CMD_CREATE_INST_WORK_BUF_SIZE_WORK_BUF_SIZE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_USERDATA_SIZE - User Data Buffer Size */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_USERDATA_SIZE_USER_DATA_BUF_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_USERDATA_SIZE_USER_DATA_BUF_SIZE_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_USERDATA_SIZE_USER_DATA_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_USERDATA_SIZE_USER_DATA_BUF_SIZE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_USERDATA_SIZE_USER_DATA_BUF_SIZE_MASK) /*! @} */ /*! @name CMD_DEC_PIC_BS_WR_PTR - Bistream Buffer Write Pointer */ /*! @{ */ #define VPU_CMD_DEC_PIC_BS_WR_PTR_WR_PTR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_PIC_BS_WR_PTR_WR_PTR_SHIFT (0U) #define VPU_CMD_DEC_PIC_BS_WR_PTR_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_BS_WR_PTR_WR_PTR_SHIFT)) & VPU_CMD_DEC_PIC_BS_WR_PTR_WR_PTR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_WR_PTR - bitstream buffer write pointer */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_WR_PTR_WR_PTR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_WR_PTR_WR_PTR_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_WR_PTR_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_WR_PTR_WR_PTR_SHIFT)) & VPU_CMD_ENC_GET_RESULT_WR_PTR_WR_PTR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_BS_SIZE - Bitstream buffer size */ /*! @{ */ #define VPU_CMD_ENC_PIC_BS_SIZE_BS_BUF_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_BS_SIZE_BS_BUF_SIZE_SHIFT (0U) #define VPU_CMD_ENC_PIC_BS_SIZE_BS_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_BS_SIZE_BS_BUF_SIZE_SHIFT)) & VPU_CMD_ENC_PIC_BS_SIZE_BS_BUF_SIZE_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_SRC_SIZE - A size of source picture */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_WIDTH_MASK (0xFFFFU) #define VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_WIDTH_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_WIDTH_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_WIDTH_MASK) #define VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_HEIGHT_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_HEIGHT_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_HEIGHT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SRC_SIZE_SRC_HEIGHT_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO - Color Sample Information */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_MASK (0xFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_MASK (0xF0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_SHIFT (4U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_MASK (0xF00U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_SHIFT (8U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_MASK (0x1000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_SHIFT (12U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_MASK (0xFF0000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_SHIFT (16U) #define VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_BS_WR_PTR - Bitstream buffer write pointer */ /*! @{ */ #define VPU_CMD_INIT_SEQ_BS_WR_PTR_WR_PTR_MASK (0xFFFFFFFFU) #define VPU_CMD_INIT_SEQ_BS_WR_PTR_WR_PTR_SHIFT (0U) #define VPU_CMD_INIT_SEQ_BS_WR_PTR_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_BS_WR_PTR_WR_PTR_SHIFT)) & VPU_CMD_INIT_SEQ_BS_WR_PTR_WR_PTR_MASK) /*! @} */ /*! @name CMD_SET_DISP_PIC_SIZE - Picture size parsed form stream */ /*! @{ */ #define VPU_CMD_SET_DISP_PIC_SIZE_PIC_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_SET_DISP_PIC_SIZE_PIC_HEIGHT_SHIFT (0U) #define VPU_CMD_SET_DISP_PIC_SIZE_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_PIC_SIZE_PIC_HEIGHT_SHIFT)) & VPU_CMD_SET_DISP_PIC_SIZE_PIC_HEIGHT_MASK) #define VPU_CMD_SET_DISP_PIC_SIZE_PIC_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_SET_DISP_PIC_SIZE_PIC_WIDTH_SHIFT (16U) #define VPU_CMD_SET_DISP_PIC_SIZE_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_PIC_SIZE_PIC_WIDTH_SHIFT)) & VPU_CMD_SET_DISP_PIC_SIZE_PIC_WIDTH_MASK) /*! @} */ /*! @name CMD_SET_FB_PIC_SIZE - Decoded picture size */ /*! @{ */ #define VPU_CMD_SET_FB_PIC_SIZE_PIC_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_SET_FB_PIC_SIZE_PIC_HEIGHT_SHIFT (0U) #define VPU_CMD_SET_FB_PIC_SIZE_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_PIC_SIZE_PIC_HEIGHT_SHIFT)) & VPU_CMD_SET_FB_PIC_SIZE_PIC_HEIGHT_MASK) #define VPU_CMD_SET_FB_PIC_SIZE_PIC_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_SET_FB_PIC_SIZE_PIC_WIDTH_SHIFT (16U) #define VPU_CMD_SET_FB_PIC_SIZE_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_PIC_SIZE_PIC_WIDTH_SHIFT)) & VPU_CMD_SET_FB_PIC_SIZE_PIC_WIDTH_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_PIC_SIZE - FBC Picture Size */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_HEIGHT_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_HEIGHT_SHIFT)) & VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_HEIGHT_MASK) #define VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_WIDTH_SHIFT (16U) #define VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_WIDTH_SHIFT)) & VPU_CMD_SET_FB_UPDATE_PIC_SIZE_PIC_WIDTH_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_1 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_1_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_1_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_PIC_BS_OPTION - Bitstream buffer option */ /*! @{ */ #define VPU_CMD_DEC_PIC_BS_OPTION_EXPLICIT_END_MASK (0x1U) #define VPU_CMD_DEC_PIC_BS_OPTION_EXPLICIT_END_SHIFT (0U) #define VPU_CMD_DEC_PIC_BS_OPTION_EXPLICIT_END(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_BS_OPTION_EXPLICIT_END_SHIFT)) & VPU_CMD_DEC_PIC_BS_OPTION_EXPLICIT_END_MASK) #define VPU_CMD_DEC_PIC_BS_OPTION_STREAM_END_MASK (0x2U) #define VPU_CMD_DEC_PIC_BS_OPTION_STREAM_END_SHIFT (1U) #define VPU_CMD_DEC_PIC_BS_OPTION_STREAM_END(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_BS_OPTION_STREAM_END_SHIFT)) & VPU_CMD_DEC_PIC_BS_OPTION_STREAM_END_MASK) #define VPU_CMD_DEC_PIC_BS_OPTION_STREAM_FORMAT_MASK (0xCU) #define VPU_CMD_DEC_PIC_BS_OPTION_STREAM_FORMAT_SHIFT (2U) #define VPU_CMD_DEC_PIC_BS_OPTION_STREAM_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_BS_OPTION_STREAM_FORMAT_SHIFT)) & VPU_CMD_DEC_PIC_BS_OPTION_STREAM_FORMAT_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_NUM_REQUIRED_FB - Minimum number of reference frame buffer required for encoding */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_FB_RET_MIN_FB_BUF_NUM_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_FB_RET_MIN_FB_BUF_NUM_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_FB_RET_MIN_FB_BUF_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_FB_RET_MIN_FB_BUF_NUM_SHIFT)) & VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_FB_RET_MIN_FB_BUF_NUM_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_MAP_ENDIAN - Custom map endianness */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_MAP_ENDIAN_CUSTOM_MAP_ENDIAN_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_MAP_ENDIAN_CUSTOM_MAP_ENDIAN_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_MAP_ENDIAN_CUSTOM_MAP_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_MAP_ENDIAN_CUSTOM_MAP_ENDIAN_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_MAP_ENDIAN_CUSTOM_MAP_ENDIAN_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO - Sample Aspect Ratio */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_HEIGHT_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_HEIGHT_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_HEIGHT_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_WIDTH_SHIFT (16U) #define VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_WIDTH_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_ASPECT_RATIO_SAR_WIDTH_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_BS_OPTION - Bitstream buffer option */ /*! @{ */ #define VPU_CMD_INIT_SEQ_BS_OPTION_EXPLICIT_END_MASK (0x1U) #define VPU_CMD_INIT_SEQ_BS_OPTION_EXPLICIT_END_SHIFT (0U) #define VPU_CMD_INIT_SEQ_BS_OPTION_EXPLICIT_END(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_BS_OPTION_EXPLICIT_END_SHIFT)) & VPU_CMD_INIT_SEQ_BS_OPTION_EXPLICIT_END_MASK) #define VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_END_MASK (0x2U) #define VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_END_SHIFT (1U) #define VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_END(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_END_SHIFT)) & VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_END_MASK) #define VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_FORMAT_MASK (0xCU) #define VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_FORMAT_SHIFT (2U) #define VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_FORMAT_SHIFT)) & VPU_CMD_INIT_SEQ_BS_OPTION_STREAM_FORMAT_MASK) /*! @} */ /*! @name CMD_SET_DISP_PIC_INFO - Input DPB information */ /*! @{ */ #define VPU_CMD_SET_DISP_PIC_INFO_STREAM_CHROMA_FOMAT_IDC_MASK (0x30000U) #define VPU_CMD_SET_DISP_PIC_INFO_STREAM_CHROMA_FOMAT_IDC_SHIFT (16U) #define VPU_CMD_SET_DISP_PIC_INFO_STREAM_CHROMA_FOMAT_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_PIC_INFO_STREAM_CHROMA_FOMAT_IDC_SHIFT)) & VPU_CMD_SET_DISP_PIC_INFO_STREAM_CHROMA_FOMAT_IDC_MASK) #define VPU_CMD_SET_DISP_PIC_INFO_CHROMA_BIT_DEPTH_MASK (0x3C0000U) #define VPU_CMD_SET_DISP_PIC_INFO_CHROMA_BIT_DEPTH_SHIFT (18U) #define VPU_CMD_SET_DISP_PIC_INFO_CHROMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_PIC_INFO_CHROMA_BIT_DEPTH_SHIFT)) & VPU_CMD_SET_DISP_PIC_INFO_CHROMA_BIT_DEPTH_MASK) #define VPU_CMD_SET_DISP_PIC_INFO_LUMA_BIT_DEPTH_MASK (0x3C00000U) #define VPU_CMD_SET_DISP_PIC_INFO_LUMA_BIT_DEPTH_SHIFT (22U) #define VPU_CMD_SET_DISP_PIC_INFO_LUMA_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_PIC_INFO_LUMA_BIT_DEPTH_SHIFT)) & VPU_CMD_SET_DISP_PIC_INFO_LUMA_BIT_DEPTH_MASK) /*! @} */ /*! @name CMD_SET_FB_NUM - The number of start/end frame buffer to set */ /*! @{ */ #define VPU_CMD_SET_FB_NUM_COL_FB_END_IDX_MASK (0x1FU) #define VPU_CMD_SET_FB_NUM_COL_FB_END_IDX_SHIFT (0U) #define VPU_CMD_SET_FB_NUM_COL_FB_END_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_NUM_COL_FB_END_IDX_SHIFT)) & VPU_CMD_SET_FB_NUM_COL_FB_END_IDX_MASK) #define VPU_CMD_SET_FB_NUM_COL_FB_START_IDX_MASK (0x3E0U) #define VPU_CMD_SET_FB_NUM_COL_FB_START_IDX_SHIFT (5U) #define VPU_CMD_SET_FB_NUM_COL_FB_START_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_NUM_COL_FB_START_IDX_SHIFT)) & VPU_CMD_SET_FB_NUM_COL_FB_START_IDX_MASK) #define VPU_CMD_SET_FB_NUM_FBC_FB_END_IDX_MASK (0x1F0000U) #define VPU_CMD_SET_FB_NUM_FBC_FB_END_IDX_SHIFT (16U) #define VPU_CMD_SET_FB_NUM_FBC_FB_END_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_NUM_FBC_FB_END_IDX_SHIFT)) & VPU_CMD_SET_FB_NUM_FBC_FB_END_IDX_MASK) #define VPU_CMD_SET_FB_NUM_FBC_FB_START_IDX_MASK (0x1F000000U) #define VPU_CMD_SET_FB_NUM_FBC_FB_START_IDX_SHIFT (24U) #define VPU_CMD_SET_FB_NUM_FBC_FB_START_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_NUM_FBC_FB_START_IDX_SHIFT)) & VPU_CMD_SET_FB_NUM_FBC_FB_START_IDX_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_2 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_2_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_2_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_2_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_2_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_2_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_2 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_2_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_2_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_2_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_2_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_2_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_BS_RD_PTR - Bitstream buffer read pointer */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_BS_RD_PTR_BS_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_BS_RD_PTR_BS_RD_PTR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_BS_RD_PTR_BS_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_BS_RD_PTR_BS_RD_PTR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_BS_RD_PTR_BS_RD_PTR_MASK) /*! @} */ /*! @name CMD_DEC_PIC_USE_SEC_AXI - Secondary AXI usage option */ /*! @{ */ #define VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_MASK (0x1U) #define VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_SHIFT (0U) #define VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_SHIFT)) & VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_MASK) #define VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_IP_ROW_MASK (0x2U) #define VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_IP_ROW_SHIFT (1U) #define VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_IP_ROW(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_IP_ROW_SHIFT)) & VPU_CMD_DEC_PIC_USE_SEC_AXI_SEC_AXI_IP_ROW_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM - Minimum number of source frame buffer required for encoding */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_SHIFT)) & VPU_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_CMD_ENC_GET_RESULT_MIN_SRC_BUF_NUM_MASK) /*! @} */ /*! @name CMD_ENC_PIC_USE_SEC_AXI - Secondary AXI usage option */ /*! @{ */ #define VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_MASK (0x1U) #define VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_SHIFT (0U) #define VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_SHIFT)) & VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_LF_ROW_MASK) #define VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_RDO_ENABLE_MASK (0x2U) #define VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_RDO_ENABLE_SHIFT (1U) #define VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_RDO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_RDO_ENABLE_SHIFT)) & VPU_CMD_ENC_PIC_USE_SEC_AXI_SEC_AXI_RDO_ENABLE_MASK) /*! @} */ /*! @name CMD_ENC_SET_FB_FBC_STRIDE - Frame buffer setting for compressed frame */ /*! @{ */ #define VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_CHROMA_STRIDE_MASK (0xFFFFU) #define VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_CHROMA_STRIDE_SHIFT (0U) #define VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_CHROMA_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_CHROMA_STRIDE_SHIFT)) & VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_CHROMA_STRIDE_MASK) #define VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_LUMA_STRIDE_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_LUMA_STRIDE_SHIFT (16U) #define VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_LUMA_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_LUMA_STRIDE_SHIFT)) & VPU_CMD_ENC_SET_FB_FBC_STRIDE_FBC_LUMA_STRIDE_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_SPS_PARAM - Encoder sequence parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_PROFILE_IDC_MASK (0x7U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_PROFILE_IDC_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_PROFILE_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_PROFILE_IDC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_PROFILE_IDC_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_LEVEL_IDC_MASK (0xFF8U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_LEVEL_IDC_SHIFT (3U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_LEVEL_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_LEVEL_IDC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_LEVEL_IDC_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_TIER_IDC_MASK (0x3000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_TIER_IDC_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_TIER_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_TIER_IDC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_TIER_IDC_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_BIT_DEPTH_MASK (0x7C000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_BIT_DEPTH_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_BIT_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_BIT_DEPTH_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_BIT_DEPTH_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_LONG_TERM_MASK (0x200000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_LONG_TERM_SHIFT (21U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_LONG_TERM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_LONG_TERM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_LONG_TERM_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_TMVP_MASK (0x800000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_TMVP_SHIFT (23U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_TMVP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_TMVP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_TMVP_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_SAO_MASK (0x1000000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_SAO_SHIFT (24U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_SAO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_SAO_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_SAO_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_INTRA_TRANS_SKIP_MASK (0x6000000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_INTRA_TRANS_SKIP_SHIFT (25U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_INTRA_TRANS_SKIP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_INTRA_TRANS_SKIP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_INTRA_TRANS_SKIP_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_STRONG_INTRA_MASK (0x8000000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_STRONG_INTRA_SHIFT (27U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_STRONG_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_STRONG_INTRA_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_STRONG_INTRA_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_STILL_PICTURE_MASK (0x40000000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_STILL_PICTURE_SHIFT (30U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_STILL_PICTURE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_STILL_PICTURE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_STILL_PICTURE_MASK) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_DEFAULT_SCALING_LIST_MASK (0x80000000U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_DEFAULT_SCALING_LIST_SHIFT (31U) #define VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_DEFAULT_SCALING_LIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_DEFAULT_SCALING_LIST_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SPS_PARAM_USE_DEFAULT_SCALING_LIST_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_BIT_RATE - Maximum Bit Rate */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_BIT_RATE_MAX_BIT_RATE_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_BIT_RATE_MAX_BIT_RATE_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_BIT_RATE_MAX_BIT_RATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_BIT_RATE_MAX_BIT_RATE_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_BIT_RATE_MAX_BIT_RATE_MASK) /*! @} */ /*! @name CMD_SET_DISP_ADDR_Y_BASE - Luma base */ /*! @{ */ #define VPU_CMD_SET_DISP_ADDR_Y_BASE_LUMA_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_DISP_ADDR_Y_BASE_LUMA_BASE_SHIFT (0U) #define VPU_CMD_SET_DISP_ADDR_Y_BASE_LUMA_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_ADDR_Y_BASE_LUMA_BASE_SHIFT)) & VPU_CMD_SET_DISP_ADDR_Y_BASE_LUMA_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_3 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_3_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_3_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_3_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_3_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_3_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_3 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_3_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_3_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_3_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_3_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_3_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_BS_PARAM - Bitstream buffer param */ /*! @{ */ #define VPU_CMD_CREATE_INST_BS_PARAM_BS_ENDIAN_MASK (0xFU) #define VPU_CMD_CREATE_INST_BS_PARAM_BS_ENDIAN_SHIFT (0U) #define VPU_CMD_CREATE_INST_BS_PARAM_BS_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_BS_PARAM_BS_ENDIAN_SHIFT)) & VPU_CMD_CREATE_INST_BS_PARAM_BS_ENDIAN_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_SEQ_PARAM - Bitstream sequence parameter information */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_LEVEL_IDC_MASK (0xFFU) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_LEVEL_IDC_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_LEVEL_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_LEVEL_IDC_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_LEVEL_IDC_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_MASK (0x100U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_SHIFT (8U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_FRAME_ONLY_CONSTRAINT_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_MASK (0x200U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_SHIFT (9U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_NON_PACKED_CONSTRAINT_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_INTERLACE_SOURCE_FLAG_MASK (0x400U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_INTERLACE_SOURCE_FLAG_SHIFT (10U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_INTERLACE_SOURCE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_INTERLACE_SOURCE_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_INTERLACE_SOURCE_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROGRESS_SOURCE_FLAG_MASK (0x800U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROGRESS_SOURCE_FLAG_SHIFT (11U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROGRESS_SOURCE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROGRESS_SOURCE_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROGRESS_SOURCE_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_MASK (0xFF000U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_SHIFT (12U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_COMPATIBILITY_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_SPS_MAX_SUB_LAYER_MASK (0xE00000U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_SPS_MAX_SUB_LAYER_SHIFT (21U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_SPS_MAX_SUB_LAYER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_SPS_MAX_SUB_LAYER_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_SPS_MAX_SUB_LAYER_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_IDC_MASK (0x1F000000U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_IDC_SHIFT (24U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_IDC_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_IDC_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_TIER_FLAG_MASK (0x20000000U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_TIER_FLAG_SHIFT (29U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_TIER_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_TIER_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_TIER_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_SPACE_MASK (0xC0000000U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_SPACE_SHIFT (30U) #define VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_SPACE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_SPACE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_SEQ_PARAM_PROFILE_SPACE_MASK) /*! @} */ /*! @name CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG - Sequence change flag */ /*! @{ */ #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_PROFILE_MASK (0x20U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_PROFILE_SHIFT (5U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_PROFILE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_PROFILE_SHIFT)) & VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_PROFILE_MASK) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_CHROMA_FORMAT_MASK (0x8000U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_CHROMA_FORMAT_SHIFT (15U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_CHROMA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_CHROMA_FORMAT_SHIFT)) & VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_CHROMA_FORMAT_MASK) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_SIZE_MASK (0x10000U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_SIZE_SHIFT (16U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_SIZE_SHIFT)) & VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_SIZE_MASK) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_INTER_RES_CHANGE_MASK (0x20000U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_INTER_RES_CHANGE_SHIFT (17U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_INTER_RES_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_INTER_RES_CHANGE_SHIFT)) & VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_INTER_RES_CHANGE_MASK) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_BITDEPTH_MASK (0x40000U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_BITDEPTH_SHIFT (18U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_BITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_BITDEPTH_SHIFT)) & VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_SEQ_CHANGE_ENABLE_FLAG_BITDEPTH_MASK) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_DEC_TEMP_ID_MODE_MASK (0x80000U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_DEC_TEMP_ID_MODE_SHIFT (19U) #define VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_DEC_TEMP_ID_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_DEC_TEMP_ID_MODE_SHIFT)) & VPU_CMD_DEC_PIC_SEQ_CHANGE_ENABLE_FLAG_DEC_TEMP_ID_MODE_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_TYPE - Encoded picture type */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_TYPE_PIC_TYPE_MASK (0xFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_TYPE_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_TYPE_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_TYPE_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_TYPE_PIC_TYPE_MASK) /*! @} */ /*! @name CMD_ENC_PIC_REPORT_PARAM - Report parameters */ /*! @{ */ #define VPU_CMD_ENC_PIC_REPORT_PARAM_ENABLE_HISTO_EN_MASK (0x2U) #define VPU_CMD_ENC_PIC_REPORT_PARAM_ENABLE_HISTO_EN_SHIFT (1U) #define VPU_CMD_ENC_PIC_REPORT_PARAM_ENABLE_HISTO_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_REPORT_PARAM_ENABLE_HISTO_EN_SHIFT)) & VPU_CMD_ENC_PIC_REPORT_PARAM_ENABLE_HISTO_EN_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_PPS_PARAM - encoder picture parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CONSTRAINED_INTRA_PRED_MASK (0x2U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CONSTRAINED_INTRA_PRED_SHIFT (1U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CONSTRAINED_INTRA_PRED(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CONSTRAINED_INTRA_PRED_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CONSTRAINED_INTRA_PRED_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_LF_CROSS_SLICE_BOUNDARY_MASK (0x4U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_LF_CROSS_SLICE_BOUNDARY_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_LF_CROSS_SLICE_BOUNDARY(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_LF_CROSS_SLICE_BOUNDARY_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_LF_CROSS_SLICE_BOUNDARY_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_DISABLE_DBK_MASK (0x20U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_DISABLE_DBK_SHIFT (5U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_DISABLE_DBK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_DISABLE_DBK_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_DISABLE_DBK_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_BETA_OFFSET_DIV2_MASK (0x3C0U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_BETA_OFFSET_DIV2_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_BETA_OFFSET_DIV2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_BETA_OFFSET_DIV2_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_BETA_OFFSET_DIV2_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_TC_OFFSET_DIV2_MASK (0x3C00U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_TC_OFFSET_DIV2_SHIFT (10U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_TC_OFFSET_DIV2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_TC_OFFSET_DIV2_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_TC_OFFSET_DIV2_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CB_QP_OFFSET_MASK (0x7C000U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CB_QP_OFFSET_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CB_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CB_QP_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CB_QP_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CR_QP_OFFSET_MASK (0xF80000U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CR_QP_OFFSET_SHIFT (19U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CR_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CR_QP_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_CR_QP_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_TRANSFORM_8x8_MASK (0x20000000U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_TRANSFORM_8x8_SHIFT (29U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_TRANSFORM_8x8(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_TRANSFORM_8x8_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_TRANSFORM_8x8_MASK) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_ENTROPY_CODING_MODE_MASK (0x40000000U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_ENTROPY_CODING_MODE_SHIFT (30U) #define VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_ENTROPY_CODING_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_ENTROPY_CODING_MODE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_PPS_PARAM_USE_ENTROPY_CODING_MODE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_NR - Frame Rate Numerator */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_NR_FRAME_RATE_NR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_NR_FRAME_RATE_NR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_NR_FRAME_RATE_NR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_NR_FRAME_RATE_NR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_NR_FRAME_RATE_NR_MASK) /*! @} */ /*! @name CMD_SET_DISP_ADDR_CB_BASE - Cb base */ /*! @{ */ #define VPU_CMD_SET_DISP_ADDR_CB_BASE_CB_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_DISP_ADDR_CB_BASE_CB_BASE_SHIFT (0U) #define VPU_CMD_SET_DISP_ADDR_CB_BASE_CB_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_ADDR_CB_BASE_CB_BASE_SHIFT)) & VPU_CMD_SET_DISP_ADDR_CB_BASE_CB_BASE_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y0 - Luma base of index0 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y0_LUMA_BASE0_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y0_LUMA_BASE0_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y0_LUMA_BASE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y0_LUMA_BASE0_SHIFT)) & VPU_CMD_SET_FB_FBC_Y0_LUMA_BASE0_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_FBC_Y - Luma base of FBC idx to be update */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_FBC_Y_FBC_LUMA_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_UPDATE_FBC_Y_FBC_LUMA_BASE_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_FBC_Y_FBC_LUMA_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_FBC_Y_FBC_LUMA_BASE_SHIFT)) & VPU_CMD_SET_FB_UPDATE_FBC_Y_FBC_LUMA_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_4 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_4_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_4_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_4_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_4_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_4_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_4 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_4_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_4_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_4_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_4_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_4_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO - Color Sample Information */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_MASK (0xFU) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_SHIFT)) & VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_LUMA_MASK) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_MASK (0xF0U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_SHIFT (4U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_SHIFT)) & VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_BIT_DEPTH_CHROMA_MASK) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_MASK (0xF00U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_SHIFT (8U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_SHIFT)) & VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_COLOR_FORMAT_IDC_MASK) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_MASK (0x1000U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_SHIFT (12U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_LF_PIC_DBK_DISABLE_MASK) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_MASK (0xFF0000U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_SHIFT (16U) #define VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_SHIFT)) & VPU_CMD_DEC_GET_RESULT_COLOR_SAMPLE_INFO_ASPECT_RATIO_IDC_MASK) /*! @} */ /*! @name CMD_DEC_PIC_USERDATA_MASK - User Data Mask */ /*! @{ */ #define VPU_CMD_DEC_PIC_USERDATA_MASK_REPORT_VUI_MASK (0x4U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_REPORT_VUI_SHIFT (2U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_REPORT_VUI(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_REPORT_VUI_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_REPORT_VUI_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_PIC_TIMING_MASK (0x10U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_PIC_TIMING_SHIFT (4U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_PIC_TIMING(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_PIC_TIMING_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_PIC_TIMING_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK (0x20U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT (5U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_MASK (0x40U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_SHIFT (6U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK (0x80U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT (7U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_MASK (0x100U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_SHIFT (8U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_MASK (0x400U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_SHIFT (10U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_MASK (0x800U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_SHIFT (11U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_MASK (0x1000U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_SHIFT (12U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_TONE_MAPPING_INFO_MASK (0x2000U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_TONE_MAPPING_INFO_SHIFT (13U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_TONE_MAPPING_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_TONE_MAPPING_INFO_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_TONE_MAPPING_INFO_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_MASK (0x4000U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_SHIFT (14U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_MASK (0x8000U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_SHIFT (15U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_MASK) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_MASK (0x10000U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_SHIFT (16U) #define VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_POC - A POC value of encoded picture */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_POC_PIC_POC_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_POC_PIC_POC_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_POC_PIC_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_POC_PIC_POC_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_POC_PIC_POC_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_GOP_PARAM - GOP parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_GOP_PRESET_IDX_MASK (0xFFU) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_GOP_PRESET_IDX_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_GOP_PRESET_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_GOP_PARAM_GOP_PRESET_IDX_SHIFT)) & VPU_CMD_ENC_SET_PARAM_GOP_PARAM_GOP_PRESET_IDX_MASK) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_0_QP_MASK (0x100U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_0_QP_SHIFT (8U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_0_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_0_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_0_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_1_QP_MASK (0x200U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_1_QP_SHIFT (9U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_1_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_1_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_1_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_2_QP_MASK (0x400U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_2_QP_SHIFT (10U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_2_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_2_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_2_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_3_QP_MASK (0x800U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_3_QP_SHIFT (11U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_3_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_3_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_GOP_PARAM_EN_TEMPORAL_LAYER_3_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_TEMPORAL_LAYER_COUNT_MASK (0xF0000U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_TEMPORAL_LAYER_COUNT_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_GOP_PARAM_TEMPORAL_LAYER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_GOP_PARAM_TEMPORAL_LAYER_COUNT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_GOP_PARAM_TEMPORAL_LAYER_COUNT_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_DR - Frame Rate Denominator */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_DR_FRAME_RATE_DR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_DR_FRAME_RATE_DR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_DR_FRAME_RATE_DR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_DR_FRAME_RATE_DR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_FRAME_RATE_DR_FRAME_RATE_DR_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_SEI_MASK - User Data Mask */ /*! @{ */ #define VPU_CMD_INIT_SEQ_SEI_MASK_REPORT_VUI_MASK (0x4U) #define VPU_CMD_INIT_SEQ_SEI_MASK_REPORT_VUI_SHIFT (2U) #define VPU_CMD_INIT_SEQ_SEI_MASK_REPORT_VUI(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_REPORT_VUI_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_REPORT_VUI_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_PIC_TIMING_MASK (0x10U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_PIC_TIMING_SHIFT (4U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_PIC_TIMING(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_PIC_TIMING_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_PIC_TIMING_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK (0x20U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT (5U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_MASK (0x40U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_SHIFT (6U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_USER_DATA_UNREGISTERED_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK (0x80U) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT (7U) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_REGISTERED_ITU_T_T35_0_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_MASK (0x100U) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_SHIFT (8U) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_USER_DATA_UNREGISTERED_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_MASK (0x400U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_SHIFT (10U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_MASTERING_DISPLAY_COLOUR_VOLUME_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_MASK (0x800U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_SHIFT (11U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CHROMA_RESAMPLING_FILTER_HINT_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_MASK (0x1000U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_SHIFT (12U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_KNEE_FUNCTION_INFO_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_TONE_MAPPING_INFO_MASK (0x2000U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_TONE_MAPPING_INFO_SHIFT (13U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_TONE_MAPPING_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_TONE_MAPPING_INFO_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_TONE_MAPPING_INFO_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_MASK (0x4000U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_SHIFT (14U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_FILM_GRAIN_CHARACTERISTICS_INFO_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_MASK (0x8000U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_SHIFT (15U) #define VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_PREFIX_SEI_CONTENT_LIGHT_LEVEL_INFO_MASK) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_MASK (0x10000U) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_SHIFT (16U) #define VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_SHIFT)) & VPU_CMD_INIT_SEQ_SEI_MASK_SUFFIX_SEI_COLOUR_REAMPPING_INFO_MASK) /*! @} */ /*! @name CMD_SET_DISP_ADDR_CR_BASE - Cr base */ /*! @{ */ #define VPU_CMD_SET_DISP_ADDR_CR_BASE_CR_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_DISP_ADDR_CR_BASE_CR_BASE_SHIFT (0U) #define VPU_CMD_SET_DISP_ADDR_CR_BASE_CR_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_ADDR_CR_BASE_CR_BASE_SHIFT)) & VPU_CMD_SET_DISP_ADDR_CR_BASE_CR_BASE_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C0 - Cb base of index0 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C0_CB_BASE0_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C0_CB_BASE0_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C0_CB_BASE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C0_CB_BASE0_SHIFT)) & VPU_CMD_SET_FB_FBC_C0_CB_BASE0_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_FBC_C - Cb base of FBC idx to be update */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_FBC_C_FBC_CHROMA_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_UPDATE_FBC_C_FBC_CHROMA_BASE_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_FBC_C_FBC_CHROMA_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_FBC_C_FBC_CHROMA_BASE_SHIFT)) & VPU_CMD_SET_FB_UPDATE_FBC_C_FBC_CHROMA_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_5 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_5_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_5_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_5_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_5_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_5_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_5 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_5_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_5_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_5_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_5_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_5_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_ADDR_EXT - AXI Address Extension */ /*! @{ */ #define VPU_CMD_CREATE_INST_ADDR_EXT_EXT_ADDR_MASK (0xFFU) #define VPU_CMD_CREATE_INST_ADDR_EXT_EXT_ADDR_SHIFT (0U) #define VPU_CMD_CREATE_INST_ADDR_EXT_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_ADDR_EXT_EXT_ADDR_SHIFT)) & VPU_CMD_CREATE_INST_ADDR_EXT_EXT_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_ASPECT_RATIO - Sample Aspect Ratio */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_HEIGHT_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_HEIGHT_SHIFT)) & VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_HEIGHT_MASK) #define VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_WIDTH_SHIFT (16U) #define VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_WIDTH_SHIFT)) & VPU_CMD_DEC_GET_RESULT_ASPECT_RATIO_SAR_WIDTH_MASK) /*! @} */ /*! @name CMD_DEC_PIC_TEMPORAL_ID_PLUS1 - Max Decode Temporal ID */ /*! @{ */ #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_TEMP_ID_PLUS1_MASK (0xFFU) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_TEMP_ID_PLUS1_SHIFT (0U) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_TEMP_ID_PLUS1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_TEMP_ID_PLUS1_SHIFT)) & VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_TEMP_ID_PLUS1_MASK) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_DEC_TEMP_ID_MODE_MASK (0x100U) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_DEC_TEMP_ID_MODE_SHIFT (8U) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_DEC_TEMP_ID_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_DEC_TEMP_ID_MODE_SHIFT)) & VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_DEC_TEMP_ID_MODE_MASK) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_SPATIAL_ID_PLUS1_MASK (0xE00U) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_SPATIAL_ID_PLUS1_SHIFT (9U) #define VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_SPATIAL_ID_PLUS1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_SPATIAL_ID_PLUS1_SHIFT)) & VPU_CMD_DEC_PIC_TEMPORAL_ID_PLUS1_TARGET_DEC_SPATIAL_ID_PLUS1_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_IDX - Frame buffer index of encoded picture */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_IDX_PIC_IDX_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_IDX_PIC_IDX_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_IDX_PIC_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_IDX_PIC_IDX_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_IDX_PIC_IDX_MASK) /*! @} */ /*! @name CMD_ENC_PIC_MV_HISTO_CLASS0 - MV histogram threshold */ /*! @{ */ #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_1_MASK (0xFFFFU) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_1_SHIFT (0U) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_1_SHIFT)) & VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_1_MASK) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_0_MASK (0xFFFF0000U) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_0_SHIFT (16U) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_0_SHIFT)) & VPU_CMD_ENC_PIC_MV_HISTO_CLASS0_MV_CLASS_THRESHOLD_0_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_INTRA_PARAM - Intra picture coding parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_DECODING_REFRESH_TYPE_MASK (0x7U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_DECODING_REFRESH_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_DECODING_REFRESH_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_DECODING_REFRESH_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_DECODING_REFRESH_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_QP_MASK (0x1F8U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_QP_SHIFT (3U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_EN_FORCED_IDR_HEADER_MASK (0x600U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_EN_FORCED_IDR_HEADER_SHIFT (9U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_EN_FORCED_IDR_HEADER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_EN_FORCED_IDR_HEADER_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_EN_FORCED_IDR_HEADER_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_PERIOD_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_PERIOD_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_PERIOD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_INTRA_PERIOD_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_INTRA_PARAM_AVC - Intra picture coding parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_QP_MASK (0x3FU) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_QP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_PERIOD_MASK (0x1FFC0U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_PERIOD_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_PERIOD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_INTRA_PERIOD_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_IDR_PERIOD_MASK (0xFFE0000U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_IDR_PERIOD_SHIFT (17U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_IDR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_IDR_PERIOD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_IDR_PERIOD_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_EN_FORCED_IDR_HEADER_MASK (0x30000000U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_EN_FORCED_IDR_HEADER_SHIFT (28U) #define VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_EN_FORCED_IDR_HEADER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_EN_FORCED_IDR_HEADER_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_PARAM_AVC_EN_FORCED_IDR_HEADER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_FBC_FB - Required Number of Minimum fbc DPB */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_MASK (0x1FU) #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_MASK) /*! @} */ /*! @name CMD_SET_DISP_DEC_PP_SCL_PARAM - scaler control paramter */ /*! @{ */ #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_EN_MASK (0x1U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_EN_SHIFT (0U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_EN_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_EN_MASK) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_COEF_MODE_MASK (0x6U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_COEF_MODE_SHIFT (1U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_COEF_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_COEF_MODE_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_COEF_MODE_MASK) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_CHR_FORMAT_MASK (0x18U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_CHR_FORMAT_SHIFT (3U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_CHR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_CHR_FORMAT_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_SCL_PARAM_SCL_CHR_FORMAT_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET0 - FBC luma offset base of index0 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET0_FBC_LUMA_OFFSET_BASE0_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET0_FBC_LUMA_OFFSET_BASE0_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET0_FBC_LUMA_OFFSET_BASE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET0_FBC_LUMA_OFFSET_BASE0_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET0_FBC_LUMA_OFFSET_BASE0_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_FBC_Y_OFFSET - FBC luma offset base of updated index */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_FBC_Y_OFFSET_FBC_LUMA_OFFSET_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_UPDATE_FBC_Y_OFFSET_FBC_LUMA_OFFSET_BASE_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_FBC_Y_OFFSET_FBC_LUMA_OFFSET_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_FBC_Y_OFFSET_FBC_LUMA_OFFSET_BASE_SHIFT)) & VPU_CMD_SET_FB_UPDATE_FBC_Y_OFFSET_FBC_LUMA_OFFSET_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_6 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_6_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_6_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_6_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_6_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_6_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_6 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_6_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_6_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_6_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_6_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_6_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_DISP_MODE - Display order for BWB output */ /*! @{ */ #define VPU_CMD_CREATE_INST_DISP_MODE_DISP_MODE_MASK (0x1U) #define VPU_CMD_CREATE_INST_DISP_MODE_DISP_MODE_SHIFT (0U) #define VPU_CMD_CREATE_INST_DISP_MODE_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_DISP_MODE_DISP_MODE_SHIFT)) & VPU_CMD_CREATE_INST_DISP_MODE_DISP_MODE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_BIT_RATE - Maximum Bit Rate */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_BIT_RATE_MAX_BIT_RATE_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_BIT_RATE_MAX_BIT_RATE_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_BIT_RATE_MAX_BIT_RATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_BIT_RATE_MAX_BIT_RATE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_BIT_RATE_MAX_BIT_RATE_MASK) /*! @} */ /*! @name CMD_DEC_PIC_FORCE_FB_LATENCY_PLUS1 - User define display latency */ /*! @{ */ #define VPU_CMD_DEC_PIC_FORCE_FB_LATENCY_PLUS1_USER_DEF_DISP_LATENCY_PLUS1_MASK (0x1FU) #define VPU_CMD_DEC_PIC_FORCE_FB_LATENCY_PLUS1_USER_DEF_DISP_LATENCY_PLUS1_SHIFT (0U) #define VPU_CMD_DEC_PIC_FORCE_FB_LATENCY_PLUS1_USER_DEF_DISP_LATENCY_PLUS1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_FORCE_FB_LATENCY_PLUS1_USER_DEF_DISP_LATENCY_PLUS1_SHIFT)) & VPU_CMD_DEC_PIC_FORCE_FB_LATENCY_PLUS1_USER_DEF_DISP_LATENCY_PLUS1_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_SLICE_NUM - Number of slice */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_SLICE_NUM_PIC_SLICE_NUM_MASK (0xFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_SLICE_NUM_PIC_SLICE_NUM_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_SLICE_NUM_PIC_SLICE_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_SLICE_NUM_PIC_SLICE_NUM_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_SLICE_NUM_PIC_SLICE_NUM_MASK) /*! @} */ /*! @name CMD_ENC_PIC_MV_HISTO_CLASS1 - MV histogram threshold */ /*! @{ */ #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_3_MASK (0xFFFFU) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_3_SHIFT (0U) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_3_SHIFT)) & VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_3_MASK) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_2_MASK (0xFFFF0000U) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_2_SHIFT (16U) #define VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_2_SHIFT)) & VPU_CMD_ENC_PIC_MV_HISTO_CLASS1_MV_CLASS_THRESHOLD_2_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT - Top and bottom size for conformance window */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_TOP_MASK (0xFFFFU) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_TOP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_TOP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_TOP_MASK) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_BOTTOM_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_BOTTOM_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_BOTTOM_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CONF_WIN_TOP_BOT_CONFORMACE_WINDOW_SIZE_BOTTOM_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_NUM_REORDER_DELAY - Reorder frame number */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REORDER_DELAY_REORDER_DELAY_NUM_MASK (0x1FU) #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REORDER_DELAY_REORDER_DELAY_NUM_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REORDER_DELAY_REORDER_DELAY_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REORDER_DELAY_REORDER_DELAY_NUM_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REORDER_DELAY_REORDER_DELAY_NUM_MASK) /*! @} */ /*! @name CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE - Scaled picture size */ /*! @{ */ #define VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_HEIGHT_SHIFT (0U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_HEIGHT_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_HEIGHT_MASK) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_WIDTH_SHIFT (16U) #define VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_WIDTH_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_SCL_PIC_SIZE_PIC_WIDTH_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET0 - FBC chroma offset base of index0 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET0_FBC_CHROMA_OFFSET_BASE0_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET0_FBC_CHROMA_OFFSET_BASE0_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET0_FBC_CHROMA_OFFSET_BASE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET0_FBC_CHROMA_OFFSET_BASE0_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET0_FBC_CHROMA_OFFSET_BASE0_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_FBC_C_OFFSET - FBC chroma offset base of updated index */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_FBC_C_OFFSET_FBC_CHROMA_OFFSET_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_UPDATE_FBC_C_OFFSET_FBC_CHROMA_OFFSET_BASE_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_FBC_C_OFFSET_FBC_CHROMA_OFFSET_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_FBC_C_OFFSET_FBC_CHROMA_OFFSET_BASE_SHIFT)) & VPU_CMD_SET_FB_UPDATE_FBC_C_OFFSET_FBC_CHROMA_OFFSET_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_7 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_7_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_7_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_7_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_7_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_7_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_7 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_7_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_7_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_7_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_7_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_7_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_FRAME_RATE_NR - Frame Rate Numerator */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_FRAME_RATE_NR_FRAME_RATE_NR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_FRAME_RATE_NR_FRAME_RATE_NR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_FRAME_RATE_NR_FRAME_RATE_NR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_FRAME_RATE_NR_FRAME_RATE_NR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_FRAME_RATE_NR_FRAME_RATE_NR_MASK) /*! @} */ /*! @name CMD_DEC_PIC_USERDATA_BASE - User Data Buffer Base Address */ /*! @{ */ #define VPU_CMD_DEC_PIC_USERDATA_BASE_USER_DATA_BUF_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_PIC_USERDATA_BASE_USER_DATA_BUF_BASE_SHIFT (0U) #define VPU_CMD_DEC_PIC_USERDATA_BASE_USER_DATA_BUF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_BASE_USER_DATA_BUF_BASE_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_BASE_USER_DATA_BUF_BASE_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_SKIP - A picture skip flag */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_SKIP_PIC_SKIP_MASK (0xFEU) #define VPU_CMD_ENC_GET_RESULT_PIC_SKIP_PIC_SKIP_SHIFT (1U) #define VPU_CMD_ENC_GET_RESULT_PIC_SKIP_PIC_SKIP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_SKIP_PIC_SKIP_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_SKIP_PIC_SKIP_MASK) /*! @} */ /*! @name CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM - Custom map parameters */ /*! @{ */ #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_QP_MAP_FLAG_MASK (0x1U) #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_QP_MAP_FLAG_SHIFT (0U) #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_QP_MAP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_QP_MAP_FLAG_SHIFT)) & VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_QP_MAP_FLAG_MASK) #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_CTU_FORCE_MODE_FLAG_MASK (0x2U) #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_CTU_FORCE_MODE_FLAG_SHIFT (1U) #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_CTU_FORCE_MODE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_CTU_FORCE_MODE_FLAG_SHIFT)) & VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM_USE_CTU_FORCE_MODE_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT - Left and right size for conformance window */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_LFET_MASK (0xFFFFU) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_LFET_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_LFET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_LFET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_LFET_MASK) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_RIGHT_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_RIGHT_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_RIGHT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CONF_WIN_LEFT_RIGHT_CONFORMANCE_WINDOW_SIZE_RIGHT_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_ADDR_USERDATA_BASE - User Data Buffer Base Address */ /*! @{ */ #define VPU_CMD_INIT_SEQ_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_INIT_SEQ_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_SHIFT (0U) #define VPU_CMD_INIT_SEQ_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_SHIFT)) & VPU_CMD_INIT_SEQ_ADDR_USERDATA_BASE_USER_DATA_BUF_BASE_MASK) /*! @} */ /*! @name CMD_SET_DISP_DEC_PP_CROP_PARAM - Crop ctrl parameter */ /*! @{ */ #define VPU_CMD_SET_DISP_DEC_PP_CROP_PARAM_CROP_EN_MASK (0x1U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_PARAM_CROP_EN_SHIFT (0U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_PARAM_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_CROP_PARAM_CROP_EN_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_CROP_PARAM_CROP_EN_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL0 - info base of index0 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL0_COL_BASE0_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL0_COL_BASE0_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL0_COL_BASE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL0_COL_BASE0_SHIFT)) & VPU_CMD_SET_FB_MV_COL0_COL_BASE0_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_MV_COL - Col base of col idx to be update */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_MV_COL_COL_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_UPDATE_MV_COL_COL_BASE_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_MV_COL_COL_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_MV_COL_COL_BASE_SHIFT)) & VPU_CMD_SET_FB_UPDATE_MV_COL_COL_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_8 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_8_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_8_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_8_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_8_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_8_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_8 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_8_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_8_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_8_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_8_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_8_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_FRAME_RATE_DR - Frame Rate Denominator */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_FRAME_RATE_DR_FRAME_RATE_DR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_FRAME_RATE_DR_FRAME_RATE_DR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_FRAME_RATE_DR_FRAME_RATE_DR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_FRAME_RATE_DR_FRAME_RATE_DR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_FRAME_RATE_DR_FRAME_RATE_DR_MASK) /*! @} */ /*! @name CMD_DEC_PIC_USERDATA_SIZE - User Data Buffer Size */ /*! @{ */ #define VPU_CMD_DEC_PIC_USERDATA_SIZE_USER_DATA_BUF_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_PIC_USERDATA_SIZE_USER_DATA_BUF_SIZE_SHIFT (0U) #define VPU_CMD_DEC_PIC_USERDATA_SIZE_USER_DATA_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_SIZE_USER_DATA_BUF_SIZE_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_SIZE_USER_DATA_BUF_SIZE_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_NUM_INTRA - Number of intra block */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_INTRA_PIC_NUM_INTRA_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_INTRA_PIC_NUM_INTRA_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_INTRA_PIC_NUM_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_NUM_INTRA_PIC_NUM_INTRA_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_NUM_INTRA_PIC_NUM_INTRA_MASK) /*! @} */ /*! @name CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR - Custom map address */ /*! @{ */ #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_RDO_PARAM - RDO coding options */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_EN_HVS_QP_MASK (0x4U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_EN_HVS_QP_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_EN_HVS_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_EN_HVS_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_EN_HVS_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_ADAPTIVE_ROUNDING_MASK (0x8U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_ADAPTIVE_ROUNDING_SHIFT (3U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_ADAPTIVE_ROUNDING(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_ADAPTIVE_ROUNDING_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_ADAPTIVE_ROUNDING_MASK) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_DISABLE_COEF_CLEAR_MASK (0x10U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_DISABLE_COEF_CLEAR_SHIFT (4U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_DISABLE_COEF_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_DISABLE_COEF_CLEAR_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_DISABLE_COEF_CLEAR_MASK) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QROUND_OFFSET_MASK (0x20000U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QROUND_OFFSET_SHIFT (17U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QROUND_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QROUND_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QROUND_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_MODE_MAP_MASK (0x80000U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_MODE_MAP_SHIFT (19U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_MODE_MAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_MODE_MAP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_MODE_MAP_MASK) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QP_MAP_MASK (0x100000U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QP_MAP_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QP_MAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QP_MAP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_QP_MAP_MASK) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_ME_SEARCH_CENTER_MASK (0x200000U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_ME_SEARCH_CENTER_SHIFT (21U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_ME_SEARCH_CENTER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_ME_SEARCH_CENTER_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_ME_SEARCH_CENTER_MASK) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_LAMBDA_MASK (0x400000U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_LAMBDA_SHIFT (22U) #define VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_LAMBDA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_LAMBDA_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RDO_PARAM_USE_CUSTOM_LAMBDA_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_PIC_SIZE - Decoded Picture Size */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_HEIGHT_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_HEIGHT_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_HEIGHT_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_WIDTH_SHIFT (16U) #define VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_WIDTH_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_PIC_SIZE_DECODED_PIC_WIDTH_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_USERDATA_SIZE - User Data Buffer Size */ /*! @{ */ #define VPU_CMD_INIT_SEQ_USERDATA_SIZE_USER_DATA_BUF_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_INIT_SEQ_USERDATA_SIZE_USER_DATA_BUF_SIZE_SHIFT (0U) #define VPU_CMD_INIT_SEQ_USERDATA_SIZE_USER_DATA_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_USERDATA_SIZE_USER_DATA_BUF_SIZE_SHIFT)) & VPU_CMD_INIT_SEQ_USERDATA_SIZE_USER_DATA_BUF_SIZE_MASK) /*! @} */ /*! @name CMD_SET_DISP_DEC_PP_CROP_POS - Crop start position for output image */ /*! @{ */ #define VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_Y_MASK (0xFFFFU) #define VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_Y_SHIFT (0U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_Y_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_Y_MASK) #define VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_X_MASK (0xFFFF0000U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_X_SHIFT (16U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_X(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_X_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_CROP_POS_CROP_START_POS_X_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED0 - Sub sampled base of index0 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED0_SUB_SAMPLED_FB_BASE0_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED0_SUB_SAMPLED_FB_BASE0_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED0_SUB_SAMPLED_FB_BASE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED0_SUB_SAMPLED_FB_BASE0_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED0_SUB_SAMPLED_FB_BASE0_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_9 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_9_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_9_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_9_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_9_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_9_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_9 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_9_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_9_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_9_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_9_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_9_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_NUM_REQUIRED_FBC_FB - Required Number of Minimum fbc DPB */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_MASK (0x1FU) #define VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_SHIFT)) & VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_FBC_FB_MIN_DPB_NUM_MASK) /*! @} */ /*! @name CMD_DEC_PIC_USERDATA_PARAM - User Data Buffer Parameter */ /*! @{ */ #define VPU_CMD_DEC_PIC_USERDATA_PARAM_USER_DATA_ENDIAN_MASK (0xFU) #define VPU_CMD_DEC_PIC_USERDATA_PARAM_USER_DATA_ENDIAN_SHIFT (0U) #define VPU_CMD_DEC_PIC_USERDATA_PARAM_USER_DATA_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_USERDATA_PARAM_USER_DATA_ENDIAN_SHIFT)) & VPU_CMD_DEC_PIC_USERDATA_PARAM_USER_DATA_ENDIAN_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_NUM_MERGE - Number of merge block */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_MERGE_PIC_NUM_MERGE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_MERGE_PIC_NUM_MERGE_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_MERGE_PIC_NUM_MERGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_NUM_MERGE_PIC_NUM_MERGE_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_NUM_MERGE_PIC_NUM_MERGE_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_SLICE_PARAM - Slice parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_SLICE_MODE_MASK (0x7U) #define VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_SLICE_MODE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_SLICE_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_SLICE_MODE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_SLICE_MODE_MASK) #define VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_ARGUMENT_MASK (0xFFFFFFF8U) #define VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_ARGUMENT_SHIFT (3U) #define VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_ARGUMENT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_ARGUMENT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SLICE_PARAM_ARGUMENT_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM - Display Crop Offset Top/Bottom */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_MASK (0xFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_MASK (0xFFFF0000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_SHIFT (16U) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_MASK) /*! @} */ /*! @name CMD_INIT_SEQ_USERDATA_PARAM - User Data Buffer Parameter */ /*! @{ */ #define VPU_CMD_INIT_SEQ_USERDATA_PARAM_USER_DATA_ENDIAN_MASK (0xFU) #define VPU_CMD_INIT_SEQ_USERDATA_PARAM_USER_DATA_ENDIAN_SHIFT (0U) #define VPU_CMD_INIT_SEQ_USERDATA_PARAM_USER_DATA_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_INIT_SEQ_USERDATA_PARAM_USER_DATA_ENDIAN_SHIFT)) & VPU_CMD_INIT_SEQ_USERDATA_PARAM_USER_DATA_ENDIAN_MASK) /*! @} */ /*! @name CMD_SET_DISP_DEC_PP_CROP_SIZE - Crop size for output image */ /*! @{ */ #define VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_HEIGHT_MASK (0xFFFFU) #define VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_HEIGHT_SHIFT (0U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_HEIGHT_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_HEIGHT_MASK) #define VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_WIDTH_MASK (0xFFFF0000U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_WIDTH_SHIFT (16U) #define VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_WIDTH_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_CROP_SIZE_CROP_WIDTH_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y1 - Luma base of index1 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y1_LUMA_BASE1_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y1_LUMA_BASE1_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y1_LUMA_BASE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y1_LUMA_BASE1_SHIFT)) & VPU_CMD_SET_FB_FBC_Y1_LUMA_BASE1_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_A - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_A_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_A_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_A_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_A_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_A_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_A - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_A_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_A_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_A_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_A_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_A_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_NUM_REORDER_DELAY - Reorder frame number */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_NUM_REORDER_DELAY_REORDER_DELAY_NUM_MASK (0x1FU) #define VPU_CMD_DEC_GET_RESULT_NUM_REORDER_DELAY_REORDER_DELAY_NUM_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_NUM_REORDER_DELAY_REORDER_DELAY_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_NUM_REORDER_DELAY_REORDER_DELAY_NUM_SHIFT)) & VPU_CMD_DEC_GET_RESULT_NUM_REORDER_DELAY_REORDER_DELAY_NUM_MASK) /*! @} */ /*! @name CMD_DEC_PIC_TIMESTAMP - CMD_DEC_PIC_TIMESTAMP */ /*! @{ */ #define VPU_CMD_DEC_PIC_TIMESTAMP_timestamp_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_PIC_TIMESTAMP_timestamp_SHIFT (0U) #define VPU_CMD_DEC_PIC_TIMESTAMP_timestamp(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_PIC_TIMESTAMP_timestamp_SHIFT)) & VPU_CMD_DEC_PIC_TIMESTAMP_timestamp_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_NON_REF_PIC_FLAG - Non reference picture flag */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_NON_REF_PIC_FLAG_PIC_NON_REF_PIC_FLAG_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_NON_REF_PIC_FLAG_PIC_NON_REF_PIC_FLAG_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_NON_REF_PIC_FLAG_PIC_NON_REF_PIC_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_NON_REF_PIC_FLAG_PIC_NON_REF_PIC_FLAG_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_NON_REF_PIC_FLAG_PIC_NON_REF_PIC_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SRC_PIC_IDX - Buffer index of source picture */ /*! @{ */ #define VPU_CMD_ENC_PIC_SRC_PIC_IDX_SRC_IDX_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_SRC_PIC_IDX_SRC_IDX_SHIFT (0U) #define VPU_CMD_ENC_PIC_SRC_PIC_IDX_SRC_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_PIC_IDX_SRC_IDX_SHIFT)) & VPU_CMD_ENC_PIC_SRC_PIC_IDX_SRC_IDX_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_INTRA_REFRESH - Intra refresh mode */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_MODE_MASK (0x7U) #define VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_MODE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_MODE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_MODE_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_ARGUMENT_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_ARGUMENT_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_ARGUMENT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_ARGUMENT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_REFRESH_INTRA_REFRESH_ARGUMENT_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT - Display Crop Offset Left/Right */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_MASK (0xFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_MASK (0xFFFF0000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_SHIFT (16U) #define VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C1 - Cb base of index1 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C1_CB_BASE1_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C1_CB_BASE1_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C1_CB_BASE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C1_CB_BASE1_SHIFT)) & VPU_CMD_SET_FB_FBC_C1_CB_BASE1_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_B - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_B_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_B_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_B_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_B_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_B_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_B - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_B_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_B_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_B_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_B_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_B_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_CORE_INFO - Dual Core information */ /*! @{ */ #define VPU_CMD_CREATE_INST_CORE_INFO_NUM_CORE_MASK (0xFU) #define VPU_CMD_CREATE_INST_CORE_INFO_NUM_CORE_SHIFT (0U) #define VPU_CMD_CREATE_INST_CORE_INFO_NUM_CORE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_CORE_INFO_NUM_CORE_SHIFT)) & VPU_CMD_CREATE_INST_CORE_INFO_NUM_CORE_MASK) #define VPU_CMD_CREATE_INST_CORE_INFO_CORE_IDC_MASK (0xF0U) #define VPU_CMD_CREATE_INST_CORE_INFO_CORE_IDC_SHIFT (4U) #define VPU_CMD_CREATE_INST_CORE_INFO_CORE_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_CORE_INFO_CORE_IDC_SHIFT)) & VPU_CMD_CREATE_INST_CORE_INFO_CORE_IDC_MASK) #define VPU_CMD_CREATE_INST_CORE_INFO_SET_CQ_DEPTH_MASK (0x700U) #define VPU_CMD_CREATE_INST_CORE_INFO_SET_CQ_DEPTH_SHIFT (8U) #define VPU_CMD_CREATE_INST_CORE_INFO_SET_CQ_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_CORE_INFO_SET_CQ_DEPTH_SHIFT)) & VPU_CMD_CREATE_INST_CORE_INFO_SET_CQ_DEPTH_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_NUM_SKIP - Number of skip block */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_SKIP_PIC_NUM_SKIP_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_SKIP_PIC_NUM_SKIP_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_SKIP_PIC_NUM_SKIP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_NUM_SKIP_PIC_NUM_SKIP_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_NUM_SKIP_PIC_NUM_SKIP_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SRC_ADDR_Y - Y component source address */ /*! @{ */ #define VPU_CMD_ENC_PIC_SRC_ADDR_Y_SRC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_SRC_ADDR_Y_SRC_ADDR_Y_SHIFT (0U) #define VPU_CMD_ENC_PIC_SRC_ADDR_Y_SRC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_ADDR_Y_SRC_ADDR_Y_SHIFT)) & VPU_CMD_ENC_PIC_SRC_ADDR_Y_SRC_ADDR_Y_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP - Min/Max QP for Intra pictures */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MIN_QP_MASK (0x3FU) #define VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MIN_QP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MIN_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MIN_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MIN_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MAX_QP_MASK (0xFC0U) #define VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MAX_QP_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MAX_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MAX_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTRA_MIN_MAX_QP_I_MAX_QP_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_COL_BUF - Required Number of Minimum col buf */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_MASK (0x1FU) #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET1 - FBC luma offset base of index1 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET1_FBC_LUMA_OFFSET_BASE1_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET1_FBC_LUMA_OFFSET_BASE1_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET1_FBC_LUMA_OFFSET_BASE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET1_FBC_LUMA_OFFSET_BASE1_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET1_FBC_LUMA_OFFSET_BASE1_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_C - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_C_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_C_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_C_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_C_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_C_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_C - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_C_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_C_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_C_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_C_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_C_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_PRIORITY - Instance priority */ /*! @{ */ #define VPU_CMD_CREATE_INST_PRIORITY_PRIORITY_VALUE_MASK (0x1FU) #define VPU_CMD_CREATE_INST_PRIORITY_PRIORITY_VALUE_SHIFT (0U) #define VPU_CMD_CREATE_INST_PRIORITY_PRIORITY_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_PRIORITY_PRIORITY_VALUE_SHIFT)) & VPU_CMD_CREATE_INST_PRIORITY_PRIORITY_VALUE_MASK) #define VPU_CMD_CREATE_INST_PRIORITY_SECURITY_FLAG_MASK (0x100U) #define VPU_CMD_CREATE_INST_PRIORITY_SECURITY_FLAG_SHIFT (8U) #define VPU_CMD_CREATE_INST_PRIORITY_SECURITY_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_PRIORITY_SECURITY_FLAG_SHIFT)) & VPU_CMD_CREATE_INST_PRIORITY_SECURITY_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_AVG_CTU_QP - CTU QP on average */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_AVG_CTU_QP_PIC_AVG_CTU_QP_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_AVG_CTU_QP_PIC_AVG_CTU_QP_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_AVG_CTU_QP_PIC_AVG_CTU_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_AVG_CTU_QP_PIC_AVG_CTU_QP_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_AVG_CTU_QP_PIC_AVG_CTU_QP_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SRC_ADDR_U - Cb component source address */ /*! @{ */ #define VPU_CMD_ENC_PIC_SRC_ADDR_U_SRC_ADDR_U_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_SRC_ADDR_U_SRC_ADDR_U_SHIFT (0U) #define VPU_CMD_ENC_PIC_SRC_ADDR_U_SRC_ADDR_U(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_ADDR_U_SRC_ADDR_U_SHIFT)) & VPU_CMD_ENC_PIC_SRC_ADDR_U_SRC_ADDR_U_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_RC_FRAME_RATE - Frame rate for rate control */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_RC_FRAME_RATE_RC_FRAME_RATE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_RC_FRAME_RATE_RC_FRAME_RATE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_RC_FRAME_RATE_RC_FRAME_RATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_FRAME_RATE_RC_FRAME_RATE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_FRAME_RATE_RC_FRAME_RATE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_NOTIFICATION - Sequence change flag */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_PROFILE_MASK (0x20U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_PROFILE_SHIFT (5U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_PROFILE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_PROFILE_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_PROFILE_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_CHROMA_FORMAT_CHANGE_MASK (0x8000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_CHROMA_FORMAT_CHANGE_SHIFT (15U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_CHROMA_FORMAT_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_CHROMA_FORMAT_CHANGE_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_CHROMA_FORMAT_CHANGE_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_SIZE_MASK (0x10000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_SIZE_SHIFT (16U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_SIZE_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_SIZE_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_INTER_RES_CHANGE_MASK (0x20000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_INTER_RES_CHANGE_SHIFT (17U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_INTER_RES_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_INTER_RES_CHANGE_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_INTER_RES_CHANGE_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_BITDEPTH_MASK (0x40000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_BITDEPTH_SHIFT (18U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_BITDEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_BITDEPTH_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_BITDEPTH_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_DPB_COUNT_MASK (0x80000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_DPB_COUNT_SHIFT (19U) #define VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_DPB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_DPB_COUNT_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_NOTIFICATION_NOTI_FLAG_DPB_COUNT_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET1 - FBC chroma offset base of index1 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET1_FBC_CHROMA_OFFSET_BASE1_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET1_FBC_CHROMA_OFFSET_BASE1_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET1_FBC_CHROMA_OFFSET_BASE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET1_FBC_CHROMA_OFFSET_BASE1_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET1_FBC_CHROMA_OFFSET_BASE1_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_D - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_D_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_D_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_D_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_D_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_D_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_D - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_D_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_D_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_D_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_D_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_D_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_BYTE - Byte size of encoded picture */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_BYTE_PIC_BYTE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_BYTE_PIC_BYTE_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_BYTE_PIC_BYTE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_BYTE_PIC_BYTE_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_BYTE_PIC_BYTE_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SRC_ADDR_V - Cr component source address */ /*! @{ */ #define VPU_CMD_ENC_PIC_SRC_ADDR_V_SRC_ADDR_V_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_SRC_ADDR_V_SRC_ADDR_V_SHIFT (0U) #define VPU_CMD_ENC_PIC_SRC_ADDR_V_SRC_ADDR_V(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_ADDR_V_SRC_ADDR_V_SHIFT)) & VPU_CMD_ENC_PIC_SRC_ADDR_V_SRC_ADDR_V_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_RC_TARGET_RATE - Target bitrate */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_RC_TARGET_RATE_RC_TARGET_RATE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_RC_TARGET_RATE_RC_TARGET_RATE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_RC_TARGET_RATE_RC_TARGET_RATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_TARGET_RATE_RC_TARGET_RATE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_TARGET_RATE_RC_TARGET_RATE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_FB_OPT - Frame_buffer_full_option */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_FBC_REPLACE_IDX_MASK (0x3FU) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_FBC_REPLACE_IDX_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_FBC_REPLACE_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_FBC_REPLACE_IDX_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_FBC_REPLACE_IDX_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_COL_REPLACE_IDX_MASK (0xFC0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_COL_REPLACE_IDX_SHIFT (6U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_COL_REPLACE_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_COL_REPLACE_IDX_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_COL_REPLACE_IDX_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_NEED_MORE_DISP_BUF_FLAG_MASK (0x1000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_NEED_MORE_DISP_BUF_FLAG_SHIFT (12U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_NEED_MORE_DISP_BUF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_NEED_MORE_DISP_BUF_FLAG_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_NEED_MORE_DISP_BUF_FLAG_MASK) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_UPDATE_SEQ_INFO_MASK (0x2000U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_UPDATE_SEQ_INFO_SHIFT (13U) #define VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_UPDATE_SEQ_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_UPDATE_SEQ_INFO_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_FB_OPT_UPDATE_SEQ_INFO_MASK) /*! @} */ /*! @name CMD_SET_DISP_DEC_PP_PVRIC_CTRL - PVRIC control resigster */ /*! @{ */ #define VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_FMT_MASK (0x7FU) #define VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_FMT_SHIFT (0U) #define VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_FMT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_FMT_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_FMT_MASK) #define VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_LOSSY_MASK (0x200U) #define VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_LOSSY_SHIFT (9U) #define VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_LOSSY(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_LOSSY_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_PVRIC_CTRL_PVRIC_REQ_LOSSY_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL1 - COL base of index1 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL1_COL_BASE1_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL1_COL_BASE1_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL1_COL_BASE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL1_COL_BASE1_SHIFT)) & VPU_CMD_SET_FB_MV_COL1_COL_BASE1_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_E - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_E_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_E_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_E_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_E_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_E_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_E - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_E_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_E_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_E_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_E_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_E_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_GOP_PIC_IDX - A picture index in GOP */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_GOP_PIC_IDX_GOP_PIC_IDX_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_GOP_PIC_IDX_GOP_PIC_IDX_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_GOP_PIC_IDX_GOP_PIC_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_GOP_PIC_IDX_GOP_PIC_IDX_SHIFT)) & VPU_CMD_ENC_GET_RESULT_GOP_PIC_IDX_GOP_PIC_IDX_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SRC_STRIDE - Stride of source picture */ /*! @{ */ #define VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_C_STRIDE_MASK (0xFFFFU) #define VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_C_STRIDE_SHIFT (0U) #define VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_C_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_C_STRIDE_SHIFT)) & VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_C_STRIDE_MASK) #define VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_Y_STRIDE_MASK (0xFFFF0000U) #define VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_Y_STRIDE_SHIFT (16U) #define VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_Y_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_Y_STRIDE_SHIFT)) & VPU_CMD_ENC_PIC_SRC_STRIDE_SRC_Y_STRIDE_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_RC_PARAM - Rate control parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_PIC_RC_MAX_DELTA_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_PIC_RC_MAX_DELTA_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_PIC_RC_MAX_DELTA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_PARAM_PIC_RC_MAX_DELTA_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_PARAM_PIC_RC_MAX_DELTA_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_QP_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_QP_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_LEVEL_MASK (0xF00000U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_LEVEL_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_LEVEL_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_INITIAL_LEVEL_MASK) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_UPDATE_SPEED_MASK (0xFF000000U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_UPDATE_SPEED_SHIFT (24U) #define VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_UPDATE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_UPDATE_SPEED_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_PARAM_RC_UPDATE_SPEED_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_NUM - Number of valid release linear buffer address */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_NUM_DISP_PIC_RELEASE_IDC_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_NUM_DISP_PIC_RELEASE_IDC_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_NUM_DISP_PIC_RELEASE_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_NUM_DISP_PIC_RELEASE_IDC_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_NUM_DISP_PIC_RELEASE_IDC_MASK) /*! @} */ /*! @name CMD_SET_DISP_DEC_PP_AFBC_COMMON - AFBC control paramter */ /*! @{ */ #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_FORMAT_IDX_MASK (0x3EU) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_FORMAT_IDX_SHIFT (1U) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_FORMAT_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_FORMAT_IDX_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_FORMAT_IDX_MASK) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWHALF_SB_MASK (0x40U) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWHALF_SB_SHIFT (6U) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWHALF_SB(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWHALF_SB_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWHALF_SB_MASK) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWWIDE_SB_MASK (0x80U) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWWIDE_SB_SHIFT (7U) #define VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWWIDE_SB(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWWIDE_SB_SHIFT)) & VPU_CMD_SET_DISP_DEC_PP_AFBC_COMMON_AFBC_AWWIDE_SB_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED1 - Sub sampled base of index1 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED1_SUB_SAMPLED_FB_BASE1_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED1_SUB_SAMPLED_FB_BASE1_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED1_SUB_SAMPLED_FB_BASE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED1_SUB_SAMPLED_FB_BASE1_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED1_SUB_SAMPLED_FB_BASE1_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_F - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_F_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_F_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_F_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_F_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_F_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_F - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_F_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_F_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_F_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_F_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_F_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM - Display Crop Offset Top/Bottom */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_MASK (0xFFFFU) #define VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_SHIFT)) & VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_BOTTOM_OFFSET_MASK) #define VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_MASK (0xFFFF0000U) #define VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_SHIFT (16U) #define VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_SHIFT)) & VPU_CMD_DEC_GET_RESULT_CROP_TOP_BOTTOM_DISPLAY_TOP_OFFSET_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_USED_SRC_IDX - Buffer index of source picture that is used for encoding */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_USED_SRC_IDX_USED_SRC_PIC_IDX_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_USED_SRC_IDX_USED_SRC_PIC_IDX_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_USED_SRC_IDX_USED_SRC_PIC_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_USED_SRC_IDX_USED_SRC_PIC_IDX_SHIFT)) & VPU_CMD_ENC_GET_RESULT_USED_SRC_IDX_USED_SRC_PIC_IDX_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SRC_FORMAT - Format of source picture */ /*! @{ */ #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_num_MASK (0x3U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_num_SHIFT (0U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_num(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_num_SHIFT)) & VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_num_MASK) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_cr_first_MASK (0x4U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_cr_first_SHIFT (2U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_cr_first(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_cr_first_SHIFT)) & VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_cr_first_MASK) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_special_flag_MASK (0x8U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_special_flag_SHIFT (3U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_special_flag(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_special_flag_SHIFT)) & VPU_CMD_ENC_PIC_SRC_FORMAT_src_plane_special_flag_MASK) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_10bit_MASK (0x10U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_10bit_SHIFT (4U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_10bit(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_10bit_SHIFT)) & VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_10bit_MASK) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_special_flag_MASK (0x20U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_special_flag_SHIFT (5U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_special_flag(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_special_flag_SHIFT)) & VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_special_flag_MASK) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_left_aligned_MASK (0x40U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_left_aligned_SHIFT (6U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_left_aligned(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_left_aligned_SHIFT)) & VPU_CMD_ENC_PIC_SRC_FORMAT_src_sample_left_aligned_MASK) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_endian_MASK (0xF000U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_endian_SHIFT (12U) #define VPU_CMD_ENC_PIC_SRC_FORMAT_src_endian(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_FORMAT_src_endian_SHIFT)) & VPU_CMD_ENC_PIC_SRC_FORMAT_src_endian_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_HVS_PARAM - HVS parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_QP_SCALE_MASK (0xFU) #define VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_QP_SCALE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_QP_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_QP_SCALE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_QP_SCALE_MASK) #define VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_MAX_DELTA_QP_MASK (0x3F000U) #define VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_MAX_DELTA_QP_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_MAX_DELTA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_MAX_DELTA_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_HVS_PARAM_HVS_MAX_DELTA_QP_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_0 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_0_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_0_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_0_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_0_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_0_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y2 - Luma base of index2 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y2_LUMA_BASE2_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y2_LUMA_BASE2_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y2_LUMA_BASE2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y2_LUMA_BASE2_SHIFT)) & VPU_CMD_SET_FB_FBC_Y2_LUMA_BASE2_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_10 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_10_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_10_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_10_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_10_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_10_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_10 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_10_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_10_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_10_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_10_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_10_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT - Display Crop Offset Left/Right */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_MASK (0xFFFFU) #define VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_SHIFT)) & VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_RIGHT_OFFSET_MASK) #define VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_MASK (0xFFFF0000U) #define VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_SHIFT (16U) #define VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_SHIFT)) & VPU_CMD_DEC_GET_RESULT_CROP_LEFT_RIGHT_DISPLAY_LEFT_OFFSET_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_NUM - Encoded picture number */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_PIC_NUM_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_PIC_NUM_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_NUM_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_NUM_PIC_NUM_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_NUM_PIC_NUM_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_RC_MAX_BITRATE - RC_MAX_BITRATE */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_RC_MAX_BITRATE_RC_MAX_BITRATE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_RC_MAX_BITRATE_RC_MAX_BITRATE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_RC_MAX_BITRATE_RC_MAX_BITRATE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_MAX_BITRATE_RC_MAX_BITRATE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_MAX_BITRATE_RC_MAX_BITRATE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C2 - Cb base of index2 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C2_CB_BASE2_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C2_CB_BASE2_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C2_CB_BASE2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C2_CB_BASE2_SHIFT)) & VPU_CMD_SET_FB_FBC_C2_CB_BASE2_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_11 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_11_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_11_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_11_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_11_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_11_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_11 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_11_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_11_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_11_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_11_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_11_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_TEMP_BASE - Temporal buffer base address */ /*! @{ */ #define VPU_CMD_CREATE_INST_TEMP_BASE_TEMP_BUF_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_TEMP_BASE_TEMP_BUF_BASE_SHIFT (0U) #define VPU_CMD_CREATE_INST_TEMP_BASE_TEMP_BUF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_TEMP_BASE_TEMP_BUF_BASE_SHIFT)) & VPU_CMD_CREATE_INST_TEMP_BASE_TEMP_BUF_BASE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_AU_START_POS - AU Bitstream Start Position */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_AU_START_POS_AU_START_POS_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_AU_START_POS_AU_START_POS_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_AU_START_POS_AU_START_POS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_AU_START_POS_AU_START_POS_SHIFT)) & VPU_CMD_DEC_GET_RESULT_AU_START_POS_AU_START_POS_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_VCL_NUT - Encoded NAL unit type of VCL */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_VCL_NUT_VCL_NUT_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_VCL_NUT_VCL_NUT_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_VCL_NUT_VCL_NUT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_VCL_NUT_VCL_NUT_SHIFT)) & VPU_CMD_ENC_GET_RESULT_VCL_NUT_VCL_NUT_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SRC_AXI_SEL - Selection of source AXI port */ /*! @{ */ #define VPU_CMD_ENC_PIC_SRC_AXI_SEL_PRP_GDI_SEL_MASK (0x1U) #define VPU_CMD_ENC_PIC_SRC_AXI_SEL_PRP_GDI_SEL_SHIFT (0U) #define VPU_CMD_ENC_PIC_SRC_AXI_SEL_PRP_GDI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SRC_AXI_SEL_PRP_GDI_SEL_SHIFT)) & VPU_CMD_ENC_PIC_SRC_AXI_SEL_PRP_GDI_SEL_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_RC_VBV_BUFFER_SIZE - RC_VBV_BUFFER_SIZE */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_RC_VBV_BUFFER_SIZE_RC_VBV_BUFFER_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_RC_VBV_BUFFER_SIZE_RC_VBV_BUFFER_SIZE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_RC_VBV_BUFFER_SIZE_RC_VBV_BUFFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_RC_VBV_BUFFER_SIZE_RC_VBV_BUFFER_SIZE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_RC_VBV_BUFFER_SIZE_RC_VBV_BUFFER_SIZE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_2 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_2_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_2_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_2_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_2_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_2_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET2 - FBC luma offset base of index2 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET2_FBC_LUMA_OFFSET_BASE2_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET2_FBC_LUMA_OFFSET_BASE2_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET2_FBC_LUMA_OFFSET_BASE2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET2_FBC_LUMA_OFFSET_BASE2_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET2_FBC_LUMA_OFFSET_BASE2_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_12 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_12_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_12_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_12_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_12_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_12_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_12 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_12_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_12_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_12_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_12_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_12_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_TEMP_SIZE - Temporal buffer size */ /*! @{ */ #define VPU_CMD_CREATE_INST_TEMP_SIZE_TEMP_BUF_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_TEMP_SIZE_TEMP_BUF_SIZE_SHIFT (0U) #define VPU_CMD_CREATE_INST_TEMP_SIZE_TEMP_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_TEMP_SIZE_TEMP_BUF_SIZE_SHIFT)) & VPU_CMD_CREATE_INST_TEMP_SIZE_TEMP_BUF_SIZE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_AU_END_POS - AU Bitstream End Position */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_AU_END_POS_AU_END_POS_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_AU_END_POS_AU_END_POS_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_AU_END_POS_AU_END_POS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_AU_END_POS_AU_END_POS_SHIFT)) & VPU_CMD_DEC_GET_RESULT_AU_END_POS_AU_END_POS_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_PADD_BYTE - Encoded NAL padding byte num */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_PADD_BYTE_PADD_BYTE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_PADD_BYTE_PADD_BYTE_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_PADD_BYTE_PADD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_PADD_BYTE_PADD_BYTE_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_PADD_BYTE_PADD_BYTE_MASK) /*! @} */ /*! @name CMD_ENC_PIC_CODE_OPTION - NAL unit coding options */ /*! @{ */ #define VPU_CMD_ENC_PIC_CODE_OPTION_IMPLICITLY_HEADER_ENCODE_MASK (0x1U) #define VPU_CMD_ENC_PIC_CODE_OPTION_IMPLICITLY_HEADER_ENCODE_SHIFT (0U) #define VPU_CMD_ENC_PIC_CODE_OPTION_IMPLICITLY_HEADER_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CODE_OPTION_IMPLICITLY_HEADER_ENCODE_SHIFT)) & VPU_CMD_ENC_PIC_CODE_OPTION_IMPLICITLY_HEADER_ENCODE_MASK) #define VPU_CMD_ENC_PIC_CODE_OPTION_VCL_MASK (0x2U) #define VPU_CMD_ENC_PIC_CODE_OPTION_VCL_SHIFT (1U) #define VPU_CMD_ENC_PIC_CODE_OPTION_VCL(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CODE_OPTION_VCL_SHIFT)) & VPU_CMD_ENC_PIC_CODE_OPTION_VCL_MASK) #define VPU_CMD_ENC_PIC_CODE_OPTION_VPS_MASK (0x4U) #define VPU_CMD_ENC_PIC_CODE_OPTION_VPS_SHIFT (2U) #define VPU_CMD_ENC_PIC_CODE_OPTION_VPS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CODE_OPTION_VPS_SHIFT)) & VPU_CMD_ENC_PIC_CODE_OPTION_VPS_MASK) #define VPU_CMD_ENC_PIC_CODE_OPTION_SPS_MASK (0x8U) #define VPU_CMD_ENC_PIC_CODE_OPTION_SPS_SHIFT (3U) #define VPU_CMD_ENC_PIC_CODE_OPTION_SPS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CODE_OPTION_SPS_SHIFT)) & VPU_CMD_ENC_PIC_CODE_OPTION_SPS_MASK) #define VPU_CMD_ENC_PIC_CODE_OPTION_PPS_MASK (0x10U) #define VPU_CMD_ENC_PIC_CODE_OPTION_PPS_SHIFT (4U) #define VPU_CMD_ENC_PIC_CODE_OPTION_PPS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CODE_OPTION_PPS_SHIFT)) & VPU_CMD_ENC_PIC_CODE_OPTION_PPS_MASK) #define VPU_CMD_ENC_PIC_CODE_OPTION_EOS_MASK (0x40U) #define VPU_CMD_ENC_PIC_CODE_OPTION_EOS_SHIFT (6U) #define VPU_CMD_ENC_PIC_CODE_OPTION_EOS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CODE_OPTION_EOS_SHIFT)) & VPU_CMD_ENC_PIC_CODE_OPTION_EOS_MASK) #define VPU_CMD_ENC_PIC_CODE_OPTION_EOB_MASK (0x80U) #define VPU_CMD_ENC_PIC_CODE_OPTION_EOB_SHIFT (7U) #define VPU_CMD_ENC_PIC_CODE_OPTION_EOB(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CODE_OPTION_EOB_SHIFT)) & VPU_CMD_ENC_PIC_CODE_OPTION_EOB_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP - Min/Max QP for Inter pictures */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MIN_QP_MASK (0x3FU) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MIN_QP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MIN_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MIN_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MIN_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MAX_QP_MASK (0xFC0U) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MAX_QP_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MAX_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MAX_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_P_MAX_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MIN_QP_MASK (0x3F000U) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MIN_QP_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MIN_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MIN_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MIN_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MAX_QP_MASK (0xFC0000U) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MAX_QP_SHIFT (18U) #define VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MAX_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MAX_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_INTER_MIN_MAX_QP_B_MAX_QP_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_3 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_3_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_3_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_3_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_3_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_3_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET2 - FBC chroma offset base of index2 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET2_FBC_CHROMA_OFFSET_BASE2_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET2_FBC_CHROMA_OFFSET_BASE2_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET2_FBC_CHROMA_OFFSET_BASE2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET2_FBC_CHROMA_OFFSET_BASE2_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET2_FBC_CHROMA_OFFSET_BASE2_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_13 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_13_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_13_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_13_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_13_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_13_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_13 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_13_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_13_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_13_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_13_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_13_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_PIC_TYPE - Decoded picture type */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_PIC_TYPE_MASK (0x7U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_PIC_TYPE_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_TYPE_PIC_TYPE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_TYPE_PIC_TYPE_MASK) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_VCL_NAL_UNIT_TYPE_MASK (0x3F0U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_VCL_NAL_UNIT_TYPE_SHIFT (4U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_VCL_NAL_UNIT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_TYPE_VCL_NAL_UNIT_TYPE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_TYPE_VCL_NAL_UNIT_TYPE_MASK) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_CTU_SIZE_MASK (0xC00U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_CTU_SIZE_SHIFT (10U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_CTU_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_TYPE_CTU_SIZE_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_TYPE_CTU_SIZE_MASK) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_REF_PIC_FLAG_MASK (0x40000000U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_REF_PIC_FLAG_SHIFT (30U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_REF_PIC_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_TYPE_REF_PIC_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_TYPE_REF_PIC_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_OUTPUT_FLAG_MASK (0x80000000U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_OUTPUT_FLAG_SHIFT (31U) #define VPU_CMD_DEC_GET_RESULT_PIC_TYPE_OUTPUT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_TYPE_OUTPUT_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_TYPE_OUTPUT_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_DIST_LOW - Low 32bit SSD */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_DIST_LOW_DIST_YUV_LOW_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_DIST_LOW_DIST_YUV_LOW_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_DIST_LOW_DIST_YUV_LOW(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_DIST_LOW_DIST_YUV_LOW_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_DIST_LOW_DIST_YUV_LOW_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PIC_PARAM - HEVC encoder picture level parameter */ /*! @{ */ #define VPU_CMD_ENC_PIC_PIC_PARAM_PIC_SKIP_FLAG_MASK (0x1U) #define VPU_CMD_ENC_PIC_PIC_PARAM_PIC_SKIP_FLAG_SHIFT (0U) #define VPU_CMD_ENC_PIC_PIC_PARAM_PIC_SKIP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_PIC_SKIP_FLAG_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_PIC_SKIP_FLAG_MASK) #define VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_QP_MASK (0x2U) #define VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_QP_SHIFT (1U) #define VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_QP_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_QP_MASK) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_I_MASK (0xFCU) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_I_SHIFT (2U) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_I(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_I_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_I_MASK) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_P_MASK (0x3F00U) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_P_SHIFT (8U) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_P_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_P_MASK) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_B_MASK (0xFC000U) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_B_SHIFT (14U) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_B(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_B_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_QP_B_MASK) #define VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_TYPE_MASK (0x100000U) #define VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_TYPE_SHIFT (20U) #define VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_USE_FORCE_PIC_TYPE_MASK) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_TYPE_MASK (0xE00000U) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_TYPE_SHIFT (21U) #define VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_FORCE_PIC_TYPE_MASK) #define VPU_CMD_ENC_PIC_PIC_PARAM_INTRA_4X4_MASK (0x30000000U) #define VPU_CMD_ENC_PIC_PIC_PARAM_INTRA_4X4_SHIFT (28U) #define VPU_CMD_ENC_PIC_PIC_PARAM_INTRA_4X4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PIC_PARAM_INTRA_4X4_SHIFT)) & VPU_CMD_ENC_PIC_PIC_PARAM_INTRA_4X4_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_ROT_PARAM - Rotation and mirror mode */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_ENABLE_MASK (0x1U) #define VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_ENABLE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_ENABLE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_ENABLE_MASK) #define VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_MODE_MASK (0x1EU) #define VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_MODE_SHIFT (1U) #define VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_MODE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_ROT_PARAM_ROTATE_MODE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_4 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_4_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_4_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_4_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_4_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_4_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL2 - COL base of index2 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL2_COL_BASE2_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL2_COL_BASE2_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL2_COL_BASE2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL2_COL_BASE2_SHIFT)) & VPU_CMD_SET_FB_MV_COL2_COL_BASE2_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_14 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_14_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_14_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_14_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_14_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_14_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_14 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_14_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_14_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_14_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_14_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_14_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_PIC_POC - Picture Order Count */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_PIC_POC_PIC_ORDER_COUNT_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_PIC_POC_PIC_ORDER_COUNT_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_PIC_POC_PIC_ORDER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_POC_PIC_ORDER_COUNT_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_POC_PIC_ORDER_COUNT_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_DIST_HIGH - High 32bit SSD */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_DIST_HIGH_DIST_YUV_HIGH_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_DIST_HIGH_DIST_YUV_HIGH_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_DIST_HIGH_DIST_YUV_HIGH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_DIST_HIGH_DIST_YUV_HIGH_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_DIST_HIGH_DIST_YUV_HIGH_MASK) /*! @} */ /*! @name CMD_ENC_PIC_LONGTERM_PIC - Longterm picture setting */ /*! @{ */ #define VPU_CMD_ENC_PIC_LONGTERM_PIC_USE_SRC_LONGTERM_PIC_MASK (0x1U) #define VPU_CMD_ENC_PIC_LONGTERM_PIC_USE_SRC_LONGTERM_PIC_SHIFT (0U) #define VPU_CMD_ENC_PIC_LONGTERM_PIC_USE_SRC_LONGTERM_PIC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_LONGTERM_PIC_USE_SRC_LONGTERM_PIC_SHIFT)) & VPU_CMD_ENC_PIC_LONGTERM_PIC_USE_SRC_LONGTERM_PIC_MASK) #define VPU_CMD_ENC_PIC_LONGTERM_PIC_cmd_enc_longterm_pic_MASK (0x2U) #define VPU_CMD_ENC_PIC_LONGTERM_PIC_cmd_enc_longterm_pic_SHIFT (1U) #define VPU_CMD_ENC_PIC_LONGTERM_PIC_cmd_enc_longterm_pic(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_LONGTERM_PIC_cmd_enc_longterm_pic_SHIFT)) & VPU_CMD_ENC_PIC_LONGTERM_PIC_cmd_enc_longterm_pic_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_NUM_UNITS_IN_TICK - NUM_UNITS_IN_TICK */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_NUM_UNITS_IN_TICK_NUM_UNITS_IN_TICK_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_NUM_UNITS_IN_TICK_NUM_UNITS_IN_TICK_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_NUM_UNITS_IN_TICK_NUM_UNITS_IN_TICK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_NUM_UNITS_IN_TICK_NUM_UNITS_IN_TICK_SHIFT)) & VPU_CMD_ENC_SET_PARAM_NUM_UNITS_IN_TICK_NUM_UNITS_IN_TICK_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_5 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_5_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_5_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_5_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_5_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_5_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED2 - Sub sampled base of index2 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED2_SUB_SAMPLED_FB_BASE2_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED2_SUB_SAMPLED_FB_BASE2_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED2_SUB_SAMPLED_FB_BASE2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED2_SUB_SAMPLED_FB_BASE2_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED2_SUB_SAMPLED_FB_BASE2_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_15 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_15_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_15_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_15_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_15_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_15_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_15 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_15_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_15_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_15_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_15_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_15_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_AR_TABLE_BASE - AdaptiveRound Table base address */ /*! @{ */ #define VPU_CMD_CREATE_INST_AR_TABLE_BASE_AR_TABLE_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_AR_TABLE_BASE_AR_TABLE_BASE_SHIFT (0U) #define VPU_CMD_CREATE_INST_AR_TABLE_BASE_AR_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_AR_TABLE_BASE_AR_TABLE_BASE_SHIFT)) & VPU_CMD_CREATE_INST_AR_TABLE_BASE_AR_TABLE_BASE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_RECOVERY_POINT - Recovery point */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_SIGNED_RECOVERY_POC_CNT_MASK (0xFFFFU) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_SIGNED_RECOVERY_POC_CNT_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_SIGNED_RECOVERY_POC_CNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_SIGNED_RECOVERY_POC_CNT_SHIFT)) & VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_SIGNED_RECOVERY_POC_CNT_MASK) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXACT_MATCH_FLAG_MASK (0x10000U) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXACT_MATCH_FLAG_SHIFT (16U) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXACT_MATCH_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXACT_MATCH_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXACT_MATCH_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_BROKEN_LINK_FLAG_MASK (0x20000U) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_BROKEN_LINK_FLAG_SHIFT (17U) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_BROKEN_LINK_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_BROKEN_LINK_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_BROKEN_LINK_FLAG_MASK) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXIST_FLAG_MASK (0x40000U) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXIST_FLAG_SHIFT (18U) #define VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXIST_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXIST_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_RECOVERY_POINT_EXIST_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_MAX_LATENCY_PICTURES - The number of latency picture */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_MAX_LATENCY_PICTURES_MAX_LATENCY_PIC_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_MAX_LATENCY_PICTURES_MAX_LATENCY_PIC_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_MAX_LATENCY_PICTURES_MAX_LATENCY_PIC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_MAX_LATENCY_PICTURES_MAX_LATENCY_PIC_SHIFT)) & VPU_CMD_ENC_GET_RESULT_MAX_LATENCY_PICTURES_MAX_LATENCY_PIC_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR - Address of prefix SEI nal data */ /*! @{ */ #define VPU_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_TIME_SCALE - TIME_SCALE */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_TIME_SCALE_TIME_SCALE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_TIME_SCALE_TIME_SCALE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_TIME_SCALE_TIME_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TIME_SCALE_TIME_SCALE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TIME_SCALE_TIME_SCALE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_6 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_6_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_6_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_6_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_6_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_6_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y3 - Luma base of index3 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y3_LUMA_BASE3_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y3_LUMA_BASE3_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y3_LUMA_BASE3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y3_LUMA_BASE3_SHIFT)) & VPU_CMD_SET_FB_FBC_Y3_LUMA_BASE3_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_16 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_16_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_16_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_16_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_16_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_16_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_16 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_16_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_16_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_16_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_16_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_16_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DEBUG_INDEX - FBC and BWB frame buffer index for internal use */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_BWB_FB_INDEX_MASK (0xFFU) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_BWB_FB_INDEX_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_BWB_FB_INDEX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_BWB_FB_INDEX_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_BWB_FB_INDEX_MASK) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_FBC_FB_INDEX_MASK (0xFF00U) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_FBC_FB_INDEX_SHIFT (8U) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_FBC_FB_INDEX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_FBC_FB_INDEX_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_FBC_FB_INDEX_MASK) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_AV1_INTRA_BC_FLAG_MASK (0x10000U) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_AV1_INTRA_BC_FLAG_SHIFT (16U) #define VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_AV1_INTRA_BC_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_AV1_INTRA_BC_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DEBUG_INDEX_DEC_AV1_INTRA_BC_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PREFIX_SEI_INFO - Information of prefix SEI nal data */ /*! @{ */ #define VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_ENABLE_MASK (0x1U) #define VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_ENABLE_SHIFT (0U) #define VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_ENABLE_SHIFT)) & VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_ENABLE_MASK) #define VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_SIZE_MASK (0xFFFF0000U) #define VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_SIZE_SHIFT (16U) #define VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_SIZE_SHIFT)) & VPU_CMD_ENC_PIC_PREFIX_SEI_INFO_NAL_SIZE_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_NUM_TICKS_POC_DIFF_ONE - NUM_TICKS_POC_DIFF_ONE */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_NUM_TICKS_POC_DIFF_ONE_NUM_TICKS_POC_DIFF_ONE_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_NUM_TICKS_POC_DIFF_ONE_NUM_TICKS_POC_DIFF_ONE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_NUM_TICKS_POC_DIFF_ONE_NUM_TICKS_POC_DIFF_ONE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_NUM_TICKS_POC_DIFF_ONE_NUM_TICKS_POC_DIFF_ONE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_NUM_TICKS_POC_DIFF_ONE_NUM_TICKS_POC_DIFF_ONE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_7 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_7_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_7_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_7_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_7_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_7_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C3 - Cb base of index3 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C3_CB_BASE3_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C3_CB_BASE3_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C3_CB_BASE3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C3_CB_BASE3_SHIFT)) & VPU_CMD_SET_FB_FBC_C3_CB_BASE3_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_17 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_17_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_17_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_17_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_17_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_17_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_17 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_17_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_17_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_17_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_17_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_17_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DECODED_ADDRESS - Decoded picture address */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DECODED_ADDRESS_DEC_PIC_ADDRESS_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DECODED_ADDRESS_DEC_PIC_ADDRESS_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DECODED_ADDRESS_DEC_PIC_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DECODED_ADDRESS_DEC_PIC_ADDRESS_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DECODED_ADDRESS_DEC_PIC_ADDRESS_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HISTO_CNT_0 - MV histogram count */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_0_HISTO_CNT_0_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_0_HISTO_CNT_0_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_0_HISTO_CNT_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HISTO_CNT_0_HISTO_CNT_0_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HISTO_CNT_0_HISTO_CNT_0_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR - Address of suffix SEI nal data */ /*! @{ */ #define VPU_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_8 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_8_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_8_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_8_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_8_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_8_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET3 - FBC luma offset base of index3 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET3_FBC_LUMA_OFFSET_BASE3_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET3_FBC_LUMA_OFFSET_BASE3_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET3_FBC_LUMA_OFFSET_BASE3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET3_FBC_LUMA_OFFSET_BASE3_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET3_FBC_LUMA_OFFSET_BASE3_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_18 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_18_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_18_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_18_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_18_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_18_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_18 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_18_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_18_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_18_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_18_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_18_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_SEC_AXI_BASE_CORE0 - Secondary AXI base address for core 0 */ /*! @{ */ #define VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE0_SEC_AXI_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE0_SEC_AXI_BASE_SHIFT (0U) #define VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE0_SEC_AXI_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE0_SEC_AXI_BASE_SHIFT)) & VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE0_SEC_AXI_BASE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISPLAY_ADDR - Display picture address of DPB */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISPLAY_ADDR_DISPLAY_PIC_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISPLAY_ADDR_DISPLAY_PIC_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISPLAY_ADDR_DISPLAY_PIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISPLAY_ADDR_DISPLAY_PIC_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISPLAY_ADDR_DISPLAY_PIC_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HISTO_CNT_1 - MV histogram count */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_1_HISTO_CNT_1_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_1_HISTO_CNT_1_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_1_HISTO_CNT_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HISTO_CNT_1_HISTO_CNT_1_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HISTO_CNT_1_HISTO_CNT_1_MASK) /*! @} */ /*! @name CMD_ENC_PIC_SUFFIX_SEI_INFO - Information of suffix SEI nal data */ /*! @{ */ #define VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_ENABLE_MASK (0x1U) #define VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_ENABLE_SHIFT (0U) #define VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_ENABLE_SHIFT)) & VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_ENABLE_MASK) #define VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_SIZE_MASK (0xFFFF0000U) #define VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_SIZE_SHIFT (16U) #define VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_SIZE_SHIFT)) & VPU_CMD_ENC_PIC_SUFFIX_SEI_INFO_NAL_SIZE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_9 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_9_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_9_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_9_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_9_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_9_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET3 - FBC chroma offset base of index3 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET3_FBC_CHROMA_OFFSET_BASE3_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET3_FBC_CHROMA_OFFSET_BASE3_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET3_FBC_CHROMA_OFFSET_BASE3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET3_FBC_CHROMA_OFFSET_BASE3_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET3_FBC_CHROMA_OFFSET_BASE3_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_19 - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_19_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_19_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_19_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_19_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_19_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_19 - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_19_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_19_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_19_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_19_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_19_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_SEC_AXI_SIZE_CORE0 - Seconary AXI memory size core 0 */ /*! @{ */ #define VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE0_SEC_AXI_MEM_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE0_SEC_AXI_MEM_SIZE_SHIFT (0U) #define VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE0_SEC_AXI_MEM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE0_SEC_AXI_MEM_SIZE_SHIFT)) & VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE0_SEC_AXI_MEM_SIZE_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HISTO_CNT_2 - MV histogram count */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_2_HISTO_CNT_2_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_2_HISTO_CNT_2_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_2_HISTO_CNT_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HISTO_CNT_2_HISTO_CNT_2_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HISTO_CNT_2_HISTO_CNT_2_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_A - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_A_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_A_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_A_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_A_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_A_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL3 - info base of index3 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL3_COL_BASE3_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL3_COL_BASE3_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL3_COL_BASE3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL3_COL_BASE3_SHIFT)) & VPU_CMD_SET_FB_MV_COL3_COL_BASE3_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_1A - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1A_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1A_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1A_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_1A_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_1A_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1A - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1A_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1A_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1A_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1A_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1A_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_SEC_AXI_BASE_CORE1 - Secondary AXI base address for core 1 */ /*! @{ */ #define VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE1_SEC_AXI_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE1_SEC_AXI_BASE_SHIFT (0U) #define VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE1_SEC_AXI_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE1_SEC_AXI_BASE_SHIFT)) & VPU_CMD_CREATE_INST_SEC_AXI_BASE_CORE1_SEC_AXI_BASE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_IDC - Display flag */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_IDC_DISPLAY_FLAG_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_IDC_DISPLAY_FLAG_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_IDC_DISPLAY_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_IDC_DISPLAY_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_IDC_DISPLAY_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HISTO_CNT_3 - MV histogram count */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_3_HISTO_CNT_3_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_3_HISTO_CNT_3_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_3_HISTO_CNT_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HISTO_CNT_3_HISTO_CNT_3_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HISTO_CNT_3_HISTO_CNT_3_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_BG_PARAM - Background encoding parameter */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_EN_BG_DETECT_MASK (0x1U) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_EN_BG_DETECT_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_EN_BG_DETECT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_BG_PARAM_EN_BG_DETECT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_BG_PARAM_EN_BG_DETECT_MASK) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MAX_DIFF_MASK (0x3FEU) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MAX_DIFF_SHIFT (1U) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MAX_DIFF_SHIFT)) & VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MAX_DIFF_MASK) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MEAN_DIFF_MASK (0x3FC00U) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MEAN_DIFF_SHIFT (10U) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MEAN_DIFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MEAN_DIFF_SHIFT)) & VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_TH_MEAN_DIFF_MASK) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_DELTA_QP_MASK (0x3F000000U) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_DELTA_QP_SHIFT (24U) #define VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_DELTA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_DELTA_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_BG_PARAM_BG_DELTA_QP_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_B - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_B_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_B_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_B_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_B_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_B_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED3 - Sub sampled base of index3 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED3_SUB_SAMPLED_FB_BASE3_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED3_SUB_SAMPLED_FB_BASE3_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED3_SUB_SAMPLED_FB_BASE3(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED3_SUB_SAMPLED_FB_BASE3_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED3_SUB_SAMPLED_FB_BASE3_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_1B - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1B_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1B_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1B_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_1B_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_1B_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1B - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1B_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1B_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1B_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1B_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1B_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_CREATE_INST_SEC_AXI_SIZE_CORE1 - Seconary AXI memory size core 1 */ /*! @{ */ #define VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE1_SEC_AXI_MEM_SIZE_MASK (0xFFFFFFFFU) #define VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE1_SEC_AXI_MEM_SIZE_SHIFT (0U) #define VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE1_SEC_AXI_MEM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE1_SEC_AXI_MEM_SIZE_SHIFT)) & VPU_CMD_CREATE_INST_SEC_AXI_SIZE_CORE1_SEC_AXI_MEM_SIZE_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_NUM_ERR_CTB - Number of error CTU */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_NUM_ERR_CTB_ERROR_CTU_NUMBER_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_NUM_ERR_CTB_ERROR_CTU_NUMBER_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_NUM_ERR_CTB_ERROR_CTU_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_NUM_ERR_CTB_ERROR_CTU_NUMBER_SHIFT)) & VPU_CMD_DEC_GET_RESULT_NUM_ERR_CTB_ERROR_CTU_NUMBER_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HISTO_CNT_4 - MV histogram count */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_4_HISTO_CNT_4_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_4_HISTO_CNT_4_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HISTO_CNT_4_HISTO_CNT_4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HISTO_CNT_4_HISTO_CNT_4_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HISTO_CNT_4_HISTO_CNT_4_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_NON_VCL_PARAM - CMD_ENC_SET_PARAM_SEQ_NON_VCL */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_AUD_MASK (0x1U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_AUD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_AUD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_AUD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_AUD_MASK) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_VUI_RBSP_MASK (0x2U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_VUI_RBSP_SHIFT (1U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_VUI_RBSP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_VUI_RBSP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_VUI_RBSP_MASK) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_HRD_RBSP_MASK (0x4U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_HRD_RBSP_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_HRD_RBSP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_HRD_RBSP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_ENCODE_HRD_RBSP_MASK) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_VUI_RBSP_SIZE_MASK (0x3FFF0U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_VUI_RBSP_SIZE_SHIFT (4U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_VUI_RBSP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_VUI_RBSP_SIZE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_VUI_RBSP_SIZE_MASK) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_HRD_RBSP_SIZE_MASK (0xFFFC0000U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_HRD_RBSP_SIZE_SHIFT (18U) #define VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_HRD_RBSP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_HRD_RBSP_SIZE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_NON_VCL_PARAM_HRD_RBSP_SIZE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_C - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_C_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_C_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_C_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_C_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_C_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y4 - Luma base of index4 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y4_LUMA_BASE4_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y4_LUMA_BASE4_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y4_LUMA_BASE4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y4_LUMA_BASE4_SHIFT)) & VPU_CMD_SET_FB_FBC_Y4_LUMA_BASE4_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_1C - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1C_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1C_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1C_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_1C_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_1C_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1C - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1C_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1C_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1C_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1C_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1C_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_NUM_TILE_COL - Number of tile columns */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_NUM_TILE_COL_NUMBER_OF_TILE_COLUMNS_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_NUM_TILE_COL_NUMBER_OF_TILE_COLUMNS_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_NUM_TILE_COL_NUMBER_OF_TILE_COLUMNS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_NUM_TILE_COL_NUMBER_OF_TILE_COLUMNS_SHIFT)) & VPU_CMD_ENC_GET_RESULT_NUM_TILE_COL_NUMBER_OF_TILE_COLUMNS_MASK) /*! @} */ /*! @name CMD_ENC_PIC_CSC_COEFF_0 - Control register of CSC */ /*! @{ */ #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_BY_MASK (0x3FFU) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_BY_SHIFT (0U) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_BY(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_BY_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_BY_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_GY_MASK (0xFFC00U) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_GY_SHIFT (10U) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_GY(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_GY_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_GY_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_RY_MASK (0x3FF00000U) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_RY_SHIFT (20U) #define VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_RY(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_RY_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_0_CSC_Coeff_RY_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_VUI_RBSP_ADDR - VUI RBSP buffer address */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_VUI_RBSP_ADDR_VUI_RBSP_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_VUI_RBSP_ADDR_VUI_RBSP_ADDR_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_VUI_RBSP_ADDR_VUI_RBSP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_VUI_RBSP_ADDR_VUI_RBSP_ADDR_SHIFT)) & VPU_CMD_ENC_SET_PARAM_VUI_RBSP_ADDR_VUI_RBSP_ADDR_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_D - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_D_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_D_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_D_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_D_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_D_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C4 - Cb base of index4 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C4_CB_BASE4_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C4_CB_BASE4_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C4_CB_BASE4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C4_CB_BASE4_SHIFT)) & VPU_CMD_SET_FB_FBC_C4_CB_BASE4_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_1D - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1D_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1D_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1D_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_1D_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_1D_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1D - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1D_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1D_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1D_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1D_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1D_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_NUM_TILE_ROW - Number of tile rows */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_NUM_TILE_ROW_NUMBER_OF_TILE_ROWS_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_NUM_TILE_ROW_NUMBER_OF_TILE_ROWS_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_NUM_TILE_ROW_NUMBER_OF_TILE_ROWS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_NUM_TILE_ROW_NUMBER_OF_TILE_ROWS_SHIFT)) & VPU_CMD_ENC_GET_RESULT_NUM_TILE_ROW_NUMBER_OF_TILE_ROWS_MASK) /*! @} */ /*! @name CMD_ENC_PIC_CSC_COEFF_1 - Control register of CSC */ /*! @{ */ #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_BCB_MASK (0x3FFU) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_BCB_SHIFT (0U) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_BCB(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_BCB_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_BCB_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_GCB_MASK (0xFFC00U) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_GCB_SHIFT (10U) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_GCB(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_GCB_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_GCB_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_RCB_MASK (0x3FF00000U) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_RCB_SHIFT (20U) #define VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_RCB(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_RCB_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_1_CSC_Coeff_RCB_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_HRD_RBSP_ADDR - HRD RBSP buffer address */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_HRD_RBSP_ADDR_HRD_RBSP_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_SET_PARAM_HRD_RBSP_ADDR_HRD_RBSP_ADDR_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_HRD_RBSP_ADDR_HRD_RBSP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_HRD_RBSP_ADDR_HRD_RBSP_ADDR_SHIFT)) & VPU_CMD_ENC_SET_PARAM_HRD_RBSP_ADDR_HRD_RBSP_ADDR_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_E - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_E_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_E_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_E_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_E_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_E_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET4 - FBC luma offset base of index4 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET4_FBC_LUMA_OFFSET_BASE4_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET4_FBC_LUMA_OFFSET_BASE4_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET4_FBC_LUMA_OFFSET_BASE4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET4_FBC_LUMA_OFFSET_BASE4_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET4_FBC_LUMA_OFFSET_BASE4_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_1E - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1E_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1E_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1E_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_1E_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_1E_RD_PTR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1E - Display picture address for release */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1E_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1E_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1E_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1E_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_RELEASE_DISP_ADDR_1E_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_WIDTH - Encoded picture width */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_WIDTH_ENCODED_PICTURE_WIDTH_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_WIDTH_ENCODED_PICTURE_WIDTH_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_WIDTH_ENCODED_PICTURE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_WIDTH_ENCODED_PICTURE_WIDTH_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_WIDTH_ENCODED_PICTURE_WIDTH_MASK) /*! @} */ /*! @name CMD_ENC_PIC_CSC_COEFF_2 - Control register of CSC */ /*! @{ */ #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_BCR_MASK (0x3FFU) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_BCR_SHIFT (0U) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_BCR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_BCR_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_BCR_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_GCR_MASK (0xFFC00U) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_GCR_SHIFT (10U) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_GCR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_GCR_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_GCR_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_RCR_MASK (0x3FF00000U) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_RCR_SHIFT (20U) #define VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_RCR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_RCR_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_2_CSC_Coeff_RCR_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_F - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_F_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_F_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_F_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_F_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_F_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET4 - FBC chroma offset base of index4 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET4_FBC_CHROMA_OFFSET_BASE4_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET4_FBC_CHROMA_OFFSET_BASE4_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET4_FBC_CHROMA_OFFSET_BASE4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET4_FBC_CHROMA_OFFSET_BASE4_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET4_FBC_CHROMA_OFFSET_BASE4_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_RD_PTR_1F - bitstream buffer read pointer */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1F_RD_PTR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1F_RD_PTR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_RD_PTR_1F_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_RD_PTR_1F_RD_PTR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_RD_PTR_1F_RD_PTR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PIC_HEIGHT - Encoded picture height */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PIC_HEIGHT_ENCODED_PICTURE_HEIGHT_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PIC_HEIGHT_ENCODED_PICTURE_HEIGHT_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PIC_HEIGHT_ENCODED_PICTURE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PIC_HEIGHT_ENCODED_PICTURE_HEIGHT_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PIC_HEIGHT_ENCODED_PICTURE_HEIGHT_MASK) /*! @} */ /*! @name CMD_ENC_PIC_CSC_COEFF_3 - Control register of CSC */ /*! @{ */ #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cr_MASK (0x3FFU) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cr_SHIFT (0U) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cr(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cr_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cr_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cb_MASK (0xFFC00U) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cb_SHIFT (10U) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cb(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cb_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Cb_MASK) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Y_MASK (0x3FF00000U) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Y_SHIFT (20U) #define VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Y_SHIFT)) & VPU_CMD_ENC_PIC_CSC_COEFF_3_CSC_Offset_Y_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_QROUND_OFFSET - Quantization rounding offset */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTRA_MASK (0x1FFCU) #define VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTRA_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTRA_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTRA_MASK) #define VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTER_MASK (0xFFE000U) #define VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTER_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTER_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QROUND_OFFSET_CUSTOM_QROUND_OFFSET_INTER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_10 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_10_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_10_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_10_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_10_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_10_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL4 - info base of index4 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL4_COL_BASE4_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL4_COL_BASE4_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL4_COL_BASE4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL4_COL_BASE4_SHIFT)) & VPU_CMD_SET_FB_MV_COL4_COL_BASE4_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_0 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_0_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_0_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_0_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_0_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_0_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_0 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_0_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_0_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_0_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_0_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_0_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_0 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_clear_MASK (0xFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_clear_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_clear(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_clear_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_clear_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_enable_MASK (0x10U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_enable_SHIFT (4U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_enable(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_enable_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_filter_enable_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_CDC_invaloverride_MASK (0x20U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_CDC_invaloverride_SHIFT (5U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_CDC_invaloverride(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_CDC_invaloverride_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_CDC_invaloverride_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_ictrl_invalidate_context_MASK (0x1C0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_ictrl_invalidate_context_SHIFT (6U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_ictrl_invalidate_context(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_ictrl_invalidate_context_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_ictrl_invalidate_context_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_sub_tag_id_MASK (0x600U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_sub_tag_id_SHIFT (9U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_sub_tag_id(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_sub_tag_id_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_sub_tag_id_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_tag_ID_MASK (0x1800U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_tag_ID_SHIFT (11U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_tag_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_tag_ID_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_0_PVRIC_request_tag_ID_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_QUANT_PARAM_1 - AV1 Qindex offset */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_AC_MASK (0xFFU) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_AC_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_AC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_AC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_AC_MASK) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_AC_MASK (0xFF00U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_AC_SHIFT (8U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_AC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_AC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_AC_MASK) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_DC_MASK (0xFF0000U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_DC_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_DC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_DC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_V_DC_MASK) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_DC_MASK (0xFF000000U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_DC_SHIFT (24U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_DC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_DC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_1_DELTA_QP_U_DC_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_11 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_11_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_11_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_11_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_11_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_11_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED4 - Sub sampled base of index4 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED4_SUB_SAMPLED_FB_BASE4_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED4_SUB_SAMPLED_FB_BASE4_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED4_SUB_SAMPLED_FB_BASE4(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED4_SUB_SAMPLED_FB_BASE4_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED4_SUB_SAMPLED_FB_BASE4_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_1 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_1 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_uv_val0_MASK (0x3FFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_uv_val0_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_uv_val0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_uv_val0_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_uv_val0_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_RSVD0_MASK (0xFC00U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_RSVD0_SHIFT (10U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_RSVD0_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_RSVD0_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_y_val0_MASK (0x3FF0000U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_y_val0_SHIFT (16U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_y_val0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_y_val0_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_1_PVRIC_cr_y_val0_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_QUANT_PARAM_2 - Lambda delta QP for customized mode decision */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_DELTA_QP_Y_DC_MASK (0xFFU) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_DELTA_QP_Y_DC_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_DELTA_QP_Y_DC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_DELTA_QP_Y_DC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_DELTA_QP_Y_DC_MASK) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTRA_MASK (0x3F00U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTRA_SHIFT (8U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTRA_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTRA_MASK) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTER_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTER_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTER_SHIFT)) & VPU_CMD_ENC_SET_PARAM_QUANT_PARAM_2_LAMBDA_DELTA_QP_INTER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_12 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_12_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_12_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_12_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_12_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_12_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y5 - Luma base of index5 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y5_LUMA_BASE5_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y5_LUMA_BASE5_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y5_LUMA_BASE5(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y5_LUMA_BASE5_SHIFT)) & VPU_CMD_SET_FB_FBC_Y5_LUMA_BASE5_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_2 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_2_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_2_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_2_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_2_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_2_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_2 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_2_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_2_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_2_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_2_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_2_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_2 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRI_c_uv_val1_MASK (0x3FFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRI_c_uv_val1_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRI_c_uv_val1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRI_c_uv_val1_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRI_c_uv_val1_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_RSVD0_MASK (0xFC00U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_RSVD0_SHIFT (10U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_RSVD0_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_RSVD0_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRIC_cr_y_val1_MASK (0x3FF0000U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRIC_cr_y_val1_SHIFT (16U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRIC_cr_y_val1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRIC_cr_y_val1_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_2_PVRIC_cr_y_val1_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PARAM - Size of source pictures of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PARAM_CUSTOM_GOP_SIZE_MASK (0x1FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PARAM_CUSTOM_GOP_SIZE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PARAM_CUSTOM_GOP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PARAM_CUSTOM_GOP_SIZE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PARAM_CUSTOM_GOP_SIZE_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_13 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_13_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_13_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_13_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_13_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_13_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C5 - Cb base of index5 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C5_CB_BASE5_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C5_CB_BASE5_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C5_CB_BASE5(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C5_CB_BASE5_SHIFT)) & VPU_CMD_SET_FB_FBC_C5_CB_BASE5_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_3 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_3_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_3_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_3_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_3_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_3_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_3 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_3_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_3_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_3_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_3_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_3_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_3 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_3_PVRIC_ch0123_val0_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_3_PVRIC_ch0123_val0_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_3_PVRIC_ch0123_val0(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_3_PVRIC_ch0123_val0_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_3_PVRIC_ch0123_val0_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0 - Parameters for the 0th picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_0_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_14 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_14_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_14_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_14_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_14_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_14_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET5 - FBC luma offset base of index5 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET5_FBC_LUMA_OFFSET_BASE5_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET5_FBC_LUMA_OFFSET_BASE5_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET5_FBC_LUMA_OFFSET_BASE5(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET5_FBC_LUMA_OFFSET_BASE5_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET5_FBC_LUMA_OFFSET_BASE5_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_4 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_4_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_4_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_4_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_4_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_4_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_4 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_4_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_4_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_4_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_4_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_4_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_4 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_4_PVRIC_cr_ch0123_val1_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_4_PVRIC_cr_ch0123_val1_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_4_PVRIC_cr_ch0123_val1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_4_PVRIC_cr_ch0123_val1_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_4_PVRIC_cr_ch0123_val1_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1 - Parameters for the 1st picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_1_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_15 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_15_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_15_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_15_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_15_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_15_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET5 - FBC chroma offset base of index5 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET5_FBC_CHROMA_OFFSET_BASE5_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET5_FBC_CHROMA_OFFSET_BASE5_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET5_FBC_CHROMA_OFFSET_BASE5(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET5_FBC_CHROMA_OFFSET_BASE5_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET5_FBC_CHROMA_OFFSET_BASE5_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_5 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_5_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_5_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_5_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_5_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_5_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_5 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_5_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_5_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_5_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_5_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_5_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_5 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_b_MASK (0xFFFFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_b_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_b(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_b_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_b_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_p_MASK (0xFFFF0000U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_p_SHIFT (16U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_p(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_p_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_5_PVRIC_core_id_p_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2 - Parameters for the 2nd picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_2_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_16 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_16_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_16_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_16_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_16_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_16_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL5 - info base of index5 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL5_COL_BASE5_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL5_COL_BASE5_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL5_COL_BASE5(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL5_COL_BASE5_SHIFT)) & VPU_CMD_SET_FB_MV_COL5_COL_BASE5_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_6 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_6_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_6_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_6_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_6_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_6_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_6 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_6_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_6_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_6_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_6_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_6_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_6 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_n_MASK (0xFFFFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_n_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_n(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_n_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_n_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_v_MASK (0xFFFF0000U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_v_SHIFT (16U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_v(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_v_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_6_PVRIC_core_id_v_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3 - Parameters for the 3rd picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_3_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_17 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_17_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_17_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_17_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_17_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_17_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED5 - Sub sampled base of index5 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED5_SUB_SAMPLED_FB_BASE5_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED5_SUB_SAMPLED_FB_BASE5_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED5_SUB_SAMPLED_FB_BASE5(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED5_SUB_SAMPLED_FB_BASE5_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED5_SUB_SAMPLED_FB_BASE5_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_7 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_7_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_7_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_7_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_7_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_7_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_7 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_7_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_7_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_7_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_7_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_7_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_CORE_IDC - Used core idc */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_CORE_IDC_DEC_CORE_IDC_MASK (0xFU) #define VPU_CMD_DEC_GET_RESULT_CORE_IDC_DEC_CORE_IDC_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_CORE_IDC_DEC_CORE_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_CORE_IDC_DEC_CORE_IDC_SHIFT)) & VPU_CMD_DEC_GET_RESULT_CORE_IDC_DEC_CORE_IDC_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_7 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_7_PVRIC_core_id_c_MASK (0xFFFFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_7_PVRIC_core_id_c_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_7_PVRIC_core_id_c(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_7_PVRIC_core_id_c_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_7_PVRIC_core_id_c_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4 - Parameters for the 4th picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_4_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_18 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_18_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_18_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_18_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_18_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_18_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y6 - Luma base of index6 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y6_LUMA_BASE6_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y6_LUMA_BASE6_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y6_LUMA_BASE6(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y6_LUMA_BASE6_SHIFT)) & VPU_CMD_SET_FB_FBC_Y6_LUMA_BASE6_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_8 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_8_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_8_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_8_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_8_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_8_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_8 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_8_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_8_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_8_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_8_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_8_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_PIC_PARAM - Bitstream sequence/pic parameter information */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_INTRABC_MASK (0x1U) #define VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_INTRABC_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_INTRABC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_INTRABC_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_INTRABC_MASK) #define VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_SCREEN_CONT_TOOLS_MASK (0x2U) #define VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_SCREEN_CONT_TOOLS_SHIFT (1U) #define VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_SCREEN_CONT_TOOLS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_SCREEN_CONT_TOOLS_SHIFT)) & VPU_CMD_DEC_GET_RESULT_PIC_PARAM_ENABLE_SCREEN_CONT_TOOLS_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_8 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_8_PVRIC_core_ip_changelist_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_8_PVRIC_core_ip_changelist_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_8_PVRIC_core_ip_changelist(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_8_PVRIC_core_ip_changelist_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_8_PVRIC_core_ip_changelist_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5 - Parameters for the 5th picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_5_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_19 - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_19_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_19_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_19_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_19_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_19_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C6 - Cb base of index6 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C6_CB_BASE6_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C6_CB_BASE6_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C6_CB_BASE6(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C6_CB_BASE6_SHIFT)) & VPU_CMD_SET_FB_FBC_C6_CB_BASE6_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_9 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_9_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_9_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_9_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_9_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_9_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_9 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_9_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_9_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_9_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_9_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_9_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISPLAY_FLAG - Validation for display address */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISPLAY_FLAG_DISP_FLAG_MASK (0x1U) #define VPU_CMD_DEC_GET_RESULT_DISPLAY_FLAG_DISP_FLAG_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISPLAY_FLAG_DISP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISPLAY_FLAG_DISP_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISPLAY_FLAG_DISP_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_CORE_IDC - Used core idc */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_CORE_IDC_ENC_CORE_IDC_MASK (0xFU) #define VPU_CMD_ENC_GET_RESULT_CORE_IDC_ENC_CORE_IDC_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_CORE_IDC_ENC_CORE_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_CORE_IDC_ENC_CORE_IDC_SHIFT)) & VPU_CMD_ENC_GET_RESULT_CORE_IDC_ENC_CORE_IDC_MASK) /*! @} */ /*! @name CMD_ENC_PIC_PVRIC_AD_CTRL_9 - additional Control reg of pvric */ /*! @{ */ #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ct_filter_status_MASK (0xFU) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ct_filter_status_SHIFT (0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ct_filter_status(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ct_filter_status_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ct_filter_status_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_invalidate_req_MASK (0xF0U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_invalidate_req_SHIFT (4U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_invalidate_req(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_invalidate_req_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_invalidate_req_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_sub_tag_MASK (0x300U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_sub_tag_SHIFT (8U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_sub_tag(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_sub_tag_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_sub_tag_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_tag_MASK (0xC00U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_tag_SHIFT (10U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_tag(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_tag_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_RD_rtn_tag_MASK) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_inv_context_out_MASK (0x7000U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_inv_context_out_SHIFT (12U) #define VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_inv_context_out(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_inv_context_out_SHIFT)) & VPU_CMD_ENC_PIC_PVRIC_AD_CTRL_9_PVRIC_ictrl_inv_context_out_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6 - Parameters for the 6th picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_6_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1A - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1A_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1A_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1A_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1A_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1A_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET6 - FBC luma offset base of index6 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET6_FBC_LUMA_OFFSET_BASE6_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET6_FBC_LUMA_OFFSET_BASE6_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET6_FBC_LUMA_OFFSET_BASE6(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET6_FBC_LUMA_OFFSET_BASE6_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET6_FBC_LUMA_OFFSET_BASE6_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_A - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_A_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_A_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_A_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_A_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_A_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_A - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_A_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_A_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_A_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_A_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_A_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_NUM - Number of valid release address */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_NUM_RELEASE_ADDRESS_NUM_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_NUM_RELEASE_ADDRESS_NUM_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_NUM_RELEASE_ADDRESS_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_NUM_RELEASE_ADDRESS_NUM_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_NUM_RELEASE_ADDRESS_NUM_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HOST_WARN_INFO - Warning Info */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HOST_WARN_INFO_cmd_enc_get_result_host_warn_info_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HOST_WARN_INFO_cmd_enc_get_result_host_warn_info_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HOST_WARN_INFO_cmd_enc_get_result_host_warn_info(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HOST_WARN_INFO_cmd_enc_get_result_host_warn_info_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HOST_WARN_INFO_cmd_enc_get_result_host_warn_info_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7 - Parameters for the 7th picture of custom GOP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_TYPE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_TYPE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_TYPE_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_POC_OFFSET_MASK (0x7CU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_POC_OFFSET_SHIFT (2U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_POC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_POC_OFFSET_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_POC_OFFSET_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_QP_MASK (0x1F80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_QP_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_PIC_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_USE_MULTI_REF_P_MASK (0x2000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_USE_MULTI_REF_P_SHIFT (13U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_USE_MULTI_REF_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_USE_MULTI_REF_P_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_USE_MULTI_REF_P_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF1_POC_MASK (0xFC000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF1_POC_SHIFT (14U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF1_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF1_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF1_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF0_POC_MASK (0x3F00000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF0_POC_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF0_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF0_POC_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_REF0_POC_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_TEMPORAL_ID_MASK (0x3C000000U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_TEMPORAL_ID_SHIFT (26U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_TEMPORAL_ID_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_GOP_PIC_PARAM_7_TEMPORAL_ID_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1B - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1B_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1B_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1B_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1B_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1B_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET6 - FBC chroma offset base of index6 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET6_FBC_CHROMA_OFFSET_BASE6_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET6_FBC_CHROMA_OFFSET_BASE6_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET6_FBC_CHROMA_OFFSET_BASE6(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET6_FBC_CHROMA_OFFSET_BASE6_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET6_FBC_CHROMA_OFFSET_BASE6_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_B - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_B_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_B_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_B_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_B_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_B_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_B - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_B_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_B_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_B_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_B_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_B_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HOST_ERR_INFO - Error Info */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HOST_ERR_INFO_CMD_ENC_GET_RESULT_HOST_ERR_INFO_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HOST_ERR_INFO_CMD_ENC_GET_RESULT_HOST_ERR_INFO_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HOST_ERR_INFO_CMD_ENC_GET_RESULT_HOST_ERR_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HOST_ERR_INFO_CMD_ENC_GET_RESULT_HOST_ERR_INFO_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HOST_ERR_INFO_CMD_ENC_GET_RESULT_HOST_ERR_INFO_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1C - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1C_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1C_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1C_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1C_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1C_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL6 - info base of index6 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL6_COL_BASE6_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL6_COL_BASE6_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL6_COL_BASE6(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL6_COL_BASE6_SHIFT)) & VPU_CMD_SET_FB_MV_COL6_COL_BASE6_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_C - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_C_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_C_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_C_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_C_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_C_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_C - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_C_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_C_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_C_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_C_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_C_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_HOST_SUCCESS - Host command Reture Value */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_HOST_SUCCESS_CMD_ENC_GET_RESULT_HOST_SUCCESS_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_HOST_SUCCESS_CMD_ENC_GET_RESULT_HOST_SUCCESS_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_HOST_SUCCESS_CMD_ENC_GET_RESULT_HOST_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_HOST_SUCCESS_CMD_ENC_GET_RESULT_HOST_SUCCESS_SHIFT)) & VPU_CMD_ENC_GET_RESULT_HOST_SUCCESS_CMD_ENC_GET_RESULT_HOST_SUCCESS_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1D - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1D_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1D_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1D_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1D_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1D_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED6 - Sub sampled base of index6 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED6_SUB_SAMPLED_FB_BASE6_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED6_SUB_SAMPLED_FB_BASE6_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED6_SUB_SAMPLED_FB_BASE6(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED6_SUB_SAMPLED_FB_BASE6_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED6_SUB_SAMPLED_FB_BASE6_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_D - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_D_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_D_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_D_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_D_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_D_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_D - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_D_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_D_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_D_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_D_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_D_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_LOWER - mv x sum lower */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_LOWER_L0_MV_X_SUIM_LOWER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_LOWER_L0_MV_X_SUIM_LOWER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_LOWER_L0_MV_X_SUIM_LOWER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_LOWER_L0_MV_X_SUIM_LOWER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_LOWER_L0_MV_X_SUIM_LOWER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1E - Display picture address for release */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1E_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1E_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1E_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1E_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_RELEASE_LINEAR_ADDR_1E_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y7 - Luma base of index7 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y7_LUMA_BASE7_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y7_LUMA_BASE7_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y7_LUMA_BASE7(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y7_LUMA_BASE7_SHIFT)) & VPU_CMD_SET_FB_FBC_Y7_LUMA_BASE7_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_E - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_E_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_E_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_E_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_E_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_E_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_E - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_E_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_E_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_E_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_E_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_E_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_HIGHER - mv x sum higher */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_HIGHER_L0_MV_X_SUIM_HIGHER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_HIGHER_L0_MV_X_SUIM_HIGHER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_HIGHER_L0_MV_X_SUIM_HIGHER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_HIGHER_L0_MV_X_SUIM_HIGHER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME0_X_DIR_HIGHER_L0_MV_X_SUIM_HIGHER_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C7 - Cb base of index7 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C7_CB_BASE7_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C7_CB_BASE7_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C7_CB_BASE7(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C7_CB_BASE7_SHIFT)) & VPU_CMD_SET_FB_FBC_C7_CB_BASE7_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_F - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_F_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_F_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_F_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_F_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_F_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_F - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_F_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_F_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_F_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_F_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_F_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DETECTED_STREAM_END - cmd_dec_get_result_detected_stream_end */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DETECTED_STREAM_END_DETECT_STREAM_END_MASK (0x1U) #define VPU_CMD_DEC_GET_RESULT_DETECTED_STREAM_END_DETECT_STREAM_END_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DETECTED_STREAM_END_DETECT_STREAM_END(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DETECTED_STREAM_END_DETECT_STREAM_END_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DETECTED_STREAM_END_DETECT_STREAM_END_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_LOWER - mv y sum lower */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_LOWER_L0_MV_Y_SUIM_LOWER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_LOWER_L0_MV_Y_SUIM_LOWER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_LOWER_L0_MV_Y_SUIM_LOWER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_LOWER_L0_MV_Y_SUIM_LOWER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_LOWER_L0_MV_Y_SUIM_LOWER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_0 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_0_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_0_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_0_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_0_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_0_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET7 - FBC luma offset base of index7 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET7_FBC_LUMA_OFFSET_BASE7_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET7_FBC_LUMA_OFFSET_BASE7_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET7_FBC_LUMA_OFFSET_BASE7(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET7_FBC_LUMA_OFFSET_BASE7_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET7_FBC_LUMA_OFFSET_BASE7_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_10 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_10_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_10_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_10_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_10_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_10_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_10 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_10_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_10_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_10_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_10_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_10_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DECODED_FLAG - Validation for decoded address */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DECODED_FLAG_DECODED_FLAG_MASK (0x1U) #define VPU_CMD_DEC_GET_RESULT_DECODED_FLAG_DECODED_FLAG_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DECODED_FLAG_DECODED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DECODED_FLAG_DECODED_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DECODED_FLAG_DECODED_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_HIGHER - mv y sum higher */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_HIGHER_L0_MV_Y_SUIM_HIGHER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_HIGHER_L0_MV_Y_SUIM_HIGHER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_HIGHER_L0_MV_Y_SUIM_HIGHER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_HIGHER_L0_MV_Y_SUIM_HIGHER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME0_Y_DIR_HIGHER_L0_MV_Y_SUIM_HIGHER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET7 - FBC chroma offset base of index7 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET7_FBC_CHROMA_OFFSET_BASE7_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET7_FBC_CHROMA_OFFSET_BASE7_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET7_FBC_CHROMA_OFFSET_BASE7(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET7_FBC_CHROMA_OFFSET_BASE7_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET7_FBC_CHROMA_OFFSET_BASE7_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_11 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_11_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_11_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_11_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_11_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_11_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_11 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_11_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_11_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_11_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_11_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_11_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_LOWER - mv x sum lower */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_LOWER_L1_MV_X_SUIM_LOWER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_LOWER_L1_MV_X_SUIM_LOWER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_LOWER_L1_MV_X_SUIM_LOWER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_LOWER_L1_MV_X_SUIM_LOWER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_LOWER_L1_MV_X_SUIM_LOWER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_2 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_2_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_2_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_2_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_2_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_2_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL7 - info base of index7 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL7_COL_BASE7_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL7_COL_BASE7_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL7_COL_BASE7(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL7_COL_BASE7_SHIFT)) & VPU_CMD_SET_FB_MV_COL7_COL_BASE7_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_12 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_12_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_12_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_12_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_12_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_12_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_12 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_12_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_12_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_12_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_12_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_12_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_WARN_INFO - Warning information */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_WARN_INFO_DEC_WARN_INFO_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_WARN_INFO_DEC_WARN_INFO_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_WARN_INFO_DEC_WARN_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_WARN_INFO_DEC_WARN_INFO_SHIFT)) & VPU_CMD_DEC_GET_RESULT_WARN_INFO_DEC_WARN_INFO_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_HIGHER - mv x sum higher */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_HIGHER_L1_MV_X_SUIM_HIGHER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_HIGHER_L1_MV_X_SUIM_HIGHER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_HIGHER_L1_MV_X_SUIM_HIGHER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_HIGHER_L1_MV_X_SUIM_HIGHER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME1_X_DIR_HIGHER_L1_MV_X_SUIM_HIGHER_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_3 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_3_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_3_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_3_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_3_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_3_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED7 - Sub sampled base of index7 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED7_SUB_SAMPLED_FB_BASE7_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED7_SUB_SAMPLED_FB_BASE7_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED7_SUB_SAMPLED_FB_BASE7(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED7_SUB_SAMPLED_FB_BASE7_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED7_SUB_SAMPLED_FB_BASE7_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_13 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_13_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_13_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_13_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_13_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_13_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_13 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_13_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_13_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_13_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_13_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_13_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_ERR_INFO - Error information */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_ERR_INFO_ERROR_INFO_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_ERR_INFO_ERROR_INFO_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_ERR_INFO_ERROR_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_ERR_INFO_ERROR_INFO_SHIFT)) & VPU_CMD_DEC_GET_RESULT_ERR_INFO_ERROR_INFO_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_LOWER - mv y sum lower */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_LOWER_L1_MV_Y_SUIM_LOWER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_LOWER_L1_MV_Y_SUIM_LOWER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_LOWER_L1_MV_Y_SUIM_LOWER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_LOWER_L1_MV_Y_SUIM_LOWER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_LOWER_L1_MV_Y_SUIM_LOWER_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_TILE_PARAM - Tile parameters */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_COL_M1_MASK (0xFU) #define VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_COL_M1_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_COL_M1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_COL_M1_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_COL_M1_MASK) #define VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_ROW_M1_MASK (0xF0U) #define VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_ROW_M1_SHIFT (4U) #define VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_ROW_M1(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_ROW_M1_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TILE_PARAM_TILE_NUM_IN_ROW_M1_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_4 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_4_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_4_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_4_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_4_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_4_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y8 - Luma base of index8 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y8_LUMA_BASE8_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y8_LUMA_BASE8_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y8_LUMA_BASE8(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y8_LUMA_BASE8_SHIFT)) & VPU_CMD_SET_FB_FBC_Y8_LUMA_BASE8_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_14 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_14_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_14_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_14_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_14_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_14_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_14 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_14_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_14_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_14_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_14_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_14_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DECODING_SUCCESS - Query result */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DECODING_SUCCESS_QUERY_DEC_SUCCESS_MASK (0x3U) #define VPU_CMD_DEC_GET_RESULT_DECODING_SUCCESS_QUERY_DEC_SUCCESS_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DECODING_SUCCESS_QUERY_DEC_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DECODING_SUCCESS_QUERY_DEC_SUCCESS_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DECODING_SUCCESS_QUERY_DEC_SUCCESS_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_HIGHER - mv y sum higher */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_HIGHER_L1_MV_Y_SUIM_HIGHER_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_HIGHER_L1_MV_Y_SUIM_HIGHER_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_HIGHER_L1_MV_Y_SUIM_HIGHER(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_HIGHER_L1_MV_Y_SUIM_HIGHER_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUM_ME1_Y_DIR_HIGHER_L1_MV_Y_SUIM_HIGHER_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_0_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_5 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_5_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_5_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_5_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_5_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_5_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C8 - Cb base of index8 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C8_CB_BASE8_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C8_CB_BASE8_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C8_CB_BASE8(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C8_CB_BASE8_SHIFT)) & VPU_CMD_SET_FB_FBC_C8_CB_BASE8_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_15 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_15_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_15_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_15_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_15_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_15_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_15 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_15_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_15_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_15_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_15_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_15_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_TIMESTAMP - cmd_dec_get_result_timestamp */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_TIMESTAMP_timestamp_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_TIMESTAMP_timestamp_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_TIMESTAMP_timestamp(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_TIMESTAMP_timestamp_SHIFT)) & VPU_CMD_DEC_GET_RESULT_TIMESTAMP_timestamp_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_1_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_6 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_6_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_6_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_6_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_6_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_6_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET8 - FBC luma offset base of index8 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET8_FBC_LUMA_OFFSET_BASE8_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET8_FBC_LUMA_OFFSET_BASE8_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET8_FBC_LUMA_OFFSET_BASE8(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET8_FBC_LUMA_OFFSET_BASE8_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET8_FBC_LUMA_OFFSET_BASE8_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_16 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_16_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_16_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_16_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_16_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_16_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_16 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_16_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_16_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_16_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_16_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_16_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_2_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_7 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_7_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_7_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_7_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_7_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_7_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET8 - FBC chroma offset base of index8 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET8_FBC_CHROMA_OFFSET_BASE8_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET8_FBC_CHROMA_OFFSET_BASE8_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET8_FBC_CHROMA_OFFSET_BASE8(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET8_FBC_CHROMA_OFFSET_BASE8_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET8_FBC_CHROMA_OFFSET_BASE8_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_17 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_17_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_17_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_17_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_17_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_17_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_17 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_17_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_17_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_17_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_17_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_17_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_LAST_FRAME_FLAG - ret_last_frame_flag */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_LAST_FRAME_FLAG_LAST_FRAME_FLAG_MASK (0x1U) #define VPU_CMD_DEC_GET_RESULT_LAST_FRAME_FLAG_LAST_FRAME_FLAG_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_LAST_FRAME_FLAG_LAST_FRAME_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_LAST_FRAME_FLAG_LAST_FRAME_FLAG_SHIFT)) & VPU_CMD_DEC_GET_RESULT_LAST_FRAME_FLAG_LAST_FRAME_FLAG_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_3_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_8 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_8_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_8_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_8_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_8_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_8_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL8 - info base of index8 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL8_COL_BASE8_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL8_COL_BASE8_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL8_COL_BASE8(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL8_COL_BASE8_SHIFT)) & VPU_CMD_SET_FB_MV_COL8_COL_BASE8_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_18 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_18_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_18_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_18_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_18_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_18_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_18 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_18_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_18_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_18_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_18_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_18_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_NUM_REQUIRED_COL_BUF - Required Number of Minimum col buf */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_MASK (0x1FU) #define VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_SHIFT)) & VPU_CMD_DEC_GET_RESULT_NUM_REQUIRED_COL_BUF_MIN_COL_BUF_NUM_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_4_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_9 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_9_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_9_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_9_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_9_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_9_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED8 - Sub sampled base of index8 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED8_SUB_SAMPLED_FB_BASE8_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED8_SUB_SAMPLED_FB_BASE8_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED8_SUB_SAMPLED_FB_BASE8(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED8_SUB_SAMPLED_FB_BASE8_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED8_SUB_SAMPLED_FB_BASE8_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_19 - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_19_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_19_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_19_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_19_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_19_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_19 - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_19_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_19_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_19_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_19_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_19_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_0 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_0_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_0_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_0_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_0_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_0_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SRC_ADDR_Y - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SRC_ADDR_Y_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SRC_ADDR_Y_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SRC_ADDR_Y_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SRC_ADDR_Y_SRC_PIC_ADDR_Y_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SRC_ADDR_Y_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_5_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_A - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_A_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_A_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_A_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_A_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_A_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y9 - Luma base of index9 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y9_LUMA_BASE9_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y9_LUMA_BASE9_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y9_LUMA_BASE9(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y9_LUMA_BASE9_SHIFT)) & VPU_CMD_SET_FB_FBC_Y9_LUMA_BASE9_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1A - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1A_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1A_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1A_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1A_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1A_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_1A - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1A_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1A_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1A_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1A_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1A_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_CUSTOM_MAP_OPTION_ADDR - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_CMD_ENC_GET_RESULT_CUSTOM_MAP_OPTION_ADDR_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_6_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_B - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_B_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_B_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_B_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_B_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_B_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C9 - Cb base of index9 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C9_CB_BASE9_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C9_CB_BASE9_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C9_CB_BASE9(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C9_CB_BASE9_SHIFT)) & VPU_CMD_SET_FB_FBC_C9_CB_BASE9_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1B - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1B_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1B_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1B_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1B_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1B_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_1B - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1B_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1B_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1B_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1B_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1B_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_2 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_2_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_2_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_2_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_2_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_2_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_PREFIX_SEI_NAL_ADDR - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_CMD_ENC_GET_RESULT_PREFIX_SEI_NAL_ADDR_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_7_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_C - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_C_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_C_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_C_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_C_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_C_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET9 - FBC luma offset base of index9 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET9_FBC_LUMA_OFFSET_BASE9_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET9_FBC_LUMA_OFFSET_BASE9_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET9_FBC_LUMA_OFFSET_BASE9(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET9_FBC_LUMA_OFFSET_BASE9_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET9_FBC_LUMA_OFFSET_BASE9_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1C - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1C_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1C_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1C_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1C_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1C_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_1C - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1C_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1C_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1C_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1C_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1C_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_3 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_3_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_3_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_3_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_3_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_3_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SUFFIX_SEI_NAL_ADDR - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SUFFIX_SEI_NAL_ADDR_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_8_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_D - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_D_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_D_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_D_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_D_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_D_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET9 - FBC chroma offset base of index9 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET9_FBC_CHROMA_OFFSET_BASE9_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET9_FBC_CHROMA_OFFSET_BASE9_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET9_FBC_CHROMA_OFFSET_BASE9(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET9_FBC_CHROMA_OFFSET_BASE9_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET9_FBC_CHROMA_OFFSET_BASE9_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1D - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1D_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1D_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1D_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1D_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1D_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_1D - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1D_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1D_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1D_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1D_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1D_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_4 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_4_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_4_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_4_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_4_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_4_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SRC_DEBUG_0 - cmd_enc_get_result_src_debug_0 */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_0_SFS_DEBUG_INFO_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_0_SFS_DEBUG_INFO_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_0_SFS_DEBUG_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_0_SFS_DEBUG_INFO_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_0_SFS_DEBUG_INFO_MASK) /*! @} */ /*! @name CMD_ENC_PIC_TIMESTAMP - cmd_enc_pic_timestamp */ /*! @{ */ #define VPU_CMD_ENC_PIC_TIMESTAMP_timestamp_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_PIC_TIMESTAMP_timestamp_SHIFT (0U) #define VPU_CMD_ENC_PIC_TIMESTAMP_timestamp(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_PIC_TIMESTAMP_timestamp_SHIFT)) & VPU_CMD_ENC_PIC_TIMESTAMP_timestamp_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_9_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_E - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_E_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_E_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_E_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_E_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_E_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL9 - info base of index9 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL9_COL_BASE9_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL9_COL_BASE9_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL9_COL_BASE9(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL9_COL_BASE9_SHIFT)) & VPU_CMD_SET_FB_MV_COL9_COL_BASE9_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1E - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1E_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1E_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1E_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1E_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1E_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_1E - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1E_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1E_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1E_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1E_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1E_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_5 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_5_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_5_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_5_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_5_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_5_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_SRC_DEBUG_1 - cmd_enc_get_result_src_debug_1 */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_1_SFS_DEBUG_INFO_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_1_SFS_DEBUG_INFO_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_1_SFS_DEBUG_INFO(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_1_SFS_DEBUG_INFO_SHIFT)) & VPU_CMD_ENC_GET_RESULT_SRC_DEBUG_1_SFS_DEBUG_INFO_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_10_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_F - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_F_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_F_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_F_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_F_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_F_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED9 - Sub sampled base of index9 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED9_SUB_SAMPLED_FB_BASE9_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED9_SUB_SAMPLED_FB_BASE9_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED9_SUB_SAMPLED_FB_BASE9(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED9_SUB_SAMPLED_FB_BASE9_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED9_SUB_SAMPLED_FB_BASE9_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1F - Y component source address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1F_SRC_PIC_ADDR_Y_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1F_SRC_PIC_ADDR_Y_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1F_SRC_PIC_ADDR_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1F_SRC_PIC_ADDR_Y_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SRC_ADDR_Y_1F_SRC_PIC_ADDR_Y_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_BS_RD_ADDR_1F - Bitstream buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1F_BS_RD_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1F_BS_RD_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1F_BS_RD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1F_BS_RD_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_BS_RD_ADDR_1F_BS_RD_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_6 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_6_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_6_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_6_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_6_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_6_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_11_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_10 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_10_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_10_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_10_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_10_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_10_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y10 - Luma base of index10 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y10_LUMA_BASE10_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y10_LUMA_BASE10_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y10_LUMA_BASE10(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y10_LUMA_BASE10_SHIFT)) & VPU_CMD_SET_FB_FBC_Y10_LUMA_BASE10_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_0 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_0_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_0_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_0_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_0_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_0_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_0 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_0_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_0_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_0_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_0_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_0_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_7 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_7_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_7_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_7_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_7_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_7_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_GET_RESULT_NUM_REQUIRED_COL_FB - Minimum number of col frame buffer required for encoding */ /*! @{ */ #define VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_COL_FB_RET_MIN_COL_FB_BUF_NUM_MASK (0xFFFFFFFFU) #define VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_COL_FB_RET_MIN_COL_FB_BUF_NUM_SHIFT (0U) #define VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_COL_FB_RET_MIN_COL_FB_BUF_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_COL_FB_RET_MIN_COL_FB_BUF_NUM_SHIFT)) & VPU_CMD_ENC_GET_RESULT_NUM_REQUIRED_COL_FB_RET_MIN_COL_FB_BUF_NUM_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_12_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_11 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_11_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_11_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_11_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_11_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_11_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C10 - Cb base of index10 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C10_CB_BASE10_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C10_CB_BASE10_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C10_CB_BASE10(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C10_CB_BASE10_SHIFT)) & VPU_CMD_SET_FB_FBC_C10_CB_BASE10_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_1 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_1_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_1_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_8 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_8_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_8_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_8_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_8_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_8_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_13_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_12 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_12_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_12_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_12_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_12_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_12_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET10 - FBC luma offset base of index10 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET10_FBC_LUMA_OFFSET_BASE10_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET10_FBC_LUMA_OFFSET_BASE10_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET10_FBC_LUMA_OFFSET_BASE10(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET10_FBC_LUMA_OFFSET_BASE10_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET10_FBC_LUMA_OFFSET_BASE10_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_2 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_2_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_2_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_2_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_2_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_2_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_2 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_2_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_2_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_2_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_2_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_2_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_9 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_9_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_9_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_9_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_9_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_9_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_14_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_13 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_13_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_13_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_13_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_13_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_13_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET10 - FBC chroma offset base of index10 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET10_FBC_CHROMA_OFFSET_BASE10_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET10_FBC_CHROMA_OFFSET_BASE10_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET10_FBC_CHROMA_OFFSET_BASE10(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET10_FBC_CHROMA_OFFSET_BASE10_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET10_FBC_CHROMA_OFFSET_BASE10_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_3 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_3_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_3_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_3_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_3_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_3_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_3 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_3_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_3_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_3_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_3_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_3_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_A - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_A_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_A_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_A_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_A_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_A_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_15_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_14 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_14_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_14_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_14_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_14_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_14_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL10 - info base of index10 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL10_COL_BASE10_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL10_COL_BASE10_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL10_COL_BASE10(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL10_COL_BASE10_SHIFT)) & VPU_CMD_SET_FB_MV_COL10_COL_BASE10_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_4 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_4_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_4_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_4_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_4_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_4_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_4 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_4_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_4_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_4_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_4_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_4_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_B - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_B_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_B_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_B_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_B_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_B_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_16_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_15 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_15_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_15_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_15_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_15_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_15_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED10 - Sub sampled base of index10 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED10_FBC_CHROMA_OFFSET_BASE10_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED10_FBC_CHROMA_OFFSET_BASE10_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED10_FBC_CHROMA_OFFSET_BASE10(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED10_FBC_CHROMA_OFFSET_BASE10_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED10_FBC_CHROMA_OFFSET_BASE10_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_5 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_5_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_5_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_5_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_5_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_5_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_5 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_5_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_5_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_5_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_5_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_5_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_C - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_C_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_C_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_C_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_C_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_C_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_17_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_16 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_16_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_16_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_16_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_16_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_16_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y11 - Luma base of index11 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y11_LUMA_BASE11_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y11_LUMA_BASE11_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y11_LUMA_BASE11(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y11_LUMA_BASE11_SHIFT)) & VPU_CMD_SET_FB_FBC_Y11_LUMA_BASE11_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_6 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_6_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_6_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_6_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_6_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_6_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_6 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_6_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_6_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_6_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_6_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_6_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_D - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_D_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_D_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_D_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_D_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_D_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_18_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_17 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_17_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_17_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_17_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_17_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_17_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C11 - Cb base of index11 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C11_CB_BASE11_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C11_CB_BASE11_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C11_CB_BASE11(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C11_CB_BASE11_SHIFT)) & VPU_CMD_SET_FB_FBC_C11_CB_BASE11_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_7 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_7_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_7_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_7_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_7_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_7_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_7 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_7_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_7_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_7_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_7_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_7_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_E - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_E_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_E_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_E_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_E_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_E_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_19_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_18 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_18_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_18_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_18_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_18_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_18_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET11 - FBC luma offset base of index11 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET11_FBC_LUMA_OFFSET_BASE11_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET11_FBC_LUMA_OFFSET_BASE11_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET11_FBC_LUMA_OFFSET_BASE11(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET11_FBC_LUMA_OFFSET_BASE11_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET11_FBC_LUMA_OFFSET_BASE11_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_8 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_8_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_8_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_8_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_8_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_8_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_8 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_8_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_8_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_8_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_8_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_8_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_F - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_F_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_F_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_F_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_F_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_F_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_20_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_19 - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_19_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_19_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_19_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_19_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_19_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET11 - FBC chroma offset base of index11 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET11_FBC_CHROMA_OFFSET_BASE11_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET11_FBC_CHROMA_OFFSET_BASE11_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET11_FBC_CHROMA_OFFSET_BASE11(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET11_FBC_CHROMA_OFFSET_BASE11_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET11_FBC_CHROMA_OFFSET_BASE11_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_9 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_9_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_9_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_9_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_9_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_9_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_9 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_9_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_9_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_9_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_9_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_9_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_10 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_10_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_10_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_10_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_10_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_10_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_21_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1A - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1A_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1A_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1A_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1A_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1A_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL11 - info base of index11 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL11_COL_BASE11_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL11_COL_BASE11_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL11_COL_BASE11(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL11_COL_BASE11_SHIFT)) & VPU_CMD_SET_FB_MV_COL11_COL_BASE11_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_A - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_A_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_A_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_A_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_A_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_A_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_A - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_A_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_A_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_A_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_A_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_A_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_11 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_11_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_11_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_11_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_11_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_11_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_22_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1B - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1B_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1B_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1B_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1B_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1B_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED11 - Sub sampled base of index11 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED11_FBC_CHROMA_OFFSET_BASE11_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED11_FBC_CHROMA_OFFSET_BASE11_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED11_FBC_CHROMA_OFFSET_BASE11(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED11_FBC_CHROMA_OFFSET_BASE11_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED11_FBC_CHROMA_OFFSET_BASE11_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_B - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_B_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_B_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_B_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_B_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_B_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_B - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_B_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_B_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_B_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_B_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_B_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_12 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_12_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_12_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_12_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_12_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_12_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_23_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1C - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1C_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1C_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1C_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1C_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1C_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y12 - Luma base of index12 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y12_LUMA_BASE12_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y12_LUMA_BASE12_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y12_LUMA_BASE12(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y12_LUMA_BASE12_SHIFT)) & VPU_CMD_SET_FB_FBC_Y12_LUMA_BASE12_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_C - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_C_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_C_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_C_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_C_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_C_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_C - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_C_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_C_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_C_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_C_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_C_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_13 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_13_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_13_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_13_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_13_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_13_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_24_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1D - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1D_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1D_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1D_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1D_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1D_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C12 - Cb base of index12 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C12_CB_BASE12_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C12_CB_BASE12_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C12_CB_BASE12(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C12_CB_BASE12_SHIFT)) & VPU_CMD_SET_FB_FBC_C12_CB_BASE12_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_D - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_D_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_D_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_D_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_D_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_D_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_D - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_D_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_D_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_D_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_D_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_D_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_14 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_14_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_14_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_14_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_14_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_14_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_25_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1E - Linear buffer address to be displayed */ /*! @{ */ #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1E_DISP_LINEAR_BUFFER_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1E_DISP_LINEAR_BUFFER_ADDR_SHIFT (0U) #define VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1E_DISP_LINEAR_BUFFER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1E_DISP_LINEAR_BUFFER_ADDR_SHIFT)) & VPU_CMD_GET_FB_UPDATE_STATUS_DISPLAY_LINEAR_ADDR_1E_DISP_LINEAR_BUFFER_ADDR_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET12 - FBC luma offset base of index12 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET12_FBC_LUMA_OFFSET_BASE12_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET12_FBC_LUMA_OFFSET_BASE12_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET12_FBC_LUMA_OFFSET_BASE12(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET12_FBC_LUMA_OFFSET_BASE12_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET12_FBC_LUMA_OFFSET_BASE12_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_E - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_E_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_E_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_E_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_E_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_E_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_E - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_E_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_E_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_E_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_E_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_E_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_15 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_15_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_15_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_15_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_15_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_15_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_26_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET12 - FBC chroma offset base of index12 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET12_FBC_CHROMA_OFFSET_BASE12_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET12_FBC_CHROMA_OFFSET_BASE12_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET12_FBC_CHROMA_OFFSET_BASE12(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET12_FBC_CHROMA_OFFSET_BASE12_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET12_FBC_CHROMA_OFFSET_BASE12_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_F - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_F_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_F_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_F_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_F_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_F_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_F - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_F_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_F_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_F_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_F_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_F_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_16 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_16_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_16_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_16_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_16_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_16_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_27_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL12 - info base of index12 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL12_COL_BASE12_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL12_COL_BASE12_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL12_COL_BASE12(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL12_COL_BASE12_SHIFT)) & VPU_CMD_SET_FB_MV_COL12_COL_BASE12_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_10 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_10_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_10_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_10_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_10_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_10_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_10 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_10_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_10_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_10_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_10_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_10_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_17 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_17_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_17_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_17_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_17_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_17_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_28_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED12 - Sub sampled base of index12 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED12_FBC_CHROMA_OFFSET_BASE12_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED12_FBC_CHROMA_OFFSET_BASE12_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED12_FBC_CHROMA_OFFSET_BASE12(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED12_FBC_CHROMA_OFFSET_BASE12_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED12_FBC_CHROMA_OFFSET_BASE12_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_11 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_11_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_11_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_11_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_11_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_11_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_11 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_11_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_11_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_11_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_11_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_11_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_18 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_18_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_18_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_18_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_18_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_18_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_29_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y13 - Luma base of index13 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y13_LUMA_BASE13_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y13_LUMA_BASE13_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y13_LUMA_BASE13(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y13_LUMA_BASE13_SHIFT)) & VPU_CMD_SET_FB_FBC_Y13_LUMA_BASE13_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_12 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_12_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_12_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_12_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_12_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_12_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_12 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_12_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_12_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_12_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_12_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_12_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_19 - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_19_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_19_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_19_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_19_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_19_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_30_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C13 - Cb base of index13 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C13_CB_BASE13_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C13_CB_BASE13_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C13_CB_BASE13(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C13_CB_BASE13_SHIFT)) & VPU_CMD_SET_FB_FBC_C13_CB_BASE13_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_13 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_13_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_13_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_13_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_13_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_13_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_13 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_13_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_13_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_13_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_13_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_13_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1A - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1A_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1A_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1A_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1A_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1A_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_31_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET13 - FBC luma offset base of index13 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET13_FBC_LUMA_OFFSET_BASE13_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET13_FBC_LUMA_OFFSET_BASE13_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET13_FBC_LUMA_OFFSET_BASE13(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET13_FBC_LUMA_OFFSET_BASE13_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET13_FBC_LUMA_OFFSET_BASE13_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_14 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_14_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_14_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_14_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_14_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_14_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_14 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_14_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_14_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_14_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_14_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_14_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1B - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1B_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1B_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1B_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1B_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1B_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_32_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET13 - FBC chroma offset base of index13 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET13_FBC_CHROMA_OFFSET_BASE13_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET13_FBC_CHROMA_OFFSET_BASE13_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET13_FBC_CHROMA_OFFSET_BASE13(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET13_FBC_CHROMA_OFFSET_BASE13_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET13_FBC_CHROMA_OFFSET_BASE13_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_15 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_15_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_15_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_15_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_15_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_15_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_15 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_15_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_15_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_15_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_15_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_15_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1C - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1C_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1C_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1C_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1C_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1C_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_33_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL13 - info base of index13 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL13_COL_BASE13_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL13_COL_BASE13_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL13_COL_BASE13(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL13_COL_BASE13_SHIFT)) & VPU_CMD_SET_FB_MV_COL13_COL_BASE13_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_16 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_16_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_16_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_16_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_16_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_16_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_16 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_16_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_16_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_16_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_16_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_16_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1D - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1D_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1D_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1D_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1D_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1D_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_34_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED13 - Sub sampled base of index13 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED13_FBC_CHROMA_OFFSET_BASE13_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED13_FBC_CHROMA_OFFSET_BASE13_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED13_FBC_CHROMA_OFFSET_BASE13(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED13_FBC_CHROMA_OFFSET_BASE13_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED13_FBC_CHROMA_OFFSET_BASE13_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_17 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_17_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_17_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_17_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_17_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_17_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_17 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_17_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_17_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_17_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_17_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_17_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1E - Display picture address for release */ /*! @{ */ #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1E_DISP_PIC_RELEASE_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1E_DISP_PIC_RELEASE_ADDR_SHIFT (0U) #define VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1E_DISP_PIC_RELEASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1E_DISP_PIC_RELEASE_ADDR_SHIFT)) & VPU_CMD_DEC_GET_RESULT_DISP_RELEASE_ADDR_1E_DISP_PIC_RELEASE_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_35_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y14 - Luma base of index14 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y14_LUMA_BASE14_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y14_LUMA_BASE14_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y14_LUMA_BASE14(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y14_LUMA_BASE14_SHIFT)) & VPU_CMD_SET_FB_FBC_Y14_LUMA_BASE14_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_18 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_18_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_18_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_18_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_18_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_18_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_18 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_18_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_18_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_18_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_18_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_18_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_36_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C14 - Cb base of index14 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C14_CB_BASE14_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C14_CB_BASE14_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C14_CB_BASE14(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C14_CB_BASE14_SHIFT)) & VPU_CMD_SET_FB_FBC_C14_CB_BASE14_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_19 - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_19_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_19_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_19_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_19_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_19_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_19 - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_19_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_19_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_19_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_19_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_19_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_37_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET14 - FBC luma offset base of index14 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET14_FBC_LUMA_OFFSET_BASE14_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET14_FBC_LUMA_OFFSET_BASE14_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET14_FBC_LUMA_OFFSET_BASE14(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET14_FBC_LUMA_OFFSET_BASE14_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET14_FBC_LUMA_OFFSET_BASE14_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1A - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1A_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1A_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1A_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1A_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1A_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_1A - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1A_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1A_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1A_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_1A_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_1A_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_38_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET14 - FBC chroma offset base of index14 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET14_FBC_CHROMA_OFFSET_BASE14_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET14_FBC_CHROMA_OFFSET_BASE14_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET14_FBC_CHROMA_OFFSET_BASE14(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET14_FBC_CHROMA_OFFSET_BASE14_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET14_FBC_CHROMA_OFFSET_BASE14_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1B - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1B_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1B_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1B_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1B_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1B_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_1B - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1B_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1B_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1B_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_1B_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_1B_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_39_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL14 - info base of index14 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL14_COL_BASE14_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL14_COL_BASE14_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL14_COL_BASE14(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL14_COL_BASE14_SHIFT)) & VPU_CMD_SET_FB_MV_COL14_COL_BASE14_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1C - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1C_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1C_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1C_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1C_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1C_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_1C - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1C_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1C_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1C_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_1C_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_1C_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_40_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED14 - Sub sampled base of index14 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED14_FBC_CHROMA_OFFSET_BASE14_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED14_FBC_CHROMA_OFFSET_BASE14_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED14_FBC_CHROMA_OFFSET_BASE14(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED14_FBC_CHROMA_OFFSET_BASE14_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED14_FBC_CHROMA_OFFSET_BASE14_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1D - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1D_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1D_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1D_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1D_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1D_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_1D - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1D_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1D_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1D_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_1D_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_1D_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_41_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y15 - Luma base of index15 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y15_LUMA_BASE15_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y15_LUMA_BASE15_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y15_LUMA_BASE15(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y15_LUMA_BASE15_SHIFT)) & VPU_CMD_SET_FB_FBC_Y15_LUMA_BASE15_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1E - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1E_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1E_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1E_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1E_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1E_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_1E - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1E_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1E_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1E_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_1E_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_1E_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_42_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C15 - Cb base of index15 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C15_CB_BASE15_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C15_CB_BASE15_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C15_CB_BASE15(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C15_CB_BASE15_SHIFT)) & VPU_CMD_SET_FB_FBC_C15_CB_BASE15_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1F - Custom map address used for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1F_CUSTOM_MAP_OPTION_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1F_CUSTOM_MAP_OPTION_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1F_CUSTOM_MAP_OPTION_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1F_CUSTOM_MAP_OPTION_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_CUSTOM_MAP_OPTION_ADDR_1F_CUSTOM_MAP_OPTION_ADDR_MASK) /*! @} */ /*! @name RET_FLUSH_CMD_INFO_USER_DATA_1F - User data buffer address */ /*! @{ */ #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1F_USERDATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1F_USERDATA_ADDR_SHIFT (0U) #define VPU_RET_FLUSH_CMD_INFO_USER_DATA_1F_USERDATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_FLUSH_CMD_INFO_USER_DATA_1F_USERDATA_ADDR_SHIFT)) & VPU_RET_FLUSH_CMD_INFO_USER_DATA_1F_USERDATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_43_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_Y_OFFSET15 - FBC luma offset base of index15 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_Y_OFFSET15_FBC_LUMA_OFFSET_BASE15_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_Y_OFFSET15_FBC_LUMA_OFFSET_BASE15_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_Y_OFFSET15_FBC_LUMA_OFFSET_BASE15(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_Y_OFFSET15_FBC_LUMA_OFFSET_BASE15_SHIFT)) & VPU_CMD_SET_FB_FBC_Y_OFFSET15_FBC_LUMA_OFFSET_BASE15_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_0 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_0_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_0_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_0_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_0_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_0_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_44_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_FBC_C_OFFSET15 - FBC chroma offset base of index15 */ /*! @{ */ #define VPU_CMD_SET_FB_FBC_C_OFFSET15_FBC_CHROMA_OFFSET_BASE15_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_FBC_C_OFFSET15_FBC_CHROMA_OFFSET_BASE15_SHIFT (0U) #define VPU_CMD_SET_FB_FBC_C_OFFSET15_FBC_CHROMA_OFFSET_BASE15(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_FBC_C_OFFSET15_FBC_CHROMA_OFFSET_BASE15_SHIFT)) & VPU_CMD_SET_FB_FBC_C_OFFSET15_FBC_CHROMA_OFFSET_BASE15_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_45_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL15 - info base of index15 */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL15_COL_BASE15_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL15_COL_BASE15_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL15_COL_BASE15(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL15_COL_BASE15_SHIFT)) & VPU_CMD_SET_FB_MV_COL15_COL_BASE15_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_2 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_2_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_2_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_2_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_2_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_2_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_46_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_SUB_SAMPLED15 - Sub sampled base of index15 */ /*! @{ */ #define VPU_CMD_SET_FB_SUB_SAMPLED15_FBC_CHROMA_OFFSET_BASE15_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SUB_SAMPLED15_FBC_CHROMA_OFFSET_BASE15_SHIFT (0U) #define VPU_CMD_SET_FB_SUB_SAMPLED15_FBC_CHROMA_OFFSET_BASE15(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SUB_SAMPLED15_FBC_CHROMA_OFFSET_BASE15_SHIFT)) & VPU_CMD_SET_FB_SUB_SAMPLED15_FBC_CHROMA_OFFSET_BASE15_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_3 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_3_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_3_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_3_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_3_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_3_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_47_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_ADDR_REPORT_BUFFER - Report buffer start address */ /*! @{ */ #define VPU_CMD_SET_FB_ADDR_REPORT_BUFFER_REPORT_START_ADDR_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_ADDR_REPORT_BUFFER_REPORT_START_ADDR_SHIFT (0U) #define VPU_CMD_SET_FB_ADDR_REPORT_BUFFER_REPORT_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_ADDR_REPORT_BUFFER_REPORT_START_ADDR_SHIFT)) & VPU_CMD_SET_FB_ADDR_REPORT_BUFFER_REPORT_START_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_4 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_4_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_4_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_4_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_4_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_4_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_48_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_DEFAULT_CDF - base of default cdf buffer */ /*! @{ */ #define VPU_CMD_SET_FB_DEFAULT_CDF_DEFAULT_CDF_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_DEFAULT_CDF_DEFAULT_CDF_BASE_SHIFT (0U) #define VPU_CMD_SET_FB_DEFAULT_CDF_DEFAULT_CDF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_DEFAULT_CDF_DEFAULT_CDF_BASE_SHIFT)) & VPU_CMD_SET_FB_DEFAULT_CDF_DEFAULT_CDF_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_5 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_5_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_5_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_5_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_5_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_5_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_49_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_SEGMAP - base of seg map buffer */ /*! @{ */ #define VPU_CMD_SET_FB_SEGMAP_SEGMAP_BUF_BASE_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_SEGMAP_SEGMAP_BUF_BASE_SHIFT (0U) #define VPU_CMD_SET_FB_SEGMAP_SEGMAP_BUF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_SEGMAP_SEGMAP_BUF_BASE_SHIFT)) & VPU_CMD_SET_FB_SEGMAP_SEGMAP_BUF_BASE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_6 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_6_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_6_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_6_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_6_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_6_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_50_LAMBDA_SSD_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_7 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_7_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_7_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_7_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_7_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_7_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51 - CUSTOM_LAMBDA_DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SAD_MASK (0x7FU) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SAD_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SAD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SAD_MASK) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SSD_MASK (0x1FFF80U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SSD_SHIFT (7U) #define VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SSD(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SSD_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CUSTOM_LAMBDA_51_LAMBDA_SSD_MASK) /*! @} */ /*! @name CMD_SET_FB_UPDATE_INDICES - DPB index to be updated */ /*! @{ */ #define VPU_CMD_SET_FB_UPDATE_INDICES_FBC_IDX_MASK (0xFFU) #define VPU_CMD_SET_FB_UPDATE_INDICES_FBC_IDX_SHIFT (0U) #define VPU_CMD_SET_FB_UPDATE_INDICES_FBC_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_INDICES_FBC_IDX_SHIFT)) & VPU_CMD_SET_FB_UPDATE_INDICES_FBC_IDX_MASK) #define VPU_CMD_SET_FB_UPDATE_INDICES_MVCOL_IDX_MASK (0xFF00U) #define VPU_CMD_SET_FB_UPDATE_INDICES_MVCOL_IDX_SHIFT (8U) #define VPU_CMD_SET_FB_UPDATE_INDICES_MVCOL_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_UPDATE_INDICES_MVCOL_IDX_SHIFT)) & VPU_CMD_SET_FB_UPDATE_INDICES_MVCOL_IDX_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_8 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_8_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_8_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_8_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_8_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_8_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP - TEMPORAL_LAYER_0_QP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_I_QP_MASK (0x3FU) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_I_QP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_I_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_I_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_I_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_P_QP_MASK (0xFC0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_P_QP_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_P_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_P_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_P_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_B_QP_MASK (0x3F000U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_B_QP_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_B_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_B_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_0_QP_B_QP_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_9 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_9_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_9_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_9_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_9_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_9_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP - TEMPORAL_LAYER_1_QP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_I_QP_MASK (0x3FU) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_I_QP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_I_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_I_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_I_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_P_QP_MASK (0xFC0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_P_QP_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_P_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_P_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_P_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_B_QP_MASK (0x3F000U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_B_QP_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_B_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_B_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_1_QP_B_QP_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_A - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_A_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_A_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_A_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_A_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_A_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP - TEMPORAL_LAYER_2_QP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_I_QP_MASK (0x3FU) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_I_QP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_I_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_I_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_I_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_P_QP_MASK (0xFC0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_P_QP_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_P_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_P_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_P_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_B_QP_MASK (0x3F000U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_B_QP_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_B_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_B_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_2_QP_B_QP_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_B - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_B_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_B_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_B_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_B_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_B_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP - TEMPORAL_LAYER_3_QP */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_I_QP_MASK (0x3FU) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_I_QP_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_I_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_I_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_I_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_P_QP_MASK (0xFC0U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_P_QP_SHIFT (6U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_P_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_P_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_P_QP_MASK) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_B_QP_MASK (0x3F000U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_B_QP_SHIFT (12U) #define VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_B_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_B_QP_SHIFT)) & VPU_CMD_ENC_SET_PARAM_TEMPORAL_LAYER_3_QP_B_QP_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_C - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_C_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_C_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_C_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_C_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_C_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_SCL_SRC_SIZE - SCALER SRC SIZE */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_WIDTH_MASK (0xFFFFU) #define VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_WIDTH_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_WIDTH_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_WIDTH_MASK) #define VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_HEIGHT_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_HEIGHT_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_HEIGHT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SCL_SRC_SIZE_PIC_HEIGHT_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_D - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_D_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_D_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_D_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_D_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_D_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_SCL_PARAM - SCALER PARAMETER */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_EN_MASK (0x1U) #define VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_EN_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_EN_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_EN_MASK) #define VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_COEF_MODE_MASK (0x6U) #define VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_COEF_MODE_SHIFT (1U) #define VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_COEF_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_COEF_MODE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SCL_PARAM_SCL_COEF_MODE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_E - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_E_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_E_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_E_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_E_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_E_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_Y2Y_PARAM - Y2Y PARAMETER */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_Y2Y_PARAM_Y2Y_MODE_MASK (0x3U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_PARAM_Y2Y_MODE_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_PARAM_Y2Y_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_PARAM_Y2Y_MODE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_PARAM_Y2Y_MODE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_F - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_F_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_F_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_F_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_F_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_F_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_10 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_10_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_10_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_10_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_10_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_10_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_SFS_PARAM - CONTROL REGISTER OF SUB FRAME SYNC */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_ON_MASK (0x1U) #define VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_ON_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_ON(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_ON_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_ON_MASK) #define VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_TYPE_MASK (0x2U) #define VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_TYPE_SHIFT (1U) #define VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_TYPE_SHIFT)) & VPU_CMD_ENC_SET_PARAM_SFS_PARAM_SUB_FRAME_SYNC_TYPE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_11 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_11_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_11_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_11_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_11_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_11_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CROP_ENABLE - PRE PROCESSING CROP DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CROP_ENABLE_CROP_EN_MASK (0x1U) #define VPU_CMD_ENC_SET_PARAM_CROP_ENABLE_CROP_EN_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CROP_ENABLE_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CROP_ENABLE_CROP_EN_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CROP_ENABLE_CROP_EN_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_12 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_12_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_12_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_12_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_12_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_12_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CROP_POS - CONTROL REGISTER OF CROP START */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_Y_MASK (0xFFFFU) #define VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_Y_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_Y_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_Y_MASK) #define VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_X_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_X_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_X(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_X_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CROP_POS_CROP_START_X_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_13 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_13_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_13_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_13_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_13_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_13_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_CROP_SRC_SIZE - CROP_SRC SIZE */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_WIDTH_MASK (0xFFFFU) #define VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_WIDTH_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_WIDTH_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_WIDTH_MASK) #define VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_HEIGHT_MASK (0xFFFF0000U) #define VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_HEIGHT_SHIFT (16U) #define VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_HEIGHT_SHIFT)) & VPU_CMD_ENC_SET_PARAM_CROP_SRC_SIZE_PIC_HEIGHT_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_14 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_14_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_14_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_14_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_14_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_14_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_15 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_15_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_15_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_15_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_15_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_15_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_Y2Y_DATA_0 - Y2Y DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MIN_MASK (0x3FFU) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MIN_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MIN_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MIN_MASK) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MAX_MASK (0xFFC00U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MAX_SHIFT (10U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MAX_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_IN_MAX_MASK) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_OUT_MIN_MASK (0x3FF00000U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_OUT_MIN_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_OUT_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_OUT_MIN_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_0_LUMA_OUT_MIN_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_16 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_16_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_16_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_16_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_16_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_16_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_Y2Y_DATA_1 - Y2Y DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_LUMA_OUT_MAX_MASK (0x3FFU) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_LUMA_OUT_MAX_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_LUMA_OUT_MAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_LUMA_OUT_MAX_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_LUMA_OUT_MAX_MASK) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MIN_MASK (0xFFC00U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MIN_SHIFT (10U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MIN_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MIN_MASK) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MAX_MASK (0x3FF00000U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MAX_SHIFT (20U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MAX_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_1_CHR_IN_MAX_MASK) /*! @} */ /*! @name CMD_SET_FB_MV_COL_PRE_ENT - Dual col buffer address */ /*! @{ */ #define VPU_CMD_SET_FB_MV_COL_PRE_ENT_ADDR_DUAL_COL_MASK (0xFFFFFFFFU) #define VPU_CMD_SET_FB_MV_COL_PRE_ENT_ADDR_DUAL_COL_SHIFT (0U) #define VPU_CMD_SET_FB_MV_COL_PRE_ENT_ADDR_DUAL_COL(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_SET_FB_MV_COL_PRE_ENT_ADDR_DUAL_COL_SHIFT)) & VPU_CMD_SET_FB_MV_COL_PRE_ENT_ADDR_DUAL_COL_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_17 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_17_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_17_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_17_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_17_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_17_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name CMD_ENC_SET_PARAM_Y2Y_DATA_2 - Y2Y DATA */ /*! @{ */ #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MIN_MASK (0x3FFU) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MIN_SHIFT (0U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MIN_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MIN_MASK) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MAX_MASK (0xFFC00U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MAX_SHIFT (10U) #define VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MAX_SHIFT)) & VPU_CMD_ENC_SET_PARAM_Y2Y_DATA_2_CHR_OUT_MAX_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_18 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_18_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_18_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_18_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_18_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_18_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_19 - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_19_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_19_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_19_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_19_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_19_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1A - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1A_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1A_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1A_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1A_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1A_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1B - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1B_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1B_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1B_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1B_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1B_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1C - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1C_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1C_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1C_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1C_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1C_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1D - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1D_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1D_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1D_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1D_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1D_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1E - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1E_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1E_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1E_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1E_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1E_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1F - Address of prefix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1F_PREFIX_SEI_NAL_DATA_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1F_PREFIX_SEI_NAL_DATA_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1F_PREFIX_SEI_NAL_DATA_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1F_PREFIX_SEI_NAL_DATA_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_PREFIX_SEI_NAL_ADDR_1F_PREFIX_SEI_NAL_DATA_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_0 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_0_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_0_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_0_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_0_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_0_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_2 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_2_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_2_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_2_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_2_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_2_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_3 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_3_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_3_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_3_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_3_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_3_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_4 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_4_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_4_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_4_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_4_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_4_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_5 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_5_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_5_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_5_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_5_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_5_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_6 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_6_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_6_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_6_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_6_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_6_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_7 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_7_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_7_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_7_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_7_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_7_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_8 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_8_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_8_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_8_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_8_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_8_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_9 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_9_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_9_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_9_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_9_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_9_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_A - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_A_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_A_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_A_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_A_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_A_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_B - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_B_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_B_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_B_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_B_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_B_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_C - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_C_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_C_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_C_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_C_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_C_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_D - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_D_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_D_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_D_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_D_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_D_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_E - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_E_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_E_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_E_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_E_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_E_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_F - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_F_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_F_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_F_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_F_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_F_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_10 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_10_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_10_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_10_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_10_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_10_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_11 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_11_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_11_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_11_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_11_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_11_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_12 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_12_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_12_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_12_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_12_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_12_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_13 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_13_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_13_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_13_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_13_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_13_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_14 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_14_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_14_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_14_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_14_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_14_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_15 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_15_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_15_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_15_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_15_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_15_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_16 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_16_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_16_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_16_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_16_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_16_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_17 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_17_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_17_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_17_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_17_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_17_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_18 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_18_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_18_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_18_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_18_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_18_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_19 - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_19_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_19_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_19_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_19_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_19_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1A - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1A_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1A_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1A_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1A_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1A_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1B - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1B_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1B_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1B_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1B_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1B_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1C - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1C_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1C_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1C_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1C_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1C_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1D - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1D_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1D_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1D_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1D_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1D_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1E - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1E_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1E_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1E_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1E_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1E_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name RET_DEC_COLOR_CONFIG - Color config */ /*! @{ */ #define VPU_RET_DEC_COLOR_CONFIG_COLOR_DESCRIPTION_PRESENT_FLAG_MASK (0x1U) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_DESCRIPTION_PRESENT_FLAG_SHIFT (0U) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_DESCRIPTION_PRESENT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_DEC_COLOR_CONFIG_COLOR_DESCRIPTION_PRESENT_FLAG_SHIFT)) & VPU_RET_DEC_COLOR_CONFIG_COLOR_DESCRIPTION_PRESENT_FLAG_MASK) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_PRIMARIES_MASK (0x1FEU) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_PRIMARIES_SHIFT (1U) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_PRIMARIES(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_DEC_COLOR_CONFIG_COLOR_PRIMARIES_SHIFT)) & VPU_RET_DEC_COLOR_CONFIG_COLOR_PRIMARIES_MASK) #define VPU_RET_DEC_COLOR_CONFIG_TRANSFER_CHARACTERISTICS_MASK (0x1FE00U) #define VPU_RET_DEC_COLOR_CONFIG_TRANSFER_CHARACTERISTICS_SHIFT (9U) #define VPU_RET_DEC_COLOR_CONFIG_TRANSFER_CHARACTERISTICS(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_DEC_COLOR_CONFIG_TRANSFER_CHARACTERISTICS_SHIFT)) & VPU_RET_DEC_COLOR_CONFIG_TRANSFER_CHARACTERISTICS_MASK) #define VPU_RET_DEC_COLOR_CONFIG_MATRIX_COEFFICIENTS_MASK (0x1FE0000U) #define VPU_RET_DEC_COLOR_CONFIG_MATRIX_COEFFICIENTS_SHIFT (17U) #define VPU_RET_DEC_COLOR_CONFIG_MATRIX_COEFFICIENTS(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_DEC_COLOR_CONFIG_MATRIX_COEFFICIENTS_SHIFT)) & VPU_RET_DEC_COLOR_CONFIG_MATRIX_COEFFICIENTS_MASK) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_RANGE_MASK (0x2000000U) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_RANGE_SHIFT (25U) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_RANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_DEC_COLOR_CONFIG_COLOR_RANGE_SHIFT)) & VPU_RET_DEC_COLOR_CONFIG_COLOR_RANGE_MASK) #define VPU_RET_DEC_COLOR_CONFIG_CHROMA_SAMPLE_POSITION_MASK (0xC000000U) #define VPU_RET_DEC_COLOR_CONFIG_CHROMA_SAMPLE_POSITION_SHIFT (26U) #define VPU_RET_DEC_COLOR_CONFIG_CHROMA_SAMPLE_POSITION(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_DEC_COLOR_CONFIG_CHROMA_SAMPLE_POSITION_SHIFT)) & VPU_RET_DEC_COLOR_CONFIG_CHROMA_SAMPLE_POSITION_MASK) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_SPACE_MASK (0x70000000U) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_SPACE_SHIFT (28U) #define VPU_RET_DEC_COLOR_CONFIG_COLOR_SPACE(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_DEC_COLOR_CONFIG_COLOR_SPACE_SHIFT)) & VPU_RET_DEC_COLOR_CONFIG_COLOR_SPACE_MASK) /*! @} */ /*! @name RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1F - Address of suffix SEI nal data for current ENC_PIC */ /*! @{ */ #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1F_SUFFIX_SEI_NAL_ADDR_MASK (0xFFFFFFFFU) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1F_SUFFIX_SEI_NAL_ADDR_SHIFT (0U) #define VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1F_SUFFIX_SEI_NAL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1F_SUFFIX_SEI_NAL_ADDR_SHIFT)) & VPU_RET_ENC_FLUSH_CMD_SUFFIX_SEI_NAL_ADDR_1F_SUFFIX_SEI_NAL_ADDR_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_PDBG_CTRL - V-CPU Debugger Control */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STEP_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STEP_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STEP(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STEP_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STEP_MASK) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_RESUME_MASK (0x2U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_RESUME_SHIFT (1U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_RESUME(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_RESUME_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_RESUME_MASK) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STABLEBRK_MASK (0x4U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STABLEBRK_SHIFT (2U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STABLEBRK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STABLEBRK_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_STABLEBRK_MASK) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_IMMBRK_MASK (0x8U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_IMMBRK_SHIFT (3U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_IMMBRK(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_IMMBRK_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_CTRL_IMMBRK_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_PDBG_IDX_REG - V-CPU Debugger Index */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_DBGIDX_MASK (0xFFU) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_DBGIDX_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_DBGIDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_DBGIDX_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_DBGIDX_MASK) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_WRDBG_MASK (0x100U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_WRDBG_SHIFT (8U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_WRDBG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_WRDBG_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_WRDBG_MASK) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_RDDBG_MASK (0x200U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_RDDBG_SHIFT (9U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_RDDBG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_RDDBG_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_IDX_REG_RDDBG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_PDBG_WDATA_REG - V-CPU Debugger Write Data */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_PDBG_WDATA_REG_VPU_PDBG_WDATA_REG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_VPU_PDBG_WDATA_REG_VPU_PDBG_WDATA_REG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_WDATA_REG_VPU_PDBG_WDATA_REG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_WDATA_REG_VPU_PDBG_WDATA_REG_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_WDATA_REG_VPU_PDBG_WDATA_REG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_PDBG_RDATA_REG - V-CPU Debugger Read Data */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_PDBG_RDATA_REG_VPU_PDBG_RDATA_REG_MASK (0xFFFFFFFFU) #define VPU_CMD_CONTROL_REG_VPU_PDBG_RDATA_REG_VPU_PDBG_RDATA_REG_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_RDATA_REG_VPU_PDBG_RDATA_REG(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_RDATA_REG_VPU_PDBG_RDATA_REG_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_RDATA_REG_VPU_PDBG_RDATA_REG_MASK) /*! @} */ /*! @name CMD_CONTROL_REG_VPU_PDBG_STEP_MASK - V-CPU Debugger Step Mask */ /*! @{ */ #define VPU_CMD_CONTROL_REG_VPU_PDBG_STEP_MASK_STEP_MASK_ENABLE_MASK (0x1U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_STEP_MASK_STEP_MASK_ENABLE_SHIFT (0U) #define VPU_CMD_CONTROL_REG_VPU_PDBG_STEP_MASK_STEP_MASK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_CONTROL_REG_VPU_PDBG_STEP_MASK_STEP_MASK_ENABLE_SHIFT)) & VPU_CMD_CONTROL_REG_VPU_PDBG_STEP_MASK_STEP_MASK_ENABLE_MASK) /*! @} */ /*! @name CMD_GLOBAL_REG_VCPU_RESTART - V-CPU Restart Request */ /*! @{ */ #define VPU_CMD_GLOBAL_REG_VCPU_RESTART_VCPU_RESTART_MASK (0x1U) #define VPU_CMD_GLOBAL_REG_VCPU_RESTART_VCPU_RESTART_SHIFT (0U) #define VPU_CMD_GLOBAL_REG_VCPU_RESTART_VCPU_RESTART(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_VCPU_RESTART_VCPU_RESTART_SHIFT)) & VPU_CMD_GLOBAL_REG_VCPU_RESTART_VCPU_RESTART_MASK) /*! @} */ /*! @name CMD_GLOBAL_REG_OPTION - Remap Control */ /*! @{ */ #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_PSIZE_MASK (0x1FFU) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_PSIZE_SHIFT (0U) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_PSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_OPTION_REMAP_PSIZE_SHIFT)) & VPU_CMD_GLOBAL_REG_OPTION_REMAP_PSIZE_MASK) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_PAGE_SIZE_EN_MASK (0x800U) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_PAGE_SIZE_EN_SHIFT (11U) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_PAGE_SIZE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_OPTION_REMAP_PAGE_SIZE_EN_SHIFT)) & VPU_CMD_GLOBAL_REG_OPTION_REMAP_PAGE_SIZE_EN_MASK) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_IDX_MASK (0xF000U) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_IDX_SHIFT (12U) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_IDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_OPTION_REMAP_IDX_SHIFT)) & VPU_CMD_GLOBAL_REG_OPTION_REMAP_IDX_MASK) #define VPU_CMD_GLOBAL_REG_OPTION_ENDIAN_MASK (0xF0000U) #define VPU_CMD_GLOBAL_REG_OPTION_ENDIAN_SHIFT (16U) #define VPU_CMD_GLOBAL_REG_OPTION_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_OPTION_ENDIAN_SHIFT)) & VPU_CMD_GLOBAL_REG_OPTION_ENDIAN_MASK) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_GLOBEN_MASK (0x80000000U) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_GLOBEN_SHIFT (31U) #define VPU_CMD_GLOBAL_REG_OPTION_REMAP_GLOBEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_OPTION_REMAP_GLOBEN_SHIFT)) & VPU_CMD_GLOBAL_REG_OPTION_REMAP_GLOBEN_MASK) /*! @} */ /*! @name CMD_GLOBAL_REG_VPU_REMAP_VADDR - Remap Virutal Address */ /*! @{ */ #define VPU_CMD_GLOBAL_REG_VPU_REMAP_VADDR_VPU_REMAP_VADDR_MASK (0xFFFFF000U) #define VPU_CMD_GLOBAL_REG_VPU_REMAP_VADDR_VPU_REMAP_VADDR_SHIFT (12U) #define VPU_CMD_GLOBAL_REG_VPU_REMAP_VADDR_VPU_REMAP_VADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_VPU_REMAP_VADDR_VPU_REMAP_VADDR_SHIFT)) & VPU_CMD_GLOBAL_REG_VPU_REMAP_VADDR_VPU_REMAP_VADDR_MASK) /*! @} */ /*! @name CMD_GLOBAL_REG_VPU_REMAP_PADDR - Remap Physical Address */ /*! @{ */ #define VPU_CMD_GLOBAL_REG_VPU_REMAP_PADDR_VPU_REMAP_PADDR_MASK (0xFFFFF000U) #define VPU_CMD_GLOBAL_REG_VPU_REMAP_PADDR_VPU_REMAP_PADDR_SHIFT (12U) #define VPU_CMD_GLOBAL_REG_VPU_REMAP_PADDR_VPU_REMAP_PADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_VPU_REMAP_PADDR_VPU_REMAP_PADDR_SHIFT)) & VPU_CMD_GLOBAL_REG_VPU_REMAP_PADDR_VPU_REMAP_PADDR_MASK) /*! @} */ /*! @name CMD_GLOBAL_REG_VPU_REMAP_CORE_START_GLOBAL - VPU Start Request */ /*! @{ */ #define VPU_CMD_GLOBAL_REG_VPU_REMAP_CORE_START_GLOBAL_VPU_REMAP_CORE_START_GLOBAL_MASK (0x1U) #define VPU_CMD_GLOBAL_REG_VPU_REMAP_CORE_START_GLOBAL_VPU_REMAP_CORE_START_GLOBAL_SHIFT (0U) #define VPU_CMD_GLOBAL_REG_VPU_REMAP_CORE_START_GLOBAL_VPU_REMAP_CORE_START_GLOBAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_VPU_REMAP_CORE_START_GLOBAL_VPU_REMAP_CORE_START_GLOBAL_SHIFT)) & VPU_CMD_GLOBAL_REG_VPU_REMAP_CORE_START_GLOBAL_VPU_REMAP_CORE_START_GLOBAL_MASK) /*! @} */ /*! @name CMD_GLOBAL_REG_COMMAND_GLOBAL - Command */ /*! @{ */ #define VPU_CMD_GLOBAL_REG_COMMAND_GLOBAL_COMMAND_MASK (0xFFFFFFFFU) #define VPU_CMD_GLOBAL_REG_COMMAND_GLOBAL_COMMAND_SHIFT (0U) #define VPU_CMD_GLOBAL_REG_COMMAND_GLOBAL_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << VPU_CMD_GLOBAL_REG_COMMAND_GLOBAL_COMMAND_SHIFT)) & VPU_CMD_GLOBAL_REG_COMMAND_GLOBAL_COMMAND_MASK) /*! @} */ /*! * @} */ /* end of group VPU_Register_Masks */ /* VPU - Peripheral instance base addresses */ /** Peripheral VPU__VPU__VPU_CODEC base address */ #define VPU__VPU__VPU_CODEC_BASE (0x4C480000u) /** Peripheral VPU__VPU__VPU_CODEC base pointer */ #define VPU__VPU__VPU_CODEC ((VPU_Type *)VPU__VPU__VPU_CODEC_BASE) /** Array initializer of VPU peripheral base addresses */ #define VPU_BASE_ADDRS { VPU__VPU__VPU_CODEC_BASE } /** Array initializer of VPU peripheral base pointers */ #define VPU_BASE_PTRS { VPU__VPU__VPU_CODEC } /*! * @} */ /* end of group VPU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VPU_BLK_CTRL_VPUMIX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_BLK_CTRL_VPUMIX_Peripheral_Access_Layer VPU_BLK_CTRL_VPUMIX Peripheral Access Layer * @{ */ /** VPU_BLK_CTRL_VPUMIX - Register Layout Typedef */ typedef struct { __I uint32_t VPU_STATUS; /**< VPU Status Register, offset: 0x0 */ __I uint32_t INIT_PENDING_TX; /**< Initiator Pending Transaction Register, offset: 0x4 */ __IO uint32_t CLOCK_GATING_CONTROL; /**< Clock Gating Control Register, offset: 0x8 */ } VPU_BLK_CTRL_VPUMIX_Type; /* ---------------------------------------------------------------------------- -- VPU_BLK_CTRL_VPUMIX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_BLK_CTRL_VPUMIX_Register_Masks VPU_BLK_CTRL_VPUMIX Register Masks * @{ */ /*! @name VPU_STATUS - VPU Status Register */ /*! @{ */ #define VPU_BLK_CTRL_VPUMIX_VPU_STATUS_VPU_IDLE_MASK (0x1U) #define VPU_BLK_CTRL_VPUMIX_VPU_STATUS_VPU_IDLE_SHIFT (0U) /*! VPU_IDLE - VPU idle status * 0b1..VPU is idle * 0b0..VPU is not idle */ #define VPU_BLK_CTRL_VPUMIX_VPU_STATUS_VPU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_VPU_STATUS_VPU_IDLE_SHIFT)) & VPU_BLK_CTRL_VPUMIX_VPU_STATUS_VPU_IDLE_MASK) /*! @} */ /*! @name INIT_PENDING_TX - Initiator Pending Transaction Register */ /*! @{ */ #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Primary_MASK (0x1U) #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Primary_SHIFT (0U) /*! VPU_Primary - Status information from initiator NIU NoC that indicates if there are pending * transaction in the NoC for VPU Primary NIUs * 0b0..No pending transaction * 0b1..Pending transaction */ #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Primary(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Primary_SHIFT)) & VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Primary_MASK) #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Secondary_MASK (0x2U) #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Secondary_SHIFT (1U) /*! VPU_Secondary - Status information from initiator NIU NoC that indicates if there are pending * transaction in the NoC for VPU Secondary NIUs * 0b1..Pending transaction * 0b0..No pending transaction */ #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Secondary(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Secondary_SHIFT)) & VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_VPU_Secondary_MASK) #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Encode_MASK (0x4U) #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Encode_SHIFT (2U) /*! JPEG_Encode - Status information from initiator NIU NoC that indicates if there are pending * transaction in the NoC for JPEG Encode NIUs * 0b1..Pending transaction * 0b0..No pending transaction */ #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Encode(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Encode_SHIFT)) & VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Encode_MASK) #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Decode_MASK (0x8U) #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Decode_SHIFT (3U) /*! JPEG_Decode - Status information from initiator NIU NoC that indicates if there are pending * transaction in the NoC for JPEG Decode NIUs * 0b1..Pending transaction * 0b0..No pending transaction */ #define VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Decode(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Decode_SHIFT)) & VPU_BLK_CTRL_VPUMIX_INIT_PENDING_TX_JPEG_Decode_MASK) /*! @} */ /*! @name CLOCK_GATING_CONTROL - Clock Gating Control Register */ /*! @{ */ #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_Wave_VPU_MASK (0x1U) #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_Wave_VPU_SHIFT (0U) /*! Wave_VPU - Gate the VPU clock (VPU_CLK_ROOT) and its associated network interface units * 0b1..Clock is disabled (gated) * 0b0..Clock is enabled */ #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_Wave_VPU(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_Wave_VPU_SHIFT)) & VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_Wave_VPU_MASK) #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_ENC_MASK (0x2U) #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_ENC_SHIFT (1U) /*! JPEG_ENC - Gate the JPEG ENC clock (VPU_JPEG_CLK_ROOT) and its associated network interface unit * 0b1..Clock is disabled (gated) * 0b0..Clock is enabled */ #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_ENC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_ENC_SHIFT)) & VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_ENC_MASK) #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_DEC_MASK (0x4U) #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_DEC_SHIFT (2U) /*! JPEG_DEC - Gate the JPEG DEC clock (VPU_JPEG_CLK_ROOT) and its associated network interface unit * 0b0..Clock is enabled * 0b1..Clock is disabled (gated) */ #define VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_DEC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_DEC_SHIFT)) & VPU_BLK_CTRL_VPUMIX_CLOCK_GATING_CONTROL_JPEG_DEC_MASK) /*! @} */ /*! * @} */ /* end of group VPU_BLK_CTRL_VPUMIX_Register_Masks */ /* VPU_BLK_CTRL_VPUMIX - Peripheral instance base addresses */ /** Peripheral VPU__BLK_CTRL_VPUMIX base address */ #define VPU__BLK_CTRL_VPUMIX_BASE (0x4C410000u) /** Peripheral VPU__BLK_CTRL_VPUMIX base pointer */ #define VPU__BLK_CTRL_VPUMIX ((VPU_BLK_CTRL_VPUMIX_Type *)VPU__BLK_CTRL_VPUMIX_BASE) /** Array initializer of VPU_BLK_CTRL_VPUMIX peripheral base addresses */ #define VPU_BLK_CTRL_VPUMIX_BASE_ADDRS { VPU__BLK_CTRL_VPUMIX_BASE } /** Array initializer of VPU_BLK_CTRL_VPUMIX peripheral base pointers */ #define VPU_BLK_CTRL_VPUMIX_BASE_PTRS { VPU__BLK_CTRL_VPUMIX } /*! * @} */ /* end of group VPU_BLK_CTRL_VPUMIX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VPU_JPEG_ENC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_JPEG_ENC_Peripheral_Access_Layer VPU_JPEG_ENC Peripheral Access Layer * @{ */ /** VPU_JPEG_ENC - Register Layout Typedef */ typedef struct { union { /* offset: 0x0 */ struct { /* offset: 0x0 */ __O uint32_t MODE; /**< Mode Control, offset: 0x0 */ __O uint32_t CFG_MODE; /**< Configuration Mode, offset: 0x4 */ __O uint32_t QUALITY; /**< Quality Factor, offset: 0x8 */ uint8_t RESERVED_0[4]; __O uint32_t RC_REGS_SEL; /**< Indirect Status Register Select, offset: 0x10 */ __O uint32_t LUMTH; /**< Luminance Threshold, offset: 0x14 */ __O uint32_t CHRTH; /**< Chrominance Threshold, offset: 0x18 */ uint8_t RESERVED_1[36]; __O uint32_t NOMFRSIZE_LO; /**< Nominal Frame Size Low, offset: 0x40 */ __O uint32_t NOMFRSIZE_HI; /**< Nominal Frame Size High, offset: 0x44 */ __O uint32_t OFBSIZE_LO; /**< FIFO Buffer Size Low, offset: 0x48 */ __O uint32_t OFBSIZE_HI; /**< FIFO Buffer Size High, offset: 0x4C */ } CONTROL; struct { /* offset: 0x0 */ __I uint32_t STATUS_0; /**< Status 0, offset: 0x0 */ __I uint32_t STATUS_1; /**< Status 1, offset: 0x4 */ __I uint32_t STATUS_2; /**< Status 2, offset: 0x8 */ __I uint32_t STATUS_3; /**< Status 3, offset: 0xC */ __I uint32_t STATUS_4; /**< Status 4, offset: 0x10 */ __I uint32_t STATUS_5; /**< Status 5, offset: 0x14 */ __I uint32_t STATUS_6; /**< Status 6, offset: 0x18 */ __I uint32_t STATUS_7; /**< Status 7, offset: 0x1C */ __I uint32_t STATUS_8; /**< Status 8, offset: 0x20 */ __I uint32_t STATUS_9; /**< Status 9, offset: 0x24 */ __I uint32_t STATUS_10; /**< Status 10, offset: 0x28 */ __I uint32_t STATUS_11; /**< Status 11, offset: 0x2C */ __I uint32_t STATUS_12; /**< Status 12, offset: 0x30 */ __I uint32_t STATUS_13; /**< Status 13, offset: 0x34 */ __I uint32_t STATUS_14; /**< Status 14, offset: 0x38 */ __I uint32_t STATUS_15; /**< Status 15, offset: 0x3C */ __I uint32_t STATUS_16; /**< Status 16, offset: 0x40 */ __I uint32_t STATUS_17; /**< Status 17, offset: 0x44 */ __I uint32_t STATUS_18; /**< Status 18, offset: 0x48 */ __I uint32_t STATUS_19; /**< Status 19, offset: 0x4C */ } STATUS; }; } VPU_JPEG_ENC_Type; /* ---------------------------------------------------------------------------- -- VPU_JPEG_ENC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_JPEG_ENC_Register_Masks VPU_JPEG_ENC Register Masks * @{ */ /*! @name MODE - Mode Control */ /*! @{ */ #define VPU_JPEG_ENC_MODE_LP_MASK (0x1U) #define VPU_JPEG_ENC_MODE_LP_SHIFT (0U) /*! LP - Low Power * 0b0..No effect * 0b1..Enable */ #define VPU_JPEG_ENC_MODE_LP(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_LP_SHIFT)) & VPU_JPEG_ENC_MODE_LP_MASK) #define VPU_JPEG_ENC_MODE_SWR_MASK (0x2U) #define VPU_JPEG_ENC_MODE_SWR_SHIFT (1U) /*! SWR - Software Reset * 0b0..No effect * 0b1..Enable */ #define VPU_JPEG_ENC_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_SWR_SHIFT)) & VPU_JPEG_ENC_MODE_SWR_MASK) #define VPU_JPEG_ENC_MODE_MS_MASK (0x8U) #define VPU_JPEG_ENC_MODE_MS_SHIFT (3U) /*! MS - Multi-Scan JPEG Encoding * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_MS_SHIFT)) & VPU_JPEG_ENC_MODE_MS_MASK) #define VPU_JPEG_ENC_MODE_EXTSEQ_MASK (0x10U) #define VPU_JPEG_ENC_MODE_EXTSEQ_SHIFT (4U) /*! EXTSEQ - Extended Sequential Operation Mode * 0b0..Baseline operation mode * 0b1..Extended sequential operation mode */ #define VPU_JPEG_ENC_MODE_EXTSEQ(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_EXTSEQ_SHIFT)) & VPU_JPEG_ENC_MODE_EXTSEQ_MASK) #define VPU_JPEG_ENC_MODE_CONF_MASK (0x20U) #define VPU_JPEG_ENC_MODE_CONF_SHIFT (5U) /*! CONF - Configuration Mode * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_MODE_CONF(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_CONF_SHIFT)) & VPU_JPEG_ENC_MODE_CONF_MASK) #define VPU_JPEG_ENC_MODE_GO_MASK (0x40U) #define VPU_JPEG_ENC_MODE_GO_SHIFT (6U) /*! GO - Start Encoding * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_MODE_GO(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_GO_SHIFT)) & VPU_JPEG_ENC_MODE_GO_MASK) #define VPU_JPEG_ENC_MODE_AUTOCLR_CONF_MASK (0x80U) #define VPU_JPEG_ENC_MODE_AUTOCLR_CONF_SHIFT (7U) /*! AUTOCLR_CONF - Auto Clear Configuration * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_MODE_AUTOCLR_CONF(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_AUTOCLR_CONF_SHIFT)) & VPU_JPEG_ENC_MODE_AUTOCLR_CONF_MASK) #define VPU_JPEG_ENC_MODE_AUTOCLR_GO_MASK (0x100U) #define VPU_JPEG_ENC_MODE_AUTOCLR_GO_SHIFT (8U) /*! AUTOCLR_GO - Auto Clear GO * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_MODE_AUTOCLR_GO(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_MODE_AUTOCLR_GO_SHIFT)) & VPU_JPEG_ENC_MODE_AUTOCLR_GO_MASK) /*! @} */ /*! @name CFG_MODE - Configuration Mode */ /*! @{ */ #define VPU_JPEG_ENC_CFG_MODE_MSOF0_MASK (0x1U) #define VPU_JPEG_ENC_CFG_MODE_MSOF0_SHIFT (0U) /*! MSOF0 - Mask Sequence Of Frame 0 * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MSOF0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MSOF0_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MSOF0_MASK) #define VPU_JPEG_ENC_CFG_MODE_MDRI_MASK (0x2U) #define VPU_JPEG_ENC_CFG_MODE_MDRI_SHIFT (1U) /*! MDRI - Mask Define Restart Interval * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MDRI(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MDRI_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MDRI_MASK) #define VPU_JPEG_ENC_CFG_MODE_MDQT_MASK (0x4U) #define VPU_JPEG_ENC_CFG_MODE_MDQT_SHIFT (2U) /*! MDQT - Mask Define Quantization Table * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MDQT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MDQT_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MDQT_MASK) #define VPU_JPEG_ENC_CFG_MODE_MDHT_MASK (0x8U) #define VPU_JPEG_ENC_CFG_MODE_MDHT_SHIFT (3U) /*! MDHT - Mask Define Huffman Table * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MDHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MDHT_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MDHT_MASK) #define VPU_JPEG_ENC_CFG_MODE_MSOS_MASK (0x10U) #define VPU_JPEG_ENC_CFG_MODE_MSOS_SHIFT (4U) /*! MSOS - Mask Start Of Scan * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MSOS(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MSOS_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MSOS_MASK) #define VPU_JPEG_ENC_CFG_MODE_MDNL_MASK (0x20U) #define VPU_JPEG_ENC_CFG_MODE_MDNL_SHIFT (5U) /*! MDNL - Mask Define Number of Lines * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MDNL(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MDNL_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MDNL_MASK) #define VPU_JPEG_ENC_CFG_MODE_MAPP_MASK (0x40U) #define VPU_JPEG_ENC_CFG_MODE_MAPP_SHIFT (6U) /*! MAPP - Mask Application * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MAPP(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MAPP_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MAPP_MASK) #define VPU_JPEG_ENC_CFG_MODE_MCOM_MASK (0x80U) #define VPU_JPEG_ENC_CFG_MODE_MCOM_SHIFT (7U) /*! MCOM - Mask Comment * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_MCOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_MCOM_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_MCOM_MASK) #define VPU_JPEG_ENC_CFG_MODE_COMB_DQT_MASK (0x100U) #define VPU_JPEG_ENC_CFG_MODE_COMB_DQT_SHIFT (8U) /*! COMB_DQT - Combined Define Quantization Table * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_COMB_DQT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_COMB_DQT_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_COMB_DQT_MASK) #define VPU_JPEG_ENC_CFG_MODE_COMB_DHT_MASK (0x200U) #define VPU_JPEG_ENC_CFG_MODE_COMB_DHT_SHIFT (9U) /*! COMB_DHT - Combined Define Huffman Table * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_COMB_DHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_COMB_DHT_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_COMB_DHT_MASK) #define VPU_JPEG_ENC_CFG_MODE_DICOM_MASK (0x400U) #define VPU_JPEG_ENC_CFG_MODE_DICOM_SHIFT (10U) /*! DICOM - DICOM * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_CFG_MODE_DICOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CFG_MODE_DICOM_SHIFT)) & VPU_JPEG_ENC_CFG_MODE_DICOM_MASK) /*! @} */ /*! @name QUALITY - Quality Factor */ /*! @{ */ #define VPU_JPEG_ENC_QUALITY_QUALITY_MASK (0x7FU) #define VPU_JPEG_ENC_QUALITY_QUALITY_SHIFT (0U) /*! QUALITY - Quality Factor */ #define VPU_JPEG_ENC_QUALITY_QUALITY(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_QUALITY_QUALITY_SHIFT)) & VPU_JPEG_ENC_QUALITY_QUALITY_MASK) /*! @} */ /*! @name RC_REGS_SEL - Indirect Status Register Select */ /*! @{ */ #define VPU_JPEG_ENC_RC_REGS_SEL_RC_REGS_SEL_MASK (0x3U) #define VPU_JPEG_ENC_RC_REGS_SEL_RC_REGS_SEL_SHIFT (0U) /*! RC_REGS_SEL - Rate-Control Register Set Select * 0b00..RC_REGS0: LUMTH; RC_REGS1: CHRTH. * 0b01..RC_REGS0: Bits [31:16] of register with total truncated bits of luminance blocks; RC_REGS1: Bits [15:0] * of register with total truncated bits of luminance blocks. * 0b10..RC_REGS0: Bits [31:16] of register with total truncated bits of chrominance blocks; RC_REGS1: Bits * [15:0] of register with total truncated bits of chrominance blocks. * 0b11.. */ #define VPU_JPEG_ENC_RC_REGS_SEL_RC_REGS_SEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_RC_REGS_SEL_RC_REGS_SEL_SHIFT)) & VPU_JPEG_ENC_RC_REGS_SEL_RC_REGS_SEL_MASK) /*! @} */ /*! @name LUMTH - Luminance Threshold */ /*! @{ */ #define VPU_JPEG_ENC_LUMTH_LUMTH_MASK (0xFFFFU) #define VPU_JPEG_ENC_LUMTH_LUMTH_SHIFT (0U) /*! LUMTH - Luminance Threshold */ #define VPU_JPEG_ENC_LUMTH_LUMTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_LUMTH_LUMTH_SHIFT)) & VPU_JPEG_ENC_LUMTH_LUMTH_MASK) /*! @} */ /*! @name CHRTH - Chrominance Threshold */ /*! @{ */ #define VPU_JPEG_ENC_CHRTH_CHRTH_MASK (0xFFFFU) #define VPU_JPEG_ENC_CHRTH_CHRTH_SHIFT (0U) /*! CHRTH - Chrominance Threshold */ #define VPU_JPEG_ENC_CHRTH_CHRTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_CHRTH_CHRTH_SHIFT)) & VPU_JPEG_ENC_CHRTH_CHRTH_MASK) /*! @} */ /*! @name NOMFRSIZE_LO - Nominal Frame Size Low */ /*! @{ */ #define VPU_JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_MASK (0xFFFFU) #define VPU_JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_SHIFT (0U) /*! NOMFRSIZE_LO - Nominal Frame Size Low */ #define VPU_JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_SHIFT)) & VPU_JPEG_ENC_NOMFRSIZE_LO_NOMFRSIZE_LO_MASK) /*! @} */ /*! @name NOMFRSIZE_HI - Nominal Frame Size High */ /*! @{ */ #define VPU_JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_MASK (0xFFFFU) #define VPU_JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_SHIFT (0U) /*! NOMFRSIZE_HI - Nominal Frame Size High */ #define VPU_JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_SHIFT)) & VPU_JPEG_ENC_NOMFRSIZE_HI_NOMFRSIZE_HI_MASK) /*! @} */ /*! @name OFBSIZE_LO - FIFO Buffer Size Low */ /*! @{ */ #define VPU_JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_MASK (0xFFFFU) #define VPU_JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_SHIFT (0U) /*! OFBSIZE_LO - FIFO Buffer Size Low */ #define VPU_JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_SHIFT)) & VPU_JPEG_ENC_OFBSIZE_LO_OFBSIZE_LO_MASK) /*! @} */ /*! @name OFBSIZE_HI - FIFO Buffer Size High */ /*! @{ */ #define VPU_JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_MASK (0xFFFFU) #define VPU_JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_SHIFT (0U) /*! OFBSIZE_HI - FIFO Buffer Size High */ #define VPU_JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_SHIFT)) & VPU_JPEG_ENC_OFBSIZE_HI_OFBSIZE_HI_MASK) /*! @} */ /*! @name STATUS_0 - Status 0 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_0_X_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_0_X_SHIFT (0U) /*! X - Image width */ #define VPU_JPEG_ENC_STATUS_0_X(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_0_X_SHIFT)) & VPU_JPEG_ENC_STATUS_0_X_MASK) /*! @} */ /*! @name STATUS_1 - Status 1 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_1_Y_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_1_Y_SHIFT (0U) /*! Y - Image Height */ #define VPU_JPEG_ENC_STATUS_1_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_1_Y_SHIFT)) & VPU_JPEG_ENC_STATUS_1_Y_MASK) /*! @} */ /*! @name STATUS_2 - Status 2 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_2_HMCU_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_2_HMCU_SHIFT (0U) /*! HMCU - Horizontal MCU */ #define VPU_JPEG_ENC_STATUS_2_HMCU(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_2_HMCU_SHIFT)) & VPU_JPEG_ENC_STATUS_2_HMCU_MASK) /*! @} */ /*! @name STATUS_3 - Status 3 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_3_VMCU_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_3_VMCU_SHIFT (0U) /*! VMCU - Vertical MCU */ #define VPU_JPEG_ENC_STATUS_3_VMCU(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_3_VMCU_SHIFT)) & VPU_JPEG_ENC_STATUS_3_VMCU_MASK) /*! @} */ /*! @name STATUS_4 - Status 4 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_4_Tq0_MASK (0x3U) #define VPU_JPEG_ENC_STATUS_4_Tq0_SHIFT (0U) /*! Tq0 - Table Quantization 0 ID */ #define VPU_JPEG_ENC_STATUS_4_Tq0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_4_Tq0_SHIFT)) & VPU_JPEG_ENC_STATUS_4_Tq0_MASK) #define VPU_JPEG_ENC_STATUS_4_V0_MASK (0x1CU) #define VPU_JPEG_ENC_STATUS_4_V0_SHIFT (2U) /*! V0 - Vertical Sampling 0 */ #define VPU_JPEG_ENC_STATUS_4_V0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_4_V0_SHIFT)) & VPU_JPEG_ENC_STATUS_4_V0_MASK) #define VPU_JPEG_ENC_STATUS_4_H0_MASK (0xE0U) #define VPU_JPEG_ENC_STATUS_4_H0_SHIFT (5U) /*! H0 - Horizontal Sampling 0 */ #define VPU_JPEG_ENC_STATUS_4_H0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_4_H0_SHIFT)) & VPU_JPEG_ENC_STATUS_4_H0_MASK) #define VPU_JPEG_ENC_STATUS_4_C0_MASK (0xFF00U) #define VPU_JPEG_ENC_STATUS_4_C0_SHIFT (8U) /*! C0 - Component 0 ID */ #define VPU_JPEG_ENC_STATUS_4_C0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_4_C0_SHIFT)) & VPU_JPEG_ENC_STATUS_4_C0_MASK) /*! @} */ /*! @name STATUS_5 - Status 5 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_5_Tq1_MASK (0x3U) #define VPU_JPEG_ENC_STATUS_5_Tq1_SHIFT (0U) /*! Tq1 - Table Quantization 1 ID */ #define VPU_JPEG_ENC_STATUS_5_Tq1(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_5_Tq1_SHIFT)) & VPU_JPEG_ENC_STATUS_5_Tq1_MASK) #define VPU_JPEG_ENC_STATUS_5_V1_MASK (0x1CU) #define VPU_JPEG_ENC_STATUS_5_V1_SHIFT (2U) /*! V1 - Vertical Sampling 1 */ #define VPU_JPEG_ENC_STATUS_5_V1(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_5_V1_SHIFT)) & VPU_JPEG_ENC_STATUS_5_V1_MASK) #define VPU_JPEG_ENC_STATUS_5_H1_MASK (0xE0U) #define VPU_JPEG_ENC_STATUS_5_H1_SHIFT (5U) /*! H1 - Horizontal Sampling 1 */ #define VPU_JPEG_ENC_STATUS_5_H1(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_5_H1_SHIFT)) & VPU_JPEG_ENC_STATUS_5_H1_MASK) #define VPU_JPEG_ENC_STATUS_5_C1_MASK (0xFF00U) #define VPU_JPEG_ENC_STATUS_5_C1_SHIFT (8U) /*! C1 - Component 1 ID */ #define VPU_JPEG_ENC_STATUS_5_C1(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_5_C1_SHIFT)) & VPU_JPEG_ENC_STATUS_5_C1_MASK) /*! @} */ /*! @name STATUS_6 - Status 6 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_6_Tq2_MASK (0x3U) #define VPU_JPEG_ENC_STATUS_6_Tq2_SHIFT (0U) /*! Tq2 - Table Quantization 2 ID */ #define VPU_JPEG_ENC_STATUS_6_Tq2(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_6_Tq2_SHIFT)) & VPU_JPEG_ENC_STATUS_6_Tq2_MASK) #define VPU_JPEG_ENC_STATUS_6_V2_MASK (0x1CU) #define VPU_JPEG_ENC_STATUS_6_V2_SHIFT (2U) /*! V2 - Vertical Sampling 2 */ #define VPU_JPEG_ENC_STATUS_6_V2(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_6_V2_SHIFT)) & VPU_JPEG_ENC_STATUS_6_V2_MASK) #define VPU_JPEG_ENC_STATUS_6_H2_MASK (0xE0U) #define VPU_JPEG_ENC_STATUS_6_H2_SHIFT (5U) /*! H2 - Horizontal Sampling 2 ID */ #define VPU_JPEG_ENC_STATUS_6_H2(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_6_H2_SHIFT)) & VPU_JPEG_ENC_STATUS_6_H2_MASK) #define VPU_JPEG_ENC_STATUS_6_C2_MASK (0xFF00U) #define VPU_JPEG_ENC_STATUS_6_C2_SHIFT (8U) /*! C2 - Component 2 */ #define VPU_JPEG_ENC_STATUS_6_C2(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_6_C2_SHIFT)) & VPU_JPEG_ENC_STATUS_6_C2_MASK) /*! @} */ /*! @name STATUS_7 - Status 7 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_7_Tq3_MASK (0x3U) #define VPU_JPEG_ENC_STATUS_7_Tq3_SHIFT (0U) /*! Tq3 - Table Quantization 3 ID */ #define VPU_JPEG_ENC_STATUS_7_Tq3(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_7_Tq3_SHIFT)) & VPU_JPEG_ENC_STATUS_7_Tq3_MASK) #define VPU_JPEG_ENC_STATUS_7_V3_MASK (0x1CU) #define VPU_JPEG_ENC_STATUS_7_V3_SHIFT (2U) /*! V3 - Vertical Sampling 3 */ #define VPU_JPEG_ENC_STATUS_7_V3(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_7_V3_SHIFT)) & VPU_JPEG_ENC_STATUS_7_V3_MASK) #define VPU_JPEG_ENC_STATUS_7_H3_MASK (0xE0U) #define VPU_JPEG_ENC_STATUS_7_H3_SHIFT (5U) /*! H3 - Horizontal Sampling 3 */ #define VPU_JPEG_ENC_STATUS_7_H3(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_7_H3_SHIFT)) & VPU_JPEG_ENC_STATUS_7_H3_MASK) #define VPU_JPEG_ENC_STATUS_7_C3_MASK (0xFF00U) #define VPU_JPEG_ENC_STATUS_7_C3_SHIFT (8U) /*! C3 - Component 3 ID */ #define VPU_JPEG_ENC_STATUS_7_C3(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_7_C3_SHIFT)) & VPU_JPEG_ENC_STATUS_7_C3_MASK) /*! @} */ /*! @name STATUS_8 - Status 8 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_8_Nf_MASK (0xFFU) #define VPU_JPEG_ENC_STATUS_8_Nf_SHIFT (0U) /*! Nf - Number of Components in Frame */ #define VPU_JPEG_ENC_STATUS_8_Nf(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_8_Nf_SHIFT)) & VPU_JPEG_ENC_STATUS_8_Nf_MASK) #define VPU_JPEG_ENC_STATUS_8_QUALITY_MASK (0xFF00U) #define VPU_JPEG_ENC_STATUS_8_QUALITY_SHIFT (8U) /*! QUALITY - Quality Factor */ #define VPU_JPEG_ENC_STATUS_8_QUALITY(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_8_QUALITY_SHIFT)) & VPU_JPEG_ENC_STATUS_8_QUALITY_MASK) /*! @} */ /*! @name STATUS_9 - Status 9 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_9_DRI_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_9_DRI_SHIFT (0U) /*! DRI - Define Restart Interval */ #define VPU_JPEG_ENC_STATUS_9_DRI(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_9_DRI_SHIFT)) & VPU_JPEG_ENC_STATUS_9_DRI_MASK) /*! @} */ /*! @name STATUS_10 - Status 10 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_10_Ns_MASK (0xFU) #define VPU_JPEG_ENC_STATUS_10_Ns_SHIFT (0U) /*! Ns - Number of Components in Scan */ #define VPU_JPEG_ENC_STATUS_10_Ns(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_10_Ns_SHIFT)) & VPU_JPEG_ENC_STATUS_10_Ns_MASK) #define VPU_JPEG_ENC_STATUS_10_NBMCU_MASK (0xF0U) #define VPU_JPEG_ENC_STATUS_10_NBMCU_SHIFT (4U) /*! NBMCU - Number of Data Unit per MCU */ #define VPU_JPEG_ENC_STATUS_10_NBMCU(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_10_NBMCU_SHIFT)) & VPU_JPEG_ENC_STATUS_10_NBMCU_MASK) #define VPU_JPEG_ENC_STATUS_10_Vmax_MASK (0xF00U) #define VPU_JPEG_ENC_STATUS_10_Vmax_SHIFT (8U) /*! Vmax - Maximum Vertical Sampling */ #define VPU_JPEG_ENC_STATUS_10_Vmax(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_10_Vmax_SHIFT)) & VPU_JPEG_ENC_STATUS_10_Vmax_MASK) #define VPU_JPEG_ENC_STATUS_10_Hmax_MASK (0xF000U) #define VPU_JPEG_ENC_STATUS_10_Hmax_SHIFT (12U) /*! Hmax - Maximum Horizontal Sampling */ #define VPU_JPEG_ENC_STATUS_10_Hmax(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_10_Hmax_SHIFT)) & VPU_JPEG_ENC_STATUS_10_Hmax_MASK) /*! @} */ /*! @name STATUS_11 - Status 11 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_11_VHS0_MASK (0xFU) #define VPU_JPEG_ENC_STATUS_11_VHS0_SHIFT (0U) /*! VHS0 - VHS0 */ #define VPU_JPEG_ENC_STATUS_11_VHS0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_11_VHS0_SHIFT)) & VPU_JPEG_ENC_STATUS_11_VHS0_MASK) #define VPU_JPEG_ENC_STATUS_11_VHS1_MASK (0xF0U) #define VPU_JPEG_ENC_STATUS_11_VHS1_SHIFT (4U) /*! VHS1 - VHS1 */ #define VPU_JPEG_ENC_STATUS_11_VHS1(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_11_VHS1_SHIFT)) & VPU_JPEG_ENC_STATUS_11_VHS1_MASK) #define VPU_JPEG_ENC_STATUS_11_VHS2_MASK (0xF00U) #define VPU_JPEG_ENC_STATUS_11_VHS2_SHIFT (8U) /*! VHS2 - VHS2 */ #define VPU_JPEG_ENC_STATUS_11_VHS2(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_11_VHS2_SHIFT)) & VPU_JPEG_ENC_STATUS_11_VHS2_MASK) #define VPU_JPEG_ENC_STATUS_11_VHS3_MASK (0xF000U) #define VPU_JPEG_ENC_STATUS_11_VHS3_SHIFT (12U) /*! VHS3 - VHS3 */ #define VPU_JPEG_ENC_STATUS_11_VHS3(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_11_VHS3_SHIFT)) & VPU_JPEG_ENC_STATUS_11_VHS3_MASK) /*! @} */ /*! @name STATUS_12 - Status 12 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_12_COM_E_MASK (0x1U) #define VPU_JPEG_ENC_STATUS_12_COM_E_SHIFT (0U) /*! COM_E - Comment Error * 0b0..No error is detected in COM segment. * 0b1..An error is detected in COM segment. */ #define VPU_JPEG_ENC_STATUS_12_COM_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_COM_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_COM_E_MASK) #define VPU_JPEG_ENC_STATUS_12_APPn_E_MASK (0x2U) #define VPU_JPEG_ENC_STATUS_12_APPn_E_SHIFT (1U) /*! APPn_E - Application n Error * 0b0..No error is detected in APPn segment. * 0b1..An error is detected in APPn segment. */ #define VPU_JPEG_ENC_STATUS_12_APPn_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_APPn_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_APPn_E_MASK) #define VPU_JPEG_ENC_STATUS_12_DRI_E_MASK (0x4U) #define VPU_JPEG_ENC_STATUS_12_DRI_E_SHIFT (2U) /*! DRI_E - Define Restart Interval Error * 0b0..No error is detected in DRI segment. * 0b1..An error is detected in DRI segment. */ #define VPU_JPEG_ENC_STATUS_12_DRI_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_DRI_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_DRI_E_MASK) #define VPU_JPEG_ENC_STATUS_12_DNL_E_MASK (0x8U) #define VPU_JPEG_ENC_STATUS_12_DNL_E_SHIFT (3U) /*! DNL_E - Define Number of Lines Error * 0b0..No error is detected in DNL segment. * 0b1..An error is detected in DNL segment. */ #define VPU_JPEG_ENC_STATUS_12_DNL_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_DNL_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_DNL_E_MASK) #define VPU_JPEG_ENC_STATUS_12_DHT_E_MASK (0x10U) #define VPU_JPEG_ENC_STATUS_12_DHT_E_SHIFT (4U) /*! DHT_E - Define Huffman Table Error * 0b0..No error is detected in DHT segment. * 0b1..An error is detected in DHT segment. */ #define VPU_JPEG_ENC_STATUS_12_DHT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_DHT_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_DHT_E_MASK) #define VPU_JPEG_ENC_STATUS_12_DQT_E_MASK (0x20U) #define VPU_JPEG_ENC_STATUS_12_DQT_E_SHIFT (5U) /*! DQT_E - Define Quantization Table Error * 0b0..No error is detected in DQT segment. * 0b1..An error is detected in DQT segment. */ #define VPU_JPEG_ENC_STATUS_12_DQT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_DQT_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_DQT_E_MASK) #define VPU_JPEG_ENC_STATUS_12_SOS_E_MASK (0x40U) #define VPU_JPEG_ENC_STATUS_12_SOS_E_SHIFT (6U) /*! SOS_E - Start Of Scan Error * 0b0..No error is detected in SOS segment. * 0b1..An error is detected in SOS segment. */ #define VPU_JPEG_ENC_STATUS_12_SOS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_SOS_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_SOS_E_MASK) #define VPU_JPEG_ENC_STATUS_12_SOF_E_MASK (0x80U) #define VPU_JPEG_ENC_STATUS_12_SOF_E_SHIFT (7U) /*! SOF_E - Sequence Of Frame 0 Error * 0b0..No error is detected in Sequence Of Frame 0 segment. * 0b1..An error is detected in Sequence Of Frame 0 segment. */ #define VPU_JPEG_ENC_STATUS_12_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_SOF_E_SHIFT)) & VPU_JPEG_ENC_STATUS_12_SOF_E_MASK) #define VPU_JPEG_ENC_STATUS_12_CONFIGERROR_MASK (0x100U) #define VPU_JPEG_ENC_STATUS_12_CONFIGERROR_SHIFT (8U) /*! CONFIGERROR - Configuration Error * 0b0..No configuration error is detected. * 0b1..A configuration error is detected. */ #define VPU_JPEG_ENC_STATUS_12_CONFIGERROR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_CONFIGERROR_SHIFT)) & VPU_JPEG_ENC_STATUS_12_CONFIGERROR_MASK) #define VPU_JPEG_ENC_STATUS_12_JPEGIN_RDY_MASK (0x200U) #define VPU_JPEG_ENC_STATUS_12_JPEGIN_RDY_SHIFT (9U) /*! JPEGIN_RDY - JPEG Input Ready * 0b0..New JPEG stream input data is not ready to transfer. * 0b1..New JPEG stream input data is ready to transfer. */ #define VPU_JPEG_ENC_STATUS_12_JPEGIN_RDY(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_JPEGIN_RDY_SHIFT)) & VPU_JPEG_ENC_STATUS_12_JPEGIN_RDY_MASK) #define VPU_JPEG_ENC_STATUS_12_PIXELIN_RDY_MASK (0x400U) #define VPU_JPEG_ENC_STATUS_12_PIXELIN_RDY_SHIFT (10U) /*! PIXELIN_RDY - Pixel Input Ready * 0b0..New pixel input data is not ready to transfer. * 0b1..New pixel input data is ready to transfer. */ #define VPU_JPEG_ENC_STATUS_12_PIXELIN_RDY(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_PIXELIN_RDY_SHIFT)) & VPU_JPEG_ENC_STATUS_12_PIXELIN_RDY_MASK) #define VPU_JPEG_ENC_STATUS_12_SCANACTIVE_MASK (0x800U) #define VPU_JPEG_ENC_STATUS_12_SCANACTIVE_SHIFT (11U) /*! SCANACTIVE - Scan Active * 0b0..The core does not encode scan data. * 0b1..The core encodes scan data. */ #define VPU_JPEG_ENC_STATUS_12_SCANACTIVE(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_12_SCANACTIVE_SHIFT)) & VPU_JPEG_ENC_STATUS_12_SCANACTIVE_MASK) /*! @} */ /*! @name STATUS_13 - Status 13 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_13_CFG_MODE_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_13_CFG_MODE_SHIFT (0U) /*! CFG_MODE - Configuration Mode */ #define VPU_JPEG_ENC_STATUS_13_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_13_CFG_MODE_SHIFT)) & VPU_JPEG_ENC_STATUS_13_CFG_MODE_MASK) /*! @} */ /*! @name STATUS_14 - Status 14 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_14_RC_REGS0_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_14_RC_REGS0_SHIFT (0U) /*! RC_REGS0 - Rate Control Register Set 0 */ #define VPU_JPEG_ENC_STATUS_14_RC_REGS0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_14_RC_REGS0_SHIFT)) & VPU_JPEG_ENC_STATUS_14_RC_REGS0_MASK) /*! @} */ /*! @name STATUS_15 - Status 15 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_15_RC_REGS1_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_15_RC_REGS1_SHIFT (0U) /*! RC_REGS1 - Rate Control Register Set 1 */ #define VPU_JPEG_ENC_STATUS_15_RC_REGS1(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_15_RC_REGS1_SHIFT)) & VPU_JPEG_ENC_STATUS_15_RC_REGS1_MASK) /*! @} */ /*! @name STATUS_16 - Status 16 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_16_NOMFRSIZE_LO_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_16_NOMFRSIZE_LO_SHIFT (0U) /*! NOMFRSIZE_LO - Nominal Frame Size Low */ #define VPU_JPEG_ENC_STATUS_16_NOMFRSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_16_NOMFRSIZE_LO_SHIFT)) & VPU_JPEG_ENC_STATUS_16_NOMFRSIZE_LO_MASK) /*! @} */ /*! @name STATUS_17 - Status 17 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_17_NOMFRSIZE_HI_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_17_NOMFRSIZE_HI_SHIFT (0U) /*! NOMFRSIZE_HI - Nominal Frame Size High */ #define VPU_JPEG_ENC_STATUS_17_NOMFRSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_17_NOMFRSIZE_HI_SHIFT)) & VPU_JPEG_ENC_STATUS_17_NOMFRSIZE_HI_MASK) /*! @} */ /*! @name STATUS_18 - Status 18 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_18_OFBSIZE_LO_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_18_OFBSIZE_LO_SHIFT (0U) /*! OFBSIZE_LO - FIFO Buffer Size Low */ #define VPU_JPEG_ENC_STATUS_18_OFBSIZE_LO(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_18_OFBSIZE_LO_SHIFT)) & VPU_JPEG_ENC_STATUS_18_OFBSIZE_LO_MASK) /*! @} */ /*! @name STATUS_19 - Status 19 */ /*! @{ */ #define VPU_JPEG_ENC_STATUS_19_OFBSIZE_HI_MASK (0xFFFFU) #define VPU_JPEG_ENC_STATUS_19_OFBSIZE_HI_SHIFT (0U) /*! OFBSIZE_HI - FIFO Buffer Size High */ #define VPU_JPEG_ENC_STATUS_19_OFBSIZE_HI(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_STATUS_19_OFBSIZE_HI_SHIFT)) & VPU_JPEG_ENC_STATUS_19_OFBSIZE_HI_MASK) /*! @} */ /*! * @} */ /* end of group VPU_JPEG_ENC_Register_Masks */ /* VPU_JPEG_ENC - Peripheral instance base addresses */ /** Peripheral VPU__JPEG_ENC base address */ #define VPU__JPEG_ENC_BASE (0x4C550100u) /** Peripheral VPU__JPEG_ENC base pointer */ #define VPU__JPEG_ENC ((VPU_JPEG_ENC_Type *)VPU__JPEG_ENC_BASE) /** Array initializer of VPU_JPEG_ENC peripheral base addresses */ #define VPU_JPEG_ENC_BASE_ADDRS { VPU__JPEG_ENC_BASE } /** Array initializer of VPU_JPEG_ENC peripheral base pointers */ #define VPU_JPEG_ENC_BASE_PTRS { VPU__JPEG_ENC } /*! * @} */ /* end of group VPU_JPEG_ENC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VPU_JPEG_ENC_WRAP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_JPEG_ENC_WRAP_Peripheral_Access_Layer VPU_JPEG_ENC_WRAP Peripheral Access Layer * @{ */ /** VPU_JPEG_ENC_WRAP - Register Layout Typedef */ typedef struct { __IO uint32_t GLB_CTRL; /**< Global Control, offset: 0x0 */ __I uint32_t COM_STATUS; /**< Common Status, offset: 0x4 */ uint8_t RESERVED_0[12]; __IO uint32_t IN_BUF_BASE0; /**< Input Image Frame Buffer 0 Base Address, offset: 0x14 */ __IO uint32_t IN_BUF_BASE1; /**< Input Image Frame Buffer 1 Base Address, offset: 0x18 */ __IO uint32_t IN_LINE_PITCH; /**< Input Image Frame Buffer Line Pitch, offset: 0x1C */ __IO uint32_t STM_BUFBASE; /**< Output JPEG Stream Buffer Base Address, offset: 0x20 */ __IO uint32_t STM_BUFSIZE; /**< Output JPEG Stream Buffer Size, offset: 0x24 */ __IO uint32_t IMGSIZE; /**< Image Resolution, offset: 0x28 */ __IO uint32_t STM_CTRL; /**< Bit Stream Switch and Control, offset: 0x2C */ uint8_t RESERVED_1[65488]; struct { /* offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_STATUS; /**< Bit Stream Slot Status, array offset: 0x10000, array step: 0x10000 */ __IO uint32_t SLOT_IRQ_EN; /**< Bit Stream Interrupt Enable, array offset: 0x10004, array step: 0x10000 */ __I uint32_t SLOT_BUF_PTR; /**< Bit Stream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */ __I uint32_t SLOT_CUR_DESCPT_PTR; /**< Current Encoding Descriptor Pointer, array offset: 0x1000C, array step: 0x10000 */ __IO uint32_t SLOT_NXT_DESCPT_PTR; /**< Next Encoding Descriptor Pointer, array offset: 0x10010, array step: 0x10000 */ uint8_t RESERVED_0[65516]; } BIT_STREAM[4]; } VPU_JPEG_ENC_WRAP_Type; /* ---------------------------------------------------------------------------- -- VPU_JPEG_ENC_WRAP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_JPEG_ENC_WRAP_Register_Masks VPU_JPEG_ENC_WRAP Register Masks * @{ */ /*! @name GLB_CTRL - Global Control */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_GLB_CTRL_JPG_ENC_EN_MASK (0x1U) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_JPG_ENC_EN_SHIFT (0U) /*! JPG_ENC_EN - JPEG Encoder and Wrapper Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_GLB_CTRL_JPG_ENC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_GLB_CTRL_JPG_ENC_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_GLB_CTRL_JPG_ENC_EN_MASK) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_SFTRST_MASK (0x2U) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_SFTRST_SHIFT (1U) /*! SFTRST - Engine Soft Reset * 0b0..No effect * 0b1..Soft reset */ #define VPU_JPEG_ENC_WRAP_GLB_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_GLB_CTRL_SFTRST_SHIFT)) & VPU_JPEG_ENC_WRAP_GLB_CTRL_SFTRST_MASK) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_ENC_GO_MASK (0x4U) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_ENC_GO_SHIFT (2U) /*! ENC_GO - Start Encoding * 0b0..Do not start encoding * 0b1..Start encoding */ #define VPU_JPEG_ENC_WRAP_GLB_CTRL_ENC_GO(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_GLB_CTRL_ENC_GO_SHIFT)) & VPU_JPEG_ENC_WRAP_GLB_CTRL_ENC_GO_MASK) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_L_ENDIAN_MASK (0x8U) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_L_ENDIAN_SHIFT (3U) /*! L_ENDIAN - Little Endian * 0b0..Enables the big-endian bit stream format * 0b1..Enables the little-endian bit stream format */ #define VPU_JPEG_ENC_WRAP_GLB_CTRL_L_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_GLB_CTRL_L_ENDIAN_SHIFT)) & VPU_JPEG_ENC_WRAP_GLB_CTRL_L_ENDIAN_MASK) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_SLOT_EN_MASK (0xF0U) #define VPU_JPEG_ENC_WRAP_GLB_CTRL_SLOT_EN_SHIFT (4U) /*! SLOT_EN - Slot Enable */ #define VPU_JPEG_ENC_WRAP_GLB_CTRL_SLOT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_GLB_CTRL_SLOT_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_GLB_CTRL_SLOT_EN_MASK) /*! @} */ /*! @name COM_STATUS - Common Status */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_COM_STATUS_CUR_SLOT_MASK (0x60000000U) #define VPU_JPEG_ENC_WRAP_COM_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current Slot */ #define VPU_JPEG_ENC_WRAP_COM_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_COM_STATUS_CUR_SLOT_SHIFT)) & VPU_JPEG_ENC_WRAP_COM_STATUS_CUR_SLOT_MASK) #define VPU_JPEG_ENC_WRAP_COM_STATUS_ENC_ONGOING_MASK (0x80000000U) #define VPU_JPEG_ENC_WRAP_COM_STATUS_ENC_ONGOING_SHIFT (31U) /*! ENC_ONGOING - Encoding Ongoing */ #define VPU_JPEG_ENC_WRAP_COM_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_COM_STATUS_ENC_ONGOING_SHIFT)) & VPU_JPEG_ENC_WRAP_COM_STATUS_ENC_ONGOING_MASK) /*! @} */ /*! @name IN_BUF_BASE0 - Input Image Frame Buffer 0 Base Address */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_IN_BUF_BASE0_IN_BUF_BASE0_MASK (0xFFFFFFF0U) #define VPU_JPEG_ENC_WRAP_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT (4U) /*! IN_BUF_BASE0 - Frame Buffer 0 Base Address */ #define VPU_JPEG_ENC_WRAP_IN_BUF_BASE0_IN_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT)) & VPU_JPEG_ENC_WRAP_IN_BUF_BASE0_IN_BUF_BASE0_MASK) /*! @} */ /*! @name IN_BUF_BASE1 - Input Image Frame Buffer 1 Base Address */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_IN_BUF_BASE1_IN_BUF_BASE1_MASK (0xFFFFFFF0U) #define VPU_JPEG_ENC_WRAP_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT (4U) /*! IN_BUF_BASE1 - Frame Buffer 1 Base Address */ #define VPU_JPEG_ENC_WRAP_IN_BUF_BASE1_IN_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT)) & VPU_JPEG_ENC_WRAP_IN_BUF_BASE1_IN_BUF_BASE1_MASK) /*! @} */ /*! @name IN_LINE_PITCH - Input Image Frame Buffer Line Pitch */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_IN_LINE_PITCH_IN_LINE_PITCH_MASK (0xFFFFU) #define VPU_JPEG_ENC_WRAP_IN_LINE_PITCH_IN_LINE_PITCH_SHIFT (0U) /*! IN_LINE_PITCH - Input Image Line Pitches */ #define VPU_JPEG_ENC_WRAP_IN_LINE_PITCH_IN_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_IN_LINE_PITCH_IN_LINE_PITCH_SHIFT)) & VPU_JPEG_ENC_WRAP_IN_LINE_PITCH_IN_LINE_PITCH_MASK) /*! @} */ /*! @name STM_BUFBASE - Output JPEG Stream Buffer Base Address */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U) #define VPU_JPEG_ENC_WRAP_STM_BUFBASE_STM_BUFBASE_SHIFT (4U) /*! STM_BUFBASE - Bit Stream Buffer Base Address */ #define VPU_JPEG_ENC_WRAP_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_STM_BUFBASE_STM_BUFBASE_SHIFT)) & VPU_JPEG_ENC_WRAP_STM_BUFBASE_STM_BUFBASE_MASK) /*! @} */ /*! @name STM_BUFSIZE - Output JPEG Stream Buffer Size */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U) #define VPU_JPEG_ENC_WRAP_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U) /*! STM_BUFSIZE - Bit Stream Buffer Size */ #define VPU_JPEG_ENC_WRAP_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & VPU_JPEG_ENC_WRAP_STM_BUFSIZE_STM_BUFSIZE_MASK) /*! @} */ /*! @name IMGSIZE - Image Resolution */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_HEIGHT_MASK (0x3FFFU) #define VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_HEIGHT_SHIFT (0U) /*! IMG_HEIGHT - Image Height */ #define VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_HEIGHT_SHIFT)) & VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_HEIGHT_MASK) #define VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_WIDTH_MASK (0x3FFF0000U) #define VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_WIDTH_SHIFT (16U) /*! IMG_WIDTH - Image Width */ #define VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_WIDTH_SHIFT)) & VPU_JPEG_ENC_WRAP_IMGSIZE_IMG_WIDTH_MASK) /*! @} */ /*! @name STM_CTRL - Bit Stream Switch and Control */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_STM_CTRL_PIXEL_PRECISION_MASK (0x4U) #define VPU_JPEG_ENC_WRAP_STM_CTRL_PIXEL_PRECISION_SHIFT (2U) /*! PIXEL_PRECISION - Pixel Precision * 0b0..8-bit * 0b1..12-bit */ #define VPU_JPEG_ENC_WRAP_STM_CTRL_PIXEL_PRECISION(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_STM_CTRL_PIXEL_PRECISION_SHIFT)) & VPU_JPEG_ENC_WRAP_STM_CTRL_PIXEL_PRECISION_MASK) #define VPU_JPEG_ENC_WRAP_STM_CTRL_IMAGE_FORMAT_MASK (0x78U) #define VPU_JPEG_ENC_WRAP_STM_CTRL_IMAGE_FORMAT_SHIFT (3U) /*! IMAGE_FORMAT - Image Format * 0b0000..YUV420 (2-planar, Y at the first planar and UV at the second planar) * 0b0001..YUV422 (1-planar in the YUYV sequence) * 0b0010..RGB (RGBRGB packed format) * 0b0011..YUV444 (1-planar in the YUVYUV sequence) * 0b0100..Gray (Y8 or Y12) or single component * 0b0101..Reserved for future use * 0b0110..ARGB (ARGBARGB packed format) */ #define VPU_JPEG_ENC_WRAP_STM_CTRL_IMAGE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_STM_CTRL_IMAGE_FORMAT_SHIFT)) & VPU_JPEG_ENC_WRAP_STM_CTRL_IMAGE_FORMAT_MASK) #define VPU_JPEG_ENC_WRAP_STM_CTRL_BITBUF_PTR_CLR_MASK (0x80U) #define VPU_JPEG_ENC_WRAP_STM_CTRL_BITBUF_PTR_CLR_SHIFT (7U) /*! BITBUF_PTR_CLR - Bit Buffer Pointer Clear * 0b0..Keeps the last bit stream buffer point. * 0b1..Clears the bit stream buffer point to base value. */ #define VPU_JPEG_ENC_WRAP_STM_CTRL_BITBUF_PTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & VPU_JPEG_ENC_WRAP_STM_CTRL_BITBUF_PTR_CLR_MASK) #define VPU_JPEG_ENC_WRAP_STM_CTRL_AUTO_START_MASK (0x100U) #define VPU_JPEG_ENC_WRAP_STM_CTRL_AUTO_START_SHIFT (8U) /*! AUTO_START - Auto Start * 0b0..Do not write 1 to CTRL[GO] in the JPEG encoder automatically. * 0b1..Writes 1 to CTRL[GO] in the JPEG encoder automatically. */ #define VPU_JPEG_ENC_WRAP_STM_CTRL_AUTO_START(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_STM_CTRL_AUTO_START_SHIFT)) & VPU_JPEG_ENC_WRAP_STM_CTRL_AUTO_START_MASK) #define VPU_JPEG_ENC_WRAP_STM_CTRL_CONFIG_MOD_MASK (0x200U) #define VPU_JPEG_ENC_WRAP_STM_CTRL_CONFIG_MOD_SHIFT (9U) /*! CONFIG_MOD - Configuration Mode * 0b0..No effect * 0b1..In configuration mode */ #define VPU_JPEG_ENC_WRAP_STM_CTRL_CONFIG_MOD(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_STM_CTRL_CONFIG_MOD_SHIFT)) & VPU_JPEG_ENC_WRAP_STM_CTRL_CONFIG_MOD_MASK) /*! @} */ /*! @name SLOT_STATUS - Bit Stream Slot Status */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_HALF_MASK (0x1U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_HALF_SHIFT (0U) /*! STMBUF_HALF - Stream Buffer Half Flag * 0b0..Buffer did not pass the half mark. * 0b1..Buffer passed the half mark. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_HALF_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_HALF_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_RTND_MASK (0x2U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_RTND_SHIFT (1U) /*! STMBUF_RTND - Stream Buffer Returned Flag * 0b0..Buffer did not pass the top mark. * 0b1..Buffer passed the top mark. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_RTND_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_STMBUF_RTND_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_SWITCHED_IN_MASK (0x4U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_SWITCHED_IN_SHIFT (2U) /*! SWITCHED_IN - Switched-In Flag * 0b0..Did not switch. * 0b1..Switched to current slot. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_SWITCHED_IN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_SWITCHED_IN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_FRMDONE_MASK (0x8U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_FRMDONE_SHIFT (3U) /*! FRMDONE - Frame Done Flag * 0b0..Full frame is not encoded. * 0b1..Full frame is encoded. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_FRMDONE(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_FRMDONE_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_FRMDONE_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_CONFG_ERR_MASK (0x100U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_CONFG_ERR_SHIFT (8U) /*! ENC_CONFG_ERR - Encoder Configure Error Flag * 0b0..Error did not occur. * 0b1..Error occurred. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_CONFG_ERR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_CONFG_ERR_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_CONFG_ERR_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_DES_RD_ERR_MASK (0x200U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_DES_RD_ERR_SHIFT (9U) /*! DES_RD_ERR - Descriptor Read Error Flag * 0b0..Error did not occur. * 0b1..Error occurred. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_DES_RD_ERR_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_DES_RD_ERR_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_BIT_WT_ERR_MASK (0x400U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_BIT_WT_ERR_SHIFT (10U) /*! BIT_WT_ERR - Bit Write Error Flag * 0b0..Error did not occur. * 0b1..Error occurred. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_BIT_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_BIT_WT_ERR_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_BIT_WT_ERR_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_IMG_RD_ERR_MASK (0x800U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_IMG_RD_ERR_SHIFT (11U) /*! IMG_RD_ERR - Image Read Error Flag * 0b0..Error did not occur. * 0b1..Error occurred. * 0b0..No effect * 0b1..Clears the flag. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_IMG_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_IMG_RD_ERR_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_IMG_RD_ERR_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_CUR_SLOT_SHIFT (29U) /*! CUR_SLOT - Current Slot */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_CUR_SLOT_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_CUR_SLOT_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_ONGOING_MASK (0x80000000U) #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_ONGOING_SHIFT (31U) /*! ENC_ONGOING - Encoding Ongoing * 0b0..Encoding is paused or stopped. * 0b1..Encoding is ongoing. */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_ONGOING_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_STATUS_ENC_ONGOING_MASK) /*! @} */ /* The count of VPU_JPEG_ENC_WRAP_SLOT_STATUS */ #define VPU_JPEG_ENC_WRAP_SLOT_STATUS_COUNT (4U) /*! @name SLOT_IRQ_EN - Bit Stream Interrupt Enable */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U) /*! STMBUF_HALF_IRQ_EN - Stream Buffer Half Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U) /*! STMBUF_RTND_IRQ_EN - Stream Buffer Returned Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK (0x4U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT (2U) /*! SWITCHED_IN_IRQ_EN - Switched-In Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK (0x8U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U) /*! FRMDONE_IRQ_EN - Frame Done Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_MASK (0x100U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_SHIFT (8U) /*! ENC_CONFG_ERR_IRQ_EN - Encoder Configure Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK (0x200U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT (9U) /*! DES_RD_ERR_IRQ_EN - Descriptor Read Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_MASK (0x400U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_SHIFT (10U) /*! BIT_WT_ERR_IRQ_EN - Bit Write Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_MASK (0x800U) #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_SHIFT (11U) /*! IMG_RD_ERR_IRQ_EN - Image Read Error Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_MASK) /*! @} */ /* The count of VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN */ #define VPU_JPEG_ENC_WRAP_SLOT_IRQ_EN_COUNT (4U) /*! @name SLOT_BUF_PTR - Bit Stream Buffer Pointer */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_MASK (0xFFFFFFFFU) #define VPU_JPEG_ENC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_SHIFT (0U) /*! STMBUF_PTR - Stream 0 Buffer Pointer */ #define VPU_JPEG_ENC_WRAP_SLOT_BUF_PTR_STMBUF_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_BUF_PTR_STMBUF_PTR_MASK) /*! @} */ /* The count of VPU_JPEG_ENC_WRAP_SLOT_BUF_PTR */ #define VPU_JPEG_ENC_WRAP_SLOT_BUF_PTR_COUNT (4U) /*! @name SLOT_CUR_DESCPT_PTR - Current Encoding Descriptor Pointer */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PTR_MASK (0xFFFFFFFCU) #define VPU_JPEG_ENC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PTR_SHIFT (2U) /*! CUR_DESCPT_PTR - Current Descriptors Pointer */ #define VPU_JPEG_ENC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PTR_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PTR_MASK) /*! @} */ /* The count of VPU_JPEG_ENC_WRAP_SLOT_CUR_DESCPT_PTR */ #define VPU_JPEG_ENC_WRAP_SLOT_CUR_DESCPT_PTR_COUNT (4U) /*! @name SLOT_NXT_DESCPT_PTR - Next Encoding Descriptor Pointer */ /*! @{ */ #define VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK (0x1U) #define VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT (0U) /*! NXT_DESCPT_PTR_EN - Slot Next Stream Descriptor Pointer Enable * 0b0..Invalid * 0b1..Valid */ #define VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK) #define VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_MASK (0xFFFFFFFCU) #define VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_SHIFT (2U) /*! NXT_DESCPT_PTR - Slot Next Encoding Descriptors Pointer */ #define VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_SHIFT)) & VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_MASK) /*! @} */ /* The count of VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR */ #define VPU_JPEG_ENC_WRAP_SLOT_NXT_DESCPT_PTR_COUNT (4U) /*! * @} */ /* end of group VPU_JPEG_ENC_WRAP_Register_Masks */ /* VPU_JPEG_ENC_WRAP - Peripheral instance base addresses */ /** Peripheral VPU__JPEG_ENC_WRAP base address */ #define VPU__JPEG_ENC_WRAP_BASE (0x4C550000u) /** Peripheral VPU__JPEG_ENC_WRAP base pointer */ #define VPU__JPEG_ENC_WRAP ((VPU_JPEG_ENC_WRAP_Type *)VPU__JPEG_ENC_WRAP_BASE) /** Array initializer of VPU_JPEG_ENC_WRAP peripheral base addresses */ #define VPU_JPEG_ENC_WRAP_BASE_ADDRS { VPU__JPEG_ENC_WRAP_BASE } /** Array initializer of VPU_JPEG_ENC_WRAP peripheral base pointers */ #define VPU_JPEG_ENC_WRAP_BASE_PTRS { VPU__JPEG_ENC_WRAP } /*! * @} */ /* end of group VPU_JPEG_ENC_WRAP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VPU_TCU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_TCU_Peripheral_Access_Layer VPU_TCU Peripheral Access Layer * @{ */ /** VPU_TCU - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW0; /**< Magic KW0, offset: 0x400 */ uint8_t RESERVED_1[12]; __IO uint32_t TCU_MAGIC_KW__MAGIC_KW1; /**< Magic KW1, offset: 0x410 */ uint8_t RESERVED_2[2028]; __IO uint32_t TCU_PLL_COUNTER; /**< tcu pll counter reg, offset: 0xC00 */ uint8_t RESERVED_3[60]; __IO uint32_t TCU_DFT_FUSE; /**< TCU fuse observe and override, offset: 0xC40 */ } VPU_TCU_Type; /* ---------------------------------------------------------------------------- -- VPU_TCU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VPU_TCU_Register_Masks VPU_TCU Register Masks * @{ */ /*! @name TCU_MAGIC_KW__MAGIC_KW0 - Magic KW0 */ /*! @{ */ #define VPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK (0xFFFFFFFFU) #define VPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT (0U) /*! out - 32-Bit Magic KW0 used in conjuction with Magic KW1 to unlock the writes to test mode registers (Value is 0x12345678) */ #define VPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_SHIFT)) & VPU_TCU_TCU_MAGIC_KW__MAGIC_KW0_out_MASK) /*! @} */ /*! @name TCU_MAGIC_KW__MAGIC_KW1 - Magic KW1 */ /*! @{ */ #define VPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK (0xFFFFFFFFU) #define VPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT (0U) /*! out - 32-Bit Magic KW1 used in conjuction with Magic KW0 to unlock the writes to test mode registers (Value - 0x87654321) */ #define VPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_SHIFT)) & VPU_TCU_TCU_MAGIC_KW__MAGIC_KW1_out_MASK) /*! @} */ /*! @name TCU_PLL_COUNTER - tcu pll counter reg */ /*! @{ */ #define VPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK (0x1U) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT (0U) /*! pll_count_rst_n - pll count reset */ #define VPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_SHIFT)) & VPU_TCU_TCU_PLL_COUNTER_pll_count_rst_n_MASK) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_start_MASK (0x2U) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT (1U) /*! pll_count_start - pll count start */ #define VPU_TCU_TCU_PLL_COUNTER_pll_count_start(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_PLL_COUNTER_pll_count_start_SHIFT)) & VPU_TCU_TCU_PLL_COUNTER_pll_count_start_MASK) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK (0x4U) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT (2U) /*! pll_count_div_en - pll count div en */ #define VPU_TCU_TCU_PLL_COUNTER_pll_count_div_en(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_SHIFT)) & VPU_TCU_TCU_PLL_COUNTER_pll_count_div_en_MASK) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK (0x38U) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT (3U) /*! pll_count_clk_sel - pll count clk sel */ #define VPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_SHIFT)) & VPU_TCU_TCU_PLL_COUNTER_pll_count_clk_sel_MASK) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK (0xFF00U) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT (8U) /*! pll_count_ref_val - pll count ref val */ #define VPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_SHIFT)) & VPU_TCU_TCU_PLL_COUNTER_pll_count_ref_val_MASK) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK (0xFFFF0000U) #define VPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT (16U) /*! pll_count_cnt - pll count cnt */ #define VPU_TCU_TCU_PLL_COUNTER_pll_count_cnt(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_SHIFT)) & VPU_TCU_TCU_PLL_COUNTER_pll_count_cnt_MASK) /*! @} */ /*! @name TCU_DFT_FUSE - TCU fuse observe and override */ /*! @{ */ #define VPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK (0x1U) #define VPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT (0U) /*! tcu_dft_fuse_disable - dft fuse disable */ #define VPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_SHIFT)) & VPU_TCU_TCU_DFT_FUSE_tcu_dft_fuse_disable_MASK) #define VPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK (0xEU) #define VPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT (1U) /*! tcu_fuse_obs - fuse observation */ #define VPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs(x) (((uint32_t)(((uint32_t)(x)) << VPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_SHIFT)) & VPU_TCU_TCU_DFT_FUSE_tcu_fuse_obs_MASK) /*! @} */ /*! * @} */ /* end of group VPU_TCU_Register_Masks */ /* VPU_TCU - Peripheral instance base addresses */ /** Peripheral VPU__TCU base address */ #define VPU__TCU_BASE (0x4C400000u) /** Peripheral VPU__TCU base pointer */ #define VPU__TCU ((VPU_TCU_Type *)VPU__TCU_BASE) /** Array initializer of VPU_TCU peripheral base addresses */ #define VPU_TCU_BASE_ADDRS { VPU__TCU_BASE } /** Array initializer of VPU_TCU peripheral base pointers */ #define VPU_TCU_BASE_PTRS { VPU__TCU } /*! * @} */ /* end of group VPU_TCU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_AHBRM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_AHBRM_Peripheral_Access_Layer WAKEUP_AHBRM Peripheral Access Layer * @{ */ /** WAKEUP_AHBRM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[2048]; __O uint32_t CR; /**< Control, offset: 0x800 */ __I uint32_t SR; /**< Status tag, offset: 0x804 */ __I uint32_t TAG; /**< Virtual tag, offset: 0x808 */ __I uint32_t DATA; /**< Physical Address Data, offset: 0x80C */ __O uint32_t DID_CR; /**< Domain ID Control, offset: 0x810 */ __I uint32_t DID_SR; /**< Domain ID Status tag, offset: 0x814 */ } WAKEUP_AHBRM_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_AHBRM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_AHBRM_Register_Masks WAKEUP_AHBRM Register Masks * @{ */ /*! @name CR - Control */ /*! @{ */ #define WAKEUP_AHBRM_CR_ENB_MASK (0x1U) #define WAKEUP_AHBRM_CR_ENB_SHIFT (0U) /*! ENB - Enable Remap. * 0b0..The module is disabled and all input AHB addresses & attributes are simply routed to the output AHB address & attributes buses. * 0b1..All AHB addresses from the designed bus master (typically a processor core) are remapped using the * constant offset defined by the CR[RADDR] field. AHB accesses from other bus masters are simply passed through * the module as if it was disabled. */ #define WAKEUP_AHBRM_CR_ENB(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_CR_ENB_SHIFT)) & WAKEUP_AHBRM_CR_ENB_MASK) #define WAKEUP_AHBRM_CR_INV_MASK (0x4U) #define WAKEUP_AHBRM_CR_INV_SHIFT (2U) /*! INV - Invalidate Tag register. */ #define WAKEUP_AHBRM_CR_INV(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_CR_INV_SHIFT)) & WAKEUP_AHBRM_CR_INV_MASK) #define WAKEUP_AHBRM_CR_LK_MASK (0x8U) #define WAKEUP_AHBRM_CR_LK_SHIFT (3U) /*! LK - Sticky lock bit. */ #define WAKEUP_AHBRM_CR_LK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_CR_LK_SHIFT)) & WAKEUP_AHBRM_CR_LK_MASK) #define WAKEUP_AHBRM_CR_RADDR_MASK (0xFFFFF80U) #define WAKEUP_AHBRM_CR_RADDR_SHIFT (7U) /*! RADDR - Remap address. */ #define WAKEUP_AHBRM_CR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_CR_RADDR_SHIFT)) & WAKEUP_AHBRM_CR_RADDR_MASK) /*! @} */ /*! @name SR - Status tag */ /*! @{ */ #define WAKEUP_AHBRM_SR_ENB_MASK (0x1U) #define WAKEUP_AHBRM_SR_ENB_SHIFT (0U) /*! ENB - Enable Remap. * 0b0..The module is disabled and all input AHB addresses & attributes are simply routed to the output AHB address & attributes buses. * 0b1..All AHB addresses from the designed bus master (typically a processor core) are remapped using the * constant offset defined by the CR[RADDR] field. AHB accesses from other bus masters are simply passed through * the module as if it was disabled. */ #define WAKEUP_AHBRM_SR_ENB(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_SR_ENB_SHIFT)) & WAKEUP_AHBRM_SR_ENB_MASK) #define WAKEUP_AHBRM_SR_INV_MASK (0x4U) #define WAKEUP_AHBRM_SR_INV_SHIFT (2U) /*! INV - Invalidate Tag register. */ #define WAKEUP_AHBRM_SR_INV(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_SR_INV_SHIFT)) & WAKEUP_AHBRM_SR_INV_MASK) #define WAKEUP_AHBRM_SR_LK_MASK (0x8U) #define WAKEUP_AHBRM_SR_LK_SHIFT (3U) /*! LK - Sticky lock bit. */ #define WAKEUP_AHBRM_SR_LK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_SR_LK_SHIFT)) & WAKEUP_AHBRM_SR_LK_MASK) #define WAKEUP_AHBRM_SR_RADDR_MASK (0xFFFFF80U) #define WAKEUP_AHBRM_SR_RADDR_SHIFT (7U) /*! RADDR - Remap address. */ #define WAKEUP_AHBRM_SR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_SR_RADDR_SHIFT)) & WAKEUP_AHBRM_SR_RADDR_MASK) /*! @} */ /*! @name TAG - Virtual tag */ /*! @{ */ #define WAKEUP_AHBRM_TAG_VLD_MASK (0x1U) #define WAKEUP_AHBRM_TAG_VLD_SHIFT (0U) /*! VLD - This bit indicates the validity of the entry. * 0b0..Disabled. * 0b1..Enabled. */ #define WAKEUP_AHBRM_TAG_VLD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_TAG_VLD_SHIFT)) & WAKEUP_AHBRM_TAG_VLD_MASK) #define WAKEUP_AHBRM_TAG_VADDR_MASK (0xFFFFFF80U) #define WAKEUP_AHBRM_TAG_VADDR_SHIFT (7U) /*! VADDR - This bit indicates the virtual address. */ #define WAKEUP_AHBRM_TAG_VADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_TAG_VADDR_SHIFT)) & WAKEUP_AHBRM_TAG_VADDR_MASK) /*! @} */ /*! @name DATA - Physical Address Data */ /*! @{ */ #define WAKEUP_AHBRM_DATA_VADDRL_MASK (0x7FU) #define WAKEUP_AHBRM_DATA_VADDRL_SHIFT (0U) /*! VADDRL - This bit indicates the low portion of the virtual address. */ #define WAKEUP_AHBRM_DATA_VADDRL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DATA_VADDRL_SHIFT)) & WAKEUP_AHBRM_DATA_VADDRL_MASK) #define WAKEUP_AHBRM_DATA_PADDR_MASK (0xFFFFF80U) #define WAKEUP_AHBRM_DATA_PADDR_SHIFT (7U) /*! PADDR - This bit indicates the physical address. */ #define WAKEUP_AHBRM_DATA_PADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DATA_PADDR_SHIFT)) & WAKEUP_AHBRM_DATA_PADDR_MASK) #define WAKEUP_AHBRM_DATA_VADDRH_MASK (0xF0000000U) #define WAKEUP_AHBRM_DATA_VADDRH_SHIFT (28U) /*! VADDRH - This bit indicates the high portion of the virtual address. */ #define WAKEUP_AHBRM_DATA_VADDRH(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DATA_VADDRH_SHIFT)) & WAKEUP_AHBRM_DATA_VADDRH_MASK) /*! @} */ /*! @name DID_CR - Domain ID Control */ /*! @{ */ #define WAKEUP_AHBRM_DID_CR_LK_MASK (0x1U) #define WAKEUP_AHBRM_DID_CR_LK_SHIFT (0U) /*! LK - Sticky lock bit. */ #define WAKEUP_AHBRM_DID_CR_LK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DID_CR_LK_SHIFT)) & WAKEUP_AHBRM_DID_CR_LK_MASK) #define WAKEUP_AHBRM_DID_CR_MSK_MASK (0xF000000U) #define WAKEUP_AHBRM_DID_CR_MSK_SHIFT (24U) /*! MSK - Domain ID match mask. */ #define WAKEUP_AHBRM_DID_CR_MSK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DID_CR_MSK_SHIFT)) & WAKEUP_AHBRM_DID_CR_MSK_MASK) #define WAKEUP_AHBRM_DID_CR_VAL_MASK (0xF0000000U) #define WAKEUP_AHBRM_DID_CR_VAL_SHIFT (28U) /*! VAL - Domain ID match value. */ #define WAKEUP_AHBRM_DID_CR_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DID_CR_VAL_SHIFT)) & WAKEUP_AHBRM_DID_CR_VAL_MASK) /*! @} */ /*! @name DID_SR - Domain ID Status tag */ /*! @{ */ #define WAKEUP_AHBRM_DID_SR_LK_MASK (0x1U) #define WAKEUP_AHBRM_DID_SR_LK_SHIFT (0U) /*! LK - Sticky lock bit. */ #define WAKEUP_AHBRM_DID_SR_LK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DID_SR_LK_SHIFT)) & WAKEUP_AHBRM_DID_SR_LK_MASK) #define WAKEUP_AHBRM_DID_SR_MSK_MASK (0xF000000U) #define WAKEUP_AHBRM_DID_SR_MSK_SHIFT (24U) /*! MSK - Domain ID match mask. */ #define WAKEUP_AHBRM_DID_SR_MSK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DID_SR_MSK_SHIFT)) & WAKEUP_AHBRM_DID_SR_MSK_MASK) #define WAKEUP_AHBRM_DID_SR_VAL_MASK (0xF0000000U) #define WAKEUP_AHBRM_DID_SR_VAL_SHIFT (28U) /*! VAL - Domain ID match value. */ #define WAKEUP_AHBRM_DID_SR_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AHBRM_DID_SR_VAL_SHIFT)) & WAKEUP_AHBRM_DID_SR_VAL_MASK) /*! @} */ /*! * @} */ /* end of group WAKEUP_AHBRM_Register_Masks */ /* WAKEUP_AHBRM - Peripheral instance base addresses */ /** Peripheral WAKEUP__AHBRM1 base address */ #define WAKEUP__AHBRM1_BASE (0x425E0000u) /** Peripheral WAKEUP__AHBRM1 base pointer */ #define WAKEUP__AHBRM1 ((WAKEUP_AHBRM_Type *)WAKEUP__AHBRM1_BASE) /** Array initializer of WAKEUP_AHBRM peripheral base addresses */ #define WAKEUP_AHBRM_BASE_ADDRS { WAKEUP__AHBRM1_BASE } /** Array initializer of WAKEUP_AHBRM peripheral base pointers */ #define WAKEUP_AHBRM_BASE_PTRS { WAKEUP__AHBRM1 } /*! * @} */ /* end of group WAKEUP_AHBRM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_ATU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_ATU_Peripheral_Access_Layer WAKEUP_ATU Peripheral Access Layer * @{ */ /** WAKEUP_ATU - Register Layout Typedef */ typedef struct { __IO uint32_t ATUCR; /**< ATU Control Register, offset: 0x0 */ __IO uint32_t ATUSR; /**< ATU Status Register, offset: 0x4 */ __I uint32_t IP_REV_1; /**< IP Block Revision 1 Register, offset: 0x8 */ __I uint32_t IP_REV_2; /**< IP Block Revision 2 Register, offset: 0xC */ uint8_t RESERVED_0[12]; __IO uint32_t PMCR; /**< Performance Monitor Register, offset: 0x1C */ uint8_t RESERVED_1[228]; __IO uint32_t ACORE_OWAR1; /**< Outbound Window Attributes Register 1, offset: 0x104 */ __IO uint32_t ACORE_OTEAR0; /**< Outbound Translated Extended Address Register 0, offset: 0x108 */ uint8_t RESERVED_2[4]; __IO uint32_t ACORE_OWBAR1; /**< Outbound Window Base Address Register 1, offset: 0x110 */ __IO uint32_t ACORE_OWAR2; /**< Outbound Window Attributes Register 2, offset: 0x114 */ __IO uint32_t ACORE_OTEAR1; /**< Outbound Translated Extended Address Register 1, offset: 0x118 */ __IO uint32_t ACORE_OTAR1; /**< Outbound Translated Address Register 1, offset: 0x11C */ __IO uint32_t ACORE_OWBAR2; /**< Outbound Window Base Address Register 2, offset: 0x120 */ __IO uint32_t ACORE_OWAR3; /**< Outbound Window Attributes Register 3, offset: 0x124 */ __IO uint32_t ACORE_OTEAR2; /**< Outbound Translated Extended Address Register 2, offset: 0x128 */ __IO uint32_t ACORE_OTAR2; /**< Outbound Translated Address Register 2, offset: 0x12C */ __IO uint32_t ACORE_OWBAR3; /**< Outbound Window Base Address Register 3, offset: 0x130 */ __IO uint32_t ACORE_OWAR4; /**< Outbound Window Attributes Register 4, offset: 0x134 */ __IO uint32_t ACORE_OTEAR3; /**< Outbound Translated Extended Address Register 3, offset: 0x138 */ __IO uint32_t ACORE_OTAR3; /**< Outbound Translated Address Register 3, offset: 0x13C */ __IO uint32_t ACORE_OWBAR4; /**< Outbound Window Base Address Register 4, offset: 0x140 */ __IO uint32_t ACORE_OWAR5; /**< Outbound Window Attributes Register 5, offset: 0x144 */ __IO uint32_t ACORE_OTEAR4; /**< Outbound Translated Extended Address Register 4, offset: 0x148 */ __IO uint32_t ACORE_OTAR4; /**< Outbound Translated Address Register 4, offset: 0x14C */ __IO uint32_t ACORE_OWBAR5; /**< Outbound Window Base Address Register 5, offset: 0x150 */ __IO uint32_t ACORE_OWAR6; /**< Outbound Window Attributes Register 6, offset: 0x154 */ __IO uint32_t ACORE_OTEAR5; /**< Outbound Translated Extended Address Register 5, offset: 0x158 */ __IO uint32_t ACORE_OTAR5; /**< Outbound Translated Address Register 5, offset: 0x15C */ __IO uint32_t ACORE_OWBAR6; /**< Outbound Window Base Address Register 6, offset: 0x160 */ __IO uint32_t ACORE_OWAR7; /**< Outbound Window Attributes Register 7, offset: 0x164 */ __IO uint32_t ACORE_OTEAR6; /**< Outbound Translated Extended Address Register 6, offset: 0x168 */ __IO uint32_t ACORE_OTAR6; /**< Outbound Translated Address Register 6, offset: 0x16C */ __IO uint32_t ACORE_OWBAR7; /**< Outbound Window Base Address Register 7, offset: 0x170 */ uint8_t RESERVED_3[4]; __IO uint32_t ACORE_OTEAR7; /**< Outbound Translated Extended Address Register 7, offset: 0x178 */ __IO uint32_t ACORE_OTAR7; /**< Outbound Translated Address Register 7, offset: 0x17C */ } WAKEUP_ATU_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_ATU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_ATU_Register_Masks WAKEUP_ATU Register Masks * @{ */ /*! @name ATUCR - ATU Control Register */ /*! @{ */ #define WAKEUP_ATU_ATUCR_Spare4_MASK (0x1U) #define WAKEUP_ATU_ATUCR_Spare4_SHIFT (0U) /*! Spare4 - Spare 4 - Reserved */ #define WAKEUP_ATU_ATUCR_Spare4(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUCR_Spare4_SHIFT)) & WAKEUP_ATU_ATUCR_Spare4_MASK) #define WAKEUP_ATU_ATUCR_Spare3_MASK (0x2U) #define WAKEUP_ATU_ATUCR_Spare3_SHIFT (1U) /*! Spare3 - Spare 3 - Reserved */ #define WAKEUP_ATU_ATUCR_Spare3(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUCR_Spare3_SHIFT)) & WAKEUP_ATU_ATUCR_Spare3_MASK) #define WAKEUP_ATU_ATUCR_Spare2_MASK (0x4U) #define WAKEUP_ATU_ATUCR_Spare2_SHIFT (2U) /*! Spare2 - Spare 2 - Reserved */ #define WAKEUP_ATU_ATUCR_Spare2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUCR_Spare2_SHIFT)) & WAKEUP_ATU_ATUCR_Spare2_MASK) #define WAKEUP_ATU_ATUCR_Spare1_MASK (0x8U) #define WAKEUP_ATU_ATUCR_Spare1_SHIFT (3U) /*! Spare1 - Spare 1 - Reserved */ #define WAKEUP_ATU_ATUCR_Spare1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUCR_Spare1_SHIFT)) & WAKEUP_ATU_ATUCR_Spare1_MASK) /*! @} */ /*! @name ATUSR - ATU Status Register */ /*! @{ */ #define WAKEUP_ATU_ATUSR_MISS_ALL_MASK (0x1U) #define WAKEUP_ATU_ATUSR_MISS_ALL_SHIFT (0U) /*! MISS_ALL - Miss all * 0b0..No window misses have been detected * 0b1..At least one transaction has been received which missed all windows (sticky) */ #define WAKEUP_ATU_ATUSR_MISS_ALL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_MISS_ALL_SHIFT)) & WAKEUP_ATU_ATUSR_MISS_ALL_MASK) #define WAKEUP_ATU_ATUSR_PGERR_W1_MASK (0x2U) #define WAKEUP_ATU_ATUSR_PGERR_W1_SHIFT (1U) /*! PGERR_W1 - Programming Error on Window 1 * 0b0..No programming error was detected for this window * 0b1..A programming error was detected for this window */ #define WAKEUP_ATU_ATUSR_PGERR_W1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_PGERR_W1_SHIFT)) & WAKEUP_ATU_ATUSR_PGERR_W1_MASK) #define WAKEUP_ATU_ATUSR_PGERR_W2_MASK (0x4U) #define WAKEUP_ATU_ATUSR_PGERR_W2_SHIFT (2U) /*! PGERR_W2 - Programming Error on Window 2 * 0b0..No programming error was detected for this window * 0b1..A programming error was detected for this window */ #define WAKEUP_ATU_ATUSR_PGERR_W2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_PGERR_W2_SHIFT)) & WAKEUP_ATU_ATUSR_PGERR_W2_MASK) #define WAKEUP_ATU_ATUSR_PGERR_W3_MASK (0x8U) #define WAKEUP_ATU_ATUSR_PGERR_W3_SHIFT (3U) /*! PGERR_W3 - Programming Error on Window 3 * 0b0..No programming error was detected for this window * 0b1..A programming error was detected for this window */ #define WAKEUP_ATU_ATUSR_PGERR_W3(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_PGERR_W3_SHIFT)) & WAKEUP_ATU_ATUSR_PGERR_W3_MASK) #define WAKEUP_ATU_ATUSR_PGERR_W4_MASK (0x10U) #define WAKEUP_ATU_ATUSR_PGERR_W4_SHIFT (4U) /*! PGERR_W4 - Programming Error on Window 4 * 0b0..No programming error was detected for this window * 0b1..A programming error was detected for this window */ #define WAKEUP_ATU_ATUSR_PGERR_W4(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_PGERR_W4_SHIFT)) & WAKEUP_ATU_ATUSR_PGERR_W4_MASK) #define WAKEUP_ATU_ATUSR_PGERR_W5_MASK (0x20U) #define WAKEUP_ATU_ATUSR_PGERR_W5_SHIFT (5U) /*! PGERR_W5 - Programming Error on Window 5 * 0b0..No programming error was detected for this window * 0b1..A programming error was detected for this window */ #define WAKEUP_ATU_ATUSR_PGERR_W5(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_PGERR_W5_SHIFT)) & WAKEUP_ATU_ATUSR_PGERR_W5_MASK) #define WAKEUP_ATU_ATUSR_PGERR_W6_MASK (0x40U) #define WAKEUP_ATU_ATUSR_PGERR_W6_SHIFT (6U) /*! PGERR_W6 - Programming Error on Window 6 * 0b0..No programming error was detected for this window * 0b1..A programming error was detected for this window */ #define WAKEUP_ATU_ATUSR_PGERR_W6(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_PGERR_W6_SHIFT)) & WAKEUP_ATU_ATUSR_PGERR_W6_MASK) #define WAKEUP_ATU_ATUSR_PGERR_W7_MASK (0x80U) #define WAKEUP_ATU_ATUSR_PGERR_W7_SHIFT (7U) /*! PGERR_W7 - Programming Error on Window 7 * 0b0..No programming error was detected for this window * 0b1..A programming error was detected for this window */ #define WAKEUP_ATU_ATUSR_PGERR_W7(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ATUSR_PGERR_W7_SHIFT)) & WAKEUP_ATU_ATUSR_PGERR_W7_MASK) /*! @} */ /*! @name IP_REV_1 - IP Block Revision 1 Register */ /*! @{ */ #define WAKEUP_ATU_IP_REV_1_IP_MN_MASK (0xFFU) #define WAKEUP_ATU_IP_REV_1_IP_MN_SHIFT (0U) #define WAKEUP_ATU_IP_REV_1_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_IP_REV_1_IP_MN_SHIFT)) & WAKEUP_ATU_IP_REV_1_IP_MN_MASK) #define WAKEUP_ATU_IP_REV_1_IP_MJ_MASK (0xFF00U) #define WAKEUP_ATU_IP_REV_1_IP_MJ_SHIFT (8U) #define WAKEUP_ATU_IP_REV_1_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_IP_REV_1_IP_MJ_SHIFT)) & WAKEUP_ATU_IP_REV_1_IP_MJ_MASK) #define WAKEUP_ATU_IP_REV_1_IP_ID_MASK (0xFFFF0000U) #define WAKEUP_ATU_IP_REV_1_IP_ID_SHIFT (16U) #define WAKEUP_ATU_IP_REV_1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_IP_REV_1_IP_ID_SHIFT)) & WAKEUP_ATU_IP_REV_1_IP_ID_MASK) /*! @} */ /*! @name IP_REV_2 - IP Block Revision 2 Register */ /*! @{ */ #define WAKEUP_ATU_IP_REV_2_IP_CFG_MASK (0xFFU) #define WAKEUP_ATU_IP_REV_2_IP_CFG_SHIFT (0U) #define WAKEUP_ATU_IP_REV_2_IP_CFG(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_IP_REV_2_IP_CFG_SHIFT)) & WAKEUP_ATU_IP_REV_2_IP_CFG_MASK) #define WAKEUP_ATU_IP_REV_2_IP_ERR_MASK (0xFF00U) #define WAKEUP_ATU_IP_REV_2_IP_ERR_SHIFT (8U) #define WAKEUP_ATU_IP_REV_2_IP_ERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_IP_REV_2_IP_ERR_SHIFT)) & WAKEUP_ATU_IP_REV_2_IP_ERR_MASK) #define WAKEUP_ATU_IP_REV_2_IP_INT_MASK (0xFF0000U) #define WAKEUP_ATU_IP_REV_2_IP_INT_SHIFT (16U) #define WAKEUP_ATU_IP_REV_2_IP_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_IP_REV_2_IP_INT_SHIFT)) & WAKEUP_ATU_IP_REV_2_IP_INT_MASK) /*! @} */ /*! @name PMCR - Performance Monitor Register */ /*! @{ */ #define WAKEUP_ATU_PMCR_PM2_SEL_MASK (0xFFU) #define WAKEUP_ATU_PMCR_PM2_SEL_SHIFT (0U) #define WAKEUP_ATU_PMCR_PM2_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_PM2_SEL_SHIFT)) & WAKEUP_ATU_PMCR_PM2_SEL_MASK) #define WAKEUP_ATU_PMCR_TM2_MSK_MASK (0x700U) #define WAKEUP_ATU_PMCR_TM2_MSK_SHIFT (8U) #define WAKEUP_ATU_PMCR_TM2_MSK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_TM2_MSK_SHIFT)) & WAKEUP_ATU_PMCR_TM2_MSK_MASK) #define WAKEUP_ATU_PMCR_TM2_VAL_MASK (0x3800U) #define WAKEUP_ATU_PMCR_TM2_VAL_SHIFT (11U) #define WAKEUP_ATU_PMCR_TM2_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_TM2_VAL_SHIFT)) & WAKEUP_ATU_PMCR_TM2_VAL_MASK) #define WAKEUP_ATU_PMCR_PM2_TYP_MASK (0xC000U) #define WAKEUP_ATU_PMCR_PM2_TYP_SHIFT (14U) #define WAKEUP_ATU_PMCR_PM2_TYP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_PM2_TYP_SHIFT)) & WAKEUP_ATU_PMCR_PM2_TYP_MASK) #define WAKEUP_ATU_PMCR_PM1_SEL_MASK (0xFF0000U) #define WAKEUP_ATU_PMCR_PM1_SEL_SHIFT (16U) #define WAKEUP_ATU_PMCR_PM1_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_PM1_SEL_SHIFT)) & WAKEUP_ATU_PMCR_PM1_SEL_MASK) #define WAKEUP_ATU_PMCR_TM1_MSK_MASK (0x7000000U) #define WAKEUP_ATU_PMCR_TM1_MSK_SHIFT (24U) #define WAKEUP_ATU_PMCR_TM1_MSK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_TM1_MSK_SHIFT)) & WAKEUP_ATU_PMCR_TM1_MSK_MASK) #define WAKEUP_ATU_PMCR_TM1_VAL_MASK (0x38000000U) #define WAKEUP_ATU_PMCR_TM1_VAL_SHIFT (27U) #define WAKEUP_ATU_PMCR_TM1_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_TM1_VAL_SHIFT)) & WAKEUP_ATU_PMCR_TM1_VAL_MASK) #define WAKEUP_ATU_PMCR_PM1_TYP_MASK (0xC0000000U) #define WAKEUP_ATU_PMCR_PM1_TYP_SHIFT (30U) /*! PM1_TYP * 0b00..This performance monitor event is disabled * 0b01..This performance monitor event is enabled for data read transactions only * 0b10..This performance monitor event is enabled for data write transactions only * 0b11..This performance monitor event is enabled for instruction fetch transactions only */ #define WAKEUP_ATU_PMCR_PM1_TYP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_PMCR_PM1_TYP_SHIFT)) & WAKEUP_ATU_PMCR_PM1_TYP_MASK) /*! @} */ /*! @name ACORE_OWAR1 - Outbound Window Attributes Register 1 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWAR1_EN_MASK (0x80000000U) #define WAKEUP_ATU_ACORE_OWAR1_EN_SHIFT (31U) /*! EN * 0b0..Disable outbound translation window * 0b1..Enable outbound translation window */ #define WAKEUP_ATU_ACORE_OWAR1_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWAR1_EN_SHIFT)) & WAKEUP_ATU_ACORE_OWAR1_EN_MASK) /*! @} */ /*! @name ACORE_OTEAR0 - Outbound Translated Extended Address Register 0 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR0_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR0_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR0_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR0_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR0_TEA_MASK) /*! @} */ /*! @name ACORE_OWBAR1 - Outbound Window Base Address Register 1 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWBAR1_OWS_MASK (0x1FU) #define WAKEUP_ATU_ACORE_OWBAR1_OWS_SHIFT (0U) /*! OWS - Outbound Window Size */ #define WAKEUP_ATU_ACORE_OWBAR1_OWS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR1_OWS_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR1_OWS_MASK) #define WAKEUP_ATU_ACORE_OWBAR1_WBA_MASK (0xFFF0000U) #define WAKEUP_ATU_ACORE_OWBAR1_WBA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OWBAR1_WBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR1_WBA_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR1_WBA_MASK) #define WAKEUP_ATU_ACORE_OWBAR1_DOMAIN_ID_MASK (0xF0000000U) #define WAKEUP_ATU_ACORE_OWBAR1_DOMAIN_ID_SHIFT (28U) /*! DOMAIN_ID - Domain identifier */ #define WAKEUP_ATU_ACORE_OWBAR1_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR1_DOMAIN_ID_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR1_DOMAIN_ID_MASK) /*! @} */ /*! @name ACORE_OWAR2 - Outbound Window Attributes Register 2 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWAR2_EN_MASK (0x80000000U) #define WAKEUP_ATU_ACORE_OWAR2_EN_SHIFT (31U) /*! EN * 0b0..Disable outbound translation window * 0b1..Enable outbound translation window */ #define WAKEUP_ATU_ACORE_OWAR2_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWAR2_EN_SHIFT)) & WAKEUP_ATU_ACORE_OWAR2_EN_MASK) /*! @} */ /*! @name ACORE_OTEAR1 - Outbound Translated Extended Address Register 1 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR1_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR1_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR1_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR1_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR1_TEA_MASK) /*! @} */ /*! @name ACORE_OTAR1 - Outbound Translated Address Register 1 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTAR1_TA_MASK (0xFFFF0000U) #define WAKEUP_ATU_ACORE_OTAR1_TA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OTAR1_TA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTAR1_TA_SHIFT)) & WAKEUP_ATU_ACORE_OTAR1_TA_MASK) /*! @} */ /*! @name ACORE_OWBAR2 - Outbound Window Base Address Register 2 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWBAR2_OWS_MASK (0x1FU) #define WAKEUP_ATU_ACORE_OWBAR2_OWS_SHIFT (0U) /*! OWS - Outbound Window Size */ #define WAKEUP_ATU_ACORE_OWBAR2_OWS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR2_OWS_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR2_OWS_MASK) #define WAKEUP_ATU_ACORE_OWBAR2_WBA_MASK (0xFFF0000U) #define WAKEUP_ATU_ACORE_OWBAR2_WBA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OWBAR2_WBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR2_WBA_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR2_WBA_MASK) #define WAKEUP_ATU_ACORE_OWBAR2_DOMAIN_ID_MASK (0xF0000000U) #define WAKEUP_ATU_ACORE_OWBAR2_DOMAIN_ID_SHIFT (28U) /*! DOMAIN_ID - Domain identifier */ #define WAKEUP_ATU_ACORE_OWBAR2_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR2_DOMAIN_ID_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR2_DOMAIN_ID_MASK) /*! @} */ /*! @name ACORE_OWAR3 - Outbound Window Attributes Register 3 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWAR3_EN_MASK (0x80000000U) #define WAKEUP_ATU_ACORE_OWAR3_EN_SHIFT (31U) /*! EN * 0b0..Disable outbound translation window * 0b1..Enable outbound translation window */ #define WAKEUP_ATU_ACORE_OWAR3_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWAR3_EN_SHIFT)) & WAKEUP_ATU_ACORE_OWAR3_EN_MASK) /*! @} */ /*! @name ACORE_OTEAR2 - Outbound Translated Extended Address Register 2 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR2_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR2_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR2_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR2_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR2_TEA_MASK) /*! @} */ /*! @name ACORE_OTAR2 - Outbound Translated Address Register 2 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTAR2_TA_MASK (0xFFFF0000U) #define WAKEUP_ATU_ACORE_OTAR2_TA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OTAR2_TA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTAR2_TA_SHIFT)) & WAKEUP_ATU_ACORE_OTAR2_TA_MASK) /*! @} */ /*! @name ACORE_OWBAR3 - Outbound Window Base Address Register 3 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWBAR3_OWS_MASK (0x1FU) #define WAKEUP_ATU_ACORE_OWBAR3_OWS_SHIFT (0U) /*! OWS - Outbound Window Size */ #define WAKEUP_ATU_ACORE_OWBAR3_OWS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR3_OWS_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR3_OWS_MASK) #define WAKEUP_ATU_ACORE_OWBAR3_WBA_MASK (0xFFF0000U) #define WAKEUP_ATU_ACORE_OWBAR3_WBA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OWBAR3_WBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR3_WBA_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR3_WBA_MASK) #define WAKEUP_ATU_ACORE_OWBAR3_DOMAIN_ID_MASK (0xF0000000U) #define WAKEUP_ATU_ACORE_OWBAR3_DOMAIN_ID_SHIFT (28U) /*! DOMAIN_ID - Domain identifier */ #define WAKEUP_ATU_ACORE_OWBAR3_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR3_DOMAIN_ID_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR3_DOMAIN_ID_MASK) /*! @} */ /*! @name ACORE_OWAR4 - Outbound Window Attributes Register 4 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWAR4_EN_MASK (0x80000000U) #define WAKEUP_ATU_ACORE_OWAR4_EN_SHIFT (31U) /*! EN * 0b0..Disable outbound translation window * 0b1..Enable outbound translation window */ #define WAKEUP_ATU_ACORE_OWAR4_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWAR4_EN_SHIFT)) & WAKEUP_ATU_ACORE_OWAR4_EN_MASK) /*! @} */ /*! @name ACORE_OTEAR3 - Outbound Translated Extended Address Register 3 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR3_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR3_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR3_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR3_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR3_TEA_MASK) /*! @} */ /*! @name ACORE_OTAR3 - Outbound Translated Address Register 3 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTAR3_TA_MASK (0xFFFF0000U) #define WAKEUP_ATU_ACORE_OTAR3_TA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OTAR3_TA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTAR3_TA_SHIFT)) & WAKEUP_ATU_ACORE_OTAR3_TA_MASK) /*! @} */ /*! @name ACORE_OWBAR4 - Outbound Window Base Address Register 4 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWBAR4_OWS_MASK (0x1FU) #define WAKEUP_ATU_ACORE_OWBAR4_OWS_SHIFT (0U) /*! OWS - Outbound Window Size */ #define WAKEUP_ATU_ACORE_OWBAR4_OWS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR4_OWS_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR4_OWS_MASK) #define WAKEUP_ATU_ACORE_OWBAR4_WBA_MASK (0xFFF0000U) #define WAKEUP_ATU_ACORE_OWBAR4_WBA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OWBAR4_WBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR4_WBA_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR4_WBA_MASK) #define WAKEUP_ATU_ACORE_OWBAR4_DOMAIN_ID_MASK (0xF0000000U) #define WAKEUP_ATU_ACORE_OWBAR4_DOMAIN_ID_SHIFT (28U) /*! DOMAIN_ID - Domain identifier */ #define WAKEUP_ATU_ACORE_OWBAR4_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR4_DOMAIN_ID_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR4_DOMAIN_ID_MASK) /*! @} */ /*! @name ACORE_OWAR5 - Outbound Window Attributes Register 5 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWAR5_EN_MASK (0x80000000U) #define WAKEUP_ATU_ACORE_OWAR5_EN_SHIFT (31U) /*! EN * 0b0..Disable outbound translation window * 0b1..Enable outbound translation window */ #define WAKEUP_ATU_ACORE_OWAR5_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWAR5_EN_SHIFT)) & WAKEUP_ATU_ACORE_OWAR5_EN_MASK) /*! @} */ /*! @name ACORE_OTEAR4 - Outbound Translated Extended Address Register 4 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR4_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR4_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR4_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR4_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR4_TEA_MASK) /*! @} */ /*! @name ACORE_OTAR4 - Outbound Translated Address Register 4 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTAR4_TA_MASK (0xFFFF0000U) #define WAKEUP_ATU_ACORE_OTAR4_TA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OTAR4_TA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTAR4_TA_SHIFT)) & WAKEUP_ATU_ACORE_OTAR4_TA_MASK) /*! @} */ /*! @name ACORE_OWBAR5 - Outbound Window Base Address Register 5 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWBAR5_OWS_MASK (0x1FU) #define WAKEUP_ATU_ACORE_OWBAR5_OWS_SHIFT (0U) /*! OWS - Outbound Window Size */ #define WAKEUP_ATU_ACORE_OWBAR5_OWS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR5_OWS_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR5_OWS_MASK) #define WAKEUP_ATU_ACORE_OWBAR5_WBA_MASK (0xFFF0000U) #define WAKEUP_ATU_ACORE_OWBAR5_WBA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OWBAR5_WBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR5_WBA_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR5_WBA_MASK) #define WAKEUP_ATU_ACORE_OWBAR5_DOMAIN_ID_MASK (0xF0000000U) #define WAKEUP_ATU_ACORE_OWBAR5_DOMAIN_ID_SHIFT (28U) /*! DOMAIN_ID - Domain identifier */ #define WAKEUP_ATU_ACORE_OWBAR5_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR5_DOMAIN_ID_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR5_DOMAIN_ID_MASK) /*! @} */ /*! @name ACORE_OWAR6 - Outbound Window Attributes Register 6 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWAR6_EN_MASK (0x80000000U) #define WAKEUP_ATU_ACORE_OWAR6_EN_SHIFT (31U) /*! EN * 0b0..Disable outbound translation window * 0b1..Enable outbound translation window */ #define WAKEUP_ATU_ACORE_OWAR6_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWAR6_EN_SHIFT)) & WAKEUP_ATU_ACORE_OWAR6_EN_MASK) /*! @} */ /*! @name ACORE_OTEAR5 - Outbound Translated Extended Address Register 5 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR5_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR5_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR5_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR5_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR5_TEA_MASK) /*! @} */ /*! @name ACORE_OTAR5 - Outbound Translated Address Register 5 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTAR5_TA_MASK (0xFFFF0000U) #define WAKEUP_ATU_ACORE_OTAR5_TA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OTAR5_TA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTAR5_TA_SHIFT)) & WAKEUP_ATU_ACORE_OTAR5_TA_MASK) /*! @} */ /*! @name ACORE_OWBAR6 - Outbound Window Base Address Register 6 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWBAR6_OWS_MASK (0x1FU) #define WAKEUP_ATU_ACORE_OWBAR6_OWS_SHIFT (0U) /*! OWS - Outbound Window Size */ #define WAKEUP_ATU_ACORE_OWBAR6_OWS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR6_OWS_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR6_OWS_MASK) #define WAKEUP_ATU_ACORE_OWBAR6_WBA_MASK (0xFFF0000U) #define WAKEUP_ATU_ACORE_OWBAR6_WBA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OWBAR6_WBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR6_WBA_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR6_WBA_MASK) #define WAKEUP_ATU_ACORE_OWBAR6_DOMAIN_ID_MASK (0xF0000000U) #define WAKEUP_ATU_ACORE_OWBAR6_DOMAIN_ID_SHIFT (28U) /*! DOMAIN_ID - Domain identifier */ #define WAKEUP_ATU_ACORE_OWBAR6_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR6_DOMAIN_ID_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR6_DOMAIN_ID_MASK) /*! @} */ /*! @name ACORE_OWAR7 - Outbound Window Attributes Register 7 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWAR7_EN_MASK (0x80000000U) #define WAKEUP_ATU_ACORE_OWAR7_EN_SHIFT (31U) /*! EN * 0b0..Disable outbound translation window * 0b1..Enable outbound translation window */ #define WAKEUP_ATU_ACORE_OWAR7_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWAR7_EN_SHIFT)) & WAKEUP_ATU_ACORE_OWAR7_EN_MASK) /*! @} */ /*! @name ACORE_OTEAR6 - Outbound Translated Extended Address Register 6 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR6_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR6_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR6_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR6_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR6_TEA_MASK) /*! @} */ /*! @name ACORE_OTAR6 - Outbound Translated Address Register 6 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTAR6_TA_MASK (0xFFFF0000U) #define WAKEUP_ATU_ACORE_OTAR6_TA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OTAR6_TA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTAR6_TA_SHIFT)) & WAKEUP_ATU_ACORE_OTAR6_TA_MASK) /*! @} */ /*! @name ACORE_OWBAR7 - Outbound Window Base Address Register 7 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OWBAR7_OWS_MASK (0x1FU) #define WAKEUP_ATU_ACORE_OWBAR7_OWS_SHIFT (0U) /*! OWS - Outbound Window Size */ #define WAKEUP_ATU_ACORE_OWBAR7_OWS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR7_OWS_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR7_OWS_MASK) #define WAKEUP_ATU_ACORE_OWBAR7_WBA_MASK (0xFFF0000U) #define WAKEUP_ATU_ACORE_OWBAR7_WBA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OWBAR7_WBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR7_WBA_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR7_WBA_MASK) #define WAKEUP_ATU_ACORE_OWBAR7_DOMAIN_ID_MASK (0xF0000000U) #define WAKEUP_ATU_ACORE_OWBAR7_DOMAIN_ID_SHIFT (28U) /*! DOMAIN_ID - Domain identifier */ #define WAKEUP_ATU_ACORE_OWBAR7_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OWBAR7_DOMAIN_ID_SHIFT)) & WAKEUP_ATU_ACORE_OWBAR7_DOMAIN_ID_MASK) /*! @} */ /*! @name ACORE_OTEAR7 - Outbound Translated Extended Address Register 7 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTEAR7_TEA_MASK (0xFFFFFFFFU) #define WAKEUP_ATU_ACORE_OTEAR7_TEA_SHIFT (0U) #define WAKEUP_ATU_ACORE_OTEAR7_TEA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTEAR7_TEA_SHIFT)) & WAKEUP_ATU_ACORE_OTEAR7_TEA_MASK) /*! @} */ /*! @name ACORE_OTAR7 - Outbound Translated Address Register 7 */ /*! @{ */ #define WAKEUP_ATU_ACORE_OTAR7_TA_MASK (0xFFFF0000U) #define WAKEUP_ATU_ACORE_OTAR7_TA_SHIFT (16U) #define WAKEUP_ATU_ACORE_OTAR7_TA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ATU_ACORE_OTAR7_TA_SHIFT)) & WAKEUP_ATU_ACORE_OTAR7_TA_MASK) /*! @} */ /*! * @} */ /* end of group WAKEUP_ATU_Register_Masks */ /* WAKEUP_ATU - Peripheral instance base addresses */ /** Peripheral WAKEUP__ATUA base address */ #define WAKEUP__ATUA_BASE (0x42760000u) /** Peripheral WAKEUP__ATUA base pointer */ #define WAKEUP__ATUA ((WAKEUP_ATU_Type *)WAKEUP__ATUA_BASE) /** Peripheral WAKEUP__ATUM base address */ #define WAKEUP__ATUM_BASE (0x42770000u) /** Peripheral WAKEUP__ATUM base pointer */ #define WAKEUP__ATUM ((WAKEUP_ATU_Type *)WAKEUP__ATUM_BASE) /** Array initializer of WAKEUP_ATU peripheral base addresses */ #define WAKEUP_ATU_BASE_ADDRS { WAKEUP__ATUA_BASE, WAKEUP__ATUM_BASE } /** Array initializer of WAKEUP_ATU peripheral base pointers */ #define WAKEUP_ATU_BASE_PTRS { WAKEUP__ATUA, WAKEUP__ATUM } /*! * @} */ /* end of group WAKEUP_ATU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_AUDIO_XCVR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_AUDIO_XCVR_Peripheral_Access_Layer WAKEUP_AUDIO_XCVR Peripheral Access Layer * @{ */ /** WAKEUP_AUDIO_XCVR - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[2048]; __IO uint32_t VERSION; /**< Version control register, offset: 0x800 */ uint8_t RESERVED_1[12]; struct { /* offset: 0x810 */ __IO uint32_t RW; /**< External control register, offset: 0x810 */ __IO uint32_t SET; /**< External control register, offset: 0x814 */ __IO uint32_t CLR; /**< External control register, offset: 0x818 */ __IO uint32_t TOG; /**< External control register, offset: 0x81C */ } EXT_CTRL; struct { /* offset: 0x820 */ __IO uint32_t RW; /**< External Status register, offset: 0x820 */ __IO uint32_t SET; /**< External Status register, offset: 0x824 */ __IO uint32_t CLR; /**< External Status register, offset: 0x828 */ __IO uint32_t TOG; /**< External Status register, offset: 0x82C */ } EXT_STATUS; struct { /* offset: 0x830 */ __IO uint32_t RW; /**< Interrupt enables for interrupt 0, offset: 0x830 */ __IO uint32_t SET; /**< Interrupt enables for interrupt 0, offset: 0x834 */ __IO uint32_t CLR; /**< Interrupt enables for interrupt 0, offset: 0x838 */ __IO uint32_t TOG; /**< Interrupt enables for interrupt 0, offset: 0x83C */ } EXT_IER0; struct { /* offset: 0x840 */ __IO uint32_t RW; /**< Interrupt enables for interrupt 1, offset: 0x840 */ __IO uint32_t SET; /**< Interrupt enables for interrupt 1, offset: 0x844 */ __IO uint32_t CLR; /**< Interrupt enables for interrupt 1, offset: 0x848 */ __IO uint32_t TOG; /**< Interrupt enables for interrupt 1, offset: 0x84C */ } EXT_IER1; struct { /* offset: 0x850 */ __IO uint32_t RW; /**< External Interrupt Status register, offset: 0x850 */ __IO uint32_t SET; /**< External Interrupt Status register, offset: 0x854 */ __IO uint32_t CLR; /**< External Interrupt Status register, offset: 0x858 */ __IO uint32_t TOG; /**< External Interrupt Status register, offset: 0x85C */ } EXT_ISR; uint8_t RESERVED_2[16]; struct { /* offset: 0x870 */ __IO uint32_t RW; /**< Interrupt enable register for M0++, offset: 0x870 */ __IO uint32_t SET; /**< Interrupt enable register for M0++, offset: 0x874 */ __IO uint32_t CLR; /**< Interrupt enable register for M0++, offset: 0x878 */ __IO uint32_t TOG; /**< Interrupt enable register for M0++, offset: 0x87C */ } IER; struct { /* offset: 0x880 */ __IO uint32_t RW; /**< Interrupt status register, offset: 0x880 */ __IO uint32_t SET; /**< Interrupt status register, offset: 0x884 */ __IO uint32_t CLR; /**< Interrupt status register, offset: 0x888 */ __IO uint32_t TOG; /**< Interrupt status register, offset: 0x88C */ } ISR; struct { /* offset: 0x890 */ __IO uint32_t RW; /**< AI interface control register, offset: 0x890 */ __IO uint32_t SET; /**< AI interface control register, offset: 0x894 */ __IO uint32_t CLR; /**< AI interface control register, offset: 0x898 */ __IO uint32_t TOG; /**< AI interface control register, offset: 0x89C */ } PHY_AI_CTRL; __IO uint32_t PHY_AI_WDATA; /**< AI interface WDATA register, offset: 0x8A0 */ __I uint32_t PHY_AI_RDATA; /**< AI interface RDATA register, offset: 0x8A4 */ __I uint32_t DPATH_STATUS; /**< AUDIO XCVR datapath status, offset: 0x8A8 */ uint8_t RESERVED_3[20]; struct { /* offset: 0x8C0 */ __IO uint32_t RW; /**< CMDC receiver control register, offset: 0x8C0 */ __IO uint32_t SET; /**< CMDC receiver control register, offset: 0x8C4 */ __IO uint32_t CLR; /**< CMDC receiver control register, offset: 0x8C8 */ __IO uint32_t TOG; /**< CMDC receiver control register, offset: 0x8CC */ } RX_CMDC_CTRL; __I uint32_t RX_CMDC_STATUS; /**< AUDIO_XCVR CMDC status, offset: 0x8D0 */ uint8_t RESERVED_4[12]; __IO uint32_t RX_CMDC_TX_DATA; /**< CMDC transmit data register, offset: 0x8E0 */ uint8_t RESERVED_5[12]; __IO uint32_t RX_CMDC_RX_DATA; /**< CMDC receive data register, offset: 0x8F0 */ uint8_t RESERVED_6[140]; struct { /* offset: 0x980 */ __IO uint32_t RW; /**< Data path control register, offset: 0x980 */ __IO uint32_t SET; /**< Data path control register, offset: 0x984 */ __IO uint32_t CLR; /**< Data path control register, offset: 0x988 */ __IO uint32_t TOG; /**< Data path control register, offset: 0x98C */ } RX_DATAPATH_CTRL; __I uint32_t RX_CS_DATA_BITS[6]; /**< Channel status bits, array offset: 0x990, array step: 0x4 */ __I uint32_t RX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0x9A8, array step: 0x4 */ struct { /* offset: 0x9C0 */ __IO uint32_t RW; /**< DMAC counter control register, offset: 0x9C0 */ __IO uint32_t SET; /**< DMAC counter control register, offset: 0x9C4 */ __IO uint32_t CLR; /**< DMAC counter control register, offset: 0x9C8 */ __IO uint32_t TOG; /**< DMAC counter control register, offset: 0x9CC */ } RX_DPATH_CNTR_CTRL; __I uint32_t RX_DPATH_TSCR; /**< Receive Datapath Timestamp Counter Register, offset: 0x9D0 */ __I uint32_t RX_DPATH_BCR; /**< Receive Datapath Bit counter register, offset: 0x9D4 */ __I uint32_t RX_DPATH_BCTR; /**< Receive datapath Bit count timestamp register., offset: 0x9D8 */ __I uint32_t RX_DPATH_BCRR; /**< Receive datapath Bit read timestamp register., offset: 0x9DC */ struct { /* offset: 0x9E0 */ __IO uint32_t RW; /**< Preamble match value register, offset: 0x9E0 */ __IO uint32_t SET; /**< Preamble match value register, offset: 0x9E4 */ __IO uint32_t CLR; /**< Preamble match value register, offset: 0x9E8 */ __IO uint32_t TOG; /**< Preamble match value register, offset: 0x9EC */ } DMAC_PRE_MATCH_VAL; struct { /* offset: 0x9F0 */ __IO uint32_t RW; /**< Preamble match value register, offset: 0x9F0 */ __IO uint32_t SET; /**< Preamble match value register, offset: 0x9F4 */ __IO uint32_t CLR; /**< Preamble match value register, offset: 0x9F8 */ __IO uint32_t TOG; /**< Preamble match value register, offset: 0x9FC */ } DMAC_DTS_PRE_MATCH_VAL; __IO uint32_t RX_DPATH_PRE_ERR; /**< Error count for IEC60958-1 Block Synchronization., offset: 0xA00 */ __IO uint32_t RX_DPATH_PARITY_ERR; /**< Parity Error count for IEC60958-1 Blocks., offset: 0xA04 */ uint8_t RESERVED_7[8]; __I uint32_t RX_DPATH_PKT_CNT; /**< Receive Data packet count., offset: 0xA10 */ __I uint32_t RX_DPATH_ONE_BIT_ERR_CNT; /**< Receive Data packet Corrected error count., offset: 0xA14 */ __I uint32_t DMAC_PRE_MATCH_OFFSET; /**< Preamble match offset value register, offset: 0xA18 */ uint8_t RESERVED_8[4]; struct { /* offset: 0xA20 */ __IO uint32_t RW; /**< Transmit Data path control register, offset: 0xA20 */ __IO uint32_t SET; /**< Transmit Data path control register, offset: 0xA24 */ __IO uint32_t CLR; /**< Transmit Data path control register, offset: 0xA28 */ __IO uint32_t TOG; /**< Transmit Data path control register, offset: 0xA2C */ } TX_DATAPATH_CTRL; __IO uint32_t TX_CS_DATA_BITS[6]; /**< Channel status bits, array offset: 0xA30, array step: 0x4 */ __IO uint32_t TX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0xA48, array step: 0x4 */ struct { /* offset: 0xA60 */ __IO uint32_t RW; /**< DMAC counter control register, offset: 0xA60 */ __IO uint32_t SET; /**< DMAC counter control register, offset: 0xA64 */ __IO uint32_t CLR; /**< DMAC counter control register, offset: 0xA68 */ __IO uint32_t TOG; /**< DMAC counter control register, offset: 0xA6C */ } TX_DPATH_CNTR_CTRL; __I uint32_t TX_DPATH_TSCR; /**< Transmit Datapath Timestamp Counter Register, offset: 0xA70 */ __I uint32_t TX_DPATH_BCR; /**< Transmit Datapath Bit counter register, offset: 0xA74 */ __I uint32_t TX_DPATH_BCTR; /**< Transmit datapath Bit count timestamp register., offset: 0xA78 */ __I uint32_t TX_DPATH_BCRR; /**< Transmit datapath Bit read timestamp register., offset: 0xA7C */ uint8_t RESERVED_9[32]; struct { /* offset: 0xAA0 */ __IO uint32_t RW; /**< HPD Debounce Control Register, offset: 0xAA0 */ __IO uint32_t SET; /**< HPD Debounce Control Register, offset: 0xAA4 */ __IO uint32_t CLR; /**< HPD Debounce Control Register, offset: 0xAA8 */ __IO uint32_t TOG; /**< HPD Debounce Control Register, offset: 0xAAC */ } HPD_DBNC_CTRL; } WAKEUP_AUDIO_XCVR_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_AUDIO_XCVR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_AUDIO_XCVR_Register_Masks WAKEUP_AUDIO_XCVR Register Masks * @{ */ /*! @name VERSION - Version control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_VERSION_VERID_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_VERSION_VERID_SHIFT (0U) /*! VERID - Version ID */ #define WAKEUP_AUDIO_XCVR_VERSION_VERID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_VERSION_VERID_SHIFT)) & WAKEUP_AUDIO_XCVR_VERSION_VERID_MASK) /*! @} */ /*! @name EXT_CTRL - External control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_FIFO_WMARK_MASK (0x7FU) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_FIFO_WMARK_SHIFT (0U) /*! TX_FIFO_WMARK - Audio Transmit FIFO Watermark Level */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_FIFO_WMARK_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_FIFO_WMARK_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_FIFO_WMARK_MASK (0x7F00U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_FIFO_WMARK_SHIFT (8U) /*! RX_FIFO_WMARK - Audio Receive FIFO Watermark Level */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_FIFO_WMARK_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_FIFO_WMARK_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_FABRIC_RR_SEL_MASK (0x8000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_FABRIC_RR_SEL_SHIFT (15U) /*! FABRIC_RR_SEL - Selects Arbitration mode of crossbar switch. */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_FABRIC_RR_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_FABRIC_RR_SEL_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_FABRIC_RR_SEL_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_PAGE_MASK (0xF0000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_PAGE_SHIFT (16U) /*! PAGE - Page Select. */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_PAGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_PAGE_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_PAGE_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_MASK (0x200000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_SHIFT (21U) /*! CORE_SLEEP_HOLD_REQ_B - Hold core from going to sleep mode when 0. */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_WAIT_MASK (0x400000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_WAIT_SHIFT (22U) /*! CORE_WAIT - Stop executing code */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_WAIT_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_WAIT_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SPDIF_MODE_MASK (0x800000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SPDIF_MODE_SHIFT (23U) /*! SPDIF_MODE - Indicates SPDIF output mode. */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SPDIF_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_SPDIF_MODE_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_SPDIF_MODE_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_WR_REQ_DIS_MASK (0x1000000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT (24U) /*! SDMA_WR_REQ_DIS - SDMA WR REQ disable */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_WR_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_WR_REQ_DIS_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_RD_REQ_DIS_MASK (0x2000000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT (25U) /*! SDMA_RD_REQ_DIS - SDMA RD REQ disable */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_RD_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_SDMA_RD_REQ_DIS_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_DPATH_RESET_MASK (0x8000000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_DPATH_RESET_SHIFT (27U) /*! TX_DPATH_RESET - Soft reset to the Datapath for Transmit */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_DPATH_RESET_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_DPATH_RESET_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_DPATH_RESET_MASK (0x10000000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_DPATH_RESET_SHIFT (28U) /*! RX_DPATH_RESET - Soft reset to the AUDIO_XCVR Differential data Receiver */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_DPATH_RESET_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_DPATH_RESET_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_CMDC_RESET_MASK (0x20000000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_CMDC_RESET_SHIFT (29U) /*! TX_CMDC_RESET - Soft reset to the AUDIO_XCVR Common mode Transmitter */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_CMDC_RESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_CMDC_RESET_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_TX_CMDC_RESET_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_CMDC_RESET_MASK (0x40000000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_CMDC_RESET_SHIFT (30U) /*! RX_CMDC_RESET - Soft reset to the AUDIO_XCVR Common mode Receiver */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_CMDC_RESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_CMDC_RESET_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_RX_CMDC_RESET_MASK) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_RESET_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_RESET_SHIFT (31U) /*! CORE_RESET - M0+ Reset */ #define WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_RESET_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_CTRL_CORE_RESET_MASK) /*! @} */ /*! @name EXT_STATUS - External Status register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK (0xFFU) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT (0U) /*! NO_TX_FIFO_ENTRIES - TX FIFO entries */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_TX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK (0xFF00U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT (8U) /*! NO_RX_FIFO_ENTRIES - RX FIFO entries */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_RX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEPING_MASK (0x10000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEPING_SHIFT (16U) /*! CM0_SLEEPING - CM0 is in Sleep mode. */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEPING_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEPING_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_DEEP_SLEEP_MASK (0x20000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_DEEP_SLEEP_SHIFT (17U) /*! CM0_DEEP_SLEEP - CM0 is in deep sleep mode. */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_DEEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_DEEP_SLEEP_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_DEEP_SLEEP_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_MASK (0x40000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_SHIFT (18U) /*! CM0_SLEEP_HOLD_ACK_B - Sleep extension acknowledge. */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_TX_PIPE_EMPTY_MASK (0x200000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_TX_PIPE_EMPTY_SHIFT (21U) /*! TX_PIPE_EMPTY - Indicates TX pipe status. */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_TX_PIPE_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_TX_PIPE_EMPTY_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_TX_PIPE_EMPTY_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_RESP_TO_MASK (0x800000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_RESP_TO_SHIFT (23U) /*! RX_CMDC_RESP_TO - CMDC Response not sent in programmed time */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_RESP_TO(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_RESP_TO_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_RESP_TO_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_COMMA_TO_MASK (0x2000000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_COMMA_TO_SHIFT (25U) /*! RX_CMDC_COMMA_TO - Receiver CMDC comma timeout Interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_COMMA_TO(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_COMMA_TO_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_RX_CMDC_COMMA_TO_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_HEARTBEAT_STATUS_MASK (0x8000000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_HEARTBEAT_STATUS_SHIFT (27U) /*! HEARTBEAT_STATUS - AUDIO_XCVR Connection Status */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_HEARTBEAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_HEARTBEAT_STATUS_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_HEARTBEAT_STATUS_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD4_REC_MASK (0x10000000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD4_REC_SHIFT (28U) /*! NEW_UD4_REC - New user data */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD4_REC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD4_REC_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD4_REC_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD5_REC_MASK (0x20000000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD5_REC_SHIFT (29U) /*! NEW_UD5_REC - New user data */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD5_REC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD5_REC_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD5_REC_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD6_REC_MASK (0x40000000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD6_REC_SHIFT (30U) /*! NEW_UD6_REC - New user data */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD6_REC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD6_REC_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_NEW_UD6_REC_MASK) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_HPD_I_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_EXT_STATUS_HPD_I_SHIFT (31U) /*! HPD_I - HPD Input status */ #define WAKEUP_AUDIO_XCVR_EXT_STATUS_HPD_I(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_STATUS_HPD_I_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_STATUS_HPD_I_MASK) /*! @} */ /*! @name EXT_IER0 - Interrupt enables for interrupt 0 */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_CS_IE_0_MASK (0x1U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_CS_IE_0_SHIFT (0U) /*! NEW_CS_IE_0 - Enable for New channel status block received interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_CS_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_CS_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_CS_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_UD_IE_0_MASK (0x2U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_UD_IE_0_SHIFT (1U) /*! NEW_UD_IE_0 - Enable for new user data received interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_UD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_UD_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_UD_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_MUTE_IE_0_MASK (0x4U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_MUTE_IE_0_SHIFT (2U) /*! MUTE_IE_0 - Enable for Mute detected interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_MUTE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_MUTE_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_MUTE_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_RESP_TO_IE_0_MASK (0x8U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_RESP_TO_IE_0_SHIFT (3U) /*! CMDC_RESP_TO_IE_0 - Receiver CMDC data response timeout interrupt enable */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_RESP_TO_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_RESP_TO_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_RESP_TO_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_ECC_ERR_IE_0_MASK (0x10U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_ECC_ERR_IE_0_SHIFT (4U) /*! ECC_ERR_IE_0 - 60958 Compressed data uncorrectable error interrupt enable */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_ECC_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_ECC_ERR_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_ECC_ERR_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK (0x20U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT (5U) /*! PREAMBLE_MISMATCH_IE_0 - Preamble mismatch interrupt enable. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK (0x40U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT (6U) /*! FIFO_OFLOW_UFLOW_ERR_IE_0 - Receive FIFO overflow error interrupt enable. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_OHPD_IE_0_MASK (0x100U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_OHPD_IE_0_SHIFT (8U) /*! OHPD_IE_0 - Output HPD interrupt enable. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_OHPD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_OHPD_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_OHPD_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_NO_DATA_REC_IE_0_MASK (0x200U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_NO_DATA_REC_IE_0_SHIFT (9U) /*! DMAC_NO_DATA_REC_IE_0 - Indicates no DMAC data is received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_NO_DATA_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_NO_DATA_REC_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_NO_DATA_REC_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_MASK (0x400U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_SHIFT (10U) /*! DMAC_FMT_CHG_DET_IE_0 - Indicates DMAC format change was detected */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_FMT_CHG_DET_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_HB_STATE_CHG_IE_0_MASK (0x800U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_HB_STATE_CHG_IE_0_SHIFT (11U) /*! HB_STATE_CHG_IE_0 - Interrupt enable for Heartbeat status change */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_HB_STATE_CHG_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_HB_STATE_CHG_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_HB_STATE_CHG_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_MASK (0x1000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_SHIFT (12U) /*! CMDC_STATUS_UPDATE_IE_0 - Interrupt enable for CMDC status register update. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_STATUS_UPDATE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_TEMP_UPDATE_IE_0_MASK (0x2000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_TEMP_UPDATE_IE_0_SHIFT (13U) /*! TEMP_UPDATE_IE_0 - Update request for chip temperature value. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_TEMP_UPDATE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_TEMP_UPDATE_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_TEMP_UPDATE_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_RD_REQ_IE_0_MASK (0x4000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT (14U) /*! DMA_RD_REQ_IE_0 - Request to read data from FIFO. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_RD_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_RD_REQ_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_WR_REQ_IE_0_MASK (0x8000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT (15U) /*! DMA_WR_REQ_IE_0 - Request to write data to FIFO. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_WR_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_DMA_WR_REQ_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_RX_BME_ERR_IE_0_MASK (0x10000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_RX_BME_ERR_IE_0_SHIFT (16U) /*! DMAC_RX_BME_ERR_IE_0 - Bi-phase mark encoding error */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_RX_BME_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_RX_BME_ERR_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_DMAC_RX_BME_ERR_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK (0x20000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT (17U) /*! PREAMBLE_MATCH_IE_0 - Interrupt enable for preamble match received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK (0x40000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT (18U) /*! M_W_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame M/W preamble mismatch received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_M_W_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK (0x80000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT (19U) /*! B_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame B preamble mismatch received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_B_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK (0x100000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT (20U) /*! UNEXP_PRE_REC_IE_0 - Interrupt enable for unexpected preamble received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_UNEXP_PRE_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_CH_UD_OFLOW_IE_0_MASK (0x400000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_CH_UD_OFLOW_IE_0_SHIFT (22U) /*! CH_UD_OFLOW_IE_0 - Channel status or used data could not be stored. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_CH_UD_OFLOW_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_CH_UD_OFLOW_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_CH_UD_OFLOW_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_BLK_RCVD_IE_0_MASK (0x800000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_BLK_RCVD_IE_0_SHIFT (23U) /*! NEW_BLK_RCVD_IE_0 - New block of data was received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_BLK_RCVD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_BLK_RCVD_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_NEW_BLK_RCVD_IE_0_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER0_SPARE_IE_0_MASK (0xFF000000U) #define WAKEUP_AUDIO_XCVR_EXT_IER0_SPARE_IE_0_SHIFT (24U) /*! SPARE_IE_0 - Spare interrupts */ #define WAKEUP_AUDIO_XCVR_EXT_IER0_SPARE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER0_SPARE_IE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER0_SPARE_IE_0_MASK) /*! @} */ /*! @name EXT_IER1 - Interrupt enables for interrupt 1 */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_CS_IE_1_MASK (0x1U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_CS_IE_1_SHIFT (0U) /*! NEW_CS_IE_1 - Enable for New channel status block received interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_CS_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_CS_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_CS_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_UD_IE_1_MASK (0x2U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_UD_IE_1_SHIFT (1U) /*! NEW_UD_IE_1 - Enable for new user data received interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_UD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_UD_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_UD_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_MUTE_IE_1_MASK (0x4U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_MUTE_IE_1_SHIFT (2U) /*! MUTE_IE_1 - Enable for Mute detected interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_MUTE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_MUTE_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_MUTE_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_RESP_TO_IE_1_MASK (0x8U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_RESP_TO_IE_1_SHIFT (3U) /*! CMDC_RESP_TO_IE_1 - Receiver CMDC data response timeout interrupt enable */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_RESP_TO_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_RESP_TO_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_RESP_TO_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_ECC_ERR_IE_1_MASK (0x10U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_ECC_ERR_IE_1_SHIFT (4U) /*! ECC_ERR_IE_1 - 60958 Compressed data uncorrectable error interrupt enable */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_ECC_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_ECC_ERR_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_ECC_ERR_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK (0x20U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT (5U) /*! PREAMBLE_MISMATCH_IE_1 - Preamble mismatch interrupt enable. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK (0x40U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT (6U) /*! FIFO_OFLOW_UFLOW_ERR_IE_1 - Receive FIFO overflow error interrupt enable. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_OHPD_IE_1_MASK (0x100U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_OHPD_IE_1_SHIFT (8U) /*! OHPD_IE_1 - Output HPD interrupt enable. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_OHPD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_OHPD_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_OHPD_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_NO_DATA_REC_IE_1_MASK (0x200U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_NO_DATA_REC_IE_1_SHIFT (9U) /*! DMAC_NO_DATA_REC_IE_1 - Indicates no DMAC data is received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_NO_DATA_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_NO_DATA_REC_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_NO_DATA_REC_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_MASK (0x400U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_SHIFT (10U) /*! DMAC_FMT_CHG_DET_IE_1 - Indicates DMAC format change was detected */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_FMT_CHG_DET_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_HB_STATE_CHG_IE_1_MASK (0x800U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_HB_STATE_CHG_IE_1_SHIFT (11U) /*! HB_STATE_CHG_IE_1 - Interrupt enable for Heartbeat status change */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_HB_STATE_CHG_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_HB_STATE_CHG_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_HB_STATE_CHG_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_MASK (0x1000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_SHIFT (12U) /*! CMDC_STATUS_UPDATE_IE_1 - Interrupt enable for CMDC status register update. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_STATUS_UPDATE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_TEMP_UPDATE_IE_1_MASK (0x2000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_TEMP_UPDATE_IE_1_SHIFT (13U) /*! TEMP_UPDATE_IE_1 - Update request for chip temperature value. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_TEMP_UPDATE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_TEMP_UPDATE_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_TEMP_UPDATE_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_RD_REQ_IE_1_MASK (0x4000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT (14U) /*! DMA_RD_REQ_IE_1 - Request to read data from FIFO. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_RD_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_RD_REQ_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_WR_REQ_IE_1_MASK (0x8000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT (15U) /*! DMA_WR_REQ_IE_1 - Request to write data to FIFO. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_WR_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_DMA_WR_REQ_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_RX_BME_ERR_IE_1_MASK (0x10000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_RX_BME_ERR_IE_1_SHIFT (16U) /*! DMAC_RX_BME_ERR_IE_1 - Bi-phase mark encoding error */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_RX_BME_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_RX_BME_ERR_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_DMAC_RX_BME_ERR_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK (0x20000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT (17U) /*! PREAMBLE_MATCH_IE_1 - Interrupt enable for preamble match received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK (0x40000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT (18U) /*! M_W_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame M/W preamble mismatch received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_M_W_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK (0x80000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT (19U) /*! B_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame B preamble mismatch received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_B_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK (0x100000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT (20U) /*! UNEXP_PRE_REC_IE_1 - Interrupt enable for Unexpected preamble received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_UNEXP_PRE_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_CH_UD_OFLOW_IE_1_MASK (0x400000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_CH_UD_OFLOW_IE_1_SHIFT (22U) /*! CH_UD_OFLOW_IE_1 - Channel status or used data could not be stored. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_CH_UD_OFLOW_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_CH_UD_OFLOW_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_CH_UD_OFLOW_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_BLK_RCVD_IE_1_MASK (0x800000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_BLK_RCVD_IE_1_SHIFT (23U) /*! NEW_BLK_RCVD_IE_1 - New block of data was received. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_BLK_RCVD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_BLK_RCVD_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_NEW_BLK_RCVD_IE_1_MASK) #define WAKEUP_AUDIO_XCVR_EXT_IER1_SPARE_IE_1_MASK (0xFF000000U) #define WAKEUP_AUDIO_XCVR_EXT_IER1_SPARE_IE_1_SHIFT (24U) /*! SPARE_IE_1 - Spare interrupt enables. */ #define WAKEUP_AUDIO_XCVR_EXT_IER1_SPARE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_IER1_SPARE_IE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_IER1_SPARE_IE_1_MASK) /*! @} */ /*! @name EXT_ISR - External Interrupt Status register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_CH_STAT_MASK (0x1U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_CH_STAT_SHIFT (0U) /*! RX_NEW_CH_STAT - Received new channel status block */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_CH_STAT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_CH_STAT_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_CH_STAT_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_USR_DATA_MASK (0x2U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_USR_DATA_SHIFT (1U) /*! RX_NEW_USR_DATA - Received new User data Information */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_USR_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_USR_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_RX_NEW_USR_DATA_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_MUTE_DET_MASK (0x4U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_MUTE_DET_SHIFT (2U) /*! MUTE_DET - Interrupt to indicate HW mute bit was detected. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_MUTE_DET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_MUTE_DET_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_MUTE_DET_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_RESP_TO_ERR_MASK (0x8U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_RESP_TO_ERR_SHIFT (3U) /*! CMDC_RESP_TO_ERR - CMDC response timeout interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_RESP_TO_ERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_RESP_TO_ERR_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_RESP_TO_ERR_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_ECC_ERR_MASK (0x10U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_ECC_ERR_SHIFT (4U) /*! ECC_ERR - 60958 Compressed data uncorrectable error interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_ECC_ERR_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_ECC_ERR_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MISMATCH_MASK (0x20U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MISMATCH_SHIFT (5U) /*! PREAMBLE_MISMATCH - Preamble mismatch interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MISMATCH_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MISMATCH_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK (0x40U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT (6U) /*! FIFO_OFLOW_UFLOW_ERR - Receive FIFO overflow error interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_FIFO_OFLOW_UFLOW_ERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_OHPD_MASK (0x100U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_OHPD_SHIFT (8U) /*! OHPD - HPD output driver */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_OHPD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_OHPD_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_OHPD_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMAC_NO_DATA_REC_MASK (0x200U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMAC_NO_DATA_REC_SHIFT (9U) /*! DMAC_NO_DATA_REC - No DMAC data is received for 1us. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMAC_NO_DATA_REC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_DMAC_NO_DATA_REC_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_DMAC_NO_DATA_REC_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_FMT_CHG_DET_MASK (0x400U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_FMT_CHG_DET_SHIFT (10U) /*! FMT_CHG_DET - Format change detect interrupt */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_FMT_CHG_DET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_FMT_CHG_DET_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_FMT_CHG_DET_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_HB_STATE_CHG_MASK (0x800U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_HB_STATE_CHG_SHIFT (11U) /*! HB_STATE_CHG - Interrupt enable for Heartbeat status change */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_HB_STATE_CHG(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_HB_STATE_CHG_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_HB_STATE_CHG_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_STATUS_UPDATE_MASK (0x1000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_STATUS_UPDATE_SHIFT (12U) /*! CMDC_STATUS_UPDATE - Interrupt enable for CMDC status register update. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_STATUS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_STATUS_UPDATE_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_CMDC_STATUS_UPDATE_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_TEMP_UPDATE_INT_MASK (0x2000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_TEMP_UPDATE_INT_SHIFT (13U) /*! TEMP_UPDATE_INT - Interrupt to get the new temperature value. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_TEMP_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_TEMP_UPDATE_INT_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_TEMP_UPDATE_INT_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_RD_REQ_MASK (0x4000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_RD_REQ_SHIFT (14U) /*! DMA_RD_REQ - Set when DMA read request is asserted. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_RD_REQ_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_RD_REQ_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_WR_REQ_MASK (0x8000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_WR_REQ_SHIFT (15U) /*! DMA_WR_REQ - Set when DMA write request is asserted. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_WR_REQ_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_DMA_WR_REQ_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_BME_BIT_ERR_MASK (0x10000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_BME_BIT_ERR_SHIFT (16U) /*! RX_BME_BIT_ERR - Set when DMAC BME data has an error. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_RX_BME_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_RX_BME_BIT_ERR_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_RX_BME_BIT_ERR_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MATCH_INT_MASK (0x20000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT (17U) /*! PREAMBLE_MATCH_INT - Interrupt to indicate PA PB / DTC CD preamble match was detected. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MATCH_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_PREAMBLE_MATCH_INT_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_M_W_PRE_MISMATCH_MASK (0x40000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_M_W_PRE_MISMATCH_SHIFT (18U) /*! M_W_PRE_MISMATCH - Set when DMAC preamble of M/W has an error. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_M_W_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_M_W_PRE_MISMATCH_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_M_W_PRE_MISMATCH_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_B_PRE_MISMATCH_MASK (0x80000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_B_PRE_MISMATCH_SHIFT (19U) /*! B_PRE_MISMATCH - Set when DMAC preamble of B has an error. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_B_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_B_PRE_MISMATCH_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_B_PRE_MISMATCH_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_UNEXP_PRE_REC_MASK (0x100000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_UNEXP_PRE_REC_SHIFT (20U) /*! UNEXP_PRE_REC - Set when DMAC preamble was received after unexpected number of input bits. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_UNEXP_PRE_REC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_UNEXP_PRE_REC_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_UNEXP_PRE_REC_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_CS_OR_UD_OFLOW_MASK (0x400000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_CS_OR_UD_OFLOW_SHIFT (22U) /*! CS_OR_UD_OFLOW - Channel status or used data could not be stored. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_CS_OR_UD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_CS_OR_UD_OFLOW_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_CS_OR_UD_OFLOW_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_NEW_BLK_RCVD_MASK (0x800000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_NEW_BLK_RCVD_SHIFT (23U) /*! NEW_BLK_RCVD - New block of data was received. */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_NEW_BLK_RCVD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_NEW_BLK_RCVD_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_NEW_BLK_RCVD_MASK) #define WAKEUP_AUDIO_XCVR_EXT_ISR_SPARE_INT_MASK (0xFF000000U) #define WAKEUP_AUDIO_XCVR_EXT_ISR_SPARE_INT_SHIFT (24U) /*! SPARE_INT - Extra interrupt. Currently not driven. Can be set by M0+ */ #define WAKEUP_AUDIO_XCVR_EXT_ISR_SPARE_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_EXT_ISR_SPARE_INT_SHIFT)) & WAKEUP_AUDIO_XCVR_EXT_ISR_SPARE_INT_MASK) /*! @} */ /*! @name IER - Interrupt enable register for M0++ */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_IER_HPD_TGL_IE_MASK (0x8000U) #define WAKEUP_AUDIO_XCVR_IER_HPD_TGL_IE_SHIFT (15U) /*! HPD_TGL_IE - HPD pin level change interrupt enable */ #define WAKEUP_AUDIO_XCVR_IER_HPD_TGL_IE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_IER_HPD_TGL_IE_SHIFT)) & WAKEUP_AUDIO_XCVR_IER_HPD_TGL_IE_MASK) #define WAKEUP_AUDIO_XCVR_IER_FMT_CHG_IE_MASK (0x40000U) #define WAKEUP_AUDIO_XCVR_IER_FMT_CHG_IE_SHIFT (18U) /*! FMT_CHG_IE - Format Change interrupt. */ #define WAKEUP_AUDIO_XCVR_IER_FMT_CHG_IE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_IER_FMT_CHG_IE_SHIFT)) & WAKEUP_AUDIO_XCVR_IER_FMT_CHG_IE_MASK) #define WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_RX_IE_MASK (0x100000U) #define WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_RX_IE_SHIFT (20U) /*! SET_SPDIF_RX_IE - Interrupt enable to set up SPDIF RX mode */ #define WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_RX_IE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_RX_IE_SHIFT)) & WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_RX_IE_MASK) #define WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_TX_IE_MASK (0x200000U) #define WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_TX_IE_SHIFT (21U) /*! SET_SPDIF_TX_IE - Interrupt enable to set up SPDIF TX mode */ #define WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_TX_IE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_TX_IE_SHIFT)) & WAKEUP_AUDIO_XCVR_IER_SET_SPDIF_TX_IE_MASK) #define WAKEUP_AUDIO_XCVR_IER_SW_HPD_TGL_IE_MASK (0x1000000U) #define WAKEUP_AUDIO_XCVR_IER_SW_HPD_TGL_IE_SHIFT (24U) /*! SW_HPD_TGL_IE - Interrupt enable to allow SW to assert HPD. */ #define WAKEUP_AUDIO_XCVR_IER_SW_HPD_TGL_IE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_IER_SW_HPD_TGL_IE_SHIFT)) & WAKEUP_AUDIO_XCVR_IER_SW_HPD_TGL_IE_MASK) /*! @} */ /*! @name ISR - Interrupt status register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_ISR_HPD_TGL_MASK (0x8000U) #define WAKEUP_AUDIO_XCVR_ISR_HPD_TGL_SHIFT (15U) /*! HPD_TGL - HPD pin level change interrupt */ #define WAKEUP_AUDIO_XCVR_ISR_HPD_TGL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_ISR_HPD_TGL_SHIFT)) & WAKEUP_AUDIO_XCVR_ISR_HPD_TGL_MASK) #define WAKEUP_AUDIO_XCVR_ISR_FMT_CHG_INT_MASK (0x40000U) #define WAKEUP_AUDIO_XCVR_ISR_FMT_CHG_INT_SHIFT (18U) /*! FMT_CHG_INT - Format Change interrupt. */ #define WAKEUP_AUDIO_XCVR_ISR_FMT_CHG_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_ISR_FMT_CHG_INT_SHIFT)) & WAKEUP_AUDIO_XCVR_ISR_FMT_CHG_INT_MASK) #define WAKEUP_AUDIO_XCVR_ISR_SET_SPDIF_RX_MODE_MASK (0x100000U) #define WAKEUP_AUDIO_XCVR_ISR_SET_SPDIF_RX_MODE_SHIFT (20U) /*! SET_SPDIF_RX_MODE - Interrupt to set up PHY and controller in SPDIF RX mode. */ #define WAKEUP_AUDIO_XCVR_ISR_SET_SPDIF_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_ISR_SET_SPDIF_RX_MODE_SHIFT)) & WAKEUP_AUDIO_XCVR_ISR_SET_SPDIF_RX_MODE_MASK) /*! @} */ /*! @name PHY_AI_CTRL - AI interface control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_ADDR_MASK (0xFFU) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_ADDR_SHIFT (0U) /*! AI_ADDR - AI ADDR value */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_ADDR_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_ADDR_MASK) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RESETN_MASK (0x8000U) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RESETN_SHIFT (15U) /*! AI_RESETN - AI reset bit */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RESETN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RESETN_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RESETN_MASK) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_0_MASK (0x1000000U) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_0_SHIFT (24U) /*! TOG_0 - AI toggle bit */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_0_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_0_MASK) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_0_MASK (0x2000000U) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_0_SHIFT (25U) /*! TOG_DONE_0 - AI toggle done bit */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_0_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_0_MASK) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_1_MASK (0x4000000U) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_1_SHIFT (26U) /*! TOG_1 - AI toggle bit */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_1_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_1_MASK) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_1_MASK (0x8000000U) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_1_SHIFT (27U) /*! TOG_DONE_1 - AI toggle done bit */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_1_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_TOG_DONE_1_MASK) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RWB_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RWB_SHIFT (31U) /*! AI_RWB - AI Read / write control bit */ #define WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RWB(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RWB_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_CTRL_AI_RWB_MASK) /*! @} */ /*! @name PHY_AI_WDATA - AI interface WDATA register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_PHY_AI_WDATA_WDATA_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_PHY_AI_WDATA_WDATA_SHIFT (0U) /*! WDATA - Write data */ #define WAKEUP_AUDIO_XCVR_PHY_AI_WDATA_WDATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_WDATA_WDATA_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_WDATA_WDATA_MASK) /*! @} */ /*! @name PHY_AI_RDATA - AI interface RDATA register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_PHY_AI_RDATA_RDATA_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_PHY_AI_RDATA_RDATA_SHIFT (0U) /*! RDATA - Read data */ #define WAKEUP_AUDIO_XCVR_PHY_AI_RDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_PHY_AI_RDATA_RDATA_SHIFT)) & WAKEUP_AUDIO_XCVR_PHY_AI_RDATA_RDATA_MASK) /*! @} */ /*! @name DPATH_STATUS - AUDIO XCVR datapath status */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_DPATH_STATUS_RX_FRM_CNT_MASK (0xFFU) #define WAKEUP_AUDIO_XCVR_DPATH_STATUS_RX_FRM_CNT_SHIFT (0U) /*! RX_FRM_CNT - Count of received frames in a block */ #define WAKEUP_AUDIO_XCVR_DPATH_STATUS_RX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_DPATH_STATUS_RX_FRM_CNT_SHIFT)) & WAKEUP_AUDIO_XCVR_DPATH_STATUS_RX_FRM_CNT_MASK) #define WAKEUP_AUDIO_XCVR_DPATH_STATUS_TX_FRM_CNT_MASK (0xFF00U) #define WAKEUP_AUDIO_XCVR_DPATH_STATUS_TX_FRM_CNT_SHIFT (8U) /*! TX_FRM_CNT - Count of transmitted frames in a block */ #define WAKEUP_AUDIO_XCVR_DPATH_STATUS_TX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_DPATH_STATUS_TX_FRM_CNT_SHIFT)) & WAKEUP_AUDIO_XCVR_DPATH_STATUS_TX_FRM_CNT_MASK) /*! @} */ /*! @name RX_CMDC_CTRL - CMDC receiver control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_BITS_MASK (0x1FU) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_BITS_SHIFT (0U) /*! COMMA_BITS - Number of repeating bits in COMMA pattern */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_BITS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_BITS_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_BITS_MASK) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_EN_MASK (0x80U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_EN_SHIFT (7U) /*! COMMA_EN - Enables COMMA pattern generation */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_EN_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_COMMA_EN_MASK) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_RESPONSE_TIME_MASK (0x1F00U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_RESPONSE_TIME_SHIFT (8U) /*! RESPONSE_TIME - Transmitter response timeout to a received message */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_RESPONSE_TIME(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_RESPONSE_TIME_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_RESPONSE_TIME_MASK) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TURNOVER_TIME_MASK (0xF0000U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TURNOVER_TIME_SHIFT (16U) /*! TURNOVER_TIME - Minimum time before a response is generated */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TURNOVER_TIME(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TURNOVER_TIME_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TURNOVER_TIME_MASK) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TX_DRIVE_STOP_MASK (0x700000U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TX_DRIVE_STOP_SHIFT (20U) /*! TX_DRIVE_STOP - Transmitter bus release time */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TX_DRIVE_STOP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TX_DRIVE_STOP_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_TX_DRIVE_STOP_MASK) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_LBACK_EN_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_LBACK_EN_SHIFT (31U) /*! LBACK_EN - Loopback enable */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_LBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_LBACK_EN_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_CTRL_LBACK_EN_MASK) /*! @} */ /*! @name RX_CMDC_STATUS - AUDIO_XCVR CMDC status */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_STATUS_CMDC_STATE_MASK (0xF0000U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_STATUS_CMDC_STATE_SHIFT (16U) /*! CMDC_STATE - Current state of the RX CDMC control state machine */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_STATUS_CMDC_STATE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_STATUS_CMDC_STATE_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_STATUS_CMDC_STATE_MASK) /*! @} */ /*! @name RX_CMDC_TX_DATA - CMDC transmit data register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_TX_DATA_MASK (0x3FFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_TX_DATA_SHIFT (0U) /*! TX_DATA - Transmit data */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_TX_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_TX_DATA_MASK) #define WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_DATA_VALID_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_DATA_VALID_SHIFT (31U) /*! DATA_VALID - Transmit Data Valid */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_DATA_VALID_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_TX_DATA_DATA_VALID_MASK) /*! @} */ /*! @name RX_CMDC_RX_DATA - CMDC receive data register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_RX_DATA_MASK (0x3FFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_RX_DATA_SHIFT (0U) /*! RX_DATA - Receive data */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_RX_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_RX_DATA_MASK) #define WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_CLR_RX_DATA_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_CLR_RX_DATA_SHIFT (31U) /*! CLR_RX_DATA - Clear RX data field and */ #define WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_CLR_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_CLR_RX_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CMDC_RX_DATA_CLR_RX_DATA_MASK) /*! @} */ /*! @name RX_DATAPATH_CTRL - Data path control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK (0x1U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT (0U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_MASK (0x8U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_SHIFT (3U) /*! ECC_VUC_BITS_EN - RX_DATAPATH: Enable VUC bit replacement after ECC correction. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_MASK (0x10U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_SHIFT (4U) /*! EN_COMP_PARITY_CALC - RX_DATAPATH: Enable Compressed mode Parity calculation. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK (0x20U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT (5U) /*! RST_PKT_CNT_FIFO - Resets the packet count fifo. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_STORE_FMT_MASK (0x40U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_STORE_FMT_SHIFT (6U) /*! STORE_FMT - Receive Data store format. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_STORE_FMT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_STORE_FMT_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_STORE_FMT_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK (0x80U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT (7U) /*! EN_PARITY_CALC - Enable Parity calculation. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_PARITY_CALC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDR_MASK (0x100U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDR_SHIFT (8U) /*! UDR - User data reset */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDR_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDR_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSR_MASK (0x200U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSR_SHIFT (9U) /*! CSR - Channel Status reset */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSR_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSR_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDA_MASK (0x400U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDA_SHIFT (10U) /*! UDA - User Data Acknowledge */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDA_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_UDA_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSA_MASK (0x800U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSA_SHIFT (11U) /*! CSA - Channel Status Acknowledge */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSA_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CSA_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK (0x1000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT (12U) /*! CLR_RX_FIFO - Clear Receive FIFO */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CLR_RX_FIFO(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DIS_B_PRE_ERR_CHK_MASK (0x2000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DIS_B_PRE_ERR_CHK_SHIFT (13U) /*! DIS_B_PRE_ERR_CHK - RX_DATAPATH: Disable B preamble error check. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DIS_B_PRE_ERR_CHK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DIS_B_PRE_ERR_CHK_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DIS_B_PRE_ERR_CHK_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK (0xC000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT (14U) /*! RX_DATA_FMT - Indicates format of data stored in memory. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RX_DATA_FMT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PABS_MASK (0x80000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PABS_SHIFT (19U) /*! PABS - Enable preamble search */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PABS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PABS_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PABS_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DTS_CDS_MASK (0x100000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DTS_CDS_SHIFT (20U) /*! DTS_CDS - Enable DTS CD 14 preamble search */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DTS_CDS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DTS_CDS_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_DTS_CDS_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_BLKC_MASK (0x200000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_BLKC_SHIFT (21U) /*! BLKC - Block Compressed data */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_BLKC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_BLKC_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_BLKC_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_CTRL_MASK (0x400000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT (22U) /*! MUTE_CTRL - M0+ mute request */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_CTRL_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_MODE_MASK (0x800000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT (23U) /*! MUTE_MODE - Mute mode control */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_MUTE_MODE_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_CTRL_MASK (0x1000000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_CTRL_SHIFT (24U) /*! FMT_CHG_CTRL - Format Change detection control. */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_CTRL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_CTRL_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_MODE_MASK (0x2000000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_MODE_SHIFT (25U) /*! FMT_CHG_MODE - Format change detected. Reset HW for next frame */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_MODE_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FMT_CHG_MODE_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_CTRL_MASK (0x4000000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_CTRL_SHIFT (26U) /*! LAYB_CTRL - Layout B mode control */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_CTRL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_CTRL_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_MODE_MASK (0x8000000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_MODE_SHIFT (27U) /*! LAYB_MODE - Layout B */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_MODE_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_LAYB_MODE_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PRC_MASK (0x10000000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PRC_SHIFT (28U) /*! PRC - Process Compressed */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PRC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PRC_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_PRC_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_COMP_MASK (0x20000000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_COMP_SHIFT (29U) /*! COMP - Compressed data search mode */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_COMP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_COMP_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_COMP_MASK) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FSM_MASK (0xC0000000U) #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FSM_SHIFT (30U) /*! FSM - IEC60958-1 Frame Synchronization Mode */ #define WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FSM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FSM_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DATAPATH_CTRL_FSM_MASK) /*! @} */ /*! @name RX_CS_DATA_BITS - Channel status bits */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_CS_DATA_BITS_CS_DATA_SHIFT (0U) /*! CS_DATA - Channel Status bits */ #define WAKEUP_AUDIO_XCVR_RX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_CS_DATA_BITS_CS_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_CS_DATA_BITS_CS_DATA_MASK) /*! @} */ /* The count of WAKEUP_AUDIO_XCVR_RX_CS_DATA_BITS */ #define WAKEUP_AUDIO_XCVR_RX_CS_DATA_BITS_COUNT (6U) /*! @name RX_USER_DATA_BITS - User data bits */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_USER_DATA_BITS_U_DATA_SHIFT (0U) /*! U_DATA - User data bits */ #define WAKEUP_AUDIO_XCVR_RX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_USER_DATA_BITS_U_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_USER_DATA_BITS_U_DATA_MASK) /*! @} */ /* The count of WAKEUP_AUDIO_XCVR_RX_USER_DATA_BITS */ #define WAKEUP_AUDIO_XCVR_RX_USER_DATA_BITS_COUNT (6U) /*! @name RX_DPATH_CNTR_CTRL - DMAC counter control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U) #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U) /*! TS_EN - Timestamp counter enable */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_EN_MASK) #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U) #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U) /*! TS_INC - Timestamp Increment */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_TS_INC_MASK) #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U) #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U) /*! RST_BIT_CNTR - Reset bit counter. */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK) #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U) #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U) /*! RST_TS_CNTR - Reset timestamp counter. */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK) /*! @} */ /*! @name RX_DPATH_TSCR - Receive Datapath Timestamp Counter Register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_TSCR_CVAL_SHIFT (0U) /*! CVAL - Timestamp counter value */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_TSCR_CVAL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_TSCR_CVAL_MASK) /*! @} */ /*! @name RX_DPATH_BCR - Receive Datapath Bit counter register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCR_CVAL_SHIFT (0U) /*! CVAL - Bit count value */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_BCR_CVAL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_BCR_CVAL_MASK) /*! @} */ /*! @name RX_DPATH_BCTR - Receive datapath Bit count timestamp register. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCTR_BCT_VAL_SHIFT (0U) /*! BCT_VAL - Bit count timestamp value */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_BCTR_BCT_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_BCTR_BCT_VAL_MASK) /*! @} */ /*! @name RX_DPATH_BCRR - Receive datapath Bit read timestamp register. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCRR_BCT_VAL_SHIFT (0U) /*! BCT_VAL - Bit count timestamp value */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_BCRR_BCT_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_BCRR_BCT_VAL_MASK) /*! @} */ /*! @name DMAC_PRE_MATCH_VAL - Preamble match value register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PB_VAL_MASK (0xFFFFU) #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PB_VAL_SHIFT (0U) /*! PB_VAL - Preamble PB value */ #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PB_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PB_VAL_MASK) #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PA_VAL_MASK (0xFFFF0000U) #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PA_VAL_SHIFT (16U) /*! PA_VAL - Preamble PA value */ #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PA_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_VAL_PA_VAL_MASK) /*! @} */ /*! @name DMAC_DTS_PRE_MATCH_VAL - Preamble match value register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK (0xFFFFU) #define WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT (0U) /*! DTS_PB_VAL - Preamble PB value */ #define WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK) #define WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK (0xFFFF0000U) #define WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT (16U) /*! DTS_PA_VAL - Preamble PA value */ #define WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK) /*! @} */ /*! @name RX_DPATH_PRE_ERR - Error count for IEC60958-1 Block Synchronization. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_PRE_ERRS_MASK (0xFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT (0U) /*! PRE_ERRS - Preamble Error counter */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_PRE_ERRS_MASK) #define WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_CLEAR_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_CLEAR_SHIFT (31U) /*! CLEAR - Clear bit for error counter. */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_CLEAR_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_PRE_ERR_CLEAR_MASK) /*! @} */ /*! @name RX_DPATH_PARITY_ERR - Parity Error count for IEC60958-1 Blocks. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK (0xFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT (0U) /*! PRE_ERRS - Preamble Error counter */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK) #define WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_CLEAR_MASK (0x80000000U) #define WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_CLEAR_SHIFT (31U) /*! CLEAR - Clear bit for error counter. */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_CLEAR_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_PARITY_ERR_CLEAR_MASK) /*! @} */ /*! @name RX_DPATH_PKT_CNT - Receive Data packet count. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PKT_CNT_VAL_MASK (0x7FFFFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_PKT_CNT_VAL_SHIFT (0U) /*! VAL - Data packet counter */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_PKT_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_PKT_CNT_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_PKT_CNT_VAL_MASK) /*! @} */ /*! @name RX_DPATH_ONE_BIT_ERR_CNT - Receive Data packet Corrected error count. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_RX_DPATH_ONE_BIT_ERR_CNT_VAL_MASK (0xFFFFU) #define WAKEUP_AUDIO_XCVR_RX_DPATH_ONE_BIT_ERR_CNT_VAL_SHIFT (0U) #define WAKEUP_AUDIO_XCVR_RX_DPATH_ONE_BIT_ERR_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_RX_DPATH_ONE_BIT_ERR_CNT_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_RX_DPATH_ONE_BIT_ERR_CNT_VAL_MASK) /*! @} */ /*! @name DMAC_PRE_MATCH_OFFSET - Preamble match offset value register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT (0U) /*! PA_OFFSET - Sample count value for PA offset match */ #define WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_OFFSET_PA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT)) & WAKEUP_AUDIO_XCVR_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_MASK) /*! @} */ /*! @name TX_DATAPATH_CTRL - Transmit Data path control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_ACK_MASK (0x1U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_ACK_SHIFT (0U) /*! CS_ACK - Channel Status ACK */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_ACK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_ACK_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_ACK_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_ACK_MASK (0x2U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_ACK_SHIFT (1U) /*! UD_ACK - User Data ACK */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_ACK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_ACK_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_ACK_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_MOD_MASK (0x4U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_MOD_SHIFT (2U) /*! CS_MOD - Enable Channel Status insertion */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_MOD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_MOD_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_CS_MOD_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_MOD_MASK (0x8U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_MOD_SHIFT (3U) /*! UD_MOD - Enable User Data insertion */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_MOD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_MOD_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_UD_MOD_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_VLD_MOD_MASK (0x10U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_VLD_MOD_SHIFT (4U) /*! VLD_MOD - Enable Valid bit insertion */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_VLD_MOD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_VLD_MOD_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_VLD_MOD_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_VLD_MASK (0x20U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_VLD_SHIFT (5U) /*! FRM_VLD - Valid bit value */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_VLD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_VLD_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_VLD_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PARITY_MASK (0x40U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PARITY_SHIFT (6U) /*! EN_PARITY - Enable parity insertion */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PARITY(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PARITY_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PARITY_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK (0x80U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT (7U) /*! EN_PREAMBLE - Enable preamble insertion */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_BYPASS_FEM_MASK (0x400U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_BYPASS_FEM_SHIFT (10U) /*! BYPASS_FEM - Control the TX clock rate */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_BYPASS_FEM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_BYPASS_FEM_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_BYPASS_FEM_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_FMT_MASK (0x800U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_FMT_SHIFT (11U) /*! FRM_FMT - Frame format of input data */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_FMT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_FMT_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_FRM_FMT_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_TX_FORMAT_MASK (0x3000U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT (12U) /*! TX_FORMAT - Transmit data format */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_TX_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_TX_FORMAT_MASK) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK (0x4000U) #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT (14U) /*! STRT_DATA_TX - Once Comma pattern is successively received, and heartbeat is detected, start TX of DMAC data. */ #define WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_STRT_DATA_TX(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK) /*! @} */ /*! @name TX_CS_DATA_BITS - Channel status bits */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_TX_CS_DATA_BITS_CS_DATA_SHIFT (0U) /*! CS_DATA - Channel Status bits / block */ #define WAKEUP_AUDIO_XCVR_TX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_CS_DATA_BITS_CS_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_CS_DATA_BITS_CS_DATA_MASK) /*! @} */ /* The count of WAKEUP_AUDIO_XCVR_TX_CS_DATA_BITS */ #define WAKEUP_AUDIO_XCVR_TX_CS_DATA_BITS_COUNT (6U) /*! @name TX_USER_DATA_BITS - User data bits */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_TX_USER_DATA_BITS_U_DATA_SHIFT (0U) /*! U_DATA - User data bits/block */ #define WAKEUP_AUDIO_XCVR_TX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_USER_DATA_BITS_U_DATA_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_USER_DATA_BITS_U_DATA_MASK) /*! @} */ /* The count of WAKEUP_AUDIO_XCVR_TX_USER_DATA_BITS */ #define WAKEUP_AUDIO_XCVR_TX_USER_DATA_BITS_COUNT (6U) /*! @name TX_DPATH_CNTR_CTRL - DMAC counter control register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U) #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U) /*! TS_EN - Timestamp counter enable */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_EN_MASK) #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U) #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U) /*! TS_INC - Timestamp Increment */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_TS_INC_MASK) #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U) #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U) /*! RST_BIT_CNTR - Reset bit counter. */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK) #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U) #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U) /*! RST_TS_CNTR - Reset timestamp counter. */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK) /*! @} */ /*! @name TX_DPATH_TSCR - Transmit Datapath Timestamp Counter Register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_TX_DPATH_TSCR_CVAL_SHIFT (0U) /*! CVAL - Timestamp counter value */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_TSCR_CVAL_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_TSCR_CVAL_MASK) /*! @} */ /*! @name TX_DPATH_BCR - Transmit Datapath Bit counter register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCR_CVAL_SHIFT (0U) /*! CVAL - Bit count value */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_BCR_CVAL_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_BCR_CVAL_MASK) /*! @} */ /*! @name TX_DPATH_BCTR - Transmit datapath Bit count timestamp register. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCTR_BCT_VAL_SHIFT (0U) /*! BCT_VAL - Bit count timestamp value */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_BCTR_BCT_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_BCTR_BCT_VAL_MASK) /*! @} */ /*! @name TX_DPATH_BCRR - Transmit datapath Bit read timestamp register. */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCRR_BCT_VAL_SHIFT (0U) /*! BCT_VAL - Bit count timestamp value */ #define WAKEUP_AUDIO_XCVR_TX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_TX_DPATH_BCRR_BCT_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_TX_DPATH_BCRR_BCT_VAL_MASK) /*! @} */ /*! @name HPD_DBNC_CTRL - HPD Debounce Control Register */ /*! @{ */ #define WAKEUP_AUDIO_XCVR_HPD_DBNC_CTRL_VAL_MASK (0xFFFFFFFFU) #define WAKEUP_AUDIO_XCVR_HPD_DBNC_CTRL_VAL_SHIFT (0U) /*! VAL - HDP pin debounce interval */ #define WAKEUP_AUDIO_XCVR_HPD_DBNC_CTRL_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_AUDIO_XCVR_HPD_DBNC_CTRL_VAL_SHIFT)) & WAKEUP_AUDIO_XCVR_HPD_DBNC_CTRL_VAL_MASK) /*! @} */ /*! * @} */ /* end of group WAKEUP_AUDIO_XCVR_Register_Masks */ /* WAKEUP_AUDIO_XCVR - Peripheral instance base addresses */ /** Peripheral WAKEUP__AUDIO_XCVR base address */ #define WAKEUP__AUDIO_XCVR_BASE (0x42680000u) /** Peripheral WAKEUP__AUDIO_XCVR base pointer */ #define WAKEUP__AUDIO_XCVR ((WAKEUP_AUDIO_XCVR_Type *)WAKEUP__AUDIO_XCVR_BASE) /** Array initializer of WAKEUP_AUDIO_XCVR peripheral base addresses */ #define WAKEUP_AUDIO_XCVR_BASE_ADDRS { WAKEUP__AUDIO_XCVR_BASE } /** Array initializer of WAKEUP_AUDIO_XCVR peripheral base pointers */ #define WAKEUP_AUDIO_XCVR_BASE_PTRS { WAKEUP__AUDIO_XCVR } /*! * @} */ /* end of group WAKEUP_AUDIO_XCVR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_CMU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_CMU_Peripheral_Access_Layer WAKEUP_CMU Peripheral Access Layer * @{ */ /** WAKEUP_CMU - Register Layout Typedef */ typedef struct { __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ __IO uint32_t SR; /**< Status Register, offset: 0x10 */ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ } WAKEUP_CMU_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_CMU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_CMU_Register_Masks WAKEUP_CMU Register Masks * @{ */ /*! @name GCR - Global Configuration Register */ /*! @{ */ #define WAKEUP_CMU_GCR_FCE_MASK (0x1U) #define WAKEUP_CMU_GCR_FCE_SHIFT (0U) /*! FCE - Frequency Check Enable * 0b0..Stops frequency checking * 0b1..Starts frequency checking */ #define WAKEUP_CMU_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_GCR_FCE_SHIFT)) & WAKEUP_CMU_GCR_FCE_MASK) /*! @} */ /*! @name RCCR - Reference Count Configuration Register */ /*! @{ */ #define WAKEUP_CMU_RCCR_REF_CNT_MASK (0xFFFFU) #define WAKEUP_CMU_RCCR_REF_CNT_SHIFT (0U) /*! REF_CNT - Reference clock count */ #define WAKEUP_CMU_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_RCCR_REF_CNT_SHIFT)) & WAKEUP_CMU_RCCR_REF_CNT_MASK) /*! @} */ /*! @name HTCR - High Threshold Configuration Register */ /*! @{ */ #define WAKEUP_CMU_HTCR_HFREF_MASK (0xFFFFFFU) #define WAKEUP_CMU_HTCR_HFREF_SHIFT (0U) /*! HFREF - High frequency reference threshold */ #define WAKEUP_CMU_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_HTCR_HFREF_SHIFT)) & WAKEUP_CMU_HTCR_HFREF_MASK) /*! @} */ /*! @name LTCR - Low Threshold Configuration Register */ /*! @{ */ #define WAKEUP_CMU_LTCR_LFREF_MASK (0xFFFFFFU) #define WAKEUP_CMU_LTCR_LFREF_SHIFT (0U) /*! LFREF - Low Frequency Reference Threshold */ #define WAKEUP_CMU_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_LTCR_LFREF_SHIFT)) & WAKEUP_CMU_LTCR_LFREF_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define WAKEUP_CMU_SR_FLL_MASK (0x1U) #define WAKEUP_CMU_SR_FLL_SHIFT (0U) /*! FLL - Frequency lower than low frequency reference threshold event status * 0b0..No FLL event * 0b1..FLL event occurred */ #define WAKEUP_CMU_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_SR_FLL_SHIFT)) & WAKEUP_CMU_SR_FLL_MASK) #define WAKEUP_CMU_SR_FHH_MASK (0x2U) #define WAKEUP_CMU_SR_FHH_SHIFT (1U) /*! FHH - Frequency higher than high frequency reference threshold event status * 0b0..No FHH event * 0b1..FHH event occurred */ #define WAKEUP_CMU_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_SR_FHH_SHIFT)) & WAKEUP_CMU_SR_FHH_MASK) #define WAKEUP_CMU_SR_RS_MASK (0x10U) #define WAKEUP_CMU_SR_RS_SHIFT (4U) /*! RS - Run Status * 0b0..Frequency check stopped * 0b1..Frequency check running */ #define WAKEUP_CMU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_SR_RS_SHIFT)) & WAKEUP_CMU_SR_RS_MASK) /*! @} */ /*! @name IER - Interrupt Enable Register */ /*! @{ */ #define WAKEUP_CMU_IER_FLLAIE_MASK (0x4U) #define WAKEUP_CMU_IER_FLLAIE_SHIFT (2U) /*! FLLAIE - Frequency Lower than Low Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FLL event interrupt disabled * 0b1..Asynchronous FLL event interrupt enabled */ #define WAKEUP_CMU_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_IER_FLLAIE_SHIFT)) & WAKEUP_CMU_IER_FLLAIE_MASK) #define WAKEUP_CMU_IER_FHHAIE_MASK (0x8U) #define WAKEUP_CMU_IER_FHHAIE_SHIFT (3U) /*! FHHAIE - Frequency Higher than High Frequency Reference Threshold Asynchronous Interrupt Enable * 0b0..Asynchronous FHH event interrupt disabled * 0b1..Asynchronous FHH event interrupt enabled */ #define WAKEUP_CMU_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_CMU_IER_FHHAIE_SHIFT)) & WAKEUP_CMU_IER_FHHAIE_MASK) /*! @} */ /*! * @} */ /* end of group WAKEUP_CMU_Register_Masks */ /* WAKEUP_CMU - Peripheral instance base addresses */ /** Peripheral WAKEUP__CMU1 base address */ #define WAKEUP__CMU1_BASE (0x42750000u) /** Peripheral WAKEUP__CMU1 base pointer */ #define WAKEUP__CMU1 ((WAKEUP_CMU_Type *)WAKEUP__CMU1_BASE) /** Peripheral WAKEUP__CMU2 base address */ #define WAKEUP__CMU2_BASE (0x427A0000u) /** Peripheral WAKEUP__CMU2 base pointer */ #define WAKEUP__CMU2 ((WAKEUP_CMU_Type *)WAKEUP__CMU2_BASE) /** Array initializer of WAKEUP_CMU peripheral base addresses */ #define WAKEUP_CMU_BASE_ADDRS { WAKEUP__CMU1_BASE, WAKEUP__CMU2_BASE } /** Array initializer of WAKEUP_CMU peripheral base pointers */ #define WAKEUP_CMU_BASE_PTRS { WAKEUP__CMU1, WAKEUP__CMU2 } /*! * @} */ /* end of group WAKEUP_CMU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_DMA_CRC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_DMA_CRC_Peripheral_Access_Layer WAKEUP_DMA_CRC Peripheral Access Layer * @{ */ /** WAKEUP_DMA_CRC - Register Layout Typedef */ typedef struct { __IO uint32_t GEC; /**< Global Enable CRC Register, offset: 0x0 */ uint8_t RESERVED_0[12]; struct { /* offset: 0x10, array step: 0x10 */ __IO uint32_t CTL; /**< CRC Control Register, array offset: 0x10, array step: 0x10 */ __IO uint32_t ICRC; /**< Initial CRC Value Register, array offset: 0x14, array step: 0x10 */ __I uint32_t FCRC; /**< Final CRC Value Register, array offset: 0x18, array step: 0x10 */ uint8_t RESERVED_0[4]; } CONTROL_REGISTER[8]; } WAKEUP_DMA_CRC_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_DMA_CRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_DMA_CRC_Register_Masks WAKEUP_DMA_CRC Register Masks * @{ */ /*! @name GEC - Global Enable CRC Register */ /*! @{ */ #define WAKEUP_DMA_CRC_GEC_GBL_EN_MASK (0x1U) #define WAKEUP_DMA_CRC_GEC_GBL_EN_SHIFT (0U) /*! GBL_EN - Global Enable bit * 0b0..Disable CRC in all channels. * 0b1..Enable CRC in all channels. */ #define WAKEUP_DMA_CRC_GEC_GBL_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_GEC_GBL_EN_SHIFT)) & WAKEUP_DMA_CRC_GEC_GBL_EN_MASK) #define WAKEUP_DMA_CRC_GEC_SWAP_BYTE_MASK (0x80U) #define WAKEUP_DMA_CRC_GEC_SWAP_BYTE_SHIFT (7U) /*! SWAP_BYTE - Swap Byte * 0b0..Do not swap. * 0b1..Byte-wise swap on the input data. */ #define WAKEUP_DMA_CRC_GEC_SWAP_BYTE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_GEC_SWAP_BYTE_SHIFT)) & WAKEUP_DMA_CRC_GEC_SWAP_BYTE_MASK) /*! @} */ /*! @name CTL - CRC Control Register */ /*! @{ */ #define WAKEUP_DMA_CRC_CTL_CH_SEL_MASK (0x3FU) #define WAKEUP_DMA_CRC_CTL_CH_SEL_SHIFT (0U) /*! CH_SEL - Channel Select * 0b000000..Select Channel 0. * 0b000001..Select Channel 1. * 0b111110..Select Channel 62. * 0b111111..Select Channel 63. */ #define WAKEUP_DMA_CRC_CTL_CH_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_CH_SEL_SHIFT)) & WAKEUP_DMA_CRC_CTL_CH_SEL_MASK) #define WAKEUP_DMA_CRC_CTL_POLY_SEL_MASK (0x700U) #define WAKEUP_DMA_CRC_CTL_POLY_SEL_SHIFT (8U) /*! POLY_SEL - Polynomial Select * 0b000..Select CRC-32 0x04C11DB7. * 0b001..Select CRC-32 0x1EDC6F41. * 0b010..Select CRC-32 0xF4ACFB13. * 0b011..Select CRC-16 0x1021. * 0b100..Select CRC-8 0x2F. * 0b101..Select CRC-8 0x1D. * 0b110..Reserved * 0b111..Reserved */ #define WAKEUP_DMA_CRC_CTL_POLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_POLY_SEL_SHIFT)) & WAKEUP_DMA_CRC_CTL_POLY_SEL_MASK) #define WAKEUP_DMA_CRC_CTL_CS_XOR_MASK (0x1000U) #define WAKEUP_DMA_CRC_CTL_CS_XOR_SHIFT (12U) /*! CS_XOR * 0b0..Do not apply the XOR. * 0b1..Perform XOR of FFFFFFFFh to the checksum for CRC-32, FFFFh for CRC-16, and FFh for CRC-8. */ #define WAKEUP_DMA_CRC_CTL_CS_XOR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_CS_XOR_SHIFT)) & WAKEUP_DMA_CRC_CTL_CS_XOR_MASK) #define WAKEUP_DMA_CRC_CTL_CS_SWAP_MASK (0x2000U) #define WAKEUP_DMA_CRC_CTL_CS_SWAP_SHIFT (13U) /*! CS_SWAP * 0b0..Do not swap. * 0b1..Perform bit-wise swap within each byte of the checksum result. */ #define WAKEUP_DMA_CRC_CTL_CS_SWAP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_CS_SWAP_SHIFT)) & WAKEUP_DMA_CRC_CTL_CS_SWAP_MASK) #define WAKEUP_DMA_CRC_CTL_SWAP_BIT_MASK (0x4000U) #define WAKEUP_DMA_CRC_CTL_SWAP_BIT_SHIFT (14U) /*! SWAP_BIT - Swap Bit * 0b0..Do not swap. * 0b1..Perform bit-wise swap within each byte of the input data. */ #define WAKEUP_DMA_CRC_CTL_SWAP_BIT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_SWAP_BIT_SHIFT)) & WAKEUP_DMA_CRC_CTL_SWAP_BIT_MASK) #define WAKEUP_DMA_CRC_CTL_INIT_SEL_MASK (0x8000U) #define WAKEUP_DMA_CRC_CTL_INIT_SEL_SHIFT (15U) /*! INIT_SEL - Initial values of the CRC * 0b0..Initialize CRC with the content of the Initial CRC Value Register (ICRC). * 0b1..Continue accumulating previous CRC values stored in Final CRC Value Register (FCRC). */ #define WAKEUP_DMA_CRC_CTL_INIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_INIT_SEL_SHIFT)) & WAKEUP_DMA_CRC_CTL_INIT_SEL_MASK) #define WAKEUP_DMA_CRC_CTL_MODE_MASK (0x70000U) #define WAKEUP_DMA_CRC_CTL_MODE_SHIFT (16U) /*! MODE - CRC Mode * 0b000..Normal CRC Mode. All other combinations are invalid. */ #define WAKEUP_DMA_CRC_CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_MODE_SHIFT)) & WAKEUP_DMA_CRC_CTL_MODE_MASK) #define WAKEUP_DMA_CRC_CTL_EN_MASK (0x80000000U) #define WAKEUP_DMA_CRC_CTL_EN_SHIFT (31U) /*! EN - CRC Logic * 0b0..Disable CRC. * 0b1..Enable CRC. */ #define WAKEUP_DMA_CRC_CTL_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_CTL_EN_SHIFT)) & WAKEUP_DMA_CRC_CTL_EN_MASK) /*! @} */ /* The count of WAKEUP_DMA_CRC_CTL */ #define WAKEUP_DMA_CRC_CTL_COUNT (8U) /*! @name ICRC - Initial CRC Value Register */ /*! @{ */ #define WAKEUP_DMA_CRC_ICRC_INI_CRC_VAL_MASK (0xFFFFFFFFU) #define WAKEUP_DMA_CRC_ICRC_INI_CRC_VAL_SHIFT (0U) /*! INI_CRC_VAL - Initial CRC Value */ #define WAKEUP_DMA_CRC_ICRC_INI_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_ICRC_INI_CRC_VAL_SHIFT)) & WAKEUP_DMA_CRC_ICRC_INI_CRC_VAL_MASK) /*! @} */ /* The count of WAKEUP_DMA_CRC_ICRC */ #define WAKEUP_DMA_CRC_ICRC_COUNT (8U) /*! @name FCRC - Final CRC Value Register */ /*! @{ */ #define WAKEUP_DMA_CRC_FCRC_CHKSUM_VAL_MASK (0xFFFFFFFFU) #define WAKEUP_DMA_CRC_FCRC_CHKSUM_VAL_SHIFT (0U) /*! CHKSUM_VAL - Final CRC Value */ #define WAKEUP_DMA_CRC_FCRC_CHKSUM_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_DMA_CRC_FCRC_CHKSUM_VAL_SHIFT)) & WAKEUP_DMA_CRC_FCRC_CHKSUM_VAL_MASK) /*! @} */ /* The count of WAKEUP_DMA_CRC_FCRC */ #define WAKEUP_DMA_CRC_FCRC_COUNT (8U) /*! * @} */ /* end of group WAKEUP_DMA_CRC_Register_Masks */ /* WAKEUP_DMA_CRC - Peripheral instance base addresses */ /** Peripheral WAKEUP__DMA_CRC2 base address */ #define WAKEUP__DMA_CRC2_BASE (0x427B0000u) /** Peripheral WAKEUP__DMA_CRC2 base pointer */ #define WAKEUP__DMA_CRC2 ((WAKEUP_DMA_CRC_Type *)WAKEUP__DMA_CRC2_BASE) /** Array initializer of WAKEUP_DMA_CRC peripheral base addresses */ #define WAKEUP_DMA_CRC_BASE_ADDRS { WAKEUP__DMA_CRC2_BASE } /** Array initializer of WAKEUP_DMA_CRC peripheral base pointers */ #define WAKEUP_DMA_CRC_BASE_PTRS { WAKEUP__DMA_CRC2 } /*! * @} */ /* end of group WAKEUP_DMA_CRC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_EIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_EIM_Peripheral_Access_Layer WAKEUP_EIM Peripheral Access Layer * @{ */ /** WAKEUP_EIM - Register Layout Typedef */ typedef struct { __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ uint8_t RESERVED_0[248]; __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ __IO uint32_t EICHD0_WORD2; /**< Error Injection Channel Descriptor 0, Word2, offset: 0x108 */ uint8_t RESERVED_1[52]; __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ uint8_t RESERVED_2[56]; __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ uint8_t RESERVED_3[124]; __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ uint8_t RESERVED_4[60]; __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ } WAKEUP_EIM_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_EIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_EIM_Register_Masks WAKEUP_EIM Register Masks * @{ */ /*! @name EIMCR - Error Injection Module Configuration Register */ /*! @{ */ #define WAKEUP_EIM_EIMCR_GEIEN_MASK (0x1U) #define WAKEUP_EIM_EIMCR_GEIEN_SHIFT (0U) /*! GEIEN - Global Error Injection Enable * 0b0..Disabled * 0b1..Enabled */ #define WAKEUP_EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EIMCR_GEIEN_SHIFT)) & WAKEUP_EIM_EIMCR_GEIEN_MASK) /*! @} */ /*! @name EICHEN - Error Injection Channel Enable register */ /*! @{ */ #define WAKEUP_EIM_EICHEN_EICH5EN_MASK (0x4000000U) #define WAKEUP_EIM_EICHEN_EICH5EN_SHIFT (26U) /*! EICH5EN - Error Injection Channel 5 Enable * 0b0..Error injection is disabled on Error Injection Channel 5 * 0b1..Error injection is enabled on Error Injection Channel 5 */ #define WAKEUP_EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHEN_EICH5EN_SHIFT)) & WAKEUP_EIM_EICHEN_EICH5EN_MASK) #define WAKEUP_EIM_EICHEN_EICH4EN_MASK (0x8000000U) #define WAKEUP_EIM_EICHEN_EICH4EN_SHIFT (27U) /*! EICH4EN - Error Injection Channel 4 Enable * 0b0..Error injection is disabled on Error Injection Channel 4 * 0b1..Error injection is enabled on Error Injection Channel 4 */ #define WAKEUP_EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHEN_EICH4EN_SHIFT)) & WAKEUP_EIM_EICHEN_EICH4EN_MASK) #define WAKEUP_EIM_EICHEN_EICH2EN_MASK (0x20000000U) #define WAKEUP_EIM_EICHEN_EICH2EN_SHIFT (29U) /*! EICH2EN - Error Injection Channel 2 Enable * 0b0..Error injection is disabled on Error Injection Channel 2 * 0b1..Error injection is enabled on Error Injection Channel 2 */ #define WAKEUP_EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHEN_EICH2EN_SHIFT)) & WAKEUP_EIM_EICHEN_EICH2EN_MASK) #define WAKEUP_EIM_EICHEN_EICH1EN_MASK (0x40000000U) #define WAKEUP_EIM_EICHEN_EICH1EN_SHIFT (30U) /*! EICH1EN - Error Injection Channel 1 Enable * 0b0..Error injection is disabled on Error Injection Channel 1 * 0b1..Error injection is enabled on Error Injection Channel 1 */ #define WAKEUP_EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHEN_EICH1EN_SHIFT)) & WAKEUP_EIM_EICHEN_EICH1EN_MASK) #define WAKEUP_EIM_EICHEN_EICH0EN_MASK (0x80000000U) #define WAKEUP_EIM_EICHEN_EICH0EN_SHIFT (31U) /*! EICH0EN - Error Injection Channel 0 Enable * 0b0..Error injection is disabled on Error Injection Channel 0 * 0b1..Error injection is enabled on Error Injection Channel 0 */ #define WAKEUP_EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHEN_EICH0EN_SHIFT)) & WAKEUP_EIM_EICHEN_EICH0EN_MASK) /*! @} */ /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ /*! @{ */ #define WAKEUP_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define WAKEUP_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define WAKEUP_EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & WAKEUP_EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ /*! @{ */ #define WAKEUP_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define WAKEUP_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define WAKEUP_EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & WAKEUP_EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD0_WORD2 - Error Injection Channel Descriptor 0, Word2 */ /*! @{ */ #define WAKEUP_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) #define WAKEUP_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT (0U) /*! B4_7DATA_MASK - Data Mask Bytes 4-7 */ #define WAKEUP_EIM_EICHD0_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT)) & WAKEUP_EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ /*! @{ */ #define WAKEUP_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define WAKEUP_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define WAKEUP_EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & WAKEUP_EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ /*! @{ */ #define WAKEUP_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0x1U) #define WAKEUP_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define WAKEUP_EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & WAKEUP_EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ /*! @{ */ #define WAKEUP_EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFF000000U) #define WAKEUP_EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (24U) /*! CHKBIT_MASK - Checkbit Mask */ #define WAKEUP_EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & WAKEUP_EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) /*! @} */ /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ /*! @{ */ #define WAKEUP_EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0x1U) #define WAKEUP_EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define WAKEUP_EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & WAKEUP_EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ /*! @{ */ #define WAKEUP_EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define WAKEUP_EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define WAKEUP_EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & WAKEUP_EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ /*! @{ */ #define WAKEUP_EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) #define WAKEUP_EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) /*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ #define WAKEUP_EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & WAKEUP_EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) /*! @} */ /*! * @} */ /* end of group WAKEUP_EIM_Register_Masks */ /* WAKEUP_EIM - Peripheral instance base addresses */ /** Peripheral WAKEUP__EIMW base address */ #define WAKEUP__EIMW_BASE (0x42780000u) /** Peripheral WAKEUP__EIMW base pointer */ #define WAKEUP__EIMW ((WAKEUP_EIM_Type *)WAKEUP__EIMW_BASE) /** Array initializer of WAKEUP_EIM peripheral base addresses */ #define WAKEUP_EIM_BASE_ADDRS { WAKEUP__EIMW_BASE } /** Array initializer of WAKEUP_EIM peripheral base pointers */ #define WAKEUP_EIM_BASE_PTRS { WAKEUP__EIMW } /*! * @} */ /* end of group WAKEUP_EIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_FLEXSPI_OTFAD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_FLEXSPI_OTFAD_Peripheral_Access_Layer WAKEUP_FLEXSPI_OTFAD Peripheral Access Layer * @{ */ /** WAKEUP_FLEXSPI_OTFAD - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[3072]; __IO uint32_t CR; /**< Control Register, offset: 0xC00 */ __IO uint32_t SR; /**< Status Register, offset: 0xC04 */ uint8_t RESERVED_1[248]; struct { /* offset: 0xD00, array step: 0x40 */ __IO uint32_t KEY[4]; /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */ __IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */ __IO uint32_t RGD_W0; /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */ __IO uint32_t RGD_W1; /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */ uint8_t RESERVED_0[32]; } CTX[4]; } WAKEUP_FLEXSPI_OTFAD_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_FLEXSPI_OTFAD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_FLEXSPI_OTFAD_Register_Masks WAKEUP_FLEXSPI_OTFAD Register Masks * @{ */ /*! @name CR - Control Register */ /*! @{ */ #define WAKEUP_FLEXSPI_OTFAD_CR_FERR_MASK (0x2U) #define WAKEUP_FLEXSPI_OTFAD_CR_FERR_SHIFT (1U) /*! FERR - Force Error * 0b0..No effect on the SR[KBERE] indicator. * 0b1..SR[KBERR] is immediately set after a write with this data bit set. */ #define WAKEUP_FLEXSPI_OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CR_FERR_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CR_FERR_MASK) #define WAKEUP_FLEXSPI_OTFAD_CR_FLDM_MASK (0x8U) #define WAKEUP_FLEXSPI_OTFAD_CR_FLDM_SHIFT (3U) /*! FLDM - Force Logically Disabled Mode * 0b0..No effect on the operating mode. * 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode. */ #define WAKEUP_FLEXSPI_OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CR_FLDM_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CR_FLDM_MASK) #define WAKEUP_FLEXSPI_OTFAD_CR_KBSE_MASK (0x10U) #define WAKEUP_FLEXSPI_OTFAD_CR_KBSE_SHIFT (4U) /*! KBSE - Key Blob Scramble Enable * 0b0..Key blob KEK scrambling is disabled. * 0b1..Key blob KEK scrambling is enabled. */ #define WAKEUP_FLEXSPI_OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CR_KBSE_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CR_KBSE_MASK) #define WAKEUP_FLEXSPI_OTFAD_CR_KBPE_MASK (0x20U) #define WAKEUP_FLEXSPI_OTFAD_CR_KBPE_SHIFT (5U) /*! KBPE - Key Blob Processing Enable * 0b0..Key blob processing is disabled. * 0b1..Key blob processing is enabled. */ #define WAKEUP_FLEXSPI_OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CR_KBPE_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CR_KBPE_MASK) #define WAKEUP_FLEXSPI_OTFAD_CR_RRAE_MASK (0x80U) #define WAKEUP_FLEXSPI_OTFAD_CR_RRAE_SHIFT (7U) /*! RRAE - Restricted Register Access Enable * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. */ #define WAKEUP_FLEXSPI_OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CR_RRAE_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CR_RRAE_MASK) #define WAKEUP_FLEXSPI_OTFAD_CR_SKBP_MASK (0x40000000U) #define WAKEUP_FLEXSPI_OTFAD_CR_SKBP_SHIFT (30U) /*! SKBP - Start key blob processing * 0b0..Key blob processing is not initiated. * 0b1..Properly-enabled key blob processing is initiated. */ #define WAKEUP_FLEXSPI_OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CR_SKBP_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CR_SKBP_MASK) #define WAKEUP_FLEXSPI_OTFAD_CR_GE_MASK (0x80000000U) #define WAKEUP_FLEXSPI_OTFAD_CR_GE_SHIFT (31U) /*! GE - Global OTFAD Enable * 0b0..OTFAD has decryption disabled. All data fetched by the QuadSPI bypasses OTFAD processing. * 0b1..OTFAD has decryption enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration. */ #define WAKEUP_FLEXSPI_OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CR_GE_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CR_GE_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ #define WAKEUP_FLEXSPI_OTFAD_SR_KBERR_MASK (0x1U) #define WAKEUP_FLEXSPI_OTFAD_SR_KBERR_SHIFT (0U) /*! KBERR - Key Blob Error * 0b0..No key blob error detected. * 0b1..One or more key blob errors has been detected. */ #define WAKEUP_FLEXSPI_OTFAD_SR_KBERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_KBERR_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_KBERR_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_MDPCP_MASK (0x2U) #define WAKEUP_FLEXSPI_OTFAD_SR_MDPCP_SHIFT (1U) /*! MDPCP - MDPC Present */ #define WAKEUP_FLEXSPI_OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_MDPCP_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_MDPCP_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_MODE_MASK (0xCU) #define WAKEUP_FLEXSPI_OTFAD_SR_MODE_SHIFT (2U) /*! MODE - Operating Mode * 0b00..Operating in Normal mode (NRM) * 0b01..Unused (reserved) * 0b10..Unused (reserved) * 0b11..Operating in Logically Disabled Mode (LDM) */ #define WAKEUP_FLEXSPI_OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_MODE_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_MODE_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_NCTX_MASK (0xF0U) #define WAKEUP_FLEXSPI_OTFAD_SR_NCTX_SHIFT (4U) /*! NCTX - Number of Contexts */ #define WAKEUP_FLEXSPI_OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_NCTX_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_NCTX_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER0_MASK (0x100U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER0_SHIFT (8U) /*! CTXER0 - Context Error * 0b0..No key blob error was detected for context "n". * 0b1..A key blob integrity error might have been detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXER0_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXER0_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER1_MASK (0x200U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER1_SHIFT (9U) /*! CTXER1 - Context Error * 0b0..No key blob error was detected for context "n". * 0b1..A key blob integrity error might have been detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXER1_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXER1_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER2_MASK (0x400U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER2_SHIFT (10U) /*! CTXER2 - Context Error * 0b0..No key blob error was detected for context "n". * 0b1..A key blob integrity error might have been detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXER2_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXER2_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER3_MASK (0x800U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER3_SHIFT (11U) /*! CTXER3 - Context Error * 0b0..No key blob error was detected for context "n". * 0b1..A key blob integrity error might have been detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXER3(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXER3_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXER3_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE0_MASK (0x10000U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE0_SHIFT (16U) /*! CTXIE0 - Context Integrity Error * 0b0..No key blob integrity error was detected for context "n". * 0b1..A key blob integrity error was detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXIE0_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXIE0_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE1_MASK (0x20000U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE1_SHIFT (17U) /*! CTXIE1 - Context Integrity Error * 0b0..No key blob integrity error was detected for context "n". * 0b1..A key blob integrity error was detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXIE1_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXIE1_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE2_MASK (0x40000U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE2_SHIFT (18U) /*! CTXIE2 - Context Integrity Error * 0b0..No key blob integrity error was detected for context "n". * 0b1..A key blob integrity error was detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXIE2_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXIE2_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE3_MASK (0x80000U) #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE3_SHIFT (19U) /*! CTXIE3 - Context Integrity Error * 0b0..No key blob integrity error was detected for context "n". * 0b1..A key blob integrity error was detected in context "n". */ #define WAKEUP_FLEXSPI_OTFAD_SR_CTXIE3(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_CTXIE3_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_CTXIE3_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_HRL_MASK (0xF000000U) #define WAKEUP_FLEXSPI_OTFAD_SR_HRL_SHIFT (24U) /*! HRL - Hardware Revision Level */ #define WAKEUP_FLEXSPI_OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_HRL_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_HRL_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_RRAM_MASK (0x10000000U) #define WAKEUP_FLEXSPI_OTFAD_SR_RRAM_SHIFT (28U) /*! RRAM - Restricted Register Access Mode * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. */ #define WAKEUP_FLEXSPI_OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_RRAM_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_RRAM_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_GEM_MASK (0x20000000U) #define WAKEUP_FLEXSPI_OTFAD_SR_GEM_SHIFT (29U) /*! GEM - Global Enable Mode * 0b0..OTFAD is disabled. All data fetched by the QuadSPI bypasses OTFAD processing. * 0b1..OTFAD is enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration. */ #define WAKEUP_FLEXSPI_OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_GEM_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_GEM_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_KBPE_MASK (0x40000000U) #define WAKEUP_FLEXSPI_OTFAD_SR_KBPE_SHIFT (30U) /*! KBPE - Key Blob Processing Enable * 0b0..Key blob processing is not enabled. * 0b1..Key blob processing is enabled. */ #define WAKEUP_FLEXSPI_OTFAD_SR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_KBPE_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_KBPE_MASK) #define WAKEUP_FLEXSPI_OTFAD_SR_KBD_MASK (0x80000000U) #define WAKEUP_FLEXSPI_OTFAD_SR_KBD_SHIFT (31U) /*! KBD - Key Blob Processing Done * 0b0..Key blob processing was not enabled, or is not complete. * 0b1..Key blob processing was enabled and is complete. */ #define WAKEUP_FLEXSPI_OTFAD_SR_KBD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_SR_KBD_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_SR_KBD_MASK) /*! @} */ /*! @name KEY - AES Key Word */ /*! @{ */ #define WAKEUP_FLEXSPI_OTFAD_KEY_KEY_MASK (0xFFFFFFFFU) #define WAKEUP_FLEXSPI_OTFAD_KEY_KEY_SHIFT (0U) /*! KEY - AES Key */ #define WAKEUP_FLEXSPI_OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_KEY_KEY_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_KEY_KEY_MASK) /*! @} */ /* The count of WAKEUP_FLEXSPI_OTFAD_KEY */ #define WAKEUP_FLEXSPI_OTFAD_KEY_COUNT (4U) /* The count of WAKEUP_FLEXSPI_OTFAD_KEY */ #define WAKEUP_FLEXSPI_OTFAD_KEY_COUNT2 (4U) /*! @name CTR - AES Counter Word */ /*! @{ */ #define WAKEUP_FLEXSPI_OTFAD_CTR_CTR_MASK (0xFFFFFFFFU) #define WAKEUP_FLEXSPI_OTFAD_CTR_CTR_SHIFT (0U) /*! CTR - AES Counter */ #define WAKEUP_FLEXSPI_OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_CTR_CTR_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_CTR_CTR_MASK) /*! @} */ /* The count of WAKEUP_FLEXSPI_OTFAD_CTR */ #define WAKEUP_FLEXSPI_OTFAD_CTR_COUNT (4U) /* The count of WAKEUP_FLEXSPI_OTFAD_CTR */ #define WAKEUP_FLEXSPI_OTFAD_CTR_COUNT2 (2U) /*! @name RGD_W0 - AES Region Descriptor Word0 */ /*! @{ */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U) #define WAKEUP_FLEXSPI_OTFAD_RGD_W0_SRTADDR_SHIFT (10U) /*! SRTADDR - Start Address */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_RGD_W0_SRTADDR_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_RGD_W0_SRTADDR_MASK) /*! @} */ /* The count of WAKEUP_FLEXSPI_OTFAD_RGD_W0 */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W0_COUNT (4U) /*! @name RGD_W1 - AES Region Descriptor Word1 */ /*! @{ */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_VLD_MASK (0x1U) #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_VLD_SHIFT (0U) /*! VLD - Valid * 0b0..Context is invalid. * 0b1..Context is valid. */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_RGD_W1_VLD_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_RGD_W1_VLD_MASK) #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_ADE_MASK (0x2U) #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_ADE_SHIFT (1U) /*! ADE - AES Decryption Enable. * 0b0..Bypass the fetched data. * 0b1..Perform the CTR-AES128 mode decryption on the fetched data. */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_RGD_W1_ADE_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_RGD_W1_ADE_MASK) #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_RO_MASK (0x4U) #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_RO_SHIFT (2U) /*! RO - Read-Only * 0b0..The context registers can be accessed normally (as defined by SR[RRAM]). * 0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM]. */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_RGD_W1_RO_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_RGD_W1_RO_MASK) #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U) #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_ENDADDR_SHIFT (10U) /*! ENDADDR - End Address */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_FLEXSPI_OTFAD_RGD_W1_ENDADDR_SHIFT)) & WAKEUP_FLEXSPI_OTFAD_RGD_W1_ENDADDR_MASK) /*! @} */ /* The count of WAKEUP_FLEXSPI_OTFAD_RGD_W1 */ #define WAKEUP_FLEXSPI_OTFAD_RGD_W1_COUNT (4U) /*! * @} */ /* end of group WAKEUP_FLEXSPI_OTFAD_Register_Masks */ /* WAKEUP_FLEXSPI_OTFAD - Peripheral instance base addresses */ /** Peripheral WAKEUP__FLEXSPI_OTFAD base address */ #define WAKEUP__FLEXSPI_OTFAD_BASE (0x425E0000u) /** Peripheral WAKEUP__FLEXSPI_OTFAD base pointer */ #define WAKEUP__FLEXSPI_OTFAD ((WAKEUP_FLEXSPI_OTFAD_Type *)WAKEUP__FLEXSPI_OTFAD_BASE) /** Array initializer of WAKEUP_FLEXSPI_OTFAD peripheral base addresses */ #define WAKEUP_FLEXSPI_OTFAD_BASE_ADDRS { WAKEUP__FLEXSPI_OTFAD_BASE } /** Array initializer of WAKEUP_FLEXSPI_OTFAD peripheral base pointers */ #define WAKEUP_FLEXSPI_OTFAD_BASE_PTRS { WAKEUP__FLEXSPI_OTFAD } /*! * @} */ /* end of group WAKEUP_FLEXSPI_OTFAD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_ROMCP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_ROMCP_Peripheral_Access_Layer WAKEUP_ROMCP Peripheral Access Layer * @{ */ /** WAKEUP_ROMCP - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[180]; __IO uint32_t ROMPATCHD[16]; /**< Data Registers, array offset: 0xB4, array step: 0x4 */ __IO uint32_t ROMPATCHCNTL; /**< Control Register, offset: 0xF4 */ uint32_t ROMPATCHENH; /**< Enable Register High, offset: 0xF8 */ __IO uint32_t ROMPATCHENL; /**< Enable Register Low, offset: 0xFC */ __IO uint32_t ROMPATCHA[32]; /**< Address Registers, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_1[136]; __IO uint32_t ROMPATCHSR; /**< Status Register, offset: 0x208 */ } WAKEUP_ROMCP_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_ROMCP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_ROMCP_Register_Masks WAKEUP_ROMCP Register Masks * @{ */ /*! @name ROMPATCHD - Data Registers */ /*! @{ */ #define WAKEUP_ROMCP_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) #define WAKEUP_ROMCP_ROMPATCHD_DATAX_SHIFT (0U) /*! DATAX - Data Fix Registers */ #define WAKEUP_ROMCP_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHD_DATAX_SHIFT)) & WAKEUP_ROMCP_ROMPATCHD_DATAX_MASK) /*! @} */ /* The count of WAKEUP_ROMCP_ROMPATCHD */ #define WAKEUP_ROMCP_ROMPATCHD_COUNT (16U) /*! @name ROMPATCHCNTL - Control Register */ /*! @{ */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX0_MASK (0x1U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT (0U) /*! DATAFIX0 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX0_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX0_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX1_MASK (0x2U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT (1U) /*! DATAFIX1 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX1_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX1_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX2_MASK (0x4U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT (2U) /*! DATAFIX2 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX2_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX2_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX3_MASK (0x8U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT (3U) /*! DATAFIX3 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX3(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX3_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX3_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX4_MASK (0x10U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT (4U) /*! DATAFIX4 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX4(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX4_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX4_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX5_MASK (0x20U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT (5U) /*! DATAFIX5 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX5(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX5_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX5_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX6_MASK (0x40U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT (6U) /*! DATAFIX6 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX6(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX6_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX6_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX7_MASK (0x80U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT (7U) /*! DATAFIX7 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX7(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX7_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX7_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX8_MASK (0x100U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX8_SHIFT (8U) /*! DATAFIX8 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX8(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX8_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX8_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX9_MASK (0x200U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX9_SHIFT (9U) /*! DATAFIX9 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX9(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX9_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX9_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX10_MASK (0x400U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX10_SHIFT (10U) /*! DATAFIX10 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX10(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX10_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX10_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX11_MASK (0x800U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX11_SHIFT (11U) /*! DATAFIX11 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX11(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX11_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX11_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX12_MASK (0x1000U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX12_SHIFT (12U) /*! DATAFIX12 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX12(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX12_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX12_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX13_MASK (0x2000U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX13_SHIFT (13U) /*! DATAFIX13 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX13(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX13_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX13_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX14_MASK (0x4000U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX14_SHIFT (14U) /*! DATAFIX14 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX14(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX14_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX14_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX15_MASK (0x8000U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX15_SHIFT (15U) /*! DATAFIX15 - Data Fix Enable * 0b0..Trigger an opcode patch * 0b1..Trigger a data fix */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX15(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX15_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DATAFIX15_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_DIS_MASK (0x20000000U) #define WAKEUP_ROMCP_ROMPATCHCNTL_DIS_SHIFT (29U) /*! DIS - Patch Disable * 0b0..Does not affect any Patch operations (default) * 0b1..Disables all Patch operations: data fixing and opcode patching */ #define WAKEUP_ROMCP_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_DIS_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_DIS_MASK) #define WAKEUP_ROMCP_ROMPATCHCNTL_LK_MASK (0x80000000U) #define WAKEUP_ROMCP_ROMPATCHCNTL_LK_SHIFT (31U) /*! LK - Register Lock * 0b0..All registers remain accessible (unlocked). * 0b1..Lock access to all registers. All ROMCP register accesses are treated as read-as-zero, except for this LK * bit which reads as set. All writes are ignored. */ #define WAKEUP_ROMCP_ROMPATCHCNTL_LK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHCNTL_LK_SHIFT)) & WAKEUP_ROMCP_ROMPATCHCNTL_LK_MASK) /*! @} */ /*! @name ROMPATCHENL - Enable Register Low */ /*! @{ */ #define WAKEUP_ROMCP_ROMPATCHENL_ENABLE_MASK (0xFFFFFFFFU) #define WAKEUP_ROMCP_ROMPATCHENL_ENABLE_SHIFT (0U) /*! ENABLE - Enable Address Comparator * 0b00000000000000000000000000000000..Address comparator is disabled * 0b00000000000000000000000000000001..Address comparator is enabled; after the associated address is matched, the ROMC will trigger a opcode patch or data fix event. */ #define WAKEUP_ROMCP_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHENL_ENABLE_SHIFT)) & WAKEUP_ROMCP_ROMPATCHENL_ENABLE_MASK) /*! @} */ /*! @name ROMPATCHA - Address Registers */ /*! @{ */ #define WAKEUP_ROMCP_ROMPATCHA_THUMBX_MASK (0x1U) #define WAKEUP_ROMCP_ROMPATCHA_THUMBX_SHIFT (0U) /*! THUMBX - THUMB Comparator Select * 0b0..ARM patch * 0b1..THUMB patch (ignore if a data fix) */ #define WAKEUP_ROMCP_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHA_THUMBX_SHIFT)) & WAKEUP_ROMCP_ROMPATCHA_THUMBX_MASK) #define WAKEUP_ROMCP_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) #define WAKEUP_ROMCP_ROMPATCHA_ADDRX_SHIFT (1U) /*! ADDRX - Address Comparator Registers */ #define WAKEUP_ROMCP_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHA_ADDRX_SHIFT)) & WAKEUP_ROMCP_ROMPATCHA_ADDRX_MASK) /*! @} */ /* The count of WAKEUP_ROMCP_ROMPATCHA */ #define WAKEUP_ROMCP_ROMPATCHA_COUNT (32U) /*! @name ROMPATCHSR - Status Register */ /*! @{ */ #define WAKEUP_ROMCP_ROMPATCHSR_SOURCE_MASK (0x3FU) #define WAKEUP_ROMCP_ROMPATCHSR_SOURCE_SHIFT (0U) /*! SOURCE - ROMCP Source Number * 0b000000..Address Comparator 0 matched * 0b000001..Address Comparator 1 matched * 0b001111..Address Comparator 15 matched */ #define WAKEUP_ROMCP_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHSR_SOURCE_SHIFT)) & WAKEUP_ROMCP_ROMPATCHSR_SOURCE_MASK) #define WAKEUP_ROMCP_ROMPATCHSR_SW_MASK (0x20000U) #define WAKEUP_ROMCP_ROMPATCHSR_SW_SHIFT (17U) /*! SW - ROMCP AHB Multiple Address Comparator Match Indicator * 0b0..No event or comparator collisions have occurred * 0b1..A collision has occurred */ #define WAKEUP_ROMCP_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_ROMCP_ROMPATCHSR_SW_SHIFT)) & WAKEUP_ROMCP_ROMPATCHSR_SW_MASK) /*! @} */ /*! * @} */ /* end of group WAKEUP_ROMCP_Register_Masks */ /* WAKEUP_ROMCP - Peripheral instance base addresses */ /** Peripheral WAKEUP__ROMCP2 base address */ #define WAKEUP__ROMCP2_BASE (0x42640000u) /** Peripheral WAKEUP__ROMCP2 base pointer */ #define WAKEUP__ROMCP2 ((WAKEUP_ROMCP_Type *)WAKEUP__ROMCP2_BASE) /** Array initializer of WAKEUP_ROMCP peripheral base addresses */ #define WAKEUP_ROMCP_BASE_ADDRS { WAKEUP__ROMCP2_BASE } /** Array initializer of WAKEUP_ROMCP peripheral base pointers */ #define WAKEUP_ROMCP_BASE_PTRS { WAKEUP__ROMCP2 } /*! * @} */ /* end of group WAKEUP_ROMCP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_USDHC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_USDHC_Peripheral_Access_Layer WAKEUP_USDHC Peripheral Access Layer * @{ */ /** WAKEUP_USDHC - Register Layout Typedef */ typedef struct { __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ uint8_t RESERVED_0[4]; __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ uint8_t RESERVED_1[4]; __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ uint8_t RESERVED_2[4]; __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */ __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */ uint8_t RESERVED_3[72]; __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ __IO uint32_t MMC_BOOT; /**< eMMC Boot, offset: 0xC4 */ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ uint8_t RESERVED_4[48]; __I uint32_t CQVER; /**< Command Queuing Version, offset: 0x100 */ __IO uint32_t CQCAP; /**< Command Queuing Capabilities, offset: 0x104 */ __IO uint32_t CQCFG; /**< Command Queuing Configuration, offset: 0x108 */ __IO uint32_t CQCTL; /**< Command Queuing Control, offset: 0x10C */ __IO uint32_t CQIS; /**< Command Queuing Interrupt Status, offset: 0x110 */ __IO uint32_t CQISTE; /**< Command Queuing Interrupt Status Enable, offset: 0x114 */ __IO uint32_t CQISGE; /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */ __IO uint32_t CQIC; /**< Command Queuing Interrupt Coalescing, offset: 0x11C */ __IO uint32_t CQTDLBA; /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */ __IO uint32_t CQTDLBAU; /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */ __IO uint32_t CQTDBR; /**< Command Queuing Task Doorbell, offset: 0x128 */ __IO uint32_t CQTCN; /**< Command Queuing Task Completion Notification, offset: 0x12C */ __I uint32_t CQDQS; /**< Command Queuing Device Queue Status, offset: 0x130 */ __I uint32_t CQDPT; /**< Command Queuing Device Pending Tasks, offset: 0x134 */ __IO uint32_t CQTCLR; /**< Command Queuing Task Clear, offset: 0x138 */ uint8_t RESERVED_5[4]; __IO uint32_t CQSSC1; /**< Command Queuing Send Status Configuration 1, offset: 0x140 */ __IO uint32_t CQSSC2; /**< Command Queuing Send Status Configuration 2, offset: 0x144 */ __I uint32_t CQCRDCT; /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */ uint8_t RESERVED_6[4]; __IO uint32_t CQRMEM; /**< Command Queuing Response Mode Error Mask, offset: 0x150 */ __I uint32_t CQTERRI; /**< Command Queuing Task Error Information, offset: 0x154 */ __I uint32_t CQCRI; /**< Command Queuing Command Response Index, offset: 0x158 */ __I uint32_t CQCRA; /**< Command Queuing Command Response Argument, offset: 0x15C */ } WAKEUP_USDHC_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_USDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_USDHC_Register_Masks WAKEUP_USDHC Register Masks * @{ */ /*! @name DS_ADDR - DMA System Address */ /*! @{ */ #define WAKEUP_USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) /*! DS_ADDR - System address */ #define WAKEUP_USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DS_ADDR_DS_ADDR_SHIFT)) & WAKEUP_USDHC_DS_ADDR_DS_ADDR_MASK) /*! @} */ /*! @name BLK_ATT - Block Attributes */ /*! @{ */ #define WAKEUP_USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define WAKEUP_USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) /*! BLKSIZE - Transfer block size * 0b1000000000000..4096 bytes * 0b0100000000000..2048 bytes * 0b0001000000000..512 bytes * 0b0000111111111..511 bytes * 0b0000000000100..4 bytes * 0b0000000000011..3 bytes * 0b0000000000010..2 bytes * 0b0000000000001..1 byte * 0b0000000000000..No data transfer */ #define WAKEUP_USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_BLK_ATT_BLKSIZE_SHIFT)) & WAKEUP_USDHC_BLK_ATT_BLKSIZE_MASK) #define WAKEUP_USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define WAKEUP_USDHC_BLK_ATT_BLKCNT_SHIFT (16U) /*! BLKCNT - Blocks count for current transfer * 0b1111111111111111..65535 blocks * 0b0000000000000010..2 blocks * 0b0000000000000001..1 block * 0b0000000000000000..Stop count */ #define WAKEUP_USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_BLK_ATT_BLKCNT_SHIFT)) & WAKEUP_USDHC_BLK_ATT_BLKCNT_MASK) /*! @} */ /*! @name CMD_ARG - Command Argument */ /*! @{ */ #define WAKEUP_USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CMD_ARG_CMDARG_SHIFT (0U) /*! CMDARG - Command argument */ #define WAKEUP_USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_ARG_CMDARG_SHIFT)) & WAKEUP_USDHC_CMD_ARG_CMDARG_MASK) /*! @} */ /*! @name CMD_XFR_TYP - Command Transfer Type */ /*! @{ */ #define WAKEUP_USDHC_CMD_XFR_TYP_DMAEN_MASK (0x1U) #define WAKEUP_USDHC_CMD_XFR_TYP_DMAEN_SHIFT (0U) /*! DMAEN - DMAEN * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_DMAEN_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_BCEN_MASK (0x2U) #define WAKEUP_USDHC_CMD_XFR_TYP_BCEN_SHIFT (1U) /*! BCEN - BCEN * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_BCEN_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_AC12EN_MASK (0x4U) #define WAKEUP_USDHC_CMD_XFR_TYP_AC12EN_SHIFT (2U) /*! AC12EN - AC12EN * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_AC12EN_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_DDR_EN_MASK (0x8U) #define WAKEUP_USDHC_CMD_XFR_TYP_DDR_EN_SHIFT (3U) /*! DDR_EN - DDR_EN * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_DDR_EN_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_DTDSEL_MASK (0x10U) #define WAKEUP_USDHC_CMD_XFR_TYP_DTDSEL_SHIFT (4U) /*! DTDSEL - DTDSEL * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_DTDSEL_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_MSBSEL_MASK (0x20U) #define WAKEUP_USDHC_CMD_XFR_TYP_MSBSEL_SHIFT (5U) /*! MSBSEL - MSBSEL * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_MSBSEL_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK (0x40U) #define WAKEUP_USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT (6U) /*! NIBBLE_POS - NIBBLE_POS * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_AC23EN_MASK (0x80U) #define WAKEUP_USDHC_CMD_XFR_TYP_AC23EN_SHIFT (7U) /*! AC23EN - AC23EN * 0b0..Disable * 0b1..Enable */ #define WAKEUP_USDHC_CMD_XFR_TYP_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_AC23EN_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define WAKEUP_USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) /*! RSPTYP - Response type select * 0b00..No response * 0b01..Response length 136 * 0b10..Response length 48 * 0b11..Response length 48, check busy after response */ #define WAKEUP_USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_RSPTYP_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define WAKEUP_USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) /*! CCCEN - Command CRC check enable * 0b1..Enables command CRC check * 0b0..Disables command CRC check */ #define WAKEUP_USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_CCCEN_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define WAKEUP_USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) /*! CICEN - Command index check enable * 0b1..Enables command index check * 0b0..Disable command index check */ #define WAKEUP_USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_CICEN_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define WAKEUP_USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) /*! DPSEL - Data present select * 0b1..Data present * 0b0..No data present */ #define WAKEUP_USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_DPSEL_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define WAKEUP_USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) /*! CMDTYP - Command type * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR * 0b10..Resume CMD52 for writing function select in CCCR * 0b01..Suspend CMD52 for writing bus suspend in CCCR * 0b00..Normal other commands */ #define WAKEUP_USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_CMDTYP_MASK) #define WAKEUP_USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define WAKEUP_USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) /*! CMDINX - Command index */ #define WAKEUP_USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & WAKEUP_USDHC_CMD_XFR_TYP_CMDINX_MASK) /*! @} */ /*! @name CMD_RSP0 - Command Response0 */ /*! @{ */ #define WAKEUP_USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) /*! CMDRSP0 - Command response 0 */ #define WAKEUP_USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & WAKEUP_USDHC_CMD_RSP0_CMDRSP0_MASK) /*! @} */ /*! @name CMD_RSP1 - Command Response1 */ /*! @{ */ #define WAKEUP_USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) /*! CMDRSP1 - Command response 1 */ #define WAKEUP_USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & WAKEUP_USDHC_CMD_RSP1_CMDRSP1_MASK) /*! @} */ /*! @name CMD_RSP2 - Command Response2 */ /*! @{ */ #define WAKEUP_USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) /*! CMDRSP2 - Command response 2 */ #define WAKEUP_USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & WAKEUP_USDHC_CMD_RSP2_CMDRSP2_MASK) /*! @} */ /*! @name CMD_RSP3 - Command Response3 */ /*! @{ */ #define WAKEUP_USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) /*! CMDRSP3 - Command response 3 */ #define WAKEUP_USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & WAKEUP_USDHC_CMD_RSP3_CMDRSP3_MASK) /*! @} */ /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ /*! @{ */ #define WAKEUP_USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) /*! DATCONT - Data content */ #define WAKEUP_USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & WAKEUP_USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) /*! @} */ /*! @name PRES_STATE - Present State */ /*! @{ */ #define WAKEUP_USDHC_PRES_STATE_CIHB_MASK (0x1U) #define WAKEUP_USDHC_PRES_STATE_CIHB_SHIFT (0U) /*! CIHB - Command inhibit (CMD) * 0b1..Cannot issue command * 0b0..Can issue command using only CMD line */ #define WAKEUP_USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_CIHB_SHIFT)) & WAKEUP_USDHC_PRES_STATE_CIHB_MASK) #define WAKEUP_USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define WAKEUP_USDHC_PRES_STATE_CDIHB_SHIFT (1U) /*! CDIHB - Command Inhibit Data (DATA) * 0b1..Cannot issue command that uses the DATA line * 0b0..Can issue command that uses the DATA line */ #define WAKEUP_USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_CDIHB_SHIFT)) & WAKEUP_USDHC_PRES_STATE_CDIHB_MASK) #define WAKEUP_USDHC_PRES_STATE_DLA_MASK (0x4U) #define WAKEUP_USDHC_PRES_STATE_DLA_SHIFT (2U) /*! DLA - Data line active * 0b1..DATA line active * 0b0..DATA line inactive */ #define WAKEUP_USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_DLA_SHIFT)) & WAKEUP_USDHC_PRES_STATE_DLA_MASK) #define WAKEUP_USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define WAKEUP_USDHC_PRES_STATE_SDSTB_SHIFT (3U) /*! SDSTB - SD clock stable * 0b1..Clock is stable. * 0b0..Clock is changing frequency and not stable. */ #define WAKEUP_USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_SDSTB_SHIFT)) & WAKEUP_USDHC_PRES_STATE_SDSTB_MASK) #define WAKEUP_USDHC_PRES_STATE_WTA_MASK (0x100U) #define WAKEUP_USDHC_PRES_STATE_WTA_SHIFT (8U) /*! WTA - Write transfer active * 0b1..Transferring data * 0b0..No valid data */ #define WAKEUP_USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_WTA_SHIFT)) & WAKEUP_USDHC_PRES_STATE_WTA_MASK) #define WAKEUP_USDHC_PRES_STATE_RTA_MASK (0x200U) #define WAKEUP_USDHC_PRES_STATE_RTA_SHIFT (9U) /*! RTA - Read transfer active * 0b1..Transferring data * 0b0..No valid data */ #define WAKEUP_USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_RTA_SHIFT)) & WAKEUP_USDHC_PRES_STATE_RTA_MASK) #define WAKEUP_USDHC_PRES_STATE_BWEN_MASK (0x400U) #define WAKEUP_USDHC_PRES_STATE_BWEN_SHIFT (10U) /*! BWEN - Buffer write enable * 0b1..Write enable * 0b0..Write disable */ #define WAKEUP_USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_BWEN_SHIFT)) & WAKEUP_USDHC_PRES_STATE_BWEN_MASK) #define WAKEUP_USDHC_PRES_STATE_BREN_MASK (0x800U) #define WAKEUP_USDHC_PRES_STATE_BREN_SHIFT (11U) /*! BREN - Buffer read enable * 0b1..Read enable * 0b0..Read disable */ #define WAKEUP_USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_BREN_SHIFT)) & WAKEUP_USDHC_PRES_STATE_BREN_MASK) #define WAKEUP_USDHC_PRES_STATE_RTR_MASK (0x1000U) #define WAKEUP_USDHC_PRES_STATE_RTR_SHIFT (12U) /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode, and eMMC HS200 mode) * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock */ #define WAKEUP_USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_RTR_SHIFT)) & WAKEUP_USDHC_PRES_STATE_RTR_MASK) #define WAKEUP_USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define WAKEUP_USDHC_PRES_STATE_TSCD_SHIFT (15U) /*! TSCD - Tap select change done * 0b1..Delay cell select change is finished. * 0b0..Delay cell select change is not finished. */ #define WAKEUP_USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_TSCD_SHIFT)) & WAKEUP_USDHC_PRES_STATE_TSCD_MASK) #define WAKEUP_USDHC_PRES_STATE_CINST_MASK (0x10000U) #define WAKEUP_USDHC_PRES_STATE_CINST_SHIFT (16U) /*! CINST - Card inserted * 0b1..Card inserted * 0b0..Power on reset or no card */ #define WAKEUP_USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_CINST_SHIFT)) & WAKEUP_USDHC_PRES_STATE_CINST_MASK) #define WAKEUP_USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define WAKEUP_USDHC_PRES_STATE_CDPL_SHIFT (18U) /*! CDPL - Card detect pin level * 0b1..Card present (CD_B = 0) * 0b0..No card present (CD_B = 1) */ #define WAKEUP_USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_CDPL_SHIFT)) & WAKEUP_USDHC_PRES_STATE_CDPL_MASK) #define WAKEUP_USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define WAKEUP_USDHC_PRES_STATE_WPSPL_SHIFT (19U) /*! WPSPL - Write protect switch pin level * 0b1..Write enabled (WP = 0) * 0b0..Write protected (WP = 1) */ #define WAKEUP_USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_WPSPL_SHIFT)) & WAKEUP_USDHC_PRES_STATE_WPSPL_MASK) #define WAKEUP_USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define WAKEUP_USDHC_PRES_STATE_CLSL_SHIFT (23U) /*! CLSL - CMD line signal level */ #define WAKEUP_USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_CLSL_SHIFT)) & WAKEUP_USDHC_PRES_STATE_CLSL_MASK) #define WAKEUP_USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define WAKEUP_USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level * 0b00000111..Data 7 line signal level * 0b00000110..Data 6 line signal level * 0b00000101..Data 5 line signal level * 0b00000100..Data 4 line signal level * 0b00000011..Data 3 line signal level * 0b00000010..Data 2 line signal level * 0b00000001..Data 1 line signal level * 0b00000000..Data 0 line signal level */ #define WAKEUP_USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PRES_STATE_DLSL_SHIFT)) & WAKEUP_USDHC_PRES_STATE_DLSL_MASK) /*! @} */ /*! @name PROT_CTRL - Protocol Control */ /*! @{ */ #define WAKEUP_USDHC_PROT_CTRL_DTW_MASK (0x6U) #define WAKEUP_USDHC_PROT_CTRL_DTW_SHIFT (1U) /*! DTW - Data transfer width * 0b10..8-bit mode * 0b01..4-bit mode * 0b00..1-bit mode * 0b11..Reserved */ #define WAKEUP_USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_DTW_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_DTW_MASK) #define WAKEUP_USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define WAKEUP_USDHC_PROT_CTRL_D3CD_SHIFT (3U) /*! D3CD - DATA3 as card detection pin * 0b1..DATA3 as card detection pin * 0b0..DATA3 does not monitor card insertion */ #define WAKEUP_USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_D3CD_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_D3CD_MASK) #define WAKEUP_USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define WAKEUP_USDHC_PROT_CTRL_EMODE_SHIFT (4U) /*! EMODE - Endian mode * 0b00..Big endian mode * 0b01..Half word big endian mode * 0b10..Little endian mode * 0b11..Reserved */ #define WAKEUP_USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_EMODE_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_EMODE_MASK) #define WAKEUP_USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define WAKEUP_USDHC_PROT_CTRL_DMASEL_SHIFT (8U) /*! DMASEL - DMA select * 0b00..No DMA or simple DMA is selected. * 0b01..ADMA1 is selected. * 0b10..ADMA2 is selected. * 0b11..Reserved */ #define WAKEUP_USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_DMASEL_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_DMASEL_MASK) #define WAKEUP_USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define WAKEUP_USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) /*! SABGREQ - Stop at block gap request * 0b1..Stop * 0b0..Transfer */ #define WAKEUP_USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_SABGREQ_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_SABGREQ_MASK) #define WAKEUP_USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define WAKEUP_USDHC_PROT_CTRL_CREQ_SHIFT (17U) /*! CREQ - Continue request * 0b1..Restart * 0b0..No effect */ #define WAKEUP_USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_CREQ_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_CREQ_MASK) #define WAKEUP_USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define WAKEUP_USDHC_PROT_CTRL_RWCTL_SHIFT (18U) /*! RWCTL - Read wait control * 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set */ #define WAKEUP_USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_RWCTL_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_RWCTL_MASK) #define WAKEUP_USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define WAKEUP_USDHC_PROT_CTRL_IABG_SHIFT (19U) /*! IABG - Interrupt at block gap * 0b1..Enables interrupt at block gap * 0b0..Disables interrupt at block gap */ #define WAKEUP_USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_IABG_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_IABG_MASK) #define WAKEUP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define WAKEUP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) /*! RD_DONE_NO_8CLK - Read performed number 8 clock */ #define WAKEUP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) #define WAKEUP_USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define WAKEUP_USDHC_PROT_CTRL_WECINT_SHIFT (24U) /*! WECINT - Wakeup event enable on card interrupt * 0b1..Enables wakeup event enable on card interrupt * 0b0..Disables wakeup event enable on card interrupt */ #define WAKEUP_USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_WECINT_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_WECINT_MASK) #define WAKEUP_USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define WAKEUP_USDHC_PROT_CTRL_WECINS_SHIFT (25U) /*! WECINS - Wakeup event enable on SD card insertion * 0b1..Enable wakeup event enable on SD card insertion * 0b0..Disable wakeup event enable on SD card insertion */ #define WAKEUP_USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_WECINS_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_WECINS_MASK) #define WAKEUP_USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define WAKEUP_USDHC_PROT_CTRL_WECRM_SHIFT (26U) /*! WECRM - Wakeup event enable on SD card removal * 0b1..Enables wakeup event enable on SD card removal * 0b0..Disables wakeup event enable on SD card removal */ #define WAKEUP_USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_WECRM_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_WECRM_MASK) #define WAKEUP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define WAKEUP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) /*! NON_EXACT_BLK_RD - Non-exact block read * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. * 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read. */ #define WAKEUP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & WAKEUP_USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) /*! @} */ /*! @name SYS_CTRL - System Control */ /*! @{ */ #define WAKEUP_USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define WAKEUP_USDHC_SYS_CTRL_DVS_SHIFT (4U) /*! DVS - Divisor * 0b0000..Divide-by-1 * 0b0001..Divide-by-2 * 0b1110..Divide-by-15 * 0b1111..Divide-by-16 */ #define WAKEUP_USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_DVS_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_DVS_MASK) #define WAKEUP_USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define WAKEUP_USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) /*! SDCLKFS - SDCLK frequency select */ #define WAKEUP_USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_SDCLKFS_MASK) #define WAKEUP_USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define WAKEUP_USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value * 0b1111..SDCLK x 2 31, recommend to use for HS400 mode * 0b1110..SDCLK x 2 30, recommend to use for HS200 and SDR104 mode * 0b1101..SDCLK x 2 29, recommend to use for supported speed modes except HS200, HS400, SDR104 mode * 0b0011..SDCLK x 2 19 * 0b0010..SDCLK x 2 18 * 0b0001..SDCLK x 2 33 * 0b0000..SDCLK x 2 32 */ #define WAKEUP_USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_DTOCV_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_DTOCV_MASK) #define WAKEUP_USDHC_SYS_CTRL_RST_FIFO_MASK (0x400000U) #define WAKEUP_USDHC_SYS_CTRL_RST_FIFO_SHIFT (22U) /*! RST_FIFO - Reset the async FIFO */ #define WAKEUP_USDHC_SYS_CTRL_RST_FIFO(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_RST_FIFO_MASK) #define WAKEUP_USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define WAKEUP_USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) /*! IPP_RST_N - Hardware reset */ #define WAKEUP_USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_IPP_RST_N_MASK) #define WAKEUP_USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define WAKEUP_USDHC_SYS_CTRL_RSTA_SHIFT (24U) /*! RSTA - Software reset for all * 0b1..Reset * 0b0..No reset */ #define WAKEUP_USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_RSTA_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_RSTA_MASK) #define WAKEUP_USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define WAKEUP_USDHC_SYS_CTRL_RSTC_SHIFT (25U) /*! RSTC - Software reset for CMD line * 0b1..Reset * 0b0..No reset */ #define WAKEUP_USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_RSTC_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_RSTC_MASK) #define WAKEUP_USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define WAKEUP_USDHC_SYS_CTRL_RSTD_SHIFT (26U) /*! RSTD - Software reset for data line * 0b1..Reset * 0b0..No reset */ #define WAKEUP_USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_RSTD_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_RSTD_MASK) #define WAKEUP_USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define WAKEUP_USDHC_SYS_CTRL_INITA_SHIFT (27U) /*! INITA - Initialization active */ #define WAKEUP_USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_INITA_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_INITA_MASK) #define WAKEUP_USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define WAKEUP_USDHC_SYS_CTRL_RSTT_SHIFT (28U) /*! RSTT - Reset tuning */ #define WAKEUP_USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_SYS_CTRL_RSTT_SHIFT)) & WAKEUP_USDHC_SYS_CTRL_RSTT_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ #define WAKEUP_USDHC_INT_STATUS_CC_MASK (0x1U) #define WAKEUP_USDHC_INT_STATUS_CC_SHIFT (0U) /*! CC - Command complete * 0b1..Command complete * 0b0..Command not complete */ #define WAKEUP_USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CC_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CC_MASK) #define WAKEUP_USDHC_INT_STATUS_TC_MASK (0x2U) #define WAKEUP_USDHC_INT_STATUS_TC_SHIFT (1U) /*! TC - Transfer complete * 0b1..Transfer complete * 0b0..Transfer does not complete */ #define WAKEUP_USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_TC_SHIFT)) & WAKEUP_USDHC_INT_STATUS_TC_MASK) #define WAKEUP_USDHC_INT_STATUS_BGE_MASK (0x4U) #define WAKEUP_USDHC_INT_STATUS_BGE_SHIFT (2U) /*! BGE - Block gap event * 0b1..Transaction stopped at block gap * 0b0..No block gap event */ #define WAKEUP_USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_BGE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_BGE_MASK) #define WAKEUP_USDHC_INT_STATUS_DINT_MASK (0x8U) #define WAKEUP_USDHC_INT_STATUS_DINT_SHIFT (3U) /*! DINT - DMA interrupt * 0b1..DMA interrupt is generated. * 0b0..No DMA interrupt */ #define WAKEUP_USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_DINT_SHIFT)) & WAKEUP_USDHC_INT_STATUS_DINT_MASK) #define WAKEUP_USDHC_INT_STATUS_BWR_MASK (0x10U) #define WAKEUP_USDHC_INT_STATUS_BWR_SHIFT (4U) /*! BWR - Buffer write ready * 0b1..Ready to write buffer * 0b0..Not ready to write buffer */ #define WAKEUP_USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_BWR_SHIFT)) & WAKEUP_USDHC_INT_STATUS_BWR_MASK) #define WAKEUP_USDHC_INT_STATUS_BRR_MASK (0x20U) #define WAKEUP_USDHC_INT_STATUS_BRR_SHIFT (5U) /*! BRR - Buffer read ready * 0b1..Ready to read buffer * 0b0..Not ready to read buffer */ #define WAKEUP_USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_BRR_SHIFT)) & WAKEUP_USDHC_INT_STATUS_BRR_MASK) #define WAKEUP_USDHC_INT_STATUS_CINS_MASK (0x40U) #define WAKEUP_USDHC_INT_STATUS_CINS_SHIFT (6U) /*! CINS - Card insertion * 0b1..Card inserted * 0b0..Card state unstable or removed */ #define WAKEUP_USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CINS_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CINS_MASK) #define WAKEUP_USDHC_INT_STATUS_CRM_MASK (0x80U) #define WAKEUP_USDHC_INT_STATUS_CRM_SHIFT (7U) /*! CRM - Card removal * 0b1..Card removed * 0b0..Card state unstable or inserted */ #define WAKEUP_USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CRM_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CRM_MASK) #define WAKEUP_USDHC_INT_STATUS_CINT_MASK (0x100U) #define WAKEUP_USDHC_INT_STATUS_CINT_SHIFT (8U) /*! CINT - Card interrupt * 0b1..Generate card interrupt * 0b0..No card interrupt */ #define WAKEUP_USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CINT_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CINT_MASK) #define WAKEUP_USDHC_INT_STATUS_RTE_MASK (0x1000U) #define WAKEUP_USDHC_INT_STATUS_RTE_SHIFT (12U) /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and eMMC HS200 mode) * 0b1..Re-tuning should be performed. * 0b0..Re-tuning is not required. */ #define WAKEUP_USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_RTE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_RTE_MASK) #define WAKEUP_USDHC_INT_STATUS_TP_MASK (0x2000U) #define WAKEUP_USDHC_INT_STATUS_TP_SHIFT (13U) /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and eMMC HS200 mode) */ #define WAKEUP_USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_TP_SHIFT)) & WAKEUP_USDHC_INT_STATUS_TP_MASK) #define WAKEUP_USDHC_INT_STATUS_CQI_MASK (0x4000U) #define WAKEUP_USDHC_INT_STATUS_CQI_SHIFT (14U) /*! CQI - Command queuing interrupt */ #define WAKEUP_USDHC_INT_STATUS_CQI(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CQI_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CQI_MASK) #define WAKEUP_USDHC_INT_STATUS_ERR_INT_STATUS_MASK (0x8000U) #define WAKEUP_USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT (15U) /*! ERR_INT_STATUS - Error Interrupt Status */ #define WAKEUP_USDHC_INT_STATUS_ERR_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & WAKEUP_USDHC_INT_STATUS_ERR_INT_STATUS_MASK) #define WAKEUP_USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define WAKEUP_USDHC_INT_STATUS_CTOE_SHIFT (16U) /*! CTOE - Command timeout error * 0b1..Time out * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CTOE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CTOE_MASK) #define WAKEUP_USDHC_INT_STATUS_CCE_MASK (0x20000U) #define WAKEUP_USDHC_INT_STATUS_CCE_SHIFT (17U) /*! CCE - Command CRC error * 0b1..CRC error generated * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CCE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CCE_MASK) #define WAKEUP_USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define WAKEUP_USDHC_INT_STATUS_CEBE_SHIFT (18U) /*! CEBE - Command end bit error * 0b1..End bit error generated * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CEBE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CEBE_MASK) #define WAKEUP_USDHC_INT_STATUS_CIE_MASK (0x80000U) #define WAKEUP_USDHC_INT_STATUS_CIE_SHIFT (19U) /*! CIE - Command index error * 0b1..Error * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_CIE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_CIE_MASK) #define WAKEUP_USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define WAKEUP_USDHC_INT_STATUS_DTOE_SHIFT (20U) /*! DTOE - Data timeout error * 0b1..Time out * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_DTOE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_DTOE_MASK) #define WAKEUP_USDHC_INT_STATUS_DCE_MASK (0x200000U) #define WAKEUP_USDHC_INT_STATUS_DCE_SHIFT (21U) /*! DCE - Data CRC error * 0b1..Error * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_DCE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_DCE_MASK) #define WAKEUP_USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define WAKEUP_USDHC_INT_STATUS_DEBE_SHIFT (22U) /*! DEBE - Data end bit error * 0b1..Error * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_DEBE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_DEBE_MASK) #define WAKEUP_USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define WAKEUP_USDHC_INT_STATUS_AC12E_SHIFT (24U) /*! AC12E - Auto CMD12 error * 0b1..Error * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_AC12E_SHIFT)) & WAKEUP_USDHC_INT_STATUS_AC12E_MASK) #define WAKEUP_USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define WAKEUP_USDHC_INT_STATUS_TNE_SHIFT (26U) /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and eMMC HS200 mode) */ #define WAKEUP_USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_TNE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_TNE_MASK) #define WAKEUP_USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define WAKEUP_USDHC_INT_STATUS_DMAE_SHIFT (28U) /*! DMAE - DMA error * 0b1..Error * 0b0..No error */ #define WAKEUP_USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_DMAE_SHIFT)) & WAKEUP_USDHC_INT_STATUS_DMAE_MASK) /*! @} */ /*! @name INT_STATUS_EN - Interrupt Status Enable */ /*! @{ */ #define WAKEUP_USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define WAKEUP_USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) /*! CCSEN - Command complete status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CCSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define WAKEUP_USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) /*! TCSEN - Transfer complete status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_TCSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define WAKEUP_USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) /*! BGESEN - Block gap event status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_BGESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define WAKEUP_USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) /*! DINTSEN - DMA interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_DINTSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define WAKEUP_USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) /*! BWRSEN - Buffer write ready status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_BWRSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define WAKEUP_USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) /*! BRRSEN - Buffer read ready status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_BRRSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define WAKEUP_USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) /*! CINSSEN - Card insertion status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CINSSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define WAKEUP_USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) /*! CRMSEN - Card removal status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CRMSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define WAKEUP_USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) /*! CINTSEN - Card interrupt status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CINTSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define WAKEUP_USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) /*! RTESEN - Re-tuning event status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_RTESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U) #define WAKEUP_USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U) /*! TPSEN - Tuning pass status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_TPSEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U) #define WAKEUP_USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U) /*! CQISEN - Command queuing status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CQISEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define WAKEUP_USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) /*! CTOESEN - Command timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CTOESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define WAKEUP_USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) /*! CCESEN - Command CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CCESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define WAKEUP_USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) /*! CEBESEN - Command end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CEBESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define WAKEUP_USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) /*! CIESEN - Command index error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_CIESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define WAKEUP_USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) /*! DTOESEN - Data timeout error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_DTOESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define WAKEUP_USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) /*! DCESEN - Data CRC error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_DCESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define WAKEUP_USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) /*! DEBESEN - Data end bit error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_DEBESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define WAKEUP_USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) /*! AC12ESEN - Auto CMD12 error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_AC12ESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define WAKEUP_USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) /*! TNESEN - Tuning error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_TNESEN_MASK) #define WAKEUP_USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define WAKEUP_USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) /*! DMAESEN - DMA error status enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & WAKEUP_USDHC_INT_STATUS_EN_DMAESEN_MASK) /*! @} */ /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ /*! @{ */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) /*! CCIEN - Command complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CCIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define WAKEUP_USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) /*! TCIEN - Transfer complete interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_TCIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define WAKEUP_USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) /*! BGEIEN - Block gap event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_BGEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define WAKEUP_USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) /*! DINTIEN - DMA interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_DINTIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define WAKEUP_USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) /*! BWRIEN - Buffer write ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_BWRIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define WAKEUP_USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) /*! BRRIEN - Buffer read ready interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_BRRIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) /*! CINSIEN - Card insertion interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CINSIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) /*! CRMIEN - Card removal interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CRMIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) /*! CINTIEN - Card interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CINTIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) /*! RTEIEN - Re-tuning event interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_RTEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U) /*! TPIEN - Tuning pass interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_TPIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U) /*! CQIIEN - Command queuing signal enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CQIIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) /*! CTOEIEN - Command timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) /*! CCEIEN - Command CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CCEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) /*! CEBEIEN - Command end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) /*! CIEIEN - Command index error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_CIEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) /*! DTOEIEN - Data timeout error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) /*! DCEIEN - Data CRC error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_DCEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) /*! DEBEIEN - Data end bit error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) /*! AC12EIEN - Auto CMD12 error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) /*! TNEIEN - Tuning error interrupt enable * 0b1..Enabled * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_TNEIEN_MASK) #define WAKEUP_USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define WAKEUP_USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) /*! DMAEIEN - DMA error interrupt enable * 0b1..Enable * 0b0..Masked */ #define WAKEUP_USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & WAKEUP_USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) /*! @} */ /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ /*! @{ */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) /*! AC12NE - Auto CMD12 not executed * 0b1..Not executed * 0b0..Executed */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) /*! AC12TOE - Auto CMD12 / 23 timeout error * 0b1..Time out * 0b0..No error */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x4U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (2U) /*! AC12CE - Auto CMD12 / 23 CRC error * 0b1..CRC error met in Auto CMD12/23 response * 0b0..No CRC error */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x8U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U) /*! AC12EBE - Auto CMD12 / 23 end bit error * 0b1..End bit error generated * 0b0..No error */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) /*! AC12IE - Auto CMD12 / 23 index error * 0b1..Error, the CMD index in response is not CMD12/23 * 0b0..No error */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) /*! CNIBAC12E - Command not issued by Auto CMD12 error * 0b1..Not issued * 0b0..No error */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) /*! EXECUTE_TUNING - Execute tuning * 0b1..Start tuning procedure * 0b0..Tuning procedure is aborted */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Sample clock select * 0b1..Tuned clock is used to sample data * 0b0..Fixed clock is used to sample data */ #define WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & WAKEUP_USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) /*! @} */ /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ /*! @{ */ #define WAKEUP_USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define WAKEUP_USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) /*! SDR50_SUPPORT - SDR50 support */ #define WAKEUP_USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) #define WAKEUP_USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) /*! SDR104_SUPPORT - SDR104 support */ #define WAKEUP_USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) #define WAKEUP_USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) /*! DDR50_SUPPORT - DDR50 support */ #define WAKEUP_USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) /*! USE_TUNING_SDR50 - Use Tuning for SDR50 * 0b1..SDR50 supports tuning * 0b0..SDR50 does not support tuning */ #define WAKEUP_USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) /*! MBL - Max block length * 0b000..512 bytes * 0b001..1024 bytes * 0b010..2048 bytes * 0b011..4096 bytes */ #define WAKEUP_USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_MBL_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) /*! ADMAS - ADMA support * 0b1..Advanced DMA supported * 0b0..Advanced DMA not supported */ #define WAKEUP_USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_ADMAS_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) /*! HSS - High speed support * 0b1..High speed supported * 0b0..High speed not supported */ #define WAKEUP_USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_HSS_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) /*! DMAS - DMA support * 0b1..DMA supported * 0b0..DMA not supported */ #define WAKEUP_USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_DMAS_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) /*! SRS - Suspend / resume support * 0b1..Supported * 0b0..Not supported */ #define WAKEUP_USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_SRS_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) /*! VS33 - Voltage support 3.3 V * 0b1..3.3 V supported * 0b0..3.3 V not supported */ #define WAKEUP_USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_VS33_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) /*! VS30 - Voltage support 3.0 V * 0b1..3.0 V supported * 0b0..3.0 V not supported */ #define WAKEUP_USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_VS30_MASK) #define WAKEUP_USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define WAKEUP_USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) /*! VS18 - Voltage support 1.8 V * 0b1..1.8 V supported * 0b0..1.8 V not supported */ #define WAKEUP_USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & WAKEUP_USDHC_HOST_CTRL_CAP_VS18_MASK) /*! @} */ /*! @name WTMK_LVL - Watermark Level */ /*! @{ */ #define WAKEUP_USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define WAKEUP_USDHC_WTMK_LVL_RD_WML_SHIFT (0U) /*! RD_WML - Read watermark level */ #define WAKEUP_USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_WTMK_LVL_RD_WML_SHIFT)) & WAKEUP_USDHC_WTMK_LVL_RD_WML_MASK) #define WAKEUP_USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) #define WAKEUP_USDHC_WTMK_LVL_WR_WML_SHIFT (16U) /*! WR_WML - Write watermark level */ #define WAKEUP_USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_WTMK_LVL_WR_WML_SHIFT)) & WAKEUP_USDHC_WTMK_LVL_WR_WML_MASK) /*! @} */ /*! @name MIX_CTRL - Mixer Control */ /*! @{ */ #define WAKEUP_USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define WAKEUP_USDHC_MIX_CTRL_DMAEN_SHIFT (0U) /*! DMAEN - DMA enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_DMAEN_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_DMAEN_MASK) #define WAKEUP_USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define WAKEUP_USDHC_MIX_CTRL_BCEN_SHIFT (1U) /*! BCEN - Block count enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_BCEN_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_BCEN_MASK) #define WAKEUP_USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define WAKEUP_USDHC_MIX_CTRL_AC12EN_SHIFT (2U) /*! AC12EN - Auto CMD12 enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_AC12EN_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_AC12EN_MASK) #define WAKEUP_USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define WAKEUP_USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) /*! DDR_EN - Dual data rate mode selection */ #define WAKEUP_USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_DDR_EN_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_DDR_EN_MASK) #define WAKEUP_USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define WAKEUP_USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) /*! DTDSEL - Data transfer direction select * 0b1..Read (Card to host) * 0b0..Write (Host to card) */ #define WAKEUP_USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_DTDSEL_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_DTDSEL_MASK) #define WAKEUP_USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define WAKEUP_USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) /*! MSBSEL - Multi / Single block select * 0b1..Multiple blocks * 0b0..Single block */ #define WAKEUP_USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_MSBSEL_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_MSBSEL_MASK) #define WAKEUP_USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define WAKEUP_USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) /*! NIBBLE_POS - Nibble position indication */ #define WAKEUP_USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_NIBBLE_POS_MASK) #define WAKEUP_USDHC_MIX_CTRL_AC23EN_MASK (0x80U) #define WAKEUP_USDHC_MIX_CTRL_AC23EN_SHIFT (7U) /*! AC23EN - Auto CMD23 enable */ #define WAKEUP_USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_AC23EN_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_AC23EN_MASK) #define WAKEUP_USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define WAKEUP_USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) * 0b1..Execute tuning * 0b0..Not tuned or tuning completed */ #define WAKEUP_USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_EXE_TUNE_MASK) #define WAKEUP_USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define WAKEUP_USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Clock selection * 0b1..Tuned clock is used to sample data / cmd * 0b0..Fixed clock is used to sample data / cmd */ #define WAKEUP_USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) #define WAKEUP_USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define WAKEUP_USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) * 0b1..Enable auto tuning * 0b0..Disable auto tuning */ #define WAKEUP_USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) #define WAKEUP_USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define WAKEUP_USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and eMMC HS200 mode) * 0b1..Feedback clock comes from the ipp_card_clk_out * 0b0..Feedback clock comes from the loopback CLK */ #define WAKEUP_USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_FBCLK_SEL_MASK) #define WAKEUP_USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) #define WAKEUP_USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) /*! HS400_MODE - Enable HS400 mode */ #define WAKEUP_USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_HS400_MODE_MASK) #define WAKEUP_USDHC_MIX_CTRL_EN_HS400_MODE_MASK (0x8000000U) #define WAKEUP_USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT (27U) /*! EN_HS400_MODE - Enable enhance HS400 mode */ #define WAKEUP_USDHC_MIX_CTRL_EN_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & WAKEUP_USDHC_MIX_CTRL_EN_HS400_MODE_MASK) /*! @} */ /*! @name FORCE_EVENT - Force Event */ /*! @{ */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) /*! FEVTAC12NE - Force event auto command 12 not executed */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTAC12NE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) /*! FEVTAC12TOE - Force event auto command 12 time out error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) /*! FEVTAC12CE - Force event auto command 12 CRC error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTAC12CE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) /*! FEVTAC12IE - Force event Auto Command 12 index error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTAC12IE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) /*! FEVTCTOE - Force event command time out error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTCTOE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) /*! FEVTCCE - Force event command CRC error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTCCE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) /*! FEVTCEBE - Force event command end bit error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTCEBE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) /*! FEVTCIE - Force event command index error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTCIE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) /*! FEVTDTOE - Force event data time out error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTDTOE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) /*! FEVTDCE - Force event data CRC error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTDCE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) /*! FEVTDEBE - Force event data end bit error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTDEBE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) /*! FEVTAC12E - Force event Auto Command 12 error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTAC12E_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) /*! FEVTTNE - Force tuning error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTTNE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) /*! FEVTDMAE - Force event DMA error */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTDMAE_MASK) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define WAKEUP_USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) /*! FEVTCINT - Force event card interrupt */ #define WAKEUP_USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & WAKEUP_USDHC_FORCE_EVENT_FEVTCINT_MASK) /*! @} */ /*! @name ADMA_ERR_STATUS - ADMA Error Status */ /*! @{ */ #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) /*! ADMAES - ADMA error state (when ADMA error is occurred) */ #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & WAKEUP_USDHC_ADMA_ERR_STATUS_ADMAES_MASK) #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) /*! ADMALME - ADMA length mismatch error * 0b1..Error * 0b0..No error */ #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & WAKEUP_USDHC_ADMA_ERR_STATUS_ADMALME_MASK) #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) /*! ADMADCE - ADMA descriptor error * 0b1..Error * 0b0..No error */ #define WAKEUP_USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & WAKEUP_USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) /*! @} */ /*! @name ADMA_SYS_ADDR - ADMA System Address */ /*! @{ */ #define WAKEUP_USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define WAKEUP_USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) /*! ADS_ADDR - ADMA system address */ #define WAKEUP_USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & WAKEUP_USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) /*! @} */ /*! @name DLL_CTRL - DLL (Delay Line) Control */ /*! @{ */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) /*! DLL_CTRL_ENABLE - DLL and delay chain */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) /*! DLL_CTRL_RESET - DLL reset */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! DLL_CTRL_GATE_UPDATE - DLL gate update */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */ #define WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & WAKEUP_USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name DLL_STATUS - DLL Status */ /*! @{ */ #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */ #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) /*! DLL_STS_REF_LOCK - Reference DLL lock status */ #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) /*! DLL_STS_SLV_SEL - Slave delay line select status */ #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & WAKEUP_USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) /*! DLL_STS_REF_SEL - Reference delay line select taps */ #define WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & WAKEUP_USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ /*! @{ */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) /*! NXT_ERR - NXT error */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) /*! TAP_SEL_PRE - TAP_SEL_PRE */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) /*! PRE_ERR - PRE error */ #define WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & WAKEUP_USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) /*! @} */ /*! @name STROBE_DLL_CTRL - Strobe DLL control */ /*! @{ */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */ #define WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) /*! @} */ /*! @name STROBE_DLL_STATUS - Strobe DLL status */ /*! @{ */ #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */ #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */ #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */ #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */ #define WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & WAKEUP_USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) /*! @} */ /*! @name VEND_SPEC - Vendor Specific Register */ /*! @{ */ #define WAKEUP_USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define WAKEUP_USDHC_VEND_SPEC_VSELECT_SHIFT (1U) /*! VSELECT - Voltage selection * 0b1..Change the voltage to low voltage range , around 1.8 V * 0b0..Change the voltage to high voltage range, around 3.0 V */ #define WAKEUP_USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC_VSELECT_SHIFT)) & WAKEUP_USDHC_VEND_SPEC_VSELECT_MASK) #define WAKEUP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define WAKEUP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) /*! AC12_WR_CHKBUSY_EN - Check busy enable * 0b0..Do not check busy after auto CMD12 for write data packet * 0b1..Check busy after auto CMD12 for write data packet */ #define WAKEUP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & WAKEUP_USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) #define WAKEUP_USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define WAKEUP_USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) /*! FRC_SDCLK_ON - Force CLK * 0b0..CLK active or inactive is fully controlled by the hardware. * 0b1..Force CLK active */ #define WAKEUP_USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & WAKEUP_USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) #define WAKEUP_USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define WAKEUP_USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) /*! CRC_CHK_DIS - CRC Check Disable * 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet */ #define WAKEUP_USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & WAKEUP_USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) #define WAKEUP_USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define WAKEUP_USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) /*! CMD_BYTE_EN - Register byte access for CMD_XFR_TYP * 0b0..Disable. MIX_CTRL[7:0] is read/write and CMD_XFR_TYP[7:0] is read-only. * 0b1..Enable. MIX_CTRL[7:0] is read-only and CMD_XFR_TYP[7:0] is read/write. */ #define WAKEUP_USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & WAKEUP_USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) /*! @} */ /*! @name MMC_BOOT - eMMC Boot */ /*! @{ */ #define WAKEUP_USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define WAKEUP_USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) /*! DTOCV_ACK - DTOCV_ACK * 0b0000..SDCLK x 2^32 * 0b0001..SDCLK x 2^33 * 0b0010..SDCLK x 2^18 * 0b0011..SDCLK x 2^19 * 0b0100..SDCLK x 2^20 * 0b0101..SDCLK x 2^21 * 0b0110..SDCLK x 2^22 * 0b0111..SDCLK x 2^23 * 0b1110..SDCLK x 2^30 * 0b1111..SDCLK x 2^31 */ #define WAKEUP_USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & WAKEUP_USDHC_MMC_BOOT_DTOCV_ACK_MASK) #define WAKEUP_USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define WAKEUP_USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) /*! BOOT_ACK - BOOT ACK * 0b0..No ack * 0b1..Ack */ #define WAKEUP_USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & WAKEUP_USDHC_MMC_BOOT_BOOT_ACK_MASK) #define WAKEUP_USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define WAKEUP_USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) /*! BOOT_MODE - Boot mode * 0b0..Normal boot * 0b1..Alternative boot */ #define WAKEUP_USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & WAKEUP_USDHC_MMC_BOOT_BOOT_MODE_MASK) #define WAKEUP_USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define WAKEUP_USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) /*! BOOT_EN - Boot enable * 0b0..Fast boot disable * 0b1..Fast boot enable */ #define WAKEUP_USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & WAKEUP_USDHC_MMC_BOOT_BOOT_EN_MASK) #define WAKEUP_USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define WAKEUP_USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) /*! AUTO_SABG_EN - Auto stop at block gap */ #define WAKEUP_USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & WAKEUP_USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) #define WAKEUP_USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define WAKEUP_USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) /*! DISABLE_TIME_OUT - Time out * 0b0..Enable time out * 0b1..Disable time out */ #define WAKEUP_USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & WAKEUP_USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) #define WAKEUP_USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define WAKEUP_USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */ #define WAKEUP_USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & WAKEUP_USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) /*! @} */ /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ /*! @{ */ #define WAKEUP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define WAKEUP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) /*! CARD_INT_D3_TEST - Card interrupt detection test * 0b0..Check the card interrupt only when DATA3 is high. * 0b1..Check the card interrupt by ignoring the status of DATA3. */ #define WAKEUP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) #define WAKEUP_USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK (0x30U) #define WAKEUP_USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT (4U) /*! TUNING_BIT_EN - Tuning bit enable * 0b00..Enable Tuning circuit for DATA[3:0] * 0b01..Enable Tuning circuit for DATA[7:0] * 0b10..Enable Tuning circuit for DATA[0] * 0b11..Invalid */ #define WAKEUP_USDHC_VEND_SPEC2_TUNING_BIT_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) #define WAKEUP_USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define WAKEUP_USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) /*! TUNING_CMD_EN - Tuning command enable * 0b0..Auto tuning circuit does not check the CMD line. * 0b1..Auto tuning circuit checks the CMD line. */ #define WAKEUP_USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) #define WAKEUP_USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) #define WAKEUP_USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */ #define WAKEUP_USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) #define WAKEUP_USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) #define WAKEUP_USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */ #define WAKEUP_USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) #define WAKEUP_USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define WAKEUP_USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. * 0b0..Disable */ #define WAKEUP_USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) #define WAKEUP_USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) #define WAKEUP_USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) /*! EN_32K_CLK - Select the clock source for host card detection. * 0b0..Use the peripheral clock (ipg_clk) for card detection. * 0b1..Use the low power clock (ipg_clk_lp) for card detection. */ #define WAKEUP_USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_EN_32K_CLK_MASK) #define WAKEUP_USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK (0xFFFF0000U) #define WAKEUP_USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT (16U) /*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock */ #define WAKEUP_USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & WAKEUP_USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control */ /*! @{ */ #define WAKEUP_USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU) #define WAKEUP_USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) /*! TUNING_START_TAP - Tuning start */ #define WAKEUP_USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & WAKEUP_USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) #define WAKEUP_USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U) #define WAKEUP_USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U) /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */ #define WAKEUP_USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & WAKEUP_USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK) #define WAKEUP_USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) #define WAKEUP_USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) /*! TUNING_COUNTER - Tuning counter */ #define WAKEUP_USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & WAKEUP_USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) #define WAKEUP_USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) #define WAKEUP_USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) /*! TUNING_STEP - TUNING_STEP */ #define WAKEUP_USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & WAKEUP_USDHC_TUNING_CTRL_TUNING_STEP_MASK) #define WAKEUP_USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) #define WAKEUP_USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) /*! TUNING_WINDOW - Data window */ #define WAKEUP_USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & WAKEUP_USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) #define WAKEUP_USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define WAKEUP_USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */ #define WAKEUP_USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & WAKEUP_USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /*! @} */ /*! @name CQVER - Command Queuing Version */ /*! @{ */ #define WAKEUP_USDHC_CQVER_VERSION_SUFFIX_MASK (0xFU) #define WAKEUP_USDHC_CQVER_VERSION_SUFFIX_SHIFT (0U) /*! VERSION_SUFFIX - eMMC version suffix */ #define WAKEUP_USDHC_CQVER_VERSION_SUFFIX(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & WAKEUP_USDHC_CQVER_VERSION_SUFFIX_MASK) #define WAKEUP_USDHC_CQVER_MINOR_VN_MASK (0xF0U) #define WAKEUP_USDHC_CQVER_MINOR_VN_SHIFT (4U) /*! MINOR_VN - eMMC minor version number */ #define WAKEUP_USDHC_CQVER_MINOR_VN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQVER_MINOR_VN_SHIFT)) & WAKEUP_USDHC_CQVER_MINOR_VN_MASK) #define WAKEUP_USDHC_CQVER_MAJOR_VN_MASK (0xF00U) #define WAKEUP_USDHC_CQVER_MAJOR_VN_SHIFT (8U) /*! MAJOR_VN - eMMC major version number */ #define WAKEUP_USDHC_CQVER_MAJOR_VN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQVER_MAJOR_VN_SHIFT)) & WAKEUP_USDHC_CQVER_MAJOR_VN_MASK) /*! @} */ /*! @name CQCAP - Command Queuing Capabilities */ /*! @{ */ #define WAKEUP_USDHC_CQCAP_ITCFVAL_MASK (0x3FFU) #define WAKEUP_USDHC_CQCAP_ITCFVAL_SHIFT (0U) /*! ITCFVAL - Internal timer clock frequency value */ #define WAKEUP_USDHC_CQCAP_ITCFVAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCAP_ITCFVAL_SHIFT)) & WAKEUP_USDHC_CQCAP_ITCFVAL_MASK) #define WAKEUP_USDHC_CQCAP_ITCFMUL_MASK (0xF000U) #define WAKEUP_USDHC_CQCAP_ITCFMUL_SHIFT (12U) /*! ITCFMUL - Internal timer clock frequency multiplier * 0b0001..0.001 MHz * 0b0010..0.01 MHz * 0b0011..0.1 MHz * 0b0100..1 MHz * 0b0101..10 MHz * 0b0110-0b1001..Reserved */ #define WAKEUP_USDHC_CQCAP_ITCFMUL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCAP_ITCFMUL_SHIFT)) & WAKEUP_USDHC_CQCAP_ITCFMUL_MASK) /*! @} */ /*! @name CQCFG - Command Queuing Configuration */ /*! @{ */ #define WAKEUP_USDHC_CQCFG_CQUE_MASK (0x1U) #define WAKEUP_USDHC_CQCFG_CQUE_SHIFT (0U) /*! CQUE - Command queuing enable */ #define WAKEUP_USDHC_CQCFG_CQUE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCFG_CQUE_SHIFT)) & WAKEUP_USDHC_CQCFG_CQUE_MASK) #define WAKEUP_USDHC_CQCFG_TDS_MASK (0x100U) #define WAKEUP_USDHC_CQCFG_TDS_SHIFT (8U) /*! TDS - Task descriptor size * 0b0..Task descriptor size is 64 bits * 0b1..Task descriptor size is 128 bits */ #define WAKEUP_USDHC_CQCFG_TDS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCFG_TDS_SHIFT)) & WAKEUP_USDHC_CQCFG_TDS_MASK) #define WAKEUP_USDHC_CQCFG_DCMDE_MASK (0x1000U) #define WAKEUP_USDHC_CQCFG_DCMDE_SHIFT (12U) /*! DCMDE - Direct command (DCMD) enable * 0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor * 0b1..Task descriptor in slot #31 is a DCMD Task Descriptor */ #define WAKEUP_USDHC_CQCFG_DCMDE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCFG_DCMDE_SHIFT)) & WAKEUP_USDHC_CQCFG_DCMDE_MASK) /*! @} */ /*! @name CQCTL - Command Queuing Control */ /*! @{ */ #define WAKEUP_USDHC_CQCTL_HALT_MASK (0x1U) #define WAKEUP_USDHC_CQCTL_HALT_SHIFT (0U) /*! HALT - Halt */ #define WAKEUP_USDHC_CQCTL_HALT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCTL_HALT_SHIFT)) & WAKEUP_USDHC_CQCTL_HALT_MASK) #define WAKEUP_USDHC_CQCTL_CLEAR_MASK (0x100U) #define WAKEUP_USDHC_CQCTL_CLEAR_SHIFT (8U) /*! CLEAR - Clear all tasks */ #define WAKEUP_USDHC_CQCTL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCTL_CLEAR_SHIFT)) & WAKEUP_USDHC_CQCTL_CLEAR_MASK) /*! @} */ /*! @name CQIS - Command Queuing Interrupt Status */ /*! @{ */ #define WAKEUP_USDHC_CQIS_HAC_MASK (0x1U) #define WAKEUP_USDHC_CQIS_HAC_SHIFT (0U) /*! HAC - Halt complete interrupt */ #define WAKEUP_USDHC_CQIS_HAC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIS_HAC_SHIFT)) & WAKEUP_USDHC_CQIS_HAC_MASK) #define WAKEUP_USDHC_CQIS_TCC_MASK (0x2U) #define WAKEUP_USDHC_CQIS_TCC_SHIFT (1U) /*! TCC - Task complete interrupt */ #define WAKEUP_USDHC_CQIS_TCC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIS_TCC_SHIFT)) & WAKEUP_USDHC_CQIS_TCC_MASK) #define WAKEUP_USDHC_CQIS_RED_MASK (0x4U) #define WAKEUP_USDHC_CQIS_RED_SHIFT (2U) /*! RED - Response error detected interrupt */ #define WAKEUP_USDHC_CQIS_RED(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIS_RED_SHIFT)) & WAKEUP_USDHC_CQIS_RED_MASK) #define WAKEUP_USDHC_CQIS_TCL_MASK (0x8U) #define WAKEUP_USDHC_CQIS_TCL_SHIFT (3U) /*! TCL - Task cleared */ #define WAKEUP_USDHC_CQIS_TCL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIS_TCL_SHIFT)) & WAKEUP_USDHC_CQIS_TCL_MASK) /*! @} */ /*! @name CQISTE - Command Queuing Interrupt Status Enable */ /*! @{ */ #define WAKEUP_USDHC_CQISTE_HAC_STE_MASK (0x1U) #define WAKEUP_USDHC_CQISTE_HAC_STE_SHIFT (0U) /*! HAC_STE - Halt complete status enable * 0b0..CQIS[HAC] is disabled * 0b1..CQIS[HAC] is set when its interrupt condition is active */ #define WAKEUP_USDHC_CQISTE_HAC_STE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISTE_HAC_STE_SHIFT)) & WAKEUP_USDHC_CQISTE_HAC_STE_MASK) #define WAKEUP_USDHC_CQISTE_TCC_STE_MASK (0x2U) #define WAKEUP_USDHC_CQISTE_TCC_STE_SHIFT (1U) /*! TCC_STE - Task complete status enable * 0b0..CQIS[TCC] is disabled * 0b1..CQIS[TCC] is set when its interrupt condition is active */ #define WAKEUP_USDHC_CQISTE_TCC_STE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISTE_TCC_STE_SHIFT)) & WAKEUP_USDHC_CQISTE_TCC_STE_MASK) #define WAKEUP_USDHC_CQISTE_RED_STE_MASK (0x4U) #define WAKEUP_USDHC_CQISTE_RED_STE_SHIFT (2U) /*! RED_STE - Response error detected status enable * 0b0..CQIS[RED]is disabled * 0b1..CQIS[RED] is set when its interrupt condition is active */ #define WAKEUP_USDHC_CQISTE_RED_STE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISTE_RED_STE_SHIFT)) & WAKEUP_USDHC_CQISTE_RED_STE_MASK) #define WAKEUP_USDHC_CQISTE_TCL_STE_MASK (0x8U) #define WAKEUP_USDHC_CQISTE_TCL_STE_SHIFT (3U) /*! TCL_STE - Task cleared status enable * 0b0..CQIS[TCL] is disabled * 0b1..CQIS[TCL] is set when its interrupt condition is active */ #define WAKEUP_USDHC_CQISTE_TCL_STE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISTE_TCL_STE_SHIFT)) & WAKEUP_USDHC_CQISTE_TCL_STE_MASK) /*! @} */ /*! @name CQISGE - Command Queuing Interrupt Signal Enable */ /*! @{ */ #define WAKEUP_USDHC_CQISGE_HAC_SGE_MASK (0x1U) #define WAKEUP_USDHC_CQISGE_HAC_SGE_SHIFT (0U) /*! HAC_SGE - Halt complete signal enable */ #define WAKEUP_USDHC_CQISGE_HAC_SGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISGE_HAC_SGE_SHIFT)) & WAKEUP_USDHC_CQISGE_HAC_SGE_MASK) #define WAKEUP_USDHC_CQISGE_TCC_SGE_MASK (0x2U) #define WAKEUP_USDHC_CQISGE_TCC_SGE_SHIFT (1U) /*! TCC_SGE - Task complete signal enable */ #define WAKEUP_USDHC_CQISGE_TCC_SGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISGE_TCC_SGE_SHIFT)) & WAKEUP_USDHC_CQISGE_TCC_SGE_MASK) #define WAKEUP_USDHC_CQISGE_RED_SGE_MASK (0x4U) #define WAKEUP_USDHC_CQISGE_RED_SGE_SHIFT (2U) /*! RED_SGE - Response error detected signal enable */ #define WAKEUP_USDHC_CQISGE_RED_SGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISGE_RED_SGE_SHIFT)) & WAKEUP_USDHC_CQISGE_RED_SGE_MASK) #define WAKEUP_USDHC_CQISGE_TCL_SGE_MASK (0x8U) #define WAKEUP_USDHC_CQISGE_TCL_SGE_SHIFT (3U) /*! TCL_SGE - Task cleared signal enable */ #define WAKEUP_USDHC_CQISGE_TCL_SGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQISGE_TCL_SGE_SHIFT)) & WAKEUP_USDHC_CQISGE_TCL_SGE_MASK) /*! @} */ /*! @name CQIC - Command Queuing Interrupt Coalescing */ /*! @{ */ #define WAKEUP_USDHC_CQIC_ICTOVAL_MASK (0x7FU) #define WAKEUP_USDHC_CQIC_ICTOVAL_SHIFT (0U) /*! ICTOVAL - Interrupt coalescing timeout value */ #define WAKEUP_USDHC_CQIC_ICTOVAL(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIC_ICTOVAL_SHIFT)) & WAKEUP_USDHC_CQIC_ICTOVAL_MASK) #define WAKEUP_USDHC_CQIC_ICTOVALWEN_MASK (0x80U) #define WAKEUP_USDHC_CQIC_ICTOVALWEN_SHIFT (7U) /*! ICTOVALWEN - Interrupt coalescing timeout value write enable */ #define WAKEUP_USDHC_CQIC_ICTOVALWEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIC_ICTOVALWEN_SHIFT)) & WAKEUP_USDHC_CQIC_ICTOVALWEN_MASK) #define WAKEUP_USDHC_CQIC_ICCTH_MASK (0x1F00U) #define WAKEUP_USDHC_CQIC_ICCTH_SHIFT (8U) /*! ICCTH - Interrupt coalescing counter threshold */ #define WAKEUP_USDHC_CQIC_ICCTH(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIC_ICCTH_SHIFT)) & WAKEUP_USDHC_CQIC_ICCTH_MASK) #define WAKEUP_USDHC_CQIC_ICCTHWEN_MASK (0x8000U) #define WAKEUP_USDHC_CQIC_ICCTHWEN_SHIFT (15U) /*! ICCTHWEN - Interrupt coalescing counter threshold write enable */ #define WAKEUP_USDHC_CQIC_ICCTHWEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIC_ICCTHWEN_SHIFT)) & WAKEUP_USDHC_CQIC_ICCTHWEN_MASK) #define WAKEUP_USDHC_CQIC_ICCTR_MASK (0x10000U) #define WAKEUP_USDHC_CQIC_ICCTR_SHIFT (16U) /*! ICCTR - Counter and timer reset */ #define WAKEUP_USDHC_CQIC_ICCTR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIC_ICCTR_SHIFT)) & WAKEUP_USDHC_CQIC_ICCTR_MASK) #define WAKEUP_USDHC_CQIC_ICSB_MASK (0x100000U) #define WAKEUP_USDHC_CQIC_ICSB_SHIFT (20U) /*! ICSB - Interrupt coalescing status * 0b0..No task completions have occurred since last counter reset (IC counter =0) * 0b1..At least one task completion has been counted (IC counter >0) */ #define WAKEUP_USDHC_CQIC_ICSB(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIC_ICSB_SHIFT)) & WAKEUP_USDHC_CQIC_ICSB_MASK) #define WAKEUP_USDHC_CQIC_ICENDIS_MASK (0x80000000U) #define WAKEUP_USDHC_CQIC_ICENDIS_SHIFT (31U) /*! ICENDIS - Interrupt coalescing enable/disable */ #define WAKEUP_USDHC_CQIC_ICENDIS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQIC_ICENDIS_SHIFT)) & WAKEUP_USDHC_CQIC_ICENDIS_MASK) /*! @} */ /*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */ /*! @{ */ #define WAKEUP_USDHC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQTDLBA_TDLBA_SHIFT (0U) /*! TDLBA - Task descriptor list base address */ #define WAKEUP_USDHC_CQTDLBA_TDLBA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTDLBA_TDLBA_SHIFT)) & WAKEUP_USDHC_CQTDLBA_TDLBA_MASK) /*! @} */ /*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */ /*! @{ */ #define WAKEUP_USDHC_CQTDLBAU_TDLBAU_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQTDLBAU_TDLBAU_SHIFT (0U) /*! TDLBAU - Task descriptor list base address */ #define WAKEUP_USDHC_CQTDLBAU_TDLBAU(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTDLBAU_TDLBAU_SHIFT)) & WAKEUP_USDHC_CQTDLBAU_TDLBAU_MASK) /*! @} */ /*! @name CQTDBR - Command Queuing Task Doorbell */ /*! @{ */ #define WAKEUP_USDHC_CQTDBR_TDBR_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQTDBR_TDBR_SHIFT (0U) /*! TDBR - Task doorbell */ #define WAKEUP_USDHC_CQTDBR_TDBR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTDBR_TDBR_SHIFT)) & WAKEUP_USDHC_CQTDBR_TDBR_MASK) /*! @} */ /*! @name CQTCN - Command Queuing Task Completion Notification */ /*! @{ */ #define WAKEUP_USDHC_CQTCN_TCN_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQTCN_TCN_SHIFT (0U) /*! TCN - Task complete notification */ #define WAKEUP_USDHC_CQTCN_TCN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTCN_TCN_SHIFT)) & WAKEUP_USDHC_CQTCN_TCN_MASK) /*! @} */ /*! @name CQDQS - Command Queuing Device Queue Status */ /*! @{ */ #define WAKEUP_USDHC_CQDQS_DQS_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQDQS_DQS_SHIFT (0U) /*! DQS - Device queue status */ #define WAKEUP_USDHC_CQDQS_DQS(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQDQS_DQS_SHIFT)) & WAKEUP_USDHC_CQDQS_DQS_MASK) /*! @} */ /*! @name CQDPT - Command Queuing Device Pending Tasks */ /*! @{ */ #define WAKEUP_USDHC_CQDPT_DPT_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQDPT_DPT_SHIFT (0U) /*! DPT - Device pending tasks */ #define WAKEUP_USDHC_CQDPT_DPT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQDPT_DPT_SHIFT)) & WAKEUP_USDHC_CQDPT_DPT_MASK) /*! @} */ /*! @name CQTCLR - Command Queuing Task Clear */ /*! @{ */ #define WAKEUP_USDHC_CQTCLR_TCLR_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQTCLR_TCLR_SHIFT (0U) /*! TCLR - Task clear */ #define WAKEUP_USDHC_CQTCLR_TCLR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTCLR_TCLR_SHIFT)) & WAKEUP_USDHC_CQTCLR_TCLR_MASK) /*! @} */ /*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */ /*! @{ */ #define WAKEUP_USDHC_CQSSC1_CIT_MASK (0xFFFFU) #define WAKEUP_USDHC_CQSSC1_CIT_SHIFT (0U) /*! CIT - Send status command idle timer */ #define WAKEUP_USDHC_CQSSC1_CIT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQSSC1_CIT_SHIFT)) & WAKEUP_USDHC_CQSSC1_CIT_MASK) #define WAKEUP_USDHC_CQSSC1_CBC_MASK (0xF0000U) #define WAKEUP_USDHC_CQSSC1_CBC_SHIFT (16U) /*! CBC - Send status command block counter */ #define WAKEUP_USDHC_CQSSC1_CBC(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQSSC1_CBC_SHIFT)) & WAKEUP_USDHC_CQSSC1_CBC_MASK) /*! @} */ /*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */ /*! @{ */ #define WAKEUP_USDHC_CQSSC2_SSC2_MASK (0xFFFFU) #define WAKEUP_USDHC_CQSSC2_SSC2_SHIFT (0U) /*! SSC2 - Send queue status RCA */ #define WAKEUP_USDHC_CQSSC2_SSC2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQSSC2_SSC2_SHIFT)) & WAKEUP_USDHC_CQSSC2_SSC2_MASK) /*! @} */ /*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */ /*! @{ */ #define WAKEUP_USDHC_CQCRDCT_CRDCT_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQCRDCT_CRDCT_SHIFT (0U) /*! CRDCT - Direct command last response */ #define WAKEUP_USDHC_CQCRDCT_CRDCT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCRDCT_CRDCT_SHIFT)) & WAKEUP_USDHC_CQCRDCT_CRDCT_MASK) /*! @} */ /*! @name CQRMEM - Command Queuing Response Mode Error Mask */ /*! @{ */ #define WAKEUP_USDHC_CQRMEM_RMEM_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQRMEM_RMEM_SHIFT (0U) /*! RMEM - Response mode error mask * 0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored * 0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated */ #define WAKEUP_USDHC_CQRMEM_RMEM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQRMEM_RMEM_SHIFT)) & WAKEUP_USDHC_CQRMEM_RMEM_MASK) /*! @} */ /*! @name CQTERRI - Command Queuing Task Error Information */ /*! @{ */ #define WAKEUP_USDHC_CQTERRI_RMECI_MASK (0x3FU) #define WAKEUP_USDHC_CQTERRI_RMECI_SHIFT (0U) /*! RMECI - Response mode error command index */ #define WAKEUP_USDHC_CQTERRI_RMECI(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTERRI_RMECI_SHIFT)) & WAKEUP_USDHC_CQTERRI_RMECI_MASK) #define WAKEUP_USDHC_CQTERRI_RMETID_MASK (0x1F00U) #define WAKEUP_USDHC_CQTERRI_RMETID_SHIFT (8U) /*! RMETID - Response mode error task ID */ #define WAKEUP_USDHC_CQTERRI_RMETID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTERRI_RMETID_SHIFT)) & WAKEUP_USDHC_CQTERRI_RMETID_MASK) #define WAKEUP_USDHC_CQTERRI_RMEFV_MASK (0x8000U) #define WAKEUP_USDHC_CQTERRI_RMEFV_SHIFT (15U) /*! RMEFV - Response mode error fields valid */ #define WAKEUP_USDHC_CQTERRI_RMEFV(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTERRI_RMEFV_SHIFT)) & WAKEUP_USDHC_CQTERRI_RMEFV_MASK) #define WAKEUP_USDHC_CQTERRI_DTECI_MASK (0x3F0000U) #define WAKEUP_USDHC_CQTERRI_DTECI_SHIFT (16U) /*! DTECI - Data transfer error command index */ #define WAKEUP_USDHC_CQTERRI_DTECI(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTERRI_DTECI_SHIFT)) & WAKEUP_USDHC_CQTERRI_DTECI_MASK) #define WAKEUP_USDHC_CQTERRI_DTETID_MASK (0x1F000000U) #define WAKEUP_USDHC_CQTERRI_DTETID_SHIFT (24U) /*! DTETID - Data transfer error task ID */ #define WAKEUP_USDHC_CQTERRI_DTETID(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTERRI_DTETID_SHIFT)) & WAKEUP_USDHC_CQTERRI_DTETID_MASK) #define WAKEUP_USDHC_CQTERRI_DTEFV_MASK (0x80000000U) #define WAKEUP_USDHC_CQTERRI_DTEFV_SHIFT (31U) /*! DTEFV - Data transfer error fields valid */ #define WAKEUP_USDHC_CQTERRI_DTEFV(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQTERRI_DTEFV_SHIFT)) & WAKEUP_USDHC_CQTERRI_DTEFV_MASK) /*! @} */ /*! @name CQCRI - Command Queuing Command Response Index */ /*! @{ */ #define WAKEUP_USDHC_CQCRI_LCMDRI_MASK (0x3FU) #define WAKEUP_USDHC_CQCRI_LCMDRI_SHIFT (0U) /*! LCMDRI - Last command response index */ #define WAKEUP_USDHC_CQCRI_LCMDRI(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCRI_LCMDRI_SHIFT)) & WAKEUP_USDHC_CQCRI_LCMDRI_MASK) /*! @} */ /*! @name CQCRA - Command Queuing Command Response Argument */ /*! @{ */ #define WAKEUP_USDHC_CQCRA_LCMDRA_MASK (0xFFFFFFFFU) #define WAKEUP_USDHC_CQCRA_LCMDRA_SHIFT (0U) /*! LCMDRA - Last command response argument */ #define WAKEUP_USDHC_CQCRA_LCMDRA(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_USDHC_CQCRA_LCMDRA_SHIFT)) & WAKEUP_USDHC_CQCRA_LCMDRA_MASK) /*! @} */ /*! * @} */ /* end of group WAKEUP_USDHC_Register_Masks */ /* WAKEUP_USDHC - Peripheral instance base addresses */ /** Peripheral WAKEUP__USDHC1 base address */ #define WAKEUP__USDHC1_BASE (0x42850000u) /** Peripheral WAKEUP__USDHC1 base pointer */ #define WAKEUP__USDHC1 ((WAKEUP_USDHC_Type *)WAKEUP__USDHC1_BASE) /** Peripheral WAKEUP__USDHC2 base address */ #define WAKEUP__USDHC2_BASE (0x42860000u) /** Peripheral WAKEUP__USDHC2 base pointer */ #define WAKEUP__USDHC2 ((WAKEUP_USDHC_Type *)WAKEUP__USDHC2_BASE) /** Peripheral WAKEUP__USDHC3 base address */ #define WAKEUP__USDHC3_BASE (0x428B0000u) /** Peripheral WAKEUP__USDHC3 base pointer */ #define WAKEUP__USDHC3 ((WAKEUP_USDHC_Type *)WAKEUP__USDHC3_BASE) /** Array initializer of WAKEUP_USDHC peripheral base addresses */ #define WAKEUP_USDHC_BASE_ADDRS { WAKEUP__USDHC1_BASE, WAKEUP__USDHC2_BASE, WAKEUP__USDHC3_BASE } /** Array initializer of WAKEUP_USDHC peripheral base pointers */ #define WAKEUP_USDHC_BASE_PTRS { WAKEUP__USDHC1, WAKEUP__USDHC2, WAKEUP__USDHC3 } /*! * @} */ /* end of group WAKEUP_USDHC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WAKEUP_XSPI_RESPONDER Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_XSPI_RESPONDER_Peripheral_Access_Layer WAKEUP_XSPI_RESPONDER Peripheral Access Layer * @{ */ /** WAKEUP_XSPI_RESPONDER - Register Layout Typedef */ typedef struct { __IO uint32_t MODULE_CONTROL; /**< Module Control, offset: 0x0 */ __IO uint32_t READ_COMMAND_CONTROL; /**< Read Command Control, offset: 0x4 */ __IO uint32_t READ_REGISTER_COMMAND0; /**< Read Register Command Setting, offset: 0x8 */ __IO uint32_t READ_COMMAND1; /**< Read Command 1 setting, offset: 0xC */ __IO uint32_t READ_COMMAND2; /**< Read Command 2 setting, offset: 0x10 */ __IO uint32_t WRITE_COMMAND_CONTROL; /**< Write Command Control, offset: 0x14 */ __IO uint32_t WRITE_REGISTER_COMMAND0; /**< Write Register Command 0 Setting, offset: 0x18 */ __IO uint32_t WRITE_COMMAND1; /**< Write Command 1 Setting, offset: 0x1C */ __IO uint32_t WRITE_COMMAND2; /**< Write Command 2 Setting, offset: 0x20 */ __IO uint32_t RW_COMMAND_BASE; /**< Read Write Command Address Base, offset: 0x24 */ __IO uint32_t CMD1_RANGE; /**< Command Suit 1 Range, offset: 0x28 */ __IO uint32_t CMD2_RANGE; /**< Command Suit 2 Range, offset: 0x2C */ __I uint32_t MODULE_STATUS; /**< Module Status, offset: 0x30 */ __IO uint32_t MODULE_INT; /**< SPI FLR interrupt, offset: 0x34 */ __IO uint32_t MODULE_INTEN; /**< SPI FLR Interrupt Enable, offset: 0x38 */ __IO uint32_t SPI_MAIL_CTRL; /**< SPI Mailbox control, offset: 0x3C */ __I uint32_t SPIMAIL0; /**< SPI Mail Interrupt, offset: 0x40 */ __I uint32_t SPIMAIL[8]; /**< SPI Mail Interrupt 1..SPI Mail Interrupt 8, array offset: 0x44, array step: 0x4 */ } WAKEUP_XSPI_RESPONDER_Type; /* ---------------------------------------------------------------------------- -- WAKEUP_XSPI_RESPONDER Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WAKEUP_XSPI_RESPONDER_Register_Masks WAKEUP_XSPI_RESPONDER Register Masks * @{ */ /*! @name MODULE_CONTROL - Module Control */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_SWRESET_MASK (0x1U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_SWRESET_SHIFT (0U) /*! SWRESET - Software Reset * 0b1..Initiate * 0b0..Finished */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_SWRESET_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_SWRESET_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_IOMODE_MASK (0x6U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_IOMODE_SHIFT (1U) /*! IOMODE - SPI IO Mode Control * 0b00..SDR*4 * 0b01..SDR*8 * 0b10..DDR*4 * 0b11..DDR*8 */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_IOMODE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_IOMODE_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_IOMODE_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_DQSSTOP_MASK (0x8U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_DQSSTOP_SHIFT (3U) /*! DQSSTOP - DQS Stop Feature * 0b1..Enable * 0b0..Disable */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_DQSSTOP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_DQSSTOP_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_DQSSTOP_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CSMASK_MASK (0x10U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CSMASK_SHIFT (4U) /*! CSMASK - Chip Select Mask * 0b1..Masked * 0b0..Not masked */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CSMASK(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CSMASK_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CSMASK_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKREAD_MASK (0x20U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKREAD_SHIFT (5U) /*! BLKREAD - Block Read * 0b1..Blocked * 0b0..Allowed */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKREAD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKREAD_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKREAD_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKWRITE_MASK (0x40U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKWRITE_SHIFT (6U) /*! BLKWRITE - Block Write * 0b1..Blocked * 0b0..Allowed */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKWRITE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKWRITE_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKWRITE_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTWR_MASK (0x80U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTWR_SHIFT (7U) /*! BLKNXTWR - Block Next Write Command * 0b1..Blocked. The next write command is not blocked. The write commands after the next one are all blocked and * all incoming write data is discarded. * 0b0..Allowed */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTWR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTWR_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTWR_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTRD_MASK (0x100U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTRD_SHIFT (8U) /*! BLKNXTRD - Block Next Read * 0b1..Blocked. The next read command is not blocked. The read commands after the next one are all blocked and return all zeroes. * 0b0..Allowed */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTRD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTRD_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_BLKNXTRD_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONEWR_MASK (0x200U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONEWR_SHIFT (9U) /*! ALLOWONEWR - Allow One More Write * 0b1..Allowed * 0b0..Not allowed */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONEWR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONEWR_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONEWR_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONERD_MASK (0x400U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONERD_SHIFT (10U) /*! ALLOWONERD - Allow One More Read * 0b1..Allowed * 0b0..Not allowed */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONERD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONERD_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_ALLOWONERD_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CMDRANGEBASEUPDATE_MASK (0x800U) #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CMDRANGEBASEUPDATE_SHIFT (11U) /*! CMDRANGEBASEUPDATE - AXI Command Range Base Update * 0b1..Updated * 0b0..Not updated */ #define WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CMDRANGEBASEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CMDRANGEBASEUPDATE_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_CONTROL_CMDRANGEBASEUPDATE_MASK) /*! @} */ /*! @name READ_COMMAND_CONTROL - Read Command Control */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDFETCHSIZE_MASK (0x3U) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDFETCHSIZE_SHIFT (0U) /*! RDFETCHSIZE - Read Fetch Size * 0b00..256 bytes * 0b01..512 bytes * 0b10..1 KB * 0b11..2 KB */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDFETCHSIZE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDFETCHSIZE_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDFETCHSIZE_MASK) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDWM_MASK (0xFCU) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDWM_SHIFT (2U) /*! RDWM - Read Watermark Level */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDWM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDWM_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDWM_MASK) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDOT_MASK (0x100U) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDOT_SHIFT (8U) /*! RDOT - Read Outstanding * 0b1..Send requests outstandingly * 0b0..Send requests after previous leaders finish */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDOT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDOT_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_RDOT_MASK) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_WMEN_MASK (0x200U) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_WMEN_SHIFT (9U) /*! WMEN - Read Water Mark Enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_WMEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_WMEN_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND_CONTROL_WMEN_MASK) /*! @} */ /*! @name READ_REGISTER_COMMAND0 - Read Register Command Setting */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_DUMMYCYCLES_MASK (0xFFFFU) #define WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_DUMMYCYCLES_SHIFT (0U) /*! DUMMYCYCLES - Read Register Dummy Cycles */ #define WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_DUMMYCYCLES(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_DUMMYCYCLES_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_DUMMYCYCLES_MASK) #define WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_COMMANDSET_MASK (0xFFFF0000U) #define WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_COMMANDSET_SHIFT (16U) /*! COMMANDSET - Read Register Command Setting */ #define WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_COMMANDSET_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_REGISTER_COMMAND0_COMMANDSET_MASK) /*! @} */ /*! @name READ_COMMAND1 - Read Command 1 setting */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND1_DUMMYCYCLES_MASK (0xFFFFU) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND1_DUMMYCYCLES_SHIFT (0U) /*! DUMMYCYCLES - Read Command 1 Dummy Cycles */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND1_DUMMYCYCLES(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND1_DUMMYCYCLES_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND1_DUMMYCYCLES_MASK) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND1_COMMANDSET_MASK (0xFFFF0000U) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND1_COMMANDSET_SHIFT (16U) /*! COMMANDSET - Read Command 1 Setting */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND1_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND1_COMMANDSET_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND1_COMMANDSET_MASK) /*! @} */ /*! @name READ_COMMAND2 - Read Command 2 setting */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND2_DUMMYCYCLES_MASK (0xFFFFU) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND2_DUMMYCYCLES_SHIFT (0U) /*! DUMMYCYCLES - Read Command 2 Dummy Cycles */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND2_DUMMYCYCLES(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND2_DUMMYCYCLES_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND2_DUMMYCYCLES_MASK) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND2_COMMANDSET_MASK (0xFFFF0000U) #define WAKEUP_XSPI_RESPONDER_READ_COMMAND2_COMMANDSET_SHIFT (16U) /*! COMMANDSET - Read Command 2 Setting */ #define WAKEUP_XSPI_RESPONDER_READ_COMMAND2_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_READ_COMMAND2_COMMANDSET_SHIFT)) & WAKEUP_XSPI_RESPONDER_READ_COMMAND2_COMMANDSET_MASK) /*! @} */ /*! @name WRITE_COMMAND_CONTROL - Write Command Control */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND_CONTROL_WRWM_MASK (0x3U) #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND_CONTROL_WRWM_SHIFT (0U) /*! WRWM - Write Watermark * 0b00..32 bytes * 0b01..64 bytes * 0b10..128 bytes * 0b11..256 bytes */ #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND_CONTROL_WRWM(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_WRITE_COMMAND_CONTROL_WRWM_SHIFT)) & WAKEUP_XSPI_RESPONDER_WRITE_COMMAND_CONTROL_WRWM_MASK) /*! @} */ /*! @name WRITE_REGISTER_COMMAND0 - Write Register Command 0 Setting */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_WRITE_REGISTER_COMMAND0_COMMANDSET_MASK (0xFFFF0000U) #define WAKEUP_XSPI_RESPONDER_WRITE_REGISTER_COMMAND0_COMMANDSET_SHIFT (16U) /*! COMMANDSET - Write Register Command Setting */ #define WAKEUP_XSPI_RESPONDER_WRITE_REGISTER_COMMAND0_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_WRITE_REGISTER_COMMAND0_COMMANDSET_SHIFT)) & WAKEUP_XSPI_RESPONDER_WRITE_REGISTER_COMMAND0_COMMANDSET_MASK) /*! @} */ /*! @name WRITE_COMMAND1 - Write Command 1 Setting */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND1_COMMANDSET_MASK (0xFFFF0000U) #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND1_COMMANDSET_SHIFT (16U) /*! COMMANDSET - Write Command 1 Setting */ #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND1_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_WRITE_COMMAND1_COMMANDSET_SHIFT)) & WAKEUP_XSPI_RESPONDER_WRITE_COMMAND1_COMMANDSET_MASK) /*! @} */ /*! @name WRITE_COMMAND2 - Write Command 2 Setting */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND2_COMMANDSET_MASK (0xFFFF0000U) #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND2_COMMANDSET_SHIFT (16U) /*! COMMANDSET - Write Command 2 Setting */ #define WAKEUP_XSPI_RESPONDER_WRITE_COMMAND2_COMMANDSET(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_WRITE_COMMAND2_COMMANDSET_SHIFT)) & WAKEUP_XSPI_RESPONDER_WRITE_COMMAND2_COMMANDSET_MASK) /*! @} */ /*! @name RW_COMMAND_BASE - Read Write Command Address Base */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE1_MASK (0xFFFFU) #define WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE1_SHIFT (0U) /*! ADDRBASE1 - Address Base 1 */ #define WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE1_SHIFT)) & WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE1_MASK) #define WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE2_MASK (0xFFFF0000U) #define WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE2_SHIFT (16U) /*! ADDRBASE2 - Address Base 2 */ #define WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE2_SHIFT)) & WAKEUP_XSPI_RESPONDER_RW_COMMAND_BASE_ADDRBASE2_MASK) /*! @} */ /*! @name CMD1_RANGE - Command Suit 1 Range */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_CMD1_RANGE_RANGE_MASK (0xFFFFFC00U) #define WAKEUP_XSPI_RESPONDER_CMD1_RANGE_RANGE_SHIFT (10U) /*! RANGE - Memory Range */ #define WAKEUP_XSPI_RESPONDER_CMD1_RANGE_RANGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_CMD1_RANGE_RANGE_SHIFT)) & WAKEUP_XSPI_RESPONDER_CMD1_RANGE_RANGE_MASK) /*! @} */ /*! @name CMD2_RANGE - Command Suit 2 Range */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_CMD2_RANGE_RANGE_MASK (0xFFFFFC00U) #define WAKEUP_XSPI_RESPONDER_CMD2_RANGE_RANGE_SHIFT (10U) /*! RANGE - Memory Range */ #define WAKEUP_XSPI_RESPONDER_CMD2_RANGE_RANGE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_CMD2_RANGE_RANGE_SHIFT)) & WAKEUP_XSPI_RESPONDER_CMD2_RANGE_RANGE_MASK) /*! @} */ /*! @name MODULE_STATUS - Module Status */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WIP_MASK (0x1U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WIP_SHIFT (0U) /*! WIP - Write in Progress * 0b1..Busy * 0b0..Not busy */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WIP(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WIP_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WIP_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_AXIREADIDLE_MASK (0x2U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_AXIREADIDLE_SHIFT (1U) /*! AXIREADIDLE - AXI Read Leader Idle * 0b1..Idle * 0b0..Busy */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_AXIREADIDLE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_AXIREADIDLE_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_AXIREADIDLE_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_REGRWIDLE_MASK (0x4U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_REGRWIDLE_SHIFT (2U) /*! REGRWIDLE - Register Read Write Idle * 0b1..Idle * 0b0..Busy */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_REGRWIDLE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_REGRWIDLE_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_REGRWIDLE_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_SEQIDLE_MASK (0x8U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_SEQIDLE_SHIFT (3U) /*! SEQIDLE - SEQ Controller Idle * 0b1..Idle * 0b0..Busy */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_SEQIDLE_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_SEQIDLE_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_RDOFR_MASK (0xF0U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_RDOFR_SHIFT (4U) /*! RDOFR - Read Out-of-Range Counter */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_RDOFR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_RDOFR_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_RDOFR_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WROFR_MASK (0xF00U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WROFR_SHIFT (8U) /*! WROFR - Write Out-of-Range Counter */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WROFR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WROFR_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_WROFR_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIRD_MASK (0x1000U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIRD_SHIFT (12U) /*! ALLOWAXIRD - Allow AXI Read Access * 0b1..Allowed * 0b0..Denied */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIRD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIRD_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIRD_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIWR_MASK (0x2000U) #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIWR_SHIFT (13U) /*! ALLOWAXIWR - Allow AXI Write Access * 0b1..Allowed * 0b0..Denied */ #define WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIWR(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIWR_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_STATUS_ALLOWAXIWR_MASK) /*! @} */ /*! @name MODULE_INT - SPI FLR interrupt */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_MODULE_INT_WOF_MASK (0x1U) #define WAKEUP_XSPI_RESPONDER_MODULE_INT_WOF_SHIFT (0U) /*! WOF - Write Overflow Interrupt * 0b1..Occurred * 0b0..Did not occur */ #define WAKEUP_XSPI_RESPONDER_MODULE_INT_WOF(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_INT_WOF_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_INT_WOF_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_INT_RUF_MASK (0x2U) #define WAKEUP_XSPI_RESPONDER_MODULE_INT_RUF_SHIFT (1U) /*! RUF - Read Underflow * 0b1..Occurred * 0b0..Did not occur */ #define WAKEUP_XSPI_RESPONDER_MODULE_INT_RUF(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_INT_RUF_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_INT_RUF_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_INT_ERRCMD_MASK (0x4U) #define WAKEUP_XSPI_RESPONDER_MODULE_INT_ERRCMD_SHIFT (2U) /*! ERRCMD - Error Command * 0b1..Received * 0b0..Not received */ #define WAKEUP_XSPI_RESPONDER_MODULE_INT_ERRCMD(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_INT_ERRCMD_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_INT_ERRCMD_MASK) /*! @} */ /*! @name MODULE_INTEN - SPI FLR Interrupt Enable */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_WOFEN_MASK (0x1U) #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_WOFEN_SHIFT (0U) /*! WOFEN - Write Overflow Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_WOFEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_INTEN_WOFEN_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_INTEN_WOFEN_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_RUFEN_MASK (0x2U) #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_RUFEN_SHIFT (1U) /*! RUFEN - Read Underflow Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_RUFEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_INTEN_RUFEN_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_INTEN_RUFEN_MASK) #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_ERRCMDEN_MASK (0x4U) #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_ERRCMDEN_SHIFT (2U) /*! ERRCMDEN - Error Command Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_XSPI_RESPONDER_MODULE_INTEN_ERRCMDEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_MODULE_INTEN_ERRCMDEN_SHIFT)) & WAKEUP_XSPI_RESPONDER_MODULE_INTEN_ERRCMDEN_MASK) /*! @} */ /*! @name SPI_MAIL_CTRL - SPI Mailbox control */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_CLRINT_MASK (0x1U) #define WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_CLRINT_SHIFT (0U) /*! CLRINT - Clear Interrupt * 0b1..Clear * 0b0..Do not clear */ #define WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_CLRINT(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_CLRINT_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_CLRINT_MASK) #define WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_SPIINTEN_MASK (0x2U) #define WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_SPIINTEN_SHIFT (1U) /*! SPIINTEN - SPI Leader Interrupt Enable * 0b1..Enable * 0b0..Disable */ #define WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_SPIINTEN(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_SPIINTEN_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPI_MAIL_CTRL_SPIINTEN_MASK) /*! @} */ /*! @name SPIMAIL0 - SPI Mail Interrupt */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_SPIMAIL0_MAILn_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL0_MAILn_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL0_MAILn(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL0_MAILn_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL0_MAILn_MASK) /*! @} */ /*! @name SPIMAIL - SPI Mail Interrupt 1..SPI Mail Interrupt 8 */ /*! @{ */ #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL1_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL1_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL1(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL1_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL1_MASK) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL2_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL2_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL2(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL2_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL2_MASK) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL3_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL3_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL3(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL3_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL3_MASK) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL4_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL4_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL4(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL4_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL4_MASK) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL5_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL5_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL5(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL5_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL5_MASK) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL6_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL6_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL6(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL6_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL6_MASK) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL7_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL7_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL7(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL7_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL7_MASK) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL8_MASK (0xFFFFFFFFU) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL8_SHIFT (0U) #define WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL8(x) (((uint32_t)(((uint32_t)(x)) << WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL8_SHIFT)) & WAKEUP_XSPI_RESPONDER_SPIMAIL_MAIL8_MASK) /*! @} */ /* The count of WAKEUP_XSPI_RESPONDER_SPIMAIL */ #define WAKEUP_XSPI_RESPONDER_SPIMAIL_COUNT (8U) /*! * @} */ /* end of group WAKEUP_XSPI_RESPONDER_Register_Masks */ /* WAKEUP_XSPI_RESPONDER - Peripheral instance base addresses */ /** Peripheral WAKEUP__XSPI_RESPONDER base address */ #define WAKEUP__XSPI_RESPONDER_BASE (0x428A0000u) /** Peripheral WAKEUP__XSPI_RESPONDER base pointer */ #define WAKEUP__XSPI_RESPONDER ((WAKEUP_XSPI_RESPONDER_Type *)WAKEUP__XSPI_RESPONDER_BASE) /** Array initializer of WAKEUP_XSPI_RESPONDER peripheral base addresses */ #define WAKEUP_XSPI_RESPONDER_BASE_ADDRS { WAKEUP__XSPI_RESPONDER_BASE } /** Array initializer of WAKEUP_XSPI_RESPONDER peripheral base pointers */ #define WAKEUP_XSPI_RESPONDER_BASE_PTRS { WAKEUP__XSPI_RESPONDER } /*! * @} */ /* end of group WAKEUP_XSPI_RESPONDER_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- WDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer * @{ */ /** WDOG - Register Layout Typedef */ typedef struct { __IO uint32_t CS; /**< WDOG Control and Status, offset: 0x0 */ __IO uint32_t CNT; /**< WDOG Counter, offset: 0x4 */ __IO uint32_t TOVAL; /**< WDOG Timeout Value, offset: 0x8 */ __IO uint32_t WIN; /**< Watchdog Window, offset: 0xC */ } WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /*! @name CS - WDOG Control and Status */ /*! @{ */ #define WDOG_CS_STOP_MASK (0x1U) #define WDOG_CS_STOP_SHIFT (0U) /*! STOP - Stop Enable * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) #define WDOG_CS_WAIT_MASK (0x2U) #define WDOG_CS_WAIT_SHIFT (1U) /*! WAIT - Wait Enable * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) #define WDOG_CS_DBG_MASK (0x4U) #define WDOG_CS_DBG_SHIFT (2U) /*! DBG - Debug Enable * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) #define WDOG_CS_TST_MASK (0x18U) #define WDOG_CS_TST_SHIFT (3U) /*! TST - WDOG Test * 0b00..Disable WDOG Test mode * 0b01..Enable WDOG User mode * 0b10-0b11..Enable WDOG Test mode */ #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) #define WDOG_CS_UPDATE_MASK (0x20U) #define WDOG_CS_UPDATE_SHIFT (5U) /*! UPDATE - Updates Allowed * 0b0..Updates not allowed * 0b1..Updates allowed */ #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) #define WDOG_CS_INT_MASK (0x40U) #define WDOG_CS_INT_SHIFT (6U) /*! INT - WDOG Interrupt * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) #define WDOG_CS_EN_MASK (0x80U) #define WDOG_CS_EN_SHIFT (7U) /*! EN - WDOG Enable * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) #define WDOG_CS_CLK_MASK (0x300U) #define WDOG_CS_CLK_SHIFT (8U) /*! CLK - WDOG Clock * 0b00..IPG * 0b01..LPO * 0b10..INT * 0b11..EXT */ #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) #define WDOG_CS_RCS_MASK (0x400U) #define WDOG_CS_RCS_SHIFT (10U) /*! RCS - Reconfiguration Success * 0b0..Unsuccessful * 0b1..Successful */ #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_RCS_SHIFT)) & WDOG_CS_RCS_MASK) #define WDOG_CS_ULK_MASK (0x800U) #define WDOG_CS_ULK_SHIFT (11U) /*! ULK - Unlock Status * 0b0..Locked * 0b1..Unlocked */ #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_ULK_SHIFT)) & WDOG_CS_ULK_MASK) #define WDOG_CS_PRES_MASK (0x1000U) #define WDOG_CS_PRES_SHIFT (12U) /*! PRES - WDOG Prescaler * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) #define WDOG_CS_CMD32EN_MASK (0x2000U) #define WDOG_CS_CMD32EN_SHIFT (13U) /*! CMD32EN - Command 32 Enable * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) #define WDOG_CS_FLG_MASK (0x4000U) #define WDOG_CS_FLG_SHIFT (14U) /*! FLG - WDOG Interrupt Flag * 0b0..No interrupt occurred * 0b1..An interrupt occurred */ #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) #define WDOG_CS_WIN_MASK (0x8000U) #define WDOG_CS_WIN_SHIFT (15U) /*! WIN - WDOG Window * 0b0..Disable * 0b1..Enable */ #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) /*! @} */ /*! @name CNT - WDOG Counter */ /*! @{ */ #define WDOG_CNT_CNTLOW_MASK (0xFFU) #define WDOG_CNT_CNTLOW_SHIFT (0U) /*! CNTLOW - Counter High Byte */ #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) #define WDOG_CNT_CNTHIGH_MASK (0xFF00U) #define WDOG_CNT_CNTHIGH_SHIFT (8U) /*! CNTHIGH - Counter Low Byte */ #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) /*! @} */ /*! @name TOVAL - WDOG Timeout Value */ /*! @{ */ #define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define WDOG_TOVAL_TOVALLOW_SHIFT (0U) /*! TOVALLOW - Timeout Value Low */ #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) #define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) /*! TOVALHIGH - Timeout Value High */ #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) /*! @} */ /*! @name WIN - Watchdog Window */ /*! @{ */ #define WDOG_WIN_WINLOW_MASK (0xFFU) #define WDOG_WIN_WINLOW_SHIFT (0U) /*! WINLOW - Low Byte */ #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) #define WDOG_WIN_WINHIGH_MASK (0xFF00U) #define WDOG_WIN_WINHIGH_SHIFT (8U) /*! WINHIGH - High Byte */ #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) /*! @} */ /*! * @} */ /* end of group WDOG_Register_Masks */ /* WDOG - Peripheral instance base addresses */ /** Peripheral WDOG1 base address */ #define WDOG1_BASE (0x442D0000u) /** Peripheral WDOG1 base pointer */ #define WDOG1 ((WDOG_Type *)WDOG1_BASE) /** Peripheral WDOG2 base address */ #define WDOG2_BASE (0x442E0000u) /** Peripheral WDOG2 base pointer */ #define WDOG2 ((WDOG_Type *)WDOG2_BASE) /** Peripheral WDOG3 base address */ #define WDOG3_BASE (0x42490000u) /** Peripheral WDOG3 base pointer */ #define WDOG3 ((WDOG_Type *)WDOG3_BASE) /** Peripheral WDOG4 base address */ #define WDOG4_BASE (0x424A0000u) /** Peripheral WDOG4 base pointer */ #define WDOG4 ((WDOG_Type *)WDOG4_BASE) /** Peripheral WDOG5 base address */ #define WDOG5_BASE (0x424B0000u) /** Peripheral WDOG5 base pointer */ #define WDOG5 ((WDOG_Type *)WDOG5_BASE) /** Array initializer of WDOG peripheral base addresses */ #define WDOG_BASE_ADDRS { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE, WDOG4_BASE, WDOG5_BASE } /** Array initializer of WDOG peripheral base pointers */ #define WDOG_BASE_PTRS { WDOG1, WDOG2, WDOG3, WDOG4, WDOG5 } /* Extra definition */ #define WDOG_UPDATE_KEY (0xD928C520U) #define WDOG_REFRESH_KEY (0xB480A602U) /*! * @} */ /* end of group WDOG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- XCACHE Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup XCACHE_Peripheral_Access_Layer XCACHE Peripheral Access Layer * @{ */ /** XCACHE - Register Layout Typedef */ typedef struct { __IO uint32_t CCR; /**< Cache Control, offset: 0x0 */ __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ __IO uint32_t CSAR; /**< Cache Search Address, offset: 0x8 */ __IO uint32_t CCVR; /**< Cache Read/Write Value, offset: 0xC */ } XCACHE_Type; /* ---------------------------------------------------------------------------- -- XCACHE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup XCACHE_Register_Masks XCACHE Register Masks * @{ */ /*! @name CCR - Cache Control */ /*! @{ */ #define XCACHE_CCR_ENCACHE_MASK (0x1U) #define XCACHE_CCR_ENCACHE_SHIFT (0U) /*! ENCACHE - Cache Enable * 0b0..Disable * 0b1..Enable */ #define XCACHE_CCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_ENCACHE_SHIFT)) & XCACHE_CCR_ENCACHE_MASK) #define XCACHE_CCR_FRCWT_MASK (0x4U) #define XCACHE_CCR_FRCWT_SHIFT (2U) /*! FRCWT - Force Write Through Mode * 0b0..Not force * 0b1..Force */ #define XCACHE_CCR_FRCWT(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_FRCWT_SHIFT)) & XCACHE_CCR_FRCWT_MASK) #define XCACHE_CCR_FRCNOALLC_MASK (0x8U) #define XCACHE_CCR_FRCNOALLC_SHIFT (3U) /*! FRCNOALLC - Force No Allocation on Cache Misses * 0b0..Allocate on cache misses * 0b1..Force no allocation on cache misses */ #define XCACHE_CCR_FRCNOALLC(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_FRCNOALLC_SHIFT)) & XCACHE_CCR_FRCNOALLC_MASK) #define XCACHE_CCR_INVW0_MASK (0x1000000U) #define XCACHE_CCR_INVW0_SHIFT (24U) /*! INVW0 - Invalidate Way 0 * 0b0..No operation * 0b1..Invalidate all lines in way 0 */ #define XCACHE_CCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_INVW0_SHIFT)) & XCACHE_CCR_INVW0_MASK) #define XCACHE_CCR_PUSHW0_MASK (0x2000000U) #define XCACHE_CCR_PUSHW0_SHIFT (25U) /*! PUSHW0 - Push Way 0 * 0b0..No operation * 0b1..Pushes all modified lines in way 0 */ #define XCACHE_CCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_PUSHW0_SHIFT)) & XCACHE_CCR_PUSHW0_MASK) #define XCACHE_CCR_INVW1_MASK (0x4000000U) #define XCACHE_CCR_INVW1_SHIFT (26U) /*! INVW1 - Invalidate Way 1 * 0b0..No operation * 0b1..Invalidate all lines in way 1 */ #define XCACHE_CCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_INVW1_SHIFT)) & XCACHE_CCR_INVW1_MASK) #define XCACHE_CCR_PUSHW1_MASK (0x8000000U) #define XCACHE_CCR_PUSHW1_SHIFT (27U) /*! PUSHW1 - Push Way 1 * 0b0..No operation * 0b1..Push all modified lines in way 1 */ #define XCACHE_CCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_PUSHW1_SHIFT)) & XCACHE_CCR_PUSHW1_MASK) #define XCACHE_CCR_GO_MASK (0x80000000U) #define XCACHE_CCR_GO_SHIFT (31U) /*! GO - Initiate Cache Command * 0b0..Write: no effect; Read: no cache command active * 0b1..Write: initiate command; Read: cache command active */ #define XCACHE_CCR_GO(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCR_GO_SHIFT)) & XCACHE_CCR_GO_MASK) /*! @} */ /*! @name CLCR - Cache Line Control */ /*! @{ */ #define XCACHE_CLCR_LGO_MASK (0x1U) #define XCACHE_CLCR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect; Read: no line command active * 0b1..Write: initiate line command; Read: line command active */ #define XCACHE_CLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LGO_SHIFT)) & XCACHE_CLCR_LGO_MASK) #define XCACHE_CLCR_CACHEADDR_MASK (0x3FFCU) #define XCACHE_CLCR_CACHEADDR_SHIFT (2U) /*! CACHEADDR - Cache Address */ #define XCACHE_CLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_CACHEADDR_SHIFT)) & XCACHE_CLCR_CACHEADDR_MASK) #define XCACHE_CLCR_WSEL_MASK (0x4000U) #define XCACHE_CLCR_WSEL_SHIFT (14U) /*! WSEL - Way Select * 0b0..Way 0 * 0b1..Way 1 */ #define XCACHE_CLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_WSEL_SHIFT)) & XCACHE_CLCR_WSEL_MASK) #define XCACHE_CLCR_TDSEL_MASK (0x10000U) #define XCACHE_CLCR_TDSEL_SHIFT (16U) /*! TDSEL - Tag or Data Select * 0b0..Data * 0b1..Tag */ #define XCACHE_CLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_TDSEL_SHIFT)) & XCACHE_CLCR_TDSEL_MASK) #define XCACHE_CLCR_LCIVB_MASK (0x100000U) #define XCACHE_CLCR_LCIVB_SHIFT (20U) /*! LCIVB - Line Command Initial Valid */ #define XCACHE_CLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCIVB_SHIFT)) & XCACHE_CLCR_LCIVB_MASK) #define XCACHE_CLCR_LCIMB_MASK (0x200000U) #define XCACHE_CLCR_LCIMB_SHIFT (21U) /*! LCIMB - Line Command Initial Modified */ #define XCACHE_CLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCIMB_SHIFT)) & XCACHE_CLCR_LCIMB_MASK) #define XCACHE_CLCR_LCWAY_MASK (0x400000U) #define XCACHE_CLCR_LCWAY_SHIFT (22U) /*! LCWAY - Line Command Way */ #define XCACHE_CLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCWAY_SHIFT)) & XCACHE_CLCR_LCWAY_MASK) #define XCACHE_CLCR_LCMD_MASK (0x3000000U) #define XCACHE_CLCR_LCMD_SHIFT (24U) /*! LCMD - Line Command * 0b00..Search and read or write * 0b01..Invalidate * 0b10..Push * 0b11..Clear */ #define XCACHE_CLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LCMD_SHIFT)) & XCACHE_CLCR_LCMD_MASK) #define XCACHE_CLCR_LADSEL_MASK (0x4000000U) #define XCACHE_CLCR_LADSEL_SHIFT (26U) /*! LADSEL - Line Address Select * 0b0..Cache address * 0b1..Physical address */ #define XCACHE_CLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LADSEL_SHIFT)) & XCACHE_CLCR_LADSEL_MASK) #define XCACHE_CLCR_LACC_MASK (0x8000000U) #define XCACHE_CLCR_LACC_SHIFT (27U) /*! LACC - Line Access Type * 0b0..Read * 0b1..Write */ #define XCACHE_CLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CLCR_LACC_SHIFT)) & XCACHE_CLCR_LACC_MASK) /*! @} */ /*! @name CSAR - Cache Search Address */ /*! @{ */ #define XCACHE_CSAR_LGO_MASK (0x1U) #define XCACHE_CSAR_LGO_SHIFT (0U) /*! LGO - Initiate Cache Line Command * 0b0..Write: no effect; Read: no line command active * 0b1..Write: initiate line command; Read: line command active */ #define XCACHE_CSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CSAR_LGO_SHIFT)) & XCACHE_CSAR_LGO_MASK) #define XCACHE_CSAR_PHYADDR_MASK (0xFFFFFFFCU) #define XCACHE_CSAR_PHYADDR_SHIFT (2U) /*! PHYADDR - Physical Address */ #define XCACHE_CSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CSAR_PHYADDR_SHIFT)) & XCACHE_CSAR_PHYADDR_MASK) /*! @} */ /*! @name CCVR - Cache Read/Write Value */ /*! @{ */ #define XCACHE_CCVR_DATA_MASK (0xFFFFFFFFU) #define XCACHE_CCVR_DATA_SHIFT (0U) /*! DATA - Cache Read/Write Data */ #define XCACHE_CCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << XCACHE_CCVR_DATA_SHIFT)) & XCACHE_CCVR_DATA_MASK) /*! @} */ /*! * @} */ /* end of group XCACHE_Register_Masks */ /* XCACHE - Peripheral instance base addresses */ /** Peripheral M33_CACHE_CTRLPC base address */ #define M33_CACHE_CTRLPC_BASE (0x44400000u) /** Peripheral M33_CACHE_CTRLPC base pointer */ #define M33_CACHE_CTRLPC ((XCACHE_Type *)M33_CACHE_CTRLPC_BASE) /** Peripheral M33_CACHE_CTRLPS base address */ #define M33_CACHE_CTRLPS_BASE (0x44400800u) /** Peripheral M33_CACHE_CTRLPS base pointer */ #define M33_CACHE_CTRLPS ((XCACHE_Type *)M33_CACHE_CTRLPS_BASE) /** Array initializer of XCACHE peripheral base addresses */ #define XCACHE_BASE_ADDRS { M33_CACHE_CTRLPC_BASE, M33_CACHE_CTRLPS_BASE } /** Array initializer of XCACHE peripheral base pointers */ #define XCACHE_BASE_PTRS { M33_CACHE_CTRLPC, M33_CACHE_CTRLPS } /*! * @} */ /* end of group XCACHE_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ieprc_ierb Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ieprc_ierb_Peripheral_Access_Layer ieprc_ierb Peripheral Access Layer * @{ */ /** ieprc_ierb - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x20 */ __IO uint32_t B_EC_F0_CFH_DIDVID; /**< Bus n EC Function 0 config header device ID and vendor ID register, array offset: 0x0, array step: 0x20 */ __IO uint32_t B_EC_F0_CFH_SIDSVID; /**< Bus n EC Function 0 config header subsystem ID and subsystem vendor ID register, array offset: 0x4, array step: 0x20 */ __IO uint32_t B_EC_F0_CFH_REVID; /**< Bus n EC Function 0 config header revision register, array offset: 0x8, array step: 0x20 */ uint8_t RESERVED_0[20]; } BUSX[2]; uint8_t RESERVED_0[8128]; __I uint32_t CAP0; /**< Capability 0 register, offset: 0x2000 */ uint8_t RESERVED_1[12]; __IO uint32_t EC_CFG; /**< EC Configuration register, offset: 0x2010 */ } ieprc_ierb_Type; /* ---------------------------------------------------------------------------- -- ieprc_ierb Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ieprc_ierb_Register_Masks ieprc_ierb Register Masks * @{ */ /*! @name B_EC_F0_CFH_DIDVID - Bus n EC Function 0 config header device ID and vendor ID register */ /*! @{ */ #define ieprc_ierb_B_EC_F0_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) #define ieprc_ierb_B_EC_F0_CFH_DIDVID_VENDOR_ID_SHIFT (0U) #define ieprc_ierb_B_EC_F0_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_B_EC_F0_CFH_DIDVID_VENDOR_ID_SHIFT)) & ieprc_ierb_B_EC_F0_CFH_DIDVID_VENDOR_ID_MASK) #define ieprc_ierb_B_EC_F0_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) #define ieprc_ierb_B_EC_F0_CFH_DIDVID_DEVICE_ID_SHIFT (16U) #define ieprc_ierb_B_EC_F0_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_B_EC_F0_CFH_DIDVID_DEVICE_ID_SHIFT)) & ieprc_ierb_B_EC_F0_CFH_DIDVID_DEVICE_ID_MASK) /*! @} */ /* The count of ieprc_ierb_B_EC_F0_CFH_DIDVID */ #define ieprc_ierb_B_EC_F0_CFH_DIDVID_COUNT (2U) /*! @name B_EC_F0_CFH_SIDSVID - Bus n EC Function 0 config header subsystem ID and subsystem vendor ID register */ /*! @{ */ #define ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) #define ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) #define ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) #define ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) #define ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) #define ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & ieprc_ierb_B_EC_F0_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) /*! @} */ /* The count of ieprc_ierb_B_EC_F0_CFH_SIDSVID */ #define ieprc_ierb_B_EC_F0_CFH_SIDSVID_COUNT (2U) /*! @name B_EC_F0_CFH_REVID - Bus n EC Function 0 config header revision register */ /*! @{ */ #define ieprc_ierb_B_EC_F0_CFH_REVID_REVISION_ID_MASK (0xFFU) #define ieprc_ierb_B_EC_F0_CFH_REVID_REVISION_ID_SHIFT (0U) #define ieprc_ierb_B_EC_F0_CFH_REVID_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_B_EC_F0_CFH_REVID_REVISION_ID_SHIFT)) & ieprc_ierb_B_EC_F0_CFH_REVID_REVISION_ID_MASK) /*! @} */ /* The count of ieprc_ierb_B_EC_F0_CFH_REVID */ #define ieprc_ierb_B_EC_F0_CFH_REVID_COUNT (2U) /*! @name CAP0 - Capability 0 register */ /*! @{ */ #define ieprc_ierb_CAP0_NUM_EP_MASK (0x7U) #define ieprc_ierb_CAP0_NUM_EP_SHIFT (0U) #define ieprc_ierb_CAP0_NUM_EP(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_CAP0_NUM_EP_SHIFT)) & ieprc_ierb_CAP0_NUM_EP_MASK) #define ieprc_ierb_CAP0_INT_TYPE_MASK (0x8U) #define ieprc_ierb_CAP0_INT_TYPE_SHIFT (3U) #define ieprc_ierb_CAP0_INT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_CAP0_INT_TYPE_SHIFT)) & ieprc_ierb_CAP0_INT_TYPE_MASK) #define ieprc_ierb_CAP0_NUM_PCI_BUS_MASK (0x7F0000U) #define ieprc_ierb_CAP0_NUM_PCI_BUS_SHIFT (16U) #define ieprc_ierb_CAP0_NUM_PCI_BUS(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_CAP0_NUM_PCI_BUS_SHIFT)) & ieprc_ierb_CAP0_NUM_PCI_BUS_MASK) #define ieprc_ierb_CAP0_NUM_RCEC_MASK (0x7F000000U) #define ieprc_ierb_CAP0_NUM_RCEC_SHIFT (24U) #define ieprc_ierb_CAP0_NUM_RCEC(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_CAP0_NUM_RCEC_SHIFT)) & ieprc_ierb_CAP0_NUM_RCEC_MASK) /*! @} */ /*! @name EC_CFG - EC Configuration register */ /*! @{ */ #define ieprc_ierb_EC_CFG_FUNC_NUM_MASK (0x7U) #define ieprc_ierb_EC_CFG_FUNC_NUM_SHIFT (0U) #define ieprc_ierb_EC_CFG_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_EC_CFG_FUNC_NUM_SHIFT)) & ieprc_ierb_EC_CFG_FUNC_NUM_MASK) #define ieprc_ierb_EC_CFG_DEV_NUM_MASK (0xF8U) #define ieprc_ierb_EC_CFG_DEV_NUM_SHIFT (3U) #define ieprc_ierb_EC_CFG_DEV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ieprc_ierb_EC_CFG_DEV_NUM_SHIFT)) & ieprc_ierb_EC_CFG_DEV_NUM_MASK) /*! @} */ /*! * @} */ /* end of group ieprc_ierb_Register_Masks */ /* ieprc_ierb - Peripheral instance base addresses */ /** Peripheral NETC__IEPRC_1__IEPRC_IERB base address */ #define NETC__IEPRC_1__IEPRC_IERB_BASE (0x4C8A0000u) /** Peripheral NETC__IEPRC_1__IEPRC_IERB base pointer */ #define NETC__IEPRC_1__IEPRC_IERB ((ieprc_ierb_Type *)NETC__IEPRC_1__IEPRC_IERB_BASE) /** Array initializer of ieprc_ierb peripheral base addresses */ #define ieprc_ierb_BASE_ADDRS { NETC__IEPRC_1__IEPRC_IERB_BASE } /** Array initializer of ieprc_ierb peripheral base pointers */ #define ieprc_ierb_BASE_PTRS { NETC__IEPRC_1__IEPRC_IERB } /*! * @} */ /* end of group ieprc_ierb_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ieprc_pci Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ieprc_pci_Peripheral_Access_Layer ieprc_pci Peripheral Access Layer * @{ */ /** ieprc_pci - Register Layout Typedef */ typedef struct { __I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset: 0x0 */ __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */ __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */ __I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offset: 0x8 */ __IO uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */ uint8_t RESERVED_0[1]; __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */ uint8_t RESERVED_1[29]; __I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x2C */ __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */ uint8_t RESERVED_2[4]; __I uint8_t PCI_CFH_CAP_PTR; /**< PCI capabilities pointer register, offset: 0x34 */ uint8_t RESERVED_3[7]; __IO uint8_t PCI_CFH_INT_LINE; /**< PCI interrupt line register, offset: 0x3C */ __I uint8_t PCI_CFH_INT_PIN; /**< PCI interrupt pin register, offset: 0x3D */ uint8_t RESERVED_4[2]; __I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset: 0x40 */ __I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42 */ __I uint32_t PCI_CFC_PCIE_DEV_CAP; /**< PCI PCIe device capabilities register, offset: 0x44 */ uint8_t RESERVED_5[2]; __I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4A */ uint8_t RESERVED_6[16]; __IO uint16_t PCI_CFC_PCIE_ROOT_CTL; /**< PCI PCIe root control register, offset: 0x5C */ uint8_t RESERVED_7[2]; __IO uint32_t PCI_CFC_PCIE_ROOT_STAT; /**< PCI PCIe root status register, offset: 0x60 */ uint8_t RESERVED_8[28]; __I uint16_t PCI_CFC_PCIPM_CAP_LIST; /**< PCI PCI-PM capabilities list register, offset: 0x80 */ __I uint16_t PCI_CFC_PCIPM_CAP; /**< PCI PCI-PM capabilities register, offset: 0x82 */ __IO uint16_t PCI_CFC_PCIPM_CTL_STAT; /**< PCI PCI-PM control and status register, offset: 0x84 */ uint8_t RESERVED_9[1]; uint8_t PCI_CFC_PCIPM_DATA; /**< PCI PCI-PM capabilities data register, offset: 0x87 */ uint8_t RESERVED_10[120]; __I uint32_t PCIE_CFC_AER_EXT_CAP_HDR; /**< PCIe AER extended capability header, offset: 0x100 */ uint8_t RESERVED_11[40]; __IO uint32_t PCIE_CFC_AER_ROOT_ERR_CMD; /**< PCIe AER root error command register, offset: 0x12C */ __IO uint32_t PCIE_CFC_AER_ROOT_ERR_STAT; /**< PCIe AER root error status register, offset: 0x130 */ __I uint32_t PCIE_CFC_AER_ERR_SRC_ID; /**< PCIe AER error source identification register, offset: 0x134 */ __I uint32_t PCIE_CFC_RCEC_EPA_EXT_CAP_HDR; /**< PCIe RCEC Endpoint association extended capability header, offset: 0x138 */ __I uint32_t PCIE_CFC_RCEC_EPA_BITMAP; /**< PCIe RCEC Endpoint association bitmap register, offset: 0x13C */ } ieprc_pci_Type; /* ---------------------------------------------------------------------------- -- ieprc_pci Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ieprc_pci_Register_Masks ieprc_pci Register Masks * @{ */ /*! @name PCI_CFH_DID_VID - PCI device ID and vendor ID register */ /*! @{ */ #define ieprc_pci_PCI_CFH_DID_VID_VENDOR_ID_MASK (0xFFFFU) #define ieprc_pci_PCI_CFH_DID_VID_VENDOR_ID_SHIFT (0U) #define ieprc_pci_PCI_CFH_DID_VID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFH_DID_VID_VENDOR_ID_SHIFT)) & ieprc_pci_PCI_CFH_DID_VID_VENDOR_ID_MASK) #define ieprc_pci_PCI_CFH_DID_VID_DEVICE_ID_MASK (0xFFFF0000U) #define ieprc_pci_PCI_CFH_DID_VID_DEVICE_ID_SHIFT (16U) #define ieprc_pci_PCI_CFH_DID_VID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFH_DID_VID_DEVICE_ID_SHIFT)) & ieprc_pci_PCI_CFH_DID_VID_DEVICE_ID_MASK) /*! @} */ /*! @name PCI_CFH_CMD - PCI command register */ /*! @{ */ #define ieprc_pci_PCI_CFH_CMD_INTR_DISABLE_MASK (0x400U) #define ieprc_pci_PCI_CFH_CMD_INTR_DISABLE_SHIFT (10U) #define ieprc_pci_PCI_CFH_CMD_INTR_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFH_CMD_INTR_DISABLE_SHIFT)) & ieprc_pci_PCI_CFH_CMD_INTR_DISABLE_MASK) /*! @} */ /*! @name PCI_CFH_STAT - PCI status register */ /*! @{ */ #define ieprc_pci_PCI_CFH_STAT_INTR_STATUS_MASK (0x8U) #define ieprc_pci_PCI_CFH_STAT_INTR_STATUS_SHIFT (3U) #define ieprc_pci_PCI_CFH_STAT_INTR_STATUS(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFH_STAT_INTR_STATUS_SHIFT)) & ieprc_pci_PCI_CFH_STAT_INTR_STATUS_MASK) #define ieprc_pci_PCI_CFH_STAT_CAP_LIST_MASK (0x10U) #define ieprc_pci_PCI_CFH_STAT_CAP_LIST_SHIFT (4U) #define ieprc_pci_PCI_CFH_STAT_CAP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFH_STAT_CAP_LIST_SHIFT)) & ieprc_pci_PCI_CFH_STAT_CAP_LIST_MASK) /*! @} */ /*! @name PCI_CFH_REVID_CLASSCODE - PCI revision ID and classcode register */ /*! @{ */ #define ieprc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK (0xFFU) #define ieprc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT (0U) #define ieprc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT)) & ieprc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK) #define ieprc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK (0xFFFFFF00U) #define ieprc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT (8U) #define ieprc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT)) & ieprc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK) /*! @} */ /*! @name PCI_CFH_CL_SIZE - PCI cache line size register */ /*! @{ */ #define ieprc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK (0xFFU) #define ieprc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT (0U) #define ieprc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE(x) (((uint8_t)(((uint8_t)(x)) << ieprc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT)) & ieprc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK) /*! @} */ /*! @name PCI_CFH_HDR_TYPE - PCI header type register */ /*! @{ */ #define ieprc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK (0x7FU) #define ieprc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT (0U) #define ieprc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE(x) (((uint8_t)(((uint8_t)(x)) << ieprc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT)) & ieprc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK) #define ieprc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK (0x80U) #define ieprc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT (7U) #define ieprc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV(x) (((uint8_t)(((uint8_t)(x)) << ieprc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT)) & ieprc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK) /*! @} */ /*! @name PCI_CFH_SUBSYS_VID - PCI subsystem vendor ID register */ /*! @{ */ #define ieprc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) #define ieprc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) #define ieprc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT)) & ieprc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK) /*! @} */ /*! @name PCI_CFH_SUBSYS_ID - PCI subsystem ID register */ /*! @{ */ #define ieprc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK (0xFFFFU) #define ieprc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT (0U) #define ieprc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT)) & ieprc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK) /*! @} */ /*! @name PCI_CFH_CAP_PTR - PCI capabilities pointer register */ /*! @{ */ #define ieprc_pci_PCI_CFH_CAP_PTR_CAP_PTR_MASK (0xFFU) #define ieprc_pci_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT (0U) #define ieprc_pci_PCI_CFH_CAP_PTR_CAP_PTR(x) (((uint8_t)(((uint8_t)(x)) << ieprc_pci_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT)) & ieprc_pci_PCI_CFH_CAP_PTR_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFH_INT_LINE - PCI interrupt line register */ /*! @{ */ #define ieprc_pci_PCI_CFH_INT_LINE_INT_LINE_MASK (0xFFU) #define ieprc_pci_PCI_CFH_INT_LINE_INT_LINE_SHIFT (0U) #define ieprc_pci_PCI_CFH_INT_LINE_INT_LINE(x) (((uint8_t)(((uint8_t)(x)) << ieprc_pci_PCI_CFH_INT_LINE_INT_LINE_SHIFT)) & ieprc_pci_PCI_CFH_INT_LINE_INT_LINE_MASK) /*! @} */ /*! @name PCI_CFH_INT_PIN - PCI interrupt pin register */ /*! @{ */ #define ieprc_pci_PCI_CFH_INT_PIN_INT_PIN_MASK (0xFFU) #define ieprc_pci_PCI_CFH_INT_PIN_INT_PIN_SHIFT (0U) #define ieprc_pci_PCI_CFH_INT_PIN_INT_PIN(x) (((uint8_t)(((uint8_t)(x)) << ieprc_pci_PCI_CFH_INT_PIN_INT_PIN_SHIFT)) & ieprc_pci_PCI_CFH_INT_PIN_INT_PIN_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_CAP_LIST - PCI PCIe capabilities list register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK (0xFFU) #define ieprc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT (0U) #define ieprc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK) #define ieprc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ieprc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ieprc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_CAP - PCI PCIe capabilities register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIE_CAP_CAP_VER_MASK (0xFU) #define ieprc_pci_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT (0U) #define ieprc_pci_PCI_CFC_PCIE_CAP_CAP_VER(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_CAP_CAP_VER_MASK) #define ieprc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK (0xF0U) #define ieprc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT (4U) #define ieprc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK) #define ieprc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK (0x3E00U) #define ieprc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT (9U) #define ieprc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_CAP - PCI PCIe device capabilities register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK (0x10000000U) #define ieprc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT (28U) #define ieprc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_DEV_STAT - PCI PCIe device status register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK (0x20U) #define ieprc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT (5U) #define ieprc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_ROOT_CTL - PCI PCIe root control register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_MASK (0x8U) #define ieprc_pci_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_SHIFT (3U) #define ieprc_pci_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_ROOT_CTL_PME_INT_EN_MASK) /*! @} */ /*! @name PCI_CFC_PCIE_ROOT_STAT - PCI PCIe root status register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_MASK (0xFFFFU) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_SHIFT (0U) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_REQ_ID_MASK) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_MASK (0x10000U) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_SHIFT (16U) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_STATUS_MASK) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_MASK (0x20000U) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_SHIFT (17U) #define ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_PEND(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_SHIFT)) & ieprc_pci_PCI_CFC_PCIE_ROOT_STAT_PME_PEND_MASK) /*! @} */ /*! @name PCI_CFC_PCIPM_CAP_LIST - PCI PCI-PM capabilities list register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK (0xFFU) #define ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT (0U) #define ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT)) & ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK) #define ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_MASK (0xFF00U) #define ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_SHIFT (8U) #define ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_SHIFT)) & ieprc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_PTR_MASK) /*! @} */ /*! @name PCI_CFC_PCIPM_CAP - PCI PCI-PM capabilities register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIPM_CAP_VERSION_MASK (0x7U) #define ieprc_pci_PCI_CFC_PCIPM_CAP_VERSION_SHIFT (0U) #define ieprc_pci_PCI_CFC_PCIPM_CAP_VERSION(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIPM_CAP_VERSION_SHIFT)) & ieprc_pci_PCI_CFC_PCIPM_CAP_VERSION_MASK) #define ieprc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK (0xF800U) #define ieprc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT (11U) #define ieprc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT)) & ieprc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK) /*! @} */ /*! @name PCI_CFC_PCIPM_CTL_STAT - PCI PCI-PM control and status register */ /*! @{ */ #define ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK (0x3U) #define ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT (0U) #define ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT)) & ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK) #define ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK (0x8U) #define ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT (3U) #define ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST(x) (((uint16_t)(((uint16_t)(x)) << ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT)) & ieprc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK) /*! @} */ /*! @name PCIE_CFC_AER_EXT_CAP_HDR - PCIe AER extended capability header */ /*! @{ */ #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT (16U) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT)) & ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ieprc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_AER_ROOT_ERR_CMD - PCIe AER root error command register */ /*! @{ */ #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_MASK (0x1U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_SHIFT (0U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_MASK (0x2U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_SHIFT (1U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_MASK (0x4U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_SHIFT (2U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_MASK) /*! @} */ /*! @name PCIE_CFC_AER_ROOT_ERR_STAT - PCIe AER root error status register */ /*! @{ */ #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_MASK (0x1U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_SHIFT (0U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_MASK (0x2U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_SHIFT (1U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_MASK (0x4U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_SHIFT (2U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_MASK (0x8U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_SHIFT (3U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_MASK (0x10U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_SHIFT (4U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_MASK (0x20U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_SHIFT (5U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_MASK) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_MASK (0x40U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_SHIFT (6U) #define ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_MASK) /*! @} */ /*! @name PCIE_CFC_AER_ERR_SRC_ID - PCIe AER error source identification register */ /*! @{ */ #define ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_MASK (0xFFFFU) #define ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_SHIFT (0U) #define ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_MASK) #define ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_MASK (0xFFFF0000U) #define ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_SHIFT (16U) #define ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_SHIFT)) & ieprc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_MASK) /*! @} */ /*! @name PCIE_CFC_RCEC_EPA_EXT_CAP_HDR - PCIe RCEC Endpoint association extended capability header */ /*! @{ */ #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_SHIFT (16U) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_SHIFT)) & ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_MASK) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) #define ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ieprc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_MASK) /*! @} */ /*! @name PCIE_CFC_RCEC_EPA_BITMAP - PCIe RCEC Endpoint association bitmap register */ /*! @{ */ #define ieprc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_MASK (0xFFFFFFFFU) #define ieprc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_SHIFT (0U) #define ieprc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP(x) (((uint32_t)(((uint32_t)(x)) << ieprc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_SHIFT)) & ieprc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_MASK) /*! @} */ /*! * @} */ /* end of group ieprc_pci_Register_Masks */ /* ieprc_pci - Peripheral instance base addresses */ /** Peripheral NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0 base address */ #define NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0_BASE (0x4CA08000u) /** Peripheral NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0 base pointer */ #define NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0 ((ieprc_pci_Type *)NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0_BASE) /** Peripheral NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0 base address */ #define NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0_BASE (0x4CB08000u) /** Peripheral NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0 base pointer */ #define NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0 ((ieprc_pci_Type *)NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0_BASE) /** Array initializer of ieprc_pci peripheral base addresses */ #define ieprc_pci_BASE_ADDRS { NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0_BASE, NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0_BASE } /** Array initializer of ieprc_pci peripheral base pointers */ #define ieprc_pci_BASE_PTRS { NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0, NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0 } /*! * @} */ /* end of group ieprc_pci_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ieprc_prb Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ieprc_prb_Peripheral_Access_Layer ieprc_prb Peripheral Access Layer * @{ */ /** ieprc_prb - Register Layout Typedef */ typedef struct { __IO uint32_t RR; /**< Reset register, offset: 0x0 */ uint8_t RESERVED_0[252]; __IO uint32_t EC_RR[2]; /**< EC Reset register, array offset: 0x100, array step: 0x4 */ } ieprc_prb_Type; /* ---------------------------------------------------------------------------- -- ieprc_prb Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ieprc_prb_Register_Masks ieprc_prb Register Masks * @{ */ /*! @name RR - Reset register */ /*! @{ */ #define ieprc_prb_RR_SR_MASK (0x1U) #define ieprc_prb_RR_SR_SHIFT (0U) /*! SR - Soft reset */ #define ieprc_prb_RR_SR(x) (((uint32_t)(((uint32_t)(x)) << ieprc_prb_RR_SR_SHIFT)) & ieprc_prb_RR_SR_MASK) #define ieprc_prb_RR_LOCK_MASK (0x2U) #define ieprc_prb_RR_LOCK_SHIFT (1U) /*! LOCK - Lock */ #define ieprc_prb_RR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ieprc_prb_RR_LOCK_SHIFT)) & ieprc_prb_RR_LOCK_MASK) /*! @} */ /*! @name EC_RR - EC Reset register */ /*! @{ */ #define ieprc_prb_EC_RR_ECSR_MASK (0x1U) #define ieprc_prb_EC_RR_ECSR_SHIFT (0U) /*! ECSR - EC Soft reset */ #define ieprc_prb_EC_RR_ECSR(x) (((uint32_t)(((uint32_t)(x)) << ieprc_prb_EC_RR_ECSR_SHIFT)) & ieprc_prb_EC_RR_ECSR_MASK) /*! @} */ /* The count of ieprc_prb_EC_RR */ #define ieprc_prb_EC_RR_COUNT (2U) /*! * @} */ /* end of group ieprc_prb_Register_Masks */ /* ieprc_prb - Peripheral instance base addresses */ /** Peripheral NETC__IEPRC_1__IEPRC_PRB base address */ #define NETC__IEPRC_1__IEPRC_PRB_BASE (0x4C8B0000u) /** Peripheral NETC__IEPRC_1__IEPRC_PRB base pointer */ #define NETC__IEPRC_1__IEPRC_PRB ((ieprc_prb_Type *)NETC__IEPRC_1__IEPRC_PRB_BASE) /** Array initializer of ieprc_prb peripheral base addresses */ #define ieprc_prb_BASE_ADDRS { NETC__IEPRC_1__IEPRC_PRB_BASE } /** Array initializer of ieprc_prb peripheral base pointers */ #define ieprc_prb_BASE_PTRS { NETC__IEPRC_1__IEPRC_PRB } /*! * @} */ /* end of group ieprc_prb_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- neutrons Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup neutrons_Peripheral_Access_Layer neutrons Peripheral Access Layer * @{ */ /** neutrons - Register Layout Typedef */ typedef struct { __IO uint32_t RESETCTRL; /**< Reset and Control, offset: 0x0 */ __IO uint32_t STATUSERR; /**< Zen-V Status and Error, offset: 0x4 */ __IO uint32_t INTENA; /**< Interrupt Enable For SoC, offset: 0x8 */ __IO uint32_t INTCLR; /**< Interrupt Clear For SoC, offset: 0xC */ __IO uint32_t CYCLOW; /**< Cycle Counter, offset: 0x10 */ __IO uint32_t CYCHIGH; /**< Cycle Counter, offset: 0x14 */ __IO uint32_t DDRLATENT; /**< DDR Latency Performance Counter, offset: 0x18 */ __IO uint32_t DDRSPREAD; /**< DDR Data Read Spread Performance Counter, offset: 0x1C */ __IO uint32_t DDRRCNTS; /**< DDR Read Performance Counter, offset: 0x20 */ __IO uint32_t DDRWWORDS; /**< DDR Write Performance Counter, offset: 0x24 */ __IO uint32_t DDRRWORDS; /**< DDR Read Word Performance Counter, offset: 0x28 */ __IO uint32_t DDRSTALL; /**< DDR Stall Performance Counter, offset: 0x2C */ __IO uint32_t NSTALL; /**< Neutron Stall Performance Counter, offset: 0x30 */ __IO uint32_t NACT; /**< Neutron active performance counter, offset: 0x34 */ uint8_t RESERVED_0[24]; __IO uint32_t EVTRCCFG; /**< Optional Event Trace configure/control, offset: 0x50 */ __IO uint32_t EVTRCDATA; /**< Optional Event Trace Software submission, offset: 0x54 */ uint8_t RESERVED_1[8]; __IO uint32_t ZVIV2P0; /**< Zen-V Code Virtual to Physical, offset: 0x60 */ __IO uint32_t ZVIV2P1; /**< Zen-V Code Virtual to Physical, offset: 0x64 */ __IO uint32_t ZVIV2P2; /**< Zen-V Code Virtual to Physical, offset: 0x68 */ __IO uint32_t ZVIV2P3; /**< Zen-V Code Virtual to Physical, offset: 0x6C */ uint8_t RESERVED_2[16]; __IO uint32_t TTCTRL; /**< TCM-to-TCM Control, offset: 0x80 */ __IO uint32_t TTSADDR; /**< TCM-to-TCM Source Address, offset: 0x84 */ __IO uint32_t TTDADDR; /**< TCM-to-TCM Destination Address, offset: 0x88 */ __IO uint32_t TTCTRL2; /**< TCM-to-TCM Control 2, offset: 0x8C */ __IO uint32_t CONFIG; /**< Configuration, offset: 0x90 */ __I uint32_t STATUS; /**< Data mover status, offset: 0x94 */ __IO uint32_t DFORDER; /**< Data Fetch Order Manager, offset: 0x98 */ __IO uint32_t DPORDER; /**< Data Push Order Manager, offset: 0x9C */ union { /* offset: 0xA0 */ __IO uint32_t DCTRL0_FETCH; /**< Push and Fetch Control, offset: 0xA0 */ __IO uint32_t DCTRL0_PUSH; /**< Push and Fetch Control, offset: 0xA0 */ }; union { /* offset: 0xA4 */ __IO uint32_t DCTRL1_FETCH; /**< Push and Fetch Control, offset: 0xA4 */ __IO uint32_t DCTRL1_PUSH; /**< Push and Fetch Control, offset: 0xA4 */ }; union { /* offset: 0xA8 */ __IO uint32_t DCTRL2_FETCH; /**< Push and Fetch Control, offset: 0xA8 */ __IO uint32_t DCTRL2_PUSH; /**< Push and Fetch Control, offset: 0xA8 */ }; union { /* offset: 0xAC */ __IO uint32_t DCTRL3_FETCH; /**< Push and Fetch Control, offset: 0xAC */ __IO uint32_t DCTRL3_PUSH; /**< Push and Fetch Control, offset: 0xAC */ }; __IO uint32_t DSADDR0; /**< Push and Fetch Source Address, offset: 0xB0 */ __IO uint32_t DSADDR1; /**< Push and Fetch Source Address, offset: 0xB4 */ __IO uint32_t DSADDR2; /**< Push and Fetch Source Address, offset: 0xB8 */ __IO uint32_t DSADDR3; /**< Push and Fetch Source Address, offset: 0xBC */ __IO uint32_t DDADDR0; /**< Push and Fetch Destination Address, offset: 0xC0 */ __IO uint32_t DDADDR1; /**< Push and Fetch Destination Address, offset: 0xC4 */ __IO uint32_t DDADDR2; /**< Push and Fetch Destination Address, offset: 0xC8 */ __IO uint32_t DDADDR3; /**< Push and Fetch Destination Address, offset: 0xCC */ __IO uint32_t DCTRL2_0; /**< Push_packed and Fetch Second Control, offset: 0xD0 */ __IO uint32_t DCTRL2_1; /**< Push_packed and Fetch Second Control, offset: 0xD4 */ __IO uint32_t DCTRL2_2; /**< Push_packed and Fetch Second Control, offset: 0xD8 */ __IO uint32_t DCTRL2_3; /**< Push_packed and Fetch Second Control, offset: 0xDC */ __IO uint32_t WCTRL; /**< Weight Fetch Control, offset: 0xE0 */ __IO uint32_t WSADDR; /**< Weight Fetch Source Address, offset: 0xE4 */ __IO uint32_t WDADDR; /**< Weight Fetch Destination Address, offset: 0xE8 */ uint8_t RESERVED_3[4]; __IO uint32_t DCTRL3_0; /**< Fetch Unpack Third Control, offset: 0xF0 */ __IO uint32_t DCTRL3_1; /**< Fetch Unpack Third Control, offset: 0xF4 */ __IO uint32_t DCTRL3_2; /**< Push pack Third Control, offset: 0xF8 */ __IO uint32_t DCTRL3_3; /**< Push pack Third Control, offset: 0xFC */ __IO uint32_t WCTRL2_0; /**< Weight Fetch Second Control, offset: 0x100 */ __IO uint32_t WCTRL3_0; /**< Weight Fetch Unpack Third Control, offset: 0x104 */ __O uint32_t WPEND1; /**< Weight Pend/Ready set, offset: 0x108 */ __O uint32_t WPEND2; /**< Weight Pend/Ready set, offset: 0x10C */ uint8_t RESERVED_4[240]; union { /* offset: 0x200 */ __IO uint32_t APPCTRL_SOC; /**< Application Control, offset: 0x200 */ __IO uint32_t APPCTRL_ZV; /**< Application Control, offset: 0x200 */ }; __IO uint32_t APPSTATUS; /**< Messages to SoC by Zen-V App using W1S, offset: 0x204 */ __IO uint32_t BASEDDRL; /**< Base physical address in DDR, offset: 0x208 */ __IO uint32_t BASEDDRH; /**< Base physical address in DDR, offset: 0x20C */ __IO uint32_t INPUT; /**< Offset of Input image from DDR Base, offset: 0x210 */ __IO uint32_t INPUT2; /**< Offset of Input image from DDR Base, offset: 0x214 */ __IO uint32_t OUTPUT; /**< Offset of Output results from DDR Base, offset: 0x218 */ __IO uint32_t OUTPUT2; /**< Offset of Output results from DDR Base, offset: 0x21C */ __IO uint32_t CODEOFF; /**< Offset of Zen-V code from BASEDDRn, offset: 0x220 */ __IO uint32_t DATAOFF; /**< Offset of Zen-V data from BASEDDRn, offset: 0x224 */ uint8_t RESERVED_5[8]; __IO uint32_t RINGCTRL; /**< Ring buffer control by Zen-V, offset: 0x230 */ uint8_t RESERVED_6[4]; __IO uint32_t TAIL; /**< Tail of ring buffer written by Zen-V, offset: 0x238 */ __IO uint32_t HEAD; /**< Head of ring buffer written by SoC, offset: 0x23C */ __IO uint32_t MBOX[8]; /**< Mailboxes For SoC/Zen-V Communications, array offset: 0x240, array step: 0x4 */ uint8_t RESERVED_7[32]; __IO uint32_t BASEINOUTL; /**< Base physical address for Input/Output fetch/push, offset: 0x280 */ __IO uint32_t BASEINOUTH; /**< Base physical address for Spill fetch/push, offset: 0x284 */ __IO uint32_t BASESPILLL; /**< Base physical address for Spill fetch/push, offset: 0x288 */ __IO uint32_t BASESPILLH; /**< Base physical address for Spill fetch/push, offset: 0x28C */ uint8_t RESERVED_8[112]; __IO uint32_t DECOMPCTRL; /**< Control For Weight Decompressor, offset: 0x300 */ __IO uint32_t DECOMPSTAT; /**< state for Weight Decompressor, offset: 0x304 */ __IO uint32_t GROUP_BASE; /**< DDR offset from base for Weight Decompressor, offset: 0x308 */ uint8_t RESERVED_9[4]; __IO uint32_t GROUP_LEN; /**< Length in bytes of current Decompressor Group in External memory, offset: 0x310 */ uint8_t RESERVED_10[44]; __IO uint32_t CRYPTO; /**< Control for Cryptographic protection of models by SoC security, offset: 0x340 */ __IO uint32_t PRIVDDRL; /**< Physical address in DDR of model when secure, offset: 0x344 */ __IO uint32_t PRIVDDRH; /**< Physical address in DDR of model when secure, offset: 0x348 */ __IO uint32_t SESSIONIV; /**< Unique IV for Protected models, offset: 0x34C */ __IO uint32_t INFCOUNT; /**< Infocount, offset: 0x350 */ __IO uint32_t FLAYERNUM; /**< Layer number for Fetch, offset: 0x354 */ __IO uint32_t PLAYERNUM; /**< Layer number for Push, offset: 0x358 */ uint8_t RESERVED_11[4]; __IO uint32_t AXIOPT; /**< Boot SoC setting for AXI optimization, offset: 0x360 */ uint8_t RESERVED_12[156]; __IO uint32_t V2P_DATA[16]; /**< Virtual to Physical registers, array offset: 0x400, array step: 0x4 */ __IO uint32_t V2P_WEIGHTS[16]; /**< Virtual to Physical registers, array offset: 0x440, array step: 0x4 */ __IO uint32_t V2P_RESULTS[16]; /**< Virtual to Physical registers, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_13[48]; __IO uint32_t LISTEN; /**< Listener Mode Enable, offset: 0x4F0 */ } neutrons_Type; /* ---------------------------------------------------------------------------- -- neutrons Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup neutrons_Register_Masks neutrons Register Masks * @{ */ /*! @name RESETCTRL - Reset and Control */ /*! @{ */ #define neutrons_RESETCTRL_ZVRUN_MASK (0x1U) #define neutrons_RESETCTRL_ZVRUN_SHIFT (0U) /*! ZVRUN - ZVRUN * 0b0..If Zen-V is held in reset * 0b1..If running */ #define neutrons_RESETCTRL_ZVRUN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_ZVRUN_SHIFT)) & neutrons_RESETCTRL_ZVRUN_MASK) #define neutrons_RESETCTRL_OCMCNT_MASK (0xEU) #define neutrons_RESETCTRL_OCMCNT_SHIFT (1U) /*! OCMCNT - OCMCNT */ #define neutrons_RESETCTRL_OCMCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_OCMCNT_SHIFT)) & neutrons_RESETCTRL_OCMCNT_MASK) #define neutrons_RESETCTRL_NRUN_MASK (0xF0U) #define neutrons_RESETCTRL_NRUN_SHIFT (4U) /*! NRUN - NRUN */ #define neutrons_RESETCTRL_NRUN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_NRUN_SHIFT)) & neutrons_RESETCTRL_NRUN_MASK) #define neutrons_RESETCTRL_MEMENA_MASK (0xF00U) #define neutrons_RESETCTRL_MEMENA_SHIFT (8U) /*! MEMENA - MEMENA */ #define neutrons_RESETCTRL_MEMENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_MEMENA_SHIFT)) & neutrons_RESETCTRL_MEMENA_MASK) #define neutrons_RESETCTRL_ZMEMFREE_MASK (0x1000U) #define neutrons_RESETCTRL_ZMEMFREE_SHIFT (12U) /*! ZMEMFREE - ZMEMFREE * 0b0..If 0, the ITCM and DTCM will be unavailable when Zen-V is (when Zen-V in reset or halted). * 0b1..If 1, the ITCM and DTCM will be available regardless of Zen-V core state. This should be used when the * memories are to be updated while Zen-V is off. */ #define neutrons_RESETCTRL_ZMEMFREE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_ZMEMFREE_SHIFT)) & neutrons_RESETCTRL_ZMEMFREE_MASK) #define neutrons_RESETCTRL_DMRESET_MASK (0x8000U) #define neutrons_RESETCTRL_DMRESET_SHIFT (15U) /*! DMRESET - DataMover Reset Control * 0b0..DataMover out-of-reset * 0b1..DataMover kept in reset */ #define neutrons_RESETCTRL_DMRESET(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_DMRESET_SHIFT)) & neutrons_RESETCTRL_DMRESET_MASK) #define neutrons_RESETCTRL_NGANGDIS_MASK (0xF0000U) #define neutrons_RESETCTRL_NGANGDIS_SHIFT (16U) /*! NGANGDIS - NGANGDIS */ #define neutrons_RESETCTRL_NGANGDIS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_NGANGDIS_SHIFT)) & neutrons_RESETCTRL_NGANGDIS_MASK) #define neutrons_RESETCTRL_OCMEN_MASK (0x40000000U) #define neutrons_RESETCTRL_OCMEN_SHIFT (30U) /*! OCMEN - OCM enable * 0b0..If 0,then OCM_CNT bit field determines the no. of OCMs. Also, for crypto models hardware forces this field to 0. * 0b1..If 1, then all neutron's TCM are available as OCM w/o scrubbing TCM contents. The field must only be set * to 1 when Neutrons are idle otherwise operation is not gauranteed. */ #define neutrons_RESETCTRL_OCMEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_OCMEN_SHIFT)) & neutrons_RESETCTRL_OCMEN_MASK) #define neutrons_RESETCTRL_ZVCLKEN_MASK (0x80000000U) #define neutrons_RESETCTRL_ZVCLKEN_SHIFT (31U) /*! ZVCLKEN - Zen-V's clock enable * 0b0..If 0, then ZVRUN bit field determines the gating state of Zen-V's clock. * 0b1..If 1, the Zen-V clock is ungated. */ #define neutrons_RESETCTRL_ZVCLKEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RESETCTRL_ZVCLKEN_SHIFT)) & neutrons_RESETCTRL_ZVCLKEN_MASK) /*! @} */ /*! @name STATUSERR - Zen-V Status and Error */ /*! @{ */ #define neutrons_STATUSERR_ZVHALT_MASK (0x1U) #define neutrons_STATUSERR_ZVHALT_SHIFT (0U) /*! ZVHALT - Zen-V core HALT */ #define neutrons_STATUSERR_ZVHALT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_ZVHALT_SHIFT)) & neutrons_STATUSERR_ZVHALT_MASK) #define neutrons_STATUSERR_ZVFAULT_MASK (0x2U) #define neutrons_STATUSERR_ZVFAULT_SHIFT (1U) /*! ZVFAULT - Zen-V core fault */ #define neutrons_STATUSERR_ZVFAULT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_ZVFAULT_SHIFT)) & neutrons_STATUSERR_ZVFAULT_MASK) #define neutrons_STATUSERR_NRAERR_MASK (0x10U) #define neutrons_STATUSERR_NRAERR_SHIFT (4U) /*! NRAERR - NRAERR */ #define neutrons_STATUSERR_NRAERR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_NRAERR_SHIFT)) & neutrons_STATUSERR_NRAERR_MASK) #define neutrons_STATUSERR_NWAERR_MASK (0x20U) #define neutrons_STATUSERR_NWAERR_SHIFT (5U) /*! NWAERR - NWAERR */ #define neutrons_STATUSERR_NWAERR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_NWAERR_SHIFT)) & neutrons_STATUSERR_NWAERR_MASK) #define neutrons_STATUSERR_NDAERR_MASK (0x40U) #define neutrons_STATUSERR_NDAERR_SHIFT (6U) /*! NDAERR - NDAERR */ #define neutrons_STATUSERR_NDAERR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_NDAERR_SHIFT)) & neutrons_STATUSERR_NDAERR_MASK) #define neutrons_STATUSERR_REQCONT_MASK (0x100U) #define neutrons_STATUSERR_REQCONT_SHIFT (8U) /*! REQCONT - REQCONT */ #define neutrons_STATUSERR_REQCONT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_REQCONT_SHIFT)) & neutrons_STATUSERR_REQCONT_MASK) #define neutrons_STATUSERR_REQCONTID_MASK (0x1FE00U) #define neutrons_STATUSERR_REQCONTID_SHIFT (9U) /*! REQCONTID - REQCONTID */ #define neutrons_STATUSERR_REQCONTID(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_REQCONTID_SHIFT)) & neutrons_STATUSERR_REQCONTID_MASK) #define neutrons_STATUSERR_OCMECCCORR_MASK (0xFF00000U) #define neutrons_STATUSERR_OCMECCCORR_SHIFT (20U) /*! OCMECCCORR - OCMECCCORR */ #define neutrons_STATUSERR_OCMECCCORR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_OCMECCCORR_SHIFT)) & neutrons_STATUSERR_OCMECCCORR_MASK) #define neutrons_STATUSERR_OCMECCFATAL_MASK (0x10000000U) #define neutrons_STATUSERR_OCMECCFATAL_SHIFT (28U) /*! OCMECCFATAL - OCMECCFATAL */ #define neutrons_STATUSERR_OCMECCFATAL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_OCMECCFATAL_SHIFT)) & neutrons_STATUSERR_OCMECCFATAL_MASK) #define neutrons_STATUSERR_INFDONE_CLR_MASK (0x40000000U) #define neutrons_STATUSERR_INFDONE_CLR_SHIFT (30U) /*! INFDONE_CLR - Interrupt on clear Inference Done */ #define neutrons_STATUSERR_INFDONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_INFDONE_CLR_SHIFT)) & neutrons_STATUSERR_INFDONE_CLR_MASK) #define neutrons_STATUSERR_MBOXINT_MASK (0x80000000U) #define neutrons_STATUSERR_MBOXINT_SHIFT (31U) /*! MBOXINT - Message Box Interrupt */ #define neutrons_STATUSERR_MBOXINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUSERR_MBOXINT_SHIFT)) & neutrons_STATUSERR_MBOXINT_MASK) /*! @} */ /*! @name INTENA - Interrupt Enable For SoC */ /*! @{ */ #define neutrons_INTENA_ZVHALT_MASK (0x1U) #define neutrons_INTENA_ZVHALT_SHIFT (0U) /*! ZVHALT - Zen-V Halt */ #define neutrons_INTENA_ZVHALT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_ZVHALT_SHIFT)) & neutrons_INTENA_ZVHALT_MASK) #define neutrons_INTENA_INFDONE_MASK (0x2U) #define neutrons_INTENA_INFDONE_SHIFT (1U) /*! INFDONE - Inference Done */ #define neutrons_INTENA_INFDONE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_INFDONE_SHIFT)) & neutrons_INTENA_INFDONE_MASK) #define neutrons_INTENA_MBOX_MASK (0x4U) #define neutrons_INTENA_MBOX_SHIFT (2U) /*! MBOX - Mailbox */ #define neutrons_INTENA_MBOX(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_MBOX_SHIFT)) & neutrons_INTENA_MBOX_MASK) #define neutrons_INTENA_SHUTDOWN_MASK (0x80U) #define neutrons_INTENA_SHUTDOWN_SHIFT (7U) /*! SHUTDOWN - Shutdown */ #define neutrons_INTENA_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_SHUTDOWN_SHIFT)) & neutrons_INTENA_SHUTDOWN_MASK) #define neutrons_INTENA_AERR_MASK (0x10000U) #define neutrons_INTENA_AERR_SHIFT (16U) /*! AERR - AERR */ #define neutrons_INTENA_AERR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_AERR_SHIFT)) & neutrons_INTENA_AERR_MASK) #define neutrons_INTENA_REQCONT_MASK (0x20000U) #define neutrons_INTENA_REQCONT_SHIFT (17U) /*! REQCONT - REQCONT */ #define neutrons_INTENA_REQCONT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_REQCONT_SHIFT)) & neutrons_INTENA_REQCONT_MASK) #define neutrons_INTENA_OCMECCSAT_MASK (0x40000U) #define neutrons_INTENA_OCMECCSAT_SHIFT (18U) /*! OCMECCSAT - OCMECCSAT */ #define neutrons_INTENA_OCMECCSAT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_OCMECCSAT_SHIFT)) & neutrons_INTENA_OCMECCSAT_MASK) #define neutrons_INTENA_OCMECCFATAL_MASK (0x80000U) #define neutrons_INTENA_OCMECCFATAL_SHIFT (19U) /*! OCMECCFATAL - OCMECCFATAL */ #define neutrons_INTENA_OCMECCFATAL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_OCMECCFATAL_SHIFT)) & neutrons_INTENA_OCMECCFATAL_MASK) #define neutrons_INTENA_ZVFAULT_MASK (0x100000U) #define neutrons_INTENA_ZVFAULT_SHIFT (20U) /*! ZVFAULT - ZVFAULT */ #define neutrons_INTENA_ZVFAULT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTENA_ZVFAULT_SHIFT)) & neutrons_INTENA_ZVFAULT_MASK) /*! @} */ /*! @name INTCLR - Interrupt Clear For SoC */ /*! @{ */ #define neutrons_INTCLR_ZVHALT_MASK (0x1U) #define neutrons_INTCLR_ZVHALT_SHIFT (0U) /*! ZVHALT - ZVHALT */ #define neutrons_INTCLR_ZVHALT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_ZVHALT_SHIFT)) & neutrons_INTCLR_ZVHALT_MASK) #define neutrons_INTCLR_INFDONE_MASK (0x2U) #define neutrons_INTCLR_INFDONE_SHIFT (1U) /*! INFDONE - Inference Done */ #define neutrons_INTCLR_INFDONE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_INFDONE_SHIFT)) & neutrons_INTCLR_INFDONE_MASK) #define neutrons_INTCLR_MBOX_MASK (0x4U) #define neutrons_INTCLR_MBOX_SHIFT (2U) /*! MBOX - Mailbox */ #define neutrons_INTCLR_MBOX(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_MBOX_SHIFT)) & neutrons_INTCLR_MBOX_MASK) #define neutrons_INTCLR_SHUTDOWN_MASK (0x80U) #define neutrons_INTCLR_SHUTDOWN_SHIFT (7U) /*! SHUTDOWN - SHUTDOWN */ #define neutrons_INTCLR_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_SHUTDOWN_SHIFT)) & neutrons_INTCLR_SHUTDOWN_MASK) #define neutrons_INTCLR_AERR_MASK (0x10000U) #define neutrons_INTCLR_AERR_SHIFT (16U) /*! AERR - AERR */ #define neutrons_INTCLR_AERR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_AERR_SHIFT)) & neutrons_INTCLR_AERR_MASK) #define neutrons_INTCLR_REQCONT_MASK (0x20000U) #define neutrons_INTCLR_REQCONT_SHIFT (17U) /*! REQCONT - REQCONT */ #define neutrons_INTCLR_REQCONT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_REQCONT_SHIFT)) & neutrons_INTCLR_REQCONT_MASK) #define neutrons_INTCLR_OCMECCSAT_MASK (0x40000U) #define neutrons_INTCLR_OCMECCSAT_SHIFT (18U) /*! OCMECCSAT - OCMECCSAT */ #define neutrons_INTCLR_OCMECCSAT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_OCMECCSAT_SHIFT)) & neutrons_INTCLR_OCMECCSAT_MASK) #define neutrons_INTCLR_OCMECCFATAL_MASK (0x80000U) #define neutrons_INTCLR_OCMECCFATAL_SHIFT (19U) /*! OCMECCFATAL - OCMECCFATAL */ #define neutrons_INTCLR_OCMECCFATAL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_OCMECCFATAL_SHIFT)) & neutrons_INTCLR_OCMECCFATAL_MASK) #define neutrons_INTCLR_ZVFAULT_MASK (0x100000U) #define neutrons_INTCLR_ZVFAULT_SHIFT (20U) /*! ZVFAULT - ZVFAULT */ #define neutrons_INTCLR_ZVFAULT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INTCLR_ZVFAULT_SHIFT)) & neutrons_INTCLR_ZVFAULT_MASK) /*! @} */ /*! @name CYCLOW - Cycle Counter */ /*! @{ */ #define neutrons_CYCLOW_CNT_LOW_MASK (0xFFFFFFFFU) #define neutrons_CYCLOW_CNT_LOW_SHIFT (0U) /*! CNT_LOW - CNT_LOW */ #define neutrons_CYCLOW_CNT_LOW(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CYCLOW_CNT_LOW_SHIFT)) & neutrons_CYCLOW_CNT_LOW_MASK) /*! @} */ /*! @name CYCHIGH - Cycle Counter */ /*! @{ */ #define neutrons_CYCHIGH_CNT_HIGH_MASK (0xFFFFFFFFU) #define neutrons_CYCHIGH_CNT_HIGH_SHIFT (0U) /*! CNT_HIGH - CNT_HIGH */ #define neutrons_CYCHIGH_CNT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CYCHIGH_CNT_HIGH_SHIFT)) & neutrons_CYCHIGH_CNT_HIGH_MASK) /*! @} */ /*! @name DDRLATENT - DDR Latency Performance Counter */ /*! @{ */ #define neutrons_DDRLATENT_CNT_MASK (0xFFFFFFFFU) #define neutrons_DDRLATENT_CNT_SHIFT (0U) /*! CNT - CNT */ #define neutrons_DDRLATENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDRLATENT_CNT_SHIFT)) & neutrons_DDRLATENT_CNT_MASK) /*! @} */ /*! @name DDRSPREAD - DDR Data Read Spread Performance Counter */ /*! @{ */ #define neutrons_DDRSPREAD_CNT_MASK (0xFFFFFFFFU) #define neutrons_DDRSPREAD_CNT_SHIFT (0U) /*! CNT - CNT */ #define neutrons_DDRSPREAD_CNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDRSPREAD_CNT_SHIFT)) & neutrons_DDRSPREAD_CNT_MASK) /*! @} */ /*! @name DDRRCNTS - DDR Read Performance Counter */ /*! @{ */ #define neutrons_DDRRCNTS_CNT_DDRR_MASK (0xFFFFFFFFU) #define neutrons_DDRRCNTS_CNT_DDRR_SHIFT (0U) /*! CNT_DDRR - CNT_DDRR */ #define neutrons_DDRRCNTS_CNT_DDRR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDRRCNTS_CNT_DDRR_SHIFT)) & neutrons_DDRRCNTS_CNT_DDRR_MASK) /*! @} */ /*! @name DDRWWORDS - DDR Write Performance Counter */ /*! @{ */ #define neutrons_DDRWWORDS_CNT_MASK (0xFFFFFFFFU) #define neutrons_DDRWWORDS_CNT_SHIFT (0U) /*! CNT - Count */ #define neutrons_DDRWWORDS_CNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDRWWORDS_CNT_SHIFT)) & neutrons_DDRWWORDS_CNT_MASK) /*! @} */ /*! @name DDRRWORDS - DDR Read Word Performance Counter */ /*! @{ */ #define neutrons_DDRRWORDS_CNT_MASK (0xFFFFFFFFU) #define neutrons_DDRRWORDS_CNT_SHIFT (0U) /*! CNT - CNT */ #define neutrons_DDRRWORDS_CNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDRRWORDS_CNT_SHIFT)) & neutrons_DDRRWORDS_CNT_MASK) /*! @} */ /*! @name DDRSTALL - DDR Stall Performance Counter */ /*! @{ */ #define neutrons_DDRSTALL_REQSTALLS_MASK (0xFFFFU) #define neutrons_DDRSTALL_REQSTALLS_SHIFT (0U) /*! REQSTALLS - REQSTALLS */ #define neutrons_DDRSTALL_REQSTALLS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDRSTALL_REQSTALLS_SHIFT)) & neutrons_DDRSTALL_REQSTALLS_MASK) #define neutrons_DDRSTALL_WSTALLS_MASK (0xFFFF0000U) #define neutrons_DDRSTALL_WSTALLS_SHIFT (16U) /*! WSTALLS - WSTALLS */ #define neutrons_DDRSTALL_WSTALLS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDRSTALL_WSTALLS_SHIFT)) & neutrons_DDRSTALL_WSTALLS_MASK) /*! @} */ /*! @name NSTALL - Neutron Stall Performance Counter */ /*! @{ */ #define neutrons_NSTALL_DSTALLS_MASK (0xFFFFU) #define neutrons_NSTALL_DSTALLS_SHIFT (0U) /*! DSTALLS - DSTALLS */ #define neutrons_NSTALL_DSTALLS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_NSTALL_DSTALLS_SHIFT)) & neutrons_NSTALL_DSTALLS_MASK) #define neutrons_NSTALL_WSTALLS_MASK (0xFFFF0000U) #define neutrons_NSTALL_WSTALLS_SHIFT (16U) /*! WSTALLS - WSTALLS */ #define neutrons_NSTALL_WSTALLS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_NSTALL_WSTALLS_SHIFT)) & neutrons_NSTALL_WSTALLS_MASK) /*! @} */ /*! @name NACT - Neutron active performance counter */ /*! @{ */ #define neutrons_NACT_CNT_MASK (0xFFFFFFFFU) #define neutrons_NACT_CNT_SHIFT (0U) /*! CNT - CNT */ #define neutrons_NACT_CNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_NACT_CNT_SHIFT)) & neutrons_NACT_CNT_MASK) /*! @} */ /*! @name EVTRCCFG - Optional Event Trace configure/control */ /*! @{ */ #define neutrons_EVTRCCFG_ENABLE_MASK (0x1U) #define neutrons_EVTRCCFG_ENABLE_SHIFT (0U) /*! ENABLE - Enable */ #define neutrons_EVTRCCFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCCFG_ENABLE_SHIFT)) & neutrons_EVTRCCFG_ENABLE_MASK) #define neutrons_EVTRCCFG_DIV_MASK (0xCU) #define neutrons_EVTRCCFG_DIV_SHIFT (2U) /*! DIV - Divider * 0b00..Cycle is one count. No divider * 0b01..Divide by 4 * 0b10..Divide by 16 * 0b11..Divide by 64 */ #define neutrons_EVTRCCFG_DIV(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCCFG_DIV_SHIFT)) & neutrons_EVTRCCFG_DIV_MASK) #define neutrons_EVTRCCFG_TSTAMP_MASK (0xFF0U) #define neutrons_EVTRCCFG_TSTAMP_SHIFT (4U) /*! TSTAMP - Time stamp * 0b00000000..No timestamp, so just byte header * 0b00000001..1 byte relative timestamp, saturating at 0xFF * 0b00000010..2 byte relative timestamp, saturating as 0xFFFF * 0b00000011..Full absolute 32b word timestamp */ #define neutrons_EVTRCCFG_TSTAMP(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCCFG_TSTAMP_SHIFT)) & neutrons_EVTRCCFG_TSTAMP_MASK) #define neutrons_EVTRCCFG_RW_MASK (0xF000U) #define neutrons_EVTRCCFG_RW_SHIFT (12U) /*! RW - Read Write */ #define neutrons_EVTRCCFG_RW(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCCFG_RW_SHIFT)) & neutrons_EVTRCCFG_RW_MASK) #define neutrons_EVTRCCFG_START_MASK (0xFF0000U) #define neutrons_EVTRCCFG_START_SHIFT (16U) /*! START - Start trace event * 0b00000001..Neutron * 0b00000010..Data fetch by Data Mover * 0b00000011..Data push by Data Mover * 0b00000100..Weight fetch by Data Mover */ #define neutrons_EVTRCCFG_START(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCCFG_START_SHIFT)) & neutrons_EVTRCCFG_START_MASK) #define neutrons_EVTRCCFG_END_MASK (0xF000000U) #define neutrons_EVTRCCFG_END_SHIFT (24U) /*! END - End trace event */ #define neutrons_EVTRCCFG_END(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCCFG_END_SHIFT)) & neutrons_EVTRCCFG_END_MASK) /*! @} */ /*! @name EVTRCDATA - Optional Event Trace Software submission */ /*! @{ */ #define neutrons_EVTRCDATA_PUSH_MASK (0x1U) #define neutrons_EVTRCDATA_PUSH_SHIFT (0U) /*! PUSH - Push */ #define neutrons_EVTRCDATA_PUSH(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCDATA_PUSH_SHIFT)) & neutrons_EVTRCDATA_PUSH_MASK) #define neutrons_EVTRCDATA_TYPE_MASK (0x70U) #define neutrons_EVTRCDATA_TYPE_SHIFT (4U) /*! TYPE - Type * 0b000..Software Event only with no data or timestamp * 0b001..Software Event with 1 byte relative timestamp * 0b010..Software Event with 2 byte relative timestamp * 0b011..Software Event with absolute timestamp * 0b100..Software Event with 2 bytes of DATA * 0b101..Reserved * 0b110..Reserved * 0b111..Reserved */ #define neutrons_EVTRCDATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCDATA_TYPE_SHIFT)) & neutrons_EVTRCDATA_TYPE_MASK) #define neutrons_EVTRCDATA_DATA_MASK (0xFFFF0000U) #define neutrons_EVTRCDATA_DATA_SHIFT (16U) /*! DATA - Optional data */ #define neutrons_EVTRCDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_EVTRCDATA_DATA_SHIFT)) & neutrons_EVTRCDATA_DATA_MASK) /*! @} */ /*! @name ZVIV2P0 - Zen-V Code Virtual to Physical */ /*! @{ */ #define neutrons_ZVIV2P0_ERROR_MASK (0x1U) #define neutrons_ZVIV2P0_ERROR_SHIFT (0U) /*! ERROR - ERROR */ #define neutrons_ZVIV2P0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P0_ERROR_SHIFT)) & neutrons_ZVIV2P0_ERROR_MASK) #define neutrons_ZVIV2P0_DATA1_MASK (0x2U) #define neutrons_ZVIV2P0_DATA1_SHIFT (1U) /*! DATA1 - DATA1 */ #define neutrons_ZVIV2P0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P0_DATA1_SHIFT)) & neutrons_ZVIV2P0_DATA1_MASK) #define neutrons_ZVIV2P0_DATA2_MASK (0x4U) #define neutrons_ZVIV2P0_DATA2_SHIFT (2U) /*! DATA2 - DATA2 */ #define neutrons_ZVIV2P0_DATA2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P0_DATA2_SHIFT)) & neutrons_ZVIV2P0_DATA2_MASK) #define neutrons_ZVIV2P0_DATA3_MASK (0x8U) #define neutrons_ZVIV2P0_DATA3_SHIFT (3U) /*! DATA3 - DATA3 */ #define neutrons_ZVIV2P0_DATA3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P0_DATA3_SHIFT)) & neutrons_ZVIV2P0_DATA3_MASK) #define neutrons_ZVIV2P0_MATCH1_MASK (0xFF00U) #define neutrons_ZVIV2P0_MATCH1_SHIFT (8U) /*! MATCH1 - MATCH1 */ #define neutrons_ZVIV2P0_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P0_MATCH1_SHIFT)) & neutrons_ZVIV2P0_MATCH1_MASK) #define neutrons_ZVIV2P0_MATCH2_MASK (0xFF0000U) #define neutrons_ZVIV2P0_MATCH2_SHIFT (16U) /*! MATCH2 - MATCH2 */ #define neutrons_ZVIV2P0_MATCH2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P0_MATCH2_SHIFT)) & neutrons_ZVIV2P0_MATCH2_MASK) #define neutrons_ZVIV2P0_MATCH3_MASK (0xFF000000U) #define neutrons_ZVIV2P0_MATCH3_SHIFT (24U) /*! MATCH3 - MATCH2 */ #define neutrons_ZVIV2P0_MATCH3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P0_MATCH3_SHIFT)) & neutrons_ZVIV2P0_MATCH3_MASK) /*! @} */ /*! @name ZVIV2P1 - Zen-V Code Virtual to Physical */ /*! @{ */ #define neutrons_ZVIV2P1_MATCH0_MASK (0xFFU) #define neutrons_ZVIV2P1_MATCH0_SHIFT (0U) /*! MATCH0 - MATCH0 */ #define neutrons_ZVIV2P1_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P1_MATCH0_SHIFT)) & neutrons_ZVIV2P1_MATCH0_MASK) #define neutrons_ZVIV2P1_MATCH1_MASK (0xFF00U) #define neutrons_ZVIV2P1_MATCH1_SHIFT (8U) /*! MATCH1 - MATCH1 */ #define neutrons_ZVIV2P1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P1_MATCH1_SHIFT)) & neutrons_ZVIV2P1_MATCH1_MASK) #define neutrons_ZVIV2P1_MATCH2_MASK (0xFF0000U) #define neutrons_ZVIV2P1_MATCH2_SHIFT (16U) /*! MATCH2 - MATCH2 */ #define neutrons_ZVIV2P1_MATCH2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P1_MATCH2_SHIFT)) & neutrons_ZVIV2P1_MATCH2_MASK) #define neutrons_ZVIV2P1_MATCH3_MASK (0xFF000000U) #define neutrons_ZVIV2P1_MATCH3_SHIFT (24U) /*! MATCH3 - MATCH3 */ #define neutrons_ZVIV2P1_MATCH3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P1_MATCH3_SHIFT)) & neutrons_ZVIV2P1_MATCH3_MASK) /*! @} */ /*! @name ZVIV2P2 - Zen-V Code Virtual to Physical */ /*! @{ */ #define neutrons_ZVIV2P2_MATCH0_MASK (0xFFU) #define neutrons_ZVIV2P2_MATCH0_SHIFT (0U) /*! MATCH0 - MATCH0 */ #define neutrons_ZVIV2P2_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P2_MATCH0_SHIFT)) & neutrons_ZVIV2P2_MATCH0_MASK) #define neutrons_ZVIV2P2_MATCH1_MASK (0xFF00U) #define neutrons_ZVIV2P2_MATCH1_SHIFT (8U) /*! MATCH1 - MATCH1 */ #define neutrons_ZVIV2P2_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P2_MATCH1_SHIFT)) & neutrons_ZVIV2P2_MATCH1_MASK) #define neutrons_ZVIV2P2_MATCH2_MASK (0xFF0000U) #define neutrons_ZVIV2P2_MATCH2_SHIFT (16U) /*! MATCH2 - MATCH2 */ #define neutrons_ZVIV2P2_MATCH2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P2_MATCH2_SHIFT)) & neutrons_ZVIV2P2_MATCH2_MASK) #define neutrons_ZVIV2P2_MATCH3_MASK (0xFF000000U) #define neutrons_ZVIV2P2_MATCH3_SHIFT (24U) /*! MATCH3 - MATCH3 */ #define neutrons_ZVIV2P2_MATCH3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P2_MATCH3_SHIFT)) & neutrons_ZVIV2P2_MATCH3_MASK) /*! @} */ /*! @name ZVIV2P3 - Zen-V Code Virtual to Physical */ /*! @{ */ #define neutrons_ZVIV2P3_MATCH0_MASK (0xFFU) #define neutrons_ZVIV2P3_MATCH0_SHIFT (0U) /*! MATCH0 - MATCH0 */ #define neutrons_ZVIV2P3_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P3_MATCH0_SHIFT)) & neutrons_ZVIV2P3_MATCH0_MASK) #define neutrons_ZVIV2P3_MATCH1_MASK (0xFF00U) #define neutrons_ZVIV2P3_MATCH1_SHIFT (8U) /*! MATCH1 - MATCH1 */ #define neutrons_ZVIV2P3_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P3_MATCH1_SHIFT)) & neutrons_ZVIV2P3_MATCH1_MASK) #define neutrons_ZVIV2P3_MATCH2_MASK (0xFF0000U) #define neutrons_ZVIV2P3_MATCH2_SHIFT (16U) /*! MATCH2 - MATCH2 */ #define neutrons_ZVIV2P3_MATCH2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P3_MATCH2_SHIFT)) & neutrons_ZVIV2P3_MATCH2_MASK) #define neutrons_ZVIV2P3_MATCH3_MASK (0xFF000000U) #define neutrons_ZVIV2P3_MATCH3_SHIFT (24U) /*! MATCH3 - MATCH3 */ #define neutrons_ZVIV2P3_MATCH3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_ZVIV2P3_MATCH3_SHIFT)) & neutrons_ZVIV2P3_MATCH3_MASK) /*! @} */ /*! @name TTCTRL - TCM-to-TCM Control */ /*! @{ */ #define neutrons_TTCTRL_STRIDE_MASK (0xFFU) #define neutrons_TTCTRL_STRIDE_SHIFT (0U) /*! STRIDE - Stride */ #define neutrons_TTCTRL_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTCTRL_STRIDE_SHIFT)) & neutrons_TTCTRL_STRIDE_MASK) #define neutrons_TTCTRL_SIZE_MASK (0x3FFF00U) #define neutrons_TTCTRL_SIZE_SHIFT (8U) /*! SIZE - Size */ #define neutrons_TTCTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTCTRL_SIZE_SHIFT)) & neutrons_TTCTRL_SIZE_MASK) #define neutrons_TTCTRL_ITER_MASK (0xFFC00000U) #define neutrons_TTCTRL_ITER_SHIFT (22U) /*! ITER - Iterations */ #define neutrons_TTCTRL_ITER(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTCTRL_ITER_SHIFT)) & neutrons_TTCTRL_ITER_MASK) /*! @} */ /*! @name TTSADDR - TCM-to-TCM Source Address */ /*! @{ */ #define neutrons_TTSADDR_ADDR_MASK (0xFFFFFFFFU) #define neutrons_TTSADDR_ADDR_SHIFT (0U) /*! ADDR - Address */ #define neutrons_TTSADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTSADDR_ADDR_SHIFT)) & neutrons_TTSADDR_ADDR_MASK) /*! @} */ /*! @name TTDADDR - TCM-to-TCM Destination Address */ /*! @{ */ #define neutrons_TTDADDR_ADDR_MASK (0xFFFFFFFFU) #define neutrons_TTDADDR_ADDR_SHIFT (0U) /*! ADDR - Address */ #define neutrons_TTDADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTDADDR_ADDR_SHIFT)) & neutrons_TTDADDR_ADDR_MASK) /*! @} */ /*! @name TTCTRL2 - TCM-to-TCM Control 2 */ /*! @{ */ #define neutrons_TTCTRL2_DSTLEN_MASK (0x7FFFFU) #define neutrons_TTCTRL2_DSTLEN_SHIFT (0U) /*! DSTLEN - Destination Length */ #define neutrons_TTCTRL2_DSTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTCTRL2_DSTLEN_SHIFT)) & neutrons_TTCTRL2_DSTLEN_MASK) #define neutrons_TTCTRL2_MODE_MASK (0xC00000U) #define neutrons_TTCTRL2_MODE_SHIFT (22U) /*! MODE - Mode * 0b00..Normal slice (src_stride) * 0b01..Destination stride (using {pad,src_stride}) * 0b10..Inject padding (using src_stride) * *.. */ #define neutrons_TTCTRL2_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTCTRL2_MODE_SHIFT)) & neutrons_TTCTRL2_MODE_MASK) #define neutrons_TTCTRL2_PAD_MASK (0xFF000000U) #define neutrons_TTCTRL2_PAD_SHIFT (24U) /*! PAD - Pad */ #define neutrons_TTCTRL2_PAD(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TTCTRL2_PAD_SHIFT)) & neutrons_TTCTRL2_PAD_MASK) /*! @} */ /*! @name CONFIG - Configuration */ /*! @{ */ #define neutrons_CONFIG_TTINTENA_MASK (0x1U) #define neutrons_CONFIG_TTINTENA_SHIFT (0U) /*! TTINTENA - Enable TCM-to-TCM Channel Interrupt * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_TTINTENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_TTINTENA_SHIFT)) & neutrons_CONFIG_TTINTENA_MASK) #define neutrons_CONFIG_FINTENA_MASK (0x2U) #define neutrons_CONFIG_FINTENA_SHIFT (1U) /*! FINTENA - Enable Fetch Channel Interrupt * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_FINTENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_FINTENA_SHIFT)) & neutrons_CONFIG_FINTENA_MASK) #define neutrons_CONFIG_PINTENA_MASK (0x4U) #define neutrons_CONFIG_PINTENA_SHIFT (2U) /*! PINTENA - Enable Push Channel Interrupt * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_PINTENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_PINTENA_SHIFT)) & neutrons_CONFIG_PINTENA_MASK) #define neutrons_CONFIG_WINTENA_MASK (0x8U) #define neutrons_CONFIG_WINTENA_SHIFT (3U) /*! WINTENA - Enable Weight Channel Interrupt * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_WINTENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_WINTENA_SHIFT)) & neutrons_CONFIG_WINTENA_MASK) #define neutrons_CONFIG_ERRENA_MASK (0x10U) #define neutrons_CONFIG_ERRENA_SHIFT (4U) /*! ERRENA - Enable Error Interrupt * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_ERRENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_ERRENA_SHIFT)) & neutrons_CONFIG_ERRENA_MASK) #define neutrons_CONFIG_RELEASE_MASK (0x80U) #define neutrons_CONFIG_RELEASE_SHIFT (7U) /*! RELEASE - Zen-V Release * 0b0..No action * 0b1..Release from reset */ #define neutrons_CONFIG_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_RELEASE_SHIFT)) & neutrons_CONFIG_RELEASE_MASK) #define neutrons_CONFIG_TTINT_MASK (0x100U) #define neutrons_CONFIG_TTINT_SHIFT (8U) /*! TTINT - TCM-to-TCM Channel Interrupt Status * 0b0..No interrupt generated * 0b1..Interrupt generated * 0b0..No effect * 0b1..Clear */ #define neutrons_CONFIG_TTINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_TTINT_SHIFT)) & neutrons_CONFIG_TTINT_MASK) #define neutrons_CONFIG_FINT_MASK (0x200U) #define neutrons_CONFIG_FINT_SHIFT (9U) /*! FINT - Fetch Channel Interrupt Status * 0b0..No interrupt generated * 0b1..Interrupt generated * 0b0..No effect * 0b1..Clear */ #define neutrons_CONFIG_FINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_FINT_SHIFT)) & neutrons_CONFIG_FINT_MASK) #define neutrons_CONFIG_PINT_MASK (0x400U) #define neutrons_CONFIG_PINT_SHIFT (10U) /*! PINT - Push Channel Interrupt Status * 0b0..No interrupt generated * 0b1..Interrupt generated * 0b0..No effect * 0b1..Clear */ #define neutrons_CONFIG_PINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_PINT_SHIFT)) & neutrons_CONFIG_PINT_MASK) #define neutrons_CONFIG_WINT_MASK (0x800U) #define neutrons_CONFIG_WINT_SHIFT (11U) /*! WINT - Data Mover Weight Channel Interrupt * 0b0..No interrupt generated * 0b1..Interrupt generated * 0b0..No effect * 0b1..Clear */ #define neutrons_CONFIG_WINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_WINT_SHIFT)) & neutrons_CONFIG_WINT_MASK) #define neutrons_CONFIG_EINT_MASK (0x1000U) #define neutrons_CONFIG_EINT_SHIFT (12U) /*! EINT - Data Mover Error Interrupt * 0b0..No interrupt generated * 0b1..Interrupt generated * 0b0..No effect * 0b1..Clear */ #define neutrons_CONFIG_EINT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_EINT_SHIFT)) & neutrons_CONFIG_EINT_MASK) #define neutrons_CONFIG_TTWFIENA_MASK (0x10000U) #define neutrons_CONFIG_TTWFIENA_SHIFT (16U) /*! TTWFIENA - TCM-to-TCM Chanel Exit Wait For Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_TTWFIENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_TTWFIENA_SHIFT)) & neutrons_CONFIG_TTWFIENA_MASK) #define neutrons_CONFIG_FWFIENA_MASK (0x20000U) #define neutrons_CONFIG_FWFIENA_SHIFT (17U) /*! FWFIENA - Fetch Channel Wait For Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_FWFIENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_FWFIENA_SHIFT)) & neutrons_CONFIG_FWFIENA_MASK) #define neutrons_CONFIG_PWFIENA_MASK (0x40000U) #define neutrons_CONFIG_PWFIENA_SHIFT (18U) /*! PWFIENA - Push Channel Wait For Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_PWFIENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_PWFIENA_SHIFT)) & neutrons_CONFIG_PWFIENA_MASK) #define neutrons_CONFIG_WWFIENA_MASK (0x80000U) #define neutrons_CONFIG_WWFIENA_SHIFT (19U) /*! WWFIENA - Weight Channel Wait For Interrupt Enable * 0b0..Disable * 0b1..Enable */ #define neutrons_CONFIG_WWFIENA(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CONFIG_WWFIENA_SHIFT)) & neutrons_CONFIG_WWFIENA_MASK) /*! @} */ /*! @name STATUS - Data mover status */ /*! @{ */ #define neutrons_STATUS_TTERRD_MASK (0x1U) #define neutrons_STATUS_TTERRD_SHIFT (0U) /*! TTERRD - TCM-to-TCM Channel Error: Destination * 0b0..No error * 0b1..Error */ #define neutrons_STATUS_TTERRD(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_TTERRD_SHIFT)) & neutrons_STATUS_TTERRD_MASK) #define neutrons_STATUS_TTERRS_MASK (0x2U) #define neutrons_STATUS_TTERRS_SHIFT (1U) /*! TTERRS - TCM-to-TCM Channel Error: Source * 0b0..No error * 0b1..Error */ #define neutrons_STATUS_TTERRS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_TTERRS_SHIFT)) & neutrons_STATUS_TTERRS_MASK) #define neutrons_STATUS_DERRD_MASK (0xF0U) #define neutrons_STATUS_DERRD_SHIFT (4U) /*! DERRD - Data Channel Error: Destination */ #define neutrons_STATUS_DERRD(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_DERRD_SHIFT)) & neutrons_STATUS_DERRD_MASK) #define neutrons_STATUS_DERRS_MASK (0xF00U) #define neutrons_STATUS_DERRS_SHIFT (8U) /*! DERRS - Data Channel Error Source */ #define neutrons_STATUS_DERRS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_DERRS_SHIFT)) & neutrons_STATUS_DERRS_MASK) #define neutrons_STATUS_WERRD_MASK (0x1000U) #define neutrons_STATUS_WERRD_SHIFT (12U) /*! WERRD - Weight Channel Error: Destination * 0b0..No error * 0b1..Error */ #define neutrons_STATUS_WERRD(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_WERRD_SHIFT)) & neutrons_STATUS_WERRD_MASK) #define neutrons_STATUS_WERRS_MASK (0x2000U) #define neutrons_STATUS_WERRS_SHIFT (13U) /*! WERRS - Weight Channel Error: Source * 0b0..No error * 0b1..Error */ #define neutrons_STATUS_WERRS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_WERRS_SHIFT)) & neutrons_STATUS_WERRS_MASK) #define neutrons_STATUS_XERR_MASK (0x8000U) #define neutrons_STATUS_XERR_SHIFT (15U) /*! XERR - DxORDER Register Error * 0b0..No error * 0b1..Error */ #define neutrons_STATUS_XERR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_XERR_SHIFT)) & neutrons_STATUS_XERR_MASK) #define neutrons_STATUS_LRDSTALL_MASK (0x10000U) #define neutrons_STATUS_LRDSTALL_SHIFT (16U) /*! LRDSTALL - Local Read Stall * 0b0..No read stall * 0b1..Read stall */ #define neutrons_STATUS_LRDSTALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_LRDSTALL_SHIFT)) & neutrons_STATUS_LRDSTALL_MASK) #define neutrons_STATUS_LWRSTALL_MASK (0x20000U) #define neutrons_STATUS_LWRSTALL_SHIFT (17U) /*! LWRSTALL - Local Write Stall * 0b0..No write stall * 0b1..Write stall */ #define neutrons_STATUS_LWRSTALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_LWRSTALL_SHIFT)) & neutrons_STATUS_LWRSTALL_MASK) #define neutrons_STATUS_XRDSTALL_MASK (0x40000U) #define neutrons_STATUS_XRDSTALL_SHIFT (18U) /*! XRDSTALL - AXI Read Stall * 0b0..No AXI read stall * 0b1..AXI read stall */ #define neutrons_STATUS_XRDSTALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_XRDSTALL_SHIFT)) & neutrons_STATUS_XRDSTALL_MASK) #define neutrons_STATUS_XWRSTALL_MASK (0x80000U) #define neutrons_STATUS_XWRSTALL_SHIFT (19U) /*! XWRSTALL - AXI Write Stall * 0b0..No AXI write stall * 0b1..AXI write stall */ #define neutrons_STATUS_XWRSTALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_XWRSTALL_SHIFT)) & neutrons_STATUS_XWRSTALL_MASK) #define neutrons_STATUS_DECOMPERR_MASK (0x100000U) #define neutrons_STATUS_DECOMPERR_SHIFT (20U) /*! DECOMPERR - Decompressor Error * 0b0..No error * 0b1..Error */ #define neutrons_STATUS_DECOMPERR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_STATUS_DECOMPERR_SHIFT)) & neutrons_STATUS_DECOMPERR_MASK) /*! @} */ /*! @name DFORDER - Data Fetch Order Manager */ /*! @{ */ #define neutrons_DFORDER_INDEX_MASK (0x3U) #define neutrons_DFORDER_INDEX_SHIFT (0U) /*! INDEX - Index */ #define neutrons_DFORDER_INDEX(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DFORDER_INDEX_SHIFT)) & neutrons_DFORDER_INDEX_MASK) #define neutrons_DFORDER_STALL_MASK (0x4U) #define neutrons_DFORDER_STALL_SHIFT (2U) /*! STALL - Stall * 0b0..No stall * 0b1..Stall */ #define neutrons_DFORDER_STALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DFORDER_STALL_SHIFT)) & neutrons_DFORDER_STALL_MASK) #define neutrons_DFORDER_LIST0_MASK (0x70U) #define neutrons_DFORDER_LIST0_SHIFT (4U) /*! LIST0 - List 0 */ #define neutrons_DFORDER_LIST0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DFORDER_LIST0_SHIFT)) & neutrons_DFORDER_LIST0_MASK) #define neutrons_DFORDER_LIST1_MASK (0x700U) #define neutrons_DFORDER_LIST1_SHIFT (8U) /*! LIST1 - List 1 */ #define neutrons_DFORDER_LIST1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DFORDER_LIST1_SHIFT)) & neutrons_DFORDER_LIST1_MASK) #define neutrons_DFORDER_LIST2_MASK (0x7000U) #define neutrons_DFORDER_LIST2_SHIFT (12U) /*! LIST2 - List 2 */ #define neutrons_DFORDER_LIST2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DFORDER_LIST2_SHIFT)) & neutrons_DFORDER_LIST2_MASK) #define neutrons_DFORDER_LIST3_MASK (0x70000U) #define neutrons_DFORDER_LIST3_SHIFT (16U) /*! LIST3 - List 3 */ #define neutrons_DFORDER_LIST3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DFORDER_LIST3_SHIFT)) & neutrons_DFORDER_LIST3_MASK) #define neutrons_DFORDER_ADD_MASK (0x7000000U) #define neutrons_DFORDER_ADD_SHIFT (24U) /*! ADD - ADD */ #define neutrons_DFORDER_ADD(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DFORDER_ADD_SHIFT)) & neutrons_DFORDER_ADD_MASK) /*! @} */ /*! @name DPORDER - Data Push Order Manager */ /*! @{ */ #define neutrons_DPORDER_INDEX_MASK (0x3U) #define neutrons_DPORDER_INDEX_SHIFT (0U) /*! INDEX - Index */ #define neutrons_DPORDER_INDEX(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DPORDER_INDEX_SHIFT)) & neutrons_DPORDER_INDEX_MASK) #define neutrons_DPORDER_STALL_MASK (0x4U) #define neutrons_DPORDER_STALL_SHIFT (2U) /*! STALL - Stall * 0b0..No stall * 0b1..Stall */ #define neutrons_DPORDER_STALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DPORDER_STALL_SHIFT)) & neutrons_DPORDER_STALL_MASK) #define neutrons_DPORDER_LIST0_MASK (0x70U) #define neutrons_DPORDER_LIST0_SHIFT (4U) /*! LIST0 - List 0 */ #define neutrons_DPORDER_LIST0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DPORDER_LIST0_SHIFT)) & neutrons_DPORDER_LIST0_MASK) #define neutrons_DPORDER_LIST1_MASK (0x700U) #define neutrons_DPORDER_LIST1_SHIFT (8U) /*! LIST1 - List 1 */ #define neutrons_DPORDER_LIST1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DPORDER_LIST1_SHIFT)) & neutrons_DPORDER_LIST1_MASK) #define neutrons_DPORDER_LIST2_MASK (0x7000U) #define neutrons_DPORDER_LIST2_SHIFT (12U) /*! LIST2 - List 2 */ #define neutrons_DPORDER_LIST2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DPORDER_LIST2_SHIFT)) & neutrons_DPORDER_LIST2_MASK) #define neutrons_DPORDER_LIST3_MASK (0x70000U) #define neutrons_DPORDER_LIST3_SHIFT (16U) /*! LIST3 - List 3 */ #define neutrons_DPORDER_LIST3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DPORDER_LIST3_SHIFT)) & neutrons_DPORDER_LIST3_MASK) #define neutrons_DPORDER_ADD_MASK (0x7000000U) #define neutrons_DPORDER_ADD_SHIFT (24U) /*! ADD - ADD */ #define neutrons_DPORDER_ADD(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DPORDER_ADD_SHIFT)) & neutrons_DPORDER_ADD_MASK) /*! @} */ /*! @name DCTRL0_FETCH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL0_FETCH_MODE_MASK (0x3U) #define neutrons_DCTRL0_FETCH_MODE_SHIFT (0U) /*! MODE - Mode */ #define neutrons_DCTRL0_FETCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_FETCH_MODE_SHIFT)) & neutrons_DCTRL0_FETCH_MODE_MASK) #define neutrons_DCTRL0_FETCH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL0_FETCH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL0_FETCH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_FETCH_SRCEQDST_SHIFT)) & neutrons_DCTRL0_FETCH_SRCEQDST_MASK) #define neutrons_DCTRL0_FETCH_PADINSERT_MASK (0x8U) #define neutrons_DCTRL0_FETCH_PADINSERT_SHIFT (3U) /*! PADINSERT - Pad Insert */ #define neutrons_DCTRL0_FETCH_PADINSERT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_FETCH_PADINSERT_SHIFT)) & neutrons_DCTRL0_FETCH_PADINSERT_MASK) #define neutrons_DCTRL0_FETCH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL0_FETCH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL0_FETCH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_FETCH_DESTLEN_SHIFT)) & neutrons_DCTRL0_FETCH_DESTLEN_MASK) #define neutrons_DCTRL0_FETCH_PADCNT_MASK (0xF00000U) #define neutrons_DCTRL0_FETCH_PADCNT_SHIFT (20U) /*! PADCNT - Pad Count */ #define neutrons_DCTRL0_FETCH_PADCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_FETCH_PADCNT_SHIFT)) & neutrons_DCTRL0_FETCH_PADCNT_MASK) #define neutrons_DCTRL0_FETCH_PADBYTE_MASK (0xFF000000U) #define neutrons_DCTRL0_FETCH_PADBYTE_SHIFT (24U) /*! PADBYTE - Pad Byte */ #define neutrons_DCTRL0_FETCH_PADBYTE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_FETCH_PADBYTE_SHIFT)) & neutrons_DCTRL0_FETCH_PADBYTE_MASK) /*! @} */ /*! @name DCTRL0_PUSH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL0_PUSH_MODE_MASK (0x3U) #define neutrons_DCTRL0_PUSH_MODE_SHIFT (0U) /*! MODE - Mode * 0b00..Disabled * 0b01..Activate * 0b10..Push packed * 0b11..Reserved */ #define neutrons_DCTRL0_PUSH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_PUSH_MODE_SHIFT)) & neutrons_DCTRL0_PUSH_MODE_MASK) #define neutrons_DCTRL0_PUSH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL0_PUSH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL0_PUSH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_PUSH_SRCEQDST_SHIFT)) & neutrons_DCTRL0_PUSH_SRCEQDST_MASK) #define neutrons_DCTRL0_PUSH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL0_PUSH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL0_PUSH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL0_PUSH_DESTLEN_SHIFT)) & neutrons_DCTRL0_PUSH_DESTLEN_MASK) /*! @} */ /*! @name DCTRL1_FETCH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL1_FETCH_MODE_MASK (0x3U) #define neutrons_DCTRL1_FETCH_MODE_SHIFT (0U) /*! MODE - Mode */ #define neutrons_DCTRL1_FETCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_FETCH_MODE_SHIFT)) & neutrons_DCTRL1_FETCH_MODE_MASK) #define neutrons_DCTRL1_FETCH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL1_FETCH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL1_FETCH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_FETCH_SRCEQDST_SHIFT)) & neutrons_DCTRL1_FETCH_SRCEQDST_MASK) #define neutrons_DCTRL1_FETCH_PADINSERT_MASK (0x8U) #define neutrons_DCTRL1_FETCH_PADINSERT_SHIFT (3U) /*! PADINSERT - Pad Insert */ #define neutrons_DCTRL1_FETCH_PADINSERT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_FETCH_PADINSERT_SHIFT)) & neutrons_DCTRL1_FETCH_PADINSERT_MASK) #define neutrons_DCTRL1_FETCH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL1_FETCH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL1_FETCH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_FETCH_DESTLEN_SHIFT)) & neutrons_DCTRL1_FETCH_DESTLEN_MASK) #define neutrons_DCTRL1_FETCH_PADCNT_MASK (0xF00000U) #define neutrons_DCTRL1_FETCH_PADCNT_SHIFT (20U) /*! PADCNT - Pad Count */ #define neutrons_DCTRL1_FETCH_PADCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_FETCH_PADCNT_SHIFT)) & neutrons_DCTRL1_FETCH_PADCNT_MASK) #define neutrons_DCTRL1_FETCH_PADBYTE_MASK (0xFF000000U) #define neutrons_DCTRL1_FETCH_PADBYTE_SHIFT (24U) /*! PADBYTE - Pad Byte */ #define neutrons_DCTRL1_FETCH_PADBYTE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_FETCH_PADBYTE_SHIFT)) & neutrons_DCTRL1_FETCH_PADBYTE_MASK) /*! @} */ /*! @name DCTRL1_PUSH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL1_PUSH_MODE_MASK (0x3U) #define neutrons_DCTRL1_PUSH_MODE_SHIFT (0U) /*! MODE - Mode * 0b00..Disabled * 0b01..Activate * *.. */ #define neutrons_DCTRL1_PUSH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_PUSH_MODE_SHIFT)) & neutrons_DCTRL1_PUSH_MODE_MASK) #define neutrons_DCTRL1_PUSH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL1_PUSH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL1_PUSH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_PUSH_SRCEQDST_SHIFT)) & neutrons_DCTRL1_PUSH_SRCEQDST_MASK) #define neutrons_DCTRL1_PUSH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL1_PUSH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL1_PUSH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL1_PUSH_DESTLEN_SHIFT)) & neutrons_DCTRL1_PUSH_DESTLEN_MASK) /*! @} */ /*! @name DCTRL2_FETCH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL2_FETCH_MODE_MASK (0x3U) #define neutrons_DCTRL2_FETCH_MODE_SHIFT (0U) /*! MODE - Mode */ #define neutrons_DCTRL2_FETCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_FETCH_MODE_SHIFT)) & neutrons_DCTRL2_FETCH_MODE_MASK) #define neutrons_DCTRL2_FETCH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL2_FETCH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL2_FETCH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_FETCH_SRCEQDST_SHIFT)) & neutrons_DCTRL2_FETCH_SRCEQDST_MASK) #define neutrons_DCTRL2_FETCH_PADINSERT_MASK (0x8U) #define neutrons_DCTRL2_FETCH_PADINSERT_SHIFT (3U) /*! PADINSERT - Pad Insert */ #define neutrons_DCTRL2_FETCH_PADINSERT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_FETCH_PADINSERT_SHIFT)) & neutrons_DCTRL2_FETCH_PADINSERT_MASK) #define neutrons_DCTRL2_FETCH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL2_FETCH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL2_FETCH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_FETCH_DESTLEN_SHIFT)) & neutrons_DCTRL2_FETCH_DESTLEN_MASK) #define neutrons_DCTRL2_FETCH_PADCNT_MASK (0xF00000U) #define neutrons_DCTRL2_FETCH_PADCNT_SHIFT (20U) /*! PADCNT - Pad Count */ #define neutrons_DCTRL2_FETCH_PADCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_FETCH_PADCNT_SHIFT)) & neutrons_DCTRL2_FETCH_PADCNT_MASK) #define neutrons_DCTRL2_FETCH_PADBYTE_MASK (0xFF000000U) #define neutrons_DCTRL2_FETCH_PADBYTE_SHIFT (24U) /*! PADBYTE - Pad Byte */ #define neutrons_DCTRL2_FETCH_PADBYTE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_FETCH_PADBYTE_SHIFT)) & neutrons_DCTRL2_FETCH_PADBYTE_MASK) /*! @} */ /*! @name DCTRL2_PUSH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL2_PUSH_MODE_MASK (0x3U) #define neutrons_DCTRL2_PUSH_MODE_SHIFT (0U) /*! MODE - Mode * 0b00..Disabled * 0b01..Activate * *.. */ #define neutrons_DCTRL2_PUSH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_PUSH_MODE_SHIFT)) & neutrons_DCTRL2_PUSH_MODE_MASK) #define neutrons_DCTRL2_PUSH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL2_PUSH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL2_PUSH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_PUSH_SRCEQDST_SHIFT)) & neutrons_DCTRL2_PUSH_SRCEQDST_MASK) #define neutrons_DCTRL2_PUSH_PADINSERT_MASK (0x8U) #define neutrons_DCTRL2_PUSH_PADINSERT_SHIFT (3U) /*! PADINSERT - Pad Insert */ #define neutrons_DCTRL2_PUSH_PADINSERT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_PUSH_PADINSERT_SHIFT)) & neutrons_DCTRL2_PUSH_PADINSERT_MASK) #define neutrons_DCTRL2_PUSH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL2_PUSH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL2_PUSH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_PUSH_DESTLEN_SHIFT)) & neutrons_DCTRL2_PUSH_DESTLEN_MASK) #define neutrons_DCTRL2_PUSH_PADCNT_MASK (0xF00000U) #define neutrons_DCTRL2_PUSH_PADCNT_SHIFT (20U) /*! PADCNT - Pad Count */ #define neutrons_DCTRL2_PUSH_PADCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_PUSH_PADCNT_SHIFT)) & neutrons_DCTRL2_PUSH_PADCNT_MASK) #define neutrons_DCTRL2_PUSH_PADBYTE_MASK (0xFF000000U) #define neutrons_DCTRL2_PUSH_PADBYTE_SHIFT (24U) /*! PADBYTE - Pad Byte */ #define neutrons_DCTRL2_PUSH_PADBYTE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_PUSH_PADBYTE_SHIFT)) & neutrons_DCTRL2_PUSH_PADBYTE_MASK) /*! @} */ /*! @name DCTRL3_FETCH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL3_FETCH_MODE_MASK (0x3U) #define neutrons_DCTRL3_FETCH_MODE_SHIFT (0U) /*! MODE - Mode */ #define neutrons_DCTRL3_FETCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_FETCH_MODE_SHIFT)) & neutrons_DCTRL3_FETCH_MODE_MASK) #define neutrons_DCTRL3_FETCH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL3_FETCH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL3_FETCH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_FETCH_SRCEQDST_SHIFT)) & neutrons_DCTRL3_FETCH_SRCEQDST_MASK) #define neutrons_DCTRL3_FETCH_PADINSERT_MASK (0x8U) #define neutrons_DCTRL3_FETCH_PADINSERT_SHIFT (3U) /*! PADINSERT - Pad Insert */ #define neutrons_DCTRL3_FETCH_PADINSERT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_FETCH_PADINSERT_SHIFT)) & neutrons_DCTRL3_FETCH_PADINSERT_MASK) #define neutrons_DCTRL3_FETCH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL3_FETCH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL3_FETCH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_FETCH_DESTLEN_SHIFT)) & neutrons_DCTRL3_FETCH_DESTLEN_MASK) #define neutrons_DCTRL3_FETCH_PADCNT_MASK (0xF00000U) #define neutrons_DCTRL3_FETCH_PADCNT_SHIFT (20U) /*! PADCNT - Pad Count */ #define neutrons_DCTRL3_FETCH_PADCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_FETCH_PADCNT_SHIFT)) & neutrons_DCTRL3_FETCH_PADCNT_MASK) #define neutrons_DCTRL3_FETCH_PADBYTE_MASK (0xFF000000U) #define neutrons_DCTRL3_FETCH_PADBYTE_SHIFT (24U) /*! PADBYTE - Pad Byte */ #define neutrons_DCTRL3_FETCH_PADBYTE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_FETCH_PADBYTE_SHIFT)) & neutrons_DCTRL3_FETCH_PADBYTE_MASK) /*! @} */ /*! @name DCTRL3_PUSH - Push and Fetch Control */ /*! @{ */ #define neutrons_DCTRL3_PUSH_MODE_MASK (0x3U) #define neutrons_DCTRL3_PUSH_MODE_SHIFT (0U) /*! MODE - Mode * 0b00..Disabled * 0b01..Activate * 0b10..Reserved. * 0b11..Reserved */ #define neutrons_DCTRL3_PUSH_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_PUSH_MODE_SHIFT)) & neutrons_DCTRL3_PUSH_MODE_MASK) #define neutrons_DCTRL3_PUSH_SRCEQDST_MASK (0x4U) #define neutrons_DCTRL3_PUSH_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_DCTRL3_PUSH_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_PUSH_SRCEQDST_SHIFT)) & neutrons_DCTRL3_PUSH_SRCEQDST_MASK) #define neutrons_DCTRL3_PUSH_PADINSERT_MASK (0x8U) #define neutrons_DCTRL3_PUSH_PADINSERT_SHIFT (3U) /*! PADINSERT - Pad Insert */ #define neutrons_DCTRL3_PUSH_PADINSERT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_PUSH_PADINSERT_SHIFT)) & neutrons_DCTRL3_PUSH_PADINSERT_MASK) #define neutrons_DCTRL3_PUSH_DESTLEN_MASK (0xFFFF0U) #define neutrons_DCTRL3_PUSH_DESTLEN_SHIFT (4U) /*! DESTLEN - Destination Length */ #define neutrons_DCTRL3_PUSH_DESTLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_PUSH_DESTLEN_SHIFT)) & neutrons_DCTRL3_PUSH_DESTLEN_MASK) #define neutrons_DCTRL3_PUSH_PADCNT_MASK (0xF00000U) #define neutrons_DCTRL3_PUSH_PADCNT_SHIFT (20U) /*! PADCNT - Pad Count */ #define neutrons_DCTRL3_PUSH_PADCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_PUSH_PADCNT_SHIFT)) & neutrons_DCTRL3_PUSH_PADCNT_MASK) #define neutrons_DCTRL3_PUSH_PADBYTE_MASK (0xFF000000U) #define neutrons_DCTRL3_PUSH_PADBYTE_SHIFT (24U) /*! PADBYTE - Pad Byte */ #define neutrons_DCTRL3_PUSH_PADBYTE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_PUSH_PADBYTE_SHIFT)) & neutrons_DCTRL3_PUSH_PADBYTE_MASK) /*! @} */ /*! @name DSADDR0 - Push and Fetch Source Address */ /*! @{ */ #define neutrons_DSADDR0_DSADDR0_MASK (0xFFFFFFFFU) #define neutrons_DSADDR0_DSADDR0_SHIFT (0U) /*! DSADDR0 - DSADDR0 */ #define neutrons_DSADDR0_DSADDR0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DSADDR0_DSADDR0_SHIFT)) & neutrons_DSADDR0_DSADDR0_MASK) /*! @} */ /*! @name DSADDR1 - Push and Fetch Source Address */ /*! @{ */ #define neutrons_DSADDR1_DSADDR1_MASK (0xFFFFFFFFU) #define neutrons_DSADDR1_DSADDR1_SHIFT (0U) /*! DSADDR1 - DSADDR1 */ #define neutrons_DSADDR1_DSADDR1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DSADDR1_DSADDR1_SHIFT)) & neutrons_DSADDR1_DSADDR1_MASK) /*! @} */ /*! @name DSADDR2 - Push and Fetch Source Address */ /*! @{ */ #define neutrons_DSADDR2_DSADDR2_MASK (0xFFFFFFFFU) #define neutrons_DSADDR2_DSADDR2_SHIFT (0U) /*! DSADDR2 - DSADDR2 */ #define neutrons_DSADDR2_DSADDR2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DSADDR2_DSADDR2_SHIFT)) & neutrons_DSADDR2_DSADDR2_MASK) /*! @} */ /*! @name DSADDR3 - Push and Fetch Source Address */ /*! @{ */ #define neutrons_DSADDR3_DSADDR3_MASK (0xFFFFFFFFU) #define neutrons_DSADDR3_DSADDR3_SHIFT (0U) /*! DSADDR3 - DSADDR3 */ #define neutrons_DSADDR3_DSADDR3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DSADDR3_DSADDR3_SHIFT)) & neutrons_DSADDR3_DSADDR3_MASK) /*! @} */ /*! @name DDADDR0 - Push and Fetch Destination Address */ /*! @{ */ #define neutrons_DDADDR0_DDADDR0_MASK (0xFFFFFFFFU) #define neutrons_DDADDR0_DDADDR0_SHIFT (0U) /*! DDADDR0 - DDADDR0 */ #define neutrons_DDADDR0_DDADDR0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDADDR0_DDADDR0_SHIFT)) & neutrons_DDADDR0_DDADDR0_MASK) /*! @} */ /*! @name DDADDR1 - Push and Fetch Destination Address */ /*! @{ */ #define neutrons_DDADDR1_DDADDR1_MASK (0xFFFFFFFFU) #define neutrons_DDADDR1_DDADDR1_SHIFT (0U) /*! DDADDR1 - DDADDR1 */ #define neutrons_DDADDR1_DDADDR1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDADDR1_DDADDR1_SHIFT)) & neutrons_DDADDR1_DDADDR1_MASK) /*! @} */ /*! @name DDADDR2 - Push and Fetch Destination Address */ /*! @{ */ #define neutrons_DDADDR2_DDADDR2_MASK (0xFFFFFFFFU) #define neutrons_DDADDR2_DDADDR2_SHIFT (0U) /*! DDADDR2 - DDADDR2 */ #define neutrons_DDADDR2_DDADDR2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDADDR2_DDADDR2_SHIFT)) & neutrons_DDADDR2_DDADDR2_MASK) /*! @} */ /*! @name DDADDR3 - Push and Fetch Destination Address */ /*! @{ */ #define neutrons_DDADDR3_DDADDR3_MASK (0xFFFFFFFFU) #define neutrons_DDADDR3_DDADDR3_SHIFT (0U) /*! DDADDR3 - DDADDR3 */ #define neutrons_DDADDR3_DDADDR3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DDADDR3_DDADDR3_SHIFT)) & neutrons_DDADDR3_DDADDR3_MASK) /*! @} */ /*! @name DCTRL2_0 - Push_packed and Fetch Second Control */ /*! @{ */ #define neutrons_DCTRL2_0_SRCLEN_MASK (0x3FFFU) #define neutrons_DCTRL2_0_SRCLEN_SHIFT (0U) /*! SRCLEN - SRCLEN */ #define neutrons_DCTRL2_0_SRCLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_0_SRCLEN_SHIFT)) & neutrons_DCTRL2_0_SRCLEN_MASK) #define neutrons_DCTRL2_0_SBIT_MASK (0x10000U) #define neutrons_DCTRL2_0_SBIT_SHIFT (16U) /*! SBIT - SBIT */ #define neutrons_DCTRL2_0_SBIT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_0_SBIT_SHIFT)) & neutrons_DCTRL2_0_SBIT_MASK) #define neutrons_DCTRL2_0_ITER_MASK (0xFFF00000U) #define neutrons_DCTRL2_0_ITER_SHIFT (20U) /*! ITER - ITER */ #define neutrons_DCTRL2_0_ITER(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_0_ITER_SHIFT)) & neutrons_DCTRL2_0_ITER_MASK) /*! @} */ /*! @name DCTRL2_1 - Push_packed and Fetch Second Control */ /*! @{ */ #define neutrons_DCTRL2_1_SRCLEN1_MASK (0x3FFFU) #define neutrons_DCTRL2_1_SRCLEN1_SHIFT (0U) /*! SRCLEN1 - SRCLEN1 */ #define neutrons_DCTRL2_1_SRCLEN1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_1_SRCLEN1_SHIFT)) & neutrons_DCTRL2_1_SRCLEN1_MASK) #define neutrons_DCTRL2_1_SBIT_MASK (0x10000U) #define neutrons_DCTRL2_1_SBIT_SHIFT (16U) /*! SBIT - SBIT */ #define neutrons_DCTRL2_1_SBIT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_1_SBIT_SHIFT)) & neutrons_DCTRL2_1_SBIT_MASK) #define neutrons_DCTRL2_1_ITER1_MASK (0xFFF00000U) #define neutrons_DCTRL2_1_ITER1_SHIFT (20U) /*! ITER1 - ITER1 */ #define neutrons_DCTRL2_1_ITER1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_1_ITER1_SHIFT)) & neutrons_DCTRL2_1_ITER1_MASK) /*! @} */ /*! @name DCTRL2_2 - Push_packed and Fetch Second Control */ /*! @{ */ #define neutrons_DCTRL2_2_SRCLEN2_MASK (0x3FFFU) #define neutrons_DCTRL2_2_SRCLEN2_SHIFT (0U) /*! SRCLEN2 - SRCLEN2 */ #define neutrons_DCTRL2_2_SRCLEN2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_2_SRCLEN2_SHIFT)) & neutrons_DCTRL2_2_SRCLEN2_MASK) #define neutrons_DCTRL2_2_SBIT_MASK (0x10000U) #define neutrons_DCTRL2_2_SBIT_SHIFT (16U) /*! SBIT - SBIT */ #define neutrons_DCTRL2_2_SBIT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_2_SBIT_SHIFT)) & neutrons_DCTRL2_2_SBIT_MASK) #define neutrons_DCTRL2_2_ITER2_MASK (0xFFF00000U) #define neutrons_DCTRL2_2_ITER2_SHIFT (20U) /*! ITER2 - ITER2 */ #define neutrons_DCTRL2_2_ITER2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_2_ITER2_SHIFT)) & neutrons_DCTRL2_2_ITER2_MASK) /*! @} */ /*! @name DCTRL2_3 - Push_packed and Fetch Second Control */ /*! @{ */ #define neutrons_DCTRL2_3_SRCLEN3_MASK (0x3FFFU) #define neutrons_DCTRL2_3_SRCLEN3_SHIFT (0U) /*! SRCLEN3 - SRCLEN3 */ #define neutrons_DCTRL2_3_SRCLEN3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_3_SRCLEN3_SHIFT)) & neutrons_DCTRL2_3_SRCLEN3_MASK) #define neutrons_DCTRL2_3_SBIT_MASK (0x10000U) #define neutrons_DCTRL2_3_SBIT_SHIFT (16U) /*! SBIT - SBIT */ #define neutrons_DCTRL2_3_SBIT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_3_SBIT_SHIFT)) & neutrons_DCTRL2_3_SBIT_MASK) #define neutrons_DCTRL2_3_ITER3_MASK (0xFFF00000U) #define neutrons_DCTRL2_3_ITER3_SHIFT (20U) /*! ITER3 - ITER3 */ #define neutrons_DCTRL2_3_ITER3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL2_3_ITER3_SHIFT)) & neutrons_DCTRL2_3_ITER3_MASK) /*! @} */ /*! @name WCTRL - Weight Fetch Control */ /*! @{ */ #define neutrons_WCTRL_MODE_MASK (0x3U) #define neutrons_WCTRL_MODE_SHIFT (0U) /*! MODE - Mode * 0b00..Reserved * 0b01..Activate * 0b10..Fetch unpack * 0b11..Clears all pend-ready bits (see WPENDx). */ #define neutrons_WCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL_MODE_SHIFT)) & neutrons_WCTRL_MODE_MASK) #define neutrons_WCTRL_SRCEQDST_MASK (0x4U) #define neutrons_WCTRL_SRCEQDST_SHIFT (2U) /*! SRCEQDST - SRCEQDST */ #define neutrons_WCTRL_SRCEQDST(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL_SRCEQDST_SHIFT)) & neutrons_WCTRL_SRCEQDST_MASK) #define neutrons_WCTRL_PADINSERT_MASK (0x8U) #define neutrons_WCTRL_PADINSERT_SHIFT (3U) /*! PADINSERT - Pad Insert */ #define neutrons_WCTRL_PADINSERT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL_PADINSERT_SHIFT)) & neutrons_WCTRL_PADINSERT_MASK) #define neutrons_WCTRL_LEN_MASK (0xFFFF0U) #define neutrons_WCTRL_LEN_SHIFT (4U) /*! LEN - LEN */ #define neutrons_WCTRL_LEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL_LEN_SHIFT)) & neutrons_WCTRL_LEN_MASK) #define neutrons_WCTRL_PADCNT_MASK (0xF00000U) #define neutrons_WCTRL_PADCNT_SHIFT (20U) /*! PADCNT - Pad Count */ #define neutrons_WCTRL_PADCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL_PADCNT_SHIFT)) & neutrons_WCTRL_PADCNT_MASK) #define neutrons_WCTRL_PADBYTE_MASK (0xFF000000U) #define neutrons_WCTRL_PADBYTE_SHIFT (24U) /*! PADBYTE - Pad Byte */ #define neutrons_WCTRL_PADBYTE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL_PADBYTE_SHIFT)) & neutrons_WCTRL_PADBYTE_MASK) /*! @} */ /*! @name WSADDR - Weight Fetch Source Address */ /*! @{ */ #define neutrons_WSADDR_ADDR_MASK (0xFFFFFFF0U) #define neutrons_WSADDR_ADDR_SHIFT (4U) /*! ADDR - ADDR */ #define neutrons_WSADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WSADDR_ADDR_SHIFT)) & neutrons_WSADDR_ADDR_MASK) /*! @} */ /*! @name WDADDR - Weight Fetch Destination Address */ /*! @{ */ #define neutrons_WDADDR_ADDR_MASK (0xFFFFFFF0U) #define neutrons_WDADDR_ADDR_SHIFT (4U) /*! ADDR - ADDR */ #define neutrons_WDADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WDADDR_ADDR_SHIFT)) & neutrons_WDADDR_ADDR_MASK) /*! @} */ /*! @name DCTRL3_0 - Fetch Unpack Third Control */ /*! @{ */ #define neutrons_DCTRL3_0_SRCSTRIDE_MASK (0xFFFFU) #define neutrons_DCTRL3_0_SRCSTRIDE_SHIFT (0U) /*! SRCSTRIDE - SRCSTRIDE */ #define neutrons_DCTRL3_0_SRCSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_0_SRCSTRIDE_SHIFT)) & neutrons_DCTRL3_0_SRCSTRIDE_MASK) #define neutrons_DCTRL3_0_DSTSTRIDE_MASK (0xFFFF0000U) #define neutrons_DCTRL3_0_DSTSTRIDE_SHIFT (16U) /*! DSTSTRIDE - DSTSTRIDE */ #define neutrons_DCTRL3_0_DSTSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_0_DSTSTRIDE_SHIFT)) & neutrons_DCTRL3_0_DSTSTRIDE_MASK) /*! @} */ /*! @name DCTRL3_1 - Fetch Unpack Third Control */ /*! @{ */ #define neutrons_DCTRL3_1_SRCSTRIDE_MASK (0xFFFFU) #define neutrons_DCTRL3_1_SRCSTRIDE_SHIFT (0U) /*! SRCSTRIDE - SRCSTRIDE */ #define neutrons_DCTRL3_1_SRCSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_1_SRCSTRIDE_SHIFT)) & neutrons_DCTRL3_1_SRCSTRIDE_MASK) #define neutrons_DCTRL3_1_DSTSTRIDE_MASK (0xFFFF0000U) #define neutrons_DCTRL3_1_DSTSTRIDE_SHIFT (16U) /*! DSTSTRIDE - DSTSTRIDE */ #define neutrons_DCTRL3_1_DSTSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_1_DSTSTRIDE_SHIFT)) & neutrons_DCTRL3_1_DSTSTRIDE_MASK) /*! @} */ /*! @name DCTRL3_2 - Push pack Third Control */ /*! @{ */ #define neutrons_DCTRL3_2_SRCSTRIDE_MASK (0xFFFFU) #define neutrons_DCTRL3_2_SRCSTRIDE_SHIFT (0U) /*! SRCSTRIDE - SRCSTRIDE */ #define neutrons_DCTRL3_2_SRCSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_2_SRCSTRIDE_SHIFT)) & neutrons_DCTRL3_2_SRCSTRIDE_MASK) #define neutrons_DCTRL3_2_DSTSTRIDE_MASK (0xFFFF0000U) #define neutrons_DCTRL3_2_DSTSTRIDE_SHIFT (16U) /*! DSTSTRIDE - DSTSTRIDE */ #define neutrons_DCTRL3_2_DSTSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_2_DSTSTRIDE_SHIFT)) & neutrons_DCTRL3_2_DSTSTRIDE_MASK) /*! @} */ /*! @name DCTRL3_3 - Push pack Third Control */ /*! @{ */ #define neutrons_DCTRL3_3_SRCSTRIDE_MASK (0xFFFFU) #define neutrons_DCTRL3_3_SRCSTRIDE_SHIFT (0U) /*! SRCSTRIDE - SRCSTRIDE */ #define neutrons_DCTRL3_3_SRCSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_3_SRCSTRIDE_SHIFT)) & neutrons_DCTRL3_3_SRCSTRIDE_MASK) #define neutrons_DCTRL3_3_DSTSTRIDE_MASK (0xFFFF0000U) #define neutrons_DCTRL3_3_DSTSTRIDE_SHIFT (16U) /*! DSTSTRIDE - DSTSTRIDE */ #define neutrons_DCTRL3_3_DSTSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DCTRL3_3_DSTSTRIDE_SHIFT)) & neutrons_DCTRL3_3_DSTSTRIDE_MASK) /*! @} */ /*! @name WCTRL2_0 - Weight Fetch Second Control */ /*! @{ */ #define neutrons_WCTRL2_0_SRCLEN_MASK (0x3FFFU) #define neutrons_WCTRL2_0_SRCLEN_SHIFT (0U) /*! SRCLEN - SRCLEN */ #define neutrons_WCTRL2_0_SRCLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL2_0_SRCLEN_SHIFT)) & neutrons_WCTRL2_0_SRCLEN_MASK) #define neutrons_WCTRL2_0_SBIT_MASK (0x10000U) #define neutrons_WCTRL2_0_SBIT_SHIFT (16U) /*! SBIT - SBIT */ #define neutrons_WCTRL2_0_SBIT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL2_0_SBIT_SHIFT)) & neutrons_WCTRL2_0_SBIT_MASK) #define neutrons_WCTRL2_0_ITER_MASK (0xFFF00000U) #define neutrons_WCTRL2_0_ITER_SHIFT (20U) /*! ITER - ITER */ #define neutrons_WCTRL2_0_ITER(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL2_0_ITER_SHIFT)) & neutrons_WCTRL2_0_ITER_MASK) /*! @} */ /*! @name WCTRL3_0 - Weight Fetch Unpack Third Control */ /*! @{ */ #define neutrons_WCTRL3_0_SRCSTRIDE_MASK (0xFFFFU) #define neutrons_WCTRL3_0_SRCSTRIDE_SHIFT (0U) /*! SRCSTRIDE - SRCSTRIDE */ #define neutrons_WCTRL3_0_SRCSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL3_0_SRCSTRIDE_SHIFT)) & neutrons_WCTRL3_0_SRCSTRIDE_MASK) #define neutrons_WCTRL3_0_DSTSTRIDE_MASK (0xFFFF0000U) #define neutrons_WCTRL3_0_DSTSTRIDE_SHIFT (16U) /*! DSTSTRIDE - DSTSTRIDE */ #define neutrons_WCTRL3_0_DSTSTRIDE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WCTRL3_0_DSTSTRIDE_SHIFT)) & neutrons_WCTRL3_0_DSTSTRIDE_MASK) /*! @} */ /*! @name WPEND1 - Weight Pend/Ready set */ /*! @{ */ #define neutrons_WPEND1_WPEND1_ZONE0_MASK (0xFFFFU) #define neutrons_WPEND1_WPEND1_ZONE0_SHIFT (0U) /*! WPEND1_ZONE0 - WPEND1_ZONE0 */ #define neutrons_WPEND1_WPEND1_ZONE0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WPEND1_WPEND1_ZONE0_SHIFT)) & neutrons_WPEND1_WPEND1_ZONE0_MASK) #define neutrons_WPEND1_WPEND1_ZONE1_MASK (0xFFFF0000U) #define neutrons_WPEND1_WPEND1_ZONE1_SHIFT (16U) /*! WPEND1_ZONE1 - WPEND1_ZONE0 */ #define neutrons_WPEND1_WPEND1_ZONE1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WPEND1_WPEND1_ZONE1_SHIFT)) & neutrons_WPEND1_WPEND1_ZONE1_MASK) /*! @} */ /*! @name WPEND2 - Weight Pend/Ready set */ /*! @{ */ #define neutrons_WPEND2_WPEND2_ZONE2_MASK (0xFFFFU) #define neutrons_WPEND2_WPEND2_ZONE2_SHIFT (0U) /*! WPEND2_ZONE2 - WPEND1_ZONE0 */ #define neutrons_WPEND2_WPEND2_ZONE2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WPEND2_WPEND2_ZONE2_SHIFT)) & neutrons_WPEND2_WPEND2_ZONE2_MASK) #define neutrons_WPEND2_WPEND2_ZONE3_MASK (0xFFFF0000U) #define neutrons_WPEND2_WPEND2_ZONE3_SHIFT (16U) /*! WPEND2_ZONE3 - WPEND1_ZONE0 */ #define neutrons_WPEND2_WPEND2_ZONE3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_WPEND2_WPEND2_ZONE3_SHIFT)) & neutrons_WPEND2_WPEND2_ZONE3_MASK) /*! @} */ /*! @name APPCTRL_SOC - Application Control */ /*! @{ */ #define neutrons_APPCTRL_SOC_INFCONT_MASK (0x1U) #define neutrons_APPCTRL_SOC_INFCONT_SHIFT (0U) /*! INFCONT - INFCONT */ #define neutrons_APPCTRL_SOC_INFCONT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_INFCONT_SHIFT)) & neutrons_APPCTRL_SOC_INFCONT_MASK) #define neutrons_APPCTRL_SOC_INFHALT_MASK (0x2U) #define neutrons_APPCTRL_SOC_INFHALT_SHIFT (1U) /*! INFHALT - INFHALT */ #define neutrons_APPCTRL_SOC_INFHALT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_INFHALT_SHIFT)) & neutrons_APPCTRL_SOC_INFHALT_MASK) #define neutrons_APPCTRL_SOC_SYS_SHUTDOWN_MASK (0x4U) #define neutrons_APPCTRL_SOC_SYS_SHUTDOWN_SHIFT (2U) /*! SYS_SHUTDOWN - SYS_SHUTDOWN */ #define neutrons_APPCTRL_SOC_SYS_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_SYS_SHUTDOWN_SHIFT)) & neutrons_APPCTRL_SOC_SYS_SHUTDOWN_MASK) #define neutrons_APPCTRL_SOC_IMGPONG_MASK (0x10U) #define neutrons_APPCTRL_SOC_IMGPONG_SHIFT (4U) /*! IMGPONG - IMGPONG */ #define neutrons_APPCTRL_SOC_IMGPONG(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_IMGPONG_SHIFT)) & neutrons_APPCTRL_SOC_IMGPONG_MASK) #define neutrons_APPCTRL_SOC_RESDONE_MASK (0x20U) #define neutrons_APPCTRL_SOC_RESDONE_SHIFT (5U) /*! RESDONE - RESDONE */ #define neutrons_APPCTRL_SOC_RESDONE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_RESDONE_SHIFT)) & neutrons_APPCTRL_SOC_RESDONE_MASK) #define neutrons_APPCTRL_SOC_RINGSTALL_MASK (0x100U) #define neutrons_APPCTRL_SOC_RINGSTALL_SHIFT (8U) /*! RINGSTALL - RINGSTALL */ #define neutrons_APPCTRL_SOC_RINGSTALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_RINGSTALL_SHIFT)) & neutrons_APPCTRL_SOC_RINGSTALL_MASK) #define neutrons_APPCTRL_SOC_INTDONEENA2_MASK (0x200U) #define neutrons_APPCTRL_SOC_INTDONEENA2_SHIFT (9U) /*! INTDONEENA2 - INTDONEENA */ #define neutrons_APPCTRL_SOC_INTDONEENA2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_INTDONEENA2_SHIFT)) & neutrons_APPCTRL_SOC_INTDONEENA2_MASK) #define neutrons_APPCTRL_SOC_INTMBOXENA2_MASK (0x400U) #define neutrons_APPCTRL_SOC_INTMBOXENA2_SHIFT (10U) /*! INTMBOXENA2 - INTMBOXENA */ #define neutrons_APPCTRL_SOC_INTMBOXENA2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_INTMBOXENA2_SHIFT)) & neutrons_APPCTRL_SOC_INTMBOXENA2_MASK) #define neutrons_APPCTRL_SOC_MBZVWR_MASK (0xFF0000U) #define neutrons_APPCTRL_SOC_MBZVWR_SHIFT (16U) /*! MBZVWR - MBZVWR */ #define neutrons_APPCTRL_SOC_MBZVWR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_MBZVWR_SHIFT)) & neutrons_APPCTRL_SOC_MBZVWR_MASK) #define neutrons_APPCTRL_SOC_MBSOCWR_MASK (0xFF000000U) #define neutrons_APPCTRL_SOC_MBSOCWR_SHIFT (24U) /*! MBSOCWR - MBSOCWR */ #define neutrons_APPCTRL_SOC_MBSOCWR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_SOC_MBSOCWR_SHIFT)) & neutrons_APPCTRL_SOC_MBSOCWR_MASK) /*! @} */ /*! @name APPCTRL_ZV - Application Control */ /*! @{ */ #define neutrons_APPCTRL_ZV_INFCONT_MASK (0x1U) #define neutrons_APPCTRL_ZV_INFCONT_SHIFT (0U) /*! INFCONT - INFCONT */ #define neutrons_APPCTRL_ZV_INFCONT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_INFCONT_SHIFT)) & neutrons_APPCTRL_ZV_INFCONT_MASK) #define neutrons_APPCTRL_ZV_INFHALT_MASK (0x2U) #define neutrons_APPCTRL_ZV_INFHALT_SHIFT (1U) /*! INFHALT - INFHALT */ #define neutrons_APPCTRL_ZV_INFHALT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_INFHALT_SHIFT)) & neutrons_APPCTRL_ZV_INFHALT_MASK) #define neutrons_APPCTRL_ZV_SYS_SHUTDOWN_MASK (0x4U) #define neutrons_APPCTRL_ZV_SYS_SHUTDOWN_SHIFT (2U) /*! SYS_SHUTDOWN - SYS_SHUTDOWN */ #define neutrons_APPCTRL_ZV_SYS_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_SYS_SHUTDOWN_SHIFT)) & neutrons_APPCTRL_ZV_SYS_SHUTDOWN_MASK) #define neutrons_APPCTRL_ZV_IMGPONG_MASK (0x10U) #define neutrons_APPCTRL_ZV_IMGPONG_SHIFT (4U) /*! IMGPONG - IMGPONG */ #define neutrons_APPCTRL_ZV_IMGPONG(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_IMGPONG_SHIFT)) & neutrons_APPCTRL_ZV_IMGPONG_MASK) #define neutrons_APPCTRL_ZV_RESDONE_MASK (0x20U) #define neutrons_APPCTRL_ZV_RESDONE_SHIFT (5U) /*! RESDONE - RESDONE */ #define neutrons_APPCTRL_ZV_RESDONE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_RESDONE_SHIFT)) & neutrons_APPCTRL_ZV_RESDONE_MASK) #define neutrons_APPCTRL_ZV_RINGSTALL_MASK (0x100U) #define neutrons_APPCTRL_ZV_RINGSTALL_SHIFT (8U) /*! RINGSTALL - RINGSTALL */ #define neutrons_APPCTRL_ZV_RINGSTALL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_RINGSTALL_SHIFT)) & neutrons_APPCTRL_ZV_RINGSTALL_MASK) #define neutrons_APPCTRL_ZV_INTDONEENA1_MASK (0x200U) #define neutrons_APPCTRL_ZV_INTDONEENA1_SHIFT (9U) /*! INTDONEENA1 - INTDONEENA */ #define neutrons_APPCTRL_ZV_INTDONEENA1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_INTDONEENA1_SHIFT)) & neutrons_APPCTRL_ZV_INTDONEENA1_MASK) #define neutrons_APPCTRL_ZV_INTMBOXENA1_MASK (0x400U) #define neutrons_APPCTRL_ZV_INTMBOXENA1_SHIFT (10U) /*! INTMBOXENA1 - INTMBOXENA */ #define neutrons_APPCTRL_ZV_INTMBOXENA1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_INTMBOXENA1_SHIFT)) & neutrons_APPCTRL_ZV_INTMBOXENA1_MASK) #define neutrons_APPCTRL_ZV_MBZVWR_MASK (0xFF0000U) #define neutrons_APPCTRL_ZV_MBZVWR_SHIFT (16U) /*! MBZVWR - MBZVWR */ #define neutrons_APPCTRL_ZV_MBZVWR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_MBZVWR_SHIFT)) & neutrons_APPCTRL_ZV_MBZVWR_MASK) #define neutrons_APPCTRL_ZV_MBSOCWR_MASK (0xFF000000U) #define neutrons_APPCTRL_ZV_MBSOCWR_SHIFT (24U) /*! MBSOCWR - MBSOCWR */ #define neutrons_APPCTRL_ZV_MBSOCWR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPCTRL_ZV_MBSOCWR_SHIFT)) & neutrons_APPCTRL_ZV_MBSOCWR_MASK) /*! @} */ /*! @name APPSTATUS - Messages to SoC by Zen-V App using W1S */ /*! @{ */ #define neutrons_APPSTATUS_INFDONE_MASK (0x1U) #define neutrons_APPSTATUS_INFDONE_SHIFT (0U) /*! INFDONE - Inference Done */ #define neutrons_APPSTATUS_INFDONE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPSTATUS_INFDONE_SHIFT)) & neutrons_APPSTATUS_INFDONE_MASK) #define neutrons_APPSTATUS_INFHALTED_MASK (0x2U) #define neutrons_APPSTATUS_INFHALTED_SHIFT (1U) /*! INFHALTED - INFHALTED */ #define neutrons_APPSTATUS_INFHALTED(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPSTATUS_INFHALTED_SHIFT)) & neutrons_APPSTATUS_INFHALTED_MASK) #define neutrons_APPSTATUS_INFBUFFHALF_MASK (0x4U) #define neutrons_APPSTATUS_INFBUFFHALF_SHIFT (2U) /*! INFBUFFHALF - INFBUFFHALF */ #define neutrons_APPSTATUS_INFBUFFHALF(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPSTATUS_INFBUFFHALF_SHIFT)) & neutrons_APPSTATUS_INFBUFFHALF_MASK) #define neutrons_APPSTATUS_INFOUTHALF_MASK (0x8U) #define neutrons_APPSTATUS_INFOUTHALF_SHIFT (3U) /*! INFOUTHALF - INFOUTHALF */ #define neutrons_APPSTATUS_INFOUTHALF(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPSTATUS_INFOUTHALF_SHIFT)) & neutrons_APPSTATUS_INFOUTHALF_MASK) #define neutrons_APPSTATUS_MBOX_MASK (0x10U) #define neutrons_APPSTATUS_MBOX_SHIFT (4U) /*! MBOX - Mailbox */ #define neutrons_APPSTATUS_MBOX(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPSTATUS_MBOX_SHIFT)) & neutrons_APPSTATUS_MBOX_MASK) #define neutrons_APPSTATUS_FAULTCAUSE_MASK (0x3F0000U) #define neutrons_APPSTATUS_FAULTCAUSE_SHIFT (16U) /*! FAULTCAUSE - Fault case */ #define neutrons_APPSTATUS_FAULTCAUSE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_APPSTATUS_FAULTCAUSE_SHIFT)) & neutrons_APPSTATUS_FAULTCAUSE_MASK) /*! @} */ /*! @name BASEDDRL - Base physical address in DDR */ /*! @{ */ #define neutrons_BASEDDRL_SPLITPRIV_MASK (0x1U) #define neutrons_BASEDDRL_SPLITPRIV_SHIFT (0U) /*! SPLITPRIV - SPLITPRIV */ #define neutrons_BASEDDRL_SPLITPRIV(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEDDRL_SPLITPRIV_SHIFT)) & neutrons_BASEDDRL_SPLITPRIV_MASK) #define neutrons_BASEDDRL_LIMITMB_MASK (0x1FF00U) #define neutrons_BASEDDRL_LIMITMB_SHIFT (8U) /*! LIMITMB - LIMITMB */ #define neutrons_BASEDDRL_LIMITMB(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEDDRL_LIMITMB_SHIFT)) & neutrons_BASEDDRL_LIMITMB_MASK) #define neutrons_BASEDDRL_BASEDDRL_MASK (0xFFF00000U) #define neutrons_BASEDDRL_BASEDDRL_SHIFT (20U) /*! BASEDDRL - BASEDDRL */ #define neutrons_BASEDDRL_BASEDDRL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEDDRL_BASEDDRL_SHIFT)) & neutrons_BASEDDRL_BASEDDRL_MASK) /*! @} */ /*! @name BASEDDRH - Base physical address in DDR */ /*! @{ */ #define neutrons_BASEDDRH_BASEDDRH_1_MASK (0x1FFFFU) #define neutrons_BASEDDRH_BASEDDRH_1_SHIFT (0U) /*! BASEDDRH_1 - BASEDDRH */ #define neutrons_BASEDDRH_BASEDDRH_1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEDDRH_BASEDDRH_1_SHIFT)) & neutrons_BASEDDRH_BASEDDRH_1_MASK) #define neutrons_BASEDDRH_BASEDDRH_2_MASK (0x20000U) #define neutrons_BASEDDRH_BASEDDRH_2_SHIFT (17U) /*! BASEDDRH_2 - BASEDDRH */ #define neutrons_BASEDDRH_BASEDDRH_2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEDDRH_BASEDDRH_2_SHIFT)) & neutrons_BASEDDRH_BASEDDRH_2_MASK) /*! @} */ /*! @name INPUT - Offset of Input image from DDR Base */ /*! @{ */ #define neutrons_INPUT_INPUT_MASK (0x3FFFFF0U) #define neutrons_INPUT_INPUT_SHIFT (4U) /*! INPUT - INPUT */ #define neutrons_INPUT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INPUT_INPUT_SHIFT)) & neutrons_INPUT_INPUT_MASK) #define neutrons_INPUT_INOUT_MASK (0x80000000U) #define neutrons_INPUT_INOUT_SHIFT (31U) /*! INOUT - INOUT */ #define neutrons_INPUT_INOUT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INPUT_INOUT_SHIFT)) & neutrons_INPUT_INOUT_MASK) /*! @} */ /*! @name INPUT2 - Offset of Input image from DDR Base */ /*! @{ */ #define neutrons_INPUT2_INPUT2_MASK (0x3FFFFF0U) #define neutrons_INPUT2_INPUT2_SHIFT (4U) /*! INPUT2 - INPUT2 */ #define neutrons_INPUT2_INPUT2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INPUT2_INPUT2_SHIFT)) & neutrons_INPUT2_INPUT2_MASK) #define neutrons_INPUT2_INOUT_MASK (0x80000000U) #define neutrons_INPUT2_INOUT_SHIFT (31U) /*! INOUT - INOUT */ #define neutrons_INPUT2_INOUT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INPUT2_INOUT_SHIFT)) & neutrons_INPUT2_INOUT_MASK) /*! @} */ /*! @name OUTPUT - Offset of Output results from DDR Base */ /*! @{ */ #define neutrons_OUTPUT_OUTPUT_MASK (0x3FFFFF0U) #define neutrons_OUTPUT_OUTPUT_SHIFT (4U) /*! OUTPUT - OUTPUT */ #define neutrons_OUTPUT_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_OUTPUT_OUTPUT_SHIFT)) & neutrons_OUTPUT_OUTPUT_MASK) #define neutrons_OUTPUT_INOUT_MASK (0x80000000U) #define neutrons_OUTPUT_INOUT_SHIFT (31U) /*! INOUT - INOUT */ #define neutrons_OUTPUT_INOUT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_OUTPUT_INOUT_SHIFT)) & neutrons_OUTPUT_INOUT_MASK) /*! @} */ /*! @name OUTPUT2 - Offset of Output results from DDR Base */ /*! @{ */ #define neutrons_OUTPUT2_OUTPUT2_MASK (0x3FFFFF0U) #define neutrons_OUTPUT2_OUTPUT2_SHIFT (4U) /*! OUTPUT2 - OUTPUT2 */ #define neutrons_OUTPUT2_OUTPUT2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_OUTPUT2_OUTPUT2_SHIFT)) & neutrons_OUTPUT2_OUTPUT2_MASK) #define neutrons_OUTPUT2_INOUT_MASK (0x80000000U) #define neutrons_OUTPUT2_INOUT_SHIFT (31U) /*! INOUT - INOUT */ #define neutrons_OUTPUT2_INOUT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_OUTPUT2_INOUT_SHIFT)) & neutrons_OUTPUT2_INOUT_MASK) /*! @} */ /*! @name CODEOFF - Offset of Zen-V code from BASEDDRn */ /*! @{ */ #define neutrons_CODEOFF_CODEOFF_MASK (0x7FFFFF0U) #define neutrons_CODEOFF_CODEOFF_SHIFT (4U) /*! CODEOFF - CODEOFF */ #define neutrons_CODEOFF_CODEOFF(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CODEOFF_CODEOFF_SHIFT)) & neutrons_CODEOFF_CODEOFF_MASK) /*! @} */ /*! @name DATAOFF - Offset of Zen-V data from BASEDDRn */ /*! @{ */ #define neutrons_DATAOFF_DATAOFF_MASK (0x7FFFFF0U) #define neutrons_DATAOFF_DATAOFF_SHIFT (4U) /*! DATAOFF - DATAOFF */ #define neutrons_DATAOFF_DATAOFF(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DATAOFF_DATAOFF_SHIFT)) & neutrons_DATAOFF_DATAOFF_MASK) /*! @} */ /*! @name RINGCTRL - Ring buffer control by Zen-V */ /*! @{ */ #define neutrons_RINGCTRL_RINGSZ_MASK (0xFFU) #define neutrons_RINGCTRL_RINGSZ_SHIFT (0U) /*! RINGSZ - RINGSZ */ #define neutrons_RINGCTRL_RINGSZ(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RINGCTRL_RINGSZ_SHIFT)) & neutrons_RINGCTRL_RINGSZ_MASK) #define neutrons_RINGCTRL_RINGADDR_MASK (0x3F00U) #define neutrons_RINGCTRL_RINGADDR_SHIFT (8U) /*! RINGADDR - RINGADDR */ #define neutrons_RINGCTRL_RINGADDR(x) (((uint32_t)(((uint32_t)(x)) << neutrons_RINGCTRL_RINGADDR_SHIFT)) & neutrons_RINGCTRL_RINGADDR_MASK) /*! @} */ /*! @name TAIL - Tail of ring buffer written by Zen-V */ /*! @{ */ #define neutrons_TAIL_TAIL_MASK (0xFFFFU) #define neutrons_TAIL_TAIL_SHIFT (0U) /*! TAIL - TAIL */ #define neutrons_TAIL_TAIL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_TAIL_TAIL_SHIFT)) & neutrons_TAIL_TAIL_MASK) /*! @} */ /*! @name HEAD - Head of ring buffer written by SoC */ /*! @{ */ #define neutrons_HEAD_HEAD_MASK (0xFFFFU) #define neutrons_HEAD_HEAD_SHIFT (0U) /*! HEAD - HEAD */ #define neutrons_HEAD_HEAD(x) (((uint32_t)(((uint32_t)(x)) << neutrons_HEAD_HEAD_SHIFT)) & neutrons_HEAD_HEAD_MASK) /*! @} */ /*! @name MBOX - Mailboxes For SoC/Zen-V Communications */ /*! @{ */ #define neutrons_MBOX_MBOX_MASK (0xFFFFFFFFU) #define neutrons_MBOX_MBOX_SHIFT (0U) /*! MBOX - Mailbox */ #define neutrons_MBOX_MBOX(x) (((uint32_t)(((uint32_t)(x)) << neutrons_MBOX_MBOX_SHIFT)) & neutrons_MBOX_MBOX_MASK) /*! @} */ /* The count of neutrons_MBOX */ #define neutrons_MBOX_COUNT (8U) /*! @name BASEINOUTL - Base physical address for Input/Output fetch/push */ /*! @{ */ #define neutrons_BASEINOUTL_LIMITMB_MASK (0x1FF00U) #define neutrons_BASEINOUTL_LIMITMB_SHIFT (8U) /*! LIMITMB - LIMITMB */ #define neutrons_BASEINOUTL_LIMITMB(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEINOUTL_LIMITMB_SHIFT)) & neutrons_BASEINOUTL_LIMITMB_MASK) #define neutrons_BASEINOUTL_BASEINOUTL_MASK (0xFFF00000U) #define neutrons_BASEINOUTL_BASEINOUTL_SHIFT (20U) /*! BASEINOUTL - BASESPILLL */ #define neutrons_BASEINOUTL_BASEINOUTL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEINOUTL_BASEINOUTL_SHIFT)) & neutrons_BASEINOUTL_BASEINOUTL_MASK) /*! @} */ /*! @name BASEINOUTH - Base physical address for Spill fetch/push */ /*! @{ */ #define neutrons_BASEINOUTH_BASEINOUTH_1_MASK (0x1FFFFU) #define neutrons_BASEINOUTH_BASEINOUTH_1_SHIFT (0U) /*! BASEINOUTH_1 - BASEINOUTH */ #define neutrons_BASEINOUTH_BASEINOUTH_1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEINOUTH_BASEINOUTH_1_SHIFT)) & neutrons_BASEINOUTH_BASEINOUTH_1_MASK) #define neutrons_BASEINOUTH_BASEINOUTH_2_MASK (0x20000U) #define neutrons_BASEINOUTH_BASEINOUTH_2_SHIFT (17U) /*! BASEINOUTH_2 - BASEINOUTH */ #define neutrons_BASEINOUTH_BASEINOUTH_2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASEINOUTH_BASEINOUTH_2_SHIFT)) & neutrons_BASEINOUTH_BASEINOUTH_2_MASK) /*! @} */ /*! @name BASESPILLL - Base physical address for Spill fetch/push */ /*! @{ */ #define neutrons_BASESPILLL_SPLITPRIV_MASK (0x1U) #define neutrons_BASESPILLL_SPLITPRIV_SHIFT (0U) /*! SPLITPRIV - SPLITPRIV */ #define neutrons_BASESPILLL_SPLITPRIV(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASESPILLL_SPLITPRIV_SHIFT)) & neutrons_BASESPILLL_SPLITPRIV_MASK) #define neutrons_BASESPILLL_LIMITMB_MASK (0x1FF00U) #define neutrons_BASESPILLL_LIMITMB_SHIFT (8U) /*! LIMITMB - LIMITMB */ #define neutrons_BASESPILLL_LIMITMB(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASESPILLL_LIMITMB_SHIFT)) & neutrons_BASESPILLL_LIMITMB_MASK) #define neutrons_BASESPILLL_BASESPILLL_MASK (0xFFF00000U) #define neutrons_BASESPILLL_BASESPILLL_SHIFT (20U) /*! BASESPILLL - BASESPILLL */ #define neutrons_BASESPILLL_BASESPILLL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASESPILLL_BASESPILLL_SHIFT)) & neutrons_BASESPILLL_BASESPILLL_MASK) /*! @} */ /*! @name BASESPILLH - Base physical address for Spill fetch/push */ /*! @{ */ #define neutrons_BASESPILLH_BASESPILLH_MASK (0x1FFFFU) #define neutrons_BASESPILLH_BASESPILLH_SHIFT (0U) /*! BASESPILLH - BASESPILLH */ #define neutrons_BASESPILLH_BASESPILLH(x) (((uint32_t)(((uint32_t)(x)) << neutrons_BASESPILLH_BASESPILLH_SHIFT)) & neutrons_BASESPILLH_BASESPILLH_MASK) /*! @} */ /*! @name DECOMPCTRL - Control For Weight Decompressor */ /*! @{ */ #define neutrons_DECOMPCTRL_ENABLE_MASK (0x1U) #define neutrons_DECOMPCTRL_ENABLE_SHIFT (0U) /*! ENABLE - Enable */ #define neutrons_DECOMPCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPCTRL_ENABLE_SHIFT)) & neutrons_DECOMPCTRL_ENABLE_MASK) #define neutrons_DECOMPCTRL_BYPASS_MASK (0x2U) #define neutrons_DECOMPCTRL_BYPASS_SHIFT (1U) /*! BYPASS - Bypass */ #define neutrons_DECOMPCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPCTRL_BYPASS_SHIFT)) & neutrons_DECOMPCTRL_BYPASS_MASK) #define neutrons_DECOMPCTRL_NEW_META_MASK (0x30U) #define neutrons_DECOMPCTRL_NEW_META_SHIFT (4U) /*! NEW_META - NEW_META */ #define neutrons_DECOMPCTRL_NEW_META(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPCTRL_NEW_META_SHIFT)) & neutrons_DECOMPCTRL_NEW_META_MASK) #define neutrons_DECOMPCTRL_NEW_GROUP_MASK (0x100U) #define neutrons_DECOMPCTRL_NEW_GROUP_SHIFT (8U) /*! NEW_GROUP - NEW_GROUP */ #define neutrons_DECOMPCTRL_NEW_GROUP(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPCTRL_NEW_GROUP_SHIFT)) & neutrons_DECOMPCTRL_NEW_GROUP_MASK) #define neutrons_DECOMPCTRL_SKIP_LEN_MASK (0xFFF00000U) #define neutrons_DECOMPCTRL_SKIP_LEN_SHIFT (20U) /*! SKIP_LEN - Skip Length */ #define neutrons_DECOMPCTRL_SKIP_LEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPCTRL_SKIP_LEN_SHIFT)) & neutrons_DECOMPCTRL_SKIP_LEN_MASK) /*! @} */ /*! @name DECOMPSTAT - state for Weight Decompressor */ /*! @{ */ #define neutrons_DECOMPSTAT_DONE_MASK (0x1U) #define neutrons_DECOMPSTAT_DONE_SHIFT (0U) /*! DONE - DONE */ #define neutrons_DECOMPSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPSTAT_DONE_SHIFT)) & neutrons_DECOMPSTAT_DONE_MASK) #define neutrons_DECOMPSTAT_ACTIVE_MASK (0x2U) #define neutrons_DECOMPSTAT_ACTIVE_SHIFT (1U) /*! ACTIVE - ACTIVE */ #define neutrons_DECOMPSTAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPSTAT_ACTIVE_SHIFT)) & neutrons_DECOMPSTAT_ACTIVE_MASK) #define neutrons_DECOMPSTAT_ERR_DECOMP_MASK (0x4U) #define neutrons_DECOMPSTAT_ERR_DECOMP_SHIFT (2U) /*! ERR_DECOMP - ERR_DECOMP */ #define neutrons_DECOMPSTAT_ERR_DECOMP(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPSTAT_ERR_DECOMP_SHIFT)) & neutrons_DECOMPSTAT_ERR_DECOMP_MASK) #define neutrons_DECOMPSTAT_ERR_BUS_MASK (0x8U) #define neutrons_DECOMPSTAT_ERR_BUS_SHIFT (3U) /*! ERR_BUS - ERR_BUS */ #define neutrons_DECOMPSTAT_ERR_BUS(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPSTAT_ERR_BUS_SHIFT)) & neutrons_DECOMPSTAT_ERR_BUS_MASK) #define neutrons_DECOMPSTAT_ERR_OVER_MASK (0x10U) #define neutrons_DECOMPSTAT_ERR_OVER_SHIFT (4U) /*! ERR_OVER - ERR_OVER */ #define neutrons_DECOMPSTAT_ERR_OVER(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPSTAT_ERR_OVER_SHIFT)) & neutrons_DECOMPSTAT_ERR_OVER_MASK) #define neutrons_DECOMPSTAT_ERR_UNDER_MASK (0x20U) #define neutrons_DECOMPSTAT_ERR_UNDER_SHIFT (5U) /*! ERR_UNDER - ERR_UNDER */ #define neutrons_DECOMPSTAT_ERR_UNDER(x) (((uint32_t)(((uint32_t)(x)) << neutrons_DECOMPSTAT_ERR_UNDER_SHIFT)) & neutrons_DECOMPSTAT_ERR_UNDER_MASK) /*! @} */ /*! @name GROUP_BASE - DDR offset from base for Weight Decompressor */ /*! @{ */ #define neutrons_GROUP_BASE_OFFSET_MASK (0x7FFFFFF0U) #define neutrons_GROUP_BASE_OFFSET_SHIFT (4U) /*! OFFSET - OFFSET */ #define neutrons_GROUP_BASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << neutrons_GROUP_BASE_OFFSET_SHIFT)) & neutrons_GROUP_BASE_OFFSET_MASK) /*! @} */ /*! @name GROUP_LEN - Length in bytes of current Decompressor Group in External memory */ /*! @{ */ #define neutrons_GROUP_LEN_LEN_MASK (0x3FFF0U) #define neutrons_GROUP_LEN_LEN_SHIFT (4U) /*! LEN - LEN */ #define neutrons_GROUP_LEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_GROUP_LEN_LEN_SHIFT)) & neutrons_GROUP_LEN_LEN_MASK) /*! @} */ /*! @name CRYPTO - Control for Cryptographic protection of models by SoC security */ /*! @{ */ #define neutrons_CRYPTO_CRYPTOLOCK_MASK (0x1U) #define neutrons_CRYPTO_CRYPTOLOCK_SHIFT (0U) /*! CRYPTOLOCK - CRYPTOLOCK */ #define neutrons_CRYPTO_CRYPTOLOCK(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CRYPTO_CRYPTOLOCK_SHIFT)) & neutrons_CRYPTO_CRYPTOLOCK_MASK) #define neutrons_CRYPTO_DBGLOCK_MASK (0x2U) #define neutrons_CRYPTO_DBGLOCK_SHIFT (1U) /*! DBGLOCK - DBGLOCK */ #define neutrons_CRYPTO_DBGLOCK(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CRYPTO_DBGLOCK_SHIFT)) & neutrons_CRYPTO_DBGLOCK_MASK) #define neutrons_CRYPTO_PCLOCK_MASK (0x4U) #define neutrons_CRYPTO_PCLOCK_SHIFT (2U) /*! PCLOCK - PCLOCK */ #define neutrons_CRYPTO_PCLOCK(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CRYPTO_PCLOCK_SHIFT)) & neutrons_CRYPTO_PCLOCK_MASK) #define neutrons_CRYPTO_CRYPTOMODEL_MASK (0x100U) #define neutrons_CRYPTO_CRYPTOMODEL_SHIFT (8U) /*! CRYPTOMODEL - CRYPTOMODEL */ #define neutrons_CRYPTO_CRYPTOMODEL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CRYPTO_CRYPTOMODEL_SHIFT)) & neutrons_CRYPTO_CRYPTOMODEL_MASK) #define neutrons_CRYPTO_ZERORAM_MASK (0x200U) #define neutrons_CRYPTO_ZERORAM_SHIFT (9U) /*! ZERORAM - ZERORAM */ #define neutrons_CRYPTO_ZERORAM(x) (((uint32_t)(((uint32_t)(x)) << neutrons_CRYPTO_ZERORAM_SHIFT)) & neutrons_CRYPTO_ZERORAM_MASK) /*! @} */ /*! @name PRIVDDRL - Physical address in DDR of model when secure */ /*! @{ */ #define neutrons_PRIVDDRL_SPLITPRIV_MASK (0x1U) #define neutrons_PRIVDDRL_SPLITPRIV_SHIFT (0U) /*! SPLITPRIV - SPLITPRIV */ #define neutrons_PRIVDDRL_SPLITPRIV(x) (((uint32_t)(((uint32_t)(x)) << neutrons_PRIVDDRL_SPLITPRIV_SHIFT)) & neutrons_PRIVDDRL_SPLITPRIV_MASK) #define neutrons_PRIVDDRL_LIMITMB_MASK (0x1FF00U) #define neutrons_PRIVDDRL_LIMITMB_SHIFT (8U) /*! LIMITMB - LIMITMB */ #define neutrons_PRIVDDRL_LIMITMB(x) (((uint32_t)(((uint32_t)(x)) << neutrons_PRIVDDRL_LIMITMB_SHIFT)) & neutrons_PRIVDDRL_LIMITMB_MASK) #define neutrons_PRIVDDRL_PRIVDDRL_MASK (0xFFF00000U) #define neutrons_PRIVDDRL_PRIVDDRL_SHIFT (20U) /*! PRIVDDRL - PRIVDDRL */ #define neutrons_PRIVDDRL_PRIVDDRL(x) (((uint32_t)(((uint32_t)(x)) << neutrons_PRIVDDRL_PRIVDDRL_SHIFT)) & neutrons_PRIVDDRL_PRIVDDRL_MASK) /*! @} */ /*! @name PRIVDDRH - Physical address in DDR of model when secure */ /*! @{ */ #define neutrons_PRIVDDRH_BASEDDRH1_MASK (0x1FFFFU) #define neutrons_PRIVDDRH_BASEDDRH1_SHIFT (0U) /*! BASEDDRH1 - BASEDDRH */ #define neutrons_PRIVDDRH_BASEDDRH1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_PRIVDDRH_BASEDDRH1_SHIFT)) & neutrons_PRIVDDRH_BASEDDRH1_MASK) #define neutrons_PRIVDDRH_BASEDDRH2_MASK (0x20000U) #define neutrons_PRIVDDRH_BASEDDRH2_SHIFT (17U) /*! BASEDDRH2 - BASEDDRH */ #define neutrons_PRIVDDRH_BASEDDRH2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_PRIVDDRH_BASEDDRH2_SHIFT)) & neutrons_PRIVDDRH_BASEDDRH2_MASK) /*! @} */ /*! @name SESSIONIV - Unique IV for Protected models */ /*! @{ */ #define neutrons_SESSIONIV_NONCE_MASK (0xFFFFFFFFU) #define neutrons_SESSIONIV_NONCE_SHIFT (0U) /*! NONCE - NONCE */ #define neutrons_SESSIONIV_NONCE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_SESSIONIV_NONCE_SHIFT)) & neutrons_SESSIONIV_NONCE_MASK) /*! @} */ /*! @name INFCOUNT - Infocount */ /*! @{ */ #define neutrons_INFCOUNT_COUNT_MASK (0xFFFFFFFFU) #define neutrons_INFCOUNT_COUNT_SHIFT (0U) /*! COUNT - COUNT */ #define neutrons_INFCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_INFCOUNT_COUNT_SHIFT)) & neutrons_INFCOUNT_COUNT_MASK) /*! @} */ /*! @name FLAYERNUM - Layer number for Fetch */ /*! @{ */ #define neutrons_FLAYERNUM_NUM_MASK (0xFFFFU) #define neutrons_FLAYERNUM_NUM_SHIFT (0U) /*! NUM - NUM */ #define neutrons_FLAYERNUM_NUM(x) (((uint32_t)(((uint32_t)(x)) << neutrons_FLAYERNUM_NUM_SHIFT)) & neutrons_FLAYERNUM_NUM_MASK) /*! @} */ /*! @name PLAYERNUM - Layer number for Push */ /*! @{ */ #define neutrons_PLAYERNUM_NUM_MASK (0xFFFFU) #define neutrons_PLAYERNUM_NUM_SHIFT (0U) /*! NUM - NUM */ #define neutrons_PLAYERNUM_NUM(x) (((uint32_t)(((uint32_t)(x)) << neutrons_PLAYERNUM_NUM_SHIFT)) & neutrons_PLAYERNUM_NUM_MASK) /*! @} */ /*! @name AXIOPT - Boot SoC setting for AXI optimization */ /*! @{ */ #define neutrons_AXIOPT_ARLEN_MASK (0xFFU) #define neutrons_AXIOPT_ARLEN_SHIFT (0U) /*! ARLEN - ARLEN */ #define neutrons_AXIOPT_ARLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_AXIOPT_ARLEN_SHIFT)) & neutrons_AXIOPT_ARLEN_MASK) #define neutrons_AXIOPT_AWLEN_MASK (0xFF00U) #define neutrons_AXIOPT_AWLEN_SHIFT (8U) /*! AWLEN - AWLEN */ #define neutrons_AXIOPT_AWLEN(x) (((uint32_t)(((uint32_t)(x)) << neutrons_AXIOPT_AWLEN_SHIFT)) & neutrons_AXIOPT_AWLEN_MASK) #define neutrons_AXIOPT_ARTRIG_MASK (0xFF0000U) #define neutrons_AXIOPT_ARTRIG_SHIFT (16U) /*! ARTRIG - ARTRIG */ #define neutrons_AXIOPT_ARTRIG(x) (((uint32_t)(((uint32_t)(x)) << neutrons_AXIOPT_ARTRIG_SHIFT)) & neutrons_AXIOPT_ARTRIG_MASK) #define neutrons_AXIOPT_USEOT_MASK (0x1000000U) #define neutrons_AXIOPT_USEOT_SHIFT (24U) /*! USEOT - Use Out Standing */ #define neutrons_AXIOPT_USEOT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_AXIOPT_USEOT_SHIFT)) & neutrons_AXIOPT_USEOT_MASK) #define neutrons_AXIOPT_RRDCNT_MASK (0xF0000000U) #define neutrons_AXIOPT_RRDCNT_SHIFT (28U) /*! RRDCNT - ARTRIG */ #define neutrons_AXIOPT_RRDCNT(x) (((uint32_t)(((uint32_t)(x)) << neutrons_AXIOPT_RRDCNT_SHIFT)) & neutrons_AXIOPT_RRDCNT_MASK) /*! @} */ /*! @name V2P_DATA - Virtual to Physical registers */ /*! @{ */ #define neutrons_V2P_DATA_D_VMAP0_MASK (0x3FU) #define neutrons_V2P_DATA_D_VMAP0_SHIFT (0U) /*! D_VMAP0 - VMAP0 */ #define neutrons_V2P_DATA_D_VMAP0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_VMAP0_SHIFT)) & neutrons_V2P_DATA_D_VMAP0_MASK) #define neutrons_V2P_DATA_D_WRUPD0_MASK (0x80U) #define neutrons_V2P_DATA_D_WRUPD0_SHIFT (7U) /*! D_WRUPD0 - WRUPD0 */ #define neutrons_V2P_DATA_D_WRUPD0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_WRUPD0_SHIFT)) & neutrons_V2P_DATA_D_WRUPD0_MASK) #define neutrons_V2P_DATA_D_VMAP1_MASK (0x3F00U) #define neutrons_V2P_DATA_D_VMAP1_SHIFT (8U) /*! D_VMAP1 - VMAP1 */ #define neutrons_V2P_DATA_D_VMAP1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_VMAP1_SHIFT)) & neutrons_V2P_DATA_D_VMAP1_MASK) #define neutrons_V2P_DATA_D_WRUPD1_MASK (0x8000U) #define neutrons_V2P_DATA_D_WRUPD1_SHIFT (15U) /*! D_WRUPD1 - WRUPD1 */ #define neutrons_V2P_DATA_D_WRUPD1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_WRUPD1_SHIFT)) & neutrons_V2P_DATA_D_WRUPD1_MASK) #define neutrons_V2P_DATA_D_VMAP2_MASK (0x3F0000U) #define neutrons_V2P_DATA_D_VMAP2_SHIFT (16U) /*! D_VMAP2 - VMAP2 */ #define neutrons_V2P_DATA_D_VMAP2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_VMAP2_SHIFT)) & neutrons_V2P_DATA_D_VMAP2_MASK) #define neutrons_V2P_DATA_D_WRUP2_MASK (0x800000U) #define neutrons_V2P_DATA_D_WRUP2_SHIFT (23U) /*! D_WRUP2 - WRUP2 */ #define neutrons_V2P_DATA_D_WRUP2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_WRUP2_SHIFT)) & neutrons_V2P_DATA_D_WRUP2_MASK) #define neutrons_V2P_DATA_D_VMAP3_MASK (0x3F000000U) #define neutrons_V2P_DATA_D_VMAP3_SHIFT (24U) /*! D_VMAP3 - VMAP3 */ #define neutrons_V2P_DATA_D_VMAP3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_VMAP3_SHIFT)) & neutrons_V2P_DATA_D_VMAP3_MASK) #define neutrons_V2P_DATA_D_WRUPD3_MASK (0x80000000U) #define neutrons_V2P_DATA_D_WRUPD3_SHIFT (31U) /*! D_WRUPD3 - WRUPD3 */ #define neutrons_V2P_DATA_D_WRUPD3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_DATA_D_WRUPD3_SHIFT)) & neutrons_V2P_DATA_D_WRUPD3_MASK) /*! @} */ /* The count of neutrons_V2P_DATA */ #define neutrons_V2P_DATA_COUNT (16U) /*! @name V2P_WEIGHTS - Virtual to Physical registers */ /*! @{ */ #define neutrons_V2P_WEIGHTS_W_VMAP0_MASK (0x3FU) #define neutrons_V2P_WEIGHTS_W_VMAP0_SHIFT (0U) /*! W_VMAP0 - VMAP0 */ #define neutrons_V2P_WEIGHTS_W_VMAP0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_VMAP0_SHIFT)) & neutrons_V2P_WEIGHTS_W_VMAP0_MASK) #define neutrons_V2P_WEIGHTS_W_WRUPD0_MASK (0x80U) #define neutrons_V2P_WEIGHTS_W_WRUPD0_SHIFT (7U) /*! W_WRUPD0 - WRUPD0 */ #define neutrons_V2P_WEIGHTS_W_WRUPD0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_WRUPD0_SHIFT)) & neutrons_V2P_WEIGHTS_W_WRUPD0_MASK) #define neutrons_V2P_WEIGHTS_W_VMAP1_MASK (0x3F00U) #define neutrons_V2P_WEIGHTS_W_VMAP1_SHIFT (8U) /*! W_VMAP1 - VMAP1 */ #define neutrons_V2P_WEIGHTS_W_VMAP1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_VMAP1_SHIFT)) & neutrons_V2P_WEIGHTS_W_VMAP1_MASK) #define neutrons_V2P_WEIGHTS_W_WRUPD1_MASK (0x8000U) #define neutrons_V2P_WEIGHTS_W_WRUPD1_SHIFT (15U) /*! W_WRUPD1 - WRUPD1 */ #define neutrons_V2P_WEIGHTS_W_WRUPD1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_WRUPD1_SHIFT)) & neutrons_V2P_WEIGHTS_W_WRUPD1_MASK) #define neutrons_V2P_WEIGHTS_W_VMAP2_MASK (0x3F0000U) #define neutrons_V2P_WEIGHTS_W_VMAP2_SHIFT (16U) /*! W_VMAP2 - VMAP2 */ #define neutrons_V2P_WEIGHTS_W_VMAP2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_VMAP2_SHIFT)) & neutrons_V2P_WEIGHTS_W_VMAP2_MASK) #define neutrons_V2P_WEIGHTS_W_WRUP2_MASK (0x800000U) #define neutrons_V2P_WEIGHTS_W_WRUP2_SHIFT (23U) /*! W_WRUP2 - WRUP2 */ #define neutrons_V2P_WEIGHTS_W_WRUP2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_WRUP2_SHIFT)) & neutrons_V2P_WEIGHTS_W_WRUP2_MASK) #define neutrons_V2P_WEIGHTS_W_VMAP3_MASK (0x3F000000U) #define neutrons_V2P_WEIGHTS_W_VMAP3_SHIFT (24U) /*! W_VMAP3 - VMAP3 */ #define neutrons_V2P_WEIGHTS_W_VMAP3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_VMAP3_SHIFT)) & neutrons_V2P_WEIGHTS_W_VMAP3_MASK) #define neutrons_V2P_WEIGHTS_W_WRUPD3_MASK (0x80000000U) #define neutrons_V2P_WEIGHTS_W_WRUPD3_SHIFT (31U) /*! W_WRUPD3 - WRUPD3 */ #define neutrons_V2P_WEIGHTS_W_WRUPD3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_WEIGHTS_W_WRUPD3_SHIFT)) & neutrons_V2P_WEIGHTS_W_WRUPD3_MASK) /*! @} */ /* The count of neutrons_V2P_WEIGHTS */ #define neutrons_V2P_WEIGHTS_COUNT (16U) /*! @name V2P_RESULTS - Virtual to Physical registers */ /*! @{ */ #define neutrons_V2P_RESULTS_R_VMAP0_MASK (0x3FU) #define neutrons_V2P_RESULTS_R_VMAP0_SHIFT (0U) /*! R_VMAP0 - VMAP0 */ #define neutrons_V2P_RESULTS_R_VMAP0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_VMAP0_SHIFT)) & neutrons_V2P_RESULTS_R_VMAP0_MASK) #define neutrons_V2P_RESULTS_R_WRUPD0_MASK (0x80U) #define neutrons_V2P_RESULTS_R_WRUPD0_SHIFT (7U) /*! R_WRUPD0 - WRUPD0 */ #define neutrons_V2P_RESULTS_R_WRUPD0(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_WRUPD0_SHIFT)) & neutrons_V2P_RESULTS_R_WRUPD0_MASK) #define neutrons_V2P_RESULTS_R_VMAP1_MASK (0x3F00U) #define neutrons_V2P_RESULTS_R_VMAP1_SHIFT (8U) /*! R_VMAP1 - VMAP1 */ #define neutrons_V2P_RESULTS_R_VMAP1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_VMAP1_SHIFT)) & neutrons_V2P_RESULTS_R_VMAP1_MASK) #define neutrons_V2P_RESULTS_R_WRUPD1_MASK (0x8000U) #define neutrons_V2P_RESULTS_R_WRUPD1_SHIFT (15U) /*! R_WRUPD1 - WRUPD1 */ #define neutrons_V2P_RESULTS_R_WRUPD1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_WRUPD1_SHIFT)) & neutrons_V2P_RESULTS_R_WRUPD1_MASK) #define neutrons_V2P_RESULTS_R_VMAP2_MASK (0x3F0000U) #define neutrons_V2P_RESULTS_R_VMAP2_SHIFT (16U) /*! R_VMAP2 - VMAP2 */ #define neutrons_V2P_RESULTS_R_VMAP2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_VMAP2_SHIFT)) & neutrons_V2P_RESULTS_R_VMAP2_MASK) #define neutrons_V2P_RESULTS_R_WRUP2_MASK (0x800000U) #define neutrons_V2P_RESULTS_R_WRUP2_SHIFT (23U) /*! R_WRUP2 - WRUP2 */ #define neutrons_V2P_RESULTS_R_WRUP2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_WRUP2_SHIFT)) & neutrons_V2P_RESULTS_R_WRUP2_MASK) #define neutrons_V2P_RESULTS_R_VMAP3_MASK (0x3F000000U) #define neutrons_V2P_RESULTS_R_VMAP3_SHIFT (24U) /*! R_VMAP3 - VMAP3 */ #define neutrons_V2P_RESULTS_R_VMAP3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_VMAP3_SHIFT)) & neutrons_V2P_RESULTS_R_VMAP3_MASK) #define neutrons_V2P_RESULTS_R_WRUPD3_MASK (0x80000000U) #define neutrons_V2P_RESULTS_R_WRUPD3_SHIFT (31U) /*! R_WRUPD3 - WRUPD3 */ #define neutrons_V2P_RESULTS_R_WRUPD3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_V2P_RESULTS_R_WRUPD3_SHIFT)) & neutrons_V2P_RESULTS_R_WRUPD3_MASK) /*! @} */ /* The count of neutrons_V2P_RESULTS */ #define neutrons_V2P_RESULTS_COUNT (16U) /*! @name LISTEN - Listener Mode Enable */ /*! @{ */ #define neutrons_LISTEN_MODE_MASK (0x3U) #define neutrons_LISTEN_MODE_SHIFT (0U) /*! MODE - Mode * 0b00..None. No listener mode * 0b01..Data listening * 0b10..Weight listening * *.. */ #define neutrons_LISTEN_MODE(x) (((uint32_t)(((uint32_t)(x)) << neutrons_LISTEN_MODE_SHIFT)) & neutrons_LISTEN_MODE_MASK) #define neutrons_LISTEN_LISTENER1_MASK (0x20U) #define neutrons_LISTEN_LISTENER1_SHIFT (5U) /*! LISTENER1 - Listener 1 * 0b0..Disable * 0b1..Enable */ #define neutrons_LISTEN_LISTENER1(x) (((uint32_t)(((uint32_t)(x)) << neutrons_LISTEN_LISTENER1_SHIFT)) & neutrons_LISTEN_LISTENER1_MASK) #define neutrons_LISTEN_LISTENER2_MASK (0x40U) #define neutrons_LISTEN_LISTENER2_SHIFT (6U) /*! LISTENER2 - Listener 2 * 0b0..Disable * 0b1..Enable */ #define neutrons_LISTEN_LISTENER2(x) (((uint32_t)(((uint32_t)(x)) << neutrons_LISTEN_LISTENER2_SHIFT)) & neutrons_LISTEN_LISTENER2_MASK) #define neutrons_LISTEN_LISTENER3_MASK (0x80U) #define neutrons_LISTEN_LISTENER3_SHIFT (7U) /*! LISTENER3 - Listener 3 * 0b0..Disable * 0b1..Enable */ #define neutrons_LISTEN_LISTENER3(x) (((uint32_t)(((uint32_t)(x)) << neutrons_LISTEN_LISTENER3_SHIFT)) & neutrons_LISTEN_LISTENER3_MASK) /*! @} */ /*! * @} */ /* end of group neutrons_Register_Masks */ /* neutrons - Peripheral instance base addresses */ /** Peripheral NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC base address */ #define NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC_BASE (0x4AB00000u) /** Peripheral NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC base pointer */ #define NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC ((neutrons_Type *)NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC_BASE) /** Peripheral NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV base address */ #define NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV_BASE (0x4AB80000u) /** Peripheral NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV base pointer */ #define NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV ((neutrons_Type *)NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV_BASE) /** Array initializer of neutrons peripheral base addresses */ #define neutrons_BASE_ADDRS { NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC_BASE, NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV_BASE } /** Array initializer of neutrons peripheral base pointers */ #define neutrons_BASE_PTRS { NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC, NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV } /*! * @} */ /* end of group neutrons_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #else #pragma pop #endif #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). ---------------------------------------------------------------------------- */ /*! * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). * @{ */ #if defined(__ARMCC_VERSION) #if (__ARMCC_VERSION >= 6010050) #pragma clang system_header #endif #elif defined(__IAR_SYSTEMS_ICC__) #pragma system_include #endif /** * @brief Mask and left-shift a bit field value for use in a register bit range. * @param field Name of the register bit field. * @param value Value of the bit field. * @return Masked and shifted value. */ #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) /** * @brief Mask and right-shift a register value to extract a bit field value. * @param field Name of the register bit field. * @param value Value of the register. * @return Masked and shifted bit field value. */ #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) /*! * @} */ /* end of group Bit_Field_Generic_Macros */ /* ---------------------------------------------------------------------------- -- SDK Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup SDK_Compatibility_Symbols SDK Compatibility * @{ */ /* No SDK compatibility issues. */ /*! * @} */ /* end of group SDK_Compatibility_Symbols */ #endif /* MIMX9596_CA55_H_ */